REVISIONSLTR

DESCRIPTIONDATEAPPROVEDA

Delete figure 5 and all VS = +3 V tests under
Table I. - ro

14-04-03

C. SAFFLE

B

Update JEDEC package from MO-178-AA to
MO-178. Add 3 footnotes to ESD section underparagraph 1.3. Add supply voltage limits toparagraph 1.4. Add JEDEC references toparagraph 2. Add sentence to footnote -2/ as
specified under Table I.
Update the “L” dimension maximum limit as
specified under Figure 1. Add terminal
descriptions to Figure 2. - ro

20-02-05

J. ESCHMEYER

II[!l

Prepared in accordance with ASME Y14.24.

Vendor item drawing

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PMIC N/A

PREPARED BY
RICK OFFICER

Original date of drawing
YY-MM-DD

CHECKED BYRAJESH PITHADIA

14-02-25

APPROVED BY
CHARLES F. SAFFLE
SIZE

A
REV

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
https://www.dla.mil/LandandMaritime
TITLE
MICROCIRCUIT, LINEAR, LOW POWER, SINGLE
SUPPLY, WIDEBAND OPERATIONAL AMPLIFIER,
MONOLITHIC SILICON

CODE IDENT. NO.

DWG NO.

V62/14610

16236
B

PAGE

1

OF

17

DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
AMSC N/A

5962-V128-19

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance low power, single supply wideband
operational amplifier microcircuit, with an operating temperature range of -40C to +105C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/14610

-

01

X

I

Drawing
numberE

I

Device type
(See 1.2.1)

I

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic

01

OPA830-EP

Circuit function
Low power, single supply wideband
operational amplifier

1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

Package styleX5

MO-178

Plastic small outline

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
F
Z

DLA LAND AND MARITIMECOLUMBUS, OHIO

Material
Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy (BGA/CGA)
Other

SIZE
A

CODE IDENT NO.
16236
REV

B

DWG NO.

V62/14610
PAGE2

1.3 Absolute maximum ratings.

1/

Power supply ............................................................................................................................ 12 V dc
Differential input voltage ........................................................................................................... 2.5 V
Internal power dissipation (PD) ................................................................................................ 73 mW
Input voltage range (single supply) .......................................................................................... -0.5 V to +VS + 0.3 V
Storage temperature range ...................................................................................................... -65C to +125C
Junction temperature range (TJ) .............................................................................................. +150C
Lead temperature (soldering, 10 seconds) ............................................................................... +300C
Electrostatic discharge (ESD): 2/
Human body model (HBM) ................................................................................................... 2,000 V 3/
Charge device model (CDM) ................................................................................................ 1,500 V 4/
Machine model (MM) ........................................................................................................... 200 V
1.4 Recommended operating conditions. 5/
Dual supply voltage ................................................................................................................... 5 V nominal,
5.5 V maximum
Single supply voltage ................................................................................................................ 5 V nominal,
11 V maximum
Operating junction temperature range (TJ) .............................................................................. -40C to +105C
1.5 Thermal characteristics.
Thermal metric

1/

2/
3/
4/
5/

SymbolCase X

Unit

Thermal resistance, junction-to-ambient

JA

218.8

C/W

Thermal resistance, junction-to-case (top)JC(TOP)

87.0

C/W

Thermal resistance, junction-to-board

JB

45.2

C/W

Characterization parameter, junction-to-top

JT

4.4

C/W

Characterization parameter, junction-to-board

JB

44.4

C/W

Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic
discharges in to the device.
Level listed above is the passing level per JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe
manufacturing with a standard ESD control process.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250 V HBM
allows safe manufacturing with a standard ESD control process.
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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2. APPLICABLE DOCUMENTSJEDEC Solid State Technology Association
JEDEC JS-001
JESD22-C101––

JEDEC PUB 95
JEDEC JEP 155
JEDEC JEP 157–––

Human Body Model Testing of Integrated Circuits
Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-WithstandThresholds of Microelectronics Components
Registered and Standard Outlines for Semiconductor Devices
Recommended ESD Target Levels for HBM/MM Qualification
Recommended ESD-CDM Target Levels(Copies of these documents are available online at https://www.jedec.org.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Test circuits. The test circuits shall be as shown in figures 3 and 4.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
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TABLE I. Electrical performance characteristics. 1/
Test

SymbolConditions -2/
VS = 5 V

Temperature,TA

Devicetype

LimitsMin

AC performance.
Small signal bandwidth

SSBW

G = +1, VO  0.2 VPP+25C

G = +2, VO  0.2 VPP-40C to +85C

01

6

SR

01

-40C to +85CtR

VO  0.2 VPP

+25C

01

G = +2, 2 V step

-40C to +85C01

0.5 V steptF

01

-40C to +85C

0.5 V steptS

01

-40C to +85C

G = +2, 1 V stepVO = 2 VPP, f = 5 MHz

2 nd harmonic

RL = 150 

01-40C to +85C

I

V/s

260

I 5.9

ns

I 6

ns

I 66

ns

42 typical

01-40C to +85C

I -56

dBc

-67 typical

+25C

I -60

-40C to +85C

RL  500 dB

3.5 typical+25C
Harmonic distortion.

6 typical

3.3 typical+25C
Settling time to 0.1%MHzI

600 typical+25C
Fall time

80

110 typical+25C
Rise timeI

11 typical+25C

Peaking at a gain of +1

I

25 typical-40C to +85CG  +10

I

15

+25C
GBWP

MHz

120 typical+25C
G = +10, VO  0.2 VPP

310 typical
65-40C to +85C

G = +5, VO  0.2 VPP

Slew rate

I Max

See figure 3.

+25C

Gain bandwidth
product

Unit-71 typical+25C
See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
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B

DWG NO.

V62/14610
PAGE

5

Test

TABLE I. Electrical performance characteristics – Continued.1/
SymbolConditions 2/
VS = 5 V-

Temperature,TA

Devicetype

LimitsMin

RL = 150 

3 rd harmonic

VO = 2 VPP, f = 5 MHz

Harmonic distortion – continued.

See figure 3.

AC performance – continued.

-40C to +85Cf  1 MHz

Input voltage noise-40C to +85C

-48

01

11.5
9.5 typical+25C-40C to +85C

Unit
Max

01

dBc

-60 typical

+25C

-59

-40C to +85C

RL  500 -77 typical+25Cf  1 MHz

Input current noise

NTSC differential gain
NTSC differentialphase
DC performance.

01

5.7

0.17 typical+25C0.07 typical+25C

3.7 typical

+25C

nV /

_t
Hz

pA /

_t
Hz

%


RL = 150 3/

-

IIB

Input bias current
drift

IIB

Input bias current

VIO

Average offset voltage
drift

VIO

Input offset voltage

AVOL

Open loop voltage gain

-40C to +105C

01

64

dB

74 typical+25C-40C to +105C

8.6

01

mV

1.5 typical+25C

VCM = 0 V

01

-40C to +105C

01

+25C

A

+13

V /
C

35

+5 typical

+25C
+25C

12

01

nA /
C

See footnotes at end of table.

SIZEA

DLA LAND AND MARITIMECOLUMBUS, OHIOCODE IDENT NO.
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B

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6

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolTemperature,TA

Conditions 2/
VS = 5 V

Devicetype

LimitsMin

DC performance - continued.

RL = 150  3/

Input offset current

VCM = 0 V

IIO

-40C to +105C

Max

1.49

01

A

0.1 typical+25C
Input offset current
drift

Unit

IIO

+25C

01

5

nA /
C

-VIN

-40C to +105C

01

-5.1

V

Input.
Negative input
voltage4/-5.5 typical+25C
Positive input
voltage

4/-40C to +105C

+VIN

01

2.8
3.2 typical+25C
Common mode
rejection ratio

CMRR

Input - referred-40C to +105C

V

01

72

dB

80 typical+25C

Input impedance.
Differential mode

5/

+25C

01

10||2.1 typicalk||pF+25C

01400||1.2 typicalk||pF-40C to +105C

01

4.84

Common mode 5/
Output.
Output voltage swing

G = +2, RL = 1 k to GND

4.88 typical+25C
G = +2, RL = 150  to GND

4.56-40C to +105C

4.64 typical+25C
Current output,
sinking and sourcing
Short circuit current-40C to +105C

01

55

Closed loop output
impedancemA

85 typical

+25C
IOS

V

Output shorted to ground

+25C

01

150 typicalmA

G = +2, f  100 kHz

+25C

01

0.06 typical

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
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B

DWG NO.

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PAGE

7

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolTemperature,TA

Conditions 2/
VS = 5 V

Devicetype

Limits
Min

Unit
Max

Power supply.
Minimum operating
voltage+25C01

1.4 typicalV

Maximum operating
voltage-40C to +105C

01

5.5

V

-40C to +105C

01

5.9

mA

Maximum quiescentcurrent

VS = 5 V

4.25 typical+25C
Minimum quiescentcurrent

VS = 5 V-40C to +105C

01

3.19
4.25 typical+25CPower supply
rejection ratio+PSRR

Input referred-40C to +105C

mA

01

59

dB

66 typical+25C

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

B

DWG NO.

V62/14610
PAGE

8

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions -6/
VS = +5 V

Temperature,TA

Devicetype

LimitsMin

AC performance.
Small signal bandwidth

SSBW

G = +1, VO  0.2 VPP+25C

G = +2, VO  0.2 VPP-40C to +85C

01

15

6

-40C to +85CG  +10SR

01-40C to +85CtR

VO  0.2 VPP

+25C

01

G = +2, 2 V step

-40C to +85C01

0.5 V steptF

01

-40C to +85C

0.5 V steptS

01

-40C to +85C

G = +2, 1 V stepVO = 2 VPP, f = 5 MHz

2 nd harmonic

RL = 150 

01-40C to +85C

dB

I

V/s

260

I 5.9

ns

I 5.9

ns

I 67

ns

43 typical

01-40C to +85C

I -53

dBc

-62 typical

+25C

I -56

-40C to +85C

RL  500 

5 typical

3.3 typical+25C
Harmonic distortion.

MHzI

3.3 typical+25C
Settling time to 0.1%79

550 typical+25C
Fall timeI

110 typical+25C
Rise timeI

11 typical+25C

Peaking at a gain of +1

I

24 typical

+25C
GBWP

MHz

110 typical+25C
G = +10, VO  0.2 VPP

250 typical
68-40C to +85C

G = +5, VO  0.2 VPP

Slew rate

I Max

See figure 4.

+25C

Gain bandwidth
product

Unit-64 typical+25C
See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
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9

Test

SymbolTABLE I. Electrical performance characteristics – Continued.1/
Conditions 6/
VS = +5 V-

Temperature,TA

Devicetype

LimitsMin

RL = 150 

3 rd harmonic

VO = 2 VPP, f = 5 MHz

Harmonic distortion – continued.

See figure 4.

AC performance – continued.

f  1 MHz

Input voltage noise

Unit
Max

01

-40C to +85C

-48

dBc

-58 typical

+25C

-60

-40C to +85C

RL  500 -84 typical+25Cf  1 MHz

Input current noise

01-40C to +85C

11.2
9.2 typical

+25C
01

-40C to +85C

NTSC differential gain
NTSC differentialphase
DC performance.

5.5

0.09 typical+25C0.08 typical+25C

3.5 typical

+25C

nV /

_f
Hz

pA /

_f
Hz

%


RL = 150 3/

-

IIB

Input bias current
drift

IIB

Input bias current

VIO

Average offset voltage
drift

VIO

Input offset voltage

AVOL

Open loop voltage gain

01

-40C to +105C

64

dB

72 typical

+25C

6.7

01

-40C to +105CmV

0.5 typical+25C

VCM = 2.5 V

01-40C to +105C

01

+25C

A

+13

V /
C

28

+5 typical

+25C

12

01

+25C

nA /
C

See footnotes at end of table.

SIZEA

DLA LAND AND MARITIMECOLUMBUS, OHIOCODE IDENT NO.
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V62/14610

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10

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolTemperature,TA

Conditions 6/
VS = +5 V

Devicetype

LimitsMin

DC performance - continued.

RL = 150  3/

Input offset current

VCM = 2.5 V

IIO-40C to +105C

Max

1.41

01

A

0.1 typical+25C
Input offset current
drift

Unit

IIO

+25C

01

5

nA /
C

+VIN

-40C to +105C

01

-0.2

V

Input.
Least positive input 4/
voltage-0.5 typical+25C
Most positive input 4/
voltage-40C to +105C

+VIN

01

2.75
3.2 typical+25C
Common mode
rejection ratio

CMRR

Input - referred-40C to +105C

V

01

72

dB

80 typical+25C

Input impedance.
Differential mode

5/

+25C

01

10||2.1 typicalk||pF+25C

01400||1.2 typicalk||pF-40C to +105C

01

0.13

Common mode 5/
Output.
Least positive
output voltage

G = +5, RL = 1 k to 2.5 V

0.09 typical+25C
G = +5, RL = 150  to GND

0.26-40C to +105C

0.21 typical+25C
Most positive
output voltage

G = +5, RL = 1 k to 2.5 V-40C to +105C

01

4.87

V

4.91 typical+25C
G = +5, RL = 150  to GND

V

4.72

-40C to +105C

4.78 typical+25C
See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
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11

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolTemperature,TA

Conditions 6/
VS = +5 V

Devicetype

Limits
Min

Unit
Max

Output – continued.
Current output,
sinking and sourcing-40C to +105C

01

52

mA

80 typical+25C
Output shorted to either supply

+25C

01

140 typicalmA

G = +2, f  100 kHz

+25C

01

0.06 typical

Minimum operating
voltage+25C01+2.8 typicalV

Maximum operating
voltage-40C to +105C

01

+11

V

-40C to +105C

01

5.5

mA

Short circuit output
current

IOS

Closed loop output
impedance
Power supply.

Maximum quiescentcurrent

VS = +5 V

3.9 typical+25C
Minimum quiescentcurrent

VS = +5 V-40C to +105C

01

3.05
3.9 typical+25CPower supply
rejection ratio+PSRR

Input referred-40C to +105C

mA

01

59

dB

66 typical

+25C

1/

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance overthe specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.

2/

Unless otherwise specified, at -40C  TJ  +105C, G = +2, RF = 750 , and RL = 150  to GND.
For production testing of these parameters to the limits in table I herein, Ambient temperature (TA) = Junction temperature (TJ).

3/

Current is considered positive out of pin.

4/

Tested  3 dB below minimum specified CMRR at  CMIR limits.

5/

The || symbolizes that the input impedance is being represented as the resistance value is in parallel with the capacitance.

6/

Unless otherwise specified, at -40C  TJ  +105C, G = +2, RF = 750 , and RL = 150  to VS / 2.

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Case X

7~
b

5 PLS

l-$-1 0.20 @ 1

5

4~

1

E E1

:-----T7----.--.-----...:::...3 I

_j_

GAGE
PLANE

I

~
D_

______.

DETAIL A

L;-tiiituJr----~_l_0

SEATING
PLANE

FIGURE 1. Case outline.

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Case X – continued.

Dimensions
SymbolInchMillimeters

Min

Max

Min

Max

A

---

.057

---

1.45

A1

.000

.006

0.00

0.15

b

.011

.019

0.30

0.50

c

.003

.008

0.08

0.22

D

.108

.120

2.75

3.05

E

.057

.068

1.45

1.75

E1

.102

.118

2.60

3.00

e
L

.037 BSC.011

0.95 BSC
.023

0.30

0.60

L1

.009 BSC

0.25 BSCn

5 leads

5 leads

NOTES:
1.

Controlling dimensions are millimeter, inch dimensions are given for reference only.

2.

Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions or gate burrs shall not
exceed 0.15 mm (0.006 inch) per end.

3.

Falls within reference to JEDEC MO-178.

FIGURE 1. Case outline - Continued.

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Device type

01

Case outline

X

Terminal number

Terminal
symbolI/O

1

OUTPUTO

Amplifier output.

2

-VS

I

Negative amplifier power supply input.

3+INPUTI

Non-inverting amplifier input.

4-INPUT

I

Inverting amplifier input.

5

+VS

I

Positive amplifier power supply input.

Description

FIGURE 2. Terminal connections.

+5 V

50 fl. SOURCE

Vo

150 fl.

RF
750.fl.

RG
750.fl.

]!-6.8 µFI

0.1 µF-5 V

FIGURE 3. DC coupled, G = +2, bipolar supply test circuit.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

B

DWG NO.

V62/14610
PAGE

15

Vs =+5 V

6.8 µF+Q

1.50 k fl

0. 1 µF

,~ Q
VouT

RL
150 fl
RG
750fl.

RF
750fl.

FIGURE 4. AC coupled, G = +2, +5 V single supply test circuit.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

B

DWG NO.

V62/14610
PAGE

16

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

Vendor item drawing
administrative control
number 1/ 2/

Devicemanufacturer
CAGE code

Transportation
mode andquantity

Top sidemarking

Vendor part number

V62/14610-01XE

01295

Tape and reel,
3000

SLM

OPA830TDBVREP

1/ The vendor item drawing establishes an administrative control number for identifying the item on theengineering documentation.
2/ For the most current package and ordering information, see the package option addendum at theend of the manufacturer’s data sheet.
CAGE code

Source of supply

01295

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

B

DWG NO.

V62/14610
PAGE

17