REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVED

Prepared in accordance with ASME Y14.24

Vendor Item Drawing

Revision Status of Sheets
REV
SHEET
REV
SHEET

1

2

PMIC N/A
Original date ofdrawing
YY-MM-DD
22-06-01

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4

5

7

8

9

10

11

PREPARED BY
RICK OFFICER

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13

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20

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

CHECKED BYRAJESH PITHADIAAPPROVED BY
JAMES R. ESCHMEYER
SIZECAGE CODEA
REVAMSC N/A

6

16236

TITLE

https://www.dla.mil/landandmaritime

MICROCIRCUIT, LINEAR, 2 MHz CURRENT MODEPWM CONTROLLERS, MONOLITHIC SILICONDWG NO.

PAGE

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

V62/22607
1 OF 205962-V045-22

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance 2 MHz current mode pulse width modulator(PWM) microcircuit, with an operating temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/22607-

Drawing
number01

X

E

Device type
(See 1.2.1)

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic

Circuit function

01
02
03
04

TPS7H5005-SEP
TPS7H5006-SEP
TPS7H5007-SEP
TPS7H5008-SEP

2 MHz current mode pulse width modulator
2 MHz current mode pulse width modulator
2 MHz current mode pulse width modulator
2 MHz current mode pulse width modulator

1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

X

24

MO-153

Package styleThin scale small outline package (TSSOP)

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

Material

A
B
C
D
E
F
Z

DLA LAND AND MARITIMECOLUMBUS, OHIO

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy (BGA/CGA)
Other

SIZE
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PAGE 2

1.3 Absolute maximum ratings.

1/

Input:
VIN ......................................................................................................................... -0.3 V to 16 V
RT, VSENSE, SS, RSC, COMP, PS, SP, HICC, LEB ............................................ -0.3 V to 3.3 V
SYNC ..................................................................................................................... -0.3 V to 7.5 V
EN, FAULT ............................................................................................................. -0.3 V to 7.5 V
DCL, CS_ILIM ........................................................................................................ -0.3 V to 7.5 V
Output:
OUTA, OUTB, SRA and SRB ................................................................................. -0.3 V to 7.5 V
VLDO ..................................................................................................................... -0.3 V to 7.5 V
REFCAP ................................................................................................................ -0.3 V to 3.3 V
Junction temperature range (TJ) ................................................................................ -55°C to +150°C
Storage temperature range (TSTG) ............................................................................ -65°C to +150°C
Electrostatic discharge (ESD) rating:
Human body model (HDM), per JEDEC JS-001, all pins ....................................... ±1000 V 2/
Charge device model (CDM), per JEDEC JS-002, all pins .................................... ±250 V 3/
1.4 Recommended operating conditions. 4/
Supply voltage range (VIN) ........................................................................................ 4 V to 14 V
Input voltage slew rate (SRVIN) .................................................................................. 0.03 V/µs maximum
Junction temperature range (TJ) ................................................................................ -55°C to +125°C
1.5 Thermal characteristics.
Thermal metric

SymbolCase X

Unit

Thermal resistance, junction-to-ambient

θJA

74.5

°C/W

Thermal resistance, junction-to-board

θJB

30.8

°C/W

Thermal resistance, junction-to-case (top)θJC(TOP)

17.9

°C/W

Characterization parameter, junction-to-top

ψJT

0.8

°C/W

Characterization parameter, junction-to-board

ψJB

30.3

°C/W

________
1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2/ JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
3/ JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
4/

Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.

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PAGE 3

1.6 Radiation features.
Maximum total dose available (dose rate = 50 - 300 rad(Si)/s) ................................................ 50 krads(Si) 5/
Heavy ion single event phenomenon (SEP):No Single event latchup (SEL) occurs at effective LET (see 4.3) ......................................... ≤ 43 MeV/(mg/cm2)

6/

No Single event burn out (SEB) occurs at effective LET (see 4.3) ....................................... ≤ 43 MeV/(mg/cm )6/

2

No Single event gate rupture (SEGR) occurs at effective LET (see 4.3) .............................. ≤ 43 MeV/(mg/cm2)6/

2. APPLICABLE DOCUMENTS
ASTM INTERNATIONAL (ASTM)
ASTM F1192–

Standard Guide for the Measurement of Single Event Phenomena (SEP) from Heavy Ion Irradiationof semiconductor Devices.

(Copies of these documents are available online at https://www.astm.org.)
DEPARTMENT OF DEFENSE STANDARDSMIL-STD-883–

Test Method Standard Microcircuits.

(Copies of these documents are available online at https://quicksearch.dla.mil.)
JEDEC Solid State Technology Association
JEDEC JS-001
JEDEC JS-002
JEDEC PUB 95
JEDEC JEP 155
JEDEC JEP 157

–
−
–
–
–

Human Body Model Testing of Integrated Circuits
Electrostatic Discharge Sensitivity Testing - Charge Device Model (CDM)
Registered and Standard Outlines for Semiconductor Devices
Recommended ESD Target Levels for HBM/MM Qualification
Recommended ESD-CDM Target Levels(Copies of these documents are available online at https://www.jedec.org.)______
5/ Device types 01-04 supplied to this drawing have been total ionizing dose (TID) characterized in accordance with
MIL-STD-883 method 1019 at dose rate condition A to TID level of 50 krads(Si). Post irradiation electrical parametric limits falls
within the specification limits during electrical measurement. The radiation end point limits for the noted parameters areguaranteed only for the conditions as specified in MIL-STD-883, method 1019, condition A to a maximum total dose of
50 krads(Si).
6/For more information on SEP test results, customers are requested to contact the manufacturer (see SEP table IB).

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PAGE 4

3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table IA herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Outputs timing waveforms. The outputs timing waveforms shall be as shown in figure 3.
3.5.4 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revisionlevel control and shall be made available to the preparing and acquiring activity upon request.

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PAGE 5TABLE IA. Electrical performance characteristics. 1/ 2/
Test

SymbolConditions
VIN = 4 V to 14 V,
unless otherwise specified

Temperature,
TJ

Devicetype-55°C to +125°C

Limits

Unit

Min

Max

01,02,
03,04
01,02,

4

14

V

8

mA

03,04

6.25 typical

SUPPLY VOLTAGES AN D CURREN TS
Operating input voltage

VIN

Operating supply current

IDD

fSW = 500 kHz, no load for OUTA,OUTB, SRA, and SRB-55°C to +125°C

9.5

fSW = 1 MHz, no load for OUTA,OUTB, SRA, and SRB

6.75 typicalfSW = 2 MHz, no load for OUTA,OUTB, SRA, and SRB

8.5 typical

13.5
9.5

fSW = 500 kHz, CL = 100 pF,
for OUTA, OUTB, SRA, and SRB

7.5 typical12

fSW = 1 MHz, CL = 100 pF,
for OUTA, OUTB, SRA, and SRB

9 typical
19.5

fSW = 2 MHz, CL = 100 pF,
for OUTA, OUTB, SRA, and SRB
Standby current
Internal linear regulator

IDD(dis)-55°C to +125°C

VLDO

5 V ≤ VIN ≤ 14 V, fSW ≤ 1 MHz-55°C to +125°C

5 V ≤ VIN ≤ 14 V, fSW = 2 MHz-55°C to +125°C

output voltage
Internal linear regulator

14 typicalEN = 0 V

VLDO

output voltage

01,02,
03,04
01,02,

4.75

03,04
01,02,

3

mA

5.2

V

5 typical
4.65

03,04

5.2

V

5 typical

ENABLE AND UNDERVO LTAGE LOC KOUT
EN threshold rising
EN threshold falling
EN hysteresis voltage
EN pin input leakage
current
VLDO UVLO rising
VLDO UVLO falling
VLDO UVLO hysteresis

VENR-55°C to +125°C

VENF-55°C to +125°C

VENH-55°C to +125°C

IEN

01,02,
03,04

VIN = 14 V, EN = 5 V-55°C to +125°C

01,02,-55°C to +125°C

VLDOUVLOF-55°C to +125°C

VLDOUVLOH-55°C to +125°C

0.65

0.47

0.55

0.5 typical

01,02,

85

03,04

95 typical

105

01,02,

50

DLA LAND AND MARITIMECOLUMBUS, OHIO

V
mV
nA

5 typical

01,02,

3.44

3.66

03,04

3.55 typical

01,02,

3.29

3.51

03,04

3.4 typical

01,02,

115

03,04

135 typical160

See footnotes at end of table.

SIZE
A

V

0.6 typical

03,04

03,04

VLDOUVLOR

0.57

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TABLE IA. Electrical performance characteristics – Continued. 1/ 2/
Test

SymbolConditions
VIN = 4 V to 14 V,

Temperature,
TJ

Devicetype

unless otherwise specified

Limits

Unit

Min

Max

1.98

3.32

SOFT STARTSoft start current

ISS

SS = 0.3 V-55°C to +125°C

01,02,
03,04µA

2.7 typical

ERROR AMPLIFIER
Transconductance

EAgm–2 µA < ICOMP < 2 µA,-55°C to +125°C

V(COMP) = 1 V

01,02,

1150

2500

03,04

1800 typical
10000 typicalµA/V

DC gain

EADC

VSENSE = 0.6 V-55°C to +125°C

01,02,
03,04

V/V

Error amplifier source
current

EAISRC

V(COMP) = 1 V,
100-mV input overdrive-55°C to +125°C

01,02,
03,04

100

190

µA

Error amplifier sinkcurrent

EAISNK

V(COMP) = 1 V,
100-mV input overdrive-55°C to +125°C

01,02,
03,04

100

190

µA

Error amplifier output
resistance

EAro-55°C to +125°C

01,02,
03,04

Error amplifier input
offset voltage

EAOS-55°C to +125°C

01,02,
03,04

Error amplifier input
bias current

EAIB-55°C to +125°C

01,02,
03,04

Bandwidth

EABW-55°C to +125°C

01,02,
03,04-55°C to +125°C

01,02,

0.8

03,04

0.8

7 typical

MΩ

2

mV

35

nA

-2

10 typicalMHz

OSCILLATORSYNC in low level

SYNCIL

VIN < 5 V
VIN ≥ 5 V

SYNC in high level

SYNCIH

VIN < 5 V

01,02,

3.5

03,04

3.5

-55°C to +125°C

01,02,
03,04

200

4000

kHz

-55°C to +125°C

01,02,
03,04

40

60

%

-55°C to +125°C

01,02,

15ns-55°C to +125°C

VIN ≥ 5 V
SYNC in frequency range FSYNC
SYNC in duty cycle

DSYNC

Duty cycle of external clock

SYNC out low-to-high

SYNCRT CL = 25 pF

rise time (10%/ 90%)

03,04

V

6 typical

See footnotes at end of table.

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PAGE 7

TABLE IA. Electrical performance characteristics – Continued. 1/ 2/
Test

SymbolConditions
VIN = 4 V to 14 V,

Temperature,
TJ

Devicetype

unless otherwise specified

Limits
Min

Unit
Max

OSCILLATOR – continued.
SYNC out high to low-55°C to +125°C

SYNCFT CL = 25 pF

fall time (10%/ 90%)01,02,

17

03,04

ns

6 typical

SYNC out low level

SYNCOL IOL = 10 mA-55°C to +125°C

01,02,
03,04

500

mV

SYNC out high level 3/

VLDO – IOH = 10 mA
SYNCOH-55°C to +125°C

01,02,
03,04

0.5

V

Externally set frequency
detection time

EXTDT

-55°C to +125°C

01,02,
03,04

20

µs

Externally set frequency

FSWEXT RT = 1.07 MΩ-55°C to +125°C

01,02,

95

115

kHz

03,04

105 typical

RT = Open, f = 200 kHz

190

RT = 511 kΩ

230

210 typical900

RT = 90.0 kΩ

11001000 typical1700

RT = 34.8 kΩ

23002000 typical
VOLTAGE REFERENCEInternal voltage reference VREF

Measured at COMP

+25°C

initial tolerance
Internal voltage reference

Measured at COMP

Measured at COMPREFCAP voltage

REFCAP REFCAP = 470 nF-55°C+125°C-55°C to +125°C

01,02,

0.609

0.615

03,04

0.613 typical

01,02,

0.607

03,04

0.609 typical

01,02,

0.611

03,04

0.614 typical

01,02,

1.213

03,04

1.225 typical

0.612

0.617

1.237

See footnotes at end of table.

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PAGE 8V

TABLE IA. Electrical performance characteristics – Continued. 1/ 2/
Test

SymbolConditions
VIN = 4 V to 14 V,

Temperature,
TJ

Devicetype

unless otherwise specified

Limits

Unit

Min

Max

01,02,

2.00

2.12

03,04

2.06 typical

CURRENT SENSE, CUR RENT LIMIT AND HICCUPCOMP to CS_LIM ratio

Current limit

CCSR-55°C to +125°C-55°C to +125°C

VCS_ILIM(overcurrent) thresholdHiccup delay current

IHICC_DEL CS_ILIM = 1.3 V, COMP = 3 V,
VSENSE = REFCAP/2 V,
CHICC = 3 nF, LEB = 49.9 kΩ,

01,02,

1.09

V

03,04

1.05 typical-55°C to +125°C

01,02,
03,04

80 typicalµA

fSW = 100 kHz
Hiccup restart current

IHICC_RST-55°C to +125°C

01,02,
03,04

1 typicalµA

Hiccup pull up threshold

VHICC_PU-55°C to +125°C

01,02,
03,04

1.0 typicalV

Hiccup shut down
threshold

VHICC_SD-55°C to +125°C

01,02,
03,04

0.6 typicalV

Hiccup restart threshold VHICC_RST-55°C to +125°C

01,02,
03,04

0.3 typicalV-55°C to +125°C

01,02,
03,04

0.033 typical

V/µs

SLOPE COMPENSATION
Slope compensation

fSW = 100 kHz, RSC = 1.18 MΩ
fSW = 200 kHz, RSC = 562 kΩ

0.066 typicalfSW = 1000 kHz, RSC = 100 kΩ

0.333 typicalfSW = 2000 kHz, RSC = 49.9 kΩ

0.666 typical

FAULT
FLT threshold rising

VFLTR-55°C to +125°C

01,02,
03,04

FLT threshold falling

FLT hysteresis voltage

VFLTF-55°C to +125°C

VFLTH

FLT minimum pulse width TFLT

-55°C to +125°C-55°C to +125°C

VFLT = 1 V

01,02,

0.57

0.65

0.6 typical
0.47

0.55

03,04

0.5 typical

01,02,

90

03,04

100 typical

01,02,
03,04

0.4

110

1.4

See footnotes at end of table.

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PAGE 9VmVµs

TABLE IA. Electrical performance characteristics – Continued. 1/ 2/
Test

SymbolConditions
VIN = 4 V to 14 V,

Temperature,
TJ

Devicetype

unless otherwise specified

Limits

Unit

Min

Max

01,02,

140

169

03,04

152 typical

FAULT – continued.
FLT delay duration

tDFLT-55°C to +125°C

fSW = 100 kHz

66

fSW = 200 kHzµs

86

78 typical14

fSW = 1 MHz

21

17 typical7

fSW = 2 MHz

14

11 typical
THERMAL SHUTDOWN
Thermal shutdown-55°C to +125°C

Thermal shutdown-55°C to +125°C

hysteresis

01,02,

165

185

03,04

175 typical

01,02,

10

03,04

15 typical

20

°C

°C

PRIMARY AND SYNCHR ONOUS R ECTIFIER OUTPUTS
Low level thresholdvoltage

ISINK = 10 mA-55°C to +125°C

01,02,
03,04

0.5 typical

V

High level thresholdvoltage

ISOURCE = 10 mA-55°C to +125°C

01,02,
03,04

4.5 typicalV

Rise and fall timeRLOAD = 50 kΩ, CLOAD = 100 pF,-55°C to +125°C

01,02,

10% to 90%

17

03,04

10 typicalns

Output source resistance RSRC_P IOUT = 20 mA, 5 V ≤ VIN ≤ 14 V

-55°C to +125°C

01,02,
03,04

15 typicalΩOutput sink resistance-55°C to +125°C

01,02,
03,04

15 typicalΩ

RSINK_P IOUT = 20 mA, 5 V ≤ VIN ≤ 14 V

See footnotes at end of table.

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PAGE 10

TABLE IA. Electrical performance characteristics – Continued. 1/ 2/
Test

SymbolConditions
VIN = 4 V to 14 V,

Temperature,
TJ

Devicetype

unless otherwise specified

Limits
Min

Unit
Max

MINIMUM ON TIME AND DEAD TIME
Minimum on timetMIN

LEB = 10 kΩ, 5 V ≤ VIN ≤ 14 V

-55°C to +125°C

01

Primary off to secondary

TDPS

PS = floating, 5 V ≤ VIN ≤ 14 V, 90%-55°C to +125°C

01

on dead time

5of OUTx falling to 10% of SRx rising,
OUTx and SRx floating

85

ns

11

ns

8 typical

PS = 49.9 kΩ, 5 V ≤ VIN ≤ 14 V, 90%

43

of OUTx falling to 10% of SRx rising,
OUTx and SRx floating

50 typical

PS = 107 kΩ, 5 V ≤ VIN ≤ 14 V, 90%

85

of OUTx falling to 10% of SRx rising,
OUTx and SRx floating

100 typical

Secondary off to primary TDSPSP = floating, 5 V ≤ VIN ≤ 14 V,

on dead time

90% of SRx falling to 10% of OUTx
rising, OUTx and SRx floating-55°C to +125°C

01

5

55

110

11

ns

8 typical

SP = 49.9 kΩ, 5 V ≤ VIN ≤ 14 V,

4355

90% of SRx falling to 10% of OUTx
rising edge, OUTx and SRx floating

50 typical

SP = 107 kΩ, 5 V ≤ VIN ≤ 14 V,

85

90% of SRx falling to 10% of OUTx
rising, OUTx and SRx floating

100 typical110

LEADING EDGE BLANK TIME AND DUTY CYCLE
Leading edge blank time TLEBLEB = 10 kΩ, 5 V ≤ VIN ≤ 14 V

-55°C to +125°C

01

12

19

ns

15 typical
LEB = 49.9 kΩ, 5 V ≤ VIN ≤ 14 V

45

55

50 typical
LEB = 110 kΩ, 5 V ≤ VIN ≤ 14 V

85

110

100 typical
Maximum duty cycle

DMAX

DCL = AVSS

-55°C to +125°C

01

45

50

48 typical
DCL = floating, clock duty cycle = 50%

70

80

75 typical
DCL = VLDO

100

See footnotes at end of table.

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PAGE 11%TABLE IA. Electrical performance characteristics – Continued. 1/ 2/
Test

SymbolConditions
VIN = 4 V to 14 V,

Temperature,
TJ

Devicetype

unless otherwise specified

Limits
Min

Unit
Max

MINIMUM ON TIME AND DEAD TIM E
Minimum on timetMIN

LEB = 10 kΩ, 5 V ≤ VIN ≤ 14 V

-55°C to +125°C

02

Primary off to secondary

TDPS

PS = floating, 5 V ≤ VIN ≤ 14 V,-55°C to +125°C

02

on dead time5

90 % of OUTx falling to 10% of SRx
rising, OUTx and SRx floating

85

ns

11

ns

8 typical

PS = 49.9 kΩ, 5 V ≤ VIN ≤ 14 V,

43

90% of OUTx falling to 10% of SRx
rising, OUTx and SRx floating

50 typical

PS = 107 kΩ, 5 V ≤ VIN ≤ 14 V,

85

90 % of OUTx falling to 10% of SRx
rising, OUTx and SRx floating

100 typical

Secondary off to primary TDSPSP = floating, 5 V ≤ VIN ≤ 14 V,

on dead time

90% of SRx falling to 10% of OUTx
rising, OUTx and SRx floating-55°C to +125°C

02

5

55

110

11

ns

8 typical

SP = 49.9 kΩ, 5 V ≤ VIN ≤ 14 V,

4355

90% of SRx falling to 10% of OUTx
rising edge, OUTx and SRx floating

50 typical

SP = 107 kΩ, 5 V ≤ VIN ≤ 14 V,

85

90% of SRx falling to 10% of OUTx
rising, OUTx and SRx floating

100 typical110

LEADING EDGE BLANKTIME AND DUTY CYCLE
Leading edge blank time TLEBLEB = 10 kΩ, 5 V ≤ VIN ≤ 14 V

-55°C to +125°C

02

12

19

ns

15 typical
LEB = 49.9 kΩ, 5 V ≤ VIN ≤ 14 V

45

55

50 typical
LEB = 110 kΩ, 5 V ≤ VIN ≤ 14 V

85

110

100 typical
Maximum duty cycle

DMAX

DCL = floating, clock duty cycle = 50%-55°C to +125°C

02

70

80

75 typical
DCL = VLDO

100

See footnotes at end of table.

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PAGE 12%TABLE IA. Electrical performance characteristics – Continued. 1/ 2/
Test

SymbolConditions
VIN = 4 V to 14 V,

Temperature,
TJ

Devicetype

unless otherwise specified

Limits
Min

Unit
Max

MINIMUM ON TIME AND DEAD TIM E
Minimum on-timetMIN

5 V ≤ VIN ≤ 14 V

-55°C to +125°C

03

Primary off to secondary
on dead timeTDPS

5 V ≤ VIN ≤ 14 V, 90% of OUTx fallingto 10% of SRx rising,-55°C to +125°C

03

OUTx and SRx floating
Secondary off to primary TDSP
on dead time

115

ns

60

ns

60

ns

60

ns

40
50 typical-55°C to +125°C

5 V ≤ VIN ≤ 14 V, 90% of SRx fallingto 10% of OUTx rising edge,

03

OUTx and SRx floating

40
50 typical

LEADING EDGE BLANKTIME AND DUTY CYCLE
Leading edge blank time TLEB

5 V ≤ VIN ≤ 14 V

-55°C to +125°C

0340

50 typical
Maximum duty cycle

DMAX

DCL = floating, clock duty cycle = 50%-55°C to +125°C

03

70

80

%

75 typical
DCL = VLDO

100

MINIMUM ON TIME AND DEAD TIM E
Minimum on-timetMIN

LEB = 10 kΩ, 5 V ≤ VIN ≤ 14 V

-55°C to +125°C

04

Leading edge blank time TLEBLEB = 10 kΩ, 5 V ≤ VIN ≤ 14 V

-55°C to +125°C

04

12

85

ns

19

ns

15 typical
LEB = 49.9 kΩ, 5 V ≤ VIN ≤ 14 V

45

55

50 typical
LEB = 110 kΩ, 5 V ≤ VIN ≤ 14 V

85

110

100 typical
Maximum duty cycle

DMAX

DCL = AVSS

-55°C to +125°C

04

45

50

%

48 typical1/

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance overthe specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.

2/

Device types 01-04 supplied to this drawing have been total ionizing dose (TID) characterized in accordance with
MIL-STD-883 method 1019 at dose rate condition A to TID level of 50 krads(Si). Post irradiation electrical parametric limits falls
within the specification limits during electrical measurement. The radiation end point limits for the noted parameters areguaranteed only for the conditions as specified in MIL-STD-883, method 1019, condition A to a maximum total dose of
50 krads(Si).

3/

Bench verified. Not tested in production.

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PAGE 13TABLE IB. SEP test limits. 1/ 2/ 3/
Devicetypes

SEP/SEE

Temperature (TC)

VIN

Effective linear energy
transfer (LET)

01,02,03,04

No SEL+125°C

14 V≤ 43 MeV/(mg/cm2)

01,02,03,04

No SEB nor SEGR

+25°C

14 V

≤ 43 MeV/(mg/cm2)

1/ For single event phenomena (SEP) test conditions, see 4.3 herein.
2/ Technology characterization and model verification supplemented by in-line data
may be used in lieu of end of line testing. Test plan must be approved by the technicalreview board.
3/ SEE test shall be performed in accordance with ASTM F1192 or JESD57. For more information on SEP test
results, customers are requested to contact the manufacturer.

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
4.2 Total dose irradiation testing. Total ionizing dose irradiation testing shall be performed in accordance with MIL-STD-883 method
1019, condition A for all device types and as specified in 1.6 herein.
4.3 Single event phenomena (SEP). SEP testing was performed on two units per the conditions in TABLE IB. The recommended
test conditions for SEP are as follows:a.

The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive(i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related affects is allowed.

b.

The fluence shall be ≥ 100 errors or ≥ 107 ions/cm2.

c.

The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by measuring thecross-section at two flux rates which differ by at least an order of magnitude.

d.

The particle range shall be ≥ 20 micron in silicon.

e.

The test temperature shall be +125°C ±10% for SEL.

f.

For SEP test limits, see table IB herein.

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PAGE 14Case XFIGURE 1. Case outline.

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PAGE 15

Case X - continued

SymbolDimensions
InchesMillimeters

Minimum

Maximum

Minimum

Maximum

A

---

.047

---

1.2

A1

.002

.006

0.05

0.15

b

.007

.012

0.19

0.30

c

.006 TYP

0.15 TYP

D

.303

.311

7.7

7.9

E

.169

.177

4.3

4.5

E1

.244

.260

6.2

6.6

e

.025 BSC

0.65 BSC

e1.281 BSC

7.15 BSC

L

.020

.029

0.50

0.75

NOTES:
1. Controlling dimensions are millimeter, inch dimensions are given for reference only.
2.

Dimension D does not include mold flash, protrusion, or gate burrs. Mold flash, protrusion, or gate burrs shall not
exceed 0.15 mm (.006 inch) per side.

3.

Dimension E does not include interlead flash. Interlead flash shall not exceed 0.25 mm (0.0098 inch) per side.

4.

Falls within reference to JEDEC MO-153.

FIGURE 1. Case outline - Continued.

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PAGE 16Case outline
Terminal
symbolX
Device Device Device Device
type 01 type 02 type 03 type 04

I/O

Description

Terminal number
RT

1

1

1

1

I/O

In internal oscillation mode, the RT pin must be populatedwith a resistor to AVSS. When the RT pin is floating,a 200 kHz to 4 MHz external clock is required at the SYNC
pin. The frequency of the external clock must be twice thedesired switching frequency.

PS

2

2

---

---

I/O

Primary off to synchronous rectifier on dead time set.
Programmable through an external resistor to AVSS.

SP

3

3

---

---

I/O

Synchronous rectifier off to primary on dead time set.
Programmable through an external resistor to AVSS.

LEB

4

4

---

4

HICC

5

5

5

5

I/O

Cycle by cycle current limit time delay and hiccup time
setting. Delay time and hiccup time determined by capacitor
from HICC to AVSS. Connecting this pin to AVSS disables
hiccup mode.

SYNC

6

6

6

6

I/O

When the RT pin is floating, SYNC is configured as an input
for a 200 kHz to 4 MHz external clock. In this case, theexternal clock input gets inverted and the system clock will
run at half the frequency of the external clock input. When
the RT pin is populated with a resistor to AVSS, SYNC
outputs a 200 kHz to 4 MHz clock signal at twice the device
switching frequency in phase with the switching of the device.

DCL

7

7

7

7

I/O

Duty cycle limit configurability. For device type 01, connect
to AVSS for 50% duty cycle limit, floating for 75%, and
VLDO for 100%. For device type 02 and device type 03, theDCL pin can be left floating or connected to VLDO to set the
maximum duty cycle to 75% or 100%, respectively. For
device type 04, this pin must be connected to AVSS in orderto obtain the 50% maximum duty cycle.

EN

8

8

8

8

I

Connecting the EN pin to the VLDO pin or external source
greater than 0.6 V enables the device. In addition, input
undervoltage lockout (UVLO) can be adjusted with two
resistors.

VIN

9

9

9

9

OUTA

10

10

10

10

I/O

Leading edge blank time set. Programmable through anexternal resistor to AVSS.

I

Input supply to the device. Input voltage range is from 4 V to
14 V.

O

Primary switching output A.

FIGURE 2. Terminal connections.

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PAGE 17Case outline
Terminal
symbolX
Device Device
type
type
01
02

Device Device
type
type
03
04

I/O

Description

Terminal number
OUTB

11

---

---

11

O

Primary switching output B. Active only when DCL = AVSS.

NC

12,13

11,12,
13,14

2,3,4,
11,12,
13,14

2,3,
12,13,
14,15---

No connect.

SRB

14

---

---

---

O

Synchronous rectifier output B. Active only when DCL =
AVSS.

SRA

15

15

15

---

O

Synchronous rectifier output A.

AVSS

16

16

16

16

---

Ground of the device.

VLDO

17

17

17

17

O

Output of internal regulator. Requires at least 1 μF external
capacitor to AVSS.

CS_ILIM

18

18

18

18

I/O

Current sense for PWM control and cycle by cycle overcurrent
protection. An input voltage over 1.05 V on CS_ILIM will
trigger an overcurrent in the PWM controller.

FAULT

19

19

19

19

I

Fault protection pin. When the rising threshold of the FAULT
pin is exceeded, the outputs will stop switching. After theexternal voltage drops below the falling threshold, the device
will restart after a set delay. Connect this pin to AVSS todisable FAULT.

REFCAP

20

20

20

20

O

1.2 V internal reference. Requires a 470 nF external
capacitor to AVSS.

RSC

21

21

21

21

I/O

A resistor from RSC to AVSS sets the desired slope
compensation.

SS

22

22

22

22

I/O

Soft start. An external capacitor connected to this pin sets theinternal voltage reference rise time. The voltage on this pin
overrides the internal reference. It can be used for tracking
and sequencing.

VSENSE

23

23

23

23

I

Inverting input of the error amplifier.

COMP

24

24

24

24

I/O

Error amplifier output. Connect frequency compensation tothis pin.

FIGURE 2. Terminal connections - Continued.

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PAGE 18

NOTE: OUTB and SRB waveforms are only applicable for device type 01.

FIGURE 3. Outputs timing waveforms.

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PAGE 19

5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Additional information. When applicable, a copy of the following additional data shall be maintained and available from thedevice manufacturer:
a. RHA test conditions of SEP.
b. Number of latchup (SEL).
6.4 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.
Vendor item drawing
administrative control
number 1/

Devicemanufacturer
CAGE code

Mode oftransportationand quantity

Top sidemarking

Vendor part number

V62/22607-01XE

01295

Small tape andreel, 250 units

7H5005PW

TPS7H5005MPWTSEP

V62/22607-02XE

01295

Small tape andreel, 250 units

7H5006PWTPS7H5006MPWTSEP

V62/22607-03XE

01295

Small tape andreel, 250 units

7H5007PW

TPS7H5007MPWTSEP

V62/22607-04XE

01295

Small tape andreel, 250 units

7H5008PW

TPS7H5008MPWTSEP

1/

The vendor item drawing establishes an administrative control number for identifying the item on theengineering documentation.

CAGE code

Source of supply

01295

DLA LAND AND MARITIMECOLUMBUS, OHIO

Texas Instruments, Incorporated
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZE
A

CAGE CODE
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PAGE 20