REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)

Prepared in accordance with ASME Y14.24

APPROVED

Vendor Item Drawing

Revision Status of Sheets
REVSHEETREVSHEET12PMIC N/A
Original date ofdrawing
YY-MM-DD
22-06-033457891011

PREPARED BY
RICK OFFICERAPPROVED BY
JAMES R. ESCHMEYER

A
REV1213

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

CHECKED BYRAJESH PITHADIASIZEAMSC N/A6

CAGE CODE

16236

TITLE

https://www.dla.mil/landandmaritime

MICROCIRCUIT,LINEAR, HIGH PRECISION, LOW
NOISE, RAIL-TO-RAIL OUTPUT, 11 MHz, JFETOPERATIONAL AMPLIFIER, MONOLITHIC
SILICONDWG NO.

PAGE

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

V62/21607
1 OF 135962-V051-22

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance high precision, low noise, rail-to-rail output,
11 MHz joint field effect transistor (JFET) operational amplifier microcircuit, with an operating temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/21607-Drawing
number01

XE

Device type
(See 1.2.1)

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

GenericCircuit function

01

OPA4H014-SEP

High precision, low noise, rail-to-rail output,
11 MHz JFET operational amplifier

1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95X

14MO-153

Package style
Plastic small outline

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

MaterialABC
DEFZ

DLA LAND AND MARITIMECOLUMBUS, OHIO

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy (BGA/CGA)
OtherSIZEACAGE CODE
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1.3 Absolute maximum ratings.

1/Supply voltage range (VS = +V - -V) :Dual supply .......................................................................................................................... ±10 VSingle supply ........................................................................................................................ 20 V
Signal input pins:
Voltage ................................................................................................................................. -VS – 0.5 V to +VS + 0.5 V 2/
Current ................................................................................................................................. ±10 mA 2/
Output short circuit ................................................................................................................... Continuous 3/
Temperature:
Operating ............................................................................................................................. -55°C to +150°C
Junction ................................................................................................................................ +150°C
Storage (Tstg) ....................................................................................................................... -65°C to +150°C
Electrostatic discharge (ESD) rating:
Human body model (HBM) per JEDEC JS-001 .................................................................... ±2000 V 4/
Charge device model (CDM) per JEDEC JS-002 ................................................................. ±500 V 5/
1.4 Recommended operating conditions. 6/
Supply voltage range (VS = +V - -V) :Dual supply .......................................................................................................................... ±2.25 V to ±9 V
Single supply ........................................................................................................................ 4.5 V to 18 V
Operating free-air temperature range (TA) ............................................................................... -55°C to +125°C
1.5 Thermal characteristics.
Thermal metricSymbol

Case X

Unit

Thermal resistance, junction-to-ambient

θJA

135°C/W

Thermal resistance, junction-to-case (top)θJC(TOP)

45°C/W

Thermal resistance, junction-to-board

θJB

66°C/W

Characterization parameter, junction-to-top

ψJT19°C/W

Characterization parameter, junction-to-board

ψJB60°C/W

Thermal resistance, junction-to-case (bottom)

θJC(BOTTOM)

N/A

°C/W

______
1/

Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.

2/

Input terminal are diode clamped to the power supply rails. Input signals that can swing more than 0.5 V beyond the supply rails
should be current limited to 10 mA or less.

3/

Short circuit to VS/2 (ground in symmetrical dual supply setups), one amplifier per package.

4/

JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

5/

JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6/

Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.

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1.6 Radiation features.
Maximum total dose available (dose rate = 50 - 300 rad(Si)/s) ................................................ 30 krads(Si) 7/
Single event phenomenon (SEP):No Single event latchup (SEL) occurs at effective LET (see 4.3) ......................................... ≤ 43 MeV/(mg/cm2)8/

2. APPLICABLE DOCUMENTS
ASTM INTERNATIONAL (ASTM)
ASTM F1192–Standard Guide for the Measurement of Single Event Phenomena (SEP) from Heavy Ion Irradiationof semiconductor Devices.

(Copies of these documents are available online at https://www.astm.org.)
DEPARTMENT OF DEFENSE STANDARDSMIL-STD-883–Test Method Standard Microcircuits.

(Copies of these documents are available online at https://quicksearch.dla.mil.)
JEDEC Solid State Technology Association
JEDEC JS-001
JEDEC JS-002
JESD 57–−−

JEDEC PUB 95
JEDEC JEP 155
JEDEC JEP 157–––

Human Body Model Testing of Integrated Circuits
Electrostatic Discharge Sensitivity Testing - Charge Device Model (CDM)
Test Procedures for the Measurement of Single Event Effects in Semiconductor Devices fromHeavy Ion Irradiation
Registered and Standard Outlines for Semiconductor Devices
Recommended ESD Target Levels for HBM/MM Qualification
Recommended ESD-CDM Target Levels(Copies of these documents are available online at https://www.jedec.org.)______
7/ All device types supplied to this drawing have been characterized at 30 krad(Si) of irradiation. However, these device’s radiation
end point limits for the noted parameters are guaranteed to TID level 30 krad(Si) as specified in MIL-STD-883, method 1019,
condition A. Pre and Post irradiation values are identical unless otherwise specified in Table IA. When performing post irradiationelectrical measurements for any RHA level, TA = +25°C (see 1.6 herein).
8/

For more information on SEP test results, customers are requested to contact the manufacturer (see SEP table IB).

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3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table IA herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revisionlevel control and shall be made available to the preparing and acquiring activity upon request.

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REVPAGE 5TABLE IA. Electrical performance characteristics. 1/Test

SymbolConditions 2/ 3/

Temperature,TADevice
typeLimits
MinUnitMax

Offset voltage
Input offset voltage

+25°C

VOS

01±120µV±30 typical-55°C to +125°C

VS = ±9 V

Input offset voltage drift∆VOS /-55°C to +125°C

VS = ±9 V±22001

µV/V

±1

µV/°C

±0.35 typical∆T
Power supply rejection
ratio±4

PSRR-55°C to +125°C

01

±0.5

µV/V

±0.1 typical
Channel separationf = dc+25°C01

f = 100 kHz

0.02 typicalµV/V

10 typicalInput bias current
Input bias current

+25°C

IB

01

±10pA

±0.5 typical-55°C to +125°C
Input offset current

+25°C

IOS

01

±3nA

±10pA

±0.5 typical-55°C to +125°C±1nA

250 typicalnVPP

42 typicalnVRMS

8 typical

nV/√HzNoise
Input voltage noiseEn

f = 0.1 Hz to 10 Hz

+25°C

01

f = 0.1 Hz to 10 Hz
Input voltage noise

endensity

Input current noise
densityinf = 10 Hz

+25°C

01

f = 100 Hz

5.8 typicalf = 1 kHz

5.1 typicalf = 1 kHz

+25°C

01

0.8 typicalSee footnotes at end of table.

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PAGE 6fA/√Hz

TABLE IA. Electrical performance characteristics – Continued. 1/Test

SymbolConditions 2/ 3/

Temperature,TA

DevicetypeLimits
Min

Max+VS –3.5

Unit

Input voltage range
Common mode voltage

VCM

Common mode

CMRR

rejection ratio

VS = ±9 V,-55°C to +125°C

01

-VS –
0.1+25°C

01

126VdB

140 typical

VCM = -VS – 0.1 V to +VS – 3.5 V

120-55°C to +125°C
Input impedanceDifferential

ZID

Common mode

ZIC

AOL+25°C

011013||10 typical

Ω||pF
4/

VCM = -VS – 0.1 V to +VS – 3.5 V+25°C

011013||7 typical

Ω||pF
4/

VO = -VS + 0.35 V to +VS – 0.35 V,

+25°C

01

Open loop gain
Open loop voltage
gain

120dB

126 typical

RL = 10 kΩ

114

VO = -VS + 0.35 V to +VS – 0.35 V,

126 typical

RL = 2 kΩ

108-55°C to +125°C
Frequency response
Gain bandwidth
product

BW+25°C01

11 typical

MHzSlew rate

SR+25°C01

20 typicalV/µs

Settling timetS+25°C

01

0.88 typicalµs

12 bits, 10 V step, gain = +116 bits, 10 V step, gain = +1

Overload recovery timetOR

Total harmonic
distortion + noise

THD+N

f = 1 kHz, G = 1, VO = 3.5 VRMS

1.6 typical
+25°C

01

600 typicalns+25°C

01

0.00005 typical%See footnotes at end of table.

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TABLE IA. Electrical performance characteristics – Continued. 1/TestSymbol

Conditions 2/ 3/Temperature,TADevice
typeLimitsMinMax-VS +0.2+VS –0.2-VS +0.35+VS –0.35

UnitOutput
Voltage output swing
from railVO

RL = 10 kΩ, AOL ≥ 108 dB+25°C

01

RL = 2 kΩ, AOL ≥ 108 dB
Short circuit current

ISC

Source+25°C

01

Sink
Open loop output
impedance

36 typicalVmA-30 typicalZO

f = 1 MHz, IO = 0 A

+25°C

01

16 typicalΩIQ

IO = 0 mA+25°C

01

2mA

Power supply
Quiescent current(per amplifier)

1.8 typical-55°C to +125°C

2.71/Testing and other quality control techniques are used to the extent deemed necessary to assure product performance overthe specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.

2/All device types supplied to this drawing have been characterized at 30 krad(Si) of irradiation. However, these device’s radiation
end point limits for the noted parameters are guaranteed to TID level 30 krad(Si) as specified in MIL-STD-883, method 1019,
condition A. Pre and Post irradiation values are identical unless otherwise specified in Table IA. When performing post irradiationelectrical measurements for any RHA level, TA = +25°C (see 1.6 herein).

3/

Unless otherwise specified, VS = ±2.25 V to ±9 V at TA = 25°C, RL = 2 kΩ connected to midsupply, andVCM = VOUT = midsupply.

4/

The || symbolizes that the input impedance is being represented as the resistance value is in parallel with the capacitance.

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TABLE IB. SEP test limits. 1/ 2/ 3/Device type

SEP/SEE

Temperature (TC)

VIN

Effective linear energytransfer (LET)01

No SEL+125°C±9 V≤ 43 MeV/(mg/cm2)

1/ For single event phenomena (SEP) test conditions, see 4.3 herein.
2/ Technology characterization and model verification supplemented by in-line data
may be used in lieu of end of line testing. Test plan must be approved by the technicalreview board.
3/ SEE test shall be performed in accordance with ASTM F1192 or JESD57. For more information on SEP test
results, customers are requested to contact the manufacturer

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements asindicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
4.2 Total dose irradiation testing. Total ionizing dose irradiation testing shall be performed in accordance with MIL-STD-883 method
1019, condition A for all device types and as specified in 1.6 herein.
4.3 Single event phenomena (SEP). SEP testing was performed on two units per the conditions in TABLE IB. The recommended
test conditions for SEP are as follows:a.

The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive(i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related affects is allowed.

b.

The fluence shall be ≥ 100 errors or ≥ 107 ions/cm2.

c.

The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by measuring thecross-section at two flux rates which differ by at least an order of magnitude.

d.

The particle range shall be ≥ 20 micron in silicon.

e.

The test temperature shall be +125°C ±10% for SEL.

f.

For SEP test limits, see table IB herein.

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PAGE 9Case XFIGURE 1. Case outline.

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Case X - continued

SymbolDimensions
InchesMillimeters

Minimum

Maximum

Minimum

Maximum

A---.047

---

1.20

A1.002

.006

0.05

0.15

b.007

.012

0.19

0.30

c.006 NOM

0.15 NOM

D.193

.201

4.90

5.10

E.169

.177

4.30

4.50

E1.244

.260

6.20

6.60

e
L.025 BSC.020

L10.65 BSC.029.010 NOM

0.50

0.75

0.25 NOMNOTES:
1. Controlling dimensions are millimeter, inch dimensions are given for reference only.
2. For dimension D, body length does not include mold flash, protrusion, or gate burrs. Mold flash, protrusion, or gate burrs
shall not exceed 0.15 mm (.006 inch) per side.
3. For dimension E, body width does not include interlead flash. Interlead flash shall not exceed 0.25 mm (0.010 inch) eachside.
4. Falls within reference to JEDEC MO-153.

FIGURE 1. Case outline - Continued.

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REVPAGE 11Device type01

Case outlineX

Terminal number

Terminalsymbol

I/O

1

OUT AOOutput, channel A.

2-IN AI

Inverting input, channel A.

3+IN AI

Noninverting input, channel A.

4+VSPower

Positive (highest) power supply.

5+IN BI

Noninverting input, channel B

6-IN B

I

Inverting input, channel B.

7OUT B

OOutput channel B.

8OUT CO

Output, channel C.

9-IN CI

Inverting input, channel C.

10+IN CI

Noninverting input, channel C.

11-VSPower

Negative (lowest) power supply.

12+IN DI

Noninverting input, channel D.

13-IN DI

Inverting input, channel D.

14

OUT DO

Output, channel D.

Description

FIGURE 2. Terminal connections.

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5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Additional information. When applicable, a copy of the following additional data shall be maintained and available from thedevice manufacturer:
a. RHA test conditions of SEP.
b. Number of latchup (SEL).
6.4 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guaranteeof present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

Vendor item drawing
administrative control
number 1/Device
manufacturer
CAGE code

Mode oftransportationand quantity

Top sidemarking

Vendor part number

V62/21607-01XE

01295

Tube, 90 units

O4H01A

OPA4H014PWSEP

Reel, 2000 units

O4H01A

OPA4H014PWTSEP

1/ The vendor item drawing establishes an administrative control number for identifying the item on theengineering documentation.

CAGE code

Source of supply01295

DLA LAND AND MARITIMECOLUMBUS, OHIO

Texas Instruments, Incorporated
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZEA

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