A Novel Five-level Three-phase PWM Rectifier using 12 Switches

Jun-ichi ItohYuichi Noge

Taketo Adachi

Member, IEEE
Nagaoka University of Technology
1603-1 Kamitomioka-cho Nagaoka City
Niigata, Japan
itoh@vos.nagaokaut.ac.jp

Student Member, IEEE
Nagaoka University of Technology
1603-1 Kamitomioka-cho Nagaoka City
Niigata, Japan
noge@stn.nagaokaut.ac.jp

Student Member, IEEE
Nagaoka University of Technology
1603-1 Kamitomioka-cho Nagaoka City
Niigata, Japanadachi@stn.nagaokaut.ac.jp

Abstract -- This paper proposes a new circuit topology for a
multilevel PWM rectifier. The proposed circuit combines a
diode clamp type topology with a flying capacitor type topology.
As a result, the proposed circuit uses only 12 switches, despite
the use of a five-level three-phase PWM rectifier. Further, theproposed circuit can obtain good performance as same as to aconventional multilevel circuit. This paper describes the featuresof the proposed topology; the control strategy and loss analysis
using circuit simulation. In addition, the basic operation of the
proposed method is confirmed by simulation and experimental
results. The proposed converter achieved 3.4% THD for the
input current and 97.4% efficiency for a 1 kW classexperimental setup.
Index Terms—Multilevel, PWM rectifier, Space vector
modulation,I.

INTRODUCTION

Recently, the harmonics current in power grids have caused
various problems, such as line voltage distortion and heatingof power factor correction capacitors. The harmonics current
in power grids is mainly generated by a diode rectifier which
is used as a front converter of an inverter. In order to reduce
the harmonics current of the power grid, power factor
correction (PFC) rectifier is still a very important technology.
A PWM rectifier, which consists of three switching legs, is
one of the popular PFC rectifiers. A PWM rectifier canstrongly reduce the harmonics current because the gridcurrent can be controlled.
A PWM rectifier requires high voltage rating devices inorder to be applied to medium voltage applications. The highvoltage rating devices have problems, such as low switching
speed and large saturation voltage between collector andemitter. The low switching speed causes the large volume of aboost reactor and filter since the high switching frequency
does not achieved. As a result, it is difficult to apply the
PWM rectifier to a medium voltage power grid.
For a medium voltage power grid, multi-level converter
technology is one of the solutions for high voltage
rectification application [1-3]. In general, a n-level converter
can reduce the voltage stress of a switching device to 1/(n–1)
of the DC output voltage. There are many circuit
configurations for a multi-level converter, such as the diodeclamp (DCLP) type [4][5] that uses clamp diodes andcapacitors for the DC output voltage, the flying capacitor(FC) type [6][7] that uses clamping capacitors floating on the
DC output voltage, and the chain link (CL) type [8][9] thatuses isolated power supplies to clamp each level. With
respect to cost reduction and downsizing, the DCLP and FC
types are better solutions than the CL type, since CL typerequires a large transformer and many switching devices.
However, for over three-level rectifiers, the DCLP typerequires balance circuits in the DC part, in order to control
the clamping capacitor voltage [10]. In contrast, the FC typerequires several capacitors for clamping capacitors. In
addition, both methods use many switches. For example, inthe case of a five-level three-phase rectifier, 24 switching
devices are required. In conclusion, the problems of multilevel converters are the number of switching devices andcontrol of the clamping capacitor voltage.
This paper proposes a novel five-level three-phase rectifier
topology, which combines the DCLP and FC type converters,
and its control strategy. The proposed converter requires only
half the number of switches in comparison with the DCLP
and FC types, that is, only 12 switches are used for the fivelevel rectifier. The point of the proposed topology is that highvoltage diodes can be more easily to be utilized than highvoltage switching devices. The features of the proposed
circuit are described, and the control strategy is using by
space vector modulation. The used of space vector
modulation can result in a good sinusoidal current of thepower grid. In addition, a loss analysis method based on the
PSIM circuit simulator is introduced [11]. The validity of the
proposed rectifier, the control strategy, and the loss analysis
are confirmed by experimental results.
II.
A.

PROPOSED CIRCUIT TOPOLOGY

Conventional Circuit

Fig. 1 (a) shows the DCLP and (b) shows the FC type fivelevel PWM rectifier topology. The switching devices of both
topologies are of the same voltage rating. Both converters canuse a voltage rating 1/4 of that for the DC output voltage;
however, these converters use 24 switching devices. As aresult, cost is increased and the control strategy becomescomplicated. For example, the control strategy for the FC
type five-level PWM rectifier is described in the following.

The FC type five-level PWM rectifier has 16 switchingpatterns. The switching patterns and its rectifier input voltage,
which is the voltage point between the rectifier and the boost
up reactor based on the neutral point of the power grid,
There are many switch patterns which can charge ordischarge to the flying capacitor in disregard of the same
voltage level. These switch patterns should be selected inorder to control the voltage of each flying capacitor inconstant. In addition, many voltage sensors are required todetect the voltage of the flying capacitors.
On the other hand, for the DCLP type, the clamping
capacitor voltage can not be controlled without an auxiliary
circuit. Additional voltage regulators, such as DC chopper,
are required to maintain each clamping capacitor voltage inthe quarter of the DC output voltage.
B.

are constrained by the direction of grid current because theproposed circuit uses diodes in the main current path.
The switching patterns and rectifier input voltage level atthat pattern are described as follows. Note that the neutral
point of the DC side is defined as the zero voltage level in this
discussion.
In principle, the proposed circuit can output seven voltage

Proposed Circuit

Fig. 2 shows the proposed five-level PWM rectifier using
only 12 switches. The proposed converter combines both the
DCLP and FC types into one. High voltage rating diodes are
required in the proposed circuit; however, a fast recovery
diode is unnecessary, because there is no recovery mode forthe high voltage diode in the proposed circuit. Thus, the highvoltage low speed diode is cheaper than the high voltage
switching devices. It should be noted that if the regeneration
mode is required, then high voltage switching devices can beused instead of the high voltage diode. In this case, low speed
switching devices, such as a thyristor or a gate turn off
thyristor (GTO), can be applied, because the high voltage
switching devices do not switch at high frequency, but only
switch at the same frequency of the power grid.
Table I shows a comparison among the DCLP, FC andproposed rectifier. The largest advantage of the proposed
circuit is that the proposed circuit allows the number of theswitches and capacitors to be reduced, so that the number ofswitching devices becomes 12, which is half of theconventional circuit. It should be noted that if the proposed
concept is applied for other multi-level rectifier topology,
then the number of switching devices can always be reduced
to half of the conventional topology, because the outside
diode can take half of the DC output voltage.
The other large advantage of the proposed circuit is that the
proposed circuit can control each clamping capacitor voltage.
The voltage of the inner clamping capacitor C1 can becontrolled, because the structure of the inside part is the sameas that of the FC type. The voltage of the middle capacitors(C2 and C3) also can also be controlled, because this part isthe same as the three-level rectifier. Note that the proposed
circuit can not accept an invert operation which is reverse
energy flow because the diodes are used instead of switches.
Fig. 3 shows the current path of the proposed rectifier ineach switching pattern. The proposed rectifier has eightswitching patterns. However, the available switching patterns(a) Diode Clamp (DCLP)(b) Flying Capacitor (FC)Fig. 1. Conventional five-level PWM rectifier topologies (single leg).

Fig. 2. Proposed hybrid PWM rectifier.
TABLE ICOMPARISON OF THE DCLP, FC AND PROPOSED CONVERTER
DCLP

FC

ProposedcircuitSwitch

24

24

12

*

Diode

60

24

36

Capacitor

4

30

13

Control of thecapacitor voltage

impossible

possiblepossible*

including FWD

levels to the AC side of the converter. However, in order tocontrol the inner clamping capacitor (C1) voltage Vc, twoswitching patterns for charge or discharge mode are required.
Therefore, to keep the two switching patterns, the voltage
levels +Vdc/2 –Vc and +Vc, -Vc and –Vdc/2 +Vc are set to thesame of each voltage level. That is, Vc is set to Vdc/4. As aresult, Vc can be controlled by switching pattern of 2) and 3)or 6) and 7), respectively.
III. CONTROL STRATEGYA.

Space Vector Modulation
Fig. 4 shows the space vector for the proposed five-levelrectifier, where “x” represents the top of the voltage vector. In
the case of the proposed rectifier, there are 61 kinds of thevoltage vectors, except for the charge or discharge switchingpatterns to the inner clamping capacitor in the proposed
circuit. Firstly, the three nearest space vectors V1, V2, and V3,
where surrounding the top of the output voltage vector vo of
the rectifier, are selected. Note that the output vector
represents the input voltage of the power converter. The
charge or discharge mode vector is selected according to theinner clamping capacitor voltage and the neutral point voltageof the DC output part. The selected vectors V1, V2, and V3 areexpressed by (1) using the α-axis (horizontal) and β-axis(vertical) components.
 V1 = V1α + V1βV2 = V2α + V2 β
V = V + V
3α
3β
 3

(a) Positive period of the input voltage.

(1)

The subscripts α and β are the horizontal and verticalcomponents of the selected vectors, respectively. The relation
between the selected vectors and the output vector is obtainedby (2).
voα = V1α T1 + V2α T2 + V3α T3voβ = V1β T1 + V2 β T2 + V3 β T3
 1 = T +T +T
1
2
3


(2)

T1, T2, and T3 are the output time ratio on a carrier period
for each of the selected vector. Therefore, the output periodof each vector is calculated using (3) from (2).
T1 =1{(V2 β − V3 β )(voα − V3α ) + (V3α − V2α )(voβ − V3 β )}
A

T2 =

1
{(V3 β − V1β )(voα − V3α ) + (V1α − V3α )(voβ − V3 β )}
A

T3 =

1
{(V2 β − V1β )(voα − V3α ) + (V1α − V2α )(voβ − V3β )}
A

(3)

where
A = (V1α − V3α )(V2 β − V3β ) − (V1β − V3 β )(V2α − V3α )The inner clamping capacitor voltage is controlled by theselection of the switching pattern, since the proposed rectifier(b) Negative period of the input voltage.
Fig. 3. Current path of the proposed rectifier.

can output the same voltage level using different switchingpatterns that achieved charge or discharge to the inner
clamping capacitor. For example, when the polarity of the
input voltage is positive, a quarter voltage level of the DC
output voltage is obtained by having both switches S2, S4
turned on and switches S1, S3 turned on, provided the inner
clamping capacitor C1 voltage is set to quarter of the DC
output voltage. While the switches S2 are S4 are turned on, theinner clamping capacitor can be charged. In contrast, while
the switches S1 are S3 are turned on, the inner clamping
capacitor can be discharged.
B.

Control Block Diagram
Fig. 5 shows the control block diagram for the space vector
modulation of the proposed rectifier. The DC output voltage
and the input current are controlled by a PI regulator on arotating frame, the same as that in a conventional PWM
rectifier. In the switching table, the output vector isdetermined by the magnitude of the vector, the phase angle ofthe power grid, and the capacitor voltage control conditions
using a hysteresis controller.
Fig. 6 shows the voltage waveform of the rectifier input
voltage. It is noted that the zero level of the rectifier input
voltage is defined as the neutral point voltage of the DC
output part. Five-step stairs waveform is obtained as therectifier input voltage, which is divided into six sectors by
voltage levels.
Table II indicates the switching pattern table of the
proposed rectifier. For example, in the sector II, when therectifier input voltage is +Vdc/2 or +Vdc/4, if the inner
clamping capacitor voltage Vc is lower than its command Vc*,
the charge mode (S2 and S4 are turned on) will be selected. On
the other hand, if Vc is higher than Vc*, the discharge mode (S1and S3 are turned on) will be selected. Thus, the inner
clamping capacitor voltage can be controlled constantly at all
sectors.
Additionally, the neutral point voltage of the DC part iscontrolled by the zero levels as the same as a conventional
three-level inverter. The zero level output switching pattern isselected by the input voltage polarity. When the input voltage
is positive, the +0 is selected for the zero level to increase theneutral point voltage. On the other hand, the –0 is selected
when the input voltage is negative to decrease the neutral
point voltage. As a result, the DC part capacitor (C3) voltage
can be balanced by the zero level selection.
IV. PARAMETER DESIGN METHODA.

Inductance of Input Inductor (Lin)
When the switching frequency is much higher than the
input frequency, the fundamental component of the reactor
voltage assumes constant during a switching cycle. Then, therelation between the input inductor Lin and the input current
ripple ∆iin can be expressed as

Fig. 4. Space vector map.

Fig. 5. Control block diagram for the proposed circuit.

Fig. 6. Rectifier input voltage waveform.
TABLE IISWITCHING TABLE OF THE PROPOSED RECTIFIER
SectorVoltage levelTurn-on switches

I+Vdc/4 , +0

S2-S4 (S1-S3)*, S3-S4

II+Vdc/2 , +Vdc/4

S1-S2, S2-S4 (S1-S3)*

III+Vdc/4 , +0

S2-S4 (S1-S3)*, S3-S4

IV–0 , –Vdc/4

S1-S2 , S1-S3 (S2-S4)*

V–Vdc/4 , –Vdc/2

S1-S3 (S2-S4)*, S3-S4

VI–0 , –Vdc/4

S1-S2 , S1-S3 (S2-S4)**

Charge (Discharge) mode∆iin =

wherevα
1 α / f sw
v L dt = L
Lin ∫0
Lin f sw

(4)

∆Vconv Vv L = Vm sin ωt −  dc +
 (0 ≤ ωt ≤ π / 6)
2 
 4

C.

∆Vconv Vv L = Vm sin ωt −  dc + (π / 6 < ωt ≤ π / 2)2 
 2

where fsw is the carrier frequency, ∆Vconv is the input
voltage ripple of the rectifier, Vm is the peak voltage of the
input phase voltage.
The duty ratio α for each section is defined as (5) because
the rectifier voltage command is a sinusoidal waveform.
 α = 2 sin ωtα = 2(sin ωt − 0.5)

( 0 ≤ ωt ≤ π / 6 )(π / 6 < ωt ≤ π / 2)

(5)

Fig. 7 shows the value of vLα when Vm and ∆Vconv aredefined to 1 p.u. and 0, respectively. Since the input current
ripple is dominated by vLα, the input current ripple ∆iin
becomes the maximum value at the duty ratio of 0.5 when the
DC voltage Vdc is 1 p.u. Then the input phase angles ωt aresin-1(1/4), or sin-1(3/4). Note that if the DC voltage is changed,
the peak position of vLα is only shifted to right and the peakvalue does not change as shown in Fig. 7. Consequently, themaximum input current ripple ∆iin can be expressed as∆VconvV
3
1∆iin = Vm sin(sin −1 ) − ( dc +)42
2
2 Lin f sw=

∆VconvV
3
1)
Vm − ( dc +42
2
2 Lin f sw

where ∆iin is the ripple current.
As shown in (10), the capacitance of C1 can be reduced byincreasing the switching frequency and the allowance voltage
ripple ∆Vc.

(6)

Capacitance of DC part Capacitor (C3)
At first, the quantity of the electric charge flowing into theneutral point should be calculated in order to design thecapacity of C3. The relation between the voltage level and thecurrent flowing into the neutral point is shown in Table III. It
is noted that the selected switching pattern depends on thephase angle of the input voltage. For example, the quantity ofthe electric charge which flowing into the neutral point from
R phase is expressed as following equations.
Qc 3 _ 0− 30 = ∫I m sin ωt ( D0 _ 0 −30 +Qc 3 _ 30 −60 = ∫Ts / 6Ts / 12I m sin ωt (DVdc / 4 _ 0 −30
2DVdc / 4 _ 30 −60
2

) dt

)dt

(11)
(12)

where Ts is a period of the input voltage, Imsinωt is the input
current of R-phase, D is the duty ratio. The subscripts indicate
the voltage level and the phase angle of the input voltage. It
should be noted that duty ratio for 0 to 30° on Vdc/4 level isused as a half of the original value because almost half of thisperiod does not flow the current into the neutral point.
The rectifier voltage command is formed in sinusoidal, andthen it can be defined as 100% at 0° and 0% at 30° at zero
output voltage level. At Vdc/4 output voltage level, therectifier voltage command can be defined as 100% at 30° and
0% at 90°. Consequently, the duty ratio of each area can be
expressed as

Therefore, Lin can be designed by∆VconvV
3
1)
Lin = Vm − ( dc +42
22∆iin f sw

Ts / 120

D0 _ 0−30 = 1 − 2 sin ωt

(13)

(7)

Thus, the input reactor can be reduced by increasing thecurrent ripple ∆iin and the switching frequency fsw.
B.

Capacitance of Inner Clamping Capacitor (C1)
The output voltage variations of the proposed circuit are±Vdc/2, ±Vdc/4, and 0. Note that ±Vdc/4 levels are outputtedthrough the inner clamping capacitor C1. The maximum
output time of ±Vdc/4 levels can be expressed as

0.15
0.1
0.05
0

Tsw _ max = 1 / f sw

(8)Consequently, the maximum voltage ripple of C1 is given by∆Vc =iin _ peak
1 Tsw _ max iin _ peak
dt =
∫
0
C1
2
2C1 f sw

(9)

where iin_peak is the peak of the input current.
Practically, the peak current includes the ripple
components. Therefore, the capacitance of C1 is decided by(10) from (9).
C1 =(iin _ peak / 2) + ∆iin
∆Vc f sw

(10)

Fig. 7. Input current ripple ∆iin and phase angle of input voltage.

TABLE III Voltage levels and connection to neutral point
Phase angle ofCurrent to neutral
Voltage level
input voltage
point0
Active0-30°+Vdc/4
Active/inactive(C1 Charge / Discharge)+Vdc/4
Active/inactive(C1 Charge / Discharge)
30-60°+Vdc/2
ActiveDVdc / 4 _ 0−30 = 2 sin ωt(14)

DVdc / 4 _ 30−60 = 2(1 − sin ωt )(15)

The quantity of the electric charge Qnp from 0 to 60° region
can be expressed by (16).
Qnp = 2(Qc 3 _ 0−30 + Qc 3 _ 30−60 )(16)flowing into the neutral point (Qnp), as expressed by (23).
∆Vnp =

Qin _ R = ∫ I m sin (ωt )dt
=
Ts
12
0

Qin _ T = ∫
=

Im 
ωT

 − cos s + 1
ω
12


4 

I m sin  ωt − π  dt
3 


Im 
4  1
 ωT
 − cos s − π  + ω 
 12 3  2 

(17)

C2 =

Qout is the quantity of the electric charge which is supplied to
the load.
Qout =

I load Ts
12(19)where Qout is the DC output current.
Therefore, the quantity of the electric charge which flowing
into the neutral point at the interval of Ts/12 is expressed as∆QC 3 = 2(Qin _ R + Qin _ T ) − 3Qnp − Qout=ωT
I m  37 3ωTs
 ωT 4 − 19 cos s − cos s − π  (20)
 −
4
12
ω 2
 12 3 
+

3
ωT
sin s
2
6

=

 I load Ts
−
12


∆i
1
(3 in + 2∆QC 3 )
C2
f sw

=

∆i
1
(3 in + ∆QC 3 )
∆Vdc
f sw
I
74 − 33 3 − 6π 0.02 I load 
1  ∆iin+ m−
3∆Vdc  f sw 100π
4
12 

− C3

I m 
π 9 3 
6− −

6 
2
4 
2∆Vnp − ∆Vdc

(24)
− C3

SIMULATION RESULT

VI. EXPERIMENTAL RESULT
Fig. 10 shows the operation waveforms for the proposed
TABLE IVSIMULATION PARAMETERS OF THE PROPOSED RECTIFIER
Output power

1 [kW]

Input voltage

200 [V]DC output voltage command (Vdc*)

320 [V](22)

Load resistance(RL)

100 [Ω]

Inner clamping capacitor(C1)47 [µF]

Clamping capacitor(C2)100 [µF]

DC part capacitor(C3)220 [µF]

Carrier frequency

10 [kHz]As shown in (22), the capacity of C3 can be reduced byincreasing voltage ripple ∆Vdc and the switching frequency fsw.
Capacitance of Clamping Capacitor (C2)
The capacitance of C2 depends on the voltage fluctuationof the neutral point voltage of the DC link part. The relation
between the voltage ripple of the neutral point ∆Vnp and C2
can be calculated from the quantity of the electric charge
D.

Qnp
2∆Vnp − ∆Vdc

(21)

Finally, the capacitance of C3 can be calculated. Note that
ωTs/12 is equal to π/6.
C3 =

(23)

Table IV show the simulation parameters. Fig. 8 show thesimulation results of the proposed rectifier at 50 Hz input
frequency. Clean sinusoidal input current waveforms wereobtained, and the total harmonic distortion (THD) for the
input current was 2.6%. However, there is a distortion at thezero-cross point of the input current. The reason of the
distortion is a phase shift of the input current depends on the
input inductor. The DC output voltage agreed with its
command of 320 V. In addition, the switching voltage of eachswitching device is reduced to 80 V, that is, Vdc/4.
Fig. 9 show the simulation results of the proposed
rectifier. The simulation parameters at 800 Hz input
frequency is used in Table IV. This condition is supposed toapply aircraft power supply systems. The sinusoidal input
current waveforms are obtained, and the total harmonic
distortion (THD) for the input current was 1.5%. The validlyof the design method is confirmed by these simulation results.

Next, the DC output voltage ripple ∆Vdc can be expressed as(21) with the input current ripple ∆iin .
∆Vdc =∆Vdc
2

As shown in (24), the capacitance of C2 can be reduced byincreasing the voltage ripple of neutral point ∆Vnp.
V.

(18)

+

As a result, the capacitance of C2 can be calculated by (24)from (23).

On the other hands, the DC output voltage ripple is generated
at six times of the input voltage frequency. Then, themaximum quantity of the rectifier input electric charge (Qin_R,
Qin_T) can be expressed by (17), (18) for a half cycle of theoutput voltage ripple, i.e. Ts/12.
Ts
12
0

Qnp
2(C 2 + C3 )50 [Hz]

800 [Hz]

Input inductor (Lin)2 [mH]

Carrier frequency

50 [kHz]

Input inductor (Lin)1 [mH]

rectifier. The input voltage is 200 V, 50 Hz, the output poweris 1 kW (rating), and the DC output voltage command is set to
320 V, that is, the inner clamping capacitor voltage commandis set to 80 V (the circuit parameter is the same as Table IV).
Clean sinusoidal input current waveforms were obtained andthe THD of that was 3.4% (the 40th or less order components
harmonics were considered). In addition, the DC output
voltage and the inner clamping capacitor voltage agreed withcommands of that respectively. In Fig. 10, a five-step voltage
waveform is observed in the rectifier input voltage of the
proposed converter, which agrees with the expectation. Itshould be noted that the spike voltage in the rectifier input
voltage is caused by the commutation of the diode at the edgeof the sectors. However, the each switching device voltage isclamped by the inner or outer clamping capacitor. Therefore,
the low voltage rating switching device can be used.
Fig. 11 shows the efficiency and input power factor of the
proposed rectifier. The maximum efficiency is 97.6% at a 0.5
kW load, and an input power factor of over 98% wasachieved at over 0.5 kW load. The proposed circuit canobtain efficiency of over 97% in a wide load condition
because the switching frequency of the outer diode is thesame as the power grid frequency even if that of the innerswitching device is high.
Fig. 12 shows the input current THD of the proposed
rectifier. The proposed rectifier achieved 3.4% THD for the
input current. It should be noted that the THD increase in thelight load condition because the magnitude of the harmonics
component is almost constant. Therefore, the ratio between
the fundamental and harmonics component becomes larger inthe light load condition
Fig. 13 illustrates the loss analysis result for 1 kW load.
The power loss is composed by linking a circuit simulator(PSIM, Powersim Technologies Inc.) and a DLL (Dynamic
Link Library) file. The DLL file has a loss table regarding theswitching and conduction losses based on the instantaneous
values of the current and the voltage of the power device, as
written in [11]. This method can estimate the power
semiconductor loss, regardless of the circuit configuration.
The loss simulation results are in good agreement with theefficiency of experimental results. In the proposed circuit, theconduction loss is the most dominant section of the power
losses. In order to improve efficiency, a low conduction loss
device should be selected.

Fig. 8. Simulation result of the proposed rectifier.(50Hz)

VII. CONCLUSIONS
A novel five-level PWM rectifier and its control strategy
were proposed. Features of the proposed circuit are thereduction in the number of switching devices, and acontrollable clamping capacitor voltage. The proposed
converter achieved 3.4% THD for the input current at 1 kWload and 97.6% efficiency at 0.5 kW load for a 1 kW classexperimental setup.

Fig. 9. Simulation result of the proposed rectifier.(800Hz)

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Fig. 11. Input power factor and efficiency of the proposed rectifier.

Input voltage [250V/div]0
Fig. 12. Input current THD of the proposed rectifier.

0
Input current [5A/div]0

DC output voltage [250V/div]0

Inner clamping capacitor (C1) voltage [100V/div]

10ms

0
Rectifier input voltage [250V/div]
Fig. 10. Experimental results of the proposed rectifier at 1 kW.

Fig. 13. Loss analysis results by loss simulation at 1 kW load.