REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVEDA

Add device type 02. Update boilerplate paragraphs to current requirements. PHN
Update boilerplate paragraphs to current VID description requirements. - DRH

13-05-28

Thomas M. Hess

22-09-26

Muhammad A. Akbar

B

CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

Prepared in accordance with ASME Y14.24

Vendor Item Drawing

Revision Status of Sheets
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PMIC N/A
Original date ofdrawing
08-10-21

PREPARED BY
Phu H. Nguyen
CHECKED BY
Phu H. Nguyen

TITLE

APPROVED BY
Thomas M. HessSIZE
CAGE CODEA
REVAMSC N/A

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
https://www.dla.mil/landandmaritime

16236
B

MICROCIRCUIT, DIGITAL, QUAD CHANNEL,
14 BIT, 125 MSPS ADC WITH SERIAL LVDSOUTPUT, MONOLITHIC SILICONDWG NO.

PAGE

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

V62/08628
1 OF 205962-V115-22

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance quad channel, 14 bit, 125 MSPS ADC with serial
LVDS outputs microcircuit for device type 01 and a quad channel, 14 bit, 105 MSPS ADC with serial LVDS outputs microcircuit for
device type 02, with an operating temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/08628-

Drawing
number

01

X

A

Device type
(See 1.2.1)

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic

Circuit function

01
02

ADS6445-EP
ADS6444-EP

Quad channel, 14 bit, 125 MSPS ADC with serial LVDS outputs
Quad channel, 14 bit, 105 MSPS ADC with serial LVDS outputs

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

Package style

X

64

Plastic quad flatpack

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

Material

A
B
C
D
E
Z

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Other

1.3 Absolute maximum ratings. 1/
Supply voltage range:
ADVDD .................................................................................................................. -0.3 V to 3.9 V
LVDD ..................................................................................................................... -0.3 V to 3.9 V
Voltage between AGND and DGND .............................................................................. -0.3 V to 0.3 V
Voltage between AVDD to LVDD .................................................................................. -0.3 V to 3.3 V
Voltage applied to external pin, VCM ............................................................................ -0.3 V to 2.0 V
Voltage applied to analog input pins .............................................................................. -0.3 V to minimum (3.6, AVDD + 0.3) V
Operating junction temperature range, TJ ..................................................................... 150°C
Storage temperature range, TSTG .................................................................................. -65°C to 150°C
Lead temperature 1.6 mm (1/16”) from the case for 10 seconds .................................. 220°C__________
1/

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.

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PAGE 2

1.4 Thermal characteristics.
Case outline X

Units

Junction to ambient thermal resistance, θJA 3/

23.6

°C/W

Junction to case (top) thermal resistance, θJCtop 4/

7.7

Junction to board thermal resistance, θJB 5/

3

Junction to top characterization parameter, ΨJT 6/

0.1

Junction to board characterization parameter, ΨJB 7/

3

Junction to case (bottom) thermal resistance, θJCbot 8/

0.3

Thermal metric 2/

1.5 Recommended operating conditions.
SUPPLIES
Analog supply voltage, AVDD ................................................................................ 3.0 V to 3.6 V
LVDS buffer supply voltage, LVDD ......................................................................... 3.0 V to 3.6 V
ANALOG INPUTS
Differential input voltage range ............................................................................... 2.0 VP-P TypicalInput common-mode voltage .................................................................................. 1.5 V ±0.1 Typical
Voltage applied on VCM in external reference mode ............................................. 1.45 V to 1.55 V
CLOCK INPUTS
Input clock sample rate, Fsrated:
Device type 01 ................................................................................................... 5 to 125 MSPS
Device type 02 ................................................................................................... 5 to 105 MSPS
Input clock amplitude differential (VCLKP – VCLKM):
Minimum sine wave, ac coupled ....................................................................... 0.4 VP-P
LVPECL, ac coupled ......................................................................................... ±0.8 VP-P Typical
LVDS, ac coupled ............................................................................................. ±0.35 VP-P Typical
LVCMOS, ac coupled ........................................................................................ 3.3 VP-P TypicalInput clock duty cycle ............................................................................................. 35% to 65%
DIGITAL INPUTS
Maximum external load capacitance from each output pin to DGND, CLOAD:
Without internal termination ............................................................................... 5 pF TypicalWith internal termination ................................................................................... 10 pF TypicalDifferential load resistance (external) between the LVDS output pairs, RLOAD ....... 100 Ω Typical__________
2/
3/
4/
5/
6/
7/
8/

For more information about traditional and new thermal metrics, see manufacturer data.
The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-Kboard, as specified in JESD51-7, in an environment described in JESD51-2a.
The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the
PCB temperature, as described in JESD51-8.
The junction to top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction to board characterization parameter, ΨJB, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No
specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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PAGE 3

2. APPLICABLE DOCUMENTS
SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)JEP 95JESD 51JESD 51-2a
JESD 51-7
JESD 51-8

–
–
–
–
–

Registered and Standard Outlines for Semiconductor Devices
Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device).
Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still Air)High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Integrated Circuits Thermal Test Method Environment Conditions – Junction-to-board(Copies of these documents are available online at https://www.jedec.org.)AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD
ANSI SEMI STANDARD G30-88– Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic
Packages(Copies of these documents are available online at https://www.ansi.org.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as
specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Terminal description. The terminal description shall be as shown in figure 3.
3.5.4 Functional block diagram. The functional block diagram shall be as shown in figure 4.
3.5.5 Latency. The latency shall be as shown in figure 5.
3.5.6 LVDS timing. The LVDS timing shall be as shown in figure 6.
3.5.7 Reset timing. The Reset timing shall be as shown in figure 7.
3.5.8 Serial interface timing. The serial interface timing shall be as shown in figure 8.

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PAGE 4TABLE I. Electrical performance characteristics. 1/ 2/
Test

SymbolDevice type 01
Fs = 125 MSPS
Min
TYP
14

Max
Resolution
Analog input
Differential input voltage range
2.0
Differential input capacitance7
Analog input bandwidth
500
Analog input common mode current (per input155
pin of each ADC)
Reference voltages
Internal reference bottom voltage
VREFB
1.0
Internal reference top voltage
VREFT
2.0
Internal reference error (VREFT-VREFB)
∆VREF
0.985
1
1.015
Common mode output voltage
VCM
1.5
VCM output current capability±4
DC accuracy
No missing code
AssuredOffset error, across devices and across
EO
-15
±2
15
channels within a device
Offset error temperature coefficient, across
0.05
devices and across channels within a device
There are two source of gain error – internal reference inaccuracy and channel gain error
Gain error due to internal reference inaccuracy
EGREF
-0.75
0.1
0.75
alone, (∆VREF /2.0)%
Reference gain error temperature coefficient
0.0125Gain error of channel alone, across devices and
EGCHAN±0.3
across channels within a device
Channel gain error temperature coefficient,
0.005
across devices and across channels within adeviceDifferential nonlinearity, Fin = 50 MHz
DNL
-0.99
±0.6
2.0
Integral nonlinearity, Fin = 50 MHz
INL
-5
±3
5
DC power supply rejection ratio
PSRR
0.5
Power supply
Total supply current
ICC
502
Analog supply current
IAVDD
410
LVDS supply current
ILVDD
92
Total power
1.65
1.8Power down (within input clock stopped)
77
150
See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
A

Device type 02
Fs = 105 MSPS
Min
TYP
14

0.985

-15

Unit
Max

2.0
7
500
130

VPP
pF
MHz
µA

1.0
2.0
1
1.5
±4

1.015

V
V
V
V
mA

15

mV

Assured
±2
0.05

-0.75

-0.99
-5

Bits

mV/°C

0.1

0.75

%FS

0.0125
±0.3

∆%/°C
%FS

0.005

∆%/°C

±0.6
±3
0.5
410
322
88
1.35
77

2.0
5

1.5
150

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PAGE 5

LSB
LSB
mV/V
mA
mA
mA
W
mW

TABLE I. Electrical performance characteristics – Continued.
Test

SymbolConditions 2/
unless otherwise specified

Dynamic AC characteristics
Signal to noise
SNR
Fin = 10 MHz
ratio
Fin = 50 MHz
Fin = 70 MHz
Fin = 100 MHz
Fin = 170 MHz
Fin =230 MHz
Signal to noiseand distortion
ratio

SINAD

Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
Fin = 100 MHz
Fin = 170 MHz
Fin =230 MHz

Output noise

RMS

Spurious freedynamic range

SFDR

Inputs tied tocommon-mode
Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
Fin = 100 MHz
Fin = 170 MHz
Fin =230 MHz

Secondharmonic

HD2

Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
Fin = 100 MHz
Fin = 170 MHz
Fin =230 MHz

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

Device type 01
Fs = 125 MSPS
Min
TYP

68.5

0 dB gain
3.5 dB Coarse gain
0 dB gain
3.5 dB Coarse gain
67.75

0 dB gain
3.5 dB Coarse gain
0 dB gain
3.5 dB Coarse gain

69

0 dB gain
3.5 dB Coarse gain
0 dB gain
3.5 dB Coarse gain
69

0 dB gain
3.5 dB Coarse gain
0 dB gain
3.5 dB Coarse gain

SIZE
A

Max

73.7
73.1
72.7
72.1
69.9
69.4
68.7
68.1
73.4
72.3
71.2
71.8
67.9
68.3
67.8
67.9
1.05
87
81
78
86
76
79
77
80
93
87
87
89
83
85
80
82

Device type 02
Fs = 105 MSPS
Min
TYP

69

68.5

74

74

Unit
Max

73.8
73.2
73
72.2
70.2
69.7
68.8
68.2
73.4
71.7
72
72
69.8
69.3
67.7
67.6
1.05

dBFS

91
80
81
88
79
83
77
80
94
88
88
90
84
86
81
83

dBc

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PAGE 6

dBFS

LSB

dBc

TABLE I. Electrical performance characteristics – Continued.
Test

SymbolConditions 2/
unless otherwise specified

Dynamic AC characteristics - continued
Third harmonic
HD3
Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
Fin = 100 MHz
Fin = 170 MHz
Fin =230 MHz
Worst harmonic(other thanHD2, HD3)

Total harmonic
distortion

THD

Effective
number of bits
2-Tone intermodulation
distortion

ENOB

Cross talk

IMD

Fin = 10 MHz
Fin = 50 MHz
Fin = 100 MHz
Fin = 170 MHz
Fin = 230 MHz
Fin = 10 MHz
Fin = 50 MHz
Fin = 100 MHz
Fin = 170 MHz
Fin = 230 MHz
Fin = 50 MHz
Fin = 70 MHz
F1 = 46.09 MHz,F2 = 50.09 MHz
F1 = 185.09 MHz,F2 = 190.09 MHz

69

0 dB gain
3.5 dB Coarse gain
0 dB gain
3.5 dB Coarse gain

69

10.95

Max

87
81
78
86
76
79
77
80
91
87
90
88
87
86
80
84.5
73.5
74
11.7
88

Near channel Cross
talk signal
frequency = 10 MHz

Far channel Cross
talk signal
frequency = 10 MHz
Input overload
Recovery to withinrecovery
1% (of final value)for 6-dB overloadwith sine wave input
Power supply
AC PSRR < 100 MHz signal,
rejection ratio
100 mVPP on AVDD
supplySee footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

Device type 01
Fs = 125 MSPS
Min
TYP

SIZE
A

Device type 02
Fs = 105 MSPS
Min
TYP

74

72

11.3

Unit
Max

91
80
81
88
79
83
77
80
91
87
91
88
87
89.5
80
79
86
77
11.7
90

dBc

dBc

dBc

Bits
dBFS

86

88

90

92

103

105

1

1

Clock
cycles

35

35

dBc

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PAGE 7dBc

TABLE I. Electrical performance characteristics – Continued.
Test

Digital inputs
High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance
Digital outputs
High level output voltage
Low level output voltage
Output differential voltage
Output offset voltage

SymbolConditions 3/
unless otherwise specified

Device type 01
Fs = 125 MSPS
Min
TYP
2.4
10
10
4
1375
1025
350
1200

|VOD|
VOS

250
Common mode voltage of
OUTP and OUTM
Output capacitance
Output capacitance inside the2device, from either output togroundTIMING SPECIFICATIONS 5/ 6/
Aperture jittertJ
Uncertainty in the sampling250
instant
Interface: 2-wire, DDR bit clock, 14x serialization
Data setup time
tsu
From data cross over to bit
0.55
8/ 9/ 10/clock cross over
Data hold timeth
From bit clock cross over to
0.58
8/ 9/ 10/
data cross over
Clock propagation delay
tpd_clk
Input clock rising edge cross
4.4
10/
over to frame clock rising edge
cross overBit clock cycle-cycle jitter
350
9/
Frame clock cycle-cycle
75
jitter 9/
See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
A

Max

0.8

450

Device type 02
Fs = 105 MSPS
Min
TYP
2.4
10
10
4

250

1375
1025
350
1200

Unit
Max

0.8

450

V
V
µA
µA
pF
mV
mV
mV
mV

2

pF

250

fs ms

0.65

ns

0.7

ns

4.4

ns

350

ps pp

75

ps pp

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PAGE 8TABLE I. Electrical performance characteristics – Continued.
Test

SymbolConditions 3/
unless otherwise specified

Device type 01
Fs = 125 MSPS
Min
TYP
Max
The following specifications apply for 5 MSPS ≤ Fs ≤ 125 MSPS and all interface options
Aperture delaytA
Delay from input clock rising
2edge to the actual sampling
instant
Aperture delay variation
Channel-channel within same±80
device
ADC latency 11/
Time for a sample to propagate
12
to ADC outputs,
See FIGURE 5
Wake up time
Time to valid data after coming
100
out of global power down
Time to valid data after input
100
clocks is re-started
Time to valid data after coming
200
out of channel standby
Data rise timetRISE
From -100 mV to +100 mV
100
Data fall time
tFALL
From +100 mV to -100 mV100
Bit clock and frame clocktRISE
From -100 mV to +100 mV
100
rise time
Bit clock and frame clocktFALL
From +100 mV to -100 mV
100
fall time
LVDS bit clock duty cycle
50%
LVDS frame clock duty
50%
cycle
See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
A

Device type 02
Fs = 105 MSPS
Min
TYP

Unit
Max

2

ns

±80

ps

12

Clock
cycles

100

µs

100

µs

200

Clock
cycles
ps

100
100
100
100
50%
50%

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PAGE 9TABLE I. Electrical performance characteristics – Continued.
Test

SCLK frequency, fSCLK = 1/tSCLKSEN to SCLK setup time
SCLK to SEN hold time
SDATA setup time
SDATA hold time
Time taken for register write to takeeffect after 16th SCLK falling edge

SymbolConditions 12/
unless otherwise specified

Devicetype

SERIAL INTERFACE TIMING CHARACTERISTICS
fSCLK
All
tSLOADStSLOADHtDSUtDH

Power on delay time

t1

Reset pulse widtht2

Register writer delay timet3

Power up delay timetPO

RESET TIMING
Delay from power-up of AVDD and
LVDD to RESET pulse active
Pulse width of active RESET
signalDelay from RESET disable to SEN
activeDelay from power-up of AVDD and
LVDD to output stable

All

Limits
Min
>DC

TYP

25
25
25
25
100

Unit
Max
20

MHz
ns

5

ms

10

ns

25

ns

6.5

ms

1/

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may notnecessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
2/ Typical values are at 25°C, min and max values are across the full junction temperature range TJ,MIN = -55°C to TJ,MAX = 125°C,
AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, -1 dBFS differential analog input, internalreference mode (unless otherwise noted).
3/ The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0
or 1 AVDD = LVDD = 3.3 V, IO = 3.5 mA, RLOAD = 100 Ω 4/. All LVDS specifications are characterized, but not tested at
production.
4/ IO refers to the LVDS buffer current setting; RL is the external differential load resistance between the LVDS output pair.
5/ Timing parameters are ensured by design and characterization and not tested in production.
6/ Typical values are at 25°C, min and max values are across the full junction temperature range TJ,MIN = -55°C to TJ,MAX = 125°C,
AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 Vpp clock amplitude, CL = 5 pF 7/, IO = 3.5
mA, RL = 100 Ω 4/, no internal termination, unless otherwise noted.
7/ CL is the external single ended load capacitance between each output pin and ground.
8/ Timing parameters are measured at the end of a 2 inch PCB trace (100 Ω characteristic impedance) terminated by RL and CL.
9/ Setup and hold time specifications take into account the effect of jitter on the output data and clock.
10/ Refer to output timing application section in manufacturer data for timing at lower sampling frequencies and other interface options.
11/ Note that the total latency = ADC latency + internal serialized latency. The serialized latency depends on the interface option
selected as in manufacturer data.
12/ Typical values are at 25°C, min and max values are across the full junction temperature range TJ,MIN = -55°C to TJ,MAX = 125°C,
AVDD = LVDD = 3.3 V, unless otherwise noted.

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PAGE 10Case X

SymbolA
A1
A2b

Dimension
Millimeters
Symbol
Min
Max

Min

0.80
1.00
0.20 REF
0.00
0.05
0.18
0.30

0.30
0.50
8.85
9.15
7.50 REF
0.50 BSC

b1
D/E
D1/E1
e1

MillimetersMax

NOTES:
1. All linear dimensions are in millimeters. Dimensioning and tolerance per ASME Y14.5 – 1994.
2. This drawing is subject to change without notice.
3. Quad flatpack, No-leads (QFN) package configuration.
4. The package thermal pad must be soldered to the board for thermal and mechanical performance. See manufacturer data for
details regarding the exposed thermal pad dimensions.
FIGURE 1. Case outline.

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PAGE 11Case X (2-Wire interface)Terminal
number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Terminal
symbol
DA1_P
DA1_M
DA0_P
DA0_M
CAP
RESET
LVDD
AGND
AVDD
AGND
INA_M
INA_P
AGND
INB_M
INB_P
AGND

Terminal
number
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Terminal
symbol
AVDD
AGND
AVDD
NC
CFG4
VCM
AGND
CLKP
CLKM
AGND
AVDD
CFG3
CFG2
CFG1
AGND
AVDD

Terminal
number
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

Terminal
symbol
AGND
INC_P
INC_M
AGND
IND_P
IND_M
AGND
AVDD
PDN
SEN
SDATA
SCLK
DD1_P
DD1_M
DD0_P
DD0_M

Terminal
number
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

Terminal
symbol
LVDD
DC1_P
DC1_M
DC0_P
DC0_M
LGND
FCLKP
FCLKM
DCLKP
DCLKM
LGND
DB1_P
DB1_M
DB0_P
DB0_M
LVDD

Terminal
symbol
AGND
INC_P
INC_M
AGND
IND_P
IND_M
AGND
AVDD
PDN
SEN
SDATA
SCLK
UNUSED
UNUSED
UNUSED
UNUSED

Terminal
number
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

Terminal
symbol
LVDD
DD_P
DD_M
DC_P
DC_M
LGND
FCLKP
FCLKM
DCLKP
DCLKM
LGND
DB_P
DB_M
DA_P
DA_M
LVDD

Case X (1-Wire interface)Terminal
number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Terminal
symbolUNUSED
UNUSED
UNUSED
UNUSED
CAP
RESET
LVDD
AGND
AVDD
AGND
INA_M
INA_P
AGND
INB_M
INB_P
AGND

Terminal
number
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Terminal
symbol
AVDD
AGND
AVDD
NC
CFG4
VCM
AGND
CLKP
CLKM
AGND
AVDD
CFG3
CFG2
CFG1
AGND
AVDD

Terminal
number
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

FIGURE 2. Terminal connections.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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PAGE 12

Pin Assignments (2-Wire interface)Terminal
Name
Number
Supply and ground Pins
AVDD
9, 17, 19,
27, 32, 40
AGND
8,10, 13
16, 18, 23
26, 31, 33
36, 39LVDD
7, 49, 64
LGND
54, 59Input pins
CLKP,
24, 25
CLKM
INA_P,
12, 11
INA_M
INB_P,
15, 14
INB_M
INC_P,
34, 35
INC_M
IND_P,
37, 38
IND_M
CAP
5
SCLK
44

I/O

No. ofpins
6

Analog power supply

11

Analog ground3
2

Digital power supply
Digital groundI

2

Differential input clock pair

I

2

I

2

I

2

I

2

I
I

1
1

Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do not
float
Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do not
float
Differential input signal pair, channel C. If unused, the pins should be tied to VCM. Do not
float
Differential input signal pair, channel D. If unused, the pins should be tied to VCM. Do not
float
Connect 2-nF capacitor from pin to ground
This pin functions as serial interface clock input when RESET is low. When RESET ishigh, it controls DESKEW, SYNC and global POWER DOWN modes (along with SDATA).
Refer to manufacturer data for description. This pin has an internal pull-down resistor
This pin functions as serial interface data input when RESET is low. When RESET ishigh, it controls DESKEW, SYNC and global POWER DOWN modes (along with SCLK).
Refer to manufacturer data for description. This pin has an internal pull-down resistor.
This pin functions as serial interface enable input when RESET is low. When RESET ishigh, it controls coarse gain and internal/external reference modes. Refer to manufacturer
data for description. This pin has an internal pull-up resistor.

SDATA

43

I

1

SEN

42

I

1

RESET

6

I

1

PDN
CFG1

41
30

Description

I
I

Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers throughhardware RESET by applying a high-going pulse on this pin or by using software reset
option. Refer to the Serial Interface section in manufacturer data. In parallel interface
mode, tie RESET permanently high. (SCLK, SDATA and SEN function as parallel control
pins in this mode). The pin has an internal pull-down resistor to ground.
Global power down control pin.
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection.
Refer to manufacturer data for description. Tie to AVDD for 2-wire interface with DDR bit
clock.

1
1

FIGURE 3. Terminal description (2 wire interface).

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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REV B

PAGE 13

Pin Assignments (2-Wire interface) – Continued.
Terminal
Name
NumberInput pins- Continued
CFG2
29

I/O

No. ofpins

Description

I

1

Parallel input pin. It controls 14x or 16x serialization and SDR bit clock capture edge. Referto manufacturer data for description. For 14x serialization with DDR bit clock, tie to groundor AVDD.
RESERVED pin - Tie to ground.
Parallel input pin. It controls data format and MSB or LSB first modes. Refer tomanufacturer data for description
Internal reference mode – common-mode voltage output. External reference mode –reference input. The voltage forced on this pin sets the internal reference.

CFG3
CFG4

28
21

I
I

1
1

VCM

22

I/O

1

DA0_P,
DA0_M

3, 4

O

2

Channel A differential LVDS data output pair, wire 0

DA1_P,
DA1_M

1, 2

O

2

Channel A differential LVDS data output pair, wire 1

DB0_P,
DB0_M

62, 63O

2Channel B differential LVDS data output pair, wire 0

DB1_P,
DB1_M

60, 61O

2Channel B differential LVDS data output pair, wire 1

52, 53O

2Channel C differential LVDS data output pair, wire 0

50, 51O

2Channel C differential LVDS data output pair, wire 1

47, 48O

2Channel D differential LVDS data output pair, wire 0

45, 46O

2

Channel D differential LVDS data output pair, wire 1

57, 58O2

Differential bit clock output pair

55, 56O

2

Differential frame clock output pair

1
1

Do Not Connect
Connect to ground plane using multiple vias. Refer to Board Design consideration in
manufacturer data section.

Output pins

DC0_P,
DC0_M
DC1_P,
DC1_M
DD0_P,
DD0_M
DD1_P,DD1_M
DCLKP,DCLKM
FCLKP,
FCLKM
NC
PAD

20
0

FIGURE 3. Terminal description (2 wire interface) - Continued.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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PAGE 14

Pin Assignments (1-Wire interface)Terminal
Name
Number
Supply and ground Pins
AVDD
9, 17, 19,
27, 32, 40
AGND
8,10, 13

LVDD
LGND
Input pins
CLKP,
CLKM
INA_P,INA_M
INB_P,
INB_M
INC_P,
INC_M
IND_P,
IND_M
CAP
SCLK

I/O

16, 18, 23
26, 31, 33
36, 397, 49, 64
54, 59No. ofpins

Description

6

Analog power supply

11

Analog ground3
2

Digital power supply
Digital ground24, 25I

2

Differential input clock pair

12, 11I

2

15, 14I

2

34, 35I

2

37, 38

I

2

5
44

I
I

1
1

SDATA

43

I

1

SEN

42

I

1

RESET

6

I

1

Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do not
float
Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do not
float
Differential input signal pair, channel C. If unused, the pins should be tied to VCM. Do not
float
Differential input signal pair, channel D. If unused, the pins should be tied to VCM. Do not
float
Connect 2-nF capacitor from pin to ground
This pin functions as serial interface clock input when RESET is low. When RESET ishigh, it controls DESKEW, SYNC and global POWER DOWN modes (along with SDATA).
Refer to manufacturer data for description. This pin has an internal pull-down resistor
This pin functions as serial interface data input when RESET is low. When RESET ishigh, it controls DESKEW, SYNC and global POWER DOWN modes (along with SCLK).
Refer to manufacturer data for description. This pin has an internal pull-down resistor
This pin functions as serial interface enable input when RESET is low. When RESET ishigh, it controls coarse gain and internal/external reference modes. Refer to manufacturer
data for description. This pin has an internal pull-up resistor.

PDN
CFG1

41
30

I
I

1
1

Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers throughhardware RESET by applying a high-going pulse on this pin or by using software reset
option. Refer to the Serial Interface section in manufacturer data. In parallel interface
mode, tie RESET permanently high. (SCLK, SDATA and SEN function as parallel control
pins in this mode). The pin has an internal pull-down resistor to ground.
Global power down control pin.
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection.
Refer to manufacturer data for description. Tie to AVDD for 2-wire interface with DDR bit
clock.

FIGURE 3. Terminal description (1 wire interface) - Continued.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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PAGE 15

Pin Assignments (1-Wire interface) – Continued.
Terminal
Name
NumberInput pins- Continued
CFG2
29

I/O

No. ofpins

Description

I

1

Parallel input pin. It controls 14x or 16x serialization and SDR bit clock capture edge. Referto manufacturer data for description. For 14x serialization with DDR bit clock, tie to groundor AVDD.
RESERVED pin - Tie to ground.
Parallel input pin. It controls data format and MSB or LSB first modes. Refer tomanufacturer data for description
Internal reference mode – common-mode voltage output. External reference mode –reference input. The voltage forced on this pin sets the internal reference.

CFG3
CFG4

28
21

I
I

1
1

VCM

22

I/O

1

DA_P,
DA_M

62, 63O

2Channel A differential LVDS data output pair.

DB_P,
DB_M

60, 61O

2Channel B differential LVDS data output pair.

DC_P,
DC_M

52, 53O

2Channel C differential LVDS data output pair.

DD_P,
DD_M

50, 51O

2Channel D differential LVDS data output pair.

57, 58O2

Differential bit clock output pair

55, 56O

2

Differential frame clock output pair

1
1

These pins are unused in the 1-wire interface. Do not connect
Do Not Connect
Connect to ground plane using multiple vias. Refer to Board Design consideration in
manufacturer data section.

Output pins

DCLKP,DCLKM
FCLKP,FCLKM
UNSUSEDNC
PAD

1-4, 45-48
200

FIGURE 3. Terminal description (1 wire interface) - Continued.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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REV B

PAGE 16

FIGURE 4. Functional block diagram.

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PAGE 17

FIGURE 5. Latency.

FIGURE 6. LVDS timing.

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PAGE 18

FIGURE 7. Reset timing.

FIGURE 8. Serial interface timing.

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REV B

PAGE 19

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicatedin their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification,
packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee ofpresent or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current
sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

1/

Vendor item drawing
administrative control
number 1/

Devicemanufacturer
CAGE code

Vendor part number

Top sidemarking

V62/08628-01XE

01295

ADS6445MRGCTEP

6445EP

V62/08628-02XE

01295

ADS6444MRGCTEP

6444EP

The vendor item drawing establishes an administrative control number for
identifying the item on the engineering documentation.

CAGE code

Source of supply

01295

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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DWG NO.
V62/08628

REV B

PAGE 20