REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVEDA

Update boilerplate paragraphs to current requirements. - PHN

17-06-29

Thomas M. HessB

Update boilerplate paragraphs to current VID description requirements.
- PHN

23-07-25

Muhammad A. Akbar

CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24

Vendor Item Drawing

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PMIC N/A
Original date of drawing
YY MM DD

PREPARED BY
Phu H. Nguyen

Phu H. Nguyen
APPROVED BY
Thomas M. HessSIZE

CAGE CODE

A

REV B

https://www.dla.mil/LandandMaritime

TITLE

CHECKED BY

10-04-06

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO 43218-3990

16236

MICROCIRCUIT, DIGITAL, DIGITAL MEDIASYSTEM ON CHIP (DMSoC), MONOLITHIC
SILICONDWG NO.

PAGE

V62/09643

1 OF 49

AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

5962-V127-23

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance Digital Media System on Chip (DMSoC)
microcircuit, with an operating temperature range of -55ºC to +125ºC.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/09643-

Drawing
number01

X

E

Device type(see 1.2.1)

Case outline(see 1.2.2)

Lead finish(see 1.2.3)

1.2.1 Device type(s).
Device type

Generic

Clock Rat

01

SM320DM355-EP

216 MHzCircuit function
Digital Media System on Chip (DMSoC)

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

Package styleX

337

Plastic ball grid array

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

Material

A
B
C
D
E
F
Z

DLA LAND AND MARITIMECOLUMBUS, OHIO

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy
Other

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PAGE 2

1.3 Absolute maximum ratings.

3/ 4/

Supply voltage ranges:
All 1.3 V supplies ................................................................................................... -0.5 V to 1.7 V
All digital 1.8 V supplies ......................................................................................... -0.5 V to 2.8 V
All analog 1.8 V supplies ........................................................................................ -0.5 V to 1.89 V
All 3.3 V supplies ................................................................................................... -0.5 V to 4.4 V
Input voltage ranges, (VI):
All 1.8 V I/Os .......................................................................................................... -0.5 V to 2.3 V
All 3.3 V I/Os .......................................................................................................... -0.5 V to 3.8 V
VBUS ..................................................................................................................... 0.0 V to 5.5 V
Clamp current for input or output, (Iclamp) .......................................................................... -20 mA to +20 mA
Operating case temperature ranges, (TC):
Device type: 01 ...................................................................................................... -55°C to +125°C
Storage temperature range, (TSTG) .................................................................................... -65°C to +150°C

5/

1.4 Recommended operating conditions. 6/
Supply voltage:
Supply voltage, Core (CVDD) .................................................................................. 1.235 V to 1.365 V
Supply voltage, PLL1 (VDDA_PLL1) ........................................................................... 1.235 V to 1.365 V
Supply voltage, PLL2 (VDDA_PLL2) ........................................................................... 1.235 V to 1.365 V
Supply voltage, USB digital (VDDD13_USB) ................................................................ 1.235 V to 1.365 V
Supply voltage, USB analog (VDDA13_USB) ............................................................... 1.235 V to 1.365 V
Supply voltage, USB analog (VDDA33_USB) ............................................................... 3.135 V to 3.465 V
Supply voltage, USB common PLL (VDDA33_USB_PLL) ............................................... 3.135 V to 3.465 V
Supply voltage, DDR2/MDDR (VDD_DDR) ................................................................ 1.71 V to 1.89 V
Supply voltage, DDR DLL Analog (VDDA33_DDRDLL) .................................................. 3.135 V to 3.465 V
Supply voltage, Digital video in (VDD_VIN) ................................................................ 3.135 V to 3.465 V
Supply voltage, Digital video out (VDD_VOUT) ........................................................... 3.135 V to 3.465 V
Supply voltage, DAC analog (VDDA18_DAC) .............................................................. 1.71 V to 1.89 V
Supply voltage, I/Os (VDD) ...................................................................................... 3.135 V to 3.465 V
Supply ground:
Supply ground, Core, USB digital (VSS) ................................................................. 0 V
Supply ground, PLL1 (VSSA_PLL1) ............................................................................ 0 V
Supply ground, PLL2 (VSSA_PLL2) ............................................................................ 0 V
Supply ground, USB (VSS_USB) ............................................................................... 0 V
Supply ground, DLL (VSSA_DLL) ............................................................................... 0 V
Supply ground, DAC analog (VSSA_DAC) .................................................................. 0 V
MXI1 osc ground, (VSS_MX1) .................................................................................... 0 V
MXI2 osc ground, (VSS_MX2) .................................................................................... 0 V 6/
Supply ground, (VSS) ............................................................................................. 0 V 6/

3/

4/
5/

6/
7/

Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
All voltage values are with respect to VSS.
Clamp current flows from an input or putput pad to a supply rail through a clamp circuit or an intrinsic diode. Positive current
results from an applied input or output voltage that is more than 0.5 V higher (more positive) than the supply voltage,
VDD/VDDA_PLL1/2/VDD_USB/VDD_DDR for dual supply macros. Negative results from an applied voltage that is more than 0.5 V less(more negative) than the VSS voltage.
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground (seemanufacturer data for more details).

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1.4 Recommended operating conditions - Continued.
Minimum high level input voltage, (VIH) ...................................................................... 2.0 V 8/
Maximum low level input voltage, (VIL) ....................................................................... 0.8 V 8/
DAC: 8/DAC reference voltage, (VREF) ........................................................................ 450 TYP mV
DAC full scale current adjust resistor, (RBIAS) .................................................. 2550 TYP Ω
Output resistor, (RLOAD) ................................................................................... 499 TYP Ω
Bypass capacitor, (CBG) .................................................................................. 0.1 TYP µF
Video buffer 9/
Output resistor (ROUT), between TVOUT and VFB pins (ROUT) ..................... 1070 TYP Ω
Feed back resistor, between VFB and IOUT pins, (RFB) ................................. 1000 TYP Ω
DAC full scale current adjust resistor, (RBIAS) .................................................. 2550 TYP Ω
Bypass capacitor, (CBG) .................................................................................. 0.1 µF
USB:
USB external charge pump input (USB_VBUS) .............................................. 4.85 V to 5.25 V
USB reference resistor, (R1) ........................................................................... 9.9 kΩ to 10.1 kΩ
Operating case temperature (TC): 11/
Device type 01 .................................................................................. -55°C to +125°C
Thermal resistance characteristics for case outline X
Junction to caseJunction to board
Junction to free air
Junction to package top
Junction to board

RθJC
RθJB
RθJA
PsiJT
PsiJB

10/

°C/W 12/
7.2
11.4
27.0
0.1
11.3

2. APPLICABLE DOCUMENTSJEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)JEDEC PUB 95
EIA/JESD51-2
EIA/JESD51-3
EIA/JESD51-7

–
–
–
–

Registered and Standard Outlines for Semiconductor Devices
Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still air).
Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages(Copies of these documents are available online at https:/www.jedec.org ).

________
8/
9/
10/
11/
12/

These I/O specifications apply to regular 3.3 V I/Os and do not apply to DDR2/mDDR, USB I/Os are 1.8 V I/Os and adhere toUSB2.0 spec.
See manufacturer data for more information. Also, resistors should be E-96 spec line (3 digits with 1% accuracy).
Connect USB_R1 to VSS_USB_REF via 10 KΩ, 1% resistor placed as close to the device as possible.
To avoid frequency performance device degradation, limit the total device power on hours to less than 16500 hrs at TC = 125°C.
The junction to case measurement was conducted in a JDEC defined 2S2P system and will change based on environment aswell as application. For more information, see three EIA/JEDEC standards: EIA/JEDEC standards: 51-2, 51-3, 51-7.

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3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Block diagram. The block diagram shall be as specified in figure 3.
3.5.4 Test load circuit for AC timing measurement. The test load circuit for AC timing measurements shall be as specified in figure
4.
3.5.5 Timing waveforms. The timing waveforms shall be as shown in figures 4-48.

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PAGE 5TABLE I. Electrical performance characteristics.
Test

Voltage output
Current
Input/Output

Capacitance
DAC

SymbolTest condition

Min
2.4

VOH

DVDD = MIN, IOH = MAX

Low level output voltage 3/

VOL

DVDD = MIN, IOL = MAX

Input current for I/O without internal
pull-up/pull-down
Input current for I/O with internal
pull-up 4/ 5/
Input current for I/O with internal
pull-down 4/ 5/
High level output current

II

VI = VSS to VDD

II(pullup)II(pulldown)

Max
V
0.6

V

-1

1

µA

VI = VSS to VDD

40

190

VI = VSS to VDD

-190

-40

IOH

-100

IOL

4000

I/O off state output current

IOZ

VO = VDD or VSS, Internal pull
disabled±10

TYP

Input capacitanceCI4

Output capacitanceCO

4

Resolution

TYP

Bits

1

TYP

LSB

Video buffer disabled

0.5

TYP

RLOAD = 499 Ω, IFS = 1.4 mA

0

0.700

V

VOH(VIDBUF)

1.55

TYP

V

VOL(VIDBUF)

0.470

TYP

V

RLOAD = 499 Ω,

Differential non-linearity

DNL

Output compliance range

Compliance

Output high voltage (top of 75%
NTSC or PAL colorbar) 6/
Output low voltage (bottom of sync
tip)

RESET
SymbolTest condition2/
Device type: All

Active low width of the ���������RESET pulse

Lim its
Min

Unit
Max

12C

tw(RESET)

Setup time, boot configuration pins valid before
tsu(BOOT)���������RESET rising edge
3
Hold time, boot configuration pins valid afterth(BOOT)���������RESET rising edge
OSCILLATORS AND CLOCKS
Switching characteristics for 24 MHz system
Start up time (from power up until oscillating at
stable frequency)
Oscillation frequency
ESR

ns

12C
12C

24 MHz36 MHz4ms

24 or 36 TYP

MHz

60

Ω

30

Frequency stability±50

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

pF

10

INL

Timing requirements for Reset 7/ 8/ (See figure 5)
No
Test

2

Unit

Low level output current

Integral non-linearity, best fit

1

Lim its2/
Device type: All
High level output voltage 3/

Resolution

Video buffer

1/

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TABLE I. Electrical performance characteristics - Continued.
No

Test

Symbol1/

Test condition2/
Device type: All

Lim its

Unit

Min

OSCILLATORS AND CLOCKS - Continued
Switching characteristics for 27 MHz system
Start up time (from power up until oscillating at
stable frequency)
Oscillation frequency

Max

4
27

TYP

ms
MHz

ESR

50

Ω

Frequency stability

±50

ppm

CLOCK PLL ELECTRICAL DATA/TIMING (Input and output clocks)
Timing requirements for MXI1/CLKIN1 9/ 10/
1
Cycle time, MXI1/CLKIN1
tc(MXI1)
See figure 6
27.7 11/41.6 11/

ns

2

Pulse duration, MXI1/CLKIN1 hightw(MXI1H)

0.45C

0.55C

ns

3

Pulse duration, MXI1/CLKIN1 low

tw(MXI1L)

0.45C

0.55C

ns

4

Transition time, MXI1/CLKIN1

tt(MXI1)

0.05C

ns

5

Period jitter, MXI1/CLKIN1tJ(MXI1)

0.02C

ns

Timing requirements for MXI2/CLKIN2 9/ 12/
1

Cycle time, MXI2/CLKIN2

tc(MXI2)

37.037 13/37.037 13/

ns2

Pulse duration, MXI2/CLKIN2 hightw(MXI2H)

0.45C

0.55C

ns

3

Pulse duration, MXI2/CLKIN2 low

tw(MXI2L)

0.45C

0.55C

ns

4

Transition time, MXI2/CLKIN2

tt(MXI2)

0.05C

ns

5

Period jitter, MXI2/CLKIN2tJ(MXI2)

0.02C

ns

Switching characteristics for CLKOUT1

See figure 7

9/ 14/

1

Cycle time CLKOUT1

tc(CLKOUT1)

2

Pulse duration, CLKOUT1 hightw(CLKOUT1H)

0.45P

0.55P

ns

3

Pulse duration, C:LKOUT1 low

tw(CLKOUT1L)

0.45P

0.55P

ns

4

Transition time, CLKOUT1

tt(CLKOUT1)

5

Delay time, MXI1/CLKIN1 high to CLKOUT1
high
6Delay time, MXI1/CLKIN1 low to CLKOUT1
low
Switching characteristics for CLKOUT2 9/ 15/

See figure 8tc(MXI1)

td(MXI1H-

ns

0.55P

ns

1

8

ns

1

8

ns

CLKOUT1H)

td(MXI1LCLKOUT1L)

1

Cycle time CLKOUT2

tc(CLKOUT2)2

Pulse duration, CLKOUT2 hightw(CLKOUT2H)

0.45P

0.55P

ns

3

Pulse duration, C:LKOUT2 lowtw(CLKOUT2L)

0.45P

0.55P

ns

4

Transition time, CLKOUT2

tt(CLKOUT2)

5

Delay time, MXI1/CLKIN1 high to CLKOUT2
high
Delay time, MXI1/CLKIN1 low to CLKOUT2
lowtd(MXI1H-

6

See figure 9tc(MXI1)/3

ns

0.05P

ns

1

8

ns

1

8

ns

CLKOUT2H)

td(MXI1LCLKOUT2L)

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.
No

Test

Symbol1/

Test condition2/
Device type: All

Lim its

Unit

Min

Max

CLOCK PLL ELECTRICAL DATA/TIMING (Input and output clocks) - Continued
Switching characteristics for CLKOUT3 9/ 16/
1

Cycle time CLKOUT3tc(CLKOUT3)

2

Pulse duration, CLKOUT3 hightw(CLKOUT3H)

See figure 10

tc(MXI1)/8
0.45P

0.55P

ns

3

Pulse duration, C:LKOUT3 lowtw(CLKOUT3L)

0.45P

0.55P

4

Transition time, CLKOUT3

tt(CLKOUT3)

5

Delay time, CLKIN/MXI high to CLKOUT3 high

0.05P

td(MXI2H-

1

8

1

8

CLKOUT3H)

6

Delay time, CLKIN/MXI low to CLKOUT3 lowtd(MXI2LCLKOUT3L)

GPIO PERIPHERAL INPUT/OUTPUT ELECTRICAL DATA/TIMING
Timing requirements for GPIO inputs
1
Pulse duration, GPIx hightw(GPIH)
See figure 10

52

ns

2

52

ns

26 17/

ns

26 17/

ns

Pulse duration, GPIx hightw(GPIL)

Switching characteristics for GPIO outputs
3

Pulse duration, GPOx hightw(GPOH)

4

Pulse duration, GPOx low

tw(GPOL)See figure 11

GPIO PERIPHERAL EXTERNAL INTERRUPTS ELECTRICAL DATA/TIMING
Timing requirements for external interrupts/EDMA events 18/
1
Width of the external interrupt pulse low
tw(ILOW)
See figure 12
52

ns

2

ns

Width of the external interrupt pulse hightw(IHIGH)

52

AEMIF ELECTRICAL DATA/TIMING
Timing requirements for Asynchronous Memory Cycles for AEMIF module 19/
READS and WRITES
2
Pulse duration, EM_WAIT assertion andtw(EM_WAIT)
deassertionREADS
12 Setup time, EM_D[15:0] valid before ���������
tsu(EMDV-EMOEH)
EM_OE high��������� high13 Hold time, EM_D[15:0] valid after EM_OE
th(EMOEH-EMDIV)���������
14 Setup time EM_WAIT asserted before EM_OE
tsu(EMOELhigh 20/
EMWAIT)READS (OneNAND Synchrnous Burst Read)
30 Setup time, EM_D[15:0] valid before �����������
tsu(EMDVEM_CLKhigh
EMCLKH)
31 Hold time, EM_D[15:0] valid after �����������
th(EMCLKH-EMDIV)
EM_CLK high
WRITES
28 Setup time, EM_WAIT asserted before validtsu(EMWELbefore ����������
EM_WE high
EMWAIT)See figure 13 and 14
2E

ns

5

ns

0

ns
4E TYP

4

ns

4

ns
4E

TYP

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.
No

Test

SymbolTest condition2/
Device type: All

1/
LimitsMin

Unit

TYPICALMax

AEMIF ELECTRICAL DATA/TIMING – Continued
Switching characteristics for Asynchrnous Memory Cycles for AEMIF module 19/ 21/ 22/ See figure 13 and 14
READS and WRITES
1Turn around timetd(TURNAROUND)(TA)*E

ns

READS
3

EMIF read cycle time (EW = 0)tc(EMRCYCLE)(RS+RST+RH)*E

nsnstsu(EMCEL-EMOEL)(RS+RST+RH+(EWC*16))*E(RS)*Ens

0ns(RH)*Ens

0nstsu(EMBAV-EMOEL)(RS)*Ensth(EMOEH-EMBAIV)(RH)*Ensth(EMOEH-EMBAIV)(RS)*Enstsu(EMBAV-EMOEL)(RH)*Ensth(EMOEL)(RST)*Ensnstd(EMWAITH-EMOEH)(RST+(EWC*1
6))*E
4E

EMIF read cycle time (EW = 1)11����������������
Output setup time, EM_CE[1:0] low to���������
EM_OE low (SS = 0)����������������
Output setup time, EM_CE[1:0] low to���������
EM_OE low (SS = 1)��������� high to
Output hold time, EM_OE
����������������
EM_CE[1: 0] high (SS = 0)��������� high to
Output hold time, EM_OE
����������������
EM_CE[1: 0] high (SS = 1)����������������
Output setup time, EM_BA[1:0] valid to��������� low
EM_OE��������� high to
Output hold time, EM_OE
����������������
EM_BA[1:0] invalid����������������
Output setup time, EM_A[13:0] valid to��������� low
EM_OE��������� high to
Output hold time, EM_OE
����������������
EM_A[13: 0] invalid���������
EM_OE active low width (EW = 0)���������
EM_OE active low width (EW = 1)

32

Frequency, EM_CLK

33

Cycle time, EM_CLK

34

38

Output setup time, EM_ADV valid before
EM_CLK highOutput hold time, EM_CLK high to
EM_ADV invalid
Output setup time,
EM_A[13:0]/EM_BA[1] valid before
EM_CLK highOutput hold time, EM_CLK high to
EM_A[13:0]/EM_BA[1] invalid
Pulse duration, EM_CLK high39

Pulse duration, EM_CLK low

4

5

6
7
8
9
10

Delay time from EM_WAIT deasserted to���������
EM_OE high
READS(OneNAND Synchronous Burst Read)

35
36
37

th(EMOEH-EMCEH)

ns

fc(EMWCYCLE)

1

66
1000

tc(EM_CLK)15tsu(EM_ADVV-EM_CLKH)

5nsth(EM_CLKH-EM_ADVIV)

6nstsu(EM_AV-EM_CLKH)

5nsth(EM_CLKH-EM_AIV)

6nstw(EM_CLKH)

23/

ns

tw(EM_CLKL)

23/

ns

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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TABLE I. Electrical performance characteristics - Continued.
No

Test

SymbolTest condition2/
Device type: All

1/
LimitsMin

TYPICALUnit
Max

AEMIF ELECTRICAL DATA/TIMING – Continued
Switching characteristics for Asynchrnous Memory Cycles for AEMIF module 19/ 21/ 22/ See figure 13 and 14
WRITES
15 EMIF write cycle time (EW = 0)tc(EMWCYCLE)(WS+WST+WH)*
E
EMIF write cycle time (EW = 1)
(WS+WST+WH+(
EWC*16))*E����������������
16 Output setup time, EM_CE[1:tsu(EMCEL-EMWEL)(WS)*E0] low to���������� low (SS = 0)
EM_WE����������������
0
Output setup time, EM_CE[1:0] low to���������� low (SS = 1)
EM_WE���������� high to
17 Output hold time, EM_WE
th(EMWEH-EMCEH)(WH)*E����������������
EM_CE[1: 0] high (SS = 0)���������� high to0
Output hold time, EM_WE����������������
EM_CE[1: 0] high (SS = 1)����������������
20 Output setup time, EM_BA[1:tsu(EMBAV-EMWEL)(WS)*E0] valid to���������� low
EM_WE���������� high to
21 Output hold time, EM_WE
th(EMWEH-EMBAIV)(WH)*E����������������
EM_BA[1: 0] invalid����������������
22 Output setup time, EM_A[13:th(EMWEH-EMBAIV)(WS)*E0] valid to����������
EM_WE low���������� high to
23 Output hold time, EM_WE
tsu(EMBAV-EMWEL)(WH)*E����������������
EM_A[13: 0] invalid���������� active low width (EW = 0)
24 EM_WE
th(EMWEL)(WST)*E����������
(WST+(EWC*16))
EM_WE active low width (EW = 1)*E
25 Delay time from EM_WAIT deasserted to td(EMWAITH-EMWEH)
4E
����������
EM_WE high����������������
26 Output setup time, EM_D[15:tsu(EMDV-EMWEL)(WS)*E0] valid to���������� low
EM_WE���������� high to
27 Output hold time, EM_WE
th(EMWEH-EMDIV)(WH)*E����������������
EM_D[15: 0] invalid
See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

B

DWG NO.
V62/09643
PAGE 10

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

TABLE I. Electrical performance characteristics - Continued.
Test

Symbol1/

Test condition

Li mits2/
Device type: All

Fast mode
Min

Max

Unit

Standard mode
Min

Max

MMC/SD ELECTRICAL DATA/TIMING
Timing requirements for MMC/SD module (See figure 19 and 21)
1

Setup time, SD_CMD valid before
tsu(CMDV-CLKH)
SD_CLK high2
Hold time, SD_CMD valid afterth(CLKH-CMDV)
SD_CLK high3
Setup time, SD_DATx valid before
tsu(DATV-CLKH)
SD_CLK high4
Hold time, SD_DATx valid afterth(CLKH-DATV)
SD_CLK highSwitching characteristics for MMC/SD module (See figure 18 - 21)

6

5

ns

2.5
24/
6

5

ns

5

ns

2.5

5

ns

7

Operating frequency, SD_CLK

f(CLK)

0

50

0

25

ns

8

f(CLK_ID)

0

400

0

400

ns

9

Identification mode frequency,
SD_CLK
Pulse width, SD_CLK lowtw(CLKL)

7

10

Pulse width, SD_CLK hightw(CLKH)

7

11

Rise time, SD_CLK

tr(CLK)

12

Fall time, SD_CLK

13

Delay time, SD_CLK low to SD_CMD
transition
Delay time, SD_CLK low to SD_DATx
transition

14

10
10
3

tf(CLK)

ns
ns
10

3

10

ns

td(CLKL-CMD)

-7.5

4

-7.5

14

ns

td(CLKL-DAT)

-7.5

4

-7.5

14

ns

SIZE
A

CAGE CODE
16236

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

ns

REV

B

DWG NO.
V62/09643
PAGE 11TABLE I. Electrical performance characteristics - Continued.
No

Test

Symbol1/

Test condition2/
Device type: All

VPFE LECTRICAL DATA/TIMING
Timing requiremenets for VPFE PCLK Master/Slave mode 25/ (See figure 22)
1
Cycle time, PCLK
tc(PCLK)
H3A not used
H3A used

Lim its

Unit

Min

Max

13.33 orP 26/
2P + 1

100

ns

100

ns

2

Pulse duration, PCLK hightw(PCLKH)

5.7

ns

3

Pulse duration, PCLK lowtw(PCLKL)

5.7

ns

4

Transition time, UXCLK

tt(PCLK)

3

ns

Timing requirements for VPFE(CCD) Slave mode (See figure 23)
5

Setup time, CCD valid before PCLK edgetsu(CCDV-PCLK)

3

ns

6

Hold time, CCD valid after PCLK edgeth(PCLK-CCDV)

2

ns

7

Setup time, HD valid before PCLK edgetsu(HDV-PCLK)

3

ns

8

Hold time, HD valid after PCLK edgeth(PCLK-HDV)

2

ns

9

Setup time, VD valid before PCLK edgetsu(VDV-PCLK)

3

ns

10

Hold time, VD valid after PCLK edge

11

Setup time, CAM_WEN_FIELD valid before
PCLK edge
12 Hold time, CAM_WEN_FIELD valid after PCLK
edge
Timing requirements for VPFE(CCD) Master modeth(PCLK-VDV)

2nstsu(CAM_WEN_FIL

3

ns

2

ns

3

ns

ELDV-PCLK)th(PCLKCAM_WEN_FIELDV)(See figure 24)

27/

15

Setup time, CCD valid before PCLK edge

16

Hold time, CCD valid after PCLK edgeth(PCLK-CCDV)

2

ns

23

Setup time, CAM_WEN_FIELD valid before
PCLK edge
Hold time, CAM_WEN_FIELD valid after PCLK
edge

tsu(CAM_WEN_FIL

3

ns

2

ns

24

tsu(CCDV-PCLK)

ELDV-PCLK)th(PCLKCAM_WEN_FIELDV)Switching characteristics for VPFE(CCD) Master mode (See figure 25)
18

Delay time, PCLK edge to HD invalidtd(PCLKL-HDIV)

3

11

ns

20

Delay time, PCLK edge to VD invalidtd(PCLKL-VDIV)

3

11

ns

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

B

DWG NO.
V62/09643
PAGE 12TABLE I. Electrical performance characteristics - Continued.
No

Test

Symbol1/

Test condition2/
Device type: All

Timing requirements for VPBE CLK inputs

Lim its

Unit

Min

Max

13.33

160

VPFE LECTRICAL DATA/TIMING

1

Cycle time, PCLK 28/

tc(PCLK)

2

Pulse duration, PCLK hightw(PCLKH)

See figure 26

5.7

3

Pulse duration, PCLK lowtw(PCLKL)

5.7

4

Transition time, PCLK

tt(PCLK)

5

Cycle time, EXTCLKtc(EXTCLK)

13.33

6

Pulse duration, EXTCLK hightw(EXTCLKH)

5.7

7

Pulse duration, EXTCLK lowtw(EXTCLKL)

5.7

8

Transition time, EXTCLK

tt(EXTCLK)

ns
ns
ns

3

ns

160

ns
ns
ns

3

ns

Timing requirements for VPBE control input with respect to PCLK and EXTCLK 27/ 29/ 30/
9Setup time, VCTL valid before VCLKIN edgetsu(VCTLV-VCLKIN)

10

Hold time, VCTL valid after VCLKIN edgeth(VCLKIN-VCTLV)

See figure 27

2

ns

1

ns

Switching characteristics for VPBE control and data output with respect to PCLK and EXTCLK
11

Delay time, VCLKIN edge to VCTL validtd(VCLKIN-VCTLV)

12

Delay time, VCLKIN edge to VCTL invalidtd(VCLKIN-VCTLIV)

13

Delay time, VCLKIN edge to VDATA validtd(VCLKIN-VDATAV)

14

Delay time, VCLKIN edge to VDATA invalidtd(VCLKIN-VDATAIV)

See figure 28

13.3
2

ns
ns

13.3
2

ns
ns

Switching characteristics for VPBE control and data output with respect to VCLK 27/ 32/
17

Cycle time, VCLK

tc(VCLK)

18

Pulse duration, VCLK hightw(VCLKH)

See figure 29

13.33
5.7

19

Pulse duration, PCLK lowtw(VCLKL)

5.7

20

Transition time, VCLK

tt(VCLK)

21

Delay time, VCLKIN high to VCLK hightd(VCLKINH-VCLKH)

22

Delay time, VCLKIN low to VCLK low

td(VCLKINL-VCLKL)

23

Delay time, VCLK edge to VCTL validtd(VCLK-VCTLV)

24

Delay time, VCLK edge to VCTL invalidtd(VCLK-VCTLIV)

25

Delay time, VCLK edge to VDATA validtd(VCLK-VDATAV)

26

Delay time, VCLK edge to VDATA invalidtd(VCLK-VDATAIV)

160

ns
ns
3

ns

2

12

ns

2

12

ns

4

ns

0

ns
4

0

DLA LAND AND MARITIMECOLUMBUS, OHIOCAGE CODE
16236
REV

B

ns
ns

See footnotes at end of table.

SIZE
A

ns

DWG NO.
V62/09643
PAGE 13TABLE I. Electrical performance characteristics - Continued.
No

Test

SymbolTest condition2/
Device type:All

Switching chrasteristics for USB2.0
1

Min

tf(D)

75

300

4

20

0.5

ns

tfrfm

80

125

90

%

VCRS

1.3

2

1.3

111.1
1
2

t(DRATE)

driver output resistanceZDRV

See figure 30

V

tjr(source)NT

2

2

ns

tjr(FUNC)NT

25

2

ns

tjr(source)PT

1

1

ns

tjr(FUNC)PT

10

1

ns

175

ns

tw(EOPT)

1250

tw(EOPR)

670

Test

1500

160
82

1.5

SymbolTiming requirements for UARTx receiver
4
Pulse duration, receive data bit (RXDn)

ns
12

28

40.5

49.5

480

Mb/s

49.5

Ω

Lim its

Test condition2/
Device type: All

5

Max

ns

Data rate

No

Max

0.5

10

7

Min

20

9

6

Max

High Speed
480 Mbps 33/

4

8

5

Min

Full Speed
12 Mbps300

output signal cross overvoltage 34/
Source (Host) driver jitter, nexttransaction
Function driver jitter, nexttransaction
Source (Host) driver jitter,paired transaction 36/
Function driver jitter, nexttransaction
Pulse duration, EOP
transmitter
Pulse duration, EOP receiver

4

Low Speed
1.5 Mbps

Unit

75

tr(D)

3

LimitsUSB2.0 ELECTRICAL DATA/TIMING

Rise time, USB_DP and
USB_DM signals 34/
Fall time, USB_DP and
USB_DM signals 34/
Rise/Fall time, matching 35/

2

1/

Min

Unit
Max

UART ELECTRICAL DATA/TIMING

Pulse duration, receive start bittw(URXDB)

See figure 31

tw(URXSB)

0.99U 37/

1.05U 37/

ns

0.99U 37/

1.05U 37/

ns

1.5

MHz

5

MHz

Switching characteristic for UARTx transmit
1

UART0/1 maximun programmable baud ratef(baud)See figure 31

UART2 maximum programmable baud rate
2

Pulse duration, transmit data bit (TXDn)

tw(UTXDB)

U-2 37/

U+2 37/

ns

3

Pulse duration, transmit start bittw(UTXSB)

U-2 37/

U+2 37/ns

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

B

DWG NO.
V62/09643
PAGE 14TABLE I. Electrical performance characteristics - Continued.
No

Test

SymbolTest condition2/
Device type: All

Timing requirements for SPI (All modes)

1/
Lim its
Min

Unit
Max

SPI ELECTRICAL DATA/TIMING

1

Cycle time, SPI_CLK

tc(CLK)

2

Pulse duration, SPI_CLK high (All master Modes)tw(CLKH)

3

Pulse duration, SPI_CLK low (All master Modes)tw(CLKL)

Timing requirements for SPI master mode [Clock phase = 0] 39/

See figure 32

37.037ns

0.45*T

0.55*Tns

0.45*T

0.55*Tns

See figure 33

4

Setup time, SPI_DI (input) valid before SPI_CLK
tsu(DIV_CLKL)
Clock polarity = 0(output) falling edge
5
Setup time, SPI_DI (input) valid before SPI_CLK
tsu(DIV_CLKH)
Clock polarity = 1(output) rising edge
6
Hold time, SPI_DI (input) valid after SPI_CLKth(CLKL-DIV)
Clock polarity = 0(output) falling edge
7
Setup time, SPI_DI (input) valid after SPI_CLKth(CLKH-DIV)
Clock polarity = 1(output) rising edge
Switching characteristics for SPI master mode [Clock phase = 0] See figure 33
8

.5P+3

ns

.5P+3

ns

.5P+3

ns

2.5P+3ns

Delay time, SPI_CLK (output) rising edge totd(CLKH_DOV) Clock polarity = 0
SPI_DO (output) transition
9
Delay time, SPI_CLK (output) falling edge totd(CLKL_DOV)
Clock polarity = 1
SPI_DO (output) transition
10
Delay time, SPI_EN[1:0] (output) falling edge totd(ENL_CLKH/L)
first SPI_CLK (output) rising or falling edge
11
Delay time, SPI_CLK (output) rising or falling edgetd(CLKH/L-ENH)
e to SPI_EN[1:0] (output) rising edge
Timing requirements for SPI master mode [Clock phase = 1] 39/ See figure 34
13

.5P+3

ns

.5P+3

ns

.5P+3

ns

.5P+3

ns

Setup time, SPI_DI (input) valid before SPI_CLK
tsu(DIV_CLKL)
Clock polarity = 0(output) riing edge
14
Setup time, SPI_DI (input) valid before SPI_CLK
tsu(DIV_CLKH)
Clock polarity = 1(output) falling edge
15
Hold time, SPI_DI (input) valid after SPI_CLKth(CLKL-DIV)
Clock polarity = 0(output) rising edge
16
Setup time, SPI_DI (input) valid after SPI_CLKth(CLKH-DIV)
Clock polarity = 1(output) falling edge
Switching characteristics for SPI master mode [Clock phase = 1] See figure 34
17
18
19
20

Delay time, SPI_CLK (output) falling edge to
SPI_DO (output) transition
Delay time, SPI_CLK (output) rising edge to
SPI_DO (output) transition
Delay time, SPI_EN[1:0] (output) falling edge tofirst SPI_CLK (output) rising or falling edge
Delay time, SPI_CLK (output) rising or falling edge
to SPI_DO (output) high impedance

-4

5

ns

-4

5

ns

2P 40/

40/

ns

P+.5C
41/

41/

ns

td(CLKH_DOV)

Clock polarity = 0

-4

5

ns

td(CLKL_DOV)

Clock polarity = 1

-4

5

ns

td(ENL_CLKH/L)

2P 40/

40/

ns

td(CLKH/L-

P+.5C
41/

41/

ns

DOHz)

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

B

DWG NO.
V62/09643
PAGE 15TABLE I. Electrical performance characteristics - Continued.
Test

SymbolTest condition
2/

LimitsStandard mode

Device type: All
Timing requirements for I2C timings

1/

Min

Max

Unit
Fast modeMin

Max

I2C ELECTRICAL DATA/TIMING

1

Cycle time, SCL

2

Setup time, SCL high before SDA low (for arepeated START condition)

3

Hold time, SCL low after SDA low (for a
START and a repeated START condition)

456tc(SCL)See figure 35

10

2.5

µs

tsu(SCLH-SDAL)

4.7

0.6

µs

th(SCLL-SDAL)

4

0.6

µs

Pulse duration, SCL lowtw(SCLL)

4.7

1.3

µs

Pulse duration, SCL hightw(SCLH)

4

0.6

µs

Setup time, SDA valid before SCL hightsu(SDAV-SCLH)

250

100
43/

ns

7

Hold time, SDA valid after SCL low (ForI2C bus device)th(SDA-SCLL)

0 44/

0 44/

8

Pulse duration, SDA high between STOP
and Start conditions

tw(SDAH)

4.7

1.3

9

Rise time, SDA

tr(SDA)1000

46/ 47/

300

ns

10

Rise time, SCL

tr(SCL)1000

46/ 47/

300

ns

11

Fall time, SDA

tf(SDA)300

46/ 47/

300

ns

12

Fall time, SCL

tf(SCL)300

46/ 47/

300

v

13

Setup time, SCL high before SDA high (for
STOP condition)

14

Pulse duration, spike (must be suppressed)tw(SP)

15

Capacitive load for each bus line

Cb 47/

tsu(SCLH-SDAH)

4

0.9
45/

µs

0.6
0
400

µs

µs
50

ns

400

pF

Switching characteristics for I2C timings 47/
16

Cycle time, SCL

17

Delay time, SCL high to SDA low ( for arepeated START condition)

18

Delay time, SDA low to SCL low (for a
START and a repeated START condition)

19
20
21
22

tc(SCL)See figure 36

10

2.5

µs

td(SCLH-SDAL)

4.7

0.6

µs

td(SDAL-SCLL)

4

0.6

µs

Pulse duration, SCL lowtw(SCLL)

4.7

1.3

µs

Pulse duration, SCL hightw(SCLH)

4

0.6

µs

Dealy time, SDA valid to SCL hightd(SDAV-SCLH)

250

100

Valid time, SDA valid after SCL low (ForI2C devices)tv(SCLL-SDAV)

0

0

23

Pulse duration, SDA high between STOP
and START conditions

tw(SDAH)

4.7

1.3

µs

28

Delay time, SCL high to SDA high (for
STOP condition)td(SCLH-SDAH)

4

0.6

µs

29

Capacitance for each I2C pin

Cp

10

µs
0.9

10

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

B

DWG NO.
V62/09643
PAGE 16µs

pF

TABLE I. Electrical performance characteristics - Continued.
No

Test

SymbolTest condition

2/

LimitsDevice types: All
ASP ELECTRICAL DATA/TIMING
Timing requirements for ASP 44/ See figure

Min

Unit
Max

37

15

Cycle time, CLKR/X

tc(CKRX)CLK ext

38.5 or 2P 49/ 50/

ns

16

Pulse duration, CLKR/X high or
CLKR/X low

OTG(CLKS)

CLKS ext

19.25 or P 49/ 50/
51/

ns

5

Setup time, external FSR high before

tsu(FRH-CKRL)CLKR int

21

ns

CLKR ext

6ns

CLKR int0ns

CLKR ext

6ns

CLKR int

21

ns

CLKR ext

6ns

CLKR int0ns

CLKR ext

6ns

CLKR int

21

ns

CLKR ext

6ns

CLKR int0ns

CLKR ext

10nstc(CKRX)

CLKR/X int

6P or 1 49/ 50/
53/

ns

CLKR low
6

Hold time, external FSR high afterth(CKRL-FRH)

CLKR low
7

Setup time, DR valid before CLKR lowtsu(DRV-CKRL)

8

Hold time, DR valid after CLKR low

th(CKRL-DRV)

10

Setup time, external FSX high before

tsu(FXH-CKXL)CLKX low
11

Hold time, external FSX high afterth(CKXL-FXH)

CLKX low
Switching characteristics for McBSP

44/

47/ See figure 37

2

Cycle time, CLKR/X

17

Delay time, CLKS high to internal
CLKR/X

td(CLKS-CLKRX)

CLKR/X int

1

24

ns

3

Pulse duration, CLKR/X high or
CLKR/X low

tw(CKRX)

CLKR/X int

C-1 54/

C+1 54/ns

4Delay time, CLKR high to internal FSR

td(CKRH-FRV)

CLKR int

3

25

ns

CLKX ext

3

25

ns

CLKX int

-4

8

ns

CLKX ext

3

25

ns

12

ns

valid
9

Delay tine, CLKR high to internal FSX

td(CKXH-FXV)

valid
12

Disable time, DX high impedancetdis(CKXH-DXHZ)

CLKX int

following last data bit from CLKX high

CLKX ext

13

Delay time, CLKX high to DX validtd(CKXH-DXV)

14

Delay time, FSX high to DX validtd(FXH-DXV)ONLY applies when in data delay 0(XDATDLY = 00b) mode

12ns

CLKX int

-5

12

ns

CLKX ext

3

25

ns

FSX int

14

ns

FSX ext

25

ns

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

B

DWG NO.
V62/09643
PAGE 17

TABLE I. Electrical performance characteristics - Continued.
Test

Symbol1/

Test condition2/
Device type: All

Mas ter
Min

Unit
Max

ASP TIMINGASP as SPI timing requirements CLKSP = 10b, CLKXP = 0
M30

Setup time, DR valid before CLKX lowtsu(DRV-CKXL)

M31

Hold time, DR valid after CLKX lowth(CKXL-DRV)

See figure 38

11

ns

0

ns

38.4 or 2P
49/ 50/ns

ASP as SPI switching characteristics CLKSP = 10b, CLKXP = 0
See figure 38

M33

Cycle time, CLKX

tc(CKX)

M24

Delay time, CLKX low to FSX high 55/

td(CKXL-FXH)

T-2

T+3

ns

M25

Delay time, FSX low to CLKX high 56/

td(FXL-CKXH)

L1-2

L1+2

ns

M26

Delay time, CLKX high to DX validtd(CKXH-DXV

-2

6

ns

M27

Disable time, DX high impedance following last
data bit from CLKX lowtdis(CKXL-DXHZ)

L1-3

L1+3

ns

ASP as SPI timing requirements CLKSP = 11b, CLKXP = 0
M39

Setup time, DR valid before CLKX hightsu(DRV-CKXH)

11

ns

M40

Hold time, DR valid after CLKX highth(CKXH-DRV)1

ns

38.5 or 2P
49/ 50/ns

ASP as SPI switching characteristics CLKSP = 11b, CLKXP = 0
M42

Cycle time, CLKX

tc(CKX)

See figure 39

M34

Delay time, CLKX low to FSX high 57/

td(CKXL-FXH)

L1-2

L1+3

ns

M35

Delay time, FSX low to CLKX high 56/

td(FXL-CKXH)

T-2

T+2

ns

M36

Delay time, CLKX low to DX validtd(CKXL-DXV

-2

6

ns

M37

Disable time, DX high impedance following last
data bit from CLKX lowtdis(CKXL-DXHZ)

-3

3

ns

M38

Delay time, FSX low to DX validtd(FXL-DXV)

H1- 2

H1+ 10ns

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

B

DWG NO.
V62/09643
PAGE 18

TABLE I. Electrical performance characteristics - Continued.
Test

Symbol1/

Test condition2/
Device type: All

Mas ter
Min

Unit
Max

ASP TIMING - Continued
ASP as SPI timing requirements CLKSP = 10b, CLKXP = 1
M49

Setup time, DR valid before CLKX hightsu(DRV-CKXH)

M50

Hold time, DR valid after CLKX highth(CKXH-DRV)

See figure 40

11

ns

0

ns

38.5 or 2P
49/ 50/ns

ASP as SPI switching characteristics CLKSP = 10b, CLKXP = 1
See figure 40

M52

Cycle time, CLKX

tc(CKX)

M43

Delay time, CLKX HIGH to FSX high 51/

td(CKXH-FXH)

T-1

T+3

ns

M44

Delay time, FSX low to CLKX low 56/

td(FXL-CKXL)

H1-2

H1+2

ns

M45

Delay time, CLKX low to DX validtd(CKXL-DXV

-2

6

ns

M46

Disable time, DX high impedance following last
data bit from CLKX hightdis(CKXH-DXHZ)

H1-3

H1+3

ns

ASP as SPI timing requirements CLKSP = 11b, CLKXP = 1
See figure 40

tc(CKX)

38.5 or 2P
49/ 50/ns

M52

Cycle time, CLKX

M43

Delay time, CLKX HIGH to FSX high 51/

td(CKXH-FXH)

T-1

T+3

ns

M44

Delay time, FSX low to CLKX low 56/

td(FXL-CKXL)

H1-2

H1+2

ns

M45

Delay time, CLKX low to DX validtd(CKXL-DXV

-2

6

ns

M46

Disable time, DX high impedance following last
data bit from CLKX hightdis(CKXH-DXHZ)

H1-3

H1+3

ns

ASP as SPI timing requirements CLKSP = 11b, CLKXP = 1
M58

Setup time, DR valid before CLKX lowtsu(DRV-CKXL)

M59

Hold time, DR valid after CLKX lowth(CKXL-DRV)

See figure 41

11

ns

0

ns

38.5 or 2P
49/ 50/ns

ASP as SPI switching characteristics CLKSP = 11b, CLKXP = 1
M62

Cycle time, CLKX

tc(CKX)

See figure 41

M53

Delay time, CLKX high to FSX high 51/

td(CKXH-FXH)

H1-1

H1+3

M54

Delay time, FSX low to CLKX low 58/

td(FXL-CKXL)

T-2

T+2

ns

M55

Delay time, CLKX low to DX validtd(CKXL-DXV

-2

6

ns

M56

Disable time, DX high impedance following last
data bit from CLKX hightdis(CKXH-DXHZ)

-3

3

ns

M57

Delay time, FSX low to DX validtd(FXL-DXV)

L1- 1

L1+ 10ns

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.
No

Test

SymbolTest condition

1/2/

LimitsDevice types: All

Min

Unit
Max

TIMER ELECTRICAL DATA/TIMING
Timing requirements for Timer input 59/ 60/ 61/
1

Cycle time, TIM_IN

tc(TIN)See figure 42

4P

ns

2

Pulse duration, TIM_IN hightw(TINPH)

0.45C

0.55C

ns

3

Pulse duration, TIM_IN low

tw(TINPL)

0.45C

0.55C

ns

4

Transition time, YTIM_IN

tt(TIN)

0.05C

ns

PULSE WIDTH MODULA (PWM)0/1/2/3 LECETRICAL TIMING DATA
Switching characteristics forPWM0/1/2/3 outputs
1

Pulse duration, PWMx hightw(PWMH)

2

Pulse duration, PWMx low

tw(PWML)

3

Transition time, PWMx

4

Delay time, CCDC(VD) trigger event to PWMx
valid

See figure 43 and 44

P

ns

P

ns

tt(PWM).05P

nstd(CCDC-PWMV)

10

ns

REAL TIME OUT (RTO) ELECTRICAL/TIMING DATA
Switching characteristics for RTO outputs
1

Pulse duration, RTOx hightw(RTOH)

2

Pulse duration, RTOx low

tw(RTOL)

3

Transition time, RTOx

4

Delay time, Timer 3 (TINT 12 or TINT34) trigger
event to RTOx valid

See figure 45 and 46

P

ns

P

ns

tt(RTO).1P

ns

td(TIMER3-RTOV)

10

ns

JTAG TEST PORT ELECTRICAL DATA/TIMING
Timing requirements for JTAG test port
1

Cycle time, TCK

tc(TCK)

2

Pulse duration, TCK hightw(TCKH)

3

Pulse duration, TCK low

4

Setup time, TDI valid before RTCK high5
6
7

See figure 47

20

ns

8

ns

tw(TCKL)8nstsu(TDIV-RTCKH)

10

ns

Hold time, TDI valid after RTCK highth(RTCKH-TDIV)

9

ns

Setup time, TMS valid before RTCK hightsu(TMSV-RTCKH)

2

ns

Hold time, TMS valid after RTCK highth(RTCKH-TMSIV)

5

ns

20

ns

Switching characteristics for JTAG test port
8

Cycle time, TCK

tc(TCK)See figure 47

9

Pulse duration, TCK hightw(TCKH)

10

ns

10

Pulse duration, TCK lowtw(TCKL)

10

ns

11

Rise time, all JTAG outputs

tr(all JTAG

1.3

ns

1.3

ns

0.25*tc(RTCK)

ns

outputs)

12

Fall time, all JTAG outputs

tf(all JTAG
outputs)

13

Delay time, TCK low to TDO validtd(RTCKL-TDOV)

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.
1/

2/
3/
4/
5/
6/
7/
8/
9/
10/
11/
12/
13/
14/
15/
16/
17/
18/
19/
20/

21/

22/
23/
24/
25/
26/
27/
28/
29/
30/

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance overthe specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured bycharacterization and/or design.
Over recommended ranges of supply voltage and operating temperature in the recommended operating conditions table. For
test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions
table. (Unless otherwise noted.)
These I/O specifications apply to regular 3.3 V I/Os and do not apply to DDR2/mDDR, USB I/Os are 1.8 V I/Os and adhere toUSB2.0 spec.
This specifications applies only to pins with an internal pullup (PU) or pulldown (PD). See manufacturer data for more
information.
To pull up a signal to the opposite supply rail, a 1 kΩ resistor is recommended.
100% color bar are not supported. 100% color bar require 1.2 V peal-to peak. The video buffer only provides 1.0 V peak-topeak.
BTSEL[1:0] and AECFG[4:0] are the boot configuration pins during device reset.
C = MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 24 MHz use C = 41.6 ns
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
C= MXI1/CLKIN1 cycle time in ns. For example, when MXI1/CLKIN1 frequency is 24 MHz use C = 41.6 nstc(MXI1) = 41.6 ns and tc(MXI1) = s7.7 ns are the only supported cycle times for MXI1/CLKIN1.
C = MXI2/CLKIN2 cycle time in ns. For example, when MXI2/CLKIN2 frequency is 24 MHz use C = 41.6 nstc(MXI2) = 37.037 ns is the only supported cycle times for MXI2/CLKIN2.
P = 1/CLKOUT1 clock frequency in nanoseconds (ns). For example, when CLKOUT1 frequency is 24 MHz use P = 41.6 ns.
P = 1/CLKOUT2 clock frequency in nanoseconds (ns). For example, when CLKOUT2 frequency is 8 MHz use P = 125 ns.
P = 1/CLKOUT3 clock frequency in nanoseconds (ns). For example, when CLKOUT3 frequency is 3 MHz use P = 333.3 ns.
This parameter value should not be used as a maximum performance specification. Actual performance of back-to-backaccesses of the GPIO is dependent upon internal bus activity.
The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have DM355 torecognize the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow
DM355 enough time to access the GPIO register through the internal bus.
E = PLLC1 SYSCLK2 period in ns. SYSCLK2 is the EMIF peripheral clock. SYSCLK2 is one-fourth the PLLC output clock.
For Example when PLLC output clock = 432 MHz, E = 9.259 ns. See manufacturer for more information.
Set up before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add
extended wait states. Figure 15 and 16 describe EMIF transactions that include extended wait states inserted during the
STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the $E requirement isto the start of where the HOLD phase would begin if there were no extended wait cycles.
TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write stobe, WH =Write hold, MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank andAsynchronous Wait cycle Configuration registers. These support the following range of values: TA[4-1], RS[16-1], RH[8-1],
WS[16-1], WST[64-1], WH[8-1], and MEW[1-256].
EWC = external wait cycles determined by EM_WAIT input signal. EWC supports the following range of values EWC[256-1].
Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration
register.
tc(EM_CLK)/3
For this parameter, you may include margin in your board design so that the toh = 2.5 ns of the MMC/SD device is notdegraded at the DM355 input pin.
P = 1/SYSCLK4 in ns. For example, if SYSCLK4 frequency is 135 MHz, use P = 7.41 ns.
Use whichever value is greater.
The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking
mode the rising edge of PCLK is referenced. When in negative edge clocking mode the failing edge of PCLK is referenced.
For timing specifications relating to PCLK see manufacturer for more information.
VCTL = HSYNC, VSYNC, and FIELDVCLKIN = PCLK or EXTCLKDLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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TABLE I. Electrical performance characteristics - Continued.
31/
32/
33/
34/
35/
36/
37/
38/
39/
40/
41/
42/
43/

44/
45/
46/
47/
48/
49/
50/
51/
52/
53/
54/

55/
56/
57/

VCTL = HSYNC, VSYNC, FIELD and LCD_OE
VCLKIN = PCLK or EXTCLK. for timing specifications relating to PCLK see manufacturer data for more information.
For more detailed specification, see manufacturer data for more information.
Low speed: CL = 200 pF, Full speed: CL = 50 pF, High speed: CL = 50 pF
tfrfm = (tr/tf) x 100. [Excluding the first transaction from the idle state.]
tjr = tpx(1) – tpx(0)U = UART baud time = 1/programmed baud rate.
T = tc(CLK) = SPI_CLK period is equal to the SPI module clock divided by a configurable divider.
P = 1/SYSCLK2 in ns. For example, if SYSCLK2 frequency is 135 MHz, use P = 7.41 ns.
The delay time can be adjusted using the SPI module register C2TDELAY.
The delay time can be adjusted using the SPI module register T2CDELAY.
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device ispowered down.
A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns mustthen be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) =1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
20 + 0.1Cb
Cb = total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall time are allowed.
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal
are also inverted.
P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1
Use whichever value is greater.
The ASP does not have a duty cycle specification, just ensure that the minimum pulse duration specification is met.
Minimum delay times also represent minimum output hold times.
Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLRK/X
cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC
timing requirements.
C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/SYSCLK2, where SYSCLK2 is an output of PLLC1)
S = sample rate generator input clock = CLKS if CLKSM = 0
H = CLKX high pulse width = (CLKGDV/2 + 1)*S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLGKDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the ASP bit rate does not exceed the maximum limit
T = CLKX period = (1 + CLKGDV) x 2P
L1 = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) x 2P when CLKGVD is even
H1 = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) x 2P when CLKGDV is even
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge ofthe master clock (CLKX).
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active low slave enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master ASP

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TABLE I. Electrical performance characteristics - Continued.
58/
59/
60/
61/

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge ofthe master clock (CLKX).
GPIO000, GPIO001, GPIO002, and GPIO003 can be used as an external clock input for Timer 3.
P = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use P = 41.6 ns.
C = TIM_IN ycle time in ns. For example, when TIM_IN frequency is 24 MHz use C = 41.6 ns.

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PAGE 23Case X

SymbolA
A1
A2b
Notes:
1.
2.

Dimensions

Millim eters
Min
Max

SymbolMillim eters
Min
Max

1.30
0.33
0.94
0.46

D/E
D1/E1
e

12.90
13.10
11.70 TYP
0.65 BSC

0.23
0.84
0.36

This drawing is subject to change without notice.
Dimensioning and tolerancing per ASME Y14.5M-1994
FIGURE 1. Case outline.

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Case XFIGURE 2. Terminal connections - Continued.

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Case X - Continued

FIGURE 2. Terminal connections - Continued.

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Case X - Continued

FIGURE 2. Terminal connections - Continued.

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FIGURE 3. Block diagram - Continued.

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Notes:1. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line
effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desiredtransmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
FIGURE 4. Test load circuit for AC timing measurements.

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FIGURE 5. Timing waveforms.

FIGURE 6. Timing waveforms.

FIGURE 7. Timing waveforms.

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PAGE 31FIGURE 8. Timing waveforms.

FIGURE 9. Timing waveforms.

FIGURE10. Timing waveforms.

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FIGURE 11. Timing waveforms.

FIGURE12. Timing waveforms.

FIGURE 13. Timing waveforms.

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FIGURE14. Timing waveforms.

FIGURE15. Timing waveforms.

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FIGURE 16. Timing waveforms.

FIGURE 17. Timing waveforms.

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FIGURE 18. Timing waveforms.

FIGURE 19. Timing waveforms.

FIGURE 20. Timing waveforms.

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PAGE 36FIGURE 21. Timing waveforms.

FIGURE 22. Timing waveforms.

FIGURE 23. Timing waveforms.

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FIGURE 24. Timing waveforms.

FIGURE 25. Timing waveforms.

FIGURE 26. Timing waveforms.

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NOTES:
1.
2.

VCLKIN = PCLK or EXTCLKVCTL = HSYNC, VSYNC, and FIELD

FIGURE 27. Timing waveforms.

NOTES:
1.
2.
3..

VCLKIN = PCLK or EXTCLKVCTL = HSYNC, VSYNC, FIELD, and LCD_OE
VDATA = COUT[7:0], YOUT[7:0], R{7:3], G[7:2], and B[7:3]
FIGURE 28. Timing waveforms.

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NOTES:
1.
2.
3..

VCLKIN = PCLK or EXTCLKVCTL = HSYNC, VSYNC, FIELD, and LCD_OE
VDATA = COUT[7:0], YOUT[7:0], R{7:3], G[7:2], and B[7:3]

FIGURE 29. Timing waveforms.

FIGURE 30. Timing waveforms.

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PAGE 40FIGURE 31. Timing waveforms.

FIGURE 32. Timing waveforms.

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FIGURE 33. Timing waveforms.

FIGURE 34. Timing waveforms.

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PAGE 42FIGURE 35. Timing waveforms.

FIGURE 36. Timing waveforms.

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PAGE 43FIGURE 37. Timing waveforms.

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PAGE 44FIGURE 38. Timing waveforms.

FIGURE 39. Timing waveforms.

FIGURE 40. Timing waveforms.

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FIGURE 41. Timing waveforms.

FIGURE 42. Timing waveforms.

FIGURE 43. Timing waveforms.

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FIGURE 44. Timing waveforms.

FIGURE 45. Timing waveforms.

FIGURE 46. Timing waveforms.

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FIGURE 47. Timing waveforms.

FIGURE 48. Timing waveforms.

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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

1/
2/
3/

Vendor item drawing administrative
control number 1/

Device manufacturer
CAGE code

Vendor part number

V62/09643-01XE

2/

SM32DM355GCEM216EP

V62/09643-01XF 3/01295

SM32DM355GCEM216EP

The vendor item drawing establishes an administrative control number for identifying the item on
the engineering documentation.
Not available from an approved source of supply.
Devices listed on this drawing are supplied to lead finish “F”. The solder ball material contains
compositions of: Sn = 63%, Pb = 34.5%, Ag = 2%, and Sb = 0.5%.
CAGE code

Source of supply

01295

DLA LAND AND MARITIMECOLUMBUS, OHIO

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZE
A

CAGE CODE
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PAGE 49