REVISIONSLTR

DESCRIPTIONAPPROVED

DATE

Vendor item drawing

Prepared in accordance with ASME Y14.24
REVPAGEREVPAGEREV STATUS
OF PAGESREV1PAGE2PMIC N/APREPARED BY
RICK OFFICER

Original date of drawing
YY-MM-DD

CHECKED BYRAJESH PITHADIA

09-01-13

APPROVED BYROBERT M. HEBERSIZEAREVAMSC N/A

34567891011121314DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
TITLE
MICROCIRCUIT, DIGITAL-LINEAR, 4:1 HIGHSPEED MULTIPLEXER, MONOLITHIC SILICONCODE IDENT. NO.

DWG NO.

V62/09616

16236
PAGE1OF

145962-V022-09

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance 4:1 high speed multiplexer microcircuit, with anoperating temperature range of -55C to +125C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/09616-01XIDrawingnumberEI

Device type(See 1.2.1)

I

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic01

Circuit function

OPA4872-EP

4:1 high speed multiplexer

1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter

Number of pinsX

14

JEDEC PUB 95

Package styleMS-012-AB

Plastic surface mount1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture:
Finish designator
ABCDEZDEFENSE SUPPLY CENTER, COLUMBUSCOLUMBUS, OHIO

Material
Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Other

SIZE

CODE IDENT NO.

DWG NO.

A

16236

V62/09616

REVPAGE

2

1.3 Absolute maximum ratings.

1/Power supply voltage ................................................................................................. 6.5 V
Input voltage range .................................................................................................... VSPower dissipation (PD) ............................................................................................... 312.5 mW
Storage temperature range (TSTG)............................................................................... -65C to +125C
Lead temperature (soldering, 10 seconds) ................................................................. +260C
Junction temperature (TJ) .......................................................................................... +150C
Junction temperature: continuous operation, long term reliability ............................... +140C
Thermal resistance, junction to ambient (JA) ............................................................ 80C/W
Electrostatic discharge (ESD) rating:
Human body model (HBM) ..................................................................................... 1500 V
Charged device model (CDM) ................................................................................ 1000 V
Machine model (MM) ............................................................................................. 200 V

1.4 Recommended operating conditions. 2/
Power supply voltage ................................................................................................. 5 V
Operating free-air temperature range (TA) .................................................................. -55C to +125C1/

Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.

2/Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIOSIZE

CODE IDENT NO.

DWG NO.

A

16236

V62/09616

REVPAGE32. APPLICABLE DOCUMENTSJEDEC PUB 95–Registered and Standard Outlines for Semiconductor Devices(Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington,
VA 22201-3834 or online at http://www.jedec.org)

3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Truth table. The truth table shall be as shown in figure 3.
3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4.

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CODE IDENT NO.

DWG NO.

A

16236

V62/09616

REVPAGE

4dB-80 typical+25C

3 channels driven at 5 MHz, 1 VPP

CTAll hostile crosstalk,0.005 typical+25C

G = +2 V/V, PAL, VO = 1.4 VP

GPDifferential phase%

0.035 typical

01+25C

G = +2 V/V, PAL, VO = 1.4 VP

GD

Differential gain

01+25C

NIN

Inverting input
current noise01+25Cf  100 kHz

NNIN

Noninverting input
current noise

01+25Cf  100 kHzNIVInput voltage noise

01+25C

HD3Third harmonic
distortion

01+25C

HD2Second harmonic
distortion

01+25CtCS

Channel switching time

01+25C

To 0.05 %, 2 V steptS

Settling time

01+25C

4 V step

tr, tfRise time and fall time

01+25C

SRSlew rate

01+25C

VO = 2 VPP, RL = 150 LSBW

Large signal bandwidth+25C

VO = 500 mVPP, RL = 150 BWBandwidth for 0.1 dbflatness

01+25C

VO = 500 mVPP, RL = 150 

SSBW

Small signal bandwidth

DevicetypeTemperature,TA

SymbolConditions 2/ 3/ 4/- - -Test

TABLE I. Electrical performance characteristics. 1/-66 typical

3 channels driven at 30 MHz, 1 VPP

input referred

MinLimits

IUnit
Max

AC performance section

4 V step01

To 0.1 %, 2 V stepns

15 typicalns

1.25 typicalV/s2300 typicalMHz

500 typicalMHz

120 typicalMHz

500 typical

14 typicalG = +2 V/V, f = 10 MHz,VO = 2 VPP, RL = 150 
G = +2 V/V, f = 10 MHz,VO = 2 VPP, RL = 150 nV /4.5 typicaldBc-78 typicaldBc-60 typicalns

10 typical_f
Hz

4.0 typical

pA /_fHzf  100 kHz

19 typical

pA /_f
Hz01
01

See footnotes at end of table.

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16236

A

CODE IDENT NO.

SIZE

DWG NO.

V62/09616

REVPAGE

5

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/ 3/ 4/

Temperature,
TADevice
typeLimitsMin

DC performance

sectionOpen looptransimpedance

ZOL

VO = 0 V, RL = 100 01+25CVIOk

60
501+25C

VCM = 0 VMax92-55C to +125C
Input offset voltage

UnitmV10.5-55C to +125C
Average input offset
voltage drift

VIO

VCM = 0 V-55C to +125C01

30

V/C

Input offset voltage
matching

VIOM

VCM = 0 V+25C01

5mV

10.5-55C to +125C
Noninverting input biascurrent

INIB

1401+25C

VCM = 0 VA

20-55C to +125C
Average noninverting
input bias current

INIB

VCM = 0 V-55C to +125C01

48nA/CInverting bias current

IIB

VCM = 0 V+25C01

18A

35-55C to +125C
Average inverting
input bias current

IIB

VCM = 0 V

CMIREach noninverting input-55C to +125C01+25C01125nA/CInput section
Common mode input
range

2.55
2.4-55C to +125C
Common mode
rejection ratio

CMRR

noninverting input
Input resistance

RIN01+25C

VCM = 0 V, input referred,+25C01

Inverting, open loop
Input capacitance

CIN

Noninverting, channel enabled+25C50dB43-55C to +125C

Noninverting, channel enabledV01

2.5 typicalM

70 typical

0.9 typicalpF

Channel deselected

0.9 typical

Chip disabled

0.9 typicalSee footnotes at end of table.

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CODE IDENT NO.

DWG NO.

A

16236

V62/09616

REVPAGE

6

TABLE I. Electrical performance characteristics – Continued. 1/Test

SymbolConditions 2/ 3/ 4/

Temperature,
TADevice
typeLimits
MinUnitMax

Output section
Output voltage swing

VOUTRL  1 k

RL = 150 

Output current

IOUT-55C to +125C

3.55+25C3.55-55C to +125C

3.3501+25C

VO = 0 V

3.901+25CV

48mA

38-55C to +125C
Short circuit output
current

IOS

Output shorted to ground+25C01

100 typicalmA

Closed loop output
impedance

ZCLO

G = +2 V/V, f  100 kHz+25C01

0.03 typicalIPD

V EN = 0 V+25C01

3.6mA

ENABLE ( EN ) section
Power down supply
current

4.3-55C to +125C
Disable timetD

VIN = 0.25 VDC+25C01

25 typicalns

Enable timetE

VIN = 0.25 VDC

+25C

01

6 typicalns

Off isolation

OI

G = +2 V/V, f = 10 MHz+25C01

88 typicaldB

Output resistance indisable

ROD+25C

01

14 typicalM

Output capacitance indisable

COD+25C

01

2.5 typical

pF

See footnotes at end of table.

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CODE IDENT NO.

DWG NO.

A

16236

V62/09616

REVPAGE

7

TABLE I. Electrical performance characteristics – Continued. 1/Test

SymbolConditions 2/ 3/ 4/

Temperature,TADevicetypeLimits
MinUnitMax

Digital inputs section
Maximum logic 0

VL001+25C

A0, A1, EN , SD

0.80.8-55C to +125C
Maximum logic 1

VL101+25C

A0, A1, EN , SD

ILIlineOutput switching glitch

VOSG

01+25C

A0, A1, EN , SD, input = 0 V each

01+25CV40

A55-55C to +125C

Channel selection, at matched load

2.02.0-55C to +125C
Logic input currentV20 typical

Channel disable, at matched load

40 typical

Shutdown, at matched load

40 typicalmVShutdown (SD) section
Shutdown supply
current

ISD

01

+25C

VSD = 0 V

1.3mA

2.0-55C to +125C
Shutdown timetSD

VIN = 0.25 VDC

+25C

01

75 typicalns

Enable timet EN

VIN = 0.25 VDC

+25C

01

15 typicalns

Off isolation

OI

G = +2 V/V, f = 10 MHz

+25C

01

88 typicaldB

Output resistance in
shutdown

RSD+25C

01

14 typicalM

Output capacitance inshutdown

CSD

+25C

01

2.5 typicalpF

See footnotes at end of table.

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CODE IDENT NO.

DWG NO.

A

16236

V62/09616

REVPAGE8TABLE I. Electrical performance characteristics – Continued. 1/TestSymbolConditions 2/ 3/ 4/Temperature,
TADevice
typeLimits
MinUnitMax

Power supply section
Specified operating
voltage

VS+25C01

Minimum operating
voltageVS(min)

+25C

01

3.5V

6.001+25CVS(max)IQ(max)VS = 5 V

01

+25C

11IQ(min)

VS = 5 V

01+25C+PSRR

Input referred-PSRR

1/01+25C

10mA

8.25-55C to +125C
Power supply rejection
ratiomA12.5-55C to +125C
Minimum quiescentcurrentV6.0-55C to +125C
Maximum quiescentcurrentV3.5-55C to +125C
Maximum operating
voltage5 typical-50-55C to +125C-42+25C-51-55C to +125C-43

dB2/Testing and other quality control techniques are used to the extent deemed necessary to assure product performance overthe specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
Unless otherwise specified, VS = 5 V, gain (G) = +2 V/V, feedback resistance (RF) = 523 , and load resistance (RL) = 150 .

3/Junction temperature = ambient for +25C tested specifications.

4/Junction temperature = ambient at low temperature limit; junction temperature = ambient +9C at high temperature limit for overtemperature specifications.

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CODE IDENT NO.

DWG NO.

A16236

V62/09616

REVPAGE

9Case Xbl-$-1. 010 co. 251®111E El

PIN 1INDEX AR
Dl_A♦
c: : ,c::::,c::::,c::::,c::::::::I

c::::::::I

c::::::::I_[Al•

FIGURE 1. Case outline.

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CODE IDENT NO.

DWG NO.

A

16236

V62/09616

REVPAGE

10

Case X – continued.

Dimensions
SymbolInchesMillimeters

Min

Max

Min

Max

A

---.069---1.75

A1.004.010

0.100.25

b.012.020

0.31

0.51

c.005.010

0.130.25

D.337

.344

8.55

8.75

e.050 BSC

1.27 BSC

E.150

.157

3.80

4.00

E1.228

.244

5.80

6.20

L.016.050

0.40

1.27n14 leads

14 leads

NOTES:
1. Controlling dimensions are inch, millimeter dimensions are given for reference only.
2. For dimension D, body length does not include mold flash, protrusion, or gate burrs. Mold flash, protrusion, orgate burrs shall not exceed 0.006 inch (0.15 mm) per end.
3. For dimension E, body width does not include interlead flash. Interlead flash shall not exceed
0.017 inch (0.43 mm) per side.
4. Falls within JEDEC MS-012 variation AB.

FIGURE 1. Case outline - Continued.

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CODE IDENT NO.

DWG NO.

A16236

V62/09616

REVPAGE11

Device type01

Case outline

X

Terminal number

Terminal
symbolDescription

1

IN 0

Device input 02

GNDGround

3IN 1

Device input 1

4GND

Ground5

IN 2

Device input 2

6-VS

Negative supply voltage

7

IN 3

Device input 3

8A0

Channel control pin 09A1

Channel control pin 1

10EN

Chip enable11SDShutdown

12FB

Feedback

13OUT

Device output

14+VS

Positive supply voltage

FIGURE 2. Terminal connections.

A0A1ENSD

VOUT0000

INPUT 01000

INPUT 10100

INPUT 21100

INPUT 3X

X

10High Z, IQ = 3.4 mA

X

X

X

1High Z, IQ = 1.1 mA

FIGURE 3. Truth table.

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CODE IDENT NO.

DWG NO.

A

16236

V62/09616

REV

PAGE

12TOP VIEW

IND

14 +Vs

GND

OUT

IN1FB

GND

SD

IN2ENuHl!)

0_J-VsAl

IN3AO

FIGURE 4. Logic diagram.

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CODE IDENT NO.

DWG NO.

A

16236

V62/09616

REVPAGE13

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.

5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.

6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item.

Vendor item drawing
administrative control
number 1/ 2/Device
manufacturer
CAGE code

Packagemarking 3/

Transport
media,
quantity

Vendor part number

V62/09616-01XE

01295

OPA4872M

Tape and reel,
2500

OPA4872MDREP

1/ The vendor item drawing establishes an administrative control number for identifying the item on theengineering documentation.
2/ For the most current package and ordering information, see the package option addendum at theend of the manufacturer’s data sheet , or use website www.ti.com.
3/ Package drawings, standard packaging quantities, thermal data, symbolization, and printed
circuit board (PCB) design guidelines are available at www.ti.com/sc/package.

CAGE code01295

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Source of supply
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493

SIZE

CODE IDENT NO.

DWG NO.

A16236

V62/09616

REV

PAGE14