REVISIONSLTR

DESCRIPTIONDATEAPPROVEDA

Add device quantity in Section 6.3. Update
boilerplate to current MIL-PRF-38535
requirements. - PHN

18-08-09

Thomas M. HessB

Update boilerplate paragraphs to current VID
description requirements. - PHN

23-11-20

Muhammad A. Akbar

CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24

Vendor item drawing

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REV STATUS
OF PAGESPMIC N/A

PREPARED BY
Phu H. Nguyen

Original date of drawing

14-04-07

TITLE

CHECKED BYYY-MM-DD

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO 43218-3990
https://www.dla.mil/landandmaritime

Phu H. Nguyen
APPROVED BYMICROCIRCUIT, DIGITAL, MIXED SIGNALMICROCONTROLLER, MONOLITHIC SILICON

Thomas M. Hess
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A
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CODE IDENT. NO.

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V62/13624

16236
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AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.

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OF

38
5962-V016-24

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance mixed signal microcontroller microcircuit, with
an operating temperature range of -40°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/13624-

Drawing
number

01

X

A

Device type
(See 1.2.1)

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic

01

Circuit function

MSP430F2132-EP

Mixed signal microcontroller

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

Package style

X

32

JEDEC MO-220

Plastic quad flatpack no-lead

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
F
Z
1.3 Absolute maximum ratings.

Material
Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy
Other

1/

Voltage applied at VCC to VSS ............................................................................................... -0.3 V to 4.1 V
Voltage applied to any pin .................................................................................................... -0.3 V to VCC + 0.3 V
Diode current at any device terminal .................................................................................... ±2 mA
Storage temperature range, TSTG
(Unprogrammed device) ................................................................................................... -55°C to 150°C 3/(Programmed device) ....................................................................................................... -55°C to 150°C 3/2/__________
1/

2/
3/

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltages referenced to VSS. The JTAG fuse blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
is applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification withpeak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

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1.4 Recommended operating conditions. 4/
Supply voltage during program execution (VCC) AVCC – DVCC = VCC :During program execution ............................................................................................. 1.8 V to 3.6 V
During flash memory programming ............................................................................... 2.2 V to 3.6 V
Supply voltage (VSS) AVSS = DVSS = VSS ............................................................................... 0.0 V
Processor frequency fSYSTEM range (Maximum MCLK frequency): 5/ 6/ See figure 4.
VCC = 1.8 V, Duty Cycle 50% ±10% .............................................................................. dc to 6 MHz
VCC = 2.7 V, Duty Cycle 50% ±10% .............................................................................. dc to 12 MHz
VCC ≥ 3.3 V, Duty Cycle 50% ±10% .............................................................................. dc to 16 MHz
Operating free air temperature range, TA ............................................................................. -40°C to 125°C
1.5 Thermal characteristics.
Thermal metric

7/

Case outline X

Units

33.2
24.3
7.3
0.3
7.3
2.3

°C/W

Junction to ambient thermal resistance, θJA 8/
Junction to case (top) thermal resistance, θJCtop 9/
Junction to board thermal resistance, θJB 10/
Junction to top characterization parameter, ΨJT 11/
Junction to board characterization parameter, ΨJB 12/
Junction to case (bottom) thermal resistance, θJCbot 13/__________
4/

Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
5/ Modules might have a different maximum input clock specification. Refer to the data sheet from the manufacturer.
6/ The MSP430F2132 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse durationof the specified maximum frequency.
7/ For more information about traditional and new thermal metrics, see manufacturer data.
8/ The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-Kboard, as specified in JESD51-7, in an environment described in JESD51-2a.
9/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
10/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the
PCB temperature, as described in JESD51-8.
11/ The junction to top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
12/ The junction to board characterization parameter, ΨJB, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
13/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No
specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88

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2. APPLICABLE DOCUMENTSJEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)JEP95
JESD51JESD51-2a
JESD51-7
JESD51-8
J-STD-020

–
–
–
–
–
–

Registered and Standard Outlines for Semiconductor Devices
Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device).
Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still Air)High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Integrated Circuits Thermal Test Method Environment Conditions – Junction-to-board
Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state
surface mount devices.

(Copies of these documents are available online at https://www.jedec.org.)AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD
ANSI SEMI STANDARD G30-88– Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic
Packages(Copies of these documents are available online at https://www.ansi.org)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3.
3.5.4 Operating area. The operating area shall be as shown in figure 4.
3.5.5 POR and BOR vs supply voltage. The POR and BOR vs supply voltage shall be as shown in figures 5.
3.5.6 VCC(drop) level with a square voltage drop to generate a POR or BOR signal. The VCC(drop) level with a square voltage drop to
generate a POR or BOR signal shall be as shown in figure 6.

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3.5.7

VCC(drop) level with a triangle voltage drop to generate a POR or BOR signal. The VCC(drop) level with a square voltage drop to
generate a POR or BOR signal shall be as shown in figure 7.

3.5.8

LFXT1 Oscillator in HF mode (XTS = 1). The LFXT1 Oscillator in HF mode (XTS = 1) shall be as shown in figure 8.

3.5.9

SPI master mode, CKPH = 0. The SPI master mode, CKPH = 0 shall be as shown in figure 9.

3.5.10 SPI master mode, CKPH = 1. The SPI master mode, CKPH = 1 shall be as shown in figure 10.
3.5.11 SPI slave mode, CKPH = 0. The SPI slave mode, CKPH = 0 shall be as shown in figure 11.
3.5.12 SPI slave mode, CKPH = 1. The SPI slave mode, CKPH = 1 shall be as shown in figure 12.
3.5.13 I2C mode timing. The I2C mode timing shall be as shown in figure 13.
3.5.14 Comparator_A+ module block diagram. The Comparator_A+ module block diagram shall be as shown in figure 14.
3.5.15 Overdrive definition. The overdirve definition shall be as shown in figure 15.
3.5.16 Comparator_A+ short resistance test condition. The comparator_A+ short resistance test condition shall be as shown infigure 16.
3.5.17 Typical comparator A+. The typical comparator A+ shall be as shown in figure 17.

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TABLE I. Electrical performance characteristics.
Test

SymbolActive mode (AM) current(1 MHz)Active mode (AM) current(4 kHz)Active mode (AM) current(100 kHz)

IAM,
1 MHz

IAM,
1 MHz

IAM,
4 kHz

IAM,
100 kHzTA

Conditions 2/
unless otherwise specified

Active mode supply current (into DVCC + AVCC ) excluding external current
Active mode (AM) current(1 MHz)1/
Limits
Min

Unit

Typ

Max

2.2 V

250

345

3V

350

455

2.2 V

220

3V

300

-40°C to
85°C
125°C

2.2 V

2

-40°C to
85°C
125°C

3V

-40°C to
85°C

2.2 V

3/ 4/ .

fDCO = fMCLK = fSMCLK = 1 MHz,fACLK = 32,768 Hz,
Program executes from flash,
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 1 MHz,fACLK = 32,768 Hz,
Program executes in RAM,BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fMCLK = fSMCLK= fACLK = 32,768 Hz/8 = 4096 Hz,
fDCO = 0 Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCGO = 0, SCG1 = 0,
OSCOFF = 0
fMCLK = fSMCLK= fDCO(0,0) ≈ 100 kHz,fACLK = 0 Hz,
Program executes in flash,
RSELx = 0, DCOx = 0,
CPUOFF = 0, SCGO = 0, SCG1 = 0,
OSCOFF = 1

VCC

µA

µA

5

µA

7
3

7
10

60

85

µA

95

125°C
3V

-40°C to
85°C

72

95
105

125°C

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.
Test

SymbolTA

Conditions 2/
unless otherwise specified

1/
VCC

LimitsMin

Low-power mode supply current (into VCC) excluding external current 3/ 4/
fMCLK = 0 MHz, fSMCLK= fDCO = 1 MHz,
-40°C to 85°C
Low power mode 0,
ILPM0,fACLK = 32,768 Hz,
105°C(LPM0) current 5/
BCSCTL1 = CALBC1_1MHz,
1 MHz-40°C to 85°C
DCOCTL = CALDCO_1MHz,CPUOFF = 1, SCG0 = 0, SCG1 = 0,105°C
OSCOFF = 0
fMCLK = 0 MHz, fSMCLK= fDCO(0,0) ≈ 100 kHz,
-40°C to 85°C
Low power mode 0,
ILPM0,fACLK = 0 Hz,
125°C(LPM0) current 5/
RSELx = 0, DCOx = 0, CPUOFF = 1,
100 kHz-40°C to 85°C
SCGO = 0, SCG1 = 0, OSCOFF = 1

2.2 V

Typ

Max

55

66

Low power mode 3(LPM3) current 6/

Low power mode 3
current (LPM3) 6/

ILPM2

ILPM3,LFXT1

ILPM3,VLO

fMCLK = fSMCLK= 0 MHz, fDCO = 1 MHz,fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0 MHz,fACLK = 32,768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0

fDCO = fMCLK = fSMCLK = 0 MHz,fACLK from internal LF oscillator (VLO),CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0-40°C to 85°C

3V

70

2.2 V

33

ILPM4

fDCO = fMCLK = fSMCLK = 0 MHz,fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1

3V

37

µA

46
50

2.2 V

20

25

µA

29
3V

22

27
33

125°C
-40°C to 25°C
85°C
105°C

2.2 V

-40°C to 25°C
85°C

3V

105°C
-40°C to 25°C

2.2 V

85°C
125°C
-40°C to 25°C

3V

-40°C
25°C

42
46

85°C
125°C
Low power mode 4
current (LPM4) 7/

83
90

125°C
-40°C to 85°C

µA

68

125°C
Low power mode 2(LPM2) current 6/

Unit

2.2 V,
3V

85°C
125°C

0.7

1.2

1.6
3

2.3
6

0.9
1.6

1.9
2.8

3
0.3
1.2

7
0.7
1.9

2
0.7

6
0.8

1.4
2.5

2.1
6.5

0.1
0.1
0.8

0.5
0.5
1.5

2

4.5

µA

µA

µA

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.
Test

SymbolConditions 2/
unless otherwise specified

Schmitt Trigger inputs (Ports P1, P2, P3, JTAG, ������𝐑𝐑𝐑𝐑𝐑𝐑/NMI, XIN
Positive-going input
VIT+
threshold voltage
Negative-going input
threshold voltage

VIT-

Input voltage hysteresis(VIT+ - VIT-)
Pullup/Pulldown resistor

Vhys

Input capacitance
Inputs (Ports P1, P2)
External interrupt timing

CI

RPull

t(int)

Leakage current (Ports P1, P2, P3)
High impedance leakage current
IIkg(Px.y)
Outputs (Ports P1, P2, P3)
High level output voltage

VOH

Low-level output voltage

VOL

Outputs frequency (Ports P1, P2, P3) 14/
Port output frequency (with load)
fPx.y
Clock output frequency
POR/brownout reset (BOR)
See Figure 5

fPort°CLK

VCC

2.2 V
3V

2.2 V, 3 V

10/

2.2 V, 3 V

11/

IOH(max) = -1.5 mA 12/
IOH(max) = -6 mA 13/
IOH(max) = -1.5 mA 12/
IOH(max) = -6 mA 13/
IOL(max) = 1.5 mA 12/
IOL(max) = 6 mA 13/
IOL(max) = 1.5 mA 12/
IOL(max) = 6 mA 13/

2.2 V

P1.4/SMCLK, CL = 20 pF,
RL = 1 kΩ 14/ 15/
P2.0/ACLK/CA2, P1.4/SMCLK,
CL = 20 pF 15/

2.2 V
3V
2.2 V
3V

V(B_IT-)
Vhys(B_IT-)

dVCC/dt ≤ 3 V/s
dVCC/dt ≤ 3 V/s

See Figure 5

td(BOR)t(reset)TypMax

0.45 VCC
0.95
1.30
0.25 VCC
0.50
0.70
0.15
0.25
19

35

0.75 VCC
1.70
2.30
0.55 VCC
1.25
1.70
1.05
1.05
52

V

V

V
kΩ

5

Port P1, P2: P1.x to P2.x,
external trigger pulse width toset interrupt flag. 9/

See Figure 5 through 7
See Figure 5

Unit

8/ )

Pullup: VIN = VSS,
Pulldown: VIN = VCC
VIN = VSS or VCC

dVCC/dt ≤ 3 V/s

Limits
Min

2.2 V
3V
2.2 V
3V

18/
VCC(start)�����/NMI pin to
Pulse length at RST
accept a reset

17/

1/

3V
2.2 V
3V

pF

20

ns

VCC – 0.3
VCC – 0.65
VCC – 0.3
VCC – 0.65
VSS
VSS
VSS
VSS

±51

nA

VCC
VCC
VCC
VCC
VSS + 0.3
VSS + 0.65
VSS + 0.3
VSS + 0.65

V

7.5
12
7.5
16

MHz

V

MHz

0.7 x
V(B_IT-)65
2.2 V, 3 V

130

V
1.75
215

V
mV

2000

µs
µs

2

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.
Test

SymbolConditions 2/
unless otherwise specified

1/

VCC

Limits
Min

Typ

Unit
Max

DCO frequency

fDCO(0, 0)
fDCO(0, 3)
fDCO(1, 3)
fDCO(2, 3)
fDCO(3, 3)
fDCO(4, 3)
fDCO(5, 3)
fDCO(6, 3)
fDCO(7, 3)
fDCO(8, 3)
fDCO(9, 3)
fDCO(10, 3)
fDCO(11, 3)
fDCO(12, 3)
fDCO(13, 3)
fDCO(14, 3)
fDCO(15, 3)
fDCO(15, 7)
SRSEL

RSELx < 14
RSELx = 14
RSELx = 15
RSELx = 0, DCOx = 0, MODx = 0
RSELx = 0, DCOx = 3, MODx = 0
RSELx = 1, DCOx = 3, MODx = 0
RSELx = 2, DCOx = 3, MODx = 0
RSELx = 3, DCOx = 3, MODx = 0
RSELx = 4, DCOx = 3, MODx = 0
RSELx = 5, DCOx = 3, MODx = 0
RSELx = 6, DCOx = 3, MODx = 0
RSELx = 7, DCOx = 3, MODx = 0
RSELx = 8, DCOx = 3, MODx = 0
RSELx = 9, DCOx = 3, MODx = 0
RSELx = 10, DCOx = 3, MODx = 0
RSELx = 11, DCOx = 3, MODx = 0
RSELx = 12, DCOx = 3, MODx = 0
RSELx = 13, DCOx = 3, MODx = 0
RSELx = 14, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 7, MODx = 0
SRSEL = fDCO(RSEL+1, DCO)/fDCO(RSEL, DCO)

2.2 V, 3 V

SDCO

SDCO = fDCO(RSEL, DCO+1)/fDCO(RSEL, DCO)

2.2 V, 3 V

1.04

1.08

1.13

ratio

Measured at P1.4/SMCLK

2.2 V, 3 V

35

50

65

%

Supply voltage range

VCC

DCO frequency (0, 0)
DCO frequency (0, 3)
DCO frequency (1, 3)
DCO frequency (2, 3)
DCO frequency (3, 3)
DCO frequency (4, 3)
DCO frequency (5, 3)
DCO frequency (6, 3)
DCO frequency (7, 3)
DCO frequency (8, 3)
DCO frequency (9, 3)
DCO frequency (10, 3)
DCO frequency (11, 3)
DCO frequency (12, 3)
DCO frequency (13, 3)
DCO frequency (14, 3)
DCO frequency (15, 3)
DCO frequency (15, 7)
Frequency step
between range RSEL
and RSEL+1
Frequency step
between tap DCO and
DCO+1
Duty cycle

2.2 V, 3 V

3V

1.8
2.2
3.0
0.055
0.065
0.095
0.135
0.195
0.27
0.38
0.53
0.70
1.05
1.50
2.40
2.90
4.20
5.90
8.50
11.5
15.5

3.6
3.6
3.6
0.145
0.175
0.205
0.285
0.405
0.55
0.78
1.07
1.60
2.20
3.10
4.40
5.60
7.40
9.70
14.0
19
26.5
1.56

V

MHz

ratio

See footnotes at end of table.

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9TABLE I. Electrical performance characteristics – Continued.
Test

SymbolTA

Conditions 2/
unless otherwise specified

1/

VCC

Calibrated DCO frequencies - tolerance at calibration
Frequency tolerance at
25°C
calibration
25°C
1 MHz calibration valuefCAL(1 MHz) BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
Gating time: 5 ms
25°C
8 MHz calibration valuefCAL(8 MHz) BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5 ms
BCSCTL1= CALBC1_12MHz,
25°C
12 MHz calibrationfCAL(12 MHz)DCOCTL = CALDCO_12MHz,
value
Gating time: 5 ms
25°C
16 MHz calibrationfCAL(16 MHz) BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
value
Gating time: 2 ms
Calibrated DCO frequencies - tolerance over temperature range 0°C to 85°C
1 MHz tolerance over
0°C to 85°C
temperature
8 MHz tolerance over
0°C to 85°C
temperature
12 MHz tolerance over
0°C to 85°C
temperature
16 MHz tolerance over
0°C to 85°C
temperature
0°C to 85°C
1 MHz calibration valuefCAL(1 MHz) BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
Gating time: 5 ms
8 MHz calibration valuefCAL(8 MHz)BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5 ms

0°C to 85°C

12 MHz calibration
value

fCAL(12 MHz)BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,
Gating time: 5 ms

0°C to 85°C

16 MHz calibration
value

fCAL(16 MHz)BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
Gating time: 2 ms

0°C to 85°C

Limits

Unit

Min

Typ

Max

3V

-1

±0.2

1

%

3V

0.990

1

1.010

MHz

3V

7.920

8

8.080

MHz

3V

11.88

12

12.12

MHz

3V

15.84

16

16.16

MHz

3V

-2.5

±0.5

+2.5

%

3V

-2.5

±1

+2.5

%

3V

-2.5

±1

+2.5

%

3V

-3.0

±2

+3.0

%

2.2 V
3V
3.6 V
2.2 V
3V
3.6 V
2.2 V
3V
3.6 V
3V
3.6 V

0.970
0.975
0.970
7.760
7.800
7.600
11.64
11.64
11.64
15.52
15.00

1
1
1
8
8
8
12
12
12
16
16

1.030
1.025
1.030
8.400
8.200
8.240
12.36
12.36
12.36
16.48
16.48

MHz

MHz

MHz

MHz

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.
Test

SymbolTA

Conditions 2/
unless otherwise specified

Calibrated DCO frequencies - tolerance over supply voltage VCC
1 MHz tolerance
over VCC
8 MHz tolerance
over VCC
12 MHz tolerance
over VCC
16 MHz tolerance
over VCC
1 MHz calibration valuefCAL(1 MHz) BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
Gating time: 5 ms
8 MHz calibration valuefCAL(8 MHz) BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5 ms
12 MHz calibrationfCAL(12 MHz) BCSCTL1 = CALBC1_12MHz,
value
DCOCTL = CALDCO_12MHz,
Gating time: 5 ms
16 MHz calibrationfCAL(16 MHz) BCSCTL1 = CALBC1_16MHz,
value
DCOCTL = CALDCO_16MHz,
Gating time: 2 ms
Calibrated DCO frequencies - overall tolerance
1 MHz tolerance overall
8 MHz tolerance overall
12 MHz tolerance
overall
16 MHz tolerance
overall

VCC

fCAL(1 MHz)

8 MHz calibration valuefCAL(8 MHz)

12 MHz calibration
value

fCAL(12 MHz)

16 MHz calibration
value

fCAL(16 MHz)BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
Gating time: 5 ms
BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5 ms
BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,
Gating time: 5 ms
BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
Gating time: 2 ms

Limits
Min

Unit
Max

25°C

1.8 V to 3.6 V

-3

±2

3

%

25°C

1.8 V to 3.6 V

-3

±2

3

%

25°C

2.2 V to 3.6 V

-3

±2

3

%

25°C

3 V to 3.6 V

-6

±2

3

%

25°C

1.8 V to 3.6 V

0.97

1.03

MHz

25°C

1.8 V to 3.6 V

7.76

8.24

MHz

25°C

2.2 V to 3.6 V

11.64

12.36

MHz

25°C

3 V to 3.6 V

15.00

16.48

MHz

-40°C to 125°C 1.8 V to 3.6 V-40°C to 125°C 1.8 V to 3.6 V-40°C to 125°C 2.2 V to 3.6 V

-6

±2

+6

%

-6
-6

±2
±2

+6
+6

%
%

3 V to 3.6 V

-7

±3

+7

%

-40°C to 125°C 1.8 V to 3.6 V

0.94

1

1.06

MHz

-40°C to 125°C 1.8 V to 3.6 V

7.5

8

8.5

MHz

-40°C to 125°C 2.2 V to 3.6 V

11.3

12

12.7

MHz

3 V to 3.6 V

14.9

16

17.1

MHz

-40°C to 125°C

1 MHz calibration value

1/-40°C to 125°C

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.
Test

SymbolVCC

Conditions 2/
unless otherwise specified

Dt

LimitsMin

Wake up from lower power modes (LPM3/4) 14/
BCSCTL1 = CALBC1_1MHz,
DCO clock wake up
tDCO,LPM3/4 DCOCTL = CALDCO_1MHz
time from LPM3/4
BCSCTL1 = CALBC1_8MHz,
19/
DCOCTL = CALDCO_8MHzBCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHzBCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz
CPU wake-up time from tCPU,LPM3/4
LPM3/4 20/
DCO with external resistor ROSC 23/
DCO output frequency
fDCO,ROSC DCOR = 1, RSELx = 4, DCOx = 3,
MODx = 0
with ROSC
Temperature drift

1/

DCOR = 1, RSELx = 4, DCOx = 3,
MODx = 0
Drift with VCC
DV
DCOR = 1, RSELx = 4, DCOx = 3,
MODx = 0
Crystal Oscillator, LFXT1, low frequency modes 22/ 23/
LFXT1 oscillator
fLFXT1,LF
XTS = 0, LFXT1Sx = 0 or 1
crystal frequency,
LF mode 0,1
XTS = 0, LFXT1Sx = 3,
LFXT1 oscillator logic
fLFXT1,LF,
logic
XCAPx = 0
level square wave
input frequency,
LF modeOscillation allowance
OALF
XTS = 0, LFXT1Sx = 0,
for LF crystal
fLFXT1,LF = 32,768 Hz, CL,eff = 6 pF
XTS = 0, LFXT1Sx = 0;
fLFXT1,LF = 32,768 Hz, CL,eff = 12 pF
Integrated effective load
CL,eff
XTS = 0
XCAPx = 0
capacitance, LF mode
XCAPx = 1
24/
XCAPx = 2
XCAPx = 3
LF mode duty cycle
Duty
XTS = 0, measured at P1.4/ACLK,
cycle
fLFXT1,LF = 32,768 Hz
Oscillator fault
fFault,LF
XTS = 0, LFXT1Sx = 3,
frequency, LF mode
XCAPx = 0 26/
25/

Unit
Max

2.2 V, 3 V

2

µs

1.5
1
3V

1
1/fMCLK +tClock,LPM3/4

2.2 V
3V

1.8
1.95

MHz

2.2 V, 3 V

±0.1

%/°C

2.2 V, 3 V

10

%/V

1.8 V to
3.6 V

32,768Hz

1.8 V to
3.6 V

10,00032,76850,000

500

Hz

kΩ

200

2.2 V, 3 V

30

2.2 V, 3 V

10

1
5.5
8.5
11
50

pF

70

%

10,000Hz

See footnotes at end of table.

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12TABLE I. Electrical performance characteristics – Continued.
Test

Symbol1/

VCC

Conditions 2/
unless otherwise specified

Limits

Unit

Min

Typ

Max

4

12

20
23

Internal very low power, Low frequency oscillator (VLO)
VLO frequency

TA = -40°C to 85°C

fVLO

TA = 125°C

VLO frequency
dfVLO/dT
27/
temperature drift
VLO frequency supply
dfVLO/dVCC
28/
voltage drift
Crystal oscillator, LFXT1, high frequency modes 23/ 29/
LFXT1 oscillator crystal
fLFXT1,HF0
XTS = 1, LFXT1Sx = 0,
frequency, HF mode 0
XCAPx = 0
LFXT1 oscillator crystal
fLFXT1,HF1
XTS = 1, LFXT1Sx = 1,
frequency, HF mode 1
XCAPx = 0
LFXT1 oscillator crystal
fLFXT1,HF2
XTS = 1, LFXT1Sx = 2,
frequency, HF mode 2
XCAPx = 0
LFXT1 oscillator logic
level square wave
input frequency,
HF modefLFXT1,HF,logic

Oscillation allowancefor HF crystals
See figure 8

OAHF

Integrated effective load
capacitance, HF mode24/
HF mode duty cycle

XTS = 1, LFXT1Sx = 3,
XCAPx = 0

CL,effDuty cycle

Oscillator fault frequency,
HF mode 25/

fFault,HF

2.2 V, 3 V
2.2 V, 3 V

0.5

%/°C

1.8 V to 3.6 V

4%/V

1.8 V to 3.6 V

0.4

1

MHz

1.8 V to 3.6 V

1

4

MHz

1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V

2
2
2
0.4
0.4
0.4

10
12
16
10
12
16

MHz

XTS = 1, XCAPx = 0, CL,eff = 15 pF,
LFXT1Sx = 0, fLFXT1,HF = 1 MHz
XTS = 1, XCAPx = 0, CL,eff = 15 pF
LFXT1Sx = 1, fLFXT1,HF = 4 MHz
XTS = 1, XCAPx = 0, CL,eff = 15 pF
LFXT1Sx = 2, fLFXT1,HF = 16 MHz
XTS = 1, XCAPx = 0 30/

XTS = 1, XCAPx = 0,
measured at P1.4/ACLK,fLFXT1,HF = 10 MHz
XTS = 1, XCAPx = 0,
measured at P1.4/ACLK,fLFXT1,HF = 16 MHz
XTS = 1, LFXT1Sx = 3, XCAPx = 0
26/

kHz

MHz

2700

Ω

800
300
1

pF

2.2 V, 3 V

40

50

60

2.2 V, 3 V

40

50

60

2.2 V, 3 V

30

300

%

kHz

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.
Test

Symbol1/

VCC

Conditions 2/
unless otherwise specified

Limits
Min

Typ

Unit
Max

Timer0_A3
Timer0_A3 clock frequency

fTA

Timer0_A3, capture timing
Timer1_A2

fTA,cap

Timer1_A2 clock frequency

fTB

Timer1_A2, capture timing

fTB,cap

2.2 V
3VInternal: SMCLK, ACLK,
External: TACLK, INCLK,
Duty cycle = 50% ±10%TA0.0, TA0.1, TA0.2

10
16

2.2 V, 3 V

20

ns

2.2 V
3V

Internal: SMCLK, ACLK,
External: TBCLK,
Duty cycle = 50% ±10%TA1.0, TA1.1

10
16

2.2 V, 3 V

MHz

20

MHz

ns

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.
Test

SymbolUSCI (UART mode)
USCI input clock frequency

BITCLK clock frequency(equals baud rate in MBaud) 31/
UART receive deglitch time 32/
USCI (SPI Master mode) 33/
USCI input clock frequency
SOMI input data setup time

fUSCI

Limits
Min

tζ

2.2 V
3V

45
45

See figure 9 and 10
SMCLK, ACLK,
Duty cycle = 50% ±10%
tSU,MItVALID,MOUCLK edge to SIMO valid,
CL = 20 pF
USCI (SPI Slave mode) 34/ See figure 11 and 12
STE lead time, STE low to clocktSTE,LEAD
STE lag time, last clock to STE hightSTE,LAG
STE access time, STE low to SOMItSTE,ACC
data out
STE disable time, STE high totSTE,DISSOMI high impedance
SIMO input data setup time
tSU,SISIMO input data hold time

tHD,SISOMI output data validtVALID,SOUCLK edge to SOMI valid,
CL = 20 pF

USCI (I2C mode) See figure 13
USCI input clock frequency

fUSCIInternal: SMCLK, ACLK,
External: UCLK,
Duty cycle = 50% ±10%

SCL clock frequency
Hold time (repeated) STARTfSCLtHD,STA

Setup time for a repeated STARTtSU,STA

Max

150
100

2.2 V
3V
2.2 V
3V
2.2 V
3V

MHz

ns

fSYSTEM
110
75
0
0

MHz
ns

30
20

2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V

50

ns

10
50

2.2 V, 3 V

50

2.2 V
3V
2.2 V
3V
2.2 V
3V

20
15
10
10
75
50

2.2 V, 3 V
2.2 V, 3 V

fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz

Unit

fSYSTEM

2

SIMO output data valid

TypInternal: SMCLK, ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
2.2 V, 3 V

tHD,MI

14/

VCC

fBITCLKSOMI input data hold time
14/

Conditions 2/-55°C ≤ TA ≤ 125°C
unless otherwise specified

1/

0
4.0
0.6
4.7
0.6

2.2 V, 3 V

11075fSYSTEM

MHz

400

µs

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.
Test

USCI (I2C mode) - Continued
Data hold time
Data setup time
Setup time for STOP
Pulse width of spikes suppressedby input filter
Comparator_A+

SymboltHD,DATtSU,DATtSU,STOtSP

LimitsVCC
Min
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V
3V

0
250
4
45
45

Typ

Unit
Max
ns
ns
µs
ns

150
100

605
605

25
45
30
45

45
65
55
85

µA

VCC - 1

V

36/
I(DD)
I(Refladder/Refdiode)

Common mode input voltage range
14/

V(IC)

Voltage at 0.25 VCC node/ VCC

V(Ref025)

Voltage at 0.5 VCC node/ VCC

V(Ref050)

See figure 17

V(RefVT)

Offset voltage
Input hysteresis

Conditions 2/
unless otherwise specified

1/

36/

V(offset)Vhyst(response)

Response time, low to high andhigh to low 37/

CAON = 1, CARSEL = 0,
CAREF = 0
CAON = 1, CARSEL = 0,
CAREF = 1/2/3,
No load at CA0 and CA1
CAON = 1

2.2 V
3V
2.2 V
3V

µA

2.2 V, 3 V0

PCA0 = 1, CARSEL = 1,
CAREF = 1,
No load at CA0 and CA1
PCA0 = 1, CARSEL = 1,
CAREF = 2,
No load at CA0 and CA1

2.2 V, 3 V

0.225

0.24

0.255

V

2.2 V, 3 V

0.465

0.48

0.505

V

PCA0 = 1, CARSEL = 1,
CAREF = 3,
No load at CA0 and CA1
TA = 85°C

2.2 V
3V

360
370

480
490

570
580

mV

2.2 V, 3 V
2.2 V, 3 V
2.2 V
3V

-42
100
50

0.7
165
120

42
1.8
320
250

mV
mV
ns

2.2 V
3V

1.3
0.7

1.9
1.5

3.0
2.5

µs

CAON = 1
TA = 25°C, Overdrive 10 mV,
Without filter; CAF = 0
See figure 14 and 15
TA = 25°C, Overdrive 10 mV,
Without filter; CAF = 0
See figure 14 and 15

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.
Test

SymbolTA

Conditions 2/
unless otherwise specified

RI

0 V ≤ VAx ≤ VCC

VCC

LimitsMin

10 bit ADC, Power supply and input range conditions 38/
Analog supply voltage
VCC
VSS = 0 V
All Ax terminals,
Analog input voltage 39/
VAx
Analog inputs selected in
ADC10AE register
fADC10CLK = 5 MHz,ADC10 supply current
IADC10
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1, ADCSHT1 = 0,40/
ADC10DIV = 0
fADC10CLK = 5 MHz,ADC10ON = 0, REF2_5V = 0
REFON = 1, REFOUT = 0
Reference supply current,
IREF+
reference buffer disabled
fADC10CLK = 5 MHz,41/
ADC10ON = 0, REF2_5V = 1
REFON = 1, REFOUT = 0
fADC10CLK = 5 MHz,
Reference buffer supply
IREFB,0
ADC10ON = 1, REFON = 0,
current with ADC10SR = 0
REF2_5V = 0, REFOUT = 1,
41/
ADC10SR = 0
fADC10CLK = 5 MHz,
Reference buffer supply
IREFB,1
ADC10ON = 1, REFON = 0,
current with ADC10SR = 1
REF2_5V = 0, REFOUT = 1,
41/
ADC10SR = 1
Input capacitanceCI
Only one terminal Ax selected ata timeInput MUX ON resistance1/

2.2 V, 3 V

I: -40°C to 85°C
T= -40°C to
105°C

Typ

2.2
0

Unit
Max
3.6
VCC

V
V

mA

2.2 V

0.52

1.06

3V

0.6

1.25

I: -40°C to 85°C 2.2 V, 3 V
T= -40°C to
105°C
3V

0.25

0.45

0.25

0.45

-40°C to 85°C

1.1

1.4

mA

2.2 V, 3 V
1.85

125°C
-40°C to 85°C

mA

0.5
2.2 V, 3 V

0.7

mA

125°C

0.85

I: -40°C to 85°C
T= -40°C to
105°C

27

pF

2000

Ω

I: -40°C to 85°C
T= -40°C to
105°C

2.2 V, 3 V

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.
Test

Symbol1/

VCC

Conditions 2/
unless otherwise specified

Limits
Min

Typ

Unit
Max

10 bit ADC, Built in voltage reference
Positive built-in reference
analog supply voltage range

VCC,REF+

Positive built-in reference
voltage

VREF+

Maximum VREF+ load current

ILD,VFRE+

IVREF+ ≤ 1 mA, REF2_5V = 0
IVREF+ ≤ 0.5 mA, REF2_5V = 1
IVREF+ ≤ 1 mA, REF2_5V = 1
IVREF+ ≤ IVREF+max, REF2_5V = 0
IVREF+ ≤ IVREF+max, REF2_5V = 0

2.2 V, 3 V
3V
2.2 V
3V

IVREF+ = 500 µA ±100 µA,
Analog input voltage VAx ≈ 0.75 V,
REFD2_5V = 0
IVREF+ = 500 µA ±100 µA,
Analog input voltage VAx ≈ 0.75 V,
REFD2_5V = 1
IVREF+ = 100 µA to 900
ADC10SR = 0µA,
VAx ≈ 0.5 x VREF+,
ADC10SR = 1
Error of conversion result≤ 1 LSB

VREF+ load regulation

VREF+ load regulation
response time
14/

2.2
2.8
2.9
1.40
2.30

V

1.5
2.5

1.60
2.70
±0.5
±1

V
mA
LSB

2.2 V, 3 V

±2

3V

±2
400

3V

ns

2000

Maximum capacitance at pin
VREF+
42/

CVREF+

IVREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1

2.2 V, 3 V

100

pF

Temperature coefficient
43/
Setting time of internalreference voltage 14/ 45/

TCREF+

IVREF+ = constant with
0 mA ≤ IVREF+ ≤ 1 mA 44/

2.2 V, 3 V

±100
±110

ppm/°C

3.6 V

30

µs

1

µs

Settling time of reference
buffer 14/ 45/

tREFBURST-40°C to 85°C
-40°C to 105°C
IVREF+ ≤ 0.5 mA, REF2_5V = 0,
REFON = 0 to 1
IVREF+ ≤ 0.5 mA,
ADC10SR = 0
REF2_5V = 0,
REFON = 1,
ADC10SR = 1
REFBURST = 1
IVREF+ ≤ 0.5 mA,
ADC10SR = 0
REF2_5V = 1,
REFON = 1,
ADC10SR = 1
REFBURST = 1

2.2 V
2.5
2
3V
4.5

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.
Test

Symbol10 bit ADC, External reference

46/

Positive external reference
input voltage range 47/

VeREF+

Negative external reference
input voltage range 49/
Differential external reference
input voltage range∆VeREF = VeREF+ - VeREF-

VeREF∆VeREF

VeREF+ > VeREF-

ADC10 input clock frequency

fADC10CLKADC10 built in oscillator
frequency

fADC10OSC

Conversion timetCONVERT

Limits
Min

Typ

Unit
Max

1.4

VCC

V

1.4

3

V

0

1.2

V

1.4

VCC

V

±1

µA

48/

50/

0 V ≤ VeREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
0 V ≤ VeREF+ ≤ VCC – 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 1
48/

Static input current into VeREF14/
10 bit ADC, Timing parameters

Turn on settling time of the
ADC
14/

VCC

Conditions 2/
unless otherwise specified

VeREF+ > VeREF-,
SREF1 = 1, SREF0 = 0
VeREF- ≤ VeREF+ ≤ (VCC – 0.15 V),
SREF1 = 1, SREF0 = 1
VeREF+ > VeREF-

Static input current into VeREF+
14/

1/

2.2 V, 3 V
0

0 V ≤ VeREF+ ≤ VCC

2.2 V, 3 V

For specified performance of
ADC10 linearity parameters

2.2 V, 3 V

ADC10SR = 0
ADC10SR = 1
ADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
fADC10CLK from ACLK, MCLK or SMCLK,ADC10SSELx ≠ 0±1

2.2 V, 3 V

0.45
0.45
3.7

6.3
1.5
6.3

MHz
MHz

2.2 V, 3 V

2.06

4.00

µs

100

ns

51/

52/

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.
Test

SymbolVCC

Conditions 2/
unless otherwise specified

Source impedance RS < 100 Ω
SREFx = 010, unbuffered external reference,
VeREF+ = 1.5 V
SREFx = 010, unbuffered external reference,
Gain error
EG
VeREF+ = 2.5 V
SREFx = 011, unbuffered external reference,
VeREF+ = 1.5 V
53/
SREFx = 011, unbuffered external reference,
VeREF+ = 2.5 V
53/
SREFx = 010, unbuffered external reference,
VeREF+ = 1.5 V
SREFx = 010, unbuffered external reference,
Total unadjusted error
ET
VeREF+ = 2.5 V
SREFx = 011, unbuffered external reference,
VeREF+ = 1.5 V
53/
SREFx = 011, unbuffered external reference,
VeREF+ = 2.5 V
53/
10 bit ADC, Temperature sensor and built-in VMID
54/
Temperature sensor
ISENSORREFON = 0, INCHX = 0Ah,
supply current
ADC10ON = 1, TA = 25°C
TCSENSOR
ADC10ON = 1, INCHX = 0Ah 55/
Sensor offset voltage
VOffset,Sensor
ADC10ON = 1, INCHX = 0Ah 55/
Temperature sensor voltage at
TA = 125°C (Q version only)
Sensor output voltage
VSENSOR
Temperature sensor voltage at TA = 85°C
56/
Temperature sensor voltage at TA = 25°C
TSENSOR(sample)

Temperature sensor voltage at TA = 0°C
ADC10ON = 1, INCHX = 0Ah ,Error of conversion result ≤ 1 LSB

Current into divider atchannel 11
57/

IVMID

ADC10ON = 1, INCHX = 0Bh

VCC divider at channel 11

VMID

Sample time required ifchannel 11 is selected
58/

tVMID(sample)

ADC10ON = 1, INCHX = 0Bh,
VMID ≈ 0.5 x VCC
ADC10ON = 1, INCHX = 0Bh ,Error of conversion result ≤ 1 LSB

LimitsMin

10 bit ADC, Linearity parameters
Integral linearity error
EI
Differential linearity error
ED
Offset error
EO

Sample time required ifchannel 10 is selected 57/

1/
Unit

Typ

Max

2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V

±1.1

±1.2
±1.2
±1.2
±2

3V

±1.1

±2

2.2 V

±1.1

±4.5

3V

±1.1

±3.5

2.2 V

±2

±5

3V

±2

±5

2.2 V

±2

±7.5

3V

±2

±6.5

2.2 V
3V
2.2 V, 3 V

40
60
3.55

120
160

2.2 V, 3 V

2.2 V, 3 V
2.2 V
3V
2.2 V
3V
2.2 V
3V

-100
1205

1365

+100
1465

1195
985
895

1295
1085
995

1395
1185
1095

LSB

µA
mV/°C
mV
mV

31

1.05
1.45
1600
1600

µs
N/A
N/A
1.15
1.55

1.1
1.5

µA
V
ns

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.
Test

Flash memory
Program and erase supply voltage
Flash timing generator frequency
Supply current from VCC during program 14/
Supply current from VCC during erase
14/
Cumulative program time
14/ 59/Cumulative mass erase time
14/
Program and Erase endurance
Data retention duration
Word or byte program time
Block program time for first byte or word
Block program time for each additional byte or
word
Block program end-sequence wait time
Mass erase time
Segment erase timeRAM
RAM retention supply voltage 61/
JTAG and Spy-Wire interface
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse duration

SymboltRetention

63/

Min

2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V

tBlock, 1-63
tBlock, End
tMass ErasetSeg Erase

60/
60/
60/

VRAMh

CPU halted

tBlock, 0

Typ

2.2
257

TJ = 25°C
60/
60/
60/

tWord

Limits

VCC

VCC(PGM/ERASE)
fFTG
IPGM
IERASEtCPT
tCMErase

Spy-Bi-Wire enable time
(TEST high to acceptance of first clockedge 62/)
Spy-Bi-Wire return to normal operation time
TCK input frequency

Conditions 2/
unless otherwise
specified

1/

Max
3.6
476
5
7
10

1
1
20
104
100

Unit

105
30
25
18

V
kHz
mA
mA
ms
ms
cycles
years
tFTG

6
10593
4819
1.6

TA = -40°C to 105°C
TA = -40°C to 105°C

2.2 V, 3 V
2.2 V, 3 V

TA = -40°C to 105°C

2.2 V, 3 V

TA = -40°C to 105°C

2.2 V, 3 V
2.2 V
3V
2.2 V, 3 V

fTCK

TA = -40°C to 105°C

Internal pulldown resistance on TESTRInternal

TA = -40°C to 105°C

JTAG fuse 64/
Supply voltage during fuse blow condition
Voltage level on TEST for fuse blow

VCC(FB)VFB

TA = 25°C
TA = 25°C

Supply current into TEST during fuse blow
Time to blow fuse

IFB
tFB

TA = 25°C
TA = 25°C

V

0
0.025

20
15

MHz
µs

1

µs

15

100

µs

0
0
25

5
10
90

MHz

60

2.5
6

kΩ

7

V
V

100
1

mA
ms

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.

1/

1/

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may notnecessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
2/ Over recommended ranges of supply voltage and operating free air temperature (unless otherwise noted). 3/ 4/
3/ All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
4/ The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal andexternal load capacitance is chosen to closely match the required 9 pF.
5/ Current for brownout and WDT clocked by SMCLK.
6/ Current for brownout and WDT clocked by ACLK.
7/ Current for brownout included.
8/ XIN only in bypass mode only.
9/ An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set with trigger
signals shorter than t(int).
10/ The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
11/ The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor isdisabled.
12/ The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to hold the maximum voltage
drop specified.
13/ The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
14/ Not ensured for TA > 105°C
15/ Alternatively, a resistive divider with 2 times 0.5 kΩ between VCC and VSS is used as load. The output is connected to the centertap of the divider.
16/ The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
17/ The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level
V(B_IT-) + Vhys(B_IT-) is ≤ 1.8 V.
18/ During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-), The default DCO
settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
19/ The DCO clock wake up time is measured from the edge of an external wake up signal (e.g., port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK)
20/ Parameter applicable only if DCOCLK is used for MCLK.
21/ ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C.
22/ To improve EMI on the XT1 oscillator the following guidelines should be observed:
a. Keep the trace between the device and the crystal as short as possible.
b. Design a good ground plane around the oscillator pin.
c. Prevent crosstalk from other clock or data lines into oscillator pin XIN and XOUT.
d. Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
e. Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
f. If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between oscillator pins.
g. Do not rout the XOUT line to the JTAG header to support the serial programming adapter as shown in other data. This signal
is no longer required for the serial programming adapter.
23/ Use of the LFXT1 Crystal Oscillator at TA > 105°C is not ensured. It is recommended that an external digital clock source or theinternal DCO is used to provide clocking.
24/ Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it isrecommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitanceshould always match the specification of the used crystal.
25/ Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
26/ Measured with logic level input frequency, but also applies to operation with crystals.
27/ Calculated using the box method:I version: [MAX(-40°C to 85°C) – MIN(-40°C to 85°C)]/ MIN(-40°C to 85°C)]/[85°C – (-40°C)]
T version: [MAX(-40°C to 105°C) – MIN(-40°C to 105°C)]/ MIN(-40°C to 105°C)]/[105°C – (-40°C)]
28/ Calculated using the box method:[Max(1.8V to 3.6V) – MIN(1.8V to 3.6 V)]/MIN(1.8V to 3.6 V)/(3.6 V – 1.8 V)

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TABLE I. Electrical performance characteristics – Continued.
29/

30/
31/
32/

1/

To improve EMI on the XT2 oscillator the following guidelines should be observed:
a. Keep the trace between the device and the crystal as short as possible.
b. Design a good ground plane around the oscillator pin.
c. Prevent crosstalk from other clock or data lines into oscillator pin XIN and XOUT.
d. Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
e. Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
f. If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between oscillator pins.
g. Do not rout the XOUT line to the JTAG header to support the serial programming adapter as shown in other data. Thissignal is no longer required for the serial programming adapter.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
The DCO clock wake up time must be considered in LPM3 and LPM4 for baud rates above 1 MHz.
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that thepulses correctly recognized, their width should exceed the maximum specification of the deglitch time.

33/

fUCxCLK =34/

fUCxCLK =1
with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(slave))
2tLO/HIFor the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.

35/
36/
37/
38/
39/
40/
41/
42/
43/
44/
45/
46/
47/
48/
49/
50/
51/
52/

1
with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))
2tLO/HIFor the master parameters tSU,SI(Master) and tVALID,SO(Master), see the SPI parameters of the attached master.
The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.x) specification.
The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive
measurements. The two successive measurements are then summed together.
The response time is measured at P2.2 /TA0.0/CA4/CAOUT. If the Comparator_A+ is enabled a setting time of 60 ns (typical)
is added to the response time.
The leakage current is defined in the leakage current table with Px.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion result.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless aconversion is active. The REFON bit enables the built in reference. The reference voltage must be settle before an A/D
conversion is started.
The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/VREF+/VeREF+ (REFOUT =1), must be limited; otherwise, the reference buffer may become unstable.
Calculated using the box method:
I temperature: [MAX(-40°C to 85°C) – MIN(-40°C to 85°C)]/ MIN(-40°C to 85°C)]/[85°C – (-40°C)]
T temperature: [MAX(-40°C to 105°C) – MIN(-40°C to 105°C)]/ MIN(-40°C to 105°C)]/[105°C – (-40°C)].
Calculated using the box method: ((MAX(VREF(T)) – MIN(VREF(T))) / MIN(VREF(T))/ (TMAX – TMIN).
The condition is that the error in a conversion started after tREFON or tRefBuf is less than ±0.5 LSB.
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, isalso the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should
follow the recommendations on analog source impedance to allow the change to settle for 10 bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with
reduced accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with
reduced accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be
applied with reduced accuracy requirements.
13 x ADC10DIVx x 1/fADC10CLK.
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are
already settled.

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TABLE I. Electrical performance characteristics – Continued.
53/
54/
55/
56/
57/
58/
59/
60/
61/
62/
63/
64/

1/

The reference buffer offset adds to the gain and total unadjusted error.
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON =1 and INCH = 0Ah and sample
signal is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of thetemperature sensor input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor, typ = TCSensor (273 + T[°C] ) + VOffset,sensor [mV] or
VSensor, typ = TCSensor T[°C] ) + VSensor (TA = 0°C) [mV].
Results based on characterization and/or production test, not TCSensor or VOffset,sensor.
No additional current is needed. The VMID is used during sampling.
The on time, tVMID(on), is included in sampling time, tVMID(sample); no additional on time is needed.
The cumulative program time must not be exceeded when writing to a 64 byte flash block. This parameter applies to all
programming methods: individual word/byte write and block write modes.
These values are hardwired into the flash controller’s state machine (tFTG = 1/tFTG).
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution
should happen during this supply voltage condition.
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin highbefore applying the first SBWCLK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
Once the fuse is blown, no further access to the JTAG/Test and emulation features is possible, and the JTAG block is switched
to bypass mode.

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TABLE I. Electrical performance characteristics – Continued. 1/
58/
59/
60/
61/
62/
63/
64/
65/
66/
67/
68/
69/
70/
71/
72/
73/
74/
75/
76/
77/
78/
79/
80/
81/

No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see manufacturer reference
for more information.
PSRR = 20 x log{∆AVCC/∆VDAC12_xOUT}.
VREF is applied externally. The internal reference is not used.
Parameters calculated from the best fit curve from 0x0A to 0xFFF. The best fit curve method is used to deliver coefficients “a” and“b” of the first order equation: y = a + bx. VDAC12_xOUT = EO + (1 + EG) x (VeREF+/4095) x DAC12_xDAT, DAC12IR = 1.
The offset calibration works on the output operation amplifier. Offset calibration is triggered setting bit DAC12CALON.
The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operation is switched off with DAC12AMPx = {0,1}. The DAC12 module should be configured prior to initiating calibration. Port activity during calibration may affect accuracy andis not recommended.
Data is valid after the offset calibration of the output amplifier.
For a full scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3*(1+EG)].
For a full scale output, the reference input voltage can be as high as of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1+EG).
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive divider for each DAC are in parallel
reducing the reference input resistance.
RLoad and CLoad are connected to AVSS (not AVCC/2) in figure 22.
Slew rate applied to output voltage step ≥ 200 mV.
RLoad = 3 kΩ, CLoad = 100 pF.
The cumulative program time must not be exceeded when writing to a 64 byte flash block. This parameter applies to all
programming methods: individual word/byte write and block write modes.
The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297x1/fFGT, max = 5297 x 1/476 kHz). To
achieve the required cumulative mass erase time, the Flash Controller’s mass erase operation can be repeated until this time is
met. A worst case minimum of 19 cycles is required.
These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
To erase the complete code area, the mass erase must be performed once with a dummy address in the range og the lower 64 kB
flash address and once with the dummy address in the upper 64 kB flash addresses.
This parameter defines the minimum supply voltage when the data in program memory RAM remain unchaged. No program
execution should take place during this supply voltage condition.
fTCK may be restricted to meet the timing requirements of the module selected.
TMS, TDI/TCLK, and TCK pullup resistor are implemented in all versions.
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched
to bypass mode.

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Case X
A

D

B

E

32
1

PIN 1 AREA

A2

C

A

0.08

SEATING
PLANE
A1

C
1

S
32 PLS

8
9

32

e1

e

25
THERMAL PAD

16
24

17
b
32 PLS
0.10

M C A B

BOTTOM VIEW

SymbolA
A1
A2b

Dimension
Millimeters
Symbol
Min
Max
0.80
1.00
D/E
0.05
e
0.20 REF
e1
0.18
0.30
S

Millimeters
Min
Max
4.85
5.15
0.50 BSC
3.50 BSC
0.30
0.50

NOTES:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the board for thermal and mechanical performance.
4. See the additional figure in the manufacturer data sheet for details regarding the exposed thermal pad features anddimensions.
3. Falls within JEDEC MO-220.
FIGURE 1. Case outline.

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Case outline X
Terminal
NumberTerminal connection

Terminal
NumberTerminal connection

1

DVSS

32

P2.5/ROSC/CA5

2

XOUT/P2.7/CA7

31

NC

3

XIN/P2.6/CA6

30

DVCC

4

29

TEST/SBWTCK28

P1.7/TA0.2/TDO/TDI

P2.0/ACLK/A0/CA2

27

P1.6/TA0.1/TDI/TCLK

7NC�����/NMI/SBWTDIO
RST

P2.1/TAINCLK/SMCLK/A1/CA3

26

P1.5/TA0.0/TMS

8

P2.2/TA0.0/A2/CA4/CAOUT

25

P1.4/SMCLK/TCK

9

P3.0/UCB0STE/UCA0CLK/A5

24

P1.3/TA0.2

10

P3.1/UCB0SIMO/UCB0SDA

23

P1.2/TA0.1

11

P3.2/UCB0SOMI/UCB0SCL

22

P1.1/TA0.0/TA1.0

12

P3.3/UCB0CLK/UCA0STE

21

P1.0/TACLK/ADC10CLK/CAOUT

13

P3.4/UCA0TXD/UCA0SIMO

20

NC

14

P3.5/UCA0RXD/UCA0SOMI

19

P2.4/TA0.2/A4/VREF+/VeREF+/CA1

15

P3.6/TA1.0/A6

18

P2.3/TA0.1/A3/VREF-/VeREF-/CA0

16

P3.7/TA1.1/A7

17

NC

5
6

FIGURE 2. Terminal connections.

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X1N

DVCC

XOUT

D/AVSS

AVCC

P1.x

P2.x

P3.x

8

8

PORT P1

PORT P2

PORTS P3

8 I/O

8 I/O

8 I/O

INTERRUPTINTERRUPT8ACLKBASIC CLOCKSYSTEM+

MCLK

ADC10

FLASH

RAM

8kB

512B

10-BIT

4kB

512B

8 CHANNELS

2kB

256B

AUTOSCAN

SMCLK

DTC

16MHz

CAPABILITYCAPABILITYPULLUP/PULLUP/DOWNPULLUP/DOWN

PULLDOWNRESISTORSRESISTORSRESISTORSTIMER0_A3

TIMER1_A2

MAB

CPU
INCL 16REGISTERSMDBWATCHDOG
EMULATION
2BP

BROWNOUTPROTECTIONUSCI AO
UART/LIN,

WDT+
COMP_A+
15-BIT

3 CC

2 CC

REGISTERSREGISTERS

IrDA, SPIUSCI B0
SPI,I2CJTAG
INTERFACE

SPY-BI WIRE

RST/NMIFIGURE 3. Functional block diagram.

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16 MHzSYSTEM FREQUENCY-MHz

LEGEND:
SUPPLY VOLTAGE RANGEDURING FLASH MEMORYPROGRAMMING

12 MHz

6 MHz

SUPPLY VOLTAGE RANGEDURING PROGRAMEXECUTION

1.8 V

2.2 V

2.7 V

3.3 V

3.6 V

SUPPLY VOLTAGE - V

NOTE: Minimum processor frequency is defined by system clock. Flash program or erase
operations require a minimum VCC of 2.2 V.
FIGURE 4. Operating area.

VCC
Vhys(B_IT-)
V(B_IT-)
VCC(START)10td(BOR)POR AND BOR vs SUPPLY VOLTAGE

FIGURE 5. POR and BOR vs supply voltage.

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2V

V
CC(drop)

-V

=3 V
CC
TYPICAL CONDITI0NS

1.5

1

0.5

0
0.001

1
t pw -PULSE WIDTH-

VCC

1000
s

tpw

3V

VCC(drop)

1 ns

1 ns

t pw -PULSE WIDTH-s

FIGURE 6. VCC(drop) level with a square voltage drop to generate a POR or BOR signal.

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2
=3 V
CC
TYPICAL CONDITI0NS

V

V CC(drop)

-V

1.5

1

0.5

0
0.001

1

1000

tpw -PULSE WIDTH-

VCC

s

tpw

3V

VCC(drop)

t
f

t
r
t =t
f
r

tpw -PULSE WIDTH-s

FIGURE 7. VCC(drop) level with a triangle voltage drop to generate a POR or BOR signal.

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OSCILLATOR ALLOWANCE
VS
CRYSTAL FREQUENCY
C L,eff=15 pF,

T =25°C
A

100000.00

OSCILLATION ALLOWANCE-OHMS

10000.00

1000.00

LFXT1Sx=2
100.00

LFXT1Sx=0

LFXT1Sx=1

10.00
0.10

1.00

10.00

100.00CRYSTAL FREQUENCY-MHzOSCILLATOR SUPPLY CURRENTVSCRYSTAL FREQUENCY
C

L,eff

=15 pF,

T =25°C
A

1800.0XT OSCILLATOR SUPPLY CURRENT-A

LFXT1Sx=2
1600.01400.01200.01000.0

800.0

600.0

400.0
LFXT1Sx=1
200.0
LFXT1Sx=0
0.0
0.0

4.0

8.0

12.0

16.0

20.0

CRYSTAL FREQUENCY-MHz

FIGURE 8. LFXT1 Oscillator in HF mode (XTS = 1).

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1/f
UCxCLKCKPL=0UCLKCKPL=1
t

LO/HI

t

t
SU,MI

LO/HI

t
HD,MI

SOMI
t

VALID,MOSIMO

FIGURE 9. SPI Master mode, CKPH = 0.

1/f
UCxCLKCKPL=0UCLKCKPL=1
t

LO/HI

t

LO/HI

t

t

SU,MI

HD,MI

SOMI
t

VALID,MOSIMO

FIGURE 10. SPI Master mode, CKPH = 1.

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t
STE,LEADt
STE,LAGSTE
1/f
UCxCLKCKPL=0UCLKCKPL=1
t

t

LO/HI

t
SU,SI

LO/HI

t
HD,SI

SIMO
t

t
STE,ACCt
STE,DISVALID,SO

SOMI

FIGURE 11. SPI slave mode, CKPH = 0.

t
STE,LAGt
STE,LEAD
STE
1/f
UCxCLKCKPL=0UCLKCKPL=1
t
LO/HI

t
LO/HI

t
SU,SI

t
HD,SI

SIMO
t
STE,ACCtt

VALID,SO

STE,DISSOMI

FIGURE 12. SPI slave mode, CKPH = 1.

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HD,STAt

SU,STA

HD,STA

SDA
1/f

t

SCL

SP

SCL
t

HD,DATtt

SU,DAT

SU,STOFIGURE 13. I2C mode timing.

0V
0

V CC

CAF

1

LOW-PASS FILTER

CAON

V+

+

0

V-

-

1

0
1

TO INTERNALMODULESCAOUTSET CAIFG
FLAG
T

2.0

s

FIGURE 14. Comparator_A+ module block diagram.

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V

OVERDRIVE

VV+

CAOUT

400 mVt(RESPONSE)

FIGURE 15. Overdriver definition.

CASHORT
CA0

VIN

+
-

CA1
1
I OUT =10

COMPARATOR_A+CASHORT = 1

A

FIGURE 16. Comparator_A+ short resistance test condition.

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V(Ref)VTVSTEMPERATURE
VCC =2.2 V
650
VCC =3 V

V(REFVT)-REFERENCE VOLTS-mV

600
TYPICAL
550

500

450

400
-45

-25

-5

15

35

55

75

95

115

TA -FREE-AIR TEMPERATURE-°C
V(Ref)VTVSTEMPERATURE
VCC =2.2 V

650

V(REFVT)-REFERENCE VOLTS-mV

VCC=2.2 V
600
TYPICAL
550

500

450

400
-45

-25

-5

15

35

55

75

95

115

TA -FREE-AIR TEMPERATURE-°C

FIGURE 17. Typical comparator_A+.

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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

Vendor item drawing
administrative control
number 1/

Devicemanufacturer
CAGE code

TopsideMarking

Transport media

Vendor part number

V62/13624-01XE

01295

F2132QRHBEP

Tape and real
Qty 250

MSP430F2132QRHBTEP

F2132QRHBEP

Tape and real
Qty 3000

MSP430F2132QRHBREP

1/

The vendor item drawing establishes an administrative control number for identifying
the item on the engineering documentation.

CAGE code

Source of supply

01295

Texas Instruments, Inc.
Semiconductor Group
8505 Forest lane
P.O. Box 660199
Dallas, TX 75243

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