Gated Integrators and Boxcar Averagers
SR250 — Gated integrator with gate width to 2 ns

· Gate width from 2 ns to 15 µs(expandable to 150 µs)· Internal rate generator· Active baseline subtraction· Shot-by-shot output· Gate output for precise gate timing· Average 1 to 10,000 samples· DC to 20 kHz repetition rate
· Low jitter (<20 ps + 0.01 % of delay)· SR250 ... $2990 (U.S. list)

SR250 Gated Integrator
The SR250 Gated Integrator is a versatile, high-speed NIM
module designed to recover fast analog signals fromnoisy backgrounds.

the signal, and makes the instrument a particularly usefulcomponent in a computer data acquisition system.
Triggering

The SR250 consists of a gate generator, a fast gated integrator,and exponential averaging circuitry. The gate generator,
triggered internally or externally, provides an adjustabledelay from a few nanoseconds to 100 ms before it generates
a continuously adjustable gate with a width between 2 ns
and 15 µs. The gate delay can be set from the front panel orautomatically scanned by applying a rear-panel control voltage.
Scanning the gate allows the recovery of entire waveforms.

The SR250 may be triggered internally or externally. Theinternal rate generator is continuously variable from 0.5 Hz to20 kHz in nine ranges. The external trigger pulse may be as
short as 5 ns, allowing the unit to be triggered with fast pulses
from photodiodes and photomultipliers. Single shot and line
triggering can also be selected.

The fast gated integrator integrates the input signal during thegate. The output from the integrator is then normalized by thegate width to provide a voltage proportional to the averageof the input signal during the sampling gate. This signal isfurther amplified and sampled by a low-droop sample-andhold amplifier, and output via a front-panel BNC connector.
The last sample output provides a shot-by-shot analysis of

The sensitivity (Vin/Vout) of the instrument may be set from
1 V/V to 5 mV/V. If additional gain is required, the SR250 canbe used with the SR240A preamplifier. The input is protected
to 100 V and has a 1 MΩ input impedance. An input filter
rejects unwanted signals before the input is sampled by theintegrator. Unwanted DC input offsets are easily nulled witha 10-turn potentiometer.

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Signal Inputs

SR250 Gated Integrator

Gate Timing
The delay of the sample gate from the trigger is set by thedelay multiplier and scale. The delay scale is multiplied by thesetting on the 10-turn multiplier dial, allowing continuously
adjustable delays from a few nanoseconds to 100 ms. The
delay multiplier may also be changed from the rear-panel
control voltage input—a useful feature in applications
requiring a scanning gate. Zero to ten volts at this input
overrides the front-panel 0 to 10× delay multiplier. Insertion
delay from trigger to gate is only 25 ns, and gate-delay jitteris only 20 ps + 0.01 % of the full-scale delay.

signal. The gate output is timed so that it can be overlayedwith the signal output for precise adjustment of gate timing.
The busy output provides a TTL timing pulse which is highwhile the unit is integrating, and goes low when the SR250 isready to accept another trigger. These outputs help simplify
experimental setup and troubleshooting.

The width of the sampling gate may be continuously adjusted
from 2 ns to 15 µs over eight width ranges. A simple
modification of the unit allows gate widths of up to 150 µs.
The front-panel gate output provides a representation of thegate that can be overlayed with the signal on an oscilloscope
to provide a precise display of the gate timing.
Signal Outputs
A moving exponential average of 1 to 10,000 samples canbe selected from the front panel. This traditional averaging
technique is useful for pulling small signals from noisy
backgrounds. In the case of a random white noise background,the signal-to-noise ratio increases by the square root of
the number of samples in the average. This allows a S/N
improvement of up to a factor of 100 using this techniquealone. If no averaging is desired, or if averaging is to be
performed on a computer, the last sample output provides a
voltage proportional to the average value of the input signal
during the last gate period.
Average Reset
The reset button sets the average output to zero. The average
may also be reset by a rear-panel logic input. The average
reset input will accept a TTL signal or a switch closure toground to reset the moving average output.
Polarity Control and Active Baseline Subtraction
The polarity of the last sample and averaged outputs is
controlled by rear-panel toggle switches. Positive outputs
can be selected for negative signals, and vice versa, allowing
easy interfacing with unipolar analog-to-digital conversion
systems. In addition to the traditional averaging modes, theSR250 possesses a unique Active Baseline Subtraction mode
which allows you to actively cancel baseline drift. In theActive Baseline Subtraction mode, the SR250 is triggered attwice the source repetition rate. On alternate triggers (whenthe signal is not present) only the baseline is sampled, and theSR250 inverts the polarity of the last sample output before itis added to the moving average. Thus, any baseline drift notassociated with the source will be subtracted out.

SR250 rear panel

Additional Outputs
The signal input is passed on to the signal output by a lengthof coaxial cable for termination and for gate timing. It isdelayed exactly 3.5 ns from the input, and can be terminatedto optimize either signal gain or response time. The gate
output provides a pulse synchronized with the internal gate

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Ordering Information
SR250

Gated integrator

SR250 Specifications

Droop rate

TriggerInternal trigger
Line trigger
External trigger

Manual trigger
Trigger LED

0.5 Hz to 20 kHz
The gate generator may be triggered
from AC line with adjustable phase.
1 MΩ input impedance. Trigger
threshold adjustable from 0.5 to 2 V.
Input protected to ±100 VDC.
Trigger pulse must be over thresholdfor >5 ns with a rise time <1 µs.
The unit will trigger if triggerthreshold is scanned through 0 VDC.
LED blinks with each trigger.

DelayDelay scale
Delay multiplierInsertion delayAccuracy
JitterExt. delay control

1 ns to 10 ms
0 to 10× using 10-turn dial
25 ns
2 ns or 5 % of full-scale delay,
whichever is larger<20 ps or 0.01 % of full-scale delay,
whichever is larger
Rear-panel 0 to 10 VDC input overrides front-panel delay multiplier.
Used by SR200 / SR245 to scan gate.

When no ext. triggers are present,
droop rate is <1 % per minute(1 to 30 samples), and <0.01 %per minute (100 to 10,000 samples).
Average polarity andRear-panel switch sets polarity ofbaseline subtraction LAST SAMPLE before it is added
to the average. Can also be used toinvert polarity of average output. InTOGGLE position, every othersample is subtracted from theaverage. By triggering at twice theexperiment’s rep rate, baseline will
be sampled on alternate triggers andsubtracted from the average.
Toggle output
Rear-panel TTL signal changes statewith each trigger. Output used with
Active Baseline Subtraction feature
to indicate if next sample will beadded to, or subtracted from, themoving average. Toggle output
can drive 50 Ω loads to +2 VDC.
Reset button
Resets average to zero
Remote reset
Rear-panel input resets average witha TTL low or switch closure.
Signal Input and Output
Signal input

Gate Width
Width scale
Width multiplier
Width accuracy
Minimum width

1, 3, 10, 30, 100, 300 ns, 1, 3 µs
Adjustable from 1× to 5×
2 ns or 20 % of full scale,
whichever is greater
2 ns, FWHM
Signal output

SignalSensitivity (Vin/Vout)
Accuracy
FilterOffset controlOver range LED

1 V/V to 5 mV/V in a 1-2-5 seq.
3 % for gate widths >10 ns,
decreasing to 50 % for a 2 ns gate
DC coupled, or AC coupled above
10 Hz or 10 kHz±0.4 VDC using 10-turn dial
Indicates input is >2 VDC or LASTSAMPLE is greater than 10 VDC

Gate and Busy Outputs
Gate output
Busy output

Last Sample
OutputPolarity switch
Responsivity±10 VDC, 10 mA (20 mA shortcircuit limit), impedance <1 ΩInverts LAST SAMPLE output
95 % (no more than 5 % of theprevious last sample remains)

Average output

Exponential moving average
1, 3, 10, 30, ... to 10,000
LAST is selected for no averaging±10 VDC full scale, 10 mA (20 mA
short circuit limit). Impedance <1 ΩStanford Research Systems

200 mV pulse marks exact positionof gate with respect to signal output.
±1 ns accuracy (50 Ω load)
TTL signal indicates output data isready. High from trigger signal until
unit is ready for next trigger (45 µsmin., longer for long delays or gatewidths). Drives 50 Ω load to 2 VDC.

GeneralPower supplies

AveragingTypeNumber of samples

1 MΩ input impedance, ±2 VDC
usable range, protected to 100 VDC.
Input offset drift <0.5 mV/hr. after
20 min. warm-up. Shot noise at
input <0.5 mV. Coherent pickup<5 mV (easily cancelled with offset
knob in fixed gate applications).
SIGNAL OUTPUT is the input
signal delayed by 3.5 ns. (Used toterminate input signal and to time
gate with respect to signal output.)

Mechanical
Dimensions
Warranty+24 V/135 mA, +12 V/380 mA,–12 V/230 mA, –24 V/150 mA.
14 W. Power from a standard NIM
crate (SR280).
Dual-width NIM enclosure2.7" × 8.174" × 11.5" (WHD)
One year parts and labor on defects
in materials and workmanship