REVISIONSLTR

DESCRIPTIONDATEAPPROVEDA

Add device type 02 and case outline Y. - ro

10-01-07

C. SAFFLE

B

Make changes to the Temperature sensor
reading, coefficient parameter as specified under
Table I. Make correction to note 1 for case Y as
specified under figure 1. Update document
paragraphs to current requirements. - ro

16-07-07

C. SAFFLEC

Update document paragraphs to current
requirements. - ro

22-01-13

J. ESCHMEYER

CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24

Vendor item drawing

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PMIC N/A

DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990

PREPARED BY
RICK OFFICER

https://www.dla.mil/landandmaritime

Original date of drawing
YY-MM-DD
09-05-12

TITLE

CHECKED BYRAJESH PITHADIAAPPROVED BYJOSEPH D. RODENBECK
SIZE

A
REV

CODE IDENT. NO.

MICROCIRCUIT, DIGITAL-LINEAR, 16 CHANNEL,
24 BIT ANALOG TO DIGITAL CONVERTER,
MONOLITHIC SILICONDWG NO.

V62/09626

16236
C

PAGE

AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.

1

OF

22
5962-V107-21

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance16 channel, 24 bit analog to digital converter(ADC) microcircuit, with an operating temperature range of -55°C to +125°C for device type 01 and -40°C to +105°C for device type 02.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/09626-

Drawing
number01

X

E

Device type
(See 1.2.1)

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic

Temperature range

01
02

ADS1258M-EP
ADS1258IP-EP-55°C to +125°C-40°C to +105°C

Circuit function
16 channel, 24 bit analog to digital converter
16 channel, 24 bit analog to digital converter

1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

X

48

See figure 1

Y48

MS-026

Package style
Plastic square leadless chip carrier withthermal pad
Plastic quad flat pack with thermal pad

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture:
Finish designator
A
B
C
D
E
F
Z

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Material
Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy (BGA/CGA)
Other

SIZE
A

CODE IDENT NO.
16236
REV

C

DWG NO.

V62/09626
PAGE2

1.3 Absolute maximum ratings.

1/

Positive analog power supply (AVDD) to negative analog power supply (AVSS) .................... -0.3 V to 5.5 V
AVSS to digital ground (DGND) ........................................................................................... -2.8 V to 0.3 V
Digital power supply (DVDD) to DGND ................................................................................. -0.3 V to 5.5 V
Input current, momentary .................................................................................................... 100 mA
Input current, continuous ..................................................................................................... 10 mA
Analog input voltage ........................................................................................................... AVSS – 0.3 V to AVDD + 0.3 V
Digital input voltage to DGND .............................................................................................. -0.3 V to DVDD + 0.3 V
Maximum junction temperature (TJ) ..................................................................................... +150°C
Storage temperature range ................................................................................................. -60°C to +150°C
Thermal resistance, junction to case (θJC) ........................................................................... 20°C/W
Thermal resistance, junction to ambient (θJA) :High K ............................................................................................................................ 33°C/W 2/
Low K ............................................................................................................................. 75°C/W 3/
1.4 Recommended operating conditions. 4/
AVDD ................................................................................................................................. +2.5 V
AVSS .................................................................................................................................. -2.5 V
DVDD ................................................................................................................................. +3.3 V
Operating temperature range (TA) ....................................................................................... -55°C to +125°C

1/

2/
3/
4/

Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
High K specifies values determined on a JESD 51-7 highly conductive printed circuit board.
Low K specifies values determined on a JESD 51-3 low conductive printed circuit board.
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.

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2. APPLICABLE DOCUMENTSJEDEC Solid State Technology Association
EIA/JEDEC 51-3 –EIA/JEDEC 51-7 –JEDEC PUB 95 –Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Registered and Standard Outlines for Semiconductor Devices(Copies of these documents are available online at https://www.jedec.org.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Block diagram. The block diagram shall be as shown in figure 3.
3.5.4 Timing waveforms. The timing waveforms shall be as shown in figure 4.

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TABLE I. Electrical performance characteristics. 1/
Test

SymbolConditions 2/

Temperature,TA

Devicetype-55°C to +125°C

Limits
Min

Max

01

AVSS
– 100
mV

AVDD
+ 100
mV

-40°C to +105°C

02

AVSS
– 100
mV

AVDD
+ 100
mV

-55°C to +125°C

01

80 typical-40°C to +105°C

02

80 typical-55°C to +125°C

01-110 typical-40°C to +105°C

02-110 typical-55°C to +125°C

01

1.5 typical-40°C to +105°C

02

1.5 typical-55°C to +125°C

01

24 typical-40°C to +105°C

02

24 typical-55°C to +125°C

01

1 typical-40°C to +105°C

02

1 typical-55°C to +125°C

01±1.0 6 VREF
typical-40°C to +105°C

02±1.0 6 VREF
typical-55°C to +125°C

01

AVSS
– 100
mV

AVDD
+ 100
mV

-40°C to +105°C

02

AVSS
– 100
mV

AVDD
+ 100
mV

-55°C to +125°C

01

65 typical-40°C to +105°C

02

65 typical

Unit

Analog multiplexer inputs section
Absolute input voltage

On channel resistance

CrosstalkSensor bias

VIN

AIN0-AIN15, AINCOM with respect
to DGND

RON

CT

SBCS

fIN = 1 kHz

SBCS[1:0] = 01

(current source)
SBCS[1:0] = 11

1.5 µA:24 µA ratio error

RE

V

Ω

dB

µA

%

ADC input section
Full scale input voltage

Absolute input voltage

Differential input
impedance

VFS

VIN

VIN = ADCINP – ADCINNADCINP, ADCINN

ZDIN

V

V

kΩ

See footnotes at end of table.

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5

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/

Temperature,TA

Devicetype

Limits-55°C to +125°C

01

24-40°C to +105°C

02

24-55°C to +125°C

01

1.953

125

-40°C to +105°C

02

1.953

125

-55°C to +125°C

01

1.805

23.739-40°C to +105°C

02

1.805

23.739-55°C to +125°C

01

0.00030.0010% of-40°C to +105°C

02

0.00030.0010

FSR 4/-55°C to +125°C

01

20 typical-40°C to +105°C

02

20 typical-55°C to +125°C

01-40°C to +105°C

02

10-55°C to +125°C

01

0.5 typical-40°C to +105°C

02

0.5 typical-55°C to +125°C

01

0.1

-40°C to +105°C

02

01-55°C to +125°C

01-40°C to +105°C

02-55°C to +125°C

01

0.4 typicalppm /-40°C to +105°C

02

2

°C

-55°C to +125°C

01

See table II-40°C to +105°C

02

See table II

Min

Unit

Max

System performance section
Resolution

RES

Data rate,
fixed channel mode

DRF

Data rate,
auto scan mode

DRA

Integral nonlinearity 3/

INL

Offset error,
chopping off

OE

Offset error,
chopping on

OE

Offset drift,
chopping off

OD

Offset drift,
chopping on

OD

Gain error

GE

Gain drift

Noise

No missing codes

Differential input

Shorted inputs

Shorted inputs

Shorted inputs

Shorted inputs

GD

N

-650

-0.5

Bits

kSPS

kSPS

µV

650

µV

µV/°C

µV/°C

0.5

%

0.5

See footnotes at end of table.

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6

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/

Temperature,TA

Devicetype

Limits-55°C to +125°C

01

90-40°C to +105°C

02

90-55°C to +125°C

01

70-40°C to +105°C

02

70-55°C to +125°C

01

80-40°C to +105°C

02

80-55°C to +125°C

01

0.5

Min

Unit

Max

System performance section - continued.
Common mode
rejection ratio

CMRR

Power supply rejection
ratio, AVDD, AVSSPSRRPower supply rejection
ratio, DVDD

PSRR

fCM = 60 Hz

fPS = 60 Hz

fPS = 60 Hz

dB

dB

dB

Voltage reference input section
Reference input
voltage

Negative reference
input

Positive reference
input

Reference input
impedance

VREF

VREF = VREFP - VREFNV

AVDD- AVSS

VREFN

VREFP

ZRIN

-40°C to +105°C

02

0.5

AVDD
- AVSS-55°C to +125°C

01

AVSS
– 0.1

VREFP
– 0.5

-40°C to +105°C

02

AVSS
– 0.1

VREFP
– 0.5

-55°C to +125°C

01

VREFN
+ 0.5

AVDD
+ 0.1

-40°C to +105°C

02

VREFN
+ 0.5

AVDD
+ 0.1

-55°C to +125°C

01

40 typical-40°C to +105°C

02

40 typical

V

V

kΩ

See footnotes at end of table.

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7

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/

Temperature,TA

Devicetype

LimitsExternal reference
reading error-55°C to +125°C

01

3-40°C to +105°C

023

Analog supply reading
error-55°C to +125°C

01

3-40°C to +105°C

023

Temperature sensor
reading, voltage

+25°C

01

168 typical02

168 typical01

394 typical02

394 typical01

563 typical02

563 typical

Min

Unit

Max

System parameters section

Temperature sensor
reading, coefficient

Only device temperature forced;
test printed circuit board (PCB) in
free air.

+25°C

Device and test PCB temperatures
forced together.

%

%

mV

µV/°C

Digital input / output section
Logic levels

VIH

VIL

VOH

VOL

IOH = 2 mA

IOL = 2 mA

-55°C to +125°C

01

0.7
DVDD

DVDD

-40°C to +105°C

02

0.7
DVDD

DVDD

-55°C to +125°C

01

DGND

0.3
DVDD

-40°C to +105°C

02

DGND

0.3
DVDD

-55°C to +125°C

01

0.8
DVDD

DVDD

-40°C to +105°C

02

0.8
DVDD

DVDD

-55°C to +125°C

01

DGND

0.2
DVDD

-40°C to +105°C

02

DGND

0.2
DVDD

V

V

V

V

See footnotes at end of table.

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8

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/

Temperature,TA

Devicetype

Limits-55°C to +125°C

01

10-40°C to +105°C

02

10-55°C to +125°C

01

0.1

16

-40°C to +105°C

02

0.1

16

-55°C to +125°C

01

40

60

-40°C to +105°C

02

40

60

-55°C to +125°C

01

32.768 typical-40°C to +105°C

02

32.768 typical-55°C to +125°C

01

15.729 typical-40°C to +105°C

02

15.729 typical

Start up time,clock output valid-55°C to +125°C

01

150 typical-40°C to +105°C

02

150 typical

Clock output duty
cycle

-55°C to +125°C

01

40

60

-40°C to +105°C

02

40

60

-55°C to +125°C

01

2.7

5.25

-40°C to +105°C

02

2.7

5.25

-55°C to +125°C

01

-2.6

0

-40°C to +105°C

02

-2.6

0

-55°C to +125°C

01

AVSS
+ 4.75AVSS+ 5.25-40°C to +105°C

02

AVSS
+ 4.75AVSS+ 5.25

Min

Unit

Max

Digital input / output section - continued.
Input leakage

Master clock input

Master clock input

IINL

CLKIO

CLKIO

VIN = DVDD, GND

Frequency

Duty cycle

µA

MHz

%

Crystal oscillator
Crystal frequency

Clock output
frequency

fCRY

fCOUT

kHz

MHz

ms

%

Power supply section
Digital supply voltage

DVDD

Negative analog power
supplyAVSS

Positive analog power
supply

AVDD

V

V

V

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/

Temperature,TA

Devicetype

Limits-55°C to +125°C

01

0.75

-40°C to +105°C

02

0.6

-55°C to +125°C

01

0.04 typical-40°C to +105°C

02

0.04 typical-55°C to +125°C

01

1.4 typical-40°C to +105°C

02

1.4 typical-55°C to +125°C

01

25-40°C to +105°C

02

25-55°C to +125°C

01

12-40°C to +105°C

02

12-55°C to +125°C

01

5.6 typical-40°C to +105°C

02

5.6 typical-55°C to +125°C

01

2.1 typical-40°C to +105°C

02

2.1 typical-55°C to +125°C

01

85-40°C to +105°C

02

85

Min

Unit

Max

Power supply section – continued.
DVDD supply current
External clock
operation

IEC

Internal oscillator
operation, clock
output disabled

IOED

Internal oscillator
operation, clock
output enabledPower down 6/

5/

ICOE

IPD

mA

mA

mA

µA

AVDD, AVSS supply current
ConvertingStandby

Sleep

Power down

IC

ISB

ISL

IPD

mA

mA

mA

µA

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/

Temperature,TA

Devicetype

Limits-55°C to +125°C

01

62-40°C to +105°C

02

62-55°C to +125°C

01

29 typical-40°C to +105°C

02

29 typical-55°C to +125°C

01

11 typical-40°C to +105°C

02

11 typical-55°C to +125°C

01

14 typical-40°C to +105°C

02

14 typical

Min

Unit

Max

Power dissipation section
ConvertingStandby

Sleep

Power down

1/

2/

3/
4/
5/
6/

PC

PSB

PSL

PD

mW

mW

mW

µW

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance overthe specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
Unless otherwise specified, AVDD = +2.5 V, AVSS = -2.5 V, DVDD = +3.3 V, fCLK = 16 MHz (external clock) or
fCLK = 15.729 MHz (internal clock), an OPA227 device buffer between multiplexer differential (MUX) outputs and ADC inputs,
VREF = +4.096 V, and VREFN = -2.5 V.
Best straight line fit method provides information about offset (intercept) and gain (slope) error. It determines in the form ofa straight line, the closet approximation to the analog to digital converter actual transfer function. This approach yields thebest repeatability and true representation of linearity.
Full scale range (FSR) = 2.1 3 VREF.
CLKIO load = 20 pF.
No clock applied to CLKIO.

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Case XFIGURE 1. Case outlines.

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Case X - continued

Dimensions
InchesSymbolMillimeters

Min

Max

Min

Max

A

---

.035

---

0.90

A1

---

.027

---

0.70

A2

.007 reference

0.20 reference

A3

.000

.001

0.00

0.05

b

.007

.011

0.18

0.30

D/E

.271

.279

6.90

7.10

D1 / E1

.261

.269

6.65

6.85

e

.019 BSC

0.50 BSC

e1.216 reference

5.50 reference

s

.009

n

---

0.25

---

48

48

NOTES:
1. Controlling dimensions are millimeter, inch dimensions are given for reference only.
2. This drawing is subject to change without notice.
3. QFN (quad flat pack with no loads) package configuration.
4. The package thermal pad must be soldered to the board for thermal and mechanical performance.

FIGURE 1. Case outlines - Continued.

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Case YFIGURE 1. Case outlines - continued.

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Case Y - continued.

Dimensions
InchesSymbolMillimeters

Min

Max

Min

Max

A

---

.047

---

1.20

A1

.037

.041

0.95

1.05

A2

.009

---

0.25

---

A3

.001

.005

0.05

0.15

b

.006

.010

0.17

0.27

c

.005

---

0.13

---

D

.346

.362

8.80

9.20

D1

.267

.283

6.80

7.20

D2

.216

---

5.50

---

E

.346

.362

8.80

9.20

E1

.267

.283

6.80

7.20

E2

.216

---

5.50

---

e
L1

.019 BSC.017

0.50 BSC
.029

0.45

0.75

NOTES:
1. Controlling dimensions are millimeter, inch dimensions are given for reference only.
2. D1/E1 body dimensions do not include mold flash, protrusion, or gate burrs. Mold flash, protrusions, or gateburrs shall not exceed 0.15 mm (.006 inch) per side.
3. This package is designed to be soldered to a thermal pad on the board. Refer to technical brief, powerpad
thermally enhanced package, manufacturer’s literature number SLMA002 for information regarding recommended
board layout.
4. Falls within JEDEC MS-026.

FIGURE 1. Case outlines – Continued.

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Device types

01 and 02

Case outlines

X and Y

Terminal
numberTerminal
symbolAnalog / Digital
Input / Output

1

AIN3

Analog input

Analog input 3: single ended channel 3, differential channel 1 (-)

2

AIN2

Analog input

Analog input 2: single ended channel 2, differential channel 1 (+)

3

AIN1

Analog input

Analog input 1: single ended channel 1, differential channel 0 (-)

4

AIN0

Analog input

Analog input 0: single ended channel 0, differential channel 0 (+)

5

AVSS

AnalogNegative analog power supply: 0 V for unipolar operation, -2.5 V for
bipolar operation. (internally connected to exposed thermal pad ofcase outline X.)

6

AVDD

AnalogPositive analog power supply: 5 V for unipolar operation, 2.5 V for
bipolar operation.

7

PLLCAP

AnalogPhase locked loop (PLL) bypass capacitor: connect 22 nF capacitor to
AVSS when using crystal oscillator.

8

XTAL1

Analog32.768 kHz crystal oscillator input 1. See crystal oscillator section of
manufacturer’s datasheet.

9

XTAL2

Analog32.768 kHz crystal oscillator input 2. See crystal oscillator section of
manufacturer’s datasheet.

10

PWDN

Digital input

Power down input: hold low for minimum of two fCLK cycles to engage
low power mode.

11

RESET

Digital input

Reset input: hold low for minimum of two fCLK cycles to reset thedevice.

12

CLKSEL

Digital input

13

CLKIO

Digital I/O

System clock input/output (see CLKSEL pin).

14

GPIO0

Digital I/O

General purpose digital input/output 0.

15

GPIO1

Digital I/O

General purpose digital input/output 1.

16

GPIO2

Digital I/O

General purpose digital input/output 2.

17

GPIO3

Digital I/O

General purpose digital input/output 3.

18

GPIO4

Digital I/O

General purpose digital input/output 4.

19

GPIO5

Digital I/O

General purpose digital input/output 5.

20

GPIO6

Digital I/O

General purpose digital input/output 6.

21

GPIO7

Digital I/O

General purpose digital input/output 7.

Description

Clock select input: Low = activates crystal oscillator, fCLK output on
CLKIO. High = disables crystal oscillator, apply fCLK to CLKIO.

FIGURE 2. Terminal connections.

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

C

DWG NO.

V62/09626
PAGE

16

Device types

01 and 02

Case outlines

X and Y

Terminal
numberTerminal
symbolAnalog / Digital
Input / Output

Description

22

SCLK

Digital input

Serial peripheral interface (SPI) clock input: data clocked in on risingedge, clocked out on falling edge.

23

DIN

Digital input

SPI interface data input: data is input to the device .

24

DOUT

Digital output

SPI interface data output: data is output from the device.

25

DRDY

Digital output

Data ready output: active low.

26

START

Digital input

Start conversion input: active high.

27

CS

Digital input

SPI interface chip select input: active low.

28

DVDD

DigitalDigital power supply: 2.7 V to 5.25 V

29

DGND

DigitalDigital ground.

30

VREFN

Analog input

Reference input negative.

31

VREFP

Analog input

Reference input positive.

32

AINCOM

Analog input

Analog input common: Common input pin to all single ended inputs.

33

AIN15

Analog input

Analog input 15: single ended channel 15, differential channel 7 (-).

34

AIN14

Analog input

Analog input 14: single ended channel 14, differential channel 7 (+).

35

AIN13

Analog input

Analog input 13: single ended channel 13, differential channel 6 (-).

36

AIN12

Analog input

Analog input 12: single ended channel 12, differential channel 6 (+).

37

AIN11

Analog input

Analog input 11: single ended channel 11, differential channel 5 (-).

38

AIN10

Analog input

Analog input 10: single ended channel 10, differential channel 5 (+).

39

AIN9

Analog input

Analog input 9: single ended channel 9, differential channel 4 (-).

40

AIN8

Analog input

Analog input 8: single ended channel 8, differential channel 4 (+).

41

ADCINN

Analog input

ADC differential input (-)

42

ADCINP

Analog input

ADC differential input (+)

43

MUXOUTN

Analog output

Multiplexer differential output (-)

44

MUXOUTP

Analog output

Multiplexer differential output(+)

45

AIN7

Analog input

Analog input 7: single ended channel 7, differential channel 3 (-).

46

AIN6

Analog input

Analog input 6: single ended channel 6, differential channel 3 (+).

47

AIN5

Analog input

Analog input 5: single ended channel 5, differential channel 2 (-).

48

AIN4

Analog input

Analog input 4: single ended channel 4, differential channel 2 (+).

FIGURE 2. Terminal connections – continued.

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

C

DWG NO.

V62/09626
PAGE

17

FIGURE 3. Block diagram.

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

C

DWG NO.

V62/09626
PAGE

18

Serial interface timing characteristics. 1/
SymbolDescription

Min

Max

Units

tSCLK

SCLK period

2

tSPW

SCLK high or low pulse width (exceeding maximum
resets SPI interface)

0.8

tCSSC

CS low to first SCLK: setup time 4/

2.5

τCLK

tDIST

Valid DIN to SCLK rising edge: setup time

10

ns

tDIHD

Valid DIN to SCLK rising edge: hold time

5

ns

tDOPD

SCLK falling edge to valid new DOUT:
propagation delaytDOHDSCLK falling edge to old DOUT invalid: hold timetCSDO

CS high to DOUT invalid (tri-state)tCSPW

CS pulse width high

τCLK 2/4096 3/

5/

20
0

τCLK

ns
ns

5
2

τCLK
τCLK

1/

Unless otherwise specified, TA = -40°C to +105°C ensured by characterization only and DVDD = 2.7 V to 5.25 V

2/

τCLK = master clock period = 1/fCLK.

3/

Programmable to 256 τCLK.

4/
5/

CS can be tied low.
DOUT load = 20 pF || 100 kΩ to DGND.

FIGURE 4. Timing waveforms.

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

C

DWG NO.

V62/09626
PAGE

19

DRDY update timing characteristics
SymbolDescription

TypicalUnitst DRDYDRDY high pulse width without data read

1

τCLK

tDDO

Valid DOUT to DRDY falling edge ( CS = 0 )

0.5

τCLK

FIGURE 4. Timing waveforms – continued.

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

C

DWG NO.

V62/09626
PAGE

20

TABLE II. Noise performance. 1/
DRATE[1:0]Data rate autoscan mode(SPS)

Data rate fixedchannel mode
(SPS)

Input referred
noise(µVRMS)

Noise freeresolution(Bits)

Effective
number of bits
(ENOB)

1123739

125000

12

16.8

19.5

10

15123

31250

7.9

17.4

20.1

01

6168

7813

4.5

18.2

20.9

00

1835

1953

2.8

18.9

21.6

1/ VREF = 4.096 V, fCLK = 16 MHZ, chop = 0, delay = 0, inputs shorted, and 2048 sample size.

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

C

DWG NO.

V62/09626
PAGE

21

6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/Programs/Smcr/.

Vendor item drawing
administrative control
number 1/ 2/

Devicemanufacturer
CAGE code

V62/09626-01XE

01295

V62/09626-01YE

01295

V62/09626-02YE

01295

Package 3/

Top sidemarking

Vendor part number

48 / RTC

Tape andreel of 250

1258MEPADS1258MRTCTEP

48 / PHP

Tray of250

ADS1258MEP

48 / PHP

Tape andreel of 250

ADS1258IEPADS1258MPHPTEPADS1258IPHPREP

1/ The vendor item drawing establishes an administrative control number for identifying the item on theengineering documentation.
2/ For the most current package and ordering information, see the package option addendum at theend of the manufacturer’s data sheet.
3/ Package drawings, standard packaging quantities, thermal data, symbolization, and printed
circuit board (PCB) design guidelines are available from the manufacturer.
CAGE code
01295

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO

Source of supply
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZE
A

CODE IDENT NO.
16236
REV

C

DWG NO.

V62/09626
PAGE

22