REVISIONSLTR

DESCRIPTIONDATEAPPROVEDA

Make correction to Vendor part number from
OPA2211-EP to OPA2211MDRGTEP.
Add JEDEC references to paragraphs 1.3 and 2.
Make temperature correction to TA = +25C for
Table I, Output section, Output voltage test withcondition of AVOL  110 dB. Add I/O andDescription columns to Figure 2 Terminal
connections. Update document paragraph tocurrent requirements. - ro

21-04-01

J. ESCHMEYER

Prepared in accordance with ASME Y14.24

Vendor item drawing

REVPAGEREVPAGEREV STATUS
OF PAGES

REVA

A

A

A

A

A

A

A

AA

A

A

PAGE

123456789101112

PMIC N/A

PREPARED BY
RICK OFFICER

Original date of drawing
YY-MM-DD

CHECKED BYRAJESH PITHADIA

15-12-04

APPROVED BY
CHARLES F. SAFFLESIZE

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
https://www.dla.mil/LandandMaritime
TITLE

CODE IDENT. NO.

A
REV

MICROCIRCUIT, LINEAR, PRECISION, LOW
POWER OPERATIONAL AMPLIFIER,MONOLITHIC SILICONDWG NO.

V62/15606

16236
A

PAGE1OF12DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
AMSC N/A5962-V007-21

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance precision, low power operational amplifier
microcircuit, with an operating temperature range of -55C to +125C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/15606-Drawing
number01XEDevice type(See 1.2.1)

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic01

OPA2211-EP

Circuit function
Dual precision low power operational amplifier

1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

X

8MO-229

Package style
Plastic quad leadless small outline

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
ABCDEFZDLA LAND AND MARITIMECOLUMBUS, OHIOMaterial
Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy (BGA/CGA)
Other

SIZE
A

CODE IDENT NO.
16236
REVA

DWG NO.

V62/15606
PAGE2

1.3 Absolute maximum ratings.

1/

Supply voltage ( VS = +VS - -VS ) .............................................................................. 40 V maximum
Input voltage .............................................................................................................. -VS – 0.5 V to +VS + 0.5 V
Input current (any pin except power supply pins) ....................................................... -10 mA to 10 mA
Output short circuit ..................................................................................................... Continuous 2/
Junction temperature range (TJ) ................................................................................ +150CStorage temperature range (TSTG) ............................................................................ -65C to +150C
Electrostatic discharge (VESD):
Human body model (HBM), per JEDEC JS-001 ..................................................... 3,000 V 3/
Charged device model (CDM), per JEDEC specification JESD22-C101 ............... 1,000 V 4/
1.4 Recommended operating conditions. 5/
Supply voltage (VS) .................................................................................................... 4.5 V (2.25 V ) to 36 V ( 18 V )Operating temperature range (TA) ............................................................................. -55C to +125C
1.5 Thermal characteristics. 6/

Thermal metric

1/

2/
3/
4/
5/
6/

SymbolCase X

Unit

Thermal resistance, junction-to-ambient

JA

47.3

C/W

Thermal resistance, junction-to-case (top)JC(TOP)

51.8

C/W

Thermal resistance, junction-to-board

JB

21.8

C/W

Characterization parameter, junction-to-top

JT0.7

C/W

Characterization parameter, junction-to-board

JB

21.9

C/W

Thermal resistance, junction-to-case (bottom)

JC(BOTTOM)

4.2

C/W

Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
Short circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
For more information about traditional and new thermal metrics, see the integrated package thermal metrics application
report, SPRA953.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACODE IDENT NO.
16236
REVA

DWG NO.

V62/15606PAGE32. APPLICABLE DOCUMENTSAMERICAN SOCIETY OF MECHANICAL ENGINEERS (ASME)
ASME Y14.5 M–Dimensioning and Tolerancing. (DoD adopted)(Copies of these documents are available from https://www.asme.org.)JEDEC Solid State Technology Association
JEDEC JS-001
JESD22-C101––

JEDEC PUB 95
JEDEC JEP 155
JEDEC JEP 157–––

Human Body Model Testing of Integrated Circuits
Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-WithstandThresholds of Microelectronics Components
Registered and Standard Outlines for Semiconductor Devices
Recommended ESD Target Levels for HBM/MM Qualification
Recommended ESD-CDM Target Levels(Copies of these documents are available online at https://www.jedec.org.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REVA

DWG NO.

V62/15606
PAGE4

TABLE I. Electrical performance characteristics. 1/
Test

SymbolConditions 2/

Temperature,TJ

DevicetypeLimits
MinUnitMax

Offset voltage
Input offset voltage

VOS01+25C

VS = 15 V

175

V

50 typical350-55C to +125C
Input offset voltage
drift

VOS/
T

Input offset voltage
versus power supply

PSRR

VS = 2.25 V to 18 V-55C to +125C01

0.35 typicalV /C+25C011

V/V

0.1 typical
3-55C to +125C
Input bias current
Input bias current

IB01-55C to +125C

VCM = 0 V50 typicalnA

350
Offset current

IOS

01

-55C to +125C

VCM = 0 V

20 typicalnA

200Noise
Input voltage noiseenf = 0.1 Hz to 10 Hz+25C01

80 typicalnVPP

Input voltage noisedensityenf = 10 Hz+25C01

2 typical

nV /Input current noise
densityIn

f = 100 Hz

1.4 typicalf = 1 kHz

1.1 typical+25C

f = 10 Hz

01

f = 1 kHz

3.2 typical

Hz

nV /
Hz

1.7 typicalSee footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REVA

DWG NO.

V62/15606
PAGE5TABLE I. Electrical performance characteristics – Continued. 1/Test

SymbolConditions 2/Temperature,
TJDevice
typeLimits

UnitMinMax-VS+ 1.8+VS– 1.4-VS+2+VS– 1.4

Input voltage range
Common mode
voltage range

VCM+25C

VS  5 V

01

VS  5 V
Common mode
rejection ratio

CMRR-55C to +125C

VS  5 V,

01

V

120 typical-VS + 2 V  VCM +VS – 2 V

114

VS  5 V,

120 typical-VS + 2 V  VCM +VS – 2 V

106dB

Input impedanceDifferential

3/+25C01

20 k || 8 typical

||pF

Common mode

3/+25C

01

109 || 2 typical

||pF-VS + 0.6 V  VO  +VS – 0.6 V,+25C01

114 typicaldB

Open loop gain
Open loop voltage gain

AOL

110

RL = 600 -55C to +125C-VS + 0.2 V  VO  +VS – 0.2V,

130 typical

RL = 10 k

114-VS + 0.6 V  VO  +VS – 0.6 V,

100

IO  15 mA
See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REVA

DWG NO.

V62/15606
PAGE6TABLE I. Electrical performance characteristics – Continued. 1/Test

SymbolConditions 2/Temperature,TJ

DevicetypeLimits
MinUnitMax

Frequency response
Gain bandwidthproduct

GBW

Slew rate

SRSettling time, 0.01%

tS+25CG = 100

01

80 typical

G=1

MHz

45 typical+25C01

27 typicalV/s+25C

01

400 typicalns+25C

01

700 typicalns

G = -10+25C01

500 typicalns

G = +1, f = 1 kHz, VO = 3 VRMS,+25C01

0.000015 typical%-136 typicaldB

VS = 15 V, G = -1, 10 V step,
CL = 100 pF

Settling time,0.0015% (16 bit)tS

CL = 100 pF

Overload recovery time
Total harmonic
distortion + noise

VS = 15 V, G = -1, 10 V step,

THD+N

RL = 600 Output
Voltage output

VOUT

AVOL  110 dB, RL = 600 +25C

AVOL  114 dB, RL = 10 k

-55C to +125C01

AVOL  100 dB, IO  15 mA
Short circuit current

ISC

Open loop output
impedance

ZO

f = 1 MHz-VS +0.6+VS –0.6-VS +0.2+VS –0.2-VS +0.6+VS –0.6

V+25C01+30/-45 typicalmA+25C01

5 typical

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REVA

DWG NO.

V62/15606
PAGE

7TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/

Temperature,TJ

DevicetypeLimits

Unit

Min

Max

2.25

18

Power supply
Specified voltage

VS

Quiescent current(per channel)

IQ

IOUT = 0 A

+25C

01

+25C

01

3.6 typicalVmA

4.5-55C to +125C

6Temperature range
Operating range

01

TJ-55

C+125

1/

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance overthe specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.

2/

Unless otherwise specified, RL = 10 k connected to mid supply and VCM = VOUT = mid supply.

3/

The || symbolizes that the input impedance is being represented as the resistance value is in parallel with the capacitance.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REVA

DWG NO.

V62/15606
PAGE

8

Case XFIGURE 1. Case outline.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REVA

DWG NO.

V62/15606
PAGE

9

Case X – continued.

Dimensions
SymbolInchesMillimeters

Min

Max

Min

Max

A.027

.031

0.70

0.80

A1.000

.002

0.00

0.05

A2.007 NOM

b.008

e0.20 NOM
.012

0.20.020 BSC

0.30
0.50 BSC

D.114.122

2.90

3.10

E.114.122

2.903.10

S.016

.024

0.40

0.60

NOTES:
1.

Controlling dimensions are millimeter, inch dimensions are given for reference only.

2.

Dimensioning and tolerancing per ASME Y14.5M-1994.

3.

The package thermal pad must be soldered to the board for thermal and mechanical performance.

4.

Falls within reference to JEDEC MO-229.

FIGURE 1. Case outline - Continued.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REVA

DWG NO.

V62/15606
PAGE

10Device type01

Case outlineX

Terminal number

Terminal
symbolI/O1OUTPUT A

O

Output terminal for channel A.

2-INPUT A

I

Inverting input for channel A.

3+INPUT A

I

Noninverting input for channel A.

4-VS---

Negative supply voltage.

5+INPUT B

I

Noninverting input for channel B.

6-INPUT B

I

Inverting input for channel B.

7

OUTPUT B

O

Output terminal channel B.

8+VS---

Positive supply voltage.

Description

FIGURE 2. Terminal connections.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACODE IDENT NO.
16236
REVA

DWG NO.

V62/15606
PAGE11

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements asindicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guaranteeof present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

Vendor item drawing
administrative control
number 1/Device
manufacturer
CAGE code

Top sidemarking

Vendor part number

V62/15606-01XE

01295

OCQM

OPA2211MDRGTEP

1/ The vendor item drawing establishes an administrative control number for identifying
the item on the engineering documentation.

CAGE code

Source of supply

01295

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACODE IDENT NO.
16236
REVA

DWG NO.

V62/15606
PAGE12