REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVED

C. SAFFLE
J. ESCHMEYERA

Add conditions to the Power supply quiescent current test underTable I. Update document paragraphs to current requirements. - ro

17-04-25

B

Make correction to note 4 as specified under Figure 1. Add quantity
information to paragraph 6.3. Update document paragraphs to current
requirements. - ro

22-05-11

CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24Vendor Item Drawing

Revision Status of Sheets
REVSHEETREVBBB

B

BB

B

B

BB

B

B

SHEET123456789101112

PMIC N/A
Original date ofdrawing
YY-MM-DD

09-01-27

PREPARED BY
RICK OFFICERTITLECHECKED BYRAJESH PITHADIA

A
REV

https://www.dla.mil/landandmaritime

MICROCIRCUIT, LINEAR, DIFFERENTIALAMPLIFIER, MONOLITHIC SILICONAPPROVED BYROBERT M. HEBERSIZEAMSC N/A

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

CAGE CODEDWG NO.

B

PAGE16236

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

V62/09613
1 OF 125962-V061-22

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance differential amplifier microcircuit, with anoperating temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/09613-Drawing
number01XEDevice type(See 1.2.1)

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic

Circuit function

01

INA159-EP

Differential amplifier

1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

Package styleX8

M0-187-AA

Plastic surface mount1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

MaterialAB
CDEFZ

DLA LAND AND MARITIMECOLUMBUS, OHIO

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy (BGA/CGA)
Other

SIZEA

CAGE CODE
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PAGE 2

1.3 Absolute maximum ratings.

1/

Supply voltage (VCC) ................................................................................................. +5.5 V
Signal input terminals (-IN and +IN), voltage .............................................................. ±30 V
Reference (REF 1 and REF 2) and series pins:
Current ................................................................................................................... ±10 mA
Voltage ................................................................................................................... -VCC – 0.5 to +VCC + 0.5 V
Output short circuit (IOS) ............................................................................................ Continuous
Storage temperature range (TSTG) ............................................................................ -65°C to +150°C
Junction temperature range (TJ) ................................................................................ +150°C
Power dissipation (PD) ............................................................................................... 833.33 mW
Thermal resistance, junction to ambient (θJA) ............................................................ 150°C/W
Thermal resistance, junction to case (θJC) ................................................................. 78.495°C/W
Electrostatic discharge (ESD) rating:
Human body model (HBM) ..................................................................................... 4000 V
Charged device model (CDM) ................................................................................ 1000 V
1.4 Recommended operating conditions. 2/
Operating free-air temperature range (TA) ................................................................. -55°C to +125°C

_____
1/

Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.

2/Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.

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2. APPLICABLE DOCUMENTSJEDEC Solid State Technology Association
JEDEC PUB 95–Registered and Standard Outlines for Semiconductor Devices(Copies of these documents are available online at https://www.jedec.org.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Test circuit for reference divider accuracy. The test circuit for reference divider accuracy shall be as shown in figure 3.

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PAGE 4TABLE I. Electrical performance characteristics. 1/
Test

SymbolConditions 2/

Temperature,TADevice
typeLimits
Min

Initial offset voltage 3/

VOS

VS = ±2.5 V, reference and input pin
grounded

Power supply rejection

PSRR

+25°C

01

ratio

+25°C

+25°C

accuracy

µV

±1450
01

±100

-55°C to +125°C

Reference divider 4/

Max
±500

-55°C to +125°C

VS = ±0.9 V to ±2.75 V

UnitµV/V±20001±0.024-55°C to +125°C%±0.050

Differential input 5/impedance

ZDIN+25°C

01

240 typicalkΩCommon mode 5/
input impedance

ZCM+25°C

01

60 typicalkΩCommon mode voltage

+VCM

+25°C

01

17.5 typical

Vrange-VCM

Common mode

CMRR

-12.5 typical
VCM = -10 V to +10 V, RS = 0 Ω

rejection ratio
Output voltage

+25°C

01

f = 0.1 Hz to 10 Hz

noise-55°C to +125°C

dB

74-55°C to +125°C
6/8001

f = 10 kHz

10 typicalµVPP

30 typical

nV /

Hz
Initial gainGi

VREF2 = 4.096 V,+25°C

01+25°C

01

0.2 typical

V/V

RL connected to GND,+VIN – (-VIN) = -10 V to +10 V,
VCM = 0 V
Gain error

Ge

VREF2 = 4.096 V,±0.024%

RL connected to GND,+VIN – (-VIN) = -10 V to +10 V,-55°C to +125°C±0.035

VCM = 0 V
Nonlinearity gainGn

VREF2 = 4.096 V, VCM = 0 V,

+25°C

01

±0.0002 typical

RL connected to GND,
+VIN – (-VIN) = -10 V to +10 V
See footnotes at end of table.

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PAGE 5% ofFS

TABLE I. Electrical performance characteristics – Continued. 1/TestSymbol

Conditions 2/Temperature,
TADevice
typeLimits
Min

Positive output voltage

+VOUT

+25°C

VREF2 = 4.096 V,
RL connected to GND

Negative output
voltage-VOUT

RL connected to GND
Current limit,
continuous tocommon

01+V– 0.1

V-V+ 0.048

V-V+ 0.070-55°C to +125°C+25°C

Max+V- 0.2-55°C to +125°C+25°C

VREF2 = 4.096 V,

01

Unit01±60 typical

Capacitive load

CLSee figure 4Open loop outputimpedanceRO

f = 1 MHz, IO = 0+25°C

01

110 typicalΩSmall signal bandwidth

SSBW-3 dB+25°C

01

1.5 typical

MHzSlew rate

SR+25°C01

15 typicalV/µs

Settling time, 0.01 %tS

4 V output step, CL = 100 pF

+25°C

01

1 typicalµs

50% overdrive

+25°C

01

250 typicalns-55°C to +125°C

01

+5V

-55°C to +125°C

01

+5.5V

+25°C

01

1.5mA

Overload recovery timePower supply specified
voltage range

01mAVSPower supply operating
voltage range
Power supplyquiescent current
1/IQIO = 0 mA, VS = ±2.5 V, reference
and input pins grounded-55°C to +125°CpF+1.8

2.02/Testing and other quality control techniques are used to the extent deemed necessary to assure product performance overthe specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
Unless otherwise specified, at TA = +25°C, RL = 10 kΩ connected to VS/2, REF 1 pin connected to ground, and3/
4/
5/
6/

REF 2 pin connected to VREF = 5 V.
Includes effects of amplifier input bias and offset currents.
Reference divider accuracy specifies the match between the reference divider resistor using figure 3.
Internal resistors are ratio matched but have 20% absolute value.
Includes effect of amplifier input current noise and terminal noise contribution of resistor network.

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PAGE 6Case X

FIGURE 1. Case outline.

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Case X - continued

SymbolDimensions
InchesMilli metersMinMaxMinMax

A---0.043

---

1.10

A1

0.001

0.006

0.05

0.15

b0.010

0.014

0.25

0.38

c0.005

0.009

0.13

0.23

D

0.114

0.122

2.90

3.10

E

0.114

0.122

2.90

3.10

E1

0.187

0.199

4.75

5.05eL0.026 BSC
0.015

0.65 BSC
0.027

0.40

0.70

NOTES:
1. Controlling dimensions are millimeter, inch dimensions are given for reference only.
2. Reference dimension D, body length does not include mold flash, protrusion, or gate burrs.
Mold flash, protrusion, or gate burrs shall not exceed 0.15 mm (0.006 inch) per end.
3. Reference dimension E, body width does not include interlead flash. Interlead flash shall not exceed
0.50 mm (0.019 inch) per side.
4. Falls with JEDEC MO-187-AA, except interlead flash.

FIGURE 1. Case outline - Continued.

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PAGE 8Device type01Case outline

XTerminal number

Terminalsymbol

1

REF 1

2-INPUT

3+INPUT

4-VCC

5SENSE

6OUTPUT

7+VCC

8REF 2

FIGURE 2. Terminal connections.

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PAGE 9NOTE:The test is performed by measuring the output with the reference applied to alternate reference resistors,
and calculating a result such that the amplifier offset is cancelled in the final measurement.

FIGURE 3. Test circuit for reference divider accuracy.

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PAGE 10Figure 4. Small signal overshoot versus load capacitance.

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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

Vendor item drawing
administrative control
number 1/ 2/

Devicemanufacturer
CAGE code

Mode oftransportationand quantity
3/

PackagedesignatorTop sidemarking

Vendor part number

V62/09613-01XE01295

Tape and reel,250 units

DGKOAA

INA159AMDGKTEP

1/ The vendor item drawing establishes an administrative control number for identifying the item on theengineering documentation.
2/ For the most current package and ordering information, see the package option addendum at the end of themanufacturer’s data sheet, or contact the manufacturer.
3/ Package drawings, standard packaging quantities, thermal data, symbolization, and printed circuit board (PCB)
design guidelines are available from the manufacturer.
CAGE code

Source of supply

01295

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

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