.-~

--

.;.

·.~t

r·

b

...

...
i...

-~.; '"··'l!i:~~i:!!!
~

~~
~-

C"f

m
·::J·

!;.

lw.

"'·.~
· .. ·.·
..

...

c(&.

~­

v

r\···
.. ·

·;

.,

r:&;:

Fairchild
Semiconductor
Integrated
Circuit
Data
Catalog

1970

The Fairchild Semiconductor Integrated
Circuit Data Catalog contains productinformation on Fairchild's complete lineof. digital and linear integrated circuits.
Comprehensive data sheet specifications are provided .for each device, including .Medium Scale Integration (MSI)
devices. Also included for your convenience: a complete listing of Application
Notes and Technical Papers (all avail·able. upon request), a preview of new .
products and reply cards for further
information.

Library of Congress Catalog Card 75-87311©1969 Fairchild Semiconductor
BR-BR-0015-29 100M
Printed In U.S.A.
Fairchild Semiconductor assumes no responsibility for the use of any circuits described herein
and makes no representations or warranties, express, implied, or statutory,
that such circuits are free from patent infringement.

ii

TABLE OF CONTENTS

How to Use the Data Catalog

Page
No.
v

INTEGRATED CIRCUITS
Integrated Circuit Numerical Index
Integrated Circuit Numerical Index by Family

1-1
2-1

GENERAL INFORMATION

A.

B.

C.

D.

E.

Compatible Current Sinking Logic
Numerical Index
Cross Reference (Including Special Circuits)
Data Sheets
Coming Soon-Products to be Announced
Special Integrated Circuits
Numerical Index
Cross Reference (Refer to CCSL Cross Reference)
Data Sheets
Coming Soon-Products to be Announced

3-i
3-ii
3-1
3-183
4-i
3-ii

4-1
4-102

Hybrid Integrated Circuits
Numerical Index
Cross Reference
Data Sheets
Coming Soon-Products to be Announced

5-i
5-ii
5-1
5-56

Linear Integrated Circuits
Numerical Index
Cross Reference
Data Sheets
Coming Soon-Products to be Announced

6-i
6-ii
6-1
6-141

MOS Integrated Circuits
Numerical Index
Cross Reference
Data Sheets
Coming Soon-Products to be Announced

7-63

APPLICATION NOTE AND TECHNICAL PAPER INDEX

8-1

ORDERING INFORMATION
A. Microcircuits
B. Hybrids
C. Terms and Conditions of Sales
D. Fairchild Sales Offices

9-1
9-2

NOTE:

7-i
7-ii
7-1

9-3
9-4

Six business reply cards may be found at the back of the book.

iii

HOW TO USE THE DATA CATALOG

The Fairchild Integrated Circuit Data Catalog is divided into five sections byproduct line: Compatible Current Sinking Logic, Special Circuits, Hybrid Circuits, Linear Circuits, and MOS Circuits.
A comprehensive listing of integrated circuits is provided on page 1-1. This
index lists the device type, function, family, and page number of all Fairchildcircuits manufactured at the time of publication. In addition, a numerical index by family is provided on page 2-1. Thus, Fairchild's available products ina given category can be checked at a glance, or a particular device can belocated even if its generic classification is not known.
In the first two sections, CCSL and Special Circuits, the data sheets appear
in numerical order by logic family, i.e., TTµ.L, DT µ.L, Cµ.L, RTµ.L, and CT µ.L. All
products in each family are listed in the index at the beginning of each major
section.
In the Hybrid, Linear, and MOS sections the data sheets appear in numericalorder and are indexed at the beginning of each section.
For each family of circuits there is a cross reference table listing the packages available for each product category. For instance, the MOS 3750 10 Bit
D/ A Converter is available in Flat Pak and Dual In-Line packages.
For each category of integrated circuits there is a "Coming Soon" section
with new product listings and descriptions. These are products for which
there were no firm specifications at publishing date for the catalog. Complete
specifications on these new products will be provided in the next edition of
the data catalog.
Further information may be obtained by contacting your local Fairchild distributor or by sending in a reply card furnished in this catalog.

v

-

I

I
I
I

ii
I

-

-- --=- -=--Integrated
CircuitsINTEGRATED CIRCUITS '.NUMERICAL INDEX

TypeµA702AµA702BµA702CµA703µA703CµA703EµA709µA709AµA709BµA709CµA710µA710BµA710CµA711µA711CµA716µA716CµA717EµA719µA719CµA722µA722BµA723µA723CµA726µA726CµA727µA727BµA730µA730CµA733µA733CµA737EµA739CµA741µA741CµA751C
3100
3101
3102
3250
3300
3303
3304
3305/6
3320
3501
3530
3700
3701
3705
3750
3751

Function

FamilyHigh Gain, Wideband DC Amplifier
Linear· High Gain, Wideband DC Amplifier , Linear
High Gain, Wideband DC Amplifier
LinearLinear
RF-IF Amplifier
Linear
RF-IF Amplifhir
Linear
RF-IF Amplifier
High Performance Operational Amp. Linear
High Performance Operational Amp. Linear
High Performance Operational Amp. Un ear
High Performance Operational Amp. Linear
High Speed Differential Amplifier
Linear ...
High Speed Differential Comparator Linear
High Speed Differential Comparator Linear
Dual Comparator
LinearDual Comparator
Linear . .
Fixed Gain, Low Distortion Amplifier Linear
Fixed Gain, Low Distortion Amplifier Linear
Multi-Purpose Amplifier
LinearHigh Gain RF Amplifier/FM Detector Linear
High Gain RF Amplifier/FM Detector Linear
10-Bit Current Source
Linear10-Bit Current Sourceli.nearPrecision Voltage Regulator
Linear •Precision Voltage Regulator
LinearTemperature Controlled Differential Linear
Pair
Temperature Controlled Differential Linear
Pair
Temperature Controlled Differential linear
AmplifierTemperature Controlled Differential Linear
AmplifierDifferential Amplifier
LinearDifferential Amplifier
Lin.earDifferential Video Amplifier
LinearDifferential Video Amplifier
LinearColor TV Chroma Demodulator
LinearDual Low-Noise Operational Amplifier Linear
Frequency Compensated Operational Linear
AmplifierHigh Performance Operational Amp. Linear
Differential Video Amplifier
Linear5-lnput Gate
MOS
Dual JK Flip-Flop
MOS
3-lnput Gate
MOS
CRT Numeric Character Generator
MOS
25-Bit MOS Static Shift Register
MOS
Dual 25-Bit Dynamic Shift Register MOS. Dual 16-Bit Static Shift Register
MOS
64-Bit 10 Static Shift Register
MOS
64-Bit - 40 Shift Register
MOS
1024-Bit Static Read Only Memory
MOS
64-Bit Static Random Access Memory MOS
Monolithic 4 Channel Switch
MOS
Monolithic 6 Channel Switch
MOS
8 Channel Multiplex Switch
MOS
10-Bit MOS/LSI D/A Converter
MOS
12-Bit A/D Converter
MOS

Page
NumberType

Function

Family·Page
Number

7-53
8-Bit MOS/LSI Parallel Accumulator MOS
7-59
10-Bit Serial/Parallel - Parallel/Serial MOS
Converter.Micromatrixr" 3-169
CCSL Micromatrix™ Quarter Cell
4501
Array
CCSL Micromatrix™ Dual 4-Bit
Micromatrix™ 3-1, 3-11, 3-171
4510
Array
Comparator. .TTL Micromatrix™ Array Internal
Micromatrix™ 3-175
4601
Array
Quarter Cell
Dual Two-Variable Function Generator Micromatrix™ 3-179
4610
Array
Hµl.
9000
JK Flip-Flop
3-1, 3-11,
3-71, 3-89
JK Flip-Flop
HµL
9001
3-1, 3-11,
3-71, 3-89
HµL
9002
Quad 2-lnput Gate
3-1, 3-11,
3-71, 3-89
Triple 3-lnput Gate
9003
TTµL
3-1, 3-11,
3-71, 3-899004
Dual 4-lnput Gate
HµL
3'1, 3-11,
3-71, 3-89
Dual 2-2 Input AND-OR-INVERT Gate HµL
9005
3-1, 3-11,
One Half Extender
3-71, 3-89
. Dual 4-lnput OR Extender
TTµL
3-1, 3-11,
9006
3-71, 3-899007
Single 8-lnput Gate
TTµL
3-1, 3-11,
3-71, 3-899008
Single Extender 2-2-2-3 AND-ORTTµL
3-1, 3-11,
INVERT Gate
3-71, 3-899009
Dual 4-lnput Buffer
TTµL
3-1, 3-11,
3-71, 3-899016
Hex Inverter
TTµL
3-1, 3-11,
3-71, 3-899020
Dual JK Flip-Flop
3-1, 3-11,TTµL
3-71, 3-899022
Dual JK Flip-Flop
3-1, 3-11,TTµL
3-71, 3-899030
8-Bit Memory Cell
CTµL
4-64
9033
16-Bit Memory Cell
3-155
Memory9034
256-Bit Read-Only Memory
Memory3-159
9034AXA
256-Bit Read-Only Memory
Memory3·163
9034AXB
256-Bit Read-Only Memory
Memory3-164
9035
64•Bit Read/Write Memory Cell
Memory3-165
9040
RS Flip-Flop
LPDTµL
3-1, 3-149
Dual 3-lnput NANO Gate
9041
LPDTµL
3-1, 3-149
Dual 3-lnput NANO Gate
9042
LPDTµL
3-1, 3-149
3and4 Input NANDGatewith Extender LPDTµL
9043
3-1
LPDTµL
3-1
Dual 4-lnput Gate
9044
Quad 2-lnput Gate
LPDTµL
3-1
9046
Triple 3-lnput Gate
LPDTµL
3-1
9047
DTµL
Dual JK Flip-Flop
3-1, 3-11, 3-113
9093
Dual JK Flip-Flop
DTµL
3-1, 3-11, 3-113
9094
DTµL
3-1, 3-11, 3-113
Dual JK Flip-Flop9097
Dual JK Flip-Flop
9099
DTµL
3-1, 3-11, 3-113
High Voltage Hex Inverter
9109
DTµL
3-1, 3-137, 3-143
High Voltage Hex Inverter
9110
DTµL
3-137, 3-145
RS Flip-Flop
9111
DTµL
3-1, 3-11, 3-113
High Voltage Hex Inverter
9112
3-1, 3-137, 3-147
DTµL

6-1
6-6
6-11
6-16
6.-20
6-22
6-26
6-30
6-34
6-36
6-38
6-42
6-46
6-50
6-54
6-56
6-60
6-64
6-68
5,74
6-80
6-84
6-88
6-94
6-100

3800
3801

6-102
6-104
6-108
6-110
6-114
6-118
6-122
6-126
6-129
. 6·133
6-135
6-137
7-1
7-3
7-5
7-9
7-15
7-17
7-19
7-21
7-23
7-27
7-29
7-33
7-37
7-39
7.43
7-47

1-1

INTEGRATED CIRCUITS NUMERICAL INDEX

Type
9300
9301
9304
9306
9307
9308
9309
9310
9311
9312
9316
9328
9601
9620
9621
9622
9624
9625
9900
9903
9904
9905
9907
9908
9909
9910
9911
9912
9913
9914
9915
9921
9923
9926
9927
9930
9932
9933
9935
9936
9937
9941
9944
9945
9946
9948
9949
9950

Function
MSI 4-Bit Universal Register
MSI 1 of 10 Decoder
MSI Dual Full Adder
MSI Up Down Decode Counter
MSI 7 Segment Decoder
MSI Dual 4-Bit Latch
MSI Dual 4-lnput Multiplexer
MSI BCD Decode Counter
MSI 1of16 Decoder
MSI 8-Bit Multiplexer
MSI 4-Bit Binary Counter
MSI Dual 8-Bit Shift Register
Retriggerable Monostable
Multivibrator
Dual Differential Line Receiver
Dual Line Driver
Dua I Line Receiver
Dual CCSL to MOS Interface Circuit
Dual MOS to CCSL Level Converter
Medium Power Buffer
Medium Power 3-lnput Gate
Medium Power Half Adder
Medium Power Half Shift Register
Medium Power 4-lnput Gate
Low Power Adder
Low Power Buffer
Low Power Dual Gate
Low Power Dual Gate with Inverter
Low Power Half Adder
Low Power Type D Flip-Flop
Medium Power Dual 2-lnput Gate
Medium Power Dual 3-lnput Gate
Low Power Gate Expander
Medium Power JK Flip-Flop
Medium Power JK Flip-Flop
Medium Power Quad Inverter
Dual 4-lnput Extendable Gate
Active Pull-Up Buffer
Extendable Element
Extendable Hex Inverter
Hex Inverter
Hex Inverter
Monostable Multivibrator
Uncommitted Output Buffer
RS Flip-Flop
Quad 2-1 nput Gate
RS. Flip-Flop
Quad 2-lnput Gate
A-C Coupled R-S Flip-Flop

FamilyPage
Number

MSI.
MSI
MSI
MSI
MSI
MS!
MSI
MSI
MSI
MSI
MSI
MSI
TTµL

3-1, 3-11, 3-21
3-1, 3-11, 3-27
3-1, 3-11,' 3-32
3-1, 3-11, 3-38
. 3-1, 3-11, 3-42
3-1, 3-11~ 3.47
3-1, 3-11, 3-51
3-1, 3-11, 3-57
3-1, 3-11
3-1, 3-11, 3-61
3-1, 3-11, 3-67
3-1, 3-11
3-1, 3-11, 3-107

SpecialSpecialSpecialSpecialSpecial
RTµL
RTµL.
RTµL
RTµL
RTµL
LPRTµLLPRTµLLPRTµLLPRTµLLPRTµLLPRTµL
RTµL
RTµL
LPRTµL
RTµL
RTµL
RTµL
DTµL
DTµL
DTµL
DTµL
DTµL
DTµL
DTµL
DTµL
DTµL
DTµL
DTµL
DTµL
DTµL

4-1
4-7
4-13
4-17
4-17
4-66
4-66
4-66
4-66
4-66
4-66, 4-90
4-66, 4-90
4-66, 4-90
4-66, 4-90
4-66, 4-90
4-66, 4-90
4-66
4-66
4-66, 4-90
4-66
4-66
4-66
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-113
3-1, 3-11, 3,113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-113

Type

Function

9951
Monostable Multivibrator
Dual 2-lnput NOR Gate
9952
AND/OR Gate
9953
. AND/OR Gate
9954
AND/OR Gate
9955
Dual 2-lnput Buffer
9956
Flip-Flop9957
Decode Counter
9958
Buffer -Storage Element
9959
Decimal Decoder/Driver
9960
Dual 4-lnput Extendable Gate
9961
Triple 3-lnput Gate
9962
Triple 3-lnput Gate
9963
·AND/OR Gate
9964
AND/OR Gate
9965
9966
AND/OR Gate
Flip-Flop9967
Dual High Speed Latch
9968
AND/OR Gate
9971
AND/OR Gate
9972
4-Bit Binary Counter
9989
4-Bit Shift Register
9997
High Voltage, High Current Driver
SH2001DTµL High Power Driver
SH2002SH2002-P DTµL High Power DriverHigh Current Driver
SH2100High Voltage Driver
SH2101High Voltage, High Current Driver
SH2200
Byte Parity Generator or Checker
SH2204
Ripple Carry Adder
SH2205High Impedance, Wideband AC
SH3000
AmplifierAnalog Switch
SH3001SPOT Analog Switch
SH3002High Impedance Differential
SH3005Comparator
Adjustable Positive DC Voltage
SH3200Regulator
SH3201
Adjustable Negative DC Voltage
Regulator
Dual High Gain Oirerational
SH3741
Amplifier
PNP Quad Core Driver
SH6400PNP Quad Core Driver
SH6401PNP Quad Core Driver
SH6402NPN Quad Core Driver
SH6500NPN Quad Core Driver
SH6501NPN Quad Core Driver
SH65024-Bit Arithmetic Unit
SH80801-2

FamilyPage
Number

DTµL
CTµL
CTµL
CTµL
CTµl
CTµL
CTµL
CµL
CµL
CµL
DTµL
DTµL
DTµL
CTµL
CTµL
CTµL
CTµL
CTµL
CTµL
CTµL
CµL
RTµL
HybridHybridHybridHybridHybridHybridHybridHybridHybrid3-1, 3-11, 3-113
4-38
4-42
4:42
4-42
4-48
4-52
4-23
4-27
4-31
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
4c42
4-42
4-42
4,52 .
4-62
4-42
4-42
4-34
4-88
5-1
5-5
5-9
5-13
5-17
5-21
5-25
5-27
5-29

HybridHybridHybrid

5-31
5-33
5-35

Hybrid5-39

Hybrid5-41

Hybrid5-43

HybridHybridHybridHybridHybrid·HybridHybrid

5-45
5.45
5.45
5-49
5-49
5-49
5-54

INTEGRATED CIRCUIT INDEX BY FAMILY
Type

Function

Page Number

Type

COMPATIBLE CURRENT SINKING LOGIC (CCSL)

9945
9946
9948
9949
9950
9951
9961
9962
9963

MSI
9300
9301
9304
9306
9307
9308
9309
9310
9311
9312
9316
9328

MSI 4-Bit Universal Register
MSI 1 of 10 Decoder
MSI Dual Full Adder
MSI Up Down Decode Counter
MSI 7 Segment Decoder
MSI Dual 4-Bit Latch
MSI Dual 4-lnput Multiplexer
MSI BCD Decode Counter
MSI 1of16 Decoder
MSI 8-Bit Multiplexer
MSI 4-Bit Binary Counter
MSI Dual 8·Bit Shift Register

3-1, 3-11, 3-21
3-1, Hl, 3-27
3-1, 3-11, 3-32
3-1, 3-11, 3-38
3-1, 3-11, 3.42
3·1, 3-11, 3-47
3-1, Hl, 3-51
3-1, 3·11, 3.57
3-1, 3.11
3-1, 3-11, 3-61
3-1, 3-11, 3.57
3-1, 3-11

CCSL Micromatrix™ Quarter Cell
3-169
CCSL Micromatrix™ Dual 4-Bit Comparator
3-1, 3-11, 3-171
TTL Micromatrix™ Array Internal Quarter Cell 3-175
Dual Two-Variable Function Generator
3-179

9006
9007
9008
9009
9016
9020
9022
9601

JK Flip-Flop
JK Flip-Flop
Quad 2-lnput Gate
Triple 3-lnput Gate
Dual 4-lnput Gate
Dual 2·2 Input AND-OR· INVERT Gate
One Half Extender
Dual 4-lnput OR ExtenderSingle 8-lnput Gate
Single Extender 2·2·2·3 AND-OR-INVERT Gate
Dual 4-lnput Buffer
Hex Inverter
Dual JK Flip-Flop
Dual JK Flip-Flop
Retriggerable Monostable Multivibrator

3-1, 3·11, 3-71, 3-89
3-1,3-11,3-71,3·89
H, 3-11, 3-71, 3-89
3-1, 3-11, 3-71, 3-89
3-1, 3-11, 3-71, 3-89
3-1, 3-11, 3.71, 3-89

Dual JK Flip-Flop
Dual JK Flip-Flop
Dual JK Flip-Flop
Dual JK Flip-Flop
High Voltage Hex Inverter
High Voltage Hex Inverter
RS Flip-Flop
High Voltage Hex Inverter
Dual 4-lnput Extendable Gate
Active Pull-Up Buffer
Extendable Element
Extendable Hex Inverter
Hex Inverter
Hex Inverter
Monostable Multivibrator
Uncommitted Output Buffer

3-1, 3-11, 3-113
3·1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
H, 3-137, 3-143
3-137, 3-145
3-1, 3-11, 3-113
3-1, 3-137, 3-147
3·1, Hl, 3-113
3·1, 3-11, 3-113
3-113
3.1, 3-11, 3-113
3.1, 3·11, 3-113
3-1, 3-11, 3-113
3·1,Hl,3-113
3.1, 3-11; 3-113

3-1, 3-11, 3.113
3-1, 3·11, 3-113
3-1, 3-11, 3-113
3·1, 3-11, 3-113
3·113
H,Hl,3·113
H, 3-11, 3.113
3-1, 3-11, 3-113
3-1, 3-11, 3-113

RS Flip-Flop
Dual 3-lnput NANO Gate
Dual 3-lnput NANO Gate
3 and 4 Input NANO Gate with Extender
Dual 4-lnput Gate
Quad 2-lnput Gate
Triple 3-lnput Gate

H,3-149
3-1, 3-149
3-1,3-149
3·1
3·1
H
H

16·Bit Memory Cell
256-Bit Read-Only Memory
256-Bit Read-Only Memory
256-Bit Read-Only Memory
64-Bit Read/Write Memory Cell

3-155
3-159
3-163
3·164
3-165

SPECIAL CIRCUITSSpecial Products
9620
9621
9622
9624
9625

3·1, 3-11, 3-71, 3-89
3-1, 3-11, 3-71, 3-89
3·1, 3-11, 3-71, 3-89
3-1, 3-11, 3-71, 3-89
3-1, 3-11, 3.71, 3-89
H, 3-11, 3-71, 3-89
3-1, 3.11, 3-71, 3-89
3·1, 3-11, 3-107

Dual Differential Line Receiver, Dual Line Driver
Dual Line Receiver
Dual CCSL to MOS Interface Circuit
Dual MOS to CCSL Level Converter

4-1
4-7
4-13
4-17
4-17

Decode Counter
Buffer -Storage Element
Decimal Decoder/Driver
4-Bit Binary Counter

4·23
4-27
4·31
4.34

8-Bit Memory Cell
Dual 2·1 nput NOR Gate
AND/OR Gate
AND/OR Gate
AND/OR Gate
Dual 2-lnput Buffer
Flip· Flop
AND/OR Gate
AND/OR Gate
AND/OR Gate
Flip-Flop
Dual High Speed Latch
AND/OR Gate
AND/OR Gate

4.54
4-38
4·42
4-42
4-42
4-48
4.52
4·42
4-42
4-42
4.52
4·62
4-42
4-42

CµL
9958
9959
9960
9989

DTµL
9093
9094
9097
9099
9109
9110
9111
9112
9930
9932
9933
9935
9936
9937
9941
9944

RS Flip-Flop
Quad 2-lnput Gate
RS Flip-Flop
Quad 2-lnput Gate
A-C Coupled R·S Flip-Flop
Monostable Multivibrator
Dual 4-lnput Extendable Gate
Triple 3-lnput Gate
Triple 3-lnput Gate

Memory9033
9034
9034 AXA
9034 AXB
9035

TTµL
9000
9001
9002
9003
9004
9005

Page Number

LPDTµL
9040
9041
9042
9043
9044
9046
9047

Micro matrixTM Array
4501
4510
4601
4610

Function

CTµL
9030
9952
9953
9954
9955
9956
9957
9964
9965
9966
9967
9968
9971
9972

2-1

i{'

'":

>'

INTEGRATED CIRCUIT INDEX 'ev FAMILY
Type.

Function

Type

Page Number

RTµL
9900
9903
9904
9905 '
9907
9914
9915
9923
9926
9927
9997

Medium Power Buffer
Medium Power 3-lnput Gate
Medium Power Half Adder
Medium Power Half Shift Register
Medium Power 4-lnput Gate
Medium Power Dual 2-lnput Gate
Medium Power Dual 3-lnput Gate
Medium Power JK Flip-Flop
Medium Power JK Flip-Flop
Medium Power Quad Inverter
4-Bit Shift Register

4-66
4-66
4-66
4-66
4-66
4-66
4'66
4-66
4-66
4-66
4-88

Low Power Adder
Low Power Buffer
Low Power Dua I Gate
Low Power Dual Gate with Inverter
Low Power Half Adder
Low Power Type D Flip-FlopLow Power Gate Expander

4-66, 4-90
4-66, 4-90
4-66, 4-90
4-66, 4-90
4-66, 4-90
4-66, 4-90
4-66, 4-90

µA703EµA709µA709AµA709BµA709CµA710µA710BµA710CµA711·µA711CµA716µA716CµA717EµA719µA719C

LPRTµL
9908
9909
9910
9911
9912
9913
9921

µA722
µA722BµA723µA723CµA726µA726CµA727µA727BµA730µA730CµA733µA733CHYBRID CIRCUITSSH2001High Voltage, High Current Driver
SH2002DTµL High Power Driver
SH2002-P DTµL High Power Driver
SH2100High Current DriverHigh Voltage Driver
SH2101High Voltage, High Current Driver
SH2200
Byte Parity Generator or Checker
SH2204
Ripple Carry Adder
SH2205High Impedance, Wideband DC Amplifier
SH3000
Analog Switch
SH3001SPOT Analog Switch
SH3002SH3005High Impedance Differential Comparator
SH3200 Adjustable Positive DC Voltage Regulator
SH3201
Adjustable Negative DC Voltage Regulator
Dual High Gain Operational AmplifierSH3741SH6400PNP Quad Core Driver
SH6401PNP Quad Core Driver
SH6402PNP Quad Core Driver
SH6500NPN Quad Core Driver
SH6501NPN Quad Core Driver
SH6502NPN Quad Core DriverSH8080 4-Bit Arithmetic Unit

5-1
5-5
5-9
5-13
5-17
5-21
5-25
5-27
5-29
5-31
5-33
5-35
5.39
5-41
5-43
5-45
5-45
5-45
5-49
5-49
5-49
5-54

µA737EµA739CµA741µA741CµA751CµA702BµA702CµA703µA703CHigh Gain, Wideband DC Amplifier
High Gain, Wideband DC Amplifier
High Gain, Wideband DC Amplifier
RF-IF Amplifier
RF~IF Amplifier

Page Number

RF-IF Amplifier
6-22High Performance Operational Amplifier
6-26
High Performance Operational Amplifier
6-30
High Performance Operational Amplifier
6-34
High Performance Operational Amplifier
6i36
High Speed Differential Amplifier
6-38
High Speed Differential Comparator
6-42High Speed Differential Comparator
6-46
Dual Comparator
6-50
Dual Comparator
6-54
Fixed Gain, Low Distortion Amplifier
6-56
6-60
Fixed Gain, Low Distortion Amplifier
6-64
Multi-Purpose Amplifier
High Gain RF Amplifier /FM Detector
6-68High Gain RF Amplifier /FM Detector
6-74
10-Bit Current Source
6-80
10-Bit Current Source
6-84
Precision Voltage Regulator
6-88
Precision Voltage Regulator
6-94
Temperature Controlled Differential Pair
6-100
Temperature Controlled Differential Pair
6-102
Temperature Controlled Differential Amplifier 6-104
Temperature Controlled Differential Amplifier 6-108
6-110
Differential Amplifier
Differential Amplifier
6-114
Differential Video Amplifier
6-118
Differential Video Amplifier
6-122
Color TV Chroma Demodulator
6-126
Dual Low-Noise Operational Amplifier
6-129
Frequency Compensated Operational Amplifier 6-133
High Performance Operational Amplifier
6-135
Differential Video Amplifier
6-137

MOS INTEGRATED CIRCUITS
3100
3101
3102
3250
3300
3303
3304
3305/6
3320
3501
3530
3700
3701
3705
3750
3751
3800
3801

LINEAR INTEGRATED CIRCUITSµA702A

Function

6-1
6-6
6-11
6-16
6-20

2-2

5-lnput Gate
Dual JK Flip-Flop
3-lnput Gate
CRT Numeric Character Generator
25-Bit MOS Static Shift Register
Dual 25-Bit Dynamic Shift Register
Dual 16-Bit Static Shift Register
64-Bit l~ Static Shift Register
64-Bit-40 Shift Register1024-Bit Static Read Only Memory
64-Bit Static Random Access Memory
Monolithic 4 Channel Switch
Monolithic 6 Channel Switch
8 Channel Multiplex Switch
10-Bit MOS/LSI D/A Converter
12-Bit A/D Converter
8-Bit MOS/LSI Parallel Accumulator
10-Bit Serial/Parallel - Parallel/Serial
Converter

7-1
7-3
7-5
7-9
7-15
7-17
7-19
7-21
7-23
7·27
7-29
. 7-33
7-37
7-39
7-43
7-47
7-53
7-59

Compatible
Current'
Sinking
Logic

COMPATIBLE CURRENT SINKING LOGIC NUMERICAL INDEX
Type

Page No.

MSI

9300
9301
9304
9306
..9307
9308
9309
9310
9311
9312
9316
9328

3-1, 3-11, 3-21
3-1, 3-11, 3-27
3-1, 3-11, 3-32
3-1, 3-11, 3-38
3-1, 3-11, 3-42
3-1, 3-11, 3.47
3-1, 3-11, 3-51
3-1, 3-11, 3-57
3-1, 3-11
3-1, 3-11, 3-61
3-1, 3-11, 3-67
3-1, 3-11

Micromatrix™ Array

4501
4510
4601
4610

3-169
3-1, 3-11, 3-171
3-175
3-179

TTµL

9000
9001
9002
9003
9004

3-1, 3-11, 3-71, 3-89
3-1, 3-11, 3-71, 3-89
3-1, 3-11, 3-71, 3-89
3-1, 3·11, 3-71, 3-89
3-1, 3-11, 3-71, 3-89

TypePage No.

. 3-1, 3-11, 3-71, 3-89
3-1, 3-11, 3-71, 3-89
3-1, 3-11, 3-71, 3-89
3-1, 3-11, 3-71, 3-89
3-1, 3-11, 3-71, 3-89
3-1, 3-11, 3-71, 3-89
3-1, 3-11, 3-71, 3-89
3-1, 3-11, 3-71, 3-89
3-1, 3-11, 3-107

9005
9006
9007
9008
9009
9016
9020
9022
9601
DTµL

9093
9094
9097
9099
9109
9110
9111
9112
9930
9932
9933
9935
9936
9937
9941

I

3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-137, 3-143
3-137, 3-145
3-1, 3-11, 3-113
3-1, 3-137, 3-147
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113

3-i

Type

Page No.

9944
9945
9946
9948
9949
9950
9951
9961
9962
9963

3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113. 3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113
3-1, 3-11, 3-113

LPDTµL

9040
9041
9042
9043
9044
9046
9047

3-1, 3-149
3-1, 3-149
3-1, 3-149
3-1
3-1
3-1
3-1

Memory9033
9034
9034AXA
9034 AXB
9035

'

3-155
3-159
3-163
3-164
3-165

CROSS :i~EFERE~CE -l,,Function.

:. ' -·· ,_. ;·~:.

LfDTµLTypTpd .·.
65 ns

Gate
Hex Inverter NANO Gate
Quad 2-input NANO Gate
Triple 3-input NANO Gate·
Dual 4-input NANO Gate
8-input NANO Gate
Dual 2-wide Expandable
AND/NOR Gate
4-wide Expandable
AND/NOR Gate
Dual 4-input Power Gate
3-input NOR Gate
4-input NOR Gate
Dual 2-input NOR Gate
Dual 3-input NOR Gate
Quad Inverter NOR Gate
2-2-3 Input AND Gate
Dual 4-input AND Gate
Dual Output, 8 Input
AND Gate
3-3-1 Input A~D Gate
Quad 1 AND Gate
3 Output Quad 2 Input
AND/OR Gate
2 Output Quad 2 In put
AND/OR Gate
BufferDual 2 Input
Dual Buffer
Counter Adapter

F, D
F, D
F,D
F, D

.. . •'pTµF
TypTpd25ns

F,D,C
F, D,CF, D, C
F, P,C;CCSL AND SPECIAL CIRCUITS

'

.·

TlµL
TypTpd
10 ns

' . .

CCSL
MSI

<

RTµL
TypTpd15 ns'

LPRTµL.
TypTpd
40ns

:

,'

MµL

CTµL
TypTpd
3.0 nsCµL

F,FP,D
F,FP,D
F, FP, D

F,C, DF, c; D

..

'·

c;F
C,F
C, F, E
C,F
C,F

;

..

c
c

·'

D

D
D
D
D
D
D

C, FP, E

c

D
D
D

c
F, C
TypTpd
lOns

F, D
F, D
F, D

Counters
BCD Up/Down Counter
Decade Counter
Hexidecimal Counter
Hexidecimal Up/Down Counter

F, D
F, D
F, D
F, D

Registers
4 Bit Shift Register
Dual 8 Bit Shift RegisterF
D

Adders & Comparators
Dual Full Adder
Dual Four-bit Comparator
Half Adder
Adder

TypTpd
25ns

D

F, D
F, D
F, C

FP

= Fairpak®

D

= Dip

C

= T0-5

E·.·Special.,

Multiplexers
Dual 4-input Multiplexer
8-input Multiplexer
Dual 8-input Multiplexer= Flat Pak

'

D

F,D
F, D
F, D

F

•, . '

HlLDTµL

FP,F,D
FP,F,DFP, F, D
FP, F, D
FP,F,D

Decoders
1 of 10 Decoder
1 of 16 Decoder
7 Segment Decoder

Legend:'= T0-5 Epoxy
3-ii

c
c

TypTpdZhs

CROSS REFERENCE Function

LPDTµLTyp Tpd
65 ns

DTµL
Typ Tpd
25 ns

CCSL AND SPECIAL CIRCUITSTTµL
Typ Tpd
10 ns

Memory & Latches
Dual 4 Input Latch
16-bit Memory Cell
256 Bit ROM
Dual 4-bit Latch

CCSL
MSI

HLLDTµL

RTµL
Typ Tpd
15 ns

LPRTµLTypTpd
40 ns

MµL

CTµL
Typ Tpd
3.0 nsD
D

Decimal DEC/DR

D~.,,

32 Gate Customizable Array
48 Gate Customizable Array

F, D
F, D
F, D

96 Gate Customizable Array
Kit Parts
4501

D

4522

D

Gate Expanders
ExpanderTyp Tpd
130 ns
F,C, D

Typ Tpd
20 ns
F,C, D

Typ Tpd
25 ns

Binary Elements
RS Flip Flop
Buffered JK Flip Flop

F, D

F,C, DF, D

FP, F, D
FP, F, D

Dual Flip Flop
AC Coupled Flip Flop
Type D Flip Flop

Typ Tpd
30 ns

F, C, E

Typ Tpd
15 ns

c
c

D

F,C,D

c
F, C

One Half Shift Register
Without Inverter

F, C

D

TypTpd100 nsInterface Functions

TypTpd2 ns

Line ReceiverLine Driver

F,D
F,D
F,D
F, D

CCSL to MOS
MOS to CCSLMultivibrators
AC Coupled One Shot
Retriggerable One Shot
F = Flat Pak

Typ Tpd
20 ns

c

FP, F, D

Dual Rank Flip FlopOne Half Shift Register
With Inverter

Legend:Special

F, D
F,D
F,D

Buffer Memory

Micromatrices

CµL

F, C, DF, DFP = Fairpak®

D = Dip

C = T0-5

E = T0-5 Epoxy

3-iii

CCSL COMPOSITE DATA SHEETCOMPATIBLE CURRENT SINKING LOGICMILITARY TEMPERATURE RANGE -55°C TO +125°C

GENERAL DESCRIPTION

Fairchild Compatible Current Sinking Logic refers to all the standard Fair·child logic circuits that operate by sinking current into the outputs in the
low state and supplying leakage current from the output in the high state.
Current sinking logic is one of the three main forms of logic, the other two
being current sourcing logic and current mode logic.

Since all the input and output levels are compatible, the system designer
can use whichever device suits his application most closely without being
limited to any one logic family. This flexibility can be of great advantage
by allowing the system designer to achieve greater system optimization.
MSI or Micromatrix arrays can be used to decrease package count, improve
speed, and cut costs. TIµL offers high speed and good A.C. noise immunity
where discrete gates and flip-flops are needed. DTµL has lower power,
medium speed, and great flexibility because of wired-OR capability. LPDTµL
offers very low power and reasonable speed.

The Fairchild logic families that rriake up CCSL include Fairchild's 9300
series MSI (Medium Scale Integration), the 4500 DTµL Micromatrix™ array,the 4600 and 4700 TIµL Micromatrix arrays, TIµL (Transistor-Transistor
Micrologic), DTµL (Diode-Transistor Micrologic), LPDTµL (Low Power Diode
Transistor Micrologic), and other circuits that are not members of any specificlogic family. All the circuits that make up CCSL have common power supply
voltages and compatible logic levels at the input and output. .

To achieve the CCSL concept, a set of normalized rules had to be generated.
These are explained and specified for every device in the CCSL family inthe data sheet.

TABLE OF CONTENTS' PageCCSL LOADING RULES ...................... ,...............................................................2
WIRED-OR APPUCATIONS (Examples 1 through 3) ..................... :................3
QUAD 2-INPUT GATES .......................................................:....... :···--······--··----···4Page
R·S FLIP-FLOPS ..................................................................................................5
9111
9945
9948
9040
1-K FLIP-FLOPS ................................................................................................6
9000
9001
DUAL J-K FLIP-FLOPS .......................................................................................&
9020
9022
9093
9094
9097
9099
MONOSTABLE MULTIVIBRATORS ......................................................................7
9601
9941
9951
MEDIUM SCALE INTEGRATION ................... :......................................................7
Shift Registers and Storage Elements
9300-4 bit universal register9328-dual 8 bit shift register9308-dual 4 bit latch
Counters
9306- up down decade counter
9310-- up decade counter
9316- up binary counter
Combinational logic ...................................................................................8
9301-1 of 10 decoder
9311-1 of 16 decoder
9304-Dual full adder
9307-BCD to 7 segment decoder

9002
9946
9949
9046
TRl!>LE 3-INPUT GATES ...................................................................................4
9003
9962
. 99639047
DUAL 4-INPUT GAJES ·.....................:.................................................................4
9004
9930
9961
9044
8-INPUT GATE ., .................................................................................................4
9007HEX INVERTERS ................................................................................................5
9016
9935
9936
9937
AND-OR-INVERT GATES AND EXTENDER . ..... ....................... .. ...... . .. .. ........5
90.05
9006
9008
BUFFER ELEMENTS ...........................................................................................5
9009
9932
9944

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD. DRlVE; MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-1

A DIVISION OF FAIRCHILD CAMERA ANO INSTRUMENT CORPORATION

I

FAIRCHILD CCSL COMPOSITE ·oATA SHEEt (~55!.CTO +22s 0 'C)
TABLE OF CONTENTS (Cont'd.)

Page

Page
9309-Dual 4 bit multiplexer •........... .................... ,..................8~312-8 bit multiplexer
4510-Dual 4 bit comparator

9622-Line receiver9624-CCSL to MOS converter
9625-MOS to CCSL converter

MEMORIES ....................:............................................................................. :.99033-16 bit scratch pad memory.
9034-256 bit read-only memory . .
9035-64 bit read/write memory cell

SPECIAL LOW POWER GATES ............................ ,: ....'.......... :......;...................9
9041
9042
(.
9043

INTERFACE ELEMENTS ·················--·····························-~---····························99620-U,ne receiver
9621·:.-line driver

EXTENDER INPUTS ·-----~---··················:~ ............ ;....... :..................................10
APPENDIX .................................................................................................. 10

CCSL LOADING RULES..;...55•c TO +125°C TEMPERATURE RANGE
GENERAL INFORMATIONThe Fairchild CCSL loading rules were established to give the systems
designer exact rules for combining the different families of FairchildCompatible Current Sinking Logic elements.

SHORTED INPUTSIn the case where unused inputs of an AND gate are shorted to a driven
input, the high level input load factor for the inputs 'wi.n be the numberof inputs shorted together times the high level input load factor for one .
input. The low level input load factor for the inputs will be the same asthat for a single input.
····

In establishing the rules, worst case limits and conditions are guaranteed
providing:

1. The loading rules are obeyed
2. Yee is maintained at 5.0 V ±10% (4.5 V to 5.5 V)
3. The ambient temperature is maintained between -55°C and+125°C.
The worst case limits guaranteed are:Maximum low level output voltage (VOL)Maximum low level input voltage (V1L)
Minimum high level output voltage (V0 H)
Minimum high level input voltage (V1H)
High level D.C. noise immunity
Low level D.C. noise immunity=

NORMALIZING FACTORSThe normalizing factors used to· derive these loading rules are listed
below. They are included in the data sheet primarily as a guideline whenworking with open collector devices such as the DTµL 9944 or the MµL
9033. They allow the designer to determine:..
1. What collector pullup resistor is required to drive the high levelloads, and supply the leEX while maintaining VoH·
2. How much the low level fanout must be reduced because of thepullup resistor.

0.4 V
0.7 V
2.5 V
2.1 V
0.4 V
0.3 V

LOGIC
LEVEL

LOADING RULES

In this data sheet the following notation has been chosen to indicate theinput loading and output drive factors for all logic elements.
INPUTSHighOUTPUTS

A/B

Low

X/Y

WORST CASE UNIT
LOAD/DRIVE FACTOR

Ve~ ..
SUPPLY VOLTAGE

SµA

4.5 V to 5.5 V .

124µA

4.5V.

160µA

5.5V

LOGIC ELEMENTWIRED·OR APPLICATIONS · ·=A (high level input load factor)
maximum normalized input current
drawn into an input when the input is at a high level.
B(low level input load factor) = maxiinum normalized input current
drawn out of an input when the input is at a low level.
X (high level output drive factor) = minimum normalized outpiit current
which the output can supply at a high level while maintaining
Y.9 H 2.5 V_
Y(low· level output drive factor) = minimum normalized output current
which the output tan sink at a low level; while maintaining'V0 i:<0.4V

It is possible to perform the wired-OR ;function by connecting together
the outputs of any of the DTµL circuits, except ttie'9932 and 9950, or of
any circuit that has the words "open collector" rather than a high level
output drive factor.
·· ··In wired-OR applications each .gate must be able to sink the current
from all the pullup resistors, as well a~. the current from the load being
driven at the common wired-OR point.· To calcutate .the load driving
capability of a wired-OR configuration simply fmd the equivalent low
level load factor for all the excess load resistors and subtract it fromeach gate's low level drive factor. For DTµL With GK puliup resistor, theequivalent load factor is 8, for DTµL with 2K puilup, it is 22. For a
discrete pullup resistor, the load factor can be calculated from thenormalizing factors above. The high level output drive factor of thegates performing the wired-CYR function is the sum of the high level
drive factors of all the gates in the combination. See Example 3 for an
example of a wired-OR application.

>

Any: CCSL device can drive any combination of other CCSL devices aslong as two conditions are met:
· l. The sum of the high level load factors at any node must be lessthan or equal to the high level drive factor at that node.
2. The sum of the low level load factors at any node must be lessthan or equal to the low level drive factor at that node.

3-2

. F'Al~~HILD CCSL COMPO$ll'E DATA SHEET (--55°C TO +125°C)
EXAMPLE 1:
The output drive factor of the 9932 is 800/235. The input load factorof the 9945 is 4/19. First divide the high level input load factor of the9945 (4) into the high level drive factor of the 9932 (800). This gives
200 as the number of 9945 clock inputs the 9932 may drive in thehigh state. Then repeat the procedure with the low level load factor andlow level drive factor. This gives 12.4 as the number of 9945· inputs a9932 can drive in the low state. The low state is the lower number,so it is necessary to limit the number of 9945's to 12.

DTµL 9932 driving DTµL 9945 clock lines.
Problem: How many .994S's can be driven by one 9932?
9945

9932

~·t

c

:

~---it

I

:

s

I
I
I
I

I
I.--

EXAMPLE 2:.,.

'

The output ·drive factor of the 9002 is 264/110. The input load factorof the 9946 is 1/9.4. Dividing the low level input load factor of the9946 into ·the low level drive factor' of the 9002 gives - 11.7. Dividing
the high level input load factor into the high level drive factor gives 264.
Therefore, the fanout is limited to 11 by the low level load and drive
factors.

TTµL 9002 drivirig DTµL gates..
Problem: How many gates can one 9002 drive?
9002

9946

=D-r:D1
I

t--D---·
I

I•• ..,

I

.,_

+--1

)>---·I
I

EXAMPLE 3:
The output drive factor of the DTµL 9946 is 36/94. The output pull-up
resistor is 6K, so 8 must be subtracted from the low level drive factor
for each extra output tied together in the wired-OR configuration.
With four outputs tied together, there are three excess pull-up resistorsand 24 must be subtracted from 94 (the low level output drive factorof each 9946) to give an output low level drive factor of 70. The output
high level drive is the sum of all the high level drive factors of thefour 9946's. Thus the high level load factor of the combination is
36 + 36 + 36 + 36 144. The 9002 inputs have load factors of 12/10,
so it can be determined, as in previous examples, that the limiting
factors are .the low level drive and load factors and that the four gatesin the wired-OR will drive seven 9002 inputs.

4 DTµL 9946's in a wired-OR configuration.
Problem: How many TTµL 9002 inputs will the output drive?
DTµL 9946

=

••J.:

3-3

FAIRCHILD CCSL COMPOSITE DATA SHEET '(~55°C::ro +r25°C). ;j

QUAD 2-INPUT NAND GATES

TT pl

12110

I=0-- 2941110

DMIBKJ

DTpL 12111

LPDTpL

1/9.4/=D-- 38/94

1/9.4/=Q--108/85

2/1 ::::0-10110 •<,f

Vee= Pin 14
Gnd =Pin 7

9002

9946

9949

PIN CONFIGURATION

9046

TRIPLE 3-INPUT NAND GATESLPDTµlTTpl

12110

I==o---

DTpL 12K)

DTpL l&KJ
284/110

1/9.41:::0---- 38/94

1/9.41:::0---- 108/85

211/3=0-- 10/10,' .

... . ,,

9003

9962

9963

9047

DTpL{2K){~

Vee= Pin 14
Gnd =Pin 7~

PIN CONFIGURATIONDUAL 4-INPUT NAND GATESDTpL l&KJ

TTpl
12110 I~ 284/110

1 / 9 . 4 1 y 38/94"

1/9.41==f")-- 108/85.=:::s:E

E

2/1

.

E

*II

9004

9930

9961

8-INPUT NAND GATE

•..

TTpL

'

12/10
Vee= Pin 14
Gnd="·Pin 7

9007

10/10

Vee= Pin 14
Gnd =Pin 7
Extenders are not present.oriileo4• ·.:.:·PIN CONFIGURATIO~';'.

9044• Extender Inputs, see note on Page 10

3-4

....

LPDTpl

I

FAIRCHILD CCSL COMPOSITE DATA SHEET (-55°C TO +125°C)
HEX INVERTERS
4

6
8

TTpL

12/10

--t>-- 264/110

DTpL• /9.4DTµL (21()

10

119:4--[>--:- 108/85

12

DTpL 16K)--t>-- 36/94

1/9.4--t>-- 36/94

Vee= Pin 14
Gnd =Pin 7

9016

9935

9936

PIN CONFIGURATION

9937• Extender Inputs, see note on Page 10

AND-OR-INVERT GATES AND EXTENDER

18/15 j1

1.5/1.51~~EMIT
12

12/10/>TTPL
264/1106 264/110
12110

COLL

I4

284/110
Vee= Pin 14
Gnd =Pin 7• Up to four 9006 Extende~ may betied to these terminals

1.5/1.5
1811s
Vee= Pin 14
Gnd = Pin 79005 EXTENDABLE
HALF

9005 NONEXTENDABLE
HALF

Vee= Pin 14
Gnd =Pin 7

I• Up to four 9006 Extenders may betied to these terminals

9006

9008

DUAL 4-INPUT NANO BUFFERS

DTpL

DTpL

TTpL
24/20 [~ 794/330

l/9.4(~800/235

1/9.51 ~ OP£N COLLECTOR/254• /9.4• /9.4=::s: [=::s:E""'"t--~E

Vee= Pin 14' - - - - - - ' Gnd =Pin 7

Extender inputs not present on 9009

9009

PIN CONFIGURATION

9944

9932

• Extender Inputs, see note on Page 10-

R-S FLIP-FLOPS
15K

1 6

Vee= Pin 14
Gnd =Pin 7

911~

2/19
10

Sp

Sp

1 6

T DTpL
l2K)
0 8
c
Co
Y1
2/19

2/19
10

Vee= Pin 14
Gnd =Pin 7

2/19

9945

5
2/19

9948

3.5

2/2.5
11

So
LPOTpLT OTpL} 108/85
12K)
9
c
0
Co
Vee= Pin 14
Gnd= Pin 7

5

10

1 6

s

OTpL .
l&K)
c
0 9
Co

Vcc~5
15K

Co
Vee= Pin 14
Gnd =Pin 7

4
2/2.5

9040

6

9 }10110

FAIRCHILD CCSL COMPOSITE DATA SHEET (~55°C TO +125°C)
J-K FLIP-FLOPS
33;27

33/27
2

So

So

TTlll.

TTlll

T

1

6
} 240/100) 2..01100

K

D

8

D 8

K

Cg

y,3
33/27

Co
Vee= Pin 14
Gnd =Pin 7

Y13
33/27

Vee= Pin 14
Gnd =Pin 7

9001

9000

DUAL J-K FLIP-FLOPS

2/19
1 6
TT pl
r-t----iT} 240/100

FFI

0 1

-'-t-+--4:1.-IKCo

48/40 14ft

13:+--1--V-\I
12/10 -'"'

1/6.3 34119 lOTpl
T. FF1

1/6.3 2K

1I '-+---IT FF2

DTlll.
FF1} 38/94}

K 16KJ

36/94

0

l6K)
2/19
J,10
Sg

iTlll.

9 }240/100

1/6.3 11
4/19 13
12.1/6.3K

12/10 / 12

I 8
1 6

I

1 10

•'

So

So

33/27

24/20 2

4

2/19
4

Co

11

8

12

DTpL
9 }36/94
ff2(6K) O

1 8

J

DTpl
T Ff2
(6K)
K

} 36/94

1/6.3 {

0 9

115

Vee= Pin 16
Gnd =Pin 8

33/27

Vee= Pin 14
Gnd =Pin 7

9020

Vee= Pin 14
Gnd =Pin 7

4/38

9097

9093

33/27

2/19
4

2/19
4

So
TT pl

0 1

Olpl
FF1.

4/15 .l.o i
1/6.3 2

1 8

1 6

1/6.3
} 240/100

FF1

So

So

1 6

K (2K)

48/40 14

OTpl
T FF1
12K)

} 108/85

5 } 108/85

K

0 5

2/19
10

8/37 1

24/20

So
13:+-~V-"'
12/10 -"''-+---I T

12/10 12

TTpL
ff2

K

1/U 11I

4/15 13

DTpl
T Ff2

1/6.3 12K (2K)

11

1 8
}

9
0

108/85

1/6.3{
12

1 8
OTpl
T FF2
K (2KJ

Co
Vee= Pin 16
Gnd= Pin 8

15
33/27

9022

Vee= Pin 14
Gnd =Pin 7

Vee= Pin 14
Gnd =Pin 7

9094

3-6

4/38

'9099

9 } 108/85.

FAIRCHILl);CC,SL COMPOSITE DATA SHEET.(....:55°CTO +125°C)
MONOSTABLE MULTIVIBRATORSTO Vee

12/10

l1

8

TO Vee1 6

1 6}144/63SSSS} 30/87...o 6.

0SS0Vee= Pin 14
Gnd =Pin 7

Vee= Pin 14
Gnd =Pin 7} 30/8711

Vee= Pin 14
Gnd =Pin 7

The DTµL 9941 is NOT
recommended for new
designs; use the 9601.

9601

The DTµL 9951 is NOT
recommended for new
designs; use the 9601.

9941

9951
NOTE: The maximum input fall time to trigger is: 25 ns
for a 1.0 volt swing; 50 ns for a 2.0 volt swing;
100 ns for a 4.0 volt swing.

• Extender Inputs, see note on Page 10

MEDIUM SCALE INTEGRATIONSHIFT REGISTERS AND STORAGE ELEMENTS
12/10

24/20

-- -18/15- 12/10

12/10,28;239

12/10,........+,....
4'24/20

PE

'1D

12

11

18/15

72/60

18/15 _..,.l-~-.I

Js·i ! 6' . 7
~

12/10

13

36/30 -..,.--&..,;'I
72/60

5- --·Po P1 1.P2 P3

Cp

24/20

12/10

4

Os
12/10 ' - - y - - 'Vee= Pin 16
Gnd = Pin.8

72/60

12/10

Di 07

Do

72/60
72/60

10&/90Vee= Pin 24
Gnd =Pin 12

9300

9308

9328

4 BIT UNIVERSAL REGISTER

DUAL 4 BIT LATCH

DUAL 8 BIT SHIFT REGISTERCOUNTERS
8/6. 78. 6.724/20

24/20~

~

211

9

11

3

5

8

~

12. 6010

12/10 7
10
72, 60

Vee=Pin24
Gnd = Pin 12

24/20

I

2

P2

CpMR

llo· 0102

72/60

15 72/60

14

Vee= Pin 16
Gnd = Pin 8

9310
UP DECADE COUNTER

3-7

72/60
24/20 \

03

1 14 13 12 11
12;10 ~

9306
UP/DOWN DECADE COUNTER

P3

Cn 9310 UP DECADE COUNTER TC

13

2

11

12/10 '----y----'

72/60

Vee= Pin 16
Gnd =Pin 89316
UP BINARY COUNTERFAIRCHILD CCSL COMPOSITE DATA SHEET (-55°C TO +125°C)
MEDIUM SCALE INTEGRATION (Cont'd.)
COMBINATIONAL LOGIC
48/40

12/10

12/10

~

~
23

22

21

20

Ao

Ai

Az

A3

12/10

,---A-----..
15 14 1

2

Ao Al

A3

A2

93011/10 OECODER

9304 FULL AQDER 1

93111/16 DECODER
0 1 2 3 4 5 6 7 B 9 10 1l 12 13 14 15s5

216/90120/100
120/100

Vee= Pin 16
Gnd =Pin 8

Vee= Pin 24
Gnd =Pin 12

9301
1 OF 10 DECODER

Vee= Pin 16
Gnd =Pin 8

9311
1 OF 16 DECODER

12/10
~

11

12

R80abcdefg

10

9304
DUAL FULL ADDER

12/10

12/10

,.....--A--..
9

6

12/10 13·s,i1oa l1a 121 l3a:

12/10 3s1 z,

7lob l1b l2b 13b9309 DUAL 4 BIT MULTIPLEXER

9307 7 SEGMENT DECODER

Za

14
216/90'.15240/100zb

zb

2
216/90240/100

I

14
15
216/90 240/100

Vee= Pin 16
Gnd ==Pin 8

Vee= Pin 16
Gnd =Pin 8

Vee= Pin 16
Gnd=Pin8

9307
BCD TO 7 SEGMENT DECODER

9~12

9309
DUAL 4 BIT MULTIPLEXER

8 BIT MULTIPLEXER

4/20

4/20
11 10

9 8

Ao Bo Al B1

4/20

13

11

168/70 216/90
168170240/100
240/100

ST

4/20

COMPARATOR I

n

A=B

14

15

ST

7 6

A2 82 Aa 83

COMPARATOR IIn
Vee= Pin 24
Gnd =Pin 12

36/30 48/40

4510
DUAL 4 BIT COMPARATOR

3-8

5 4

A=B

2
3
36/30 48/40

FAfRCHILD CCSL CQMPOSITE DATA SHEET {-55°C TO +125°C)·
MEMORIES
20/9.4320/1020/9.4

40/20

26

H/H!
80/69

1

Xg

2

lC1

Wu

10

3

X2

E A4 A3 A2 A1 Ao

4

X3

9034 32W x 88 x ROM

13

Yg

9033 MEMORY

Ag CS

9035 MEMORY

20/10

Do o1 D2 03 04 05 Os 07

12

Y1

11

Y2

Y1 Y2 y3 y4 Ys Ys Y1 y9

10

Y3

OPEN COLLECTOR/63
Vee= Pin 16
Gnd =Pin 8
OPEN COLLECTI>R/125

Vee= Pin 14
Gnd =Pin 7

9033
16 Bit Scratch Pad Memory

NOTE: The 9034 is programmed on a custom basis. Contact your. Fairchild salesman for more information.

OPEN COLLECTOR/62

Vee= Pin 28
Gnd =Pin 99034
32 Word by 8 Bit Read Only Memory

9035
64 Bit Read/Write Memory Cell

INTERFACE ELEMENTS
5 130Q3~D-112~• /110 _11__'

1/10{~~~57/9.4
Inputs are differential, one pair attenuated, onepair nonattenuated ..

13 57/94-.·.. ' 1133~

Vee= Pin 14
Gnd =Pin 7+SV= Pin 8

Outputs are extremely low impedance to drive longlines. Back matching resistors for 130 ll line areprovided.
·Vee= Pin 14· Gnd =Pin 7+BV= Pin 8

9620
Dual Differential Line Receiver

9621
Dual Line Driver

1;::~1-;-::i. .
lO

·

• /9

1/9

{:it::LJ-1-

MOS
LEVELS....r-u_ 57/94

~
10
1/9.4

57/9.4''

VEE= Pin 8
Vee= Pin 7
Gnd =Pin 14
Si= Pin 1
If Si =Vee, then output is normallyhigh with inputs open
If Si = Gnd 7, then output is normally
low with inputs open

9622
Dual Differential Line Receiver(CCSL Threshhold Inputs)[-y--l...Lt>-L~

Vee= Pin 14
Yoo= Pin 7
Gnd =Pin 1
TAP= Pin 13

MOS LEVELS

9624
CCSL to MOS Converter

12/10

Gnd =Pin 1
Yoo = Pin 7
Vee= Pin 14

9625
MOS to CCSL Converter• Extender Inputs, see note on Page 10

SPECIAL LOW POWE~ GATESI

4211\~ 10/10•;1~
15KINOMJ 2~~

OPEN COLLECTOR/10

v~
15KINOM) 8
~10/0

2/1

2/11

~ OPEN COLLECTOR/10

Vee= Pin 14
Gnd =Pin 7

9041

I~ OPEN COLLECTOR/10.~

2/1/l . 15KINOM) 5
Vee --'INv---=13

15KINOMJ

211[~ 10/10
• 11

2/1 [

1 10/015KINOMJ 3

v~
11

4

Vee= Pin 14
Gnd =Pin 7

9042• Extender Inputs, see note on Page 10

3-9

•;1

[~
~

OPEN eOLLEeTOR/10

9043

Vee=Pin 14
Gnd =Pin 7

FAIRCHILD CCSL COMPOSITE DATA SHEET (--55°C TO .;f125°C)
EXTENDER INPUTS
Extender inputs require OTµL 9933 or external silicon diodes in order
to be used. Use of extender pins without diodes is not recommended.
The low level load factor is determined by the resistor already in·eluded in the device. The high level load factor is usually negligible
as most discrete silieon diodes have leakages of less than 1.0 µA at+125°C. A leakage of 1.0 µA corresponds to an input high level loadfactor of 0.2. The normalizing factor given in the introduction canalways be used to determine the load factor of a diode. In order tomaintain CCSL levels the diode should have <0.65 volt drop at 1.5 mAof current at 25

•c.

·'

APPENDIX
This maximum allowed input low current is normalized to give the lowlevel input load factor.

The purpose of this appendix is to cover in more detail the testing of·ccsL products and thereby show how the logic levels ar11 guaranteed.
The testing must guarantee the input loading in both the high and low
states and also must guarantee the output drive capability in both thehigh and low states. Both input and output characteristics must be
guaranteed at worst case Vee and input conditions and over the temperature range.

The output must be tested to insure that it meets the required high _and.. ...
low level drive factors, while maintaining the required noise immunity.
To test the low level output drive factor, all inputs are maintained at
V1H, the minimum high level input voltage. The Vee is maintained at
4.5 Volts and current is forced into the output. This current, IOL, isrelated to. the output low level -drive .factor by the normalizing fa~torsfor 4.5 Volts. The output voltage is measured to insure that it is lessthan VOL.

The examples given are for NANO gates. The application of the ideas
to more complex devices is very much the same, excePt that manipulation of the inputs to achieve a required condition is more complex.
Testing is always done with the worst case set of inputs.
First, consider the testing of the inputs to guarantee the input loadfactors. The high state input load current is tested by grounding theother inputs of the gate under test and measuring the input current
with a voltage much higher than VoH· Maximum Voc is applied to thedevice as this has been found to be the worst case for TTµL circuits. The
maximum allowed input high current is normalized to give the high level
input load factor,

loL TEST CIRCUIT

Ycc=5.5V...~IT

The test is repeated with Vee= 5.5 Volts arid the IOL determined by
the 5.5 Volts normalizing factor.
\'',

IR TEST CIRCUITThe output is then tested for the output high level drive factor. The
maximum low level input voltage is applied to one input at a time withthe other inputs held high~ Current is then pulled out of the output.
This current, loH• is related by normalizing factors to the output highlevel drive factor. The output voltage is measured to insure that it
exceeds VoH·

To test the low level input load factor, a voltag!f equal to V0 L is applied
to one input and the current flowing out of the input is measured. The
other inputs are tied to a high voltage. Maximum Vee is used.

b'T
~
y~H
Eich input is tested separately
IF TEST CIRCUIT
loH TEST CIRCUIT

3-10

CCSL COMPOSITE DATA SHEETCOMPATIBLE CURRENT SINKING LOGICTEMPERATURE RANGE 0°C TO 75°C

GENERAL DESCRIPTION
Fairchild Compatible Current Sinking Logic refers to all the standard Fair·child logic cfrcuits that operate by sinking current into the outputs in the
low state and supplying leakage current from the output in the high state.
Current sinking logic is one of the three main forms of logic, the other two
being current sourcing logic and current mode logic.

can use whichever device suits his application most closely without being
limited to any one logic family. This flexibility can be of great advantage
by allowing the system designer to achieve greater system optimization.
MS I or Micromatrix arrays can be used to decrease package count, improve
speed, and cut costs. TTµL offers high speed and good A.C. noise immunity
where discrete gates and flip-flops are needed. OTµL has lower power,
medium speed, and great flexibility because of wired-OR capability. LPDTµL
offers very low power and reasonable speed.
To achieve the CCSL concept, a set of normalized rules had to be generated.
These are explained and specified for every device in the CCSL family in,
the data sheet.

The Fairchild logic families that make up CCSL include Fairchild's 9300
series MSI (Medium Scale Integration), the 4500 DTµL Micromatrix™ array,the 4600 and 4700 TTµL Micromatrix arrays, TTµL (Transistor-Transistor
Micrologic), DTµL (Diode-TransistoF Micrologic), LPDTµL* (low Power Diode
Transistor Micrologic), and other circuits that are not members of any specificlogic family. All the circuits that make up CCSL have common power supply
voltages and compatible logic levels at the input and output.

* Since LPDTµL is not manufactured in a 0°C to 75°C temp range, it is notincluded in this data sheet. The load rules given for it in the -55°C to+125°C temp range CCSL data sheet apply also for 0° to 75°C operation.

Since all the input and output levels are compatible, the system designer

TABLE OF CONTENTS
Page

Page
R·S FLIP-FLOPS ..................................................................................................5
9lll
9945
9948
l·K FLIP-FLOPS ................................................................................................6
9000
9001
DUAL J-K FLIP-FLOPS ........................................................................................&
9020
9022
9093
9094
9097
9099
MONOSTABLE MULTIVIBRATORS ......................................................................7
9601
9941
9951

CCSL LOADING RULES ......................................................................................2
WIRED-OR APPLICATIONS (Examples 1 through 3) ......................................3
QUAD 2-INPUT GATES ......................................................................................4
9002
9946
9949
TRIPLE 3-INPUT GATES ....................................................................................4
9003
9962
9963
DUAL 4-INPUT GATES ........................................................................................4
9004
9930
9961
8-INPUT GATE ....................................................................................................49007
HEX INVERTERS ................................................................................................5
9016
9935
9936
9937
AND-OR-INVERT GATES AND EXTENDER ..........................................................5
9005
9006
9008
BUFFER ELEMENTS ............................................................................................5
9009
9932
9944

MEDIUM SCALE INTEGRATION ..........................................................................7
Shift Registers and Storage Elements
9300-4 bit universal register
932S-dual 8 bit shift register
930S-dual 4 bit latch
Counters
9306-up down decade counter
9310-up decade counter
9316-up binary counter

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-11

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD CCSL COMPOSITE DATA SHEET(O~C,T0·75°C)
TABLE OF CONTENTS(Cont'd.)

Page

Page

Combinational logic·---·--·---·····-·--·-·---------·----------···········-·--······-················-·-•
9301-1 of 10 decoder
9311-1 of 16 decoder
9304-Dual full adder
9307-BCD to 7 segment decoder
9309-Dual 4 bit multiplexer
9312-8 bit multiplexer
4510--Dual 4 bit comparator

INTERFACE ELEMENTS .................................................................................9

MEMORIES ······-"·-·-·-·····-······-···--··················:.................................................•9mENDER INPUTS ........................:............'. ...........'. .....................•...........10
APPENDIX ................:.................,.......·:.... ~.: ..... ._........~----~·-:·-·········'. .... :.. ~ .... .io

9033-16 bit scratch pad memory
9034-256 bit read-only memor/
9035--64 bit read/write memory cell

9620--Line receiver
9621-line driver9622-Line receiver9624-CCSL to MOS converter
9625-MOS to CCSL converter
91Qg......HLLDTµL to CCSL hex converter' 1 ·9112-CCSL to HLLDTµL hex converter·····CCSL LOADiNG RULESo•c TO 75°C TEMPERATURE RANGE
GENERAL INFORMATIONThe Fairchild CCSL loading rules were established to give the systems
designer exact rules for combining the different families of FairchildCompatible Current Sinking Logic elements.

SHORTED INPUTS
In. the case where unused inputs of an AND gate are shorted to a driven
input, the high level input load factor for the inputs will be the numberof inputs shorted together times the high level input load factor fo(oneInput. The low level input load factor for the inputs will be the same asthat for a single input.
·.

In establishing the rules, worst ca.se limits and conditions are guaranteed
providing:·
1. The loading rules are obeyed
2. Yee is maintained at 5.0 V ±5% (4.75 V to 5.25 V)
3. The ambient temperature is maintained between 0°C and 75°C.

NORMALIZING FACTORSThe normalizing factors used to derive these loading l'l!ll!s are listed.
below. They are included in the data sheet primarily as a guideline whenworking with open collector devices such as the DTµL 9944 or the MµL
9033. They allow the designer to determine:

The worst case limits guaranteed are:=Maximum low level output voltage (V0 L)
0.45 V
Maximum low level input voltage (V1L)= 0.85 V
Minimum high level output voltage (V0 H) = 2.4 V
Minimum high level input voltage (V1H)
2.0 V
D.C. noise immunity· ::::: . 0.4 ; V

1. What collector pullup resistor is required to drive 'the high levelloads, and supply the lcex while maintaining YoH·
2. How much the low level fanout must be reduced because of thepullup resistor.

=

LOADING RULES
In this data sheet the following notation has been chosen to indicate theinput loading and output drive factors for all logic elements.
IMP TS

LOGIC
LEVEL

WORST CASE UNIT
LOAD/DRIVE FACTOR

Yee · · .
SUPPLY VOLTAGE·..

High

5µA

4.75 V to 5.25 V

OUTPUTS

Low

. X/Y

A/I

•'·;

141 µA
160µA

4.75V
·.,:

5.25V

LOGIC ELEMENTWIRED·OR APPLICATIONS==

A (high level input load factor) maximum · normalized input current
drawn into an input when the input is at a high revel.
B (low level input load factor) maximum normalized lriput current
drawn out of an input when the input is at a low level.
X (high level output drive factor) = minimum normalized output current
which the output can supply at a high level while maintaining
YoH> ~.4V.
.
.
Y(low level output drive factor) = minimum normalized output current
which the outplit .can sink at a low level, while maintaining· YoL<t45V .

It is possible to perform the wired-OR function by connecting· together
the outputs of any of the DTµL circuits, except the 9932 and 9950, or of
any circuit that has the words "open collector" rather than a high level
output drive factor.
In wired-OR applications each gate must be able to sink the current
from all the pullup resistors, as well as the current from the load being
driven at the common wired-OR point. To calculate the load driving
capability of a wired-OR configuration simply find the equivalent low
level load factor for all the excess load resistors and subtract it fromeach gate's low level drive factor. For DTµL with 6K pullup resistor, theequivalent load factor is 8, for DTµL with 2K pullup, it is 22. For a
discrete pullup resistor, the load factor can be.. C<!lculated from thenormalizing factors above. The high level output drive factor of thegates performing the wired-OR function is the sum of the high level
drive factors of all the gates in the combination. See Example 3 for an
example of a wired-OR application.

Any CCSL device can drive any combination of other CCSL devices aslorig as two conditions are met:
1. The sum of the high level load factors at any node must be lessthan or equal to the high level drive factor at that node.
2. The sum of the low level load factors at any node must be lessthan or equal to the low level drive factor at that node.
3-12

.FAIRCHltD CCSL COMPOSITE DATA SHEET (0°C TO 75°C)
EXAMPLE 1:

The output drive factor of the 9S32 is 600/235. The input load factorof the 9945 is 6/19. First divide the high level input load factor of the9945 (6) into the high level drive factor of the 9932 (600). This gives
100 as the number of 9945 clock. inputs the 9932 may drive to in thehigh state; Then repeat the procedure with. the low level load. factor andlow level drive factor. This gives 12.4 as. the number of 9945 inputs a9932 can drive in the low state. The .low state is the lower number,so it is necessary to limit the number of 9945's to 12.

DTµL 9932 driving DTµL 9945 clock lines.
Problem: How many 9945's can be driven by one 9932?
9945

6
9932

~-tI
I
I

I
I

I
I
I
I

I
L---

EXAMPLE 2:

TTµL 9002 driving DTµL gates.
Problem: How many gates can one 9002 drive?
9002

9946

=D-r-=D1

The output drive factor of the 9002 is 240/100. The input load. factorof the 9946 is 2/9.4. Dividing the low level input load factor of the9946 into the low level drive factor of the 9002 gives ~ 10.5. Dividing
the high level input load factor into the high level drive factor gives 120.
Therefore, the fanout is limited to 10 by the low level load and drive
factors.

:+---b-·.:· --1
II•• ,..

I

.,_

+--1

Jo---·I'

EXAMPLE 3:
4 DTµL 9946's in a wired-OR configuration.
Problem: How many TTµl 9002 inputs will the output drive?
DTµL9946

=D
=D
=D
=D

TTµL9002's

1··~D-I~·

The output drive factor of the DTµL 9946 is 36/94. The output pull-up
resistor i~ 6K, so 8 must be subtracted from the low level drive factor
for each extra output tied together in .the wired-.OR configuration.
With four outp1,1ts tied together, there are three. excess pull-up resistor~and 24 must be suptracted from 94 (t.he low level output drive factorof eac.h 9946) to give an output· 10¥.! level drive factor of 70. The output
high level drive is the sum of all the high level drive factors of thefour 9946's. Thus the high level load factor of the combination · is
36 + 3.6 + 36 .+ 36 = 144. The 9002 inputs have load factors of 12/10,
so it can be . determined, as in previous examples, that the lim,iting
factors are the low level drive and load factors and that th!! four gatesin the wired-OR will drive seven 9002 inputs.

It--L--

3-13

FAIRCHILD CCSL COMPOSITE DATA SHEET (0°C TO 75°C)
QUAD 2-INPUT NAND GATES
TTpl

121101=D--

DTpL (2KJ

DTpL (6KJ

2401100

2/9.4 /

=D--

2/9.4 j

36/94

=D--

108/85

Vee= Pin 14
Gnd =Pin 7

9002

9946

9949

DTpL (BK)

DTpL (2K)PIN CONFIGURATIONTRIPLE 3-INPUT NAND GATES

13

TipL

12110

I=a---

2401100

2/9.4

2/9.41:::0--- 36/94

l=Qo---

4

108/85591011

Vee= Pin 14
Gnd=Pin 7

9003

9962

9963

PIN CONFIGURATIONDUAL 4-INPUT NAND GATESDTpL(6K)

TTpl

2110!~ 240/100

2/9.4

DTpL(2KJ\gj....- 36/94

2/9.4. ~ 108/85.=::sE

Vee= Pin 14
Gnd =Pin 7
Extenders are not present on 9004

9004

9930

9961

Extender Inputs, see note on Page 10

8-INPUT NAND GATE

12/10
Vee= Pin 14
Gnd= Pin 7

9007

3-14

PIN CONFIGl,JRATIONFAIRCHILD CCSL COMPOSITE DATA SHEET (0°C TO 75°C)
HEX INVERTERS

DTpL (6K]

OTpL

TJpL

12/10

--t>-- 240/100*;9.4 --l>--36/94

2/9.4

OTpL (2K]--I>-- 36/94

2/9.4--t>-- 108/85
Vee= Pin 14
Gnd =Pin 7

9016

9937

9935

•Extender Inputs, see note' on Pag1110

PIN CONFIGURATION

AND-OR-INVERT GATES AND EXTENDER
13

1.5/1.51~1

240/100

12/10/>TTpL
6 240/100
412110

240/100

4I

Vee= Pin 14
G.nd =Pin 7• Up to four 9006 Extenders may betied to these terminals

COLL

~EMIT

18/15 /

1.5/1.51

~COLL

~EMIT
Vee= Pin 14
Gnd =Pin 79005 EXTENDABLE
HALF

9005 NONEXTENDABLE
HALF

Vee= Pin 14
Gnd =Pin 7

18/15• Up to four 9006 Extenders may betied to these terminals

9008

9006

DUAL 4-INPUT NANO BUFFERSv--

24/20 {

OTpL

OTpL

TTpL

720/300

2/9.41 ~ 600/235

2/9.51 ~ OPEN COLLECTOR/254

*/9.4

*/9.4

~E

~E

Vee= Pin 14
Gnd =Pin 7
Extender inputs not present on 9009

9009

9944

9932

PIN CONFIGURATION• Extender Inputs, see note on Page 10

R-S FLIP-FLOPS

1 6

S

Co

4/19

10

10

So
108/92

c

4/19

OTpL

0

1 6

I 9 ]36/IDI] 108/9200Co
Vee= Pin 14
Gnd =Pin 7

y5
4/19

9945

9111

3·15

Vee= Pin 14
Gnd =Pin 7

5
4/19

9948

9

FAIRCHILD CCSL COMPOSITE DATA SHEET (0°C TO 75°C)
J.K FLIP-FLOPS
33/27
2

33/27
2

So

So
TTpl

1

6

]2'0noo

T
K

TT pl

0

6

)2'0/100

T

8

0

K

8

Co

Co

?13
33/27

1

Vee= Pin 14
Gnd =Pin 7

Vee= Pin 14
Gnd =Pin 7

113
33/27

9000

9001

DUAL J·K FLIP-FLOPS

4/19

4
12/10 3

4/19
4

6
TI pl

T Ffl

5

7 } 240/100

2/6.3

1 6
OTpl
T FF1

6/19
48/40 14
2/6.3

1
33/27

24/20 2
12/10 132

11

12/10 ( 12
Cg

6/19

15
33/27

Vee= Pin 16
Gnd =Pin 8

1 8

J

llo

2/6.3 1

OTpl
T FF2

So

]31/100

2~31

Vee= Pin 14
Gnd =Pin 7

8

1

DTpL
T FF2

12

) 38/100

K

Co

0 9

K

9020

4/19
610

11

So

2/6.3 11

0

1

4/19
10

9 } 240/100

5

Co

12/30

TIpl

]38/100

K

0 5

10
T FF2

DTpL
T FF1

2/8.3 [ ']31/100

K

6

1

So

3

K

12/10 14So

3

Vee.= Pin 14
Gnd =Pin 7

8/38

9097

9093

4/19
33/27

64
4/19
4

!5
So

1 6

So

TT pl
T

}240/100

Ffl

12/10

0 7
Co

48/40

'?L 33/27

24/20

11 33/27
So

12/10 13FF2

lnuL
6/15 l.o T FF1

2/6.3 23

1 6]•Dl/92
0

K

15
33/27

2/6.3 11J

6/15 1

OTpl
T FF2

2/6.3 12

K

K

I

8

12

3-16

5

4/19
10

So

1 8

,
0

K

Co

9

Vee= Pin 14
Gnd =Pin 7

9094

6

]10Bm

OT pl
T FF2

2/8.3 [) 1081"2

0

1

0

1

11

So
9 }240/100

DTpL
T FF1

5

12/37

Vee= Pin 14
Gnd =Pin 7

9022

[ '

4/19
10

Co
Vee= Pin 16
Gnd =Pin 8

2~3

I 10

TT pl

12/10 12

2/6.3

So

8/38

9099

] •08/92

FAIRCHILD CCSL COMPOSITE DATA SHEET (0°C TO 75°C)
MONOSTABLE MULTIVIBRATORSTO Yee1 6SS
Vee= Pin 14
Gnd =Pin 7

l

30/87

0 1

Vee= Pin 14
Gnd =Pin 7

Vee= Pin 14
Gnd =Pin 7
The DTµL 9941 is NOT
recommended for new
designs; use the 9601.

9601

The DTµL 9951 is NOT
recommended for new
designs; use the 9601.

9951

9941

NOTE: The maximum input fall time to trigger is: 25 ns
for a 1.0 volt swing; 50 ns for a 2.0 volt swing;
100 ns for a 4.0 volt swing.
• Extender Inputs, see note on Page 10

MEDIUM SCALE INTEGRATIONSHIFT REGISTERS AND STORAGE ELEMENTS
12/10

24/20
12/10
28;23
9

--

12/10

~

4

5

6

-18/15· - 12/10

18/15

18/15 _l,.___..........

13

11

12

Os

Do

Di 07

14

36/30 ~....-"'-"~'

7

72/60
72/60

12/10

24/20

24/20

11

12/10

72/60

72/SC
'---y---'

12/10

72/60

72/60

Vee= Pin 16
Gnd =Pin 8

Vee= Pin 24
Gnd =Pin 12

Vee= Pin 16
Gnd =Pin 8

9300

9308

9328

4 BIT UNIVERSAL REGISTER

DUAL 4 BIT LATCH

DUAL 8 BIT SHIFT REGISTERCOUNTERS
8/6.7

8/6.7

9

11

72,60

5

0

'-----y-----'

3

4

5

6

Po

P1

P2

P3

Cu 9310 UP DECADE COUNTER TC
Cp Mft3

8/6.7
24 /20 ,--------A--.-.

24 /20 ,.---A---.,

24/20 ~
23 22 21
20
9

6tJ

01

Oz

12/10
15 72/60

9306

P3

P2

lltJ0,0203

1
14
13 12 11
12/10 ' - - y - - '12/10 ' - - y - - '

72/60

14

13

2

11

72/60

Vee= Pin 16
Gnd =Pin 8

Vee= Pin 16
Gnd =Pin 8

UP/DOWN DECADE COUNTER

P1

03

72;60

Vee= Pin 24
Gnd =Pin 12

Po

Cu 9316111' BINARY CGUllTER TC

9310
UP DECADE COUNTER

3-17

9316
UP BINARY COUNTER

72/60

FAIRCHILD CCSL COMPOSITE DATA SHEET (0°C TO 75°C)
MEDIUM SCALE INTEGRATION (Cont'd.)
COMBINATIONAL LOGIC,.---->--...

--->------.
23

12/10
,...-A--.
15 14 1 2
Ao At A2

48/40

12/10

12/10

22

20

21

Ag A1 A2 A3
93111/1& DECODER
0 I 2 3 4 5 & 7 8 9 10 11 12 13 14 15A393011/10 OECOOER

216/90120/100

120/1005
11
168/70 216/90
1&8/70240/100
240/100

Vee= Pin 16
Gnd =Pin 8

Vee= Pin 24
Gnd= Pin 12

Vee= Pin 16
Gnd =Pin 8

9301
1 OF 10 DECODER

9311
1OF16 DECODER

9304
DUAL FULL ADDER

12/10
12
Ag At A2 A3 LT RBI

9

B

So'oa •11 •21 131: •ob •1b •n l3b9309 OUAL 4 BIT MULTIPLEXER

12/10 3I

21&/90240/100

216/9023456797

12/10 139307 7 SEGMENT DECODER
RB01bcdefg

10

11

12/10

12/10

,..--->---..

,.---->--...

10 11. 12.. 13 14 15 16 179312 8 Ill' MULTIPlEXER

1
240/100

Vee= Pin 16
Gnd =Pin 8

9307
BCD TO 7 SEGMENT DECODER

9309
DUAL 4 BIT MULTIPLEXER

11 10

Ao Bo A1 B1 A2 B2 A3 B3COMPARATOR I

9312

Q

14

9 B

1 8

5 4

Ao Bo Ai 81 A2 82 A3 83
4/20

ST

COMPARATOR II

A=8

Q

15

A=B

2
3
38/40 80/50

38/40 80/50
Vee= Pin 24
Gnd =Pin 12

4510
DUAL 4 BIT COMPARATOR

3-18

15

8 BIT MULTIPLEXER

4/20

23 22 21 20 19 1B 17 16

ST

14 .

216/90 240/100

4/20

4/20

z

Vee= Pin 16
Gnd =Pin 8

Vee= Pin 16
Gnd =Pin 8

13

z

I

FAIRCHILD CCSL COMPoSITE PATA SHEET·co c TO 75°C)
0

MEMORIES
40/20

20/10

1o 11 12 13w

320/1020/9.4

20/9.4

26.
1 Xo
2

Wo

12/10

~

X1

10/Hl 3 X2
80/69

4

X3

13

Yo

12

Yt

11

Y2

10

Y3

15!14 1 1 1 1
E ~A3A2A1Ao. 9033 MEMORY

9035 MEMORY

20/10

S1

So

OPEN COLLECTOR/63

6
Vee= Pin 16
Gnd =Pin 8~
OPEN COLUCTOR/62

NOTE: The 9034 is programmed on a custom basis. Con·tact your Fairchild salesman for more information.

Vee=Pin28
Gnd= Pin 99034
32 Word by 8 Bit Read Only Memory

64 Bit Read/Write Memory Cell'-----r--'
OPEN COLLECTOR/125
Vee= Pin 14
Gnd =Pin 7

9033
16 Bit Scratch Pad Memory

9035

INTERFACE ELEMENTS

~·I~

3

~57/9.4

1300~57/9411•1110~
2/10{ 10
.
13

~n~

.

Vee= Pin 14
Gnd =Pin 7+BV=Pin8

9620
Dual. Differential Line Receiver

9621
Dual Line Driver•is:---,
2;s{:l:::QJ-l·1·~~

Vee= Pin 14
Voe= Pin 7
Gnd =Pin 1
TAP= Pin 13

13 57/94

Vee= Pin 8
Vee= Pin 7
Gnd-Pln 14$3-Plnl
If S3·= Vee, then output is normallyhigh with Inputs open
If $3 = Gnd 7, then output is normally
low with inputs open

12

Outputs are extremely low impedance to drive longlines. Back matching resistors for 130 0 line areprovided.
Vee= Pin 14
Gnd =Pin 7+BV=Pin 8

Inputs are dlff•rentlal, one pair attenuated, onepair nonattanuated.

2/9.4

r=~t>-:::::19622
Dual Differential Line Receiver(CCSL Threshhold Inputs)llOS LEVELS-14>-'L J.t2/18

r

-4>-L

1

Gnd =Pin 1
Voe= Pin 7
Vee= Pin 14

2/S{Il:D-1-

9625
MOS to CCSL Converter

9624
CCSL to MOS Converter

HIGK LEVEL __Joo,,,,___OPEN
LOGIC - V - -COLLECTOR/56
The 9109 converts from HLLDTµl levels(thres.hold - 7.5 Volts) to CCSL levels.

9109
Hex Converter

Z/B 8 _____,.,,___ HIGH LEVEL·~LOGICThe 9112 converts from CCSL levels to
HLLOTµL levels. (Vour - 12 to 20 Volts
depending on Vee)

9112
Hex Converter

3-19-t--1::~-~-+--6

9 -+---Do,-+-- e
11

10

13

12

9112,9109

PIN CONFIGURATIONFAIRCHILD CCSL COMPOSITE DATA SHEET (0°C TO 75°C)
EXTENDER INPUTS
75°C. A leakage of 1.0 µA corresponds to an input high level loadfactor of 0.2. The normalizing factor given in the introduction canalways be used to determine the load factor of a diode. In order tomaintain CCSL levels the diode should have <0.65 volt drop at 1.5. mAof current at 25 °C.

Extender inputs require DTµL 9933 or external silicon. diodes in order
to be used. Use of extender pins without' diodes is not recommended.
The low level load factor is determined by the resistor already included in the device. The high level load factor is usually negligible
as most discrete silicon diodes have leakages of less than 1.0 µA at

APPENDIX
This maximum allowed input low current is normalized to give the lowlevel input load factor.

The purpose of this appendix is to cover in more detail the testing of
CCSL products and thereby show how the logic levels are guaranteed.
The testing must guarantee the input loading in both the high and low
states and also must guarantee the output drive capability in both thehigh and low .states. Both input and output characteristics must be
guaranteed at worst case Vee and input conditions and over the temperature range.

The output must be tested to insure that it meets the required high andlow level drive factors, while maintaining the required noise immunity.
To test the low level output drive factor, all inputs are maintained at
V1H, the minimum high level input voltage. The Vee is maintained at
4.75 Volts and current is forced into the output. This current, IOL, isrelated to the output low level drive factor by the normalizing factors
for 4.75 Volts. The output voltage is measured to 'insure that it is lessthan VOL.

The examples given are for NANO gates. The application of the ideas
to more complex devices is very much the same, except that manipulation of the inputs to achieve a required condition is more complex.
Testing is always done with the worst case set of inputs.
First, consider the testing of the inputs to guarantee the input loadfactors. The high state input load current is tested by grounding theother inputs of the gate under test and measuring the input current
with a voltage much higher than VoH· Maximum Yee is used as thishas been found to be the worst case for TTµL circuits. The maximum
allowed input high current is normalized to give the high level input
load factor.

loL TEST CIRCUIT=The test is repeated with Vee 5.25 Volts and the IOL determined by
the 5.25 Volts normalizing factor.

Vcc=5.25Y.....~
fr
The output is then tested for the output high level drive factor. The
maximum low level input voltage is applied to one input at a time withthe other inputs held high. Current is then pulled out of the output.
This current, loH• is related by· normalizing factors to the output highlevel drive factor. The output voltage is measured to insure that it
exceeds VoH·

It TEST CIRCUIT

To test the low level input load factor, a voltage equal to V0 L is applied
to one input and the current flowing out of the input is measured. The
other inputs are tied to a high voltage. Maximum Yee is used.

b·~r.

~

Each input is tested separately
IOH TEST CIRCUITIF TEST CIRCUIT

3-20

9300
'MSI 4-BIT SHIFT REGISTERA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRlmON- The 9300 Four Bit Shift Register is a high speed multi-functionalsequentiai logic block which is useful in a wide variety of register and counter applications.
As a register it may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial,and parallel-parallel data transfers. The circuit uses TTµL for high speed and high fanout capability, and is compatible with all dev.ices in the CCSL group of digital integrated circuits.

PHYSICAL DIMENSIONS• 15 MHz shift frequency• Synchronous parallel entry• J, i inputs to first stageLI• A5ynchronous common reset

.023
MAX.

• Typical power dissipation of 300 mW• The input/output characteristic$ provide easy interfacing with Fairchild DTµL,NOTES:

LPDTµL, and TTµL families (CCSL).

l. Leads ere intended for insertion in hole rows on.300" centers. They are p~rposely shipped with''positive" (,375) misalignment to facilitate insertion.
2. Board·drilling dimensions should equal yourpractice for a conventional .020 l1nch diameter lead.

• All ceramic "HERMETIC" 16 pin Dual In-Line package.
• Input diode clamping

Figure 1

ABSOLUTE MAXIMUM RATINGS (above Which the useful life may be impaired)

LOGIC SYMBOLStorage Temperature-65°Cto +150°C

Temperature (Ambient) Under Bias

-55°C to + 125°C

Vee Pin Potential to Ground Pin-0.5Vto +7V

Voltage Applied to Outputs for high output state-0.5 Vto +Vee value

Input Voltage (D.C.)-0.5 V to +5.5 V

9
2
10
3

J PE Po

Specify U6B9300XXX for 16 pin Dual In-Line pack<1ge where XXX is 51X for the -55°C to +125°C temperature range, or 59X for the 0°C to + 75°C temperature range.

5

6

7

Pl

P2

P3

Cp

9300 SR

K MR

Qo

Q1

Q2

Q3 Q3

15

14

13

12

1

ORDER INFORMATION

4

11

Vee= PIN 16
GND =PIN 8

Figure 2

F=AIRCl-tll...C
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-21

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MEDIUM SCALE INTEGRATION • 9300
FUNCTIONAL DESCRIPTION
The logic symbol of Figure 2 provides an indication of the functional characteristics of the 9300 four bit shift register. Several special logical features of the9300 design which provide a high degree of general usefulness are described below:
1. A JK input 'is provided to the first flip flop in the register. This type of input is the same as the more common JK input except that the low voltage
level activates the K input. This provides the greater power of the JK type input for more general applications and at the same time the simple D type
input that is most appropriate for a shift register can be easily obtained by simply tying the two inputs together.
2. There is no restriction on the activity of the J or K inputs for logical operation - except for the set up and release time requirements.
3. Parallel inputs for all four stages are provided. These will determine the next condition of the shift register synchronous with the clock input, whenever
the Parallel Enable input is low. With the Parallel Enable input low the element appears as four common clocked D flip flops. When the Parallel Enable
is high, or not connected, the shift register performs a one bit shift for each clock input. In both cases the next state of the flip flops occurs after the
low to high transition of the clock input.
4. An internal clock buffer provides both reduced clock input loading, and the ability to gate the clock with only a single NAND gate.
5. The active high output is provided for all four stages and an active low output is provi~ed for the last stage.
6. A master asynchronous clear input allows the setting to zero of all stages, independent of the condition of any other inputs.

TABLE I - TRUTH TABLEFOR SERIAL ENTRY(PE = HIGH, MR = HIGH, (n + 1) indicatesstate after next clock)K

Qo attn+ I

L

L

L

L

H

Q0 at t0 (no change)

H

L

Q0 at t (toggles)

H

H

H

TABLE 11 -0

TABLE Ill
ELECTRICAL CHARACTERISTICS (TA= -55°C to +125°C, Vee= 5.0 V ± 10%)LOADING RULES (1 U.L.

= 1 TTµL Gate Input Load)

INPUTSLOADING

J, K, MR, P0 , Pp P2 & P3

1 U.L.

PE

2.3 U.L.

Cp

4 U.L.

OUTPUTSFANOUT

Qo, QI' Qz. Qi & QJ

6 U.L.

(Part #U6B930051X)
LIMITSUNITSCONDITIONS & COMMENTS

Volts

Vee = 4.5 V, 10 H = -0.36 mA

Volts

Vee = 5.5 V, IOL = 9.6 mA
Vee = 4.5 V, 10 L = 7.44 mA

Volts

Guaranteed input highthreshold for all inputs

0.8

Volts

Guaranteed input low
threshold for all inputs

-1.6
-1.24

mA
mA

Vee= 5.5 V
VF= 0.4
Vee= 4.5V

60µA

Vee = 5.5 V, VR = 4.5 V+75°C
MIN. MAX.

UNITSCONDITIONS

2.4

Volts

Vee= 4.75 V, 10 H = -0.36 mA

Volts

Vee = 5.25 V, 10 L = 9.6 mA

Volts

V,ce = 4.75 V, 10 L = 8.5 mA
Guaranteed input highthreshold for all inputs

SYMBOLCHARACTERISTICS-55°C
MIN. MAX.

+25°C
MIN. TYP. MAX.

+125°C
MIN. MAX.

VoH

Output High Voltage

2.2

2.4

2.4

VOL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.8

Input Load Current*

-1.6
-1.24

IF

0.4
2.0

J, K, MR, P0 , Pp P2 & P3
IR

2.7
0.2

0.4

0.4
1.4

1.7
0.9
-1.10 -1.6
-0.97 -1.24

Input Leakage Current*

15

60

v

J, K, MR, P0 , Pp P2 & P3
TABLE IV
ELECTRICAL CHARACTERISTICS (TA= 0°C to +75°C, Vee= 5.0 V ±5%}(Part #U6B930059X)
LIMITS

SYMBOLCHARACTERISTICS

0°C
MIN. MAX.

MIN.

2.4

2.4

+25°C
TYP. MAX.

VoH

Output High Voltage

VoL

Output Low Voltage

V1H

Input High Voltage

VIL

Input Low Voltage

0.85

0.85

0.85

Volts

Guaranteed input low
threshold for all inputs

Input Load Current*

-1.6
-1.41

-1.0 -1.6-0.9 -1.41

-1.6
-1.41

mA
mA

Vee= 5.25 V
Vee= 4.75 V, VF= 0.45 V

60µA

Vee= 5.25 V, VR = 4.5 V

IFJ, K, MR, P0 , Pp P2 & P3
IR

0.45

3.0
0.2

1.9

1.6

1.8

Input Leakage Current*

15

J, K MR, P0 , Pp P2 & P3

*For CP and PE input currents, use load factors in Table II

3-22

0.45

0.45

60

FAIRCHILD ·MEDIUM SCALE INTEGRATION .• 9300
TYPICAL INPUT AND OUTPUT CHARACTERISTICS

Vee
EQUIVALENT CIRCUITINPUTSINPUT CURRENT VERSUS INPUT VOLTAGE

PE

CP

Vee· 5.ov
TA~ 25°C-1.0--0.4 1---+--+--+--+--#-l---+---l

7_

~

~

...Y

~ -2.0!-3.0 I v/~

~i.4.0';;;-4.0
-

%

-6.0

-1.0

VIN - INPUT VOLTAGE - VOLTS,___.._.....L'.1~17,__+--+--+--+-1----<

v

±

-6.0
-1.0

3.0

2.0

1.0

Vee
OUTPUTSEQUIVALENT CIRCUITOUTPUT CURRENT VERSUS OUTPUT VOLTAGE(Qo, Q" Q2, Q3 AND Q3)

LOW STATEHIGH STATE

50

40

I

.L'.l

_L]

i

_L1

~-IS

v

!5

I

9
5

JZ:

..:..-10

1

5 20

IL

0

's-20

_L1

E

2

10

0

7
0

-25

0.2

0.4

::2J

-5.0

-I

50

~

lL:l

vcc 5.ovTA• 25'e

lLJ

0.6

0.8

1.0

-50

1.2

-1.0

7

v

1.0

2.0

3.0

VoUT- OUTPUT VOLTAGE - VOLTS

Vour - OUTPUT VOLTAGE - VOLTS

3-23

1.0

2.0

V1N- INPUTVOLTAGE-VOLTS

VIN - INPUT VOlTAGE -VOLTS

Vee· 5.ov
TA• 25'e)7-5.0 1-7''+--t--+--t-+--t--t---t-5.0-2.0 ~~~-+-~~-~~~
-1.0
1.0
3.0
2.0

1

[ : t---+--+---+----+-1>-+---+-t--ti-1.6 1--t+--+--+--+--+-l---+---l-1.0 t---+--+---+----+--<>+---+--+----<

4.0

5.0

3.0

FAIRCHILD MEDIUM SCALE INTEGRATION • 9300
)WITCHING CHARACTERISTICS (TA = 25°C)(Parts #UGB930051X and UGB930059X)
TYP.

MAX.

UNITS

CONDITIONS & COMMENTS

20
25

35
45

ns
ns

Vee = 5.0 V, CL = 15 pf(See Fig. 5 & Ga)

25

MHz

Vee= 5.0V, CL= 15 pf(See Fig. 5 & Ge)

35

15

35

17
lG

ns
ns

SYMBOLCHARACTERISTIC

MIN.

tpd+
tpdf sr

Turn Off Delay
Turn On Delay
Shift Right
Frequency

15

CPpw
t,

Clock Pulse Width
Set-up Timetrt,(PE)

Release. Time
Set-up Time for PEtr(PE)

Release Time for PE

tpd-(MR)tree< MR}

Reset Time for MR
Recovery Time for MR

MRpw

Min Reset Pulse Width

0

ns

10

ns
ns

2G

45

25
35

Vee= 5.0V
CL= 15 pf(See Figs. Ga & Gb)

ns

20
15

ns
ns

>ET-UP TIME: t, is defined as the minimum time required for the logic level to be present at the logic input prior to the clock transition from low to highin order for the flip-flop(s) to respond.
~ELEASE TIME: tr is defined as the maximum time allowed for the logic level to be present at the logic input prior to the clock transition from low to highin order for the flip-flop(s) not to respond.
~ECOVERY TIME FOR MR: trec(MR)is defined as the minimum time required between the end of the reset pulse and the clock transition from low to highin order for the flip-flop(s) to respond to the clock.
Figure 3
PROPAGATION DELAY CLOCK TO Qi OR Qi
OUTPUT VS TEMPERATURE
68

See Fig. 5 and 6a

~~

20

/

1

lL

See Fig. 5 and 6a

rt

52

~'!L

~'
;;-'

N

A'

~

~.>i

b.

1~PI~

N

60

_L

60

28

Figure 4
PROPAGATION DELAY CLOCK TO Qi OR Q1
OUTPUT VS TEMPERATURE

vt.~'-A~v

20'\'12112·55 ·35 ·15 +5

25

45

65

85 IC15 125-55 ·35 ·15

5 25 45 65 85 105 125
TEMPERATURE °C

TEMPERATURE °C

Vcc=+SV

2k

9

4

5

6

7 16

- -2- - o J
PE Po P1 P2 P3
10Q3- - - - - -3- - o CP
9300 SRK MR Qo Q1 Q2 Q3 GND

PULSE
GEN

l
Pulse Generator Output
1. Switching Time (!pd+ & tpd-) Tests
Rise fime < 15 ns
Fall Time < 15 ns
Amplitude ::::: 4 V
Freq. = 2 MHz ± 5% at 50% duty cycle
2. Shift Right Frequency Test
Rise Time < 15 ns
Fall Time
15 ns
Amplitude::::: 4 V
Freq. = 15 MHz with pulse width
adjustment so that V1N has
duty cycle of approx. 50%.

11

15 14 13 12 8

CL includes
probe and jig

capacitance<

Figure 5 -

Vour

Vour

Vour

Your

Vour

SWITCHING TIME & SHIFT RIGHT FREQUENCY TEST CIRCUIT
3-24

FArRCHILD MEDIUM SCALE INTEGRATION ·•: 9300
Fig. &b

Fig. &a

OATAA-.
.
SERIAL-.-------.-.------1.5V

p~Af~-------------- 1.5V

CP\..________,rFig. 6c.,.
Your(PIN 12 OR 111

Your Frequency

Figure 6 -='h X V1N Frequency

SWITCHING TIME & SHIFT RIGHT FREQUENCY WAVEFOR.MS

APPLICATIONS - The 9300 has been designed to be useful in a wide variety of applications. The multifunctional capability of the Fairchild 9300 is illustrated by the applications shown below.
·
LS/RS SELECTRS DATA IN

l

J PE

r---1 Cp
K MRll

Po P1 P2
9300 SRQo Q1 Q2

P3

J PE
~

Cp
K MR

Q3 Q3

ll

Po P1 P2
9300 SR

P3

Qo

Q3 Q3

Q1

11

LS DATA OUT
CLOCK
MASTER RESETLS DATA IN

Q2

p-

11

RS DATA OUT

Figure 7 - EIGHT BIT LEFT /RIGHT SHIFT REGISTER
This register shifts Left or Right on each shift clock, depending upon the condition of the LS/RS SELECT
input. If this input is high, Right Shift occurs and if low, Left Shift occurs.
~----

7 PARALLEL DATA INPUTS - - - - - - - .

GND
INPUT READ

l
Vee-

J PE

.--- Cp

Vcc-1f--o K MR

Po P1 P2
9300 SR

P3

Qo

Q3 Q3

Q1

Q2

I

p-

J PE

..--- Cp
K MR

V~c

Jc

REQUESTPo P1 P2
9300 SR

P3

Qo

Q3 Q3

Q1

Q2

I

SERIALOUTPUT

CLOCK_).007
Figure 8 - SEVEN BIT PARALLEL TO SERIAL CONVERTERThis parallel to serial converter uses a marker bit, to count the data bits shifted out, so that a parallel load
enable is generated to load the next parallel word for.conversion at the correct time.

3-25

FAIRCHILD MEDIUM SCALE INTEGRATION • 9300

SELECTOR SWITCH SHOWN IN N=l5 POSITION
2

3

4

5

6

7

8

9

10 11 12 13 14 15

JPE
INPUT - - - - - - - 1 C p
K MR

Po P1 P2
9300 SR
Qo 01 Q2

P3
Q3 03

MASTER _ _ _ _ _ _ __.
RESETFigure 9 -DIVIDE BY N COUNTER FOR N = 2 to 15

This counter produces an output pulse for every N. input pulses, where the number N is determined by thesetting of the slide selector switch as shown or by logic inputs to the parallel data lines from an externalsource.

MSD
SELECTORSWITCHLSD
SELECTORSWITCH.

-:-

123456789

123456789. - - - - - - - - 1 J PE Po
Cp
K MR

P1 P2
9300 SRQo Q1 Q2~------1 J

P3~ 9002

Q3 Q3

Po P1 P2
9300 SR

P3

Cp

PE

K MR

Qo

01

Q3 Q3

Q2

t9004

-L~----k~~~
INPUT

!

9007

COUNT SEQUENCEOUTPUT
fin+ N

0011
0001
0000
1000
1 1 0.0
0110
1011
1101
1110
0111

This circuit divides by any number "N" from 1 to 100. The selected N is one greater than is shown on theslide switches. As an example the switches are showing 56, therefore the circuit will divide by 57 withthis setting.

9
8
7
6
.5

4
3
2

1
0

Figure 10 ~ TWO DECADE PROGRAMMABLE DIVIDER

3·26

9301
MSI ONE-OF-TEN DECODERA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTThe 9301 is a multipurpose decoder designed to accept four
GENERAL DESCRIPTION inputs and provide 10 mutually exclusive outputs. The circuit uses TTµL for high speed andhigh fan out capability, and is compatible with all members of the CCSL group of digital
integrated circuits.

PHYSICAL DIMENSIONS• Multi·function capability• Mutually exclusive outputs• Guaranteed fanout of 10 TTµL loads over the full temperature range and supply
voltage ranges• High capacitive drive capabilityt=• Demultiplexing capability

.023
MAX.

• Typical power dissipation of 145 mW• The input/011tput characteristics provide easy interfacing with Fairchild DTµL,
LPDTµL and TTµL families (CCSL).

llOTU:

1. L••di •re lntendU 1or lnHrtion In hole row• on• All ceramic "HERMmC" l&·pin Dual ln·Line• package.300" ctAttrt. they ere purposely· shipped witb

"positive" (.375) mln1i1nment to t1ciut1te insertion.

• Input clamp.diodes limit high speed line termination effects

2. B01rd-drillin1 dimensions should eq111I yourpractice for 1 convention1I .020 Unch di1meter. le1d.

Fig. 1
ABSOLUTE MAXIMUM RATINGS. (above which the useful life may be impaired)
Storage Temperature-65°C to +150°C

Temperature (Ambient) Under Bias-ss•c to +125°C

Vee Pin Potential to Ground Pin-0.5Vto +7V

Voltage Applied to Outputs for high output state-0.5 Vto +Vee value

Input Voltage (D.C.)-0.5 V to +5.5 V

LOGIC SYMBOL

15

14

I

2

ORDER INFORMATION
Specify U6B9301XXX for 16 pin Dual in-Line package where XXX is 51X for the -55°C to +125°C temperature range, or 59X for the 0°C to+ 75°C temperature range.

131211109 3 45 6 7
Vcc•PIN16

GNO•PIN8

Fig. 2•Fairchild patent pending.

F=A.IRCHILCJSEMICCJNDUCTCJR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011, TWX: 910-379-6435

3-27'A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MEDIUM SCALE INTEGRATION • 9301
FUNCTIONAL DESCRIPTION
The 9301 Decoder accepts four active high BCD inputs and provides ten mutually exclusive active low outputs, as shown by Figure 2. The active low outputs
facilitate memory addressing when inverting drivers are used between decoder and memory elements such as the 9033.
The logic design of the 9301 ensures that all outputs are high when binary codes greater than nine are applied to the inputs.
The most significant A3 input produces a useful inhibit function when the 9301 is used as a 1 out of 8 decoder. This is illustrated in the 1 out of 32 decoder
shown in Figure 9.
The Truth Table and Loading Rules for the 9301 are shown in Table I and Table II.

TABLE I -TRUTH TABLE

TABLE II LOADING RULES (1 U.L. :A0 A1 Az Al

0 1 2 3 4 5 6 7 8 9

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
L
L
L
L.
L
L
H
H
H
H
H
H
H
H

H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H

TTµL Gate Input Load)

INPUTSLOADING
1 U.L.

OUTPUTSFANOUT0, l, 2, 3, 4, 5, 6, 7, 8, & 9

10 U.L.

H = High Voltage Level
L = Low Voltage Level

TABLE Ill -ELECTRICAL CHARACTERISTICS (TA= -55°C to +125°C, Vee = 5.0 V ± 10%) (Part #U6B930151X)
SYMBOLCHARACTERISTICS-55°C
MIN. MAX.

LIMITS+25°C
MIN. TYP. MAX.

+125°C
MIN. MAX.

UNITS

VoH

Output High Voltage

2.4

2.4

2.4

Volts

Vee= 4.5 V, 10 H = -0.6 mA

VOL

Output Low Voltage

Volts

Vee= 4.5 V, Im = 12.4 mA
Vee = 5.5 V, loL = 16.0 mA

VIH

Input High Voltage

Volts

Guaranteed input highthreshold for all inputs

VIL

Input Low Voltage

0.8

0.9

0.8

Volts

Guaranteed input low
threshold for all inputs

IF

Input Load Current

-1.6
-1.24

-1.10 -1.6
-0.97 -1.24

-1.6
-1.24

mA
mA

Vee=5.5V
Vee= 4.5 V

IR

Input Leakage Current

15

60

60

µA

Vee= 5.5V, VR = 4.5V

tpd+
tpd-

Turn Off Delay Input to Output
Turn On Delay lnputto Output

23
20

35
30

ns
ns

Vee= 5.0V
CL= 15 pf
See Fig. 8

2.7
0.2

0.4
2.0

0.4

1.7

3-28

0.4
1.4

CONDITIONSJ _l VF - 0.4 V

FAIRCHILD MEDIUM SCALE INTEGRATION • 9301
TABLE IV-

ELECTRICAL CHARACTERISTICS (TA:::; 0°C to +75°C, Vee= 5.0 v ±5%)(Part #U6B930159X)

SYMBOLCHARACTERISTICSo•cMIN. MAX.

LIMITS+25°c
MIN. TYP. MAX.

VoH
Vol

Output High Voltage
Output Low Voltage

2.4

2.4

VIH

Input High Voltage

1.9

VIL

Input Low Voltage

0.85

0.85

0.85

Volts

IF

Input Load Current

-1.6
-1.41

!it

Input Leakage Current
Turn Off Delay Input to Output
Turn-U-n ue1ay-1.0 -1.6-0.9 -1.41
15
60
35
23
30

-1.6
-1.41
6lf

mA
mA
µA
ns
ns

!e.d+
1i>d-

0.45

3.0
0.2

+75°c
MIN. MAX.

UNITS

2.4

Volts
Volts

0.45

0.45

1.8

1.6

-w-

TYPICAL INPUT AND OUTPUT CHARACTERISTICS

o.5~e=5.25VJ

Vee= 4.75V l VF= 0.45V
Yee = -s:25Y. VR = T.5V
Yes;,_= 5.0 V
CL -15 pF
See Fig. 8

Fig. 7TYPICAL TURN OFF DELAY
VERSUS TEMP-ERATURE

Fig. 6TYPICAL TURN ON DELAY
VERSUS TEMPERATURE

INPUT CURRENT VERSUSINPUT VOLTAGE

EQUIVALENT CIRCUIT

Vee = 4.75 V, kH = -0.6 mA
Vee= 4.75 V, loL = 14.1 mA~ = 5.25 V, loL = 16.0 mA
Guaranteed input highthreshold for all inputs
Guaranteed input low
threshold for all iflJl_uts

SWITCHING PERFORMANCE

Fig. 3
INPUTS

Volts

CONDITIONS

Vcc· 5.5V
TA• 25°C -+-+-+______- t

vcc

I/

~t-t-+--+--+--+-+-t-t-+-+---i~t-t-+--+--+--+-+-t-t-+-+---i

4i -0.5 1--if--i--t--tl,..'j-+-+--+--+--+---i

1-1.5 ~~z.: -2.5 t-Hf--i--t--+-+-+--+--+--+---i• 16 ..........-+-+--+--+-+-i--+-+-+--1 + 16 t-t-+--+--+--+-+-t-t-+-+---i
_11.
_11.

+-+-

B.O ,...._..-+-+--+--+-+-see Fig. 5
Vee· 5.ov
t-t-+--+--+--+-+-CL •
+--t-

15;

0

1;0
2.0
l.O
VIN - INPUT VOLTAGE - VOi.Tl

4.0-55 -35 -15

5

25

8.0

See Fig. 5 --t-+""1
t-t-+--+--+--+-+-vcc • 5.ov+-+---<
CL• 15 pf-55 -35 -15

45 65 Bl 105 125

25

45

65

BS 105 125

OUTPUT CURRENT VERSUSOUTPUT VOLTAGEOUTPUT LOW

Fig. 4OUTPUTS

1-Tcc~.751

EQUIVALENT CIRCUIT

Vcc•5V

TA •2l"COUTPUT LOW

5TA· AMBIENTTEMP£RAJURE ·°C

TA - AMBIENTJEMP£RATURE - °C

z

JO

--

2kCl

I

J

.L

-10
-1.0

OUTPUT HIGH

-0.5
0
0.5
1.0
VouT" OUTPUT VOLTAGE - VOLTS

v~c

-l.ov
-5.0 r-TA·25·c
<

e

-10

.

s
s

1.5

PULSE GEN CHARACTERISTICS
FREQ • 1 MHz
PULSE WIDTH • 100 ns
tr= tf s 15ns
AMPLITUDE • 4 V

-20

s -25
-JO

IZJ

131211109* INCLUDES ALL PROBE AND JIG CAPACITANCE

45 67

3
PIN 16 =5V

I

';'

.2

v

~

iB -15

2

14

Ao A1
9301

OUTPUT CURRENT VERSUSOUTPUT VOLTAGEOUTPUT HIGH

Fig. 5

Yee

15

1-1

j_
I

VouT

-35

-1.0

0

1.0

3.0

5.0

7.0

9.0

Fig. 8 -. Your· OUTPUI VOLTAGE - VOi.iS

3-29

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

FAIRCHILD MEDIUM SCALE INTEGRATION • 9301
APPLICATIONS - The 9301 decoder may be used for BCD to Decimal or 3 bit binary to octal conversion as well as many other applications. The
general purpose nature of the 9301 is indicated by its use in the following applications.

----GND. . . . . - - - - - STROBE
1110 DECODER
9301
0123456789

Ao A1 A2 A3
1/10 DECODER
9301
0123456789

Ao A1 A2 A3
l/10 DECODER
9301
0123456789

0123456789

Ao A1 A2 A3
1/10 DECODER
9301
0123456789

01234567

8 9 101112131415

16

24 26 28 30

Fig. 9 -Ao A1 A2 A3
1/10 DECODER
9301

18 20 22

ONE·OUT·Of·THIRTY·TWO DECODINGBCD CODEOUTPUT SELECTION

l

A1
A2
A3
Ao
1110 DECODER
9301

Ao
A1
A2
A3
1110 DECODER
9301
0 123456789
i1 c) c QC I) C) ci1 c) 9

0 I .2 3 4 5 6 7 8 9) ci1 c11';J l 11;J\11 1)110123456789

I 0 1112 13 1415 16 17 18 19

DECIMAL
DIGIT
0
1
2
3
4
5
6
7
8
9

8421

BCD CODEEXCESS
5421
3

4221

0,18
l, 19
2
3
4
5
6
7
8,10
9, 11

0,18
1,19
2
3
4
8,10
9, 11
12
13
14

0,18
1,19
2
3
6
9, 11
14
15
16
17

OUTPUTS
Decode any BCD code using two 9301 elements. Any 4 bit BCD code may be decodedby selecting outputs as shown in the table.
Fig.10- DECODE ANY BCD CODE

3-30

3
4
5
6
7
8,10
9, 11
12
13
14

FAIRCHILD MEDIUM SCALE INTEGRATION • 9301

ADDRESS DATAADDRESS OUTPUT
LINE
A B

~

c

0 0 0
I 0 0
0 I 0
I I 0
0 0 I
I 0 I
0 I I
I I I

Ao A1 A2 A3
I/ 10 DECODER
9301
0123456789

0
I

2
3
4
5
6
7

Data may be routed from a source to any of 8 outputs by addressing that output.
All non-addressed outputs remain high.
Complements of outputs 0 and 1 are available at outputs 8 and 9 respectively.

Fig.11- DIGITAL DEMULTIPLEXER

INPUT

A

B

c

D

Ao

A1

A2

A3

9301

1flo DECODER

3456789

1/2

l/2

9004

9004

Each output of the 9301 may be considered a minterm of the input code.
Several sums of minterms may be generated economically using discrete
IC gates and one 9301 decoder.

A
B _ __,'--.... Q =A BCD+ ABCD+ ABCD + ABCD

c ______,'-------l~P =AB CD+ ABCD+ ABCD+ ABCDOUTPUT P

Fig.12- MINTERM GENERATOR

3-31

9304
MSI DUAL FULL ADDERA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRIPTION The 9304 consists of two independent, high speed, binary
full adders. The adders are useful in a wide variety of applications including multiple bit
parallel add/serial carry addition, parity generation and checking, code conversion, andmajority gating. The circuit uses TTµL for high speed, high fanout operation and is compatible with all members of the CCSL group of digital integrated circuits.

PHYSICAL DIMENSIONS

.1001
MIN.

:c

• Multi-function capability• 8ns carry propagation delay

.110
.090

• Complementary inputs and outputs available

L• Typical power dissipation of 150 mW

I

.023
MAX.

• The input/output characteristics provide easy interfacing with Fairchild DTµL,
LPDTµL and TTµL families (CCSL).
• All ceramic "HERMETIC" 16-pin Dual In-Line'" package

NOTES'
I. leads ue intended for insertion in hole rows on.300" cent-ers. They are purposely shipped with"positive" (.375) misalignment to lecilitete insertion.
2. Boerd·drillin& dimensions should equal yourpractice for a conventional .020 hnch diameter lead.

• Input clamp diodes limit high speed termination effects

Fig. 1IBSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature-ss•c to + 1so 0 c

Temperature (Ambient) Under Bias-ss•c to +125•c

Vee Pin Potential to Ground Pin-0.5Vto+7V

Voltage Applied to Outputs for high output state

LOGIC SYMBOL-0.5 V to +Vee value

Input Voltage (D.C.)-0.5 V to +5.5 V

IRDER INFORMATION
pecify UGB9304XXX for 16 pin Dual In-Line package where XXX is 51X for the -55°C to +125°C temprature range, or 59X for the 0°C to + 75°C temperature range.

Vee= PIN 16
GND =PIN 8'airchild patent pending

Fig. 2

F=AIRCHILCJSEMICONDUCTOl:::r·313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379·6435

3-32

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD' MEDIUM SCALE INTEGRATION • 9304
FUNCTIONAL DESCRIPTION
The Fairchild 9304 logic block consists of two separate high speed carry dependent sum .full adders.. 'This design allows a minimum carry propagation time
when the adders are used in ripple carry applications. 'The adders are identical except that adder 2 has provision for either active high or active low inputs
at the A and B terminals. The adders prodUte a low carry and both low and high sum with active high inputs, a high carry and both high and low sum when
active low inputs are used. Thi's principle of duality is shown iii Figure 12, where the adders are drawn as functional blocks.
:

1.l

The Trut~ Table and Loading',:RuJes for the 9304 are shown in Table I and Table II.

TABLE I -TRUTH TABLESADDER 2ADDER 1

c

B

A

Co

s

s

c

L

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

H
H
H
L
H
L
L
L

H
L
L
H
L
H
H
L

L
H
H
L

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

L
L
L
H
H
H
H

H
L
L
H

...
·TABLE II...,,..
•'

.' ..

'

.

',

LOADING RULES (1 U.L.

=

TTµL Gate Input Unit Load)

LOADINGINPUTS
FA 1
FA2
'·;·

A,B&C

4 U.L.

. Ai. 82 & c

4 U.L.

'A1&B1

1 U.L.

OUTPUTS
FA 1

Co.

..~

FA2

FANOUT.,OUTPUTSINPUTSOUTPUTSINPUTS

7 U.L.

s

9 U.L.

s

10 U.L.

Co

7 U.L.

s

9 U.L.

s

lOU.L

81

A1

B2 A2

Co

s

s

L
L
L
L
L
L
L
L

L
L
L
L
H
H
H
H

H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
H

H
L
L
H
H
H
L
L
H
L
H
L
H
H
H
H
L
H
H
L
L
L
H
H
L
H
L
H
L
L
L
L

L
H
H
L
L
L
H
H
L
H
L
H
L
L
L
L
H
L
L
H
H
H
L
L
H
L
H
L
H
H
H
H

H = High Voltage Level
L Low Voltage Level

=

3-33

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

FAIRCHILD MEDIUM SCALE INTEGRATION • 9304
TABLE 111ELECTRICAL CHARACTERISTICS (TA = -55°C to +125°C, Vee = 5.0 V ± 10%) (Part #U6B930451X)
SYMBOLCHARACTERISTICS-55°C
MIN. MAX.

LIMITS+25°C
MIN. TYP. MAX.

+125°C
MIN. MAX.

UNITS

VoH

Output High Voltage

2.2

2.4

2.4

Volts

VOL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.8

0.9

0.8

IF
4 IF

-1.6
-6.4

tpd+

c toC0-1.1 -1.6-4.4 -6.4-0.97 -1.24-3.88 -4.96
15
60
60
240
8
13

-1.6
-6.4
-1.24
-4.96

IR
4 IR

Input Load Current
Input Load Current
Input Load Current
Input Load Current
Input Leakage Current
Input Leakage Current

tpd-

c to C0

8

13

ns

tpd+

A1 to S
A1 to S

28
25

40
35

ns

IF
4 IF

tpd-

0.4

2.0

2.7

0.21

1.7

-1.24
-4.96

0.4

0.4

Volts

Volts

1.4

60
240

CONDITIONS
Vee= 4.5 V, 10 H = -1.2 mA (Pins 7 & 9)
Vee= 4.5 V, 10 H = -1.08 mA (Pins 6 & 10)
Vee = 4.5 V, 10 H = -0.84 mA (Pins 5 & 11)
Vee= 5.5V, 10 L = 16 mA (Pins 7 & 9)
10 L = 14.4 mA (Pins 6 & 10)
Im = 11.2 mA (Pins 5 & 11)
Vee= 4.5V, 10 L = 12.4 mA (Pins 7 & 9)
10 L = 11.2 mA (Pins 6 & 10)
1.oL = 8.7 mA (Pins 5 & 11)
Guaranteed input highthreshold for all inputs

Volts

Guaranteed input low
threshold for all inputs

mA

Vee= 5.5V

mA

Vee= 4.5VµA

Vee= 5.5 V, VR = 4.5 V
Ground on other inputs

VF=0.4V
VR = 5.5Vonother inputs

ns
Vee= 5.0V
CL= 15 pF
See Fig.11

ns

TABLE IVELECTRICAL CHARACTERISTICS (TA= 0°C to +75°C, Vee= 5.0 V ±5%) (Part #U6B930459X)
SYMBOLCHARACTERISTICS

0°C
MIN. MAX.

LIMITS+25°C
MIN. TYP. MAX.

+75°C
MIN. MAX.

UNITS

VoH

Output High Voltage

2.4

2.4

2.4

Volts

VOL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.85

0.85

0.85

IF
4 IF

Input Load Current
Input Load Current

-1.6
-6.4

-1.0 -1.6-4.0 -6.4

IF
4 IF

Input Load Current
Input Load Current

-1.41
-5.64

IR
4 IR
tpd+

Input Leakage Current
Input Leakage Current
c toC0-0.9 -1.41-3.6 -5.64
15
60
60
240
8.0
15

-1.6
-6.4
-1.41
-5.64

tpd-

c toC 0

8.0

15

ns

A1 to S

28
25

45
40

ns
ns

!e9+
tpd-

A, toS

0.45

3.0

0.21

1.8

1.9

0.45

0.45

Volts

1.6

3-34

Volts

60
240

Volts

CONDITIONS
Vee= 4.75V, 10 H = -1.2 mA (Pins 7 & 9)
V0e = 4.75 V, 10 H = -1.08 mA (Pins 6 & 10)
Vee= 4.75V, 10 H = -0.84 mA (Pins 5 & 11)
Vee= 5.25 V, 10 L = 16 mA (Pins 7 & 9)
IOL = 14.4 mA (Pins 6 & 10)
10 L = 11.2 mA (Pins 5 & 11)
V0e = 4.75 V, 10 L = 14.1 mA (Pins 7 & 9)
10 L = 12.7 mA (Pins 6 & 10)
IOL = 9.85 mA (Pins 5 & 11)
Guaranteed input highthreshold for all inputs
Guaranteed input low
threshold for all inputs

mA

Vee= 5.25 V, VF= 0.45 V
VR = 5.25 Von other inputs

mA

Vee= 4.75 V, VF= 0.45 v
VR = 5.25 Von other inputsµA

Vee= 5.25 V, VR = 4.5 V
Ground on other inputs

ns
Vee= 5.0V
CL= 15 pF
See Fig.11

FAIRCHILD MEDIUM. SCALE INTEGRATION • 9304
TYPICAL INPUT AND OUTPUT CHARACTERISTICS
INPUT CURRENT VS INPUT VOLTAGE
FIG. 3 PINS 1, 2, 3, 4, 12, 15
FIG. 4 PINS 13, 14

INPUTS
0.5

Vcc"S,OV
1.·is·c

EQUIVALENT C1Reu1t·M

Vee~ ·1.5asIf~ -2.5

7

v

/

~

!!

-,

·3.S

-

-2.s H--t---l--l--l--1-11-1--1--1--1

]

-4.S
-1.0

1.0

2.0

3.0

4.0

1.0

VIN - INPUI VOLTAGE· VOLIS

1.0

2.0

4.0

VIN· INPUT VOLTAGE· VOLISOUTPUT CURRENT VS OUTPUT VOLTAGE
FIG. 5 LOW STATE
FIG. 6 HIGH STATEOUTPUTS70

HIGH STATELOW STAtE

ID

Vcc•S,OV
TA·zs•c -1--1--1-+-+---l--~-+--l

Vee

Vee· s.ov+-

TA• 25°C

I
l/

lZ

lL

s

_o -SO~................._._..._..._._.__._..._.L-1__,
-0.6

-1.0

-0.2 0 0.2

0.6

1.0

1.4

·70

f

-1.0

vA
o

1.0

24

!!

Fig. 7

Fig. 8TYPICAL CARRY TURN ON
D£LAY TIMEVERSUS tEM!J.RATURE

TYPICAL CARRY TURN OFF
DELAY TIMEVERSUS· TEMPERATURE

24

48

iii)

Fig. 9TYPICAL ADD TURN ON
DELAY TIMEVERSUS TEMPERATURE

Fig. 10.

.......,;:: 32~! 12 r-...

y
!"---

i
!

v

e

........

.

~

1--

>

SOeFif, 1

4.D'+---J

L....:p'Vee· s.ov
eL·ur

Vee• s.ov-SS ·35 ·15 5.0 25

TA • AMBiENT TEMPliRATURF. • ~C

45 65 85 105 1lS

TA• AMBIENT TEMPERATURE· 'C

lfcc

v

-ss ·35 ·IS 5.0 25

41 65

SOeflg. 7\"15~

CL• ISpf

115 105 125

TA· AMBIENT TEMPERATURE· 'C

Youn

I

'INClUOl!S PROBE AND JIG
CAllACltANCE

Vee

Fig.11- SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

3-35

~

SOe Fig. 7
Vee• 5.0V

2.0 kOFREQUENCY"' 2.0 MHz
PULSE WIDTH "'250 ns
RISI! 'l'IME < 15 ns
FALL tlME < 15 ns
AMPLITUDE .. 4.0 V""'......., v

16

SOeflg. 7

CL •!Spf·» •!$,•II 5.0 i5 41 6S 85 ll& 1lS

24

9.o

TYPICAL ADD TU~ OFF
DELAY TIMEVERSUS TEMPERATURE

'

!I!

= 16
1.0

.o

1

!! ..,

!I!

;

s.o

. 1.0

Voui • OUTPUTVOLTAGE ·VOLTS

VouT. OUTPUI VOLTAGE - VOi.JS

Vee· s.ov·SS ·35 ·IS S.O 25

45

6S

85 105 125

TA· AMBIENT TEMPERATURE· •eFAIRCHILD MEDIUM SCALE INTEGRAllbN ··~ 9304
APPLICATIONS - The 9304 dual adder has been designed to be useful in a wide variety of applications such as addition, parity generation andchecking, code conversion, majority gating and other applications for which this combination of logic gates may be useful. The multifunctional
capabilities of the Fairchild dual adder can be seen from reference to the applications shown.

__Q_

c

B
A
9304 FA 1

s

<:Y

s

Co

C
B
A
9304 FA 2

S

S

i

_j

__Q_

c B A
9304 FA 1
s s Co

-OR-

Co

v-

I

Fig.12'- FUNCTIONAL BLOCK REPRESENT}\TION ,The principle of duality allows 2 ways of representing each adder. The circuit'is the same in both ca$es but the lo~ic diagrams diffe~~ _The dual
diagrams facilitate logic design and allow a greater understanding of the capabilities of the device.
,-

.::·.

.

·!i

,",'\'. ,·:.•:, ! ·. , . •·... ·..

PROPAGATION DELAY AND
PACKAGE COUNT AGAINST WORD. LENGTH -FC)R .: RIPP(E CARRY ~DDITION
400 ~----~"-.--~~-

C

B"'- _300 >--l--'-l-~~~-::+-:-__.1-.£-1. c .......

A

9304 FA 1

S

S

Co

o.____.__,_---'--'--'----'---'--'o
0

10

20

JO

40

NUMBER OF BITS·,,j•

Fig.13- RIPPLE CARRY PARALLEL ADDITION
Shown above is a high speed ripple carry parallel addition scheme.
Only one and-or-not gate relay is incurred at each stage allowing atypical addition speed of (N+l) x 8 ns, where N is the number of bitsin the word. A similar scheme will work if the negation inputs are used,
and the design acts as a subtractor when the complement of one variable is provided.

Fig. 14
The curve shows pr9pai_11tion _delay of the rip.NJ~ Garry Adderdritwn:in Figure 5. Plotte4 on, the same diagram i~ .~ curve showing the__ low pa-*age countres~ltin~ from this Ripple Scheme.

"1-:

3-36

FAIRCHILD MEDIUM SCALE INTEGRATION • 9304

Ca>-------.
FROM
STAGE

x-1

Ca
TO STAGE'-------------+-----cb x+l~---ccSx
Cx
TO PARALLEL ADDER

Fig. 15 -ADDITION OF SIX VARIABLES
The above design shows how the 9304 can be used in carry save arithmetic. Six input variable are reduced
to two where they can be added in a parallel adder. Delay between inputs and outputs is typically 50 ns,
allowing extremely high speed computation. Additional variables may be added or the concept can be extended to multiplication, division, and various other ar.ithmetic operations.

GND.

Go
GND.---+-<t-+-.

Bo

Fig. 16 -BYTE PARITY GENERATION OR CHECKING

The 9304 can be used for parity checking or generating. The above
design uses 2 9304's to generate parity for an 8 bit byte or check
parity over 9 bits. The delay from input to odd parity is typically 35 ns.
Additional adder blocks can be used to generate or check parity overlarger word lengths. The concept can also be used for hamming andcyclic code generation and checking.

Fig. 17 -4 BIT PARALLEL GRAY TO BINARY CONVERSION

A 4 bit parallel binary to gray conversion is shown. The adders can also
be used for other cyclic code manipulations.

9306
MSI UP/DOWN BCD COUNTERA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRIPTION - The 9306 i~ a high speed synchronous 8421 BCD up/down decade counter. It isa synchronqusly presetable, multifunctional MSI building block useful iii a large number of counting, digital
integration, and conversion applications. Seven decades of synchronous operation are obtalnable with noexternal gating packages required through an internal carry look-ahead counting technique.

FEATURES:• SYNCHRONOUS COUNTING AND PARALLEL ENm• DECODm TERMINAL COUNT. .
• BUILT"IN CARRY/BORROW .CIRCUITRY• 1YPICAL POWER DISSIPATION OF 350 mW.
• THE INPUT/.ouTPUT CHARACTERISTICS PROVIDE EASY INTERFACING WITH FAIRCHILD DTµL,
LPDTµL, AND TTµL FAMILIES (CCSL). ·.
• ALL CERAMIC H~RMETIC 24 PIN DUAL IN-LINE PACKAGE• INPUT DIODE CIAMPINGPHYSICAL DIMENSIONS.110.()9()j_k.015
ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Tempe_rature
Temperature (Ambient) Under Bias
Yee Pin Potential to Ground Pin
Voltage Applied to Outputs for high output state
Input Voltage (D.C.)-6S°C to +150°C-ss cto +125°C
0-0.SVtO +7V-0.S V to Vcc value-o.s vto +s.s v

LOGIC DIAGRAM

ORDER INFORMATION - Specify U6N9306XXX for 24-pin Dual ln:Line package where XXX is SIX for the-SS°C to +12S°C temperature range, or S9X for the 0°C to 7S°C te(llperature range.

23

22

21

2o

19

11

'

'
ls--.
_

_,.1.-....;.....;jl-._~_.

3

5

8

10

Ycc-Pin24
Gnd.-Pin 12

l=AIRCHILC>
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-38

SEMICONDUCTORA DIVIStON Of fAIRCHllD CAMERA AND INSTRUMENT CORPORATNJHFAIRCHllll MEPlUM SCALE INTEGHATION • 9306
FUNCTIONAL DESCRIPTION -A clock buffer and inverter drives the four clocked RS master-slave flip flops in parallel, so that synchronous operation
is obtained. When the clock input (CP) is low, the slave is steady, but .data can enter the master via the R and the S inputs. During the lqw to hightransition of CP, first the data inputs (R and S) are inhibited, so that a later change in the input data will not affect the master; secondly, the now
trapped information in the master is transferred t(l the slave and is reflected at the outputs. When the transfer is completed both the master andthe slave are steady as long as the clock input remains, high, and regardless of the logic state at any other input to the device. During the high to
low transition of the clock input, first the transfer pathJrom master to slave are inhibited, leaving the slave steady in its present state, secondly, thedata inputs (R and S) are. enabled so that new data can enter the master. As a result of this synchronous operation higher clock frequency ispossible and much less e~o/nal logic is required in most applications. Mode selection is accomplished as shown in the table below. However, several
restrictions are placed on the manner of selection. First, the transition of CE from high to low or of PE from low to high may only be done when CP
is high. Second, any change of CD must be done only when CP is high. The remaining transitions may be made by following the setup and releasetimes specified under "Switcliing Characteristics.'',I'•

MODE SELECTION SCHEME..

PE

CD

CE

Mode

0
0
0
0
1
1
1
1

0
0
1
1
1
0
1
0

0
1
0
1
1
1
0
0

presetting
presetting
presetting
presetting
count upcountdownno change
no change

LOADING RULES(1 U.L. = 1 TTµl input gate load)

INPUT

FAN IN

2 Unit Loads

P0, P1, P2' P3% Unit LoadOUTPUT~~:';

1 Unit LoadFAN OUT

Qo, Q,, Qi, Q3, TC'. ; ·~. ii'! ;., '1 Unit load

CD, CE0 , CE" CE2'
CE 3, CE4, CE5
CP, PE

6 Unit Loads...' ·.

ELECTRICAL CHARACTERISTICS (TA =' ~55°C to +125°C, Vee = 5.0 v ± 10%)....... '.

\c
SYMBOL_c_

CHARACTERlSTICS
',.!

VoH

Output High Voltage

VOL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

IF
2 IF

%IF
IR
2 fR

+25°C
MIN. TYP. MAX.

+125°C
MIN. MAX.

UNITSCONDITIONS & COMMENTS

2.4

2.4

2.4

Volts

Vee= 4.5 V, 10 H = -0.36 mA

Volts

Vee= 5.5 V, 10 L = 9.6 mA
Vee= 4.5 V, IOL = 7.44 mA
Guaranteed input highthreshold for all inputs

0.4
2.0

2.7
0.2

0.4

0.4
1.4

1.7

I

''• '
Input Load Current
E0 , E1, E2' E3 , E4 , E5 , CD
Input Load Current
CP,PE
Input Load Current
P0 , P1, Pv P3
Input Leakage Current
E0 , E" E2' E3 , E4 , E5 , CD
Input Leakage Current
CP,PEIn put Leakage Current
Po, pl' Pv P3

LIMITS-55°C
MIN. MAX.

Volts

0.8

0.9

0.8

Volts

-1.6

-1.0 -1.6

-1.6

mA

-3.2

-2.0 -3.2

-3.2

mA

-1.07

-.7 -1.07

-1.07

mA

60

10

60

60

µA

120

20

120

120

µA

40

7

40

40

µA

3-39

Guaranteed input low
threshold for all inputs

Vee= 5.5V
VF= 0.4v

Vee= 5.5V
VR=4.5V

~~~~~~~~~~~~~~~~~~-'-~~~~~~~~~~~~~~~~~~~~~~~~~~--,FAIRCHILD MEDIUM SCALE INTEGRATION • 9306

I

L~-·~·-·~,_...... ~'"'"' """~J

ELECTRICAL CHARACTERISTICS (TA = 0°C to +75°C, Vee=5.0 V ±5%)SYMBOLCHARACTERISTICS

0°C
MIN. MAX.

+25°C
MIN. TYP. MAX.

+75°C
MIN. MAX.

UNITSCONDITIONS & COMMENTS

VoH
VOL

2.4

2.4

2.4

VIH

Output High Voltage
Output Low Voltage
Input High Voltage

Volts
Volts
Volts

VIL

Input Low Voltage

0.85

0.85

0.85

Volts

Vee= 4.75 V, 10 H -0.36 mA
Vee = 5.25 V, 10 L == 9.6 mA
Vee= 4.75 V, IOL 8.5 mA
Guiiranteed input highthreshold for all inputs
Guaranteed input low
threshold for all inputs

IF

Input Load Current
Ea, E1, Ev E3, E4, Es, CD
Input Load Current
CP, PE
Input Load Current
Pa, p" Pv P3
Input Leakage Current
Ea, E1, E2, E3, E4 , Es, CD
Input Leakage Current
CP, PE
Input Leakage Current
Pa, p" p2' P3-1.6-1.0 -1.6

-1.6

mA

-3.2

-2.0 -3.2

-3.2

mA

-1.07

-.7 -1.07

-1.07

mA

LIMITS

2 IF
%IF
IR
2 IR
%1R

SWITCHING CHARACTERISTICS (TA

1.9

3.0
0.2

0.45

1.8

0.45
1.6

60

10

60

60

µA

120

20

120

.120

µA

40

7

40

40

µA

=

=

-1

I

Vee= 5.25V
VF= 0.4 v--!

Vee= 5.25V
VR =4.5V=25°C)SYMBOLCHARACTERISTICS

tpd+ (Q)tpd- (Q)!e_d+ (TC)tpd- (TC)t, (CE)t, (CE)

Turn-Off Delay
Turn-On Delay
Turn-Off Delay for TC
Turn-On Delay for TC
Set-Up Time for CE
Release Time for CE
Set-Up Time for Data
Release Time for Data
Set·UP Time for PE
Release Time for PEt,t,t, (PE)t, (PE)

0.45

MIN.

TYP.
20
20
40
30
25
25
15
15
20
20

MAX.

UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns

CONDITIONS & COMMENTS
Vee= 5.0V
C~ = 15 pF(fig. l)Vcc=5.0V
CL = 15 pF (Fig. 2)
Vee= 5.0V
CL= 15 pF(Fig. 3)ns

SET-UP TIME: t, is defined as the minimum time required for the logic level to be present at the logic input prior to the clock transition from low
to high in order for the flip-flop(s) to respond.
RELEASE TIME: t, is defined as the maximum time allowed for the logic level to be present at the logic input prior to the clock transition from low
to high in order for the flip-flop(s) not to respond.

3-40

_]

FAIRCHILD MEDIUM SCALE INTEGRATION • 9306--------1.5¥
I

lslCE)lj-.

I

lpd+ ITC)
TC

CE

t

-j \--1,ICE)
I--------1.5¥

I-1•--lpd-ITC)-------f - - \I

Go~ - - - - - - - - - - - - 1 . 5 ¥---------1.5¥

I

Fig. 1

Po

Fig. 2------_::--_::--~-------------------~ - - - - 1 . 5 ¥Is~r- ~ rlr
I

I

CP

-J

1--trlPE)

I

PE------------1.5¥-----+ ------ \---1.5¥

Fig. 3

APPLICATIONSPARALLEL INPUT ENABLE
COUNT DIRECTIONCP

COUNT ENABLE

TO MORESIGNIFICANTDECADES

Fig. 4

3-41

9307
MSI SEVEN SEGMENT DECODERA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTlENERAL DESCRIPTION
The. 9307 is a Seven Segment Decoder designed to accept
our inputs in 8421 BCD code and provide the appropriate outputs to drive a seven segment
1umerical display. The decoder can be used with seven segm~nt incandescent lamp, neon,'lectro-luminescent, or CRT numeric displays. The 9307 is compatible with all other Fairchild:CSL devices.

• CCSL COMPATIBLE• AUTOMATIC RIPPLE BLANKING FOR SUPPRESSION OF LEADING EDGE ZEROES• LAMP INTENSITY MODULATION CAPABILITY· LAMP TEST FACILITY· BLANKING INPUTACTIVE HIGH OUTPUTSALL CERAMIC "HERMETIC" 16 PIN DUAL
IN-LINE* PACKAGE

PHYSiCAL DIMENSIONS

.1001
MIN.

r=

.110
.090'

L

'

.023

MAX.

NOTES,
1. Leads are intended for insertion m hole rows on.300" centers. They are purposely shipped with"positive" (.375) misalignment to facilitate insertion.
2. Board·drrlling dimensions should equal yourpractice tor a conventional .020 !inch diameter lead.

Fig. 1LOGIC SYMBOL
712635

BSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature-65°C to +150°c

Temperature (Ambient) Under Bias

-55°c to +125°C-0.5 Vto +7 V

Vee Pin Potential to Ground Pin
Voltage Applied to Outputs for high output state
Input Voltage (D.C.)

JlJ>-0.5 V to +Vee value-0.5 V to +5.5 V
9307 7$ DECODER
RBO a

b

c

d

e

f

g

RDER INFORMATION
iecify U6B9307XXX for 16 pin Dual In-Line package where XXX is 51X for the -55°C to +125°C temperture range, or 59X for the o•c to +75°C temperature range.
4 13 12 11 10 9

15 14

Vcc=PIN 16
GND=PIN 8

Fig. 2

Fairchild patent pending.

F=A.IRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-42

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MEDIUM SCALE INTEGRATION • 9307
The 9307 seven segment decoder accepts a 4 Bit BCD 8421 code input and produces the appropriate outputs for selection of segments in a sevensegment matrix display used for representing the decimal numbers 0 • 9. The seven outputs (a, b, c, d, e, f, g) of the decoder select the correspond·
ing segments in the matrix shown in Figure 3. The numeric designations chosen to represent the decimal numbers are shown in Figure 5, together
with the resulting displays for input code configu'rations in excess of binary nine.
The decoder has active high outputs so that a buffer transistor may be used directly to provide the high currents required for incandescent displays.
If additional base drive current is required external resistors may be added from the supply voltage to the seven segment outputs of the decoders.
T11e value of this resistor is constrained by the 10 mA current sinking capability of the output transistors of the circuit.
The device has provision for automatic blanking of the leading and/or trailing edge zeroes in a multidigit decimal number, resulting in an easily read·able decimal display, conforming to normal writing practice. In an eight digit mixed integer fraction decimal representation, using the automatic
blanking capability, (0060.0300) would be displayed as (60.03). Leading edge zero suppres~ion is obtained by connecting the Ripple Blankiog Output(RBO) of a decoder to the Ripple Blanking Input (RBI) of the next lower stage device. The most significant decoder stage should have the RBI input
grounded; and, since suppression of the least significant integer zero in a number is not usually desired, the RBI input of this decoder stage should beleft open. A similar procedure for the fractional part of a display will provide automatic suppression of trailing edge zeroes.
The decoder has an active low input Lamp Test which overrides all other input combinations and enables a check to be made on possible display mal·functions. The RBO terminal of the decoder can be OR· tied with a modulating signal via an isolating buffer to achieve pulse duration intensity
modulation. A suitable signal can be generated for this purpose by forming a variable frequency multivibrator with a cross coupled pair of OTµL gates.

Fig. 3Fig. 4

SEGMENT DESIGNATIONTRUTH TABLE

a

LT

RB
IN

L
H

L

L

L

L

L

L

L

L

L

L

L

L

H
L 0

H

H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
L
L
L

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

H
L
H
H
L
H
H
H
H
H
L
L
L
H
L
L

H
H
H
H
H
L
L
H
H
H
L
L
H
L

H
H
L
H
H
H
H
H
H
H
L
L
H
H
L
L

H
L
H
H
L
H
H
L
H
H
H
H
L
H
H
L

H
L
H
L
L
L
H
L
H
L
H
L
L
L
H
L

H
L
L
L
H
H
H
L
H
H
L
L
H
H
H
L

L
L
H
H
H
H
H
L
H
H
H
H
H
H
H
L

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

a

b

c

d

•

I

RB
OUT

9

x x x x x H H H H H H H
xd
HAo A1 A2 A3

x

H

H
H
H
L
L
L

L
H
H
H
H

L.
L

0
1
2
3
4

s

6
7

8
9
10
11
12
13
14
15

H =HIGH VOLTAGE LEVEL
L= LOW VOLTAGE LEVELX .. EITHER HIGH OR LOW VOLTAGE LEVEL

Fig. 5NUMERICAL DESIGNATIONS

0

1-1
I- I

1

2

3

5

4

-I I I I

II
I I-

I-

I-

I

6

8

7

Ao, A,, A,, Ai
Ro11N)
LT

1
1
5

11

12

13

14

I- LJI I I I I

--

-

-

=1 DTµL Gate Input Load)

Loading (51X & 59X)
High State

10

I -I 1-1 I In
I n- -I I

Table 1-Loading Rules (1 U.L.

Inputs9Outputs

Lew State
1a, b, c, d, e, f, g

1h

Rs1our1

4.3

3-43

Fal) Out
59X
51X
8
7
2.0
1.5

-

15

FAIRCHILD MEDIUM SCALE INTEGRATION • 9307
TABLE 11ELECTRICAL CHARACTERISTICS (TA= -55°C to +125°C, Yee= 5.0 v ± 10%) (Part #U6B930751X)
LIMITS
SYMBOLCHARACTERISTICS-55°c
MIN. MAX.

+z5°c
MIN. TYP. MAX.

+125°cMIN. MAX.

UNITSCONDITIONS

YoH

Output High Voltage

4.3
3.0

4.3
3.0

4.4
3.0

Volts

Yee= 4.5 V 10 H = 0.0 mA (Pins 9-15)
Vee= 4.5 V loH = -70 µA (Pin 4)
Inputs at threshold voltages (V 1L or V1H)

VOL

Output Low Voltage

Volts

10 L = 12.5 mA (Pins 9-15)
IOL = 3.1 mA (Pin 4)(Pins 9-15)
Yee= 4.5V loL = 10 mA
IOL = 2.4 mA (Pin 4)
Inputs at threshold voltages (V1L or V1H)

VIH

Input High Voltage

Volts

Guaranteed input highthreshold for all inputs

VIL

Input Low Voltage

1.4

1.1

0.8

Volts

Guaranteed input low
threshold for all inputs

IF (Pin 3)
IF (Pins 1, 2, 6, 7)
IF (Pin 5)

Input Load Current
Input Load Current
Input Load Current

-6.4
-1.5
-0.75

-6.4
-1.5
-0.75

-6.4
-1.5
-0.75

mA

Yee= 5.5V

IR (Pin 3)
IR (Pins 1, 2, 5,. 6, 7)

Input Leakage Current
Input Leakage Current

10
2.0

25
5.0

µA

VR=4.5V
Yee= 5.5 V
Ground on other inputs

IA (Pins9-15)

Available Output Current

mA

Yee=4.5V
Your= 0.85 V
Inputs at threshold voltages (V 1L or V1H)

15e (Pins 9-15)

Short Circuit Current

-3.7

mA

Your= O.OV

tpd+

Switching Speed

500

ns

tpd-

Switching Speed

500

ns

0.4

2.1

4.4
4.0
0.4

0.21

0.4

1.7

1.9

-1.4

-1.0

-1.4

Yee= 5.5V

VF= 0.4 v
YR= 5.5 Von
other inputs

Vee=5.5V

Yee = 5.0 V, See Figure 6

TABLE 111ELECTRICAL CHARACTERISTICS (TA= 0°C to +75°C, Yee= 5.0 V ±5%) (Part #U6B930759X)
LIMITS
SYMBOLCHARACTERISTICSo•cMIN. MAX.

MIN.

4.3
2.7

4.3
2.7

+25°C
TYP. MAX.

+75°c
MIN. MAX.

UNITSCONDITIONS

4.3
2.7

Volts

Yee= 4.75 V 10 H = 0.0 mA (Pins 9-15)
Yee= 4.75 v 'OH= -70 µA (Pin 4)
Inputs at threshold voltages (V 1L or V1H)

Volts

Yee= 5.25 V 10 L = 11.5 mA (Pins 9-15)
IOL = 2.75 mA (Pin4)(Pins 9-15)
Yee= 4.75 V IOL = 10 mA
10 L = 2.4 mA (Pin 4)
Inputs at threshold voltages (V 1L or V1H)

Volts

Guaranteed input highthreshold for all inputs

VoH

Output High Voltage

VOL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.85

0.85

0.85

Volts

Guaranteed input low
threshold for all inputs

IF (Pin 3)
IF (Pins 1, 2, 6, 7)
IF (Pin 5)

Input Load Current
Input Load Current
Input Load Current

-6.4
-1.5
-0.75

-6.4
-1.5
-0.75

-6.4
-1.5
-0.75

mA

VF= 0.45 V
Vee= 5.25 V
YR = 5.25 on other inputs

IR (Pin 3)
IR (Pins 1, 2, 5, 6, 7)

Input Leakage Current
Input Leakage Current

25
5.0

50
10

µA

YR= 4.5 v
Vee= 5.25 V
Ground on other inputs

IA (Pins 9-15)

Available Output Current

mA

Yee= 4.75 V
Your= 0.75 V
lnpu-1s at threshold voltages (V 1L or V1H)

lse (Pins 9-15)

Short Circuit Current

-4.0

mA

Your= 0.0 V

tpd+

Switching Speed;:;cc 1ns

tpd-

Switching Speed

500

ns

0.45

0.21

0.45

0.45

2.0

2.0

-1.4

4.6
4.0

2.0

-1.0

-1.4

3-44

Yee= 5.5V

Yee= 5.0 V, See Figure 6

FAIRCHILD MEDIUM SCALE INTEGRATION • 9307
TYPICAL INPUT AND OUTPUT CHARACTERISTICS
INPUTSINPUT CURRENT VERSUS INPUT VOLTAGE

Equivalent Circuit

t-~e·J.ov
-0.4

I

f

I-TA• 25'e

-0.8

ii

<

JL1

fS

_/

~

kd

1

Vee· 5.ov-o.H--rA. 25'e ---1--1--1-1--+--+---t-4.0 f--+--=-1-"""'-"f--+--t--f---t--i~·8.0 H-+--+-l--+--+-1----t---i-10 ~~~-~~~-~-+-~
-1.0
1.0
2.0
3.0

-2.0

-2.0

-2.o l---+--+-........i-+-V--1[2]-ft--+----1----;~ -6.0 H-+--+-l--+--+-1----t---i

u

·1.6

RB11N1 INPUTeP1~ -1.2LT INPUT

-1.0

1.0

2.0

3.0

~

1'

!;;

~-0.4 l--+-+-+--+-."'1v--ll--l--t--+--I

1£

5~-0.6 l--+-+v_,...c.......+--1---11--1---t--+--1~0.8 f--+t+-+--+---+-+--+-+---+--+---1-1.0 ~~~~-+--+--+-~~~~
-2.0
-1.0
1.0
2.0
3.

VIN - INPUT VOLTAGE - VOLTS

VIN - INPUT VOLTAGE -VOLTS

VIN - INPUT VOLTAGE· VOLTS- - - - - - - - - - - - - - O U T P U T CURRENT VERSUS OUTPUT V O L T A G E - - - - - - - - - - - - - U6B930751X (-55°C to +125°C)
U6B930759X (0°C to +75°C)
OUTPUT IN HIGH STATEOUTPUT IN HIGH STATEa, b, c, d,e, f, g

a, b, c, d,e, f, g

OUTPUTS
5.0

RB1our1 OUTPUTt'· .r.

I- Vee 5.ov
TA• 25'e

v

v

t

_..J/

1.0

OUTPUTS

<

I

7

<.>

v

~

7.0

·l.O

0

1.0

3.0

5.0

_)./

t

v

\

-5.0 [

7.0

-1.0

-5.0

0

3.0

1.0

Your - OUTPUT VOl.TAGE - VOLTS

vour - ourPur volrAGE. VOLTS

I/

lZ:

i

a

30

5

20

~

0

lL

~

Ii

ll'.:

0

0.2

1-

]
j_
2.0

/I
0.4

0.6

0.8

1.0

Your- OUTPUT VOLTAl;E - VOLTS

1.2

0.2

0
0.4

7.

...d VT5]v·rr_,

8.0

Yee. 4.5V

_i

0

10

12

_g 4.0TA• -55°C H

5.0

RB1our1 OUTPUT

~

[ZJ

3.0

12

~

a

f

10

1.0

a, b, c, d, e, f, g
OUTPUTS

RB1our1 OUTPUT

TA •25'e!-- <Vee· 5.ove0Your - OUTPUT VOl.TAGE -VOLTS

16

INPUTS AT THRESHOLD VOLTAGES IVIL or Vrnl.__/___,____...___.____.___.___._..__~-1.0

OUTPUT IN LOW STATEOUTPUT IN LOW STATEO.UTPUTS

7.0

5.0

Your - OUTPUT VOl.TAGE - VOLTSa, b, c, d,e, f, g
50/........

-~

5.0

I
1

r-+-·

<e

e

0

3.0

RB1our1 OUTPUT

TA •25'e-s.o ~T~-~~~-~~~~
0.!.

I- Vee· 5.ov

[

-5.0
-1.0

.,

5.0

0.6

0.8

1.0

_j
0.2

1.2

0.4

0.6

0.8

Your - OUTPUT VOLTAGE - VOLTS

Your - OUTPUT VOLTAGE - VOLTS

OUTPUTS
Equivalent Circuit

Vee

3-45

1.0

1.2

i

0.2

7

0.4

III
Vee- 4.75V, TA. O'e-1

0.6

0.8

Your. OUTPUT VOLTAGE - VOLTS

FAIRCHILD MEDIUM SCALE INTEGRATION • 9307
Fig. ~SWITCHING CIRCUIT AND WAVEFORMS

11ill~ generahir characteristics:

Amptitud~ = 3.o \t

···~
\tpl
:
I i.r:::-

Freq. = 500 kHz
Pilise width = 1000 ns
t, = t1 ::::; 15 ns"Includes probe and jig capacitance

VOUT~ • ---

tpd+1

~-

~ l.3VAPPLICATIONS

11 X2 X4X1

9307 79 DECODER

I

I

I

I

I

I

I

I

9307 TS DECODER

To remaining segments
via driving circuitryl TO REMAINING SEGMENTS'' ''VIA BUFFER CIRQJITS

v,.

-

c

E.L. Display
Segment..

___...I
RI
L ___ .J

The current sinking
capability DI the 9307
makes it possible to
add a resistor extarnallyto increase the drive tothe buffer transistor if needed.

TO CATHODEOf OTHER SCRS

Fig. 79307 Seven Segment Decoder driving Electro-Luminescent Display.

Fig. 89307 Seven Segment Decoder driving Incandescent lamp Display.

8421 BCD CODE DECADES

11•2•···INTENSITY
MODULATION

9307 75 DECODER

9307 7S DECODER

I

I

I

I

I

I

I

I

I

I

I

I

I

I

LEAST SIGNIFICANT DECADE

9307 7S DECODER

I

..

I

I

I

I

I

I

I

I

I

I

I

I

I
I

I
I

I
I

I
I

I
I

I
I

TO SEVEN SEGMENT DISPLAY LAMPS VIA DRIVING CIRCUITRY

9307 75 DECODER

I
I

I

I

I

I

I

I

I

I

I

I

I

1-

I

I

MOST SIGNIFICANT DECADE

Fi~.~ 9-FOUR DECADE SEVEN SEGMENT INTEGER DISPLAY SCHEME
This scheme incorporates automatic blanking of leading edge zeroes and intensity modulation using an
external variable duty cycle signal.

3-46

9308
MSI DUAL FOUR-BIT LATCHA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRIPTION - The MSI 9308 is a Dual 4-Bit Latch designed for general purpose storag!I applications in high speed digital systems. The 9308 uses TTµL technology and is CCSL compatible. All inputs
incorporate diode clamps to ground to reduce negative line transients. All outputs have active pull-up circuitry
to provide high capacitive drive and low impedance outputs in both logic states to provide good A.C. noise
immunity.

PHYSICAL DIMENSIONSFEATURES• ACTIVE LEVEL LOW ENABLE GATE INPUTS• OVERRIDING MASTER RESET• 25 ns THROUGH DELAY• THE INPUT/OUTPUT CHARACTERISTICS PROVIDE DIRECT INTERFACING WITH FAIRCHILD
DTµL, LPDTµL, TTµL, AND MSI FAMILIES (CCSL).
• INPUT CLAMP DIODES LIMIT HIGH SPEED TERMINATION EFFECTS.

24
23

22
21

.110
.Q90

~

l_

1!LJ1230

,--

15

.020
.015

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Yee Pin Potential to Ground Pin
Input Voltage (D.C.) (See Note 1)
Input Current (D.C.) (See Note 1)
Voltage Applied to Outputs (Output High)
Output Current (D.C.) (Output Low)

1310

14
13
1------!

-65°Cto +1so c-55°C to +125°C-0.5Vto+7V-0.5 Vto +s.5 V-30 mA to +s mA-0.5 V to + Vcc value+30mA
0l-~~--1

NOTE 1: Either Input Voltlge limit or Input Current limit is sufficient to protect the inputs.

LOGIC DIAGRAMDESCRIPTION OF LATCH OPERATION - Data can be entered into the latch when both of the enable inputs
are low. As long as this' logic condition exists, the output of the latch will follow the input. If either of thec1nable inputs goes high, the data present in the latch at that time is held in the latch and is no longer
af'ected by the data input.
The master reset overrides all other input conditions and forces the outputs of all the latches low when alow signal is applied to the master reset input.

ORDER INFORMATION - Specify U6N9308XXX for 24-pin Dual In-Line package where XXX is SIX for the-55°C to +125°C temperature range, or 59X for the 0°C to +75°C temperature range.

2 3 4 6 8 10 14 15 16 18 20 22

1 5 7 9 11 13 17 19 21 23

Vc:c = Pln24
Gnd =Pin 12

Electrical Characteristics on Paa:e 2.

F=AI RC 1-11 L.C
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-643!>

3-47

SEMICONDUCTOR
A DMllON Of FUICHILO CAME.RA AND INSTRUMENT CORPOllATIQllll

F~IRCHILD ME~IUM ~A~E, INTE~RATION • 930$
TABLE 1ELECTRICAL CHARACTERISTICS (T" - -55°C to +u5•c, Yee - 5.0v:I:10%, See Note l) (Pllrt #U6N930851X)
LIMITS
SYMBOLCHARACTERISTICS-55°C
MIN. MAX.

CONPITIONS

TYP.

+125°CMAX. MIN. MAX.

UNITS

MIN.

2.4

2.4

u

2.4

Volts

Yee • 4.5 V, 10 H • -0.6 mA
Inputs at threshold voltages (V1Lor V1H)
(See Note 2)
Yee= 5.5 V, loL = 14.4 mA
Yee== 4.5 V, 10 L"" 11.2 mA
Inputs at threshold voltages (V1Lor V1H)
(See Note 2)
Guaranteed inp1.1t highthresh<1ld for all inputs
Guaranteed input low
threshold for all Inputs
VF= 0.4V.
Yce""5.5V

+25"C

YOH

Output High Voltage

YoL

Output Low Voltage

Y1H

Input High Voltage

VIL

Input low Voltage

0.f

0.9

0.8

Volts

IF

Input Load Cummt
E0, E1and MR Inputs
Input load C1,1rrent
D Inputs
Input Leakage Current
Ee,. E, 1md MR Inputsll)put Leakage Cl.lm'"t
D Inputs
Power Supply Current-1.6-1.1 -1.6

-1.6

mA

-2.7

-1.9 -2.7

-2.7

10

60

60

15

90

9(1

65

9(1

90

1.5 IFIR

J.5 IR
lpo

().4

0.21

u

1.7

2.0

90

0.4

0.4

Volts

VoltS

VF== 0.0 V (See Note 3)
pA

Vee - 5.5 v, VR = 4.5 v

mA

Vee=5.0V

all outputs low
inputs disabled

TABL~ 11..,..

El.ECTRICAL CHARACTERl$1'1CS (T" m; O"C to +75°C, Vee - 5.0 V ::t:5%, See Note 1) (Part .#U6N930859X)
SYMBOLCHARACTERISTIC$

LIMITS+25°C+1s 0 cMIN. MAX. MIN. TYP. MAX. MIN. MAX.

UNITSCONDITIONS

YoH

Output High Voltage

2.4

Volts

VoL

Output low Voltage

VIH

Input High Voltage

VIL

Input low Voltage

IF

Input load Current
E0, E, and MR Inputs
Input Load current
D Inputs
Input Leakage Current
E0, E1 and MR Inputs
Input Leakage Current

Yee • 4.75 V, lour -0.6 mA
Inputs at threshold voltages (V1Lor V1H)
(See Note 2)
Yee""' 5.25 V, lour ;om 14.4 mA
Yee 4.75 V, •our ""' 12.7 mA
Inputs at threshold voltages (V1Lor V1H)
(See Note~.
Guara11teed input highthreshold for all inputs
Guaranteed input low
threshold for all inputs
v00 -5.25V VF=0.45V

1,5 IFIR
1.5 IR

o•c

2.4

0.45

1.9

3.1

D.21

2,4

0.45

0.45

1.6

1.8
0.85

Volts

Volts

0.85

0.85

Volts
mA

....;u

-1.0

-u

-1.6

-2.7

-1.8 -2.6

-2.7

10

60

60

15

90

90

65

117

117

=

=

VF = 0.0 V (See Note 3)

pA

Yee;,.. 5.25 V, Vlt

mA

Vee= 5.0V=4.5 V

Dl~ts

lpo

Power Supply Current

117

all outputs low
inputs disabled

N()TE 1: Units •re pulse tested.
NOTE 2: Output Volteaes •re 11m.nteall for either the in1111t "1•bled cir input di.. b1'4 cai11e.
NOTE 3: This current 11 m..sured at V1N ... o.o V to ln$ure th•t nci 1:11rrent Is being 1norbed '1y .llM tlevi• lnter1111lly. The maximum value elven cuaranteu that th• maximum
instentaneo111 cu111nt tl"t 1:1n flow 1111t of 11141 input at V1N ... 0.4 V i, 2.4 mA.

~

FAIRCHILD MEDIUM SCALE ·INTEGRATION • 9308
A.C. CHARACTERISTICS
9308 SWITCHING WAVEFORMSSTORING A ONE
E1=GND______....,. ...~~t3

~1,_

i.svf
-..I

TIME

________

t4

STORING A ZERO
E1=GND~~·

Min. time that data
, must be present before
enable to not increase t2

x

minus
4

-

ns

tz

Delay from enable tooutput turning off

-

22

x

ns

t3

Min. enable pulse
width to store a ONE

x

15

-

ns

t.

Min. time that data
must remain constantafter removal of enable

x

5

-

ns

ts

Min. time that data
must be present before
the enable to not increase 1t.

x

0

-

ns

t6

Delay from enable
to ·output turning on

-

15

x

ns

t1

Min. enable pulse
width to store a ZERO

x

15

-

ns

ta

Min. time that data
must remain constantafter removal of enable

x

2

-

ns

.,_._t7'----t1•.i1

" ".
'I .

__E_o___. , . , l.SV:=.---!ts I·..-=
D
l.SV

Q

1.-t&

l.SV/~----------.1 taLIMIT (See Note 4)
MIN. TYP. MAX. UNITS

ti

1.SV

__o__________

DEFINITION\i.sv

NOTE 4: Limits indicated by X will be shownon final data sheets.

All delays are measured with Yee= 5.0 V applied to Pin 24 and Pin 12 grounded. The active input is driven by a 9002 TTµL gate with the output loadedwith 15 pf. All outputs are loaded with 15 pf.

LOADING RULESPINLOADINGINPUTS

Do, D1, D2, D3
MR, E0, E1

1.5
1.0

OUTPUTS

Q()I Q,, Q2' Q3

9.0

APPLICATIONSABSTROBE
DATA

c
D

EDoO,~D3

9308 4 Bil LATCH 1

MR

IJo 0, 02 03

AND·OR ENABLE SHOWING ACTIVE LEVELLOW ENABLE GATE UTILITY

3-49

FAIRCHILD ME~IUM SCALE INTEGRATION • 9308
SINGLE MASTER/MULTIPLE SLAVE FLIP-FLOPCLOCK

SLAVE RESISTERADDRESS

11111

II II IRESISTER 7RESISTER I

9308 AS A HOLDING REGISTER.IN COU ...Tl"G AND DISPLAY APPLICATIONSCEP PE

Pg

P1

P2

P3

C(r 9310 UP DECADE COUllrER TC
Ill

Do

°'

02

Ao A1 A2 A3 LT RBI

Ao A1 A2 la LTllBI

9307 7 SEGMENT DECOllER

9307 1 SEGMENT DECOllER

RBOabcdtfl

3-50

9309
MSI DUAL FOUR-INPUT MULTIPLEXERA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRIPTION - The 9309 is a monolithic, high speed, dual four-input digital multiplexer. circuit,constructed with the Fairchild Planar" epitaxial process. It consists of two multiplexing circuits with common
input select logic, each circuit contains four inputs and fully buffered complementary outputs. In addition tooperating as a multiplexer, the 9309 can generate any two function of three variables. Active pullups in the
outputs ensure high drive and high speed performance. Because of its high speed performance and on-chip
select decoding, the 9309 may be cascaded to multiple levels so that any number of lines can be multiplexed
onto a single output buss. The circuit uses TTµL for high speed, high fanout operation and is compatible
with all other members of the CCSL family of digital integrated circuits.

DUAL IN·LINE PACKAGE~~~
ffi.009,~\
011·~ .~~-,=-J

FEATURES• MULTIFUNCTION CAPABILITY• 25 ns THROUGH DELAY• ON-CHIP SELECT LOGIC DECODING• FULLY BUFFERED COMPLEMENTARY OUTPUTS• THE INPUT/OUTPUT CHARACTERISTICS PROVIDE EASY INTERFACING WITH FAIRCHILD DTµL, LPDTµL,
TTµL, AND MSI FAMILIES (CCSL).
• INPUT CLAMP DIODES LIMIT HIGH SPEED TERMINATION EFFECTS.

.090

L

I

.o23
MAX.

NOTES:
I. l,.e1ds are intended for insertion in hole rows on.300" centers. They 11e purposely shipped with
"Positive" (.375) miseli1nment to t1cilit1te insertion.

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature-65°Cto +150°C
Temperature (Ambient) Under Bias
-55°C to +125°C
Vee Pin Potential to Ground Pin-0.5Vto +7V
Voltage Applied to Output when output is high0 V to +Vee value
Input Voltage (DC) (See Note 1)-0.5 V to +5.5 V
Input Current {DC) (See Note 1) .
-30 mA to +5 mA
Current into Output when output is low+30mA
Note 1-either Input Voltage limit or Input Current limit is sufficient to protect the inputs.

Fig. 1ORDER INFORMATION - Specify U6B9309XXX for 16-pin Dual In-Line package or U3L9309i<XX for 16-pin
Flatpak, where XXX is 51X for the -55°C to +125°C temperature range, or 59X for the 0°C to +75°C
temperature range.

LOGIC DIAGRAMLOGIC SYMBOL
12

13

-®
z,

@®

1Y
""'cc

9309

11

10

9

4

7

511'01 '11 '21 131: '1111 '1b '2b 139309 DUAL 4 INPlll' MULTIPLEXER

Si z1

z1

14

15

'

D~al four input· multiplexer

Logic diagram

Fig. 4

6

zb

zb

2
1
Yee= PIN 16
GND=PIN8

Fig. 3*Planar is a patented Fairchild process.

FAI RCt-11 LCJ
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA; (415) 962-5011, TWX: 910-379-6435

SEMICONDUCTORA DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD -MEDIUM SCALE INTEGRATION 9309
FUNCTIONAL DESCRIPTION

The 9309 dual four input multiplexer is a member of the Fairchild family of compatible Medium Scale Integrated (MSI) digital building blocks. It
provides this family with the ability to select two bits of either data or control from up to four sources, in one package.
The 9309 dual four input multiplexer is the logical implementation of a two-pole four-position switch, with the position of the switch being set by the
logic levels supplied to the two select inputs. Both assertion and negation outputs are provided for both multiplexers. The logic equations for the
outputs are shown below:
Z1 = 101 • S1 .• S0 + 110 • S1 • S0 + 121 • S1 • S0 + 1.30 • S1 • S0
Zb = IOb • S1 • S0 + 11b • S1 • S0 + 12b • S1 • S0 + 13b • S1 • S0
A common use of the 9309 would be the moving of data from a group of registers to a common output buss. The particular register from which thedata came would be determined by the state of the select inputs.
TRUTH TABLE

SELECT INPUTS
So

sI

L
L
H
H
L
L
H
H

L
L
L
L
H
H
H
H

So

s,

L
L
H
H
L
L
H
H

L
L
L
L
H
H
H
H

INPUTS

1,.

'°L"

x
x

z.

z.
H
L
H
L
H
L
H
L

x
x
x
x
x
x

x
x

L
H

1,b

l2b

13b

zb

zb

x
x

x
x
x
x

x
x
x
x
x
x

L
H
L
H
L
H
L
H

H
L
H
L
H
L
H
L

L
H

x
x
x
x
x
x

'3•

x
x
x
x

L
H

'Ob

x
x
x
x

L
H
L
H
L
H
L
H

H

x
x
x
x
x
x

'2•

OUTPUTS

L
H

x
x
x
x

L
H

L
H

x
x

L
H

LOADING RULES(1U.L=1 TTµLgate input load)
INPUTSLOADINGloa, 1, •• 121• 13•'lob• I, b• l2b• l3b•
S0, S1

1 U.L

FANOUT Al LOGIC LEVEL
HIGH
LOW

OUTPUTS

20U.L
18U.L

z•• zbz•• zblOU.L.
9U.L.

L = low voltage level
H = high voltage level
X= either high or low logic level

TYPICAL INPUT AND OUTPUT CHARACTERISTICSVee
EOUIVALEIT CIRCUITOUTPUT CURRENT VERSUSOUTPUT VOLTAGE(OUTPUT HIGH)INPUT CURRENT· VERSUSINPUT VOLTAGE
2.0

211

l_: T

Ycc·S.OVLli:.
~'
J r~ is·<2S"ct::JrL-:r re :JI ~ c-"""'l_,,.cf".l--+---+--+---+--<+iboc:

t-+-'~..2.0l~o 1--1~i--1--+--+-+-+-+-+-t

·211

i

OUTPUT CURRENT VERSUSOUTPUT VOLTAGE.. (OUTPUT· LOW)

,.I-

~~~~'

,.L

~]·15"C·12S"C,_.,.........,_...--+--+-+-t--+---+-_,-8.0 t-ll--li--1--+-+-+-+-+-+-t

2.0

4.0

6.0

8,0

..,

·1.0

1.0

J.O

VIN· INPUIVOlTAGE ·VOLJS

Fig. 5

s.o

7.0

0

~
!:£..

n

L
211

...... ~k1~
15~ ~ 1-o-c.,,r.;i ,_c
12S"C~~-6.0

vz

_J

7__

l
,o

o.s

1.0

o.s

Your • OUTPUT VOLTAGE" VOi.TS

Fig. 6

3-52

Fig. 72.0

FAIRCHILD MEDIUM SGALE INTEGRATION 9309

ELECTRICAL CHARACTERISTICS* (TA= -55°C to +125°C, Vee= 5.0V ±10%) (Part No. UXX930951X)
LIMITS
SYMBOLCHARACTERISTICS

VoH

Output High Voltage

VOL

Output Low Voltage

VIH·
VIL
IF (all inputs)

Input High Voltage
Input Low Voltage
Input Load Current

IR (all inputs)

Input Leakage Current-55°C
MIN. MAX.

MIN.

2.4

2.4

+25°C
TYP. MAX.
2.7+125°C
MIN. MAX.

UNITSCONDITIONS

2.4

Volts

Vc/;b4.5V 10 H = -1.2 mA (Pins 1 & 15)
Vcc=4.5V 10 H = -1.08 mA (Pins 2 & 14)
Inputs at threshold voltages (V1Lor V1H)
as per truth table

0.4

Volts

Vee= 5.5V~uaranteed input low threshold for all inputs

..J..

IPDH
...:.. tpd+ (S 0 to Z0 )tpd- (S0 to Z0 )

0.4

2.0

0.21

1.7
0.8
-1.6

40

Vee Current
Switching Speed
Switching Speed

0.4

1.4

loL = 16.0 mA (Pins 1 & 15)
10 L = 14.4 mA (Pins 2 & 14)
Vcc=4.5V Im = 12.4 mA (Pins 1 & 15)
10 L = 11.2 mA (Pins 2 & 14)
Inputs at threshold voltages (V1Lor V1H)~s per truth table

0.9-1.1 -1.6

0.8

Volts
Volts

-1.6

mA

Vee= 5.5V
Input selected

15

60

60

µA

VR = 4.5V
Vee= 5.5V
Input not selected

30
24
24

40

.40

mA
ns
ns

Vee= 5.0V

32
32

Guaranteed input high threshold for all inputs
VF= 0.4V--"'.

All inputs hig~t'

Vee = 5.0 V, CL = 15 pF, See Figure 5•Pulse tested

ELECTRICAL CHARACTERISTICS* (TA= 0°C to +7S°C, Vee= 5.0 V ±S%) (Part No. UXX930959X)
LIMITS-"-

SYMBOLCHARACTERISTICS

0°C
MIN. MAX.

+25°C
MIN. TYP. MAX.

VoH

Output High Voltage

2.4

2.4

Vol

Output Low Voltage

VIH
VIL
IF (all inputs)

Input High Voltage

0.45

1.9

3.0

0.21

0.85

Input Load .current

-1.6

UNITS

2.4

Volts

0.45

0.45

1.6

1.8

Input Low Voltage+75°C
MIN. MAX.

0.85-" 1.0 --'1.6

0.85
-1.6

Volts

Volts
Volts

Input Leakage Current

15

60

43

Vee Current
Switching Speed
Switching Speed

~

30

43

24
24

32
32

•Pulse tested

3-53

Vee = 5.25 V Im= 16.0 mA (Pins 1 & 15)
10 L == 14.4 mA (Pins 2 & 14)
Vee= 4.75 V l()L = 14.1 mA (Pins 1 & 15)• 10 L = 12.7 mA (Pins 2 & 14)
Inputs at threshold voltages (V1Lor V1H)
as per truth table
Guaranteed input high threshold for all inputs
Guaranteed input low· threshold for all inputs
Vee= 5.25V
Input selected

60µA

Vee= 5.25V
VR = 4.5V
Input not selected

43mA

Vee= 5.0V

-

ns
ns

Vee= 5.0 V, CL= 15 pF, See Figure 5...:...

IPDH
tpd + (S0 to Z0 )tpc1 _ (S0 to Z0 )'Vee= 4.75 V 10 H = -1.2 mA (Pills 1 & 15)
Vee= 4.75 v 10 H = -1.08 mA (Pins 2 & 14)
Inputs at threshold voltages (V1Lor V1H)
as per truth table

mA

•'k/

IR (all inputs)

CONDITIONS

VF= 0.45V

All inputs high

FAIRCHILD MEDIUM SCALE. INTEGRATION 9309

SWITCHING WAVEFORMS

All input waveforms are output of TTµL 9000 series gates loaded with 15 pf. All outputs are loaded with the same capacitance (referred to as CL)
and only with capacitance.

Fig. 8 -tpd; So to Z.

tpd; S0 to Z.

tpd; lao to Z.

CONDITIONS
Pins 3, 12 GND.
Pin 11 =Yee

CONDITIONS
Pins 3, 12 GND.
Pin 11 =Yee

CONDITIONS
Pins 3, 13 :;= GND.

=

Yut•lo

WAVEFORMS

1.5V~1.5V[PM13l~tpd•~
yllllT.z ___/"1.!IY='

UV\___[Pll1151

SWITCHIN(; CHARACTERISTICS
TURN OFF DElAY TIME VERSUSAMBIENT TEMPERATURE!
(S. to Z.)

TURN ON DElAY TIME VERSUSTEMPERATURE(Soto Z.)25

(la. to Z.)

o._..__,___.__.__.__.__._,___,

oL--l---'--....L--'-......1---'---1-'---'-55

TURN OFF DElAY TIME VERSUSAMBIENT TEMPERATURE

125

m

25

TA· AJ.1BIENTlfMPERATURE • •e

-55

TA· AMBIENT TEMPERATURE· 'eFig. 9Fig. 10TURN ON DElAY TIME VERSUS. AMBIENT TEMPERATURETYRN OFF DElAY TIME VERSUSAMBIENT TEMPERATURE(la. to Z.)

·

fig.

(Soto Z.)u

TURN ON DElAY TIME VERSUS' AMBIENT TEMPERATURE<s.io Z.»

48

Yee ·5.ovm

25
TA ·AMBIENT lfMPERATURE • 'e

Yee· 5.o v~L • 15pF

CL• 15pF[L"ISb:, ""'+--

..._

MAX

"

-55

/

.i.1.-i""',1...-1'"""

IMX

001

"'-T"
0

L

25
TA ·AMBIENT lfMPERATURE • 'C

Fig. 12

-i--

_m

1••.

125

0

..

.L

v
OL--1---'--_.___.__.__.__..._,___,

m

-55

25

I

; TA•AMBIENTlfMPERATUR£-'e

TA· AMBIENT lfMl'ERATURE • 'e

Fig. 13

Fig. 14

3-54

-55

25

125

FAIRCHILD MEDIUM SCALE INTEGRATION 9309
APPLICATIONS~~--+_...,~~-+-~~~--1~~~~-+-4--~-+-~~~--1~~~~-+-4--~-+~~~--1~~~~~t--1~~----~~-+-~~~--1~~~~--~---+-----4----------+-----I'-------'

52-----.
S3

BIT a
OUT

Bil b
OUT

Fig. 12- MULTIPLEXING TWO BITS FROM SIXTEEN SOURCES
This diagram shows the interconnection of five 9309 dual four bit multiplexers to provide switching of two bits of datafrom one of sixteen words onto a two bit data buss. The selection of which word will be transferred to the buss is madeby the address supplied to the S0 , s,, S2 and S3 inputs. As an example: if twelve bit words are to be transferred to a
twelve bit buss, the above diagram would be repeated six times. Notice that the negative outputs are used at both levels
resulting in the assertion output (negation of the negation) at a higher speed due to the fact that the through delay isless on the negation output.
If the word selecting address is held in four TIµL flip flops (two dual packages) enough load capability is available toselect between sixteen, sixteen bit words.

ACCbMUUT6R OUTPUT

Fig. 13 -GENERAL PURPOSE ACCUMULATOR

A fast, general purpose accumulator for computer applications is capable of: 1) shift left; 2) add; 3) shift right and 4) complement operations. Only
three packages are required to construct two stages of the general purpose accumulator (Figure 1).
The D input capability of the 9022 is utilized here to allow each flip flop of the accumulator to accept the data as presented by the 9309 multiplexer.
Under the operation code instructions the multiplexer provides an input to the 9022 from: 1) adjacent stage to the right for a shift left operation;2) adjacent stage to the left for a shift right operation; 3) output of. adders for add operation and 4) Q outputs of 9022 for the complement operation. The operation code at the right of Figure 1 shows the instruction codes to perform the various operations.
The accumulator should be capable of 20 to 25 MHz operation.

3-55

FAIRCHILD MEDIUM SCALE INTEGRATION 9309
'cc

"""''

MiYIOlillliER

Fig. 14 -16·BIT PATTERN GENERATOR

This application illustrates the use of 9309 and 9020 in the design of one channel of a 16 bit pattern generator. Each channel requires Vz 9020,
1h 9002 and 21h 9309. Each channel consists of a switch serializer/pattern generator and resynchronizer sections with a modulo 16 binary countercommon to all channels.
The two least significant bits and two most significant bits of the counter control the first and second stages of multiplexing respectively. In thismanner four bits are multiplexed on each of the four lines from t~e firs.t stage to the second stage. Every four clock times a new input line containing
four multiplexed bits is selected by the second stage of the serializer thus serializing the 16 input bits from the switches.
The resynchronizer flip flop is used to eliminate decoding spikes.

•11---------1------,
I•• - - - - - - - - 1

15-------..

I•• - - - - - - - - 1
131---------1

I

121---------1

I

L _ -

-IGll~-- _J

llULTIVllRATllllS'• ....
9601

IETRICiGERABLE OIE·SHllTS

OPERATION CODE LIST
INSTR.UCTIQff

S0 S 1
0

0

SHIFf LEFT

1

0

·ADD

Q

1
1

SHIFT RIGHT

1

1:1="1",.

COMPL~MENT
L·~ .~o··;Fig.• 15 -NON·LINEAR COUNTER

The rate of the non-linear counter depends on the multivibrator clock frequency
selected under control of the three most significant bits cif the counter. This
makes the count rate a function of both the count value of counter and frequencyof clock multivibrator selected.
·
Clock multiplexing Is accomplished by a 9309 · dual 4·input multiplexer and one
9002 quad gate. Eight line segments representing clock rates of the multivibrators
may be adjusted ·in slope Iii approximate a non-linear function.
·

3-56

9310
MSI BCD DECADE COUNTERA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRIPTION - The 9310 is a high speed synchronous 8421 BCD decade counter. It is a synchronously presetable, multifunctional MSI building block useful in a large number of counting, digital
integration, and conversion applications. Several decades of synchronous operation are obtaina.ble with noexternal gating packages required through an internal carry look-ahead counting technique.

PHYSICAL DIMENSIONSDUAL IN-LINE PACKAGEFEATURES:• SYNCHRONOUS COUNTING AND PARALLEL ENTRY• DECODED TERMINAL COUNT• BUILT-IN CARRY CIRCUlm• TYPICAL POWER DISSIPATION OF 300 mW• THE INPUT/OUTPUT CHARACTERISTICS PROVIDE EASY INTERFACING WITH FAIRCHILD DTµL,
LPDTµL, AND TTµL FAMILIES (CCSL).
• ALL CERAMIC HERMmc 16 PIN DUAL IN-LINE PACKAGE AND FLAT PACKAGE• INPUT DIODE CLAMPING

L

·.oaI

ABSOWTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias.. Yee Pin .Potential to Ground Pin· Voltage Applied to Outputs for high output state
Input Voltage (D.C.)

MAX.

-'65°C to +150°C-55°C to +125°C-0.5Vto+7V-0.5 V to Yee value-0.5 Vto +5.5 V

ORDER INFORMATION ~. S~ify U6B9310XXX for 16-piri Dual In-Line Package, U3L9310XXX for i6-pin Flat
Package where XXX is 51X for the -55°C to +125°C temperature range, or 59X for the 0°C to 75°C
temperature range.

llOTI:
1. Lud1 ire intended tor Insertion in hOle rows on.300" centers. TbQ tr• purposely shipped with"posilive" (.3~, miuli1nment to t1eiliWte lnHrtlon.

FLAT PACKAGE.

LOGIC DIAGRAM

9 3

4

5 6

7
10

15

2
I

14 13 12 11

Yee= Pin 16
Gnil Pin8=

F=.A.I RCH I L.C
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011.• TWX: 910,:379-6435

3-57.SEMICtJNDUCTt:lA
A 01v1s10N OF FAIRCHILD CAMERA ANEi INSTRUMENT COR~RATIONFAIRCHILD MEDIUM. SCALE INTEGRATION • 9310
FUNCTIONAL DESCRIPTION - A clock buffer and inverter drives the four clocked RS master-slave flip flops in parallel, so that synchronous operation
is obtained. When the clock input (CP) is low, the slave is steady, but data can enter the master via the R and the S inputs. During the low to hightransition of CP, first the data inputs (R and S) are inhibited, so that a later change in the input data will not affect the master; secondly, the now
trapped information in the master is transferred to the slave and is reflected at the outputs. When the transfer is completed both the master and.the slave are steady as long as the clock input remains high, and regardless of the logic state at any other input to the device. During the high to
low transition of the clock input, first the transfer path from master to slave are inhibited, leaving the slave steady in its present state, secondly, thedata inputs (R and S) are enabled so that new data can enter the master. As a result of this synchronous operation higher clock frequency ispossible and much less external logic is required in most applications. Some restrictions are placed on the manner of selection. First, the transitionof CEP or CET from high to low or of PE from low to high may only be done when CP is high. The remaining transitions may be made by following
the setup and release times specified under "Switching Characteristics." The asynchronous MR clears the counter independent of any\other input.
Note: CE (count enable) = CEP • CET
TC= CET • Qo • Q1 • Q2 • Ql

LOADING RULE:SCCSL LOAD AND DRIVE FACTORS

TTµL LOAD AND DRIVE FACTORS

8/6.7
24/20
9 3 4 5 6

2 2/3 2/3 2/3 2/3

9 3 4

24/20

5 6

I

12/10 715 6

2
2

15 72/60

1 1:
1 14 13 12 11
12/10
72/60

6

6 6

6
Vee= Pin 16
Gnd =Pin 8

Vee= Pin 16
Gnd =Pin 8(1 U.L. = 1 TTµ~ input gate load)

ELECTRICAL CHARACTERISTICS (TA= -55°C to +125°C, Yee= 5.0 V ±10%)
LIMITS
SYMBOLCHARACTERISTICS-55°C
MIN. MAX.

+25°C
MIN. TYP. MAX.

+125°C
MIN. MAX.

YoH
VOL

Output High Voltage

2.4

2.4

2.4

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.8

0.9

0.8

Volts

IF

Input Load Current
MR, CEP
Input Load Current
CP, PE, CET
Input Load Current
Pa, P1, p2' P3Input Leakage Current
MR,CEP
Input Leakage Current
CP,PE,CET
Input Leakage Current
Pa, P1, p2' P3-1.6-1.0 -1.6

-1.6

mA

-3.2

-2.0 -3.2

-3.2

mA

-1.07

-0.7 -1.07

-1.07

mA

2 IF
%IF
IR
21R
%1R

0.4
2.0

2.7
0.2

0.4

l.7

0.4
1.4

UNITS
Volts

Yee= 4.5 V, 10 H = -0.36 mA

Volts

Yee= 5.5 V, 10 L = 9.6 mA
Yee= 4.5 v, IOL = 7.44 mA
Guaranteed input highthreshold for all inputs
Guaranteed input low
threshold for all inputs

Volts

60

10

60

60

µA

120

20

120

120

µA

40

7.0

40

40

µA

3-,58

CONDITIONS & COMMENTS

Yee= 5.5V
VF= 0.4V

Yee=5.5V
VR =4.5V

FAIRCHILD MEDIUM SCALE INTEGRATION'• 9310
ELECTRICAL CHARACTERISTICS (TA ... 0°C to +75°C, Vee ... s.o v :1::5%)
LIMITS
SYMBOLCHARACTERISTICS

0°C
MIN. MAX.

MIN.
2.4

UNITS

+25°C
+75°C
tvP. MAX. MIN. MAX.

VoH
Vol

Output High Voltage
Output Low Voltage

2.4

VIH

Input High Voltage

1.9

VIL

Input Low Voltage

0.85

0.85

0.85

Volts

IF

Input Load Current
MR, CEP
Input Load Current
CP,PE,CE'r
Input Load Current
P0, P1, P2, P3
Input Leaka~e Current
MR,CEP
Input Leakage Current
CP,PE,CET
Input Leakage Current
P0,P"P2,P3-1.6-1.0 -1.6

-1.6

mA

-3.2

-2.0 -3.2

-3.2

mA

-1.07

-0.1 -i.01

-1.07

rnA

21F
%IF
IR
2 IR
%1R

3.0

0.2

0.45

2.4
0.45

Volts
Volts

0.45

u

CONDITIONS & COMMENTS

=

Volts

1.6

60

10

60

60

p.A

120

20

120

120

p.A

40

7.0

40

40

µ.A

=. .
=

Yee• 4.75 V, loH
0.36 mA
Yee""' 5.25 v, 16L 9.6 mA
V<&_. 4.75 V, loL.., 8.5 mA
Guaranteed input highthreshold for all inputs
Guaranteed input low
threshold for all inputs

Vee= 5.25V
VF= 0.4 v

Vee== 5.25 V
VR ... 4.5v

SWITCHING CHARACTERISTICS (TA ... 25°C)
SYMBOLCHARACTERISTICS

tpd+ (Q)tpd_ (O°)

Tum-Off Delay
lum:On Delay
Tum~Off Delay for TC
Tutn·On Defay for TC
Set-Uiiilme for CE
Release Tin\e for CE
Set· Up Time for Data
Release Time for Data
Set-Up Time for PE
Release Time for PE
Turn-On Delay for MR
Propagation Delay for CET to TC

tP<l+ (TC)tpd- (TC)t. (SE)tr (CE)t.

trt, (PE)tr (PE)
tpa- (MR)
tP±

MIN.

tvl>.
20

15

35
20
14
12
18

l7
30

28
33
14

MAX.

UNITS

CONDITIONS & COMMENTS

ns
ns
ns

Vee= 5.QV
CL ... 15 pF(Fig. 1)

ns
ns
ns
ns
ns
ns
ns
ns
ns

Vee• 5.0V
CL = 15 pf (Fig.2)
Vee= 5.0V
CL== 15 pf(Fig. 3)
Vee ... 5.0 V, CL ... 15 pf (Fig. 4)
Vee.., 5.0 V1
15 pF (Fig. 5)

Ci. ...

SET-UP TIME: t, is defined as the minimum time required for the logic level to be present at the logic input prior to the clock transition from low
to high in order for the flip-flop(s) to respond.
RELEASE TIME: tr is defined as the maximum time allowed for the logic level to be ~resent at the logic input prior to the clock transition ftom low
to high in order for the flip·flop(s) not to respond.

3-59FAIRCHILD MEDIUM SCALE INTEGRATION • 9310
SWITCHING TIME WAVEFORMS
Fig. 1

Fig. 2-------1.5¥
II-j l--1,fCfJ

ls!Cf)--i ~
Cf

t

TC

I

·'

-------1.5¥-1•--t,1-ITCJ-------1--. '.\-1--------------------,

ao.=...::f----------uv---------1.5¥

Fig. 3~'·~r- -jr-1,

'•

1.5¥

I

I

I

I

CP
I

11IPEJ--j III-1 l--1,f

Pf)

I

1.5¥

Pf

•• -==========-+ ------ \-Fig. 5

Fig. 4-=\----1.5¥=f-\-1.5V'pd--1--1.5¥

---en

MR

TC

ANY Q

APPLICATIONS

TQ MORE....

SIGNIFICANTDECADES

cr~+----------------------------<o---------.

SYNCHRONOUS COUNTING SCHEME

3-60

9312
MSI EIGHT-INPUT MULTIPLEXERA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRIPTION - The 9312 is a monolithic, high speed, eight input digital multiplexer circuit. It
provides in one package the ability to select one bit of data from up to eight sources. The 9312 can be used
as a universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided. TTµL circuitry with active pullups on the outputs provides high speed, high fanout
operation and is compatible with all other members of the CCSL family of digital integrated circuits.

LOGIC SYMBOL

1011

12

13

14

15

1s17

,9312, I lllPUT llULTPlEXER

·13

z

Sz

FEATURES• MULTIFUNCTION CAPABILITY• 25 ns THROUGH DELAY• ON-CHIP SELECT LOGIC DECODING• FULLY BUFFERED COMPLEMENTARY OUTPUTS• THE INPUT/OUTPUT CHARACTERISTICS PROVIDE EASY INTERFACING WITH FAIRCHILD DTµL, LPDTµL,
TTµL, AND MSI FAMILIES (CCSL).
• INPUT CLAMP DIODES LIMIT HIGH SPEED TERMINATION EFFECTS.

14

z
15

Vee= PIN 16
GND=PIN8

Fig. 1

DUAL IN-LINE PACKAGE

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature-65°C to +150°C
Temperature (Ambient) Under Bias
-55°C to +125°C
Vcc Pin Potential to Ground Pin-0.5Vto+7V
Voltage applied to output when output is high0 V to +Vee value
Input Voltage (DC) (See Note 1)-0.5 V to +5.5 V
Input Current (DC) (See Note 1)-30 mA to +5 mA
Current into output when output is low+30mA
Note 1: Either Input Voltage limit or Input Current limit is sufficient to protect the inputs.

.1001
MIN.

I

r=

.llO
.090

L
I

023
MAX.

ORDER INFORMATION - Specify U6B9312XXX for 16-pin Dual In-Line package or U3L9312XXX for 16-pin
Flatpak, where XXX is 51X for the -55°C to +125°C temperature range, or 59X for the 0°C to +75°C
temperature range.

NOTE '
Leads are intended for insertion m hole rows on.300" centers. They are purposely shipped with.. pos1t1ve" (.375) misalignment to. factlitate insertion.

Fig. 2
FLAT PACKAGE

409
.371

I

020
.015

j_

!1

1-igg~TOP VIEW

1--:~~ __j

0050

o~~
'

I

075
050

l

r---:~~3~

Fig. 3FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-61

A DIVISION .Of FAIRCHILD CAME~:!) .AND INSTRUMENT CORPORATIONFAIRCHILD MEDIUM SCALE INTEGRATION 9312
FUNCTIONAL DESCRIPTION - The 9312 is a logical implementation of a single pole - 8 position switch with the switch position controlled by the stateof three select inputs, S0 , Sp S2. Both assertion and negation outputs are provided. The enable input (E) is active low. When it is not activated thenegation output is high and the assertion output is low regardless of all other inputs. The logic function provided at the output is:Z= E•(l •S •S •S2 + 1 1 •S0 ~S 1 •S2 + 12•S ·SrS2 + 13•S •S •S2 + 14•S •S •S2 +15•S •S •S2 +1 •S •S •S2 + 1 •S •S •S2).
0

0

1

0

0

1

0

1

0

1

6

0

1

7

0

1

The 9312 provides the ability, in one package, to select from eight sources of data or control information. By proper manipulation of the inputs, the9312 can provide any logic function of four variables and its negation. Thus any number of random topic elements used to generate unusual truth
tables can be replaced by one 9312.
TRUTH TABLE

LOADING 8ULES

17

z z

x x x x x x x x x x x
L L x x x x x x x
L H x x x x x x x
H x L x. x x x x x
H x 1:1 x x x x x x
L x x L x x x x x
L x x H x x x x x
H x x x L x x x x
H x x x H x x x x
L x x x x L x x x
L x x x x H x x x
H x x x x x L x x
H x x x x x H x x
L x x x x x x L x
L x x x x x x H x
H x x x x x x x L
H x x x x x x x H

H L
H L
L H
H L
L H
H L
L H
1:1 L
L H
H L
L H
H L
L H
H L
L H
H L
L H

s,

E S2

1,

lo

So

12

13

15

14

lb

H
L L L
L L L
L L L
L L .L
L L H
L L H
L L H
L L H
L H L
L H L
L H L
L H L
L H H
L: H H
L H H
L H H

H

L
X

INPUTSLOADINGAll Inputs

1 U.L.

OUTPUTSFAN-OUTzz

High State

Low State

18
20

9
10

Fig. 4

1U.L.=1 nµL Unit Load
1 U.L. is defined by the entries=Hip voltage level=Level does not 1ffact output

IR and IF in the table on page 3.

=Low voltage level

Fig. 5TYPICAL INPUT AND OUTPUT CHARACTERISTICSOUTPUT HIGH
EQUIVALENT CIRCUIT.EQUIVALENT INPUT CIRCUITOUTPUT LOW
EQUIVALENT CIRCUIT.-----------,__-n Vee
80 Cl

IN

NOT

10

SELECIED·•JT°OUT

SELE~ED. 1 ~0.3V

4K'---+--o OUTOUTPUT CURRENT VERSUSOUTPUT VOLTAGE(OUTPUT HIGH)INPUT CURRENT VERSUSINPUT VOLTAGE
2.0

125°C~~~-2.0 f--~

~ -55°C'tr~

OUTPUT CURRENT VERSUSOUTPUT VOLTAGE(OUTPUT LOW)rJ

INPUT NOT SELECTED
15°

'~r
-- --

<

\Q°c

E

SELECTED 25°C

U-4.0

i

'!:1.0
-8.0

-10
-2.0

2.0

4.0

6,0

8.0

-~1'-.0--1._1._.-0__._J._.o__._5+-'.o--'~,.o

VIN· INPUT VOLTAGE· VOLTS

VouT - OUJPUT VOLTAGE - VOLTS

Your· OUTPUT VOLTAGE - VOLTS

Fig. 6

Fig. 7

Fig. 83-62

FAIRCHILD ME[)IUM SCALE INTEGRATION 9312
ELECTRICAL CHARACTERISTICS* (TA::::;: -55°C to +125°C, Yee= 5.0 V ±10%) (Part No. UXX931251X)
LIMITS

0SYMBOLCHARACTERISTICS-55°C
MIN. MAX.

+25°C
MIN. TYP. MAX.

+125°C
MIN. MAX.

UNITS

YoH

Output High Voltage

2.4

2.4

2.4

Volts

vOL ..

Yee =4.5V 10 H = -1.2 mA (Pinl5)
Yee=4.5V 10 H = -1.08 mA (Pin 14)
Inputs at threshold voltages (V 1L or V1H)
as per truth table

Output Low Voltage

Volts

VIH
VIL
I~ (all inputs)

Input High Voltage
Input Lpw Voltage
Input Load Current

10 L = 16.0 mA (Pin 15)
10 L = 14.4 mA (Pinl4)
Yec=4.5V Im= 12.4 mA (Pinl5)
Im= 11.2 mA (Pinl4)
Inputs at threshold voltages (V1Lor V1H)
as per truth table
Guaranteed input high threshold for all inputs
Guaranteed input low threshold for all inputs
VF= 0.4 V.
Yee=5.5V

IR (all inputs)

Input Leakage Current

IPDH
tpd + (S0 to Z)
tpd- (S0 to Z)

Yee Current
Switching Speed
Switching Speed

0.21

0.4

2.0

2.7.

0.4

1.7

0.4

1.4
0.9
-1.1 -1.6-0.85 -1.24
15
60

0.8
-1.6
-1.24

40

27
23
25

40
34
36

Volts
0.8
Volts
-1.6 mA-1.24 mA
µA
60
40

mA
ns
ns

CONDITIONS

Yee=5.5V

J

Yee=4.5V } Input Selected
VR = 4.5V
Yee= 5.5V· Input not selected
Yee= 5.0V
Yee= 5.0 V, See Page 4
CL= 15 pf

Pulse linted

ELECTRICAL CHARACTERISTICS* (TA= 0°C to +75°C, Yee= 5.0 V ±5%) (Part No. UXX931259X)
LIMITS

0SYMBOLCHARACTERISTICS

0°C
MIN. MAX.

+25°C
MIN. TYP. MAX.

YoH

Output High Voltage

2.4

2.4

VOL

Output Low Voltage

VIH
VIL
IF (all inputs)

Input High Voltage
Input Low Voltage
Input Load Current

IR (all inputs)

Input Leakage Current

IPDH
tpd + (S0 to Z)
tpd- (S0 to Z)

Vee Current
Switching Speed
Switching Speed ·

UNITS

2.4

Volts

Yee =4.75V 10 H = -1.2 mA (Pinl5)
Vee =4.75V 10 H = -1.08 mA (Pin 14)
Inputs at threshold voltages (V1Lor V1H)
as per truth table

0.45

Volts

0.85
-1.0 -1.6-0.91 -1.41
15
60

0.85
-1.6
-1.41
60

Vo.Its
Volts
mA
mA
µA

10 L = 16.0 mA (Pinl5)
10 L = 14.4 mA (Pin 14)
Vee=4.75V 10 L = 14.1 mA (Pinl5)
Im = 12.7 mA (Pin 14)
Inputs at threshold voltages (V1L or V1H)
as per truth table
Guaranteed input high threshold for all inputs
Guaranteed input low threshold for all inputs

27
23
25

43

3.0

0.21

0.45

1.9

+75°C
MIN. MAX.

0.45

1.8
0.85
-1.6
-1.41

43

1.6

43

34

mA
ns

36

.ns

Pulse linted

3~63

CONDITIONS

Vee= 5.25V

Vee= 5.25 v
Vee= 4.75V

J VF= 0.45 v
1 Input Selected

VR =4.5V
Vee= 5.25V
Input not selected
Yee= 5.0V
Vee = 5.0 V, See Page 4
CL= 15 pf

FAIRCHILD MEDIUM SCALE INTEGRATION 9312
A. C. CHARACTERISTICS
A.C. CHARACTERISTics·All measurements are made with Vee= 5.0 V applied to pin 16 and with pin 8 grounded. The active input is driven by a 9002 TTµL gate with theoutput loaded with 15 pf. Both outputs of the 9312 are loaded with 15 pf.

tpd: 10 to Z

1.sv-f----=\-1.5v=I t:: -l

INPUT IPIN 11)

lpd+

1.5¥--OUTPUT (Pit 15)+

l.5V-f----=\--1.5V
INPUT (PIN 1 )OUTPUT (PIN 14I\-1.5¥=TURN Of'F DELAY VERSUSAMBIENT TEMPERATURE;
S. to l

1.5V

TURN ON DELAY VERSUSAMBIENT TEMPERATURE;
loto ZTURN OFF DELAY VERSUSAMBIENT TEMPERATURE;
I.to Zs. to Z-~ JO 'i-J

f-\

Other Conditions: Pins 8, 10, 11, 12; 13 ::: Gnd
Pin 16 =Vee

TURN ON DELAY VERSUSAMBIENT TEMPERATURE;!Sii!: «> i-=+.......,..,.+i--..--+-f-+-1t-.
~-+~--+j--'!--:1==-t!!i-l lpd+ I=

lpd-r-

1.5V

Other Conditions: Pins 1, 8, 10, 12, 13 Gnd
Pin 2 =Vee through 1.0 k!ll>ln 16 =Vee~=i

lpd-r-

50~~ «> "-±:::-+--+--+--+-t""'1H'--t--i,.........._
I rMi.I .-1".,......+-""~ JO f"">-o"'-::t:+t-.--f"-"11-1-~Pt-J.....--1-t""""'""--t--i
NN"' 20 l-'-+-+-+--+--+-'-'+--t-t--1

i 10 l:,.......,:E;f;l;;;b;~M~!!!l.~:E=t::1~ 20 Nt--+-+--+--+--Ml+-+--+i.---+-r:::.-1

j.101-'-+--+-+--+--+~--t-l"--lo..._.....__._....__..._.......,_..__._.___,•

o~~~~~~~~-~m

ZS
TA• AMBIENTTEMPERAfURE • °C

i:!S

ZS

•SS

m

ZS
TA· AMBIENT TEMPERATURE· °C

TA· AMBIENT TEMPERATURE• °C

Fig. 10

Fig. 11

Fig. 12Fig. 9-_-I--~""'""""--"\. ::. ___=i---1 r-'=- -fllPUT(PIN 10) - - -----

lllPut (Pill 11)

tpd-

,pd.

OUfi'UT (PIN 14)

OUTPUT (PIN 141
Other Conditions: Pins 1, 8, 10, 12, l3 = Gnd
Pin 2 ::: Vee through 1.0 k!lPin 16 =Vee

z

=

=

TURN OFF DELAY VERSUSAMBIENT TEMPERATURE;

So totVee• S.DV
Cl•I!pFJ.

\-·

Other Conditions: Pins 8, 11, 12, 13 Gnd
Pin 1 Vee through 2.0 k!lPin 16 =Vee

TURN ON DELAY VERSUSAMBIENT rEMPERATURE;

TURN OFF DELAY VERSUSAMBIENT TEMPERATURE;
S. to
so

m

ZS

\A· AMBIENT TEMPERATURE· °C

TURN ON DELAY VERSUSAMBIENT TEMPERATURE;
E toZ

Etoz

Vee • S.O+-V--+--t-t--+--"--+--+---'lCl • ISpF

Vee· s.ov

Vee· s.ov

cl· 1spF

Cl 0 15pF~ lD

1-'-+--+--+--+---+-t-·---t-t--i~~ *> ,__.,_.....+--+---+--1'--+---t-!--'-'I

«>

~ lD

!!i

I 20
;;;
Iii ID

.ff

31. 0
"ll

-MAX

(p ......-i

P7

./'!

~

~ 30!-=~k-+--+--+--+-+--+-1---1
~

~

MM

_.)..-

~

JN

bd

~r--

J;.

t--1

1~

MAi

...- v

TYP-I.......,_

l,...d--.;.....

_ni

_Mli

MIN

zs

o~~~~~~~~-~

125

-55

ZS

12!

0

ZS

12S

·SS

ZS

TA· AMBIENT TEMPERATURE· °C

TA· AMBIENT TEMPERATURE· °C

TA• AMBIENT TEMPERATURE· 'C

TA· AMBIENT TEMPERATURE - °C

Fig. 13

Fig. 14

Fig. 15

Fig. 163-64

125

FAIRCHILD MEDIUM SCALE INTEGRATION 9312
APPLICATIONSA MULTI-PORT MEMORY MODULE.
The four bit by eight word multi-port memory module shown in the below diagram uses only thirteen MSI packages; four 9308 24 pin dual four bit
latches, eight 9312 eight input multiplexers, and one 9301 one-out-of-ten decoder.
The module as shown is capable of simultaneously reading from two independently specified locations and writing into a third independently selected
location. The necessary enables are provided so that a number of these modules may be connected together to produce a larger memory. As an example
a sixteen bit by sixty-four word memory would require thirty-two of the modules shown below.
By connecting this type of memory to a function generator unit, a processor could be constructed that would e~ecute three address instructions at avery high speed on the data contained in this type of memory. In order to utilize the speed of the memory the instructions would also have to becontained in fast semiconductor memory.

WRITE
DATA

rr

WRITE

DllES
ADI

MOOULENA~BLE

I ..,,/10_'o'1"2"3WRITE
ST RD BE

ADDRESS A

v'IV
~

,,_

I

1123411711

rr'i

:L~

WORD.
STORAGE

N &'I-&'j!
... ~..• .I --1t.:>-6... ~ '*--

.....
I

*

- ,,.

-- ~!N___..,
~L

I b--

~

i ::t - ...,, i ......t - -- ;5............

~~

&'

-

~

• l..1b--

&'; -

BIT

""'°'~~....--- 5~*_.,,. Mz... Iii .rt--

II

BIT 3

Z"N

... i ... ~

:)I

I

,a

'"'

7'=-;;'MODULE ENABLE

WORD

-

7

ADORESS I

__
A

"I
~L

0-7

~

:)II

M5

,,.

MODULE ENAILE

4... §.rt--.....I

IP--1-+-1-+--- BIT 2......t - -

..)ti

-

I b--

II

..

~
r-N&j

&'

! .st--.... .i. ..f"'l_..,____

1"11"'--=i2&' - '"I&'~.rt-......t - -.. i •I t>II......-1&' N ...
&' !!

~

...

"1--

.. i .rr-.
II

I 1b--............
G - ..

0.......~~.rl--,, ...
.)I• I I b--.--..---'

~

.,,_

M1

- ,,.
- ~L
- ..!';:- """=
....

:L
"'

BIT

*

I0--1-+-I-+--- BIT 1

~~

----

L - - - ,,_Mo

,,.

:L

"I
·~L

.

BIT 0

*

Z"N

..,!i

-to1:r...

..

11··~

Fig. 17

3-65•AH Multlplenr connections are
slmllir ta Mo and Ma wtth Inputs ta Mo and Mo being theQo outputs of the lllll:hes, M1
and M1 Inputs being the Q1 out·
puts of tha lllll:h, Mz and Mz
Inputs being Qz outputs of thelatch, etc:.

BIT D

FAIRCHILD MEDIUM SCALE INTEGRATION 9312
APPLICATIONS
3 BIT COMPARATOR
Three bits of data to be compared are supplied to the address and select inputs of the 9301 and 9312 respectively. If A0, A1, Av and B0, B 1, B2
compare, the mutually exclusive active low output of the 9301 1/10 decoder and the selected input of the 9312 multiplexer will be coincidental and
COMPARE OUT will be high. The COMPARE ENABLE must be low to permit compare operation.

INTERCONNECTION DIAGRAM

3 BIT COMPARATOR

FOR 9 BITS-- -- -B

r::--:==::r----1-" sr.:;__~----f ~ ~ -COMPARE ENABLE
TO NEXT STAGE

p--~----1-" ~i::------:-..----f ,. i -A

B

COMPARE OUT

Fig. 18

IMPLEMENTING ANY FOUR-VARIABLE .BOOLEAN FUNCTION
The 9312 eight input multiplexer can (in addition to performing its nominal function) produce any Boolean function of four variables without any
additional elements if both the assertion and negation of one of the variables are present. If an assertion and negation are not present, one inverter
may be required.
The procedure for implementing a. four-variable function, along with an example, is shown in the attached diagram. First, consider the function interms of a Karnaugh map. If the Q0 , Q1 and Q2 variable are connected to the S0 , S1 and S2 inputs of the 9312 then the Karnaugh map will be split,
as shown, into eight sections, with each section corresponding to an input to the 9312. In order to implement the function each input of the 9312
is connected to one of the following four signals: ground, Vee• the assertion, or negation of the fourth variable.
The contents of the two squares associated with an input, on the Karnaugh map, determine which connection is made to that input. If both squares .
contain a zero, ground should be connected to the input; if both squares contain a one, the input should be connected to Vee· If the two squares
contain a one and a zero then either the assertion or negation of the fourth variable will be required to implement the function. If the single one
is located in the square associated with the assertion of the fourth variable then the assertion of the assertion of the fourth varia~le is connectedto that input, and vice versa.
Shown in the illustration below is a 9312 decoding the condition of a 9300, producing a one output whenever the register contains two or moretransitions. The truth table, Karnaugh map and the connection to the 9312 for this function are also shown in the illustration.
In many applications, using the 9312 to implement general logic functions of four variables will result in a sizeable reduction in package count.
In many cases use of the 9312 with additional gates to produce functions of more than four variables will also reduce the package count.
The concept of using the 9312 eight input-multiplexer as a general logic function generator is described by S. S. Yau and C. K. Tang of Northwestern University in a paper presented at the 1968 Spring Joint Computer Conference in Atlantic City, New Jersey.

REQ'EO.

REQ'ED.
INPUT CONNECTN.

INPUT CONNECT'N.
Oo•cceoo, Q2 ~ F1
0

0

0

0

0

0

0

0

1

0

0

0

1

0

,

0

0

1

1

0

0

1

0 0

1

0

1

0

1

1

0

1

1

0

1
0

0

1

1

,

1 0

0

0

0

0

1

,

1 0

1

0
1

1 0
1

0

1

1

1

1

1

0

0

0

1

1

0

1

1

1

1

1 0

0

1

1

1

0

1

TRUTH TABLE

0,

Ql

0

1

1

0 Q3

1 0

0

0

1

1

0

1
0 03

0

1

0

,

0

Q3

Q2
0

02

Qo

Q2

13 'GNO

0

o,

Qo

Qo

Io 'GNO

Qo

Io

13'

1

KARNAUGH MAP OF
FOUR VARIABLE FUNCTION.

Ql

Qi
1

Q3

0

Q3

0
Q2

Q2

Co
oo
o, ]3

Ql

Ql

11 Is l2t-

13

0
1
Q3

0 Q3

03

1

I, ]5 14 lot-

Q2

Q2

Qo

02
MULTIPLEXERINPUT MAP FOR
s, 'Ql' 52'Q2

Co

Io

Qo

Io

13

1
Ql

Ql

5c'Oo·

1

1

Q3

Q3

1

02

Fig. 19

3-66

FROM THE KARNAUGH MAP OF THE DESIRED FUNCTION
Io-17 CONNECTIONS CAN BE DETERMINED.

Q2

9316
MSI 4-BIT BINARY COUNTERA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTPHYSICAL DIMENSIONS

GENERAL DESCRIPTION -'- The 9316 is a high speed synchronous 4-bit binary decade counter. It is asynchronously presetable, multifunctional MSI building block useful in a large number of counting, digital
integration, and conversion applications. Several stages of synchronous operation are obtainable with noexternal gating packages required through an internal carry look-ahead counting technique.

DUAL IN-LINE PACKAGEFEATURES:• SYNCHRONOUS COUNTING AND PARALLEL ENTRY• DECODED TERMINAL COUNT• BUILT-IN CARRY CIRCUlm• TYPICAL POWER DISSIPATION OF 300 mW· • THE INPUT/OUTPUT CHARACTERISTICS PROYID[ EASY INTERFACING WITH FAIRCHILD DTµL,
LPDTµL, AND nµL FAMILIES (CCSL).
• ALL CERAMIC HERMETIC 16 PIN DUAL IN~LINE PACKAGE AND FLAT PACKAGE• INPUT DIODE CLAMPINGL

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Vcc Pin Potential to Ground Pin
Voltage Applied ·to Outputs for high output state
Input Voltage (D.C.)-65°C to +1so 0 c-55°C to +125°C-0.SVto +7V-0.5 Vto Vee value-0.5 Vto +5.5 V

'

.023
MAX.

llOTEI
1. Leads are intended tor insertion in hole rows on.300" centen. They are purposely shipped with"positive" (.375) misali1nment to f1cilit1te insertion.

ORDER INFORMATION - Specify U6B9316XXX for 16-pin Dual ln:Line Package, U3L9316XXX for 16-pin
Flat Package where XXX is 51X for the -55°C to +125°C temperature range, or 59X for the 0°C to 75°C
temperature range.

FLAT PACKAGELOGIC DIAGRAM
I •

9

3

4

5

6
.020
.015

7
10
2

Po

P1

P2

9316

a,

L

TC

0

IL

P3

15

.0050

0

a
.350 .....,.....
' -TOP_V_IEW
_

_,

.200

o+:=~
.2a3
I
.---.247---l

1 14 13 12 II

Vee= Pin 16
Gnd= Pin8

F=AIRCHIL.CJ ,,SEMICONDUCTOR.313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-67

A DIVISION OF FAIRCHILD CAMERA ANO. tNS'fRUMENT CORPORATIONFAIRCHILD. MEDIUM SCALE ·INTEGRATION • 9316
FUNCTIONAL DESCRIPTION - A clock buffer and inverter drives the four clocked RS master-slave flip flops in parallel, so that synchronous operation
is obtained. When the clock input (CP) is low, the slave is steady, but data can enter the master via the R and the S inputs. During the low to hightransition of CP, first the data inputs (R and S) are inhibited, so that a later change in the input data will not affect the master; secondly, the now
trapped information in the master is transferred to the slave and is reflected at the outputs. When the transfer is completed both the master andthe slave are steady as long as the clock input remains high, and regardless of the logic state at any other input to the device. During the high to
low transition of the clock input, first the transfer path from master to slave are inhibited, leaving the slave steady in its present state, secondly, thedata inputs (R and S) are enabled so that new data can enter the master.. As a result of this synchronous operation higher clock frequency ispossible and much less external logic is required in most applications. Some restrictions are placed on the manner of selection. First, the transitionof CEP or CET from high to low or of PE from low to high may only be done when CP is high. The remaining transitions may be made by following
the setup and release times specified u'nder "Switching Characteristics." The asynchronous MR clears the counter independent of any other input.
Note: CE (count enable) = CEP • CET
TC= CET • Q0 • Q1 • Q2 • Q3

LOADING RULES

TTµL LOAD AND DRIVE FACTORSCCSL LOAD AND DRIVE FACTORS

8/6.7
24/20
9 3 4 56

2 2/3 2/3 2/3 2/3
9

24/20

3 4

5

6

1

12/10 71 1~

2
2

15 72/60

1 14 13 12 11
12/10
72/60
Vee= Pin 16
Gnd =Pins

Vee= Pin 16
Gnd =Pin 8(1 U.L. = 1 TTµL input gate load)

ELECTRICAL CHARACTERISTICS (TA= -55°C to +125°C, Yee= 5.0 v ±10%)
LIMITS
SYMBOLCHARACTERISTICS-55°c
MIN. MAX.

+25°c
MIN. TYP. MAX.

+125°cMIN. MAX.

UNITS

VoH
VOL

Output High Voltage

2.4

2.4

2.4

Volts

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.8

0.9

0.8

Volts

IF

Input Load Current
MR, CEP-1.6-1.0 -1.6

-1.6

mA

2 IF

Input Load Current
CP, PE, CET-3.2-2.0 -3.2

-3.2

mA

%IF

Input Load Current
Pa, p" P2, P3
Input Leakage Current
MR, CEP
Input Leakage Current
CP, PE, CET
In put Leakage Current
Pa, p" p2' P3-1.07-0.7 -1.07

-1.07

mA

IR
I

2fR
%1R

0.4
2.0

2.7
0.2

0.4

1.7

-0.4
1.4

Volts
Volts

60

10

60

60

µA

120

20

120

120

µA

40

7.0

40

40

µA

I

3-68

CONDITIONS & COMMENTS
Vee = 4.5 V, 10 H = -0.36 mA. Vee = 5.5 V, Im= 9.6 mA
Yee = 4.5 V, IOL = 7.44 mA
Guaranteed input highthreshold for all inputs
Guaranteed input low
threshold for all inputs

Vee= 5.5V
VF= 0.4 v

Vee= 5.5V
VR = 4.5 v

FAIRCHILD MEDIUM SCALE INTEGRATION • 9316
ELECTRICAL CHARACTERISTICS (TA= 0°C to +75°C, Vee= 5.0 V ±5%)
LIMITS
SYMBOLCHARACTERISTICS

0°C
MIN. MAX.

+25°C
MIN. TYP. MAX.

+75°C
MIN. MAX.

VOH

Output High Voltage

2.4

2.4

2.4

VOL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.85

0.85

IF

lnp1.1t Load Current
MR, CEP

-1.6

2 IF

Input Load Current
CP, PE, CET%IFCONDITIONS & COMMENTS

UNITS
Volts

Vee= 4.75 V, 10 H = -0.36 mA

Volts

Vee= 5.25 V, 10 L = 9.6 mA
Vee= 4.75 V, IOL = 8.5 mA

Volts

Guaranteed input highthreshold for all inputs

0.85

Volts

Guaranteed input low
threshold for all inputs-1.0 -1.6

-1.6

mA

-3.2

-2.0 -3.2

-3.2

mA

Input Load Current
P0, Pp P2, P3-1.07-0.7 -1.07

-1.07

mA

IR

Input Leakage Current
MR, CEP

60

10

60

60

µA

21R

Input Leakage Current
CP,PE,CET

120

20

120

120

µA

%1R

Input Leakage Current
P0,PpP2,P 3

40

7.0

40

40

µA

0.45
1.9

3.0
0.2

0.45

0.45

1.8

1.6

Yee= 5.25 V
VF= 0.4 v

Vee= 5.25 V
VR = 4.5 v-;-

SWITCHING CHARACTERISTICS (TA = 25°C)
SYMBOLCHARACTERISTICS

tpd+ (Q)

Turn.Off Delay20ns

tpd- (Q)

Turn-On Delay

15

ns

MIN.

TYP.

MAX.

UNITS

CONDITIONS & COMMENTS
Vee= 5.0V
CL= 15 pF(Fig. 1)

tpci+ (TC)

Turn-Off Delay for TC

35

ns

tpd- (TC)t, (SE)

Turn-On Delay for TC

20

ns

Set-Up Time for CE

14nst, (CE)

Reliiase Time for CE

12

ns

t,

Set-Up Time for Data

18

ns

t,
t, (PE)

Release Time for Data

17

ns

Set-Up Time for PE

30

nst, (PE)

Release Time for PE

28

ns

tpci- (MR)T1.1rn-On Delay for MR

33

ns

Vee= 5.0 V, CL= 15 pF (Fig. 4)

tP±

Propagation Delay for CET to TC

14

ns

Vee= 5.0 V, CL= 15 pF (Fig. 5)

Vee= 5.0V
CL = 15 pF (Fig.2)
Vee= 5.0V
CL= 15 pF(Fig. 3)

SET-UP TIME: t, is defined as the minimum time required for the logic level to be present at the logic input prior to the clock transition from low
to high in order for the flip-flop(s) to respond,
RELEASE TIME: t, is defined as the maximum time allowed for the logic level to be present at the logic input prior to the clock transition from low
to high in order for the flip-flop(s) not to respond.

3-69FAIRCHILD MEDIUM SCALE INTEGRATION • 9316
SWITCHING TIME WAVEFORMS
Fig. 1

Fig. 2___________--i,,_,rtpd-IQol

1--tr!CEJ--------1.5Y

CEt . ·,.,

tpd + ITC)
TC-------1.SY
I---tpd-ITCJ

Qo~ - - - - - - - - - - - 1 . 5 V------- f --- ~. . --..-._============::::::::::::1.5V.
I,-

Fig. 3

Po""""--========::::::::::::;;:::::::::::::._··~ - - - - 1 . 5 Y
is_.j~ r-tr

rI

CP
.

I

-j~t,IPEJ
I

PE-----------UVOo-===========...J+ ------- =\- - - 1 . 5 Y

Fig. 4-=\-.- ~ -.-.-

Fig. 5l.5V~---\-i.5v..- tpd-_.I'-----CET

MR

ANY Q

TC

APPLICATIONS

9316

TC

9316

9316

TC

I----

TO MORESIGNIFICANT
STAGES

CP--------------~--------------------<9----------.

SYNCHRbNOUS COUNTING SCHEME

TRANSISTOR~TRANSISTOR MICROLOGIC®

INTEGRATED Cl.R.CUITSA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTMILITARY TEMPERATURE RANGE: -55°C to +125°C

duces the ringing which can result from long lines and impedance mismatches. The binary elements are of a JK, DC master slave design and will
toggle at 40 MHz, except for the 9000 element. The .9000 has capacitors
purposely incorporated in the design to increase its set-up time and provide
it with considerable immunity to long clock skew. Due to the longer set-up
time the 9000 toggle frequency is 20 MHz. A common JK input is incorporated on all binary elements to provide data entry inhibit/enable. The input
to the clock on each element is buffered to reduce the clock input loading.

GENERAL DESCRIPTION.

The Fairchild 9000 Series of 1TµL circuits is designed to be used in any
digital system where good noise immunity, high speed, medium power andhigh fan-out performance is required. The line is characterized by a broad
number of functions available in a variety of packages. The basic elementsof the family are active low level output AND gates commonly known as
NANO gates.
Typical high level noise immunity of every device in the family is 1.9 V andtypical low level noise immunity is 0.9 V. Worst case immunity is 400 mVover the entire temperature range. Power dissipation is typically 11 mW pergate function at a 50% duty cycle, and the average propagation delay is
7 nanoseconds per gate function. A single 5 V ± 10 per cent power supply isused with the circuits.

The Vee and ground terminals of all devices are located on diagonal cornersof the package which allows two degrees of freedom in routing of power andground leads on the PC boards. Special care has been taken in establishing
pin-outs for the flip-flop so as to minimize cross-overs when laying out
common dynamic functions with these elements. Simple loading rules areincorporated so that the fan-in and fan-out capability of each device will bequickly established.

The gates were designed to provide low output impedance in both high andlow states which results in good capacitive drive capability and good im·munity to crosstalk. The output impedance in the low state is about 10 ohms

The $000 series lTµL is part of the CCSL family and is compatible with allother Fairchild DTµL, Low Power DTµL and MSI devices as well as the more
complex functions which will be available in the future.

and in the high state, about 20 ohms. To further enhance noi5e immunity,
all inputs of all devices incorporate diode clamps which considerably re-

TABLE OF CONTENTS

Page

Page

ABSOLUTE MAXIMUM RATINGS, LOGIC DIAGRAMS ..................................2 • 3

AND-OR-INVERT GATES and EXTENDER ....................................................& • 109005 Dual 2-2-input AND-OR-INVERT Gate
one half extendable
9008 Single Extendable 2-2·2·3 AND-OR-INVERT Gate
9006 Dual 4-input OR Extender

Explanation of Loading Rules andprovisions for Unused Inputs

NANO GATES and HEX INVERTER ................................................................4 • 5

JK FLIP-FLOPS ......•...................................................................................11 • 16

9002 Quad 2-input gate
9003 Triple 3 -input gate
9004 Dual 4-input gate
9007 Single 8 -input gate
9016 Hex Inverter

9000 JK Flip-Flop9001 JK Flip-Flop
9020 Dual JK Flip-Aop
9022 Dual JK Flip-Flop

APPLICATIONS ................................................................................................. .17
ORDER AND PACKAGE INFORMATION ............................................................ 18

NAND BUFFER ..............................................................................................& • 79009 Dual 4-input buffer

l=AI RCH I L.C>
.SEMICDNDUCTD[R313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA~ (415) 962-5011, TWX: 9.10-379-6435

3-71

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD TRANSISTOR~TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
9000 SERIES TTµL INTEGRATED CIRCUITSNANO GATES

9002

9016
2
3

9003
3

4
4

5

6

5

6

9

8

9
10

8

12
13

II

II

10

13

12

1
2
13
3
4

1

I
2

5
9
10
12
13

9009

9007

6

2

6

4

5

4
10
II
12
13

8

8.

·.

BUFFER

9004

4

6

5
9
10
II

NANO GATES

..

12

8

9
10
12
13

8

AND·OR·INVERT GATES AND EXTENDER

9005
1
13

9
10

13
1
2
3

13
I

8
_,........__.__ II EMIT.
12COLL.

2
3
4
5

9006

9008

2
3

8
II EMIT.
12COLL.

9
10
6

4
5
6

4
5
6

8

Vee= Pin 14
Gnd =Pin 7

12COLL.
11 EMIT.

9COLL.
lOEMIT.

(extender for use with 9005 & 9008)

ABSOLUTE MAl(IMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Vee Pin Potential to Ground (See Note 1)
Input Voltage (D.C.) (See Note 2)
Input Current (See Note 2)
Output Voltage, Output Normally High
Current Into Output Terminal, Output Low (except 9009)
Current Into Output Terminal, Output Low 9009

-65°Cto +150°C-55°C to +125°C-o.5 vto +s.o v-0.5 V to +5.5 V-30 mA to +5.0 mA
OVto+Veevalue
50mA
lOOmA

NOTE 1
The maximum Vee value of 8.0 volts is not the primary factor in determining the maximum Vee which may be applied to a number of interconnected
devices. The voltage at a high output is approximately 2 Vae's below the Vee voltage, so the primary liniit on the Vee is that the voltage at any input
may not go above 5.5 V unless the current is limited, so this effectively limits the system Vee to approximately 7.0 volts.

NOTE Z
Because of the input clamp diodes, excess current can be drawn out of the inputs if the. D.C. input voltage is more negative than -0.5 V. The diodeis designed to clamp off large negative A.C. swings associated with fast fall times and long lines. This maximum rating is intended only to limit thesteady state input voltage and current.

3-72

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
9000 SERIES TIµL INTEG_RATED . CIRCUITSSINGtE FLIP·FLOPS

9000

9001

So

So

12

0

0

10
11

Co

13

Co

13

Vee== Pin 16
Gnd= Pin 8

DUAL FLIP·FLOPS

9020

9022
11

So

10.

10

0

0

Co

9

Co
15
15

Vee= Pin 14
Gnd =Pin 7

LOADING RULES

low logic level and is 60 µA maximum at the high logic level.
In the case where unused inputs of an AND gate are shorted to a driven
input, the high logic level input load factor for the inputs will be thenumber of inputs shorted together times the high logic input load factor
for one input. The low logic level input load factor for the inputs will be
the same as that for a single input.

In this data sheet the following notation has been chosen to indicate
the input loading and output drive for all logic elements.

INPUTSOUTPUTS

A/B

X/Y
LOGIC ELEMENTUNUSED INPUTS

Proper termination of unused . inputs will result in maximum c;iperating
speed. Substantial degradation cit turn·oil delay may occur if unused
inputs are left open.
Where
A = high logic level input load factor
B low logic level input load factor
X high logic level output drive factor
Y = low logic level output drive factor
When checking for loading violations it is only necessary to insure thatthe sum of the high logic level input load factol'S at any node does notexceed the high logic level output drive factor at that node. The sameis true for I.ow l9gic leve.1 load and drive factors. These rules apply. only .
within .the TTµL 9QOO series. for loading rules to other Fairchild logic.
elements refer to the CCSL Composite Data Sheet.
.
Multiplying the factor with the appropriate current per unit load gives
the input loading or output drive in. terms of curr,ent. For the TTµL
circuits qf this data sheet, current per unit is ·-1.6 mA maximum at the

The following are acceptable ways. to: terminate unused inputs:==

1. Tie the input to a used input on the same gate. The TTµL 9000 series
has made special provision for this method by offering extra high level
drive factor on all outputs.
·
2. Tie the input to Vee through a resistor. This resistor should be chosen
to keep the input current within absolute maximum ratings for any
possible extreme of the Vee supply. More than one input may beterminated through one resistor.
·'

3. Tie inputs to a separate supply between 4.5 and 2.4 V, if one should
be available.
4. Tie the inputs to the output of an unused gate. The unused gate .must
provide a constant high level output.

3-73

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSNAND GATES-9002, 9003, 9004 AND 9007
HEX INVERTER - 9016
The 9002, 9003, 9004 and 9007 are active low level output AND gates commonly known as NANO gates. The 9016 is a hex inverter with input andoutput characteristics identical to the 9002, 9003, 9004 and 9007. The variety of gate combinations provides the system designer the utmost in logic
flexibility and reduces package count.
Figure 1-LOGIC SYMBOL AND PIN CONFIGURATIONS

9016

9002

3

9003

1
2

3

4

5

6

9
10

8

12
13

11

4

6

9
11

10

13

12

1
2
13
3
4
5
9
10
11

9004
12
6
8

1
2
4
5

*

o---------'

8

9
10
12
13

13
Vee= Pin 14_ _ _ __.Gnd =Pin 7

Figure 2-BASIC GATE CIRCUIT

INPUT

9007

Figure 3-LOADING FACTORSI IQJ---.,-----J:
I I

o--

I

o---

---l--I,___-vv'lr-----o OUT PUTI_t __ .J
I

**
I

I

• .L

-_l_.

-

Nominal Resistor Values

R1 = Rs = 4.0 kO
R2 = 1.5 kO
lb= 150 0
R4=800
Ro= 1.25 kO*Number of inputs depends on the gate.

ELECTRICAL CHARACTERISTICS 9002, 9003, 9004, 9007 AND 9016 (TA = -55°C to 125°C, Vee= 5.0 V ± 10%)SYMBOLCHARACTERISTICS

LIMITS
25°C-55°C
MIN. MAX.

MIN.

TYP.

2.4

2.4

2.7

MAX.

125°C
MIN. MAX.

UNITSCONDITIONS

2.4

Volts

loH = -1.32 mA
Vcc=4.5V
Inputs at Vl.L (see below)
Vee = 5.5 V IOL = 17.6 mA V1H = 5.5V
Vee = 4.5 v IOL = 13.6 mA
Inputs at V1H (see below)
Guaranteed input highthreshold for all il!l!..uts
Guaranteed input low
threshold for all inputs
Vee_= 5.5 V
VF=0.4V
5.5 Von other inputs
Vee.= 4.5V
VR = 4.5 v
Vee= 5.5V
GND on other inp_uts
Inputs high

VoH

Output High Voltage

VOL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.8

0.9

0.8

Volts

IF

Input Load Current

-1.6
-1.24

Input Leakage Current

-1.6
-1.24
60

mA

IR

-1.1 -1.6-0.87 -1.24
60
10

lpo

Vcc Current, Gate On(each gate)
Vcc Current, Gate Off(each gate)
Switching Speed
Switching Speed

5.5

3.5

5.5

5.5

1.6

1.07

1.6

1.6

tf>d+
tpd-

0.4

2.0

0.21

0.4

1.7

3.0
3.0

0.4

1.4

10
12

3-74

Volts

Volts

µA

mA

Vee= 5.0V

nsns

Vee= 5.0 V, See Figure 12
CL= 15 pF

Inputs at gnd

FAIRCHILD TRANSISTOR~TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
9002, 9003, 9004, 9007 AND 9016
TYPICAL INPUT AND OUTPUT CHARACTERISTICSOUTPUT VOLTAGE VERSUSINPUT VOLTAGEOUTPUT CURRENT VER$USOUTPUT VOLTAGE(OUTPUT I.OW>OUTPUT CURRENT VERSUSOUTPUT VOLTAGE(OUTPUT HIGH)INPUT CURRENT VERSUSINPUT VOLTAGE
2~,..._,,.....,._.,.._.,.......,.....,....,.~-II~~

Vee• 5.ov +-+-~i--+-11-1-_,

Vcc•5.0V
INPUTS AT GND.

0 1-+-125'C:i-'""""'"-~:.....~r:....+...-1'15'C ~H'C ..,.._....i.,.....+-~

1

iB

-~=~

r

!. . . z.o_.___._. . . _. . . . . 1!iiI-4.o 1--11-4---+---l-..-.1--+-....J.....1.-.....1--10...._..._..........

i-~1--4--1--1--Mt....<--+-4-~Bi!!! ·&.O .......

'40......,~---+-+-+--1-....+....l.--dI

j 2oi.-.t~Jl.--l--l--l-....,....j~+.--..1--~~

ol,.....l-l.....L...L...!:~=t::::;:t::::l::...1.....L..J
0

-10
-2.0

J~

1.0
2.0
V1rlNPUT VOLTAGE-VOLTS

(

Q
2.0
4.0
·~
V1N ·INPUT VOLTAGE ·VOLTS

Fig. 4e.of-eo L.-.J.,-,..J-....J..-J..--1-i..-..i.......1•1.0

Fig. 5

1.Q
J.O$.O
Your-OUTPUT VOll'AGE •VOLTS

Qo~'"'-~~~5..,....._-1-1~--'_,..1.~5-"".,..,....12D

f.O

VouT -OUTPUT VOLTAGC •VOLTS

Fig. 7

Fig. 6POWER DISSIPATION, LOGIC LEVELS AND NOISE IMMUNITYWORST CASE LOW LMLNOISE IMMUNITY VERSUS
AMIJIENT TEMPERATURE

WO!fST CASE HIGH LEVEL .
NOISE IMMUNITY VERSUSAMBIENT. TEMPERATURE

WORST CASE LOQIC LEVELSVERSUSAMBIENT TEMPERATURE

POWER DISSIPATION VERSUS
SUPPLY VOLTAGE

2,4,........,..._.,.._.,..........,.......,........,......,.........,......,

1.2 ,..,......,..._..,..._..,..1 ................-..-....................
1--+...-,-1--+.--.+.--.o1-4.5V svcc u.~v

~ 1.0
I

25

~e~t--r,.._-+--+-+-+-+-+-+-+

i~ 0.$ p~!
bl o.&

1-+-=t="=-......d~!a! 20t--+--t--+-:+_,--::::i.--to==~ ~ u 1-t-t-+-+-+:==i--...;.....i,.._=.

~ 151:::;;;::.i;;;-"'F'-t--t_,~f-+-~....j

f 10t:~~~~~......r-t=i ~ ~-"~-=:t:::t=t:V:l~:et::t=t;j15i!iJ 0.4

1.0~5~ol::=~~~::::P"=:f=:f==i::::j

5.0

5.5

Yee-SUPPLY VOLTAGE-VOLTS

Fig. 8

VoL

·55

·55

125

1
F.0.•11....j...-"~1--1--.i-.i-..1---1-.--1-.--1--1

2~

125

TA •AMBIENT TEMPERATUM; ·'C~"~,.__..__...._~21--i.-.,1._.........,.-,,.!1as
TEMPERATURE l'Cl

Fig. 10

Fig. 9j....-1~ 0.2

o.__..__..___,__,_....__,__,__,_-'

25

~.• \

;:g;.5~~ 0.4

oI- ~f J.-+-+-rv-jccjm+-TA ·AMBIENT TEMPERATURE -•efFig. 11

SWITCHING CHARACTERISTICS
Fig. 12SWITCHING WAVEFORM ·tpd TEST CIRCUIT
II C

PULSE
INPUT
f c:::! 1.0 MHz

Amp c:::! 4.0V
Width C!:! 200 ns

tf = t,:SlO ns

WORST CASE TURN OFF DELAY
VERSUSAMBIENT TEMPERATURE

WORST CASE TURN ON DELAY
VERSUSAMBIENT TEMPERATURE

Fig. 13

Fig. 14
S..75

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSNANO BUFFER -9009

The 9009 is a power gate capable of sinking and sourcing large currents for high fanout applications. Logically it is the same as the 9004.

Figure 2

Figure 1

CIRCUIT DIAGRAMLOGIC DIAGRAM AND PINCONFIGURATION(One Gate)

Vee
1--+-~

2 ------.___]
4 --+----r-"'.']
5--+---'
9----~

12--+---r~'13--+---'

Vee= Pin 14
Gnd= Pin 7--------~

05

Figure 3

LOADING FACTORS
Nominal Resistor Values~~~---r--)
212

2/2

---1----

R1 =2.0 kO
R2=5600
Rl= 1500- - - 66/33

R4= 50 0

Rs=4.0 kO
R•=5000

ELECTRICAL CHARACTERISTICS 9009 (TA = -55°C to 125°C, Vee = 5.0 V ± 10%)SYMBOLCHARACTERISTICS-55°C
MIN. MAX.

LIMITS
25°C
MIN. TYP. MAX.

125°C
MIN. MAX.

UNITSCONDITIONS

VoH

Output High Voltage

2.4

2.4

2.4

Volts

VOL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.8

0.9

0.8

Volts

IF

Input Load Current

-3.2
-2.48

Input Leakage Current

-3.2
-2.48
120

mA

IR

-2.2 -3.2-1.74 -2.48
20
120

lpo

Vee Current, Gate On(each gate)
Vcc Current, Gate Off(each gate)
Switching Speed
Switching Speed

12.9

8.6

12.9

12.9

loH = -3.96 mA
Yee =4.5V
Inputs at Vll. (see below)!.s:._e = 5.5 v IOL = _gll_mA """- = 5.5 v'Yee = 4:5Y 1 0 L = 40.8 mA
Inputs at V1H (see below)
Guaranteed input highthreshold for all inputs
Guaranteed input low
threshold for all inputs
VF= 0.4V
Y_ee = 5.5V
5.5 Von other inputs
Vee_= 4.5 V
VR = 4.5V
Vee= 5.5V
GND on other inputs
Inputs high

3.2

2.15

3.2

3.2

k
tpd-

0.4

2.0

2.7
0.21

1.7

4.0
3.0

0.4

0.4

Volts

1.4

15
10

3-76

Volts

µA

mA

Vee= 5.0V

nsns

Vee= 5.0 V, See Figure 12
CL= 15 pf

Inputs groundedFAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
9009
TYPICAL INPUT AND OUTPUT CHARACTERISTICS
INPUT CURRENT VERSUSINPUT VOLTAGEOUTPUT VOLTAGE VERSUSINPUT VOLTAGE
2.0

E

1-Vcc•5.ov

.

H

1~~~"

,.

t--1 25"C-=; ~~·cE.!.z -2.0
:11

I

5"C

.J

!;;

-20 1--+--+--t--tWI"'"!-·

u-40 1 - - - t - _ - - +_ _+----+--+---t--lI"' -:4.oBi
T -6.o

...

~

-55"C

? -60 t---t---Jo!i~-r--t--t---t---1
~

_1!

-8.0

0 0Ll-1.-L~to.!::!:~::±::2~.o=..L-L..LJ3.o

OUTPUT CURRENT VERSUSOUTPUT VOLTAGE(OUTPUT LOW)OUTPUT CURRENT VERSUSOUTPUT VOLTAGE

-10
-2.0

VIN - INPUT VOLTAGE-VOLTS

Fig. 4

-80

8.0

2.0
4.0
6.0
VIN-INPUT VOLTAGE-VOLTS

0.5
1.0
1.5
VouT -OUTPUT VOLTAGE - VOLTS

Fig. 6

Fig. 52.0

Fig. 7POWER DISSIPATION, LOGIC LEVELS AND NOISE IMMUNITYWORST CASE LOGIC LEVELSVERSUSAMBIENT TEMPERATURE

POWER DISSIPATION VERSUS
SUPPLY VOLTAGE

WORST. CASE HIGH LEVELNOISE IMMUNITY VERSUSAMBIENT TEMPERATURE

WORST CASE LOW LEVELNOISE !MM.UNITY VERSUSAMBIENT TEMPERATURE

1 s HIGH LEVEL FAN OUT s 66

2.0

1.5

~
VIH +--+---+---+---<
t-+-+--t--~r-+t---1,,,.,,1--"=:I

g 0.2 t--+---+---+--+--+---1-t--~

0.5 ~:+=:+=:::t::::::+:Vo!!!;L:t::::::t=::::!:::=l::::::::I0t--t-- F.OJ33 4.5-55

1

Vcr5.Y--+---I

Vee-COLLECTOR SUPPLY VOLTAGE - VOLTS

25
TA-AMBIENT TEMPERATURE-"C

Fig. 8Fig. 9125

o.__+---+---+---'--+---'---'-'--'

o,__..__.__._-'---'---'---''--..___,

Fig. 10

Fig. 11-55

25
TA ·AMBIENT TEMPERATURE-"C

125

-55

25
TA-AMBIENT TEMPERATURE-"CSWITCHING CHARACTERISTICS
Fig. 12

tpd TEST CIRCUIT
Vee

SWITCHING WAVEFORM

2.0 k.ll

PULSE
INPUT

JO---.---+<> Vourio-~--,-.----t--/f"" 1.0 MHz
Amp"" 4.0V
Width "" 200 ns
t 1 = t,~10 ns

WORST CASE TURN OFF DELAY
VERSUSAMBIENT TEMPERATURE

WORST CASE TURN ON DELAY
VERSUSAMBIENT TEMPERATURE
60
Vcc•5.0V
SEE FIG.12

Vee 5.ov_t--+---+---+--+----+---<SEE FIGc 12
50 f----t----t----+--+--+--1-f--'+-----l

50

5i!l
z
0
z

7"'
~

40

...,,_
30

20......
b-..J

100'---+---+---'----'---'---'-t--~
-55
25
125
TA -AMBIENT TEMPERATURE-"cFig. 13......... -..

:t·---·TT·-··t-

MAX.AT CL•15pF

AT CL •150pFt::=

MJ. AT 1cL·J~pF t---

0

-55

25
TA-AMBIENT tEMP£RATURE-"C

Fig. 14125125

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
EXTENDABLE AND-OR-INVERT GATES-9005, 9008
EXTENDER-9006
The TTµL 9005 and .9008 are ANO-OR-INVERT gates which may be OR extended with the use of the 9006. For noise immunity and ojierating level
curves, refer to the gate ~ction on Page 4 and 5.

Figure 1-LOGIC DIAGRAMS AND LOADING FACTORSThe numbers by each input and output give the input loading and output drive capability. For complete explanation see Page 3.

9008

9005
1.511.5
1.511.5
1.511.5
1.511.5

13
. 9
10:

1.5/l.5;JIO-~e- 22111

1.511.5-a;::-.....__.:.:ll_,. EllllT.
12 -ti COLL.
~~

1.511.5

EXTENDABLE
Ill
Ill
111
111

1.511.5

2

1.511.5
l.511.5

3
4

9006

13

9

13 .
2 .

.

3

··

.

12

COLL

11

Ellll't.

10

8J0---=22111
11'---!!
tt EllllT.
12- t t COLL.
'--=

2
3

4

•

1.511.5~·.

1.511.5
1.5/1.5

1.511.5
1.511.5
1.511.55•l.511.5
1.511.5
1.511.5

1.5/,1.5~1
.

i

6
8

.

l.!ill.5

9

COLL.

IO

EMIT.

'

·

NON·EX'tENDABLE*Four Extenders (9006) may be.tied to theSe terminlls*Four ~nders (9006) may betied to these terminals

Vee== Pin 14
Gnd,... Pin 7

Vee=Pin 14
Gnd :-=Pin 7

Vee= Pin 14
Gnd=Pin7

Figure 2-CIRCUIT DIAGRAMS

9008

9005

ve:c
R2

Rs

I
13

2
3

8
8

9

.,,.

10

9

.,,. .,,.

10.,,. .,,.

Vcc=Pln 14
Gnd=Pln 7

45

EXTENDABLE.6

Tjpical Reiistor Values
R1 =lb= R•=-Rs=-2.il kO
lb=81l00
Rl.=1500
R1=800Ra=4.0k0
R9=6650

Vee
R12
2
3

Og

9006

6

Vee
4
5

.,,. .,,.
NON ·EXTENDABLE

Vee=Pin 14
Gnd =Pin 7
two in 1 package

Typical Resistor Values
R1 = RJ = 2.6 kO
lb=8000
R4= R11=1500
Rs= R12= 80 0

Rl. = Re == Rio = R1J = 4.0 kO
R1=6650R•= 1.5 kO
R1•.= 1.25 kO

Vee= Pin 14
Gnd =Pin 7

.,,.

3-78

.,,.

.,,.

.,,.

.

FAl:RCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSELECTRICAL CHARACTERISTICS 9005, 9006 AND 9008 (TA:: -55°C to 125°C, Vee

= v
5.0

± 10%)..

LIMITS
SYMBOLCHARACTERISTICS

VoH

Output High Voltage

VOL

Output Low Voltage

VIH.

Input High Voltage

VIL

Input Low Voltage

IF

Input Load Current
9005 Nonextendable Gate
Input Load Current
Extendable Gate and Extender-55°C
MIN. MAX.

MIN.

25°C
TYP.

2.4

2.4

2.7

MAX.

125°C
MIN. MAX.

UNITS

2.4

Volts

.

0.2

2.0

lpo

1.4

10 H = -1.32 mA
Vee =4.5V
V1L =value ,indicated below, on this ta.bl~

Volts

Vee= 5.5 V 10 L = 17.6 mA V1H = 5.5 V
Yee ~UV Im = fr.I).mAV;H (see beloW}

Volts

Guaranteed input high thresholdfor all inputs

0.8

0.9

0.8

Volts

Guaranteed input low thresholdfor all inputs

-1.6
-1.24
-2.4
-1.86

-1.1 -1.6-0.87 -1.24-1.5 -2.4

-1.6
-1.24
-2.4
-1.86

mA

Vee=5.5V _.::_
Vee=4.5V
Vee= 5.5V
Vee =4.5V

VF=0.4V,
5.5 Vonother inputs

Vee= 5.5V
VR = 4.5V

Gnd on allother inputs

Vee= 5.0V

All inputs
open·. -1.31.-1.86

µA
mA

5.0

60

60

7.5

90

90

6.5
11.3
12.5

4.5
7.6

9.3

6.5
11.3
12.5

6.5
11.3
12.5

3.1
4.7
9.4

2.1
3.3
6.6

3.1
4.7
9.4

3.1
4.7
9.4

1.61

1.08

1.61

1.61

mA

Vee = 5.0 V All inputs high9006 attached to a 9005

2.35

1.65

2.35

2.35

mA

Vee= 5.0 V All inputs grounded
9006 attached to a 9005...

Vee Current, Gate "ON"9005 Nonextendable Gate
9005 Extendable Gate
9008
V,ee Current, Gate "OFF"9005 Nonextendable Gate
9005 Extendable Gate

mA

mA

9008
~lpo

0.4

1.7

Input Leakage Current
9005 Nonextendable Gate
Input leakage Current
Extendable Gate and Extender

IR

0.4

CONDITIONS & COMMENTS

.

;,;_

0.4

I

Extra Current Drain
from one 9006 Extender
Gate "ON"Extra Current Drain
from one 9006 Extender
Gate "OFF"All inputs
except extender inputs
gnd.

Vee= 5.0V

Note: Output characteristics apply to a 9005 (both gates) or a 9008.
Input characteristics apply to a 9005 (both gates) or a 9008 using either the internal gates or an external 9006 extender.

9005, 9006, 9008
TYPICAL INPUT-OUTPUT CHARACTERISTICS(EXTENDABLE GATES*)

2.0 Vee • 5.o v

v

25'~"

~.

vcc5.ov

f--1 l25''e,4,,..+--i-~+-+-+----l~

15•e,-,,~o·c 1----+--+-+-+--l

~

1

E-2.0
~

,.

-55'C

1--.....,--t--+---+-+-+--+--+-~

B-4.o 1---+---.i--t--+---+-+-+--+--+-~~~ -6.0 f--<.__,---+--+--+--+-+--+--+---l--

INPUTS AT GND. ~0 I--+--+--

§'
~ -20
~

1--+--'-+-·-+---•~+---l---+---l~-401--+---+-------l-+---l-·--+---l

5I

z

0

1.0

2.0

v1N-INPUT VOLTAGE-VOLTS

3.0

.

~ 80

r--ir--<,...1. . .i--__

5

II

5I

2

-8.0 f-111----lf--i--t--t--t--t---t--+--i

1-+---+---1-++-T+H--H--f---+---+---l---o l.....l_L_l__.L::J~::t:r::.Ll_J_~

OUTPUT CURRENT VERSUSOUTPUT VOLTAGE(OUTPUT LOW)OUTPUT CURRENT VERSUSOUTPUT VOLTAGE(OUTPUT HIGH)INPUT CURRENT VERSUSINPUT VOLTAGEOUTPUT VOLTAGE VERSUSINPUT VOLTAGE_,--+--+--+--+--+---I-55°C

40,___,~~LL.-+--+--1--+-+--+--+--l---l
III-I+-+--+--+--+-..,~-+-+--+-~-10~~~~-•~--+~~~

-2.0

0

2.0

4.0

6.0

8.0

-80 ~~-+--+---+-~-+---~---!
-1.0
7.0
1.0
3.0
5.0

~

M

. M

U

~

V1N - INPUT VOLTAGE -VOLTS

Vour OUTPUT VOLTAGE-VOLTS

VouT -OUTPUT VOLTAGE ·-VOLTS

fig. 4

Fig. 5

Fig. 6

Fig. 3*Curves on Page 5 apply to 9005 nonextendable gate.

3-79

U

9601
RETRIGGERABLE MONOSTABLE MULTIVIBRATOR
TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRIPTION - The ITµL 9601 is a DC level sensitive retriggerable monostable multivibrator
which provides an output pulse whose duration and accuracy is a function of external timing components
only. The 9601 has excellent immunity to noise on the Vee and ground lines. The 9601 uses ITµL for highspeed and high fanout capability and is compatible with all devices in the CCSL family of integrated circuits.

PHYSICAL DIMENSIONS
Similar to JEDEC (T0-116) Outline

FEATURES:• 50 ns TO oo OUTPUT PULSE WIDTH RANGE• RETRIGGERABLE 0 TO 100% DUTY CYCLE• COMPLEMENTARY D.C. LEVEL SENSITIVE INPUTS• COMPLEMENTARY OUTPUTS• CCSL COMPATIBLE• OPTIONAL RETRIGGER LOCK-OUT CAPABIUTY• PULSE WIDTH COMPENSATED FOR Yee AND TEMPERATURE VARIATIONS~BSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)

Storage Temperature
Temperature (Ambient) Under Bias
Vcc Pin Potential to Ground (See Note 1)
Input Voltage (D.C.) (See Note 2)
Input Current (See Note 2)
Voltage Applied to Output When Output is High
Current Into Output When Output is Low-65°C to +150°C-55°C to +125°C-0.5 vto +s.o v-0.5 V to +5.5 V-30 mA to +5.0 mA· OVto +Vee value
50mA

JRDER INFORMATION:
ipecify U3196015XX for flat package and U6A96015XX for Dual-In-Line package, where 5XX is 51X for-55°C to +125°C temperature range or 59X for the 0°C to +75°C temperature range.

!OTES:!) The maximum Vee value of 8.0 volts is not the primary factor in determining the maximum Vee which may be applied to a number of interconnected devices. The voltage at a high output ·is approximately 1 Vae below the Vee
voltage, so the primary limit on the Vee is -that the voltage at any input may not go above 5.5 V unless the current
is limited, so this effectively limits the system Vee to approximately 7.0 volts.
··
1) Because of the input clamp diodes, excess current can be drawn out of the inputs if the D.C. input voltage is morenegative than -0.5 V. The diode is designed to clamp off large negative A.C. swings .associated with fast fell times
and long lines. This maximum rating. is intended only to limit the ~teady state input voltage and current.

NOTE: All dimensions in inches

Fig. 2l=AIRCl-llLCJ
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW,. CALIFORNIA, (415) 962-5011, TWX: 910-379·6435

3-80

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC®. INTEGRATED CIRCUITSJ-K FLIP-FLOPS-9000, 9001
DUAL J-K FLIP-FLOPS-9020, 9022
GENERAL DESCRIPTION

A joint (JK) input is provided for all flip-flops in this family. This common
input removes the necessity of gating the clock signal with an external gate
in many applications. This not only reduces package count, but also reduces
the possibility of clock skew problems, since with internal gating provided,
all flip-flops may be driven from a common clock line. Several TTJ.1L drivers
may be used in parallel to drive this common clock line, if the load exceeds
the F.O. capability of the 9009 buffer.
The asynchronous inputs provide ability to control the state of the flip-flop
independent of static conditions of the clock and synchronous inputs. Bothasynchronous set and clear are provided on all flip-flops except the 9020,
which because of a logic trade-off has only clear inputs. The set or clear pin
being low absolutely guarantees that one output will be high, but if opposing
data is present at the synchronous inputs and the flip-flop is clocked, thelow output may momentarily spike high synchronous with a positive transi·tion of the clock. If the low output of the flip.flop is connected to otherflip-flop inputs clocked from the same line, the spike will be masked by theclock. If the clock is suspended during the time when the asynchronous
inputs are activated, no spike will occur. When the spikes can cause prob·lems, a simple solution is to common the joint JK inputs with the synchron·ous set or reset signal.

The TTJ.1L 9000 series has four flip-flops to satisfy the storage requirementsof a logic system. All are master-slave JK designs and have the same highspeed and high noise immunity as the rest of the 9000 series. As with thegates, all inputs hav.e diode clamps to further enhance the noise immunity.
The JK type flip-flop was chosen for all flip-flop elements in this family
because of its inherent logic power. The input function required to produce
a given sequency of states for a JK flip-flop will, in general, contain more
"don't care" conditions than the corresponding function for an RS flip-flop.
These additional "don't care" conditions will, in most cases, reduce theamount of gating elements required to implement the input function.
The master-slave design offers the advantage of a DC threshold on the clock
input initiating t~e transition of the outputs, so that careful control of clock
pulse rise and fall times is not required.
Data is accepted by the master while the clock is in the low state. Refer tothe truth table for definition of "ONE" and "ZERO" data. Transfer from themaster to the slave occurs on the low to high transition of the clock. Whenthe clock is high, the J and K inputs are inhibited.
Figure 1-LOGIC DIAGRAMS AND LOADING FACTORS

9000
111
111
111
111
212
111
111
111

9020
4/4

4
6 20/10

12
9
1
3
10
11

14

"1

111
1 6

20110

0 7

20/10

20/10

FFl
T

212

1---Co 0~--2.7/z.7

8 20/10

1,1
1,1

0

9

2~o

13

Vee= Pin 14
Gnd =Pin 7

9001

9022
4/4

1/1
1/1
111
111
212
111
111
111

4
5
12

2
6

So l

9
l
3
10
11

20/10

1/1

212

T
K

111

e 201i 0

Co 0

0 7

20/10

lti.

Vee= Pin 14
Gnd =Pin 7

Figure 2-FUNCTIONAL LOGIC DIAGRAMS

9000/9001

9020/9022
So 9022 ONLYy

So 9022 ONLY
9
I

T

0

3-81

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSTRUTH TABLESSYNCHRONOUS OPERATIONBEFORE CLOCKOUTPUTS
ONE
ZERO
L :
H
L
H
H
L
H
L

INPUTS
J

K

L"
H*

x
x

x
x

L*
H*

ASYNCHRONOUS OPERATIONOUTPUTS
AFTER
CLOCK
ONE
ZERO
L
H
H
L
H
L
L
H

INPUTSOUTPUTS

So
L
L
H

Co
L
H
L

H

H

ONE

ZERO

H
H
L

H
L
H

SYNCHRONOUS
INPUTS CONTROLThe H" symbol in the J or K input column is defined as meaning that the
input has been high at some time while the clock was low.
The X symbol indicates that the condition of that input has no effect on the·next state of the flip-flop.
The H and L symbols. refer to steady state high and low voltage levels,
respectively.

SYNCHRONOUS OPERATION
The truth table defines the next state of the flip-flop after a low-to-hightransition of the clock pulse. The next state is a function of the present
state and the J and K inputs as shown in the table.
The J and K inputs in the table refer to the basic flip-flop J and K inputs
as indicated on the logic diagrams. These internal inputs are for every flipflop the result of a logic operation on the external J and K inputs. This
operation is represented symbolically by AND gates in the logic diagram foreach flip-flop. Logic diagrams are in accordance with MIL Standard 806B.
The L* symbol in the J and K input column is defined as meaning thatthat input does not go high at any time while the clock is low.

UNUSED INPUTSThe 9001, 9020 and 9022 all have active level low synchronous inputs.
When not in use they must be grounded. All other .unused inputs including
asynchronous should be tied high for maximum operating speed. Use oneof the methods recommended on Page 3.

ELECTRICAL CHARACTERISTICS 9000, 9001, 9020 AND 9022 (TA = -55°C to 125°C, Yee = 5.0 V :1;.10%)
LIMITS
SYMBOLCHARACTERISTICS

VaH

Output High Voltage

Val

Output Low Voltage

VIH

Input High Voltage-55°C
MIN. MAX.

MIN.

25°C
TYP.

2.4

2.4

2.7

0.4
2.0

0.21

·.··

MAX.

UNITS

2.4

Volts

Yee =4.5V

laH = -1.2mA

Volts

Yee=4.5V
Yee=5.5V

10 L = 12.4 mA
10 L = 16.0mA

Volts

Guaranteed input high thresholdfor all inputs.

0.4

1.7

0.4
1.4

:

VIL

Input Low.Voltage

IR

Input Leakage
All J, K inputs; T inputs 9000, 9001
J, K inputs 9000, 9001; T inputs 9020, 9022
JK inputs 9020, 9022
S0 , C0 (all flip-flops)

IF

IF

lpo

,

0.8

-1.60
-3.20
-6.40
-4.32

Input Current
All J, K inputs; T inputs 9000, 9001
J,K inputs 9000,9001; T inputs 9020,9022
JK inputs 9020, 9022
S0 , C0 (all flip-flops)

-1.24
-2.48
-4.96
. -3.35

Yee Current
9000
9001
9020,9022
each flip-flop

0.9

0.8

Volts

Guaranteed input low thresholdfor all inputs.

60
120
240
160

60
120
240
160

µA

VR =4.5V
Yee= 5.5V
Gnd. on other inputs.

.,-1.l -1.60-2.2 -3.20-4.4 -6.40-2.97 -4.32

-1.60
-3.20
-6.40
-4.32

mA

Yee= 5.5V-0.87 ,-1.24

-1.24
-2.48
-4.96
-3.35

mA

Yee =4.5V

24
28
27

mA

· S0 atgnd
S0 at gnd
C0 " C02 at gnd

5.0
10
20
14

Input Current
All J, K inputs; T inputs 9000, 9001
J,K inputs 9000,9001; T inputs 9020,9022
JK inputs 9020, 9022
S0 , C0 (all flip-flops)

24
28
27

CONDITIONS & COMMENTS

125°C
MIN. MAX.

.. -1.74 -2.48-3.48 -4.96..'....;2.35-3.75
13
14
14

24
28
27

VF= 0.4V
5.5 V Gnd on other
inputsYee= 5.0V

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSTYPICAL INPUT AND OUTPUT CHARACTERISTICS
9000, 9001, 9020 AND 9022

OUTPUT VOLTAGE VERSUSINPUT VOLTAGE
ASYNCHRONOUS INPUTS

CLOCK OUTPUT VOLTAGE
VERSUS INPUT VOLTAGE

INPUT CURRENT VERSUSINPUT VOLTAGE 9004

4.0

2.0

~•5.0V

.g

g 3.0

..

I

I

.n

'::;

3.0 l--l--+--l--U-41-14-++--+--+-~--!

I

~

'::;

E

~ 2.0 l-+-+-+--IH+t-1.-fl..~g:~ t-t-+--1 ~> 2.0
rl1 ,~~:~ ;--;--;--;

I~ 1.0 >-+-+--+--++-++++--++--+--t--+---t---1;~.,_ 1.0

1.0
2.0
VIN - INPUT VOLTAGE -VOLTS~~~:~ +--+-1--1---+.

~ -6.0
I

.7

~

~

....
:::.

5

-.6.0 t:--11--1--1--1--1--11--1--1---!--l-8.0 l--IJ--t--1---1---1--1---+--l--l--l

-10
-2D

-10!":"'""~~~~~~~~~

BD

0
2D
4.0
6.0
VIN - INPUT VOLTAGE - VOLTS

-2.0

0
2.0
4.0
6.0
VIN -INPUT VOLTAGE -VOLTS

INPUT CURRENT VERSUSINPUT VOLTAGE
JK INPUT 9000, 9001

INPUT CURRENT VERSUSINPUT VOLTAGE
JK INPUT 9020, 9022

INPUT CURRENT VERSUS INPUTVOLTAGE ASYNCHRONOUS
INPUTS-ALL FLIP-FLOPSOUTPUT CURRENT VERSUSOUTPUT VOLTAGE .
(OUTPUT LOW)

,J.e"'

I,......

0 f--1 2s•e~-ss•eiE .
~~.... -2.0~""""'"'a-•.o t---1--1'--1---1--11--1---+--1--i"'a-4.o

3.0

£.

::I

Fig. 6

I

~
I

!-2.0

25'C

Fig. 5

E

~

1.0
2.0
V1N·-INPUT VOLTAGE-VOLTS

3.01s•c°"'~.,...t--io·-c+-,,_.1"-11--l

1

Fig. 4I- Vcc•S.OV

ia -4.o~t--o•e~~5·cFig. 32.0.

Ve~• S.OV-+--+--+-+--+--1•',,-+-~

O f---1 125°e-8.0

OLl-L.....L.l!:::!l:::!::!:::!:!:::~l::::::l:=l:::~02.0.--,--,--.--.--.--.--,.-,~,......,

_JU_
1'.

"'"'

pSS'e
O"e
j..--25°e
J.--75°e
125'C

~

~

r:

.... -2.0
z

:ii

-55'e

1-vee •5.ov
t- 12s•e
0 f---1 75•e

INPUl CURRENT VERSUSINPUT VOLTAGE 9009~

I-- i.rss•e..5-

I-- k;?"C
v~s·c

-2.0

-4.0

-8D 1--

i

t.O

-2.0

(TA

i

t--+-25·~"
f-- 75°e ~ss•c
o•c

0
2.0
4.0
6.0
VIN-INPUT VOLTAGE-VOLTS

8.0

7~

2s•e

"
~

,.boe

~

O"e

L
T..

40

-ss•c

I

~~r~------t--+--t----l~+--+-------1

f----1 1'125'C

f
I

0
2.0
4.0
6D
V1N-INPUT VOLTAGE-VOLTS

8.0

IL

0 0,._..._~ns~'--~1D--'~1~.s-'---'2.0

Your - OUTPUT VOLTAGE - VOLTS

Fig~

Fig. 9

10

1

MIN.

J, Kor JK
9000 Only
Data Entryl or..!Data Entry.
J, Kor JK
19000 Only_
Data Entry
J or K Data En!!I_
Positive
Clock
9000
Only
Nejative
PositivelN~ative

Negative
9000 Only

30
10
17

TYP.

MAX.

UNITS

FIGURES

12
12
20
25
22
8.0
12
18
7.0
11
20
25
8.0
10
25
20
50

20
20
30
35

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz

16 17 18
16, 17, 18
16, 17, 18
16, 17, 18
16,18
16,17,18
16, 17, 18
16, 1816, 17; 18
16,17;18
16, 1816,18'
16,17,18
16,17 18
16,17,1816,18
16, 17, 18

3-83

--I

80

:::.

1

-10
-2D

1~

Ld

v
ti
L
~ 60H-14~·-=t=t=+:W
~

JZ

-8.0

v1s·1

Vee •SDVINPUTS OPEN

c

125°e

1--1

~~

~ock-to-Output

Toggle Frequency'ii

100.---.--..--.---.---.~,---.-~

v.o·c
7 -6.0 f---1 v,;rs•e~~s·Clock-to-Outfillt
So or C0 -to-Output

~or~

I

B -4.o~or ~to-Output

Pulse
Widths.

_ll_= 25°C, Yee = 5.0 V, CL = C = 15 pf of all flip-flops uriless otherwise noted)

CHARACTERISTICS

treleasevee•5.0V

111

Fig. 8SWITCHING CHARACTERISTICS

ts et-up.!. -2.0
::I

-10
0
2.0
4.0
6.0
VIN - INPUT VOLTAGE -VOLTS

0E

1!'125°e

Fig. 7tpd-..

WJ2:::.we~~ l'io•e,2s•e

I -6.0 1-- v-rs•cv_2s•c~I-- [<,o•e

-8.0

tpd+

2.0

vJ•5.0V75"e..,J
0 I-- i2s•e._,z-6.0 I-- Kr~'ei.-12s•c

10
-2.0

2.0

BD

12
1.0
4.0

,,.

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
MAX. AND MIN. PROPAGATIONDELAYS VERSUSAMBIENT TEMPERATURE
ASYNCHRONOUS INPUTSTO OUTPUTS

MAX. AND MIN. PROPAGATIONDELAYS VERSUSAMBIENT TEMPERATURE
T TO OUTPUT
52
44

'

T

CL• 15pflT

52\-Vee • 5.o v -ji-+--+---+---+----+---1

r--J-+---_,T---t--+---t---+--c~IZ:__,

36~

rzf12
L

~A~d-

~l T
d. {

HIGJilJ

l l

ld

1 l

281--1-- ---+--1-.1-.-.+,.-1--li"'-l---l~i.---oc+..._--t~--fc..MA""X~.
tp·;;+i. _..
20
,~
'/'

L"i

{ T LOW)

J I

L

2

4.0
. -55

m

~

L'.'.'.1

;::

2.0

e.o

,/L_

A

!!;

..

./Y, ~,~_·.,__,__,

Vy~+o~~=i..r--l_i--'---l-'--'-~J_J_J..L-.L-J

125

0

40

80

120

11

h,..
MINI NEGIATIV~ -+--+---i
36 '\I 'j-<J CLOCK PULSE WIDTH

---j

·~

I

ZS t--+--f---+---'·<-l"iM-IN-+-.-SE~T--U-P>--TIM-E+---<

I J~

i---.-

ro1--t-+-+-+--l1--tl-+-t--1'::::REfLE:::A3SE=T=IM~E;t:l

12 t=t,_.-d:::J1"::::M::::AXf.

MAX. RELEASE TIME

-2.0
-55

200

Fig. 13

::~~

I'

I J
,l ,~
~,-~v

*
11

160

Cl-LOAD CAPACITANCE-pf At BOTH OUTPUTSNEGATIVE CLOCK PULSE WIDTH
SET-UP/RELEASE TIMEVERSUS AMBIENT TEMPERATUREf~

X k;::t" ,..J

SET-UP/RELEASE TIME AND
NEGATIVE CLOCK PULSE WIDTHVERSUS AMBIENT TEMPERATURE\-vC-;. 5'1.~~
1 ~,~M,...,.LJ"-+--+--+__,_tj , .#-J,'lI,,,.,....,./,...._,___,--;

9000

10
6.0

f

Fig. 1214'i

9001-9020-9022 .

'M!N~cr;;;V

~

J.L_

12 t--t--+--+--+--;u~ 4.0

k::'.1/k".:.

-.11

-

;!;

)..--'

25
TA-AMBIENT TEMPERATURE-'.C

Fig. 11

18

I

i1l

l l

TA-AMBIENT TEMPERATURE-'C

22

~· 1s

J/1

MIN.tpd+( T HIGH)

~

.LI

L'1

MIN. lpd- ( T LOW)

~~

z

20

1-Ycc1 ~ 5.0 v
CL• 15pF

44

INCREASE IN ASYNCHRONOUS
OR CLOCK INPUTDUE TO OUTPUT CAPACITANCE

4.o~~~~-l~l~~~

l l

25

-55

125

25

125

TA-AMBIENT TEMPERATURE-'C

TA-AMBIENT TEMPERATURE-'C

Fig. 14

Fig; 15
SWITCHING TEST CIRCUITS

9000/9001
Fig. 169020/9022
Fig. 17

Vee= 5.0 V
R = 2.0 k!l
C1 ,,;, CL= 15 pf includingVeeRprobe and jig

capacitancecapacitanceVJK I - - - - - 'WAVEFORMS>3.0 v---1,__ _\ _ _..,..---J/'·.
VJK<::: ~ ----J1-+>3.0 v=-iR

Vee=5.0V
R = 2.0 k!l
C1 = CL = 15 pF includingprobe and jig

9000. Fig. 18

Veet SET-UP OR't RELEASE

1.5 v<0;4 v>3.0 v
1.5 v<0.4 v

3-84

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSSWITCHING TEST NOTES
tpd+ and tpd-

trelease

1. VJK should be kept at the high logic level when performing tpd tests.

1. tretease is defined as the maximum time allowed for a HIGH to be presenta

at a synchronous logic input at any time during the low state of the

2. Drive the clock pulse input with suitable pulse source. tpd+ and tpddelays are as defined in the waveforms.

clock and hot be recognized.
2. The test for tretease is performed by adjusting the timing relationship be-tset-uptween VCP and VJK to the tretease maximum value. The outputs of devices

1. t,et-up is defined as the minimum time required for a HIGH to be present
at a synchronous logic input at any time during the low state of theclock in order for the flip-flop to respond to the data.

that pass will remain at static logic levels. In order to check both J andk sides of the flip-flop it is necessary to perform the test with the flip-

2. The test for tset-up is performed by adjusting the timing relationshipbetween the Vcp and VJK inpu.ts to the tset-up minimeim value. A device
that passes the test will have the output Waveform shown. The output ofa device that does not pass the tset-up test will remain at a static logic
level (no switching will occur).

flop In each of its two possible states, i.e., set and clear. This can beaccomplished by making use of the appropriate direct inputs to establish
the state before a test. The outputs of devices that do not pass thetrelease test will exhibit pulses instead of static levels.

RECOMMENDED INPUT PULSE SOURCESDTµL9932 gates with adjustable capacitors
connected from extender inputs to groundmake suitable delay elements.

PULSE
GENERATORADJUSTABLE..--~.--_.... DELAY_/
NETWORKFREQUENCY " 2 MHz-----'
DUTY CYCLE " 50%
ADJUSTABLE
DELAY
NETWORK

9001 SCHEMATIC DIAGRAM

9000 SCHEMATIC DIAGRAM

For resistor values,see page 16

For resistor values,see page 16

Yee

Yee

Vee= Pin 14
Gnd =Pin 7

Vee= Pin 14
Gnd =Pin 7

3-85

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
•

t

'

••

.,.

9020 SCHEMATIC DIAGRAM
16.vee

Vee= Pin 16
Gnd =Pin 8

NOM!NAL COMPONENT YAL~ES (ALL FLIP-FLOPS)

R" R4, R5, R8, R10, R14, R17, R21 , Rw R23 , R240 R260 R29 = 4.0 kn.
R2 , R3 , ~6 • R7 = 2.0 kn
R9, R16, Rw R31 = 6.0 ~n
R;" R18 =1.5kn
R12 , R19 150 n
R13 , R20 =110 Q
R15, Rw R25 , R27, R30 1.25 kn==

R32 =1.0kll
C" C2 =10 pf

3-86

•

'

'.

FAIRCHILD:' TRANSISTOR-TRANSISTOR~ MICROLOGIC® rNTEGRATED :CIRCUITS
9022 SCHEMATIC DIAGRAM
For resistor values see table on page 16

4

Vee= Pin·15
Gnd =Pin 8

APPLICATIONSSYNCHRONOUS BCD COUNTERDIVIDE BY TEN COUNTER
Vee

Q8

Q2

Ql

Two TTµL 9020 Dual Flip-Flops require no additional gating
elements to produce divide by ten circuit with a square wave
divide by ten output and a divide by five output.

Two TTµL 9020 Dual Flip-Flops require >no _additional gating
to produce a fully synchronous 8421 code BCD Counter.

BINARY COUNTER WITH ASYNCHRONOUS PARALLEL LOAD AND CLEAR-

r1

PARALLEL INPUT -t---+----.

Binary counter using synchronous 2
bit stages with trickle down between
stages illustrates method of utilizing
dual JK flip-flops having common
clocks in counter applications.

I
I
I
I

I
I

I
I

COUNT INPUT--!------+-+-'MASTER CLEAR ------o>---t-Q-~~~-->-Q------+--+Q-~~~~

1

2

-

4

PARALLEL OUTPUT - -3·87

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS•PACKAGE OUTLINES
U6A
U6B

PHYSICAL DIMENSIONSSIMILAR TO
JEDEC (T0-116) Outline
Duai ln·Line Package

PHYSICAL DIMENSIONS
16 Lead Dual In-Line

r-.310-1

IF.290

=ii

R

;
.

.Oil
.009

L.315__J·.125Ll

I

NOM:

I

I

.1001
MIN.

+=

T

NOTE I

.llO
.090

_i_

--r-

.110
.090

~:~~-1
NOTE: 1. Board drilling dimensions should ·equal yourpractice for a conventional ,;020 inch.· diame·ter lead.

U31

U3L

CERPAK 14 LEAD

CERPAK 16 LEAD
I e

ll

_l_
;

-,

i--.370--.-1.250

1-- .260 ---1

f.050 .26 0
.240

..·..

7 8
Jf I

.240

~

l:

r

1 14

_:_l_
.020J
.015 f-.370.0060.250.0~35 _)_

-

.16

.409

~L ..

!

.0050

.065
.050

.200

8

-J .--

.0035

9

-

L~J I
·200

.050

t

t=~-==-1'--~~--'l~-'-'---1.-.-~·
I~-283
~
.
.247

.025

TYP

ORDER· INFORMATION
To order Transistor-Transistor Micrologic elements specify
U31XXXX51X for 14-pin Flat package
U6AXXXX51X for 14:pin Dual ln-Une package. U3LXXXX5lX for 16-pin Flat package
U6BXXXX51X for 16-pin Dual In-Line package
Where XXXX is the four-digit number d~noting the specific element desired and 51X is for -55°C to +125°C temperature.

3-88

'
-~i

TRANSISTOR-TRANSISTOR MICROLOGIC®
INTEGRATED CIRCUITSA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTTEMPERATURE RANGE: 0°C to 75°C

duces the ringing which can result from long lines and impedance mismatches. The binary elements are of a JK, DC master slave design and will
toggle at 40 MHz, except for the 9000 element. The 9000 has capacitors
purposely incorporated in the design to increase its set-up time and provide
it with considerable immunity to long clock skew. Due to the longer set-up
time the 9000 toggle frequency is 20 MHz. A common JK input is incorpor-

GENERAL DESCRIPTION

The Fairchild 9000 Series of TTµL circuits is designed to be used in any
digital system where good noise immunity, high speed, medium power andhigh fan-out performance is required. The line is characterized by a broad
number of functions available in a variety of packages. The basic elementsof the family are active low level output AND gates commonly known as
NANO gates.
Typical high level noise immunity of every device in the family is 1.9 V andtypical low level noise immunity is 0.9 V. Worst case immunity is 400 mVover the entire temperature range. Power dissipation is typically 11 mW pergate function at a 50% duty cycle, and the average propagation delay is
7 nanoseconds per gate function. A single 5 V ± 5 per cent power supply isused with the circuits.

ated on all binary elements to provide data entry inhibit/enable. The input
to the clock on each element is buffered to reduce the clock input loading.
The Vee and ground terminals of all devices are located on diagonal cornersof the package which allows two degrees of freedom in routing of power andground leads on the PC boards. Special care has been taken in establishing
pin-outs for the flip-flop so as to minimize cross-overs when laying out
common dynamic functions with these elements. Simple loading rules areincorporated so that the fan-in and fan-out capability of each device will bequickly established.

The gates were designed to provide low output impedance in both high andlow states which results in good capacitive drive capability and good immunity to crosstalk. The output impedance in the low state is about IO ohms

The 9000 series TTµL is part of the CCSL family and is compatible with allother Fairchild DTµL, Low Power DTµL and MSI devices as well as the more
complex functions which will be available in the future.

and in the high state, about 20 ohms. To further enhance noise immunity,
all inputs of all devices incorporate diode clamps which considerably re-

TABLE OF CONTENTS

ABSOLUTE MAXIMUM RATINGS, LOGIC DIAGRAMS --····----- _Page.. 2. 3Page
AND-OR-INVERT GATES and EXTENDER ....................................................8 -109005 Dual 2-2-input AND-OR-INVERT Gate
one half extendable
9008 Single Extendable 2-2-2-3 AND-OR-INVERT Gate
9006 Dual 4-input OR Extender

Explanation of Loading Rules andprovisions for Unused Inputs

NAND GATES and HEX INVERTER ...............................................................4 • 59002 Quad 2-input gate
9003 Triple 3-input gate
9004 Dual 4-input gate
9007 Single 8-input gate
9016 Hex Inverter

JK FLIP-FLOPS ----------------------------··-···---·----- ........................................ 11·16
9000 JK Flip-Flop9001 JK Flip-Flop
9020 Dual JK Flip-Flop9022 Dual JK Flip-Flop

APPLICATIONS ................................................................................................. 17
NAND BUFFER ............................................................................................& • 7
ORDER AND PACKAGE INFORMATION ............................................................. 189009 Dual 4-input buffer

SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-89

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
9000 SERIES· TTµL INTEGRATED CIRCUITSNAND GATES

9016

9002

9003

--+---~~M>-+-~45">0----+-69-+----1»-+-e

4--1----1

5--t-----t

6

9
10

11 -+--1~0-----+--1013

1212--+---i
13 - - t - - - - t _ _ J

11

1
2
13
3
4
5
9
10

9
10
12
13

9007

9009
2
4
5

3
4
10

6

8
9
10
12
13

11
8

8

BUFFER

9004
6

6

11

NAND GATES

1
2
4
5

12

12
13

8

AND-OR-INVERT GATES AND EXTENDER
9005

9008
13
I

1
13
9
10

9006
13
1
2
3

8
...,........_..__llEMIT.
12COLL.

12COLL.
11 EMIT.

8

2

9
10

3
6
4
5

11 EMIT.
12COLL.

4 - - M ' -....

5
6 -........-

4
5
6

8

Vee= Pin 14
Gnd =Pin 7

9 COLL.
lOEMIT.

(extender for use with 9005 & 9008)

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Yee Pin Potential to Ground (See Note 1)
Input Voltage (D.C.) (See Note 2)
Input Current (See Note 2)
Output Voltage, Output Normally High
Current Into Output Terminal, Output Low (except 9009)
Current Into Output Terminal, Output Low 9009

-65°C to + 150°C
0°Cto +75°C-0.5 vto +s.o v-0.5 V to +5.5 V-30 mA to +5.0 mA
0 V to +Vee value
50mA
lOOmA

NOTE 1
The maximum Vee value of 8.0 volts is not the primary factor in determining the maximum Vee which may be applied to a number of interconnected
devices. The voltage at a high output is approximately 2 V8e's below the Vee voltage, so the primary limit on the Vee is that the voltage· at any input
may not go above 5.5 V unless the current is limited, so this effectively limits the system Vee to approximately 7.0 volts.

NOTE 2
Because of the input clamp diodes, excess current can be drawn out of the inputs if the D.C. input voltage is more negative than -0.5 V. The diodeis designed to clamp off large negative A.C. swings associated with fast fall times and long lines. This maximum rating is intended only to limit thesteady state input voltage and current.

3-90

FAIRCHILD "TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
9000 SERI.ES TTµL INTEGRATED CIRCUITS
9000

9001

SINGLE FLIP·FLOPS

4

4

12

5
12

6

l

3.

0

10
11

Cp

11

Vee= Pin 14
Gnd=Pin 7

13----- ----

010~-------------- 9020

13

9022

DUAL FLIP·FLOPS

11

Sp

Sp

10

6

10
13

T

0

7

11

FFI

0

12

T

FF2

0

.c

Cp

15

0
12

Co

15

Vcc=Pin 16
Gnd= Pin 8

LOADING RULES

at the low logic level and is 60 µA maximum at the high logic level.
In the case where unused inputs of an AND gate are shorted to a driven
input, the high logic level input load factor for the inputs will be thenumber of inputs shorted together times the high logic input load factor
for one input. The low rogic level input load factor for the in puts will be
the same as that for a single input.

In this data sheet the following notation has been chosen to indicate
the input loading and output driv~ for all logic elements.
INPUTSOUTPUTS

A/B

X/Y
LOGIC ELEMENTUNUSED INPUTS

Proper termination of unused inputs will result in maximum operating
speed. Substantial degradation of tum-on delay may occur if unused
inputs are left open.
The following are acceptable ways to terminate unused inputs:

Where
A high logic level input load factor
B =low logic level.input load factor
X =high logic level.output drive factor
Y = low logic level output drive factor
When checking for loading violations it is only necessary .to insure thatthe sum of the high logic level input load factors at any node does
not exceed the high logic level output drive factor at that node. The
same is true for low logfo level load and drive factors. These rules apply
only within the TTµL 9000 series. For loading rules to other Fairchildlogic elements refer to the CCSL Composite Data Sheet.
Multiplying the factor with the appropriate current per unit load gives
the input loading or output drive in terms of current. For the TTµL
circuits of this data sheet, current per unit load is -1.6 mA maximum=

1. Tie the input to a used input on the same gate. The TTµL 9000. series
has made special provision for this method by offering extra highlevel drive factor on all outputs.
2. Tie the input to Yee through a resistor. This resistor should be chosen
to keep the input current within absolute maximum ratings for any
possible extreme of the Yee supply. More than one input may beterminated through one resistor.
3. Tie inputs to a separate supply between 4.5 and 2.4 Y, if one should
be available.
4. Tie the inputs to the output of an unused gate. The unused gate must
provide a constant high level output.

3-91.

I

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INJEGRATED CIRCUITS.
.

'..

.,

.

NANO GATE~9002, 9003, 9004 AND 9007
HEX INVERTER-·. 9016
. .
The 9002, 9003, 9004 and 9007 are active loW :level output AND gafes eoinmonly known as NANO gates. The 9016 is a hex inverter with input andoutput characteristics identical to the 9002, 90Q3, 9004 and 9007. This variety of gate combinations provides the system designer the utmost in logic
flexibility and enables a reduction of package ci>unt'.
·.... ,... ·.
Fig.ure 1-LOGIC SYMBOL AND PIN ·CONFIGURATIONS

9016

9002
2

1
2

4

3
5

6

9

8

11

10

13

' 12

9003
3

4

5

6

9

8.

.. 12

11

9004

1
2
13
3

·Vee= PIN 14, GND =PIN 7

'

10

6

6

9
10
12
13

5
9
lQ

13

1
2

12

4

9007.

8

11

8

2
3
4 ---..._____.
10--1u--==
11
12
13

8

·

Figure 3-LOADING FAGTORS

Figure 2"""'."BASIC GATE CIRCUIT_-,.,:.··

INPUT<>--------""

*

I I
I· I

o--

---.,-----J :I

1.........'VV11--<.....,.-<> OUTPUT

. 5

I

.

I

**
I

·.t-·

.;..,__

R ..

.o--- ---~---t--.1
I.·.----"···2ono,,,,,,~~~..,---3__)~··
---

0.

I

·.t-·

Nominal Resistor Values

R1 = Rs = 4.0 kO
lb= 1.5 kO
R1= 1500
R4=800
R&= 1.25 kO*Number of inputs depends on the gate.

_;··'

ELECTRICAL CHARACTERISTICS 9002, 9003, 9004, 9007 AND 9016 (TA= 0°C to 75°C, Yee= 5.0 Y ±5%)SYMBOLCHARACTERISTIC

0°C
MIN. MAX.

LIMITS
25°C
MIN. TYP. MAX.

75°C
MIN. MAX.

UNITS

COND.ITIONS

VoH

Output High Voltage

2.4

2.4

2.4

Volts

Vol

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.85

0.85

0.85

IF

Input Load Current

,71.6
-1.41

IR

Input Leakage Current-1.0 -1.6-0.91 -1.41
1060. _;l,6
-1.41
60

lpo

Vee Current, Gate On(each gate)
Vee Current, Gate Off(each gate)
Switching Speed
SWitCliTngSpeicf

Vee =4.75V
loH = -L2mA
Inputs at~ (see below)
Vee=--S-:25Y !m = l6;0mA ~=5.25V
Vee = 4.75 v IOL = 14.1 mA
Inputs at Vll::L (see below)
Guaranteed input highthreshold for all inputs
Guaranteed input low
threshold for all inputs
Vee= 5.25V
VF= 0.45V
Yee_= 4.75V
5.25 V on other i'!P_uts
Vee= 5.25V
VR =4.5V
GND on other inputs
Inputs high

!e_d+

-

2.9

0.45

. iu

'""",,._

..

.O.Zl

0.45

l.~ :

1.8,.

6.1
1.7

..

3.0
3.0

... 0.45·: ,'.

3.6

6.1

6.1

1.07

1.7

1.7 '•.

13
15
3-92

Volts

Volts
Volts

mA
p.A

mA
ns
ns

Inputs at gnd=

Vee= 5.0V

Yee 5.0 V, See Figure 11
CL= 15 pf

FAIRCHILD TRANSISTOR-TRANSISTOR ·MICROLOGIC® INTEGRATED CIRCUITS
9002, 9003, 9Q04, 9007 AND 9016
TYPICAL INPUT AND 01.JTPUT CHARACTERISTICSOUTPUT VOLTAGE VERSUSINPUT VOLTAGEOUTPUT CURRENT VERSUSOUTPUT VOLTAQE(OUTPUT HIGH)INPUT CURRENT VERSUSINPOT yclLTAGE
2.0 ,....-,.---.--.-..,..-T"-.--r--....l-.-...,

..J

~

~

,

~~

5' 0 1--+--+--+--+iI-201---1--+--i---1-- , ...

~ -401--+--+-..i--+---1-+--+-~

a~-8.01--11--1--4-+-+-l--+--1--+-~_a~ao-8.0 ~f--1---+-+-l--t--+--+-~

i

~

I

~

-1~2.0...,.............0,.......__,.,2.0........_4.0...__..__,,8.0~........,..8.0

3.0

80

I

B

-+-+-+-t--+--+-~

i

1.0
2.0
VIN-INPUT voq~GE-VOLTS

INPll~ HIGH

1,__....._.__.__...__..-+--+---+--t-~"'B-4.0t--......_.__

Vcc•5.0V .

lllPllTS AT 4lllD.

Ol--t-75"~:~~,...f-.c-~~C~--+oor!!--l-~!ii;-2.0100

Vee •5.0y

Yee• 5.0 v--+--+--+--+-+-<lf--1--1
I

OUTPUT CURRENT VERSUSOUTPUT VOLTAGE(OUTPUT i.QW)

L
,,,.

eo
40
20

j

1
IL

75';f;_

v

~

1c

.L
l
0.5

1.0

1.5

VIN ·INPUT VOLTAGE ·VOLTS

YouT·OUTPUT VOLTAGE-VOLTS

VouT -OUTPUT VOLTAGE -VOi.TS

Fig. 5

Fig. 6

Fig. 7

Fig. 4

LQGIC LEVELS ANI) NOISE IMMUNITYWORST c;A:R~IC LEVELSWORST CASE HIGH LEVELNOISE IMMUNITY VERSUS.AMBIENT TEMPERATURE

AMBIENT TEMPERATURE

3.0 i:::;:;;:c;~c::;;;i:::;=c:;::::c=i=~1-"er •; Vile• ~25~, 'f" •1-~ lllAl-+--F.O.• 20 HIGH LEVEL UWIS

2.51-l-Vilit A~•4.75V, IOJt•-12111Al-t-;2.01-1-+-+-+-t--+--+--+--t--1-+~~ 2.0I:::: ~-+-+-I-+-+--+-+-+-+-~

iui-+--+--+-1-+--+--+-1-+--+-~

ii u

111 12

I

•

I

0.5

I~

i 1-i~-t+--=::;l;o-+-"Fi..--9~ 0.8 ~
Vcc.•t.75.!-i--+-t""". J..-1-f-i).O~l--+-~~L-+-l-+--+--+-1-+-+-+-1

Lvri.. FOR ..,.F.0.•10,
4.75v Hccs5.25v..,.
]"

f·· l--+--1~--t-+-+-+-+-+-I~ 0.4!0.21--f--lf--1---+-+-l--t--t-~........-+--+-+-+-+--+-+-+-+--+--<
50

25

0

75

50

o

z.o

(Q

8.0

8.Q

Tr-ENT TE~TUllE-"C

Fig. 8Fi~.

Fig. 10

9SWITCHING CHA~CTERISTl<;S
Figure 11-tpd TEST ~IRCUIT~c

SWITCHING WAVEFORM

2.0k.11
PULSE
INPUT

n----f-o Your

10-.....--....,----1.~,

f""' 1.0 MHz
Amp""' 4;0 V
Width ""' 200 ns
t 1 t,SlO ns

I~5pF*

=

,,,.

· ..-

•includes •II probe and jig capacitance

WORST CASE TURN OFF DEL4Y
VERSUS AMBIENT TEMPERATURE
30~--~~.........~~-~

251-+-+--+-+--I--+--+--+-+-+-+-~

~ 20

f

.....!-"'"~

l--+-1--<--........__._~

b~..i.--t-i==i--+-+-1-+-+-+-+-1~ 15,_~~.~~~~·'tll.l---4-+-+=::J;.-1~C..· 1~'1!_..1..-+-

I 10 l-+-+--l-+--1--+-l--+-+-t-+-~
+ .

:J.

1-+-+--+-I+--1-+--+--+-+-+-+-~

5.0 ,___.._.__,_ lllN. AT CL • 15 pF -+--+--+--<
50

Ta-AllllENT TEllPEflATURE-"C

Tr.AMBIENT TEMPERATURE-'C

Fig. 12

fig. 13
3-93

iii

2.0

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® · INTEGRATED· CIRCUITSNAND JIUFFER -9009

The 9009 i$ a power gate capable of sinking and sourcing large currents for high fanout applications. Logically it is the same as the 9004.

Fig. lFig. 2LOGIC DIAGRAM AND PINCONFIGURATIONCIRCUIT DIAGRAM(One Gate)Vee
1------.
2 --t----,_::::i4. --1----::1

5--+-..........

9------.
10 -----,___i
12 --+---T"::J
13--+----'

Vcc=PIN 14
GND =PIN7

Fig. 3LOADING FACTORS~~~____,..---...)

212

212--~--

Nominal Resistor Values------- 60/30

Rt =2.0kO
R2=5600R•=l500

114=500
Rs=4.0 kO
R•=5000

ELECTRICAL CffAltACTERISTICS 9009 (TA= 0°C to 75°C, Yee= 5.0 V ±5%)SYMBOLCHARACTERISTIC

0°C
MIN. MAX.

LIMITS
25°C
MIN. TYP. MAX.

75°C
MIN. MAX.

UNITS

YoH

Output High Voltage

2.4

2.4

2.4

Volts

Vol

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.85

0.85

0.85

IF

lnp1.1t Load Current

-3.2
-2.82

IR

Input Leakage Current-2.0 -3.2-1.82 -2.82
120
20

-3.2
-2.82
120

lpo

Yee Current, Gate On(each gitte)
Yee Current, Gate Off(each gate)
SWitching Speed
SWitctiing SJ>eed

14.6

8.6

14.6

14.6

3.4

2.15

3.4

3.4

-.;:;:
\xi-

0.45

1.9

2.9
0.21

L8

3.0
-z:ir

0.45

0.45

l.6

17
13

3-94

CONDITIONSYee =4.75V
10 H = -3.6 mA .
Inputs at~ (see below)
Volts
Yee = 5.25 V !oi. = 48.0 mA ~=5.25V
Yee= 4.75 V 10 L = 42.3 mA
Inputs at VJH (see below)
Volts · Guaranteed input highthreshold for all irm_uts
Volts
Guaranteed input low
threshold for all iiywts
VF==0.45V
Yee= 5.25V
mA
5.25 Von other inputs
Yee=4.75VJ
p.A
YR :=4.5V
Yee= 5.25V
GND on other inputs
Inputs high

mA
ns
ns

Inputs at gnd

Yce=5.0V

Vee = 5.0 V, See Figure 11. Ct= 15pF

FAIRCHILD -TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
9009
TYPICAL INPUT AND OUTPUT CHARACTERISTICS
INPUT CURRENT VERSUSINPUT VOLTAGEOUTPUT VOLTAGE VERSUSINPUT VOLTAGE
2.0

..

0

E

.!. -2.0~"'B -4.o

z

~~~~

...-1

20

F

f-Vcc•5.ov

1

5 -60

-8.0

2.0

I-

~

g
-

-10
-2.0

2.0

4.0

6.0

8.0

11{

-80 1--

vz

i3

~ 80

t

ill

~ 40

2.0

3.0

4.0

5.0

6.0

25!e"-1o•e---1i---1

8§ 120

5•c
o•c

1.0

75"C

.L'.'.1

i-

I

!i
...

~5'C

t--100-1.0 0

~
L.!--

1160

-JJL

~ -40

-~

Vcc•5.ov
INPUTS HIGHv

15•c
25'C_...
o·c- ,,

~

-

~

1.0

T

0

I

!z -20

T-6.o

3.0

200
Vcc•5.ov
INPUTS AT GNO.

o•c

...

OUTPUT CURRENT VERSUSOUTPUT VOLTAGE(OUTPUT LOW)OUTPUT CURRENT VERSUSOUTPUT VOLTAGE

7.0

l-

r

0.5

1.0

1.5

VIN - INPUT VOLTAGE-VOLTS

V1N-INPUT VOLTAGE-VOLTS

VouT -OUTPUT VOLTAGE-VOLTS

Your -OUTPUT VOLTAGE - VOLTS

Fig. 4

Fig. 5

Fig. 6

Fig. 7LOGIC LEVELS AND NOISE IMMUNITYWORST CASE LOGIC LEVELSVERSUSAMBIENT TEMPERATURE
3.0

1--VOH AT Vcc-5.25 v, IoH' -3.6mA

J. l l l _L l l l l +-

2.5

I--

1--VOH AT Vee. 4.75V, IoH' -3.6mA t--I--ll

F.O. • 60 HIGH LEVEL LOAOS

t--+---+---+---+--+o•c s TA s 15•c ·gI!! 2.0,_I

to t--+---+--+--+--+4.75 v •Vee• 5.25 v

1----+-+-t--+--+--t-1----+--+--+-----t-----i!i 1.61----+-+-+--+--+-+-l----+--+--+-----t-----i

t--1.

ii

0.81-<;;:::j--j-.....---+---+---+-+-+-+-+-+---1--+... 1.2 t---+-+--+--+-1 Ve~~-1-f='t---i

1--;1ii

v

!!

II

~

t-- 1vILI
-!-I

II

0.5

WORST CASE
LOW LEVEL NOISE IMMUNITYVERSUS FANOUTWORSt CASE HIGH LEVELNOISE IMMUNITY VERSUSAMBIENT TEMPERATURE~=1Vol FOR F.O•• 30, 4.75 v • Vee '5.25'

1--r~ o.8 _j.--1-1

o.61---t--t--+-1"'---t-=i-....,,,.,_._,=+-N-+-+-+---I~~++-=::l-.-4-'f='-1
v e,4.75~~~ 0.41--1~-+--l--+-+-l--+-+--+-+-l

0.21--+--+--+-+-+--+-+-+--1--1

n i 111111111J
25

12

75

50

TA-AMBIENT TEMPERATUAE-'e

18

24

TA-AMBIENT TEMPERATURE-'e

LOW LEVEL FANOUT, TT~L UNIT LOAOS

Fig. 9Fig. 10

Fig. 830

SWITCHING CHARACTERISTICS
Fig. 11

tpd TEST CIRCUIT

SWITCHING WAVEFORM

PULSE
INPUT
0

f"" 1.0 MHz

Alllp"" 4.0 V
Width "" 200 ns
t1
t,:$10 ns=

WORST CASE TURN ON DELAY
VERSUS AMBIENT TEMPERATURE

WORST CASE TURN OFF DELAY
VERSUS AMBIENT TEMPERATURE
36+

Vcc•5.ov!-I
SEE FIG.11
MAX. AT CL• lOOpF

30

I

5' 24 t-0

g;:
z
z

0

18

a:

~ 12 !'-;.....

MAX.AT CL•15pf+--f---!-I~

S.O 1--4~--+--+--'--MIN. AT CL•15pf

t---+--t-6.0

o~~~~~~~~~~

0

0

25
50
TA-AMBIENT TEMPERATURE-'C

75-

MIN. AT Cl•l5pf

l
0

_l

so

25

[A-AMBIENT TEMPERATVRE-°C

Fig. 12Fig. 13

3-95

f---!-I75

2.0

FAIRCHILD TRANSISTOR~TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
EXTENDABLE AND-OR-INVERT GATES-9005, 9008
EXTENDER-9006
The TIµL 9005 and 9008 are AND-OR~INVERT gates which may be OR extended with the use of the 9006. For noise immunity and operating level curves,refer to ttie gate section on Page 4 and 5.
Figure !-LOGIC.DIAGRAMS AND LOADING FACTORSThe numbers by each input and output give the input loading and output drive capability. For complete explanation see Page 3.

9005

9008

1.511.5
1.511.5
1.511.5
1.511.5

13

a

9

11

10

12

1.511.5
20/.10•EMIT.

1.5/1.5•Coll.

1.511.5111
1/1

1.511.5. 1.'511.5

2
3
6

4

NON·EXTENDABLE GATE

1~
1.s11.s·~
1.511.52
12COLL

1.5/l.5
1.5/1.5

9

10

11

.

11 - •EMIT.
-~

12 ....,.. *COLL.
-~

VGG =Pin 14

Gnd,,,.. Pin 7

4.

1.5./1.5~
96.

1,5/1.S
1.5/1.5 .
1.511.5

8

lO

OLL

c

VGG =Pin 14
Gnd=Pin 7•four Extenders (9006) may betied to these terminals

Figure 2-CIRCUIT DIAGRAMS

9005
Vee
2

10------'
130--+-----'

3

990----~'

10~-~--~

10 0---1---....1

VGG= Pin 14

4<>-1,___

Gnd =Pin 7

so-+---'

6 -i--t--..-

Typical Resistor Values
R1 =Ra =·R•= Rs= 2.6 ldl
R•=8000
Rt; ... 150 0
R1=800
Ra =4.0 kO
R9=6650o-·

EXTENDABLE GATE .

2 ,,______,. r

9006~- o---1----'

vcc
R- 2.6 kO Typical
4"-----''T~----~

50---1---.....1

NON-EXTENDABLE GATE
Typical Resistor Values
R1 = Rl = 2.6 kO
R2=8000
ff.= R11=1500
Rs= R12=80 0·Vcc=Piri 14
Gnd :=Pin 7.

Two in a package& = Rs = Rio = Rll = 4.0 kO
R1=6650
R9 = 1.5 ldl
R14 ""'.' 1.25 kO

Vee= Pin 14
Gnd= Pin7

3-96

.

EMIT.

Gnd=Pin 7•four Extenders (9006) may betied to these terminals

.

EMIT.

,,,...~8- 20110

2

1.5/l.5
1.511.5
1.511.5

20110

Vee= Pin 14·513

1.5 /1.5

EXTENDABLE GATE
1/1
1/1

9006

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSELECTRICAL CHARACTERISTICS 9005, 9006 AND 9008 (TA= 0°C to 75°C, Vee= 5.0 v ±5%)SYMBOLCHARACTERISTIC

0°c
MIN. MAX.

LIMITS
25°c
MIN. TYP. MAX.

75°C
MIN. MAX.

UNITS

VoH

Output High Voltage

2.4

2.4

2.4

Volts

Vee =4.75V,
loH = ·-1.2 mA
V1L = value indicated below on this table

VoL

Output Low Voltage

0.45

Volts

Vee= 5.25V,
Vee =4.75V,

VIH

Input High Voltage

Volts

Guaranteed input high threshold for all inputs

VIL

Input Low Voltage

0.85

0.85

0.85

Volts

Guaranteed input low threshold for all inputs

IF

Input Load Current
9005 Non-Extendable Gate

-1.6
-1.41

-1.04 -1.6
-0.79 -1.41

-1.6
-1.41

mA

Vee= 5.25V
Vee =4.75V

Input Load Current
9005 Extendable Gates
and Extender

-2.4
-2.12

-1.56 -2.4
-1.19 -2.12

-2.4
-2.12

mA

Vee= 5.25V-Vee = 4:75-v

Input Leakage Current
9005 Non-Extendable Gate

5.0

60

60

µA

Tn put Leakage Current
Extendable Gates and Extender

7.5

90

90

IR

lpo

.Iii po

2.9

0.45

0.2

0.45

u

1.9

1.6

Voe Current,Gate "ON"9005 Non-Extendable Gate
9005 Extendable Gate
9008

7.7
13.6
17.7

4.5
7.6
9.3

7.7
13.6
17.7

7.7
13.6
17.7

V0 e Current, Gate "OFF"9005 Non-Extendable Gate
9005 Extendable Gate
9008

3.4
5.1
10.2

2.2
3.3
6.6

3.4
5.1
10.2

3.4
5.1
10.2

Extra Current Drain
when one 9006 Extenderis attached to a
9005 G~te "ON"

2.05

1.08

2.05

Extra Current Drain
when one 9006 Extenderis attached to a
9005 Gate "OFF"

2.54

1.65

2.54

CONDITIONS & COMMENTS

IOL = 16.0 mA
loL = 14.1 mA

VF= 0.45 V
5.25 Vonother inputs

VR = 4.5 v
Vee= 4.75 V
Gnd on all other inputs

mA

Vee= 5.0V
All inputs open

mA

Vee= 5.0V
All inputs except
extender inputs gnd.

2.05

mA

Vee= 5.0V
All inputs high

2.54

mA

V,ee = 5.0V
All inputs grounded

Note: Output characteristics above apply to a 9005 (both gates) or a 9008.
Input characteristics above apply to a 9005 (both gates) or a 9008 using either the internal gates or an external 9006 extender.

9005, 9006, 9008 TYPICAL INPUT-OUTPUT CHARACTERISTICSOUTPUT VOLTAGE VERSUSINPUT VOLTAGE

INPUT CURRENT VERSUSINPUT VOLTAGE(EXTENDABLE GATES*)OUTPUT CURRENT VERSUSOUTPUT VOLTAGE (OUTPUT LOW)OUTPUT CURRENT VERSUSOUTPUT VOLTAGE (OUTPUT HIGH)
200

20

o1--t-'-1r~~c~~~l.1'1<.-1-"-1-"-1--th.:fc-+--+--+--+--1«~ _ 2 1--~~.,i----t--+1'~125""•c'-+--+--t---+---1.3~

Vcc·s.ov
INPUTS AT GND.

«

0

O'C

E
I

....
z

~ -20

-4 1--.--t--t--1t--1f--lf--l--t--t--I

"'
i:l
....

T -61--1t--1--t--+--+-4---+--+--+--1

:!!

_?E

z

~

-8t-llt--l--t--1f--lf--l--t--t--t--I

~

I

rs•c
25°C f - -t---1

~

---60

75•~

rJ•c

I

__.J_

~ -40

-lq_~2~~o~~~~~-+--+-~

VIN-INPUT VOLTAGE-VOLTS

Ycc·s.ov

i..-1 i! 160 INPUTS HIGH

IL

25·~

....
z

p

...~ 120
:0

"

,

~ 80
s

E

5I

ll

-ao-1

2s•c

~r-

O' c

IL

~ 40

Ne

l

+-1

00

0.4

0.8

1.2

1.6

V1N - INPUT VOLTAGE -VOLTS

Your -OUTPUT VOLTAGE -VOLTS

Your-OUTPUT VOLTAGE-VOLTS

Fig. 4

Fig. 5

Fig. 6

Fig. 3*Curves on Page 5 apply to 9005 nonextendable gate.

3-97

2.0

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSAC CHARACTERISTICS
tpd TEST CIRCUITS

9005 NON·EXTENDABLE GATE
Fig. 79005 OR 9008 EXTENDABLE GATE

Fig. 8_n_1•1.0MHz
AMP•4.0V
WIDTH•200ns
t, • l1SlOns

f :o].0 MHz
AMP=4.0V
WIOTH.,200 ns
t, 0 11s1ons*Includes all probe and/or jig capacitance.

Fig. 9*Includes all probe and/or jig capacitance.

9006 EXTENDER
Vee

SWITCHING WAVEFORM

2.0kll".,. .I

9009

NOTES:
With switch in position (1) measure !pd
of 9005. With switch in position (2) meas·
ure !pd (9005)
Li.tpd (9006). Capacitances include probe and jig capacitances.

+*Includes all probe and/or jig capacitance.

AC CHARACTERISTICS (TA = 25°C)
LIMITS
SYMBOL

MIN.

MAX.

UNITS

CONDITIONS & COMMENTS.!e..d+
tpd-

3.0
-g:u-

15
15

ns

Vee = 5.0 V, CL = 15 pF
9005 Nonextendable gate only, See. Fig. 7.!e..ci+

3.0
3.0

18
13

ns

tpd~

Vee= 5.0 V, CL = 15 pF, CN = 5.0 pF
9005 Extendable gate and 9008, See Fig. 8.:itpiJ+.:itpd-5.0

ns...:.T.(f9006 only
The 9006 is tested by measuring its
propagation time through the 9005.

-3.0

o.cr

The tpd readings shall not exceed
the 9005 readings by the specified
amount. See Fig. 9.

Symbols are defined in the test circuit.
.l.

WORST CASE TURN OFF DELAY
OF EXTENDABLE GATEVERSUS TEMPERATURE
9005, 9008 l--t--+-+--+-+---4--+-l481--1--+-+--+--+-+---t-1 9005

Vcc•5.ov

40

SEE FIG. 8 +--t-1--+-+--+--+-+--1

WORST CASE TURN ON DELAY
OF NONEXTENDABLE GATEVERSUS TEMPERATURE

WORST CASE TURN OFF DELAY
OF NONEXTENDABLE GATEVERSUS TEMPERATURE

WORST CASE TURN ON DELAY
OF EXTENDABLE GATEVERSUS TEMPERATURE

....,

48

401--1--t-+--t--+-+---t-+ SEE FIG. 7 -1

40

Vcc•5.ov

40 1-+--+-+--+--+--+-<f--t 9005, 9008

Vcc•5.ov

1--+-t--+--+--+-r-f--t SEE FIG. 8;

I~

24r--t--+--+--·MAX.AT

1

lG

~

).
8.0
o~~~_.__.__.__.__.__.__._-'-'-'

0

25

50

TA- AMBIENT TEMPERATURE- 'C

Fig. 1075

t-+--+-+-_,~,_IN+.i_-A/+-cL_,•1,_·15-tpF-=-:~'"=--::

o~~-+--+-~~~~-+-~

0

25

50

321--1--+-+--t--+-+---t-1--+-+--t-1

75

TA -AMBIENT TEMPERATURE -•c

CL•i50~3-98

11321--1--+-+--+-+-+---1--+11--+-+--+--1

I I

MAX.AT CL•15pF

1)

8.0 ,...._,__,__,_ MIN. AT CL•15pF-t--j~ 5:0:-s~f FIG. 7 . t-+-1

i!I
Nf--'f-+-;;;;;lt:Fi:::-"'AX. AT CL• 150pF-t--t--t--;
i!5 24~~~-+--+--+--j--+---t--+--+-+-t-1'---1+r:ri.2

l&f"i-t-+..;M::AX;.A::_T.j:1CL:::_•1~5p4F;;;;;;j::::j::::j::;Jllll

ao 1--1--+-+--+-+--+--l--+--+-+--+--1
MIN. AT CL•l5pF

o~--+_..._...,._~+-~~~~

0

25
50
TA-AMBIENT TEMPERATURE-'C

Fig. 12Fig. 11sf

r--t-+---+-+--1-+J;;r--r

75

25

50

TA-AMBIENT TEMPERATURE-'C

Fig. 1375

l.___ _;..._;FA_l_RC'--H-'-l_LD_._T_R_AN_S_l_St_O_R_~T_R_A_N_Sl_ST_O_R_M_IC_R_O_L_OG_l_C_®_l_N_TE_G_R_A_TE_D_C_IR_C_U_IT_S_ ___,
J-K FLIP-FLOPS.-9000, 9001
DUAL J-K FLIP·FLOPS-9020, 9022
GENERAL DESCRIPTION
A joint (JK) input is provided for all flip-flops in this family. This common
input removes the necessity of gating the clock signal with an external gate
in many applications. This not only reduces package count, but also reduces
the possibility of clock skew problems, since with internal gating provided,
all flip.flops may be driven from a common clock line. Several TTµL drivers
may be used in parallel to drive .this common clock line, if the load exceeds
the F.O. capability of the 9009 buffer.
The asynchronous inputs provide ability to control the state of the flip-flop
independent of static conditions of the clock and synchronous inputs. Bothasynchronous set and clear are provided on all flip-flops except the 9020,
which because of a logic trade-off has only clear inputs. The set or clear pin
being low absolutely guarantees that one output will be high, but if opposing
data is present at the synchronous inputs and the flip.flop is clocked, thelow output may momentarily spike high synchronous with a positive transi·tion of the clock. If the low output of the flip.flop is connected to otherflip-flop inputs clocked from the same line, the spike will be masked by theclock. If the clock is suspended during the time when the asynchronous
inputs are activated, no spike will occur. When the spikes can cause prob·lems, a simple solution is to common the joint JK inputs with the synchronous set or reset signal.

The TTµL 9000 series has four flip-flops to satisfy the storage requirementsof a logic system. All are master-slave JK designs and have the same highspeed and high noise immunity as the rest of the 9000 series. As with thegates, all inputs have diode clamps to reduce ringing caused by long lines
and impedance mismatches.
The JK type flip-flop was chosen for all flip-flop elements in this family
because of its inherent logic power. The input function required to produce· a given sequence of st1,1tes for a JK flip-flop will, in general, contain more
"don't care" conditions than the corresponding function for an RS flip-flop.
These additional "don't care" conditions will, in most cases, reduce theamount of gating. elements required to implement the input function.
The master-slave design offers the advantage of a DC threshold on the clock
input initiating the transition of the outputs, so that careful control of clock
pulse rise and fall times is not required.
Data is accepted by the master while the clock is in the low state. Refer. to
the truth table for definition of "HIGH" and "LOW" data. Transfer from themaster to the slav.e occurs on the low to high transition of the clock. Whenthe clock is high, the J and K inputs are inhibited.

Figure 1-LOGIC DIAGRAMS AND LOADING FACTORS
9000

i2

i,i

9

212
i,i

3

i,i
i,i

2.7/2.1

4

1/1
iti
i,i

9020
4~o-'i~4_,.._ _ _~----------.

5

10
11

2.7f2.7i,1 o--3L..4-I

So i

s

Co 0

a 2011 0i,12011 020tio

i,1 0 - - - + - - 1
1,1 .,___,4-~-/

20110

20tio

0

vcc·is
GN0•8

GND=7

9001
i1i

11.1
212
l/1
lti
1,1

20/io

i3

Vee= 14

i11
i,i

9

9022

4
5
i2

So i

s 201i 0

1/1
20/io

20/io

9
1
3

Co 0

10

11

2.7/2.7

20110

8 20/1009i3Vee-is
GNO•B

Vee= 14
GND=7

Figure 2-FUNCTIONAL LOGIC DIAGRAMS
9020/9022

900,0/9001

So 9022 ONLYq

So 9022 ONLY.
'?
I
I

Ji
J2

T

T

JK
Ki
0
K2......, ...__.LJ..J'--~---

3-99

20/10

FAIRCHILD·· TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSTRUTH TABLESSYNCHRONOUS OPERATIONASYNCHRONOUS OPERATIONOUTPUTS
AFTER
CLOCK

BEFORE CLOCKOUTPUTS
ONE
ZERO
H
H
L
L

L
L
H
H

INPUTS

J
L*

H*

x
x

INPUTS

K

ONE

ZERO

x
x

l
H
Ii
L

H
L
L
H

L*
H*

OUTPUTS

So
L
L
H

Co
L
H
L

H

H

ONE

ZERO

H
H
L

H
L
H

SYNCHRONOUS
INPUTS CONTROLSYNCHRONOUS OPERATION
The truth table defines the next state of the flip-flop after a low-to-hightransition of the clock pulse. The next state is a function of the present
state and the J and K inputs as shown in the table.

The H* symbol iff the J or K input column is defined as meaning that the
input is high at some time while the clock is low.

The J and K inputs in the table refer to the basic flip-flop J and K inputs
as indicated on the logic diagrams. These internal. inputs are for every flipflop the result of a logic operation on the external J and K inputs. This
operation is represented symbolically by AND gates in the logic diagram foreach flip-flop. Logic diagrams are in accordance with MIL Standard 8068.

The H and L symbols refer to steady state high and low voltage levels,
respectively.

The X symbol indicates that the condition of that input has no effect on thenext state of the flip-flop.

UNUSED INPUTSThe L* symbol in the J and K input column is defined as meaning thatthat input does not go high at any time while the clock is low.

The 9001, 9020 and 9022 all have active level low synchronous inputs.
When not in use they must be grounded. All other unused inputs. including
asynchronous should be tied high for maximum operating. speed. Use oneof the methods recommended on Page 3.
ELECTRICAL CHARACTERISTICS 9000, 9001, 9020 AND 9022 (TA= .0°C to 75°C, Vee= 5.0 V ±5%)
LIMITS
SYMBOLCHARACTERISTIC

0°c
MIN. MAX.

MIN.
2.4

VoH
VOL

Output High Voltage
Output Low Voltage

2.4

VIH

Input High Voltage

1.9

Input Low Voltage

VIL

0.45

25°C
TYP.

MAX.

3.0
0.21

0.45

1.8

75°C
MIN. MAX.

UNITS

2.4

Volts
Volts

0.45
1.6

0.85

Volts

0.85

0.85

5.0

60

60

10

120

120

20
14

240
160

240
160

IF

-1.60

-1.0 -1.60

-1.60

-3.20

-2.0 -3.20

-3.20

-6.40
-4.32

-4.0 .-6.40-2.7 -4.32

-6.40
-4.32

IF

-1.41

-0.94 -1.41

-1.41

-2.82

-1.88 -2.82

-2.82

-5.64
-3.78

-3.76 -5.64-2.54 -3.78

-5.64
-3.78

IPD

Input Leakage
All J, K inputs
T inputs 9000, 9001
JK inputs 9000, 9001
T inputs 9020, 9022
JK inputs 9020, 9022
S0 , C0 (all flip-flops)

input Current
All J, K inputs
T inputs 9000, 9001
JK inputs 9000, 9001
T .inputs 9020, 9022
JK inputs 9020, 9022
S0 , C0 (all flip-flops)
Input Current
All J, K inputs
T inputs 9000, 9001
JK inputs 9000, 9001
T inputs 9020, 9022
JK inputs 9020, 9022
S0 , C0 (all flip-flops)
Vee Current
9000
9001
9020,9022
each flip-flop==

Guaranteed input low thresholdfor all inputs.

µ.A

v,ee = 5.25 V, VR = 4.5 v
Gnd. on other inputs.

mAv,ec = 5.25 v

mA

Vee= 4.75V

28
33
30

'-·

3-100

28
33
30

VF= 0.45 v
5.25 V on other
inputs

Vee= 5.0V

mA
28
33
30

=

Vee= 4.75 V, 10 H -1.2 mA
Vee 4.75 V, IOL = 14.1 mA
Vee 5.25 V, IOL = 16 mA
Guaranteed input high thresholdfor all inputs.

Volts

•.

IR

CONDITIONS & COMMENTS

S0 at gnd
S0 at gnd
C01 , C02 at gnd

FAl.RCHILD TRANSISTOR-TRANSISTOR MICROLOG,C®. INTEGRATED. CIRCUITSTYPICAL INPUT AND OUTPUT CHARACTERISTICS
9000, 9001, 9020 AND 9022

OUTPUT VOLTAGE VERSUSASYNCHRONOUS INPUT VOLTAGE
4.0

I

'

I
$

~ -4.0uil
1l~?5•c~-2.0....-1

25'C
o•c

v I

~ -20 t--+--+--+---+-a~ -40t--+-~---+--+-+--+--f

...=>
...

!\'

"'-6.0
I
z

--

1.0

Ot--+--+--+--4-...+--+-"l---f

I

ii<

0:

75'C

j-60

-8.0

2.0

1.0

3.0

-10
-2.0

3.0

0

2.0

4.0

-80 .__~~_..___.___._.__.....__,
-1.0
1.0
3.0
5.0
7.0

8.0

~

VIN - INPUT VOLTAGE-VOLTS

VIN -INPUT VOLTAGE-VOLTS

Your - OUTPUT VOLTAGE - VOLTS

Fig. 3Fig, 4

Fig. 5

Fig. 6

INPUT CURRENT VERSUSINPUT VOLTAGE
JK INPUT 9000, 9001

INPUT CURRENT VERSUSINPUT VOLTAGE
JK INPUT 9020, 9022

INPUT CURRENT VERSUS INPUTVOLTAGE, ASYNCHRONOUS
INPUTS -ALL FLlr·fLOPS
2.0 ,_v.. . ,ce,. . 5.....,.o-v' ...,..--..-...-...--..--fI.-i......,,.......,OUTPUT CURRENT VERSUSOUTPUT VOLTAGE. (OUTPUT (OW),

Vee •5.ov

_,

2.0

..

Vcc•5.ov

0

E

1.

/

i-!.. -2.0

r--o·c25'C.....__75!eg§

8 -4.0~o•c~iB -4.o t--1..--t--t-+-+--+--+--+----+--l
,,fZJ

_1

L

--

.!-8.0-10o•e1--1 F:,5'C
75'C
-8.0

M

~

Fig. 70

2.0
U~V1rlNPUT VOLTAGE-VOLTS

!;;

~ 60
=>

......

Fig. 8

L

~ 40

_§20

10 ~.........__._~_..__.__._...__...._.
,2.0
0
2.0
4.0
6.0
8.0

y

0:

!

-8.0 t--1.--t--t-+-+--+--+--+----+--l

z

I

§

M

Vcc•5.0V

E~
O'C!! -6.0 r- tgs•c -+--+--+--+-+-t--1
I
1--7'•C

-10

0
2.0
U
~
V1N-INPUT VOLTAGE-VOLTS

100

.. 80

1/L 25'C -+-+----+--+--!
1- -2.0 ....._,'--'_L~~i75°C -+-+--+--+--<

7 -6.0zt--t-+· _C":O'C'"

i5

1--1 t'--25•c
7 -6.0 t--1 l:--75•c~t-±-f·OUTPUT CURRENT VERSUSOUTPUT VOLTAGE(OUTPUT HIGH)

VIN-INPUT VOLTAGE-VOLTS

0~ w2.0' 2.0

i-Vcc•5.ov..B-4.o l'.J

~g:~

v

I

1.0

E

I

~ 2.0

>5

..

1

I

~

11/WC

... 1.0

2.0"'g':::; 3.0

.."'

14g:~

"'

~
> 2.0

2.0

vc~·IoJ"

Vee. 5.0V"'g':::; 3.0

INPUT CURRENT VERSUSINPUT VOLTAGE
CP iNPUT 9020, 9022

OUTPUT VOLTAGE VERSUS
CLOCK INPUT ,VOLTAGE

4.0

.

I

0

o

_itt

~

'
-+-···--->- -

'{_

i
rL

~

v
··i---·--·,

l
0.5

1.0

Clock-to-Oum_ut
tpdf~or ~to-Output· Clock-to-Output
tpdS0 or C0 -to-Output
J, Kor JK
9000 On.!!
tset-up
Data Ent_I}'
Ior!:Data Entry
J, Kor JK
9000 Only
trelease
Data En!!!_1 or..KData Entn
Pulse
Clock
9000 Positive.
Only
WidthsN~ative .
Positive
Negative
Negative~Qr~
9000 ·()nly
Toggle Frequency

l

MIN.

35
12
17

Your-OUTPUT VOLTAGE-VOLTS

Fig. 9Fig. ~O

lYP.

MAX.

UNITS

FIGURES

12
12
20
25
22
8:0
12
18
7.0

20
20
30
35

ns

12
1.0

11

_to

16,17,18
16, 17, 18
16,17,18
16, 17, 16
16 18
16,17, 18
16, 17,18
16,18
16, 17, 18
16, 17, 18
16, 1816, 1816, 17, 16
16,17, 18
16, p,18
16, 1816,17,18

20
25.
8.0
10
25
20

50

3-101

1.5

VIN - INPUT VOLTAGE - VOLTS

SWITCHING CHARACTERISTICS (TA = 25°C, Yee= 5.0 V, CL = C1 = 15 pF of all flip-flops unless otherwise noted)
CHARACTERISTICS

J_

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz

2.0

'-'---_ _FA_l_RC_H_lt'--D_·_TR_A___N_S_IS_T_OR_-_TR_A_N_S_IS_TO_R_M_IC_R_O_L_OG_l_C_®_l_NT_E_G_R'--AT_E_D_C_l_RC_U_l_TS_ _"'----'I ·CLOCK-TO-OUTPUT DELAYS, VERSUSAMBIENT TEMPERATURE

I

ASYNCitRONOiJS IN.PUT-TO-OUTPUT
DELAYS VERSUSAMBIENT TEMPERATURE

DELAY INCREASE WITH
ADDED LOAD CAPACITANCE~r-T-,--,-.,.......,,--,--.--r--.--r-.-~i!!I 40

i

't
21

24

I

16

~

~

,.i.

N

~

MA .

1--t__i_

~·

lpd-

l

ti

J. e.o I-+-+- 111ti.-+--+- 1..-.-+--+-t--t:ri.
l

16 t--+--+--+--+--t--+--+-~..._..~_,

1}. 8.0115~

i::::+:::+.!~+=l~~::;:::::rf--rl~

o........._.__.__...........__.__...__._._.._._~

4.0

OO

0

75

50

25

:A-+J~::t=.iF-t""F-+-t--t--+--t

TA-AMBIENT TEllPERATURE-"C

TA-AllBIENT TEllPERATIJAE·•C

BO

120

160

200

240

CL - LOAO CAPACITANCE - pf
{ii ONE ANO ZERO OUTPUTS

Fig. 12Fig. 1140

Fig. 1352

Vcc•5.0V"- .Ml11. NE~~36t-·~ i\u\.Sf. 'llJ9!l!.-1111,St'.I-~

It

I!

*

~ 2B

10>--+-+---+--+-+-+-+-+--+-+---ic--t

6.0t--+-+--+--+-+-+-+-+--+-+---ic--t

20

12llAX'-'1£L

25

Tl Mi

50

-2.0 ~__.__._............__.__.__.__........_.__._.....
0
25
50
75

75

TA-AMBIENT TEMPERATURE-'c

TA-AMBIENT TEllPERATURE-"C

Fig. 14

Fig. 15
SWITCHING TEST CIRCUl1S

9000/9001
Fig. 169020/9022
Fig. 17

Vcc=5.llV
R=2.0 kO
Cr = CL = 15 pF includingprobe and jig
capacitance

Vee
R

Yee
II

9000

WAVEFORMS
Fig. 18>3.0 v

1.5 v<0.4 v>3.0 v

I

I

VJK

~

1.5 v
<0.4 v>3.0 v

1.5 v<0.4 v

tpd-

tpd+

3-102

Vcc=5.0V
R= 2.0kO
Cr =CL= 15 pf includingprobe and jig
capacitanceFAIRCHILD TRANSISTOR-TRA~SISJOR ·MICROLOGIC® INTEGRATED CIRCUltS .·.

SWITCHING TEST NOTES
tpd+ and tpd-

1. VJK should be kept at the high logic level when performing tpd tests.

1. t, 01 ;,.,. is defined as the maximum time allowed for a HIGH to be present

2. Drive the clock pulse input with a suitable pulse source. tpd+ and tpddelays are as defined in the waveforms.

at a synchronous logic input at any time during the low state of theclock and not be recognized.

2. The ,test for trelease is performed by adjusting the timing relationship be·tset-up

1. t,et-up is defined as the minimum time required for a HIGH to be present
at a synchronous logic input at any time during the low state of theclock in order for the flip-flop to respond to the data.
2. The test for t,et-up is performed by adjusting the timing relationshipbetween the Yep and VJK inputs to the t,et-up minimum value. A device
that passes the test will have the output waveform shown. The output ofa device that. does not pass the tset-up test will remain at a static logic
level (no switching will occur).
·.
·tweeii,VCP and VJK to the trelease maximum value. Tile outputs of devices
that pass will remain at static logic levels. In order to check both J andK sides of the flip.flop it is necessary to perform the test with the flip·
flop in each of its two possible states, i:e·., set and clear. This can beaccomplished by making use of the appropriate direct inputs to establish
the state before a test, The outputs of devices that do not pass thetrelease test will exhibit: pulses instead of static levels.

RECOMMENDED INPUT PULSE SOURCES

PULSEGENERATORADJUSTABLE.
.----....-___, DELAY
1------1
NETWORKr .,_ __/
FREQUENCY "' 2 MHz.__ _ __.
DUTY CYCLE ,. 50%

DTµL 9932 gates with adjustable capacitors
connected from extender Inputs lo ground makesuitable delay elements.

ADJUSTABLE
DELAY
NETWORK

9000 SCHEMATIC DIAGRAM
For resistor values see, page 169001 SCHEMATIC DIAGRAM
For resistor values see, page 16

Vee

R~

Vee= Pin 14
Gnd =Pin 7

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS

9020 SCHEMATIC DIAGRAM

16
Vee

4
Vee= Pin 16
Gnd =Pin 8

NOMINAL COMPONENT VALUES (ALL FLIP-FLOPS)

Rp R4, R5, R8; R10, Rw R17, Rw Rw R23 , R24' R26, R29 = 4.0 kn
R2, R3, R6, R7 2.0 kn
Rq. R16' R28• R3 I = 6.0 kn
R1p R18 =1.5kn
R12' R19 = 150 n
R13 , R20 = 80 n
Ris• Rw R2s• R21• R30 = 1.25 kn
R32 = 1.0 kn
Cp C2 = 10 pF

=

3-104

FAIRCHILD. TRANSISTOR-TRANSl.STOR .MICROLOGIC® INTEGRATED CIRCUITS
9022 SCHEMATIC DIAGRAM
For resistor values, sea tabla on page 16

16

Vee

Vee= Pin 14
Gnd =Pin 7

APPLICATIONSSYNCHRONOUS BCD COUNTER

Ql

Q2

DIVIDE BY TEN COUNTER

Q4

Two TTµL 9020 Dual Flip-Flops require no additional gating
elements to produce divide by ten circuit with a square wave
divide by tan output and a divide by five output.

Two TTµL 9020 Dual Flip-Flops require no additional gating
to produce a fully synchronous 8421 code BCD Counter.

BINARY COUNTER WITH ASYNCHRONOUS PARALLEL LOAD AND CLEAR-

PARALLEL INPUT -

---,

I

I

I
I
I

I
I
I
I

I
I

COUNT INPUT-+-+----+--+-'_J--=='--'MASTER CLEAR ------+-+----'='-----1-o2 ----+---+-04.-

PARALLEL OUTPUT -3-105

Binary counter using synchronous 2
bit stages with trickle down between
stages illustrates method of utilizing
dual JK flip-flops having common'Clocks in counter applications.

FAIRCHILD TRANSISTOR-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSPACKAGE OUTLINES
U6A
U6B

PHYSICAL DIMENSIONSSIMILAR TO
JEDEC (T0-116) Outline
Dual In-Line Package

PHYSICAL DIMENSIONS
16 Lead Dual In-Line

~~~gj

~.OJI

,-_+-009

~J6~~

1001
MIN.

I

:r=

.110

.090

_i__

--,.110.090

I .2so I

r-- .240-1

Non,

1. Board-drilling dimensions should equal yourpractice for a conventional .020 linch diameter lead.

U31

U3L

CERPAK 14 LEAD

CERPAK 16 LEAD

11 _[
114

1 e

16

t

_j__

.050 .26 0
0
.2r

-.-_L
7 8
.02~
[f 1
.015 f-.370-j
f----.370--j
.250
.0060
.250
.0035)-tr--.260--I
.240

~l

.409

.020

.015

8

9

I

.065

1 L.350-1

.050

.0050

.200

TOP VIEW

TYP

.050

1_~~=1

F===_L

I

.0~4

1

I
283
1----.247------1

ORDER INFORMATION
To order Transistor-Transistor Micrologic elements specify
U31XXXX59X for 14-pin Flat package
U6AXXXX59X for 14-pin Dual In-Line package
U3LXXXX59X for 16-pin Flat package
U6BXXXX59X for 16-pin Dual In-Line package
Where XXXX is the four-digit number denoting the specific element desired and 59X is for 0°C to +75°C temperature.
3-106

t=

.200

.0035

025

~rll

I=

l_

TYP

FAIRCHILD TRANSISTOR~TRANSISTO.R MICROLOGIC® INTEGRATED CIRCUITSAC CHARACTERISTICS
t.,d TEST CIRCUITS
9005 OR 9008 EXTENDABLE GATE

9005 NON-EXTENDABLE GATE
Fig. 7

Fig. 81•1.0 MHz1•1.0 MHz

AMP•4.0V

AMP•4.0V

WIDTH•200 ns
1, =11s1ons

WIDTH•200ns
t, • 11s1ons

Note: Capacitance includes probe and jig capacitance

Note: Capacitance in.eludes probe and jig capacitanceFig. 99006 EXTENDER
Vee
SWITCHING WAVEFORM
2.0 k.11

VIN---....

,..---'x------~V
I
I · ·

i
--t i'pd/------~v'pd+--_____·, _.,. .I

PULSE
INPUT

Your

·

-·- -

NOltS:

With switch in position (1) measure tpd
of 9005. With switch in position (2) meas·
ure tpd (9005)
Atpd (9006). Capaci·tances include probe an.d jig capacitances.

+

Note: Capacitance includes probe and jig capacitanca

AC CHARACTERISTICS CTA = 25°C)
LIMITS
SYMBOL

MIN.

MAX.

UNITS

k

3.0
3.0
3.0

12
14
15

ns
ns
ns

~'!>cl+

-rz-

~-

TIT
-2.0

4_.(l_

At;,d----ztr

4:u-

~tod±

CONDITIONS & COMMENTS=

Symbols are defined in the test circuit.

WORST CASE TURN OFF DELAY
OF EXTENDABLE GATE VERSUSAMBIENT TEMPERATURE .

WORST CASE TURN ON DELAY
OF EXTENDABLE GATE VERSUSAMBIENT TEMPERATURE ·41,...-.,.;..;;;;+.;.;;;;.;..;.-i-"...,;-.;..,.;.;.;_;;.;~......,=

Yee ·5.0 V, CL 15 pf
9005 Nonextendable gate only, See Fig. 7
Yee - 5.0 V, CL - 15 pf, CN --' 5.0 pf
9005 Extendable gate and 9008, See Fig. 8
9UU6 orily
The 9006 is tested by measuring its
propagation time through the 9005.
The tpd readings s~all not exceed
the 9005 readings by the specified
amount. See Fig. 9.

WORST CASE TURN OFF DELAY
OF NONEXTENDABLE GATE
48 VERSUS AMBIENT. TEMPERATURE~t--+-+--+--+--+--+--+--t--t

WORST CASE TURN ON DELAY
OF NONEXTENDABLE GATE
48VERSUS AMBIENT TEMPERATURE~.

~r:i&~-i~T\.
lI~32t--+--~~----+---+--+--+-+--tiii
rs:~· AT Ct. JsopFt-

401--f---'.r--+--+--+-+-+--t-~~ N l--.l--.j_;_.j___j_.:::i::::t::::i=;:;,;,::,,,J

±

~16~N
·J
l
~X.4Tct_~- a t--+--+--+--+--+-+-.+I--+---1~N. A~ cL!l5pFt-

iitl~lCL•\5,f ~>---1--1-t::t:

ob=::!::=::t::::::r::::.-L..L..L;.;.L-L__J
-55

25

12!;

o...._............__,_~l~,__..__.,__.........~.
-SS

25

TA -AMBIENT TElllPERATUl!E - •c

TA~ AlliieNT .TE111'£RATURE- ·c··

Fig. 10

Fig.U

·.~··

25

· r,- AMmfNT . TElllPERA~ -•cFig; 123-107

125
TA-AMBIENT TEMPEATIJRE,.-•C

Fig. 13

FAIRCHILD RETRIGGERABLE MONOSTABLE MULTIVIBRATQRi9601
FUNCTIONAL DESCRIPTION
The 9601 monostable multiv.ibrator has four inputs,. two of which are active level high and two active level low. This allows a choice of leading edge
or trailing edge triggering.
.
. The inputs are D.C. coupled making triggering independent of input transition times.
.
.,

Each time the input conditions for triggering are met, the external capacitor is discharged in a short time and a new cycle is begun. Successive. inputs
with a period shorter than the delay time retrigger the 9601 and result ·in a continuous true output. Retriggering may be inhibited by tying the negation(Q) outp!Jt back to an active level high input.
•
Active pullups are provided for good drive capiibility into capacitive loads.

OPERATION RULES
1. An external resistor Rx anci an external capacitor Cx are required as shown in the logic diagram. The values of Rx may vary from 5.0 kn to 50 kn
for 0 to +75°C operafio?, and 5.0 kn to 25 kn for -55 to +125°C operation. Cx may vary from 0 to any value necessary and obtainable.
2. If a fixed value of Rx is used, the following values are recommended: Rx= 30 kn for 0 to +75°C operation; Rx= 10 kn for -55 to +125°C
operation.
·
3. The output pulse width T is defined as follows:
0.7. .
T = 0.32 RxCx [l + -·- ] (For Cx greater than 10' pf)
Rx
Where Rx is in kn
Cx is in pf
Tis inns
For Cx 10' pf, see Fig, 14

<

.ri ·

4. If electrolytic type capacitors are. to be used, the following two arrangements are recommended:

.

+

-

RH R

R < 0.6 Rx (Max).·.~

01: any silicon·

type diode, such

x

·

uro~

~~ ·

01

PIN 11 PIN 13·This circuit also amplifies Cx allowing
for longer output pulse width.
·

R < Rx (0.7) (h1eQ1)Rx (min) < Rx

< Rx (max)

Q1: Any NPN silicon device with
sufficient hFE at low currents,
such as 2N2511

Both circuits prevent reverse voltage across Cx. The pulse width T for the circuits is defined as follows:o.7 ] Where: R i~ in kn
R
Cx is in pF
Tis inns· T = 0.36 RCx [l +5. To· obtain variable pulse width, by remote trimming, the 'following circuit is recommended:

PIN13

PIN l1.

~-------b·
J.. ~AS

cr1"

CLOSE AS POSSIBLE
JO DEVICE.

. . R<Rx (MAXJ-Rx

0--:-.-------Ycc

6. Under anY operating condition, .Cx and Rx (min) must be kept as close to the circuit as possible to minimize stray capacitance and reduce noise
pickup.
7. Input Trigger Pulse Rules.

Input to Pin 1 (2)Pins 2, (1), 3 & 4 = 1=

Input to Pin 3 (4)Pin 4 (3) .;., 1. Pins 1 or 2 = 0

>
>

t1, 4
Setup time
40 ns
h, b = Release time
40 ns

8. The retrigger pulse width is calculated as shown below:
tw = tpw + tpd+ = 0.32 RxCx (1 +:..__tw~

_J

!

L

.7
NOTE: Retriggering will not occur if the retrigger pulse comes within .32 RxCx (Rx) ns after the initial trigger pulse •• 3-108°ft: ) + tpd+

The retrigger pulse width is equal to the pulse width tpw plus
a delay time. For pulse widths greater than 500 ns, tw can beapproximated as tpw.

FAIRCHILD RETRIGGERABLE MONOSTABLE MULTIVIBRATOR 9601
TABLE 1ELECTRICAL CHARACTERISTICS (TA= -55°C to 125°C Yee= 5 V ±10%).

SYMBOLCHARACTERISTIC-55°C
MIN. MAX.

LIMITS+25°C
MIN. TYP. MAX.

+125°C
MIN. MA)(.

UNITS

CONDITIONS(Note 1)

YoH

Output High Voltage

2.4

2.4

2.4

Volts

VOL
VIH
VJ.I.
IF

Output Low Voltage
TnpufHignVOlfage
Input Low Voltage
Input Load Current

Yee,,;,, 4.5 V, loH = -0.72 ll!A
(Note 2)
Yee_= 4.5 V, IOL = 10 mA (Note 2)
Yee = 4.5-V (Note 3)
Yee= 5.5V
Yee= 5-:S-V!&.

Input Leakage Current
Short Circuit Current
Quiescent Power Supply Drain--rfegative Trigger Input
to True Output

--rr

0.4

3.3
0.2

0.4

CJ
t>.85
-1.6

0.4

1.4
0.90
-1.1 -1.6

0.85
-1.6

15

60

60
25

2s-

-40
25
40

Volts
-VoltsVolts
mA~=0.4V

!sc_

!P<l
Tpd+

-10
25

µA
mA
mA
ns

tpd-

NegativeTrigger Input
to Complement Output

25

40

ns

tpw(min)

Minimum True Output
Pulse Width·'
Pu1se Width Variation
MaximumAIJ:owa6fe
Wiring Cap. (Pin 13)
Timing Resistor

45

65

ns

3.42

3.76
-00

A~w

CsTRAYRx--so5.0

25

3.08

25

5.0

oO
5.0

. 25

µsec

Pt

Yee = 5.5 v, ~ = 4.5 V
Yer.=_!Q_V, Your = 0 V (Note 2)
Yee= 5.5V
Yee= 5.ov
Rx= 5.0kn
Cx = 0, ~ = 15 pf
Yee= 5.0V
Rx= 5.0kn
Cx.,:= 0, ~ = 15 pf
Yee== 5.0V
Rx= 5.0kn .
St= 0, ~ = 15 p~ .
Vee_= 5.0V,, ~ -10 kn, Cx -1000 pf
Pin 13 to Grouriifkn

TABLE 11ELECTRICAL CHARACTERISTICS (TA= 0°C to 75°C, Yee= 5 V ±5%)SYMBOLCHARACTERISTIC

0°C
MIN. MAX.

LIMITS+25°C
MIN. TYP. MAX.

+75°C
MIN. MAX.

UNITS

YoH

Output High Voltage

2.4

2.4

2.4

Volts

VOL
VIH
VIL
TF

Output Low Voltage
lnput-W1gl1Voltage
Input Low Voltage
lnpufLI>acrc-urrent

IR.!.s.c.

lnputTeuage Current
Short Circuit Current
Quiescentl'ower SupplylJrain

tpd+

Negative Trigger Input
to True Output

25

40

ns

tpd-

--rfegat1ve TriggerTnput
to Complement Output

~

-.m-

ns

tpw(min)

Minimum True Output
Pulse Width

45

65

ns

A~w

... PUTse WldffiVariation
Maximum Allowable
Wiring Cap._(Pin 13)
Timing Resistor

3.42

3.76
50

lpd

CsTRAY
Rx

0.45

3.4
0.2

0.85

0.85
-1.6

-Tir -T.6
15
-10

25

3.08
50
50

0.45
1.6

.85

-Tir

5.0

0.45

1.8

1.9

5.0

(1) Unless otherwise noted, 10 kO resistor placild between Pin 13 and Vee, for all tests. (Rx)(2) Ground Pin 11 for VoL Pin 6 or VoH Pin 8 or lse Pin 8.
·Open Pin 11 for VoL Pin 8 or YOH Pin 6 or lsc Pin 6.
(3) Pulse Test to determine V1H and V1L (Min PW 40 ns).

3-109

rilA

60
-40

60

µA
mA

~

~5

riiA

50

NOTES:

Volts
Volts
Volts

5.0

50

µsec
pf

50

kn

CONDITIONS(Note 1)
Yee = 4.75 V, loH = -0.96 mA
J_Note 2)
Ye~= 4.75 V, !oL = 12.8 mA (Note 2)
Yee =4.75V(Note 3)
Ye_e = 5.25V
Yee= 5.25V
VE= 0.45V~e = 5.25 V, VR = 4.5 V
Yee= 5.0 V, Your=_Q_'.'_ (Note 2)
Yee= 5.25V
Ground Pins 1 and 2
Yee= 5.0V
Rx= 5.0k!!
Cx = 0, CL = 15 pf
Yee= 5.0V
Rx= 5.0 kn
St= 0, Cj, = 15 pf
Yee= 5.0V
Rx= 5.0kn
Cx_ = 0, ~ = 15 pf
Yee -'5.0V, Rx -10 kn,.:5._-lOO!fPF
Pm 13 to GroundFA~RCHJLD RETRIGGERABLE MONdSTABLE MULTIVIBRATOR 9601
TYPICAL ELECTRICAL CHARACTERISTICS

IN~UT LoAD CURRENTVERSUS INPUT VOLTAGEOUTPUT CURRENT VERSUSOUTPUT VOLTAGE (LOW STATE)INPUT lEAiAGE CURltENT
VERSUS INPUf VOLTAGE
ao.--~-,__,.-,..-~-...--,.---.

ao~~T-1~.-..-~~-.--..---.

Vcc·S.OV._J.___._~__._..___.___.

-3.5 .__.......

-1,5

I- 68fp~:·.?,~.-t--+-t---t--t---t

o

-o.5

2.S

b.5

INPUT VOUAGE - VOUS

OUTPUT VOl.TAGE • VOlTS

Fig. 3 .

Fig. 4

oliTPur. CliRMNT VERSUS

PowER DISSIPAfl01'4 VERSUSAMIHEt4T TEMPERATURE.

~

OUTPUT VOLTAGE (HIGH STATE) ·..

NEGATIVE TRIGGER DELAY TIME
VER$US AMBIENT TEMPERATURE

IS

80 vcc • 5.o v
S, • ISpF

Vcc·5.0V
OUTPUT "HIGH"~'

l~l---+--1--4-+---+--+--+--I

e

i5

~
~ 90 t--+--t--+..-vcc-·.,,.5"".ov:;t--+--+--tc;i-~2-.0-----2-.0-.-'--4.~0-,~~70 >---+--+---+Vc(}4.S V'+---+-'-+---!--1~5-~-~-~0_IS__.__7_5__.~~­!•OUTPUT VOl.TAGf·.· VOLTS

TA -AMBIENT TEMPERATURE - 'C

Fig. 6

fig. 7

Ag.

NOR.MALIZED O~~t
PULSE WIDTH 'IEQUS'AMBIENT TEMPERATIIRENORMALIZED OUTPUr
PULSE WIDTH · ·QUS SU,,LY VOLTAGE

JfO-MALIZED· OUTPUT
PULSE WIDTH VERSUSOPERATING DUTY CYCLE

. '

1.6

1.4
vcc ·5.ov
Rx• IOkll
Cx • lolpF

TA· AMBIENT TEMPERATORE • 'Ca

1.4

Vcc·5.0V
Rx· IOkll
Cx •lolpF
TA•IS'CTA •IS'C
Rx ·.IOkll
Cx • lolpF

%

~ 1.2

~
~

t--

$. 1.0

':""1

i--

0

~

~

~ 0.8

0.6
·5

-IS

0

11S

75

0.6

!IS

4.0

4.5

TA· AMBIENT TEMPERATURE' 'C

5.0

55

80

6.0

. OPERATING DUTY cvc1£·-·

SUPPlV VOLTAGE r VOllS

Fig. 11

Fig. 9
t:

:

'

' ' •

OUTflUT PULSE WIDTH VERSUSAMBIENT TEMPERATURE

PULSE WIDTH VERSlJSTIMING RESISTANCE
I
20"cc. 5.ov

Vcc·5.0V
Rx •5.0kll
Cx • D

Cx: • JolpF,__-+--+---1-+--t--<v!9. 16 t---+--+--+-+---+--+--.L-+v-7'1

;

x
.Lf

~NTARV o~P'!!-cotAl'li ;:..--<.

!!:! 12 t---+--+-+-+---+17"+--+---+--1~~!~OUTPUT

8 8;0 t---t--t-->"fkd-+---+--+--+--1

y

4.D

10

L

30.,

20
4l
Rx· EXTERNAL TtMINJl RESISTOR - kll.

10
-75

so

Fig. 12.

-ISIS
5TA • AMBIENT T£Mt>ERATURE • 'C

Fig. 13
3-110

llS

100

I

FAIRCHILD R'ETRIGGERABLE MONOSTABLE MULTIVIB.RAT0~960i.

OUTPUT PULSE WIDTH VERSUS· .TIMING RESISTANCE AND CAPACITANCE·For Cx< 10 pf (For Cx ~ 10 pF;\w ==: '0.32 RxCx (1 + ~.7)
3

· . ..

3

Rx.

104

--------------z--1.l
.L

~

Ill

c:
I

:::c
.Ic
3::

'""

~
::::::>

-··'

c...

I-

::::::>

c...

I-::::::>

0

10 --------~----~--~------~--~-----!
10
~
~.
.
.,

;

Cx - TIMI NG CAPACITANCE - pF

Fig. 14
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS+uv

LOADING RULES

Yee

TTµL INPUT LOAD AND DRIVE FACTORS-55°C to +125°C
INPUT .LEVEL
'High
Low
OUTPUT STATE
High
Low

~~~

3.0Vj_f..

.
~
1.-tpw•-I'
YouT ·.1. 5 V- . vOUT~
tpd--1. 'NOTE: Capacitance includes

LOAD FACTOR
1
1
DRIVE.~CTOR

12
6

INPUT LEVELHigh
Low
OUTPUT STATE
High
Low

LOAD FACTOR
1
1
DRIVE FACTOR
16
8CCSL INPUT LOAD AND DRIVE FACTORS~

t,d+-l 1::

0°Cto 75°C

-55°C to +125°C
INPUT LEVELHigh
Low
OUTPUT STATE
High
Low

Jig and Pro~a

3-111

LOAD FACTOR
1210DRIVE FACTOR
144
. 62

INPUT LEVEL
·High
Low
OUTPUT STATE
High
Low

LOAD FACTOR
1210.5
DRIVE FACTOR
192
85 .

. ·. FAIRCHILD REfRIGGERABLE MONOSTABLE MU;LTIVIBRATOR 9601
APPLICATIONS

lllPUT

1 OUT
0 OUT

n.I1Jl.J1.JUl..

J PULSE WIDTH T LJ

l~~~~--1-1~~~-FREQUENCY DIVISION
This ·Configuration ·makes the 9601 non-retriggerable and capable of frequency division.

OUT
Ill

DELAYED PULSE GENERATION
The first 9601 determines the time T1 before the initiation of the output pulse.
The second 9601 determines T2, the output pulse width.

lllPUT

FREQUENCY

MALFUNCTION INDICATOR
The output of the retrlggerable single shot will only remain high if the input
frequency is above some fixed value. The input.may be a flip flop which normallyhas a fixed frequency of operation. A system malfunction is indicated when theflip flop frequency drops and retrig&ering operation of single shot ceasts. 'DISCRIMINATOR
The 9601 can be used to produce a voltage output proportional to input frequency.
For a fixed TC of Rx and Cx, the duty cycle of the outpu.t will vary with frequency.
This is integrated by Rz C2 producing a voltage proportional to frequency.

1311..............__ , 9801 1i-----.

A OUT

RSS

r--t.___r-i____

BOUT~

.•

ASTABLE MULTIVIBRATl>R
Frequency of operation is dependent upon value of Rx aml Cx.

3-112

DIODE-TR.ANSISTOR MlCROLOGlC®
INTEGRATED . Cl RCU ITSA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTMILITARY TEMPERATURE RANGE: -55°C tO +125°C
GENERAL DESCRIPTION
The 9932 buffer has active pull·up to provide increased capacitive drive andhigher fan-out. The 9944 has a bare collector output to allow for wired-ORor driving of low-power lamps, Fan-In for the buffers can be extended withthe use of the 9933.
·

The Fairchild 9930 series of Diode Transistor Micrologic is _a member of
the Compatible Current Sinking Logic (CCSL) family designed for use insystems where good noise immunity, medium speed, medium power, andgood fan-out are required. OTµL is available in CERPAK and hermeticallysealed Dual In-Line packages over the full military temperature range.
Basic members of the family are active low level output AND gates com·monly called NANO gates.

The binary products are direct coupled master-slave flip-flops making
operation independent of the clock pulse rise and fall times. The binary
products Incorporate direct clear, direct set, and buffered output$ to provide
output isolation from the slave circuitry.

Noise immunity is typically 1 volt. Worst case noise immunity over the
military temperature range is 400 mV. Power dissipation is typically 8.5 mW
per .gate function at a 50% duty cycle. The average propagation delay is
30 ns per gate function. A single 5 volt ± 10% supply is used.

The Yee and ground terminals of all devices are located on diagonal comersof the packllge which allow two degrees of freedom Jn routing of powerand ground lines on the P/C boards. Simple loading rules are incorporated
so that the fan-in and fan-out capability of each device can be quickly
established.
·

A variety of gate combinations is available which provides the system designer the utmost in logic flexibility and helps to reduce package requirements to a minimum. Gate outputs may be tied together to perform thewired-OR function. Some gates are provided with 2K pull-up resistors which
offer improved propagation delay times. An extender is provided to increase
the fan-in for some of the gates.

The DTµL 9930 series is compatible with the CCSL devices which Include
LPDTµL, TTµL, MµL, Medium Scale Integration (MSI), and Micromatrlx™
array products.

TABLE OF CONTENTS
ABSOLUTE MAXIMUM RATINGS, LOGIC DIAGRAMS ................................2 • 3
Explanation of loading rules

NANO GATES AND HEX INVERTER ..............................................................3 • &9930, 9961 dual four input extendable gates
9946, 9949 quad two input gates
9962, 9963 triple three input gates
9936, 9937 hex inverters
NANO BUFFERS ....................................•.......................................................&• 99932 active pull-up buffer
9944 uncommitted output buffer

mENDABLE HEX INVERTER ......................................................................9 • 10
9935
EXTENDER ELEMENT ........................................................................................11
9933
BINARY ELEMENTS ...............................,.............•....................................12 • 23
9111, 9945, 9948 R·S flip-flop
9093, 9094, 9097, 9099 Dual J~K flip.flops
9950 A·C coupled R·S flip-flop
9941, 9951 Monostable Multivibrators
ORDER AND PACKAGE INFORMATION ••...........................•..............:.............%4F=AIRCHIL.C
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011, TWX: 910·379·6435

3-113

SE M IC::::ONDUC::::TOR
A DIYISl9M OF FAIRCHILD CAMERA ANO INSTRUMENT CORPORATIONFAIRCHILD DIODE-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
9300 SERIES DTµL INTEGRATED CIRCUITSNAND GATESHEX INVERTERS

1
3
5

2
4
6

9
11
13

8 .

10
12

9962, 9963

9936, 9937

9930, 9961

EXTENDABLE HEX INVERTEREXTENDER.

~:i~~:>--t-4

2

1
3

4

6

5
9
11

6
9

8

~~ -=:;=J=L.J---11

10
12

13

13

9935

9933

10
2

3

s So 1

2
12
11

T

4

C Co 0

1

3
4
9

6

8

SS

0

9
10
11

5

9950

9945, 9948

9941, 9951

4

2
3

4

6

5
13
9
10

8

4

3
1
2

5

8
.5

10

10
11
13
12

11
12

3
1
2

6

8

11

8

9

12

9

13

1
Vee= 149111

9093, 9094

GND=7

ABSOLUTE MAXIMUM RATINGS (Above which useful life may be impaired)-65°C to 150°C-55°C to 125°C-0.5 vto +s.o v
12V-1.5 Vto 5.5 V+Vee
1.0 mA
30mA
100 mA
300°C

Storage Temperature
Temperature (Ambient) under bias
Vcc pin potential to groundVcc• pulsed 1 second
Input voltage, applied to input
Voltage applied to output when output is highInput current, into inputs
Current into output when output is low (except 9932 & 9944)
Current into output when output is low (9932 & 9944)
Lead temperature (soldering, 60 seconds)
3-114

9097, 9099

I

FAIRCHILD DIODE-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSLOADING RULES
In this data sheet the following notation· has been chosen to indicate the input loading and output drive for all logic elements.
INPUTSOUTPUTS

A/B

Where
A= high logic level input load factor
B= low logic level input load factor
X high logic level output drive factor
Y= low logic level output drive factor

X/Y=

LOGE ELEMENT---·

When checking for loading violations it is only necessary to insure that the sum of the high logic level input load factors at any node does not exceed
the high logic level output drive factor at that node. The same is true for low logic level load and drive factors. These rules apply only within the OTµL
9930 series.· For loading. rules to other Fairchild logic elements refer to the CCSL Composite Data Sheet.
Multiplying the factor with the appropriate current per unit load gives the input loading or output drive in terms of current. For the DTµL circuits of thisdata sheet, current per unit load is -1.5 mA maximum at low logic level and is 5 µA maximum at high logic level.
In the case where unused inputs of an AND gate are shorted to a driven input, the high logic level input load factor for inputs will be the number of
inputs shorted together ti111es the high logic level input load factor for one input. The low logic level input load factor for the inputs will be the sameas that for a single input. 'FANOUT REDUCTION RULES FOR WIRED-OR APPLICATIONSEach DTµL output has a pull-up resistor connected to the output (except 9932 and 9944
and 9950). In wired-OR applications, any gate must be able to sink the current from all
pull-up resistors in addition to the loads connected to the common wired "AND" point.
A 6K pull-up resistor represents 0.82 unit loads (U.L.) and a 2K pull-up resistor represents
2.3 U.L. To calculate the load driving capability of a wired-OR configuration simply findthe total U.L. contribution of excess pull-up resistors. The FAN-OUT of the wired AND isthen the fan-out of the lowest rated fan-out gate in the wired-OR combination minus theexcess pull-up resistor contribution.

: =Q10--~~ z = (AB) (CD) ... (XV") or,e--o--Lr--"T

Z

F---

= AB + CD + ... + XY

E--r"'"'L

NANO GATES-9930, 9946, 9949, 9961, 9962, 9963
HEX INVERTERS-9936, 9937
DESCRIPTION
The 9930, 9946 and 9962 are active low NANO gates. The 9936 is a hex inverter with input and output characteristics identical to the NANO gates.
The variety of gate combinations provides the system designer the utmost in logic: flexibility and reduces package count.
The 9961, 9949, 9937 and 9963 are versions of the 9930, 9946, 9936 and 9962 with 2K collector pullup resistors in place of 6K pullup resistors. These
gates have increased speeds and greater high level drive factors over their 6K counterparts.

Fig. 1-LOGIC SYMBOL AND PIN CONFIGURATIONS
1--+-~~.a---t---23-+-._,,

12--r--r)o--1-11J _,13 -+---4.....,

Fig. 2-BASIC GATE CIRCUIT

Vee

INPUT

OUTPUTI

0--*--f

Vee= 14GND=79946, 9949

3-----

9

4
5
9
10
11

1~ -H!l.---l~
8
]
.I"'

9936, 9937:::;:~~C>o-1~-a
5

1
2
13
3

3
]
.I'
21--t-f'""'\c--1-]~::t=Dc4- 64~~~~~C)o-1~-8

13
11-----

9962, 9963

9930, 9961

Fig. 3-LOADING FACTORS

Fig. 4-LOADING FACTORS(9930, 9936, 9946, 9962)(9937, 9949, 9961, 9963)==

1/1--o-r-""'I~36/10* ____ _.' E

1/l==0~108/9'•-----"EI

Q._ ______ JE
R1 =2.0 kO
R2 = 1.75 kO
Rl = 5.0 kO
R• = 6.0 kO (9930, 9936,
9946, 9962)
R• = 2.0 kO (9937, 9949,
9961, 9963)•Extender pin on 9930, 9963 allows increased number of
inputs by addition of discrete diodes or extender element
DTµL9933.

• Number of inputs depends on the gate.

t 9930 and 9961 only.

3-115

•:·FAIRCl:llLD .DtODE-TRANSISTOR MICROLOGIC® INTEGRATED CIRC(JITSTABLE I
ELECTRICAL CHARACTERISTICS OF 6K GATES......... 9930. 9936, 9946 AND 9962 (TA = .,....ss•c to +125°C; Vee
';,

..

=v

± 10%)+125°C
MIN.
MAX.

UNITS

CONDITIONS AND COMMENTS

2.5

Volts

Yee= 4.5 V, foH = -0.18 mA..·
Inputs at V1L (See Below)
Vee= 4.5 V, loi. = 12 mA
Vee= 5.5 V, foL 15 rnA
Inputs at Vll:l (See Below)
Guaranteed Input High T~reshold
ForAll l~s
Guaranteed Input Low Threshold .
For All Inputs
Vee= 5.5 v VF= o:4 v
Vee= 4,5_! J 4. 0 Von other inpu~
Yee =5.5V, VR = 4.0V • ;Ground on other i'!l!!lts
Inputs Open
JVcc= 5.0V
Inputs Groundedl
Vee - 5.0 V, See Page 6, Fig. 7

'

.·.

5.0

SYMBOL.

CHARACTERISTIC

-ss•c
MIN.
MAX.

YoH

Output High Voltage

2.5

Vol

Output Low Voltage.

MIN.

+25°C
TYP.

2.6

3.5

0.4

MAX.

0.25

0.4

Volts

0.4

...
VJH

Input High Voltage

VIL

Input Low Volt11ge

1.4

IF

In put Load Current-'-1.5--1:16

2.1. •Triput Leakag1f~urrent

IR

1.7

1.9

...

Yee Cu.rreh.t "Gate On'
lpo(per gate) ~ Curr~nt "Gate Off"
Turn un Delay
tpd+· · Tum On Delay
tpd-

1.1
-1.2
-0.93

-1.5

-qs

0.8

Volts

-1.4

mA
rnA
µA

-:s:o

3.25
·1:47

2.41
. 1.15
45
20

10

Volts

-1.08

-zo

;

25

mA
mA
ns
ns

-so·
30

Yott

Output High Voltage

VOL·Output Low Voltage.VIH

lr\.l>Ut High Voltage ..

-55°C
MIN.
MAX.

MIN.

+25°C
TYP.

2.5

2.6

3.5

. ·2.s. !.0.27. . Q;4.

OA

• f~

'

., '

2.1

:

1.9 ..

...::.

.,~VIL. Input Low Voltage

1.4

IF

. I np~t Load Current

I .

-1.5
-1.16

· Input Leakage_ Current

lpo(per gate) .

Vcc Current ''Gate On"·vcc· ·Current "Gate
Off".
..Turn Off Delay
Turn On Delay"l.7: .:, ':.. ·l.h:,·
--1.2
-0.93

:~

'-:'.'.. ·,~

-LS

0.8

2.0
'

1.1.5
10
10

J

5.45
1.47

4.05

~sn

35
.20

-c::-

Vee= 4.5 V, loH = -0.54 mA
Inputs at ~L (See Below)
Volts Yee= 4.5V, loL = 10.8_mA
Vee= 5.5 'I/, foL = 13.5 mA
lnp11ts atVlli(See Below).
Volts Guara11tee4 .lnpµffflilf,Threshold
For AIUnputs ·.· .. , ..
Volts Qu~ranteed Input Low Th.reshold
For. All Inputs
mA
Vee= 5.5V
VF= 0.4 v .
mA · Vee= 4.5 V 4J) Von other inputsµA
Y(;(;=<5:5V, VR:::4.0V
Ground on other inputs
mA
Inputs Open
Vee= 5.0 V
mA IInputs Grounded}. .
ns
Yee - 5.0 V, See page 6, Fig. 7
ns

J

-1.4
-1.08
5.0

.:...us

CONDITIONS

Volts·o.4 ·..,..

'...'.·"

tpd+
tpd-

J

UNITS

+12s•c
MIN.
MAX.

MAX.

. ~:

R

=

LIMITS

CHARACTERISTIC

'

-

.
.
9937, 9949, 9961 AND 9963 (TA= -55°C to +125°C, Vee= 5.0 v ±10%),.

_- , ,..

..

TABLE II· . ..
ELECTRICAL CHARACTERISTICS OF 2K $ATES SYMBOL,LIMITS

30·

ELECTRICAL CHARACTERISTICS.
. .
Fig. 5a
WORST CASE POWERDISSIPATION VERSUSAMBIENT TEMPERATURE

Fig. 5b
WORST CASE LOGIC,LEVELS
V.ERSUS,.·AMBIENT TEMPERATURE

Fig. 5c
WORST CASE HIGH LEVELNOISE IMMUNl:JY VERSUSAMBIENT TEMPERATURE .
I .

1.6

Fig. 5d
WORST CASE LOW LEVELNOISE IMMUNITY VERSUSAMBIENT TEMPERATURE
1.6 ,.---,.--,.--,.--,.--..--..--,---..----.

u1vsv~cS5~5V~--~

l.O l--+-+-+-+-+--t--t--1--1~ ~ ·12!! • -18QIA,.Vcc • 4.5v ·~ 0=r~1+·-··+-+-+-+--+-___,-l
1.2

io.s 11~ r-~·~· ·~·~ 0.4 l"-L,d-+--+--+--+--+--+--+--+--lF.0• 1016kl

T1~~

25

TA - AMBIENT TEMPERATURE - °C

125o._...._..__.___._......._'-'--~L-'-'--'--'-55
IA· fiMBIENl lIMPERAIURE • °C

O'--,__,__,__.__.__,__.__.___.
55: OL-'--'--'--..._..._..._..._..__.
-55

TA -AMBl-ENT TEM~RATURE.· \IC25
TA - AMBIENT TEMPERATURE - °C

125

. FAIRCHILb · DlODE-TRANSiSTOR ·. MICROLOGIC® INTEGRATED CIRCUITS
Fig. 5e.

WORST CASE TURN ON DElAY
VE"SUS AMB,l~T TEMPERATURE(6k Gates)
60

J60(&k Gates)~1--4

tMl\ P1

MlllJ

t--1t-.

::MJ.!l0

l!l 80 t---+--+--+---1-+---+--h~v

i!ifi 60 t--+--+--+--+~~~ «J t--+---+---+.

0...J!..20t--+--t-'-+---l-+---+,1-+,-i' ~~~~........~~~~~·80·«I ,____,__.___..__._..__-L--L..--1

J25

20

60

«J

80

JOO

II

J

'A· AMBIENT ltMP£RATURE • •e

. Fit; SI
WORST CASE t'URN ON DElAY
VERSUS AMBIENT TEMPERATURE(2k Gates)

f'ig. Sif'ig. 5k

Fig; 51·

WORST CASE TURl\I OFF DElAY
VERSUS AMBIENT TEMPERATURE

INCREASE OF PROPAGATIONDELAY VERSUS CAPACITANCE

DECREASE OF TURN ON DElAY
VERSUS FANOUT.
(2k Gates)

Ycc·S.OV~........!'---.

120

See Fig. 7

~JI»

..
;

lMBl!.Y~I 20 t--+--+-+-+--+--t--t--+-i

80 t---+--+---+---+-+---+--+---trs::~ «J t---+--+---+--+:s 20 1--+-+-~~SEE FIG. 1"" ~ .........

~

~

4~

!!il ·L_J.,:::::;t;:;:J.~::E:::t::::t:~N0~ •20 MIN.Atpi1+ F.O. •JO

25

25

125

TA • AMBIENT 1EMP£RATURE • •e

J25

60

80

-so

JOO

J

CAPACITANCE • pf

TA • AMBIENT 1EMP£RATURE • °C

FAN OUT !UNIT IOADSIINPUT AND OUTPUT CHARACTERISTICS.

Fig.'&cfir~ &blYPICAL OUTPUT VOLTAGE
VERSUS INPUT VOLTAGE(&k & 2k Cates)
l.S

5.0

12SoC-jVee• s.ov

J.0

7S"t-hi

i o.s

O"~e~
-ss•e

'\,. ~\

25°C-1

12S:f

~ 0

,

!!! 4.0

g

~-1.0

·2.0
·2.S

·3.0

tr:c

~

~ ~ .....,.
~

IO"'Cj 1--125•e
t-ktl

A

Inputs~~·~z-ss•e V1-=:1.s~80 Vee• s.ov.;;;_ ~
Po "! ~ "75 e~251c- IO"e-s5•i;a-o.s'

1YPICAL OUTPUT CURRENTVERSUS OUTPUT VOLTAGE(&k & 2k Gates)

V c·S.OV

J";

3.0

6.0

0
0.4

9.0

0.8

J.2

2.0

1.6

0

2.4

0.4

. Fig:. &cl
TYPICAL OUTPUT CURRENTVERSUS OUTPUT VOLTAGE(2k Gates).

Fig. 68..

TYPICAL OUTPUT CURRENt
VERSUS OUTPUT VOLTAG&:(&k Gates)

''

3.0

0.8

us•cr;
7S"ct::
25•c

i

J.O

~

0

a

O"c4=1,,~ ·J.O

·jr.;Ill""'8
ll-3.0

-5.0

;,J_

~

~ '55°c

~

j

12S"C

r-

"

0

Vee• 5t0V

1"'"1gnd
2.0

17" ~

f5

. . 'i'.C

l.u.s[115'cl--+-,~...<:..i----l-+--+--1--1

8·1.0 ,___,...,,..._--+---+-+---+--+---<•'P""'"" ~ 75•c
~
zs•c

-2.0

~

4.0

-5S"c

us•c

-1.s t---t-9-+--+--t-+---+--+--tt---+9-+--+---1--1--Vcc • s.ov _-2.0 ._____.__,___._,__·....
'"-"""_'.r._nd__,.
-2.0
2.0
4.0
6.0.

6.0

VOUT • OUTl'liT VOLTAGE· VOLTS

V0ur ·OUTPUT VOl.TAGE ·VOLTS

3-117

1.2

J.6

Your. OUTPUT VOLTAGE. VOLTS

VIN· INPUT VOLTAGE· VOLTS

YIN· INPUT llOl.TAGl • VOLIS.

Vcc•S.OY

''\l

~ 60

;

,

........
~r-...

SEE FIG. 7-1---1--+---l-+--+--I

!

.5
:!!
l!i «J t--+--+-+-+--+--+--+--+--l~N

FAN OUT .'UNIT ,LOADS!

(2k Gates)

Yee •s.ov

e 60t--+-+-+-+--+-+-~l.Ll"-+---1«J ,.,._.+--+-+-+--+--+--+--+-I"b..

CAPACITANCE· pf(2k Gates)

501--t--+-+-+--+--+--+--+-ii!i lO. (_..j..:::+,#-;::::;:=:;::;;::t::i

TA· AMBIENT 1EMP£RATURE. ·e

80~

20 t--+--r....,....-+-:-:~

;

+-

0
-SS.

J25

25

·55

'

5ee Fig. 7 t--+--+--t--+---1--i

'100

~

~

Yee ·.5.ov

~

:s

10

.

.120 .----...-~--.-.......-..--..........-.---.

vce • s.ov
Seefig.7

5
t--

.'

Fig. Sh

DECREASE ,OF .tuRN OOFF DElAY.
VERSUS FANOUT(&kGates) .

D~lAY VERsUS CAPACITANCE

50

."I

.

1fl\IOREASE OF·. PROPAGATION

WORST cASE TURN OFF DElAY
VERSUS AMBIENT TEMPERATURE. (&k Gates)

Vtc • S.OV
See Fig. 7 -.

Fig. 5a;' ,, . i. Fig. Sf..::..

..,._

FAIRCHILD DIQDE-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS.
; ''fig. 7,;;..!,tp<I TEST Cl~CUIT AND W~V~FQRMS.
.
Vcc=5.ov

PULSE INPUT

JL

f = 1.0 MHz
PPw = 110 ·ns ± 10 ns

GND

Ampl. ·= ~.o V ±0.3 v
Offset = ± Q.5 v
Rise.Time= 10 ns
Fall Time 10 .ns

=

tpM

RI

c,
Cz

3.9 k!J
30 pF
20 Pf

tpd-

Diodes are FD600.
C1 and C2 include all jig andprobe capacitance

400!]
50 pF
20 pF

vml

vm2

Temp.

(Volts)(Volts)

-55°C
25°C
125°C

1.7

1.5

1.5
1.2

.q
1.0

BUFFER ELE~ENTS--9932 AND 9944
The OTµL 9932 an~ DTµL 9944 are (lual "N~ND" power gates capable of ·driving and sinking large currents for high fan-out applications. The DTµL
~932 features an emitter-follower output pull-up, which provides a ~igh fan-out ~evice with superior capacitanc~·driving capability. 'The PTµL 9944
!s fntended as a high fan-out gat~ interface driver, or low power lamp driver.

Fig. 1-LOGIC DIA~RA!\t1 AND. · ' PIN CONFIGURATIQN. ·9932, 9944 .

Fig. 2-SCHENIATIC DIAGRAM OF THE
DTµL 9932' ELEMENT . '" . (C,?N!! GATE);

Fig. 3-SCH~MATIC DIAGRAM QF THE.
DTµL.99,W ELEMENT .
. ..'(ONE ~ATE)'":,;

Vee = 14
GND= 7

Vee= 14
GND=7

Fig. 4-LOADING FACTORS;(9~3~)

fig. 5-:-LOADING FACTORS,, .
· (9944)111. I~<>--·· 121

*

.E

3-118

Vee = 14
GNQ =7NOTES:
1. Extender pin (•) allows increased number pf inputs !>Y ad·~ition of discret, diodes or extender element DTµL9933.
2. (..) denotes the need for an external resistor to provide
high level 'drive taP,Bbility. The use of an externil resistor
will then detract from the low level drive fictor as follows;
subtraci one (1) fan-out for· every 3.4 kO path from Vee~-~.
.
3. 993.2 iiutputs cannot be wired-OR.

.

. FAl'RC-HIU) DIODE-TRANSISTOR . MICROLOGIC® INTEGRATED CIRCUITS ;
-··

·. .

TABLE I
ELECTRICAL CHARACTERISTICS9932 (TA= -55°C to +125.°C, Vee= 5.0 V ±10%)..

SYMBOLVoH

CHARACTERISTIC...
Output High Voltage""'-55°C
MIN.
MAX.

MIN.

LIMITS
+25°C
TYP.

2.5

2.6

2.8

., .

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage+125°C
MIN.. MAX.

0.27

0.4

0.4

1.9
1.4./

""\.'

UNiTS
Vcc=.4.5V
Inputs a.t V1L(See Below). Volts

Vee= 4.5 V, Im= 36 mA
Vee= 5.5 V, loL = 37.5 mA . ·Inputs at V1H (See Below)
Guaranteed Input High Threshold
For All In puts
Guaranteed Input Low Threshold
For All Inputs

Volts

1.7
1.1

0.8

Volts

-i.5
-1.16
2.0

-1.4
-1.08
5.0

mA
mA
µA

/

-·

IF

Input Load Current-- ..--•----~~- -1.5

-1.2
-0.93

-1.16
IR

Input Leakage Current.lpo(per gate)

Vee Current "Gate On"
Vcc Current "Gate Off"
Turn Off Delay
Turn on Delay

tpd+
tpd-

25
15

:L

-"13.310
1.15. 50 ..

mA
mA
ns
ns

'.•

10 1-i = -2.0 mA at -55°C-2:5 mA at 25°C •·= -4.0 mA at 125°C=

Vee= 5.5 v, '.VF= 0.4 v
Vee= 4.5 v. VF= 0.4 v
VR = 4.0V
Other inputs grounded
Vee= 5.0 V, Inputs Open
Vee= 5.0 V, Inputs Grounded
Vee = 5,0 V, See Page 8, Fig. 7

.I•

1.47
80
40 .

25

CONDITIONS

Volts
_::,,

0.4

2.1

...

2.5

..

. .,, '•• ,.

VOL

MAX.

TABLE II
ELECTRICAL CHARACTERISTICS - 9944 (TA= -55°C to +125°C, Vee = 5.0 V ± 10%)SYMBOLCHARACTERISTIC

-55°C
MIN.
MAX.

MIN.

:tl25°C
MIN .
MAX.

UNITS

MAX.

0.27

0.4

0.4

Volts

CONDITIONS
Vee= 4.5 V, l~L = .36mA
Vee= 5.5 V, 10 L = 37.5 mA
Inputs at V!li (see below)
Guaranteed input hig~· thresholdfor all inputs
Guaranteed input low thresho.ld
for all inputs·

VoL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

1.4

1.1

0.8

Volts

lcEX

Output Leak~ge

50

100

200

µA

VcEx = 4.5 V
Inputs at V1L (see above)IF

Input Load Current

IR

Input Leakage Current-1.3. -1.0
0.02

-1.5
-1.16
2.0

-1.4
-1.08
5.0

mA
mA
µA

lpo·
(per gate)

Vee Current "Gate On"
Vcc Current "Gate Off"
Turn Off Delay
Turn .On Delay

7.6
1.15
35
20

10
1.47.
50
35

Vee = 5.5 V, VF= 0.4 V
Vee = 4.5 V, VF= 0.4 V
YR= 4.0V
Other inputs grounded
Vee= 5.0 V, Inputs Operi
Vee= 5.0 V, lriputs Grounded
Vee= 5.0 V; See Page 8, Fig. 8

tpd+
tpd-

0.4

LIMITS+25°C. TYP.

2.1

1.9

-1.5

....:.us

15
10

Volts

1.7

'.

3-119

mA
mA
ns
ns

....:.

FAIRCHILD DIODE-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
9932 AND 9944 ELECTRICAL CHARACTERISTICS
Fig. 6a
WORST CASE POWERDISSIPATION VERSUSAMBIENT TEMPERATURE

Fig. 6c
WORST CASE 'HIGH LEVELNOISE IMMUNITY VERSUSAMBIENT TEMPERATURE(9932 ONLY)

Fig. 6b
WORST CASE LOGIC LEVELSVERSUSAMBIENT TEMPERATURE

so.--.....-..,-...,.........--,...-.,...-.-......,.--,

1.6 ~--.-~~--.-.--.~
4.5V ~ Vi:e ~ ·s.5v

1.699321MX GATEL-+--+--+--+--tj.....-i~ 80 f--+-+--+--+---+--+--+t--!--++-"""I

!91.2

~

z

g

- 9!_32 TYP IGATE ONI

I~ v.e.•'-•)l~-:;-~11.0M\~ 40_

r- -- -- -

f

l!

g
0~~~~VJ~L~-1~~-B~~1-•nd~1-'p~r-E7~..................

125

25

·55

-55

125

25

Fig. 6f
TYPICAL OUTPUT VOLTAGE
VERSUS INPUT VOLTAGE(9932 ONLY)

Fig. 6g
TYPICAL OUTPUT CURRENTVERSUS OUTPUT VOLTAGE(9932 ONLY)

Fig. 6h
TYPICAL OUTPUT CURRENTVERSUS OUTPUT VOLTAGE

5.5
5.0

is·2=1'ooc:=J

:wR

125°C

0

~
g
l.O

75•e...,
251e

l1J !"-O"e
55•e

~

~I""

·SS°e

r~·e

O"~

~15•e

·l.O

O.__...___._.....__.__.__._...........__.__,.

0125

Fig. 6e
TYPICAL INPUT CURRENTVERSUS INPUT VOLTAGE

~

·2.5

25

TA • AMBIENT TEMPERATURE • •e'~:g~

-2.0 hVee. 4.sv.TA -AMBIENT TEMPERATURE. ·e

u--0.5-=--1.5l---1

TA • AMBIENT TEMPERATURE • •e

1 0.5

z

rT~

TA· AMBIENT TEMPERATURE -°e

1.0

~-1.0

.,5

125

1.5

iii

--+~

25

v

1---1

o.51=;:=;:=+:;;::t:;;:+.;::;;+=;:l==;::!;;;:;;:l9932 and 9944 MM_ IGATE OFFl-to~~~~~~~~ 0.4 /

20 t--+--+--+--+--+--+--+--+---t

.,5

y

v
lo.a
~

-olillf"I2ii

Fig. 6d
WORST CASE LOW LEVELNOISE IMMUNITY VERSUSAMBIENT TEMPERATURE~

Vee• 5.0Y
F.O. ·10 -I

~'

~

'-'

0

l.O

6.0

9.0

u

0

l-10

J-20

~ ~::s ~ ::sVee•5.0Vu

VIN· INPUT VOLTAGE· VOLTS

u

~J

~10

L'-' l.l-1

s2.0

P.t·e

./

t-+--+-+-t--:J;,,..""""',_--l

1120

2.0

u

·1,0

.........~-~~~~
1.0. 2.0 l.O 4.0 5.0 6.0 7.0

0

~

~

-40~~~

Vou1. OUTPUT VOLTAGE. VOLTS

~

80

40

0

,, i': e

A ~

~

.Y
g
tM~~"-1"'-+-+--t--+--l j

VIN· INPUT VOLTAGE· VOLTS~~ k;"r17'

160·JO I""uve~ · ~.ov 1

Inputs at v 1_H

1 20 f--+--+--+--+-+---+--+--'1
Ii 1

jj !(, ~ I~ I~

~1.0

200

Vee ·5.ov

JO 1-1npu1s atv 1L·--+--t-+--+--+--<

rt_
0

~

/J le

0.4

0.8

1.2

1.6

2.0

2.4

Your· OUTPUT VOLTAGE - VOLTS

SWITCHING CHARACTERISTICS
Fig. 7-tpd TEST CIRCUIT FOR DTµL 9932 ELEMENT

Fig. 8-tpd TEST CIRCUIT FOR DTµL 9944 ELEMENT

Vee
Vee=5.ov

PULSE INPUT(SEE PAGE 6)

PULSE INPUT!SEE PAGE 6)__r-,_

:e?+
510n
2 kn
20 pf
20 pf

R,
R2

c,
C2

R,

c,
C2

510n
500 pf
20 pf.J"L:e?150n
2 kn
100 pf
20 pf'

Fig. 9-WAVEFORMS FOR 9932 AND 9944

150n
500 pf
20 pf

All Diodes are FD600 or Equivalent
C1 and. C2 include Probe and Jig Capacitance

Temp.

VM
(Volts)-55°C
25°C· 125°C

1.7
1.5
1.2

t:-Your---GND

3-120

I

FAIRCHILD DIODE-TRANSISTOR Ml~ROLOGIC® INTEGRATED CIRCUITS
Fig.10a
WORST CASE TURN ON DELAY
VERSUS· AMBIENT TEMPERATURE
IO
0:

Fig. 10c
INCREASE OF TURN OFF DELAY
VERSUS CAPACITANCE

Fig. lOb
WORST CASE TURN OFF DELAY
VERSUS AMBIENT TEMPERATURE~~~+-+-+--+--+--+--+--fO'--'--'--~~~'""'--'--'--'.,,TA • AMBIENI TEMPERATURE • •c

25

l2S

200

«JO

600

800

1000

CAPACITANCE· pf

TA· AMBIENI lEMPERATURE • 'C

EXTENDABLE HEX INVERTER -9935

A 9935 inverter is intended for use with discrete diode expansion of the input. Input load and drive factors can be calculated with the aid of thecurves on Page 11 and the forward/reverse characteristics of the diode used.
A single 9935 inverter can be driven directly by the outputs of other DTµL elements, with the exception of 9932 and 9950.• providing no more than
5 mA is allowed to flow into the input of the 9935. Commoning 9935 inputs is not a recommended configuration.
When extending inputs with diodes, care should be taken to minimize capacitance on the input node as turn on delay will be increased by 2 ns perpicofarad of stray capacitance at this node.
Fig. 2-SCHEMATIC DIAGRAM(ONE INVERTER ONLY)

Fig. 1-LOGIC DIAGRAM AND PIN CONFIGURATION
1
3

5
9
11
13

2

.---~-e-~---l\l'lf'y--~--...---oVcc

4
6
8

R2

10
12

Vee= 14
GND=7

Fig. 3-LOADING FACTORS
R1 =2.00kQ
R2= 1.75 kO
Ri =5.00 kO
ft4=6.00kO

x -;>o-- 36/10
X - input to be used with 9933 ordiscrete diode.

'--------o GND.

TABLE I
ELECTRICAL CHARACTERISTICS- 9935 (TA= -55°C to +125°C, Vee= 5.0 V ±10%)
-55°C
MIN.
MAX.

MAX.

+125°C
MAX.
MIN.

UNITS

SYMBOLCHARACTERISTIC

YoH

Output High Voltage

2.5

3.5

2.6

2.5

Volts

Vol

Output Low Voltage

0.4

0.25

0.4

0.4

Volts

VIH'

Input High Voltage

VIL

Input Low Voltage

1.4

IF

Input Load Current

-1.5
-1.2

lpo
(per gate)
tptl+
tpd_

Yee Current "Gate On"
Yee Current "Gate Off"
Turn Off Delay
TumlrnlJelay

2.3

MIN.

LIMITS
+25°C
TYP.

2.0

25
10

1.8

-1.2
-0.93
2.41
1.33
65.
30

Volts

1.1

0.8

Volts

-1.5
-1.2
3.1
1.7

-1.5

mA
mA
mA
mA
ns
ns

80
40
3-121

~1.2

CONDITIONS
Yee= 4.5 V, 10 H = -0.18 mA
Inputs at V1L
Yee= 4.5 V, 10 L = 12 mA
Yee= 5.5 V, loL = 15 mA
Inputs at V1H
Guaranteed input high thresholdwith FD600 diode
Guaranteed input low thresholdwith FD600 diodel

Yee= 5.5 V, VF= 0.4 V FD~O DiodeYee = 4.5 V, VF= 0.4 V on mput
Yee= 5.0 V, Inputs open
Vee= 5.0 V, Inputs gnd.
Vee= 5.0 V, See Page 10, Fig. 5

FAIRCHILD DIODE-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
9935 ELECTRICAL CHARACTERISTICS
Fig. 4a
WORST CASE POWER DISSIPATIONVERSUS AMBIENT TEMPERATURE(EACH INVERTER) ---2• ..--..--....-...--...--.....--.-~-..-~
t--+--+-+--+--<--+-Je

Fig. 4d
WORST CASE HIGH LEVELNOISE IMMUNITY VERSUSAMBIENT TEMPERATURE

Fig. 4c
HIGH INPUT THRESHOLDVOLTAGE VERSUS FORWARD
EXTENDER DIODE VOLTAGE

Fig. 4b
WORST CASE LOGIC LEVELSVERSUS AMBIENT TEMPERATURE
4.0 ..--..--....-....--.---.---....-..--.---.

·Iov...,

i

6.01::..- ---:±.- llJ.!.~- -Vee·4.H

FD 600 on nput

O'--'--"---'-+--'-....__.____.___.
-»
IS
125
TA • AMBl£NJ TEMP£RAIUR£ • 'eO'--"---'-+--'--'---'---'--'-~

-»

125

25

Fig. 41LOW INPUT THRESHOLDVOLTAGE VERSUSFORWARD DIODE VOLTAGE

2.0 ..................,......,.--.--,---,--,--.-...,.-...,

u ....--.---..,.-...,.....-,--,..,._,.,,5v,,...~,_,.v,....~'""'~...,.5.'="5v,..,

TA· AMBIENT T£MPERATUR£ - °C

Fig. 4g
WORST CASE TURN OFF DELAY
VERSUS AMBIENT TEMPERATURE

Fig. 4h
WORST CASE TURN ON DELAY
VERSUS AMBIENT TEMPERATURE

160 Vee. 5.ov

J'.l

FD 600on Input

1.0

0.5
VFD • FORWARD DIODE VDLJAG( I IQJA • VOLTS

TA - AMBIENT TEMPERATURE - °C

Fig. 4e
WORST CASE LOW LEVELNOISE IMMUNITY VERSUSAMBIENT TEMPERATURE

l $ F.O. $ 10
D'--"--+-_._......__,____.___,_____..'--'
-»
IS
~

~

., Vee• 5.0\1

l.9klll--+--+--+--+--+--+--I
cR11 ••20pf
see Fig. 5.

l20 1--+-+--+--+--+---+--+-+---t

E . 60olXJll l--+--+--+--+-+--1--1
cR11 •• 50pf
see Fig. 5.

L..-1o~~~~~~~~~~

-»

IS

125

D.__.__..__..._..._..._...__..__._~

0 0~~0.-2~~0.4~-o~••~-o~.s~-1.o-»

VFD ·FORWARD DIODE VOllAGE 01.5 mA ·VOLTS

TA - AMBIENT TEMPERATURE - °C

25o~~~~~~~~~~

~

·55

IS

TA - AMBIENT TEMPERATURE • °C

llS

TA - AMBIENT TEMPERATURE· - °C

Fig. 5-SWITCHING TIME TEST CIRCUIT

vcc=s.ov
9935!UNUSED INPUTS ARE. DPENJ"

.' --

R,

91

PULSE INPUTISEE PAGE &I

c,
C2
C3

,-,
-I "-

3.9 k
30 pf
20 pf
5 pf

400!2
50 pf
20 pf
5 pf

Diodes are FD600 or equivalent
C1 and C2 include Jig andProbe Capacitance

v.,.
v•2

~ r- r:
v•1
v•1
~

Vooy

GND

GND

3-122

vml

vm2

Temp,

(Volts)(Volts)

-55°C
+25°C
+125°C

1.7
1.5
1.2

1.5
1.3
1.0

FAIRCHILD DIODE-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSDTµL EXTENDER ELEMENT~9933
The OTµL 9933 is a dual four-input extender element. OTµL 9933 elements may be used to extend fan-in capability to more than 20 without adversely .affecting the noise immunity or load driving capability of the element to which they are cohnected.
Typical input capacitance of OTµL. 9933 is 2.0 pf and output capacitance is 5.0 pF.

Fig. 1-LOGIC DIAGRAM AND
PIN CONFIGURATION

Fig. 2-SCHEMATIC DIAGRAM
13

2

2
3
6
9

10
12
13

12

3

4

5

I A

>.I

4

- i ( I - T -l>tI 'I
I
I" I

11

5

I

10

I

11

I

I

6

9

67

GND.

9933 ELECTRICAL CHARACTERISTICS
Fig.3aTYPICAL FORWARD AND
REVERSE CHARACTERISTICS(WITH 9933)
6

Fig.4aFig.4bWORST CASE PROPAGATIONDELAY VERSUS EXTENDER PINCAPACITANCE(WITH 9930, 9935, 9963)

WORST CASE PROPAGATIONDELAY VERSUS EXTENDER PINCAPACITANCE(WITH 9932)
200

160

Vec-;5.ov
TA• 25°C
See Fig. 5.

54Vee· 5.ov
TA• 25°C
See Fig. 5.

120

i '.5L'TEST POINTSl
MIN

2

8

~~~

1pc1+ R• 3.9kQ C )" 30pF

.nJOv;JJ

80

I

0
0
40

2

l'rtlT PO INT

4
6

150

.L1

~

3

Vi

4.0

2.0

0 0 .2

VR IVOLTSI

0
.4 .6

L_

100

lpd+

L.

tpd R• 390Q
e 1 ·~pF

50

lpc1. R • l50Q
Cl• 500pF

Cz1pF
R • 5lOQ c 1 •500pF·c~~c 2 ~ 20 p:

TA m 25oc

6.0

~
/ v

"..2J

JI

.8 1.0

0

60

40

0

80

25

0

50

15

100

Cx· CAPACITANCE - pf

CX ·CAPACITANCE - pF

VF IVOLTSI

Fig. 5-WAVEFORMS AND TEST CIRCUIT
Yee

c ..

~~

,.,~
vout

Diodes are FD600
Cx represents the summation of theDTµL 9933 Dual Extender Element
output capacitances (-5.0 pF per
output) and associated board, con·nector and wiring capacitances.

PULSE INPUTISEE PAGE 61;c····
GND.

Typical Curves to Show the Effects of Extender Pin Capacitanceon Noise Threshold of OTµL9930 Dual Gate
Fig. 6aFig. 6bFig. 6c

PULSED GROUND NOISETHRESHOLD AS A FUNCTION OF
EXTENDER PIN CAPACITANCEPULSED SIGNAL LINE NOISETHRESHOLD AS A FUNCTION OF
EXTENDER PIN CAPACITANCETEST CONDITIONSPULSE WIDTHPULSE WIDTH

-

3-123

ns

VCC = S.OV

Diodes are FD600
or equivalentFAIRCHI Li>· QIOl)E. ~TRANSISTOR Ml CROLOGIC® INTEGRATED Cl RCUITSR-S FLIP-FLOPS 9945; 9948 AND 9111
DUAL J-K FLIP-FLOPS 9093, 9094, 9097 AND 9099
GENERAL DESCRIPTION
The DTµL 9930 series has seven flip-flops to satisfy the storage requirements of a logic system. Four flip-flops are dual J-K designs with buffered
outputs, allowing the wired-OR configuration to be used. The other three flip-flops operate in the R-S mode and can be converted to J-K operation with· external cross-coupled connections. All flip-flops incorporate the master-slave design which offers the advantage of a D.C. threshold on the clock
input initiating the transition of the outputs, so that careful control of the clilck pulse rise and fall times is not required.
Data is accepted by the master flip-flop while the clock is high. Refer to truth table for definition of "one" and "zero" levels. Transfer from the masterflip-flop to the slave flip-flop occurs on the high to low transition of the clock. When the clock is low, the J, K, S, and C inputs are inhibited.
The asynchronous inputs provide ability to control the state of the flip-flop independent of static conditions on the clock and synchronous inputs.
Both asynchronous set and clear are provided on the 9945, 9948, 9097 and 9099. The 9093 and 9094 have only asynchronous set inputs, and the9111 has only asynchronous clear inputs.

LOGIC DIAGRAMS AND LOADING FACTORS
Fig. 1-9945

Fig. 2-9093.l/.67
4/2
1f.67

1/.67
4/2
1/.67

Vee= 14-.
&ND =.7 .'Fig. 3~948

Fig. 4-9094

1/.67
4/1.5
1/.67 2

1/.67
4/1.5
1/.67
Vee= 14
GND = 7

Fig. 6-9097

Fig. 5-9111

1/.67
1/.67
1/.67
1/.67

1/.67

108/9

108/9

•,.1/.67

108/9

Vee= 14
GND = 7

2/4

108/9

1/.67
1/.67

Fig. 7.I'cc=14&ND =79945/9948 (J·K MODE)

Fig. 8

9099

8/4
9945

9948

35/~.33

1117/8.34

35/9.33

107/8.34

36/10
36/10

1/.67

Vec=14&ND= 7

Vee= 14&ND = 7

3-124

I

FAIRCHILD DIODE-TRANSISTOR. MICROLOGIC® INTEGRATED CIRCUITS
•

'

'

•

•,

,.

'

"#,

t

t

'

'

f

:

'.

FUNCTIONAL L9~1C DIAGRAMS.
Fig. 9-9945, 99.48 AND 9111

ONE

ZERO

Vee= 14
GND=7

Fig. 10-9093, 9094, 9091 AND 9099

IK~-----~-----------------------.....------'----------'

Vee= 14C~---J 9097/9099 .

GND=7

SYNCHRONOUS OPERATION
The truth table defines the next state of the flip-flop after a high to lowtransition of the clock pulse. The output of all flip-flops operating in the
J-K mode is a function of the prevjous state of the flip-flop and the condition of the inputs prior to a high to low transition of the clock. The output
of all flip-flops operati~g in the R-S mode is a function of the S and C
inputs at the time of a ~igh to low clock tra~sition.

The L• symbol in the J, K, C, and S input cqlumns is defined as that input
qoes not go high at any time while the clock is high_
The H* sy~bol in the J, K, C, and $ input columns is defined as that the
inp4t is high at some time while the clock is high.
The X symbol indicates that the condition of that input or 9utput has noeffect on the next state of the flip-flop.

The S anl! C inputs in the table refer to the basic S and C inputs as indicated on the logic diagrams of the 9945, 9948, and 9111. These internal
inputs are the result of a logic operation on the external S and C ·inputs.
This operation is represented symbolically by "AND" gates in the logic
diagram for eac~ flip-flop. Logic diagrams are in accordance with MIL
STANDARD 806B.
TABL~ ISYNCHRONOUS OPERATION
R-5 FJ..IP-FLOP"BEFORE CLOCKOUTPUTSINPUT$OUTPUTS AFTER
CLOCK

ONE

ZERO

s

c

ONE

L
H

H
L

x

L*
L*
H*
L
H

L

x
x
x

L*
L*
L
H*
H

x
x

ZERO
H
L
H

H
L
H
L
Undetermined

The H and L symbols refer to steady state high and low voltage levels,
resp~ctively.

TABLE IISYNCHRO~OUS OPERATION

J-_!i FLIP-FLOPTABLE Ill
~SYNCHRONOUS OPER~TION·.

l

BEFORE CLOCKINPUTSOUTPUTS
ONE .ZERO
K
~
H
L*
J
,L
H
x
·H*
L
H
L*
H
L
x H*

x

x

3-125

OUTPUTS AFTER
CLOCK
ZERO
ONE
·H
L
L
H
H
L
L
H

INPUTS

sD .
L
L
H

Ii

OUTPUTS
CD
L
H
L
H

ONE
ZERO
H
H
H
L
L
H
State determinedby synchronous inputs
and clock input

FAIRCHILQ ~IODE-TRANSISTOR MICROLOG,C® l~TEGRATE.D CIRCUITSELECTRICAL CHARACTERISTIChBl"AR~ ELEMENTS (TA= -,,55°C to +125°0, Yee= 5.0 V ;t:10%)
LIMITS.,..55qc+25°C+125°C
MIN. MAX. t.11N. TYP. MAX. MIN. MAX.

SYMBOLCHARACTERISTIC

YoH

Output High Voltage(9945, 9093, 9099)(9948,9094,9097,9111)

2.5

2.5

2.5

~.5

,•

Vol

VIH

Output Low Voltage(9945;9093,9099)(994s, 9094, Qo9z, 9111>
Input Hig~ Voltage

3.3
3.3

2.5
2.5

0.4

0.25

0.4

0.4

0.4

0;25

0.4

0.4

2.1

1.9

1.7

UNITS

Volts

Yee= 4.5 V, IOH:::: -180 µA
Yee:;= 4.5 V, IOH = -540 µA

Volts

Yee= 4.5 V, 10 L = 12.0 mA
Yee= 5.5 V, IOL = 15.Q mA
Yee= 4.5 V, 10 L = 13.0 mA (@ -55°C)
Yee= 5.5 V, IOL = 13.6 mA

Volts

Guaranteed input high t~resholdfor 1111 i~puts'

VIL

Input Low Voltage

IR

Input Leakage, all J-K
S, C, S0 , C0 inputs(~xcept C0 of9P97, 9099)
Input Leakage of C0(9097. 9099)
Input Lea~ag~. CP inputs(9~5. 9948, 9093;9Q94, 91U)
(9097, 909~) ,'

IReP

..!..

IF

~'

1.1

0.8

Volts

Guaranteed input low thres~old
for all inputs

2.0

5.0

µA

Yee 5.5 V, VR .:• 4.0 V
Gnd on other inputs

4.0

10

10
20

2(\
40
mA

Vee=5.5V
VF= 0.4V
4.0 Von other inputs

Input Curren,, all
J, K, $. C inp~ts-.98-.82 -.98=.92

Input Current, S0 or C0(9093, 9094, 9111)
Input ~urrent, CP inputs(9945, 9093)(9948. 90,94)-2.2-1:8 -2.2

-1.93

<imp
(9097)(9099)
IF, 1.4

lnputCurrent, all J, K, s, C inputs
lnpul Current, ~o or C0 inputs(9093,9094,911\)'
i'c
Input ~urre,nt'. GP, inputs(9945, 9Q93)(g94~. 9q94),,(9lll)(9o97)~(9099~IFS!

Input Current, C0 , S0 inputs(9945,9948,9097,9099)

lpo

Yee C~rrent(9945)(99413)(gHp(9093)(9094}(9?97~(9099)

CONDITIONS & COMMENTS

=

/

-2.93
-2.35
-3.76
-4.68
-5.&f).,-2.40 -2.93-1.93 -2.35-3.00 -3.7~-3.~ -4.6~-4.Q4-4.81 -5.86...,-5.14

-0.76
-1.7

-0.62 ~0.7~-1.39 -1.7..:...0.12-1.5-1.85 -2.26

-2.57
-2.03
-3.76

-2.26
-1.83
-2.90
-3.66
-4.52

-2.48 -2.90•-3.00 -3.66-3.70 -4:52

-2.02
-1.59
- -2.88
-3.18
-4.04

-2.93
-2.26

-2.40 -2.93-1.85 -~-~6

-2.57
-2.20

.:...i.so -1.83
'.

•,

8.3
9.9
12.1
16.6
19.8
19.8
16.6

.t

14.0
16.2 18.0
28.0
32.-4
32.4
28.0

3-126

mA

Vee=4.5V
VF=0.4V
4.0 Von other inputs

mA

Yee= 5.5V VF:= 0.4 V
Yee= 4,5 V } 4.0 Von other inputs

mA

Yee = 5.0 V, all inputs open
Momentary ground on S0JFAIRCHILD .DIODE·T~ANSISTOR. MICROLQGIC® INTEGRATED CIRCUITS·.·INPUT AND OUTPUT CHARACTERISTICS OF BINARY ELEMENTS _Fig. 12OUTPUT CURRENT VERSUSOUTPUT VOLTAGE"(OUTPUT HIGH)

Fig. 11TYPICAL OUTPUT CURRENTVERSUS .OUTPUT VOLTAGE.
(OUTPUT LOW)

Ve~5.~

Il

TA•25'e.
Frg; 14INPUT CURRENT VERSUSINPUT VOLTAGE· CLOCK INPUT(9948, 9094)...

Fig; 13.. . " .
CLOCK INPUT CURRENT VERSUS
CLOCK INPUT VOLTAGE(9945, 9093; 9099)'

ti.r-+--+-!945 on~r-- k::::v

1 v b:::::~!L
9lll·'l097-~-2.0 ...
~......--+--+--+--.+-+--+--+--+--t

I
0

!l

0.8

1.2

. 1.6

-6.0
-2.0

2,4

. 2.0

2.0

4.0

6.0

8.0

-l.O
f-'125'e
·1.0
1.0

l.O

5.0

7.0

9.0

VouT" OUTPUT VOLTAGE - VOL~

Your· OUTPUT VOLTAGE -.VOLT5

VIN· INPUT VOLTAGE· VOLTS

VIN· INPUT VOLTAGE· VOLTS

Fig. 15INPUT CURRENT VERSUSINPUT VOLTAGE CLOCK INPUT(9lll)

Fig. 16
INPUT CURRENT VERSUSINPUT VOLTAGE CLOCK INPUT(9097)

Fig. 17
CLOCK INPUT CURRENT VERSUS
CLOCK INPUT VOLTAGE(9099)

Fig. 18.· .INPUT CURRENT VERSUSINPUT VOLTAGESYNCHRONOUS INPUTS.--..--..--..---r--r--r-.--"TJ:--n.-.

2.0

"1i

0.4

-2.0 ~ P.fs'el'-75, e--+--+--+--+--+--+--+--I

llt~~-+--t--t--t--+---+---+--~·l.O ..._...._...._..__..__...__...__..._..._....__.
-1.0
1.0
l.O
5.0
7.0
9.0

Vee. 5.0V -+--+-+-+-+125;.,'+~--=llllHlnpu}ls Openl5'ef-.:.1.o
251e ~ ~

'o•bl

'

o

-+--+--+---+---+--tt':I .·.

~.5K··4.0 -~O'_,,,e+-+-+-+-+--t--t--t--1
25'e75'et--t--t--t--t--t--t--J--1·2.0 -55'e

il~tte !'7~;e-+--+--+--+--+---t--1!t'_~'e

0

~-1.0

F

a

25'e-;IJ)..-s5•e~lJ-6.0 ll-6.0 WILL.::125::.;'e'--J--'--'--''----'---'--'
·1.0
1.0
l.O
5.0
7.0
9.0

-1.0

~ -~5'eF.·55"e
O'e

~

J.0

1.0

7.0

5.0

·l.O
-2.0

9.0

H

rt-!<-- 251

-2.0

0

O'e
:We

7~

I--- 125'e
2.0

6.0

4.0

8.0

VIN - INPUT. VOLTAGE_· VOLTS

VIN._ INPUT VOLTAGE - VOLTS

Fig. 19
INPUT CURRENT· VERSUSINPUT VOLTAGE
ASYNCHRONOUS INPUTS

Fig. 20OUTPUT VOLTAGE VERSUS
CLOCK INPUT· VOLTAGE(9945, 9093, 9099) .

Fig. 21OUTPUT VOLTAGE VERSUS
CLOCK INPUT VOLTAGE(9948, 9094, 9097). Fig. 22
OUTPUT VOLTAGE VERSUSASYNCHRONOUS
INPUT VOLTAGE

25'e

1

1.0

O'e

6.0

I
!<

125 e

~

TI

' 4.0

"~~

Jll'-55'e3.0-55'}_ ..

·55~e•.~ i.o. ~ 2.0
. !5

25°e,

l

1.0

l.O

5.0

7.0

0

9.0

VIN· INPUT VOLTAGE - VOLTS

O'e
·55'e

VJ

1.0

0

·.·. • .. ·.,

1.0

0

J.O

2.0

g
~ 4.0

125°C

~ l.O

75'e

~ 2.0

25'e

~I'

1.0

0

VrN·INPUTVOLTAGE -VOLTS

J.O

2.0

0

jffe

-55'e

It

$
>o.
1.0

~

1.0

Vee· 5.ov!S
125._3.
75'e

·>~ '

!--175'?1
125'e

0

1.0

2.0.

VIN· INPUT VOLTAGE· VOLTS

VrN ·INPUT VOLTAGE - VOLTS

SWITCHING CHARACTERISTICS (TA= 25°C, Yee= 5.0 V)
SYMBOLCHARACTERISTIC

tpd+
tpd_
tset-uptrelease

Clock to Output
Clock to Output

9094, 9097, 9lll and 9948
MIN.
TYP.
MAX.

9093, 9099 and 9945 .
MIN.
TYP.
MAX.

30
30
35

35
30
35

65
75
22
14

10

5.0

5.0

. ~ 4.0

[L

•25°C

6.0

Vee· 5.ov

O'e75'e-.!

$
~ 2.0

weJ
25'e

l'1

;

!S

125 e

l

~

6.0

Vee· 5.ov

5.0

7.5°C

·55 e ,

125·I

-l. 0
-1.0

~·

75'~ O'elJe

VIN· INPUT VOLTAGE· VOLTS

Vee· 5.ov-2.0-55'e,""1 H

VIN· INPUT VOLTAGE· VOLTS

2.0

025'e-.,-4.0~"""::'::.125::..':::.1e.l__,__,--''--'--'--L.....J
1.0
l.O
5.0
7.0
9.0

0

~

7~e'i

O'~

\25•e1~-2.0:~·1.01--t----t--t--r--ir--ir--ir--;--t i~2.o 1~

·l.O
-1.0

l5

lJe..J

251e"1i+t:"'°'55•*e-+-+---+---+---+---+

Vee· 5.ov

75'e~

'"Ti"

2.0

2.0

l~'e;-oi

Vee· 5.ov

2.0 f--f--f--f--f--f--ll--'-t=1125,de._,l-fllF'rl
I
i
tfCI

~

I
!~ 1-·:....:T-F25·~ehw~~HHL...!!!l~..-~-55"-''e'-i~...,.-55'~e5o ,__.._\_...

4.0

4.0 .--.--,...--,,...--,,...--,,...--,r--...,,125.,;..;e.....-,_,.r-,Vee • 5.0V -+--+--+--+--t=-~·...,..,
lnpl Open
75'er-

10

3-127.

75
75
22
14

10

UNITS
ns
ns
ns
ns

FIGURES28,29,30

J.O

FAIRCHILD ·010DE~TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS
Fig. 23

Fig. 25

fig. 24
WORST CASE TURN ON DELAY
VERSUS AMBIENT TEMPERATURE
200
Vee· s.ov l.

WORST CASE TURN OFF DELAY
VERSUS AMBIENT TEMPERATURE

WORST CASE INCREASE OFPROPAGATION DELAY
VERSUS CAPACITANCE

R1 •2.0kQ R2 • 3900
C1 •20pF, Cz • SOpF

~ 80

160 See Fig. 28, 29, and 30

i!!

~ 60 t---t---t---t-t----Y-~~

J....--"

1-::---' MAX lpo-l!;!l! «! t--+--+----+-+-t'~J.

«lt--t-l-t-1+--+-+-+--+--+-t.___._l...__l. . . . . . .~__.___.__.__,

0
-SS

0
-SS

l2S

2S

20

~

l--*7L1---=-lo-""""=-.-~-d--+--I

l2S

1S

90

120

160

c2 - CAPACLTANCE ·pf

TA - AMBIENT TEMPERATURE - 'C

Fig. 27

Fig. 26

WORST CASE S~ UP AND
RELEASE TIME VERSUSAMBIENT TEMPERATURE
Vee· s.ov

DECREASE OF TURN OFF
DELAY VERSUS FANOUT

1--+---+---+---+---+---<See Fig, 28 and 29

so t--+---+---+--+--+-+-....,-t--t

!!!
;::

·-35 ...._..__....__..___._~_.....___.._.___.
l2
34
s 6 1 8 9 lO

l2S

2S
TA - AMBIENT TEMPERATURE· 'C

FAN OUT IONI T LOADSISWITCHING TEST CIRCUITS, TA:: 25°C, Vee= 5.0 V
Fig. 28-9945 AND 9948

Fig. 29-9093, 9094, 9097 AND 9099

Fig. 30-9111

Yee

Vee

Yee

Fig. 31......WAVEFORMS
LOADS

RI
l!z__

c1
C2

tpd+

tpd-

.2.okn2.0 kn20 pf
30 pf

2.0 kn
390n
20 pf
50 pf

MEASURING °VOLTAGE
THRESHOLDS (Vin)

Temp

Vm

-55°c
25•c
i25°c

1.7 v
1.5 v
1.2 v

>30V---

Ym-~--\'-·- - - - - - - - - - - .ov --'L...i__~!setup OR t1e1ease

VJK

<0.4V
>3
VcpVm
<0.4V
> 3.0V

Vout <All capacitances include probe and jig capacitanceAll diodes _FD600 or equivalent

3-128

0:~

\

t.....

-~..~f------+:

tpd+·~ tpd-\. ____

FAIRCHILD. DIODE-TRANSISTOR MICROLOGIC® INTEGRATED ·CIRCUITSSWITCHING TEST NOTES
tpd+ and tpd.
.
Drive the clock pulse input with a suitable pulse source. tpd+ and tpd- delays are defined in the waveforms Fig. 31 ....
t..t.up.
.

1. t,et-up is defined as the minimum time required for a Hl,GH to be present at a synchroitous logic input at any time during the high state of theclock i.n order for the flip-flo_p to resPond to the data.
···.
2. The test for t,et-up is performed by adjusting the timing relationship between the Yep and YJK pulse to .the tsat-up minimum value •. A device thatpasses the test win have the output waveform shown in Fig. 31. The output of a device that do11s not pass the tsat-up test will remain at a
static level (no switching will occur).
·t ••1.....
1. trelease is defined as the maximum time allowed for a high to be prese.nt at a synchronous logic Input at any time during the high state of theclock and not be recognized.
2. The test for trelease is performed by adjusting the timing relationship between Yep _and ·yJK to the treleese maximum value. The outputs of devices
that pass will remain at static logic levels. In order to check both J and K sides ·of the flip-flop it is necessary to perform the test with the
flip.flop in each of its two Possible states, i.e., set and clear. This can be accomplished by making use of the appropriate direct inputs toestablish the state before a test. The outputs of devices that do not pass the treleasa test will exhibit pulses instead of ·static levels.

Fig. 32-RECOMMENDED INPUT PULSE SC)~RCES

1MHz 50%
DUTY CYCLE

DTµL9932 bufftrs with adjustablec:apacltors connected from ex·tander Inputs to ground makesuitable delay elements.

PULSE

GENERATORADJUSTABLE
DELAY
t----4>0---1
NETWORK

Fig. 33-9945 AND 9948 SCHEMATIC
DIAGRAM

Fig. 34-9111 SCHEMATIC DIAGRAM

....•

...

...

•

+------<>•

...
'"'

•••

'"'

'"'

IM

...

'11

·ij,..

...

...

...

' ..

.. ..
CJ I

...
IS,

Vcc-14...

GND-7

RESISTOR VALUES 9945, 9948 AND 9111
R1, R• = 6.0 kll (9945)
R1, Rio = 1.2 kO= 2.0 kll (9948, 9111)
Rs, R9 = 3.0 kO
R2, R3 = 2.2 kll
R11, R12, R19, R20 = 9.0 kO
Rs, R•, R1s, R21, Rn, lbs= 3.5 kll R11=10 kll
R1s, R1•.= 3.2 kll
Ri., R11, R•z. R24 = 2.5 kO

3-129

FAIRCHILD DIODE· TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSSCHEMATIC DIAGRAMS
Fig. 35-9093 AND 9094

Vee= 14
GND=7

Fig. 36-9097 AND 9099

...

....

.

ZERO

I

'

Vee= 14
GND=7••"

Resistor Values: 9093, 9094, 9097, 9099

R1, R<, lb" R25 = 6.0 kQ (9093, 9099)= 2.0 kO (9094, 9097)
Rz, R•, lb!, Rz• = 2.2 kll

I,

Rs, R•, RIB, Rz1, Rzo, Rz1, ff39, R42 = 3.5 kQ
R1, Rio, Iba, Rll = 1.2 kO
Ra, R9, R2•, R!o = 3.0 kO
R11, R12, R1~, R20, R32, Ru, R<o, R<1 = 9.0 kO

3-130

R13, 1b6 = 10 kO
R14, R11, R3s, R38 = 2.5 kO
R15, R16, R••· R37 = 3.2 kO

FAIRCHILD DIODE· TRANSISTOR MICROLOGIC® ·INTEGRATED CIRCUITSBINARY ELEMENT -9950

The DTµL 9950 is an A·C coupled R-S flip-flop.

Fig. 1-LOGIC DIAGRAM AND PIN CONFIGURATION

13

9

S Sg

4
5
6
10

Fig. 2-LOADING RULES

3
4
5
7

3

Ts

Tc
C Cg 011
Vee= 142

300/108300/10Vee= 10
GND = 6

GND = 7

1/1.1

' CAPACITIVE INPUTS

TO·lOO PACKAGE

14 PIN DIP OR FLATPACK

Outputs cannot be wired· OR

Fig. 3-SCHEMATIC DIAGRAM

Co

2

So

Vee.

Rt

. R13

13

.12

R1&

11

ZERO

Rn

-=-

Ts 5

-=4

10

s

c

TRUTH TABLE -4

PULSE INPUTSINPUTSOUTPUTS
5
6 10
3 11

DIRECT INPUTSOUTPUTSINPUTS
1 13
3 11

H

x

H

H

L
H
L

H
L
L

L
L

L
L

H

x

L

H
L

x

H

x
x

x
H
H

H

x

L

L
L
L

L
L

Tc

D14

NC NC
NC NC
H l.
H L
L H
L H
AMBIGUOUS

Vee= 14
GND=7

TABLE INOTES:
1. Abbreviations used in the body of tables:
L = low, the more negative voltage level
H = high, the more positive voltage level(in all cases, open pins have the same effectas high.)
X = immaterial, either H or L has equal effect
NC =no change, the trigger·pulse has no effect on outputs
2. H or L for pins 5 and 6 represent voltage transitions ta
the level indicated rather than the levels themselves.
3. The tables assume independent use of pulsed inputs anddirect inputs. Otherwise, direct inputs will predominate.

RESPONSE TO

H

8

0,3

R1, R9, R13, R19 = 1.0 kD
R2, R12 = 2.0 kD
RJ, Rio, R11, R11 = 3.0 kD
R4, R16 = 200 D
Rs, R1s""' 6.5 D
R6, R14 = 520 D
R1, R20 = 750 D
Ra, Ria= 100 D
C1, C2==30 pF

x

-=-

NC NC
L H
H L
H H

3-131

._.-.,;--·~·--·-·FAIRCHILD DIODE-TRANSISTOR 'MICROLOGIC® INTEGRATED CIRCUITSTABLE 1ELECTRICAL CHARACTERISTICS 9950 (TA = -55°C to +125°C, Vee = 5.0 V ± 10%)

-55°C
MIN.
MAX.

MIN.
2.6

SYMBOLCHARACTERISTIC

Vlli
VOL

Output High Voltage
Output Low Voltage

2.5

VIHS

Asynchronous
Input High Voltage
Asynchronous
Input Low Voltage
Input Leakage

2.1

VILS
IR
IF
IF
IFSI
IFSI
IPD

~d+

~d-

LIMITS
+25°C
TYP.

0.4

Volts
Volts

0.4

1.9

1.7

.95

CONDITIONS

UNITS

2.5

0.4

In put Load Current
Input Load Current
Asynchronous
Input Load Current
Asynchronous
Input Load Current
Vee Current
Turn Off Delay
Turn On Delay
Toggling Frequency+12s 0 c
MIN.
MAX.

MAX.

Volts

Vee= 4.5 V, 10 H = -1.5 mA
Vee= 4.5 V, Im= 12 mA
Vee = 5.5 V, !2.L = 15 mA
Guaranteed high thres~old
for asynchronous inputs
Guaranteed low thresholdfor asynchronous inputs
Vee= 5.5 V, VR = 4.0V Asynchronous
inputs only
~c= 5.5 V, VF= 0.4 V

.80

.605

Volts

2.0

5.0

µA

-2.22
-1.83

-2.22
-1.83

mA
mA

~..,.4.5V, ~-0.4V

-1.~

-1.64

-2.09
-1.71
-1.46

mA

Vee= 5.5 V, VF= 0.4 V

-1.20

-1.24

-1.14

mA

Vee. =.4.5 V; VF= 0.4 V

8.7
30
30

8.7

mA
ns
ns
MHz

Vee= 5.0 V, Input 4 gnd.
Vee= 5.0V
See Fig.4

8.7

6.7

20

Fig. 4-tpd TEST CIRCUIT

a.ov--Vcp

ov"'3.0V

Vour
ov

c•

: _._.·-f. ___.

~1

Vm = 1.5 v@ 25°C
= 1.2 v @ 12s•c= 1.7 v@ -ss•c• Includes probe and jig
capacitance* • All diodes FDGOO orequivalent

tpd+
tpd20 MHz toggle

R,

R2

c1

3.9 kn390n

2.0 kn2.0 kn0000

100 pf
100 pf5.0 pf. 3-132

FAIRCf-ll~D DIODE~ TRANSISTOR. MICR·Ol-OGIC® INTEGRATED CIRCUITSMONOSTABLE llJ!ULTIVIBRATORS-9941, 99~;1
The DTµL 9941 and 9951 are 111ono5ta~le ~u.ltivibrators' design'ed for use with other members of the DT/,L family. They provide complementa[Y output
pulses which are typically 100 ns wide. This pulse \"\'ldth is adjustable by the addition oh~tern11I cqmponents.
.
The n µL 9~01 is 'ii retriggera~le art~ shot having severa·I feat~fes w~ich are superior to the ~941 and 9951. it is therefore recommended for n11w
system designs in preference "to the 9941 or 9951.
·

fig. 2-LOADING FAPTOR~

Fig, I-LOGIC O!AGRAM AND
PIN CONFIGURATION

2.·~··E.
1.,,..-q· SS 1 6•

Vee= 14
GND=7

'

Q

.

2/2.3

1

·--6tt36/10

I::::::0 SS

0

rr1

9

1g

36/10

1. Outputs can be wire "AND"ed
2. E~tender pin allows increased numberof inp1tts by addition of discrete diodes
or e~tende~ el~me~t DT1'L9933.

11

Fig. 3-SCHEl\llATIC DIAGRAM
14

11

ex

------~1------

10Rx- - .J\/Vv- - .., --0 Vee-.A,/\.l\r--+----0 9---<J6E2n--------1~11

Vee= 14GND=7

R1 = 2.1 kn
R1 = 7.0 kn
Ri = 2.4 kn
R•= 4.0 kn .
Rs=2.0 ksl
Ri., Rio= 1.8 kn

R1=4.0kn
Ra;= 1.2 kQR• ;_. 3.6 kli
RH ='24kn
R12=9.0 kn

C1=20 pf
.C2=25pf
Ci=l5pF

FAIRCHILD DIODE-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSTABLE I·
ELECTRICAL CHARACTERISTICS - 9941 AND 9951 (TA ;. -55°C to +I25°C, Vee = 5.0 v ± 10 %)LIMITS
SYMBOLCHARACTERISTIC

YOH
Vol

Output High Voltage
Output Low Voltage

IPDL

Power Dissipation Current
with Inputs Grounded
Input Load Current

IF
.IR
tpd+

tpd-

PW

Input leakage Current
Tum Off Delay-ru.m On Delay
Pulse Width
994i
9951

-ss•c
MIN.
MAX.

MIN.

2.5

2.5

+25°C
tvP.

MAX.

2.5

0.4

0.4
7.2

0.4

9.0

-2:93
....:2.26-2 ..93....:2.26

5.0

5.,0
40
40
90
.70
90
70

. +125°c
MAX,
MIN.

UNITS
Volts
Volts
mA

-2.75
-2.22
10.0

mA
mA
µA
ns
ns

330
330
220
160

CONDITIONS
Vee= 4.5 V, loH ="-0,18 mA
Vee= 5.5 V, i~L 15 mA
Vee= 4.5 V, IOL::. 15 mA
Vee= 5.0 V, Inputs= Gnd.

=

=5.5 V, VF = 0.4 V= 4.5 V, VF== 0.4 V
Vee =5.5 V, VR = 4.0 V, Pin 2 = Gnd.
Vee
Vee

Pin 6
Pin I

Vee= 5.0V
See Figs. 4 & 5 on Page 23

Pin 1
Piri ~Pin 1
Pini>

RULES FOR USE OF 9951
1. With Pin 9 connected to Vee and no external capacitor (Cx), the output pulse width is approximately lOQ ns.

2. With Pin 9 connected to Vee and an external capacitor (Cx) connecttid between Pins io arid 11, the output pulse width (T) is: T = 4.5 (Cx + 20)
with Cx in pF and T in ns.
..
.
.
.
3. For improv11d pulse width control, P,in 9 is left open and a stable exter.nal tesiStor (Rx) of 9,0 kn minimum to 15 kn maximum is connected fromPin 10 to Yee· The output pulse width is giveri by the expression: T = 0.5 Rx (Cx + 20) with Rx in kn, Cx in pF and Tin ns.
.
4. The output duty cycle (pulse width/period) should not exceed 40%, It may. be increased to 50% by adding a 2.0 k!J resisto~ between Pin 11
and Vct· Higher duty cycles life, obtainable but the output puise widlh ancl performance are less predictable.
5. The maximum input fall time to trigger: 25 ns for a 1.0 volt swing; .50. ns tor a 2.0 volt swing; 100 ns for a 4.0 wit swing.
6. The minimum pulse width at output Pin 1 is approximately 100 ns. This pulse width may be decreased to 50 ns by connecting a 10 kn resistor,between Pin 5 and Vee· (not applicable to T0-100 package.)
7. For pulse widths greater than 1.0 µ5, Pin I should be used as the output and inverted if required.

3-134

FAIRCHILo·· DIODE~TRANSISToR···MICROLOGIC® .·INTEGRATED. CIRCUITSSWITCHING TIME TEST CIRCUIT AND WAVEFORMS
Fig. 4

Fig. 5

INPUT

Yee
6
P!:-···--··- ------------- 14----,

lpdt PIN 6 __,._____ ,..,___

I
I__,_PULSE WIDTH

lI
I

I
I

10

I

"::"

I

PULSE
GENERATOR

1.5Y

YouT IPIN SJ

I~--3+;~!

.

I

lpd- PIN

I

I

!

r.

I

:

I

I

~i"------------------.i:-1·-~

PULSE GENERATOR
trise = 20 ns

9941 OR 9951._.

t1a11 = 20 ns

Pulse Height= 2.0 V
Pulse Width = 200 ns
Frequency = 1.0 MHz
Capacitance includes probe and jig
All Diodes FD 100

1---

90%
!fall . 10% TO 90%

90%

l.5Y

YoUT IPtN 11---'I-+--+--10%!rise . 10% TO 90%

c, = 50 pf
R1 = 3300

9941 AND 9951 TIMING CHARACTERISTICS(Test circuit above is used with appropriate modifications where necessary)

OUTPUT PULSE WIDTH VERSUS
EXTERNAL TIMINGCAPACITANCE Cx
100
Vee • 5.0V • V9 • V14

1.2

RI • JOIHlz

c 1 • so pF

!9.

:5

iii

~

..

~

5

~ l.O

~

0

f-PIN l~w

frULS~ WIDTH

J.ll

Pl.l

~

. ~

~

O.B 4.0

s.o

NORMALIZED OUTPUT PULSEWIDTH VERSUS TEMPERATUREUSING EXTERNAL TIMINGRESISTOR Rx
l.l Vcc·s.ov T

I ] J1J

Rx• !Ok tit CONNECTED BETWEEN PIN 10 -t-R1 • 300 Q
AND Vee~I~ ::roPEN

6.0

o.~.,,,;io-.40=--=.20=--:0~20=--=40=--=;io=--=11>~100,,...,.;120,....,-!140·

Vee • SUPPLY VOLTAGE • VOLTSTEMPERA!URE • ° C

TYPICAL POWER DISSIPATIONVERSUS TEMPERATURE

SWITCHING TIMES VERSUSTEMPERATURE

Cx • EXTERNAL TIMING CAPACITANCE • pfl.l~+--+--+--+--+--+--<

c 1•50pF!§ 1.1 t--~+--+-+-+-+-+-+--+--t

111

PULSE
~ 1.0 f-\¥1DTH

0.1

v~-~-v~
R1• JOOQ:~rZ

TA • 25°C

10

NORMALIZED OUTPUT PULSEWIDTH VERSUSTEMPERATURENORMALIZED OUTPUT PULSEWIDTH VERSUS SUPPLYVOLTAGE

-

Vee

·s.sv

V9. V14. Vee
1--1--1--1--1--1--+- v7 • V4 • v5 • 0 -0.9 t--t--t--t--+-+-+-+-+-+-i

Wt--+--+--+--+-+-+-~+-~+-~+-<

6'.8;io·':-.40,,......,.20,,......,~o-20:':--40.;,--;io.,.,___~11>""'1"'00...,1"'20_,..140~;io·'--.40:':--.20:':--0,,....,20=--40=--!0:':--lll~l~00...,1~20~140

TEMPERATURE ~ °C

TEMPERATURE ~ °C

TEMPERATURE • 'C

FAIRCHILD DIODE-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSPACKAGE OUTLINES

U6A
SIMILAR TO
JEDEC (T0-116) Outline
Dual In-Line Package

i-310-1

IF 91
290

HR

,-~.009.011

L.31s_J .
I NOM: l

,-

.llO
.090

I

.2ao

1·

!":'- 240-1

llOTI,

1.1eoard-drillin1 dimensions should eqvel yourpractice-for a convention...020 linch di•mettr lead.

U31

CERPAK 14 LEAD

1

lL
14

J_

f

.050 .260
.24 0

-.
_J_
.020)
.015 f.-.370~
.0060
.250

7
JT

1

8
1

f--.370-j
.250

.065

.0035 ) = .............i:======::e~~~<~·0=50=!:if--.260__,
025
.240

-,

TYP

ORDER INFORMATION
To order diode-transistor micrologic elements specify U31XXXX51X for 14 pin Flat package; U6AXXXX51X for 14 pin Dual In-Line package where
XXXX is the four-digit number denoting the specific element desired and SIX is for -55°C to + 125°C.

3-136

HIGH. LEVEL LOGIC DIODE-TRANSISTOR MICROLOGlC®
INTEGRATED CIRCUITS COMPOSITE DATA SHEETA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCT
0°C TO 75°C TEMPERATURE RANGE

GENERAL DESCRIPTION - The Fairchild High Level Logic Diode-Transistor Micrologic® Integrated Circuit
family (HLLDTµL) consists of three high voltage, high threshold hex inverters which offer extremely good
D.C. and A.C. Noise Immunity. These circuits are useful in applications involving a high noise environment
or high voltage supply which prohibits the use of CCSLTYPICAL DUAL IN-LINE PACKAGE
similar to
JEDEC (T0-116) Outline

Interfacing from CCSL to HLLDTµL is accomplished with the 9112, shifting from HLLDTµL to CCSL is accomplished with the 9109. The 9112 can also be used to drive the µM3700 MOS Multiplexer.
T.he circuits are fabricated within a silicon monolithic substrate using standard Fairchild Planar• and Epitaxial processes.
HLLDTµL elements are available in the hermetically sealed ceramic Dual In-Line Package (DIP), designed forautomated and low cost insertion techniques.
FEATURES• High Voltage Operation ••• Yee Range 12 to 20 V.
• Utilizes inexpensive external input diodes to facilitate a high density building block approach and very
high Logic Fan-In where desired.
• High D.C. Noise Immunity ••• 6;5 V minimum• High A.C. Noise Immunity ••• 10 V at 150 ns• Interfaces with CCSL

.200~
~·

.OISM
.125 TYP.
.090'

·t=

llOTEI:
1. Lucis are intended for insertion in hole rows on.300" centers. They .,, purposel1 shipped with

ABSOLUTE MAXIMUM RATINGS (above which the reliability of the device may be impaired)
Storage Temperature-65°Cto +150°C
Operating Temperature
0°Cto +75°C
Vee Pin Potential to Gnd Pin-0.5 vto +25 v
Output Current when output is low
40mA
Input Current (9109, 9110)
lOmA
Output Voltage
25V
Input Voltage (9112)
5.5V"positive" (.375) miseli1nment to f1cllit1te insertion.
2. 8o1rd·drillln1 dimensions should equal yourpr1ctlct for 1 conventional .020 linch diameter .,ad.

LOGIC DIAGRAM

ORDERING INFORMATION
To order HLLDTµL elements specify U6AXXXX59X, where XXXX is the four-digit number denoting thespecific element desired.
t

13
VCC = Pin 14
GND=Pln7*Planar is a patented Fairchild process.

F=AI ROH IL.Cl
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011, TWX: 910-379-6435

3-137

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATION

.,_~~-----------~---·F_A_IR_C_Hf~l~D~H~L_LD_T_µ_L_l_NT_E_G_R_AT_E_D_C_l_RC_U_IT_S_·~---~~~~~-ELECTRICAL CHARACTERISTICSSYMBOLCHARACTERISTIC

DEVICE

0°C
MIN; MAX.

LIMITS+25°C
MIN. TYP. MAX.

+75°C
MIN. MAX.

UNITSCONDITIONS ANDCOMMENTS

YoH

Output High Voltage

Note2

Note2

Note 2

Volts

•cexl

Output Leakage Current

9110
9112
9109

75

1.0

75

75

µA

VOLi

Output Low Voltage

0.5

0.25. 0.5

0.5

Volts

Vee = 12 V to 20 V @ v•oH -0.1 mAIL
Yee=20V@VIL
VoH = 20V
Vee= 12V@V1H•oL = lOmA

1.0

0.5

1.0

1.0

Volts

Vee=20V
IOL ;= 20mA

7.05

7.0

6.8

Volts

Input Low Threshold
@VoH

1.05

1.0

0.8
Volts

Input High Threshold@VoL

VOLZ .

VIL.

VIH

IF

lsc
leex
IPDH

IR
I max

tpc1+

\.clVrN
Vrp

Output Low Voltage

l:llput Low. Voltage

Input High Voltage

Input Load Currant

Output Short Circuit
Current
Output Leakage Current
Input High Supply
Currant
lnput.Laakaaa'current
Ground Current

Turn Off Delay

Tum On Delay"O" Leval A.C. Noise
Immunity"l" Leval A.C, Noise
Immunity

9109
9110
9112
9109
9110
9112
9109
9110
9112
9109
9110
9112
9109
9110
9112
9110
9112
9110
.9112
9109
9110
9112
9112
9109
9110
9112
9109
9110
9112
9109
9110
9112
9110

8.6

8.5

8.4

2.1

2.0

1.9

=

@V1H

I
-1.20

-0.80 ..,...1.12-1.12 mA

Vee= 20V, VF= 0.5V

-17
-2.4

-9.0 -16.3-1.65 -2.3

-15.6 mA
-2.3

75

1.0

75

Yee = 20 v. v,N = 0 v
Your= OV
Yee= 20V, Your= 20V
V1N=OV

19

28

22

34
5.0

·--".

NOTES:(1) Tests on 91119, 9110 ire perfollllM 11\!lth. FDH6 Input diodes.
(2) MIN.-Vcc -2.0V for 111 temP.niture ·TYP-Vcc -1.SV for 25•c

3-138

~
mA

10

·,"

JI.A ..

Yee = 20 V, Input Open

15mA

Yee= 2oy. V11. = 4.0V.
Yee = Your =·25 V,
lnputs@GND

145

300

ns

See Fig.4

95

200

ns

Sea Fig.4

30
7.0

125
Volts

Sae Fig. 5

Volts

Saa Fig. 5

8.5

9110

75

FAIRCHILD·. HLLDTµL INTEGRATED. CIRCUITS
Fig. lb

Fig. laFig. le8k

l&k

1/6 HLLDTL 9110
HLL-+ HLL

1/6 HLLtm 9109
HLL,... CCSL

12k

1/6 HLLDTL 9112
CCSL-+ HLL

Fig. 2b
OUTPUT LOADS(LOW LEVEL ORI~ FACTOR)
VERSUS SUPPLY VOLTAGE

Fig. 2alO/"'-

YpL'l·DY.z<!

,.

9109: OPEN CCILLECTOR
9110 .9112: 20

LOW LEVEL LOAD FACTOR(see Fil. 31)

L

.

z

LOW LEVlL DRIVE FACTOR(Sii Fil. 2bJ~

WITH FOH9 INPUT DIODE FOR 1109.9110

~

~

L

.Ll

z

~

~-0.1
10
12

Fig. 3a
WORST CASE INPUT FORWARD
CURRENT AND INPUT LOADSVERSUS SUPPLY VOLTAGE

Fig. 3b
WORST CASE POWER DISSIPATIONVERSUS SUPPLY VOLTAGE(PER GATE)

16
18
Yee· SUPPLY VOLTAGE· VOLTS

20

Fig. 3c
WORST CASE HIGH LEVEL
D.C. NOISE IMMUNITYVERSUS TEMPERATURE
I <F.0.< 28.4

~ 10 ----~~

9110ijNLvl/;:

If5_s.o >--+-+-+---+-T
v'c• iv
IH
i6.0

~

u

i

1.0
0,6 ..,___ _ _ _ __...__,___.___.__.
12

14
16
18
Yee- SUPPlY VOLTAGE· VOLTS

l-+-+--l-~l-+~4-+---1-+--I

i t--+--+--l-~l-+-l--+-+-1--+--I

1.25 ~

4.0

2.D i-+-+--1-..+-·Ycc· ~ v

O'--..._........,_.___.___..__..__...__.

20

12

16
14
18
Yee· SUPPlY VOLTAGE· VOLTS

Fig. 3e
WORST CASE LOW THRESHOLDVOLTAGE VERSUSFORWARD DIODE VOLTAGE

Fig, 3d

WORST CASE HIGH INPUTTHRESHOLD VOLTAGE VERSUSFORWARD DIODE VOLTAGE

o..._._._....._.._.._.._,,_...._...._._._~

20

9109, 9110

0

25

~

~

TA· AMBIENTTEMPUATUA£ • '<:ia9.0.Fig. 3f
WORST CASE LOW LEVEL
D.C. NOISE IMMUNITYVERSUS AMBIENT TEMPERATURE

l-b09,191~
ZV<Ycc<zov-!ii<~d<zl.4

/;:

;s.o
IH

i

Irvl

i

J.C.

..;1.0~7.0~~

6,8 ..................._....._..._ _ _ ___.._._....

0Vf •FORWARD DIOOE VOLTAGE@1QµA • YOLT5

0.2
0.4
0.6
0.8
1.0
VF • FORWARD OIOOE Vl)t.TAGE I D.7111A ·VOLTS

3-139

~6.0

r-

~

111

is.o
0

25
~
TA· AMBIENT TEMP£RATURE • 'C

75

FAIRCHILD HLLDTµ.L· INTEGRATED CIRCUITS
Fig. 3g
TURN OFF DELAY
VERSUS AMBIENT TEMPERATURE

Fig. 3h
TURN ON DELAY
VERSUS AMBIENT TEMPERAJURE
lllO

20

J_ Vee· 11.v_ Hel• 15~
FIG. 4 H

I!!

9109, 9110

. • 200

iiJl50~50 ..........

_.__._..___._.__.__._,__,__._~

0

25

~'

iMx:

i-

.......

9i 2MAX.

~9109. 9110 ~·

z

0

~

LOW 1£VEL .. , .

HIGHl£VE~~8.0 I~> 4.0

9110 typ•

0

50

~IG.5

~

16

~ 12.

).100
50

Fig. 3i
TYPICAL A.C. NOISE IMMUNITYINPUT VOLTAGE VERSUSPULSE WIDTH

0

100

75

50

25

500

400

lllO

PUlSE WI DTH • ns.·, . ·...Fig.. 4.

.

.

SWITCHING TIME TEST CIRCUIT
AND. WAVEFORMS

PULSE
GENERATORR

C1 = 5.0 pf
C.
10 pf
CL=l5pf=

Includes all prolle
and Jig capacitance

FDH6 Input Diodes areused on 9109, 9110

TEST CONDITIONS · .
D.U.T.

DEV. 1

Vm1(V)

Vm2<V)

VL(V)

R+pd-

R+pd+

9109 .

9110
9110
932

7.~

l~

7.5
1.5

7.5
7.5

5.0
17.0
17.0

5100
2.4k
2.4k

3.6 k
24 k
24k

9110
9112

Fig. 5
A;C. NOISE IMMUNITY TEST CIRCUIT

Vee
PULSE
Unuied Inputs groundad
diodes are FDH6·
C1
5.0 pf Includes ill and·C. = 10 pf
all probe cepacltllnce.GENERATOR=t,, tf < IOns
FREQ = 1.0MHz

CL=l5pf

1--1sons-=J...~-v...1N- VoH = isv.

~150ns==J Vol= 0.5V

TEST CONDITIONS AND LIMITS
TEST

VTP

_[ t

LIMIT
MIN.

Vrp
VTN

MAX.

8.5V
7.0V

Vee

R

(Volts)

(kO)

TA
(°C)

17

24
2.4

25

17

25

VIN

(Volts)1010FAIRCHILD.. HLLDTµ.L. INTEGRATED CIRCUITSAPPLICATIONS:

CCSLFig. 6-CCSL INTERFACINGC.CSL

CCSL-HlpL.
9112

I
I

I

4---oa--.

• FDFl6 INPUT DIODES

1 HLLDn High Lnal Load Eactor
l· CCSL High Level Load Factor
1 HLLDn Low Leir81 Load fictor
7.5 CCSL Low Level Load Factors==

Fig. 7-LAMP DRIVER

20V

20 VOLT LAMP

FDH6.. L~L 9109,9110

FIG. 8-DRIVING MOS3700 MULTIPLEXER OR EQUIVALENTQ DATA INPUTs;

Output Levels : min "l" lewt =Vee ·~1.5 V: mu"ci"tev.t:i::0.2V

3-141

FAIRCHILD HLLDTµL INTEGRATED CIRCUITS
Fig. 9-SEQUENTIAL COUNTERDIODES ARE FDH6 OR EQUIVALENT

,8'1

CLOCK

,8'3

,8'2

¢1

¢3

¢2

Clock

1

0
0

0

1

0
1

1
1

0

0
0

0
I

0

0

0
0

1

1

1

1

1

1

DIVlbE BY THREE ilR THREE PHASE GENERATOR

12k

JO-.+------t---ozn
MAJORITY GATE : '/, S109

Fig. 10-JK FLIP FLOP

AD
CLOCK
SET

CP
R

ALT. DRIVE

Q

ii

Q

D

R

D

TOGGLE MODE

Q

"l"in
CP

CP

"O"in

Q

R

AD

AD

Q

Q

0:

Q

0

0

CLOCK
SHIFT MOOE
DIODES ARE FDH6 OR EQUIVALENT

J K
L H
L L

H H
H L

3-142

Qn+l
L

Qn
Qn
H

HLLDTuL 9109
HIGH VOLTAGE HEX INVERTERHIGH LEVEL LOGIC DIODE-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRIPTION

The HLLDT µL9109 is a high voltage, high threshold hex inverter designed for the conversion of

TYPICAL DUAL IN-LINE PACKAGE

high level logic to any logic level from 4V to 20V. The unit is characterized by a 6.5V(min.)(In accordance with JEDEC T0-116)

DC Noise Immunity and a 20V/100 nsec AC Noise Immunity. The input diode has been left off
the circuit so that the input can be expanded to any number of inputs which allows maximum flexibility in use.
The 9109 is available in ceramic Dual In-Line* Package.
FEATURESCCSL Compatibility
High Voltage Operation

12 to 20V

Utilizes external input diodes to facilitate high density building block approach
F.O. = 7 CCSL
D. C. Noiselmmunity of 6.5V
NOTES,
I Leads are intended for insertion in hole rows on.300" centers. They are purposely shipped with"positive" (.375) misali9nment to facilitate insertion.
2 Board-drltline dimensions should equal yourpractice for a conventional .020 !inch diameter leld.

APPLICATIONSInterfacing from HLL to CCSL levels.

ORDER PART NO. U6A910959X

Line receiver.
General purpose logic level converter

LOGIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Storage Temperature-65°C to 150°C· Operating temperature

0°C to 75°c·

vcc

25V

Output Voltage

25V

Output low current

40 mA

YCC = Pin 14
JC>----f--8
GND::: Pln 7

11

10

13

12

*Fairchild patent pending

l=A.IRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-143

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD HLLDTuL INTEGRATED CIRCUITS 9109
Vee

Bk··

12k

16k

6 Per Package

C1RCUIT DIAGRAM
ELECTRICAL CHARACTERISTICS
LIMITS

0°C

SYMBOL

MIN. MAX.

o. 2

VIL

o. 5

VOLl

UNITS

CONDITIONS AND COMMENTS

MIN. TYP. MAX. MIN, MAX.

75

IoH

75~C

25°C

o. 25

75

75

µ,A

7,0

6.8

Volts

o. 5

o. 5

Volts

VCC • 20 V, VOH = 20 V

vcc = 12v, 10L = lO mAv • Value indicated
IH

VIH

0.5

1.0

VoL2

a.a

1.0

1.0

8.5

on this table,

Vee= 20V, 10L. 20 mA
Volts

IF

-1. 24

-.81

-1.16

mA

VCC = 20 V, VF = O. 5 V

1PDH

30

19

211

mA

Vee= 20V, Inputs open

Il?DL

9. 5

lf.O

9.0

mA

VCC = 25 V, Inputs GnD
VOUT = 25V

tpd+

145

400

n.s

tpd-

85

200

ns

See switching time
test circuit

NOTE: Tests are performed with FDH6 input diode.

SY

PULSE WIDTH = lps
REPETITION RATE = SOOkHzAMPLITUDE = 12V

R

PULSE
GEN.

"::'

C1"SpF
C2=lOpF'With FDH6 Input Diode

CIRCUIT AND WAVEFORMS FOR SWITCHING TE.STS

3-144

JlSpF

HLLDT1.1L 9110
HIGH VOLTAGE HEX INVERTERHIGH LEVEL LOGIC DIODE-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSA FAIRCHILD COMPATIBLE CURRENT SINK ING LOGIC PRODUCTGENERAL DESCRIPTIONTheHLLDTµL 9110isahigh voltage, high threshold hex inverter with extremely good D. C. and
A. C. Noise Immunity. The circuit is useful in applications involving a high noise environment
or high voltage supplies which prohibit the use of DT µL.

TYPICAL DUAL IN-LINE PACKAGE
In Accordance WithJEOEC (T0-116) Outline

The 9110,contains six basic logic building blocks from which more complex functions (Flip-Flop,
Shift Registers, etc.} can easily be built.
The 9110 is available in the hermetically sealed cermic. Dual-In-Line Package (DIP), designed
for automated and low cost insertion techniques.

FEATURES• High Voltage Operation Vee Range 12 to 20V.
• Utilizes inexpensive external input diodes to facilitate a high density building block approachand a very high logic Fan-In where desired.
• High D. C. Noise Immunity 6. 5 V minimum• High A. C. Noise Immunity lOV at 150 ns.
APPLICATIONS
Industrial Control Logic, Automotive Logic, Lamp Driver, Relay Driver
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Operating Temperature
Vee
Output Voltage
Output low current

CIRCUIT DIAGRAM

l.-L11d5•re·1nt•ndedforlnsertioninbotero"$Dn.300"unters.Tt1ey11e-u5°C to 150°C
0°C to -75°C
25V
25V
40mA

purpasely ship91d witH 'pO$itive" (.350) mi51li1nm1ntto facilitate inHrlion

2.8oud-dritlin1dimensionsshouldequa1yourpruticefor•conv.ntional.020

incti.di1meteri.•d.

ORDER PART NO, U6A911059X

LOGIC DIAGRAM

vee

VCC = Pin 14
JO--+-B
GND =Pin 7
11

~~-10

13

* Fairchild patent pending

GND

F.AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-145

A DIVISION OF FAIRCHILD CAMERA AND jNSTRUMENT CORPORATIONFAIRCHILD HLLDTpL INTEGRATED CIRCUITS 9110
ELECTRICAL CHARACTERISTICS
LIMITSo•c

SYMBOLMIN.

2s 0 c
1J.[IN.

MAX.

TYP.

AND COMMENTS

VoH (min.)= CVcc - 2.ov)
V OH(typ.) = (V CC -1. 5 V)

VOH
VIL

CONDITIONS

UNITS

1s 0 cMIN. MAX.

MAX.

Vee= 12 to 2ov

Volts

IOH = -0. 1 mA @V:IL

7.0

6. 8

Volts

Vee= 12 to 2ov

VOLl

0.5

o. 25

o. 5

0.5

.Volts

Vee= 12v
IOL = 10 mA@VIH

VOL2

1. 0

o. 5

1.0

1. 0

Volts

Vee= 2ov= 20 mA@V'IH

loL

V~H

8,5

8. 6

Volts

Vee= 12 to 2ov
Vee= 2ov
VF= 0.5VIF-1. 24-0. 81

-1.16

-1.16

mA

Isc

17.0

9. {)

16.3

15. 6

mA

Vee= 2ov
vout = ov

1PDH

30

19

28

28

mA

Vee= 2ov
Inputs open.

1PDL

9. 5

6.0

9,0

9,0

mA

Vee= 25V
Inputs GND
Outputs = 25 V

tpd+

145

400

118

See switching

tpd-

100

200

ns

test. circuit.

SWITCHING TIME TEST CIRCUIT
D.U.T.
r----,I

I
PULSE
l--Klh~-'11--1
GEN.

amp.=12V
p.w.=lps
V1N {0:!-1rl0--.--i-f

11.r-:-,
1_

___,

l ~C2

C2 = lOpF

R

CL= 15pF

tpci- : R = 2.4k

10-+'-+-...--4-~~)VOUT

lpd+: R = 24k"INCLUDES JIG CAPACITANCEDIODES ARE FDH&
GND UNUSED INPUTSNOTE: TESTS ARE PERfOR~ED WITH fDH6 JNl'UT DIODE

A.C. NOISE IMMUNITY TEST CIRCUIT
LOW LEVEL AC f<IOISE IMMUNITY

Vee_j_·-----.

R
D.U.T.

D.U.T,

Y1N

PULSE
GEN.

Ir, If< lOns

lOV j:1sons-=j~------vol-T

C = 15pF(INCLUDES JIG AND-:- · PROBE CAPACITANCE)I

Freq.= lMHz

UNUSED INPUTS GROUNDEDDIODES ARE FDH&
C1

=SpF

HIGH LEVEL AC NOISE IMMUNITY

Cz = lOpF
Y1N_L_,lOVTEST CONDITIONS AND LIMITS
TEST

.
VTP
VTN

LIMIT
Vee
MIN • MAX. _!..Volts)
8.5V
17
7.0V
17

R

kO
24k
2. 4

-r

l'A

-.-c

VouT _

25
25

V_,__ _ _ _ _
VTP

ft
3-146

YoH

tl5Dns-=J

HLLDT~L 9112

HIGH VOLTAGE HEX INVERTERHIGH LEVEL LOGIC DIODE-TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITSA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRIPTION

The HLLDTµ.L9112 is a CCSLtoMghleveihex interface element, The 9112 consists of six gates

TYPICAL DUAL IN-LINE PACKAGE(In accordance with JEDEC T0-116)

suitableforconvertingfromCCSL levels up to high ioglc levels (lOV to 18V.) The 9112 is idealfor driving MOS devices such as the µ.M3700 element (6 Channel Multiplexer.)
The 9112 is available in ceramic Dual In-Line• Package.

FEATURESCCSL Compatioility.
High Voltage Operation

Vee Range 12 to 2ov

F.O, = 10 HL
Wired-OR Capabillty
Good AC Noise Immunity
NOTES:
l. L.e1d1 lrt intended for lntertion jn hole rows on.300" centers. They ere purposely shipped with"positive" (.375) mlHllgnment to f1clllt1te instrtlon.
2. Bo1rd·drlllln1 dlm1n~ion1 should eQutl yourpr1ct1ce for 1 conv1ntion11 .020 Unch diameter lttd.

APPLICATIONS·ORDER PART NO. U&A911259X

CCSL-+HL interface element
MOS driver

LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS

Storage temperature
Operating temperature-65°C to 150°C
o•c to 75°C

vcc
Output Voltage
Output low current

25V
25V

9

VCC = Pin 14
JC>--1"--8
GND =Pin 7

11p--;--:10

40 mA

13

P--t--6*Fairchild patent pending

l=AIRCHIL.C
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415} 962-5011, TWX: 910-37.9·6435

3-147

SEMICONCJWCTC>RA DIVISION OF FAIRCHILD CAMERA ANO INSTRUMENT CORPORATION .

·FAIRCHILD HLLDTpL INTEGRATED CIRCUITS 9112
Vee

12k

8k

11ik

3k
6 Par Package

CIRCUIT ;DIAGRA~ .

ELECTRICAL CHARACTERl.STICSSYMBOL

0°C
MIN. MAX.

LIMITS
25°C
MIN• . TYP. MAX.
18

VOH
(Output High)

75°C

18. 5

o. 8

1.0

VIL
1cEX

UNITS

CONDITIONS.AND COMMENTS

Volts

Vee= 2ov, ·loH = 0.1 mA
VIL = Value indicated in thistable.

MIN. MAX.

Volts
µA

75

o. 2 75

75

o. 5

o. 25 o. 5

o. 5

Volts

,,

0.8

Volts

(Output Leakage)

Vee= 20V,. VOH = 20. v
VIN= OV.

.

VOLl.(Output Low)
VIH

2.1

2.0

..

Vee= 12V, loL = lOmA
VIH =Value indicated in thistable.
· ·

VOL2

1.0

0.5

1.0

1. 0

Volts

Vee= 20V, loL = 20mA

IF
(Input Low)·-1. 20-0.8 ·;:.1. i2

-1.12

mA

Vee= 20V, VF= 0.45V

Isc(Output Shorted)-2.4-1. 65-2. 3

-2. 3

mA

Vee= 2ov, vIN. ov. VOUT = OV

1PDH
(Power Diss. )

36

22

34

34

mA

Vee= 2ov, Input open

1PDL
(Power Diss.)

9. 5

6.0

9.0

9.0

mA.

Vee= 25V, Input GND
VOUT = 25V
See switching time
test circuit'

tpd+(Turn Off)

145

400

ns

tpd(Turn On).

25

200

ns

R

tpd-: R = 2.4k
tpd+: R := 24k
VL = 17V

PULSE.WIDTH= lps
REPETITION RATE = 500kHzAMPLITUDE = 3V~=lOpF

CIRCUIT AND WAVEFORMS FOR SWITCHING TESTSLPDTJJL'904'.0, 9041 AND 9042
LOW POWER DIODE TRANSISTOR MICROLOGIC®
INTEGRATED CIRCUITS',GENERAL DESCRIPTIONTYPICAL FLAT PACKAGE

The Fairchild LPDT µL Micrologic® Integrated Circuit Family consists of a set of compatible,
integrated logic circuits specifically designed fdr low power, medium speed applications.

TOP VIEWThe circuits are fabricated with a silicon moriolithlc substrate using standard Fairchild Planar•
epitaxial processes.

C:::::S?l-_Jj~::::::::::> 14*-

Pacbging options include the Flat package and the Dual In-Line package.
Important features of the LPDTµL Micrologic® integrate<! circuits include the foliowing:

T

~~=i

• Reliable operation over the full military temperature range of _;55°c to,05,......._ _......,...,_i_+125°CI• Typical power drains of less than 1 mW per gate (50% duty cycle) forthe logic gate elements and less than 4 mW for the clocked flip-flop.
• Single power supply requirement-5 volts optimum, 4. 5 to 5. 5 volts range.
TYPICAL DUAL IN-LINE PACKAGE• Guaranteed fan-out of 10 LPDTµL unit loads or 1 standard Fairchild
DT µL unit load, over the full temperature and supply voltage range.
• Guaranteed minimum of 450 mV noise immunity 'at the temperature
extremes.

it Typical logic gate propagation delays of 60 ns and binary clock rate of
2.5 MHZ••

Emitter follower outputs providing good capacitive drive capability.

•OTll•
1 LHds1reu1t1ndlld1ormH•IM1n111holerowson lOO"e.ntt~. ThitYJrl
purpoHly sh1""d w1llt 'poSlb,,." (.350) m1salitnm1nt to fac:1hlM11111ert11)11.

2.801ril-clnll1n1d1111111s1on1shoutd.,,u.iyourprut1c1for1connnt1on11.020
1nchd11metfflHd.

*Planar is a patented Fairchild process.

ORDER INFORMATION
To order Low Power Diode Transistor Mtcrologic® integrated circuit elements specify U31XXXX51X for flat package and U6AXXXX51X
for Dual In-Line package where XXXX is 9040, 9041 or 9042.

FA.I RCH I LC
SEMICDNDUCTD~, 313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-149

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MICROLOGIC~LOW POWER DIODE TRANSISTORINTEGRATED CIRCUITS
.
.
,,

'

.

'

'•

'

LPDT~L 9040 CLOCKED FLIP-FLOPLOGIC DIAGRAll!I 'HOWING FLATOR DUAL-IN LINE P~CKAGE PINDESCRIPTIONASSIGNME~T

The LPDT µL ~040 element is a directly coupled, dual:-rank flip-flop suitable for use
in counters, shift registers andotherstorageapplications.
Either R-S or J-K mode
.
.

CP

14

•cc

operation is p0$sil;>le. Direct set and clear inputs are provided which override all

C1

13

51
Sz

other data inputs.

Cz

12

Co

11

RESISTOR
PULL-UP

10SoRESISTOR
PULL-UPQ

Q

GROUNDSYNCHRONOUS ENTRY TRUTH TABLES
R-S MODE O.. ERATIONINPUTS @tn

ASYCHRONOUS ENTRY

J-K MODE OPERATIONOUTPUTS @tn+l

TRUTH TABLE

INPUTS @tn

OUTPUTS @tn+l

OUTPUTSl!'fPUTS

s1

s2

cl

c2

Q

Q

sl

cl

Q

Q'

s .
D

c·
D

Q

Q

13

12

2

3

. 6

9

13

2

6

9

11

4

0

9

L
L

x
x

L

x

NC

H

H

. NC

NC

L

L
H

NC

L

NC
NC

L

x

NC
NC

L

H

H

L

L

H

x
x

L

L

x

NC

NC

H

L

H

L

L

H

H

L

x

L

NC

NC

H

L

L

H

L
H

L

x

H

H

L

H

Symbols

x

L

H

H

L

H

H

H

J..

x

H

L

H

H

x

L

H

L

H

H

H

a

AMBIGUOUS

TOGGLESH- Most positive logic levelL - Most negative logic level
X - Either H or L can be present
NC - No change in stateH

NOTES:
1. For J-K mode operation connect Pin 6 toPin3 and Pin 9 to Pin 12.
2. Asynchronous entries override all synchronous entries.
LOADING RULESCIRCUIT DIAGRAM*NORMALIZEDINPUTUNIT LOADS (lJ.L.)
s1 s2-cl-C2SD

0.75 U.L.

2.5 U.L.

~D

2.5 U.L.

CP
•cc

•cc

-.-

32k

OUTPUT..
FAN-OUT

10 U.L.

Q,Q

RESISTOR VALUESCP

7 U.L. WITHRESISTOR
PULL-UPCONNECTED

1*lUNIT LOAD EQUALS 1-LPDT"L9041 OR 9042 ·INPUT LOAD

ARE TYPICAL

3-150

.

_F_A_IR_C_H_l_LD_._M~IC_·R_O_LO_G_l_C®_·_LO_·w_·_·P~OW_ER_·_D_IO_D_E_T_Ft_A--'-N_'Sl_S_TO_·R_·_:t'N_T_E_G_RA_t_E_D_C_IR_C_U_IT_s___.I.__I

LPDTpL 9041-- DUAL 3 INPUT NANO GATELOGIC DIAGRAM SHOWING FLATDESCRIPTION

OR DUAL-IN-LINE PACKAGE PIN. ASSIGNMENT

The L:E>DT µL 9041 element
consistsof two, 3-input positive logic NANO gates' suitabie.
.
.
.
''

for ge'1eral logic gate aqd invet:fer applications. The unique feature of this gate is

HllnERFO«LOWU PUU·UP

14

•cc

that the output tran~istor collector and the emitter follower pull-up are not internally

OUTPUT13

INPUT

RESISTOR
PULL·UPconnected. This .allows the u~er to tie collectors to a common m,xie for the wired"OR" logic function.

12

INPUT

INPUT

II

l~PUT

INPUT

10

RESISTOR
PULL·UP3INPUTOUTPUT

GllOUNO

EMlnERFOLLOWER PULL-UP

WIRED 'OR' APPLICATIONPOSITIVE LOGIC NANO GATEAIc;=c),"'.

AI·Gl_io_ _ _ _,...

c

.

I

I

EACH INPUT • l UNIT LOAD

I::::[)o-----J

OUTPUT FAN-OUT • 10 UNIT LOADS• 7 U.L. WITH RESISTOR
PULL-UP CONNECTED

ABC + DEF + .. • • .+ LMN • Z
OUTPUT FAN-OUT • 10 - 3 (NO. OF RESI sroR
PULL-UPS)EITHER THE EMITTER FOLLOWER OR RESISfOR PULL-UP
MUSf BE CONNECTED TO THE OUTPUT TO ESfABLISH
THE HIGH LEVEL.

CIRCUIT DIAGRAMONE PULL-UP RESISTOR IS REQUIRED FOR EVERY 8GATES CONNECTED TO THE COMMON "OR" NODE.

•cc
14

RESISTOR VALUESARE TYPICAL

3-151

FAIRCHILD MICROLOGIC® LOW POWER DIODE TRANSISTOR INTEGRATED CIRCUITSLPDT1.1L 9042 - DUAL 3 INPUT NANO GATE WITH EXTENDERINPUTSLOGIC DIAGRAM SHOWING FLATOR DUAL·IN-LINE PACKAGE PINASSIGNMENTDESCRIPTION

The LPDTµL9042 element consists of two 3-input positive logic NANO gates with'extender inputs. This element in the family allows theuser to implement logic
applications requiring a gate fan-in exceeding three.
The Dl'µ.L 9933 4-input extender element or equivalent-may be used to provide
additional diode inputs. Any capacitance added to the extender input will increase
the turn-on delay of the LPDTµL9042 gate. Typically, the increase is ions/picofarad. Turn-off delay is not affected.

CIRCUIT DIAGRAM

14

14

•cc

PULL-UP.

13

l~PUT

EXTENDER
INPUT

12

INPOT

INPUT

II

INPUT

INPUT

10

EXTENDER
INPUT

OUTPUTRESISTORRESISTOR

INPUT

PULL·UPGROUNDOUTPUTPOSITIVE LOGIC NANO GATE

•cc

21k

40t

A
8

c

AiCTxT· D

1 8

EACH INPUT • 1 UNIT LOADOUTPUT FAN·OUT • 10 UNIT LOADS• .7 UNIT LOADS WITHRESISTOR PULL-UP
CONNECTED,___-010
RESISTOR VALUESARE TYPICAL,,,.-··

BUFFER ELEMENT
For applications requiring a fan-out exceeding ten, the Fairchild DTµL9930 Dual4-InputGate maybeused. The DTµL9930 will drive
44 LPDT µL unit loads, while maintaining the same output logic levels as the low power circuits.
The input of a DTµL9930 requires the equivalent.of 10 LPDTµL unit loads.
DT j.LL 9930 input.

3-152

Therefore, a low power circuit can drive only oneFAIRCHILD MICROLOGlC® LOW POWER DIODE TRANSISTOR INTEGRATED CIRCUITSPOWER CHARACTERISTICS
VCC = 5V

OPERATING VOLTAGE CHARACTERISTICS
WORST CASE OUTPUT LOGIC LEVELS .• VoH AND VoLINPUT THRESHOLD LEVELS • VIH AND V L

EMITTER FOLLOWER PULL-UP

6.0--;r,-.0-CLOC-:r..-D-FL-J-••-LQ-P_T-_IWC_lMUM_:r_ _ _ _ __5.0 ......__,,__--1--+--+--+---+---+---I

4,01---+---+---+---+---+---+---+----I.?~~..:~~O~Oo~~:~~!. <:::~!~~~OHOO-- 000-00H -··-

:.
"'

~

'

15 3.0 1----''----1--+--+--+---+---+---I

g 1.61--1--11--~l--11-.::::;-....i::--+---:...,-l

~
2,0

0.8

0:9

..:.. &

I

0.1

1. 0 J-- 9041 ,s, 9042 PCMER. PER GATE GATE "OFF" (MAXnrui1_t

Yot M.\X@ FAM-OU'I' • 10 U.L0

0.4

4 S V ;$ VCC S S.S V, VIH APPLIED TO INPUTS.! -~.!..~r--~~!r~--I··~y~:r-·1··

0

o.2s

0.2

0

0'---'---'---'----''----''----'---'--"-75

r--:'0!=41;.•:.='0iii42mPm!llmER"'..PER~(ll;~TE~(ll;;;;T£1-'..;,'W-'..,;(t'IWC-lMUM)-r-""'1"Cll" -\.rr.IcJ). r. . .9.).2.r.P!l/E~. . .rFER. . ..J..r. . .GAT~. T........
r. . . . r. . . .

-50

·25

25
50
TEMPERATURE - °C

75

100

-75

125

-so

-25

0
25
50
TEMPERATURE - °C

75

...

100

125

LOW LEVEL NOISE IMMUNITYHIGH LEVEL NOISE IMMUNITY~

g== 0.6..;Q

0.5 1---1---1--___,r---___,_ _ _ _ _ _ _~0.81---1---t-."'""l--___,l--___,f--___,l----t-"'""'1
4.5 v svcc 5 s.s v

1 :$ FAN-OUT $ 10

0.6 ,___.....,.,_,___,____,....._EMITTER FOLLOWER
PULL-UP

0.4'----'---'--~'----''----''----'---'--'

-75

-50

-25

50
TEMPERATURE - °C
0

25

75

100

0.4'--'--'-----''----''----'----'----'----'--'

125

-75

3-153

-50

-25

0
25
50
TEMPERATURE - °C

75

100

125

FAIRCHILD MICROLOGIC® LOW POWER DIODE TRANSISTOR INTEGRATED CIRCUITSTEST CIRCUIT

r<f: ~r<fEH>-9-f:D'~.
I' . I'I'~

TYPICALAVERAGE PROPAGATION DELAY
LPDT11.L 9041•9042

Your

T

"="

'::'

CONDITIONSYee • 5:aY, CL• lOpl UNCLUDING PROBE' AND 'JIG 'cAPACITANCEIYMEA5URE • 1.6Y I ·55°C
IGNO. REF.ll.3Yt2S°C
0.9Y f.125°C'NOTE:WAVE FORMS

lelistive Loading up to Maximum
Fan..OUt, Typically Improves the -+--+---<
Average Prcipagacldn Delay~YME~E

SO'----'~-'-~....____...___,.____.~_.____.

-7S

-so

-25

0.
25
so 7S
TEMPERATURE • °C .

100

125

-i

-.1 ~ ~ . .

~MEASURE

TEST CIRCUITPULSE GEN.

YtN

TYPICAL DELAY CHARACTERISTICS
LPDT11L 9040

s

So

ij

rl . .

T

PULSE GEN.

c

Q

Co

¥001 .

YouT!CL'='

YtN

CONDITIONS
Yee. 5.0V, CL. 50pl UNClUDING PROBE AND JIG CAPACITY}'YMEASURE • l.6V t ·55°C
IGND. REF.I l.3Y I

2S°C

0.9V I l2S°C
ro'---'-~-'-~-'-~'----'~-'-~-'----'.-1s -so

-25

2S

so

7S . 100

125

WAVE FORMSTEMPERATURE - °C

Y1N~.
-YMEASURE. .

YfN--rc:::
I
.
--i
r
-VME~RElpl)..

tp~+ You~-.YouT. 3-154 .

YMEASURE.

·

VMEASURE·IMpl9033
16·BIT MEMORY CELLMEMORY MICROLOGIC® INTEGRATED CIRCUITSA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRIPTION - The MµL9033 is a Planar* epitaxial integrated 16·bit. bit-oriented, non-destructiVQ
readout memory cell, compatible with Fairchild Transistor-Transistor Micrologic® (TTµL) and other Compatible
Current-Sinking Logic (CCSL) integrated circuits. This memory cell, organized as 16 words by one bit, isdesigned for high-speed scratch-pad memory applications.

OPERATION - The memory cell consists of 16 R·S flip-flops arranged in an addressable four-by-four matrix.
The desired bit location is selected by raising the coincident X-Y address lines to a logic "H" level (>2.1
volts) and holding the non-selected address lines at logic ''.L" level ( <0.7 volts). As many as four locations
may be ad'dressed simultaneously without destroying stored information. The stored data and its complement
at the addressed bit location may be read at the output terminals. If the addressed bit location contains a"l", the S1 output will be low and the S0 output will be high. If the addressed bit location contains a "O",the S1 output will be high and the S0 output will be low.

PHYSICAL DIMENSIONSIn Accordance WithJEDEC (T0-116) Outline
Dual In-Line Package.020 Ml~.-ft::i.12sivP.-~

1

.110

.090

Writing is accomplished by activating one of the write amplifiers. To write a "l", the desired bit location isaddressed and the input of the "write one" (W 1) amplifier is raised to a High level. To write a "0", theinput of the "write zero" (W0) amplifier is raised to a High level.
The outputs are open-collector, which may be wire "OR"ed for word expansion. (The output transistors are
off when none of the bits are selected.) An external resistor should be returned to Vee to pull:up thewire "0 R" ed outputs.

NOTES:
1. Leads are intended for insertion in hole rows
on .300" centers. They are purposely shippedwith "positive" (.350) misilignment to fa.

cilitate insertion.
2. Board drilling dimensions should equal yourpractice for a conventional .020 inch diame-

FEATURES• CCSL COMPATIBLE• OUTPUT WIRED·OR CAPABILln• TRUE AND COMPLEMENTARY OUTPUTS ARE PROVIDED• NON DESTRUCTIVE READ OUT

ter lead.

PHYSICAL DIMENSIONSIn Accordance WithJEDEC (T0·86) Outline
CEttPAK I 14 lead

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Yee Pin Potential to Ground
Input Pin Voltage
Current Into Output Terminal
Output Voltage-65°C to +150°C-55°C to +125°C-o.5 vto +s.o v-1.5 Vto +5.5 V

lOOmA-0.5 vto +s.o v

ORDER INFORMATION - Specify A319033XXX for Flat Package or A6A9033XXX for Dual In-Line (T0-116) pack·age where XXX is SIX for -55°C to 125°C temperature range or 59X for the 0°C to 75°C range. The last
digit in the order code is 1 for 40 mA Fanout and 2 for 20 mA Fanout.

Xo--X3 Yo--Y3
Wo

. W1

9033

*Planar. is a patented l'"airchild process.

l=AIRCHIL-C>
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALll'ORNIA, (415) 962-5011, TWX: 910-379-6435

3-155

SEEMICONC>UCTOAA DIVISION·oF FAlf:tCHILO CAMERA ANO INSTRUMl::NT CORPORATIONFAIRCHILD MEMORY MICROLOGIC® INTEGRATED CIRCUIT • Mµ,L9033
ELECTRICAL CHARACTERISTICS (TA= -55°C to +125°C, Vee= 5.0 V ±10%)
SYMBOL

LIMITS
MIN. MAX.

TEST

IFX
IFY
IRX
IRY
IFw
IRw
Ice
lsv
lcex
VOL
VXY(W)X Address Input Load Current
Y Address Input Load Current
XAddress Input Leakage Current
Y Address Input Leakage Current
Write Input Load Current
Write Input leakage Current
Power Supply Current
Power Supply Current at Vee = 7 V
Output Leakage Current
Output Low Voltage
Address Input Threshold to Prevent Writing

VXY(W)

Address Input Threshold to insure Writing

2.1

VXY(R)VXY(R)

Address Input Threshold to Prevent Reading
Address Input Threshold to Insure Reading

2.1

VW(W)

Write Input Threshold to Prevent Writing

VW(W)•Write Input Threshold to Insure Writing

UNITS

TEST CONDITIONS

mA
mA
µA
µA
mA
µA
mA
mA
µA

11
11
400
400
1.5
100
65
84
250
0.45
0.75

Vee= 5.5 V, Vx = 0 V, Vy= 4.5 V, other X inputs grounded
Vee = 5.5 V, Vy = 0 V, Vx = 4.5 V, other Y inputs grounded
Vee = 5.5 V, Vx = 4.5 V, other X and Y inputs grounded
Vee = 5.5 V, Vy = 4.5 V, other X and Y inputs grounded
Vee = 5.5 V, Vw = OV
Vee= 5.5 V, Vw = 4.5 V,
Vee= 5.5 V, All Inputs Grounded
Vee= 7.0 V, All Inputs Grounded
Vee= 5.5 V, Veex = 5.5 V, all inputs grounded
Vee= 4.5 V, One Bit Selected IOL = 20 mA (A6A9033512 · A3F9033512)
Vee= 5.0 V, other X and Y grounded. Alternately pulse W0 and W"
cell must not change state.
Vee= 5.0 V, other X and Y grounded. Alternately pulse W0 and W"
cell state must alternate.
Vee = 5.0 V, other inputs grounded. Both outputs must be on "high" state.
Vee= 5.0 V, other X and Y grounded. Alternately pulse W0 and W1,
cell state must alternate.
Vee = 5.0 V, one X and one Y to 4.5 V, other X and Y grounded. One write
input to Vwcwl' pulse the other write input. If W0 is pulsed, S0 will assume
low state. If W1 is pulsed, S1 will assume low state.
Vcc = 5.0 V, one X and one Y to 4.5 V, other X and Y grounded. One write
input to Vwiwi• pulse the other write input. If W0 is pulsed, S1 will assume
low state. If W1 is pulsed, S0 will assume low state.

v
v•
v•

0.8

v
v•

0.8

v•
v•

2.1

ELECTRICAL CHARACTERISTICS (TA= 0°C to 75°C, Vee= 5.0 V ± 5%)
SYMBOL

LIMITS
MIN. MAX.

TEST

IFX
fFY
IRx
IRY
IFW
IRW
Ice
lsv
lcex
Vol

XAddress Input Load Current
YAddress Input Load Current
XAddress Input Leakage Current
YAddress Input Leakage Current
Write Input Load Current
Write Input Leakage Current
Power Supply Current
Power Supply Current at Vee = 7 V
Output Leakage Current
Output Low Voltage

11
11
400
400
1.5
100
65
95
250
0.45

VXY(W)

Address Input Threshold to Prevent Writing

0.8

VXY(W)

Address Input Threshold to insure Writing

2.0

VXY(R)VXY(R)

Address Input Threshold to· Prevent Reading
Address lnputThreshold to Insure Reading

2.0

VW(W)

Write Input Threshold to Prevent Writing

VW(W)Write Input Threshold to Insure Writing

TEST CONDITIONSUNITSVee = 5.25 V, Vx = 0 V, Vy = 4.5 V, other X inputs grounded
Vee = 5.25 V, Vy = 0 V, Vx = 4.5 V, other X inputs grounded
Vee = 5.25 V, Vx = 4.5 V, other X and Y inputs grounded
Vee= 5.25 V, Vy= 4.5 V, other X and Y inputs grounded
Vee= 5.25V, Vw= OV
Vee = 5.25 V, Vw = 4.5 V
Vee= 5.25 V, All Inputs Grounded
Vee= 7.0 V, All Inputs Grounded
Vee= 5.25 V, Vcex = 5.5 V, all inputs grounded
Vee= 4.75 V, One bit selected loL = 20 mA (A6A9033592. A3F9033592)
IOL = 40 mA (A6A9033591 • A3F9033591)
Vee= 5.0 V, other X and Y grounded. Alternately pulse W0 and W1,
cell must not change state.
Vee = 5.0 V, other X and Y grounded. Alternately pulse W0 and W1,
cell state must alternate.
Vee= 5.0 V, other inputs grounded. Both outputs must be on "high" state.
Vee= 5.0 V, other X and Y grounded. Alternately pulse W0 and W1,
cell state must alternate.
Vcc = 5.0 V, one X and one Y to 4.5 V, other X and Y grounded. One write
input to Vwiwi• pulse the other write input. If W0 is pulsed, S0 will assume
low state. If W1 is pulsed, S1 will assume low state.
Vee= 5.0 V, one X and one Y to 4.5 V, other X and Y grounded. One write
input to Vwcwl' pulse the other write input. If W0 is pulsed, S1 will assume
low state. If W1 is pulsed, S0 will assume low state.

mA
mA
µA

µA
mA
µA

mA
mA
µA

v

v•
v•

1.0

v
v•

1.0

v•
v•

2.0
;

• Amplitude of the pulse ;;::: 2.5 V, pulse width ;;::: 100 ns. The cell state is determined 35 ns after pulse disappears.

SWITCHING CHARACTERISTICSSYMBOL

twp

CHARACTERISTICS
Write Pulse Width

9033511-55°C to 125°C
MIN.
MAX.
25

9033591

MIN.

MAX.

CONDITIONS

9033592

o·c to 1s•co•c to 75°c
MIN.

UNITS

MAX.
ns

25
25

twR

Write Recovery Time

40

ns

35
35

ton

Turn On Delay

25
35

ns

20
30
20
30

to ff

Turn Off Read Delay

25
35

ns

20
30
20
30

'---

3-156

LOAD
(mA)
20
40
20
40
20
20
40
40
20
20
40
40

CL
(pf)

INPUT
Vee = 5.0 V, One X-Y Location
Selected

30
30
30
100
30
200
30
100
30
200

Vee= 5.0 V, One X-Y Location
Switched

FAIRCHILD MEMORY MICROLOGIC® INTEGRATED cn~c~.JIT .• MµL9033
TYPICAL ELECTRICAL CHARACTERISTIC~
ADDRESS INPUT READ
THRESHOLD VOLTAGE-VERSUSAMBIENT TEMPERATUREADDRESS INPUT LEAKAGE
CURRENT VERSUS
INPl!T VOLTAGE

ADDRESS INPUT LOAD
CURRENT VERSUS
ltiPUT VQLTAGE

2.D ..--..---....-..---.---....-..----.--,

160

Vee· s.ov

Vee ·5.DVAll OTHER X·Y
LI NI'S GROUNDED

Vee ·5.DV--+--+-+---+----+ ONEX OR ONEY~MEASURED.ALL".D
OTHER X AND Y
6 ~"h~T04.5V

1----1----l----l-+- ONE X·Y LOCATION
SElfCTEDf'-.-

1.0 l--l--+-l--l--+-1---1---l

J--TA• 125°C

1-.,l". :!A_" 25°C
l.D

I
~

~

3.D

D

4.D

r

:::2 TA • -55°C

2..D

D

0.5 l---+---+-l---+---+-1---+--l

4.D

6.D

8.D

D.___.___.__....__.___.__....__.___.
~~~o 25 w 75 m ~ADDRESS INPU) VOLTAGE - VOLTS

ADDRESS INPUT VOLTAGE - VOLTS

TA - AMBIENT TEMPERATURE - °C

OUTPUT CURRENT VERSUSOUTPUT SATURATION VOLTAGE

POWER DISSIPATIONVERSUS AMBIENT TEMPERATURE~EAD DELAY VE~SUS
AMBIENT TEMPERATURE
20 mA LOAD

Jlli

400

60 l---t---t--l---t----Jil/_'-:::::j"""...,.,-1
rTA•25oC

"300

_!

80

i

2.D

L

_.,,

Vee. 5.0V
I
ONEX-Y LOCATION SElfCTED

40

~'(/

30

•

.vi:J5.ov:::cc:! 4.5V

Jl2Dl--l--Wl~~l-+---l--I-+-~
Av

40

30

_y

Q.2

.D.4

D.6

0.8

10

0
-75

-50

-25

25

51)

. . .: : : : : : . :~:: :~:. . . :·····:::c;;;

20

0

0

20mA LOA_..D '---+--+-+---+--+--lcl. JOpF
CL• lOOpF----

Vee' S.5v

40 t---+--+-f-c//H+-+---+--+--;' /_TA •·55°C

0Vee· 5.Dv

IL INPtrr PIJGRolDm-;;_;}

75

100

125

~..J-...j,,,==t::-::::i::.f-i;;,+v-1--+---1o'---'--'---J'---'--'---J'---'---'
~

~

o

~

25

30

75

m

~

OUTPUT SATURATION VOLTAGE - VOLTS

TA - AMBIENT TEMPERATURE- °C

TA - AMBIENT TEMPERATURE - °C

READ DELAY VERSUSAMBIENT TEMPERATURE
40 mA LOAD

WRITE P!JLSE WIDTHVERSUS AMBIENT TEMPERATURE

WRITE RECOVERY TIMEVERSUS AMBIENT TEMPERATURE

20

Vee -s.ov
40mA LOAD
cl. 30pF
CL. 200pF -·--

40

TT

Vee· 5.ov
20mA LOAD
cl. 30pF

Vcc·5.DVONE X·Y LOCATION SElfCTED-1-+---.--+---+---1
1530······ ············ 'f~~ ....... ············ ······
201---+--+---+--+... ~'!.::f:::::=­
r···-····_····+··_····_····_·t----+---+-~

10~-l=~:::::i:::=P1;:o11 +---..J..--1

10

D

·75

TA - AMBIENT TEMPERATURE - °Ct----.........

20

~

-50

-25

D

25

5D

75

100

125

0

-75

-50

-25

25

30

20mA

5 · 0:LOA0~400

OUTPUT.,,. -= 5600
WRITE
PULSE
GMD_.............,I

,,,,

40mA

5 -0Y
LOA0~
120!l

OUTPUTOUTPUT

cl

3-157

75

TA· AMBIENT TEMPE~ATURE ·°C

TA - AMBIENT TEMPERATURE - °C

I

.330!l100~

FAIRC~llD

MEMORY MICROLOGIC® INTEGRATED CIRCUIT • Mµ,L9033

APPLICATION:
A memory utilizing 9033 memory cells may have any desired word length. The number of words in the memory is a multiple of four words. The following
example of a s4 worci memory illustrates how a number of 16 bit memory cells 9033 may be used to constru~t a typical memory.
The 64 wor~ memory as shown in Figure A consists of groups of four 9033 memory cells. Each of the groµps of four 9033 memory cells supplies one
bit for each of the 64 words storlld in the memory. All bits belonging to one word are stored in the same address location. Therefqre, the address of aword in the memory is the address of each of ttie bits of !he addressed word in the groups ot' four 9033 memory cells. The equal outputs of thll fourmemory cells are tied together so that each group of four memory cells has one high and one_ low level output.
· ·The six memory address li~es from an exter11al source are decoded at the first level with two "!1301 decoders, The fourth input to each of the two decoders can be used as an 11nabfe control input to the 64 word memory. If the address enable is at a low logic level, one and only one· of the eight
outputs, 0 to 7, in the illustration assumes a low logic level. If the address enable is at a high logic ·level, the outputs 0 to 7 of the two decoders
assume a high logic level, thus non11 of the 64 words stored in the memory is addressed. The outputs, 0 to 7, of the two decoders serve as X-and-Y
address lines. The output signals of the decoders are connected to driving transistors which prpvide the necessary curre11t to address t~e memory cells.
The example given above is only one of the many organi?:ati 0ns and is presented as an illustration. Obviously many address decoding schemes may beutilized depending on memorr si~e, driver fan-out, decoder fan-out, wiring, heat dissipation, etc.
Figures B through D show ~lternative schemes to enter data into the memory cell.

LOGIC plAGRAM

fig. BDOUBLE RAIL ACTIVE
LOW INPUTS AND ENABLE

Fig. AMEMORY ADDRESS LINESTO CELLS

4
4

r

4

BIT 0

BIT 1

BIT 2

--------------------,---,---,

I

Xo•-x3 Yg--Y3

lg-~X3

Wo

Wo

W1

Yg--Y3Fig. CSINGLE RAIL ACTIVE
HIGH INPUT AND ENABLE

W1
9033

9033

DATA

· ENABLE

I
I
I
I
I
I
I
I
I
I
I

Xg-'-X-3 Yq-:--Y 3

x 0 -~x3

Wo

Wg

W1

W1
9033

9033
So

Y'g--Y3

Sg

S1

I
I

I
I

I
S1

II

I

I

Fig. DSINGLE RAIL ACTIVE
LOW INP\..!T AND ENABLE'--~1---~+-~~~-+~-+'I

I

I
I
I
I
IV cc

I
I
I

~9016

~9016

DATA

I

Yccl

\19002I

I

WRITE ENABLE

TO CELLS

L-~

?

g

...iii

~

•

?
5;
~

•

...6
3-158

Mpl9034
256-BIT READ-ONLY MEMORYMEMORY MICROLOGIC® INTEGRATED CIRCUITSA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRIPTION - The Fairchild MµL9034 is a 256-~it bipolar transistor read-only niemory. The
memory is organized as 32 words of 8-bits each. The words are selected ijlrough 5 address lines. The 8
outputs of the words are uncommitted collectors which may be Wired·OR'd with the outputs of other ROMs.
An Enable input is provided for additional decoding flexibility. A high on the Enable input forces all outputs
to be high.

PHYSICAL DIMENSIONS·~:~~.009iffi\.Oil

The contents of the memory are· permanently programmed to customer order.

.200 MAX.

FEATURES:• CCSL COMPATIBLE• OUTPUT WIRm-OR'D CAPABILITY• SINGLE TTL LOAD INPUTS

1.-.375 - · ~

L

'

.023
MAX.

NOTO:
1. Leeds ere intended tor insertion in hole rows on

ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Temperature (Ambient) Under Bias
Vee Pin Potential to Ground
Input Pin Voltage
Current Into Output Terminal
Output Voltages-65°C to +150°C-55°C to +125°C-0.5 vto +s.o v-1.5 V to 5.5 V
lOOmA-0.5 V to Yee Value.300" centers. They ue purposely shipped with"positive" 1.375) m1s1li1nment to facihtate insertion.
2. 801rd·drilhn1 dimensions should equal yourpractice for a convention1I .020 linch diameter lead.

LOGIC. Dl,4\GRAM

15 10 11 12 .13 14

ORDER INFORMATION
Custom Code-Specify A6B9034XXX where XIX is for -55°C to +125°C temperature range or X9X is for
0°C to +75°C temperature range. Remaining X's are to be assigned alphabet letters to customer code.
Standard Code Available - Two standard preprogrammed 9034s are available for evaluation purposes.
. The A6B9034AXA contains the numerals 1 through 6; the A6B9034AXB contains the figures 7 through0, a comma, and a period. For additional information on these two programmed 9034s refer to theirrespective data sheets.

E Ao Al A2 A3 A49034
32W x BB X ROM
o0 o1 o2 o3 o4 o5 06 o7~ ~il (il il il ~il ~il Q

GND =8

Vee = 16

12345679

l=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-159

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATiONFAIRCHILD MEMORY MICROLOGIC® INTEGRATED CIRCUIT MµL9034
ELECTRICAL CHARACTERISTICS <T. .

= -55°C to +125°C, Yee= 5.0 v±10%)-ss 0 cMIN.
MAX.

LIMITS+2s 0 cMIN.
MAX.

+12s 0 c
MIN.
MAX.

Address Input Load Current
Enable Input Load Current
Addi'ess Input LeakageCurrent
Enable Input Leakage Current
Output'Leakage Current

-1.6
-1.6
·100
100
200

-1.6
-1.6
100
100
200

VoL

Output Low Voltage

0.4

VIL

Input Low Voltage

0.8

VIH

Input High Voltage

lpoPower·Supply Current

SYMBOL

TEST

IFA
IFE
IRA
IRE
leex

2.0

UNITS

TEST CONDITIONS

-1.6
-1.6
100
100
200

mA
mA
µA
µA
µA

VA= 0.4 v
Yee= 5.5V
Ve= 0.4V
Yee=5.5V
VA =4.5V
Yee=5.5V
Yee=5.5V
Ve=4.5V
Yee=5.5V
Yeex 5.5 V
Enable input to 2.0 V

0.4

0.4

v

0.9

0.8

v

Yee= 4.5 V
lour= 10 mA
The word containing a "l" brt isse.lected when performing this test.
Yee= 5.5V
Enable input grounded. Monitor
appropriate output toguarantee this test.

1.7

v

1.4

80

80

80

MAX.

LIMITS
+25°c
MIN.
MAX.

+75°c
MIN.
MAX.

mA

=

Yee =4.5V
Enable input grounded. Monitor
appropriate output toguarantee this test.
Yee= 5.5V
All inputs grounded

ELECTRICAL CHARACTERISTICS (TA= 0°C to +75°C, Yee= 5.0 v ±5%)SYMBOL

TEST

0°C
MIN.

UNITS

TEST CONDITIONS
VA=0.45V
Yee= 5.25V
Ve= 0.45 V
Yee=5.25V
VA =4.5V
Vee= 5.25V
Yee =5.25V~-=4.5V·Yeex 5.25 V
Yee =.5.25V
Enable input to 2.0 V
Yee =4.75V
lour= lOmA
The word containing a "l" bit isselected when performing this test.
Yee= 5.25V.
Enable input grounded. Monitor
appropriate output toguarantee this test.
Yee =4.75V
Enable input grounded. Monitor
appropriate output toguarantee this test.
Yee ='5.25V
All inputs grounded

IFA
IFE
IRA
IRE
leex

Address Input Load Current
Enable Input Load Current
Address Input Leakage Current
Enable Input Leakage Current
Output Leakage Current

-1.6
-1.6
100
100
200

-1.6
-1.6
1.00
100
200

. -1.6
-1.6
100
100
200

mA
mA
µA
µA
µA

VOL

Output Low Voltage

0.45. 0.45

0.45

v

VIL

lnputlow Voltage

0.85

0.85

0.85

v

VIH

Input High Voltage

lpoPower Supply Current

1.9

1.8

80

80

SWltcHING TIME CHARACTERISTICS (TA = 25°C)
LIMITS
SYMBOL

TEST

t++

t+-

Enable andAddress Delay
Enable andAddress Delay
Address Delayt_+

Address Delay

t --

MIN.

TYP.

MAX.

UNITS

*

50

ns

*

50

ns

*

50

ns

*

50

ns

v

1.6

TEST
CONDITIONS
10 mAload.
See Note 1.
lOmAload.
See Note 1.
10 mAload.
See Note 2.
lOmAload.
See Note 2.

•see Typical Electrical Characteristics curves.
3-160

80

mA

=

NOTES:(1) To test Enable delay, apply Input pulse to Enable input. The word
selected must contain a "1" in the bit under test.
To test Address delay, the Enable input must be low. Apply the
input pulse to the Address input under test. The Words selectedmust contain a "l" when input pulse is low and a "O" when
input pulse is high in the bit under test.
(2) To test Address delay, the Enable input must be low. Apply the· input pulse to the Address input under test. The words selectedmust contain a "0" when input pulse is low and a "1" when
input pulsa is high in the bit under test.

FAIRCHILD MEMORY MICROLOGIC®. INTEGRATED CIRCUIT Mµ,l9034
SWITCHING TIME TEST CONDITIONS AND WAVEFORMS-.,._5.0ns

ADDRESS OR
ENABLE INPUT

2.DV
1.5V

1.0V

-s.ons

2.0V
1.5V

SWITCHING TEST OUTPUT LOAD

1.0V

200ns-

5.0V
1.5V

- -

OUTPUT----

ADDRESS INPUTtt++-s.ons4700-s.ons

f-2.0V
1.5V

1.0V-ii--

2.0V"'s
1.5V

OUTPUT

k;J.OV

1.0kQ

200ns

OUTPUT-}.sv\ ,.5V- -t+- i--

10mA LOADt_+

LOADING RULES....-----TT...:..µ_L_IN_P_U~T LOAD AND DRIVE FACTORSINPUTSLOADINGAll inputs

1.7 /1 U.L.

CCSL INPUT LOAD AND DRIVE FACTORS....-------~OUTPUTSDRIVE FACTOR

All outputs

Open Collector-----U.L.

INPUTSLOADINGOUTPUTSAll inputs

20/10

All outputs

1-----------1

DRIVE FACTOR
Open Collector

62.5 .

6.25
l

U.L. = l ITµL Input Loadl CCSL High Level Load Factor= 5.0 µA
l CCSL Low Level Load Factor= 160 µA

TYPICAL ELECTRICAL CHARACTERISTICS
INPUT THRESHOLD VOLTAGE
VERSUSAMBIENT TEMPERATURE

INPUT LEAKAGE CURRENTVERSUS INPUT VOLTAGE

INPUT LOAD CURRENTVERSUS INPUT VOLTAGE

3.0 ....-~~~~---..-....-T~~

Vee; 5.ov

II

ll_IJLITTA - -55°e"3. 120 t---+---+--+---+-t-11+----t---i-0.2 f-+-+---t--+-l'--lf-IF~-+-<--1-+--I
I-{- TA - 25°e

2.0 t---+--+--1--+~-!--+--l-OA f-+-+--+-+J+lro~H-lf-1--+TA_-1._2.5°-+e-+--I

I-ii(O'--..._-"-_.__.____._,__...___,-LO ~~-"--'--''---'---'--'--~---'---'
3,0
O
0.5
l.O
1,5
2.0
2.5

2.0

4.0

8.0

6.0

~

~

~

o

n

m n

~

INPUT VOLTAGE- VOLTS

l NPUT VOLTAGE - VOLfSTA - AMBIENT TEMPERATURE - °C

OUTPUT CURRENT VERSUSOUTPUT VOLTAGE

ADDRESS INPUT DELAY VERSUSAMBIENT TEMPERATUREENABLE INPUT DELAY VERSUSAMBIENT TEMPERATURE

80 .--...,.---.---...---..-.,.----r-~--.

w....-...,.--.---,.--,.-.,.--...,.-ve-e·~5.--.ovt---+--+--+--+-+---+lOmA LOAO
el· 30pF
60 I---+--+--+--+-+---+--+---<

1--+--+---+---t---t--+lOmA LOAD

Vee • 5.ov

301---+--+--+---+-+---+---+---I~

me, - 30pf'" t2J

20 ~+--+--,,..v""'h(.J.--+-1---+--i:'>t---+--+-_,/'..J.",_,,,_,,_ t---1 ~- -55"e-j-c-10f-+--711.1';~"7'-+-+-+--+--+--J

A_V

0

O.l

0.2

0.3

0.4

0.5

0.6

OUTPUT VOLTAGE - VOLTS

0.7

0,8

O'--....___.__,___._...___i__.___,~~~o B m n ~ rnTA - AMBIENTTEMPERATURE • 'e

3-161........

o~~~~~-~

·75

·50

·25

0

25

50

~~

75

TA - AMBIENT TEMPERATURE· 0 e

100

125

.

FA_IR_C_H_IL_D_._M_E_M_O_RY_-_M_IC_R_O_L_O_Gl_C_®_IN_T_E_G_R_AT_E_D_C_l_R_CU_l_T_M_µ_L_9_03_4_ _ _. _ I_ _ _ _----J

APPLICATJONS:The Fairchild MµL9034 Read-Only Memory has. many storage and display applications. Two main uses of the memory are for microprogrammed subroutines(core replacements) and character generator display systems.
APPLICATION OF THE 9034 READ-ONLY _MEMORY IN DIFFERENT TYPES OF DISPLAY SYSTEMS.
In the application of this ROM as display storage, the Enable input is the most importarit control, since every display system requires a number of ROM'sorganized in parallel to each other. The effectiveness of such a character storage system depends on the flexibility in addressing a desired character. Mostof the character storage systems will be character code oriented.

16 SEGMENT DECODER
CHARACTER CODE INPUT

32

128

I 2 4 8 18

111

1/49002

j_l

l

)_1

EA0A1A2A3A.f

E Ao At A2A3 A4
9034

9034

Do 0, 02 03 04 05 Os 07

o0 01 82 03 04 05 0& 07

ii iii iii

iilliiii

9 10 11 12 13 14 15 18

TO SEGMENT 1 2 3 4 5 & 7 8This figure llllistrlltes th Ullt of two 9034 ROM s for driving a 16 segment decoder. The cheracter code Is used dlrectlr asa control for both ROMs. One additional 3-input gate controlling the enable inputs of the two ROMs is required for salectlng
the 1roup of codas within the ASCII srstem which refer to the characters. For uninterrupted control,two lioMs are required
for each of the 16 sagment dlspla;r units.

DISPLAY GENERATOR 5 x 8 DOT MATRIX,....-... __..,
l!i~~=:::__..,==~ e t-~-+~~.....t-t,_~~~~~-+~----.
I!~

I;;__..,_,.J~A..

...

-

E~~~~~

5__,..., .

CP

t-+-1

..

~)

--~=-,;.....<~~DI9034

Oo 0, 02 03 04 05 05 07

11

j>Q

t-+-1 ~'-H ... 1--

E~~~~~. 9034

1:

Oo 0t 02 03 04 05 05 _07

9

j>

jj

~~~~-t-t-t--t-1-+-~J~i....._.
CLOCK

T

LINE PATTERN INFORMATllN

The five 8-blt words repfllltntin1 the 5 x 8 dot pattern of a figure are stored In sequence. The external source which calls
for a figure has to supply the address of the first 8-bit word of this figure. The clock will Increment this address bJ one
each time the generated pattern has bean dlsplaJld until all five 8-bit patterns hen been used. The mod. 5 counter calls
for the first line address of the nelt figure automatlcallr.
If these data are usad to control a CRT displar the outputs of the two 9034 ROM s mly be connected to an 8-channal
multiplexer (3705) which as an Interface to the Z modulation input of the dlsplar unit. The el1ht- channels ara
salected in sequence bJ a mod. 8 counter of which the eight output generates the control pul- for the mod. 5 and theaddress counter.

3-162

MµL9034AXA
256-BIT READ-ONLY MEMORYMEMORY MICROLOGIC® INTEGRATED CIRCUITSGENERAL DESCRIPTION
The 9034 Read-Only_ Memory code AXA (9034AXA)_ is programmed to

LOGIC SYMBOL

store information for generating Figures 1 thru 6 on a 5 by 8 dot patterndisplay. The memory stores the information by using 5 consecutive wordsof 8 bits for each figure or symbol.

15 14 13 12 11 10

PHYSICAL DIMENSIONS

~~~
. ffi
Il-.374NOM+...1

OPERATION AND ELECTRICAL CHARACTERISTICS.011

Refer to 9034 Data Sheetl.
E A4 A3 A2 A1 Ag

ORDER INFORMATION
Specify A6B9034AXA where AlA is for -55°C to +125°C temperature· range or A9A for the 0°C to + 75°C temperature range.

.1001
MIN.

9034
32W x BB XROM
01 02 03 04 05 Os 07 09~;l" ~;,- I~ I;l n ;lljJ

009

r=

~

v

12345679

GND=avee = 16
9034AXA TRUTH TABLE

0

u

T
p

u

T

s
I

N

o,
02
03

o..

05
06
07
Os

Ao

p

A,

T

A3
A4

u
s

Ai

H
L
H
H
H
L
L
L

L

H
H
H
H
H
L
H
H

L L
L H
L H
L L
H H
H H
H H
L L

L L
H H
H H
L L
H H
H H
H H
L L

L
H
L
L
H

H
H
L
L·
H

L H
L L
H H
L L
H H

L
H
H
L
H

H
L
H
H
H
H
L
H

L
H
H
H
H
H
H
L

L L H
H H L
H H L
L L H
H H L
H H L
H H L
L L H

H
L
L
L
L
L
H
H

H
H
H
H
H
L
H
H

H
H
H
H
H
L
H
H

L
L·
L
L
L
L

H L
L H
L L
H H
L L

H
H
L

L
L
H
H
L

H
H
H
H
L

L
L
L
L
H

H
L
L
L
H

H H
H H
H H
H H
H H
H H
H H
ti H

L H L
H L H
H L H
H L L
L L H
L L H
L L H
H H L

L
H
H
L
H
H
H
L

L
H
H
L
H
H
H
L

H
L
H
H
L
L
L
H

H l
L H
L L
H H
H H

H
H
L
H
H

L.
L
H
H
H

H L -H
L H H
H H H
H H H
H H H

H H
H L
H H
H H
H H
H H
H H
H L

L
L
L
L
L
L
L
L

H
H
H
H
H
H
H
L

H
H
H
H
H
H
H
H

L
H
H
H
L
H
H
L

L
H
H
L
H
H
H
L

L H
H L
L H
H H
H H
H H
H H
L L

L
L
L
L
L

H
L
L
L
L

L
H
L
L
L

H
H
L
L
L'

L H L
L L H
H H H
L L L
L L L

H
H
H
L
L

L
L
L
H
L

1

2

3

4

5

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22. 23 24 25 26 27- 28 29 30 31 32

lt

L

L
H
H
H
L

L

H
H
H
L
H

L
L
L
H
H

0I
0

u

T

02
03

p

o..

u

Os

T

s

06
07
Os.
Q

=
0

:;:

L - Low Voltage

67

H - High Voltage

F=AIRCHIL..C>
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011._ TWX: 910-379-6435

3-163

SEMICONDUCTORA DIVISION Of FAltfc:HILO CAMERA ,AND INSTRUMENT CORPORATIONMµL9034AXB
256-BIT READ-ONLY MEMORYMEMORY MICROLOGIC"' INTEGRATED CIRCUITSGENERAL DESCRIPTION
The 9034 Read-Only Memory code AXB (9034AXB) is programmed tostore information for generating Figures 7 thru 0, a comma and period
on a 5 x 8 dot pattern display. The memory stores the information byusing 5 consecutive words of 8 .bits for each figure or symbol.

LOGIC SYMBOLPHYSICAL DIMENSIONS

15 14 13 12 11 10

IF. =ii..Q.

I63+.009

OPERATION AND ELECTRICAL CHARACTERISTICS
Refer to 9034 Data Sheetr-315-1.
300

.
.Oil

ORDER INFORMATION
Specify A6B9034AXB where Al B is for -55°C to +125°C temperature
range or A9A for the 0°C to + 75°C temperature range.

E A4 A3 A2 At Ao

.1001

9034
32W x 88 X ROM
Dt 02 03 04 05 05 07 09

.105

~

..J

r.-.374NOM .

MIN.

r=

.095

I~ ;l ;l ;l ~~ ~~ Q

2345679
GND = 8

Vee= 1s
9034AXB TRUTH TABLE

0

u

T

p

u
T

s
I

N

p

u

T

s

07
Os

L
L
H
H
H
H
L
L

L
H
H
H
H
L
H
H

L
H
H
H
L
H
H
H

L
H
H
L
H
H
H
H

L
L
L
H
H
H
H
H

H
L
L
H
L
L
L
H

H
L

H
L
H
H
H
L

Ao
A1
A2
Al
A4

L
L
L
L
L

H
L
L
L
L

L
H
L
L
L

H
H
L
L
L

L
L
H
L
L

H
L
H
L
L

L
H
H
L
L

H
H
L
L

01
02
03
04
05

ob

L

L

H H
H
L
H

H

H

H H

H
L
H
H
L

L
H
H
H
L
H
H
L

L
H
H
H
L
H
H
L

H
L
L
L
L
L
L
H

H
L
L
L
L
L
L
H

L
H
H
H
H
H
H
L

L
H
H
H
H
H
H
L

L
H
H
H
H
H
H
L

H
L
L
L
L
L
L
H

H
H
H
H
H
H
H

H
H
H
L
L
H
L

H
H
H
H
L
L
L
H

L H
H H
L L
H .H
L L

L
L
H
H
L

H
L
H
H
L

L
H
H
H
L

H
H
H
H
L

L
L
L
L
H

H
L
L
L
H

L
H
L
L
H

H
H
L
L
H

L
L
H
L
H

H
L
H
L
H

L
H
H
L
H

L
H
H
L
H
H
H
L

H
L
L
H
L
L
L
H

H
L
L
L
H
H
L
H

L
L
L
H
L

H
L
L
H
L

L
H

H

H

H

H
H
H
H
H
H
H
H

H
H
H
L
H

L
L
L
H
H

H
H
H
H
H
H

H
H
H
H
H
H
H

H
H
H
H
L
L
H
H

H
H
H
H
L
L
H
H

H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H

H
L
L
H
H

L
H
L
H
H

H
H
L
H
H

L
L
H
H
H

H
L
H
H
H

L
H
H
H
H

H
H
H
H
H

H

0

u
T
p

Ill

u
T

s

2
L-

Low Voltage

3

4

5

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

H - High Voltage

l=AIRCHILC>SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-164

A DIVISION Of FAIRCHIL~ CAMERA .ANO INSTRUMENT CORPORATIONMuL9035
64-BIT READ/WRITE MEMORY CELLMEMORY MICROLOGIC® INTEGRATED CIRCLpTS
A FAIRCH.ILD COMPATIBLE CURRENT SINKING LOGIC PRODUCT.
'GENERAL DESCRIPTION - The 9035 is ·a high speed 64-bit read/write memory cell designed for use inhigh speed scratch pad memories. It is organized in a linear select 16 word by 4·bit array. The 9035 is madewith TTµL circuitry making it CCSL compatible.
.'
The 9035 is available in the hermetically sealed 36-pin ceramic dual in-line package and will operate over
the temperature range from -55°C to +125°C.
·
OPERATION- In addition to 16 address lines, 4 data outputs, and 4 data inputs, the 9035 has a..chip selectand a write enable. When the chip select is high, a word niay be addressed by a high on the address input.
Data is written into the addressed word only when the write enable is held low. While the address is present,
the outputs continuously show the contents of the word selected. Readout is non-destructive.
Up to four words may be addressed and read siinultaneously with the OR function of the words appearing
at the. output. Data can be written into two locations simultaneously.
Uncommitted collector outputs are provided on the 9035 to allow maximum flexibility in output connection.
In many applications such as word expansion, the outputs of many 9035's are wire-OR'd together. In otherappUcations the wire-OR is not used. In either .case an extern~I pullup resistor of value R must be used toprovide a high at the output when it is off. Any value of R within the range specified below may be used.

5.1
10 - F.O. (1.6)

S R S

2.1
N(O.l) + F.O. (0.06).

'

PliYSICAL DIMENSIONS
l-

675

1-

.043

-l

.. _ : _.,..

I _ .m _.040

1.··r~ .01s+-M- ~

0

200:_

.100 .

I

.050

5

.072

L

I
2
3
4

36
35
34
33

.110
.090

5
•

32
31

7

30

8
9
10
11
12
13
14
15
16
17
18

29

.019
.017

R is in Kn
N = number of·
outputs wire-OR'd
F.O. = number of
TTµL loads driven"1

28 1.868
27 1832
26
25
24
23
22
21
20
~-~, ___19__ _i'I

L.s2s~.515

The minimum value of R is limited by output current sinking ability. The maximum value of R is determinedby the output and input leakage current (leEx and IR) which must be supplied to hold the output at 2.4 V.
FEATURES:PIN CONFIGURATIONLOGIC DIAGRAM• 35 ns READ ACCESS TIME
• CHIP SELECT AND WRITE ENABLES• UNCOMMITTED COLLECTOR OUTPUTS fOR WIRE OR CAPABILITY• LINEAR SELECT• ON CHIP ADDRESS LINE BUFFERING• CCSL. COMPATIBLE

CHIP
SELECTWRITE
ENABLEDATA IN!!!

38

AfS It 12 13 14 WE
A2

A3 ' ''L1

ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Temperature (Ambient) Under Bias
Vee Pin Potential to Ground
Input Pin Voltage
Current, into Output Terminal
Output Voltage

I
I-65°Cto +150°C-55°C to +1~5°C-0.5 Vto +,8.0 V-:-l.5Vto +s.sv
lOOmA· -0.5Vto H.OV

I

I
I

WORD. AliDRESS:

Mpl 9035

I
I
I

I
I.
I
I

I
I
I
I

41& Dt 02 03 04,,.. '

1111

ORDER INFORMATION - Specify A6H* 9035XXX where XXX is 51X
forthe -55°C to +125°C temperature range or 59X for. the 0°C
to 75°C temperature range.

18

19

DATA OUT

l=AIRCHIL.C>
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011, TWX: 910-379·6435

3-165

SEMIC::::CJNCJUCTCJRA DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT c;ORPORA'ttON

FAIRCHiLD MEMORY MICROUlGIC® INTEGRATED CIRCUIT· Mµ,l9035· LOADING RULESHIGH LEVEL(TTµL Unit Loads)

LOW LEVEL(TTµL Unit Loads)

1.67
26.7
1.67
3.34
Open Collector

1

MdressChip SelectWrite Enable
Data Input
Data Output

1 (see note 1)

1
2
6.2

1 Low Level TTµL Unit Load= 60 µA
1 High Level TTµL Unit Load= -1.6 mA
ELECTRICAL C,HARACTERlsTICS

SYMBOLIFA
IFS<t,., = ~~s 0 c to 12s c, Vee;,;. 5.0 v ±10%)
0

TEST
_,:_
Addr9ss Input Lo~d Current
Chip Select Load Current....;1.6,;;..,3.2

leexWrite En~ble Load Ciureiit
Data ·lriput Load Current
Address Input Leakage Curi"enf
Chip Select Input Leakage C.urtent
Write Enable Leakage Current
Data. Input Leakage Current
Output Leakage ~urrent

VoL

Output "Low" Voltage

0.4

VIL

Input "Low" Voltage

0.8

VIH

Input "High" Voltage

lpo

Supply Current ·

IFw
IFo
IRA
IRS
IRw
'RO

LIMITS
+25°C
MIN.
MJ\X.
-1.6
-1.6

-55°C
MIN.
MAX.
-1.6
-1.6

LS

. -1.6, -3.2
100
1.6

100
200
200

'-l.6
-3.2
100

100
1.6
100
200
200

2.1

+125°C
MAX.
MIN.
-1.6
-1.6

·.

..

100
200
200

µA
mA
µA
µA
µA

Vee=:= 5.5 V,
VA 74.SV. Vcs -4.SV
Vee=:= 5.5 v,
Vee::::: 5.SV,
Vw=4.5V
V0 =4.5V·Vee= 5.SV,
Vee =;= 5.5 V,
Veex = 5.5 V
Enabie Input .Grounded

0.4

0.4

v

0.8

0.8

v

Vee =4.SV,
loL = 10 mA
One Wotd Selected
Vee= 5.0 V,. Mcm.itor Appropriate Output
To Guarantee...;;.
.. This Test Limit
Vee= 5.0 V, Monitor Appropriate Output
To Guarantee This Test Limit

~

2.0

.

·'

CONDITIONS
UNITS
mA
VA= 0.4 V
Vee= 5.SV,
mA
Ves =0.4V
Vee=.5,SV;.
See Note 1
mA
Vw = 0.4 V
Vee= 5.SV,
V0 = 0.4 V
mA
Vee= s..sv,

118

v

.2.0
118

118

mA

Vee =·5.5 V, One Word Selected~

NOTE 1: IFe increases by 1.6 ~A for each address enable 'held lit a logical l.
ELECTRICAL CHARACTERISTICS (TA = 0°C to 75°C, Yee= 5.0 V ±5%)..

0°C
SYMBOL
IFA
IFS

TEST
.,.
Aadress Input Load
Current,.
r:
Chip Select Load Current ·

MIN .

MAX.
-1.6
-1.6

LIMITS
+25°C
+75°C
MIN.
MAX.
MIN.
MAX.
-1.6 .
-1.6
-1.6

-1.6
-1.6
-3.2
100
1.6
100
200
200

'·:

leex

Write Enable Load Ci:lrrent
Data Input Load Current ·Address Input Leakage Curr.ent
Chip Select Leakage Current
Write Enable Leakage Current·Data Input Leakage Current
Output Leakage Current

-1.6
-3.2
100
1.6
100
200
200

-1.6
-3.2
100
1.6
100
200
200

VoL

Output "low" Voltage

0.45

0.45

VIL

Input "Low" Voltage

0.85

0.85

VIH

Input "High" Voltage

lpo

supply Current

IFw
IFo
IRA
IRE
IRw
IRo

2.0

2.0
124

.

NOTE .1: IFe increases by 1.6 inA for each address enable held at a logical 1.
3-166

.

-

UNITS
C~ND(TIONS
inA
Vee= 5.25V,
VA=Q.45V
mA
Vee= 5.2sv,
Yes =.0.45V
See Note 1mA
Vee= 5.25V,
Vw=0.45V
mA
V0 = 0.45V
Vee= 5.25V,µA
VA =4.5V
Vee= 5.25 V,.
mA
µA
µA
µA

Vee= 5.25V,
Vee= 5.25V,
Vee= 5.25V,
Vee= 5.25V,
Enable Input Grounded

0.45

v

0.85

v

Vee=4.75V,
IOL = lOmA
One Word Selected
Vee= 5.0 V, Monitor Appropriate Output
To Guarantee This Test Limit
Vee= 5,o V, Monitor Appropriate Output
To Guarantee This Test Limitv

2.0·· 124

·'

124

mA

Yes =4.5V
Vw=4.5V
V0 = 4.SV
Yeex = 5.25 V

Vee= 5.25 V, One Word Selected

.

I

.

'

.

. .

..

.

.

'

FAIRCHJLD .MEMORY. MICROLOGIC®:·INTEGRATED CIRCUIT. Mµ.L9035
TYPICAL ELECTRICAL CHARACTERISTICSADDRESS INPUT LOAD
CURRENT VERSUSINPUT VOLTAGE

ADDRESS INPUT LEAKAGE
CURRENT VERSUSINPUT VOLTAGE

ADDRESS INPUT THRESHOLDVOLTAGE VERSUSTEMPERATURE

!. ·

100

4.0

Vee· s.o~J.. .
ENABl£ INPUT AT GNl •.
..

Vee~.ov~.. g.~ 3.0

'·

~

9

~ 2.0

>.

r--t--t-iEii!zTA·25be0 IL:
0-1.2 L-'--'---''--'---'"'--'--'--1.--L--'
0
O.S
1.0
1,5
2.0
2.S

:r

. 2.0

-

~ 1.0

..

1--1-- TA• 125°e

Iii!

TA• ?S"e

4.0

. 0

6.0

8.0

INPUT VOLTAGE· VOi.TS

INPUT VOLTAGE - VOLTS

OUTPUT CURRENT·VERSUSOUTPUT SATURAJIONVOLTAGE.

ADDRESS TO OUTPUT DELAY
TIME VERSUS TEMPERATURE

~

~

~

0

~

25

~

B

m

TA -AMBIENTTEMIUATURE • •e

WRITE PULSE WIDTHVERSUS TEMPERATURE
30

Vcc·s.ov

Vee• S,OV

WmALOAD. I

eL•30pf'!--.,.

~

0

;;
0.4

l.i

0.8

0

1.6

~

OUTPUT SATURATION VOLTAGE - VOLTS

~

~

y

--

....,,,_

l

0

25

~

B

~

'--I--

0
4

m

~

~

0

~

25

B

~

m

TA ' AMBIENT TEMPERATURE - °C

TA - AMBIEtfl TEMPERATURE - •e

SWITCHING CHARACTERISTICS (TA= 25°C, Yee= 5.0 V)-

SYMBOL

TEST

MIN.

Address to Output Turn-On Delay
Address to Output Turn-Off Delay. Write Pulse Width Required to Write
Write Delay

ton
toff
twp
two

25

LIMIT (ns)
lYP.
16
18
15
30

MAX.
35
35
50

CONDITION
LOAD
c
10 mA
30pF
lOmA
30pF
lOmA.
30 pF
lOmA
30pF

NOTE
1
1
2.
2

.NOTE 1: To test t0 n and t01p a "Low" must be stored in the cell under test.
NOTE 2: One word is selected during the test.

5....

CHIP

SELECT---o1·
INPUT

2.GV
2.0V
·1.5¥-----1.5¥
1.0V
UJV

OUTPUT

uv-----uv

5.0V

470Q
OUTPUT_____ ..._ __1.0kQ
J.5¥--------.
OUTPUT --..----...,,....-W.1D
1\I~-·-------------1

10 mA TEST LOAD

3-167

FAIRCHILD MEMORY MICROLOGIC® INTEGRATED· CIRCUIT MµL9035
APPLICATIONSMEMORY EXPANSIONS: N16 WORDS BY 4-BITS-ti '.i''j''"'J_"j'.'H••"
1/1lllRIRIH11_ll""j_J'

JlHH

ttt:l451Jll111111131415

1/llHCllEIHtl-

IATllllPIT

J

1111114

It 11451711~~:.[ rr~ -r~~~..
r.JS1t1i~•1 'ft..

............

~
~

~

....

....

...111..I...•11"'-"-"l1ll....

............

...·~~.. lilzls ll~

tlfMHTA•=~t.
......

..

....... .......

'[Ill

1t ....fCILUl1111

In this application the 9035 memory cells are connected in parallel and two levels of decoding are performed. One of the cells is selected by the 9310
decoder and then a word is addressed by the 9316..
·

-

--

MEMORY STACK 160 WORDS OF 40·BITS

1i1 .i"j"_i""J' .

_in_j':i'_iJl "•n1".....:..~ Jlllillllillllil
J~!.,"•n1~1111"

11114111111'1111111411

111'L!_IJll....

_~1111-iTijl1ll t.lll ll.

~l..l[lll1111••

All. """"II
...,

l•I'

••..

... ~

......'"...

... •1'1'21J

U'.1_

~~
.. .........
~

...

.
.....~ ...

......
......

•11 ....

...

._.::"''"""'

llz.,

,___

tilT
Tl_,CILLll·le

1'

-- i
-:

-llf4'

There are 16 words by 40 bits for each stack. The outputs and inputs of all stacks are tied together. Stack 1 contains words 1-16, stack 2, 17-32,
and so on through 144-160 for the 10th stack~ The .stack address decoder tells which word group (1-16 or 17-32, etc.) is addressed while the word
location dec<ider addresses one of the 16 words of. the stack addressed. The entire memory has 40 data input lines, 40 data output lines, 8 addresslines, and a write enable line.

3-168

4501
CCSL MICROMATRIX™ QUARTER-CELL
A FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRIPTION - The 4501 consists of a single 4-input DTµL gate designed for use in breadboarding
the 4500 Micromatrix™. It corresponds to one of the 32 quarter-cells available in the 4500 Micromatrix
array. Logic flexibility is offered with pin options for interconnections of four independent elements. Theseelements are a) 4-diode cluster, b) non-inverting amplifier, c) common emitter inverting amplifier andd) load resistor.

PHYSICAL DIMENSIONSTYPICAL DUAL IN-LINE PACKAGEFEATURES• Offers 4500 Micromatrix breadboarding capability• Compatible with all CCSL devices

ABSOLUTE MAXIMUM RATINGS-.SVto +7V

Yee Pin Potential to Ground Pin
Input Voltage
Voltage Applied to Outputs
Storage Temperature
Temperature (ambient) under Bias-.s vto +s.s v-.5 V to +Yee Value-65°C to +150°C-55°C to +125°C.....

I LHlb1,.111te1u11111or11111•11Gf1111hol•ro••Ofl.3CIO''cenllf1 Ttieyare
putptMI' 1111"*9 ••tit 'positlH" ( n<» M1S11l'lnm1nt to f1eddlff 1111111toont. loanf·drllff•dlin1111iont1IMMtldtQUU,DUrfr1CliMfor1 conn111ionll .oa
l11Chdl-l1rluct.

ORDER INFORMATION
Specify A6A45015XX, where SXX is SlX for -55°C to +125°C temperature range or 59X for the 0°C to+75°C temperature range.
To order 4500 design kit, specify A6A4501KTXLOGIC DIAGRAM (PIN NUMBERS)CIRCUIT SCHEMATIC (PIN NUMBERS)
14

14

•2

:

:

~11

'cc= PIM 14

14

HD= PIM 3

l~~ ~

2

0-------C

~L

. f,

RESISTOR VALUES
R1 =2k0
R2 =1.75k0
R3 = 5k0
6k0a.=l=AIRCHIL.C
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-169

SEMICCJNCJUCTCJRA DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD 4500 MICROMATRIX™ • 4501 QUARTER-CELL
ELECTRICAL CHARACTERISTICS (TA= -55°C t~. +125°C, Vee ,.,;, 5.0V = 10%) Connected as NANO gate with pull-up resistor
MILITARY TEMPERATURE RANGE
LIMITS
SYMBOLCHARACTERISTIC

VoH

Output High Voltage

VOL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

IF

Input Load C11rrent-55°C
MIN. MAX.

MIN.

2.6

2.6

+25°C
TYP. MAX.
3.4+125°C
MIN. MAX.

UNITS

2.5

Volts

CONDITIONS
loH = -180µA

Vee= 4.5V
V 1 ~ on any input

0.4
2.1

0.22

0.4

1.9

0.4
1.7

1.3

0.7

1.0

Volts

Vee= 5.5V
Vee=4.5V

Volts

Guaranteed input highthreshold for all inputs

Volts

Guaranteed input low
threshold for all inputs

loL = 8mAlc)L = 6.2mA

1.6

1.18

1.6

1.6

mA

Vee=5.5V

VF::;0.4V

1.24

0.91

1.24

1.24

mA

Vee =4.5V

VF= 0.4V

10µA

VR = 4 v, GND on other inputs

IR

Input Leakage Current

2

PoPower Dissipation

15.5

mW

Vee = 5 V Inputs open, pull-up c11nnected

8.8

mW

Vee= 5 VAny input groundedc

ELECTRICAL CHARACTEIUSTICS (TA= 0°C to +75°C, Vee= 5.0 V = 5%) Connected as NANO gate with pull-up resisfor
INDUSTRIAL TEMPERATURE RANGE
LIMITSCHAAACTERISTICSYMBOL

CONDITIONS

0°C
MIN. MAX.

+25°C
TYP. MAX.

+75°C
MIN. MAX.

UNITS

MIN.

2.6

2.6

3.65

2.5

Volts

Vee·,;.. 4.75 V
V1L on any input

loH = -1~0 µA

Volts

Vee= 5.25V
Vee =4.75V

10 L = 9.6mA
loi.. =8.5mA

Volts

Guaranteed input highthreshold for all inputs

VoH

Output High Voltage

VOL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

1.1

IF

Input Load Current

1.6

1.09

1.41
IR

Input leakage Current

PoPower Dissipation

16.5

.. mW

9

mW

0.45
2.0

0.22

0.45

1.9

0.45
1.8

l.O

0.8

Volts ·

Guaranteed input low
threshold for all inputs

1.6

1.6

mA

Vee= 5.25V

VF= 0.45V

0.96 .1.41

1.41

mA

Vee= 4.75V

VF= 0.45V

5

10

µA

VR = 4 V, GND on other inputs
Vee= 5 V Inputs open, pull:up connected
Vee= 5 VAny input grounded

Loading and interconnections for 4501 are identical to 4500 Micromatrix array except for Note 3.
LOADING RULES

INTERCONNECTION RULES

Expanding theConnected as NANO gatewith pull-up resistor
Fan-in1 DTµL .unit load

Load

Fan-out.
51X
59X

~
.

If OR tie is utilized, 4501 fan-out
is restricted to 3 unit loads for 51X
temperature range operation (4 unit
loads for 59X temperature range.)(Note 3.)

•
•

~

DTL

TTL
,.

. Maximum fan-in - 20 inputs
corresponding to 5 diode clusters.
Fan,out- same as NAND gate.

Maximum of 4 OR ties allowed.

Note 3: Fan-out of 5 (6 for 59X temperature range) with OR tie used, can be maintained if temperature range of operation is limited to +15°C to+125°C (+15°C to +75°C for S9Xtemperature range.)
3-170

4510
CCSL MICROMATRIX™ DUAL 4-BIT COMPARATORA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRIPTION - The 4510 consists of two independent 4-bit comparators useful in many decision
making control applications, such as digital printers. Each comparator is capable of accepting two 4-bit
inputs and provides a high level output signal when they are identical. An output latch stores the compared
output when the strobe pin is high. Outputs may be "Wire ANDed" to expand comparison capability.
The circuit is produced with two layer metal interconnections using the Fairchild 4500 Bipolar Micromatrix'"'
Array•

24 PIN CERPAKOUTLINE. FEATURES• ASYNCHRONOUS AND SYNCHRONOUS OUTPUTS• OPTIONAL LATCH STORAGE OF OUTPUT• EXPANDABLE IN GROUPS OF 4 BITS
• TYPICAL POWER DISSIPATION OF 250 mW

.425
.378

• CCSL COMPATIBLE• ALL CERAMIC "HERMETIC" 24 PIN CERPAK.
• MEMBER OF 4500 MICROMATRIX™ ARRAY FAMILY• TWO LAYER METAL INTERCONNECTIONS

.

-1.J~
.00511 .

.1)935

Cl Cl

I.

.

CJ Cl Cl Cl CJ Cl CJ CJ

....
.551

.

_J

h

.

tr-.015.055

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias

-65°c to +150°C-55°C to +i25•c-0.5 Vto +7.0 V

Vee Pin Potential to Ground Pin
Voltage Applied to Output for High Output State
Output Current Into Low Output State· Input Voltage (O.C.)-0.5 V to +Vee Value
20 mA-0.5 Vto +5.5 V

ORDER INFORMATION - Specify A3M45105XX for flat package, where 5XX is 51X for -55°C to +l25°C
temperature range or 59X for the 0°C to +75°C temperature range.

13

23 22 21 20 19 18 17 16

11 10

9 8

ST

ST

COMPARATOR II

COMPARATOR I
Q

A=B

14

15

7 6

5 4

Q

A=B

2

3

PIN 24=Vcc

Fig. 1 -PIN t 2=GND

4510 DUAL 4·BIT COMPARATOR LOGIC DIAGRAM

F=AIRCl-llL.O
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011, TWX: 910-379-6435

3-171

A OIVISION OF FAIRCl11LD CAMERA ANO IN·STRUMENT CORPORATIONFAIRCHILD 4510 MICROMATRIX'M CIRCUIT

ELECTRICAL CHARACTERISTICS (TA = -55°C to +125°C, Yee= 5.0 v= 10%)MILITARY TEMPERATURE RANGE
LIMITS
SYMBOLCHARACTERISTIC-55°C
MIN. MAX.

MIN.

+25°C
TYP. MAX.

+125°C
MIN. MAX.

UNITS

2.6
2.6

2.6
2.6

2.5
2.5

0.4

3.4
3.4
0.22

0.4

0.4

0.4

0.22 . 0.4

0.4

Volts loH = -180.PAJV,L on any two inputs
Volts 10 H = -240 pA Yee = 4.5·V
Volts Yee = 5.5 V loL = 6.4 mA Y51 = GNDfor
Yee = 4.5 v IOL = 5.0 mA >A B output only
Volts Yee = 5.5 v IOL = 4.8 mA
Yee.= 4.5 V IOL = 3.7 mA >V51 =4V
Volts Guaranteed input highthreshold for all inputs
Volts Guaranteed input low
threshold for all inputs
mA Yee=5.5V
VF= 0.4 v
mA¥E_ = 0.4 v
Yrr=4.5V
mA
Yee= 5.5V { VF=0.4V

VIH

QOutput High Voltage
A = B Output High Voltage
Output Low Voltage
Qand A = B Output
Output Low Voltage
A = B OutputOnly
Input High Voltage

VIL

Input Low Voltage

1.3

2 IF

Input Load Current

3.2
2.43
2.4
1.86
4.0
3.1

VoH
Vol

2.1

1.5 IF=

2.5 IFIR
t23+ 15+
t23-15-A B Output Load Current
For "Wired AND"

1.9

1.7

2.36
1.82
1.77
1.37
2.95
2.28

Input Leakage Current
Comparison Switching Speed

1.0

0.7

3.2
2.48
2.4
1.86
4.0
3.1

3.2
2.48
2.4
1.86
4.0
3.1
20

20
50
50

AotgA=B

CONDITIONS

=

mA
mA

I
=

Yee =4.5V

Ysr=GND

pA

Yee = 5.5 V
VF = 0.4 V
Yee 4.5 V
V51 = 4 V
VR = 4 V, GND on other inputs

nsns

CL = 15 pf @ Pin 15

mA

~=5V

ELECTRICAL CHARACTERISTICS (TA= 0°C to +75°C, Yee= 5.0. v= 5%)
INDUSTRIAL TEMPERATURE RANGE
LIMITS
SYMBOLCHARACTERISTIC

0°C
MIN. MAX.

+25°C
MIN. TYP. MAX.

+75°C
MIN. MAX.

UNITS

YoH

2.6
2.6

2.6
2.6

2.5
2.5

VIH

QOutput High Voltage
A = B Output High Voltage
Output Low Voltage
Qand A = B Output
Output Low Voltage
A = B Output Only
Input High Voltage

VIL

Input Low Voltage

1.1

2 IF

Input Load Current

3.2
2.82
2.4
2.11
4.0
3.52

Volts loH = -180µA{ V1Lon any two inputs
Volts loH = -300 .PA Vee = 4.75 V
Volts Yee = 5.25 V loL = 8.0 mA V51 GNDfor
Vee = 4.75 V 10 L 6.25 mA >A = B output only
Volts Vee = 5.25 vIOL 6.4 mA
Vee = 4.75 V 10 L = 5.0 mA_ >Vs1 =4V\toIts Guaranteed input highthreshold for all inputs
Volts Guaranteed input low
threshold for all inputs
mA
VF= 0.45V
Yee= 5.25V
mA
VF= 0.45V
Vee=4.75V
mA
Vee = 5.25 V
VF = 0.4 V

VOL

1.5 IF
2.5 IFA = B Output Load Current
For "Wired AND"IR
t23+ 15+
t23-15-

Input Leakage Current
Comparison Switching Speed .
A0 toA=B

0.45

3.65
3.65
0.22

0.45

0.45

0.45

0.22

0.45

0.45

2.0

1.9

1.8

2.18
L92
1.65
1.44
2.64
2.4

1.0

0.8

3.2
2.82
2.4
2.11
4.0
3.52
20

3.2
2.82
2.4
2.11
4.0
3.52
20

50
50
3-172

CONDITIONS

=
=

l

l

mA

Vcc=4.75V

mA
mA

JI.A

Vee = 5.25 V
VF = 0.4 V
lvee = 4.75 V
V51 = 4 V
VR = 4 V, GND on other inputs·ns
ns

Vee= 5V
CL = 15.pf @ Pin 15

~=GND

=

FAIRCHILD 4510 MICROMATRIXn'CIRCUITFUNCTIONAL DESCRIPTIONASYNCHRONOUS - Fig. 2 ·shows the detailed logic representation of the comparator and latch ('h 4510). Whenever the 4-bit data word on lines A is identicalto the 4-bit data word on lines B the A =B output is high. If data word A is not equal to data word B the A= B output is low.
SYNCHRONOUS- The strobe (ST) and the latch output (Q) provide storage capability of the A = B output. This function is shown in Table 1. When ST is high,O., equals the A= B output. When ST is low; QN = QN-i·

DETAILED LOGIC DIAGRAMTABLE 1
TRANSITION TABLE
FOR LATCH OUTPUT (Q)
ST

ADI
BO

Al
81

QN

Low

QN-1

High

A=B

A2
82

A3
83
ST

Fig. 2SUGGESTED COMPARATOR EXPANSION METHODSCPAQA,......__,~'.:____.. OUTPUT [F.0.= 5]

L.4_8_n_s..r---, COMPARE A
TW012
BIT INPUTS

4 BiTS ---COMPARE B

The internal "wired OR" COMPARE ncide uses two pull-up
resistors for Improved rise time, and drives an internal
gate. Tw~ COMPARE outputs may be "wire OR'd" externally to provide a 12 bit ~mparator as shown in Figure 3. This may be expanded further by using additionalgates.

4 BITS - - - - COMPARE A
Fig. 34510 EQUIVALENT CIRCUITSOUTPUTSINPUTS

Vee

Vee

1.BBkoTYP

COMPARE R=3kuTVP
LATCH R=Sko TYP

Fig. 4

3-173

FAIRCHILD 4510 MICROMATRIX™ CIRCUITLOADING RULESINPUT LOADING RULES (FAN-IN)
DTµL UNIT LOADS

SIX

59X

Data Inputs
Strobe Inputs

2.0
2.Q

2.0
2.0

"Wired AND"
A= B Outputs(STGND)

1.5

1.5

2.5

2.5

A= B Outputs(ST High)

OUTPUT DRIVE CAPABILITY (FAN-OUT}
DTµL LOADS

TTµL LOADSST= GND

ST= HIGH

ST =GND

ST= HIGH

51X

59X

51X

59X

51X

59X

51X

59X

4.0
4.0
2.5
1.0

5.0
5.0
3.5
2.0

4.0
3.0
1.5
0

5.0
4.0
2.5
1.0

3.0
4.0
2.5
1.0

3.0
5.0
3.5
2.0

3.0
3.0
1.5
0

3.0
4.0
2.5
1.0

Q OUTPUT
A= B Outputs(1) "Wired AND" 2(1) "Wired AND" 3(1) "Wired AND" 2 and 3 means the number of compare outputs (A= B) that are connected together. The

result of this "Wired AND" connection, logically, is a high level true "AND" gate.

4-BIT COMPARATOR AND LAMP/RELAY DRIVER
One-half of a 4510 dual comparator drives a discrete driver so that when Ao= Bo, A1 = B1,
A2 = B,, and Ai = Bi the lamp will light <>r the .relay operate. This circuit might also be used
for a digital printer solenoid driver. The ST input is connected through a 2 kO resistor to Vee sothat Q and A= B may be paralleled for additional driver.base current.

Bo
A3
A2
Ai
Ao

l

Bi

l

.........
2ko

ST

B3

+5V

Ao Bo Ai Bi
Vee""

B2

A2 B2 A3 B3~5100~ 4510±5%r-+-

OUTPUT
VMAX= .+40V
IMAX= 500mA[0- 75°e1

Q

A=B

1 I

2N3569Fig. 5

3-174

4601
TTL MICROMATRIX™ ARRAY INTERNAL QUARTER-CELL
A FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCTGENERAL DESCRIPTION- The 4601 is a single 4-4 AND-OR-INVERT (AOI) TTµL gate to be used for breadboarding logic designs planned for the 4600 or 4700 MicromatrixrM arrays. The 4601 corresponds to one of
the quarter-cell gate elements that are intended for internal (on-chip) usage on the 4600 or 4700 arrays.
Standard family TTµL gates such as the 9002' through 9008 may be used to breadboard the quarter-cells
having external drive capability. The TTµL 9006 may be used to extend the 4601 at the OR tie points.

PHYSICAL DIMENSIONSTYPICAL DUAL IN-LINE PACKAGE
In Accordance WithJEDEC (T0-116) Outliner--·290-l

IF.310==il

FEATURES• "INTERNAL" TYPE LOGIC GATES FOR BREADBOARDING 4600 OR
4700 MICROMATRIX ARRAY DESIGNS• CCSL COMPATIBLE• OR EXTENDABLE WITH TTµL 9006
• FANOUT : 7 INTERNAL LOADS OR 4.5 EXTERNAL LOADS• "WIRED-AND" OUTPUT CAPABILITY• INPUT CLAMP DIODES FOR RINGING ATTENUATION

N0I£

A

1+- .350 MAX.--1.125 TYP.
...090·r=

ABSOLUTE MAXIMUM RATINGS (above which useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Vcc Pin Potential Referenced to Ground
Input Voltage Applied to Input
Voltage Applied to Output When Output is High
Input Current Into Inputs
Current Into Output When Output is Low
Lead Temperature (soldering, 60 seconds)-65°C to +150°C-55°Cto+125°C-0.5 Vto 7V..;.0.5 V to 5.5 V
Vee
5mA
30mA
300°C

"°""
l.1Aad11r1lnt.nd1dfori111ertloninllol1ro•1on.300"c1n11r1. Tl'Hly1r1
pvrJ1GHly1hlpp1dw1tlt'positiv1"! ..350lm111U1nm1ntlol1c1h11l1insertion.

2.Sa1rd·drlllln1dlm1111lon1sll1H1ld1qullyourpr1ct1cefor1conventiDQl.020
lnclldl1met1rlud.

ORDER INFORMATION - Specify A6M6015XX where 5XX is 51X for -55°C to +125°C temperature range
and Vee = 5 V ± 10%; and 59X for 0°C to 75°C temperature range and Vee= 5 V ±5%.
To order the 4600 Design Kit, specify A6M600KTX. For the 4700 Design Kit, specify A6M700KTX.

CIRCUIT SCHEMATIC

LOGIC DIAGRAM

Vee

PIN 14=Vcc
PIN 7=GND
PIN 1 =NOT USED

1011
12 0 - . j - - - - 1 - - - - - - - '13 O-+----+--+------'TYPICAL RESISTOR VALUES
R1 = lb=4 Kil
Ri = R4= 1.5 Kil

Logic Equation: Z = A1A2A3A4 + 81828384 • ••• •• More terms are provided with
OR extension

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011. TWX:. 910·379-6435

3-175

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONTTL MICROMATRIX™ •ARRAY INTERNAL QUART~R-CELL 4601
ELECTRICAL CHARACTERISTICS:
Temperature Range: 0°C to +75°C
Supply Voltage Range: 5 V :t:5%0°C
MIN. MAX.

LIMITS
25°C
MIN. lYP. MAX.

75°C
MIN. -MAX.

UNITS

2.3

2.3

2.3

v

CONDITIONSSYMBOLCHARACTERISTIC

VoH

Output High Voltage

Vol

VIH

Output Low Voltage
Internal Loading
Output Low Voltage
External CCSL Loading
Input High Voltage

VIL

Input Low Voltage

0.8

0.8

0.8

v

IF

Input Load Current
Internal VF Level
Input ~d Current
External CCSL VF Level
Input Leakage Current
Power Dissipation

-1.52
-1.33
-1.60
-1.41

-1.00 -1.52-0.87 -1.33-1.08 -1.60-0.91 -1.41
5.0
60
21
30
16
11

-1.52
-1.33
--1.60

mA
mA

--Ul

rilA-

60

µA
mW
mW

~c=5.25V
VF= 0.6V
Vee ~4.75V
Vc.e= 5.25V
VF= 0.45V
Yee=4:75Y
Vee= 5.25 v. VR = 4.5 v
Inputs Open
Vee=5.0V
Llnputs Grounded

125°C
MIN. MAX.

UNITSCONDITIONS

2.3

v

IR
Po

2.8

0.6

0.42

0.6

0.6

v

0.4

0.3

0.4

0.4

v

1.9

1.8

v

1.6

=

•

mA

Vee= 4.75 V, loH -600 µA
V1LOn Inputs
Vee= 5.25 v. IOL = 10.7 mA
Vee= 4.75 V, loL = 9.3 mA
Vee= 5.25 V, 10 L = 7.3 mA
Vee= 4.75 V, loL = 6.4 mA
Guaranteed Input ,High
Threshold For All Inputs
Guaranteed Input Low
Threshold For All Inputs

ELECTRICAL CHARACTERISTICS:
Temperature Range: -55°C to +125°C
Supply Voltage Range: 5 V :t: 10%
SYMBOLCHARACTERISTIC-55°C
MIN. MAX.

LIMITS
25°C
MIN. lYP. MAX.

VoH

Output High Voltage

2.3

2.3

VoL

VIH

Output Low Voltage
Internal Loading
Output Low Voltage
External CCSL Loading
Input High Voltage

VIL

Input Low Voltage

IF

Input Load Current
Internal VF Level
Input Load Current
External CCSL VF Level
Input Leakage Current
Power Dissipation

IR
Po

2.55

0.55

0.42

0.55

0.55

v

0.4

0.3

0.4

0.4

v

2.0

1.7

v

1.4

0.8

0.8

0.7

v

-1.52

-1.04 --1.52--0.8 --1.17--1.1 -1.60-0.85 -1~4
5.0
60
21
30
11
16

-1.52
--1.17-1.60--1.24
60

mA
mA
mA
mA
µA
mW
mW

-1.17
--1.60-1.24

Vee= 4.5 V, loH = -600 µA
V1LOn Inputs
Vee= 5.5 V, IOL = 10.7 mA
Vee= 4.5 V, loL = 8.2 mA
Vee= 5.5 V, 10 L = 7.3 mA
Vee= 4.5 v, IOL = 5.6 mA
Guaranteed Input High
Threshold For All Inputs
Guaranteed Input Low
Threshold For All Inputs~e=5.5V

Vee=-UiY~e=5.5V
VF= 0.4 V
Vee =4.5V
Vee= 5.5V, VR = 4.5V
Inputs Open
Vec=5.0V
Inputs Grounded

LOADING RULES
FAN-OUT (Sae table):

WIRED "AND":Tiie internal or "on-chip" fan-out of the 4601 Is specified
with reduced noise margins since on·chip noise is low. If the4601 is used specifically for off·chip driving, the maximum
fan-out must be reduced to maintain CCSL noise margins.

Since the 4601 internal gale$ have resistive pull-ups,
the AND tie of outputs is allowed. (Sae Fig. 4).
Breadboarding of the combined outputs is:
FAN·OUT=7- (3)(number of' outputs tied together -1)
For "on array" usage optional pull-up resistors allow
fan-out as summarized below:

FAN-OUT TABLE

EXTENSION:
Extension at the 4601 OR extender pins 9 and 6 may
be accomplished with TTµL 9006 dual 4 input extenderelements. A maximum of 10 extenders (5·9006's) may
be tied to the 4601 pins. (Sae Fig. 1)

3-176

VF= 0.55 v

LOADING
TYPE

FAN-OUTINTERNALTTµL
DTpL
LPDTµL

7
4.5
4.5
45

I

TTL MICROMATRIX™ ARRAY. INTERNAL QUARTER~CELL 4601
TYPICAL INPUT-OUTPUT CHARACTERISTICS
TRANSFER CHARACTERISTIC

5.o
4•5
4.o

~~1·c..

INPUT CHARACTERISTIC~~c·*"-+--+---t-UNLO~ ED-

f-s5"

~

25C

b.

. l~

~- 3.5 t--+-1-0't;-1'-H-~il>o....+"'-+-I

'C

E

-,2

~ 3.0
~

2.5 >--+--+--+--++-++-+-++-.--0-...,_...,

5 2.0 t--+-+-+-·ll'lpl-t~"t-t--Ht--fl--+--t~ 1.5 t--+-+-+-++-+:..-t+i1:,"'l-Ht--+t--+--t}

Vcc·5V-+-+--+--oMR INPU

1.0 l--+--+--+--+++-l-+-1--'Fl-'l'l-+-l·l.2.5 .__+--+--+--+-++-t+-t+I+-+<>-+--t·1.4

oL..LJLJ;.....J.....:t::l:::l:~~~

·1.6

0

32

.2

.4

.6

.8

I.It 1.2 1.4 1.6 1.8 2.0

OPEN

·I

INPUT VOLTAGE· VOLlSINPUT VOLTAGE • VOLlS

LOW LEVELOUTPUT CHARACTERISTICHIGH LEVELOUTPUT CHARACTERISTIC

vcc·5v

IR?·[v];~ •.. c

28 INPIJ1SOPEN

J·l-l

f
Vi

':! 24

INPUTS'1ROUN1lED

'..I,

IA"
~r..

A

D'v~5·cz

1--:55'75'C

i.-II~~ l::='f-1~
-8
. ·.8

·.4

""""

25'~

-",.

P"irc

~

tft.~
~ iis"c

rt

~

0

.z .4

.8

1.2

1.6

·5

2.0

OUTPUT LOW VOLTAGE iVoLI • VOLlS·l. OUTPUT HIGH VOLTAGE IVoHI ·VOLTS

TYPICAL APPLICATIONSEIGHT INPUT DIGITAL MULTIPLEXERUSING "OR" EXTENSIONGATED LATCH USING TWO 4601

lg

4601
---OUTPUT

Fig. 2

Fig. iThree bit address A B C selects an input (lo, I 1 ••• h) which :is presented at the output ininverted form. The 4601 is OR-expanded using 3-9006 extender elements.

3-177

I

TTL MICROMATRIXTM ARRAY INTERNAL QUARTER-CELL 4601
APPLICATIONS (continued)
INPUT "AND" EXPANSIONWIRED "AND"

A

B

c
D

0

OUTPUT Z

FG

Z (FANOUT = 4 INTERNAL)

J~

K

K
l

M

i

0--0

9007

M

N

'"''

p
Q

Z = ABCD + EFGJKLMNPQR

R

Standard TTJLL gates may be used for expansion of "AND" inputs.
•Provision for "AND" expansion is made on the micromatrix
array thru "selective bar" options.

Z= [ABCD+EFGH] • [JKLM+NPQRJ

Fig. 4

GENERAL PURPOSE MASTER-SLAVE FLIP-FLOP
USING FOUR 4601

Sor---------------- ,I

I
I
S1 ...._-+-+----!
S2--+--+--'

~

Q

~

~

Cp

C2--+-T--,
C3-.--++-..:::::;;;;;;;::;iL---------------~CD

For J.K operation, connect as shown in dotted lines. The outputs change on the high to low clock transition.

Fig. 5
3-178

4610
DUAL TWO-VARIABLE FUNCTION GENERATORTTL MICROMATRIX™ARRAY CIRCUITA FAIRCHILDCOMPATIBLECURRENTSINKING LOGIC PRODUCTGENERAL DESCRIPTION-The 4610 is a Dual Two-Variable Function Generator useful for non-arithmetic operations and variable decision making control in central processor units. Each circuit, controlled by a common
4-bit word, can select one of 16 possible Boolean functions performed on the two variable inputs. An
alternate input select configuration increases circuit flexibility and allows simultaneous generation of two
separate output functions from a single pair of variables. The circuit is produced with two layer metal inter·
connection using the Fairchild 4600 TTL Micromatrix1 t.t Array.

FLAT PACKAGE

020
015

FEATURES• EXPANDABLE IN GROUPS OF 2 BITS
• MEMBER OF 4600 MICROMATRIX ARRAY FAMILY• CCSL COMPATIBLE• ALL CERAMIC "HERMETIC" 16-PIN FLAT PACK• TWO LAYER METAL INTERCONNECTIONS• SIMULTANEOUS FUNCTIONS OF 1 PAIR OF VARIABLES

l_

!

L

.350 ___:
200

TOP VIEW

.0050

o~~
I
2s3
I
1----.247---l

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature-65°C to +150°C
Temperature (Case) Under Bias
-55°C to+125°C
Vcc Pin Potential to Ground Pin-0.5Vto +7V
Voltage Applied to Outputs (Output high)Gnd to +Vee value
Input Voltage (DC) (See Note 1)-0.5 V to +5.5 V
Input Current (DC) (See Note 1)-30 mA to +5 mA
Current into Output (Output low)
+30mA
Note 1-either Input Voltage limit or Input Current limit is sufficient to protect the inputs.
ORDER INFORMATION- Specify A3L46105XX for Flat package, where 51X is for -55°C to +125°C (Case)temperature range or 59X for the 0°C to +75°C (Case) temperature range.

FIG. 1 -4610 DUAL TWO·VARIABLE FUNCTION GENERATOR

12 13 11

14

2

StJAO AO BO BO

10
1
9

S1
S2

:

4

5

3

6

Al

ii

Bl

Bi

I
4610 DUAL FUNCTION
GENERATOR
I

S3

I

I

FD

I

Fl

7

15
Pin 16 =Vee
Pin 8 = Gnd

F=AIRCHIL.C
313 FAIRCHILD DRIVE, MOUNTA1N VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

3-179

SEMICONDUCTORA DIVISION Of FAIRCHILD CAMERA AND INSTRUMENT CORPORATtONFAIRCHILD 4610 MICROMATRIX™ ARRAY CIRCUIT
ELECTRICAL CHARACTERISTICS CTc = -55°C to +125°C, Vee= 5.0 V ± 10%)
LIMITS-55°C
MIN. MAX.

+25°C
MIN. TYP. MAX.

+125°C
MIN. MAX.

2.4

2.4

SYMBOLCHARACTERISTIC

VoH
VOL

Output High Voltage
Output Low Voltage

2.4

VIH

Input High Voltage

2.0

VIL

Input tow Voltage

0.8

0.9

.75

VoltS

Input Load Current

-1.60
-1.24

-1.1 -1.60-0.85 -1.24

-1.60
-1.24

mA
mA

Vcc=5.5V~ VF= 0.45V60µA

Vee= 5.5 V, VR = 4.5 V

mW

Vee= 5.0 V, Inputs openns

Vee= 5.0V

IF(See Loading
Rules
Note 1)

0.45

One Low Level Unit Load

0.45
1.7

0.45
1.4

IR
(See Loading
Rules
Note 2)

Input Leakage Current

5.0

60

Po

Power Dissipation

375

500

t,2

Avg. Propagation Delay

20

UNITS

CONDITIONS

Volts
Volts

Vee= 4.5 V, loH = -1.2 mA
Vee= 5.5 V, IOL = 12.8 mA
Vee= 4.5 V, IOL = 9.92 mA
Guaranteed input highthreshold for all inputs
Guaranteed input low
threshold for all inputs

Volts

Vcc=4.5V

J

CL = 20 pf, RL = 1 k:LECTRICAL CHARACTERISTICS (Tc= 0°C to +75°C, Vee= 5.0 V ± 5%)
LIMITS
0°C
MIN. MAX.

+25°C
MIN. TYP. MAX.

+75°C
MIN. MAX.

2.4'

2.4

2.4

SYMBOLCHARACTERISTIC

VoH
Vol

QOutput High Voltage
Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.85

0.85

0.85

Volts

IF
(See Loading
Rules
Note 1)

Input Load Current
One Low Level Unit Load

-1.60
-1.41

-1.08 -1.60-0.91 -1.41

-1.60
-1.41

mA
mA

Vee= 5.25V
Vee= 4.75V]

IR(See Loading
Rules
Note 2)

Input Leakage Current

60µA

Vee= 5.25 V, VR = 4.5 V

Po

Power Dissipation

375

mW

Vcc = 5.0 V, Inputs open

t12

Avg. Propagation Delay20

ns

Vee= 5.0V

0.45

0.45

0.45

UNITS

CONDITIONS.Volts, Volts, Vee = 4.75 V, loH = -1.2 mA
Vee= 5.25 V, IOL = 12.8 mA
Vee= 4.75 V, IOL = 11.3.mA
Guaranteed input highthreshold for all inputs
Guaranteed input low
threshold for all inputs

;

L9

1.8

Volts

1.6

60

3-180

500

J VF= 0.45V

CL = 20 pf, RL = 1 k

FAIRCHILD 4610 MICROMATRIXT~ ARRAY. CIRCUITFUNCTION GENERATOR DESCRIPTION

A detailed logic representation of the common control (S 0, S1, S2, S3) and one of· the two output function blocks is shown in Figure 2. The Truth
Table implemented by the function generator shows the functions of input variables A and B with the 16 possible combinations of S0, Sp S2' and S3(refer to Table 1). Note that any desired output function may be chosen active level high or active level low.

FUNCTION GENERATOR
TRUTH TABLE
WITH INPUT VARIABLES
ACTIVE HIGH

So

SI

S2

S3

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

DETAILED LOGIC DIAGRAM

FUNCTION(ACTIVE LOW)FUNCTION(ACTIVE HIGH)

A+ B
A+B
A+ B
A+ Er

A • "D'
A• B
A • B
A • B
A+B
A+B
A+ B
A+ lf
AE1' Ii
A$B
01

x • 13A • B
A • 'B'
A • B
A$B
A@B
1
0
A
B

A
8

A
'B'

A
B

TABLE 1

FIG. 2

Circuit flexibility can be increased by using S2' S3, A and B inputs as controls and S0, S1 as the input variables. In this mode of operation two
separate output functions are performed simultaneously on a single pair of variables S0 and S1. Refer to Table 2 below for complete truth table.
For example, if it is desired to obtain the active high functions S0 • S1 and S0 • S 1 simultaneously, S2' S3 are set low, A0 low, B0 high, A1 high, andB1 low. The function S0 • S1 will appear at the F0 output; lik~wise function S0 • S 1 will appear at the F1output.

FUNCTION GENERATOR TRUTH TABLE WITH INPUT VARIABLES ACTIVE HIGH
WHERE A, B, s2' S3 ARE USED AS CONTROL INPUTS AND So, SI ARE INPUTVARIABLES ON WHICH THE FUNCTIONS ARE PERFORMED.
S2

Si

A

B

FUNCTION(ACTIVE LOW)

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

So+ S1
So+ "S;
So+ S1
So+ S1

So
S"o
So
So

L
L
L
L

H
H
H
H

L
L
.. H
H

L
H
L
H

~ • SI

So+ S1
So+ S1
So+ S1'S'o + S1

H
H
H
H

L
L
L
L

L
L
H
H

L
H
L
H

H
H
H
H

H
H
H
H

L
L
'H
H

L
H
L
H

So • SISo ·~So • S1
So

e SI
°SI
SI

FUNCTION(ACTIVE HIGH)

So

• SI
• SI
• SI
• SI

e SI

So

SI
SI
SoE9S1

So EB
So

So
SoE9S1
So
SI
So

e SI
So
So e SI

5ie

TABLE 2
Note that by varying control lines S2, S3, A and B that any pair of S0 and S1 min terms, max terms, or symmetric function can be generated.

3•181

FAIRCHILD 4610 MICROMATRIXri.i ARRAY CIRCUITLOADING RULES

2. IR is defined as one unit high level load. The multipliers to determine
high level unit loads for individual inputs are:Input Loading R.ules (Fan-in)
1. IF is defined as one low level unit load. The multipliers to determine
low level unit loads for individual inputs are:

INPUT

MULTIPLIERSI

Ao, Al' S2, S3

8
6
5

5

B0, B_i, ~ B14e;;, Br

4

Ao, A1

3

Ao, A1

3

INPUT

MULTIPLIER

SI

8

So

So
S2' S3

6

Ao· A1, Bo, B1

FAN OUTLEVELOUTPUT

HIGH

LOW

~

20
20

8
8

F1

APPLICATIONSA Typical Processor Application is the transfer and logical operation control between two registers (A and B). The function generators are controlled
by a 4-bit operation code field, S0, S1, S2' and S3. The operation code repertoire includes the 16 operations listed below.
AND A and B to A
AND A and B to A
AND A and B to A
AND A and B to A

OR A and B to A
OR A and B to A
OR A and B to A
OR A and B to A

Exclusive OR A and B to A
Exclusive OR A and B to A
Reset A
Set A

Complement A
Transfer B to A
No Operation
Transfer B to A

FIG. 3

BO

B2

81

BN-1

B3

B REGISTERBN-------OP CODE [ISO-S3 INPUTS)---......,......,.____,.____,

'--I

'--I

1·
Fo

lo

4610

I

F1

FUNCTION LOGIC

F3

Fz
~

AO

A1

A2

3-182

A3

AN-1

AN

A REGISTERCOMPATIBLE CURRENT SINKING. LOGIC .COMING SOON
Type

Function

Type

Function

9315
9317
9318
9320
9324
9326

One-of-Ten Decoder/Driver
Seven Segment Display Decoder /Driver
Priority 8-lnput Encoder
Up/Down BCD Decade Synchronous Counter
Expandable 5-Bit Comparator
Up/Down Binary Hexidecimal Synchronous
Counter
8-Bit Multi-Access Memory

9322
9602
9614
9615
9642

Quad 2-lnput Digital Multiplexer
Dual Retriggerable/Non-retriggerable One-Shot
Dual Differential Line Driver
Dual Differential Line Receiver
Dual 3-lnput NAl'm High Current, High Voltage
DriverDual 4-lnput NANO High Current, High Voltage
Buffer
· · ·

9338

9644

9315-0ne-of-Ten Decoder/Driver designed to accept 8421 BCD inputs and directly drive Nixie* readouts.
Propagation delay: 250 nsec
Power dissipation: 100 mW
Packages: 3L (Flat) & 6B (DW)

9318-Priority 8-lnput Encoder with an input enable and group signal
and all zero outputs for expanding to larger input words.
Propagation delay: 25 nsec
Power dissipation: 150 mW
Packages: 3L (Flat) &6B (DIP)

Loading:
Inputs/Outputs
INTRA
CCSL
Ao, A,, A,, A,
1 UL
12/10
Outputs: 55V on any output, sufficient to drive gas filled readout
tubes directly.

Loading:
In puts/Outputs
All Inputs
All Outputs

INTRA
1 UL
10 UL

CCSL
12/10
240/100*Registered trademark of Burroughs Corp.
3

6

7

4
Yee= 5
Gnd = 12

_Q__o__o__Q__o__Q_Q__Q_

_Q_

o 1 2

a

3

4

5

6

1

9318
8 INPUT PRIORITY ENCODER
GS

9315 1/10 DRIVER DECODER
0123456789

16 15 89 13 14 11 10129317-Seven Segment Display Decoder/Driver with over-riding lamp
test input and capability for providing automatic blanking of insignificant zeroes in multi-digit displays.
Propagation delay: 200 nsec
Power dissipation: 260 mW
Package: 3L (Flat) & GB (DIP)
Loading:
In puts/Outputs
INTRA
CCSL
Ao, A,, A,, A,
1 UL
2/9.5
LT
4 UL
10/40
RBI
11z UL
2/4.8
RBO
1.5 UL
14/19
Outputs
12 UL• /120*Uncommitted Collector Outputs: 30V on any output.

9320-Up/Down BCD Decade Synchronous Counter with parallel presetting synchronous inputs, over-riding master reset, two line up/
down control, 2-input clock and carry look-ahead logic for multi·
decade operation.
Propagation delay: 20 nsec
Power dissipation: 360 mW. Packages: 3M (Flat) & 6N (DIP)
Loading:
Inputs/Outputs
CD, CE, MR
Po, P,, P,, P,
PE, CP, CU
Outputs

INTRA
1 UL
% UL
2 UL
6 UL

2

712635

23

22

CCSL
12/10
8/6.7
24/20
72/60
21

20

19

P1

P2

P3

Vee= 16
Gnd = 8
Ao A1 A2 A3 LT RBI

13
14
15
16
17
18
9

9317 7 SEGMENT DECODER

4 13 .12 .11 10 9 15 143-1839320 UP/DOWN DECADE COUNTER

TC

Qo

Q3

3

Q1

Q2

10

11

Vee= 24
Gnd = 12

COMPATIBLE CURRENT SINKING LOGIC COMING SOON
9326-Up/Down Binary Hexidecimal Synchronous Counter with parallel presetting synchronous inputs, over-riding master reset, two line
up/down control, 2-input clock and carry look-ahead logic for multidecade operation.
Propagation delay: 20 nsec
Power dissipation: 360 mW
Packages: 3M (Flat) & 6N (DIP)
Loading:
In puts/Outputs
CD, CE, MR
Po, P,, P,, P,
PE, CP, CU
Outputs

13
14
15
16
17
18

Di

Ao A1 A2

W1

Bo B1 B2

OE

9338
MAM

W2

QA

CP

Qs

CCSL
12/10
8/6.7
24/20
72/60

INTRA
1 UL
2h UL
2 UL
6 UL
23

Wo

22

21

20

19

Po

P1

P2

P3

9326 UP/DOWN BINARY COUNTER
Ql

Qo

9322-Quad 2-lnput Digital Multiplexer with input enabling and single
line control input.
Propagation delay: 25 nsec
Power dissipation: 150 mW
Packages: 3L (Flat) & 6B (DIP)

TC

Q2

Q3

8

10

11

Loading:
Inputs/Outputs
All Inputs
All Outputs

CCSL
12/10
240/100

INTRA
1 UL
10 UL

Vcc=24
Gnd = 12

Quad 2 Input Multiplexer=

9324-Expandable 5-Bit Comparator with A B, A> B, A< B outputs. An enable input is also provided for the A and B outputs.
Propagation delay: 15 nsec
Power dissipation: 120 mW
Packages: 3L (Flat) & 6B (DIP)
Loading:
Inputs/Outputs
All A & B Inputs
ABE
AB & C Outputs

INTRA
1 UL
2 UL
10 UL

13 12 11 10

ABE

9

3

CCSL
12/10
24/20
240/100
4

5

6

79602-Dual Retriggerable/Non-retriggerable One-Shot, each with two
DC level-sensitive inputs, one is active-level High and one is activelevel Low. They also have over-riding reset inputs.
Propagation delay: 25 nsec
Power dissipation: 87 mW /function
Packages: 3L (Flat) & 6B (DIP)

9324 5 BIT COMPARATOR
AB

15

14

Vee= 16
Gnd = 8

Loading:
Inputs/Outputs
Inputs
Outputs

INTRA
1 UL
6 UL

CCSL
12/10
144/63

Rx
9338-8-Bit Multi-Access Memory (MAM) organized like a masterslave flip-flop that has eight masters and two slaves. The data input(D,) is connected to the input of the master selected by the write
select (Wx) inputs synchronously with the clock pulse (C,). The two
independent outputs are addressed by the read select (Ax & Bx)
inputs. The two outputs (QA & Q,) can be read independent of theclock pulse when the output enable (0,) is low.
Propagation read delay: 35 nsec
Propagation write delay: 35 nsec
Power dissipation: 370 mW
Packages: 3L (Flat) & 6B (DIP)
Loading:
Inputs/Outputs
All Inputs
QA & QB

cx
15

Q
9602
0/S

Q

12

9602

11

O/S

Q

Q

CD

INTRA
1 UL
6 UL

14

CD

vcc= 16

CCSL
12/10

Gnd = 8
13

3-184

10

COMPATIBLE CURRENT SINKING LOGIC COMING SOON
9614-Dual Differential. Line Driver with short-circuit and diod.e protected outputs, input diode clamps and operates from a single 5V
supply. It is designed to be used wlth the 9615 line Receiver.
Propagation delay: 10 nsec
Power dissipation: 110 mW
Packages: 3L (Flat) & 68 (DIP)
Loading:
Inputs/Outputs
INTRA
CCSL
All Inputs
1 UL
2/10
Differential Outputs
loH =40 mA(VoH = 2.5 V, VoL = 0.5 V)
loL = 40 mA
Supply Voltage: Vee = 5 V

9642-Dual 3-lnput NAND High,Current, High-Voltage Driver withexpander inputs, designed to drive core, thin film, and plated-wire
memories. Either gate can be used to source or. sink up to 5.00 mA.
Propagation delay: 35 nsec
Power dissipation: 470 mW/driver gate
Packages: 3L (Flat) & 68 (DIP)
Loading:
Inputs/Outputs
INTRA
Gate Inputs
1 UL
Expander Inputs
1 UL
Outputs High
500 mA
Outputs Low
500 mA•A function of input diodes used.

CCSL
2/9.4
*/9.4

~---4

Vee= Pin 16
Gnd =Pin 8

Gnd

Vee

. 14

NC

TAP

13

NC

12

------12910
11

6 - - t - - -....

---1--- 89615-Dual Differential Line Receiver can sense 80 mV differential
signals on ± 15 volt common mode. The 9615 is designed to operatewith the 9614 Line Driver at speeds up to 20 MHz.
Propagation delay: 20 nsec
Power dissipation: 100 mW
Packages: 3L (Flat) & 68 (DIP)
Loading:
Inputs/Outputs
Differential Inputs
Gate Inputs
OutputSupply Voltage: Vee = 5 V

INTRA
80 mV
1 UL
6 UL

CCSL
threshold
2/10
100/62.5

Gnd

Yee

14
13

12
Terminating Resistor

4

3 Response Control

Differential 5
Input

2 Active Pullup

10

Vee= Pin 16
Gnd =Pin 8

Yoo

14

11

15

12

3-185

8

COMPATIBLE CURRENT SINKING LOGIC COMING SOON
9644-Dual 4-lnput NAND High-Current, High-Voltage Buffer withexpander inputs and a common enable input. It is to sink up to
500 mA and hold-off up to 30 volts.
Propagation delay: 35 nsec
Power dissipation: 450 mW/buffer gate
Packages: 3L (Flat) & 68 (DIP)
Loading:
Inputs/Outputs
Common Gate Input
Gate Inputs
Expander Inputs
Outputs

INTRA
2 UL
1 UL
1 UL
312 UL

4--t---,

s------1

CCSL
4/19
2/9.4
*/9.4
Open collector,
sinks 500 mA

11---~

12--1----f
13--1---'*A function of input diodes used.

14---~

10-----

3-186

Gnd =Pin 16
Gnd =Pin 8
Vcc=Pin 7

Special
Integrated
Circuits

SPECIAL CIRCUITS NUMERICAL INDEX
Type

Page No.

SPECIAL PRODUCTS
9620
9621
9622
9624
9625

4-1
4-7
4-13
4-17
4-17

CµL
9958
9959
9960
9989

4-23
4-27
4-31
4.34

CTµL
9030
9952
9953
9954

4-64
4-38
4-42
4-42

Type

Page No.

Type

Page No.

9955
9956
9957
9964
9965
9966
9967
9968
9971
9972

4-42
4-48
4-52
4-42
4-42
4-42
4-52
4-62
4-42
4-42

9923
9926
9927
9997

4-66
4-66
4-66
4-88

RTµL
9900
9903
9904
9905
9907
9914
9915

4-66
4-66
4-66
4-66
4-66
4-66
4-66

LPRTµL
9908
9909
9910
9911
9912
9913
9921

4-66, 4-90
4-66, 4-90
4-66, 4-90
4-66,4-90
4-66, 4-90
4-66, 4-90
4-66, 4-90

SPECIAL CIRCUITS CROSS REFERENCE
NOTE: The Special Circuits Cross Reference
included in CCSL Cross Reference, page 3-ii.

4-i

9620
DUAL DIFFERENTIAL LINE RECEIVER
FAIRCHILD INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 9620 is a dual differential line receiver designed to receive differential digital
data from transmission lines and operate over the military and industrial temperature ranges. It can receive±500 mV of differential data in the presence of high level (±15 V) common mode voltages and deliver
undisturbed CCSL logic to the output. In addition to line reception the 9620 can perform many functions,a few of which are presented in the applications section. It can interface with nearly all input logic levels
including CML, CTµL, HLLDTµL, RT µL and CCSL. HLLDTµL logic can be provided by tieing the output to
Vcc 2 (+12 V) through a resistor. The outputs can also be wire OR'ed. The 9620 offers the advantages oflogic compatible voltages (+5 V, +12 V), CCSL output characteristics, and a flexible input array with a highcommon mode range. The direct inputs are provided in addition to the attenuated inputs (normally used)
to allow the input attenuation and response time to be changed by use of external components.

TYPICAL DUAL IN·LINE PACKAGE
In Accordance WithJEDEC (T0·116) Outline

FEATURES:• CCSl COMPATIBLE OUTPUT• HIGH COMMON MODE VOLTAGE RANGE• WIRED-OR CAPABILITY• DIRECT INPUTS (AD• BD)• FULL MILITARY TEMPERATURE RANGE• LOGIC COMPATIBLE SUPPLY VOLTAGESNOTESo1. Leads are intended for insertion in hole rows on
300" centers. They are purposely shipped with"positive" j.375) misalignment to facilitate insertion.
2. Board·dritling dimensions should equal yourpractice for a conventtonal .020 hnch diameter lead.

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Vcc 1 Pin Potential to Ground Pin
Input Voltage Referred to Ground (Attenuator Inputs)
Voltage Applied to Outputs for High Output State
Vcc 2 Pin Potential to Ground Pin

I-65°C to +150°C-55°C to +125°C-0.5Vto+7.0V±20V-0.5 V to + 13.2 V
Vcc 1 to+15V

14-PIN FLAT PACKAGE--.e;;;;:==. . . ,.......,.--1
I

.065
.050

LOGIC DIAGRAM
OPEN

ORDER INFORMATION
Specify U6A9620XXX for 14 pin Dual In-Line package or U319620XXX for 14 pin Flat Package where XXX is
SIX for the -55°C to +125°C temperature range, or 59X for the 0°C to +75°C temperature range.

OUT A
Ao+
A+
A-

AoGND

FA.IRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910·379-6435

4-1

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD INTEGRATED CIRCUIT • 9620''f

ELECTRICAL ·CHARACTERISTICS (Temperature Range -55°C to +125°C, Vcci = 5.0 V ± 10%, Vccz = 12.0 V ± 10%)
LIMITS
SYMBOLCHARACTERISTIC-55°C
MIN. MAX.

MIN.

+25°C
TYP. MAX.

VOL

Output Low Voltage

VoH

Output High Voltage

le EX
lsc
IF
tVTH
tvcM

Output Leakage Current
Output Shorted Current
Input Forward Current
Differential Input
Threshold Voltage
Common Mode Voltage

lvcc1

5 V Supply Current

13

8.2

lvcc2

12 V Supply Current

8.0

tpd+
tpd-

Turn·off Time
Turn·on Time

0.40

0.25

2.8
50

-15

UNITS

0.45

Volts

Vcci =4.5V
IOL = 15.0 mA

Volts

Vcci =4.5V
loH = -0.2mA
VcEx = 13.2V
Vcci = 5.0V
Vcci = 5.0V
Vcci = 5.0V

0.40

3.3

3.0

+125°C
MIN. MAX.

2.9
200

µA
mA

-3.0
500

mA

15

Volts

13

13

mA

5.6

8.0

8.0

mA

35
20

50
50

-3.1
500

100
-1.4 -2.15 -3.1
-2.1 -3.0
120 50015-15 ±17.5

15-15

CONDITIONS & COMMENTS

mV

ns
ns

Vcci = 5.0V
"VotFF = 2.0 V
Vcci = 5.5V
Vccz = 13.2V
Vcci = 5.5V
Vccz = 13.2V
RL = 3.9 kn
RL = 390ntAll input voltages are referred to the attenuated inputs (A+, A-, B+, e-)*V01 FF is a differential input voltage referred from A+ to A- and from B+ to B-.

Fig. 1 - SCHEMATIC DIAGRAM

OUT A

0.4k

0.4k

8.2k

Ao+
A -

D

2k

2k

A+

-::-

A-

3000

3000

STANDARD USAGE
DRIVER SYSTEM·tOGICRECEIVER SYSTEM

9620

LINE DRIVER

4-2

LOGIC

-::-

Vccz = 10.8V*VolFF = 0.5 V
Vccz = 10.8V. *Vo1FF = ..,.Q,5 V
Vccz = 12.0V
Vccz = 12.0V
Vccz = 12.0V

Vccz = 12.0V+Input= 5.5 V-Input= OV+Input= 5.5 V-Input= OV
CL= 30 pf
CL= 30 pf

FAIRCHILD INTEGRATED CIRCUIT • 9620
ELECTRICAL CHARACTERISTICS (Temperature Range 0°C to +75°C, Vcci = 5.0 V ±5%, Vcc 2 = 12.0 V ±5%)
LIMITS
SYMBOLCHARACTERISTIC

VOL

Output Low Voltage

VoH

Output High Voltage

le Ex
lsc
IF

o•c
MIN. MAX.
0.45
.2.8

Output Leakage Current

0.25

0.45

0.50

Volts

Vcci =4.75V
IOL = 15.0 mA

Vcci = 11.4 V*VDIFF = 0.5 V

Volts

Vcci =4.7SV
10 H = -0.2mA

Vcci = 12.6 V*VDIFF = -0.5 VµA

VcEX = s.25 v
Vcci =.5.0V
Vcci = 5.0V

Vcci = 12.0V
Vcci = 12.0V

Vcci = 4.75V

Vcci = 12.6 V .

3.0
so

2.9

3.3

100
-1.4 -2.15 -3.1

200

-2.1 -3.0
120 500

-3.0
500

mA
mV

12

Volts

tVcM

Output Shorted Current
Input Forward Current
Differential Input
Threshold Voltage
Common Mode Voltage

lvcc1

5 V Supply Current

13.5

8.2

13.5

13.5

mA

lvcc2

12 V Supply Current

8.5

5.6

8.5

8.5

mA

tpd+
tpd_

Turn-off Time
Turn-on Time

35
20

75
75

tyTH

-3.1
500
-12

12

CONDITIONS & COMMENTS

MAX.

+1s•c
MIN. MAX.

UNITS

TYP.

+25°C
MIN.

-12 ±17.5

12

mA

-12

ns
ns

Vcci = S.OV
*VDIFF = 2.0 V
Vcci = 5.25 V
Vcci = 12.6V
Vcci = S.2SV
Vcci = 12.6V
RL = 3.9 kn

CL= 30 pf

RL =390!1

CL= 30 pf

Vcci = 12.0 V+Input= 5.25 V-Input= 0 V+Input= 5.25 V-Input= 0 V

tAll input voltages are referred to the attenuated inputs (A+, A-, s+, s-)*V01 FF is a differential input voltage referred from A+ to A- and from B+ to 8-.

WAVEFORMS
Fig. 2 -SWITCHING TIME TEST CIRCUIT-----+--¥=
50%

Vcc1 =5.0V
Vcc2= 12V

ov

0.5V
50%

0.5V~
DY

You1

3
~._.v--:---j,,.,~

i=---1

1.5V

lPhotograph of a 9620 switchingdifferential data in the presenceof high common mode noise.

A··{
0--HtA{·-{
VERT= 2.0 V/div•. HORIZ = 50 ns/div.

4-3

FAIRCHILD INTEGRATED CIRCUIT • 9620
TYPICAL ELECTRICAL CHARACTERISTICS
TYPICAL OUTPUT HIGH VOLTAGE
VERSUSOUTPUT HIGH CURRENTTYPICAL OUTPUT LOW VOLTAGE
VERSUSOUTPUT LOW CURRENTLOGIC LEVELS VERSUSAMBIENT TEMPERATURE~ 200 l---!---l--+--+-hijl4-~--I

ill~~ 2. 0 1---!--+--+--+--+--+__,1--+--+--lg~ 1.5 l--+-+--+--+--+--+--+-,.,.v-+-....J...-1~ 150 t---+---1-+-,...+-+---+---+--i

;

5

~-~r
~~l.O L.T-YP.J..IC-Al.J.Vo_L...J@-lo-L·L.15-mA..._.J..-..+Vccy. 10l.8V ~~1001-'t-'1---:;ijlll~-+--+-+--+---+--i

0. 5 L.lZJwolsT cAsc vbL@ 10 L• 15mAl

7T "To'--'----'--.J......-'--'--_,_-'----'
0

5.0

15

lO

10
TA· AMBIENT lEMPERAlURE -"C

loH - OUlPUT HIGH CURRENT - mA'oL - OU1PU1 LOW CURRENT -mA

TYPICAL Vo,, VERSUS VolFF
TRANSFER CHARACTERISTIC

TYPICAL Vo,1 VERSUS Vo1FF
TRANSFER CHARACTERISTIC
7.0
TA·25°CI]

1 1I
re 7f.....

AllENUATOR INPUlS

6.0

I

Vcc1. 5.:!}v

~ 5.0

~ 4.0
§

g

)'cc2:

52.0 I -l-jcc2; 12.y

120

80

«l

160

-500

200

-300

~ 3.0

TA• O"C~~!"""rli 7 7

~ 71[

TA• 25.]

]

~

5 2.0

TA·W~-...

0

g

50

0

i

~

~ 4.0 l--+-+--+--+--1--1---1-~~gv/N • 51.ov-+-:~ l.O 1---!--+--+--+--+-VtN. 2,.ov~ j.;:1--gv\N. ol5v,~u.......

II'

1.0 l--!--+--+--+--+-::r-+--1)1--l-l-.ai--

lLri

~

~

z

>-

-12

-18

N_"Lo.5110 JOV

o.........,_""""............i....1...~A..1
150

100

-25

250

200

-15

-5.0

0

5.0

15

25

VcM - INPUT COMMON MODE VOLTAGE - VOLTS

POWER DISSIPATION VERSUSAMBIENT TEMPERATURE

SWITCHING TIME VERSUSAMBIENT TEMPERATURElw~~~~~~~~-~~!Z

Vcc1. 5.ov~jVcc 2 • 12v
SEE FIG. 2

,

<!>/"
~1"-1-~'V,.-. t""'.... . . .

:l

60

IL

-;- -6.0

t-,

u

.,f'

INPUT VOLTAGE VERSUSINPUT CURRENT~' 6.0
~
g 0

500

300

!5

VOIFF - DIFFERENTIAL INPu·, VOLTAGE - mv

12V

100

g 5.0 l--+-+--+--+--l--+--1-1---1--1....

TA• l25°C

> l.O

-

~TENJATOR1 1NPJisl lg

Vcc 1 • 5.ov __,:.. • 25°c

0

TYPICAL Vo,, VERSUS Ve ..
CHARACTERISTICSTA• -55°C

pCl •t-- flTYPICAL Vo,1 VERSUS VolFF
TRANSFER CHARACTERISTIC

j!? 4.0

12

F=..I I)Vol FF - DIFFERENTIAL INPUT VOLlAGE- mv

Vee! • 5.0V
Vcc2·12v

18

-100

·~

VOIFF- DIFFERENltAL INPUT VOLTAGE- mv

5.00

tril3. 2V~

1.0 I -

0

rllvcc 1

10.8(·-<l>

1

>o

h

I

7

v r7

g
~ 3.0
> 1.0 1--

Vee ·.;.sv:?

......... JST CASE tPtJ- ..................

_......................·,,~~

IL

. ~

~ «l

J..LV

o

~

~ 150 E=f:f:±:t:f'.3=l~l::D
i1oo~T>itii::dt;"t::~~-.+....Jb:::J.-..J--.l

.....

1-

~~~

;,, 1 Q O L - - -1w1c~~

20~::zr A-15o'--l-_,__._-'-_....__,,__._,__...__.
-l.O

J.O

11t,i- INPUT CURRENT- mA

9.0

15

~60

-10

0

20

60

100

TA - AMBIENTTEMPERATURE-°C

4-4

l«l

-10

0

20

60

100

TA - AMBIENTTEMPERATURE-°Cl«l

FAIRCHILD INTEGRATED CIRCUIT • 9620
APPLICATIONSDIGITAL COMPARATOR WITH
DIODE REFERENCE AND
HIGH LEVEL LOGIC OUTDIGITAL DIFFERENTIAL LINERECEIVER WITH INPUTSROLLED OFF

EXPANDED INTERFACE

12.0V

Yth 2VOIOOE
0-=-t-INVERTING

R, ~ 75012

Vref =Resistor, Diodes, or Supply

DIGITAL DIFFERENTIAL AMPLIFIERDIGITAL COMPARATOR(Line Receiver)

SJ>-ol
L

l

~~J
1

I

INVERTING WITH TERMINATIONNON·INVERTING WITH TERMINATIONDIGITAL COMPARATOR WITHRESISTIVE DIVIDER
AS REFERENCE

INTERFACING METHODSl
INVERTINGI
NON-INVERTING

4-5

FAIRCHILD INTEGRATED CIRCUIT • 9620

MULTIVIBRATOR

A.C. COUPLED DIGITAL AMPLIFIERWITH HYSTERESISTYPICALLY
R1 = 1.6 kn, R, = 2.7 kn, T = 1.3 R,C

TYPICALLY
R, = 1.6 kn, R, = 2.1 kn

MONOSTABLE MULTIVIBRATORNEGATIVE EDGE TRIGGERINGDOUBLE-ENDED COMPARATOR

~~
~2
C1

OUT

Rl

":"

":"

TYPICALLY

c, = 0.1 µf, R, = 1.2 kn, R2 = 1.0 kn
Pulse Width = 50 ns + 3.15 x 10' C2CRYSTAL CONTROLLED
MULTIVIBRATORHIGH INPUT IMPEDANCELINE RECEIVER(Positive Signals Only)
12¥

TYPICALLY
R
2
R, = 1.6 kn, R2 = 2.1 kn, c = 1000

4-6

9621
DUAL-LINE DRIVER
FAIRCHILD INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 9621 was designed to drive transmission lines in either a differential or asingle-ended mode. Output clamp diodes and back-matching resistors for 130fl twisted pair are provided. The
output has the capability of driving high capacitance loads. It can typically switch >200 mA during transients.

TYPICAL DUAL IN-LINE PACKAGE
Similar to
JEDEC (T0-116) Outline

FEATURES• CCSL COMPATIBILITY• TRANSMISSION LINE BACK-MATCHING• OUTPUT CLAMP DIODES• HIGH CAPACITANCE DRIVE• HIGH OUTPUT VOLTAGE• MILITARY TEMPERATURE .RANGE

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Vcci Pin Potential to Ground Pin
Input Voltage
Voltage Applied to Outputs
Vcc 2 Pin Potential to Ground Pin·

-65°C to + 150°C-55°Cto +125°C+3.8 Vto +8 V-.5Vto+l5V-2Vto +Vcci + 1 V
Vcci to +15 V

NOTES'
1. Leads are intended for insertion in hole rows on.300" centers. They are purpOsely shipped with"pos111ve·· (.375) m1sahgnment to tac1l1tfte 1nsert1on.
2 Board-llr1111ns dimensions should equal yourpractice tor a conve~tional 020 hnch diameter lead . .

ORDER INFORMATION

14 PIN FLAT PACKAGE

Specify U6A9621XXX for 14 pin Dual In-Line Package or U319621XXX for 14 pin Flat Package where XXX is
SIX for the -55°C to +125°C temperature range, or 59X for the 0°C to +75°C temperature range.

1.
SCHEMATIC DIAGRAM

1

3E9:r

.~,2TAX

~ 7 -.370 ---.260MAX.- .370- S
.250

.250

.065

~~~==::=.;;;;i;;;;;;;;:;;;;;;;;-(.050

Vee,

I

LOGIC DIAGRAM

1050

Vcc1=14
Vcc2=sGND=7

l=A.IRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

4-7

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD INTEGRATED CIRCUIT 9621
ELECTRICAL CHARACTERISTICSMILITARY TEMPERATURE RANGE -55°C to +125°C (UXX962151X)
LIMITS
SYMBOLNOTES CHARACTERISTICS

VOL

Output Low Voltage

VoH

Output High Voltage-55°C
MIN. MAX.

+25°C
MIN.

350
4.0

4.0

TYP.

MAX.

+125°C
MIN. MAX.

200

350

400

4.3

4.0

UNITS

CONDITIONS & COMMENTS

mV

IOL

= 20 mA

Vcci = 4.5V
Vcci = 10.8 V

v

10 H = -20 mA

Vcci = 4.5V
Vcci = 10.8 V

lsc

1Output "Short Circuit"
Current-180 -300

mA

Your= OV

Vcci = 4.5V
Vcci = 10.8V

IOL

1

Output Low Current

150

mA

Vout = 5.0V

Vcci = 4.5V
Vcci = 10.8 V

200

IF

Input Forward Current

1.8

1.15

1.8

1.8

mA

VF= ovVcci = 5.5V
Vcci = 13.2 V

IRlnputReverse Current

2.0

<l.O

2.0

5.0

µA

VR=5.5V

Vcci = 5.5V
Vcci = 13.2V

380

500

v

10 L = 2.8mA

Vcci = 5.0V
Vcci = 12.0V

4.2v

loH = -2.3 mA

Vcci = 5.0V
Vcc 2 = 12.0V

VoLR

2

Resistive Output· Low Voltage

VOHR

2

Resistive Output
High Voltage

VOLc

3

Clamped Output
Low Voltage-1.0 -2.0v

IOL = -20 mA

Vcci = 5.0V
Vcci = 12.0 V

VoHc

3

Clamped Output
High Voltage

6.0

7.0

v

10 H = 20 mA

Vcci = 5.0V
Vcci = 12.0V

7.0

7.3 ..

mA

InputsOpen

Vcci = 5.5V
Vcci = 13.2V

9.8

CL= 5000 pf

Vcci = 5.0V
Vcci = 12.0V

CL= 30 pf

Vcci = 5.0V
Vcci = 12.0V

lcc1

4.0

+5 V Supply Current

7.0

4.7

+ 12 V Supply Current

9.8

6.5

9.8

tpd+

4

Turn-Off Time

30

'150

tpd-

4

Turn-On Time

80

150

ns

tpd+

Turn-Off Time

13

25

ns

tpd-

Turn-On Time

9

25

ns

VIL

Input Low Voltage

1.5

1.0

VIH

Input High Voltage

lcc2

1.3
2.2

2.0

1.7

mA
ns

0.7
1.8

v

Vcci = 5.5V
Vcci = 10.8Vv

Vcci =4.5V
Vcci = 13.2V

NOTES:(1) Pulse tests to insure transient current handling (test time= 3 seconds maximum - one side only).
(2) Test output resistance including 1050 output resistor.
(3) Tests output clamp diodes.
(4) With both sides loaded at TA= +125°C, maximum frequency= 500 kHz for Dual ln·Line package (OJA= 95°C/W) or 300 kHz for Ceramic Flat Pak (OJA= 165°C/W).

4-8

FAIRCHILD INTEGRATED CIRCUIT 9621
ELECTRICAL CHARACTERISTICS
INDUSTRIAL TEMPERATURE RANGE 0°C to +75°C (UXX962159X)
LIMITS
SYMBOLNOTES

CHARACTERISTICS

Vol

Output Low Voltage

VoH

Output High Voltage

0°C
MIN. MAX.

+25°C
MIN.

400
4.2

4.2

TYP.

MAX.

+75°C
MIN. MAX.

200

400

450

4.4

4.2

UNITS

CONDITIONS & COMMENTS

mV

IOL = 20 mA

Vcci =4.75V
Vccz = 11.4 V

v

10 H = -20mA

Vcci =4.75V
Vccz = 11.4 V

lsc

1Output "Short Circuit"
Current-100 -300

mA

Your= OV

Vcci = 4.75V
Vccz = 11.4 V

loL

1Output Low Current

75mA

Your= 5.0V

Vcci = 4.75V
Vccz 11.4 V
Vcci = 5.25V
Vccz = 12.6V

200

=

IF

Input Forward Current

l.8

1.15

1.8

1.8

mA

VF=OV

IR

Input Reverse Current

5.0

<LO

5.0

10.0

µA

VR

= 5.5V

Vcci
5.25V
Vccz = 12.6V

380

500

v

t0 L = 2.8 mA

Vcci = 5.0V
Vccz 12.0V

4.2v

loH = -2.3mA

Vcci = 5.0V
Vccz 12.0V

=

VoLR

2

Resistive Output
Low Voltage

VoHR

2

Resistive Output· High Voltage

VoLc

3

Clamped Output
Low Voltage-1.0 -2.0v

loL= -20mA

Vcci
5.0V
Vccz = 12.0V

VoHc

3

Clamped Output
High Voltage

6.0

7.0

v

10 H = 20mA

Vcci
5.0V
Vccz = 12.0V

Inputs
Open

Vcci
Vccz

= 5.25V= 12.6 V

CL= 5000 pf

Vcci
Vccz

= 5.0V= 12.0V

CL=30pF

Vcci
5.0V
Vccz = 12.0 V

4.0

lcc1

+5 V Supply Current

7.0

4.7

7.0

7.3

mA

lcc2

+12 V Supply Current

9.8

6.5

9.8

9.8

mA

30

200

tpd+

4

1i>d-

4

Turn-Off Timens

Turn-On Time

80

200

ns

\.d+

Turn-Off Time

13

40

ns

1i>d-

Turn-On Time

9

40

ns

VIL

Input Low Voltage

1.5

1.0

VIH

Input High Voltage

1.3
2.2

2.0

1.7

0.7
1.8

v
v

NOTES:(1) Pulse tests to insure transient current handling (test time= 3 seconds maximum - one side only).
(2) Test output resistance including 1050 output resistor.
(3) Tests output clamp diodes.
(4) Maximum frequency= 500 kHz with both sides loaded at TA= +75°C for both Dual In-line package and Ceramic Flat Pak.

4-9

= 5.25V= 12.6 V
Vcci = 4.75V
Vccz = 11.4 V
Vcci
Vccz

=
=
=
=

=

FAIRCHILD INTEGRATED CIRCUIT 9621
TYPICAL OUTPUT LOW
CURRENT VERSUSOUTPUT LOW VOLTAGE
300

vc7 ·

Iov
1
Ycc 2 • 12V·

< 250

•

TYPICAL OUTPUT HIGH
CURRENT VERSUSOUTPUT HIGH VOLTAGE

a~200,-

Ycc 2 • 12V,__I-' ;;-

~ 150

~ 100

0

2 50

_5-400

0

if

0

p lZl

vcc 1 • 5.ov

I-"

_L

1.0

3.0

2.0

4.0

17

vv

LOGIC LEVEl,s VERSUSAMBIENT TEMPERATURE

v

v

~

5.0 ..-..---,.---.-.....-~--.---,-.---.,.--,TYP!CAL+-+--+--t--1
CASE
t--+-+--+--+--+-+--t-t--+--1~·
Vcc1 • 4.5v --t-t--+-+--+--+--4~ 3.0 Vcc 2 • l0.8V
10H • -romA--t-l--+-+--+--+--4~~ 2.0 t--+-+--+--+--+-+--t-l--+-l

s
>01.0

l-+-+-+--+-+-+--t-l-+-1.!m. • romA

TYPICAL WORST CA!i£---!::--

0'--~-'--'--"--'--"'--'-~.,___,

-500

5.0

wili!

~ 4.0

0

1.0

2.0

3.0

5.0

VOL - OUTPUT LOW VOLTAGE - VOLTS

VoH - OUTPUT HIGH VOLTAGE - VOLTS

SUPPLY CURRENT VERSUS
SUPPLY VOLTAGE
INPUTS GROUNDED

SUPPLY CURRENT VERSUS
SUPPLY VOLTAGE
INPUTS OPEN

-60

4.0

-ro

o

ro

60

100

SUPPLY CURRENT VERSUS
SUPPLY VOLTAGE
10ll

Yee • 12Y
TA 15°C!

16 1---t---+-+--+-+--+---+--t

-1.

!ii;

~. 12
:::

WORST CASE

~

JL
ruV

ili 8.0 t--t---t--t--i-L._-V'_L_'7t"-.,,t.-.t':71
INPUTSOPE~ JL ~TYPICAJ&f/C&:'.
JI ..J.

0

U

U

0
0

2.0

4.0

6.0

SWITCHING TIME VERSUSTEMPERATURE

SWITCHING TIME VERSUSTEMPERATURE

lL
fl_

~

17

I

.L

1/

/

§ -10

Jl -30

WI

$!'

[Z

rt

-6.0

7-

~j_

0

{/_

~

7
-2.0

0

2.0

6.0

O'--~-'--'--'--"--'--"'--'~'---'

-60

10

-ro

o

ro

TYPICAL SUPPLY CURRENTVERSUS FREQUENCY
Vcc 2 - 12V
NOOUTPLij_LOADING
~ 30

ru

]

I

lL
v

DUTY CYCLE50%

AMPLITUDE
0·4V

~
0.5

1.0

2.0

100

140

SWITCHING TIME TEST CIRCUIT

Vcc 1 : s.ov

0.2

60

TEMPERATURE (°CI

VouT - OUTPUT VOLTAGE - VOLTS

0.1

M

U

TYPICAL OUTPUT IMPEDANCEWITH BACK MATCHINGRESISTORS

§
~ 10

0

1--v ORS!jlSE

INPUTS GROUNDED

Vccl - SUPPLy VOLTAGE - VOLTS

il 30

40

TYPICAL~

If'.::
1v

Vcc2 - SUPPLY VOLTAGE - VOLTS

Vcc 1 • 5.ov
Ycc 1 • 12V

-50
·10

i

8

fL p
"
v.z

Vcc 1 - SUPPLY VOLTAGE- VOllS

50~~~ 4.0-1.0O'----'---'~-'-~-~_.___,~

0

!L

I

4.0

-ro'---'---'--'--'--~-"---'~

il
§

1.0

~ 6.0

l-----l----+----1---l----l----.L.--l-~~lZ-...i

J/>N

5.0

10

f - FREQUENCY - MHz

4-10

140

TA - AMBIENTTEMPERATURE-°C

TA - AMBIENT TEMPERA~URE - C

WAVEFORMS

8.0

FAIRCHILD INTEGRATED CIRCUIT 9621
DESCRIPTION OF REFLECTION DIAGRAM USAGE

The reflections on any line may be found by using the following procedure:

1. Draw the driver output characteristics for both the "high state" and the "low state" on an I - V graph in the same manner as the reflection
diagram.
2. Draw the receiver input characteristic on the same graph. The two points of intersection of the receiver and driver characteristics are the two
DC operating points.
3. Choose to analyze either the reflections for the output going low or high. In the example chosen the negative transition is analyzed.
4. Draw a line with a slope equal to the impedance of the line to be used, (Z 0 = lOOfl in the example), from the "high state" operating point(labeled A on our graph) to the "low state" output device characteristic (B 1). B1 equals the conditions at the driver output immediately afterturn-on.
5. Reverse the slope of Z0 and sketch it from B1 to the receiver input characteristic (C 1). C1 equals the conditions at the receiver when the
wavefront B1 first reaches it.
6. By continuing this procedure of reversing the slope of Z0 at each node all the reflections (BJ> C1, B2' C2, B3 , C3 - - - BN, CN), where Bx is thevoltage at the driver and Cx is the voltage at the receiver, can be found.
The same procedure is used to check the reflections when switching the output high.

BACK-MATCHING, also referred to as reverse termination, offers several advantages to the user. It reduces the system power by not requiring the highcurrent for resistive termination and it reduces the DC line losses because IR drops in the line become minimum.
To back-match any line (output switching low):
1. Measure the output resistance, Rout• from the "low state" operating point to B1•
2. Subtract Rout from Z. (Rout+ RM = Z0). This value RM, is the required back-matching resistance.
3. Place RM in series with the output of driver.
4., The reflections that occur on the line with RM inserted can be treated in the same manner as the general case. The results are B1' and C1' andthe receiver will not see any reflections.
When switching the line differentially RM + Rout= Z0/ 2 • The matched output characteristics of the 9621 make it possible to back-match effectively andrequire analysis of switching only one state.
·

TYPICAL REFLECTION DIAGRAM*

-3.0

i

-1.0

1.0

-1

3.0

Your· OUTPUT VOLTAGE - VOLTS*GRAPHICAL ANALYSISFirst Presented by John B. James of I .C.T. (Eng.) LTD.

4-11

.·

5.0

7.0

9.0

10

FAIRCHILD INTEGRATED CIRCUIT 9621

n

REFLECTION TEST CIRCUIT

9621

RM

BACK MATCHING TABLE

Zo
50 ll
75 ll
92 ll
100 ll130 ll
300 llThe reflections are two delay's of the line wide. Rt.. m is the total impedance seen at the receiving end.

RM = 0600 llRM

RM

when usedsingle ended
32 ll
62 ll
82 ll
90 ll
120 ll
290 ll
590 llwhen useddifferentially
16 ll
30 ll
41 ll
45 ll
60 ll
145 ll295 llR+erm = .75!1

11111111111111111••••••••••••••••••~········==~·········1••••••••

~
:==.

tii
,

1·

N • • • • • • • • •

J

.. •

1111••111111111
200 ns/Div.

4-12

9622
DUAL LINE RECEIVERA FAIRCHILD COMPATIBLE CURRENT SINKING LOGIC PRODUCT;ENERAL DESCRIPTION - The 9622 is a dual line receiver designed to discriminate a worst case logic swing
lf 2 volts from a ± 10 volt common mode noise signal or ground shift. A 1.5 volt threshold is built into theiifferential amplifier to offer a CCSL compatible threshold voltage and maximum noise immunity. The offset
s obtained by use of current sources and matched resistors and varies only ± 5% (75 mV) over the military
md industrial temperature ranges.

TYPICAL DUAL IN-LINE PACKAGE
In Accordance WithJEDEC (T0-116) Outline

rhe 9622 allows the choice of output states with the inputs open without affecting circuit performance by
Jse of S3. A 130 n terminating resistor is provided at the input of the each line receiver. An enable is also
lrovided for each line receiver. The output is CCSL compatible. The output high level can be increased to+12 V by tieing it to a positive supply through a resistor. The outputs can be wire-OR'ed.

FEATURES:• CCSL COMPATIBLE THRESHOLD VOLTAGE• INPUT TERMINATING RESISTORS• CHOICE OF OUTPUT STATE WITH INPUTS OPEN
• CCSL COMPATIBLE OUTPUT• HIGH COMMON MODE
• WIRE-OR CAPABILITY• ENABLE INPUTS• FULL MILITARY TEMPERATURE RANGE• LOGIC COMPATIBLE SUPPLY VOLTAGESNOTES'
L LHds iire intended for insertion in hole rows on·'-!~~,i~.i~:?.t~-~5j5Tt~~s~~~g~~:~:i~1!~1i~~:tde ~~~~rtion
2. Board-drilling dimensions should equal yourpractice for a conventional .020 11nch diameter lead

FLAT PACKAGETOP VIEW~BSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)

Storage Temperature
Temperature (Ambient) Under Bias
Vcci Pin Potential to Ground Pin
Input Voltage
Voltage Applied to Outputs for High Output StateVEE Pin Potential to Ground Pin
Enable Pin Potential to Ground Pin-65°C to +150°C-55°C to +125°C-0.5 Vto +7V±15V-0.5 V to +13.2 V-0.5 Vto -12 V-0.5 V to +15 V.

,'3"~~;J6,_MAX.

.015"}7~8-.020~.370~.26MAX.-.370, .250 '
.250

.065
( .050--~=::....>-===----._T

LOGIC DIAGRAM
S3

GMO

OUTA

~.._~OUTB

EN A

EN B

A+

8+

A1300

8 1300,ORDER INFORMATIONA-

8-Specify U6A9622XXX for 14 pin Dual In-Line package, U319622XXX for 14 pin Flat package where XXX is 51X
for the -55°C to +125~C temperature range, or 59X for the 0°C to +75°C temperature range.

Vcc ..._ _;....__..-- VEE

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

4-13

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD DUAL LINE RECEIVER • 9622
ELECTRICAL CHARACTERISTICS (Temperature Range -55°C to +125°C, Vee= 5.0 V ± 10%, VEE= -10 V ± 10%) (Part No. UXX962251X)
LIMITS
SYMBOLCHARACTERISTICS

VOL

Output Low Voltage

VoH

Output High Voltage

lcEx

Output Leakage Current

lsc

Output Shorted Current

IR(ENABLE)

Enable Input
Leakage Current
Enable Input
Forward CurrentIF( ENABLE)-55°C
MIN. MAX.

MIN.

0.40
2.8

+25°C
TYP. MAX.
0.25

3.0

+125°C
MIN. MAX.
0.40

0.40

3.3

v

200

µA

-1.3 -3.1 -1.4 -2.15 -3.1 -1.3 -3.1

mA

100

50

Vcc=4.5V*VDIFF = 2.0 V
Vee= 4.5V*VDIFF = 1.0 V
Vcc=4.5V*VDIFF = 1.0 V
Vee= 5.0V*VoiFF = 1.0 V
Vee= 4.5V
S3 = 4.5Vv

2.9

CONDITIONS & COMMENTS

UNITS

2.0

5.0

µA

-1.5

-0.96 -1.5

-1.5

mA

VEE= -11 v
IOL = 12.4 mA
VEE= -9.0V
loH = -0.2mA
VEE= -11 v
VcEx = 12V
VEE= -lOV
V5c = OVVEE= -11 v
VR =4.0V ""VEE= -9.0V
VF=OV

Vee= 5.5V
S3 = OV
Vee= 5.0V- Input= Gnd

JF(+ Input)+InputForward Current-2.3-1.67 -2.1

-2.0

mA

IF(-lnput)- Input
Forward Current
Input Low Voltage-2.6-1.87 -2.4

-2.3

mA

Vco S3 = 5.0V
+Input= Gnd

1.3

1.4

1.0

0.7

v

1.0

1.5

2.0

2.0

v

Vee= 5.0V ±10%
VEE= -10 v ±10%
Vee= 5.0V ±10%
VEE= -10 v ±10%

-10

±12

+10

v

130

175
22.9

n

VIL(ENABLE)

VcM

Differential Input
Threshold Voltage
Common Mode Voltage

R13o!:lTerminating ResistanceIce

5 V Supply Current

13.7

IEE

-10 V Supply Current-6.5 -11.1

mA

tpd+

Turn-off Time

38

50

ns

tpd-

Turn-on Time

35

50

ns

vth

1.0

2.0

100

1.0

mA

Vee= 5.5V
VEE= -11 v
S3, + Inputs= 5.5 V, - Inputs= 0 V
Vee= 5.5V
VEE= -11 V
S3, + lriputs = 5.5 V, - Inputs= 0 V
Vee= 5.0V
VEE= -lOV
VIN 0'.""'3 V, RL = 3.9 k!J, CL = 30 pF
Vee= 5.0V
VEE=-lOV
v 1N 0-+3.0 v, RL = 0.39 kn, CL = 30 pF

SCHEMATIC DIAGRAM(LINE RECEIVER)
Vee 111

2k!l

(131

3k0

141

3110

1300

1300

(141

151
3k0

3110

161
5k!l

51dl

111
8.2k!l

3.000

8800

' - - - + - - - + - - - - - - - - - - - - - - - - + - - - + - - < > I l l VEE

4-14

VEE=-lOV
VF=OV

Vcc=5.0V
VEE=-lOV*VDIFF = 1.0 v or 2.0 v*V01 FF is a differential input voltage referred from A+ to A- and from B+ to B-.

5110

VEE= -lOV
VF= ov

FAIRCHILD DUAL LINE RECEIVER • 9622
ELECTRICAL CHARACTERISTICS (Temperature Range 0°C to +75°C, Vee= 5.0 V ±5%, VEE= -10 V ±5%) (Part No. UXX962259X)~

SYMBOLCHARACTERISTICS

0°C
MIN. MAX.

VOL

Output Low Voltage

0.45

VoH

. Output High Voltage .

lcEx

Output Leakage Current

80

lsc

Output Shorted Current-1.3 -3.1

IR(ENABLEJ

Enable Input
Leakage Current
Enable Input
Forward Current

IF(ENABLEJ

LIMITS+25°C
MIN. TYP. MAX.
0.25

2.9

3.o

0.45

0.45

3.3

UNITS

+75°C
MIN. MAX.

2.9v

Vee =4.75V. *VDIFF = 2.0 V,

VEE= -10.5 v
10 L = 14.1 mAv

Vee= 4.75V*VDIFF = 1.0 V
Vee= 4.75V*VDIFF = 1.0 V
Vcc=5.0V*VolFF = 1.0V
Vee =4.7~V
S3 = 4.75V

VEE= -9.5 V
10 H = -0.2mA

VEE= -lOV
V5c = OVVEE= -10.5 v
VR = 4.0V

200µA-1.4 -2.15 -3.2 -1.3 -3.l

mA

5

10

µA

100

CONDITIONS & COMMENTS

VEE= -10.5 v
VCEX = 5.25V-1.5-.96 -1:5

-'l.5

mA

Vee= 5.25 V
S3 = OVVEE= -9.5V
VF=OV
VEE= -lOV
VF.= OV
VeE=-lOV
VF= ov

IF(+lnput)+InputForward Current-2.6-1.67 -2.4-bmA

Vee= 5.0V- Input= Gnd

IF(- Input)- Input
Forward Current-2.9-1.87 .-2.7

-2.6

mA

Vee· S3 = 5.0 V+Input= Gnd

VIL( ENABLE)

lnputlow Voltage .

1.2

1.4

1.0

0.85

v

Vee= 5.0V ±5%
VEE= -10 v ±5%

vthDifferential Input
Threshold Voltage

i.o

1.5

2.0

2.0

v

.VCM

Common.Mode Voltage-7.5±12 +7.5v

Vee= 5.0V ±5%
VEE= -lOV ±5%
Vee= 5.0V
VEE= -lOV*VDIFF = 1.0 v or 2.0 v

R13on

Terminating Resistance

91

130

185

n

Ice

5 V Supply Current

i3.7

22.9

mA

lee

-:10 V Supply Current-6.5 -11.1

mA

tpd+

·Turn-off Time

38

100

ns

Vee= 5.0V·Vee= -10 V
v 1N o-.3.0 v, RL = .3.9 kn, CL = 30 pF

tpd-

Turn-on Time

35

ioo

ns

Vcc=5.0V
VeE=-lOV
v 1N o-.3.0 v, RL = 0.39 kn, cL = 30 pF

1.0

2.0

1.0

Vee= 5.25V'
Vee= .:..10.5 v
S3 , +Inputs=; 5:25 V, -Inputs= 0 V
Vee= '5.25 v:
VEE= -10.5 v
S3 , +Inputs= 5.25 V, -Inputs= 0 V*V01 FF is a differential input voltage referred from A+ to A- and from B+ to B-.

WAVEFORMS

SWITCHING TIME TEST CIRCUIT

Vee

tpd+

tpd-

1

I. ~..

I

VIN~_:Hu·-~

OY- - ~ :~-~-rt:J---vouT

·~

JCL

VouT
----------------. · ov
STANDARD USAGE

RECEIVER SYSTEM

DRIVER SYSTEM

LOGIC

9622

LINE DRIVER

4-15

LOGIC

FAIRCHILD· DUAL· llNE RECEIVER • 9622
TYPICAL ELECTRICAL CHARACTERISTICS

TYPICAL OUTPUT LOW VOLTAGE
VERSUSOUTPUT LOW CURRENTTYPICAL OUTPUT HIGH VOLTAGE
VERSUSOUTPUT HIGH CURRENTLOGIC LEVELS VERSUSAMBIENT TEMPERATURE
13.0

5.0 t----+--+--+--+--+-+-+-+--+----+---1

"

;::

E

~

~

200

TYPICAL VoH@ 'ciH. -0.2mA......., WORST CASE VoH ® loH. -o.2mA-

1-

2.5

~ 2.0

:i

g

g

"59 150

~

5 100

1.5

Vee· 4.5v§

0VEE· -UV

's Lo
>o

>o

0,5 1--1 WORST CASE Vol® 'oL. ,12 •. 4rriA~JPICAL ~ '.E·4mA
0

0

5.o

~

~

-2.0

-2.5

-3.0

TYPICAL V.,, • Vo1FF TRANSFER
CHARACTERISTICS

TYPICAL OUTPUT VOLTAGE
VERSUSCOMMON MODE VOLTAGE

0

20

40

60

4.0

2.0

~

3.0 t--+--+--it+++--+-llt+--+*i-f--+--tts

t--+--+--it+++--+-ot+->-..-r---t--t

g

E;

g

} ~

3.0 t--t-+-t--+--t--+-+--l-1-t-f--lt-----1~ 2.0 t--t-+-t--+--t--+-+--l--i...: ~-...,

t-~11++--+....+---t--i~-+ff-1--1--'-i>o 1.0 1--t--t---ttt+l--t-J_

1.4

±

1.8

2.0

~

~ -2.0z>~ 1.0 t---t-+-+--+--+--+---+--+-l-+t---1
-20

-12

-4.0

0

4.0

12

A -INPUT

iii

-4.0

Ol:::::::i:::!:::l:::::±:=V~IN=·~2.=0-~5.=0V:±::::l=:::!::l::::::I
1.6

100 120 140

INPUT CURRENT VERSUSINPUT VOLTAGE

4.0 t--t-+-t--+--t--+-+--l-1-t-t--f~

80

TA• AMBIENT 1EMPERA1URE °C

Vee. 4.'5V

t-+-+-~-60 -40 -20

5•0 Vee. 5.0V VEE. -lOV

Vee. 5.5v

2.0

-6.0
-12

20

~

..

-8.0

~
-4.0

4.0

8.0

VOIFF - DIFFERENTIAL INPUT VOLTAGE - VOLTS

VcM - COMMON MOOE VOLTAGE - VOLTS

VIN - INPUT VOLTAGE· VOLTS

TURN ON TIME VERSUSAMBIENT TEMPERATURE

TURN OFF TIME VERSUSAMBIENT TEMPERATURE

POWER DISSIPATION VERSUSAMBIENT TEMPERATURE

loo Vee • 5.ov
VEE = -lOV --+---tf--+-+-_,_-+----+--<LOAD A, Rt• 500Q c 1 • 50pf v1.• 5.0V
80 LOAD B' Rt. 390Q cl. 30pF vl. 5.0V
LOAD c'200Q cl. 50pf vl ·.l.OV

++--1

".!..

~

-1.5

loH - OUTPUT HIGH CURRENT - mA

I t-+-+-~
5-1.0'oL - OUl PUl LOW CURRENT -mA

4.o Vee~ 5.ov

~

-0.5

;: :-±-·· ... !'OR~T

ioo Vee. 5.ov
VEE • -lOV -+--+---tf--+-+--+--+--<LOAD A' Rl. 500Q cl. 50pF vl. 5.0V
80 LOAD B, Rt• l.9kQ Cl• 30pF Vl • 5.0V
LOAD C, ~ • 200Q ~I.." 50pF V • 3.0V

t-"--t--1--

60f-,--+-+-+--+--+-+-+--l-f--I~I~

CAk WI \H LO~D 8

12

• •

15 200 I--+--+--+--+--+--+--+->--+--<

~

iii
c;

C LOAD B
YPICAl~ «J (LOAD~~~i:::tI$~:::;~-H

i lOO~:t::::t:::t:::l=::±:::..i.-J=c-I-=~j.

201---+-+--+--+--+--+--+--+-t--to~......_+-~~~~--+---+-~~-2002060

100

TA - AMBIENT TEMPERATURE - °C

140

-20
TA - AMBIENT TE~PERATURE - °C

4-16

0

20

60

100

TA - AMBIENT TEMPERATURE - °C

140

9624. 9625
DUAL CCSL, MOS INTERFACE ELEMENTS
FAIRCHILD INTEGRATED CIRCUITSGENERAL DESCRIPTION - The 9624 is a dual two-input CCSL compatible interface gate specifically designed
to drive MOS. The output swing is adjustable and will allow it to be used as a data driver, clock driver ordiscrete MOS driver. It has an active output for driving medium capacitive loads.

TYPICAL DUAL IN-LINE PACKAGE
In Accordance WithJEDEC (T0-116) Outline

The 9625 is a dual MOS to CCSL level converter. It is designed to convert standard negative MOS logic levels
to CCSL levels. The 9625 features a high input impedance which allows preservation of the driving MOS
logic level.
Both the 9624 and 9625 are available in the 14-pin ceramic Dual In-Line package and the 114 x 114 Flat Pak.

NOTE 1+.375 MAX.--j.200MAX.

FEATURES• CCSL COMPATIBLE INPUTS/OUTPUT• MOS COMPATIBLE OUTPUT/INPUTS•LOW POWER.125 TYP..110
.090

NOTE2

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Vee Pin Potential to Ground Pin
Voltage Applied to Outputs for high output. state (9624)
Voltage Applied to Outputs for high output state (9625)
Input Voltage (D.C.) (9624)
In put Voltage (D.C.) (9625)
V00 Pin Potential to Ground Pin
V00 Pin Potential to Tap Pin (9624)-65°Cto +150°C-55°C to +125°C
V00 to +lOV
V00 to +Vee value-0.5 V to Vcc value-0.5 V to +5.5 V
Vee to Voo-30 V to +0.5 V-30 vto +o.5 v
Vee+ 0.5V

VTAP

NOTES,
I. Leads are intended for insertion in hole rows on.300".centers. They are purposely shipped ~ith"positive" (.375) misalignment to facilitate insertion.
2. Board·drilling dimensions should equal yourpractice for a conventional .020 linch diameter lead.

14-PIN FLAT PACKAGETOP VIEW

ORDER INFORMATION
Specify U6A9624XXX and U6A9625XXX for 14-pin T0-116 Dual In-Line package or U319624XXX and U319625XXX
for 14-pin Flat Package where XXX is 51X for the -55°C to +125°C temperature range, or 59X for the
0°C to + 75°C temperature range.

9624

2

9625

GNO

Vee

14

NC

TAP

13

GND

Vee

14
13

2

3

12

3

12

4

11

4

11

5

10

5

10

6

9

6

9

7

8

7

Yoo

8

F.A.IRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

4-17

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD INTEGRATED CIRCUIT 9624
TABLE 1.,.... ·ELECTRICAL CHARACTERISTICS (TA= -55°C to +125°C, Vee= 5.0 v ±10%)
SYMBOLCHARACTERISTICS-55°C
MIN. MAX.

LIMITS+25°c
MIN. TYP. MAX.

+125°cMIN. MAX.

UNITS

VOHI

Output High Voltage-1.0-1.0 -0.5

-1.0

Volts

VOH2

Output High Voltage+3.5+3.5 +4.0

+3.5

VOL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

1.4

1.1

0.8

IF

Input Load Current

-1.40

-1.25

-1.13

IR

Input Leakage
Current
Output Leakage
Current
Output Short
Circuit Current

2.0

2.0

5.0

leEx
lse

Vee= 4.5 V, Yoo= -28 V, VrAP = 0 V
loH=-10,µA
Vee= 5.5 V, Y00 = -20 V, VrAP = 5.5 V
Inputs at threshold voltages (V1L) 10 H = ·-10 µA
Volts Vee=4.5V, 10 L = 10 mA, V00 = -11 to -28 V@ V1H• 0 ~ VrAP ~ Vee
Volts Guaranteed input highthreshold for all inputs
Volts Guaranteed input low
threshold for all inputs
mA
Vee= 5.5 V, VF= 0.4 v
V00 = -11 to -28 VµA
Vee= 5.5 V, Vp_ = 4.0 V
V00 = -11 to·-28Vµ.A
Vee= 5.5 V, VrAP = 0 V
V00 = -28 V, Your= 0 V
mA
Vee= 4.5 V, VrAP = 0 V, V1N = 0 V
V00 = -11 V, Your= ...,..11 V
mA
Vee= 5.5V, V00 = ·-15 V, VrAP = 0 V
Inputs OpenmA
Vee= 10 V, V00 = -30 V, Inputs Open
VrAp=OV
ns
Vee= 5.0 V, See Figure 2
ns
V00 = -13 V, VrAP = OV

See Note 1
2.1

1.7

1.9

50
-12

-31

-14

-32

lvee

Vee Supply Current

6.1

IMAX

Max. Current

10

tpd+
tpd-

Switching Speed
Switching Speed

190
50

-11

CONDITIONS

-28

250
100

Note 1: Max =.V00 +LO V over Temperature Range
Typ = V00 +0.2 V over Temperature Range

SCHEMATIC DIAGRAM

mo

5kQ

IN 1

5000

5kO

15k0

GNO

IN 2

GND
1

1

OUT 1

OUT 2

----<i10

6110

6k0
Jk(l

Yoo
7

Fig. l4-18

FAIRCHILD INTEGRATED CIRCUIT 9624
TABLE 11ELECTRICAL CHARACTERISTICS (TA = 0°C to + 75 °C, Vcc = 5.0 V ± 5%)
SYMBOLCHARACTERISTICS

LIMITS+25°C

0°C
MIN. MAX.

MIN.

TYP.

MAX.

+75°C
MIN. MAX.

UNITS

VOHI

Output High Voltage-1.0-1.0 -0.5

-1.0

Volts

VOH2

Output High Voltage+3.25+3.25 +3.75

+3.25

Volts

Vol

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

1.2

1.1

0.95

Volts

IF
IR

Input Load Current
Input Leakage
Current
Output Leakage
Current
Output Short
Circuit Current

-1.32
5.0

-1.25
5.0

-1.20
10

µA

ICEX
lsc

See Note 1
2.0

Volts

1.9

1.8

Volts

100
-12

-31

-14

mA

µA

-32

-12

-31

mA

lvcc

Vcc Supply Current

6.1

mA

IMAX

Max. Current

10

mA

tpd+
tpd-

Switching Speed
Switching Speed

250
100

ns
ns

190
50

CONDITIONS
Vee= 4.75V, V00 = -28 V, VrAP = 0 V
loH = -lOµA
Vee= 5.25 V, V00 = -20 V, VrAP = 5.25 V
10 H = -lOµA
Inputs at threshold voltages (V 1L or V1H)
Vee =4.5V, Im= 10 mA, V00 = -11 to -28 V@ 0::;; Yr AP ::;; Vee
Guaranteed input highthreshold for all inputs
Guaranteed in put low
threshold for all inputs
Vee = 5.25 V, VF = 0.45 V
Vee= 5.25 V, VR = 4.5 v
Vee= 5.25 V, VrAP = 0 V
V00 = ·-28 V, Your= 0 Y
Vcc=4.75V, VrAP=OV, V1N=OV
V00 = -11 V, Your= -11 V
Vee= 5.25 V, Y00 -15 V, VTAP = 0 V
Input Open=

Vee= lOV, V00 = -30V, VrAP = OV
Input Open
Vee = 5.0 V, See Figure 2
V00 = -13V, VrAP = OVNote 1: Max= V00 +l.O V over Temperature Range
Typ = V00 +0.2 V over Temperature Range
ELECTRICAL CHARACTERISTICS • 9624

TYPICAL OUTPUT CURRENTVERSUS OUTPUT VOLTAGE(LOW STATE)THRESHOLD VOLTAGE VERSUSAMBIENT TEMPERATURE

TA·~S°C

kd

Vee ~s.ov

2.5 l---+----+--+-+---+----+--+---1

Voo. -nv

200

1150

~

L

5100

-55

·25

0

25

50

15

100

125

50

lL

-13

z

rz::

rz::

I-

0

0.5 1---+----+--+-+---+----+---+---I

TYPICAL OUTPUT CURRENTVERSUS OUTPUT VOLTAGE(HIGH STATE)

p-35 !----+--+-- f-·+--t--+--1---1-40~~~~-~~~~~

-12

-II

-IO

-9.0

-8.0

-7 .0

-6.0

0

-4.0

-8.0

-12

-16

TA· AMBIENT TEMPERATURE· °C

VOL - OUTPUT VOLTAGE - VOLTS

VoH - OUTPUT VOLTAGE - VOLTS

POWER DISSIPATION VERSUSAMBIENT TEMPERATURE

TYPICAL SWITCHING TIMEVERSUS LOAD CAPACITANCESWITCHING TIME VERSUSAMBIENT TEMPERATURE

Vee =5.SV

Voo. -~v
I" 50 >---+--+--+~MAXt--G-+ATE_O_NPO+-WE-R-+--<~ ~=~=--=~=:==~--::::-:-_:_---:
40~~~r--1::;:;;::t--t~TrYP-GA~TE-ON~PO~WE~R:t:'"Iiit-~~l---+--+---+-t---+--+---+--1~

I< 10~~--~f-·MAX_·-:t.!!:i~:t.--1--+­200

b--1!",..AY-l-'"'"-+-+-+-+-+-+-+--l

TYP GATE OFF POWER
o~~~~~~~~~~

-55

-25
0
25
50
15
'100
TA - AMBIENT TEMPERATURE - °C

125

0

200

400
600
800
C1 · LOAO CAPACITANCE· pf

4-19

1000

-55

-25
0
25
50
75
TA - AMBIENTTEMPERATURE • °C

100

125

FAIRCHILD INTEGRATED CIRCUITS 9624 • 9625
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

9624
VIN

Your

PULSE GENERATOR

VIN
REP RATE = 500 kHz
AMPLITUDE= 3 V
PULSE WIDTH= lµst,, t 1 :::; 10 ns

e=

!voo

TAP!
13 7

re
15pf

J
J

re

":"

l

j

tpd+

1.5¥

!pd-

Your

":"

TESTS

CONDITIONS

tpd +, tpd -

TA
(oC)

Yee
(Volts)Yoo(Volts)Tap
Voltage

25

5.0

-13

0

Fig. 2LOADING RULES:----t>:JI-----

9624

1/1

1/1

__l_)o9625

SEE NOTE 1

SEENOTE2

3/1**The extender pin allows the number of inputs to be extended by adding diodes or the DTµL 933 extender.
Note 1: Fan out into MOS is limited only by MOS leakage currents.
Note 2: 1,N = + 210 µA

APPLICATION:

1-ccsl' i:OGic- ~I

II: =D1u--+,__,
L------J

CLOCK DRIVING (using a high capacitance drive scheme)

TYPICAL SWITCHING TIMESVERSUS LOAD CAPACITANCE

220

200
l80

VIN

1.5V--~I~v0o=-27V
VTAP = OV

FDH& OREQUIVALENT

VouT
Vour

J

k:'.'.

loll=-i!49624

Vee= sv

1-lroR MlL

160

llO

\-_DELAY TIME

I - 'I

-1Ti

I

-ts-1

1---FALL TIME

IOO

v=-:::I-RISE TIME

!Kl
60
40

~

lO ~

~

A~
~RI Tl

.1

0
0

200

400

CAPACITIVE. LOAD - pf

4-20

..d7

800

FAIRCHILD INTEGRATED CIRCUIT 9625 ··TABLE 111ELECTRICAL CHARACTERISTICS (TA= -55°C to +125°C, Yee= 5.0 V ±10%)
SYMBOLCHARACTERISTICS-55°C
MIN. MAX.

LIMITS+25°C
MIN. TYP. MAX.

.. +125°C
MIN. MAX.

UNITSCONDITIONS

YoH

Output High Voltage

2.5

2.6

2.5

Volts

Yee= 4.5 V, 10 H ::::: -60 µA
V00 = -11 V
Inputs at threshold voltages (V1H)

YoL

Output Low Voltage

Yee= 5.5 V, IOL = 1.5 mA
Yee= 4.5 V, loL = 1.2 mA
V00 = -11 V
Inputs at threshold voltages (V1L). Guarantee.d input highthreshold for all inputs
Guarantee.d jnput low
threshold torall inputs

0.5..
Input HighVoltage

VIL .

Input Low Voltage

IF

Input Load Current·Output Leakage Current
Supply Current
Supply Current ·V00 Supply Current

IMAX
tpd+
tpd-

-3.0
-9.0

~

Volts

-3.0

-.3.0

Volts

-9.0

-9.0

210

210
'50
4.8
2.1
-9.0

·-

Max. V00 Supply Current
Switching Speed
Switching Speed

<

0.5

..

VIH

leEx
lveeL
lveeH
lvoo

0.5

.,..-25
55
90

100
150

Volts
210

µA

µA
mA

Yee= 5.0 V, VF= -3.0 V, V00 = -13 \I
Yee= VeEx = 4.5 V, V00 = -13 V
Yee= 5.5 V, V00 = -15 V, V1N = -10 V
Yee= 5.5 V, ·V00 -15 V, V1N = oV
Yee;:::: 5.5 V, V00 = ::-15 V
Input open or.gnd '

=

mA
mA
ns
ns

Yee= 8.0V, Vl)0 =-20V, V1N = OV
Yee= 5.0 V, V00 = -13 V"
See Figure4'.

SCHEMATIC DIAGRAM

Vee
14

IN 1 5lO IN 2

22kQ

22kQ

GND

7

Voo
Fig. 3

FAIRGHILD INTEGRATED CIRCUIT 9625
TABLE IVELECTRICAL CHARACTERISTICS (TA = o•c to + 75 •c, vcc = 5.0 v ± 5%)
SYMBOL

LIMITS+25°C

o•c

CHARACTERISTICS

MIN. MAX.

MIN.

2.5

2.6

TYP.

MAX.

+75°C
MIN. MAX.

UNITSCONDITIONS

2.5

Volts

Vee= 4.75 V, 10 H = -60 µA
V00 = -11 V
Inputs at threshold voltages (V1H)
Vee= 5.25 V, IOL = 1.52 mA
Vee= 4.75 V, IOL = 1.33 mA
Inputs at threshold voltages (V1L)
Guaranteed input highthreshold for all inputs
Guaranteed input low
threshold for all inputs

VoH

Output High Voltage

VOL

Output Low Voltage

0.5

0.5

0.5

Volts

VIH

Input High Voltage

-3.0

-3.0

-3.0

Volts

VIL

In put Low Voltage

IF

Input Load Current
Output Leakage Current
Supply Current
Supply Current
V00 Supply Current

lcex
lvccL
lvccH
lvoo

-9.0

-9.0
210

tpd+
tpd-

µA
µA

-25
100
150

55
90

THRESHOLD VOLTAGE VERSUSAMBIENT TEMPERATURE

Volts
210

210
100
4.8
2.1
-9.0

Max. V00 Supply Current
Switching Speed
Switching Speed

IMAX

-9.0

Vee= 5.0 V, VF= -3.0 V, V00 = -13 V

mA
mA
mA

Vee= Vcex = 4.75 V, V00 = -13 V
Vee= 5.25 V, V00 = -15 V, V1N = -10 V
Vee= 5.25 V, V00 = -:15 V, V1N = 0 V
Vee= 5.5 V, V00 :i::: -15 V
Input open or gnd

mA
ns
ns

Vee= 8.0V, V00 = -20V, V1N = OV
Vee= 5.0V, V00 = -13 V
See Figure 4

POWER DISSIPATION VERSUSAMBIENT TEMPERATURE

SWITCHING TIME VERSUSAMBIENT TEMPERATURE-Kl

MAX V!l..THRESHOID

1----1 -ff-

TYP ~THRESHOLDTYPVIH THRESHOLD

120 1---+--t--+---t--+--+--+---i

ie~-

l 1
__ _, --1----1 -- -~H- --80 ~-lYP.

~ IOt---+--+--+-----+-+---+--+-~

-2.0

-25

ff
0

25

SO

75

IOO

--l;:.::.:=

tpd+TYP.

Mlj_ VIH THRESHO_t-55- ::::F1-55

125

TA· AMBIENT TEMPERATURE· °C

-25
0
25
50
75
TA - AMBIENT TEMPERATURE - °C

100

~1---+--t--+---t--+--+--+---i

125

-55

-25
0
25
so 75
TA - AMBIENT TEMPERATURE - °C

100

125

SWITCHING TIME TEST CIRCUIT AND WAVEFORMSREP RATE= 500 kHz
AMPLITUDE= - JO V
PULSE WIDTH= 1.0 µst,, t, = 20 ns

V1N

Vee

tpd--i IR
PULSE.
GENERATOR

~

9625

Your

I 15pF

Your-\

CONDITIONS

TESTS
tpd +, tpd -

-\

TA
("C)

Vee
(Volts)Yoo(Volts)

R
(kn)

25

5.0

-13

3.75

Fig. 4f--6.0V~

j--tpd +f--1.5VCJJL 9958
DECADE COUNTERCOUNTER MICROLOGIC® INTEGRATED CIRCUITSGENERAL DESCRIPTION

The C µ.L 9958 is a complete Decade Counter consisting of four

cascaded binary triggered flip-flops modified by a feedback loop to count in the familiar
8-4-2-1 code. Provision is made for clearing and presetting any one of the possible decimal

PHYSICAL DIMENSIONS(SIMILAR TO T0-5)

states. The monolithic structure employs only resistors and transistors and is manufactured
with Fairchild Planar* Epitaxial process to assure maximum performance and reliability.
The Decade Counter is designed to operate in the 0° to +75°C temperature range with nominal
power supply voltage of 3.3 to 5.5 volts. It is also available in the -55°C to +125°C temperature range with power supply voltage of 4.0 to 4.4 volts.
The Cµ.L9985 is available in the hermetically sealed 14 pin Dual In-line ceramic package, andin the 8 pin modified TO- 5 metal can.
ABSOLUTE MAXIMUM RATINGS (Note 1)-55°C to +150°C

storage Temperature
Voltage at pin 7 (0°C 14 on Dip (0°C to +75°C)+6.0V

Count Input Pin Voltage+4.0 v, -2.0 v

Reset Input Pin Voltage+4.0 V, -2.0 V

Current into Each Output Terminal±5.0 mA......
NOTES; Dimensions as per latest JS·lO committee.
All dimensions in inches

Leads are gold·plated kovar
Package weight is 1.12 grams.

(PRoqpcr CODE' U58995879X)

ELECTRICAL CHARACTERISTICS (25°C Free Air Temperature unless otherwise noted)

Parameter

Min. Typ. Max. Units

Supply Voltage

3.3

Conditions
TYPICAL DUAL IN-LINE PACKAGE

5.5Count Input-High

1.2

v
v

Count Input Pulse Width-High

150

ns

Count Input-Low

0.45

V/ µ.sCount Input Slope-Positive Going 1.0
Maximum Count Input Frequency
Reset Input-Low
Reset Input-HighPower Consumption

MHz

0.45

v
v
v
v

1.2

Output-Low
Output-High

2.0

0.35
1.4

I
out
I
out

vcc = 4.0 v
vcc = 3.• 6 v
vcc = 4.0 v= 0.4 mA
= -0.7 mA

mW

140

Count Input Impedance

2 k fl in series with a transistor base-emitter diode

Reset Input Impedance

300 fl in series with a transistor base-emitter diodeMaximum Delay from Count Input
to z8 Output(count 7 to 8)

300 ns (Loaa: · 2 k fl parallel with 50 pF from each
output to ground)l.Le11dsareinlendedforinsertioninholerowson.300"centers. Theyare-

purposelyshlppedw1ttt'positive"!.350\misat1a:nmenttcifacilitatei11sertion
2.eo.,d·dr1Uintdimensionsshouldeq11•lyourpracticeforaconwenlional.020
Inch diameter lead.

(PRODUCT CODE, U6A995879X).::..

*Planar is a patented Fairchild process.
NOTE:(1) These ratings are limiHng .values above which serviceability of unit may be impaired.

FAIRCHILCSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

4-23

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD COUNTING MICROLOGIC®INTEGRATED CIRCUITS CµL9958

RESET/PRESET

The circuit is reset to count 0 (all outputs high) with a high level at the reset input pin.
To preset an arbitrary count:
1. Reset to count 0 and then return the reset pin to a low level.
2. Ground (below 0.45 V) the appropriate outputs.

TABLE OF OUTPUT STATES

T0-5 CONNECTION DIAGRAM(Top View)

COUNT(H=High, L=Low)

0 1 2 3 4 5 6 7 8 9

Zs
Z4

+vcc

Z2

RESET

Z1

COUNT

Z1 H L H L H L H L H L
Z2 H H L L H H L L H H
Z4 H H H H L L L L H H
Zs H H H H H H H H L L

GND

14 PIN DUAL IN-LINE
CONNECTION DIAGRAM(TOP VIEW)OUTPUT WAVEFORMS

COUNT
0
1

14

Zs

2

13

Z4

3

12

Z2

4

11

Z1

5

10

6

9

7

s

GND

Vee

2

3

4

5

6

7

8

9

COUNT
INPUT

RESET

.::
"Cl

'>
"'
COUNT

Zs
lµs/div

4-24

FAIRCHILD COUNTING MICROLOGIC®INTEGRATED CIRCUITS. Cul.:9958
SCHEMATIC DIAGRAM
OF DECADE FLIP-FLOPBLOCK DIAGRAM

Yee

Zs

Z2

TYPICAL ELECTRICAL CHARACTERISTICS

COUNT INPUT
CHARACTERISTICRESET INPUT
CHARACTERISTIC

0,5

~
_Jf

0.4

u 1---1--+--+---+--+-+..L1---1

~t

1(1'

1i 1.01--4---+--+---<l---+H'../"~---I

lh

i O.l

i

~"

1--I-~~~...!!ire!: 0.2~ o. 6~vi

oi......_...L.....l.'.fL..L~L-...1..-~

0.2

0,4

0.6

0.8

1.0

1.2

VIN - INPUT VOLTAGE - V

OUTPUT CHARACTERISTICS!OUTPUT LOW!

POWER SUPPLY CURRENTVERSUS SUPPLY VOLTAGE

b---:-:

-

12::

cz:J
i--

~

-

i!1

~

~ 33

·~~ i...--........~ .ft--

1.4

44

IL.

~
v
v
200

0

V1N • INPUTVOLTAGE -V

Yee· 4.ovv

Jl/0,21--1--1--t-//JHl--+--+---1

0.2 0.4 0,6 0.8 1.0 1.2 1,4 1.6 1.8 2.0

lOO

1---+--t---+---tV-+Ht-ffl-T--'1

~0.4

L.'f

0.1

0.11--+-+--+---+-]-+if//-H-t---1

~

i

v

_8
4-4
Vee - SUPPLY VOLTAGE - VOLTS

0loUT - SINKING CURRENT - MA

4-25

,_,

FAIRCHILD COUNTING MICROLOGIC® INTEGRATED CIRCUITS CuL9958
LOADING RULES
DRIVING DEVICECAN DRIVE

AT Vee OF

CµL995S:z1, z2' Z4

3.3 Min.

1CµL9959

Zs

3.3 Min.

1 C µL9959 plus 1 C µL 995S
Count Input

zl' Z2' Z4

4.0 Min.

2 CµL 9959

ZS

4.0 Min.

2 C µL9959plus 1 C µL 995S
Count Input

z1, z2' Z4

4.0 V Min. and one 390 Q current limiting
resistor in series with each output

4 CµL 9959

Zs

4.0 V Min. and one 330 Q current limiting
resistor in series with Zs output

4 C µL9959plus 1 C µL 995S
Count Input

zl, z2' Z4

3.3 Min,

1CµL9960

Zs

3.3 Min.

1 C µL9960plus 1 C µL 995S
Count Input

z1, z2' Z4

4.0 Min.

2 CµL9960

ZS

4.0 Min.

2 C µL9960plus 1 C µL 995S
Count Input

zl' z2, Z4

4.0 Min. and one 330 Q current limiting
resistor in series with each output

5 CµL9960

Zs

4.0 Min. and one 270 Q current limiting
resistor in series with Zs output

5 C µL9960plus 1 C µL 995S
Count Inputs

Industrial Range
Milliwatt RTL :3.6V±l0%

1 C µL995SCount Input

Industrial Range RTL :3.6V±l0%

6 C µL995SCount Inputs, or 1 C µL 995S
Reset Input

Industrial Range DTL
6k Family:

4.5 Min.

Industrial Range DT L
2k Family:

4.5 Min.

1 C µL995SCount Input
3 CµL995SCount Inputs, or 1 CµL995S
Reset Input

CµL 9958 FAN-OUT VERSUS Yee
AND SERIES LIMITING RESISTORS/ / FANOUT/ / FANOUT
330

7

390
/

SERIES
LIMITING 560
RESISTOR

L 4//7 3 /

L

72/

750
/

0

/

/

/

/

270

pl LOADS

Z1

/

/

/

Zz

/

/

Zs

/

330

RUM

SERIES
LIMITING 390
RESISTOR

/

RuM

560

/:3

~8

4.0

l!-s

/

~

~.3

MIN Yee///: 5 / /
"/
/

-,,

/

J./

~-/

/
/

3.5

]3.~
MIN Yee

4-26

/

/IN
/:&-/ /INDUSTRIAL//: 4 / /
/

0

j3.5

7

RUM

/
/

/

~.3

RLIM

Z4

/

/

l /

/

/IN
// 5 "INDUSTRIAL

~·~

~5

pl LOADS

·CµL9959
BUFFER - STORAGE ELEMENTCOUNTING MICROLOGIC®INTEGRATED CIRCUIT

GENERAL DESCRIPTION-

The C µ.L 9959 Buffer-Storage unit consists of four gated-latch circuits,
PHYSICAL DIMENSIONS

and a common: gate driver, diffused into a single silicon substrate. Information which is present

Cf.IL PACKAGE OU:ruNE

at the four data inputs enters the latches throughout the interval of a loaq command applied to thegate input terminal. With gate high, information is stored until a subsequent load command
permits a change.
The unit haS eight·output terminals (both true and complement for each storage position).

.200MAX.

RULES FOR USE OF CµL9959

The principal intended use of the Cµ.i.9959 is with industrial and ground support system13, with
operating VCC from 3.3 to 5.0 volts, and from 0°C to +75°C ambient temperature. This temperature range niay be extended to -55°C by raising minimum VCC to 4,0 Volts or it may be
extended to +125°C by lowering maximum VCC to 4.4 Volts.

ABSOLUTE MAXIMUM RATINGS (Note 1)

Storage Temperature-55°c to +150°c

Supply Voltage (0°C to +75°C)

6.0 v+4.0 v, -2.0 v·Gate Input and Data Input Pin Voltage
Current into Each Output Terminal

NOTES,
1. Le.ds ere intended for insertion in hole rows on.300" centers. They •re purpo11ly shipped with"'positive" (.350) m111111nmtnl to f1c1htet1 insertion.
2. Board-drilling dlmen11on1 should equ1I yourpractice for a convenllonal .020 hnch diameter Ind.

+15 mA+6.0 v, -0.3 v

Voltage Applied to an Output Terminal

ELECTRICAL CHARACTERISTICS (25°C Free Air Temperature unless otherwise noted)

Characteristic

Min.

Typ.

Max.

Units

Supply Voltage

3.3

3.8

5,0

v

Conditions

Power Consumptj.on

115

mW

3.8

v

Gate HighPower Consumption

135

mW

3.8

v

Gate.Lpw

Gate Input Highl.1

v

Gate Input Low
Data Input High

v

0.5
1.0

v

Data Input Low

0.5v

Output Low

0.4

v

IOUT

3.0

mA

v

IOUT

10

mA

VOUT

1.5

v

Output Low

0.6

Load Current
Max. Sampling Rate

-0.4

mA

Sampling Pul.s4:! Width (Gate)

100

MHz
ns

>5.0

• vcc
• vcc

5.0 v

-. 3.3 v

NOTES:(1) These ratings are limiting values above which severiceablllty of unit may be Impaired.

l=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNiA, (415) 962-5011, TWX: 910-379-6435

4-27

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATION

.. · FAIRCHILD COUNTING MICROLOGIC® INTEGRATED CIRCUITS • CIJL,9959

TRUTH TABLEBLOCK DIAGRAM

GATE

I

z

z

L

L

L

H

L

H

H

L

H

ANY

Q

Q

H =HIGHGATE

I8

L =LOW

Q = THE STATE ASSUMED PRIOR
TO "GATE HIGH" IS MAINTAINED.

16 PINDUAL IN-LINE PACKAGE(TOP VIEW)

TYPICAL APPLICATION+V

0123 45 67 89
GATE

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

9

GAS FILLEDREADOUT

Citi.9960

Citl.9959----o
C1tL9958

INPUT

4-28

l

COMPLEMENTARY
1-2-4-8 OUTPUT

CARRY

.: FAIRCHILD COUNTING MICROLOGiC® INTEGRATED CIRCUITS "CJ,tl.9959
SCHEMATIC DIAGRAM OF BUFFER STORAGE UNIT
Za

Za

r- -------------------------- ,
I

Zb

I

r~l __ l_,I

Veeo-----------------+----------------~-------------------_.,..----11
3.6k

1.lk

1.lk

2k

3.6k

2k

!}
I

FFb

L=--r ____
Zc

0.7 k

lk

Zb

r~l

lb

I

J

-=-·

Zc

___l_,
I

O.Sk

FFc

l ___
.

L___

GATE

!JI
I

_J

le

._

-

Zd'

Zd

r_I ___ I_,
FF a------------ ------ ---------

~---

GND
, oo----

1la

PROPAGATION DELAY
4.0 v

Vee
la
eitL9959

Ia
GN.D lb

Za.
le

Id'

':"

2.0 v
Delay from data Input to Output (Gateinput low)

>

....c

TEST POINTS
Delay from Gate Input to Output

'•
Za

::

z.
50 ns/Oiv, 4-29I~--~~·
Id

GATE

___J1
.

-:-

. FAIRCHILD ccfUNTING MICROLOGlC® INTEGRATED CIRCUITS ; Cl}L.9959
TYPICAL ELECTRICAL CHARACTERISTICSOUTPUT CHARACTERISTIC!OUTPUT LOW>

TRANSFER CHARACTERISTICDATA INPUT CHARACTERISTIC

1.0.------.----.,..----.----.

vcc·4JJV
vcate•ov

vcc·4.ov
VGate • 2.0V

Vcc·4.ov
0.751----t--'-+-----t----1

0.751----+----+---+----iT• +2S°C

o.___.....__

0

0.5

0

GATE INPUT CHARACTERISTIC

1,0

1.5

2.0

__,__

__._

v 1N-Volts

1ou1 - mA

TRANSFER CHARACTERISTICOUTPUT CHARACTERISTIC!OUTPUT HIGH!

Vcc."•.ov
Vca18•0V
T· -ss•cT• +l25°C. ~ 0.501----+--+--fl---A-1'-+-l---lJ!'

0 o.,__

0_..,.__.o..<-1.L...o---'1.-5---'2.00

VG -Vons

0.5

uo

1.5

2.0
1our - mA

VIN - VOLTS

LOADING RULES FOR CµL9959

Driving Device

At VCC of

9959

3.3 to 5.0 V

2 9960 inputs ts

9959

3.3 to 5.0 V

4 Low Power RTµL loads

9959

3.3 to 5.0 V

1 RTµL load

9959

3.3 to 5.0 V

2 DTµL loads

9958

3.6 to 4.0 V

2 9959 data inputs

Full Range J..ow Power RTµL

4.0 V Min.*at -55°C

3 9959 data inputs or 1 9959 gate input

Industrial Range Low Power RTµL

3.6 v ±10%2 9959 data inputs

Full Range RTµL

3.0 ±10%10 9959 data inputs or 3 9959 gate inputs

Industri!l.l.R11,nge RTµL
Full Ra~e DT µ. L.
6 KFamily.3.• 6±10%

13 9959 data 1nputs or 5 9959 gate inputs ·. ' 4.5V Min.

2 9959 data inputs or 1 9959 gate il).prit

4.5 V M:in.

6 9959 data inputs or 2 9959 gate inputs

I

Full R.ange DT µ,L
2 K Family__.

0

Can Drive:*See Low Power RTµL data sh_eet fqr details~-~· ·, . ' ..

4-30

CµL9960
DECIMAL DECODER/DRIVER
COUNTING MICROLOGIC® INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The CµL 9960 Decoder /Driver is a monolithic .silicon circuit
which accepts 1-2-4-8 binary coded decimal inputs at integrated circuit signal levels and produces ten mutually exclusive outputs which can directly control the ionizing potentials of
many gas filled cold cathode indicator tubes. The CµL 9960 is designed specifically for use

PHYSICAL DIMENSIONSC~L PACKAGE OUTLINE

with the CµL 9958 Decade Counter or CµL 9959 Buffer-Storage, but can be used with otherintegrated circuit types. Only true values are required as inputs thereby simplifying the con.200 MAX.

nection with counters or other information sources.

[~
NOTE (1)RULES FOR USE OF CµL 9960
The principal in.tended use of the CµL 9960 is with industrial and ground support systems,
from o•c to +75°C ambient, and with operating Vee from 3.3 to 5.5 volts. The lower limitof the temperature range may be extended to -55°C by raising the minimum Vee to 4.0 volts.
ABSOLUTE MAXIMUM RATINGS (Note 1)
Storage Temperature-55°c to +12s·c
o·c to +75°c

Operating Temperature
Supply Voltage (0°C to +75°C)
Input Voltage
Current into each Output Terminal (In the ON State) ·

loL
loH

Symbol
Vee
Po
VrH
VrL
VoL
VoH
lco

1. Leads are intended for insertion 1n hole rows on.300" centers. They are purposely shipped with"positive" {.350) misalignment to facilitate Insertion.
2. Boa'fd-drilling dimensions should equal yourpractice for a conventional .020 linch diameter lead.

15 mA

Current into each Output Terminal (In the OFF State) (Notes 2 and 3)

ELECT~ICALNOTES'

6V+4'V, .:..2V

PRODUCT CODE: U6B996079X

0.6mA

CHARACTERISTICS (25°C Free Air Temperatu.re unless otherwise noted)
Characteristic

Min.

Power Supply (Note 4)
Power Consumption
Input High

3.3

Input Low
ON Output Voltage (Note 2)
OFF Output Voltage
OFF Output Leakage Current

Typ.

Max.
5.5

Units

v
mW

45
1.0
0.4
4.0
55
50

Test Conditionsvv
v

Vee= 4.0 V Input Highv

V1H =. 1.0 V, loL = 3 mA
loH = 0.2 mAµA

Vour = 50 V

NOTES:(1) These ratings are limiting values above which serviceability of unit may be impaired.
(2) Outputs in the OFF state. l\,lust not be left floating, they should be tied to Vee through 10 k!l if they are not connected to the cathodes of a readout tube.
(3) Total current through all 9. outputs in the OFF state must not exceed 1.5 mA.
(4) For operation using gas filled re.,pout tubes requiring 6 to lOmA ON current, Vee Min.= 4.0 V.

F=AIRCHIL..CJ
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

4-31

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD COUNTING MICROLOGIC® INTEGRATED CIRCUIT- Cµ.L9960

TYPICAL ELECTRICAL CHARACTERISTICS

ON OUTPUT CURRENTVERSUS OUTPUT VOLTAGE

INPUT CHARACTERISTICS

'

IO

8
0.31---+--+--~~---t8z:: o.21---+--+---1l!ll------t---1

4

1·

t7

.

I

2

~

~

.~

u

: V1N~·vous

~

~

0

OFF OUTPUT CURRENTVERSUS OUTPUT VOLTAGE

7?- 4001---+-'--+--r-.,-i--+--;!i!~,___-+---+~-+-+-+--,-<~5200>-----+-~-+--+---<t--t----t

j_
0

0.5
1.0
1.5
2.0
. VOL ·OUTPUT VOLTAGE ·VOLTS

0o

2.5

20

40

60

80

100

VoH ·OUTPUT VOl..TAGE-VOl.'ts

TRUTH TABLE
With the coding shown in the table only one of the outputs will be low or On at any time.

1,

'2
1.
1,
ON
Output

H
H
H
H

L
H
H
H

H
L
H
H

L
L
H
H

Zo

z,

z.

i,

L
H

L
H
L
H

H
L
L
H

L
L
L
H

z.

Zs

z.

z,

H
H'

H'
H··

H

H
L

H
L

z,

z.

•,

L

L=Low
H=High

16 F'IN DUAL IN-LINE PACKAGE(Top View)

BLOCK DIAGRAM

zo Z1 Z2 Z3 Z4
Zg

1

16

Vee

z.1

2

15

14

Z5 Z5 Z7 Zs Zg

-..,

I
I
I
I

I
I
I

Z5

3

14

Is

Z3

4

13

Zs

11

Z1

5

12

Z&

12

11

6

11

Z4

12

7

10

Z2

9

Zo

I
.I

DECODERMATRIX

14

Is

GND

I

L-------------------------------~
·'

.4-32

FAIRCHILD COUNTING MICROLOGIC® INTEGRATED CIRCUIT-Cµ.L9960

TYPICAL APPLICATIONS+V+V

0123 4567 89

GAS FILLEDREADOUT

0123 45 67 89

vcco---- CµL9960

GAS FILLEDREADOUTCµL9960CARRYlCOMPLEMENTARY.
1-2-4-8 OUTPUT

GATE

---.g

INPUT

CARRY

CµL995S

INPUT*The CS£L996() is ·suitable for·driving all commercial available numeric gas filled readout tubes in which ON
Cathode current does not exceed lOmA and total OFF Cathode leakages do not exceed 1.5mA.
The Values ofand R may be chosen following the readout tube manufacturers' specifications.

+v

LOADING RULES FOR CµL9960
Driving Device
CµL9959
CµL9958

At Vee of
3.3 to 5.•5V
3.3 to 5.5 V

Industrial Range Milliwatt RTL
Industrial Range RTL
ln.dustrial Range OTµL
6K Family·
Industrial Range DTµL
2K Family

3.6 v ±10%
3.6 ±10%

2 CµL9960 inputs
1 CµL9960 plus 1 CµL9958

4.5V Min.

Count Input
1 CµL9960
6CµL9960
1 CµL9960

4.5VMiri.

3 CµL9960

4-33

CµL9989
4-BIT BINARY COUNTERCOUNTING MICROLOGIC® INTEGRATED CIRCUITSGENERAL DESCRIPTION - The CµL9989 is a Ripple Counter using 8421 binary weighted count sequence
consisting of four cascaded binary triggered flip-flops. Provision is made for clearing and pre-setting any one

PHYSICAL DIMENSIONS(T0-99)of the possible binary states. The monolithic structure employs only resistors and transistors and is manu. factured with Fairchild Planar* Epitaxial process to assure maximum performance and reliability.
The CµL9989 counter is designed to operate in the 0°C to 75°C temperature range with nominal power
supply voltage of 3.6 to 5.5 volts.
The CµL9989 is available in the hermetically sealed 14 pin Dual In-Line ceramic package (T0-116), and in
the 8 pin modified T0-5 metal can (T0-99).

ABSOLUTE MAXIMUM RATINGS (above which useful life may be impaired)
Storage Temperature-55°C to +150°C

Voltage at pin 7 (0°C to +75°C) (T0-99)
Count Input Pin Voltage
Reset Input Pin Voltage' ·+6.0V+4.0 V, -2.0 V+4.0 V, -2.0 V±5.0mA

Current into Each Output Terminal

NOTES' Dlmen1ions as per latest JS·IO committee.
All dimensions in lnchet.
Lelldseregold·pl•teGko111r.
Po1ekage weight ls0.95 arams.

(PRODUCT CODE U5B998979X)

ELECTRICAL CHARACTERISTICS (0 - 75°C Free Air Temperature unless otherwise stated)
PARAMETER

MIN.

TYP.

MAX.

UNITS

5.5
385

Volts
mW
mW
Volts
Volts
µA
ns

CONDITIONSTYPICAL DUAL IN-LINE PACKAGE(T0-116)

Supply Voltage-Vee
3.6
Power Dissipation
Power Dissipation
Count lnput-Low-V1Le
Count lnput-High-VrHe
1.2
Count Input Current
Count Input Pulse Width-High
40
Count Input Slope-Positive Going
Max. Freq. of Input Count Pulses
10
Reset I nput-Low-V1LR
Reset lnput-High-V1HR
Reset Input Current
Reset Input Pulse Width-High
Output-Low__;_Vm
Output-High-V0H
Max. Delay From Count Input
To Zs Output

300
132

0.45
210

330

v/µs

1.0
15

MHz
0.45

1.2
1.45
220

2.30

0.45
1.2
90

120

Volts
Volts
mA
ns
Volts
Volts
ns

See Loading Rules
Vee= 5.5 Volts, 25°C
Yee = 4.0 Volts, 25°C
75°C
25°c
25°C, V1He = 1.2 Volts
25•c
25°C
ZI' Z2, Z4, One Standard LoadZs, Two Standard Loads
75°C
25°C
25°C, V1HR = 1.2 Volts
Zp Z2, Z4, One Standard LoadZs, Two Standard Loads, Vee = 5.5 Volts
Vee = 5.5 Volts, 10L = 0.4 mA Load
Vee= 3.5 Volts, 10H = -0.7 mA
Yee= 4.0 Volts, ZI, z2' Z4 One
Standard Load, ZsTwo standard Loads 25°C

I. Leads ue 111ttndad for ms1rt1on m hole row$ on .300" center1 Thay are
purposelyshlppedw1ttt'pos1t1ve''(.3~0)m111hgnmenttotee1l1t1te1nse111on.

2.Board·dr1ll1n1d•man11onssho11ldequa1yourpr1cbceforaconunt10n•I 020"'chd••rneterlead.

(PRODUCT CODE U6A998979X)•Planar is a patented Fairchild process.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

4-34

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD COUNTING MICROLOGIC® INTEGRATED CIRCUITS Cµ,L9989
SCHEMATIC DIAGRAM
Zl

COUNT

Z4

Z2

ZS

RESET

14 PIN DUAL IN-LINE
CONNECTION DIAGRAM(Top View)

LOGIC DIAGRAM

T0-99 CONNECTION DIAGRAM(Top View)

Zs
RESET

1

COUNT

Z1

Z2

Z4

Z8

14

Zs

2

Z4

3

12

Z2

4

11

Z1

5

10

6

9

7

s

GND

z,

2 3

RESET

COUNT

Z4

+Vee

Z2

RESET

Z1

COUNT

GND

INPUT/OUTPUT WAVEFORM

TABLE OF OUTPUT STATES

0 1

Vee

COUNT (H = High, L = Low)
4 5 6 7 8 9 10 11 12 13 14 15

H L H L H L H L H L H L H L H L

Z2 H H L L H H L L H H L L H H L L
Z4 H H H H L L L L H H H H L L L L
Za H H H H H H H H L L L L L L L L

RESET/PRESET
The circuit is reset to count 0 (all outputs high) with a high level at the reset input pin.
To preset an arbitrary count:

1. Reset to count 0 and then return the reset pin to a low level.
2. Ground (below 0.45 V) the appropriate outputs.

4-35

FAIRCHILD COUNTING MICROLOGIC® INTEGRATED CIRCUITS Cµ.L9989

TYPICAL ELECTRICAL CHARACTERISTICS

POWER SUPPLY CURRENTVERSUS SUPPLY VOLTAGEOUTPUT VOLTAGE-LOW
VERSUS SUPPLY VOLTAGE.

loL•0.4 mA~ 1.s 1---+f'.-..-"'!Nc----1--10_·H-+'-_o._1m-A+----i

e

....I

~

OUTPUT VOLTAGE-HIGH
VERSUS TEMPERATURE
1. r .---.--.---.---,1.--_-.--I-,.,~!--"....+--+--+ Vee•3.5V _

50

~

0:
0:

:c

~ 1.51---+---+--+---+-""'"".,+---;
~

:::>

..

"'~ 40~~g~~~ 1.41---+---+--+--+--I---;

~

>'ff,

ii!

..,
0:

I.,

1. 3 0~-..l..---:!2'=-5-+--::500---'----:!75
Yee-SUPPLY VOLTAGE-V(ll.TS

OUTPUT CHARACTERISTICS(OUTPUT LOW)

Vee-SUPPLY VOLTAGE-VOLTSAMBIENT TEMPERATURE -'C

COUNT INPUT
CHARACTERISTICRESET INPUT
CHARACTERISTIC

0.5-.--.--.--.--.--.--.--.--~...-7"0J,.,.

o.4 ~t-t-t-t---,-t-t-rgf'751H

~ O.l

~

~ 1--+-+-+-+--+-~~~<:i-+f!!

rz~
~

0.2

~ o.11-t-t-t-hw'14f---t--t--t--t--IJ,"

1i 1,0 t - - - t - - t - - - t - - t - - - t t - T I

i 0,81---+----l--+--+-'l-IH--+----!
~

l 0.61---+----l--+--+-++.ll---+----!
!!
~~ 0.40.21---1----1--+-+H-+--+----!

oi....i.....i...~A~-L-L-L-L-L~

2<1l ' - - - - ' - - - ' - - " ' - - - - - ' - - ' - - - '0louT - SINKING CURRENT • MA

oi.......i..._.~~rL..L-J.,--L-,J

0 0,2 0.4 0.6 0,8 1.0 1,2 1.4 1.6 I.I 2.0

PROPAGATION DELAY..;,..tpd ·VERSUS SUPPLY VOLTAGE

1....--.---.----..,,---,

0.

f 25

i§

T••25'C~ii~l~••O'C
I 706...+-".-==!-...---l~.,.::...::+--+---i>---!

!5

80

o.

!

J

~23~-l--+--1-t-:::;l.o-"""f=-j--1~221--t..-"'1"''-t-.,_-t--+.,.-J=--i821~+-+==*.......~+-+-l--1

60l---+--l---l~Zl~,Z~2~&~Z~4-~1+.Sro=.~L~M....-ID
Z8 -2 STD. LMDS
so~_,__,___._..__~~~~
3.5

4.0
4.5 .
5.0
Vee-SUPPLY VOLTAGE-VOLTS

1.0

1.2

1.4

260

~24"'""'+--+--+-+---+--1---1--!

i.

0.8

RESET PULSE WIDTHVERSUS SUPPLY VOLTAGE~ 1oo~:i:V~~-l-I+-+-+-+---d!i 90 ~++-I,-::.
~]-"'t=;....+-if--1
~
~

0.6

COUNT PULSE WIDTHVERSUS SUPPLY VOLTAGE

120 t---+--+--+-t--t--+-::;;l........i

T••7~

0.4

VIN - INPUT VOLTAGE - V

130 .---.---.---.-

j' 110 ~+-+--l=--~+-+-lf--1

0,2

VIN - INPUT VOLTAGE - V

.i
..e

220

:c

190

y

!I .

~ 140

~

0:

100

60

~

u

5.5
Vee-SUPPLY VOLTAGE-VOLTS

4-36

kd

L'.'.Jv[2'£Zl, Z2 & Z4-1 STD. LMD
Z8-2 STD. LOADS

4.0

4.5

5.0

Vee-SUPPLY VOLTAGE-VOLTS

5.5

FAIRCHILD COUNTING MICROLOGIC® INTEGRATED CIRCUITS CµL9989
LOADING RULES··.

DRIVING DEVICECAN DRIVE

AT Vee RANGE OF

CµL9989z" z2' z4Open
1 Standard Load

3.6 to 5.5 Volts

1 Standard Load
2 Standard Loads

4.0 to 5.5 Voltsz" z2' z4z8

2 Standard Loads
4 Standard Loads

5.0 to 5.5 Volts

Industrial Range
Milliwatt RTL

1CµL9989 Count

3.6 to 3.96 Volts

Industrial Range
RTL

6 CµL9989 Count
1 CµL9989 Reset

3.6 to 3.96 Volts

Industrial Range
DTL6K Family

1 CµL9989 Count

4.5 to 5.5 Volts

Industrial Range
DTL 2K Family

3 CµL9989 Count
1 CµL9989 Reset

4.5 to 5.5 Volts

Za
CµL9989

Z" Z2 , Z4
Za
CµL9989

One Standard Load, worst case, is defined for testing
purposes as shown in the figure below.

The following are defined as One Standard Load:
CµL9989 Count Input
CµL9958 Couiit Input
CµL9959 Data Input
CµL9960 Data Input
LP-RTL GATE INPUT

1.5 k.O.
16 pF
FD 6004-37

-C-T1.1L9952
DUAL 2-INPUT NOR GATECOMPLEMENTARY TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS+15°C TO +55°C TEMPERATURE RANGE

GENERAL DESCRIPTION-The CTµL 9952 Dual 2-lnput Inverter Gate provides logic gating at its input
and output terminals. Compatible with all other CTµL elements, the output can be tied to any otherelement to perform the wired OR function.

TYPICAL DUAL IN-LINE.PACKAGE
in accord with JEDEC (T0-116) outline

The 9952 may be used to set and restore the system logic levels; having a high noise immunity, it
can drive and be driven by a number of cascaded CTµL AND-OR gates. The following data, stressing
worst case conditions, plus 100% testing by Fairchild Semiconductor, will assur.e the dl!Signer ofproper worst case performance in his own system.
The CTµL 9952 is designed for general purpose industrial and commercial usage where high speed
logic is required. It is p;ickaged in the versatile Dual-In-Line* package, which is a hermetically sealed
ceramic package intended for low-cost insertion techniques.

FEATURES• POWER SUPPLIES ARE +4.5 V ::1:10% AND -2.0 V ::!: 10%

l.Lt1d11reln-ndecl1Grln11rtlonlnltol1rowson.300''e1nt1rs. T111y1rt
purposely11!1pp1dwitff'po111i'«'"l-350lmlull1nmenttof1clllt.W1nsertlofl.

• HIGH FAN·OUT CAPABILITY -2.ao1rd·drlHlnt:dim1nslon1shouldequ.lyourprtctlc:efor1conw1ntion...020

12

lnch4l1mflertt1d•+ 1S°C TO +ss•c• TEMPERATURE RANGE -• OPTIONAL PULLDOWN 1.0 k RESISTOR FOR OPTIMUM SPEED• LOW POWER DISSIPATIONCONNECTION DIAGRAM• LOW PROPAGATION DELAY - 7.0 ns TYPICALTOP VIEW• LOGIC SWING OF 3.0 V• HIGH NOISE IMMUNITY> 1.0 V AT FAN-OUT= 12

14 PULL DOWNRESISTOR
Cl-~~,_,_+-ICJ13

12 Vee

GND 5

PURCHASING INFORMATION
POSlrlVE LOGIC F = A+B
G=C+D

Use the ten-letter code U6A995279X for ordering purposes.

NOTE' X = NOT CONNECTED

All units are marked CTµL-995279 and date code unless otherwise specified.

•Fairchild Patent Pending

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE. MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

4-38

A DIVISION OF FAIRCHILD CAMERA AND INSTRl,IMENT CORPORATION

CT11L·9952 COMPLEMENTARY TRANSISTOR MICROLOGIC® IC
SCHEMATIC DIAGRAM
12Yee = 4.SV :t:l0%

ABSOLUTE MAXIMUM RATINGS .

(above which the useful life may be impaired)

INPUT

R1

Maximum Current in or out of a pin.

lOOmA

Maximum Chip Temperature+150°cM.aximum Power Dissipation

1.0 Watt

Maximum Voltage Applied to any Input Pin

10 Volts

Maximum Negative Voltage Applied to any Input Pin-4.0Volts

Maximum Voltage Applied to Output Pin

11
VEE = ·2.0Y ±10%6.0Volts

5<>-j'_GN_Dj_

NOTE: Only one 2-lnput Inverter pte shown.

DC TESTSTEST (at TA= 25"C)

Output ONE Level

LIMITS
MIN.

TYP.

2:35

2.50

CONDITIONS

MAX.I'>LOAD TO

UNITS

Vee

v,,

Volts

4.05V

-2;20Vv,,

F.0. 12l

COMMENTS= 12, Inputs ·to +0.8 V sequentially. Guarantees

Output ZERO Level-0.50.

-0.36

Volt

4.95V

-1.80V

F.O.

=1

Output ONE Level

2.75

2.90

Volts

4.95V

-1.80V

F.O.

=1

Input Current

4.20

5.30

6.86

mA

4.05.V-1.80VN!> load

Output Resistor

1.6 k

2.0k

2.4 k

Ohms

4.05V

-2.20VNo loadInput Pulldown Resistor

0.8k

LOk

1.2 k

Ohms

4.05V

-2.20VNo loadOutput Falling Delay, tu

6

12

ns

4.sov

-2.00V

Output Rising Delay, ti,

8

14

ns

4.50V

= 12
..;;..2.00V· F.O. = 12

input low threshold >0.80 V; and output
ONE level >2.35 V.
Inputs to 1.25 V sequentially. Guarantees
input high .threshold <1.25 V; output
ZERO level < -0.36 V.
Inputs to -0.70 V simultaneously. Guaran·
tees output never more 'positive than 2.90 v.
Inputs fo 3.5 V simultaneously. Guarantees
Input loading <1.5 AND gate loads.
Inputs to -0.7 V simultaneously. (Outputs
to 3.5 V sequentially.) . Guarantees output
OR tie <LO AND-OR gate loads.
ResiStor to 3.50 V sequentially: Guarantees
1. k resistor available for input pulldown is
within 20% of nominal value. · ·· ·See t po Test Cii:cuit

F.O.

Positive Suppiy Current

18.5

30

36.2

mA

4.95V.

-2.20VNo loadNegative Supply Current

6.75

8

14.8

mA

4.95V

-2.20VNo loadSee tp 0 Test Circuit
Inputs to +3.50 V simultaneously. Tests in·ternal resistors to be.:. no more than :± 20%
from nominal. ·Inputs to -0.70 V simultaneously. Test in·
ternal resistors to be no more than ± 20%
from nomi11al.

NOTES: (1) "Maximum" means "no more positive than"(2) f.O. = Fan-Out: F.O. = 12 equivalent to 133 0 to -2.20 V under worst case conditions.
F.O. = 1 equivalent to 2.4 kll to -1.80 V under worst case conditions.

INPUT CHARACTERISTICSTOLERANCE VARIATION
OF. PARAMETERS

AS A FUNCTION OF .
TEMPERATURE. AS A FUNCTION OF .
COLI.ECTOR SUPPLY VOLTAGE

Vee· 4.5v
vEE ·.·2.ov+--+-~-+~1111"--I

VEE." ·2.0V
F.O.• 6-1---+--+-=.:.....+~---+--I

9 l.O F.O. •6>!; 1.0 ,_..'+---+---+-+--+--+---<>=--<>

o~~~~___,~~~~~

0

IIN • INPUT CURRENT·- mA

2.0
4.0
6.0
llN • INPUICURRENT • mA

4-39·

B.O

OL--'--'---'-~'---'-__J'--~

0

1.0

2.0
l.O
4.0
5.0
llN • INPUT CURRENT· mA

6.0

7.0

CTJJL-9952 COMPLEMENTARY TRANSISTOR MICROlOGlC® IC
OUTPUT CHARACTERISTICSTOLERANCE VARIATIONOF PARAMETERS

AS A FUNCTION OF
TEMPERATURE

AS A FUNCTION OF
COLLECTOR SUPPLY VOLTAGE~! t--+---+-+--+---1--+--+--l

!::i

§;

> .2.1~~gg
s 2.41--l--1--1--1--1--µ"'--1~

1.7.___,___,__.....__.1_....__.__L-....J
0

10

20

2' 3 '-o--'--'-10_.___.20_...___J0.___.__.40

40JO

I our - OUTPUT CURRENT - mA'our - OUTPUT CURRENT - mA'our - OUTPUT CURRENT - µA

AS A FUNCTION OF
NEGATIVE SUPPLY VOLTAGE

SCHEMATIC DIAGRAM'our+y,-9952

Your
VIN=-0.7V

o'---'---'--...__.__..__ _,___.___,
10
JO
20
I our - OUTPUT CURRENT - mA

0

40

TRANSFER CHARACTERISTICSTOLERANCE. VARIATIONOF PARAMETERS
l.O

IT

l.O

l.O

Vee· 4.5v
VEE • -2.0V!S§; 2.0

AS A FUNCTION OF
FAN-OUTAS A FUNCTION OF
TEMPERATURE!S

TA· 25°Cg

2.0

Vee· 4.5v

TA•25CVEE • ·2.0V
F.O. •6

F1..1oF.0. • 112~§! 2.0TA• lllO'C

F.O. •6~

TA•O'C

F.d.

Vee • 4.S°C
VEE • ·2,0V

7

TA • 25'C

•6.~/

~

"'>~

> 1.0

~

g

1Pl~LMJIM_j--;.

1.0

~

·"'

vMAXIMUM

.

-1.0

·l.O
1.6
0.8
1.2
0.4
VIN - INPUT VOLTAGE - VOLTS

2.0

0

0.4

0.8

1.2

0

VIN • INPUT VOLTAGE - VOLTS

0.8
1.2
L6
0.4
VIN - INPUT VOLTAGE - VOLTS

2.0_ NOTE: Variation of VEE does not alter transfer characteristics. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -l.O

v~c -l95v
Vee -~11;v!S 2.0
g

Ve-:

"'>~

WORST CASE JUNCTIONTEMPERATURE VERSUS
POWER DISSIPATIONPOWER DISSIPATION VERSUS
POSITIVE SUPPLY VOLTAGE

AS A FUNCTION OF
POSITIVE SUPPLY VOLTAGE
VEE. ·2.ov
F.0.-6_[§ 80 .___,___...__...__...___.____

r •2S'C

!

4.IJ

I

60 .__..._....._......__,_

I!!

°'

1.0

~

~

g

~
~

40----""' 20 I-+-,-¥,.¥-+- il'.:,;:~-f--1--1--l
"~

~
-1.0
0

1.6
0.4
0.8
1.2
VIN • INPUT VOLTAGE - VOLTS

2.0

4.0

4.2
4.4
4.6
4.8
Vee - POSITIVE SUPPLY VOLTAGE - VOLTS

5.0

0.8
0.6
0.4
0,2
POWER DISSIPATION ~ WAHS

1.0

CT1.1L·9952 COMPLEMENTARY TRANSISTOR MICROLOGIC® IC
WORST CASE PROPAGATIONDELAY VERSUS LOADCAPACITANCE AS A
FUNCTION OF LOAD RESISTANCEWORST CASE PROPAGATIONDELAY VERSUS AMBIENTTEMPERATURE~~..--..--....-....--..---..--,---.--.---.

v~~ • 4.~v

2

20

VEE • -2.0V+-+-+-+--1--1--+---t
F.0.•12y

8.0 .__..___,__...__...__.___.___.__.___,____.
0
20
40
60
80
100
TA • AMBIENT TEMPERATURE - •c

20

40
60
80
CL - LOAD CAPACITANCE - pF

tpo TEST CIRCUIT FOR ABOVE

tpo TEST CIRCUIT
•cc

•cc

OUTPUTOUTPUT•••

Yee= 4.SV
Yee= 4.SOY

VEE= -2.0V

VEE= -2.00V

TA=2s·c

TA= 2s·c

APPLICATION INFORMATIONThe electrical specification tests performed under the conditions set, emphasize the worst case results and should be considered as conservative limits.
Throughout this data sheet, WORST CASE should be interpreted as using power supplies, internal resistors, transistor parameters and external loads
having extreme loads chosen in a manner to guarantee proper operation under worst case conditions.
LOADING RULES: Each input to the CTµL 9952 represents 1.5 unit loads.
(One unit load is defined as an input to the CTµL AND-OR gate.)a) Connecting the 1.0 kn pulldown resistor to the input adds two unit loads to the fan-in.
b) Connecting the 1.0 kn pulldown resistor to the output reduces the fan-out by two unit loads.
c) Each wired-OR connection reduces the fan-out by one.
PULLDOWN RESISTOR: Two pulldown 1.0 kn resistors are built into the package with one end tied to the negative power supply (Vee). Connecting the
1.0 kn resistor to the CTµL 9952 input will improve the turn.off characteristics and speed up the output rising propagation delay. When the input of theCTµL 9952 is driven by four or more AND-OR gates, there is no advantage in connecting the 1.0 kn resistor to the same input. The pulldown resistor
may also be connected to the CTµL 9952 output. This will improve the output falling propagation delay when low fan-out is used.
WI RED OR: A powerful feature of the CTµL 9952 inverter is that the output may be tied together with the output of any other element in the CTµL
family to form the positive OR function at the tie point, thus achieving two logic functions without additional propagation delay.
INTERFACING: The CTµL 9952 inverter gate serves as an excellent interfacing link between external signals coming from other logic forms or peripheral
equipment and the CTµL family.
NOISE IMMUNITY: The CTµL 9952, having excellent noise immunity under maximum loading and worst case conditions, is used primarily to restore logic
levels degraded after passing through several CTµL AND-OR gates.
HIGH SPEED CONSIDERATIONS: The high·speed logic operation available using CTµL requires that care be exercised in packaging and interconnection
techniques. Normally logic circuits using emitter followers as drivers have a tendency to oscillate when driven by high·speed pulse signals. Each CTµL
9952 includes a clamping network so designed that it reduces ringing at high·speed operation. These features eliminate the necessity for the use of strip
lines or coaxial cables for all but the longest lines. However, care must still be exercised in the layout of printed circuit boards. Any one line over 12" inlength tied to a gate output should be terminated in a 200 n resistor to ground. Such a 200 n resistor approximates the characteristic impedance ofthe back panel wiring and is considered equivalent to a fan.out of 4.
SHORT CIRCUIT PROTECTION: The CTµL 9952 inverter gate output is protected by a limiting resistor at the output and may sustain prolonged shortcircuit to ground with Vee not greater than 5.0 V. Excessive destructive heat may develop when more than one output in a single package is short circuited to ground. In general, short circuiting the output should be avoided.

4-41.

CTµL 9953-9955 ·9964-9966 • 9971-9972 AND-OR GATE$COMPLEMENTARY TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS+15°C TO +55°C TEMPERATURE RANGE

GENERAL DESCRIPTION - The Fairchild CTµL AND-OR gate is a PNP-NPN complementary logic circuit which
provides the system designer wit~ the basic tools for designing extremely fast, proven, low cost synchronous
systems.

PHYSICAL DIMENSIONSTYPICAL DUAL IN-LINE PACKAGE
In Accordance WithJEDEC (T0·116)0utline

Tfie following data, stressing worst case conditions, plus 100% testing by Fairchild for a minimum fanout of
11 and a maximum propagation delay of 4.5 nseconds at full fanout at 25°C, will assure the designer ofproper worst case performance in his own system.

1r:~g~The AND-OR gate is basically a cascade connected PNP-NPN complementary non-saturating transistor pair.
The output transistor is an emitter follower having virtually no threshold level. Therefore, there is no delay
in output response due to input charging to threshold voltage, no stored charge to remove, negligible emitterbase transition charge and no collector-base transition capacity multiplication. Thus, typically 3 nseconds
delays are obtainable at full fanout without the necessity of fast rise and fall time. This means conventional
back panel wiring may be used with substantial reduction in inductive and capacitive noise usually generated
by threshold circuits. The emitter follower low output impedance coupled with the high input impedance contributes to the large fanout and exceptional performance in the presence of stray capacitance.

.020 M

200~
AX.

/BE\

NOTE I}- .350 MAX.

--1

.125 lYP.

.090

.110

t

CTµL circuits are packaged in the versatile JEDEC T0-116 DUAL-IN-LINE packages which are hermeticallysealed ceramic units intended for low cost insertion techniques.

I Lead&are1ntendedlor1nurtio111nhol1rowson.3DO"cant1r&. Theyere
piirposely shipped w1tN 'positive" { 350) m1uh1nment to fac1htate m5ert1on
2.B111rd-dnllln1d1mensronsshouldequalyo11rpr1et1ctfor1eonvent1onal 0:20
1nehd1amet9flead.

FEATURES:• Power supplies are 4.5 V :t:10% and -2.0 V :t:l0%.
• High fanout capability• Temperature range +is•c to +ss•c• Low power dissipation• Low propagation delay - 3.0 ns typical• Logic swing of 3.0 V

PURCHASING INFORMATION:
Description
CTµL9953 - 2-2-3 Input AND-OR Gate (three gates in one package)CTµL9954- Dual 4-lnput AND-OR Gate (two gates i.n.one package)CTµL9955- Dual Output 8-lnput AND·OR Gate
CTµL9964- 3-3-1 Input AND-OR Gate (three gates in one package)CTµL9965- Quad 1-lnput AND-OR Gate
CTµL9966 - Quad 2-lnput AND-OR Gate (with three outputs)
CTµL9971 - Quad 2-lnput AND-OR Gate (with two outputs)
CTµL9972- Quad 2-lnput AND-OR Gate (with three outputs, all pull down resistors omitted)

Code

Marking

U6A995379X
U6A995479X
U6A995579X
U6A996479X
U6A996579X
U6A996679X

CTµL95379
CTµL95479
CTµL95579
CTµL96479
CTµL96579
CTµL96679
CTµL97179
CTµL97279

U6A9~7179X

U6A997279X

Use the ten letter code for ordering purposes.
All units are marked as above unless otherwise specified.

•Planar is a patented Fairchild process.

F=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

4-42

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD COMPLEMENTARY TRANSISTOR MICROLOGIC® IC
CIRCUIT DIAGRAMPIN CONFIGURATION AND LOGIC DIAGRAM(TOP VIEW)CTµL9954

CTµL9953

12 Vee

14
13
12

CLAMP

11
10

14
INPUT lCTµL9964

CTµL9965
14

14

13

13

12

12

11

11

10

10

NOTE: Only one representative
AND-OR gate shown.

CTµL9955

Vee
13
12
11
10

CTµL9966/9972'''

CTµL9971
14
13

R3

12

CLAMP---1>------1(

CLAMP

R2

11

Rz

10

R1

10
II

VEE

NOTE: One AND/DR gate shown.

CLAMP

Rs

Rs

5
NOTES:(1) R1 deleted for CTµL 19972
X = Not connected.

____}CLAMP
Pin 12: Vee= 4.5 V ± 10%
Pin 11: VEE= -2,0 V ± 10%
Pin 5: Ground

4-43

5*

OUTPUT

FAIRCHILD COMPLEMENTARY TRANSISTOR· MICROLOGIC® IC

ABSOLUTE MAXIMUM RATINGS (above whjch the useful life may be impaired)
Maximum current in or out of a pin

lOOmA

Maximum chip temperature

150°C

Maximum power dissipation

1.0Watt

Maximum voltage applied to any input pin

lOVolts

Maximum negative voltage applied to any
input pin (output open)-8.0Volts

Maximum voltage applied to output pin(input grounded)

5.0Volts

D.C. TESTSTYP.

LIMITS
MAX.II)ONE level offset

200

ZERO level offset-120

TESTS (atTA = 25°C)

MIN.

Clamp level

2.10

Clamp level

CONDITIONSLOAD TO VEE

UNITS

Yee

VEE

270

mV

4.05

-2.20

-195

mV

4.95

-1.80

Volts

4.05

-2.20

2.30
2.60

2.90

Volts

4.95

-1.80

Input resistors

1.6 k

2.0k

2.4 k

a

4.05

-1.80

Output resistors

1.6 k

2.0k

2.4 k

a

4.05

-1.80

lps
-INS
3.5
3.0

lps max-INS max
4.5
4.0

mA
mA
ns
ns

4.95
4.95
4.50
4.50

-2.20
-1.80
-2.00
-2.00

Positive supply current, lps
Negative supply current, INs
Rising Propagation Delay, tdr
Falling Propagation Delay, td 1

COMMENTS

F.O. = Ul2l Inputs sequentially to +2.25 V, other inputs
to 3.5 V, pin 5 open. Worst case offset
assuming ± 10% supplies. and. W.C. piira·meters. Gates with lower input voltage will
have smaller offsets; see fig. 12.
F.O. = 1 Worst case offset assuming ±10% supplies
and min. fanout. Inputs. sequentially to-0.36 V, other inputs to 3.50 V; pin 5 to
GND.
F.O. = 11 Inputs simultaneously at 3.5 V, pin 5 to
GND. Tests minimum clamp level.
No load Inputs simultaneously to 3.5 V, pin 5 to
GND. Tests max. possible clamp level tocheck existence of clamp.
No load Inputs to 3.5 V sequentially, other inputs
to -0.7 V, sense input current. Tests min.
R for max. loading, max. R for adequate
turn-off and line termination.
No load Outputs to 3.5 V sequentially, inputs to-0.7 V, sense output current. Tests min.
R for max. wired OR loading, max. R foradequate turn off.
No load Inputs to -0.7 V simultaneously.
No load Inputs to +3.5 V simultaneously.
F.O. = 12 See tpd test circuit, page 6.
F.O. 12 See tpd test circuit, page 6.

=

NOTES: (1) "Maximum" means "no more positive than"(2) F.O. =Fan-Out: F.O. = 11 equivalent to 145 0 to -2.20 V under worst case conditions
F.O. = 1 equivalent to 2.4 k to -1.80.V under worst case conditions

MAXIMUM POWER DISSIPATION VS. POSITIVE SUPPLY VOLTAGE
500 ....

~~·-2.zov'
VIN• 3.50 V': 400 I- TA=25"eI~

3001---+--+---lf--+--+---+--+-QCl54--l-+---I

4.5

Q.

~

l

--+--T+--+--+-~1---+---1

9965

1

F.0.= 12.,Ji:.

I_

F.0.=12·~300 1--+--+--+---lf. 0.•12-

.

QCl~2

i5

9955
200 ~-+---+--+--+--+---+---+-l--+___,.___.

Vee-POSITIVE SUPPLY VOLTAGE-VOLTS~

1.

POSITIVE AND NEGATIVECURRENT DRAIN

a::

~

5.0
Vee-POSITIVE SUPPLY VOLTAGE-VOLTS

4-44

CTµL
Element lps typ
9953
9954
9955
9964
9965
9966
9971
9972

22.0
16.5
11.5
22.0
28.0
27.0
26.0
12.0

INs max UNITS
27.7
20.5
14.3
27.7
34.9
33.9
32.9
20.0

33.0
33.0
30.0
33.0
29.0
38.0
36.0
5.0

41.4
39.6
37.1
41.4
36.0
47.5

mA
mA
mA
mA

mA
mA

44.6

mA

10.0

mA

FAIRCHILD COMPLEMENTARY TRANSISTOR. MICROLOGIC® IC
INPUT CHARACTERISTICS
AS A FUNCTION OF Vee
4.0}"EE• -z.o V
F.0.•6TA•25"C

~ 3.0

j_

I

~

i

2.0

A_

i

Vcc•4.95:L
liYcc • 4.50 v

I

~ 1.0

0

1£

0

-¥!
1.0

l'vcc•4.05 v

z.o

3.0

4.0

l1N-INPUT CURRENT-mA

AS A FUNCTION OF TEMPERATURE
4.o!S 3.0Yee~ 4.5Vrl-"fE • -2.0V
F.0.. 6

IJ.i!

1Z~

~
cli
_j_z

i
I
IV
:!

~ 2.0

iz

T

I
__:_

,,jj_

~ 1JJ

0
0

2.0
3.0
1.0
l1N-INPUT CURRENT-MA

4.0

OUTPUT CHARACTERISTICSTOLERANCE VARIATIONAS A FUNCTION OF Vee

4.0 ....--.---.--.---.---.--.....--....--.

4.0
_.:.
~

g 3.0
I

VE£'-2.0V. V1N•Z.5V -j
TA"25°C

Vccj_4.95l

~
g 2.0

Vcc•4.50V-·.

~

Vee .r4.os_,j/........

I
~ 1.0

.,p

0
10
20
30
lour-OUTPUT CURRENT-MA

0

40

10

20

40

lour-OUTPUT CURRENT-MA

WORST CASE JUNCTIONTEMPERATURE VERSUS
POWER DISSIPATIONAS A FUNCTION OF TEMPERATURE., 100r-r-r-....-....--.--.--,-..,..,,.-,--,
u!ffi 80~..

..~t-t-+--t--t---'_,g:il't60 !-t-+--t--t~;?F-c~'lljl'-!,<~'.::l'f"-ji""-!

a:

!
~

;

00-=o....._..._....._.....__.__,__.___._~_,
0.2
o.4
0.6
o.a
POWER DISSIPATION - WATTS

IouT-OUTPUT CURRENT-mA

4-45

1.0

FAIRCl-f ILD· CONf.PLEM,ENTARY TRANSISTOR· MICROLOGIC® · IC
TRANSFER·· CHARACTERISTICS
AS, A FUNCTION OF Vee

TOLERANCE VARIATION
3.0

3.0
TA•25°C
F.0.•6

...

~ 2.0
I

MAXI

Ill

~

~

!;i:
I

MU~

~

!;

§
0

~

.§.>
-1.0
-0.5

T
.---!cc• 4.95._S

~

~

!;

0

\lcc-4.05Y

~

I

.§.>

[,#,

~ "~cc•4.l50 v
~

I

~

--i

I/ff

2.0

ii! 1.0."'MINIMUM

7J

TA• 12~/C

Ill~TYPICAL~

ii! 1.0
I~vEc-2.ov
f--F.O.; 6

I'

-1.0
1.0

0

-0.5 ' 0

3.0

3.0

Y1rlNPUT VOLTAGE-VOLTS

AS A FUNCTION OF FAN OUT

AS A FUNCTION OF TEMPERATURE

3.0

a
>

Ycc•4.5 v
YfE•-2.0y
TA •25"C
2.0

F.0.'~

I

~

~

~

~0.•6

~

1.0

F.0.•12~?'I-1.0 ~--+-~...._...___.._..____,__...___.
-o.5
0
1.0
2.0
3.0

-1.0
0

3.0

2.0

1.0

Y1N-INPUT VOLTAGE-VOLTS

Y1N-'INPUT VOLTAGE-VOLTS·"ONE" LEVEL OFFSET
AS A FUNCTION OF FAN-OUT
120

AS A FUNCTION OF Vee

Ycc•4.5Y
YEE•-2.0Y .---1-+--+-+-7'1"--I
TA•25'C70

YEf'-2.0Y
F.0.•6 +--"-+-+-.-+:-t--t--7'iTA•25'C

~ 100

~ 80
~

601--...1"''----l--+---b.>r=-+---+--t-~~40t---t----l..,,C.+--+-+--+--t-~~20h-""+----I-+--+-+-~

ot---+---t-+--::a."""'-+---+--t-~101--.ci-----1-+--+-+--+--t-~o~_.___.

-20 '---'--==-..J........J._.l.......J__J._..J
1.0
1.5
2.5
3.0

1.0

_ _..__,__..___.__...__.

1.5

2.0

2.5

3.0

Y1N-INPUT VOLTAGE-VOLTS

Y1N-l.NPUT VOLTAGE-VOLTS"ZERO" LEVEL OFFSET
AS A FUNCTION OF. FAN-OUT

AS A FUNCTION OF Vee

vcc•4.sv
60 t--+---+-+--+-->-- YEE •-2.0 Y .TA• 25'C~

10

vtc•4.5Y
F.0.•.6 -+---+-+--+--+---+-----<rA • 2s•c40t---+--+-+--+--t---t----l----l~ 20t--t--t..,---t-f.Q..-1'1._ i--+~-+-+-tJ~~ -2oi---.,..+-....,,..---==--+'~--+--l----+---!--l~ -40t--t----t-+--+~F.0.-.~,~t--,__f-=ll
1-60

l---kkd:::±::J:l=tIJ
0.2

0.4

-0.2

0.6

0

0.2·

0.4

Y1N-INPUT YOLTAGE--YOLTS

Y1N-INPUT VOLTAGE-VOi.TS

4-46

0.6

FAIRCHILD COMPLEMENTARY TRANSISTOR MICROLOGIC® IC
WORST CASE PROPAGATION

WORST CASE PROPAGATIONDELAY VERSUS
CL AS A FUNCTION OF RL

DELAY VERSUSAMBIENT TEMPERATURE
12

s

2-1~

I!

f
?c 7~0 f--+-+-+--+--+--+--+--+---+---i

I!:

!!!

i

~
0
'"'-~
g:
5.01-+-+--+-+-+--~'-l"':..+--+-c:::l~i~·fOlll~

1--t::::[

I

60......
...~ 4.0-+-f-1 ~

4.o

~

~ 8.0

~ 6.01----+-+-+--+--+--+--+---+--+--t!cti#,"'L "TJ ;"'I---ldf

10

,/

I

L.

,
.a.,...

..

,/

~~ ~

, , ~

,v

I

I

I~

I

25011

500D.~

t;

~ 2.0

I

3.0 .__....._....._..._....__,__,__,___.___.__,
40
100
0
20
60
80
AMBIENT l[MPERAIURE • °C

0

20

0

40

60

80

100

11_-'LOAD CAPACITANCE-pf

t'° TEST CIRCUIT FOR ABOVE

tpo TEST CIRCUIT
Vee

+fi
LOY
IJV
1.0V INPUT._,,___o~u-coTPUT

51D.

133D.

30pF 13D.

_ 0_5 v

RLI. .Ci.

I36pF

....

1,•11°1ons

yt

OUTPUT~E.OV

Vee= 4.5 V
VEE= -2.0V

Vee=4.5 V
VEE= -2.0V

TA= 2s•c

TA= 2s•c
APPLICATION INFORMATION:

Greatest system speed will be realized by performing most of the logic with the use of the ultra-fast AND-OR gates. Consideration, however, must be given tolevel shifting, loading effects.• impedance matching and ringing, which are inherent in fast switching syStems. The AND-OR gates have built-in capability toovercome these problems. A few rules are outlined below to assist in solving these problems.
The electrical specification tests are performed under conditions chosen to emphasize the worst case results, and could be considered as conservative limits.
For initial steps in designing new systems, typical values and data from graphs may be consulted for a realistic design. The different diagrams for eachparameter are correlated through the nominal curve. To arrive at the worst case performance under a given set of conditions, deviation from nominal curve
must be added or sulstracted as the case may be.
INTERFACING - The AND-OR Gate should always be driven from another CTµL element. When interfacing from another logic form, or from a test signal generator, the signal should be introduced via a CTµL inverter, buffer, or flip-flop and then into the AND-OR Gate.
WIRED-OR-A powerful feature of the AND-OR Gates is that two or more outputs may be wired together to form the positive OR function at the output tie
point, thus achieving two logic decisions in a maximum of 4.5 ns. Subtract 1 unit fanout for each OR added gate.
OFFSET LEVEL . NOISE IMMUNITY - The AND-OR Gate may be looked upon as a non-inverting amplifier having a gain of less than. one. Thus, the output
levels are offset from the input. The amount of offset is a function of loading, positive and negative power supplies, temperature, and input voltage and could
be determined from the One and Zero level offset curves. When cascading AND-OR Gates, it should be noted that the offset of the first element has the largest
offset and is decreasing sequentially on the following elements, due to smaller inp1,1t level. It is recommended that noise-immunity levels be re-establishedby inserting such CTµL elements as the 952 Inverter, 956 Buffer, or 967 Flip-Flop after several offsets.
HIGH FREQUENCY RINGING - Each AND-OR Gate is internally equipped with a clamp circuit designed to reduce output ringing at high speed operation, at
low fanout and moderate speed, the clamp may be released by leaving pin 5 open.
Any one length over 12" long connected to the output should be terminated with a 200 n resistor to ground at the output. The 200 n approximates thecharacteristii: impedance of back panel wiring. The 200 n termination is considered as a fanout of 4.
Regular equal spacing of AND-OR along a single path should be avoided as they tend to appear to the driving gate as a set of similarly tuned tank circuits
and may induce ringing. When unavoidable, 200 n resistor to ground along the path will eliminate the ringing.
l:arge capacitive loads may cause ringing at the AND-OR Gate output and should be driven from a CTµL inverter or buffer.
UNUSED INPUTS- Unused inputs to the AND-OR Gate will effectively inhibit the gate output, and therefore, must be tied to the most positive voltage level.
The unused input may be tied directly to +Vee or through a resistor not greater than soon. Unused inputs may be tied to active inputs at a cost of reduced
fanout.
SHORT CIRCUIT PROTECTION - The AND-OR Gate output is protected by a limiting resistor at the output and may sustain prolonged short circuit to groundat Vee not greater than 5 volts. Excessive destructive heat may develop when more than one output in a single package is short circuited to ground. Shortcircuiting the output to the -2 volts supply should be avoided.

4-47

CT1.1L9956
DUAL 2~1NPUT BUFFERCOMPLEMENTARY TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS+15°C TO +55°C TEMPERATURE RANGE

GENERAL DESCRIPTION - The CTµL 9956 dual 2-input power AND gate is a low impedance non-invertinglevel setting circuit intended to dr.ive high fanout, and may be used as a son line driver. The input thresholdand output levels are compatible with any other CTµL elements. The output of the CTµL 9956 may be tiedwith any other CTµL element to perform the wired OR function.

PHYSICAL DIMENSIONSTYPICAL DUAL IN-LINE PACKAGE

In Accordance WithJEDEC (T0-116) Outline~.290-lCTµL 9956 is packaged in the versatile Jedec T0-116 Dual In-Line Package* which is a hermetically sealed
ceramic package intended for low cost insertion techniques.

IF.310=fl

F8\CTµL 9956 is designed to operate over a commercial ambient temperature range of +15 to +55°C. Powersupplies are 4.5 volts ± 10% and -2 volts ± 10%. Typical power dissipation per gate is 60 mW and isdesigned to increase with fanout. Typical propagation delay 14 ns.

...j

NOTE 1-j.- .350 MAX.

•Fairchild patent pending.

FEATURES:• Power Supplies are. +4.50 V ±10% and -2.00 V ±10%.
• High Fan-Out Capability ••• 25.
• Two Optional Pull Down 1.0 k Resistors for Optimum Speed.
• Low Power Dissipation.
• Low Propagation Delay.
• Logic Swing of 3.0 V.

1.1.t1d11,.intendtdforinsertloniflllol1rowson.300"c1nl1tr1.Th•rpurponlrsllifl!Mld wltlt 'pnltlv..' U50l 111ihlit;nm111tto fHililllt I-lion.
2.lffrd·d,.lliqdl1111nMon11t1ou1d1qu11rourpr1cticelor1convanl-al.020
lnchdl1mtt.,lnd.

CONNECTION DIAGRAM

P~LtsPs~~= 1

PURCHASING INFORMATION

2• l!se the ten letter code U6A995679X for ordering purposes.
• All units are marked CTµL 995679 and date code, unless otherwise specified.

NC3
NC4

GND 5

B

TOP VIEW/

F=AIRCHIL.C
SEMICONDUCTOR

313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011, TWX: 910-379-6435

4-48

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD COMPLEMENTARY TRANSISTOR MICROLOGIC® IC
SCHEMATIC DIAGRAMABSOWTE MAXIMUM RATINGS

Vee· +4.svt 10%(above which the useful life may be impaired)

R7

R3

Maximum Current in or out of a Pin
Maximum Chip Temperature
Maximum Power Dissipation
Maximum Voltage Applied
to any Input Pin
Maximum Negative Voltage
Applied to any Input Pin
Maximum Voltage Applied
to Output Pin

R4
OUTPUT
R5
GNO

lOOmA
150°C
1.0Watt
10 Volts-4.0Volts
6.0 Volts

NOTE: ONLY ONE BUFFER SHOWNDC TESTSTEST (at TA = 25"C)MIN.

ONE Level Output
ONE Level Output
ONE Level Output
ZERO Level Output

2.25
2.46

LIMITS
TYP.
MAX.
2.60

Yee

Yee

4~05

Note 1
Note 1
Note 1-1.SV

12 >f.O. =

4.95
4.95
4.05

25
F.O.=lInternal 1 k
F.0.=1

2.70
-0.45

3.20
-0.36

Volts
Volts
Volts
Volts

5.30

6.40

mA

4.05

Note 1No Load

1.0

1.2
69.2
18.0
18.0

kn
mA
ns
ns

4.05
4.95
4.50

-2.2V
-2.2V
Note 1
Note 1No LoadNo LoadF.O. = 25
F.O. = 25

Input Current

Input Pull Down Resistor
Positive Supply Current
Output Rising Delay, tdr
Output Falling Delay, tdf

CONDITIONSLOAD TO Vee

UNITS

0.8

12.0
12.0

uo

COMMENTS

Inputs simultaneously to 1.25 V
Inputs simultaneously to 1.25 V
Inputs simultaneously to 3.5 V
Inputs to 0.8 V sequentially,
unused input to 3.5 V
Inputs to 3.5 V simultaneously,
guarantees input loading ~ 1.5
AND·OR gate loads
3.5 V applied to pull down resistor
One input to 3.5 V, other inputs to GND.
See tpd test circuit, page 4
See tpd test circuit, page 4

NOTES:(1) Value of Vee is non.critical: -2.20 V:5 VEE :5 -1.80 V(2) F.O. - Fan Out; F.O. = 25 equivalent to 64 0 to -2.20 V under worst case conditions
F.O. == 1 equivalent to 2.4 kO to -1.80 V under worst case conditions

INPUT CHARACTERISTICSTOLERANCE VARIATIONOF PARAMETERS

AS A FUNCTION OF
POSITIVE SUPPLY VOLTAGE

AS A FUNCTION OF
TEMPERATURE

VEe•-2DV

3.0 T,;•25'e--+·--+--+-=·~ 2.51'--t-t-+-+--i-+7~
I~ 2DI--+-+-+--_,....,...,._+--+---+--+--<!:ig.. 1.51--+--+--..of.-+-+-+-+-+-+-I

...
::>

z
T
to i--++--+--+---+---+--+---+---+---+--<
z
>

0

LO

4.0

4.0
l1N-INPUT CURRENT-mA

l1N-INPUT eURRENT-mA

4-49

11N-INPUT eURRENT-mA

5.0

l._______c_Tµ_L_:.>_99_5_6_CO_···'_M_PL_E_·M_EN_T_A_R_V._T_RA_.'N_·s_is_'f_bR_....__:M_IC_R_O_LOG_..•_IC®_·_·._1c_._ _ _ _ _·1
OUTPUT CHARACTERISTICSTOLERANCE VARIATIONAS A FUNCTION OF
POSITIVE SUPPLY VOLTAGE

OF PARAMETERS .

AS A FUNCTION OF
TEMPERATURE

12..-....--....---.--.--......---.----.,.........,
l---+----+---<-+--+-VEE'-2.o·v

Ta•2s•c. "·z.oo'---'-~2~0----'-4~0--'-eo....__.__.eolour-OUTPUT CURRENT-llA

2.0 .__.....___.___._..__.....___.___.__,
0.
40
BO
20.
IOUT. • OU!PUT CURRENT- Illlour - OUTPUT CURRENT- llA

AS A FUNCTION OF
NEGATIVE SUPPLY VOLTAGE

SCHEMATIC DIAGRAM

3.2

vcc•4.5Y '·TA•2!5°c·'!!!5.0g. rs..
I.... 2.8;!

·. g• 2.6~

" ~-0~-.. +~•l.Bva

....

~tv

~·2.4

.
~2.2

:· ·'

I

20
40
BO
lour - OUTPUT CURRENT- llA!'r

TRANSFER · CHARACTERISTICS · ··AS A FUNCTION OF· 1'0LERAt4CE VARIATIONOF PARAMETERS

10I·YEE •-2.0V

TA•25'C~ 2.0 F.0.•12

MAXIMUM-1---1
HfYPICAI.
MINIMUM.-1---1

~ 1.0

~ 0.5

YE[•-2:0Y·
~

I

!:l

0

I
g
I

2.ol-+-+-+-++-+++-+-+-+--i~ 0o.51-+-+-+-++-+++-+-+-+--iI- ' ·O l-+-+-+-++-+++-+-+-+. .,-1
·.
g'
·~
~
I

-0.5

>

-1.0
0.4
o.B
1.2
1.6
Ytil., INPuT VOlTAGE·· VOLTS

2.0.

2.5 Ta•25'C
F.0.•12
~ 2.0

!:l

...'

,

•

-o.s~~~~~f--t-f-+-+-i-1.0 ,__..__..__..__...._...._....__,___,__...__.
0
QA
0.8
i.2
1.6
2.0
V1N ·INPUT VOLTAGE~vom·

WORST CASE
.POWER DISSIPATION VERSUS
POSITIVE SUPPLY VOLTAGE

AS A FUNCTION OF
POSITIVE SUPPLY VOLTAGE
VEE ··-2:ov :· •.,...

...

:: 1.51-1--1----t--t~--t--t--t--t

i 1.01-+-+-+-+-----+-+-+-+--i~~ 0.,~ Ol-+-+-+-+-..__+-+-+-+.,-1~-0.5-1.0 ,__..__..__...._...._.._.._...._...._...__.
0
0.4
0.8
1.2
l6
z.o
· YIN - INPUT "VOLTAGE• VOLTS!mll$=$=$=:1=if-t-t-t-t-1'i··'

NOTE: Variation of."Vee: does
not alter transfer
characteristics.

3.0

VEr·2.0V• 1_+-t$F.O.~·~l**~2.5 Vcc•4.5V-j
TA•25'C
F.O.·~~~ 2.0 l-l--r--tr--t--t.....-+1F.O. o2o t-+-!S
1

1.5 f-f-Jl---ll---IH-il::-ll""l+."iA....;'.o...o.'c..__1--1~TA•25'C
1.0 t--t-.TA•loo'C":!-+-+-1-+--+--+--+--t0

0

FAN.OUT

10..-..-,..._..-..-.,..-....--.---.--...--.

vcc•4.5V t-~::lt'.l~=e=e=e~!S 2.5 F.0.•12.,... 1.5

AS A FUNCTION OF

TEMPERATURE

I!! 2.5 Vcc•4.5V
I

BO~CC_' 4.9ili;._· WORST CASE JUNCTIONTEMPERATURE. VERSUS ·POWER DISSIPATION'i' 120 ..--..--..--.....-.....--.---.--.,.--.,.--..,.....,,

5! 1001--t--t--+--+--+-+-t--'-t--1
I •o >--+---+-+--+-- ,.,.._+--+-__,

Vcc·4.5or-d
Vcc•4.05Y-f -:: 1.5!:l!II! 60 1--t--t--+--+

~ 0.5

i::

.

~ 1.0

~

0

~

1001-+-+-+-+-+-+-+-+-+--i

-0.5
-1.0
0

0.4
0.8
1.2
1.6
YJr INPUT VOLTAGE-VOLTS

2.0

o,__..__..__..__..__..__..__.._.._...__.
4.0
4.2
4.4
4.6
4.8
5.0
Yee-POSITIVE SUPPLY VOLTAGE-VOLTS'4-50....l4or--r-i-•v--~.,,.~~
i!l 20 i--'h'"i1~f!Gl"!'-o::;I~i
POWER DISSIPATION-WATTS

, FAIRCHILD COMPLEMENTARY TRANSISTOR MICROLOGIC® IC
WORST CASE PROP~TION

WORST CASE PROPAGATIONDELAY VERSUS AMBIENTTEMPERATURE

DELAY VERSUS LOADCAPACITANCE AS A
FUNCTION OF LOAD RESISTANCE

1&~~~~~~~~~...__,

0

20

40

60

80

100

Ta- AMBIENT TEllP£RATURE -•c

CL· LOAD CAPACITANCE - pf

1,o TEST CIRCUITVe

1,o TEST CIRCUIT FOR ABOVE
1.ov

1.ov

INPUT

-o.sv

ANO
5111

OUTPUT1,=t1=1on1
644

&2pF

&.44
75pf

-.i ldrr-+i r
ldt

5111

OUTPUT~v

J·~+IT.SYINPUTOUTPUT

INPUT

I--0.SV}:{r·
W• :

••

~
OUTPUT.

Vcc•4.
5V
VE['-2.0V

1.0V

TA•25•c

APPLICATION INFORMATIONThe electrical specification tests are performed under conditions chosen to emphasize the worst case results and could be considered as conservative limits.
The output ONE level at worst case is guaranteed to drive a fanout of 25 AND-OR gates. The maximum input current assures that 9956 input presents a loadof not more than 1.5 AND-OR gate input.
INTERFACING-The CTµL 9956 buffer could serve as an excellent interfacing link between external signals coming from other logic forms or peripheral equip~
ments and the CTµL Family logic.
PULL DOWN RESISTORS - Two pull down 1 kn resistors are built into the package with one end tied to the negative power supply <V~e>· When the 9956 input
is driven by a single AND-OR gate, the 1 kn resistors should be connected to the same input pin. This will improve the 9956 output rise and fall time. The
pull-down resistor may be also connected. to the CTµL 9956 output, which will improve the output falling delay when the fanout is low.
LINE DRIVER-The CTµL 9956 could be used as a line driver. To drive a 50 n line, a 680 resistor should be connected from the output to ground. This will
reduce the fanout capability by 15.
WIRED-OR-A powerful feature of the CTµL 9956 Buffer is that the output may be tied together with the output of any other element in the CTµL family toform the positive OR function at the tie point. When two or more CTµL 9956 outputs are tied for the OR function, a pull-down resistor must be used.
UNUSED INPUTS - Unused inputs to the AND-OR Gate will effectively inhibit the gate output, and therefore, must be tied to the most positive voltage level.
The unused input may be tied directly to +Vee or through a resistor not greater than 600 n. Tying an unused input to an active input is not recommended.
SHORT CIRCUIT PROTECTION - The CTµL 9956 Gate output is protected by a limiting resistor at the output and may sustain prolonged short circuit to groundat Yee not greater than 5 volts. Excessive destructive heat may develop when more than one output in a single package is short circuited to ground. Shortcircuiting the output to the -2 volts supply should be avoided.

4-51

CTuL 9957•9967
FLIP-FLOPSCOMPLEMENTARY TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS+15°C TO +55°C TEMPERATURE RANGECTµL 9967 FLIP-FLOP GENERAL DESCRIPTIONPHYSICAL DIMENSIONSThe CTµL 9967 dual rank J-K Flip-Flop is a high speed directly coupled multi-purpose storage element usefulfor shift registers, counters, and other control functions.

TYPICAL DUAL IN-LINE PACKAGE

Operation of the CTµL 9967 is based on the "master-slave" principle whereby information is entered intothe "master" when the clock pulse goes high and is transferred to "slave" &nd outputs when the clock
pulse goes low. DC coupling throughout makes the Flip-Flop input insensitive to rise and fall times.

IF.310 ==tl

In Accordance WithJEDEC (T0-116)Q,u;n~_ 290 --I

ifID\

NOTE l+-.350 MAX.---1

The CTµL 9967 employs the PNP-NPN complementary logic to achieve fast response with typical toggling
rate of 35 MHz. The emitter follower outputs are compatible with all other elements in the CTµL family.
Two phase clock outputs at half the clock input frequency is available when the CTµL 9967 is operated as abinary counter. Typical power dissipation is 420 mW and is designed to increase with fanout.

CTµL 9957 GENERAL DESCRIPTION
The CTµL 9957 is a basic dual-rank R-S Flip-Flop intended for storage and control function. Logic and clock
inputs are omitted for additional flexibility. J-K operation with either two-phase or single-phase clocking canbe exercised by adding AND-OR gates to the inputs. Wired OR ties within the flip-flop reduce typical throughpropagation delays to 14 ns.

I. Leads are intended for inslflicrn in hole rows on .300" centers. They are
11urpo,elyshlpp1dwlttt'p.;>$itive"(.350)mls11ignman1tof1cillt&t1insution.
2.8oard-drilli111dimensionssltouldequa1yourpracticefor1ccmvenlional.020
lnchdlamate•lead.

The CTµL 9957 is DC coupled throughout. The inputs respond exclusively to voltage levels and are insensitive
to rise and fall times. Emitter follower outputs, compatible with all other CTµL elements, provide efficientdrive capability into long line and capacitive loads.
The CTµL 9967 and CTµL 9957 are packaged in the versatile Dual In-Line Package which is hermeticallysealed ceramic package intended for low cost insertion techniques.
Both flip-flops are designed to operate over a commercial ambient temperature range of +15°C to +55°C.
Power supplies are 4.5 volts ±10% and -2 volts ±10%.

PURCHASING INFORMATIONDESCRIPTIONCODEMARKINGCTµL9957
CTµL 9967

U6A99577!!XU6A996779X

CTµL95759
CTµL96779

Use the ten letter code for ordering purposes.
All units marked as above unless otherwise specified.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

4-52

A DJVISlON OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATION

CTµL 9967 COMPLEMENTARY TRANSISTOR MICROLOG.IC® IC
SCHEMATIC DIAGRAMPIN 12

Vee

.,,.

[~]
----------~ ---------ji--------o OJ
PIN 13
PIN 100o-+---~--~--~-------j..__~
PIN 1

PIN 3

PIN 8

PIN 6

TRUTH TABLE

PIN & LOGIC DIAGRAM CTµL9967 - JK FLIP FLOPASYNCHRONOUS ENTRYSYNCHRONOUS ENTRY
eP-CLOCK 1

J

K

SD

CD

t. + 1
output (Q)

L
L

L

L
L
L
L
L

l

Q.

H

L
L
L

L

Q.

H

H

L

L
Undeterminedt.,

14 J-INPUT
13 'l'-OUTPUT•1 2
So-DIRECT SET 3

12 YeeN.C. 4

11 VEEGROUND 5

10 'O'-OUTPUT

Co- DIRECT Cl.EAR 6

9 LOGICAL CLEAR-Pc

L

H
H

H

L
L
L

L
L
L

H
H

H

H

Inputs
SD
CD

"l"

L
L

NC
L

H
H

L

H
L

H

H
H

Outputs
"0"
NC

H
L

H

Clock Input Low

8 'K'-INPUT•2 7
Vcc•4.50V
VEE'-2.00V
N. c.- NOT CONNECTEDLOADING RULES

FLIP-FLOP INPUTSCP

J, K
So, Co,.

Pc
OUTPUTSQ, Q
0

1 LoadLOADING 0

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Maximum current in or out of a pin
100 mA

2.0
1.0
1.5
1.0

Maximum chip temperature

150°C

Maximum power dissipation

1.0 Watt

Maximum voltage applied to any input pin

lOVolts

Maximum negative voltage applied to any input pin

FAN OUT

12

Maximum voltage applied to output pin= 1 CTµL AND-OR Gate Input Load
4-53

-4.0Volts
6.0Volts

CTµ,L 9967. COMPLEMENTARY TRANSl~TOR MICROLOGIC® IC
ELECTRICAL CHARACTERISTICS
9957·oc TESTS'LIMITSTESTS (at TA = 25°C)
MIN.

TYP.

ONE Level Output

2.35

2.50

ONE Level Output
ONE Level Output

CONDITIONS

MAX.IS)

UNITS

Vee

VEE

Load to VEE

Volts

4.05

NOTEl

l 3IF.O. = 12

2.56

Volts

4.95

NOTE 1No Load

2.56

Volts

4.95

NOTE 1No Load

COMMENTS
Untested output to 3.50 V; logic input to 1.33 V;
clock inputs to pulse (Note 4)
Untested output to 3.50 V; logic input to 1.33 V;
clock inputs to pulse (Note 4)
Untested direct input to 3.50 V; tested direct input
to 1.25 V; clock input to -0.70 V.
Corresponding direct input is 3.50 V.

ONE Level Output
ZERO Level Output

-0.50

3.20
-0.31?

Volts
Volts

4.95
NOTE2

-1.80
-1.80

F.O. = 1
F.O. = 1

ONE Level Offset

200

270

mV

4.05

-2.20

F.O. =4ZERO Level Offset

120

195

mV

4.95

-1.80

F.O. = 1

1.6 k

2.0 k

2.4 k

n

NOTE2

-1.80

No LoadDirect input to 3.50 V; other direct input to 0.80 V;
logic inputs to 3.50 V; clock input to 0.47 V.
Trigger and logic inputs sequentially to 2.25 V;
untested inputs and outputs to.3.50 V.
Clock and logic inputs sequentially to -0.36 V.
Untested inputs and outputs to 3.50 V.
Logic input is 3.50 V.

0.8 k

1.0 k

1.2 k

n

NOTE2

-1.80

No LoadClock input to 3.50 V.

6.1
2.0
51.0

7.67
3.27
64.0

mA
mA
mA

NOTE2
4.05
4.95

-1.80
-1.80
-2.20

No LoadNo LoadNo LoadTerminals 2 and 7 to 3.50 V.
Direct set.and clear inputs to 3.50 V.
Clock input to -0.47 V.

55.0

68.7

mA

4.95

-2.20

No Load

ns

4.50

-2.00

F.O. = 12

Clock, logic inputs and "l" outputs to 3.50 V
simultaneously.
Min. required pulse width to trigger 967.

Logic Input
Pull-down Resistor
Clock Input
Pull-down Resistor
Input Current
Input Current
Positive Supply
Current
Negative Supply
Current
Clock Pulse
Width -tpw
Output Rising
Delay· tdr
Output Falling
Delay· tdr
Direct ThroughRising Delay· t.,
Direct ThroughFalling Delay • t,r

25

16.0
10.0

15.0

ns

4.50

-2.00

F.O. = 12

Seetdf'. tdr test circuit, page 4

16.0

25.0

ns

4.50

-2.00

F.O. = 12

Seetdr• tdr test circuit, page 4

17.0

25.0

ns

4.50

-2.00

F.O. = 12

See t,r• t,r test circuit, page 5

25.0

38.0

ns

4.50

-2.00

F.O. = 12

See tsr• t,r test circuit, page 5

NOTES:(1) Value of VEE non·critical, -1.80 V::::; VEE < -2.20 V.
(2) Value of Vee non-critical, 4.05 V::::; Vee::::; 4.95 V.
(3) F.O. = Fan-Out: F.O. = 12 equivalent to 1330 to -2.20 V under worst case conditions.
F.O. = 4 equivalent to 4000 to -2.20 V under worst case conditions.
F.O. = 1 equivalent to 2.4 k to -1.80 V under worst case conditions.
(4) Pulse is a positive pulse of non-critical amplitude and width.
(5) HMaximum" means "no more positive than."

WORST CASE PoWER DISSIPATION
VS. POSITIVE S.UPPLY VOLTAGE
550

T
VEE•-2.2V/

17'~ 100 ,--,--,--,--.,--.,--.,--..,.--,,-'T'"""O.._1_-=-._-:J7'~-:1Z-/_--l+v:.L.:~:~

500 ,_r_A·,_25_•c,_-_-1-,_-_-1-,_-_...

rd2~.~ .Lv
•

450

400

350

400 <---+--+---+-+---+--t-----i---i

1...-1300 t---+--+---+-+---+--t-----1---i

f--+-+-7'F-v-+>I/<-+-?' .~t---+--+---+F.O. • 1·Mo '--'--'--'--'---'---'---'----'----'--'

M«!I 80 t--t--+--+--+--+-~
j60 1--i--!-+-+~

200 l--+--+---+-+--+---+----1--;
Vee• 4.5 v!--+--+---+VEE • -2.0V
t---+--1
100 l--+--+---tvlN·-~5 51;,Cl0fo5u~y CYCLE

P"U.......ziii~

f!L:j v
v l7 .A7
Yv
v~

WORST CASE JUNCTIONTEMPERATURE VS. POWERDISSIPATION

WORST CASE POWER DISSIPATION
VS. CLOCK INPUT FREQUENCYUPOSITIVE SUPPLY VOLTAGE-VOLTS~.J.+--+--+--1TA•25'Co.__~~--+-i+---+--+-----<~

0

10

20
30
I ·FREQUENCY-MHz

40.

40

,.

~ 20l--t-t'~:t£-+-t.-~+-+-+:-J

;

0.4
0.6
0.8
POWER DISSIPATION-WATTS

1.0

CTµ,L 9967 COMPLEMENTARY TRANSISTOR MICROLOGIC® IC
TRANSFER CHARACTERISTICS
CLOCK-ONE LEVEL VERSUSTEMPERATURE

DIRECT SET/DIRECT CLEAR
VERSUS TEMPERATURE
3.0
Vee· 4.5v
f-VEE' "2.0V
F.O. •12

Vee • 4.5 v.LI
VEE•-2.ov+--l--A=;J+:::+==l:::::::i==I!:i~ 2.0 t-F.-.0+.·_12+--+--tt-++t-+--i-t---t--1...
~~

SWITCHING CHARACTERISTICS

40

TA• •cvcc•4.5V
vEE'-2.ov_,
F.0.•.12

TA•25'f:.IrTA•lOO'C

~ 30

5:!l

j.-TAso'c~ 1.0 l--+-+--+--+-c;.1-TA • 25' C t--f-!;f..:'~A•lOO'C

...z

'df

~20

~

0
...I

;

INCREASE IN PROPAGATIONDELAY DUE TO OUTPUTCAPACITANCE

PROPAGATION DELAY VERSUSAMBIENT TEMPERATURE

--1

ldr

~ 20

I
tdi MAXIMUM

f

tdr MINIM~f tob::k::±::±:~:±:j~=::t=tJ

0

g: 10

Ot--+--+--+--+-++<>-+--t-t--.,_...,

!:ii

0

-1.0~+--+--+-_....~__.__._.__~

0

0.4

0.8

1.2

1.6

-1.0

2.0

0

CLOCK INPUT VOLTAGE ·VOLTS

o.4

. o.e

1.2

1.6

0
0

2.0

25

75

50

TA· AMBIENT TEMPERATURE-'C

DIRECT SET INPUT VOLTAGE - VOLTS

tour - OUTPUT CAPACITANCE -pf

OUTPUT· CHARACTERISTICS
AS .A FUNCTION OF
COLLECTOR SUPPLY VOLTAGE

TOLERANCE VARIATIONOF PARAMETERS

AS A FUNCTION OF
TEMPERATURE

3.0 .-.....---,---,.,.----,--.--.....---.----.

4.0
Vcc•4.5V

1---+---+-+--+-f- VEE•· 2.0V
TA•25'C

VEE'10V--j

"'~

g3.o

J.o•c

.....
I

"'~

TA1_5'C

0>Z.O

TA •lOO'C

!;
a.
!;
0

~1.0

~
2.0.__-+-.....-+--+--'---+-.....~
0
10
20
30
40
lour-OUTPUT CURRENT-mA0

2.0 '---+-.....-+--'--'---'---"-~
0
10
20
30
40
lour·OUTPUT 'CURRENT-mA

0

10

20

40

DIRECT SET AND DIRECT CLEAR
PROPAGATION DELAY VERSUSTEMPERATURE

td 1 and tdr SWITCHING TIME TEST CIRCUIT

Vcc•4.5v·VEE•-2.0V
50 t----+--+-+--+--1--F.0.• 12 . ...,

+1.7 vo.c.
TO OSCILLOSCOPE--i
TRACE A30

louT ·OUTPUT CURRENT - mA•oEL~~--t-1
540>----+--'§!4F-~~~R

. J·

z

:!l

_LJ_

~

1s'R·OIRECT SET DELAY~ 30

C.P. lot--1----t----<

T

--I

120
'--....-'=---r-'11~..,...__TO~i~~~O~

lOt----+--+-+--+-t----+--+---lI

Io~_.___._+-_...._,___.___.__.

I

0

I

t2 TcExr
1----l>-'---'

R1 =1330 ± 1%
R2 = 13 0 ± 1%
R3 =500 ± 1%
c, =36 pf± 2%==·30 pf ± 2%
Z = Probe lm~edance 2: 5k

~

c,

25
50
. 75
TA·AMBIENT TEMPERATURE·'C

100 .

WORST CASE SETUP AND RELEASE
TIME VERSUS TEMPERATURE
30

Vc~4.5V

VEE':-2.0V --11----t---+-+--+--i
F.0.•12_)/~SWITCHING NOTES:(1) Input Pulse

Frequency: 10 Hz to 10 MHz
Pulse Width (tpw)
25 ns
Rise Time = 10 ns
Your
Fall Time = 10 ns
PIN 13 - - - - - - - 'at 10% to 90% pts.
(2) The load capacitance indicated in the test circuit YourPIN 10includes the c.apacitance of the probe and jig.
(3) Vee= 4.50 V; VEE= -2.00 v

=

\___

--------_}=...

L
ldf

I

_i.ov_
WAVEFORMS'___,.

TA-AMBIENT TEMPERATURE-'C

4-55

CTµL 9967 COMPLEMENTARY TRANSISTOR MICROLOGIC® IC
DIRECT SET & DIRECT CLEAR SWITCHING TIME TEST Cl!ff:UIT
TO OSCILLOSCOPE
TRACE A

-i

.

z
So

V1NCOI---+-----'

R1 =133 0 :t 1%
R2 = 13 0 :t 1%
R3 =500 :t 1%
C1 =36 pF :!: 2%
C2 =30 pF :!: 2%
Z = Probe Impedance ;:::: 5k1----.-------.· .,._TO OSCILLOSCOPE
i

TRACE 8SWITCHING NOTES:(1) Input Pulse

Frequency: 10 Hz to 10 MHz
Pulse Width
25 ns
Rise Time= 10 ns
Fall Time= 10 ns
tseT-UP & tRELEASE SWITCHING TIME TEST CIRCUIT
at 10% to 90% pts.
1.7VD.C.
(2) The load capacitance indicated in the test circuit
includes the capacitance of the probe and jig.
TO OSCILLOSCOPE
TRACE A
(3) Vee= 4.50 V; VEE= -2.00 v=

Z--i ...

!------.··~,....-

WAVEFORMS

R1 =1330 :!: 1%
R2 = 13 0 :t 1%
R3 = 50 0 :!: 1%
C1 = 36 pF :t 2%
C2 = 30 pF :t 2%
Z = Probe Impedance ;:::: 5k

TO OSCILLOSCOPE
TRACE 8VIN::z
PIN 111!1---+------1

022ov·---SWITCHING NOTES:(1) Input Pulse

Rise Time= 10 ns
Fall Time = 10 ns

at 10% to 90% pts.

Amplitude= 2.10 V(2) The load capacitance indicatad in the test circuit includes the capacitance of the probe andthe jig.
(3) Vee·= 4.50 V; VEE= -2.00 v.
(4) Similar tests may be made at "0" output if
logic input is the "K" input.

1.0V(5) tm .uP is defined as the minimum time required for a "ONE" to be present at either
iogic input prior to a clock transition from ahigh to a low in order for the flip-flop to
respond. tRELEASE is defined as the _maximum
time required for a ONE to be present ateither logic Input prior to clock transition froma high to a low in order for. the flip-flop not
to respond.
·-o.sov
LOGIC
INPUT-~-ur-<P-1N_1_3'-F-oR_G_o _o_o_Ev-1c_E___,~------------------------·OPERATION OF FLIP-FLOPThe CTµL 9967 is directly coupled throughout and hence, its inputs are not sensitive to rise times. It responds exclusively to input voltage levels with definite,separated thresholds for both high and low voltage levels.

CLOCK INPUT VOLTAGE

As the clock input rises from ZERO level, above Vn, the transfer gates·between the .master and the slave are inhibited and the slave is isolated
from the master. Above V13 , the logic input gates are enabled and themaster is set. Above Vw the master is sure to be set under the worst
case condition and clock input is reaching the ONE level. As the clock
input falls from the ONE level below Vw it inhibits the logic input
gates and assures no further change in the master flip-flop. Below Vw
the transfer gates are enabled, the slave and outputs are set according
to information stored in the master. Below Yr" the transfer gates are
sure to be. enabled. under .the worst case condition. The clock input
reaches the ZERO level.
Synchronous entry of information is ~one at the J and K inputs while the clock input is high.

· Asynchronous information is entered at the S0 and C0 Direct Set and Direct Clear. A high level ONE is applied to the appropriate asynchronous input while theclock input is at the ZERO (low) level. Sufficient time must be allowed for the flip-flop to change state before the clock goes high.
''Pins 2 and 7 may serve as an output for a two phase clock having the

CLOCK INPUT

same pulse duration as the.-:clock input. Each output has a repetition
rate of half the clock input frequency. (Fig. 1, Wired OR)nlOUTPUTJ·I
I. Pin 9, designated as a Logical Clear, may be used to block information

TERMINAL 2

from entering .the J input without inhibiting the internal AND gate. It

Jl

TERMINAL 7 _ _ _may also serve as an additional isolated J input.
4-56

n

n

n

I
n

l

.J.~r~~

.I
I
I
1

_.rl

I
I

I
I

:

ri_

CTµL 9957 COMPLEMENTARY TRANSISTOR MICROLOGIC® IC
SCHEMATIC DIAGRAM

•1

vcc

vcc

I

BLOCKING
INPUT•1

14<>-t---.-''WV--r--1:...

••

••

0
!LOCKING
INPUT.:l-........."'"1r--+--o•

11

Vu=- 2Y t 10%••

R3

1.......,.,.......-c

~~
INPUT

~

~-------~----+--'------.___,LOGIC DIAGRAM

~~
INPUT

TRUTH TABLE(POSITIVE LOGIC)s.

c.

Qnt+ 1

0
0
1

0
1
0
1

Qn
0

1

1
Undetermined

NOTES:(1) Connect pin 1 to pin 14 and pin 7 to pin 8(2) Flip-Flop changes state on negative transition of input waveforms(3) For asynchronous entry use pins 2 and 6

TOP VIEWLOADING RULES
FLIP-FLOP UNITS
Data

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)SA, CALO
2.0

Blocking

3.5

OUTPUTS
Q,Q

Maximum current in or out of a pin
Maximum chip temperature
Maximum power dissipation
Maximum voltage applied to any input pin
Maximum negative voltage applied to any input pin
Maximum voltage applied to output pin

LOADING'"FAN OUT
9.5*l Load = 1 CTµL AND-OR Gate Input Load

4-57

100 mA
150°C
1.0 Watt
10 Volts-4.0Volts
6.0Volts

CTµl 9957 COMPLEMENTARY TRANSISTOR MICROLOGIC® IC

DC TESTSTESTS (atTA

LIMITS= 25°C)

MIN.

I

TYP.

ONE Level Output

CONDITIONS

MAX.
3.20V

UNITS

Yee

Yee

Volts

4.50

-2.00

ONElevel Output

2.20

Volts

4.05

-2.20

12 lf.O.

ONE Level Output

2.20

Volts

4.05

-2.20

F.O.

Volts

4.95

-1.80

No LoadZERO Level Output-0.36

COMMENTS

Load to Yee
No LoadPulse note (1) to pin 3.

= 9.5

0.8 Vto Pins 1 and 6, 2.5 V to Pin 8; Pulse to
Pin 2. Guarantees min. ONE level output.

= 9.5

2.5 Vto Pins 2 and 6, 0.8 V to Pin 8.
Pulse to Pin 6, 1.25 V to Pin 7.

ZERO Level Output

-0.36

Volts

4.95

-1.80

No LoadPulse to Pin 2, 1.25 V to Pin 6, 2.5 Vto Pin 14.

ZERO Level Output

-0.36

Volts

4.95

-1.80

No Load1.25 Vto Pin 8, 2.5 Vto Pins 6 and 7.

-0.36

Volts

4.95

-1.80

No Load'

2.5 V to Pins 2, 8, 14; 1.25 V to Pin 13.

2.25

mA

4.50

-2.0

No Load

2.5 Vto Pins 1 and 7 sequentially.

6.75

mA

4.5

-2.0

No.. Load

2.5 V to Pins 2 and 6 sequentially.
Guarantees asynchronous input loading.

ZERO Level Output
Input Current Data Input

1.5

Input Current Async. Input
Input Current Blocking Input
Output Resistor

6.75

10.13

mA

4.5

-2.0

No Load

2.5 V to Pins 8 and 14 sequentially.

10.13

mA

4.5

-2.0

No Load

2.5 Vto Pins 6 and 9,
Pins 2 and 13 sequentially.

= 9.5
F.O. = 9.5

See Fig.

Propagation Delay, t 0R

10

15

ns

4.5

-2.0

Propagation Delay, t 0 F

17

30

ns

4.5

-2.0

F.0.

See Fig.

NOTES:(1) Pulse, positive pulse of non-critical amplitude and width.
(2) F.O. =Fan-Out: F.O. = 9.5 equivalent to 1680 to -2.20 V under worst case conditions.

ELECTRICAL CHARACTERISTICS
WORST CASE POWERDISSIPATION VERSUS
POSITIVE SUPPLY VOLTAGE

tI~

WORST CASE JUNCTIONTEMPERATURE VERSUS
POWER DISSIPATIONVEE'-2.2 V

TA a25•c
7001----t---+---+--+---i

if

2i 5001---=1-==-+---+---+--li3i 3001----t--t-J.ll~-=t---l
5..
1100

4.0

4.5

20

0.2

5.0

0.4

0.6

0.8

POWER DISSIPATION-WATTS

Yee-POSITIVE SUPPLY VOLTAGE-VOLTS

4-58

1.0

CT/LL 9957 COMPLEMENTAR.Y, TRANSISTOR MICROLOGIC® IC ·TRANSFER CHARACTERISTICS. BLOCKIN8 INPUT· ONE LEVEL·OUTPUT VOLTAGE .VERSUS·TEMPERATURE

ASYNCHRONOUS SET/CLEAR-ONE
LEVEL OUTPUT VOLTAGE
VERSUS TEMPERATURE ·.
h-l--L.-J---1;.;...j.--'-'· . Yee ,4;5y

DATA INPUT • ONE LEVELOUTPUT VOLTAGE VERSUSTEMPERATURE:TA•O'cYee• 4.5 vj;;;;~F.=;~~l=;j:'.\.--1..YEE'-2.0YTa•~ftF.0.•10I 2.0 t---+-fTA• ~i

5.0 ~~1c---.-,.--.--,.-~--.--.--,TA•'o-C

l=:!=:!=:!=l=~~YE£'-2DY­~·>

lf 2.0 F=jTA •Toii'C.!, 2.0 h-1---1---1---1-41---3+.+.--l--+-....I

ti

~
~

~

~

I~

f--TA·o·c·

S 1 Ot--+--+--l---l-il--lll-blTA•25°Cl---~ 1.0 l---l--ll---+--+-11--11-11-+--+--+---i~n. ~ 1.0 ~+-+-i--1+-1-Wl--ll--ll--ll--I

So. 1-t- TA•;.::;loo'.::...i:..._.----IH-+--+-+-4~

VcJ•4.5Y

5 liiiifllliiaiil'B"i~Cf;;;;;;;;l;;o;:°"'rt-t-~~~:1~2.ov_

F.0. •10.

a~ 0 ~+-l--l--l-~\~·-1---1---1----1~ 0 l---l--ll---+--+-11--11-11-+--+--+---ig~ Oh-1--11--1---1-----+.+.--l--+-....II..........~-_..___.___.__,__.__.
0.40.11.21.&
2.Q-.l.00.,__.__.0.._4__.___.O.l_.._.;_1-'-.2--'--1.._.I_.__.2.0-1.0 L.-JL.-J--'1.--1.--l---L---L......l-.....l-....I
0
0.4
0.1
u
1.6
2.0

ASYNCHRONoiis CLEAR INPUT VOLTAGE-VOLTS

BLOCKING INPUT YOl.TAGE-YOl.TS

-1.0~

0

OATA INPUT YOl.TAGE -VOLTS

I

t--..

OUTPUT CHARACTERISTICS
AS A FUNCTION OF
TEMPERATURE

AS A FUNCTION OF
COLLECTOR SUPPLyo, VOLTAGE-TOLERANCE VARIATIONOF PARAMETERSYEE•-2.QY=
6 z.a= !---<

l"-1-+-i-

Hl---l-t-f==l"-1-~d---+-4. ··~ 2.8~.,>
~ 2.6 RF=t=t:::1.T¥YP:!£11CA!j:.L4-dkd::d-c-I

.5

~

5

-~ 2.6.....,·~ 2.41--11---+--+-+-+-+-+--;-H1--1---1
i 2.21--11---+--+-+-+-+-I Yee· 4.5Y _,;>~ 2.81--i--

..._

I

... r--!Iit-·TA •·O'C~=f.:.t.rA9·2~s'tc;;:J::--;=i:N::t-l::JH'F""-'=1.

2.61---1---1--+--+-+-l--l--l----+---I

12.4

au
I

>

VE£•·2.0V
2•0 o.,_.;_.......,.5.o_

Ve. •4.sovVo •4.osv>

r--t-t--+-.

1---1---11---1---1---1---1--+ VEE• -2.0V

v~.Jru',I'IW.;

YC['4.5Y

TA• 25'C

TA•25'C'·"

2.Q_.._10---'--1-'-5_,__20.........,___,zs0lour - OUTPUT CURRENT - ntA

s.o

10

15

20 "

2.0 L.-JL.-J--'1.--1.--L--L---L......l--l-....I
0
s.o
10
15
20
25

2~

.. lour 'OUTJIUT CURRENT- onA .

lour -OUTPUT CURRENT - onA

SWITCHING CHARACTERISTICS
INCREASE IN PROPAGATIONDEIAY DUE TO OUTPUTCAPACITANCE

PROPAGATION DELAY VERSUSAMBIENT TEMPERATURE
30

Ycc•4.5Y
YEE•-2.QY
F.0.•10 . -

25

di

J'd•

~

5.0
0
0

20

40

80

60

80

100

TA - AMBIENT TEllll£RATURE -'c80

CoUT - OUTJIUT CAPACITANCE - pF

4-59

100

~-------C_T~~-L_99_5_7_COM__P_l_E_M_EN_t_A~R_Y~TR~·A_N_S_IS_TO~R_M_··-~_RO_L_O_G_IC_®_IC________SWITCHING CHARACTERISTICS
tdr AND tdf SWITCHING TIME TEST CIRCUITTO OSCILLOSCOPE
TRACE A

t

5k

14
R.

2

••.....--TO OSCILLOSCOPE

13

3

12

4

11

5

10

6

9

E2'1ot---------.--1 7

8

I
I

Vee
VEE

168.Q

24pf

17.Q
31pf

Sk

I

*couT
I
I
I
I

~

VEE

IV\

I
I

R
168.Q

24pf

TRACE B

17.Q
31pf

5k

"

TO OSCILLOSCOPE
TRACE B

I
I

*couT
I
I

I
I

VEE

~

WAVEFORMS
INPUT E2'
PINS 7 a 8

1.0V

GND

INPUT El:PINS 1a14 .
1.0V

GND----..1

1.0V
24ns
:t0.2
1

dr}=

OUTPUT PIN 13----------OUTPUT .PIN 9

1.0V

I

L...

J c _ l . O V-

SWITCHING NOTES:(1) Vee= 4.50 V :!: 10%
VEE - 2.00 V :!: 10%

Select proper c:apacitor to provide adequate bypaaln1.
(2) Select R to provide proper termination for pulse
generator used.
(3) Use oscilloscope with at least 5 k input impedance.
(4) Rise & Fall Times:
tf = 5ns measured at 10% to 90% points.

t..

4-60

_.I

CTµ,L 9957 COMPLEMENTARY TRANSISTOR MICROLOGIC® IC
OPERATION OF FLIP-FLOPThe CTµL 9957 is a dual-rank directly-coupled R-S Flip-Flop. The first rank or "master" consists of two cross-coupled NOR gates similar to the CTµL 9952. The
second rank or "slave" employs OR ties as shown in the functional logic diagram, thereby minimizing through delay. Two NANO gates provide feedback inversion, while the other two provide gating between "master" and "slave."
The primary data inputs to the Flip-Flop are through pins 1 and 7. These inputs work directly from AND gate outputs, allowing OR ties and multiple inputs
to each Flip-Flop.
To take advantage of the dual-rank principle, mutually exclusive active inputs should be applied to the gating to "master" and "slave" so that only one or theother can change at any particular instant. This is easily accomplished in the CTµL 9957 due to the difference in active polarity of the two gates. Thus; what
appears as a logic 1 to CTµL· gates of the Flip-Flop data inputs is a logic 0 to the "slave" gates, and vice versa.
These observations lead to the connection of pin 1 to pin 14 and pin 7 to pin 8 as shown in Fig. 2. Although both "slave" gates are not necessarily inhibitedwhen a change takes place, the output cannot change unless both data inputs are logic 0. Therefore, this connection is t~e usual one, tending to minimize
the loading of timing circuits.
In case phased timing signals are advantageous, pins 8 and 14 may be used independently as long as they are never active (low) while their corresponding
data inputs are· high.
Direct inputs to both "master'' and "slave" appear on pins 2 and 6, A logic (high) on either input Sets or resets the "master" and simultaneously inhibits a
feedback NANO gate in the "slave." The net effect is that both "master" and "slave" move to the desired condition during the presence of the direct input signal.
The response of the Flip-Flop to concurrent inputs tending to set opposite output conditions is ambiguous. That is, simultaneous logic 1 inputs must be avoided
for well-defined· operation.

APPLICATION
FIG. Z DUAL RANK FLIP-FLOP CONNECTED FOR
SINGLE-PHASE CLOCKING, J-K MODE

FIG. 1 DUAL RANK FLIP-FLOP CONNECTEDFOR TWO-PHASE CLOCKING, J-K MODE

A.SET

A.SET
9954

113

113

FIG. 39957

9957

A.CLEAR

A.CLEAR

FIG. 4SERIAL BINARY COUNTER
CTfll.·9957

INPUT

NOTES:
1. On all CTµL 9957's, tie pins 1·14 and 7·8.
2. All gates. are CTµL 9953's.

4-61

1·2-4-8 DECADE9968
DUAL HIGH SPEED LATCHCOMPLEMENTARY TRANSISTOR MICROLOGIC® INTEGRATED CIRCUITS+l5°C TO +ss·c TEMPERATURE RANGE

GENERAL DESCRIPTION - The 9968 is a dual gated latch for use as a high speed buffer memory. Compatible
with all other CTµL elements, the output can be OR-tied, allowing several latches to connect to a single
data line.

TYPICAL DUAL IN-LINE PACKAGE

The 9968 combines both gating and storage facilities. To ensure that only valid information is entered, a"ONE" must be present at the WRITE input for data at the DATA input to be stored. In the absence of a
WRITE signal, the feedback loop maintains the output state caused by the last set of input conditions.
To read out the information, a "ONE" must be present on the READ input. This readout is non-destructive.
Output data is one AND gate offset below read level.
Typical delays are Write time 25 ns, Read, 3 ns. For increased storage capacity, where read delays of 25 ns
can be tolerated, refer to the 9030 8-Bit Memory Cell data sheet.
The 9968 is packaged in the hermetically sealed ceramic Dual In-Line Package (similar to JEDEC TO-ll6)
intended for low cost insertion techniques.

k.-.. 310 ___.....;
I

.290

i

I

F\
!

I.
.01!
.009

L __ 375---il -NOM ;I
I.125 TYP.-J_,- I
NOTE lFEATURES:• POWER SUPPLIES - +4.5 V :±:10% AND -2.0 V :±:10%• HIGH FAN-OUT CAPABILITY - 12
• TEMPERATURE RANGE - +1s·c TO +ss·c• INPUT AND OUTPUT GATING• NON-DESTRUCTIVE READ OUT• FAST READ TIME - 3.0 ns• LOGIC SWING OF 3.0 V

_j __

,.llO
.090

I
015 MIN.--1

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Current in or out of a pin
100 mA
Chip temperature
1so 0 cPower dissipation
1.0 Watt
Voltage applied to any input pin
10 Volts
Negative voltage applied to any input pin-4.0 Volts
Voltage applied to output pin
6.0 Volts

LOGIC DIAGRAM

1.--l. Board-dr1ll1ng dimensions should equal yourpractice for a conventional .020 hnch diameter lead

ORDER PART NO. U6A996879X

PIN CONFIGURATIONLOADING RULES
14
13

9

INPUTSLOADING*

DATA
WRITE
READ
OUTPUTS
DATA

1.0
1.0
1.0
FAN OUT
12*1Load=1 CTµLAND-OR Gate Input Load

TOP VIEW

l=AIRCHILC
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

4-62

SEMICONDUCTOR
A. DIVISION OF FAIRCHILD CAMERA ANO INSTRUMENT CORPORATIONCOMPLEMENTARY TRANSISTOR MICROLOGIC® IC 9968
ELECTRICAL CHARACTERISTICSTESTS (at TA = 25°C)

MIN.

ONE Level Output

2.35

LIMITSTYP.

CONDITIONS
UNITS

Vee

VEE

Load to VEE

Volts

4.95

-2.0

-Q.36

Volts

4.95

-1.8

ONE Level Offset

220

mV

4.05

~2.2

ZERO Level Offset

160

mV

4.95

-1.8

2.4

kn

4.5

-2.0

Write Input = 1.8 V
Data Input = 1.25 V
Read Input = 2.5 V
Write Input= 1.25 V
Data Input = 0.8 V
F.O. = 1
Read Input = 1.25 V
F.O. = 11111 Data Input = 1.25 V Write Input = 1.25 V
Read Input= 2.25 V
Write Input = 2.5 V
Data
Input= 2.5 V
F.O. = 1
Read Input = -0.36 V
Input or Output to 2.5 V
No Load

v
v

4.95
4.95
4.5
4.5
4.5
4.5

-2.0
-2.0
-2.0
-2.0
-2.0
-2.0

No LoadNo LoadF.O. = 12
F.0. = 12
F.O. = 12
F.O. = 12ZERO Level Output-0.50

Input and Output
Pull-down Resistors
ONE Latching Threshold
ZERO Latching Threshold

1.6

MAX.!''

2.0

1.25
0.8
40
40
25
30

Data delay t + +t -Write delay t+ _
t++

ns
ns
ns
ns

COMMENTSNo LoadMin. input level which provides ONE output
Max. input level which provides ZERO output
See test circuit below
See test circuit below

NOTES: (1) "Maximum" means "no more positive than"(2) F.O. = Fan-Out: F.O. = 11 equivalent to 145 D to -2.20 V under worst case conditions
F.O. = 1 equivalent to 2.4 k to -1.80 V under worst case conditions

WRITE DELAY TEST CIRCUIT
Yeet, = t 1 = 10 ns
PW @ 1.0 V ~ 50 ns
READ
I

'++l
I

9968

WRITE ONE DELAY

f"1.ovI!\i.ov--t !--•+DATA IN FOR WRITE ZERO(INVERT FOR WRITE ONE)"' lOOns DELAY FROM WRITE

PW ~50ns*Includes Probe and Jig Capacitance

Vee= 4.5 V
VEE= -2.0 V
TA= 25°C

DATA DELAY TEST CIRCUIT

Yee

Vee
l.8V

WRITE IN

1.ov ......

READ
-0.5V

DATA IN

DATA OUT
9968

TO SCOPE

1.ov----

36pF-=Vec=4.5V
VEE= -2.0 V
TA= 25°C

t++~ [IVEE

4-63

M1.1L9030
8-BIT MEMORY CELLMEMORY MICROLOGIC®INTEGRATED CIRCUITSGENERAL DESCRIPTION - The Mµ.L 9030 is a Planar* epitaxial integrated 8-bit (nonTYPICAL DUAL IN·LINE PACKAGE

destructive readout) memory cell consisting of four 2-bit words. The cell is addressable
by word.

It is permissible to write. into one word while reading another.

The same

information may also be written in two. words simultaneously. The "Write" time for acell is 45 nanoseconds maximum and the "Read" delay is 25 nanoseconds.

The element is fully compatible with Fairchild CT µ.L Circuits. The "Read"· and "Data"
inputs are the equivalent of 1.5 CT µ.L gate loads, and the "Write" inputs, 3 C'I' µ.L gateloads. The outputs can drive 3 CT µ.L gate loads.

For applications where faster "Readout" speed is essential, the users are encouraged
to investigate the properties of the CT µ.L 968 Integrated Dual Latch.

l.~•,.•lllOdllitdllJll ... nlncr11Mt11C1ion.loanl-dril11R1

4im11111an1.,,...,lf"MllJff!PP1C1ic.lor1co11nnti.n11.020lnclldllmtfforl11111.

i.Mn.-... for1Hpl1J11nldpldo1p•.ithlldtlltn""'llf.

*Planar is a Patented Fairchild Process.

LOGIC DIAGRAM AND PIN ARRANGEMENTS

11
R1

9

10

W1

R2

W2

R3

W3

4
R4

W4

D1, D2: DATA INPUTS
R1,R2,R3, R4: READ INPUTS

D1

W1, W2, W3, W4: WRITE INPUTS
01

01, Oz: OR-ABLE OUTPUTS

6

13
Vee= PIN 12

D2

GND =PIN 5

'

02

14

F=.AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

4-64

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MEMORY MICROLOGIC 9 1NTEGRATED CIRCUITS M11L9030
D.C, TESTS (Vcc ., 4.5V, T

25°C)
LIMITS
MIN
MAX

UNITS

EQUIV
CTµLLOAD

vl, v2' V3, V4 = 2.5V

4.4

mAea.

1.5

I7, I13v 7, v 13 = 2.5V

4.4

mA ea.

1.5

Write Input Current

1s• I9, IlO' Illv 8' v 9' v 10' v 11 = 2.5 v

8.8

mAea.

3

Output Voltage(High State)

V6, V14

I6, 114 = -10 mA

Output Voltage(Low State)v 6' v 14

I6, 114 = -1 mA

-0.36

v

Output Leakage

I6' I14v 6, v 14 =4V

5µA

Output Capacitance

C6, C14v 6, v 14 = 0
Boonton Bridge

8pF· DESCRIPTIONTESTRead Input Current

Il' I2' I3' I4Data Input Current

CONDITIONS

2.35

v

INPUT LEVEL: Maximum permissible "low" level = 0.8 V. Maximum required "high" level: 1.25 V.
RECOMMENDED OPERATING CONDITIONS:

The above test specifications characterize the terminal properties of the circuit under one set of conditions.

They in no way limit

the circuit to be used under different conditions where certain advantages may be achieved. In general, excessive heat generated in thecircuit presents the largest factor in degrading the performance of the circuit. For noise immunity greater than 0.5 V and operating
speed within 20% of 25°C speed, junction temperature must be kept within 0-125°C. The circuit dissipates 350 mW with VCC = 4.5 V ± 10%
and full load. (F/O = 3 CTµL Gates.)
Maximum .thermal resistances of the package from junction to air are:ioo c/w
0in still air

65°C/W

with 200 feet/min air flow

50°C/W

with 400 feet/ min air flow

For example, the circuit may be operated in still air at TA = 90°C with VCC = 4.5 V ± 10%. Higher ambient temperatures are possible
in moving air, as can be calculated from the data above.
The outputs of the MµL 9030 may be "OR-ed" with the outputs of different words. Each output terminal represents 8 pF capacitanceand 5 µA leakage current. The limit on OR'-tying outputs is the degradation of switching speed that the user can tolerate due to added
capacitance.
Fan-out of the MµL 9030 can be increased to 15 with only a slight increase in delay by buffering with the CT µL 965.
SWITCHING TIME:

Load Resista~e: 1 k to -2V- Load Capacitance: lOpF probe and jig capacitance -Input waveform rise and fall time: 6 ns

These tests are for correlations only. While t 1 through t 4 do not change with varied loads, t 5, t 6, and t 7 may differ under different
output loading conditions.

SWITCHING TIME:
l.8V

t 1: 25 ns MIN.

50%

t 2 : 10 ns MIN.
t 3 : 10 ns MIN.
t 4 : 10 ns MIN.

WRITE

t 5 : 25 ns MAX.

DATA

t1

50%

t 6 : 25 ns MAX.

t 7: 25 ns MIN.

50%
READ lNOTE:

15l) DOTTED LINES REPRUENT CELLSTORING "LOW" LEVEL.
2) t7 REPRESENTS TIME .INTERVALGND. LEVELOUTBETWEEN READ PULSES FORERROR-FREE READOUT.

l.5V---- ----

I&

.5V

I.BY

t7
READ 24-65

50%

RTµL ·COMPOSITE D,ATA,. SHEETINDUSTRIAL MICROLOGIC® INTEGRATE.D CIRCUITS·OPERATING TEMPERATURE RANGE: 0°C to +70°C (METAL PACKAGE)
15°C to, 55°C (EPOXY)a

GENERAL DESCRIPTION -The Fairchild Industrial Resistor:Transistor Micrologic® (RTµL) integrated Circuit family consists of ~umber. of medium and low power compatible integrated circuits made up. by resistor-transistor logic and capable of performing logic functions
for use in digital electronic equipment.
.

.

.

.

'

The elements of this family are manufactured using the familiar Fairchild· Planar* epitaxial process by which all the individual transistors
and resistors are diffUsed into a single silicon wafer, thus assuring a high degree of reliability.
"'Plana.r is a patented Fairchild process.
Some of the important features of the RTµL integrated ci~cuit family are the following:• Guaranteed operation over the specified temperature range.

• Power dissipation of typically 2mW per gate for the low power
elements.

• System operates.with one power supply (3.6V±10%).

• Low cost.·• Trade-off between fan-out and temperature (permitted).·• Medium power buffer 9900, dual two·illput gate 9914 and JK
flip-flop9923 available in epoxy for additional cost advantages.

• RTL uses positive NOR or negative NANO logic.
• High noise immuriity-300 rriv.

• Mixing medium and low power elements optimizes fan-out and· power dissipation.

• Very low propagation delays - typical 12 nanoseconds for
medium power gate and 40 nanoseconds for low power gate.

• Application briefs, notes and thorough individual data sheets
available.

PHYSICAL DIMENSIONS (T0-5 TYPES)
T0-99

TO·lOO(8 pin package)(10 pin package)f

PURCHASING INFORMATIONEPOXY PACKAGE
lsiinil•r to T0·5) ·

.370
.335

330 MAX.

.

3351.040-'E_~.305 ·l:;""!""Purchasing Agent please riote·:

DIA.

.2

~-+-~~~1:=!="

Ceramic

8o~~A ~~ ~ ~~ ~~- ·~r-~ir-n"'Tll!---+.400

m~ UL--.:t.016.. 200TPA B C D E F G H I
A = U for all" elements
BC= SB for 8-pin (T0-99) pkg.
= SF for 10-pin (T0-100)p~.

.2~.. .. ,,

tr"o...l_•.o'

MOTES: AH dimensions 1n iru:hes
NOT-£$: All dimensions in inches

Dimensions as per latest J-10 committee~

Leads are gold·pleted kover
Lead No. 1 internally connected= SA for 8-pin epoxy .

.100

'

4-+-.

Leads are 1old•pfated llovar ·Wei1ht is 1.12 crams

To order part, the following.numbering system should be
used to expedite handling. The·
complete number will be a ninedigit number with the designati.ons as follows:

NOTES: All dimensions in inchesl.Hds lrt 1old·pl9ted nlcket

DEFG =The four-digit number
denoting the specificelement desired
H = 2 for ·all eleriients
I;= 9 for O"C to 70"C for
metal packages,=8 for 1s•c to ss•cei:ioxy pkg.

to caseP1ckqe wei1ht.is l.321r1ms

Note: All elements are available in a metal TO-S type. package, but not necessarily in epoxy. Consult your sales representati~e.fo~·details.

F=AIRCHIL.CJ
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (41S) 962-SOll, TWX: 910·379-643S

4-66

SEMICON.DUCTOR
A'o1visrbN.OF FAlficfftL\O•CAMERA AND INSTRUMENT CORPORATION

LOADING RULES
Industrial Resistor-Transistor Micrologic~ (RTµL) integrated circuits consist of low and medium power devices. The primarydifference between a low and a medium power element Ues inthe values of the base and collector resistors associated witheach element. The medium power elements have base and collector resistors of 450 n and 640 n typical, whereas the low power
elements have typical base and collector resistors of 1.5 kn and3.6 kn respectively.
As a result of these differences in resistance values, the input
load and output drive factors (maximum input current and minimum output available current) are higher for the medium, andlower for the low power elements.

For purposes of simplification, all input load and output drive
factors have been normalized using as a basis the current required to turn on a low-power gate transistor. As a result of thisnormalization, the input load factor of the 9 914 P.lement is 3 andthe input load factor of the 9910 element is 1, thus, the 9914
requires three times as much input current. For the output drive
factors, the 9910 has an output drive factor four times less thanthat of the 9914.
The number of elements (bases) that may be drive.n by an output
terminal may consist of any combination of low and medrum
power elements as long as the sum of all the input load factors
does not exceed the output drive factor of the driving element.

LOADING CHART

LOW POWER ELEMENTS:

8

1~

1

2

7
6

1

3

5

1

8

·1~7
1
6
4

4

34

1

4
9908

1

8
2.:@:l.8 7 1 1~
1

1

2

:.
'.

3

4

5

7.

3

1

2. .

3

1

3

6

.

6

3

5

4
9910

1

5
4

8
1~

1

2

7
6

1

3

5

1

43

4

9911

9912

5

9921

.A~

:~.- ..

9900

9903

4

8
3~
7

3

6

5

9914

1

34

-0.5
-0.5

8
3y
7
:~::

MEDIUM POWER ELEMENTS:

3

76

1

1

9913

3

8
1~

16
16

3~

3~13

4

4

6

5
9915

2

3

4
9923

4-67

5
9926

6

3

16

5

3

9907

9905

:~:
~:· :~~'
3~10
3~

1

3

:~l ~:
10

3

3

3

4

98

7

5

9927

6

16
16

PARALLELING AND OTHER RULES:
1. All unused input pins should be grounded.

4. For each low-power gate output terminal tied to another low
power gate output terminal (and Vee open on an gates butone) the output drive factor should be reduced by qne load.

2. On all 8-pin lead devices, Vee is connected to pin 8 and pin 4
is grounded. On 10-pin lead devices, pins 10 and 5 are Vee
and Ground pins respectively.

5. By increasing the input load requirement by 0.75 load for me·
dium power and 0.33 for low power to cover any reduction in
base-emitter impedance, any number of gates may be placedin parallel as shown below:

3. For each medium power gate output terminal tied to anothermedium power gate output terminal (and Vee open on all gates
but one) the output drive factor should be reduced by 2 loads.

3.75

1.33 .....__

3.75
3.75 o--~~-R

1.33
1.33 v--.......---,~

3.75

o----

26

1.33

3.75

....

_,~

o----

1.33

3.75

1.33

3.75u---<'1.-~

3.75 o - - - - - '1.33 u - -......--:~
1.330----PARALLELING MEDIUM
POWER ELEMENTSPARALLELING LOW
POWER ELEMENTS• =NO Vee CONNECTED

4-68

5

9900 MEDIUM POWER BUFFER*
The Buffer element is a low-impedance
inverting driver circuit. Because of itsvery low source impedance the element
can supply substantially more output
current than the basic circuit. As a con·sequence, the Buffer element is valuable
in driving heavily loaded circuits or minimizing rise-time deterioration due to ca·
pacitive loading. A resistor is internallyconnected to the Buffer element inpµt
which may be returned to the supply
voltage if capacitive coupling is desired.
Typical applications of this type connection are astable and monostable multivibrators, and for the differentiation ofpulses.

SCHEMATl'C DIAGRAM
8

GND

4

FUNCTIONSTYPICAL RESISTOR VALUESPOSITIVE LOGIC:

R, = 4500
R1 10000
R, = 1000
R. = 10000

B=A=

NEGATI~ LOGIC:

B=A

LOADING RULES. JNPUT PIN

LOAD FACTOROUTPUT PIN .

DRIVE FACTOR

3

6

5

80

Note: For more information on loading rules and for parallel combination of elements, see page 2.

TYPICAL APPLICATIONS

9914

/1'>.
E---V--o

o--l

DRIVE

FACTOR 80

ASTABLE MULTIVIBRATORONE SHOT MULTIVIBRATOR

3.6V

300
6

HIGH FAN·OUT EXTENSIONMONOSTABLE CIRCUIT• This element also available in the epoxy package.

4-69

9903 MEDIUM POWER' THREE INPUT GATEThe Gate element is a three-input resistor-transistor-logic circuit, one of four
similar-basic NANO/NOR gates produced by Fairchild. The versatility of the
NANO/NOR function permits the generation of any logic function through theexclusive use of gate elements. Individual gate elements may be paralleled toincrease the number of inputs fo a sihgle
output node (subject to loading rules),or combined with other Micrologic® integrated circuits to augment their logic
functions.

SCHEMATIC DIAGRAM

8GND

FUNCTIONSPOSITIVE D = _A_+_B_+_C
LOGIC:=ABC

H =HIGH
L= LOW
POSITIVE LOGIC: H = 1 =TRUE
L = 0 =FALSE

4NEGATIVE D =ABC
LoG1c:="A

TYPICAL RESISTOR VALUES
R,
450!1
R, 650!1+a +c

NEGATIVE LOGIC: L = 1 =TRUE
H = 0 =FALSE==

Note: Pins 5 and 7 omitted.

LOADING RULES

TRUTH TABLE
A

B

c

D

H
H
H
H
L
L
L
L

H
H
L
L
H
H
L
L

H
L
H
L
H
L
H
L

L
L
L
L
L
L
L
H

INPUT PIN

LOAD FACTORSOUTPUT PIN

DRIVE FACTORS

1

3
3
3

6

16

2
3

Note: For more information on loading rules and for parallel combination of elements, see page 2.

TYPICAL APPLICATIONS'Vee
Ao---efVeex

B0---9--;;Do-9--..---0

co---o...

TRIGGER INPUT

9900
OUTPUTD o----cr

E o--+~~:-9----'
F u------<>VCC NOT CONNECTEDMONOSTABLE CIRCUITSIX INPUT GATEPOSITIVE LOGIC:_ _ _ _ __A+B+C+D+E+F=A·B·C·D·E·F
NEGATIVE LOGIC;___
A·B·C·D·E·F=A+B+C+D+E+F

4-70

9904 MEDIUM POWER HALF··ADDERThe Half·Adder element is a multipur·
pose combination of three basic Circuits.
The configuration ;is well-suited as acomplete half-adder, an exclusive OR
gate, or any otber similar logic construction. Output No. 7 is a noninverting func:tion of the four inputs, whereas output
No. 6 may be considered as either a
NANO or a NOR gate.

SCHEMATIC DIAGRAM
8GND

FUNCTIONSPOSITIVE E = C + D
LOGIC: F = (A+ B) (C + D)
NEGATIVE E =CD
LOGIC: F = AB + CD
H =HIGH
L= LOW
POSITIVE LOGIC: H = 1 =TRUE
L = 0 =FALSE

IFC;,,, A and D = B
POSITIVE E = AB
LOGIC: F :::: AB + AB

.NEGATIVE LOGIC: :L = 1 =TRUE
H = 0 =FALSE

NEGATIVE E =A+ B
LOGIC: F = AB + CD

1
H
L
H
H
H
L
L
L
H
H
.H
L
L
L
H
L

2

3
H
H
H
L
H
H
L
H
L
H
L
L
L
H
L
L

H
H
L
H
H
L
H
H
L
L
H
L
H
L
L
L

4

5

TYPICAL RESISTOR VALUES

R, = 45ori

R, = 640U
R,'·= soon

LOADING RULES

TRUTH TABLE
INPUTS.2OUTPUTSINPUT PIN

LOAD FACTOROUTPUT PIN

DRIVE FACTORS

3
3
3
3

6
7

16
13

5

7

6

1

H
H
H
H
L
H
H
L
H
L
L
H
L
L
L
L

H
H
H
H
H
L
H
H
H
···H

L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
H

2
3
5

L
L
L
L
L
L

Note: For more information on loading rules and for parallel combination of elements, see page 2.

TYPICAL APPLICATIONS

X10--~-rY10---ir

A"'--...rB

X10---1....'--~""n----o F = (A+B)·E

Y1u-----..............L-'..Jr---u E= C+F

c 0----10.....'----:-P.--'

X20--~,r~-~~-~--~---lY20--~.

GATED .FLIP • FLOP

X2 o---1....'-'-~
Y2n-----Z IS HIGH WHEN X1 = Y1
ANDX2=Y2

PARALLEL COMPARISON

4-71

z

9905 MEDIUM POWER HALF '.SHIFT REGISTER
The Half Shift Register element is agated input storage element composedof five basic gate circuits. Internal crossconnectioi:i of the two output gate circuits provides memory. The input gating
signal is applied to the remaining threegate circuits. Two of these control the
logic inputs, while the third provides thecomplement of the gating signal at an
output pin. Because of the two cascadedinternal logic levels, the unit changes
state in response to near-ground input
signals. Consequently, from a terminal
standpoint, the unit should be regarded
as requiring NANO input logic levels.
Concurrent near-ground signals at all
three inputs will cause near-ground signals at both outputs.
H =HIGHL=LOW
POSITIVE LOGIC: · H = 1 = TRUE
L = 0 =FALSE
NEGATIVE LOGIC: L = 1 =TRUE
H= 0 =FALSESCHEMATIC DIAGRAM
8GND

FUNCTIONSPOSITIVE A1 = 8, (Ao + P)
LOGIC: B, =A, (Bo + P)
NEGATIVE A,= lf, + AoP
LOGIC: Bo =A, + BoP

4

TYPICAL RESISTOR VALUES
R,
4500
R,
6400
R, = 8000==

TRUTH TABLE
INPUTLOADING RULESOUTPUT

H
H
H
H
L
L
L

p
H
H
L
L
H
H
L

H
L
H
L
H
L
H

A,
H
H
H
H
L
L
L

B,
L
L
L
L
H
H
H

L

L

L

L

L

Ao

Bo

INPUT PIN

LOAD FACTOROUTPUT PIN

DRIVE FACTOR

1

3

2
3

9

5
6
7

13
16
13

3

Note: For more information on loading rules and for parallel combi.nation of elements, see page 2.

TYPICAL APPLICATIONSCOUNTING DECADE
Rj;sETOUTPUT---+------+---!~-------......----+----!~----------------+________________....,.___t - 0

TRANSFER

INPUT

0

L__r

COUNTING DECADE WITH MEMORYCOMPLEMENTARY FLIP-FLOP

4-72

9907 MEDIUM POWER FOUR INPUT GATEThe Four-Input Gate element is a fourinput resistor-transistor-logic circuit, oneof four similar NANO/NOR gates produced by Fairchild. The versatility of the
NANO/NOR function permits the generation of any logic-function through the exclusive use of four-input gate elements.
Individual four-input gate elements may
be paralleled to increase the number of
inputs to a single output node (subject
to loading rules), or combined with otherMicrologic® integrated circuits to augment their logic functions. This element
performs the AND and exclusive OR
function. It is also used to select one oftwo data streams under control of a single gate signal.
H =HIGH
L= LOW
POSITIVE LOGIC: H = 1 =TRUE
L = 0 =FALSE
NEGATIVE LOGIC: L = 1 =TRUE
H = 0 =FALSESCHEMATIC DIAGRAM

8GND

FUNCTIONSPOSITIVE E = _A_+___B_+_C,__+_D,,_LOGIC:=AB CD
NEGATIVE E = A B C D
LOGIC:= A + B + C+ 5

A
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L

B
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L

c
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L

D
H
L

TYPICAL RESISTOR VALUES
R1 450\Q=

R, = 6400

TRUTH TABLE
INPUTS

4

LOADING RULESOUTPUTINPUT PIN

LOAD FACTORSOUTPUT PIN

DRIVE FACTORS

_L

1
2

3
3
3
3

6

16

H
L
H
L
H
L
H
L
H
L
H
L
H
L

L
L
L
L
L

3
5

L.

L
L
L
L
L
L
L
L
L
H

Note: For more information on loading rules and for parallel combination of elements, see page 2.

TYPICAL APPLICATIONS
An---r
BO--Q-i"l!Do-Q~.---ol4

c O---Q.!:-:-"":R
Do-----'

En--....rF O----<~C>'<-9---'GO---Q.!~":R
H<>----~VCC NOT CONNECTEDEIGHT INPUT GATEPOSITIVE LOGIC:
A+B+C+D+E+F+G+H=ABCDEFGH
NEGATIVE LOGIC:ABC DE FG H =A+ 8 + C + D + E + F + G + H

4-73

9908 LOW POWER ADDERThis element performs the AND and
exclusive OR function. It is also used
to select one of two data streams undercontrol of a single gate signal.

8

SCHEMATIC DIAGRAM

24FUNCTIONSPOSIIIY.E..J_OGIC:
6 = (3 + '5) = 3. 5
7 = (1 + 2) (3 + 5)
NEGJU.!Y.E LOGIC:
6 = (3. 5) = 3 + 5

H =HIGH
L= LOW
POSITIVE LOGIC: H = 1 =TRUE
L = 0 =FALSE
NEGATIVE LOGIC: L = 1 =TRUE
H = 0 =FALSE

3

5

6

L
L
H
H

L
H
L
H

L
L
L
H

R, = l.5kn
R, = 3.6kn

LOADING RULES

II, Output "7''
1
L
L
L
L
H
H
H
H

TYPICAL RESISTOR VALUES

7 = 1·2 + 3.5

TRUTH TABLE
I, Output "6"4

INPUT PIN

LOAD FACTOROUTPUT PIN

DRIVE FACTOR

6

7

3
4

2

6

7

1

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

L
L
H
L
H
L
H
L

2

1
1

3
5

1
1

• For loading rule explanations see page 10.
Note:. For more information on loading rules and for parallel combination of elements,
see page 2.

TYPICAL APPLICATIONS (POSITIVE LOGIC)Ai+ AB (SUM)

2

7

3

5

-

4

EXCLUSIVE OR GATE

DATA

Ac--;::t::I:>o---~r"'l1(A+C)(B+C)ORAC+iic..--.:>L...J--'---l'I 7

2

3
DATA io---+-c11>....1
5,

4

-=
DATA STREAM SWITCH

4-74

9909 LOW··-POWER··euFFER
This element is a low-output impedance,
two-input inverting drive_r. _It can supply
substantially more output current thanthe basic circuit to provide higher fanout or drive capacitive loads. A resistor
is connected internally to one Qf the inputs which may be returned to the sup. ply voltage if capacitive coupling is. desired.

SCHEMATl.C DIAGRAM ·64FUNCTIONS.

POSITIVE LOGIC:

6=2+3

4

NEGATIVE LOGIC:

6.=2·3.

._ .

TYPICAL RESISTOR VALUES

R1=1.5kn
Ri =3.6kn
R• = lOOn

LOADING RULESi' ..

INPUT PIN.

LOAD FACTOR

2
3

2
2

OUTPUT PIN_

DRIVE FACTOR

30

Note: For: more irif'ormatio~ on 1oadi!1g rules. and for pa,ra11e1 combin.ation of elements, see. page 2.

Yee

>'

TYPICAL APPLICATIONS
IN

OUT

2

ONE SHOT MULTIVIBRATOR

FOUR BUFFERS CONNECTED ASFREE RUNNING.'MULTIVIBRATORPARALLEL PULSE DRIVER

4-75

9910 LOW POWER DUAL GATE .
This element can be used on a NOR gate,
Double Inverter RS flip-flop or as a pairof Inverters. It can also be used withthe gate expander to increase its fan-in
capacity.

SCHEMATIC DIAGRAM

8

8

6

2

4

FUNCTIONSPOSITIVE LOGIC:
7=1+2
6=3+5
NEGATIVE LOGIC:
7 = 1·2
6=3·5

H =HIGH
L= LOW
POSITIVE LOGIC: H = 1 =TRUE
L = 0 =FALSE
NEGATIVE LOGIC: L = 1 =TRUE
H = 0 =FALSE

TRUTH TABLEOUTPUT 7
1
L
L
H
H

2
L
H
L
H

3
L
L
H
H

TYPICAi. RESISTOR VALUES

R, = l.5kn

R, = 3.6kn

LOADING RULESOUTPUT 6
7
H
L
L
L

4

5
L

INPUT PIN

LOAD FACTOROUTPUT PIN

DRIVE FACTOR

_§_

1

2

7

4
4

3

1
1
1

6

H
L
L
L

5

1

H

L
H

Note: For more information on loading rules and for parallel combination of elements, see page 2.

TYPICAL APPLICATIONS

Vee
R

A

c
OUT
SINGLE DUAL GATE AS
FREE-RUNNING MULTIVIBRATORSIMPLE INVERTER

R2 = 3k'2
R1S12kC ~ lOOpF------oouT
SINGLE OUAL GATE USED AS
A ONE-SHOT MULTIVIBRATOR

MOD· 5 BINARY COUNTER

Function: To count to a Modulo of 5 using a 1-2-4
code, or to divide an input frequency
by a factor of 5.
4-76

9911 LOW POWER DUAL GATE WITH INVERTERThis element is a general purpose four.
input gate with inverter for NOR, OR
functions and can also be used as anamplifier-inverter.

8

SCHEMATIC DIAGRAM
8420--o'VVI.----+---'
30--.1\M----1,___

FUNCTIONSH =HIGH
L= LOW
POSITIVE LOGIC: H = 1 =TRUE
L = 0 =FALSE
NEGATIVE LOGIC: L = 1 =TRUE
H =0= FALSE_.

50--'VVI.---+--------+----'POSITIVE LOGIC:.
7=1+2+3+5
6-1+2+3+5
NEGATIVE LOGIC:
7=1·2·3·5
6 = 1·2·3·5

4

TYPICAL RESISTOR VALUES

R,
R.

= l.5kn= 3.6kn

LOADING RULES

TRUTH TABLE
1

2

3

5

6

7

INPUT PIN

LOAD FACTOROUTPUT PIN

DRIVE FACTOR

L
L
L
L
L
L
L
L
H
H·
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

H
L··
L
L
L
L
L
L
L
L
L
L
L
L
L
L

L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

1
2
3
5

1
1
1
1

6
7

3
4

Note: For more information on loading rules and for parallel combination of elements, see page 2.

TYPICAL APPLICATIONS

A~S A
7

2

3

&

A

5
4

CONNECTED AS INVERTER·AMPLIFIER

MODULO 9 BINARY COUNTER

Function: To count to a Modulo of 9 using 1-2-4·8 code,or to divide an input frequency by a factor
of 9.
··

4-77

9912 LOW POWER HALF ADDERThis element is a multipurpose combination of three basic circuits that can beused as a complete half adder, an exclusive OR gate, gated-set flip-flop or any
other similar logic construction.

SCHEMATIC DIAGRAM
8

2

6

4

FUNCTIONSPOSITIVE LOGIC:
7 = (1 + 2). (3 + 5)
6=1·2+3·5
NEGATIVE LOGIC:
7=1·2+3·5
6 = (l + 2). (3 + 3)

H =HIGHL=LOW
POSITIVE LOGIC: H = 1 =TRUE
L = 0 =FALSE
NEGATIVE l.,OGIC: L = 1 =TRUE
H = 0 =FALSE

TYPICAL RESISTOR VALUES
R, = 1.5k!2
R, = 3.6k!2

LOADING RULES

TRUTH TABLE
1

2

3

5

6

7

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

H
H
H
H
H
L
L
L
H
L
L
L
H
L
L
L

L
L
L
L
L
H
H
H
L
H
H
H
L
H
H

ff

INPUT PIN

LOAD FACTOROUTPUT PIN

DRIVE FACTOR

1

1

6

4

2
3
5

1

7

3

1
1

Note: For more information on loading rules and for parallel combination of elements, see page 2.

TYPICAL APPLICATIONS (POSITIVE LOGIC)EXCLUSIVE OR GATE OR HALF ADDER

CON~~~~~~ ~ Do-,CONTROL C~ ~o;--:DATAB~DATA STREAM SWITCH=:~.~~'~Joo
GATED R·S FLIP-FLOP

4-78

6

(A+C) (B+C)

9913 LOW POWER TYPE D FLIP FLOPThe 9913 is a gated flip-flop very suit·able for shift registers and control cir·
cuitry. The state of the input at pin 2 isstored in the element when the input at
pin 1 changes from logical "l" to logical"O:' The element can be reset only whenpin 1 is maintained at a logical "l" during the time that pin 7 undergoes achange from a logical "O" to a logi·
cal "l:'SCHEMATIC DIAGRAM

2

6

4

FUNCTIONSDIRECT INPUTS' GATED INPUT't = n t=n+l
3 7
5
2
6
6
5
L L NC NC'
H
H
L
L
L H L
H
L
H
H L H
L
L
H H L

TYPICAL RESISTOR VALUES
R, = l.5k12
R, = 3.6k12
R. = 18012
R, = 48012(1) Pin 1 must be high.
(2) NC= No change.
(3) Pins 3 and 7 must be low.

LOADING RULES

H =HIGH
L= LOW
POSITIVE LOGIC: H = 1 =TRUE
L = 0 =FALSE

INPUT PIN

LOAD FACTOROUTPUT PIN

DRIVE FACTOR

1

2

2
3
7

1
1
1

5
6

3
3

NEGATIVE LOGIC: L = 1 =TRUE
H = 0 =FALSE
Note: For more information on loading rules and for parallel combination of elements, see page 2.

TYPICAL APPLICATIONSPARALLELDATAPARALLELDATASHIFT REGISTER STAGES USING TYPE D FLIP-FLOP~~-™1t----~-GND--

BINARY RIPPLE CARRY COUNTER STAGES USING TYPE D FLIP·FLOP--. 4-79METHOD OF PARALLEL ENTRY OF DATA INTO SHIFT REGISTER
Vee AND GROUND CONNECTIONS ARE NOT SHOWN

9914 MEDIUM POWER DUAL TWO INPUT GATE*The Dual Two-Input Gate element is adual combination of two-input resistortransistor-logic circuits, one of four similar basic NANO/NOR gates produced by
Fairchild. The versatility of the NANO/
NOR function permits the generation of
any logic-function through the exclusive
use of dual two-input gate elements. In
addition to the applications of othergate-type elements, the dual two-input
gate element circuits may be cross-con·nected to form a flip-flop, or in tandem
to form non inverting gates.

8

SCHEMATIC DIAGRAM
A
B

8

c
4

GND

FUNCTIONSPOSITIVE LOGIC:F =A+ B =AB

H =HIGH
L= LOW
POSITIVE LOGIC: H = 1 =TRUE
L = 0 =FALSE
NEGATIVE LOGIC: L = 1 =TRUE
H = 0 =FALSE

4

E = c + D =CD

NEGATIVE LOGIC:
F= AB= A+ B
E =CD= C + D

TYPICAL RESISTOR VALUES

R, = 450n
R, = 640n

LOADING RULES

TRUTH TABLEA8FINPUT PIN

LOAD FACTORSOUTPUT PIN

DRIVE FACTOR

H
H
L
L

H
L
H
L

L
L
L
H

1

2
3
5

3
3
3
3

6
7

16
16

Note: For more information on loading rules and for parallel combination of elements, see page 2.

TYPICAL APPLICATIONS
A
B
co--~-71
on----~

FOUR INPUT GATEPOSITIVE LOGIC:
A+B+C+D=A·B·C·D
NEGATIVE LOGIC:
ABCD=A+B+c+oD
Ev---...--~

Fv----SIX INPUT GATE

16
16
RS FLIP-FLOPINPUTTWO INPUT GATEPOSITIVE LOGIC:
A+B=A·B
NEGATIVE LOGIC:
A·B=A+B

OUTPUT

1

3

6

7

L
L
H
H

L
H
L
H

NC
L
H

NC
H
L

NOT ALLOWED
NC = No change.

*This element also available in the epoxy package.

4-80

S

76
S~
13
2
13

PIN NUMBERS

R

3

5

4

9915 MEDIUM POWER DUAL THREE INPUT GATEThe Dual Three·lnput Gate element is adual combination of three-input resistor·transistor· logic circuits, one of four simi·
lar basic NANO/NOR gates produced by
Fairchild. The versatility of the NANO/
NOR function permits the generation of
any logic-function through the exclusive
use of dual three-input gate elements. In
addition to the applications of othergate-type elements, the dual three-input
gate element circuits may be cross-con·nected to form a flip-flop with 2 set and2 reset inputs, or in tandem to form non·inverting gates.

H =HIGH
L= LOW
POSITIVE LOGIC: Hl
TRUE
L
0 =FALSE
NEGATIVE LOGIC: L = 1 =TRUE
H = 0 =FALSE

= =

=

10
A

H

B

G

c

F

D

E

SCHEMATIC DIAGRAM

9

4

5

GND

FUNCTIONSPOSITIVE LOGIC: __ _O=A+B+C::;;::ABC
H=E+F+G=EFG
NEGATIVE LOGIC:
O=ABC=A+B+C
H=EFG:::EFG

2

5

8

•

TYPICAL RESISTOR VALUES

R,

Ri

=4500

= 6400LOADING RULES

TRUTH TABLE
A

B

c

0

H
H
H
H
L
L
L
L

H
H
L
L
H
H
L
L

H
L
H
L
H
L
H
L

L
L
L
L
L
L
L
H

INPUT PIN

LOAD FACTORSOUTPUT PIN

DRIVE FACTORS

l

3
3
3

4
9

16
16

2
3
6
7
8

3
3
3

Note: For more information on loading rules and for parallel combination of l!llements, see page 2.

TYPICAL APPLICATIONS
so----r::;::.0...----013sR:o-.------'
Ro------'RS FLIP-FLOP

Ao---a-.:='°Q-__,.,_-030
Bco--...o..::~

Do-----~ o-----_.
SIX INPUT GATEPOSITIVE LOGIC:
A+ B + c + D + E + F = A·B·C·D·E·F
NEGATIVE LOGIC:
A·B·C·O·E>F=A+B+C+D+E+F

4-81

'.9921 LOW POWERGATE'EXPANDER
This element is a double gate without·the node resistors: Its output terminals
may be connected in parallel to those of
the 9910 or 9911 elements to increase
the fan-in capability of the circuit. Pin
8 of the element must always be connected to Vee.

8

SCHEMATIC DI.AGRAM
664FUNCTIONS

4POSITIVE LOGIC:

7=1+2
6=3+5

TYPICAL RESISTOR VALUES

R, = l.5kn

NEGATIVE LOGIC:

7 =TI
6=3-5

LOADING RULESINPUT PIN

LOAD FACTOR

OUTP.UT PIN

1

1
1
1
1

6
7

2
3
5

DRIVE FACTORS

-0.5
-0.5

Note: For more information on loading rules and for parallel combination of elements, see page 2.

TYPICAL APPLICATIONS

.1.0
1.0

4

1.33

3.5

3

1.33

3.5

1.33

1.33

1.33

1.33

1.33
1.33
1.33

1.33
1.33

1.33

.· ("

1:33

4-82

9923 MEDIUM POWER JK FLIP FLOP*The 9923 Industrial Flip-Flop is a fully
integrated, monolithic circuit: This element is designed for use in industrial
shift-register and binary counting applications. The 9923 JK Flip-Flop is compatible with the basic Industrial Micrologic~ integrated circuit family and isguaranteed to operate at a frequency of
2.0 MHz minimum over the 0°C to 70°C
temperature range.

SCHEMATIC DIAGRAM
674FUNCTIONSCLEAR OUTPUT(3)(7)
t = n t = n +1
H
X"
L
H
H
L
L
X"

SET
(1)

H
H
L
L

3 ' '

H =HIGH
L=LOW
X IS THE OUTPUT STATEAT TIME n
A HIGH ON PIN 6 WILL PRESETOUTPUT PIN 7 LOW

TYPICAL RESISTOR VALUES

R, = 260!J

R. = 300il

R, = 450n
R, =640il

R, = 700n

LOADING RULESINPUT PIN

LOAD FACTOROUTPUT PIN

DRIVE FACTOR

1

3
5
3

5
6
7

10
3
10

2
3

Note: For more information on loading rules and for parallel combination of elements, see page 2,

TYPICAL APPLICATIONSDECODING

TRUTH TABLE

0

1

2 3

CT

x

y

z

0

L
H
H
H
L
L

L
L
H
H
H
L

L
L
L
H
H
H

1
4

5

2
3
4
5

1

x
x

y

x
x
y

2

z

y

z

z
y
z

TIME DIAGRAM:

RESET
CP
CP

,J
MODE SUPPRESSOR

Y------'MOD 6 SHIFT REGISTER COUNTER WITH DECODING
z-------~• This element also available in the epoxy package.

4-83

I
I

9926 MEDIUM POWER JK FLIP FLOPThe Fairchild JK Flip-Flop is a complete,
general-purpose, storage element suit·able for use in shift registers, countersor any type of control function.
The JK Flip-Flop c!iffers from ordinary
RS Flip-Flops in that no ambiguous output state can result from simultaneous
one inputs. In the JK Flip.Flop simulta.
neous ones on both the set and clear
inputs cause the output state to toggle(reverse). This feature enhances the OP·
eration of the JK Flip·Flop in binary
counters. as no external feedback con·nections are required. The toggling ac.
tion can also be used to advantage forminimizing the logic structure of con·trol units.
The unique input triggering circuit per·mits the JK Flip-Flop to respond to negative clock pulse transition$ as short as 1
nanosecond or as long as 100 nanoseconds.
Asynchronous preset and preclear inputs are included for presetting cou.nten~. inserting parallel data in registers,
and similar applications.
This element is guaranteed to operate
at a frequency of 8.0 MHz minimum(20.0 MHz typical) over the o·c to70"C temperature range.

SCHEMATIC DIAGRAM

10

16

3
6

9"1"

16

3
5

SET
(2)

FUN(:TIONS
Cl,.EAR OUTPUT
(4)
(9)
t
n
t
n +l

=

=

x•

H

H
L

L

H

L

L

L

X"

H

H

H=HIGH
L=LOW
X IS THE OUTPUT STATEAT TIME n

5GND'l. •TYPICAL RESISTOR VALUES
R, = 3kn
R1 = 900n R,
640n R,== 5500R, =1.0kn R. = 1oon R. = soon Ra = 300n
LOADING RULESINPUT PIN

LOAD FACTORSOUTPUT PIN

DRIVE FACTOR

1

3
3
6
3

7
8
9

16
3
16

2
3
4

Pin configurations for T0-5. Cerpak and Flatpack are identical.

TYPICAL APPLICATIONS.,__)....,..

COUNT

LO=GATE

)

9914

9914

9914
PARALLELl

PARALLEL2

PARALLEL4

9914

PARALLELS

LEAST SIGNIFICANT STAGE

9914

PARALLEL 16
MOST SIGll!IFICANT STAGE

BINARY COUNTER AND SAMPLING CONTROLRESET().,...-------"..__-----+-------+..+--1------'
9914

1·2·4·8, MOD 10, COUNT UP COUNTER (POSITIVE LOGIC)

4·84

SAMPUNGCONTROL9927 MEDIUM POWER QUAD INVERTERThe Quad Inverter element is a fouri n put resistor-transistor-logic inverter
circuit. This circuit is very useful wherea complement of several signals is desired simultaneously.

A'"'--~-._.,...,___ _,.,. H

SCHEMATIC DIAGRAM

B..,-y....._-bo-__..."('""-vG
10

C

F

DV-~:U.,.__,..,~V:--"U E
5GND

FUNCTIONSPOSITIVE AND
NEGATIVE LOGIC:

H=A
G=B
F=C
E = i5TYPICAL RESISTOR VALUES
R, = 450!1
R, = 640!1

LOADING CHARTLOADING RULESINPUT PIN

. '1
2
3

4

LOAD FACTORSOUTPUT PIN

DRIVE FACTOR

3
3
3
3

6

16
16
16
16

7
8
9

10

3

16

3

16

3

16

3
Note:
For more information on loading rules and for parallel combination of elements, see page 2.

TYPICAL APPLICATIONSDELAY INTRODUCED IN EACH STAGE IS A FUNCTION OF RC TIME CONSTANTPULSE DELAY /SHAPER CIRCUIT

4-85

16
5

LOW POWER ELEMENTS ·· PROPAGATION DELAY GUARANTEED LIMITS
ns(max)ELEMENT

'cc

9908

t1-7+
t,.,_

80
100

7cE iii
GROUND
UNUSED':"INPUT PIN

9909

t,.,_
t1-•+

w... iii_

cc

90
70

GROUND
UNUSED-;:- INPUT PIN

9910

ti-7+
t,.,_

40
50

sv: iii_
...

TP

~

"0

7!100

16pF

fD600

GROUND-:- UNUSEDtNPUTPINS

Vee

9911

t,_,_
t1+1+

·mJfr,.
L

70
90

Li

GROUND-=- rN~~~s:,~s

9912

100
80

GROUND':' 1.8V

9913

t1-s-, t,_,_t1-s+, ti-•+

•cc

80
120

f'"
t,.,_, t,_,.

t,_,_, t,_,_":' ~N~UJ,.EglNS'cc

60 min30 min

'10

I20pF

4-86

_

GROUND
UlllUSED-INPUTPINSMEDIUM POWER ELEMENTS·· PROPAGATION DELAY GUARANTEED LIMITSELEMENT

MAX.

9900

32 ns
32 ns

PROPAGATION DELAY AND TOGGLE TEST CIRCUIT FOR JK 9923 OR 9926
+Vee

SCOPE
IN

6800±5%
A

20 ns
32 ns

9903

TOP VIEW

510

T0-5
+Vee

9905

t2+6- .
t2-6+

tr+7+

t,_,_

9904

9907

D = FD600 at temperature ofelement under test.
Capacitance values include jig
and probe.

30 ns
26 ns
42 ns
42 ns

SYNC

20 ns
32 ns
38 ns
38 ns

t2+•t2-6+

9914

20 ns
32 ns

~-____..'

20 ns
32 ns
SWITCHING TIME TEST CIRCUIT: (FOR A GATE TYPE DEVICE)
Vee

9915

9923

20 ns
32 ns

t2-1+

t,_,_
t2-s+

t,_,_

9926

'L-•+

t,_._

t3-7+

t,_,_

9927

t2+8t2-s+

80 ns
50 ns
80 ns
50 ns

60 ns
.60 ns
60 ns
60 ns

20 ns
32 ns

0.5V

v

tx

0.5V

}-~~if'
0.5V

0.5V

PIN 2

PIN 4

±Y :j:

lWlJ

input pin
input slope.
output pin
output slope

Switching time test circuit shown above is for µL 9915, but the
input and output loading circuit shown is the same for Micrologic 9900, 9903, 9904, 9905, 9907, 9914, and 9927 elements. By appropriately connecting the input and output pinsof the device under test (D.U.T.) in the circuit above, switching speeds could be measured in any of the said elements.

4-87

9997 FOUR BIT SHIFT REGISTER
INDUSTRIAL MICROLOGIC® INTEGRATED CIRCUITOPERATING TEMPERATURE RANGE 0°C TO 70°C

GENERAL DESCRIPTION - The Micrologic® Integrated Circuit Four-Bit Shift Register is a fully integrated,monolithic digital circuit which is manufactured using the patented Fairchild Planar* epitaxial process.

TYPICAL DUAL IN-LINE PACKAGE(In accordance with JEDEC T0-116)

THE 9997 FOUR-BIT SHIFT REGISTER consists of four series connected Flip-Flops and the circuitry required
for triggering and resetting the Flip-Flops. Each Flip-Flop has a common reset input, a parallel (asynchronous)
input, data input, and a non-inverted, buffered output which receives power from a separate voltage supply(Vee'> that is common to all outputs.
The separate voltage supply (Vee'> is independent of the Vee terminal, i.e., the circuit will operate with
Vee= 5.5V and Vee'= 3.3V or Vee= 3.3V and Vee' = 5.5V, etc.
Typical applications include: Serial shifting, parallel shifting (static storage register), serial input-parallel
output, parallel input-serial output, and shift counters.

FEATURES•SERIAL OPERATION WITH PARALLEL ENTRY TO ALL BITS

•
•
•
•

ASYNCHRONOUS GANGED RESET CAPABILITY
WIDE Yee RANGE- COMPATIBLE OPERATION WITH SEVERAL LOGIC FAMILIESOUTPUTS CAN BE GATEDSINGLE LINE SERIAL INPUT•HANDLES BLOCKS OF FOUR BITS OF DATA COMMON TO MANY PARALLEL/SERIAL AND SERIAL/PARALLEL OPERATIONS•CAN DRIVE 40 CCSL UNIT LOADS

l.Ludsare111tendedfor'"n•t1on1nholerowson.300"c1nters.Theyere
purposelysh1ppedw1ttt'pos1t1v1"(.350Jm1ul1gnm1nttof1c1ht1ternsert1on

ELECTRICAL CHARACTERISTICS
Operating Voltage Range

2.801rd-dr1H1ngd1mens1onssho11ldequa1yourpract1ceforaconventional.020
inchdoametarlud.

PURCHASING INFORMATION:
To order this device specify U6A999729X.

3.3 to 5.5 Volts
D.C. to 5.0 MHz

Minimum Shifting Rate
Typical Shifting Rate

D.C. to 7.0 MHz

380 mW
260 mW

Maximum Power Dissipation (Yee'= Vee>
Maximum Power Dissipation (Ve~/ = open)

NORMAL OPERATIONSERIAL SHIFTING-A high to low voltage transition at the trigger input (T) initiates the following simultaneous state transfers: D-+Qp Q1-+Q2 , Q2 -+Q 3, andQ3-+Q4.
RESET AND PARALLEL ENTRY -A high voltage level at the reset input (R) overrides all other inputs and causes all four Flip-Flops to be reset such that
the Q1, Qv Q3, and Q4 outputs assume a high voltage level and remain high after removal of the reset signal. After removal of the reset signal, a highvoltage level at a set input (S 1 through S4) will cause each Flip-Flop to be set such that its corresponding output (Q 1 through Q4) will be at a low voltage
level. No change of state will occur if a set input is at a low signal level.
Note that since the buffered outputs receive power from a separate voltage supply they can be gated (or enabled) by gating the voltage applied to Pin 13. Thisfeature is useful from a logical viewpoint, as well as a power conservation consideration. The gated emitter-follower circuit shown on the back of this sheet isrecommended.
" Planar is a patented Fairchild process.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

4-88

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATION

9997 FOUR BIT SHIFT REGISTERBLOCK DIAGRAMSz

BUFFER

GATED
E.F.

FOUR BIT SHIFT REGISTER ( PRODUCT CODE 9997 ) BLOCK DIAGllAM

TYPICAL TIMING DIAGRAMPINNOSYMBOL

10
II

SERIAL SHIFT REGISTER WITH GATED OUTPUTS.

TIMING DIAGRAM

Vee

eP
DATA
ENABLE--------~

01--------...J~~--------~
03~---------------­
Q4~--------GATED EMrtTER FOLLOWER

MODULO 8 SHIFT REGISTER COUNTER(Shifting Rate Test Circuit)
TIMINGDIAGRAM

4-89

LOW POWER RTµL
PLANAR* EPITAXIAL LOW POWER RESISTOR-TRANSISTORMICROLOGIC ® INTEGRATED CIRCUITSWHAT IS LOW POWER RTµL?
Fairchild Low Power RTµL Integrated Circuits are a set of compatible,
integrated logic building blocks. The elements are manufactured using
the Fairchild Planar* epitaxial process by which all the necessary transistors and resistors are diffused into a single silicon wafer. The 'individual RTL gates within the logic blocks are interconnected by metalover oxide.

PURCHASING

INFO~MATIONPHYSICAL DIMENSIOMI(SIMILARTOTo-5)

Purchasing Agent please note:
To· order part, the following
numbering system should be
used to expedite handling. The
complete number will be aseven digit number with thedesignations as follows ..

SPEED AND POWER
Low Power RTµL is characterized by very low propagation delays at low
DC power dissipation. Typical propagation delay for the basic RTL circuit is 40 nanoseconds, and its power dissipation. is o/PiCi!lllY 2 mW..

ABCDEFGA= 9 for all elements.

B= 5 for the T0-5 package.
1 for the flat package.

CDE ='the four digit number
denoting the specific element desired (I.e. thebuffer) would be 9909.

ABSOLUTE MAXIMUM RATINGS (25°C Free Air Temperature)
Maximum voltage applied to pin 8 (continuous)
BV
Maximum voltage applied to any input pin±4.0 volts
Storage Temperature-65°c to +150°c
Maximum Power Dissipation
250mW
Maximum Voltage applied to pin 8 (Pulsed, ~ 1 second)
12VF= 2 for Planar epitaxialG= 1 for -55°C to +125•coperation.

material.

NOTt&;D1m..,.,ons11Plfl•lntJ.IO_...,_
Nl<lm•.,....,1 ,n1nch11
i.url•••uold·Plal•dllowllr

l'lollllltweostit"l.221•-•

AMBIENT TEMPERATURE OPERATION
Low Power RTµL Integrated Circuits may be used in accordance with the Loading Chart below through the full military temperature
range of -55°C to +125°C. Nominal Supply voltage is 3.00 Volts. The Loading Chart below is valid for Vee = 3.00 Volts ±10%.
Improved speed and Noise Immunity will result if Vee is increased above 3.00 Volts to a maximum of 3.66 Volts at +125°C withmaximum Vee increasing linearly to 4.5 Volts at -55°C.
ELEMENTS
The 9908 Element (ADDER) performs MOD 2 Addition, the exclusive OR function, and control of 2 data streams (pins 1 and 5) bytying pins 2 and 3 together to control.
The 9909 Element (BUFFER) is a 2 input, high fan-out, invert.ing gate, with internal timing resistor.
The 9910 Element (DUAL GATE) is a dual, 2 input gate ..
The 9911 Element (GATE) is a 4 input gate with added inverter for the output to generate OR, NOR, AND, and NANO functions.
The 9912 Element (HALF-ADDER) is a two-level AND-OR gate with added output inverter.
The 9913 Element (TYPED FLIP-FLOP) is a gated D-Flip-Flop with asynchronous set and reset inputs suitable for shifting and counting.
The 9913 was previously known as an R, Register, or Full Shift Register Eelement.
The 9921 Element (EXPANDER) is a dual 2 input gate without node resistors, to be used when increased fan-in is required.
LOW POWER RTµL LOADING CHART valid for system operation .from -55°C to +125°C

7•
•
1~

l

.8

I

43

ly4
3

7

I

6

s

3

I

3

3

5

I

9908

2

4

I

5

.8

1

lg·764(symbols shown top view)

9909

9910

7
1~

.1

l·

·

2

.

3

·

6

.

'

5

3
4

.·

1.:~7
I

1

•

•

'

3

6

5

3
3

I

9911

9912

9913

•,Planar is a patented Fairchild process.

FAIRCHIL..CJ
313 FAIRCHILD DRIVE, MOUNTAIN VIEW. CALIFORNIA. (415) 962·5011, TWX: 910·379-6435

4-90

SEMICONDUCTORA DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATION

GENERAL RULESThe number of elements that may be driven by an output terminal may consist of any combination of elements whose summationof input loading does not exceed the output terminal driving capability.
Unused input pins should be tied to ground.
See expander element (9921) for paralleling.

FIG. 1

FIG. 2aFIG. 2b

TYPICAL POWER DISSIPATION VS. Vee

TYPICAL SIGNAL LEVEL VS. TEMPERATURE
V~c = 3.0V

TYPICAL SIGNAL LEVEL VS. TEMPERATURE
Vee= 4.0V
2.4

8.0

r/_j_

"'5.... 1,6 I-~

lL

...I

6.0

I

"'00
z

I!;
4.0

fl..
0:

~

FAN OUT= 1
2.0

t-~~F=>g"' 2.0>·-'""'~ 0.8
·in

2.0

4.0

6.0

8.0

-55

-25

Vee - VOLTS

0

25

0

50

TEMPERATURE - •e.

-r----- -- I\ --\-- rv~,~~.L --- --.-+- r---~[7 t-FAN OUT= 4

WORST· CASE MAX. LIMITS

...

1-6

0

·o

..
..

1\

TYPl~AL--'.j---

1-->
0.4 r-~

v

""'

:i:

~ 1.2

IT
J

4.

"'

:i:

t-!.!!

WORST CASE MAX. LIMITS

-55

-25

0

25

50

F.J_;E(&, = 1
75
100 125

TEMPERATURE - '.eFIG. 3

FIG. 4TYPICAL INPUT CHARACTERISTICS

TRANSFER CHARACTERISTICS
1.6
F.0. = 1

~

1.4
1.2

ll_7

;00
TEST POINT;!;

F.0.&.

"'0~ 1,0

'1j_

>
I

100 l---l---1--+~--J'.J.174--1--1--1--~

....

li
:I

0.8

~

~

])..

0.2

0.4

0.6

>o 0.6

0.4

V1N-VOLTS

0.2
0.8

l'

.aov,

1.0

1.2

1.4

1.6

0
25"C

'
' _ _ _ 12s•c
59

1------.=91~vo+,---- ~ssoc~----.~-v..._

Note: This curve will apply as Vee is increased from
3 V to 5 V with small decrease in 11N for same V 1N.

TYPICAL VoN VS. VeeIi-ss•c +2s c +22s c

I\

::>

25"C -55'C

lj_"C

_i_~

Vee= av\1~"::si :s

VoN ·.Your
ryTpor
0

0.2

0.4

0.6

0.8

1.0

VIN - VOLTS

V1N • VcE
TEST POINT1.2

1.4

1.6

Vee =3 V .890
Vcc=4V .940
Vcc=5V .990

0

0

.680
.710
.750

.530
.550
.575

FIG. 5 TEST CIRCUIT FOR NOISE THRESHOLD MEASUREMENTS

RESET

4

Yee

Yaor

3v
4V

1.8 v
2.0V

5v

2.4 v

6V

2.9V

CLOSE FOR
F.O.
3

=

Note that elements with specified
fan-out = 4 have good immunity
to worst case ground noise in a test
circuit when used in a fan•out - 5
configuration.

FIG. 6

FIG. 7

FIG. 8DC NOISE THRESHOLD VS. Yee

DC NOISE THRESHOLD VS. Yee

DC NOISE THRESHOLD VS. Yee
T = +125'e

~

----

........

--

300 t--+---t-_-____-±,,...-1~

I..........

9
~

~ 200

...!:!
...

VI

0
z 100

903 OF UNITS HAVE A
GREATER NOISE THRESHOLD
o._......_ _..__.__. . . . _ _._. . . . .___._---'

2.0

3.0

4.0

5.0

6.0

FIG. 9

FIG. 10TYPICAL PULSED NOISE THRESHOLD
VERSUS PULSE WIDTHrYPICAL PULSED NOISE THRESHOLD
VERSUS PULSE WIDTH

2.0l"'~ l.S
>
I

I

\

1.0

!

FAN OUT= 4

Vee = 3 . 0 _TA= 25'C

~

VI

~

...
.,...
:c

FANOUT-4

g,ANOUT•l-~ 1.01---+--+~~--+--t----i'~ -"',..J:~....

25 o.s 1--t--+--+--f"'l:i:ttt:!l!i!l~

~ 0.6

0
0

1.51---+--"'"--l~----+--t----i

I

~'1--

0:

,___,.__..,....,.._--i-Ytt = 3.0 to 6.0 V
TA = •55 to 125'C

~

~

90

~

Vee - VOLTS

Vee - VOLTS

Vee - VOLTS

z

10

20

30

40

50

60

PULSE WIDTH - ns

PULSE WIDTH - ns

4-92

FIG. 11 TEST CIRCUIT AND TABLE FOR TYPICAL tpd MEASUREMENTS

L

1

1

AVERAGE tpd = f ••• x TO

SCOPE

R

ELEMENTc

INPUT OUTPUTPIN NO. PIN NO.

~08 ADDER

00

3

7

9909 BUFFER

220!2

3

6

OTHER
INPUTSNOTEPINS 2 & 5
TO 1.8 V219910 DUAL GATE

00

1

7

2, 3, & 5
TOGND

9912 HALF ADDER

00

2

6

PIN 3 TO
1.8 v

2
2

TEST FOR 9909 ELEMENTS
1. All "A" switches left open in tpd test for 9909 element.
2. For curves shown, fan-out= 1 corresponds to switch "A" open; and for
fan-out= 4, switch "A" closed.

Connect pin 8 to Vee
Connect pin 4 to ground.
Connect all unused input pins to ground

AVERAGE PROPAGATION DELAY VERSUS CAPICITANCE
FIG. 12

FIG. 13

FIG. 14

70

60

~

~

50
I

u

u

~

w

"g
;;:

u

~

40

~

w

w

"
30

~

Vee = 3 v

Vee= 3V
FANOUT=4

FAN OUT = 1
20

20

10
10

20

30

40

50

0

60

10

LOAD CAPACITANCE - pf

20

30

90

60

80

50

70

50

10

60

0

10

-- --

~

~

40

w

~
;;:

30

60

30

10

20

30

40

LOAD CAPACITANCE - pf

50

60

50

60

FIG. 17,............
'

80
~
u

~

w

::;"'
;;:

70

<(

50
---·Vee= 3V- V e e =4V
OUTPUT LOAD = 220!.l

60
Vee = 3V
FAN OUT = 1 THRU 4RESISTOR TO GND
10
0

40

90

..............

40

FAN OUT= 4

20

LOAD CAPACITANCE - pf

,
,,

u

u

20

40

FIG. 1670-~~:,c,~

Vee = 4V
FANOUT=4

LOAD CAPACITANCE - pf

FIG. 15

>
<(

30

20

10
0

w

~

30

40

30

50
0

100

200

300

400

LOAD CAPACITANCE - pf

4-93

500

600

0

10

20

30

40

LOAD CAPACITANCE - pf

50

60

9908 LOW POWER
RT1>L ADDER
THE LOW POWER RTµL
ADDER PERFORMS THE
MOD 2 ADDITION OR EXCLUSIVE OR FUNCTION;
IT ALSO IS USED TO SELECT ONE OF TWO DATASTREAMS UNDER CONTROL OF A SINGLE GATESIGNAL.

AVERAGE POWER

CIRCUIT DIAGRAMLOGIC SYMBOL AND FUNCTIONS
8POSITIVE LOGIC=(3+5) =3·5
7 =(1+2) (3+5)

2

6

7

6

6
4

8

NEGATIVE LOGICDISSIPATION (25°C)
Typical Resistors

10 mW
6
7

=(3·5) =3+5
=1•2+3·5

2

R, = L5kn
R, = 3.6kU

64

SWITCHING TIME TEST CIRCUIT

l.SV

T.P.

3.6 k

750 Q
FO 600_n__J500 ~ -=-

7

ns

Test
No.
1
2
3
4
5
6

7
8

9
10

11
12
13
14
15

GROUND
UNUSED
INPUT PIN

T EST
Test
I,

Is

1,
1,
1.
I,

1,

v.
v.
v,
v,
v,
1,
t3-7+
t3+7-

Note

c 0 N D IT I 0 NS

Pin 1

Pin 2

Pin 3

Pin 4

Pin 5

GND
GND
V1N
Veor
GND
VoN
GND
GND
GND
VoH
Veor
Veor
GND
GND
GND

GND
GND
Veor
V1N
GND
GND
VoN
GND
GND
VoFF
Veor
Veor
GND
Veor
Veor

V1N
GND
GND
GND
VoN
VOFF
VoH
Vaor
VoFF
GND
Veor
Veor
GND
Pulse inPulse in

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
V1N
GND
GND
VoN
VoH
VoFF
VoFF
Veor
GND
Veor
Vaor
GND
Veor
Veor

~NP

GND

4-94

Pin 6

TEST LIMITS
Pin 7

Pin 8

V1N
V1N

Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee

V1N

V1N
VoN

v,,

Pulse out
Pulse out

Vee
Vee

MIN.

MAX.
.8l1N
.8l1N
l1N
l1N

IA,
IA4
IA4
Ve,
Ve,
Ve,
Ve,
Vour

1,
80 ns
100 ns9909 LOW POWER
RTvL BUFFER
THE LOW POWER RTµL
BUFFER IS A LOW IMPEDANCE INVERTING DRIVER
CIRCUIT. THE ELEMENTCAN SUPPLY SUSSTANTIALLY MORE OUTPUTCURRENT THAN THE BASIC
RTL CIRCUIT. A RESISTORIS INTERNALLY CONNECTED TO THE BUFFER EL&
MENT INPUT' WHICH MAY
BE RETURNED TO THE
SUPPLY VOLTA~E IF CAPACITIVE COUPLING IS DESIRED. TYPICAL APPLICATIONS OF THIS TYPE CONNECTION ARE ASTABLE
AND MONOSTABLE MULTIVIBRATORS, AND FOR THE
DIFFERENTIATION OF
PULSES.

LOGIC SYMBOL AND FUNCTIONSCIRCUIT DIAGRAMPOSITIVE LOGIC

6=2+3

NEGATIVE LOGICAVERAGE POWERDISSIPATION (25°C)
10 mW at 50% Duty Cycle

SWITCHING TIME TEST CIRCUIT

Vee
T.P.

-nt f:sJ_t-,V

3.6 k

r··

___n_

~500 ~ -=-

-=-

ns

Test
No.

1

1,
I,

v,
v,
v,
v,
v,
1,
tl+6t1~6+

Note

Pin 1

3+6-

GROUND
UNUSED-=- INPUT PIN
T EST

Test

2

3
4
5
6
7
8
9
10

-=-

t

2200

240 pF

c 0 N D IT I 0 N S

Pin 2

Pin 3

Pin 4

V1N
Vaor
VoFF
VoN
GND
VIN
GND
GND
GND
GND

Voor
V1N
VoFF
GND
VoN
GND
V1N
GND
Pulse inPulse in

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

4-95

Pin 5

Pin 6

V1N
VoH
VoH
VoH
VoH
Pulse out
Pulse out

TEST LIMITS

Pin 7

Pin 8
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee

MIN.

MAX.
211N
21,N

IAa
Vour
Vour
Vee
Vee

1,
90 ns
70 ns

9910 LOW POWER· . LOGIC SYMBOL AND FUNCTIONSRTJ>L DUAL GATE
THE LOW POWER RTµL
DUAL GATE. MAY BE USEDAS A PAIR OF NOR GATES,AS AN R-S FLIP-FLOP, AS A
PAIR OF·INYERTERS, OR AS
A DOUBLE INVERTER. IT
MAY ALSO BE USED WITH
THE LOW POWER RTµL
GATE EXPANDER TO INCREASE ITS FAN-IN CAPACITY.

CIRCUIT. DIAGRAM

8POSITIVE LOGIC

8

2

6
6

7

7=1+2

5

6=3+5

4
3

2

AVERAGE POWERDISSIPATION (25°C)
4mW
8

NEGATIVE LOGIC

Typical Resistors
R,
2

R2

6

= 1.5 k= 3.6k1= 1•2
6=3·5
4SWITCHING TIME TEST CIRCUIT
Vee
T.P.

T.P.

3.6 k

FD600

*~

GROUND~UNUSEDINPUT PINS

500 "'.i /':

;.!.

T EST

Test
No.

Test

1

1,

2

I,
I,
Is
I,

3
4
5
6'
7
8

9
10

.u

12
13
14
15
16
17

1.

v,
v,
v.
v.
v.
v.
v,
v,
la
ti-7+
t1+1-

Note

CONDIT I 0 NS

Pin 1

Pin 2

Pin 3

Pin 4

Pin 5

V1N
Vaor
GND
GND
Vo••
GND
VoN
GND
GND
GND
GND
GND
V1N
GND
GND
Pulse inPulse in

VaoT
V1N
GND
GND
Vo••
Vaor
GND
VoN
GND
GND
GND
GND
GND
V1N
GND
GND
GND

GND
GND
V1N
Vaor
Vaor
Vo••
GND
GND
YoN
GND
V1N
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
Vaor
. V1N
GND
Vo••
GND
GND
GND
VON
GND
V1N
GND
GND
GND
GND
GND

4-96

Pin 6

TEST LIMITS
Pin 7

V1N
V1N

Pulse out
Pulse out

Pin 8
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee

MIN.

IM
IM

MAX.
l1N
l1N
l1N
l1N
IAM
IAM
Vour.
Vour
Vour
Vour
VeE
VeE
VeE
VcE
It
40 nsec
50 nsec

9911 LOW POWER
RTµ.L GATELOGIC SYMBOL AND FUNCTIONS

THE LOW POWER RTµL
GATE MAY BE USED AS AN
OR GATE BY APPLYING
TRUE INPUTS; THE PIN 7OUTPUT IS THEN THE
TRUE OR FUNCTION OF
THE INPUTS, AND THE PIN
6 OUTPUT IS THE INVERSE,OR NOR.

POSITIVE LOGICAVERAGE POWERDISSIPATION (25°C)

CIRCUIT DIAGRAM
8

8

2

6

7

6

7::: 1+2+3+5
2

6= 1+2+3+5

R1

4

3

R1
5

8

NEGATIVE LOGIC

44mW

Typical Resistors
2=R,
l.5krlRt= 3.6kn

67 = 1•2•3•5
6 = f.2-'3:5

4

SWITCHING TIME TEST CIRCUIT

Vee
T.P.

T.P.

3.6 k

7500
FD600

JL

~500 k- -: -

-::-

ns

T EST

Test
No.

Test

1
2
3
4
5

1,
J,
I,

6

1,
1.

18

I,
v.
v.
v.
v.
v.
v.
v.
v.
v,
v,
1,
t,_,_

19

t1+7+

7

8
9
10
11

12
13
14
15
16

p

GROUND
UNUSED
INPUT PINS

Note

c 0 N DI T I 0 N S

Pin 1

Pin 2

Pin 3

Pin 4

Pin 5

V1N
Vaor
Vaor
Vaor
VoH
GND
VoN
GND
GND
GND
V1·N
GND
GND
GNO
GND
GND
GND
Pulse inPulse in

Vaor
V1N
Vaor
Vaor
VoFF
GND
GND
VoN
GND
GNO
GNO
v,«
GND
GND
GND
GND
GND
GNO
GND

Vaor
Vaor
V1N
Vaor
VoFF
GND
GNO
GND
VON
GNO
GND
GNO
v,«
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GNO
GND
GNO
GND
GND
GNO
GNO
GND
GND
GNO
GND
GNO
GNO

Vaor
VaoT
Vaor
V1N
Vo,,
GND
GNO
GNO
GNO
VoN
GND
GNO
GND
V1N
GNO
GND
GNO
GND
GND

4-97

Pin 6

v,«
VoFF

TEST LIMITS
Pin 7

V1N

VoN
V1N
Pulse out
Pulse out

Pin 8
Vee
Vee
Vee
Vee
Vee
Vee
Vet
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
v,.
Vee
Vee

MIN.

MAX.
11«
l1N
Ii«
iiN

'"'
IA•

IAM
Vour
Vour
Vour
Vour
Vee
Ve•
Ve•
Ve•
Vour
Ve•

1.
70 ns
90 ns

9912 LOW POWER
RTµ.L HALF ADDER. CIRCUIT DIAGRAMLOGIC SYMBOL AND FUNCTIONS

88POSITIVE LOGIC

THE.LOW POWER RTµL
HALF-ADDER IS A MULTIPURPOSE COMBINATION
OF THREE BASIC RTL CIRCUITS. THE CONFIGURATION IS WELL SUITED AS ACOMPLETE HALF-ADDER,
AN EXCLUSIVE OR GATE,OR ANY OTHER SIMILAR
LOGIC CONSTRUCTION.

R2
2·

7

6

7 = (1+2) (3+5)
6

6=1·2+3·5

4
2
4
3

5

8

NEGATIVE LOGIC

R1

AVERAGE POWERDISSIPATION (25°C)

Typical Resistors

8mW

2

6

Ro= l.5k!1
R, = 3.6k!1

7 = 1•2+3•5
6 = ci+2> ci+5>

4

SWITCHING TIME TEST CIRCUIT

T.P.

T.P.
3.6 k

it

FD600

FD600

GROUND

500 ns

T EST

Test
No.

Test

1
2
3
4

lo
I,
I,

5

I,
I,

6
7
8

1,

1.

11

v.
v.
v,
v,

12
13
14

la
To+•To-•+910"=- ~:p~Si~INS

Notes

CONDITIONS

Pin 1

Pin 2

Pin 3

Pin 4

Pin 5

VoN
Veor
GND
GND
VoN
GND
GND
Veor
Veor
Vo,,
Veor
GND
Pulse inPulse in

Veor
VoN
GND
GND
GND
VoN
GND
Veor
Veor
VoFF
Veor
GND
GND
GND

GND
GND
VoN
Veor
VON
GND
GND
Veor
Veor
Veor
VoFF
GND
GND
GND

GND
GND
'GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
Veor
VoN
GND

4-98.

Pin 6

Pin 7

VoN
VoN

vo;.

GND
Veor
Veor
Veor
VoFF
GND
Veor
Veor

TEST LIMITS

VoN
VoN
VoN

Pulse out
Pulse out

Pin 8
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
VLL
Vee
Vee

Min.

MAX.
liN
liN
loN
loN

IA!
IA1
IA4
Vour
Vee
Vei
Vee
IL
100 ns80 ns

9913 LOW POWER
RTµL TYPEDFLIP-FLOP
THE LOW POWER RTµL
TYPE D FLIP-FLOP IS ACOMPLETE, GENERAL PURPOSE STORAGE EL.EMENT.
THE STATE OF INPUT 2 IS
STORED WHEN INPUT 1
CHANGES FROM HIGH TO
LOW. A SUBSEQUENTCHANGE OF INPUT 2 WHILE
INPUT 1 IS LOW HAS NO
EFFECT. THE 9913 FLIPFLOP HAS APPLICATION IN
SHIFT REGISTERS, COUNT:ERS, AND CONTROL CIR·
CUITRY.

LOGIC SYMBOL AND FUNCTIONS ----

8

2

6

DIRECT INPUTS'''GATED INPUT'''

3

7

L

L NC NCl•I

t=n t=n+l
2
6
5

L

H

L

H

H

H

L

H

L

H

L

L

L

H

H

H

L

L

6

5

4

1. Pin 1 must be high
2. NC= no change·
3. Pins 3 and 7 must be low

CIRCUIT DIAGRAM.,..

AVERAGE POWERDISSIPATION (25°C)

.,
••

••

••

12mW

Typical Resistors

Test
No.
1
2
3
4
5
6
7
8
9
10

11

T EST
Test

Note·

v.

v.
v.
v.
v,
v.

v.
v.
1,
1,
1,
1.

12
13
14
15
16
17
18
19
20
21

t,_._

22

ti-•+

23

... t.~.~.

24. t1-s+25

t2+1-.

I,

1.
I,
I,

h

v,
v.
1,

1
1
1
1
1
1
1

R, = 1.5kn R. =Ison
R, = 3.6kn Rs= 480n

CONDITIONS

Pin 2

Pin 3

Pin 4

GND
VtoT
GND
Vsor
GND
VtoT
GND
VtoT
GND
VtoT
. V.or
GND
GND
VtoT
GND
Vsor
GND
V1N
V1N
VtoT
VaoT
V&N
Vot1
GND
GND
VoFF
Vot1
VoFF
VoFF
V1N
VoFF
Vaor
GND
VoFF
VoFF
VoN
VoFF
VoFF
GND
GND
Pulse
Tie to
In
Pin 5
Pulse
Tie toIn
Pin 5
Tie toPulse,· 11'.1
Pin 5
Puise ·•TietoIn
Pin 5: ,:·.: Pulse t· Pulse 2
In
In
Pulse 1 Pulse 2
. In
· In
•· Pulse i' 'Pulse 2
In.
In
Pulse 1 Pulse 2
In
In

VoN
Vaor
GND
GND
V1N
Vaor
GND
GND
GND
GND
VoFF
Vaor
VoFF
VaoT
GND
V1N
GND
GND
Vaor
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

GND

GND

GND

GND

GND

GND

GND

Pin 1

Pin 5

Pin 6

Vot1
VoN

V1N
V1N

V1N
V1N
V1N
V1N

Pulse
Out
Pulse
Out
Pulse
Out
Pulse
Out

Pulse
Out
·. t:~;~.
26
GND
GND
Pulse
"
Out
27
't2-1~.
GND
GND
Pulse
Out
28
GND
Pulse
GND
t1-2+
Out
Note 1: Voltage applied to Pin 1 changes from Vu to specified value prior to making measurements.

4-99 .

TE.ST LIMITS
MIN.

MAX.

Pin 7

Pin 8

Vaor
Vot1
GND
GND
Vaor
V1N
GND
GND
GND
GND
Vaor
VoFF
VaoT
VoFF
GND
GND·
V1N
Vaor
GND
GND
GND

Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee

v••

1.

Vee

80 ns

GND

Vee

120 ns

GND

Vee

80 ns

GND

Vee

120 ns

GND

Vee

60 ns

GND

Vee

30 ns

GND

Vee

60 ns

GND

Vee

30 ns

Vour
Vour
Vour
Vour
Vee
Vee
Ve&
Vee
1.8 l1N
1.8 l1N
IA,

1...
IA,
IAJ
l1N
l1N
l1N
Vee
Vee

CIRCUIT FOR MEASURING T,_,., T,_,_, T,_,., T,_,_

PROPAGATION DELAY

Vee

T.P.

3.6k

T.P.

51 ll

L...r

_J k500 ns

"";;"

r·

FD600

T.P.

-

-=

GROUND
UNUSED
INPUT PINSCIRCUIT FOR MEASURING MINIMUM INPUT PULSE WIDTH

L_£-~~~~~_.__1 _1-li_:~sv
PIN&

T.P.

T.P.

MINIMUM PULSE WIDTH

51 0

I
-::-

20pF

3.6k

510

20pF

VARIABLE DELAY BETWEEN PULSE 1 AND PULSE 2

CONNECTED AS BINARY COUNTERTYPICAL OPERATING CLOCK PULSEFREQUENCY VERSUS Vee

Vee

I

T.P.

~

8.0

~ 6.0

.."

~

4.0

""g
" 2.0
0

0

1.0

2.0

3.0

4.0

5.0

Vee - VOLTS

OUTPUT PIN 6

,;

:;:;
....._>CP INPUT PIN 1"'

JOO n~/div.

6.09921 LOW POWER
RTr>L GATEEXPANDER

CIRCUIT DIAGRAM

7

THE LOW POWER RTµL
GATE EXPANDER IS A DOUBLE GATE WITHOUT THE
NODE RESISTORS. ITS OUTPUT TERMINALS MAY BE
CONNECTED IN PARALLEL
TO THOSE OF A DUAL GATE
OR A GATE TO INCREASETHE FAN-IN CAPABILITY OF
THE CIRCUITS.
WHEN A DUAL GATE OR A
GATE IS USED WITH THE
EXPANDER, THE FOLLOWING RULES APPLY.

6

Typical ResistorR,
2 0--"VV'lr------= l.5k!J~----'VVY--<>3

4

DIAGRAM FOR USE OF GATE EXPANDER

1) Pin 8 of the Expander must be connected
to Vee2) The input load factor of the expanded
gate is 1.33
3) The output drive
factor of the expanded
gate is decreased by.5 load for every node
added.

•cc
3.0

.:
~
==B

1.33

1.33
1.33

1.33
1.33

------------------

~
~

•cc

...

1.33
1.33

AVERAGE POWERDISSIPATION (25°C)

1.33

•cc
1.33

No Power Flowing

1.33
1.33
1.33

Example of loading rules and logic symbols

T.E ST

Test
No.

Test

7

8
9
10

11
12
13
14
15

I,
I,

1,
V1
V1

v.
v.
.W
;~;
. 'Y(
y,,
11,:
V1

.,

·,

h

1•.
.1 •. ·1,.

...
·'

C 0 ND .1 T. I 0 NS

Pin 2

Pin 3

Pin 4

Pin 5

V1N
Vaor
V10T
V1N
GND
GND
GND
GND
GND
VoN
GND
VoN
GND
GND
GND
GND
GND. .GND
GND
GND
GND
V1N
.·GND
V1N
VoFF
Vo••
GN.D
GND
~·
GND
GND

GND
GND
V1N
Vaor
GND
GND
VoN
GND
V1N
GND
GND
GND
GND
Vo••
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
Vaor
V1N
GND
GND
GND
VON
GND
V1N
GND
GND
GND
VoFF
GND

Pin 1

11

1
2
3
4
5

6

Notes

.·~·

4-101

Pin 6

TEST LIMITS
Pin 7

Pin 8

VoH
VoH

Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee

VoH
VoH
Vol
VRL
VRL
VRL
VRL
VRL
VRL
VRL
V1N
V1N
Vee

Vee

MIN.

MAX.
l,N
l1N
l1N
l1N
Vour
Vour
Vour
Vour
Vee
Vee
Vee
Vee
lcex
leEx
IL

SPECIAL CIRCUITS COMING SOON
Type

Function

Type

FunctionInterface Circuits
9626
9627
9826
9827

Dual CCSL Telephone Line Driver
Dual Telephone to CCSL Line Receiver
Dual CTL Telephone Line Driver
Dual CTL Telephone Line Receiver

9852
9853
9854
9855
9856

RRTTL
9702
9704
9705
9708
9711
9774
9709

Quad 2-lnput NANO Gate
Dual 4-1 nput NAN D Gate
Dual, Dual 2-lnput AOI
Quad 2-lnput AOI
Flip-Flop- Single D
Flip-Flop- Dual D
BufferDual 2-lnput NOR Gate
2-2-3 Input AND Gate
Dual 4-lnput AND Gat!I
Single 8-lnput, 2-0utput AND Gate
Dual 2-lnput AND Buffer Gate
3-1-3 Input AND Gate
Quad Single Input AND Gate
Dual 2-lnput AND Gate with 2 Wide,
2-lnput AND-OR Gate
Dual 2 Wide, 2-lnput AND-OR Gate
As 9866 w/o 2K Load and Pulldown·Resistors
J-K, D Flip-Flop

RRDTL
9732
9744
9745
9748
9762

Active Pullup Buffer
Uncommitted Output Buffer
R-S Flip-Flop (6K Pullup)
R-S Flip-Flop (2K Pullup)
Triple 3-lnput Gate

986~

9865

CTµL II
9806
9816
9842

986~

9871
9812

9828
:'
CTµL II Line Interface Circuits
9819/20 ·lOOn Line Receivers
9821
1000 Line Driver
9826
EIA Telephone Line Driver
9~~7
EIA Telephone Line Receivercrµi.. rins1
9822
9824
9834
9838
9881

Hex Restorer AND Gate
Hex Inverter NOR Gate
Quad 2-lnput AND Gate

Dual Full Adder/Subtractor
Four-Bit Comparator
Quad Latch
One-of-Eight Decoder
Eight-Input Multiplexer

INTERFACE CIRCUITS
9626 - DUAL CCSL TELEPHONE LINE DRIVER
GENERAL
The 9626 is a dual device designed to translate incoming CCSL
levels onto either military (MIL-STD 188B) or commercial (RS-232B)
equipment. The outputs are single-ended, incorporate short circuit
protection, and will have the same output impedance in either thehigh or low output state. Inputs are CCSL compatible. Rise andfall times are symmetrical and can be controlled by use of an
external feedback capacitor connected between dV/dt and output
pins. Power dissipation is constant for both frequency and rise andfall time control variations. The product will be released in the 16
pin ceramic dual in-line package.

9627 - l)UAL TELEPHONE TO CC$L L!NE RECEIVER
GENERAL
The '9527 is a dual device to receive either military (MIL-STD 188B) ·or cbmmercial (RS-232B) line signals and translate them to CCSL
output levels.
.
The input features a differential 'amplifier with hysteresis in orderto improve noise immunity and allow single-ended transmission reception. Outputs are CCSL compatible. Provision has been made to
independently strobe each receiver and also to control receiverresponse time by use of an external capacitor tied to ground. The
product is planned for release· in the 16 pin ceramic dual in-line
package.

TARGET SPECIFICATIONS
Supply voltages

TARGET SPECIFICATIONS
Supply voltages
V1N Hysteresis

Your
VIN

IR
IF
Rour
lse
Power dissipation
Propagation delay

Yee= 12V ±10%, VEE= -12V ±10%
V0 H = 6V, VOL= -6V
VIL= lV, VIH = 2V
2µA at V1N = 4V
50µA typical (0.5mA maximum) at V1n = OV
25 ohms typical
80mA nominal (lOOmA maximum)
160mW/gate
lOOns typical (200ns maximum)

Vee= 12V ±10%, VEE= -12V ±10%
EIA 6 ±JV (EIA Pin to VEE)MIL-STD 1.0 ± 0.5V (EIA Pin OPEN)
EIA 3K to 7K (R 1N to GND)
MIL-STD> 6K (10.7K nominal with R1N OPEN)

Common Mode
Noise Rejection
Your
Power Dissipation
Propagation Delay

LOGIC DIAGRAM AND PIN ASSIGNMENTS± 25V (referenced to ground)
V0 L < 0.4Vat IOL = 5mA
V0 H 2.4V at IOL = -0.5mA
160mW/receiver
80ns typical (200ns maximum)>

LOGIC DIAGRAM AND PIN ASSIGNMENTS~--+-oIn A (14) 0--1--.rr--'.........
In A (13) D--+-<ll
In A (1) U--+---t(4) Response
Control A

RlnA (6)-- In A (5) n------~(3) Strobe A+ In B (10) n--1----~(14) Strobe B

In B (11) n--1--.rr--'.._In B (10) O--+-<ll

R1n B (11)(15) Out B

In B (9) 0--f---L_.....J(13) Response
Control B

(5)

Gnd

(12)
Vee

(6)

VEE

Supplies
Vee= 12V ± 10%
VEE= 12V ± 10%

4-102

SPECIAL CIRCUITS COMING SOONen 9826 - TELEPHONE LINE DRIVER
The 9826 is a dual device designed to interface CTL levels at the
input with equipment meeting military (MIL-STD-188B), or commercial - EIA (RS-232B) telephone line specifications.
Both inverting, and noninverting CTL compatible inputs are provided.
Power dissipation remains constant at typically 160mW, for all
frequency and rise and full time variations.
Outputs are single ended, have the same impedance in either highor low output state and incorporate short circuit protection. Rise andfall times are symmetrical and can be controlled by connecting an
external feedback capacitor between dV /dt and the output pins.
The 9826 will be available in the 14 pin ceramic Dual In-line Package.
SPECIFICATIONS=VIL = 0.8V, VIH
1.25V
V0 H = 6V, VOL= -6V
2mA at V1N 2 volts
25 oh ms (typica I)
100 ns (typ) 200 ns (max)
80mA (typ) lOOmA (max)

VIN

Your

en 9827 - TELEPHONE LINE RECEIVER
The 9827 is a dual device designed to interface incoming signals
meeting military (MIL-STD-188B) and commercial - EIA (RS-232B)
telephone line specifications, with standard CTL logic levels.
The input features a differential amplifier with hysteresis, to improvenoise immunity and allow single ended transmission reception. A
tapped resistive network is employed to adapt the input to either
EIA or MIL requirements.
The outputs are CTL compatible. Receiver response time is adjusted
by choice of external capacitor.
The 9827 is supplied in the 14 pin ceramic Dual In-line Package.
SPECIFICATIONS
V1N Hysteresis

EIA: 6V (± 3V) (Pin 13 to VEE)MIL-STD: 1.0V (± 0.5V)
EIA: 3K to 7K (R 1N to GND)
MIL-STD: >GK (10.7K t;tp)
VOL= 0.7Vto -0.3V
VoH > 2.0V at 20 mA

=

IF
Rour
Propagation Delay
Ice

LOGIC DIAGRAM

Common Mode
Noise Rejection
Power Dissipation
Propagation Delay± 25V (referred to ground)
160mW /receiver
120ns typ (200ns max)

LOGIC DIAGRAM(4) dv/dt A~------+--<l

In (I)In (2)(1) Response
Control A

R1N A (3)(6) Out A

In (3)(5) Output Amp Control- In A (2) o---+------'(11) Output Amp Control+ In B (7) C>----+-----~(7) Out B

R1N B (8)In (12)
In (13)
In (14)
In (15)' - - - - - - - - + - - n (10) Response(10) dv/dt B

Control B
Supplies
(8)
Gnd

(16)
Vee

Gnd
(5)

(9)
VEE

RRTTL
Fairchild is developing a Radiation Resistant T'L family which will
be manufactured using production proven dielectric isolation andthin film resistor technologies. The family has been specificallydesigned for low propagation delay times and has been designed for
operation and survivability in high radiation environments. Performance to particular categories is available from the factory ona need to know basis. The product line will be available in our
14 lead 1,4" x 1;4'' CERPAK.

Vee
(12)

VEE
(6)

EIA
(13)

Vee= +12V ± 10%

VEE= -12V ± 10%

CERPAK DIMENSIONS

14

~
.260

.240

R'T'L DESIGN OBJECTIVESSingle power supply: 5.0 volts ± 10%
Temperature range: 0°C to 125°C
Guaranteed fanout of 10 TTL loads over full temperature and supply
voltage range
Guaranteed minimum of 0.4 volts noise immunity over temperature.
Typical high level noise immunity of 1.3 volts and low level noise
immunity of 0.8 volts
Typical power dissipation of 22mW per gate at 50% duty cycle
Typical propagation delays of 6ns for 50pf load

.050

T

r--

FAMILY ELEMENTS
9702
Quad 2-input NAND Gate
9704
Dual 4-input NAND Gate
9705
Dual, Dual 2-input AND/OR Invert
9708
Single, Quad 2-input AND/OR Invert
9711
Flip-Flop- Single D
9774
Flip-Flop - Dual Dr-----l :~;~--1 :~;~_J_T ·~~c=~~~·~·d::!
____J
f t
I
- ~I
.0060
.0035

4-103

L_.250
240

.065
.050

.025

Typ.

SPECIAL CIRCUITS COMING SOONRRDTLCERPAK DIMENSIONS

GENERAL DESCRIPTION
The Fairchild Radiation Resistant series of Diode Transistor Micrologic is a member of the Compatible Current Sinking Logic (CCSL)
family designed for use in system where good noise immunity,
medium speed, medium power, and good fanout are required. R'DTµL
is available in CERPAK package over o•c to 125°C temperature range.
Noise immunity is typically 1 volt. Worst case noise immunity overthe military temperature range is 400mV. Power dissipation istypically 8.5mW per gate function at a 50% duty cycle. The average
propagation delay is 30ns per gate function. A single 5 volt ± 10%
supply can be used. The announced functions are identical in bothpinouts and logic to their existing function isolated counterparts.
Fairchild R'DTL devices incorporate dielectric isolation and thin film
resistor manufacturing technologies. All family elements have been
designed for operation and survivability in high radiation environments. Performance to particular categories is available from thefactory on a need to know basis.

.260
.240

_L
_l_

.050

T

T

.020
.015

--j :~~~.

FAMILY ELEMENTS
9732
Active Pull-up Buffer
9744
Uncommitted Output Bulfer
9745
R-S Flip Flop (GK pull-up)
9748
R-S Flip Flop (2K pull-up)
9762
Triple Three Input Gate

~

14

r-

--1 :~~~ 1-_J_c::::•~~=::5~~·~l4!
T
L__.250~
f f
.0060
.0035

1-

·240 -------i.065 .025.050 Typ.

CTµL II
CTµL II is a new high speed version of the CTµL 9952 series circuits.
The first elements to be announced will be pin-for-pin replacements
for the existing family. The gates will offer tpd 3 nsec (max) andthe buffer and inverter 8 nsec (max). Complete circuit listing is:
GATES, INVERTERS, AND BUFFERS (RESTORERS)
16
15

14Ycc
13Vcc
12

Gnd5

God

GND5

Ii
ID

9806

9816

9853

• 9854Hex Restorer AND Gate

Hex Inverter NOR Gate

2-2-3 Input AND Gate

Dual 4-lnput AND Gate

"

"

"

"'

13

13

13

'"

u ·~

UV~

12Vcc

U Ye

11VE£

God

''°'

9842
Quad 2-lnput AND Gate

ID

9852
Dual 2-lnput NOR Gate

4-104

GNDS

ID

uv..

....

ID

9855

9856

Single 8-lnput, 2-0utput AND Gate

Dual 2-lnput AND Buffer Gate

SPECIAL CIRCUITS COMING SOON

...

3.

....

'"

v,,

....

,,,

"''

9865

9864

9819

Quad Single Input AND Gate

3.1,3 Input AND Gate

....

v,,

9820

llRDS

9821

9866 / 9872

98il

9866: Dual 2·1nput AND Gatewith 2 Wide, 2-lnput AND-OR Gate
9872: As 9866 w/o.2K Load and
Pulldown Resistors

Dual 2 Wide, 2-lnput AND-OR Gate

9828-J.K, D FLIP-FLOP

CTµL·MSIThe 9828 is a dual J.K or D type flip.flop designed for high speed
storage, counting and parallel. or serial loading shift register
applications.
A high input on the Parallel Enable P.E. terminal permits D type
operation and a low input enables the J-K. The device is triggeredon the clock falling edge and has a common clock line. Toggle frequency will be in excess of 45 MHz.

CTµL-MSI elements offer the same advantages as the standard
CCSL·MSI functions building blocks at a two to three times speed
improvement. All devices have fully restored input and output levels
and are clamped to reduce high frequency ringing problems. The
elements will be available in the hermetic, 16 lead Dual-In-linePackage.

9822 - DUAL FULL ADDER/SUBTRACTOR

D

D

PEU----.
Q

Q

K

K

0

K

The 9822 is dual element which adds two numbers A and B andcarry in C, if the enable function D is low. The sum S is produced,
along with Carry Generate Cq and Carry Propagate Cp in 1 nsec.
These permit the device to be used in very high speed carry lookahead configurations. If D is high the device acts as a subtr<1ctor.
This element is intended for adding or subtracting binary or BCD
numbers in series or parallel, parity checking, decoding and cycle
encoding applications.

0A

CTµL II LINE INTERFACE CIRCUITS

B

C;

F/A·S

9819/20 - 1000 LINE RECEIVERS
The 9819 and 9820 are dual elements designed for interfacing
1000 transmission lines, used for peripheral equipment interconnections, with CTµL systems.
The 9819 offers a differential input; 9820 is a two input single
ended receiver. Both devices have direct and inverted outputs. An
active low level output enable facility permits up to eight drivers
and receivers to be connected to a common buss line.

9821-1000 LINE DRIVER
The 9821 is a dual 1000 line driver designed for use with the 9819
and 20 line receivers. This element accepts single ended CTµL
levels, and provides complimentary outputs.
DRIVER/RECEIVER FEATURES
Driver/Receiver pair delay-12 nsec
Min line noise immunity ± 0.4 volts
14 lead ceramic DIP

4-105

D

A

B

F/A·S

C;

SPECIAL CIRCUITS COMING SOON
9838 ..._ ONE OF EIGHT DECODER
The 9838 is a multi.function decoder designed to convert three
digital inputs to one of eight mutually exclusive digital outputs.
A gated enable control permits use of the 9838 in many demulti·. plexing, memory and control decoding applications. The selected
output is enabled by a high on E, and low on E.

9824 - FOUR BIT COMPARATOR
The 9~24 is a high speed four bit comparafor •for data processing
and instrumentation applications. The element compares tWo four
bit parallel words and provides a high output at the appropriate
termin_al A < B, A B and A > B in 25 nsec.
Extension to larger word sizes is achieved with the A < B and
A > B inputs. A > B IN to A > B OUT is provided in 12 nsec,

=

Ao

A1

A2

A3

A>B

Aj

A2

A=B

A1

Ao

Bi
Bo

81

82

83

A<B

Outputs

049881- EIGHT INPUT MULTIPLEXERThe 9881 is an eight input digital multiplexer designed for gating
information . from several sources onto a single buss. Extension of
the multiplexing ·capability and numerous other logic functions areprovided by the enable terminal E.
Delay of 15 nsec is obtained from presentation of binary address
to At,, A,, and A, to information available at the output. Device
through delay is 10 nsec.

9834 - QUAD lATCH
The 9834 is a gated latch circuit for 4 bit parallel data storage.
Two write lines w, and W2 provide clock input and clock enablefacilities, common read line R presents the fully restored outputs
to Q, through Q•. Write time is 12 nsec, read time 8 nsec.
Synchronous mode controls A and B, common to all four latches
determine set, clear, or data transfer function.

E 0
A

01

02

03

04

4
Inputs

So

R

S1
B
Q1

Q2

Q3

S2

Q4

4-106

06

Output

6

·7

-==

HybridIntegrated
Circuits

HYBRID CIRCUITS NUMERICAL INDEX
Type

Page No.

Type

Page No.

Type

Page No.

5-1
5-5
5-9
5-13
5-17
5-21
5-25
5-27

SH3000SH3001SH3002SH3005
SH3200SH3201
SH3741

5-29
5-31
5-33
5-35
5-39
5-41
5-43

SH6400SH6401SH6402SH6500SH6501SH6502SH8080

5-45
5-45
5-45
5-49
5-49
5-49
5-54

SH2001SH2002SH2002-P
SH2100SH2101
SH2200SH2204SH2205HYBRID CROSS REFERENCE
Function

DevicePackage

Lamp & Relay Driver

SH2001SH2002SH2002-P
SH2100SH2101
SH2200SH3000SH3001SH3002SH3005

T0-100, FP
T0-100, FP
Plastic DIP
T0-99, FP
T0-99
Plastic DIP, T0-100, FP
T0-100T0-100T0-100T0-99, FP

SH2205

Ceramic DIPHigh Impedance Amplifier
Analog Switch
High ImpedanceDifferential Comparator
Quad Full Adder

Function

5-i

DevicePackage

Parity Generator

SH2204FP

Voltage Regulator

SH3200SH3201

T0-99
T0-99

Quad Core Drivers

SH6400SH6401SH6402SH6500SH6501.
SH6502

FP, Ceramic DIP, Plastic DIP
FP, Ceramic DIP, Plastic DIP
FP, Ceramic DIP, Plastic DIP
FP, Ceramic DIP, Plastic DIP
FP, Ceramic DIP, Plastic DIP
FP, Ceramic DIP, Plastic DIP

4 Bit Arithmetic Unit

SH8080FP

Dual Operational AmplifierSH3741

Plastic DIP, Ceramic DIP

SH2001
HIGH-VOLTAGE, HIGH-CURRENT DRIVER
FAIRCHILD HYBRID CIRCUITSPHYSICAL DIMENSIONSTO-JOO(JO pin package)• INPUTS CCSL COMPATIBLE• USE FOR CORE, CABLE, AND LAMP DRIVER• HIGH CURRENT CAPABILITY ••• 250 mA SINKING CURRENT AT 0.5 VOLT

.040

• HIGH VOLTAGE CAPABILITY ••• 40 VOLTS LVceo• LOGIC FLEXIBILITY •••••••• 4 INPUT NANO WITH INHIBIT (NOR) INPUT

LlDJ• HIGH SPEED ••••••••••• t 0 N =70 ns (TYP) • • toFF

=110

.335
.370ii
.335
.J85
13051
.J65

IF

!~-,- 500

ns (TYP).JOOJ9LEADS.OJ6DIA.

m~~~~m .040
MAX. MIN
I.
-.230 TPABSOLUTE MAXIMUM RATINGS (25°C Free Air Temperature unless otherwise noted)
Voltage Applied to Pin 8
Voltage Applied to Pin 10
Operating PowerOperating Temperature
Storage Temperature
Input Reverse Current
Current on Pin 8+40Volts
8Volts
SOD mW(See Part Nos.)-65°C to +150°C
1 mA
lAmp

NOTES: All dimensions in inches
Leads are gold-plated kovar
Package weight is 1.32 grams

PART NO. -55°C TO +125°C HAG·2001111X
o•c TO + 70°C HAG 20019JIXLOGIC SYMBOLS AND FUNCTIONS

BG- PACKAGETOP VIEW

8l"--_J--...
2
34...--,,_ _,8 = 1·2·3•4 + 9 POSITIVE(NANO LOGIC)
6

7

1·
·1
-~-_l_
.-T
.760

.083
.077

.006
.004

PART NO. -55°C TO +125°C HBG-2001111X
o•c TO + 70°C HBG 20019XX

FAIRCHILC'

313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-1

SEMICONDUCTORA DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD HYBRID CIRCUITS SH-2001
GUARANTEED TEST SEQUENCE SH-2001
LTPD
GROUP

TEST NO.

A
A
A
A
A
A
A
B
B
B
B
B

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22*
23*

PIN 1

PIN2

PIN3

PIN4

PIN 5

VIH
VIL
VIL

VIH

VIH

VIH

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

VIL
VIL

c
c
c
c
c

D
E
F
F
F
F

VR
GND
GND
GND

GND
VR
GND
GND

GND
GND
VR
GND

VF
VR
VR
VR

VR
VF
VR
VR

VR
VR
VF
VR

VIL
GND
GND
GND
GND
VR
VR
VR
VR
VF
GND

GND
GND

PIN 6

PIN 7

PINS

PIN9

GND
GND

IOLI
IOLI

VIL

IOL2
IOL2
IOL2
IOL2
IOL2

VIH

VR

VF
GND
GND
GND

Vox

PIN 10

SENSE

VccL
VccL
VccL
VccL
VccL
VccL
VccL
VccH,
VccH
VccH
VccH
VccH
VccH
VccH
VccH
VcCH
VccH
VccL
VccL
Vpo
VMAX
Vpo
Vpo

Va
Va

i,
12
13
14
19
i,
12
13
14
19

v6

VoH

la
I IO
110

FORCING FUNCTIONS (Temperature Range -55°C to +125°C)

I

UNITS

-55°C

+25°C

+125°C

Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Milliamps
Milliamps
Volts

4.50
5.50

4.50
5.50

1.40
2.10
4.00
0.00
250
8.00
40.0

4.50
5.50
5.00
8.00
1.10
1.90
4.00
0.00
250
8.00
40.0

0.80
1.70
4.00
0.00
250
7.50
40.0

UNITS

0°C

+25°C

+10°c

Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Milliamps
Milliamps
Volts

5.00
5.00

5.00
5.00
5.00
8.00
1.10
1.90
4.00
0.45
250
8.0
40.0

5.00
5.00

FORCING FUNCTIONS (Temperature Range 0°C to +70°C)

..

VccL
VccH
Vpo
VMAX
VIL
VIH
VR
VF
lou
loL2
Vox

1.20
2.00
4.00
0.45
250
8.0
40.0
5-2

LIMIT
MAX.
VOL
VOL
VOL2
VOL2
VOL2
VOL2
VOL2
IR
IR
IR
IR
IR
-IF
-IF
-IF
-IF
-IF

v6
v6
v6
v6
v6

*See Test Conditions and Definitions on Page 3

VccL
VccH
Vpo
VMAX
VIL
VIH
VR
VF
lou
IOL2
Vox

MIN.

.950
1.80
4.00
0.50
250
7.5
40.0

lox
IPDH
IMAX
toN
to FF

FAIRCHILD HYBRID CIRCUITS SH-2001
TEST LIMITS (Temperature Range -55°C to +125°C)
-55°C
UNITS

MIN.

Volts
Volts
Volts
Microamp
Milliamp
Microamp
Milliamp
Milliamp
Nanosec.
Nanosec.

Voll
VOL2
VoH
IR
-IF
lox
IPDH
IMAX
loN
to FF

+25°C
MAX.

MIN.

+125°C
MAX.

MIN.

MAX.

0.40
0.40

0.45
0.45
2.20

0.45
0.45

2.00

1.80
2.0
1.60
5.0
30.6
29.6
160
220

1.60

5.0
1.50

:mo

TEST LIMITS (Temperature Range 0°C to +70°C)
0°C
UNITS
Volts
Volts
Volts
Microamp
Milliamp
Microamp
Milliamp
Milliamp
Nanosec.
Nanosec.

You
VOL2
VoH
IR
-IF
lox
IPDH
IMAX
toN
to FF

+25°C

MIN.

MAX.

MIN.

+10°c
MAX.

0.45
0.45

MIN.

MAX.

0.45
0.45

2.05

0.5
0.5

1.95

1.85
5.0
1.40
5.0
30.6
34.0
200
260

1.40

10.0
1.35
200

TABLE OF LTPD'S (These apply to test sequence page 2)
GROUP

COLD

25°C

HOT

A
B
c
D
E
F

15%

10%
10%
10%
10%
10%
10%

15%
15%
15%
15%
15%
15%

15%
15%

TYPICAL SWITCHING TIMESSWITCHING TIME TEST CONDITIONS~

2001---+--+~+---+--+~l---+--+~I--~"'c:l~l---+--+~+---+--+~l---+-'"'""""k1_'-+---I~

FREQ.= lMc
P.W.= 500ns

INPUT

-50°C

25°C
TEMPERATURE~200n

PULSE ~-<_r..>-..r--""' PIN 10 = Vee = 5VGEN.
~,............,,

125°C

ov

_ _,,.

t 2V

PIN 5, PIN 7 GND

~

r L~~
5-3

\

I .,
Ic

"<'cJ
\ '-,__,.....-/l--'l·,,N\r--1..

IC

4V

'

4V

2V

,,J

OUTPUT"'10 pf= WIRING
CAP.

-::-

l.

40V

I

FAIRCHILD HYBRID CIRCUITS SH-2001

APPLICATIONSLAMP DRIVER3 • #327 BULBSINPUTS FROM,.,___.---...
DECADE
COUNTER,ETC.

LAMP TESTLATCHING RELAY-

UNLATCHINPUTS{~

3
LATCH INPUT

96+28V DC

Relay will unlatch if any input (1, 2, 3) goes low.

DTµL INTERFACE DRIVER-

r-0--...---0 OUTPUT(Logic levels selectedby Vccl-=-Vee

RL ~ 1600 at Vee = 40 VOLTS
RL ~son at Vee= 20 VOLTS

HIGH-CURRENT LINE TRANSMITTER-r<>4~===:)1--<>0UTPUT

INVERTING
INPUTS

500 CABLE

500

Vee(UP TO +12 V)

NON-INVERTING INPUTNOTE: If only non-inverting input is used, one of the inverting inputs must be grounded.

5-4

SH2002
DTµL HIGH POWER DRIVER
FAIRCHILD HYBRID CIRCUITS• LOGIC FLEXIBIUn ••••••• LATCHABLE 4 INPUT NAND WITH INHIBIT (NOR) INPUT• HIGH CURRENT CAPABILln • • • UP TO 150 mA• HIGH VOLTAGE CAPABILln ••• 40 VOLTS LYceo• INPUT COMPATIBLE WITH CCSL PRODUCTS• FULL -ss·c TO +125°C TEMPERATURE OPERATION• APPLICATIONS INCLUDE CABLE AND LAMP DRIVER

PHYSICAL DIMENSIONS
T0-100(10 pin package)

335

.185

3o5l

.165

~W4+
=- ~:.

10 LEADS

ABSOLUTE MAXIMUM RATINGS (25°C Free Air TelJlperature unless otherwise noted)
Voltage Applied to Pin 10 (continuous)
Input Reverse current
Voltage Applied to Pin 8 (continuous)
Voltage Applied to Pin 10 (pulsed ~ 1 second)
Storage Temperature
Operating TemperaturePower Dissipation (Derate Linearly to +175°C)

~

_040

.335
.3703it:g~: DIA.

+8.0Volts
l.OmA+40Volts+12Volts-ss•cto +1so 0 c(See Part Nos.)
800mW

lffinnnnnn
twUU uuuu

I.230 TPNOTES: All dimensions in inches
Leads are 1old·pl1ted kovtr

Packqe wei1ht is 1.32 1r1m1

HAGz0021xx <-ss•c TO +1zs•C)
HAGZOOZ9XX (0°C TO +70°C)

LOGIC SYMBOLS AND FUNCTIONSBG - PACKAGE
TOl'YIEW

1.---108Vee.019~~1
-T_
!:~~
j

I
f--:~~ --j

TOP VIEW

f--~--j.0061>

7

60---------GND·~--c:::=:=>.;;;;;;;;;;;;;;;¢

I

f-~--l ·:ib

NOTES: Alldl!Nllllo"'lnlnc:llff

AlternltemerkiflloldotlnupperlefttllMlcon11ris

L_5

1lt011CCeptlibl•

PKkl.. W111htl11ptlJOldfnlltefy0.71ft'-

HBGZOOZIXX (-55°CTO +1Z5°C)
HBGZOOZ9XX (0°C TO +70°C)

FA.I RCH IL.CJ
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-5

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD DIODE TRANSISTOR MICROLOGIC® l.C.
GUARANTEED TEST SEQUENCE SH2002

TEST NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

LTPD
GROUP
A

A
A
A
A
A
A
B
B
B
B
B

PIN 1

PIN 2

PIN 3

PIN4

PIN 5

VIH
VIL
VIL

VIH

VIH

VIH

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

VIL
VIL

c
c
c
c
c
D
E
F
F

VR
GND
GND
GND

GND
VR
GND
GND

GND
GND
VR
GND

VF
VR
VR
VR

VR
VF
VR
VR

VR
VR
VF
VR

VIL
GND
GND
GND
GND
VR
VR
VR
VR
VF
GND

GND
GND

PIN 6

PIN 7

PIN 8

PIN 9

GND
GND

IOLI
loll

VIL

loL2
IOL2
IOL2
IOL2
loL2

VIH

VR

VF
GND
GND
GND

Vox

PIN 10

SENSE

VccL
VccL
VccL
VccL
VccL
VCCL
VccL
VccH
VccH
VccH
VccH
VccH
VccH
VccH
VccH
VccH
VccH
VccL
VccL
Vpo
VMAX

Va
Vs

11
12
13
14
19
11
12
13
14
l9

vb
lg
110
110

Vax

UNITS

-55°C

+25°C

+125°C

Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Milli amps
Milliamps
Volts

4.50
5.50

4.50
5.50

1.40
2.10
4.00
0.00
150
8.00
40.0

4.50
5.50
5.00
8.00
1.10
1.90
4.00
0.00
150
8.00
40.0

0.80
1.70
4.00
0.00
150
7.50
40.0

UNITS

0°C

+25°C

+70°C

Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Milliamps
Milliamps
Volts

5.00
5.00

5.00
5.00
5.00
8.00
1.10
1.90
4.00
0.45
250
8.0
40.0

5.00
5.00

FORCING FUNCTIONS (Temperature Range 0°C to +70°C)

VccL
VccH
Vpo
VMAX
VIL
VIH
VR
VF
loll
IOL2

Vax

1.20
2.00
4.00
0.45
250
8.0
40.0

5-6

.950
1.80
4.00
0.50
250
7.5
40.0

LIMIT
MAX.
VOL
VoL
VOL2
VOL2
VOL2
VOL2
VOL2
IR
IR
IR
IR
IR
-IF
-IF
-IF
-IF
-IF

vb
vb
vb
vb
vb

FORCING FUNCTIONS (Temperature Range -55°C to +125°C)

VccL
VccH
Vpo
VMAX
VIL
VIH
VR
VF
loll
loL2

MIN.

VoH
lox
IPDH
IMAX

FAIRCHILD DIODE TRANSISTOR MICROLOGIC® l.C.
TEST LIMITS (Temperature Range -55°C to +125°C)
-55°C
UNITS

MIN.

MIN.

MAX.

0.45
0.45

Volts
Volts
Volts
Microamp
Milliamp
Microamp
Milliamp
Milliamp

Voll
VoL2
VoH
IR
-IF
lox
IPDH
IMAX

+125°C

+25°C
MAX.

2.20

MIN.

MAX.

0.40
0.40
2.00

0.45
0.45
1.80

2.0
1.60
5.0
30.6
29.6

1.60

5.0
1.50
200

TEST LIMITS (Temperature Range 0°C to +70°C)
0°C
UNITS

MIN.

MIN.

+10°c
MAX.

0.45
0.45

Volts
Volts
Volts
Microamp
Milliamp
Microamp
Milliamp
Milliamp

VOLi
VoL2
VoH
IR
-IF
lox
IPDH
IMAX

+25°C
MAX.

MAX.

0.45
0.45
1.95

2.05

MIN.

0.5
0.5
1.85

5.0
1.40
5.0
30.6
34.0

1.40

10.0
1.35
200

TABLE OF LTPD'S (These apply to test sequence page 2)
GROUP

COLD

+25°C

HOT

A

15%

10%
10%
10%
10%
10%
10%

15%
15%
15%
15%
15%
15%

B
15%
15%

c
D

E
F

SWITCHING TIME TEST CONDITIONSTYPICAL SWITCHING TIMES

400ilo----vv..~---------<> OUTPUT

2001--1--+-+-+--+--+--+-+-t-1

C"'lOpF=WIRING CAP
FREQ.= lMHz
P.W. =500ns

OL...-J.-'--'--'--'--_.__..._..__.__.
-50'C

25'C

TEMPERATURE

125'C

PIN 5, PIN 7 GND

FAIRCHILD DIODE TRANSISTOR MICROLOGIC® l.C.
APPLICATIONSLAMP DRIVER-

2 - NO. 327 BULBS+28V DCLATCHING RELAY-OR FAULT LAMP DRIVER

N0.330BULB

LATCH INPUT 9

D

6 o-------1---'

_c:::

-:

~
+28VDCRELAY WILL UNLATCH IF ANY INPUT ( 1, 2, 3) GOES LOW.

OUTPUT TRANSFER PULSE SAFE OPERATING AREA

VcE - COLLECTOR TO EMITTER VOLTAGE-VOLTS

5-8+ 14V DC

SH2002-P
DTµL HIGH POWER DRIVER
IN PLASTIC DUAL-IN-LINE PACKFAIRCHILD HYBRID CIRCUITS• LOGIC FLEXIBILITY • • • • • • • LATCHABLE 4 INPUT NAND WITH INHIBIT (NOR) INPUT• HIGH CURRENT CAPABILITY • • • UP TO 150 mA
PHYSICAL DIMENSIONS• HIGH VOLTAGE CAPABILITY ••• 40 VOLTS LVceo• INPUT COMPATIBLE WITH CCSL PRODUCTS• APPpCATIONS INCL~DE CABLE, LAMP, AND RELAY DRIVER

ABSOLUTE MAXIMUM RATINGS (25°C Free Air Temperature unless otherwise noted)
Voltage Applied to Pin 10 (continuous)
Input Reverse Current
Voltage Applied to Pin 8 (continuous)
Voltage Applied to Pin 10 (pulsed ~ 1 second)
Storage Temperature
Operating TemperaturePower Dissipation (Derate Linearly to +175°C)+8.0Volts
1.0 mA+40Volts+12Volts-ss•cto +1so 0 c
0°c to +10°c
800mW

.011

.009

.110
.090

L
,-.023.015

NOTE: All dimensions in inches

H&F20029xx co•c TO +10°c>

LOGIC SYMBOLS AND FUNCTIONS

l.---108Vee

760-------+--'

GND

L_5

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379.-6435

5.9

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD HYBRID CIRCUIT SH2002-P
GUARANTEED TEST SEQUENCETEST NO.

1
2
3

4
5
6
7
8
9
10
11

12
13
14
15
16
17
18
19
20
21

LTPD
GROUP

A
A
A
A
A,
A
A
B
B
B
B
B

PIN 1

PIN 2

PIN3

PIN4

PIN 5

VIH
Vil
Vil

VIH

VIH

VIH

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

Vil
Vil

c
c
c
c
c

VR
GND
GND
GND

GND
VR
GND
GND

GND
GND
VR
GND

VF
VR
VR
VR

VR
VF
VR
VR

VR
VR
VF
VR

D
E

GND

F
F

GND

Vil
GND
GND
GND
GND
VR
VR
VR
VR
VF
GND

PIN 6

PIN 7

PIN 8

PIN9

GND
GND

loll
loll

Vil

10l2
10l2
10l2
lm2
10l2

VIH

VR

VF
GND
GND
GND

Vox

PIN 10

SENSE

Vccl
Vccl
Vccl
Vccl
Vccl
Vccl
Vccl
VccH
VccH
VccH
VccH
VccH
VccH
VccH
VccH
VccH
VccH
Vccl
Vccl.
Vpo
VMAX

Va
Va
v6
v6
v6
v6
v6
1,
12
13
14
l9
1,
12
13
14
19
v6
la
110
110

FORCING FUNCTIONS (Temperature Range 0°C to +70°C)

Vccl
VccH
Vpo
VMAX
Vil
VIH
VR
VF
loll
10l2
Vox

UNITS

0°C

+25°C

+70°C

Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Milliamps
Milliamps
Volts

5.00
5.00

5.00
5.00
5.00
8.00
1.10
1.90
4.00
0.45
150
8.0
40.0

5.00
5.00

1.20
2.00
4.00
0.45
150
8.0
40.0

5-10

.950
1.80
4.00
0.50
150
7.5
40.0

MIN.

LIMIT
MAX.
Vol
Vol
v0l2
v0l2
v0l2
v0l2
v0l2
IR
IR
IR
IR
IR
-IF
-IF
-IF
-IF
-IF

VoH
lox
IPDH
IMAX

FAIRCHILD HYBRID CIRCUIT SH2002-P
TEST LIMITS (Temperature Range 0°C to +70°C)
+25°C

0°C
MIN.

UNITS

IMAX

+70°C
MAX.

MIN.

MAX.

0.45
0.45

0.45
0.45

Volts
Volts
Volts
Microamp
Milliamp
Microamp
Milliamp
Milliamp

Voll
VOL2
VoH
IR
-IF
lox
IPDH

MIN.

MAX.

2.05

0.5
0.5
1.85

1.95

10.0
1.35
200

5.0
1.40
5.0
30.6
34.0

1.40

TABLE OF LTPD'S (These apply to test sequence page 2)
GROUP

0°C

+25°C

+70°c

A

15%

10%
10%
10%
10%
10%
10%

15%
15%
15%
15%
15%
15%

B
15%
15%

c
D
E
F

TYPICAL SWITCHING TIMEVERSUS AMBIENT TEMPERATURE

SWITCHING TIME TEST CONDITIONS

160 1---+--+--f--+--+---i----<

400D.
o------'vv..~-----+---<> OUTPUT

C"'lOpF•WIRING CAP
FREQ.• !MHzP.W. • 500 ns

PIN 5, PIN 7 GNOo~~~~~~~~~

o

w ro

~

~

~

60

ro

TA - AMBIENT TEMPERATURE - °C

40V OUTPUT
INPUT

f
4V

2V

ov-....__ __,,

I

~ 1 on--J

5-11

4V

2V

4V

1off

FAIRCHILD HYBRID CIRCUIT SH2002-P
APPLICATIONSLAMP DRIVER-

2 - NO. 327 BULBS+28V DCLATCHING RELAY-OR FAULT LAMP DRIVER

N0.330BULB

LATCH INPUT 9

D

6e>-------+--'

r=:
r=:

..,,.
+28VDCRELAY WILL UNLATCH IF ANY INPUT (1,2,3) GOES LOW.

OUTPUT TRANSFER PULSE SAFE OPERATING AREA

VcE-COLLECTOR TO EMITTER VOLTAGE-VOLTS

5-12+14VDCSH2100
HIGH CURRENT DRIVERHYBRID CIRCUITSGENERAL DESCRIPTION-The SH 2100 Hybrid consists of a Buffer Micrologic® Integrated

Circuit driving a high-current NPN Planar* Epitaxial Silicon Transistor.

PHYSICAL DIMENSIONS(lllMIMTOT0-5)*Planar is a patented Fairchild process.

•

135 mA CURRENT SINKeINPUT COMPATIBLE WITH 11L, MW11L, DT11L, AND CTIJLeOPERATES AT 12V•

FAN-OUT=200 IJLOGIC LOADSABSOLUTE MAXIMUM RATINGS (25°C Free Air Temperature unless otherwise noted}
Maximum Temperatures
Storage Temperature-65°c to +150°c

Operating Temperature-55°c to +125°C

Maximum Voltages

NOTES:Olm11nmlons11perl1tntHOeommitt..
Alldlm11nslonsinlnchH
l.NdslfllOld·plat«lkovar

Maximum Voltage Applied to Pin 8+12 Volts

Maximum Voltage Applied to Pin 3±4 Volts

Maximum Voltage Applied to Pin 5

VCBO+30 Volts

LVCEO+12 Volts

hckmctwellhtisl.221r1ms

PART NO. HXK21001XX -55'C TO +125'C
HXK21009XXO'C TO +70'C
G - PACKAGE

Maximum Total Power Dissipation at 25°C Ambient

500 mW

Typical Power Dissipation at 25°C Ambient

65mW

Maximum Current Applied to Pin 5

500 mA

Maximum Fan-out (Rout = 20 C! ± 5%) into RTL Micrologic

200•

TOP VIEWFLAT PKG .

----,Vee 10

I

•

I

8

Ref

,.

...

.,

"'"

-?==J--=t

____.
7

.760

L

I

I

.083
.077'

.006
.004

PART NO. HBG21001XX -55'C TO +125'C
HBG21009XXO'C TO +70'C

TOP VIEWLOGIC: A=B

DC ACCEPTANCE TEST CONDITIONS
Test
No.
1

V5

v

Test Conditions
Pin 4
Pin 5
GND
VIN
VOFF GND
VR2

15

mA

VON

Test
Title

1a

Units
mA

Finl Pin2

Pin 3

Pin 6 Pin 7

Pin 8

Test Limits
Min. Typ. Max.

vcc

2irn

vcc
vmax

1CEX

2
3
4

t3+5+

See Switching Time Test Circuit

30 nsec

t3-5-

See Switching Time Test Circuit

70 nsec

5

GND

vmax

vout

FAIRCHIL.CJ
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-13

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD HYBRID CIRCUITS SH2100

DC ACCEPTANCE TEST LIMITS

Symbol*Test Tolerance-55°C ±2°C

Vee

±0.010 v

3.00 v

3.00 v

3.00V

VIN±0.002 v

1.014 v

0.844 v

0.674 v

VON

±0.002 v

1.014 v

0.815 v

0.674 v

VOFF

±0.002 v

0.710 v

0.565 v

0.320 v

VR2
vout

±0.01

vmax

±0.01 v

n

21iN
1CEX

25°C ± 2°C+125°C ± 2°C

20 n

20 n

20 n

0.710 vo.• 3oo v

0.320 v

12.0 v

12.0 v

12.0 v

0.990 mA
0.100 mA

0.870 mA
0.218 mA

0.940 mA
0.235 mA

*For definition of the symbols refer to standard Fairchild Micrologic specification.

TESTS FOR END POINTS GROUP B 1, 2, 3
LTPD'S

Test 1

10% 25°C

15%-55° & +125°C

Group A

Test 2

10% 25°C

15%-55

Test 3

10% 25°C

15%-55° & +125°C& +125°C

NOTE: Fairchild.Assured Customer Test Programs are Identical to latest issue Epitaxial µLogic Tentative Specifications.
NOTE: Mid-Range .(0°C to 70'C) SH2100 Hybrids may be operated over the full m!lltary (-55°C to +125'C) temperature range by using asliding voltage power supply which varies linearly from 4.2 VDC at -55°C to 2.6 VDC at +125'C.

SWITCHING TIME TEST CIRCUIT

vee
vee

vee

vee

RouT

l_

20(!

Input

_J_

Input

::=f-"J:::GNDµL 903GNDµL 903

GND
FULL DRIVE
EQUIVALENT
LOAD

100 nsec

For Low Drive

l~

e

1rn }
300pf

FD2
or
FD6

-

INPUT
SCOPE

NOTE: FULL DRIVE IS EQUIVALENT TO FAN-OUT OF
200 MieROLOGie GATES.
LOW DRIVE IS EQUIVALENT TO FAN-OUT
OF 40 MieROLOGie GATES.

TA =25°C

5-14J_
Output 0.5V
tpd 1

OUTPUT
SCOPE

0.5V

tpd2

FAIRCHILD HYBRID CIRCUITS SH2100

RULES FOR SELECTING VALUES OF RouT
(Applicable over -55°C to +125°C

temperature range. )Primary consideration is to minimize overdrive to driven elements and reduce power drain.

FANOUT MAXIMUM VS. Rour

A. MICROLOGIC Elements

20f! ± 5%4,000------0
Max Fan-out Used

80
Rour IN Q

FANOUT MAXIMUM VS. Rour
800

B. MW11L Elements
R 00t(min)20f! ± 5%
13,000-------0Max. Fan-out Used

OL.....l---L----l.-L-1..-L.--1--'---'--J
0

40

80

120

160

Rour IN Q

tpd 1

34

TYPICAL
VERSUS TEMPERATURE

tpd z

TYPICAL
VERSUS TEMPERATURE

V1N VERSUS 211N

58 ~1~1~1~~~~,..--1 } 1

f- '-d 11-2.25015001i-+---+---+----<.___.,

f- lpd 2ll:M~1Wit00 ~ -+---+-17il-'~'rT1'+---1

m,1--+--+--t--+-f--+---+---1~l-.1-.1-.1-.1-.1-/~u+-+--ll' I

2-llQJOOjt

60
"

4.0

421--1---l---+--+-+IZ--R---+---I

2~

34

ll-

J

l l l

5.011--21+-;n_vert-su-lsv_in-+--+--+-+--+.y MAX.-

~

Vin

/-

yN.

-+---+.1_L'-+-_,,..L'-+--l1
3.0,1--+--+--1--tt-

Iv v

IT
2.01--+--+--l--fl--vf+-~1---11---11---1

I/ J

I

21; 0 Test

Pol"\ !11/

21;0 -~-f- =f-~
18-60

60
120
Hfii1PERATURE IN °C

180

26-60

0
60
120
TEMPERATURE IN °C

5-15

180

0.4

~

0.8

1.2

Vin - VOLTS

1.6

2.0

FAIRCHILD HYBRID CIRCUITS SH2100
APPLICATIONS-When driven from standard MICROLOGIC
Input Loading
Factor2 when driven
from Micrologic
6.0 when driven
from MWµL#47 or#328 or Equivalent

LAMP DRIVER

GND

6V or 12V

E
Sole:::;::,::,r--<>than 250 mA current

RELAY DRIVER--cdrain

G:ND+ 12VDC

V DC~

2 times desired
pulse amplitude

R =5051

50 51 LINE DRIVER

GND
R =5051

R can be 7551 or 9351 forcables of these impedances

CORE MEMORY DRIVER

5051

2051 ±5%
1/2 w
Clock Inputof
100 µL 926 or 923µLOGIC CLOCK DRIVER
GND

Elements

To additional SH 2100
as needed

5·16

SH2101
HIGH VOLTAGE DRIVERHYBRID CIRCUITS.

GENERAL DESCRIPTION-

The Fairchild SH 2101 Hybrid High-Voltage Driver consists of an

Integrated 4-input Milliwatt RTµL Gate driving a High-Voltage Transistor.

PHYSICAL DIMENSIONS(SIMILARTOT0·5)•

100 VOLT OUTPUT-CAN SINK TO 10 mA•

INPUT COMPATIBLE WITH 11L, MILLIWATT RT11L, DTIJL, AND CT11L•

FULL -55°C TO +125°C TEMPERATURE OPERATION•APPLICATIONS INCLUDE NEON BULB AND GAS READOUT TUBE DRIVER AND HIGH VOLTAGE
INTERFACING

ABSOLUTE MAXIMUM RATINGS(25°C Free Air Temperature)

Maximum Voltage Applied to Pin 8 (continuous)+8.0 Volts

Maximum Voltage Applied to any Input Pin (continuous)± 4.0 Volts

Maximum Voltage Applied to Pin 6 (continuous)+100 Volts

Maximum Voltage Applied to Pin 8 (pulsed ~ 1 second)+12 Volts

Maximum Storage Temperatµre-65°C to +150°C

Maximum Operating Temperature-55°C to +125°C

Maximum Power Dissipation ·

.,.

...
NOTES ~I":,~~::,:~: ~::~= J.10 committee
Leo~· •••frOld platf'd ko•a•P•ck11<wa11hl10ll2F•m•

250 mWOPERATING VOLTAGE RANGEVCC (Pin ~)VH-(Pin 6)+3.0 ± 10% to +4.0 ± 10% Volts

PART NO. HXK2101TXX
T=l FOR -55°C TO +125°C TEMP. RANGE
T=9 FOR 0°C TO +70°C TEMP. RANGE< +100 Volts

LOAD CHART

LOGIC SYMBOLNEGATIVE LOGIC: 6
POSITIVE LOGIC: 6= 1 •2 •3 • 5= 1+2+3+5
GND.

PIN 7 IS AN EXPANDER INPUT.
ADDITIONAL PAIRS OF INPUTS
MAY BE ADDED USING THE' MIL·
LIWATT RTµL EXPANDER, FOL·
LOWING THE LOADING RULESSHOWN ON THE MILLIWATT RTµl
921 DAiTA.~HEET.
.

DRIVEN BYMILUWATT RT.alµL
CTµL

N (EQUIV. INPUT LOAD)
1

'h
1/3

DRIVEN BY

NO. OF SH-2101 ALLOWEDDTµL GATEBUFFER

3 MAX WITH NO DTµL FANOUT{ 10 MAX WITH NO DTµL FANOUT
1 MAX WITH SPECIFIED DTµL FANOUTSE;MICDNDUCTDR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-17

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATION.FAIRCHILD HYBRID CIRCUIT SH2101

TEST CONDITIONS
Test
No.

Test
Title

Units

1

11

mA

12

mA

3
4

Pin 4

Pin 2

Pin 3
VBOT

GND

VBOT

VBOT

VBOT
VIN

VBOT

GND

VBOT

13

mA

VBOT

VBOT

VIN

GND

VBOT

15

mA

VBOT

VBOT

VBOT

GND

VIN

5

Va

mV

VOFF

a

Ia

µ.A

VOFF
GND

GND

VOFF
GND

10L
VH

7

Ia

µ.A

VON
GND

VOFF
GND

GND

GND

GND

GND

VH

8

16

µ.A

GND

VON
GND

GND

VH

GND

VON
GND

GND

GND

GND

2

Pin 1
VIN

Pin 5

TEST LIMITS
Pin aMin. Typ. Max.
1iN

1iN
1iN
1iN
VOL

Vee

Ia

10

tl-a-

nsec

Pulse in

GND

GND

GND

VON
GND

VH
Pulse out

11

tl+a+

nsec

Pulse in

GND

GND

GND

GND

Pulse out

DC TEST LIMITS

Pin 8

vcc
vcc
vcc
vcc
vcc

µ.A

9

Pin 7

lox
1ox
1ox

vcc
vcc
vcc
vcc
vcc

1ox
200
1ao

-55°C

+25°C

+125°Cv

3,00 :1:0.01

3.00 :1:0.01

3,00 :1:0.01

VBOT

v

1.80 :1:0.01

1.80 :1:0.01

1.80 :1:0.01

VIN

mV

970 :1:2

805:1:2

590:1:2
555:1: 2
2ao:1: 2

vcc
VON

mV

935 :1:2

750:1: 2VOFFmVa50 :1:2

450:1: 2

1iN

µ.A

125

130

110

VH

v

100:I:1

100:1: 1

100:1: 1

VOL

mV

220

220

320

µ.A

5

5

40

mA

10 +0.1

10 + 0.1

10 + 0.1lox
1oL

SYMBOLS AND DEFINITIONS

vcc

Supply Voltage

VON

Minimum threshold voltage which will insure an off output transistor.

VIN

Input voltage used to measure maximum I1N required to define fan-in.

VBOT

Voltage level sufficient to insure full saturation of remaining input transistors for measurement of worst case input loading.

VOFF

The maximum voltage which may be applied to an input terminal without turning on the transistor.

1iN
VOL
1ox

Maximum saturated output voltage when V OFF voltage is applied at all inputs and 10 L is supplied to output collector.
Collector leakage current when VON is applied to one input and VH is applied to output collector.

1oL

Output transistor collector current.

VH

Voltage applied to output collector to measure lox·

The current drawn from the v1N supply by one input of a gate with a fan-in of two or more.

5-18

FAIRCHILD HYBRID CIRCUIT SH2101
SWITCHING TIME TEST CIRCUITPULSE IN

Vcc=3VIL

3.6K---..-ii 1--soo ns

sv

T.P.

51

PIN 6

GNO.

GROUND UNUSEDINPUT PINS

T on- - - .

TYPICAL ELECTRICAL CHARACTERISTICS

FIG. 1

FIG. 2TYPICAL SWITCHING TIMES

FIG. 3TYPICAL INPUT CHARACTERISTICS

TYPICAL POWER DISSIPATION
VS. Vee (FOR OPEN OUTPUT)
8.0

i-

~

.,0.....' 6.0

300 ns

r/-

z

~

c:

1on

' 200 ns~t--f--47

100 ns

:s-

;:::

ct:
.....
0.

z

85 4.0~.....
<:>

01--.....__.....~_..._.....__._~~"\_

1-lo11

0.2 0.4 0.6 018 1.0 1.2 1.4

v1N - voLTs
-55°e

+25°e
TA - AMBIENTTEMP - °C

+125°e

II

<
ct:
.....
>
<

2.0

7

~

v

1-----~+------25°e.80 Vi1-----.~97~V+-1- - - - - - 5 5 o e' - - - - - =.59V'------125°e
NOTE: This curve will apply as VCC is increased from
3 V to 5 V with small decrease infor same VIN"

fxN

5-19

2.0

4.0
Vee - VOLTS

6.0

8.0

FAIRCHILD HYBRID CIRCUIT SH2101

TYPICAL APPLICATION

Sl:!210.l
lOK~----------v.J'v.----0170V

INPUTSBOKTO OTHER i.S.H.210.11 DRIVERS

NIXIE® - Re1i1tered Trade lbrk Burrou1h1 Corp.

Yee

INPUTSNEON GLOW LAMP DRIVER
NOTE: LAMP LIGHTS ONLY
WHEN ALL INPUTS ARE LOWINPUTSINTERFACE GATEMICROLOGIC TO 24 VOLT LOGICNOTE: FOR 12 VOLT CIRCUITSUSE 1.2K RESISTOR AND +12 VOLT SUPPLYFOR DTµL AND TTµL CIRCUITSUSE 2K RESISTOR AND +5 VOLT SUPPLY

5-20

SH2200
HIGH-VOLTAGE, HIGH-CURRENT DRIVER
A FAIRCHILD HYBRID DESIGN SPECIFICATION CIRCUITFEATURES• INPUT CCSL COMPATIBLE• HIGH SINKING CURRENT CAPABILITY ••• 500 mA AT 0.6 VOLT
• HIGH VOLTAGE CAPABILITY ••••••••• 50 VOLTS, V0 x
• LOGIC FLEXIBILITY •••••••••••••• 4 INPUT NAND WITH INHIBIT (NOR) INPUTPHYSICAL DIMENSIONSPLASTIC DIP~c32Q~.300

APPLICATIONS• RELAY AND LAMP DRIVER WITH LATCHING• TAPE READOUT, TEST EQUIPMENT• SOLENOID DRIVER_jl--.010 TYP.

.150 MIN.n

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
METAL CAN &Maximum Temperature
FLAT PACK
Storage Temperature-65°C to +200°C
Operating Temperature-55°C to +125°C*METAL CAN
800mW

TYP.

_LLi

.100

TYP.

Maximum Power Dissipation
At 25°C Ambient Temperature

Fl
r.120

f

r--~

r---

.050

PLASTIC DIP-65°C to +150°C
0°C to +70°C°FLAT PAK
750mW~

.075 MAX. -PLASTIC DIP
455mW

Maximum Voltages and Currents
Voltage Applied to Pin 8
Voltage Applied to Pin 10
Input Reverse Current
Current on Pin 8

METAL CAN (JEDEC T0-100)

H

:.t=j
I

.335

+50Volts
8.0 Volts
1.0 mA
l.OAmp_.3.35m""::~.~l*Use proper heat sink at temperature above 100°C.

m~~~~oo ~~~IMINm

ORDER INFORMATION
Specify H6F22009XX for 10 pin Plastic DIP, TA= 0°C to +70°C
HAG22001XX for pin Metal Can (JEDEC T0-100), TA = -55°C to +125°C
HBG22001XX for 10 pin Flat Pak, TA = -55°C to +125°C

DIA

LOGIC SYMBOLS AND FUNCTIONSFLAT PAK2
3
4

S = 1·2·3·4 + 9 POSITIVE(NANO LOGIC)l-rT-~1••10135 105_L:uo .095_.J....:£:_

.055

.240

__,L
-.-f.-.019 /.015

f ,6o------.-· L.37Q.2so---I5

6

TOPVIEW- - 370.r-----:250-J

l=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-21

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD HYBRID SH2200
GUARANTEED TEST SEQUENCELTPD GROUP AT

TEST
NO.

COLD

+25°c

2
3

B
B

A
A

4

-

-

0
6

I

-

9

B
B
B

!U

lf

11
TI

B

8

IT
14
15
TO
17
18

B
B

w

lf

20
21
22

B
B
B

~

-R
~

-

-

-

A

LIMITS

HOT

PIN 1

PIN 2

PIN3

PIN4

PIN 5

c
c

VIH
VIL

vll:L

VIH

~

GND
GND
GND
GND
uND
GND
GND
GND

-

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c

A

-

A

VIL
-v;L
VIL
VIL
VIL
VIL

~

G-WD
VR
GND
_§_ND

GNlY
GND
TR
uND

VF
VR
VR
VR

VR
VF

VR
VR

GND
GND
GND

'f'R
VR

GND

~

VR

-VIL
GND
GND
GND
GN-0
VR
VR
VR
VR
VF
GND

GND
GND
GND
GND
GND
GND
GND
GND
liNU
GND
GND
GND
GND
GND

UND

-

GND

PIN 6

PIN 7

PIN 8

GND
GND
GND
GND
GND

lo_il

PIN 9

!m.i.

\la

Voll
Voll
Voll
VOLi
VoL2
VOLZ
VOLZ
ToLz
VOLZ.
IR
IR
IR
IR
IR
-IF
-IF
-IF

~

Vll

~L

Y_c_e
Vee

~e

~

VJ_L

IQJ.J

v!b.

10L2
1obi
IOL2
loLz
IOLz

SENSE

"c._e

~

lo.LL

!mi

PIN 10

VIH

VR

Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee_
Vee
Vee
Vee

~

IOL3

GND
GND

GND

MAX

~I

~

~

Y_i,_

v6
v6
v6
v6
II
lz
13
14_
19
II
lz

~

"c._e

14

Y_p_

"s:c

GND

Vee
Vee
Yi>o
VMAX

~

Vox

MIN

Y_i,_

la
Tia
1,0

-Ir_

-!£_
VOHI
lox
Tpo
TMAX

FORCING FUNCTIONS (Temperature Range 0°C to 70°C)
SYMBOL

0°c

+25°c

+10°c

UNITS

Vee
Vpo
VMAX
VIL
VIH
VR
VF
Vox
loL1
loLz
IOL3

5.0

5.0
5.0
8.0
0.85
1.8
4.5
0.45
50
500
16
8.0

5.0

Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
mA
mA
mA

0.85
1.9
4.5
0.45
500
16

0.85
1.6
4.5
0.45
50
500
16

TEST LIMITS (Temperature Range 0°C to 70°C)
SYMBOL

o•c

+25°c

+10°c

UNITS

VOLi
VoLz
VOHI
IR
-IF
lox
lpo
IMAX

0.6
0.45
1.95

0.6
0:45
1.85
60
1.6
5.0
12.2
10

0.6
0.45
1.65
60
1.6
200

Volts
Volts
Volts
µA
mA
µA
mA
mA

1.6

5-22

FAIRCHILD HYBRID SH2200
FORCING FUNCTIONS (Temperature Range -55°C to +125°C)
SYMBOL

-55°C

+25°C

+125°C

UNITS

Vee
Vpo
VMAX
VIL
VIH
VR
VF
Vox
loL1
loL2
IOL3

5.0

5.0
5.0
8.0
0.9
1.7
4.5
0.4
50
500
16
8.0

5.0

Volts
Volts
Volts
Vo its
Volts
Volts
Volts
Volts
mA
mA
mA

0.8
2.0
4.5
0.4
500
16

0.8
1.4
4.5
0.4
50
500
16

TEST LIMITS (Temperature Range -55°C to +125°C)
SYMBOL

-55°C

+25°C

+125°C

UNITS

0.8
0.4
2.05

0.6
0.4
1.75
60
1.6
5.0
11
9.0

0.7
0.4
1.45
60
1.6
200

Volts
volts
Volts

You
VoL2
VOHI
IR
-IF
lox
lpo
IMAX

1.6

µA
mA
µA
mA

mA

ELECTRICAL CHARACTERISTICS

TYPICAL OUTPUT VOLTAGE
VERSUSAMBIENT TEMPERATURE

OUTPUT VOLTAGE
TEST CIRCUIT

1.2
~

1.0

~ 0.8

"'....

;!!

0I

I SH2200'le• 600mA

""-

1---

-55

1.

II

----1
le• 400m!_ ---1.!J;,_• 500mA.J 0.20-~-..... 50V

1
..--0

I

~

g 0.6
~
....

~ 0.4

Vee= 5.ov

r-------- -----------1\ -s::g

L-----

le, 3oomA
_l

0
25
70
TA - AMBIENT TEMPERATURE - •c

125

TYPICAL SWITCHING TIMEVERSUSAMBIENT TEMPERATURE

SWITCHING TIME TEST CIRCUIT

1oon

300

o-----vvv-----------oOUTPUT
PULSE
GEN.
200

'•"

100

'··
10

20

C"'10pF =WIRING CAP

FREQ.• 1MHz
PW• 500ns-l-1
PIN 10 • Vee • 5V
PIN 5, PIN 7 GND
30

40

50

60

70

TA -AMBIENT TEMPERATURE - 'C

5-23

FAIRCHILD HYBRID SH2200'
APPLICATIONLAMP DRIVER

INPUTS FROMDECADE
COUNTER,UP TO 50 VOLTSETC.

LATCHING RELAY OR FAULT LAMP DRIVER

60-------+---'UNLATCHINPUTSI~

2

3

II ~~~ABULB
CTO
c:50 VOLTS-:UP

TO 50 VOLTS

RELAY WILL UNLATCH IF ANY INPUT (1, 2, 3) GOES ~ow.

5-24

c:

SH2204
BYTE PARITY GENERATOR OR CHECKER
A FAIRCHILD HYBRID DESIGN SPECIFICATION CIRCUIT

GENERAL DESCRIPTION - The SH2204 consists of four high speed binary full adders. The design is two
9304 MSI circuits useful to generate parity for an 8 bit byte or to check parity over 9 bits. Delay from input
to odd parity is typically 35 ns. Additional parity units can be connected for larger word lengths.

PHYSICAL DIMENSIONS~1~1~1~1.050 ITYPICALFEATURES:• 35 ns TYPICAL INPUT TO ODD PARITY DELAY• ALL INPUT DIODE CLAMPING• CCSL INTERFACE.

--'------

T1=

7

8

.037
TYP
.Q90MAXl=L..
_l! :g1~,~~~TRANSFER SURFAC~ :003
ORDER PART NOS;:_HBK22041XX (-55°C to +125°C)
HBK22049XX (0°C to 70°C)

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Vcc Pin Potential to Ground Pin
Voltage Applied to Outputs for high output state
Input Vpltage (D.C.)-65°C to +150°C-55°C to +125°C-0.5Vto +7V-0.5Vto +Vccvalue-0.5 V to +5.5 V

PIN CONFIGURATIONLOGIC DIAGRAMFAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-25

A DIVISION OF FAIRCHILD CAMERA ANO INSTRUMENT CORPORAllONFAIRCHILD HYBRID CIRCUIT SH2204
ELECTRICAL CHARACTERISTICS (TA = -55°C to +125°C, Vee = 5.0 V ± 10%)
LIMITS
SYMBOLCHARACTERISTICS-55°C
MIN. MAX.

MIN.

2.2

2.4

+25°C
TYP. MAX.
2.7+125°cMIN. MAX.

UNITSCONDITIONS

2.4

Volts

Vee= 4.5 V, 10 H = -1.2 mA
Vee =4.5 V, loH = -1.08 mA
Vee =4.5 V, 10 H = -0.84 mA

Volts

Vee= 5.5 V, loL = 16 mA
IOL = 14.4 mA
IOL = 11.2 mA
Vee =4.5 V, loL = 12.4 mA
loL = 11.2 mA
IOL = 8.7 mA

Volts

Guaranteed input highthreshold for all inputs

VoH

Output High Voltage

VoL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.8

0.9

0.8

Volts

Guaranteed input low
threshold for all inputs

4 IF

In put Load Current-6.4-4.4 -6.4

-6.4

mA

Vee=5.5V

4 IF

Input Load Current-4.96-3.88 -4.96

-4.96

mA

Vee=4.5V

4 IR

Input Leakage Current

240

240

µA

Vee= 5.5 V, VR = 4.5
Ground on other inputs+25°C
TYP. MAX.

+10°c
MIN. MAX,

UNITS

2.4

Volts

Vee= 4.75 V, 10 H = -1.2 mA
Vee= 4.75 V, 10 H = -1.08 mA
Vee = 4.75 V, 10 H = -0.84 mA

Volts

Vee= 5.25 V, loL = 16 mA
IOL = 14.4 mA
10 L = 11.2 mA
Vee= 4.75 V, 10 L = 14.l mA
10 L = 12.7 mA
10 L = 9.85 mA

Volts

Guaranteed input highthreshold for all inputs

0.21

0.4

1.4

1.7

2.0

60

ELECTRICAL CHARACTERISTICS (TA= 0°C to +70°C, Vee= 5.0

0.4

0.4

VF=0.4V
VR = 5.5 Von
other inputsv

v ±5%)
LIMITS

SYMBOLCHARACTERISTICS

0°c
MIN. MAX.

MIN.

2.4

2.4

3.0

CONDITIONS

VoH

Output High Voltage

VOL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.85

0.85

0.85

Volts

Guaranteed input low
threshold for all inputs

4 IF

Input Load Current-6.4-4.0 -6.4

-6.4

mA

Vee= 5.25 V, VF= 0.45 V
VR= 5.25 Von other inputs

4 IF

Input Load Current-5.64-3.6 -5.64

-5.64

mA

Vee= 4.75 V, VF= 0.45 V
VR = 5.25 Von other inputs

4 IR

Input Leakage Current

60

240

µA

Vee= 5.25 V, VR = 4.5 V
Ground on other inputs

0.21

0.45

1.8

1.9

0.45

0.45

1.6

5-26

240

SH2205
RIPPLE CARRY ADDERA FAIRCHILD HYBRID DESIGN SPECIFICATION CIRCUIT

GENERAL DESCRIPTION - The SH2205 consists of four, high speed, binary full adders. The adder is usefulas ripple carry parallel addition (or subtraction) function blocks. Circuits are TTµL for high speed, highfanout operation and is compatible with all members of the CCSL group of digital integrated circuits.

PHYSICAL DIMENSIONS

r''o--j290

IF. =,I.009iffi
' \
Oil

Fl
'

FEATURES:·.WOMAX.

I-

375 NOM.

~• 8.0 ns TYPICAL CARRY PROPAGATION DELAY PER BIT• ALL INPUT DIODE CLAMPING• CCSL INTERFACE

L

!

.023
MAX.

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)-ss•c to +150°c-55°c to +125°c-0.5to+7V-0.5 V to +Vee value-0.5 Vto 5.5 V

Storage Temperature
Temperature (Ambient) Under Bias
Vee Pin Potential to Ground Pin
Voltage Applied to Output when output is highInput Voltage (D.C.)

NOTES'
I. Lnds are intended for insertion 1n hole rows on.300" centers. The)' are purposely shipped with"positive" (.375) m1sa!1gnment to facilitate 10s1Ht1on
2. Bo.,d·drilhnt dimensions should equal yourpractice for a conventmn'al .020 lincti diamete1 lud

ORDER PART NO. H6B22051XX

SCHEMATIC DIAGRAM

4

s,

S1

15

s.

S3

13

12

14

II

9

10

Vee= 16G['ID=

8

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-27

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD HYBRID SH2205
LOADING RULES (lUL= 1.6 mA)
INPUTSLOADING

A1, B1, A3, B3, & Cl 1
A2' B2' A4 & B4
OUTPUTS

TRUTH TABLE(Each Stage)
INPUTS

4UL

C1n
L
L
L
L
H
H
H
H

lUL
FAN OUTlOUL

SI & S3
S2 & S4

9UL
7UL

C0 4

~
L
L
H
H
L
L
H
H

OUTPUTS
Bn
L
H
L
H
L
H
L
H

Sn
L
H
H
L
H
L
L
H

con
L
L
L
H
L
H
H
H

ELECTRICAL CHARACTERISTICS (TA= -55°C to +125°C, Vee= 5.0 V ±10%)
SYMBOLCHARACTERISTICS

LIMITS-55°C+25°C+125°C
MIN. MAX. MIN. TYP.
MAX. MIN. MAX.

UNITSCONDITIONS

VoH

Output High Voltage

2.2

Volts

-VOL

Output Tow VOftage

VIH

Input ~1gh Voltage

VIL

Input Low Voltage

0.8

Vee= 4.5V, 10 H = -1.2 mA (Pins 3 & 5)
Vee =4.5V, 10 H = -1.08 mA (Pins 4 & 6)
Vg;._ = 4.5 V, !oo = -0.84 mA (Pin 7)
Vee= 5.5V, IOL = 16 mA (Pins 3 & 5)
10 L = 14.4 mA (Pins 4 & 6)
IOL = 11.2 mA (Pin 7)
Vee= 4.5 V, IOL = 12.4 mA (Pins 3 & 5)
IOL = 11.2 mA (Pins 4 & 6)
!m = 8.7 mA (Pin 7)
Guaranteed input highthreshold for all. inputs
Guaranteed input low
threshold for all il!l!.uts

IF
4 IF
IF
4 !E
IR
4 IR
tpd+
,.pd-

Input Load Current
Input Load Current
Input Load Current
Input Load Current
Input Leakage Current
Input Leakage Current
C1tOC04""'C";-fo""to4

-1.6
-6.4
-1.24
-4.96

2.4

Q.4

2.0

2.7

0.21

2.4

0.4

1.7

0.4

1.4

Volts

0.9

0.8

-1.6
-4.4 -6.4-0.97 -1.24-3.88 -4.96
15
60
60
240
35
55
-35
55

-1.6
-6.4
-1.24
-4.96
60
240

-1.1

Volts

Volts
mA

Vee=5.5V

mA

Vee= 4.5V

µA
ns
ns

VF= 0.4 v
5.5 Von other inputs

Vee = 5.5 V, VR = 4.5 v
Ground on other inputs
Vee= 5.0V
CL= 15 pf

ELECTRICAL CHARACTERISTICS (TA = 0°C to + 75°C, Vee = 5.0 V ±5%)SYMBOLCHARACTERISTICS

LIMITS
0°C
+25°C
+75°C
MIN. MAX. MIN. TYP.
MAX. MIN. MAX.

UNITSCONDITIONS

VoH

Output High Voltage

2.4

Volts

-VOL

Output Low Voltage

VIH

Input High Voltage

VIL

Input Low Voltage

0.85

IF
4 IF
IF
4 IF
IR
4 IR

Input Load Current
Input Load Current
Input Load Current
Input Load Current
Input Leakage Current
Input Leakage Current
C1to C04

-l.6
-6.4
-1.41
-5.64

Vee= 4.75 V, 10 H = -1.2 mA (Pins 3 & 5)
Ver:;= 4.75 V, 10 H = ~l.08 mA (Pins 4 & 6)
Y_cr,_ = 4.75 V, !mi_= -0.84 mA (Pin 7)
Vee= 5.25 V, IOL = 16 mA (Pins 3 & 5)
IOL = 14.4 mA (Pins 4 & 6)
10L = 11.2 mA (Pin 7)
Vee = 4.75 V, IOL = 14.1 mA (Pins 3 & 5)
IOL = 12.7 mA (Pins 4 & 6)
b. = 9.85 mA (Pin 7)
Guaranteed input highthreshold for all inputs
Guaranteed input low
threshold for all inputs
Vee= 5.25 V, VF= 0.45 v
5.25 Von other inputs
Vee= 4.75 V, VF= 0.45 V
5.25 Von other inputs
Vee= 5.25 v, VR = 4.5 v
Ground on other inputs
Vee= 5.0V
CL= 15 pf!ie.d+-Tpd-~Ti:JG 04

2.4

0.45

1.9

3.0

0.21

2.4

0.45

1.8

0.45

1.6

Volts

0.85

0.85

-1.0
-4.0
-0.9
-3.6
15
60
35

-1.6
-6.4
-1.41
-5.64
60
240
55

-1.6
-6.4
-1.41
-5.64
60
240

-go

~

5-28

Volts

Volts
mA
mA
µA
ns
ns

SH3000
HIGH IMPEDANCE, WIDEBAND DC AMPLIFIERFAIRCHILD HYBRID CIRCUITSGENERAL DESCRIPTION - The SH 3000 Hybrid consists of a pair of high-gain,

matchedPHYSICAL DIMENSIONS
T0-100(10 pin package)transistors connected as emitter-followers at the inputs of a µA 702A operational amplifier.

.370~

IF
i_c=JlFEATURES.335• 5 Mn TYPICAL INPUT IMPEDANCE.040• 0.3 JJ-A TYPICAL INPUT BIAS CURRENT• DC TO 30 MHz USEFUL BANDWIDTH
•

.335

.185

.3051

.165

,___.~ 500

LATCH-UP PROTECTED

10.019LEADS.016 DIA.

• -55°C TO +125°C TEMPERATURE RANGE

m~~~~oo .050
MAX. MIN
I.
-.230 TPABSOLUTE MAXIMUM RATINGS (Note 1)

Total Supply Voltage Between v+ and V- Terminals

21 Volts

Peak Load Current

50 mA

Input Voltage+0.5 V to -6.0 V

Differential Input Voltage± 5 Volts

Internal Power Dissipation(Note l}300 mW

Operating Temperature Range-55°C to +125°C

Storage Temperature Range-65°C to +150°C

Lead Temperature (Soldering, 60 seconds}

300°C

SCHEMATIC DIAGRAM~-------------0

10

V+

NOTES: AH dimensions in inches
Leads are gold-plated kovar

Pack8ge weight is 1.32 grams

PART NO. HAG30001XX:-55°C TO +125°C
CONNECTION DIAGRAMLAG FREQUENCYCOMPENSATION

INVERTING
INPUT

INPUT
VNote: Pin 5 connected to case.

CONNECTION DIAGRAM(TOP VIEW)NOTE 1: Rating applies for case temperatures to +125°C; derate linearity at 5.6mW/°C for ambient temperatures above +125°C.

F=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-29

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATION[FAIRCHILD LINEAR INTEGRATED CIRCUITS SH3000

ELECTRICAL CHARACTERISTICS (TA = +25°C, v+ = 12 v, v

-6.0 V, RE 1 = RE 2 = 200 k unless otherwise noted)

Conditions

Parameter
Input Offset Voltage

Min.

Typ.

Max.

Units

2.0

6.0

mV
nA

RS S20 k

Input Offset Current

35

100

Input Bias Current

300

750

Input Resistance

1.0

Input Voltage Range-3.5

Common Mode Rejection Ratio

RS S 20 k, f _'.S 1 kHz

Voltage Gain
Output Voltage Swing

RL? 100 k

nA

mn

5.0

v

0

70

80

1400

2600

±5.0

±5.3

Supply Voltage Rejection Ratio

75

Power Consumption

70

dB

v
µV/V
120

mW

7.5

mV

The following Specifications apply for -55°C < +125°C:
Input Offset Voltage

RS< 20 kVoltage Gain

1000

Input Offset Current
Input Offset Current
Input Bias CurrentTA+125°C

100

nA

TA

-55°C

200

nA

TA

-55°C

1.0

Average Temperature Coefficientof Input Offset Voltage

µA

7.5

µV/°C

TYPICAL PERFORMANCE CURVESINPUT BIAS CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

INPUT OFFSET CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

INPUT RESISTANCEAS A FUNCTION OF
AMBIENT TEMPERATURE
100~~--~~~---~

1y+ • +12V_i,v-., -6.oyv+ • +12V

0, 8 >--t---+--+--+---+---41REI ~ REz • 200 k ---l

0.6 ~

60

-~
0.4 f-+-+"..!-~--t-f--+-+--+--+--j

1--+-~.,-+--+--+---+---+--+--+--t--<.

~i.o r-+--+V__.,..,.V__,.~1--+-+-·+--+---<
r--+-t-·-t--+--+--+--+--il--t---io~+---+--+--+---+--+---+--+--+--i

-60

-20

+20
-t60
TEMPERA fURE - °C

•IOC

+140

o'---'---'--"---'----"--'--"---'---'--'
-60
-20
+20
+60
•100

TfMPERATUREFREQUENCY RESPONSE
FOR VARIOUS CLOSED-LOOP
GAINS

T

°C

FREQUENCY COMPENSATIONCIRCUIT

+140

10L
-6()

-2n

+20
t60
TEMPERATURE - °C

+100

H40

VOLTAGE TRANSFER
CHARACTERISTIC

-6V

10

1.0
FREQUENCY-6.0 .__...__,__...__.__..___.___.___,__....__,-5.0 -4.0 -3.0 -2.0 -1.0 0 1.0 2.0 3.0 4.0 5.0
INPUT VOLTAGE - mv

MHz

5-30

SH 3001
ANALOGSWITCHFAIRCHILD HYBRID CIRCUITS• INPUTS CCSL COMPATIBLE• mW MICROLOGIC AND MICROLOGIC COMPATIBLE INPUTS• LOW FEED THROUGH SPIKES ON THE OUTPUT• TYPICAL t 0 " - - 145 ns LOADED• APPLICATIONS- - SCANNING, MULTIPLEXING, A/D CONVERSION,
4-POLE ST NORMALLY OPEN RELAY OR CHOPPERPHYSICAL DIMENSIONS
TO·IOO(10 pin package)
.335
.335
.185
.37031/f
j.3051
.165

IF
1W

.040

L

J_
I

MAX.

ABSOLUTE MAXIMUM RATINGS

Maximum Temperatures

Storage Temperature-65°C to +150°C

Operating Temperature-55°C to +125°C

10.019LEADS.016DIA.

!ill~~~~oo

---i-

f

500
.040
MAX. MIN .

I

Maximum Power Dissipation

at 25°C Case

500 mWat 25°C Ambient

350 mW

Maximum Voltages and Current

v.m

±10 v

(Pins 1, 2, 8 & 9)

NOTES: All dimensions in inches
LP.ads are gold-plated kovar±10 v

vout (Pins 3 & 7)v+
(Pin 10)

+11 v

v-

-22 v

(Pin 6)

Package weisht is I.02 grams

PART NO. HAG 30011 XX

100 mA

1in' 1out
V switch (Pin 4)

±6V

Y+
0

..-----~--1 3

t---------1,__,.-------1 l

lOk

Your
YIN

- - - - - - 4 9 YIN'---------<7 YourElectrical Characteristics on page 2

l=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-31

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD HYBRID CIRCUITS SH 3001
ELECTRICAL CHARACTERISTICS (TA= 25°C, v+

Symbol= 10 v, v - = -20 V Unless Otherwise Specified)

Characteristic

1SWH
VSWL

Min. Typ. Max. Units

Test Conditions

High Switch Drive Current (On)

o. 4

mA

Low Switch Drive Voltage (Off)

o. 6

v

o. 5

v

TA "' -55°C to +125°C
TA= 25°C
TA• -55°C, +125°C

2000Isw = o.4 mA,

VSWL

Low Switch Drive Voltage (Off)RON/channel

Channel On Resistance120

Iin = 1. 0 mA

vout = o.o v
1oFF
10FF

Channel Off Leakage Current

1.0

nA

Channel Off Leakage Current

1.0

µA

vsw = o. 5 v,

TA= +125°C

VIN
-16

Analog Peak Signal Input±10v

TA= -55°C to +125°C

Negative Supply Current

4,4

mA

IIN = O,
ISW = 0,4 mA,

CIN/channel
COUT
ton+
t on -

Channel Input Capacitance

3. 5

pF

vsw = o.o v

VIN•O,OV

Channel Output Capacitance
Switch Turn-On Time

5,0
145

pF
ns

vsw = o.o v
VOUT "'0,0 V
See Figures 1 & 2

Switch Turn-On Time

230

280

ns

See Figures 1 & 3

toff+

Switch Turn-Off Time

580

600

ns

See Figures 1 & 2

tofC

Switch Turn-Off Time

270

300

ns

See Figures 1 & 3

6,0

180

vsw = o.6V

TA= -55°C to +125°C

TYPICAL ELECTRICAL CHARACTERISTICS+lOV

CHANNEL "ON" RESISTANCEVERSUS TEMPERATURE_o->,.--_.,....---o +5 VOLTS OR -5 VOLTS

o-i--....--.-o OUTPUT

2.0 .---.----.-l-.--l_..,v-·-10,.v·-.---.----._,TO SCOPE
6.Bka=f=!===l==!

6
1.0 l-~~Jl\IN~OR~OU~Tl\!M:!:IN-F

TO SCOPE

I.>--~

C =lOpF(including strayand scope probe
capacitance)

FIGURE 1

-25

25

75

c 1 ~~1

125

TA-AMBIENT TEMPERATURE-'C

PULSE INPUT

50%

tr= If= 25ns±20%50%41on.~•l-----+-......- - 90%

CHANNEL OUTPUT

CHANNEL "ON" RESISTANCEVERSUS V (IN OR OUT) MIN
MINUS V&

ov

2.0

c;

I

.

!!I
z

FIGURE 2

1.0
0.5

t;;

~

I ---1- µs!
PULSE INPUT _ _ )503

CHANNEL OUTPUT
0.01 '---'---'----'---'-__,_-'--'-__.._-'------'
10
14
18
22
26
30

~on~

~lolf1'------"~.

FIGURE 3

5-32

tr= If= 25nso±20%

T

503\

90~
\,..

Y(IN OR OUTIMIN-V6 VOLTS±10%~1-o-v5v

SH3002
SPOT ANALOG SWITCHFAIRCHILD HYBRID CIRCUITS• INPUTS CCSL COMPATIBLE• MW MICROLOGIC® AND MICROLOGIC® COMPATIBLE INPUTS• LOW FEED THROUGH SPIKES ON THE OUTPUT• TYPICAL ton - 120 ns• APPLICATIONS: SERIES SHUNT CHOPPERS, AID CONVERSION SINGLE POLE DT RELAYS,
MULTIPLEXING OR SCANNING

PHYSICAL DIMENSIONS(in accordance with JEDEC T0-100)i..-...----1-:m.335-------11.305

ABSOLUTE MAXIMUM RATINGS
Maximum Temperatures
Storage Tempera~ure
Operating Temperature

10 LEADS-65°C to +150°C-55°C to +125°C:mo1A.

Maximum Power Dissipation
at 25°C Caseat 25°C Ambient

500mW
350mW

Maximum Voltages and Current
V;n (Pins 1, 2, 8 &9)
Vout (Pins 3 & 7)
y+ (Pin 10)
v- (Pin 6)-22V

lin• lout
Vswitch (Pin 4)

100 mA
±6V

±lOV
±lOV

+uv

NOTES:All dimensions in inches
Leads are gold-plated Kovar
Package weight is 1.02 grams
PART NO. HAG30021XX

v+ Q11---..----.------------------.

GND 5i---~15k

FIG.1.

l=AIRCHILCl
SEMICDNDUCTD R
1

313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-33

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD HYBRID CIRCUITS SH3002
ELECTRICAL CHARACTERISTICS (TA = 25°C, v+ = 10 V, v- = -20 V unless otherwise specified)
SYMBOLCHARACTERISTICS

MIN.

VswH
VswH
VswL
VswL
RoN/ charmelHigh Switch Drive Voltage
High Switch Drive Voltage
Low Switch Drive Voltage
Low Switch Drive Voltage
Channel "ON" Resistance

2.5
2.6

IOFF
IOFF
VIN
I 10
C1N/CHWL
Cour
ton+
toff+
tontofftoff+ton+
toffton-Channel "OFF" Leakage Current
Channel "OFF" Leakage Current
Analog Peak Signal Input
Positive Supply Current
Channel Input Capacitance
Channel Output Capacitance
Switch Turn-on Time (Pin 9)
Switch Turn-offTime (Pin 7)
Switch Turn-on Time (Pin 9)
Switch Turn-offTime (Pin 7)
Switch Turn-off Time (Pin 9)
Switch Turn-on Time (Pin 7)
Switch Turn-off Time (Pin 9)
Switch Turn-on Time (Pin 7)

TYP.

140

MAX.

0.8
1.1
200
1.0
1.0
±10
8.0

3.5
5.0
120
430
130
300
1.6
1.35
1.5
1.6

TYPICAL ELECTRICAL CHARACTERISTICS

150
500
160
340
1.9
2.0
1.7
2.5

UNITS

v
v
v
v
f!

nA
µ.A

v
mA
pf
pf
ns
ns
ns
ns
µ.s
µ.s

µ.s
µ.s

TEST CONDITIONS
TA= 25°c, TA= 125°c
TA= -55°C
TA= 125°c
TA= -55°c, TA= 25°c
lcommon = 1.0 mA
V7 orV9 = O.OV
TA= 25°C
TA= 125°c
lcHNL = o, TA= -55°C to +125°C
VswH = 4.0 v, TA= -55°C to +125°c
Channel Off, V7 orV9 = 0.0 V
Channel Off, V7 orV9 = 0.0 V
See Figures 2 and 3
See Figures 2 and 3
See Figures 2 and 4
See Figures 2 and 4
See Figures 2 and 3
See Figures 2 and 3
See Figures 2 and 4
See Figures 2 and 4

SWITCHING TEST CIRCUIT+lOVCHANNEL "ON" RESISTANCEVERSUS TEMPERATURE
2.0.L J J_vl1ov

Cl

1.0 t--1 V(70RBOR9)MIN

i
iij

0.5

6

~

;
~
~

15V

2ov
30V

0.1

Fig. 2.

i 0.05"~Pi

O.Ol75 -50 -25

0

25

50

75

i--1111 t 10% -'---1~-;,-:tf~3V~~.25 ±5ns

100 125__ ·- 6

TA-AMBIENT TEMPERATURE-'C

CHANNEL~!-~toll"'-! 10%
OV OVOUTPUT
I90%
PIN 9

-5V

CHANNEL "ON" RESISTANCEVERSUS Y11 ., a., •l MIN MINUS Y,

11

0.0 5 l~O--'--1~4-'---'-1B--'--'2-2~-2'-6-'---'30
v(7 OR 8 OR 9)MIN-

v,-voLTS

Fig. 3.

5-34

Fig. 4.

SH3005
HIGH IMPEDANCE DIFFERENTIAL COMPARATORFAIRCHILD HYBRID CIRCUITS- The SH 3005 consists of a pair of high current gain, matched

GENERAL DESCRIPTION

transistors connected as emitter followers at the inputs of a µ.A 710 comparator.

PHYSICAL DIMENSIONS(T0-99)FEATURES• 2 MO INPUT IMPEDANCE• 0.8 iJ'A INPUT BIAS CURRENT• -55°C TO +125°C TEMPERATURE RANGEAPPLICATIONS• Variable Threshold Schmitt Trigger• Pulse Height Discriminator• High Noise Immunity Line Receiver• Memory Sense Amplifier
ABSOLUTE MAXIMUM RATINGS (Note 1)

Positive Supply Voltage+14.0 Volts

Negative Supply Voltage-7.0 Volts

Peak Output Current

10 mA

Differential Input Voltage± 5.0 Volts

Input Voltage± 7.0 Volts.20DTP....

Internal Power Dissipation
T0-5

.121

300 mW(Note 1)200 mW

Flat Package (Note 2)

NOTES D1mensoonsasperl1IHIJ·IOcomm1ttee

Qperating Temperature Range-55°C to +125°C

Storage Temperature Range-65°C to +150°C

Lead Temperature (Soldering, 60 seconds)

300°C

SCHEMATIC DIAGRAM

..

2.8k

.,

Alld1mens1ons1n1nehes
Leadsaregoldpiatedkovar
Packagewe1ght1s1.221rams

PART NO. HXK30051XX: -55°C TO +125°C
PART NO. HXK30059XX: 0°C TO :+ 70°C

PHYSICAL DIMENSIONS

3.9k

TYPICAL FLAT PACKAGETOP VIEWNON-INVERT INC
INPUT

JN~:rui"co---~-!"

f-.1875-+- 265MAX-+.1875--l

PART NO. HBG30051XX: -55°C TO +125°C
PART NO. HBG30059XX: 0°C TO +70°C

Notes on page 2
Electrical Characteristics on page 2

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-35

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD HYBRID CIRCUIT SH3005

ELECTRICAL CHARACTERISTICS (TA

25°C, v+

12.0 V, v- = -6.0 V Unless Otherwise Specified)Parameter (see definitions)Min.

Conditions

Input Offset Voltage

vout

Input Offset Current

vout+1.4 V, RS~ 20k+1.4 v

Max.

Units

7.0

mV

0.3

0.4

µA

0.8

2.0

µA

±5.0

v

±5.0

v
v

Input Bias Current
750

Voltage Gain

Typ.

Output Resistance

1500
200

~7.0

Input Voltage Rangev

Differential Input Voltage Range
Positive Output Level

Vin > 15 mV, 0 ~ 10 ~ 0.5 mA

Negative Output Level
Output Sink Current
Positive Supply Current

vout ~ 0

+2.5

+3.2

+4.0

Vin > 15 mV

-1.0

-0.5

0

Vin > 15 mV, Vout > 0

1.6

2.5

mA

6.4

mA

5.5

mA

Negative Supply CurrentvPower Consumption
T0-5 Package

110

175

mW

The following specifications apply for -55°C ~ TA < +125°C:
Input Offset Voltage(Note 4)8.5

mV

Input Offset Current(Note 4)1.0

µA

Input Bias Current

5.0

Temperature Coefficient of Input
Offset Voltage(Note 4)
Voltage Gain

µA

µV/°C

7.0
500

NOTES:(1) Rating applies for case temperatures to +125°C; derate linearly at 5.6 mW/°C for ambient t£mperature above +105°C.
(2) Derate linearly at 4.4 mW/°C for case temperatures above +115°C; derate linearly at 3.3 mW/°C for ambient temperatures above +100°C.
(3) The res11onse time specified (see deflnttlons) is for a 100-mV Input step with 5-mV overdrive.
(4) The input offset voltage (see definitions) Is specified for a logic threshold voltage of 1.8 Vat -55°C, 1.4 Vat +25°C and 1.0 Vat +12?°C.

T0-5 CONNECTION DIAGRAMFLAT PACKAGE CONNECTION DIAGRAM(TOP VIEW)(TOP VIEW)y+

GND
NON INVERTING
INPUT

y.

Note:

Pin 4 connected to case

5-36

,.

10

N.C.
N.C.

INVERTING
INPUT

Y+

N.C.

N.C.

y.

OUTPUT

FAIRCHILD HYBRID CIRCUIT SH3005

TYPICAL PERFORMANCE CURVESVOLTAGE GAIN
AS AFUNCTION OF
AMBIENT TEMPERATURE

VOLTAGE TRANSFER
CHARACTERISTIC!~-------~~.~

4.0

3.0 I - -1--1--1---1-----+---l--+-----+-V+ • +12V _27~

V+•~l2Vv-. -6.0V

V· • -6.0V

~ l==

·55'C

7L~·c

2.0

1.0

-1.~4.0

i

E2'

-1

I--t--'hw

INPUTVOlTAGE- mv

700L-..L-..J--l--l--1--1---l----1----1---'
-60
-20
+20
+60
+100
+140
TEMPERATURE - 'C

RESPONSE TIME FOR
VARIOUS INPUT OVERDRIVESRESPONSE TIME FOR
VARIOUS INPUT OVERDRIVES-3.0 -2.0 -1.0

0

1.0

2.0

3.0

4.0

4.0
3.0

co:

2.0

Jr~~ ~~v

20mv-- ~ 5mV

1.0

~~

·1.0

-1.0 t-+--l-+-+--l-+-l---l-+-1---1-+-+--l

!;
~

100

<

g 50
~

INPUT BIAS CURRENT
AS AFUNCTION OF
AMBIENT TEMPERATURECOMMON MODE
PULSE RESPONSE
V+:~l2V

3.0

0o.s----------v•*+l2Vv· • -6.ov'r:5°~

POWER CONSUMPTIONAS HUNCTION OF
AMBIENT TEMPERATURE
120-.--.-~~~~~~~

V+*+l2Vl--.f--1--1--1---l--I----+ V}•

V· • ·6V+12~

V- • ·6.0V -V· • -6.0V

2.011-.V::t=t=t=PwTA • '2s'c+-1.011----+-+--+--+--+--+--+--+--1---<

1-T-

".

v,,. -+-+t-+t-+- '" +--+--+--+--+--+--!----!
50 Q· SH!:S~~

2.0t--+- "::' +--+--+--+--+--+--!----<

~

1.0

~~

s~

o
~~+--+--+--+--+--+--+--~

40

80
TIME- ns120

160

O'-'-+--'---''---''---''---'--'--'---"

1~601...-'---20.l...-.l...-+20J,--L......,+60'--L,...JIOOL..-L+...JJ40

TEMPERATURE - 'C

TEMPERATURE - 'C

-60

-20

+20

+60

5-37

+100

+140

FAIRCHILD HYBRID CIRCUIT SH3005
DEFINITIONSLOGIC THRESHOLD VOLTAGE - The approximate voltage at the output of the comparator at which the loading logic circuitry changes
its digital state.
INPUT OFFSET VOLTAGE* - The voltage between the input terminals when the output is at the logic threshold voltage. The input
offset voltage may also be defined for the case where two equal resistances are inserted in series with the input leads.
INPUT OFFSET CURRENT* - The difference in the currents into the two input terminals with the output at the logic threshold voltage.
INPUT BIAS CURRENT* - The average of the two input currents.
INPUT VOLTAGE RANGE* - The range of voltage on the input terminals for which the comparator will operate within, specifications.
DIFFERENTIAL INPUT VOLTAGE RANGE* -The range of voltage between the input terminals for which operation within specifications
is assured.
VOLTAGE GAIN* - The ratio of the change in output voltage to the change in voltage between the input terminals producing it with
the DC output level in the vicinity of the logic threshold voltage.
RESPONSE TIME* - The interval between the application of an input step function and the time when the output crosses the logic
threshold voltage.

The input step drives the comparator from some initial, saturated input voltage to an input level just barely inexcess of that required to bring the output from saturation to the logic threshold voltage. This excess is referred to as the voltage
overdrive.
POSITIVE OUTPUT LEVEL* - The DC output voltage in the positive direction with the input voltage equal to or greater than aminimum specified amount.
NEGATIVE OUTPUT LEVEL* - The DC output voltage in the negative direction with the input voltage equal to or greater than aminimum specified amount.
OUTPUT SINK CURRENT - The maximum negative current that can be delivered by the comparator.
PEAK OUTPUT CURRENT - The maximum current that may flow into the output load without causing damage to the comparator.
OUTPUT RESISTANCE* - The resistance seen looking into the output terminal with the DC output level at the logic threshold voltage.
POWER CONSUMPTION - The DC power into the amplifier with no output load.
specified as a maximum for the entire range of input-signal conditions.

5-38

The DC power will vary with signal level, but isSH3200
ADJUSTABLE POSITIVE DC VOLTAGE REGULATORFAIRCHILD HYBRID CIRCUIT• SHORT CIRCUIT PROTECTED• BROAD RANGE OF OUTPUT VOLTAGES ••• 8.5 V TO 30 V
• LOAD CURRENTS 0 TO 50 mA AND 5.0 AMPS USING AN EXTERNAL PASS TRANSISTOR• EXCELLENT REGULATION: LINE REGULATION ••• 0.005%/Y MAX.
LOAD REGULATION ••• 0.05% MAX.
• APPLICATIONS: SERIES REGULATOR FOR POSITIVE DC POWER SUPPLIES, DIGITALAND ANALOG INTEGRATED CIRCUITS• A COMPLEMENT SH3201 OF THIS REGULATOR IS ALSO AVAILABLE FOR NEGATIVEVOLTAGE REGULATIONPHYSICAL DIMENSIONS

.185
.165

.5DDMIN.

&Leeds.019.016

ABSOLUTE MAXIMUM RATINGS
Maximum Temperatures
Storage Temperature
Operating Temperature-65°C to +1so 0 c-55°Cto +12s 0 c
45' TP

Maximum Power Dissipation
at 25°C Ambient Temperature (Note 1)
at -55°C to +125°C Case Temperature
Maximum Voltages and Current
Input Voltage
Output Voltage (Note 2)
Input-Output Voltage Differential
Output Current (Note 3)

.034

780mW
l.OW

.028

?<'~

NOTES:
Dimensions as per latest J-10 committee
All dimensions in inches
Leads are gold-plated.Kovar
Package weight is0-9Sgrams

+35V
+28V
+28V
50mA

PART NO. HXK32001XX

SCHEMATIC DIAGRAM
EXTERNAL SHORT CIRCUITCURRENT SET RESISTOR(Do----.----~~----

!@

@

VouT

~--~>--->.,,..,•.,--------------------,

V1N

I

I

t EXTERNAL OUTPUT

I
I

I
I
I

I
I

i VOLTAGERESISTORADJUST
::

lI

1

SEE NOTE 4@

O'.

LOAD

!MAY BE REMOTE)@

CD o----------.~J--------------0 VsAMPLE

1

NOISE SUPPRESSION

:
I
I
I

GND

FIGURE 1

@

<D

.

I
I
I
I

------------------------------------i
LOW OR GROUND END
j_.
OF REMOTE SENSING-=

FAIRCHILCSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011, TWX: 910-379-6435

5-39

A DIVISION OF FAIRCfill,D CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD HYBRID CIRCUIT SH3200

ELECTRICAL CHARACTERISTICS (25°C Free Air Temperature unless otherwise noted)
SYMBOLCHARACTERISTICS

MIN.

VIN

Input Voltage Range

Your

Output Voltage Range (Note 2)

12.5
8.5

TYP.

IV1wYourl
IL

Input-Output Voltage Differential
Load Current (Note 3)

4.0
0

V(NOISE)

Uncompensated Output Noise Voltage

30

50
150

Volts
mA
mVp.p.

V(NOISE)

Compensated Output Noise Voltage

3.0

5.0

mVp.p.

8.5 V IYouTI 30 V
0
IL
50 mA
C ~ 0.4 µF, Pin 7 to Pin 8
8.5 V IYourl 30 V
0 SIL S 50 mA

.002

.005

%/V

35V >IViNl>IYourl +4.0V

.02

.05.

%

IV1NJ>IYourl +4.0V

Temperature Stability
TA= -55°Cto +125°C

.01

%/"C

At Package Dissipation
780mW

Power Dissipation Stability

.002

%/mW

4.0 V IV1N - Your I
0
IL
50mA

AV1N
l<AVour1Your>%IL! Line Regulation
Load Regulation (IL = 0 to 50 mA)

I(AYour!Vour>%AT(AYour/Your>%Po

TYPICAL REGULATED OUTPUT
VOLTAGE ADJUSTMENT.
0>....!. 25~ 20....> 15

v

:>

~

0

5 v
0

10

v

y

1

TEST CONDITIONS
35V>IV1Nl>IVourl +4.0V

s
s s

s

s

s

s

s
s s

s 28 V

\

50

I\

_l

I

~ 40

~ 30

~

·O

I/

3

~

~ 20

k"'

;::
:ii

:;

; 5.0

0

v
L

Volts
Volts

TYPICAL SHORT CIRCUIT PROTECTION
SETTING CURRENT

60

35!::; 30

UNITS

35
30
28

l<AVour/You1>%J

!

MAX.

"'

10

~

H

(Pin I Gr•dodl
0

0

20

40

60

80

0

100

~

w

~

~

~

00

EXTERNAL RESISTOR, PIN 3 TO PIN 4-0

EXTERNAL SENSE RESISTOR, PIN 2 TO PIN 3 -ko

FIGURE 3

FIGURE 2
MAXIMUM POWER DISSIPATIONVERSUS AMBIENT. TEMPERATURE
1000

"1-..

800

N

""'

N
~

200

I DERAii NG FACTOR 2.8mW/°C I
0
-55

125

25

IA - AMBIENT lEMPERAlURE - °C

FIGURE 4
NOTES:(1) Derating factor as shown in Fig. 4 is 2.8 mW/"C.
(2) Selection of Output Voltages: By exiernally connecting a preselected sense resistor (see figure 2) between pin 2 and pin 3 any desired output voltage in the range of 8.5 V
to 30 V is achieved.
(3) Selection of Short Circuit Current: The maximum limit on the internal short circuit protection at any current from l to 50 mA can be set by externally connecting a pre·selected resistor (see figure 3) between pin 3 and pin 4.
(4) This pin is made available for connections to compensating networks which can be used to alter the dynamic response of the regulator to meet unusual load requirements.
No connection is· necessary for normal operation.

5-40

SH3201
ADJUSTABLE NEGATIVE DC VOLTAGE REGULAT.OR
FAIRCHILD HYBRID CIRCUIT• SHORT CIRCUIT PROTECTED• BROAD RANGE OF OUTPUT VOLTAGES • • • -8.5 V TO -30 V• LOAD CURRENTS 0 TO 50 mA AND 5.0 AMPS USING AN EXTERNAL PASS TRANSISTOR• EXCELLENT REGULATION: LINE REGULATION ••• 0.005%/V MAX.
LOAD REGULATION ••• 0.05% MAX.
• APPLICATIONS: SERIES REGULATOR FOR NEGATIVE DC POWER SUPPLIES, DIGITALAND ANALOG INTEGRATED CIRCUITS• A COMPLEMENT SH3200 OF THIS REGULATOR IS ALSO AVAILABLE FOR POSITIVEVOLTAGE REGULATIONPHYSICAL DIMENSIONS
in accordance withJEDEC (T0-99) outline

.185
.165

8 Leads.500 MIN.

.019
.016

ABSOLUTE MAXIMUM RATINGS
Maximum Temperatures
Storage Temperature
Operating Temperature-65°C to + 1so 0 c-55°C to +125°C

Maximum Power Dissipation
at 25°C Free Air Temperature (Note 1)
at -55°C to +l25°C Case Temperature
Maximum Voltages and Current
Input Voltage
Output Voltage (Note 2)
Input-Output Voltage Differential
Output Current (Note 3)

780 mW
1.0 w
NOTES:
Dimensions as per latest J-10 committee
All dimensions in inches
Leads are gold-plated Kovar
Package weight is 0.95 grams

-35V
-28V
28V
50mA

PART NO. HXK32011XX

SCHEMATIC DIAGRAM

EXTERNAL SHORT CIRCUITCURRENT SET RESISTOR@---------

©

/®

YouT

,----•-->•'\,"r---------o-- - - -,

Y1N

I

I

:

I

•• ADJUST RESISTORI~EXTERNAL YOLTAGd

1IMAY BE REMOTEIO:LOAD~-----------01(!)
YSAMPLE<D-----...

I
I
I

NOISE SUPRESSIDN

I
I@;N;------------------Q)-------1

LOW OR GND END
OF REMOTE SENSING-=-FIGURE 1

FAIRCHILCJSEMICDNDUCTD'R
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-41

A DIVISION OF FAIRCHILD C~MERA AND INSTRUMENT CORPORATIONFAIRCHILD HYBRID CIRCUIT SH3201

ELECTRICAL CHARACTERISTICS (25°C Free Air Temperature unless otherwise noted)
TYP.

MAX.

UNITS

30

-35
-30
28
50
150

Volts
Volts
Volts
mA
mVp.p.

3.0

5.0

mVp.p.

8.5 Vs IYourl s 30 V
0 SIL S 50 mA
C ~ 0.4 ,uF, Pin 1 to Pin 8
8.5 Vs IVourl s 30 V
0 SIL S 50 mA! Line Regulation

.002

.005

%/V

35V>IV1Ni>IYourl +4.0V

I Load Regulation (IL = 0 to 50 mA)l<~Vour/Your>%J
Stability
I . ~T l Temperature
TA= -55°cto +12s c

.02

.05

%

IV1Nl>IVourl +4.0V

.01

%!°C

At Package Power Dissipations 780mW

.002

%/mW

4.0 V S IV1N" Your I S 28 V
0 SIL S 50 mA

SYMBOLCHARACTERISTICS

MIN.

VIN

-12.5
-8.5
4.0
0

V(NOISE)

Input Voltage Range
Output Voltage Range (Note 2)
Input-Output Voltage Differential
Load Current (Note 3)
Uncompensated Output Noise Voltage

V(NOISE)

Compensated Output Noise Voltage

Your
IV1N.YourlIL

l<~VourfYour>%J

!

~VIN

l<~VourfYour>%J

!

IL

Po

35V>IV1Nl>IVourl +4.0V

0l<~Vour!Your>%J

I

TEST CONDITIONSPower Dissipation Stabilityl

TYPICAL SHORT CIRCUIT PROTECTION
smlNG CURRENTTYPICAL REGULATED OUTPUT
VOLTAGE ADJUSTMENTi
I

55,..-,.--.,-..,......,._.,.-..,--,---.--.---.

-+--+--+--+-+-<f---+--+-~

50 ........

•~20

i
:

i

60

H

15

10V

/

v

y-r
~

50

k'.'.'.
40

~
~

30

~

20

""" t--..

10

5.0 t--+---i-+-+-+--+--+--+--+---1

II!
20

40

60

80

0o

100

10

20

50

40

50

EXTERNAL SENSE RESISTOR, PIN 5 TO PIN 6-kll

EXTERNAL RESISTOR, PIN 4 TO PIN 5 -R

FIGURE 2

FIGURE 3

60

MAXIMUM POWER DISSIPATIONVERSUS AMBIENT TEMPERATURE

lllllll ..........,

I"-

800

['....

"""........

I'-...

200
I DERAllNG FACTOR 2.BmW/'C I
0................

·SS

25

125

TA • AMBIENT TEMPERATURE - 'C

FIGURE 4
NOTES:(1) Derating factor as shown in Fig. 4 is 2.8 mW/°C.
(2) Selection of Output Voltages: By externally connecting a preselected sense -resistor (see figure 2) between pin 5 and pin 6 any desired output voltage in the range of 8.5 V
to 30 V is achieved.
(3) Selection of Short Circuit Current: The maximum limit on the internal short circuit protection at any current from I to 50 mA can be set by externally connecting a preselected resistor (see figure 3) between pin 4 and pin 5.
(4) This pin is made available for connections to compensating networks which can be used to alter the dynamic response of the regulator to meet unusual load requirements.
No connection is necessary for normal operation.
0

5-42

SH3741
DUAL HIGH GAIN OPERATIONAL AMPLIFIERA FAIRCHILD HYBRID DESIGN SPECIFICATION CIRCUIT

GENERAL DESCRIPTION - The SH3741 is a dual high performance operational amplifier constructed using the
Fairchild Planar* epitaxial process. It is intended for a wide range of analog applications. High common mode
voltage range and absence of "latch-up" tendencies make the SH3741 ideal for use as a voltage follower. The
high gain and wide range of operating voltages provide superior performance in integrator, summing amplifier
and general feedback applications. The SH3741 is short-circuit protected, is similar to the popular µA709
operational amplifier, but requires no external components for frequency compensation. The internal GdB/
octave roll-off insures stability in closed loop applications.

PHYSICAL DIMENSIONSCERAMIC DUAL IN-LINE

FEATURES• NO FREQUENCY COMPENSATION REQUIRED• SHORT-CIRCUIT PROTECTION• OFFSET VOLTAGE NULL CAPABILITY• LARGE COMMON-MODE AND DIFFERENTIAL VOLTAG~ RANGES• LOW POWER CONSUMPTION• NO LATCH UP

1i1&:
.011
.009

~· .350 ··~-I

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
CERAMIC DIP
Supply Voltage±22V
Internal Power Dissipation, TA = 25°C
780mW
Differential Input Voltage±30V
Input Voltage (Note 1)±15V
Storage Temperature Range-65°C to +150°C
Operating Temperature Range-55°C to +125°C
Lead Temperature (Soldering, 60 second)
300°C
Output Short-Circuit Duration (Note 2)
Indefinite

ORDER PART NO. H6K37411XX

PLASTIC DIP±18V
GOO mW±30V±15V-65°C to +iso•c
0°c to +70°c
300°C
Indefinite

PHYSICAL DIMENSIONSPLASTIC DUAL IN-LINE

1-I

'''"
I~~.

.J
.I

.125
115

__ I
.l__~g3;

c JL ~ J1no08~

SCHEMATIC DIAGRAM(EACH AMPLIFIER).150MIN.I

.023
.015

110

+8M

.090

ORDER PART NO. H6Q37419XXPIN CONFIGURATIONNOTES:(1) For supply voltages less than ± 15 V, the absolute maximum input voltage is equal to the supply voltage.
(2) Short circuit may be to ground or either supply.

*Planar is a patented Fairchild process.

l=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-43

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD HYBRID SH3741
ELECTRICAL CHARACTERISTICS (Vs= ±15 V, TA= 25°C unless otherwise specified) (EACH SIDE)
PARAMETERCONDITIONS

Input Offset Voltage
In put Offset Current
In put Bias Current
In put Resistance
Large-Signal Voltage Gain
Output Voltage Swing
Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Power Consumption
Transient Response (unity gain)

H6K37411XX
TYP.
MAX.

MIN.

Rs S 10 kO

300
50,000
±11
±9.0
±11
80

RL:?::: 2 kn, Your= ±lOV
RL ~ 10 kn
RL ~ 2 kn
Rs
Rs

2.0
35
0.15
800
200,000
±13
±12
±12
100
30
50

s 10 kns 10 kn

MIN.

7.0
375
1.0
300
20,000
±11
±9.0
±11
80
150
100

H6Q37419XX
TYP.
MAX.
3.0
35
0.15
800
100,000
±13
±12
±12
100
30
50

UNITS

8.0
375
1.0

mV
nA
µA
kn

v
v
v
dB

µV/V

150
100

mW

V1N = 20 mV, RL = 2 kn,
CL S 100 pF

Risetime
OvershootSlew Rate (unity gain)

0.3
5.0
0.5

s
s

V/µs

8.5
950
3.0

mV
nA
µA

25,000±10v

s

The following specifications apply for 0°C
TA+70°C:
Input Offset Voltage
Rs
10 kn
In put Offset Current
Input Bias Current
Large-Signal Voltage Gain
RL ;?::: 2 kn, Your = ± 10 V
Output Voltage Swing
RL;?::: 2 kn

s

µS

%

s

The following specifications apply for -55°C
TA+125°C:
Input Offset Voltage
Rs
10 kn
In put Offset Current
Input Bias Current
Large-Signal Voltage Gain
RL;?::: 2 kn, Your= ±lOV
Output Voltage Swing
RL;?::: 2 kn

s

0.3
5.0
0.5

9.5
475
1.5

mV
nA
µA

15,000±10v

TYPICAL PERFORMANCE CURVESOPEN LOOPVOLTAGE GAIN

OPEN LOOPFREQUENCY RESPONSE

TRANSi ENT RESPONSE

120

28

TA•25°C

24

100

bJ

80

20

~

'E

LS:

so~~~~~~~~~~

024

6

8~1214161820-20

SLPPLY VOlTAGE i!VI

J

~

~

JO

100

lk

!Ok

1001<

lM

1

lOM

-·-o.so.s

1.0
TINE - µs

TRANSIENT RESPONSETEST CIRCUIT

5-44

A'25°CR1•2kQCL IOOpF

RISE

FREQIENCY • Hz

VOLTAGE OFFSETNULL CIRCUIT

v5·!1sv_

7!iTI
t---1

~

l

t

!5 12

G

20

91J•7

16

1.5

2.0

2.5

SH6400•SH640l•SH6402
PNP QUAD CORE DRIVERS
FAIRCHILD HYBRID CIRCUITSFEATURESPHYSICAL DIMENSIONS• HIGH VOLTAGE ••••••• UP TO 50 VOLT LVcEo• HIGH CURRENT • • • • • • • UP TO 1.0 AMP• FAST SWITCHING • • • • • • 25 ns (TYP) ton
65 ns (TYP) t 011• COMPACT PACKAGING • • • 4 TRANSISTORS PER PACKAGE
ABSOLUTE MAXIMUM RATINGS (Note 1)
Maximum Temperature
Storage Temperature
Operating Temperature
Operating Junction Temperature
Lead Temperature (Soldering, 60 second time limit)
Maximum Power Dissipation (Notes 2 & 3)
25°C Case Temperature
25°C Ambient Temperature

FLAT PAKFLAT PACK &CERAMIC DIP-65°C to +200°C-55°C to +125°C+200°C+300°cPLASTIC DIP-65°C to +150°C
0°Cto +70°C+150°C+300°cFLAT PACK CERAMIC DIP PLASTIC DIP
1.2 Watts
1.5 Watts
1.5 Watts
0.5 Watt
0.8Watt
0.6 Watt

CERAMIC DIPORDER INFORMATION
Specify HBHXXXXlXX, 9XX for 14-pin Flat Pak
H6A*XXXX1XX, 9XX for 14-pin Ceramic DIP
H6E*XXXX9XX for 14-pin Plastic DIP
Where first XXXX is the four-digit number denoting
the specific element desired, lXX is for -55°C to
125°C and 9XX is for 0°C to 70°C.
NOTE: The packages 6A* and 6E* are similar to
6A and 6E. For ordering, the asterisk must be
included.

CONNECTION DIAGRAM

PLASTIC DIP
375
TVP.

l=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-45

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD ..HYBRID CIRCUITS SH6400 • SH6401 • SH6402
ELECTRICAL CHARACTERISTICS (25°C Free Air Temperature unless otherwise noted}

SH6400SYMBOLCHARACTERISTIC

MIN.

Collector to Emitter Sustaining Voltage (Note 4)
VcEOrsusl
Collector to Base Breakdown Voltage
BVceo
Collector to Base Breakdown Voltage
BVcEs
Emitter to Base Breakdown Voltage
BVEeO
Collector Reverse Current
Ices
Collector Reverse Current
Ices
Collector Reverse Current
ICES
Collector Cutoff Current
lceoCollector Cutoff Current
lceoCollector Cutoff Current
lceoCollector Cutoff Current
lceo(l00°C)
Collector Cutoff Current
lceo(l00°C)
Pulsed Base Saturation Voltage (Note 4)
VeErsatl
Pulsed Base Saturation Voltage (Note 4)
VeErsatl
Pulsed Base Saturation Voltage (Note 4)
VeErsallPulsed Base Saturation Voltage (Note 4)
VeErsatl
Pulsed Collector Saturation Voltage (Note 4)
VCElsallPulsed Collector Saturation Voltage (Note 4)
VCElsallPulsed Collector Saturation Voltage (Note 4)
VCE!sallPulsed Collector Saturation Voltage (Note 4)
VCElsallVcE1sat1(-55°C) Pulsed Collector Saturation Voltage (Note 4)
VcE1sa11(-55°C) Pulsed Collector Saturation Voltage (Note 4)
Pulsed Collector Saturation Voltage (Note 4)
VcE1satl(l00°C)
VCElsatl(100°C) Pulsed Collector Saturation Voltage (Note 4)
DC Pulse Current Gain (Note 4)hFE
DC Pulse Current Gain (Note 4)hFE
DC Pulse Current Gain (Note 4)hFE
DC Pulse Current Gain (Note 4)
hFE
High Frequency Current Gain (f = 100 MHz)
hre
Turn On Time (Note 5)
ton
Turn Off Time (Note 5)
to ff
Storage Time (Note 5)t,Collector to Base Capacitance (f = 1.0 MHz)
ccb
Emitter to Base Capacitance (f = 1.0 MHz)
c.b

TYP.

SH6401
MAX.

-50
-50
-50
-5.0

MIN.

TYP.

SH6402
MAX.

-40
-40
-40
-5.0
0.01

TYP.

-20
-20
-20
-5.0

Volts
Volts
Volts
Volts
µA
µA
µA
0.01
5.0
µA
µA
µA
0.01
10
µA
µA
-0.7 -0.9 Volt
-0.8 -1.0 Volt
-1.0 -1.5 Volts
Volts-0.1 -0.3 Volt
-0.l -0.3 Volt
-0.3 -0.6 Volt
Volt
Volt
Volt
Volt
Volt
50
75
70

1.0

0.01

0.5

MIN.

0.01

1.0

0.01

1.0

1.0

120

0.5
120
-0.7 -0.8-0.7 -0.8-0.8 -0.9-0.8 -0.9-0.6 -1.0 -1.2 -0.6 -1.0 -1.2
-1.1 -1.7-1.1 -1.7-0.1 -0.25-0.1 -0.25-0.1 -0.3-0.1 -0.25-0.3 -0.55-0.3 -0.5-0.5 -1.0-0.5 -0.9
-0.25
-0.25
-0.5
-0.55
-0.3
-0.3
-0.65
-0.6
20
50
20
50
50
75
50
75
30
20
70
70
10
15
30
30
1.7
2.8
2.0
2.8
25
40
25
40
65
90
65
90
50
50
60
60
15
25
15
25
100
80
100
80

15
25
10
1.5

2.8
25
65
50
20
80

MAX.

50
100
75
25
100

UNITS

TEST CONDITIONS
le= lOmA
le =0
le= lOµA
IE =0
le= lOµA
VeE = 0
IE= 10 µA
lc=O
VcE=-30V
VeE = 0VcE=-25V
VeE = 0VcE = -15 V
VeE=O
Vee= -30V
IE= 0
Vee= -25V
IE =0
Vee= -15 V
IE= 0
Vee= -30V
IE= 0
Vee= -25V
IE= 0
le= LO mA
le= lOmA·le= 10 mA
le= lOOmA
le= 500mA
le= 50 mA
le= lOOOmA
le= lOOmA
le= 1.0 mA
le= lOmA
le= lOOmA
le= 10 mA
le= 50 mA
le= 500mA
le= lOOOmA
le= 100 mA
le= 1.0 mA
le= lOmA
le= 50 mA
le= 500 mA
le= 1.0 mA
le= lOmA
le= 500 mA
le= 50 mA
le= lOmAVcE = -1.0 V
le= lOpmA
VcE=-1.0V
le= 500mA
VcE=-1.0V
le= lOOOmA
VcE = -1.0 V
le= 50mA
VcE = -lOV
le= 500mA
le 1 = 50mA
le= 500mA le 1 = -le 2 = 50 mA
le= 500mA le 1 = -le 2 = 50 mA
Vee= -lOV
IE=O
VEe = -0.5 V
lc=O

ns
ns
ns
pF
pF

TYPICAL ELECTRICAL CHARACTERISTICS
SH6400
COLLECTOR CHARACTERISTICS"'

DC PULSE CURRENT GAIN
VERSUS COLLECTOR CURRENTCOLLECTOR CHARACTERISTICS 0-20,.--r--....-.--,,---,,-"MT"rrnr--,--,lOO

A• -55'C-: ~16

~

I
t-

I
t-

ffi

~ -121f-~--l--o.,.~:...+-f-IH+--+--l

<.>

~

-16

z

...c

-16

5

ffi

a"'"'

"'
!;i -8.0 lt'7"""t--+-:-::, ~ c:o--t---t-t-tlt---t---i I'!~ -8.0

z

""
"'

~

a..."'
_,

60

. 40

I'!

"'~

fi:: -8.0:::ll'--b,.....F--1--1--.A-.J+l---+---l8~8
1-4.0 t<--+:::::::J~"i""=J--lf-H-+-l ~' -4.0 i-,,,.i..;""""F--1--1-----hHl---+---l ; 20~-4.0Ll~~::r::r::rn
<.>

-40

-60

-60

-80

VcE -COLLECTOR -EMITTER VOLTAGE-VOLTS-80

VcE -COLLECTOR-EMITTER VOLTAGE - VOLTS

COLLECTOR CHARACTERISTICS*

COLLECTOR CHARACTERISTICS"-1000 r=---::c:o:--r---r-177r-:..,--,.,----,:7'1

-0.2

-0.4

-0.6

-60

-40

~

~

0

-80

-10

'

Jl i~·c
_I

"""

~·c

~

~

I
-20

VcE- COLLECTOR TO EMITTER VOLTAGE-VOLTS

-50

-100

-200

-500 -1000

Ic -COLLECTOR CURRENT-mA

COLLECTOR SATURATIONVOLTAGE VERSUSCOLLECTOR CURRENT-IOOO .-----.-,.--,----,7"7''"7""-::;r--:P......-,

VcE -COLLECTOR-EMITTER VOLTAGE.-VOLTS

v

I

I

-20

•c

f!ff

t-

~ -12 -~-+-<----t--+H-+Hf---t----1

l!i

80

VcE • -5.0V-1.0

VCE -COLLECTOR -EMITTER VOLTAGE -VOLTS•Single family characteristic on Transistor Curve Tracer.

5-46

0 0

...

-0.2

-0.4

-0.6

-1.2 ~

VcE-COLLECTOR -EMITTER VOLTAGE-VOLTS

~10

-20

-50

-100

-200

-500 -1000

le- COLLECTOR CURRENT- mA

FAIRCHILD HYBRID CIRCUITS SH6400 • SH6401 • SH6402,
TYPICAL ELECTRICAL CHARACTERISTICS
SH6401 • SH6402
COLLECTOR CHARACTERISTICS*

DC PULSE CURRENT GAIN
VERSUS COLLECTOR CURRENTCOLLECTOR CHARACTERISTICS0

COLLECTOR CHARACTERISTICS 0

100

"'EI

"'
...~
..,"'"' -12
-16

E

"'E

-16

...

...
...z

~ 80

!;;

...

..,"'"' -12

B

~ 60

..,::>

::>

kd

...

-40

-50

-30

-40

-10

-50

-30

-40

-10

-50

-zo

-50

-'100 -zoo~
-500 -1000

le -COLLECTOR CURRENT-mA

COLLECTOR SATURATIONVOLTAGE VERSUSCOLLECTOR CURRENTCOLLECTOR CHARACTERISTICS*

COLLECTOR CHARACTERISTICS*

COLLECTOR CHARACTERISTICS*-20

VcE -COLLECTOR· EMITTER VOLTAGE-VOLTS

VcE - COLLECTOR-EMITTER VOLTAGE-VOLTS*~

1A'_55'C

0
-30

-20

~

..1--H

i 20

-10

~

1. •c

~

..,~ 40"'I

VcE-COLLECTOR VOLTAGE-VOLTS

,.~
~

I

~ -12

::>

VcE•~5.0Vz-16

I---+-+-++-·-----

0'--~--+--'--....__..._...._.._.._~

-0.4

-0.2

-0.6

-0.S

-0.Z

-1.0

-10

-1.0

-0.4

VcE -COLLECTOR- EMITTER VOLTAGE -VOLTS

VcE -COLLECTOR-EMITTER VOLTAGE ·VOLTS

-20

-50

SH6400 • SH6401 • SH6402
BASE CHARACTERISTIC*BASE CHARACTERISTIC 0

l

-1000
TA•IOOl[-20mA--;

El -soo-~...

El -sooH -120mA 1--1---i !;;It--t1-., Fl

I

1--

1:l

8"' -600

1-'"~mAf---'.Y_Omi"'~ -400jjt---r--t--t-t--l'T--fitl~t-+--~SO~mf-A-t--1 ~';l -SOO t--+--t--t-t--+-itllf--lOOmA t-- ,!.
~~p120mA..,~ -600Is• -IOmA

t3 -400l-40mA-1

...

l

"'~

-1000 .--T-A-.--5--5-.C,.-,--.-_-60-rl_m-A-mnrr-r---r--i "' -1.6 Ic • 16Is

-60mA

°TA• 25'C

H-SOmA-IOOmA-20mA~

-2b~

~
~

8

..l

~

-0.4

-0.S

-1.2

-1.6

10

17

1.0

~

0.51---+-+---+--+---1--t-tz:..L.J...,__,.A~ 0.2 1----+---+----+---+J:Z__,[L_l"--+---+--t~:~

O.l l---+-+---t-7'F----11---+-+---i
0.051---+-+-L-AV--+-_,l---+-+---i

8

~0.02

~
~8.0

a"'
~6.0
~4.0

~

~

~~

-1.2

-1.6

-2.0

VBE - COLLECTOR-EMITTER VOLTAGE -VOLTS

INPUT AND OUTPUTCAPACITANCE VERSUSREVERSE BIAS VOLTAGE.......

0'--~_,-+_,____....__..._...._

-10

-20

-50

-100 -200

2[Z

CONTOURS OF CONSTANTBANDWIDTH PRODUCT (fr)v

vL

. ~2.0

L

~

50

75

100

TA ·AMSIENT TEMPERATURE-'C

125

-10

-20

-30

-0.1

VCE· REVERSE SIAS VOLTAGE-VOLTS

-1.0

·10

REVERSE BIAS VOLTAGE -VOLTS*Single family characteristic on Transistor Curve Tracer.

5-47

_~

-500 -1000

Ic - COLLECTOR CURRENT- mA

.L

!;;

;:;
"'

-o.s

~

2j

TA• 25•c

I~ O.Ol~"'--+--~-+-~~-~-1---,-! .!I 0 025.....__.._.__...._~-0.4.,.,·c ~ ~~_vl-1J/I

1-+-+---t-ffilll'ftti/11tttl/Ll-+-+--t-1 ~
0

-2.0

-o.s

~ -0.4 '---+--<-+-+--+--+--+-+-+--t1L

O'---'--'---'-...._........
-1.6

COLLECTOR REVERSE
CURRENT VERSUSREVERSE BIAS VOLTAGE...

aJJ./Jlli -1.2

-0.B

VBE - SASE- EMITTER VOLTAGE-VOLTS

COLLECTOR REVERSE
CURRENT VERSUSAMBIENT TEMPERATURE

1:l:::f -2QQ

Jl1JJJL

-0.4

-2.0

VsE - BASE-EMITTER VOLTAGE-VOLTS:i:
1- 2.0 VcE•-30V

Ie=-lOm~1:::/ -200

V,

-600

"'
~

~ -1.2

f--12omAaI

I,!1-200

j40mA"":~ -400 l--+--+--+-l--+t-Hft--+-1---+--1 ~Ie•-lOmA°"

8

8-500 -1000

BASE SATURATIONVOLTAGE VERSUSCOLLECTOR CURRENT

BASE CHARACTERISTIC*-1000-100 -200

Jc-COLLECTOR CURRENT-mA

VccCOLLECTOR-EMITTER VOLTAGE-VOLTS-50
Ic - COLLECTOR CURRENT- mA

FAIRCHILD HYBRID CIRCUITS SH6400 • SH6401 • SH6402
TYPICAL SWITCHING CHARACTERISTICS
DELAY TIME VERSUS TURN ON
BASE CU~RENT AND REVERSE
BASE EMITTERVOLTAGE{_:v

STORAGE TIME VERSUS
TURN ON AND TURN OFF
BASE CURRENTS"'~ 5.0..
...a..
......

...~

STORAGE TIME VERSUS
TURN ON AND TURN OFF
BASE CURRENTS

50

..
'
.....
...
..
'
..

E

"'~ 4.0.....

!Z 150~>:: 3.0...i...; 2.0

B

30

lJl

I

.
..
....

~ 100

z

~ 20

0

z

lJl

... 0

>m

::>
....
50

~ 10

.;:'

~

'§

0

IB1 - TURN ON BASE CURRENT- mA

-10
-20
-30
-40
lBl - TURN ON BASE CURRENT- mA

RISE TIME VERSUS COLLECTORCURRENT AND TURN ON
BASE CURRENTS

FALL TIME VERSUS
TURN ON AND TURN OFF
BASE CURRENTS

-20

-30

-50

-70

-100

5.0 f----+-----+---cf---f----+--+--+-+-+-H

z

::>

~ 1.0

200

E

~ 40

0

SWITCHING TIMES VERSUSCOLLECTOR CURRENT0

2.0 t---+---+--+-+-- le ·10191 •101B2_,
vcc -3ov..\.....Ci]

1---+--+--"'-+--+-----4- lc•500mA
vcc·-3ov

1' 1

1.0~-~~-~~-+-~~-J_UJ~~

0
0

-50

-100

-150

-200

-100

-200

-300

-500

-1000

151 - TURN ON BASE CURRENT- mA

le - COLLECTOR CURRENT- mA

FALL TIME VERSUS
TURN ON AND TURN OFF
BASE CURRENTSSWITCHING TIMES VERSUSAMBIENT TEMPERATURE
100

..

50

E

'

.
!;;

:;

~50b-~""""""'l'----+---+-+--,J

--<
e--

~
t'-.;;;;
I---

If t-"'"' 10 t--~

~ 20

B

.;::

lJl

:l

z

;;

z

-

td

"~ 5.00z~ 20.b::::=:I~

1-le lj: 500mA

2.0

-100

-200

-500

-20

-10

0

le - COLLECTOR CURRENT-mA

-30

-40

1.0

-50

191 - TURN ON BASE CURRENT - mA

-50r

TURN OFF CIRCUIT+13.4V

-30V

•2.0Y

r r
O.lpF

20pF

2000

r

IOO
TA - AMBIENT TEMPERATURE-'c

191 - TURN ON BASE CURRENT - mA

TURN ON CIRCUIT

O.lpF

Ia1"IB2"'jmA
Vee• -3ov

20pf

2000

!590

TO SAMPLING SCOPE

LJ YiNT-2.0pf

lr<lnsZ1N•IOOkQ

2000

-30Y

590

TO SAMPLING SCOPE

1,<lnsZ1N• IOOkO
1N916

V1N•~t9.5V~--+--<>+3V

PW=2.0t11

lplf "<5.5ns

1000

I_ O.lpF

1000

Z1N• 500

DUTY CYCLE <2.0%

NOTES:(1) These ratings are limiting values above whicH the serviceability of any individual semiconductor device may be impaired.
(2) These are steady state limits. The factoiy sho~ld be consulted on applications involving pulsed or low duty cycle operations.
(3) These ratings give a maximum junction temperature of 200°C and junction to case thermal resistance of -135°C/Watt (derating factor of -7.4 mW!°C) for the Flat
package and Ceramic Dual In-Line package. Maximum junction temperature of 150°C and junction to case thermal resistance of -83°C/Watt (derating factor of -12
mwl° C)· for the Plastic Dual In-Line package.
(4) Pulse Conditions: length= 300 µs; duty cycle= 1 %.
(5) See switching circuit for exact value of le, 1.,, and 182.

5-48

150

SH6500•SH650l•SH6502
NPN QUAD CORE DRIVERS
FAIRCHILD HYBRID CIRCUITSFEATURESPHYSICAL DIMENSIONS• HIGH VOLTAGE •..•••• UP TO 50 VOLT LVceo• HIGH CURRENT .•••••• UP TO 1 AMP• FAST SWITCHING •••••• 25 ns t 0 n (TYP)
45 ns t 011 (TYP)• COMPACT PACKAGING ••• 4 TRANSISTORS PER PACKAGEFLAT PACK

.0060

.ago

TOP VIEW:°":5'
11_____L:'6'~====c=====:J§~§-.ABSOLUTE MAXIMUM RATINGS (Note 1)
Maximum Temperature
Storage Temperature
Operating Temperature
Operating Junction Temperature
Lead Temperature (Soldering, GO second time limit)
Maximum Power Dissipation (Notes 2 & 3)
Total Dissipation at 25°C Case Temperature
at 25°C Ambient Temperature

FLAT PACKCERAMIC DIP
PLASTIC DIP-G5°C to +200°C -G5°C to +150°C-55°C to +125°C
0°c to +70°C+200°c+iso 0 c+300°c+300°cFLAT PACKCERAMIC DIP PLASTIC DIP
1.2 Watts
1.5 Watts
1.5 Watts
0.5 Watt
0.8 Watt
O.G Watt

"·038
.032

1--~~----j

1

CERAMIC DIPORDER INFORMATION
Specify HBHXXXXlXX, 9XX for 14-pin Flat Pak
HGA*XXXXlXX, 9XX for 14-pin Ceramic DIP
HGE*XXXX9XX for 14-pin Plastic DIP
Where first XXXX is the four-digit number denoting
the specific element desired, lXX is for -55°C to
125°C and 9XX is for 0°C to 70°C.
NOTE: The packages GA* and GE* are similar to
6A and GE. For ordering, the asterisk must be
included.

---14

CONNECTION DIAGRAM

PLASTIC DIP
.375
lYP.

.011
.009

l-

F.AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-49

A DIVISION OF FAIRCHILD CAMERA ANO INSTRUME"4T CORPORATIONFAIRCHILD HYBRID CIRCUITS SH6500 • SH6501 • SH6502
ELECTRICAL CHARACTERISTICS (25°C Free Air Temperature unless otherwise noted)
SYMBOLCHARACTERISTICMIN.

VCEO(sus)
BVcso
BVcEs
BVESO
ICES
lcso
lcso(100°C)
VBE(satl
VeEcsatl
V.eECsatl
VeE(satl
VCECsatl
VCECsatl
VCECsatl
VCE(satl
VCE(satl(-55"C)
VcEcsatl(-55°C)
VcEcsati(lOO•c)
VcEcsatl(lOO•c)
hFE
hFE
hFE
hFE
hie
ton
to ff
t,

Collector to Emitter Sustaining Voltage (Note 4)
Collector to Base Breakdown Voltage
Collector to Emitter Breakdown Voltage
Emitter to Base Breakdown Voltage
Collector Cutoff Current
Collector Cutoff Current
Collector Cutoff Current
Pulsed Base Saturation Voltage (Note 4)
Pulsed Base Saturation Voltage (Note 4)
Pulsed Base Saturation Voltage (Note 4)
Pulsed Base Saturation Voltage (Note 4)
Pulsed Collector Saturation Voltage (Note 4)
Pulsed Collector Saturation Voltage (Note 4)
Pulsed Collector Saturation Voltage (Note 4)
Pulsed Collector Saturation Voltage (Note 4)
Pulsed Collector Saturation Voltage (Note 4)
Pulsed Collector Saturation Voltage (Note 4)
Pulsed Collector Saturation Voltage (Note 4)
Pulsed Collector Saturation Voltage (Note 4)
DC Pulse Current Gain (Note 4)
DC Pulse Current Gain (Note 4)
DC Pulse Current Gain (Note 4)
DC Pulse Current Gain (Note 4)
High Frequency Current Gain (f = 100 MHz)
Turn On Time
Turn Off Time
Storage Time
Emitter to Base CapacitanceCollector to Base Capacitance

50
80
80
6.0

c.b
ccb

SH6500
TYP.

0.1
0.1
5.0
0.7
0.8
0.95

0.9

1.1
0.15
0.16
0.3
0.5

UNITS

TEST CONDITIONS

120
0.8
0.9
1.2
1.7
0.25
0.3
0.55
1.0
0.25
0.55
0.3
0.65

Volts
Volts
Volts
Volts
µA
µA
µA
Volt
Volt
Volts
Volts
Volt
Volt
Volt
Volt
Volt
Volt
Volt
Volt

35
60
50
55
12

ns
ns
ns
pf
pf

le= 10 mA
Is= 0
le= 10 µA
IE= 0
le= lOµA
Is= 0
IE= 10 µA
lc=O
VsE = 0VcE = 40V
IE= 0
Vcs = 40V
IE= 0
Vcs = 40V ·Is= 1.0 mA
le= 10 mA
Is= 10 mA
le= 100 mA
Is= 50mA
le= 500 mA
Is= 100 mA
le= 1000 mA
Is= 1.0 mA
le= lOmA
Is= 10 mA
le= 100 mA
le= 50 mA
le= 500 mA
16 = 100 mA
le= 1000 mA
Is= 1.0 mA
le= lOmA
le= 50 mA
le= 500 mA
Is= 1.0 mA
le= lOmA
le= 50 mA
le= 500 mA
VcE·= 1.0 V
le= lOmA
le= 100 mA
VcE = 1.0 V
le= 500 mA
VcE = 1.0 V
le= 1000 mA
VcE = 1.0 V
le= 50mA
VcE = lOV
le= 500 mA
le 1= 50 mA
le= 500 mA, le 1= -le 2 = 50 mA. le= 500 mA, le 1= -le 2 = 50 mA
lc=O
VEe = 0.5 v
IE= 0Vee= lOV

MAX.

1.7

1.7

65
90
50
20
4.5
25
45
35
40
5.0

20
50
20
10
2.5

TYPICAL ELECTRICAL CHARACTERISTICS
SH6500
COLLECTOR CHARACTERISTICS"'COLLECTOR CHARACTERISTICS"'

DC PULSE CURRENT GAIN
VERSUS COLLECTOR CURRENTCOLLECTOR CHARACTERISTICS*
ro.-~.-~~~~~--.--,-~

<

E

16

v

o~~~~~-++~~~~~

100
VcE - COLLECTOR-EMITTER VOLTAGE - VOLTS

VCE - COLLECTOR-EMITTER VOLTAGE - VOLTS

COLLECTOR CHARACTERISTICS"'COLLECTOR CHARACTERISTICS"'COLLECTOR CHARACTERISTICS*

11100 r-r-r-r--r-T?.cr:;,..,.-....,,,.-,--,

IK,-,-,-,--,--~..,-;;,.,-:,,..,---r::=

·<

600

ag

E

!!!

~ 600

!;:

~

BOO

g
bl 400~..!' 200

_u

~

800

~

Hl1!1-+--+-+++-+--+-+++-1_,,

0.61--++++--+-+-+++-+--+-1-++-+-1

~
i!L

i~

~

a

~ 0.4

I

400

g

~

-

200

~ 17
I--+-

OLL.._.._....__,__._....._-'---'---'--J
0.8

l.2

2.0

0.4

0.8

l.2

l.6

0

2.0

0.4

0.8

1.2

1.6

VcE - COLLECTOR-EMITTER VOLTAGE - VOLTS

VCE - COLLECTOR-EMITTER VOLTAGE - VOLTS• Single family characteristics on Transistor Curve Tracer.

5-50

2.0

A~~.2~5~'C-t-+t1--l~-7r7f7ft-~

l::::::J~!:t'.~J~r~:.·~1o~o·c~$...-1:;if~~Y1r-tiH

0.21

~

VcE - COLLECTOR-EMITTER VOLTAGE - VOLTS

11100

COLLECTOR SATURATION VOLTAGE
VERSUS COLLECTOR CURRENT
8

800

100

le - COLLECTOR CURRENT - mA

: o.
<E

10

1.0

VCE - COLLECTOR-EMITTER VOLTAGE - VOLTS

lUss•c"' ·~~~~~-++~~~~~

~

l.O

10

100

le - COLLECTOR CURRENT - mA

11100

FAIRCHILD HYBRID CIRCUITS SH6500 • SH6501 • SH6502
ELECTRICAL CHARACTERISTICS (25°C Free Air Temperature unless otherwise noted)
SYMBOLCHARACTERISTIC

MIN.

Collector to Emitter Sustaining Voltage
VcEO
Collector to Base Breakdown Voltage
BVceo
Collector to Emitter Breakdown Voltage
BVcEs
Emitter to Base Breakdown Voltage
BVEBO
Collector Cutoff Current
ICES
Collector Cutoff Current
lceo
lcso(lOOoC)
Collector Cutoff Current
Pulsed Base Saturation Voltage (Note 4)
VBErsatl
Pulsed Base Saturation Voltage (Note 4)
V.SECsatl
Pulsed Base Saturation Voltage (Note 4)
VBECsatl
Pulsed Base Saturation Voltage (Note 4)
VBEfsatl
Pulsed Collector Saturation Voltage (Note 4)
VcErsatl
Pulsed Collector Saturation Voltage (Note 4)
Vcersatl
Pulsed Collector Saturation Voltage (Note 4)
VcErsatl
Pulsed Collector Saturation Voltage (Note 4)
Vcersatl
VCE!sa+1(-55oC) Pulsed Collector Saturation Voltage (Note 4)
Vcersat1(-55°C) Pulsed Collector Saturation Voltage (Note 4)
Pulsed Collector Saturation Voltage (Note 4)
VcErsatl(l00°C)
Pulsed Collector Saturation Voltage (Note 4)
Vcersatl(lOOoC)
DC Pulse Current Gain (Note 4)
hFe
DC Pulse Current Gain (Note 4)hFE
DC Pulse Current Gain (Note 4)hFE
DC Pulse Current Gain (Note 4)
hFe
High Frequency Current Gain (f = 100 MHz)
hie
Turn On Timeton
Turn Off Time
to ff
Storage Timet,
Emitter to Base Capacitancec.bCollector to Base Capacitance
ccb

SH6501
TYP. MAX.

40
70
70
6.0

0.9

30
50
30
15
2.5

MIN.

SH6502
TYP. MAX.

20
40
40
6.0
1.7
1.7
120
0.8
0.9
1.2

0.1
0.1
5.0
0.7
0.8
0.95
1.1

1.7

0.15
0.16
0.3
0.5

0.25
0.25
0.5
0.9
0.25
0.5
0.3
0.6

65
90
50
20
4.5
25
45
35
40
5.0

0.1
0.1

10
10

0.7
0.8
0.95

0.9
1.0
1.5

0.15
0.16
0.3

0.3
0.25
0.6

15
25
10

65
90
50

2.0

4.5
25
45
35
40
5.0

35
60
50
55
12

50
75
65
55
12

UNITS

TEST CONDITIONS

Volts
Volts
Volts
Volts
µA
µA
µA
Volt
Volt
Volts
Volts
Volt
Volt
Volt
Volt
Volt
Volt
Volt
Volt

18 = 0le= lOmA
le= 10 µA
IE= 0
18 =0
le= lOµA
le= lOµA
lc=O
VcE=40V
VBE = 0le=O
Vcs = 40V
Vc 8 =40V
IE= 0
Is= 1.0 mA
le= lOmA
18 = lOmA
le= 100 mA
18 = 50 mA
le= 500 mA
18 = 100 mA
le= lOOOmA
18 = 1.0 mA
le= lOmA
le= lOOmA
Is= lOmA
le= 500 mA
Is= 50mA
le= 1000 mA
Is= 100 mA
Is= 1.0 mA
le= lOmA
Is= 50mA
le= 500mA
18 = 1.0 mA
le= 10 mA
Is= 50mA
le= 500mA
le= lOmAVcE = 1.0 V
le= lOOmA
Vee= l.OV
le= 500 mA
VcE = l.OV
le= lOOOmA
Vee= l.OV
le= 50mA
VcE = lOV
181 =50mA
le= 500mA
le= 500 mA, ls 1 = -ls2 = 50 mA
le= 50mA, 181 = -ls 2 = 50 mA
VEB = 0.5
lc=O
Vcs = lOV
le= 0

ns
ns
ns
pf
pf

v

TYPICAL ELECTRICAL CHARACTERISTICS
SH6501 • SH6502
COLLECTOR CHARACTERISTICS 0

'!!

~

a

DC PULSE CURRENT GAIN
VERSUS COLLECTOR.CURRENTCOLLECTOR CHARACTERISTICS 0

COLLECTOR CHARACTERISTICS*

16

12

i'l

~

8.0

-"' 4.0

VCE - COLLECTOR-EMITTER VOLTAGE - VOLTS

VcE - COLLECTOR-EMITIER VOLTAGE - VOLTS

VcE • COLLECTOR-EMITTER VOLTAGE - VOLTS

COLLECTOR CHARACTERISTICS*

COLLECTOR CHARACTERISTICS*

COLLECTOR CHARACTERISTICS"'le - COLLECTOR CURRENT • mA

COLLECTOR SATURATION VOLTAGE
VERSUS COLLECTOR CURRENT

looo,-,-,-,--;:-::;=-:,.,.---r:;;...,~,..,

i

a

I

0.8

~

0.6

g

'!! 800~. 600

I!?

·H
0.4

8 0.2 ~-"' 200

lJ 0
VcE - COLLECTOR-EMITTER VOLTAGE - VOLTS

0.4

VCE - COLLECTOR-EMITTER VOLTAGE - VOLTS

0.8

Ver - COLLECTOR-EMITTER VOLTAGE - VOLTS• Single family characteristics on Transistor Curve Tracer.

5-51

2.0

l.O

~

u
~

I~

~

2.0

t--

;rr25h ko' l?lTA • 100°C

l;l

L.6

H

1

I

i5

I 400~t.1~i.._j...4::~=t==+=+~ Ie400r-i}111

10

I

TA•

1-1r

100

le - COLLECTOR CURRENT - mA

1000

FAIRCHILD HYBRID CIRCUITS SH6500 • SH6501 • SH6502
TYPICAL ELECT-RICAL CHARACTERISTICS
BASE CHARACTERISTICS*

BASE CHARACTERISTICS*
1000

r--{ .Jc·1~~A

18·mmA] '1

-j_ ~
1 iL1

0

Ve£ - BASE-EMl11ER VOLTAGE - VOLTS

~ 400

Tf!f!

1.2

1,6

2.0

~

j7
---+-l0.1

o~.._._.....__..,.,_-'-'...J..J..-J--'--L...L.J--,.,1.

0.8
1.2
1.6
0.4
VeE - BASE-EMITTER VOLTAGE • VOLTS

I. 0

2.0

y
k::::r

!;!

8

100

1000

CONTOURS OF CONSTANTBANDWIDTH PRODUCT (fr)10

Cell - EMITTER TRANSITION CAPACITANCE r

0.4"~ 0.210

le - COLLECTOR CURRENT - mA

100

B 0.3
~

j7
1.0

00

INPUT AND OUTPUTCAPACITANCE VERSUSREVERSE BIAS VOLTAGEt-T)25°Cflv J.-"':J11JJJ
11111-" 200

0.5

10

600

8

50
~

~ 800

VeE - BASE-EMITTER VOLTAGE - VOLTS

~

~

'j_

COLLECTOR CUTOFF CURRENTVERSUS REVERSE BIAS VOLTAGE

B

i

0.8

>

lM>mA

!!i

COLLECTOR CUTOFF CURRENTVERSUS AMBIENT TEMPERATURE
t--Vce ·«>v~

0.4

T .• -5S°C

I

_L~I;

0

0 ~o-'-~o~.4_..~o~.8..LJ...-+.1.2,_.;._.,...1.6_.,...-='2.o

9 1.6 I~ ·'1J1~

IK

H_i.JmA

1801--+-l

1

BASE SATURATION VOLTAGE
VERSUS COLLECTOR CURRENT

BASE CHARACTERISTICS*

v

1-d

~

le. o

I"---.

c}: OUTPUTI~

CAPACIT~NC,E

- -

~ J

I lL

_l ~ ~ L1 v Y1
Hz

1.0

SH6501 and 511652

IE"O Sll6500

ii J_

_l

l't

35

MHz

--

z

./

JL

~~ 0.1
o.oI
75

0

100

TA - AMBIENTTEMPERATURE - °C

0

m

80

Vee - COLI.ECTOR-BASE VOLTAGE - VOLTS

DELAY TIME VERSUS TURN ON
BASE CURRENT AND REVERSE
BASE EMITTER VOLTAGE

STORAGE TIME VERSUS TURN ON
AND TURN OFF BASE CURRENTS

0.5 1.0
5.0 10
REVERSE BIAS VOLTAGE - VOLTS

le - COlllCTOR CURRENT - mA

STORAGE TIME VERSUS TURN ON
AND TURN OFF BASE CURRENTS

STORAGE TIME VERSUS TURN ON
AND TURN OFF BASE CURRENTS

JOO.----.--.....---.--.-....---.----.

50.--.--,--,--,--,--,--,--,--,v~~ 2001----+-+-+--

!!i

"

~

!;

i 100r---+-~__,l---7'f--+---I
_.s'

=

>

lO
40
50 60 70 80 90 100
IBl - TURN ON BASE CURRENT - mA

50
100
150
I91 - TURN ON BASE CURRENT - mA

I Bl - TURN ON BASE CURRENT - mA

LL

1---+-p-;~~
~

~

~·Y

~z lO ~
~

L

~

50

B 401--"~zle • 800mA
Yee• JOV

L

IL
1L

vlL1 _LJv

71k'.".:'--t-+-++-v-I,,~·.......-

mt-t-t-H-t-:7"'t...--t--1-+..-+--t--1

J..-1--v

JOO

JOO.--~-....----.~-.---.----.

1rTtz

1-t-

100
200
191 - TURNONBASECURRENT - mA

FALL TIME VERSUS TURN ON
AND TURN OFF BASE CURRENTS

FALL TIME VERSUS TURN ON
AND TURN OFF BASE CURRENTS

RISE TIME VERSUS COLLECTOR
AND TURN ON BASE CURRENTS
loo

200

V1

~~-J_+vee-ti-i~-v-i

I---+---+---+-+---+- le• 500mA

Vee ·JO

I050!::--'--'-.L..J.,1±00.e::;;._-'---:±200,_.l.~JOO,b.-l.-,!400,,.-,!.500

le - COlllCTOR CURRENT - mA

100
I91 - TURN-ON BASE CURRENT - mA

'e1 - TURN ON BASE CURRENT - mA

• Single family characteristics on Transistor Curve Tracer.

5-52

200
I91 - TURN ON BASE CURRENT - mA

FAIRCHILD HYBRID CIRCUITS SH6500 • SH6501 • SH6502
TYPICAL SWITCHING CHARACTERISTICSSWITCHING TIMES VERSUSCOLLECTOR CURRENTSWITCHING TIMES VERSUSAMBIENT TEMPERATURE

100

t,

--i-..

20 I"'--...~

~t---

w

r--i-..

\!-~~!.:::::le •SlllJmA
181 •18i • SOmA

l-1c·Wls1 ·10182

v,,;iov

Vee• 30V

200
SOO
le • COLLECTOR CURRENT • mA

so100
TA • AMBIENTTEMPERATURE • 'C

IK

ISO

SWITCHING TIME TEST CIRCUIT
-3.BV

+30V

150
ll'F VOUT

f--o

lkO

ZIN~ lOOkll

l.Op·f
VtN = +9.7V
Ir & If ~ lns
P.W.'" lps
Z1N = 500
DUTY CYCLE < 2%

TO SAMPLING SCOPE
Ir < lns

VtNL

1620

lc '"500mA, 181 '"50mA, 182 "'-50mA

NOTES:(1) These ratings are limiting values above which the serviceability of any individual semiconductor device may be impaired.
(2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
(3) These ratings give a maximum junction temperature of 200°C and junction to case thermal resistance of -135°C/Watt (derating factor of -7.4 mW/°C) for the Flat package
and Ceramic Dual In-Line package. Maximum junction temperature of 150°C and junction to case thermal resistancs of -83°C/Watt (derating factor of -12 mW!°C) for the
Plastic Dual In-Line package.
(4) Pulse Conditions: length= 300 µs; duty cycle= 1 %.
(5) See switching circuit for exact value of le, IB1, and h2.

5-53

SH8080
4-BlT ARITHMETIC UNIT
FAIRCHILD HYBRID CIRCUITSGENERAL DESCRIPTION The SH8080 is a 4-bit ripple carry adder with holding register included.
It consists of MSI chips interconnected on a multi-layer thick-film substrate.

PHYSICAL DIMENSIONSFEATURES• 4 BIT RIPPLE CARRY ADDITION PLUS 4 BIT HOLDING REGISTERWITH TRUE AND COMPLEMENT OUTPUTS• CCSL COMPATIBLE• 32 ns CARRY PROPAGATION TIME (TYP)• 1 VOLT NOISE MARGIN• MILITARY AND INDUSTRIAL TEMPERATURE RANGES• HERMETIC PACKAGEAPPLICATION• AIRBORNE COMPUTERS• DESK TOP CALCULATORS• HIGH SPEED DATA PROCESSING EQUIPMENT• HIGH SPEED GROUND SUPPORT EQUIPMENT

.170
MAX.

ouo

J__

0035

#-~=T
.055

TYPICAL

ABSOLUTE MAXIMUM RATINGS (25°C unless noted)
Vee (pin 32) to ground (pin 16)
InputsVoltage applied to outputs
Current into low output
Storage Temperature
Operating Temperature

NOTES Alld1mens1onsminches

Packagewe1ght1sapprox1mately50eram-0.5 to 8.0 Volts-0.5 to 6.5 Volts-0.5 to Vee
50mA-65°C to +150°C-55°C to +125°C*
0°Cto +70°C

HBY80801XX -55°C to +125°C*
HBY80809XX 0°C to + 70°C

LOGIC DIAGRAM
17

cour n.=15_~

CP
04

ii4

84
A4

03

03
02
02

o,

a,

CLEAR

*At operating temperatures above +100°C, device must be heat sunk.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

5-54

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD HYBRID CIRCUIT SH8080
ELECTRICAL CHARACTERISTICS (Yee= +5.0 Volts, Pin 16 Grounded, TA= 25°C unless otherwise specified)
CHARACTERISTICS

TTµL Load*
Factors

CCSL Load*
Factors

4
1
11
4
9
6

80/48
20/12
240/14480/48
120/72
180/108

Input Loading
Input Loading
Input Loading
Input Loading
Output Drive
Output Drive

Pins 1, 3, 5, 10, 11
Pins 7, 8, 12, 14
Pin 30
Pin 17
Pin 15
Pinsl8, 19, 21, 22,
24,25,27,28
Typical Power Consumption
Typical Carry Propagation Delay
Typica) Clock Pulse Width
Typical Data Setup Time
Typical Output Delay Time (\,d+>Typical Output Delay Time (tpd->

840mW
32 ns
11 ns
64 ns
12rls
21 ns

•Based on TTµL standard Load Factors in Fairchild iTµL Data Sheets and on CCSL Load Factors in CCSL Application Note (AllJllicatlon Nola #154).

SWITCHING TIME TEST CIRCUITAPPLICATIONS.------a GND
530
AH capacitors-50 pf
CLOCK

In this configur1tion
SH8080 increments
on each clock.

17
8
25

11
22

A&B INPUTS

A&B INPUTS

7
10
12
3

C1N
CLEAR

SCOPE

30 SHBOBO

CLOCK- 17

28
14

SCOPE

Q&Q OUTPUTS

19
15

SCOPE

__

30 SH8080-....._
17........

Q&Q OUTPUTS

8 Bit Parallel Adder. Typical operating time is given by 32 ns typicalcarry propagation delay in first stage plus 64 ns data setup timein second stage = 96 ns. By returning true outputs to "A" inputs,
the function A - A+B is performed. If B is "l's" complemented andthe input carry= l, then A - A-Bis realized.

Carry propagation time is measured from pin 19 and/or pin 28 to pin 15
at the appropriate counts.

SWITCHING WAVEFORMSCARRY SAVE ADDER CASCADE~~:;~

1.5¥ - - - GNDl":::mft~TflME__,CARRY IN
1. 5¥ - V
PINS 1,3 OR 5 _ ___,rt.
GND--------1-------.-..v,,..._,- - - - - - --1 ~CARRY

PRoPAGATION DELAY

c•:r.Y i~uT uv - - l ______,i,______s•o::::;:J 1- tpd OUTPUTSj
SH8080*'--------~l----- SH8080

For high speed multiplication a carry save adder cascade followed bySH8080 as carry propagate adder/accumulator can be used. Refer to
App-163 Applications of the CCSL 9304 Dual Adder.

1.5¥
GND----------+----------------~lpd+

1.5¥------

GMO------------------------------Note 1. Clear is normally held high. Q is reset during high to lowtransition.

5-55

HYBRID INTEGRATED CIRCUITS COMING SOON
Type

Function

Type

Function

SH2005
SH3202

Quad Power Gate
Voltage Regulator with Compensation and
Foldback Current

SH80814-Bit Arithmetic Logic Unit

SH2005 - QUAD POWER GATEThe SH2005 is a high speed core, cable or lamp driver. The device
features high voltage and high current capability .. All inputs are CCSL
compatible.
Features:
Inputs CCSL Compatible
Use for Core, Cable and Lamp DriverHigh Current Capability ... 250mA Sinking Current at 0.5 volts.
High Voltage Capability ... 40 volts LVceo ... four 2 input NANO
gates
High Speed - ton = 60ns (typ) ... to11 = 50ns (typ) ... All fourgates switching simultaneously~H3202-Voltage Regulator with Compensation and Foldback Current
The SH3202 is a Hybrid voltage regulator. The device consists of atemperature compensated reference amplifier, power series passtransistor and current limit circuitry.

5-56

Features:
Positive or negative supply operation
Series, shunt, switching or floating operation.01 % line and load regulation
Output voltage adjustable from 2 to 27 volts
Output current to 150mA without external pass transistor
SH8081 - 4·Bit Arithmetic Logic Unit
The SH8081 consists of six MSI 9304, dual full adders and two MSI
9309, dual four bit digital multiplexers.
Features;Multifunction capability
High speed operation
Eight CCSL'MSI chips in one 30 pin flat package
Fully buffered complementary outputs
The input/output characteristics provide easy interfacing with Fairchild DTµL, LPDTµL, and TTµL families CCSLLinearIntegrated
Circuits

LINEAR INTEGRATED CIRCUIT NUMERICAL INDEX
Type

Page No.

Type

Page No.

T~11ePage No.

µA702AµA702BµA702CµA703µA703CµA703EµA709µA709AµA709BµA709CµA710µA710BµA710C

6-1
6-6
6-11
6-16
6-20
6-22
6-26
6-30
6-34
6-36
6-38
6-42
6-46

µA711
µA711CµA716µA716CµA717EµA719µA719CµA722,uA722BµA723µA723C
µA726

6-50
6-54
6-56
6-60
6-64
6-68
6-74
6-80
6-84
6-88
6-94
6-100

µMl.5'-

6-102
6-104
6-108
6-110
6-114
6-118
6-122
6-126
6-129
6-133
6-135
6-137

µAl!'!
µA72lBµA730µA730CµA733µA733CµA737EµA739CµA741µA741CµA751CLINEAR APPLICATIONS/PRODUCTS CROSS REFERENCE
Differential Input, Differential Output AmplifiersµA727, µA730, µA733, µA751C, µ.A725

Operational Amplifiers
General Purpose Summing, Subtracting, Integrating, Differentiating, Impedance Transformers, Analog ComputersµA702,µA709,µA715, µA739,µA740,µA741,µA749

Instrumentation Low drift, Chopper stabilized, Strain gage, ThermocoupleµA726,µA727,µA725

High Input Impedance Active filters, Buffer amps, Transducers, Integrators

1iA727, µA740, µA715, l'A725

low Power Consumption Battery powered, Airborne, Spaceborne, portable, low weight systems,,A741, µA749, µA735

High SpeedPhase-locked loops, A/D & D/A converters, pulse height analyzers, multiplexed analog gates, sample andholds, integrators, and differentiatorsµA702, µA715, ,uA740

Temperature Stabilized Bridge amplifiers, process control, precision measurements, instrumentation amps.

µA726, µA727, l'A725

Power /Driver Amplifiers
Audio Preamp Low noise, magnetic tape, phonoµA730,µA739,µA749

Medium Power Telephone Sysems, head sets

µA716

Power Driver Servos, AudioµA716

High Speed Video -µA715

Comparators
High SpeedLevel detectors, Schmitt triggers, Go-No-Go detectors, Window detector, pulse h1:•ght discriminator, line receivers
Precision Digital volt-meters, A/D and D/ A converters, pulse width modulators, 1Jt,_,,_;r h~~-ed loops, precision
measuring equipment.

µA710,µA711,µA731µA715,µA727,µA740,µA739,,uA749

High Frequency/Communications
IF Amplifiers Microwave, radar, AM & FM IF strips, TVµA703, µA7l 7, µA719

Video Amplifiers -µA702, 11A715, 1tA733

Audio Amplifier -µA716

Demodulators -µA737,µA746

AGC IF Amps-

µA719

6-i

LINEAR APPLICATIONS/PRODUCTS INDEX CROSS REFERENCE
Oscillators
AudioTelemetry phase detector reference, servo systemsµA709,µA740,µA741,µA739,µA749

High Frequency Radar, communications receivers and transmitters, radio, TVµA702,µA703,µA715,µA733

Linear-Digital InterfaceµA710,µA7ll,µA731

Line Receivers Analog to Digital Telemetry, Maintenance monitor, process control
Digital to Analog Telemetry, Process Control, displaysµA710,µA715,µA722µA715,µA722

TelevisionµA703,µA717,µA716,µA719µA703µA703,µA717,µA719µA737, µA746

SoundChroma Oscillator IF Amplifiers Chroma Demodulator -Digital Computer SystemsµA710,µA711,µA731,µA739,µA749,µA751

Core Memories Other Memories Film, Plated wire, magnetic tape, Disc. file
Displays-µA702,µA710,µA733,µA75~µA715, µA722µA722

Hybrid Computers -Power SuppliesµA723µA710,µA7ll,µA723,µA742µA726

Series Voltage Regulators Switching Voltage Regulators Precis!on Low Drift Voltage Reference -µA702,µA709,µA715µA716,µA739,µA740µA741, µA749

Active Filters

Special FunctionsµA722µA715,µA722,µA741
µA726
µA703
µA726,µA737,µA746µA726µA737, µA746µA722µA709,µA726,µA739µA740,µA741,µA749

Digitally Controlled Function Generators Voltage Controlled Function Generator D.C. Logarithmic Amp IF Logarithmic Amp MultiplierDividersProduct Detector ScalerTrigonometric Function Generators -Medical ElectronicsµA727,µA739,µA740µA741,µA725,µA749

Power Control

µA742

6-ii

µA702A
HIGH GAIN, WIDEBAND DC AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITS• IMPROVED SPECIFICATIONSPHYSICAL DIMENSIONS
in accordance withJEDEC(T0-99) outline• 2 mV MAXIMUM OFFSET VOLTAGE~_.370---j• 2500 MINIMUM VOLTAGE GAINI

Ii- -11• 10 µV/°C MAXIMUM OFFSET VOLTAGE DRIFT
GENERAL DESCRIPTION - The µA702A is a complete DC amplifier constructed on a single silicon chip, using
the Fairchild Planar* epitaxial process. It is intended for use as an operational amplifier in high speed analog computers, as a precision instrumentation amplifier, or in other applications requiring a feedback amplifier usefulfrom DC to 30 MHz.

I

.335

,

335
.305

-----11ii~1~'g]·-~!

1

Seat;ng-L'-Plane- j

_::_
1

_

~Ax

T
-

8L~~~~ ~·~ ~ ~~ -~-:cN.016

ABSOLUTE MAXIMUM RATINGS

Voltage Between V+ and v- Terminals
Peak Output Current
Differential Input Voltage
Input Voltage
Internal Power Dissipation
T0-99 [Note ll
Flat Package [Note 21
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 seconds)

21 v
50 mA
±5.0V
+ 1.5 Volts to -6.0 V------T450 TP

300mW
200mW
- 55°C to + 125°C-65°C to + 150°C
300°C

034

\

028~ x;/"'/~/'___ .045//"- A,.029

NOTES D1mens1ons as per latest J-10 comm•tlee
Alld1mens1ons1nmches
Leads aregold·plaled Kovar
Package weight 1s 1.22 grams

ORDER PART NO. U5B770231Xt

PHYSICAL DIMENSIONSSCHEMATIC DIAGRAM(TYPICAL FLAT PACKAGE)(TOP VIEW)

1~'--i__ __,-----1

INVERTINGINPUTOUTPUT

•12

2.&kQ

__l_

~.050

I

••

2.4 kQ

••

480Q

•11

2400

'----~---...__ _ _- 0

ORDER PART NO. U3H770231Xv-

T0-99 CONNECTION DIAGRAM (TOP VIEW)FLAT PACKAGE CONNECTION DIAGRAM (TOP VIEW)v+
NO CONNECTIONGROUND

6 LA]

10

y+

NO CONNECTION

INVERTING INPUTFREQUENCY. COMPENSATIONNON-INVERTING INPUT C::::::t---1

LEAD

LAG COMPENSATIONLEAD COMPENSATION

Note: Pin 4 connected to case.

* Planar is a patented Fairchild process.

Notes on page 2t Equivalent to U5B771231X and U3H771231X

FAIRCHILCl
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-1

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A702A
ELECTRICAL CHARACTERISTICS (TA= 25°C unless otherwise specified)

PARAMETER(see definitions)
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Input Voltage Range
Common Mode Rejection Ratio
Large-Signal Voltage Gain
Output Resistance
Supply Current
Power Consumption
Transient Response (unity-gain)
Risetime
OvershootTransient Response ( x 100 gain)

CONDITIONS

Rs

V+ = 12.0 V, v- = -6.0 V
MIN.
TYP.
MAX.

V+ = 6.0V, v- = -3.0V
MIN.
TYP.
MAX.

0.5
180
2.0
40

0.7
120
1.2
67

s 2 kn
16
-4.0
80
2500

Rs S 2 kn, f < 1 kHz
RL 2 100 kn, Vouf = ±5.0 V
RL 2 100 kn, Vouf = ±2.5 V
Vouf = 0
Vouf = 0
C, = 0.01 µF, R, = 20 n,
RL 2 100 kn, V;, = 10 mVs

CL
100 pFC, = 50 pF, RL 2 100 kn,
V;, = 1 mV

Risetime
OvershootThe following specifications apply for -55°C
Input Offset Voltage
Average Temperature Coefficient of
Input Offset Voltage
Input Offset Current
Average Temperature Coefficientof Input Offset Current
Input Bias Current
Input ResistanceCommon Mode Rejection Ratio
Supply Voltage Rejection Ratio
Large-Signal Voltage Gain
Output Voltage Swing
Supply Current
Power Consumption

2.0
500
5.0

25
10

120
50

ns
%

10
20

30
40

ns
%

600

900
300
2.1
19

n
mA
mW

mV

3.5

15

µV/°C

10
500
1500
5.0

3.0
50
280
0.7

15
500
1500
4.0

µV/°C

3.0

16

2.0

13

nA/°C

4.3

10

2.6

7.5

µA
krl
dB

200

µV/V

TA= 25°C to TA= -55°C

8.0
70

95
75

±5.3
±4.0
4.4
5.0
80
90

95
75

200
7000

2000

500
±2.5
±1.5

1.7

6.7
7.5
120
135

2.1
15
19

(1) Rating applies for case temperatures to +125'C; derate linearly at 5.6 mW/'C for ambient temperatures above +10s c.
(2) Derate linearly at 4.4 mW/'C for case temperatures above +115'C; derate linearly at 3.3 mW/'C for ambient temperatures above +100°C.
0

nA
nA
nA/°C

1750
±2.7
±2.0

NOTES:

6-2

1500
700
3.3
30

4.0

2.0
80
400
1.0

±5.0
±3.5

kn

500
6.7
120

10

s

v
dB

200
5.0
90

2.5

1 kHz
Rs
2 Im, fV+ = 12V, v- = -6V tov- = -3V
v+ = 6 v.
Rs S 2 kn
RL 2 100 k!1, Vout = ±5.0 V
RL 2 100 kn, Vout = ±2.5 V
RL 2 100 kn
RL 2 10 Im
TA= +125°C, Vout = 0
TA= -55°C, v,., = 0
TA= +125°C, Vout = 0
TA= -55°C, Vout = 0

+0.5
100

3.0

6.0
70

mV
nA
µA

6000

s TA s + 125°C:s

TA= -55°C

3.0
500
3.5

100
3600

Rs
2 kn
Rs= 50 n,
TA= 25°C to TA= +125°C
Rs= 50 n,
TA= 25°C to TA= -55°C
TA= +125°C
TA= -55°C
TA=25°CtoTA= +125°C

s

22
-1.5
80

+0.5

UNITS

3.3
3.9
30
35

v
v
mA
mA
mW
mW

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA702A
TYPICAL PERFORMANCE CURVESVOLTAGE TRANSFER
CHARACTERISTIC

VOLTAGE TRANSFER
CHARACTERISTIC
3.o~~~~~~?LJ~V~~

4200

2.01---'e-----l~TA_'-~55_'C_,_t--,_::y_u~-'--'-~
I !j( °"TA•125'C]j_>
TA•25'C~ 1.0 l--l-->----<---+--+1r._--H-+--+~~--<,g Ot---r-+-+-+--r-+--t---t---+--t~-2 1--1--t--+---hT[_'f-+-+--+--t----t--1-

I

R~1001a4-6 .___.....__.____..-+___.___._-+--_.__-'-~-1-5-3
INPUT VOLTAGE - mv~,_

VOLTAGE GAIN
AS AFUNCTION OF
AMBIENT TEMPERATURE
T

~

3800

z

'

-3.0 '---'--'---'---'---'---'--_i..___l'--'--'
-2
-10
-6
10
INPUT VOLTAGE -mv

2200

~

~

g
... 3400v•~ +12V __.
v·•-6V'\,~ 3000

'\,

>

'\,

§-1.0 1--1--t--+-+l[_H-+-+--+--t----t--1
-2.0

1·~ka

'~

v'•+6vrl-RL • 100ka i--.i+IL-+---+- v·· -3V 1--

VOLTAGE GAIN
AS AFUNCTION OF
AMBIENT TEMPERATURE

~

2600

-60

-20

20
60
TEMPERATURE -'C

100

140

INPUT OFFSET CURRENT
AS AFUNCTION OF
AMBIENT TEMPERATURE

INPUT BIAS CURRENT
AS AFUNCTION OF
AMBIENT TEMPERATURE

1100
v•=+6V

1000...g...

~

~ 900

~

v··-3v-!"--.
~

3001--1"-...P<-11--t--+--+--+-+-+-+--I

I'

""" ~

800

'\
700

1001--1--

~

600
~

~

20
60
TEMPERATURE - 'C

100

~

v•·~
~
v· • -3V
I-\--,._ -;o'---'--'---'---'--'---'--'---'---'--'

o'---'--''--'---'--'---'-+-+-+-'TEMPERATURE-'C

TEMPERATURE- •c

COMMON MODE REJECTION RATIOAS AFUNCTION OF
AMBIENT TEMPERATURE

POWER SUPPLY CURRENT
AS AFUNCTION OF
AMBIENT TEMPERATURE-60

SUPPLY VOLTAGE REJECTION RATIOAS A FUNCTION OF
AMBIENT TEMPERATURE

-20

20

60

100

140

-60

-20

20

60

100

160

105
Rs!!i2ko>~~901-->----<---+--+--+--+-+-+--+---i~8of---+-+--t--t-:.J;.....-fi..-==---t+.---+-1
~
~
~70
~
~ I _,.V
~

g

i

.z

100

~

95

~

IZ

""

I

90

v+ = +6VH~v;_ • -3 v -+--+--+-+--!---<---+

85
60 f------jf------1---t--+--+-+-+-+--+---i

50 .___.....__.____..-+--'---'--+---'--'-~
-60
-20
20
60
100
140

80
-60

-20

100

TEMPERATURE - 'C

20
60
TEMPERATURE - 'C

INPUT RESISTANCEAS A FUNCTION OF
AMBIENT TEMPERATURE

OUTPUT RESISTANCE
AS AFUNCTION OF
AMBIENT TEMPERATURE

500

::s.:

140
TEMPERATURE -'C

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
LOAD RESISTANCE
14~~~~1~~~~~~

1

400 1--1\,.1-'<-l--+-+-+--+--+--+---+-~

.'\I

\

v•=+6V'),.._v- i_:-3 v+--+--1--1--1

300 l-"~H-+-""l-J..t.-....+r---+-+-+--+--1

200

I~~~.~.f~12::-~---t;::)::=l::::t::tl

1--+- v-. - 6 v -+---+---+--+--+--I
100
10 '---'---'---'-+--'---'---'-..,..._,.-'-~
-60
-20
20
60
100
140
TEMPERATURE - 'C

1--+-+--+--+-II_,_-+-+-1--+----io~~~~~__._~~~~

-60

-20

20
60
TEMPERATURE-'C

6-3

100

140

100

1k
10k
LOAD RESISTANCE - ll

100k

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA702A
TYPICAL PERFORMANCE CURVESVOLTAGE GA.IN
AS A FUNCTION OF
SUPPLY VOLTAGES~..........~~~~~~~~~

3.0

1-+--+-+-+-+-+--+-+TA~ Joe f-

4000 1---+---+--+--+-+-+---+--+--+-+-t--i..~ 30001---+--+-+-+-+-+--+-+-__.Ll+-v-+-1y!20001-+--+-+-+..~kd4V1--+-+-+-+-+--I>

vr

INPUT OFFSET CURRENTAS A FUNCTION OF
SUPPLY VOLTAGESINPUT BIAS CURRENTAS A FUNCTION OF
SUPPLY VOLTAGES

~

.

c

1-+-+--+-+-!-+-+--+--+

!i'

i 2.0

,,.i....-r..

B.......~

11.5!!!

100 1--+-t--+-+-+-+---+--+-+-+-t--I.i.-i-r

50 t--t-+--+-+-!-+-+-+-+--+--+-t1.0

lo._.._.__.__,_....__.._.__.__,_....__._.
+6

+8

+10

-3

-4

-5

T7• Joe200 1---+-t--+-+-+-+---+--+-+-+-t--I

2.5~

1000 .-..---+--+--+-+-+---+--+--+-+-t--i.........~~..-i-r---.-~~~~~o~A•25°Co._.._.__._..__,___.___.__._....__.._._~

0.5

+12
-6

+12
-6

SUPPLY VOLTAGES -V

+8
+10
-4
-5
SUPPLY VOLTAGES-V

INPUT VOLTAGE RANGEAS A FUNCTION OF
SUPPLY VOLTAGESOUTPUT VOLTAGE SWING
AS A FUNCTION OF
SUPPLY VOLTAGES

+6
-3

+8
-4

+6

-3

+10
-5

+12
-6

SUPPLY VOLTAGES -V

SUPPLY CURRENTAS A FUNCTION OF
SUPPLY VOLTAGES
1--+--+--+-+-+--+--<--+-+~·~~

2._.._.__.__,_._.__.__.__,_....__._.

-4 L......1..--'-..J........JL....L-L-..L.......l--J...-'N--L.:1'...,,..
+6
+8
+10
+12
~
-4
~
-6
SUPPLY VOLTAGES-V

+8

+6

-3

+10

1~~~~~~-+-~~~

+12
-6

-4
-5
SUPPLY VOLTAGES·V-3

100v•-:1:121

Lr-Y"•·6V~11..

~ ., 1~·;1t-~l-+-H+-~~c+-Hft--T~~~+++-~l\rl-t-tt---1

f--TA• 25"C~>2>-+-+-++--+-"-•-1'.f--t-1';.,,+-+-++tt---1

...'
5l

~>-+-+++--+-+-+->:~•c+-+-H>l-t--+-t-H-1

i!;

~

~

6D '--L.J..J.J..-'-..L...W~-'-L..lol....-'---1....U.J-'
lOOk
lM
lk
10k
1011
FREQUENCY - Hz

~

~0.5

0.2

0.1

+12
-6

SLEW RAT~AS A FUNCTION OF
CLOSED-LOOP VOLTAGE GAIN
!LEAD-LAG COMPENSATION!

10
TA'25°C

100 f-+..c,t+-+-~+-t-kHt-+-IH+i--1+10-5

SUPPLY VOLTAGES-V

SLEW RATEAS A FUNCTION OF
CLOSED-LOOP VOLTAGE GAIN
(LAG COMPENSATION!

COMMON MODE REJECTION RATIOAS A FUNCTION OF
FREQUENCY

+8
-4

+6

~

IL

L

z

50

P'
~20

>

...'

i 10

•
~

5

LL
v•=+12V
v-·-6V TAj_5"C
1

10

1

20

50

100

10

1

CLOSED-LOOP VOLTAGE GAIN

20

50

100

CLOSED-LOOP VOLTAGE GAIN

TRANSIENT RESPONSE TEST CIRCUITSUNITY-GAIN AMPLIFIER!LAG COMPENSATION!

X100 AMPLIFIER(LEAD COMPENSATION!

2kQ

TRANSIENT RESPONSE

. 5kQ
i.2

i.o

oJJ;6
T

90'11.

:::::==1-===============
0.4 ~---+--+--+---+---+---<----<

0.2
O

1

10~ RISETIME
TIME

6-4

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA702A
DEFIN1TION OF TERMS
INPUT OFFSET VOLTAGE- That voltage which must be applied between the input terminals to obtain zero output voltage. The input offset voltage
may also be defined for the case where two equal resistances are inserted in series with the input leads.
INPUT OFFSET CURRENT - The difference in the currents into the two input terminals with the output at zero volts.
INPUT RESISTANCE- The resistance looking into either input terminal with the other grounded.
INPUT BIAS CURRENT - The average of the two input currents.
INPUT VOLTAGE RANGE- The range of voltage which, if exceeded on either input terminal, could cause the amplifier to cease functioning properly.
INPUT COMMON MODE REJECTION RATIO- The ratio of the input voltage range to the maximum change in input offset voltage over this range.
SUPPLY VOLTAGE REJECTION RATIO- The ratio of the change in input offset voltage to the change in supply voltage producing it.
LARGE-SIGNAL VOLTAGE GAIN- The ratio of the maximum output voltage swing with load to the change in input voltage required to drive theoutput from zero to this voltage.
OUTPUT VOLTAGE.SWING- The peak output swing, referred to zero, that can be obtained without clipping.
OUTPUT RESISTANCE- The resistance seen looking into the output term in al with the output at null. This parameter is defined only under small
signal conditions at frequencies above a few hundred cycles to eliminate the influence of drift and thermal feedback.
POWER CONSUMPTION - The DC power required to operate the amplifier with the output at zero and with no load current.
TRANSIENT RESPONSE- The closed-loop step.function response of the amplifier under small-signal conditions.
PEAK OUTPUT CURRENT - The maximum current that may flow in the output load without causing damage to the unit.

TYPICAL PERFORMANCE CURVESFREQUENCY RESPONSE FOR
VARIOUS CLOSED-LOOP GAINS(LAG COMPENSATION)FREQUENCY RESPONSE FOR
VARIOUS CLOSED-LOOP GAINS(LEAD-LAG COMPENSATION)FREQUENCY RESPONSE
WITH CONSERVATIVECOMPENSATION NETWORK

....

"'

~~l--i'"-T-T'T""'-'i-...:....r~...+--+--1.d--+J

§?

lM

lOM

50M

FREQUENCY - Hz

FREQUENCY - Hz

FREQUENCY - Hz

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
FREQUENCY FOR VARIOUS
LAG COMPENSATION NETWORKSFREQUENCY COMPENSATIONCIRCUITSOUTPUT VOLTAGE SWING
AS A FUNCTION OF FREQUENCYWITH LEAD-LAG COMPENSATION(Refer to Fairchild APP-117 forfurther details.)

14v+=·+l2Vy-. -6V -1

12

--+-I
10

~

TA• +25'C

~

"'

4

LAG
COMPENSATION

LEAD-LAGCOMPENSATION

0
100k

~

~

lM

lOM

FREQUENCY - Hz

FREQUENCY - Hz

6-5

lOOM

µA702B
HIGH GAIN, WIDEBAND DC AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITS• 5 mV MAXIMUM OFFSET VOLTAGE• 2000 MINIMUM VOLTAGE GAIN
• 20 µVf°C MAXIMUM OFFSET VOLTAGE DRIFTPHYSICAL DIMENSIONS(TYPICAL FLAT PACKAGE)(TOP VIEW)

GENERAL DESCRIPTION - The µA702B is a complete DC amplifier constructed on a single silicon chip,using the Fairchild Planar* epitaxial process. It is intended for use as an operational amplifier in miniaturized
analog computers, as a precision instrumentation amplifier, or in other applications requiring a feedback
amplifier useful from DC to 30 MHz.
For improved specifications, see µA702A data sheet.

1~r----,_ _ABSOLUTE MAXIMUM RATINGS
Voltage Between v+ and v- Terminals
Peak Output Current
Differential Input Voltage
Input Voltage
Internal Power Dissipation (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec.)

21 v
50 mA
±5.0V
+1.5 Vto -6.0 V
200mW-55° Cto +125°C-65°C to +I50°C
300°C

r--J
_J_

~.060

!

ORDER PART NO.

U3H7702313

SCHEMATIC DIAGRAM

v•

.,

8kQ

.,

•1
2k0

CONNECTION .DIAGRAM

2kQ

I
GROUND 0--1----4--1----~••NO
CONNECTION

3.4k0

INPUT

y+

NO
CONNECTiClll

GROUND

INVERTING 2

10•

INVERTINGOUTPUT

NON-INVE~NT~~~ 0.3- - - - 1 1 - - - - - 'INPUT .--''I...._,----,

•12

2.6kQ

•10
240Q

••

2.4kQ

••

4800

y·

•u

2400

(TOP VIEW)NOTE 1: Derate linearly at 4.4 mW!°C for case temperatures above + 115°C; deratelinearly at 3.3 mW/ °C for ambient temperatures above + 100°C.

*Planar is a patented Fairchild process.

F.AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-6

A DlVIS!ON OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A7028
ELECTRICAL CHARACTERISTICS(TA = 25°C unless otherwise specified)

PARAMETER{see definitions)
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Input Voltage Range
Common Mode Rejection Ratio
Large-Signal Voltage Gain
Output Resistance
Supply Current
Power Consumption
Transient Response {unity gain)
Risetime
OvershootTransient·Response { x 100 gain)

V+ = 12.0 V, v- = -6.0 V
MIN.
TYP.
MAX.

CONDITIONS

Rs S 2 kn

10
-4.0
70
2000

Rs S 2 kn,
f S 1 kHzR, ~ 100 kn, v••• = ±5.0 v
R, ~ 100 kn, v••• = ±2.5 vv••• = 0v.,. = 0
C, = 0.01 µF,
R, S 100 kn,

Input Offset Voltage
Average Temperature Coefficientof Input Offset Voltage
Input Offset Current
Average Temperature Coefficientof Input Offset Current
Input Bias Current
Input ResistanceCommon Mode Rejection Ratio
Supply Voltage Rejection Ratio

16
-1.5
70

6.0
2.0
5.0
+0.5

mV
µA
µA
kn
v
dB

92
3400

6000

200
5.0
90

600
6.7
120

25
10

120'
50

ns

10
20

30
40

ns

92
800
300
2.1
19

1500
800
3.3
30

n
mA
mW

%

R, ~ 100 kn,

s T,. s +70°C:
Rs s 2 kn%

6.5

Rs= 50 n,
T,. = +70°C toT,. = 0°c

5.0T,. = 25°C to T,. = +70°C
T,. = 25°C to T,. = 0°C
TA= 0°C

4.0
6.0
4.0
18
86

20

7.5

2.5

6.0
65

s

Rs
2 kn, f
1 kHz
v+ = 12 V, v- = 6 V tov+ = 6 v, v- = 3 v
Rs
2 kn
R, ~ 100 kn, v... = ±5.0 v
R, ~ 100 kn, v••• = ±2.5 v

90s

Large-Signal Voltage Gain

+0.5

1.7
0.3
1.5
55

UNITS

R, = 20n
V;, = 10 mVc, S 100 pF
C, = 50 pF,
V;, = 1 mV

s

5.0
2.0
7.5

500

Risetime
OvershootThe following specifications apply for 0°C

1.5
0.5
2.5
32

V+ = 6.0 V, v- = -3.0 V
MIN.
TYP.
MAX.

1500

10

20
12
9.0
65
300

3.0
5.5
2.7
27
86
90

7.5

mV

25

µV/°C

2.5
8.0
18
8

µA
nA/°C
nA/°C
µA
kn
dB

300

µV/V

7000
1750

400

s TA s +125°C:
Rs s 2 kfl

The following specifications apply for -55°C
Input Offset Voltage
Input Offset Current
Input Bias Current
Input ResistanceCommon Mode Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
Supply Current
Power Consumption

0.2
1.2
5.5

TA= +125°c
TA "."-55°C
TA=-55°c

s

3.0
60
1200

s

Rs
2 kn, f
1 kHz
RL ~ 100 kf!, Vout = ±5.0 V
RL ~ 100 kf!, vout = ±2.5 v
RL ~ 100 ki2
RL ~ 10 kn
TA= +125°C, vout = 0
TA= ·-55°C, voul = 0
TA= +125°C, voul = 0
TA = -55°C, vout = 0

±5.0
±3.5

6-7

7.5
2.0
4.0
20
4.0
60

80

±5.3
±4.0
4.4
5.0
80
90

0.14
0.8
3.4

300
±2.5
±1.5
6.7
7.5
120
135

8.0
2.0
4.0
15

mV
µA
µA
µA
kn

80

dB

±2.7
±2.0
1.7
2.1
15

v
v
mA
mA
mW
mW

~9

3.3
3.9
30
35

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA7028
TYPICAL PERFORMANCE CURVES

6.0

TA • O'C
v+ • 12VI
v- • -6.0 v t-

4.0

7li

3.0

~ TA • 70°C

2.0

IA •

1.0

~TA •70'C

rT

rT

rf

-I

-1.0

'fl.

Rl • lOkQ-4.0
f-Rl • IOOkQ
-6.0
-5.0

1::-. 25'C+-

~

_1
-2.0

///~

v- • -3.0 v~5'c +--

3800,--.--,.---.--,.---1,.---.---.
f---+--l---+--1---~- : '.!.~ v-/"fl_v+ - 6.!! v j-TA•O'.C

l//L_~

ti

2.0

VOLTAGE GAIN
AS A FUNCTION OF
AMBIENT TEMPERATURE

VOLTAGE TRANSFER
CHARACTERISTIC

VOLTAGE TRANSFER
CHARACTERISTIC

-1.0
1.0
INPUT VOLTAGE - mv

3.0

5.0

1'
JOOOl---+--+--+--+--+--µ.,,.--l

'

-2.0

7j

71

2800L--+-_...__.__...__,__...__,

-3.0
-IO

VOLTAGE GAIN
AS A FUNCTION OF
AMBIENT TEMPERATURE

-6.0

-2.0
2.0
INPUT VOLT AGE. - mv

IO

6.0

0

30

40

50

60

70

TEMPERATURE - 'C

INPUT OFFSET CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

INPUT BIAS CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE~-~--~---7--1--20

10

3.5-----------

l---+---l--+--+-v_ · 6.o v _V • -3.0V

800 l---+--1---+--l---+---ll---l-2

y+. 12V

150 l---+--1---+--l'-....1--'.,._---'1---1~---i-.-

2 o 1---1----+- v' · 6.o v. I'--.

v- • -3.0V

-...,

-

1001---+--t---+--1---+----'t--~l.51-+K----11""'7-..+--1-+----1----l200 I---+- v' • :.o v -tt----t-1---;--'T"'"-+.=-iv- • -3.0 v-....,~...___.__.___.__.___.____..__~

1.0 ....__,__.___,__.___,____.._____.

01---'----''---'----'~-'----'-~

t-l-.

010203040506010
TEMPERATURE - 'C

SUPPLY VOLTAGE REJECTION RATIOAS A FUNCTION OF
AMBIENT TEMPERATURE

0

10

20

30
40
5060
TEMPERATURE - 'C

96

?,

~

~

~

,J--"

..-!--"

ool--t--:;;,....,::+-+--t--+-~~i--~.j..-/~+---1---+~+--+--

2~

OOt---+----t--+---+-+---+--

88

15 .___.____._....____.__...____J__86010203040506010

5.0

1.0
0

I020

3040
506070TEMPERATURE - "C

400 <---+--+---1-v• · 6.o v ->---+----<v- • -3.0V

0

10

20

3040
5060
TEMPERATURE - "C

~~

12 l-

f101-

-

~.-.RY.L-~A702B+

11R

JL

100 .....__,____,_ v-

v-1··6.0 V.____.____._~_,__.....__.___,

01020304050
TEMPERATURE - °C

1k

lOk

_l

v•· 12vi-v'~v
20 l---+--t---+10~ ~,k-'-6Vv-·~

200r---

70

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
LOAD RESISTANCE
14 ,--..,........,.1.,..-.,..-..,......,....._ _100 t--- y+. 6.0 v -+----+-+---+---<-

t--t--

7

2.0

1

50

-

V+•6,0Vv- • -3.0V

3.0

OUTPUT RESISTANCEAS A FUNCTION OF
AMBIENT TEMPERATURE~~----------

2()()t---+---+--+---+--+---+---<

v-. .o v

4.0"-t-- ........
t--......

TEMPERATURE - 'C

INPUT RESISTANCEAS A FUNCTION OF
AMBIENT TEMPERATURE

17
v•-12 v

00~

POWER SUPPLY CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE
6.0

94~,.. ~t---+----t--+---+-+---+-­~TEMfltRATURE • °C

R5 ·::: 2.0 kQ

95 l---t---t-+--+-+-.,_.""...-1=-l0

OI0203040506010

70

COMMON MODE REJECTION RATIOAS A FUNCTION OF
AMBIENT TEMPERATURE

R5:52.0kQ"'·6.0 v +---+---+

60

10

1·0 v-+---+-+---!

o.___,___._....__,__...____.____.
0

IO

20

30
40
50
TEMPERATURE - °C

6-8

60

10

100

LOAD RESISTANCE - o

100k

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA702B
TYPICAL PERFORMANCE CURVESVOLTAGE GAIN
AS A FUNCTION OF
SUPPLY VOLTAGESINPUT OFFSET CURRENTAS A FUNCTION OF
SUPPLY VOLTAGESINPUT BIAS CURRENTAS A FUNCTION OF
SUPPLY VOLTAGES
600

m>t-+-+-+--+-+-t-+-+--+--+-+--iTA • 25°C

500

.).-1
2.0 H-+-+--t-H"'"1'<=t-+--t-H
~

1---"

400

...J.-1300~-6~-~.8:-'"--'--+-.~10__._~~.12
-3

-4

-

s

-6

1.0 t-+-+-+--+-+--11-+-+--t--+-+-t

200

o.s L--J.---'--'--'---'---''-'---'--'--'-..__.
+12
+8
+10
+6
-3
-4
- s
- 6

100

I---

...v

+6

+8

-3

+10

+12
- 6

- s

-4

SUPPLY VOLTAGES - V

SUPPLY VOLTAGES -V

SUPPLY VOLTAGES - V

INPUT VOLTAGE RANGEAS A FUNCTION OF
SUPPLY VOLTAGESOUTPUT VOLTAGE SWING
AS A FUNCTION OF
SUPPLY VOLTAGESSUPPLY CURRENTAS A FUNCTION OF
SUPPLY VOLTAGES

l.O ,.--,_,..-,---,-PO-,-JSl"T-IJ.,-El-rl~-IT-.---,--.-,.--,

10 t--t--+-+--+-+-t-+-+-+---tP""7"!'-bd-;
Rl-lOOkQ~-LO +-+--+--+--+--+-+-+-+--+--+-+-<~-+--+-~-~-+--+-b..~f'-+-t:::::._

-4.0
+6
"3

+8
-4

+12

+10

-s

- 6

k'.'.!7l"J 1--1

8.0 H-+-+--+k:'.'.-+l-"""~q-+-1-,....,--+H-l:...l

6.0~

~"11r
-3.0 1--1-+-+-+-+-t-~;:.:_~+i-....-+-+-+-I

s.o t-+--+--+--+-+--1--+-+--+-+-+--.1

yVi\:;:il.....f"""

~

r

3.o

Rl - IOkQ t-t-1

I

t--t-+--+->""~-+v-+-+-+--1--+-+--1~~

4.0 l-""+-+-+-+-~e--+-1--+-+-+-I

2.0 t-+--+--+--+-+--1--+-+--+-+-+-1

2.0 L--J.---1...--'--'---'---''-'---'--'--'-..__.
+12
+8
+10
+6
- 6
-3
-4
- s

1.0 ~-+-~~~~__.___._....._..__.
+6
+8
+10
+12
-3
-4
- s
- 6

SUPPLY VOLTAGES - V

SUPPLY VOLTAGES - V

SUPPLY VOLTAGES - V

COMMON MODE REJECTION RATIOAS A FUNCTION OF
FREQUENCY

SLEW RATEAS A FUNCTION OF
CLOSED-LOOP VOLTAGE GAIN
(LAG COMPENSATION)SLEW RATEAS A FUNCTION OF
CLOSED-LOOP VOLTAGE GAIN
tLEAD-LAG COMPENSATION)

10

100

_LJ

v• •112v 1
5.0 t- v· • -6.0V

f- TA• 2S°C

2.0

lL

l.O

..........

so~~__._~~-+-~~~

I.Ok

!Ok

lOOk
I.OM
FREQUENCY - Hz

!OM

0.1

10

~

o.s
0.2

.L'l

0

~~: ~~~ov-1

2.0

[71
I

l

5.0

~

TA• 25°C

l.O

10
20
CLOSED- LOOP VOLTAGE GAIN

50

I

100

10
20
CLOSED-LOOP VOLTAGE GAIN

50

100

TRANSIENT RESPONSE TEST CIRCUITSUNITY-GAIN AMPLIFIER(LAG COMPENSATION)
2kQ

TRANSIENT RESPONSE

X100 AMPLIFIER(LEAD COMPENSATION)
5kQ

lZ
1.0

OV~~
r

90%

:.: :=:=:17::=:=::::::::=:
0.2

~

t

lO;;r-t---1 RISETIMEOf--F--f---f---f---~--1--1--1----1

TIME

6-9

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A702B
DEFINITION OF TERMS
INPUT OFFSET VOLTAGE- That voltage which must be applied between the input terminals to obtain zero output voltage. The input offset voltage
may also be defined for the case where two equal resistances are inserted in series with the input leads.
INPUT OFFSET CURRENT - The difference in the currents into the two input terminals with the output at zero volts.
INPUT RESISTANCE- The resistance looking into either input terminal with the other grounded.
INPUT BIAS CURRENT - The average of the two input currents.
INPUT VOLTAGE RANGE- The range of voltage which, if exceeded on either input terminal, could cause the amplifier to cease functioning properly.
INPUT COMMON MODE REJECTION RATIO - The ratio of the input voltage range to the maximum change in input offset voltage over this range.
SUPPLY VOLTAGE REJECTION RATIO - The ratio of the change in input offset voltage to the change in supply voltage producing it.
LARGE-SIGNAL VOLTAGE GAIN - The ratio of the maximum output voltage swing with load to the change in input voltage required to drive theoutput from zero to this voltage.
OUTPUT VOLTAGE SWING - The peak output swing, referred to zero, that can be obtained without clipping.
OUTPUT RESISTANCE - The resistance seen looking into the output term in al with the output at null. This parameter is defined only under small
signal conditions at frequencies above a few hundred cycles to eliminate the influence of drift and thermal feedback.
POWER CONSUMPTION - The DC power required to operate the amplifier with the output at zero and with no load current.
TRANSIENT RESPONSE- The closed-loop step-function response of the amplifier under small-signal conditions.
PEAK OUTPUT CURRENT - The maximum current that may flow in the output load without causing damage to the unit.

TYPICAL PERFORMANCE CURVESFREQUENCY RESPONSE FOR
VARIOUS CLOSED-LOOP GAINS!LAG COMPENSATION)FREQUENCY RESPONSE
WITH CONSERVATIVECOMPENSATION NETWORKFREQUENCY RESPONSE FOR
VARIOUS CLOSED-LOOP GAINS!LEAD-LAG COMPENSATION)

"'

'll

~

~4or--,,...,-,--,----;-t--1-t:-~--r-t-tiI

z40t--,.....,_"1'1--t----;r-t-tt-.......,..._..~H

~

...~

...
"'

~2or-,,...,-,--,----,--,-~;;::t---r-t-ti
g~201--+-+++--+--<f-+-++--+--+-+--~

J lJl lk .li lOk

-20
100

lOOk

lM

N

lOM

FREQUENCY - Hz

FREQUENCY - Hz

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
FREQUENCY FOR VARIOUS
I.AG COMPENSATION NETWORKSFREQUENCY COMPENSATION CIRCUITS

lM

lOM

OUTPUT VOLTAGE SWING
AS A FUNCTION OF FREQUENCYWITH LEAD,LAG COMPENSATION(Refer to Fairchild APP-117 for further details)

14

14 ~~~~~~~~V-,-+--12-V___,y+r. +12V
y-. -6V -I

v- • -6.0V
12

12 1---t-++1--+-H-tt--+-+-H+-T A• 25'C~

Rl • lOOkQ

~

10

~-

8.0

I .,

TA • +25°C

J".,

'1'

f\

c,

6.0

I\

4.0

LEAD-LAGCOMPENSATIONLAGCOMPENSATION
lk

!Ok

!OOk

50M

FREQUENCY - HzIMFREQUENCY - Hz

~

0

lOOk

lM

lOM

FREQUENCY - Hz

6-10

lOOM

1.1A702C
HIGH GAIN, WIDEBAND DC AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITS• IMPROVED SPECIFICATIONS• 5 mV MAXIMUM OFFSET VOLTAGE• 2000 MINIMUM VOLTAGE GAIN
• 20 µV/°C MAXIMU~ OFFSET VOLTAGE DRIFT
GENERAL DESCRIPTION- The µA702C is a complete DC amplifier constructed on a single silicon chip, using the
Fairchild Planar* epitaxial process. It is intended for use as an operational amplifier in miniaturized analog computers, as a precision instrumentation amplifier, or in other applications requiring a feedback amplifier useful from DC
to 30 MHz.
For full temperature range operation (-55°C to + 125°C) see µA702A data sheet.

.500 MIN.

8 Leads.019.016

ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and v- Terminals
Peak Output Current
Differential Input Voltage
Input Voltage
Internal Power Dissipation [Note 11
Operating Temperatur.e Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec.)

21 v
50mA
±5.0V
+ 1.5 Vto - 6.0 V
300mW
0°c to +70°C- 65°C to + 150°C
300°C

.034
.028

~~

NOTES: Dimensions as per latest J-10 committee
Alld1mens1onsininches
Leadsaregold-platedKovar
Packa1ewei1ht1sl.22grams

ORDER PART NO. U5B770239X

SCHEMATIC DIAGRAM

T0-99 CONNECTION DIAGRAMv+(TOP VIEW)v+
LEAD ) EXTERNALFREQUENCYCOMPENSATION

Rs

3.4kQ

l

GROUND<>---l---_...--4----~- - - - 1 - - - 0 LAG

6 LA;

INVERTING 2
INPUTFREQUENCYCOMPENSATIONLEAD

o----<>OUTPUT

v·

R12
2.6kQ

R10
240Q

Rs

2.4kQ

Ru

NOTE: Pin 4 connected to can.

240Q

v
NOTES:(1) Rating applies for ambient temperatures lo +1o•c.
(2) For Flat Package see µA702B data sheet.

• Planar is a patented Fairchild process.

FAIRCHILCJ
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-11

SEMICONDUCTORA DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A702C

ELECTRICAL CHARACTERISTICS, PARAMETER(see definitions)
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Input Voltage Range
Common Mode Rejection Ratio
Large-Signal Voltage Gain
Output Resistance
Supply Current
Power Consumption
Transient Response (unity gain)
Risetime
OvershootTransient Response ( x 100 gain)(TA = 25°C unless otherwise specified)
CONDITIONS

V• = 12.0 V, v- = -6.0 V
MIN.
TYP.
MAX.

v• = 6.0 V, v- = -3.0 V
MIN.
TYP.
MAX.

1.5
0,5
2.5
32

1.7
0.3
1.5
55

Rs s 2 kn

Rs s 2 kf!,
RL :::: 100 kf!,
R, 2 100 kn,

f s 1 kHzv••• = ±5.0 v
v••• = ±2.5 v

10
-4.0
70
2000

c, s 100 pf
c, = 50 pf,

+0.5

16
-1.5
70

6.0
2.0
5.0

mV
µA
µA
kn

+0.5

v

92
3400

6000

200
5.0
90

600
6.7
120

25
10

120
50

ns

10
20

30
40

ns

500

v••• = 0v... = 0
C, = 0.01 µf,
RL s 100 kn,

5.0
2.0
7.5

UNITS

92
800
3PO
2.1
19

dB
1500
800
3.3
30

'n
mA
mW

R, = 20n
V,, = 10 mV%R, 2 100 kn,

V,, = 1 mV
Risetime
Overshoot%The following specifications apply for 0°C s TA s + 70°C:
Input Qffset Voltage
Average Temperature Coefficientof Input Offset Voltage
Input Offset Current
Average Terllperature Coefficientof Input Offset Current
Input Bias Current
Input ResistanceCommon Mode Rejection Ratio
Supply Voltage Rejection Ratio. Large-Signal Voltage Gain
Output Voltage Swing
Supply Current
Power Consumption

Rs s 2 kn
Rs= 50-n,TA= +70°C to TA= 0°C

6.5
5.0

TA= 25°C to T... = +70°C
T... = 25°C to T,, = 0°C
TA = 0°C
Rs s 2 kf!, f S 1 kHz
v· = 12 v, v- = 6 v toV• = 6 V, y- = 3 V
Rs S 2kn
R, 2 100 kn, v... = ±5.0 v
R, 2 100 kn, v••• = ±2.5 v
RL ;::: 100 kn
R, 2 10 kf!
v... = 0v••• = 0

6.0
65

4.0
6.0
4.0
18
86
90

1500
±5.0
±3.5

6-12

7.5

20

7.5

2.5
10
20
12
9.0
65
300

3.0
5.5
2.7
27
86
90

mV

25

µV/°C

2.5
8.0
18
8

µA
nA/°C
nA/°C
µA
kn
dB

300

µV/V

7000
±5.3
±4.0
5.0
90

400
±2.5
±1.5
7.0
125

1750
±2.7
±2.0
2.1
19

v
v
3.9
35

mA
mW

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA702C
TYPICAL PERFORMANCE CURVESC~ARACTERISTIC

3.0

I-~:

-

2.0

_i

~

-l.O

'

-2.0
-6.o~-----~~~~
-5.0
-3.0
-1.0
1.0
3.0
5.0

900

. ~~- t-If

3600

cs;

25°C

01--1--t--t--t-..,-,f-t-t-t-+----i~ -2.0 t--t--t--t--Htf-+---+---+---+---+--1

t---+---+---1---+--v: • 12 v ___,
V • ·6.0V'1$,_ITA • 7ffC

l.O~

3800~~~-~~-~T-~T~~

V • -3.0V~

VOLTAGE GAIN
AS A FUNCTION OF
AMBIENT TEMPERATURE

VOLTAGE TRANSFER
CHARACTERISTIC
fl[_
6.0 v 1-TA·~C

VOLTAGE TRANSFER

34001---+-"'-4t-..._,.,_-+---l--+--+---l

'b..
"'-

3200t---+---+--+---+~_,,,,r+----+---<

f

ll

-l.O

-10

-6.0

"'h

31XXlt---+--+-+--+-t--~~'t-...i-3'o.~
~

-2.0

2.0

2800~~~-~--+--t--~~

10

6.0

0

1020

3040

506070INPUT VOLTAGE - mv

INPUT VOLTAGE - mV

TEMPERATURE - °C

VOLTAGE GAIN
AS A FUNCTION OF
AMBIENT TEMPERATURE

INPUT BIAS CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

INPUT OFFSEt CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

t---+---+---1---+--v! •6.o~ _V • -l.OV

l.O l'-,...._-+--4--+--+--+----1---1

800 l---+--4--+--+--+---+--I~~

t---+--+b.._,.,,,,,+~1·0 v +--+---I

2.5

--~

7501---T---lt---T---l~~~--t--t

700t---+---+t---+---+--+----+~--'Iv•= 12V

v>12v

2.0

600"'

L~.ov

N

v•·6.0V +--.,-+r-...---"',....dv··-l.OV-,~

N7

l.51---+--f""-dNt---it---+--+---i~9~~10~~20,._~30r-~40-~50-~60__.ro

20

30

40

50

60

ro

10

20

30

40

50

60

TEMPERATURE - °C

TEMPERATURE - °C

TEMPERATURE • °C

SUPPLY VOLTAGE REJECTION RATIO
AS:A FUNCTION OF
AMBIEtff TEMPERATURECOMMON MODE REJECTION RATIOAS A FUNCTION OF
AMBIENT TEMPERATURE

POWER SUPPLY CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

100

96

D_

90

-

.......

i----

.A-

v
!-""

6.0
Rs 5- 2.0 kQ

Rs!2.0kQ

95

94

<

e

92

-r-.

~

90

85

80

88

75

86

o

10

20

30

•

50

60

ro

!!]

['--....

o

10

20

30

40

50

60

ro

~

~ 3.0

v+·6.0V"'zv··-l.OV-

1.0010203040506070
TEMPERATURE - °C

INPUT RESISTANCEAS A FUNCTION OF
AMBIENT TEMPERATURE

OUTPUT RESISTANCEAS A FUNCTION OF
AMBIENT TEMPERATURE

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
LOAD RESISTANCE

14

500

v··-l.OV

300

~~
~~

--

~
v•· 12v

~r-

10

i--

20·

30

200

40

t ~A702C-6V

J....-""I

JL

.L1 L
ll
if.

L

~-Tv

17

17 L

v
;..A-'

v+= +12V v-. -6V TA= +25•c---i

v

L

ro

0

o

10

!

30

40

TEMPERATURE - °C

6-13

I---":

2l t:-1v•· 12v

60

k'I

~~

~

L

100

50

1R-i
RL

t--1--

v·i-6.0V

TEMPERATURE - °C

10

_L

r-t--

~+

12 t--

v•.1.ovov·. .ov~ 4.0

TEMPERATURE - °C

y+ .. ~.ov
100 t - v··K-

lO

v+· 12v.

~ 2.0

200

20

..,...__t---

5.0

TEMPERATURE - °C

500

50

ro

50

60

ro

0
100

lk

10k

LOAD RESISTANCE - 11::uu 100k

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A702C
TYPICAL PERFORMANCE CURVESVOLTAGE GAIN
AS A FUNCTION OF
SUPPLY VOLTAGESINPUT OFFSET CURRENTAS A FUNCTION OF
SUPPLY VOLTAGES
TA· 2s c

INPUT BIAS CURRENTAS A FUNCTION OF
SUPPLY VOLTAGES
600

0

mlt-t-+-+-+-t--t-+-+--+-t--tf-i

2.S t-t-+-t-+-t-+-+-+-t-t-+::ot....I-"~ 2.0 H-+-++L..-"-IV--1::~+-t--+-+---l
1l~
~

.Y

looo l-'~"9--+-+-H-+-+-+-H-l

+8

+10

200

o.s L.....J._..._-'-..1........J'--'-_._.....,_...........__._~
+6

-6

+8

-3

+10

100
+6

+12

- s

-4

..J-1

JOO ~

~ 1.0 t-t-+--+-+-t--+-+--+-+--t-+--i

+12

s

-4
SUPPLY VOLTAG<S • V_;....r-vl'"'=l--+-+-+--t-+-+-+-t-t-+-1

1.5

v

SOD

V""""

-6

+8

-3

+12

+10

s

SUPPLY VOLTAGES -V-4
SUPPLY VOLTAG<S - V

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
SUPPLY VOLTAGESSUPPLY CURRENTAS A FUNCTION OF
SUPPLY VOLTAGES

l--f-+-+--+-+-tr-+--+--+--17"'f-~--is.o l--f-+-+--+-+-t-t-+--+--1--1-..1

INPUT VOLTAGE RANGEAS A FUNCTION OF
SUPPLY VOLTAGES- 6

1.0 .---.--..--,---...-p-oJr-.ITl"T.)r_-LI~.-IT~..--.-..--.

>

~

i

-1.0

t--+--+--+--+--~--+--+--+-~--<~~-2.0~~
t--.. ~-+-+-t-t-+-i~,,-3.o t-t-+-+-+-t--t-~-.-Nt-t-+--+--t10~

Rl•lOOkO~s 8.0 f-+-++-+--t--7f"'+-+-t-t-t..i
l~.Y

~

bd"'

~6.0 v y
~

~·:;:
~

v

.....!--'

J.d71z'1!

~ 4.0 t-t-+-+-+-t--+-l"'t-:>'f'-t--+-t--t

~

~

B

k'.j

~ 3.0 t-t-+--+....----+-+---+-+--+-t--t

Rl • lOkO t-+-~ 4.0 """"--++-+--t-+--+-+-l--+-+--1

~

2.0~

k':'.

2.0~--+-~~~~~~--+-~

+8
+10
-4
SUPPLY VOLTAG<S - V

-+126

s

-s

-3

COMMON MODE REJECTION RATIOAS A FUNCTION OF
FREQUENCY

v'·112V I
s.o l-v··-6.0V
t-TA •ZS°C!9. 2.0
1.0"'OI o.s
r-...

\J

~

0.2

50.__._.L.U..._,_J....J..1.L-J.....J....l....__L-...1..J.,J..L.~

l.Ok

10 k

vr

~

100 k
I.OM
FREQUENCY - Hz

!OM

0.1

~
I

+10

-4

-

+12

s

- 6

SUPPLY VOLTAGES - V

SLEW RATEAS A FUNCTION OF
CLOSED-LOOP VOLTAGE GAIN
!LEAD-LAG COMPENSATION)

100.--~~~-.--~~~-

.L1

.LJ

>

+8

-6

SLEW RATEAS A FUNCTION OF
CLOSED-LOOP VOLTAGE GAIN
!LAG COMPENSATION!

10

~

+12

+8
+10
-4
SUPPLY VOLTAGES - V+6.Ll
10 t---+--+-H--t---l--t-11-t-----l[2J

5.0 t---l---t-H--t---l--t-11-t-----lv•-1zv

2.0 1---1--t-1-+---+--+-- v· • -6.ov-l
TA • 25°C

20
10
CLOSED- LOOP VOLTAGE GAi N

50

100

!. Ol'----'--t-1-+--IO'---...J20L-.J._J_J50--'IOO
CLOSED-LOOP VOLTAGE GAi N

TRANSIENT RESPONSE TEST CIRCUITSUNITY-GAIN AMPLIFIER!LAG ,COMPENSATION!

TRANSIENT RESPONSE

X100 AMPLIFIER!LEAD COMPENSATION!

2kQ

5kQ

.:::oJ~1190%:::=:==~===============

0.4 t - - t - - - < l - - + t - - t - - 1 - - 1 - - l - - l - - l - - - I
0.2

~1H

10%

RISETIME

Ot--f--l--t--t--1--1--l--l--t--t

TIME

6-14

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA702C
DEFINITION OF TERMS
INPUT OFFSET VOLTAGE- That voltage which must be applied between the input terminals to obtain zero output voltage. The input offset voltage
may also be defined for the case where two equal resistances are inserted in series with the input leads.
INPUT OFFSET CURRENT - The difference in the currents into the two input terminals with the output at zero volts.
INPUT RESISTANCE - The resistance looking into either input terminal with the other grounded.
INPUT BIAS CURRENT - The average of the two input currents.
INPUT VOLTAGE RANGE- The range of voltage which, if exceeded on either input terminal, could cause the amplifier to cease functioning properly.
INPUT COMMON MODE REJECTION RATIO- The ratio of the input voltage range to the maximum change in input offset voltage over this range.
SUPPLY VOLTAGE REJECTION RATIO- The ratio of the change in input offset voltage to the change in supply voltage producing it.
LARGE-SIGNAL VOLTAGE GAIN - The ratio of the maximum output voltage swing with load to the change in input voltage required to drive theoutput from zero to this voltage.
OUTPUT VOLTAGE SWING - The peak output swing, referred to zero, that can be obtained without clipping.
OUTPUT RESISTANCE - The resistance seen looking into the output term in al with the output at null. This parameter is defined only under small
signal conditions at frequencies above a few hundred cycles to eliminate the influence of drift and thermal feedback.
POWER CONSUMPTION - The DC power required to operate the amplifier with the output at zero and with no load current.
TRANSIENT RESPONSE- The closed-loop step-function response of the amplifier under small-signal conditions.
PEAK OUTPUT CURRENT - The maximum current that may flow in the output load without causing damage to the unit.

TYPICAL PERFORMANCE CURVESFREQUENCY RESPONSE FOR
VARIOUS CLOSED-LOOP GAINS(LAG COMPENSATION)FREQUENCY RESPONSE
WITH CONSERVATIVECOMPENSATION NETWORKFREQUENCY RESPONSE FOR
VARIOUS CLOSED-LOOP GAINS(LEAD-LAG COMPENSATION!

Ill

Ill

3

3

~4oi--,.....,.....,...,..-..,---1-+-o.t:--~-+-t-H!40t-'i"-T-i+--t--++++--t-~rH~ w1--;--,-.,.,..;.-'-r'--T-i-~::::+--++-H
~

-20
100

Jll 1lJ.
lk

10k

100k

lM

N

lOM

FREQUENCY - Hz

FREQUENCY - Hz

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
FREQUENCY FOR VARIOUS
LAG COMPENSATION NETWORKSFREQUENCY COMPENSATION CIRCUITS
14

y+. +12V
12

~
~
c,

-

10

I .,

6.0

50M

lOM

OUTPUT VOLTAGE SWING
AS A FUNCTION OF FREQUENCYWITH LEAD-LAG COMPENSATION(Refer to Fairchild APP-117 for further details)

14 r-r...,..,..,--.--r-..,.,.-....-rTT,--v"""+.12V--.
v· • -6.0V
12 1-+-++1-+----+-+-++--+-+-+++-TA· 25°C
Rl • lOOkQ

8.0

lM

FREQUENCY - Hzbiy-, -6V TA• +25°C

~N

\

4.0

LAG
COMPENSATION

LEAD-LAGCOMPENSATIONFREQUENCY - Hz

~
0
100k

._;
lM

lOM

FREQUENCY - Hz

6-15

lOOM

µA703
RF-IF AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITSThe µA 703 is an RF-IF amplifier constructed on a single silicon

GENERAL DESCRIPTION

chip and is intended for use as a limiting or nonlimiting amplifier, harmonic mixer, or os-

PHYSICAL DIMENSIONS(in accordance with JEDEC T0-99 outline)

cillator to 150 MHz. The low internal feedback of the device insures a higher stability-limited
gain than that available from conventional circuitry. Including the biasing network in the same
package reduces the number of external components required, thereby increasing the reliability and versatility of the device.
ABSOLUTE MAXIMUM RATINGS

Supply Voltage

20 v

Output Collector Voltage

24 v±5.0 v

Voltage Between Input Terminals
Internal Power Dissipation (Note 1)

200 mW

Operating Temperature Range-55°C to +125°C

Storage Temperature Range-65°C to +150°C

Lead Temperature (Soldering - 60 seconds)

300°C
NOTES: All dimensions in inches

Leadsaregold·platedkovar
Package weight is 1.27 grams

ORDER PART NO. U5D770331X

SCHEMATIC DIAGRAM

8CONNECTION DIAGRAM

SOQ

v+o-~~-'\JVl..~~--~~~~~--.t-~~~~~~-o

OUTPUT(TOP VIEW)

7

3

INPUT

5

GROUND4
NOTE: Pin 4 connected to case.

GROUNDNOTE 1: Rating applies for ambient temperatures to 125°C.

FAIRCHILCSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-16

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS JIA703
ELECTRICAL CHARACTERISTICS (TA

25°C, v+ = 12 v unless otherwise specified)Parameter

Min.

Conditions

e.m = 0e =0inPower Consumption
Quiescent Output Current

2.1

ein = 400 mV rms, f = 1 kHz

Peak-to-Peak Output Current

Typ.

Max.

Units

110

170

mW

2.5

3.1

mA

4.0

mA

Output Saturation Voltage

29

1.7

v
mmho
mmho

35

Forward Transadmittance
Input Conductanceein = 10 mV rms, f SlkHzein < 10 mV rms, f S 5 MHz

0.30

0.43

Input Capacitance

7.0

16.0

2.0

3.0

Output Conductanceein < 10 mV rms, f S 5 MHz
f <5 MHze 0 :::; lOOmVrms, f _:::; 5MHz

0.02

0.04

Noise Figure

f = 30 MHz, Rs = 500 '2

6.5

dB

=100 MHz, Rs = 500 fl

8.0

dB

Output Capacitance

f

IJF
pF
mmho

The following specifications apply for -55°C ST AS+ 125°C

e.m = O

Quiescent Output Current

1.7

ein = 400 mV rms, f == 1 kHz

3.2

Forward Transadmittanceein = 10 mV rms, f S lkHz

21

Input Conductanceein <10 mV rms, f S5 MHz
e 0 :::;1oomvrms, f:::; 5MHz

Peak-to-Peak Output Current

3.1

mA

Output Saturation Voltage

1.8Output Conductance

25

1.2

mmho

0.05

mmho

INPUT ADMITTANCE AS A
FUNCTION OF FREQUENCY
v+;I~~
J9JSCE~CE
1--rA • 25°CI{

20v+ • 12V .
I- TA • 25°C --+--+--+--+--+--+--+---!

I •SMHZ
20 l--+--'-+-+-+--t--t--t--+--t----l l6

~

E
E

_l

1

I/ lLCONDUCTANCE

IL IL
1,-C I-"~ "'1---,._ CA~ACllANCEo.__..__..___.__.__.__.__.__...__._~o

0

100

200

300

400

_j_f--- 0

0

500

I

IO

100

INPUT VOLTAGE - mVrms

FREQUENCY - MHz

OUTPUT ADMITTANCE AS A
FUNCTION OF FREQUENCYFORWARD TRANSADMITTANCE
AS AFUNCTION OF FREQUENCY

1000

1.0
0.9

"° 1----+-+-H-v=-·....:·
12V~++l---l---+-+++--i -40
TA· 25°Cv•'.12vo.sco~Ill:E

TA "'25°C

0.7

MAGNITUDE ~30 l---+-+-H--t---+-'"l<+-+---+---+-+++--i-80

0.6

o.s

9J1mH
20 +---+-+-+-+--+---+--+-+-!-----+--+--+++---l -120

0.4

0.3

jL

0.2

o. I

~

0
I

IO
100
FREQUfNCY - MHz

0

1000
FREQUENCY - MHz

6-17

v
mmho

TYPICAL PERFORMANCE CURVESINPUT RESISTANCE AND
CAPACITANCE AS A
FUNCTION OF INPUT VOLTAGE

mA

FAIRCHILD LINEAR INTEGRATED CIRCUITS

a,JA703

TYPICAL PERFORMANCE CURVES

MAXIMUM REVERSE
TRANSAOMITTANCE AS A
FUNCTION OF FREQUENCYOUTPUT CURRENT AS A
FUNCTION OF INPUT VOLTAGE

0.05

1"v• ~ 1zv

0.04

TA =2SoC

0.03

0.02

"'

v+= 12V~TA -25°C

~
~

7

~

)

v

0.01

v

0

I

0

100

IO

-250 -roo -1so -100 -so

1000

~

so 100 1so 200 2so

INPUT VOLTAGE - mv

FREQUENCY - MHz

OUTPUT CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

POWER CONSUMPTION AS A
FUNCTION OF SUPPLY VOLTAGEOUTPUT CURRENT AS A
FUNCTION OF INPUT VOLTAGE

WQt--+-+-+-+-+-+-+-+-+--<

10

o

~b.

~l-+--+-+--+-+-v--1'·_12V~

0 ~1--'---'---'--'---'---'--10_,___,___,___,12

12

SUPPLY VOLTAGE - V

00

POWER CONSUMPTION AS A
FUNCTION OF
AMBIENT TEMPERATURE

OUTPUT CURRENT AS AFUNCTION
OF AMBIENT TEMPERATURE

80

100

INPUT VOLTAGE - mv

SUPPLY VOLTAGE - V

TRANSAOMITTANCE AS A
FUNCTION OF
AMBIENT TEMPERATURE

v+ = 12V
2001---t--t--+--+--+--+-+-+-+--li5~ 1001---t--t--+--+--+--+-+-+-+--l~ 1001--F:::::~t::::t::::t:::::t===:l=-.j.-..b--i

1_...1-----t-ffi

30 ~t-t-t-+-O:=+-+-+-t--1~

Wt--t--t--t--t--t--+-+--t--+---1~

11--+--+--+-+-+-..._..._..._.....___,

so l---t--t--+--+--+-+-+-+--1---l

10 t--+-+-+-+-+-+-+-+-t--1

o.__..__..__..__....._+--+---'--+--.L..-J

o.__....._..._....._..._+---'---'---'---'--'o..__,__,__,__,__..___..___....._....._...__.

~

~

~

O W

~

00

TEMPERATURE- °C

M

~

~

~

~

~

~

0

W

~

00

TEMPERATURE - °C

6-18

M

~

~

~

~

~

~

0

ro

~

00

TEMPERATURE - °C

M

~

~

~

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA703

DEFINITION OF TERMS
POWER CONSUMPTION - The DC power required to operate the device with no signal applied.
·QUIESCENT OUTPUT CURRENT - The DC current delivered to the load with the input terminals short-circuited.
PEAK-TO-PEAK OUTPUT CURRENT - The short-circuit output current excursion for a large-signal input volmge.
OUTPUT SATURATION VOLTAGE - The minimum voltage to which the output collector may be reduced without degrading circuit
performance.
TRANSADMITTANCE - The ratio of the output current to the input voltage.
INPUT ADMITTANCE - The admittance between the input terminals with the output short-circuited.
OUTPUT ADMITTANCE - The admittance between the output terminals with the input short-circuited.

6-19

µA703C
RF-IF AMPLIFIERFAIRCHILD LINEAR INTEGRATER CIRCUITSThe µ.A 703C is an RF-IF amplifier constructed on a single silicon

GENERAL DESCRIPTION

chip and is intended for use. as a limiting or non-limiting amplifier, harmonic mixer, or oscil-'

PHYSICAL DIMENSIONS

lator to 150 MHz. The low internal feedback of the device insures a higher stability-limited
gain than that available from conventional circuitry. Including the biasing network in the same
package reduces the number of external components required, thereby increasing the reliability and versatility of the device.

For full range operation (-55°C to +125°C) see µ.A 703 data

sheet.
ABSOLUTE MAXIMUM RATINGS

Supply Voltage

20 v

Output Collector Voltage

24 v±5.0 v

Voltage Between Input Terminals
Internal Power Dissipation (Note 1)

200mW

Operating Temperature Range

0°c to +70°C

storage Temperature Range-65°C to +150°C

Lead Temperature (Soldering - 60 second)

300°C

HOT£S: AM dimenMons in inc:hnl.udl•r.aold-ptatedkonr~wellhtlll?71f11111$

ORDER PART NO.
SCHEMATIC DIAGRAM

8

U5D770339X

CONNECTION DIAGRAM

500

v+o-~~-'VV\.~~.....~~~~~--<1,__~~~~~~-0(TOP VIEW)v+
OUTPUT

3

7

INPUT
5

4
GROUND

NOTE: Pin 4 connected to case.

NOTE 1: Rating applies for ambient temperatures to 70°C.

FAIRCHILC1SEMICdNDUCTDR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011, TWX: 910·379-6435

6-20

A DIVISION OF FAIRCHILD CAMERA ANO INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA703C
ELECTRICAL CHARACTERISTICS (TA= 25°C, v+ = 12 V unless otherwise specified)Parameter

Conditions

Min.

Power Consumption

e.lil = 0

Quiescent Output Current

e.lil = 0

1.9

Peak-to-Peak Output Current

ein = 400 mV rms, f = 1 kHz

3.6

Typ.

Max.

Units

110

170

mW

2.5

3.3

mA

mA

Output Saturation Voltagev

1.7

Forward Transadmittancee.

Input Conductanceein < 10 mV rms, f :S 5 MHz

0.35

0.50

Input Capacitanceein < 10 mV rms, f :S 5 MHz

9.0

16. 0

pF

Output Capacitancef <5 MHz

2.0

3.0

pF

0.05

mmho

lil

= 10 mV rms, f < lkHz
-

23

-

33

mmho
mmho

Output Conductancee 0 ~ lOOmVrms, f ~ 5MHz

Noise Figure

f = 30 MHz, Rs = 500 fl

6.5

dB

f = 100 MHz, Rs = 500 fl

8.0

dB

The following specifications apply for 0°C :ST A :S 70°C:
Quiescent Output Current

e.lil = 0

1.7

Peak-to-Peak Output Current

ein = 400 mV rms, f = 1 kHz

3.2

3.5

mA
mA

Output Saturation Voltagev

1.8
ein =lOmV rms

Forward Trl)-nsad~ittance22

f <lkHz

Input Conquctanceein <10 mV rms, f :S5 MHz

Output Conductancee 0 :S lOOmVrms, f :S. 5MHz

mmho
mmho

0.71
0.06

mmho

TYPICAL PERFORMANCE CURVESINPUT RESISTANCE AND
CAPACITANCE AS A
FUNCTION OF INPUT VOLTAGE

INPUT ADMITTANCE AS A
FUNCTION OF FREQUENCY

25

1.0 r---r-T-r-r--r----r-.-.r-r--r--r-.,.,-,....-,

l SU~EPTANCE
I

2IJ

/12v
20 t--+-+-"TA-.-"'25""'•c'--t--+-+--+--t--i 16

OUTPUT ADMITTANCE AS A
FUNCTION Of FREQUENCY

y+: 12VTA" 2s 0 c

0.9 t--+-+-++--1+ -.......,H-+--+-+-+++---<

v+'· 12V~-8 t--+-+-++-TA ·.. 25oc+-+-+-+--+---+-+-H-----l
0.7 t--+-+-++---+---+-H-+---+-.--+-~1---i

1--+--+-f 'm 5MHz--+-+--+---l---l---Io. 6 t--+-+-++---+---+-+-<-+--t-t-c.'.t,_N~+I+-l1-NC--<E

1o~t::::J-'-1--"""-'---'--'-'--~~P-Aj~'M_N~l__.~t--__,o
0

100

200

300

400

IL]

I

lLJ I'

I

I

IO

IOO
FREQUENCY - MHz

FORWARD TRANSADMITTANCEAS A FUNCTION. OF FREQUENCYMAXIMUM REVERSE
TRANSADMITTANCE AS A
FUNCJION OF FREQUENCY
. .

l'hi

0,03

2IJ l--+-t-++-+---+-+-H--t--+-++1----1-120

0.02

l"fi.

FREQUENCY· MHz

I

IO

IOO

IOOO

FREQUENCY - MHz )OUTPUT CURRENT AS A
FUNCTION OF INPUT VOLTAGE

TA~ 25°C

I

r/-

0,0I

O~l-'--'-'-'--~IO--'-.~iLI:---1100'--~~_,I000-200

1--+-t+t--+-:::;j.~~"'f+-t-t-+t+--l~ol.--.,i!!!l:!:::::t:=..J..J...L.L...L....L.lJ..L...Joy+. 12V

0.04

MAGNITUDE
JO t--+-+-++--t---t~l"'l..-~Ht---1---t!--"-t-+++--i -so

IOOO

~·

0.05

0.2 l--++++-+--+-+-1-JolL--.+-t-+++--i I

0.1
0INPUT VOLTAGE - mVrms

v-+· 12V~t--+-+-++-7~-·~25°~C-+-H--t--+-++l----l·~0.4 t--+-+-++---+---+-H-+---ff--t-++-1---i
0.3 1--++++-+--+-+-l+---+-++1----l

lZ

0

500

0.5 t--+-+-++---+---+-H-+--++---+-~1---i
SUSCEPTANCE~ONDUCTANCE

_..}"

0
I

IO

100

FREQUENCY - MHz

6-21

IOOO

-150

-50
50
INPUT VOLTAGE - mv

150

250

1.JA703E
RF-IF AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITSGENERAL DESCRIPTION-

The µA 703E is a linear integrated circuit with usefill unneutralized

power gain to frequencies in excess of 100 MHz.

It features the capability of nonsaturating

PHYSICAL DIMENSIONSEPOXY PACKAGE

limiter operation with a suitable output load, making it ideally suited for FM - IF limiter
applications.
Applications include FM-IF limiter - amplifier, TV sound IF amplifier, chroma reference.240~1'11T"'"'-+-

oscillator for color TV, and fixed-gain amplifiers to 100 MHz.

.500

Ceramic

ABSOLUTE MAXIMUM RATINGS

Supply Voltage

20 v

Output Collector Voltage

24 v±5.0 v

Voltage Between Input Terminals
Internal Power Dissipation(Note 1)

45•

200mW

Operating Temperature Range

0°c to +70°C

Storage Temperature Range-55°C to +125°C

Lead Temperature (Soldering - 10 seconds)

260°C

SCHEMATIC DIAGRAM
8MIN.

6 LEADS.019 DIA
.016
·.200

NOTES: All dimensions in Inches

leadsare10ld-ptat1dnlckel
P1ckagew11g11t110.31Sram

ORDER PART NO. U8B770339X

CONNECTION DIAGRAM
500

1v+n-~~...IU"-A~~--~~~~~.............~~~~~~--oRi(TOP VIEW)OUTPUT

V+

7

3

INPUT

5
GND

4
GROUNDNOTE 1: Rating applies for ambient temperatures to +70°C.

l=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-22

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µ.A703E

ELECTRICAL CHARACTERISTICS(TA

25°C, v+ = 12 V, f = 10.7 MHz unless otherwise specified)Parameter
Power Consumption

Min.

Conditions

Typ.

Max.

Units

110

170

mW

2.5

3.3

mA

1.7

Volts

ein =0Quiescent Output Current
Peak-to-Peak Output Current
Forward Transadmittance

mA

5.0

3.0

ein = 400 mV rms

1.4

Output Saturation Voltage

3524

e. = 10 mV rms
m

mmhos
mm ho

0.002

Reverse Transadmittancee. < lOmV rms

.33

1.0

mm ho

e. <10 mV rms
in

9.0

18.0

pF

Output Conductance

0.03

0.05

mmho

Output Capacitance

2.6

4.0

pF

Noise Figure

6.0

dB

8.0

dB

40

dB

Input Conductance
Input Capacitancem

RS= 500fl
Rs = 500 n, f = 100 MHz

Maximum stable Gain

TYPICAL PERFORMANCE CURVESINPUT RESISTANCE AND
CAPACITANCE AS A
FUNCTION OF INPUT VOLTAGEOUTPUT ADMITTANCE AS A
FUNCTION OF FREQUENCYINPUT ADMITTANCE AS A
FUNCTION OF FREQUENCY

f1

y+~ 12V

0.9 1---+-+++--:r+--+-+++--+-++++-I

i :~:

]

l

If [ZcoNoucr.i.NcE
II
IJ

1n i--'T"'T,..,--,--..--......,...-,...-'T"'T,..,..-,SUSCEf'TANCE ;1--+-+++-v' • 12V+-+++--+-+-t-t-t--i-+-++-+-r,-'='~=-1 ~1--+-+++--TA+-·.25-o+C

fiNmNCE l!!;!

!5 o.; 1---+-+-++-+-+-H+-++-SUSC-'-'E-'PTA+NC--iE

f;l

~ 0.6
~

s

~

IJ

0

~

lL

0.3
0.2

§

0.1 f---+-++t-L.--J::::::::+-::~"l+-+-+-+++OL-.lo:::l::U.._J..-l....J...J.J__J__..L.J...LJ..._JO
I
10
100
1000

o l...,,j,,,!!!El::::t::::J..J..J.1-1-..Ll.J.l.~ o

INPUT VOLTAGE - mVrms

FREQUENCY • MHz

FREQUENCY • MHz

FORWARD TRANSADMITTANCE
AS AFUNCTION OF FREQUENCYMAXIMUM REVERSE
TRANSADMITIANCE AS A
FUNCTION OF FREQUENCYOUTPUT CURRENT AS A
FUNCTION OF INPUT VOLTAGE

I

10

IOO

1000

f'..._
1---+-+-..P..-f--l---f v' • 12V t--t-""" ~MAGNITUDE......,.._~1--+-+++---+---+-"l.++-+-+-+++--i·oo

TA·25°C

0.031--+-+++---+---+--l-ll-1----1---+-+++--I

20 l--+-+++---+--+-+++-+-+-++t----1 ·120

IJ.
O.Ol

>-->--H--<-p-17..._....-+++------'f--+--+++--Il~
OLl-L..J...J..l--~IO-L..J...J..1--1~00-L..J...J.~moo"~o.._.....,=--'--'-..W..-1----1---J....LJ..L.-I

FREQUENCY - MHz

FREQUENCY • MHz

I

IOO

10

6-23

1000

~

~ 0.4 1---+-+-++--+--+-H+--H-'-+-+-++--l 2 ;;;:

·llO

·lO

lO

INPUT VOLTAGE - mv

llO

250

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ.A703E
TYPICAL CIRCUIT APPLICATIONS+12V

COLOR TV SOUND-IF AMPLIFIER

r - ---- - - - - - - - - - - - - -1
I

I

FDMlOOO

1

0.0ltJF I

I
1I

O.OljJFI_[

15ko +
511F

11

i
4.7k11I

I
I
I

FDMlOOO
l.5pF
Ein

r---1 r-------<~--F'__ _v'--+--,ii [~ ~
:
E_.:J
~

I

It

-;:I

L _____ - - - - -II- - - _____ _j

2200

7.Sko

"I
I

PERFORMANCE

FINAL VIDEOIF AMPL

O.OlµFI

O.OOlµFI
Ein ® 41.25MHz - INPUT TEST SIGNALS - mV RMS
40 20
41.25MHz

I

•

I

1

I

I

I

~

100

20

MODULATION,....L..

~~~~k~~)VOLUMEf-----7'-'----+----.,,."""'"--~ 0.4

I
0

;
"'

~

10

Ein ® 45.75MHz - INPUT TEST SIGNALS - mV RMS

NORMALIZED OSCILLATORFREQUENCY AS A FUNCTION
OF CONTROL VOLTAGE

3.58-MHz VOLTAGE-CONTROLLED OSCILLATOR

400.--------r----.----.,------,+12V

J57~.545 kHz

FAIRCHILD
i------r----t-

MC102B

10 •TA• 25°C
V + • 12V-

3579.545kHz0

M.,______.F-=
lOOOpF
NPO

I

-400

N750

-1.0

-0.5

NORMALIZED OSCILLATORFREQUENCY AND OUTPUT
VOLTAGE AS A FUNCTION
OF SUPPLY VOLTAGE

l.O

NORMALIZED OSCILLATORFREQUENCY AS A FUNCTION
OF AMBIENT TEMPERATURE

JO .--------r----.----.,------, 14
t0 • 3579.545 kHz

JO

10 - 3579.545 kHz
v + 12VG

TA· 25°C

VControl ~ 0 V

0.5

CONTROL VOLTAGE-=

10 ' - - - - + - - - + - -11

Vcontrol ·av

10

10

10
8.0

6,0

-101-------+---------i-10'-----1----+---+-----< 4.0-20~----~----~-JO L - . . - - - - ' - - - - + - - - + - - - - - < 2.0

10

11

11

13

~~~-'II

200 0.8

30 >-----+--~-+-----< 0.6

z

~

50

AUDIO
OUTPUT

15

14

SUPPLY VOLTAGE-V

6-24

50
TEMPERATURE - °C

75

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA703E
3.58-MHz INJECTION-LOCKED OSCILLATORNORMALIZED PHASE SHIFTAS A FUNCTION OF NORMALIZEDOSCILLATOR FREQUENCY+12V
Color Burst_ _ _ _ Transformer

6.0mA

I

~

Ol----+--t---,ol'--+--+------i

29pH

O.OlpF""·'""'h.1-F-":"____,

2.7kO·50 ._____.__....._____._
-300

N750

NPO

iii

~

IO.OlpF

470pFI

25

I

7

30pFI
NPO

i:l

10 • 3579.54.SkHz
TA• 2SoC
V + • 12V
BURST I NJEC!!ON VOLTAGE. 6-+-------1
FEEDBACK VOLTAGE

O.OlpFrv

NORMALIZED OSCILLATORFREQUENCY AND OUTPUT
VOLTAGE AS AFUNCTION
OF SUPPLY VOLTAGE

-200

-100
OSCILLATOR__.___.____.

100
200
FREQUENCY - Hz

300

NORMALIZED OSCILLATORFREQUENCY AS AFUNCTION
OF AMBIENT TEMPERATURE

20~-~-~~-~-~12~.----------.------,'•. 3579.54.SkHz
V+ • 12V

10 • l579.54HHzTA • 25"Ci o1----+--"""'o!E'---+----t s.o~§bl. -10 1 - - - - + - - - + - - - - + - - - " ! 6.0
0-10 ....__ _ _ _...____ _ _______,
50
75
25

-2!1'---~---'--~---'4.0

10

11

12
1)
SUPPLY VOLTAGE - V

14

TEMPERA!URE - °C

FOUR-STAGE FM-IF AMPLIFIER+12V

Full limiting with V;.

< 50µV.

Pea~to-Peak separation of detector 800 kHz.

THO < 0.8% with :!: 75 kHz deviation @ 400 Hz.

Current consumption 27 mA.
Power gain / stage 26.5 dB.
6-25

JJA709
HIGH PERFORMANCE OPERATIONAL AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITSGENERAL DESCRIPTIONS - The µ.A 709 is a high-gain operational amplifier constructed on a

PHYSICAL DIMENSIONS

single silicon chip using the Fairchild Planar epitaxial process. It features low offset, highinput impedance, large input common mode range, high output swing under load and low power
consumption. The device displays exceptional temperature stability and will operate over awide range of supply voltages with little degradation of performance. The amplifier is intended for use in DC servo systems, high impedance analog computers, in low-level instru-

SEATING

Pl.JiN£mentation applications and for the generation of special linear and nonlinear transfer functions.
ABSOLUTE MAXIMUM RATINGSv

Supply Voltage± 18Internal Power Dissipation T0-99 (Note 1)
Dual -In-Line
Differential Input Voltage

300 mW±5.0 v

Input Voltage±10 v

Output Short-Circuit Duration(TA

300 mW

25°C)

5 sec

Storage Temperature Range-65°C to + 150°C

Operating Temperature Range-55°C to + 125°C

Lead Temperature(Soldering, 60 sec)

NOTES: All dimensions in inches
Dimensions as per latest J -10 committee
Leads are gold. plated Kovar
Package weight is 1.22 grams

ORDER PART NO. U5B770931X

300°C

SCHEMATIC DIAGRAM

CONNECTION DIAGRAMSTYPICAL FLAT PACKAGE(Top View)

INPUT FflEQUENCYCOMPENSATION

••

IOkQ

...

""

'--+---1:.·Qa

Q14

'"

30lQ

T0-99

1 N.C.
N.c.o•OUTPUTr--+--t-<> FREQUENCY(TOP VIEW)

INPUT
COMPENSATION

26COMPENSATIONNOTES: All dimensions in inches

INPUT
COMPENSATION

INVERTING INPUT

B

V+~~~~NVERTING

7

OUTPUTv~

6

ggr:PuE~SATlONORDER PART NO. U3F770931X

FLAT-PAKNOTES:
1. Rating applies for case temperatures to +125°C; derate linearly at 5. 6 mW/°C for ambient temperatures above +95°C.

2. Rating applies for case temperatures to +125°C; derate linearly at 2. 5 mW/°C for ambient temperatures above +30°C.

l=A.IRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (4.l.5) 962-5011, TWX: 910-379-6435

6-26

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA709
ELECTRICAL CHARACTERISTICS (TA = +25°C, ± 9 V ~VS ~ ± 15 V unless otherwise specified)Parameter (see definitions)

C::onditions

Min.

Typ.

RS~ lOkO

Input Offset Voltage

Max.

Units

1.0

5.0

mV

Input Offset Current

50

200

nA

Input Bias Current

200

500

nA

Input Resistance150

Output Resistance

400

kO

150

n

Power Consumption

VS= ±15V

80

165

mW

Transient Response

Vin= 20mV,RL=2kO,
c 1 = 5000 pF, R 1 = 1.5 kO,

0.3

1.0

µ.s

10

30

%

6.0

mV

Risetime

C 2 =200pF, R 2 =500
CL ~100 pF

OvershootThe following specifications apply for -55°C ~TA ~+125°C:
Input Offset Voltage

RS~lO kr2

Average Temperature Coefficientof Input Offset Voltage

Rs= 50 n

3.0µ.V/°C

RS~lO kO

6.0µ.V/°C

Large-Signal Voltage Gain

VS=± 15 V, RL? 2 kO,
vout = ±10 v

25,00045,000±12±1470,000

Output Voltage Swing

VS=± 15 V, RL? 10 kO
VS= ±15 V, RL ?2k0

±10

±13

v

Input Voltage Range

vs= ±15 v

±8.0

±10

v

70

90

dB

v

Common Mode Rejection Ratio

RS~lO kO

Supply Voltage Rejection Ratio

RS~lO kO

25

150

µ.V/V

Input Offset Current

TA= +125°C

20

200

nA

TA= -55°C

100

500

nA

TA= -55°C

0,5

1.5

µ.A

Input Bias Current
Input Resistance

100

40

kO

GUARANTEED ELECTRICAL CHARACTERISTICSOUTPUT VOLTAGE SWINGVOLTAGE GAIN70k
RL>2kQ

I I·SS°C s TA! +l25°C
llOk

50k

40k
30k

IL

v

IL
~~
kd

VI

v IL1

rok >-+-+--+-t--t--+-~>~1-+-+--t-~1--+-+-,1--+-+--t--i~rot-+-t--+-t--t---+--+

i.o~ll ~~~j.-11/.lll~§ Bl-t:;;of""9-::::;;j;.."1=J--f--+-t--1-t--i"'....-I"' J...--t~~ 101-+-+--t-~1--+-+--t--1--"l-+--i..........

~ s.o t-+-+--+--+-<--+-+--+--+-<t-+--<

10 k ~..::c-=iHL-...L.H-1..--1.__i__.L--..J__J_..L-J
91011121314B
SUPPLYVOLTAGE - !Vo'--'--'---'-...._._.__._--L-..____.'---'-_,
9
W
II
~
D
W
B
SUPPLY VOLTAGE - !V

6-27

FAIRCHILD LINEAR INlEGRATED CIRCllllS µA7(!)9
GUARANTEED ELECTRICAL CHARACTERISTICS (CONT'D)
INPUT COMMON MODE
VOLTAGE RANGE

POWER CONSUMPTION~- J.c -+-+-+--+--+--+-+--1--+--<

lOO
:;;-

101--+--+--+--t-1--+-+--+--t-+-+---<

I!
;:!

e

z 2001--+--+--+-+-1-+-+--+-+-+-+--t8.0o--+--+--+--t-t--+-"''ll't<\I)"'0; >~ 6.0t-tj...-i-+1--1-=t;..-t-=F-+-+-+-+-t-+--l~i

BO H-+-t-+-1-+:+:::J.."J.."'1F-t-+k'.'.'.-l
glOOI--+-+--+-+~\~~~ 4.0f-+--+--+-+-f-+--+--+-+-!--+---lI-T~2501--+--+--+-+-1-+-+--+-+-+-+--t.

~

2.01-+--+--+-+-1-+--+--+-+-1--+---l~ so Ht;±+-1~:trtil'f~V\rC~jlHt1+-1=t!jo9.___.____.,.10-'-~11-+-~12-'-~13-'--l~4-'--'B

o.___.____.,._._....__.___.__,__._....__..._._.

SUPPLY VOLTAGE

9

- tV

11

10

12

13

14

B

SUPPLY VOLTAGE - ±V

TYPICAL PERFORMANCE CURVES

B

10

Vs~ tllV{/£_Rl • lOkQ

f/1

TA·

c

I-

0

.
~ ~

~ 0.61--........,f--I--+--+--+--+---+---+--!

~ 0.41--P......
.-+--+--+--+--+-+-+-+--i7.

~~ -5.0

:

I/_

0

~o.z

_!,I

·10

'

-

~

v;

0.4

k'J

y

f

::;;

Bil

;:

~

~

g

"'

+20

+60

TEMPERATURE -

+100

+l«I

•c

INPUT BIAS CURRENTAS A FUNCTION OF
SUPPLY VOLTAGE

~

-t-1-

~

"'1
-20

+20

+60

+100

+l«J

- •c

~

~200r-+-+--l--l::::;l~-t"'"F-+-l-+~~t--f--1--+--+--+--+--+---+--+-~~ _.H-4--r"'~mi-+--+--+-+-11-+-+--+-+-1--+~
m

,,
~

~

~t--f--1--+--+--+--+--+--+--+-~'.!;: BO 1-+--+--+-+-11-+-+--+-+-1--+~m.~'--:'~-:"~___.,._,__.._-+-~
-60

-20

+20

+60

+100

125 .___.__,__,_..___.'--'--'--'-.1..-J'-'---'

+l«J

9

TEMPERATURE - •c

OUTPUT VOLTAGE
SWING AS A FUNCllON OF
LOAD RESIS~~·cE

TRANSIENT RESPONSE TEST CIRCUIT

1.4

Vs· !BV.
2S I- TA• +2S°C ++-+--+-[Ll-tj.1-HH=---1

1.2>

Ui---i--f-+-jl--+l/"~l"'-+-++----l~~l---+-+-+-+--4',__-l-f-+-f--~~~

I mi---+-+-+,~~lL.----+---+--+-+-+---t

~ 0.6
0.4

~ ~1---+-~~H--+--+---+--+-+-+---t

0.2

Wt---+-lt-t-+---+-+-f--+-f--~~>--~f--+-+-+--+--+-+-+-<---'

ro._____.,_-'---'-'--'---'-L-L...+-~

o.s

I

6-28

13

W

B

TRANSIENT RESPONSE

I

o~

i1

rnfr=

Vs.

~ 1ETl"1E

.

o.s

ro ·

LOAD RESISTANCE - kQ

~-

90ll'

0.8

~

18 t---+-+-lll.J'+---+-+-f--+-f--~

0.2

1.0

10k'1

~ ~t---+-+-+-+-r+~-+-f--+-f--4

11

ID

SUPPLY VOLTAGE - ±V~~~~~-.--~~~~

0.1

-20

~ 1001--f--I--+--+-+--+--+---+--+-~

. ILl
JL
V1

TEMPERATURE~-60

Vs• ±BV~ 0.6~

o,__.__.___,____,__,__,__.__.__,__,+140

lm.---..--.,--,--.-.-.---.-.----,--.

0.8

0
-60

+20
+60
+100
TEMPERATURE - °C

POWER CONSUMPTION
AS A FUNCTION OF
AMBIENT TEMPERATURE

Vs •!llV

0.2

-20

mv t

l.O

~

~

OL-'---'---'---'-'--'--'--'---+--'-60.0.2 D.4. o.6 o.8 l.o

INPUT VOLTAGE

INPUT RESISTANCE:AS A FUNCTION Of
AMBIENT TEMPERATURE

"

~

lh
7.7)

· 1~r:o-o.8 -o.6-0.4 -0.2 o"'lW l--.__,f--1--+--+--+--+--+--+--!

_l '"-i TA• +12S'C-

s.o>Vs· ±BV<-o;s•c r-.' !-'=l\ •+2S'C"'<~

INPUT OFFSET CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

INPUT BIAS CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

VOLTAGE TRANSFER
CHARACTERISTICTA:t:lSV:i2S°C~

1.0
l.l
TIME - ps

2.0

2.l

FAIRChllld'.l LINEAR INTEGRATED CIRCUITS JJA709
DEFIN.ITION OF TERMS

INPUT OFFSET VOLTAGE - That voltage which must be applied between the input terminals to obtain zero output voltage.

The

input offset voltage may also be defined for the case where two equal resistances are inserted in series with the input leads.
INPUT OFFSET CURRENT - The difference in the currents into the two input terminals with the output at zero volts.
INPUT RESISTANCE - The resistance looking into either input terminal with the other grounded.
INPUT BIAS CURRENT - The average of the two input currents.
INPUT VOLTAGE RANGE - A range of voltage which, if exceeded on either input terminal, could cause the amplifier to cease
functioning· properly.
INPUT COMMON MODE REJECTION RATIO - The ratio of the input voltage range to the maximum change in input offset voltage
over this range.
LARGE-SIGNAL VOLTAGE GAIN - The ratio of the maximum output voltage swing with load to the change in input voltage required to.,drive the output from zero to this voltage.
OUTPUT VOLTAGE SWING - The peak output swing, referred to zero, that can be obtained without clipping.
OUTPUT RESISTANCE - The resistance seen looking into the output terminal with the output at null. This parameter is defined
only under small signal conditions at frequencies above a fe.w hundred cycles to eliminate the influence of drift and thermal feedback.
POWER CONSUMPTION - The DC power required to operate the amplifier with the output at zero and with no load current.
SUPPLY VOLTAGE REJECTION RATIO - The ratio of the change in input offset voltage to the change in supply voltage producing it.
TRANSIENT RESPONSE - The closed-loop step function response of the amplifier under small-signal conditions.

TYPICAL PERFORMANCE CURVESOUTPUT VOLTAGE.
SWING AS ·A FUNCTION OF
FREQUENCY FOR VARIOUS
COMPENSATION NETWORKS,.:·

OPEN-LOOP FREQUENCYRESPONSE FOR VARIOUS
VALUES OF COMPENSATIONFREQUENCYRESPONSE FOR VARIOUS
CLOSED-LOOP GAINS~...-....,.,..,r-r-.-rn--.-""T"""T'"'T'r'"-r-.,.,.,,...,

'

24

l1

iii
g

20

~ 16

~

!:§

4) .........>++-+-+-+++-....

0~~ 201-+H+-+-++H-+-'H+l_,.._~....t->t--t't-rH

12

~

~

~ 8.0

0

4.0
-20~~~~~~~~._,_~~·20100

lk

!Ok

IOOk

IM

!OM

FREQUENCY - Hz

100

lk

!Ok
IOOk
FREQUENCY - Hz

FREQUENCYCOMPENSATIONCIRCUITlM!OM•use R2 = 50 Q when theamplifier is operated withcapacitive loading.

6-29

!Ok

IOOk
FREQUENCY - HzIM

µA709A
HIGH PERFORMANCE OPERATIONAL AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITS• 2 mV MAXIMUM OFFSET VOLTAGE• 50 nA MAXIMUM OFFSET CURRENT• GUARANTEED DRIFT CHARACTERISTICS

PHYSICAL DIMENSIONS

GENERAL DESCRIPTION - The µA709A is a high-gain operational amplifier constructed on a single siliconchip using the Fairchild Planar* epitaxial process. It features low offset, high input impedance, large input
common mode range, high output swing under load, and low power consumption. The device displays exceptional temperature stability and will operate over a 14-36 V range of total supply voltage with little degradation of performance. The amplifier is intended for use in DC· servo systems, high impedance analog
computers, low-level instrumentation applications, and for the generation of special linear and nonlinear
transfer functions. Although it features improved performance, the µA709A is a direct plug-in replacement forthe µA709 operational amplifier.
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage
Internal Power Dissipation T0-99 (Note 1)
Flat Package (Note 2)
Differential Input Voltage
Input Voltage
Output Short-Circuit Duration (TA = +25°C)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 60 sec)

.019
.016

36V
300mW
300mW
±5.0V
±lOV
5sec
-65°Cto +150°C-55°C to +125°C
300°c

CONNECTION DIAGRAMS.500 MIN

8 Leads~~

NOTES: Dimensions as per latest J·lO committee
Alldimens1onsln1nches
Leadsarepld·platedl<ovar
Packa1ewei1htisl.221rams

ORDER PART NO. U5B7709311

FLAT

SCHEMATIC DIAGRAM

PACKAGE(Top View)
INPUT FREQUENCYCOMPENSATION....••

. .,.

...

7

,.

I

OUTPUT

R~4~---<••

...•1

R15
30tll

T0-5
S
OUTPUT>---+--+--<>FREQUENCYCOMPENSATION(TOP VIEW)
N.C.

INPtJTCOMPENSATION

INVERTING INPUT~~~NVERTINGV-D

NOTES: .All dimensions in inches

N.C.

INPUT

COMPENSATIONV+

ORDER PART NO. U3F7709311

OUTPUT&,~NSATION•V"

FLAT-PAKNOTES:(1) Rating applies for case temperatures to +125°C; derate linearly at 5.6 mW/°C for ambient temperatures above +95°C.
(2) Rating applies for case temperatures to +125°C; derate linearly for ambient temperatures above +30°C.

*Planar is a patented Fairchild process.

FAIRCHIL..CJ
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-30

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA709A
ELECTRICAL CHARACTERISTICS (TA= +25°C, ±9 VS Vs S ±15 V unless otherwise specified)
PARAMETER (see definitions)

CONDITIONS

Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Output Resistance
Supply Current
Power Consumption
Transient Response

Rs

MIN.

TYP.

MAX.

UNITS

2.0
50
200

350

0.6
10
100
700
150
2.5
75

mV
nA
nA
kn
fl
mA
mW

s 10 kn

Vs=±15V
Vs=±15V
Vs= ± 15 V, Vin = 20 mV, RL = 2 kfl, C1 = 5 nf,
RI= 1.5 kn, Cz = 200 pf, Rz =son

Risetime
Overshoot

3.6
108

CL S 100 pf

s TA s +125°C:
Rs s 10 kn

1.5
30

µs

3.0
10
10
15
25
50
250
0.5
2.8
600

mV

%

The following specifications apply for -55°C
Input Offset Voltage
Average Temperature Coefficientof Input Offset Voltage

Rs= 50 n, TA= +25°C to TA= +125°C
Rs= 50 n, TA= +25°Cto TA= -55°C
Rs= 10 kn, TA= +25°C to TA= +125°C
Rs = 10 kn, TA = +25°C to TA = -55°C
TA= +125°C
TA= -55°C
TA= +25°C to TA= +125°C
TA= +25°CtoTA = -55°C
TA= -55°C
TA= -55°C
Vs=±15V
Rs S 10 ks:!
Rs
10 ks:!
Vs= ±15V, RL
2k!J, vout = ±15V
Vs= ±15V, RL
lOk!JVs= ±15V, RL
2 kn
TA= +125°C, Vs= ±15V
TA= -55°C, Vs= ±15V
TA= +125°C, Vs= ±15V
TA= -55°C, Vs= ±15V

Input Offset Current
Average Temperature Coefficientof Input Offset Current
Input Bias Current
Input Resistance
Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Large-Signa I Voltage Gain
Output Voltage Swings

Supply Current
Power Consumption

85
±8.0
80

z
z
z

25,000
±12
±10

1.8
1.8
2.0
4.8
3.5
40
0.08
0.45
300
170

µV/°C
µV!°C

µVl°C
µVl°C
nA
nA
nA/°C
nA/°C
nA
kn

v
110
40

100
70,000

dB
µV/V

v
v

±14
±13
2.1
2.7
63
81

3.0
4.5
90
135

mA
mA
mW
mW

GUARANTEED ELECTRICAL CHARACTERISTICS

INPUT COMMON MODE
VOLTAGE RANGEOUTPUT VOLTAGE SWINGVOLTAGE GAIN

12~~~~~~~~~~-SS°C :STA :S+l25°C:;;-

z

POWER CONSUMPTION
110~~~-~~~~~~171~-I' I

TA•25°C

101-+-+--+--+-+--1-+-+--+--+--+--1<~~kl--+-+--+-~#'>i·~JL<-+--+-+-t---1-~~~~9-~-+----11-+-+--+--+=-i<~ ""' VV1
v J....-r~~.IL1~-+-+--+:::-~~~~,~-~~:;~=~=;~~- ~t-t).-1-b~bdl-+-+--+--t-t--t-+-....-1-!'7"t"71

0

~

20•

5.01--+-+--+--+-+---1-+--+--+--+--+--1

ID k 9.__......cl..-=H'--;L+---'--:':---'--o'o-'-+-'-..J_

10

II

12

13

SUPPLY VOLTAGE - !V

10 t-+-+--+--+--+-t--t-+-+--+-+-t

1415o~~-+--+-~~~-+--+-~
9
W
II
~
13
U
U

o'"--'_,,__,____,___._,.__,-,L__,__..,...___,__.
91011121314
u

SUPPLY VOLTAGE - :!'v

SUPPLY VOLTAGE

6-31

- ±V

10 ~~-+-~,.__,~~-+--~~
9
10
11
12
13
14
15
SUPPLY VOLTAGE - t V

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA709A
TYPICAL PERFORMANCE CURVESVOLTAGE TRANSFER
CHARACTERISTIC

VOLTAGE GAIN AS A FUNCTION
OF AMBIENT TEMPERATURE

IS
Vs· ±ISVRL •lOkQ

10

rJ

0

~
E.
~

I'""- TA • +125°C-1

26

24

iii

22

::ii

l
I

14

~

~,

.0.2 0.4 0.6 0.8 1.0

INPUT VOLTAGE

-

0.1

0.5
LOAD RESISTANCE - kQ

INPUT BIAS CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

INPUT OFFSET CURRENT AS A
FUNCTION OF AMBIENTTEMPERATURE

400

~ 40

cs.:

"'~ 200
~

b..

~ 20

1',,.

i'-...

100

-60

~

0

!;

,..__

0

-20

20

60

100

140

...

85 >-+-+--+--+-.......+-+--+-+--t-+--<!! 10~ ..........--'--+--'--'--'--'--'--'-'--'-~
9
10
11
12
13
14
15

0

COMMON MODE REJECTIONRATIO AS A FUNCTION OF
AMBIENT TEMPERATURE

f"

-60

60

20

100

TEMPERATURE - 'C

INPUT RESISTANCE AS
A FUNCTION OF
AMBIENT TEMPERATURE

POWER CONSUMPTION
AS A FUNCTION OF
AMBIENT TEMPERATURE

140

3.0

!II
' 110 1--t--lf--l,,...+--=t:-+-+--+--t

_y

~

~

~ 108 ~'/-+--+--1--+-+-+-+--+-f"'_,_f--Ii;i~80t=""1"""",..._t--"j--...t--t--t--t--l--tr--t----J

vv

~

'

~ 1.0

I

~701--+--t---t---t---t.....f--lpo.,ji',--ib,,.--t--t

~

ii!

iii

~ 1061--f--l--+--l--+-1--l--+--+--I

II! 0.5

i
25

~ 0.3

~ 104 l--t---<l--+--+--+-+--+--1--1--<

102 '--L......l--1.--L--'---'--'--'---'--'
-60
-20
20
60
100
140
TEMPERATURE- 'C

TRANSIENT RESPONSE

1.4~----~~--~

IZ
L"J

...

1601--t--lt----tt--l----J--t--t--t--I

I

~
[7

8

o.1

-60

-20

20

60

100

sot--t--f--1--t--+--+--+--+--+--t
40 .........'--'__..__,___,___,__,__,__.__,
-60
-20
20
60
100
140

140

TEMPERATURE ·'C

TEMPERATURE ·'C

TRANSIENT RESPONSE TEST CIRCUITSLEW RATE AS A FUNCTION OF
CLOSED-LOOP GAIN USING
RECOMMENDED COMPENSATIONNETWORKS
100
V5•t15V
TA•25'C

l.2t---+:=±=-+--+--+---t

ov~

~

-20

f-i....

SUPPLY VOLTAGE- ±V

TEMPERATURE·'C~

10...z' ll...~ 30 \......a
~

~

I

0.2

50

...'

!!

I-

10

500

~

JL

lL

TEMPERATURE - 'C

mv

INPUT BIAS CURRENT AS A
FUNCTION OF
AMBIENT TEMPERATURE

f5 300..L

12

10k ~~~~~~--+--+-~
-60
-20
20
60
100
140

~

.:z:J

lL

18

~ 16

·IS
-1.0 -0.8 -0.6 -0.4 -0.2 0aVs• ±ISV
I-TA• +25°C

8 20

I

·10

>

!i!

~

I/

> -50

0

28

60 k l--t---<1--+--+--+--+-+--+--1--<·SS'Cf-../l!l=ITA•+25'C

s.o
"'

30

:r:=

{lL.t

'{fj_
TA •

OUTPUT VOLTAGE SWING AS A
FUNCTION OF LOAD RESISTANCE

1.01---+--'--A-~--""""--+--i

0.81---1---1--+----l---l----i

"' 10

0.6

...'ti:"

~

17

..
:ii

L
~·

1.0

0.2'---'-''--'"+---0--+-VS • ±lSV
p:ISETIME
TA "-1_25'C

1.0

I-'

a:

.. 0.4 ~1_._.__+---+---+---1

0.5

y

lOkQ

II
lL

0.1
1.5

2.0

2.5

1

10

100

CLOSED-LOOP GAIN

TIME· ~s

6-32

1000

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA709A
DEFINITION OF TERMS
INPUT OFFSET VOLTAGE- That voltage which must be applied between the input terminals to obtain zero output voltage. The input offset voltage
may also be defined for the case where two equal resistances are inserted in series with the input leads.
INPUT OFFSET CURRENT- The difference in the currents into the two input terminals with the output at zero volts.
INPUT RESISTANCE- The resistance looking into either input terminal with the other grounded.
INPUT BIAS CURRENT - The average of the two input currents.
INPUT VOLTAGE RANGE- The range of voltage which, if exceeded on either input terminal, could cause the amplifier to cease functioning properly.
INPUT· COMMON MODE REJECTION RATIO- The ratio of the input voltage range to the maximum change in input offset voltage over this range.
SUPPLY VOLTAGE REJECTION RATIO - The ratio of the change in input offset voltage to the change in supply voltage producing it.
LARGE-SIGNAL VOLTAGE GAIN -The ratio of the maximum output voltage swing with load to the change in input voltage required to drive theoutput from zero to this voltage.
OUTPUT VOLTAGE SWING - The peak output swing, referred to zero, that can be obtained without clipping.
OUTPUT RESISTANCE - The resistance seen looking into the output terminal with the output at null. This parameter is defined only under small
signal conditions at frequencies above a few hundred cycles to eliminate the influence of drift and thermal feedback.
POWER CONSUMPTION - The DC power required to operate the amplifier with the output at zero and with no load current.
TRANSIENT RESPONSE- The closed-loop step-function response of the ampLifier under small-signal conditions.

TYPICAL PERFORMANCE CURVES

OPEN-LOOP FREQUENCYRESPONSE FOR VARIOUS
VALUES OF COMPENSATIONOUTPUT VOLTAGE SWING AS A
FUNCTION OF FREQUENCYFOR VARIOUS
COMPENSATION NETWORKSFREQUENCY RESPONSE
FOR VARIOUS
CLOSED-LOOP GAINS'z

60 r-T"lTrl"- . , , . , . ,

~
!:i

~

~

g

z

.........,.........................

§ ro1-H+1-1-+-1-tH1-H-t+-4~...,,.tt-'lrt'ttt'-1

i

24

lE

~ ~h""m-"t-Ttn-.,.....,.-m-........-191;;:+-1-\tt-,g~§ roh""m-"t-Ttn-.,.....,.-m-..,....,-H+od-i-N-,

ii ro

~

*

5

$0
"'ii!

16
12

~ 8.0
4.0

~~~~~~~~~~~

100

lk

!Ok
IOOk
FREQUENCY • Hz

IM

!OM

FREQUENCY CHARACTERISTICS
AS A FUNCTION OF
SUPPLY VOLTAGE!Ok
FREQUENCY - Hz

IM

!OM

IOOk
FREQUENCY - HzIMFREQUENCY CHARACTERISTICS
AS A FUNCTION OF
AMBIENT TEMPERATUREFREQUENCY COMPENSATIONCIRCUITT •25'C*Use R2 = 50 Q when theamplifier is operated withcapacitive loading.

"t-... £~···· --t,,---1---1---1

1.2
0.8 I -

vV~~E
~D"tOQ

~

1--1--1--t--t--+-+-~~
rorlf

0.7 1-i-+-+--+--+--t-t-t-+-+--+-;

0.4 1--1--1--t--t--t--t---r--r--r-1

0.5 L...J--'.-'--'--'-.J..-1--1-..J..-'--'--'
9
10
11
12
13
14
15

o,__,__,__,__,__,__,__,__,__~·60

SUPPLY VOLTAGE· ty

-20

20

60

TEMPERATURE - 'C

6-33

100

140

uA709B
HIGH PERFORMANCE OPERATIONAL AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITSGENERAL DESCRIPTION - The µA709B is a high-gain operational amplifier constructed on a single siliconchip using the Fairchild Planar" epitaxial process. It features low offset, high input impedance, large input
common mode range, high output swing under load and low power consumption. The device displays ex·
ceptional temperature stability and will operate over a wide range of supply voltages with little degr11dationof performance. The amplifier is intended for use in DC servo systems, high impedance analog computers,
in low-level instrumentation applications and for the generation of special linear and nonlinear transfer
functions. For improved specifications, see µA709A or µA709 data sheet.
ABSOLUTE MAXIMUM RATINGSPHYSICAL DIMENSIONS(TYPICAL FLAT PACKAGE)

r- ~~g--~----·~~g ··--·-·r·---~;gl

'Fl

L[]
1='

050

T-

--~

5

Supply Voltage
Internal Power Dissipation (Note 1)
Differential Input Voltage
Input Voltage
Output Short-Circuit Duration (TA25°C)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 60 second time limit)±18V
300 mW
±5.0V
±lOV
5 sec
-65°C to +150°C-55°Cto +125°C
300°C

=

SCHEMATIC DIAGRAM

6

019
015

26o
.240

··-~ _J
J

__

065
050

L=~·::i__l~60

L____r=
_____
==

0035

n

024

NOTES: All dimensions in inches

ORDER PART NO. U3F7709313

CONNECTION DIAGRAM!TOP VIEW)
N.C.
INPUT
COMPF<NSATION
INVERTING INPUT
NON·lNVERTING
INPUT.

NC
INPUT
COMPENSATIONV•OUTPUTv.

INVERTING<>--------+---~
INPUT*Planar is a patented Fairchild process.

NON-INVERTING n - - - - - <INPUTNOTES:(1) Rating applies for case temperatures to +125°C; derate linearly at 2.5 mW/°C for ambient temperatures above +60°C.

l=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-34

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA709B
ELECTRICAL CHARACTERISTICS (Vs= ± 15 V, TA= 25°C unless otherwise specified)
PARAMETERCONDITIONSMIN.

Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Output Resistance
Large-Signal Voltage Gain
Output Voltage SwingRs :5: lOkO, ±9V :5: Vs :5: ±15V

50
RL ~ 2k0, You+= ±lOV
RL ~ 10 kO
RL ~ 2k0

Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection 1Ratio
Power Consumption
Transient Response
Risetime

15,000
±12
±10
±8.0

Rs :5: 10 kO
Rs :5: 10 kO

65

Vin = 20 mV, RL = 2 kU,
C1 = 5000 pf, R1 =1.5 kO,
C2 = 200 pf, R2 = 50 n
CL :5; 100 pf

Overshoot

TYP.

MAX.

UNITS

2.0
100
0.3
250
150
45,000
±14
±13
±10
90
25
80

7.5
500
1.5

mV
nA
µ.A
kO

n

v
v
v
dB
µ.V/V

200
200

mW

0.3

%

10

The following specifications apply for 0°C :5; TA :5: + 70°C:
Input Offset Voltage
Rs :5: 10 kO, ±9 V :5: Vs :5: ± 15 V
Input Offset Current
Input Bias Current
Large-Signal Voltage Gain
Rt ~ 2 kO, Vout = ± 10 V
Input Resistance
The following specifications apply for -55°C :5; TA :5: +125°C:
Input Offset Voltage.
Rs :5: 10 kO, ±9 V :5: Vs :5: ± 15 V
Input Offset Current
Input Bias Current
Large-Signal Voltage Gain
RL ~ 2 kO, You+ = ± 10 V

mV
nA

10
750
2.0

µ.A

12,000
35

kO
mV

12.5
1.2
3.0

µ.A
µ.A

10,000

GUARANTEED ELECTRICAL CHARACTERISTICSVOLTAGE GAININPUT COMMON MODE
VOLTAGE RANGEOUTPUT VOLTAGE SWING
12

T TTT

I- rtc•T~ +JO'c t--t--+--+-+--1-+-t~1--1--1--+-+-i-+-+-+-t--t--+-~

1--+--t--t-+-1--t--T- I

1120

i

~~o~

-~~

.....1-"1"'"'~

ilS~~

10

11

12

SUPPLY VOLTAGE

13

U

IS

• tV

.-111-•·t-1._,--t.--:::::l;;o~~ •1-t-t-::::i..-it"""Fl--1~1-1-+-+-+-t-+-,1-t"""

i

i101--1---+--+-~-+-+--+-+-i-.t-~I •1--+-+-+-1--+-+-+-+-+--+--+-1

ii! 5

Iz

a
.:.

o,

I

l-+-+-+--+-+-+--1-+-+-+--+--Iuo,.........-10~_._11.......~12........~u_._~u__._~IS.

o,........-I0...._._1~1.......~12_._~13_._~1'_._~IS
SUPPLY VOLTAGE•

SUPPLY VOLTAGE

i V

• i V

TYPICAL PERFORMANCE CURVESISVOLTAGE TRANSFER
CHARACTERISTIC
Vs• tlSV
rM· r-"1-t- RL • IOkll

fJL

TA ·o·c,...... P-TA •+JO'C

11_

FREQUENCYCOMPENSATIONCIRCUIT":- TA• +l!"C --i

iIll 41 ...,.m-11""1"'1,,_.,-i-rM-r'"'l"'+lll;;:-t--ttlH

If
I/_

.!.'

(/J
·IS

:!!

~

1.

·5

FREQUENCYRESPONSE FOR VARIOUS
CLOSED-LOOP GAINS•use R2 • 50Qwhen theamplifier is operated withcapacitive loading.

Iu

20 1-++111-+-Hl+-+-Hltt-++ttt-Hi:ttt-I

Ot-Mm--irt"T'IT-T""T"Mrf"T"T'Tt'lod-TftlH

lk·1.0·0.I ·G.6 ·0.4 ·0.Z 0 O.Z 0.4 0.6 0.8 1.0
INPUT VOLTAGE • mv

6-36

IOk
llllk
FREQUENCY • Hz

lM

lOM

µA709C
HIGH PERFORMANCE OPERATIONAL AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITS

ii.A 709C is a high-gain operational amplifier constructed on asingle silicon chip using the Fairchild Planar epitaxial process. It features low offset, high

GENERAL DESCR,PTION - The

PHYSICAL DIMENSIONS
in accordance withJEOEC(T0·99) outline

input impedance, large input common mode range, high output swing under load and low power
consumption. The device displays exceptional temperature stability and will operate over a.335.3709hwide range of supply voltages with little degradation of performance. The amplifier is in-,335__J.305 -----itended for use in DC servo systems, high impedance analog computers, in low-level instru-

.
0
MAX.
I 40Q
Seating_l_mentation applications and for the generation of special linear and nonlinear transfer functions.

Piii-•·r1-

For full temperature range operation (-55"C to +125"C) see µ.A709 or µ.A709A data sheet.

8L~g~; ~~ ~ ~~ABSOLUTE MAXIMUM RATINGS.185

1 '165~500 MIN.

.016

±18 v
250 mW±5.0 v±10 v
5 sec-65°C to + 150°C-55°C to +125°C
0°c. to +70°C
300°C
260°C

Supply Voltage
Internal Power Dissipation(Note 1)
Differential Input Voltage
Input Voltage
Output Short-Circuit Duration(TA = 25°C)
Storage Temperature Range T0-99
Dual-In-Line
Operating Temperature Range
Lead Temperature
T0-99 (Soldering, 60 sec)
Dual-In-Line (Soldering, 10 sec)

.034
.028

~~

NOTES. Dimensions as per latest J·IO committee
Alld1mens1ons1n1nches
Leadsare1old·platedK0'11'1r

Packagewe1ght1sl.221nms

ORDER PART NO.

U5B770939X

SCHEMATIC DIAGRAM

CONNECTION DIAGRAMPHYSICAL DIMENSIONS

i--- TYP.
.375
INPUT FREQUENCYCOMPENSATION

NOH·'1n4--.tMt.-.011(Top View)

.009

j\__

CONNECTION DIAGRAM

T-

.no

INVERTING
INPUT

o-------1------<" Q2

NON· INVERTING

INPUT

R10
18KO

OUTPUT---+----<"-<> FREQUENCYCOMPENSATION

.090

NC
NC

o-'-'------<" Q1

INPUT
FREQ. COMP.

INVERTING
INPUT

V+

NON-INVERl'ING
INPUT

v-

NOTES: All dimensions in inches
OUTPUT
FREQ. COMP.

ORDER PART NO.
U6E7709393

NOTE 1: Rating applies for ambient temperatures to +70°C.

F.AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-36

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA709C
ELECTRICAL CHARACTERISTICS (VS

25°C unless otherwise specified)±15V, TA

Parameter

Min.

Conditions

Typ.

Max.

Units
mV

Input Offset Voltage

2.0

7.5

Input Offset Current

100

500

nA

Input Bias Current

0.3

1.5

µ.A

Input Resistance50

Output Resistance
Large-Signal Voltage Gain

RL ? 2 kfl, Vout = ± lOV

Output Voltage Swing

kfl

150

'2

15,00045,000

RL? 10 kfl

±12

±14

RL? 2kfl

±10

±13

±8.0

±10

v

65

90

dB

Input Voltage Range
Common Mode Rej1fotion Ratio

RS '.S lOkfl

Supply Voltage RejflcuonRatio

RS '.S lOkfl

Power Consumption
Transient Response

250

V.

m

v
v

25

200

µ.V/V

80

200

mW

= 20 mV, RL = 2 kfl,

kRisetime

cl= 5000 PF1R1 = l.:> kn,
c 2 = 200 pF, R 2 = 50 fl

0.3

µ.s

OvershootCL '.SlOO pF

10%

The following specifications apply for 0°C '.S TA '.S+70°C
Input Offset Voltage

Rs

S lOkfl, ± 9 V '.S ± 15 V

10mV

Input Offset Current

750

nA

Input Bias Current

2.0

µ.A

Large-Signal Voltage Gain

12,000

RL ? 2k'2, Vout = ± lOVInput Resistaiice

35

kfl

GUARANTEED ELECTRIC}\L CHARACTERISTICS.
OUTPUT VOLTAfiE SWINGVOLTAGE GAININPUT COMMON MODE
VOLTAGE RANGE

31--1--+-+---l--l--+-+-+-1--1--1---1~--+-+--+--+-+---<>-- I lll'll ~

~zo

;;

~~~

ID l--t--+-+-+----1--1--+-+-+-1--4'--I

~

~~~~

~

~
.....i----~1lll~
il! ISH-,...!o4--d;.~4--+-+-t-H-I~ 6HH-:!....!-""'FJ..-.-:.:...1-1H-+-+-+-+-I"' ro1--1--+-+---+--l--+-+-+-1--1-+---1
g.:.ii! 51-+--+-+---+--l--+-+-+-l--t-+---I§ 41--t'--l--+-+---+--+--+--+-+-+-l--l8..........-i-r-

g~

~

I

~

21--t'--l--+-+---+--l--+--+-+-+-l--lo~9~~10~-1~1~~u~~13~-14~~15

SUPPLY VOlTAGE- •V

SUPPLY VOLTAGE-±V

SUPPLY VOLTAGE- ±V

TYPICAL PERFORMANCE CURVESVOLTAGE TRANSFER
CHARACTERISTIC{f,i ::1::1--

Vs· ±ISV'flt- RL • IOkQ
10TA·o•C):... FfTA·+7ll"C

FREQUENCYCOMPENSATIONCIRCUITi"-:TA • +3°C ---1

1
f

-5

•use R2 = 50 Q when theamplifier is operated withcapacitive loading.

I

-10

!JiI

-15
-l.0-0.8 ·0.6-0.4 -0.2 0
INPUT VOLTAGE

z

R•
2

I

0.2 0.4 0.6 0.8 1.0-

mVFREQUENCYRESPONSE FOR VARIOUS
CLOSED-LOOP GAINS~l-T'TIT""1"""1-t1T""T""niir-T-"""!""+llld-Hrrt-1
g~§ ZOt-T"m-.,.....,.-111""...,........-f!-.-"t"-ttkt-H'w-1:~ Ot-T"m-.,....,.-t!T...,....,....,.,.....,_.,...,.;kt-Mw-1

u

lk

IOk

IOOk

FREQUENCY - Hz

IM

!OM

µA710
HIGH-SPEED DIFFERENTIAL COMPARATORFAIRCHILD LINEAR INTEGRATED CIRCUITS• IMPROVED SPECIFICATIONS• 2 mV MAXIMUM OFFSET VOLTAGE• 3 µA MAXIMUM OFFSET CURRENT• 1250 MINIMUM VOLTAGE GAIN
• 10 µV/°C MAXIMUM OFFSETVOLTAGE DRIFTPHYSICAL DIMENSIONS
in accordance withJEFDEC(TO::;~ o~utline.335.335__J.305 -----i

GENERAL DESCRIPTION - The µA710 is a differential voltage comparator intended for applications requiring high accuracy and fast response times. It is constructed on a single silicon chip using the Fairchild Planar*
epitaxial process. The device is useful as a variable threshold Schmidt trigger, a pulse height discriminator, a voltage comparator in high-speed A-D converters, a memory sense amplifier or a high-noise immunity line receiver. The
output of the comparator is compatible with all integrated logic forms.

MAX.
.
040Q

· 165

Plane-ff
8 Lem

.185

_~

Seating_L~~ ~ ~~

500 MIN.

.016

ABSOLUTE MAXIMUM RATINGS

Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Internal Power Dissipation
T0-99[Note 11
Flat Package[Note 21
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec.l+14.0V
-7.0V
lOmA

±5.0V
±7.0V
300mW
200mW

-55°C to + 125°C- 65°C to + 150°C
300°C

T0-99 CONNECTION DIAGRAM.~~NOTES: D1mens1ons asper latest J·lO committee
Alld1mens1ons1ninches
Leads are gold-plated Kovar

Packagewe1ght1sl.22grams

ORDER PART NO.
U5B771031X

SCHEMATIC DIAGRAM(TOP VIEW)PHYSICAL DIMENSIONS(lYPICAL FLAT PACKAGE)(TOP VIEW)

R4
2.8k0

R5

3.9k

y.

Note: Pin 4 connected to case.

FLAT PACKAGE CONNECTION DIAGRAM(TOP VIEW)

GND

10

N.C.

NOTES: All dimensions in inches
NON INVE~:~c:::----.

INVE:::~~c:::::::j~--1....N.C.
y.

N.C.
V+

ORDER PART NO. U3F771031X

N.C.
OUTPUT

Notes on page 2·•Planar is a patented Fairchild process.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910·379·6435

6-38

A DIVISION OF FAIRCHILD CAMERA ANO INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA710
ELECTRICAL CHARACTERISTICS (TA= +25°C, v+ = 12.0V, v- = -6.0V unless otherwise specified)

PARAMETER(see definitions)
Input Offset Voltage
Input Offset Current
Input Bias Current
Voltage Gain
Output Resistance
Output Sink Current
Response Time [Note 31

The following specifications apply for -55°C
Input Offset Voltage
Average Temperature Coefficient of Input
Offset Voltage
Input Offset Current
Average Temperature Coefficient of Input
Offset Current
Input Bias Current
Input Voltage Range
Common Mode Rejection Ratio
Differential Input Voltage Range ·Voltage Gain
Positive Output Level
Negative Output Level
Output Sink Current
Positive Supply Current
Negative Supply Current
Power Consumption

CONDITIONS(Note 4)

MIN.

TYP.

MAX.

UNITS

2.0
3.0
20

µA
µA

1250

0.6
0.75
13
1700
200
2.5
40

Rs S 200!1

t:.V;, 2 5 mV, Vo,1 = 0

2.0

mV

!1
mA
ns

s TA s + 125°C:
Rs S 200!1
Rs=50!1,TA=25°CtoTA= +125°C
Rs= 50!1, TA= 25°C to TA= -55°C
TA= +125°C
TA= -55°C
TA= 25°CtoTA = +125°C
TA= 25°C to TA = -55°C
TA= -55°C
v- = -7.0V
Rs
200!1

s

t:.V;, 2 5 mV, 0 S lo,t S 5.0 mA
t:.V;, 2 5 mV
TA= +125°C, t:.V;, 2 5 mV, Vo,1 = 0
TA = -55°C, t:.V;, 2 5 mV, Vo,t = 0
Vo,, s 0

3.5
2.7
0.25
1.8
5.0
15
27
±5.0
80
±5.0
1000
2.5
-1.0
0.5
1.0

10

mV
µV/°C
µVf 0C

3.0
7.0
25
75
45

µA
µA
nA/°C
nA/°C
µA

3:0
10

v
dB

100

v
3.2
-0.5
1.7
2.3
5.2
4.6
90

4.0
0

v
v

9.0
7.0
150

mA
mA
mA
mA
mW

NOTES:(!) Rating applies for case temperatures to +125°C; derate linearly at 5.6 mW/°C. for ambient temperatures above -j-!05°C.
(2) Derate linearly at 4.4 mW/°C for case temperatures above +115°C; derate linearly at 3.3 mW/°C for ambient temperatures above +100°c.
(3) The response time specified (see definitions) is for a 100-mV input step with 5-mV overdrive.
(4) The input offset voltage and input offset current (see definitions) are specified for a logic threshold voltage of l.8V at -55°C, l.4V at -j-25°C and l.OV at -j-!25°C.

6-39

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A710
TYPICAL PERFORMANCE CURVES

:r

4.0

1800

~

v'. 12 v--"r··.:t·-3.o L~L...LLL~t=::t:::w
TA • -55°C // ··r::·1z¥r;·v· • -6.o v

v+ "' 12 v,---

'ti"'!'

2.0 l--+--+--+--+--""'rr.'L,_,._--1---1---1--1

v· "' -6.o v

D

1100

~

1600

~

IS

l /

' ,

1.0
0

j;_' '

-3.0

-1.0

rs.

I~

25°C +-+-+--!

1' -[-1.0 --- --- --- --

~

1500

r;
--- --- --- - •r---r ·-5.0

VOLTAGE GAIN
AS A FUNCTION OF
SUPPLY VOLTAGESVOLTAGE GAIN
AS A FUNCTION OF
AMBIENT TEMPERATURE

VOLTAGE TRANSFER
CHARACTERISTIC

1.0

3.0

5.0

1300
-60

-20

100

60

20

l~

INPUT VOLTAGE - mV

TEMPERATURE - °C

POSITIVE SUPPLY VOLTAGE - V

INPUT BIAS CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

INPUT OFFSET CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURECOMMON MODE REJECTION RATIOAS A FUNCTION OF
AMBIENT TEMPERATURE

2.0
1--+----+----+----f-----1----<--+ v+ • 12 v
v··-6.0V

rs:~l--+-+-+-+-+-+--+-+-+-1

y+"' 12V

y+ "' 12 v

t---+--+--+--+-+-_-+--1+I v· • -1 .o v-

v· • -6.0V
102

\

["""

20

l--+-~---f'--1-i-....-+--+-+-+-+-+--<~-5.0Vs. VcMs.+5.0V

)..

L

1.0

100

JS

f'

10 l-+-+-+-+-+"'"t--<:::t-+-+--1

t-t-

-20

b

~

981---l---l--+--+-+-+-+"'..i.~-+-<

~

0

-60

t--t--+-r---+-b,,-'l-~-+-+-+-+-----1

60

20%1--+--+-+-+-+-+-+--1--+--I

f-.t.
140

HJ()

TEMPERATURE - °C

TEMPERATURE - °C

TEMPERATURE - °C

POWER CONSUMPTION
AS A FUNCTION OF
AMBIENT TEMPERATURE

OUTPUT SINK CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

OUTPUT VOLTAGE LEVELSAS A FUNCTION OF
AMBIENT TEMPERATURE

3.5

4.0 .---..---,--,--,.---,,.---,,.---,,--,,--,,--,~l--+-+-+--+-+--+--+--1--~

J ..tv+ • i'2v

V+ • 12V!--+-+-+--+-+--+--+- v· • -6.o v

3.0
2.5

17

I'-

2.0

2.0 l--+-+-+-+-+-+-+--1--+-I ~GJC fHRfSHOLD

~

1.5
1.0

-60

V+•l2V

3.01-~.1-j:::::-:i==PO+S/=TfV':f::fo~u:i:r+-PU~Tlf1"+V~flJ_:v...,··=·d6.0:_:__Vv· • -6.o v~ t--

1.0 f-f-f-t-t-+-+L...J:::::-+--f"""T'-l~Ol--+--+--+--+--+-+-+-+--+--1
NEGATIVE OUTPUT LEVEL "---!
-20

60

20

100

l~

-l.~60~~...,_20+----+----2~0__,___,_60--1---1-100~~1~

TEMPERATURE - °C

TEMPERATURE - °C

TEMPERATURE - °C

RESPONSE TIME FOR
VARIOUS INPUT OVERDRIVESRESPONSE TIME FOR
VARIOUS INPUT OVERDRIVESCOMMON MODE
PULSE RESPONSE

4.0

3.0

1.0

1.o~~+=+:=+::::j::::.j_..+rA .'25°c1--

~ ~

lOmV
20mV

-l. O>-+--+--.......+-+--+--<-+--t-V,'-·-+•12-Vf-+-<V+ :1:12v
l.O t--+-+-+-+-+--1--+7'-v--·-7_6,_,V- - l

I~ N _LI 1Tmv

2.0

1.ot--+-+-+-+-+-+--+--+--+--lJi\ "bLs.omv 1'i--.,f--'t-:~'"

r--+-

-1.0

r-t-

>-+--+--.......+-+--+--<-+--+V· ·• -6: 0 VJ-l-

100 ........._--l---'--l--+--+--<-+--+--TA~·-+~o-Cf-+-<

50Q

VcM

11A7lO

v out

+-+-

-+----+--+--1--11--~

2.0 r--+- ~ +--+--1--1--+--+--+--l100

1.of::::::t:~:::J,,=i:~==l:==l:~:::::j:=j::::::j

V+= +12V

50

V- = -6,0V

Tj·r t-t20~

60
TIME- ns

80

100

120

20

~

60
Tl ME- ns

6-40

80

100

120

80
TIME - ns

120

160

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA710

DEFINITIONSLOGIC THRESHOLD VOLTAGE- The approximate voltage at the output of the comparator at which the loading logic circuitry changes its digital state.
INPUT OFFSET VOLTAGE- The voltage between the input terminals when the output is at the logic threshold voltage. The input offset voltage may also be
defined for the case where two equal resistances are inserted in series with the input leads.
INPUT OFFSET CURRENT - The difference in the currents into the two input terminals with the output at the logic threshold voltage.
INPUT BIAS CURRENT - The average of the two input currents.
INPUT VOLTAGE RANGE- The range of voltage on the input terrnirials for which the comparator will operafe within specifications.
I

INPUT COMMON MODE REJECTION RATIO - The ratio of the input voltage range to the maximum change in input offset voltage over this range.
DIFFERENTIAL INPUT VOLTAGE RANGE- The range of voltage between the input terminals for which operation within specifications is assured.
VOLTAGE GAIN - The ratio of the change in output voltage to the change in voltage between the input terminals producing it with the DC output level in thevicinity of the logic threshold voltage.
RESPONSE TIME- The interval between the application of an input step function and the time when the output crosses the logic threshold voltage. The input step dr.ives the comparator from some initial, saturated input voltage to an input level just barely in excess of that required to bring the output fromsaturation to the logic threshold voltage. This excess is, referred to as the voltage overdrive.
POSITIVE OUTPUT LEVEL- The DC output voltage in the positive direction with the input voltage equal to or greater than a minimum specified amount.
NEGATIVE OUTPUT LEVEL- The DC output voltage in the negative direction with the input voltage equal to or greater than a minimum specified amount.
OUTPUT SINK CURRENT-"- The maximum negative current than can be delivered by the comparator.
PEAK OUTPUT CURRENT - The maximum current that may flow into the output load without causing damage to the comparator.
OUTPUT RESISTANCE - The resistance seen looking into the output terminal with the DC output level at the logic threshold voltage.
POWER CONSUMPTION - The DC power into the amplifier with no output load. The DC power will vary with signal level, but is specified as a maximum forthe entire range of input-signal conditions.

6-41

µA710B
HIGH-SPEED DIFFERENTIAL COMPARATORFAIRCHILD LINEAR INTEGRATED CIRCUITS• 5 mV MAXIMUM OFFSET VOLTAGE• 5 µA MAXIMUM OFFSET CURRENT• 1000 MINIMUM VOLTAGE GAIN
• 20 µV/"C MAXIMUM OFFSET VOLTAGE DRIFTPHYSICAL DIMENSIONS(TYPICAL FLAT PACKAGE)(TOP VIEW)

GENERAL DESCRIPTION - The µA710B is a differential voltage comparator intended for applications requiring high accuracy and fast response times. It is constructed on a single silicon chip using the Fairchild
Planar• epitaxial process. The device is useful as a variable threshold Schmidt trigger, a pulse height discriminator, a voltage .comparator in high-speed A-D converters, a memory sense amplifier or a high-noise
immunity line receiver. The output of the comparator is compatible with all integrated logic forms..
L

For improved specifications, see µA710 data sheet.

I

019

.065
.050

.015

ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Internal Power Dissipation (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec.)+14.0V
-7.0V
10 mA
±5.0V
±7.0V
200mW

-55°C to +125°C. -65°C to +1so 0 c

t~-1

·'°'°
.0035

r

.024
TYP

t

NOTES: All dimensions .in inches

ORDER PART NO. U3F7710313

300°C
CONNECTION DIAGRAMSCHEMATIC DIAGRAM
GND

NON
INVERTING
INPUT

••

10

N.C.

N.C.

INVERTI~
INP T

Y+

N.C.

N.C.

y.

OUTPllT(TOP VIEW)*Planar is a patented Fairchild process.

Notes on page 2

F=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-42

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA710B
ELECTRICAL CHARACTERISTICS (TA = 25°C, v+ = 12.0V, v- = -6.0V unless otherwise specified)
PARAMETER(see definitions)
Input Offset Voltage
Input Offset Current
Input Bias Current
Voltage Gain
Output Resistance
Output Sink Current
Response Time (Note 2)

CONDITIONS(Note 3)

MIN.

TYP.

MAX.

UNITS

5.0
5.0
25

µA

1000

1.6
1.8
16
1500
200
2.5
40

Rs~ 2000

liV;n ~ 5 mV, VOIJt = 0

1.6

mV
µ.A
0
mA
ns

The following specifications apply for .0°C ~ TA ~ + 70°C:
Input Offset Voltage
Average Temperature Coefficient of Input
Offset Voltage
Input Offset Current
Average Temperature Coefficient of Input
Offset Current
Input Bias Current
Voltage Gain
01Jtput Sink CurrentRs~ 2000
Rs = 50 o, TA = 0°C to TA = + 70°C

5.0

6.5
20

mV
µ.V!°C

15
24
25

7.5
50.
100
40

µA

TA= 25°CtoTA = +70°C
TA= 25°Cfo TA= 0°C
TA= 0°C
800
0.5.iV;n ~ 5 mV, VOIJ1 = 0

nA!°C
nA!°C
µA

mA

The following specifications apply for -55°C ~ TA ~ + 125°C:
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Voltage Range
Common Mode Rejection Ratio
Differential Input Voltage Range
Voltage Gain
Positive Output Level
Negative Output Level
Positive Supply Current
Negative Supply Current
Power Consumption.

Rs~ 2000
TA= +125°C
TA= -55°C
TA= -55°C
v- = -7.0V

0.9
3.8
34

Rs~ 2000

liV;n ~ 5 mV, 0 ~ IOIJt ~ 5.0 mA
liV;n ~ 5 mVvout ~ 0

±5.0
70
±5.0
500
2.5
-1.0

7,5
5.0
15
80

mV
JiA
µ.A
µ.A

v
98

dB

v
3.2
-0.5
5.2
4.6
90

4.0
0
9.0
7.0
150

v
v
mA
mA
mW

NOTES:(1) Derate linearly at 4.4 mW!°C for case temperatures above + 115°C; derate linearly at 3.3 mW!°C for ambient temperatures above + 1oo•c.
(2) The response time specified (See definitions) is for a 100-mV input step with 5-mV overdrive.
(3) The input offset voltage and input offset current (see definitions) are specified for a logic threshold voltage of 1.SV at -55°C, 1.5V at o•c, 1.4V at +25°C, 1.2V at + 70°C,
and 1.0V at + 125°C.

6-43

·~1~~~~~~-FA_l_RC_H_l_LD~L_IN_E_A_R_l_NT_E_G_R_AT_E_D~C_IR_C_U_IT_S~µ_A_7_10_B~~~~~~__.
TYPICAL PERFORMANCE ·CURVESVOLTAGE GAIN
AS A FUNCTION Of
AMBIENT TEMPERATURE

VOLTAGE TRANSFER
CHARACTERISTIC
4.0

1700

v• • 12 v
t-v- • -6.0V... ... ...
f.ll°J
j_ 1;;:;; ~TA• 25oc
rfLV
t_ TA· 71l°C

>

~ 1.0

~

I

1

~ 1.0

1

~

llOO

-1.0

~

z

t'......

~lG

1200
-3.0

2000

!---.

zl500

~
~

.........
1-.....

~

~

-1.0
1.0
INPUT VOLTAGE - mv

3.0

5.0

1600

0

>

1300

--- --- ... -~
-5.0

--1

y+ • l2V

>

T

T

T

v· • -6.0V

T

3.0

VOLTAGE GAIN
AS A FUNCTION Of
SUPPLY VOLTAGES

1200
800

0

INPUT BIAS CURRENTAS A FUNCTION Of
AMBIENT TEMPERATURE

1010

lll6050
TEMPERATURE - °C

40010

6070

INPUT OFFSET CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

50~..,---.-~--.-~1-T~~

3.0

14

l

COMMON MODE REJECTION RATIOAS A FUNCTION Of
AMBIENT TEMPERATURE
112 r--r---.--r---r--r--....---.

Tt---+--+-+- Iv•·12v ---1>----+---+-+--+-- v_ • 11 v --1
V • -6.0V

11
POSITIVE SUPPLY VOLTAGE - V

v· • -6.0V). 11 v I

v· • -7.0V
100 t---+--+-+- -5:o vS VcMS •5.0 V«lt---+--t--+--t-+--+---l
0

~

iii!

301---+-----t--+---+--+--+---I

!'!
~

i

~
1.0

10 t-'t-........,1:::--+----t-+---+-+---1

r--t-_..60___,..70~

I;~1-.....

~
_.50_

;:::

..........

10 l---+---1--+--4-+-'==="l'.........i00'--"""10'--"""10-"""30-_.41_~ 98t--+--~t-...

1.0
0

1010

TEMPERATURE - °C

N

Mt--+----IC--+--t--+--+---l.......,
91! 0'---10.___.10~_.30_

3060506070
TEMPERATURE - °C

100

3.5

1

v!· 11v · V • -6.0V
95

OUTPUT VOLTAGE LEVELSAS A FUNCTION OF
AMBIENT TEMPERATURE..--..,---,--r--....--r!-..-I-,y+ • 12V

3.0

P:"'i'='-f-""-"d-+--+----J

~ 2.0

r-+-

1.0 f---1---1--+---+-+--+--I...:.:_

4.0

f---1--t--+--+- ~-: ~~y __,3.0 f---1--t--+--+-+---+---I

1.5

10

10

~

~
~

LOGIC THRESHOLD VOLTAGE - t-1.0

1.5 f---1---1--+---+-+--+--I
NEGATIVE OUTPUT LEVEL

lll
60
50
TEMPERATURE - °C

60

70

RESPONSE TIME FOR
VARIOUS INPUT OVERDRIVES
4.0

':'"

3.0

~

1.0

g
~
~

1.oo~-1~0~10~"""30-_.41__..60~10

_.50_

-1.0

TEMPERATURE - °C

0ID10

lll«I
50
TEMPERATURE - °C

RESPONSE TIME FOR
VARIOUS INPUT OVERDRIVESCOMMON MODE
PULSE RESPONSE

6070

4.o~~~~..,..~~~~~

10mV
lOmY

1.0

v· • -6.0V

POSlTIVE OUTPUT LEVEL

-·
25 0

_.50_..1,60__,70_.40_

TEMPERATURE - °C

OUTPUT SINK CURRENTAS A FUNCTION OF •.
AMBIENT TEMPERATURE

POWER CONSUMPTJ.llN
AS A FUNCTION dF
AMBIENT TEMPERATURE

ID

'16

~

3.0 l=f=l5;""'1hd-+~-:-.r.+-1-+-l-l-l
z.omv
1.0 t-+-+-+-1r'<f-...,,..;:t-t-t-++-+-+-+-t

V1

l_A-s.omv\l'\1'-i.,N

12[

lLV ~~

IOmY~ II.

~

1.0 t-+-+--+L\-+<"->+T+~,....._+-t-.+--+-+-+-1-1
ZOmV
w.omv ~

N \

2.0mV

~

-1.0

V+• +12V

v-·· -6:ov t-+TA.· 25°c

100

':'"

v+:1:12v

1.0 f--+--+--+--+-+-+--+7.-v--·-"'"6v,;+---t~ 1.01-¥::+:=+:=+::+::>1--~TA ."zsocl--~

1.01--+-+--+-+--+-+--+--+--+--<

An
H--~a

t--+-

'°Ht

r-t- Vc11----t--+--+--+

1.0f---t- "" 1--1--1--f--f--~f--t

501-+-+-+-+--l-~f-+~v~~-::~~~~f-+~

50

Ti·t~
10

40

60
TIME- ns

80

100

110

10

60

60
TIME- ns

6-44

80

100

110

ID
TIME- ns

110

160

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA710B

DEFINITIONSLOGIC THRESHOLD VOLTAGE- The approximate voltage at the output of the comparator at which the loading logic circuitry changes its digital state.
INPUT OFFSET VOLTAGE- The voltage between the input terminals when the output is at the logic threshold voltage. The input offset voltage may also be
defined for the case where two equal resistances are inserted in series with the input leads.
INPUT OFFSET CURRENT - The difference in the cu.rrents into the two input terminals with the output at the logic threshold voltage.
INPUT BIAS CURRENT - The average of the two input currents.
INPUT VOLTAGE RANGE- The range of voltage on the input terminals for which the comparator will operate within specifications.
'.

INPUT COMMON MODE REJECTION RATIO - The ratio of the input voltage range to the maximum change in input offset voltage over this range.
DIFFERENTIAL INPUT VOLTAGE RANGE- The range of voltage between the input terminals for which operation within specifications is assured.
VOLTAGE GAIN- The ratio of the change in output voltage to the change in voltage between the input terminals producing it with the DC output level in thevicinity of the logic threshold voltage.
RESPONSE TIME- The interval between the application gf an input step function and the time when the output crosses the logic threshold voltage. The input step drives the comparator from some initial, saturated input voltage to an input level just barely in excess of that required to bring the output fromsaturation to the logic threshold voltage. This excess is referred to as the voltage overdrive.
POSITIVE QUTPUT LEVEL- The DC output voltage in the positive direction with the input voltage equal to or greater than a minimum specified afTlount.
NEGATIVE oµlPUT LEVEL- The DC output voltage in the negative direction with the input voltage equal to or greater than a minimum specified amount.
OUTPUT §INK CURRENT - The maximum negative current than can be delivered by the comparator.
PEAK OUTPUT CURRENT - The maximum currep,t that may flow into the output load without causing damage to the comparator.
OUTPUT RESISTANCE- The resistance seen looking into the output terminal with the DC output level at the logic threshold voltage.
POWER CONSUMPTION- The DC power into the amplifier with no output load. The DC power will vary with signal level, but is specified as a maximum forthe entire range of input-signal conditions.

6-45

µA710C
HIGH-SPEED DIFFERENTIAL COMPARATORFAIRCHILD LINEAR INTEGRATED CIRCUITS• IMPROVED SPECIFICATIONS• 5mY MAXIMUM OFFSET VOLTAGE• 5µA MAXIMUM OFFSET CURRENT• 1000 MINIMUM VOLTAGE GAIN
• 20µV/°C MAXIMUM OFFSET VOLTAGE DRIFTPHYSICAL DIMENSIONS
in accordance withJEOEC(T0·99) outline

GENERAL DESCRIPTION- The µA710C is a differential voltage comparator intended for applications requir-

ing high accuracy and fast response times. It is constructed on a single silicon chip using the Fairchild Planar*
epitaxial process. The device is useful as a variable threshold Schmidt trigger, a pulse height discriminator, a voltage comparator in high-speed A-D converters, a memory sense amplifier or a high-noise immunity line receiver. The
output of the comparator is compatible with all integrated logic forms.
··
For full temperature range operation (-55°C to +125°C) see µA710 data sheet.

F

.370~
.335

.335__J

-1

.305

.040~
_MAX.

.185
' 165

-~

Seating_l_

PianeT8 Lem~~ ~ ~~.500 MIN.016

ABSOLUTE ·MAXIMUM RATINGS

Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Internal Power Dissipation £Note 11
Operating Temperature Range
Storage Temperature Range T0-99
Dual-In-Line
Lead Temperature T0-99 (Soldering, 60 sec)
Dual-In-Line (Soldering, 10 sec)

+14.0V
-7.0V
lOmA
±5.0V
±7.0V
300mW
0°C to +70°C-ss•c to +iso•c-55°C to +12s 0 c

aoo•c
2so c

NOTES! DimtnsiOnsas,.,. latntJ·lO committee
All dimensions In Inchesl.Udl .,. aold-pllted Kovar
Pllckapwtl1htlsl.221ram1

0

ORDER PART NO.U5B771039X

T0-99 CONNECTION DIAGRAMSCHEMATIC DIAGRAM(TOP VIEW)PHYSICAL DIMENSIONS

V+

R4

Rs

2.Bkll3.9klly.

Note:

Pin 4 connected to case
NON-INVERTING
INPUT
INVERTING INPUTGROUNDNOTES: All dimensions in inches
Leads are intended for insertion in hole rows,.300 centers

ORDER PART NO.
U6E7710393• Planar is a patented Faire hi Id process.

F=AI RC 1-11 LCJ
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011, TWX: 910-379·6435

6-46

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA710C
ELECTRICAL CHARACTERISTICS (TA = 25°C, V+ = 12.0V,

PARAMETER(see definitions)v- = - 6.0V unless otherwise specified)
CONDITIONS(Note 3)

Input Offset Voltage
Input Offset Current
Input Bias Current
Voltage Gain
Output Resistance.
Output Sink Current
Response Time [Note 21

Rs

TYP.

MAX.

UNITS

5.0
5.0
25

µA
µA

1000

1.6
1.8
16
1500
200
2.5
40

s 200nAV;, ~ 5 mV, Voot = 0

The following specifications apply for 0°C

MIN.

1.6

s TA s .+70°C:
Rs s 200n

Input Offset Voltage ·Average Te~perature Coefficient of Input'
Offset Voltage
Input Offse~ Current
Average Temperature Coefficient of Input
Offset Current
Input Bias Current
Input Voltage Range
Common Mode Rejection Ratio
Differential Input Voltage Range
Voltage Gain
Positive Output Level
Negative Output Level
Output Sink Current
Positive Supply Current
Negative Supply Current
Power Consumption

mV

n
mA
ns

Rs= 50n, TA= 0°C to TA= +70°C

5.0

6.5
20

mV
µV/°C

TA=25°CtoTA= +70°C
TA= 25°C to TA= 0°C
TA = 0°C= -7.0V

15
24
25

7.5
50
100
40

µA
nA/°C
nA/°C
µA

'

vRs

s 200nAV;,~ 5 mV, 0 S loot S 5.0 mA
AV;,~ 5mV

AV;, ;::: 5 mV, Voot = 0
Vool SQ

±5.0
70
±5.0
800
2.5
-1.0
.0.5

v
98

dB

v
3.2
-0.5

4.0
0

v
v

5.2
4.6
90

9.0
7.0
150

mA
mA
mA
mW

NOTES:(1) Ratings apply for ambient temperatures to +10°C.

(2) The response time specified (see definitions) is for a 100-mV input ste'p with 5-mV overdrive.
(3) The input offset voltage and. input offset current (see definitions) are specified for a logic threshold voltage of 1.SV at

6-47o•c, 1.4V at +25•c and l.2V at +70°C.

FAIRCHILD LINEAR INTEGRATED. CIRCUITS. •. µA710C
TYPICAL PERFORMANCE CURVESVOLTAGE GAIN
AS A FUNCTION OF
AMBIENT TEMPERATURE

VOLTAGE TRANSFER
CHARACTERISTIC
4.0

1100

I

l.;v'

I- v· • -6.0 v
T/O"r

l.O

j_

I~

TA· 2S°C}*j/ I

2.0

II!_

lf21

--- --- ---

1600

1
I/
·1.0

~
ill 1600

f'...... ...........

~

~

l~

·1.0
·l.O

z

1400

--- --- --- -:J
·5.0

2QXJ

~

TA• 70"C

/

1.0

I

v'• 12V -1
v· • -6.0V

1500

-

VOLTAGE GAIN
AS A FUNCTION OF
SUPPLY VOLTAGES

1.0

5.0

l.O

INPUT VOLTAGE -.mv

1200

~>

121Xl

IWlO

o

~40~

1oro

6070

400 10TEMPERATURE - °C

INPUT BIAS CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

INPUT OFFSET CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE~.---.-~~~--.-~1-T-.--~

l.o.---.-~~~---.-,---.T~>---+---+-+---+-- ~-: ~.~ v ->---+---<1---+---+- v• • 12 v _v· • ·6.0V

11
12
ll
POSITIVE SUPPLY VOLTAGE· V

14

COMMON MODE REJECTION RATIOAS A FUNCTION OF
AMBIENT TEMPERATURE
102 ..---r---.--,.--....,T--.-_1-....-1.,>---+---+--+v• • 12 v
v· • ·7.0V
100 >---+---+--+-.5,0 VS VcMS +5.0 V

~

2.0

""

%t---+---t--+---t--+---+---l~I----+---<--+---+--+---+--<

OO.....__l~O-ro~~~~~40-~~-~60--'70

TEMPERATURE • °C

POWER CONSUMPTION
AS A FUNCTION OF
AMBIENT TEMPERATURE

OUTPUT SINK CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

100

10

10ro~40~6010

T£MPERATURE - "Cl.5
v?·12i __V • -6.0V~
40~
TEMPERATURE - "C

60

·7o

OUTPUT VOLTAGE LEVELSAS A FUNCTION OF
AMBIENT TEMPERATURE.---.---.---.-----.--.J--.-I--.
>-----+-----<--+---+- v . 12 v --1

4.0 .---.---,--.....---.--.-~---,
V+ • 12V

t---+--POS=±::n'°"1vE=--'o-uT-Pu-+1LE-VE-L-+ v· • -6•0 v

v· • -6.0V

l.O t---+---t--+---+--+---+---l

95

ro

-

l.O

~::t:==1=~==l~=*=""'*==l

2.0 t---+---t--+---1--+---+---J
LOGIC IHRESHOLO VOL7AGE-+--

2.0 t---+---t--+---+--+---+---l80

1.5 t---+---t--+---+--+---+---l

15

1.0~~~-~--+-~--+~

1.0 1---+---+--+---+--+---+---t

NEGATIVE OUTPUT LEVEL

o

10

ro

~
40
~
TEMPERATURE - °C

60

ro

o

10

ro

~
40
~
TEMPERATURE - °C60ro4.0 ,...,...-,-,......,.-,-.....,,.,..-,-,......,.-,-..,-,

4.0

i.o ~-1-W=*==~~=t=j;;::;f;~:t:=il.O

2•0 1-+-ro__,m_v.,..fi!..,.ll'-++J....,_,5.oc-mv..,..A
4 V-+--+-i--+-tlOmV ~
J/r
l.o 1-+--+--.o-[71+T7~.....
r7...,uf-+--+-+-+-+-+-t
Jt ft-12.omv

1

~ I'.

2.0

1.0

lOmV
romv

'd
~I\

K

bil.OmV

V+• +12V~~-+-+-+-+-+-11-+-+-'TA~'.~~"_cl-+~

1'l

COMMON MODE
PULSE RESPONSE

2.0t--t- .,,. +--+--+--+--+--+--<--+

100

Ti!C
120

6010

V

1.0 t---1--i

V· • ·6.0V

loo

50

~40

,.Q
HSOQ µA710
out-+--+--!
t-+f--1- ~M~r-i--+-+-+-+-+--1-1.0

V+~ +12V.80

rov+:-1:12v
3.0 t--+-+-+-+-+-+---+7.-v_-._-76v..+-~
2.o~Jt:=1f:::'.HHPJ--frA · '250 ct--1

l-+-+-+-+-+-+-11-+-tV· ', -6'.0Vt-+-1

60
TIME- nslo

TEMPERATURE • °C

21mv

K

·1.0 1-+-+-+-+-+-+-11-+-+-+-+-+-+-i

40

o

RESPONSE TIME FOR
VARIOUS INPUT OVERDRIVESRESPONSE TIME FOR
VARIOUS INPUT OVERDRIVESro-1.0~~~-~--+-~--+~

1-t-

ro406080lOOtro
TIME- ns

6-48

80
TIME- ns160

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A710C

DEFINITIONSLOGIC THRESHOLD VOLTAGE- The approximate voltage at the output of the comparator at which the loading logic circuitry changes its digital state.
INPUT OFFSET VOLTAGE- The voltage between the input terminals when the output is at the logic threshold voltage. The input offset voltage may also be
defined for the case where two equal resistances are inserted in series with the input leads.
INPUT OFFSET CURRENT - The difference in the currents into the two input terminals with the output at the logic threshold voltage.
INPUT BIAS CURRENT - The average of the two input currents.
INPUT VOLTAGE RANGE- The range of voltage on the input terminals for which the comparator will operate within specifications.
INPUT COMMON MODE REJECTION RATIO - The ratio of the input voltage range to the maximum change in input offset voltage over this range.
DIFFERENTIAL INPUT VOLTAGE RANGE- The range of voltage between the input terminals for which operation within specifications is assured.
VOLTAGE GAIN- The ratio of the change in output voltage to the change in voltage between the input terminals producing it with the DC output level in thevicinity of the logic threshold voltage.
RESPONSE TIME- The interval between the application of an input step function and the time when the output crosses the logic threshold voltage. The input step drives the comparator from some initial, saturated input voltage to an input level just barely in excess of that required to bring the output fromsaturation to the logic threshold voltage. This excess is referred to as the voltage overdrive.
POSITIVE OUTPUT LEVEL- The DC output voltage in the positive direction with the input voltage equal to or greater than a minimum specified amount.
NEGATIVE OUTPUT LEVEL- The DC output voltage in the negative direction with the input voltage equal to or greater than a minimum specified amount.
OUTPUT SINK CURRENT - The maximum negative current than can be delivered by the comparator.
PEAK OUTPUT CURRENT - The maximum current that may flow into the output load without causing damage to the comparator.
OUTPUT RESISTANCE - The resistance seen looking into the output terminal with the DC output level at the logic threshold voltage.
POWER CONSUMPTION - The DC power into the amplifier with no output load. The DC power will vary with signal level, but is specified as a maximum forthe entire range of input-signal conditions.

6-49

µA71lDUAL COMPARATORFAIRCHILD LINEAR INTEGRATED CIRCUITSGENERAL DESCRIPTION- The µA 711 is a dual, differential voltage comparator intended

PHYSICAL DIMENSIONS

primarily for core-memory sense amplifier applications. The device features high accuracy,
fast response times, large input voltage range, low power consumption and compatibility withpractically all integrated logic forms.

When used as a sense amplifier, the threshold voltage

can be adjusted over a wide range, almost independent of the integrated circuit characteristics.
Independent strobing of each comparator channel is provided, and pulse stretching on the output is easily accomplished. Other applications of the dual comparator include a window discriminator in pulse height detectors and a double-ended limit detector for automatic Go/No-go
test equipment. The µA 711, which is similar to the µA 710 differential comparator, is constructed on a 40-mil square· silicon chip using the Fairchild Planar' epitaxial process.
ABSOLUTE MAXIMUM RATINGS+14.0 v
-7.0 v
50 mA±5.0 v±7.0 v
0 to +6.0 V
300 mW
300 mW-55°C to +125°C-65°C to +150°C
300°C

Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Strobe Voltage
Internal Power Dissipation TO - 100{Note 1)
Flat-Package (Note 2)
Operating Temperature Range
Storage Temperature Range
Lead Temperature {Soldering, 60 sec.)

CONNECTION DIAGRAMSCHEMATIC DIAGRAMNOTES: All d1mens1ons in inches
Leads are gold-plated k.ovar
Package weight 1s 1.32 grams

ORDER PART NO.

U5F771131X

FLAT PACKAGEy+STROBE 1

STROBE 2

INVERTING

INVERTING
INPUT 2

INPUT 1v-

T0-100STROBE I
NON·INVERTING
INPUT 1

2

GROUNDV-

V+

NON·INVERTING
INPUT 2

4

INVERTING
INPUT 25

OUTPUTSTROBE 2

ORDER PART NO. U3T771131X

Note: Pin 3 is connected to case.

FLAT-PAK
Notes on page 2• Planar is a patented Fairchild process.

F=A.IRCHILC
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-50

A DIVISION OF FAIRCHJLD CAMERA ANO INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA711

ELECTRICAL CHARACTERISTICS{TA= 25°C, v+ = 12.0 V, V- = -6.0 V unless otherwise specified)Parameter {see definitions)

Conditions

Input Offset Voltage

Vout

Input Offset Current

Min.

= +l.4V, RS~200S1, VCM = 0

Max.

Units

1.0

3.5

mV

V out = + 1.4 v, Rs :::=: 200 n

1.0

5.0

mV

V out = + 1.4 V

0.5

10.0

µA

25

75

µA

Input Bias Current\T oltage Gain

750 1500

Response Time (Note 3)
Strobe Release Time
Input Voltage Range

Typ.

v- = -7.0 v

40

ns

12

ns

v

± 5.0

Differential Input Voltage Range

v

±5.0

Output Resistance

200

Positive Output Level

Vin? 10 mV

4.5

Loaded Positive Output Level

S1
5.0

Vin? 10 mV, I0 = 5 mA

2.5

Negative Output Level

Vin? 10 mV-1.0 -0.5

0strobed Output Level

Vstrobe ::=:o. 3 V
Vin ?10 mV, V out

-1.0

0

Output Sink Current
Strobe Current

V strobe

Positive Supply Current

V out

>O

0.5

3.5

0.8
1.2

= 10 0 m V

v
v
v
v
mA

2.'5

mA

8.6

mA

Negative Supply Current

3.9

mA

Power Consumption

130

<o

200

mW

4.5

mV

6.0

mV

Input Offset Current (Note 4)

20µA

Input Bias Current

150

µA

The following specifications apply for -55°C :::=: TA ::=:+125°C:
Input Offset Voltage {Note 4)

R 8 ::::2000, VCM=0

RS ::::: 200 S1

Temperature Coefficient of Input Offset
Voltage

5.0

Voltage Gain500

NOTES:(1) Rating applies for case temperatures to +125°C; derate linearly at 5.6 mW/°C for ambient temperatures above 105°C.
(2) Rating applies for case temperatures to +125°C; derate linearly at 2. 5 mW/°C for ambient temperatures above +40°C,(3) The response time specified (see definitions) is for a 100-mV input step with 5-mV overdrive.
(4) The input offset voltage (see definitions) is specified for a logic threshold voltage of 1.8V at -55°C, 1.4V at +25°C and 1.0V at +125°C.

6-51

µV/°C

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA711

TYPICAL PERFORMANCE CURVES

s.o

1700

I- ~+~.+12v

a,

4.0

1600

{L'

-1.0
·5.0

jff_
'!ff_

+25°C

-

-1.0

~

rs:~

+l,O

3.0

I'

1200
-60

5.0

-20

+20

+60

+100

INPUT VOLTAGE - mv

TEMPERATURE °CRESPONSE TIME FOR
VARIOUS INPUT OVERDRIVESSTROBE RELEASE TIMEFOR VARIOUS INPUTOVERDRIVESv lLl:
20mV
?Jl~

lOmV

_j_

tr/I

5.0mV

400 lO+l«J.."1~:: :!'.:v-

·1.0

6.0

gj$ 1.01---lZ~~--.--+--+--+-+--+--+---t~

14

TA • 25'C

:it

:E--

ll

12

OUTPUT PULSE STRETCHINGWITH CAPACITIVE LOADING

E

1-1 2.0mV

11

POSITIVE SUPPLY VOLTAGE - V

l.O r--,.--;,.--;r-::;:i-r---r--r--r-r-r"'"'I
V+•+l2V
2.0 1----f--lr-+-+-+--+--+- V- • -6.0V -1

5.0

2.0

~

llOO

-r_r-j_'-ss•c
-3.0

~

1400

I
+12,5°C

1.0

~

//,

l.O

l.O

~

1500

[[J_

2.0I

V+• +l2V
V- •-6.0V

"'\

r/Z__

3.0

4.0

"'\

~v

V- • -6.0V

VOLTAGE GAIN
AS A FUNCTION OF
SUPPLY VOLTAGESVOLTAGE GAIN
AS A FUNCTION OF
AMBIENT TEMPERATURE

VOLTAGE TRANSFER
CHARACTERISTIC

4.0

Ot--~f--lf--1-+--t---t--t---t--+-~Ill

TA ·25'C

~

a
>

~

100
50

0
20

40

60
80
TIME - ns

100

10

120

~
~>

~.:.

V+• +12V

3.0 1---+--+-+--t--+--t----t-V- • -6.0V
TA ·25°C
2.0

i~
s~

40

so

200
JOO
TIME - ns

so

lO

500

140r----ir----ir----ic--ic--ic--ic--i---.---.--.

~

40

400

POWER CONSUMPTION·· AS A FUNCTION OF·!·AMBIENT TEMPERATURE

INPUT BIAS CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURECOMMON MODE
PULSE RESPONSE~

20
lO
TINE - ns~

t--1--t--t-+--+-+-+V- • -6.0V--,

~

JS]

~

20

v.'•+12~~~: ~!~:v -1

i5

N

11-r--130

r--.r--..

lll

~

10

m.,_....__,....__,.___.___...__....__....__.'--''--'

0-60

TIME - ns

-20

+20
+60
TEMPERATURE - °C

6-52

+100

+l«t

-60

-20

+20

+60

TEMPERATURE - 'C

+100

+ l«l

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA711
DEFINITIONSLOGIC THRESHOLD VOLTAGE - The approximate voltage at the output of the comparator at which the loading logic circuitry changes
its digital state.
INPUT OFFSET VOLTAGE* - The voltage between the input terminals when the output is at the logic threshold voltage. The input
offset voltage may also be defined for the case where two equal resistances are inserted in series with the input leads.
INPUT OFFSET CURRENT* - The difference in the currents into the two input terminals with the output at the logic threshold voltage.
INPUT BIAS CURRENT* - The average of the two input currents.
INPUT VOLTAGE RANGE* - Therange of voltage on the input terminals for which the comparator will operate within specifications.
DIFFERENTIAL INPUT VOLTAGE RANGE* - The range of voltage between the input terminals for which operation within specifications
is assured.
VOLTAGE GAIN* - The ratio of the change in output voltage to the change in voltage between the input terminals producing it with
the DC output level in the vicinity of the logic threshold voltage.
RESPONSE TIME* - The interval between the application of an input step function and the time when the output crosses the logic
threshold voltage.

The input step drives the comparator from some initial, saturated input voltage to an input level just barely inexcess of that required to bring the output from saturation to the logic threshold voltage. This excess is referred to as the voltage
overdrive.
STROBE RELEASE TIME* - The time required for the output to rise to the logic threshold voltage after the strobe terminal has
been driven from the zero to the one logic level. Appropriate input conditions are assumed.
POSITIVE OUTPUT LEVEL* - The DC output voltage in the positive direction with the input voltage equal to or greater than aminimum specified amount.
NEGATIVE OUTPUT LEV,EL* - The DC output voltage in the negative direction with the input voltage equal to or greater than aminimum specified amount.
OUTPUT SINK CURRENT - The maximum negative current that can be delivered by the comparator.
PEAK OUTPUT CUBRENT - The maximum current that may flow into tte output load without causing damage to the comparator.
OUTPUT RESISTt.NCE* - The resistance seen looking into the output terminal with the DC output level at the logic threshold voltage.
STROBED OUTPUT LEVEL* - The DC output voltage, independent of input voltage, with the voltage on the strobe terminal equal toor les~ than a minimum specified amount.
STR0!3E CURRENT - The maximum current drawn by the strobe terminal when it is at the zero logic level.
POWER CONSUMPTION - The DC power into the amplifier with no output load.
specified as a maximum for the entire range of input-signal conditions.
*These definitions apply for either side with the other disabled with the strobe.

6-53

The DC power will vary with signal level, but isµA711C
DUAL COMPARATORFAIRCHILD LINEAR INTEGRATED CIRCUITSGENERAL DESCRIPTION- The µ.A 711C is a dual, differential voltage comparator intended
PHYSICAL DIMENSIONS

primarily for core-memory sense amplifier applications. The device features high accuracy,

In accordance with JEDEC (TO·IOO) outline

fast response times, large input voltage range, low power consumption and compatibility v·ith
practically all integrated logic forms. When used as a sense amplifier, the threshold voltage
can be adjusted over a wide range, almost independent of the integrated circuit characteristics.
Independent strobing of each comparator channel is provided, and pulse stretching on the output is easily accomplished. Other applications of the dual comparator include a window discriminator in pulse height detectors and a double-ended limit detector for automatic Go/No-go
test equipment. The µ.A 7 llC, which is similar to the µ.A 710C differential comparator, is constructed on a 40-mil square silicon chip using the Fairchild Planar epitaxial process.
For full temperature range operation (-55°C to +125°C) see µ.A 711 data sheet.
ABSOLUTE MAXIMUM RATINGS+14.0 v
-7.0
50 mA
±5.0 v±7.0 v
Oto +6.0 V
300 mW
300 mW
0°C to +70°C-65°C to +150°C
300°C

Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Strobe Voltage
Internal Power Dissipationv

TO - 100 (Note 1)
Flat-Package (Note 2)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)

CONNECTION DIAGRAMSNOTES: All dimensions in inches
Leads are gold-plated Kovar

Package weight is 1.02 grams

ORDER PART NO.

U5F771139X

SCHEMATIC DIAGRAMFLAT PACKAGEv+

STROBE 1

STROBE 2

INVERTING
INPUT 1

INVERTING
INPUT 2)~~1=u·,,~
·

gm=

L

r:::
=

L~r,f.--1

v-

-1, T
050 2so5

6_=·

l- ij~-~

T0-100STROBE 1
NON-INVERTING
INPUT 1

2

GROUNDV+

V·
NON-INVERTING
INPUT 2

4

INVERTING
INPUT 2

5

ORDER PART NO. U3T771139XOUTPUTSTROBE 2

Note: Pin 3 is connected to case.

FLAT-PAK
Notes on page 2* Planar i$ a patented Fairchild process.

l=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-54

A DIVISION OF FAIRCHILD CAMERA ANO INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITSELECTRICAL CHARACTERISTICSµA711C(TA= 25°C, v+ = 12.0 V, V- = -6.0 V unless otherwise specified)

Conditions

Parameter
Input Offset Voltage
Input Offset Current

Min.

Typ.

Max

Units

l.O

5.0

mV

vout

=+1.4V, Rs:'.S200Q, vcM=O

vout=+l.4V, Rs:'.S200Q

1.0

7.5

mV

vout

= +1.4 v

0.5

15

µA

25

100

µA

Input Bias Current
Voltage Gain

700

1500

Response Time (Note 3)

40

ns

Strobe Release Time12nsv - = -7.0 v

Input Voltage Range
Differential Input Voltage Range

±5.0

v

±5.0

v
Q

Output Resistance

200

Positive Output Level

Vin? 10 mV

Loaded Positive Output Level

Vin? 10 mV, r0 =5mA

2.5

3.5

Negative Output Level

Vin? 10 mV

-1.0

-0.5

Strobed Output Level

Vstrobe :'.S 0. 3 V
Vin? 10 mV, Vout

-1.0

Output Sink Current
Strobe Current

4.5

->o

0.5

Positive fiupply Current

v

0

v

v
0

v
mA

0.8
1.2

Vstrobe = 100 mV
vout <O

5.0

2.5

mA

8.6

mA

Negative Supply Current

3.9

mA

Power Consumption

130

230

mW

6.0

mV

10

mV

25

µA

The following specifications apply for 0°C :'.ST A ::S+70°C:
Rs:'.S200 n, VCM = 0

Input Offset Voltage (Note 4)

RS :'.S200 Q
Input Offset Current (Note 4:)
Input 1'3ias Current

150

Temperature Coefficient of Input Offset Voltage

5.0

Voltage Gain

µA
µV/°C

500

NOTES:(1) Rating applies for ambient temperatures to +70°C,(2) Rating applies for case temperatures to+ 70 °C; derate linearly at 2. 5 mW/"C for ambient temperatures above +40°C,(3) The response time specified is for a 100-mV input step with 5-mV overdrive.
(4) The input offset voltage is specified for a logic threshold voltage of 1.5V at 0°C, l,4V at +25°C and 1.2V at +70°C.

TYPICAL ELECTRICAL CHARACTERISTICSRESPONSE TIME FOR
VARIOUS INPUT OVERDRIVESVOLTAGE TRANSFER
CHARACTERISTIC
5.0

4.0

v+ • +12V.a•

V- • -0.0V

~
~

>

g

3.0

~

g

1.0

~

0

].?"""

l.O
20mV
5.0mV
2.0 1-t-+--+l--l--l<'-+--11~..<i<q--+-1--+--+--1
l.o 1--+-1om+-v+-+...,..L,..__......,l'l_,__,2.0m,_v-+--+-+-+--1

I 0 t:!:~14i~v/ILJrli--r-l.!:'!:!I

t'5
2.0

;ziz:J2OUTPUT PULSE STRETCHINGWITH CAPACITIVE LOADING-1.0 1-t-+--+-+--+-+-+--t--11-t ~~: ~ !'.~v -1,-l.0_'-5.0_.___.,,._3.0~~-l.~O-+-_,l~.0_.___..,..3.0,..--'-.,,.5.0
INPUT VOLTAGE - mv

1--+-+--+---t--t--+--t-..--,i-t-TA • 25°C -;~100 ...........-+--+--T-t--+--t-..--,>--+-+--+--+--i~

50 t-t-+--+--+--+-+-+--t--11-t-+--+--t-f~0-2.0 ~+-+--+---+--+--+--+-+--t--i'--'o--'-~20--'-~~'--'--~'-'--m'--'--1~00-'--1~20~

TIME - ns

6-55

100

200

300
TIME - ns~

500µA716
FIXED-GAIN, LOW DISTORTION AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITSGENERAL DESCRIPTION - The µA716 is a fixed-gain, medium power amplifier intended for use as a telephonesystem channel amplifier, headset amplifier or a general-purpose audio preamplifier. It provides medium
output current capability, low distortion, excellent gain stability, and wide bandwidth. Fixed voltage gainsof 10, 20, 100, and 200 are available by selecting external taps.

PHYSICAL DIMENSIONS
similar to
JEDEC(T0-99) outline

rr

.335
.370+.
.335__J
.305
·1

_l_
~:~~~
-+
.165
.185

Seating

ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Internal Power Dissipation (Note 1)
Input Voltage
Peak Output Current (TA = 25 • C)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 seconds)~
8 L~~f~ ~~ ~ ~~

27V
400mW

1

500 MIN.

.016

± 5V
100 mA- ss•c to+ 150°c- ss·c to+ 125°C
300°C
.034
028

R~

NOTES: Dimensions as per latest J·lO comm1t1ee
AU dimensions in inches
Leads are gold·plated Kovar

ORDER PART NO. U5K7716312

CONNECTION DIAGRAMSCHEMATIC DIAGRAM

Vt

...

8.2V

COMPENSATION

.,

100

Ru

OUTPUT

100

INPUT

••
6!180

R15

!U2ko

""

GND
7730

a17
3150

GND

•1•

(TOP VIEW)

6.SllmNOTE: Pin 4 internally connected to case.
GAIN TAPSNOTE 1: Ratine applies for case temperatures to +125°C; derate linearly at 8.4 mW!°C for ambient temperature above+11o•c.

FAIRCHILCSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011, TWX: 910·379·6435

6-56

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA716

DEFINITION OF TERMS
Quiescent Power Consumption - The DC power required to operate the amplifier with .no signal applied at the input and the load current equal to zero.
Total Harmonic Distortion - The ratio of the sum of the amplitudes of all signals harmonically related to the fundamental, and the amplitude of the fundamental signal.
Input Noise Voltage - The noise voltage at the output of the amplifier, divided by the amplifier voltage gain.
Output Voltage Swini- The maximum output voltage that may be obtained at the output of the amplifier before saturation occurs.
Input Resistance - The small-signal resistance seen looking into the input terminal of the amplifier.
Voltage Gain - The ratio of the small-signal output voltage to the input voltage of the amplifier.
Temperature Stability of Voltage Gain - The maximum variation of the voltage gain over the specified temperature range.

6-59

µA716C
FIXED-GAIN, LOW DISTORTION AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITSGENERAL DESCRIPTION - The µA716C is a fixed-gain, medium power amplifier intended for use as atelephone system channel amplifier, headset amplifier or general purpose audio amplifier. It provides
medium output current capability, low distortion, excellent gain stability, and wide bandwidth. Fixed voltage
gains of 10, 20, 100 and 200 are available by selecting external taps.

ABSOLUTE MAXIMUM RATINGS:
Supply Voltage
Internal Power Dissipation
Input Voltage
Peak Output Current (TA = 25 • C)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 60 seconds)

PHYSICAL DIMENSIONS

27V.500 MIN.

8 Leads.019.016

GOO mW±5V
100 mA-ss•cto +lso·co•cto +10°c
Joo·c
.034

R~

.028

NOTES: Oimensions11s per latest J-10 committee
All dimensions in inches
Leads are gold-plated Kovar

Package w8'ight is 1.22 grams

ORDER PART NO.U5B771639X

CONNECTION DIAGRAMSCHEMATIC DIAGRAMCOMPENSATIONOUTPUT

INPUT

INPUT

••

2

FREQUENCY

6

V+

3

COMPENSATION

773a

R17
3650

4
GND

...

GND

(TOP VIEW)

6.58kn~OTE:

Lead No. 4 internally connected to case

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-60

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA716C
ELECTRICAL CHARACTERISTICS (0°C:::; TA:::; 70°C, v+ = 21Vunless otherwise specified)
PARAMETER (see definitions)

CONDITIONS

Quiescent Power Consumption

TA= 25°C
Av = 10, f = 1 kHz, P0 = 50 mW, RL = 150 n
Av= 100, f = 1 kHz, Po= 50 mW, RL = 150n
R5 = 600 n, TA= 25°C, B" = 16 Hz to 150 kHz
RL = 15on
RL ~ 5kn

Total Harmonic Distortion
Input Noise Voltage
Output Voltage Swing

MIN.

Input Resistance
Output Resistance

TYP.

MAX.

UNITS

280
0.01
0.10
8.0

350
0.05
0.50

mW

10

14

15
9.0

17
11
1.0

%
%
µVrms
vp-p
vp-p

kn
n

See Table I

Voltage Gain
lOx
20x
lOOx
200x
Bandwidth

10

9.0
18
95
185
TA= 25•cTemperature Stability of Voltage Gain
lOx
20x
lOOx
200x

11
22
115
225

20
105
205
2.0

MHz

T,.1 = 25°C
±0.02
±0.02
±0.02
±0.05

±0.25
±0.25
±0.25
±0.50

TYPICAL PERFORMANCE CURVES.. !

vottAGE. GAIN
AS A FUNCTION OF FREQUENCYTRANSIENT RESPONSE

60

V+·2ll(TA• 15 C

J.
'AV= 100

I

IZ

~

l
Av•tfu

JO

~

10

0

101

io2

ui3

1o4

ui5

FREQUENCY - Hz

irf'

107

[
Av= 100v

I\]

Av '" 1 1~1

20

V+•21.i(TA•15C

Av!• 10

0.2

irJl

h_

1
\
o.4

o,6

TIME-µs

6-61

o.s

i.o

dB
dB
dB
dB

FAIRCHILD. LINEAR INTEGRATED CIRCUITS· µA716C

TYPICAL PERFORMANCE CURVESTOTAL POWER CONSUMPTION AND
INTERNAL DEVICE DISSIPATION AS
A FUNCTION OF OUTPUT POWER

TOTAL HARMONIC DISTORTION
AS A FUNCTIONOF OUTPUT POWER
1.0

V+• 21V_jL

T,\•25°C

~ 0.6

i

0
<.>

~ 0.4
;;!

g 0.2

- _,.._
0

k.~

~

w

t--1

10

~

Av • 200

All I
A'ill

1:Z1t-1 t--1
VLv---Mj"JnrJ, 1i
~---

so

20

Aj"2j_

200

500

0

1000

la3

lrf

OUTPUT POWER • mW

OUTPUT POWER· mW

A;i: l;;fl50

20, 10100

ri:.~

Av•lO~Tfl!

100 ~~-+--+--~~-+-~~~
10
100
1000
1

_ill

RL • !50 Q

i!i

1!1¥i~

Ur~b

200

f •.lkHz. -j 1----i... 0.8

IlT

V+•21V

Rl • ISOQ
T ·25°CTA• 25°C-j t--1

ii

200 >--i-+-<-+---+--+-+-++--+--+-+++--1

250v}·21i

RL • 150Qt+-+-+-++J.•11--+._1_--+..~-+.1_++--f

500 1 • lkH~ t+--+--t-1-trot..,.•l~powe...-+rco't-'ns;'um'h(e!j~on-+

POWER OUTPUT AS A FUNCTIONOF FREQUENCY
5% AND 1% THO

1o4

lrY

H

l
lrf

FREQUENCY - Hz

VOLTAGE SWING
AS A FUNCTION
OF SUPPLY VOLTAGE

RELATIVE VOLTAGE GAIN
AS A FUNCTION
OF SUPPLY VOLTAGEQUIESCENT POWER CONSUMPTION
AS A FUNCTION
OF SUPPLY VOLTAGE
500..----~---~T-~

TA ."15•c'ii
0,40,2t---;...,

.;!,

_y

I

0

t-t-i-. .% Av • 10 20

8 JOO ~-+---+--+-,,6..~==__,=----i

Pi12" r-F,g
Av•IOO~-0.2~ 1---+---t----t--+--+---t

~
le

v

~

!
!z

-0.4rAv·200-0.6 l-L+-+--+-+-1-+-+-+-+-+-+--l12g 200 t---+---+---t--+---+------1

vY

§

0

·0.8 t-+-+--+-+-i-+--+--+-+-+-+--I·LO ~-+--+-~--'--+--+-+-+-+-~

18

22

20

24

22

20

24

SUPPLY VOLTAGE· V

RELATIVE VOLTAGE GAIN
AS A FUNCTION OF
AMBIENT TEMPERATURE

22

20

SUPPLY VOLTAGE· V

24

SUPPLY VOLTAGE - V

CONNECTION DIAGRAM AND COMPONENT TABLE FOR AVAILABLE GAIN OPTIONS

1.0 ..----.--,--..--.....---.--..---.
0,8 f----+--+-+---+--+-+---+

V+

lj
T

0.6 t----+---+-+---+---+-+--1
0.4 f----t--+-+---+--+-+---+~

0.2

Av~ 10, 20

t-.....
Av •100-0.2 ~-+--+-+-"""""..........__-+-+--I-,.....
-o.4 f----+--+-+---+-~A,-'-j~200~N+-N--1

Voltage Gain

C1

c,

R1

10

68 pf

39 pf

75 (I

20

50 pf

27 pf

75 (I

8

100

None

3 pf

None

1, 7

200

None

3 pf

None

7, 8

-0.6 <-----+---+-+---+---+--+--"<-0.8 f----+--+-+--+--+-+---+·J.O ...____,___.__

o

w

20

_.___...__....._
~

~

so

_.__~

oo

ro

TABLE ITEMPERATURE - 'C

6-62

Decouple Pins:

FREQUENCYCOMPENSATIONFAIRCHILD. LINEAR INTEGRATED CIRCUITS µA716C

DEFINITION OF TERMS
Quiescent Power Consumption - The DC power required to operate the amplifier with no signal applied at the input and the load current equal to zero.
Total Harmonic Distortion - The ratio of the sum of the amplitudes of all signals harmonically related to the fundamental, and the amplitude of thefundamental signal.
Input Noise Voltage - The noise voltage at the output of the amplifier, divided by the amplifier voltage gain.
Output Voltage Swing- The maximum output voltage that may be obtained at the output of the amplifier before saturation occurs.
Input Resistance - The small·signal resistance seen looking into the input terminal of the amplifier.
Voltage Gain - The ratio of the small·signal output voltage to the input voltage of the amplifier.
Temperature Stability of Voltage Gain - The maximum variation of the voltage gain over the specified temperature range.

6-63

µA7.17E.
MULTI-PURPOSE AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITSGENERAL DESCRIPTION - The µA717E is a multi-purpose circuit designed primarily for TV sound systems
and general FM-audio applications. In TV sound systems it functions- as a 4.5 MHz amplifier, limiter and FM
detector (simple quadrature type), audio preamplifier and driver. Special features of the µA717E include(a) operation at supply voltages from 6 to 15 volts with simple rebiasing by the use of an external resistor,and (b) the option of using the microcircuit without the quadrature detector as a high gain amplifier from 100
kHz to 50 MHz.

PHYSICAL DIMENSIONS

ABSOLUTE MAXIMUM RATINGS:
Supply Voltage
Output Collector Voltage (RF Section)
Voltage Between "High Input" and "Low Input" Terminals
Power Dissipation (Note 1)
Maximum Internal Temperature (Note 2)
Operating Temperature Range
Lead Temperature (Soldering, 10 second time limit)

15V
20V
±5V
350mW
125•c
o•cto +10°c
260°C

ORDER PART NO.

U8A771739X

SCHEMATIC DIAGRAM
QUAD

RF OUTPUT
AUDIO SECTIONV+

CONNECTION DIAGRAM
2.2kll
5k0

2.2k0

5k0

3pF

(top view)

1.5
kO

HIGH
INPUT

2k0

LOW

INPUT

l.2k0

3300

3300

3300

1000

1000

GROUND

l.5k0

1.5k0

5000

RF SECTIONNOTES:(1) Rating applies for ambient temperatures from

AUDIO INPUTAUDIO OUTPUTo•c +1o•c.

to(2) Derate maximum dissipaiion by 6.4 mW/"C above 70°C.

FAIRCH-•L..CJ
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-64

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA717E
ELECTRICAL CHARACTERISTICS (TA= 25°C, v+ = 12V, Test Circuit 4 unless otherwise specified)
PARAMETER (see definitions)

CONDITIONS

Total Supply Current
Power Consumption
Audio Output D-C Bias Voltage
Voltage Gain of Audio Section
Audio Output Drive Current (clipping)
Input Voltage for -3 dB Limiting
Noise Figure
Noise Figure

MIN.

TYP.

2.0

21
250
2.6
35
20

Audio output load 250!1 applied between
pin 7 and groundf = 4.5 MHz Test Circuit 9
Rs = lk!1, f = 4.5 MHz Test Circuit 10
Rs= lk!1, f = 10.7 MHz Test Circuit 10@f

PARAMETERTEST CONDITION

Input Conductance
Input Capacitance
Output Conductance
Output Capacitance
Forward TransadmittanceGain Maximum Stable (GMS)
Gain Maximum Available (GMA)
Quadrature Conductance
Quadrature Capacitancee;n :::::; 20 mV rms
e;n :::::; 20 mV rms

e;n :::::; 20 mV rms
e;n :::::; 20 mV rms= 4.5MHz

Test Circuit 5
Test Circuit 5
Test Circuit 6
Test Circuit 6
Test Circuit 8
Test Circuit 10
Test Circuit 10
Test Circuit 7
Test Circuit 7

TYP.

@f

MAX.

0.21
12
0.05
6.0
2200
80
81
0.22
9.5

MIN.

UNITS

350
3.2

mW

mA

5.0

TYP.

MAX.

0.35
10
O~l

5_0
1200
80

71
0.35
8.0

25 ..--,---,---,---,---.--..--..---.---.----,·~

lf,"EST CIRCUIT 1
20 t--+-+-+-++-!Zt---#+--r,+--+--f---1
TEST CIRCUIT
V
15

f---t---1----h~,__._JZ_,._.._..LL__.lZ'--1-1--f---1_L JrEST CIRCUIT 2

10 t--+--+---+.1;,_y+-+-+---t--t--t--f--1

5.0

l--+-l--~-1--1--f--<---<>--<---<
SUPPLY VOLTAGE-VOLTSTEST CIRCUIT 1TEST CIRCUIT 2TEST CIRCUIT 3

v+

v+

v+
5.lk

l.2k

TOTAL SUPPLY CURRENT

6-65

UNITS
mm ho
pf
mmho
pf
mmho
dB
dB
mm ho
pf

SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

1

mVrms
dB
dB

= 10.7 MHz

TYPICAL PERFORMANCE CURVES

t--t--l--lf--1-++--t-_LF--+- I A. 25v, mA peak

1.5
7.0
7.0

MIN.

MAX.

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA717E
TYPICAL PERFORMANCE CURVESINPUT CONDUCTANCE AND
CAPACITANCE AS A
FUNCTION OF FREQUENCYOUTPUT CONDUCTANCE AND
CAPACITANCE AS A
FUNCTION OF FREQUENCYFORWARD TRANSADMITIANCE
AS A FUNCTIONOF FREQUENCY

25

10•

v•·12v
TA· 25•cv•·12vTA• 25•c~

20

2.0 .I! 15

1.5 tl

';.

v

I

'
lj

I
i

'

b-..

.. 10

0
0.1

1.0

['-.j

CONDUCTANCE...,.,,v

1.0

10

8iii:

IL

±
IZ

~

V'

N

0.5 !!!

o•cON.....,o~~~~·N=CE====~~..L.U-1.-1...U..LJO

0
100

0.1

1.0

FREQUENCY - MHz

10

!

!I

10

~

! 4D

i 4.0 H
i!

~ 20

H
2.0

0
0.1

CONDUCTANCE

16.D

i

10

1.0

0
O.OOI

100

ABSOLUTEMAXIMUM
INPUT
VOLTAGE-1

n±~ II..

';.
.:. 8.0n1v• •12VTA•u•c1t~1 no.&ll

C PACITANCE

j~

~

TII

v•·12vTA• 25•cv lcH ~

10

INPUT CONDUCTANCE AND
CAPACITANCE AS A
FUNCTION OF INPUT VOLTAGE
12

80
60

1.0

FREQUENCY· MHz

100

i=

10
0.1

100

FREQUENCY - MHz

GAIN MAXIMUM AVAILABLE(GMA) AS A
FUNCTION OF FREQUENCY

'

'b..
-sJ

[Z]

e

CAPACITANCE

I- 0.5

0.3 G

~

o.J
0.1

ill 1 l

illl
l
0.01

•

0.4 ~

:ii

~

JS:

K

'f

t-

\

0.1

1.0

i

0
10

INPUT VOLTAGE • Vrm1

FREQUENCY· MHz

TEST CIRCUIT 4

TEST CIRCUIT 5
+12V

+12V

RX METERo----Jll":!::'l-~--~OR EQUIV.~i--4':t>ir1>'~..._-t-----,

1.0kll

AUDIO INPUT
INPUT CONDUCTANCE AND CAPACITANCEMEASUREMENT CIRCUITDC AND AUDIO GAIN TEST CIRCUITTEST CIRCUIT 6+12v
RX METER
OR EQUIV.

0.1
p.F

0.1
p.F

0.01
p.F

0.01
p.F

OUTPUT CONDUCTANCE AND CAPACITANCEMEASUREMENT CIRCUIT

6-66

100

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA717E

TEST CIRCUIT 7

TEST CIRCUIT 8·-

RX METER
OR EQUIV.

+12V

O.Ol,.F

+12V

I
I
I
I
I
I

<>--t---~

I
I

50A

_ 1 1.0l'F

50A

RF
VOLTMETER

50 I
A I RF
SIGNALI GENERATOR
I
I

I'-- ---'
0.01
,.F

I-<>
O.Oll'F
1.0
l'F

0.01
l'F

QUADRATURE CONDUCTANCE AND CAPACITANCE MEASUREMENT CIRCUITFORWARD TRANSADMITTANCE MEASUREMENT CIRCUITTEST CIRCUIT 9

TEST CIRCUIT 10

+12V

+12V
O.ll'FINPUT <>-i
4.5MHz i25kHz
DEVIATION AT
400Hz

+120V
0.01
l'F

4.7kA

lie[]

15-50pF

30:1
3.0A

50A

SE703015-50pF
VIN
VouT

QUAD TANK
15S'Q'<40
560pF
0.1,.F

5.0 + 5.0 +l'F - l'F
0.05
l'F
25kA

-

68A
O.ll'F

0.011&F

O.ll'F

50A

MEASUREMENT CIRCUITTV SOUND SYSTEMNOISE FIGURE
GAIN MAXIMUM STABLE
GAIN MAXIMUM AVAILABLE

DEFINITION OF TERMS
POWER CONSUMPTION -The total power consumption of Test Circuit 1.

GAIN MAXIMUM STABLE (GMS) - This gain figure gives the maximum possible gain based on stability criteria only. This gain figure does not necessarily
represent the realizable power gain of an amplifier. For unneutralized amplifiers, the maximum practical power gain realizable based on normal circuit
tolerances is either (GMS-6 dB) or GMA, whichever is smaller.
GAIN MAXIMUM AVAILABLE (GMA) - This gain figure is the theoretical maximum power gain of an amplifier with conjugate matching at both the input
and terminals and assumes no reverse transadmittance (feedback component) in the amplifier.
INPUT LIMITING VOLTAGE - Referring to Test Circuit 9; set 25 kilohm potentiometer to give 1 watt audio output power into speaker with an input
signal of 50 mV rms. The -3 dB input limiting voltag~ is defined as the value of the input voltage when the audio output power has fallen to 0.5 watt.
For further information on the µA717E refer to Fairchild Application Bulletin No. 158, - "Two High Performance Monolithic Microcircuits For FM Sound
Systems." by David Bingham.

6-67

µA719HIGH GAIN RF AMPLIFIER/FM DETECTOR
FAIRCHILD LINEAR INTEGRATED CIRCUITS• HIGH GAIN AT 10.7 MHz• AGC RANGE
30 dB• TWO SEPARATE AMPLIFIERS• SUPPLY VOLTAGE 5 TO 15 VOLTS• OPTIONAL FM QUADRATURE DETECTOR>PHYSICAL

DllVl~~SIONS(In accordance with JEDEC T0-100)

GENERAL DESCRIPTION - The µA719 is a high gain RF amplifier /FM detector which contains two independent amplifier sections designed for IF systems to 50 MHz. Section 1 utilizes three cascaded emitter
coupled amplifiers having high gain and a reverse AGC capability. In addition, Section 1 may be used as anamplifier limiter and quadrature detector for FM systems. Section 2 is a single stage amplifier useful fromDC to 50 MHz.
ABSOLUTE MAXIMUM RATINGS
15 v
20 v
±5.0V
Oto +4.0 V±2.0V
350 mW+150°C-65°Cto +150°C-55°C to + 125°C
300°C

Supply Voltage
Output Collector Voltage (Section 1)
Voltage between "High Input l" and "Low Input 1" Terminals
Voltage between "Quad" and "Ground" Terminals
Voltage between "Input 2" and "Ground" Terminals
Power Dissipation (Note 1)
Maximum Chip Temperature
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 60 second time limit)

230 TP-,~---1

115 TPNOTES: All dimensions in inches
Leads are gold-plated Kovar
Package weight is 1.02 grams

ORDER PART NO.
U5F7719312

SCHEMATIC DIAGRAMQUADOUTPUT l
SECTION 2

SECTION 1

V+

4.0kQ

8.0kQ

CONNECTION DIAGRAM(TOP VIEW)

1.5
kQ

HIGH
INPUT 1 300Q

4.0
kQ

OUTPUT 2LOW

INPUT 1GROUND

lOOQ

330Q

9.0kQ

l.5kQ

l.5kn

500Q

INPUT 2AGC

NOTE:
(1) Rating applies for ambient temperatures to +125°C if the package case to ambient thermal resistance is lowered to 40°C/Watt by the addition of a heat dissipator.
Derate linearly 5.6 mW/°C for ambient temperatures above 87°C.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-68

A DlVJSlON OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA719
ELECTRICAL C"IARACTERISTICS (TA = 25°C, v+ = 12 V, Test Circuit 1 unless otherwise specified)
PARAMETER (See Definitions)
Supply Current
Supply Current
Power Dissipation
Power Dissipation
Section 1 Quiescent Output Current
Section 1 DC Voltage at
AGC Terminalll

TEST CONDITIONS

MIN.

TYP.

MAX.

UNITS

TA=+25°C
Tc= -55°C
Tc= +125°C
v+ = 9.0V,

12

18
17.5
17
12.5

25

mA
mA
mA
mA
mW
mW
mW

6.0

TA= +25°c
Tc= -55°C
Tc= +125°C
v+ = 9.0V,

18.5

144

216
210
204

300

54
1.0

113
2.5

0.55

0.73

167
4.0
1.25

v

250

µA

mW
mA

Section 1 AGC Current
For30 dB AGC
Section 1 Output Current

f = 10.7 MHz, Test Circuit 3

170

f = 1.0 MHz, Test Circuit 8

4.4

mAp-p

Section 1 Voltage Gainf = 10.7 MHz, Test Circuit 3
TA= +25°C
Tc= -55°C
Tc= +125°C
f = 10.7 MHz, Test Circuit 3, v+ = 9.o V

60
63
58
53

dB
dB
dB
dB

Section 1 Voltage Gain
Section 1 Input Voltage
For -3.0 dB Limitinglf = 4.5 MHz, Test Circuit 4~

f = 1.0 kHz, Test Circuit 2

4.0

1.5

R5 = 1.0 k~. Test Circuit 5
f = 4.5 MHz
f = 10.7 MHz

Section 1 Noise Figure

Section 2 DC Voltage at
Output 2
Section 2 Voltage Gain

53

mV

5.2

7.0
7.0
6.3

dB
dB

22

31

dB

10

vp-p

7.4

v

Section 2 Voltage at
Output 2 Without Clipping

f = 1.0 kHz, Test Circuit 2
f = 4.5 MHz

f = 10.7 MHz

PARAMETERS (See Definitions)

TEST CONDITIONS

TYP.

TVP.

UNITS

SECTION 1
Input Conductance
Input Capacitance

e1N :-::; 20 mV Test (:ircuit 6
e1N :-::; 20 mV Test Circuit 6

300
6.3

µmho
pf
µmho
pf

Test Circuit 9
Test Circuit 9

170
7.5
50
6.7
2200
1000
200
8.0

Test Circuit 5
Test Circuit 5

Output Conductance
Output Capacitance
Forward Transadmittance
Forward Transadmittance
Quad Conductance
Quad CapacitanceGain Maximum Available (GMA)
Gain Maximum Stable (GMS)SECTION 2
Input Conductance.,

Input Capacitance

Output Conductance

Output Capacitance

Forward TransadmittanceGain Maximum Available (GMA).,

Test Circuit 7
Test Circuit 7
Test Circuit 8
Test Circuit 8 v+ = 9.0 V

l
l
l
~

l

1

Test Circuit 10
Pin #8 Unbypassed
Pin #S Bypassed
Test Circuit 10
Pin #8 Unbypassed
Pin #8 ~ypassed
Test Circuit 11
Pin #8 Unbypassed
Pin #8 Bypassed
Test Circuit 11
Pin #8 Unbypassed
Pin #8 Bypassed
Test Circuit 12
Pin #8 Unbypassed
Pin #8 Bypassed
Pin #8 Unbypassed
Pin #8 Bypassed

6-69

130
5.4

mm ho
mm ho
µmho
pF

83
85

1400
600
330
7.0
71
78

300
360

300
460

µmho
µmho

3.3
10.4

3.3
8.7

pf
pF

250
270

260
340

µmho
µmho

5.2
8.9

5.2
8.0

pF
pF

8.0
34

8.0
34

24
35

24
32

mm ho
mm ho
dB
dB

dB
dB

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA719
TYPICAL . PERFORMANCE CURVESSECTION 1
VOLTAGE GAIN AS A FUNCTION
OF TEMPERATURE
100~~~~-.---.---.---.---.---,-.,.,
v+'-12v

SECTION 1
FORWARD TRANSADMITTANCE AS .
wk A FUNCTION OF FREQUENCY

i .l~o~1A901--+--+--+--r-r-+f • 10.7 MHz+-1

SECTION 1
FORWARD TRANSADMITTANCEAS A FUNCTION OF
SUPPLY VOLTAGE!Ok

TA~ 250~~--1~ f • 10.7 MHz

JEST CIRCUIT~1--1--1--1--+--+--+--+--+--t--l~ 701--1--1--1--+--+--+--+--+--t--lj..--"1--rlk~oof---=f==f=F-t-!==~:f:=j--t-iz_z-

ts SOt--t--t--t--t--+--+--+--+--+--1<~~1--1--1--t--t--t--+-+-+-+--1
100~1--1--t--t--+-t--+-+-+-+--t~1--1--1--1--t--+--t--t--t--t--lOl--1--1--1--t--t--r-t--t--t--l

V1

v
lZ

O..,___,'--.,__'--..,__..,__..,___,___,__,,,__,-75 -so -25 0 +25 +50 +75 +100+125+150+175

ii._,.~~~---:-'1.70-+-~----='=10'---'~~IOO

TEMPERATURE - °C

FREQUENCY - MHz

SUPPLY VOLTAGE - V

SECTION 1
INPUT CAPACITANCE AND
CONDUCTANCE AS A FUNCTION
OF INPUT SIGNAL VOLTAGE

SECTION 1
INPUT CAPACITANCE AND
CONDUCTANCE AS A
FUNCTION OF FREQUENCYSECTION 1
OUTPUT CAPACITANCE AND
CONDUCTANCE AS A
FUNCTION OF FREQUENCY

8.0
7.0

I

CAPACITANCE

6.0

1+.1JTTA· 2S°C
f= 10.7 MHz

b-

s.o
4.0
3.0
2.0

0

1.0

100

N

800

14 1--Jlllc-+--+-+-++--+--+-+++--< 100
12

7.0

9.0

13

17

IS

14

700
y+ = 12V
TA• 2S°C

12/klc++---1 5ooi;t--1 600

CAPACITANCE

lOl--c*'AP+Ac""1T'"'"AN"'"'cE---l--Hf+-+-+1--1

6.01--+-+++--+--+-+++N__,,li.....,.-+++---1300 1 ~I 11 ~·~
4.0l--+-+++--+--+-+-HILJ<-+--+-++'1----1200 ~

100

JL

2.0t--CONOUCTANCE

100

i'-c.1-'--'--LI'---'1.-0-+-"-LI.--+10----'---'--L-'---'100°

SECTION 1
AGC AS A FUNCTION
OF AGC CURRENT

f--;~'·•10.71~vMHzI~·10+-:25°c-t-- +125°C
t--=r=-:->5°c.

'

\
\
\
\1_

-20
·~

-40

0

·50

·100

-ISO

\lI

AGC CURRENT - µA

6-70

2._o
CONDUCTANCE

0.1

1.0

~
~
v
10

FREQUENCY - MHz

FREQUENCY - MHz

INPUT VOLTAGE - mV trmsl

I~ t:,.

8.01-tttt--t---..i"'l"-M+-+----kL-t+t---1400 gt-IIt--+-+++--+--+-+-++--+--+-+-t;,,....._.6001_gt--1.......

!"10

t--1 700

l'--

~

1.0

16

~

CONDUCTANCE~:i:iJv

800

10
5.0

·200

-250

100
D

100

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA719
TYPICAL PERFORMANCE CURVESSECTION 2
FORWARD TRANSADMllTANCE AS
A FUNCTION OF FREQUENCY
060

SECTION 2
OUTPUT CAPACITANCE AND
CONDUCTANCE AS A
FUNCTION OF FREQUENCYSECTION 2
INPUT CAPACITANCE AND
CONDUCTANCE AS A
FUNCTION OF FREQUENCY

t---;1m•25°C--+---+-+++--+--++++--I
A Jj_

PINI& DECOUPIED TO PINIS

30r-+- WrTH O.llJf CAPACITOR-;.....

20t--+-+++--+--+--+++--+--+-+++--I
10 !--+-+++--+--+--+++--+--+-+++--!
........................... ·······················_IT*SlPEl

i.1

1.0

10

100

i~.1~~......,.,~~.o~~"'--:1~0~~~~200

FREQUENCY • MHz

FREQUENCY • MHz

MAXIMUM INTERNAL DISSIPATIONAS A FUNCTION OF EITHERAMBIENT OR CASE TEMPERATURE

SUPPLY CURRENT AS A
FUNCTION OF
INPUT 1 SIGNAL VOLTAGE

soo

r-1

SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE
25v+. 12v
1~
MJBIE1-+v.LllOBTAINEd WITHHEAT SINK RATEDCASE TO AMBIENT

140°r1s7·~ll1'-TA -+l25°C

161--t-t-++-+l--+1-+-t'..l+-+--+-+++-;+~TEMPERATURE °Cry101--+--+--+.A----+--+--+---+---+---l

\

·~

.L

[Z

15

11

~

J

'\._ l01~!~~~-+f--'t-1·SS

1-T+.Jv

TA• 2S°C
201--TEST CIRCUIT l,"e 400

10

100

lk

s.o
0o

INPUT VOLTAGE - mVrms

~

4.0

s.o

12

SUPPLY VOLTAGE -·v

16

TEST CIRCUITSTEST CIRCUIT 1TEST CIRCUIT 2

DC MEASUREMENTS

SECTION 2 GAIN AND OUTPUT VOLTAGE SWING
+12V

V+

I SUPPLY CURRENTI QUIESCENT (OUTPUT 1)
VTUM

0.1 µF

O.lµF

I
6-71

RL • 100kll

20

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA719
TEST CIRCUITSTEST CIRCUIT 4

TEST CIRCUIT 3-3.0 dB LIMITING

10.7 MHz VOLTAGE GAIN AND AGC

AT 4.5 MHz USING A QUADRATURE DETECTOR*+12Vv+
0.1 µF

1.0kll4.7kllrl---.....__~~

0.1 µF

son

RF
L---fiF-H_...v_o-OLTMETER!--- --·!
SJ> i 0 .QT
l.O
i:10.7 MHz:: µF~µF
l ~ !RF:

L_ _____ J SIGNAL
GEN.
-=-

INPUT SIGNAL 4.5 MHz 25kHz DEVIATION AT 400 Hz. UNLOADED QUALITY FACTOR OFQUADRATURE TANK INDUCTOR IS 65.
*SEE DEFINITIONS":::'"TEST CIRCUIT 6

TEST CIRCUIT 5
SECTION I : NOISE FIGURE.
+12V
GAIN MAX. AVAILABLE.
GAIN MAX. STABLE.

SECTION 1 INPUT PARAMETERS
+12V

10ll

RX METER
OR EQUIV.

15-50pF

RF
O.lµF

0.01 µF 0.01 uF O.lµF 50ll VOLTMETER

rrr

O.luF

r

0.01 µF 0.01 iF 0.lµF

~ ~-~

J

TEST CIRCUIT 8

TEST CIRCUIT 7

SECTION I FORWARD TRANSADMITTANCE OUTPUT CURRENTSECTION I OUTPUT PARAMETERS

Vt

+12V

RX METER .
OR EQUIV.

50ll---- ---,

'

!:50
n
'

'

) eouTI

L---fif;,---1-l-'---l-O:_:.:i.O~

i RF

iL______- J\SIGNAL
GEN.

0.1 µF

O.!µF

rr

O.OlµF

O.OlµFrr

1.0µF

0.01 uF

.01

I

1iµF

.

0.01

rFoµi1pµF"::' -=-

FORWARD TRANSADMITTANCE • :~T ;o . 10 3 mmho

6-72

RF

VOLTMETER(SCOPE FORl O CURRENT TEST)"::'FAIRCHILD LINEAR INTEGRATED CIRCUITS µA719

TEST CIRCUIT 9

TEST CIRCUJT 10

SECTION 1 QUAD PARAMETERSSECTION 2 INPUT PARAMETERS
+12V

+12V

RX METER
OR EQUIV.

O.lµF..-< J-+-t--t--lf-0

I

PIN #8 BYPASS
60O.lµF .

O.OlµF

0.11
µF"'

IRX
OR METER
EQUIV.

II ~fl . .

TEST CIRCUIT 12

TEST CIRCUIT 11+12V

SECTION 2 OUTPUT PARAMETERSSECTION 2 FORWARD TRANSADMITTANCE

+12V

O.lµF

~--+------i~ETER
OR EQUIV.

Pl~ "BI·--" ~-~~ASS

PIN#8
BYPASS0lµF
0.1 µF0.1 µF

l

l l

":'

":'

"=

e

5J>!

!

L___- __ j

LfµF.lµF L1µF

Ie,N) 50a J
0.01!

RF VOLTMETER

iurl 50o

rF
0.1

-

":"

RF SiGNAL
GENERATORFORWARD TRANSADMITTANCE • J!!!l . ..L.103 mmho
81N 50

DEFINITION OF TERMS
Gain Maximum Available (GMA) - This gain figure is the theoretical maximum power gain .of an amplifier with conjugate matching. at both the input andthe output terminals and assumes no reverse transadmittance (feedback component) in the amplifier.
GMA=

j forward transadmittance I 2
4 x input conductance x output conductance· Gain Maximum Stable (GMS) - This gain figure gives the maximum possible gain based on stability criteria only. This gain figure does not necessarily represent the realizable power gain of an amplifier. For unneutralized amplifiers, the maximum power gain realizable based on normal circuit tolerances is either(GMS - 6.0 dB) or GMA, whichever is smaller.
GMSI
I reverse transad mittance I[forward transadmittance

Input Voltage For -3.0 dB Limiting - Refer to Test Circuit 4 which shows the µA719 being used as an amplifier, limiter, and FM detector (simple quadrature type with the LC tank circuit connected between pins No. 3 and No. 2). An input FM signal (carrier frequency 4.5 MHz, ±25 kHz deviation at 400 Hz)
of 50 mV rms is applied to the µA719 and the value of the recovered audio output signal (400 Hz) at pin No. 6 is noted. The -3.0 dB input limiting voltage
is defined as the value of the input voltage to produce an output voltage 3dB below the output level obtained with 50 mV rms of input signal.

6-73

pA719C
HIGH GAIN RF AMPLIFIER/FM DETECTO.R
FAIRCHILD LINEAR INTEGRATED CIRCUITS• HIGH GAIN AT 10.7 MHz• AGC RANGE
30 dB• TWO SEPARATE AMPLIFIERS• SUPPLY VOLTAGE 5 TO 15 VOLTS• OPTIONAL FM QUADRATURE DETECTOR>PHYSICAL DIMENSIONS(Jn accordance with JEDEC T0-100)

GENERAL DESCRIPTION - The µA719C is a high gain RF amplifier/FM detector which contains two inde·
pendent amplifier sections designed for IF systems to 50 MHz. Section 1 utilizes three cascaded emitter
coupled amplifiers having high gain and a reverse AGC capability. In addition, Section 1 may be used as anamplifier limiter and quadrature detector for FM systems. Section 2 is a single stage amplifier useful fromDC to 50 MHz.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Output Collector Voltage (Section 1)
Voltage between "High Input l" and "Low Input l" Terminals
Voltage between "Quad" and "Ground" Terminals
Voltage between "Input 2" and "Ground" Terminals
Power Dissipation
Maximum Chip Temperature
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 60 second time limit)

15V
20V
±5.0V
Oto +4.0V
±2.0V
350mW
+150°C-65°C to +150°Co•cto +1o•c
300°C

NOTES: All dimensions in inches
Leads are gold·plated Kovar
Package weight is 1.02 grams

ORDER PART NO.
U5F7719393

SCHEMATIC DIAGRAMQUADOUTPUT 1
SECTION 2

SECTION 1

V+

CONNECTION DIAGRAM
5.0k!l(TOP VIEW)

4.0k!l

8.0k!lV+

HIGH
INPUT 1 3000

4.0
ko

Qs

4 .0
k!l

OUTPUT 2
LOW

Qg

INPUT!

LOW

2

INPUT 1lOO!lINPUT2GROUND
500!l

INPUT 2AGC

l=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-74

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA719C.

-~

ELECTRICAL CHARACTERISTICS (TA = 25°C, v+ = 12 V, Test Circuit 1 unless otherwise specified)
PARAMETER,, (See Definitions)
Supply Current
Supply Current
Supply Current
Power Dissipation
Power Dissipation
Power Dissipation
Section 1 Quiescent Output Current
Section 1 DC Voltage at
AGC Terminal
Section 1 AGC Current
For 30 dB AGC
Section 1 Output Current
Section 1 Voltage Gain

~
~
s

l
Section 1 Voltage Gain
Section 1 Voltage Gain
Section 1 Input Voltage
For -3.0 dB Limiting
Section l Noise Figure
Sections 1 and 2 Cascaded Voltage Gainl

TEST CONDITIONS

MIN.

TYP.

MAX.

UNITS

TA= +25°C
TA= 0°C
TA= +10°c
v+ = 9.0V
v+ = 6.0V, 70°C ~TA~ 0°C
TA= +25°C
TA= 0°C
TA= +10°c
v+ = 9.0V
v+ = 6.0V, 70°C ~TA~ 0°C

12
10
10
6.0
3.0
144
120
120
54
18
1.0
0.55

18
17.5
17
12.5
6.0
216
210
204
113
36
2.5
0.73

25
27
25
18.5
10
300
324
300
167
60
4.0
1.25

mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
mA
v

f = 10.7 MHz, Test Circuit 3

170

250

µA

f = 1.0 MHz, Test Circuit 8
f = 10.7 MHz, Test Circuit 3

4.4

TA= +25°C
TA=ooc
TA= +10°c
f = 10.7 MHz, Test Circuit 3, v+ = 9.0 V
f = 10.7 MHz, Test Circuit 3, v+ = 6.0 V
f = 4.5 MHz, Test Circuit 4

50
50
48

f = 1.0 kHz, Test Circuit 2
f = 1.0 kHz, Test Circuit 2

PARAMETERS (See Definitions)

Output Conductance

Output Capacitance

Forward TransadmittanceGain Maximum Available (GMA)

70
70
70
6.5

dB
dB
dB
dB
dB
mV

7.0
7.0

dB
dB

5.2

51
56
6.3

7.4

dB
dB
v

22
7.0

31
10

40
11.5

dB
vp-p

{ Iv+~=10.7
6.0""'"""V, R = 3.0""""
kS2 13

Section 2 DC Voltage at
Output 2
Section 2 Voltage Gain
Section 2 Voltage at
Output 2 Without Clipping

Input Capacitance

60
61
59
53
38
1.5

R5 = 1.0 kS2, Test Circuit 5
f = 4.5 MHz
f = 10.7 MHz

Pin #8 Unbypassed
Pin #8 Bypassed

SECTION 1
Input Conductance
Input Capacitance
Output Conductance
Output Capacitance
Forward Transadmittance
Forward Transadmittance
Forward Transadmittance
Quad Conductance
Quad CapacitanceGain Maximum Available (GMA)
Gain Maximum Stable (GMS)SECTION 2
Input Conductance

mAp-p

~
~
~
~
~
~

f = 4.5 MHz

f = 10.7 MHz

TEST CONDITIONS

TYP.

TYP.

UNITS

Test Circuit 6, e1N ~ 20 mV
Test Circuit 6, e1N ~ 20 mV
Test Circuit 7
Test Circuit 7
Test Circuit 8
Test Circuit 8, v+ = 9.0 V
Test Circuit 8, v+ = 6.0 V
Test Circuit 9
Test Circuit 9
Test Circuit 5
Test Circuit 5
Test Circuit 10
Pin #8 Unbypassed
Pin #8 Bypassed
Test Circuit 10
Pin #8 Unbypassed
Pin #8 Bypassed
Test Circuit 11
Pin #8 Unbypassed
Pin #8 Bypassed
Test Circuit 11
Pin #8 Unbypassed
Pin #8 Bypassed
Test Circuit 12
Pin #8 Unbypassed
Pin #8 Bypassed
Pin #8 Unbypassed
Pin #8 Bypassed

170
7.5
50
6.7
2200
1000
180
200
8.0
83
85

300
6.3
130
5.4
1400
600
100
330
7.0
71
78

µmho
pF
µmho
pF
mm ho
mm ho
mm ho
µmho
pF
dB
dB

300
360

300
460

µmho
µmho

3.3
10.4

3.3
8.7

pF
pF

250
270

260
340

µmho
µmho

5.2
8.9

5.2
8.0

pF
pF

8.0
34
24
35

8.0
34
24
32

mm ho
mmho
dB
dB

6-75

FAIRCH.I~ LINEAR INTEGRATED CIRCUITS µA719C~~~~~~~~~~~~~~~~-""<v

TYPICAL PERFORMANCE CURVESSECTIONS 1 AND 2
SUPPLY CURRENT AS A
FUNCTION OF
INPUT 1 SIGNAL VOLTAGE

SECTIONS 1 AND 2
SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE
25

TEST CIRCUIT 3
V+ ~ 12V

211--t-i

1·10.1 MHz-+++--+--+-H-tv__,,...

TA • +25°C

80

f--~"1Lv

vV

18 ~H'+l--+-+-+f+--+--+-++1-1

10lZ

171--+-+-++--+--+~H--+--+-++-t----<

5.0

_L_

161--+-+-++--+--+-+-H--+---+-++-t----<

L

1 \"".o--'--'-'-,,____,,10___.-+->+-""1000--~~~1.k

v

~

20

JO

8.0
12
SUPPLY VOLTAGE - V

SECTION 1
AGC AS A FUNCTION
OF AGC CURRENT

g

V+ ~ 12V

~

~

-10

ti 10

~
~ 8.0

.l

-20

12

V-

-100
-150
AGC CURRENT - llA

FORWARD TRANSADMITTANCE ·AS
A FUNCTION OF FREQUENCY

w

~
20

(

'

~

0
0.1

100

l.O
10
FREQUENCY· MHz

SECTION 1
OUTPUT CAPACITANCE AND
CONDUCTANCE AS A
FUNCTION OF FREQUENCY

~

M

700

12 f---+-+-++-+--+-+-f+--IT A • 25°C t-- 600
TEST CIRCUIT 7 V1

.!

~

0

CAPACITANCE

v
V1

-....

~1s.ot=+CA=!P=!AC+IT::::ANC::J.E....d---l-f-l----l--l-,tl-l-l--l.m1~

~

lL

1.0

I/

t--N ~~uU!"'L ~

iL1

~

0

~~

~

t.o

2001

2.01--+CO+ND+U+-CT-AN+C£-+-+-++P1--..-+-+-++--llOO

100

ot.1::t:i:t:t::1~.o::!:J]l_~10~LllL_J1~

10
FREQUENCY • MHz

FREQl£NCY - MHz

SECTION 1
INPUT CAPACITANCE AND
CONDUCTANCE AS A FUNCTION
OF INPUT SIGNAL VOLTAGE....

TEST C! RCUl,T 6,
V+ ~ 12V

I~

~ 4.0

Ii-I"-

1.0
10s"".o-+-~7."'"o~9"".o,.......~1!,-1-+-'""'13,,__._,.,15__._-i11~

CONO UCT ANCE

3.0

- 2.0

~

t-

"1

r- t-1 100

0LO

FREQUENCY - MHz

SUPPLY VOLTAGE - V

10100
INPUT VOLTAGE - mV ~rmsl

SECTION 2
INPUT CAPACITANCE AND
CONDUCTANCE AS A
FUNCTION OF FREQUENCYSECTION 2
OUTPUT CAPACITANCE AND
CONDUCTANCE AS A
FUNCTION OF FREQUENCY .

SECTION 2
FORWARD TRANSADMITTANCE.
AS A FUNCTIONOF FREQUENCY

~

~

70

1X!2~

y+., 12V

12TA• 2_5~C-+--+-+-+-+--+--+-<

700

i"-

~

i

~

I

TA• 25°C
f" 10.7 MHz t--

6,0

~ 5.0

100

60

r-;A • 25°C.!

~ !Ot-M'"r+'-"'i'--4-..ll

50't-- TEST]C] 12;518,0 I--+-+++--+--+-+-+-+----<-++-+-+--<

40~
5 6,0 1--+-"'~-+-+-+-+-+--+-++-+-t>t--is

JO t--H!;]~ 4.0t---+-+-++--+--t-+-i-t-~-+c.....

PINl8 DECOUPLEO TO PINf5
WITH O.llJf CAPACITOR

N

20
10 ....... ..... ........ ....... ..

....... ······

fl#81PE".t_

0
O.l

6-76

~

~ 10 f--+-+-++-+--+-+-f+--+--+-IFt-t--15001 5.

CAPACITANCE

10

100

1.0
10
FREQUENCY - MHz

8.0

1.0

~

10

7.0

1i.1

PIN 18 BYPASSED~~

D'R·l.JQ

SECTION 1
FORWARD TRANSADMITTANCEAS A FUNCTION OF
SUPPLY VOLTAGE

SECTION 1~

R·I~

1"20kQTEST CIRCUIT 6

0
0.1

-250

liili. TEST Cl RCUIT 13-1

V+ ~ 12V

~ 6.0

-200

60

~

t!f- R·l.~Q

0.1

4.0

-50

12.0kQ~

TA'" 25°C

70

1

2.0'!--CONDUCTANCE

0

.J,V
~

SECTION 1
INPUT CAPACITANCE AND
CONPUCTANCE AS A
FUNCTION OF FREQUENCY

-JO

·40

~

TA· 25°C
TEST Cl RCUIT 13
Pl N I 8 UNBYP~D

0

20

16

1L
14 f--TA • 25°C

t--O"C' TA '70"Cf • 10.7 MHz

\I

Q

~

z

4.0

INPUT VOLTAGE - mVrms

TEST CIRCUIT 3

R • 3.0k

lLJ

15

19 f--+-+-++-+--JA--t.-t+--+--+++t--1

70

LI

SECTIONS 1 AND 2
CASCADED VOLTAGE GAIN AS A
FUNCTION OF FREQUENCYv•·w TT

I,[

1

_L

TA•25°cJ
20 t--TEST CIRCUIT I.

201---++++--+J_J+-t+t-----b""+~-+++--l

SECTIONS 1 AND 2
CASCADED VOLTAGE GAIN AS A
FUNCTION OF FREQUENCYv• • 6.ov I

1.010
FREQUENCY - i\1Hz

100

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA719C
TEST CIRCUITSTEST CIRCUIT 1TEST CIRCUIT ~DC MEASUREMENTS

SECTION 2 GAIN AND OUTPUT VOLTAGE SWING
+12V

V+

I QUIESCENT (OUTPUT 1)

I SUPPLY CURRENT

VTVM

O.lµF

I
TEST CIRCUIT 3

TEST CIRCUIT 4

10.7 MHz VOLTAGE GAIN AND AGC-3.0dB LIMITING AT 4.5 MHz USING A QUADRATURE DETECTOR*

v+

+12V

rt----'l!W-----.
0.1 pF

l.Okll4.7kll

0.1 µF
5011

i

--i

!1
j4.5MH'i!

:50la,--- --,.
''''
i 1iO i 0.01
1.0
ino.1 MHz!: µF~µF'"·'Ir~!L___~___!SIGNAL
!RF
GEN.

-::

':"

AUDIO
RMS VOLTMETER'---1Ji;--+:470o9 ·Hz OUTPUT

FM I ISIGNAL!
:GEN. L-- ___ J

J;:0.015µF

INPUT SIGNAL 4.5 MHz 25kHz DEVIATION AT 400 Hz. UNLOADED QUALITY FACTOR OfQUADRATURE TANK INDUCTOR IS 22.
•SEE DEFINITIONS":'-::TEST CIRCUIT 5

TEST CIRCUIT 6

SECTION 1: NOISE FIGURE.
+12V
GAIN MAX. AVAILABLE.
GAIN MAX. STABLE.

SECTION 1 INPUT PARAMETERS
+12V

1011

RX METER
OR EQUIV.

1--- ----,

:

!:

!

50i
Q l

RF :' ..... I'
SIGNAL I:
GEN. L. ____ J

O.lµF

O.luf

J

I
6-77

0.01 µF 0.01 pf O.lµF

III
':"

":"

':"

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA719C
TEST CIRCUITSTEST CIRCUIT 8

TEST CIRCUIT 7

SECTION 1 FORWARD TRANSADMITTANCE OUTPUT CURRENTSECTION 1 OUTPUT PARAMETERS

V+

+12V

RX METER
OR EQUIV.

500.

:---- ---1'

J5o iI RFla

0.01pF

L-~.£J,.--+-+--+--l~l'--O!L_ _____,.,, ;!SIGNAL
GEN.

0.1 pF

O.lµF

0.01 µF

rr

RF
VOLTMETER(SCOPE FOR
10 CURRENT TEST)

0.01 µF

rr

1.0µF

1eoor

0.01 uF.01

0.01

I rFo,;i1p~F

~µF

-=-

-=- ':"

FORWARD TRANSADMITTANCE • :~ · ~O · 103 mmho

TEST CIRCUIT 10

TEST CIRCUIT 9

SECTION 2 INPUT PARAMETERSSECTION 1 QUAD PARAMETERS
+12V

+12V

RX METER
OR EQUIV.
O.lµF

I

Pl N # 8 BYPASS

o

6
O.lµF

O.lI
µF ~

I

rrFDf
0.01

= -:

TEST CIRCUIT 11

RX METER
OR EQUIV.

-:TEST CIRCUIT 12+l2V

SECTION 2 OUTPUT PARAMETERSSECTION 2 FORWARD TRANSADMITTANCE

+12V
O.lµF

Pl~ *81·--- ~-~~ASS

e1N! 500lµF
0.1 µF

r

0.01

LfµF~

O.lµF

l

:i

!

~
o:
!

'burf 500c[,___~ __J

RF SiGNAL
GENERATOR
3
FORWARD TRANSADMITTANCE •our . ..L.10 mmho
e1N 50e

6-78

RF VOLTMETER

I

0.1
µF

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A719C
TEST CIRCUIT 13
SECTION I AND 2 CASCADED VOLTAGE GAINv•=s.ov

RF

VOLTMETERRFSIGNALGEN.

r-- - - ,
I

I

:

5rul:

I
I

I
I

I
I
~

I
I

I._ _ _ _ _ .JI

DEFINITION OF TERMS
Gain Maximum Available (GMA) - This gain figure is the theoretical maximum power gain of an amplifier with conjugate matching at both the input andthe output terminals and assumes no reverse transadmittance (feedback component) in the amplifier.
GMA

=

I

forward transadmittance 1 2

4 x input conductance x output conductanceGain Maximum Stable (GMS) - This gain figure gives the maximum possible gain based on stability CJ'l~ria only. This gain figure does not necessarily repre·
sent the realizable power gain of an amplifier. For unneutralized amplifiers, the maximum power gain realizable based on normal circuit tolerances is either(GMS • 6.0 dB) or GMA, whichever ls.smaller.
GMS=

I·forward transadmittance I
I reverse transadmittance I

Input Voltage For -3.0 dB. Limiting - Refer to Test Circuit 4 which shows the µA719C being used as an amplifier, limiter, and FM detector (simple quad·
rature type with the LC tank circuit connected between pins No. 3 and No. 2). An input FM signal (carrier frequency 4.5 MHz, ± 25 kHz deviation at 400 Hz) ·of 50 mV rms is applied to the µA719C and the value of the recovered audio output signal (400 Hz) at pin No. 6 is noted. The -3.0 dB input limiting voltage
is defined as the value of the input voltage to produce an output voitage 3dB below the output level obtained with 50 mV rms of 'input signal.

6-79

µ.A72210-BIT CURRENT SOURCEFAIRCHILD LINEAR INTEGRATED CIRCUITS• 8 ::t: lh BIT ACCURACY FROM o·c TO +ss·c• 7::t:lfz BIT ACCURACY FROM -20°C TO +ss•c• 600 ns SWITCHING SPEED• INTERNAL PRECISION REFERENCE• CCSL COMPATIBLE

PHYSICAL DIMENSIONS(TYPICAL FLAT PACKAGE)(TOP VIEW)

GENERAL DESCRIPTION- The µA722 is a high-speed, 10-bit precision ~~.rent source intended for use incurrent-summing digital-to-analog converters.or as the feedback element in successive approximation analogto-digital converters. It is constructed on a single silicon chip, using the Fairchild Planar• epitaxial process,and consists of a reference supply, 10 current sources connected to a single output summing line, andassociated logic switches. The full-scale current and coding format are set by an external resistor array, which
may be preselected and fixed for general usage or trimmed for greater accuracy. The µA722 is compatible
with the Fairchild families of linear and digital circuits.

ABSOLUTE MAXIMUM RATINGS
Voltage from v+ to vVoltage from Output to v+
Voltage from Output to vVoltage from Logic Inputs to Output
Voltage from Logic Inputs to v+
Voltage from Logic Inputs to vi nternal Power Dissipation (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)

-0.5Vto +18V
-12Vto+6V
OVto +12V-9Vto +7V.-18VtoOV
OVto +12V
450mW-20°C to +85°C-65°C to +1so 0 c
300°C

EQUIVALENT CIRCUIT

o0'01 fo ooOo"D or
Ii
ORDER PART NO. U3M7722333

CONNECTION DIAGRAM(TOP VIEW)
BIT CONTROL LOGIC INPUTS- - CURRENT
SOURCESPRECISION
VOLTAGESOURCEDDDDDDDDDDDD

13 14 15 16 17 18 19 20 21 22 23 24
y- I REI RE2 RE3RE4REsRE6RE7REsRE9RE10
FREQ>
v
'
COMP.
OUTPUTS TO RESISTOR ARRAYNOTE: PIN 13 INTERNALLY CONNECTED TO CASE,

Notes on Page 2*Planar is a patented Fairchild process.

F=AI RC 1-11 LCJ
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW. CALIFORNIA. (415) 962-5011. TWX: 910-379-6435

6-80

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA722

ELECTRICAL CHARACTERISTICSPARAMETER(See Definitions)

CONDITIONS(Note 2)

Resolution
Absolute Error

TA=25°C
0°c::::; TA::::; +55°C-20°c ::::; TA ::::; +85°c

Output Current
Full-Scale

UNITS
Bits

±.07
. ±.10

±.20
±.20

%
%

±.13

±.39

%

2560

3000

±.002
±.06

±.25

µA
µA

±0.l

%/%

i::.v+ = i::.v- = ±5%Power Supply Rejection
Output Resistance

0.2

1.2
600

2.1

2.5

Switching Speed
Logic Input High Voltage

MAX.

10

2160

Logic Inputs = 0.4 V
Logic Inputs = 2.5 V

Zero-Scale

TYP.

MIN.

Logic Input Low Voltage

0.4Power Consumption

165

Mn
ns

v

v

0.7
250

mW

NOTES:(1)

Rating applies for ambient temperatures to +85°C.

(2) Unless otherwise specified, TA= 25'C, v+ = 6.0 V ± .01 V, v- = -6.0 V ± .01 V, Vo"+= O V, C1 = 200 pF, and external resistor array as per Table 1.
(3) In Table 1, the maximum absolute value tolerance for REI = ± 10%.

TABLE lBINARY CODE RESISTOR ARRAY
FOR 8 ± 1/z BIT ACCURACY

TYPICAL FULL-SCALEOUTPUT CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE
Resistor
Number(REJ)·Olxl i1~····~l
·0.2

·O.J

r--

-I

L+-i

j

f--+--+-l+--+-t+-t ~ Jj

t-+-+--+-i-~

u t-t-+tt

m

®

m

m

~

H::MPERATURE - C

6-81

NominalValue(kn)Nominal
Ratio(REJ/RE,)

Max. Ratio
Tolerance(TA= 25°c)(%)

Max. Ratio
Temp. Coeff.
(ppm/°C)

2.547

1.000

Note 3

5.094

2.000

..!:0.02±5

10.245

4.022

±0.05

±10

±5

20.60

8.088

±0.10

±20

41.43
81.93

16.265
32.17

±0.20
±0.20

±20
±50

163.4

64.16

±0.50

±100

325.7

127.9

±1.0

±200

644.9

253.2

±2.0

±500

1275

500.8

±2.0

±500

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A722
TYPICAL DIGITAL-TO-ANALOG CONVERTERDATA REGISTERPARALLEL DATA INSERIAL DATA IN
RESET
FULL-SCALE ADJUST+6.0V----t
200pF-6.ov--...--t~---<)ANALOG DATA OUTPUTTYPICAL ANALOG·TO·DIGITAL CONVERTER.--P-R-D-GR_A_M_M-ER--...-~~[~~: /STOP CONVERSION

AND

RESET
PARALLEL DATA OUTCOMPARATOR DECISION+6.ov--~

200pF-6.0V __...._~

BUFFER AMPLIFIER

DEFINITION OF TERMS
FULL SCALE OUTPUT CURRENT - The output current for all bits turned on.
ZERO SCALE OUTPUT CURRENT - The output current for all bits turned off.
ABSOLUTE ERROR- The worst-case deviation from a straight line drawn through zero and the 25°C value of the full-scale output current.
POWER SUPPLY REJECTION - The ratio of the percentage change in full-scale output current to the percentage change in supply voltage producing it.
OUTPUT RESISTANCE- The resistance seen looking into the output terminal with the output at virtual ground and all bits turned on.
SWITCH I NG SPEED - The time required to turn on the least significant bit.
LOGIC INPUT HIGH VOLTAGE- The minimum voltage

arlow~dat a bit control gate to hold the bit off.

LOGIC INPUT LOW VOLTAGE- The maximum voltage allowea at a bit control gate to hold the bit on.
POWER CONSUMPTION - The DC power required to operate the device; the power will vary with logic condition, but is specified as a maximum forthe entire range of signal conditions.

6-82

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA722

SCHEMATIC DIAGRAMBIT CONTROL LOGIC INPUTSFREQUENCY COMPENSATION

14

V'

65
7

12

R12
1.8kQ

D13
6.2V

Rg
3.Bko

Rlo

R11

3.6k

3.BkC!

Q

R1
3.6kQ

13

v-

17

19

21

RE3

RE5

Rn

OUTPUTS TO RESISTllll ARRI!

6-83

23
Rm

µA722B
10-BIT CURRENT SOURCEFAIRCHILD LINEAR INTEGRATED CIRCUITS• 7 ±1/z BIT ACCURACY FROM o·c TO +ss·c• 6 ± 1/z BIT ACCURACY FROM -20°C TO +ss·c• 600 ns SWITCHING SPEED• INTERNAL PRECISION REFERENCE• CCSL COMPATIBLE

PHYSICAL DIMENSIONS(TYPICAL FLAT PACKAGE)(TOP VIEW)

GENERAL DESCRIPTION - The µA722B is a high-speed, 10-bit precision current source intended for use incurrent-summing digital-to-analog converters or as the feedback element in successive approximation analogto-digital converters. It is constructed on a single silicon chip, using the Fairchild Planar* epitaxial process,and consists of a reference supply, 10 current sources connected to a single output summing line, andassociated logic switches. The full-scale current and coding format are set by an external resistor array, which
may be preselected and fixed for general usage or trimmed for greater accuracy. The µA722B is compatible
with the Fairchild families of linear and digital circuits. For higher accuracy, see µA722 data sheet.

ABSOLUTE MAXIMUM RATINGS
Voltage from v+ to vVoltage from Output to v+
Voltage from Output to vVoltage from Logic Inputs to Output
Voltage from Logic Inputs to v+
Voltage from Logic Inputs to vlnternal Power Dissipation (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)

-0.5 V to +18 V-12Vto+6V
0Vto+l2V-9Vto +7V
-18VtoOV
OVto +12V
450mW-20°c to +ss•c-Gs 0 c to +1so 0 c
300°c

EQUIVALENT CIRCUITORDER PART NO. U3M7722334

CONNECTION DIAGRAM(TOP VIEW)
BIT CONTROL LOGIC INPUTS69_CURRENT
SOURCESPRECISION
VOLTAGESOURCEDDDDDDDDDDDD

13 14 15 16 17 18 19 20 21 22 23 24
y- ' Rn RE2 R£3R[4RE5RE6RE7REBRE9R£10
FREQ~
v
I
COMP.
OUTPUTS TO RESISTOR ARRAYNOTE: PIN 13 INTERNALLY CONNECTED TO CASE.

Notes on Page 2*Planar is a patented Fairchild process.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-84

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA722B

ELECTRICAL CHARACTERISTICSPARAMETER(See Definitions)

CONDITIONS(Note·2)

Resolution
Absolute Error

MIN.

TA=25°C
0°C ::::; TA ::::; +55°C-20°c ::::; TA
+85°C

±.08

±.17
±.22

s

Output Current
Full-Scale

Logic Inputs= 0.4 V

Zero-Scale

Logic Inputs= 2.5 V

2160

t.v+ = t.v- = ±5%Power Supply Rejection

TYP.

Output Resistance

0.2

Switching Speed
Logic Input High Voltage

2.1

Logic Input Low Voltage
Power Consumption

2560
±.002
±.06
1.2
600
2.5
0.4
165

MAX.

UNITS

10
±.39
±.39
±.78

Bits

3000
±.25
±0.1

µ.A

%

%
%

µ.A

%/%

Mn
ns

v

v

0.7
250

mW

NOTES:(1) Rating applies for ambient temperatures to +85°C.
(2) Unless otherwise speci.fied, TA= 25°C, v+ = 6.00 V ± .01 V, v- = -6.00 V ±(3) In Table 1, the maximum absolute value tolerance for REI=± 10%.

.01 V, Voot = 0 V, C1 = 200 pf, and external resistor array as per Table I.

TABLE 1
BINARY CODE RESISTOR ARRAYFOR 6 :!: Vz BIT ACCURACY

TYPICAL FULL-SCALEOUTPUT CURRENTAS A FUNCTION Of
AMBIENT TEMPERATURE+0.2~~~~~~~~1~~!+--+--<+ 0.1 t--t--t--t--t--+-+-ir-+-+-

1--t-+ . +---+--j - - --+--+--t- -+--1v~·--rj__...,,__ __, _ _,~--t--H--t --t---t---+-·t

-0.1

I/

L

I

IL....---r---r----t---t--t--t--+--1-"--lr-+ - j----0. 2 l--+--1--+--+--+-+-i--+--I--+--+--<

20

40

60

11:.MPERATURE - 'C

80

l[)()

Resistor
Number(REJ)

NominalValue(kn)Nominal
Ratio(REJ/RE,)

2.547
5.094
10.245
20.60
41.43
81.93
163.4
325.7
644.9
1275

1.000
2.000
4.022
8.088
16.265
32.17
64.16
127.9
253.2
500.8

Max. Ratio
Tolerance(TA= 25°C)(o/o)

Note 3

±0.10
±0.20
±0.20
±0.50
±0.50
±1.0
±1.0
±5.0
±5.0

Max. Ratio
Temp. Coeff.
(ppm/°C)

±20
±20
±50
±50
±100
±100
±500
±500
±1000
±1000

. FAIRCHILD LINEAR INTEGRATED CIRCUITS µA722B
TYPICAL DIGITAL-TO-ANALOG CONVERTERDATA REGISTERPARALLEL DATA INSERIAL DATA IN
RESET
FULL-SCALE ADJUST+&.ov---1-s.ov---1>----o ANALOG DATA OUTPUTTYPICAL ANALOG-TO-DIGITAL CONVERTERCOMPARATOR DECISION+6.0V-----mi-s.ov _..............

BUFFER AMPLIFIER

DEFINITION OF TERMS

FULL SCALE OUTPUT CURRENT - The output current for all bits turned on.
ZERO SCALE OUTPUT CURRENT-The output current for all bits turned off.
ABSOLUTE ERROR - The worst-case deviation from a straight line drawn through zero and the 25°C value of the full-scale output current.
POWER SUPPLY REJECTION - The ratio of the percentage change in full-scale output current to the percentage change in supply voltage producing it.
OUTPUT RESISTANCE- The resistance seen looking into the output terminal with the output at virtual ground and all bits turned on.
SWITCHING SPEED- The time required to turn on the least significant bit.
LOGIC INPUT HIGH VOLTAGE- The minimum voltage allowed at a bit control gate to hold the bit off.
LOGIC INPUT LOW VOLTAGE-The maximum voltage allowed at a bit control gate to hold the bit on.
POWER CONSUMPTION - The DC power required to operate the device; the power will vary with logic condition, but is specified as a maximum forthe entire range of signal conditions.

6-86

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA722B

SCHEMATIC DIAGRAMBIT CONTROL LOGIC INPUTSFREQUENCY COMPENSATION

14

y+

12

R12
1.Bkn

Oz3

R9
3.BkQ

6.2V

R1&
2.4k
Q

R10

Rn

3.&k

3.BkQ

Q

R7

Rs

3.&kQ

2.&ku

13

v-

16

18
R14

R12

20

Ru
OUTPUTS TO RESISTOR ARRAY

6-87

21
REJ

22

Ru

24
Ri10

µA723PRECISION VOLTAGE REGULATORFAIRCHILD LINEAR INTEGRATED CIRCUITS• POSITIVE OR NEGATIVE SUPPLY OPERATION• SERIES, SHUNJ, SWITCHING OR FLOATING OPERATION• .01% LINE AND LOAD REGULATION• OUTPUT VOLTAGE ADJUStABLE FROM 2 TO 37 VOLTS• OUTPUT CURRENT TO 150 mA WITHOUT EXTERNAL PASS TRANSISTORPHYSICAL DIMENSIONS:~~~DIA,,___ _ __.,

GENERAL DESCRIPTION - The µA723 is a monolithic voltage regulator constructed on a single silicon chipusing the Fairchild Planar* epitaxial process. The device consists of a temperature compensated reference
amplifier, error amplifier, power series pass transistor and current limit circuitry. Additional NPN or PNP
pass elements may be used when output currents exceeding 150 mA are required. Provisions are made foradjustable current limiting and remote shutdown. In addition to the above, the device features low standby
current drain, low temperature drift and high ripple rejection. The µA723 is intended for use with positiveor negative supplies as a series, shunt, switching or floating regulator. Applications include laboratory power
supplies, isolation regulators for low level data amplifiers, logic card regulators, small instrument power
supplies, airborne systems and other power supplies for digital and linear circuits.
ABSOLUTE MAXIMUM RATINGS
Pulse Voltage from v+ to v- (50 msec)
Continuous Voltage from v+ to vlnput-Output Voltage .Differential
Current from Vz
Current from VREF
Internal Power Dissipation Metal Can (Note 1)
DIP (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec.)

50V
40V
40V
25 mA

15 mA
800mW
900mW
-55°C to +125°C-65°c to +150°c
300°C

EQUIVALENT CIRCUITNOTES: All dimensions in inches
Leads are gold-plated Kovar
Package weight is 1.32 grams

ORDER PART NO. U5R7723312

TYPICAL DUAL IN-LINE PACKAGECONNECTION DIAGRAMSTOP VIEWS.290
lr: .310~

CURRENT
LIMIT

A
''
'

Vt

FREQUENCYCOMPENSATION

INVERTING
INPUT

Vt

NON·INYERTING
INPUT

Y-

Vour
VOLTAGEREFERENCEAMPLIFIER

NC 1

Vz
V-

CURRENT LIMITCURRENT SENSE
INVERTING INPUT 4

u

14 NC

~~~~i:~lnoN

13
12 Vt
11 Ye

10 Your

NON·INYERTING INPUT
VREF 6

9 Yz

V-

8 NC

7

Note: On metal can, pin 5 is connected to case

Notes on Page 2.

NOTES: All dimensions in inches· Leads are intended for insertion
in hole rows, .300 centers

ORDER PART NO. U6A7723393*Planar is a patented Fairchild process.

FAIRCHILCSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011, TWX: 910·379·6435

6-88

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA723
ELECTRICAL CHARACTERISTICS (Note 2)
TYP.

MAX.

UNITS

V1N = 12 V to V1N = 15 V

.01

0.1

%Your

= 12 v to v,N = 40 v

.02

0.2

% Your

0.3% Your

PARAMETER (see definitions)

CONDITIONSLine Regulation

V1N

MIN.

-55°C ::;; TA ::;; +125°C, VIN= 12 v to VIN= 15 v
Load Regulation.03

IL= 1 mA to IL= 50 mA

0.15
0.6

-55°C ::;; TA ::;; +125°C, IL = 1 mA to IL = 50 mA
f = 50 Hz to 10 kHz, Cm= 0

74

dB

f = 50 Hz to 10 kHz, CREF = 5 µF

86

dB

Average Temperature Coefficientof Output Voltage-55°C ::;; TA ::;;. +125°C.002

Short Circuit Current Limit

Rsc = 10 n, Your= 0

65

Ripple Rejection

6.95

Reference Voltage
Output Noise Voltage

BW = 100 Hz to 10 kHz, CREF = 0

20

BW = 100 Hz to 10 kHz, CREF = 5 µF

2.5

2.3

IL = 0, VIN = 30 v

%!°C
mA

7.35

0.1

Long Term Stability
Standby Current Drain

7.15

.015

v

%/1000 hrs
3.5mA

Input Voltage Range

9.5

40

v

Output Voltage Range

2.0

37

v

Input-Output Voltage Differential

3.0

38

v

DEFINITION OF TERMSLINE REGULATION - The percentage change in output voltage for a specified change in input voltage.
LOAD REG\lLATION - The percentage change in output voltage for a specified change in load current.
RIPPLE REJECTION - The ratio of the peak to peak input ripple voltage to the peak to peak output ripple voltage.
AVERAGE TEMPERATURE COEFFICIENT OF OUTPUT VOLTAGE- The percentage change in output voltage for a specified change in ambient temperature.
SHORT CIRCUIT CURRENT LIMIT - The output current of the regulator with the output shorted to the negative supply.
REFERENCE VOLTAGE- The output of the reference amplifier measured with respect to the negative supply.
OUTPUT NOISE VOLTAGE- The· rms output noise voltage with constant load and no input ripple.
STANDBY CURRENT DRAIN - The supply current drawn by the regulator with no output load and no reference voltage load.
INPUT VOLTAGE RANGE- The range of supply voltage over which the regulator will operate.
OUTPUT VOLTAGE RANGE- The range of output voltage over which the regulator will operate.
INPUT-OUTPUT VOLTAGE DIFFERENTIAL- The range of voltage difference between the supply voltage and the regulated output voltage over which theregulator will operate.
SENSE VOLTAGE- The voltage between current sense and current limit terminals necessary to cause current limiting.
TRANSIENT RESPONSE- The closed-loop step function response of the regulator under small-signal conditions.

NOTES:(1) Derate metal can package at 6.8 mW!°C and dual-in-line package at 9 mW/°C for operation at ambient temperatures above 25°C.
(2) Unless otherwise specified, TA= 25°C, V1N = v+ =Ve= 12 V, v- = 0, v.,+ = 5 V, IL= 1 mA, Rsc = 0, C1 = 100 pF, CREF = 0 and divider impedance as seen byerror amplifier :s; 10 KO connected as shown in Fig. 1.
(3) L1 is 40 turns of #20 enameled copper wire wound on Ferroxcube P36/22-3B7 pot core or equivalent with 0.009" air gap.
(4) Figures in parentheses may be used if R1/R2 divider is placed on opposite of error amp.
(5) Replace R1/R2 in figures with divider shown in figure 13.
(6) v+ must be connected to a +3 V or greater supply.

6-89

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A723
TYPICAL PERFORMANCE CURVES
MAXIMUM LOAD CURRENTAS A FUNCTION OF
INPUT-OUTPUT VOLTAGE
DIFFERENTIAL

LOAD REGULATIONCHARACTERISTICS WITHOUTCURRENT LIMITING

LOAD REGULATIONCHARACTERISTICS WITH
CURRENT LIMITING~.--,..-.--.--.--,--,~TJ_Mf.X__,"l=~=c--.

l--t---1--1--1--1--+ RTH • ISO"C/W _PsTANDBY. 60mW
160 >-r-1--+---+---+---+---+-__,_ !No heat sin kl-~~~ ~:loocc-""'l~N=--1

J;-0,05"'~ -0.l~~ -0.1 1--+-+----+---+-+--'"""'-)'....'
l"'KlJ~ K-0.IS~-o.oo~~ -0.15 t--+-+--+--+--+-<>----+--+---+--+-+---<>--+-+-+--+--+--+---+---+-"""1-~+->I-0.2

VouT -+SV, v,N. +12V,
Rsc • lOQ
t-+-+-+-+-+-1-0.25 ~~--+-~~>------+--+---+-_._...........
0
to
IS
20
2S
30

LOAD REGULATIONCHARACTERISTICS
WITH CURRENT LIMITINGOUTPUT CURRENT· mA

OUTPUT CURRENT· mA

CURRENT LIMITING
CHARACTERISTICSCURRENT LIMITING
CHARACTERISTICS AS A
FUNCTION OF JUNCTIONTEMPERATURE~ 0.8 l--+-+-+-+-'+--1+-+--+--+----l!;:;g~ 0,6 l--+-+-+-+-'+--1+-+--+--+----l~,,....

,,. H-;... 1-t-----1~ 0,4 t--+--+---+---+- " t- "t-t- . t-+--1~1-1r+~l-t-----1
I

ii!
0.2

0'--'--'--'--'--~1~~~~
0
20
40
60
100

0,3 ........
-50

OUTPUT CURRENT· mA

LINE REGULATION AS A
FUNCTION OF INPUT-OUTPUT
VOLTAGE DIFFERENTIAL

LOAD REGULATION AS A
FUNCTION OF INPUT-OUTPUT
VOLTAGE DIFFERENTIAL

+0,3

+0.2

~

l.

~

_,.

~

0>--t--1--t--+--+--+-+-+-+--t-+-+-~iil-0,l

s.o

-0.2
·S

4.0

!Z 3,0

1i,..

35

45

TA• "25oC

20

30

~

k'.'.'.'.f""'"

l.O

2S

TA• ·S5°C

~

JL

~

IS

IL......

lZ

~ 2.0

-5

+ISO

Vo1uT • VREF
IL•O

ii!

VIN• +l2V-0.2 Vour. +SV
Rsc •OTA•25°C·0,3 IL•lmAtolL •50mA

·0.l

+100

STANDBY CURRENT DRAIN
AS A FUNCTION OF
INPUT VOLTAGE+0,11--1--1--+-+-+-+-+-+-+--t

J'50

JUNCTION TEMPERATURE • °C

+0.2 .--...--...--.--.--.--....-....-....-..---.

VoUT • +5V

Rsc •O
TA. +2SOC
IJ.V • +3V
I • lmA........__..

~.__.__..._...._.__.__.

BO

OUTPUT CURRENT • mA

D

D

ID

50

INPUT VOLTAGE - V

LINE TRANSIENTRESPONSE
6.o·

1

4.0

1Jirr~LTA~

LOAD TRANSIENTRESPONSE
4.0

1

lL

g

~

Ii": CL• lllf

r--11-11l,t--r-~OLTAGE--+---+---+----t ·10i"'t7.--'-c=t.--+-+-H~--lf---+--+--+----t~
V1N·+12v
IV

V1

D.I

-4.o Vour • .sv -+---+---+----+--+--+--+--+-2.0 Your= t5VIL •40mA

IL •lmA

TA. 25°C

TA •25°C
Rsc • 0
-4.0
-5

J_ l

4.0 1--t+---tt-+-+--+-+---+--+--+---t~TAGE

VIN• +12V

s.o i---tt'.L>--=t--+-+--+ll,._..__,_+--+--+

v0ur·+sv
VIN• +I2V
Rsc •OTA• +2SoC
ll •50mA

1.0

IL

itb...

to2.0 I"

2.0

OUTPUT IMPEDANCE AS A
FUNCTION OF FREQUENCY

IS

25

35

45

-6.0

-8,0 Rsc •O-5·-·-+---+---+--+---+-----+--+'--! ·30
25

IS

TINE ·!JS

6-90

35

.DI
100

lk

!Ok

FREQUENCY - Hz

IOOk

IM

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA723
TABLE IRESISTOR VALUES (kn) FOR STANDARD OUTPUT VOLTAGESPOSITIVEOUTPUT VOLTAGE
+3.0
+3.6
+5.0
+6.0
+9.0
+12
+15
+28
+45
+75

APPLICABLE
FIGURES(Note 4)

FIXED OUTPUT
±5%
R,
Ri

1, 5, 6, 9,
4.12
12 (4)
1, 5, 6, 9,
3.57
12 (4)
l, 5, 6, 9,
2.15
12 (4)
1, 5, 6, 9,
1.15
12 (4)
2, 4, (5, 6, 1.87
12, 9)
2, 4, (5, 6, 4.87
9, 12)
2, 4, (5, 6, 7.87
9, 12)
2, 4, (5, 6, 21.0
9, 12)
7
3.57
7
3.57

OUTPUT ADJUSTABLE± 10% (Note 5)
R,
P,
Ri

NEGATIVEAPPLICABLE
OUTPUT VOLTAGE
FIGURESFIXED OUTPUT
±5%
R,
Ri

5% OUTPUT
ADJUSTABLE ±10%
R,
P,
Ri

3.01

1.8

0.5

1.2

+100

7

3.57

102

2.2

10

91

3.65

1.5

0.5

1.5

+250

7

3.57

255

2.2

10

240

4.99

.75

0.5

2.2

-6 (note 6)

3, (10)

3.57

2.43

1.2

0.5

.75

6.04

0.5

0.5

2.7

-9

3, 10

3.48

5.36

1.2

0.5

2.0

7.15

.75

1.0

2.7

-12

3, 10

3.57

8.45

1.2

0.5

3.3

7.15

2.0

1.0

3.0

-15

3, 10

3.65

11.5

1.2

0.5

4.3

7.15

3.3

1.0

3.0

-28

3, 10

3.57

24.3

1.2

0.5

10

7.15

5.6

1.0

2.0

-45

8

3.57

41.2

2.2

10

33

48.7
78.7

2.2
2.2

10
10

39
68

-100
-250

8
8

3.57
3.57

97.6
249

2.2
2.2

10
10

91
240

TABLE IIFORMULAE FOR INTERMEDIATE OUTPUT VOLTAGES

Outputs from +2 to +7 volts[Figures l, 5, 6, 9, 12, (4)]Outputs from +4 to +250 volts[Figure 7]

Ri
Your= [VREF X ~+
R l

VREF
R2 - R,
Your= [ - 2 - X - - - l; R3 = R4
R,

Outputs from + 7 to +37 volts[Figures 2, 4, (5, 6, 9, 12)]
R1 + R2
Your= [VREF X - - - ]RiOutputs from -6 to -250 volts[Figures 3, 8, 10]I

2Current Limiting
VSENSE
luM1r=-R,cFoldback Current Limiting_ [ Your R3 + YsENSE (R3 + R4) ]IKNEE--R,c R4
R,c R4

VREF
R, + R2
Your=[-2- X - - - ] ; R3=R4

R,YsENSE XISHORT CKT = [ -Rsc

Figure l

Figure 2

BASIC LOW VOLTAGE REGULATOR(Vout
2 to 7 Volts)

BASIC HIGH VOLTAGE REGULATOR(Vout
7 to 37 Volts)

R3 + R4 ]
R4

=

=

Ve

V+

Ve
Vour

pA723

Rsc
REGULATED
CL t--_......~--- OUTPUT

csi-----..
N.I.
V-

C1100pf

TYPICAL PERFORMANCETYPICAL PERFORMANCE

Regulated Output Voltage
5VLine Regulation (dV1N = 3 V) 0.5 mV
Load Regulation (dlL=50 mA) 1.5 mV
Note: R1 =:,'+~, for minimum temperature drift.

Note: R1 =:,'+~,

Regulated Output Voltage
15 VLine Regulation (dVLN = 3 V) 1.5 mV
Load Regulation (dlL=50 mA) 4.5 mV
for minimum temperature drift.

RJ may be eliminated for minimum component count.

6-91

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A723-::-

Figure 3

Figure 4

NEGATIVE VOLTAGE REGULATORPOSITIVE VOLTAGE REGULATOR(External NPN Pass Transistor)

R2

V+
V+

VREF
T1
2N5001
pA723

pA723
REGULATEDOUTPUT

N.I.
V-

TYPICAL PERFORMANCETYPICAL PERFORMANCE

Regulated Output Voltage-15 VLine Regulation (Ll.V1N = 3 V)
1 mV
Load Regulation (LI.IL= 100 mA) 2 mV

Regulated Output Voltage+15 VLine Regulation (Ll.V1N = 3 V) 1.5 mV
Load Regulation (LI.IL= 1 A)
15 mV

Figure 5

Figure 6

POSITIVE VOLTAGE REGULATOR(External PNP Pass Transistor)

FOLDBACK CURRENT LIMITING

VIN

T1
2N5001VREF

Rsc JonYour

REGULATEDOUTPUT

R3
2.7KQ

pA723

R4
5.6KQ

CLI----_.

cs
N.I.
V- COMPJC1 lnF
TYPICAL PERFORMANCETYPICAL PERFORMANCE

Regulated Output Voltage+5 VLine Regulation (Ll.V1N = 3 V) 0.5 mV
Load Regulation (LI.IL= 1 A)
5 mV

Regulated Output Voltage+5 VLine Regulation (Ll.V1N = 3 V) 0.5 mV
Load Regulation (LI.IL= 10 mA) 1 mVCurrent Limit Knee
20 mA

Figure 7

Figure .8

POSITIVE FLOATING REGULATORNEGATIVE FLOATING REGULATOR

Y+

T1
2N5287

D1 36V
1N1364

CLI-----_.

~--+--+---+-t N.I.

R3
3.0KQ

V-

TYPICAL PERFORMANCETYPICAL PERFORMANCE

Regulated Output Voltage+so Vline Regulation (Ll.V1N = 20 V) 15 mV
Load Regulation (LI.IL= 50 mA) 20 mV

Regulated Output Voltage-100 Vline Regulation (Ll.V1N = 20 V) 30 mV
Load Regulation (Ll.IL=IOO mA) 20 mV

6-92

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA723
Figure 9

Figure 10

POSITIVE SWITCHING REGULATORNEGATIVE SWITCHING REGULATOR

02 1N753
R5 3KOV+

V e . - - -..

~-----1 VREF

Your

uA723

~.---.---+-----<...---.

T2
2N5153
1N2071

V+

Ve

VREF

11 1

~ 2mH

CL l--+-'Rsvv..51_0~_ __..__ ~~~~TED

uA723

CSI--+---'CLcs

R3 IKQ
N.I.

Inv
R1

COMP

R4
IMO

V-

TYPICAL PERFORMANCETYPICAL PERFORMANCE
Regulated Output Voltage
Line Regulation (.<\V1N =.30 V)
Load Regulation (<\IL= 2 A)

Note 3

D1
1N2071T1
2N5287

C1
0.luF

+5 V
10 mV
80 mV

Regulated Output Voltage-15VLine Regulatlon (.<\V1N = 20 V)
8 mV
6mV
Load Regulation (AIL= 2 A)

Note 3Figure 11

Figure 12

REMOTE SHUTDOWN REGULATOR WITH
CURRENT LIMITINGSHUNT REGULATORREGULATEDV+-~-OUTPUT

Ve

uA723
CL

N.1.
V- COMP ..__-'VV.,.__~CCSL.,_-"N'---<> LOGIC INPUT

2KO

Note: Current limit transistor may be
used for shutdown if current
limiting is not required.

TYPICAL PERFORMANCETYPICAL PERFORMANCE

Regulated Output Voltage+5 VLine Regulation (AV1N = 3 V) 0.5 mV
Load Regulation (.<\IL=50 mA) 1.5 mVRegulated Output Voltage+5 VLine Regulation (.<\V1N = 10 V) 0.5 mV
Load Regulation (.<\IL=lOO mA)l.5 mVFigure 13

V+

SCHEMATIC DIAGRAMOUTPUT VOLTAGE
ADJUST
DJ
6.2V

Your

-·-----o COMPENSATION
R10
Rg
20
3000 KO

VREF

6-93

NON-INVERTING
INPUT

016 ">------<> ~r:1~ENT

Rn
1500

V-

CURRENT'-------<>SENSE

INVERTING
INPUT

uA723C
PRECISION VOLTAGE REGULATORFAIRCHILD LINEAR INTEGRATED CIRCUITS• POSITIVE OR NEGATIVE SUPPLY OPERATION• SERIES, SHUNT, SWITCHING OR FLOATING OPERATION• .01% LINE AND LOAD REGULATION• OUTPUT VOLTAGE ADJUSTABLE FROM 2 TO 37 VOLTS• OUTPUT CURRENT TO 150 mA WITHOUT EXTERNAL PASS TRANSISTORPHYSICAL DIMENSIONS

GENERAL DESCRIPTION - The µA723C is a .monolithic voltage regulator constructed on a single silicon chipusing the Fairchild Planar* epitaxial process. The device consists of a temperature compensated reference
amplifier, error amplifier, power series pass transistor and current limit circuitry. Additional NPN or PNP
pass elements may be used when output currents exceeding 150 mA are required. Provisions are made foradjustable current limiting and remote shutdown. In addition to the above, the device features low standby
current drain, low temperature drift and high ripple rejection. The µA723C is intended for use with positiveor negative supplies as a series, shunt, switching or floating regulator. Applications include laboratory power
supplies, isolation regulators for low level data amplifiers, logic card regulators, small instrument power
supplies, airborne systems and other power supplies for digital and linear circuits. For full temperature
range operation (-55°C to +125°C), see µA723 data sheet.
ABSOLUTE MAXIMUM RATINGS
40V
Voltage from v+ to v40V
lnput-Output Voltage Differential
150 mA
Maximum Output Current
25 mA
Current from Vz
15 mA
Current from VREF
800mW
Internal Power Dissipation-Metal Can (Note 1)
Internal Power Dissipation-DIP (Note 1)
900mW
Operating Temperature Range
0°c to +70°C
Storage Temperature Range-65°Cto +150°C
Lead Temperature (Soldering, 60 second time limit)
300°c
EQUIVALENT CIRCUITCONNECTION DIAGRAMS.230 TYP.

NOTES: All dimensions in inches
Leads are gold-plated Kovar
Package weight is 1.32 grams

ORDER PART NO. U5R7723393

TYPICAL DUAL IN-LINE PACKAGETOP VIEWS.290
lr .310~CURRENT
LIMIT

A
'
'
'

Y+

FREQUENCYCOMPENSATION

INVERTING
INPUT

Ye

V+

NON-INVERTING
INPUT

V-

Your
NC
VOLTAGEREFERENCEAMPLIFIER

Yz

Y-

ERROR
AMPLIFIER

CURRENT LIMIT

2CURRENT SENSE

11 Ye

INVERTING INPUT

10 YourNON-INVERTING INPUT

9 Yz

VREF
V-

14 NC
13 FREQUENCYCOMPENSATION
12 Y+

7

NC

Note: On metal can, pin 5 is connected to case
Notes on Page 2.

NOTES: All dimensions in inches
Leads are intended for insertion
in hole rows, .300 centers

ORDER PART NO. U6A7723393*Planar is a patented Fairchild process.

FAIRCHILCSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011, TWX: 910-379-6435

6-94

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATION

I

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA723C
ELECTRICAL CHARACTERISTICS (Note 2)
PARAMETER (see definitions)

CONDITIONSLine Regulation

TYP.

MAX.

UNITS

v,N = 12 v to v,N = 15 v

.01

0.1

% Yourv,N = 12 Vto v,N = 40V

0.1

0.5

% Your

0.3% Your

0.2

%Your

0.6

%Vour

0°c
load Regulations TA s 10°c, V1N= 12 Vto v,N = 15 v

lL = 1 mA to IL = 50 mA
0°C

Ripple Rejection

MIN.

.03

s TA s 70°C, IL= 1 mAto IL= 50 mA= 50 Hz to 10 kHz, CREF = 0
f= 50 Hz to 10 kHz, CREF = 5 µF
f

74

dB

86

dB

Average Temperature Coefficientof Output Voltage

0°c

s TA s 70°C

.003

Short Circuit Current limit

Rsc= 10 n, Your= O

65

6.80

Reference Voltage
Output Noise Voltage= 100 Hz to 10 kHz, CREF = 0
BW = 100 Hz to 10 kHz, CREF = 5 µF
BW

7.15

.015

%!°C
mA

7.50

v

20
2.5

long Term Stability

0.1Standby Current Drain

2.3%/1000 hrs
4.0mA

Input Voltage Range

9.5

40

v

Output Voltage Range

2.0

37

Input-Output Voltage Differential

3.0

38

v
v

DEFINITION OF TERMSLINE REGULATION - The percentage change in output voltage for a specified change in input voltage.
LOAD REGULATION - The percentage change in output voltage for a specified change in load current.
RIPPLE REJECTION - The ratio of the peak to peak input ripple voltage to the peak to peak output ripple voltage.
AVERAGE TEMPERATURE COEFFICIENT OF OUTPUT VOLTAGE- The percentage change in output voltage for a specified change in ambient temperature.
SHORT CIRCUIT CURRENT LIMIT - The output current of the regulator with the output shorted to the negative supply.
REFERENCE VOLTAGE- The output of the reference amplifier measured with respect to the negative supply.
OUTPUT NOISE VOLTAGE- The rms output noise voltage with constant load and no input ripple.
STANDBY CURRENT DRAIN - The supply current drawn by the regulator with no output load and no reference voltage load.
INPUT VOLTAGE RANGE- The range of supply voltage over which the regulator will operate.
OUTPUT VOLTAGE RANGE- The range of output voltage over which the regulator will operate.
INPUT-OUTPUT VOLTAGE DIFFERENTIAL- The range of voltage difference between the supply voltage and the regulated output voltage over which theregulator will operate.
SENSE VOLTAGE- The voltage between current sense and current limit terminals necessary to cause current limiting.
TRANSi ENT RESPONSE - The closed-loop step function response of the regulator under small-signal conditions.

NOTES:(1) Derate metal can package at 6.8 mW/°C and dual in-line package at 9 mW!°C for operation at ambient temperatures above 25°C.
(2) Unless otherwise specified, TA= 25°C, V1N = v+ =Ve= 12 V, v- = 0, Vo"t = 5 V, IL= 1 mA, Rsc = 0, C1 = 100 pF, CREF =0, divider impedance as seen byerror amplifier :::; 10 kll, and connected as shown in Figure I.
(3) For metal can applications where Vz is required, an external 6.2 zener should be connected in series with Vo,t.
(4) Figures in parentheses may be used if R1/R2 divider is placed on opposite side of error amp.
(5) Replace R1/R2 in figures with divider shown in figure 13.
(6) v+ must be connected to a +3 V or greater supply.
(7) L1 is 40 turns of #20 enameled copper wire wound on Ferroxcube P36/22·3B7 pot core or equivalent with 0.009" air gap.

6-95

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A723C
TYPICAL PERFORMANCE CURVES
MAXIMUM LOAD CURRENTAS A FUNCTION OF
INPUT-OUTPUT VOLTAGE
DIFFERENTIALMAXIMUM LOAD CURRENTAS A FUNCTION OF
INPUT-OUTPUT VOLTAGE
DIFFERENTIAL
200 .--..--..--..--..--..--.,-T-JMAX.-·-150'_,.C__,

LOAD REGULATIONCHARACTERISTICS WITHOUTCURRENT LIMITINGTJMAX •125°C
1--t-->--<--+--+--+. RTH • l11°C/W
PSTANOBY • 60 mW
160 l--r--lr--l--l--l--to1 P PACKAGEINO IEAT SI NKI

1--t--t--t--t----t'RTH • ISO'CIWPSTANDBY • 60mW
160 ,__._.,t--._.,._.,--t,r,UAL CAN PACKAGE
INO HEAT SINK!

~ ~·a'i:"""·i··:a: ;o:c-.

>g;~ -0.1 t--+--+--+-+--t--+--+--+-_,r-----1
~

\.~

40

!--- TA~Your" +sv

'i---+-

VIN• +12V --+--+--+--+--+--+--+--+Rsc•O-Q,2 ~+--+--+--+--~~-+--+--+-~

o ~-l~l~~~~'--'-~
0

10

30

50

0

20

10

30

0

40

LOAD REGULATIONCHARACTERISTICS
WITH CURRENT LIMITING
1.2

1--t--+--+---+--+-+-+->--+ V1N • +12 V
1--t--+--+-·-+--+-+-+->--+ Rsc • lOQ

1.0

L

100

OUTPUT CURRENT - mA

CURRENT LIMITING
CHARACTERISTICS AS A
FUNCTION OF JUNCTIONTEMPERATURE

CURRENT LIMITING
CHARACTERISTICS+0.1 ,.--,--,..-,...-,.-...,--..,.-+-r-r-:-:vo-ur-·"""+s=v80201v1" - v0UT1 • v

T\ 1\

0.8

ILTA •25°C

VI

TA• 70°C

0.6

TA •O'C

0.4
0.2

VIN c +l2V

Your. +SV
Rsc •!Oil
0

80

40

0

100

OUTPUT CURRENT • mA

OUTPUT CURRENT· mA

JUNCTION TEMPERATURE - °C

LINE REGULATION AS A
FUNCTION OF INPUT-OUTPUT
VOLTAGE DIFFERENTIAL

LOAD REGULATION AS A
FUNCTION OF INPUT-OUTPUT
VOLTAGE DIFFERENTIAL

STANDBY CURRENT DRAIN
AS A FUNCTION OF
INPUT VOLTAGE

+0.3

+0,2

v 0 UT • +sv
Rsc ·oTA• +25°C
AV• +3VI • lmA

+0.2

+0,1

4.0 1--+--+--+-+-+-+--+--+--+--I

Ji
':""

I

0

-r-1-

i5

...,,..

~~~-1

-...

N

1'

-Q,2 Vour. +SV·O,ll.O 1--t--+--+-+-+-+--+--+--+--I

Rsc •OTA ·2S°C
IL •lmAtolL •50mA

-Q,3

-Q,2

·S

3S

·S

4S

3S

o~+-+-+-+-~~~-+--+-~

4S

0

so

30

10

INPUT VOLTAGE - V

6.0

1JUT~LTAJ;

i5
~ 2.0
~

s

0

2.0 I!!

gll

0b... 1--.. OUTPUT VOLTAGE

if

!l!

0

-2.0 VoUT. +SV
It •lmA

Tl/lf•JIS~m

TA• +2SoC
IL •SOmA

I\

i5

~ 4,0

"

• 1.0

~

l

~

-4.0~

g-4.o ~~~ :~~~ --+--+---+--+v--+--+--+--+

4S -6.0

'

I\

~

ll_

·20

~CL•l(.f~t--it-T'~t-t-~VOLTAGE-+---+---+--t ·10~ oTA•2SOC
Rsc ·O

3S

~ 8.0

·2.0~

g

\....

15

~
~

.....,

VIN'" +12V

·4.0
·S

Vour. +sv
VIN• +12V
Rsc •O

I

e

~
~

10

T

1

> 4.0

OUTPUT IMPEDANCE AS A
FUNCTION OF FREQUENCYLOAD TRANSIENTRESPONSE

LINE TRANSIENTRESPONSE

s~ 0.10v

J.1

IL •40mA
TA = 25°C ·--+--+--+--+---+---+--+---1 ·30

-8.0

-s

Rsc. 0
35

15

TINE-115

6-96

.01

100

!Ok
FREQUENCY • Hz

IOOk

lM

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA723C
TABLE IRESISTOR VALUES (kn) FOR STANDARD OUTPUT VOLTAGESPOSITIVEOUTPUT VOLTAGE
+3.0
+3.6
+5.0
+6.0
+9.0
+12
+15
+28
+45
+75

APPLICABLE
FIGURES(Note 4)

FIXED OUTPUT
±5%
RI
Rz

1, 5, 6, 9,
4.12
3.01
12 (4)
1, 5, 6, 9,
3.57
3.65
12 (4)
1, 5, 6, 9,
2.15
4.99
12 (4)
1, 5, 6, 9,
1.15
6.04
12 (4)
2, 4, (5, 6, l.87
7.15
12, 9)
2, 4, (5, 6, 4.87
7.15
9, 12)
2, 4, (5, 6, 7.87
7.15
9, 12)
2, 4, (5, 6, 21.0
7.15
9, 12.f
7
3.57 ~ 48.7
7
3.57
78.7

OUTPUT ADJUSTABLE± 10% (Note 5)

NEGATIVEAPPLICABLE
OUTPUT VOLTAGE
FIGURESFIXED OUTPUT
±5%
RI
Rz

5% OUTPUT
ADJUSTABLE ± 10%
RI

pl

Rz

3.57

102

2.2

10

91

RI

pl

Rz

1.8

0.5

1.2

+100

7

1.5

0.5

1.5

+250

7

3.57

255

2.2

10

240

.75

0.5

2.2

-6 (note 6)

3, (10)

3.57

2.43

1.2

0.5

.75

0.5

0.5

2.7

-9

3, 10

3.48 .

5.36

1.2

0.5

2.0

.75

1.0

2.7

-12

3, 10

3.57

8.45

1.2

0.5

3.3

2.0

1.0

3.0

-15

3, 10

3.65

11.5

1.2

0.5

4.3

3.3

1.0

3.0

-28

3, 10

3.57

24.3

1.2

0.5

10

5.6

1.0

2.0

-45

8

3.57

41.2

2.2

10

33

2.2
2.2

10
10

39
68

-100
-250

8
8

3.57
3.57

97.6
249

2.2
2.2

10
10

91
240

TABLE IIFORMULAE FOR INTERMEDIATE OUTPUT VOLTAGESCurrent Limiting

Outputs from +2 to + 7 volts"[Figures 1, 5, 6, 9, 12, (4)]Outputs from +4 to +250 volts[Figure 7]

Rz
Your= [VREF X - - - ]RI+ RzVREF
R2 - RI
VOUT = [-2- x - - - ] ; R3 = R4
RI

Outputs from + 7 to +37 volts[Figures 2, 4, (5, 6, 9, 12)]Outputs from -6 to -250 volts[Figures 3, 8, 10]

R1 + Rz
Rz

VREF

Your= [VREF X - - - ]RI + R2
RI

Vour = [ -2- X - - - ] ; RJ

VSENSEILIMIT=-R,cFoldback Current Limiting- [ Your R3 + VsENSE (R3 + R4) l
IKNEE--R,c R4
R,c R4= R4vSENSEI SHORT CKT = [ -R-.

x R3 + R4 l
R4SC

Figure 1

Figure 2

BASIC LOW VOLTAGE REGULATORBASIC HIGH VOLTAGE REGULATOR(Vout= 2 to 7 Volts)(Vout=7 to 37 Volts)

Vt

Ve

VREf

Your

pA723CR3

REGULATEDOUTPUT

CL

cs
R1

N.I.
V-

TYPICAL PERFORMANCETYPICAL PERFORMANCE

Regulated Output Voltage
5VLine Regulation (!IV1N = 3 V) 0:5 mV
Load Regulation (LllL=50 mA) 1.5 mVRegulated Output Voltage
15 VLine Regulation (LIVrN = 3 V) 1.5 mV
Load Regulation (LllL=50 mA) 4.5 mV~~~: for minimum temperature drift.

Rr R, f. .
d ·1
Note: R' = Rr+R,
or minimum temperature n t.

Note: Ri =R, may be eliminated for minimum component count.

R3 may be eliminated for minimum component count.

6-97

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA723C
Figure 3

Figure 4

NEGATIVE VOLTAGE REGULATORPOSITIVE VOLTAGE REGULATOR(External NPN Pass Transistor)

-::-

R2

V+

Ve

VREF

Your
Tt
2N5001Vz
pA723C

V+

Ve

VREF

Your
Vz

pA723C

CL

CL

cs

cs

N.I.
R1

N.I.

C1
100pF

V-

V-::-

Note 3TYPICAL PERFORMANCETYPICAL PERFORMANCE

Regulated Output Voltage-15 VLine Regulation (LW1N = 3 V)
1 mV
Load Regulation (AIL= 100 mA) 2 mV

Regulated Output Voltage+1s V
Line Regulation (AV1N = 3 V) 1.5 mV
Load Regulation (AIL= 1 A)
15 mV

Figure 5

Figure 6

POSITIVE VOLTAGE REGULATOR(External PNP Pass Transistor)

FOLDBACK CURRENT LIMITING

VIN

R3
600
V+

Ve

VREF

Your

Tt.
2N5001

Rsc 300
VREF

Your

REGULATEDOUTPUT

R3
2.7KO

Vz

Vz
pA723C

R4
5.&KO

TYPICAL PERFORMANCETYPICAL PERFORMANCE

Regulated Output Voltage+5 VLine Regulation (AV1N = 3 V) 0.5 mV
Load Regulation (AIL= 10 mA) 1 mVCurrent Limit Knee
20 mA

Regulated Output Voltage+s VLine Regulation (AV1N = 3 V) 0.5 mV
Load Regulation (AIL= 1 A)
5 mV

Figure 7

Figure 8

POSITIVE FLOATING REGULATORNEGATIVE FLOATING REGULATOR

V+Ve.----<t-1 vREF

Your

-::-

Vz 1 - - - - - £ T12N2580

Cll-----_.

T1
2N5287Vz
pA723C·

R2

R3
3.0KQ

Cl
cs

...---+-+--+-! N.I.
V-

R1

Note 3

Ve
Your

D112V
1N1426

pA723C
01 36V
1N1364

V+
YREf

R4
3.0KQ

C1
100pF

TYPICAL PERFORMANCETYPICAL PERFORMANCE

Regulated Output Voltage+so VLine Regulation (AV1N = 20 V) 15 mV
Load Regulation (AIL= 50 mA) 20 mV

Regulated Output Voltage-100 VLine Regulation (AV1N = 20 V) 30 mV
Load Regulation (AIL=lOO mA) 20 mV

6-98

Note 3

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A723C
Figure 9

Figure 10

POSITIVE SWITCHING REGULATORNEGATIVE SWITCHING REGULATOR

R5 3KQ
V+

T2
2N5153
1N2071

Ve

Your

VREF

01

Vz
Rs 51Q

Rl

11

"::"

"::"

~~2mH

C1
0.lpF

REGULATEDOUTPUT

CL

R2

r

Inv

R2

C1

COMP

V-

R4
1MQ

O.MI
":"

Your
Vz l----1f-i:... T1
2N5287

cs

r

N.1.
Rl

R4
1MQ

V-

C2 100pF

TYPICAL PERFORMANCETYPICAL PERFORMANCE
Regulated Output Voltage
line Regulation (6.V1N = 30 V)
Load Regulation (6.IL = 2 A)

Note 7

+5v
10 mV
80 mV

Regulated Output Voltage-15 Vline Regulation (6.V1N = 20 V)
8 mV
Load Reg_ulation (6.IL = 2 A)
6 mV

Note 3Note 7

Figure 11

Figure 12

REMOTE SHUTDOWN REGULATOR WITH
CURRENT LIMITINGSHUNT REGULATOR

Rsc

REGULATEDYour 1----'V'VV---..-<• REGULATEDOUTPUT

VREF

01-::- 1N2071

CL

R3 1KQ

C2 100pF

N.I.

Ve

pA723C

cs
R31KQ

V+
VREF

--+-<.. OUTPUT

V+

Vz
pA723CCL
pA723C
N.1.
COMP

Inv
V- COMP

"::"

"::"

Note: Current limit transistor may be
used for shutdown if current
limiting is not required.

-::-

C 5nF

~1

TYPICAL PERFORMANCETYPICAL PERFORMANCE

Regulated Output Voltage+5 VLine Regulation (6.V1N = 3 V) 0.5 mV
Load Regulation (6.IL=50 mA) 1.5 mVRegulated Output Voltage+5 VLine Regulation (6.V1N = 10 V) 0.5 mV
Load Regulation (6.IL=lOO mA) 1.5 mV

Note 3V+

SCHEMATIC DIAGRAM

Figure 13
OUTPUT VOLTAGE
ADJUST
01
6.2V

09

Vz

- - - - - - - u COMPENSATION
015 J - - - - - - - - u ~~:l~ENT

R10
Rg
20
JOOQ KQ

NON-INVERTING
INPUT

6-99

CURRENT' - - - - - - - 0 SENSEV-

INVERTING
INPUT

µA726TEMPERATURE-CONTROLLED DIFFERENTIAL PAIR
FAIRCHILD LINEAR INTEGRATED CIRCUITSGENERAL DESCRIPTION - The µA726 is a monolithic transistor pair in a high thermal-resistance package, held at a constant temperature by active temperature re~ulator circuitry. The transistor pair displays the excellent matching, close
thermal coupling, and fast thermal response inherent in monolithic construction. The high gain and low standby dissipation of the regulator circuit permits tight temperature control over a wide range of ambient temperatures. It is intended
for use as an input stage in very-low-drift de amplifiers, replacing complex chopper-stabilized amplifiers; it is also
useful as the nonlinear element in logarithmic amplifiers and multipliers where the highly predictable exponential relation between emitter-base voltage and collector current is employed. The device is constructed on 'a single silicon chipusing the Fairchild Planar* process.

PHYSICAL DIMENSIONS

10 LEADS

ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 seconds)
Supply Voltage-55°C to + 125°C-65°C to·+ 150°C
300°C
±18V

MAXIMUM RATINGS FDR EACH TRANSISTOR
Maximum collector-to-substrate voltage
BVcoo
LVc•o [Note ll
BVElloCollector Current:g~: DIA.

40V
40V

30V
5V
5mA
NOTES: All dimensions in inches
Leads are gold-plated Kovar

Package weight is 1.32 grams

ORDER PART NO. U5J772631X

CO.NNECTION DIAGRAMSCHEMATIC DIAGRAMV+TEMP ADJ
Q_3

6

"3
81

E1

2

E2

'3
9

82

1

R1

2lkO

lko

D1
6.2V

NC

Q4

Q1

3

2

R2

R3
4.Sko

V-

TOP VIEW

D2
6.2V
R5

Q2

10 0
V-

E2

10

5

Note 1: Measured at 1 mA collector current.

*.Planar isa patented Fairchild process.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, .MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-100

A DIVISION OF FAIRCHILD CAMERA ANO INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA726
ELECTRICAL C~ARACTERISTICS (-55°C

s TA s + 125°C, Vs = ±15 V, R•di = 62 kn unless otherwise specified)

PARAMETERCONDITIONS

MIN.

TYP.

MAX.

UNITS

Input Offset Voltage

10 µA le100 µA
Vee= 5 V, Rs S 50n

s s

1.0

2.5

mV

Input Offset Current

le = 10 µA, Vee = 5 V

10

50

nA

Input Offset Current

le= lOOµA, Vee= 5 V

50

200

nA

Average Input Bias Current

le= 10 µA, Vee= 5 V

50

150

nA

Average Input Bias Current

250

Offset Voltage Change

le = 100 µA, Ve• = 5 V
le = 10 µA, 5 V S Ve• S 25 V, Rs S 100 kn

500
6.0

mV

Offset Voltage Change

le = 100 µA, 5 V S Ve• S 25 V, Rs S 10 kn

Input Offset Voltage Drift

10 µA le100 µA, Vee = 5 V,
Rs 500, +25°C TA+125°C

'0.3
0.3

s s
s
s s
lOµA s le s 100 µA, Vee = 5 V,
Rs s 50n, -55°C s TA s +25°C

Input Offset Voltage Drift

nA

6.0

mV

0.2

1.0

µV/°C

0.2

1.0

µV/°C

10

pA/°C

30

pA/°C

Low-Frequency NoiselOµA S le S 100 µA, Rs S 50n,
le = 10 µA, Vee = 5 V, Rs S 500
BW = .001 Hz to 0.1 Hz

25
4.0

µV/V
µVpp

Broadband Noisele = 10 µA, Vee = 5 V, Rs S 50n
BW = 0.1 Hz to 10 kHz

10

µVpp

5.0
3.5

µV/week

Input Offset Current Driftle = 10 µA, Ve• = 5 V
le = 100 µA, Vee = 5 V

Input Offset Current Drift
Supply Voltage Rejection Ratio

Long-term DriftlOµA S le S 100 µA, Ve•= 5 V, Rs S 50n,TA=25°C

High Frequency Current Gainf = 20 MHz, le = 100 µA, Ve• = 5 V

1.5

Output Capacitance

I. = 0, Vea = 5 V

1.0

pF

Emitter Transition CapacitanceI.= lOOµA

1.0

pF

Collector Saturation Voltage

la = 100 µA, le = 1 mA

0.5

TYPICAL P~RFORMANCE CURVESTYPICAL XlOOO CIRCUITCURRENT GAIN AS AFUNCTION
OF COLLECTOR CURRENT

1000

VcE • 5,0V

11s·mv-

R · • 62kQ

-i'l'ic~rA~+125•c .....,

800

v~
200

v

1.0

.....,

.iY"

f"

IL

Eout

0

lO!lfA

lllJA

lOmA

lmA

COLLECTOR CURRENT20

SUPPLY CURRENT AS AFUNCTION
OF AMBIENT TEMPERATURE
Vs= ±15V
Rad( 62kQ

+--

16

12

8

5011
R4

~

R

1--..]',
"b,.

0
-60

-20

20

60

R

100

140

TEMPERATURE - °C

6-101

SOkll
ALL RESISTORS l %µA726C
TEMPERATURE-CONTROLLED DIFFERENTIAL PAIR
FAIRCHILD LINEAR INTEGRATED CIRCUITSGENERAL DESCRIPTION-The µA726C is a monolithic transistor pair in a high thermal-resistance package, held
at a constant temperature by active temperature regulator circuitry. The transistor pair displays the excellent
matching, close thermal coupling, and fast thermal response inherent in monolithic construction. The highgain and low standby dissipation of the regulator circuit permits tight temperature control over a wide rangeof ambient temperatures. It is intended for use as an input stage in very-low-drift de amplifiers, replacing
complex chopper-stabilized amplifiers; it is also useful as the nonlinear element in logarithmic amplifiers andmultipliers where the highly predictable exponential relation between em.itter-base voltage and collector current
is employed. The device is constructed on a single silicon chip using the Fairchild Planar* process. For fulltemperature range (-55°C to +125°C) see µA726 data sheet.
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 seconds)
Supply Voltage

o·c to +ss·c-6s c to +iso·c
0

PHYSICAL DIMENSIONS

ii~.040~
II
f~

185
:165

MAX.

~

*=

10 LEADS..J:~:~DIA-:;6 I

m~~~~oo M~O? MIN.

300~C

±18V

MAXIMUM RATINGS FOR EACH TRANSISTOR
Maximum collector-to-substrate voltage
BVceo
LVcEO (Note 1)
BVeeo
Collector Current

40V
40V
30V
5V
5mA
NOTES: All d1mens1ons in inches
Leads are gold·plated Kovar
Package weight ts 1.32 grams

ORDER PART NO. U5J772632X

SCHEMATIC DIAGRAM

CONNECTION DIAGRAMTEMP ADJ
6

R3
4.Sko

TOP VIEW

Rs100'--~~~~~~-+-~~~.._~~~~~~~~-+---oV-

SUBSTRATE

5

NOTE: (1) Measured at 1 mA collector current.

*Planar is a patented Fairchild process.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-102

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA726C
ELECTRICAL CHARACTERISTICS (0°C S TA S +8S°C, Vs= ± lSV, Radi = 7S kn unless otherwise specified)
PARAMETERCONDITIONS

Input Offset Voltage

TYP.

MAX.

UNITS

10 µA S le S 100 µA
VeE = sv, Rs
son

MIN.

1.0

3.0

mV
nA

s

Input Offset Current

le = 10 µA, VeE = SV

10

100

Input Offset Current

le= 100 µA, VeE = SV

so

400

nA

Average Input Bias Current

le = 10 µA, VeE = SV

so

300

nA

Average Input Bias Current

le = 100 µA, VeE = sv

2SO

1000

nA

Offset Voltage Change

le = 10 µA, SV

0.3

6.0

mV

Offset Voltage Changes VeE s 2IJV, Rs s 100 kn
le = 100 µA, sv s VeE s 2SV, Rs s 10 kn

0.3

6.0

mV

Input Offset Voltage Driftle = 100 µA, VeE = SV, Rs S SOn

0.2

2.0

µV/°C

Input Offset Current Driftle = 10 µA, VeE = SV

10

pA/°C

Input Offset Current Driftle = 100 µA, VeE = sv

30

pA/°C

2S

Supply Voltage Rejection Ratio

le = 100 µA, Rs = SOn

Low-Frequency Noisele = 10 µA, VeE = sv, Rs
BW = 0.001 Hz to 0.1 Hzs ·son,

4.0

µV/V
µVpp

Broadband Noisele = 10 µA, VeE = SV, R5 S SOn,
BW = 0.1 Hz to 10 kHz

10

µVpp

Long-Term Driftle = 100 µA, VeE = SV,
Rsson, TA= 2s·cs.oµV/week

s

l.S

3.S

High-Frequency Current Gainf "."' 20 MHz, le = 100 µA, VeE = SV

Output Capacitance

1.0

pF

Emitter Transition Capacitance.le= 0, Vea= SV
le= 100 µA

1.0

pF

Collector Saturation Voltage

la = 100 µA, le = 1 mA

o.s

1.0

TYPICAL XlOOO CIRCUITTYPICAL PERFORMANCE CURVESCURRENT GAIN AS A FUNCTION
OF COLLECTOR CURRENT

llXll .--,...-,-n--..-,-,-.,-,.-..,..--.-i-.,-,.--,
VcE • 5~0 I
1---+-+-++--+--+-+-++-vs • :!:lS V

Jt--

Rai1j • mo t--

800

+15V

1---+-+-++--+--+-+-++-00c 'STA'S 85°Cf---<~i--t-t-H--t-t-1-ttf-"'-=+-~,-t-ttt-~

25ko

25ko

R1

Rz

~t-+-+-++v-k::::'F--+-+-++~~~. . . . . . .~

Eout

C1

0'--'-'-''-'--'-.1-.L..W.--'---'-L..l..L-~

IQJA

10

IOQJA
I. OmA
COLLECTOR CURRENT

lOmA

SUPPLY CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
VS m~l5 V

Radj • 75kQ
8.0

SnF

I"

6.0

1--SOko'h.

ALL RESISTORS I%

~

t-,.

4.0

t--..

~

2.0

0
0

20

40
60
TEMPERATURE - °C

""

80

100

6-103

v

uA727TEMPERATURE-CONTROLLED DIFFERENTIAL PREAMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITSFEATURES• VERY LOW OFFSET DRlns• HIGH INPUT IMPEDANCE• WIDE COMMON MODE RANGEPHYSICAL DIMENSIONS(In accordance with JEDEC TD-100)_ _ _ _ _ _ .370

.335
.305

GENERAL DESCRIPTION - The µA727 is a monolithic, fixed gain, differential-input differential-output amplifier, constructed with the Fairchild Planar" epitaxial process, mounted in a high thermal-resistance package,and held at constant temperature by active regulator circuitry. The high gain and low standby dissipation of
the regulator circuit give tight temperature control over a wide ambient temperature range. The device isintended for use as a self-contained input stage in very low-drift DC amplifiers, replacing complex chopperstabilized amplifiers in such applications as thermo-couple bridges, strain gage transducers, and A to D
converters.

ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 second time limit)
Supply Voltage (Amplifier and Heater)
Differential Input Voltage
Common Mode Input Voltage-55°C to +125°C-65°C to + 1so 0 c
3QQ°C
±lBV
±lOV
±15V

.335

10 LEADS:mo1A.

NOTES: All dimensions in inches
Leads are gold·plated Kovar
Packa1e weight is 1.32 grams

ORDER PART NO. U5J7727312

SCHEMATIC DIAGRAMFAIRCHILCJSEMICONDUCTOR
313 f'AIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-104

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA727
ELECTRICAL CHARACTERISTICS (-SS°C s TA s +12S°C, VH + = vA+ = +lS V, v- = -lS V,
RADJ = 330 kn, unless otherwise specified)
PARAMETERCONDITIONS

Input Offset Voltage
Input Offset Current
Input Bias Current
Input Offset Voltage Drift

Rs s son

MIN.

Rs s son, +2S°C s TA s +12s 0 c
Rs s son, -ss 0 c s TA s +2S°C+2S°C s TA s +12s 0 c-SS°C s TA s +2S°C-ss 0 c s TA s +12s 0 c

Input Offset Current Drift
Input Bias Current Drift
Differential Input Resista nee
Common Mode Input Resistance
Input Voltage Range
Supply Voltage Rejection Ratio
Common Mode Rejection Ratio
Output Resistance
Output Common Mode Voltage
Differential Output Voltage Swing
Output Sink Current
Differential Load Rejection
Differential Voltage Gain
Low Frequency NoiseLong Term Drift
Amplifier Supply Current
Heater Supply Current±12
Rs s 100 kn
R5 s 100 kn

80
-6.0
±S.O
10
60

BW = 10 Hz to SOO Hz, Rs s SO n
Rs s son
TA= +2S°C
TA= +2S°C

TYP.

MAX.

UNITS

2.0
2.S
12
0.6
0.6
2.0
2.0
lS
300
1000
±13
80
100
1.0
-S.O
±7.0

10
lS
40
l.S
l.S

mV
nA

nA
µV!°C
µV/°C
pA!°C
pA!°C
pA!°C
Mn
Mn
v
µV/V
dB
kn
v
v

4.0
-4.0
±10
80
10
250

30
s.o
100
3.0
s.o
1.0
10

µA

µV/µA
µVrms
µV/week
mA
mA

2.0
lS

TYPICAL XlOOO CIRCUIT

+15V
50k0
+15V

500

EtN

500

3

3

6

2

2

50k0

-15V

6-105

Eour

-15V

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA727
TYPICAL PERFORMANCE CURVESNOISE VOLTAGE
AS A FUNCTION OF
FREQUENCY

NOISE CURRENTAS A FUNCTION OF
FREQUENCY

is.

Vs• ±.15V
RADt3JOk0~

SPOT NOISE FIGURE CONTOURS
lM~'1lv1ylZ..AI"" Vs· i15v

RADJ°330k0
lOOk

!'--

~

['SI

~

"'

b..

is;:

·~

IS.

dB

I

rs ~

!Ok

!:i
5l

IL

/

I

"'

RADJ°3JOkQ

Ii":

8~e-1

j,,..oj

lOdB't-...

lk

N.....,
dB

t--

t-

10·18
10

100

lk

100<

!Ok

100

lk

!Ok

100

lOOk

FREQUENCY • Hz

FREQlENCY - Hz

RECOMMENDED R..oJ AS A
FUNCTION OF MAXIMUMAMBIENT TEMPERATURE

RELATIVE CHIP TEMPERATURE
AS A FUNCTION OF
AMBIENT TEMPERATURE

100

10

lk

POWER CONSUMPTION
AS A FUNCTION OF
AMBIENT TEMPERATURE

2.2

1000
Vs· ,t.lSV

Vs·115J
RADt 330k0

20~~t-t-t-t-t-t-+---+-t

1.8

§!

100<

!Ok

FREQUENCY - Hz

.,

i

1.4

ii:

i

~

0,6

50

~

l"'-J

400

N

~

~

-20 ~t-t-t-+---t-+---+---+---+-t
Vs· :t15V

I'-

no

70

~

roe

JS

0.2

600

~

-10 ~+--+--+--+----+----+----+----+----~

~
JO

'h.

•

z

0

[

~'fi. 1.0

800 1..-..

!JO

-60

0

-20

+20

+100

.f60

-60

+140

-20

' l'I

i60

+100

MAXIMUM AMBIENT TEMPERATURE - °C

AMBIENT TEMPERATURE· °C

AMBIENT TEMPERATURE - °C

INPUT COMMON MODE VOLTAGE
RANGE AS A FUNCTION OF
SUPPLY VOLTAGEOUTPUT COMMON MODE
VOLTAGE AS A FUNCTION OF
SUPPLY VOLTAGEAMPLIFIER CURRENTAS A FUNCTION OF
SUPPLY VOLTAGE

+l«>

2.0

1ADJ° 6BJJA
1.6

<

•

~

1.2

~

u:
~
;j!

0.8

0.4

0

9

10

n

-10
13

12

14

15

0

...__.___.__.__~~~___.___._~

9

10

n

g

13

M

9

15

n

10

g

13

M

SUPPLY VOLTAGE - t V

SUPPLY VOLTAGE- .tV

DIFFERENTIAL VOLTAGE GAIN
AS A FUNCTION OF
SUPPLY VOLTAGE

REQUIRED RADJ FOR CONSTANT
IAoJ AS A FUNCTION OF
SUPPLY VOLTAGE

OPEN-LOOP FREQUENCYRESPONSE FOR VARIOUS
VALUES OF COMPENSATION

no

60

lli

1ADt 6BOA

40

I

F'jo..

IJo JoM SATloJ~

20~ 0.05JJf, Rj" 20k Q

N

lll

N
'I'

!"I

N

lU

)'.,

li·0.05JJf.~·O-20.........._.__.__._.

Vs" :tl5V~...__._.__.__.__.__.__

9

15

SUPPLY VOLTAGE - .tV

10

ll

12

13

SUPPLY VOLTAGE - !V

14

-40

15

10
SUPPLY VOLTAGl - i. V

6-106

100

lk

!Ok

FREQUENCY - Hz

lOOk

lM

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A727
DEFINITION OF TERMS
INPUT OFFSET VOLTAGE - That voltage which must be applied between the input terminals to obtain zero differential output voltage.
INPUT OFFSET CURRENT - The difference in the currents into the two input terminals with the differential output at zero.
DIFFERENTIAL INPUT RESISTANCE - The resistance looking into either input terminal with the other grounded.
COMMON MODE INPUT RESISTANCE- The resistance looking into both inputs tied together.
INPUT BIAS CURRENT - The average of the two input currents.
INPUT VOLTAGE RANGE-A range of voltage which, if exceeded on either input terminal, could cause the amplifier to cease functioning properly.
INPUT COMMON MODE REJECTION RATIO - The ratio of the input voltage range to the maximum change in input offset voltage over this range.
DIFFERENTIAL VOLTAGE GAIN - The ratio of the change in differential output voltage to the change in differential input voltage producing it.
DIFFERENTIAL OUTPUT VOLTAGE SWING - The peak differential output swing that can be obtained without clipping.
OUTPUT RESISTANCE- The resistance seen looking into either output terminal with the differential output at zero.
SUPPLY VOLTAGE REJECTION RATIO - The ratio of the change in input offset voltage to the change in supply voltage producing it.
OUTPUT COMMON MODE VOLTAGE - The average voltage at the two output terminals referred to ground.
OUTPUT SINK CURRENT- The maximum negative current that can be supplied by each output.
DIFFERENTIAL LOAD REJECTION - The ratio of the change in. input offset voltage to the change in differential load current producing it.
IADJ - The current into terminal 6.

FREQUENCY COMPENSATION CIRCUIT

2

3

6-107

1-1A727B
TEMPERATURE-CONTROLLED DIFFERENTIAL PREAMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITSFEATURESPHYSICAL DIMENSIONS• VERY LOW OFFSET DRIFTS• HIGH INPUT IMPEDANCE• WIDE COMMON MODE RANGE(in accordance with JEDEC T0-100)

GENERAL DESCRIPTION - The µA727B is a monolithic, fixed gain, differential-input differential-output amplifier, constructed with the Fairchild Planar• epitaxial process, mounted in a high thermal-resistance package,and held at constant temperature by active regulator circuitry. The high gain and low standby dissipation of
the regulator circuit give tight temperature control over a wide ambient temperature range. The device isintended for use as a self-contained input stage in very low-drift DC amplifiers, replacing complex chopperstabilized amplifiers in such applications as thermo-couple bridges, strain gage transducers, and A to D
converters. For full temperature range operation (-55°C to +125°C) see µA727 data sheet.

ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 second time limit)
Supply Voltage (Amplifier and Heater)
Differential Input Voltage
Common Mode Input Voltage-20°c to +85°C-65°C to + 1so 0 c
300°C
±18V
±lOV
±15V

NOTES: All dimensions in inches
Leads are gold-plated Kovar

Package weight is 1.02 grams

ORDER PART NO. U5J7727333

SCHEMATIC DIAGRAM

CONNECTION DIAGRAM
1

¥1

I

'~

(top view)

G3
R1
21k0

FREQ.COMP .#1

1kO

u,
110

fRIQ.COMP.#2
4

INPUT #2

OUTPUT #2

INPUT #1

YR

2
INPUI #2Oz

R4 2.4!0y-

R5 1110v5•Planar is a patented Fairchild process.

F=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-108

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATION

I

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A727B

ELECTRICAL CHARACTERISTICS (-20°C

s TA s +85°C, VH + = vA+ = +15 v. v- = -15 V, RADJ = 680 Kn, unless otherwise specified)

PARAMETERCONDITIONS

Input Offset Voltage

Rs

s 50n

Input Offset Current
Input Bias Current
Input Offset Voltage Drift
Input Offset Current Drift
Input Bias Current Drift

Rs

MAX.

UNITS

2.0

10

mV

2.5
12

25

nA

75

nA

0.6

3.0

µVf°C

TYP.

MIN.

s 50 n

pA/°C
pA/°C
Mn

2.0
15

Differential Input ResistanceCommon Mode Input Resistance

300
1000

Input Voltage Range
Supply Voltage Rejection Ratio

Rs

Common Mode Rejection Ratio

Rss 100 kns 100 kn

Output Resistance
Output Common Mode Voltage
Differential Output Voltage Swing
Output Sink Current
Differential Load Rejection

Mn

±12

±13

v
µV/V

70

80
100

dB

1.0

4.0

kn

-7.0

-5.0

-4.0

±3.0

±7.0

10

30

±10.0
80

v
v
µA

5.0

15.0

µV/µA

100
3.0

250

Differential Voltage Gain
Low Frequency NoiseLong Term Drift

BW = 10 Hz to 500 Hz, Rs S 50 n

Amplifier Supply Current

TA= +25°c

1.0

2.0

Heater Supply Current

TA=+25°c

10

15

50
R5

s son

µVrms
µV/week

5.0

mA
mA

TYPICAL XlOOO CIRCUIT

+15V
50kQ
+15V

50Q

E1N

50Q

3

3

6

2

2

50kQ

-15V

6-109

Eou1

-15V

µA730
DIFFERENTIAL AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITSGENERAL DESCRIPTION - The µA730 is a differential amplifier constructed on a single silicon-chip using the
Fairchild Planar* epitaxial process. This device has a wide range of applications since it has both a differential
input and output; any combination of single-ended or differential configurations can be employed at its input
and output. The emitter follower output stage gives this device a low output impedance making it useful asa preamplifier.

PHYSICAL DIMENSIONS
in accordance withJEDEC(T0-99) outline

F

.370~

.335

.335__J
.305
·1

.040~
MAX.

_¥

Seating..1_

ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Differential Input Voltage
Common Mode Input Voltage
Internal Power Dissipation (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 seconds)

15V±5V
2.5to 5.5 V
300mW-55°c to +i25•c-65°Cto +150°c+3oo·cFa•..-rB

Le~~; ~~ ~ ~~

.185
' 165

.500 MIN.

.016

.034
.028

;;z~

NOTES: D1mens1ons u per latest J·lO'comm1ttee
Alldimens1ons1ninches'Leadsaregold-platedKovar
Package weight ts 1.22grams

Order Part No. USB773031X

SCHEMATIC DIAGRAM

CONNECTION DIAGRAM(Top View)v+

5.6kll

lOkll

03

HiZ
OUTPUTl

Hi Z
OUTPUT
2

INPUT
l

INPUT
2

LOW Z
OUTPUT l

lOkll

04
LOW Z
OUTPUT 1

LOW Z
OUTPUT 2

Oz

GND

2kll

2kll
l.3kllNote: Pin 4 connected to case

GND

NOTES:(1) Rating applies for case temperature to +125°C; derate linearly at 5.6 mW/°C for ambient temperatures above +105°C.

•Planar is a patented Fairchild process.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-110

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA730
ELECTRICAL CHARACTERISTICS (TA= 2S°C, V+ = 12.0 V, and VcM = 3.S V unless otherwise specified)
PARAMETER (See Definitions)

CONDITIONS

Input Offset Voltage
Input Offset Current
Input Bias Current
Input ResistanceDifferential Voltage Gain
Differential Distortion
Bandwidth
Single:Ended Output Resistance
Output Voltage Swing
Supply Current
Power Consumption

Rs~ son

MIN.

s.o
100

RL 2 100 k!J
RL 2 100 k!J

1.0
RL 2 100 k!J
RL 2 100 k!J
RL 2 100 k!Js.o

The following speci.fications apply for -ss•c ~TA~ 12s 0 c:
Input Offset Voltage
Rs~ sonInput Offset Current
TA= +12s 0 c
TA= -ss·c
Input Bias Current
TA= -ss·c
Input Resistance
Input Voltage Range
Common Mode Rejection Ratio
Rs~ sonf ~ 1.0 kHz,

UNITS

l.O
o.s
3.S
20
14S
80
l.S
70
8.0
9.S
114

2.S
l.S
7.S

mV
µA
µA
k!J

0.9
3.S
70

8S

90
s.s

7.0

4.S
TA= -ss·c
TA=12s·c
TA= -ss·c
TA= 12s·c

Power Consumption

MAX.

160
300

mVpp
MHz
SJ
Vpp
mA
mW

soo
13
1S6

0.2
1.0
6.S

+3.S V ~ VcM ~ +S.2 V
RL 2 100 k!JDifferential Voltage Gain
Common Mode Output Voltage
Output Resistance
Output Voltage Swing
Supply Current

TYP.

3.S
l.S
3.0
lS

mV
µA
µA
µA
k!J

S.2

v
dB

6.8
10
8.0
120
96

17S
7.7S
600

SJ

lS
11
180
121

Vpp
mA
mA
mW
mW

v

TYPICAL PERFORMANCE CURVES\INPUT OFFSET CURRENTAS A FUNCTION OF
SUPPLY VOLTAGE

INPUT OFFSET CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

INPUT BIAS CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE
10.

y+ •12Y,_ 1.6 1--1---!--t--+--+--+-+--+--+---I
Iv•·12v

1- 0.8~~~ 1.2 1--1---!--+--+--+---+---+---+--+--<

"'

<.>

~

~

:::: 0.8 l--~--t--+--+-+-+--+--+---1

::

~

ir

!!: 0.4......

l--lf-1-+-+r--.---1"......_,.+--1--1-~

T'-N

0~1---1--+~--+---+---+--'--'-~

-60

-20

20

60

TEMPERATURE-"C

100

140

1--1---1--+--+-+---+---+---+--+--<.:""'g; 0.6 1--1---!--t--t--+--+-+-~-"-+---IL1!z~ o.4 1--1---1--+--+-L'.1-+-v_._--+---+--+--<
v

a

*
i

I ./I

~ 6.0

17

b.

"'~ 4.0~!!:!!: 0.2 1--1---!v-.IL.J'--+-+---+---+---+--+--<

8.0

2.0

b..

""

~

t"--..

0

7.0

9.0

11

SUPPLY VOLTAGE-V

6~111

13

15

-60

-20

20

60

TEMPERATURE-'C

100

140

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA730
TYPICAL PERFORMANCE CURVESINPUT BIAS CURRENTAS A FUNCTION OF
SUPPLY VOLTAGE

INPUT RESISTANCEAS A FUNCTION OF
AMBIENT TEMPERATURE

VOLTAGE TRANSFER
CHARACTERISTICS

5.0
TA• 25"C

c 4.0

:'

~ 3.0

a"'

~

ii"' 2.0v

801--t----t----t----t----f---lf---l--J--J--J...}--'

v

!;;;

....

~
- 1.0

"'

0

o.__~~~~~~~--+--+

5.0

7.0

9.0

11

13

15

-60

-20

20

60

100

140

SUPPLY VOLTAGE-V

TEMPERATURE-'C

INPUT VOLTAGE-mV

DIFFERENTIAL VOLTAGE GAIN
AS A FUNCTION OF
AMBIENT TEMPERATURE

DIFFERENTIAL VOLTAGE GAIN AS A
FUNCTION OF SUPPLY VOLTAGE

DIFFERENTIAL DISTORTION
AS A FUNCTION OF
AMBIENT TEMPERATURE
1000

y+c 12Vy+, 12V~ 170 l--f---f---f---+-+-+-+-+-+--1~ 160 l--+--l--~~---J---JJ71--,jk:"."-4--I~'E 800Iy~~120 >--+--+--+---->--<...iv~__.__.__.__,~

L_J~ 801--+--vl---Tk"'f--"---J---J---J---J---f--I
v

ffi

It:

ii 600

v
lZl

~
a

~ 400

;:::
~

~ 40t--+--t--t--f-f-f-f---+--+--+--I"'~ 200/~a90.__.__.__.__..__..__..__..__..__...__.
-60
-20
20
60
100
140

o.__.__.__.__'---"'--''--'--'--'--'
5.0

7.0

9.0

11

13

15

v1

0
-60

-20

20

60

100

TEMPERATURE -'C

SUPPLY VOLTAGE-V

TEMPERATURE -'C

OUTPUT RESISTANCEAS A FUNCTION OF
AMBIENT TEMPERATURE

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
AMBIENT TEMPERATURE

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
SUPPLY VOLTAGE
129.5
y+ = 12V

V'• 12VTA• 25'C

>~ 10

"'
:'/

[7

~

v

~

~

g 6.5

1l

'
"'
z
~ 8.0

~
1'

1Ll
lZ
lZ

....
401--1--f---f---t----t----+-+-+-+--I

20 '--'--'--~~~~~~~
-60
-20
20
60
JOO
140

140

5~ 5.5
4.5
-60

-20

20

60

100

140

2.0
5.0

v

k/'
v
v
7.0

9.0

13

11

15

TEMPERATURE-'C

TEMPERATURE-'C

SUPPLY VOLTAGE - V

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
LOAD RESISTANCE

SUPPLY CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

9.0
TA• 25 'C

V'•l2V -1
~

~8.0

I
"'
z

~ 7.0

"'

i:l"'

~ 6.0

~

_Ll

z 07

10 r-"'-::t-+-+-+-+-+--+--+---1

v

r-+-.

8.0

I

5 5.0
4.0
0.1

~

9.0 t---+-+-+-+-+--l"""'-+]'--,.--+--+--if--t--j--J--J--t--+-+--+-rs:~--l

.x

10

7

8.0 >-----+-----+--+--+__.,,,.__1'.".'.'.-+--+--+--+--i6.0

rJ---k11----21.L"'--+--+--+-+--+--+--+---l

7.0 t---+-+-+-+-+-+--+--+--+----<

0.2

0.5

1.0 2.0

5.0

LOAD RESISTANCE - kA

10

2.0 .__..__..__.__.__'---''--''--''--''--'
5.0
7.0
9.0
11
13
15

20
TEMPERATURE -•c

6-112

SUPPLY VOLTAGE-V

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA730
DEFINITION OF TERMS
INPUT OFFSET VOLTAGE-That voltage which must be applied between the input terminals to obtain zero differential output voltage.
INPUT OFFSET CURRENT-The difference in the currents into the two input terminals with the output at zero differential volts.
INPUT BIAS CURRENT-The average of the two input currents.
INPUT BIAS RESISTANCE-The resistance looking into either input terminal with the other grounded.
INPUT VOLTAGE RANGE-The range of voltage which, if exceeded on either input terminal, could cause the amplifier to cease functioning properly'.
COMMON MODE REJECTION RATIO-The ratio of the input voltage range to the maximum change in input offset voltage over this range.
DIFFERENTIAL VOLTAGE GAIN-The ratio of the change in the differential output voltage to the change in voltage between the input terminals producing it.
DIFFERENTIAL DISTORTION-The A.C. unbalance in the output common mode voltage produced by unsymmetrical output voltage swings.
BANDWIDTH-The frequency at which the differential voltage gain is 3 dB below its low frequency value.
OUTPUT RESISTANCE-The resistance seen looking into either output terminal with the output at differential null.
COMMON MODE OUTPUT VOLTAGE-The average voltage at the two output terminals referred to ground.
OUTPUT VOLTAGE SWING-The peak-to-peak output swing that can be obtained without clipping.
SUPPLY CURRENT-The current required from the power supply to operate the device with no load.
POWER CONSUMPTION-The ,DC power required to operate the amplifier with no load current.

TYPICAL PERFORMANCE CURVESCOMMON MODE REJECTIONRATIO AS A FUNCTION OF
AMBIENT TEMPERATUREm

2' 951--1--+-+-+-+-+-+-+-+-l:~v• • 12 V-1

>

'

z

h

751--+-+-+-+-+-+-+-+-+-lii!

I &51--+--+--+-+-+--+--+-+--+--<
855...._.__.__._.__,___,___,___,__.__.
-60
-20
20
60
100
140
TEMPERATURE- 'C

t--t--+--+--+--+--+--+-TA • 25'C':"

~ 8.0 t--1t--1t--1t--1---t---t-+1-+...-V-:;;ot--;

~ 9.0

~

z

2 85t--t-:::;;*"'""T-T-1-T-~±--t--1~

COMMON MODE OUTPUT VOLTAGE
AS A FUNCTION OF
SUPPLY VOLTAGE

10

.
a:

COMMON MODE OUTPUT
VOLTAGE AS A FUNCTION OF
AMBIENT TEMPERATURE

~

g
~ 8.0

e:

§

~

5

.

~ 7.0

1•.o

-r-t--~z~

f--f--f--r--lf-i---t--+--+-+---t

I 2.0 1--1--1--t--1t--1---t---t---t---t---t

86.0
5.0
-60

!£:....

kd"
s 6.0 f--t--f--l-1c.--r::..1"--l--t--t--+--+g8of--f--f--f--~~~~~~

-20

20
60
TEMPERATURE- 'C

FAIRCHILCJSEMICONDUCTORA DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATION

6·113

100

140

5.0

7.0

9.0
11
SUPPLY VOLTAGE·V

1315

µA730C.,,DIFFERENTIAL AMPLIFIER .
FAIRCHILD LINEAR INTEGRATED CIRCUITSGENERAL DESCRIPTION- The µA730C is a differential amplifier constructed on a single silicon-chip using the
Fairchild Planar= epitaxial process. This device has a wide range of.applications since it has both a differential
input and output; any combination of single-ended or differential configurations can be employed at its input
and output. The emitter follower output stage gives this device a low output impedance making it useful asa preamplifier.
For full temperature range operation (-55°C to +125°C), see µA730 data sheet.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Differential Input Voltage
Common Mode Input Voltage
Internal Power Dissipation (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 seconds)

15V
:t5V
2.5to 5.5 V
300mWo•cto+-65°Cto +150°C+3oo•c1o·c

ORDER PART NO. U58773039X

SCHEMATIC DIAGRAM

CONNECTION DIAGRAM(Top View)y+5.6k.ll!Ok.II
HiZ
03 ,._ _ _ _....__ _OUTPUT
__.,
1
INPUT
1

LOW Z
OUTPUT 1!Ok.IIHI Z
OUTPUT
2 o-----+-----L. 04

LOW Z

INPUT
2

OUTPUT 1

LOW Z
OUTPUT Z

GND
2k.ll

2k.ll
2.1 k.ll

1.3 k.ll

Note: Pin 4 connected to case

GND

•Planar is a patented Fairchild process.

NOTES:(1)

Rating applies for ambient temperatures to + 70"C.

l=AIRCHILC
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-114

A DIVISION OF FAIRCHILD CAMERA A/l(D INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µ.A730C
ELECTRICAL CHARACTERISTICS (TA= 2S°C, V+ = 12.0 V, and VcM = 3.S V unless otherwise specified)
PARAMETER (See Definitions)

CONDITIONS

Input Offset Voltage
Input Offset Current
Input Bias Current
Input ResistanceDifferential Voltage Gain
Differential Distortion
Bandwidth
Single-Ended Output Resistance
Output Voltage Swing
Supply Current
Power Consumption

Rs

MIN.

s son
2.S
100

RL ~ 100 kn
RL ~ 100 kn

1.0
RL ~ 100 kn
RL ~ 100 kn
RL ~ 100 kn

The following specifications apply for 0°C
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Input Voltage Range
Common Mode Rejection Ratio

s.o

UNITS

2.0
0.7
4.S
lS
13S
8S
1.S
70
8.0
9.S
114

s.o
3.0
16.0

mV
µA
µA
kn

160
300
soo

o.s
0.8
s.o

TA =+70°C
TA= 0°C
TA= 0°C

s

1.8
+3.S
60

80

80
s.o

7.0

+3.S V S VcM S +S.2 V
RL ~ 100 kn

mVpp
MHz
n
Vpp

13
1S6

mA

7.S
3.0
s.o
20

mV
µA
µA
µA
kn

mW

+s.2
dB

7.. s
10
8.8
120
1Q6

4.S
TA= 0°C
TA =+70°C
TA= o·c
TA= +10°·c

Power Consumption

MAX.

s TA s +70°C
Rs s sonRs
sonf S 1.0 kHz,

Differential Voltage Gain
Common Mode Output Voltage
Output Resistance
Output Voltage Swing
Supply Current

TYP.

190
8.0
600

n

15
13
180
1S6

Vpp
mA
mA
mW
mW

v

TYPICAL PERFORMANCE CURVES

2.0

1.0

v• 12vTA• 25°C

0.. o.a1_ 1.6kd~

I

a~ 1.2

!E
~0.6

iii

iii
!ii 0.4i3::: o.s0r--t--t--

~
-o.4

-

1--1

0

INPUT BIAS CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

INPUT OFFSET CURRENTAS A FUNCTION OF
SUPPLY VOLTAGE

INPUT OFFSET CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE~!!!; 0.2

y
JL

L'l

1. 8.0
~

1d
)7

a

L
Z.O>---+---+-+--+---<--+--<

o.__......_--1._ _._-'---'--'---'

0

0

1020

3040506070
TEllPERATURE-'C

5.0>---+---+~+--+---<f---+--<

ill &.o >---+---+-+--+---<f---+--<

7.0

9.0

11

SUPPLY VOLTAGE-V

6-115

13

15

0

10203040506070
TEMPERATURE-"&FAIRCHILD LINEAR INTEGRATED CIRCUITS µA730C
TYPICAL PERFORMANCE CURVESINPUT RESISTANCEAS A FUNCTION OF
AMBIENT TEMPERATURE

INPUT BIAS CURRENTAS A FUNCTION OF
SUPPLY VOLTAGE

VOLTAGE TRANSFER
CHARACTERISTICS
5.0

~25"C

TA•25"~

v+•12v401---+--+-+---+---t-+-----llL-""·TA•Cl"S

3.0.s!l~°'TA•+70"C

>

If'

I

~

1.0

g

17
Ll

,_

~ -1.0gr-r-

101---+--+-+---+---t-+-----lo.___.___.__..___...___.._-+-~

1.o.'-->-,,'--'~-+-----:':--+-~-+--='-

5.0

7.0

9.0
11
SUPPLY VOLTAGE-¥

13

0

15

DIFFERENTIAL VOLTAGE GAIN
AS A FUNCTION OF
AMBIENT TEMPERATURE
190

DIFFERENTIAL VOLTAGE GAIN AS A
FUNCTION OF SUPPLY VOLTAGE

DIFFERENTIAL DISTORTION
AS A FUNCTION OF
AMBIENT TEMPERATURE

z 160

Ill
~ 150

Ill
~ 120

ffi
it

0 110

90
0

10

20

3,0 40 50
TEMPERATURE-"C

-

r-.

~ 80

~

lL

40

..

I

!

V1

~

JZ::cz::ffi~
2; 100 l----+----t---c:::7'!---t---t-+----l
~

9.0

7.0

,,

13

15

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
AMBIENT TEMPERATURE~ BO

r--t--

60~101-->----<-+--+-+--+--+--+-_,.._-I~~~ 8.0 r---+1--1--+-+-+-+--+-lt"--+J-+--1~·.........

3040506070

v•·12v7.5

g 6.51---+--+-+---+---t-+-----l~ 5,51---+--+-+---+---t-+-----l

0

ro~

~

1--1----<-+)7--+-Iz:_,._-+--+--+--+--I

s 4.o i--r--.A-+V-A-+-+-+---+--+---+--1v

4.5 .____.___.__..___..._____.._-+-~
0
10
20
30
40
50
6.0
70
TEMPERATURE-"C

2.0 '--~-+--+---+-~---+----+---+--~
5.0
7.0
9.0
II
13
15
SUPPLY VOLTAGE - V

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
LOAD RESISTANCE

SUPPLY CURRENTAS A FUNCTION OF
AMBIENT TEMPERATURE

SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

I_,...

10 t---+---+-+---+---+--+----<

50
0

1020

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
SUPPLY VOLTAGE!... _.......r

~

g

0

TEMPERATURE-"C

J,

N

VA

:!! 200 l----+----t-+--l-----..4'-----1-----l~9.51---+--+-+---+---t-+-----l

90

~ 70

300 l----+----+-+---+-__,--+17->'LJ'--l

SUPPLY VOLTAGE-¥

I

10203040506070
TEMPERATURE-"C~8.0_,,,r-

I~ii;g 7.0 t---+-+><--1----+--I--+--+--+--+---<

Ill

z

17

~P;.400 1----+----+-+---+-__,f---+----lZ'

y+.12v~50

o.___.___.__..___...___.._ _.._____.

5.0

70

OUTPUT RESISTANCEAS A FUNCTION OF
AMBIENT TEMPERATURE
100

~

0

·60

-30

TA•25"C11-i---;-5.0-503040506070

-10
10
30
INPUT VOLTAGE-mV

z 170

130

.. ~!"TEMPERATURE-"C

11

..8

20

,V

200

v•·12v

_,

10

..ti.

-3.0

lL1

9.01-----tr--i-+t--+-t-----=F"'"""+-..d::r--i=---'.L
g6.0 1-7+-+-+-++---+-t-1-++--11------1

Ml---+---+-+---+---+--+--<~6&01---+-+--+-l--+---+-+++---+---l

7.01---t---+-+---+---t-+-----l

4.0 l--+--+--+--1--1--+l--Jl--Jl--J--I~.____.__.__..____..._____.._...__,

2.0 ..__..___..___..___.__.__.____..__..___.
5.0
7.0
9.0
11
13
15

I!;

4.0 '---+-~'----+--+--+--+--+--l-~0.1 0.2
0.5 1.0 2.0
5.0 10 20
LOAD RESISTANCE - kll

0

10

20

30
40
50
TEMPERATURE-"C

6-116

60

70

SUPPLY VOLTAGE -V

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA730C

DEFINITION OF TERMS
INPUT OFFSET VOLTAGE-That voltage which must be applied between the input terminals to obtain zero differential output voltage.
INPUT OFFSET CURRENT-The difference in the currents into the two input terminals with the output at zero differential volts.
INPUT BIAS CURRENT-The average of the two input currents.
INPUT BIAS RESISTANCE-The resistance looking into either input terminal with the other grounded.
INPUT VOLTAGE RANGE-The range of voltage which, if exceeded on either input terminal, could cause the amplifier to cease functioning properly.
COMMON MODE REJECTION RATIO-The ratio of the input voltage range to the maximum change in input offset voltage over this range.
DIFFERENTIAL VOLTAGE GAIN-The ratio of the change in the differential output voltage to the change in voltage between the input terminals producing it.
DIFFERENTIAL DISTORTION-The A.C. unbalance in the output common mode voltage produced by unsymmetrical output voltage swings.
BANDWIDTH-The frequency at which the differential voltage gain is 3 dB below its low frequency value.
OUTPUT RESISTANCE-The resistance seen looking into either output terminal with the output at differential null.
COMMON MODE OUTPUT VOLTAGE-The average voltage at the two output terminals referred to ground.
OUTPUT VOLTAGE SWING-The peak-to-peak output swing that can be obtained without clipping.
SUPPLY CURRENT-The current required from the power supply to operate the device with no load.
POWER CONSUMPTION-The DC power required to operate the amplifier with no load current.

TYPICAL PERFORMANCE CURVESCOMMON MODE OUTPUT
VOLTAGE AS A FUNCTION OF
AMBIENT TEMPERATURECOMMON MODE REJECTIONRATIO AS A FUNCTION OF
AMBIENT TEMPERATURECOMMON MODE OUTPUT
VOLTAGE AS A FUNCTION OF
SUPPLY VOLTAGE
t--t---t---+---+---+-;-+-TA = 2 5 °C --J

851---+--+--+--+-+--+---t

9.0 t---t---t--+---+--+---+-----ia.o 1--t---t---+---+---+---;-+/'1.......,._v---..-___,

SOL---+---+-+--+~+--+-__.

8.0 t---t---t--+---+--+---+-----i

6.0 l--1--t--t-+:7f.k:':'-l-P'-+--+--t--1

751---+---t--+---t--;--+---t

1d'~·°Clj::t=t:=t:l;d4.0 1--f'--t---+---;-+--;-+---+--+--i

70 t---t---tf---+---+--+---+-----i

6.0 1---+---+--+---+-+---+-----i

2.0 1--1--+---+---+--+--;-+--+--+--i

65 1---+---tf---+---+--'------+---'
010203040506070~0'----+---+--+---+--'------+---'o,___,___.._.._..__..__..__..__......__....___,

1

TEMPERATURE-'C

010203040506070
TEMPERATURE-'C

6-117

5.0

7.0

9.0

11

SUPPLY VOLTAGE-V

13

15

µA733
DIFFERENTIAL VIDEO AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITSFEATURES• 120 MHz BANDWIDTH• 250 kn INPUT RESISTANCE• SELECiABLE GAINS OF 10, 100, AND 400• NO FREQUENCY COMPENSATION REQUIREDPHYSICAL DIMENSIONS(In accordance with JED EC TD·lDO)

I
.

MAt_

GENERAL DESCRIPTION - The µA733 is a monolithic two-stage differential input, differential output video
amplifier constructed on a single silicon chip using the Fairchild Planar* epitaxial process. Internal seriesshunt feedback is used to obtain wide bandwidth, low phase distortion, and excellent gain stability. Emitter
follower outputs enable the device to drive capacitive loads and all stages are current-source biased to obtainhigh power supply and common mode rejection ratios. It offers fixed gains of 10, 100, or 400 without external
components, and adjustable gains from 10 to 400 by the use of a single external resistor. No externalfrequency compensation components are required for any gain option. The device is particularly useful inmagnetic tape or disc file systems using phase or NRZ encoding and in high-speed thin film or plated wire
memories. Other applications include general-purpose video and pulse amplifiers where wide bandwidth, lowphase shift, and excellent gain stability are required.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Differential Input Voltage
Common Mode Input Voltage
Output Current
Internal Power Dissipation T0-100 (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 second time limit)

';i

.370

I
'"
I
]
.040W.'

.3o5

.185
.165

."'"~ rmnnnnrm-:~ I
019:016 DIA.

lWLILILILIMAX.
50? MIN.

1-- .115 TP

'

±8V
±5V
±GV
10 mA
500mW
-55°C to 125°C-65°C to 150°C
300°C

NOTES: All dimensions in inches
Leads are gold-plated Kovar
Package weight is 1.32 grams

ORDER PART NO. U5F7733312

CONNECTION DIAGRAMS(TOP VIEW)...

SCHEMATIC DIAGRAMGAIN SELECTFLAT PACKAGE,.
370~.260--j-370---jr, 250I.240
I .250 I

ok-U··.
10~''°'"GAIN.SEtECT!

T0-100-t=

GAIN
SELECT

019
015

1'"
'"

5

6~

065

l~_lo
T~_i

0035
"'"'

024

m

NOTES: All dimensions .in inches

FLAT-PAKORDER PART NO. U3F7733312*Planar is a patented Fairchild process.

Notes on Page 2

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-118

A DIVISION OF FAIRCHILD CAMERA AND lNSTRU~ENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA733
ELECTRICAL CHARACTERISTICS (TA= 25°C, Vs= ±6.0 V unless otherwise specified)
PARAMETER (see definitions)

CONDITIONS

Differential Voltage Gain
Gain 1 (Note 2)
Gain 2 (Note 3)
Gain 3 (Note 4)
Bandwidth
Gain 1Gain 2Gain 3

Rs= 50 n

Risetime
Gain 1Gain 2Gain 3

Rs= 50n, Vout

Propagation Delay
Gain 1Gain 2Gain 3

R5

MIN.

TYP.

MAX.

300
90
9.0

400
100
10

500
110
11

UNITS

40
90
120

MHz
MHz
MHz

= 1Vpp
10.5
4.5
2.5

10

7.5
6.0
3.6

10

ns
ns

ns

= 50 n, Vout = l Vpp

Input ResistanceGain 1Gain 2Gain 320

Input CapacitanceIn put Offset Current
Input Bias Current

Gain 2

Input Noise Voltage

Rs

4.0
30
250

kn
kn
kn

pf

2.0
0.4
9.0

= 50 n, BW = 1 kHz to 10 MHz

ns
ns
ns

3.0
20

µA
µA
µVrms

12

Input Voltage Range

v

±1.0

Common Mode Rejection Ratio
Gain 2Gain 2

Vcm = ± 1 V, f :-:;; 100 kHz
Vcm=±lV, f=5MHz

60

86
60

dB
dB

Supply Voltage Rejection Ratio
Gain 2!:..Vs= ±0.5 V

50

70

dB

Output Offset Voltage
Gain 1Gain 2 and Gain 3

0.6
0.35

1.5
1.0
3.4

v
v
v

Output Common Mode Voltage

2.4

2.9

Output Voltage Swing

3.0

4.0

Output Sink Current

2.5

3.6

mA

Output Resistance

20nPower Supply Current

18

Vpp

24

mA

NOTES:(1) For T0-100 rating applies for case temperature to 125°C; derate linearly at 6.5 mW/°C for ambient temperature above 75°C.
(2) Gain Select pins G1A and GIB connected together.
(3) Gain Select pins G2A and G2B connected together.
(4) All Gain Select pins open.

TYPICAL PERFORMANCE CURVESPHASE SHIFTAS A FUNCTIONOF FREQUENCYPHASE SHIFTAS A FUNCTIONOF FREQUENCY
-50

--'-

-150

1

-200

-350
5

6

FREQUENCY - MHZ

7

8

9

10

l

~

1

25°C

tit

l

l0.\
~
~~~ 1----ilr~rl.lI ""'

I

1

11

~

l

-JOO

4

TA~

~

I

-250

3

v5 ·±6V

~~

iI

-100

VOLTAGE GAIN
AS A FUNCTIONOF FREQUENCY

I

G'

5

10

l

50

100

FREQUENCY - MHz

6-119~++500 1000

io

I T
l l'
5

11
10

~

,'
50

100

FREQUENCY - MHZ!,,

500 lOOl

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA733
TYPICAL PERFORMANCE CURVESCOMMON MODE REJECTION RATIOAS A FUNCTIONOF FREQUENCYOUTPUT VOLTAGE SWING
AS A FUNCTIONOF FREQUENCY
1.0

GAINZ
fll 90 1-++t+-t--H-tt--+-H+r-+Vs • :t6V
o 80::::::, 'fi
TA. 25•c! 70t-++++-+--+-+~b._,,_f"'_~+-+++-t-+-+++---t
El liO t-++++-+--+-+-tt--+-+-H'r-t-+-+++---t~ 50t-++++-+--+-+-tt--+-t-t-+T"+-tb,J___,__,
1401-+-H+-+-++++--+-!-H+--+-t-t++bJ~

I :1-++-~++++--+-+-+++-1--++++---t

1.6

Vs• ±6V"!'A. 25oc

1.2

~ 5.0

lM

WM

"'z

!l1 0.8

~ 4.0

~

!i

~ 3.0

~

~ 0.6

1.0

~ L1

Ii ~NI
j_

!5

~ 0.4

\

~ 2.0

I

0.2

J

-0.2
llo'-733

5WOM

so 10010-0.4

SOil 1000

~

~

~

0

DIFFERENTIALOVERDRIVERECOVERY TIME

1.6 pA7U

~m

l.Z

vJ±s

> 1.0

_[_ Vs• ±6V

GAIN 2Vs" ±6V
R1• lkQ-------t~0.4]'IT0.2 +---+--+--1-1_________,____,_-I-__.

0

0.2

J

-o.z l--t--t--t--l--f--lf--lf--1--1,---t-0.4 ,__,__,__,__,__...._...._...._.....___.__.

-0.4-IS -100·SS

DIFFERENTIAL INPUT VOLTAGE· mV

10

20

IS

25

30

~

JS

~

~

0

W

B

20

25

v5 • ±6v

JS1l.l +---+--+--+---+-+-+--+--+--+---<

1.10 t--t--1"<~-::t---t--t--t--+--+-+--ti.2 +---+--+---+---+-+-+--+--+V___,,..d,..__.

'(1-,..

z 1.05 +---+--+--...
,-+--+---+---+---+---+---<~I.I!l1 1.0 1L;;

!l11.o ~ i..-i-v
g .9 ~~ y~~\GA N3+-t----1

g~~o.95 1-t-+--+-+-i><-~-+-'"Fo.~:-iN-+-1
~

I

y

~

.6171

.s ,_ILJ--+---+--+--+--+--+--+---t---t---<•)Qo.so-------~-~
-60
-20
100
140

.4 ,___,__,__,__~~~~~'"'-"

!1'7U

1

TEMPERATURE - •c

5

10

so

100

500 1000l

FREQUENCY - MHz

SUPPlYVOLTAGE·•V

SUPPLY CURRENTAS A .FUNCTION
OF TEMPERATUREGAIN VERSUS FREQUENCYAS A FUNCTION
OF SUPPLY VOLTAGE
GAINZTA• 25°C
RL • lkQ!'A7SJ-8

I!! .7~~¥---+---+---+--+-t--+-+----1

O.BS i--+--+--+--i--+--+---1-'~.-+--+--<

so7~ .817"-+--+--~.L_~-+--+--+-+-+--t'\

l!!o. 90 +---+--+--+--+--+--+'I\-+--+--+---<

21 (jiUn

Vs. t.6V

SUPPLY CURRENTAS A FUNCTION
OF SUPPLY VOLTAGE

Z8

TA• 25"C

201--1--1--t--+--+--+-+-+-+-I
Z4

<

e

I\'

~

vs:.•~V

vd·'t~V

l.LL

10

50

100

FREQUENCY - "9tz

LL

18

u

~

SOil 1000_y

O! 16 1--1--t--+--+--+--+-+-+-+-I
12Vs• ±6Vs

7

Wl--1--t--t--+--+--+-+-+-+-I

1Ul--1--t--t--+--+--+-+~--"k,-+-i
1.-1
~

\~

I

30

VOLTAGE GAIN
AS A FUNCTION
Of SUPPLY VOLTAGE

GAIN VERSUS FREQUENCYAS A FUNCTION
OF TEMPERATURE

I.IS . - -....
,~~,,.=,,.
1 ,-,---,---,---,----,--~S

TIN£.- ns

Tl~-nsVOLTAGE GAIN
AS A FUNCTION
OF TEMPERATURE

-10

JS

L
~ 0.8 1--+-+-+-+l~f-+vr+-TA•
IZS'C -t§1 o.6 1--+--1--1--1-L_,,_--+---+---+--+---I-0.2

O'-'--'--"'--"'--"'--"'--.J...-.J...-"'--'
0 20 40 60 80 100 120 140 160 180 20030

1.Z t--t--t--t--~,,._,e,,0,.,.+--.,.+-:,~,,---tTA• ·S5 C _'.i ZS C.. 1.0 l-l-l-1-h~.........""""'.....~

I Vs• ±3V
rJ_

~ 0.4
0

25

PULSE RESPONSE
AS A FUNCTION
OF TEMPERATURE

1. 6 ,.-.m
1.4

GAIN!
TA· z5•c
R1• lkQ

1.4

~ 0.8

20

TINE- ns

PULSE RESPONSE
AS A FUNCTION
OF SUPPLY VOLTAGE

i 0.6

W B

5

FREQUENCY - MHz

FREQUENCY • Hz

I \

GAl~J
GAl~2

> 1.0

o~~-+-~~-+-~~~~·-u~~lllllkVs• t6VTA• 25°C
RL•lkQ

1.4

6.0 R1 • lkQ

10 1-++t+-t--H-tt--+-H++-+-t-H+-l
Wk

PULSE RESPONSE,..,u

IS 1--t--t--+--+--+--+-+-+-+-I

14 +--------~~~
-60
-20
100
140
20
60
TEMPERATURE • •c

6-120

8

iL

vv

IL'.

L

,.,,.

l
SUPPLYVOLTAGE-:tV

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ.A733
DEFINITION OF TERMSDIFFERENTIAL VOLTAGE GAIN - The ratio of the change in the differential output voltage to the change in voltage between the input terminals producing it.
BANDWIDTH - The frequency at which the differential gain is 3 dB below its low frequency value.
RISE TIME- The time required for an output voltage step to change from 10% to 90% of its final value.
PROPAGATION DELAY - The interval between the application of an input voltage step and its arrival ~t either output, measured at 50% of the final value.
INPUT RESISTANCE- The resistance seen looking into either input terminal with the other grounded.
INPUT OFFSET CURRENT - The difference between the currents into the two input terminals.
INPUT BIAS CURRENT-The average of the two input currents.
INPUT VOLTAGE RANGE- The range of voltage which, if exceeded on either input terminal, could cause the amplifier to cease functioning properly.
COMMON MODE REJECTION RATIO - The ratio of a change in input common mode voltage to the resulting change in output offset voltage referredto the input.
SUPPLY VOLTAGE REJECTION RATIO- The ratio of a change in supply voltage to the resulting change in output offset voltage referred to the input.
OUTPUT OFFSET VOLTAGE- The difference between the voltages at the two output terminals with the inputs grounded.
OUTPUT COMMON MODE VOLTAGE-The average of the voltages at the two output terminals.
OUTPUT VOLTAGE SWING - The peak-to-peak output swing that can be obtained without clipping. This includes the unbalance caused by output offset
voltage.
·
OUTPUT SINK CURRENT - The peak negative current available at either output of the amplifier.
OUTPUT RESISTANCE - The resistance seen looking into either output terminal.
POWER SUPPLY CURRENT - The current required from the power supplies to operate the device with no load.

TYPICAL. PERFORMANCE CURVESOUTPUT VOLTAGE AND
CURRENT SWING AS A
FUNCTION OF SUPPLY VOLTAGE
7.0~...-.~--.-~--.---.-~~

1.0

6.0 l--jf---l-+-+-+-+-f--l--+--1

6.0

INPUT RESISTANCEAS A FUNCTION
OF TEMPERATURE

OUTPUT VOLTAGE SWING
AS A FUNCTION
OF LOAD RESISTANCE,.....

Vs· t6VTA• 25°C

10 '""GAINZ

60l--f--l-+-+-+-+v~s·~•6_vt--f--l

~ 5.0
li!

~ 4.0

{'

~ 3.0
g
~ 2.0

vr1

0

1.0 t--f--1-+-+-+-+-t--f--+--I

1.0o~~~~~~~~~-"-x~

0

3,0

100

4.0

5,0

6.0

1.0

8.0

10

50

100

zoo

500

-zo

0

zo

60

TEMPERATURE - °C

INPUT NOISE VOLTAGE
AS A FUNCTION
OF SOURCE RESISTANCE

VOLTAGE GAIN
ADJUST
CIRCUITVOLTAGE GAIN
AS A FUNCTION
OF RAoJ~'"

GAIN2
Vs• t6V
TA ·25°C
BW• lOMHzlk

1 ~~~=,,.,.....,......,.-....-.,.....,...rr-...,.--,..,.,.~-·t=6~V

F

'F

510

..Y
100

140

TA •25°C

10

10

100

0.2pf

Ii"

1 z.o

5k lilt

LOAD RESI S!ANCE • <l

f
0

lk

' SUPPLY VOLTAGE· +V

N
100 l--t-+-l+b..-"<-l--+-t+t--1--t-Hc+---t~!Ok

Radj· <l

SOURCE RESI SI ANCE • <l6-121

µA733C
DIFFERENTIAL VIDEO AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITSFEATURESPHYSICAL DIMENSIONS• 120 MHz BANDWIDTH• 250 kn INPUT RESISTANCE• SELECTABLE GAINS OF 10, 100, AND 400• NO FREQUENCY COMPENSATION REQUIRED(In accordance with JEDEC T0-100)·~~~ ji·~.040~I :165
185
MA_L

GENERAL DESCRIPTION - The µA733C is a monolithic two-stage differential input, differential output video
amplifier constructed on a single silicon chip using the Fairchild Planar* epitaxial process. Internal seriesshunt feedback is used to obtain wide bandwidth, low phase distortion, and excellent gain stability. Emitter
follower outputs enable the device to drive capacitive loads and all stages are current-source biased to obtainhigh power supply and common mode rejection ratios. It offers fixed gains of 10, 100, or 400 without external
components, and adjustable gains from 10 to 400 by the use of a single external resistor. No externalfrequency compensation components are required for any gain option. The device is particularly useful inmagnetic tape or disc file systems using phase or NRZ encoding and in high-speed thin film or plated wire
memories. Other applications include general-purpose video and pulse amplifiers where wide bandwidth, lowphase shift, and excellent gain stability are required.

,,,,,~_,,rrnnnnnrm ,~I019
016 DIA.

MAx.

lWUUUUllU __.5o? MIN.

For full temperature range performance (-55°C to 125°C), see µA733 data sheet.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Differential Input Voltage
Common Mode Input Voltage
Output Current
Internal Power Dissipation (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 second time limit)

±SV
±SV
±6V
lOmA
500mW
0°C to 70°C
-65°C to 1so 0
300°C

NOTES: All dimensions in inches
leads are gotd·plated Kovar
Package weight is 1.32 grams

ORDER PART NO. U5F7733393

c
CONNECTION DIAGRAMSCHEMATIC DIAGRAM(TOP VIEW)

G11GAIN SELECTOUTPUT l
OUTPUT 2

G1a

GAIN SELIC!

Note: Pin 5 connected to case.

Notes on Page 2*Planar is a patented Fairchild process.

FAIRCHILCJ
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-122

SEMICONDUCTORA DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA733C
ELECTRICAL CHARACTERISTICS (TA= 2S°C, Vs= ±6.0 V unless otherwise specified)
PARAMETER (see definitions)

CONDITIONS

Differential Voltage Gain
Gain 1 (Note 2)
Gain 2 (Note 3)
Gain 3 (Note 4)
Bandwidth
Gain 1Gain 2Gain 3
Risetime
Gain 1Gain 2Gain 3
Propagation Delay
Gain 1Gain 2
Gain3
Input ResistanceGain 1Gain 2Gain 3
Input CapacitanceIn put Offset Current
Input B.ias Current
Input Noise Voltage
Input Voltage Range
Common Mode Rejection Ratio
Gain 2Gain 2
Supply Voltage Rejection Ratio
Gain 2
Output Offset Voltage
Gain 1Gain 2 and Gain 3
Output Common Mode Voltage
Output Voltage Swing
Output Sink Current
Output ResistancePower Supply Current

MIN.

TYP.

MAX.

2SO
80
8.0

400
100
10

600
120
12

UNITS

Rs= son
40
90
120

MHz
MHz
MHz

Rs =SO n, Vout = 1 Vpp
10.S
4.S
2.S

12

ns
ns
ns

7.S
6.0
3.6

10

ns
ns
ns

Rs= SOn, Vout = 1 Vpp

10Gain 2

Rs= SOn, BW = 1 kHz to lOMHz

4.0
30
2SO
2.0
0.4
9.0
12

kn
kn
kn
pf
µA
µA
µVrms

s.o
30

v

±1.0
Vern= ±1 V, f ~ lOOkHz
Vcm=±lV, f=SMHz

60

86
60

dB
dB

fl.Vs= ±0.SV

so

70

dB

2.4
3.0
2.S

0.6
0.3S
2.9
4.0
3.6
20
18

v
v
v

l.S
l.S
3.4

Vpp
mA
n
mA

24

NOTES:(1) Rating applies for ambient temperatures to 70°C.
(2) Gain Select pins GrA and Gre connected together.
(3) Gain Select pins G2A and G2B connected together.
(4) All Gain Select pins open.

TYPICAL PERFORMANCE CURVESPHASE SHIFTAS A FUNCTIONOF FREQUENCYVOLTAGE GAIN
AS A FUNCTIONOF FREQUENCYPHASE SHIFTAS A FUNCTIONOF FREQUENCY
60

v5 ·'6V
TA ·~·c

50

RL = lkQ

GAIN I

N

'
1\

GAIN2

GAINl

.......,~

1..

-~~~~~..._..._..._..._..._.="~

5012345678910
FREQUENCY· t.'1iz

FREQUENCY· t.'liz

10

50

100

FREQUENCY· t.'liz""'

500 llXIJFAIRCHILD LINEAR INTEGRATED CIRCUITS µA733C
TYPICAL PERFORMANCE CURVESCOMMON MODE REJECTION RATIO.
AS A FUNCTIONOF FREQUENCYOUTPUT VOLTAGE SWING
AS A FUNCTIONOF FREQUENCY
7.0

100
GAIN 2
Vs• ±6V1--

TA· 25'C

['--,

80

!'-.....

70
6()

5.0

1--

I"b-J

4.0

N

i

lO

J.O

l

2.0

-r

l.O

l.O

0. 8
0, 6

l

f-+-+"'GA"\ll"'J-.'f-,f"-71"""=1:.....-1-t-t--1

t--+---l-"'GAcc;llN~2__,f_~_,_,L1'-+-----<-t--+--1
l--+--+--+--W.-r-1+-~=GA"'-IN~l-+--+--+---+

0.4 >-+-+--+-.,,_7-1-+--+---+-----<---+---+~

0.2 t--+-+--t-H--+--+--t-t--+--1

lOOk

lM

!OM

lOOM

f<A.753l

5

FREQUENCY - Hz

DIFFERENTIALOVERDRIVERECOVERY TIME

lO

50

FREQUENCY

MHz

500 1000100-0.4 +--+--+---+----+--+---+--+-+--~-B -W ~
05
10 5
W 3 ~ ~
TIME- ns.

PULSE RESPONSE
AS A FUNCTION
OF TEMPERATURE

PULSE RESPONSE
AS A FUNCTION
OF SUPPLY VOLTAGE=,,,

70 ~v-s-~±-6V~~~~~~~~~
...

l.6

GAIN2

TA• 25'C

1--+-+--+---t--+-t--t--+TA· 25°C

GAi N 2 +--+--+---+----+--+---+--4/lv--.<l60

Rl= lkQ

l.2 t--+-+--t---+---+---+--t-t--+--l-0.2 t--+--+---+--+--+--+--+-t--+----<

0

f'A.73l

0
!Ok

I
I

40

20 1--

T
1
l'l

!

50

JO

TA• 25°C
Rl • lkQ

6,0

PULSE RESPONSEµAnl
v 5 ~ ±6V
l.6 ----------~
l.4 t--+-+--t---t--+-t--t--+TA= 25°Cl'Vs· :!:6V

GAIN 2
Vs= i6V
RL= lkQ

µA733

l.4

RL• lkQ

l,2
50 1--+--+--+--+--+--+--+-HLJ'-+-----<

40f--+---+--t-+---f--+_,,,_J,,"1-+-+--ll/1

JO f-----1--1--1---+/1]7---.<-+---+---+--+---+

0

w

~

~

00

100

l~

~

~

~

~

r/;__ TA· 70°C

0.6
0.4

20 l--+--+---+---1-;'LJ-+--+--+-1--+--I

o+--+--+--+----+--+--+--+-+--~{[J. TA- 25'C

0.8

1--+--+--+-_,.__,..._-+--+--t--t--k-J

TA= 0°C

1,0

1

0_2

-0.2 l--+--+--+--+--+--+--+-1--+--I-0.2-0.4 +--+--+---+----+--+--+--+-+--~

-0.4
-15

-B

-10

~

0

S

10

B

00

3

M

~

-IO

-5

0

5

IO

15

20

25

30

DIFFERENTIAL INPUT VOLTAGE~ mV

TINf - ns

TIME - ns

VOLTAGE GAIN
AS A FUNCTION
OF TEMPERATUREGAIN VERSUS FREQUENCYAS A FUNCTION
OF TEMPERATURE

VOLTAGE GAIN
AS A FUNCTION
OF SUPPLY VOLTAGE

6()

35

v5- ± 6V!"'733RL• lkQ

GAIN 2-1

50

l.J 1--+--+--+--+---+---+--i-+--+----<
l.2 >--+--+--+--+--+--+-+-+V1__.,.c_.._.

40

I.02

u t--t--+--t--t--t---t-/".'.-1y-rt-_,-t-+--=:1

JO

l.00 r'T,,,;:;:f°"-&~1=::::µ~(=:J
0.98

0.96

fu'c l1A·o'c

20

TA·70°c'!I

10

~

0,94
0.92

-10
10

6()

~

00

~

50

~

SUPPLY VOLTAGE - ± V

GAIN VERSUS FREQUENCYAS A FUNCTION
OF SUPPLY VOLTAGE

SUPPLY CURRENTAS A FUNCTION
OF SUPPLY VOLTAGE

1"'7351~-----~~---~
TA= 25"C

GAIN 2

TA·25'C
50

RL· lkQ""""'

I

'

JO

20

~

I I

-

10 f--t-1

-10
I

l

70

TEMPERATURE ~~c

5

10

so

100

FREQUENCY - MHz

18.8 1----1---+----+--+--+--+-----1
18.6 I---+----+---+---+---<---+---<
~18.4

--

1---+-+---t--+--+--+---l~18.2~

24 t---+---+--+--+--+--+--<-+-+v,.._,>-+-+--+---+-+-4-+---v+--1
201--+--+---+---t--t---t---1".L'.'l-t---t---t

N

f---t-1 --1---+---IIZ-__,,_L.-"_,__+---1-----<~ 17.8 l--+-+--t---P-.......,dt--.......-+--1

16 1--+--+---+---+-v----+-tl---+-+-l

81s.o~ 17.6 f--+-+---+--+--f--""l--,~c--1

1-+--+-~v,._,,_+-+---+---t-----t-1

Vs,• ,±,8V
Vs• ±6V

V1_1,JV

lil

500 1000

17 .4 t---+---+----+--+--t---+--ll7 .2 t---+-+----+--+--t---+--l
17.0 '---1---'----'--+--'---+-~0C-"=-<~
JO
40
50
70
0
lO
20

w

Tt.MPERATURE -"C

6-124

12 >-+--+-..
L'-+--+--+--+--+-+--+---+,__~~"'-+v---'C---+--+--+-----+--+--+---'

81L

SUPPl Y VOLTAGE - ± V

FAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A733C
DEFINITION OF TERMSDIFFERENTIAL VOLTAGE GAIN - The ratio of the change in the differential output voltage to the change in voltage between the input terminals producing it.
BANDWIDTH - The frequency at which the differential gain is 3 dB below its low frequency value.
RISE TIME- The time required for an output voltage step to change from 10% to 90% of its final value.
PROPAGATION DELAY - The interval between the application of an input voltage step and its arrival at either output, measured at 50% of the final value.
INPUT RESISTANCE- The resistance seen looking into either input terminal with the other grounded.
INPUT OFFSET CURRENT - The difference between the currents into the two input terminals.
INPUT BIAS CURRENT - The average of the two input currents.
INPUT VOLTAGE RANGE- The range of voltage which, if exceeded on either input terminal, could cause the amplifier to cease functioning properly.
COMMON MODE REJECTION RATIO - The ratio of a change in input common mode voltage to the resulting change in output offset voltage referredto the input.
SUPPLY VOLTAGE REJECTION RATIO- The ratio of a change in supply voltage to the resulting change in output offset voltage referred to the input.
OUTPUT OFFSET VOLTAGE- The difference between the voltages at the two output terminals with the inputs grounded.
OUTPUT COMMON MODE VOLTAGE-The average of the voltages at the two output terminals.
OUTPUT VOLTAGE SWING - The peak-to-peak output swing that can be obtained without clipping. This includes the unbalance caused by output offset
voltage.
OUTPUT SINK CURRENT - The peak negative current available at either output of the amplifier.
OUTPUT RESISTANCE- The resistance seen looking into either output terminal.
POWER SUPPLY CURRENT - The current required from the power supplies to operate the device with no load.

TYPICAL PERFORMANCE CURVESOUTPUT VOLTAGE SWING
AS A FUNCTION
OF LOAD RESISTANCEOUTPUT VOLTAGE AND
CURRENT SWING AS A
FUNCTION OF SUPPLY VOLTAGE

7.0

""'

INPUT RESISTANCEAS A FUNCTION
OF TEMPERATURE

Vs" ±6VTA •25°C

6.0

6.0 t--+--+--+--+--+--+--+-+--t--f

5.0

v

4.0
J,O

GAIN 220 t---+-----1--+---+-v5·;t,6V---t----v

2.0
1.0 ~+--+--+--+--+--+--+-+-+--!

1.0

0~~~~~~~~~"="X~

0

J.O

JOO

4.0

5.0

7.0

6.0

8.0

JO t---+-----1--1---+--+---+----<

11

vf
JO

50

JOO 200

500

w

~

~

~

~

TEMPERATURE - °C

INPUT NOISE VOLTAGE
AS A FUNCTION
OF SOURCE RESISTANCE

VOLTAGE GAIN
ADJUST
CIRCUITVOLTAGE GAIN
AS A FUNCTION
OF RAoJ

po\73380

TA= 25°C
BW • JOMHz

60

0.2pf

F

~

'F

II

.Y

20
JO
JO

JOO

lk

ro

TA· 25°C

70

50

oo

1000 ~.,-,,,~~~~m---.~-V~s_..,..,6.,-,V

GAIN2

Vs• ±6V

I 2.0

!Dk

LOAD RESISTANCE - Q

90

0

5k

lk

SUPPLYVOLTAGE-+V!Ok

lD L_.LL.U...._.L_.Ll..Ll--l--l_l...I:==<
!Ok
lk
100
10

R olj- Q

SOURCE RESISTANCE· Q

6-125

µA737E
COLOR TV CHROMA DEMODULATORFAIRCHILD LINEAR INTEGRATED CIRCUITSGENERAL DESCRIPTION - The µA737E is a monolithic silicon integrated circuit which demodulates thechroma subcarrier information contained in a color television video signal and provides color-difference signals
at the outputs.

PHYSICAL DIMENSIONSFEATURES• DOUBLY BALANCED DEMODULATION• INTERNAL COLOR-DIFFERENCE MATRIX FOR NTSC COLOR TV• 10 VOLT PEAK-TO-PEAK E8 • Ey OUTPUT• PLUGS INTO A STANDARD 9-PIN MINIATURE TUBE SOCKET OR SOLDERS INTO A PRINTED BOARD

ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Minimum Load ResistancePeak-to-Peak Reference Input Voltage
Peak-to-Peak Chroma Input Voltage
Internal Power Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

+28V
3 kn
5V
5V
450mW
0°C to +70°C-55°C to +125°C+260°CORDER PART NO. U8F7737394

SCHEMATIC DIAGRAM
6~--<1>---+-----<11------+--<>------------------ov+

BOOQ

6.BkQ

2.3kQ

12kQ

BkQ

llkQ

CONNECTION DIAGRAM(TOP VIEW)

4.7kQ_ _ _ ____,__
22kQ__,____,. Q20

lOkQ

JOOQ

7
E6-Ey
4

. . _ - - - - - - - - n R E f '11"
REF "A"
22kQ

2.2kQ

1-1
CHROMA[+[

2kQ

CHROMA
lkQ

3.3kQ

1
~---+-----------------__...-----------nGND

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-126

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS p.A737E
ELECTRICAL CHARACTERISTICS (TA = 25°C, v+ = 24 V, Test Circuit 1 unless otherwise specified)
PARAMETERCONDITIONS

MIN.

TYP.

MAX.

UNITS

Supply Current

ec = O, RL = 1 Mn
ec = 0, RL = 1 Mn, ,TA = 70°C

4.5

8.0

11.5
12.0

mA

ec = 0ec = 0, TA = 70°C

16.5

8.0
21

25.5

mA
mA

410

mW

21
320
320

mA

Internal Power Dissipation

ec=O
ec = 0, TA = 70°C

DC Voltage at any Output Terminal

ec=O
ec = o, TA = 70°C

Absolute Value of DC
Difference Voltage between
any Two Outputs

ec = 00.2

DC Voltage at either
Reference Terminal
DC Voltage at either
Chroma Terminal
Reference Input Resistance
Reference Input Capacitance
Chroma Input Resistance
Chroma Input Capacitance· eA = e8 = ec = 0

5.8

v

ec=O

3.2

v

ec= 0
ec= 0

1.7
6.0
0.8

kn
pF

5.0

pF

Peak-to-Peak Chroma
Input Voltage
Peak-to-Peak
ER - Ey Output Voltage
Peak-to-Peak
E6 · Ey Output Voltage
Maximum Peak-to-PeakE8 • Ey Output Voltage

EB • Ey = 5Vp-p

12.5
12.0

14.7
14.3

420
16.5

mW

v
v
v

1.0

kn

0.4

0.7

v

EB • Ey = 5Vp-p

3.5

3.8

4.2

v

E8 • Ey = 5Vp-p

0.75

1.0

1.25

v

ec = 1.5Vp-p

8.0

10

v

3

DegreesER • Ey Demodulation Angle.

E8 • Ey = 5Vp-p
EB • Ey = 5Vp-p

109

EG • Ey Demodulation Angle

E8 • Ey = 5Vp-p

259

Degrees
Degrees

ER · Ey Demodulation Angle
relative to E8 - Ey
Demodulation Angle

E8 • Ey = 5Vp-p

101

106

111

Degrees

E8 • Ey Demodulation Angle
relative to E6 - Ey
Demodulation Angle

EB • Ey = 5Vp-p

96

104

112

Degrees

Highest Peak-to-Peak
Demodulator AC Unbalance
Voltage at any Output Terminal

ec= 0

0.3

0.8

v

E8 - Ey Demodu!atiqn Angla

DEFINITIONSColor-Difference Demodulation Angle - A color-difference demodulation angle is defined as the instantaneous phase of the ( +) Chrorria input signal
which produces the most positive voltage at the respective color-difference output with the phase of Reference "A" taken at 3 degrees and the phaseof Reference ''B" taken at 106 degrees.
(+) Chroma Input - A composite chroma signal containing me burst at a phase of 180 degrees is demodulated to produce specified color-difference
demodulation angles when applied to the ( +) Chroma input.

(-) Chroma Input - A composite chroma signal containing the burst at a phase of 0 degrees is demodulated to produce specified color-difference
demodulation angles when applied to the (-) Chroma input.

6-127

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA737E
TYPICAL ELECTRICAL CHARACTERISTICS(TEST CIRCUIT 1 UNLESS OTHERWISE SPECIFIED)SUPPLY CURRENT VERSUS
SUPPLY VOLTAGE

INTERNAL POWER DISSIPATIONVERSUS SUPPLY VOLTAGE

i2---T------~~

28 I--

DIFFERENCE BETWEEN THE
SUPPLY VOLTAGE AND THE
DC VOLTAGE AT ANY OUTPUT
VERSUS SUPPLY VOLTAGE

400 ~......--..--~-..----.----.-----,TA • 25°C•c·
Io +--+--+-+--+---!

24 l-+--+--l-+--+--+=-1,..-=i~rol-+---:::!--.:o!==-+--+--+--1f----------1

TA·l25'C

I--- •c • o

10.0

vV

T

t---1 TA • 25'C•c • o +--+--+-t--+--i+--+~-t,,,..-F-+---1~J~-i~-4---+-~

300~l\1.1.·1·~>JI.I>

16 1-----"-''--+--__,__,__--+--+__,f--------<

100 1---+--+---+-+--+--+__,r---lO'----'-----'-------'---'---'----'---'---'
ro

24

22

26

8"0 ro
L--'--L22-'-----'-24_.._...J26,..---'--'28

28

SUPPLY VOLTAGE - VOLTS

5UPPlY VOLTAGE· VOLTS

5UPPlY VOLTAGE - VOLTS

SUPPLY CURRENTVERSUS LOAD RESISTANCE

INTERNAL POWER DISSIPATIONVERSUS LOAD RESISTANCE

DC VOLTAGE AT ANY OUTPUT
VERSUS AMBIENT TEMPERATURE

m~

15.0 ...--.--..---.--~-,~-.--­

I\v+ .. 24v

280 f---+''V-1',_--+---t--+-+-t-TA • 25'C--t--24 l-+---l------l------l----l-1--1--4---1---l

_I"'

l'-t-

100,_._-+--+---+--t-+-+--+---+---<
iro,_._-+--+---+--+-+-+--+---+---<,__..__,....__,_..,.._--+- v• • 24 v-+-~ecaO~~ 14.61---t---+-"+t:::.....-+--+--t---i~'1'

roof-t+--t-+==f""r+~~==l:::::l12 ,___.__.__..._~__,-+____,_+---+--_,___.

"'t--+-~-~l-+-1-~--+--+-H--+--+~,_._-+"____,,_______,_____,_,__--+-_ _,___.

16

J\

14.B

ec•O

~

g

~ 14.4 1---t---+--+--+-+-'...,....._r---i
~
J__,

g

M,_._-+--+--+--t-+-+--+---+---<

14.21---+---+--f--+--I---+---+
401-+-+---+--+--+-t-+--+--+10

ro

30

50

100

roo 300

LOAD RESISTANCE - kQ

DEMODULATION LINEARITY

0'--'--'---'--'--'--~-+-~-

3

5

io

ro

30

so

ioo roo 300

14 "0 Lo___jlOL--....lro_...J.30_.J...40_5.._0-00'---...JIO .

LOAD RESI STANCE - kQ

AMBIENT TIMPERATURE - °C

DEMODULATION ANGLES
AND RELATIVE GAINSDEMODULATION SENSITIVITY
TO RELATIVE PHASING OF
REFERENCE SIGNALS

PEAK-TO-PEAK CHROMA INPUT VOIJAGE -VOLTS

DEMODULATION SENSITIVITY
TO AMPLITUDE OF
REFERENCE SIGNALSTEST CIRCUIT 1

y+ • 24V

I-- TA • 25'C•c • D.4Vp-p

INPUTS!Ok

CHROMA,v

7!

•c "1.5 p-p

fc • l.59 MHz!Ok

REFERENCES "A" AND "B",10 k

eA "' e8 m l Vp-p..-

'A • 18 • 3.58 MHz
Be • BA + 103°

'24V

0

0.4

0.8

1.2

1.6

2.0

PEAK-TO-PEAK REFERfNCE l~PUT VOLTAGES - VOLTS

RL

RL

RL

3.lk

3.3 k

3.Jk

1-1A739C
DUAL LOW-NOISE OPERATIONAL AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITSGENERAL DESCRIPTION - The µA739C consists of two identical operational amplifiers constructed on asingle silicon chip using the Fairchild Planar* epitaxial process. These low-noise, high-gain amplifiers exhibit
extremely stable operating characte.ristics over a wide range of supply voltage and temperatures. The. device
is intended for a variety of applications requiring two high performance operational amplifiers.
FEATURES• SINGLE OR DUAL SUPPLY OPERATION• LOW NOISE FIGURE, 2.0 dB• HIGH GAIN, 20,000 V/V• LARGE COMMON MODE RANGE, :1::11 V• EXCELLENT GAIN STABILITY VS. SUPPLY VOLTAGE• NO LATCH-UP• OUTPUT SHORT CIRCUIT PROTECTEDTYPICAL APPLICATIONS• DUAL OPERATIONAL AMPLIFIER• PHONO AND TAPE STERED PREAMPLIFIER• TV REMOTE CONTROL RECEIVER• DUAL COMPARATOR• SENSE AMPLIFIER• OSCILLATOR• ACTIVE FILTER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage±18V
Internal Power Dissipation (Note 1)
500mW
Differential Input Voltage±SV
Input Voltage (Note 2)±15V
Storage Temperature Range-ss•c to +12s 0 c
Operating Temperature Rangeo•cto +10°c
Lead Temperature (Soldering, 10 seconds)
2so 0 cOutput Short-Circuit Duration, TA 25°C (Note 3)
30 seconds

TYPICAL DUAL IN·LINE PACKAGE
.375
TYP.

.Oil
.009

.110
.090

L
,.023
.015

ORDER PART NO. U6E7739393=

CONNECTION DIAGRAMSCHEMATIC DIAGRAM(TOP VIEW)Y+"
OUTPUT A
OUTPUT
I.AB A

~UT

LAG A

l

NON-INVERTING..
OUTPUT B
OUTPUT
LAG 8) INPUTLAGBINPUT A
INVERTING
INPUT AOUTPUTLAG A¥-

NON-INVERTING
INPUT AllYERTlllG
llPUT A·-llVERTIN&
INPUT BNON·lllVERTING
lllPUT B
INVERTING
INPUT B

Nllll·llVERTING
INPUT B

Notes on page 2•Planar is a patented Fairchild process.

F=AIRCHILCJ
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-129

SEMICONDUCTORA DIVISION OF FAIRCi-tlLD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A739C
ELECTRICAL CHARACTERISTICS (Vs = ±15 V, RL = 50 kn to Pin 7, TA= 25°C unless otherwise specified)
PARAMETERCONDITIONS

Input Offset Voltage
Input Offset Current
In put Bias Current
In put Resistance
Large-Signal Voltage Gain
Positive Output Voltage Swing
Negative Output Voltage Swing
Output Resistance
Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Power Consumption
Supply Current
Broadband Noise Figure
Turn On Delay (See Figure 1)
Turn Off Delay (See Figure 1)
Slew Rate (unity gain) (See Figure 2)
Channel Separation (See Figure 3)

Rs s 200 n

MIN.

37
6500
+12
-14

Your= ±5.0 V

f = 1.0 kHz
Rs s 10 kn
RsslOkn
Your= 0Your= 0Rs = 10 kn, BW = 10 Hz to 10 kHz
Open Loop, V1N = ±20 mVOpen Loop, V1N = ±20 mV
c1 =O.lµF, R1 =4.7n
Rs s 10 kn, f = 10 kHz

The following specifications apply for Vs = ±4.0 V, T" = 25°C
Input Offset Voltage
Rs s 200n
In put Offset Current
Input Bias Current
Supply Current
Your= 0Power Consumption
Your= 0Large-Signal Voltage Gain
Your= ±1.0 V
Positive Output Voltage Swing
Negative Output Voltage Swing

PULSE RESPONSE
WAVEFORMS

±10
70

2500
+2.5
-3.6

FREQUENCY RESPONSETEST CIRCUIT

TYP.

MAX.

UNITS

1.0
50
300
150
20,000
+13
-15
5.0
±11
90
50
270
9.0
2.0
0.2
0.3
1.0
140

6.0
1000
2000

mV
nA
nA
kn
V/V

1.0
50
300
2.5
20
15,000
+2.8
-4.0

6.0
1000

v
v

kn

v
420
14

CHANNEL SEPARATIONTEST CIRCUITc,Figure 1

Figure 2

NOTES:(1) Rating applies at ambient temperature below 60°C, Derate at 7.7 mwl°C above 60°C.
(2) For supply voltages less than ± 15 V, the absolute maximum input voltage is equal to the supply voltage.
(3) Short circuit may be to ground or either supply.

6-130

Figure 3

dB
µV/V
mW
mA
dB
µS
µS
V/µs
dB

mV
nA
nA
mA
mW
V/V

v
v

FAIRCHILD LINEAR INTEGRAT~D CIRCUITS µ,A739C
TYPICAL PERFORMANCE CURVESINPUT NOISE VOLTAGE
AS A FUNCTIONOF FREQUENCYINPUT NOISE CURRENTAS A FUNCTIONOF FREQUENCYWIDE BAND INPUT NOISEVOLTAGE AS A FUNCTION
OF TEMPERATURE
2.0

Vs• :tl5vi=

l=1

Vs" t15V
Rs• lllllk!lt-1
TA•25°C j:::::jRs• IOO!l I-

TA·!S"C

I=

1.6

;;.

r-lwJol5kffz
r-v5•tl5V

t--Rs• lOO!l!l! 1.2

[:S
JS
N

iIll

c--

i

.I

f--i--~.4

0
FRfQlENCY • Hz

lO
«>
>D
TEMPERATURE • "C

WIDE BAND INPUT NOISE
CURRENT AS A FUNCTION
OF TEMPERATURECOMMON MODE RANGEAS A FUNCTION OF
SUPPLY VOLTAGE

TYPICAL OUTPUT VOLTAGE
AS A FUNCTION OF
SUPPLY VOLTAGE

300 1---+--+-+--+-__,>---+---I

':'

It

100

lO

lk

«II BW•20TOl5kHz
Vs• :t15V

0

IOOk

!Ok

15

15

10

lO

i

>

~

1001---+--+-+--+--l---+---to.___.___.__.__..._+-_...~

0

ii 0

~z

-5

0

8

-10

·ID

·15
10

12

14

16

10

18

14

II

16

SUPPLY VOLTAGE· t V

SUPPLY VOLTAGE • t V

OUTPUT CAPABILITY
AS A FUNCTION OF
SUPPLY VOLTAGE

TOTAL SUPPLY CURRENTAS A FUNCTION OF
SUPPLY VOLTAGE

TOTAL POWER DISSIPATIONAS A FUNCTION OF
SUPPLY VOLTAGE AND LOAD
54111

20

«II

16

fi

':'

8

i'l

~ 61---+-1--71>'"-117"-"~

12

TEMPERATURE - °C

10

70

~ -5

Ol020lO«J>Dll070

8

20

5

g

~

lO

~

<

!::;

~

"°

~Y·Hz

lllll

10

~

300

iii
;;;

i

•l---t:~i7"':.+:7-IF--

200

lllll
a.___.___._....__.__+-~~

10

2>k

12

14

16

18

1'12141611

4

12

.14

16

18J

SUl'ft.Y YOl.TAGE • !Y

SUPPLY YOl.TAGE ·!VOPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF
SUPPLY VOLTAGE

OPEN LOOP GAIN
AS A FUNCTION OF
TEMPERATURE

INPUT OFFSET CURRENTAND BIAS CURRENT AS
FUNCTIONS OF TEMPERATURE ·v0 ·0?Vrms

1;:~1~·LB~~!Ok

f"lOkHz

t::=-

0.4

lOk"'---t---t--+--+-+-"Ri.fO__,..GR_ou--jND

~

~-j_

!l!!::;

0.5

Vs"!l5V

Vs" :tl5V

1---1--+-+--+--->Vo ·0.5Vrms--l..........r--~ lSk

g lOk L10

SUPPLY VOLTAGE· tV

~

~

O.l

~

I o.z

R •JOl<O

~~~NT
t--1

u

"11_1.·>klr

111.· rn-

5k

0.1

0

o~~~-~~-~~~

4

lO

12

14

SUPPLY VOLTAGE-!V

16

18

0

lO

20

lO
«>
>D
TEMPERATURE · "C

6-131

"°

70

-+-

0
0

!lfFSET CIJRQ

l020lO«J>Oll070

TEMPERATURE - °C

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA739C
TYPICAL PERFORMANCE CURVES

CLOSED LOOP GAIN
AS A FUNCTION OF
FREQUENCY
10
IO

50

l'c 1 !J~ 1 V41Jd

Ji.

l lilllJl]\ \ITIITITI
cl.lo.LJ 4.lJl IIIIIJl
1k

lot

~.zo

~

~ 10

~
~
IOOI<

IM

r--.

I

~1 - &.olJ ·~,- 33d'-1L-+-1Htt-Vs. t 15vCS
c1·o.i.f'ii;-bcij,JTA·25°CH

I-

lk

1111

FREQUENCY • Hz

IOt

lCllk

I

0.1
1111

IOM

IM

2

g

0.2

llll

SnFIG2, PAGE2j

·lO

!OM

lot

lk

~l\

IM

!OM

CHAN~E OF A.C.
CHARACTERISTICS
WITH TEMPERATURE

CHANNEL SEPARATIONAS A FUNCTION OF
FREQUENCY

OPEN LOOP PHASE SHIFTWITHOUT COMPENSATION

llllk

FRfQUENC Y• Hz

FllEQIJENCY ·Hz

FREQUENCY COMPENSATIONNETWORK

.-1

~ 0.5

C1• im)pf 1R1- lso0<+<'[L.,......++++-+-+-++PH

0

~
~

L\

c 1• JlllpF R1• 47011' +t+t7'+*<+-+--..........,~:'.--:Fl

~ 5

§
0

~

0

~
z

[[RI!

100

~ II

~ lO

\N

5• 15Vf-- Ay•!QIB c 1·JlllpFR 1·470Q-TA·25°C

t-

>

z

cI ·lo.JJIR!33~1
I

·10

50

R1

J1I OJI TIJT v r

1111

Ill

V5· !15V
TA• 2SOC

IIIIIITI
c ~.JJJI l 1Job
1

OUTPUT VOLTAGE
SW.ING AS A FUNCTION OF
FREQUENCY FOR VARIOUS
COMPENSATION NETWORKS

OPEN LOOP FREQUENCYRESPONSE USING RECOMMENDED
COMPENSATION NETWORKS

2.0

Vs" !15V

Vs• !15V

TA= 25°CllO t-+++f--+-++f+--1f-++!4--l-++l+--l

1.6

I\

~

N

[\

~

~

' 8.1Xi;,~WRATE

IV!DfH~

f\

·2«1

0.4

SEE FIGURE f3

o .......................,.__...................._._._......__._~l~l,_,

·3111
1111

lk

lot

IOOk

IM

lOM

10

1111

lk

0

lOot

lot

0

ID

2030«150

TEMPERATURE - °C

FREQUENCY • Hz

FREQUENCY· Hz

TYPICAL APPLICATIONSTEREO PHONO PREAMPLIFIER-RIAA EQUALIZED+3DY

OUTPUT A

514'/75y- +OUTPUT B

1M!l

1M!l

750pF

~T

.002
1ootn

'm

270

270HI

kn

1.2kn

f+r
n

INPUT

TYPICAL PERFORMANCE

Gain 40 dB at 1 kHz, RIAA equalized
Input overload point, 80 mV rms
Noise level, 2µV referred to input
Signal to noise ratio, 74 dB below 10 mV
Channel separation @ 1 kHz, 80 dB

6-132

750pf

I
I OD kn

IO

10µA741
HIGH PERFORMANCE OPERATIONAL AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITS• NO FREQUENCY COMPENSATION REQUIRED• SHORT-CIRCUIT PROTECTION• OFFSET VOLTAGE NUlil CAPABILITY• LARGE COMMON-MODE AND DIFFERENTIAL VOLTAGE RANGES• LOW POWER CONSUMPTION• NO LATCH UP

PHYSICAL DIMENSIONS
in accordance with
JED EC (T0-99) outline -!~!~=h~:~.Q J~;
Lt=
-T-- --r--- -·1.305

GENERAL DESCRIPTION - The µA741 is a high performance monolithic operational amplifier constructed ona single silicon chip, using the Fairchild Planar* epitaxial process. It is intended for a wide range of analog
applications. High common mode voltage range and absence of "latch-up" tendencies make the µA741 ideal
for use as a voltage follower. The high gain and wide range of operating voitai;!es provide superior performance in integrator, summing amplifier, and general feedback applications. The µA741 is short-circuit protected, has the same pin configuration as the popular µA709 operational amplifier, but requires no external
components for frequency compensation. The internal GdB/octave roll-off insures stability in closed loop
applications.

Seating_l_

Pian~

8 Lem

.040 MAX.

~~ ~ ~~.500 MIN.016

ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Internal Power Dissipation (Note 1)
Differential Input Voltage
Input Voltage (Note 2)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 60 sec)
Output Short-Circuit Duration (Note 3)

>//~~

±22V
500 mW±30V±15V-65°C to +150°C-55°C to +125°C
300°C
Indefinite

A

A

_.045
029

NOTES. D1mens1ons as per latest J-10 committee
Alld1mens1onsm1nches
Leads are gold-plated Kovar

f>ackagewe1ghl1s l.22grams

ORDER PART NO. U587741312

SCHEMATIC DIAGRAM

CONNECTION DIAGRAM.--.------+---+-------.---------.-~v+
7(TOP VIEW)
NC

Rg
25Q

2
INVERTING INPUTOUTPUT

6

OFFSET NULL

1

NOTE: PIN 4 CONNECTED TO CASE.__ _.__ _.__ __.__ _......_._ _....__....__....__ _ _ _ _ __...--ov·
4

NOTES:(1) Rating applies for case temperatures to 125'C; derate linearly at 6.5 mW/'G for ambient temperatures above +75'G.
(2) For supply voltages less than ± 15 V, the absolute maximum input voltage is equal to the supply voltage.
(3) Short circuit may be to ground or either supply. Rating applies to + 125'G case temperature or + 75'C ambient temperature.
*Planar is a patented Fairchild process.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-133

A DIVISION Of FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A741
ELECTRICAL CHARACTERISTICS (Vs = ± 15 V, TA = 25°C unless otherwise specified)
PARAMETERCONDITIONS

Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Large-Signal Voltage Gain
Output Voltage Swing

Rs S 10 kD

MIN.

RL ~ 2kD, vout = ±lOV
RL ~ 10 kD
RL ~ 2kD

Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Power Consumption
Transient Response (unity gain)

Rs S 10 kD
Rs S 10 kD

TYP.

MAX.

UNITS

1.0
30
200

5.0
200
500

mV
nA
nA

0.3

1.0

MD

50,000
±12
±10
±12
70

200,000
±14
±13
±13
90
30
50

v
v
v
dB
µV/V
mW

150
85

Vin = 20 mV, RL = 2 kD,
CL S 100 pf

Risetime
OvershootSlew Rate (unity gain)

RL~2kDThe following specifications apply for -55°C
Input Offset Voltage
Input Offset Current
Input Bias Current
Large-Signal Voltage Gain
Output Voltage Swing%
V/µss TA s +125°C:
Rs s 10 kD

mV
nA
µA

6.0
500
1.5

RL ~ 2kD, Vout = ± 10 V

25,000±10RL~2kD

OPEN LOOPVOLTAGE GAIN

µs

0.3
5.0
0.5

v

ABSOLUTE MAXIMUM
POWER DISSIPATIONVOLTAGE OFFSETNULL CIRCUIT
500

~

f\..

105 l--l--11--t-+-+-+.,,..+<::::.+--+-~

'i'

Y1

v

~

6

~lOOl--ll--lf.-ff.-f~-L'-'--<--<--<-+---1<li~ 9'j l--ll--lr7f--+ff--f--'--'---1----1----<---I

g

300

:s

~

!'-:..

I/

90 1--lL.l"-i--t--+--+-+--+--+--+--i
100851--1--1--11--11---ll---l--t--t-+-I
w~~~~__,__.__.__.__._~

o

2

4

6

s

m

~

~

m ro

~

v-

0

25

lllS

125

AMBIENT TEMPERATURE· °C

OPEN LOOPFREQUENCY RESPONSE

TRANSIENT RESPONSETEST CIRCUIT

1ro

TRANSIENT RESPONSE
28

KIO

24

-~

rs:~

M
60

40

ro

-ro

85

65

45

SUPPLY VOLTAGE It VI

90~

16
12

~

~

I

10

100

lk

~

ro

IOk

IOOk

tLI
~

~

IM

I - - RISE

Vs· !5V_TA• 2S°C

TT

Rl•2kQCL• IOOpF

.S

IOM

1.0

TIME ·115

FREQUENCY • Hz

6-134

1.5

2.0

2.S

µA741C
HIGH PERFORMANCE OPERATIONAL AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITS• NO FREQUENCY COMPENSATION REQUIRED• SHORT-CIRCUIT PROTECTION• OFFSET VOLTAGE NULL CAPABILITY• LARGE COMMON-MODE AND DIFFERENTIAL VOLTAGE RANGES• LOW POWER CONSUMPTION• NO LATCH UP

PHYSICAL DIMENSIONS
in accordance withJEDEC '(T0-99) outline::::_J.370t

GENERAL DESCRIPTION - The µA741C is a high performance monolithic operational amplifier constructed ona single silicon chip, using th'e Fairchild Planar* epitaxial process. It is intended for a wide range of analog
applications. High common mode voltage range and absence of "latch-up" tendencies make the µA741C ideal
for use as a voltage follower. The high gain and wide range of operating voltages provide superior perform·
ance in integrator, summing amplifier, and general feedback applications. The µA741C is short-circuit pro·tected, has the same pin configuration as the popular µA709 operational amplifier, but requires no external
components for frequency compensation. The internal 6dB/octave roll-off insures stability in closed loop
applications. For full temperature range operation (-55°C to +125°C) see µA741 data sheet.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Internal Power Dissipation
Differential Input Voltage
Input Voltage (Note 1)
Storage Temperature Range T0-99
Dual-In-Line
Operating Temperature Range
Lead Temperature (Soldering, 60 sec) T0-99(Soldering, 10 sec) Dual-In-Line
Output Short-Circuit Duration (Note 2)

±lSV
500mW
±30V
±15V
-65°C to +150°C-55°C to +125°C
0°c to +70°C
300°C
260°C
Indefinite
CONNECTIO.N DIAGRAMS.305·-1~:~~I::;;;JJ,..~.185

Seating_J_, ~8l•m ~~ ~ ~~.500 MIN.

Pilne-r.016~~

NOTES: 01mens1ons as pier latest J-10 committee
Alldimens1onsmmches
Leadsaregold·platedKovar

Palkagel#eight1s l.22grams

ORDER PART NO. U5B7741393

TYPICAL DUAL IN-LINE PACKAGE

SCHE.MATIC DIAGRAM.130
NOTEt Pin 4 ._.Mtted ta - ·

NC

NC

NC

NC

OFFSET
NULL:Ne·INVERTINGINPUT

NON-INVERTING
INPUT

v-

V+
OUTPUTNOTES: All dimensions in inches
Leads are intended for insertion in hole rOws 1 .300 centers

OFFSETNULL

ORDER PART NO•. U6E7741393
NOTES:(1) For supply voltages less than ± 15 V, the absolute maximum input voltage is equal to the supply voltage.
(2) Short circuit may be to ground or either supply.

*Planar is a patented Fairchild process.

l=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-135

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µ,A741C
ELEC'fRICAL CHARACTERISTICS (Vs = ± 15 V, TA = 25°C unless otherwise specified)
PARAMETERCONDITIONS

Input Offset Voltage
Input Offset CurrentRs~ 10 kn

Mitt

Input Bias Current
Input Resistance
Large-Signal Voltage GainRL 2::: 2 kn, voul = ±1.0 v
RL 2::: 10 kn

Output Voltage Swing

MAX.

UNITS

2.0
30

6.0
200

mV

200

500

1.0
100,000

Mn

±12
±10

±14
±13
±13

v
v
v

±12

Input Voltage Range
Rs~ 10 kn

90

70

dB

30

Rs~ 10 kn

150
85

50

Power Consumption
Transient Response (unity gain)

nA
nA

0.3
20,000RL 2::: 2 kn
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio

TYP.

µV/V
mW

Vin = 20 mV, RL = 2 kn
CL~ 100 pF
µs

0.3
5.0
0.5

Risetime
OvershootSlew Rate (unity gain)

RL;:::: 2 kn%
V/µs

The following specifications apply for 0°C ~ TA ~ +70°C :
mV

7.5
300

Rs~ 10 kn

Input Offset Voltage
Input Offset Current

nA
nA

800

Input Bias Current
Large-Signal Voltage GainRL 2::: 2kn, vout= ±lOV
RL 2::: 2 kn

Output Voltage Swing

15,000v±10

TYPICAL PERFORMANCE CURVESOPEN LOOPFREQUENCY RESPONSE

OPEN LOOPVOLTAGE GAIN

TRANSIENT RESPONSE
28
24

l-..

20

90%

16

100 1--t--t---l-+-+--+---b.£.vt--t---l~t--t-+-+--+-~l,./'--+-y..--+--+--+-I
oo t--t--+--,+J.,,-'--+-v-+--+--+--+--~

I

12

L

l--10%~l--V----f-----l---l--+-+-+-+-1~

v5·!15v_
TA• 25°C~

I - - RIS<Tli

Rl•2kQCl• IOOpf

oo~..__..__..__..__.___,'--'----'----'~

0

2

4

6

8

10

12

14

16

18

20

SUPPLY VOLTAGE !"!:V)

10

100

lk

IOk

IOOk

IM

IOM

VOLTAGE OFFSETNULL CIRCUIT

TRANSIENT RESPONSETEST CIRCUIT

6-136

.5

1.0
Tlr.t: ·µS

FREQUENCY - Hz

1.5

2.0

2.5

µA751C
DIFFERENTIAL VIDEO AMPLIFIERFAIRCHILD LINEAR INTEGRATED CIRCUITSFE'ATURES• VOLTAGE GAIN 600• 2000 INPUT LINE TERMINATION• 10 ns TYPICAL PROPAGATION DELAY• NO FREQUENCY COMPENSATION REQUIREDPHYSICAL DIMENSIONS
in accordance withJEDEC (T0-99) outline

GENERAL DESCRIPTION - The µA751C is a monolithic two-stage differential input differential output video
amplifier constructed on a single silicon chip using the Fairchild Planar* epitaxial process. Internal series
feedback is used for high gain and excellent gain stability. Internal sense line termination minimizes linereflections and eliminates the need for external termination components. External frequency compensation
is not required. The device is particularly useful as a read amplifier in high-speed thin film memories. Other
applications include general purpose video and pulse amplifiers where high gain and excellent gain stability
are required. For applications where lower gain is required and where input termination is not desirable, see
the µA733 data sheet.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Differential Input Voltage
Common Mode Input Voltage (Note 1)
Output Current
Internal Power Dissipation (Note 2)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 60 second time limit)

±SV
±2V
±1 v
7.5mA
250mW
-0° to +70°C-65°C to +150°C
300°C

8 Leads.500 MIN.

.019
.016

NOTES: Dimensions as per latest J-10 committee
All dimensions in inches

Leads are gold·plated Kovar
Package weiaht is 1.22 grams

ORDER PART NO. U5B7751393

SCHEMATIC DIAGRAM .·CONNECTION DIAGRAMSPHYSICAL DIMENSIONS(TOP VIEW)(TYPICAL FLAT PACKAGE)(TOP VIEW)

TAI

MPlll1llll'UT IND

MPllllllPllllllll

Y+

IC

IC

.065

.050

-·-·
·-

llUTfllll
llUTfllll

llmllllD

ORDER PART NO. U3H7751393*Planar is a patented Fairchild process.

NOTES:(1) Input voltage limited due to internal resistor between inputs and ground.
(2) Rating applies for ambient temperatures to 70°C.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

6-137

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD LINEAR INTEGRATED CIRCUITS µA751C
ELECTRICAL CHARACTERISTICS (TA= 25°C, v+ = +4.8 V, v-= -6.0 V unless otherwise specified)
PARAMETER (see definitions, page 4)

CONDITIONS

Differential Voltage Gai.n

MIN.

TYP.

MAX.

375

600

825

Bandwidth

UNITS

MHz

30

v,N = 1.0 mVv,N = 1.0 mV

Risetime
Propagation Delay25

12Differential Input Resistance

140

Input Capacitance

ns

10

20

ns

180

220

n

2.0

pf

Output Noise Voltage

BW = 20 Hz to 30 MHz

7.5

mVrms

Common Mode Rejection Ratio

VcM = 20mV

46

dB

60

dB

Supply Voltage Rejection Ratio
Output Offset Voltage
Output Common Mode Voltage

0.9

0.5

1.5

1.8

3.5

v
v

OutputVoltage SWing

1.2

Output Resistance50

Positive Power Supply Current

11

14

mA

9.0

12

mA

Negative Power Supply Current

Vppn

TYPICAL PERFORMANCE CURVESGAIN VERSUS FREQUENCYAS A FUNCTION
OF TEMPERATURE

PHASE SHIFTAS A FUNCTIONOF FREQUENCY
H-50t--...~~-100

rA·,2rc~\"'-250
·lllO

I

5

10

80

v·· -6.0V'II 50 i-o........mt-!!!l;~;;;!~it-ii.-t--tR 1•l.2k0

50TA•25°C~~ ~1--t-+-H--t-++tt---.-+~f--i\~

80..-,--,-,,..,.-~~~-.--~-.~4.8-V~

;

.i

~~150

t:
iii-200-350v••4.8V
v··-6.0V
RL •l.2kQ

GAIN VERSUS FREQUENCYAS A FUNCTION
OF SUPPLY VOLTAGE'~A·01i30~Wt--+-+-H-+-+-+-++--+-+-+++--~

20

y+.3J~~UL

t_·~t\ .l.c~-. -4.0V

-10
I

200

TA•25°C~~:~;~

v·· -6.0V

ti-]\J

'.;!
~ 0.8

120

i..--r-

~

~

~ 0.6

s

~ 0.4

10

50

100

L

80

i

0.2

5

v+·uv -I
v··-6.0V
RL•l.2k0

180

RL ·l.2kQ~=;-1.050 100

DIFFERENTIALOVERDRIVERECOVERY TIME

1.4
1.2

10

FREQUENCY - MHz

OUTPUT VOLTAGE SWING
AS A FUNCTION.
OF FREQUENCYI

5FREQUENCY - MHz

FREQUENCY - MHz0

V"• ·6.0V;;;

11 500 1000

50 100:ur~.--\/+.6.4V~ V}.llV102030~508070

500 1000

DIFFERENTIAL INPUT VOLTAGE- mv

FREQUENCY - MHz

6-138

500 1000FAIRCHILD LINEAR INTEGRATED CIRCUITS µA751C
TYPICAL PERFORMANCE CURVESPULSE RESPONSE
AS A FUNCTIONOf TEMPERATUREv•·4.avt--~~:11·~~T)~.5c~

o.z

J,

i

~
>

-10

1.4

10

20

~·
~
O.!IO 1---t---+-+--+---t--+--"t

~
:;
g

I.I

~

$

0

v

0.6 .______.__...____.__
-lO
-20
·10

__.___.._____.
10
20
lO

OUTPUT VOLTAGE SWING
AS A FUNCTION
OF SUPPLY VOLTAGEOUTPUT VOLTAGE SWING
AS A FUNCTION
OF AC LOAD RESISTANCEOUTPUT VOLTAGE SWING
AS A FUNCTION
OF DC LOAD RESISTANCE

1.4

v!- 1.0
li!
j

~

1
l

~

!'-..

l

1.0

:A. 25°C
V +• 4.BVv-· -6.0V
RL IDCI •l.2k!l

1.Z~::4:!_~v-

0.9
-«I

~

PERCENT CHANIJE IN SUPPLY VOLTAGE

1.3

1.Z

~0.8

TEMPERATURE - "C

>

li!
j

v~

l!:

111/l-nsTA• 25°C
RL·1.zu1-t~g 1.0 I-----+---+---~-+--+--<

o.llS .___......___.__..____...____._....___.
0
10
20
30
40
50
10
ro

II

30

~

'b.~

i0.95

JZ
-0.1

~ l.Z 1-- RLl.Zlc!l"b.

~

Y+• 4.8Vv-. -6.0V

l!!ll.00 1---t---+---+--+---t--+--i

L

0.1

t-

1.lliLSl

TA•,70"C~

TA·25"C1------+---+-+--+---+-V-· -6.0VRl ·l.Zk!l

!A_•O"CL>

I

VOLTAGE GAIN
AS A FUNCTION
Of SUPPLY VOLTAGE

v+•4,8V

0.3~

VOLTAGE GAIN
AS A FUNCTIONOf TEMPERATURE

~

V1

0.8

I

0.6

I o.z

~

20

10

40

1.Z

~

~ I.I

0

0

-20

TA•25oC
V+• 4.BVv-. -6.0V

i

~

v
v

0.4

\

r

500

lk

1.0

Sk lilt

1111

500

AC LOAD RfSISIANCE !l

PERCENT CHANGE IN SUPPl.Y VOLTAGE

1k

DC lDAD RESISIANCE • ll

SUPPLY CURRENTAS A FUNCTION
OF SUPPLY VOLTAGE

SUPPLY CURRENTAS A FUNCTIONOf TEMPERATURE~.----..----..-.,.-----.--~-~~

V+•4,8Vv-• -6.ov ___,
RL• 1.Zlc!lII

l"'"ti1i:-+-r-r~!==t=::::t.=__,=1

1~101---+--+-+--+---t--+--i!
7._____.___.__..____.____._...___.
0

2.___...._...._........__.____._..__....._~-«I

1020301150!070
TEMPERATURE - "C

-211

20

PERCENT CHANGE IN SUPPLY VOLTAGES

6-139

40

Sk

!Dk

FAIRCHILD LINEAR INTEGRATED CIRCUITS µA751C

TEST CIRCUIT

lkQ

r--------------< l OUTPUT 1OUTPUT 2

V-=-6.0V

NOTE: Circuit measures device performance with common mode and differential pulses simultaneously applied and typical output loading. Pin
numbers are for T0-99 package.

DEFINITION OF TERMSDIFFERENTIAL VOLTAGE GAIN - The ratio of the change in the differential output voltage to the change in voltage between the input terminals producing it.
BANDWIDTH - The frequency at which the differential gain is 3 dB below its low frequency value.
RISE TIME- The time required for an output voltage step to change from 10% to 90% of its final value.
PROPAGATION DELAY - The interval between the application of an input voltage step and its arrival at either output, measured at 50% of the final
value.
INPUT RESISTANCE - The resistance seen between the two input terminals.
INPUT VOLTAGE RANGE- The range of voltage which, if exceeded on either input terminal, cottld cause the amplifier to cease functioning properly.
COMMON MODE REJECTION RATIO- The ratio of a change in input common mode voltage to the resulting change in output offset voltage referredto the input.
SUPPLY VOLTAGE REJECTION RATIO- The ratio of a change in supply voltage to the resulting change in output offset voltage referred to the input.
OUTPUT OFFSET VOLTAGE - The difference between the voltages at the two output terminals with the inputs grounded.
OUTPUT COMMON MODE VOLTAGE-The average of the voltages at the two output terminals.
OUTPUT VOLTAGE SWING - The peak-to-peak output swing that can be obtained without distortion. This includes the unbalance caused by output offset
voltage.
OUTPUT RESISTANCE- The resistance seen looking into either output terminal.
POWER SUPPLY CURRENT - The current required from the power supplies to operate the device with each output externally loaded with 1.2 kn.

6-140

LINEAR INTEGRATED CIRCUITS COMING SOON
Type

Function

Type

Function

µA715
µA725
µA731
µA735

High Speed Operational Amplifier
Instrumentation Amplifier
High Speed Dual Channel Sense Amplifier
Micropow~r Operational Amplifier

µA740
µA742

Field Effect Operational Amplifier
AC Power Control System (Trigac)
Radiation Resistant Operational Amplifier
Dual Operational Amplifj~fµA'744µA749

COMMUNICATIONS CIRCUITS
Second Generation linear circuits will make their biggest impact in thefield of communications. Previously limited by high noise, restrictedfrequency range, and poor dynamic range performance, linear circuits
will extend their usefulness into the microwave range with operation
above 1 GHz. An entire family of circuits is under development for
manpack, mobile, and ground based communication systems as well

as for radar, CATV, and telephone systems. These circuits will find use
as AM & FM IF amplifiers, balanced modulators and demodulatorsfor suppressed carrier systems, frequency doublers, oscillators, logarithmic amplifiers, variable phase shifters, audio mixers, ultra wideband amplifiers, multiplex decoders, and RF amplifiers.

µA715- HIGH SPEED OPERATIONAL AMPLIFIERµA735 - MICROPOWER OPERATIONAL AMPLIFIERDESCRIPTION
The µA715 is a monolithic, high speed, high gain, operational amplifierfeaturing high slew rate, low setting time, low offsets, high input
impedance, wide common mode range, high output swing, and zeroadjust. It is useful in A to D and D to A converters, phase locked loops,
video amplifiers, sample and holds, and multiplexed analog gateswhere moderate speeds and bandwidths from D.C. to 30 MHz are
required.

DESCRIPTION
Many applications of operational amplifiers call for minimum power
consumption. This amplifier features electrical performance on a parwith the µA709 but consumes much less power. Some applications
are: missiles, portable military equipment, spacecraft, ordnance andmedical electronics.

FEATURES
Input ImpedanceOpen Loop Gain
Slew Rate at Unity Gain
SUPPLY VOLTAGESTEMPERATURE RANGESPACKAGESµA725 -

10 Mn
45,00020V/µS±5to ±18V-55 to +125°C
oto +10°c
T0-5, FLATPACK, and DIP

INSTRUMENTATION AMPLIFIERFEATURESPower Consumption
Operating Supply Voltage Range
Open Loop Gain
Input Impedance
Input Offset Current
Input Offset Voltage
TEMPERATURE RANGEPACKAGE

lOOµW±3Vto ±15V
88 dB

3 Mll
2 nA
3 mV
-55 to +125°C
Oto +10°c
T0-5, FLATPACK, and DIPµA740 FIELD EFFECT OPERATIONAL AMPLIFIERDESCRIPTIONThis operational amplifier is specifically designed for use in low levelprocess control and irstrumentation systems. Second generation processing allows the design of the circuit to reach a level of complexityand performance previously attained in discrete designs requiring as
many as 100 transistors. Noise levels closely approach thermal noise
limits.

DESCRIPTION
The µA740 is a monolithic FET input high performance operational
amplifier featuring ultra high input impedance, low input current,
wide common mode range, short circuit protection, and zero adjust.
It is internally compensated for unity gain, and is useful as anintegrator, active filter, and other applications requiring high input
impedance and low input currents.

FEATURES
Noise Voltage (0.01 to 1 Hz)
Open Loop Gain
Offset Voltage Drift
Common Mode Rejection
Supply Rejection
Input Offset Current

FEATURES
Input Impedance
Input Offset Current
Open Loop Voltage Gain
Slew Rate
Output Swing
SUPPLY VOLTAGESTEMPERATURE RANGE

0.5µVp-p
120 dB
0.6µV/°C
125 dB
lOOdB
3 nAµA731 - HIGH SPEED DUAL CHANNEL SENSE AMPLIFIERDESCRIPTION
The µA731 is designed for high speed core memories operating at
cycle times down to 400 nS. The device will accept inputs from twosense lines and consists of two preamplifiers OR'd into a thresholding circuit which drives the output logic which can be used as amemory data resistor. The device features fast response time, tightthreshold accuracy and ccst:'output logic.
FEATURES
Threshold Accuracy
Threshold Range
Propogation Delay
Strobe Release Time Variation
SUPPLY VOLTAGESTEMPERATURE RANGE

2 mV*
Oto 50mV
30 nS
±5 nS
±6 Volts-55 to +125°C
Oto +70°C
PACKAGES
DIP and FLATPACK*Worst case for unit to unit, 5% power supplies and O to +70°C
temperature range.

PACKAGE

10'' Il
50 pA
100 dB
8V/µS±13V±5to ±20V-55 to +125°C
Oto +70°C
T0-5, F.LATPAGlt, and DIPµA742 - AC POWER CONTROL SYSTEM (Trigac)
DESCRIPTIONThis versatile circuit is designed for a variety of AC power controls
where it performs the interface detecti9r and signal translation to
trigger pulses for thyristors such as SCR's. The device consists of a
voltage regulator, oscillator, differential amplifier, and signal processor. Four layer functions such as integrated gate turn-off SCR's,
made possible by second generation technology, permit circuit designs
unattainable with either discrete components or first generation integrated circuits.
Firing is accomplished at the zero crossing of load current thus
minimizing RFI and allowing operation with leading, lagging, or
resistive loads. The circuit also provides adjustable hysterisis set
points, operation with either positive or negative temperature coefficient sensors, and time proportioning operation for precision control.
FEATURES
Peak Output Current
Supply Voltage Qperation
Supply Voltage Range
High Common Mode Noise Immunity
TEMPERATURE RANGE.
PACKAGE

6-141

2ADC, or AC to 440 Hz
24 V and higher-55 to +125°C
Oto +70°C
DIP

LINEAR INTEGRATED CIRCUITS COMING SOON
µA744 - RADIATION RESISTANT OPERATIONAL AMPLIFIERDESCRIPTIONThis device offers electrical performance similar to the µA709, and ispin compatible. Built using dielectric isolation, the unit is resistantto both gamma and neutron radiation and meets military post irradi·
ation specifications.
FEATURES
Input Offset Voltage
Input Offset Current
Input Bias Current
Open Loop Gain
Input Impedance
Output Voltage Swing
SUPPLY VOLTAGE
TEMPERATURE RANGEPACKAGE

1 mV
50 nA
200 nA
94 dB
100 kn±lOV±9Vto ±15V
-55 to +125°C. oto 70°C
T0-5, FLATPACK, and DIP

6-14ZµA749- DUAL OPERATIONU AMPLIFIERDESCRIPTIONThis device consists of two identical differentiai-input, single-ended
output operational amplifiers built on a single chip. These high gain,high output swing amplifiers exhibit extremely stable operating characteristics over a wide range of supply voltages and temperatures.
External loads allow high output capability and circuit flexibility.
FEATURES
Input Offset Voltage
1.0 mV
Input Offset Current
50 nA
Voltage Gain
20,000
Output Swing±13 v
SUPPLY VOLTAGE±4Vto±18V
TEMPERATURE RANGE-55 to +125°C
Oto +70°C
PACKAGE
T0-5, FLATPACK, and DIPMOS
Integrated
Circuits

MOS INTEGRATED CIRCUIT NUMERICAL INDEX
Type

Page No.

Type

Page No.

Type

Page No.

3100
3101
3102
3250
3300
3303

7-1
7-3
7-5
7-9
7-15
7-17

3304
3305/6
3320
3501
3530
3700

7-19
7-21
7-23
7-27
7-29
7-33

3701
3705
3750
3751
3800
3801

7-37
7-39
7-43
7-47
7-53
7-59

MOS/LSI CROSS REFERENCE
PACKAGES
Part No.

Device Type

MOS
3100
3101
3102
3250
3300
3303
3304
3305
3320
3S01
3530
3700
3701
3705
3750
3751
3800
3801

Dual 5 Input Gate
Dual J·K Flip Flop
Dual 3-lnput Gate
CRT Numeric Character Generator
25-Bit Static Shift Register
Dual 25-Bit Dynamic Shift Register
Dual 16-Bit Static Shift Register
64-Bit Static Shift Register
64-Bit Dynamic Shift Register1024-Bit Read Only Memory
64-Bit Static Random Access Memory
4-Channel Multiplex Switch with all channel blarrking
6-Channel Multiplex Switch
8-Channel Multiplex Switch CCSL Compatible
10-Bit D/A Converter
12-Bit A/D Converter
8-Bit Parallel Accumulator
10-Bit SER/PAR, PAR/SER

DIP

Flat Pack

6J
6J
6J
6G

5F
5F
5F
SF
SF
5F

SJ
6G
6J
3J
3J
6J
6H
6H
6H
6H

7-i

T0-5

3Q
3V
3V

3100
FIVE-INPUT GATE
MOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3100 dual five-input gate is a MOS monolithic integrated circuit. This device
can be utilized as a logic block in an all MOS system, or as a breadboarding gate in designing customer
integrated circuits. Input protection is provided on all inputs.

PHYSICAL DIMENSIONS
16 Lead Dual In-Line

FEATURES• GATE PROTECTION• INVERTED AND NON-INVERTED OUTPUT BUFFERS• AND/OR, NAND/NOR CAPABILITY

ABSOLUTE MAXIMUM RATINGS (Notes 2 & 3)
Storage Temperature
Operating TemperaturePower Dissipation at +25°C
Positive Voltage on any pin
Negative Voltage on any pin-65°Cto +iso 0 c-55°C to +as 0 c
200mW
+0.3V
-30V

ORDER PART NO. A6J310014X

CONNECTION DIAGRAMSCHEMATIC DIAGRAM

VDD

AND 1 3
AND 2 4
AND 3 501

OR 1 6
OR 2 7

AND~

~D21

OR~

OR 2

AND~

~D22

ANDJ!i

~D23

01

15 02

OR 1 10

VDD

OR~

2

AND 1 13
AND 2 12
AND 3 11

~22

~21

9

14 02
GND = 8VDD = 16

NOTE: Polarity indicators (o) external to the solidbox conform to MIL-STD-806B where 0
indicates the less positive state is active.
Internal to the box and in the remainderof this data sheet conventional MOS polarities are used, where HI= "l"-lOVand LO= "0"
Gnd.

"°"

"°"

NOTES:(I) These ratings are limiting values above which serviceability may be impaired.
(2) Voltage levels are with respect to GND Pin.

Electrical Characteristics on Page 2*Planar is a patented Fairchild process.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-1

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED CIRCUIT • 3100
ELECTRICAL CHARACTERISTICS (V 00 = -27 ±2 Volts, Load= 10 Mn, 10 pf, TA= +25°C unless otherwise specified)
MIN.

CHARACTERISTIC
Output Impedance to Ground
Input Leakage Current
Input Capacitance
Input Logic Levels"O" Level"1" Level
Input Data Pulse Width
Output Logic Levels"O" Level"l" Level
tpd+ (Q}tpd- <g>tpd+ <g>tpd- (Q}Power Consumption

TYP.

MAX.

UNITS

CONDITIONS

1.0

1.5
1.0

kn
µA
pf

lour= 100 µA
V1N = -20V
VIN= ov

-2.0

Volts
Volts
µs

-1.0

Volts
Volts
µs
µs
µs
µs
mW

5.0
0

-9.0
0.5

-10

0.4
0.4
0.4
0.6
60

TRUTH TABLE\

TA:25°C-12 >---+----+..l._,l-+---+--+--+voo = -21v t---\~-8.0 1--+--+------j\--l-+-+--+---+---l~

i f---+---<---l.l---+ll-+-+---t---1---1

5

0

-4. 0

~

>o

o...._..__........_._..-_~_,_.~..___...._~

c
ANDI

0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0
1
0

1
1

0

1
1

x
x
x

D
E
AND 2 AND 3

1
1

x
x
x

1
1

1

x
x
x

TYPICAL PROPAGATION DELAY\_...

OUTPUT OV

I
I
I
I
I

-1.0V

I

I
I

-1.0V

-l

I-- tpd-(Q)

I
I

I

I
I

tpd-[0)-1

I-I

I
OUTPUT-201-lOV

tpd+(O)-lov- - - _ _J _ I

Q

0
0
0
0
0
0
0

1
1
1
1
1
1

1
1
1
1

0
0
0
0

logical 'l' is more negative than -9.0 V
logical '0' is more positive than -2.0 V and :::; 0 V
Xis either 'l' or 'O'
BOOLEAN FUNCTION: Q =A + B + C•D•E
Q =A + B + C•D•E

INPUT OV

Q

-12

-9.0
-3.0
-6.0
VIN - INPUT VOLTAGE - VOLTS

0'our - OUTPUT CURRENT - mA

B
OR 2

A
ORI

TYPICAL
TRANSFER CHARACTERISTICS

TYPICAL .
OUTPUT CHARACTERISTIC

7-2

-lDV

I - tpd+(Q)

1

3101
DUAL JK FLIP-FLOPMOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3101 dual JK flip-flop is a MOS monolithic integrated circuit utilizing PChannel enhancement technology. This device can be utilized as a logic block in an all MOS system, or as abreadboarding flip-flop in designing custom integrated circuits. Input protection is provided on all inputs.

PHYSICAL DIMENSIONS
16.Lead Dual In-Line

r3!01

lc290-,IFEATURES• INPUT PROTECTION• BUFFERED OUTPUTS• ASYNCHRONOUS SET AND CLEAR• SEPARATE CLOCK LINES

~.171
r

1

ABSOLUTE MAXIMUM RATINGS (Notes 1 &2)
Storage Temperature
Operating TemperaturePower Dissipation at +25°C
Positive Voltage on any pin
Negative Voltage on any input pin

.141

.Oil~
.009---r:-\
1--.375--1
NOM.

1

.L
-65°C to +1so 0 c-55°C to +85°C

.----

.105
.095

200mW

+0.3V
-30V

ORDER PART NO. A6J310114X

SCHEMATIC DIAGRAM

CONNECTION DIAGRAM(TOP VIEW)

NOTE: Polarity indicators (o) external to the solidbox conform to MIL-STD-8068 where 0
indicates the less positive state is active.
Internal to the box and in the remainderof this data sheet conventional MOS polari·ties are used, where HI= "l""" -lOV
and LO= "O" "" Gnd.

PIN 8 = GND

NOTES:(1) These ratings are limiting values above which serviceability may be impaired.
'(2) Voltage levels are with respect t~ the GND Pin.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-3

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED CIRCUIT • 3101
ELECTRICAL CHARACTERISTICS (V00 = -27 ±2 Volts; TA = 25°C unless otherwise specified)
CHARACTERISTICS

MIN.

Clock Frequency
Clock Amplitude
Clock Pulse Width
Input Leakage Current
Input Capacitance
Input Logic Levels"O" Level"l" Level
Input Data Pulse Width
Output Impedance to Ground
Output Logic Levels"O" Level"l" Leveltsetuptrelease
tpd+
tpdPower Consumption

DC
-9.0
1.0

TYP.

MAX.

UNITS

CONDITIONS

250

kHz
Volts

V00 = -26V

µs

1.0

µA

5.0

V1N = -20V
VIN= ov

pf

0
-9.0
1.0

-2.0

Volts
Volts

1.0

kn

-1.0

Volts
Volts
µs
µs

µs

-10
0.5
0.5
1.0
0.5
75

µs

µs

mW

TRUTH TABLE
TYPICAL OUTPUT CHARACTERISTICS

K

J

t= n
0
0
1
1

Logical '1' is more negative
than -9.0 V

Q
t=n+l

Logical 'O' is more positive
than-2.0 Vand:::; 0

xn
0
1
xn

0
1
0
1

VoH't-+-+-+-t--t---i~

xn is the output state
at time n~0ol.-:6:::=:t:::I::.L2L.s__l___l___l___l_~s.olour· OUTPUT CURRENT - mA

TYPICAL SWITCHING WAVEFORMS/~1.""ov_ _ _-1ov----I

VJKINPUTV1KINPUTMAXIMUM FREQUENCY VERSUS
SUPPLY VOLTAGE

ov

IOOl

I

TA. 2SOC

I

i----1~DY___./~-lOV

i,"'-

~·ov
I

"""'-$'

-lOV

1--1

t---tpd+--l

VouTPUT

I

~

.A'.:

'-TEST POINT

I

:

1

I

I

~.OV-1ov-25-ii

Voo - SUPPLY VOLTAGE - VOLTS~ov
VouTPUT

IL

L";¢'.; .

i--tpd--l

I

7-4

-29

3102
3 INPUT GATE
MOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3102 is a MOS Monolithic 3-lnput Gate Integrated Circuit. This device canbe utilized as a vehicle in gaining familiarity with MOS integrated circuit logic versatility, as a building
block in an all MOS system, or as a breadboarding gate in designing complex custom integrated circuits.
Input protection is provided on all gate inputs.

PHYSICAL DIMENSIONS(In accordance with JEDEC TO:lOO).335_.......-~-_-_-_-_-_-_-_-__,....305m

ABSOLUTE MAXIMUM RATINGS (Note 1)
Storage Temperature
Operating Temperature
Positive Voltage on any Pin (Vaody = 0)
Negative Voltage on any Pin (Vsody = 0)
Power Dissipation at TA = 25°C

-65°C to +150°C-55°C to +85°C+0.3 Volt-35Volts::;200 mW

10 LEADS:morA.

SCHEMATIC DIAGRAMNOTES: All dimensions in inches
Leads are gold·plated Kovar
Package weight Is 1.02 grams

ORDER PART NO. A5F3102XXXCONNECTION DIAGRAM
D3

BODY

J

GND

TOP VIEWNOTES:(1) These ratings are limiting values above which serviceability of the device may be impaired.

F.A.IRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-5

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED CIRCUIT 3102
ELECTRICAL CHARACTERISTICS (VBody= O; TA = 25°C)

CHARACTERISTICS

MIN.

CONDITIONS

=

=

UNITS

kil

140

V00 -27 V ± 2.0 V
V01 =Gnd
V1N = -20V
V1N = -25V
V0 V6 , 10 -lOµA

R0 N(See Figure 1)
Input Leakage Current
Threshold Voltage (V1H)
Input CapacitancePower Consumption

MAX.

TYP.

n

500

=

µA

1.0
-5.5

-2.0

v
pf

4.-0
6.0

V00 = -30 V, V1N = -10 V

mW

SCHEMATIC DIAGRAM
VDD

FIG. 1nPICAL "ON" RESISTANCERESISTANCE CHARACTERISTIC

3.Z

Parameters

s 2.4

!

~ 1.6

i!i
.,.i!i 0.8

_l_

l
l

~

Conditions

TYP.

RLoad

V00 = -25V
V01 = OV

140 "'1

RoN

Yss =-20V
Vos~ -1.0V
V02 =OVsoon

Yss= -9.0V
Vos~ -1.0V
V02 = OVsoon~

I'-t--.

RoN

004.08.01216

2024

Di
G10
D2,Sl
G20
D3,S2
G30

Vcs - GATE TO SOURCE VOLTAGE· VOl.lS

GND
53

Pin 8 =Pin 10 = V0 u1
Pin 1 = Pin 9 = GND
V00 = -27V ± 2.0V

VOLTAGE LEVEL
MIN.
MAX.

LOGIC
LEVEL

NOR GATE CONFIGURATION
VIH
VIL
YoH
Vol

1
0
1
0

NANO GATE CONFIGURATION

=

-2.0V

Pin 5 GND
Pin 8 = OUTPUT
V00 = -27V ± 2.0V

-1.0V

Yoo

-9.0V
-lOV

Yoo

7-6

l

I

FAIRCHILD MOS INTEGRATED CIRCUIT 3102

FIG. 2
FIG. 3TYPICAL DRAIN TO SOURCE
CHARACTERISTICS

TYPICAL PULL-UP RESISTANCE<Ill ...--,--..,,....~~~__,_y--,_Lj <Ill~

JOO t--+--+--\1---t-!---+v-+-lr----i JOO
Rpull-up

Yoo. DRAIN VOLTAGE. VOLTS

Yoo. DRAIN VOLTAGE. VOLTS

APPLICATIONS - MOS logic will provide the versatility to build many different functions. The following circuits show how to build the functions using one
or two 3102 packages.

A

INVERTING BUFFER

NON-INVERTING BUFFER

Yoo

A

A

B
so--~~-+----~--'

C=AB+Ai.

C=AB+BA

EXCLUSIVE NOR

EXCLUSIVE OR

7-7

FAIRCHILD MOS INTEGRATED CIRCUIT 3102

Yoo

c~+l

Yoo

ii

Ao-j

Cno-j

Ao-j

Bo-j

eo--1

Li

~

~

Li

c.
o:.-f

~

-::"

C' n+I =AB + c.(A + B)
S = (A+B+Cn) C' n +I + ABC0
FULL ADDER

Yoo

Yoo
Yoo

Q

Q

Q

Q

1-os

Ro-j

Ic

1-os

Ro-j

-

RST FLIP·FLOPRS FLIP·FLOP

Ic

T

TYPED FLIP-FLOP<1>2

OUTPUTOUTPUT..J...
,-~.,..

..J...

.;:.

l

~SLOW

STATIC (DC) SHIFT REGISTER BIT

DYNAMIC 4-PHASE (4<1>')
SHIFT REGISTER BIT

7-8

3250
CRT NUMERIC CHARACTER GENERATOR
MOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3250 is a numeric character generator subsystem on a single chip. It is designed to be used in conjunction with a cathode ray tube to display numeric information. Deflection pulses
are provided to sweep the beam through a seven segment character in eight clock pulses. Video pulses
synchronized with the deflection pulses, are provided to blank the appropriate segments needed to form
numerals. Approximately 520 characters may be displayed at a 60 cps refresher rate. Parallel data from akeyboard may be entered directly into the 3250 thereby simplifying systems applications.

PHYSICAL DIMENSION

rr:::~1

1~1.011~-}oog

FEATURES:• SERIAL OR PARALLEL STORAGE BUFFER ENTRY• DIRECT KEYBOARD ENTRY• 250 kHz SEGMENT RATE
• BOTH HALF AND WHOLE ZEROS• D/A TYPE OUTPUTS AVAILABLE FOR ±x, ±y CURRENT SUMMING AMPLIFIERS• SPECIAL OUTPUTS FOR "l" OFFSET, DECIMAL POINT, AND OPTIONAL CONTROL USE• INDEPENDENCE BETWEEN CHARACTER DISPLAY AND BUFFER MOTION• 160 mW POWER CONSUMPTION• OPTIONAL CUSTOM CHARACTER SHAPES

.050

MIN.1

1r
_

g~~

~~n
22
21

090

.110

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
All Voltages and Data Input Lines
Power Supply
Storage Temperature
Operating Temperature (A6G325014X)(A6G325019X)

16

15
14
13

-30 v to +o.3 v-30V-55°C to +150°C-55°C to +85°C
0°C to +70°C

APPLICATIONS:CALCULATOR READOUTSCOCKPIT DISPLAYSTEST EQUIPMENT READOUTSDATA ACQUISITION SYSTEM READOUTSNUMERICAL CONTROL MACHINE POSITION READOUTSPROCESS. CONTROL MONITORS

uu1i

1i

_L_
~
.020
.015

~-~

I

l.--s15515.------1

ORDER PART NO. A6G325014X
ORDER PART NO. A6G325019X-55°C to +85°Co•c to 70°C

PIN CONFIGURATIONBLOCK DIAGRAM;--------------------------------------------------------------------------~

'

'

l
il I

r-;

I

1l ~ ~ l l·"""""

l
l

: Tl
l
:

1

SUIAUURRESETI""""" ""'[:'""' RRISlH CCOCI

F=>~·"'"""""'
11 ~ ~ i u.,••:' ""'""''"""'eSERlAlOUTPUTRYRTI=1~ ~ :I~~ ~:--r'°""oOUTPUTSUPPLY2(Vos 2 )OUTPUTSUPPLYl(Vos 1 )VIOEOBLANKING(V0,)

S£RIALIZERRfSCT(SRT):J ....

SERIALIZER CLOC~ ( i1s )·oom··rmSEo"""'~:~: ~~: ::;;:~TT

SERIALDATAOUTPllT(SOO)

INPUTREGISTERCLOC!\(J18l
St'~IAL DATA INPUT (SOI)

PARAl.l.Et INPUT~-------------~--------- -------- - ---- --------- ----------- ---____PARALLELDATAINPUTl(PDll)

PARALLEL!lATAINPllT4(POl4)

1___]

sum PARALLEL
lllPUT£11ABL£

3250 CRT NUMERIC CHARACTER GENERATORFAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-9

A OIVJSION OF FAIRCHILD CAMERA ANO INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED CIRCUIT 3250
ELECTRICAL CHARACTERISTICS Vee= -27 ±1.0 Volts, RL = 10 MO, CL= 10 pF (unless otherwise specified)~

SYMBOL

MAX.

UNITS

0
-9.0

-2.0
-30

Volts
Volts

0
-10

-1.0
-30

Volts
Volts

-9.0
1.0
DC

-30
10
250

Volts
µS
kHz

9.5
250
5.0

mA
mW
µA
µS
µS
µS
µs

MIN.

CHARACTERISTICS
Logic Inputs
-uQ"

ul"

TYP.

CONDITIONS

Logic Outputs

uon

ul"

<f>s, <f>s
wcp

fmax

CJN
Imax
pmax

ILx

~.

ti
tdr
t,

}

Clock
Amplitude
Width
Segment and Input Register
Frequency
Data and Control Input CapacitancePower Supply Current Drain
Power Dissipation
Input Leakage Current

pF

7.0
7.5
200
1.2
0.4
1.0
1.0
..

Rise and Fall
Times

'I

Vee= -27V
Vee= -27V
VIN= -20V}

VGG = -27V
fmax = 250 kHz

DESCRIPTION OF PIN FUNCTIONS
PIN

1, 2
23
24

3
22

SYMBOL-x,+x-y,+y

Vos 1 & 2

NAME
DEFLECTIONPULSESOUTPUT
SUPPLY

1&2
4

VDB

5,6
7,8

9

10

VIDEO
BLANKING

Video Blanking pulses,, synchronous with thex & y deflections pulses, are supplied to display a character on the CRT.

SPECIALPURPOSEOUTPUTS

Special purpose binary codes were brought
out through output buffers to be utilized forcontrol purposes. The programmed codes may
be used as follows:
To control a "one offset" circuit which isnece1isary to center the character ONE withina character position.

1100
1111
1101

To be utilized at customer option. For example
a blank space 19r decimal point control.

SYMBOLPOI 1-4

NAME
PARALLELDATAINPUTSFUNCTION
Parallel data entry is provided through POI
1-4 into the input register in synchronouswith ¢• when PE is a logical "l."

15

SDI

SERIALDATA
INPUTSD I is shifted into the MSB of the input
register when PE is a logical "O" ard t/JB ispulsed.

16

¢•

INPUT
REGISTER
CLOCK¢• is utilized to control the data manipulationof the input register. (Sea explanation for PE

1114

Vos 1 is normally connected to ground andVos 2 to -27 volts. However, for special applications, they may ba connected anywhere
between 0 and -27 volts.

0001

SDO

PIN

FUNCTION
These pulses are synchronous with the video
output. When differentially integrated, they
provide the deflection voltages necessery to
sweep a CRT beam through the basic figureeight shape.

Character "A'~'.!is displayed with this code.
An output is provided for external system control to be used at customer discretion.

17

PE

PARALLELENABLE

Data manipulation of the input register is
synchronous with ¢• and depends upon the
logical state of PE. If PE is a logical "1,"the parallel inputs POI 1-4 are loaded into
the input raglster (POI 4 = MSB). If PE isa logical "0," the parallel inputs are disabled and the input register operates in a
serial mode.

20¢s

SERIALIZER
CLOCK¢s is utilized to control the serializer. (SeeSERIALIZERRESETIf SRT is a logical "0" the serializer will
shift right one position when ¢s is pulsed.
Zero's will ba inserted into the MSB as theregister shifts right. If SRT is a logical "l,"then a one is inserted into the first stage
and the remaining seven stages ire set tozero, when ¢s is pulsed.

21

SERIALDATA'OUTPUTSDO is the LSB of the 4 bit input register. It
may ba connected to a larger buffer register.

POWER
SUPPLY=SRT-27 ± 1 v.

TIMING DIAGRAMOUTPUT DELAY, RISE AND FALL TIMES

Clock: Wcp:: Wcp:

I

I

I

LJ

I

Data Output

I

I• Time

LJ

I

I

I
I

I

I
I
I

~

I
I
I
I
I ldf : If,;:--TimeI

lI

ldr: Ir I

7-10

below.)

explanation of SRT below.)

I'FAIRCHILD MOS INTEGRATED CIRCUIT 3250
PARALLEL BUFFER APPLICATIONI POSITIOll
J POSITION

CLOCK

1 DEFLECTION

CHARACTER---<>---+-~PDSiTllN

coumR
AND

ASSOCIATED
BATllB(SERIAL BY woio
PARALLEL BY BIT)·SERIAL BUFFER APPLICATION

CLOCK

1

PoSITllN

1 DEFLECTION

CHARACTER t----<t---+-+-<~POSITllN

VIDEO BLANKlllB

coum•

J DEFLECTIONANOSATING
I

I
I

I
I

I

1

I

: L-1 : :•-; I I I__ 1._.. _.. ..._,I/"-KEYBOARD

L----1

AND

L_ _______ J ASSOCIATED SATINSCHARACTER
BUFFER(SERIAL BY WORDSERIAL BY BIT)

DEFLECTION WAVE FORMS

3250 OUTPUT~~--..o...--o-o-~o~o.---o~·­.........
o,........,...0....--......o,........,...o....--......o,........,...o....-__,u..--· .........
o-o-"'P'o-o--o"""'.-u,....----o-.

1 DEFLECTION VOLTAGE

J DEFLECTION VOLTAGE

SYNTHESIS OF x
DEFLECTION VOLTAGE

SYNTHESIS OF y
DEFLECTION VOLTAGE

7-11

FAIRCHILD MOS INTEGRATED CIRCUIT 3250
CHARACTER FORMATION3

A dashed line indicates a blanked segment (segment one is always blanked).

48:
5

The numbers indicate the order in which
segments are displayed.

2
7

6

r--,

BINARY*
INPUT
CODE

o
0000

BaB6 BaBBB

~-]
f-I

L-0001

0010

0011

0101

0100

0110

1000

0111

1001

r--,

.........,I

I

I

I

L_...1

1010

1011

8

2

BE
1101

1110

NOTES:

1. The "1100" and "1111" codes are used for special control purposes and create no corresponding display. Characters
may be inserted into these positions for special applications.
2. See pin description for special outputs provided with 0001 and 1101 input codes.

TYPICAL TIMING DIAGRAMDISPLAY PERIOD ONEDISPLAY PERIOD TWO

482

3

3

4

19-

5

I
L_

5

1

B
2

7

L

6
CHARACTER DISPLAYED

6
CHARACTER DISPLAYED

"'s
SRT

+x
-x

+y
-y

VIDEO BLANKING"0001"

<Pa
PE

PDl 1
PD1 2
PDl 3
PDl4

SDI
SDO
SEGMENT DISPLAY

8

2

3

4

5

6

8

2

3

4

5

6

7

The binary data for the character displayed in period one was available for parallel loading during segment 8 of the previous period. Actual loading occurred at the fall of

r/J• during segment one. The binary data for the character displayed during display period two was loaded serially during display period one. The input data must not change
during segment two of any display period.

7-12

LOGIC BLOCK DIAGRAM,-----,
I~•

I [o

,

u

,

I

.o

i

I

H

Ti~~~=d=W~~~I[:::

o

I

: Ho

:

~ I

1

~ ~

=r:I:L[o ' ~~---<10--<IB.--Trz..I___,,

r-

e

s::

1
1

0

1

U>

+-- - i- - - +-- - - -1]§~-~~F_JF=nt--t_;r+--i-+-t-t--t=~=::;===t-+--+-+--+--H~p- "0001" PULSE OUTPUT
kY~-- b "1100" PULSE OUTPUT
I---+---+--'-'

T -- -IIj_ J_

f- - -

1---'--'-'kY(~===~====~_,··~·. -~.~ ~ rp~ffj ~~~:~~1l-A-"'"'~(IJ:1fgf(I~
I

I T
I

I

I

8

I

t-L--111

I
R

D

I

I

_J_

I

I

10-Df0Ir1
i:~I. I 1+qT
I
PARALLEl INPUT -

!

I T

,-J
"'IT~!I;I
PlRALLELTtiuTCDllTRBL-.;BUFFER CLOtk~
SERIAL OUTPUT
;.

-..,

j

Jl

I

s

-

I

I

J_

T

I

h CNrn-·Pttl=I!
I

I
1

o

I

1

I

0

I
1

b--v.:Q!r
1

I

I

:

I

T

e

Ll'ARAL~ll!!!T_!!T~ ~.!!!:_ _

I

• •

I

1T

i

I

D

I

I

I

I

l!!fooERMATRIL_ _ _ _ _ _ _ -

I

I

I

1 ~1
~s
R

o

J!!ll.!!!._GA_!!! _J!!!J!!" m!_S!lli"BUFFER REGISTER

I

rr

S.

I

I

::a
::c

(")

tJ'

~l

i

1

;?
h_ VIDEO~·~~~--~~
c!_ r
o:F

I
I

]r~-tTTt-t---tt--~I-r--r-t--!---+--+--+-+--+---+--+---+lffif--~--irJ<('gl-----(". ---"1rl---<1DEf.[

1 DEFLECTION-:

1

tt-:==--_L,J I

0

c

T

I
I

1

' o]_ lI

ifH '~

A

I

L1

0

JI

,.J

1

l

I

R£SET

I

:~- i I
H , 1
0

y

I

-{)

I

~I
~,
I

I
!

I

o

SHIFT REGISTER CLOC~l

JJ!

1 11_oI

lcHARACTERM;;;;I;---------------- - - - ,I:-- ----- -

_____

_J

z

-I

ITI

r-

"~::a

h_ "1101" PULSE OUTPUT

c

ITI

~

p ,,.. - ••

M

::a
(")
c:

=i

w

N
U1

0

CIRCUIT DIAGRAM"0001"1"1" OFFSET)PULSE OUTPUT''1100"!itECIM~L POllT)PULSE OUTPUT.;!

"1101" PULSE OUTPUT

·~

-e

:C'

"1111"1SPACE)

PULSE OUTPUT

r-

s::

0

SERIAi. DATA OUTPUT

tA

z

-I

l'l"I

G')
P~ALL~L DATA INPUTS- - iTI I

I
I
I
I
I

~+-"!----- 0111rr 2

II
I

I

I
I
1----"-LI'-t1---_:11~T4

DEFLfctliiN VotlAsEs

I
I

I
I

REFERENCE 1
REFERENCE 2

I_ _ _ _ _ _J

SERIALIZER
CLOCK

!

l'l"I

c

~·

::0

(')

c:

=i
w
N
U'I

0

3300
25 BIT STATIC SHIFT REGISTERMOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION-The 3300 is a 25 bit Static Shift Register. It is a monolithic integrated circuit utilizing Planar II", P-channel enhancement mode MOS
technology. Input and output access is made available in 16, 8 and 1 bit increments. This device was designed for use in single phase clock sequential digitalsystems as a delay line or memory element.
PHYSICAL DIMENSIONS(In ac~ordance with JEDEC T0-100)

ABSOLUTE MAXIMUM RATINGS (Note 1)
Storage Temperature
Operating TemperaturePower Dissipation at TA = 25 • C
Voltage On Clock, Inputs and Supply Pins::o5iifi.335i.335-65°c to +150°c-55°cto +s5°c
200mW-35 Vto +0.3 V

3

Mr:

I

1

185
:165

·1: ~ mmmm ~...
--r

I

.040

NOTES: All dimensions in inches
Leads are gold·plated Kovar

Packaae weight is 1.02 grams

ORDER CODE A5F330014X

SCHEMATIC DIAGRAMBLOCK DIAGRAM

CONNECTION DIAGRAM(ONE BIT)TOP VIEW
IN 16

DATA
OUTPUT

DATA
INPUT

16

OUT 16

IN 8

0 T 8

IN 1

OUT 1

OUT 1

IN 16

IN I

OUT 16GND

INTERNALLY
GENERATED
CLOCKS*Planar is a patented Fairchild process.
NOTE: These ratings are limiting values above which the serviceability of the device may be impaired.

FAIRCHILCJSEMICDNDUCTD R
1

313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-15

A DIVISION OF FAIRCHILD CAMERA ANO INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED CIRCUIT 3300

ELECTRICAL CHARACTERISTICS (TA= 25°C, VGG (Pin 6) = -27 ± 2 V, V00 (Pin 10) = -13 ± 2 V, unless otherwise specified)

SYMBOLMIN.

CHARACTERISTICS

Wcp

lcL
VIL
VIH
cin
Ill
VOL
VoH
tdf
tdr

MAX.

50

Power Consumption
Operating Frequency
Clock Pulse Amplitude "O" level"l" level
Clock Pulse Width
Clock Pulse Rise .and Fall Time
Clock Capacitance
Clock Leakage Current
Input Amplitude"O" level"l" level
Input Capacitance
Input Leakage Current"O" level
Output Levels"1" level
Time Delay-FallTime Delay-Rise

VCP

TYP.

250
-2.0

0
-9.0
1.0

100
10
3.0
-1.0
-2.0

-9.0
2.5
-1.0
-1.0
-10

UNITS

TEST CONDITIONS

mW
kHz
Volts
Volts
µS
µS
pF
µA
Volts
Volts
pF
µA
Volts
Volts

vclock = 0 v

1.0
1.2

VGG = -27V

VCP = OVVCP = -20V

Vin= OVV1n = -20V
lout= -10 µA
lout= -10 µAµsµs

TIMING DIAGRAM

+
CLOCK
PULSE

u-

ov --+-----~

1_,Wcpr-

LJ...- - - - - - - - ·•------.

TIME

TYPICAL OPERATINGFREQUENCYVERSUS GATE VOLTAGE
1000

TA· 25'C+
750

1-----....---------•~INPUT
DATA O V - - - + - - - - - - i

TIME
500

v

~-<

\'{V

I

''
''

'

I

250

+

'
'
'
I'

'

'

\TEST POINT:''
'
'

'
DATA

OUTPUT OV(1 bit -10 V - - - - - - - - - - - - 1 delayed):I

ldf - - - I, - - - - - - - - TIME/.-1.0V,.,______...,1/;
I
f----

7-16

-25

·ZI

-29

VGG - GATE VOLTAGE - VOLTS

3303
DUAL 25-BIT DYNAMIC SHIFT REGISTERMOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3303 is a dual 25-bit dynamic shift register. It is a monolithic integrated
circuit utilizing Planar* II, P-Channel enhancement mode MOS technology. A two phase clock is used toreduce power consumption and increase speed.

PHYSICAL DIMENSIONS(In accordance with JEDEC T0-100)

ABSOLUTE MAXIMUM RATINGS (Note 1)
Clock Voltages ( Vff 1 = V ~ 2 )Data Input Voltage (V;n)-30 V to +0.3 V

Supply Voltage-30 V to +0.3 V-30 V to +0.3 V

Storage Temperature
Operating Temperature-65°C to +150°C-55°C to +85°C
0°c to +70°C( 330314X)
330319X

NOTES: All dimensions in inches
leads 8re gold-plated Kovar

Package weight is 1.02 grams

ORDER PART NOS.

LOGIC DIAGRAM

A5F330314X
A5F330319X

Vs

CONNECTION DIAGRAM
N.C.

INPUT I

25 BITSINPUT 225 BITSGND

TOP VIEWThe output device requires an external resistor (R 1), ground and power
supply (V5) and can be used either as an inverter or source follower(inverter shown).
NOTE:(!) These ratings are limiting values above which the serviceability of the .device may be impaired.
Electrical Characteristics on Page 2*Planar is a patented Fairchild process.

F.A.IRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-17

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED CIRCUIT 3303
ELECTRJCAL CHARACTERISTICS
STANDARD CONDITIONS (unless otherwise specified)
Load ... 10 M!l and 10 pf
V5 = -15V ± l.OV, VJI = -27V ± l.OV
R1= 20 k!l, TA= -55°Cto +85°C
SYMBOLCHARACTERISTICS

MIN.

Ji,,Jf2
ft1w• J! 2w
0' d

Clock Repetition Rate

10
0.4

Vg

Clock Pulse Amplitude"O" Level"l" Level

Vin

Dpw
Vo

opw
Ro
lcL

Clock Pulse Width
Clock Deiay

TYP.

MAX.
500

kHz

45

µs

0.4

""I

0
-9.0

Data Pulse Width200

Output Logic Levels
Logic "O"
Logic "l"-10Output Fall Time
Output Pulse Width

1.0

-0.5
-28

Volts
Volts

100

ns

-2.0

Volts
Volts
ns

-1.0
550
1000
100

Data Input Capacitance

4.0

Clock Input CapacitanceFan InFan Out

20
1.0
5.0

TYPICAL WAVEFORMS

!62
-4.0V

.,..

d 1=0.4µs}1 2 = 0.4 µs

Volts
Volts
ns
µs

Output Impedance to Ground
Clock Input Leakage Currentg--1--__,f/llW J'dfi1 -27V

CONDITIONS

µs

0
-26

Clock Pulse Rise and Fall Time
(10% - 90%)
Data Input Logic Levels
Logic "O"
Logic "l"

-4.0V

UNITS

-27V

-9V

DATA IN-4.0V

OUTPUTDATA-lOV.....,....::::'.:====================t===:t:l-~~~-~
Vo

Opw-----note - - - Note: Delayed 50 Bit Times

7-18

n
pf

VJ!= -26V
VJI = 0 V

pf

V;f = OVµA

3304
DUAL 16-BIT STATIC SHIFT REGISTERMOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3304 is a Dual 16-Bit Static Shift Register. It is a monolithic integrated circuit
utilizing Planar II*, P-Channel Enhancement Mode MOS Technology. It is designed to operate on a twophase clock in delay line or in serial binary or BCD data storage applications. For DC storage conditions, it isimportant that ¢ 1 is a logic "d" and ¢ 2 is a logic "l".

ABSOLUTE MAXIMUM RATINGS (Note 1)
Drain Voltage (V00 )Gate Voltage (VGG)
Clock and Data Input Voltages
Storage Temperature
Operating Temperature Range
Power Dissipation at TA-30 v to +o.3 v-30 V to +0.3 V-30 V to +0.3 V-55°c to +I50°C-55°C to +85°C
0°Cto +70°C
200mW= 25°CPHYSICAL DIMENSIONS(In accordance with JEDEC T0-100).230TP--~NOTES: All dimen'sions in inches
Leads are gold-plated Kovar
Package weight is 1.02 grams

ORDER PART# A5F330414X (-55°C to +85°C)
ORDER PART# A5F330419X (0°C to + 70°C)

SCHEMATIC DIAGRAM(ONE BIT)BLOCK DIAGRAM

CONNECTION DIAGRAM
TOP VIEW

VGG

DATA
INPUT

Yoo
IN

16 BIT
DELAY

OUT

IN

16 BIT
DELAY

DUT

GND

NOTE:

(1) These ratings are limiting values above which the serviceability of the device may be impaired.
*Planar is a patented Fairchild process.

FA RCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-19

A DIVISION OF FAJRCHJLD CAMERA AND INSTRUMENT CORPORATIONMOS INTEGRATED CIRCUIT 3304
ELECTRICAL CHARACTERISTICS(V00 -13 Volts ± 1 Volt, V66== -27 Volts ± 1 Volt, Load = 10 Mn and 10 pF, TA = -55°C to +85°C, unless otherwise specified)

CHARACTERISTIC

MIN.

Clock Repetition Rate
Clock Pulse Widths¢1 pw¢ 2 pw
Clock Delay (¢d)
Clock Pulse Rise and Fall Time
(10% to 90%)
Clock Pulse Logic Levels(¢1 & ¢2)
Logic "O"
Logic "l"Clock Pulse Input Capacitance(¢1 &¢2)
Data Pulse Width (Dpw)
Data Input Capacitance
Data Input Logic Levels
Logic "O"
Logic "l"

MAX.

UNITS

D.C.

1.0

MHz

0.4
0.4
0.01

10

TYP.

-26

µs

-2.0
-28

Volts
Volts

µs

4.0

¢1

µs

2.0
-2.0
-9.0
1.0
100
60

Output Logic Levels
Logic "O"
Logic "l"Output Impedance to Ground
Output Drive Capability= ¢ 2 = OVolt

pF

0.4

Data Input Leakage Current
Clock Input Leakage Current
Clock (¢ 2) Input Impedance

See Figure 1
See Figure 1
See Figure 1
See Figure 1

µs
µ$

10
5.0

CONDITIONS

pF

v,N = OVolt

Volts
Volts
µA
µA

v,N = -20 Voltsv,N = -26 Volts= -26 Volts= OVolt

kn

-0.5

-1.0

Volts
Volts
kn
Volts
mA
mA

-11

-10

2.0

3.0

-5.0

Power Supply Current Drain Vim
Power Supply Current Drain V66

¢1
¢2

10
2.0

Output at Logic "O"===

RL 4.0 kn to GroundV00 -13 Volts
V66 -27 Volts

TIMING DIAGRAMS::LJ---~ ~~~f~ ~CLOCK4'1 _ 2-14'1PW ~ (4'dJ _:<1>2PWI'

I

I I

I I

II

I

I

I

I

I

I

I

CLOCK</>2 _ 26 V LJ

I

I

I

I

DATA
INPUT

1 I

I I

I

I

ov, ,., . - -...., ,..., ...., ,..., r-1tri- -otfi- -otr~ -it~I

I_ - _JI-27V-90%------,,--rr-I

-~
L..,J

LJ

OV,
r- -10V L-..J

LJ

L.J

LJ

- -

I
I

I

.

-27:~---_-_---~-:;-::_:_:_u~------

g~i:uT -1~!~- - --- - - - -l__f- ---- - - 1 & BIT DELAY____,

Figure 1

Figure 2

IL

FDH&

-27
FDH6

'

.--iCl-.....--+-0-2~ _n_I

L_=__:::::[.21Jo---.1>----<:>---t-4--K.2N2845 :Z1 • %9824
11i•310211REQUIVALENT"OPTIONAL FOR HIGH CAPACITANCE LOADS:_______ J

2 PHASE-NON-OVERLAPPING CLOCK DRIVER
7-20

3305/6
64-BIT 10 STATIC SHIFT REGISTERMOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3305/6 is a 64-bit l</I static shift register. The 3305 is a Quad 16 in a DIP
package and the 3306 is a Dual 16, Single 32 in a T0-100 package. It is a monolithic integrated circuit
utilizing Planar II*, P-channel Enhancement Mode Technology.

PHYSICAL DIMENSIONS(In accordance with JEDEC T0-100)

FEATURES:• SINGLE PHASE CLOCK• LOW POWER CONSUMPTION - LESS THAN 3 mW /BIT
• HIGH SPEED OPERATION - DC TO 1.0 MHz
APPLICATIONS:
Delay line and binary or BCD storage in:• Calculators• Peripheral Equipment• Data Acquisition• Telemetry• Computers and Business Machines• Machine Control
ABSOLUTE MAXIMUM RATINGS (Note 1)
Drain Voltage (V00 )Gate Voltage (VG·G)
Clock and Data Input Voltages
Storage Temperature
Operating. Temperature Range
Power Dissipation at TA 25°C

-30 Vto +0.3 V-30 Vto +0.3 V-30 Vto +0.3 V-55°C to +150°C-55°C to +85°C
300mW

=

NOTES: All dimensions 1n inches
leads are gold-ptated Kovar
Package weight is 1.02 grams

ORDER PART NO. A5F330614X

330~ BLOCK DIAGRAM

3305 BLOCK DIAGRAM

_c-05

_c-04
IN 1

PHYSICAL DIMENSIONS

16 BIT DELAY

2

IN 2

OUTl

IN l

OUT2

IN 2

OUT3

IN 3

8

6

16 BIT DELAY

OUT 1

3
16 BIT DELAY

OUT2

GP
IN 3
9

8

32 BIT DELAY

OUT 3
9

16 BIT DELAY
15

OUT 4

.---

105
.095

CP
IN 4

L_

4

10
YGG pin 10
Yoo pin 1
Gnd pin 5

YGG pin 12, Yoo pin 13~l~j ~ORDER PART NO. A6J330514X*Planar is a patented Fairchild process.

F=AIRCHILC
SEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962·5011, TWX: 910·379-6435

7-21

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED CIRCUIT 3305/6
ELECTRICAL CHARACTERISTICS (TA= 25°C, V66 = -27 ± 2 V, V00 = -13 ± 2 V, unless otherwise specified)
SYMBOLCHARACTERISTICS

MIN.

Power Consumption
Operating Frequency
Clock Pulse Amplituded.c.
"O" level"l" level

UNITS

1.0
-2.0

mW
MHz
Volts
Volts

100

µS

10

µS
pf

-1.0
-2.0

µA

-9.0
0.3
8.0

"O" level"l" level

-1.0
-1.0
0.5
0.5

0.4
0.4

TOP VIEW
OUT 2
2

µS

lout= -10 µA
lout= -lOµA
V66 = -27V

µS

V66 = -27V

TOP VIEW
16

OUT 3

15

IN 4

CP

3

14

NC

GND

4

13

V00

NC

5

12

VGG

11

NC

10

OUT 4

9

IN 3

NC
IN 1
IN 2

Vin= OV
Vin =-20V

3306 CONNECTION DIAGRAM

3305 CONNECTION DIAGRAM

OUT 1

Yep= OV
Yep= -20V

µA
Volts
Volts

-10

Time Delay Fall
Time Delay-Rise

VGG = -27V

Volts
pf

2.5
"O" level"l" level

TEST CONDITLONS

Volts

-9.0

Input Capacitance
Input Leakage Current
Output Levels

MAX.

200

Clock Pulse Width
Clock Pulse Rise and Fall Time
Clock Capacitance
Clock Leakage Current
Input Amplitude

TYP.

8

VGG

OUT 2

IN 3

OUT 1

IN 2

GND

TIMING DIAGRAM
+
CLOCK
PULSE

u·

OV --+----~

1

r---

u-

_ _ , Wcp

----~

.,

- - - - - - - - - - TIME+DATA~--~--------....• TIMEINPUT O V

1
+
DATA

- - - - - - - - - TIME
1 -1.0V

OUTPUT OV(1 bit -10 V - - - - - - - - - - - _I delayed)
:
I

ldt-

I

1---

7-22

3320
64 BIT-40-SHIFT REGISTERMOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3320 is a 64 bit dynamic shift register plus logic for loading or recirculating
information within the circuit. It is a monolithic integrated circuit utilizing Planar* II, P-channel enhancement mode MOS technology.

PHYSICAL DIMENSIONS(In accordance with JEDEC T0-100)
.335
.305

ABSOLUTE MAXIMUM RATINGS'----->-:~~g''-----!+--~.185• CLOCK VOLTAGES (¢ 1, ¢ 2, ¢ 3, ¢ 4) • • • -30 V to +0.3 V• DATA INPUT AND STORE VOLTAGES ••• -30 V to +0.3 V• STORAGE TEMPERATURE ••.•••••• -ss·c to +150°C• OPERATING TEMPERATURE RANGE ••• -ss·c to +ss·c

10 LEADS:g:~ DIA .

FEATURES

l~~IDO~:,.

• LOW POWER - 200 µW/BIT AT 2.0 MHz• INPUT STORE AND ENTER CONTROL LOGIC• DATA AND DATA COMPLEMENT OUTPUT• INPUT GATE PROTECTION• TYPICALLY 3.0 VOLT NOISE MARGINNOTES: All d1mens1ons 1n inches
leads are gold-plated Kovar
Package weight is 1.02 grams

ORDER PART NO. A5F332014X

CONNECTION DIAGRAM

r---------------,I

I
STORE

4

64BITSI.1I

I
REGISTER _

9

I
L- -

OUTPUT l (DATA)

-

-~

-

-

-

-

I

7

_.__...._ _ OUTPUT 2 (DATA)-l;-1 6 1;-I;-

I
I

10

OUTPUT 1 (DATA)

NC

...J

cf>1 4'2 cf>3 c/>4

TOP VIEW"Planar is a patented Fairchild process.

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-23

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED CIRCUIT • 3320
ELECTRICAL CHARACTERISTICS Standard Conditions (unless otherwise specified)
Load 10 Mn and 10 pf, TA = -55°C to +85°C=

SYMBOL

Vcp

CHARACTERISTIC

MIN.

Clock Repetition Rate
Clock Pulse Width (¢ 1 & ¢ 3)

0.01
100

Clock Pulse Width (¢ 2 & ¢ 4)
Clock Logic Levels

200

Logic "O"
Logic "l"
VIN

VOL
VoH

MHz
ns

-1.0
-27

Volts
Volts

0
-10

-2.0

Volts

-24

Data Input Pulse Width

100

Volts
ns

Store Pulse Width

200

ns

CONDITIONS

at -24 Volts } seeat -24 Volts
Figure 1

Stable During tmp
See Figure 1
Stable During t,,
See Figure 1

Clock Input Capacitance

Data and Store Input Capacitance
Input Leakage to Ground

15
10

pf
pf

2.0

pf
100
1.0

µA
µA

0

-2.0

Volts

-11

-24

Volts

¢1• ¢2• ¢3. ¢4

ILX

2.0

+0.3
-24

¢p¢3

ILCP

UNITS

ns

¢v ¢4

CIN

MAX.

Data and Store Input Logic Levels
Logic "O"
Logic "l"

Cc

TYP.

Data and Store Terminals
Output Logic Levels
Logic "O"
*Logic "l"Power Per Bit**
Power Per Output Buffer

0.2
10

mW
mW

Plus Output Capacitive Load

Ve= -27V
VIN= -20V

at 2.0 MHz
at 2.0 MHz and 10 pf Load

•NOTE: A resistive load to ground will have the effect of discharging the output level (Logic "l") to ground with a time constant equivalent to the RC time constant of theexternal load.
••NOTE: The power dissipation of each of these stages decreases proportionally with frequency.

MINIMUM CLOCK REQUIREMENTS

CHARACTERISTICSYMBOL

MIN.
VALUE
(ns)

¢ 1 Pulse Width

tcd
tlm
tgh
t,,
tbh
tks
tpa
tfj
tin
tpe
t,m
tgd

100
100
200
200
100
100
0
0
0
0
100
100

'PJ Pulse Width¢ 2 Pulse Width¢ 4 Pulse Width

Sampling Width 1
Sampling Width 2¢ 4 - ¢ 1 Overlap¢ 2 - ¢ 3 Overlap¢ 2 - ¢ 4 Overlap¢ 4 - ¢ 2 Overlap¢ 3 Precharge Time
¢ 1 Precharge Time

MAX.
VALUE
(µs)

1.0

1.0

FAIRCHILD MOS INTEGRATED CIRCUIT • 3320
FIG. 1 -TYPICAL WAVEFORMS

I

I

I

i1

•I
01
------..
I

v

·Ye I

i2

\

I
I ii

j3

cl Id

•I
ol...____....

-Vcl

-Vcl

I•

1I

Im

It

I

sl

lh

IP

nI

Ik

01

lb

lk

ii

II

Im

IP

j4 -V:~.______,/.....-----..\.______,/,...--1 rI
DATA INPUT

Is

rI

Is

I
m

p

I
STORE INPUT!

IOUTPUTS :- - - - 6 4 BIT DELAY - - - -

I

m

p

I

SCHEMATIC DIAGRAM~IT 1

BITS 3 THROUGH 63

BIT 64OUTPUT
DRIVERS~~lilffiJ

•mm

--t

•2

7-25

I

FAIRCHILD MOS INTEGRATED CIRCUIT • 3320
TYPICAL INTERFACE AND INTERCONNECTION DIAGRAM.-----,,-----i
TTL;DTL

I
I: STORE

I

I

I
I

DATA

I

TTL/DTL

I

I

3320

I

I

I

I

DATA

DUAL
: INPUTI CCSL-MOS 1

DUAL
I: MOS-CCSL I
1 INTERFACE I~~~m1:EJ

L--~~--J

Vee
STORE 13320
INPUT

EXTERNAL R;;, IOkQ
FOR IMPROVED NOISE MARGIN
TO CCSL.

4f6 CLOCK GENERATOR

z1; y, TTpL 9016
z2; 'A TTpL 9002
z3; ~ TTpL 9624

r------,

I

:

ICP

12

I
JK01-1------t---t...:.!~..rL..J"l..

I~

rr

0

•

0

lflf

I

-27V

-27V

lflf ~27¥: OPTIONAi :L - _j-.1 H .. _.J

rr0

PRECHARGE ONE SHOTS WITH R = 100 0 & C = .002 µ,F FOR - 80 ns PRECHARGE PULSE.

3.30

-27V

-..1\A.~-+--------+----..

+

IOpFl

15kQ

01,03; 2N3644
02,04; 2N3641

1.5kQ
1.0W

.001pF
IOOQ

330--'V\~......___,...

s

100pF
r[MINJ••OPTIONAL BIPOLAR TO MOS INTERFACE WHERE HEAVY DRIVE CAPABILITY IS REQUIRED.

7-26

o
-27V

3501
1024-BIT STATIC READ-ONLY MEMORYMOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION- The 3501 is a 1024-bit read-only memory in a 128 word by 8 .bit fprmat. It isan
MOS monolithic integrated circuit utilizing P-channel enhancement mode techm:ilogy. The fixed program
memory must be specified by the customer and is customized by modifying one mask in the fabrication
process. This results in a fast turnaround, low cost custom memory.
FEATURES:CHIP SELECTACCESS TIME- 2.5 µs TYP.
STATIC OPERATIONLOW POWER CONSUMPTION'- 120 mW TYP.
BIPOLAR COMPATIBLE OUTPUTSPHYSICAL DIMENSION

R
IF \I
·7~-~

.050

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
All Voltages and Data Input Lines
Power Dissipation
Storage Temperatur~
Operating Temperature

MIN1

.Oil
.009

~r~

-30 Vto +0.3 V
250mW-55°C to + 150°C-ss•c to +ss•co•cto +10°c

APPLICATIONS:
Micro Programming
Code Conversion
Table Lookup
Control Logic

ORDER PART NO. A6G3501X4X (-55~C to +85°C)
A6G3501X9X (0°C to + 70°C)

LOGIC ~IAGRAM (MIL STD 8068)

PIN CONFIGURATION

N.C.

N.<

..•
CHIP SELECT READ *~·TOP vtEW

22

INPUT 621

OUTPUTOLSB20OUTPUTl

19

OllTPUT2LSBINPUTO

718

OUTPUTl

INPUTl8"'l7

OUTPUT4

INPUT2

9

16

OUTPUTS

INPllTl

10

15

OUTPUT6

INPUT4

11

14

OUTPUT 7

GROUND

12

13

118

MSB

MSS

OUTPUTS*WHE.N plllP SELECT READ IS AT GROUND THE OUTPUTS ARE FLOATING.

FA.IRCHILCJ
SE;:MICDNDUCTDR
313 FAIRCHILD DRIVE, MOU.NTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-27

A DIVISl,~;OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED CIRCUIT 3501
ELECTRICAL CHARACTERISTICS Standard Conditions (unless otherwise specified)
V00 = -13V ±1 V, V66 = -27V ±2V, Vs =-27V ±2V
Load 10 Mn, 10 pf, TA = 25°C
CHARACTERISTIC

MIN.

Input Logic Levels
Logic O
Logic 1
Output Pulse Delay
Output Logic Levels
Logic 0
Logic 1logic 1
Output Capacitance
Input Capacitance
Input Leakage
Supply Current Drainloo
IGG
Power Consumption

TYP.

0
-9.0
2.5
0
-10
-5.0

MAX.

UNITS

-2.0

Volts
Volts
µ,s

4.0
-1.0

Volts
Volts
Volts
pf
pf
µ,A

-7.0
5.0
7.0
5.0
6.5
4.0

RL = 4.0 kn, Vs= -15 V

VIN= -20V

mA
mA
mW

120

BUFFER CIRCUITCONDITIONSTYPICAL TIMING DIAGRAMINPUT !PIN 91
OUTPUTOUTPUT IPIN 17)
OUTPUT !PIN 21)
2.0ps_.., 2.5ps

INPUT PINS 7, 8, 10, 11, 22, 23, GROUNDWORST CASE CONDITION INPUT 0 OUTPUT 0
t----OCHIP SELECT READ

TYPICAL CONNECTION FOR BIPOLAR
COMPATIBLE OUTPUTTYPICAL EXPANDED MEMORY(CONNECTION FOR 256 WORDS BY 8 BITS)

CHIP SELECTJREAD #1

0
1"'
2 ,_

0
"'1
,_ 2

LOGIC LEVELS-4.0V & +5.0V

-20V

-10V

-10V

PIN 2

PIN 1

PIN13

TT)IL DEVICE~33~3501 #1

4 !;
5 C>
6

!! 4
5

OUTPUTS

6

7

3501

PIN 12....,..........
,___

...__

Vee

I-'
t-t---"

I----'

3501 #2+5.0V

cHIP SELECTREAD #2

7-28

J

3530
64-BIT STATIC RANDOM ACCESS MEMORY
MOS/LSI INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3530 is a 64 word by 1 bit Non-Destructive Read Out (NDRO) static Random
Access Memory. It is a P-channel enhancement mode monolithic integrated <;ircuit utilizing Planar II* technology. Bit address is achieved by a 6 line binary decoder included on the chip. Memory system implementation is simplified by providing on chip initiate and chip select control lines for data steering.

PHYSICAL DIMENSIONS
16 Lead Dual In Line

r3!01
lc290:=JIFEATURES:• LOW. POWER CONSUMPTION - 2·3 mW/BIT• COMMON DATA BUSSING - WIRED-OR CAPABILITY• SMALLER SYSTEM SIZE - 16 PIN DIP PACKAGE• SIMPLIFIED SYSTEM DESIGN - ON CHIP CONTROL LOGIC~.009-.r\.Oll.

1-375--1
NOM.

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Storage Temperature
Operating Temperature
Voltage on any pin (Pin 8 at GND)
Total power dissipation in package (TA= 85°C)-65°C to +1so 0 c-55°C to +ss 0 c-30 Vto +0.3 V
500mW

APPLICATIONS:SCRATCH PAD MEMORY - MOS SYSTEMSSYSTEM CONTROLDATA ACCUMULATIONDATA STORAGE• CARD READERS• COMPUTER PERIPHERAL EQUIPMENT• AIRBORNE AND MISSILE MEMORY SYSTEMS• DESK CALCULATOR MEMORIESORDER PART NO. A6J353014X

PIN CONFIGURATIONLOGIC DIAGRAM (MIL STD 8068)
DATA IN

A0

CHIP SELECTBllTADDRESS~ DATA INPUT

cs

{ A
BIT
1
ADDRESS

2

15

WRITE ENABLE---0 AoA,

3

14

INITIATE'CHIP SELECT

4

13

READ ENABLE

12DATA OUTPUT---0 Al---0 A2---0 A3

WE
3530
64W/IB

WRITE ENABLE
INITIATE
READ ENABLE

A4AA, } BIT'
ADDRESS
GND a...;.s_ _....;..i A,
N.C.

7

::

---0 A50

TOP VIEWDATA OUT

l=AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435. 7-29A DIVISION OF FAIRCHILD CAMERA ANO INSTRUMENT CORPORATIONFAIRCHILD MOS/LSI INTEGRATED CIRCUIT 3530
ELECTRICAL c;HARACTERISTICS (TA= -55°C to +85°C, V00 = -13 V ±2 V, Vee= -27 V ±2V)
SYMBOLCHARACTERISTIC

MIN.

VIL
VIH

Input Logic Levels(data and control lines)
Logic 0
Logic 1

-9.0

Vol
VoH

Output Logic Levels(data and control lines)
Logic 0
Logic 1
Input Leakage(data and control lines)

MAX.

UNITS

-2.0

Volts
Volts

-1.0

Volts
Volts

RL = 10 Mn

5.0

µA

V1N = -15V

TYP.

-10

CONDITIONS

5.0

pf

V1N = 0 Y, f = 1.0 MHz

loo
lee

Input Capacitance(data and control lines)
Power Supply Current
Drain Power Supply Current
Gate Power Supply Current

7.0
5.0

mA
mA

Y00 = -13 Y, Yee= -27 Y
Y00 = -13V, Vee= -27V

225

mW

Y00 = -13 Y, Yee= -27 V

ZOL

Power Consumption
Output ImpedanceKn

fol= 100 µ.A

µ.S
µ.s
µ.S

CL= 15 pf
CL= 15 pf
CL= 15 pf

2.0

Initiate Pulse Timing
ti
t2
t3

!

0.5
1.0
2.0

See Timing Diagram

TIMING DIAGRAM

I

0\

WRITE
BIT A

I

READ
BIT A

WRITE
BIT A

WRITE
&
READ
BIT c

WRITE
BIT B

I

READ
BIT A

I

READ
BIT B

I

READ
BIT c

I

1r
ADDRESS LINES

I

01

I
I

111---------------CHIP SELECT

1
I

0r
I

7

1~-------'-----'----------'----'---------1r
DATA INPUT

I

0 ----. - - - - ,I

11r ____ ~ ____ ~ ___----.

~---_ . . . .__. I.

I

I

DATA INPUT MAY BE
EITHER HIGH OR LOWr..__ _.._, - - - - L - - - -.1... - - -

I
I

I
I

1

I

01
WRITE ENABLE

I

1

11----

I
I

I

I

1

01~-­

READ ENABLE

I

11
I

INITIATEDATA OUTPUT

A: The initiate line may function as a chip select if the chip select line is tied permanently to a Logic "l".
B: With the initiate line tied permanently to a Logic "l", the write or read enable line may be used to perform the enable function when they areapplied like the initiate line in the above diagram (t3 MIN usually increases slightly when the memory is operated this way).
C: ti' t 2 and t 3 measurements are made from the -3.0 or -8.0 volt levels.

7-30

FAIRCHILD MOS/LSI INTEGRATED CIRCUIT 3530
ELECTRICAL CHARACTERISTICSMINIMUM INITIATE PULSEWIDTH VERSUSAMBIENT TEMPERATURE

DEFINITION OF
PROPAGATION DELAY

1-13Y

2.0

Yoo

INITIATE

f-YG8·' -27V +---+--t---t---1--i

i

i

OL_

-VIN

O~
-Your
! ~

-+-

i!
1.0

f-i---::::;~-F==+--+-+--+--1

OUTPUT•~I o.5 1-----+--+---+--+---+--+---1

I''
OUTPUT

-55

-35

-15

+5

+25

+45

+65

t--+--+-+--+--+-b4J....-1F-l...-v-1-1

1.0 >---"f')...-'"--11--1-+---l----l--+---l---I;i

I tpd+-

i 0.5 1---+---+--+---+--+--+---+----i

O_J
~

-vour

+85

1.5

i

voil • -13V~· -27~-+--+--+--+--1----1:>&'

O'---'--..__-'--..__-'---'---'

2.0I

1.5 !----+--+--+--+--+--+---I!!

TYPICAL PROPAGATION DELAY
VERSUS
LOAD CAPACITANCE:

TA · AMBENT TEMPERATURE • "C

50

'

'

100

150

200

Cl · WD CAPACITANCE -pf

MULTICHIP MEMORYADDRESS LINESM CHIP SELECT LINESlI

r--<j RE1CS~~ l=+•2•n+--+-+-e

rlwE
rtj p

o

IO-l-+--+-t---.
•o In-+-+--+-+-+--+-_.
A3
A4 IO+-f-+--if-+--1••.,

r--0 WE

rO

l

CS

I

,---0 RE(~ 64xM WORDS)

I-'

t--+-<., IU+-t-+-.

., IO-I--+--+-+--.
•• I0+-1-+--il-+-...
•• lo+-+-+-+-+-+-..

p0,---0 RE,-0 WE

rO

I

p

0

I

I

l

I

I

cs
••

••

~WE

I-'

!-+-<

., ID+-1-+--t
A3 ID-+-+--+-+-e
A4 IO-l-l-+--if-+--f~·•• IO-I--+--+-+-+--+-...

cs

~RE

~~ !=+., ID+-+-+--t~WE., l<>+-+--+-+--41•• in+-+--+--<--+-....

~·•• IO-I--+--+-+-+--+-..

.____,I_____.

H-f-tj•Et-ftj WE~·~~

j:::i__,

A2 K>+--+-+-e

1
~RE

CS

., K>-1-+--+-+--.
•• IO+-t-+--il-+--1•• IO-l-+--+-+-+-+--1

-0
cs

•o

••

H

!-+-<

., I0+-1-+--t., IO-l-+--+-+-4•• lu-+-+--+--<--+--4'•• K>-1-+--+-+-+-+--t.____,I_____.

N DATA INPUTS &N DATA OUTPUTS
1~woRDLENGTH

OF N BITS)

I
I

I

l
t--t---j-tj

IRE•• >-•,in--~•,ID-----'

~WE

ttj

CS

•• >----'

A4IO-----'

p

0

1

•• I D - - - - - - - '

l
H-fo

I

•• >--

RE•210--~

WE• , >---'

~WE

~·

cs

CS

RE

•,ID----'•,10------'o•s I O - - - - - - '

1

••.,

•210--~

A3IO-----'•,10----~.____,,...-........

•slO-----~ItIT-b-INITIATEWRITE ENABLE
READ ENABLE~---------------------------------~---~-·--------------'

7-31

FAIRCHILD MOS/LSI INTEGRATED CIRCUIT 3530
SCHEMATIC DIAGRAM~~~~-~~~~~~~~~-.--o'GG.-+-..-+--.-+-++-++-+-+-+-t--+-t-+-+--++--+-+---._,_,__,f<-+----0•10'-+---<>READ EIABU'+----+---<>WAITE EIMILE

r-fi=li=fi~E:::::r=h==t=fl=t=t=l° '••111

DATl OUTPIT

r---------- --- -- --- --- -- --- --- -------,

t

¥Liii

XLIRI$_______________________________________________ J

X·llllllSS

BASIC BLOCK DIAGRAM

BIT ADDRESS
Ao Ai A2 Aa A4 A5

r---------------DATA INPUT- -- - - - -,

1

I

bvGG

POWER SUPPLIES {?

Voo

MEMO:: CELLSDECODER

OGND

I

INPUT /OUTPUT
CONTROL
CIRCUITRY

I

I

I

I

I

L __ -- - - - - - - - - - - - - -- -.- - - - -CHIP SELECT

7-32- - - - - -- - - -DATA OUTPUT- -J

WRITE ENABLE
INITIATE
READ ENABLE

3700
MOS MONOLITHIC 4 CHANNEL SWITCHMOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3700 is a four-channel multiplex switch with all channel blanking. It isa monolithic integrated circuit utilizing Planar* II, P-Channel enhancement mode MOS technology.
Control logic has been included on the chip to make the 3700 NPN bipolar compatible. The HLLDTµL
9112 High Level Hex Inverter can be used to directly interface the 3700 with CCSL logic levels. This
device is intended for use in A/D Converters, Multiplexing, Analog or Digital Data Transmission Systems, and other airborne or ground instrumentation signal routing applications.

PHYSICAL DIMENSIONSFEATURES:• BIPOLAR COMPATIBLE INPUT LOGIC LEVELS• HIGH ON/Off RATIO• ALL CHANNEL BLANKING CONTROL• PLANAR II STABILITY• INPUT GATE PROTECTION• LOW LEAKAGE CURRENT•ZERO OFFSET VOLTAGE

TOP VIEW=4 ---c===::::i~~~:::(=·=·
l--:~~---1

ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2)
Storage Temperature
Operating Temperature

A3J370011X
A3J370019X

Positive Voltage on Any Pin
Negative Voltage on Digital andAnalog Input pins
Analog Output pins
Negative Voltage on V00 and VGG pins
A3J3700112/192
A3J3700113/193
Total Power Dissipation in package (TA = 25°C)-65°C to +150°C-55°Cto +125°C
0°Cto +70°C+0.3V

PIN CONFIGURATION IN
14 PIN CERPAK II-30V

Vss====::;i

-50V
-35V
200 mW

ORDERING INFORMATION - The 3700 is available for use in two signal ranges. (See electrical characteristics for supply voltage requirements.)+5.0 to -5.0 volts signal applications, Order A3J3700112/192
0 to +5.0 volts signal applications, Order A3J3700113/193

LOGIC DIAGRAM

14r.===oRAIN

r.---'"---..LL--,

G1

51

G2

S2

G3

S3

G4

S4

VGG -~"L--...--~.--.....-~

Yoo===='-'

NC

l!::::::==:::iGcs.-------DATA INPUTS-------,

DRAIN

0

(OUTPUT)OVGG} POWER

0 Yoo

SUPPLIESOVss

ALL CHANNEL0BLANKING (Geel'-------LOGIC INPUTS-------'NOTES:*Planar is a patented Fairchild process.

(1) These ratings are limiting values above which the serviceability of any individual semiconductor device may be impaired.
(2) Voltage ratings are all referenced to pin 1 (V55).

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-33

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED CIRCUIT 3700
TYPICAL CHARACTERISTICS
ON RESISTANCE VERSUSDATA INPUT VOLTAGE(3700 113 ONLY)111111I
500 ~POINT t---ON RESISTANCE VERSUSDATA INPUT VOLTAGE(3700 112 ONLY)

i!fto.A~~0t--+--+--+--t- 21v±=..i·:~

500
t""'1fST POINT f---j-;--+-1y~~t-'
1~~ i 500~~..l.
[\,._

""

1.0

2.0

*
100

3.0

4.0

5.0

6.0

,--,lESTPOINT

lOO•A-~*

I-=..+SY-=..+SV~ON RESISTANCE VERSUSDATA INPUT VOLTAGE(3700 192 ONLY)111111 -~~~~.----..----.,----,,..--,--.

UIOO

1&~

ON RESISTANCE VERSUSDATA INPUT VOLTAGE(3700 193 ONLY)~-TEST POINT-,*\lOOoA -t--1-=..+BY ·ii! 200-i!i~I}
I "'i-.._
1 ---~$;;;t==J::::j:=l
100 l=l=t::::t

::i=

~

7.o

~~~~~~~~t---<t---<~-5.0

DATA INPUT VOLTAGE - VOLTS

·3.0

-1.0

0 1.0

3.0

2.0

4.0

6.0

8.0

10

-3.0

-1.0

~

~
......i~ 150 r-i-+-t--~f-+H-+1-1-:±--i"":+-l}-i--+-

125

-'1(

~

~

'PCINT~~ ~>--l-->--t---<1--1-->-->--t-i--t

':'

;

3.0

DATA INPUT LEAKAGE
CURRENT VERSUSAMBIENT TEMPERATURE(3700 112/113)

111111 ,.-V-,Ol!Jr-T·--lr-5V-,--,--,--,-TEST-,-P0-,1Nr-T-1-rt-~~175 t--+--+--+--+--+--+-+-+-+--i

1.0

DATA INPUT VOLTAGE· VOLT5OUTPUT LEAKAGE CURRENTVERSUSAMBIENT TEMPERATURE(3700 112/113)

ON RESISTANCE VERSUSAMBIENT TEMPERATURE-5.0

DATA INPUT VOLT~GE • VOLT5DATA INPUT VOLTAGE· VOUSrv.-i -i-r~

lo i--r--r--r---ir--r--1-IL_,,..L'-1--11--t~

pTEST POINT-+V-7"1--l--ll--1--f--l~ 1.0

1001--1--+--+--+--+--+-+-+-+--i17

L15~~~~~~~~~..__.

25

45

8S

115

125

85

TA· AMBIENT TEMPERATURE· °C

TA· AMBIENT TEMPERATURE - ·c

115

125

TA -AMBIENT TEMPERATURE - ·c

I Vss

Vss

OUTPUT
LOGIC IN

3700

DATA IN

Voltage levels between semiconductor electrodes are normally referenced to one of the electrodes. In MOS, this electrode is the Substrate (body). The
voltages can be translated to an equivalent level and referenced to another electrode. In order to measure the ON resistance of the data channel accurately, the data inp!Jt is at ground potential and all other terminals are c~anged correspondingly to test worst case conditions.
The following sets of bias conditions are equivalent
Condition 1

Condition 2

Condition 3+5.0V

Yoo= VGG

+s.ov
-21 v

-3'.l:lV
OV
-29V

+3.0V
-26V

Logic in
1 Level0 Level

+7.0V
+l.5V

-1.0V
-6.5V

+2.0V
-3.5V

Data inYss

The logic input levels are

V55 - 30 V< "O" level < V55 - 7.5 V to turn a data channel off
V55 - 1.5 V< "l" level < V55
to turn a data channel on.

7-34

ov

5.0

FAIRCHILD MOS INTEGRATED CIRCUIT 3700

ELECTRICAL CHARACTERISTICS
FOR 3700112/192: -5.0 v <Your< +5.0 V, TA= 25°C, Voo = VGG = -35 v ± 10%.
V55 = +8.0 V ± 10% unless otherwise specified.
FOR 3700113/193: 0 v::::; Your ::::; +5.0 V, TA= 25°C, Voo = VGG = -21 v ± 10%,
V55 = +8.0 V ± 10% unless otherwise specified.
SYMBOLCHARACTERISTICS

RoNChannel "ON" Resistance
A3J3700112
A3J3700113
A3J3700192
A3J37!J0193~13100112 @ +125°c
A3J3700113 @ +125°C
Channel "OFF" Resistance
A3J3700112/113 @ +125°C
Output Leakage Current
A3J3700112/113
A3J3700192/193
A3J31001121113 @ +125°c
Data Input Leakage Current
A3Js1001121113 @ +125°c
logic Gate Input "l" Level
Logic Gate Input "O" Level
Channel Switching Time (see Fig. 1)
Output Capacitance
Data Input Capacitance
Lggic Input Capacitance
Chan11~! Blanking Input Capacitance

ROFF

ILO

lu
VIH
VIL

t,
cdb
C;,
C;g
cit

MIN.

TYP.

UNITS

270
400
400
600
600
650
650

n
n
n
n
n
n
n
Gn
M!J

Your= Vss
Your= -5.0V
Your= OV·vOUr = -5.0 V
Your= OV
Your= -5.0V
Your= OV
Vss • Vour = 15V
Vss · Vour = 15V

lour= -100 µA
lour= -100 µA
lour= -100 µA
lour= -100 µA
lour= -100 µA
lour= -100 µA
lour= -100 µA
VG= Gnd
VG= Gnd

2.0
10
700

nA
nA
nA
nA
nA

Vss - Your= +15 V
Vss - Your= +15 V
Vss - Your= +15 V
V55 - VIN = 15 v
V55 - V1N = 15 V

VG= Gnd
VG= Gnd
VG= Gnd
VG= Gnd
VG= GndV55 • Vour = ov
Vss - VIN =OV
Vss - VG =OV
Vss - VG =OV= 1.0 MHz
f=l.OMHzf = 1.0 MHz
f = 1.0 MHz

1.5
2.1

1.5
200
Vss
V55 - 30

Vss - 1.5
V55 - 7.5

TEST CONDITIONS

MAX.

1.0
25
9.0
3.5
10

v
v
µS

pf
pF
pF
pf

f

,,~,,

FIG. 1
SWITCHING TIME TEST CIRCUITlOpF
INPUT AND OUTPUT WAVEFORMS

vouT

LOGIC{::: _ _ _ _ _ _ ,....__ _ __INPUTSYss - - - - - - i . . . - - - - GND------...1

OUTPUT

7-35

CH l
CH 2

FAIRCHILD MOS INTEGRATED CIRCUIT 3700

SCHEMATIC DIAGRAM..---------DATA INPUTS--------

U

ll

W

11

r- - - - - - - - - - - - - - - - - - -- - - - - - - - - -- - - - - - - - - - - - - I

OUTPUT

14

I(DRAIN)~-----1--------'-----------1-------1-....n &VGG~-----'--+------"-1-------~-1----~--'---n 7 Yoo

l_ ___f_ _L-_-_- -1_1-_~_-_ _4-_-_--4_-_-_-_"'-_--+_-_-_+___....._..._-_

2

3-l_l-_~_-_-1_

1-----4_-_-_-_+-_•_-_J-o

4i; ;:l~ NEL

5~-------LOGIC I N P U T S - - - - - - - - - 'TYPICAL CIRCUIT CONFIGURATION
Typical circuit configuration showing the 3700 driven by bipolar Diode-Transistor Logic
such as the Fairchild HLLDTµL 9112.

+l.OV

v~._,.

_________

Vss......;;;-=======;i

LOGIC INPUTS

OUT

•
3700

Yoo

9112

Voo

7-36

J~·

INPUT

3701
MOS MONOLITHIC 6-CHANNEL SWITCHMOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3701 is a P-channel enhancement mode Monolithic MOS six-channel, single
output switch. This devi~e can be used as a basic switching element for airborne or ground instrumentation,
telemetry or other signal routing applications.

PHYSICAL DIMENSIONSFEATURES• GATE PROTECTION• ZERO OFFSET VOLTAGE• LOW LEAKAGE CURRENT• GUARANTEED OPERATIONS OVER -55°C TO +125°C• PLANAR0 II STABILITY

ABSOLUTE MAXIMUM RATINGS (Note 1)
Storage Temperature
5 A3J370111X
Operating Temperature
I A3J370119X
Power Dissipation at +25°C
Positive Voltage on any pin (V800 y = 0)
Negative Gate Voltage (VBODY = 0)
Negative Source or Drain Voltage (V800 y = 0)-65°c to + 150°c-55°c to +i25°c
0°c to +10°c
200mW+0.3 Volt-35Volts-30Volts

ORDER PART NO. A3J370111X/19X

PIN CONFIGURATION IN
14 PIN CERPAK II
14
DRAIN
G1

S1

GJ

S2

G4

S3

G5

S4

G6

S5

BODY

s6
SOURCEELECTRICAL CHARACTERISTICS (V800 y = 0 Volt, TA = 25°C unless otherwise specified)
SYMBOLCHARACTERISTIC

RoN

Channel "ON" Resistance
A3J370111X
A3J370111x (125°C)
A3J370119X
Channel "OFF" Resistance
A3J370111X
A3J37omx (125°C)
A3J370119X
Gate Threshold Voltage
Input Leakage.A3J370111X
A3J310111x (125°C)
A3J370119X

MIN.

10
100

4.0

TYP.

MAX.

UNITS

210
310
300

375
550
500

n
n
n

Vs= OV, VG= -30V, 10 = -lOOµA
Vs= OV, VG= -30V, 10 = -lOOµA
Vs= OV, VG= -30V, 10 = -lOOµA

-5.5

. Gn
Mn
Gn
Volts

V0 = -20 V, VG = 0, Vs = 0 V
V0 = -20 V, VG = 0, Vs = 0 V
V0 = -20 V, VG = 0, Vs = 0 V
Vs= 0 V, VG = V0 , 10 = -10 µA

1.0
150
1.0

nA
nA
nA

Vs= -20V, V0 = OV, VG= OV
Vs= -20V, V0 = OV, VG= OV
Vs= -20V, V0 = OV, VG= OV

200
250
200

TEST CONDITIONS*Planar is a patented Fairchild process.
NOTE:(1) Theseratings are limiting values above which the serviceability of any individual semiconductor device may be impaired.

F.AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-37

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED CIRCUIT 3701
ELECTRICAL CHARACTERISTICS (V 800 y = 0 Volt, TA= 25°C unless otherwise specified)
SYMBOLCHARACTERISTIC

loL

Output Leakage
A3J370111X
A3J370111X (125°C)
A3J370119X
Gate Leakage
Input Capacitance
Input Capacitance
Output Capacitance
Output Capacitance
Gate Capacitance
Gate-Source or Gate-Drain Capacitance

IGL
Cs
Cs
Co
Co
CG
CGs or CGo

MIN.

TYP.

MAX.

UNITS

2.0
200
5.0
1.0

nA
nA
nA
nA
pF
pF
pF
pf
pF
pF

4.0
3.0
13
7.0
4.0
1.0

V0 = -20 V, Vs =VG = 0 V
V0 = -20V, Vs= VG= OV
V0 = -20 V, Vs= VG= 0 V
VG= -20 V, V0 =Vs= 0 V
Vs = 0 V, V0 = 0 V, VG = 0 V
Vs= -lOV, V0 = OV, VG= OV
Vs=OV, V0 =0V, VG=OV
Vs= OV, V0 = -lOV, VG= OV
Vs=OV, V0 =0V, VG=OV
Vs=OV, V0 =0V, VG=OV

A3J370111X

TYPICAL CHANNEL ON
RESISTANCE VERSUS GATE TO
BODY VOLTAGE WITH BODY TO
SOURCE VOLTAGE AS PARAMETERTEST CONDITIONS

A3J370119X

TYPICAL CHANNEL ON
RESISTANCE VERSUS GATE TO
BODY VOLTAGE WITH BODY TO
SOURCE VOLTAGE AS PARAMETERTYPICAL CHANNEL ON
RESISTANCE VERSUS AMBIENTTEMPERATURE WITH BODY TO
SOURCE VOLTAGE AS PARAMETERTYPICAL CHANNEL ON
RESISTANCE VERSUS AMBIENTTEMPERATURE WITH BODY TO
SOURCE VOLTAGE AS PARAMETER

1500 ,...-.,..--,..-~-,...~-.--....--~

VGB

1000 .---...,------.---~! ·30Vv85 • ov

c: 1250 1--+--+--t---+---+-+--+---i"'' 1500 f------l--+--1---+----t----i~ 1600 1--+--+--+--\+--t-+----t---l

!ii

~

~

u

~
~

~1200

1000 f------\--t----\--+-+----t----i~~ 800 ,__.._...-+-_..,_-+-_..,_-I--+--<

o.___.....__ _.__ _
-10

-20

·30

-40

-60

·30

Vee - GATE TO BODY VOLTAGE - VOLTS

0

30

60

90

120

150

180

-10

0

-20

,___~

-30

o~-~---'---J..--~

-40

·60

VGB - GATE TO BODY VOLTAGE - VOLTS

TA - AMBIENT TEMPERATURE - "CSCHEMATIC DIAGRAM

BODY

r-------- - - - --,I DRAIN.-----+----+---+----+---1-------0
I
I

S2 a--.--+----.

S3o-t--+----+----.
S4e>--1--+----+----+-----.
S5<>-----+----+---+---+--~

S6o-.--+----+----+---+---t---~

L

I
_J

7-38

-20
20
60
TA - AMBIENTTEMPERATURE - "C

100

3705
MOS MONOLITHIC 8 CHANNEL MULTIPLEX SWITCHMOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3705 is an eight-channel multiplex switch with output enable control andone-out-of-eight decoder included on the chip. It is a monolithic integrated circuit utilizing Planar* II, Pchannel enhancement Mode MOS technology. The logic input lines of the 3705 are NPN bipolar compatible
and can be used directly with CCSL 5.0 volt logic levels with no level-shifting interface required. This device
is intended for use in A/D converters, multiplexing in analog or digital data transmission systems, and otherairborne or ground instrumentation signal routing applications.
FEATURES• CCSL COMPATIBLE INPUT LOGIC LEVELS• ONE-OUT-OF-EIGHT DECODER ON THE CHIP
• HIGH ON/OFF RATIO• OUTPUT ENABLE CONTROL• PLANAR II STABILITY• INPUT GATE PROTECTION• LOW LEAKAGE CURRENT• ZERO OFFSET VOLTAGE

PHYSICAL DIMENSIONS

16 Lead Dual In-Line

r

.3151
.300

.~·
1

Oil
009

.171

.141

~JJ~-1l_.---

ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2)
Storage Temperature
Operating Temperature
Positive Voltage on any pin
Negative Voltage on digital
and analog input pins
and analog output pins
Negative Voltage on V00 pin
Total power dissipation in package (TA = 25°C)-65°C to +150°C-55°C to +85°C
+0.3V

105
.095

I

015-1 If--

MIN

L2s5...I
279

-35V
-35V
-35V
200mW

ORDERING INFORMATION - The 3705 is available for use in two signal ranges
PIN CONFIGURATION-5.0 to +5.0 volts signal applications, Order A6J3705142
0 to +5.0 volts signal applications, Order A6J3705143
SYMBOLIC DIAGRAM(MIL STD 806B)
DATA INPUT

TRUTH TABLELOGIC INPUTSCHANNEL NO'S

LLLLLLLL
ONE·OUT-DF·EIGHT DECODER

0 DATA OUTPUT

j ·vssYoo

20 2' 22OUTPUT ENABLE
LOSO: INPUT(16 lead DIP)

•Both Vss lines are internallyconnected; either one orboth may be used.

20

21

22

L
H
L
H
L
H

L
L
H
H

L

H

L
H
H

L
L
H
H
H
H

x

x

x

OE
H
H
H
H
H
H
H
H

22

OE

CHANNEL

•oN'

s,
s,
s,
. s,
s,
s,
s,
s,
OFF

NOTES:

Vss

21

OUT

20

Vss

Voo

Sa

Sl

S7

S2

S5

S3

S5

S4

TOP VIEW*Planar is a patented Fairchild process.

(1) These ratings are limiting values above which the serviceability of the device may be impaired.
(2) Voltage ratings are all referenced to pins 2 and 4 (Vss).

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-39

A DIVISION OF FAIRCHILD CAMERA ANO INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED CIRCUIT 3705
ELECTRICAL CHARACTERISTICS
for3705142: -5.0 V <VouT <+5.0 V, TA= 25°C, -20 V<V00 <-24 V,
5.0 V<V55 <7.0 V unless otherwise specified
For3705143: 0 V <VouT<+5.0 V, TA= 25°C, -20 V<V00 <-24 V,
5.0 V<V55 <7.0 V unless otherwise specified
SYMBOLCHARACTERISTICS

RoN

Data Channel "ON" Resistance
142
143
Data Channel "OFF" Resistance
Output Leakage Current
Output Leakage Current
Data Input Leakage Current
142
143
Logic Input Leakage Current
Logic Gate Input "Low" Level
Logic Gate Input "High" Level
Channel Switching Time (See Fig. 1)
Output Capacitance
Data Input Capacitance
Logic Input CapacitancePower Dissipation

Ro FF
(LO

IL0(85°C)
(LOI

lu
*VIL
*V1H
ts
cdb

C;,
C;g
Po
0

MIN.

TYP.

MAX.

UNITS

TEST CONDITIONS

250
190

400
350

n
n
Gn
nA
nA

VouT= -5.0V, louT = -lOOµA
VouT = 0 V, louT = -100 µA
V55-VouT = 15 v
V55-VouT = 15 v
V55-VouT = 15 v

nA
nA
µA

V55 -V 1.N = 15 V
V55 -V 1N = 10 V
Yss-VL0G1c-1N = 15 V

1.5
10
500

Yoo
Vss -1.5
1.0
40
7.5
5.5
130

3.0
2.0
1.0
+0.2
Vss

v
v

175

µS
pF
pF
pF
mW

V55 -V0 ur = 0 V, f = 1.0 MHz
V55 -V1N = 0 V, f = 1.0 MHz
Vss-VL0G1c-1N = 0 V, f = 1.0 MHz
V00 = -31 V, V55 = OVWhen driven by CCSL elements, avoid excessive D.C. loading of CCSL elements to insure 3705 logic levels under maximum fan·out conditions.

SCHEMATIC DIAGRAM..----ILOGIC INPUT-----,
22
21
20
OE

CHANNEL #

Sa

S7

/S&

S5

~---------S4
OATA INPUT---------~

FAIRCHILD MOS. INTEGRATED CIRCUIT 3705
TYPICAL DEVICE CHARACTERISTICS

ON RESISTANCE VERSUSDATA INPUT VOLTAGE(3705 142 ONLY)

ON RESISTANCE VERSUSDATA INPUT VOLTAGE(3705 143 ONLY)

ON RESISTANCE VERSUSAMBIENT TEMPERATURE(3705 142 ONLY)

':'

"'

·~ 300 t---+---+-

l;l 300 1---+--+-

iii

1;;

~

~

1!i 200 l---+--+-+---1-~l---+---io~~~-~~~~~~

1.0

5.0

3.0

1.0

7.0

2.0

3.0

4,0

5.0

6.0

7.0

-55

-35

DATA INPUT VOLTAGE - VOLTSDATA INPUT VOLTAGE - YOLTS

-15

5.0

25

45

65

TA - AMBIENTTEMPERATURE - °C

ON RESISTANCE VERSUSAMBIENT TEMPERATURE(3705 143 ONLY)OUTPUT LEAKAGE CURRENTVERSUS
AM.BIENT TEMPERATURE
500

Vl!..UT • ·15V

t-+-1--+-+-+--+-+-TEST P01Nfzl=

O!---'---'--..____.___.__..___,

.-55

65

-35

-15

5.0

25

45

_._...._..L-J__.__.__..__..........._.___.

1.0 ..........
25

85

35

TA - AMBIENT TEMPERATURE- °C

45

35

65

TS

85

TA - AMBIENT TEMPERATURE- °C

FIG. 1
SWITCHING TIME TEST CIRCUIT
S1t-----<:> VINls2
t---t---<:> VIN2

_JVss
20

GND

Yss

21

Vss

22

Yss

OE

I.--- - - V s s
INPUT

GND - - - - - ! i
I
II

V1N2--------f---- -~-=~I.
I
90%
I
I

VINl

----..1

7-41

I

I
I
I
I
I
I
i--ts--i
I

lOMO

I
I

10pf

I

OUTPUT85

FAIRCHILD MOS INTEGRATED CIRCUIT 3705

I Vss
VLOGIC-IN
DATA IN
3705

B

DATA OUT

Tvaa

Voltage levels between semiconductor electrodes are normally referenced to one of the electrodes. In MOS, this electrode is the substrate (body or V55 ). The
voltages can be translated to an equivalent level and referenced to another electrode. In order to measure the 'ON' resistance of the data channel accurately,
the data output is at ground potential and all other terminals are changed correspondingly to test worst case conditions.
The following sets of bias conditions are equivalent:

DATA IN
VssYoo
LOGIC IN
"Low" Level"High" Level

CONDITION 1

CONDITION 2

+5.0V
+7.0V
-20V

OV
+2.0V
-25V

+o.2v

-4.SV
+0.5V

+5.5V

TYPICAL CONTROL CIRCUIT

+5.0V

;

ANY CCSL INTEGRATED CIRCUIT

7-42

,37~010-BIT D/A CO~VERTERMOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3750 is ,a monolithic MOS/LSI ten bit digital to analog converter using p.
channel enhancement mode MOS technology. The d'igital word can be entered serially or in parallel. If
desired, the word is available in serial. f,orm through an output buffer in either an 8 or 10 bit format. The
converter output data is available thru
single pole double throw (SPOT) MOS switches. The holding register
retains the state of the previous digital input word and drives the output switches. Transfer gates are used
to isolate the holding register from the input register while new data is being entered. The 'on' resistance ofthe MOS switches is weighted to provide the necessary accuracy and stability for a ten bit conversion.

PHYSICAL DrMENSION
36 PINDUAL IN·LINE PACKAGE

fo

FEATURES• 8 AND 10 BIT DATA LENGTHS• SERIAL AND PARALLEL. OPERATION• 250 kHz SERIAL BIT RATE
• 500 kHz PARALLEL WORD RATE
• 250 n TYPICAL 'ON' RESISTANCE OF TWO MSB's• 500 n TYPICAL 'ON' RESISTANCE OF REMAINING EIGHT BITS
• 110 mW POWER DiSSIPATION• ZERO AND FULL SCALE CALIBRATION LOGl.C

.124
.115

.009

.078

.072

.110
.090

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Input Voltages
Power Supply
Storage Temperature
Operation Temperature-30 to +0.3 Volts-29 Volts-ss 0 c to +1so0 c-ss 0 c to +ss 0 c

L
I

.019
.017

APPLICATIONSDIA Converters
Telemetry
Analog data. plotters
Industrial process control
Servo systems

ORDER PART NO. A6H375014X

PIN CONFIGURATIONBLOCK DIAGRAM.

,---

I
I

----1

REF. 2I
I

REF. 1

I

....

.011

.190
.140

I
.I

I

I

TRANSFtRI

35

TJIANSFERO

l3

S£RIALINPUT

3Z

9 lll'PUT(MSBJ

31

81NPUTI

TRANS. 0 I
TRANS. 1 I

SET
RESET

I

i

36

I
SERIAL IN

I ~~~~;I PARALLELI ENABLE
I
Msa

27

41NPtiT23

OllfPUT(LSB)f

SHlfl REGISTERS.

i
I

PARALLEL ~PUTS
isa
I
L---~--~~---~------~-~OOUTPUT(LSB)

POWERSUPPLY(V6 ,.J

12

PARAU.ELENABLE

21

CLOCK INPUT

20

MOCOllMECTIOfl

18

CIRCWTRY ON CHiP

F.AIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7.43

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED .CIRCUIT 3750
ELECTRICAL CHARACTERISTICS VGG = -27 ±2.0 Volts, RL = 10 Mn, CL= 10 pf (unless otherwise specified)
SYMBOLCHARACTERISTICS

MIN.

TYP.

MAX.

UNITS

CONDITIONS

0
-9.0

-2.0
-3Q

Volts
Volts

0
-10

-1.0
-30

Volts
Volts

-9.0
1.0

-30
10

Volts
µs

DC
DC

250
500

kHz
kHz

250
250
550

500
500
1000

ohms
ohms
ohms

VREF = -5.0V
VGG = -27V

70
70
120
0.6
0.2
0.5
0.5
0.55
0.35
0.4
0.3
7.0
4.5
120
0.3
0.03

150
150
250

ohms
ohms
ohms
µs
µs
µs
µs
µs
µs
µs
µs

VREF2 = -5.0V
VREF1 = OV

Logic Inputs

"O"

ron

"1"
Logic Outputs
"O"
"l"
Clock
Amplitude
Width
Frequency
SerialParallel
MOS Switches

Aron

"8"
"7" thru "O"
Switch Mismatch

fmax

"9"

150
150
325

"9"
"8"
"7" thru "O"
Serial Delay,'·Irise and fall
times

tf
tdr
tr

Parallel oelay,'·1

rise and fall
times

tf
tdr
tr
C;n

Data and Control Input CapacitancePower Supply Current Drain
Power Dissipation
Temperature Coefficient of Switches
Temperature Coefficient Tracking
Input Leakage Current
Data Delay Time

Imax
!!max

ILX
tdd

pf
7.0
190

mA
mW

VGG= -27V
VGG = -27V

%l°C
%!°C
5.0

µA

250

Vin= -20V

ns

TIMING DIAGRAMTYPICAL ELECTRICAL CHARACTERISTICSOUTPUT DELAY, RISE AND FALL TIMES---.u

IWcp I: Wcp:ON RESISTANCE VERSUS
POWER SUPPLY VOLTAGE (Yes)OUTPUT VOLTAGE (REF. 2)

Clock

ON RESISTANCE VERSUSOUTPUT VOLTAGE (REF. 2)

Wr-'---••Time
I

I

81159 AND 8

Data Output

MOt--1---<,__.-+--+-+---+---+--+-~a~ ~ t--1---i--+--+--+-+---+---+--vn-L'-i~

VGG" ·27V

..J'1

i ~
! ;rTime: : -----....,,-_,! I~,

1~ 600 l--+--+--1---'

ldf 1 If i

I ldr I tr I

iii

DATA BIT TIMINGc,o

C L O C K - - - - - - . u r - - - - - - - - - - · Time~ «Xl ~~H--t-1---l--l--h.~qw.---------•II,

O'--J-..J'-'--L-'---'----'---'--'-~

0

z.o

4.0

6.0

8.0

REFERENCE 2 VOLTAGE· VOLTS

10o~,___,'-'__.._,__.____.__.._,_._~

0

z.o

4.0

6.0

8.0

REFERENCE Z VOLTAGE· VOLTS

10

Data Input

I

I

Itddi

TIMING DIAGRAMS

7-44

Time

I I._________· F_A_IR_C_H_IL_D_M_O_S_l_NT_E_G_R_AT_E_D_·_Cl_R_C_Ul_T_3_7_5_0_ _ _ _ _ _ _..._.
LOGIC DIAGRAMOUTPUTS

I

I

REF 1
BIT 8

BIT 9

BIT7

BIT 6

BIT 5
TYPICAL BASIC
LOGIC DIAGRAM
OF ONE BIT
SEGMENTII
I

RESET HRSET HR

BIT4

I
I
I
I
I
I
I

TRANSF. 0
TRANSF. 1-t>-- I
BIT 2 ONLY I-t>-- I

BIT 2

BIT 1

BIT D

I
I
I
I
I
I
I
I

8 BIT OUTPUT

I

10 BIT OUTPUTI

BIT 0 ONLY I.ISERIAL IN

REF 2II BIT 3
I
I

I

I
I

I

CLOCK
RESET SR

I

I
I
I
I
I

PE

PARALLEL INMSBSERIAL OPERATIONPARALLEL OPERATION
100k Q

IOOk Q;---£J-

0 TO +IOV

i 33.3kQi~
I

-

:

-

I
I

50kQ

0 TO ·5.0V
50kQ

50kQ

99.5k099.5kQ

EXTERNAL CONTROLSERIAL DATA INPUT

REF. 'I'
SETRESET
TRANSFER 'O'
TRANSFER '1'
RESET SRSERIAL INPUT

65
43
PARALLEL OUTPUT

PARALLEL INPUT
4653

REF. '2''8' OUT'10' OUT
VGG
GND.
CLOCK
PARA. ENABLE

100kQ

DY

OV

500

OV
FULL SCALE CALIB.
ZERO SCALE CALIB.

99.5kQ

IOOkO

ov

-5.0V

FULL SCALE CALIB.
ZERO SCALE CALIB.
EXTERNAL CONTROL
EXTERNAL
CLOCK

REF. '1'SET
RESET
TRANSFER 'O'
TRANSFER '1'
RESEJ SRSERIAL INPUT

54
3
6
PARALLEL OUTPUT

Vss

6

PARALLEL INPUT
4
5.
3
PARALLEL DATA

7-45

REF. '2''8' OUT'ID' OUT
GND.
CLOCK
PARA. ENABLE

-5.DV

-27V
EXTERNAL
CLOCK
27V

r----

>
:::CJ

C')

;J~
Ji
~i
~ ~ t---+--i!l r:72 i---t¥l r:72 1----h r:72

lJ~
T~:~~L -vi µ';:.

r~ L.*1J~!JrL:~1 L,*'1

ti L.*..

r1 L;~..

!-------+-,~, L;~'

u~

!JL:

:c
re

~~

[JIL:

~ IX 1-----hF ~ --nn ~ t---t-:iF ~ >---tv G1D f - 1

r1 L,~..

t1 L,*~ I t1 L,*1

r1 L,*'l:s::~1 L,~10(/)'-t-----+--+~---+-+-++---+--+-+-t-----!1--+--1+----+-+++----+-f-+-+----+-+4-+-~-++l+---1--+->-+----+-+-+-+- 41's~~~~~~TER

~~

~lf

~~

~~

T

T

T

'---+--~l____,_

~~

~~

~~

~~

~~

~

z

-I

___,T'---+--~I----+---'-+----+---+--_._-+--_._---++-----+----<.__~l.__1-1-1-~s

fTI
C)

:::CJ

~
c

fTI

C')

:::CJ
C')

IT
tiJ

EP.-----------1-lOBIT~ ,_J
OUTPUT.----------8BIT'f
CLOCK --+-----!-+------!---+--4--~' - - - - - - - - - + - 4>'c:-I.----------~GND

00-

(/J

~

3751
12-BIT A/D CONVERTERMOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3751 is a twelve bit analog to digital converter using P channel enhancementmode MOS/LSI technology. The conversion is accomplished by the successive approximation technique. The
word length is variable for eight, nine, ten or twelve bits by applying ~ DC potential to each of two control
pins. The 3751 provides all the A/D system control functions such as: master timing, automatic start andrecycle, and RZ or NRZ format control. By choosing the appropriate ladder network, the output will be ineither a binary or binary coded decimal digital format.
FEATURES• 8, 9, 10, OR 12 BIT WORD LENGTH• RZ OR NRZ DIGITAL FORMAT• COMPLETE LOGIC AND SYSTEM TIMING CIRCUITS INCLUDED ON THE CHIP
• BCD OVERVOLTAGE FLAG
• 200 n TYPICAL "ON" RESISTANCE FOR THE TWO MSB• 500 ffTYPICAL "ON" RESISTANCE FOR THE REMAINING TEN SWITCHES• 150 mW POWER DISSIPATION• AUTOMATIC RESTART CIRCUITSPHYSICAL DIMENSIONS
36 PINDUAL IN~LINE _PACKAGE-'----+-+~-~~
.124

.011

.115

.009

.190
.140

-J

.078
IJ72

.no

IJ90

L
ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Input Voltages
Power Supply
Storage Teinperature
Operation Temperature

'

.019

-30 to +0.3 Volts-30 Volts-55°C to +150°C-55°C to +85°C.017

ORDER PART NO. A6H375114X

APPLICATIONS
A/D Converters
Three Digit DVM's
Telemetry
Industrial Control
Computer Interface
BLOCK DIAGRAMPIN CONFIGURATIONFROM COMPARATORTO UOOER NETWORKNO CONNECTION
llEFERENCE2

REF.
VOLTAGEBCD OVERYOLTAGE--+---<..

""NOCONJIECTION
POWERSllPPL'f(VsslllOUTPUT(MSB)llETURMTOZEROIOOUTI'UT

Ml CONNECTION

90UTPUTAJOOUTPUT'""""(;OMPAllATORRETURN"""

70IJTPIJT

A/0 OUTPUTBCOOYEINOlTAGE&OUTPUTACPRE$£T

DCPJIES(T

50UTPUT

Cl.OSCO LOOP CONTROLTIME OUT

CLOCK---8.9.10 OR

20UTPUT

12 BIT CONTROLSYSTEM PRESET-TIMEOUTPUTSYSTEM
SYNCHRONIZATIONIOUTI'UT

ltOCONltECTIONOOIJlPUl(lSBlNOCONllfCTIONNOCONNECTIOH".

NOCONMECTION

FAIRCHILCJ
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-47

SEMICONDUCTORA DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATION[FAIRCHILD MOS INTEGRATED CIRCUIT • 3751

ELECTRICAL CHARACTERISTICS (V6 .6 = -27 ± 2.0 Volts, RL = 10 Mf!, CL= 10 pf unless otherwise specified)
SYMBOL

ILx
tdf
tf
tdr

t,

}

0
-9.0

-2.0
-30

Volts
Volts

0
-10

-1.0
-30

Volts
Volts

-9.0
1.0
DC

-30
10
250

Volts
µs
kHz

250
250
550

500
500
1000

fl
fl
fl

70
70
120
7.0
4.5
120
0.3
0.03

150
150
250

fl
fl
fl

logic Inputs"O""1"
logic Outputs

"O"

pmax

UNITS

MIN.

"l"

CIN
Imax

MAX.

CHARACTERISTIC

Clock
Amplitude
Width
Bit Frequency
MOS Switches
"11"
"10"
"9" thru "O"
Switch Mismatch
"11"
"10"
"9" thru "O"
Data and Control Input CapacitancePower Supply Current Drain
Power Dissipation
Temperature Coefficient of Switches
Temperature Coefficient of Tracking
Input Leakage Current
Analog Switch Delay,rise and fall times(10% to 90% points)

TYP.

150
150
325

CONDITIONS

pf
mA
mW
%!°C
%/oc
µA

7.0
190

5.0

µs
µs
µs
µs

0.7
0.5
1.1
0.25

VGG=-27V
V66 =-27V}

V66 = -27V

TYPICAL ELECTRICAL CHARACTERISTICS
ON RESISTANCE VERSUS
POWER SUPPLY VOLTAGE (V&&)
OUTPUT VOLTAGE (REF. 2)

ON RESISTANCE VERSUSOUTPUT VOLTAGE (REF. 2)

811Sl!ANDJO

WOt--+--+--+--+--+--+-+-+-+---<

tJ
~

600

~

l---+--+--~~~-1--1--1---+-J~ 400 """'~+-+--+--+--+--1--6.~
~

2.0

4.0

6.0

8.0

2.0

JO

REFERHJCE 2 VOLTAGE - VOLTS

4,0
6,0
8.0
REFERENCE 2 VOLTAGE - VOLTS

TIMING DIAGRAMOUTPUT DELAY, RISE AND FALL TIMES

uP.:----•: Wcp:Clocki Wcpi--___,;uI

I

Serial Data Output

: :'

:I

~I TimeI '\...._.- - - - - - - ' - - - - ' / !

::I
I ldf I If :

I

I

I

l ldr : tr I

7-48

Time

lO

FAIRCHILD MOS INTEGRATED CIRCUIT • 3751
TEN. BIT A/D CONVERTERND. OF BITS
89

R VALUE
12.5k

m

10
50k
12
20Dk
LADDER NETWORK MFGR'SNEGADYNE CORP., ROCHESTER. N.Y.
ANGSTROM PRECISION INC., VAN NUYS, CALIF.

3751 ANALOG TD DIGITAL CONVERTER
19

20

21

22

23

24

25

26

27

VGG

SERIAL DIGITALOUTPUTIMSB FIRST)

END OF CONVERSIONOUTPUT PULSE

28

29

30

CLOCK

31

32

33

34

35

36

'--+-----------+---Ut----'

THREE DIGIT BCD A/D CONVERTER
D TD llFERINCI VDLTAGIANALOG INPUT VDLllGILADDIR NITWDRK

'

21

2R

2R

8.IR

8.IR

9R

ZR

21

2R

2R

21

Bl·PDLAR
INTIRIACI CIRCUIT. - - - - - - RErvDLTAGI

3151 ANALOG TD DIGITAL CDNVIRTER ·CLOCK

IND DI CONVIRSIDN OUTPUT PULSE

7-49

FAIRCHILD MOS INTEGRATED CiRCUIT • 3751
TYPICAL TIMING DIAGRAM~.~~~~~~.~~~~~~.~~~~~~.~~~~~~.~~~~~­~ ,~~~,~~~~~~r~~~~~,~~,~~~,~~~~~~,~~~•s~~~~~~~--J ·~~' ~~~~~~~~J ·~~' ~~~~---SR 011010---,__- - - - - - - - - - - - - - - - - , ___0 9 - - - -_-\.
___ J_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___r---------------0&--------------,___r----------05-----------------.___
O a - - - - - - - - - ,_ _07------------,____r-------------_ J_ _ _ _ _ _ __04~---------------------,___r-----

HR 011010----.L___...,J~-----------------'--~._____

Q9--------,'------------------__J,-----Q9---------,___.....- - - - - - - - - - - - - - - Q7-----------,____________J,-----Q6--------------.,.__________J,------

05-----------------,____r---------

04-------------------,__~_r------,r-------------------\__PRESET ..,__ _TIMEOUTCOMPARATOR OUTPUT - - - - , __ __ r - - - \ __A/D OUTPUT - - - -MSB= 1_ J_ __

r------_ J - - - - - , __ _ _ _ _

0

0

0

LSB= 08 BIT FORMATANALOG INPUT= -3.369 v = 10101ioo
REFERENCE VOLTAGE= -5.000 V
FIGURE 3

DESCRIPTION OF PIN FUNCTIONPIN NO.
24, 21

A, B: These two pins are connected as shown in the truth table below to centrol the length of the digital word.

8
A 1
25

9
0

10
1

12

0
0

B 1 1 0TIME OUT: A synchronqus pulse with the clock is applied at this output at the end of each conversion. This pulse may be used to step amultiplexer or oth,\!rwise notify the system of the readiness of the A/D to start another conversion.
.

26

CLOSE.D LOOP CONTROL: A 'l' voltage level continuously applied to this input will put the A/D in an automatic mode of operation. The tirrie
output pulse is internally gated to cause a preset at the. end of each conversion and initiate a new conversion. The automatic start
circuitry pre~ets the circuit and restarts the conversion ,if a bit has been dropped in this mode of operation.

27

D.C. PRESET: A 'l' voltage level applied to this input will tause an immediate preset and the unit will stay preset until this input is returned
to a 'O' voltage level.
. .
.

28

A.C. PRESh: When. 'l' level is applied to this in~~t. the A/D is p~eset on the next clock pulse. The unit wiii continue to be preset on eachclock pulse until t~e 'l' level is removed from the inptit
·

a

31

A/D OUTPUT: The serial digital conversion is available at this pin ih a most significant bit (MSB) first format. The data output is delayedby one bit time.

36

BCD OVERVOLTAGE: this output is used when a three digit analog to binary coded decimal (BCD) conversion is being made. If the binary
equivalent of the most significant digit is greater than 9, a 'l' voltage level is applied on this output.

33

RETURN·TO·ZERO: This input modifies the digital code format from non-return-to-zero (NRZ) to return-to-zero (RZ) if used. When tied to theclock iine, the digit~l ilLtput will return to zero during each ciock pulse. The RZ duty cycle can be varied by controlling ~he length oftime that a 'l' level is applied to this input.
COMPARATOR RETURN: The comparator output should tie connected to this input. The input must be prevented from going positive withrespect to substrate (ground). The output SPOT MOS switches are successively toggled to the reference voltage. This input will cause
these switches to be conditionally reset if the ladder network output voltage is greater than the signal voltage.

30

2, 17

REFERENCES 1 & 2: Reference 1 is normally connected to ground and reference 2 to -5.o volts. However, they may each be connected
anywhere between 0 and -5.0 volts D.C. for special applications.

7-50

LOGIC BLOCK DIAGRAM

OUTPvTS~

O-y~AFl..OW

OoT

::u

0

:::c:
r-

iF

0

3!:

0

en

z

-I

fT'I

Ci)

"~

::u

>
-I

.

fT'I

, ...,,.

CLOCK

0

Q
:::0
(")

TIME

OIJTPU'fc::=i•

COMPAl\~TOI\

lt£TUlllHw.......

(J1

.....

NOTE: Polarity indicators (0) external to the solid box conform to MIL-ST0-8068 where 0 indicates the less positive state is active. Internal to the box and in the remainderof this data sheet conventional MOS polarities are used, where HI = "l" :::= -10 V and 1.0 = "O" :::= Gnd.

SCHEMATIC DIAGRAM::ct l I l l l I I l I l I......

10

0

J

I

J

0

f

J[

J

•

J

J

>
::0

(')

::c
r-

e

3:

0

en

z

-t

-..j
I

CJ'I

I\)

a
::0

~
c

l"l'I

Q
::0
(')

c
=i
•

3800
8-BIT PARALLEL ACCUMULATORMOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3800 is a LSI-MOS integrated circuit containing approximately 200 gates. It
functions as an eight bit slice of an arithmetic unit, which may be_ connected to form any word length. It iscapable of parallel addition and subtraction, and by simultaneously shifting the sum or difference right orleft, multiplication and division algorithms. A direct subtraction capability eliminates the need for the usual
carry input to the LSB during subtraction, thus allowing operands to be located anywhere in the truly variable
word length accumulator. The parallel data organization of the 3800 improves speed and greatly reduces theamount of random control logic when compared to the same function performed serially.

PHYSICAL DIMENSIONS
38°PinDual In-Line Package

i_f~

FEATURES• DIRECT SUBTRACTION USED TO PROVIDE VARIABLE WORD LENGTH CAPABILITY• STROBED OUTPUTS FOR HARD WIRE COMMON BUS SYSTEMS• DC TO 200 kHz ADD AND SHIFT RATE
• 3.0 µ.s, 8 STAGE CARRY PROPAGATION TIME
• LOW POWER-180 mW.190:rf~l:~

.140
.078

.072

APPLICATIONSBasic Accumulator Block
Index Register= .< Comparator
General Logic Control
Up-Down Counter
Divide By N Counter

•

ln
..

~.868

=u1S32.....

>.

.. ..•.
"~ri;J

ABSOLUTE MAXIMUM RATINGS
Input Voltages
VGG and V00 Supply Lines
Storage Temperature
Operating Temperature

ORDER PART NO. A611380014X <-ss•c to +85°C)
A6H380019X (0°C to 70°C)-30 Vto +0.3 V-30 Vto +0.3 V-ss 0 c to + 150°C-55°C to +85°C

BLOCK DIAGRAMPIN CONFIGURATIONOUTPUTS (llSBJ 7 I 5 4 3 2 1 D
I 18910111213

OUTPUT DRIVERS(WITH STROBE FDR
COllllON BUS SYSTEMS IOUTPUT STROH CONTROL 14

ZERO FLAG

18 SHIFT LEFT INPUT
17 SHIFT RIGHT OUTPUTSHIFT RIGHT CLOCK IISHIFT LEFT CLOCK 20
ACCUMULATE CLOCK 21

15 RESET"A"REG.

22 CARRY /BORROW INPUT

4 ~t

11\\0 1.iY~1\f.TJ:¥~Wf 3~ ----11 ........................._..........
,_~_._"R" REG. DATA LOAD 32&ND ¥66 -19 GROUND
35 -27¥3& -13¥31

V1111 -IJY

as

Ve;& .... nv

SNIFTMIHTIJIPIJT(Sllt)..

<CllOI c:AlllTl•llROWOUTl'UT

JS

fflSll ''II'' llUIJ'lll OlffM

ZIRORMl{f)12(l.OAD)"~'REllSTtlLOi\P

JI

INPUT701S8).....,,_""""'......

""""'-'GUTPUT4""""'CARRY /BORROW OUTPUT 34

'oo -

l

SHll'fl.EfTM(SlO)

5

SHIFT LEFT OUTPUTSHIFT RIGHT INPUTADD/SUBTRACT SELECT

AOD/M'fllflCl'lflllllT(MI)

10

""""'

II

OUTM I30

INPUT6It

1Mllllf5

21

'''""

.

INJVI'!

" '"'""
ZS

lllMI

24

INMO

''"''"'

OUft'UfmtOlllECOWTllOl.(S)

"
"
14

z3

(1111) llUU"ll" llRISltR

llESE'l""A"llDllSltl(RA)II

22(CIN)CAllRY/IJQllOWIM'UTSlffFfRlCllTCLOCKCSIC>

II

:ti

MC>M:CUtlUIATECUICISHIFTllGHTOUT(SllO)

11

20(St.C).HFTlEf1'Q..OCI(

stflnUFTlllPllTISl.ll'--~~~~~~-·~·......

23 RESET "R" REG.
INPUTS IMSBJ

F.AIRCHIL.CJ
SEMICONOUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-53

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED CIRCUIT 3800
ELECTRICAL CHARACTERISTICS V66 = -27 V ± 1 V, V00
SYMBOL

tcs

l,i1 &l,ii
ILX= -13 V ± l V, RL = 10 MO, CL= 10 pf (unless otherwise specified)MIN.

. CHARACTERISTICS
Logic inputs
Logic "0"Logic "1"
ClocksAmplitude
Width
Shift frequency
Shift &add frequency
Delay Times. 8 stage carry
Output delay
Input leakage current
Logic outputs
Logic"O"
Logic "l"Logic "1"Supply current drain

TYP•

MAX.

UNITS

0
-10

-2.0
-30

Volts
Volts

-10.
1.0
DC
.DC

-30
10
300
200

Volts
µs
kHz
kHz

5.0
3.0
5.0

µs
µA

3.0

1.Q

-11

..:.:.o.5.··
-12

-10

-11

0

-1.0

7.0
5.0

Yoo
VGG
Network dissipation

180

µs

Volts
. Volts
Volts
mA
mA
mW

CONDITIONS
V66 = -27V
V66 -27V=}see Figure 1
VIN= -20V

RL:::::40k0

V66 = -27 V, V00 = -13 V
V66 = -27 V, V00 = -13 V

DESCRIPTION OF PIN FUNCTIONSPIN NO.

NAMESYMBOLFUNCTION
When ASI is a logic "l", no addition or subtraction will occur when the ACC, SRC or SLC clock are pulsed.
The accumulator register will shift right or left normally however. The carry/borrow through line is not affected, allowing numbers to be shifted and compared when the subtract mode is selected.
SLO is the MSB output of the ACC and may be connected directly to the SLI input of the next eight bit
section of the accumulator. Shift and add function normally.
SRI accepts the SRO output of a higher order, 8 bit slice. Shift and add function normally.
When ASS is a logic "l", addition is performed, and when ASS is a logic "O", subtraction is performed.
The zero flag output is a logic "l" only if the accumulator register contains all zeros. This output is independent of the strobe control.
When the strobe control STR is a logic "O", all outputs represent the contents of the accumulator register.
When STR is a logic "1", all parallel outputs, 0-7, are disconnected from the power and ground lines allowing them to float. Thus several similar outputs may be hard wired together for a common buss system.
When RA = logic "1", the accumulator is reset to zero. This asynchronous signal overrides all others.
Pulsing the SRC with a logic "l" shifts the contents of the accumulator one bit position to the right. If the
add/subtract controls are enabled, the sum or difference of the accumulator register and the "R" register isshifted one bit to the right and written into the accumulator. ·SRO is the LSB end of the 8 bit accumulator and may be connected directly to the SRI of an adjacent
8 bit slice.
The SLI accepts the SLO output from a lower order, 8 blt slice:
Circuit common and substrate ground are both connected to this pin.
.
Pulsing the SLC with a logic "l" shifts the contents of the accumulator one bit position to the left. If the
add/subtract controls are enabled, the sum or differe'1ce of the accumulator and the "R" register is shifted
one bit to the right and written into the accumulator.
Pulsing the 'AC input adds the contents of the accumulator and the "R" register if ASS = logic "l". The "R"register .is subtracted from the accumulator if ASS= "O". If ASI"l", no action occurs.
A logic "1" on CBI enters a carry or borrow into the LSB position of the add/subtract logic.

1

Add/subtract
inhibitASI

2

Shift left
outputShift right input
Add/Subtract selectZero flag

SLO

3
4
5
6-13
14
15
16

17
18
19
20

Outputs
Output strobe
control
Reset Accum. register
Shift rightclock
Shift right
outputShift left input
GroundShift left
clock

SRI
ASS
F
7-0
STR
RA
SRC

SRO
SLI
GND
SLC

Accumulate· clock
Carry /borrow input

AC

23
24·31
32

Reset "R" register
Inputs"R" registerdata load

RR
0-7
RL

33

MSB"R"
register output
Carry /borrow
outputVee power
supplyV00 power
supply

MSB

21
22

34
35
36

CBI

=

Vee

Placing a logic "l" on RR asynchronously resets the "R" register.
Inputs are entered into the "R" register asynchronously when RL is activated.
When RL is a logic "l", data presented at the inputs are loaded into the. "R" register. RL may be permanently a logic "l'', effectively bypassing the R register during normal operation. Note that RR overrides thedata inputs regardless of the load command.
It shows the MSB of the "R" register. When the "R" register is used to temporarily hold operands duringmultiply, divide, etc., the MSB output indicates the sign of the stored operand.
The CBO is the asynchronous carry or borrow output from the MSB of the add/subtract logic. It is not affected by the ASI control.
-27 V supply.

Yoo-13 V supply.

CBO

7-54

FAIRCHILD MOS INTEGRATED CIRCUIT 3800
CARRY/BORROW 8 STAGE
PROPAGATION TIMESHIFT COMMAND TIMING DIAGRAM--Jwcpl-CLOCK PULSE OYDATA INPUT DY

SRO,SLO& PARALLEL DYDATA OUTPUTS
-lOV

TIME

-,

I

I
I
I
I

CARRY 1 BORROW INPUT OYII- - - - - -I - - - - - TIME

I
I
I
I

I

I

i:
---~-\,_-------ICARRY 1 BORROW OUTPUT DV = + L I-ri;v TIME

-lOV- --LOY

- i ldt

I

I
---i

td2

-+
I

I

I

---i___-ttcel--1,-

I

FIGURE 1
STANDARD CONNECTIONS FOR ADDITION AND SUBTRACTIONPARALLEL OUTPUTS

7------0

15--- ---BCARRY BORROWOUTPUT

CBO

--

CBI

3800
#2

AC
ASI
ASS
RA
LOAD

CBO
AC
ASI
ASS
RA
LOAD

3800
#1

ttttti tt

tttt ttt3
CLOCK-l V "--y-"'RESETINPUT ADDITION, ACC
SUBTRACTION
7- - - - - -O

15------ 8~---------C_ON~T~~l~l~IN~E~S_ _ _ _ _ _~J

PARALLEL INPUTSSIXTEEN BIT PARALLEL ADDITION (SUBTRACTION)": The addition (subtraction) operation begins by resetting the accumulator, then transferring the augend (suotrahend)
through the "R" register into the accumulator by pulsing the AC clock line. The operation is completed by loading the addend (minuend) into or through the "R" register,then adding (or subtracting if ASS= logic "0") it from the accumulator by again pulsing the AC clock. Multiple addition and subtraction or combinations of both operati~ns
may be performed by repeating the last operation. Thus a running total may be kept in the accumulator.

STANDARD CONNECTIONS FOR MULTIPLICATIONPRODUCT

1------0

15------8

ACC
REGISTER

3800

AS;I
AC
MO
LOAD REGISTER
ASS
3800

LOAD
ASS t---t---t<>O<l3--l MSB
RARAt t ttttt.,
tt ttt~---1---..-"'SRC... ..."'..."' .."' 5
5 ...
a
...
"'. "' "'"'g =
s
"'
SRC

7-- - - - - 0

MULTIPLICAND INPUT

z

:::;
:::>

c

w

= :::;

8

:::>

....
w

~

~

'7------0::

MULTIPLIER INPUT

~

;;;

"'

MULTIPLICATION: The multiplication operation, shown above, begins by clearing the ACC and MQ registers, then loading the multiplier into the MQ "R" register. If the
MSB of the MQ's "R" register is a "l", ie. the multiplier is negative, the ACC and MQ subtract lines are enabled before the multiplier is transferred into the MQ. Thus
the multiplier in the MQ is always positive. However, the multiplicand, which has been loaded into the ACC "R" register for temporary storage, will be subtracted from thepartial product in the ACC if the multiplier was negative. The multiplicand is added to or subtracted from the partial product and shifted one bit to the right each time the
LSB of the MQ register is a "l". If it is a "O", only a shift right occurs. Neither the multiplicand nor the resulting product require any further sign corrections as theanswers will automatically be in two's complement.
DIVISION: The division algorithm is similar to the multiply and is described in detail in The logic of Coll11luter Arithmetic by Flores. The most straightforward way to per·form division is to convert both the divisor and dividend to sign magnitude numbers the same way the multiplier was converted in multiplication. Then proceed through a
successive subtraction division. The resulting positive quotient must however then be corrected to two's complement rotation if the signs of the dividend and the divisor
were not the same.
NOTES: 1. Input logic levels may be selected by referring to the list of Pin Function Descriptions.
2. All unused input or control pins should be grounded.
3. All operands are in two's complement notation.
4. All diagrams are BASIC BLOCK DIAGRAMS and no electrical levels are indicated. See Logic Diagram for correct 806B notation •.

7-55

FA~RCHIL~ ·MOS INTEGRATED CIRCUIT 3800

APPLICATIONSPARALLEL OUTPUTS

15------8

1------0

3800

3800
#1

OVlRFLOWCBI#~INPUT COUNT

15------ 8
COUNT 8Y"N"INPUTSUP·DOWN COUNTER$1XT~El'I

STAGE UP·DOWN COUNTER: Operation be,ios by resetting !he registers and en,bling ASS, which determines the count' direction. Counting by one may be ac·
comPli•hed by •nabling CBI ar INPUT "0". To count by n, Slit n inlo th• "R" register.
A>R

A<R

-------1..,_

CBO___,,.___ _,CBI

ASS

GND

AC

LOAD ACC

3800

RESET ACCLOAD

COMPARE STROBELOAD Rt t t tt t~
DATA INPUT

L, =>COMPARATORCOMPARE OPERATION: To compare tw0 numbers, simply Insert the first Into a previously clear.d accumulator by pulsing AC. Enabling the subtract control will immediately
indicate whether R>A, as a borrow output will 1ppear. If th• borrow output follows a pulse on the borrow input, the numbers are equal. If neither, then R<A. The logic isshown above.

t
7

O~=~; _ _..,.__ _.. CBO· +dz-__J.....,-dz~,--,,__,

3800{\~ t!::::::::r;;;;i::= ~dJy

!ACCUMULATOR! C
SLO:A RR7654321:L

COUNT UP [•dyj
1~~-1._,- COUNT DOWN [-DY)t
INITIAL CONDITION INPUTSDDA CONNECTIONS
Thf DDA shown a~ave utilizes one 3800 for a remainder register and a second 3800 for a y accumulator counter.

7-56

:J

LOGIC BLOCK DIAGRAMPARALLEL OUTPUTS
(MSB]

7

5

&

3

2

I BIT 3
I

BIT 2

4

BIT 4

0

BIT 1 j BIT 0I
II

INPUTS FROMEACH ACC ff

IlZERO FLAG OUTPUT(LSB]OUTPUT STROBE COllTROL

I
I
I

Co

~

:::0

(")

:::c

I

r0

.------tU- AC.CUMULATE CLOCK..-----<>-- SHIFT RIGllTCLOCK

3::
en

0

z-I

...._---«>- SHIFT LEFT CLOCKSHIFT RIGHT INPUT -<:it-------'....__---<>- SHIFT LEFT INPUT

r-...--o---«>- SHIFT RIGHT OUTPUT
ADD/SUBTRACT INHIBIT -<:it------.

ITI
C)

:::0

~
c

ITI

~

ADD/SUBTRACT SELECT - - < > - - - - - - - - +1---r----;-1--.,...4-T-H-Bl-T-------_.,..--4-T-H-Bl-T-!-l---t----;----i-- I

I

I

I
I

T

R REGISTER MSB OUTPUT --<k----<1-----t,...._..

I
I

I
I

I
I

I
I

c:
=i
w
co

I

I

I

I

I

I

I

I

I

I

0

I

I CARRY

I
I

I
I
j

I OUTPUT
I
I

I

I

I

I

CARRY /BORROW OUTPUT --<>-----<1--t- - 1 --r - - . . - . - - t - - - t .

SA/SFULL ADDERA SUBTRACTER BCARRY Il-t-II - --tII - - fII - -11------DCARRY/BORROW INPUT
l

-

INPUT

1 --""°l_ _..:..l_ _;..I------1~ "R" REGISTER RESET_ _...__......__ _.._I_ _ _ _ _+--+--------+--..:..
"R" REGISTER LOAD CONTROL--<J1--------+----+--..._---1------+----------1.--...._-__._ _...__

7

&

5

:::0

(")

4

3

2

0

--------------PARALLEL INPUTS--------------'

NOTE: Polarity indicators (0) external lo the solid box conform lo MIL·STD-8068 where 0 indicates the less positive stale is active. Internal to the box and in the remainderof this data sheet conventional MOS polarities are used, where HI = "l" :::;:-10 V and LO = "O" ::::;: Gnd.

o·

SCHEMATIC DIAGRAM,._,

f!o .- ......_\fii?OTHEblSl

.-,

"'l'I

:!!:
::a
n

1iWf!M!QB

-c

:c
r-

31:

0

en

--

z·

~lBACf
SHl'1

-;"
01
cc

"

-I

ITI
G')

::a

>
....
'ITI
c
:(')

::u

GIOW?

Yi.,

"'"""'ill''t.

"'

INf'UlS

1...

'.!!~

n
c:
=i
w
co.

g

3801
10-BIT SERIAL/PARALLEL-PARALLEL/SERIAL CONVERTERMOS INTEGRATED CIRCUIT

GENERAL DESCRIPTION - The 3801 is a monolithic MOS/LSI ten bit serial/parallel - parallel/serial converter
utilizing P-Channel Enhancement mode MOS technology. The device has the capability of serial or parallel
input and serial or parallel output. A holding register included on the chip is isolated from the shift registerby transfer gates. In serial to parallel applications data may be stored in the holding register while newdata is being entered into the shift register.
FEATURES• 8 AND 10 BIT SERIAL OUTPUT• 250 kHz SERIAL TO PARALLEL OPERATION• 500 kHz PARALLEL TO PARALLEL QPERATION• 120 mW POWER DISSIPATION• INPUT GATE PROTECTION• SE,T AND RESET OF HOLDING REGISTER• OUTPUT STROBE CONTROL• SINGLE PH~E CLOCK• RESET OF SERIAL REGISTERPHYSICAL DIMENSION
36 PINDUAL ,,!!"·LINE PACKAGE

.190
.140

:01a

1)72

.no
.090

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)
Input Voltages
Power Supply
Storage Temperature
Operation Temperature (A6H380114X)l(A6H380119X)APPLICATIONS
Serial and Parallel Data Conversion in• Process Control• Data Terminals• Computer Peripheral Equipment• Data Acquisition-30 to +0.3 Volts-30 Volts-55°Cto +1so 0 c-55°C to +ss 0 c
0°Cto +70°C

L
t

.019

.017

ORDER PART NO.A6H380114X
A6H380119X

BLOCK DIAGRAMPIN CONFIGURATIONPAIALLEL IATA omm
36

TRMISFElll

34

RESET s~30

7tNPUf29&IN""!

21

51NPUT-{llES£l"HR
"'"

12

2S

21NPUT"

24!INPUTIBITSEft.OUTPUJ

I llT SEllAL tQTPllJ

IOBITSEll.OUTPUJPOWERSUPPl.V(V.,.,)

11 BIT SHiil OUTPIT17

ZZ

PAMUEL EMILE

21

CLOClllNPUT

20

10 COllllfECflOJI._"_ _ _ _ _ ____J

t nPllALlELt t tDATAt llPlfJS
t+t

FAIRCHILCJSEMICONDUCTOR
313 FAIRCHILD DRIVE, MOUNTAIN VIEW, CALIFORNIA, (415) 962-5011, TWX: 910-379-6435

7-59

A DIVISION OF FAIRCHILD CAMERA AND INSTRUMENT CORPORATIONFAIRCHILD MOS INTEGRATED CIRCUIT 3801
ELECTRICAL CHARACTERISTICS (V66 = -27 ±2.0 Volts, RL = lOMO, CL= 10 pF unless otherwise specified)
SYMBOLCHARACTERISTIC

MIN.

TYP.

MAX.

UNITS

-2.0
-30

Volts
Volts

-1.0

Volts
Volts
Volts

CONDITIONS

Logic Inputs

fmax

l

tdf
tr
tdr
tr '

f

''}
tf
tdr
tr

"0"
"l"
Logic Outputs
"0"
·"1"
··1"
Clock
Amplitude
Width
Frequency
SerialParallel
Serial Delay,rise and fall
times

0
-9.0

-11

-11

-12

-9.0
1.()

-30
10

Volts
µs

DC
DC

250
500

kHz
kHz

Imax
pmax
ILX
tdd

Input Leakage Current
Data Delay Time

P.S

µs
P.S

µs
µs

7.0
190

pF
mA
mW

V66 =-27V
V66 = -27V

5.0

p.A

V;n

ns

250

TIMING DIAGRAMOUTPUT DELAY, RISE AND FALL TIMES:•ct1i

1wc,1-------;I I

w

Click - - - .1

yI

Serial Data D1tput

•

1
i-

_ _ ___.,....._..,.

I

:I

Ti111

r - Ti111

Ii !\: ~,-----.;-,~,/ !I1: ldr l tr I

I ldf I If :om BIT TIMlllG
CLOCK------.u...- - - - - - - - • • Ti111

wr----------•. .
I
I

Data Input

I

I

itddl

7-60

RL=40k0

µ$
µs
µs

0.6
0.2
0.5
0.5
0.55
0.35
0.4
0.3
7.0
4.5
120

Parallel Delay,rise and falltimes
Data and Control Input CapacitancePower Supply Current Drain
Power Dissipation

cin

0
-10

Tl11e

= -20V[

FAIRCHILD MOS INTEGRATED CIRCUIT 3801

LOGIC DIAGRAM
DllPUTS

I
. I

lif I

I
I

I
I
I llT 9 I Bil 8

I

I
BIT 1

BIT 6

BIT5

TYPICAL BASIC
LOGIC DIAGRAM
Of ONE BIT
SEGMENTI

I
I

I llT 4 I llT I
I
I
I

llT2

I
I
I

I
I

TRANSf. 0
TRANSF.1

I-t>-- I

BIT2 OlllY I-t>-- I
BIT 0 ONLY ISERIAL Ill

I
I

8 BIT OUTPUT

I
I

10 BIT OUTPUT

I
I
I
I

I

CLOCK
RISETSR

I
I
I
I

I

PE

I

PARALLEL IIAPPLICATIONS (Basic Logic Reptesentation)

PARALLEL to SERIALSERIAL TO PARALLELCONVERTER

CONVERTEft........... .......................
\ .-9876543210

REF '1'!RANS. TO
OUTPUTSERIAi:. INPUT~PARALLEL OUTPUT
SET'8' OUT
RESET'10' OUT-27V

TRANS. '0'
VGG
TRANS. '1'
GND.
RESET SR
CLOCK
PARALLEL INPUT-27V

9 B7 6 5 4 3 2 1 0

SET'8' GUY _..._a~EliEf'10' OUT.....,_oVaa-27V
GMO • ..,...._<>

TRANS. '0'

HAMS. '1'
RESU SR--o

CLOCK ..----o
PARALLEL INPUT
9 8_
7 6_
5 4__
3 .,....._...,
2. 1 0 l'--o PARALLEL...._._ENABLEPARALLEL ENABLE__..........._...._···-·-·----~---------------------------------""-

7-61_ _____..__....__......

__,

FAIRCHILD. MOS INTEGRATED CIRCUIT 3801
APPLICATIONS(Basic Logic Representation)

SERIAL TO SERIAL BUFFER REGISTER·a·ouT---o'10' ouT--o

SET
RESET

TRANS. 'Q'
Vec--o -27V
TRANS. '1'
eNo.--oRESET SR
CLOCK
PARALLEL INPUT.
9876543210
PARALLEL ENABLE--oSERIAL INPUT. PARALLEL TO PARALLEL BUFFERREGISTER

REF '1'\

98 76543210
PARALLEL OUTPUT

SET
RESET
TRANS.TOOUTPUT-: f-27V'8' OUT'10' OUT

TRANS. 'O'
Vee
TRANS. '1'
eND.
RESET SR
CLOCK
PARALLEL INPUT
9876543210

SERIAL. INPUT

7-62

-27V

I

MOS INTEGRATED Gl~CUITS COMING SOON
Type

Function

Type

Function

3103
3104
3251

Dynamic Universal Gate
Dynamic Universal Storage Element
64 Character Raster Scan Character Generator(7 x 9 Matrix)
Dual 100-Bit Static Shift Register
Triple 66-Bit Dynamic Shift Register
Triple 64-Bit Dynamic Shift Register
512-Bit Dynamic Shift Register3502
3503-6
3511
3531
3716
3802
3804

4096-Bit Dynamic Read Only Memory
2048-Bit Dynamic Read Only Memory
256-Bit Random Access Memory
256-Bit Random Access Memory ,16 Channel Random Sequential Multiplexer
8-Bit S-P, P-S Dynamic Shift Register /Converter
4-Bit Arithmetic Unit (Basic CPU Element)

3307
3322
3323
3324

3322/3 -TRIPLE 66/64 BIT 20 DYNAMIC SHIFT REGISTER
The 3322/3 is a triple 66 bit dynamic shift register. It is a monolithic
integrated circuit utilizing Planar II* P-channel Enhancement Mode
MOS Technology. The 3322 is designed to hold a 64 bit data wordand 2 bit sign word. The 3323 is a 64 bit mask option of the 3322.

3103 - DYNAMIC 40 UNIVERSAL GATE
The 3103 is a universal gate utilizing P-channe.I Enhancement Mode
MOS technology. It is a dynamic 4¢ circuit with DC stable outputs
and is compatible with the dynamic logic family. Both data anddata compliment outputs are available.
V00

r----------------1

Gnd---;--:_____~-;.~-:~~~~. . .r-t>~~~~-;.~-:~~~~. . .r-t>~~~-

r~---~------1~_1_ 1r-t>~-

A
B

c

E

F
.. G

L ___

T--T--T--1-- -~3324 - 512 BIT DYNAMIC SHIFT REGISTER
The 3324 is a 512 Bit Dynamic MOS Shift Register. Input logic isprovided for multiplexing two data sources or recirculating storeddata.

3307 - DUAL 100 BIT STATIC SHIFT REGISTER
The 3307 is a dual 100 bit static serial in-serial out shift register
utilizing 2 phase clock capable of operating from DC to 1 MH,.
Yoo

6

10

Input I01

100 Bits

Output I

Input A
Input B
Input
Select802
Input 2

Output 2

7~63

256 Bit

8

9
IO

Input
Multi·
plexerOutput256.BitMOS INTEGRATED CIRCUITS COMING SOON
3104- DYNAMIC 40 UNIVERSAL STORAGE ELEMENT
The 3104 is a Universal Flip·Flop utilizing P-channel Enhancement
Mode MOS technology. It is a monolithic dynamic 4¢ storage element incorporating DC stable output and bi-directional bussing
techniques. This provides "write in" or "read out" capability on
the same data lines. The 3104 is a member of.a compatible dynamic
logic family.

3502 - 4096-BIT DYNAMIC READ-ONLY MEMORY
Fairchild will announce a 4096-bit dynamic read-only memory. It
will be a monolithic integraterl circuit utilizing 4¢ technology for
operation. The output buffers will have static characteristics. lheformat will be 512 words by 8 bits. The fixed program memory mustbe specified by the customer and is customized by modifying one
mask in the fabrication process. This results in a low cost, fast
tum-around custom memory.
·~--.___-WI.--~~~~~~~~~~--1

Input

512 Words

i

}'"'"

8 BitsChip SelectV DD Gnd

3503-6 - 2048-BIT DYNAMIC READ-ONLY MEMORY
The 2048-bit dynamic read-only memory utilizes P-channel enhancement mode MOS technology. The output buffers feature bipolar
compatibility and static characteristics. Metal mask options allow
memory formats of 2048 words by 1 bit, 1024 words by 2 bits,
512 words by 4 bits, and 256 words by 8 bits. The fixed program
memory must be specified by the customer. The memory is customized utilizing computer aided design techniques to generate themodified gate oxide cut mask. This results in a fast turnaround,
low cost custom memory.
Reset

W1= W2= 1
R1=R2=l3511- 256 BIT RANDOM ACCESS MEMORY
The 3511 is a 256 bit MOS memory cell designed to operate withbipolar decode drivers and a current mode sense amplifier. The
256-1 bit words are selected by coincident addressing of the X-Yadress lines. Cycle times (read or · write) of approximately 200
nanoseconds are achieved.

3251 - 64 CHARACTER RASTER SCAN CHARACTER GENERATOR
The 3251 is a character generator designed for use with a CRT
display utilizing TV type raster. Six input lines are provided to
select one of 64 alpha-numeric or special symbol characters fordisplay in an 8 x 10 point pattern (7 x 9 dot matrix). Four additional input lines are provided to select the lines within a character.
NOTE: This device can be used as a 640 word by 8 bit (5120 bit)general purpose Read Only Memory.
·
Vaa
21

flt
15

112
5

CHA~ACTER&

LINE

Decode36

MemoryADDRESS

OutputBuffers

24
25
26
27
28

Top
View

OUTPUT

29
30
31
18

34

7-64

19

MOS INTEGRATED CIRCUITS COMING SOON
3531 - 256 BIT RANDOM ACCESS MEMORY
The 3531 is a monolithic MOS/LSI two hundred fifty-six bit random
access non-destructive read out (NDRO) memory with decode andoutput buffers on chip. The memory is arranged as 256 on{bitwords, which may be addressed one at a time by means of 8
address lines.
8 pinsAddress:
Supplies:
3 pins1 pin
Input:
1 pin
Output:Chip select:
1 pin
Read/Write:
1 pin
1 pin
Strobe:16 pins

DecodeM~~rl~ t - - - - - 1

3716-16 CHANNEL MULTIPLEXER
The 3716 is an analog or digital multiplexer which may be used
as a single 16 channel, a dual 8 channel or a differential 8 channel
multiplexer. The 3716 channel selection can be made in a random
access, or sequential mode.
Analog Inputs
1------------------16

Analog Output(chan. 1·8)
19

Current Shunt
Switches34

Differential
Mode Control
32

Output23

Decoder

Terminal Count

33

Gnd

Yoo

DecodeRead/Write
Logic

Address

Data R/W Initiate
In Enable

VGG

Clock

Chip SelectCounter

35

3804 - 4 BIT CPU ELEMENT
The 3804 is an MOS/LSI device that functions as a 4 bit slice of aCentral Processing Unit. It is expandable to any word length in
4 bit increments. The 3804 performs the logic functions of OR,
AND, Exclusive NOR and Compare, and the arithmetic functions of
ADD or Subtract (A-B or B-A). It has the capability of signed orunsigned operation as well as the capability to shift right or left
for multiply or divide operation.
4 Bit Parallel
Input/Output "lA"

Gnd

4 Bit Parallel
Input/Output "2A"

1111

l l

1

1
Read lA

Shilt Right In
Shilt Left Out
Clock Pulse
Accumulator Bypass
Shift Right Enable
Shift Left Enable

MSB/Overflow
Carry/Borrow Out
Flag Out

Write Control 1....!!...

28

Ao A1 A2 AJ
Bi-Directional Input/Output Buffer

35

31

11

Ao A1 A2 AJ
Bi-Directional Input/Output Buller

11

16
17

JJ

29
26
25

~ Read 2A

22
20
21

32
33

Arithmetic Logic Unit

L=rJ
1

1111

Accumulator Registor

30

34

19

11
t

24
26
27
18

Shift Right Out
Shift Left In

E

OpCodeMult./Div. Override
Index Override
Carry/Borrow In
Flag In

L_J

13 10 7 4
4 Bit Parallel
Input "B"

7-65

36

Write Control 2

MOS INTEGRATED C!RCUITS COMING SOON
3802 - 8 BIT DUAL RANK 4¢ DYNAMIC BUFFER REGISTER
The 3802 is a Dual Rank Buffer Register featuring bi-directional
bussing capability. Data may be entere~ into register A or B fromeither one of two common data busses. The data may be trans-

AO

BO

Al

Bl

A2.

B2

A3

B3

A4

B4

ferred between registers but register A can only be read out on
Buss I and register B on 1L

A5

B5

A6

B6

A7

87

l l l t l l 1111111111

Read All
Read Ell

B Register

write BlA'i 87

iili iili

Write Bill 1
CompareShift RightIn
Shift Left
Out

-

-

t---

J--- Shift Right Out!---- Shift Left In
Shift Right - Left Enable

1---- Clear or Circulate

ARegister14"--- Read AI
14"--- Read Bl
1---- Write Al1---- Write All

1111111-Tl 1111111

7-66

111 112 113 114

Gnd

Yoo

Application
Notes
and
Technical
PapersAPPLICATION NOTES • NUMERIC LISTING
APP-41

Stable Wideband Emitter Followers - Paul J. Beneteau

APP-124

APP-59An Improved Emitter-Coupled MultivibratorP. J. Beneteau and A. Evangeliste

Designing with Off-the-Shelf Linear Microcircuits Robert Widlar and James Giles

APP-125

A Versatile Tester for Linear Integrated Circuits James Giles

APP-128

Complementary Transistor Micrologic® Integrated
Circuits - R. C. Ghest

APP·61/2 Long Delay Transistor Timer - P. Alderisio
APl>-64

Application of Milliwatt Micrologic® Elements - H. T. Chua

APP-85Micrologic® Shift Counters - George Powers

APP-130

Aids for Digital IC Systems-Murray Siegel and Lee Marley

APP-87

A Varactor Bias Servo System - Bruce 0. Anderson

APP-131

APP-88

Medium Power Silicon Transistor DC to DC Converters Thomas B. Mills

Transistor-Transistor Micrologic® Integrated Circuits John Nichols

APP-132

Single-Phase Control for Cycloconverter - Samuel Schwartz

APP·93

Transient Response Characteristics of Phototransistors George T. Daughters

APP-133

Precision Electronic Digital Clock Uses IC's B. Jensen and J. Irwin

APP-103

Applications of the Silicon Planar* Field-Effect Transistor Larry Blaser and John MacDougall

APP-134

Effect of Integrated Circuits on Systems Comparative Case - Robert Ricks .

APP-105

A Monolithic Operational Amplifier - Robert Widlar

APP-135

APP-106

Using Fairchild Integrated Circuits as Monostable
Multivibrators - Robert Ricks

Performance of the µA703 in 100 MHz and 200 MHz
Amplifiers and 100 MHz Harmonic Mixers David Bingham

APP·107

Diode Transistor Micrologic® - George Powers

APP-139

Multivibrator-Type Vertical-Deflection Circuit for
Television - J. S. MacDougall

APP·109

ApplicatiOns of the Silicon Planar* II MOS FETJohn MacDougall

APP-141

Transistorized TV Horizontal Driver System Larry Blaser and Hermann Ebenhoech

APP-111The Improved µA702** Wideband DC Amplifier Robert Widlar

APP-142

15-Watt Audio Amplifier with Short-Circuit Protection Don Smith

APP-143

A Horizontal Oscillator for Transistorized TV Set Larry Blaser and Hermann Ebenhoech

APP-144

Frequency Synthesizer for 27 MHz Citizens' Band
Transceiver - Larry Blaser

APP-145

Color Television Chroma Reference Systems Using theµA703 - Larry Blaser and No.rm Sturn

APP-114µA702** Circuit Design Ideas - (Six Authors)

APP-115

Maximum Integrated Circuit Utilization Through Mixing
Compatible Logic Families - Robert Ricks

APP-116

The Operation and Use of a Fast Integrated Circuit
Comparator - Robert Widlar

APP·117Frequency Compensation Techniques for an Integrated
Operational Amplifier ...... James Giles

APP-118

Counter Micrologic® A New Dimension in Multi-Function
Integrated Circuits-'- George Powers

APP·146

Color TV Sound System Using the Fairchild µA703 Larry Blaser

APP-119

Ways to Increase Speed in Large Count Binary Counters Jack Irwin·

APP-147

Characterization and Application of µA703 in Four-Stage
High-Quality FM IF Amplifier - David Bingham

APP-120

Using the J·K Flip-Flop in Small Modulo Counters Jack Irwin

APP-148

25-Watt Audio Amplifier with Short-Circuit Protection Derek Bray and Wesley Votipka

APP-121

A High-Efficiency Power Supply Using Micrologic®
Integrated Circuits- Samuel Schwartz

APP-149

Semiconductor Circuits for 19-inch Black and White
Television Receivers- Derek Bray

APP·123Core Memory Sense Amplifier Designs Using an Integrated
Dual Comparator - Robert Widlar

APP-150

Semiconductor Circuits for Hybrid Color Television Derek Bray

•Planar is a patented fairchild process.
**The µ,A702 i~ renumbered the µA702A.

APPLICATION NOTES/TECHNICAL PAPERS,NUMERIC LISTING

APP-151

High-Performance Integrated .FM IF Strips - Ted Hanna

APP-177

The Hot Carrier Mixer Diode - S. Sir

APP-152

250 MHz Distributed Amplitier Suitable for CATV
Truck Line - Larry Blaser and Norman Sturn

APP-178

A Navigation Receiver Using a Digit!ll Frequency
Synthesizer - J. Stinehelfer

APP-153

Logic Designs Using the TTµL9008- Clive Ghest

APP-179

APP-154

Compatible Current Sinking Logic - Abe Marder andRalph Bennett

Line-Operated Phono Circuits Using the PFB 1400 D. Campbell, R. Westlake

APP-155

Industrial Code Conversion - Don Femling

APP-156

Designing with the µA703 Monolithic RF·IF Amplifier G. J, Estep

APP-157

A Fixed-Gain Low-Distortion AF Amplifier - G. J. Estep

APP-158

Two High-Performance Monolithic Microcircuits for FM
Sound System - David Bingham

TP-24

Overloading and Spurious Responses in Transistor FM
Tuners - Earl Cummins

APP-159

A Low-Cost AM-FM Radio Employing an Integrated Circuit
Design - David Bingham and John (Ted) Hanna

TP-27

Forward AGC Design Considerations in Transistorized
Television ,Receivers - Harry Suzuki

APP-160

Applications of the CCSL 9301 Decoder - R. Clive Ghest

TP-28

APP-161

CCSL 9300 Shift Register - John L. Nichols

Measurement of Transistor High-Frequency Current Gain Heitor Franco

APP-163

Applications of the CCSL 9304 Dual Adder R. Clive Ghest

TP-31

An FM Tuner Using MOS-FET's and Integrated Circuits John Barrett, Larry Blaser, and Harry Suzuki

APP-164

Application of the µA722 10-Bit Current Source M. Rudin, G. Erdi, R. Walker, R. Ricks

TP-32

A Unique Circuit Design for a High-Performance,
Operational Amplifier Especially Suited to Monolithic
Construction - Robert Widlar

APP-165

SH3200-SH3201 Hybrid DC Voltage Regulators S. K. Leong

TP-33

Some Circuit Design Techniques for Linear Integrated
Circuits - Robert Widlar

APP-166

HLLDTµL Integrated Circuits- R. Repass, 0. Lykins

TP-35

APP-167

MSI 9308 Dual 4-Bit Latch - R. C. Ghest

A Black and White and Color TV Video 1.-F Output
Transistor - Derek Bray and Philip Froess

APP-168

Applications of the 9034 Read-Only Memory P. F. Schenck

TP-36

A Low Noise, AGC Silicon Transistor Useful From LF to
UHF - David Bingham, Harry Suzuki, and Charles Watson

APP-169

CCSL 9306 Up-Down BCD Counter - R. C. Ghest,
S. Simonsen

TP-37

Integrated Circuits in Industrial Control Donald Femling and Jack Irwin

APP-170

Applications of the 9311-0ne-Out-of-16-DecoderR. C. Ghest·

TP-38

Semiconductor Video Amplifiers for Monochrome andColor Receivers - Derek Bray

APP-171

Applications of the µA739 and µA749 Dual Preamplifier
Circuits in .Home. Entertainment EquipmentD. Campbell, et al

TP-39

A New 400-Volt Horizontal Output Transistor T. B. Mills and E. F. Kiburis

TP-40

Radiation Testing of Linear Microcircuits-J. Darryl Lieux

APP-172

The 3800 Arithmetic Unit- P. Schenck

TP-41

APP-173

The 9601 · A Second Generation One-Shot - lAnderson,
T. Gray, R. Walker

Space and Nuclear Environments and their Effects on
Semiconductors - David K. Myers

TP-42

Novel Multi-Purpose LIC's Introduce New Concepts into
Circuit Design - D11.vid Bingham

TP-43

Color TV Processing Using Integrated Circuits Larry Blaser and Derek Bray

TP-44

Let's Clarify IC Noise Margins - R. Clive Ghest

TP-46

TTµL Integrated Circuits: High Speed Considerations R. C. Ghest

APP-174

A Low-Cost Hybrid Color TV Receiver....:.. N. Doyle, D. Smith

APP-175

A Low-Noise Dual Operational Amplifier- D. Long,
D. Campbell

APP-176

A Digital Frequency Synthesizer for Airborne Navigation
or Communications Transceiver - M. Nichols,
J. Stinehelfer

Note: The following publications are obsolete and out of print:

APP's 1-40, 42-58, 60, 62, 63, 65-84, 86, 89-92, 94-102,
104, 108, 110, 112, 113, 122,
126, 127, 129, 138, 140.
TP's 1-23, 25, 26, 29, 30, 34.

8-2

MICROCIRCUITS PRODUCT CODE EXPLANATIONTO-S

IXING PRIVILEGES:
gital Circuits: (RTµL, LPRTµL, TIµL, CµL and CTµL).
gital circuits may be mixed for price advantage within the following groups
gardless of temperature range or package, as long as minimum line item
1antity is met.
Group 1:All RT µL and LPRTµL may be mixed except for epoxy circuits.
Group 2:Mixing is allowed on all DTµL, TI µL, MSI, CCSL, LPDTµL, HLLDTµL and
Dual DTµL device types.
Group 3:CTµL circuits may be mixed.
Group 4:CµL circuits may be mixed.
Linear Circuits (LIC):
Linear circuits may not be mixed.
1 integrated circuit purchases, 100 pieces or more of any single product areways sold at the 100 piece single price.
1 the purchase of more than one product, any quantity under 100 pieces may
i bought at the 100 piece mixed price if;a) all the items total 100 pieces or more;b) Minimum quantity per line item is 10 pieces.

s

All 8 pins
All 8 pins
1, 2, 3,4, G& 8 pins
1, 3, 4, S, 7 & 8 pins
All 10 pins
All 10 pins
All 12 pins
All 14 pinsl, 2, 3, 4, 5, G,
8, 9, 19 pins

s
10
10
12
14
10

All 8 pins
1, 3, 4, 5, 7 & 8 pins

CODE

114 x~).6

10
14
10
10
10
14
14
14
lG

CerpakCerpakCerpakFlat Pack
Glass
CerpakFlat Pack
Cerpak
Glass

30

=
=
=

D. Two digits are used to indicate process and temperature range
respectively.

11 = (-55°C to +125°C)
14 (-55°C to +S5°C)
19 (0°C to + 70°C)
21(-55°C to +125°C)
22 = (0°C to +100°C)
28 = (+15°Cto +55°C)
29 = (0°C to + 10°C)
31(-55°cto +125°C)
32 = (0°C to +S5°C)
39 (0° to +10°C)
51 = (-55°C to +125°C)
5G = c-20°c to +ioo 0 c)
59
co·c to +75°C)
59 = (+15°Cto+SS°C)
79 = (+15°Cto +55°C)
79(O°C to +75°C)

=
=
=
=
=
=

=

MICROCIRCUITS FAMILY DESIGNATIONSCµLCounting Micrologic® Integrated Circuits= Complementary Transistor Micrologic:t<iCTµL= Diode Transistor Micrologic®
C/DTµL"
C/LPDTµL * = Low Power Diode Transistor Micrologic®
= Micrologic® Integrated Circuits
RTµL=Low Power Micrologic® Integrated Circuits (Formerly MWµL)
LPRTµL=Transistor Transistor Micrologic® (T')
C/TIµL= Linear Integrated Circuits (Formerly ALC)UC
= Metal over Silicon/Integrated Circuit
MOS/IC
Elements which are part of Fairchild Semiconductor's"'C/XX
Compatible Current Sinking Logic (CCSL) family
MSI= Medium Scale Integration
MµL
Memory Micrologic®

=

PLUG-IN PACKAGES
SIZE

NAME

CODE

1,4 x %
1,4 x %
.520 x .850
.255 x .750
.255 x .sso
.2S2 x .7G7.300 x .84G
.GOO x 1.23
.GOO x 1.83

14
lG
lG
14
10
14
lG
24
3G

Dip
Dip
Dip
Dip
Dip
Fairpak'M
Dip
Dip
Dip

GA
GB
GO
GE
GF
lA
GJ
GG
GH

MOS/Full Range Military
MOS/Intermediate Range
MOS/Industrial Range
Full Range Military Equipment
Military Ground Support Equipment
Commercial Equipment
Industrial Equipment
Full Range Military Equipment (LIC)
Industrial Equipment (LIC)
Industrial Equipment (LIC)
Full Range Military Equipment
Intermediate Range
Industrial Equipment (DTµL and CµL)
Commercial Equipment (CTµL)
Commercial Equipment (CTµL) Clamped
Counting Family (CµL)

E. This digit is used by LIC to indicate electrical class.
1 High performance Aerospace and Defense
2 = Standard Aerospace and Defense
3 = Industrial and Ground Aerospace and Defense
4 =Consumer
This digit used by MOS/IC to indicate electrical class.
2 = ± 5.0 volt analog input
3 = 0 to 5.0 volt analog input

3E
3F
3G
3H
31
3J
3K
3L
3S

MAXIMUM LEADS

BA
SB
SS

C. Four digits are used for general product groups.
0000-0099 = Kits and kit parts
1000-1999 =Custom integrated circuits
3000-3900
MOS Integrated Circuit
5000-5999 = Second source integrated circuits
7000-7999 Linear integrated circuits
9000-9999 Digital integrated circuits

=

NAME

4
None
5
None
None
None

SA
SB
SC
5D
5E
SF
5G
5H
5J
5S

8
8
Custom•. PACKAGE CODEFLAT PACKAGESMAXIMUM LEADS

None
4
4

CODE

EPOXY

x

SIZE

PINS SHORTEDTO CAN

Custom

A. Generic Device Type - U for microcircuits, H for hybrids, A for MOS/IC,
and Bipolar Arrays and Memories.
B. Package Code (see table belbw).
C. Basic Circuit Code.
D. Temperature Range (see table below).
E. This digit is used by LIC to indicate electrical class (see below).

1.4 x ~l6
1,4 x 1,4
1,4 x 1,4
1,4 x 1,4
1,4 x 1,4
1,4 x 1,4
1,4 x %
1,4 x %
CustomPINS USED

88

llCROCIRCUITS PRODUCT CODE EXPLANATION; Fairchild integrated circuits are available in a wide variety of package congurations and operating temperature ranges, it is essential that customers>ecify the. exact circuit, package, and temperature range desired.
1ere is a ten-digit product code used by all Fairchild distributors and field sales'fices to identify integrated circuits in a particular package and temperature
1nge. Proper use of this product code, explained in detail below, will ensure
1e expeditious handling of all customer orders.
full range RTµL 9900 in a TO-S package is designated by code number
5D990021X. Breakdown of the code is as follows:
5D 9900 21
A
B
C
D
E

u

MAXIMUM LEADS

=
=

9-1

HYBRIDS PRODUCT CODE EXPLANATION==MINIMUM ORDER $50.00

BH
114 x 1,4 Forbes Flat Package, 14 leads
BK% x % Flat Package, 14 leads
BY = l" x 0.8" Flat Packago, 32 leads
CL = Ceramic Channel
GQ ::.=: 14 lead Plastic DIP
GF = 10 lead Plastic DIP
GK
14 lead Ceramic DIPGRlG lead Ceramic DIP
2A%x % Flat Package
2Bl" x l" Fl.at Package (Flat metal lid)

MIXING PRIVILEGES:
Hybrid circuits may not be mixed.
HYBRIDS PRODUCT CODE EXPLANATION
The product code consists of a ten digit number giving all information necessary to properly iq~ntify the part. For example:
Product Code H/AG/2001/1/XX
Group Letter A/B/C/D/E

=
=
=
=

C. Four digits are used for general hybrid product groups.
0000-1999
Custom Circuit
2000-2999
Standard Hybrids - Digital
3000-3999 = Standard Hybrids - Linear
GOOO-G999
Quads
9000-9999
Flyer

=
=

Group Letter Explanations:A. This digit indicates general product code. Currently an "H" isused by Hybrids.

==

B. Two letters are used to indicate the package as follows:
XC = T0-5, 3 lead header
AM
T0-5, Glead header
5T = T0-100, 8 lead header
AG = T0-5, 10 lead header
BW = T0-5, 12 lead header
BG = 114 x 1,4 Forbes Flat Package, 10 leads

D. One digit is used to indicate the operating temperature range.
lXX(-55°C to +125°C)
Full Range Military Equipment
8XX = (+15°C to +55°C)
CommerCial Equipment
9XX(0°C to + 70°C)
Industrial Equtpment===

E. Currently "XX" is used for these digits.

9-2

FAIRCHILD SEMICONDUCTORTERMS AND CONDITIONS OF SALE"
1. SCOPE- THE TERMS AND CONDITIONS OF SALE CONTAINEDHEREINAPPLY TO ALL QUOTATIONS MADE AND PURCHASE ORDERS ENTERED INTO
BY THE SELLER. THE SAID TERMS AND CONDITIONS MAY IN SOME INSTANCESCONFLICT WITH SOME OF THE TERMS AND CONDITIONS AFFIXED TO THE
FORM OR ORDER BLANK AND/OR SPECIFIED BY THE BUYER. THEREFORE,
ACCEPTANCE OF THE BUYER'S ORDER IS MADE ONLY ON THE EXPRESS UNDERSTANDING AND CONDITION THAT INSOFAR AS THE TERMS AND CONDITIONS OF THIS ACCEPTANCE CONFLICT WITH ANY TERMS AND CONDITIONS
OF THE BUYER'S ORDER, THE TERMS AND CONDITIONS OF THIS ACCEPTANCE
SHALL GOVERN, IRRESPECTIVE OF WHETHER THE BUYER ACCEPTS THESE
CONDITIONS BY A WRITTEN ACKNOWLEDGMENT, BY IMPLICATION, OR ACCEPTANCE AND PAYMENT OF GOODS ORDERED HEREUNDER. SELLER'S FAILURE TO OBJECT TO PROVISIONS CONTAINED IN ANY COMMUNICATION FROMBUYER SHALL NOT BE DEEMED A WAIVER OF THE PROVISIONS OF THIS ACCEPTANCE. ANY CHANGES IN THE TERMS AND. CONDITIONS OF SALE CON:
TAlNED HEREIN MUST SPECIFICALLY BE AGREED TO IN WRITING BY THE
GENERAL MANAGER OF THE SELLER BEFORE BECOMING BINDING ON EITHERTHE SELLER OR THE BUYER.
All orders or contracts must be approved and accepted by the Seller at its
home office.
The said terms and conditions of sale shall be appijcable whether or notthey are attached to or enclosed with . the products to be sold or soldhereunder.
·
Prices quoted for the items described above· and acknowledged hereby are
firm and not subject to audit, price revision, or price redetermination.
2. TERMS OF PAYMENT -All invoices are due and payable 30 days fromdate of invoice. No discounts are authorized.
'.

F.. o. B. POINT -All sales are made F. 0. B. point of shipment. Seller's

title passes to Buyer and Seller's liability as to delivery .ceases upon making
delivery of material purchased hereurid.er to carrier at shipping point ingood condition; the carrier acting as Buyer's agent. All claims for damages
must be filed with the carrier. All shipments will normally. be made by Parcel Post, Railway Express, Air Express or Air Freight Unless specific instructions from Buyer specify which of the fo'regoing methods of shipment is. tobe used, the Seller will exercise his own discretion. ··4. DELIVERY - Shipping dates are approximate and are based upon prompt
receipt from Buyer of all necessary information. In no event will Seller beliable for any reprocurement costs, nor for delay or non-delivery, due tocauses beyond its reasonable control, includ.ihg but not Iimited to acts ofGod, acts of civil or military authority, priorities, fires, strikes, lockouts,
slowdowns, factory or labor conditions, errors .in manufactu·e and inability
due to causes beyond the Seller's reasonable control to obtain necessary
labor, materials, or manufacturing facilities. In the event of any such delay
the date of delivery shall, at the request of the Seller, be deferred for aperiod equal to the time lost by reason of the delay.
5. TAXES - Unless otherwise specifically provided herein, the amount of any
present or future sales, revenue, excise or othertax applicable to the products covered by this order or the .manufacture or sale thereof, shall be
added to the purchase price and shall be paid by the Buyer, or in Iieu
thereof the Buyer shall provide the Seller with a tax. exemption certificate
acceptable to the taxing authorities.
·
6. PATENTS - The Buyer shall hold the Seller harmless against any expense
or loss resulting from infringement of patents or trademarks arising fromcompliance with Buyer's designs or specifications or instructions. The saleof products by the Seller does not convey any license, by implication,
estoppel, or otherwise, under patent claims covering combinations of said
products with other devices or elements.
·

non-infringing, or remove said product and refund the purchase price andthe transportation and installation costs thereof. The foregoing states theentire liability of the Seller for patent infringement by the said products or
any part thereof.
7. ASSIGNMENT - The Buyer shall not assign his order or any interest
therein or any rights thereunder without the prior written consent of Seller.
8. WARRANTY - The Seller warrants that the articles to be delivered under
this purchase order will be free from defects in material and workmanshipunder normal use and service. Seller's obligations under this warranty are
limited to replacing or repairing, at its option, at its factory, any of said
articles which shall within one (1) year after shipment be returned to theSeller's factory of origin, transportation charges prepaid, and which are,after examination, disclosed to the Seller's satisfaction to be thus defective. THIS WARRANTY IS EXPRESSED IN. LIEU OF ALL OTHER WARRANTIES,EXPRESSED OR IMPLIED, INCLUDING THE IMPLIED WARRANTY OF FITNESSFOR A PARTICULAR PURPOSE, AND OF ALL OTHER OBLIGATIONS OR LIABILITIES ON. THE SELL.ER'S PP.RT AND IT NEITHER ASSUMES NOR AUTHORIZESANY OTHER PERSON TO ASSUME FOR THE SELLER ANY OTHER LIABILITIES INCONNECTION WITH THE SALE OF THE SAID ARTICLES. This warranty shall not
apply to any of such articles wliich shall have been repaired or altered,
except by the Seller, or which shall have been subjected to misuse, negligence, or accident. The aforementioned provisions do not extend the original
warranty period of any article which has either bee.n repaired or replaced
by Seller.
·
9. PAYMENTS- If, in the judgment of the Seller, the financial conditions of
the Buyer at any time does not justify continuation of production or shipment on the terms of payment originally specified, the Seller niay require
full or partial payment in advance, and, in the event of the bankruptcy or
insolvency of the Buyer or in the event any proceeding is brought by oragainst the Buyer under the bankruptcy or insolvency laws, the Seller shallbe entitled to cancel any order then outstanding and shall receive reimbursement for its cancellation charges.
Each shipment shall be considered a separate and independent transaction,and payment therefor shall be made accordingly. If shipments are delayedby the Buyer, payments shall become due ori the date when the Seller isprepared to make shipment. If the .work covered by the purchase order isdelayed. by the Buyer, payments shall be made based on the purchase priceand the percentage of completion, Products held for the Buyer shall be at
the risk and expense of the Buyer .. The Seller reserves the right to ship to
its order and make collection by sight draft with bill of lading attached.
10. GENERAL- The Seller represents that with respect to the production of
the articles and/ or the performance of the services covered by this order,
it will fully comply with alt requirements· of the Fair Labor Standards Act of1938, as amended.
In no event shall any claim for consequential or special damages be madeby either party.
11. GOVERNMENT CONTRACT PROVISIONS - If Buyer's original purchase or11er indicates, by Contract Number, that it is placed under a Government contract, the following provisions of the current Ar.med Services
Procmement Regulation are applicable in accord.ance with the terms
thereof, with an appropriate. substitution of parties, as the case may be,i.e., "Contracting Officer" shall mean "Buyer," "Contractor" shall mean
"Seller,.., and the term "Contract" shall mean this order.
7-103.1, Definitions; 7-103.3, Extras; 7-103.4, Variation in Quantity; 7-103.6, Responsibility for Supplies; 7-103.7, Payments;
7-103.8, Assignment of Claims; 7-103.9, Additional Bond Security;
7-103.10, Federal, State, and Local Taxes; 7-103.13, Renegotiation;
Z-103.15, Soviet Controlled Areas; 7-103.16, Contract Work Hours
Standards Act- Overtime Compensation; 7-103.17, Walsh-Healey
Public Contract.s Act; 7-103.18, Equal Opportunity; 7-103.19, Officials Not to Benefit; 7-103.20, Covenant Against Contingent Fees;
7-103.21, Termination for Convenience of the Government- (onlyto the extent that Buyer's contract is terminated for the convenience of the Government); 7-103.22, Authorization and Consent;
7-103.23, Notice and Assistance Regarding Patent Infringement;
7-104.3, Buy America Act; 7-104.4, Notice to the Government ofLabor Disputes; 7-104.11, Excess Profit; 7-104.14, Utilization of
Small Business Concerns; 7-104.15, Examination of Records;
7-104.20, Utilization of Concerns in Labor Surplus Areas.

Except as otherwise provided in the preceding paragraph, the Seller shalldefend any suit or proceeding brought against the Buyer so far as based ona claim that any product, or any part thereof, furnished under this contract
constitutes an infringement of any patent of the United States, if notified
promptly in writing and given authority, information and assistance (at the
Seller's expense) for the defense of same, and the Seller shall pay all damages and costs awarded therein against the Buyer. In case said product, or
any part thereof, is in such suit held to constitute infringement and the useof said product or part is enjoined, the Seller shall, at its own expense,
either procure for the Buyer the right to continue using said product orpart, or replace same with non-infringing product, or modify it so it becomes

9-3

FAIRCHILD SALES OFFICESHUNTSVILLE, ALABAMA
2109 W. Clinton Bldg. 35805
Suite 420
Tel: 205·536-4428
TWX: 810·726·2217

BLADENSBURG, MARYLAND
5809 Annapolis Road, Suite 408
Bladensburg, Md .. 20710
Tel: 301·779·0954
TWX: 710·826·9654

SYRACUSE, NEW YORK
333 E. Onondaga Street
Syracuse, N.Y. 13202
Tel: 315-472-3391
TWX: 710·541·0499

PHOENIX, ARIZONA
301 West Indian School Rd. 85013
Suite 103
Tel: 602-264·4948
TWX: 910-951-1544

BOSTON, MASSACHUSEITS
167 Worcester Street
Wellesley Hills, Mass. 02181
Tel: 617-237·3400

DAYTON, OHIO
5055 North Main Street 45415
Suite 290
Tel: 513-278·8278
TWX: 810·459·1803

LOS ALTOS, CALIFORNIA
Village Corner, Suite L
El Camino and San Antonio Rds. 94022
Tel: 415-941-3150
TWX: 910-370-7952

DETROIT, MICHIGAN
24755 Five Mile Rd. 48239
Tel: 313-537·9520
TWX: 810-221·6936

JENKINTOWN, PENNSYLVANIA
100 Old York Road 19046
Tel: 215-886-6623
TWX: 510-665-1654

LOS ANGELES, CALIFORNIA
6922 Hollywood Blvd. 90028
Suite 818
Tel: 213-466-8393
TWX: 910-321-3009

MINNEAPOLIS, MINNESOTA
4901 W. 'i7th Street 55435
Room 104
Tel: 612-920·1030
TWX: 910-576-2944

DALLAS, TEXAS
10210 Monroe, Suite 102 75220
Tel: 214·352·9523
TWX: 910-861-4512

DENVER, COLORADO
2765 South Colorado Blvd. 80223
Suite 204
Tel: 303-757-7163
TWX: 910-935-0706
FT, LAUDERDALE, FLORIDA
3440 N.E. 12th Ave., Rm. 2 33308
Tel: 305-566-7414
TWX: 510-955-9840
ORLANDO, FLORIDA
7040 Lake Ellenor Dr., Rm.130 32809
Tel: 305-855-8012
TWX: 810-850-0152
ELMWOOD PARK, ILLINOIS
7310 West North Avenue 60635
Tel: 312·456-4200
TWX: 910-255-2064

ALBUQUERQUE, NEW MEXICO
Suite 1216
First National Bank, Bldg. E
5301 Central N.E.
Albuquerque, N.M. 87108
Tel: 505-265-5601
TWX: 910-989-1186
JERICHO, L. I., NEW YORK
50 Jericho Turnpike 11753
Tel: 516-334-8500
TWX: 510-222-4450
POUGHKEEPSIE, NEW YORK
44 Haight Avenue 12603
Tel: 914-454"7320
TWX: 510-248-0030

9.4

SEATTLE, WASHINGTON
700 108th Avenue Northeast
Suite 211
Bellevue, Washington 98004
Tel: 206-454-4946
TWX: 910-443-2318
ONTARIO OFFICE
P.O. Box 160
1040 Martin Grove Road
Rexdale, Ontario, Canada
Tel: 416-248-0285
TWX: 610-492-2700
QUEBEC OFFICE
1385 Mazurette street
Suite 3Montreal 355, Quebec, Canada
Tel: 514-382-2552

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