REVISIONSLTR

DESCRIPTIONDATEAPPROVEDA

Add AIN, AIN , CLK and CLK parameters toparagraph 1.3. Update document paragraphs toreflect current requirements. - ro

14-09-10

C. SAFFLE

B

Make clarification to Voltage difference limits as
specified under paragraph 1.3.
Update document paragraphs to current
requirements. - ro

20-05-27

J. ESCHMEYER

CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24

Vendor item drawing

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PMIC N/A

PREPARED BY
RICK OFFICER

Original date of drawing
YY-MM-DD

CHECKED BY
TOM HESS

06-12-22

DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
TITLE
MICROCIRCUIT, DIGITAL-LINEAR, 12-BIT,
500 MSPS, ANALOG-TO-DIGITAL CONVERTER,
MONOLITHIC SILICONAPPROVED BYRAYMOND MONNIN
SIZE

A
REV

CODE IDENT. NO.

DWG NO.

V62/07607

16236
B

PAGE

AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.

1

OF

20
5962-V022-20

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance 12-bit, 500 MSPS analog to digital converter
microcircuit, with an operating temperature range of -55C to +125C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/07607-

Drawing
number01

X

E

Device type
(See 1.2.1)

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic

01

Circuit function

ADS5463-EP

12 bit, 500 MSPS, analog to digital converter

1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

X80

MS-026

Package style
Plastic quad flat pack with thermal pad

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture:
Finish designator
A
B
C
D
E
F
Z

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Material
Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy (BGA/CGA)
Other

SIZE
A

CODE IDENT NO.
16236
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DWG NO.

V62/07607
PAGE2

1.3 Absolute maximum ratings.

1/

Supply voltage :AVDD5 to GND ..................................................................................................................... 6 V
AVDD3 to GND ..................................................................................................................... 5 V
DVDD3 to GND ..................................................................................................................... 5 V
Voltage difference between pin and ground:
AIN, AIN to GND: 2/
AC signal .......................................................................................................................... -0.3 V to (AVDD5 + 0.3 V)
DC signal, TJ = 105C ...................................................................................................... 0.4 V to 4.4 V
DC signal, TJ = 125C ...................................................................................................... 1.0 V to 3.8 V
Voltage difference between these pins:
AIN to AIN : 2/
AC signal .......................................................................................................................... -5.2 V to 5.2 V
DC signal, TJ = 105C ...................................................................................................... -4 V to 4 V
DC signal, TJ = 125C ...................................................................................................... -2.8 V to 2.8 V
Voltage difference between pin and ground:
CLK, CLK to GND: 2/
AC signal .......................................................................................................................... -0.3 V to (AVDD5 + 0.3 V)
DC signal, TJ = 105C ...................................................................................................... 0.1 V to 4.7 V
DC signal, TJ = 125C ...................................................................................................... 1.1 V to 3.7 V
Voltage difference between these pins:
CLK to CLK : 2/
AC signal .......................................................................................................................... -3.3 V to 3.3 V
DC signal, TJ = 105C ...................................................................................................... -3.3 V to 3.3 V
DC signal, TJ = 125C ...................................................................................................... -2.6 V to 2.6 V
Digital data output to GND ....................................................................................................... -0.3 V to DVDD3 + 0.3 V
Maximum junction temperature (TJ) ......................................................................................... +150C
Storage temperature range (TSTG) .......................................................................................... -65C to 150C
Electrostatic discharge (ESD) human body model (HBM) ........................................................ 2 kV

1/

2/

Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
Valid when supplies are within recommended operating range.

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1.4 Recommended operating conditions. 3/
Supplies:
Analog supply voltage (AVDD5) ............................................................................................ 4.75 V to 5.25 V
Analog supply voltage (AVDD3) ............................................................................................ 3 V to 3.6 V
Output driver supply voltage (DVDD3) .................................................................................. 3 V to 3.6 V
Analog input:
Differential input range ......................................................................................................... 2.2 VPP typicalInput common mode voltage (VCM) ..................................................................................... 2.4 V typical
Digital output: (DRY, DATA, OVR)
Maximum differential output load ......................................................................................... 10 pF typical
Clock input:
CLK input sample rate (sine wave) ...................................................................................... 20 MSPS to 500 MSPS
Clock amplitude, differential sine wave ................................................................................ 3 VPP typical
Clock duty cycle ................................................................................................................... 50 % typical
Operating free-air temperature range (TA) ............................................................................... -55C to +125C
1.5 Thermal characteristics. 4/

Parameter

Test conditions

Typical limits

RJA 5/

Soldered thermal pad, no airflow

23.7C/W

RJA 5/

Soldered thermal pad, 150 LFM airflow

17.8C/W

RJA 5/

Soldered thermal pad, 250 LFM airflow

16.4C/W

RJP 6/

Bottom of package (thermal pad)

2.99C/W______
3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
4/ Using 36 thermal vias (6 x 6 array).
5/

RJA is the thermal resistance from junction to ambient.

6/

RJP is the thermal resistance from junction to the thermal pad.

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2. APPLICABLE DOCUMENTSJEDEC Solid State Technology Association
JEDEC PUB 95 –Registered and Standard Outlines for Semiconductor Devices(Copies of these documents are available online at https://www.jedec.org.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Block diagram. The block diagram shall be as shown in figure 3.
3.5.4 Timing waveforms. The timing waveforms shall be as shown in figure 4.

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TABLE I. Electrical performance characteristics. 1/
Test

SymbolConditions 2/

Temperature,TA

Devicetype

LimitsMin

Resolution

Unit
Max

+25C

01

12 typical

Bits

+25C

01

2.2 typical

VPP

+25C

01

2.4 typicalV

Analog inputs section
Differential input range
Input common mode

VCM

Input resistance (dc)

Each input to ground

+25C

01

500 typicalInput capacitance

Each input to ground

+25C

01

2.5 typical

pF

Analog input
bandwidth (-3 dB)

Dependent on source impedance

+25C

01

2 typical

GHz

Common mode signal = 10 MHz

+25C

01

80 typical

dB

+25C

01

2.4 typicalV

Common mode
rejection ratio

CMRR

Internal reference voltage section
Reference voltage

VREF

Dynamic accuracy section
No missing codes

AssuredDifferential linearity
error

DNL

fIN = 10 MHz-55C to +125C

01

-0.95

0.95

LSB

Integral linearity
error

INL

fIN = 10 MHz-55C to +125C

01

-2.5

2.5

LSB

-55C to +125C

01

-11

11

mV

+25C

01

0.0005 typicalmV/C-55C to +125C

01

-5.2

5.2

%FS

+25C

01

-0.02 typical

%/C

+25C

01

85 typicaldB

Offset error
Offset temperature
coefficient
Gain error
Gain temperature
coefficientPower supply rejection
ratio

PSRR

100 kHz supply noise,see figure 5

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/

Temperature,TA

Devicetype

Limits
Min

Unit
Max

Power supply section
5 V analog supply
current

IAVDD5

3.3 V analog supply
current

IAVDD3

3.3 V digital supply
current

IDVDD3

Total power dissipation

PD-55C to +125C

01

365

mA

-55C to +125C

01

145

mA

-55C to +125C

01

92

mA

-55C to +125C

01

2.575

W

+25C

01

200 typicalsfIN = 10 MHz

+25C

01

65.3 typicaldBFS

fIN = 70 MHz+25C

65.4 typicalfIN = 100 MHz

+25C

63.5

-55C to +125C

63

VIN = full scale, fIN = 10 MHz,fS = 500 MSPS
VIN = full scale, fIN = 10 MHz,fS = 500 MSPS
VIN = full scale, fIN = 10 MHz,fS = 500 MSPS

Power up time
Dynamic AC characteristics section
Signal-to-noise ratio

SNR

65.1 typicalfIN = 230 MHz+25C

fIN = 300 MHz

+25C

63.25

-55C to +125C

61.75

fIN = 450 MHz+25C

64.6 typicalfIN = 650 MHz+25C

63.9 typicalfIN = 900 MHz+25C

62.6 typicalfIN = 1.3 GHz+25C

59.3 typicalSee footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/

Temperature,TA

Devicetype

Limits
Min

Unit
Max

Dynamic AC characteristics section - continued.
Spurious free dynamic
range

Second harmonic

SFDR

HD2

01

85 typicalfIN = 10 MHz+25C

fIN = 70 MHz+25C

82 typicalfIN = 100 MHz

+25C

70

-55C to +125C67

fIN = 230 MHz+25C

78 typicalfIN = 300 MHz

+25C

64

-55C to +125C62

fIN = 450 MHz+25C

75 typicalfIN = 650 MHz+25C

65 typicalfIN = 900 MHz+25C

56 typicalfIN = 1.3 GHz+25C

45 typicalfIN = 10 MHz+25C

fIN = 70 MHz+25C

fIN = 100 MHz-55C to +125C

fIN = 230 MHz+25C

fIN = 300 MHz-55C to +125C

fIN = 450 MHz+25C

80 typicalfIN = 650 MHz+25C

77 typicalfIN = 900 MHz+25C

66 typicalfIN = 1.3 GHz+25C

50 typical

01

dBc

87 typicaldBc

82 typical67
81 typical62.5

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/

Temperature,TA

Devicetype

Limits
Min

Unit
Max

Dynamic AC characteristics section – continued.
Third harmonic

Worst harmonic/spur(other than HD2 and
HD3)

HD3

HD3

01

85 typicalfIN = 10 MHz+25C

fIN = 70 MHz+25C

fIN = 100 MHz-55C to +125C

fIN = 230 MHz+25C

fIN = 300 MHz-55C to +125C

fIN = 450 MHz+25C

75 typicalfIN = 650 MHz+25C

65 typicalfIN = 900 MHz+25C

56 typicalfIN = 1.3 GHz+25C

45 typicalfIN = 10 MHz+25C

fIN = 70 MHz+25C

86 typicalfIN = 100 MHz+25C

86 typicalfIN = 230 MHz+25C

77 typicalfIN = 300 MHz+25C

81 typicalfIN = 450 MHz+25C

86 typicalfIN = 650 MHz+25C

85 typicalfIN = 900 MHz+25C

78 typicalfIN = 1.3 GHz+25C

67 typicaldBc

90 typical
67.5
90 typical
63

01

86 typicaldBc

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/

Temperature,TA

Devicetype

Limits
Min

Unit
Max

Dynamic AC characteristics section – continued.
Total harmonic
distortion

Signal-to-noise anddistortion

THD

SINAD

01

80 typicalfIN = 10 MHz+25C

fIN = 70 MHz+25C

79 typicalfIN = 100 MHz+25C

77 typicalfIN = 230 MHz+25C

75 typicalfIN = 300 MHz+25C

73 typicalfIN = 450 MHz+25C

73 typicalfIN = 650 MHz+25C

64 typicalfIN = 900 MHz+25C

55 typicalfIN = 1.3 GHz+25C

44 typicalfIN = 10 MHz+25C

fIN = 70 MHz+25C

fIN = 100 MHz-55C to +125C

fIN = 230 MHz+25C

fIN = 300 MHz-55C to +125C

fIN = 450 MHz+25C

64.1 typicalfIN = 650 MHz+25C

61.5 typicalfIN = 900 MHz+25C

55.4 typicalfIN = 1.3 GHz+25C

45.1 typical0165.2 typical

dBc

dBc

65.2 typical62
64.7 typical
58.75

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/

Temperature,TA

Devicetype

Limits
Min

Unit
Max

Dynamic AC characteristics section – continued.
Two-tone SFDR

Effective number of bits

ENOB

RMS idle channel
noise

01

90 typicalfIN1 = 65 MHz, fIN2 = 70 MHz,each tone at -7 dBFS

+25C

fIN1 = 65 MHz, fIN2 = 70 MHz,each tone at -16 dBFS

+25C

89 typicalfIN1 = 350 MHz, fIN2 = 355 MHz,each tone at -7 dBFS

+25C

82 typicalfIN1 = 350 MHz, fIN2 = 355 MHz,each tone at -16 dBFS

+25C

89 typical01

fIN = 100 MHz-55C to +125C

fIN = 300 MHz+25C

Inputs tied to common mode

+25C

01

9.9

dBc

Bits

10.4 typical
0.7 typicalLSB

Low voltage differential signaling (LVDS) digital outputs characteristics section
Differential output
voltage (  )

VOD

+25C

01

247

454

mV

Common mode output
voltage

VOC-55C to +125C

01

1.125

1.375

V

+25C

01

200 typicalps

Aperture jitter, rms

+25C

01

160 typicalfs

Latency+25C01

3.5 typical

CyclesTiming characteristics section
Aperture delay

3/tA

Clock periodtCLK-55C to +125C

01

2

ns

Clock pulse duration,
high

tCLKH

-55C to +125C

01

1

ns

Clock pulse duration,
low

tCLKL

-55C to +125C

01

1

ns

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/

Temperature,TA

Devicetype

LimitsMin

Timing characteristics section – continued.

Unit
Max

3/

CLK to DRY delay 4/tDRYZero crossing,
7 pF differential loading

+25C

01

1100 typicalps

CLK to DATA/OVR 4/
delay

tDATA

Zero crossing,
7 pF differential loading

+25C

01

1100 typicalps

DRY to DATA skew

tSKEW

tDATA - tDRY,
7 pF differential loading

+25C

01

0 typical

ps

DRY/DATA/OVR
rise time

tRISE

7 pF differential loading

+25C

01

500 typicalps

DRY/DATA/OVR
fall time

tFALL

7 pF differential loading

+25C

01

500 typicalps1/

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance overthe specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.

2/

Unless otherwise specified, sampling rate = 500 MSPS, 50 % clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,-1 dbFS differential input, and 3 VPP differential clock.

3/

Timing parameters assured by design or characterization, but not production tested.

4/

DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine thedata propagation delay.

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Case XFIGURE 1. Case outline.

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Case X - continued

Dimensions
InchesSymbolMillimeters

Min

Max

Min

Max

A

---

0.047

---

1.20

A1

0.037

0.041

0.95

1.05

A2

0.009

---

0.25

---

A3

0.001

0.005

0.05

0.15

b

0.006

0.010

0.17

0.27

c

0.005 nominal

0.13 nominal

D

0.543

0.559

13.80

14.20

D1

0.464

0.480

11.80

12.20

D2

0.037

---

0.95

---

e

0.019 BSC

0.50 BSC

E

0.543

0.559

13.80

14.20

E1

0.464

0.480

11.80

12.20

E2

0.037

---

0.95

---

L

0.017

0.029

0.45

0.75

NOTES:
1. Controlling dimensions are millimeter, inch dimensions are given for reference only.
2. Body dimensions do not include mold flash or protrusion.
3. This package is designed to be soldered to a thermal pad on the board. Refer to technical brief, power pad thermallyenhanced package, manufacturer’s literature number SLMA002 for information regarding recommended board layout.
The vendor datasheet is available from the manufacturer.
4. Falls within JEDEC MS-026.

FIGURE 1. Case outline – continued.

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Device type

01

Case outline

X

Terminal
numberTerminal
symbolTerminal
numberTerminal
symbolTerminal
numberTerminal
symbolTerminal
numberTerminal
symbol

1

DVDD3

21

AVDD5

41

OVR

61

D4

2

GND

22

GND

42

OVR

62

D4

3

AVDD5

23

AVDD5

43

NC

63

D5

4

NC

24

GND

44

NC

64

D5

5

NC

25

AVDD5

45

NC

65

GND

6

VREF

26

GND

46

NC

66

DVDD3

7

GND

27

AVDD5

47

NC

67

D6

8

AVDD5

28

GND

48

NC

68

D6

9

GND

29

RESERVED

49

NC

69

D7

10

CLK

30

GND

50

NC

70

D7

11

CLK

31

AVDD5

51

DVDD3

71

D8

12

GND

32

GND

52

GND

72

D8

13

AVDD5

33

RESERVED

53

D0

73

D9

14

AVDD5

34

GND

54

D0

74

D9

15

GND

35

AVDD3

55

D1

75

D10

16

AIN

36

GND

56

D1

76

D10

17

AIN

37

AVDD3

57

D2

77

D11 (MSB)

18

GND

38

GND

58

D2

78

D11 (MSB)

19

AVDD5

39

AVDD3

59

D3

79

DRY

20

GND

40

GND

60

D3

80

DRY

NC = No connection

FIGURE 2. Terminal connections.

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Terminal symbol

Description

AIN

Differential input signal (positive).

AIN

Differential input signal (negative).

AVDD5

Analog power supply (5 V).

AVDD3

Analog power supply (3.3 V). (Suggestion for  250 MSPS: leave
option to connect to 5 V for ADS5440/4 compatibility).

DVDD

Output driver power supply (3.3 V).

GND

Ground.

CLK

Differential input clock (positive).
Conversion initiated on rising edge.

CLK

Differential input clock (negative).

D0, D0
D1 – D10, D1 - D10

LVDS digital output pair, least-significant bit (LSB).
LVDS digital output pairs.

D11, D11

LVDS digital output pair, most significant bit (MSB).

DRY, DRY

Data ready LVDS output pair.

NC

No connect. Pins 4 and 5 should be left floating, pins 43 – 50 are
possible future bit additions for this pin out and therefore can beconnected to a digital bus or left floating.

OVR, OVROver range indicator LVDS output. A logic high signals an analog
input in excess of the full-scale range.

RESERVEDPin 29 reserved for possible future VCM output for this pinout; pin 33 isreserved for possible future power down control pin for this pinout.

VREF

Reference voltage.

FIGURE 2. Terminal connections – continued.

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

B

DWG NO.

V62/07607
PAGE

16

FIGURE 3. Block diagram.

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

B

DWG NO.

V62/07607
PAGE

17

FIGURE 4. Timing waveforms.

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

B

DWG NO.

V62/07607
PAGE

18

FIGURE 5. PSRR versus supply injected frequency.

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

B

DWG NO.

V62/07607
PAGE

19

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/Programs/Smcr/.

Vendor item drawing
administrative control
number 1/

Devicemanufacturer
CAGE code

Package 2/
lead

Mode oftransportationand quantity

Packagemarking

Vendor part number

V62/07607-01XE

01295

HTQFP-80(thermal pad)Tray, 96

ADS5463MEPADS5463MPFPEP

1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering
documentation.
2/ Thermal pad size: 9.5 mm x 9.5 mm ( 0.374 inch ) minimum, 10 mm x 10 mm ( 0.393 inch ) maximum.

CAGE code

Source of supply

01295

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REV

B

DWG NO.

V62/07607
PAGE

20