電気学会論文誌●（●●●●●●●部門誌）
IEEJ Transactions on ●●●●●●●●●●●●●●●
Vol.●● No.● pp.●-●●
DOI: ●.●●/ieejeiss.●●.●

Paper

Microcomputer-based Discontinuous PWM for
DC-link Current Harmonic Reduction in Three-phase VSIs
Koroku Nishizawa＊, Student member, Jun-ichi Itoh＊a), Senior member
Akihiro Odaka＊＊, Member, Akio Toba＊＊, Senior member, Hidetoshi Umida＊＊, Fellow(Manuscript received Jan. 00, 20XX, revised May 00, 20XX)
This paper proposes a novel discontinuous pulse width modulation (DPWM) strategy to reduce the switching-frequency-orderDC-link current harmonics for a two-level three-phase voltage source inverter (VSI). The proposed modulation method realizes along lifetime of the smoothing capacitor to the motor drive system. Furthermore, the proposed strategy requires only one carrier;thus, high cost hardware such as field-programmable gate arrays are unnecessary. The DC-link current harmonics are reduced byshifting two unclamped modulating signals in every half control period. In addition, the injection of the zero sequence signal to all
discontinuous modulating signals optimizes the phase of the clamped modulating signal and its clamped value according to theconditions of the output phase currents; consequently, the DC-link current harmonics are reduced even when the load power factor
varies. Experiments confirm that the proposed DPWM strategy can reduce the DC-link current harmonics by a maximum of 18.3%
at a modulation index of 0.705 and a load power factor of 0.819.
Keywords : Two-level voltage source inverter, Discontinuous PWM, DC-link capacitors, DC-link current harmonics

1.

harmonics are reduced by comparing only one certain phasemodulating signal with the inverse triangular carrier and comparing
the other two modulating signals with the original triangular carrier.
However, this method leads to a constraint of the digital hardware
due to the generation of the inverse triangular carrier. Furthermore,when the load power factor becomes lower than 0.866, the DC-linkcurrent harmonics cannot be reduced by these methods.
As another approach to minimize the DC-link current harmonics,
a new space vector PWM (SVPWM) has been proposed(15). In thisSVPWM, the optimized voltage space vectors for the DC-linkcurrent harmonic reduction are selected on the basis of the detected
output phase current directions to adapt to the variation of the load
power factor. However, the employment of this SVPWM also leads
a constraint of the digital hardware such as FPGA because the
SVPWM not only compares the on-duties of the selected output
voltage space vectors with single carrier but also decides the gating
signals based on the carrier comparison results to realize theoptimized combinations of the voltage space vectors.
This paper proposes a novel carrier-comparison DPWM whichuses only one carrier to reduce the switching-frequency-order DClink current harmonics of VSI and eliminates the need of thecomplex digital hardware. In other words, the proposed DPWM issimply implemented with the general-purpose microcomputer
without additional digital hardware. In order to reduce the DC-linkcurrent harmonics by using just only one carrier, two unclamped
phase modulating signals of the conventional DPWM are optimallyshifted in every half control period. Furthermore, the injection of
the zero sequence signal to all discontinuous modulating signals
optimizes the phase of clamped modulating signal and its clamped
value according to the conditions of the output phase currents;
consequently, the DC-link current harmonics are reduced evenwhen the load power factor varies.
This paper is organized as follows; first, the reduction method ofIntroduction

Three-phase AC motors are widely utilized in widespread
applications such as traction and automotive and so on(1)–(7).
Recently, lifetime extension of such system has been actively
researched(8)–(12). Generally, electrolytic capacitors are applied in
the DC-link of the PWM inverter as a smoothing capacitor. The
smoothing capacitor acts as an energy buffer to stabilize the DClink voltage and guarantees a dynamic performance of the system
by suppressing an overshoot voltage during a transient state. These
functions are realized by using bulky electrolytic capacitors whichmake the system large and less reliable.
The DC-link capacitors absorb large switching-frequency
harmonics contained in the PWM inverter DC-link current, leading
joule losses in the equivalent series resistance (ESR) of thecapacitors. The internal heating considerably worsens the capacitor
reliability according to the Arrhenius equation(13). There are several
methods to extend the lifetime of the smoothing capacitor. One of
the approaches is the application of film capacitors instead of theelectrolytic capacitor as the smoothing capacitor(14). However, thismethod makes the system larger due to its low energy density.
Meanwhile, it is also possible to extend the lifetime of thesmoothing capacitor by reducing the DC-link current harmonics of
VSI. So far, numerous modulation methods of VSI, which reduce
the DC-link current harmonics of VSI, have been also proposed(8)–(10), (15). In (8)–(10), double carriers, two inverted triangular carriers,
are used as a double-carrier-comparison pulse width modulation(PWM). In these modulation methods, the DC-link currenta) Correspondence to: Jun-ichi Itoh.
E-mail: itoh@vos.nagaokaut.ac.jp＊
Nagaoka University of Technology.
1603-1, Kamitomioka-machi, Nagaoka, Niigata, Japan 940-2188＊＊
Fuji Electric Co., Ltd.
1, Fuji-machi, Hino, Tokyo, Japan 191-8502© 200● The Institute of Electrical Engineers of Japan.

1Discontinuous PWM for DC-link Current Harmonic Reduction (Koroku Nishizawa et al.)

1.2
1.2 *
*
*
vu.DPWM
vv.DPWM
vw.DPWM
1
1.0
*
*
*
0.8
vu.CPWM
vv.CPWM
vw.CPWM
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0.0
-0.20.2
-0.4
0.4
-0.6
*
voffset
0.6
-0.8
0.8
-11.0
-1.2
00 30
60 0.005
90
120
150 0.01
180
210
2400.015
270
300
330 0.02360
1.2 0.0016667
0.0033333
0.0066667
0.0083333
0.0116667
0.0133333
0.0166667
0.0183333
50 deg.
2πft [deg.](zoomed at Fig. 3 and Fig. 4)

iC
+

Cdc

Sup

Swp

Svp
u

o

Edc

Cdc

v
w

+

Sun

Fig. 1.

Svn

iu
iv vuv
iw vvw

Modulation waves [-]iDC.in.ave iDC.in
Motor
load
n
vwu

Swn

g

Three-phase two-level VSI with motor load.

the DC-link current harmonics by using the novel modulating
signals of the DPWM is introduced. Next, the mechanism to adapt
the variation of the load power factor is explained. Then, theperformances on the input current harmonics, the output current
harmonics and the inverter efficiency are compared between theconventional and proposed DPWM by analysis and experiment.
Finally, the electrolytic capacitor lifetimes with those DPWM are
estimated and compared.

2.

Fig. 2. Modulating signals of CPWM, conventional DPWM
and its injected zero sequence signal at m = 0.8.
1

v*u.DPWM
v*v.DPWM

Proposed PWM method to reduce DC-linkcurrent harmonics of VSIs

su
sv
sw


 1, (Sxp : ON, Sxn : OFF)sx  
, ( x  u, v, w). ............. (1) 0, (Sxp : OFF, Sxn : ON)

iDC.inFig. 2 shows the modulating signals of the continuous PWM(CPWM), conventional DPWM and its injected zero sequencesignal at the modulation index of 0.8. The discontinuous
modulating signals are obtained by injecting the zero sequencesignal v*offset into the continuous modulating signals as(16):***v  max[vu .CPWM , vv.CPWM , vw.CPWM ]and  max,*** vmin  min[vu .CPWM , vv.CPWM , vw.CPWM ]*v*x.DPWM  v*x.CPWM  voffset,

V0 (0 0 0)V1
iu+iv
iu

V2 (1 1 0)

V1 (1 0 0) V0iDC.in.ave

TsFig. 3.
Zoomed-in waveforms of modulating signals of
conventional DPWM, switching functions and DC-link current
at m = 0.8, 2πft = 50 deg., cos φ = 1.

 vu*.CPWM  m  cos  2 ft  *
 vv.CPWM  m  cos  2 ft  2 3 , .................................... (2)v * w.CPWM  m  cos  2 ft  2 3
if vmax  vmin
if vmin ＜ vmax*
vw.DPWM-1

2.1 Conventional Discontinuous PWM
Fig. 1 shows athree-phase two-level VSI with a motor load. This circuit consistsof three legs. If IGBTs are treated as ideal switches, the conduction
status of any one leg can be represented by binary switching
functions: 1  vmax*
voffset
1  vmin

Triangular carrieran average value of the DC-link current. These area correspond to
the root-mean-square (RMS) value of the DC-link capacitor current
based on the geometrical difference between the RMS value of theDC-link current iDC.in.RMS and the average value of the DC-linkcurrent iDC.in.ave as follows:2
2
iC .RMS Ts   iDC.in. RMS Ts   iDC .in .ave............... (3)
1 Ts 2iDC .in dt ........................ (6)iDC .in. RMS Ts  
Ts 0

and 
,
3

iDC .in.ave  4 m  I m cos  x  u, v, w , ......................... (4)where m is the modulation index.
Fig. 3 shows the zoomed-in waveforms of the modulating signalsof the conventional DPWM, the three-phase switching functions
and the DC-link current at the modulation index of 0.8, the phaseangle of 50 degrees and the unity load power factor. The
instantaneous value of the DC-link current is a superpositionsummation of the switched current pulses from each phase leg andcalculated as(17):iDC .in    sx  ix . ....................................................... (5)where Ts is the control period, Im is the maximum value of the output
phase current and φ is the load power factor angle. Note that asmaller fluctuation of the DC-link current around its average value
results in a smaller RMS value of the DC-link capacitor current(18).
In cases where the conventional DPWM is applied, the center of thegate pulses are matched to the center of the control period, leading
a long overlap period of the gate pulses. This results in a large
fluctuation of the DC-link current around its average value, i.e. thehigh DC-link capacitor current harmonics.
2.2
Microcomputer-based Approach to Reduce
Harmonics
Fig. 4 shows the zoomed-in waveforms of thex u ,v, w

The shaded areas in the DC-link current waveform indicates thetime integral of the difference between the instantaneous value and
2

IEEJ Trans. ●●, Vol.●●, No.●, ●●●Discontinuous PWM for DC-link Current Harmonic Reduction (Koroku Nishizawa et al.)modulating signals of the proposed DPWM, the three-phaseswitching functions and the DC-link current at the modulationindex of 0.8, the phase angle of 50 degrees and the unity load power
factor. The operation of the proposed DPWM changes
corresponding to the load power factor. In this section, the load
power factor is considered as unity. The basic concept of the
proposed DPWM for the DC-link current harmonic reduction is toshorten the zero-vector period, i.e. period where (su sv sw) = (0 0 0)or (1 1 1), during the control period, leading to the reduction of theDC-link current fluctuation around its average value. Therefore, thebasic concept of the proposed DPWM is similar to that of theconventional DC-link current harmonic reduction SVPWM
method(15). In the proposed DPWM, this concept is realized under
the premise that the modulating signals can be updated at positive
and negative peaks of the triangular carrier, which is constraint of
the microcomputer. In order to adjust the gate pulse positions asshown in Fig. 4, only two unclamped phase modulating signals
v*u.DPWM and v*v.DPWM should be updated, whereas the clamped
modulating signal v*w.DPWM does not change. Each proposed
modulating signal is generated by shifting the unclamped original
DPWM modulating signal as:*
vxp  1 **vxn  2  vx.DPWM  1

 if v**vxp  2  vx.DPWM  1 *vxn  1

 if v*x . DPWM*
x . DPWM

0*
vu.DPWM*
vv.DPWM*
vw.DPWM
-1

v*un
v*vn

vw*

sv
sw
V3 (0 1 0)
iu+iv

V2 (1 1 0)

V1 (1 0 0)iu

iDC.iniDC.in.ave

iv

TsFig. 4.
Zoomed-in waveforms of modulating signals of
proposed DPWM, switching functions and DC-link current
at m = 0.8, 2πft = 50 deg., cos φ = 1.

Table 1.

Sector definitions of proposed DPWM.

Current polarity
Optimized clamped value
KOCV
Sector (P: Positive, N: Negative)
iv
iw
Driving Reg. Braking
iu
A
P
N
N
1
–1
B
P
P
N
–1
1
C
N
P
N
1
–1
D
N
P
P
–1
1
E
N
N
P
1
–1
F
P
N
P
–1
1

........................... (7)0 ,where v*xp is the positively-shifted modulating signal, and v*xn is thenegatively-shifted modulating signal. Note that the overlap period
between two unclamped phases’ switching functions, su and sv in
Fig. 4, should be shortened to reduce the fluctuation of the DC-linkcurrent around its average value. Therefore, these two phasemodulating signals are alternately shifted to the positive side.
Besides, the averaged values of the shifted modulating signals ineach control period are same as those of the original signals,
whereas the pulse widths of the switching functions areunchanged(19).
However, note that the reduction effect on the DC-link current
harmonics by the use of the shifted modulation signals is dependent
on the load power factor because the instantaneous value of the DClink current is also dependent on the output phase currents. Thus, itis necessary to deal with the wide variation of the load power factor,
which is a typical requirement of the motor drive system.
2.3 Adaption to Wide Load Power Factor Range
Table 1 lists the sector definition of the load current conditions.
These sectors are determined by the combination of the detected
output phase current directions.
Fig. 5 shows the conventional and proposed discontinuous
modulating signals at the modulation index of 0.8 and the load
power factor of 0.966 (15 deg. lagging). In order to reduce the DClink current harmonics at any condition of the load power factor,
first, three conventional discontinuous modulating signals v*x.DPWM(x = u, v, w) are added with the offset v*offset.2 to obtain the voltage
reference with the offset v*x.PDPWM as:

Proposed Sector
E
D
C

B

A
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
0
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2

F
A

Output phase currents
iv
iw

iu

0

Modulating signals of conventional DPWM***
vu.DPWM
vv.DPWM
vw.DPWM
0.00 166 67

0.00 333 33

0.00 50.00 666 67

0.00 833 33

0.01

0.01 166 67

0.01 333 33

0.00 166 67

0.00 333 33

0.00 5*Adding offset voffset.2

0.01 50.01 666 67

0.01 833 33

0.02

0.01 50.01 666 67

0.01 833 33

0.02

0

1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2

0

0.00 666 67

0.00 833 33

0.01

0.01 166 67

0.01 333 33

0

0

1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2

*
Modulating signals with voffset.2
at  = 15 deg.
**
vu.PDPWM
vw.PDPWM
v*v.PDPWM
0.00 166 67

0.00 333 33

0.00 50.00 666 67

0.00 833 33

0.01

0.01 166 67

0.01 333 33

0.01 50.01 666 67

0.01 833 33

0.02

0

1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2

Mod. signals of proposed DPWM at  = 15 deg.
vu*
vw*
v*v
0

0.00 166 67

0.00 333 33

0.00 50.00 666 67

0.00 833 33

0.01

0.01 166 67

0.01 333 33

0.01 50.01 666 67

0.01 833 33

0.02

0

0.00 166 67

0.00 333 33

0.00 50.00 666 67

0.00 833 33

0.01

0.01 166 67

0.01 333 33

0.01 50.01 666 67

0.01 833 33

0.02

0

0

45

105

165

225

285

345 3602πft [deg.]

Fig. 5. Proposed modulating signals at m = 0.8 cos φ = 0.966(15 deg. lagging). v*x.PDPWM is generated by adding an offset
v*offset.2 to v*x.DPWM to maintain the clamped period of themodulating signal at each proposed sector. The proposed
modulating signals are then generated by shifting two unclamped
modulating signals of v*x.PDPWM in every half control period.

*
v*x. PDPWM  v*x. DPWM  voffset.2

 KOCV  vu*. DPWM
**and voffset.2   K OCV  vv. DPWM*
K
 OCV  vw. DPWM

*
vup

su




v*vp
Triangular carrier1

if sector = A,D........... (8)if sector = B,E
if sector = C,F

3

IEEJ Trans. ●●, Vol.●●, No.●, ●●●Discontinuous PWM for DC-link Current Harmonic Reduction (Koroku Nishizawa et al.)

where KOCV is the optimized clamped value of the modulating signal
in each proposed sector listed in Table 1. The offset value v*offset.2 isoptimized according to the conditions of the output phase currents
and the clamped phase of the modulating signals. In the case of
sector B, for example, where iu and iv are positive and iw is negative,
w-phase switching function sw must be zero to obtain the minimum
fluctuation of the DC-link current around its average value. If sw
becomes 1 during the sector B, the instantaneous value of the DClink current becomes negative, which leads to a large fluctuation,i.e. the large increase in the DC-link current harmonics. Next, two
unclamped offset-added modulating signals v*x.PDPWM are shiftedbased on the sub-section 2.2, resulting in the proposed modulating
signals v*x. With this optimization for the clamped phase and its
value of the modulating signal based on the load current conditions,the DC-link current harmonics is reduced even when the load power
factor varies(19).
In case of the regenerative braking mode, the average value of
the DC-link current become a negative value. Therefore, theoptimized clamped value KOCV of the modulating signal for the
reduction of the DC-link current fluctuation around its averagevalue in each proposed sector is reversed between driving andregenerative braking modes as listed in Table 1. Note that whether
the motor operating mode is driving or regenerative braking can bedetected from the polarity combinations of the modulating signals
and the detected output phase currents(15). In addition, the shiftingof the other two unclamped offset-added modulating signals inevery half control period is also performed in the case ofregenerative braking mode as the driving mode.
Fig. 6 shows the conventional and proposed discontinuous
modulating signals at the modulation index of 0.8 and the load
power factor of 0.707 (45 deg. lagging). In the case where the load
power factor is lower than 0.866 (φ < 30 deg.), the proposed offsetadded modulating signals v*x.PDPWM might be more than 1 or lower
than -1 due to the addition of the offset v*offset.2 in each sector,
leading an overmodulation operation. Therefore, the conventional
DPWM is applied in these periods as shown in the gray-coloredperiods in Fig. 6. Accordingly, the phase of the clamped modulating
signal is not optimized for the reduction of the DC-link current
harmonics; thus, the modulating signal shift in every half control
period are not performed in these periods.

1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2

iu

Output phase currents
iv
iw

0

F

E

Modulating signals of conventional DPWM***
vu.DPWM
vv.DPWM
vw.DPWM

00.00 166 67

0.00 333 33

0.00 500.00 166 67

0.00 333 33

0.00 5

1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2

0.00 666 67

0.00 833 33

0.01

0.01 166 67

0.01 333 33

0.01 50.01 666 67

0.01 833 33

0.02

0.01 50.01 666 67

0.01 833 33

0.02

0

1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2

*
Adding offset voffset.2
0.00 666 67

0.00 833 33

0.01

0.01 166 67

0.01 333 33

0

0

1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2

*
Modulating signals with voffset.2
at  = 45 deg.
**
vu.PDPWM
vw.PDPWM
v*v.PDPWM
0.00 166 67

0.00 333 33

0.00 50.00 666 67

0.00 833 33

0.01

0.01 166 67

0.01 333 33

0.01 50.01 666 67

0.01 833 33

0.02

0

0

1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2

Mod. signals of proposed DPWM at  = 45 deg.
vu*
vw*
v*v
Applying conv. DPWM
0.00 166 67

0.00 333 33

0.00 50.00 666 67

0.00 833 33

0.01

0.01 166 67

0.01 333 33

0.01 50.01 666 67

0.01 833 33

0.02

0.00 166 67

0.00 333 33

0.00 50.00 666 67

0.00 833 33

0.01

0.01 166 67

0.01 333 33

0.01 50.01 666 67

0.01 833 33

360

0

0

0 15

75

135

195

255

315

0.02

2πft [deg.]

Fig. 6. Proposed modulating signals at m = 0.8 cos φ = 0.707(45 deg. lagging). In gray-colored periods, the conventional
DPWM are applied to avoid the overmodulation operation due tothe addition of v*offset.2.
0.5
0.45
0.4
0.35

0.8

0.3
0.6

0.25
0.2

0.4

0.15

IC.RMS (p.u.) [p.u.]

Modulation index m [-]

1

0.1

0.2

0.05
0
0

Analytical Evaluations

20

40

60

80 100 120 140 160 180

0Load power factor angle  [deg.](a) Conventional DPWM.

3.1 DC-link Capacitor RMS Current
As explained in
the sub-section 2.1, the RMS value of the DC-link capacitor current
is dependent on m, φ and the switching patterns. The DC side of thethree-phase VSI operates at sixfold fundamental frequency; hence,
the normalized DC-link capacitor RMS current can be calculated
based on (6) by considering only a sixth of the fundamental period:

0.5
0.45

Modulation index m [-]

1


2
1 3 3   tx
I C.RMS  p.u.     iDC.in. x  iDC .in.ave    d ... (9)I m  0   Tswhere tx is the ON duty of a VSI voltage space vector Vx (su, sv, sw)
within Ts, and iDC.in.x is the instantaneous DC-link current value withthis voltage space vector Vx.
Fig. 7 shows the analytical results of the DC-link capacitor
current with regard to the modulation index m and the load power
factor angle φ. It can be seen from Fig. 7 that the proposed DPWM
performs better in terms of the DC-link capacitor RMS current
compared to the conventional DPWM under any cases of m and φ.

0.4
0.35

0.8

0.3
0.6

0.25
0.2

0.4

0.15
0.1

0.2

0.05
0
0

20

40

60

80 100 120 140 160 180

0Load power factor angle  [deg.](b) Proposed DPWM.

Fig. 7.
4

Analytical results of DC-link capacitor RMS current.
IEEJ Trans. ●●, Vol.●●, No.●, ●●●IC.RMS (p.u.) [p.u.]

3.

A

Proposed Sector
D
C
B

F

Discontinuous PWM for DC-link Current Harmonic Reduction (Koroku Nishizawa et al.)The characteristic to reduce the harmonic components in the DClink capacitor current is same between driving and regenerative
braking modes. In addition, a higher load power factor absolutevalue |cos φ| leads to a greater reduction effect on the DC-link
capacitor RMS current, because the application ratio of the
proposed discontinuous modulating signals becomes higher as the|cos φ| is higher. The power factor variation range of the motor loads
is dependent on the applications; e.g., the rated speed and rated
torque conditions are mainly used in the fan or pump applications,whereas any speed and torque conditions are expected in the
traction applications such as train and electric vehicle. Furthermore,
the load power factor is also dependent on the motor type such as
IM or PMSM. The actual effect on the DC-link capacitor RMS
current reduction could be estimated by using this analytical resultswith the consideration of the expected operating conditions andtheir occurrence frequencies in each certain application.
3.2 Load Current Quality
Since the switchingfrequency harmonics in the output voltage and output current of
VSI have a critical role in the generation of the motor copper losses,
the torque ripple of the test motor and the phase current total
harmonic distortion (THD), the switching frequency harmonic
characteristic of VSI is important to determine the performance ofthe modulation method. In this paper, the concept of the harmonicflux(20) is used as an evaluation method for the load current quality
characterized by the modulation method. This concept does not
require the calculation of the harmonic spectrum of the inverter
output voltage waveform, which is complicated for the proposed
DPWM because of its gate pulse asymmetry in the carrier cycle.
Assuming the switching frequency model of the load induction
motor as an inductance L, a harmonic load current vector Ih is
proportional to a harmonic flux vector λh, which is the time integralof the instantaneous error voltage vector, N 1Ts V - V  dt  
*

k

NTs

 N 1Ts
NTsλhRMS 

3

1

λ
 
3
0

2

0

h

0

V2

λh

3

V3

1

V2
V3h

V2h
-V0h = V*

V2h-V0h = V*

V1h

V0

V1h

V1

V1

(a) Conventional DPWM.

(b) Proposed DPWM.

Fig. 8. Harmonic flux trajectories at m = 0.8, 2πft = 50 deg
under same switching frequency.
0.3
0.25

0.8

0.2

0.6

0.15

0.4

0.1

0.2

0.05

0
0

RMS [-]

Modulation index m [-]

1

20

40

60

80 100 120 140 160 180

0Load power factor angle  [deg.](a) Conventional DPWM.

0.3

Vkh dt ............... (10)1Modulation index m [-]where Vk (k = 0~7) is the output voltage space vector of the 2-level
VSI, V* is the voltage reference vector, and Vkh is the instantaneous
error voltage vector.
Fig. 8 shows the harmonic flux trajectories with the conventional
and proposed DPWM at the modulation index of 0.8, and the phaseangle of 50 deg., under the same analytical conditions as in Figs. 3
and 4. The calculation of (10) and Fig. 8 visualize and evaluate theripple current on a per-carrier cycle base. Since the harmonic flux
vector characteristic has six-fold space symmetry, the perfundamental cycle (per 60 deg. in space) harmonic flux RMS value,
which characterizes the load current quality and the harmonic losses
in the test motor, is calculated as follows:


1
0

0.25

0.8

0.2

0.6

0.15

0.4

0.1

0.2

0.05

0
0

RMS [-]λ h  LIh  

2

1
2

20

40

60

80 100 120 140 160 180

0Load power factor angle  [deg.](b) Proposed DPWM.

dd .d . ..........................................(11)Fig. 9.

Fig. 9 shows the analytical results of the harmonic flux RMS
values with regard to the modulation index and the load power
factor angle under the same switching frequency. In case of theconventional DPWM, the modulating signals are only dependent on
the modulation index. Therefore, λRMS obtained with theconventional DPWM is variable by only the modulation index.
Nevertheless, in case of the proposed DPWM, the modulating
signals are varied to reduce the DC-link capacitor RMS current withregard to m and φ. Furthermore, Figs. 8 and 9 confirm that the
proposed DPWM leads to a larger λRMS compared to theconventional DPWM. Note that the distance between the

Comparison of harmonic flux RMS values.

trajectories and the origin, initial value of λh at the beginning of thecarrier cycle, is equal to the magnitude of the harmonic flux(20). The
proposed discontinuous modulating signals result in the applicationof the voltage space vector which is not the closest to V*, i.e. V3 in
Fig. 8. On the other hand, only voltage space vectors which are theclosest to V* are employed in the conventional DPWM. Therefore,
the proposed DPWM leads to worse λRMS. Fig. 9 also confirms thata higher |cos φ| leads to a larger λRMS, of which characteristics areopposite of the DC-link capacitor RMS current reduction effectshown in Fig. 7.
5

IEEJ Trans. ●●, Vol.●●, No.●, ●●●Discontinuous PWM for DC-link Current Harmonic Reduction (Koroku Nishizawa et al.)00*vu.DPWM[2.0 -/div.]

vuv [500 V/div.]

vu* [2.0 -/div.]

vuv [500 V/div.]

0

+Edc

Dead-time
width

0
0

0

0

iDC.in [20 A/div.]

iDC.in [20 A/div.]

iu [20 A/div.]–Edc

iu [20 A/div.]00[10 ms/div.]

Ts[10 ms/div.](a) Conventional DPWM.

(b) Proposed DPWM.

Fig. 10. Experimental waveforms at m = 0.705, cos φ = 0.819 (35 deg. lagging), i.e. driving mode; u-phase modulating signal, output
line-to-line voltage, DC-link current and output phase current. The zoomed-in waveform of vuv is from the simulation model using PLECS.
100

20.9 %

IDC.in(p.u.) = 0.412 [p.u.]

Input current [%]Input current [%]

100
10
1
0.1

0.01
0.001
0.001
10

100

1000

10000

1
0.1

0.01
0.001
0.001
10

100000IDC.in(p.u.) = 0.336 [p.u.] 15.4 %

10

100

1000

10000

Frequency [Hz]Frequency [Hz](a) Conventional DPWM.

(b) Proposed DPWM.

100000Fig. 11. Harmonic components of DC-link current at m = 0.705, cos φ = 0.819 (35 deg. lagging), i.e. driving mode (under same conditions
as in Fig. 10).

4.

under the same conditions as in Fig. 10. Note that 100% of thevertical axis indicates the maximum value of the output phasecurrent. The application of the proposed DPWM reduces theswitching frequency component of the DC-link current by 5.49
points.
Fig. 12 shows the measured DC-link current harmonics withregard to the modulation index and load power factor in driving
mode. The DC-link current harmonics is evaluated as the RMS
value of the DC-link current, which is normalized by the maximum
value of the output phase current as:

Simulation and Experimental Results

The performance of the proposed DPWM is verified
experimentally. In this experiment, a three-phase induction motor(MVK8115A-R, Fuji Electric Co. Ltd.) of which rated power is
3.7 kW is used as the test motor. The test motor is driven by thethree-phase 2-level VSI, composed of IGBT power module(7MBP50RA120, Fuji Electric Co. Ltd.) and operated at theswitching frequency of 10 kHz. The VSI is controlled by V/f control
with the conventional and proposed DPWM, which are
implemented into an evaluation board (TMS320C6713, Texas
Instruments). The load power factor is varied by controlling thetorque reference of the load motor.
4.1 DC-link Current Harmonics
Fig. 10 shows theoperating waveforms of VSI with the conventional and proposed
DPWM at a modulation index of 0.705, and a load power factor of
0.819 (35 deg. lagging), i.e. driving mode. Under this load power
factor condition, the application interval of the proposed DPWM islong; however, the conventional DPWM is also partially applied.
Fig. 10 confirms that the width of the step change in the DC-linkcurrent is reduced by an application of the proposed DPWM. On
the other hand, the larger transitions between +Edc and –Edc seem tooccur in the output line-to-line voltage with the proposed DPWM
due to the application of the voltage space vector which is not theclosest to V*. However, the zoomed-in waveform of vuv shown in
Fig. 10(b) confirms that the instantaneous voltage transition
between +Edc and –Edc never occurs due to the dead-time period.
Therefore, the proposed DPWM does not increase the motor surge
voltage in practice compared to the conventional DPWM.
Fig. 11 shows the harmonic components of the DC-link current

I DC .in (p.u.) 

1
Im

 i
n 1

DC .in. RMS . n2.................................... (12)where n is the harmonic order and iDC.in.RMS.n is the RMS value ofthe n-order DC-link current harmonics component. The harmoniccomponents of the DC-link current up to 20th-order of the switchingfrequency are considered in this evaluation. Fig. 12 confirms thatthe DC-link current harmonics is reduced under any modulationindex and load power factor conditions. In addition, it is also
confirmed that higher load power factor leads to a greater DC-linkcurrent harmonics-reduction effect with the proposed DPWM.
Fig. 13 shows the operating waveforms of VSI at the modulationindex of 0.445, and the load power factor of –0.766 (140 deg.
lagging), i.e. regenerative braking mode. Even in regenerative
braking mode, the width of the step change in the DC-link current
can be reduced by the proposed DPWM, resulting in a reduced DClink current harmonics.
Fig. 14 shows the harmonic components of the DC-link current
under the same conditions as in Fig. 13. When the conventional
DPWM is applied, the switching frequency component is 17.9%
6

IEEJ Trans. ●●, Vol.●●, No.●, ●●●Discontinuous PWM for DC-link Current Harmonic Reduction (Koroku Nishizawa et al.)

IIDC.in(p.u.)[p.u.]
DC.in(p.u.) [p.u.]

0.40
0.40

0.50
0.50

cos φ = 0.819(φ = 35 deg.)Lines : Sim. results
Plots : Exp. results

0.40
0.40

IIDC.in(p.u.)[p.u.]
DC.in(p.u.) [p.u.]

0.50
0.50

0.30
0.30
0.20
0.20

cos φ = 0.707(φ = 45 deg.)cos φ = 0.259(φ = 75 deg.)

0.10
0.10

Lines : Sim. results
Plots : Exp. results

0.30
0.30
0.20
0.20

0.00
0.00
0.0
0.0

0.2
0.2

0.4
0.6
0.8
0.4
0.6
0.8
Modulationindexmm[-][-]
Modulation index

1.0
1.0

1.2
1.2

0.0
0.0

0.2
0.2

0.4
0.4

0.6
0.6

0.8
0.8

1.0
1.0

1.2
1.2

Modulationindexmm[-][-]
Modulation index(a) Conventional DPWM.

Fig. 12.

cos φ = 0.259(φ = 75 deg.)cos φ = 0.707(φ = 45 deg.)

0.10
0.10

0.00
0.00

cos φ = 0.819(φ = 35 deg.)(b) Proposed DPWM.

Measured DC-link current harmonics in driving mode.
vu* [2.0 -/div.]

v*u.DPWM [2.0 -/div.]00

vuv [500 V/div.]

vuv [500 V/div.]00iDC.in [50 A/div.]

iDC.in [50 A/div.]00iu [50 A/div.]

iu [50 A/div.]00[10 ms/div.][10 ms/div.](a) Conventional DPWM.

(b) Proposed DPWM.

Fig. 13. Experimental waveforms at m = 0.445, cos φ = –0.766 (140 deg. lagging), i.e. regenerative braking mode; u-phase modulating
signal, output line-to-line voltage, DC-link current and output phase current.

IDC.in(p.u.) = 0.374 [p.u.]100

17.9 %

Input current [%]Input current [%]

100
10
1
0.1

0.01

0.001
10

100

1000

10000

13.3 %

1
0.1

0.01
0.001
0.001
10

100000IDC.in(p.u.) = 0.319 [p.u.]

10

100

1000

10000

Frequency [Hz]Frequency [Hz](a) Conventional DPWM.

(b) Proposed DPWM.

100000Fig. 14. Harmonic components of DC-link current at m = 0.445, cos φ = –0.766 (140 deg. lagging), i.e. regenerative braking mode
(under same conditions as in Fig. 13).
and the DC-link current harmonics is 0.374 p.u. The application of
the proposed DPWM reduces the switching frequency component
by 4.6 points, and the DC-link current harmonics by 0.319 p.u. The
experimental results in Figs. 10–14 confirm that the proposed
DPWM is effective to reduce the DC-link current harmonics for the
motor drive system, of which the variation of the load power factor
is considerably wide.
4.2 Output Phase Current Harmonics
Fig. 15 shows
THD of the output u-phase current at the load power factor of 0.866.
Up to 40th-order harmonic components of the phase current areconsidered in this evaluation. Even though the analytic criterion of
λRMS, explained in sub-section 3.2, and current THD are different,
both of them are used to evaluate the output current quality. Fig. 15
confirms the analytical results shown in Fig. 9 except for the high-modulation index area; in other words, the measured THD of theoutput phase current obtained with the proposed DPWM is higher
than those obtained with the conventional DPWM. One of thereasons for the increase of the current THD with the proposed
DPWM is the current detection error around zero-current-crossing
points. These errors cause the incorrect selection of the current
sector (A–F), listed in Table 1, and increase the output phase current
distortion, especially around the output phase current zero-crossing.
This worse output phase current distortion might cause an increaseof the iron loss in the load motor.
4.3 Inverter Efficiency
Fig. 16 shows the inverter
efficiency comparison between the conventional and proposed
DPWM at the load power factor of 0.866. The inverter efficiency ismeasured using Yokogawa WT1800 power analyzer. The
7

IEEJ Trans. ●●, Vol.●●, No.●, ●●●Discontinuous PWM for DC-link Current Harmonic Reduction (Koroku Nishizawa et al.)application of the proposed DPWM slightly improves the inverter
efficiency. In terms of the number of switching transitions, thosenumber are same between the conventional and proposed DPWM,
which can be observed from Figs. 3–4. In addition, the proposed
DPWM always clamps the phase whose flowed current’s absolutevalue is the maximum among three-phase currents due to theadaption process to the load power factor range, which can beobserved from Fig. 5. In other words, the proposed DPWM enables
to avoid the larger current chopping, leading to the smallerswitching loss compared to those with the conventional DPWM
under conditions where the load power factor is not unity.
4.4 Common-mode Voltage
Figs. 17–18 show thesimulation results for VSI operating waveforms and the harmoniccomponents of the common-mode voltage at the modulation index
of 0.705 and the load power factor of 0.819 (under the same
conditions as in experimental conditions in Figs 10–11). The
common-mode voltage (vno) is defined as the potential difference
between the star point of the motor load (n) and the center of the
dc-bus (o), which can be calculated as following.

Proposed DPWM
THD of iu [%]

8.0

4.0
2.0

0.0
0.0

0.6
0.6

0.8
0.8

1.0
1.0

1.2
1.2

100.0
100.0

vuo  vvo  vwo. ...................................................... (13)3

Proposed DPWM
95.0
95.0

90.0
90.0

Conventional DPWM
85.0
85.0

80.0
80.0

0.0
0.0

0.2

0.4

0.6
0.6

0.8
0.8

1.0
1.0

1.2
1.2

Modulation index m [-]Fig. 16. Inverter efficiency comparison between conventional
DPWM and proposed DPWM at cos φ = 0.866.
vu*
1.0
v*
u.DPWM

0
–1.0
vuv

vuv

vno

vno

(a) Conventional DPWM.

(b) Proposed DPWM.

Edc
0
–Edc
Edc/2
0
–Edc/220 ms/div.

Fig. 17. Simulation results of common-mode voltage at m =0.705, cos φ = 0.819 under same conditions as in Figs. 10–11.
This waveforms are from simulation model using PLECS.

100

100

28.8 %
10

vno/Edc [%]vno/Edc [%]0.4

Fig. 15. THD of output u-phase current iu at cos φ = 0.866.

Expected lifetime of the electrolytic capacitor is calculated as themultiplication of the specified lifetime Lo in the manufacturer
datasheet by three acceleration rates which are dependent on theambient temperature FT, the ripple current FI, and the applied
voltage FV(13). In this section, only the acceleration rate related to
the ripple current FI is considered, and the other two factors FT and
FV are assumed as 1.
Table 2 lists the frequency coefficient Kf of the rated ripple
current flowing through the electrolytic capacitor (RWF series,

1
0.1

0.01

12.3 %

10
1
0.1

0.01

0.001

Fig. 18.

0.2

Modulation index m [-]Electrolytic Capacitor Lifetime Comparison

10

Conventional DPWM

0.0

According to (13), the biggest vno transition occurs when the bothswitching states of the zero vector (V0 (0 0 0) and V7 (1 1 1)) areapplied during control period. However, the proposed DPWM uses
only one zero vector at a maximum during control period, which isthe same as the conventional DPWM. Therefore, the proposed
DPWM does not increase the vno transition width. Spectrum of vno
shown in Fig. 18 confirm that the proposed DPWM reduces theswitching frequency component by 16.5 points; however, increases
the high-frequency components (higher than 100 kHz) compared tothe conventional DPWM. This worse high-frequency vno
component might result in high common-mode current (motor
leakage current). This may lead to the motor bearing failures, EMInoise and so on(21)–(22).

5.

6.0

Inverter efficiency [%]

vno 

10.0
10.0

0.001
100

1000

10000

100000

10

100

1000

10000

Frequency [Hz]Frequency [Hz](a) Conventional DPWM.

(b) Proposed DPWM.

100000Harmonic components of common-mode voltage at m = 0.705, cos φ = 0.819 (under same conditions as in Figs. 10–11, 17).

8

IEEJ Trans. ●●, Vol.●●, No.●, ●●●Discontinuous PWM for DC-link Current Harmonic Reduction (Koroku Nishizawa et al.)Table 2. Frequency coefficient of rated ripple current flowing
through electrolytic capacitors (RWF series, Nippon Chemi-Con
Corp.)

Nippon Chemi-Con Corp.(23)), which has been used in thelaboratory setup. With the consideration for the frequency
dependency of the ESR in the electrolytic capacitors, the DC-linkcurrent harmonics is recalculated for its lifetime estimation as:
2

1
Im iDC.in.RMS .n 
 . ............................. (14) Kf
n 1 


Input current / Kf [%]I DC.in. freq (p.u.) Fig. 19 shows the harmonic components of the DC-link current
at the modulation index of 0.705, and the load power factor of 0.819(under the same conditions as in Figs. 10–11) with the consideration
for the frequency dependency of the ESR in the electrolytic
capacitors. The application of the proposed DPWM reduces
IDC.in.freq(p.u.) by 18.3% even when the frequency dependency of ESR
in the electrolytic capacitor is considered. Note that it is necessary
to consider the expected operation range for exact estimation of thecapacitor lifetime. However, the actual operation range in motor
speed and torque plane is dependent on each applications; therefore,
full consideration with those is difficult. Therefore, simplified
estimation is provided in this section with the assumption that thisoperating conditions (at modulation index of around 0.7 and load
power factor of around 0.8) are the medium-speed and mediumtorque conditions in the variable-speed drive systems, which are thefrequent operating conditions. Assuming that the electrolytic
capacitors in the VSI, modulated by the conventional DPWM, isdesigned at the worst case of the rated ripple current as FI = 1, theestimated lifetime Ln of the electrolytic capacitor can be given by:

Ln _ Conv.DPWM  Lo  FI  Lo 1  5 000 h
Ln _ Prop.DPWM  Lo  FI  Lo 1.26  6 300 h

50

120

300

1k

3 k~

Coefficient Kf

0.80

1.0

1.1

1.3

1.4

100

14.9 %

IDC.in.freq(p.u.) = 0.295 [p.u.]

10
1
0.1

0.01
0.001
0.001
10

100

1000

10000

100000Frequency [Hz]Input current / Kf [%](a) Conventional DPWM.

100

IDC.in.freq(p.u.) = 0.241 [p.u.] 11.0 %

10
1
0.1

0.01
0.001
0.001
10

100

1000

10000

100000Frequency [Hz](b) Proposed DPWM.

Fig. 19.
Harmonic components of DC-link current at
m = 0.705, cos φ = 0.819 (under same conditions as in Figs. 10–11) with consideration for frequency dependency of ESR inelectrolytic capacitors.

...................... (15)where Lo is 5 000 hours in case of RWF series, Nippon Chemi-Con
Corp. The ripple current factor FI is calculated by using the resultsin Fig. 19 based on the technical notes on electrolytic capacitors(13).
Note that the above lifetime estimation is just one example.
However, it can be concluded that the application of the proposed
DPWM might extend the lifetime of the electrolytic capacitor about
1.26 times longer than that with the conventional DPWM.

6.

Frequency [Hz]power factor, i.e. in both driving mode and regenerative braking
mode.

References

Conclusion(1)

A novel DPWM was proposed to reduce the DC-link current
harmonics of the three-phase VSI, which flowed through the DClink capacitor, over the wide variation of the load power factor. This
modulation method contributed the long lifetime of the smoothing
capacitor in the motor drive system. Furthermore, this strategy
required only one carrier; thus, high cost hardware such as FPGA
was unnecessary. The DC-link current harmonics were reduced byshifting two unclamped modulating signals in every half control
period. In addition, the injection of the zero sequence signal to all
discontinuous modulating signals optimized the phase of clamped
modulating signal and its clamped value according to the conditionsof the output phase currents; consequently, the DC-link current
harmonics were reduced even when the load power factor varied.
The experimental results confirmed that the application of the
proposed DPWM reduced the RMS value of the DC-link current by
18.3% with the consideration for the frequency dependency of the
ESR of the electrolytic capacitor. The lifetime estimation results
confirmed that the DC-link RMS current reduction of 18.3% could
lead to the lifetime extension of 1.26 times for the electrolytic
capacitor. Furthermore, the application of the proposed DPWM
reduced the DC-link current harmonics over entire range of the load

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

9

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Koroku Nishizawa

Takahashi Power Electronics Award in IPEC-Sapporo 2010 from IEEJ, 58th
OHM Technology Award from The Foundation for Electrical Science andEngineering, November, 2011, Intelligent Cosmos Award from Intelligent
Cosmos Foundation for the Promotion of Science, May, 2012, and Third
prize award from Energy Conversion Congress and Exposition-Asia, June,
2013. Prizes for Science and Technology (Development Category) from theCommendation for Science and Technology by the Minister of Education,
Culture, Sports, Science and Technology, April 2017. He is a senior memberof the Institute of Electrical Engineers of Japan, the Society of Automotive
Engineers of Japan and the IEEE.

Akihiro Odaka(Member) received the B.S. and M.S. degrees from
Tokyo Denki University, Tokyo, Japan, in 1996 and1998, respectively. Since 1998, he has been with Fuji
Electric Co., Ltd., Tokyo. He is a member of IEEJ andIEEE. His research interests include static converters
and power semiconductor applications.

Akio Toba(Senior member) received the M.E. and Ph.D.
degrees from Tokyo Metropolitan University, Tokyo,
Japan, in 1994 and 2006, respectively. In 1994, hejoined Fuji Electric Co. Ltd., Tokyo, where he has
been conducting the research and development of
power electronics, motor drives, and electricmachines. From 1997 to 1999, he was a Visiting
Researcher with Wisconsin Electric Machines andPower Electronics Consortium, University of
Wisconsin, Madison, USA. He is a senior member of IEEJ and a member ofIEEE.

(Student member) received the B.S. degree inelectrical, electronics and information engineeringfrom Nagaoka University of Technology, Niigata,Japan, in 2015, where he is currently working toward
the Ph.D. degree. He is a student member of IEEJ andIEEE. His current research focuses on the modulation
strategy of converters.

Hidetoshi Umida(Fellow) received the B.E., M.E. and Ph.D. degrees
in electrical engineering from Tokyo Institute ofTechnology, Tokyo, Japan, in 1970, 1981 and 1984,
respectively. Since 1984, he has been with Fuji
Electric Co., Ltd., Tokyo. He is currently a Chief
Engineer with Fuji’s Corporate R&D Headquarters.
His research interests include control theory and its
application to motor drives and converters. He is afellow of IEEJ and a member of IEEE.

Jun-ichi Itoh

(Senior member) received the M.S. and Ph.D.
degrees in electrical and electronic systems
engineering from Nagaoka University of Technology,
Niigata, Japan in 1996, 2000, respectively. From 1996
to 2004, he was with Fuji Electric Corporate Researchand Development Ltd., Tokyo, Japan. He was with
Nagaoka University of Technology, Niigata, Japan as
an associate professor. Since 2017, he has been aprofessor. His research interests are matrix converters, dc/dc converters,
power factor correction techniques, energy storage system and adjustablespeed drive systems. He received IEEJ Academic Promotion Award (IEEJ
Technical Development Award) in 2007. In addition, he also received Isao
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