DATA SHEET( DOC No. HX8357-D00/D01-DS )HX8357-D00/D01
320RGB x 480 dot, 16M color,
with internal GRAM,
TFT Mobile Single Chip Driver
Temporary Version 00 April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Contents
1.
2.

3.

4.

5.

April, 2012

General Description ................................................................................................................................. 9
Features................................................................................................................................................... 10
2.1
Display ........................................................................................................................................... 10
2.2
Display module .............................................................................................................................. 10
2.3
Display control interface .................................................................................................................11
2.4
Input power .....................................................................................................................................11
2.5
Miscellaneous .................................................................................................................................11
Block Diagram ........................................................................................................................................ 12
3.1
Block diagram ................................................................................................................................ 12
3.2
Pin description ............................................................................................................................... 13
3.3
Pin assignment .............................................................................................................................. 16
Interface................................................................................................................................................... 17
4.1
MIPI DBI-B interface...................................................................................................................... 18
4.2
Serial data transfer interface (MIPI DBI TYPE-C) ......................................................................... 34
4.2.1 Serial data write mode.......................................................................................................... 34
4.2.2 Read operation in serial peripheral interface........................................................................ 35
4.2.3 DBI TYPE-C interface data color coding .............................................................................. 36
4.2.4 Break and pause sequences ................................................................................................ 38
4.3
MIPI DPI interface (display pixel interface) ................................................................................... 40
4.4
DSI system interface (For HX8357-D01 only) ............................................................................... 45
4.4.1 DSI layer definitions.............................................................................................................. 46
4.4.2 DSI protocol .......................................................................................................................... 47
Functional Description .......................................................................................................................... 59
5.1
Display data GRAM mapping ........................................................................................................ 59
5.1.1 Address counter (AC) ........................................................................................................... 59
5.1.2 System interface to GRAM write direction............................................................................ 60
5.1.3 Source, gate and memory map ............................................................................................ 62
5.1.4 Fully display, partial display, vertical scrolling display .......................................................... 63
5.2
Tearing effect output line ............................................................................................................... 70
5.2.1 Tearing effect line modes...................................................................................................... 70
5.2.2 Tearing effect line timing....................................................................................................... 72
5.2.3 Example 1: MPU write is faster than panel read .................................................................. 73
5.2.4 Example 2: MPU write is slower than panel read................................................................. 74
5.3
Checksums .................................................................................................................................... 75
5.4
Oscillator........................................................................................................................................ 78
5.5
Source driver ................................................................................................................................. 79
5.6
Gate driver ..................................................................................................................................... 80
5.7
LCD power generation circuit ........................................................................................................ 81
5.7.1 Power supply circuit.............................................................................................................. 81
5.7.2 LCD power generation scheme............................................................................................ 82
5.8
Gamma characteristic correction function ..................................................................................... 83
5.8.1 Gamma characteristic correction function ............................................................................ 84
5.8.2 Gray voltage generator for digital gamma correction ........................................................... 87
5.9Power function ............................................................................................................................... 88
5.9.1 Power on/off sequence......................................................................................................... 88
5.9.2 Power levels definition.......................................................................................................... 91
5.9.3 Deep standby mode set up flow ........................................................................................... 92
5.10 Input / output pin state ................................................................................................................... 93
5.10.1 Output pins ........................................................................................................................... 93
5.10.2 Input pins .............................................................................................................................. 93
5.11 Sleep out – command and self-diagnostic functions of display module........................................ 94
5.11.1 Register loading detection .................................................................................................... 94
5.11.2 Functionality detection.......................................................................................................... 95
5.12 Content adaptive brightness control (CABC) function................................................................... 96
5.12.1 Module architectures ............................................................................................................ 97
5.12.2 Brightness control block ....................................................................................................... 98

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.2April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Contents

6.

April, 2012

5.12.3 Minimum brightness setting of CABC function ..................................................................... 99
5.12.4 Display dimming ................................................................................................................. 102
5.13 OTP programing .......................................................................................................................... 103
5.13.1 OTP table............................................................................................................................ 103
5.13.2 OTP programming flow....................................................................................................... 104
Command Set ....................................................................................................................................... 105
6.1
Command set list ......................................................................................................................... 105
6.1.1 Standard command ............................................................................................................ 105
6.1.2 User define command list table ...........................................................................................110
6.2
Command description...................................................................................................................114
6.2.1 NOP .....................................................................................................................................114
6.2.2 Software reset (01h) ............................................................................................................115
6.2.3 Read display identification information (04h) ......................................................................116
6.2.4 RDNUMPE: Read Number of the Errors on DSI (05h) .......................................................117
6.2.5 Read red color (06h)............................................................................................................118
6.2.6 Read green color (07h)........................................................................................................1196.2.7 Read blue color (08h) ......................................................................................................... 120
6.2.8 Read display power mode (0Ah) ........................................................................................ 121
6.2.9 Read display MADCTL (0Bh) ............................................................................................. 123
6.2.10 Read display pixel format (0Ch) ......................................................................................... 125
6.2.11 Read display image mode (0Dh) ........................................................................................ 127
6.2.12 Read display signal mode (0Eh) ........................................................................................ 129
6.2.13 Read display self-diagnostic result (0Fh) ........................................................................... 130
6.2.14 Sleep in (10h) ..................................................................................................................... 131
6.2.15 Sleep out (11h) ................................................................................................................... 133
6.2.16 Partial mode on (12h) ......................................................................................................... 135
6.2.17 Normal display mode on (13h) ........................................................................................... 136
6.2.18 Display inversion off (20h) .................................................................................................. 137
6.2.19 Display inversion on (21h) .................................................................................................. 138
6.2.20 All pixel off (22h) ................................................................................................................. 139
6.2.21 All pixel on (23h) ................................................................................................................. 140
6.2.22 Gamma set (26h)................................................................................................................ 141
6.2.23 Display off (28h).................................................................................................................. 142
6.2.24 Display on (29h) ................................................................................................................. 143
6.2.25 Column address set (2Ah).................................................................................................. 144
6.2.26 Page address set (2Bh)...................................................................................................... 146
6.2.27 Memory write (2Ch) ............................................................................................................ 148
6.2.28 Memory read (2Eh)............................................................................................................. 149
6.2.29 Partial area (30h) ................................................................................................................ 150
6.2.30 Vertical scrolling definition (33h)......................................................................................... 152
6.2.31 Tearing effect line off (34h) ................................................................................................. 155
6.2.32 Tearing effect line on (35h) ................................................................................................. 156
6.2.33 Memory access control (36h) ............................................................................................. 157
6.2.34 Vertical scrolling start address (37h) .................................................................................. 159
6.2.35 Idle mode off (38h) ............................................................................................................. 161
6.2.36 Idle mode on (39h) ............................................................................................................. 162
6.2.37 Interface pixel format (3Ah) ................................................................................................ 164
6.2.38 Write_memory_contiune (3Ch)........................................................................................... 165
6.2.39 Raed_memory_continue (3Eh) .......................................................................................... 166
6.2.40 Set tear scan line (44h) ...................................................................................................... 167
6.2.41 Get Scan Lines (45h).......................................................................................................... 168
6.2.42 Write display brightness value (51h) .................................................................................. 169
6.2.43 Read display brightness value (52h) .................................................................................. 170
6.2.44 Write control display (53h).................................................................................................. 171
6.2.45 Read control value display (54h) ........................................................................................ 172

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.3April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Contents

7.

8.

April, 2012

6.2.46 Write content adaptive brightness control (55h)................................................................. 173
6.2.47 Read content adaptive brightness control (56h) ................................................................ 174
6.2.48 Write CABC minimum brightness (5Eh) ............................................................................. 175
6.2.49 Read CABC minimum brightness (5Fh) ............................................................................. 176
6.2.50 Read automatic brightness control self-diagnostic result (68h) ......................................... 177
6.2.51 Read Black/White Low Bits (70h) ....................................................................................... 178
6.2.52 Read Bkx (71h)................................................................................................................... 179
6.2.53 Read Bky (72h)................................................................................................................... 180
6.2.54 Read Wx (73h) ................................................................................................................... 181
6.2.55 Read Wy (74h) ................................................................................................................... 182
6.2.56 Read Red/Green Low Bits (75h) ........................................................................................ 183
6.2.57 Read Rx (76h) .................................................................................................................... 184
6.2.58 Read Ry (77h) .................................................................................................................... 185
6.2.59 Read Gx (78h) .................................................................................................................... 186
6.2.60 Read Gy (79h) .................................................................................................................... 187
6.2.61 Read Blue/AColur Low Bits (7Ah) ...................................................................................... 188
6.2.62 Read Bx (7Bh) .................................................................................................................... 189
6.2.63 Read By (7Ch) .................................................................................................................... 190
6.2.64 Read Ax (7Dh) .................................................................................................................... 191
6.2.65 Read Ay (7Eh) .................................................................................................................... 192
6.2.66 Read_DDB_start (A1h)....................................................................................................... 193
6.2.67 Read_DDB_continue (A8h) ................................................................................................ 194
6.2.68 Read first checksum (AAh)................................................................................................. 195
6.2.69 Read continue checksum (AFh) ......................................................................................... 196
6.2.70 Read ID1 (DAh) .................................................................................................................. 197
6.2.71 Read ID2 (DBh) .................................................................................................................. 198
6.2.72 Read ID3 (DCh) .................................................................................................................. 199
6.2.73 SETOSC: set internal oscillator (B0h) ................................................................................ 200
6.2.74 SETPOWER: set power control (B1h)................................................................................ 201
6.2.75 SETDISPLAY: set display related register (B2h)................................................................ 205
6.2.76 SETRGB: set RGB interface (B3h) .................................................................................... 207
6.2.77 SETCYC: set display cycle register (B4h).......................................................................... 210
6.2.78 SETBGP (B5h) ................................................................................................................... 212
6.2.79 SETCOM: set VCOM voltage related register (B6h) .......................................................... 214
6.2.80 SETOTP: set OTP setting (B7h)......................................................................................... 216
6.2.81 SETEXTC: enable extension command (B9h) ................................................................... 217
6.2.82 SETSTBA (C0h) ................................................................................................................. 218
6.2.83 SETDGC: set DGC related setting (C1h) ........................................................................... 220
6.2.84 SETID: set ID (C3h)............................................................................................................ 221
6.2.85 SETDDB: Set DDB (C4h) ................................................................................................... 222
6.2.86 SETCABC: set CABC related setting (C9h) ....................................................................... 223
6.2.87 SETPanel: set panel characteristic (CCh) .......................................................................... 224
6.2.88 SETGamma: set gamma curve (E0h) ................................................................................ 225
6.2.89 SETIMAGE: set image function (E9h)................................................................................ 227
6.2.90 SETMESSI: Set Command type (EAh) .............................................................................. 228
6.2.91 SETCOLOR: set color (EBh) .............................................................................................. 229
6.2.92 SETREADINDEX: set SPI read index (FEh) ...................................................................... 231
6.2.93 GETSPIREAD: SPI Read Command Data (FFh)............................................................... 232
6.2.94 GETICID: IC ID Read Command Data (D0h)..................................................................... 233
Layout Recommendation .................................................................................................................... 234
7.1
Maximum layout resistance ......................................................................................................... 235
7.2
External components connection ................................................................................................ 236
Electrical Characteristic ...................................................................................................................... 237
8.1
Absolute maximum ratings .......................................................................................................... 237
8.2
DC characteristics ....................................................................................................................... 238

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.4April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Contents

April, 2012

8.3
8.4

AC characteristics........................................................................................................................ 239
DBI Type B interface characteristic ............................................................................................. 239
8.4.1 DBI Type C interface characteristics .................................................................................. 240
8.4.2 DPI interface characteristics............................................................................................... 241
8.4.3 Reset input timing............................................................................................................... 243
8.4.4 DSI D-PHY electrical characteristics .................................................................................. 246
9. Ordering Information............................................................................................................................ 254
10. Revision History ................................................................................................................................... 254

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.5April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Figures

April, 2012

Figure 4.1: DBI-B system interface protocol, write to register or GRAM .......................................... 18
Figure 4.2: DBI-B system interface protocol, read from register or GRAM....................................... 18
Figure 4.3: Example of DBI-B System 8-bit bus Interface ................................................................ 19
Figure 4.4: Write data for RGB 5-6-5 (65k colors) bits input in 8-bit parallel interface ..................... 19
Figure 4.5: Write data for RGB 6-6-6-bits(262k colors) input in 8-bit parallel interface .................... 20
Figure 4.6: Write data for RGB 8-8-8-bits(16M colors) input in 8-bit parallel interface..................... 21
Figure 4.7: Example of DBI-B system 9-bit bus interface ................................................................. 22
Figure 4.8: Write data for RGB 5-6-5 (65k colors) bits input in 9-bit parallel interface ..................... 22
Figure 4.9: Write data for RGB 6-6-6 (262k colors) bits input in 9-bit parallel interface ................... 23
Figure 4.10: Example of DBI-B System 16-bit bus interface ............................................................ 24
Figure 4.11: Write data for RGB 5-6-5 (65k colors) bits input in 16-bit parallel interface ................. 25
Figure 4.12: Write data for RGB 6-6-6 (262k colors) bits input in 16-bit parallel interface ............... 26
Figure 4.13: Write data for RGB 8-8-8 (16M colors) bits input in 16-bit parallel interface ................ 27
Figure 4.14: Example of DBI-B system 18-bit parallel bus interface ................................................ 28
Figure 4.15 Write data for RGB 6-6-6 (262k colors) bits input in 18-bit parallel interface ................ 29
Figure 4.16: Example of DBI-B system 24-bit parallel bus interface ................................................ 30
Figure 4.17 Write data for RGB 8-8-8 (16M colors) bits input in 24-bit parallel interface ................. 31
Figure 4.18: DBI type C – serial interface protocol 3 wire/ 4 wire, write mode ................................. 34
Figure 4.19: Command read operation in serial peripheral interface................................................ 35
Figure 4.20: Write data for RGB 5-6-5-bit input of DBI TYPE-C OPTION 1 ..................................... 36
Figure 4.21: Write data for RGB 5-6-5-bit input of DBI TYPE-C OPTION 3 ..................................... 36
Figure 4.22: Write data for RGB 6-6-6-bit input of DBI TYPE-C OPTION 1 ..................................... 36
Figure 4.23: Write data for RGB 6-6-6-bit input of DBI TYPE-C OPTION 3 ..................................... 36
Figure 4.24: Display module data transfer recovery ......................................................................... 38
Figure 4.25: Break during parameter ................................................................................................ 38
Figure 4.26: Display module data transfer pause ............................................................................. 39
Figure 4.27: PCLK cycle ................................................................................................................... 40
Figure 4.28: General timing diagram................................................................................................. 41
Figure 4.29: DPI timing diagram ....................................................................................................... 41
Figure 4.30: 16-bit data bus color order on DPI interface ................................................................. 42
Figure 4.31: 18-bit data bus color order on DPI interface ................................................................. 43
Figure 4.32: DSI transmitter and receiver interface .......................................................................... 45
Figure 4.33: Transmitter and receiver interface ................................................................................ 46
Figure 4.34: DSI multiple HS transmission packets.......................................................................... 47
Figure 4.35: Structure of the short packet......................................................................................... 47
Figure 4.36: Structure of the long packet.......................................................................................... 48
Figure 4.37: Format of data ID .......................................................................................................... 48
Figure 4.38: Show short- / long-packet transmission command sequence ...................................... 49
Figure 5.1: Image data sending order from host............................................................................... 60
Figure 5.2: MY,MX,MV Setting of GRAM control.............................................................................. 60
Figure 5.3: Memory map 320RGBx480 dot ...................................................................................... 62
Figure 5.4: Memory map of full display ............................................................................................. 63
Figure 5.5: Vertical scrolling .............................................................................................................. 66
Figure 5.6: Memory map of vertical scrolling example 1................................................................... 66
Figure 5.7: Memory map of vertical scrolling example 2................................................................... 67
Figure 5.8: Memory map of vertical scrolling example 3................................................................... 67
Figure 5.9: Display of vertical scroll example 1................................................................................. 68
Figure 5.10: Display of vertical scroll example 2............................................................................... 69
Figure 5.11: TE mode 1 output.......................................................................................................... 70
Figure 5.12: TE delay output............................................................................................................. 70
Figure 5.13: TE mode 2 output ......................................................................................................... 71
Figure 5.14: TE output waveform...................................................................................................... 71
Figure 5.15: Waveform of tearing effect signal ................................................................................. 72
Figure 5.16: Timing of tearing effect signal....................................................................................... 72

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.6April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Figures

April, 2012

Figure 5.17: Timing of MPU write is faster than panel read .............................................................. 73
Figure 5.18: Display of MPU write is faster than panel read............................................................. 73
Figure 5.19: Timing of MPU write is slower than panel read............................................................. 74
Figure 5.20: Display of MPU write is slower than panel read ........................................................... 74
Figure 5.21: HX8357-D00/D01 internal clock circuit ......................................................................... 78
Figure 5.22: Source channels of ZigZag inversion mode ................................................................. 79
Figure 5.23: Scan direction of Gate Driver........................................................................................ 80
Figure 5.24: Block diagram of HX8357-D00/D01 power circuit ........................................................ 81
Figure 5.25: LCD power generation scheme .................................................................................... 82
Figure 5.26: Gamma adjustments different of source driver with digital gamma correction ............. 83
Figure 5.27: Gamma resister stream and gamma reference voltage ............................................... 84
Figure 5.28: Relationship between GRAM data and output level (normal white panel REV_Panel=“0”)................................................................................................................................................... 85
Figure 5.29: Gamma curve according to GC0 to GC3 bit ................................................................. 86
Figure 5.30: Block diagram of digital gamma correction................................................................... 87
Figure 5.31: Case 1 – NRESET line is held high or unstable by host at power on........................... 89
Figure 5.32: NRESET line is held low by host at power on .............................................................. 90
Figure 5.33: Power flow chart for different power modes ................................................................. 91
Figure 5.34: Deep standby mode setting flow................................................................................... 92
Figure 5.35: RDDSDR register loading detection flow...................................................................... 94
Figure 5.36: Functionality detection flow........................................................................................... 95
Figure 5.37: CABC block diagram..................................................................................................... 96
Figure 5.38: CABC_PWM_OUT output duty..................................................................................... 98
Figure 5.39: RDABCSDR register loading detection flow ............................................................... 100
Figure 5.40: RDABCSDR functionality detection flow..................................................................... 101
Figure 5.41: Dimming function ........................................................................................................ 102
Figure 5.42: OTP programming sequence...................................................................................... 104
Figure 7.1: Layout recommendation of HX8357-D00/D01.............................................................. 234
Figure 8.1: DBI Type B interface characteristics ............................................................................. 239
Figure 8.2: DBI Type C interface characteristics............................................................................. 240
Figure 8.3: General timings for RGB I/F-2 ...................................................................................... 242
Figure 8.4: Reset input timing ......................................................................................................... 243
Figure 8.5: tACC and tOH measurement condition set-up ............................................................. 244
Figure 8.6: tACC and tOH minimum condition set-up..................................................................... 244
Figure 8.7: tACC and tOH maximum value measurement.............................................................. 245
Figure 8.8: Electrical functions of a fully D-PHY transceiver .......................................................... 246
Figure 8.9: Shows both the HS and LP signal levels ...................................................................... 246
Figure 8.10: Input glitch rejections of low-power receivers ............................................................. 249
Figure 8.11: DDR clock definition.................................................................................................... 251
Figure 8.12: Data to clock timing definitions ................................................................................... 252

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.7April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Tables

April, 2012

Table 4.1: Interface selection ............................................................................................................ 17
Table 4.2: 8-bit interface GRAM write table....................................................................................... 32
Table 4.3: 9-bit interface GRAM write table....................................................................................... 32
Table 4.4: 16-bit interface GRAM write table .................................................................................... 32
Table 4.5: 18-bit interface GRAM write table .................................................................................... 32
Table 4.6: 24-bit interface GRAM write table .................................................................................... 32
Table 4.7: 8-bit parallel interface GRAM read table .......................................................................... 33
Table 4.8: 16-bit parallel interface GRAM read table ........................................................................ 33
Table 4.9: 9-bit parallel interface GRAM read table .......................................................................... 33
Table 4.10: 18-bit parallel interface GRAM read table ...................................................................... 33
Table 4.11: 24-bit parallel interface GRAM read table ...................................................................... 33
Table 4.12: DBI TYPE-C interface GRAM write table ....................................................................... 37
Table 4.13: 16-/18- DPI color mapping ............................................................................................. 42
Table 4.14: 24-DPI color mapping..................................................................................................... 42
Table 4.15: Data types for processor-sourced packets..................................................................... 50
Table 4.16: Shows the error report bit definitions.............................................................................. 57
Table 4.17: Complete set of peripheral-to-processor data types ...................................................... 57
Table 5.1: Addresses counter range.................................................................................................. 59
Table 5.2: MY.MX.MV Setting of GRAM address mapping .............................................................. 60
Table 5.3: Address direction settings ................................................................................................ 61
Table 5.4: Memory map of full display............................................................................................... 63
Table 5.5: Memory map of partial display ......................................................................................... 65
Table 5.6: AC characteristics of tearing effect signal ........................................................................ 72
Table 5.7 Adoptability of capacitor..................................................................................................... 81
Table 5.8: Characteristics of output pins ........................................................................................... 93
Table 5.9: Characteristics of input pins ............................................................................................. 93
Table 8.1: Absolute maximum ratings ............................................................................................. 237
Table 8.2: DBI Type B interface characteristics .............................................................................. 239
Table 8.3: DBI Type C interface characteristics .............................................................................. 240
Table 8.4: DPI interface characteristics-1 ....................................................................................... 241
Table 8.5: DPI interface characteristics-2 ....................................................................................... 242
Table 8.6: Reset input timing........................................................................................................... 243
Table 8.7: LP transmitter DC specifications .................................................................................... 247
Table 8.8: LP transmitter AC specifications .................................................................................... 247
Table 8.9: HS receiver DC specifications ........................................................................................ 248
Table 8.10: HS receiver AC specifications ...................................................................................... 248
Table 8.11: LP receiver DC specifications....................................................................................... 249
Table 8.12: LP receiver AC specifications....................................................................................... 249
Table 8.13: Contention detector DC specifications ......................................................................... 250
Table 8.14: Reverse HS data transmission timing parameters....................................................... 251
Table 8.15: Data to clock timing specifications ............................................................................... 253

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.8April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, with internal
GRAM, TFT Mobile Single Chip Driver

Temporary Version 00

April, 2012

1. General Description
This document describes Himax’s HX8357-D00/D01 supports HVGA resolution
driving controller. The HX8357-D00/D01 is designed to provide a single-chip solutionthat combines a source driver, power supply circuit to drive a TFT-LCD panel with
320RGBx480 dots at maximum.
The HX8357-D00/D01 can be operated in low-voltage condition for the interface andintegrated internal boosters that produce the liquid crystal voltage, breeder resistanceand the voltage follower circuit for liquid crystal driver. In addition, The
HX8357-D00/D01 also supports various functions to reduce the power consumptionof a TFT-LCD panel via software control.
The HX8357-D00/D01 supports several interface modes, including MPU MIPI DBI
Type B interface mode and MIPI DPI/DBI Type C interface mode. The HX8357-D01
also supports MIPI DSI (Display Serial Interface) interface mode. The interface modeis selected by the external hardware pins IM2~0.
The HX8357-D00/D01 is suitable for any small portable battery-driven and long-term
driving products, such as small PDAs, digital cellular phones and bi-directional
pagers.

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.9April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

2. Features
2.1Display
 Resolution:
 320(H) x RGB(H) x 480(V) Display Color modes Normal Display Mode On
1. DBI Interface
a. 65k colors (R(5),G(6),B(5))
b. 262k colors (R(6),G(6),B(6))
c. Virtual 24 bits colors (R(8),G(8),B(8))
2. DPI Interface
a. 65k colors (R(5),G(6),B(5))
b. 262k colors (R(6),G(6),B(6))
c. 16M colors (R(8),G(8),B(8))
3. MIPI Interface (For HX8357-D01 only)
a. 65k colors (R(5),G(6),B(5))
b. 262k colors (R(6),G(6),B(6))
c. Virtual 24 bits colors (R(8),G(8),B(8))
 Idle Mode On− 8 (R(1),G(1),B(1)) colors
2.2Display module












Frame Memory area 320 (H) x 480 (V) x 18 bits
On module DC/DC converter
VSP = 5.2 V for two time pump (Power supply for driver circuit range)
VSP = 6.2 V for three time pump (Power supply for driver circuit range)
VSN = -5.2 V for two time pump (Power supply for driver circuit range)
VSN = -6.2 V for three time pump (Power supply for driver circuit range)
VSPR =3.3V to 5.8V (Positive Source output voltage range)
VSNR= -3.3V to -5.8V (Negative Source output voltage range)
VGH = +10.0 to +15.3V (Positive Gate output voltage range)
VGL = -7.5 to -12.8V (Negative Gate output voltage range)
VCOM=-2.5V to 0V

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

2.3Display control interface

MIPI-DBI 8-/9-/16-/18-/24-bit MPU parallel interface.
MIPI-DBI Serial data transfer interface.
MIPI-DPI 8-/16-/18-/24-data lines parallel video (RGB) interface.
MIPI-DSI interface.(for Display Serial Interface Version 1.01 and D-PHY Version
1.00)

2.4Input power Logic power supply (IOVCC): 1.65V ~ 3.3V
 Analog power supply (VCI): 2.5V ~ 3.3V
2.5Miscellaneous


















Low power consumption, suitable for battery operated systems
Image sticking eliminated function
CMOS compatible inputs
One chip solution for COG assembly
Support 24-bits Input Image function
Support 1-dot/2-dot/4-dot/column inversion/Zig-Zag inversion
Support Area scrolling
Support Partial display mode
Support Deep standby mode
Support normal black/normal white LCD
Support wide view angle display
On-chip OTP (One-time-programming) and MTP(four-time-programming for ID
and VCOM register)
Built-in internal OTP power
Support Content Adaptive Brightness Control(CABC) function
Support Color enhancement function
Support Digital 3-Gamma function
Operating temperature range : -40℃~ 85℃

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320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
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3. Block Diagram
3.1Block diagram

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3.2Pin description
Interface Logic Pin
Signals

Pin
Connected
I/O
Numberwith

Description
System interface select.

IM2,IM1,IM0

I

3

VSSD/
IOVCC

CSX

I

1

MPU

WRX_SCL

I

1

MPU

IM2

IM1

IM0

Interface

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

DBI TYPE-B 18-bit/24-bit
DBI TYPE-B 9-bit
DBI TYPE-B 16-bit
DBI TYPE-B 8-bit
Not useDBI TYPE-C Option 1
MIPI DSI (For HX8357-D01 only)
DBI TYPE-C Option 3

If not used, please fix this pin to IOVCC or VSSD level.
Chip select signal.
Low: chip can be accessed;
High: chip cannot be accessed.
Fix it to IOVCC when not used.
DBI Type-B mode: Serves as a write signal and write data at the low level.
DBI Type-C mode: it servers as SCL (Serial Clock)Fix it to IOVCC or VSSD level when not used.
RDX

I

1

DCX

I

1

VSYNC

I

1

HSYNC

I

1

DE

I

1

PCLK

I

1

RESX

I

1

DIN_SDA

I/O

1

MPU
MPU

DBI Type-B: Serves as a read signal and read data at the low level.

If not used, please fix this pin at IOVCC or GND level
DBI Type-B, Type-C Option 3: Data / Command Selection pin

If not used, please fix this pin at IOVCC or GND level.
Vertical synchronizing signal in DPI interface.
MPU
Let to open or connected to VSSD.
Horizontal synchronizing signal in DPI interface.
MPU
Let to open or connected to VSSD.
A data ENABLE signal in DPI I/F mode.
MPU
Let to open or connected to VSSD.
Data enable signal in DPI interface.
MPU
Let to open or connected to VSSD.
MPU or Reset pin. Setting either pin low initializes the LSI. Must be reset
reset circuit after power is supplied.
Serial data input pin and output pin in serial bus system interface.
MCU
The data is inputted on the rising edge of the SCL signal.
If not used, please let it open
Serial data output.
If SDO_EN=0, DOUT is not use.

DOUT

O

1

MPU

If SDO_EN=1, DOUT is serial data output.
Let it to open in MPU interface mode.

DB17~0DB18
TS0_DB19
TS1_DB20
TS2_DB21
TS3_DB22
TS4_DB23

I/O

24

MPU

24-bit bi-directional data bus.
The unused pins let to open or connected to VSSD.

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Output Part
Signals

I/O

Pin
NumberConnected
with

S1~S961

O

961

LCD

G1~G480

O

480

VCOM

O

13

TE

O

1

CABC_PWM1O1CABC_PWM2

O1

CABC_ONO

1

Signals

I/O

Pin
NumberInput/Output Part
Connected
with

C11A,C11B
C13A, C13B

I/O

11,11
10,10

Step-upCapacitor

Connect to the step-up capacitors for step up circuit 1
operation (VSP).

C12A,C12B
C14A,C14B

I/O

6,6
13,14

Step-upCapacitor

Connect to the step-up capacitors for step up circuit 3
operation (VSN).

C22A,C22B

I/O

12,13

Step-upCapacitor

Connect to the step-up capacitors for step up circuit 1
operation (VGH/VGL).

Signals

I/O

Pin
Number

IOVCC
VCI
VSSD
VSSA

P
P
P
P

7
22
13
8

VDDD

O

11

NVDDDOUTVSPROUTVSNROUT

O
O
O

10
4
7

VSP

O

9

VSN

O

11

VGH

O

8

VGL

O

10

VCOMDCO

3

Description

Output voltages applied to the liquid crystal.
Gate driver output pins. These pins output VGH, VGL.(If not used,
LCD
should be open).
TFT common The power supply of common voltage in TFT driving. Connect this pin
electrodeto the common electrode in TFT panel.
Tearing effect output.
MPU
If not used, please open this pin.
Backlight
CABC backlight control PWM signal output.
Circuit/MPU
Backlight
CABC backlight control PWM signal output.
CircuitBacklight
LED Driver Enable Signal.
CircuitIf not used, please open this pin.

Description

Power Part
Connected
Description
withPower Supply Digital IO Pad power supply.
Power Supply Analog power supply.
GroundDigital ground.
GroundAnalog ground.
Stabilizing
For internal logic voltage. Connect to a stabilizing capacitor.
capacitorOpen
For internal logic voltage

Internal generated stable power for source driver unit.
Internal generated stable power for source driver unit.
An output from the step-up circuit1.
Connect a stabilizing capacitor between VSSA and VSP.
An output from the step-up circuit3.
Connect a stabilizing capacitor between VSSA and VSN.
A positive power output from the step-up circuit 2 for the gateline drive circuit.
A negative power output from the step-up circuit 2 for the gate
Schottkey
line drive circuit.
barrier diode
Connect a schottkey barrier diode between VSSA and VGL.
Open
An output of VCOM level.
Open
Open
Stabilizing
capacitor
Stabilizing
capacitor
Stabilizing
capacitor

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320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
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High speed interface parts
Signals

I/O

Pin
NumberConnected
with

HSI_DP,
HSI_DN

I/O

2/2

DSI Host

HSI_CP,
HSI_CNI

2/2

DSI Host

HSI_VSSP

4GroundHSI_LDOO

3

Capacitor

Description
High speed interface data differential signal input/output pins.
If not used, please open or connect it to VSSAHigh speed interface CLOCK differential signal input pins.
If not used, please open or connect it to VSSAHigh speed interface analogy ground. HSI_VSS=0V. When using the
COG method, connect to VSSA on the FPC to prevent noise.
High speed interface regulator output pin.
Connect to a stabilizing capacitor between HSI_VSS and HSI_LDO
If not used, please open these pins.

Test pin and others
Connected
with

Signals

I/O

Pin
Number

TEST1

I

1

Open

TEST2

I

1

Open

TEST3

I

1

Open

OSC
TESTDPVTEST
NVTEST

I
O
O
O

1
1
1
1

Open
Open
Open
Open

DUMMY1~30
DUMMY31~69

-

69

Open

DUMMY_VCL

-

9

Open

Description

Test pin input (Internal pull low).
If not used, please open or connect it to VSSA
Test pin input (Internal pull low).
If not used, please open or connect it to VSSA
Test pin input (Internal pull low).
If not used, please open or connect it to VSSA
A test pin. Please let it open
A test pin. Please let it open
A test pin. Please let it open
Gamma voltage of Panel test pin output. Must be left open.
Dummy pads. Please let it open
Dummy1 can be used as COG bonding resistancemeasurement
Dummy pads. Please let it open

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3.3Pin assignment
TBD

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4. Interface
The HX8357-D supports MIPI interfaces: DBI (Display Bus Interface), DPI (Display Pixel
Interface), DSI (Display Serial Interface). Where DBI supports (24-/18-/16-/9-/8-bit interface)
Parallel Interface (Type B) and Serial interface (Type C Option 1/ Option 3). The interface
mode can be selected by IM2-0 pins setting as show in Table 4.1.

IM2 IM1 IM0
0
0
0
0
0
1
1
1

0
0
0
1
1
0
0
1

0
0
1
0
1
0
1
0

1

1

1

InterfaceWRX_SCL

DBI TYPE-B 18-bit (DB_EN=’0’) WRX
DBI TYPE-B 24-bit(DB_EN=’1’) WRX
DBI TYPE-B 9-bit
WRX
DBI TYPE-B 16-bit
WRX
DBI TYPE-B 8-bit
WRX
Not useDBI TYPE-C Option 1
SCL
MIPI DSI(For HX8357-D01 only)
DBI TYPE-C Option 3
SCL

Data Bus use
Command/GRAM
Parament
DB7-DB0
DB7-DB0
DB7-DB0
DB7-DB0
DB7-DB0
SDA

DB17-DB0: 18-bits Data
DB23-DB0: 24-bits Data
DB8-DB0: 9-bits Data
DB15-DB0: 16-bits Data
DB7-DB0: 8-bit Data

HSI_CP/N , HSI_D0P/N
SDA

Table 4.1: Interface selection

The HX8357-D includes an index register (IR), which is stored the index data of internal
control register and GRAM. When DCX=”L”, the command via DBI interface write into register.
When DCX=”H”, GRAM data via R2Ch register can be written through data bus. When thedata is written into the GRAM from the MPU, it is first written into the write-data latch and thenautomatically written into the GRAM by internal operation. Data is read through the read-datalatch when reading from the GRAM.
When data is read from the GRAM to the MPU, it is first read from GRAM to the read-datalatch and then data is read to MPU through the read-data latch in next read operation.
Therefore, the read data in data bus in first read operation is invalid, and the read data is valid
from second read in data bus.

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4.1MIPI DBI-B interface
The selection of DBI interface IM2~IM0 pin to select DBI interface mode. The parallelinterface timing diagram is described in Figure 4.1 and Figure 4.2.

Figure 4.1: DBI-B system interface protocol, write to register or GRAM

Figure 4.2: DBI-B system interface protocol, read from register or GRAM

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DBI TYPE-B 8-bit Parallel Bus System Interface
The DBI-B system 8-bit bus parallel data transfer can be used by setting “IM2-0” pins
to “011”. The Figure4.3 is the example of interface with 8-bit DBI-B microcomputer
system interface.

Figure 4.3: Example of DBI-B System 8-bit bus Interface

8-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colors, 3AH=”05h”
There is 1-pixel (3 sub-pixels) per 2-bytes.
RESX 1‘ ’
CSX
DCX
WRX
RDX

1‘ ’

DB7

0

DB6

0

DB5

1

DB4

0

DB3

1

DB2

1

DB1

0

DB0

0

Pixel n+1

Pixel n16-bits

16-bits

16-to-18 bit Conversion
18-bits

Frame
Memory18-bits

R1 G1 B1 R2 G2 B2 R3 G3 B3Figure 4.4: Write data for RGB 5-6-5 (65k colors) bits input in 8-bit parallel interface

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8-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 3AH=”06h”
There is 1-pixel (3 sub-pixels) per 3-bytes.

Figure 4.5: Write data for RGB 6-6-6-bits(262k colors) input in 8-bit parallel interface

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8-bits data bus for 24-bits/pixel (RGB 8-8-8-bits input), 16M-colors, 3AH=”07h”
There is 1-pixel (3 sub-pixels) per 3-bytes.
NRESET ‘
1’
NCS
DNC
NWR
NRD

‘
1’

DB7

0

R1, Bit 7

G1, Bit 7

B1, Bit 7

R2, Bit 7

DB6

0

R1, Bit 6

G1, Bit 6

B1, Bit 6

R2, Bit 6

DB5

1

R1, Bit 5

G1, Bit 5

B1, Bit 5

R2, Bit 5

DB4

0

R1, Bit 4

G1, Bit 4

B1, Bit 4

R2, Bit 4

DB3

1

R1, Bit 3

G1, Bit 3

B1, Bit 3

R2, Bit 3

DB2

1

R1, Bit 2

G1, Bit 2

B0, Bit 2

R2, Bit 2

DB1

0

R1, Bit 1

G1, Bit 1

B0, Bit 1

R2, Bit 1

DB0

0R1, Bit 0

G1, Bit 0

B0, Bit 0

Pixel nR2, Bit 0

Pixel n+1

24-to-18 conversion
18- bits

Frame
Memory18- bits

R1 G1 B1 R2 G2 B2 R3 G3 B3Figure 4.6: Write data for RGB 8-8-8-bits(16M colors) input in 8-bit parallel interface

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DBI TYPE-B 9-bit Parallel Bus System Interface
The DBI-B system 9-bit bus parallel data transfer can be used by setting “IM2-0” pins
to “001”. The Figure4.7 is the example of interface with 9-bit DBI-B microcomputer
system interface.

Figure 4.7: Example of DBI-B system 9-bit bus interface

9-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colors, 3AH=”05h”
There is 1-pixel (3 sub-pixels) per 2-bytes.
RESX 1‘ ’
CSX
DCX
WRX
RDX

1‘ ’

DB8

x

DB7

0

DB6

0

DB5

1

DB4

0

DB3

1

DB2

1

DB1

0

DB0

0

Pixel n+1

Pixel n16-bits

16-bits

16-to-18 bit Conversion
18-bits

Frame
Memory18-bits

R1 G1 B1 R2 G2 B2 R3 G3 B3Figure 4.8: Write data for RGB 5-6-5 (65k colors) bits input in 9-bit parallel interface

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9-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 3AH=”06h”
There is 1-pixel (3 sub-pixels) per 2-bytes
RESX 1‘ ’
CSX
DCX
WRX
RDX

1‘ ’

DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Pixel nPixel n+1

18-bits

Frame
Memory18-bits

R1 G1 B1 R2 G2 B2 R3G3 B3Figure 4.9: Write data for RGB 6-6-6 (262k colors) bits input in 9-bit parallel interface

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DBI TYPE-B 16-bit Parallel Bus System Interface
The DBI-B system 16-bit bus parallel data transfer can be used by setting “IM2-0”pins to “010”.
The Figure4.10 is the example of interface with 16-bit DBI-B microcomputer system interface.

Figure 4.10: Example of DBI-B System 16-bit bus interface

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16-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colors, 3AH=”05h”
There is 1-pixel (3 sub-pixels) per 1-byte

Figure 4.11: Write data for RGB 5-6-5 (65k colors) bits input in 16-bit parallel interface

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in whole or in part without prior written permission of Himax.

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16-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 3AH=”06h”
There are 2-pixels (6 sub-pixels) per 3-bytes
RESX 1‘ ’
CSX
DCX
WRX
RDX

1‘ ’

DB15

-

DB14

-

DB13

-

DB12

-

DB11

-

DB10

-

DB9

-

DB8

-

DB7

0

DB6

0

DB5

1

DB4

0

DB3

1

DB2

1

DB1

0

DB0

0

Frame
MemoryPixel nPixel n+1

18-bits

18-bits

R1 G1 B1 R2 G2 B2 R3 G3 B3Figure 4.12: Write data for RGB 6-6-6 (262k colors) bits input in 16-bit parallel interface

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16-bits data bus for 18-bits/pixel (RGB 8-8-8-bits input), 16M-colors, 3AH=”07h”
There are 2-pixels (6 sub-pixels) per 3-bytes
NRESET 1‘ ’
NCS
DNC
NWR
NRD

1‘ ’

DB15

-

DB14

-

DB13

-

DB12

-

DB11

-

DB10

-

DB9

-

DB8

-

DB7

0

DB6

0

DB5

1

DB4

0

DB3

1

DB2

1

DB1

0

DB0

0

Pixel nPixel n+1

24-to-18 bit Conversion
18-bits

Frame
Memory18-bits

R1 G1 B1 R2 G2 B2 R3 G3 B3Figure 4.13: Write data for RGB 8-8-8 (16M colors) bits input in 16-bit parallel interface

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DBI TYPE-B 18-bit Parallel Bus System Interface
The DBI-B system 18-bit bus parallel data transfer can be used by setting “IM2-0”pins
to “000” and register setting DB_EN=’0’. The Figure 4.14 is the example of interface
with 18-bit DBI-B microcomputer system interface.

Figure 4.14: Example of DBI-B system 18-bit parallel bus interface

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18-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 3AH=”06h”
There is 1-pixel (6 sub-pixels) per 1-byte

Figure 4.15 Write data for RGB 6-6-6 (262k colors) bits input in 18-bit parallel interface

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DBI TYPE-B 24-bit Parallel Bus System Interface
The DBI-B system 24-bit bus parallel data transfer can be used by setting “IM2-0”pins
to “000” and register setting DB_EN=’1’. The Figure 4.16 is the example of interface
with 24-bit DBI-B microcomputer system interface.

Figure 4.16: Example of DBI-B system 24-bit parallel bus interface

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24-bits data bus for 24-bits/pixel (RGB 8-8-8-bits input), 16M-colors, 3AH=”07h”
There is 1-pixel (8 sub-pixels) per 1-byte
RESX ‘
1’
CSX
DCX
WRX
RDX

‘
1’

DB23

-

R1 , Bit 7

R2 , Bit 7

R3 , Bit7

R4 , Bit 7

DB22

-

R1 , Bit 6

R2 , Bit 6

R3 , Bit6

R4 , Bit 6

DB21

-

R1 , Bit 5

R2 , Bit 5

R3 , Bit5

R4 , Bit 5

DB20

-

R1 , Bit 4

R2 , Bit 4

R3 , Bit4

R4 , Bit 4

DB19

-

R1 , Bit 3

R2 , Bit 3

R3 , Bit 3

R4 , Bit 3

DB18

-

R1 , Bit 2

R2 , Bit 2

R3 , Bit 2

R4 , Bit 2

DB17

-

R1 , Bit 1

R2 , Bit 1

R3 , Bit 1

R4 , Bit 1

DB16

-

R1 , Bit 0

R2 , Bit 0

R3 , Bit 0

R4 , Bit 0

DB15

-

G1 , Bit 7

G2 , Bit 7

G3 , Bit 7

G4 , Bit 7

DB14

-

G1 , Bit 6

G2 , Bit 6

G3 , Bit 6

G4 , Bit 6

DB13

-

G1 , Bit 5

G2 , Bit 5

G3 , Bit 5

G4 , Bit 5

DB12

-

G1 , Bit 4

G2 , Bit 4

G3 , Bit 4

G4 , Bit 4

DB11

-

G1 , Bit 3

G2 , Bit 3

G3 , Bit 3

G4 , Bit 3

DB10

-

G1 , Bit 2

G2 , Bit 2

G3 , Bit 2

G4 , Bit 2

DB9-

G1 , Bit 1

G2 , Bit 1

G3 , Bit 1

G4 , Bit 1

DB8-

G1 , Bit 0

G2 , Bit 0

G3 , Bit 0

G4 , Bit 0

DB70

B1 , Bit 7

B2 , Bit 7

B3 , Bit 7

B4 , Bit 7

DB6

0

B1 , Bit 5

B2 , Bit 6

B3 , Bit 6

B4 , Bit 6

DB5

1

B1 , Bit 5

B2 , Bit 5

B3 , Bit 5

B4 , Bit 5

DB40

B1 , Bit 4

B2 , Bit 4

B3 , Bit 4

B4 , Bit 4

DB3

1

B1 , Bit 3

B2 , Bit 3

B3 , Bit 3

B4 , Bit 3

DB2

1

B1 , Bit 2

B2 , Bit 2

B3 , Bit 2

B4 , Bit 2

DB1

0

B1 , Bit 1

B2 , Bit 1

B3 , Bit 1

B4 , Bit 1

DB00

B1 , Bit 0

B2 , Bit 0

B1 , Bit 0

B4 , Bit 0

Pixel nPixel n+1

Pixel n+2

Pixel n+3

24-to-18 conversion
18- bits

Frame
Memory18- bits

R1 G1 B1 R2 G2 B2 R3 G3 B3Figure 4.17 Write data for RGB 8-8-8 (16M colors) bits input in 24-bit parallel interface

Himax Confidential
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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Parallel Interface Data Color Coding
Data Color Coding for GRAM data Write- Parallel 8-Bits Bus Interface (IM2,IM1,IM0=”011”)
RegisterCommand

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x

x

x

x

x

x

x

x

x

x

0

0

1

0

1

1

0

0

3AH

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x

R4
G2
R5
G5
B5
R7
G7
B7

R3
G1
R4
G4
B4
R6
G6
B6

R2
G0
R3
G3
B3
R5
G5
B5

R1
B4
R2
G2
B2
R4
G4
B4

R0
B3
R1
G1
B1
R3
G3
B3

G5
B2
R0
G0
B0
R2
G2
B2

G4
B1
x
x
x
R1
G1
B1

G3
B0
x
x
x
R0
G0
B0

05h

06h

07h

Command2CH
Color
65K-Color(1-pixel/ 2-bytes)
262K-Color(1-pixel/ 3bytes)
16M-Color(1-pixel/ 3bytes)

Table 4.2: 8-bit interface GRAM write table- Parallel 9-Bits Bus Interface (IM2,IM1,IM0=”001”)
RegisterCommand

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x

x

x

x

x

x

x

x

x

x

0

0

1

0

1

1

0

0

3AH

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
R5
G2

R4
G2
R4
G1

R3
G1
R3
G0

R2
G0
R2
B5

R1
B4
R1
B4

R0
B3
R0
B3

G5
B2
G5
B2

G4
B1
G4
B1

G3
B0
G3
B0

05h
06h

Register
2CH
Color
65K-Color(1-pixel/ 2-bytes)
262K-Color(1-pixel/ 2bytes)

Table 4.3: 9-bit interface GRAM write table- Parallel 16-Bits Bus Interface (IM2,IM1,IM0=”010”)
RegisterCommand

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x

x

x

x

x

x

x

x

x

x

0

0

1

0

1

1

0

0

3AH
05h

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x
x
x
x
x
x
x

x
x
x
x
x
x
x

R4
R5
B5
G5
R7
B7
G7

R3
R4
B4
G4
R6
B6
G6

R2
R3
B3
G3
R5
B5
G5

R1
R2
B2
G2
R4
B4
G4

R0
R1
B1
G1
R3
B3
G3

G5
R0
B0
G0
R2
B2
G2

G4
x
x
x
R1
B1
G1

G3
x
x
x
R0
B0
G0

G2
G5
R5
B5
G7
R7
B7

G1
G4
R4
B4
G6
R6
B6

G0
G3
R3
B3
G5
R5
B5

B4
G2
R2
B2
G4
R4
B4

B3
G1
R1
B1
G3
R3
B3

B2
G0
R0
B0
G2
R2
B2

B1
x
x
x
G1
R1
B1

B0
x
x
x
G0
R0
B0

06h

07h

Command2CH
Color
65K-Color
262K-Color(2-pixels/ 3bytes)
16M-Color(2-pixels/ 3bytes)

Table 4.4: 16-bit interface GRAM write table- Parallel 18-Bits Bus Interface (IM2,IM1,IM0=”000”and DB_EN=’0’ )DB4 DB3

DB2 DB1

DB0

0

0

1

0

0

DB4 DB3

DB2 DB1

DB0

Register
2CH
Color

B4

B2

B0

262K-Color

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

3AH
06h

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8 DB7

DB6 DB5

R5

G2

G0

x

x

x

R4

x

R3

R2

x
R1

x
R0

x
G5

x
G4

x

DB8 DB7

DB6 DB5

RegisterCommand

x

G3

0
G1

1
B5

1
B3

B1

Table 4.5: 18-bit interface GRAM write table- Parallel 24-Bits Bus Interface (IM2,IM1,IM0=”000” and DB_EN=’1’)
Register DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Command
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
1
0
1
1
0
0

3Ah
07h

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R7

G0

B7

B6

B5

B4

B3

B2

B1

B0

R6

R5

R4

R3

R2

R1

R0

G7

G6

G5

G4

G3

G2

G1

Register
2Ch
Color
16M-Color

Table 4.6: 24-bit interface GRAM write table

Himax Confidential
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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Data Color Coding for RAM data Read
- Parallel 8-Bits Bus Interface (IM2,IM1,IM0=”011”)
RegisterCommand

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x

x

x

x

x

x

x

x

x

x

0

0

1

0

1

1

1

0

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
R5
G5
B5

x
R4
G4
B4

x
R3
G3
B3

x
R2
G2
B2

x
R1
G1
B1

x
R0
G0
B0

x
x
x
x

x
x
x
x

Read
Data Format

Command
2EH
ColorDummy Read
262K-Color(1-pixel/ 3bytes)

Table 4.7: 8-bit parallel interface GRAM read table- Parallel 16-Bits Bus Interface (IM2,IM1,IM0=”010”)
RegisterCommand

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x

x

x

x

x

x

x

x

x

x

0

0

1

0

1

1

1

0

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x
x
x
x

x
x
x
x

x
R5
B5
G5

x
R4
B4
G4

x
R3
B3
G3

x
R2
B2
G2

x
R1
B1
G1

x
R0
B0
G0

x
x
x
x

x
x
x
x

x
G5
R5
B5

x
G4
R4
B4

x
G3
R3
B3

x
G2
R2
B2

x
G1
R1
B1

x
G0
R0
B0

x
x
x
x

x
x
x
x

Read
Data Format

Command
2EH
ColorDummy Read
262K-Color(2-pixels/ 3bytes)

Table 4.8: 16-bit parallel interface GRAM read table- Parallel 9-Bits Bus Interface (IM2,IM1,IM0=”001”)
RegisterCommand

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x

x

x

x

x

x

x

x

x

x

0

0

1

0

1

1

1

0

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x
x
x

x
x
x

x
x
x

x
x
x

x
x
x

x
x
x

x
x
x

x
x
x

x
x
x

x
R5
G2

x
R4
G1

x
R3
G0

x
R2
B5

x
R1
B4

x
R0
B3

x
G5
B2

x
G4
B1

x
G3
B0

Read
Data Format

Register
2EH
Color
Dummy Read
262K-Color(1-pixel/ 2bytes)

Table 4.9: 9-bit parallel interface GRAM read table- Parallel 18-Bits Bus Interface (IM2,IM1,IM0=”000” and DB_EN=’0’)RegisterCommandRead
Data Format

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x

x

x

x

x

x

x

x

x

x

0

0

1

0

1

1

1

0

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x
R5

x
R4

x
R3

x
R2

x
R1

x
R0

x
G5

x
G4

x
G3

x
G2

x
G1

x
G0

x
B5

x
B4

x
B3

x
B2

x
B1

x
B0

Register
2EH
Color
Dummy Read
262K-Color

Table 4.10: 18-bit parallel interface GRAM read table- Parallel 24-Bits Bus Interface (IM2,IM1,IM0=”000” and DB_EN=’1’)
Register DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Command
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
1
0
1
1
1
0

Read
Data
FormatDB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
x

x

x

x

x

x

R7

R6

R5

R4

R3

R2

x

x

x

x

x

x

x

x

G7

G6

G5

G4

G3

G2

x

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

x

x

x

x

x

x

x

x

x

B7

B6

B5

B4

B3

B2

Register
2Eh
Color
Dummy Read
262K-Color

Table 4.11: 24-bit parallel interface GRAM read table

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

4.2Serial data transfer interface (MIPI DBI TYPE-C)
The HX8357-D00/D01 supports DBI Type C option 1(3-wire) and option 3(4-wire) serial datatransfer interface, the interface selection by setting IM2-0 pins, The IM2-0 set “101” is selectoption1 3 wire serial bus. The IM2-0 set “111” is select option3 4 wire serial bus.
The 3 wire serial bus is use: chip select line (CSX), serial input/output data (SDA) and theserial transfer clock line (WRX_SCL).
The 4 wire serial bus is use: chip select line (CSX), data/command select (DCX), serial
input/output data (SDA/SDO) and the serial transfer clock line (WRX_SCL).

4.2.1 Serial data write mode
The 3-Pin serial data packet contains a control bit D/CX and a transmission byte If D/CX islow, the transmission byte is command byte. If D/CX is high, the transmission byte is stored in
to command register or GRAM. The MSB is transmitted first. The serial interface is initialized
when CSX is high. In this state, SCL clock pulse or serial input/output data (SDA/SDO) haveno effect. A falling edge on CSX enables the serial interface and indicates the start of datatransmission.

Figure 4.18: DBI type C – serial interface protocol 3 wire/ 4 wire, write mode

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Temporary DATA SHEET V00

4.2.2 Read operation in serial peripheral interface
In serial peripheral interface read operation, the host controller first has to send a commandand then the following byte is transmitted to host controller in the SDA. The read mode has
two type command data read (8-/Over 8-bit) and one type GRAM data read.

Figure 4.19: Command read operation in serial peripheral interface

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Temporary DATA SHEET V00

4.2.3 DBI TYPE-C interface data color coding
There are two types data format to write display data at Serial data bus Interface and it is assame as 8-bit bus Interface.

Figure 4.20: Write data for RGB 5-6-5-bit input of DBI TYPE-C OPTION 1

Figure 4.21: Write data for RGB 5-6-5-bit input of DBI TYPE-C OPTION 3
SCL
SDA

1

R15 R14 R13 R12 R11 R10

1

G15 G14 G13 G12 G11 G10

1

B15

G3

B3

B14 B13

B12

B11

B10

18-bit

GRAM

R1

G1

B1

R2

G2

B2

R3

Figure 4.22: Write data for RGB 6-6-6-bit input of DBI TYPE-C OPTION 1

Figure 4.23: Write data for RGB 6-6-6-bit input of DBI TYPE-C OPTION 3

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Register Command
3Ah
05h

06h

D7
0
R4

D6
0
R3

D5
1
R2

D4
0
R1

D3
1
R0

D2
1
G5

D1
0
G4

D0
0
G3

G2

G1

G0

B4

B3

B2

B1

B0

R5
G5
B5

R4
G4
B4

R3
G3
B3

R2
G2
B2

R1
G1
B1

R0
G0
B0

x
x
x

x
x
x

Command2CH
65K-Color(1-pixel/ 2-transfer)262K-Color(1-pixel/ 3-transfer)

Table 4.12: DBI TYPE-C interface GRAM write table

Himax Confidential
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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

4.2.4 Break and pause sequences
If there is a break on data transmission when transmit a command before a whole byte has
been completed, then the display module will have reset the interface such that it will beready to receive the same byte re-transmitted when the chip select line (CSX) is next
activated. See the following figure.

Figure 4.24: Display module data transfer recovery

If a one or more parameter command is being sent and a break occurs while sending any
parameter before the last one and if the host then sends a new command rather thanretransmitting the parameter that was interrupted, then the parameters that were successfully
sent are stored and the parameter where the break occurred is rejected. The interface isready to receive next byte as shown:

Figure 4.25: Break during parameter

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320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

The host processor can pause a write sequence by pulling the CSX signal high between
command or data bytes. The display module shall wait for the host processor to drive CSX
low before continuing the write sequence at the point where the sequence was paused.

Figure 4.26: Display module data transfer pause

There are 4 cases where there is possible to see this kind of pause:
1. Command – Pause – Command
2. Command – Pause – Parameter
3. Parameter – Pause – Command
4. Parameter – Pause – Parameter

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4.3MIPI DPI interface (display pixel interface)
The HX8357-D00/D01 uses 16, 18, 24-bit parallel DPI interface which includes: HSYNC,
VSYNC, DE, PCLK, DB23~DB0. The interface is active after Power On sequence. Pixel clock(PCLK) is running all the time without stopping and it is used to entering HSYNC, VSYNC, DE
and DB17~DB0 –lines states when there is a rising edge of the PCLK. The PCLK cannot be
used as continue internal clock for other functions of the display module e.g. Sleep In –mode
etc. Vertical synchronization (VSYNC) is used to tell when there is received a new frame ofthe display. This is negative (‘-‘, ‘0’, low) active and its state is read to the display module by arising edge of the PCLK-line. Horizontal synchronization (HSYNC) is used to tell when there
is received a new line of the frame. This is negative (‘-‘, ‘0’, low) active and its state is read tothe display module by a rising edge of the PCLK-line. Data enable (DE) is used to tell when
there is received RGB information that should be transferred on the display. This is positive(‘+’, ‘1’, high) active and its state is read to the display module by a rising edge of the
PCLK-line. DB pin 24 bit: DB23-DB16(R7-R0), DB15-DB8(G7-G0) and DB7-DB0(B7-B0);18
bit: DB17-DB12(R5-R0), DB11-DB6(G5-G0) and DB5-DB0(B5-B0); 16 bit: DB17-DB13(R4R0), DB11-DB6(G5-G0) and DB5-DB1(B4-B0); are used to tell what is the information of theimage that is transferred on the display (when DE =1 and there is a rising edge of PCLK).
DB17~DB0 – lines can be set to “0” (low) or “1” (high). These lines are read by a rising edgeof the PCLK-line.
The pixel clock cycle is described in the following figure.

Figure 4.27: PCLK cycle

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General timing diagram

Figure 4.28: General timing diagram
1 Frame

VBP

480

1

Panel
Display
VSYNC

Display

Area

HSYNC
DE
Start to latch data

PCLK
HBP
HSYNC
PCLK
DE
Data Bus

D1

D2

D318

D319

D320

Figure 4.29: DPI timing diagram

The image information must be correct on the display, when the timings are in range on theinterface. However, the image information can be incorrect on the display, when timings areout of the range on the interface (Out of the range timings cannot cause any damage on thedisplay module or it cannot cause any damage on the host side). The correct image
information must be displayed automatically (by the display module) on the next frame(vertical sync.), when there is returned from out of the range to in range interface timings.

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DPI interface data color coding

The MIPI DPI interface includes three types which are 16-/ 18-bit data format by register 3Ah(set_pixel_format) to select.
Register
3Ah

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

50h

R4

R3

R2

R1

R0

60h

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B4

B3

B2

B1

B0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

DB0

DPI Interface
mode

B0

18-bit 262K-Color

16-bit 65K-Color

Table 4.13: 16-/18- DPI color mapping
Register
3Ah
70h

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

R7

R6

R5

R4

R3

R2

R1

R0

G7

G6

G5

G4

G3

G2

G1

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DPI Interface
mode

G0

B7

B6

B5

B4

B3

B2

B1

B0

24-bit 16M-Color

Table 4.14: 24-DPI color mapping
PCLK
D17,R4

R 1, BIT4
BIT4

R 2, BIT4
BIT4

R 3, BIT4
BIT4R 4 , BIT4
BIT4

R 5 , BIT4BIT4

D16,R3

R 1, BIT3
BIT3

R 2, BIT3
BIT3

R 3, BIT3
BIT3

R 4 , BIT3
BIT3

R 5 , BIT3
BIT3

D15,R2

R 1, BIT2
BIT2

R 2, BIT2
BIT2

R 3, BIT2
BIT2

R 4 , BIT2
BIT2

R 5 , BIT2
BIT2

D14,R1

R 1, BIT1
BIT1

R 2, BIT1
BIT1

R 3, BIT1
BIT1

R 4 , BIT1
BIT1

R 5 , BIT1
BIT1

D13,R0R 1, BIT0
BIT0

R 2, BIT0
BIT0

R 3, BIT0
BIT0

R 4 , BIT0
BIT0

R 5 , BIT0
BIT0

D11,G5G 1 , BIT5
BIT 5

G 2, BIT5
BIT 5

G 3, BIT5
BIT 5

G 4, BIT5
BIT 5

G 5, BIT5
BIT 5

D10,G4G 1 , BIT4
BIT 4

G 2, BIT4
BIT 4

G 3, BIT4
BIT 4

G 4, BIT4
BIT 4

G 5, BIT4
BIT 4

D9,G3

G 1 , BIT3
BIT 3

G 2, BIT3
BIT 3

G 3, BIT3
BIT 3

G 4, BIT3
BIT 3

G 5, BIT3
BIT 3

D8,G2

G 1 , BIT2
BIT 2

G 2, BIT2
BIT 2

G 3, BIT2
BIT 2

G 4, BIT2
BIT 2

G 5, BIT2
BIT 2

D12

D7,G1

G 1 , BIT1
BIT 1

G 2, BIT1
BIT 1

G 3, BIT1
BIT 1

G 4, BIT1
BIT 1

G 5, BIT1
BIT 1

D6,G0

G 1 , BIT0
BIT 0

G 2, BIT0
BIT 0

G 3, BIT0
BIT 0

G 4, BIT0
BIT 0

G 5, BIT0
BIT 0

D5,B4

B 1, BIT4
BIT4

B 2, BIT4
BIT4

B 3 , BIT4BIT4

B 4 , BIT4
BIT4

B 5 , BIT4
BIT 4

D4,B3

B 1, BIT3
BIT3

B 2, BIT3
BIT3

B 3 , BIT3
BIT3

B 4 , BIT3
BIT3

B 5 , BIT3
BIT 3

D3,B2

B 1, BIT2
BIT2

B 2, BIT2
BIT2

B 3 , BIT2
BIT2

B 4 , BIT2
BIT2

B 5 , BIT2
BIT 2

D2,B1

B 1, BIT1
BIT1

B 2, BIT1
BIT1

B 3 , BIT1
BIT1

B 4 , BIT1
BIT1

B 5 , BIT1
BIT 1

D1,B0

B 1, BIT0
BIT0

B 2, BIT0
BIT0

B 3 , BIT0
BIT0

B 4 , BIT0
BIT0

B 5 , BIT0
BIT 0

16Bits

16BitsD0
16Bits16-bit to 18-bit data mapping operation
18BitsPixels on
the display

R
1

18Bits
G
1

B
1

R
2

18Bits
G
2

B
2

R
3

G
3

B
3

Figure 4.30: 16-bit data bus color order on DPI interface

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PC LK
D 17,R 5

R 1 , BIT 5

R 2 , BIT 5

R 3 , BIT 5

R 4 , BIT 5

R 5 , BIT 5

D 16,R 4

R 1 , BIT 4

R 2 , BIT 4

R 3 , BIT 4

R 4 , BIT 4

R 5 , BIT 4

D 15,R 3

R 1 , BIT 3

R 2 , BIT 3

R 3 , BIT 3

R 4 , BIT 3

R 5 , BIT 3

D14,R 2R 1 , BIT 2

R 2 , BIT 2

R 3 , BIT 2

R 4 , BIT 2

R 5 , BIT 2

D13,R 1R 1 , BIT 1

R 2 , BIT 1

R 3 , BIT 1

R 4 , BIT 1

R 5 , BIT 1

D12,R 0R 1 , BIT 0

R 2 , BIT 0

R 3 , BIT 0

R 4 , BIT 0

R 5 , BIT 0

D 11,G 5

G 1 , BIT 5

G 2 , BIT 5

G 3 , BIT 5

G 4 , BIT 5

G 5 , BIT 5

D 10,G 4

G 1 , BIT 4

G 2 , BIT 4

G 3 , BIT 4

G 4 , BIT 4

G 5 , BIT 4

D 9,G 3G 1 , BIT 3

G 2 , BIT 3

G 3 , BIT 3

G 4 , BIT 3

G 5 , BIT 3

D 8,G 2G 1 , BIT 2

G 2 , BIT 2

G 3 , BIT 2

G 4 , BIT 2

G 5 , BIT 2

D 7,G 1G 1 , BIT 1

G 2 , BIT 1

G 3 , BIT 1

G 4 , BIT 1

G 5 , BIT 1

D 6,G 0G 1 , BIT 0

G 2 , BIT 0

G 3 , BIT 0

G 4 , BIT 0

G 5 , BIT 0

D5,B5

B 1 , BIT 5

B 2 , BIT 5

B 3 , BIT 5

B 4 , BIT 5

B 5 , BIT 5

D4,B4

B 1 , BIT 4

B 2 , BIT 4

B 3 , BIT 4

B 4 , BIT 4

B 5 , BIT 4

D3,B3

B 1 , BIT 3

B 2 , BIT 3

B 3 , BIT 3

B 4 , BIT 3

B 5 , BIT 3

D2,B2

B 1 , BIT 2

B 2 , BIT 2

B 3 , BIT 2

B 4 , BIT 2

B 5 , BIT 2

D1,B1

B 1 , BIT 1

B 2 , BIT 1

B 3 , BIT 1

B 4 , BIT 1

B 5 , BIT 1

D0,B0

B 1 , BIT 0

B 2 , BIT 0

B 3 , BIT 0

B 4 , BIT 0

B 5 , BIT 0

18BitsPixels on
the display

18B its

18Bits

R
1

G
1

B
1

R
2

G
2

B
2

R
3

G
3

B
3

Figure 4.31: 18-bit data bus color order on DPI interface

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DPI interface displaying moving pictures can be selected to by register DM and RM.
RM The bit is used to select an interface for the Frame Memory access operation. The Frame
Memory is accessed only via the interface defined by RM bit. Because the interface can beselected separately from display operation mode, writing data to the Frame Memory is
possible via system interface when RM = 0, even in the DPI display operation.
RM setting is enabled from the next frame. Wait 1 frame to transfer data after setting.
RM
0
1

Interface for RAM access
DBI Interface (MPU)
DPI Interface (RGB)

DM bit is used to select display operation mode. The setting allows switching between display
operation in synchronization with internal oscillation clock, VSYNC, or DPI signal.
DM
0
1

Operation Mode
Internal clock operation(displaying still pictures)
DPI interface(displaying moving pictures)

Display Mode
Internal oscillation clock
DPI interface
Frame Memory AccessSetting (RM)
MPU interface(RM=0)DPI interface(RM=1)

Display Operation Mode
(DM)
Internal clock operation(DM=0)DPI interface(DM=1)

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4.4 DSI system interface (For HX8357-D01 only)
The selection of interface is by IM(2-0) =”110 “, the DSI specifies the interface between a hostprocessor and a peripheral such as a display module. Figure 4.30 shows a simplified DSIinterface. From a conceptual viewpoint, a DSI-compliant interface also sends pixels orcommands to the peripheral, and can read back status or pixel information from theperipheral. The main difference is that DSI serializes all pixel data, commands, and events
that. DSI-compliant peripherals support Command Mode. Which mode is used depends on
the architecture and capabilities of the peripheral. The mode definitions reflect the primary
intended use of DSI for display.
Command Mode refers to operation in which transactions primarily take the form of sending
Commands and data to a peripheral, such as a display module, that incorporates a display
controller. The display controller may include local registers and a frame buffer. Systems
using Command Mode write to, and read from, the registers and frame buffer memory. The
host processor indirectly controls activity at the peripheral by sending commands, parametersand data to the display controller. The host processor can also read display module status
information or the contents of the frame memory. Command Mode operation requires abidirectional interface.

Figure 4.32: DSI transmitter and receiver interface

Please refer to “MIPI Alliance Standard for DSI” for DSI detailed specifications.

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4.4.1 DSI layer definitions
According Figure 4.31 DSI transmitter and Receiver interface to understand simple interface
block diagram. Then under diagram is internal block for DSI which include four types: PHY
Layer, Lane Management Layer, Low level protocol and Application Layer.
The PHY Layer specifies the characteristics of transmission medium and electricalparameters for signaling the timing relationship between clock and Data Lanes.
The Lane Management Layer specifies DSI is Lane-scalable for increased performance. The
data signals maybe transmission through one or more channel depending on the bandwidth
requirements of the application.
The Protocol Layer specifies at the lowest level, DSI protocol specifies the sequence andvalue of bits and bytes traversing the interface. It specifies how bytes are organized into
defined groups called packets.
The Application Layer describes higher-level encoding and interpretation of data contained in
the data stream. The DSI specification describes the mapping of pixel values, commands andcommand’s parameters to bytes in the packet assembly.

Figure 4.33: Transmitter and receiver interface

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4.4.2 DSI protocol
The protocol layer appends packet-protocol information and headers. The receiver side of a
DSI Link performs the converse of the transmitter side, decomposing the packet into parallel
data, signal events and commands. The DSI protocol permits multiple packets which is usefulfor events such as peripheral initialization, where many registers may be loaded separate
write commands at system startup. Figure 4.34 illustrates multiple HS Transmission packets.

LPS：Low power state
SOT：Start of Transmission
SP：Short Packet
LP：Long Packet
EOT：End of Transmission
Figure 4.34: DSI multiple HS transmission packets

The packet includes two types which are Long packet and short packet. The first byte of thepacket, the Data Identifier (DI), includes information specifying the length of the packet.
Command Mode systems send commands and an associated set of parameters, with thenumber of parameters depending on the command type.
Short packets specify the payload length using the Data Type field and are from two to nine
bytes in length. Short packet is used for most Command Mode commands and associatedparameters. Where short packets format include an 8-bit Data ID followed by zero to sevenbytes and an 8-bit ECC. Figure 4.33 shows the structure of the Short packet.

DI(Data ID): Contain Virtual Channel Identifier and Data Type.
ECC(Error Correction Code): The Error Correction Code allows single-bit errors to be corrected and2-bit errors to be detected in the Packet Header.
Figure 4.35: Structure of the short packet

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Long packets specify the payload length using a two-byte Word Count field and then the
payload maybe from 0 to 65,541 bytes in length. Long packets permit transmission of large
blocks of pixel or other data.. Figure 4.43 shows the structure of the Long packet. Long
Packet Header composed of three elements: an 8-bit Data Identifier, a 16-bit Word Count,and 8-bit ECC. The Packet Footer has one element, a 16-bit checksum. Long packets can befrom 6 to 65,541 bytes in length.
Where 65,541 bytes = (216-1) + 4 bytes PH + 2 bytes PF

DI (Data ID)：
：Contain Virtual Channel Identifier and Data Type.
WC (Word Count)：：The receiver use WC to define packet end.
ECC (Error Correction Code)：：The Error Correction Code allows single-bit errors to be corrected and2-bit errors to be detected in the Packet Header.
PF(Packet Footer)：：Mean 16-bit Checksum.
Figure 4.36: Structure of the long packet

According to packet form, basic elements include DI and ECC. Figure 4.44 the shows format
of Data ID.
DI7

DI6

VC (Virtual Channel)

DI5

DI4

DI3

DI2

DI1

DI0

DT (Data Type)DI[7:6]  These two bits identify the data as directed to one of four virtual channels.
DI[5:0]: These six bits specify the Data Type, which specifies the size, format and, in some cases, theinterpretation of the packet contents.
Figure 4.37: Format of data ID

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Due to Data Type (DT) mean format of transmission type, Figure 4.36 show Short- /Long-packet transmission command sequence.
Long packet write Command / Parameters / Pixel Datas

Short packet write Command / Parameters

Figure 4.38: Show short- / long-packet transmission command sequence

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4.4.2.1 Processor to peripheral direction packets data types
The set of transaction types sent from the host processor to a peripheral, such as a display
module, are shown in Table 4.12 Data Types for Processor-sourced Packets.
Data type, hex

Data type, binary

01h00 0001

Sync Event, V Sync Start

Short

11h

01 0001

Sync Event, V Sync End

Short

21h

10 0001

Sync Event, H Sync Start

Short

31h

11 0001

Sync Event, H Sync End

Short

02h

00 0010

Color Mode (CM) Off Command

Short

12h

01 0010

Color Mode (CM) On Command

Short

22h

10 0010

Shut Down Peripheral Command

Short

32h

11 0010

Turn On Peripheral Command

Short

06h

00 0110DCS READ, no parameters

Short

37h

11 0111

Set Maximum Return Packet Size

Short

09h

00 1001

Null Packet, no data

Long

19h

01 1001

Blanking Packet, no data

Long

39h

11 1001

DCS Long Write/write_LUT Command Packet

Long

0Eh

00 1110

Packed Pixel Stream, 16-bit RGB, 5-6-5 Format

Long

1Eh

01 1110Long

2Eh

10 11103Eh

11 1110

Packed Pixel Stream, 18-bit RGB, 6-6-6 Format
Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6
FormatPacked Pixel Stream, 24-bit RGB, 8-8-8 Format

X0h and XFh, unspecified

xx 0000
xx 1111

Description packet

DO NOT USE
All unspecified codes are reserved

Size

Long
Long
-

Table 4.15: Data types for processor-sourced packets

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Under tables list all detail function of all data types
Sync event (H start, H end, V start, V end), data type=xx 0001 (x1h)
Data type, hex
Function description
01h
V Sync start, Start of VSA pulse.
11h
V Sync End, End of VSA pulse.
21h
H Sync Start, Start of HSA pulse.
31h
H Sync End, End of HSA pulse.

Number of bytes
2 bytes(DI + ECC)

Note: V Sync Start and V Sync End event represents the start and end of the VSA, respectively. Similarly H Sync Start
and H Sync End event represents the start and end of the HSA, respectively.

Color mode status (Color Mode On, Color Mode Off)
Data type, hex
Function description
Color Mode On that switches a Video Mode display module to
02ha low-color mode for power saving.
Color Mode Off that switches a Video Mode display module
12hfrom low-color display to normal display.
Display status (shutdown command, turn-on command )Data type, hex
Function description
Shutdown Peripheral command that turns off the display in a
22hVideo Mode display for power saving.
Turn On Peripheral command that turns on the display in Video32h
Mode display for normal display.

Number of bytes
2 bytes(DI + ECC)

Number of bytes
2 bytes(DI + ECC)

Note: When use shutdown command, interface shall remain powered in order to receive the turn-on, or wake-up, command.

DCS command setting
Data type, hex
Function description
DCS Read command, the returned data may be of Short or
06h
Long packet format.
39h

DCS Long Write/ Write _ LUT Command is used to send larger
blocks of data to a display module that implements the Display
Command Set.

Number of bytes
3 bytes(DI + DCS CMD. + ECC)
Up to 65541 bytes( DI + WC + ECC+ DCS CMD.
+ Payload DATA + PF )Note: (1) For write part, If DCS Short Write command, followed by BTA, the peripheral shall respond with ACK when
without error was detected in the transmission (Host  Slave). Unless an error was detected, the peripheral shall
respond with Acknowledge with Error Report.
(2) When use DCS Read Command, the Set Max Return Packet Size command will limit the size of returning
packets.
(3) The peripheral shall respond to DCS Read Command Request in one of the following ways:◆ If an error was detected by the peripheral, it shall send Acknowledge with Error Report. So the peripheral
shall transmit the requested READ data packet with suitable ECC in the same transmission.
◆ If no error was detected by the peripheral, it shall send the requested READ packet (Short or Long) withappropriate ECC and Checksum, if either or both features are enabled.
WC(4) One byte <= Length of payload DATA <= 2 -1

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Return packet size setting
Data type, hex
Function description
Set Maximum Return Packet Size that specifies the maximum
37hsize of the payload in a Long packet transmitted from peripheral
back to the host processor.

Number of bytes
4 bytes(DI + WC + ECC)

Note: The two-byte value is transmitted with LS byte first. And during a power-on or Reset sequence, the Maximum Return
Packet Size shall be set by the peripheral to a default value of one.

Variable data packet
Data type, hex
Function description
Null Packet is a mechanism for keeping the serial Data Lane(s)09hin High-Speed mode while sending dummy data.

Number of bytes
Up to 65541 bytes( DI + WC + ECC+ DCS CMD.
+ Payload DATA +PF )Blanking packet is used to convey blanking timing information
in a Long packet.

19h

Note: (1) When Null Packet, the Payload Data belong “null” Data, actual data values sent are irrelevant because theperipheral does not capture or store the data.
(2) When Blanking packet, the packet represents a period between active scan lines of a Video Mode display,

Data stream format – 16bit Format
Data type, hex
Function description
Packed Pixel Stream 16-Bit Format is used to transmit image
data formatted as 16-bit pixels to a Video Mode display
0Eh
module. Pixel format is“(5 bits) red, (6 bits) green and (5 bits) blue”.

Number of bytes
Up to 65541 bytes( DI + WC + ECC+ DCS CMD.
+ Payload DATA + PF )1 byte 1 byte
D0

D7D0

R0

R4 G0

5b

G5 B0

6b

D7
B4

5b

Pixel 1

Data Type

Virtual Channel

1 byte2 bytes

1 byteWord Count

1 byte 1 byte

1 byte 1 byte

5b

5b

6b

5b

5b

Checksum

ECC

Pixel 1
PH (Packet Header)

6b

2 bytes

Pixel nVariable Payload data

PF (Packet Footer)

Note: Within a color component, the “LSB is sent first, the MSB last “.

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Data stream format – 18bit Format
Data type, hex
Function description
Packed Pixel Stream 18-Bit Format is used to transmit image
data formatted as 18-bit pixels to a Video Mode display
1Eh
module. Pixel format is“(6 bits) red, (6 bits) green and (6 bits) blue”.

Number of bytes
Up to 65541 bytes( DI + WC + ECC+ DCS CMD.
+ Payload DATA + PF )1 byte 1 byte
D0

D7

D0

D7

R0

R5 G0

G5 B0

B5

6b

6b

6b

Pixel 1
2 bytes

1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte
6b

Data Type

Virtual Channel

1 byte

6b

6b

6b

6b

6b

6b

6b

6b

6b

6b

6b

Word Count ECC

Pixel 2

Pixel 1

Pixel 3

Variable Payload Data (First 4 pixels packed at 9 bytes)

PH (Packet Header)

1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte
6b

6bPixel 4

6b

6b

6b

6b

6b

6b

6b

6b

6b

2 bytes

6b

Checksum

Pixel n-3

Pixel n-2

Pixel n-1

Pixel nVariable Payload Data (First 4 pixels packed at 9 bytes) PF (Packet Footer)
Note: Within a color component, the LSB is sent first and the MSB last and pixel boundaries only line up with byteboundaries every four pixels (nine bytes). Preferably, display modules employing this format have a horizontal extent(width in pixels) evenly divisible by four, so no partial bytes remain at the end of the display line data. It is possible tosend pixel data that represent a line width that is not a multiple of four pixels, but display logic on the receiver end shalldispose of the extra bits of the partial byte at the end of active display and ensure a “clean start” for the next line.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
Data stream format – 18bit Format
Data type, hex
Function description
Packed Pixel Stream 18-Bit Format, each R, G, or B color
component is one byte form, but the valid pixel bits occupy bits
2Eh
[7:2] and bits [1:0] of are ignored. Pixel format is “(6 bits) red,
(6 bits) green and (6 bits) blue”.

Number of bytes
Up to 65541 bytes( DI + WC + ECC+ DCS CMD.
+ Payload DATA + PF )1 byte 1 byte 1 byte
D0

D7 D0
R0

R5

6b

D7

D7 D0
G0

G5

B0

6b

B5

6b

Pixel 1

2 bytes

1 byte 1 byte 1 byte 1 byte
6b

Data Type

Virtual Channel

1 byte

6b

6b

6b

6b

Word Count ECC

6b

Checksum

Pixel 1
PH (Packet Header)

2 bytes

1 byte 1 byte 1 byte

Pixel nVariable Payload Data

PF (Packet Footer)

Note: Within a color component, the LSB is sent first, the MSB last and With this format, pixel boundaries line up with byteboundaries every three bytes.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
Data stream forma – 24bit Format
Data Type, Hex

3Eh

Function Description
Packed Pixel Stream 24-Bit Format is used to transmit
image data formatted as 24-bit pixels to a Video Modedisplay module. Pixel format is (8 bits) red, (8 bits)
green and (8 bits) blue.

Number of bytes
Up to 65541 bytes( DI + WC + ECC+ DCS CMD.
+ Payload DATA + PF )Note: Within a color component, the LSB is sent first, the MSB last and With this format, pixel boundaries line up withbyte boundaries every three bytes.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

4.4.2.2 Peripheral to processor (reverse direction)
All Command Mode systems require bidirectional capability for returning READ data, ACK or
error information to the host processor. Command Mode that use DCS shall have abidirectional data path. Short packets and the header of Long packets may use ECC andChecksum to provide a higher level of data integrity. The Checksum feature enables detectionof errors in the payload of Long packets. The packet structure for peripheral-to-processor
transactions is the same as for the processor-to-peripheral direction.
Peripheral-to-processor transactions are of four basic types:
A.

B.
C.

D.

Tearing Effect is a Trigger message sent to convey display timing information to the hostprocessor. Trigger messages ate signal byte packets sent by a peripheral’s PHY layer in
response to a signal form the DSI protocol layer.
Acknowledge is a Trigger Message sent when the current transmission, as well as all
preceding transmissions since the last peripheral to host communication.
Acknowledge and Error Report is a Short packet sent if any errors were detected inpreceding transmission from the host processor. Once reported, accumulated errors in
the error register are cleared.
Response to Read Request may be Short or Long packet that returns data requested by
the preceding READ command from the processor.

In general, if the host processor completes a transmission to the peripheral with BTA asserted,
the peripheral shall respond with one or more appropriate packet(s), and then return bus
ownership to the host processor. If BTA is not asserted following a transmission from the hostprocessor, the peripheral shall not communicate an Acknowledge or other error informationback to the host processor.
The processor-to-peripheral transactions with BTA asserted, can contain under form.
A.
B.
C.

D.

E.

Following a non-Read command in which no error was detected, the peripheral shall
respond with Acknowledge.
Following a Read request in which no error was detected, the peripheral shall send therequested READ data.
Following a Read request in which the ECC error was detected and corrected, thePeripheral shall send the requested READ data in a Long or Short packet, followed by a
4-byte (Acknowledge with Error Report) packet in the same LP transmission. The Error
Report shall have the ECC Error flag set.
Following a non-Read command in which the ECC error was detected and corrected,
the peripheral shall proceed to execute the command, and shall respond to BTA bysending a 4-byte (Acknowledge with Error Report) packet, the Error Report shall havethe ECC Error flag set.
Following any command in which SoT Error, SoT Sync Error, EoT Sync Error, LP
Transmit Sync Error, checksum error or DSI VC ID Invalid was detected, or the DSI
command was not recognized, the peripheral shall send a 4-byte Acknowledge with
Error Report response, with the appropriate error flags set in the two-byte error field.
Only the ACK/Error Report packet shall be transmitted; no read or write accesses shalltake place on the peripheral in response.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Which,A.
B.
C.

“Acknowledge” includes 2 bytes which are DI (VC + Acknowledge Data Type) and ECC.
“Acknowledge with Error Report” include 4 bytes which are DI, 2 bytes Error report and
ECC.
“Response to Read Request” contains 2 types which are Short packet and long packet.

An error report is comprised of two bytes following the DI byte, with an ECC byte following theerror report bytes. Table 4.16 shows the Error Report Bit Definitions. And Table 4.16 list
complete set of peripheral-to-processor Data Types.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Data type, hex
02h
08h
1Ch
21h
22h
Others (00h3Fh)

Description
SoT Error
SoT Sync Error
EoT Sync Error
Escape Mode Entry Command Error
Low-Power Transmit Sync Error
HS Receive Timeout Error
reserved
reserved
ECC Error, single-bit (detected and corrected)
ECC Error, multi-bit (detected, not corrected)
Checksum Error (long packet only)
DSI Data Type Not Recognized
DSI VC ID Invalid
reserved
reserved
reserved
Table 4.16: Shows the error report bit definitions
Data type,binary00 001000 1000
01 1100
10 0001
10 0010

Description packet

Acknowledge with Error Report
End of Transmission (EoT) packet
DCS Long READ Response
DCS Short READ Response, 1 byte returned
DCS Short READ Response, 2 bytes returned
Reserved
Table 4.17: Complete set of peripheral-to-processor data types

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Size
Short
Short
Long
Short
Short
-

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
Acknowledge types
Data type, hex
Function description
Get Acknowledge with Error report when Error occurs
02
from processor transmission.

Number of bytes
4 bytes

Note: When processor transmits complete Payload, following signal by BTA, peripheral must respond to processor.
With errorAcknowledge with error report, Without error Acknowledge.

DCS Read types
Data type, hex
21h, 22h

1Ch

Function description
This is the DCS Short Read Response, 1 or 2 bytes,
respectively.
This is the long-packet response to DCS Long Read
Request.

Number of bytes
4 bytes
Up to 65541 bytes( DI + WC + ECC + DCS
CMD. + Payload DATA +PF )Note: If the peripheral is Checksum capable, is shall return a calculated two-byte Checksum appended to the N-byte
payload data. If the peripheral does not support Checksum, it shall return 0000h.
If the DCS command itself is possibly corrupt, due to an uncorrectable ECC error, SoT or SoT Sync error, therequested READ data packet shall not be sent after the Acknowledge with Error Report packet be sent.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

5. Functional Description
5.1Display data GRAM mapping
The display data RAM stores display dots and consists of 2,764,800 bits (320x18x480bits). There is no restriction on access to the RAM even when the display data on thesame address is loaded to DAC. There will be no abnormal visible effect on the display
when there is a simultaneous Panel Read and Interface Read or Write to the same
location of the Frame Memory.

Every pixel (18-bit) data in GRAM is located by a (Page, Column) address (Y, X). By specifying thearbitrary window address CASET’s SC, EC and PASET’s SP, EP, it is possible to access the GRAM
by setting RAMWR or RAMRD commands from start positions of the window address.

5.1.1 Address counter (AC)The HX8357-D00/D01 contains an address counter (AC) which assigns address forwriting/reading pixel data to/from GRAM. The address pointers set the position of GRAM
whose addresses range:MV
0
1

X rangeY range
Panel resolution
0~319d.
0~479d.
320 RGBX480 dot
0~479d.
0~319d.
Table 5.1: Addresses counter range

Every time when a pixel data is written into the GRAM, the X address or Y address of AC will
be automatically increased by 1 (or decreased by 1), which is decided by the register (MV, MX
and MY bit) setting.
To simplify the address control of GRAM access, the window address function allows forwriting data only to a window area of GRAM specified by registers. After data is written to the
GRAM, the AC will be increased or decreased within setting window address-range which is
specified by the Column address register (start: SC, end: EC) or the Row address register(start: SP, end: EP). Therefore, the data can be written consecutively without thinking a data
wrap by those bit function.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

5.1.2 System interface to GRAM write direction
Data stream from MCU is likethis figure

BE
Figure 5.1: Image data sending order from hostThe data is written in the order illustrated above. The counter which dictates where in
the physical memory the data is to be written is controlled by MADTCL’s MV(B5),
MX(B6) and MY(B7) bits setting

Figure 5.2: MY,MX,MV Setting of GRAM control
MV
0
0
0
0
1
1
1
1

MX
0
0
1
1
0
0
1
1

MY
0
1
0
1
0
1
0
1

CASET
PASET
Direct to Physical Column PointerDirect to Physical Page PointerDirect to Physical Column PointerDirect to (479-Physical Page Pointer)
Direct to (319-Physical Column Pointer)
Direct to Physical Page PointerDirect to (319-Physical Column Pointer)
Direct to (479-Physical Page Pointer)
Direct to Physical Page PointerDirect to Physical Column PointerDirect to (479-Physical Page Pointer)
Direct to Physical Column PointerDirect to Physical Page PointerDirect to (319-Physical Column Pointer)
Direct to (479-Physical Page Pointer)
Direct to (319-Physical Column Pointer)
Table 5.2: MY.MX.MV Setting of GRAM address mapping

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

The following figure depicts the GRAM address update method with MV, MX and MY bit
setting.
Display
MADCTR
Data
parameter
Direction MV MX MY

Normal0

0

Image in the
Host

Image in the Driver (GRAM)

B

H/W Position (0,0)

B

X,Y address (0,0)
X: CASET
Y: RASET

0

E

E
B

Y-Invert

00

H/W Position (0,0)

1

X,Y address (0,0)
X: CASET
Y: RASET

E

B

E
B

X-Invert

0

1

H/W Position (0,0)

B

X,Y address (0,0)
X: CASET
Y: RASET0E

E
H/W Position (0,0)

B

X-Invert
Y-Invert

0

1

E

1

X,Y address (0,0)
X: CASET
Y: RASET

B

E
B

X-Y
Exchange

10

H/W Position (0,0)

B

X,Y address (0,0)
X: CASET
Y: RASET0E

E
H/W Position (0,0)

B

X-Y
Exchange
X-invert

1

0

1
X,Y address (0,0)
X: CASET
Y: RASETE
B

X-Y
ExchangeY-invert

1

1

H /W

Position (0,0)

1

B

X ,Y address ( 0, 0)
X : CASET
Y : RASETE
H/W Position (0,0)

B

1

B

0
E

X-Y
Exchange
X-invert
Y-invert

E

E

1
E

B

X,Y address (0,0)
X: CASET
Y: RASET

Table 5.3: Address direction settings

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

5.1.3 Source, gate and memory map

Pixel1

Source Out

S1

S2

Pixel2S3

S4

S5

Pixel319

S955

S6

S956

Pixel320

S958

S957

S959

S960

RGB Order

RA
MY=0

MY=1

0
1
2
3
4
5
6
7
8
9
10
11
:
:
:
:
:
:
472
473
474
475
476
477
478
479

479
478
477
476
475
474
473
472
471
470
469
468
:
:
:
:
:
:
7
6
5
4
3
2
1
0

CA

MX=0
MX= 1

SA

:BGR=0:BGR=1

R0 5-0

:
:
:
:
:
:

G0 5-0

:
:
:
:
:
:

B0 5-0

:
:
:
:
:
:

R1 5-0

:
:
:
:
:
:

G1 5-0

:
:
:
:
:
:

B15-0

:
:
:
:
:
:

--

-------------

R318

5-0

G318

5-0

5-0

R319

5-0

G319

5-0

479

5-0

5
6

:
:
:
:
:
:

:
:
:
:
:
:

:
:
:
:
:
:

:
:
:
:
:
:

Display Pattern Data

1
318

ML=1

0
1

B319

2
3
4

--------0
319

B318

ML=0

:
:
:
:
:
:

:
:
:
:
:
:

RN 5-0 GN 5-0 BN 5-0

318
1

478
477
476
475
474

7
8

473
472
471

9
10
11
:
:
:
:
:
:
472

470
469
468
:
:
:
:
:
:
7

473
474

6
5

475
476
477

4
3
2

478
479

1
0

319
0

Note: RA = Row Address.
CA = Column Address.
SA = Scan Address.
MX = Mirror X-axis (Column address direction parameter), D6 parameter of Memory Access Control (R36h)
command
MY = Mirror Y-axis (Row address direction parameter), D7 parameter of Memory Access Control (R36h)
command
ML = Scan direction parameter, D4 parameter of Memory Access Control (R36h) command
BGR = Red, Green and Blue pixel position change, D3 parameter of Memory Access Control (R36h)
commandFigure 5.3: Memory map 320RGBx480 dot

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

5.1.4 Fully display, partial display, vertical scrolling display
5.1.4.1 Full display
Example: (1) 320RGBx480 dot display mode.
(2) NORON (Normal Display Mode On) instruction (R13h).
(3) SC=0x000h, EC=0x13Fh (R2Ah) and SP=0x000h, EP=0x1DFh (R2Bh), ML=0.

------1DA000H
1DB000H
1DC000H
1DD000H
1DE000H
1DF000H

13Eh
DB---DB
17 --- 000013EH
00113EH
00213EH
00313EH
00413EH
00513EH---------------------------------------------------------

13Fh
DB---DB
17 --- 000013FH
00113FH
00213FH
00313FH
00413FH
00513FH----------------------1DAh
1DBh
1DCh
1DDh
1DEh
1DFh

----------------

01hDB---DB
17 --- 0000001H
001001H
002001H
003001H
004001H
005001H-------

000h
001h
002h
003h
004h
005h

00h
DB---DB
17 --- 0000000H
001000H
002000H
003000H
004000H
005000H

GRAM

1DA001H
1DB001H
1DC001H
1DD001H
1DE001H
1DF001H-------------------------------------------------

1DA13EH
1DB13EH
1DC13EH
1DD13EH
1DE13EH
1DF13EH

1DA13FH
1DB13FH
1DC13FH
1DD13FH
1DE13FH
1DF13FH

Table 5.4: Memory map of full display

00

01 02 03 04 05

1 W1 X 1 Y 1Z

01 h

10 11

20

22 23
32

20

21 22

3 Y 3Z30

31 32

Y0 Y 1 Y 2 Y3

23

2X 2 Y2 Z
3 Y3 Z

320X480

Frame memory

Z0 Z1 Z 2 Z 3 Z4 Z 5320

4 8 0 li n es

4 8 0 li n es
1DEh

1W 1X 1Y 1 Z

LCD panel

WX WY WZ

X0 X1 X 2

1DFh

2 X 2 Y 2Z

0 V 0W 0X 0Y 0 Z

13 14

320X480X18bit

W0 W 11DDh

12WX WY WZ

W0W1

XW XX XY XZ

X 0 X1 X 2

XW XX XY XZ

1DDh

YW YX YY YZ

1DEh

Y0 Y 1 Y 2 Y 3ZV ZW ZX ZY ZZ

1DFh

Z 0 Z 1 Z 2 Z 3 Z4 Z5320

columns

13Fh

00 h

13Eh

0 V 0W 0 X 0 Y 0 Z

13Dh

12 13 14

21

01h

10 11

30 31

00h

02 03 04 05

13Eh

01

13Fh

00

13Dh

01h

01 h

00h
00 h

YW YX YY YZZV ZW ZX ZY ZZ

columns

Figure 5.4: Memory map of full display

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

5.1.4.2 Partial display
Example: (1) 320RGBx480 dot display mode.
(2) PLTON instruction (R12h).
(3) SR[15:0]=0002h, ER[15:0]=01DBh, ML=0.

000h
001h
002h
003h
004h
005h

00h
DB---DB
17 --- 0000000H
001000H
002000H
003000H
004000H
005000H

01h
DB---DB
17 --- 0000001H
001001H
002001H
003001H
004001H
005001H----------------------------------------------------------------------------------------

1DAh
1DBh
1DCh
1DDh
1DEh
1DFh

1DA000H
1DB000H
1DC000H
1DD000H
1DE000H
1DF000H

1DA001H
1DB001H
1DC001H
1DD001H
1DE001H
1DF001H-------------------------------------------------

1DA13EH
1DB13EH
1DC13EH
1DD13EH
1DE13EH
1DF13EH

1DA13FH
1DB13FH
1DC13FH
1DD13FH
1DE13FH
1DF13FH

GRAM-----------------

13Eh
DB---DB
17 --- 000013EH
00113EH
00213EH
00313EH
00413EH
00513EH

13Fh
DB---DB
17 --- 000013FH
00113FH
00213FH
00313FH
00413FH
00513FH

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

LCD panel
S/G pins

Pixel 1

Pixel 2---------

Pixel319

Pixel320

G1
G2
G3
G4
G5
G6

000000H
001000H
002000H
003000H
004000H
005000H

000001H
001001H
002001H
003001H
004001H
005001H-------------------------------------------------

00013EH
00113EH
00213EH
00313EH
00413EH
00513EH

00013FH
00113FH
00213FH
00313FH
00413FH
00513FH---------------------------------------

G475
G476
G477
G478
G479
G480

1DA000H
1DB000H
1DC000H
1DD000H
1DE000H
1DF000H

1DA001H
1DB001H
1DC001H
1DD001H
1DE001H
1DF001H-------------------------------------------------

1DA13EH
1DB13EH
1DC13EH
1DD13EH
1DE13EH
1DF13EH

1DA13FH
1DB13FH
1DC13FH
1DD13FH
1DE13FH
1DF13FH

Table 5.5: Memory map of partial display

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320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

5.1.4.3 Vertical scrolling display
The vertical scrolling display is specified by VSCRDEF instruction (R33h) and VSCRSADD
instruction (R37h).

Original

Scrolling
TFA

VSA

BFA

Figure 5.5: Vertical scrolling

When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=Panel total scan lines. In
this case, scrolling is applied as shown below.
Example 1 : (1) 320RGBx480 dot display mode.
(2) TFA=2,VSA=478,BFA=0 when MADCTL B4=0
(3) VSCRSADD=03h

13Fh

13Eh

13Dh

001h

000h

13Fh

13Eh

13Dh

001h

000h

S c r o l l a rea

S c r o l l ar e a = 4 7 8 l i n es

T o p f i x e d are a

Figure 5.6: Memory map of vertical scrolling example 1

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320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
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Example 2 : (1) 320RGBx480 dot display mode.
(2) TFA=2,VSA=476,BFA=2 when MADCTL B4=0
(3) VSCRSADD=03h
13Dh

13Eh

13Fh

13Dh

13Eh

13Fh

001h

000h

13Fh

13Dh

13Eh

001h

000h

Top
fixed
area
S c r o l l ar e a = 4 7 6 l i n es

S c r o l l a rea
Bottomfixed
area

Figure 5.7: Memory map of vertical scrolling example 2

Example 3 : (1) 320RGBx480 dot display mode.
(2) TFA=2,VSA=476,BFA=2 when MADCTL B4=0
(3) VSCRSADD=04h
001h

000h

13Fh

13Dh

13Eh

001h

000h

Top
fixed
area
S c r o l l ar e a = 4 7 6 l i n es

S c r o l l a rea
Bottomfixed
area

Figure 5.8: Memory map of vertical scrolling example 3

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Temporary DATA SHEET V00

Vertical Scroll Example
There are 2 types of vertical scrolling, which are determined by the commands “ Vertical
Scrolling Definition” (33h) and “Vertical Scrolling Start Address” (37h).
Case 1: TFA + VSA + BFA ≠ Panel scan lines
N/A. Do not set TFA + VSA + BFA≠Panel scan lines. In that case, unexpected picture will beshown.
Case 2: TFA + VSA + BFA = Panel scan lines ( Scrolling)
Example 1 : (1) 320RGBx480 dot display mode.
(2) When TFA=0, VSA=480, BFA=0 and VSCRSADD=40. MADCTL parameter
B4=”0”

Figure 5.9: Display of vertical scroll example 1

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320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
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Example 2 : (1) 320RGBx480 dot display mode.
(2) TFA=60, VSA=420, BFA=0 and VSCRSADD =160. MADCTRL parameter
B4=”1”

Figure 5.10: Display of vertical scroll example 2

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5.2Tearing effect output line
The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal
can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the
Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command.
The signal can be used by the MPU to synchronize Frame Memory Writing when displaying
video images.

5.2.1 Tearing effect line modes
Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:tVdh= The LCD display is not updated from the Frame Memory
tvdl = The LCD display is updated from the Frame Memory (except Invisible Line – see below)

Figure 5.11: TE mode 1 output

Under Mode1, the TE output timing will be defined by TSEL[15:0] setting.
Ex:
1. TSEL[15:0]=0, then TE signal will output after last Line finished.
2. TSEL[15:0]=2, then TE signal will output at second Line start.

Figure 5.12: TE delay output

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Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking
Information, there is one V-sync and 480 H-sync pulses per field.

thdh= The LCD display is not updated from the Frame Memory
thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)

Figure 5.13: TE mode 2 output

Note: During Sleep In Mode, the Tearing Output Pin is active Low

Figure 5.14: TE output waveform

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5.2.2 Tearing effect line timing
The Tearing Effect signal is described below.

Figure 5.15: Waveform of tearing effect signal
Idle Mode Off (Frame Rate = 60 Hz)
Symbol
tvdl
tvdh
thdl
thdh

Parameter

Spec.
Typ.

Min.
Max.
Vertical Timing Low Duration
Vertical Timing High Duration
1000
Horizontal Timing Low Duration
Horizontal Timing High Duration
500
Table 5.6: AC characteristics of tearing effect signal

Unit

Description

ms
µs
µs
µs

-

The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.

Figure 5.16: Timing of tearing effect signal

The Tearing Effect Output Line is fed back to the MPU and should be used as shown
below to avoid Tearing Effect:

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5.2.3 Example 1: MPU write is faster than panel read

MCU to Memory
1st

Time

320th

TE output signal
Time

Memory to LCD
Time
1st

Image on LCD

a

320th

b

c

d

Figure 5.17: Timing of MPU write is faster than panel read

Data write to Frame Memory is now synchronized to the Panel Scan. It should be
written during the vertical sync pulse of the Tearing Effect Output Line. This ensuresthat data is always written ahead of the panel scan and each Panel Frame refresh has
a complete new image:

Figure 5.18: Display of MPU write is faster than panel read

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320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
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5.2.4 Example 2: MPU write is slower than panel read

MCU to Memory
1st

Time

320th

TE output signal
Time

Memory to LCD
Time
1st

Image on LCD

a

320th

b

c

d

e

f

Figure 5.19: Timing of MPU write is slower than panel read

The MPU to Frame Memory write begins just after Panel Read has commenced i.e.
after one horizontal sync pulse of the Tearing Effect Output Line. This allows time forthe image to download behind the Panel Read pointer and finishing download during
the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory
write position.

Figure 5.20: Display of MPU write is slower than panel read

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320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
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5.3Checksums
The display module consists of two 8-bit checksum registers, which are used checksum
calculations for area registers (includes the frame memory), on the display module.
Command area registers are registers which values users can change a commanddirectly.
One of the checksum registers is “First Checksum” (FCS) and another is “Continue
Checksum” (CCS).
These register values are set to 00h as an initial value when there is started to calculate
a new checksum.
The display module is starting to calculate the new checksum after there is a write
access on command area registers. This means that read commands are not used as a
calculation starting trigger in this case.
The checksum calculation is always interrupted, when there is a new write access oncommand area registers.
The checksum calculation is also started from the beginning.
The result of the first finished checksum calculation is stored on the FCS register, which
value is kept until there is the new write access on area registers and the newchecksum value is calculated in the first time again.
The maximum time, when the FCS is readable, is 150ms after there is the last write
access on area registers.
The checksum calculation is continuing after the finished first checksum calculation
where the FCS has gotten the checksum value. These new checksum values arealways stored on CCS register (Old value is replaced a new one) after the lastcommand area register has been calculated to the checksum.
The maximum time, when the CCS is readable in the first time, is 300ms after there is
the last write access on command area registers.
There is always updated a checksum comparison bit (See section: “Read Display
Self-Diagnostic Result (0Fh)” and bit D0) when there is compared FCS and CCS
checksums after a new checksum value is stored on CCS.
The maximum time, when the comparison has been done between FCS and CCS in thefirst time, is 300ms then the comparison has been done in every 150ms (this is
maximum time).
Users can read FCS, CCS and Comparison bit D0 values. See section: “Read First
Checksum (AAh)”,“Read Continue Checksum (AFh)” and ”Read Display Self-Diagnostic Result (0Fh)”.
There can be an overflow during a checksum calculation. These overflow bits are notneeded to store anywhere. This means that these overflow bits can be ignored by thedisplay module.

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An example of the checksum calculation:
 Register Values: A1h, 12h, 81h, DEh, F2h
 Calculated Value: 304h (= A1h + 12h + 81h + DEh + F2h)
 Ignored Bits: 3h
 Stored Checksum: 04h
This checksum calculation function is only running in “Sleep Out” mode and it isstopped in “Sleep In” mode.

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320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
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Step
Note 1Time
Note 21

0

2

Temporary
Register

ActionFirst Checksum
Register (FCS)

Continue
Checksum
Register (CCS)

Comment

Initialization

Set to 00h

Set to 00h

Set to 00h

The last write action
on area registers => FCS
and CCS registers are
initialized.

0–
150ms

Counting Sum ofcommand Area
Registers

Counting--

The first register counting isrunning

3

150ms

Stores Sum ofRegisters on FCSRegister

Set to 00h after
Value is Moved to
FCS Register

Stores Sum of
Area Registers
on FCS Register-

The result of the first registercounting
is stored on the FCS
register. The result of the
FCS is available to the MCU.

4

150 –
300ms

Counting Sum ofcommand Area
Registers

Counting--

The second registercounting is running

5

300ms

1) Stores Sum ofRegisters on
CCS Register2) Compares Stored
FCS and CCS
ValuesSet to 00h after
Value is Moved to
CCS Register-

Area Registerson
CCS Register

6

300 –
450ms

Counting Sum ofcommand Area
Registers

Counting

-

-

7

450ms

1) Stores Sum ofRegisters on CCS
Register2) Compares Stored
FCS and CCS Values

8

450 –
600ms

Counting Sum ofcommand Area
Registers

9

600ms

10

etc

Stores Sum ofcommandStores Sum of

Set to 00h after
Value is Moved to
CCS Register-command

Counting--

Area Registers
on CCS Register

1) Stores Sum ofRegisters on CCS
Register2) Compares Stored
FCS and CCS Values

Set to 00h after
Value is Moved to
CCS Register-command

-

-

-

-

Stores Sum of
Area Registers
on CCS Register

The result of the comparison
is stored on separated
registers, which can readseparated readcommands. The result of the
CCS andcomparison result areavailable to the MCU.
The third register counting isrunning
The result of the comparison
is stored on separated
registers, which can readseparated readcommands. The latest resultof the CCS and comparison
result are available to the
MCU.
The fourth register counting
is running
The result of the comparison
is stored on separated
registers, which can readseparated readcommands. The latest resultof the CCS and comparison
result are available to the
MCU.
Same Sequence Countinuee.g. steps 4 and 5

Note: (1) This function is restarted at Step 1 if there is any write action on command area registers.
(2) These time can be shorter on the display module.

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320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
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5.4Oscillator
The HX8357-D00/D01 can oscillate an internal R-C oscillator for internal operation.
Because the tolerance of internal oscillator frequency is ±5%, it can be adjusted by
the UADJ [3:0] bits for initial 10MHz internal clock generation. With other dividers
setting, the 10MHz internal clock can be used to generate clock for other part of thechip using.
RGB Display Mode

PCLK

PWM_
PWM_CLK(for Backlight CABC)
CABC)

DM

Display
Controller

Internal Display Mode

Oscillator
Clock

10MHz
10MHz

fosc
UADJ[
UADJ[3:0]

DIV[
DIV[1:0]

5MHz

Frequency
Divider 1
FS0
FS0[7:0]

Step up Circuit 1( for VSP)
VSP)

Frequency
Divider 1
FS1
FS1[7:0]

Step up Circuit 3( for VSN)
VSN)

Frequency
Divider 1
FS2
FS2[7:0]

Step up Circuit 2( for VGH,
VGH,VGL)
VGL)

Figure 5.21: HX8357-D00/D01 internal clock circuit

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5.5Source driver
The HX8357-D00/D01 contains a 481 channels of source driver (normal S1~S480;
Zig-zag S1~S481) which is used for driving the source line of TFT LCD panel. The
source driver converts the digital data from GRAM into the analog voltage for 481
channels and generates corresponding gray scale voltage output, which can realize a
262k colors display simultaneously. Since the output circuit of this source driverincorporates an operational amplifier, a positive and a negative voltage can bealternately outputted from each channel.

Figure 5.22: Source channels of ZigZag inversion mode

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5.6Gate driver
The HX8357-D00/D01 contains a 480 gate channels of gate driver (G1~G480) which
is used for driving the gate. The gate driver level is VGH in scan line, the other lines is
VGL.
The HX8357-D00/D01 can set internal register SM_PANEL and GS_PANEL bit todetermine the pin assignment of gate. The SM_PANEL and GS_PANEL setting allows
changing the shift direction of gate outputs by connecting LCD panel with the
HX8357-D00/D01.
Scan direction

SM_PANEL GS_PANEL

G2
G4

OddG1
number line G3

Evennumber line

TFT panel
0

0

G478
G480

G477
G479

G1, G2, G3, G4,......,G477, G478, G479, G480
G2
G4

OddG1
number line G3

Evennumber line

TFT panel

0

1

G478
G480

G477
G479

G480, G479, G478, G477,......,G4, G3, G2, G1
G2

Evennumber line

TFT panel
G480

Odd number line G1
1

0
G479

G2, G4,...., G478, G480, G1, G3,....,G477, G479,
G2
TFT panel
Odd number line G1
1

1

Evennumber line

G480

G479

G479, G477,...., G3, G1, G480, G478,....,G4, G2,

Figure 5.23: Scan direction of Gate Driver

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320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
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5.7LCD power generation circuit
5.7.1 Power supply circuit
The power circuit of HX8357-D00/D01 is used to generate supply voltages for LCD
panel driving.
C12A

C13A

C4

C1

C12B
C14A
C5

Step up
Circuit 3

C14B
C6

C13B
Step up
Circuit 1

VSN

C11A
C2

C11B
VSP

VSPROUT

Reference
Voltage
Generation
CircuitVCI

C3

VSNROUTC10VSSA

HSI_LDO

VSSD

VSP
C9

NVDDDOUT

VDDD

Reference
Voltage
Generation
Circuit

VGH
Step up
Circuit 2

C8

VGL
C22B

C7

C22A

Figure 5.24: Block diagram of HX8357-D00/D01 power circuit

Specification of connected passive component
Capacitor
C1 (C13A/B)
C2 (C11A/B)
C3 (VSP)
C4 (C14A/B)
C5 (C12A/B)
C6 (VSN)
C7 (C22A/B)
C8 (VGH)
C9(VDDD)
C10(HSI_LDO)

Recommended voltage
10V
10V
10V
10V
10V
10V
16V
25V
6V
6V

D1 (VGL-VSSA)

Schottky Diode

Capacity
1 µF (B characteristics)
1 µF (B characteristics)
1 µF ~ 2.2uF (B characteristics)
1 µF (B characteristics)
1 µF (B characteristics)
1 µF~2.2uF (B characteristics)
1 µF (B characteristics)
1 µF (B characteristics)
1 µF (B characteristics)
1 µF (B characteristics)
VF < 0.4V / 20mA at 25°C, VR ≥30V
(Recommended diode: RB521S-30)

Note: If not use High speed interface (DSI), the capacitor of HSI_LDO can be removed.

Table 5.7 Adoptability of capacitor

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5.7.2 LCD power generation scheme
The boost voltage generated is shown as below.
VGH (10.
10.0V~14.
14.8V)VSP

DC/DC
converter

VSPROUT(VSPROUT(3.3V~5.8V)

VCI (2.3V ~ 4.8V)
IOVCC (1.65V
65V ~ 3.3V)
VDDD

VSSD,
VSSD,VSSA
DC/DC
converter

VCOM (-2.5V~0V)
NVDDDOUTVSNROUT(VSNROUT(-5.8V ~ -3.3V)

VSN

VGL (-7.5V~-12.
12.5V)

Figure 5.25: LCD power generation scheme

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5.8Gamma characteristic correction function
The HX8357-D00/D01 offers two kinds of Gamma adjustment ways to come to accord
with LC characteristic, one kind is through Source Driver directly, another one isadjusted by the digital gamma correction. The Gamma adjustment way is select byinternal register DGC_EN bit.
A) Gamma adjustment of Source DriverGary-scale of R

6

SourceDriverGary-scale of White

Gary-scale of G

Gamma
registerGary-scale of B

B) Gamma adjustment of Digital Gamma Correction

Gary-scale of R

6

R,G,B
Gamma
correction(LUT)

Dithering
8

6

SourceDriverGary-scale of G

Gary-scale of R

Gary-scale of G

Gamma
registerGary-scale of B

Gary-scale of B

Figure 5.26: Gamma adjustments different of source driver with digital gamma correction

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5.8.1 Gamma characteristic correction function
The HX8357-D00/D01 incorporates gamma adjustment function for the 262,144-color
display. Gamma adjustment operation is implemented by deciding the 16 grayscalelevels firstly in gamma adjustment control registers to match the LCD panel. These
registers are available both for positive polarities and negative polarities.
Gamma resister stream
The block consists of two gamma resister streams one is for positive polarity and theother is for negative polarity, each one including 16 gamma reference voltages.
VgP/N (0, 1, 2, 4, 6, 13, 20, 27, 36, 43, 50, 57, 59, 61, 63). Furthermore, the block hasa pin (VGS) to connect a variable resistor outside the chip for the variation between
panels, if needed.
VSPROUT

V0
1R
1R
1R

128 to 1
128
to 1
selector128
to 1
selector
128selector
to 1
128 to1selector
128selector
to 1
128 to 1
128 to 1 selector
selector
selector

V1
V2
V4
V6
V13
V20
V27

V36

168R/1R

1R
1R
1R

128 to 1
128
to 1
selector128
to 1
selector
128selector
to 1
128 to1selector
128selector
to 1
128 to 1
128 to 1 selector
selector
selector

V43
V50
V57
V59
V61
V62

6R

V63

VGS

V63

6R
1R
1R

128 to 1
128
to 1
selector128
to 1
selector
selector
128 to 1
128 to1selector
128selector
to 1
128 to 1
128 toselector
1 selector
selector

V62
V50
V57
V59
V61
V43

1R

V36

168R/1R

1R
1R
1R

128 to 1
128
to 1
selector128
to 1
selector
128selector
to 1
128 to1selector
128selector
to 1
128 to 1
128 toselector
1 selector
selector

V27
V20
V13
V6
V4
V2
V1
V0

VSNROUT

Figure 5.27: Gamma resister stream and gamma reference voltage

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Figure 5.28: Relationship between GRAM data and output level (normal white panel REV_Panel=“0”)Himax Confidential
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Four-characteristic gamma curve selection
There are four kinds of Gamma Curve which can be selected by GAMSET command.
The parameter GC[7:0] is stored in internal register and used to select one set of
gamma correction register.

Figure 5.29: Gamma curve according to GC0 to GC3 bit

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5.8.2 Gray voltage generator for digital gamma correction

luminance of R
luminance of G
luminance of B

luminance of B

luminance of G

luminance of R

The HX8357-D00/D01 digital gamma correction can reach the independent GAMMA
curve of RGB. The HX8357-D00/D01 utilizes DGC_LUT (Digital Gamma Correction
Look Up Table) to change input data from 6-bit into 8-bit and sends 8-bit data to
Dithering circuit, and then drive Source Driver via Dithering circuit. The following of
the block diagram of the function.

Figure 5.30: Block diagram of digital gamma correction

There are 99 bytes DGC LUT to set R, G, B gamma independently. When
DGC_EN=1, R, G, B gamma will mapping V0, V2, V4, ...., V60, V62, V63 voltage tothe LUT register setting gray level voltage. V(2N+1) = (V(2N) + V(2N+2))/2 (N=0~30).
Parameter Input (6 bit)
1st
R00h
2nd
R02h
3rd
R04h
:
:
32nd
R62h
33rd
R63h
34th
G00h
35th
G02h
36th
G04h
:
:
65th
G62h
66th
G63h
67th
B00h
68th
B02h
69th
B04h
:
:
98th
B62h
99th
B63h

D7
R007
R017
R027
:
:
R317
R327
G007
G017
G027
:
:
G317
G327
B007
B017
B027
:
:
B317
B327

D6
R006
R016
R026
:
:
R316
R326
G006
G016
G026
:
:
G316
R326
B006
B016
B026
:
:
B316
B326

D5
R005
R015
R025
:
:
R315
R325
G005
G015
G025
:
:
G315
G325
B005
B015
B025
:
:
B315
B325

D4
R004
R014
R024
:
:
R314
R324
G004
G014
G024
:
:
G314
G324
B004
B014
B024
:
:
B314
B324

D3
R003
R013
R023
:
:
R313
R323
G003
G013
G023
:
:
G313
G323
B003
B013
B023
:
:
B313
B323

D2
R002
R012
R022
:
:
R312
R322
G002
G012
G022
:
:
G312
G322
B002
B012
B022
:
:
B312
B322

D1
R001
R011
R021
:
:
R311
R321
G001
G011
G021
:
:
G311
G321
B001
B011
B021
:
:
B311
B321

D0
Default
R000
00h
R010
08h
R020
10h
:
:
:
:
R310
F8h
R320
FCh
G000
00h
G010
08h
G020
10h
:
:
:
:
G310
F8h
G320
FCh
B000
00h
B010
08h
B020
10h
:
:
:
:
B310
F8h
B320
FCh

Gray Mapping
R_V0
R_V2
R_V4
:
:
R_V62
R_V63
G_V0
G_V2
G_V4
:
:
G_V62
G_V63
B_V0
B_V2
B_V4
:
:
B_V62
B_V63

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5.9Power function
5.9.1 Power on/off sequence
Power source IOVCC, VCI can be applied and powered down in any order.
IOVCC, VCI can be powered down in any order.
During power off, if LCD is in the Sleep Out mode, IOVCC, VCI must be powered
down minimum 120msec after NRESET has been released.
During power off, if LCD is in the Sleep In mode, IOVCC, VCI can be powered downminimum 0msec after NRESET has been released.
NCS can be applied at any timing or can be permanently grounded. NRESET haspriority over NCS.
Note: (1) There will be no damage to the display module if the power sequences are not met.
(2) There will be no abnormal visible effects on the display panel during the Power On/Off Sequences.
(3) There will be no abnormal visible effects on the display between end of Power on Sequence and before
receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence.
(4) If NRESET line is not held stable by host during Power on Sequence as defined in Sections 5.11.1.1 and5.11.1.2, then it will be necessary to apply a Hardware Reset (NRESET) after Host Power on Sequence
to ensure correct operation. Otherwise correct function is not guaranteed.

If NRESET line is not held stable by host during Power on Sequence as defined in
Sections 5.9.1.1 and 5.9.1.2 then it will be necessary to apply a Hardware Reset(NRESET) after Host Power on Sequence is complete to ensure correct operation,otherwise correct functionality is not guaranteed. The power on/off sequence isillustrated as below

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5.9.1.1

Case 1 – NRESET line is held high or unstable by host at power on

If NRESET line is held high or unstable by the host during Power On, then a
Hardware Reset must be applied after both IOVCC, VCI have been applied,otherwise correct functionality is not guaranteed. There is no timing restriction uponthis hardware reset.
tRPW= +/- no limit

tFPW= +/- no limit

IOVCC

VCI

Time when the latter signal rises up to 90% of its typical .
valueTime when the former signal falls down to 90% of its
Typical valuetRPWNCS = +/- no limit

NCS

tFPWNCS = +/- no limit

H or LtRPWNRES= + no limit

tFPWNRES1 = min120ms

NRESET(Power down insleep out mode)tRPWNRES= + no limit

NRESET( Power down insleep in mode)tFPWNRES2 = min0ns

tFPWNRES1 is applied to NRESET falling in the Sleep Out ModetFPWNRES2 is applied to NRESET falling in the Sleep In Mode

Note: Unless otherwise specified,
timings herein show cross point at 50% of signal/power level
Figure 5.31: Case 1 – NRESET line is held high or unstable by host at power on

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5.9.1.2

Case 2 – NRESET line is held low by host at power on

If NRESET line is held Low (and stable) by the host during Power On, then the
NRESET must be held low for minimum 10µsec after VCI have been applied.
tRPW= +/- no limit

tFPW= +/- no limit

IOVCC

VCI
Time when the latter signal rises up to 90% of its typical value

Time when the former signal falls down to 90% of its Typicalvalue

tRPWNCS= +/- no limittRPWNCS= +/- no limit

NCS.

H or LtFPWNRES1= min120ms
tRPWNRES = min10us

NRESET( Power down in
Sleep Out mode)tRPWNRES= min10us

NRESETtFPWNRES 2 = min0 ns(Power down in
Sleep In mode )tFPWNRES1 is applied to NREST falling in the Sleep Out ModetFPWNRES2 is applied to NREST falling in the Sleep In Mode

Note: Unless otherwise specified timings herein show cross point at 50% of signal/power level

Figure 5.32: NRESET line is held low by host at power on

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5.9.2 Power levels definition
5.9.2.1

General definition for power levels

Figure 5.33: Power flow chart for different power modes

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5.9.3 Deep standby mode set up flow

Display off flow

SLEEP IN
Set deep
SETEXTC(RB9h=FFh,83h,57h)
Set deep standby(DP_STB_S = "1", RB1h=01h)
Set deep standby(DP_STB = "1",RB1h=03h)
Set deep standby(DP_STB = "0",RB1h=01h)
Wait >20ms
Set deep standby(DP_STB_S = "0",RB1h=00h)

standbyReleasedeep
standbySLEEP OUT

Display on

Figure 5.34: Deep standby mode setting flow

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5.10Input / output pin state
5.10.1 Output pins
Output or Bi-directional pins
After Power On
After Hardware Reset
DB23 to DB0
High-Z (Inactive)
High-Z (Inactive)(Output driver)
SDO
High-Z (Inactive)
High-Z (Inactive)
CABC_ON
Low
Low
CABC_PWM
Low
Low
Table 5.8: Characteristics of output pins

5.10.2 Input pins
Input pins
RESX
CSX
WRX_SCLRDX
DCX
DIN_SDA
VSYNC
HSYNC
DE
PCLK
D[23:0]
OSC, IM2,
IM1,IM0
TEST3-1

During PowerOn Process
Input valid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid

AfterPower On
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid

After Hardware
Reset
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid

During Power
Off Process
Input valid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid

Input invalid

Input valid

Input valid

Input invalid

Input invalid
Input valid
Input valid
Table 5.9: Characteristics of input pins

Input invalid

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5.11Sleep out – command and self-diagnostic functions of display module
5.11.1 Register loading detection
Sleep Out-command (See section “Sleep Out (11h)”) is a trigger for an internalfunction of the display module, which indicates, if the display module loading functionof factory default values from EEPROM (or similar device) to registers of the display
controller is working properly.
There are compared factory values of the EEPROM and register values of the display
controller by the display controller. If those both values (EEPROM and register values)
are the same, there is an inverted (=increased by 1) bit, which is defined in section“Read Display Self-Diagnostic Result (0Fh)” (=RDDSDR) (The bit used for thiscommand is D7). If those both values are not the same, this bit (D7) is not inverted (=increased by 1). The flow chart for this internal function is shown as below.
Power on sequence
HW reset
SW reset

Sleep In (10h)Sleep OutMode

Sleep In
Mode

RDDSDR`s D7=0

Sleep Out (11h)Compares EEPROM and registervaluesLoad
EEPROM toregisterNO
If RGB_EN=1,
the block function
will pass

Are EEPROM andregister values the
same

YES

D7 inverted

Note: There is not compared and loaded register values, which can be changed by User (User area commands: 00h to
AFh and DAh to DDh), by the display module.

Figure 5.35: RDDSDR register loading detection flow

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5.11.2 Functionality detection
Sleep Out-command (“Sleep Out (11h)”) is a trigger for an internal function of thedisplay module, which indicates, if the display module is still running and meetsfunctionality requirements.
The internal function (= the display controller) is comparing, if the display module is still
meeting functionality requirements (e.g. booster voltage levels, timings, etc.) If
functionality requirement is met, there is an inverted (= increased by 1) bit, which
defined in section 6.2.13 “Read Display Self- Diagnostic Result (0Fh)” (= RDDSDR)(The used bit of this command is D6). If functionality requirement is not same, this bit(D6) is not inverted (= increased by 1). The flow chart for this internal function is shown
as below.

Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In –mode to Sleep Out-mode, before there is possible to check if User’s functionality requirements are met and a value of RDDSDR’s D6
is valid. Otherwise, there is 5msec delay for D6’s value, when Sleep Out –command is sent in Sleep Out -mode.

Figure 5.36: Functionality detection flow

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5.12Content adaptive brightness control (CABC) function
The general block diagram of the CABC and the brightness control is illustrated below:

VSYNC, HSYNC, DE ,PCLK ( in RGB IF)

Display Control
Signal Generator

Display Data
Generator

Image Data

Display Data
Contents Analysis

CABC Block

C[1:0]='00': Off
C[1:0]='01','10','11': On

Gain
CABC Gain/ DutyDuty

DBV[7:0] (R52h)( BL = `0`)
PWM_CLK(foscD)

PWM Clock
Devider

Brightness Control
Block

CABC_ PWM_ OUT( BL = `1`)

BCTRL='0': Off
BCTRL='1': On

Figure 5.37: CABC block diagram

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5.12.1 Module architectures
The HX8357-D00/D01 can support two module architectures for CABC operation.
The BL bit setting of R53h can be used to select used display module architecture.
White LED driver circuit for display backlight is located on the main PWB, not in thedisplay module both in architecture I and II.
• Architecture I

CABC_
PWM_OUT

1. BL =`1` of R53h
2. LED backlight brightness for thedi spl ay i s control led by external
output “CABC_PWM_OUT”.

• Architecture II

1. BL =`0` of R53h
2. LED backlight brightness data forthe display is read with DBV[7:0] bitsof R52h.
3. Read commands R52h should be
synchronized with V-sync.

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5.12.2 Brightness control block
There is an external output signal from brightness block, CABC_PWM_OUT, tocontrol the LED driver IC in order to control display brightness. The
CABC_PWM_OUT output active polarity is defined by INVPULS bit of RC9h.
The CABC_PWM_OUT output period is controlled by PWMDIV[2:0] andPWM_PERIOD[7:0] bits of RC9h setting.
Ex: PWM CLK is 5.5MHz (period 180ns), PWMDIV=110(divide by 64),
and PWM_PERIOD=00h (the value is 0+1).
 CABC_PWM_OUT period = 180ns x 64 x (1x256) = 2.95 ms
There are resister bits, DBV[7:0] of R51h, for display brightness of manual brightness
setting. The CABC_PWM_OUT duty is calculated as DBV[7:0]/255 x CABC duty
(generated after one-frame display data content analysis).
For ex: CABC_PWM_OUT period = 2.95 ms, and DBV[7:0](R51h) = ‘228DEC’ and
CABC duty is 74%. Then CABC_PWM_OUT duty = 228 / 255 x 74% ≡ 66.16%.
Correspond to the CABC_PWM_OUT period = 2.95 ms, the high-level of
CABC_PWM_OUT (high effective) = 1.95ms, and the low-level of CABC_PWM_OUT= 1.00ms.

One Period

ON

CABC_
PWM_OUT(INVPLUS=`1`)

Display
Brightness
OFF
Duty = 100%OFF

Duty = 100%
Maximum

Duty = 33%

Duty = 66.16%

Figure 5.38: CABC_PWM_OUT output duty

When Architecture II module is used (BL=’0’) with the example below, the
CABC_PWM_OUT is always output low (INVPULS=’1’) and the DBV[7:0](R52h) will
be read a value as 169DEC (169/255≡ 66.27%).

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5.12.3 Minimum brightness setting of CABC function
CABC function is automatically reduced backlight brightness based on image
contents. In the case of the combination with the CABC or manual brightness setting,display brightness is too dark. It must affect to image quality degradation. CABC
minimum brightness setting (CMB[7:0] bits of R5Eh) is to avoid too much brightness
reduction.
When CABC is active, CABC can not reduce the display brightness to less than
CABC minimum brightness setting. Image processing function is worked as normal,
even if the brightness can not be changed.
This function does not affect to the other function, manual brightness setting. Manualbrightness can be set the display brightness to less than CABC minimum brightness.
Smooth transition and dimming function can be worked as normal.
When display brightness is turned off (BCTRL=’0’ of R53h), CABC minimum
brightness setting is ignored. “CMB[7:0], Read CABC minimum brightness (R5Fh)“always read the setting value of “CMB[7:0], Write CABC minimum brightness(R5Eh)”.

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5.12.3.1 Register loading detection
Sleep Out command is a trigger for an internal function of the display module, whichindicates, if the display module loading function of factory default values from
EEPROM (or similar device) to registers of the display controller is working properly.
There are compared factory values of the EEPROM and register values of the display
controller by the display controller (1st step: compares register and EEPROM values,
2nd step: loads EEPROM values to registers). If those both values (EEPROM andregister values) are same, there is inverted (=increased by 1) a bit, which is defined incommand “Read Automatic Brightness Control Self-Diagnostic Result (68h)”(=RDABCSDR) (The used bit of this command is D7). If those both values are notsame, this bit (D7) is not inverted (= not increased by 1).
The flow chart for this internal function is following:

Note: There is not compared and loaded register values, which can be changed by User (User area commands: 00h
to AFh and DAh to DDh), by the display module

Figure 5.39: RDABCSDR register loading detection flow

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5.12.3.2 Functionality detection
Sleep Out command (See section 6.2.15, Sleep Out (11h)) is a trigger for an internalfunction of the display module, which indicates, if the display module is still runningand meets functionality requirements.
The internal function (= the display controller) is comparing, if the display module isstill meeting functionality requirements (e.g. booster voltage levels, timings, etc.). If
the functionality requirement is met, there is inverted (increased by 1) a bit, which
defined in command “Read Automatic Brightness Control Self-Diagnostic Result(68h)” (=RDABCSDR) (The used bit of this command is D6). If the functionality
requirement is not same, this bit (D6) is not inverted (=not increased by 1).
The flow chart for this internal function is following:

Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In –mode to
Sleep Out -mode, before there is possible to check if User’s functionality requirements are met and a valueof RDABCSDR’s D6 is valid. Otherwise, there is 5msec delay for D6’s value, when Sleep Out –command issent in Sleep Out -mode.

Figure 5.40: RDABCSDR functionality detection flow

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5.12.4 Display dimming
A dimming function (how fast to change the brightness from old to new level and what
are brightness levels during the change) is used when changing from one brightnesslevel to another to avoid flicker in the actual display module. This dimming function
curve is the same in increment and decrement directions.

Figure 5.41: Dimming function

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5.13OTP programing
5.13.1 OTP table
OTP_Index

01

0D

12
13
16
18
1A
7F

Table_
Index

01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
12
13
14
15
16
18
19
1A
7F
80
81
82
83
84
85

83
A1
A2
A3

D7

D6

D5

D4

D3

D2

D1

D0

ID1[7:0]ID2[7:0]ID3[7:0]
ID1[7:0]ID2[7:0]ID3[7:0]
ID1[7:0]ID2[7:0]ID3[7:0]
ID1[7:0]ID2[7:0]ID3[7:0]*
VCOM[6:0]*
VCOM[6:0]*
VCOM[6:0]*
VCOM[6:0]
SM_PANE
GS_PANE REV_PAN BGR_PAN***
SS_PANEL
L
L
EL
EL
*
*
TRI
XDK
BT[2:0]**
VRH[5:0]**
NVRH[5:0]
FS1[3:0]FS0[3:0]
SDO_EN
BYPASS
EPF[1:0]
*
*
*
RM
DM
*
*
*
*
DPL
HSPL
VSPL
EPL
ZINV
I_NW[1:0]**
N_NW[1:0]
DDB1[7:0]
DDB2[7:0]
DDB3[7:0]
DDB4[7:0]
VRP0[6:0]
VRP1[6:0]
VRP2[6:0]:
VRN14[6:0]
VRN15[6:0]
CGN[1:0]
CGN[1:0]
CGP[1:0]
CGP[1:0]

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5.13.2 OTP programming flow

Figure 5.42: OTP programming sequence

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6. Command Set
6.1Command set list
6.1.1 Standard command(Hex)

Operation
code

00

NOP

0

1

↑

01

SWRESET

0

1

0
04

RDDIDIF05

RDNUMPE

06

RDRED

07

RDGREEN

08

RDBLUE

0A

RDDPM

0B

RDDMADCTL

0C

RDDCOLMOD

0D

RDDIM

0E

RDDSM

0F

RDDSDR

10
11

SLPIN
SLPOUT

D/CX RDX WRX D7

D6

D5

D4

D3

D2

D1

D0

Function

0

0

0

0

0

0

0

0

↑

0

0

0

0

0

0

0

1

1

↑

0

0

0

0

0

1

0

1

1
1
1
1

↑
↑
↑
↑

1
1
1
1

x

x

x

x
x
ID1[7:0]ID2[7:0]ID3[7:0]

x

x

x

0

1

↑

0

0

0

0

0

1

0

1

1
1

↑
↑

1
1

x

x

x

x
x
P[7:0]

x

x

x

0

1

↑

0

0

0

0

0

1

1

0

1
1

↑
↑

1
1

x
R7

x
R6

x
R5

x
R4

x
R3

x
R2

x
R1

x
R0

0

1

↑

0

0

0

0

0

1

1

1

1
1

↑
↑

1
1

x
G7

x
G6

x
G5

x
G4

x
G3

x
G2

x
G1

x
G0

0

1

↑

0

0

0

0

1

0

0

0

1
1

↑
↑

1
1

x
B7

x
B6

x
B5

x
B4

x
B3

x
B2

x
B1

x
B0

0

1

↑

0

0

0

0

1

0

1

0

1
1

↑
↑

1
1

x
D7

x
D6

x
D5

x
D4

x
D3

x
D2

x
0

x
0

0

1

↑

0

0

0

0

1

0

1

1

1
1

↑
↑

1
1

x
D7

x
D6

x
D5

x
D4

x
D3

x
D2

x
0

x
0

0

1

↑

0

0

0

0

1

1

0

0

1
1

↑
↑

1
1

x
-

x
D6

x
D5

x
D4

x
-

x
D2

x
D1

x
D0

0

1

↑

0

0

0

0

1

1

0

1

1
1

↑
↑

1
1

x
D7

x
D6

x
D5

x
0

x
0

x
D2

x
D1

x
D0

0

1

↑

0

0

0

0

1

1

1

0

1
1

↑
↑

1
1

x
D7

x
D6

x
0

x
0

x
0

x
0

x
0

x
D0

0

1

↑

0

0

0

0

1

1

1

1

1
1
0
0

↑
↑
1
1

1
1
↑
↑

x
D7
0
0

x
D6
0
0

x
0
0
0

x
0
1
1

x
0
0
0

x
0
0
0

x
0
0
0

X
D0
0
1

No Operation
SoftwareReset
Read Display
Identification
Information
Dummy read
ID1
ID2
ID3
Read Numberof the Errors
on DSI
Dummy read
Read Red
ColourDummy readxx
Read Green
ColourDummy readxx
Read Blue
ColourDummy readxx
Read display
power mode
Dummy read
Read display
MADCTL
Dummy read
Read display
pixel format
Dummy read
Read display
image mode
Dummy read
Read display
signal mode
Dummy read
Read display
self-diagnostic
resultDummy read
Sleep In
Sleep Out

Default MESSI_ENB
(Hex)
‘0’
‘1’
-

Yes

-

Yes

00h
00h
00h

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

00h
00h
00h
00h
08h

Yes

00h

Yes

07h

Yes

00h

Yes

00h

Yes

Yes
00h
-

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

Yes
Yes

-P.105April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00(Hex)

Operation
code

12

PTLON

0

1

13

NORON

0

20

INVOFF

21
22
23

D7

D6

↑

0

0

1

↑

0

0

0

1

↑

0

0

INVON

0

1

↑

0

0

ALLPOFFALLPON

0
0
0
0
0
0

1
1
1
1
1
1

↑
↑
↑
↑
↑
↑

0
0
0
GC7
0
0

0
0
0
GC6
0
0

0

1

↑

0

0

1

1

↑

SC15

SC14

1

1

↑

SC7

SC6

1

1

↑

EC15

EC14

1

1

↑

EC7

EC6

0

1

↑

0

0

1

1

↑

SP15

SP14

1

1

↑

SP7

SP6

1

1

↑

EP15

EP14

1

1

↑

EP7

EP6

0
1
1

1
1
1

↑
↑
↑

0
D17
Dx7

0
D16
Dx6

Partial Mode
On
Normal01
00
1
1 display modeon
Display100
0
00
inversion off
Display10
0
001
inversion on
1
0
0
0
1
0 All Pixel Off
1
0
0
0
1
1 All Pixel On
1
0
0
0
1
1 Gamma Set
GC5 GC4 GC3 GC2 GC1 GC0 Gamma Curve
1
0
1
0
0
0 Display off
1
0
1
0
0
1 Display on
Column101010Address Set
ColumnSC13 SC12 SC11 SC10 SC9 SC8address start
ColumnSC5SC4SC3 SC2 SC1 SC0
address start
ColumnEC13 EC12 EC11 EC10 EC9 EC8address end
ColumnEC5EC4EC3 EC2 EC1 EC0address end
Row address
1
0
1
0
1
1
set
Row address
SP13 SP12 SP11 SP10 SP9 SP8
start
Row address
SP5
SP4 SP3 SP2 SP1 SP0
start
Row address
EP13 EP12 EP11 EP10 EP9 EP8end
Row address
EP5
EP4 EP3 EP2 EP1 EP0
end
1
0
1
1
0
0 Memory Write
D15
D14
D13 D12 D11 D10 Write data
Dx5
Dx4
Dx3 Dx2 Dx1 Dx0 Write data

1

1

↑

Dn7

Dn6

Dn5

Dn4

Dn3

0
1
1
1
1
0
1
1
1
1

1
↑
↑
↑
↑
1
1
1
1
1

↑
1
1
1
1
↑
↑
↑
↑
↑

0
x
D17
Dx7
Dn7
0

0
x
D16
Dx6
Dn6
0

1
x
D15
Dx5
Dn5
1

0
x
D14
Dx4
Dn4
1

1
x
D13
Dx3
Dn3
0

SR15
SR7
ER15
ER7

SR14
SR6
ER14
ER6

SR13
SR5
ER13
ER5

SR12
SR4
ER12
ER4

26

GAMSET

28
29

DISPOFFDISPON

2A

2B

2C

CASET

PASET

RAMWR

2E

RAMRD

30

PLTAR

D/CX RDX WRX

D5
0

D4
1

D3
0

D2
0

D1
1

D0

Function0

Dn2 Dn1 Dn0 Write data

1
1
0 Memory readxx
x Dummy read
D12 D11 D10 Read data
Dx2 Dx1 Dx0 Read data
Dn2 Dn1 Dn0
00
0 Partial Area
SR11 SR10 SR9 SR8 Start row
SR3 SR2 SR1 SR0 Start row
ER11 ER10 ER9 ER8 End row
ER3 ER2 ER1 ER0 End row

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

Default MESSI_ENB
(Hex)
‘0’
‘1’
-

Yes

-

Yes

-

Yes

-

Yes

01h
-

Yes
Yes
Yes
Yes
Yes

00h
00h

Yes

01h
67h
00h
00h

Yes

02h
7Fh
-

Yes

00h
00h
02h
7Fh

Yes

Yes

-P.106April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00(Hex)

Operation
Code

D/CX RDX WRX D7

D6

D5

D4

D3

D2

D1

0

1

1

0

0

1

1
1

1
1

↑
↑

0

1

↑

1

1

↑

0

1

↑

0

1

0

1

0

0

1

1
1
0

↑
↑
1

1
1
↑

x

x

x

x

x

0

1

0

1

1

1

↑

0

0

0
BCT
RL

x
x
DBV[7:0]
1
0
0

DD

BL

0

0

1

↑

0

1

0

1

0

0

1

1

1

↑

1

x

x

x

x

x

x

x

1

↑

1

0

0

x
BCTR
L

0

DD

BL

0

0

1

↑

1
1
1
1
1
1

1
1
1
1
1
1

↑
↑
↑
↑
↑
↑

0

TFA[15:8]
TFA[7:0]
VSA[15:8]
VSA[7:0]
BFA[15:8]
BFA[7:0]

VSCRDEF

34

TEOFF

0

1

↑

0

0

1

1

0

1

0

35

TEON

0

1

↑

0

0

1

1

0

1

0

36

MADCTL

0

1

↑

0

0

1

1

0

1

1

1

1

↑

B7

B6

B5

B4

B3

B2

0

0

1

↑

0

0

1

1

0

1

1

1
1
0
0
0
1
0
1
1
1
0
1
1
1
1
0
1
1

1
1
1
1
1
1
1
1
1
1
1
↑
↑
↑
↑
1
1
1

↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
↑
↑
↑

0
0
0
0
0
D17
Dx7
Dn7
0
x
D17
Dx7
Dn7
0

0

1

↑

0

VSCRSADD

38
39

IDMOFF
IDMON

3A

COLMOD3C

RAMWRCON

3E

RAMRDCON

44

TESL

45

GETSCAN

51

52

53

54

55

WRDISBV

0
0
0
D6
0
D16
Dx6
Dn6
0
x
D16
Dx6
Dn6
1

1

VSP[15:8]
VSP[7:0]
1
1
1
0
1
1
1
0
1
1
1
0
D5
D4
0
D2
1
1
1
1
D15 D14 D13 D12
Dx5 Dx4 Dx3 Dx2
Dn5 Dn4 Dn3 Dn2
1
1
1
1
x
x
x
x
D15 D14 D13 D12
Dx5 Dx4 Dx3 Dx2
Dn5 Dn4 Dn3 Dn20001
TELINE[15:8](8’b0)
TELINE[7:0](8’b0)

0
0
1
D1
0
D11
Dx1
Dn1
1
x
D11
Dx1
Dn1
0

0

0

0

0

1

SLN[15:8]
SLN[7:0]
0

1

0

1

0

0

0

DBV[7:0]

RDDISBV

WRCTRLDRDCTRLD

WRCABC

Function

Vertical
scrollingdefinition
Tearing Effect0Line OFF
Tearing Effect1
Line ON
Memory0 Access
Control0
Vertical
1 scrolling start
address
0 Idle mode off
1 Idle mode on0
D0
0 Memory write
D10
Dx0
Dn0
0 Memory readx Dummy read
D10
Dx0
Dn0
0 TESL
Reture thecurrent
1
scanline
SLN[15:0]
Write Display
1
Brightness
Read Display
0 Brightness
Value
x Dummy read1
Write CTRL
0 Display

0

33

37

D0

0

1

↑

0

1

0

1

0

1

1

1

↑

0

0

0

0

0

0

1

Read Control
Value Display
Dummy read-Write Adaptive0
1 Brightness
Control
CABC[1:0]-

Default MESSI_ENB
(Hex)
‘0’
‘1’
00h
00h
02h
80h
00h
00h

Yes

-

Yes

-

Yes

-

Yes

00h
Yes
00h
00h
07h
00h
00h

Yes
Yes
Yes

Yes

Yes

No

Yes

No

Yes

00h
00h
-

Yes

00h
Yes
00h
00h

Yes

-

Yes

00h
-

Yes

00h

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.107April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00(Hex)

Operation
Code

D/CX RDX WRX D7

0
56

5E

5F

68

70

1

↑

RDCABC

WRCABCMB

1
1

↑
↑

1
1

0

1

↑

1

1

↑

0

1

↑

1
1

↑
↑

1
1

0

1

↑

RDCABCMBRDABCSDR
1
1

↑
↑

1
1

0

1

↑

1
1
0
1
1
0
1
1
0
1
1
0
1
1

↑
↑
1
↑
↑
1
↑
↑
1
↑
↑
1
↑
↑

1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1

0

1

↑

1
1
0
1
1
0
1
1
0
1
1
0
1
1

↑
↑
1
↑
↑
1
↑
↑
1
↑
↑
1
↑
↑

1
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1

0

1

↑

1
1
0
1
1
0
1
1

↑
↑
1
↑
↑
1
↑
↑

1
1
↑
1
1
↑
1
1

RDBWLB

71

RDBkx

72

RDBky

73

RDWx

74

RDWy

75

RDRGLB

76

RDRx

77

RDRy

78

RDGx

79

RDRy

7A

RDBALB

7B

RDBx

7C

RDBy

D6

D5

D4

D3

D2

D1

D0

Function

Read
Adaptive
0
1
0
1
0
1
1
0 Brightness
Control
Content
x
x
x
x
x
x
x
x Dummy read
0
0
0
0
0
0
C1 C0
Write CABC
0
1
0
1
1
1
1
0 minimum
brightness
CMB[7:0]
Read CABC
0
1
0
1
1
1
1
1 minimum
brightness
x
x
x
x
x
x
x
x Dummy read
CMB[7:0]
Read
Automatic
Brightness
0
1
1
0
1
0
0
0
Control
Self-Diagnostic Result
x
x
x
x
x
x
x
x
D[7:6]
0
0
0
0
0
0
Read
0
1
1
1
0
0
0
0 Black/White
Low Bits
x
x
x
x
x
x
x
x Dummy read
Bkx1 Bkx0 Bky1 Bky0 Wx1 Wx0 Wy1 Wy0
0
1
1
1
0
0
0
1 Read Bkx
x
x
x
x
x
x
x
x Dummy read
Bkx9 Bkx8 Bkx7 Bkx6 Bkx5 Bkx4 Bkx3 Bkx2
0
1
1
1
0
0
1
0 Read Bky
x
x
x
x
x
x
x
x Dummy read
Bky9 Bky8 Bky7 Bky6 Bky5 Bky4 Bky3 Bky2
0
1
1
1
0
0
1
1 Read Wx
x
x
x
x
x
x
x
x Dummy read
Wx9 Wx8 Wx7 Wx6 Wx5 Wx4 Wx3 Wx2
0
1
1
1
0
1
0
0 Read Wy
x
x
x
x
x
x
x
x Dummy read
Wy9 Wy8 Wy7 Wy6 Wy5 Wy4 Wy3 Wy2
Read
0
1
1
1
0
1
0
1 Red/Green
Low Bits
x
x
x
x
x
x
x
x Dummy read
Rx1 Rx0 Ry1 Rx0 Gx1 Gx0 Gy1 Gy0
0
1
1
1
0
1
1
0 Read Rx
x
x
x
x
x
x
x
x Dummy read
Rx9 Rx8 Rx7 Rx6 Rx5 Rx4 Rx3 Rx2
0
1
1
1
0
1
1
1 Read Ry
x
x
x
x
x
x
x
x Dummy read
Ry9 Ry8 Ry7 Ry6 Ry5 Ry4 Ry3 Ry2
0
1
1
1
1
0
0
0 Read Gx
x
x
x
x
x
x
x
x Dummy read
Gx9 Gx8 Gx7 Gx6 Gx5 Gx4 Gx3 Gx2
0
1
1
1
1
0
0
1 Read Gy
x
x
x
x
x
x
x
x Dummy read
Gy9 Gy8 Gy7 Gy6 Gy5 Gy4 Gy3 Gy2
Read
0
1
1
1
1
0
1
0 Biue/AColour
Low Bits
x
x
x
x
x
x
x
x Dummy read
Bx1 Bx0 By1 Bx0 Ax1 Ax0 Ay1 Ay0
0
1
1
1
1
0
1
1 Read Bx
x
x
x
x
x
x
x
x Dummy read
Bx9 Bx8 Bx7 Bx6 Bx5 Bx4 Bx3 Bx2
0
1
1
1
1
1
0
0 Read By
x
x
x
x
x
x
x
x Dummy read
By9 By8 By7 By6 By5 By4 By3 By2-Default MESSI_ENB
(Hex)
‘0’
‘1’

Yes
00h
-

Yes

00h
Yes
00h

Yes
00h
Yes
-

Yes

Yes

Yes

Yes

Yes
-

Yes

Yes

Yes

Yes

Yes
-

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

Yes

Yes

-P.108April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00(Hex)

Operation
Code

7D

RDAx

7E

RDAy

A1

A8

AA

AF

Read_DDB_start

Read_DDB_contin
ue

RDFCS

D/CX RDX WRX D7

D6

D5

D4

D3

D2

D1

D0

0
1
1
0
1
1

1
↑
↑
1
↑
↑

↑
1
1
↑
1
1

0
1
x
x
Ax9 Ax80
1xx
Ay9 Ay8

1
x
Ax7
1
x
Ay7

1
x
Ax6
1
x
Ay6

1
1
0
x
x
x
Ax5 Ax4 Ax3
1
1
1
x
x
x
Ay5 Ay4 Ay3

0

1

↑

1

0

1

0

0

0

0

1
1
1
1
1
1

↑
↑
↑
↑
↑
↑

1
1
1
1
1
1

x
x
x
x
x
1

x
x
x
x
x
1

x
x
x
x
x
1

x
x
x
x
x
1

x
x
x
x
x
1

x
x
x
x
x
1

x
x
x
x
x
1

0

1

↑

1

0

1

0

1

0

0

1
1
1
1

↑
↑
↑
↑

1
1
1
1

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

x
x
x
x

0

1

↑

1

0

1

0

1

1

0

1
1

↑
↑

1
1

x

x

x

x
x
FCS[7:0]xx

1 Read Axx
Dummy read
Ax2
0 Read Ayx Dummy read
Ay2
Read the DDB
from the1
providedlocation.
x Dummy read
x
x
x
x
1
0xFF
Continue
reading0
the DDB
from the lastread location.
x Dummy readxxx
Read First
0
Checksumx Dummy read

0

1

↑

1

0

1

0

1

0

0

1
1
0
1
1
0
1
1
0
1
1

↑
↑
↑
1
1
↑
1
1
↑
1
1

1
1
1
↑
↑
1
↑
↑
1
↑
↑

x

x

x

x
x
x
x
CCS[7:0]
1
0
1
1
0
1
x
x
x
x
x
x
module’s manufacturer[7:0]
1
0
1
1
0
1
x
x
x
x
x
x
LCD module/driver version [7:0]
1
0
1
1
1
0
x
x
x
x
x
x
LCD module/driver ID[7:0]

x

1

RDCCS

DA

RDID1

DB

RDID2

DC

RDID3

Function

1
x
1
x
1
x

0
x
1
x
0
x

Read
Continue
Checksum
Dummy read
Read ID1
Dummy read
Read ID2
Dummy read
Read ID3
Dummy read-

Default MESSI_ENB
(Hex)
‘0’
‘1’
-

Yes

Yes

00h
00h
00h
00h
FFh

Yes

Yes
00h
00h
00h
00h

00h
00h

Yes

Yes
00h
00h
00h
80h
00h

Yes

Yes

Yes

Note: (1) Undefined commands are treated as NOP (00h) command.

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.109April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.1.2 User define command list table
(Hex)
B0

B1

Operation
Code
SETOSCSETPOWER

B2

SETDISPLAY

B3

SETRGB

B4

SETCYCB5SETBGP

B6

SETVCOM

B7

B9SETOTPSETEXTCDNC NWR NRD D15-8 D7
0
1

↑
↑

1
1

-

1

D6

D5

D4

D3

0
1
I_UADJ[3:0]

1

0

D2

D1

D0

0
0
N_UADJ[3:0]

0

1

↑

1

-

-

-

-

-

-

-

-

0

↑

1

-

1

0

1

1

0

0

0

1

↑

1

-

-

-

-

-

-

-

-

1
1
1

↑
↑
↑

1
1
1

-

-

TRI

XDK

1

↑

1

-

GAS
EN

-

-

-

1

↑

1

-

1

↑

1

-

0
1
1
1
1
1
0

↑
↑
↑
↑
↑
↑
↑

1
1
1
1
1
1
1

-

1

↑

1

-

1
1
1
0
1
1

↑
↑
↑
↑
↑
↑

1
1
1
1
1
1

-

1

↑

1

-

1
1
1
1
0
1
1
1
0
1

↑
↑
↑
↑
↑
↑
↑
↑
↑
↑

1
1
1
1
1
1
1
1
1
1

-

1

1

↑

-

0
1
1
1

↑
↑
↑
↑

1
1
1
1

-

1

↑

1

-

1
0
1
1
1

1
↑
↑
↑
↑

↑
1
1
1
1

-

Set Internal
OSC_ Oscillator
EN
1
DP_S
TB

BT[2:0]
VRH[5:0]
NVRH[5:0]-

FunctionSet power control

AP[2:0]FS1[3:0]FS0[3:0]
VCO
1
PON DK
0
0
STB
MG
1
0
1
1
0
0
1
0
ISC[3:0]
PT[1:0]PTG REF Set Display
NL[5:0]control
SCN[6:0]
GON DTE
D[1:0]
1
0
1
1
0
0
1
1
SDO BYPA
EPF[1:0]
RM DM_ENB SSSet RGB I/F
DPL HSPL VSPL EPL
RCM
HBP[5:0]
VBP[5:0]
1
0
1
1
0
1
0
0
ZINV
I_NW[1:0]
N_NW[1:0]
RTN[6:0]
OSC_
DIV[1:0]
DIV2
Set Display cycle
N_DUM[7:0]
I_DUM[7:0]
GDON[7:0]
GDOF[7:0]
1
0
1
1
0
1
0
1
VREF[3:0]
Set BGP Voltage
NVREF[3:0]
VPP[2:0]
VVDH[2:0]
1
0
1
1
0
1
1
0
Set VCOM
VCOM[6:0]
VCOM_OTP_TIME voltage
S[2:0]
1
0
1
1
0
1
1
1
OTP_KEY[7:0]
OTP_MASK[7:0]
OTP_INDEX[7:0]
Set OTPLOAOTP_VPP_ OTP_ OTP_ OTP_PTM[1: VPP_
D_DI
PRO
0]
SEL
EN POR PWESGOTP_DOUT[7:0](8’hFF)
1
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1 Enter extention
1
0
0
0
0
0
1
1 command
0
1
0
1
0
1
1
1

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.110April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
(Hex)

C1

C0

C3

Operation
Code

SETDGCSETSTBASETID

C4SET DDBC9SETCABCCCSETPANELDNC NWR NRD D15-8 D7

D6

D5

D4

D3

D2

D1

D0
1
DGC
_EN

0

↑

1

-

1

1

0

0

0

0

0

1

↑

1

-

-

-

-

-

-

-

-

1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1

↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

-

1

1

↑

-

-

0
1
1
1
1
0

↑
↑
↑
↑
↑
↑

1
1
1
1
1
1

-

1

1

↑

1

-

1
0

↑
↑

1
1

-

1

1

↑

1

-

-

1

1

1
BC_C
TL

Function

DGC_LUT_R00[7:0]:
Set Digital
DGC_LUT_R32[7:0]Gamma
DGC_LUT_G00[7:0]
Correction:
DGC_LUT_G32[7:0]
DGC_LUT_B00[7:0]:
DGC_LUT_B32[7:0]
1
0
0
0
0
0
0
N/P_OPON[7:0]
I/PI_OPON[7:0]
Set Source option
STBA[15:8]
STBA[7:0]
GENON[7:0]
1
0
0
0
0
1
1
ID1[7:0]ID2[7:0]
Set ID
ID3[7:0]
ID_OTP_TIMES[2:
0]
1
0
0
0
1
0
0
DDB1[7:0]
DDB2[7:0]
SET DDB
DDB3[7:0]
DDB4[7:0]
1
0
0
1
0
0
1
INVP
PWMDIV[2:0]
1
1
1 SET CABCLUS
PWM_PERIOD[7:0]
1
0
0
1
1
0
0
REV_ BGR_ Set Panel
SM_P SS_P GS_P
PANE PANE characteristics
ANEL ANEL ANEL
L
L

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.111April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
(Hex)

E0

E9

EA

EB

Operation
Code

SETGAMMASETIMAGEISETMESSISETCOLORDNC NWR NRD D15-8

D7

D6

D5

D4

D2

D1

D0

1
1
CGN1[1:0]

1

0

0
0
VRP0[6:0]
VRP1[6:0]
VRP2[6:0]
VRP3[6:0]
VRP4[6:0]
VRP5[6:0]
VRP6[6:0]
VRP7[6:0]
VRP8[6:0]
VRP9[6:0]
VRP10[6:0]
VRP11[6:0]
VRP12[6:0]
VRP13[6:0]
VRP14[6:0]
VRP15[6:0]
VRN0[6:0]
VRN1[6:0]
VRN2[6:0]
VRN3[6:0]
VRN4[6:0]
VRN5[6:0]
VRN6[6:0]
VRN7[6:0]
VRN8[6:0]
VRN9[6:0]
VRN10[6:0]
VRN11[6:0]
VRN12[6:0]
VRN13[6:0]
VRN14[6:0]
VRN15[6:0]
CGN0[1:0] CGP1[1:0]

0

0

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

-

1

↑

1

-

0

1

↑

1

1

1

↑

-

-

0

1

↑

PWM2_
EN
-

1

1

1

1

↑

-

-

-

-

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑

-

1
Bkx1
Bkx9
Bky9
Wx9
Wy9
Rx1
Rx9
Ry9
Gx9
Gy9
Bx1
Bx9
By9
Ax9
Ay9

1
Bkx0
Bkx8
Bky8
Wx8
Wy8
Rx0
Rx8
Ry8
Gx8
Gy8
Bx0
Bx8
By8
Ax8
Ay8

1
Bky1
Bkx7
Bky7
Wx7
Wy7
Ry1
Rx7
Ry7
Gx7
Gy7
By1
Bx7
By7
Ax7
Ay7

1

1
0
DITH_ YUV_
EN
EN
1
0

D3

1

0

-

-

1

0

-

-

-

0
Bky0
Bkx6
Bky6
Wx6
Wy6
Ry0
Rx6
Ry6
Gx6
Gy6
By0
Bx6
By6
Ax6
Ay6

1
Wx1
Bkx5
Bky5
Wx5
Wy5
Gx1
Rx5
Ry5
Gx5
Gy5
Ax1
Bx5
By5
Ax5
Ay5

0
Wx0
Bkx4
Bky4
Wx4
Wy4
Gx0
Rx4
Ry4
Gx4
Gy4
Ax0
Bx4
By4
Ax4
Ay4

Function
Set Gamma

Set Gamma

CGP0[1:0]
GMA
_REL
OAD
0
-

1
DB_E Set Image type
N
0

1
SPI_D
MESSI Set command type
CX_S
_ENB
EL
1
1
Wy1 Wy0
Bkx3 Bkx2
Bky3 Bky2
Wx3 Wx2
Wy3 Wy2
Gy1
Gy0
Rx3
Rx2
Set Color
Ry3
Ry2
Gx3
Gx2
Gy3
Gy2
Ay1
Ay0
Bx3
Bx2
By3
By2
Ax3
Ax2
Ay3
Ay2

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.112April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00(Hex)

Operation
Code

FE

SETREADINDEXFF

GETSPIREAD

DNC NWR NRD D15-8
0
1
0
1
1
1

1
1
1
↑
↑
↑

↑
↑
↑
1
1
1

-

D7

D6

D5

1

1

1

1

1

D4

D3

D2

D1

D0

1
1
1
CMD_ADD[7:0]1111
CMD_DATA1[7:0]:
CMD_DATAn[7:0]

1

0

1

1

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

Function
SET SPI READ
Command Address
Read SPI Command
Data-P.113April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2Command description
6.2.1 NOP
00 H
CommandParameter
Description
Restriction

NOP (No Operation)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
0
0
0
0
0
0
00
NO PARAMETER
This command is an empty command; it does not have any effect on the display module.
However it can be used to terminate Frame Memory Write as described in RAMWR (Memory
Write) or RAMRD (Memory Read) command.
-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

StatusPower On Sequence
S/W Reset
H/W Reset

Default Value
N/A
N/A
N/A

Default

Flow Chart-

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.114April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.2 Software reset (01h)
01 H
CommandParameter

Description

Restriction

Register
Availability

SWRESET (Software Reset)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
0
0
0
0
0
1
01
NO PARAMETER
When the Software Reset command is written, it causes a software reset. It resets thecommands and parameters to their S/W Reset default values. (See default tables in eachcommand description.)
The display is blank immediately.
Note: The GRAM contents are unaffected by this command.
It will be necessary to wait 5msec before sending new command following software reset.
The display module loads all display supplier’s factory default values to the registers during
this 5m sec.
If SW Reset is applied during Sleep Out mode, it will be necessary to wait 120m sec before
sending Sleep Out command.
SW Reset command cannot be sent during Sleep Out sequence.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

StatusPower On Sequence
S/W Reset
H/W Reset

Default Value
N/A
N/A
N/A

Default

LegendRed and Blue

Parameter

Flow Chart

Display

ActionMode

Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.115April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.3 Read display identification information (04h)
04 H

RDDIDIF (Read Display Identification Information)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0
Command
0
↑
1
0
0
0
0
0
1
0
0
1st parameter 1
1↑nd
2 parameter
1
1↑
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10rd
3 parameter
1
1↑
ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20th
4 parameter
1
1↑
ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30
This read byte returns 24-bit display identification information.
st
The 1 parameter is dummy data.
nd
The 2 parameter: LCD module’s manufacturer ID.
rd
Description
The 3 parameter: LCD module/driver version ID.
th
The 4 parameter: LCD module/driver ID.

HEX
04
-

Note: Commands RDID1/2/3(DAh, DBh and DCh) read data correspond to the parameters 2, 3, 4 ofthe command 04h, respectively.

Restriction

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

StatusPower On Sequence
S/W Reset
H/W Reset

Default Value
00h
00h
00h

Default

Flow Chart

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.116April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.4 RDNUMPE: Read Number of the Errors on DSI (05h)05hCommandst

1 parameter
Description

Restriction

Register
Availability

Default

D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

RDNUMPE (Read Number of the Errors on DSI)
D7
D6
D5
D4
D3
D2
D1
D15-D8
0
0
0
0
0
1
0
x
x
x
x
x
x
x
P7
P6
P5
P4
P3
P2
P1
-

D0
HEX
1
05
x
Dummy read
P0xx
The first parameter is telling a number of the errors on DSI. The more detailed description of the bits is below.
P[6..0] bits are telling a number of the errors.
P[7] is set to ‘1’ if there is overflow with P[6..0] bits.
P[7..0] bits are set to ‘0’s (as well as RDDSM(0Eh)’s D0 is set ‘0’ at the same time) after there is sent the second
parameter information (= The read function is completed).

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default value
00h
00h
00h
LegendDSI I/F Mode

Command

RDNUMPE(R05h)

Host

Parameter

DriverSend 1st parameter
Display

Flow Chart

ActionRDDSM (R0Eh) 's D0 = '0'
P[7:0] = "00"h
ModeSequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.117April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.5 Read red color (06h)
06 H
Commandst
1 parameter
Description
Restriction

Register
Availability

RDRED (Read Red Color)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
↑
1
0
0
0
0
0
1
1
0
06
1
1
↑
R5
R4
R3
R2
R1
R0
The first parameter is telling red color value of the first pixel of the frame when there is used in
RGB I/F.
16 bit format: R5 is MSB and R1 is LSB. R0 is set to ‘0’.
18 bit format: R5 is MSB and R0 is LSB.
When BYPASS=’0’, this command is working as a NOP (00h) command.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h
LegendParameter

DisplayFlow Chart
ActionMode

Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.118April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.6 Read green color (07h)
07 H

RDGREEN (Read Green Color)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
Command
0
↑
1
0
0
0
0
0
1
1
1
07
st
1 parameter
1
1
↑
G5
G4
G3
G2
G1
G0
The first parameter is telling red color value of the first pixel of the frame when there is
Description used in RGB I/F.
16, 18 bit formats: G5 is MSB and G0 is LSB.
Restriction When BYPASS=’0’ is disabled, this command is working as a NOP (00h) command.

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h

Flow Chart

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.119April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.7 Read blue color (08h)
08 H

RDBLUE (Read Blue Color)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
↑
1
0
0
0
0
1
0
0
0
08
st
1 parameter
1
1
↑
B5
B4
B3
B2
B1
B0
The first parameter is telling red color value of the first pixel of the frame when there isused in RGB I/F.
Description
16 bit format: B5 is MSB and B1 is LSB. B0 is set to ‘0’.
18 bit format: B5 is MSB and B0 is LSB.
Restriction When BYPASS=’0’ is disabled, this command is working as a NOP (00h) command.

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h

Flow Chart

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.120April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.8 Read display power mode (0Ah)
0A H
Commandst
1 parameternd
2 parameter

Description

Restrictions

Register
Availability

RDDPM (Read Display Power Mode)DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
0
0
1
0
1
0
0A
1
1
↑
1
1
↑
D7
D6
D5
D4
D3
D2
0
0
xx
This command indicates the current status of the display as described in the table below:
Bit
Description
Comment
D7
Booster Voltage Status
D6
Idle Mode On/Off
D5
Partial Mode On/Off
D4
Sleep In/Out
D3
Display Normal Mode On/Off
D2
Display On/Off
D1
Not Defined
Set to ‘0’
D0
Not Defined
Set to ‘0’Bit D7 – Booster Voltage Status‘0’ = Booster Off or has a fault.
‘1’ = Booster On and working OK (Meets display supplier’s optical requirements).
Bit D6 – Idle Mode On/Off‘0’ = Idle Mode Off.
‘1’ = Idle Mode On.
Bit D5 – Partial Display Mode On/Off‘0’ = Partial Mode Off.
‘1’ = Partial Mode On.
Bit D4 – Sleep In/Out‘0’ = Sleep In Mode.
‘1’ = Sleep Out Mode.
Bit D3 – Normal Display Mode On/Off‘0’ = Display Normal Mode Off.
‘1’ = Display Normal Mode On.
Bit D2 – Display On/Off‘0’ = Display is Off.
‘1’ = Display is On.
Bit D1 – Not DefinedThis bit is not applicable for this project, so it is set to ‘0’.
Bit D0 – Not DefinedThis bit is not applicable for this project, so it is set to ‘0’.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes
Default Value
08h
08h
08h

Himax Confidential
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in whole or in part without prior written permission of Himax.

-P.121April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Flow Chart

Himax Confidential
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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.9 Read display MADCTL (0Bh)
0B H
Commandst
1 parameternd
2 parameter

RDDMADCTL (Read Display MADCTL)DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0
0
↑
1
0
0
0
0
1
0
1
1
1
1
↑
1
1
↑
D7
D6
D5
D4
D3
D2
0
0
This command indicates the current status of the display as described in the table below:
Bit
D7
D6
D5
D4
D3
D2
D1
D0

Description

Description
Page Address Order
Column Address Order
Page/Column OrderLine Address Order
RGB/BGR Order
Display Data Latch Order
Switching between Segment outputs and RAM
Switching between Common outputs and RAM

HEX
0B
xx

Comment
Set to ‘0’
Set to ‘0’

Bit D7 – Page Address Order‘0’ = Top to Bottom (When MADCTL B7(MY) = ’0’).
‘1’ = Bottom to Top (When MADCTL B7(MY) =’1’).
Bit D6 – Column Address Order‘0’ = Left to Right (When MADCTL B6(MX) = ’0’).
‘1’ = Right to Left (When MADCTL B6(MX) = ’1’).
Bit D5 –Page / Column Order‘0’ = Normal Mode (When MADCTL B5(MV) = ’0’).
‘1’ = Reverse Mode (When MADCTL B5(MV) = ’1’).
Bit D4 – Line Address Order‘0’ = LCD Refresh Top to Bottom (When MADCTL B4(ML) = ’0’).
‘1’ = LCD Refresh Bottom to Top (When MADCTL B4(ML) = ’1’).
Bit D3 – RGB/BGR Order‘0’ = RGB (When MADCTL B3 = ’0’).
‘1’ = BGR (When MADCTL B3 = ’1’).
Note: For bits D4, D3 and D2 also refer to 6.2.32 Memory Access Control (R36h)

Restrictions

Register
Availability

Bit D2 – Display Data Latch Order‘0’ = LCD Refresh Left to Right (When MADCTL B2 = ’0’).
‘1’ = LCD Refresh Right to Left (When MADCTL B2 = ’1’).
Bit D1 – Switching Between Segment Outputs and RAM
This bit is not applicable for this project, so it is set to ‘0’.
Bit D0 – Switching Between Common Outputs and RAM
This bit is not applicable for this project, so it is set to ‘0’.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes
Default Value00h
No Change
00h

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.123April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Flow Chart

Himax Confidential
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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.10 Read display pixel format (0Ch)
0C H
Commandst
1 parameternd
2 parameter

DNC
0
1
1

NWR
↑
1
1

RDDCOLMOD (Read Display COLMOD)
NRD D15-8 D7
D6
D5
D4
D3
D2
1
0
0
0
0
1
1
↑
↑
0
D6
D5
D4
0
D2

D1
0
D1

D0
0
D0

HEX
0C
xx

This command indicates the current status of the display as described in the table below:
Bit
Description
Comment
D7
Reserved
Set to ‘0’
D6
DPI Interface Pixel format
D5
D4
D3
Reserved
Set to ‘0’
D2
DBI Interface Pixel format
D1
D0-

Description

Bits D6, D5, D4 – DPI Interface Colour Pixel Format Definition
Bits D2, D1, D0 – DSI, DBI Interface Colour Pixel Format Definition.
D6/D2
D5/D1
D4/D0
Interface Colour Format
Not Defined000
Not Defined00
1
Not Defined0
1
0
12 bit/pixel
0
1
1
Not Defined
10
0
16 bit/pixel
10
1
18 bit/pixel
1
1
0
24 bit/pixel
1
1
1
If a particular interface, either DSI, DBI or DPI, is not used then the corresponding bits in the

Restrictions

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes
Default Value
18-bit/pixel
18-bit/pixel
18-bit/pixel

Himax Confidential
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-P.125April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Flow Chart

Himax Confidential
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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.11 Read display image mode (0Dh)
0D H
Commandst
1 parameternd
2 parameter

DNC
0
1
1

NWR
↑
1
1

RDDIM (Read Display Image Mode)
NRD D15-8 D7
D6
D5
D4
D3
1
0
0
0
0
1
↑
↑
D7
0
D5
0
0

D2
1
D2

D1
0
D1

D0
1
D0

HEX
0D
xx

Description

This command indicates the current status of the display as described in the table below:
Bit D7 – Vertical Scrolling On/Off‘0’ = Vertical Scrolling is Off.
‘1’ = Vertical Scrolling is On.
Bit D6 – Horizontal Scrolling Status
This bit is not applicable for this project, so it is set to ‘0’
Bit D5 – Inversion On/Off‘0’ = Inversion is Off.
‘1’ = Inversion is On.
This bit is not applicable for this project, so it is set to ‘0’
Bit D4 – All Pixels On
This bit is not applicable for this project, so it is set to ‘0’
Bit D3 – All Pixels Off
This bit is not applicable for this project, so it is set to ‘0’
Bits D2, D1, D0 – Gamma Curve Selection
Gamma Curve Selected
D2 D1 D0 Gamma Set (R26h) Parameter
Gamma Curve 1
0
0
0
GC0
Gamma Curve 2
0
0
1
GC1
Gamma Curve 3
0
1
0
GC2
Gamma Curve 4
0
1
1
GC3
Not Defined
10
0
Not DefinedNot Defined
1
0
1
Not DefinedNot Defined1
1
0
Not DefinedNot Defined
1
1
1
Not Defined

Restrictions-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes
Default Value00h
No change
00h

Himax Confidential
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-P.127April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Flow Chart

Himax Confidential
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-P.128April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.12 Read display signal mode (0Eh)
0E H
Commandst
1 parameternd
2 parameter

Description

Restrictions

Register
Availability

RDDSM (Read Display Signal Mode)DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
↑
1
0
0
0
0
1
1
1
0
0E
1
1
↑
1
1
↑
D7
D6
D5
D4
D3
D2
0
D0
xx
This command indicates the current status of the display as described in the table below:
Bit D7 – Tearing Effect Line On/Off‘0’ = Tearing Effect Line Off.
‘1’ = Tearing Effect On.
Bit D6 – Tearing Effect Line Output Mode, see section 5.2 for mode definitions.
‘0’ = Mode 1.
‘1’ = Mode 2.
Bit [D5:D1] – are for future use and are set to ‘0’.
Bit D0 – Error on DSI, see section “6.2.4RDNUMPE: Read Number of the Errors on DSI(05h)”‘0’ = No Error.
‘1’ = Error.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h

Flow Chart

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.13 Read display self-diagnostic result (0Fh)
0F H
Commandst
1 parameternd
2 parameter

Description

Restrictions

Register
Availability

RDDSDR (Read Display Self-Diagnostic Result)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
0
0
1
1
1
1
0F
1
1
↑
1
1
↑
D7
D6
0
0
0
0
0
D0
The display module returns the self-diagnostic results following a Sleep Out command.
Bit D7 – Register Loading Detection
Bit D6 – Functionality Detection
Bits D[5:1] – Reserved, Set to ‘0’.
Bit D0 – Checksums comparison‘0’ = Checksums are same
‘1’ = Checksums are not same-

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h

Flow Chart

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-P.130April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.14 Sleep in (10h)
10 HCommandParameter

SLPIN (Sleep In)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
↑
1
0
0
0
1
0
0
0
0
10
NO PARAMETER
This command causes the LCD module to enter the minimum power consumption mode.
In this mode the DC/DC converter is stopped, Internal oscillator is stopped, and panel
scanning is stopped.

Description

Restriction

Register
Availability

MCU interface and memory are still working and the memory keeps its contents.
This command has no effect when module is already in sleep in mode. Sleep In Mode canonly be left by the Sleep Out Command (11h).
It will be necessary to wait 5msec before sending next command, this is to allow time
for the supply voltages and clock circuits to stabilize.
It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep
In Mode) before Sleep In command can be sent.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
Sleep In Mode
Sleep In Mode
Sleep In Mode

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
It takes 120msec to get into Sleep In mode after SLPIN command issued.

Flow Chart

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.15 Sleep out (11h)
11 H
CommandParameter

SLPOUT (Sleep Out)
D6
D5
D4
D3
D2
D1
D0 HEX
0
0
1
0
0
0
1
11
NO PARAMETER
This command turns off sleep mode.
In this mode the DC/DC converter is enabled, Internal oscillator is started, and panel
scanning is started.

DNC NWR NRD D15-8
0
↑
1
-

D7
0

Description

Restriction

Register
Availability

This command has no effect when module is already in sleep out mode. Sleep Out
Mode can only be left by the Sleep In Command (10h).
It will be necessary to wait 5msec before sending next command, this is to allow time
for the supply voltages and clock circuits to stabilize.
The display module loads all display supplier’s factory default values to the registers
during this 5msec and there cannot be any abnormal visual effect on the display
image if factory default and register values are same when this load is done and when
the display module is already Sleep Out –mode.
The display module is doing self-diagnostic functions during this 5msec.
It will be necessary to wait 120msec after sending Sleep In command (when in Sleep
Out mode) before Sleep Out command can be sent.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
Sleep In Mode
Sleep In Mode
Sleep In Mode

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
It takes 120msec to become Sleep Out mode after SLPOUT command issued.
SLPOUT

LegendStart Internal
Oscillator

Flow Chart

Start
DC-DC
Converter

Command
Display whole blankscreen for 2 frames(Automatic No effect to
DISP ON/OFF
Commands)

Parameter
Display
ActionMode

Charge Offset
voltage for LCD
Panel

Display Memory
contents in accordancewith the current
command table settings

Sequential
transfer

Sleep Out Mode

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.16 Partial mode on (12h)
12 HCommandParameter
Description
Restrictions

Register
Availability

PTLON (Partial Mode On)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
↑
1
0
0
0
1
0
0
1
0
12
NO PARAMETER
This command turns on partial mode The partial mode window is described by the Partial
Area command (30H). To leave Partial mode, the Normal Display Mode On command(13H) should be written.
This command has no effect when Partial mode is active.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Default

Flow Chart

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
Normal Display Mode On
Normal Display Mode On
Normal Display Mode On

See Partial Area (30h)Himax Confidential
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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.17 Normal display mode on (13h)13 HCommandParameter
Description
Restriction

NORON (Normal Display Mode On)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
↑
1
0
0
0
1
0
0
1
1
13
NO PARAMETER
This command returns the display to normal mode. Normal display mode on means
Partial mode off, Scroll mode Off.
This command has no effect when Normal mode is active.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Register
Availability

StatusPower On Sequence
S/W Reset
H/W Reset

Default

Flow Chart

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
Normal Display Mode On
Normal Display Mode On
Normal Display Mode On

See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use thiscommand.

Himax Confidential
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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.18 Display inversion off (20h)
20 H
CommandParameter

INVOFF (Display Inversion Off)DNC NRD NWR D15-8 D7
D6
D5
D4
D3
D2
0
1
↑
0
0
1
0
0
0
NO PARAMETER
This command is used to recover from display inversion mode.
This command makes no change of contents of frame memory.
This command does not change any other status.

D1
0

D0
0

HEX
20

(Example)memoryDescription

Restriction

displayThis command has no effect when module is already in inversion off mode.

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
Display Inversion Off
Display Inversion Off
Display Inversion Off

Flow Chart

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.19 Display inversion on (21h)21 H
CommandParameter

INVON (Display Inversion On)
DNC NRD NWR D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
1
↑
0
0
1
0
0
0
0
1
21
NO PARAMETER
This command is used to enter into display inversion mode.
This command makes no change of contents of frame memory. Every bit is inverted
from the frame memory to the display.
This command does not change any other status.

(Example)memoryDescription

Restriction

displayThis command has no effect when module is already in inversion on mode.

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
Display Inversion Off
Display Inversion Off
Display Inversion Off

Flow Chart

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-P.138April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.20 All pixel off (22h)22hCommandParameter

ALLPOFF (All Pixel Off)D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
0
1
↑
0
0
1
0
0
0
1
0
22
NO PARAMETER
This command turns the display panel black in ‘Sleep Out’ –mode and a status of the‘Display On/Off’ –register can be ‘on’ or ‘off’.
This command makes no change of contents of frame memory.
This command does not change any other status

Description

Restriction

Register
Availability

Default‘All Pixels On’, ’Normal Display Mode On’ or ’Partial Mode On’ – commands are used toleave this mode. The display panel is showing the content of the frame memory after‘Normal Display Mode On’ and ‘Partial Mode On’ -commands.
This command has no effect when module is already in all pixels off mode.
StatusAvailability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
YesPartial Mode On, Idle Mode Off, Sleep Out
YesPartial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
StatusPower On Sequence
S/W Reset
H/W Reset

Default value
off
off
off

Flow Chart

Himax Confidential
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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.21 All pixel on (23h)23hCommandParameter

ALLPON(All Pixel On)
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
0
1
↑
0
0
1
0
0
0
1
1
23
NO PARAMETER
This command turns the display panel white in ‘Sleep out ‘ –mode and a status of the‘Display On/Off’ –register can be ‘on’ or ‘off’.
This command makes no change of contents of frame memory.
This command does not change any other status.

Description

Restriction

Register
Availability

Default‘All Pixels Off’, ’Normal Display Mode On’ or ’Partial Mode On’ – commands are used toleave this mode. The display is showing the content of the frame memory after ‘Normal
Display Mode On’ and ‘Partial Mode On’ –commands.
This command has no effect when module is already in all pixels on mode.
StatusAvailability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
YesPartial Mode On, Idle Mode Off, Sleep Out
YesPartial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
StatusPower On Sequence
S/W Reset
H/W Reset

Default value
off
off
off

Flow Chart

Himax Confidential
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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.22 Gamma set (26h)
26 HCommandParameter

GAMSET (Gamma Set)
D6
D5
D4
D3
D2
D1
D0 HEXDNC NWR NRD D15-8 D7
0
↑
1
0
0
1
0
0
1
1
0
26
1
↑
1
GC7 GC6 GC5 GC4 GC3 GC2 GC1 GC0This command is used to select the desired Gamma curve for the current display. A
maximum of 4 fixed gamma curves can be selected. The curve is selected by setting theappropriate bit in the parameter as described in the table:
GC[7..0]
01h
02h
04h
08h

Description

Parameter
GC0
GC1
GC2
GC3

Curve Selected
Gamma Curve 1
Gamma Curve 2
Gamma Curve 3
Gamma Curve 4

Note: All other values are undefined.

Restriction

Register
Availability

Values of GC[7..0] not shown in table above are invalid and will not change thecurrent selected Gamma curve until valid value is received.
StatusAvailability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
YesPartial Mode On, Idle Mode Off, Sleep Out
YesPartial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Default Value
01h
01h
01h

Flow Chart

Himax Confidential
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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.23 Display off (28h)28 HCommandParameter

DISPOFF (Display Off)DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
↑
1
0
0
1
0
1
0
0
0
28
NO PARAMETER
This command is used to enter into DISPLAY OFF mode. In this mode, the output fromFrame Memory is disabled and blank page inserted.
This command makes no change of contents of frame memory.
This command does not change any other status.
There will be no abnormal visible effect on the display.

(Example)
Description

memoryRestriction

This command has no effect when module is already in display off mode.

Register
Availability

display

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
Display Off
Display Off
Display Off

LegendDisplay On
ModeCommandParameter
Display

Flow ChartDISPOFF

ActionMode

Display Off
ModeSequential
transfer

Himax Confidential
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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.24 Display on (29h)29 H

DISPON (Display On)
D6
D5
D4
D3
D2
D1
D0 HEXDNC NWR NRD D15-8 D7Command
0
↑
1
0
0
1
0
1
0
0
1
29
Parameter NO PARAMETER
This command is used to recover from DISPLAY OFF mode. Output from the Frame
Memory is enabled.
This command makes no change of contents of frame memory.
This command does not change any other status.

(Example)memoryDescription

Restriction

Register
Availability

displayThis command has no effect when module is already in display on mode.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
Display Off
Display Off
Display Off

Flow Chart

Himax Confidential
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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.25 Column address set (2Ah)
2A H
Command
1st parameter2nd parameter3rd parameter4th parameter

DNC NWR NRD D15-8
0
↑
1
1

↑

1

-

1

↑

1

-

1

↑

1

-

1

↑

1

-

CASET (Column Address Set)
D7
D6
D5
D4
D3
D2
0
0
1
0
1
0
SC15 SC14 SC13 SC12 SC11 SC10SC7 SC6 SC5 SC4 SC3 SC2
EC15 EC14 EC13 EC12 EC11 EC10EC7 EC6 EC5 EC4 EC3 EC2

D1
1
SC9
SC1
EC9
EC1

D0
0
SC8
SC0
EC8
EC0

HEX
2A
Note 1
Note 1This command is used to define area of frame memory where MCU can access.
This command makes no change on the other driver status.
The values of SC[15:0] and EC[15:0] are referred when RAMWR command comes. Eachvalue represents one column line in the Frame Memory.

Description

SC[15:0] always must be equal to or less than EC[15:0]
Restriction

Note: When SC[15:0] or EC[15:0] is greater than maximum address like below, data out of range
will be ignored

0000h<=SC[15:0]<=EC[15:0] <=013Fh ,when MADCTL’s B5=00000h<=SC[15:0]<=EC[15:0] <=01DFh ,when MADCTL’s B5=1

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

StatusPower On Sequence
SW Reset
HW Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
SC[15:0]=0000h
EC[15:0]=013Fh
SC[15:0]=0000h
EC[15:0]=013Fh
SC[15:0]=0000h
EC[15:0]=013Fh

Himax Confidential
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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Flow Chart

Himax Confidential
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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.26 Page address set (2Bh)
2B H
Command
1st parameter2nd parameter3rd parameter4th parameter

PASET (Page Address Set)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
0
1
0
1
0
1
1
2B
1
↑
1
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8Note 1
1↑
1
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
1↑
1
EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8Note 11↑
1
EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0This command is used to define area of frame memory where MCU can access.
This command makes no change on the other driver status.
The values of SP[15:0] and EP[15:0] are referred when RAMWR command comes.
Each value represents one Page line in the Frame Memory.

Description

SP[15:0] always must be equal to or less than EP[15:0]
Restriction

Note: When SP[15:0] or EP[15:0] is greater than maximum row address like below, data of out ofrange will be ignored

0000h<=SP[15:0]<=EP[15:0]<=01DFh (When MADCTL’s B5=0)0000h<=SP[15:0]<=EP[15:0]<=013Fh (When MADCTL’s B5=1)

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

StatusPower On Sequence
SW Reset
HW Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
SP[15:0]=0000h
EP[15:0]=01DFh
SP[15:0]=0000h
EP[15:0]=01DFh
SP[15:0]=0000h
EP[15:0]=01DFh

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
CASET

st

nd

1 &2
parameter SC [15:0]
3 rd & 4th parameter EC [15:0]

LegendCommandParameter

RASET

Display
Action

1 st & 2 nd parameter SP [15:0]

Flow Chart

3 rd & 4th

parameter EP [15:0]

Mode
Sequential
transfer

RAMWR

Image Data
D1[17:0],D2[17:0],...,Dn[17:0]

Any Command

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.27 Memory write (2Ch)2C H
Command
1st parameter:nth parameter

DNC NWR NRD D15-8
0
↑
1
1

↑

1

1

↑

1

1

↑

1

D7
0

RAMWR (Memory Write)
D6
D5
D4
D3
0
1
0
1
D1[15:0]
Dx[15:0]
Dn[15:0]

D2
1

D1
0

D0
0

HEX
2C
00..FF
00..FF
00..FF

Description

This command is used to transfer data from MCU to frame memory.
This command makes no change to the other driver status.
When this command is accepted, the column register and the page register are reset to
the Start Column/Start Page positions.
The Start Column/Start Page positions are different in accordance with MADCTL setting.
Then D[7:0] is stored in frame memory and the column register and the page register
incremented.
Sending any other command can stop frame Write.

Restriction

In all color modes, there is no restriction on length of parameters.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Register
Availability

StatusPower On Sequence
S/W Reset
H/W Reset

Default

RAMWR

Availability
Yes
Yes
Yes
Yes
No

Default Value
Contents of memory is set randomly
Contents of memory is not cleared
Contents of memory is not cleared

LegendCommandParameter

Flow Chart

Image Data
DB1[15:0],DB2[15:0],...,DBn[15:0]

Display
ActionMode

Any Command

Sequential
transfer

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.28 Memory read (2Eh)
2E H
Command
1st parameter2nd parameter:(n+1)thparameter

Description

DNC NWR NRD D15-8
0
↑
1
1
↑
1
1

↑

1

1

↑

1

1

↑

1

D7
0
-

RAMRD (Memory Read)
D6
D5
D4
D3
0
1
0
1
D1[15:0]
Dx[15:0]

D2
1
-

D1
1
-

Dn[15:0]

D0
0
-

HEX
2E
00..FF
00..FF
00..FF

This command is used to transfer data from frame memory to MCU. This command makes
no change to the other driver status.
When this command is accepted, the column register and the page register are reset to theStart Column/Start Page positions.
The Start Column/Start Page positions are different in accordance with MADCTL setting.
Then D[7:0] is read back from the frame memory and the column register and the pageregister incremented
Frame Read can be stopped by sending any other command.

Restriction
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Register
Availability

StatusPower On Sequence
S/W Reset
H/W Reset

Default

Availability
Yes
Yes
Yes
Yes
No

Default Value
Contents of memory is set randomly
Contents of memory is not cleared
Contents of memory is not cleared

RAMRD
LegendCommand
Dummy
Parameter

Flow Chart

Display
Image Data
DB1[15:0],DB2[
15:0],DBn[15:0]

ActionMode
Sequential
transfer

Any Command

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.29 Partial area (30h)30 H

PLTAR (Partial Area)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Command
0
0
1
1
0
0
0
0
30
1st parameter 1↑
1
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 0000:↑
1
2nd parameter 1
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 01DF
3rd parameter 1↑
1
ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 0000:↑
1
4th parameter 1
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 01DF
This command defines the partial mode’s display area. There are 4 parameters associatedwith this command, the first defines the Start Row (SR) and the second the End Row (ER),as illustrated in the figures below. SR and ER refer to the Frame Memory Line Pointer.
DNC NWR NRD D15-8
0↑
1-

If End Row > Start Row when MADCTL B4(ML) = 0:Start Row
SR[15:0]
Partial Area
ER[15:0]
End Row
If End Row > Start Row when MADCTL B4(ML) = 1:
End RowER[15:0]

Description

Partial Area
SR[15:0]
Start Row

If End Row<Start Row when MADCTL’s B4(ML) = 0:
End RowER[15:0]
Partial Area
SR[15:0]
Start Row

If End Row = Start Row then the Partial Area will be one row deep.

Restriction

SR[15:0] and ER[15:0] cannot be exceeding than 01DFh.

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
StatusPower On Sequence
S/W Reset
H/W Reset

Default

Default Value
SR[15:0]=0000h
ER[15:0]=01DFh
SR[15:0]=0000h
ER[15:0]=01DFh
SR[15:0]=0000h
ER[15:0]=01DFh

1. To Enter Partial Display Mode:

PLTAR

LegendCommandSR[15:0]

Parameter
DisplayER[15:0]
ActionPTLONPartial Mode

Flow Chart

Mode
Sequential
transfer

2. To Leave Partial Display Mode
Partial ModeDISPOFF(Optional)
To prevent
Tearing Effect
Image displayed

NORON
Partial Mode OFF
RAMRW

Image DataDISPON

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.30 Vertical scrolling definition (33h)33 H

VSCRDEF (Vertical Scrolling Definition)
D6
D5
D4
D3
D2
D1
D0
HEX
DNC NWR NRD D15-8 D7Command
0
↑
1
0
0
1
1
0
0
1
1
33
1st parameter
TFA TFA TFA TFA TFA TFA TFA TFA
1
↑
1
0000:
15
14
13
12
11
10
9
8
TFA TFA TFA TFA TFA TFA TFA TFA 01E0↑
1
2nd parameter 1
7
6
5
4
3
2
1
0
3rd parameter
VSA VSA VSA VSA VSA VSA VSA VSA
1
↑
1
15
14
13
12
11
10
9
8
0000:
VSA VSA VSA VSA VSA VSA VSA VSA 01E0↑
1
4th parameter 1
7
6
5
4
3
2
1
0
BFA BFA BFA BFA BFA BFA BFA BFAth1↑
1
5 parameter
15
14
13
12
11
10
9
8
0000:
BFA BFA BFA BFA BFA BFA BFA BFA 01E0th1↑
1
6 parameter
7
6
5
4
3
2
1
0
This command defines the Vertical Scrolling Area of the display. When MADCTL B4=0, thestnd
1 & 2 parameter TFA[15:0] describes the Top Fixed Area (in No. of lines from top of therdthFrame Memory and Display). The 3 & 4 parameter VSA[15:0] describes the height of the
Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the
Vertical Scrolling Start Address). The first line read from Frame Memory appearsthth
immediately after the bottom most line of the Top Fixed Area. The 5 & 6 parameter
BFA[15:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame
Memory and Display). TFA, VSA and BFA refer to the Frame Memory Line Pointer.
Top Fixed Area

(0 ,0 )

TFA [ 15:0 ]First line read fromframe memory

Scroll Area

BFA [15:0]

Description

Bottom Fixed Area

When MADCTL B4=1
stnd
The 1 & 2 parameter TFA[15:0] describes the Top Fixed Area (in No. of lines fromrdthbottom of the Frame Memory and Display). The 3 & 4 parameter VSA[15:0] describes
the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not thedisplay] from the Vertical Scrolling Start Address). The first line read from Frame Memoryththappears immediately after the top most line of the Top Fixed Area. The 5 & 6 parameter
BFA[15:0] describes the Bottom Fixed Area (in No. of lines from Top of the Frame Memory
and Display).
Bottom Fixed Area

(0 ,0 )

BFA [15:0]

Scroll Area

TFA [ 15:0 ]Top Fixed Area

Restriction

First line read fromframe memory

The condition is (TFA+VSA+BFA)=480, otherwise Scrolling mode is undefined. In Vertical Scroll
Mode, MADCTL B5 should be set to ‘0’ – this only affects the Frame Memory Write.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

TFA[15:0]=0000
TFA[15:0]=0000
TFA[15:0]=0000

Availability
Yes
Yes
Yes
Yes
Yes

Default ValueVSA[15:0]=01E0h
VSA[15:0]=01E0h
VSA[15:0]=01E0h

BFA[15:0]=0000
BFA[15:0]=0000
BFA[15:0]=0000

1. To enter Vertical Scroll Mode:
Normal Mode

LegendCommand

VSCRDEF
Parameter
1st & 2nd Parameter TFA[15...0]

Display

3rd & 4th Parameter VSA[15...0]

Action5th & 6th Parameter BFA[15...0]

Mode

CASET

Sequential
transfer

1st & 2nd Parameter SC[15...0]
3rd & 4th Parameter EC[15...0]
PASET

Flow Charts

Onlyrequired
for nonrolling
scrolling

Redefines the Frame
Memory Window thatthe scroll data will be
written to.
See Note 1

1st & 2nd Parameter SP[15...0]
3rd & 4th Parameter EP[15..0]
MADCTL
Parameter

Optional – It may benecessary to redefine
the Frame Memory
Write Direction.

RAMRW
Scroll ImageData

VSCRSADD
1st & 2nd Parameter VSP[15...0]
Scroll Mode

Note: The Frame Memory Window size must be defined correctly otherwise undesirable image will be
displayed.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
2. Continuous Scroll:
LegendScroll Mode
CASET
1st & 2nd Parameter SC[15..0]

CommandParameter
Display
Action3rd & 4th Parameter EC[15..0]
Mode
PASET
1st & 2nd Parameter SP[15..0]

Sequential
transfer

3rd & 4th Parameter EP[15..0]
RAMRW
Scroll ImageData

VSCRSADD
1st & 2nd Parameter VSP[15..0]

3. To Leave Vertical Scroll Mode:
Scroll ModeDISPOFF(Optional)
To prevent
Tearing Effect
Image displayed

NORON/PTLON
Scroll Mode OFF
RAMRW
Image Data
D1[15:0], D2[15:0],…., Dn[15:0]

DISPON

Note: Scroll Mode can be left by both the Normal Display Mode On (13h) and Partial Mode On (12h)commands.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.31 Tearing effect line off (34h)
34 HCommandParameter
Description
Restriction

TEOFF (Tearing Effect Line OFF)
D6
D5
D4
D3
D2
D1
D0
HEX
DNC NWR NRD D15-8 D7
0
↑
1
0
0
1
1
0
1
0
0
34
No Parameter
This command is used to turn OFF the Tearing Effect output signal from the TE signal line.
This command has no effect when Tearing Effect output is already OFF.

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
Tearing Effect Off
Tearing Effect Off
Tearing Effect Off
LegendCommand

TE Line Output ON
Parameter
TEOFF

Flow Chart

Display
ActionTE Line Output OFF
Mode
Sequential
transfer

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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.32 Tearing effect line on (35h)
35 HCommand
1stparameter

DNC NWR NRD D15-8
0↑
1-

TEON (Tearing Effect Line ON)
D7
D6
D5
D4
D3
0
0
1
1
0

D2
1

D1
0

D0
HEX
1
35
TEMO
0
↑
1
DE
This command is used to turn ON the Tearing Effect output signal from the TE signal
line. This output is not affected by changing MADCTL bit B4.
The Tearing Effect Line On has one parameter which describes the mode of the
Tearing Effect Output Line. (X=Don’t Care).
When TEMODE=0:The Tearing Effect Output line consists of V-Blanking information only:
tvdl

tvdh

Vertical Time
Scale

Description
When TEMODE=1:
The Tearing Effect Output Line consists of both V-Blanking and H-Blanking
information:
tvdl

tvdh

Vertical Time
Scale

Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin
will be active Low.

Restriction

This command has no effect when Tearing Effect output is already ON.

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
Tearing Effect Off
Tearing Effect Off
Tearing Effect Off
LegendTE Line Output OFF

CommandParameter

TEON

Flow Chart

M

Display
ActionMode

TE Line Output ON
Sequential
transfer

Himax Confidential
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in whole or in part without prior written permission of Himax.

-P.156April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.33 Memory access control (36h)36 HCommand
1st parameter

MADCTL (Memory Access Control)
D6
D5
D4
D3
D2
DNC NWR NRD D15-8 D7
0
↑
1
0
0
1
1
0
1
1
↑
1
MY
MX
MV
ML BGR
SS
This command defines read/write scanning direction of frame memory.
This command makes no change on the other driver status.

D1
1
-

D0
0
-

HEX
36
-

Bit Assignment
BIT
B7
B6
B5
B4

NAME
PAGE ADDRESS ORDER (MY)COLUMN ADDRESS ORDER (MX)PAGE/COLUMN SELECTION (MV)
Vertical ORDER (ML)B3

RGB-BGR ORDER (BGR)

B2

Horizontal ORDER (SS)DESCRIPTION
These 3 bits controls MCU to memory write/readdirection.
LCD vertical refresh direction control
Colour selector switch control(0=RGB colour filter panel, 1=BGR colour filter
panel)LCD horizontal refresh direction control

RGB-BGR Order
B3= 0
SIG1

Driver IC
SIG2 …………

SIG1

SIG2 …………

RGB

Description

B3= 1
RGB

RG B

SIG320RG B RG B
RG B RG B

SIG1Driver IC
SIG2 …………

SIG320

SIG320

SIG1

SIG2 …………

SIG320RG B
RG B

B GR B GR
B GR B GR

LCD panel

RGB

B GR
B GR

LCD panel

Sent First (1)Sent 2nd
Sent 3rd

Sent last (320)Sent last (320)Sent 2nd

Sent 3rd

Sent First (1)Note: Top-Left (0,0) means a physical memory location.
Bit D1 – Switching Between Segment Output and RAM
This bit is not applicable for this project, so it is set to ‘0’
Bit D0 – Switching Between Common Output and RAM
This bit is not applicable for this project, so it is set to ‘0’

Restriction

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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes
Default Value00h
No change
00h

Flow Chart

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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.34 Vertical scrolling start address (37h)37 HCommandst

1 parameternd

2 parameter

VSCRSADD (Vertical Scrolling Start Address)
D15-8
D7
D6
D5
D4
D3
D2
D1 D0
HEX
0
0
1
1
0
1
1
1
37
VSP VSP VSP VSP VSP VSP VSP VSP
1
1
↑
01.
13
12
11
10
9
8
15
14
DF
VSP
VSP VSPVSP VSP VSP
VSP 2
1
1
↑
VSP 4
3
1
0
7
6
5
This command is used together with Vertical Scrolling Definition (33h). These twocommands describe the scrolling area and the scrolling mode. The Vertical Scrolling Start
Address command has one parameter which describes the address of the line in the
Frame Memory that will be written as the first line after the last line of the Top Fixed Area
on the display as illustrated below:

DNC
0

NRD NWR
1↑

When MADCTL B4=’0’
Example:When Top Fixed Area TFA = ‘00d’, Bottom Fixed Area BFA = ‘02’d, Vertical Scrolling Area
VSA = ‘318'd’ and VSP = ‘3d’

(Example)(0,0)

MemoryB4 = 0

Display

Pointer
0
1
2
3
:
:
:
:
318
319

Line PointerVSP[15:0](0,319)When MADCTL B4=’1’
Example:When Top Fixed Area TFA = ‘00d’, Bottom Fixed Area BFA = ‘02d, Vertical Scrolling Area
VSA = ‘318d’ and VSP = ‘3d’

(Example)(0,0)

Line PointerVSP[15:0]

MemoryB4 =1

Display

Pointer
319
318
:
:
:
:
3
2
1
0

(0,319)Restriction

When new Pointer position and Picture Data are sent, the result on the display will happen at
the next Panel Scan to avoid tearing effect. VSP refers to the Frame Memory line Pointer.
Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame
Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition (33h) –otherwise undesirable image will be displayed on the Panel.

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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Register
Availability

StatusPower On Sequence
S/W Reset
H/W Reset

Default

Flow Chart

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h

See Vertical Scrolling Definition (33h) description.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.35 Idle mode off (38h)38 H
CommandParameter

DNC
0

NWR
↑

NRD
1

D15-8
-

IDMOFF (Idle Mode Off)
D7
D6
D5
D4
0
0
1
1
NO PARAMETER

D3
1

D2
0

D1
0

D0
0

HEX
38

Description This command is used to recover from Idle mode on.
In the idle off mode, LCD can display maximum 262,144 colors.
Restriction

Register
Availability

This command has no effect when module is already in idle off mode.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
Idle Mode Off
Idle Mode Off
Idle Mode Off

Flow Chart

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.36 Idle mode on (39h)39 HCommandParameter

IDMON (Idle Mode On)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
0
1
1
1
0
0
1
39
NO PARAMETER
This command is used to enter into Idle mode on.
In the idle on mode, color expression is reduced. The primary and the secondary colors using
MSB of each R, G and B in the Frame Memory, 8 color depth data is displayed.
DNC
0

NWR
↑

NRD
1

D15-8
-

Description
Memory contents vs. Display ColorR5 R4 R3 R2 R1 R0
Black
0XXXXXBlue
0XXXXXRed
1XXXXX
Magenta
1XXXXXGreen
0XXXXXCyan
0XXXXX
Yellow
1XXXXXWhite
1XXXXX
Restriction

Register
Availability

G5 G4 G3 G2 G1 G0
0XXXXX
0XXXXX
0XXXXX
0XXXXX
1XXXXX
1XXXXX
1XXXXX
1XXXXXB5 B4 B3 B2 B1 B0
0XXXXX
1XXXXX
0XXXXX
1XXXXX
0XXXXX
1XXXXX
0XXXXX
1XXXXX

This command has no effect when module is already in idle off mode.

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Idle Mode Off
Idle Mode Off
Idle Mode Off

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Flow Chart

Himax Confidential
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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.37 Interface pixel format (3Ah)
3A H
Commandst

1 parameter

Description

DNC NWR NRD D15-8
0
↑
1
1

↑

1

Register
Availability

D2
0

D1
1

D0
0

HEX
3A

D2

D1

D0

-

This command is used to define the format of RGB picture data, which is to be transfer via thesystem and RGB interface. The formats are shown in the table:
DBI interface (RM=’0’)Interface Format
D2
D1
D0
Not Defined000
Not Defined00
1
Not Defined01
0
12 Bit/Pixel
0
1
1
Not Defined
100
16 Bit/Pixel
10
1
18 Bit/Pixel
11
024 Bit/Pixel
1
1
1
DPI interface (RM=’1’)
Interface Format
Not DefinedNot DefinedNot DefinedNot DefinedNot Defined
16 Bit/Pixel
18 Bit/Pixel
24 Bit/Pixel

Restriction-

COLMOD (Interface Pixel Format)
D7
D6
D5
D4
D3
0
0
1
1
1
CS
CS
CS
EL2 EL1 EL0

CSEL2
0
0
0
0
1
1
1
1

CSEL1
0
0
1
1
0
0
1
1

CSEL0
0
1
0
1
0
1
0
1

There is no visible effect until the Frame Memory is written to.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
18-bit/pixel
No Change
18-bit/pixel

Flow Chart

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-P.164April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.38 Write_memory_contiune (3Ch)
3Ch
Commandst
1 parameter:th
N parameter

Description

Restriction
Register
Availability

Default

Write_memory_contiune
D/CX RDX WRX D15-D8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
1
↑
0
0
1
1
1
1
0
0
3C
1
1
↑
D17 D16 D15 D14 D13 D12 D11 D10 00..FF
1
1↑
Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 00..FF
1
1↑
Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 00..FF
This command transfers image data from the host processor to the display module’s frame
memory continuing from the pixel location following the previous write_memory_continue or
write_memory_start command. Sending any other command can stop frame Write.
If set_address_mode B5 = 0:
Data is written continuing from the pixel location after the write range of the previous
write_memory_start or write_memory_continue. The column register is then incremented
and pixels are written to the frame memory until the column register equals the End Column(EC) value. The column register is then reset to SC and the page register is incremented.
Pixels are written to the frame memory until the page register equals the End Page (EP)value or the host processor sends another command. If the number of pixels exceeds (EC –SC + 1) * (EP – SP + 1) the extra pixels are ignored.
If set_address_mode B5 = 1:
Data is written continuing from the pixel location after the write range of the previous
write_memory_start or write_memory_continue. The page register is then incremented andpixels are written to the frame memory until the page register equals the End Page (EP)value. The page register is then reset to SP and the column register is incremented. Pixels
are written to the frame memory until the column register equals the End column (EC) valueor the host processor sends another command. If the number of pixels exceeds (EC – SC +1) * (EP – SP + 1) the extra pixels are ignored.
In all colour modes, there is no restriction on length of parameters.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default value
Contents of memory is set randomly
Contents of memory is set randomly
Contents of memory is set randomly
LegendRAMWR

CommandParameter

Flow Chart

Image Data
D1[7:0],D2[7:0],...,Dn[7:0]Display
ActionAny Command

Mode
Sequential
transfer

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.39 Raed_memory_continue (3Eh)
3Eh

Raed_memory_continue
D/CX

RDX

WRX

D15-D8

D7

D6

D5

D4

D3

D2

D1

D0

0

1

↑

-

0

0

1

1

1

1

1

0

Command

HEX

3E

st

1 parameter

1

↑

1

-

x

x

x

x

x

x

x

x

nd

1
1

↑
↑

1
1

-

D17

D16

D15

D14

D13

D12

D11

D10

Dummy
read
00..FF

Dx7

Dx6

Dx5

Dx4

Dx3

Dx2

Dx1

Dx0

00..FF

1

↑

1

-

Dn7

Dn6

Dn5

Dn4

Dn3

Dn2

Dn1

Dn0

00..FF2 parameter
:
th
(n+1)
parameter

Description

Restriction

Register
Availability

Default

This command transfers image data from the display module’s frame memory to the hostprocessor continuing from the location following the previous read_memory_continue or
read_memory_start command.
If set_address_mode B5=0:
Pixels are read continuing from the pixel location after the read range of the previous
read_memory_start or read_memory_continue. The column register is then incremented
and pixels are read from the frame memory until the column register equals the End
Column (EC) value. The column register is then reset to SC and the page register isincremented. Pixels are read from the frame memory until the page register equals the End
Page (EP) value or the host processor sends another command.
If set_address_mode B5=1:
Pixels are read continuing from the pixel location after the read range of the previous
read_memory_start or read_memory_continue. The page register is then incremented andpixels are read from the frame memory until the page register equals the End Page (EP)value. The page register is then reset to SP and the column register is incremented. Pixels
are read from the frame memory until the column register equals the End Column (EC)value or the host processor sends another command.
Regardless of the color mode set in set_pixel_format, the pixel format returned byread_memory_continue is always 24-bit so there is no restriction on the length of data.
A read_memory_start should follow a set_column_address, set_page_address or
set_address_mode to define the read location. Otherwise, data read with
read_memory_continue is undefined.
StatusAvailability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
YesPartial Mode On, Idle Mode Off, Sleep Out
YesPartial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
StatusPower On Sequence
S/W Reset
H/W Reset

Default value
Contents of memory is set randomly
Contents of memory is set randomly
Contents of memory is set randomly

Flow Chart

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.40 Set tear scan line (44h)44 HCommandst
1 parameternd
2 parameter

Description

TESL(Tear Effect Scan Lines)
D/CX RDXWRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0
HEX
0
1
↑
0
1
0
0
0
1
0
0
44
1
1
↑
TELINE[15:8](8’b0)00..FF
1
1↑
TELINE[7:0](8’b0)00..FF
This command is turns on the display module’s Tearing Effect output signal on the TE signal
Line when the display module reacfes line TELINE. The TE signal is not affected bychanging MADCTL bit B4.
The Tearing Effect Line On has one parameter which describes the mode of the Tearing
Effect Output Line.
The Tearing Effect Output line consists of V-Blanking information only:
tvdl

tvdh

Vertical Time
Scale

Note: That TELINE=0 is equivalent to TEMODE=0. The Tearing Effect Output Line shall be active low
when the display module is in Sleep mode.

Restriction

The command has no effect when Tearing Effect output is already ON.

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default ValueTELINE[15:8]=0000h
TELINE[15:8]=0000h
TELINE[15:8]=0000h

Flow Chart

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.41 Get Scan Lines (45h)45 HCommandst

1 parameternd

2 parameterth
3 parameter
Description

GETSL(Mipi new Get Scan Lines)
D/CX RDX WRX D15~D8 D7
0
1
↑
0

D6
1

D5
0

D4
0

D3
0

D2
1

D1
0

D0
1

HEX
45
Dummy
1
↑
1
X
X
X
X
X
X
X
X
read
1
↑
1
SL[15:8]
1↑
1
SL[7:0]The display module returns the current scanline, N, used to update the display device.
The total number of scanlines on a display device is defined as VSYNC + VBP + VACT
+ VFP. The first scanline is defined as the first line of V Sync and is denoted as Line 0.

Restriction

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h

Flow Chart

Himax Confidential
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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.42 Write display brightness value (51h)
51 H

Commandst
1 parameter
Description

WRDISBV (Write Display Brightness Value)
D6
D5
D4
D3
D2
D1
D0
HEX
DNC NWR NRD D15-8 D7
0
↑
1
0
1
0
1
0
0
0
1
51
1
↑
1
DBV7 DBV6 DBV5 DBV4 DBV3 DBV2 DBV1 DBV0 00..FF
This command is used to adjust the brightness value of the display.
The backlight PWM pulse output duty is equal to DBV[7:0]/255 x CABC_duty.

Restriction

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h

LegendWRDISBV(R51h)

CommandParameter

1st Parameter

Display

Flow Chart

New Display
Luminance
Value Loaded

ActionMode
Sequential
transfer

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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.43 Read display brightness value (52h)
52H

RDDISBV (Read Display Brightness Value)
D6
D5
D4
D3
D2
D1
D0
DNC NWR NRD D15-8 D7Command
0
↑
1
0
1
0
1
0
0
1
0
1st parameter
11↑nd
2 parameter
1
1↑
DBV7 DBV6 DBV5 DBV4 DBV3 DBV2 DBV1 DBV0
This command returns the brightness value of the display.

Description

Restriction

HEX
52
xx
xx

DBV[7:0] is reset when display is in sleep-in mode.
DBV[7:0] is ‘0’ when bit BCTRL of “Write CTRL Display (R53h)” command is ‘0’.
DBV[7:0] is manual set brightness specified with “Write CTRL Display (R53h)” command
when bit BCTRL is ‘1’.
When bit BCTRL of “Write CTRL Display (R53h)” command is ‘1’ and bit C1/C0 of “Write
Content Adaptive Brightness Control (R55h)” are ‘0’, DBV[7:0] output is the brightness value
specified with “ Write Display Brightness (R51h)” command.
-

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h

LegendCommand

RDDISBV(R52h)
Host
Display
Flow Chart

Parameter
Display

Dummy Read
ActionMode
Send
2nd Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.170April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.44 Write control display (53h)53HCommandst
1 parameter

WRCTRLD (Write Control Display)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
1
0
1
0
0
1
1
53
1
↑
1
- BCTRL DD
BL
00..FF
This command is used to control display brightness.
BCTRL: Backlight Control Block On/Off, This bit is always used to switch brightness fordisplay.
0 = Off (Brightness registers are 00h, DBV[7:0] of R52h)
1 = On (Brightness registers are active, according to the other parameters.)
Display Dimming (DD): (Only for manual brightness setting)DD = 0: Display Dimming is off
DD = 1: Display Dimming is on

Description
BL: Backlight Control On/Off
0 = Off (Completely turn off backlight circuit. Control lines must be low. )1 = OnDimming function is adapted to the brightness registers for display when bit BCTRL ischanged at DD=1, e.g. BCTRL: 0 -> 1 or 1-> 0.

Restriction

When BL bit change from “On” to “Off”, backlight is turned off without gradual dimming, even
if dimming-on (DD=1) are selected.
-

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h

LegendWRCTRLD(R53h)

CommandParameter

BCTRL, DD, BL

Display

Flow Chart

Action
New Control
Value Loaded

ModeSequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.171April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.45 Read control value display (54h)
54H

RDCTRLD (Read Control Value Display)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0
Command
0
↑
1
0
1
0
1
0
1
0
0
1st parameter
11↑nd
2 parameter
1
1↑
0
0 BCTRL 0DDBL00This command returns ambient light and brightness control values, see chapter:“Write CTRL Display (R53h)”.

HEX
54
xx
xx

BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness fordisplay.
0 = Off
1 = OnDescription
Display Dimming (DD):DD = 0: Display Dimming is off
DD = 1: Display Dimming is on

Restriction

BL: Backlight Control On/Off
0 = Off
1 = On-Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h

LegendCommand

RDCTRLD(R54h)
Host
Display
Flow Chart

Parameter
Display

Dummy Read
ActionMode
Send
2nd Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.172April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.46 Write content adaptive brightness control (55h)
55HCommandst
1 parameter

WRCABC (Write Content Adaptive Brightness Control)
DNC NWR NRD D15-8 D7
D6
D5
D4
0
↑
1
0
1
0
1
1
↑
1
-

D3
0
-

D2
1
-

D1
0
C1

D0
1
C0

HEX
55
00..03This command is used to set parameters for image content based adaptive brightness
control functionality.
There is possible to use 4 different modes for content adaptive image functionality, which
are defined on a table below.
Description

Restriction

C1
0
0
1
1

C0
0
1
0
1

Function
Off
User Interface Image
Still Picture
Moving Image

Note
-

-

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h

LegendWRCABC(R55h)

CommandParameter

C1, C0

Display

Flow Chart

Action
New Adaptive
Image Mode

Mode
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.173April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.47 Read content adaptive brightness control (56h)
56H

RDCABC (Read Content Adaptive Brightness Control)
D6
D5
D4
D3
D2
D1
D0
HEX
DNC NWR NRD D15-8 D7Command
0
↑
1
0
1
0
1
0
1
1
0
56
1st parameter
1
1
↑
xx
nd
2 parameter
1
1
↑
0
0
0
0
0
0
C1
C0
xx
This command is used to read the settings for image content based adaptive brightness
control functionality.
There is possible to use 4 different modes for content adaptive image functionality, which
are defined on a table below.
Description
C1
0
0
1
1
Restriction

C0
0
1
0
1

Function
Off
User Interface Image
Still Picture
Moving Image

Note
-

-

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h

LegendCommand

RDCABC(R56h)
Host
Display
Flow Chart

Parameter
Display

Dummy Read
ActionMode
Send
2nd Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.174April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.48 Write CABC minimum brightness (5Eh)
5EH
Commandst
1 parameter

Description

Restriction

WRCABCMB (Write CABC Minimum Brightness)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
0
1
0
1
1
1
1
0
5E
1
↑
1
CMB7 CMB6 CMB5 CMB4 CMB3 CMB2 CMB1 CMB0 00..FF
This command is used to set the minimum brightness value of the display for CABC
function.
In principle relationship is that 00h value means the lowest brightness for CABC and FFhvalue means the highest brightness for CABC.
-

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h

LegendWRCABCMB(R5Eh)

CommandParameter

CMB[7:0]

Display

Flow Chart

New Display
Luminance
Value Loaded

ActionMode
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.175April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.49 Read CABC minimum brightness (5Fh)
5FH

RDCABCMB (Read CABC Minimum Brightness)
D6
D5
D4
D3
D2
D1
D0
HEX
DNC NWR NRD D15-8 D7Command
0
↑
1
0
1
0
1
1
1
1
1
5F
1st parameter
1
1
↑
xx
nd
2 parameter
1
1↑
CMB7 CMB6 CMB5 CMB4 CMB3 CMB2 CMB1 CMB0xx
This command is used to return the minimum brightness value of CABC function.

Description

In principle relationship is that 00h value means the lowest brightness for CABC and FFhvalue means the highest brightness for CABC.

Restriction

CMB[7:0] is CABC minimum brightness specified with “Write CABC minimum brightness(R5Eh)” command.
-

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
00h
00h
00h

LegendCommand

RDCABCMB(R5Fh)
Host
Display
Flow Chart

Parameter
Display

Dummy Read
ActionMode
Send
2nd Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.176April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.50 Read automatic brightness control self-diagnostic result (68h)
68H
Commandst
1 parameternd
2 parameter

Description

Restriction

RDABCSDR (Read Automatic Brightness Control Self-Diagnostic Result)
DNC NWR NRD D15-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
↑
1
0
1
1
0
1
0
0
0
68
1
1
↑
xx
1
1
↑
D7
D6
0
0
0
0
0
0
xx
This command indicates the status of the display self-diagnostic results for automaticbrightness control after Sleep Out command as described in the table below.
Bit D7: Register Loading Detection.
Bit D6: Functionality Detection.
Bit D5, D4, D3, D2, D1 and D0 are for future use and are set to ‘0’.
-Register
Availability

Default

StatusSleep Out
Sleep In
StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Default Value
00h
00h
00h

Flow Chart

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.177April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.51 Read Black/White Low Bits (70h)70hCommandst
1 parameternd
2 parameter

Description
Restriction

Register
Availability

Default

RDBWLK (Read Black/White Low Bits)
D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
Bkx1

D6
1
x
Bkx0

D5
1
x
Bky1

D4
1
x
Bky0

D3
0
x
Wx1

D2
0
x
Wx0

D1
0
x
Wy1

D0
0
x
Wy0

HEX
70
xx
xx

This command returns the lowest bits of black and white color characteristics.
Black: Bkx and Bky
White: Wx and Wy
StatusAvailability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
YesPartial Mode On, Idle Mode Off, Sleep Out
YesPartial Mode On, Idle Mode On, Sleep Out
Yes
StatusPower On Sequence
S/W Reset
H/W Reset

Default value
XXh
XXh
XXh
LegendSerial I/F Mode

Parallel I/F Mode

Read RDBWLB

Read RDBWLB

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionModendSend 2 Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.178April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.52 Read Bkx (71h)71hCommandst
1 parameternd
2 parameter

Description
Restriction

Register
Availability

Default

RDBkx (Read Bkx)
D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
Bkx9

D6
1
x
Bkx8

D5
1
x
Bkx7

D4
1
x
Bkx6

D3
0
x
Bkx5

D2
0
x
Bkx4

D1
0
x
Bkx3

D0
1
x
Bkx2

HEX
71
xx
xx

This command returns the Bkx bits (Bkx[9:2]) of black color characteristics.
StatusAvailability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
YesPartial Mode On, Idle Mode Off, Sleep Out
YesPartial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
StatusPower On Sequence
S/W Reset
H/W Reset

Default value
XXh
XXh
XXh
LegendSerial I/F Mode

Parallel I/F Mode

Read RDBkx

Read RDBkx

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionMode

Send 2nd Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.179April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.53 Read Bky (72h)72h

RDBky (Read Bky)Commandst
1 parameternd
2 parameter

D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
Bky9

D6
1
x
Bky8

D5
1
x
Bky7

D4
1
x
Bky6

D3
0
x
Bky5

D2
0
x
Bky4

Description
Restriction

This command returns the Bky bits (Bky[9:2]) of black color characteristics.
-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

D1
1
x
Bky3

D0
0
x
Bky2

HEX
72
xx
xx

Availability
Yes
Yes
Yes
Yes
Yes

Default value
XXh
XXh
XXh

Flow Chart

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.180April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.54 Read Wx (73h)73h

RDWx (Read Wx)

Commandst
1 parameternd
2 parameter

D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
Wx9

D6
1
x
Wx8

D5
1
x
Wx7

D4
1
x
Wx6

D3
0
x
Wx5

D2
0
x
Wx4

Description
Restriction

This command returns the Wx bits (Wx[9:2]) of white color characteristics.
-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

D1
1
x
Wx3

D0
1
x
Wx2

HEX
73
xx
xx

Availability
Yes
Yes
Yes
Yes
Yes

Default value
XXh
XXh
XXh

Flow Chart

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.181April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.55 Read Wy (74h)74h

RDWy (Read Wy)

Commandst
1 parameternd
2 parameter

D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
Wy9

D6
1
x
Wy8

D5
1
x
Wy7

D4
1
x
Wy6

D3
0
x
Wy5

D2
1
x
Wy4

Description
Restriction

This command returns the Wy bits (Wy[9:2]) of white color characteristics.
-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

D1
0
x
Wy3

D0
0
x
Wy2

HEX
74
xx
xx

Availability
Yes
Yes
Yes
Yes
Yes

Default value
XXh
XXh
XXh
LegendSerial I/F Mode

Parallel I/F Mode

Read RDWy

Read RDWy

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionModendSend 2 Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.182April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.56 Read Red/Green Low Bits (75h)75hCommandst
1 parameternd
2 parameter

Description
Restriction

RDRGLB (Read Red/Green Low Bits)
D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
Rx1

D6
1
x
Rx0

D5
1
x
Ry1

D4
1
x
Ry0

D3
0
x
Gx1

D2
1
x
Gx0

D1
0
x
Gy1

D0
1
x
Gy0

HEX
75
xx
xx

This command returns the lowest bits of red and green color characteristics.
Red: Rx and Ry
Green: Gx and Gy-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default value
XXh
XXh
XXh
LegendSerial I/F Mode

Parallel I/F Mode

Read RDRGLB

Read RDRGLB

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionMode

Send 2nd Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.183April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.57 Read Rx (76h)76h

RDRx (Read Rx)

Commandst
1 parameternd
2 parameter

D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
Rx9

D6
1
x
Rx8

D5
1
x
Rx7

D4
1
x
Rx6

D3
0
x
Rx5

D2
1
x
Rx4

Description
Restriction

This command returns the Rx bits (Rx[9:2]) of red color characteristics.
-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

D1
1
x
Rx3

D0
0
x
Rx2

HEX
76
xx
xx

Availability
Yes
Yes
Yes
Yes
Yes

Default value
XXh
XXh
XXh
LegendSerial I/F Mode

Parallel I/F Mode

Read RDRx

Read RDRx

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionModendSend 2 Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.184April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.58 Read Ry (77h)77h

RDRy (Read Ry)

Commandst
1 parameternd
2 parameter

D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
Ry9

D6
1
x
Ry8

D5
1
x
Ry7

D4
1
x
Ry6

D3
0
x
Ry5

D2
1
x
Ry4

Description
Restriction

This command returns the Ry bits (Ry[9:2]) of red color characteristics.
-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

D1
1
x
Ry3

D0
1
x
Ry2

HEX
77
xx
xx

Availability
Yes
Yes
Yes
Yes
Yes

Default value
XXh
XXh
XXh
LegendSerial I/F Mode

Parallel I/F Mode

Read RDWy

Read RDWy

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionModendSend 2 Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.185April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.59 Read Gx (78h)78hCommandst
1 parameternd
2 parameter

Description
Restriction

Register
Availability

Default

RDGx (Read Gx)
D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
Gx9

D6
1
x
Gx8

D5
1
x
Gx7

D4
1
x
Gx6

D3
1
x
Gx5

D2
0
x
Gx4

D1
0
x
Gx3

D0
0
x
Gx2

HEX
78
xx
xx

This command returns the Gx bits (Gx[9:2]) of green color characteristics.
StatusAvailability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
YesPartial Mode On, Idle Mode Off, Sleep Out
YesPartial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
StatusPower On Sequence
S/W Reset
H/W Reset

Default value
XXh
XXh
XXh
LegendSerial I/F Mode

Parallel I/F Mode

Read RDGx

Read RDGx

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionMode

Send 2nd Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.186April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.60 Read Gy (79h)79h

RDGy (Read Gy)

Commandst
1 parameternd
2 parameter

D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
Gy9

D6
1
x
Gy8

D5
1
x
Gy7

D4
1
x
Gy6

D3
0
x
Gy5

D2
1
x
Gy4

Description
Restriction

This command returns the Gy bits (Gy[9:2]) of green color characteristics.
-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

D1
1
x
Gy3

D0
1
x
Gy2

HEX
79
xx
xx

Availability
Yes
Yes
Yes
Yes
Yes

Default value
XXh
XXh
XXh
LegendSerial I/F Mode

Parallel I/F Mode

Read RDGy

Read RDGy

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionModendSend 2 Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.187April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.61 Read Blue/AColur Low Bits (7Ah)
7AhCommandst
1 parameternd
2 parameter

Description
Restriction

Register
Availability

Default

RDBALB (Read Blue/AColour Low Bits)
D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
Bx1

D6
1
x
Bx0

D5
1
x
By1

D4
1
x
By0

D3
1
x
Ax1

D2
0
x
Ax0

D1
1
x
Ay1

D0
0
x
Ay0

HEX
7A
xx
xx

This command returns the lowest bits of blue and A color characteristics.
Blue: Bx and By
A: Ax and Ay
If A is not used Ax[1:0] and Ay[1:0] bits are set to ‘0’s.
StatusAvailability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
YesPartial Mode On, Idle Mode Off, Sleep Out
YesPartial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
StatusPower On Sequence
S/W Reset
H/W Reset

Default value
XXh
XXh
XXh
LegendSerial I/F Mode

Parallel I/F Mode

Read RDBALB

Read RDBALB

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionMode

Send 2nd Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.188April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.62 Read Bx (7Bh)
7Bh

RDBx (Read Bx)

Commandst
1 parameternd
2 parameter

D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
Bx9

D6
1
x
Bx8

D5
1
x
Bx7

D4
1
x
Bx6

D3
1
x
Bx5

D2
0
x
Bx4

Description
Restriction

This command returns the Bx bits (Bx[9:2]) of blue color characteristics.
-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

D1
1
x
Bx3

D0
1
x
Bx2

HEX
7B
xx
xx

Availability
Yes
Yes
Yes
Yes
Yes

Default value
XXh
XXh
XXh
LegendSerial I/F Mode

Parallel I/F Mode

Read RDBx

Read RDBx

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionMode

Send 2nd Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.189April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.63 Read By (7Ch)
7Ch

RDBy (Read By)

Commandst
1 parameternd
2 parameter

D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
By9

D6
1
x
By8

D5
1
x
By7

D4
1
x
By6

D3
1
x
By5

D2
1
x
By4

Description
Restriction

This command returns the Gy bits (Gy[9:2]) of Blue color characteristics.
-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

D1
0
x
By3

D0
0
x
By2

HEX
7C
xx
xx

Availability
Yes
Yes
Yes
Yes
Yes

Default value
XXh
XXh
XXh
LegendSerial I/F Mode

Parallel I/F Mode

Read RDBy

Read RDBy

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionModendSend 2 Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.190April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.64 Read Ax (7Dh)
7DhCommandst
1 parameternd
2 parameter

Description
Restriction

RDAx (Read Ax)
D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
Ax9

D6
1
x
Ax8

D5
1
x
Ax7

D4
1
x
Ax6

D3
1
x
Ax5

D2
0
x
Ax4

D1
0
x
Ax3

D0
0
x
Ax2

HEX
78
xx
xx

This command returns the Ax bits (Ax[9:2]) of A color characteristics.
Ax[9:2] are set to ‘0’s if they are not used.
-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default value
XXh
XXh
XXh
LegendSerial I/F Mode

Parallel I/F Mode

Read RDAx

Read RDAx

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionMode

Send 2nd Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.191April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.65 Read Ay (7Eh)
7EhCommandst
1 parameternd
2 parameter

Description
Restriction

RDAy (Read Ay)
D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
0
x
Ay9

D6
1
x
Ay8

D5
1
x
Ay7

D4
1
x
Ay6

D3
1
x
Ay5

D2
1
x
Ay4

D1
1
x
Ay3

D0
0
x
Ay2

HEX
7E
xx
xx

This command returns the Ay bits (Ay[9:2]) of A color characteristics.
Ay[9:2] are set to ‘0’s if they are not used.
-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default value
XXh
XXh
XXh
LegendSerial I/F Mode

Parallel I/F Mode

Read RDAy

Read RDAy

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionMode

Send 2nd Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.192April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.66 Read_DDB_start (A1h)
A1hCommandst
1 parameternd
2 parameterrd
3 parameterth
4 parameterth
5 parameterth
6 parameter

Description

Restrictions

Read_DDB_start
D/CX
0
1
1
1
1
1
1

RDX
1
↑
↑
↑
↑
↑
↑

WRX
↑
1
1
1
1
1
1

D15-D8
-

-

D7
1
x
x
x
x
x
1

D6
0
x
x
x
x
x
1

D5
1
x
x
x
x
x
1

D4
0
x
x
x
x
x
1

D3
0
x
x
x
x
x
1

D2
0
x
x
x
x
x
1

D1
0
x
x
x
x
x
1

D0
1
X
x
x
x
x
1

HEX
A1
Dummy read
xx
xx
xx
xx
FF

The format of returned data is as follows:
Parameter 2: LS (least significant) byte of Supplier ID. Supplier ID is a unique value assigned
to each peripheral supplier by the MIPI organization.
Parameter 3: MS (most significant) byte of Supplier ID.
Parameter 4: LS (least significant) byte of Supplier Elective Data. This is a byte of informationthat is determined by the supplier. It could include model number or revision information, forexample.
Parameter 5: MS (most significant) byte of Supplier Elective Data
Parameter 6: single-byte Escape or Exit Code (EEC). The code is interpreted as follows:- FFh - Exit code – there is no more data in the Descriptor Block- 00h - Escape code – there is supplier-proprietary data in the Descriptor Block (does notconform to any MIPI standard)-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default valuendthth
PA 2 ~5 =OTP Value, PA 6 =FFhndthth
PA 2 ~5 =OTP Value, PA 6 =FFhndthth
PA 2 ~5 =OTP Value, PA 6 =FFh

Flow Chart

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.193April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.67 Read_DDB_continue (A8h)
A8hCommandst
1 parameternd
2 parameter:th
N parameter

Description
Restrictions

Register
Availability

Read_DDB_continue
D/CX
0
1
1
1
1

RDX
1
↑
↑
↑
↑

WRX
↑
1
1
1
1

D7
1
x
x
x
x

D6
0
x
x
x
x

D5
1
x
x
x
x

D4
0
x
x
x
x

D3
1
x
x
x
x

D2
0
x
x
x
x

D1
0
x
x
x
x

D0
0
x
x
x
x

HEX
A8
Dummy read
xx
xx
xx

A read_DDB_start command should be executed at least once before a read_DDB_continuecommand to define the read location. Otherwise, data read with a read_DDB_continuecommand is undefined.
StatusAvailability
Normal Mode On, Idle Mode Off, Sleep Out
Yes
Normal Mode On, Idle Mode On, Sleep Out
YesPartial Mode On, Idle Mode Off, Sleep Out
YesPartial Mode On, Idle Mode On, Sleep Out
Yes
Sleep In or Booster Off
Yes
StatusPower On Sequence

Default

D15-D8-S/W Reset
H/W Reset

Default valuendthWithout reading A1h, read PA 2 ~5 is the same as A1h
ndthth
2 ~5 OTP value, and the 6 read is FFh.
ndth
Without reading A1h, read PA 2 ~5 is the same as A1h
ndthth
2 ~5 OTP value, and the 6 read is FFh.
ndth
Without reading A1h, read PA 2 ~5 is the same as A1h
ndthth
2 ~5 OTP value, and the 6 read is FFh.

Flow Chart

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.194April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.68 Read first checksum (AAh)AAHCommandst
1 parameternd
2 parameter

Description
Restrictions

RDFCS (Read First Checksum)
D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
1
XX

D6
0
XX

D5
1
XX

D4
D3
0
1
XX
XX
FCS[7:0]

D2
0
XX

D1
1
XX

D0
0
XX

HEX
AA
Dummy readxx

This command returns the first checksum what has been calculated from
The area registers and the frame memory after the write access to those registers and/or
frame memory has been done.
It will be necessary to wait 150ms after there is the last write access on command area
registers before there can read this checksum value.

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

FCS[7:0] = 0x00h

Availability
Yes
Yes
Yes
Yes
Yes
LegendSerial I/F Mode

Parallel I/F Mode

Read FCS

Read FCS

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionMode

Send 2nd Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.195April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.69 Read continue checksum (AFh)
AFH
Commandst
1 parameternd
2 parameter

Description
Restrictions

RDCCS (Read Continue Checksum)
D/CX
0
1
1

RDX
1
↑
↑

WRX
↑
1
1

D15-D8
-

D7
1
XX

D6
0
XX

D5
1
XX

D4
D3
0
1
XX
XX
CCS[7:0]

D2
1
XX

D1
1
XX

D0
1
XX

HEX
AA
Dummy readxx

This command returns the continue checksum what has been calculated continuously after
the first checksum has calculated from command area registers and the frame memory after
the write access to those registers and/or frame memory has been done.
It will be necessary to wait 300ms after there is the last write access on commandarea registers before there can read this checksum value in the first time.

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

CCS[7:0] = 0x00h

Availability
Yes
Yes
Yes
Yes
Yes
LegendSerial I/F Mode

Parallel I/F Mode

Read CCS

Read CCS

CommandParameter

Flow Chart

Send 2nd Parameter

Dummy Read

Host
Display

Display
ActionMode

Send 2nd Parameter
Sequential
transfer

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.196April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.70 Read ID1 (DAh)DA H

RDID1 (Read ID1)
NWR
NRD
DNC
0
↑
1
1
1
↑
1
1
↑

D15-8
-

D7
1
-

D6
D5
D4
D3
D2
D1
1
0
1
1
0
1
module’s manufacturer m[7:0]Command
1st parameternd
2 parameter
Description

This read byte identifies the LCD module’s manufacturer.

Restriction-

Register
Availability

Default

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
StatusPower On Sequence
S/W Reset
H/W Reset

D0
0
-

HEX
DA
-

00

Availability
Yes
Yes
Yes
Yes
Yes

Default Value

xxHEX
xxHEX
xxHEX

Flow Chart

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.197April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.71 Read ID2 (DBh)DB H

RDID2 (Read ID2)DNC NWR NRD D15-8
Command0↑
1
st
1 parameter
11↑nd
2 parameter 1
1↑
Description

Restrictions

D7
1
V7

D6
1
V6

D5
0
V5

D4
1
V4

D3
1
V3

D2
0
V2

D1
1
V1

D0
1
V0

HEX
DB
80

This read byte is used to track the LCD module/driver version. It is defined by display
supplier and changes each time a revision is made to the display, material or construction
specifications.
-Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value

xxHEX
xxHEX
xxHEX

Flow Chart

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.198April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.72 Read ID3 (DCh)DC H

RDID3 (Read ID3)DNC NWR NRD D15-8 D7
D6
D5Command0↑
1
1
1
0
1st parameter 1
1↑nd
2 parameter 1
1
↑
ID7
ID6
ID5
This read byte identifies the LCD module/driver.
Description
Restrictions

D4
1
ID4

D3
1
ID3

D2
1
ID2

D1
0
ID1

D0
0
ID0

HEX
DC
00

-

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Default

StatusPower On Sequence
S/W Reset
H/W Reset

Availability
Yes
Yes
Yes
Yes
Yes

Default Value

xxHEX
xxHEX
xxHEX

Flow Chart

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.199April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.73 SETOSC: set internal oscillator (B0h)
B0 H
DNC NWR
Commandst
1 parameternd

2 parameter

NRD D17-8

SETOSC( Set Internal Oscillator)
D7
D6
D5
D4
D3

0
1

↑
↑

1
1

-

1

0
1
I_UADJ[3:0]

1

0

1

↑

1

-

-

-

-

-

-

D2

D1

D0

HEX

0
0
N_UADJ[3:0]

0

B0
66

-

-

OSC_
EN

00

These command is used to set internal oscillator related setting
OSC_EN: Enable internal oscillator, OSC_EN = ‘1’, internal oscillator start to oscillate.
OSC_EN = ‘0’, internal oscillator stop.
N_UADJ[3:0]: Internal oscillator frequency adjusts in Normal / Partial mode.
I_UADJ[3:0]: Internal oscillator frequency adjusts in Idle(8-color) / Partial Idle mode.
UADJ3 UADJ2 UADJ1 UADJ0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Description

Restrictions

Register
Availability

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Internal Oscillator
Frequency
50% x 10MHz
58% x 10MHz
67% x 10MHz
75% x 10MHz
83% x 10MHz
92% x 10MHz
100% x 10MHz
108% x 10MHz
116% x 10MHz
125% x 10MHz
133% x 10MHz
142% x 10MHz
150% x 10MHz
158% x 10MHz
167% x 10MHz
175% x 10MHz

Display Frame rate
30Hz
35Hz
40Hz
45Hz
50Hz
55Hz
60Hz
65Hz
70Hz
75Hz
80Hz
85Hz
90Hz
95Hz
100Hz
105Hz

Must enable SETEXTC command
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.200April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.74 SETPOWER: set power control (B1h)
B1 H
Commandst
1
parameternd2parameterrd3parameterth4parameterth5parameterth6parameterth7parameter

DNC NWR NRD D17-8
0
↑
1
-

D7
1

SETPOWER (Set power control )
D6
D5
D4
D3
0
1
1
0

D2
0

D1
0

D0
1

HEX
B1

-

-

DP_STB

00

1

↑

1

-

-

-

-

-

-

1

↑

1

-

-

-

TRI

XDK

-

1

↑

1

-

-

-

VRH[5:0]

1C--

NVRH[5:0]

1C

GASEN

-

1

↑

1

-

1

↑

1

-

FS1[3:0]

1

↑

1

-

VCOMG

-

-

11

BT[2:0]-83

AP[2:0]FS0[3:0]
1

PON

DK

0

0

5C
29

STB

DP_STB,: These two bits can let the driver into the deep standby mode. And when into deep standby, alldisplay operation stops, including the internal R-C oscillator. In the deep standby mode, the GRAM data
and register content are not retained.

XDK, TRI: Specify the ratio of step-up circuit for VSP voltage generation.
TRI
0
0
1
1

XDK
0
1
0
1

Step up circuit 1
2 x VCI
2 x VCI
3 x VCI
Setting inhabited

Capacitor connection pins
C11P, C11N
C11P, C11N, C12P, C12N
C11P, C11N, C12P, C12N
Setting inhabited

VRH[5:0]: Specify the VSPROUT voltage adjusting. VSPROUT voltage is for gamma voltage
NVRH[5:0]: Specify the VSNR voltage adjusting. VSNR voltage is for gamma voltage
TRI=0
VRH[5:0]
NVRH[5:0](Hex)

VSPROUTVSNROUT(V)

VRH[5:0]
NVRH[5:0](Hex)

VSPROUTVSNROUT(V)

VRH[5:0]
NVRH[5:0](Hex)

VSPROUTVSNROUT(V)

0

3.09/-3.09

B

3.61/-3.61

16

4.13/-4.13

1
2
3
4
5
6
7
8
9
A

3.14/-3.14
3.19/-3.19
3.23/-3.23
3.28/-3.28
3.33/-3.33
3.38/-3.38
3.42/-3.42
3.47/-3.47
3.52/-3.52
3.56/-3.56

C
D
E
F
10
11
12
13
14
15

3.66/-3.66
3.70/-3.70
3.75/-3.75
3.80/-3.80
3.84/-3.84
3.89/-3.89
3.94/-3.94
3.98/-3.98
4.03/-4.03
4.08/-4.08

17
18
19
1A
1B
1C
1D
1E
1F
20~3F

4.17/-4.17
4.22/-4.22
4.27/-4.27
4.31/-4.31
4.36/-4.36
4.41/-4.41
4.45/-4.45
4.50/-4.50
STOP
STOP

Description

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.201April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

VRH[5:0]
NVRH[5:0](Hex)
0

VSPROUTVSNROUT(V)
3.09/-3.09

1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11

3.14/-3.14
3.19/-3.19
3.23/-3.23
3.28/-3.28
3.33/-3.33
3.38/-3.38
3.42/-3.42
3.47/-3.47
3.52/-3.52
3.56/-3.56
3.61/-3.61
3.66/-3.66
3.70/-3.70
3.75/-3.75
3.80/-3.80
3.84/-3.84
3.89/-3.89

TRI=1
VRH[5:0] VSPROUT
NVRH[5:0] VSNROUT
(Hex)
(V)
12
3.94/-3.94
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23

VRH[5:0]
NVRH[5:0](Hex)
24

VSPROUTVSNROUT(V)
4.78/-4.78

3.98/-3.98
4.03/-4.03
4.08/-4.08
4.13/-4.13
4.17/-4.17
4.22/-4.22
4.27/-4.27
4.31/-4.31
4.36/-4.36
4.41/-4.41
4.45/-4.45
4.50/-4.50
4.55/-4.55
4.59/-4.59
4.6
4.64/-4.64

25
26
27
28
29
2A
2B
2C
2D
2E
2F
30

4.83/-4.83
4.88/-4.88
4.92
4.92/-4.92

31
32

4.97/-4.97
5.02/-5.02
5.06/-5.06
5.11/-5.11
5.16/-5.16
5.20/-5.20
5.25/-5.25
5.30/-5.30
5.34/-5.34
5.39/-5.39
5.44/-5.44

4.69/-4.69
4.73/-4.73

33~3F

STOP

Note: Internal VREF can be modified by Custom’s special request.
VSPR={Decimal(VRH[5:0])x0.05+3.3 }*(VREF/4.8) if TRI=0.
VSNR={Decimal(VRH[5:0])x0.05+3.3 }*(VREF/5.8) if TRI=1.
Note: Internal nVREF can be modified by Custom’s special request.
VSNR={Decimal(-NVRH[5:0])x0.05-3.3 }*(nVREF/4.8) if TRI=0.
VSNR={Decimal(-NVRH[5:0])x0.05-3.3 }*(nVREF/5.8) if TRI=1.

BT[2:0]: Switch the output factor of step-up circuit 2 for VGH and VGL voltage generation.
BT2
BT1
BT0
VSP
VGH
VGL
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Note: When VCI = 2.8V, TRI=0

0
1
0
1
0
1
0
1

5.1V
5.1V
5.1V
5.1V
5.1V
5.1V
5.1V
5.1V

3VSP
3 VSP
3 VSP
VCI + 2 VSP
VCI + 2 VSP
VCI + 2 VSP
2 VSP
2 VSP

-3 VSP-2 VSP-2 VSP-VCI-2 VSP-2 VSP
VCI-2 VSP
-2 VSP
VCI- VSP

FS0[3:0]: Set the operating frequency for VSP and VSN voltage generation.
Operation
Operation
FS0[3:0]FS0[3:0]
Frequency for
Frequency for
(HEX)
(HEX)
VSP and VSN
VSP and VSN
0
Setting Inhibited
8
Fosc/2881
Fosc/32
9
Fosc/3202
Fosc/48
A
Fosc/352
3
Fosc/64B
Fosc/384
4
Fosc/80C
Fosc/4165
Fosc/96D
Fosc/4486
Fosc/112
E
Fosc/4807
Fosc/128F
Fosc/512

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.202April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

FS1[3:0]: Set the operating frequency for VGH/VGL voltage generation.
FS1[3:0]
(HEX)
0
1
2
3
4
5
6
7

Operation Frequency for
VGH and VGL
Setting Inhibited
Fosc/32
Fosc/48
Fosc/64
Fosc/80
Fosc/96
Fosc/112
Fosc/128

FS1[3:0]
(HEX)
8
9
A
B
C
D
E
F

Operation Frequency for
VGH and VGL
Fosc/288
Fosc/320Fosc/352
Fosc/384
Fosc/416
Fosc/448
Fosc/480
Fosc/512

AP[2:0]: Adjust the amount of current driving for the operational amplifier in the power supply
circuit.
AP2
0
0
0
0
1
1
1
1

AP1
0
0
1
1
0
0
1
1

AP0
0
1
0
1
0
1
0
1

Constant Current of Operational Amplifier
Operation of the operational amplifier stops
Small
Small
Small
MediumMedium High
Large
Small

STB: When STB = “1”, the HX8357-D into the standby mode, where all display operation stops,
suspend all the internal operations including the internal R-C oscillator.
In the standby mode, the GRAM data and register content will be keeping.
GASEN: This stands for abnormal power-off monitor function when the power is off.
DK: Specify on/off control of step-up circuit 1 for VSP voltage generation. For detail, see thePower Supply Setting Sequence.
DK
01

Operation of step-up circuit 1
ON
OFF

PON: Specify on/off control of step-up circuit 2 for VGH, VGL voltage generation.
For detail, see the Power Supply Setting Sequence.
PON
01

Operation of step-up circuit 2
OFFON

VCOMG: Specify on/off control of step-up circuit 3 for VSN voltage generation. For detail, see
the Power Supply Setting Sequence.
VCOMG
0
1
Restrictions Must enable SETEXTC command

Operation of step-up circuit 3
OFFON

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.203April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.204April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.75 SETDISPLAY: set display related register (B2h)
B2H
Commandst
1 parameternd
2 parameterrd
3 parameterrd
3 parameterrd
3 parameter

SETDISCTRL ( Set display control )DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
0
↑
1
1
0
1
1
0
0
1
↑
1
ISC3 ISC2
1↑
1
PT1 PT0
1↑
1
NL[5:0]1↑
1SCN[6:0]
1↑
1
GON DTE
D1
D0This command is used to set display related register

D1
1
ISC1
PTG

D0
0
ISC0
REF

-

-

HEX
B2
00
83
3B
00
20

D[1:0]: When D1 = ‘1’, display is on; when D1 = ‘0’, display is off. When display is off, thedisplay data is retained in the GRAM and the entire source outputs are set to the VSSD
level.
When D[1:0]= ‘01’, the internal display of the HX8357-D is performed although the actual
display is off. When D[1:0]= ‘00’, the internal display operation halts and the display is off.
D1
0
0
1
1

D0
0
1
0
1

Source Output
VSSD
VSSD
=PT(0,0)
DisplayInternal Display Operations
Halt
OperateOperateOperateGate-Driver Control Signals
Halt
OperateOperateOperateGON, DTE:
GON
0
1
1

DTE
x
0
1

Gate Output
Fixed to VGHFixed to VGL
Normal Operation (VGH/VGL)

PT[1:0] : Specify the Non-display area source output in partial display mode.
Description

Source Output Level
Non-display Area
REV_Panel

GRAM
Data

Display area
PT1-0=(0,*)

PT1-0=(1,0) PT1-0=(1,1)

Positive Negative Positive Negative1
18’h00000(Normally.
Black Panel) 18’h3FFFF0
18’h00000(Normally.
White Panel) 18’h3FFFF

V63P
.
V0P
V0P
.
V63P

V0N
.
V63N
V63N
.
V0N

V63P

-

V0N
GND

V63P

Hi-z

V0N

REF: Refresh display in non-display area in Partial mode enable bit.
REF = ‘0’: Refresh display operation is disabling.
REF = ‘1’: Refresh display operation is enable.
PTG: Specify the scan mode of gate driver in non-display area.
PTG
01

Gate Outputs in Non-display Area
Normal Drive
Fixed VGL

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.205April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
ISC[3:0]: Specify the scan cycle of gate driver when REF = ‘1’ in non-display area. Then
scan cycle is set to Decimal(ISC[3:0])x4+1.The polarity is inverted every scan cycle.
ISC3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

ISC2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

ISC1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

ISC0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Scan Cycle
1 frame
5 frames
9 frames
13 frames
17 frames
21 frames
25 frames
29 frames

fFLM = 60Hz
17ms
83ms
150ms
217ms
283ms
350ms
417ms
483ms

33 frames
37 frames
41 frames
45 frames
49 frames
53 frames
57 frames

550ms
616ms
683ms
750ms
816ms
883ms
950ms

Setting inhibited

NL[5:0]: Set the number of lines to drive the LCD at an interval of 8 lines. The GRAM address
mapping is not affected by the number of lines set by NL[5:0]. The number of lines must be
the same or more than the number of lines necessary for the size of the liquid crystal panel.
NL5
0
0
0
:
1
1

NL4
0
0
0
:
1
1

NL3
NL2
0
0
0
0
0
0
:
:
1
0
1
0
Other Setting

NL1
0
0
1
:
1
1

NL0
0
1
0
:
0
1

LCD Drive Lines
8 lines
16 lines
24 lines:
472 lines
480 lines
480 lines

SCN[6:0]: Specifies the gate line where the gate driver starts scan.
SCN[6:0]00h~63hOthersRestrictions

Scanning Start Position
GS=0
G(1+SCN[6:0]*4)
Setting inhibited

GS=1
G(SCN[6:0]*4+NL[5:0]*8)
Setting inhibitedMust enable SETEXTC command

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.206April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.76 SETRGB: set RGB interface (B3h)
B3 H

SETRGBIF( Set RGB interface related register)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0
Command
0
↑
1
1
0
1
1
0
0
1
1
SDO_ BYP
st
1 parameter1↑
1
EPF[1:0]
RM
DM
EN
ASS
nd
2 parameter
1↑
1
DPL HSPL VSPL EPL
RCrd
3 parameter
1↑
1
HBP[5:0]Mth
4 parameter
1↑
1
VBP[5:0]This command is used to set RGB interface related register
SDO_EN: SDO Pin Enable.
SDO_EN
Input Pin
Output pin
SDA
SDA
0
SDA
SDO
1

HEX
B3
00
00
06
06

RM setting is enabled from the next frame. Wait 1 frame to transfer data after
setting.
RM
0
1

Interface for RAM access
DBI Interface (MPU)
DPI Interface (RGB)

DM bit is used to select display operation mode. The setting allows switching
between display operation in synchronization with internal oscillation clock,
VSYNC, or DPI signal.
DM
01

Description

Display Mode
Internal oscillation clock
DPI interface

BYPASS: Select the display data path whether memory or direct to display in RGB interface.
BYPASSInterface SelectMemory0
Direction
to display
1
Note: When set BYPASS=0, must ensure internal OSC faster than PCLK.

RCM: Select RGB interface mode.
RCM
0
1

Interface SelectRGB mode 1(VS+HS+DE)
RGB mode 2(VS+HS)BYPASS

RCM

RM

DM

Ram

Display

x
x
0
0
1
1

x
x
0
1
0
1

0
0
1
1
1
1

0
1
1
1
1
1

MPU
MPU
RGB1
RGB2
RGB1
RGB2

Internal
V-sync interface
RGB1
RGB2
RGB1
RGB2

Himax Confidential
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in whole or in part without prior written permission of Himax.

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
EPL: Specify the polarity of Enable pin in RGB interface mode.
EPL
ENABLE pin
Display image
0
High
Enable0
Low
Disable1High
Disable1
Low
EnableOperation
Write data to
D17-0
DisableDisableWrite data to
D17-0
VSPL: The polarity of VSYNC pin. When VSPL=0, the VSYNC pin is Low active. WhenVSPL=1, the VSYNC pin is High active.
HSPL: The polarity of HSYNC pin. When HSPL=0, the HSYNC pin is Low active. WhenHSPL=1, the HSYNC pin is High active.
DPL: The polarity of DOTCLK pin. When DPL=0, the data is read on the rising edge of
DOTCLK signal. When DPL=1, the data is read on the falling edge of DOTCLK signal.
HBP[5:0]: Set the delay period from falling edge of HSYNC signal to first valid data in DPI I/F
mode 2
HBP[5:0]
00d
01d
02d
03d
04d
:
62d
63d

No. of clock cycle of DOTCLK
Setting Inhibited
Setting Inhibited
2
3
4
:
62
Setting Inhibited

VBP[5:0]: Set the delay period from falling edge of VSYNC signal to first valid line in DPI I/F
mode 2
VBP[5:0]
00d
01d
02d
03d
04d
:
61d
62d
63d

No. of clock cycle of HSYNC
Setting Inhibited
Setting Inhibited
2
3
4
:
61
62
Setting Inhibited

EPF[1:0]: 65K color mode data format

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.208April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Restrictions

Register
Availability

Must enable SETEXTC command
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.209April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.77 SETCYC: set display cycle register (B4h)
B4 H
Commandst
1 parameternd
2 parameterrd

3 parameterth

4 parameterth
5 parameterth
6 parameterth
7 parameter

SETCYC( Set display cycle register)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
0
↑
1
1
0
1
1
0
1
1
↑
1
ZINV
I_NW[1:0]
1↑
1
RTN[6:0]
OSC_
1
↑
1
DIV2
1
↑
1
N_DUM[7:0]1↑
1
I_DUM[7:0]1↑
1
GDON[7:0]
1↑
1
GDOF[7:0]
This command is used to set display related register
ZINV: Set Z-inversion mode.
ZINV
0
1

D1
D0
0
0
N_NW[1:0]

HEX
B4
02
40

DIV[1:0]

00
2A
2A
0D
96

Z-inversion
DisableEnableN_ NW[1:0]: Specify LCD driving inversion type in Normal/ Partial mode.
I_ NW[1:0]: Specify LCD driving inversion type in Idle / Partial Idle mode.
NW[1:0]0d1d2d3d
OSC_DIV2: Set the internal clock divide by 2.

Description

LCD driving Inversion Type
Column inversion
1-dot inversion
2-dot inversion
4-dot inversion

DIV[1:0]: Specify the division ratio of internal clocks mode for internal operation. Whenused internal clock for the display operation, frame frequency can be adjusted with thesebits.
fosc = R-C oscillation frequency
DIV1
DIV0
Division Ratio Internal Display Operation Clock Frequency
001
fosc / 10
1
2
fosc / 21
0
4
fosc / 41
1
8
fosc / 8
RTN[6:0]: Specify clock number of one line period for internal operation.
Clock cycles=1/internal operation clock frequency(fosc)
RTN[6:0]
Clock number per Line00h~7Fh
192+RTN[6:0]*2
320
Default:40h
N_DUM[7:0]: Specify dummy line number in blanking area of one frame in Normal / Partial
mode for internal operation.
I_DUM[7:0]: Specify dummy line number in blanking area of one frame in Idle (8-color) /Partial Idle mode for internal operation.
DUM[7:0]
000d
001d
002d
003d
004d

Line number in blanking period
Setting Inhibited
Setting Inhibited2
3
4

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.210April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00:
190d
others:190
Setting Inhibited

Formula for the Frame Frequency during internal display mode:
Frame frequency = fosc/( RTN × DIV × (320+DUM) ) [Hz]fosc: RC oscillation frequency
GDON[7:0]: Specify the valid gate output start time in 1-line driving period. The period timevalue is defined as SYSCLK number in internal clock display mode. The
period time value is defined as DOTCLK number in 18/16-bit bus width RGB
display mode and is defined as DOTCLK/3 number in 6-bit bus width RGB
display mode. (Please note that the setting “00h”, “01h”, “02h” is inhibited).
GDOF[7:0]: Specify the gate output end time in 1-line driving period. The period time value
is defined as SYSCLK number in internal clock display mode. The period timevalue is defined as DOTCLK number in 18/16-bit bus width RGB display mode
and is defined as DOTCLK/3 number in 6-bit bus width RGB display mode.
(Please note that the GDON[7:0] + 1≤ GDOF[7:0] ≤ RTN-1).
1- Line Period

S 1 – S720

Source Output Period
GDON

GDOF
Gate Output Period

VCOM

G(N)
Nth Gate Output Period
G(N+1)
N+1 th Gate Output Period

Restrictions

Must enable SETEXTC command

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.211April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.78 SETBGP (B5h)
B5 H
Commandst
1 parameternd
2 parameterrd
3 parameter

SETPTBA ( Set Power Option)
D/CX RDX WRX D15-D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
↑
1
0
1
1
1
1
0
1
1
1
↑
VREF[3:0]
1
1↑
nVREF[2:0]1
1↑
VPP[2:0]
VVDHS[2:0]
VREF[3:0]: Specify VREF voltage. This command will affect the VSPR voltage.
nVREF[3:0]: Specify nVREF voltage. This command will affect the VSNR voltage.
VSPR={Decimal(VRH[5:0])x0.05+3.3 }*(VREF/4.8)
VSNR={Decimal(NVRH[5:0])x0.05+3.3 }*(nVREF/4.8)

VREF[3:0]/nVREF
0
0
0
0
0
0
0
0
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0

0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1

others

TRI=0
VREF/nVREF
4.1V/-4.1V
4.2V/-4.2V
4.3V/-4.3V
4.4V/-4.4V
4.45V/-4.45V
4.5V/-4.5V
4.55V/-4.55V
4.6V/-4.6V
4.65V/-4.65V
4.7V/-4.7V
4.75V/-4.75V
4.8V/-4.8V

TRI=1
VREF/nVREF
5.1V/-5.1V
5.2V/-5.2V
5.3V/-5.3V
5.4V/-5.4V
5.45V/-5.45V
5.5V/-5.5V
5.55V/-5.55V
5.6V/-5.6V
5.65V/-5.65V
5.7V/-5.7V
5.75V/-5.75V
5.8V/-5.8V

Setting disable

Setting disable

HEX
B5
05
05
63

VVDHS[2:0]: Specify VSP/VSN voltage.
Description

VVDHS[2:0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

TRI=0
VSP/VSN

TRI=1
VSP/VSN

4.64V/-4.64V

6.08V/-6.08V

4.80V/-4.80V

6.37V/-6.37V

5.07V/-5.07V

6.68V/-6.68V

5.26V/-5.26V

5.59V/-5.59V

5.35V/-5.35V

5.70V/-5.70V

5.47V/-5.47V

5.82V/-5.82V

5.59V/-5.59V

5.95V/-5.95V

5.70V/-5.70V

8.05V/-8.05V

VPP[2:0]: Specify the OTP VPP voltage.

VPP[2:0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Restrictions

0
0
1
1
0
0
1
1

VPP
0
1
0
1
0
1
0
1

7.2V
7.3V
7.4V
7.5V
7.6V
7.7V
7.8V
External

1 turn on to enable this command.
SETEXTC

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.212April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In

Register
Availability

Flow Chart

Availability
Yes
Yes
Yes
Yes
Yes

-

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.213April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.79 SETCOM: set VCOM voltage related register (B6h)
B6 H
Command

DNC NWR
0↑

NRD D17-8
1-

SETCOM ( Set VCOM Voltage)
D7
D6
D5
D4
D3
1
0
1
1
0

st

1

↑

1

-

-

nd

1

1

↑

-

-

1 parameter2 parameter

-

-

D2
1

D1
1

D0
0

HEX
B6

VCOM[6:0]
VCOM_OTP_TIMES[
2:0]

4B

This command is used to set VCOM Voltage.
VCOM[6:0]: DC VCOM voltage setting.
VCOM
[6:0]
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F

Description

VCOM
Voltage

-2.34
-2.33
-2.31
-2.29
-2.27
-2.25
-2.23
-2.21
-2.19
-2.18
-2.16
-2.14
-2.12
-2.10
-2.08
-2.06
-2.04
-2.03
-2.01
-1.99
-1.97
-1.95
-1.93
-1.91
-1.89
-1.88
-1.86
-1.84
-1.82
-1.80
-1.78
-1.76

VCOM
[6:0]
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F

VCOM
Voltage

-1.74
-1.73
-1.71
-1.69
-1.67
-1.65
-1.63
-1.61
-1.59
-1.58
-1.56
-1.54
-1.52
-1.50
-1.48
-1.46
-1.44
-1.43
-1.41
-1.39
-1.37
-1.35
-1.33
-1.31
-1.29
-1.28
-1.26
-1.24
-1.22
-1.20
-1.18
-1.16

VCOM
[6:0]
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F

VCOM
Voltage

-1.14
-1.13
-1.11
-1.09
-1.07
-1.05
-1.03
-1.01
-0.99
-0.98
-0.96
-0.94
-0.92
-0.90
-0.88
-0.86
-0.84
-0.83
-0.81
-0.79
-0.77
-0.75
-0.73
-0.71
-0.69
-0.68
-0.66
-0.64
-0.62
-0.60
-0.58
-0.56

VCOM
[6:0]
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F

VCOM
Voltage

-0.54
-0.53
-0.51
-0.49
-0.47
-0.45
-0.43
-0.41
-0.39
-0.38
-0.36
-0.34
-0.32
-0.30
-0.28
-0.26
-0.24
-0.23
-0.21
-0.19
-0.17
-0.15
-0.13
-0.11
-0.09
-0.08
-0.06
-0.04
-0.02
0.00
0.00
0.00

VCOM_OTP_TIMES[2:0]: Read VCOM OTP programmed times.
VCOM_OTP_TIMES[2:0]
3’b0003b001
3’b010
3’b0113’b100Restrictions

VCOM OTP programmed times
Not programmed
1 time2 times
3 times
4 timesMust enable SETEXTC command

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.214April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.215April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.80 SETOTP: set OTP setting (B7h)
B7 H

SETOTP ( Set OTP related setting)
D7
D6
D5
D4
D3
D2
1
0
1
1
0
1
OTP_KEY[7:0]
OTP_MASK[7:0]
OTP_INDEX[7:0]
LOA
VPP OTP_ OTP_ OTP_PTM[
D_ID
1
↑
1
_EN POR PWE
1:0]
S
1
1
↑
OTP_DOUT[7:0]This command is used to set the OTP control.

DNC NWR NRD D17-8
Command0↑
1
st
1 parameter
1↑1nd
2 parameter
1↑1rd
3 parameter
1
↑
1
th

4 parameterth

5 parameter

D1
1

D0
1

HEX
B7
FF
00
00

VPP_
SEL

OTP_
PRO
G

00
00

Description

OTP_KEY[7:0]: “AAh” OTP register access enable and other registers access disable.
OTP_MASK[7:0]: Bit programming mask. If “1”, means don’t programming this bit.
OTP_INDEX[7:0]: Set index of OTP to be programmed.
LOAD_DIS: When written to “1”, OTP load disable.
VPP_EN: When written to “1”, OTP power OP is enable.
OTP_POR: for OTP read control. When set to from “0” to “1”, OTP data can be read therelated OTP index at OTP_DOUT[7:0].
OTP_PROG : When this bit set to “1”, it will programmed to the setting OTP index from
related register value.
OTP_PWE : Internal use, not open.
OTP_PTM[1:0] : Internal use, not open.
VPP_SEL : When set to ‘1’, VPP input voltage is fed to OTP.
OTP_DOUT[7:0] : OTP read data.

Restrictions

Must enable SETEXTC command

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.216April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.81 SETEXTC: enable extension command (B9h)
B9 H

SETEXTC ( Set extended command set)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
Command
0
↑
1
1
0
1
1
1
0
st
1 parameter
1
↑
1
1
1
1
1
1
1
nd
2 parameter
1
↑
1
1
0
0
0
0
0
rd
3 parameter
1
↑
1
0
1
0
0
0
1
This command is used to set extended command set access enable.
Extend cmd
EnableDescription

Disable(default)

Restrictions

Register
Availability

D1
0
1
1
1

D0
1
1
1
1

HEX
B9
00
00
00

Command description
After command (B9h), must write 3 parameters(FFh,83h,57h) by order
After command(B9h), write 3 parameters (xxh,xxh,xxh)
any value is all right, but can not be (FFh,83h,47h)

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.217April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.82 SETSTBA (C0h)
C0 H
Commandst
1 parameternd
2 parameterrd
3 parameterth
4 parameterth
5 parameterth
6 parameter

SETSTBA ( Set Source Option)
DNC NRD NWR D15~8
0
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1

↑
↑

1
1

D7
1

D6
1

D5
0

-

D4
D3
0
0
N/P_OPON[7:0]
I/PI_OPON[7:0]
STBA[23:16]
STBA[15:8]
STBA[7:0]
GENON[7:0]

D2
0

D1
0

D0
0

HEX
C0
73
50
00
3C
C4
-08

This command is used to set source circuit option
N/P_OPON[7:0]: Specify the Normal mode valid source OP period in 1-line driving period. The
period time value is defined as SYSCLK number in internal clock display mode.
I/PI_OPON[7:0]: Specify the IDLE mode valid source OP period in 1-line driving period. The
period time value is defined as SYSCLK number in internal clock display mode.
Clock cycles=1/internal operation clock frequency(fosc)
N/P_OPON[7:0]/ I/PI_OPON[7:0]
Source Period
8’h00
Setting inhabited
8’h01
1 clock cycle
8’h02
2 clock cycles
.
.
.
.
.
.
8’hFF
255 clock cycles
STBA[16:10]: Source Bias current fine tune setting.
STBA[9:6]: Source Bias current coarse tune setting.
Description

STBA[4:2]: Gamma Bias current setting.
STBA161
1
1
1

STBA14
1
0
0
0

STBA9
0
0
1
STBA4
1
1
1

STBA131
1
0
0

STBA12
1
1
1
0

STBA8
0
0
1

STBA7
1
0
0
STBA3
0
0
1

STBA11
1
1
1
1

STBA101
1
1
1Fine tune
Very Large
Large
Middle
Small

STBA6
1
0
0
STBA2
1
0
1

Coarse tune
Small
MiddleLarge
Driving Level
Small
Middle Small
Large

GENON[7:0]: Gamma OP on period control The period time value is defined as SYSCLK
number in internal clock display mode.
Restrictions

SETEXTC turn on to enable this command.

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.218April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In

Register
Availability

StatusPower On Sequence
Default

S/W Reset
H/W Reset

Flow Chart

Availability
Yes
Yes
Yes
Yes
Yes

Default Value
N/P_OPON[7:0]=8’h40, I/PI_OPON[7:0]=8’h38,
STBA[15:0]=16’h0CC4, GENON[7:0]=8’h10,
N/P_OPON[7:0]=8’h40, I/PI_OPON[7:0]=8’h38,
STBA[15:0]=16’h0CC4, GENON[7:0]=8’h10
N/P_OPON[7:0]=OTP value, I/PI_OPON[7:0]=8’hC0,
STBA[11:8]=4’b0000, STBA[7:0]=8’h48,
GENON[7:0]=8’h30-

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.219April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.83 SETDGC: set DGC related setting (C1h)
C1 H
Command

DNC NWR NRD D17-8
0
↑
1
-

st

1

↑

1

-

nd

1
1
1
1
1
1
1
1
1
1
1
1

↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑

1
1
1
1
1
1
1
1
1
1
1
1

-

1 parameter2 parameterrd
3 parameter:th
34 parameterth
35 parameterth
36 parameter:th
67 parameterth
68 parameterth
69 parameter:th
100 parameter

Description

Restrictions

D7
1

SETDGC ( Set DGC)
D6
D5
D4
D3
1
0
0
0

D2
0

D1
0

D0
1

HEX
C1

-

-

-

-

DGC
_EN

00

-

-

-

DGC_LUT_R00[7:0]
DGC_LUT_R01[7:0]:
DGC_LUT_R32[7:0]
DGC_LUT_G00[7:0]
DGC_LUT_G01[7:0]:
DGC_LUT_G32[7:0]
DGC_LUT_B00[7:0]
DGC_LUT_B01[7:0]:
DGC_LUT_B32[7:0]

00
08
:
FC
00
08
:
FC
00
08
:
FC

DGC_EN: Digital gamma correction enable.
‘0’: Disable‘1’: Enable
For more information about these registers, refer to “5.10.2Gray Voltage Generator for
Digital Gamma Correction“ section
Must enable SETEXTC command

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.220April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.84 SETID: set ID (C3h)
C3 H
Commandst
1 parameternd
2 parameterrd
3 parameterth
4 parameter

DNC NWR NRD D17-8
0
↑
1
1
↑
1
1
↑
1
1
↑
1
1
1
↑
-

D7
1

SETID ( Set ID)
D6
D5
D4
1
0
0

D3
0

D2
0

D1
1

D0
1

ID1[7:0]ID2[7:0]ID3[7:0]

-

-

-

-

-

ID_OTP_TIMES[2:0]

HEX
C3
00
80
00
00

This command is used to set ID.
ID_OTP_TIMES[2:0]: Read ID OTP programmed times.
ID_OTP_TIMES[2:0]
3’b000
3’b0013’b010
3’b0113’b100Description

Restrictions

ID OTP programmed times
Not programmed
1 time2 times
3 times
4 timesMust enable SETEXTC command

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.221April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.85 SETDDB: Set DDB (C4h)C4hCommandst
1 parameternd
2 parameterrd
3 parameterth
4 parameter
Description
Restrictions

Register
Availability

SETDDB ( Set DDB)
DNC

NRD

NWR D15-D8

0

1

↑

-

1

1

↑

-

1

1

↑

-

1
1

1
1

↑
↑

-

D7

D6

D5

D4

D3

D2

D1

D0

HEX

1

1

0

0

0

1

0

0

C4

DDB1[7:0]
DDB2[7:0]
DDB3[7:0]
DDB4[7:0]

00
00
00
00

This command is used to set DDB value.
SETEXTC turn on to enable this command.
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.222April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.86 SETCABC: set CABC related setting (C9h)
C9 H
Commandst

1 parameternd

2 parameter

SETCABC( Set CABC Related Setting)
D7
D6
D5
D4
D3
D2
1
1
0
0
1
0
BC_
1
↑
1
PWMDIV[2:0]
1
1
ON
1
↑
1
PWM_PERIOD[7:0]This command is used to set CABC parameter

DNC NWR NRD D17-8
0
↑
1
-

D1
0

D0
1

HEX
C9

INVP
LUS

1

0F
82

BC_ON: The control reigister for LED driver when IC needs enable signal.
‘0’: CABC_ON pin=’L’‘1’: CABC_ON pin=’H’
INVPLUS: The backlight PWM output polarity select.
‘0’, The backlight PWM output is low level active.
‘1’, The backlight PWM output is high level active.
PWMDIV[2:0]: Internal PWM_CLK divider for CABC clock.

0
0
0
0
1
1
1
1

Description

PWMDIV[2:0]
DC_DIV1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Brightness Control Clock
PWM_CLK / 1
PWM_CLK / 2
PWM_CLK / 4
PWM_CLK / 8
PWM_CLK / 16
PWM_CLK / 32
PWM_CLK / 64
PWM_CLK / 128

PWM_PERIOD[7:0]: The backlight PWM output period setting.
Backlight PWM output period = 1 / (PWM_CLK / clock divider (PWMDIV )) x
(256x(PWM_PERIOD[7:0]+1)).
Restrictions

Must enable SETEXTC command

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.223April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.87 SETPanel: set panel characteristic (CCh)CCHCommandst

1 parameter

SETPANEL( Set Panel characteristic register)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0
0
↑
1
1
1
0
0
1
1
0
0
SS_
REV_ BGR
SM_P
GS_P
1
↑
1
PAN
PANE _PA
ANEL
ANEL
EL
L
NEL
This command is used to set Panel characteristic related register

HEX
CC
00

REV_PANEL: The source output data polarity selected.
‘0’: normally white panel.
‘1’: normally black panel.
BGR_PANEL: The color filter order direction selected.
‘0’: S1:S2:S3=’R’:’G’:’B’‘1’: S1:S2:S3=’B’:’G’:’R’
Description

GS_PANEL: The gate driver output shift direction selected.
‘0’: G1G480‘1’: G480G1
SS_PANEL: The source driver output shift direction selected.
‘0’: S1S960‘1’: S960S1
SM_PANEL: Specify the scan order of gate driver. The scan order according to the mounting
method of gate driver output pin.

Restrictions

Register
Availability

Must enable SETEXTC command
StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.224April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.88 SETGamma: set gamma curve (E0h)
E0H
Commandst
1 parameternd
2 parameterrd
3 parameterth
4 parameterth
5 parameterth
6 parameterth
7 parameterth
8 parameterth
9 parameterth
10 parameterth
11 parameterth
12 parameterth
13 parameterth
14 parameterth
15 parameterth
16 parameterth
17 parameterth
18 parameterth
19 parameterth
20 parameterth
21 parameterth
22 parameterth
23 parameterth
24 parameterth
25 parameterth
26 parameterth
27 parameterth
28 parameterth
29 parameterth
30 parameterth
31 parameterth
32 parameterth
33 parameterth

34 parameter

Description

SETGAMMA ( Set Gamma Curve Related Setting )
DNC

NRD

NWR D15-D8

0

1

↑

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑

-

1

1

↑

-

D7

D6

D5

D4

D3

D2

D1

D0

HEX

1
1
CGN1[1:0]

10

0
VRP0[6:0]
VRP1[6:0]
VRP2[6:0]
VRP3[6:0]
VRP4[6:0]
VRP5[6:0]
VRP6[6:0]
VRP7[6:0]
VRP8[6:0]
VRP9[6:0]
VRP10[6:0]
VRP11[6:0]
VRP12[6:0]
VRP13[6:0]
VRP14[6:0]
VRP15[6:0]
VRN0[6:0]
VRN1[6:0]
VRN2[6:0]
VRN3[6:0]
VRN4[6:0]
VRN5[6:0]
VRN6[6:0]
VRN7[6:0]
VRN8[6:0]
VRN9[6:0]
VRN10[6:0]
VRN11[6:0]
VRN12[6:0]
VRN13[6:0]
VRN14[6:0]
VRN15[6:0]
E0

0

0

0

E0
0B
0C
11
1D
25
37
43
4B
4E
47
41
39
35
31
2E
21
1C
1D
1D
26
31
44
4E
56
44
3F
39
33
31
2E
28
1D
E0

CGN0[1:0]00

CGP0[1:0]

GMA_R
ELOAD

00

GMA_RELOAD: Enable this gamma register function.
Positive/Negative
Description
Polarity
VRP0/VRN0
Variable resistor (VR0)for V0 offset adjustment
VRP1/VRN1
Variable resistor (VR1)for V1 offset adjustment
VRP2/VRN2
Variable resistor (VR2)for V2 offset adjustment
VRP3/VRN3
Variable resistor (VR3)for V4 offset adjustment
VRP4/VRN4
Variable resistor (VR4)for V6 offset adjustment
VRP5/VRN5
Variable resistor (VR5)for V13 offset adjustment
VRP6/VRN6
Variable resistor (VR6)for V20 offset adjustment
VRP7/VRN7
Variable resistor (VR7)for V27 offset adjustment
VRP8/VRN8
Variable resistor (VR8)for V36 offset adjustment
VRP9/VRN9
Variable resistor (VR9)for V43 offset adjustment
VRP10/VRN10
Variable resistor (VR10)for V50 offset adjustment
VRP11/VRN11
Variable resistor (VR11)for V57 offset adjustment
VRP12/VRN12
Variable resistor (VR12)for V59 offset adjustment
VRP13/VRN13
Variable resistor (VR13)for V61 offset adjustment

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.225April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00
VRP15/VRN15

Variable resistor (VR15)for V63 offset adjustment

Restriction

SETEXTC turn on to enable this command.

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.226April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.89 SETIMAGE: set image function (E9h)
EAhCommandst

1 parameter

Description

SETMESSI (Set Command type)
DNC

NRD

NWR

D15~D8

D7

D6

D5

D4

D3

D2

D1

D0

HEX

0

1

↑

-

1
PWM
2_EN

1

1

0

1

0

0

1

E9

-

-

DB_EN

00

1

1

↑

-

-

DITH_E
YUV_ENN

DB_EN: Enable 24-bits Data Bus, user can using DB23~DB0 as 24-bits data input.
YUV_EN: Enable YUV function for 24-bits input transform.
DITH_EN: Enable DITH function for 24-bits input transform.
PWM2_EN: Enable CABC_PWM2 as CABC PWM output.

Restrictions

SETEXTC turn on to enable this command.

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.227April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.90 SETMESSI: Set Command type (EAh)
EAhCommandst
1 parameter

SETMESSI (Set Command type)
DNC

NRD

NWR

D15~D8

D7

D6

D5

D4

D3

D2

D1

D0

HEX

0

1

↑

-

1

1

1

0

1

0

1

0

EA

1

1

↑

-

-

-

-

-

-

-

SPI_DC MESSI_
X_SEL
ENB

02

MESSI_ENB: Command selectDescription

SPI_DCX_SEL: DCX select in 4-wrie SPI Interface.
SPI_DCX_SEL
0
1

Restrictions

SETEXTC turn on to enable this command.

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

DCX
th
8 SCL
st

1 SCL
Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.228April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.91 SETCOLOR: set color (EBh)EBhCommandst

1 parameternd
2 parameterrd
3 Parameterth
4 Parameterth
5 Parameterth
6 Parameterth
7 Parameterth
8 Parameterth
9 Parameterth
10 Parameterth
11 Parameterth
12 Parameterth
13 Parameterth
14 Parameterth
15 Parameter

SETCOLOR (Set Color)
DNC

NRD

NWR

D15~D8

D7

D6

D5

D4

D3

D2

D1

D0

HEX

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑

-

1
Bkx1
Bkx9
Bky9
Wx9
Wy9
Rx1
Rx9
Ry9
Gx9
Gy9
Bx1
Bx9
By9
Ax9
Ay9

1
Bkx0
Bkx8
Bky8
Wx8
Wy8
Rx0
Rx8
Ry8
Gx8
Gy8
Bx0
Bx8
By8
Ax8
Ay8

1
Bky1
Bkx7
Bky7
Wx7
Wy7
Ry1
Rx7
Ry7
Gx7
Gy7
By1
Bx7
By7
Ax7
Ay7

0
Bky0
Bkx6
Bky6
Wx6
Wy6
Ry0
Rx6
Ry6
Gx6
Gy6
By0
Bx6
By6
Ax6
Ay6

1
Wx1
Bkx5
Bky5
Wx5
Wy5
Gx1
Rx5
Ry5
Gx5
Gy5
Ax1
Bx5
By5
Ax5
Ay5

0
Wx0
Bkx4
Bky4
Wx4
Wy4
Gx0
Rx4
Ry4
Gx4
Gy4
Ax0
Bx4
By4
Ax4
Ay4

1
Wy1
Bkx3
Bky3
Wx3
Wy3
Gy1
Rx3
Ry3
Gx3
Gy3
Ay1
Bx3
By3
Ax3
Ay3

1
Wy0
Bkx2
Bky2
Wx2
Wy2
Gy0
Rx2
Ry2
Gx2
Gy2
Ay0
Bx2
By2
Ax2
Ay2

EB
-

Bkx[9:0]:
Set the Bkx bits of black color characteristics.
Bky[9:0]:
Set the Bky bits of black color characteristics.
Wx[9:0]:
Set the Wx bits of white color characteristics.
Wy[9:0]:
Set the Wy bits of white color characteristics.
Rx[9:0]:
Set the Rx bits of red color characteristics.
Ry[9:0]:
Set the Ry bits of red color characteristics.
Description

Gx[9:0]:
Set the Gx bits of green color characteristics.
Gy[9:0]:
Set the Gy bits of green color characteristics.
Bx[9:0]:
Set the Bx bits of blue color characteristics.
By[9:0]:
Set the By bits of blue color characteristics.
Ax[9:0]:
Set the Ax bits of A color characteristics.
Ay[9:0]:
Set the Ay bits of A color characteristics.

Restrictions

SETEXTC turn on to enable this command.

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.229April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

Register
Availability

StatusNormal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.230April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.92 SETREADINDEX: set SPI read index (FEh)FEhCommand
1 parameter
Description
Restrictions
stRegister
Availability

SET SPI READ INDEX (Set SPI READ Command Address)
DNC

NRD

0

1

NWR D15-D8
↑

-

D7

D6

D5

D4

D3

D2

D1

D0

HEX

1

1

1

1

1

1

1

0

FE

CMD_ADD[7:0]
SET SPI READ Command Address for User Define Command.
SETEXTC turn on to enable this command
1

1

↑

-

StatusIdle Mode Off, Sleep Out
Idle Mode On, Sleep Out
Sleep In or Booster Off-

Availability
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.231April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.93 GETSPIREAD: SPI Read Command Data (FFh)FFhCommand
1 parameter:thn parameter
Description
Restrictions
stRegister
Availability

GETSPIREAD (Read Command Data)
DNC

NRD

NWR D15-D8

0

1

↑

-

D7

D6

D5

D4

D3

D2

D1

D0

HEX

1

1

1

1

1

1

1

1

1

↑

1

-

FF

1

↑

1

-

:

-

1

↑

1

-

CMD_DATAn[7:0]-

CMD_DATA1[7:0]-

Read SPI Command Data for User Define Command.
SETEXTC turn on to enable this command.
StatusIdle Mode Off, Sleep Out
Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.232April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

6.2.94 GETICID: IC ID Read Command Data (D0h)
D0hCommand
1 parameternd
2 parameter
Description
Restrictions
stRegister
Availability

GETSPIREAD (Read Command Data)
DNC

NRD

NWR D15-D8

0

1

↑

-

D7

D6

D5

D4

D3

D2

D1

D0

HEX

1

1

0

1

0

0

0

0

1

↑

1

-

DUMMY

D0
-

1

↑

1

-

HIMAX_ID

99

Read HX8357-D ID=99h.
SETEXTC turn on to enable this command.
StatusIdle Mode Off, Sleep Out
Idle Mode On, Sleep Out
Sleep In or Booster Off

Availability
Yes
Yes
Yes

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.233April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

7. Layout Recommendation
TBD
Figure 7.1: Layout recommendation of HX8357-D00/D01

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.234April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

7.1Maximum layout resistance
Name
IOVCC
VCI
HSI_VCCVSSA
HSI_VSS
VSSD
OSC
IM[2:0]
RDX, WRX_SCL, DCX, CSX, DIN_SDA
RESXTE, CABC_PWM, CABC_ON,DOUT
DB[23:0]
HSI_DN,HSI_DP,HSI_CN,HSI_CP
PCLK, DE, VSYNC, HSYNC
VGH
VGL
HSI_LDOVCOMDCVSN
VSP
VDDD
VSPROUT,VSNROUT, NVDDDOUT
C13A, C13B, C14A, C14B
C11A, C11B ,C12A, C12B
TEST[3:1]
DUMMY_VCL
VCOM
C22B, C22A

Type
Power supply
Power supply
Power supply
Power supply
Power supply
Power supply
Input
Input
Input
Input
Output
I/O
I/O
Input
OutputOutputCapacitor
connection
OutputCapacitor
connection
Capacitor
connection
Capacitor
connection
OutputCapacitor
connection
Capacitor
connection
Input
Dummy
Panel
connection
Capacitor
connection

Maximum Series
Resistance
5
5
10
5
10
5
100
100
100
100
100
100
10
100
10
10

Unit
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω

20

Ω

10

Ω

5

Ω

5

Ω

5

Ω

50

Ω

5

Ω

5

Ω

100

Ω

100

Ω

5

Ω

5

Ω

DUMMY

Dummy

100

Ω

VTEST, NVTEST

Test Pin

100Ω

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.235April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

7.2External components connection
Capacitor
C1 (C13A/B)
C2 (C11A/B)
C3 (VSP)
C4 (C14A/B)
C5 (C12A/B)
C6 (VSN)
C7 (C22A/B)
C8 (VGH)
C9(VDDD)
C10(HSI_LDO)

Recommended voltage
10V
10V
10V
10V
10V
10V
16V
25V
6V
6V

D1 (VGL-VSSA)

Schottky Diode

Capacity
1 µF (B characteristics)
1 µF (B characteristics)
1 µF ~ 2.2uF (B characteristics)
1 µF (B characteristics)
1 µF (B characteristics)
1 µF~2.2uF (B characteristics)
1 µF (B characteristics)
1 µF (B characteristics)
1 µF (B characteristics)
1 µF (B characteristics)
VF < 0.4V / 20mA at 25°C, VR ≥30V
(Recommended diode: RB521S-30)

Note: If not use High speed interface (DSI), the capacitor of HSI_LDO can be removed.

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8. Electrical Characteristic
8.1Absolute maximum ratings
Item
Power Supply Voltage 1
Power Supply Voltage 2Power Supply Voltage 3Power Supply Voltage 4Power Supply Voltage 5Power Supply Voltage 6
Logic Input Voltage
Logic Output Voltage
Operating Temperature
Storage Temperature

SymbolUnit

IOVCC~VSSD
VCI ~ VSSA
VSP ~ VSSAVSSA ~ VSN
VGH ~ VSSAVSSA ~ VGL
VIN
Vo
Topr
Tstg

V
V
V
V
V
V
V
V
℃
℃

Min.
-0.3
-0.3
-0.3
-0.3
-0.3
-16.5
-0.3
-0.3
-40
-55

Spec.
Typ.
Max.
+4.6
+4.6
+6.6
+6.6
+18.5
0
IOVCC+0.5
IOVCC+0.5
+85
+110

Note
(1),(2)

Note
(3)
Note
(4)
Note
(5)
Note
(6)
Note
(7)
Note
(8),(9)Note(8),(9)Note

Note: (1) IOVCC, VSSD must be maintained.
(2) To make sure IOVCC ≥ VSSD.
(3) To make sure VCI ≥ VSSA.
(4) To make sure VSP ≥ VSSA.
(5) To make sure VSSA ≥ VSN.
(6) To make sure VGH ≥ VSSA.
(7) To make sure VSSA ≥ VGL
VGH +|VGL| < 32V(8) For die and wafer products, specified up to +85℃.
(9) This temperature specifications apply to the TCP package.

Table 8.1: Absolute maximum ratings

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8.2DC characteristics
Parameter

SymbolPower & Operating Voltages
IO Operating voltage
IOVCC
Driver Operating voltage
VCI
VSPROUTVSPROUT
Source Drive Voltage
VSNROUTVSNROUT

Gate Drive High Voltage

VGH

Min.

Spec.
Typ.

Max.

I/O supply voltage
Operation voltage
Dual Pump
Triple Pump
Dual Pump
Triple Pump
VCI=2.8V
Dual Pump(Typ:BT=001)
IVGH=80uA
IVGH=70uA
IVGH=60uA
IVGH=50uA
IVGH=40uA
VCI=2.8V
Dual Pump(Typ:BT=001)
IVGL=-80uA
IVGL=-70uA
IVGL=-60uA
IVGL=-50uA
IVGL=-40uA

1.65
2.5

1.8
2.8

3.3
3.3

-

-

-

Conditions

Unit

V

Gate Drive Low Voltage

VGL

Drive Supply Voltage
Input / Output
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
Input leakage current|VGH-VGL|

-

-

-

32

VIH
VIL
VOH
VOL
IIL

IOH = -1.0mA
IOL = +1.0mA

0.7IOVCC
VSSD
0.8IOVCC
VSSD

-

IOVCC
0.3IOVCC
IOVCC
0.2IOVCC

V

-

-1

-

1

µA

Oscillator frequency

fOSC

Frame rate at
60hz,default Vs
and Hs setting
Ta=25℃MHz

Dual Pump
IVSP=1mA
Triple Pump
IVSP=1mA
Dual Pump
IVSN=-1mA
Triple Pump
IVSN=-1mA

V

Booster(VCI=2.8V)
VSP boost voltage

VSN boost voltage

VSP

VSN

VCOM Generator(VCI=2.8V)
VCOM amplitude
VCOM
Source Driver(Typ:Ta=25℃ VCI=2.8v)
Output voltage deviation(mean value)

DVOS

No load,VSSD+1.0 ~VSPROUT-1.0
VSSD+0.1V ~VSSD+1.0
VSPROUT-1.0 ~VSPROUT-0.1V

Output voltage range
VOS
Output offset voltage
Voff
Current Consumption(Typ: TA=25℃ IOVCC=VCI=2.8V)
IiovccSleep in(MPU mode)
Ivci

-2.5

-

0

V

-

+/- 10+/- 20mV-+/- 30+/- 50mV

0.1-

VSP-0.1

+/-30

+/-50

V
mV

-

TBD
TBD

µA
µA

-

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8.3 AC characteristics
8.4 DBI Type B interface characteristic

Figure 8.1: DBI Type B interface characteristics(VSSA=0V, VDD1=1.8V, VDD3=2.8V, TA=25°C)
SignalSymbolParameter
Min.
Max.
Unit
DescriptiontAST
Address setup time
0
DCX
ns
tAHT
Address hold time (Write/Read)
10tCS
Chip select setup time (Write)
10tRCS
Chip select setup time (Read register)
45
CSX
ns
tRCSFM
Chip select setup time (GRAM)
355
tCSF
Chip select wait time (Write/Read)
10
tWC
Write cycle (write register)
50
tWC
Write cycle (write GRAM@SLPOUT)47
WRX_SCL
ns
tWC
Write cycle (write GRAM@SLPIN)
100tWRH
Control pulse “H” duration
15tWRL
Control pulse “L” duration
15
tRC
Read cycle (read register)
160
tRC
Read cycle (GRAM)
450
RDX
tRDH
Control pulse “H” duration
90
ns
tRDL
Control pulse “L” duration(read register)
35
tRDL
Control pulse “L” duration(GRAM)
345
tDST
Data setup time10
tDHT
Data hold time10
For maximum CL=30pF
DB[23:0]ns
tRAT
Read access time(read register)40
For minimum CL=8pF
tRAT
Read access time(GRAM)
340
tODH
Output disable time
20
80
Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals.

Table 8.2: DBI Type B interface characteristics

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8.4.1 DBI Type C interface characteristics

Figure 8.2: DBI Type C interface characteristics(VSSA=0V, IOVCC=1.8V, VCI=2.8V, TA = 25°C)
SignalSymbolParameter
Min.
Max.
Unit
tCSS
Chip select setup time (Write)
15
Chip select setup time (Read)
60
tCSS
CSX
ns
tCSH
Chip select hold time (Write)
15
tCSH
Chip select hold time (Read)
65
tAST
Address setup time0
DCX
ns
Address hold time (Write/Read)
10
tAHT
tWC
Write cycle
66
WRX_SCL
Control pulse “H” duration
15
ns
tWRH
(Write)tWRLControl pulse “L” duration
15
tRC
Read cycle
150
WRX_SCL
Control pulse “H” duration
60
ns
tRDH
(Read)tRDL
Control pulse “L” duration
60
SDA
tDS
Data setup time
10ns
(Input)tDH
Data hold time
10
SDA
tACC
Read access time
1050
ns
(Output)
tOH
Output disable time
15
50
Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of IOVCC for Input signals.

Description---

For maximum CL=30pF
For minimum CL=8pF

Table 8.3: DBI Type C interface characteristics

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8.4.2 DPI interface characteristics
TVSST

VIH

VS

HS

TVSHT

VIL

THSST

Thv

TPCLKCYCDOTCLKTHSHT

TPCLKHTTPCLKLT

VIH
VIL

TDST/TDEST

DB[B:0]DE

Item
Pixel low pulse width
Pixel high pulse width
Vertical Sync. set-up time
Vertical Sync. hold time
Horizontal Sync. set-up time
Horizontal Sync. hold time
Data Enable set-up time
Data Enable hold time
Data set-up time
Data hold time
Phase difference of sync signal
falling edge

TDHT/TDEHT

VIH
VIL

(VSSA=0V, IOVCC=1.65V to 3.3V, VCI=2.3V to 3.3V,TA = -30 to 70°C)
Spec.
SymbolCondition
Unit
Min.
Typ.
Max.
TCLKLT
15
ns
TCLKHT
15
ns
TVSST
15
ns
TVSHT
15
ns
THSST
15
ns
THSHT
15
ns
TDEST
15
ns
TDEHT
15
ns
TDST
15
ns
TDHT
15
ns
Thv

0

-

320

DotclkNote: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.

Table 8.4: DPI interface characteristics-1

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Figure 8.3: General timings for RGB I/F-2

Item

SymbolCondition

Vertical Timing
Vertical cycle period
Vertical low pulse width
Vertical front porch
Vertical back porch
Vertical blanking period

TVP
TVS
TVFP
TVBP
TVBL

TVBP + TVFP

Vertical active area

TVDISP

-

Min.
486
2
2
2
6
-

Specification
Typ.
480

Max.
70

Unit
HS
HS
HS
HS
HS
HS
HS
HS
Hz

Vertical refresh rate
TVRR
Frame rate
50
60
Horizontal Timing
Horizontal cycle period
THP
326
DOTCLK
Horizontal low pulse width
THS
2
DOTCLK
Horizontal front porch
THFP
2
DOTCLK
Horizontal back porch
THBP
2
DOTCLK
Horizontal blanking period
THBL
THBP + THFP6
DOTCLK
320
Horizontal active area
THDISPDOTCLK
Pixel clock cycle
fCLKCYC
9MHz
TVRR=60Hz
Note: (1) IOVCC=1.65 to 3.3V, VCI=2.3 to 3.3V, VSSA=VSSD=0V, Ta=-30 to 70℃ (to +85℃ no damage)(2) Data lines can be set to “High” or “Low” during blanking time – Don’t care.
(3) HP is multiples of PCLK.

Table 8.5: DPI interface characteristics-2

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8.4.3 Reset input timing
Shorter than 5µs

tRESW

NRESET
tREST

Internal Status

Normal Operation

Initial Condition(Default for H/W reset)

ResettingFigure 8.4: Reset input timing
SymbolParametertRESW

Reset low pulse width

tREST

Reset complete time

(1)

(2)

RelatedPins
NRESET

Min.
10

Spec.
Typ. Max.
-

-

5

-

-

-

120

-

-

Note
When reset applied
during SLPIN mode
When reset applied
during SLPOUT mode

Unit
µs
ms
ms

Table 8.6: Reset input timing
Note: (1) Spike due to an electrostatic discharge on NRESET line does not cause irregular system reset according to thefollowing table.

NRESET Pulse
Shorter than 5 µs
Longer than 10 µs
Between 5 µs and 10 µs

ActionReset Rejected
Reset
Reset Start(2) During the resetting period, the display will be blanked (The display is entering blanking sequence, which
Maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep
In –mode) and then return to Default condition for H/W reset.
(3) During Reset Complete Time, ID and VCOM value in OTP will be latched to internal register during thisperiod. This loading is done every time when there is H/W reset complete time (tREST) within 5ms after a risingedge of NRESET.
(4) Spike Rejection also applies during a valid reset pulse as shown as below:(5) It is necessary to wait 5msec after releasing NRESET before sending commands. Also Sleep Out commandcannot be sent for 120msec.

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tACC, tOH measurement condition
Measurement condition set-up
Oscilloscope
See “NOTE”

Data Generator

Connector

LCD Panel

FPC

External components for test condition(pull-down and pull-up cases) which areremoved after test:
Resistor: 3kOhm ± 5%
Capacitor: 8 or 30pF ± 10%

Connector Pin / Measurement Point

See “NOTE”

Note: Capacitances and resistances of the oscilloscope’s probe must be included externals components in thesemeasurements

Figure 8.5: tACC and tOH measurement condition set-up

Minimum value measurement

Figure 8.6: tACC and tOH minimum condition set-up

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Maximum value measurement

Figure 8.7: tACC and tOH maximum value measurement

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8.4.4 DSI D-PHY electrical characteristics
8.4.4.1 The Electrical Characteristics of D-PHY Layer
In general, the DSI - PHY may contain the following electrical functions: High-Speed Receiver(HS-RX), Low Power Transmitter (LP-TX), a Low-Power Receiver (LP-RX), and the
Low-Power Contention Detector (LP-CD). Figure 8.6 shows the complete set of electricalfunctions required for a fully featured PHY transceiver.

Figure 8.8: Electrical functions of a fully D-PHY transceiver

Where, the HS receiver utilize low-voltage swing differential signaling for signal transmission.
The LP transmitter and LP receiver serve as a low power signaling mechanism. The Figure
8.9 shows both the HS and LP signal levels on the left and right sides, respectively.
Because the HS signaling levels are below the LP low-level input threshold, Lane switches
between Low-Power and High-Speed mode during normal operation.

Figure 8.9: Shows both the HS and LP signal levels

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8.4.4.2 Electrical characteristics of low-power transmitter
The Low-Power transmitter shall be a slew-rate controlled push-pull driver. It is used for
driving the Lines in all Low-Power operating modes It is therefore important that the static
power consumption of a LP transmitter be as low as possible. Under tables list DC and AC
characteristic for LP-TX
Parameter
VOL
VOH
ZOLP

Description
Thevenin output low level
Thevenin output high level
Output impedance of LP-TX

Min.
-50
1.1
110

Typ.
1.2
-

Max.
50
1.3
-

Unit
mV
V
Ω

Note
1

Note: Though no maximum value for ZOLP is specified, the LP transmitter output impedance shall ensure the tRLP/tFLP
specification is met.

Table 8.7: LP transmitter DC specifications
ParametertRLP/tFLP

δV/δtSR

CLOAD

Description
15%-85% rise time and fall timeSlew rate @ CLOAD = 0pF
Slew rate @ CLOAD = 5pF
Slew rate @ CLOAD = 20pF
Slew rate @ CLOAD = 70pF
Slew rate @ CLOAD = 0 to 70pF
(Falling Edge Only)
Slew rate @ CLOAD = 0 to 70pF
(Rising Edge Only)
Slew rate @ CLOAD = 0 to 70pF
(Rising Edge Only)
Load capacitance

Min.
30
-

Typ.
-

Max.
25
500
300
250
150

Unit
ns
mV/ns
mV/ns
mV/ns
mV/ns

Note
1
1, 3, 5, 6
1, 3, 5, 6
1, 3, 5, 6
1, 3, 5, 6

30

-

-

mV/ns

1, 2, 3

30

-

-

mV/ns

1, 3, 7

-

-

mV/ns

1, 8, 9

-

70

pF

-

30 – 0.075 *(VO,INST –700)-

Note: (1) CLOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX areassumed to always be <10pF. The distributed line capacitance can be up to 50pF for a transmission line with
2ns delay.
(2) When the output voltage is between 400 mV and 930 mV.
(3) Measured as average across any 50 mV segment of the output signal transition.
(4) This parameter value can be lower than TLPX due to differences in rise vs. fall signal slopes and trip levels andmismatches between Dp and Dn LP transmitters.
(5) This value represents a corner point in a piecewise linear curve.
(6) When the output voltage is in the range specified by VPIN(absmax).
(7) When the output voltage is between 400 mV and 700 mV.
(8) Where VO,INST is the instantaneous output voltage, VDP or VDN, in millivolts.
(9) When the output voltage is between 700 mV and 930 mV.

Table 8.8: LP transmitter AC specifications

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8.4.4.3 Electrical characteristics of receiverThis part will contain two parts which High-Speed Receiver and Low-Power Receiver.
Because their have differential DC and AC characteristic, describe HS-RX first then describe
LP-RX.

8.4.4.4 High-speed receiver
The HS receiver is a differential line receiver. It contains a switch-able parallel input
termination, ZID, between the positive input pin Dp and the negative input pin Dn. Under
Tables list DC and AC characteristic for HS-RX.
Parameter
VIDTH
VIDTL
VILHS
VIHHS
VCMRXDC
ZID

Description
Differential input high threshold
Differential input low threshold
Single-ended input low voltage
Single-ended input high voltage
Common-mode voltage HS receivemode
Differential input impedance

Min.
-70
-40
-

Typ.
-

Max.
70
460

Unit
mV
mV
mV
mV

Note
1
1

70

-

330

mV

1, 2

80

100

125

Ω

-

Note: (1) Excluding possible additional RF interference of 100mV peak sine wave beyond 450MHz.
(2) This table value includes a ground difference of 50mV between the transmitter and the receiver, the staticcommon-mode level tolerance and variations below 450MHz

Table 8.9: HS receiver DC specifications
Parameter∆VCMRX(HF)
CCM

Description
Common mode interference beyond 450
MHz
Common mode termination

Min.
-

Typ.
-

Max.

Unit

Note

100

mVPP

1

-

60

pF

2

Note: (1) ∆VCMRX(HF) is the peak amplitude of a sine wave superimposed on the receiver inputs.
(2) For higher bit rates a 14pF capacitor will be needed to meet the common-mode return loss specification.

Table 8.10: HS receiver AC specifications

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8.4.4.5 Low-Power Receiver
The low power receiver is an un-terminated, single-ended receiver circuit. The LP receiver isused to detect the Low-Power state on each pin. For high robustness, the LP receiver shallfilter out noise pulses and RF interference. It is recommended the implementer optimize the
LP receiver design for low power. The LP receiver shall reject any input glitch when the glitch
is smaller than eSPIKE. The filter shall allow pulses wider than TMIN to propagate throughthe LP receiver. The related diagram shows as Figure 8.10 Input Glitch Rejection of
Low-Power Receivers. Besides, under tables list DC and AC characteristic for LP-RX.

Figure 8.10: Input glitch rejections of low-power receivers
Parameter
VIL
VIH

Description
Min.
Typ.
Logic 0 input threshold
Logic 1 input threshold
880
Table 8.11: LP receiver DC specifications

Max.
550
-

Unit
mV
mV

Note
-

ParametereSPIKE
TMIN
VINT
fINT

Description
Input pulse rejection
Minimum pulse width response
Peak-to-peak interference voltage
Interference frequency

Max.
300
200
-

Unit
V.ps
ns
mV
MHz

Note
1, 2, 3
4
-

Min.
20
450

Typ.
-

Note: (1) Time-voltage integration of a spike above VIL when being in LP-0 state or below VIH when being in LP-1 state.
(2) An impulse less than this will not change the receiver state.
(3) In addition to the required glitch rejection, implementers shall ensure rejection of known RF-interferers.
(4) An input pulse greater than this shall toggle the output.

Table 8.12: LP receiver AC specifications

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8.4.4.6 Line contention detection
Contention can be inferred from any of the following conditions:
1. An LP high fault shall be detected when the LP transmitter is driving high and the pin
voltage is less than VIL.
2. An LP low fault shall be detected when the LP transmitter is driving low and the pad pin
voltage is greater than VILF.
Parameter
VIHCD
VILCD

Description
Min.
Typ.
Max.
Logic 1 contention threshold
450
Logic 0 contention threshold
200
Table 8.13: Contention detector DC specifications

Unit
mV
mV

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8.4.4.7

High-speed data-clock timingThis section specifies the required timings on the high-speed signaling interface independentof the electrical characteristics of the signal. The PHY is a source synchronous interface in
the Forward direction. In either the Forward or Reverse signaling modes there shall be only
one clock source. In the Reverse direction, Clock is sent in the Forward direction and one offour possible edges is used to launch the data.
The Master side of the Link shall send a differential clock signal to the Slave side to be used
for data sampling. This signal shall be a DDR (half-rate) clock and shall have one transition
per data bit time. All timing relationships required for correct data sampling are defined
relative to the clock transitions. Therefore, implementations may use frequency spreading
modulation on the clock to reduce EMI.
The DDR clock signal shall maintain a quadrature phase relationship to the data signal. Data
shall be sampled on both the rising and falling edges of the Clock signal. The term “risingedge” means “rising edge of the differential signal, i.e. CLKP – CLKN, and similarly for “fallingedge”. Therefore, the period of the Clock signal shall be the sum of two successive
instantaneous data bit times. This relationship is shown in Figure 8.9.

Figure 8.11: DDR clock definition

The same clock source is used to generate the DDR Clock and launch the serial data. Since
the Clock and Data signals propagate together over a channel of specified skew, the Clockmay be used directly to sample the Data lines in the receiver. Such a system canaccommodate large instantaneous variations in UI.
The allowed instantaneous UI variation can cause large, instantaneous data rate variations.
Therefore, devices shall either accommodate these instantaneous variations with appropriate
FIFO logic outside of the PHY or provide an accurate clock source to the Lane Module toeliminate these instantaneous variations.
The UIINST specifications for the Clock signal are summarized in Table 8.14.
Parameter
UI instantaneous

SymbolUIINST

Min.
-

Typ.
-

Max.
12.5

Unit
ns

Note
1, 2

Note: (1) This value corresponds to a minimum 80 Mbps data rate.
(2) The minimum UI shall not be violated for any single bit period, i.e., any DDR half cycle within a data burst.

Table 8.14: Reverse HS data transmission timing parameters

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The timing relationship of the DDR Clock differential signal to the Data differential signal isshown in Figure 8.12. Data is launched in a quadrature relationship to the clock such that the
Clock signal edge may be used directly by the receiver to sample the received data.
The transmitter shall ensure that a rising edge of the DDR clock is sent during the first
payload bit of a transmission burst such that the first payload bit can be sampled by thereceiver on the rising clock edge, the second bit can be sampled on the falling edge, and all
following bits can be sampled on alternating rising and falling edges.
All timing values are measured with respect to the actual observed crossing of the Clockdifferential signal. The effects due to variations in this level are included in the clock to datatiming budget.
Receiver input offset and threshold effects shall be accounted as part of the receiver setup
and hold parameters.

Figure 8.12: Data to clock timing definitions

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HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

8.4.4.8 Data-Clock Timing Specifications
The Data-Clock timing specifications are shown in Table 8.16. Implementers shall specify avalue UIINST,MIN that represents the minimum instantaneous UI possible within a
High-Speed data transfer for a given implementation. Parameters in Table 8.16 are specified
as a part of this value. The skew specification, TSKEW[TX], is the allowed deviation of thedata launch time to the ideal ½UIINST displaced quadrature clock edge. The setup and holdtimes, TSETUP[RX] and THOLD[RX], respectively, describe the timing relationships between
the data and clock signals. TSETUP[RX] is the minimum time that data shall be present
before a rising or falling clock edge and THOLD[RX] is the minimum time that data shallremain in its current state after a rising or falling clock edge. The timing budget specifications
for a receiver shall represent the minimum variations observable at the receiver for which thereceiver will operate at the maximum specified acceptable bit error rate.
The intent in the timing budget is to leave 0.4*UIINST, i.e. ±0.2*UIINST for degradation
contributed by the interconnect.
Parameter
Data to Clock Setup Time
[receiver]
Clock to Data Hold Time
[receiver]

Symbol

Min.

Typ.

Max.

Unit

Note

TSETUP[RX]

0.15

-

-

UIINST

1

THOLD[RX]

0.15

-

-

UIINST

1

Note: (1) Total setup and hold window for receiver of 0.3*UIINST.

Table 8.15: Data to clock timing specifications

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This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.253April, 2012

HX8357-D00/D01
320RGB x 480 dot, 16M color, TFT Mobile Single Chip Driver
Temporary DATA SHEET V00

9. Ordering Information
Part No.
HX8357-D0x0 PDxxx

Package
PD : mean COG
xxx : mean chip thickness (µm), (default: 250 µm)
D000: Without MIPI DSI interface.
D010: With MIPI DSI interface.

10.Revision History
Version00

Date
2012/04/20

Description of Changes
New setup.

Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.254April, 2012