REVISIONSLTR

DESCRIPTIONDATEAPPROVEDA

Add JEDEC references to paragraphs 1.3 and 2.
Add I/O column to figure 2 Terminal connections.
Make correction to Vendor part number as
specified in paragraph 6.3. Update document
paragraphs to current requirements. - ro

21-03-18

J. ESCHMEYER

Prepared in accordance with ASME Y14.24

Vendor item drawing

REVPAGEREVPAGEREV STATUS
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1234567891011

PMIC N/A

PREPARED BY
RICK OFFICER

Original date of drawingYY-MM-DD

CHECKED BYRAJESH PITHADIA

15-10-20

APPROVED BY
CHARLES F. SAFFLESIZE

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
https://www.dla.mil/LandandMaritime
TITLE

CODE IDENT. NO.

A
REV

MICROCIRCUIT, LINEAR, 36 V SINGLE SUPPLYGENERAL PURPOSE OPERATIONALAMPLIFIER, MONOLITHIC SILICONDWG NO.

V62/15605

16236
A

PAGE1OF11DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
AMSC N/A5962-V109-20

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance 36 V single supply general purpose
operational amplifier microcircuit, with an operating temperature range of -55C to +125C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/15605-Drawing
number01

XE

Device type
(See 1.2.1)

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic01

OPA2171-EPCircuit function
36 V single supply general purpose operationalamplifier

1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

Package style

X8MO-187-CA

Plastic small outline

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
AB
CDEFZ

DLA LAND AND MARITIMECOLUMBUS, OHIO

Material
Hot solder dip
Tin-lead plate
Gold platePalladiumGold flash palladium
Tin-lead alloy (BGA/CGA)
OtherSIZEACODE IDENT NO.
16236
REVA

DWG NO.

V62/15605
PAGE2

1.3 Absolute maximum ratings.

1/

Supply voltage range (VS) ........................................................................................................ 20 V minimum
Signal input pins:
Voltage ................................................................................................................................. -VS – 0.5 V to +VS + 0.5 V
Current ................................................................................................................................. -10 mA to + 10 mA
Output short circuit ................................................................................................................... Continuous 2/
Junction temperature range (TJ) .............................................................................................. +150C
Storage temperature range (TSTG) .......................................................................................... -65C to +150C
Electrostatic discharge (ESD):
Human body model (HBM), per JEDEC JS-001 ................................................................... 4000 V 3/
Charged device model (CDM), per JEDEC JESD22-C101 .................................................. 750 V 4/
1.4 Recommended operating conditions. 5/
Supply voltage (VS) .................................................................................................................. 4.5 V (2.25 V) to 36 V (18 V)
Operating temperature range (TA) ........................................................................................... -55C to +125C
1.5 Thermal characteristics. 6/
Thermal metric

SymbolCase X

Unit

Thermal resistance, junction-to-ambient

JA

175.2

C/W

Thermal resistance, junction-to-case (top)JC(TOP)

74.9

C/W

Thermal resistance, junction-to-board

JB

22.2

C/W

Characterization parameter, junction-to-top

JT

1.6

C/W

Characterization parameter, junction-to-board

JB

22.8

C/W

Thermal resistance, junction-to-case (bottom)

JC(BOTTOM)

N/A

C/W

1/

Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.

2/

Short circuit to ground, one amplifier per package.

3/

JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

4/

JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

5/

Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.

6/For more information about traditional and new thermal metrics, see integrated circuit package thermal metrics application
report, SPRA953.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACODE IDENT NO.
16236
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DWG NO.

V62/15605
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3

2. APPLICABLE DOCUMENTSJEDEC Solid State Technology Association
JEDEC JS-001
JEDEC/JESD22-C101
JEDEC PUB 95
JEDEC JEP 155
JEDEC JEP 157–––––

Human Body Model Testing of Integrated Circuits
Qualification Testing for Plastic Encapsulated Solid State Devices
Registered and Standard Outlines for Semiconductor DevicesRecommended ESD Target Levels for HBM/MM Qualification
Recommended ESD-CDM Target Levels(Copies of these documents are available online at https://www.jedec.org.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REVA

DWG NO.

V62/15605PAGE4TABLE I. Electrical performance characteristics. 1/
Test

SymbolConditions 2/

Temperature,TJDevice
typeLimits
MinUnitMax

Offset voltage
Input offset voltage+25CVOS01

1.8mV

0.25 typical2-55C to +125C

0.3 typicalInput offset voltage drift

VOS /
T

Input offset voltage
versus power supply

PSRR

VS = 4 V to 36 V-55C to +125C01

0.3 typical-55C to +125C01

5V /CV/V

1 typical
Channel separation, dcdc+25C01+25C01

5 typical

V/V

Input bias current
Input bias currentIB15pA8 typical-55C to +125C
Input offset current+25CIOS

01-55C to +125C

4nA

4 typicalpA

4nA

Noise
Input voltage noise
Input voltage noisedensityenf = 0.1 Hz to 10 Hz+25C01

3 typical

VPP

f = 100 Hz

+25C

01

25 typicalnV /f = 1 kHz

14 typicalHz

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REVA

DWG NO.

V62/15605
PAGE

5TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/

Temperature,
TJ

DevicetypeLimits

UnitMinMax-VS- 0.1+VS-2

Input voltage
Common mode 3/voltage range

VCM

Common mode
rejection ratio

CMRR

VS = 2 V,-VS – 0.1 V  VCM  +VS – 2 V

01+25C

01

104 typical

VdB87-55C to +125C

120 typical+25C

VS = 18 V,-VS – 0.1 V  VCM  +VS – 2 V+25C

104-55C to +125C

Input impedanceDifferential

4/+25C01

100||3 typicalM||pF

Common mode

4/+25C016||3 typical1012||pF

VS = 4 V to 36 V,+25C01

130 typicaldB

Open loop gain
Open loop voltage gain

AOL-VS + 0.35 V  VO  +VS – 0.35 V

110-55C to +125C

Frequency response
Gain bandwidth
product

GBP

Slew rate

SRSettling time

tS+25C01

3.0 typicalMHz

G = +1+25C01

1.5 typicalV/s

To 0.1%, VS = 18 V, G = +1,10 V step

+25C01

6 typical

s

10 typical

To 0.01% (12 bit), VS = 18 V,
G = +1, 10 V step
Overload recovery time
Total harmonicdistortion + noise

THD +NVIN x Gain  VS+25C

012 typicalsGain = + 1, f = 1 kHz,VO = 3 VRMS

+25C01

0.0002 typical%

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REVA

DWG NO.

V62/15605
PAGE

6

TABLE I. Electrical performance characteristics – Continued. 1/Test

SymbolConditions 2/Temperature,
TJ

DevicetypeLimits
Min

Unit
Max

OutputVoltage output swing
from railVO

RL = 10 k, AOL  110 dB
Short circuit current

ISC

Open loop outputresistance

RO01+25C

VS = 5 V, RL = 10 k

-55C to +125C

f = 1 MHz, IO = 0 A

30 typical-VS+ 0.35+VS– 0.35

mVV+25C

01+25/-35 typicalmA+25C01

150 typical



+25C

01

2.736

V+25C

01

595

APower supply
Specified voltage range

VSQuiescent current peramplifier

IQ

IO = 0 A

475 typical
650-55C to +125C
Temperature
Operating temperature

01-55+125

C

1/Testing and other quality control techniques are used to the extent deemed necessary to assure product performance overthe specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.

2/

Unless otherwise specified, VS = 2.7 V to 3.6 V, VCM = VOUT = VS/2, and RL = 10 k connected to VS/2.

3/

The input range can be extended beyond +VS – 2 V up to +VS. See typical characteristics and application and implementationin the manufacturer’s datasheet for more additional information.

4/The || symbolizes that the input impedance is being represented as the resistance value is in parallel with the capacitance.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
REVA

DWG NO.

V62/15605
PAGE

7

Case XFIGURE 1. Case outline.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236
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8

Case X – continued.

Dimensions
SymbolInchesMillimeters

Min

Max

Min

Max

A.024

.035

0.60

0.90

A1.000.003

0.00

0.10

b.007

.010

0.17

0.25

c.005 NOM

0.13 NOM

D.075

.083

1.90

2.10

E.087.094

2.20

2.40

E1.118.126

3.00

3.20

e.020 BSC

L.008

0.50 BSC
.014

0.20

0.35

NOTES:
1. Controlling dimensions are millimeter, inch dimensions are given for reference only.
2. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed
0.15 mm ( .006 inch ) per side.
3. Falls with JEDEC MO-187 variation CA.

FIGURE 1. Case outline - Continued.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACODE IDENT NO.
16236
REVA

DWG NO.

V62/15605
PAGE9Device type01

Case outline

X

Terminal number

Terminalsymbol

I/O

Description

1

OUTPUT A

OOutput, channel A.

2-INPUT A

I

Inverting input, channel A.

3+INPUT A

I

Noninverting input, channel A.

4-VS---

Negative (lowest) power supply.

5+INPUT B

I

Noninverting input, channel B.

6-INPUT B

I

Inverting input, channel B.

7

OUTPUT B

O

Output, channel B.

8+VS---

Positive (highest) power supply.

FIGURE 2. Terminal connections.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACODE IDENT NO.
16236
REVA

DWG NO.

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PAGE

10

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercialpractices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guaranteeof present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

Vendor item drawing
administrative control
number 1/Devicemanufacturer
CAGE code

Top sidemarking

Vendor part number

V62/15605-01XE

01295

ZGAA

OPA2171MDCUTEP

1/ The vendor item drawing establishes an administrative control number for identifying
the item on the engineering documentation.

CAGE code
01295

DLA LAND AND MARITIMECOLUMBUS, OHIO

Source of supply
Texas Instruments, Incorporated
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZEA

CODE IDENT NO.
16236
REVA

DWG NO.

V62/15605
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