REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVEDA

Update document paragraphs to current requirements. - ro

18-08-09

C. SAFFLEB

Add ANSI SEMI standard G30-88 reference to paragraph 2.0.
Under Table I, add typical limits to VOS, PSRR, IB, IOS, CMRR, AOL, ISD, and IQ
test parameters. Update document to requirements. - ro24-01-10

J. ESCHMEYER

Prepared in accordance with ASME Y14.24

Vendor Item Drawing

Revision Status of Sheets
REVSHEETREV

B

B

B

B

B

B

B

B

B

B

B

SHEET1234567891011

PMIC N/A
Original date ofdrawing
YY-MM-DD
12-07-31

PREPARED BY
RICK OFFICERCHECKED BYRAJESH PITHADIAAPPROVED BY
CHARLES F. SAFFLE
SIZE

AREVAMSC N/A

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

CAGE CODE

16236
B

TITLE

https://www.dla.mil/landandmaritime

MICROCIRCUIT, LINEAR, OPERATIONALAMPLIFIER, LOW POWER, PRECISION,MONOLITHIC SILICONDWG NO.

PAGE

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

V62/12619
1 OF 115962-V147-23

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance low power precision operational amplifier
microcircuit, with an operating temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/12619-Drawing
number01

X

E

Device type
(See 1.2.1)

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic01

OPA211-EP

Circuit function
Low power precision operational amplifier

1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

Package styleX

8MO-187-AA

Plastic small outline

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

MaterialABC
DEF
Z

DLA LAND AND MARITIMECOLUMBUS, OHIO

Hot solder dip
Tin-lead plate
Gold platePalladiumGold flash palladium
Tin-lead alloy (BGA/CGA)
OtherSIZEACAGE CODE
16236

DWG NO.
V62/12619

REV B

PAGE 2

1.3 Absolute maximum ratings.

1/

Supply voltage (VS = +V - -V) .................................................................................................. 40 V
Input voltage (VIN) .................................................................................................................... -V – 0.5 V to +V + 0.5 V
Input current (any pin except power supply pins) ..................................................................... ±10 mA
Output short circuit ................................................................................................................... Continuous 2/
Storage temperature range (TSTG) .......................................................................................... -65°C to +150°C
Junction temperature range (TJ) .............................................................................................. 200°C
Electrostatic discharge (ESD) ratings:
Human body model (HBM) ................................................................................................... 3000 V
Charged device model (CDM) .............................................................................................. 1000 V
1.4 Recommended operating conditions. 3/
Supply voltage .......................................................................................................................... ±2.25 V to ±18 V
Operating free-air temperature range (TA) ............................................................................... -55°C to +125°C
1.5 Thermal characteristics.
Thermal metric

SymbolCase XUnitThermal resistance, junction-to-ambient 4/

θJA

184.9°C/W

Thermal resistance, junction-to-case (top) 5/

θJC(TOP)71.2°C/W

Thermal resistance, junction-to-board 6/

θJB

104.9°C/W

Characterization parameter, junction-to-top 7/

ψJT

11.5°C/W

Characterization parameter, junction-to-board 8/

ψJB

103.4°C/W_______
1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2/ Short circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.
3/ Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
4/ The thermal resistance, junction-to-ambient under natural convection is obtained in a simulation on aJEDEC standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
5/ The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the package top.
No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
6/ The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold platefixture to control the printed circuit board (PCB) temperature, as described in JESD51-8.
7/ Characterization parameter, junction-to-top (ψJT ) estimates the junction temperature of a device in a real system

8/

and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6and 7).
Characterization parameter, junction-to-board (ψJB ) estimates the junction temperature of a device in a real system
and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6and 7).

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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PAGE 32. APPLICABLE DOCUMENTSAMERICAN NATIONAL STANDARDS INSTITUTE, SEMICONDUCTOR EQUIPMENT and MATERIALS INTERNATIONALANSI SEMI STANDARD G30-88– Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic
Packages(Copies of these documents are available from https://www.ansi.org.)JEDEC Solid State Technology Association
EIA/JESD 51-2a
EIA/JEDEC 51-7
EIA/JESD 51-8
JEDEC PUB 95––––Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still Air)High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Integrated Circuits Thermal Test Method Environment Conditions – Junction-to-Board
Registered and Standard Outlines for Semiconductor Devices(Copies of these documents are available online at https://www.jedec.org.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.

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PAGE 4TABLE I. Electrical performance characteristics. 1/TestSymbolConditions 2/
VS = ±2.25 V to ±18 V

Temperature,
TADevicetype

unless otherwise specifiedLimits
MinUnitMax

Offset voltage section.
Input offset voltage

VOS+25°C

VS = ±15 V

01±100µV±20 typical-55°C to +125°C
Input offset voltage drift∆VOS /∆T

Input offset voltage
versus power supply

PSRR

VS = ±2.25 V to ±18 V±180-55°C to +125°C

01+25°C01

0.35

typicalµV/°C

0.5µV/V

0.1 typical
3-55°C to +125°C
Input bias current section.
Input bias current

IB-55°C to +125°C

VCM = 0 V

01±200nA±50 typical
Offset current

IOS-55°C to +125°C

VCM = 0 V

01±150nA±20 typical
Noise section.
Input voltage noiseenf = 0.1 Hz to 10 Hz+25°C

01

80 typicalnVPP

Input voltage noisedensityenf = 10 Hz+25°C

01

2 typical

nV /Input current noisedensityIn

f = 100 Hz

1.4 typicalf = 1 kHz

1.1 typicalf = 10 Hz+25°C01f = 1 kHz

3.2 typical
1.7 typical

HznV /HzInput voltage range.
Common mode
voltage range

VCM+25°C

VS ≥ ±5 V
VS < ±5 V01(-V)+ 1.8(+V)– 1.4(-V)+2(+V)– 1.4

See footnotes at end of table.

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PAGE 5V

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/
VS = ±2.25 V to ±18 V

Temperature,TADevicetypeunless otherwise specifiedLimits
MinUnitMaxInput voltage range - continued.
Common mode
rejection ratio

CMRR-55°C to +125°C

VS ≥ ±5 V,

01114dB

120 typical(-V) + 2 V ≤ VCM (+V) -2 V108

VS < ±5 V,

120(-V) + 2 V ≤ VCM (+V) -2 V

typicalInput impedance.
Differential

3/+25°C

01

20k || 8 typicalΩ||pF

Common mode

3/+25°C

01

109 || 2 typicalΩ||pF-55°C to +125°C

01114

dB

Open loop gain.
Open loop voltage gain

AOL(-V) + 0.2 V ≤ VO ≤ (+V) – 0.2 V,

130 typical

RL = 10 kΩ(-V) + 0.6 V ≤ VO ≤ (+V) – 0.6 V,

110+25°C

114 typical

RL = 600 ΩOpen loop gain overtemperature

AOL(-V) + 0.6 V ≤ VO ≤ (+V) – 0.6 V,-55°C to +125°C

01

110dB

IO ≤ 15 mA
103(-V) + 0.6 V ≤ VO ≤ (+V) – 0.6 V,
15 mA < IO < 30 mA
Frequency response.
Gain bandwidth
product

GBWSlew rate

SRSettling time, 0.01%

tS

G = 100+25°C

01

G=180 typicalMHz

45 typical+25°C

01

27 typicalV/µs+25°C

01

400 typicalns+25°C

01

700 typicalns

G = -10+25°C01500 typicalns

G = +1, f = 1 kHz, VO = 3 VRMS,+25°C

010.000015 typical%

VS = ±15 V, G = -1, 10 V step,
CL = 100 pF

Settling time,0.0015% (16 bit)tS

CL = 100 pF

Overload recovery time
Total harmonic
distortion + noise

VS = ±15 V, G = -1, 10 V step,

THD +N

RL = 600 Ω

See footnotes at end of table.

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PAGE 6

TABLE I. Electrical performance characteristics – Continued. 1/TestSymbolConditions 2/VS = ±2.25 V to ±18 VTemperature,TADevice
typeunless otherwise specifiedLimits

UnitMinMax(-V)+ 0.2(+V)– 0.2Output
Voltage output

VOUT

Short circuit current

ISCOpen loop output
impedance

ZO

01

RL = 10 kΩ, AOL ≥ 114 dB-55°C to +125°C

RL = 600 Ω, AOL ≥ 110 dB+25°C(-V)+ 0.6(+V)– 0.6

IO < 15 mA, AOL ≥ 110 dB-55°C to +125°C(-V)+ 0.6(+V)– 0.6

V+25°C01+30/-45 typicalmA

f = 1 MHz+25°C

01

5 typicalΩDevice disabled (shutdown)

+25°C

01

Shutdown.
Shutdown pin input 4/voltage(+V)– 0.35

Device enabledV(+V)-3

Shutdown pin leakage
current+25°C

01

1 typicalµA

Turn on time

+25°C

01

2 typicalµs

Turn off time

+25°C

01

3 typical

µs

+25°C

01

20

µA

Shutdown current

ISD

Shutdown (disabled)

1 typical
Power supply.
Specified voltage

VS

Quiescent current(per channel)

IQ

IOUT = 0 A

+25°C

01

+25°C

01

±2.25±18V

4.5mA

3.6 typical
6-55°C to +125°C
Temperature range.
Operating rangeTAThermal resistance

θJA

1/

2/3/4/+25°C

01-55+125°C

01

200 typical°C/W

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance overthe specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
Unless otherwise specified, RL = 10 kΩ connected to midsupply and VCM = VOUT = midsupply.
The || symbolizes that the input impedance is being represented as the resistance value is in parallel with the capacitance.
When disabled, the output assumes a high impedance state.

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Case XFIGURE 1. Case outline.

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PAGE 8Case X – continued.

SymbolDimensions
InchesMillimeters

MinMaxMinMax

A---0.043---1.10A10.001

0.006

0.05

0.15

b0.010

0.014

0.25

0.38

c0.005

0.009

0.13

0.23

D

0.114

0.122

2.90

3.10

E

0.114

0.122

2.90

3.10

E1

0.187

0.199

4.75

5.05

eL

0.026

BSC

0.015

0.027

0.65

BSC

0.40

0.70

NOTES:
1. Controlling dimensions are millimeter, inch dimensions are given for reference only.
2. For dimension D, body length does not include mold flash, protrusion, or gate burrs.
Mold flash, protrusion, or gate burrs shall not exceed 0.15 mm (0.006 inch) per end.
3. For dimension E, body width does not include interlead flash. Interlead flash shall not exceed
0.50 mm (0.019 inch) per side.
4. Falls with JEDEC MO-187-AA, except interlead flash.

FIGURE 1. Case outline - Continued.

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PAGE 9NOTES:

Device type

01

Case outline

X

Terminal number

Terminal
symbol1

NC
SEE NOTE 12-INPUT

3+INPUT

4-V

5NC
SEE NOTE 16

OUTPUT

7+V

8

SHUTDOWN
SEE NOTE 2

1. NC denotes no internal connection.
2. Shutdown function:
Device enabled: (-V) ≤ VSHUTDOWN ≤ (+V) – 3 V
Device disabled: VSHUTDOWN ≥ (+V) – 0.35 V

FIGURE 2. Terminal connections.

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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

Vendor item drawing
administrative control
number 1/ 2/Device
manufacturer
CAGE code

Top sidemarking

Vendor part number

V62/12619-01XE

01295

OBCM

OPA211MDGKTEP

1/ The vendor item drawing establishes an administrative control number for identifying theitem on the engineering documentation.
2/ For the most current package and ordering information, see the package option addendum at theend of the manufacturer’s data sheet.

CAGE code

Source of supply

01295

DLA LAND AND MARITIMECOLUMBUS, OHIO

Texas Instruments, Incorporated
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZEA

CAGE CODE
16236

DWG NO.
V62/12619

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