Silicon Nanoelectronics Workshop 2023 (SNW 2023)
June 11th-12th, 2023
Rihga Royal Hotel Kyoto, Kyoto, Japan
Sunday, June 11th, 2023
8:45

Opening remarks
Katsuhiro Tomioka, Hokkaido Univ.

Session 1: Plenary
Session Chair: Katsuhiro Tomioka, Hokkaido Univ.
8:50
1-01
(Plenary)
CMOS Device Scaling by Nanosheet Channel Architectures and New Channel Materials*Naoto Horiguchi, imec (Belgium)
9:20
1-02
(Plenary)
ALD Nanometer-Thin In2O3 for BEOL Logic, Memory and RF Applications*Peide Ye, Purdue Univ. (USA)
Session 2: Machine Learning
Session Chair: Woo Young Choi, Seoul National University
9:50
2-01
Data Matching Engine for Efficient Big Data Searching Systems Using a RRAM Based Novel
Computing Paradigm*Shiyue Song1,2, Yizhou Zhang1,2, Jin Kang3, Kai Zheng, Weihai Bu3, Lifeng Liu1,2, Xiaoyan Liu1,2, Jinfeng
Kang1,2, Peng Huang1,2 ,1Peking Univ. (China), 2Beijing Advanced Innovation Center for Integrated Circuits(China), 3Semiconductor Technology Innovation Center (Beijing) Corp. (China)
10:10 2-02
A Novel Ferroelectric Tunnel FET-based Time-Domain Content Addressable Memory with HighDistance-Metric Linearity and Energy Efficiency for Edge Machine Learning*Weikai Xu1, Jin Luo1, Qianqian Huang1, Ru Huang1 ,1Peking University (China)
10:30 2-03
Machine Learning-based Accurate Single Wafer Wet Etching Amount Prediction*Shinsei Yoshikiyo1, Hiroshi Horiguchi2, Chihiro Matsui1, Ken Takeuchi1, 1Univ. of Tokyo (Japan), 2
SCREEN Semiconductor Solutions (Japan)
Break (10 min)

Session 3: Neuromorphic Application I
Session Chair: Steve Chung, National Yang Ming Chiao Tung Univ.
11:00 3-01
(Invited talk)Bayesian Nanoelectronics*Damien Querlioz, Université Paris-Saclay (France)
11:30 3-02
Suppressed Relaxation Effect in TPT-RAM and Dual-mode Neural Network Application*Xing Mou1, Xiangpeng Liang1, Yingjie Lyu2, Jianshi Tang1, Bin Gao1, Pu Yu2, He Qian1, Huaqiang Wu1,
1
School of Integrated Circuits, Tsinghua University (China), 2State Key Laboratory of Low Dimensional
Quantum Physics and Department of Physics, Tsinghua University (China)
11:50 3-03
Synapse Array with Buried Bottom Gate Structure for Neuromorphic Systems*Bosung Jeon1, Taejin Jang1, Seongjae Cho2, Hyungcheol Shin1, Woo Young Choi1, 1Seoul National Univ.
(Korea), 2Ewha Womans Univ. (Korea)
Lunch break (12:10-13:10)
Session 4: Neuromorphic Application II
Session Chair: Kasidit Toprasertpong, the Univ. of Tokyo
13:10 4-01
(Invited talk)
In-Materio Reservoir Devices Made of Random Network of Nanomaterials for Application to Smart
Sensors and Autonomous Robotics*Hirofumi Tanaka, Kyusyu Institute of Tech. (Japan)
13:40 4-02
FDSOI-based 1T Pixel with Long-term Data Retention for in-situ Convolution*Haozhang Yang1, Zheng Zhou1, Guihai Yu1, Ruiqi Chen1, Lixia Han1, Peng Huang1, Xiaoyan Liu1, Jinfeng
Kang1, 1Peking Univ. (China)
14:00 4-03
Artificial Nociceptor Based on Short-Term Memory TFT with Controllable Sensitization Level*Ruiqi Chen1,2, Ruiyi Li1,2, Haozhang Yang1,2, Guihai Yu1,2, Yizhou Zhang1,2, Yiyang Chen1,2, Lianliang
Wu1,2, Junchen Dong3, Dedong Han1,2, Zheng Zhou1,2, Peng Huang1,2, Xiaoyan Liu1,2, Jinfeng Kang1,2,
1School of Integrated Circuits, Peking University (China), 2Beijing Advanced Innovation Center for
Integrated Circuits (China), 3Beijing Information Science & Technology University (China)
Break (10 min)Session 5: Advanced CMOS Technology
Session Chairs: Masaharu Kobayashi, Univ. of Tokyo, Peide Ye, Purdue Univ.
14:30 5-01
High Performance Ge FinFET CMOS Invertor with ION=2.0 mA/μm at VOV =1V, S.S.=64 mV/dec,

ION/IOFF=2.5x106, and Voltage Gain=90 V/V by Using High Pressure Supercritical Fluid Hydroxide
Oxidation*Cheng-Yu Wu1, Dun-Bao Ruan2, Kuei-Shu Chang-Liao1, Yao-Jen Lee3, Yu-Chuan Chiu4, Chih-Wei Liu1,
Guan-Ting Liu1, Bo-Lien Kuo1, Kai-Chun Yang1, Cheng-Han Li1, Po-Tsun Liu4, 1National Tsing Hua
University (Taiwan), 2Fuzhou University (China), 3Taiwan Semiconductor Research Institute (Taiwan),
4
National Yang Ming Chiao Tung University (Taiwan)
14:50 5-02
Enhanced Performance for SiGe/Si Gate-All-Around Field-Effect-Transistor with Ge Condensation
Using Supercritical Fluid Treatment*Wei-Ren Chen1, Dun-Bao Ruan2, Kuei-Shu Chang-Liao1, Hao-Yan Wang1, Guang-Li Luo3, Yu-Chuan
Chiu4, Ting-Kai Kuan1, Po-Tsun Liu4, 1National Tsing Hua University (Taiwan), 2Fuzhou University (China),
3
Taiwan Semiconductor Research Institute (Taiwan), 4National Yang Ming Chiao Tung University (Taiwan)
15:10 5-03
Thermal consideration in nanoscale gate-all-around vertical transistors*Guilhem Larrieu1, Houssem Rezgui2, Abhishek Kumar1, Jonas Müller1, Sylvain Pelloquin1, Yifan Wang2,
Marina Deng2, Aurélie Lecestre1, Cristell Maneux2, Chhandak Mukherjee2, 1LAAS-CNRS (France), 2IMS
laboratory (France)
15:30 5-04
Thermal and Performance Analysis of Back-side Power Delivery Network beyond 3nm Technology
Node*Haoyu Zhang1, Linlin Cai1, Yutao Chen1, Jianwen Lin1, Wangyong Chen1, 1Sun Yat-Sen Univ. (China)
15:50 5-05
Green Laser Crystallized Poly-Si Thin-film Transistor and CMOS Inverter using HfO2-ZrO2
Superlattice Gate Insulator and Microwave Annealing for BEOL Applications*Chih-Hsiang Chang1, Siao-Cheng Yan1, Chong-Jhe Sun1, Ming-Yueh Huang1, Bo-An Chen1, Xin-Chan
Zhong1, Yi-Wen Lin1, Yung-Chun Wu1, 1National Tsing Hua Univ. (Taiwan)
16:10 5-06
Study of Ferroelectric HfO2-ZrO2 Superlattice Poly-Si Junctionless Nanosheet Gate-all-around Fieldeffect-transistor and CMOS Inverter*Xin-Chan Zhong1, Siao-Cheng Yan1, Ming-Yueh Huang1, Chih-Siang Chang1, Chong-Jhe Sun1, Bo-An
Chen1, Yi-Wen Lin1, Yung-Chun Wu1, 1National Tsing Hua University (Taiwan)
Session 6: Poster presentation (poster short presentation 16:40~17:00)
Session Chair: Kuniyuki Kakushima, Tokyo Tech.
17:00-18:30 at Syunjyu IIMonday, June 12th, 2023
Session 7: Si Nanoelectronics & Device Physics
Session Chair: Takahide Oya, Yokohama National Univ.
8:50
7-01
(invited talk)
Silicon Electron Nano-Aspirator - Current enhancement based on electron-electron scattering –*Yukinori Ono, Shizuoka Univ. (Japan)
9:20
7-02
Effects of Quantum Confinement on Charge-Based Threshold Voltage Definition*Kiyoshi Takeuchi1, Masaharu Kobayashi1, Toshiro Hiramoto1, 1Univ. of Tokyo (Japan)
9:40
7-03
An Enhanced AC Conductance Method with Source/Drain Resistance Correction for Self-Heating
Effects of Novel Nano-Scaled Devices*Jyun-Yan Kuo1, Wei Lee1, Ke-Wei Su1, Chung-Kai Lin1, 1Taiwan Semiconductor Manufacturing Company(Taiwan)
10:00 7-04
Drag of Electron-Hole Bilayer in Silicon-on-Insulator at Low Temperature*Ahmed Nabil1, Manjakavahoaka Razanoelina1, Masahiro Hori 1, Akira Fujiwara2, Yukinori Ono1, 1Shizuoka
Univ. (Japan), 2NTT Basic Research Laboratory (Japan)
10:20 7-05
Modification and Ablation of Thin Silicon-on-Insulator Films by fs-Laser*Daniel Moraru1,2, Tsutomu Kaneko1, Daniel Smith2, Tomas Katkus2, Soon Hock Ng2, Saulius Juodkazis2,
1
Shizuoka Univ. (Japan), 2Swinburne Univ. of Tech. (Australia)
Break (10 min)Session 8: Quantum dots
Session Chair: Pei-Wen Li, National Yang Ming Chiao Tung Univ.
10:50 8-01
Integrable Germanium Few-Hole Double Quantum-Dots and Single-Hole Transistors
using CMOS Fabrication Approaches*Chi-Cheng Lai1, I-Hsiang Wang1, Ting Tsai1, Horng-Chih Lin1, Pei-Wen Li1, 1National Yang Ming Chiao
Tung University (Taiwan)
11:10 8-02
Single-Electron Charge Sensor Self-Aligned to a Quantum Dot Array by Double-Gate
Patterning Process for a Large-Scale Silicon Quantum Computer*Takuma Kuno1, Takeru Utsugi1, Ryuta Tsuchiya1, Noriyuki Lee1, Gou Shinkai1, Toshiyuki Mine1, Itaru
Yanagi1, Raisei Mizokuchi2, Jun Yoneda2, Tetsuo Kodera2, Shinichi Saito1, Digh Hisamoto1, Hiroyuki
Mizuno1, 1Hitachi, Ltd. (Japan), 2Tokyo Institute of Technology (Japan)
11:30 8-03
Individual Control of Characteristics of Vertically Stacked Silicon Quantum Dots
*Junoh Kim1, Tomoko Mizutani1, Takuya Saraya1, Hiroshi Oka2, Takahiro Mori2, Masaharu Kobayashi1,3,
Toshiro Hiramoto1, 1IIS, Univ. of Tokyo (Japan), 2AIST (Japan), 3d.lab, Univ. of Tokyo (Japan)
11:50 8-04
Structural and Electrostatic Confinement of a Single Electron in a Scalable 2D Array

of Quantum Dots
*Amina Sadik1, Etienne Nowak1, Louis Hutin1, Pierre-André Mortemousque1, Benoit Bertrand1, 1CEA-Leti,
Univ. of Grenoble Alpes (France)
Lunch break (12:10-13:10)
Session 9: Application of 2D material
Session Chair: Daniel Moraru, Shizuoka, Univ.
13:10 9-01
(invited talk)
Graphene Based NEMS and Electric Field Sensor: From Research to Real-World Applications*Afsal Kareekunnan1, Manoharan Muruganathan1, Ngoc Huynh Van1, Marek E Schmidt1, Takeshi Kudo2,
Takeshi Maruyama2, Hiroshi Mizuta1,3, 1JAIST (Japan), 2Otowa Elec. (Japan), 3Univ. Southampton (UK)
13:40 9-02
Novel MoS2 Dual-Gate FET with a Highly Scaled EOT of ~2.4 nm High-k Gate Dielectric Layer for
Reconfigurable Logic Gate and High-Precision Analog Synapse*Lingqi Li1, Haofei Zheng1, Heng Xiang1, Yu-Chieh Chien1, Kah-Wee Ang1,2, 1Department of Electrical andComputer Eng., National Univ. of Singapore (Singapore), 2Inst. of Materials Res. and Eng., A*STAR(Singapore)
14:00 9-03
Forming-Free Resistive Switching by Lateral Ag Ion Migration on MoS2
*Sofia Cruces1, Lukas Voelkel1, Jimin Lee1, Dennis Braun1, Ardeshir Esteki1, Annika Grundmann2, Holger
Kalisch2, Michael Heuken2,3, Andrei Vescan2, Alwin Daus1, Max Christian Lemme1,4, 1Chair of Electronic
Devices, RWTH Aachen Univ. (Germany), 2Compound Semiconductor Tech., RWTH Aachen Univ.
(Germany), 3AIXTRON SE (Germany), 4AMO GmbH (Germany)
14:20 9-04
Scalability of h-BN Based Memristors: Yield and Variability Considerations
Abdelrahman S. Abdelrahman1, Hesham ElSawy2, Mario Lanza3, Deji Akinwande4, *Feras Al-Dirini1,5,
1Electrical Engineering Department, King Fahd University of Petroleum & Minerals (Saudi Arabia), 2Schoolof Computing, Queen's University (Canada), 3Physical Science and Engineering Division, King Abdullah
University of Science and Technology (Saudi Arabia), 4Microelectronics Research Center, The University ofTexas at Austin (United States of America), 5Center for Advanced Materials, King Fahd University ofPetroleum & Minerals (Saudi Arabia)
Break (10 min)Session 10: Memory Technology
Session Chairs: Minoru Oda, KIOXIA Cooperation
14:50 10-01
A 40-nm Loadless 4T-SRAM TRNG MACRO with Read-just-after-write (RAW) Scheme Featuring
5.3Gb/s and 3.64TOP/W
Y. S. Wu1, K. H. Chang1, P. S. Huang1, M. L. Miu1, S. Y. Huang1, S. M. Lu1, H. S. Su1, *E Ray Hsieh1,1National Central University (Taiwan)

15:10 10-02
Record-High Memory Window and Robust Retention Anti-Fuse OTP Memory: Electrical andReliability Characteristics
Dong Ru Hsieh1, *Jia Chian Ni1, Wei Ju Yeh1, Tzu Chieh Hong1, Zi Yang Hong1, Yan Kui Liang1, Huai En
Luo1, Michael Hsu1, Ta Chun Cho2, Tien Sheng Chao1, 1National Yang Ming Chiao Tung Univ. (Taiwan),
2
Taiwan Semiconductor Res. Inst. (Taiwan)
15:30 10-03
Physical Understanding on the Anti-fuse Instability to Construct a Selector-Type One-TimeProgramming Memory in the High-k Metal-Gate CMOS Generation
C. C. Chuang1, C. W. Chang1, H. W. Chen1, *T. C. Kao1, Y. J. Li1, J. C. Guo1, Steve S Chung1, 1National
Yang Ming Chiao Tung Univ. (Taiwan)
15:50 10-04
Physical mechanisms and Enhancement of Endurance Degradation of SiOx: Ag-based Volatile
Memristors*Ruiyi Li1,2, Haozhang Yang1,2, Yizhou Zhang1,2, Xujin Song1,2, Nan Tang1,2, Ruiqi Chen1,2, Zheng Zhou1,2,
Weihai Bu3, Kai Zheng3, Jin Kang3, Lifeng Liu1,2, Jinfeng Kang1,2, Peng Huang1,2, 1Peking University(China), 2Beijing Advanced Innovation Center for Integrated Circuits (China), 3Semiconductor Technology
Innovation Center (Beijing) Corporation (China)
16:10 10-05
Stand-alone STT-MRAM development on VCT transistor in 0.0045 µm2 unit cell
Jaewoo Kim1, *Qiong Tuo1, Handong Xu1, Yali Tan1, Tingting Gu1, Haiyang Dong1, Xingkun Xue1, Zelun
Li1, Kuoming Huang1, Zhonghan Cao1, Bowen Dong2, Kaifeng Dong3, Huihui Li2, Chao Zhao2, Abraham
Yoo1, 1ChangXin Memory Tech., Inc. (China), 2Superstring Academy of Memory Tech. (China), 3China Univ.
of Geosciences (China)
Break (10 min)Session 11: Ferroelectric devices
Session Chairs: Katsuhiko Nishiguchi, NTT Basic Research laboratories
16:40 11-01 (invited talk)Stacked Gate-All-Around Nanosheet Channel Ferroelectric HfxZr1–xO2 FETs With NH3 Plasma
Treatment Featuring High Footprint Current
Dong-Ru Hsieh, Chia-Chin Lee, *Tien-Sheng Chao, National Yang Ming Chiao Tung University (Taiwan)
17:10 11-02
New Insights into the Memory Window Estimation in FeFET from a Dynamic Perspective*Puyang Cai1, Hao Li1, Chang Su1, Tianxiang Zhu1, Lining Zhang1, Runsheng Wang1, Ru Huang1, 1Peking
University (China)
17:30 11-03
Investigation of HfO2/ZrO2 Superlattice Dielectric and High-k AlON Interfacial Layer on Ferroelectric
FinFET

*Ming-Yueh Huang1, Siao-Cheng Yan1, Xin-Chan Zhong1, Chih-Siang Chang1, Chong-Jhe Sun1, Bo-An
Chen1, Yi-Wen Lin1, Yung-Chun Wu1, 1National Tsing Hua Univ. (Taiwan)
17:50 11-04
Vertically Stacked Ge Diamond-shape Nanowires GAAFET with Ferroelectric HZO*Bo-An Chen1, Yi-Wen Lin1, Hao-Hsiang Chang1, Chih-Hsiang Chang1, Ming-Yueh Huang1, Xin-Chan
Zhong1, Siao-Cheng Yan1, Chong-Jhe Sun1, Fu-Ju Hou2, Yung-Chun Wu1, 1National Tsing Hua Univ.
(Taiwan), 2Taiwan Semiconductor Research Inst. (Taiwan)
18:10

Closing remarks

Kuniyuki Kakushima, Tokyo Tech.

Poster Presentation (June 11th, 17:00-18:30, with poster short presentation 16:40~17:00)
P01
Performance Improvement of Single-Electron Reservoir Computing Circuit with Multiple-TunnelJunction Single Electron Oscillator*Shunya Watanabe1, Takahide Oya1, 1Yokohama National Univ. (Japan)
P02
Single-Electron Information-Processing Circuit Inspired by Principles of Molecular Computing*Kairi Yokoyama1, Takahide Oya1, 1Yokohama National Univ. (Japan)
P03
Logically Synthesized Invertible Logic Based on Many-body Effects with Probabilistic-bit
Implementation*Yihan He1, Chao Fang1, Sheng Luo1, Gengchiau Liang1, 1National Univ. of Singapore (Singapore)
P04
Influence of Weight Transfer Error on Vector-Matrix Multiplication Using AND Array Architectures*Junsu Yu1, Donghyun Ryu1, Taejin Jang1, Woo Young Choi1, 1Seoul National Univ. (Korea)
P05
Experimental Demonstration of Memristor Delay-Based Logic In-Memory Ternary Neural Network
Adrien Renaudineau1, Kamel-Eddine Harabi1, Clément Turck1, Axel Laborieux1, Elisa Vianello2, Marc
Boquet3, Jean-Michel Portal3, *Damien Querlioz1, 1Univ. Paris-Saclay, CNRS, C2N (France), 2CEA-LETI,
Univ. Grenoble-Alpes (France), 3Aix-Marseille Univ., CNRS, IM2NP (France)
P06
A Crossbar-wise IR-drop Compensation Schemes for 5G/6G Hybrid Precoding with Highly-parallel
Analog RRAM Array*Qi Qin1, Qingtian Zhang1, Bin Gao1, Jianshi Tang1, He Qian1, Huaqiang Wu1, 1Tsinghua Univ. (China)
P07
Ultra-Large Memory Window of 3.8V and 75% Read/Write Speed Improvement through Stressed
Alumina and Angstrom-Laminated HfZrO2*Zi-Rong Huang1, Sheng Min Wang1, Cheng Rui Liu1, Yu Ting Chen1, Yu Tzu Cai1, Zheng Kai Chen1, Chia
Shou Pai1, Ying Tsan Tang1, 1National Central Univ. (Taiwan)
P08
Optimization of Ferroelectricity in Al-Doped HfO2 Capacitors: Electrical and Endurance
Characteristics*Dong Ru Hsieh1, Huai En Luo1, Jia Chian Ni1, Zi Yang Hong1, Yi Hsiu Chen1, Wei Ju Yeh1, Tien Sheng
Chao1, 1 National Yang Ming Chiao Tung Univ. (Taiwan)
P09
Improved Switching behaviors of MFM Capacitor with Reduced Ec and Enhanced Pr-V Linearity by
Using La-Al co-doped HfO2 Ferroelectric layer*Xujin Song1, Haolin Li1, Zhuohua Tang1, Peng Huang1, Xiaoyan Liu1, Jinfeng Kang1, 1Peking Univ.
(China)P10
Variability Analysis of Stacked-Nanosheet FeFET for MLC Memory and Synapse Applications*Heng Li Lin1, Pin Su1, 1Univ. of National Yang Ming Chiao Tung (Taiwan)
P11
New Understanding of Memory Window Reduction Induced by Ferroelectric Dynamics for HfO2based 1T1C FeRAM*Zhiyuan Fu1, Mengxuan Yang1, Kaifeng Wang1, Qianqian Huang1,2,3, Ru Huang1,2, 1Peking Univ. (China),
2
Beijing Advanced Innovation Center for Integrated Circuits (China), 3Beijing Superstring Academy ofMemory Tech. (China)
P12(Withdrawn) Impact of Fringing Field on the Memory Window of FeFET*Athira Sunil1, Maximilian Lederer1, Yannick Raffel1, Franz Müller1, Konrad Seidel1, Thomas Kämpfe1,
Sourav De1, 1Fraunhofer Institute for Photonic Microsystems (Germany)
P13
Impact of Si-Based Interfacial Layer for Ferroelectric Memory*Siddheswar Maikap1,2, Asim Senapati1, Zhao-Feng Lou3, Min-Hung Lee3, 1Chang Gung Univ. (Taiwan),
2
Keelung Chang Gung Memorial Hospital (Taiwan), 3National Taiwan Normal Univ. (Taiwan)
P14(Withdrawn) A Comprehensive Understanding for AFeFET with Double Hysteresis Loop Model:
Guidelines for Performance and Reliability*Min Liao1, Junshuai Chai1, Jinjuan Xiang2, Kai Han3, Yanrong Wang4, Hao Xu1, Xiaolei Wang1, Jing
Zhang4, Wenwu Wang1, 1Inst. of Microelectronics Chinese Academy of Sciences (China), 2Beijing
Superstring Academy of Memory Tech. (China), 3Weifang Univ. (China), 4North China Univ. of Tech. (China)
P15
In-Solution Germanium Selenide Nanosheets as Charge Trapping Layer in Flash Memories
Nazek El-Atab1, *Bashayr Ali Alqahtani1, 1Program of Electrical and Computer Engineering, King Abdullah
Univ. of Sci. and Tech. (Saudi Arabia)
P16
Spherical Shallow Trench Isolation with silicon nitride layer in Buried Gate DRAM for reducing passgate disturbance*Yeon-Seok Kim1,2, Chang-Young Lim1,2, Min-Woo Kwon1,2, 1National Univ. of Gangneung-Wonju (Korea),
2
Lab. of ISDL (Korea)
P17
A Physics-based Numerical Model of Resistive Switching Behavior in Electrochemical Metallization
Memristor*Yeongkwon Kim1, Byung Chul Jang1, 1Kyungpook Nat'l Univ. (Korea)
P18
A High-Speed and Self-calibratable True Random Number Generator (TRNG) based on Unified
Selector-RRAM*Yabo Qin1, Zongwei Wang1,2, Jiajun Gao1, Linbo Shan1, Qishen Wang1, Yimao Cai1,2, Ru Huang1,2, 1Peking

Univ. (China), 2Beijing Adv. Innovation Center for IC (China)
P19
Generative Network Utilizing Random Number Based on Memristor Array for Medical Image
Synthesis*Namju Kim1, Byung Chul Jang1, 1Kyungpook Nat. Univ. (Korea)
P20
Design of New Single-Electron Reaction-Diffusion Circuit with Ability to Generate and Control Plane
Waves*Keiichiro Tamura1, Yuito Nakamori1, Takahide Oya1, 1Yokohama National Univ. (Japan)
P21
Theoretical Study of High Performance Germanium Nanowire Quantum Dot*Han-Wei Yang1, Yung-Feng Wu1, Ming-Jung Hsu1, Shao-Chen Lee1, Ying-Tsan Tang1, 1National Central
University (Taiwan)
P22
Enhanced Electrical Performance of Ge nMOSFET with Rapid Remote Plasma Oxidation Treatment*Jia-Cheng Liu1, Dun-Bao Ruan2, Kuei-Shu Chang-Liao1, Guan-Ting Liu1, 1National Tsing Hua University(Taiwan), 2Fuzhou University (China)
P23
Improved Radiation Hardness for Nanosheet FETs with Partial Bottom Dielectric Isolation*Xun-Ting Zheng1, Vita Pi-Ho Hu1, 1National Taiwan University (Taiwan)
P24
Phosphorus Deactivation and Electron Mobility Enhancement in Ultrathin Silicon Nanosheets*Michele Perego1, Andrea Pulici1,2, Stefano Kuschlan1,3, Gabriele Seguini1, Fabiana Taglietti2, Marco
Fanciulli1,2, Riccardo Chiarcos3, Michele Laus3, 1CNR-IMM Unit of Agrate (Italy), 2Università degli Studi diMilano-Bicocca (Italy), 3Università del Piemonte Orientale ‘‘A. Avogadro’’ (Italy)
P25
Performance Investigation of Source/Drain Extension Region on Nanosheet FET: A Digital Design
Perspective*Shobhit Srivastava1, Sourabh Panwar1, Shashidhara M.1, Navjeet Bagga2, Deepak Joshi1, Abhishek
Acharya1, 1Sardar Vallabhbhai National Institute of Technology, Surat, Gujarat (India), 2IIT Bhubaneswar,
Odisha (India)
P26
Comprehensive Investigation of Back Gate Biasing on Performance of Line TFETs*Sourabh Panwar1, Shobhit Srivastava1, Shashidhara M1, Prabhat Dubey2, Deepak Joshi1, Abhishek
Acharya1, 1Sardar Vallabhbhai National Institute of Technology, SVNIT (India), 2Univ. of Pisa (Italy)
P27
Atomically Thin 0.65nm and 6nm Vertical Side-Wall MoS2 Channel Transistors*Kihan Kim1, Byung Chul Jang1, 1Kyungpook National Univ. (Korea)