Clock and Data Recovery for Serial
Digital Communication(plus a tutorial on bang-bang Phase-Locked-Loops )Rick Walker
Hewlett-Packard Company
Palo Alto, California

walker@opus.hpl.hp.com

Agenda• Overview of serial data communications• Degradation mechanisms, data coding• Clock recovery methods and components• Jitter measurements• Break• BB PLL Theory• Simulation techniques• 1st, 2nd order loops• Key design parameters
2Diversity of CDR applications• Clock and Data Recovery (CDR) applications span therange from ultra-high-volume, low cost datacom
applications to very high precision, long-haul telecom
applications• Many different trade-offs tailor each circuit to the target
application area

1.25Gb/s Gigabit
Ethernet Transceiver<$6 in volume(datacom application)

1cm

2.488Gb/s SONET
CDR ~$400 (telecom
application)
3

Basic Idea
Serial data transmission sends binary bits of
information as a series of optical or electrical pulses:
0111011000111110011010010000101011101100011111..

The transmission channel (coax, radio, fiber) generally
distorts the signal in various ways:

From this signal we must recover both clock and data4

Bit Error Rate (BER) Testing• Pseudo-Random-Bit-Sequence (PRBS) is used tosimulate random data for transmission across the link

• PRBS pattern 2N-1 Bits long contains all N-bit patterns• Number of errored-bits divided by total bits = BER.
• Typical links are designed for BERs better than 10-12
PRBS
data
generator
clock in

TX

RX
link
synth

PRBS
data
receiverclock in5

Eye diagram construction
random
data

scope
TX

RX
link
triggersynth

symbol cell (UI)Y
Use a precise clock to chop the data
into equal periods

XX

overlay each period onto one plot

jitterYamplitude
distribution at Y-Y

6

Some Signal Degradation Mechanisms• Multiplex Jitter• AC Coupling• Optical Pulse Dispersion• Skin Loss
• Random Noise• E+O Crosstalk• Intersymbol Interference

7

Multiplex Jitter
bit stuffing events
high speed data
sub-rate dataphase error[in UI]
time
Multiplex jitter is not a problem on the high rate channel
itself - it only occurs on non-synchronous, lower speed
tributaries that have been sent over the high-speed
channel (e.g.: DS3 over SONET OC-48).
8

Time/Voltage aberrations from AC-coupling
∆t

V
V
t=0

t

t=t

1

t1
V – VtPercent AC coupled droop is P ≡ ---------------- × 100 ≈ -------- × 100 .
V
RC

Jitter is introduced by finite slope of pulse rise/fall time:
tr t1∆t = ---------------( 2RC )9Quantized Feedback
AC-Coupled Transmission Link

TX

H (ω)

RX

Feedback voltage models missing DC information
1 – H (ω)

D Q

Output Data(models ideal
TX waveform)

clock
10

Skin Loss and Dielectric Loss
Nearly all cables are well modelled by a product of Skin Loss
S ( f ) = 10

( –k ) f( –l ) f, and Dielectric Loss D ( f ) = 10
withappropriate k,l factors. Dielectric Loss dominates in the multiGHz range. Both plot as straight lines on log(dB) vs log(f) graph.
Ring 3
Ring 2
Ring 1linear amplitude

1.0

0.0

k=.001k=.0001
k=.00001

1k freq (log scale) 10G[YFW82]

R3
R2

L3
L2
R1

Three-element equivalentcircuit of a conductor with11
skin loss

transmission (linear scale)

Skin Loss Equalization at Receiver
1.4
3dB boost
1.0 1
0.5
0.0 0
1k

equalized
pure skinloss
freq (log)

2x improvement inmaximum usable
bit-rate

10G[WWS92]12

Skin Loss Equalization at Transmitterboost the first pulse after every transition
Error at sampling pt.

usable signal[FMW97]
beforeafter
13

Decision Threshold Generation• To minimize bit-error rate, the decision threshold X-X
must centered in the signal swing. Two common ways of
automatically generating threshold voltage are:• Peak detection of signal extremes, limited run-length
required

Signalpositive peak detector

Decisionnegative peak detector

Threshold• Decision threshold = signal average, balanced signal
required

Signal

Low-Pass Filter

Decision
Threshold

After Tom Hornak: “Interface Electronics for Fiber Optic Computer Links”, (see bibliography for full citation)

14

Code Disparity
Disparity is defined as Nhigh - Nlow in past transmitted signal+5

encoded data signal

0-5signal disparity• In an unbalanced code the disparity can growwithout limit. e.g.: 4B5B code of FDDI

• In a balanced code, the disparity is limited to a
finite worst case value. e.g.: 8B10B of
FibreChannel
After Tom Hornak: “Interface Electronics for Fiber Optic Computer Links”, (see bibliography for full citation)

15

Coding for Desirable Properties• DC balance, low disparity• Bounded run length• High Coding Efficiency• Spectral Properties (decrease HF and/or DC
component)• Many Variations are Possible!
• Manchester [San82]• mB/nB [Gri69][Rou76][WiF83] [YKI84] [Pet88]• Scrambling [CCI90]• CIMT [WHY91], Conservative Code [Ofe89]
16

Simple 3B/4B code example
4B Output Data
3B Input Data
Even Words

Odd Words

000

0011

001

0101

010

0110

011

1001

100

1010

101

1100

Maximum Runlength is 6
Coding Efficiency is 4/3
Sending Sync Sequence:
SyncA(even), SyncA(odd),
SyncB(even), SyncB(odd)allows the unambiguousalignment of 4-bit frame

110

0100

1011

111

0010

1101

SyncA

0111

1110

SyncB

1000

0001

17

Scrambling• Uses a feedback shift register to randomize data reversing process at receiver restores original data
Data Input

Scrambled Data

Data Output

XOR
Shift Register
n

j

1 2

2 1

j

n

Clk
PRBS Generators
Caveat: Only guarantees balance and runlength under very specific data conditions!
After Tom Hornak: “Interface Electronics for Fiber Optic Computer Links”, (see bibliography for full citation)18

Definition of Jitter
unit
interval

-3T
-2T
-T
0
T
2T
3T
4T
Impulses spaced equally in time (jitter free signal)

time

-3T
-2T
-T
0
T
2T
3T
4T
Impulses spaced irregularly in time (jittered signal)

Errors treated as discrete samples of continuous time jitter
After Trischitta and Varma: “Jitter in Digital Transmission Systems”

19Spectrum of NRZ data
variations due to DC balance strategy

power in dB

sin ( 2πfT )------------------------2π fT

missing clock
frequency

f = 0

1 ⁄ 2T1⁄T

3 ⁄ 2T

2⁄T

20

NRZ and RZ signalling
NRZ = “non return to zero” data

+
+

+
+

+

RZ = “return to zero” data

+
+

+
+

neither clock nor
data frequency inspectrumdata frequency
clock frequency+T
NRZ signalling is almost universally used.

clock, but no data
frequency inspectrum21

Filter Method Examples[Yam80][YTY80][RFC84][Ros84][FHH84][AFK87]

X

non-linear element
delay

bandpass
filtere.g.: SAW filter
bandpass
filterLC tank

Recovered Clock Output

NRZ Data Inputd ⁄ dt2(this last circuit can be thought of as an NRZ-RZ converter)22

Summary of Filter Method
Jittered NRZ Data Signald ⁄ dtX

2

τRetimed Data
D Q

bandpass
filter/limiter

Pro:

Con:

Very simple to implement

Temperature and frequency variationof filter group delay makes samplingtime difficult to control

Can be built withmicrowave “tinkertoys”
using coax to very highfrequencies

Narrow pulses imply high fT
Hi-Q filter difficult to integrate23

Q-Factor in resonant circuits
Voltage envelope of ringing circuit falls to 1/sqrt(e) in Q
radians.
1.0

Q/2*PI cycles
Q also equals the center
frequency of a filter divided by
the full-width of the resonancemeasured at the half power
points:Fcenter/

amplitude

1.0/sqrt(e)Fcenter

High-Q filter can be emulated by PLL with low loop B.W.

24

Data Recovery with simple PLL
Jittered Data
SignalRetimed
Data
D

Q

Phase
Detector
PLL
Low-pass
Loop Filter

Voltage
Controlled
Oscillator

25

Analytic Treatment of Jitter
Perfect Clock:x ( t ) = A cos ω c t

Jittered Clock:x ( t ) = A cos [ ω c t + φ ( t ) ]φ ( t ) is then treated as a continuous time signal
After Behzad Razavi: “Monolithic Phase-Locked Loops, ISSCC96 Tutorial”

26

Model of Loop
Phase
Detector

Loop
Filter

Kφ

VCO

Kv

1
--s

1
β + ------------------( 1 + sτ )Warning: Extra Integration in loop makes for tricky design!
See Floyd M. Gardner, “Phaselock Techniques”, John Wiley and Sons, for good introduction to PLL theory27

Loop frequency responsea1
β + ------------------( 1 + sτ )Kφ(inputdata jitter)

Kv-----scb

80dB

open loop gain

40dB
0dB

c/b

c/a

-40dB
-80dB
1k

10k

100k

1M

10M

100M

1G

10G

28

Phase Detectors• Phase detectors generate a DC component proportional
to deviation of the sampling point from center of bit-cell• Phase detectors are:Continuous90°– 180 °

– 90 °

180°

0°

Binary Quantized• Binary quantized phase detectors are also called “Bangbang” phase detectors
After Tom Hornak: “Interface Electronics for Fiber Optic Computer Links”, (see bibliography for full citation)

29

“Self-Correcting Phase Detector”
UP
Data

D Q

D Q

DOWN
Data

[Hog85][Shi87]

Clock
1 = Data.................
2= Clock (Early).....
3 = 1 retimed..........
4 = Clock.................
5 = 3 retimed..........
6 = 1 xor 3 (UP).....
7 = 3xor 5 (DOWN)

30

Binary Quantized Phase Detector• NRZ data is sampled at each bit cell and near thetransitions of each bit cell

• The sign of the transition sample is compared with thepreceeding and following bit cell sample to deduce thephase error

Data

D Q

D Q

B
A

Clock

A T B
D Q

D Q

T

[Ale75][WHY91][LaW91][ReG73]

A
0
0
0
0
1
1
1
1

T
0
0
1
1
0
0
1
1

B
0
1
0
1
0
1
0
1

Outputtristate
vco fast?
vco slow
vco slow?
vco fast
tristate

31

Decision Circuit• Quantizes amplitude at precise sample instant• Typically uses positive feedback to resolve small input
signals• A master/slave D-flip-flop carefully optimized for input
sensitivity and clock phase margin is a common choice• Latches data on the rising edge of clock signal

simplified schematic symbol:

D Q
clock
32

Example Bipolar Decision Circuit
master latchslave latch
gnd

data indata out
clock inVbias
-5V

• many clever optimizations are possible[OhT83][Con84][Lai90][Run91][Hau91][Run91]

33

Loop Filters[Den88] [Dev91][LaW91] [WuW92]
VOUT

UP

DOWN

VOUT

UP

DOWN

0

0

tristate

01

ramp DOWN

10

ramp UP1

1tristate• should have provision for holding value constant (tristating) under long run-length conditions• may be analog (integrator) or digital (up-down
counter) - but watch out for metastability!

34

Metastability
slope = dv/dt
ε

∆V

D Q

∆T

For uniform clock jitter, and a latch “danger zone” of ε ,
ε dt
∆T dv

the metastability probability p metastability , is ------- ⋅ ------ .
35

Regeneration time constant τ
0.5

log10(volts)

volts

v=ε
vdiff

vdiff

0.0
0.0

log10(vdiff)
-8.0
-1.0

0.0

1.0

2.0

3.0

time [ns]A small voltage ε is forced on latch, until t=0. Differential
voltage V diff grows as ε ⋅ et⁄τ. For a given V min and ε ,the regeneration time required isV minτ ⋅ log  -------------
 ε 

.

36

SPICE tip: current-controlled R/switch# SPICE time variable resistor.
# the resistance between %in and %out is numerically# equal to the current pulled out of %ic.SUBCKT tvres %in %out %ic
h1 %inx %outx poly(2) vx vc 0 0 0 0 1
rdamp %out %outx 0.001
vx %inx %in 0
vc %ic 0 0.ENDS

R = iin * 1 Ω/Α
in
ic

out

iin

v(h1)=i(vx)*i(vc)*1 Ω/Α
in
ic

vx

h1

out

vc
36a

VCO alternatives
LC Oscillator
Speed

Multivibrator

Ring Oscillator

Technology Dependent 1-10’s of GHz, CMOS 1-2 GHz

Phase Noise

Good

Poor

Integration

Poor(L, Varactor)

Excellent

Tunability

Narrow/Slow

Wide/Fast

Stability

Good

Poor
(needs acquisition aid)

Other

Multi-Phase
Clocks• [Cor79, Ena87, Wal89, DeV91, Lam93, WKG94]
After Todd Weigandt, B. Kim, P.Gray, “Timing Jitter Analysis for High-Frequency CMOS Ring Oscillators”, March 10, 1994

37

Multivibrator VCO
Capacitor is alternately charged anddischarged by constant current
Tuned by varying Itune in current source
Diode clamps keep output voltage
constant independent of frequency
Relies on non-linear switching for
oscillation behavior, and so is limited tomoderate frequencies.
Itune

I tuneFrequency = ----------------4CV be

After Alan B. Grebene, “Analog Integrated Circuit Design”, Van Nostrand Reinhold, 1972, pp 313-315

38

Example Ring Oscillator VCO[SyA86][EnA87][Wal89]Input 1
Input 2

Input 1

OutputTune

OutputInpu

t2

Input 1Tune

Input 2
Output39

VCO injection locking (problem)
Noise coupling back to VCO

Vcc

Noise glitch

propagation delay

τ

Vtune

most VCO’s sample the tune
voltage once per cycle - down
converting the system noise.

high VCO
nom VCO•PLL: Fosc α Vtune α θerror•ILO: Fosc α Vtune α θerror

slow VCO
delayedglitchτ

VCO can injection lock to its own
delayed signal more rapidly thanto input data!

40

VCO injection locking (a solution)
Decompose theloopfilter pole/zero
into two separate
tuning inputs:Σ• a wide range input
with very low
bandwidth

low gain, wide BW• a narrow tuning
range input withwide BW.
this greatly reduces
effect of VCO noise
on tuning curve.

VCOhigh gain, low BW

41

False or Harmonic Locking to Data
data
clock
1/2 clock
2x clock
4/3 clockearly/late indications
cancel in loop filter,leaving an attenuated,but possibly stable locksignal.
correct

early

late

correct

42

Aided Acquistion• Tricky task due to Nyquist sampling constraints causedby stuttering data transitions
PDloop filter 1

Input Data
VCO
FDloop filter 2• Still subject to false lock if VCO range is too wide
After Behzad Razavi: “Monolithic Phase-Locked Loops, ISSCC96 Tutorial”

43Training Loops
Data

retimed databang-bang drive

Input
PDET

SEL

dlock
dtransflock

Reference Clock2.488GHz/256

charge
pump

Clock
VCO

LOS

State
MachineFDET[WSY97]Clock/256

1/256
divider

An increasingly common technique is to provide areference clock to the CDR circuit. This allows the VCO
process-variation to be dynamically trimmed out, avoiding
false locking problems.
44

Phasor Diagram• Graph of relative phase between clock and data
• Each complete rotation is 1 unit interval of phase slip
• Rotations/second = frequency error (in Hz)
0°

270°

Plot of data transitions
versus VCO clock phase.
90°dθ/dt = ∆F
180°

= missing transitions= actual transitions

Data at 1/2, or VCO at 2x,
the proper frequency look
locked. This puts a limit on
VCO tolerance to prevent
false locking.

45

Example Lock Detector
0°[WSY97]

270°

ideal data eye

90°

noisy data eye
180°clock a,b

data

DQ
DQ

Raw out-of lockindication
46

20G

Serial Link Speed

10G

CDR
only

5G
2G
1G

end
r
T
r
la

.4 f T)
0
5
.0
r

ne

I
8x

10M

t
5M

tC

2M

rend
T
S
MO

10X

2X

.4

200M

4X

n
u
o

o
H
t

e
nt

500M

20M

s

(0

po
Si Bi

?

-0
5
0
.
0
(

8X
e f T)
v
i
t
c
effe

500K
200K

C

100M

1M

100K
Si Bipolar
CMOS

50M
20M

Internet Host Count

Communication Trends

50K
20K

1988

1990

1992

1994

1996

Year of Publication (ISSCC)

1998

47

Multiphase Receiver Block Diagram
0

1

2

3

multi-phase clock generator(VCO + interpolator)

90o

0o

Data input

D

Q

D

Q

270o

180o
D

Q

D

Q

D

45o
Q

22o
D

Q

fT -doubler
data amplifierDQ

phasedetector/
statemachineReference Clock2.5GHz/128

16
4:16 demultiplexer[WHK98]

67o

data
clock

loop
filterLOS

48

DLL vs PLL which is “best”?
• DLLs do not filter input reference jitter, but do notaccumulate VCO phase errors - best for clock
synthesizers running from clean reference.

• PLLs can have higher phase noise because of multiple
passes through the delay gates of VCO, however is able
to filter noisy input signals.

1

ck

2 3

τ delayline

4

ck
1

2

3

4
1

[KWG94]2

3

Degraded clock period

49

Jitter Measurements• SONET has the most complete set of jittermeasurement standards, but the techniques areuseful and relevant for datacom applications also

• Jitter Tolerance• Jitter Transfer• Jitter Generation

50

Jitter Tolerance Test Setup
laser
transmitter

opticalreceiverdata
generator

FM
modulatedclocksine wave
generator

xamp +
limiter
opticalattenuator

decisioncircuit

bit error
rate tester

retiming
circuitAt each frequency, the sinewave
modulation amplitude is increased until
the BER penalty is equal to thatcaused by 1dB optical attentuation

After Trischitta and Varma: “Jitter in Digital Transmission Systems”

51

SONET Jitter Tolerance Mask
15 UI

acceptablerange

1.5 UI
0.15 UI
f0

f1

f2

f3

ft

Data Ratef0[Hz]

f1[Hz]

f2 [Hz]f3 [kHz]ft [kHz]

155 Mb

10

30

300

6.5

65

622 Mb

10

30

300

25

250

2.488 Gb

10

600

6000

100

1000

10 Gb

?

?

?

400

4000

from SONET SPEC: TA-NWT-000253 Issue 6, Sept. 1990, fig 5-13

52

Jitter Transfer Measurement
data
generator

decisioncircuitclock

SignalGenerator

Phase
detector

retiming
circuitPhase
modulator

D.U.T.
ϕ[TrV89] [RaO91]
IN

OUT

network
analyzer
53

Jitter Transfer Specification
P[dB]slope = -20 dB/decade
acceptable
range

f

c

Data Ratefc[kHz]P[dB]

155 Mb130

0.1

622 Mb500

0.1

2.488 Gb

2000

0.1

This specification isintended to control
jitter peaking in long
repeater chains
54

Jitter Generation
decisioncircuitretiming
circuit
S.U.T.

computerspectrum
analyzer

recovered
clock

55

Jitter Generation (cont.)

3) RMS sum total noise voltages over band

nt
ulta

2) Multiply Jitter components by Filter Mask

∆Θ

res

 V sidebandJitter pp ( rads ) = 2∆Θ ≅ 2 atan  -------------------------- V clock 

sidebandclock amplitude

1) Measure Jitter Sidebands around Clock4) Convert RMS noise voltage to RMS jitter

OC-48 (2.488 Gb/s SONET) specifies 12 kHz hipass filter,and maximum 0.01 UI RMS integrated jitter.
56

Why bother with a BB loop?
• it may be difficult to maintain optimum sampling pointwith traditional PD/PLL or with filter method overprocess, temperature and supply variation• Narrow pulses of linear PD’s may not work well at
extremely high bit rates• for monolithic implementation, BB PD has excellent
match between retiming latch and PD latch - allows
for operation at highest latch toggle frequency
B

data

D Q

DQ

DQ

A

DQ

DQ

T

data
PD
clk
filterVCO

57

Simple first-order BB loop
VCO
D

Q
tupdate• VCO runs at two discrete frequencies: f nom ± f bb .
• Phase error is evaluated at a discrete time intervalt update . In the general case, this can be consideredapproximately equal to mean transition time of the
data.
58

How to simulate a loop?
• SPICE (boolean & polynomial)• timestep simulator [FLS63]• event driven simulator [Mac87]• actual hardware

The need for fast simulation• understand the design space• check corner cases• build intuition59

Efficient Simulation Strategy• Simulating VCO waveform is unnecessary to accurately
model ideal PLL behavior.

• Only frequency and phase is needed.
• Model all circuit time-varying state variables as voltages.
• Convert between frequency and phase variables with
explicit integration block.

60

Model of First-order Loop
φmod
Fin

∫ v dtΣΣ

Kvco
fsample

node:

Fin

∆F

∆θ1

Θerrorbbtune

Fvco

unit:

Hz

Hz

UI

UI

V

Hz

61

The simulator main loopfor (simtime=STARTTIME; simtime<=STOPTIME; simtime+=stepsize) {update();/* update nodes each tstep */if (simtime-SAVETIME >= savestep*points_plotted) {output();points_plotted++;}/* swap pointers to avoid copying data arrays */temp = nodeold;nodeold = node;
node = nodenew;
nodenew = temp;
}

0

1 2
nodeold

N

2N
node

3N
nodenew

62

The update() routine
void update() /* this routine responsible for updating node[] */{fin(1,FIN,FSTEP,STEPTIME);/* vo, f, fs, t0 */difference(1,8,2);/* plus, minus, out */freq_to_phase(2,3);/* in, out */sing(11,PHIFREQ,180.0*PHIDEV); /* phase modulation input */
difference(3,11,4);/* in+, in-, output */sample(4,6,UTIME,VPHI,0.0);/* in, out, utime, swing, err */rcfilter(6,7,TAU1);/* in, out, tau */vco(7,8,FVCO,FDEL);/* in, out, nom, del */}• notice similiarity to SPICE deck (numbered nodes)• input “deck” parsing done by C-compiler• user must assign nodes manually63difference() and sine generator code
void difference(plus, minus, out) /* output node = plus - minus */int plus, minus, out;{
nodenew[out] = node[plus] - node[minus];}

void sing(out, freq, ampl) /* a sinusoidal voltage source */int out;
double freq,ampl;{
nodenew[out] = ampl*sin(2.0*M_PI*simtime*freq);}64RC-filter implementation
void rcfilter(in, out, tau)
int in, out;
double tau;{
double temp1, temp2;/* a single pole rc filter */

vin

R

vout
I = C dv/dt/* Implements discrete diff. eqn:
Vout = Vin - (tau * dVout/dt)
where dVout = nodenew[out]-node[out] */temp1 = node[in] + tau*(node[out])/stepsize;
temp2 = 1 + tau/stepsize;
nodenew[out] = (temp1/temp2);}

65

The freq_to_phase() block
void freq_to_phase(in, out)
int in, out;/* performs true integral of input *//* scaled by factor of 360. This *//* gives output of 1 volt/degree */{double chunk;/* new integrated portion of signal */chunk = (180.0 * (nodeold[in] + node[in]) * stepsize);
nodenew[out] = node[out] + chunk;# now wrap it into the range of -180 to +180 degrees
if (nodenew[out] > 180)
nodenew[out] = nodenew[out]-360;
if (nodenew[out] < -180)
nodenew[out] = nodenew[out]+360;}

66

Lock Range for 1st-order loop
06:52Aug 1998
vcofreqMHz2490.0fin
2484.0Degrees

200.0

0.0

phierr-200.0

5.0

10.0
time (µseconds)

15.0

67

1st-order loop: locked region
06:52Aug 1998
2490.0vcofreqMHzfin2485.0Degrees40.0
phierr
0.0

-40.0
8.0

10.0
time (µseconds)

12.0

68

1st-order loop: slew-rate limiting
05:32Jul 1998

MHz

2490.0vcofreqfin

Degrees2486.00.0

phimoddphi1

Degrees-200.00.0-100.05.0

phierr

6.0

7.0

8.0

time (µseconds)

69Summary of 1st-order loop
• Lock range: ( f nom + f bb ) < f c < ( f nom – f bb ) .
• Jitter (peak to peak): J pp ≈ 2 ⋅ 360 ⋅ t update ⋅ f bb .
• Maximum amplitude of phase modulation at frequency
f mod before onset of slew-rate limiting:• If locked, then the duty cycle C , must result in the
average loop frequency being equal to the input
frequency f c ,f c = f nom + ∆f = C ( f nom + f bb ) + ( 1 – C ) ( f nom – f bb )• Phase detector average duty cycle C , given by∆f 
 1--- + -------------------- (proportional to 2 ( 2 ⋅ f )
bb

∆f ).

70

Observations• Jitter generation, Lock range, and Jitter tolerance are allinconveniently controlled by one parameter, f bb .

• Phase detector average duty-cycle is proportional tofrequency error.

• Strategy: Use the average duty cycle to control loop
center frequency. This decouples the lock range fromjitter tolerance/generation giving more design freedom.

71

2nd-order BB loop
Proportional (BB) branch
VCO

β
D

Q Vφ

Σ

∫

1
--- v dt
τKvco

Integral branch72

2nd-order loop step response
tupdateVφ

pd output

VφβKv

BB frequency change

VφβKvtBB phase phase change

VφKvt/τ

Integrator path frequency change

VφKvt2/2τ

Integrator path phase change73

Stability Factor ξ
tupdatephase change from BB path
phase change from integral path

To quantify the relative independance of the two feedback
loops, take ratio of phase change from BB path to thephase change of the integral path:∆θ bb
βV φ K v t2βτξ ≡ ------------- = ---------------------------------- = -----------------2∆θ intt updateV φ K v t ⁄ ( 2τ )74

structural evolution of 2nd-order loop
φmod
Fin

∫ v dt

Σ

β

Σ

Fin

Σ
∆F

∫ v dtΣ

1--- v dt
τ

Kv

∫

∫

βK v v dt

θbb

Fint

Kv

1
--- v dtτfsampleφmodΣΣ∆θ1 ∆θ2 ∆θ3Vφfsample∫75

2nd-order loop: small step in F
FindegreesMHz

2490.0Fint
2487.0
40.0

∆θ1

∆θ3

0.0

θbb
3

3

1

1

volts

2.0
1

1

1

1

0.0

Vφ
1

1

1

1

1

1

-2.0
4.0

5.0

6.0

7.0

time (µseconds)
76

2nd-order loop: large step in F
MHz

2500.0degrees2480.0
400.0

Fin
Fint
θbb

∆θ1

0.0

∆θ3

volts

2.0
0.0

Vφ

-2.0
4.0

5.0

6.0

7.0

time (µseconds)
77

2nd-order loop: phase jitter tracking

volts

degreesdegrees

100.0

2
1

0.0

2

2
3

∆θ2

-100.0
50.0
0.0
-50.0
2.0

1

φmod

1

θbb
∆θ2

∆θ1
3

1

2
3

1
2

∆θ3
2

0.0
-2.0

4.0

2

Vφ
5.0

6.0

7.0

time (µseconds)
78

degrees

degrees

2nd-order loop: slope overload
200.0

∆θ1

0.0

φmod

∆θ2

-200.0
100.0

θbb

0.0
-100.0

1

∆θ3

∆θ2

volts

2.0

Vφ

0.0
-2.0
4.0

5.0

6.0

7.0

time (µseconds)
79

normalized ∆Σ form of 2nd-order loop
• pull integrators through the summing node
• normalize update interval to 1
• let βKvVφ = fbb• substitute in definition for ξ
f bb

Fin

Σ

∆F

Σ

∫ v dt∆θ±1

t=0,1,2...
1st-order ∆Σ on ∆F∫ v dt2 f bb-----------ξ80∆Σ linear system analogy for bb-loop

Σ
X(z)

H(z)

Σ
Y(z)

(integration)[Hau91b][Gal95]

Q(z)

gain

gain

H (z)
1
--------------------------------------- Q(z)Y (z) =
X (z) +
1 + H (z)1 + H (z)

freq

freq

81

solve for slope overload
f bb

Fin

Σ

∆F

Σ

1
--s

∆θ

1
--s

2 f bb-----------ξ

• Slew rate limiting occurs when ∆F > fbb• Maximum input phase modulation in UI, normalizedto ∆θbb is s 2 + s + 2--- ⁄ ( s 3 + s 2 ) .

ξ

82

slope overload limit vs ξ
max jitter before S.R.L [normalized to ∆θBB]

100G

ξ=0.1
 s 2 + s + 2--- ⁄ ( s 3 + s 2 )

ξ
ξ=1
ξ=10

1G
10M
100k

points shown
are from numericalsimulation

ξ=100
ξ=1000

1k
10
0.1
1µ

10µ

100µ

1m

10m

0.1

jitter frequency * tupdate

1

10

83

jitter generation in frequency-domain• ∆Σ approximation justifies replacing BB phase detector
with a noise source.

• Combine total loop phase noise by combining eachphase noise source in RMS fashion.

source
phase
noise

Σ

1
β + ----sτΣBB phase noiseof form: Asin(x)/xKv-----sΣ

output

VCO open loop phase noiseKv1H ( s ) = ------ β + ----s sτ84dBc/HzdBc/HzdB

example jitter generation calculation
0
-20
-40
-60
-80
-100
-120
-80
-90
-100
-110
-120
-130
-140
-80
-90
-100
-110
-120
-130
-140
1k

H (s)
--------------------1 + H (s)1--------------------1 + H (s)vco phase noisebb phase noise

sourcephase noisecomputed phase noise
measured phase noise
10k

100k

1M

10M

100M

see [WSY97]: fvco=2.488 GHz, fbb = 6 MHz, ξ=32000, tupdate=400ps.

1G

85

The ultimate in simulator speed• Compute precise transient response of system at
discrete update times with Laplace transforms.

f bb±1-----sΣ
2 f bb-----------ξs

vc
----s

2 f bb-----------ξsfv-----stbbbbΦ ( t + 1 ) = Φ ( t ) ± b b + 2 ------ ∑ ( earlylate ) ± -----ξξ
086

simulator core loopfor (cycle=1; cycle<=numpoints; cycle++) {data_phase = gauss()*jitter;
vco_phase += direction*bangbang;
vco_phase += 2.0*loop_filter*bangbang/psi;
vco_phase += direction*bangbang/psi;
printf(“%d %g\n”, cycle, vco_phase);

fflush(stdout);

direction = (vco_phase >= data_phase) ? (-1) : (1);loop_filter += direction;}

87

RMS output jitter [normalized to θBB]

gaussian jitter generation & gain vs ξ
10M
1M

ξ = 1e-06
ξ = 1e-05

100k
10k

ξ = 1e-04
ξ = 0.001

1kξ = 0.01100

ξ = 0.1

10

Jidle = 0.6+(1.65/ξ)Jlin = 2*Jin/(1+sqrt(ξ))
Jwalk = 0.7*sqrt(Jin)
Jtot = Jidle + Jlin +Jwalk

ξ=1
ξ = 101
0.1
1m

10m 0.1

1

10

100

1k

10k

RMS input jitter [normalized to θBB]
( non-tristated loop , ptransition = 100% , 10 timesteps simulated per point)
8

100k

1M

88

Stability with run-length & latency
Slope(t=0) = S

0

∆1
∆0

ε2/ξ - Sεε

For bounded convergence and stable operation, theovershoot ∆1 must be less than or equal to theundershoot ∆0. This condition is guaranteed if

ξ > 2ε(ε is the loop update latency normalized to tupdate)89

jitter [normalized to θBB]

Effect of BB/charge-pump tristating
15
10
5
0
-5
-10
-15
0

tristated loop

non-tristated
1000

2000

3000

4000

5000

6000

7000

8000

9000

10000

timestep [normalized to bit time]•tristating doesn’t change
vco frequency when notransition in the data.

•Untristated loop has peakjitter run-length times
worse than tristated loop
(simulated with ξ=100, ptransition = 50% )

12
8
4
0
-4
8880

8920

8960

9000

90

Public Domain Tools
Linux (a free UNIX clone for INTEL x86 platforms) - Excellent
platform for creative circuit design and simulation. See
www.cheapbytes.com for a $1.95 distribution CD.

•Homepage: http://www.linux.org/•Documentation: http://sunsite.unc.edu/mdw/LDP•Scientific Apps: http://SAL.KachinaTech.COM/index.shtml• ACS Circuit simulator• EOS Electronic Object Simulator• Berkeley SPICE 3f5 (bsim3 models)• SCEPTRE
91

Summary
A lot of complexity for a “simple” system...
It’s more of an art than a science
After understanding:• the components,• the block diagrams,• the problems and the attempted solutions,• and the unique needs for your application,
Then it’s time to have fun!

92

CDR Application Space
Datacom 26%

Telecom 7%
Fiber 3%Coppercoax 23%
pcb

Radio

3%

tp
IR

0.5%

Other (disk 3%)
numbers estimated from ~250 attendees at February 1997 ISSCC CDR tutorialCDR Design Checklist
RCW 01/15/97, updated 9/18/98
1) Eye Margin• how much noise can be added to the input signal while maintaining target BER?
(voltage margin)• How far can clock phase alignment be varied while maintaining target BER? (phasemargin)• how much does the static phase error vary versus frequency, temperature andprocess variation?
• Is input amplifier gain, noise and offset sufficient?
2) Jitter Characteristics• what is the jitter generation? (VCO phase noise, etc)
• what is the jitter transfer function? (peaking and bandwidth)• what is the jitter tracking tolerance versus frequency?
3) Pattern Dependency• how do long runlengths affect system performance?
• is bandwidth sufficient for individual isolated bit pulses?

• are there other problematic data patterns? (resonances)• does PLL bandwidth, jitter, and stability change versus transition density?
4) Acquisition Time• what is the initial, power-on lock time?
• what is the phase-lock aquisition time when input source is changed?
5) How is precision achieved?

• are external capacitors, inductors needed?
• does the CDR need an external reference frequency?
• are laser-trimming or highly precise IC processes required?
6) Input/output impedance• Is S11/S22 (input/output impedance) maintained across the frequency band?
• are reflections large enough to lead to eye closure and pattern dependency?
• is >15 dB return loss maintained across the band?
7) Power Supply• does the CDR create power supply noise?
• how sensitive is the CDR to supply noise?
• Is the VCO self-modulated through its own supply noise? (can be “deadly”)

• what is the total static power dissipation?
• what is the die temperature under worse case conditions?
8) False lock susceptibility• can false lock occur with particular data patterns?
• are false lock conditions be detected and eliminated?
• does the phase detector have VCO frequency leakage that can cause injection
locking?
• can the VCO run faster than the phase/frequency detector can operate? (another“killer”)• have all latchup/deadly embrace conditions been considered and eliminated?

References[Ale75][AFD87][Arm83][Baa86][Buc92][Byr63][CCI90][Car56][Cho92][Con84][Cor79][DR78][DeV91][Den88][EnA87]Alexander, J. D. H., Clock Recovery from Random Binary Signals, Electronics Letters 11, 22 (30th October 1975), 541-542. {binary
quantized phase detector}.
Andrews, G. E., D. C. Farley, S. H. Dravitz, A. W. Schelling, P. C. Davis and L. G. McAfee, A 300Mb/s Clock Recovery and Data
Retiming System, ISSCC Digest of Technical Papers, 1987, 188-189. {SAW Filter Clock Recovery with emphasis on phase alignment
problem}.
Armitage, C. B., SAW Filter Retiming in the AT&T 432 Mb/s Lightwave Regenerator, Conference Proceedings: AT&T Bell Labs.,
Holmdel, NJ, USA, September 3-6, 1984, 102-103. {matches tempco of SAW to tempco of electronics.}.
Baack, C., Optical Wide Band Transmission Systems, CRC Press Inc., 1986. {example of PLL for clock recovery}.
Buchwald et al., A., A 6GHz Integrated Phase-Locked Loop using AlGaAs/GaAs Heterojunction Bipolar Transistors, ISSCC Digestof Technical Papers, 1992, 98,99,253. {Frequency multiplying ring oscillator}.
Byrne et al., C. J., Systematic Jitter in Chain of Digital Regenerators, The Bell System Technical Journal, November 1963, 2679.
{clock extraction by filtering}.
CCITT, Digital Line systems based on the synchronous digital hierarchy for use on optical fiber cables, CCITT G.958, 1990.
{SONET Payload test patterns regenerator scrambling}.
Carter, R. O., Low-Disparity Binary Coding System, Electronics Letters 1, 3 (May, 1956), 67-68. {conditional inversion data encoding disparity}.
Chona, F. M. R., Draft Standard, SONET inter-office and intra-office line jitter re., T1X1.3, May 11, 1992. {Standards SONET jitter}.
Connor et al., P. O., A Monolithic Multigigabit/Second DCFL GaAs Decision Circuit, IEEE Electron Device Letters EDL-5, 7 (July
1984), 226-227. {GaAs Fet decision circuit example}.
Cordell et al., R. R., A 50MHz Phase and Frequency Locked Loop, IEEE Journal of Solid State Circuits SC-14, 6 (December 1979),
1003-1009. {quadricorrellator phase detector, Tunable LC Oscillator}.
D’Andrea, N. A. and F. Russo, A Binary Quantized Digital Phase Locked Loop: A Graphical Analysis, IEEE Transactions on Communications COM-26, 9 (September 1978), 1355-1364. {Analysis of BB loop}.
DeVito et al., L., A 52 MHz and 155MHz Clock-Recovery PLL, ISSCC Digest of Technical Papers, February 13-15, 1991, 142, 143,
306. {multivibrator example, Negative resistor chargepump, rotational freq.det.}.
Den Dulk, R. C., Digital Fast Acquisition Method for Phase-Lock Loops, Electronics Letters 24, 17 (18th August 1988), 1079-1080.
{2 order of magnitude locking speed-up with fancy slip detector & charge pump}.
Enam, S. K. and A. A. Abidi, Decision and clock Recovery Circuits for Gigahertz Optical Fiber Receivers in Silicon NMOS, Journalof Lightwave Technology LT-5, 3 (March 1987), 367-372. {MOS tunable monolithic ring oscillator example - Some clever circuit
ideas for gigabit rates}.

[EnA92][FHH84][FLS63][FMW97][Gal94][Gal95][Gar79][Gla85][Gri69][GMP78][Gup75][Hau91a][Hau91b][HeS88][Hog85][Hor92][Hu93]

Enam, S. K. and A. A. Abidi, MOS Decision and Clock Recovery Circuits for Gb/s Optical-Fiber Receivers, ISSCC Digest of Technical Papers, 1992, 96,97,253. {quadratic phase detector} {MOS decision circuit example}.
Faulkner, D. W., I. Hawker, R. J. Hawkins and A. Stevenson, An Integrated Regenerator for High Speed Optical Fiber Transmission
Systems, IEE Conference Proceedings (November 30 - December 1, 1983) 8-13. {uses rectifier/SAW combo}.
Feynman, R., R. B. Leighton and M. Sands, The Feynman Lectures on Physics, Addison-Wesley Publishing Company, 1963. {Short,
simple presentation of timestep analysis for planetary motion}.
Fiedler, A., R. Mactaggart, J. Welch and S. Krishnan, A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal PreEmphasis, ISSCC Digest of Technical Papers 40 (February 6-8 1997), 238,239,464. {transmit pre-emphasis, skin loss equalizer}.
Galton, I., Higher-order Delta-Sigma Frequency-to-Digital Conversion, Proceedings of IEEE International Symposium on Circuits
and Systems (May 30 - June 2, 1994) 441-444 {Delta-Sigma BB loops phase tracking frequency digitalization PLL}.
Galton, I., Analog-Input Digital Phase-Locked Loops for Precise Frequency and Phase Demodulation, Transactions on Circuits andSystems-II: Analog and Digital Signal Processing 42, 10 (October 1995), 621-630. {good discussion of delta-sigma analysis of BB
PLL’s}.
Gardner, F. M., Phaselock Techniques, Second Edition, John Wiley and Sons, Inc., 1979. {example of using exor-gate to generateclock component from NRZ data}.
Glance, B. S., New Phase-Lock Loop Circuit Providing Very Fast Acquistion Time, IEEE Transactions on Microwave Theory andTechniques MTT-33, 9 (September 1985), 747-754. {adds non-linear time constant to speed PLL acquisition by 2 orders of mag.}.
Griffiths, J. M., Binary Code Suitable for Line Transmission, Electronics Letters 5, 4 (February 20, 1969), 79-81. {5b/6b encoding
example}.
Gruber, J., P. Marten, R. Petschacher and P. Russer, Electronic Circuits for High Bit Rate Digital Fiber Optic Communication Systems, IEEE Transactions on Communications COM-26, 7 (July 1978), 1088-1098.
Gupta, S. C., Phase-Locked Loops, Proceedings of the IEEE 63, 2 (February 1975), 291-306. {Good systematic outline survey ofcommunication-type PLL’s}.
Hauenschild et al., J., A Silicon Bipolar Decision Circuit Operating up to 15Gb/s, IEEE Journal of Solid State Circuits 26, No.11(November 1991), 1734-1736. {Si bipolar decision circuit example}.
Hauser, M. W., Principles of Oversampling A/D Conversion, J. Audio Eng. So. Vol 39, 1/2 (Jan/February 1991), 3-26. {excellent tutorial on Delta Sigma AD, Oversampling, noiseshaping}.
Hein, J. P. and J. W. Scott, z-Domain Model for Discrete-Time PLL’s, IEEE Transactions on Circuits and Systems 35, 11 (November
1988), 1393-1400. {good discussion of using z-transforms in PLL analysis}.
Hogge, Jr., C. R., A Self Correcting Clock Recovery Circuit, IEEE Transactions on Electron Devices ED-32, 12 (December 1985),
2704-2706. {Original Hogge detector, interesting phase detector idea...}.
Hornak, T., Interface Electronics for Fiber Optic Computer Links, Intensive Course on Practical Aspects in Analog IC Design, Lausanne, Switzerland, June 29-July 10, 1992. {Excellent overview of components for serial optical data transmission}.
Hu, T. and P. Gray, A Monolithic 480 Mb/s AGC/Decision/Clock Recovery Circuit in 1.2 um CMOS, IEEE Journal of Solid State
Circuits 28, 12 (Dec. 1993) 1314-20 {CMOS parallel signal paths multiphase sampling CDR mux}.

[Kas85][KWG94][Lai90][LaW91][Lam93][LiC81][Mac87][McG90][OFC84][Ofe89][OhT83][Par89][Pet88][RaO91][Raz96a][Raz96b][ReG73]Kasper et al., B. L., SAGM Avalanche Photodiode Optical Receiver for 2 Gbit/s and 4 Gbit/s, Electronic Letters 21, 21 (10th October1985), 982-984. {eye diagram}.
Kim, B., T. C. Weigandt and P. R. Gray, PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design, ISCAS proceedings, May 30 - June 2, 1994, 31-34. {Excellent and Intuitive discussion of Jitter in Ring Oscillators}.
Lai, B., Decision Circuit Lowers Transmission Bit Error Rates, Microwaves and RF, July 1990, 118- 122. {Si bipolar decision circuit
example}.
Lai, B. and R. C. Walker, A Monolithic 622Mb/s Clock Extraction Data Retiming Circuit, ISSCC Digest of Technical Papers 34 (February 13-15, 1991), 144,145. {binary quantized phase detector}.
Lam, V. M. T., Microwave Oscillator Phase Noise Reduction Using Negative Resistance Compensation, Electronics Letters 29, 4(February 18th, 1993), 379-340. {Leeson negative resistance phase noise second harmonic IC}.
Lindsey, W. C. and C. M. Chie, A Survey of Digital Phase-Locked Loops, Proceeding of the IEEE 69, 4 (April 1981), 410-431. {Presents a good taxonomy of digital PLLs}.
MacDougall, M. H., Simulating Computer Systems - Techniques and Tools, The MIT Press, Cambridge, Massachusetts, 1987.
{description and source code for event driven simulator}.
McGaughey, J. T., Convert NRZ format to Biphase, Electronic Design, April 12, 1990, 86. {biphase example}.
O’Connor, P., P. G. Flahive, W. Clemetson, R. L. Panock, S. H. Wemple, S. C. Shunk and D. P. Takahashi, A Monolithic Multigigabit/
Second DCFL GaAs Decision Circuit, IEEE Electron Device Letters EDL-5, 7 (July 1984),. {2.4 GHz ED GaAs Mesfet Flip-flop w/
input buffer amp}.
Ofek, Y., The Conservative Code for Bit Synchronization, IEEE Transactions on Communications, 1989. {conserves transition number uses divider for clock recovery}.
Ohta, N. and T. Takada, High Speed GaAs SCFL Monolithic Integrated Decision Circuit for Gb/s Optical Repeaters, Electronics Letters, September 1983. {GaAs Decision Circuit}.
Park et al., M. S., Novel Regeneration Having Simple Clock Extraction and Automatic Phase Controlled Retiming Circuit, Electronic
Letters 25 (January 1989), 83-84. {clock extraction by filtering}.
Petrovic, R., Low Redundancy Optical Fiber Line Code, Journal of Optical Communication 9, 3 (1988), 108-111. {13B/14B code
design}.
Ransijn, H. and P. O’Connor, A PLL-Based 2.5-Gb/s GaAs Clock and Data Regenerator IC, JSSC 26, 10 (October 1991), 1345-1353.
{Rotational frequency detector, Limiting Amp, Jitter Transfer Measurement}.
B. Razavi, ed., Monolithic phase-locked loops and clock recovery circuits: theory and design, IEEE Press, 1996. {A volume of
selected reprints with bibliography}.
Razavi, B., Monolithic Phase-Locked Loops, ISSCC Tutorial, San Francisco, CA, February 7, 1996. {Good overview of non-datadriven PLL theory}.
Reddy, C. P. and S. C. Gupta, A Class of All-Digital Phase Locked Loops: Modeling and Analysis, IEEE Transactions on industrial
Electronics and Control Instrumentation IECI-20, 4 (November 1973), 239-251. {discusses of binary-quantized phase detection}.

[RCF84][Ros84][Ros85][RHF90][Rou76][RoM77][RuG91][Run91][San82][Shi87][SyA86][TrV89][Wal89][WHY91][WWS92][WSY97]

Rosenberg, R. L., C. Chamzas and D. A. Fishman, Timing Recovery with SAW Transversal Filters in the Regenerators of Undersea
Long-Haul Fiber Transmission Systems, Journal of Lightwave Technology LT-2, 6 (December 1984), 917-925. {discusses jitter accumulation}.
Rosenberg et al., R. L., Timing Recovery with SAW Transversal filters in the Regenerators of Undersea Long-haul Fiber Transmission Systems, IEEE Journal of Lightwave Technology LT-2, 6 (December 1984), 917-925. {clock extraction by SAW}.
Ross, F. E., An Overview of FDDI: the Fiber Distributed Data Interface, IEEE Journal on Selected Areas in Communications 7, 7
(September 1985), 1046, Table 1. {4b/5b encoding example, example of frame synch characters}.
Ross, F. E., J. R. Hamstra and R. L. Fink, FDDI - A LAN among MANs, ACM Computer Communications Review, July 1990, 16-31.
{4b/5b encoding example}.
Rousseau, M., Block Codes for Optical-Fibre Communication, Electronics Letters 12, 18 (2nd September 1976), 478-479. {mBnB
code discussion, run length limits, power spectra, 5b6b recommended}.
Roza, E. and P. W. Millenaar, An Experimental 560 MBit/s Repeater with Integrated Circuits, IEEE Transactions on Communications
COM-25, 9 (September 1977),. {coax-based. good comparison of PLL vs filter-type clock extraction}.
Runge, K. and J. L. Gimlett, 20Gb/s AlGaAs HBT Decision Circuit IC, Electronics Letters 27, 25 (5th December 1991), 2376-2378.
{GaAs HBT decision circuit example}.
Runge et al., K., Silicon Bipolar Integrated Circuits for Multi-Gb/s Optical Communication Systems, IEEE Journal on Selected Areasin Communications 9, 5 (June 1991), 640. {Si bipolar decision circuit example}.
Sandera, L., Improve Datacomm Links by Using Manchester Code, EDN, February 17, 1982, 155-162. {manchester coding example}.
Shin et al., D., Selfcorrecting Clock Recovery Circuit with Improved Jitter Performance, Electronics Letters 23, 3 (29th January1987), 110-111. {Improved Hogge detector}.
Syed, K. E. and A. A. Abidi, Gigahertz Voltage Controlled Oscillator, Electronics Letters 22 (June 5, 1986), 677-679. {MOS tunablemonolithic ring oscillator example}.
Trischitta, P. R. and E. L. Varma, Jitter in digital transmission systems, Artech House, Inc., 1989. {good overview of jitter (textbook)ISBN 0-89006-248-X}.
Walker, R. C., Fully Integrated High Speed Voltage Controlled Ring Oscillator, U.S. Patent 4,884,041, Granted Nov. 28, 1989. {Sibipolar tunable monolithic ring oscillator example}.
Walker, R. C., T. Hornak, C. Yen, J. Doernberg and K. H. Springer, A 1.5Gb/s Link Interface Chipset for Computer Data Transmission, IEEE Journal on Selected Areas in Communications 9, 5 (June 1991), 698-703. {binary quantized phase detector with mastertransition}.
Walker, R., J. Wu, C. Stout, B. Lai, C. Yen, T. Hornak and P. Petruno, A 2-Chip 1.5Gb/s Bus-Oriented Serial Link Interface, ISSCC
Digest of Technical Papers 35 (February 19-21 1992), 226,227,291. {MT Code, Ring Osc} binary quantized phase detector with master transition}.
Walker, R., C. Stout and C. Yen, A 2.488Gb/s Si-Bipolar Cloc k and Data Recovery IC with Robust Loss of Signal Detection, ISSCC
Digest of Technical Papers 40 (February 6-8 1997), 246,247,466. {training loop, loss of signal detection, bb-loop, ring oscillator}.

[WHK98][WKG94][WiF83][Wu92][YTY80][Yam80][YFW82][YKI84]

Walker, R. C., K. Hsieh, T. A. Knotts and C. Yen, A 10Gb/s Si-Bipolar TX/RX Chipset for Computer Data Transmission, ISSCC
Digest of Technical Papers 41 (February 5-7 1998), 302,303,450. {multi-phase architecture, 8-phase VCO, ft-doubler amplifier, bbloop}.
Weigandt, T. C., B. Kim and P. R. Gray, Analysis of Timing Jitter in CMOS Ring Oscillators, ISCAS proceedings, May 30 - June 2,
1994. {Excellent and Intuitive discussion of Jitter in Ring Oscillators}.
Widmar, A. X. and P. A. Franaszek, A DC Balanced, partitioned-Block 8B/10B Transmission Code, IBM Journal of Research andDevelopment 27, 5 (September 1983), 440-451. {8b/10b encoding example - Precursor to Fiber Channel’s 8B/10B code}.
Wu, J. and R. C. Walker, A Bipolar 1.5Gb/s Monolithic Phase Locked Loop for Clock and Data Extraction, VLSI Circuit Symposium,
Seattle, June 3-5, 1992. {positive feedback PLL loop filter}.
Yamada, J., J. Temmyo, S. Yoshikawa and T. Kimura, 1.6 Gbit/s Optical Receiver at 1.3um with SAW Timing Retrieval Circuit, Electronics Letters, 1980, 57-58. {basic SAW system, with discussion of power penalty for SAW phase shifts}.
Yamada et al., J., 1.6Gb/s Optical Receiver at 1.3um with SAW Timing Retrieval Circuit, Electronics Letters 16, 2 (17th January1980), 57- 58. {clock extraction by SAW}.
Yen, C., Z. Fazarinc and R. Wheeler, Time-domain skin-effect model for transient analysis of lossy transmission lines., Proceedingsof the IEEE 70, 7 (July 1982), 750-757. {skin-effect lossy transmission line transient simulation modelling}.
Yoshikai, N., K. Katagiri and T. Ito, mB1C Code and its Performance in an Optical Communication System, IEEE Transactions on
Communications COM-32, 2 (February 1984). {uses m binary bits + one complementary bit stuffed to break runs}.