Two-Level Controlled Parallel
Reconfigurable Architecture
Takanobu Baba and Kanemitsu Ootsu,

Utsunomiya University, JapanOutline
Review of microprogramming and two-levelmicroprogramming scheme
Introduction of two-level microprogrammed
multiprocessor architecture
Proposal of two-level control structure forfine-grained reconfiguration
Conclusion

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2Our motivation
To use old wineskins- microprogramming to store new wine
- reconfigurable parallel architecture -2017.2.4

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Review of microprogramming
andtwo-level microprogramming scheme2017.2.4

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4Microprogramming revisited
Invented by M.V. Wilkes in 1951


as a means for systematically designing computer’scontrol part

Utilization of the technology
bridging the gap between an instruction set definition
and the underlying hardware
 the use of semiconductor memory as control storage
lead to dynamic microprogramming
Types of microinstruction set
vertical type vs horizontal type two-level microprogramming as the combination

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Features of micro-instruction set
level architecture
Basically, one-machine cycle execution
Decoded signals -micro-orders- directly control
RTL operations -micro-operations –Single micro-instruction controls not only usual
ALU & memory operations but also sequence ofmicro-instructions

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Inheritance of the technologies
RISC computerspolicy of simple operations

VLIW architecturelong microinstruction of horizontal typeCompiler optimizations
local and global microprogram optimization
technologies

To me, they seem to raise micro-instruction set
level technologies to machine instruction set one
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Introduction oftwo-level microprogrammedmultiprocessor architecture-MUNAP-

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Two-level microprogrammed
multiprocessor architecture –MUNAP Adoption of two-level
control structure
coupled with themultiprocessor
parallelism
 MUlti-NAnoProgrammachine2017.2.4

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9Micro-nano interaction mechanism(i) activation of nanos by micro, and notifying thetermination of nano to micro;(ii) transferring the test results from nano to micro; and(iii) requesting from one-level to another2017.2.4

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10Micro-level reconfiguration
f0BABAf0CCDf1
f2f1EDf2E

f3(((A f0 B)f1 C)f2 D)f3 Ef3(((A f0 B) f1 C) f2 D) f3 E(a) Logical view of four-stage
16-bit cascading(b) Physical data flow for (a) f0 through f3 indicate functions of PU0 through PU3, respectively other configurations are possible by using the same HW
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MUNAP prototype (1978~)2017.2.4

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12Proposal of
two-level control structure
for fine-grained reconfiguration

FPGA accelerators and dynamically
microprogrammable machinesReconfigurable fabric for heavy workloads
e.g., Catapult・・Bing’s ranking engine by 8 FPGAs

Standing position
between the HW implementation (ASIC) and the SWimplementation
 ASIC - realizes high performance execution, but lacks
the reconfigurability and fast development round SW - hard to meet heavy workloads
Both bridge the gap between these two extreme
implementations by utilizing RTL parallelism
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Major challenge of FPGA
development
Requirement for extensive hand coding using
RTL language and manual tuning of thedesigned configurations

Need to repeat the processes of description
by HDL, generation of the configuration data,and downloading it to FPGA

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Our solution is …
to isolate the programming view from the detailed
implementation view

A new parallel reconfigurable architecture thatutilizes the two levels of control
The single stream microprogram specifies multinanoprograms and manages their execution
The multi-nanoprograms control a lot of finegrained operational units in parallel⇒ Our scheme will ease the development ofapplications without sacrificing the parallelism！
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Top view of parallel reconfigurable
architecture2017.2.4

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Internal organization of FUs
Micro-order from micro-level
Nano-sequencer

Nanoprogram Memory(NPM)
Nano-instruction
Operational Unit Array

Nano-orderInter-FU Network

Intra-FU Network
Register Array
REG

REG

REG

REG

REG

Scratchpad Memory
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Our image of using the two-level
microprogram – example sorting
μI
nP
μI

Sub-sorting operations by multi-nanoprograms

Merge operations by multi-nanoprograms

Data transfer between FUs
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Nanoprogram controlled sub-sorting
operation2017.2.4

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Advantages
Our scheme isolates the programming view
from the detailed implementation view andallows the flexibility of the underlying HW
Microprogram description and its translation
will be much better than the HDL description
and the logic compilation
Our scheme replaces many complex
sequence control circuits of FPGA design with
nanoprograms of horizontal type2017.2.4

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Conclusion
Based on our experience, we proposed a newparallel reconfigurable architecture that utilizes
the two levels of control
Following the original motivation of Wilkes, ourscheme isolates the programming view fromthe detailed implementation view and allows
the flexibility of the underlying HWThus, it will be much better for the application
developers than the use of an HDL and logic
compiler scheme.
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Thank you!

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