End-to-End Stochastic Computing
Mikko Lipasti

Carly Schulz

Department of Electrical andComputer Engineering
University of Wisconsin-Madison
Madison, WI
Email: mikko@engr.wisc.edu

Department of Electrical andComputer Engineering
University of Wisconsin-Madison
Madison, WI
Email: cschulz8@wisc.edu

Abstract—Embedded systems that require high performance
hardware for signal processing, optimization, and control havehistorically relied on optimized fixed-point algorithms deployedon low-power microprocessors and/or digital signal processors.
However, the sensing and actuation interfaces in such systems increasingly rely on oversampled, single-bit sigma-deltamodulated (SDM) representations of data inputs and control
outputs. Conventional computing substrates requires conversion
both on the input side and on the output side in order toeffectively interface with physical systems that utilize SDM representations. This position paper argues that embedded systems
should be designed to sense, process, compute, and actuate using
an approach called stochastic computing, which operates directlyon the oversampled SDM representation that is a natural fit forinterfacing with physical systems. Stochastic computing offers
numerous advantages in terms of datapath simplicity, robustness,
error tolerance, and support for variable precision, all of whichmake it an appealing approach for these embedded applications.
On the other hand, stochastic computing has a number oflimitations that make design of entire systems based on thisapproach quite challenging. This paper outlines some of thosechallenges and details our experiences with building such a
prototype system.

I. I NTRODUCTION
Presently, digital binary representation is the wellestablished standard for computation. As technology continues
to shrink in size, the circuits become more error-prone andunpredictable [1]. With the limits of the deterministic binary
computing, these unpredictable elements have to be guarded
against and often end up having a high hardware cost [2].
An alternative paradigm that was proposed in the 1960s
is stochastic computing. Stochastic computing is based on
probabilities and inherent uncertainties and works well withthe same uncertainties that make deterministic computing
more difficult [1]. Interest in stochastic computing was driven
by contemporary concerns about device and circuit reliability,
and was in fact rooted in Von Neumann’s even earlier workon probabilistic calculus. As device technology matured, theseconcerns were successfully addressed by improvements in
the reliability of the underlying devices and circuits usedas building blocks in computing systems, and so interest in
stochastic computing waned. More recently, similar reliability
concerns have been raised regarding emerging, post-CMOS
device technologies, and there has been a resurgence of interestin stochastic computing, including a number of proposals

for using it to replace conventional, deterministic computing
models for a broad array of applications.
Stochastic computing has a number of advantages as well as
drawbacks, and it is unlikely that it will serve as a wholesale
replacement for conventional computing. However, there are
domains where it is a compelling and very natural fit. This
paper focuses on a class of systems where the most naturalrepresentation for both input and output data is one that fits
well within the stochastic computing paradigm. Specifically,
we are interested in applying stochastic computing to replacea conventional data path in systems that required high performance hardware for tasks including signal processing, task
optimization, and control, but that also interface to the physicalworld using data representations that appear very similar to theprobabilistic bit streams utilized by stochastic computing.
Systems that interact with the physical world must bothsense their environment and control actuators that provide
them with the ability to manipulate physical elements. On thesensing side, oversampling, single-bit sigma-delta-modulated(SDM) representations have become increasingly popular due
to their robust performance and ease of implementation. Whilethey require higher data rates for comparable accuracy, thephysical design simplicity of both the ADC (single-bit SDM)
over more complex multi-bit ADCs, as well as the ease of
system design (single-bit, serial interconnects like SPI) has
made them the standard choice for applications like digitalaudio processing. Similarly, on the control side, pulse-widthmodulation (PWM) has largely replaced earlier, more complex
multi-bit or level-based digital-to-analog (DAC) approaches.
In the PWM approach, the control output also has only one
bit of DAC precision (it is either on or off), but the width ofthe pulses is modulated to provide a wider dynamic range.
Both SDM and PWM represenations are a natural fit forstochastic computing, since signals in these formats can beeasily consumed as inputs or generated as outputs by SC
datapaths.
This paper argues that the datapath simplicity, robustness,
error tolerance, and support for variable datapath precision
provided by the stochastic computing approach makes it anatural fit for such applications. We first discuss the history of
stochastic computing and the tradeoffs associated with using
it, and then describe a prototype system—a digital audio
equalizer—that we have implemented, and conclude the paper

with an assessment of the advantages of this paper along withsome thoughts on future work.
II. BACKGROUND
A stochastic representation of a number is a bit stream ofones and zeros where the desired transmission value is theprobability of whether a given bit is a one [3]. This methodof representation is inherently fault tolerant and provides anopportunity as we reach the limits of Moores law and explore
new technologies [4]. The field of stochastic computing has
gained attention recently for its applications in LDPC decoding, image processing, filters, and fault tree analysis [1].
A. Probabilistic Calculus
Although he is credited with the traditional computing
model and computer architecture as we know them today, Von
Neumann also began the gestation of stochastic computing
with his lecture on performing operations on probabilistic
values. He detailed his probabilistic calculus methods using
stochastic bit streams and developed automata to illustrate theirfunction. Using probabilistic methods, multiplication becomestrivial to implement at the gate level and is simply calculated
by feeding both inputs to an AND gate. As long as the inputs
are not correlated with each other which is handled by theirrandom nature, then the result of the gate will be, with highprobability, the result of the two values multiplied together[5]. The development and proof of such calculus shows that
exploiting stochastic numbers can result in drastically simpler
logic to perform operations such as multiplication, division,
etc.
Stochastic computing computes Bernstein polynomials witha block of adders and a block of multiplexers. Other functions
beyond polynomial functions can be mapped as approximations of a Bernstein polynomial. Stochastic functions canimplement any finite interval function that maps to anotherfinite interval [4].
B. Benefits Over Deterministic Computing1) Error Tolerant: Stochastic computing is quite error
tolerant and is well adapted to neural networks. It has several
applications in neural networks and image processing due toits parallel nature [3]. Since the bits are randomly set or not set
within a predetermined stream of bits, stochastic computing israther tolerant of soft errors, a flip of a bit, than traditional
computing where specific bits have much larger importance[4]. A more error tolerant method of computing requires lesshardware resources to be placed in error correcting or guarding
techniques. Stochastic bit encodings have been shown to generate correct outputs in applications such as image processing
even with soft error rates as high as 30% [6]. In stochastic
computing, the hardware is designed so as to allow errors
or without the over-designing mechanisms in use today andpushes the handling of errors up to the software level [4].

2) Circuit Size: Using Stochastic numbers allows the implementation of more complicated computations with very
simple logic and low gate cost as a result [7]. In addition to thelow gate cost multiplication and division, complex computations such as Taylor expansions of the exponential function andsquare-root function can be implemented with a small numberof gates under this computing model . Traditional deterministic
binary encoding requires much more complex logic elementsor relies on software to compute these functions[4].
3) Timing: Along with the decreased hardware cost, thesize often results in a shorter critical path which allows
a stochastic circuit to operate at higher clock frequencies[6]. This could result in a faster overall computation time,depending on the length of the bit stream that is being operated
on.
C. Traditional Challenges
There are some obstacles that prevented stochastic computing from proliferating. Some issues
1) Representation Cost: A large one is that there is a higher
cost in terms of bits required to represent the number witha certain degree of precision when compared to traditional
digital representations. That issue creates another, the costof multiplication in terms of gate invocations can be quite
high for stochastic representations as the number of bits
increases [8]. Longer streams of bits that are required forstochastic computing may end up consuming more power
than expected from a small and simple circuit. When using
stochastic computing for issues with low precision requirements, these representation costs can be somewhat mitigatedby the decrease in the length of the bit stream [7]2) Energy Consumption: Generating stochastic numbers
from the deterministic binary numbers consumes more energy
than leaving it in the deterministic form [7]. This is not an
issue when using SDM signals in the end-to-end stochastic
computing method. What does become an issue is the potentially higher energy cost from computing with long bit streams
of stochastic numbers [7].This is slightly alleviated by pushing
the burden of error correcting beyond hardware [4]. Energy
efficiency of the system is improved when the design can be
optimized for a non-zero error rate [2].
3) Timing: In serial encoding, computation time is a significant factor. (If a parallel implementation is being used,then area is the challenge here.) The length of the bit streams
needed to preserve precision leads to longer computation
times, even if the clock cycles can be shorter than in traditional
processors [4]. Stochastic computing cannot be pipelined
which makes high throughput difficult to attain [1].
4) Errors: There is error introduced through mapping thefunction to a Bernstein approximation in addition to thenormal quantization errors that one would expect in hardware[4]. Noise also contributes to the errors in this method ofcomputing. Since stochastic numbers are restricted to the[0,1] range, as the computation progresses the power of thescaled stochastic number decreases which leads to the SNR
decreasing as well. It should be noted that in the case ofmain advantage of using PDM input is the simple interface
circuitry and relatively low cost and ease of design of sigmadelta modulators that nevertheless provide very high audio
fidelity[11].

(a) An example of PDM of 100 samples of one period of a sine wave.
1s represented by blue, 0s represented by white, overlaid with the sine
wave.

Fig. 1: Prototype PDM Equalizer Board.

transient noise, stochastic computing tolerates the noise better
than binary computing [1].
These issues try to imply that stochastic representations may
be more costly than they are worth. We argue that the benefit ofeliminating conversion circuits makes stochastic computing acompetitive option in systems where both the input and output
are encoded in a stochastic way, such as SDM signals.
III. I MPLEMENTATIONThis section describes a system prototype that we have builtthat utilizes principles from stochastic computing to implementa system that processes audio signals end to end using apulse-density-modulated representation that is a natural fit forstochastic arithmetic. The prototype system board is illustrated
in Figure 1. The digital logic that utilizes stochastic computing
principles is implemented using a DE0-nano development
board from Terasic[9]. This board contains an Altera Cyclone
IV FPGA, as well as interface circuitry to the custom daughtercard, which contains a stereo class-D amplifier, connections
for two PDM digital microphones (shown attached to ribbon
cables behind the board), a 3.5mm audio input with PDM
ADC, as well as a set of potentiometer sliders used for controlling volume as well as five bands of frequency components
to realize an audio equalizer.
Pulse-density modulation is an approach for encoding timevarying signals that utilizes an oversampled, single bit torepresent complex waveforms[10]. Figure 2 shows two examples of sine waves at different frequencies encoded in
PDM format. PDM format has become very popular as arepresentation in the audio domain, and is very commonlyused in modern cellular phones, where the on-board PDM
microphones are attached to the rest of the system with a lowcost, single-wire PDM bus that it typically over-sampled ataround 3MHz. The PDM microphones contain a low-cost but
high precision sigma-delta modulator (SDM) [11] that converts
the analog audio signal captured by the MEMS microphone
into a series of PDM pulses. Our prototype includes two such
PDM microphones connected to the system, but also provides
a 3.5mm audio jack connected to a low-cost PDM ADC thatconverts standard analog audio from any sound device (e.g.
a portable MP3 player) to an oversampled PDM stream. The(b) A second example of PDM of 100 samples of two periods of asine wave of twice the frequency

Fig. 2: Examples of pulse-density modulation (aka SDM).
From [10]Class-D amplifiers are switching amplifiers that do not
attempt to utilize the linear region of a transistor for gain, as
in conventional amplifiers, but instead rapidly switch the gain
device (a MOSFET) based on a train of pulses which represents an audio signal encoded in the above PDM format[12].
Class-D amplifiers are extremely efficient and relatively easy
to design, since they do not suffer from the design complexities
and vulnerabilities of classic amplifiers that were extremely
sensitive to the transfer characteristics of the amplifying MOSFET.
In summary, we have built a protyping platform that takes
as input audio signals in PDM format, operates on them while
maintaining that representation, and drives output circuitry(class D amplifiers) that then drive actuators (speakers) thatcreate a physical audio signal. Within this context, the advantages of designing circuitry that maintains the original input
and output data representation are clear.
Figure 3 shows a block diagram of the digital circuitry wehave implemented on the Altera FPGA in our prototype system. As shown, it supports two identical audio channels (leftand right). Each channel provides volume control followed by
five bands of equalization targeted at frequencies ranging fromvery low (bass) to very high (treble), and allowing the user toattenuate or amplify these frequency bands to shape the final
sound.
In a conventional digital signal processing-based design,
the audio inputs would first be converted a pulse-code modulated PCM format with multiple bits of precisions for eachsample (e.g. 16-bit samples at 44KHz per channel for CDquality audio). This conversion task requires a fairly heavyweight cascaded integrator comb (CIC) filter to reconstruct alower-sample-rate multi-bit signal from the oversampled PDM
representation[13]. Following this conversion, standard digital
filtering techniques would be used to implement each of thefiltering stages shown, typically using cascaded biquad filters[14]. Such an implementation would require high-performance
digital signal processor cores capable of executing highprecision (at least 16x16=32, but preferably higher) multiplyaccumulate operations at a fast rate. Finally, after the final

Fig. 3: PDM Equalizer Block Diagram.

equalizer filter stage, the conventional design would require a
multi-bit digital-to-analog converter (DAC) in order to supply
an analog output to a conventional amplifier design. In our
prototype, this analog output would then be converted back to
a PDM bitstream to drive the gain MOSFET inside the class
D amplifier, leading to an additional level of inefficiency andadded noise from the redundant DAC-ADC stages.
Instead, we have implemented each filtering stage with adesign that is functionally equivalent to a biquad filter, bututilizes principles of stochastic computing to dramaticallysimplify the arithmetic datapath. For example, since the PDM
input stream represents values with a stream of 0/1 bits thatare numerically weighted as -1/+1, all digital multipliers in
the design have been replaced with simple, reduced-precisionadders. Furthermore, since even the oversampled data rate of
3MHz is still very low compared to the speed of modern
digital circuitry, even on FPGAs, these adders need not use
high-speed and power-hungry circuit topologies. In the end,
the datapath for realizing these filters is substantially simpler
and more energy-efficient than a conventional digital baseline.
Finally, since the filtering circuitry operates directly on
PDM format data, no input conversion or output conversion isneeded. Input from a PDM microphone is consumed directly,
while the final filter stage outputs can be used to directly drive
the gain MOSFETs in the class D amplifier.
IV. E VALUATION
We have implemented the design from the preceding section
and synthesized it to target the Altera Cyclone IV FPGA on
our DE0-nano development board [9]. To provide a reasonablebaseline of comparison, we have also designed a conventional
PCM-based design that can be synthesized for the same FPGA.
There are three key differences with respect to the design
shown in Figure 3:• The PDM digital input is downsampled (decimated) andconverted to 16-bit PCM format.
• The signal processing components (biquad filters) operateon the PCM data.

•

The outputs from the rightmost filters are converted from
PCM back to PDM via interpolation and sigma-delta
modulation.

These changes introduce additional overhead for the format
conversion, but also reduce the operating frequency of thesignal processing core substantially. We elaborate on thesechanges in the following paragraphs.
A. PDM to PCM Conversion
In our design, the PDM input arrives at a rate of 3.125MHz
per channel. All the filters in the system (both PDM-based
and PCM-based) are designed with a sampling frequency of
24.414KHz, corresponding to the input PDM sample rate divided by 128 1 . In order to maintain the same filter coefficientsfor our biquad filters, we need to downsample (by 128x) the
3.125MHz PDM input to a 24.414KHz rate. We used a lowcost, 3-stage cascaded integrator-comb (CIC) Hogenauer filter[15] modeled after the scheme described in a blog post fromCheshire Engineering [16], but implemented in Verilog rather
than C.
B. Biquad filters
The biquad filters in our design assume a sampling frequency of 24.414KHz, and are parameterized based on theequations found here [17]. The bass and treble filters are
configured as low shelf and high shelf, while the three midrange filters are configured as peak filters. Each filter can beparameterized to provide from -8dB to +8dB gain for eachband. In the PDM design, each biquad simply integrates thefive biquad coefficients, stored as 16-bit fixed–point values,
based on the five binary PDM inputs (the current input andthe last two inputs, as well as the last two outputs), andthen quantizes the integrated sum into a single PDM bit. The
delayed inputs and outputs are buffered for 128 time steps to1 This sampling frequency is clearly too low for high-fidelity audio applications, but we found it acceptable for our boombox scenario.

realize the 24.414KHz sampling rate; this delay memory ismapped to block RAMs on our FPGA prototype.
In the PCM baseline, we simply implement these biquadfilters in the conventional fashion, using fixed-point multiplication and addition. Since the performance requirement isvery low at our 24.414KHz sample rate, we implement themultipliers using a multicycle accumulator-based design. To
further reduce hardware cost in the baseline, we share thatsingle multiplier to integrate all five biquad terms (i.e. eachbiquad evaluation consists of 5x16=80 accumulate operations).
Finally, we quantize the output to 16 bits and use 16-bit
registers to implement the biquad’s delay buffers.
C. PCM to PDM Conversion
The biquad filter cascade generates a 16-bit filtered PCM
result at a rate of 24.414KHz. The final stage in our PCM baseline must convert this to a PDM representation at 3.125MHz todrive our class-D audio amplifier. This requires interpolation
by a factor of 128x, which we accomplish with a 3-stage
filter cascade, where each stage uses 3rd-order CIC filters thatinterpolate at rates of 2x, 8x, and 8x, respectively, for a total
upsampling of 128x. The final interpolated results are then fed
to a second-order sigma-delta modulator.2 , which generates
a PDM stream at 3.125MHz. The cascaded CIC filters inthis conversion step are surprisingly expensive, as the integer
datapath in each must be sized to avoid overflow, requiring an
additional bit of precision for each order and each stage.
D. Area results
In order to assess the area cost of the proposed PDM design,
we synthesized it in the Altera Quartus 16.1 environment.
Table I reports the number of logic elements (LEs) requiredby the biquad filters, by the conversion logic (in the baseline
design), and everything else (Misc, which includes control
logic for reading equalizer settings and parameterizing thebiquads accordingly, etc). The relative LE breakdown was
obtained from the synthesis report (pre-place and route) andthe LE counts shown are normalized to the final post-PR LE
count.
As can be seen from Table I, the overhead of format conversions in this environment is substantial (39% of the total area
required for the baseline PCM design). This is particularly trueof the PCM to PDM conversion block, which requires widearithmetic and delay elements to implement the multi-stage
CIC filter (progressively wider in the later stages). The PDM
biquad filters are about 20% larger than the PCM baseline.
Since both designs are based on accumulator-style multipliers
using just a single adder, this overhead is mostly caused by the
PDM quantizer, which is a first-order sigma-delta modulator.
This requires an additional adder/subtractor and register for
carrying over quantization error, whereas the PCM quantizer
simply truncates the low order bits. However, despite themodest area increase per filter, the PDM design is attractivefrom an efficiency perspective: the vast majority of the FPGA
2 Again, inadequate for a high-fidelity audio solution, but adequate for aboomboxresources are consumed for useful work (filtering), rather thanformat conversion. The majority of the RAM in both designs isused by the biquad parameter lookup RAM (16kb); this is used
to store the biquad parameters that are chosen for each filter
based on the equalizer settings. The PDM biquads also utilize
RAM blocks for their delay memories, which requires 3kb ofstorage across all ten biquads. This leads to an increase of
19% in overall RAM consumption, and highlights the storage
inefficiency of unary representations, which is one of the major
shortcomings of PDM-based processing.
It is also worth pointing out that both the baseline PCM
and proposed PDM designs are first-pass efforts at building aworking prototype, and there are numerous hardware optimizations that could significantly affect the area and performanceof the designs. Exploration of such optimizations is left to
future work.
V. C ONCLUSIONS AND F UTURE W ORKThis paper argues that stochastic computing can form acompelling computational substrate for systems where inputs
and outputs are encoded as a single-bit stream. We havebuilt a prototype system that operates directly on such a
bit stream to implement an audio equalizer. This system
avoids the overheads of input and output conversion that aremandatory in conventional digital signal processing datapaths
that operate on pulse-code-modulated (PCM) data, and also
simplifies the datapath hardware, since arithmetic operations
like multiplication can be implemented at much lower cost on
serial PDM bitstreams. Overall, with respect to a conventional
PCM baseline equalizer, the PDM design reduces logic area
by 32%, but does increase RAM usage by 19%.
Evaluating the energy efficiency of the PDM design presentsa challenge; the approximate power modeling provided by the
Quartus tool relies on a single activity rate parameter andreturns power results for the two designs that are 1) dominatedby the static power of the chip, and 2) differ only marginally interms of dynamic power. In future work, we will synthesize
these designs with a standard-cell design flow and evaluateenergy efficiency with sufficient accuracy to determine any
relative benefit provided by the PDM design.
As described and implemented, the cascaded biquad approach for implementing an equalizer suffers from additivenoise; that is, any noise introduced by the first filter is amplified by subsequent stages. When multiple filters are active,
this can lead to very poor audio quality. To avoid this problem,an alternative architecture that operates the filters in paralleland mixes the output of each based on the equalizer settings
should lead to a better result. Design of such an alternative isalso left to future work.
Generalizing from this experience with a specific system,
we would argue that future designs for embedded systems
that match these characteristics—systems where the input
and output are most naturally represented as a serial oversampled bitstream—stochastic computing forms a natural andvery appealing foundation for dramatically reducing cost andcomplexity. We are currently working on prototyping twoCategory
PDMtoPCM
Biquads
PCMtoPDM
Misc
Total

PCM LE
196 ( 5%)2052 (50%)
1386 (34%)
444 (11%)4078

PDM LE0 ( 0%)
2431 (60%)
0 ( 0%)
327 (08%)
2758 (68%)

PCM RAM
0 (0%)
0 (0%)
0 (0%)
16kb (100%)
16kb (0%)

PDM RAM
0 (0%)
3kb (19%)
0 (0%)
16kb (100%)19kb (119%)TABLE I: Area Cost of PDM vs. PCM Equalizer Design

such additional example systems as further evidence for thisassertion. First, we are building a drone system that will
rely on computer vision algorithms for object localization andoptical flow to provide a guidance system for the drone. In
this scenario, the visual input to the drone will be represented
as serial bitstreams that represent features extracted from thedrone’s camera. Our current-generation drone hardware still
relies on conventional pixel-based input from the camera, but
in the future we expect to transition to a camera system similar
to the Inilabs Digital Vision Sensor [18], which reports visual
input using spike trains that strongly resemble single-bit bitstreams. Similarly, the control output from the drone’s onboard
guidance system is a pulse-width modulated (PWM) streamthat controls the speed of each of the drone’s four fan motors.
Hence, this is a system where the inputs and outputs are mostnaturally represented as streams of single-bit binary data, so
we are investigating how best to implement the entire datapathof the drone’s flight controller using stochastic computing-likecircuitry that operates directly on this data type. Second, weare prototyping a robotic control arm system that relies onsolving the inverse kinematics problem to position the roboticarm at a target location[19]. Here again, the visual input tothe robotic controller will come from a camera that ideallyutilizes the Inilabs sensor[18], while the output is once again
a PWM stream that drives rotational actuation in each of therobot arm’s joints. Solving the inverse kinematics to determine
the correct angular velocity for each joint requires matrix
division, which will present a series of interesting challenges
for deployment on stochastic circuits.
In summary, we argue that stochastic computing can offer
numerous advantages in terms of datapath simplicity, robustness, error tolerance, and support for variable precision, allof which make it an appealing approach for these embedded
applications where the most natural representations for inputs,
outputs, and computation are serial oversampled bistreams.
VI. ACKNOWLEDGMENTS
The demonstration board for this project was designed andbuilt by Eric Hoffman. Chenxiao Guan, the teaching assistantfor the Fall 2016 section of ECE 551 (Digital System Design
and Synthesis), as well as all of the 56 enrolled students,
waited patiently for the final specification for this effort andfaithfully implemented it as their course project (thank you!).
This work was supported in part by NSF grant CCF-1615014.
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