MM74C922 • MM74C923
16-Key Encoder • 20-Key Encoder
General Description
The MM74C922 and MM74C923 CMOS key encoders provide all the necessary logic to fully encode an array ofSPST switches. The keyboard scan can be implemented
by either an external clock or external capacitor. Theseencoders also have on-chip pull-up devices which permit
switches with up to 50 kΩ on resistance to be used. No
diodes in the switch array are needed to eliminate ghostswitches. The internal debounce circuit needs only a single
external capacitor and can be defeated by omitting thecapacitor. A Data Available output goes to a high level
when a valid keyboard entry has been made. The Data
Available output returns to a low level when the entered
key is released, even if another key is depressed. The Data
Available will return high to indicate acceptance of the new
key after a normal debounce period; this two-key roll-overis provided between any two switches.

An internal register remembers the last key pressed evenafter the key is released. The 3-STATE outputs provide foreasy expansion and bus operation and are LPTTL compatible.

Features■ 50 kΩ maximum switch on resistance■ On or off chip clock■ On-chip row pull-up devices■ 2 key roll-over■ Keybounce elimination with single capacitor■ Last key register at outputs■ 3-STATE output LPTTL compatible■ Wide supply range:

3V to 15V

■ Low power consumption

Ordering Code:
Order Number
MM74C922N

Package Number
N18A

Package Description
18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

MM74C922WM

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

MM74C923WM

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

MM74C923N

N20A

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagrams
Pin Assignment for SOICPin Assignment for DIP

Top View
MM74C922
Top View
MM74C922© 1999 Fairchild Semiconductor Corporation

DS006037.prf

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MM74C922 • MM74C923 16-Key Encoder • 20-Key Encoder

October 1987
Revised January 1999

MM74C922 • MM74C923

Connection Diagrams (Continued)
Pin Assignment for
DIP and SOIC Package

Top View
MM74C923

Truth Tables(Pins 0 through 11)
SwitchPosition01234567891011

Y1,X1 Y1,X2 Y1,X3 Y1,X4 Y2,X1 Y2,X2 Y2,X3 Y2,X4 Y3,X1 Y3,X2 Y3,X3 Y3,X4DA

A0

10

10

10

1010T

B

0011001100

111AC000011110000O

D000000001111UE (Note 1)

000000000000T(Pins 12 through 19)
SwitchPosition

1213

14

15

Y4,X1

Y4,X2

Y4,X3

Y4,X4

16

171819

A

A

010

1010T

B

001

1001

1A

C

1

1

1

1

0000

O

D

11110000UE (Note 1)

0000

1

1

1

1

Y5(Note 1), Y5 (Note 1), Y5 (Note 1), Y5 (Note 1),
X1
X2
X3
X4

DT
Note 1: Omit for MM74C922

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MM74C922 • MM74C923

Block Diagram

3

www.fairchildsemi.comMM74C922 • MM74C923

Absolute Maximum Ratings(Note 2)

Operating VCC Range

VCC − 0.3V to V CC + 0.3V

Voltage at Any Pin−40°C to +85°C

Storage Temperature Range−65°C to +150°C(Soldering, 10 seconds)

Dual-In-Line

700 mW
500 mW

260°C

Note 2: “Absolute Maximum Ratings” are those values beyond which thesafety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.

Power Dissipation (P D)
Small Outline

18V

Lead Temperature

Operating Temperature Range
MM74C922, MM74C923

3V to 15V

VCC

DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise specified
SymbolParameterConditions

Min

TypMaxUnits

CMOS TO CMOS
VT+VT−VIN(1)Positive-Going Threshold Voltage

VCC = 5V, IIN ≥ 0.7 mA

3.0

3.6

4.3

V

at Osc and KBM Inputs

VCC = 10V, IIN ≥ 1.4 mA

6.0

6.8

8.6V

VCC = 15V, IIN ≥ 2.1 mA

9.01012.9V

Negative-Going Threshold Voltage

VCC = 5V, IIN ≥ 0.7 mA

0.7

1.4

2.0

Vat Osc and KBM Inputs

VCC = 10V, IIN ≥ 1.4 mA

1.4

3.2

4.0

V

6.0

Logical “1” Input Voltage,
Except Osc and KBM Inputs

VIN(0)Irp

VOUT(1)

VOUT(0)

Ron

ICC

2.1

5

VCC = 5V

3.5

4.5

V
V

VCC = 10V

8.0

9

VCC = 15V

12.5

13.5

VV

Logical “0” Input Voltage,

VCC = 5V

0.5

1.5

V

Except Osc and KBM Inputs

VCC = 10V

12V

VCC = 15V

1.5

2.5

VRow Pull-Up Current at Y1, Y2,

VCC = 5V, VIN = 0.1 VCC−2−5µA

Y3, Y4 and Y5 Inputs

VCC = 10V−10−20µA

VCC = 15V

−22−45µA

Logical “1” Output Voltage

Logical “0” Output Voltage

VCC = 5V, IO = −10 µA

4.5

V

VCC = 10V, IO = −10 µA

9V

VCC = 15V, IO = −10 µA

13.5

V

VCC = 5V, IO = 10 µA

0.5

V

VCC = 10V, IO = 10 µA

1V

VCC = 15V, IO = 10 µA

1.5

V

Column “ON” Resistance at

VCC = 5V, VO = 0.5V500

1400

Ω

X1, X2, X3 and X4 Outputs

VCC = 10V, VO = 1V

300

700

Ω

VCC = 15V, VO = 1.5V

200

500

Ω

VCC = 5V

0.55

1.1mA

Supply Current
Osc at 0V, (one Y low)

IIN(1)VCC = 15V, IIN ≥ 2.1 mA

Logical “1” Input Current

VCC = 10V

1.1

1.9mA

VCC = 15V

1.7

2.6mA

VCC = 15V, VIN = 15V

0.005

1.0µA

at Output Enable
IIN(0)

Logical “0” Input Current

VCC = 15V, VIN = 0V

−1.0−0.005µA

at Output Enable
CMOS/LPTTL INTERFACE
VIN(1)

Except Osc and KBM Inputs

VCC = 4.75V

VIN(0)

Except Osc and KBM Inputs

VCC = 4.75V

VOUT(1)

Logical “1” Output Voltage

VCC − 1.5

V
0.8

V

IO = −360 µA
VCC = 4.75V

2.4

V

IO = −360 µA
VOUT(0)

Logical “0” Output Voltage

IO = −360 µA
VCC = 4.75V

0.4

IO = −360 µA

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4V

Symbol(Continued)

Parameter

Conditions

Min

TypMax

Units

−1.75

−3.3mA−8−15mA

1.75

3.6mA

816mA

Min

TypMaxUnitsns

OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
ISOURCEISOURCE
ISINK
ISINK

Output Source Current

VCC = 5V, VOUT = 0V,(P-Channel)

TA = 25°C

Output Source Current

VCC = 10V, VOUT = 0V,(P-Channel)

TA = 25°C

Output Sink Current

VCC = 5V, VOUT = VCC,

(N-Channel)

TA = 25°C

Output Sink Current

VCC = 10V, VOUT = VCC,

(N-Channel)

TA = 25°C

AC Electrical Characteristics (Note 3)
TA = 25°C, CL = 50 pF, unless otherwise noted
Symboltpd0, tpd1

t0H, t1H

tH0, tH1

ParameterConditions

Propagation Delay Time to

CL = 50 pF (Figure 1)

Logical “0” or Logical “1”

VCC = 5V

60150

from D.A.

VCC = 10V

3580

ns

VCC = 15V

2560

ns

Propagation Delay Time from

RL = 10k, CL = 10 pF (Figure 2)

Logical “0” or Logical “1”

VCC = 5V, RL = 10k

80

200

ns

into High Impedance State

VCC = 10V, C L = 10 pF

65150

ns

VCC = 15V50110

ns

Propagation Delay Time from

RL = 10k, CL = 50 pF (Figure 2)

High Impedance State to a

VCC = 5V, RL = 10k100250ns

Logical “0” or Logical “1”

VCC = 10V, CL = 50 pF

55125

ns

VCC = 15V

4090

ns

7.5

pF

CIN

Input CapacitanceAny Input (Note 4)

5

COUT

3-STATE Output Capacitance

Any Output (Note 4)

10pF

Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: Capacitance is guaranteed by periodic testing.

5

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MM74C922 • MM74C923

DC Electrical Characteristics

MM74C922 • MM74C923

Switching Time Waveforms

T1 ≈ T2 ≈ RC, T3 ≈ 0.7 RC, where R ≈ 10k and C is external capacitor at KBM input.

FIGURE 1.

FIGURE 2.

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Typical Irp vs VIN at Any Y Input

Typical Ron vs VOUT at Any X Output

Typical FSCAN vs COSC

Typical Debounce Period vs CKBM

Typical Applications
Synchronous Handshake (MM74C922)

Synchronous Data Entry Onto Bus (MM74C922)

The keyboard may be synchronously scanned by omitting the capacitor atosc. and driving osc. directly if the system clock rate is lower than 10 kHz

Outputs are enabled when valid entry is made and go into 3-STATE when
key is released.
The keyboard may be synchronously scanned by omitting the capacitor atosc. and driving osc. directly if the system clock rate is lower than 10 kHz

7

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MM74C922 • MM74C923

Typical Performance Characteristics

MM74C922 • MM74C923

Asynchronous Data Entry Onto Bus (MM74C922)

Outputs are in 3-STATE until key is pressed, then data is placed on bus. When key is released, outputs return to 3-STATE.

Expansion to 32 Key Encoder (MM74C922)

Theory of Operation
going low also initiates the key bounce circuit timing andlocks out the other Y inputs. The key code to be output is acombination of the frozen counter value and the decoded Yinputs. Once the key bounce circuit times out, the data islatched, and the Data Available (DAV) output goes high.

The MM74C922/MM74C923 Keyboard Encoders implement all the logic necessary to interface a 16 or 20 SPST
key switch matrix to a digital system. The encoder will convert a key switch closer to a 4(MM74C922) or5(MM74C923) bit nibble. The designer can control both thekeyboard scan rate and the key debounce period by altering the oscillator capacitor, COSE, and the key bouncemask capacitor, CMSK. Thus, the MM74C922/MM74C923’s
performance can be optimized for many keyboards.

If, during the key closure the switch bounces, Y1 input will
go high again, restarting the scan and resetting the key
bounce circuitry. The key may bounce several times, but assoon as the switch stays low for a debounce period, theclosure is assumed valid and the data is latched.

The keyboard encoders connect to a switch matrix that is 4rows by 4 columns (MM74C922) or 5 rows by 4 columns(MM74C923). When no keys are depressed, the row inputs
are pulled high by internal pull-ups and the column outputs
sequentially output a logic “0”. These outputs are open
drain and are therefore low for 25% of the time and otherwise off. The column scan rate is controlled by the oscillator input, which consists of a Schmitt trigger oscillator, a 2bit counter, and a 2–4-bit decoder.

A key may also bounce when it is released. To ensure thatthe encoder does not recognize this bounce as another keyclosure, the debounce circuit must time out before anotherclosure is recognized.
The two-key roll-over feature can be illustrated by assuming a key is depressed, and then a second key isdepressed. Since all scanning has stopped, and all other Y
inputs are disabled, the second key is not recognized until
the first key is lifted and the key bounce circuitry has reset.

When a key is depressed, key 0, for example, nothing will
happen when the X1 input is off, since Y1 will remain high.
When the X1 column is scanned, X1 goes low and Y1 will
go low. This disables the counter and keeps X1 low. Y1

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The output latches feed 3-STATE, which is enabled when
the Output Enable (OE) input is taken low.

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MM74C922 • MM74C923

Physical Dimensions inches (millimeters) unless otherwise noted

18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N18A

20-Lead Plastic Small Outline I.C. Package (M)Package Number M20B

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MM74C922 • MM74C923 16-Key Encoder • 20-Key Encoder

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” WidePackage Number N20A

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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.