A Survey of Low Power Techniques for Efficient
Network-on-Chip Design
Emmanuel Ofori-Attah, Michael Opoku Agyeman
Faculty of Art, Science and Technology
Univeristy of Northampton, UK.

Abstract—Power consumption continues to be a challenge
for designers as the complexity of NoC increases. The scaling
down of technology towards the deep nanometer era will only
cause an increase in the amount of power NoC components
will consume. Therefore, low power design solution is one of
the essential requirements of future NoC-based System-on-Chip(SoC) applications. Several techniques have been proposed over
the years to improve the performance of the NoCs, trading-off
power efficiency; particularly power hungry elements in NoC
routers. Power dissipation can be reduced by optimizing therouter elements, applying architecture saving techniques andcommunication links. This paper presents recent contributions
and efficient saving techniques at the router, NoC architecture
and Communication link level.

I. I NTRODUCTION
The poor scalability of bus-based architectures with technological growth has resulted in the emergence of the Networkon-Chip (NoC) paradigm as the communication standard for
SoC [1]. The main idea of NoC is to allow simultaneoususe of wires across a network, thus enabling parallelism,
whereas in bus-based architectures, only one communication isachieved at a time. Figure 1 is an image of a typical 2D NoCbased shared-memory chip multiprocessor (CMPs) comprisedof 36 nodes. Each node is comprised of a core, private level1 instruction and data caches, a second level cache which
could either be shared or made private, a router and logic.
Connection is established between each node through therouters using links. Consequently, NoC’s enrichment supply ofparallelism impart high throughput, high bandwidth, and low
latency [2]. However, switching activities and leakage powerof the resources increases the on-chip power consumption.
Furthermore, prior investigations suggest that as transistor
size shrinks with technology, leakage power contributes to a
substantial amount of NoC power consumption; particularly
in NoC Routers [3], [4]. NoC router components consume asignificant amount of power yet enhance the network performance. Nonetheless, reducing leakage power is proving to bea problem for designers as the complexity of NoC increases.
The growth in core count increases the number of on-chip
resource. For this purpose, existing work trade-off network
performance for power efficiency. Some have even resulted
to the removal of power-hungry elements such as buffersand virtual channels. However, this results in impecunious
performances.
Consequently, this rapid growth of technology does not
only affect the power consumption in routers, but also impose

heavy delays on their implemented SoC design. Over thelast few years, existing 2D NoC architectures have not beenable to comprehend the demands of modern SoC design. As
more resources are added, hop distance caused by additional
wire length adds to the power consumption of the NoC,
causing a negative effect on the performance. Therefore,
efficient techniques are required to balance network and power
performance. Particularly, to achieve this, we have categorized
NoC into three main areas and have investigated power saving
technique that can be applied in these areas. The rest of
the paper is organised as follows. Section 3 discusses efficient techniques for power in NoC architectures. Section IV
provides low-power techniques for communication links andfinally, section V concludes the paper.
II. ROUTER A RCHITECTURE
Routers are the main components in NoC. A traditional
single-stage router architecture consists of an arbiter, buffer,crossbar, virtual channels, input, and output ports (Figure 1c).
As powerful and as effective as NoC is, research confirms
that, it is responsible for consuming 40% of chip power [5],[6]. Majority of this consumption is caused by power hungry
elements in routers such as the buffers and crossbar. Buffers
are embedded into routers as temporal storage for packets
while awaiting transmission. A study conducted by [7] revealthat 33% of dynamic power in routers are consumed by the
buffers. Particularly, input buffers are considered to consume
45% of router power and occupies 15% of area [8]. On theother hand, the use of large buffer size expands the power
consumption and area overhead whereas a reduction of it
diminishes the overall performance of the network. Powerconsumption in the crossbar is solely dependent on the of
the number of PEs employed. Recently, the increase of PEs
in NoC has caused a major increase in the size of crossbars
resulting in high power consumption, scalability issues, andlarge area [9]. Consequently, Intel’s TeraFLOPS Processor [10]and MIT RAW [11] crossbars constitutes to a combined 40%of router power.
Therefore, to reduce the power consumption of the routers,
existing work have utilized novel techniques to improve power
efficiency, the crossbar size, arbiter, and buffer designs. For
this purpose, this paper focuses on optimized power saving
techniques at the buffer and crossbar level.

Fig. 1. 2D NoC-based CMP

A. Bufferless Routers and Buffered Routers
The power demand of modern SoC design is proving to
be a struggle for designers. NoC is expected to provide
high bandwidth, high throughput and low latency while still
operating at a low power. This expectation however is proving
to be design constraint for designers because of NoC components. Of all the power consuming elements there are in
NoC routers, buffers and crossbars are the most consuming.
Bufferless routers such as CHIPPER [12], SCEPTER[13] andMulti-ejection [14] ports have therefore been proposed forward
as an alternative solution to combat this challenge. These
two-different types of buffers are often disputed about theirsignificance to the overall performance on NoC. While many
prefer buffered routers, its high-power consumption and large
area overhead often leads to the implementation of bufferlessrouters. In Bufferless routers, buffers are substituted withflow control deflection algorithms to transmit packets as soon
as they arrive. Therefore, low power and low area pipeline
registers are the only buffers employed in bufferless routers[15]. Consequently, the implementation of bufferless routers
trade-off network performance for low power making it a highcandidate to replace buffers.
On the other hand, many contests that bufferless routers attimes contradicts its main target of providing low power. For
example, CHIPPER [12] has its algorithm built based on a
permutation tree. Permutation trees on the hand, are known tobe high consumers of power [16].
Furthermore, because they are comprised of single ejection
ports, bufferless routers suffer extensively from performancedegradation when the network traffic reaches its peak. In
addition, due to their inability to house packets, contention
materialises when multiple flits arrive at the same time andcontest to eject at the same node. Eventually, one flit will

be designated an output port while the other is diverted ona different route causing additional latency and eventually
resulting in the packet to never reach its destination (Livelock).
Therefore, Livelock is considered a major drawback and problem for bufferless routers because, at some point, the network
will saturate and some packets will be deflected of course.
This high deflection rates in the NoC contributes to bandwidthissues, high latency, and an increase in power consumption.
Consequently, various techniques have been proposed forward to resolve latency and livelock issues in bufferlessrouters. CHIPPER employs an algorithm which prevents contention by allocating output ports to packets based on theirpriority. Even though CHIPPER promises a reduction of 54%
less power than conventional buffered routers, it is not evident
that livelock is permanently eliminated. Whereas, input bufferswith embedded virtual channels (VC) can be deployed to allow
simultaneous transmission without a packet being thrown ofcourse.
To tackle the deflection rates in Bufferless routers, Fenget al. proposed the multi-ejection port router [14] while
Xiang et al. [17] proposed Deflection Containment (Dec). The
bufferless routers used by Feng can be optimized to have fourejection ports which in effect will reduce the contention rates
and latency. However, if more than four flits arrive, livelock
can still materialise. Furthermore, an extension of the ejection
ports will lead to an increase in the size of the crossbars
resulting to more power being consumed in NoC. Xiang on thehand proposed an architecture which consists of virtual routers.
These virtual routers allow the joining of sub routers. An extra
link has been added to each virtual router to join sub networks
together. The link allows packets which has been denied accessin the current network to be transmitted to neighbouring sub
networks to contest for an ejection port.

Moreover, bufferless routers present a great idea for reducing power however the employment of buffered routers tradeoff area and power consumption to prevent deadlock, livelock,and high throughput. For this purpose, we focus on presenting
techniques which can applied in buffered routers to reduce thepower consumption.
B. Low Power Buffered Router Techniques
1) Power-Gating the resources in the Router Architecture:
Power-gating (PG) is an effective technique applied to manyarchitectures to manage the amount of power generated by
NoC resources. Their use at the router architecture level
reduces the amount of static power dissipated in circuits which
are rarely used. Many proposed architectures split resources
into different parts and de-activate them based on the network
traffic. The following authors have divided VCs into different
groups; each group can be switched-off depending on the
network traffic and performance.
Muhammad et al. [18] introduces the Traffic-Based Virtual
Channel Algorithm. The algorithm divides the VCs in a switch
port into three cells. Anyone of these three cells can be
activated and deactivated based on the network traffic andcongestion. Thus, allowing resource power to be saved when
they not being used. Similarly, DimNoc is proposed by [19]to effectively manage PG operations. VCs are grouped anddivided into levels. The lower level of the VCs is designedwith SRAM and the higher level with SST-RAM. The lower
level can be either be powered on or left in a drowsy state. The
high-level VC’s are utilized when there is heavy traffic. [20]employs a PG control unit which after completing a certain
amount of cycles, it disables buffers from routers which are
idle.
PG may be power efficient, however, an excessive useof it can have a diminishing impact on the performance ofa network. Recently, many proposed architectures focus on
saving power by using PG to disable resources however, theyignore the problems that arise when a packet encounters anidle router. According to [21], PG architectures are prone
to deadlock. This is because, idle routers block all paths
it intersects with, causing packet transmission to be halted
resulting in performance degradation (wake-up latency). In
addition to this, the constant turning on and off routers leads
to non-negligible power overhead. In such an infrastructure,
wake-up signals can be employed to either alert powered-off
routers or routers which are scheduled to be powered-off ofan incoming packet. For this purpose, Chen et al. proposed
Power Punch, an optimized technique which sends wake-up
signal 3 hops ahead, ensuring intersecting routers which are
powered-off are activated in time to avert latency [22].
2) Different types of Buffers: Another novel technique isto use alternative buffers other than input buffers. Kodi etal. proposed iDeal [23], an architecture which employs theuse of dual-function links. Unlike static buffer allocation, theproposed architecture uses a dynamic router buffer allocation
to assign incoming flits to any free buffer. iDeal permits the
reduction in buffer size to decrease power consumption by

employing existing repeaters to function as buffers during network congestion. Similarly, DiTomaso et al. proposed QORE
[7], an architecture which improves power consumption using
power-efficient Multi-Function channel buffers (MFC) andenhances the performance through reversible links. The useof MFC enables the channel buffers to be utilized instead of
the buffers in the routers. [24] deals with power consumption
by replacing the conventional SRAM with 3T N eDRAM.
Significantly, buffer area was reduced by 52% and power by
43%.
3) Reduction in the pipeline stages: Packets traverse aroundthe network through many pipeline stages: Buffer Write (BW),Route Computation (RC), Virtual Channel Allocation (VA),
Switch Allocation (SA), and Switch Stage (ST).
Postman et al. [25] highlights that, buffers are not effectively
optimized in existing architectures. Particularly, little emphasis
is placed on path availability and network congestion whichcauses additional pipeline stages. The implementation of analgorithm which considers these challenges can help packets
evade the buffering stage. Consequently, they proposed SWIFT
NoC. The SWIFT NoC achieves low power consumption by
allowing flits which bypass the buffering stage to do so in
one cycle: Escaping the need for read/write power. Bypassing
the buffering stage results in the use of fewer buffers and lesspower. Similarly, [26] proposes virtual circuit switching: A
hybrid scheme which combines circuit and packet switching toallow flits to traverse through the network with only one stage.
In contrast with the virtual point to point connections, 6.8%
is the decrease in latency and 11.3% in power respectively.
C. Crossbar Switches
A crossbar switch is composed of individual switches arranged in a matrix form between several inputs and outputs.
Crossbar switches can be categorized into two groups, single
stage and multi stage. Figure 1.c depicts a typical n × n
Crossbar switch in a single-stage router architecture.
1) Crossbar size: To achieve low power consumption andsmall area, existing work focuses on splitting large crossbars
into smaller ones. Kim et al. [27] proposed a router architecture composed of two crossbars. In the proposed routerarchitecture, Smaller crossbars are employed to reduce the sizeof the Virtual Channel Allocator (VA), Switch Arbiter units(SA) and shorter logic depth. Similarly, Park et al. propose
an optimized crossbar [28] which combines decompositionand segmentation to effectively reduce power consumption
by 35%. The crossbar has been disassembled in two small
crossbars to reduce area and power. However, in large scale
networks, there will an increase in average latency.
Recently, multi-stage crossbars such as the Clos and Benes
network [29], [30], [31] has been proposed. Multi-stage crossbars provide low power and smaller area. Yikun Jiang conducted a study on Circuit design [32] and concluded that the
Clos networks outperform their counterparts (Benes[31] andSingle-stage Crossbars) in several ways. In the Clos network,
there is a reduction in the number of logic units used. The

Benes network suffers from 65% delay in timing and lesspower in Clos consumed because of the size of crossbars.
Naik et al. proposed a heterogeneous NoC [33] embedded with circuit switched routers composed of buffered andbufferless routers and a 3-stage CLOS network. In comparison
to crossbar switch of the same size, the results of this is areduction of 26% in power consumption and 32% in area.
However, circuit switched network causes additional latency
when a transmission is established between a source and its
destination.
Bansal et al. proposed a power efficient 3-Dimensional
Crossbar Switch with 7 input ports and 7 output ports. Although the 3D routers in the architecture consists of more
ports compared to 2D routers (5 input ports and 5 Output
ports), the crossbar consumes the same amount of power yet
offers high throughput and low latency because of the extra
two ports (up and down).
2) Switching Algorithm: In theory, there are two different
types of routers; circuit switched routers and packet switchedrouters. In packet switched routers, data is encoded into
packets and routed individually through the network. Circuit
switching routers on the hand establishes a connecting between
the source and destination and specifically allocates resources
which will be used for transmission [34]. In Circuit switchingrouters, there is guaranteed throughput because all packets canbe transmitted at the same time without delay in any router
however, there is an increase in latency. This is because during
the transmission process, the resources allocated cannot be
accessed.
For this purpose, a switching mechanism has been proposed
to effectively use the benefits of packet switching and circuit
switching [35]. In this architecture, messages are split into
different groups: High priority and Low priority. High priority
messages are transmitted using circuit switching and low
priority messages are transmitted using packet switching. The
employment of these two mechanism allow power rails to bedisconnected and PG to be used to disconnect parts of therouter which are not used during a transmission.
III. L OW N ETWORK A RCHITECTURE
Novel NoC architectures have been proposed to reduce
the average packet latency while increasing the throughput.
However, this usually at the expense of power consumption. To
combat the challenges imposed by these power-hungry NoCs,
various architectures have been proposed.
The exponential increase in the number of cores in multicore over the last decade has resulted in the emergenceof Three-Dimension (3D) NoC as the platform for on-chipcommunication. 3D NoC allows multiple silicon layers to
be stacked together to not only enhance the throughput andlatency, but also to reduce power consumption [36], [37]. In
3D NoC, the lengthy wires are replaced with short throughsilicon vias (TSVs) to minimize the number of hops it takes
for a packet to traverse through the network. Particularly,
the increase in the number of connectivity in 3D Integrated

Circuits allows the transmission of more messages around the
network [38].
Debora Matos et al. proposed the 3D HiCIT, an architecture
comprised of two hierarchical levels with a mesh topology at
the top level. In comparison with the traditional 3D-SPIN and
3D Mesh topologies, the proposed architecture reduces theaverage latency to 50% and 54% respectively, with the 3DSPIN been the latter [39]. In addition to this, the architecture
is comprised of a crossbar and low-cost routers. Compared tothe 3D-SPIN and 3D-BFT, the proposed architecture uses less
TSVs.
However, limitations such as power density caused by thechip size, the cost of TSV and its defects [40], [39] prevents
3D NoC from reaching its potential. For this purpose, Nayak et
al. [41] recommends the use of monolithic 3D. One approachto reduce power consumption is to use fewer buffers at therouter port [42], [43], [44]. Similarly, Fang et al. proposed
RRCIES, an architecture based on a mesh topology. RRCIES
allows multiple cores to be connected between one router. As
a result, hop distance is reduced. The use of fewer routers
constitutes to a reduction in power hungry components suchas buffers, crossbar, switches, and virtual channels [45].
Another alternative is to employ PG. The study of verticalslit field effect transistors led to the proposal of a 3D Hybridarchitecture in [46]. PG and clock gating is employed inthis architecture to enable different level of buffers to be deactivated. The proposed architecture splits the input buffers
into three 3. Each input port is designed to access all threelevels and permit any virtual channel destination to be chosen.
In addition, the buffers from ports which are not being used
are shared among busy ports.
For further enhancement in NoC architectures, Wireless
NoC (WiNoC) has been proposed to overcome the bottleneck
and limitations 3D NoCs. WiNoC reduces the hop-countbetween routers. The implementation of WiNoC allows thetransmission of messages with a single hop, long range wireless links [47]. In such WiNoC architectures, communications
over short distances materialise through the wired connections
and long range communication occur through the wirelesslayer [48]. However, conventional WiNoC only permits one
active wireless communication. During this period, the remaining wireless interfaces which are not being used dissipate
static power. The proposed architecture in [49] categorizes therouters in the network into three zones. These zones are highutilization zone (UTZ), low utilization zone and rare utilization
zone. The routers which are rarely utilized are power-gated andhave their data rerouted. As a result, 88.76% of static powerin the base router can be saved.
IV. C OMMUNICATION L INKS
Although routers consume more power in NoCs, the communication links can be optimized to accommodate this.
According to [50] and [51], routers and communication channels contribute to most of the power consumption in NoC.
Therefore, novel techniques have been developed to reduce
the amount of power consumed by the links.

1) Voltage Scaling : The voltage swing in the communication links can be optimized to reduce the amount of power it
consumes. However, this is at a cost of a rise in bit-error-rate.
For this purpose, Mineo et al. [52] proposed to reduce power
consumption by using a technique which permits two working
levels in a link. A flag is attached to each communication to
identify their priority. Low prioritised communications (Bodyand Tail flit) can be transmitted on a low-level voltage swing
while the others (Head flit) can be sent using a normal level
voltage.
2) Half-cycle Flits : The longer flits traverse throughthe links in NoC, the more power is consumed. Therefore,
decreasing the number of cycles of it takes from a flit totransmit routers would not only enhance the performance ofthe network but also save power. A. Psarras et al. proposed atechnique which allows flits to only use a half cycle to hop
between routers. By allowing flits to spend less time in thelinks, less power is consumed compared to single cycle routerswhere one cycle is used to execute all operations in the routerand one is used to hop between routers [53].
TABLE IN O C C OMPONENTS & P OWER S AVING D ESIGN T ECHNIQUESRouterArchitecture

Bufferless[54], [14], [17], [55]Buffered[25], [26], [18][19], [20], [21][22], [23], [7]Network
Architecture

3D NoC[45], [56], [38], [36],[40], [39], [41],Wireless NoC[47], [49], [48]Communication
Links

Voltage Scaling[52]

Half-Cycle Flits[53]

V. C ONCLUSION
In this paper, several NoC power saving techniques havebeen evaluated. Particularly, the effect of buffered and bufferless routers on power consumption has been presented. Moreover, a summary of these techniques have presented to compare and contrast their trade-off. The combination of some of
the architectures presented, if employed, can help improve theamount of power consumed by NoC resources which can either be removed or switched-off. This could be the adjustmentof the components (crossbar size, buffers, virtual channels)in the router architecture, modification of the architectures(resource management) and the amount of voltage used in thecommunication links. Also, we explore low power techniques
used in emerging NoC Architectures (3D NoC and WiNOC).
Based on our discussions, we can conclude power dissipation
can be reduced in all areas of a network infrastructure.

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