Design Guide for
COM Express Type 6,7 & Type 10
Carrier Board
Edit by ECD Dept.

Version : 1.2
Date : 2020 / 03 / 16

AAEON Technology Inc.

Focus • Agility • CompetitivenessCompany Profile
Established in 1992, AAEON is one of the leading designers and manufacturers of advanced industrial
and embedded computing platforms today.
Committed to innovative engineering, AAEON provides integrated solutions, hardware and services forpremier OEM/ODMs and system integrators worldwide. Reliable and high quality computing platforms
include industrial motherboards and systems, industrial displays, rugged tablets, PC/104, PICMG and
COM modules, embedded SBCs, embedded controllers, network appliances and related accessories.
AAEON also offers customized end-to-end services from initial product conceptualization and productdevelopment on through to volume manufacturing and after-sales service programs.
With a continuous pursuit of innovation and excellence, AAEON became a member of the ASUS group in
2011, further strengthening its leadership fueled by advanced technology from ASUS and leveraging
resources within the group. AAEON is posed to offer more diversified embedded products and solutions
at higher quality standards to meet world-class design and manufacturing demands in the years to come.
AAEON is an Associate member of the Intel® Intelligent Systems Alliance.

AAEON Core Values
Reliability: Delivering trustworthy products on a timely manner to our customers
Integrity: We value business integrity and ethics, making AAEON your choice business partner
Innovation: Working abreast with industry leaders to maintain technology leadership, AAEON is able tohelp customers turn cutting-edge concepts into reality

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Focus • Agility • CompetitivenessContents
1.

Introduction
1.1 Document Overview
1.2 Acronyms
1.2.1 Abbreviations and Definitions Used
1.2.2 Signal Table Terminology Descriptions
1.3 COM Express Type 6 & Type 10 Pinout Comparison

2.

COM Express Mechanical Specification
2.1 COM Express Module Form Factors
2.2 COM Express Connector

3.

Signal Description and Routing Guideline
3.1 PCB Stack Example
3.2 General Layout rule – BY PLATFORM DESIGN GUIDE
3.3 Interface Layout and Routing Recommendations
3.3.1 PCIE
3.3.1.1 Signal Definitions
3.3.1.2 PCIE Reference Schematics
3.3.1.3 PCIE Layout Recommendations
3.3.2 PEG
3.3.2.1 Signal Definitions
3.3.2.2 PEG Reference Schematics
3.3.2.3 PEG Layout Recommendations
3.3.3 LAN3.3.3.1 Signal Definitions
3.3.3.2 LAN Reference Schematics
3.3.3.3 LAN Layout Recommendations
3.3.4 USB
3.3.4.1 Signal Definitions
3.3.4.2 USB Reference Schematics
3.3.4.3 USB Layout Recommendations
3.3.5 SATA
3.3.5.1 Signal Definitions
3.3.5.2 SATA Reference Schematics
3.3.5.3 SATA Layout Recommendations
3.3.6 LVDS
3.3.6.1 Signal Definitions
3.3.6.2 LVDS Reference Schematics
3.3.6.3 LVDS Layout Recommendations

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Focus • Agility • Competitiveness3.3.7 Embedded DisplayPort
3.3.7.1 Signal Definitions
3.3.7.2 Embedded DisplayPort Reference Schematics
3.3.7.3 Embedded DisplayPort Layout Recommendations - by platform layout guide
3.3.8 VGA
3.3.8.1 Signal Definitions
3.3.8.2 VGA Reference Schematics
3.3.8.3 VGA Layout Recommendations - BY PLATFORM LAYOUT GUIDE
3.3.9 Digital Display
3.3.9.1 Signal Definitions
3.3.9.2 Digital Display Reference Schematics
3.3.9.3 Digital Display Layout Recommendations
3.3.10 Digital Audio
3.3.10.1 Signal Definitions
3.3.10.2 Digital Audio Reference Schematics
3.3.10.3 Digital Audio Layout Recommendations - BY PLATFORM LAYOUT GUIDE
3.3.11 LPC
3.3.11.1 Signal Definitions
3.3.11.2 LPC Reference Schematics
3.3.11.3 LPC Layout Recommendations
3.3.12 SPI
3.3.12.1 Signal Definitions
3.3.12.2 SPI Reference Schematics
3.3.12.3 SPI Layout Recommendations - BY PLATFORM LAYOUT GUIDE
3.3.13 I2C
3.3.13.1 Signal Definitions
3.3.14 SMBUS
3.3.14.1 Signal Definitions
3.3.15 CANBUS
3.3.15.1 Signal Definitions
3.3.15.2 CANBUS Reference Schematics
3.3.15.3 CANBUS Layout Recommendations - BY PLATFORM LAYOUT GUIDE
3.3.16 RTC Battery
3.3.16.1 Signal Definitions
3.3.16.2 RTC Battery Reference Schematics
3.3.16.3 RTC Battery Layout Recommendations - BY PLATFORM LAYOUT GUIDE
3.3.17 DIO
3.3.17.1 Signal Definitions
3.3.17.2 DIO Reference Schematics
3.3.17.3 DIO Layout Recommendations - BY PLATFORM LAYOUT GUIDEAAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.18 SDIO
3.3.18.1 Signal Definitions
3.3.18.2 SDIO Reference Schematics
3.3.18.3 SDIO Layout Recommendations - BY PLATFORM LAYOUT GUIDE
3.3.19 Serial Interface
3.3.19.1 Signal Definitions
3.3.19.2 Serial Interface Reference Schematics
3.3.19.3 Serial Interface Layout Recommendations - BY PLATFORM LAYOUT GUIDE
3.3.20 Power Management Signals
3.3.20.1 Signal Definitions
3.3.20.2 Power Management Signals Reference Schematics
3.3.20.3 Power Management Signals Layout Recommendations - BY PLATFORM LAYOUT
GUIDE
3.3.21 FAN Connector
3.3.21.1 Signal Definitions
3.3.21.2 FAN Connector Reference Schematics
3.3.21.3 FAN Connector Layout Recommendations - BY PLATFORM LAYOUT GUIDE
3.3.22 Miscellaneous Signals
3.3.22.1 Signal Definitions
3.3.22.2 Miscellaneous Signals Reference Schematics
3.3.22.3 Miscellaneous Signals Layout Recommendations - BY PLATFORM LAYOUT GUIDE
3.3.23 10G Signals
3.3.23.1 Signal Definitions
3.3.23.2 10G Signals Reference Schematics
3.3.23.3 10G Signals Layout Recommendations - BY PLATFORM LAYOUT GUIDE
3.3.24 NCSI Signals
3.3.24.1 Signal Definitions
3.3.24.2 NCSI Signals Reference Schematics
3.3.24.3 NCSI Signals Layout Recommendations - BY PLATFORM LAYOUT GUIDE

4.

Power and Reset
4.1 ATX Power Sequence for +12 VDC and +5 VDC , +3.3 VDC
4.2 COM Express ATX vs AT Supplies
4.3 COM Express ATX and AT Power State
4.4 COM Express ATX and AT Power Sequence
4.5 Reference Schematics

5.

Appendix
5.1 List of Figures
5.2 List of Tables

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Focus • Agility • CompetitivenessRevision History
VersionRelease Date

RemarkV0.1

AUG 24, 2016

First release

V1.0

SEP 1, 2016

PublishV1.1

JAN 21, 2019

Update eDP on page 49, DP on page 53, RTC on page 64,
TYPE0#, TYPE1#, TYPE2# on page 71 and Rev 3.0 pin-out on
page 11.

V1.2

Mar 6, 2020

Update Type 7 design guide

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Focus • Agility • Competitiveness1. Introduction
1.1 Document Overview
Brief description of each chapter is given below :Chapter 1: Introduction
Chapter 1 briefly introduces the pinout of type 6 &7& 10 and the structure of the design guide
document.
Chapter 2: COM Express Mechanical Specification
Detailed information about the COM Express connector placement and dimensions are described in
Chapter2.
Chapter 3: Signal Description and Routing Guideline
General design schemes and recommended layout rules are shown in chapter 3. This chapter contains
board descriptions and general layout and routing guidelines for a COM Express Carrier Board. Thesedesign recommendations should be followed for a better quality and robustness.
Chapter 4: Power and Reset
Introduce ATX/AT power supplies and described the power sequence in detail.

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Focus • Agility • Competitiveness1.2 Acronyms
1.2.1 Abbreviations and Definitions Used
Table 1-1: Abbreviations and Definitions Used
Term

Description

AC ‘97 / HDA

Audio CODEC '97/High Definition Audio

ACPI

Advanced Configuration Power Interface – standard to implement
power saving modes in PCAT systems

BIOS

Basic Input Output System – firmware in PC-AT system that isused to initialize system components before handing control overto the operating system

BMC

Baseboard Management Controller

CAN

Controller-area network (CAN or CAN-bus) is a vehicle bus
standard designed to allow microcontrollers to communicate witheach other within a vehicle without a host computer.

Carrier Board

An application specific circuit board that accepts a COM Express
Module.

DAC

Digital Analog Converter

DDC

Display Data Control – VESA (Video Electronics Standards
Association) standard to allow identification of the capabilities ofa VGA monitor

DDI

Digital Display Interface– containing DisplayPort, HDMI/DVI and
SDVO

DP

DisplayPort is a digital display interface standard put forth by theVideo Electronics Standards Association (VESA). It defines a newlicense free, royalty free, digital audio/video interconnect,
intended to be used primarily between a computer and its display
monitor.

DVI

Digital Visual Interface - a Digital Display Working Group (DDWG)
standard that defines a standard video interface supporting both
digital and analog video signals. The digital signals use TMDS.

EDID

Extended Display Identification DataeDP

Embedded DisplayPort (eDP) is a digital display interface standard
produced by the Video Electronics Standards Association (VESA)
for digital interconnect of Audio and Video.

EEPROM

Electrically Erasable Programmable Read-Only Memory

EMI

Electromagnetic Interference

ESD

Electrostatic Discharge

Express Card

A PCMCIA standard built on the latest USB 2.0 and PCI Express

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Focus • Agility • CompetitivenessbusesEAPI

Embedded Application Programming Interface
Software interface for COM Express specific industrial functions•

System information•

Watchdog timer•

I2C Bus•

Flat Panel brightness control•

User storage area

•

GPIO

eSPI

Enhanced Serial Peripheral Interface

GBE

Gigabit Ethernet

GPIO

General Purpose Input Output

HDMI

High Definition Multimedia Interface

I2C

Inter Integrated Circuit – 2 wire (clock and data) signaling scheme
allowing communication between integrated circuits, primarily
used to read and load register values.

LPC

Low Pin-Count Interface: a low speed interface used for peripheral
circuits such as Super I/O controllers, which typically combine
legacy-device support into a single IC.

LVDS

Low-Voltage Differential Signaling – widely used as a physicalinterface for TFT flat panels. LVDS can be used for many highspeed signaling applications. In this document, it refers only
to TFT flat-panel applications.

MDIOManagement Data Input/Output, or MDIO, is a 2-wire serial bus
that is used to manage PHYs or physical layer devices in media
access controllers (MACs).

NC-SI

Network Controller Sideband Interface

PCI Express (PCIE)

Peripheral Component Interface Express – next-generation highspeed Serialized I/O bus

PEG

PCI Express Graphics

RTC

Real Time Clock – battery backed circuit in PC-AT systems thatkeeps system time and date as well as certain system setup
parameters

S0, S1, S2, S3, S4, S5

Sleep States defined by the ACPI specificationS0 Full power,
all devices powered
S1: Sleep State, all context maintained
S2: Sleep State, CPU and Cache context lost
S3: Suspend to RAM System context stored in RAM; RAM is instandby

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Focus • Agility • CompetitivenessS4: Suspend to Disk System context stored on disk
S5: Soft Off Main power rail off, only standby power rail present
SATA

Serial AT Attachment: serial-interface standard for hard disks

SMBus

System Management Bus

SPI

Serial Peripheral Interface

SAFS

eSPI tTerm for Slave Attached Flash Sharing where the Flashcomponent is attached behind a BMC component.

SGMII

Serial Gigabit Media Independent Interface

USB

Universal Serial Bus

WDT

Watch Dog Timer

TVSTransient Voltage Suppressors

TPM

TrustedPlatform

Module,security

features

of

chip

to

enhancethea computer system.

VDR (Varistor)

Voltage Dependent Resistor

10GBase-KR

10 Gbit internal copper interface. Operates over a single lane anduses the same physical layer coding (defined in IEEE 802.3 Clause49) as 10GBASE-LR (Single Mode Fiber 1310 nm ) /ER (Single Mode
Fiber 1550 nm) /SR (Multi Mode Fiber 850 nm)

10GBase-KX44x 10 Gbit internal copper interface. Operates over four lanes anduses the same physical layer coding (defined in IEEE 802.3 Clause48) as 10GBASE-CX4

1.2.2 Signal Table Terminology Descriptions
Table 1-2: Signal Table Terminology Descriptions
Term

Description

I/O 3.3V

Bi-directional signal 3.3V tolerantI/O 5V

Bi-directional signal 5V tolerant

I 3.3V

Input 3.3V tolerant

I 5V

Input 5V tolerantI/O 3V3_SBY

Bi-directional 3.3V tolerant active during Suspend and running state.

O 3.3V

Output 3.3V signal level

O 5V

Output 5V signal level

OD

Open drain output

P

Power input/output

PCIE

In compliance with PCI Express Base Specification

REF

Reference voltage output.

PDS

Pull-down strap.
connected.

May be sourced from a Module power plane.

A Module output pin that is either tied to GND or is not

Used to signal

Module capabilities (pin-out type) to the Carrier Board.

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Focus • Agility • Competitiveness1.3 COM Express Type 6 & Type 10 & Type 7 Pinout Comparison
Table 1-3: COM Express Type 6 & Type 10 Pinout(Refer PICMG Module DG Rev 3.0)

PinType 6

Type 10

Type 7

A1

GND

GND

GND

A2

GBE0_MDI3-

GBE0_MDI3-

GBE0_MDI3-

A3

GBE0_MDI3+

GBE0_MDI3+

GBE0_MDI3+

A4

GBE0_LNIK100#

GBE0_LNIK100#

GBE0_LNIK100#

A5

GBE0_LNIK1000#

GBE0_LNIK1000#

GBE0_LNIK1000#

A6

GBE0_MDI2-

GBE0_MDI2-

GBE0_MDI2-

A7

GBE0_MDI2+

GBE0_MDI2+

GBE0_MDI2+

A8

GBE0_LINK#

GBE0_LINK#

GBE0_LINK#A9

GBE0_MDI1-

GBE0_MDI1-

GBE0_MDI1-

A10

GBE0_MDI1+

GBE0_MDI1+

GBE0_MDI1+

A11

GND

GND

GND

A12

GBE0_MDI0-

GBE0_MDI0-

GBE0_MDI0-

A13

GBE0_MDI0+

GBE0_MDI0+

GBE0_MDI0+

A14

GBE0_CTREF

GBE0_CTREF

GBE0_CTREF

A15

SUS_S3#

SUS_S3#

SUS_S3#

A16

SATA0_TX+

SATA0_TX+

SATA0_TX+

A17

SATA0_TX-

SATA0_TX-

SATA0_TX-

A18

SUS_S4#

SUS_S4#

SUS_S4#

A19

SATA0_RX+

SATA0_RX+

SATA0_RX+

A20

SATA0_RX-

SATA0_RX-

SATA0_RX-

A21

GND

GND

GND

A22

SATA2_TX+

USB_SSRX0-

PCIE_TX15+

A23

SATA2_TX-

USB_SSRX0+

PCIE_TX15-

A24

SUS_S5#SUS_S5#SUS_S5#

A25

SATA2_RX+

USB_SSRX1-

PCIE_TX14+

A26

SATA2_RX-

USB_SSRX1+

PCIE_TX14-

A27

BATLOW#BATLOW#BATLOW#

A28(S)ATA_ACT#(S)ATA_ACT#(S)ATA_ACT#A29

AC/HDA_SYNC

AC/HDA_SYNC

RSVD

A30

AC/HDA_RST#

AC/HDA_RST#

RSVD

A31

GND

GND

GND

A32

AC/HDA_BITCLKAC/HDA_BITCLK

RSVD

A33

AC/HDA_SDOUT

AC/HDA_SDOUT

RSVD

A34

BIOS_DIS0#/ESPI_SAFS

BIOS_DIS0#/ESPI_SAFS

BIOS_DIS0#/ESPI_SAFSA35

THRMTRIP#THRMTRIP#THRMTRIP#

A36

USB6-

USB6-

PCIE_TX13+

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Focus • Agility • CompetitivenessPinType 6

Type 10

Type 7

A37

USB6+

USB6+

PCIE_TX13-

A38

USB_6_7_OC#

USB_6_7_OC#

GND

A39

USB4-

USB4-

PCIE_TX12+

A40

USB4+

USB4+

PCIE_TX12-

A41

GND

GND

GND

A42

USB2-

USB2-

USB2-

A43

USB2+

USB2+

USB2+

A44

USB_2_3_OC#

USB_2_3_OC#

USB_2_3_OC#

A45

USB0-

USB0-

USB0-

A46

USB0+

USB0+

USB0+

A47

VCC_RTC

VCC_RTC

VCC_RTC

A48

RSVD

RSVD

RSVD

A49

GBE0_SDP

GBE0_SDP

GBE0_SDP

A50

LPC_SERIRQ/ESPI_CS1#

LPC_SERIRQ/ESPI_CS1#

LPC_SERIRQ/ESPI_CS1#

A51

GND

GND

GND

A52

PCIE_TX5+

RSVD

PCIE_TX5+

A53

PCIE_TX5-

RSVD

PCIE_TX5-

A54

GPI0

GPI0

GPI0

A55

PCIE_TX4+

RSVD

PCIE_TX4+

A56

PCIE_TX4-

RSVD

PCIE_TX4-

A57

GND

GND

GND

A58

PCIE_TX3+

PCIE_TX3+

PCIE_TX3+

A59

PCIE_TX3-

PCIE_TX3-

PCIE_TX3-

A60

GND

GND

GND

A61

PCIE_TX2+

PCIE_TX2+

PCIE_TX2+

A62

PCIE_TX2-

PCIE_TX2-

PCIE_TX2-

A63

GPI1

GPI1

GPI1

A64

PCIE_TX1+

PCIE_TX1+

PCIE_TX1+

A65

PCIE_TX1-

PCIE_TX1-

PCIE_TX1-

A66

GND

GND

GND

A67

GPI2

GPI2

GPI2

A68

PCIE_TX0+

PCIE_TX0+

PCIE_TX0+

A69

PCIE_TX0-

PCIE_TX0-

PCIE_TX0-

A70

GND

GND

GND

A71

LVDS_A0+

LVDS_A0+

PCIE_TX8+

A72

LVDS_A0-

LVDS_A0-

PCIE_TX8-

A73

LVDS_A1+

LVDS_A1+GND

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Focus • Agility • CompetitivenessPinType 6

Type 10

Type 7

A74

LVDS_A1-

LVDS_A1-

PCIE_TX9+

A75

LVDS_A2+

LVDS_A2+

PCIE_TX9-

A76

LVDS_A2-

LVDS_A2-

GND

A77

LVDS_VDD_EN

LVDS_VDD_EN

PCIE_TX10+

A78

LVDS_A3+

LVDS_A3+

PCIE_TX10-

A79

LVDS_A3-

LVDS_A3-

GND

A80

GND

GND

GND

A81

LVDS_A_CK+LVDS_A_CK+

PCIE_TX11+

A82

LVDS_A_CK-LVDS_A_CK-

PCIE_TX11-

A83

LVDS_I2C_CK

LVDS_I2C_CK

GND

A84

LVDS_I2C_DATLVDS_I2C_DATNCSI_TX_EN

A85

GPI3

GPI3

GPI3

A86

RSVD

RSVD

RSVD

A87

eDP_HPD

eDP_HPDRSVD

A88

PCIE_CLK_REF+

PCIE_CLK_REF+

PCIE_CLK_REF+

A89

PCIE_CLK_REF-

PCIE_CLK_REF-

PCIE_CLK_REF-

A90

GND

GND

GND

A91

SPI_POWERSPI_POWERSPI_POWERA92

SPI_MISO

SPI_MISO

SPI_MISO

A93

GPO0

GPO0

GPO0

A94

SPI_CLKSPI_CLKSPI_CLK

A95

SPI_MOSISPI_MOSISPI_MOSI

A96

TPM_PP

TPM_PP

TPM_PP

A97

TYPE10#

TYPE10#

TYPE10#A98

SER0_TX

SER0_TX

SER0_TX

A99

SER0_RXSER0_RXSER0_RX

A100

GND

GND

GND

A101

SER1_TX

SER1_TX

SER1_TX

A102

SER1_RXSER1_RXSER1_RX

A103

LID#

LID#

LID#

A104

VCC_12V

VCC_12V

VCC_12V

A105

VCC_12V

VCC_12V

VCC_12V

A106

VCC_12V

VCC_12V

VCC_12V

A107

VCC_12V

VCC_12V

VCC_12V

A108

VCC_12V

VCC_12V

VCC_12V

A109

VCC_12V

VCC_12V

VCC_12V

A110

GND

GND

GND

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Focus • Agility • CompetitivenessPinType 6

Type 10

Type 7

B1

GND

GND

GND

B2

GBE0_ACT#

GBE0_ACT#

GBE0_ACT#B3

LPC_FRAME#/ESPI_CS0#

LPC_FRAME#/ESPI_CS0#

LPC_FRAME#/ESPI_CS0#

B4

LPC_AD0/ESPI_IO_0

LPC_AD0/ESPI_IO_0

LPC_AD0/ESPI_IO_0

B5

LPC_AD1/ESPI_IO_1

LPC_AD1/ESPI_IO_1

LPC_AD1/ESPI_IO_1

B6

LPC_AD2/ESPI_IO_2

LPC_AD2/ESPI_IO_2

LPC_AD2/ESPI_IO_2

B7

LPC_AD3/ESPI_IO_3

LPC_AD3/ESPI_IO_3

LPC_AD3/ESPI_IO_3

B8

LPC_DRQ0#/ESPI_ALERT0#

LPC_DRQ0#/ESPI_ALERT0#

LPC_DRQ0#/ESPI_ALERT0#

B9

LPC_DRQ1#/ESPI_ALERT1#

LPC_DRQ1#/ESPI_ALERT1#

LPC_DRQ1#/ESPI_ALERT1#

B10

LPC_CLK/ESPI_CKLPC_CLK/ESPI_CKLPC_CLK/ESPI_CK

B11

GND

GND

GND

B12

PWRBTN#PWRBTN#PWRBTN#B13

SMB_CK

SMB_CK

SMB_CK

B14

SMB_DATSMB_DATSMB_DATB15

SMB_ALERT#SMB_ALERT#SMB_ALERT#

B16

SATA1_TX+

SATA1_TX+

SATA1_TX+

B17

SATA1_TX-

SATA1_TX-

SATA1_TX-

B18

SUS_STAT#/ESPI_RESET#SUS_STAT#/ESPI_RESET#SUS_STAT#/ESPI_RESET#

B19

SATA1_RX+

SATA1_RX+

SATA1_RX+

B20

SATA1_RX-

SATA1_RX-

SATA1_RX-

B21

GND

GND

GND

B22

SATA3_TX+

USB_SSTX0-

PCIE_RX15+

B23

SATA3_TX-

USB_SSTX0+

PCIE_RX15-

B24

PWR_OKPWR_OKPWR_OK

B25

SATA3_RX+

USB_SSTX1-

PCIE_RX14+

B26

SATA3_RX-

USB_SSTX1+

PCIE_RX14-

B27

WDT

WDT

WDT

B28

AC/HDA_SDIN2

AC/HDA_SDIN2

RSVD

B29

AC/HDA_SDIN1

AC/HDA_SDIN1

RSVD

B30

AC/HDA_SDIN0

AC/HDA_SDIN0

RSVD

B31

GND

GND

GND

B32

SPKR

SPKR

SPKR

B33

I2C_CKI2C_CKI2C_CK

B34

I2C_DATI2C_DATI2C_DAT

B35

THRM#

THRM#

THRM#

B36

USB7-

USB7-

PCIE_RX13+

B37

USB7+

USB7+

PCIE_RX13-

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Focus • Agility • CompetitivenessPinType 6

Type 10

Type 7

B38

USB_4_5_OC#

USB_4_5_OC#

GND

B39

USB5-

USB5-

PCIE_RX12+

B40

USB5+

USB5+

PCIE_RX12-

B41

GND

GND

GND

B42

USB3-

USB3-

USB3-

B43

USB3+

USB3+

USB3+

B44

USB_0_1_OC#

USB_0_1_OC#

USB_0_1_OC#

B45

USB1-

USB1-

USB1-

B46

USB1+

USB1+

USB1+

B47

ESPI_EN#ESPI_EN#ESPI_EN#

B48

USB0_HOST_PRSNT

USB0_HOST_PRSNT

USB0_HOST_PRSNTB49

SYS_RESET#SYS_RESET#SYS_RESET#

B50

CB_RESET#CB_RESET#CB_RESET#

B51

GND

GND

GND

B52

PCIE_RX5+

RSVD

PCIE_RX5+

B53

PCIE_RX5-

RSVD

PCIE_RX5-

B54

GPO1

GPO1

GPO1

B55

PCIE_RX4+RSVD

PCIE_RX4+

B56

PCIE_RX4-RSVD

PCIE_RX4-

B57

GPO2

GPO2

GPO2

B58

PCIE_RX3+

PCIE_RX3+

PCIE_RX3+

B59

PCIE_RX3-

PCIE_RX3-

PCIE_RX3-

B60

GND

GND

GND

B61

PCIE_RX2+

PCIE_RX2+

PCIE_RX2+

B62

PCIE_RX2-

PCIE_RX2-

PCIE_RX2-

B63

GPO3

GPO3

GPO3

B64

PCIE_RX1+

PCIE_RX1+

PCIE_RX1+

B65

PCIE_RX1-

PCIE_RX1-

PCIE_RX1-

B66

WAKE0#

WAKE0#

WAKE0#

B67

WAKE1#

WAKE1#

WAKE1#

B68

PCIE_RX0+

PCIE_RX0+

PCIE_RX0+

B69

PCIE_RX0-

PCIE_RX0-

PCIE_RX0-

B70

GND

GND

GND

B71

LVDS_B0+

DDI0_PAIR0+

PCIE_RX8+

B72

LVDS_B0-

DDI0_PAIR0-

PCIE_RX8-

B73

LVDS_B1+

DDI0_PAIR1+

GND

B74

LVDS_B1-

DDI0_PAIR1-

PCIE_RX9+AAEON Technology Inc.

www.aaeon.com
Focus • Agility • CompetitivenessPinType 6

Type 10

Type 7

B75

LVDS_B2+

DDI0_PAIR2+

PCIE_RX9-

B76

LVDS_B2-

DDI0_PAIR2-

GND

B77

LVDS_B3+

DDI0_PAIR4+

PCIE_RX10+

B78

LVDS_B3-

DDI0_PAIR4-

PCIE_RX10-

B79

LVDS_BKLT_EN

LVDS_BKLT_EN

GND

B80

GND

GND

GND

B81

LVDS_B_CK+

DDI0_PAIR3+

PCIE_RX11+

B82

LVDS_B_CK-

DDI0_PAIR3-

PCIE_RX11-

B83

LVDS_BKLT_CTRL

LVDS_BKLT_CTRL

GND

B84

VCC_5V_SBY

VCC_5V_SBY

VCC_5V_SBY

B85

VCC_5V_SBY

VCC_5V_SBY

VCC_5V_SBY

B86

VCC_5V_SBY

VCC_5V_SBY

VCC_5V_SBY

B87

VCC_5V_SBY

VCC_5V_SBY

VCC_5V_SBY

B88

BIOS_DIS1#

BIOS_DIS1#

BIOS_DIS1#

B89

VGA_RED

DDI0_HPDNCSI_RX_ER

B90

GND

GND

GND

B91

VGA_GRN

DDI0_PAIR5+NCSI_CLK_IN

B92

VGA_BLU

DDI0_PAIR5-NCSI_RXD1

B93

VGA_HSYNC

DDI0_PAIR6+NCSI_RXD0

B94

VGA_VSYNC

DDI0_PAIR6-NCSI_CRS_DV

B95

VGA_I2C_CKDDI0_DDC_AUX_SEL

NCSI_TXD1

B96

VGA_I2C_DAT

USB7_HOST_PRSNTNCSI_TXD0

B97

SPI_CS#SPI_CS#SPI_CS#

B98

RSVD

DDI0_CTRLCLK_AUX+

NCSI_ARB_IN

B99

RSVD

DDI0_CTRLDATA_AUX-

NCSI_ARB_OUT

B100

GND

GND

GND

B101

FAN_PWMOUT

FAN_PWMOUT

FAN_PWMOUTB102

FAN_TACHIN

FAN_TACHIN

FAN_TACHINB103

SLEEP#SLEEP#SLEEP#B104

VCC_12V

VCC_12V

VCC_12V

B105

VCC_12V

VCC_12V

VCC_12V

B106

VCC_12V

VCC_12V

VCC_12V

B107

VCC_12V

VCC_12V

VCC_12V

B108

VCC_12V

VCC_12V

VCC_12V

B109

VCC_12V

VCC_12V

VCC_12V

B110

GND

GND

GND

AAEON Technology Inc.

www.aaeon.com
Focus • Agility • CompetitivenessPinType 6

Type 7

C1

GND

GND

C2

GND

GND

C3

USB_SSRX0-

USB_SSRX0-

C4

USB_SSRX0+

USB_SSRX0+

C5

GND

GND

C6

USB_SSRX1-

USB_SSRX1-

C7

USB_SSRX1+

USB_SSRX1+

C8

GND

GND

C9

USB_SSRX2-

USB_SSRX2-

C10

USB_SSRX2+

USB_SSRX2+

C11

GND

GND

C12

USB_SSRX3-

USB_SSRX3-

C13

USB_SSRX3+

USB_SSRX3+

C14

GND

GND

C15

DDI1_PAIR6+

10G_PHY_MDC_SCL3

C16

DDI1_PAIR6-

10G_PHY_MDC_SCL2

C17

RSVD

10G_SDP2

C18

RSVD

GND

C19

PCIE_RX6+

PCIE_RX6+

C20

PCIE_RX6-

PCIE_RX6-

C21

GND

GND

C22

PCIE_RX7+

PCIE_RX7+

C23

PCIE_RX7-

PCIE_RX7-

C24

DDI1_HPD

10G_INT2

C25

DDI1_PAIR4+

GND

C26

DDI1_PAIR4-

10G_KR_RX3+

C27

RSVD

10G_KR_RX3-

C28

RSVD

GND

C29

DDI1_PAIR5+

10G_KR_RX2+

C30

DDI1_PAIR5-

10G_KR_RX2-

C31

GND

GND

C32

DDI2_CTRLCLK_AUX+

10G_SFP_SDA3

C33

DDI2_CTRLDATA_AUX-

10G_SFP_SDA2

C34

DDI2_DDC_AUX_SEL

10G_PHY_RST_23

C35

RSVD

10G_PHY_RST_01

C36

DDI3_CTRLCLK_AUX+

10G_LED_SDA

C37

DDI3_CTRLDATA_AUX-

10G_LED_SCL

AAEON Technology Inc.

www.aaeon.com
Focus • Agility • CompetitivenessPinType 6

Type 7

C38

DDI3_DDC_AUX_SEL

10G_SFP_SDA1

C39

DDI3_PAIR0+

10G_SFP_SDA0

C40

DDI3_PAIR0-

10G_SDP0

C41

GND

GND

C42

DDI3_PAIR1+

10G_KR_RX1+

C43

DDI3_PAIR1-

10G_KR_RX1-

C44

DDI3_HPD

GND

C45

RSVD

10G_PHY_MDC_SCL1

C46

DDI3_PAIR2+

10G_PHY_MDC_SCL0

C47

DDI3_PAIR2-

10G_INT0

C48

RSVD

GND

C49

DDI3_PAIR3+

10G_KR_RX0+

C50

DDI3_PAIR3-

10G_KR_RX0-

C51

GND

GND

C52

PEG_RX0+

PCIE_RX16+

C53

PEG_RX0-

PCIE_RX16-

C54

TYPE0#

TYPE0#

C55

PEG_RX1+

PCIE_RX17+

C56

PEG_RX1-

PCIE_RX17-

C57

TYPE1#TYPE1#C58

PEG_RX2+

PCIE_RX18+

C59

PEG_RX2-

PCIE_RX18-

C60

GND

GND

C61

PEG_RX3+

PCIE_RX19+

C62

PEG_RX3-

PCIE_RX19-

C63

RSVD

RSVD

C64

RSVD

RSVD

C65

PEG_RX4+

PCIE_RX20+

C66

PEG_RX4-

PCIE_RX20-

C67

RAPID_SHUTDOWNRAPID_SHUTDOWNC68

PEG_RX5+

PCIE_RX21+

C69

PEG_RX5-

PCIE_RX21-

C70

GND

GND

C71

PEG_RX6+

PCIE_RX22+

C72

PEG_RX6-

PCIE_RX22-

C73

GND

GND

C74

PEG_RX7+

PCIE_RX23+

AAEON Technology Inc.

www.aaeon.com
Focus • Agility • CompetitivenessPinType 6

Type 7C75

PEG_RX7-

PCIE_RX23-

C76

GND

GND

C77

RSVD

RSVD

C78

PEG_RX8+

PCIE_RX24+

C79

PEG_RX8-

PCIE_RX24-

C80

GND

GND

C81

PEG_RX9+

PCIE_RX25+

C82

PEG_RX9-

PCIE_RX25-

C83

RSVD

RSVD

C84

GND

GND

C85

PEG_RX10+

PCIE_RX26+

C86

PEG_RX10-

PCIE_RX26-

C87

GND

GND

C88

PEG_RX11+

PCIE_RX27+

C89

PEG_RX11-

PCIE_RX27-

C90

GND

GND

C91

PEG_RX12+

PCIE_RX28+

C92

PEG_RX12-

PCIE_RX28-

C93

GND

GND

C94

PEG_RX13+

PCIE_RX29+

C95

PEG_RX13-

PCIE_RX29-

C96

GND

GND

C97

RSVD

RSVD

C98

PEG_RX14+

PCIE_RX30+

C99

PEG_RX14-

PCIE_RX30-

C100

GND

GND

C101

PEG_RX15+

PCIE_RX31+

C102

PEG_RX15-

PCIE_RX31-

C103

GND

GND

C104

VCC_12V

VCC_12V

C105

VCC_12V

VCC_12V

C106

VCC_12V

VCC_12V

C107

VCC_12V

VCC_12V

C108

VCC_12V

VCC_12V

C109

VCC_12V

VCC_12V

C110

GND

GND

AAEON Technology Inc.

www.aaeon.com
Focus • Agility • CompetitivenessPinType 6

Type 7

D1

GND

GND

D2

GND

GND

D3

USB_SSTX0-

USB_SSTX0-

D4

USB_SSTX0+

USB_SSTX0+

D5

GND

GND

D6

USB_SSTX1-

USB_SSTX1-

D7

USB_SSTX1+

USB_SSTX1+

D8

GND

GND

D9

USB_SSTX2-

USB_SSTX2-

D10

USB_SSTX2+

USB_SSTX2+

D11

GND

GND

D12

USB_SSTX3-

USB_SSTX3-

D13

USB_SSTX3+

USB_SSTX3+

D14

GND

GND

D15

DDI1_CTRLCLK_AUX+

10G_PHY_MDIO_SDA3

D16

DDI1_CTRLDATA_AUX-

10G_PHY_MDIO_SDA2

D17

RSVD

10G_SDP3

D18

RSVD

GND

D19

PCIE_TX6+

PCIE_TX6+

D20

PCIE_TX6-

PCIE_TX6-

D21

GND

GND

D22

PCIE_TX7+

PCIE_TX7+

D23

PCIE_TX7-

PCIE_TX7-

D24

RSVD

10G_INT3

D25

RSVD

RSVD

D26

DDI1_PAIR0+

10G_KR_TX3+

D27

DDI1_PAIR0-

10G_KR_TX3-

D28

RSVD

GND

D29

DDI1_PAIR1+

10G_KR_TX2+

D30

DDI1_PAIR1-

10G_KR_TX2-

D31

GND

GND

D32

DDI1_PAIR2+

10G_SFP_SCL3

D33

DDI1_PAIR2-

10G_SFP_SCL2 -D34

DDI1_DDC_AUX_SEL

10G_PHY_CAP_23

D35

RSVD

10G_PHY_CAP_01

D36

DDI1_PAIR3+

RSVD

D37

DDI1_PAIR3-RSVD

AAEON Technology Inc.

www.aaeon.com
Focus • Agility • CompetitivenessPinType 6

Type 7D38

RSVD

10G_SFP_SCL1

D39

DDI2_PAIR0+

10G_SFP_SCL0

D40

DDI2_PAIR0-

10G_SDP1

D41

GND

GND

D42

DDI2_PAIR1+

10G_KR_TX1+

D43

DDI2_PAIR1-

10G_KR_TX1-

D44

DDI2_HPD

GND

D45

RSVD

10G_PHY_MDIO_SDA1

D46

DDI2_PAIR2+

10G_PHY_MDIO_SDA0

D47

DDI2_PAIR2-

10G_INT1

D48

RSVD

GND

D49

DDI2_PAIR3+

10G_KR_TX0+

D50

DDI2_PAIR3-

10G_KR_TX0-

D51

GND

GND

D52

PEG_TX0+

PCIE_TX16+

D53

PEG_TX0-

PCIE_TX16-

D54

PEG_LANE_RV#

RSVD

D55

PEG_TX1+

PCIE_TX17+

D56

PEG_TX1-

PCIE_TX17-

D57

TYPE2#

TYPE2#D58

PEG_TX2+

PCIE_TX18+

D59

PEG_TX2-

PCIE_TX18-

D60

GND

GND

D61

PEG_TX3+

PCIE_TX19+

D62

PEG_TX3-

PCIE_TX19-

D63

RSVD

RSVD

D64

RSVD

RSVD

D65

PEG_TX4+

PCIE_TX20+

D66

PEG_TX4-

PCIE_TX20-

D67

GND

GND

D68

PEG_TX5+

PCIE_TX21+

D69

PEG_TX5-

PCIE_TX21-

D70

GND

GND

D71

PEG_TX6+

PCIE_TX22+

D72

PEG_TX6-

PCIE_TX22-

D73

GND

GND

D74

PEG_TX7+

PCIE_TX23+

AAEON Technology Inc.

www.aaeon.com
Focus • Agility • CompetitivenessPinType 6

Type 7

D75

PEG_TX7-

PCIE_TX23-

D76

GND

GND

D77

RSVD

RSVD

D78

PEG_TX8+

PCIE_TX24+

D79

PEG_TX8-

PCIE_TX24-

D80

GND

GND

D81

PEG_TX9+

PCIE_TX25+

D82

PEG_TX9-

PCIE_TX25-

D83

RSVD

RSVD

D84

GND

GND

D85

PEG_TX10+

PCIE_TX26+

D86

PEG_TX10-

PCIE_TX26-

D87

GND

GND

D88

PEG_TX11+

PCIE_TX27+

D89

PEG_TX11-

PCIE_TX27-

D90

GND

GND

D91

PEG_TX12+

PCIE_TX28+

D92

PEG_TX12-

PCIE_TX28-

D93

GND

GND

D94

PEG_TX13+

PCIE_TX29+

D95

PEG_TX13-

PCIE_TX29-

D96

GND

GND

D97

RSVD

RSVD

D98

PEG_TX14+

PCIE_TX30+

D99

PEG_TX14-

PCIE_TX30-

D100

GND

GND

D101

PEG_TX15+

PCIE_TX31+

D102

PEG_TX15-

PCIE_TX31-

D103

GND

GND

D104

VCC_12V

VCC_12V

D105

VCC_12V

VCC_12V

D106

VCC_12V

VCC_12V

D107

VCC_12V

VCC_12V

D108

VCC_12V

VCC_12V

D109

VCC_12V

VCC_12V

D110

GND

GND

AAEON Technology Inc.

www.aaeon.com
Focus • Agility • Competitiveness2.

COM Express Mechanical Specification

2.1 COM Express Module Form Factors (Refer PICMG Module DG Rev.2.1)
Figure 2-1 Module Form Factors

AAEON Technology Inc.

www.aaeon.com
Focus • Agility • CompetitivenessFigure 2-1-1 AAEON COM Express Module

Product: NanoCOM-SKU
COM Express Mini Type 10

Product: COM-SKHB6COM Express Basic Type 6

AAEON Technology Inc.

Product: COM-SKU6
COM Express Compact Type 6

Product: COM-SKDB7COM Express Compact Type 7

www.aaeon.com
Focus • Agility • Competitiveness2.2 COM Express Connector
Type 6 of COM Express module utilizes two 220-pin high density connectors to interface the COM
Express module and carrier board.
Figure 2-2 Type 6 ROW ABCD Connector

AAEON Technology Inc.

www.aaeon.com
Focus • Agility • CompetitivenessType 10 of COM Express module utilizes one 220-pin high density connectors tointerface the COM Express module and carrier board.
Figure 2-3 Type 10 ROW AB Connector

AAEON Technology Inc.

www.aaeon.com
Focus • Agility • CompetitivenessType 7 of COM Express module utilizes two 220-pin high density connectors tointerface the COM Express module and carrier board.
Figure 2-4 Type 7 ROW ABCD Connector

AAEON Technology Inc.

www.aaeon.com
Focus • Agility • CompetitivenessAAEON Connector Type :Table 2-1: AAEON Connector Type
Connector Type

HeightSupplier - Model

AAEON’s P/NCarrier Board (Plug)

8 .0 mm

FOXCONN / QT002206-4131-3H

16540M0201

Module Board (Receptacle)

3.25 mm

FOXCONN / QT012206-1031-2H

16540M0001

Figure 2-5 Plug and Receptacle

Figure 2-6 Heat spreader with Threaded Standoffs

AAEON Technology Inc.

www.aaeon.com
Focus • Agility • Competitiveness3.

Signal Description and Routing Guideline

3.1 PCB Stack Example
Table 3-1: PCB Stack Example
Layer

1

2

3

4

4

S1

G

P

S2

4

S1

S2/G

P

S3

4

S1

G

S2/P

S3

6

S1

G

S2

6

S1

S2/G

6

S1

8
8
Note :

5

6

7

8

S3

P

S4

S3

S4

P

S5

G

S2

S3

P/S4

S5

S1

G

S2

G

P

S3

G

S4

S1

G

S2

S3

P

S4

G

S5

9

10

11

12

13

14

S=Signal routing layer , P=Power , G=Ground

3.2 General Layout rule : BY PLATFORM LAYOUT GUIDEAAEON Technology Inc.

www.aaeon.com
Focus • Agility • Competitiveness3.3 Interface Layout and Routing Recommendations
3.3.1 PCIEPCI Express provides a scalable, high-speed, serial I/O point-to-point bus connection. PCIE iseasy to work with, but design rules must be followed. The most important design rule is that
the PCIE lanes must be routed as differential pairs.
3.3.1.1 Signal Definitions
Table 3-2: PCIE Signal Definitions
Pin

Type

SignalDescription

B68

Type 6,7

PCIE_RX0+PCIE channel 0.

B69

Type 10

PCIE_RX0-

differential pair.

A68

Type 6,7

PCIE_TX0+PCIE channel 0.

A69

Type 10

PCIE_TX0-

differential pair.

B64

Type 6,7

PCIE_RX1+

PCIE channel 1.

B65

Type 10

PCIE_RX1-

differential pair.

A64

Type 6,7

PCIE_TX1+

PCIE channel 1.

A65

Type 10

PCIE_TX1-

differential pair.

B61

Type 6,7

PCIE_RX2+PCIE channel 2.

B62

Type 10

PCIE_RX2-differential pair.

A61

Type 6,7

PCIE_TX2+

PCIE channel 2.

A62

Type 10

PCIE_TX2-

differential pair.

B58

Type 6,7

PCIE_RX3+

PCIE channel 3.

B59

Type 10

PCIE_RX3-

differential pair.

A58

Type 6,7

PCIE_TX3+

PCIE channel 3.

A59

Type 10

PCIE_TX3-

differential pair.

B55

Type 6

PCIE_RX4+

PCIE channel 4.

B56

Type 7

PCIE_RX4-

differential pair.

A55

Type 6

PCIE_TX4+

PCIE channel 4.

A56

Type 7

PCIE_TX4-

differential pair.

B52

Type 6

PCIE_RX5+

PCIE channel 5.

B53

Type 7

PCIE_RX5-differential pair.

A52

Type 6

PCIE_TX5+

PCIE channel 5.

A53

Type 7

PCIE_TX5-

differential pair.

C19Type 6

PCIE_RX6+

PCIE channel 6.

C20Type 7

PCIE_RX6-

differential pair.

D19Type 6

PCIE_TX6+

PCIE channel 6.

D20Type 7

PCIE_TX6-

differential pair.

C22Type 6

PCIE_RX7+

PCIE channel 7.

C23

Type 7

PCIE_RX7-

differential pair.

AAEON Technology Inc.

I/O
Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIEwww.aaeon.com
Focus • Agility • CompetitivenessD22Type 6

PCIE_TX7+

PCIE channel 7.

D23

Type 7

PCIE_TX7-

differential pair.

B71

Type 7

PCIE_RX8+PCIE channel 8.

PCIE_RX8-differential pair.

PCIE_TX8+

PCIE channel 8.

PCIE_TX8-

differential pair.

PCIE_RX9+PCIE channel 9.

PCIE_RX9-differential pair.

PCIE_TX9+

PCIE channel 9.

PCIE_TX9-

differential pair.

PCIE_RX10+

PCIE channel 10.

PCIE_RX10-

differential pair.

PCIE_TX10+

PCIE channel 10.

PCIE_TX10-

differential pair.

PCIE_RX11+

PCIE channel 11.

PCIE_RX11-differential pair.

PCIE_TX11+

PCIE channel 11.

PCIE_TX11-

differential pair.

PCIE_RX12+

PCIE channel 12.

PCIE_RX12-differential pair.

PCIE_TX12+

PCIE channel 12.

PCIE_TX12-

differential pair.

PCIE_RX13+

PCIE channel 13.

PCIE_RX13-

differential pair.

PCIE_TX13+

PCIE channel 13.

PCIE_TX13-

differential pair.

PCIE_RX14+

PCIE channel 14.

PCIE_RX14-differential pair.

PCIE_TX14+

PCIE channel 14.

PCIE_TX14-

differential pair.

PCIE_RX15+

PCIE channel 15.

PCIE_RX15-

differential pair.

PCIE_TX15+

PCIE channel 15.

PCIE_TX15-

differential pair.

PCIE_RX16+

PCIE channel 16.

PCIE_RX16-differential pair.

PCIE_TX16+

PCIE channel 16.

PCIE_TX16-

differential pair.

B72
A71

Type 7A72
B74

Type 7B75
A74Type 7A75
B77

Type 7B78
A77

Type 7A78
B81

Type 7B82
A81

Type 7A82
B39Type 7B40
A39Type 7A40B36Type 7B37A36Type 7A37
B25Type 7B26A25Type 7A26
B22Type 7B23A22Type 7A23
C52Type 7C53
D52Type 7D53

AAEON Technology Inc.

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIEwww.aaeon.com
Focus • Agility • CompetitivenessC55

Type 7C56
D55Type 7D56
C58Type 7C59
D58Type 7D59
C61Type 7C62
D61Type 7D62
C65Type 7C66
D65Type 7

D66
C68Type 7

C69
D68Type 7

D69
C71Type 7C72
D71Type 7D72
C74Type 7C75
D74Type 7D75
C78Type 7

C79
D78Type 7

D79
C81Type 7C82
D81Type 7D82C85Type 7C86

AAEON Technology Inc.

PCIE_RX17+

PCIE channel 17.

PCIE_RX17-differential pair.

PCIE_TX17+

PCIE channel 17.

PCIE_TX17-

differential pair.

PCIE_RX18+

PCIE channel 18.

PCIE_RX18-

differential pair.

PCIE_TX18+

PCIE channel 18.

PCIE_TX18-

differential pair.

PCIE_RX19+

PCIE channel 19.

PCIE_RX19-

differential pair.

PCIE_TX19+

PCIE channel 19.

PCIE_TX19-

differential pair.

PCIE_RX20+

PCIE channel 20.

PCIE_RX20-

differential pair.

PCIE_TX20+

PCIE channel 20.

PCIE_TX20-

differential pair.

PCIE_RX21+

PCIE channel 21.

PCIE_RX21-

differential pair.

PCIE_TX21+

PCIE channel 21.

PCIE_TX21-

differential pair.

PCIE_RX22+

PCIE channel 22.

PCIE_RX22-

differential pair.

PCIE_TX22+

PCIE channel 22.

PCIE_TX22-

differential pair.

PCIE_RX23+

PCIE channel 23.

PCIE_RX23-

differential pair.

PCIE_TX23+

PCIE channel 23.

PCIE_TX23-

differential pair.

PCIE_RX24+

PCIE channel 24.

PCIE_RX24-

differential pair.

PCIE_TX24+

PCIE channel 24.

PCIE_TX24-

differential pair.

PCIE_RX25+

PCIE channel 25.

PCIE_RX25-

differential pair.

PCIE_TX25+

PCIE channel 25.

PCIE_TX25-

differential pair.

PCIE_RX26+

PCIE channel 26.

PCIE_RX26-

differential pair.

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIEwww.aaeon.com
Focus • Agility • CompetitivenessD85Type 7D86
C88

Type 7C89
D88

Type 7

D89
C91

Type 7

C92
D91

Type 7D92
C94

Type 7C95
D94Type 7

D95
C98

Type 7

C99
D98

Type 7D99
C101Type 7C102
D101Type 7

D102

PCIE_TX26+

PCIE channel 26.

PCIE_TX26-

differential pair.

PCIE_RX27+

PCIE channel 27.

PCIE_RX27-

differential pair.

PCIE_TX27+

PCIE channel 27.

PCIE_TX27-

differential pair.

PCIE_RX28+

PCIE channel 28.

PCIE_RX28-

differential pair.

PCIE_TX28+

PCIE channel 28.

PCIE_TX28-

differential pair.

PCIE_RX29+

PCIE channel 29.

PCIE_RX29-

differential pair.

PCIE_TX29+

PCIE channel 29.

PCIE_TX29-

differential pair.

PCIE_RX30+

PCIE channel 30.

PCIE_RX30-

differential pair.

PCIE_TX30+

PCIE channel 30.

PCIE_TX30-

differential pair.

PCIE_RX31+

PCIE channel 31.

PCIE_RX31-

differential pair.

PCIE_TX31+

PCIE channel 31.

PCIE_TX31-

differential pair.

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

Receive Input

I PCIE

Transmit Output

O PCIE

A88

Type 6,7

PCIE_CLK_REF+

PCIE Reference Clock for all COM

A89

Type 10

PCIE_CLK_REF-

Express PCIE lanes, and for PEG lanes.

A49

Type 6,7

GBE0_SDP

Gigabit Ethernet Controller 0 Software-Type 10O PCIE

IO

Definable Pin. Can also be used forIEEE1588 support such as a 1pps signal.

A48

Type 6,7

RSVD

Type 10
B48

Type 6,7

USB0_HOST_PRSNTType 10

Module USB client may detect theI CMOS

presence of a USB host on USB0. A
high value
indicates that a host is present.

B47

Type 6,7
Type 10

ESPI_EN#

This signal is used by the Carrier to

O CMOS

indicate the operating mode of the
LPC/eSPI bus. If left unconnected on
the carrier, LPC mode (default) is
selected. If pulled to GND on the
carrier, eSPI mode is selected. This

AAEON Technology Inc.

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Focus • Agility • Competitivenesssignal is pulled to a logic high on themodule through a resistor. The Carrier
should only float this line or pull it
Low.
B50

Type 6,7

CB_RESET#

Type 10

Reset output from Module to Carrier
Board.

O CMOS

Active low. Issued by Module

chipset and may result from a low
SYS_RESET# input, a low PWR_OK
input, a VCC_12V power input that falls
below the minimum specification, awatchdog timeout, or may be initiatedby the Module software.
B66

Type 6,7

WAKE0#PCI Express wake up signal

I CMOSType 103.3.1.2 PCIE Reference Schematics
Figure 3-1 PCIE[x1] Reference Schematic

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Focus • Agility • CompetitivenessFigure 3-2 Mini-Card for mSATA / PCIE Switching Reference Schematic

Figure 3-3 Mini-Card for mSATA / PCIE Reference Schematic

AAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.1.3 PCIE Layout Recommendations
Table 3-3: PCIE / PEG Trace Routing Guidelines
Parameter

PCIE Gen1

PCIE Gen2

PCIE Gen3

Symbol Rate

2.5 G

5.0 G

8.0 G

Carrier Board Signal length(to PCIE slot)

9.0 inches

9.0 inches

4.0 inches

Differential impedance

85 Ω +/-15%(Impedence may vary when different platform used)

Single-ended Impedance

55 Ω +/-15%

Trace width / Spacing between
differential pairs

PCB stack-up dependent

Spacing between RX and TX(inter-pair) / differential pairs
and low-speed non periodic
signalsMin. 20mils

Spacing between differential
pairs and high-speed periodic
signalsMin. 50mils

Length matching between

Max. 5mils

a redriver may benecessary for GEN3signaling rates

50 Ω +/-15%

50 Ω +/-15%

differential pairs (intra-pair)
Reference plane

GND referenced preferred

Length matching between RX
and TX pairs (inter-pair)No strict electrical requirements.Keep difference within a
3.0 inch delta to minimize latency.

Via Usage

Max. 2 vias per TX trace
Max. 4 vias per RX trace

AC coupling capacitors

Capacitor type: X7R, 100nF +/- 10%, 16V, shape 0402.

AAEON Technology Inc.

Max. 2 vias per TX trace
Max. 2 vias per RX trace

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Focus • Agility • Competitiveness3.3.2 PEG
The PEG Port can utilize COM Express PCIE lanes 16-32 to drive a x16 link for an external highperformance PCI Express Graphics card. Type 6 provides dedicated PEG and SDVO channels.
3.3.2.1 Signal Definitions
Table 3-4: PEG Signal Definitions
Pin

Type

SignalDescription

I/O

C52

Type 6

PEG_RX0+

PEG channel 0, Receive Input

I PCIEPEG_RX0-

differential pair.

PEG_TX0+

PEG channel 0, Transmit Output

PEG_TX0-

differential pair.

PEG_RX1+

PEG channel 1, Receive Input

PEG_RX1-

differential pair.

PEG_TX1+

PEG channel 1, Transmit Output

PEG_TX1-

differential pair.

PEG_RX2+

PEG channel 2, Receive Input

PEG_RX2-

differential pair.

PEG_TX2+

PEG channel 2, Transmit Output

PEG_TX2-

differential pair.

PEG_RX3+

PEG channel 3, Receive Input

PEG_RX3-

differential pair.

PEG_TX3+

PEG channel 3, Transmit Output

PEG_TX3-

differential pair.

PEG_RX4+

PEG channel 4, Receive Input

PEG_RX4-

differential pair.

PEG_TX4+

PEG channel 4, Transmit Output

PEG_TX4-

differential pair.

PEG_RX5+

PEG channel 5, Receive Input

PEG_RX5-

differential pair.

PEG_TX5+

PEG channel 5, Transmit Output

PEG_TX5-

differential pair.

PEG_RX6+

PEG channel 6, Receive Input

PEG_RX6-

differential pair.

PEG_TX6+

PEG channel 6, Transmit Output

PEG_TX6-

differential pair.

PEG_RX7+

PEG channel 7, Receive Input

PEG_RX7-

differential pair.

PEG_TX7+

PEG channel 7, Transmit Output

PEG_TX7-

differential pair.

C53
D52

Type 6D53
C55Type 6C56
D55Type 6D56
C58

Type 6C59
D58

Type 6

D59
C61

Type 6C62
D61Type 6D62
C65Type 6C66
D65Type 6

D66
C68Type 6

C69
D68Type 6

D69
C71

Type 6C72
D71

Type 6D72
C74Type 6C75
D74Type 6D75

AAEON Technology Inc.

O PCIEI PCIEO PCIEI PCIEO PCIEI PCIEO PCIEI PCIEO PCIEI PCIEO PCIEI PCIEO PCIEI PCIEO PCIEwww.aaeon.com
Focus • Agility • CompetitivenessC78

Type 6

C79
D78

Type 6

D79
C81

Type 6C82
D81Type 6D82
C85Type 6C86
D85Type 6D86
C88

Type 6C89
D88

Type 6

D89
C91

Type 6

C92
D91

Type 6D92
C94

Type 6C95
D94

Type 6

D95
C98

Type 6

C99
D98

Type 6D99
C101

Type 6C102
D101Type 6

D102
D54Type 6

PEG_RX8+

PEG channel 8, Receive Input

I PCIEPEG_RX8-

differential pair.

PEG_TX8+

PEG channel 8, Transmit Output

PEG_TX8-

differential pair.

PEG_RX9+

PEG channel 9, Receive Input

PEG_RX9-

differential pair.

PEG_TX9+

PEG channel 9, Transmit Output

PEG_TX9-

differential pair.

PEG_RX10+

PEG channel 10, Receive Input

PEG_RX10-

differential pair.

PEG_TX10+

PEG channel 10, Transmit Output

PEG_TX10-

differential pair.

PEG_RX11+

PEG channel 11, Receive Input

PEG_RX11-

differential pair.

PEG_TX11+

PEG channel 11, Transmit Output

PEG_TX11-

differential pair.

PEG_RX12+

PEG channel 12, Receive Input

PEG_RX12-

differential pair.

PEG_TX12+

PEG channel 12, Transmit Output

PEG_TX12-

differential pair.

PEG_RX13+

PEG channel 13, Receive Input

PEG_RX13-

differential pair.

PEG_TX13+

PEG channel 13 Transmit Output

PEG_TX13-

differential pair.

PEG_RX14+

PEG channel 14, Receive Input

PEG_RX14-

differential pair.

PEG_TX14+

PEG channel 14, Transmit Output

PEG_TX14-

differential pair.

PEG_RX15+

PEG channel 15, Receive Input

PEG_RX15-

differential pair.

PEG_TX15+

PEG channel 15, Transmit Output

PEG_TX15-

differential pair.

PEG_LANE_RV#PCI Express Graphics lane reversal

I 3.3V

input strap.

CMOS

O PCIEI PCIE

Pull low on the carrier

O PCIEI PCIEO PCIEI PCIEO PCIEI PCIEO PCIEI PCIEO PCIEI PCIEO PCIEI PCIEO PCIE

board to reverse lane order.
A88

Type 6

PCIE_CLK_REF+

PCIE Reference Clock for all COM

A89

Type 10

PCIE_CLK_REF-

Express PCIE lanes, and for PEG lanes

AAEON Technology Inc.

O CMOS

www.aaeon.com
Focus • Agility • Competitiveness3.3.2.2 PEG Reference Schematics
Figure 3-4 PEG Reference Schematic

3.3.2.3 PEG Layout Recommendations(Refer 3.3.1.3)

AAEON Technology Inc.

www.aaeon.com
Focus • Agility • Competitiveness3.3.3 LAN
All COM Express Modules provide at least one LAN port. The 8-wire 10/100/1000BaseT
Gigabit Ethernet interface compliant to the IEEE 802.3-2005 specification is the preferredinterface for this port, with the COM Express Module PHY responsible for implementing
auto-negotiation of 10/100BaseTX vs 10/100/1000BaseT operation.
3.3.3.1 Signal Definitions
Table 3-5: LAN Signal Definitions
Pin Type

SignalDescription

I/O

A2

Type 6,7

GBE0_MDI3-Media Dependent Interface (MDI) differential pair 3. The

I/O GBE

A3

Type 10

GBE0_MDI3+

MDI can operate in 1000, 100, and 10Mbit/sec modes.

A4Type 6,7

GBE0_LINK100#

Ethernet controller 0 100Mbit/sec link indicator, active low.

O 3.3V Suspend

A5

Type 10

GBE0_LINK1000#

Ethernet controller 0 1000Mbit/sec link indicator, active low.

OD CMOSA6

Type 6,7

GBE0_MDI2-Media Dependent Interface (MDI) differential pair 2. The

I/O GBE

A7

Type 10

GBE0_MDI2+

MDI can operate in 1000, 100, and 10Mbit/sec modes.

I/O GBE

A8

Type 6,7

GBE0_LINK#

Ethernet controller 0 link indicator, active low.

O 3.3V Suspend

B2

Type 10

GBE0_ACT#

Ethernet controller 0 activity indicator, active low.

OD CMOSA9Type 6,7

GBE0_MDI1-Media Dependent Interface (MDI) differential pair 1. The

I/O GBE

A10

Type 10

GBE0_MDI1+

MDI can operate in 1000, 100, and 10Mbit/sec modes.

I/O GBE

A12Type 6,7

GBE0_MDI0-Media Dependent Interface (MDI) differential pair 0. The

I/O GBE

A13

Type 10

GBE0_MDI0+

MDI can operate in 1000, 100, and 10Mbit/sec modes.

I/O GBE

A14

Type 6,7

GBE0_CTREF

Reference voltage for Carrier Board Ethernet

REF

Type 10AAEON Technology Inc.

channel 0 magnetics center tap.

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Focus • Agility • Competitiveness3.3.3.2 LAN Reference Schematics
Figure 3-5 RJ45 Reference Schematic

Note : TVS placement must be close to Connector for ESD Solution .

AAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.3.3 LAN Layout Recommendations
Table 3-6: LAN Trace Routing Guidelines
Parameter

Trace Routing

Carrier Board Signal length

5.0 inches

Max signal length between isolation magnetics 1.0 inch
Module and RJ45 connector
Differential Impedance

95 Ω +/-20%(Impedence may vary when different LAN IC )Single-ended Impedance

55 Ω +/-15%

Trace width / Differential pairs Spacing (intrapair)

PCB stack-up dependent

Spacing between RX and TX pairs (inter-pair)Min. 50mils

Spacing between differential pairs and highspeed periodic signals

Min. 300mils

Spacing between differential pairs and lowspeed non periodic signals

Min. 100mils

Length matching between differential pairs(intra-pair)Max. 5mils

Length matching between RX and TX pairs(inter-pair)Max. 30mils

Spacing between digital ground and analog

Min. 60mils

ground plane (between the magnetics Module
and RJ45 connector)
Spacing from edge of plane

Min. 40mils

Via Usage

Max. of 2 vias on TX pathMax. of 2 vias on RX path

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Focus • Agility • Competitiveness3.3.4 USB
All USB interfaces shall be USB 2.0 compliant. There are 4 over-current signals shared by the
8 USB Ports. A Carrier must current limit the USB power source to minimize disruption of the
Carrier in the event that a short or over-current condition exists on one of the USB Ports. A
Module must fill the USB Ports starting at Port 0.
3.3.4.1 Signal Definitions
Table 3-7: USB2.0 Signal Definitions
Pin Type

SignalDescription

I/O

A46

Type 6,7

USB0+

USB Port 0, data + or D+, mandatory on Module

I/O USB

A45

Type 10USB0-

USB Port 0, data - or D-, mandatory on Module

I/O USB

B46

Type 6,7

USB1+

USB Port 1, data + or D+, mandatory on Module

I/O USB

B45

Type 10USB1-

USB Port 1, data - or D-, mandatory on Module

I/O USB

A43

Type 6,7

USB2+

USB Port 2, data + or D+, mandatory on Module

I/O USB

A42

Type 10

USB2-

USB Port 2, data - or D-, mandatory on Module

I/O USB

B43

Type 6,7

USB3+

USB Port 3, data + or D+, mandatory on Module

I/O USB

B42

Type 10

USB3-

USB Port 3, data - or D-, mandatory on Module

I/O USB

A40

Type 6

USB4+

USB Port 4, data + or D+, optional on Module

I/O USB

A39

Type 10

USB4-

USB Port 4, data - or D-, optional on Module

I/O USB

B40

Type 6

USB5+

USB Port 5, data + or D+, optional on Module

I/O USB

B39

Type 10

USB5-

USB Port 5, data - or D-, optional on Module

I/O USB

A37

Type 6USB6+

USB Port 6, data + or D+, optional on Module

I/O USB

A36

Type 10

USB6-

USB Port 6, data - or D-, optional on Module

I/O USB

B37

Type 6

USB7+

USB Port 7, data + or D+, optional on Module

I/O USB

B36

Type 10

USB7-

USB Port 7, data - or D-, optional on Module

I/O USB

USB_0_1_OC#

USB over-current sense, USB ports 0 and 1.

I 3.3V CMOS

B44
Type 6,7
A44Type 10

optional on Module
USB_2_3_OC#

USB over-current sense, USB ports 2 and 3.

I 3.3V CMOS

optional on Module
B38

USB_4_5_OC#
Type 6

A38

Type 10USB over-current sense, USB ports 4 and 5.

I 3.3V CMOS

optional on Module
USB_6_7_OC#

USB over-current sense, USB ports 6 and 7.

I 3.3V CMOS

optional on Module

AAEON Technology Inc.

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Focus • Agility • CompetitivenessTable 3-8: USB3.0 Signal Definitions
Pin Type

SignalDescription

I/O

D4

Type 6,7

USB_SSTX0+

USB Port 0, SuperSpeed TX +O PCIE

B23

Type 10D3Type 6,7

USB_SSTX0-

USB Port 0, SuperSpeed TX -O PCIE

B22

Type 10D7Type 6,7

USB_SSTX1+

USB Port 1, SuperSpeed TX +O PCIE

B26

Type 10D6Type 6,7

USB_SSTX1-

USB Port 1, SuperSpeed TX -O PCIE

B25

Type 10D10Type 6,7

USB_SSTX2+

USB Port 2, SuperSpeed TX +O PCIED9Type 6,7

USB_SSTX2-

USB Port 2, SuperSpeed TX -O PCIE

D13

Type 6,7

USB_SSTX3+

USB Port 3, SuperSpeed TX +O PCIED12Type 6,7

USB_SSTX3-

USB Port 3, SuperSpeed TX -O PCIE

C4Type 6,7

USB_SSRX0+

USB Port 0, SuperSpeed RX +I PCIE

A23

Type 10C3Type 6,7

USB_SSRX0-

USB Port 0, SuperSpeed RX -I PCIE

A22

Type 10C7Type 6,7

USB_SSRX1+

USB Port 1, SuperSpeed RX +I PCIE

A26

Type 10C6Type 6,7

USB_SSRX1-

USB Port 1, SuperSpeed RX -I PCIE

A25

Type 10C10Type 6,7

USB_SSRX2+

USB Port 2, SuperSpeed RX +I PCIEC9Type 6,7

USB_SSRX2-

USB Port 2, SuperSpeed RX -I PCIE

C13

Type 6,7

USB_SSRX3+

USB Port 3, SuperSpeed RX +I PCIEC12Type 6,7

USB_SSRX3-

USB Port 3, SuperSpeed RX -I PCIEAAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.4.2 USB Reference Schematics - USB2.0 & USB3.0
Figure 3-6 USB2.0+USB3.0 Reference Schematic

Note : TVS placement must be close to Connector for ESD Solution .

Figure 3-7 USB Power Over-Current Protection Reference Schematic

AAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.4.3 USB Layout Recommendations
Table 3-9: USB2.0 and USB3.0 Trace Routing Guidelines
ParameterUSB2.0 Trace Routing

USB3.0 Trace Routing

Transfer rate

480 MBit/s

5.0 GBit/s

Maximum signal line lengthMax. 17.0 inches

7.5 inches

Carrier Board Signal length

14.0 inches

4.5 inches

Differential Impedance

90 Ω +/-15%(Impedence may vary whendifferent platform used)

85 Ω +/-10%(Impedence may vary whendifferent platform used)

Single-ended Impedance

45 Ω +/-10%

50 Ω +/-15%

Trace width / differential
pairs Spacing (intra-pair)

PCB stack-up dependent

PCB stack-up dependent

Spacing between pairs-topairs (inter-pair)Min. 20mils

Min. 15mils

Spacing between

Min. 50mils

Min. 15mils

Min. 20mils

Min. 20mils

differential pairs and highspeed periodic
signals
Spacing between
differential pairs and lowspeed non
periodic signals

Length matching between
150mils
differential pairs (intra-pair)Max. 5mils

Reference plane

GroundGroundSpacing from edge of plane

Min. 40mils

Via Usage

Try to minimize number of vias
(Max. 3 vias per differential signal trace)

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Focus • Agility • Competitiveness3.3.5 SATA
Serial ATA links for support of existing SATA Gen1, 2 and 3 devices.
3.3.5.1 Signal Definitions
Table 3-10: SATA Signal Definitions
Pin Type

SignalDescription

I/O

A16

Type 6,7

SATA0_TX+

SATA channel 0

O SATA

A17

Type 10

SATA0_TX-

Transmit output differential pair.

A19Type 6,7

SATA0_RX+

SATA channel 0

A20

Type 10

SATA0_RX-

Receive input differential pair.

B16Type 6,7

SATA1_TX+

SATA channel 1

B17

Type 10

SATA1_TX-

Transmit output differential pair.

B19

Type 6,7

SATA1_RX+

SATA channel 1

B20

Type 10

SATA1_RX-

Receive input differential pair.

A22Type 6

SATA2_TX+

SATA channel 2

SATA2_TX-

Transmit output differential pair.

SATA2_RX+

SATA channel 2

SATA2_RX-

Receive input differential pair.

SATA3_TX+

SATA channel 3

SATA3_TX-

Transmit output differential pair.

SATA3_RX+

SATA channel 3

SATA3_RX-

Receive input differential pair.

SATA_ACT#SATA activity LED. Open collector

O 3.3Voutput pin driven during SATACMOS OC

A23
A25

Type 6A26
B22Type 6B23
B25Type 6B26A28Type 6,7
Type 10I SATAO SATAI SATAO SATAI SATAO SATAI SATA

command activity.

AAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.5.2 SATA Reference Schematics
Figure 3-8 SATA (with Repeater IC) Reference Schematic

Note: Please contact repeater IC vendor FAE for high-quality SATA electrical signals.
3.3.5.3 SATA Layout Recommendations
Table 3-11: SATA Trace Routing Guidelines
Parameter

Trace Routing

Transfer Rate

Up to 6.0 GBit/s

Maximum signal line length

5.0 inches

Carrier Board Signal length

3 inchesa redriver may be necessary forGEN3 signaling rates

Differential Impedance

85 Ω +/-20%(Impedence may vary whendifferent platform used)

Single-ended Impedance

50 Ω +/-15%

Trace width / differential pairs Spacing (intra-pair)

PCB stack-up dependent

Spacing between RX and TX pairs (inter-pair)Min. 20mils

Spacing between differential pairs and high-speed periodic signals

Min. 50mils

Spacing between differential pairs and low-speed non periodic

Min. 20mils

signals
Length matching between differential pairs (intra-pair)Max. 5mils

Length matching between RX and TX pairs (inter-pair)No strict length-matchingrequirements.

Spacing from edge of plane

Min. 40mils

Via Usage

maximum of 2 vias

AAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.6 LVDS
Each COM Express LVDS channel consists of four differential data pairs and a differential
clock pair for a total of five differential pairs per channel. COM Express Modules and Module
chipsets may not use all pairs.
3.3.6.1 Signal Definitions
Table 3-12: LVDS Signal Definitions
Pin Type

SignalDescription

I/O

A71

Type 6

LVDS_A0+

LVDS channel A differential signal

O LVDS

A72

Type 10

LVDS_A0-

pair 0A73

Type 6

LVDS_A1+

LVDS channel A differential signal

A74

Type 10

LVDS_A1-

pair 1

A75

Type 6

LVDS_A2+

LVDS channel A differential signal

A76

Type 10

LVDS_A2-

pair 2

A78

Type 6

LVDS_A3+

LVDS channel A differential signal

A79

Type 10

LVDS_A3-

pair 3

A81

Type 6

LVDS_A_CK+LVDS channel A differential clock pairO LVDS

A82

Type 10

LVDS_A_CK-

B71

Type 6

LVDS_B0+

LVDS channel B differential signal

O LVDS

LVDS_B0-

pair 0

LVDS_B1+

LVDS channel B differential signal

LVDS_B1-

pair 1

LVDS_B2+

LVDS channel B differential signal

LVDS_B2-

pair 2

LVDS_B3+

LVDS channel B differential signal

LVDS_B3-

pair 3

LVDS_B_CK+LVDS channel B differential clock pairO LVDS

LVDS_VDD_EN

LVDS flat panel power enable.

O 3.3V, CMOSLVDS_BKLT_EN

LVDS flat panel backlight enable highO 3.3V, CMOS

B72
B73

Type 6B74
B75Type 6B76
B77

Type 6B78
B81

Type 6

B82
A77

O LVDSO LVDSO LVDSO LVDSO LVDSO LVDS

LVDS_B_CKType 6
Type 10B79Type 6
Type 10

B83

Type 6

active signal
LVDS_BKLT_CTRL

Type 10
A83

Type 6

Type 6

O 3.3V, CMOS

control
LVDS_I2C_CKType 10A84

LVDS flat panel backlight brightness

DDC I2C clock signal used for flat panel

O 3.3V, CMOS

detection and control.
LVDS_I2C_DAT

Type 10AAEON Technology Inc.

DDC I2C data signal used for flat panel

I/O 3.3V,

detection and control.

OD CMOS

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Focus • Agility • Competitiveness3.3.6.2 LVDS Reference Schematics
Figure 3-9 LVDS Reference Schematic

Note : TVS placement must be close to Connector for ESD Solution .

AAEON Technology Inc.

www.aaeon.com
Focus • Agility • Competitiveness3.3.6.3 LVDS Layout Recommendations
Table 3-13: LVDS Trace Routing Guidelines
Parameter

Trace Routing

Max signal line length to the LVDS connector

8.75 inches

Carrier Board Signal length

6.75 inches

Differential Impedance

100 Ω +/-20%(Impedence may vary when different LVDS IC used)

Single-ended Impedance

55 Ω +/-15%

Trace width / differential pairs Spacing (intrapair)

PCB stack-up dependent

Spacing between pair to pairs (inter-pair)Min. 20mils

Spacing between differential pairs and highspeed periodic signals

Min. 20mils

Spacing between differential pairs and low-

Min. 20mils

speed non periodic signals
Length matching between differential pairs(intra-pair)+/- 20mils

Length matching between clock and data pairs(inter-pair)+/- 20mils

Length matching between data pairs+/- 40mils

Spacing from edge of plane+/- 40mils

Reference plane

GroundVia Usage

Max. of 2 vias per line

AAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.7

Embedded DisplayPort

3.3.7.1 Signal Definitions
Table 3-14: Embedded DisplayPort Signal Definitions
Pin Type

SignalDescription

I/O

A75

eDP_TX0+eDP lane 0, TX +O PCIeeDP_TX0-eDP lane 0, TX -O PCIeeDP_TX1+

eDP lane 1, TX +O PCIeeDP_TX1-

eDP lane 1, TX -O PCIeeDP_TX2+

eDP lane 2, TX +O PCIeeDP_TX2-

eDP lane 2, TX -O PCIeeDP_TX3+

eDP lane 3, TX +O PCIeeDP_TX3-

eDP lane 3, TX -O PCIeeDP_VDD_ENeDP power enable

O CMOS

eDP_BLKT_EN

eDP backlight enable

O CMOS

eDP_BLKT_CTRL

EDP backlight brightness control

O CMOS

eDP_AUX+eDP auxiliary lane +I/O PCIeeDP_AUX-eDP auxiliary lane -I/O PCIeeDP_HPD

Detection of Hot Plug / Unplug andI CMOSType 6
Type 10A76

Type 6
Type 10A73

Type 6
Type 10A74Type 6
Type 10A71

Type 6
Type 10A72Type 6
Type 10

A81

Type 6
Type 10A82Type 6
Type 10

A77

Type 6
Type 10B79Type 6
Type 10

B83

Type 6
Type 10

A83

Type 6
Type 10

A84

Type 6
Type 10

A87

Type 6
Type 10AAEON Technology Inc.

notification of the link layer

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Focus • Agility • Competitiveness3.3.7.2 Embedded DisplayPort Reference Schematics
Figure 3-10 eDP Reference Schematic

3.3.7.3 Embedded DisplayPort Layout Recommendations: BY PLATFORM LAYOUT GUIDEAAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.8 VGA
The COM Express Specification defines an analog VGA RGB interface for all Module types.
3.3.8.1 Signal Definitions
Table 3-15: VGA Signal Definitions
Pin Type

SignalDescription

I/O

B89

VGA_REDRed component of analog DAC monitor

O Analog

Type 6

output, designed to drive a 37.5Ω
equivalent load.
B91

Type 6

VGA_GRN

Green component of analog DAC monitor

O Analog

output, designed to drive a 37.5Ω
equivalent load.
B92

Type 6

VGA_BLU

Blue component of analog DAC monitor

O Analog

output, designed to drive a 37.5Ω
equivalent load.
B93

Type 6

VGA_HSYNC

Horizontal sync output to VGA monitor.

O 3.3V CMOS

B94

Type 6

VGA_VSYNC

Vertical sync output to VGA monitor.

O 3.3V CMOS

B95

Type 6

VGA_I2C_CKDDC clock line (I2C port dedicated toO 3.3V CMOS

identify VGA monitor capabilities).
B96

Type 6

VGA_I2C_DATAAEON Technology Inc.

DDC data line.

I/O 3.3V CMOS

www.aaeon.com
Focus • Agility • Competitiveness3.3.8.2 VGA Reference Schematics
Figure 3-11 VGA Connector Reference Schematic

Note : CM2009 placement must be close to Connector for ESD Solution .

3.3.8.3 VGA Layout Recommendations : BY PLATFORM LAYOUT GUIDEAAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.9 Digital Display
Module Types 6 and 10 use Digital Display Interfaces (DDI) to provide DisplayPort, HDMI/DVI,
and SDVO interfaces. Type 10 Modules can contain a single DDI (DDI[0]) that can support
DisplayPort, HDMI/DVI, and SDVO. Type 6 Modules can contain up to 3 DDIs (DDI[1:3]) of
which DDI[1:3] can support DisplayPort, HDMI/DVI.
3.3.9.1 Signal Definitions
Table 3-16: Digital Display Signal Definitions
COM Express
Pin Name

DDI0
Type 10DDI1Type 6DDI2Type 6DDI3Type 6Function(DDIX) Function (DDIX)
DisplayPort
HDMI / DVI

DDIX_PAIR0+

B71

D26

D39

C39

DPX_LANE0+

TMDSX_DATA2+

DDIX_PAIR0-

B72

D27

D40

C40

DPX_LANE0-

TMDSX_DATA2-

DDIX_PAIR1+

B73

D29

D42

C42

DPX_LANE1+TMDSX_DATA1+

DDIX_PAIR1-

B74

D30

D43

C43

DPX_LANE1-TMDSX_DATA1-

DDIX_PAIR2+

B75

D32

D46

C46

DPX_LANE2+TMDSX_DATA0+

DDIX_PAIR2-

B76

D33

D47

C47

DPX_LANE2-TMDSX_DATA0-

DDIX_PAIR3+

B81

D36

D49

C49

DPX_LANE3+TMDSX_CLK+

DDIX_PAIR3-

B82

D37

D50

C50

DPX_LANE3-TMDSX_CLK-

DDIX_HPD

B89

C24

D44

C44

DPX_HPDHDMIX_HPD

DDIX_CTRLCLK_AUX+

B98

D15

C32

C36

DPX_AUX+HDMIX_CTRLCLK

DDIX_CTRLDATA_AUX-

B99

D16

C33

C37

DPX_AUX-HDMIX_CTRLDATA

DDIX_DDC_AUX_SEL

B95

D34

C34

C38

AAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.9.2 Digital Display Reference Schematics
Figure 3-12 DP Connector Reference Schematic
2

2

DDI0_PAIR0+2
2

DDI0_PAIR0DDI0_PAIR1+

2
2

DDI0_PAIR1DDI0_PAIR2+

2
2

DDI0_PAIR2DDI0_PAIR3+

2

DDI0_PAIR3-

C334

0.1uF C0402

DP0_PAIR0+

C325
C337

0.1uF C0402
0.1uF C0402

DP0_PAIR0DP0_PAIR1+

C335
C339

0.1uF C0402
0.1uF C0402

DP0_PAIR1DP0_PAIR2+

C338
C341

0.1uF C0402
0.1uF C0402

DP0_PAIR2DP0_PAIR3+

C340

0.1uF C0402

DP0_PAIR3-

DDI0_DDC_AUX_SEL

R571
1M
R0402

2

DDI0_CTRLCLK_AUX+

R572
2
5M

DDI0_CTRLDATA_AUX-

DP0_AUX+
DP0_AUXDP0_HPD

R0402

2

+3V3
FB30
30ohm(100MHz)
L0603
+3V3

LANE0P
GND1
LANE0NLANE1P
GND2
LANE1NLANE2P
GND3
LANE2NLANE3P
GND4
LANE3NCONFIG1
CONFIG2
AUXP
GND7
GND12
AUXN
GND11
HPD
GND10
RTN_PWR GND9
PWR
GND8

D

DP0_PAIR0+
DP0_PAIR0DP0_PAIR1+
DP0_PAIR1-

U64
Line-1NC1
Line-2NC2
GND GND1
Line-3NC3Line-4
NC4

10
9
8
7
6

AZ1045-04F

25
24
23
22
21

DP0_PAIR2+
DP0_PAIR2DP0_PAIR3+
DP0_PAIR3-

1
2
3
4
5

20P 3VD51203-H7JJ-4H

U63
Line-1NC1
Line-2NC2
GND GND1
Line-3NC3Line-4
NC4

10
9
8
7
6

AZ1045-04F

FB28
30ohm(100MHz)
L0603

DP0_AUX+
DP0_AUX-

DDI0_HPD

1
2
3
4
5

DP0_HPD

2

1
2
3
4
5

U62
Line-1NC1
Line-2NC2
GND GND1
Line-3NC3Line-4
NC4

10
9
8
7
6

AZ1045-04F

Q57
2N7002WT1G
TS-SOT323_GSD

S

G

S

R199
100K
R0603

C0603

CN30

R797
4.7K
R0603

D
G

C162
0.1uF

D38
MBR130T1G
TS-SOD123-1

+3V3

R796
4.7K
R0603

DP0_HPD

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Q58
2N7002WT1G
TS-SOT323_GSD

Note: TVS placement must be close to Connector for ESD Solution.

AAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.9.3 Digital Display Layout Recommendations
Table 3-17: DisplayPort Trace Routing Guidelines
Parameter

Trace Routing

Transfer Rate

Max. 5.4 GBit/s

Carrier Board Signal length

3.2 inches

Differential Impedance

85 Ω +/-10%(Impedence may vary when different platform used)

Single-ended Impedance

50 Ω +/-15%

Trace width / differential pairs Spacing(intra-pair)

PCB stack-up dependent

Spacing between pair to pairs

Min. 15mils

Spacing between differential pairs and high- Min. 15mils
speed periodic signals
Spacing between differential pairs and low-

Min. 15mils

speed non periodic signals
Length matching between differential pairs(intra-pair)Max. 5mils

Length matching between differential pairs(inter-pair)Max 1 inch

Spacing from edge of plane

Min. 40mils

Via Usage

Max. 2

AC coupling capacitors

100nF

AAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.10 Digital Audio
The COM Express Specification allocates seven pins on the A-B connector to support digital
AC’97 and HD interfaces to audio Codecs on the Carrier Board. The pins are available on all
Module types. High-definition (HD) audio uses the same digital-signal interface as AC ’97
audio. Codecs for AC ’97 and HD Audio are different.
3.3.10.1 Signal Definitions
Table 3-18: Digital Audio Signal Definitions
Pin Type

SignalDescription

I/O

A29

AC/HDA_SYNC

Serial Sample Rate Synchronization.

O 3.3V

Type 6CMOS

Type 10A30Type 6

AC/HDA_RST#

CODEC Reset.

O 3.3V Suspend
CMOS

Type 10A32Type 6

AC/HDA_BITCLKType 10A33Type 6

AC/HDA_SDOUT

24 MHz Serial Bit Clock for HDA

O 3.3V

CODEC.

CMOS

Audio Serial Data Output Stream.

O 3.3V
CMOS

Type 10B28Type 6

AC/HDA_SDIN2

Type 10B29Type 6

AC/HDA_SDIN1

Type 10B30Type 6

AC/HDA_SDIN0

Type 10AAEON Technology Inc.

Audio Serial Data Input Stream fromI 3.3V Suspend

CODEC[0:2].

CMOS

Audio Serial Data Input Stream fromI 3.3V Suspend

CODEC[0:2].

CMOS

Audio Serial Data Input Stream fromI 3.3V Suspend

CODEC[0:2].

CMOS

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Focus • Agility • Competitiveness3.3.10.2 Digital Audio Reference Schematics
Figure 3-13 Audio Jack Reference Schematic

Note : VDR placement must be close to Connector for ESD Solution .

3.3.10.3 Digital Audio Layout Recommendations : BY PLATFORM LAYOUT GUIDEAAEON Technology Inc.

www.aaeon.com
Focus • Agility • Competitiveness3.3.11 LPC
COM Express is designed to be a legacy free standard for embedded modules. It does notsupport legacy functionality on the Module, such as PS/2 keyboard/mouse, serial ports, andparallel ports. It provides an LPC interface that can be used to add peripheral devices to the
Carrier Board design. AAEON can provide the available LPC IO schematic for customer’sreference design.
3.3.11.1 Signal Definitions
Table 3-19: LPC Signal Definitions
Pin Type

SignalDescription

I/O

A50

LPC_SERIRQ

LPC serialized IRQ.

I/O 3.3V

Type 6,7
Type 10B3Type 6,7

CMOS
LPC_FRAME#

Type 10
B4

LPC frame indicates start of a new

O 3.3V

cycle or termination of a broken cycle.

CMOS

LPC_AD0

B5Type 6,7

LPC_AD1

LPC multiplexed command, address

I/O 3.3V

B6Type 10

LPC_AD2and data.

CMOS

LPC encoded DMA/Bus master request.

I 3.3VB7

LPC_AD3B8Type 6,7

LPC_DRQ0#

B9Type 10

LPC_DRQ1#

B10

Type 6,7

LPC_CLKCMOS
LPC clock output 33MHz.

Type 10

O 3.3V
CMOS

3.3.11.2 LPC Reference Schematics
Figure 3-14 LPC Debug Connector Reference Schematic

AAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.11.3 LPC Layout Recommendations
Table 3-20: LPC Trace Routing Guidelines
Parameter

Trace Routing

Transfer Rate @ 33MHz

16 MBit/s

Carrier Board Max data and control signal length

15.0 inches

Carrier Board Max clock signal length

8.88 inches

Single-ended Impedance

55 Ω +/-15%(Impedence may vary whendifferent platform used)

Trace width / Spacing between signals (intersignal)

PCB stack-up dependent

Length matching between
single ended / clock signals

Max. 200mils

Spacing from edge of plane

Min. 40mils

Reference plane

GroundVia Usage

Try to minimize number of vias

AAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.12 SPIThe SPI interface is defined in this specification to service as an off-module option for BIOS
storage. The SPI interface replaces the LPC Firmware Hub interface, which is now considered alegacy interface for firmware storage (LPC does continue to be used for SuperIO connectivity).
3.3.12.1 Signal Definitions
Table 3-21: SPI Signal Definitions
Pin Type

SignalDescription

I/O

B97

SPI_CS#

Chip select for Carrier Board SPI – may

O CMOS –be sourced from chipset SPI0 or SPI1

3.3V Suspend

Data in to Module from Carrier SPII CMOS –Type 6,7
Type 10A92

Type 6,7

SPI_MISO

Type 10
A95

Type 6,7

3.3V Suspend
SPI_MOSI

Data out from Module to Carrier SPI

Type 10A94

Type 6,7

3.3V Suspend
SPI_CLK

Clock from Module to Carrier SPI

Type 10
A91

Type 6,7

O CMOS –O CMOS –3.3V Suspend

SPI_POWER

Type 10

Power supply for Carrier Board SPI –O – 3.3V

sourced from Module – nominallySuspend

3.3V.

The Module shall provide aminimum of 100mA on SPI_POWER.
Carriers shall use less than 100mA of
SPI_POWER.
SPI_POWER shall only be used to
power SPI devices on the Carrier.
A34

Type 6,7

BIOS_DIS0#

Type 10

Selection strap to determine the BIOS

I CMOSboot device. The Carrier should only
float these or pull them low, pleaserefer to for strapping options of BIOS
disable signals.

B88

Type 6,7
Type 10

BIOS_DIS1#

Selection strap to determine the BIOS

I CMOSboot device. The Carrier should only
float these or pull them low.

AAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.12.2 SPI Reference Schematics
Figure 3-15 SPI Connector Reference Schematic

Note: SPI Signals must be added isolation circuit(level shift or N MOSFET) for System protection.

3.3.12.3 SPI Layout Recommendations : BY PLATFORM LAYOUT GUIDEAAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.13 I2C
The I2C (Inter-Integrated Circuit) bus is a two-wire serial bus originally defined by Philips. The
bus is used for low-speed (up to 400kbps) communication between system ICs. The bus is often
used to access small serial EEPROM memories and to set up IC registers. The COM Express
Specification defines several I2C interfaces that are brought to the Module connector for use on
the Carrier. Some of these interfaces are for very specific functions (VGA, LVDS, and DDIX),
one interface is the SMBus used primarily for management and one other interface is a general
purpose I2C interface. Since COM.0 Rev. 2.0 this interface should support multi-master
operation. This capability will allow a carrier to read an optional module EEPROM before
powering up the module.
3.3.13.1 Signal Definitions
Table 3-22: I2C Signal Definitions
Pin Type

SignalDescription

I/O

B33

I2C_CK

General Purpose I2C Clock output

I/O OD

Type 6,7
Type 10B34Type 6,7
Type 10AAEON Technology Inc.

CMOS
I2C_DAT

General Purpose I2C data I/O line.

I/O OD
CMOS

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Focus • Agility • Competitiveness3.3.14 SMBus
The SMBus is primarily used as an interface to manage peripherals such as serial presence detect (SPD)on RAM, thermal sensors, PCI/PCIe devices, smart battery, etc. The devices that can connect to the
SMBus can be located on the Module and Carrier. The SMBus is similar to I2C. I2C devices have thepotential to lock up the data line while sending information and require a power cycle to clear the fault
condition. SMBus devices contain a timeout to monitor for and correct this condition. Designers are
urged to use SMBus devices when possible over standard I2C devices.
3.3.14.1 SMBus Signal Definitions
Table 3-23: SMBus Signal Definitions
Pin Type

SignalDescription

I/O

B13

SMB_CK

System Management Bus bidirectional

I/O ODclock line

CMOS

System Management bidirectional data

I/O OD

line.

CMOS

System Management Bus Alert

I

Type 6,7
Type 10B14Type 6,7

SMB_DAT

Type 10B15Type 6,7
Type 10AAEON Technology Inc.

SMB_ALERT#

CMOS

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Focus • Agility • Competitiveness3.3.15 CANBUS
CAN bus is a vehicle bus standard designed to allow controllers and devices to communicate
with each other without a host computer. CAN bus is a message-based protocol, designed
specifically for automotive applications but now also used in other areas such as industrial
automation and medical equipment.
3.3.15.1 Signal Definitions
Table 3-24: CANBUS Signal Definitions
Pin

Type

SignalDescription

I/O

A101

Type 6,7

SER1_TX

Transmit Line for CAN

O CMOS(can be shared with SER1 function)(protected)

Receive Line for CAN

I CMOS(can be shared with SER1 function)(protected)

Type 10A102Type 6,7
Type 10

SER1_RX3.3.15.2 CANBUS Reference Schematics
Figure 3-16 CANBUS Connector Reference Schematic

Note : VDR placement must be close to Connector for ESD Solution .
3.3.15.3 CANBUS Layout Recommendations : BY PLATFORM LAYOUT GUIDEAAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.16 RTC Battery
The Real Time Clock (RTC) is responsible for maintaining the time and date even when the COM
Express Module is not connected to a main power supply. Usually a +3V lithium battery cell isused to supply the internal RTC of the Module. The COM Express Specification defines an extra
power pin 'VCC_RTC', which connects the RTC of the Module to the external battery. The specified input
voltage range of the battery is defined between +2.0V and +3.0V. The signal'VCC_RTC' can be found on the Module's connector row A pin A47.
3.3.16.1 Signal Definitions
Table 3-25: RTC Battery Signal Definitions
Pin

Type

SignalDescription

I/O

A47

Type 6,7

VCC_RTC

General purpose input pins.

I 3.3V

Pulled high internally on the Module.

CMOS

Type 103.3.16.2 RTC Battery Reference Schematics
Figure 3-17 RTC Connector Reference Schematic

3.3.16.3 RTC Battery Layout Recommendations : BY PLATFORM LAYOUT GUIDEAAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.17 DIO
General Purpose Input / Output (GPIO)
3.3.17.1 Signal Definitions
Table 3-26: DIO Signal Definitions
Pin

Type

A54

SignalDescription

GPI0

General purpose input pins.
Pulled high internally on the Module.

A63

Type 6,7

GPI1

A67

Type 10

GPI2

I/O
I 3.3V
CMOS

A85

GPI3

A93

GPO0

General purpose output pins.

B54

Type 6,7

GPO1

Upon a hardware reset, these outputs

O 3.3V

B57

Type 10GPO2

should be low.

CMOS

B63

GPO3

3.3.17.2 DIO Reference Schematics
Figure 3-18 DIO Connector Reference Schematic

Note :(1) TVS placement must be close to Connector for ESD Solution .
(2) SDIO and DIO share the GPIO pin .

3.3.17.3 DIO Layout Recommendations : BY PLATFORM LAYOUT GUIDEAAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.18 SDIOSD Card support was added in COM.0 Rev. 2.0 as an alternative use for the GPIO pins.
3.3.18.1 Signal Definitions
Table 3-27: SDIO Signal Definitions
Pin

Type

A54

COM Express
SignalSD CardInterface Signals

GPI0

SD_DATA0A63

Type 6,7

GPI1

SD_DATA1

A67

Type 10

GPI2

SD_DATA2

A85

GPI3

SD_DATA3

A93

GPO0

SD_CLK

B54

Type 6,7

GPO1

SD_CMD

B57

Type 10

GPO2

SD_WP

GPO3

SD_CD#

B63

3.3.18.2 SDIO Reference Schematics
Figure 3-19 SDIO Connector Reference Schematic

Note :(1) TVS placement must be close to Connector for ESD Solution .
(2) SDIO and DIO share the GPIO pin .

3.3.18.3 SDIO Layout Recommendations : BY PLATFORM LAYOUT GUIDEAAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.19 Serial Interface
General Purpose Serial Interface ,Since Revision 2.0 of the COM Express specification two optional serial
ports are available on Type 10 and Type 6 COM Express Modules uses pins on the A-B connector.
3.3.19.1 Signal Definitions
Table 3-28: Serial Interface Signal Definitions
Pin

Type

SignalDescription

I/O

A98

Type 6,7

SER0_TX

Transmit Line for Serial Port 0

O CMOSType 10
A99

Type 6,7(protected)
SER0_RX

Receive Line for Serial Port 0

I CMOSType 10A101

Type 6,7(protected)
SER1_TX

Type 10A102Type 6,7
Type 10

SER1_RXTransmit Line for Serial Port 1

O CMOS(can be shared with CAN function)(protected)

Receive Line for Serial Port 1 (can be

I CMOS

shared with CAN function)(protected)

3.3.19.2 Serial Interface Reference Schematics : BY PLATFORM LAYOUT GUIDE
3.3.19.3 Serial Interface Layout Recommendations : BY PLATFORM LAYOUT GUIDEAAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.20 Power Management Signals
3.3.20.1 Signal Definitions
Table 3-29: Power Management Signal Definitions
Pin Type

SignalDescription

I/O

B12

PWRBTN#Power button low active signal used to wake up the

I 3.3V Suspend

system from S5 state (soft off). This signal is triggered

CMOS

Type 6,7
Type 10on the falling edge.
B49

Type 6,7

SYS_RESET#

Type 10

Reset button input.
reset and reboot.

Active low request for Module to
May be falling edge sensitive.

For

I 3.3V Suspend
CMOS

situations when SYS_RESET# is not able to reestablish
control of the system, PWR_OK or a power cycle may be
used.
B50

Type 6,7

CB_RESET#

Type 10

Reset output signal from Module to Carrier Board.

O 3.3VThis signal may be driven low by the Module to reset

Suspend CMOS

external components located on the Carrier Board.
B24

Type 6,7

PWR_OK

Type 10

Power OK status signal generated by the ATX power

I 3.3V

supply to notify the Module that the DC operating

CMOS

voltages are within the ranges required for proper
operation.
B18

Type 6,7

SUS_STAT#

Type 10Suspend status signal to indicate that the system will

O 3.3Vbe entering a low power state soon.

Suspend CMOS

It can be usedby other peripherals on the Carrier Board as anindication that they should go into power-down mode.
A15Type 6,7

SUS_S3#

Type 10A18Type 6,7

SUS_S4#

Type 10A24Type 6,7

SUS_S5#

Type 10B66Type 6,7

WAKE0#

S3 Sleep control signal indicating that the system

O 3.3V

resides in S3 state (Suspend to RAM).

Suspend CMOS

S4 Sleep control signal indicating that the system

O 3.3V

resides in S4 state (Suspend to Disk).

Suspend CMOS

S5 Sleep Control signal indicating that the system

O 3.3V

resides in S5 State (Soft Off).

Suspend CMOSPCI Express wake-up event signal.

I 3.3V Suspend

Type 10B67Type 6,7

CMOS
WAKE1#

General purpose wake-up signal.

I 3.3V Suspend

Type 10A27Type 6,7

CMOS
BATLOW#

Type 10

Battery low input. This signal may be driven low by

I 3.3V Suspend

external circuitry to signal that the system battery is

CMOS

low.

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Focus • Agility • Competitiveness3.3.20.2 Power Management Reference Schematics
Figure 3-20 PWRBTN# Reference Schematic

Figure 3-21 CB_RESET# Reference Schematic

Figure 3-22 PWR_OK Reference Schematic

3.3.20.3 Power Management Layout Recommendations : BY PLATFORM LAYOUT GUIDEAAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.21 FAN Connector
3.3.21.1 Signal Definitions
Table 3-30: FAN Connector Signal Definitions
Pin

Type

SignalDescription

B101

Type 6,7

FAN_PWMOUT

Fan speed control.

Type 10B102Type 6,7

FAN_TACHIN

I/O
Uses the Pulse Width Modulation

O 3.3V(PWM) technique to control the fan’s RPM.

CMOS OD

Fan tachometer input for a fan with a two pulse output.

I 3.3V

Type 10CMOS OD

3.3.21.2 FAN Connector Reference Schematics
Figure 3-23 FAN Connector Reference Schematics

3.3.21.3 FAN Connector Layout Recommendations : BY PLATFORM LAYOUT GUIDEAAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.22

Miscellaneous Signals

3.3.22.1 Signal Definitions
Table 3-31: Miscellaneous Signals Definitions
Pin

Type

C54
C57

Type 6,7

D57

SignalDescription

I/O

TYPE0#The TYPE pins indicate to the Carrier Board the Pin-out Type

O 5V

TYPE1#

that is implemented on the Module.

The pins are tied on the

PDS

TYPE2#

Module to either ground (GND) or areno-connects (NC).

For

Pin-out Type 1 and Type 10, these pins are not present (X).
TYPE0#TYPE1#

TYPE2#

GND

NC

NC

Pin-out Type 6

The Carrier Board should implement combinatorial logic thatmonitors the Module TYPE pins and keeps power off (e.g.
deactivates the ATX_ON signal for an ATX power supply) if an
incompatible Module pin-out type is detected.

The Carrier

Board logic may also implement a fault indicator such as an LED.
A97

Type 6,7

TYPE10#Type 10

Indicates to the Carrier Board that a Type 10 Module isinstalled.

Indicates to the Carrier Board, that a Rev 1.0/2.0

Module is installed.
TYPE10#B32

Type 6,7

SPKR

Type 10B27Type 6,7

WDT

Type 10A103Type 6,7

LID#

Type 10NC

Pin-out R2.0

PD

Pin-out Type 10 pull down to ground with 47k

12V

Pin-out R1.0

Output used to control an external FET or a logic gate to drive

O 3.3Van external PC speaker.

CMOS

Output indicating that a watchdog time-out event has

O 3.3Voccurred.

CMOS

LID switch.

I 3.3V

Low active signal used by the ACPI operating system for a LID

CMOS OD

switch.
B103

Type 6,7

SLEEP#

Type 10Sleep button.

I 3.3V

Low active signal used by the ACPI operating system to

CMOS OD

bring the system to sleep state or to wake it up again.
A96

Type 6,7

TPM_PP

Type 10

Trusted Platform Module (TPM) Physical Presence pin.

I 3.3V

Active high.

CMOS

TPM chip has an internal pull down.

This signal

is used to indicate Physical Presence to the TPM.

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Focus • Agility • Competitiveness3.3.22.2 Miscellaneous Signals Schematics
Figure 3-24 LID# and SLEEP# Reference Schematic

Figure 3-25 WDT Reference Schematic

Figure 3-26 SPKR Reference Schematic

3.3.22.3 Miscellaneous Signals Layout Recommendations : BY PLATFORM LAYOUT GUIDEAAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.23 10G Interface
10GBASE-KR support was added to COM Express with revision 3.0 of the specification.
Type 7 supports up to four 10GBASE-KR interfaces. The 10G MAC is located on the Module and
the PHY is located on the Carrier. 10GBASE-KR uses a single transmit and a single receive ac coupled
differential pair for data and a sideband bus for the PHY control and configuration. COM Express
supports both MDIO and I2C control interfaces for the PHY.
The PHY control interfaces are grouped into pairs. 10G Ports 0 and 1 share a common PHY
control interface and 10G ports 2 and 3 share a common PHY control interface. The PHY interface
selection is made using the 10G_PHY_CAP_01 and 10G_PHY_CAP_23 pins. The Carrier design canselect the PHY that is appropriate for the design. The Module designer should design the module insuch a way that it can provide the PHY interface that is selected regardless of the capabilities of thesilicon used on the Module. Appropriate level shifters shall be used.
A two wire I2C bus (designated 10G_LED_SDA and 10G_LED_SCL) is defined to serialize theoutbound (Module to Carrier) MAC LED and PHY strapping signals, conserving COM Express pins.
The Carrier should use a PCA9539 or compatible I2C I/O expander. The Carrier PCA9539 shall bemapped to I2C address 1110 100x (x=R/W bit). Table 14 below defines the port pin mapping for the
I/O expander.
There are two pairs of PHY strapping signals defined. The first pair is designated as
10G_PHY_CAP_01 and 10G_PHY_CAP_23. These are actual COM Express pins. They are inputs to
the COM Express Module. The Carrier may either tie these lines to GND or leave them NC on the
Carrier. If 10G_PHY_CAP_01 is tied low on the Carrier, this indicates to the Module that the PHY on
the Carrier for 10G interfaces 0 and 1 can be configured by either I2C or by MDIO. If the Carrier
leaves the line NC, then this indicates to the Module that the Carrier PHY can only be configured by
MDIO. Similarly for strap signal 10G_PHY_CAP_23 and 10G interfaces 2 and 3.
The second pair of PHY strapping signals are outputs from the Module, serialized onto the
10G_LED_Sxx I2C bus. They are desterilized on the Carrier I/O expander and may used to set Carrier
PHY strapping pins to set the desired Carrier PHY configuration mode, if the PHY is capable ofmultiple configuration modes.
This arrangement with a pair of input straps (telling the Module what configuration modes are
possible on the Carrier PHY) and a pair of serialized output straps (telling the Carrier PHY what
configuration mode to use) allow Module designs that can use a variety of PHYs. In particular, Intel
Broadwell DE Modules that can be used with either Intel "Coppervale" PHYs or with Inphy / Cortina
PHYs can be realized.

AAEON Technology Inc.

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Focus • Agility • Competitiveness3.3.23.1 Signal Definitions
Table 3-32: 10G Interface Signal Definitions
Pin Type

SignalDescription

I/O

D49

10G_KR_TX0+

10GBASE-KR port, transmit output differential

O KR

10G_KR_TX0-

pairs.

Type 7

D50

Carrier board:
Device - Connect AC Coupling cap 0.1uF near
PHY. N/C if not used.
C49

Type 7C50

10G_KR_RX0+

10GBASE-KR port, receive input differential pairs.

10G_KR_RX0-

Module has integrated AC Coupling Capacitor.

I KR

Carrier board:N/C if not used.N/C if not used.
D42Type 7

D43

10G_KR_TX1+

10GBASE-KR port, transmit output differential

10G_KR_TX1-

pairs.

O KR

Carrier board:
Device - Connect AC Coupling cap 0.1uF near
PHY. N/C if not used.
C42

Type 7

C43

10G_KR_RX1+

10GBASE-KR port, receive input differential pairs.

10G_KR_RX1-

Module has integrated AC Coupling Capacitor.

I KR

Carrier board:N/C if not used.N/C if not used.
D29Type 7D30

10G_KR_TX2+

10GBASE-KR port, transmit output differential

10G_KR_TX2-

pairs.

O KR

Carrier board:
Device - Connect AC Coupling cap 0.1uF near
PHY. N/C if not used.
C29

Type 7C30

10G_KR_RX2+

10GBASE-KR port, receive input differential pairs.

10G_KR_RX2-

Module has integrated AC Coupling Capacitor.

I KR

Carrier board:N/C if not used.N/C if not used.
D26

Type 7

D27

10G_KR_TX3+

10GBASE-KR port, transmit output differential

10G_KR_TX3-

pairs.

O KR

Carrier board:
Device - Connect AC Coupling cap 0.1uF near
PHY. N/C if not used.
C26
C27

Type 7

10G_KR_RX3+

10GBASE-KR port, receive input differential pairs.

10G_KR_RX3-

Module has integrated AC Coupling Capacitor.

I KR

Carrier board:

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Focus • Agility • CompetitivenessN/C if not used.N/C if not used.
D49

Type 7

D50

10G_KR_TX0+

10GBASE-KR port, transmit output differential

10G_KR_TX0-

pairs.

O KR

Carrier board:
Device - Connect AC Coupling cap 0.1uF near
PHY. N/C if not used.
D46

Type 7

10G_PHY_MDIO_SDA0

MDIO Mode: Management Data I/O interface

OC MOSmode data signal for serial data transfers

3.3V

between the MAC and an external PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
I2C Mode: I2C data signal, of the 2-wire

I/O OD

management interface used for serial data

CMOS

transfers between the MAC and an external

3.3V

PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
C46

Type 7

10G_PHY_MDIO_SCL0

MDIO Mode: Management Data I/O interface

OC MOSmode data signal for serial data transfers

3.3V

between the MAC and an external PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
I2C Mode: I2C Clock signal, of the 2-wire

I/O OD

management interface used for serial data

CMOS

transfers between the MAC and an external

3.3V

PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
D45

Type 7

10G_PHY_MDIO_SDA1

MDIO Mode: Management Data I/O interface

OC MOSmode data signal for serial data transfers

3.3V

between the MAC and an external PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
I2C Mode: I2C data signal, of the 2-wire

AAEON Technology Inc.

I/O ODwww.aaeon.com
Focus • Agility • Competitivenessmanagement interface used for serial data

CMOS

transfers between the MAC and an external

3.3V

PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
C45

Type 7

10G_PHY_MDIO_SCL1

MDIO Mode: Management Data I/O interface

OC MOSmode data signal for serial data transfers

3.3V

between the MAC and an external PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
I2C Mode: I2C Clock signal, of the 2-wire

I/O OD

management interface used for serial data

CMOS

transfers between the MAC and an external

3.3V

PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
D16Type 7

10G_PHY_MDIO_SDA2

MDIO Mode: Management Data I/O interface

OC MOSmode data signal for serial data transfers

3.3V

between the MAC and an external PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
I2C Mode: I2C data signal, of the 2-wire

I/O OD

management interface used for serial data

CMOS

transfers between the MAC and an external

3.3V

PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
C16

Type 7

10G_PHY_MDIO_SCL2

MDIO Mode: Management Data I/O interface

OC MOSmode data signal for serial data transfers

3.3V

between the MAC and an external PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
I2C Mode: I2C Clock signal, of the 2-wire

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I/O ODwww.aaeon.com
Focus • Agility • Competitivenessmanagement interface used for serial data

CMOS

transfers between the MAC and an external

3.3V

PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
D15Type 7

10G_PHY_MDIO_SDA3

MDIO Mode: Management Data I/O interface

OC MOSmode data signal for serial data transfers

3.3V

between the MAC and an external PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
I2C Mode: I2C data signal, of the 2-wire

I/O OD

management interface used for serial data

CMOS

transfers between the MAC and an external

3.3V

PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
C15

Type 7

10G_PHY_MDIO_SCL3

MDIO Mode: Management Data I/O interface

OC MOSmode data signal for serial data transfers

3.3V

between the MAC and an external PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
I2C Mode: I2C Clock signal, of the 2-wire

I/O OD

management interface used for serial data

CMOS

transfers between the MAC and an external

3.3V

PHY.

SuspendCarrier board:/ 3.3V

Device-Connect to PHY circuit.
N/C if not used.
D35

Type 7

10G_PHY_CAP_01

PHY mode capability pin: Indicates if theI CMOSPHY for 10G lanes 0 and 1 is capable of

3.3V

configuration by I2C. High indicates

Suspend

MDIO-only configuration, and low indicates/ 3.3Vconfiguration capability via I2C or MDIO. The
actual protocol used for PHY configuration isdetermined by the module, in part based on

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Focus • Agility • Competitivenessthis input. The actual protocol used isindicated over the dedicated I2C interface(see Table 13)
Carrier board:
D34

Type 7

10G_PHY_CAP_23

PHY mode capability pin: Indicates if theI CMOSPHY for 10G lanes 0 and 1 is capable of

3.3V

configuration by I2C. High indicates

Suspend

MDIO-only configuration, and low indicates/ 3.3Vconfiguration capability via I2C or MDIO. The
actual protocol used for PHY configuration isdetermined by the module, in part based on
this input. The actual protocol used isindicated over the dedicated I2C interface(see Table 13)
Carrier board:
C39

D39

C38

D38

C33

Type 7

Type 7

Type 7

Type 7

Type 7

10G_SFP_SDA0

10G_SFP_SCL0

10G_SFP_SDA1

10G_SFP_SCL1

10G_SFP_SDA2

AAEON Technology Inc.

I2C data signal of the 2-wire management

I/O ODinterface used by the 10GbE controller to

CMOS

access the management registers of an

3.3V

external Optical SFP Module.

SuspendCarrier board:/ 3.3VI2C clock signal of the 2-wire management

I/O ODinterface used by the 10GbE controller to

CMOS

access the management registers of an

3.3V

external Optical SFP Module.

SuspendCarrier board:/ 3.3VI2C data signal of the 2-wire management

I/O ODinterface used by the 10GbE controller to

CMOS

access the management registers of an

3.3V

external Optical SFP Module.

SuspendCarrier board:/ 3.3VI2C clock signal of the 2-wire management

I/O ODinterface used by the 10GbE controller to

CMOS

access the management registers of an

3.3V

external Optical SFP Module.

SuspendCarrier board:/ 3.3VI2C data signal of the 2-wire management

I/O ODinterface used by the 10GbE controller to

CMOS

access the management registers of an

3.3V

external Optical SFP Module.

Suspendwww.aaeon.com
Focus • Agility • Competitiveness

D33

C32

D32

C37

Type 7

Type 7

Type 7

Type 7

10G_SFP_SCL2

10G_SFP_SDA3

10G_SFP_SCL3

10G_LED_SCL

Carrier board:/ 3.3VI2C clock signal of the 2-wire management

I/O ODinterface used by the 10GbE controller to

CMOS

access the management registers of an

3.3V

external Optical SFP Module.

SuspendCarrier board:/ 3.3VI2C data signal of the 2-wire management

I/O ODinterface used by the 10GbE controller to

CMOS

access the management registers of an

3.3V

external Optical SFP Module.

SuspendCarrier board:/ 3.3VI2C clock signal of the 2-wire management

I/O ODinterface used by the 10GbE controller to

CMOS

access the management registers of an

3.3V

external Optical SFP Module.

SuspendCarrier board:/ 3.3VI2C Clock of the 2-wire interface that transfers

I/O OD

LED and strap signals for I2C or MDIO operation

CMOS

of optical PHYs.

3.3V

Carrier board:

Suspend/ 3.3V

C35

C34

C47

Type 7

Type 7

Type 7

10G_PHY_RST_01

10G_PHY_RST_23

10G_INT0

Output signal that resets an optical PHY on port 0

O CMOSand port1 (with copper PHY this signal is not

3.3V

used).

SuspendCarrier board:/ 3.3V

Output signal that resets an optical PHY on port 0

O CMOSand port3 (with copper PHY this signal is not

3.3V

used).

SuspendCarrier board:/ 3.3VInterrupt pin from copper PHY or optical SFPI CMOS

Module to the 10GbE controller.

3.3V

Carrier board:

Suspend/ 3.3V

D47

Type 7

10G_INT1

Interrupt pin from copper PHY or optical SFPI CMOS

Module to the 10GbE controller.

3.3V

Carrier board:

Suspend/ 3.3V

C24

Type 7

10G_INT2

AAEON Technology Inc.

Interrupt pin from copper PHY or optical SFPI CMOS

Module to the 10GbE controller.

3.3V

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Focus • Agility • CompetitivenessCarrier board:

Suspend/ 3.3V

D24

Type 7

10G_INT3

Interrupt pin from copper PHY or optical SFPI CMOS

Module to the 10GbE controller.

3.3V

Carrier board:

Suspend/ 3.3V

C40

Type 7

10G_SDP00

Software-Definable Pins. Can also be used for

I/O

IEEE1588 support such as a 1pps signal. See

CMOSsection 2.6.2 for details.

3.3V
Suspend/ 3.3V

D40

Type 7

10G_SDP01

Software-Definable Pins. Can also be used for

I/O

IEEE1588 support such as a 1pps signal. See

CMOSsection 2.6.2 for details.

3.3V
Suspend/ 3.3V

C17

Type 7

10G_SDP02

Software-Definable Pins. Can also be used for

I/O

IEEE1588 support such as a 1pps signal. See

CMOSsection 2.6.2 for details.

3.3V
Suspend/ 3.3V

D17

Type 7

10G_SDP03

Software-Definable Pins. Can also be used for

I/O

IEEE1588 support such as a 1pps signal. See

CMOSsection 2.6.2 for details.

3.3V
Suspend/ 3.3V

C36

Type 7

10G_LED_SDA

AAEON Technology Inc.

I2C Data of the 2-wire interface that transfers

I/O ODLED signals and PHY straps for I2C or MDIO

CMOS

operation of optical PHYs.Refer to the details in

3.3V

table 14 ‘I2C Data Mapping to Carrier Board

Suspendbased PCA9539 I/O expander‘/ 3.3Vwww.aaeon.com
Focus • Agility • Competitiveness3.3.23.2 10G Interface Reference Schematics : BY PLATFORM LAYOUT GUIDE
Figure 3-27 10G Interface Reference Schematic-1

Figure 3-28 10G Interface Reference Schematic-2

Figure 3-29 10G Interface Reference Schematic-3

AAEON Technology Inc.

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Focus • Agility • CompetitivenessFigure 3-30 10G Interface Reference Schematic-4

3.3.23.3 10G Interface Layout Recommendations : BY PLATFORM LAYOUT GUIDETable 3-33: 10G Interface Layout Recommendations
Parameter

10GB LAN KR

Symbol Rate

10.0 Gb/s

Carrier Board Signal length

16.0 inches

Differential impedance

100 Ω +/-15%(Impedence may vary when different platform used)

Single-ended Impedance

50 Ω +/-15%

Trace width / Spacing between
differential pairs

PCB stack-up dependent

Spacing between RX and TX(inter-pair) / differential pairs
and low-speed non periodic
signalsMin. 20mils

Spacing between differential
pairs and high-speed periodic
signalsMin. 50mils

Length matching between

Max. 5mils

differential pairs (intra-pair)
Reference plane

GND referenced preferred

Length matching between RX
and TX pairs (inter-pair)No strict electrical requirements.Keep difference within a
3.0 inch delta to minimize latency.

Via Usage

Max. 2 vias per TX trace
Max. 2 vias per RX trace

AC coupling capacitors

Capacitor type: X7R, 100nF +/- 10%, 16V, shape 0402.

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Focus • Agility • Competitiveness3.3.24 NCSI Interface
The NC-SI (‘Network Controller Sideband Interface’) is an electrical interface and protocol
defined by the Distributed Management Task Force (DMTF), which enables the connection of a
BMC (Baseboard Management Controller) to enable out-of-band remote manageability. If
implemented, the NC-SI shall be assigned to the GBE0 interface. NC-SI architecture also enables
multiple endpoints to be connected to the same management controller.
In this configuration, the bus arbitration can also be implemented by hardware using a token ring
configuration. The NCSI_ARB_IN pin of one controller must be connected to the NCSI_ARB_OUT
of another controller to form a ring configuration. A maximum of four network controllers can beconnected in this manner and all controllers sharing the same NC-SI interface pins must support
this feature in order to use hardware-based arbitration. NCSI_ARB_IN and NCSI_ARB_OUT are to beleft unconnected on the Carrier if there is no Carrier network controller.
3.3.24.1 Signal Definitions
Table 3-34: NCSI Interface Signal Definitions
Pin

Type

SignalDescription

I/O

B89

Type 7

NCSI_RX_ER

NC-SI Receive error.

O COM
3.3V Suspend/ 3.3V

B91

Type 7
NCSI_CLK_IN

NC-SI Clock reference for receive,

I COM

transmit, and control interface.

3.3V Suspend/ 3.3V

B92

Type 7
NCSI_RXD1

NC-SI Receive Data (from NC to

O COM

BMC).

3.3V Suspend/ 3.3V

B93

Type 7
NCSI_RXD0

NC-SI Receive Data (from NC to

O COM

BMC).

3.3V Suspend/ 3.3V

B94

Type 7
NCSI_CRS_DV

NC-SI Carrier Sense/Receive Data

O COM

Valid to MC, indicating that t

3.3V Suspend/ 3.3V

B95

Type 7
NCSI_TXD1

NC-SI Transmit Data (from BMC to

I COM

NC).

3.3V Suspend/ 3.3V

B96

Type 7
NCSI_TXD0

NC-SI Transmit Data (from BMC to

I COM

NC).

3.3V Suspend/ 3.3V

B98

Type 7

NCSI_ARB_IN

NC-SI hardware arbitration input.

I COM

N/C if not used.

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Focus • Agility • CompetitivenessB99

Type 7

NCSI_ARB_OUT

NC-SI hardware arbitration output.

O COM

N/C if not used.

3.3V Suspend/ 3.3V

A84

Type 7

NCSI_TX_EN

NC-SI Transmit enable.

I COM
3.3V Suspend/ 3.3V

3.3.24.2 NCSI Interface Reference Schematics : BY PLATFORM LAYOUT GUIDE
Figure 3-31 NCSI Interface Reference Schematic

3.3.24.3 NCSI Interface Layout Recommendations : BY PLATFORM LAYOUT GUIDETable 3-35: NCSI Trace Routing Guidelines
Parameter

Trace Routing

Carrier Board Max data and control signal length

8.5 inches

Nominal Trace Space within LPC Signal Group

3H

Single-ended Impedance

50 Ω +/-15%(Impedence may vary whendifferent platform used)

Trace width / Spacing between signals (intersignal)

PCB stack-up dependent

Reference plane

GroundVia Usage

Try to minimize number of vias

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Focus • Agility • Competitiveness4.

Power and Reset

4.1 ATX Power Sequence for +12 VDC and +5 VDC , +3.3 VDC
The +12 VDC and +5 VDC output levels must be equal to or greater than the +3.3 VDC output at all times
during power-up and normal operation. The time between the +12 VDC or +5 VDC output reaching its
minimum in-regulation level and +3.3 VDC reaching its minimum in-regulation level must be ≤ 20 ms.
(Refer : ATX12V Power Supply Design Guide_ Version 2.2)
Figure 4-1 ATX Power Supply Timing

Table 4-1: ATX Power Signals Timing
Signal Type

TimingPower-on TimeT1 < 500 ms

Rise time

0.1 ms ≤ T2 ≤ 20 ms

PWR_OK delay

100 ms < T3 < 500 ms

PWR_OK rise timeT4 ≤ 10 ms

AC loss to PWR_OK hold-up timeT5 ≥ 16 ms

Power-down warning

T6 ≥ 1 ms

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Focus • Agility • Competitiveness4.2 COM Express ATX vs AT Supplies
ATX power supplies are in common use in contemporary PCs. ATX supplies have two sets of power rails: a
set for normal operation (12V, 5V, 3.3V and -12V) and a separate 5V Suspend rail. The 5V Suspend rail ispresent whenever the ATX supply has AC input power. The other rails are on only when a control signal
from the PC hardware known as PS_ON# is held low by the motherboard, allowing software control ofthe power supply. The PC motherboard may implement several mechanisms for controlling the AC
power, including a push button switch that switches a low voltage logic signal rather than the AC main
power. Other options may be implemented, including the capability to turn on the main power on
events such as a keyboard press, mouse activity, etc.
AT power supplies do not have a Suspend rail and do not allow software control of the power supply.
An AT supply is on when the supply is connected to the AC main and the power switch that is in series
with the AC main input is on. AT supplies are extinct in the commercial PC market, but the term lives
on as a reference to a power supply that does not allow software control.
An ATX supply may be converted to AT style operation by simply holding the ATX PS_ON# input low all
the time.

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Focus • Agility • Competitiveness4.3 COM Express ATX and AT Power state (Refer PICMG Carrier DG Rev 2.0)
Table 4-2: COM Express Power stateState Description

Comment

G3

System power consumption is near zero – the only

Mechanical Off

power consumption is that of the RTC circuits, which
are powered by a backup battery.
S5

Soft Off

System is off except for a small subset that is
powered by the 5V Suspend rail.

S4

Suspend to

Disk

System is off except for a small subset that is
powered by the 5V Suspend rail. (that is powered
off).

S3

Suspend to RAM

System is off except for system subset that includes
the RAM.

Suspend power is provided by the 5V

Suspend rail.
S0

On

System is on.

Table 4-3: COM Express Signals SUS_S5#, SUS_S4# and SUS_S3# Power States
State SUS_S5#

SUS_S4#

SUS_S3#

G3

NA

NA

NA

S5

Low

Low

Low

S4

High

Low

Low

S3

High

High

Low

S0

High

High

High

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Focus • Agility • Competitiveness4.4 COM Express ATX and AT Power Sequence
A sequence diagram for an ATX style boot from a soft-off state (S5), initiated by a power button press, isshown in Figure 64 below. A sequence diagram for an AT style boot from the mechanical off state (G3)is shown in Figure 65 below.
In both cases, the VCC_12V, VCC_5V and VCC_3V3 power lines should rise together in a monotonic ramp
with a positive slope only, and their rise time should be limited. Please refer to the ATX specification for
more details.
(Refer PICMG Carrier DG Rev 2.0)
Figure 4-2 ATX Sequence

Figure 4-3 AT Sequence

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Focus • Agility • CompetitivenessTable 4-4: ATX and AT Power Up Timing Values
Parameter Min
TPB

TPSR

Max

Value

Value

10ms

500ms

0.1ms

20ms

Description

Comments

Push Button Power Switch – time to bring Module

Applies only to ATX

chipset out of Suspend mode

Style Power Up

Power Supply Rise Time

4.5 Reference Schematics
Figure 4-4 COM Express Main Power

Note : Independent Power Input Design of COM Express Module Power Consumption Measurement Use.

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Focus • Agility • Competitiveness5. Appendix
5.1 List of Figures
Figure 2-1 Module Form Factors ……………………………………………………………………………………………….page23
Figure 2-1-1 AAEON COM Express Module ……………………………………………………………………………….page24
Figure 2-2 Type 6 ROW ABCD Connector ………………………………………………………………………………….page25
Figure 2-3 Type 10 ROW AB Connector …………………………………………………………………………………….page26
Figure 2-4 Type 7 ROW ABCD Connector …………….…………………………………………………………………..page27
Figure 2-5 Plug and Receptacle ………………………………………………………………………………………………..page28
Figure 2-6 Heat spreader with Threaded Standoffs …………………………………………………………………..page28
Figure 3-1 PCIE[x1] Reference Schematic …………………………………………………………………………………page34
Figure 3-2 Mini-Card for mSATA / PCIE Switching Reference Schematic ……………………………………page35
Figure 3-3 Mini-Card for mSATA / PCIE Reference Schematic ……………………………………………………page35
Figure 3-4 PEG Reference Schematic ……………………………………………………………………………………….page39
Figure 3-5 RJ45 Reference Schematic …………………………………………………………….…………………………page41
Figure 3-6 USB2.0+USB3.0 Reference Schematic ……………………………………………………………………..page45
Figure 3-7 USB Power Over-current Reference Schematic ………………………………………………………..page45
Figure 3-8 SATA (with Repeater IC) Reference Schematic ………………………………………………………….page48
Figure 3-9 LVDS Reference Schematic ……………………………………..………………………………………………..page50
Figure 3-10 eDP Reference Schematic ……………………………………………………………………………………….page53
Figure 3-11 VGA Connector Reference Schematic ……………………………………………………………………..page55
Figure 3-12 DP Connector Reference Schematic ………………………………………………………………………..page57
Figure 3-13 Audio Jack Reference Schematic ……………………………………………………………………………..page60
Figure 3-14 LPC Connector Reference Schematic ……………………………………………………………………….page61
Figure 3-15 SPI Connector Reference Schematic ………………………………………………………………………..page64
Figure 3-16 CANBUS Connector Reference Schematic ………………………………………………………………..page67
Figure 3-17 RTC Connector Reference Schematic ……………………………………………………………………….page68
Figure 3-18 DIO Connector Reference Schematic ……………………………………………………………………….page69
Figure 3-19 SDIO Connector Reference Schematic ……………………………………………………………………..page70
Figure 3-20 PWRBTN# Reference Schematic ……………………………………………………………………………….page73
Figure 3-21 CB_RESET# Reference Schematic ……………………………………………………………………………..page73
Figure 3-22 PWR_OK Reference Schematic …………………………………………………………………………………page73
Figure 3-23 FAN Connector Reference Schematics ………………………………………………………………………..page74
Figure 3-24 LID# and SLEEP# Reference Schematic ……………………………………………………………………..page76
Figure 3-25 WDT Reference Schematic ……………………………………………………………………………………….page76
Figure 3-26 SPKR Reference Schematic ……………………………………………………………………………………….page76
Figure 3-27 10G Interface Reference Schematic-1………..…………….……………………………………………….page85
Figure 3-28 10G Interface Reference Schematic-2………..…………….……………………………………………….page85
Figure 3-29 10G Interface Reference Schematic-3………..…………….……………………………………………….page85
Figure 3-30 10G Interface Reference Schematic-4………..…………….……………………………………………….page86

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Focus • Agility • CompetitivenessFigure 3-31 NCSI Interface Reference Schematic………..…………….…………….………………………………….page88
Figure 4-1 ATX Power Supply Timing …………………………………………………………………………………………..page89
Figure 4-2 ATX Sequence …………………………………………………………………………………………………………….page92
Figure 4-3 AT Sequence ……………………………………………………………………………………………………………….page92
Figure 4-4 COM Express Main Power …………………………………………………………………………………………..page93
5.2 List of Tables
Table 1-1: Abbreviations and Definitions Used …………………………………………………………………………..page8-10
Table 1-2: Signal Table Terminology Descriptions ………………………………………….…………………………….page10
Table 1-3: COM Express Type 6 ,7 & Type 10 Pinout ………………………………………………………………page11-22
Table 2-1: AAEON Connector Type ……………………………………………………………………………………………..page28
Table 3-1: PCB Stack Example ……………………………………………………………………………………………………..page29
Table 3-2: PCIE Signal Definitions …………………………………………………………………………………………..page30-34
Table 3-3: PCIE / PEG Trace Routing Guidelines …………………………………………………………………………..page36
Table 3-4: PEG Signal Definitions ……………………………………………………………………………………………page37-38
Table 3-5: LAN Signal Definitions ………………………………………………………………………………………………..page40
Table 3-6: LAN Trace Routing Guidelines …………………………………………………………………………………….page42
Table 3-7: USB2.0 Signal Definitions …………………………………………………………………………………………..page43
Table 3-8: USB3.0 Signal Definitions …………………………………………………………………………………………..page44
Table 3-9: USB2.0 and USB3.0 Trace Routing Guidelines …………………………………………………………….page46
Table 3-10 SATA Signal Definitions ………………………………………………………………………………………………page47
Table 3-11: SATA Trace Routing Guidelines ………………………………………………………………………………..page48
Table 3-12: LVDS Signal Definitions ……………………………………………………………………………………………page49
Table 3-13: LVDS Trace Routing Guidelines ………………………………………………………………………………..page51
Table 3-14: Embedded DisplayPort Signal Definitions ………………………………………………………………..page52
Table 3-15: VGA Signal Definitions ……………………………………………………………………………………………..page54
Table 3-16: Digital Display Signal Definitions ………………………………………………………………………………page56
Table 3-17: DisplayPort Trace Routing Guidelines ……………………………………………………………………….page58
Table 3-18: Digital Audio Signal Definitions …………………………………………………………………………………page59
Table 3-19: LPC Signal Definitions ……………………………………………………………………………………………….page61
Table 3-20: LPC Trace Routing Guidelines ……………………………………………………………………………………page62
Table 3-21: SPI Signal Definitions ………………………………………………………………………………………………..page63
Table 3-22: I2C Signal Definitions ………………………………………………………………………………………………..page65
Table 3-23: SMBus Signal Definitions …………………………………………………………………………………………..page66
Table 3-24: CANBUS Signal Definitions ………………………………………………………………………………………..page67
Table 3-25: RTC Battery Signal Definitions …………………………………………………………………………………..page68
Table 3-26: DIO Signal Definitions ……………………………………………………………………………………………….page69
Table 3-27: SDIO Signal Definitions ……………………………………………………………………………………………..page70
Table 3-28: Serial Interface Signal Definitions ……………………………………………………………………………..page71

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Focus • Agility • CompetitivenessTable 3-29: Power Management Signal Definitions ………………………………………………………………………..page72
Table 3-30: FAN Connector Signal Definitions ……………………………………………..……………….……………..page74
Table 3-31: Miscellaneous Signals Definitions ……………………………………………………………………………..page75
Table 3-32: 10G Interface Signal Definitions… ………………………………………………………………………..page78-84
Table 3-33: 10G Interface Layout Recommendations……………………………………………..……………….…..page86
Table 3-34: NCSI Interface Signal Definitions …………………………………………………………………………..page87-88
Table 3-35: NCSI Trace Routing Guidelines………………………...………………..……………...……………………..page88
Table 4-1: ATX Power Signals Timing ……………………………………………………………………………………………page89
Table 4-2: COM Express Power state .………………………………………………………….………………………………page91
Table 4-3: COM Express Signals SUS_S5#, SUS_S4# and SUS_S3# Power States …………………………..page91
Table 4-4: ATX and AT Power Up Timing Values ………………………………………………………………………….page93

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