National Synchrotron Radiation Research Center

Introductions to Taiwan Photon
Source and Control System
Vacuum GroupJyun Yan Chuang
荘 俊彦 （そう とし ひこ）
30 Nov. 2016
KEK Tsukuba Japan

Outline• Introductions to TLS and TPS• TPS control system• Front end interlock control system• Conclusions

TLS
Utility-III andGuest House II

Activity center
Administrationbuilding
TPS

Guest
House IThe Status of TPS and TLS

Taiwan Light Source (TLS) is the 2nd third
generation light source (1993)
VUV

SX

HX

1E16U9(1)Flux (Phot/s/0.1%bw)

1E15(3)EPU5.6(1)SP8-IVXU3.2(1)
U5(1)
(3)
(3)
(5)
(5)
(7)
SW6

1E14

1E13(3)(5)(7)
SP8-BM

IASW6W20BM
1E12SWLS
1E110.1

110100

1000

10000

Photon Energy (eV)

Ø Circumference – 120 m
Ø Critical Energy – 2.14 keV
Ø Natural Emittance – 25 n mrad
HXØ Average Pressure (200 mA) – 0.68 nTorr
VUVØ Accumulated Dose > 8000 Ah
SXØ Life Time – 10 h
VUVSXØ 1993 – Operation 1.3 GeV
Ø 1996 – Ramping to 1.5 GeV

HXHXHX

Ø 2000 – 1.5 GeV Full Energy Injection (200 mA)
Ø 2004 – Operation with Superconducting RFCavity

Ø 2005 – Top-up Injection at 300 mA

HXHX

ID in operation
W20 (1995) 4 ~ 15 keV
U10(1995) 3 ~ 500 eVU5(1997) 60 ~ 1500 eVU9(1999) 4 ~ 100 eV
EPU5.6 (1999) 60 ~ 1400 eV
SWLS (2002) 4 ~ 30 keV
SW6(2004) 6.5 ~ 19 keV
IASW6 (2006) 6.5 ~ 19 keV

New ID in planning
2nd IASW6 (2009)
3rd IASW6 (2010)

Major Parameters of Taiwan Photon Source

Milestones of Taiwan Photon Source

LINACBoosterLayout of 1/6 Super periods (L = 86.4 m) for the Electron StorageRing Vacuum System
Arc Unit Cells (4×)
- 1× B1 for ID beam lines- 1× B2 for BM beam lines
12m Long Straight (1×)- Injection system- SRF cavities- Double Insertion Devices

7m Short Straight (3×)- SRF cavities- Insertion Devices

A Standard Ultra-High Vacuum Unit Cellfor the Electron Storage Ring
SGV

•BPM (5)•Crotch Absorber (2)•Photon Stopper (2)•Front End Valve (2)•Pumping Gate Valve (2)S3B1•Bellows (2)•Sector Gate Valve (2)•Extractor IG (3)•Triode IP 200 l/s (4)•NEG 350 l/s (8) + 200 l/s (2)•Magnetic suspension TMP 400 l/s (2)~14 m

S4B2G.
Y. Hsiung - 12SGV

Typical Design of Bending chamber (~ 4m) assembly forElectron Storage Ring
• Simple structure of vacuum beam ducts
along the beam channel, no flange, few
absorbers, few bellows, for lowering
the impedance.
• Completely oil-free and precise CNC
machining for the B-chambers and TIG
welding in the clean room to obtain aclean surface with lowest surface
outgassing rate and the consequent
lowest pressure.
• Strong back supports for the BPMfixed on the girders for positioning theBPM precisely and cooling channels
drilled through the B-chambers
provides an uniform temperature
control for assuring the BPM shift <0.1 micron against the thermal stress.
1. Button : φ6.9 mm
2. Gap : 0.3 mm
3. Distance : 17.5 mm
4. Angle : 6.7°

Outline• Introductions to TLS and TPS• TPS control system• Front end interlock control system• Conclusions

Software VersionsOutline• Introductions to TLS and TPS• TPS control system• Front end interlock control system• Conclusions

Introductions to Front end

The main functions of a front end are:
• To protect radiation safety for user.

• To allow synchrotron light generated in the storage ring to pass through to abeamline.
• To monitor the position of the synchrotron light.
• To protect the vacuum of storage ring if there is a leak in the beamline.
• To remove as much of the heat as possible from the synchrotron light.
• To allow safe access into the optics hutch when required.

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Scheme of FE Signals Transmission

29

Hardware of TPS FE Interlock System
EMG loop

NI Compact RIO
9074à9030

NI 9476
32-channel
500 µs digital output
6 to 36 V output range, sourcing
250 mA/ch maximum current
drive on all channels
Industry-standard 37-pin D-Sub
connector
Hot-swappable operation-40 to 70 °C operating range

NI 9425
32-channel
7 µs sinking digital inputs
Compatible with 12 and 24 Vlevels
Industry-standard 37-pin D-Sub
connector
Hot-swappable operation
Extreme industrial-40 to 70 °C operating range

30

System Architecture of NI Compact RIO

Program Architecture of NI Compact RIO

RT Processor
1. Real-time OS
2. Application software
3. Networking andperipheral I/O drivers
4. DMA, interrupt, and bus
control drivers
FPGA
1. Application IP
2. Control IP
3. DSP IP
4. Specialized I/O drivers
and interface
5. DMA controller
Reference from ni.com

31

Reliability increase and fail safe
• Keep CPU usage
below 70%.
• Utilized Watch dog

1. RT Safe
2. Emergency Safe
3. Watchdog safe
4. Control input valid

32

Network communication

ADAM
Modbussystem

EPICS server

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Outline• Introductions to TLS and TPS• TPS control system• Front end interlock control system• Conclusions

Conclusions• TPS have operated for user by 3 GeV and 300 mA top-up mode.
• TPS BL construcHon is in progress, 5BLs are operated for user.
• RadiaHon safety is upgrading for human safety.
• YOKOSO TPS Taiwan.

Thank You For Your Attention