Micro-Research Finland Oy
Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finland

Document: EVR-MRM-003.doc
Date: 14 January 2011
Issue: 1
Page: 1 of 64
Author: Jukka Pietarinen

Event ReceivercPCI-EVR-220, cPCI-EVR-230, PMC-EVR-230,
VME-EVR-230, VME-EVR-230RF, cPCI-EVRTG-300,
cRIO-EVR-300 and cPCI-EVR-300
Technical ReferenceFirmware Version 0005
Contents
Introduction ................................................................................................................................5
Functional Description ............................................................................................................5
Event Decoding...................................................................................................................5Heartbeat Monitor ...............................................................................................................6
Event FIFO and Timestamp Events......................................................................................6
Event Log............................................................................................................................7
Distributed Bus and Data Transmission ...............................................................................7
Pulse Generators..................................................................................................................7
Prescalers ............................................................................................................................8
Programmable Front Panel Connections ..............................................................................8
Front Panel CML Outputs (VME-EVR-230RF only) ...........................................................9cPCI-EVRTG-300 GTX Front Panel Outputs ....................................................................11
Configurable Size Data Buffer...........................................................................................14
Interrupt Generation ..........................................................................................................14
External Event Input..........................................................................................................15
Programmable Reference Clock ............................................................................................15
Fractional Synthesiser........................................................................................................15
Connections ..............................................................................................................................15
cPCI-EVR-2x0 Front Panel Connections ...............................................................................15
VME-EVR-230 and VME-EVR-230RF Front Panel Connections..........................................16
VME P2 User I/O Pin Configuration .....................................................................................17
PMC-EVR-230 Front Panel Connections...............................................................................18
PMC-EVR-230 Pn4 User I/O Pin Configuration....................................................................19cRIO-EVR-300 Front Panel Connections...............................................................................20
cPCI-EVRTG-300 Front Panel Connections..............................................................................20
cPCI-EVR-300 Front Panel Connections...................................................................................21
VME-EVR-230 and VME-EVR-230RF Network Interface........................................................22
Assigning an IP Address to the Module .................................................................................22

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Document: EVR-MRM-003.doc
Date: 14 January 2011
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Author: Jukka Pietarinen

Using Telnet to Configure Module ........................................................................................22
Boot Configuration (command b) ......................................................................................22
Memory dump (command d) .............................................................................................23
Memory modify (commands d and m) ...............................................................................23
Tuning Delay Line (command t) ........................................................................................24
Upgrading IP2022 Microprocessor Software (command u) ................................................24
Linux.................................................................................................................................24
Windows ...........................................................................................................................24
Upgrading FPGA Configuration File .....................................................................................25
Linux.................................................................................................................................25
Windows ...........................................................................................................................25
Linux.................................................................................................................................25
Windows ...........................................................................................................................25
UDP Remote Programming Protocol .....................................................................................26
Read Access (Type 0x01) ..................................................................................................26
Write Access (Type 0x02) .................................................................................................27
cRIO-EVR-300 .........................................................................................................................28
Connections ..........................................................................................................................28
Boot Monitor.........................................................................................................................28
Firmware Upgrade (on Linux) ...............................................................................................29
Programming Details ................................................................................................................29
VME CR/CSR Support..........................................................................................................29
Event Receiver Function 0,1 and 2 Registers .........................................................................30
Register Map .....................................................................................................................31
SFP Module EEPROM and Diagnostics ................................................................................39
Application Programming Interface (API) .................................................................................39
Function Reference ...............................................................................................................39
int EvrOpen(struct MrfErRegs **pEr, char *device_name);...............................................39
int EvrClose(int fd);...........................................................................................................39
int EvrEnable(volatile struct MrfErRegs *pEr, int state);....................................................39
int EvrGetEnable(volatile struct MrfErRegs *pEr); ............................................................39
void EvrDumpStatus(volatile struct MrfErRegs *pEr); ......................................................39
int EvrGetViolation(volatile struct MrfErRegs *pEr, int clear);..........................................39
void EvrDumpMapRam(volatile struct MrfErRegs *pEr, int ram);.....................................39
int EvrMapRamEnable(volatile struct MrfErRegs *pEr, int ram, int enable);......................39
int EvrSetForwardEvent(volatile struct MrfErRegs *pEr, int ram, int code, int enable);......39
int EvrEnableEventForwarding(volatile struct MrfErRegs *pEr, int state);.........................39
int EvrGetEventForwarding(volatile struct MrfErRegs *pEr);............................................39
int EvrSetLedEvent(volatile struct MrfErRegs *pEr, int ram, int code, int enable);.............39
int EvrSetFIFOEvent(volatile struct MrfErRegs *pEr, int ram, int code, int enable); ..........39
int EvrSetLatchEvent(volatile struct MrfErRegs *pEr, int ram, int code, int enable);..........39
int EvrSetLogStopEvent(volatile struct MrfErRegs *pEr, int ram, int code, int enable); .....39
int EvrClearFIFO(volatile struct MrfErRegs *pEr);............................................................39
int EvrGetFIFOEvent(volatile struct MrfErRegs *pEr, struct FIFOEvent *fe); ...................39
int EvrEnableLogStopEvent(volatile struct MrfErRegs *pEr, int enable);...........................39
int EvrGetLogStopEvent(volatile struct MrfErRegs *pEr);.................................................39
int EvrEnableLog(volatile struct MrfErRegs *pEr, int enable); ..........................................39
int EvrGetLogState(volatile struct MrfErRegs *pEr, int enable); ........................................39

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Author: Jukka Pietarinen

int EvrGetLogStart(volatile struct MrfErRegs *pEr); .........................................................39
int EvrGetLogEntries(volatile struct MrfErRegs *pEr);......................................................39
void EvrDumpFIFO(volatile struct MrfErRegs *pEr);........................................................39
int EvrClearLog(volatile struct MrfErRegs *pEr);..............................................................39
void EvrDumpLog(volatile struct MrfErRegs *pEr);..........................................................39
int EvrSetPulseMap(volatile struct MrfErRegs *pEr, int ram, int code, int trig, int set, int
clear);................................................................................................................................39
int EvrClearPulseMap(volatile struct MrfErRegs *pEr, int ram, int code, int trig, int set, int
clear);................................................................................................................................39
int EvrSetPulseParams(volatile struct MrfErRegs *pEr, int pulse, int presc, int delay, int
width);...............................................................................................................................39
void EvrDumpPulses(volatile struct MrfErRegs *pEr, int pulses);......................................39
int EvrSetPulseProperties(volatile struct MrfErRegs *pEr, int pulse, int polarity, int
map_reset_ena, int map_set_ena, int map_trigger_ena, int enable);....................................39
int EvrSetUnivOutMap(volatile struct MrfErRegs *pEr, int output, int map);.....................39
void EvrDumpUnivOutMap(volatile struct MrfErRegs *pEr, int outputs); .........................39
int EvrSetFPOutMap(volatile struct MrfErRegs *pEr, int output, int map); ........................39
void EvrDumpFPOutMap(volatile struct MrfErRegs *pEr, int outputs);.............................39
int EvrSetTBOutMap(volatile struct MrfErRegs *pEr, int output, int map); .......................39
void EvrDumpTBOutMap(volatile struct MrfErRegs *pEr, int outputs); ............................39
void EvrIrqAssignHandler(volatile struct MrfErRegs *pEr, int fd, void (*handler)(int));....39
int EvrIrqEnable(volatile struct MrfErRegs *pEr, int mask); ..............................................39
int EvrGetIrqFlags(volatile struct MrfErRegs *pEr);..........................................................39
int EvrClearIrqFlags(volatile struct MrfErRegs *pEr, int mask); ........................................39
void EvrIrqHandled(int fd); ...............................................................................................39
int EvrSetPulseIrqMap(volatile struct MrfErRegs *pEr, int map); ......................................39
int EvrUnivDlyEnable(volatile struct MrfErRegs *pEr, int dlymod, int enable);.................39
int EvrUnivDlySetDelay(volatile struct MrfErRegs *pEr, int dlymod, int dly0, int dly1);...39
int EvrSetFracDiv(volatile struct MrfErRegs *pEr, int fracdiv); .........................................39
int EvrGetFracDiv(volatile struct MrfErRegs *pEr); ..........................................................39
int EvrSetDBufMode(volatile struct MrfErRegs *pEr, int enable); .....................................39
int EvrGetDBufStatus(volatile struct MrfErRegs *pEr);.....................................................39
int EvrReceiveDBuf(volatile struct MrfErRegs *pEr, int enable); ......................................39
int EvrGetDBuf(volatile struct MrfErRegs *pEr, char *dbuf, int size); ...............................39
int EvrSetTimestampDivider(volatile struct MrfErRegs *pEr, int div);...............................39
int EvrSetTimestampDBus(volatile struct MrfErRegs *pEr, int enable); ............................39
int EvrGetTimestampCounter(volatile struct MrfErRegs *pEr); .........................................39
int EvrGetSecondsCounter(volatile struct MrfErRegs *pEr);..............................................39
int EvrGetTimestampLatch(volatile struct MrfErRegs *pEr);.............................................39
int EvrGetSecondsLatch(volatile struct MrfErRegs *pEr); .................................................39
int EvrSetPrescaler(volatile struct MrfErRegs *pEr, int presc, int div); ..............................39
int EvrSetExtEvent(volatile struct MrfErRegs *pEr, int ttlin, int code, int edge_enable, intlevel_enable); ....................................................................................................................39
int EvrSetBackEvent(volatile struct MrfErRegs *pEr, int ttlin, int code, int edge_enable, intlevel_enable); ....................................................................................................................39
int EvrSetExtEdgeSensitivity(volatile struct MrfErRegs *pEr, int ttlin, int edge);...............39
int EvrSetExtLevelSensitivity(volatile struct MrfErRegs *pEr, int ttlin, int level); .............39
int EvrSetTxDBufMode(volatile struct MrfErRegs *pEr, int enable);.................................39

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Author: Jukka Pietarinen

int EvrGetTxDBufStatus(volatile struct MrfErRegs *pEr);.................................................39
int EvrSendTxDBuf(volatile struct MrfErRegs *pEr, char *dbuf, int size);.........................39
int EvrGetFormFactor(volatile struct MrfErRegs *pEr);.....................................................39

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Introduction
Event Receivers decode timing events and signals from an optical event stream transmitted by an
Event Generator. Events and signals are received at predefined rate the event clock that is usuallydivided down from an accelerators main RF reference. The event receivers lock to the phase
event clock of the Event Generator and are thus phase locked to the RF reference. Event
Receivers convert event codes transmitted by an Event Generator to hardware outputs. They canalso generate software interrupts and store the event codes with globally distributed timestamps
into FIFO memory to be read by a CPU.

Functional Description
After recovering the event clock the Event Receiver demultiplexes the event stream to 8-bit
distributed bus data and 8-bit event codes. The distributed bus may be configured to share its
bandwidth with time deterministic data transmission.

Event Decoding
The Event Receiver provides two mapping RAMs of 256 × 128 bits. Only one of the RAMs canbe active at a time, however both RAMs may be modified at any time. The event code is applied
to the address lines of the active mapping RAM. The 128-bit data programmed into a specificmemory location pointed to by the event code determines what actions will be taken.
Event code
0x00
0x01
0x02
…
0xFF

Offset0x00000x00100x0020…
0x0FF0Internal functions
4 bytes/32 bits
4 bytes/32 bits
4 bytes/32 bits…
4 bytes/32 bits

Pulse Triggers
4 bytes/32 bits
4 bytes/32 bits
4 bytes/32 bits…
4 bytes/32 bits

‘Set’ Pulse
4 bytes/32 bits
4 bytes/32 bits
4 bytes/32 bits…
4 bytes/32 bits

‘Reset’ Pulse
4 bytes/32 bits
4 bytes/32 bits
4 bytes/32 bits…
4 bytes/32 bits

There are 32 bits reserved for internal functions which are by default mapped to the event codes
shown in table . The remaining 96 bits control internal pulse generators. For each pulse generator
there is one bit to trigger the pulse generator, one bit to set the pulse generator output and one bit
to clear the pulse generator output.
Map bit
127
126
125
124
123
122
102 to 121
101
100
99
98
97
96

Default event code
n/a
n/a
n/a
n/a
0x79
n/a
n/a
0x7a
0x7b
0x7d
0x7c
0x71
0x70

Function
Save event in FIFO
Latch timestamp
Led eventForward event from RX to TX
Stop event log
Log event(Reserved)
Hearbeat
Reset Prescalers
Timestamp reset event
Timestamp clock event
Seconds shift register ‘1’
Seconds shift register ‘0’Micro-Research Finland Oy
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74 to 95
73…
64
42 to 63
41…
32
10 to 319…
0Document: EVR-MRM-003.doc
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Trigger pulse generator 9…
Trigger pulse generator 0(Reserved)
Set pulse generator 9 output high…
Set pulse generator 0 output high(Reserved)
Reset pulse generator 9 output low…
Reset pulse generator 0 output low

Heartbeat Monitor
A heartbeat monitor is provided to receive heartbeat events. Event code $7A is by default set up
to reset the heartbeat counter. If no heartbeat event is received the counter times out (approx. 1.6s) and a heartbeat flag is set. The Event Receiver may be programmed to generate a heartbeat
interrupt.

Event FIFO and Timestamp EventsThe Event System provides a global timebase to attach timestamps to collected data andperformed actions. The time stamping system consists of a 32-bit timestamp event counter and a
32-bit seconds counter. The timestamp event counter either counts received timestamp counterclock events or runs freely with a clock derived from the event clock. The event counter is alsoable to run on a clock provided on a distributed bus bit.
The event counter clock source is determined by the prescaler control register. The timestamp
event counter is cleared at the next event counter rising clock edge after receiving a timestamp
event counter reset event. The seconds counter is updated serially by loading zeros and ones (seemapping register bits) into a shift register MSB first. The seconds register is updated from theshift register at the same time the timestamp event counter is reset.
The timestamp event counter and seconds counter contents may be latched into a timestamp latch.
Latching is determined by the active event map RAM and may be enabled for any event code.
An event FIFO memory is implemented to store selected event codes with attached timing
information. The 80-bit wide FIFO can hold up to 511 events. The recorded event is stored alongwith 32-bit seconds counter contents and 32-bit timestamp event counter contents at the time ofreception. The event FIFO as well as the timestamp counter and latch are accessible by software.

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dbus_ena
distributed
bus bit 4
TS event counter clk
event code $7C

load bit '0'
event code $70

1prescaler = 0032-bit Seconds Shift Registerload bit '1'
event code $71

1event clock

16-bit prescaler
reset

32-bit Seconds Register
TS event counter reset
event code $7D

load

sync.

32-bit Timestamp Event Counterreset

32-bit Seconds Latch
latch timestamp
MAP14

0

latch

32-bit Timestamp Latch
latch

event
code
Event FIFO

Event FIFO write
MAP1532-bit Seconds

32-bit Timestamp

event

32-bit Seconds

32-bit Timestamp

event

32-bit Seconds

32-bit Timestamp

event

Figure 1: Event FIFO and Timestamping

Event Log
Up to 512 events with timestamping information can be stored in the event log. The log is
implemented as a ring buffer and is accessible as a memory region. Logging events can be
stopped by an event or software.

Distributed Bus and Data Transmission
The distributed bus is able to carry eight simultaneous signals sampled with the event clock rateover the fibre optic transmission media. The distributed bus signals may be output on
programmable front panel outputs.
The distributed bus bandwidth may be shared by transmission of a configurable size data buffer
to up to 2 kbytes. When data transmission is enabled the distributed bus bandwidth is halved. The
remaining bandwidth is reserved for transmitting data with a speed up to 50 Mbytes/s (event
clock rate divide by two).

Pulse Generators
The structure of the pulse generation logic is shown in Figure 2. Three signals from the mapping
RAM control the output of the pulse: trigger, ‘set’ pulse and ‘reset’ pulse. A trigger causes thedelay counter to start counting, when the end-of-count is reached the output pulse changes to the‘set’ state and the width counter starts counting. At the end of the width count the output pulse iscleared. The mapping RAM signal ‘set’ and ‘reset’ cause the output to change state immediately
without any delay.

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Map RAM
trigger x
event clk
reset

trigger

Prescaler(optional)

Delay Counter
enable out

count enable

Map RAM'set' pulse x

POLx

set
set

trigger

Width Countercount enable

clear
ena clear

ouput
polarity

Pulse Output
to mapping logic

Master enable
SW enable
Map RAM'reset' pulse x

Figure 2: Pulse Output Structure

32 bit registers are reserved for both counters and the prescaler, however, the prescaler is notnecessarily implemented for all channels and may be hard coded to 1 in case the prescaler isomitted. Software may write 0xFFFFFFFF to these registers and read out the actual width or
hard-coded value of the register. For example if the width counter is limited to 16 bits a read will
return 0x0000FFFF after a write of 0xFFFFFFFF.

Prescalers
The Event Receiver provides a number of programmable prescalers. The frequencies areprogrammable and are derived from the event clock. A special event code reset prescalers $7B
causes the prescalers to be synchronously reset, so the frequency outputs will be in same phaseacross all event receivers.

Programmable Front Panel Connections
The front panel outputs are programmable: each pulse generator output, prescaler and distributed
bus bit can be mapped to any output. The mapping is shown in table below.
Table 1: Signal mapping IDs

Mapping ID
0 to n-1
n to 31
32
…
39
40
41
42
43 to 61
62
63

SignalPulse generator output (number n of pulse generators depends on HW andfirmware version)(Reserved)
Distributed bus bit 0 (DBUS0)…
Distributed bus bit 7 (DBUS7)
Prescaler 0
Prescaler 1
Prescaler 2(Reserved)
Force output high (logic 1)
Force output low (logic 0)

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Front Panel TTL Outputs (VME-EVR-230 and VME-EVR-230RF)
The VME-EVR-230 provides eight programmable TTL outputs in the front panel TTL0 to TTL7
whereas the number of TTL level outputs in the VME-EVR-230RF is limited to four (TTL0 to
TTL3). These outputs are capable of driving a TTL level signal into a 50 ohm ground terminatedcoaxial cable. The source for these signals are determined by mapping registers which allow
selecting different types of pulse outputs, prescalers and distributed bus signals.

Front Panel Universal I/O Slots
Universal I/O slots provide different types of output with exchangeable Universal I/O modules.
Each module provides two outputs e.g. two TTL output, two NIM output or two optical outputs.
The source for these outputs is selected with mapping registers.
Two front panel Universal I/O slots have extra I/O pins to allow controlling the delay of UNIVLVPECL-DLY modules. For the cPCI-EVR-300 the two slots that allow UNIV-LVPECL-DLY
modules are UNIV8/9 and UNIV10/11.
An optional side-by-side front panel module for the cPCI-EVR-220 and cPCI-EVR-230 offers
three additional Universal I/O slots with a maximum of six outputs. The cPCI-EVR-300 has six
Universal I/O slots.

Front Panel CML Outputs (VME-EVR-230RF only)
Front Panel CML Outputs provide low jitter differential signals with special outputs. The outputs
can work in different configurations: pulse mode, pattern mode and frequency mode.

CML Pulse Mode
The source for these outputs is selected in a similar way than the TTL outputs using mapping
registers, however, the output logic monitors the state of this signal and distinguishes between
state low (00), rising edge (01), high state (11) and falling edge (10). Based on the state a 20 bit
pattern is sent out with a bit rate of 20 times the event clock rate.

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0

Pulse Output
Mapping Multiplexer

2

1

Event Clock

17

16

15

14

19

18

17

16

15

19

18

17

16

15

14

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

00

4

3

2

1

0

01

4

3

2

1

0

10

4

3

2

1

0

11

6

5

4

18

7

Pattern Register for state 'rising edge (01)'
13

12

11

10

9

8

7

6

5

10

9

8

14

11

10

9

8

7

6

5

12

12

14

13

13

11

Pattern Register for state 'falling edge (10)'

11

10

9

8

7

6

5

16

12

19

18

17

13

15

Pattern Register for state 'high (11)'Shift Register Operating at 20 x Event Clock Rate

3

Pattern Register for state 'low (00)'19

CML differential
output LEMO-EPY

Figure 3: Block Diagram of Programmable CML Outputs

•
•
•
•

When the source for a CML output is low and was low one event clock cycle earlier(state low), the CML output repeats the 20 bit pattern stored in pattern_00 register.
When the source for a CML output is high and was low one event clock cycle earlier(state rising), the CML output sends out the 20 bit pattern stored in pattern_01 register.
When the source for a CML output is high and was high one event clock cycle earlier(state high), the CML output repeats the 20 bit pattern stored in pattern_11 register.
When the source for a CML output is low and was high one event clock cycle earlier(state falling), the CML output sends out the 20 bit pattern stored in pattern_10 register.

For an event clock of 125 MHz the duration of one single CML output bit is 400 ps. These
outputs allow for producing fine grained adjustable output pulses and clock frequencies.

CML Frequency ModeIn frequency mode one can generate clocks where the clock period can be defined in steps of
1/20th part of the event clock cycle i.e. 400 ps step with an event clock of 125 MHz. There aresome limitations, however:••

Clock high time and clock low time must be ≥ 20/20th event clock period steps
Clock high time and clock low time must be < 65536/20th event clock period steps

The clock output can be synchronized by one of the pulse generators, distributed bus signal etc.
When a rising edge of the mapped output signal is detected the frequency generator takes its

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output value from the trigger level bit and the counter value from the trigger position register.
Thus one can adjust the phase of the synchronized clock in 1/20th steps of the event clock period.
Usage example: Australian synchrotron booster clock. We have following:••••

Event clock of 499.654 MHz/4
Storage ring 360 RF buckets
Booster 217 RF buckets
Booster and storage ring coincidence clock on DBUS7

The CML outputs are running at a rate of 20 times the event clock or 499.654 MHz * 5, thus thebooster revolution period is 217 * 5 CML bit periods. In CML frequency mode we can now set
the output period (pulse high time + pulse low time) to 217 * 5 = 1085 bits. For approximately
50% duty cycle we set the pulse high time to 542 (0x21e) and the pulse low time to 543 (0x21f).
The actual register settings required are:Write 0x00000011 to CML Control register (CMLxENA)
Write 0x021e to CML High Period Count register (CMLxHP)
Write 0x021f to CML Low Period Count register (CMLxLP)
We also need to set the trigger from DBUS7 by setting up register FPOutMapx.
To change the generated clock phase in respect to the trigger we can select the trigger polarity by
bit CMLTL in the CML Control register and the trigger position also in the CML Control
register.

CML Pattern ModeIn pattern mode one can generate arbitrary bit patterns taking into account following:• The pattern length is a multiple of 20 bits, where each bit is 1/20th of the event clock
period• Maximum length of the arbitrary pattern is 20 × 2048 bits
• A pattern can be triggered from any pulse generator, distributed bus bit etc. Whentriggered the pattern generator starts sending 20 bit words from the pattern memory
sequentially starting from position 0. This goes on until the pattern length set by the
samples register has been reached.
• If the pattern generator is in recycle mode the pattern continues immediately fromposition 0 of the pattern memory.
• If the pattern generator is in single pattern mode, the pattern stops and the 20 bit wordfrom the last position of the pattern memory (2047) is sent out until the pattern generator
is triggered again.

cPCI-EVRTG-300 GTX Front Panel Outputs
All eight cPCI-EVRTG-300 front panel output are similar to the CML outputs on the VME-EVR230RF. The GTX Outputs provide low jitter differential signals with special outputs. The outputs
can work in different configurations: pulse mode, pattern mode and frequency mode. The
difference compared to the CML output of the VME-EVR-230RF is that instead of 20 bits per

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event clock cycle the GTX outputs have 40 bits per event clock cycle doubling the resolution to
200 ps/bit at an event clock of 125 MHz.
In addition to the higher bit rate each of the GTX outputs has a programmable delay line between
the FPGA and the actual output which allows a delay range of 1024 steps of ~9 ps. The delay
value is set with registers GTX0Dly to GTX7Dly.

GTX Pulse Mode
The source for these outputs is selected in a similar way than the TTL outputs using mapping
registers, however, the output logic monitors the state of this signal and distinguishes between
state low (00), rising edge (01), high state (11) and falling edge (10). Based on the state a 40 bit
pattern is sent out with a bit rate of 40 times the event clock rate.

0

Pulse Output
Mapping Multiplexer

2

1

Event Clock

37

36

35

34

39

38

37

36

35

39

38

37

36

35

34

39

38

37

36

35

34

33

32

7

6

5

4

3

2

1

0

00

4

3

2

1

0

01

5

4

3

2

1

0

10

5

4

3

2

1

0

11

6

5

4

38

7

Pattern Register for state 'rising edge (01)'
34

33

32

7

6

5

32

7

6

34

33

33

32

Pattern Register for state 'falling edge (10)'

7

6

36

32

39

38

37

33

35

Pattern Register for state 'high (11)'Shift Register Operating at 40 x Event Clock Rate

3

Pattern Register for state 'low (00)'39

GTX output: UNIV I/O,
LVPECL, optical SFP

Figure 4: Block Diagram of Programmable GTX Outputs

•
•
•
•

When the source for a GTX output is low and was low one event clock cycle earlier (statelow), the GTX output repeats the 40 bit pattern stored in pattern_00 register.
When the source for a GTX output is high and was low one event clock cycle earlier(state rising), the GTX output sends out the 40 bit pattern stored in pattern_01 register.
When the source for a GTX output is high and was high one event clock cycle earlier(state high), the GTX output repeats the 40 bit pattern stored in pattern_11 register.
When the source for a GTX output is low and was high one event clock cycle earlier(state falling), the GTX output sends out the 40 bit pattern stored in pattern_10 register.

For an event clock of 125 MHz the duration of one single GTX output bit is 200 ps. These
outputs allow for producing fine grained adjustable output pulses and clock frequencies.

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GTX Frequency ModeIn frequency mode one can generate clocks where the clock period can be defined in steps of
1/40th part of the event clock cycle i.e. 200 ps step with an event clock of 125 MHz. There aresome limitations, however:••

Clock high time and clock low time must be ≥ 40/40th event clock period steps
Clock high time and clock low time must be < 65536/40th event clock period steps

The clock output can be synchronized by one of the pulse generators, distributed bus signal etc.
When a rising edge of the mapped output signal is detected the frequency generator takes its
output value from the trigger level bit and the counter value from the trigger position register.
Thus one can adjust the phase of the synchronized clock in 1/40th steps of the event clock period.
To change the generated clock phase in respect to the trigger we can select the trigger polarity by
bit CMLTL in the CML Control register and the trigger position also in the CML Control
register.

GTX Pattern ModeIn pattern mode one can generate arbitrary bit patterns taking into account following:• The pattern length is a multiple of 40 bits, where each bit is 1/40th of the event clock
period• Maximum length of the arbitrary pattern is 40 × 2048 bits
• A pattern can be triggered from any pulse generator, distributed bus bit etc. Whentriggered the pattern generator starts sending 40 bit words from the pattern memory
sequentially starting from position 0. This goes on until the pattern length set by the
samples register has been reached.
• If the pattern generator is in recycle mode the pattern continues immediately fromposition 0 of the pattern memory.
• If the pattern generator is in single pattern mode, the pattern stops and the 40 bit wordfrom the last position of the pattern memory (2047) is sent out until the pattern generator
is triggered again.

GTX GUN-TX-203 Mode
The cPCI-EVRTG-300 has two SFP outputs CH1 (GTX6) and CH2 (GTX7) that can generate amodulated signal that can be received by the Electron Gun trigger receiver GUN-RC-203. The
GUN-TX-203 Mode has been designed to operate with a RF bucket clock of 499.654 MHz andevent clock of ¼ of the RF clock.
To enable the GUN-TX-203 Mode one has to set bits GTX2MD and CMLENA in the CML/GTX
Control register for the given GTX output. The pulse output delay can be changed in quarters of
the event clock period by the GTXPH1:0 bits. For finer delay tuning the GTX delay lines may be
adjusted (registers GTX6Dly for CH1 and GTX7Dly for CH2).
The two SFP outputs share an external inhibit signal that only allows triggers when the external
inhibit signal is in a given state. To use the external inhibit function a UNIV-TTLIN-IL module
has to be mounted in Universal I/O slot UNIV0/1. To allow output pulses the inhibit signal at

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UNIV0 has to be pulled low. In case of an open circuit output pulses are inhibited. It is possible
to override the inhibit input with a control register bit.

Configurable Size Data Buffer
Some applications require deterministic data transmission. The configurable size data buffer
provides a configurable size buffer that may be transmitted over the event system link. The buffer
size is configured in the Event Generator to up to 2 kbytes. The Event Receiver is able to receive
buffers of any size from 4 bytes to 2 kbytes in four byte (long word) increments.
Data reception is enabled by changing the distributed bus mode for data transmission (mode = 1
in Data Buffer Control Register). This halves the distributed bus update rate. Before a data buffer
can be received the data buffer receiver has to be enabled (write enable = 1 in control register).
This clears the checksum error flag and sets the rx_enable flag. When a data buffer has been
received the rx_enable flag is cleared and rx_complete flag is set. If the received and computed
checksums do not match the checksum error flag is set.

distributed
bus interface

receptionengine andchecksumcomparison

2 kbytedual ported
data transmit
buffermemoryaccessenabledisablebufsize_words
rx_enable
rx_complete
checksum_error

Figure 5: Data Receive Buffer

The size of the data buffer transfer can be read from the control register. An interrupt may begenerated after reception of a data buffer.

Interrupt Generation
The Event Receiver has multiple interrupt sources which all have their own enable and flag bits.
The following events may be programmed to generate an interrupt:• Receiver link state change• Receiver violation: bit error or the loss of signal.
• Lost heartbeat: heartbeat monitor timeout.
• Write operation of an event to the event FIFO.
• Event FIFO is full.
• Data Buffer reception complete.

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In addition to the events listed above an interrupt can be generated from one of the pulse
generator outputs, distributed bus bits or prescalers. The pulse interrupt can be mapped in asimilar way as the front panel outputs.

External Event Input
An external hardware input is provided to be able to take an external pulse to generate an internal
event. This event will be handled as any other received event.

Programmable Reference Clock
The event receiver requires a reference clock to be able to synchronise on the incoming event
stream sent by the event generator. For flexibility a programmable reference clock is provided toallow the use of the equipment in various applications with varying frequency requirements.

Fractional Synthesiser
The clock reference for the event receiver is generated on-board the event receiver using afractional synthesiser. A Micrel (http://www.micrel.com) SY87739L Protocol Transparent
Fractional-N Synthesiser with a reference clock of 24 MHz is used. The following table lists
programming bit patterns for a few frequencies.
Event Rate
499.8 MHz/5= 99.96 MHz
50 MHz499.8 MHz/10= 49.98 MHz

Configuration Bit
Pattern
0x025B41ED

Reference Output
99.956 MHz

Precision(theoretical)-40 ppm

0x009743AD
0x025B43AD

50.0 MHz49.978 MHz

0-40 ppm

The event receiver reference clock is required to be in ±100 ppm range of the event generator
event clock.

Connections
cPCI-EVR-2x0 Front Panel Connections

LNK

UNIV0

UNIV1

UNIV2

UNIV3

TTL

RX

Figure 6: Event Receiver Front Panel

OFF

EVT

TX

IN0

IN1

PXI-EVR-220

Micro-Research

The front panel of the Event Receiver and its optional side-by-side module is shown in Figure 6
and Figure 7.

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Micro-Research Finland Oy

PXI-EVSBS-220

Micro-Research

Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finland

UNIV4

UNIV5

UNIV6

UNIV7

UNIV8

UNIV9

Figure 7: Optional Side-by-side Module Front Panel

The front panel of the Event Receiver includes the following connections and status leds:
Connector / Led
LNK

Style
Red/Green
Led

Level

EVT

Red/Green
Led

TX
RX
TTL IN0TTL IN1
UNIV0/1
UNIV2/3
UNIV4/5
UNIV6/7
UNIV8/9LC
LC
LEMO-EPY
LEMO-EPY
Universal slot
Universal slot
Universal slot
Universal slot
Universal slot

Description
Red: receiver violation detectedGreen: RX link OK, violation flagclearedGreen: link OK, flashes when eventcode received
Red: Flashes on led event
Transmit Optical Output (TX)
Receiver Optical Input (RX)External Event Input
External Event Input
Universal Output 0/1
Universal Output 2/3
Universal Output 4/6
Universal Output 6/7
Universal Output 8/9

opticalopticalTTL
TTL

VME-EVR-230 and VME-EVR-230RF Front Panel Connections

10/100

TX

RX

TTL

TTL

TTL

OUT6 OUT7

OUT5

TTL

TTL

UNIV0

UNIV1

UNIV2

UNIV3

Micro
Research

10baseTOUT4ENA OUT ERR ACT

VME-EVR-230

OUT2 OUT3

IN1
IN0

RX EVENT RX
FAIL LINK IN FAIL RUN
OFF

OUT0 OUT1

The front panel of the VME-EVR-230 Event Receiver is shown in Figure 6 and VME-EVR230RF in Figure 9: VME-EVR-230RF Event Receiver Front PanelFigure 9 respectively.

COM

10/100

TX

RX

TTL

TTL

TTL

CML

CML

OUT6+ OUT6-

OUT5+ OUT5-

OUT4+ OUT4-ENA OUT ERR ACT

VME-EVR-230RF 10baseT

OUT2 OUT3

IN1
IN0

RX EVENT RX
FAIL LINK IN FAIL RUN
OFF

OUT0 OUT1

Figure 8: VME-EVR-230 Event Receiver Front Panel

CML

UNIV0

UNIV1

UNIV2

UNIV3

COM

Figure 9: VME-EVR-230RF Event Receiver Front Panel

The front panel of the Event Receiver includes the following connections and status leds:
Connector / Led
FAIL

Style
Red LedLevel

Description
Module Failure/Interlock active

Micro-Research Finland Oy
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OFF

Blue Led

RX LINKENA
EVENT IN
EVENT OUT
RX FAIL
ERR
RUN
ACT

Green Led
Green Led
Yellow Led
Yellow Led
Red LedRed LedGreen Led
Yellow Led

10baseT with LEDs

RJ45
green Led
amber Led
RJ45
LC
LC
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
Universal slot
Universal slot
RJ45

10/100TX
RXTTL IN0TTL IN1
TTL OUT0
TTL OUT1TTL OUT2TTL OUT3
TTL OUT4TTL OUT5
TTL OUT6
TTL OUT7CML OUT4CML OUT5
CML OUT6
UNIV0/1
UNIV2/3
COM

10baseT

opticaloptical
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
CML
CML
CML

RS232

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Module not Configured/Powered
Down
Receiver Link Signal OK
Event Receiver Enabled
Incoming Event (RX)Active HW output
Receiver Violation
SY87739L reference not locked
Ubicom IP2022 software running
Ubicom IP2022 telnet connection
active10baseT Ethernet Connection
link establishedlink activity(reserved)
Transmit Optical Output (TX)
Receiver Optical Input (RX)External Event Input
External Event Input
Programmable TTL Output 0
Programmable TTL Output 1
Programmable TTL Output 2
Programmable TTL Output 3
Programmable TTL Output 41
Programmable TTL Output 5
Programmable TTL Output 6
Programmable TTL Output 7
Programmable CML Output 42
Programmable CML Output 5
Programmable CML Output 6
Universal Output 0/1
Universal Output 2/3(reserved)

VME P2 User I/O Pin Configuration
The following table lists the connections to the VME P2 User I/O Pins.
Pin
A1
A2
A3-A10
A11
A12
A13-A15
1
2

SignalTransition board ID0
Transition board ID1
GroundTransition board ID2
Transition board ID3
GroundTTL outputs TTL4-TTL7 available on VME-EVR-230 only
CML outputs available on VME-EVR-230RF only

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A16
A17-A26
A27-A31
A32
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32

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Transition board handle switch
Ground+5V
Power control for transition board(reserved)(reserved)(reserved)(reserved)(reserved)(reserved)(reserved)(reserved)(reserved)(reserved)(reserved)
Programmable transition board output 0
Programmable transition board output 1
Programmable transition board output 2
Programmable transition board output 3
Programmable transition board output 4
Programmable transition board output 5
Programmable transition board output 6
Programmable transition board output 7
Programmable transition board output 8
Programmable transition board output 9
Programmable transition board output 10
Programmable transition board output 11
Programmable transition board output 12
Programmable transition board output 13
Programmable transition board output 14
Programmable transition board output 15(reserved)(reserved)(reserved)(reserved)(reserved)

PMC-EVR-230 Front Panel Connections
The front panel of the PMC Event Receiver is shown in Figure 10.

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Micro-Research Finland Oy

OUT2

OUT3 EXT.IN

OUT FAILOUT1

EVT LINK

Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finland

Figure 10: PMC-EVR-230 Event Receiver Front Panel

The front panel of the Event Receiver includes the following connections and status leds:
Connector / Led
LINK
EVT
OUT
FAIL
TX (SFP) next to leds
RX (SFP) next to EXT.IN
OUT0
OUT1
OUT2
EXT IN

Style
Green Led
Yellow Led
Yellow Led
Red LedLC
LC
LEMO-EPL
LEMO-EPL
LEMO-EPL
LEMO-EPL

Level

Optical 850 nm
Optical 850 nm
TTL
TTL
TTL
TTL

Description
Receiver Link Signal OK
Incoming Event (RX)Active HW output
Receiver Violation
Event link Transmit
Event link Receiver
Programmable TTL Output 0
Programmable TTL Output 1
Programmable TTL Output 2
External Event Input

PMC-EVR-230 Pn4 User I/O Pin Configuration
The following table lists the connections to the PMC Pn4 User I/O Pins and to VME P2 pins
when the module is mounted on a host with “P4V2-64ac” mapping complying VITA-35 PMC-P4
to VME-P2-Rows-A,C.
PMC Pn4 pin
2
4
6, 8, …, 20
22
24
26, 28, 30
32
34, 36, …, 52
54, 56, …, 62
64
1
3
5
7
9
11
13
15
17

VME P2 Pin Signal
A1
Transition board ID0
A2
Transition board ID1
A3-A10Ground
A11
Transition board ID2
A12Transition board ID3
A13-A15 Ground
A16
Transition board handle switch
A17-A26 Ground
A27-A31 +5V
A32
Power control for transition board
C1(reserved)
C2(reserved)
C3(reserved)
C4(reserved)
C5(reserved)
C6(reserved)
C7(reserved)
C8(reserved)
C9(reserved)

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19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63

C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32

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Programmable transition board output 0
Programmable transition board output 1
Programmable transition board output 2
Programmable transition board output 3
Programmable transition board output 4
Programmable transition board output 5
Programmable transition board output 6
Programmable transition board output 7
Programmable transition board output 8
Programmable transition board output 9
Programmable transition board output 10
Programmable transition board output 11
Programmable transition board output 12
Programmable transition board output 13
Programmable transition board output 14
Programmable transition board output 15(reserved)(reserved)(reserved)(reserved)(reserved)

cRIO-EVR-300 Front Panel Connections

Figure 11: cRIO-EVR-300 Event Receiver Front Panel

Connector / Led
TX (SFP)
RX (SFP)
ETH
V+

Style
LC
LC
RJ45
Terminal

Level
Optical 850 nm
Optical 850 nm
10baseT/100baseTX+6 to +30 VDC

GND

Terminal

GroundcPCI-EVRTG-300 Front Panel Connections

Description
Event link Transmit
Event link Receiver
Ethernet port
Power supply positive
supplyPower supply groundMicro-Research Finland Oy
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Figure 12: cPCI-EVRTG-300 Event Receiver Front Panel

Connector / Led
10baseT with LEDs

10/100/GbE
LNK
ACT
COM
TX
RX
UNIV0/1
UNIV2/3
LVPECL 0
LVPECL 1
A
B
C
D
CH 1
CH 2
Link TX (SFP)
Link RX (SFP)

Style
RJ45
green Led
amber Led
RJ45
led
led
RJ45
Led
Led
Universal slot
Universal slot
EPG.00.302
EPG.00.302
RGB LedRGB LedRGB LedRGB Led
LC
LC
LC
LC

Level
10baseT

RS-232

3.3V diff. LVPECL
3.3V diff. LVPECL

Optical 850 nm
Optical 850 nm
Optical 850 nm
Optical 850 nm

Description
10baseT Ethernet Connection
link establishedlink activity(reserved)
10/100/GbE link led
10/100/GbE active led(reserved)(reserved)(reserved)
Universal Output 0/1
Universal Output 2/3
LVPECL Output
LVPECL Output(reserved)(reserved)(reserved)(reserved)
GunTX Output
GunTX Output
Event link Transmit
Event link ReceivercPCI-EVR-300 Front Panel Connections

Figure 13: cPCI-EVR-300 Event Receiver Front Panel

Connector / Led
UNIV0/1
UNIV2/3
UNIV4/5
UNIV6/7
UNIV8/9
UNIV10/11
USB
10/100
IN0
IN1
Link TX (SFP)
Link RX (SFP)

Style
Universal slot
Universal slot
Universal slot
Universal slot
Universal slot
Universal slot
USB
RJ45
Lemo
Lemo
LC
LC

Level

TTL
TTL
Optical 850 nm
Optical 850 nm

Description
Universal Output 0/1
Universal Output 2/3
Universal Output 4/5
Universal Output 6/7
Universal Output 8/9
Universal Output 10/11(USB Serial Port, reserved)(10/100 Ethernet, reserved)
TTL Input IN0
TTL Input IN1
Event link Transmit
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VME-EVR-230 and VME-EVR-230RF Network Interface
A 10baseT network interface is provided to upgrade the FPGA firmware and set up boot options.
It is also possible to control the module over the network interface.

Assigning an IP Address to the Module
By default the modules uses DHCP (dynamic host configuration protocol) to acquire an IP
address. In case a lease cannot be acquired the IP address set randomly in the 169.254.x.x subnet.
The board can be programmed to use a static address instead if DHCP is not available.
The module can be located looking at the lease log of the DHCP server or using a Windows tool
called Locator.exe.

Using Telnet to Configure Module
To connect to the configuration utility of the module issue the following command:telnet 192.168.1.32 23

The latter parameter is the telnet port number and is required in Linux to prevent negotiation oftelnet parameters which the telnet server of the module is not capable of.
The telnet server responds to the following commands:
Commandbdh/?
m <address> [<data>]
r
s
t
+
u
q

Description
Show/change boot parameters, IP address etc.
Dump 16 bytes of memory
Show Help
Read/Write FPGA CR/CSR, Function 0
Reset Board
Save boot configuration & dynamic configuration values into nonvolatile memory
Tune delay line for event clock recovery
Manually increase delay line delay *)Manually decrease delay line delay *)Update IP2022 software
Quit Telnet*) This option has been added with IP2022 software version 060309 for VME-EVR-230RF (displayed in output fromhelp command)

Boot Configuration (command b)
Command b displays the current boot configuration parameters of the module. The parameter
may be changed by giving a new parameter value. The following parameters are displayed:
Parameter
Use DHCP
IP address

Description
0 = use static IP address, 1 = use DHCP to acquire address, net masketc.
IP address of module

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Subnet mask
Default GW
FPGA mode

FTP server
Username
Password
FTP Filename
Flash Filenameµs divider
Fractional divider
configuration word

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Subnet mask of module
Default gateway
FPGA configuration mode
0 – FPGA is not configured after power up
1 – FPGA configured from internal Flash memory
2 – FPGA is configured from FTP server
FTP server IP address where configuration bit file resides
FTP server username
FTP server password
FTP server configuration file name
Configuration file name on internal flash
Integer divider to get from event clock to 1MHz, e.g. 125 for124.9135 MHz
Micrel SY87739UMI fractional divider configuration word to set
refenrence for event clock

Note that after changing parameters the parameters have to be saved to internal flash by issuing
the Save boot configuration (s) command. The changes are applied only after resetting themodule using the reset command or hardware reset/power sequencing.

Memory dump (command d)This command dumps 16 bytes of memory starting at the given address, if the address is omitted
the previous address value is increased by 16 bytes.
The most significant byte of the address determines the function of the access:Address
0x78000000
0x7a000000

Function
CR/CSR space access
EVR registers accessTo dump the start of the EVR register map issue the ‘d’ command from the telnet prompt:
VME-EVR-230RF -> d 7a000000 ↵Addr 7a000000: 1005 0001 0000 0000 0000 0000 0000 0000
VME-EVR-230RF -> d ↵Addr 7a000010: 0000 0000 0000 0000 0000 0000 0000 0000
VME-EVR-230RF ->Memory modify (commands d and m)
The access size is always a short word i.e. two bytes.
To check the status register from the telnet prompt:
VME-EVR-230RF -> m 7a000000 ↵Addr 7a000000 data 1005
VME-EVR-230RF ->To clear the violation flag issue:
VME-EVR-230RF -> m 7a000000 1005 ↵Micro-Research Finland Oy
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Addr 7a000000 data 0000
VME-EVR-230RF ->Tuning Delay Line (command t)
The VME Event Receiver VME-EVR-230RF has to be configured for proper event clock rate andthe on-board delay line has to be tuned for the operating conditions. Before setting up the board
make sure you have an Event Generator with the correct event clock connected to the Event
Receiver. Also, let the EVR reach operating temperature (power on for 10 minutes in crate). See
previous section for setting up the event clock rate.
To start tuning issue command ‘t’ from the telnet prompt:
VME-EVR-230RF -> t ↵Starting tuning...
Adjusted sampling phase to 75
Initial DCM phase -85
Fine tuned sampling phase to 78
Final DCM phase -73.
VME-EVR-230RF ->After tuning the tuned values have to be stored in non-volatile memory:
VME-EVR-230RF -> s ↵Confirm save (yes/no) ? yes ↵Configuration saved.
VME-EVR-230RF ->Upgrading IP2022 Microprocessor Software (command u)
To upgrade the Ubicom IP2022 microprocessor software download the upgrade image containing
the upgrade to the module using TFTP:LinuxIn Linux use e.g. interactive tftp:$ tftp 192.168.1.32
tftp> bintftp> put upgrade.bin /fw
tftp> quit

Windows
In Windows command prompt issue the following command:
C:\> tftp –i 192.168.1.32 PUT upgrade.bin /fw

When the upgrade image has been downloaded and verified, enter at the telnet prompt following:
VME-EVR-230 -> u ↵Really update firmware (yes/no) ? yes ↵Micro-Research Finland Oy
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Self programming triggered.

The Event Receiver starts programming the new software and restarts.

Upgrading FPGA Configuration File
When the FPGA configuration file resides in internal flash memory a new file system image has
to be downloaded to the module. This is done using TFTP protocol:

Linux
In Linux use e.g. interactive tftp:$ tftp 192.168.1.32
tftp> bintftp> put filesystem.bin /tftp> quit

Windows
In Windows command prompt issue the following command:
C:\> tftp –i 192.168.1.32 PUT filesystem.bin /Now the FPGA configuration file has been upgraded and the new configuration is loaded after
next reset/power sequencing.
Note! Due to the UDP protocol it is recommended to verify (read back and compare) the
filesystem image before restarting the module. This is done following:

Linux
In Linux use e.g. interactive tftp:$ tftp 192.168.1.32
tftp> bintftp> get / verify.bin
tftp> quit
$ diff filesystem.bin verify.bin$

If files differ you should get following message:
Binary files filesystem.bin and verify.bin differ

Windows
In Windows command prompt issue the following command:
C:\> tftp –i 192.168.1.32 GET / verify.bin
C:\> fc /b filesystem.bin verify.bin
Comparing files filesystem.bin and verify.bin
FC: no differences encountered

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UDP Remote Programming Protocol
The VME-EVR can be remotely programmed using the 10baseT Ethernet interface with aprotocol over UDP (User Datagram Protocol) which runs on top of IP (Internet Protocol). The
default port for remote programming is UDP port 2000. The UDP commands are built upon thefollowing structure:access_type (1 byte)

status (1 byte)
address (4 bytes)
ref (4 bytes)

data (2 bytes)

The first field defines the access type:access_type
0x01
0x02

Description
Read Register from module
Write and Read back Register from module

The second field tells the status of the access:Status0-1-2-3

Description
Command OK
Bus ERROR (Invalid read/write address)
Timeout (FPGA did not respond)
Invalid command

The access size is always a short word i.e. two bytes. The most significant byte of the address
determines the function of the access:Address
0x78000000
0x7a000000

Function
CR/CSR space access
EVR registers access

Read Access (Type 0x01)
The host sends a UDP packet to port 2000 of the VME-EVR with the following contents:
access_type (1 byte)
0x01

status (1 byte)
data (2 bytes)
0x00
0x0000address (4 bytes)
0x7a000000 (Control and Status register Function 0 address)
ref (4 bytes)
0x00000000

If the read access is successful the VME-EVR replies to the same host and port the message camefrom with the following packet:
access_type (1 byte)
0x01

status (1 byte)
data (2 bytes)
0x00
0x0032address (4 bytes)
0x7a000000 (Control and Status register Function 0 address)

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ref (4 bytes)
0x00000000

Write Access (Type 0x02)
The host sends a UDP packet to port 2000 of the VME-EVR with the following contents:
access_type (1 byte)
0x02

status (1 byte)
data (2 bytes)
0x00
0x0001address (4 bytes)
0x7a000002 (Mapping RAM Address register Function 0 address)
ref (4 bytes)
0x00000000

If the write access is successful the VME-EVR replies to the same host and port the message
came from with the following packet:
access_type (1 byte)
0x02

status (1 byte)
data (2 bytes)
0x00
0x0001address (4 bytes)
0x80000000 (Mapping RAM Address register Function 0 address)
ref (4 bytes)
0x00000000

Notice that in the reply message the data returned really is the data read from the address
specified in the address field so one can verify that the data really was written ok.

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cRIO-EVR-300
Connections
The cRIO-EVR connects to the CompactRIO backplane through a DSUB connector. The pin
usage is as follows:
cRIO (DSUB) signal
IDSEL
USER0
USER1
USER2
USER3
USER4
USER5
USER6
USER7
USER8

EVR signal
UART RXD
UNIV3 Output
UNIV2 Output
UNIV1 Output
UNIV0 Output
UNIV3 Input
UNIV2 Input
UNIV1 Input
UNIV0 Input
UART TXD

Description
Asynchronous serial data receive

Asynchronous serial data transmit

The serial interface runs with a baud rate of 115200 baud, 8 bit data, one stop bit, no parity andno handshaking.

Boot Monitor
The boot monitor is started in case the cRIO-EVR receives a ‘@’ character immediately after it
has been powered up. The boot monitor can be used to flash the cRIO-EVR firmware. It supports
the following commands:
Command
EPI
EGI
L
V
PPI
PGI
RP
RG
.

Description
Erase FPGA Primary configuration Image
Outputs ‘+’ for each successful sector erase
Erase FPGA Golden configuration Image
Outputs ‘+’ for each successful sector erase
Load S3-records into RAM‘@’ to stop loading records
Verify S3-records with RAM‘@’ to stop verifying records
Program FPGA Primary Image from RAM to flash.
Outputs ‘+’ for each successful page program
Program FPGA Golden Image from RAM to flash.
Outputs ‘+’ for each successful page program
Load FPGA Primary Image from flash into RAM
Load FPGA Golden Image from flash into RAM
Exit Boot Monitor

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Firmware Upgrade (on Linux)
The configuration flash memory of the cRIO-EVR holds two firmware images: a primary image
and a golden image. The primary image is normally loaded and upgraded. If the primary image
for gets corrupted because of a programming error or power failure during upgrade the golden
image gets loaded which will allow retrying the firmware upgrade of the primary image.
This upgrade procedure will require the cRIO-EVR-UNIVIO –board connected to the cRIOEVR. The firmware can be upgraded on a CompactRIO system using a tool written in LabView.
Connect a USB cable to the cRIO-EVR-UNIVIO USB connector and start your favourite
terminal program with 115200 baud, 8 bit data, one stop bit, no parity and no handshaking.
1. Keep the ‘@’ key pressed, power up the cRIO-EVR and wait until the cRIO-EVR
responds with periods ‘.’
2. Enter the command ‘EPI’ (the characters are not echoed back). The cRIO-EVR will
respond with a number of ‘+’ one for each erased sector and a final ‘.’ when complete.
3. Enter the command ‘L’
4. From a command window send the new firmware image to the serial port e.g.
dd if=firmware_file.exo of=/dev/ttyusb0

5. When the previous operation is complete enter ‘@’ on the terminal to stop loading Srecords. The cRIO-EVR will responds with the number of S-records received and thenumber of checksum errors, two concatenated 32-bit hexadecimal numbers
6. Enter command ‘PPI’ to program the firmware image from RAM to flash. The cRIOEVR will output lots of ‘+’, one for each successful page program and a final ‘.’
7. The following steps are optional: Enter command ‘RP’ to refresh the RAM image fromflash.
8. Enter command ‘V’
9. From a command window send the new firmware image to the serial port e.g.
dd if=firmware_file.exo of=/dev/ttyusb0

10. When the previous operation is complete enter ‘@’ on the terminal to stop loading Srecords. The cRIO-EVR will responds with the number of S-records received and thenumber of checksum errors, two concatenated 32-bit hexadecimal numbers

Programming Details
VME CR/CSR Support
The VME Event Receiver modules provides CR/CSR Support as specified in the VME64x
specification. The CR/CSR Base Address Register is determined after reset by the inverted stateof VME64x P1 connector signal pins GA4*-GA0*. In case the parity signal GAP* does notmatch the GAx* pins the CR/CSR Base Address Register is loaded with the value 0xf8 whichcorresponds to slot number 31.
Note: the boards can be used in standard VME crates where geographical pins do not exist, in thiscase the user may either insert jumpers to set the geographical address or use the default setting
when the board’s CR/CSR base address will be set to 0xf8.

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After power up or reset the board responds only to CR/CSR accesses with its geographicaladdress. Prior to accessing Event Receiver functions the board has to be configured by accessing
the boards CSR space.
The Configuration ROM (CR) contains information about manufacturer, board ID etc. to identify
boards plugged in different VME slots. The following table lists the required field to locate an
Event Receiver module.
CR address
0x27, 0x2B, 0x2F
0x33, 0x37, 0x3B, 0x3F

Register
Manufacturer’s ID (IEEEOUI)
Board ID

VME-EVR-230RF
0x000EB20x455246E6

For convenience functions are provided to locate VME64x capable boards in the VME crate.
STATUS vmeCRFindBoard(int slot, UINT32 ieee_oui, UINT32 board_id,
int *p_slot);

To locate the first Event Receiver in the crate starting from slot 1, the function has to be called
following:#include “vme64x_cr.h”
int slot = 1;
int slot_evr;
vmeCRFindBoard(slot, MRF_IEEE_OUI, MRF_EVR200RF_BID, &slot_evr);

If this function returns OK, an Event Receiver board was found in slot slot_evr.

Event Receiver Function 0,1 and 2 Registers
The Event Receiver specific register are accessed via Function 0 and Function 1 as specified inthe VME64x specification. The access size for Function 0 has been limited to 2 kbytes (0x0800)
so not all EVR registers are accessible through this Function. The access size for Functions 1 and
2 is 256 kbytes, so this function should not be used for A16 access. Contrary to the VME64x
specification the address/address modifier compare logic does not distinguish between privileged
and non-privileged accesses and accepts both.
To enable a Function, the address decoder compare register for the Function in CSR space has tobe programmed. For convenience a function to perform this is provided, too:
STATUS vmeCSRWriteADER(int slot, int func, UINT32 ader);To configure Function 0 of a Event Receiver board in slot 3 to respond to A16 accesses at theaddress range 0x1800-0x1FFF the function has to be called with following values:
vmeCSRWriteADER(3, 0, 0x18A4);ADER contents are composed of the address mask and address modifier, the above is the sameas:

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vmeCSRWriteADER(3, 0, (slot << 11) | (VME_AM_SUP_SHORT_IO << 2));

To get the memory mapped pointer to the configured Function 0 registers on the Event Receiverboard the following VxWorks function has to be called:
MrfEvrStruct *pEvr;
sysBusToLocalAdrs(VME_AM_SUP_SHORT_IO, (char *) (slot << 11),
(void *) pEvr);

Note: using the data transmission capability requires more than 4 kbytes, so using function 1 withaddressing mode A24 is suggested, following:
vmeCSRWriteADER(3, 1, (slot << 19) | (VME_AM_STD_USR_DATA << 2));

MrfEvrStruct *pEvr;
sysBusToLocalAdrs(VME_AM_STD_USR_DATA, (char *) (slot << 19),
(void *) pEvr);

Register Map
Address
0x000
0x004
0x008
0x00C
0x010
0x020
0x024
0x02C
0x040
0x04C
0x050
0x05C
0x060
0x064
0x068
0x06C
0x070
0x074
0x078
0x07C
0x080

Register
StatusControl
IrqFlag
IrqEnable
PulseIrqMap
DataBufCtrl
TxDataBufCtrl
FWVersion
EvCntPresc
UsecDivider
ClockControl
SecSR
SecCounter
EventCounter
SecLatch
EvCntLatch
EvFIFOSec
EvFIFOEvCnt
EvFIFOCode
LogStatus
FracDiv

Type
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT16
UINT32
UINT320x088

RxInitPS

UINT32

0x090
0x094

GPIODir
GPIOInUINT32
UINT32

Description
Status Register
Control Register
Interrupt Flag Register
Interrupt Enable Register
Mapping register for pulse interrupt
Data Buffer Control and Status Register
TX Data Buffer Control and Status Register
Firmware Version Register
Event Counter Prescaler
Divider to get from Event Clock to 1 MHz
Event Clock Control Register
Seconds Shift Register
Timestamp Seconds Counter
Timestamp Event Counter
Timestamp Seconds Counter Latch
Timestamp Event Counter Latch
Event FIFO Seconds Register
Event FIFO Event Counter Register
Event FIFO Event Code Register
Event Log Status Register
Micrel SY87739L Fractional Divider Configuration
Word
Reserved for Initial value for RF recovery DCM
phase shift (VME-EVR-230RF)
Front Panel UnivIO GPIO signal direction
Front Panel UnivIO GPIO input register

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0x098
0x0A0
0x0A4
0x100
0x104
0x108
0x200
0x204
0x208
0x20C
0x210
0x220
…
0x2F0
0x400
0x402
0x404
0x406
0x408
0x40A
0x40C
0x40E
0x440
0x442
0x444
0x446
0x448
0x44A
0x44C
0x44E
0x450
0x452
0x480
0x482
0x484
0x486
0x488
0x48A
0x48C
0x48E
0x490
0x492
0x494
0x496
0x498

GPIOOut
SPIData
SPIControl
Prescaler_0
Prescaler_1
Prescaler_2
Pulse0Ctrl
Pulse0Presc
Pulse0Delay
Pulse0Width

UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32…

…

FPOutMap0
FPOutMap1
FPOutMap2
FPOutMap3
FPOutMap4
FPOutMap5
FPOutMap6
FPOutMap7
UnivOutMap0
UnivOutMap1
UnivOutMap2
UnivOutMap3
UnivOutMap4
UnivOutMap5
UnivOutMap6
UnivOutMap7
UnivOutMap8
UnivOutMap9
TBOutMap0
TBOutMap1
TBOutMap2
TBOutMap3
TBOutMap4
TBOutMap5
TBOutMap6
TBOutMap7
TBOutMap8
TBOutMap9
TBOutMap10
TBOutMap11
TBOutMap12

UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16

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Front Panel UnivIO GPIO output register
SPI Data Register
SPI Control Register
Prescaler 0 Divider
Prescaler 1 Divider
Prescaler 2 Divider
Pulse 0 Control Register
Pulse 0 Prescaler Register
Pulse 0 Delay Register
Pulse 0 Width Register
Pulse 1 Registers
Pulse 2 Registers…
Pulse 15 Registers
Front Panel Output 0 Map Register
Front Panel Output 1 Map Register
Front Panel Output 2 Map Register
Front Panel Output 3 Map Register
Front Panel Output 4 Map Register
Front Panel Output 5 Map Register
Front Panel Output 6 Map Register
Front Panel Output 7 Map Register
Front Panel Universal Output 0 Map Register
Front Panel Universal Output 1 Map Register
Front Panel Universal Output 2 Map Register
Front Panel Universal Output 3 Map Register
Front Panel Universal Output 4 Map Register
Front Panel Universal Output 5 Map Register
Front Panel Universal Output 6 Map Register
Front Panel Universal Output 7 Map Register
Front Panel Universal Output 8 Map Register
Front Panel Universal Output 9 Map Register
Transition Board Output 0 Map Register
Transition Board Output 1 Map Register
Transition Board Output 2 Map Register
Transition Board Output 3 Map Register
Transition Board Output 4 Map Register
Transition Board Output 5 Map Register
Transition Board Output 6 Map Register
Transition Board Output 7 Map Register
Transition Board Output 8 Map Register
Transition Board Output 9 Map Register
Transition Board Output 10 Map Register
Transition Board Output 11 Map Register
Transition Board Output 12 Map Register

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0x49A
0x49C
0x49E
0x4A0
0x4A2
0x4A4
0x4A6
0x4A8
0x4AA
0x4AC
0x4AE
0x4B0
0x4B2
0x4B4
0x4B6
0x4B8
0x4BA
0x4BC
0x4BE
0x500
0x504
0x580
0x584
0x588
0x58C
0x590
0x594
0x598
0x59C
0x600
0x604
0x608
0x60C
0x610
0x614
0x616
0x618
0x620
0x624
0x628
0x62C

TBOutMap13
TBOutMap14
TBOutMap15
TBOutMap16
TBOutMap17
TBOutMap18
TBOutMap19
TBOutMap20
TBOutMap21
TBOutMap22
TBOutMap23
TBOutMap24
TBOutMap25
TBOutMap26
TBOutMap27
TBOutMap28
TBOutMap29
TBOutMap30
TBOutMap31
FPInMap0
FPInMap1
GTX0Dly
GTX1Dly
GTX2Dly
GTX3Dly
GTX4Dly
GTX5Dly
GTX6Dly
GTX7Dly
CML4Pat00
CML4Pat01
CML4Pat10
CML4Pat11
CML4Ena
GTX0Ctrl
CML4HP
GTX0HP
CML4LP
GTX0LP
CML4Samp
GTX0Samp
CML5Pat00
CML5Pat01
CML5Pat10
CML5Pat11

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UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32

Transition Board Output 13 Map Register
Transition Board Output 14 Map Register
Transition Board Output 15 Map Register
Transition Board Output 16 Map Register
Transition Board Output 17 Map Register
Transition Board Output 18 Map Register
Transition Board Output 19 Map Register
Transition Board Output 20 Map Register
Transition Board Output 21 Map Register
Transition Board Output 22 Map Register
Transition Board Output 23 Map Register
Transition Board Output 24 Map Register
Transition Board Output 25 Map Register
Transition Board Output 26 Map Register
Transition Board Output 27 Map Register
Transition Board Output 28 Map Register
Transition Board Output 29 Map Register
Transition Board Output 30 Map Register
Transition Board Output 31 Map Register
Front Panel Input 0 Mapping Register
Front Panel Input 1 Mapping Register
GTX Output 0 Fine Delay Register
GTX Output 1 Fine Delay Register
GTX Output 2 Fine Delay Register
GTX Output 3 Fine Delay Register
GTX Output 4 Fine Delay Register
GTX Output 5 Fine Delay Register
GTX Output 6 Fine Delay Register
GTX Output 7 Fine Delay Register
20 bit output pattern for state low
20 bit output pattern for state rising edge
20 bit output pattern for state falling edge
20 bit output pattern for state highCML 4 Output Control Register

UINT16

CML 4 Output High Period CountUINT16

CML 4 Output Low Period CountUINT32

CML 4 Output Number of 20 bit word patterns
GTX0 Output Number of 40 bit word patterns
20 bit output pattern for state low
20 bit output pattern for state rising edge
20 bit output pattern for state falling edge
20 bit output pattern for state highUINT32
UINT32
UINT32
UINT32

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0x630
0x634
0x636
0x638
0x640
0x644
0x648
0x64C
0x650
0x654
0x656
0x658
0x670
0x674
0x676
0x678
0x690
0x694
0x696
0x698
0x6B0
0x6B4
0x6B6
0x6B8
0x6D0
0x6D4
0x6D6
0x6D8
0x6E0
0x6E4
0x6E6
0x6E8
0x800 –
0xFFF
0x1000 –0x17FF0x1800 –CML5Ena
GTX1Ctrl
CML5HPGTX1HP
CML5LP
GTX1LP
CML5Samp
GTX1Samp
CML6Pat00
CML6Pat01
CML6Pat10
CML6Pat11
CML6Ena
GTX2Ctrl
CML6HPGTX2HP
CML6LP
GTX2LP
CML6Samp
GTX2Samp
GTX3Ctrl
GTX3HP
GTX3LP
GTX3Samp
GTX4Ctrl
GTX4HP
GTX4LP
GTX4Samp
GTX5Ctrl
GTX5HP
GTX5LP
GTX5Samp
GTX6Ctrl
GTX6HP
GTX6LP
GTX6Samp
GTX7Ctrl
GTX7HP
GTX7LP
GTX7Samp
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UINT32

CML 5 Output Control Register

UINT16

CML 5 Output High Period CountUINT16

CML 5 Output Low Period CountUINT32
UINT32
UINT32
UINT32
UINT32
UINT32

CML 5 Output Number of 20 bit word patterns
GTX1 Output Number of 40 bit word patterns
20 bit output pattern for state low
20 bit output pattern for state rising edge
20 bit output pattern for state falling edge
20 bit output pattern for state highCML 6 Output Control Register

UINT16

CML 6 Output High Period CountUINT16

CML 6 Output Low Period CountUINT32

CML 6 Output Number of 20 bit word patterns
GTX2 Output Number of 40 bit word patterns
GTX3 Output Control Register
GTX3 Output High Period Count
GTX3 Output Low Period Count
GTX3 Output Number of 40 bit word patterns
GTX4 Output Control Register
GTX4 Output High Period CountGTX4 Output Low Period CountGTX4 Output Number of 40 bit word patterns
GTX5 Output Control Register
GTX5 Output High Period Count
GTX5 Output Low Period Count
GTX5 Output Number of 40 bit word patterns
GTX6 Output Control Register
GTX6 Output High Period Count
GTX6 Output Low Period Count
GTX6 Output Number of 40 bit word patterns
GTX7 Output Control Register
GTX7 Output High Period Count
GTX7 Output Low Period Count
GTX7 Output Number of 40 bit word patterns
Data Buffer Receive Memory

UINT32
UINT16
UINT16
UINT32
UINT32
UINT16
UINT16
UINT32
UINT32
UINT16
UINT16
UINT32
UINT32
UINT16
UINT16
UINT32
UINT32
UINT16
UINT16
UINT32

Diagnostics counters
TxDataBuf

Data Buffer Transmit Memory

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0x1FFF0x2000 –0x3FFF0x4000 –0x5FFF0x6000 –0x7FFF0x8000 –0x80FF0x8100 –0x81FF0x8200 –0x82FF0x8300 –0x83FF0x20000 –0x23FFF

EventLog

512 x 16 byte position Event Log

MapRam1

Event Mapping RAM 1

MapRam2

Event Mapping RAM 2

configROM
scratchRAMSFPEEPROM

SFP Transceiver EEPROM contents (SFP address
0xA0)
SFP Transceiver diagnostics (SFP address 0xA2)

SFPDIAGCML4PMEM
GTX0MEM

0x24000 –0x27FFF

CML5PMEM
GTX1MEM

0x28000 –0x2BFFF

CML6PMEM
GTX2MEM

0x2C000 –0x2FFFF
0x30000 –0x33FFF
0x34000 –0x37FFF
0x38000 –0x3BFFF0x3C000 –0x3FFFF

GTX3MEM

Pattern memory:
8k bytes CML output 4 (VME-EVR-230RF)
16k bytes GTX output 0 (cPCI-EVRTG-300)
Pattern memory:
8k bytes CML output 5 (VME-EVR-230RF)
16k bytes GTX output 1 (cPCI-EVRTG-300)
Pattern memory:
8k bytes CML output 6 (VME-EVR-230RF)
16k bytes GTX output 2 (cPCI-EVRTG-300)
Pattern memory:
16k bytes GTX output 3 (cPCI-EVRTG-300)
Pattern memory:
16k bytes GTX output 4 (cPCI-EVRTG-300)
Pattern memory:
16k bytes GTX output 5 (cPCI-EVRTG-300)
Pattern memory:
16k bytes GTX output 6 (cPCI-EVRTG-300)
Pattern memory:
16k bytes GTX output 7 (cPCI-EVRTG-300)

GTX4MEM
GTX5MEM
GTX6MEM
GTX7MEM

Status Register
address
0x000

bit 31
DBUS7

bit 30
DBUS6

bit 29DBUS5

Bit 28
DBUS4

bit 27
DBUS3

bit 26
DBUS2

bit 25DBUS1

bit 24DBUS0address0x001

bit 23

bit 22

bit 21

bit 20

bit 19bit 18bit 17

bit 16LEGVIO

address

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

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0x002
address
bit 7
0x003 SFPMOD

bit 6
LINK

Bit
DBUS7
DBUS6
DBUS5
DBUS4
DBUS3
DBUS2
DBUS1
DBUS0
LEGVIOSFPMOD

bit 5
FIFOSTP

Bit 4

bit 3

bit 2

bit 1

bit 0

Function
Read status of DBUS bit 7
Read status of DBUS bit 6
Read status of DBUS bit 5
Read status of DBUS bit 4
Read status of DBUS bit 3
Read status of DBUS bit 2
Read status of DBUS bit 1
Read status of DBUS bit 0
Legacy VIO (series 100, 200 and 230)
SFP module status:‘0’ – plugged in‘1’ – no module installed
Link status:‘0’ – link down
‘1’ – link up
Event FIFO stopped flag

LINK

FIFOSTP

Control Register
address
0x004

bit 31
EVREN

bit 30
EVFWD

bit 29TXLP

bit 28RXLP

bit 27
OUTEN

Obit 26
SRST

bit 25LEMDE

bit 24
GTXIO

address
0x006

bit 15

bit 14TSDBUSbit 13
RSTS

bit 12

bit 11

bit 10
LTS

bit 9
MAPEN

bit 8
MAPRS

address
0x007

bit 7
LOGRS

bit 6
LOGEN

bit 5
Bit 4
LOGDIS LOGSE

bit 3
RSFIFO

bit 2

bit 1

bit 0

Bit
EVREN
TXLP

Function
Event Receiver Master enable
Transmitter loopback:0 – Receive signal from SFP transceiver (normal operation)
1 – Loopback EVR TX into EVR RX
Receiver loopback:0 – Transmit signal from EVR on SFP transceiver TX
1 – Loopback SFP RX on SFP TX
Output enable for FPGA external components (cPCI-EVRTG-300)
0 – disable delay line outputs
1 – enable delay line outputs
Soft reset IP
Little endian mode (cPCI-EVR-300)
0 – PCI core in big endian mode (power up default)

RXLP

OUTEN

SRST
LEMDE

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1 – PCI core in little endian mode
GUN-TX output hardware inhibit override
0 – honor hardware inhibit signal (default)
1 – inhibit override, don’t care about hardware inhibit input state
TSDBUS Use timestamp counter clock on DBUS4
RSTS
Reset Timestamp. Write 1 to reset timestamp event counter and timestamp
latch.
LTS
Latch Timestamp: Write 1 to latch timestamp from timestamp event
counter to timestamp latch.
MAPEN Event mapping RAM enable.
MAPRS Mapping RAM select bit for event decoding:0 – select mapping RAM 1
1 – select mapping RAM 2.
LOGRSReset Event Log. Write 1 to reset log.
LOGEN Enable Event Log. Write 1 to (re)enable event log.
LOGDIS Disable Event Log. Write 1 to disable event log.
LOGSE
Log Stop Event Enable.
RSFIFO Reset Event FIFO. Write 1 to clear event FIFO.
GTXIOInterrupt Flag Register
address
0x008

bit 31

bit 30

bit 29bit 28bit 27

bit 26bit 25bit 24address
0x00b

Bit 7

bit 6
IFLINK

bit 5
Bit 4
IFDBUF IFHW

bit 3
IFEV

bit 2
IFHB

bit 1
IFFF

bit 0
IFVIO

Bit
IFLINKIFDBUF
IFHW
IFEV
IFHB
IFFF
IFVIO

Function
Link state change interrupt flag
Data buffer flag
Hardware interrupt flag (mapped signal)
Event interrupt flag
Heartbeat interrupt flag
Event FIFO full flag
Receiver violation flag

Interrupt Enable Register
address
0x00c

Bit 31
IRQEN

bit 30
PCIIE

bit 29bit 28bit 27

bit 26bit 25bit 24address
0x00f

Bit 7

bit 6
IELINK

bit 5
Bit 4
IEDBUF IEHW

bit 3
IEEV

bit 2
IEHB

bit 1
IEFF

bit 0
IEVIO

Bit
IRQEN

Function
Master interrupt enable:
0 – disable all interrupts
1 – allow interrupts

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PCIIE

PCI core interrupt enable (cPCI-EVR-300)
This bit is used by the low level driver to disable further interrupts before
the first interrupt has been handled in user space
IELINK Link state change interrupt flag
IEDBUF Data buffer interrupt enable
IEHW
Hardware interrupt enable (mapped signal)
IEEV
Event interrupt enable
IEHB
Heartbeat interrupt enable
IEFF
Event FIFO full interrupt enable
IEVIO
Receiver violation interrupt enable

Hardware Interrupt Mapping Register
address
0x013

Bit 7

bit 6

bit 5
Bit 4
bit 3
bit 2
Mapping ID (see Table 1 for mapping IDs)

bit 1

bit 0

bit 10
bit 9
RXSIZE(11:8)

bit 8

bit 2

bit 0

Receive Data Buffer Control and Status Register
address
0x022

Bit 15DBRX/
DBENA

address
0x023

bit 7

bit 14
bit 13
DBRDY/ DBCS
DBDIS
bit 6

Bit
DBRX
DBENA
DBRDY
DBDIS
DBCS

bit 5

bit 12
DBEN

bit 11

bit 4
bit 3
RXSIZE(7:0)

bit 1

Function
Data Buffer Receiving (read-only)
Set-up for Single Reception (write ‘1’ to set-up)
Data Buffer Transmit Complete / Interrupt Flag
Stop Reception (write ‘1’ to stop/disable)
Data Buffer Checksum Error (read-only)
Flag is cleared by writing ‘1’ to DBRX or DBRDY or disablingdata buffer
Data Buffer Enable Data Buffer Mode‘0’ – Distributed bus not shared with data transmission, full speed
distributed bus‘1’ – Distributed bus shared with data transmission, half speed
distributed bus
Data Buffer Received Buffer Size (read-only)

DBEN

RXSIZE

Transmit Data Buffer Control Register
address
0x025

bit 23

bit 22

bit 21

bit 20

bit 19bit 18address
0x026

bit 15

Bit 14

bit 13

bit 12

bit 11

bit 10bit 9
DTSZ(10:8)

bit 8

address

Bit 7

bit 6

bit 5

Bit 4

bit 3

bit 2

bit 1

bit 0

TXCPT TXRUN TRIG

bit 17

bit 16ENA

MODE

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0x027

DTSZ(7:2)

0

0

Bits

Function

TXCPT
TXRUN

Data Buffer Transmission Complete
Data Buffer Transmission Running – set when data transmission has
been triggered and has not been completed yet
Data Buffer Trigger Transmission
Write ‘1’ to start transmission of data in buffer
Data Buffer Transmission enable‘0’ – data transmission engine disabled‘1’ – data transmission engine enabled
Distributed bus sharing mode‘0’ – distributed bus not shared with data transmission‘1’ – distributed bus shared with data transmission
Data Transfer size 4 bytes to 2k in four byte increments

TRIG
ENA

MODE

DTSZ(10:8)

FPGA Firmware Version Register
address
0x02C

bit 31address
0x02D

bit 23address
0x02F

bit 7

bit 27

bit 26

EVR = 0x1

bit 24Form Factor
bit 8

Reserved
bit 0
Version ID

Bits

Function

Form Factor

0 – CompactPCI 3U
1 – PMC
2 – VME64x
3 – CompactRIO
4 – CompactPCI 6U

Event Counter Clock Prescaler Register
address
0x042

bit 15bit 0
Timestamp Event Counter Clock Prescaler Register

Microsecond Divider Register
address
0x04e

bit 15bit 0
Rounded integer value of 1 µs * event clock

For 100 MHz event clock this register should read 100, for 50 MHz event clock this registershould read 50. This value is used e.g. for the heartbeat timeout.

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Clock Control Register
address
0x052
address
0x053

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

RECDCM
RUN

RECDCM
INITDONERECDCM
PSDONE

EVDCM
STOPPED

EVDCM
LOCKED

EVDCM
PSDONECGLOCK

RECDCM
PSDEC

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

RECDCM
PSINC

RECDCM
RES

EVDCM
PSDEC

EVDCM
PSINC

EVDCM
SRUN

EVDCM
SRES

EVDCM
RES

EVCLKSEL

Bit
CGLOCK
Other bits

Function
Micrel SY87739L locked (read-only)
n/a on cPCI-EVR

Seconds Shift Register
address
0x05c

bit 31

bit 0
Seconds Shift Register (read-only)

Seconds Counter Register
address
0x060

bit 31

bit 0
Seconds Counter Register (read-only)

Timestamp Event Counter Register
address
0x064

bit 31

bit 0
Timestamp Event Counter Register (read-only)

Seconds Latch Register
address
0x068

bit 31

bit 0
Seconds Latch Register (read-only)

Timestamp Event Latch Register
address
0x06c

bit 31

bit 0
Timestamp Event Latch Register (read-only)

FIFO Seconds Register
address
0x070

bit 31

bit 0
FIFO Seconds Register (read-only)

FIFO Timestamp Register
address
0x074

bit 31

bit 0
FIFO Timestamp Register (read-only)

FIFO Event Register
address
0x07b

bit 7

bit 0
FIFO Event Code Register (read-only)Document: EVR-MRM-003.doc
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Note that reading the FIFO event code registers pulls the event code and timestamp/seconds value
from the FIFO for access. The correct order to read an event from FIFO is to first read the eventcode register and after this the timestamp/seconds registers in any order. Every read access to the
FIFO event register pulls a new event from the FIFO if it is not empty.

Event Log Status Register
address
0x07C

bit 31
LOGOV

address
0x07E

bit 15

bit 30

bit 29bit 28bit 9

bit 27

bit 26bit 25bit 8

bit 24

bit 0
Log writing pointerSY87739L Fractional Divider Configuration Word
address
0x080

bit 31

bit 0
SY87739L Fractional Divider Configuration Word

Configuration Word
0x00DE816D
0x00FE816D
0x0C928166
0x018741AD
0x072F01AD
0x049E81AD
0x008201AD
0x025B41ED
0x0187422D
0x0082822D
0x0106822D
0x019E822D
0x018742AD
0x0C9282A6
0x009743AD
0x025B43AD
0x0176C36D

Frequency with 24 MHz reference oscillator
125 MHz124.95 MHz
124.908 MHz
119 MHz114.24 MHz
106.25 MHz
100 MHz99.956 MHz
89.25 MHz
81 MHz80 MHz78.900 MHz
71.4 MHz62.454 MHz
50 MHz49.978 MHz
49.965 MHz

Prescaler 0 Register
address
0x102

Bit 15

bit 0
Prescaler 0 Register

Prescaler 1 Register
address
0x106

Bit 15

bit 0
Prescaler 1 Register

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Prescaler 2 Register
address
0x10a

Bit 15

bit 0
Prescaler 2 Register

Pulse Generator Registers
address
0x203

bit 7
PxOUT

address
0x204

bit 31address
0x208

bit 31address
0x20C

bit 31

bit 6
PxSWS

bit 5
PxSWR

bit 4
PxPOL

bit 3
PxMRE

bit 2
PxMSE

bit 1
PxMTE

bit 0
PxENA
bit 0

Pulse Generator Prescaler Register
bit 0
Pulse Generator Delay Register
bit 0
Pulse Generator Width Register

Note: addresses shown above are for pulse generator 0.

bit
PxOUT
PxSWS
PxSWC
PxPOL

PxMRE

PxMSE

PxMTE

PxENA

Function
Pulse Generator Output (read-only)
Pulse Generator Software Set
Pulse Generator Software Reset
Pulse Generator Output Polarity
0 – normal polarity
1 – inverted polarity
Pulse Generator Event Mapping RAM Reset Event Enable
0 – Reset events disabled
1 – Mapped Reset Events reset pulse generator output
Pulse Generator Event Mapping RAM Set Event Enable
0 – Set events disabled
1 – Mapped Set Events set pulse generator output
Pulse Generator Event Mapping RAM Trigger Event Enable
0 – Event Triggers disabled
1 – Mapped Trigger Events trigger pulse generator
Pulse Generator Enable
0 – generator disabled
1 – generator enabled

Front Panel Output Mapping Registers
address
0x401
0x403
0x405
0x407
0x409
0x40B

Bit 7

bit 6
bit 5
Bit 4
bit 3
bit 2
bit 1
Front panel OUT0 Mapping ID (see Table 1 for mapping IDs)
Front panel OUT1 Mapping ID
Front panel OUT2 Mapping ID
Front panel OUT3 Mapping ID
Front panel OUT4 Mapping ID
Front panel OUT5 Mapping ID

bit 0

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0x40D
0x40F

Front panel OUT6 Mapping ID
Front panel OUT7 Mapping ID

Notes:cPCI-EVR does not have any Front panel outputs.
PMC-EVR has three front panel outputs OUT0 to OUT2.
VME-EVR-230 has eight Front panel outputs OUT0 to OUT7.
VME-EVR-230RF has seven Front panel outputs OUT0 to OUT3 (TTL level), OUT4 to OUT6 CML level (see section about CML
outputs for details).

Universal I/O Output Mapping Registers
address
0x441
0x443
0x445
0x447
0x449
0x44b
0x44d
0x44f
0x451
0x453
0x453
0x453

Bit 7

bit 6
bit 5
Bit 4
bit 3
bit 2
bit 1
Universal I/O UNIV0 Mapping ID (see Table 1 for mapping IDs)
Universal I/O UNIV1 Mapping ID
Universal I/O UNIV2 Mapping ID
Universal I/O UNIV3 Mapping ID
Universal I/O UNIV4 Mapping ID
Universal I/O UNIV5 Mapping ID
Universal I/O UNIV6 Mapping ID
Universal I/O UNIV7 Mapping ID
Universal I/O UNIV8 Mapping ID
Universal I/O UNIV9 Mapping ID
Universal I/O UNIV10 Mapping ID
Universal I/O UNIV11 Mapping ID

bit 0

Notes:cPCI-EVR-220/230 has two Universal I/O slots (four outputs UNIV0 to UNIV3). An optional side-by-side module provides three
more slots (six additional outputs UNIV4 to UNIV9).
PMC-EVR does not have any Universal I/O slots.
VME-EVR has two Universal I/O slots (four outputs UNIV0 to UNIV3).
cPCI-EVR-300 has six Universal I/O slots (twelve outputs UNIV0 to UNIV11).

Transition Board Output Mapping Registers
address
0x481
0x483
0x485
…

Bit 7
bit 6
bit 5
Bit 4
bit 3
bit 2
bit 1
bit 0
Transition Board Output TBOUT0 Mapping ID (see Table 1 for mapping IDs)
Transition Board Output TBOUT1 Mapping ID
Transition Board Output TBOUT2 Mapping ID…

Notes:cPCI-EVRs and cRIO-EVR do not have any Transition board outputs.

Front Panel Input Mapping Registers
address
0x500

bit 31address
0x501

bit 23
T0DB7

address
0x502

bit 15address
0x503

bit 7

bit 30

bit 22
T0DB6

bit 29bit 28bit 27

bit 26bit 25bit 24EXTLV0BCKLE0EXTLE0EXTED0

BCKEV0EXTEV0

bit 21
T0DB5

bit 20
T0DB4

bit 19T0DB3

bit 18
T0DB2

bit 17
T0DB1

bit 16
T0DB0
bit 8

Backward Event Code Register for front panel input 0
bit 0
External Event Code Register for front panel input 0

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address
0x504

bit 31address
0x505

bit 23
T1DB7

address
0x506

bit 15address
0x507

bit 7

bit 30

bit 22
T1DB6

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bit 29bit 28bit 27

bit 26bit 25bit 24EXTLV1BCKLE1

EXTLE1

EXTED1

BCKEV1EXTEV1

bit 21
T1DB5

bit 20
T1DB4

bit 19
T1DB3

bit 18
T1DB2

bit 17
T1DB1

bit 16
T1DB0
bit 8

Backward Event Code Register for front panel input 1
bit 0
External Event Code Register for front panel input 1bit
EXTLVxFunction
Backward HW Event Level Sensitivity for input x
0 – active high1 – active low
BCKLEx Backward HW Event Level Trigger enable for input x
0 – disable level events
1 – enable level events, send out backward event code every 1 us when
input is active (see EXTLVx for level sensitivity)
EXTLEx External HW Event Level Trigger enable for input x
0 – disable level events
1 – enable level events, apply external event code to active mapping
RAM every 1 us when input is active (see EXTLVx for level sensitivity)
EXTEDx Backward HW Event Edge Sensitivity for input x
0 – trigger on rising edge
1 – trigger on falling edge
BCKEVx Backward HW Event Edge Trigger Enable for input x
0 – disable backward HW event
1 – enable backward HW event, send out backward event code on
detected edge of hardware input (see EXTEDx bit for edge)
EXTEVx External HW Event Enable for input x
0 – disable external HW event
1 – enable external HW event, apply external event code to active
mapping RAM on edge of hardware input
TxDB7Backward distributed bus bit enable:
TxDB0
0 – disable distributed bus bit
1 – enable distributed bus bit control from hardware input: e.g. when
TxDB7 is ‘1’ the hardware input x state is sent out on distributed bus bit
7.

CML Output Pattern Registers (CMLxPatxx)
bit 23

bit 22

bit 21

bit 20

bit 1919 MSBbit 1818

bit 1717

bit 1616

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bit 1515

bit 1414

bit 1313

bit 12
12

bit 11
11

bit 10
10

bit 9
9

bit 8
8

bit 7
7

bit 6
6

bit 5
5

bit 4
4

bit 3
3

bit 2
2

bit 1
1

bit 0
0 LSB

Bit 19 MSB is sent out first, LSB lastNote that GTX pattern registers are accessed through the first four address locations of the GTX
pattern memory.

CML/GTX Output Control Register
Address

bit 31

bit 16Frequency mode trigger position

Address

bit 15

bit 14Address

bit 7
CMLRC

bit 6
CMLTL

GTX2MD

GTXPH1:0

CMLRC
CMLTL
CMLMD

CMLRESCMLPWD

CMLENAbit 13

bit 12

bit 11

bit 10GTX2MD

bit 9
GTXPH1bit 8
GTXPH0

bit 5
bit 4
CMLMD

bit 3

bit 2
bit 1
bit 0
CMLRES CMLPWD CMLENAGUN-TX-203 Mode (cPCI-EVRTG-300 only)
0 – CML/GTX Mode1 – SFP output in GUN-TX-203 Mode
GUN-TX-203 Trigger output phase shift (cPCI-EVRTG-300 only)
00 – no delay
01 – output pulse delayed by ¼ event clock period (~2 ns)
10 – output pulse delayed by ½ event clock period (~4 ns)
11 – output pulse delayed by ¾ event clock period (~6 ns)
CML Pattern recycle
CML Frequency mode trigger level
CML Mode Select:
00 = classic mode
01 = frequency mode
10 = pattern mode
11 = undefined
CML Reset
1 = reset CML output (default on EVR power up)
0 = normal operation
CML Power Down
1 = CML outputs powered down (default on EVR power up)
0 = normal operation
CML Enable
0 = CML output disabled (default on EVR power up)
1 = CML output enabledMicro-Research Finland Oy
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Document: EVR-MRM-003.doc
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SFP Module EEPROM and Diagnostics
Small Form Factor Pluggable (SFP) transceiver modules provide a means to identify the moduleby accessing an EEPROM. As an advanced feature some modules also support reading dynamic
information including module temperature, receive and transmit power levels etc. from themodule. The EVR gives access to all of this information through a memory window of 2 × 256
bytes. The first 256 bytes consist of the EEPROM values and the rest of the advanced values.
Byte #
DecimalField size
(bytes)

0
1

1
1

2
3 – 10

1
8

11
12

1
1

13
14

1
1

15

1

16

1

17

1

18

1

19
20 – 351
16

36
37 – 391
3

40 – 5516

56 – 594

60 – 62633
1

64 – 652

66
67
68 – 83

1
1
16

Notes
BASE ID FIELDS
Type of serial transceiver
Extended identifier of type serialtransceiver
Code for connector type
Code for electronic compatibility or
optical compatibility
Code for serial encoding algorithm
Nominal bit rate, units of 100
MBits/sec
Reserved
Link length supported for 9/125 µm
fiber, units of km
Link length supported for 9/125 µm
fiber, units of 100 m
Link length supported for 50/125µm fiber, units of 10 m
Link length supported for 62.5/125µm fiber, units of 10 m
Link length supported for copper,
units of meters
Reserved
SFP transceiver vendor name(ASCII)
Reserved
SFP transceiver vendor IEEE
company ID
Part number provided by SFP
transceiver vendor (ASCII)
Revision level for part number
provided by vendor (ASCII)
Reserved
Check code for Base ID Fields
EXTENDED ID FIELDS
Indicated which optional SFP
signals are implemented
Upper bit rate margin, units of %Lower bit rate margin, units of %Serial number provided by vendor

Value Hex

03 = SFP transceiver
04 = serial ID module
definition
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84 – 91
92 – 9495

83
1

96 – 127
128 – 25532

256 – 2572

258 – 2592

260 – 2612

262 – 263

2

264 – 2652

266 – 2672

268 – 2692

270 – 2712

272 – 2732

274 – 2752

276 – 2772

278 – 2792

280 – 281

2

Document: EVR-MRM-003.doc
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Vendor’s manufacturing date code
Reserved
Check code for the Extended ID
FieldsVENDOR SPECIFIC ID FIELDS
Vendor specific data
Reserved
ENHANCED FEATURE SET MEMORY
Temp H Alarm
Signed twos complement
integer in increments of 1/256°C
Temp L Alarm
Signed twos complement
integer in increments of 1/256°C
Temp H Warning
Signed twos complement
integer in increments of 1/256°C
Temp L Warning
Signed twos complement
integer in increments of 1/256°C
VCC H Alarm
Supply voltage decoded as
unsigned integer in incrementsof 100 µV
VCC L Alarm
Supply voltage decoded as
unsigned integer in incrementsof 100 µV
VCC H Warning
Supply voltage decoded as
unsigned integer in incrementsof 100 µV
VCC L Warning
Supply voltage decoded as
unsigned integer in incrementsof 100 µV
Tx Bias H Alarm
Laser bias current decoded as
unsigned integer in incrementof 2 µA
Tx Bias L Alarm
Laser bias current decoded as
unsigned integer in incrementof 2 µA
Tx Bias H Warning
Laser bias current decoded as
unsigned integer in incrementof 2 µA
Tx Bias L Warning
Laser bias current decoded as
unsigned integer in incrementof 2 µA
Tx Power H Alarm
Transmitter average opticalpower decoded as unsigned
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282 – 283

2

Tx Power L Alarm

284 – 285

2

Tx Power H Warning

286 – 287

2

Tx Power L Warning

288 – 289

2

Rx Power H Alarm

290 – 291

2

Rx Power L Alarm

292 – 293

2

Rx Power H Warning

294 – 295

2

Rx Power L Warning

296 – 311
312 – 350
351
352 – 353

16

Reserved
External Calibration Constants
Checksum for Bytes 256 – 350
Real Time Temperature

354 – 355

2

Real Time VCC Power
SupplyVoltage

356 – 357

2

Real Time Tx Bias Current

358 – 359

2

Real Time Tx Power360 – 361

2

Real Time Rx Power362 – 365

4

Reserved

1
2

Transmitter average opticalpower decoded as unsigned
integer in increments of 0.1µW
Transmitter average opticalpower decoded as unsigned
integer in increments of 0.1µW
Transmitter average opticalpower decoded as unsigned
integer in increments of 0.1µW
Receiver average opticalpower decoded as unsigned
integer in increments of 0.1µW
Receiver average opticalpower decoded as unsigned
integer in increments of 0.1µW
Receiver average opticalpower decoded as unsigned
integer in increments of 0.1µW
Receiver average opticalpower decoded as unsigned
integer in increments of 0.1µW

Signed twos complement
integer in increments of 1/256°C
Supply voltage decoded as
unsigned integer in incrementsof 100 µV
Laser bias current decoded as
unsigned integer in incrementof 2 µA
Transmitter average opticalpower decoded as unsigned
integer in increments of 0.1µW
Receiver average opticalpower decoded as unsigned
integer in increments of 0.1µW

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366

1

Status/Control

367
368

1
1

Reserved
Alarm Flags

369

1

Alarm Flags cont.

370 – 371
372

2
1

Reserved
Warning Flags

373

1

Warning Flags cont.

374 – 511

bit 7: TX_DISABLE Statebit 6 – 3: Reserved
bit 2: TX_FAULT Statebit 1: RX_LOS Statebit 0: Data Ready (Bar)bit 7: Temp High Alarm
bit 6: Temp Low Alarm
bit 5: VCC High Alarm
bit 4: VCC Low Alarm
bit 3: Tx Bias High Alarm
bit 2: Tx Bias Low Alarm
bit 1: Tx Power High Alarm
bit 0: Tx Power Low Alarm
bit 7: Rx Power High Alarm
bit 6: Rx Power Low Alarm
bit 5 – 0: Reserved
bit 7: Temp High Warning
bit 6: Temp Low Warning
bit 5: VCC High Warning
bit 4: VCC Low Warning
bit 3: Tx Bias High Warning
bit 2: Tx Bias Low Warning
bit 1: Tx Power High Warning
bit 0: Tx Power Low Warning
bit 7: Rx Power High Warning
bit 6: Rx Power Low Warning
bit 5 – 0: Reserved

Reserved/Vendor Specific

Application Programming Interface (API)A Linux device driver and application interface is provided to setup up the Event Receiver.

Function Reference
int EvrOpen(struct MrfErRegs **pEr, char *device_name);
Description
Parameters

struct MrfErRegs **pEr

char *device_name

Return value

Opens the EVR device for access. Simultaneousaccesses are allowed.
EvgOpen returns pointer to EVR registers bymemory mapping the I/O registers into user
space.
Holds the device name of the EVR, e.g.
/dev/ega3. The device names are set up by themodule_load script of the device driver.
Return file descriptor on success.

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Returns -1 on error.

int EvrClose(int fd);
Description
Parameters
Return value

int fdCloses the EVR device after opening by
EvrOpen.
File descriptor returned by EvrOpen
Returns zero on success.
Returns -1 on error.

int EvrEnable(volatile struct MrfErRegs *pEr, int state);
Description
Parameters

volatile struct MrfErRegs *pEr
int state

Return value

Enables the EVR and allows reception of
events.
Pointer to memory mapped EVR registerbase.
0: disable
1: enable
Returns zero when EVR disabled
Returns non-zero when EVR enabled

int EvrGetEnable(volatile struct MrfErRegs *pEr);
Description
Parameters

volatile struct MrfErRegs *pEr

Return value

Retrieves state of the EVR.
Pointer to memory mapped EVR register
base.
Returns zero when EVR disabled
Returns non-zero when EVR enabled

void EvrDumpStatus(volatile struct MrfErRegs *pEr);
Description
Parameters

volatile struct MrfErRegs *pEr

Return value

Dump EVR status.
Pointer to memory mapped EVR register
base.
None

int EvrGetViolation(volatile struct MrfErRegs *pEr, int clear);
Description
Parameters

volatile struct MrfErRegs *pEr
int clear

Return value

Get/clear EVR link violation status.
Pointer to memory mapped EVR registerbase.
0: don’t clear
1: clear status
Returns 0 when no violation detected.
Return non-zero when violation detected.

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void EvrDumpMapRam(volatile struct MrfErRegs *pEr, int ram);
Description
Parameters

volatile struct MrfErRegs *pEr
int ramReturn value

Dump EVR mapping RAM.
Pointer to memory mapped EVR register
base.
Number of RAM: 0 or 1
None

int EvrMapRamEnable(volatile struct MrfErRegs *pEr, int ram, int
enable);Description
Parameters

volatile struct MrfErRegs *pEr
int ramint enable

Return value

Enable/disable EVR mapping RAM.
Pointer to memory mapped EVR register
base.
Number of RAM: 0 or 1
0: disable RAM
1: enable RAM
None

int EvrSetForwardEvent(volatile struct MrfErRegs *pEr, int ram, int
code, int enable);
Description
Parameters

volatile struct MrfErRegs *pEr
int ramint code
int enable

Return value

Enable/disable EVR event forwarding.
Pointer to memory mapped EVR register
base.
Number of mapping RAM: 0 or 1
Event code to enable/disable event
forwarding
0: disable event forwarding for code
1: enable event forwarding for code
None

int EvrEnableEventForwarding(volatile struct MrfErRegs *pEr, int
state);
Description
Parameters

volatile struct MrfErRegs *pEr
int state

Return value

Enables forwarding of enabled event codes.
Pointer to memory mapped EVR registerbase.
0: disable forwarding
1: enable forwarding
Returns zero when forwarding disabled
Returns non-zero when forwarding enabled

int EvrGetEventForwarding(volatile struct MrfErRegs *pEr);
Description
Parameters
Return value

volatile struct MrfErRegs *pEr

Retrieves state of event forwarding.
Pointer to memory mapped EVR register
base.
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Returns non-zero when forwarding enabled

int EvrSetLedEvent(volatile struct MrfErRegs *pEr, int ram, int code,
int enable);
Description
Parameters

volatile struct MrfErRegs *pEr
int ramint code
int enable

Return value

Enable/disable EVR led event (Front panel
led will flash up for enabled event codes).
Pointer to memory mapped EVR register
base.
Number of mapping RAM: 0 or 1
Event code to enable/disable led event for
0: disable led event for code
1: enable led event for code
None

int EvrSetFIFOEvent(volatile struct MrfErRegs *pEr, int ram, int code,
int enable);
Description
Parameters

volatile struct MrfErRegs *pEr
int ramint code
int enable

Return value

Enable/disable storing specified event code
into FIFO.
Pointer to memory mapped EVR register
base.
Number of mapping RAM: 0 or 1
Event code to enable/disable
0: disable storing event code in FIFO
1: enable storing event code in FIFO
None

int EvrSetLatchEvent(volatile struct MrfErRegs *pEr, int ram, int code,
int enable);
Description
Parameters

volatile struct MrfErRegs *pEr
int ramint code
int enable

Return value

Enable/disable latching timestamp on
specified event code.
Pointer to memory mapped EVR register
base.
Number of mapping RAM: 0 or 1
Event code to enable/disable
0: disable latching of timestamp on eventcode
1: enable latching of timestamp upon
reception of event code
None

int EvrSetLogStopEvent(volatile struct MrfErRegs *pEr, int ram, int
code, int enable);
Description
Parameters

volatile struct MrfErRegs *pEr

Enable/disable stopping of writes to eventlog on reception of event code.
Pointer to memory mapped EVR registerbase.

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int ramint code
int enable

Return value

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Number of mapping RAM: 0 or 1
Event code to enable/disable
0: disable stop log event
1: stop log writes upon reception of event
code
None

int EvrClearFIFO(volatile struct MrfErRegs *pEr);
Description
Parameters

volatile struct MrfErRegs *pEr

Return value

Clear EVR Event FIFO.
Pointer to memory mapped EVR register
base.
None.

int EvrGetFIFOEvent(volatile struct MrfErRegs *pEr, struct FIFOEvent*fe);
Description
Parameters

volatile struct MrfErRegs *pEr
struct FIFOEvent *fe
struct FIFOEvent {u32 TimestampHigh;u32 TimestampLow;
u32 EventCode;};Get one Event from EVR Event FIFO.
Pointer to memory mapped EVR register
base.
Pointer to structure to place event in.

0 – Event retrieved successfully-1 – Event FIFO was empty

Return value

int EvrEnableLogStopEvent(volatile struct MrfErRegs *pEr, int
enable);Description

Parameters

volatile struct MrfErRegs *pEr
int enable

Return value

Enable/disable stopping of writing to eventlog on reception of event codes with STOP
Log mapping bit set.
Pointer to memory mapped EVR registerbase.
0: disable stop log event
1: stop log writes upon reception of eventcodes with STOP log mapping bit set.
Returns zero when stop events disabled
Returns non-zero when stop events enabled

int EvrGetLogStopEvent(volatile struct MrfErRegs *pEr);
Description
Parameters
Return value

volatile struct MrfErRegs *pEr

Check if log stop events are enabled.
Pointer to memory mapped EVR register
base.
Returns zero when stop events disabled
Returns non-zero when stop events enabledMicro-Research Finland Oy
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int EvrEnableLog(volatile struct MrfErRegs *pEr, int enable);
Description
Parameters

volatile struct MrfErRegs *pEr
int enable

Return value

Enable/disable writing to log.
Pointer to memory mapped EVR registerbase.
0: disable writes to log
1: enable writes to log
Returns zero when log enabled
Returns non-zero when log stopped.

int EvrGetLogState(volatile struct MrfErRegs *pEr, int enable);
Description
Parameters

volatile struct MrfErRegs *pEr

Return value

Get log state.
Pointer to memory mapped EVR register
base.
Returns zero when logging enabled
Returns non-zero when logging stopped.

int EvrGetLogStart(volatile struct MrfErRegs *pEr);
Description
Parameters

volatile struct MrfErRegs *pEr

Return value

Get log start position.
Pointer to memory mapped EVR register
base.
Returns relative address to first log entry inlog ring buffer.

int EvrGetLogEntries(volatile struct MrfErRegs *pEr);
Description
Parameters

volatile struct MrfErRegs *pEr

Return value

Get number of entries in log.
Pointer to memory mapped EVR register
base.
Returns number of entries in log (0 to 512).

void EvrDumpFIFO(volatile struct MrfErRegs *pEr);
Description
Parameters

volatile struct MrfErRegs *pEr

Return value

Dump EVR FIFO on stdout.
Pointer to memory mapped EVR register
base.
None

int EvrClearLog(volatile struct MrfErRegs *pEr);
Description
Parameters

volatile struct MrfErRegs *pEr

Return value

Empty EVR Event Log.
Pointer to memory mapped EVR register
base.
None.

void EvrDumpLog(volatile struct MrfErRegs *pEr);
Description
Parameters
Return value

volatile struct MrfErRegs *pEr

Print out full EVR event log on stdout.
Pointer to memory mapped EVR register
base.
None

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int EvrSetPulseMap(volatile struct MrfErRegs *pEr, int ram, int code,
int trig, int set, int clear);
Description
Parameters

volatile struct MrfErRegs *pEr
int ramint code
int trig
int setint clear

Return value

Set up pulse generators for event codes.
Pointer to memory mapped EVR register
base.
Number of mapping RAM: 0 or 1
Event code affected
0: no change
1: Trigger pulse generator from event code
0: no change
1: Set pulse high with this event code
0: no change
1: Pull pulse low with this event code
None

int EvrClearPulseMap(volatile struct MrfErRegs *pEr, int ram, int
code, int trig, int set, int clear);
Description
Parameters

volatile struct MrfErRegs *pEr
int ramint code
int trig

int setint clear
Return value

Set up pulse generators for event codes.
Pointer to memory mapped EVR register
base.
Number of mapping RAM: 0 or 1
Event code affected
0: no change
1: Don’t trigger pulse generator from thisevent code
0: no change
1: Don’t set pulse high with this event code
0: no change
1: Don’t pull pulse low with this event code
None

int EvrSetPulseParams(volatile struct MrfErRegs *pEr, int pulse, int
presc, int delay, int width);
Description
Parameters

volatile struct MrfErRegs *pEr
int pulse
int presc
int delay
int width

Return value

Set pulse generator parameters.
Pointer to memory mapped EVR register
base.
Number of pulse generator 0-9
Prescaler value
Delay Value
Width Value
Returns 0 on success, -1 on error

void EvrDumpPulses(volatile struct MrfErRegs *pEr, int pulses);
Description
Parameters

volatile struct MrfErRegs *pEr

Dump EVR pulse generator settings.
Pointer to memory mapped EVR register

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int pulses
Return value

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base.
Number of pulse generators to dump
None

int EvrSetPulseProperties(volatile struct MrfErRegs *pEr, int pulse, int
polarity, int map_reset_ena, int map_set_ena, int map_trigger_ena,
int enable);
Description
Parameters

volatile struct MrfErRegs *pEr
int pulse
int polarity
int map_reset_ena
int map_set_ena
int map_trigger_ena
int enable

Return value

Set pulse generator properties.
Pointer to memory mapped EVR register
base.
Number of pulse generator 0-9
0: normal polarity
1: inverted polarity
0: disable reset input
1: enable reset input
0: disable set input
1: enable set input
0: disable trigger input
1: enable trigger input
0: pulse output disabled
1: pulse output enabled
Returns 0 on success, -1 on error

int EvrSetUnivOutMap(volatile struct MrfErRegs *pEr, int output, intmap);
Description
Parameters

volatile struct MrfErRegs *pEr
int output
int map

Return value

Set up universal output mappings.
Pointer to memory mapped EVR register
base.
Universal Output number
Signal mapping (see erapi.h for details)
Returns 0 on success, -1 on error

void EvrDumpUnivOutMap(volatile struct MrfErRegs *pEr, int
outputs);
Description
Parameters

volatile struct MrfErRegs *pEr
int outputs

Return value

Dump EVR Universal output mappings.
Pointer to memory mapped EVR register
base.
Number of outputs to dump
None

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int EvrSetFPOutMap(volatile struct MrfErRegs *pEr, int output, intmap);
Description
Parameters

volatile struct MrfErRegs *pEr
int output
int map

Return value

Set up front panel output mappings.
Pointer to memory mapped EVR register
base.
Front Panel Output number
Signal mapping (see erapi.h for details)
Returns 0 on success, -1 on error

void EvrDumpFPOutMap(volatile struct MrfErRegs *pEr, int outputs);
Description
Parameters

volatile struct MrfErRegs *pEr
int outputs

Return value

Dump EVR Front panel output mappings.
Pointer to memory mapped EVR register
base.
Number of outputs to dump
None

int EvrSetTBOutMap(volatile struct MrfErRegs *pEr, int output, intmap);
Description
Parameters

volatile struct MrfErRegs *pEr
int output
int map

Return value

Set up Transition board output mappings.
Pointer to memory mapped EVR register
base.
Transition Board Output number
Signal mapping (see erapi.h for details)
Returns 0 on success, -1 on error

void EvrDumpTBOutMap(volatile struct MrfErRegs *pEr, int outputs);
Description
Parameters

volatile struct MrfErRegs *pEr
int outputs

Return value

Dump EVR Transition board output
mappings.
Pointer to memory mapped EVR register
base.
Number of outputs to dump
Nonevoid EvrIrqAssignHandler(volatile struct MrfErRegs *pEr, int fd, void(*handler)(int));
Description
Parameters

volatile struct MrfErRegs *pEr
int fdvoid (*handler)(int)

Return value

Assign EVR interrupt handler.
Pointer to memory mapped EVR register
base.
File descriptor returned by EvrOpen
Pointer to interrupt handler function
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int EvrIrqEnable(volatile struct MrfErRegs *pEr, int mask);
Description
Parameters

volatile struct MrfErRegs *pEr
int mask

Return value

Enable EVR interrupts.
Pointer to memory mapped EVR register
base.
Interrupt mask (see erapi.h) for mask bits.
Returns mask read back from EVR.

int EvrGetIrqFlags(volatile struct MrfErRegs *pEr);
Description
Parameters

volatile struct MrfErRegs *pEr

Return value

Get EVR interrupt flags.
Pointer to memory mapped EVR register
base.
Returns EVR interrupt flags.

int EvrClearIrqFlags(volatile struct MrfErRegs *pEr, int mask);
Description
Parameters

volatile struct MrfErRegs *pEr
int mask

Return value

Clears EVR interrupt flags.
Pointer to memory mapped EVR register
base.
Interrupt clear mask (see erapi.h) for flag
bits.
Returns flags read back from EVR.

void EvrIrqHandled(int fd);
Description
Parameters

volatile struct MrfErRegs *pEr
int fdReturn value

Function to call at the end of interrupt
handler function.
Pointer to memory mapped EVR register
base.
File descriptor returned by EvrOpen
None

int EvrSetPulseIrqMap(volatile struct MrfErRegs *pEr, int map);
Description
Parameters

volatile struct MrfErRegs *pEr
int map

Return value

Set up interrupt mappings.
Pointer to memory mapped EVR registerbase.
Signal mapping (see erapi.h for details)
Returns 0 on success, -1 on error

int EvrUnivDlyEnable(volatile struct MrfErRegs *pEr, int dlymod, int
enable);Description
Parameters

volatile struct MrfErRegs *pEr

Enable/disable UNIV-LVPECL-DLY output.
Pointer to memory mapped EVR registerbase.

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int dlymod

int enable
Return value

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Number of UNIV-LVPECL-DLY module:
0 – module in slot #1 (UNIV0/1)
1 – module in slot #2 (UNIV2/3)
0 – disable module output
1 – enable module output
Returns 0 on success, -1 on error

int EvrUnivDlySetDelay(volatile struct MrfErRegs *pEr, int dlymod, int
dly0, int dly1);
Description
Parameters

volatile struct MrfErRegs *pEr
int dlymod

int dly0

int dly01

Return value

Enable/disable UNIV-LVPECL-DLY output.
Pointer to memory mapped EVR register
base.
Number of UNIV-LVPECL-DLY module:
0 – module in slot #1 (UNIV0/1)
1 – module in slot #2 (UNIV2/3)
Delay value for output 0/2:
0 – shortest delay
1023 – longest delay (approx. 9-10 ps/step)
Delay value for output 1/3:
0 – shortest delay
1023 – longest delay (approx. 9-10 ps/step)
Returns 0 on success, -1 on error

int EvrSetFracDiv(volatile struct MrfErRegs *pEr, int fracdiv);
Description
Parameters

volatile struct MrfErRegs *pEr
int fracdiv

Return value

Set fractional divider control word which
provides reference frequency for receiver.
Pointer to memory mapped EVR register
base.
Fractional divider control word
Returns control word written

int EvrGetFracDiv(volatile struct MrfErRegs *pEr);
Description
Parameters
Return value

volatile struct MrfErRegs *pEr

Get fractional divider control word which
provides reference frequency for receiver.
Pointer to memory mapped EVR register
base.
Returns control word

int EvrSetDBufMode(volatile struct MrfErRegs *pEr, int enable);
Description

Enable/disable data buffer mode. When data
buffer mode is enabled every other
distributed bus byte is reserved for datatransmission thus the distributed bus

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Parameters

volatile struct MrfErRegs *pEr
int enable

Return value

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bandwidth is halved.
Pointer to memory mapped EVR registerbase.
0 – disable data buffer mode
1 – enable data buffer mode
Data buffer status (see Receive Data Buffer
Control and Status Register on page 38 forbit definitions).

int EvrGetDBufStatus(volatile struct MrfErRegs *pEr);
Description

Parameters

volatile struct MrfErRegs *pEr

Return value

Get data buffer mode. When data buffer
mode is enabled every other distributed bus
byte is reserved for data transmission thus the
distributed bus bandwidth is halved.
Pointer to memory mapped EVR register
base.
Data buffer status (see Receive Data Buffer
Control and Status Register on page 38 forbit definitions).

int EvrReceiveDBuf(volatile struct MrfErRegs *pEr, int enable);
Description

Parameters

volatile struct MrfErRegs *pEr
int enable

Return value

Enable reception of data buffer. After
reception of a data buffer further reception isdisabled until re-enabled by software.
Pointer to memory mapped EVR registerbase.
0 – disable data buffer reception.
1 – enable data buffer reception
Data buffer status (see Receive Data Buffer
Control and Status Register on page 38 fordefinitions).

int EvrGetDBuf(volatile struct MrfErRegs *pEr, char *dbuf, int size);
Description
Parameters

volatile struct MrfErRegs *pEr
char *dbuf
int size

Return value

Receive data buffer data.
Pointer to memory mapped EVR register
base.
Pointer to local data buffer
Size of dbuf buffer.
Size of received buffer.
-1 on error (no buffer received, local buffer
too small or checksum error)

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int EvrSetTimestampDivider(volatile struct MrfErRegs *pEr, int div);
Description
Parameters

volatile struct MrfErRegs *pEr
int div

Return value

Set timestamp counter divider
Pointer to memory mapped EVR registerbase.
Timestamp divider value:0 – count timestamp events (or use DBUS4
as clock)
1 to 65535 – count at event clock/value rate
Return divider value.

int EvrSetTimestampDBus(volatile struct MrfErRegs *pEr, int enable);
Description
Parameters

volatile struct MrfErRegs *pEr
int enable

Control timestamp counter count from
distributed bus bit 4 (DBUS4).
Pointer to memory mapped EVR registerbase.
0 – disable counting from DBUS4
1 – enable timestamp counting from DBUS4.
Note: Timestamp counter has to be 0.

Return value

int EvrGetTimestampCounter(volatile struct MrfErRegs *pEr);
Description
Parameters

volatile struct MrfErRegs *pEr

Return value

Get Timestamp Counter value
Pointer to memory mapped EVR registerbase.
Timestamp Counter value

int EvrGetSecondsCounter(volatile struct MrfErRegs *pEr);
Description
Parameters

volatile struct MrfErRegs *pEr

Return value

Get Timestamp Seconds Counter value
Pointer to memory mapped EVR registerbase.
Timestamp Seconds Counter value

int EvrGetTimestampLatch(volatile struct MrfErRegs *pEr);
Description
Parameters

volatile struct MrfErRegs *pEr

Return value

Get Timestamp Latch value
Pointer to memory mapped EVR registerbase.
Timestamp Latch value

int EvrGetSecondsLatch(volatile struct MrfErRegs *pEr);
Description
Parameters

volatile struct MrfErRegs *pEr

Get Timestamp Seconds Latch value
Pointer to memory mapped EVR register

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base.
Timestamp Seconds Latch value

Return value

int EvrSetPrescaler(volatile struct MrfErRegs *pEr, int presc, int div);
Description
Parameters

volatile struct MrfErRegs *pEr
int presc
int div

Return value

Set prescaler divider
Pointer to memory mapped EVR register
base.
Number of prescaler
Prescaler divider value:
1 to 65535 – count at event clock/value rate
Return divider value.

int EvrSetExtEvent(volatile struct MrfErRegs *pEr, int ttlin, int code,
int edge_enable, int level_enable);
Description
Parameters

volatile struct MrfErRegs *pEr
int ttlin
int code
int edge_enable
int level_enable

Return value

Set external event code
Pointer to memory mapped EVR register
base.
Number of front panel input: 0, 1
Event code to generate on detected edge/level0 – disable
1 – enable events on active edge
0 – disable
1 – enable sending out event every 1 us on
active level0 – successful-1 – error

int EvrSetBackEvent(volatile struct MrfErRegs *pEr, int ttlin, int code,
int edge_enable, int level_enable);
Description
Parameters

volatile struct MrfErRegs *pEr
int ttlin
int code
int edge_enable
int level_enable

Return value

Set backwards event code
Pointer to memory mapped EVR register
base.
Number of front panel input: 0, 1
Event code to send out on detected edge/level0 – disable
1 – enable events on active edge
0 – disable
1 – enable sending out event every 1 us on
active level0 – successful-1 – error

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int EvrSetExtEdgeSensitivity(volatile struct MrfErRegs *pEr, int ttlin,
int edge);
Description
Parameters

volatile struct MrfErRegs *pEr
int ttlin
int edge

Return value

Set external input edge sensitivity
Pointer to memory mapped EVR register
base.
Number of front panel input: 0, 1
0 – detect rising edges
1 – detect falling edges
0 – successful-1 – error

int EvrSetExtLevelSensitivity(volatile struct MrfErRegs *pEr, int ttlin,
int level);
Description
Parameters

volatile struct MrfErRegs *pEr
int ttlin
int level

Return value

Set external input edge sensitivity
Pointer to memory mapped EVR register
base.
Number of front panel input: 0, 1
0 – detect high level (active high)1 – detect low level (active low)
0 – successful-1 – error

int EvrSetTxDBufMode(volatile struct MrfErRegs *pEr, int enable);
Description

Parameters

volatile struct MrfErRegs *pEr
int enable

Return value

Enable/disable transmitter data buffer mode.
When data buffer mode is enabled every
other distributed bus byte is reserved for datatransmission thus the distributed bus
bandwidth is halved.
Pointer to memory mapped EVR registerbase.
0 – disable transmitter data buffer mode
1 – enable transmitter data buffer mode
Transmit data buffer status (see Transmit
Data Buffer Control Register on page 38 forbit definitions).

int EvrGetTxDBufStatus(volatile struct MrfErRegs *pEr);
Description

Parameters
Return value

volatile struct MrfErRegs *pEr

Get transmit data buffer status. When data
buffer mode is enabled every other
distributed bus byte is reserved for datatransmission thus the distributed bus
bandwidth is halved.
Pointer to memory mapped EVR register
base.
Transmit data buffer status (see Transmit
Data Buffer Control Register on page 38 forMicro-Research Finland Oy
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bit definitions).

int EvrSendTxDBuf(volatile struct MrfErRegs *pEr, char *dbuf, intsize);
Description

Parameters

volatile struct MrfErRegs *pEr
char *dbuf
int size

Return value

Get transmit data buffer status. When data
buffer mode is enabled every other
distributed bus byte is reserved for datatransmission thus the distributed bus
bandwidth is halved.
Pointer to memory mapped EVR register
base.
Pointer to local data buffer
Size of data in bytes to be transmitted:
4, 8, 12, …, 2048.
Size of buffer being sent.
-1 on error.

int EvrGetFormFactor(volatile struct MrfErRegs *pEr);
Description
Parameters
Return value

volatile struct MrfErRegs *pEr

Get form factor code from EVR.
Pointer to memory mapped EVR register
base.
Form factor. See FPGA Firmware Version
Register on page 39 for details.