Study of Reliable Timing System at
KEK Accelerator Complex

Author:
Di Wang

Supervisor:
Prof. Furukawa Kazuro

Doctor of Philosophy

Department of Accelerator Science
School of High Energy Accelerator Science
The Graduate University for Advanced Studies, SOKENDAI

September 2021

Declaration of Authorship
I, Di Wang, declare that this thesis titled, ’Study of Reliable Timing System at KEK
Accelerator Complex’ and the work presented in it are my own. I confirm that:This work was done wholly or mainly while in candidature for a research degree
at this University.



Where any part of this thesis has previously been submitted for a degree or any
other qualification at this University or any other institution, this has been clearlystated.

Where I have consulted the published work of others, this is always clearly attributed.



Where I have quoted from the work of others, the source is always given. With
the exception of such quotations, this thesis is entirely my own work.



I have acknowledged all main sources of help.

Where the thesis is based on work done by myself jointly with others, I have madeclear exactly what was done by others and what I have contributed myself.

Signed: Di Wang

Date: June, 2021

ii

A dissertation submitted to Department of Accelerator Science,
School of High Energy Accelerator Science,
The Graduate University for Advanced Studies, SOKENDAI,
in partial fulfillment of the requirements for the degree ofDoctor of Philosophy

Advisory Committee
1. Prof.Obina Takashi

KEK,

2. Prof.Kamikubota Norihiko

KEK

3. Assoc.Prof.Kobayashi Tetsuya

KEK

4. Assoc.Prof.Satoh Masanori

KEK

5. Prof.Furukawa Kazuro

KEK

6. Prof.Masuda Takemasa

Japan Synchrotron Radiation ResearchInstituteTHE GRADUATE UNIVERSITY FOR ADVANCED STUDIES, SOKENDAI

Abstract
School of High Energy Accelerator Science
Department of Accelerator Science
Doctor of Philosophy
Study of Reliable Timing System at KEK Accelerator Complex
by Di Wang

The timing system provides high-precision signals to control a variety of hardware andsoftware in the accelerator complex. At KEK, the timing system at injector linear
accelerator (LINAC) is responsible for RF frequency synchronization between two SuperKEKB main rings (MR) and LINAC, trigger delivery, and bucket selection process. The LINAC timing system also provides trigger signals for two light source rings(PF/PF-AR) simultaneously, which demanding the timing system handle the injection
procedure for 4 rings at 50 Hz. The beam properties and device control parameters are
modulated every pulse through the timing system.
The event-based timing system generates event codes in an event generator (EVG) anddistributes these event codes in a scheduled delay time to all local event receivers (EVR).
The EVR module equips with the pulse generation circuit with variable pulse delay andwidth to supply trigger signals for hardware upon receiving the desired event code.
Several constraints from hardware must be considered during the design of the timing
system. Some devices, like pulsed magnet power supply, need to be triggered at thesame phase of the 50 Hz AC (AC50) power line to maintain a stable operation. Thus,
the timing system operates under the AC50-dependent mode. On the other hand, thehigh-power klystron modulator needs at least 18 ms to accumulate power for klystron
which results in a trigger interval restriction for consecutive injection pulse. The bucket
selection cycle (BSC) is defined as a period that can select all the RF buckets inside
a ring. The BSC for SuperKEKB electron beam injection is 493 µs which is effortless
to synchronize with AC50 in 50 Hz. However, a newly constructed positron damping
ring (DR) to lower the positron beam emittance enlarges the bucket selection period
for a whole DR-MR cycle. The RF bucket number for DR and MR are 230 and 5120,
respectively. The BSC for SuperKEKB positron beam injection becomes 23 times longer

iii(i.e., 11.34 ms) due to DR operation and the synchronization between BSC and AC50
in every pulse is broken. The AC line always fluctuates due to requirements from thepower company. Consequently, a method called “sequence shift” is implemented tosynchronize with both AC50 and BSC for positron as well as compensating for the ACline fluctuation. The length of the sequence and how the sequence shift is accomplished
are described in detail.
Apart from the triggering function of a timing system, several significant features arealso utilized to either meet the hardware requirement or improve the functionality ofthe timing system. The beam gate system provides a highly flexible way to disable thetrigger delivery to specific devices, such as electron guns or DR injection and extraction
magnet, without stopping the operation of EVG. The data buffer component contributes
to the auxiliary data delivery, like beam mode, pulse ID, or bucket number information,other than normal trigger signal delivery.
Another limit of the numbers of selectable MR RF buckets for the 2-bunch and 2-pulse
operation comes from the rising time of the DR kicker magnet field. To overcome thisdisadvantage, the RF phase in the downstream LINAC is modulated every pulse toincrease the coincidence opportunity between DR RF and LINAC RF. The RF phaseshift also brings time discrepancy of nanosecond scale between timing trigger and beam
trigger. The beam behavior under such discrepancy is investigated to assure that thebeam quality variation is acceptable for the SuperKEKB physics run. By means of thepulse-to-pulse RF phase modulation, all MR RF buckets can be selected in one pulse
even during 2-bunch and 2-pulse operations.
The effort of establishing a reliable timing system at LINAC and several solutions toimprove the system’s robustness are presented in this work. During the commissioning ofSuperKEKB, the beam error originates from the timing system was observed. This work
mainly focuses on the failure mode analysis of the timing system at LINAC. We follow
the procedure of failure mode analysis to understand the failure mode, identify the failurecause, and propose solutions. Several log systems for quickly diagnosing the complex
system are built and tested. With the help of the log system, two failure modes called“beam mode replacement” and “redundant beam mode” are comprehensively analyzed
and their failure causes are identified. The error can be categorized into two parts, thesystematic error caused by either software bug or problematic system design, and theunexpected error caused by strong AC50 drift.
Several possibilities for solutions are discussed in this work. One solution is to remove
the AC50 trigger dependency. A beam experiment is done by examining the beam quality degradation under the AC50-independent mode. According to the beam experiment,
the AC50-independent operation is acceptable for SuperKEKB MR whereas not feasible

iv
for PF injection due to the strong relationship between the power supply of the PF
injection kicker magnet and AC50. Partially AC50-dependent operation mode is proposed by switching between the AC50-independent mode and AC50-dependent mode.
Consequently, an AC50 regulator module is installed in the timing system to mask thestrong AC50 drift and provide signals within 50±0.1 Hz to stabilize the timing system.
A detailed analysis of the process logic and performance of the AC50 regulator module
is represented in this thesis. Another possibility is to decrease the sequence length tomitigate the AC50 drift effect. The DR storage time becomes significant because both
DR injection and extraction timing need to synchronize with AC50. The injection timing and extraction timing are strongly related without downstream LINAC RF phaseshift. Thus, either decreasing the DR storage time or decoupling the DR injection andextraction pulse will allow us to shorten the sequence length. An improvement of thesequence shift algorithm is also necessary to handle some extremely strong AC50 drift
situations. An example is given to illustrate how the sequence shift with considering
recent AC drift value can increase the stability of the timing system.

Acknowledgements
Many talented and amiable people shared their knowledge and helped form my thinking in this thesis. First and foremost, I want to thank my esteemed supervisors, Dr.
Kazuro Furukawa and Dr. Masanori Satoh, who patiently gave me advices and recommendations to pursue interesting and significant problems in my area. The classes
they taught provide not only invaluable insight of the historical evolution of accelerator
control system but also the philosophy of phronesis on practical obstacle.
I am deeply grateful to Dr. Hiroshi Kaji, Dr. Hitoshi Sugimura, Dr. Fusashi Miyahara and Dr. Yoshinori Enomoto for their insightful comments and suggestions at
every stage of the research project.
I would like to offer my special thanks to Dr. Tetsuo Shidara, Dr. Hiroyasu Ego, Dr.
Takuya Natsui and Dr. Takako Miura for their kindly help on detailed explanationand test bench construction during my klystron experiment.
I have also benefitted from conversations with Mr. Yuichi Iitsuka, Mr. Takuya Kudou,
Mr. Shiro Kusano, Mr. Hideki Saotome and many other staffs during the software
programming and hardware debugging.
My leisure life in Japan becomes pleasing, satisfactory and cheerful with the help of mycolleagues, Dr. Baiting Du, Dr. Na Liu, Dr. M.A. Rehman, Mrs. Min Yang, Mr. Ce
Zhang, Mr. Yao Lu and Mr. Yuki Abe.
Last but not least, I want to thank all the open knowledge organizations, such as the
Wikimedia Foundation and the Free Software Foundation, whose principles and methodologies are knowledge acquirement is a basic human-rights. What they pursue inspires
me to insist on the belief of the existence of common good for all human.

v

Contents
Declaration of Authorshipii

Abstractii

Acknowledgementsv

Contents

vii

List of Figuresxi

List of Tables

xv

Abbreviations

xvii

1 Introduction
1.1 Accelerator Complex at KEK . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 EPICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Reliability Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Motivation of this study . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Structure of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1
1
3
5
7
8

2 Accelerator Timing System
11
2.1 RF Synchronization and Bucket Selection . . . . . . . . . . . . . . . . . . 11
2.2 Classification of Timing System . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 Fast Timing and Slow Timing . . . . . . . . . . . . . . . . . . . . . 15
2.2.2 Analogue Timing and Digital Timing . . . . . . . . . . . . . . . . 16
2.2.3 Event-based Timing and Timestamp-based Timing . . . . . . . . . 18
2.3 EBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.1 RF Clock and Event Clock . . . . . . . . . . . . . . . . . . . . . . 20
2.3.2 Event Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.3 AC Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.4 Event Codes Generation . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.5 Timestamp Synchronization . . . . . . . . . . . . . . . . . . . . . . 22
2.3.6 Event Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4 TBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5 Examples of Accelerator Timing system . . . . . . . . . . . . . . . . . . . 25
vii

Contents
2.5.1
2.5.2

viii
BEPC II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SLS Timing System . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3 Overview of Timing System at KEK LINAC
29
3.1 Hardware and Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.1 Event Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.2 MTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.3 TDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.4 RFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2 RF Synchronization at LINAC . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3 Bucket Selection for SuperKEKB . . . . . . . . . . . . . . . . . . . . . . . 38
3.3.1 Delay Calculation of RF Buckets . . . . . . . . . . . . . . . . . . . 38
3.3.2 Decision Making of Injection Bucket . . . . . . . . . . . . . . . . . 41
3.3.3 Constituents of Bucket Selection System . . . . . . . . . . . . . . . 44
3.4 Beam Gate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4 Requirement of Timing System at KEK LINAC
47
4.1 PPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.1.1 Simultaneous Injection . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1.2 Beam Mode and Injection Pattern . . . . . . . . . . . . . . . . . . 49
4.1.3 Dependency between Pulses . . . . . . . . . . . . . . . . . . . . . . 52
4.2 AC50 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3 DR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.1 Dependency between Injection and Extraction Pulse . . . . . . . . 55
4.3.2 DR Storage Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3.3 2-bunch and 2-pulse operation . . . . . . . . . . . . . . . . . . . . 57
5 Implementation of Timing System at KEK LINAC
63
5.1 Sequence Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.1.1 8/9 Pulses Sequence Shift . . . . . . . . . . . . . . . . . . . . . . . 64
5.1.2 Sequence Shift Algorithm . . . . . . . . . . . . . . . . . . . . . . . 65
5.1.3 16/18 Pulses Sequence Shift . . . . . . . . . . . . . . . . . . . . . . 68
5.2 Structure of Main Timing Station . . . . . . . . . . . . . . . . . . . . . . . 69
5.3 RF Phase Shift of LINAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.1 Implementation of RF Phase Shift . . . . . . . . . . . . . . . . . . 71
5.3.2 Balance of DR Bucket Selection . . . . . . . . . . . . . . . . . . . . 75
6 Reliability Analysis of Timing System
79
6.1 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2 Data and Information Acquisition . . . . . . . . . . . . . . . . . . . . . . . 81
6.2.1 Event Code Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.2.2 AC50 Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3 Failure Mode of Timing System . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.1 Beam Mode Replacement . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.2 Redundant Beam Mode . . . . . . . . . . . . . . . . . . . . . . . . 86
6.4 Failure Mechanism and Failure Cause . . . . . . . . . . . . . . . . . . . . 87
6.4.1 AC50 Drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.4.2 Injection Pattern Switch . . . . . . . . . . . . . . . . . . . . . . . . 89

Contents
6.5

ix

Reliability Requirements Evaluation . . . . . . . . . . . . . . . . . . . . . 91

7 Reliability Improvement and Future Prospects
95
7.1 Reliability Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.1.1 AC50 Independent Operation . . . . . . . . . . . . . . . . . . . . . 95
7.1.2 Partially AC50 Independent Operation . . . . . . . . . . . . . . . . 98
7.1.3 Performance of AC50 regulator . . . . . . . . . . . . . . . . . . . . 99
7.1.4 Improvement for sequence shift . . . . . . . . . . . . . . . . . . . . 100
7.2 Future prospects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.2.1 Log Data Synchronization . . . . . . . . . . . . . . . . . . . . . . . 103
7.2.2 Smooth Pattern Switch . . . . . . . . . . . . . . . . . . . . . . . . 104
8 Conclusion

107

A Source Code111
A.1 DR Buckets for 2-bunch and 2-pulse . . . . . . . . . . . . . . . . . . . . . 111
A.2 Available DR buckets for RF Phase Shift . . . . . . . . . . . . . . . . . . . 112
A.3 Sequence Shift Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Bibliography

117

List of Figures
1.1
1.2

Overview of the LINAC, SuperKEKB and PF/PF-AR. . . . . . . . . . . .
Schematic layout of 600-m injector LINAC. . . . . . . . . . . . . . . . . .

1
2

Timing sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The injection opportunity is decided by fLI−RF and fM R−RF . . . . . . . .
The 50 Hz timing trigger signal (up) and 571.2 MHz clock signal (down)
were generated at the LINAC main timing station and distributed to theremote stations through coaxial cable in the KEKB project era [1]. . . . .
2.4 EBTS for APS. Two event generators are cascaded and transmit eventcodes as well as periodic timestamp events to an array of event receivers
through fiber optic links. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 A typical layout of event timing system. . . . . . . . . . . . . . . . . . . .
2.6 The event stream consist of a combination of 8-bit event codes and data
sent out at the event clock. . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Sub-components inside the MRF EVG. . . . . . . . . . . . . . . . . . . . .
2.8 Timestamp synchronization logic. . . . . . . . . . . . . . . . . . . . . . . .
2.9 IEEE 1588 synchronisation mechanism and delay calculation. . . . . . . .
2.10 Layout of SLS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12
13

2.1
2.2
2.3

16

20
20
21
22
23
24
26

3.1 Layout of timing stations at LINAC [2]. . . . . . . . . . . . . . . . . . . . 30
3.2 Event modules installed at MTS. . . . . . . . . . . . . . . . . . . . . . . . 31
3.3 Schematic view of MR Sub-timing Station. . . . . . . . . . . . . . . . . . 32
3.4 MTG module (right) in a NIM crate. . . . . . . . . . . . . . . . . . . . . . 33
3.5 TDC module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.6 Reflective memory module (VME-5565). . . . . . . . . . . . . . . . . . . . 35
3.7 ACC-5595 Reflective Memory Hub. . . . . . . . . . . . . . . . . . . . . . . 36
3.8 Block diagram of synchronization system for LINAC, DR, and MR. . . . . 37
3.9 Bucket selection for DR and LER. . . . . . . . . . . . . . . . . . . . . . . 39
3.10 Delay calculation for DR and LER. . . . . . . . . . . . . . . . . . . . . . . 40
3.11 An example of fill pattern in LER during KEKB era. . . . . . . . . . . . . 41
3.12 Fill pattern during SuperKEKB era for HER. . . . . . . . . . . . . . . . . 42
3.13 Bucket selection fill mode of “star” type. . . . . . . . . . . . . . . . . . . . 43
3.14 Bucket selection system with three functional nodes and one monitor node. 45
4.1
4.2
4.3
4.4
4.5

Injection pattern, sequence, beam mode, and event codes. . . . . . . . . .
PPM operation for 4 (+1) rings at LINAC [3]. . . . . . . . . . . . . . . .
The GUI of IP-GEN program. . . . . . . . . . . . . . . . . . . . . . . . . .
The repetition rate of beam modes in IP-GEN program. . . . . . . . . . .
Schematic view of pre-trigger generation. . . . . . . . . . . . . . . . . . .
xi

48
48
50
51
52

List of Figures
4.6
4.7

Charging time of PFN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization between AC50 and BSC for LER cannot be achieved
every pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Time difference between DR extraction trigger and AC50. . . . . . . . . .
4.9 DR kicker magnets are active due to the power supply rising and falling
time of 100 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 DR operation with 2-bunch and 1-pulse injection. . . . . . . . . . . . . . .
4.11 DR operation with 2-bunch and 2-pulse injection. . . . . . . . . . . . . . .
4.12 The 2 ms injection windows comes together with 2-bunch and 2-pulse
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xii
54
55
57
58
59
59
60

5.1 Time difference between BSC and 50 Hz. . . . . . . . . . . . . . . . . . .
5.2 AC50 position manipulation by sequence shift. . . . . . . . . . . . . . . .
5.3 Logic of sequence shift. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 The schematic view of the sequence shift. . . . . . . . . . . . . . . . . . .
5.5 Example of sequence shift under two kinds of AC50 frequencies. . . . . . .
5.6 The conflict between 8/9 pulses sequence and DR storage time. . . . . . .
5.7 Schematic view of MTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8 Sequence of 3 important triggers happening in one MTS pulse. . . . . . .
5.9 RF phase shift of downstream LINAC. . . . . . . . . . . . . . . . . . . . .
5.10 Schematic view of RF phase shift in downstream LINAC. . . . . . . . . .
5.11 Equivalent view of BSC cycle shift by RF phase shift. . . . . . . . . . . .
5.12 Calculation process of new DR bucket under RF phase shift. . . . . . . .
5.13 Optional DR buckets numbers. . . . . . . . . . . . . . . . . . . . . . . . .

64
65
66
66
68
69
69
71
72
72
73
74
75

6.1 Timing system requirements. . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Two EVRs are used for event code log. . . . . . . . . . . . . . . . . . . . .
6.3 Architecture of CA-based event code log system. . . . . . . . . . . . . . .
6.4 VxWorks task delay information. . . . . . . . . . . . . . . . . . . . . . . .
6.5 Histogram of AC50 drift value in 24 hours. . . . . . . . . . . . . . . . . .
6.6 AC50 drift value in ∼5 minutes. . . . . . . . . . . . . . . . . . . . . . . .
6.7 Failure mode of beam mode replacement. . . . . . . . . . . . . . . . . . .
6.8 Failure mode of beam mode redundancy. . . . . . . . . . . . . . . . . . . .
6.9 AC50 drifts mildly in 24 h. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 AC50 drifts strongly in 24 h. . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 Drift of AC50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 The relation between time to failure and of extend of AC50 drift for 16/18
pulses sequence shift. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 8/9 pulses sequence shift method is able to handle lager AC50 drift value.
6.14 Injection pattern switch error caused by DR operation. . . . . . . . . . . .
6.15 Counts of large AC50 drift from June, 2019 to April, 2021. . . . . . . . .
6.16 Maximal AC50 drift value in a day from June, 2019 to April, 2021. . . . .

79
81
82
83
84
84
85
86
87
87
88
89
90
90
92
92

7.1
7.2
7.3
7.4
7.5

96
97
97
98
99

Change of energy jitter at the beam transport line of LINAC. . . . . . . .
Relation between klystron output and AC50 arrival timing. . . . . . . . .
Schematic diagram of AC50 regulator module. . . . . . . . . . . . . . . .
Schematic diagram of AC50 regulator module. . . . . . . . . . . . . . . .
Comparison of AC50 regulator and MTG output. . . . . . . . . . . . . . .

List of Figures
7.6
7.7

xiii

Resynchronization to AC50 after strong AC50 fluctuation stops. . . . . . 100
Comparison of AC50 arrival timing between 16/18-pulse sequence and8/9-pulse sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.8 Extremely strong AC50 drift recorded by TDC. . . . . . . . . . . . . . . . 101
7.9 16/18-pulse sequence shift data measured by TDC. . . . . . . . . . . . . . 102
7.10 Simulation of 8/9 pulse sequence shift. . . . . . . . . . . . . . . . . . . . . 102
7.11 Simulation of 8/9 pulse sequence shift with considering the AC drift. . . . 103
7.12 Abort Trigger System log displayed in Grafana. . . . . . . . . . . . . . . . 103
7.13 Injection pattern switch times in November, 2020. . . . . . . . . . . . . . 104

List of Tables
2.1
2.2
2.3

Special event codes for MRF EBTS. . . . . . . . . . . . . . . . . . . . . . 23
Timing system parameters of BEPC II . . . . . . . . . . . . . . . . . . . . 26
Timing system parameters of the Swiss Light Source. . . . . . . . . . . . . 27

3.1
3.2
3.3
3.4
3.5

Specifications of MRF and SINAP VME event modules used for MR-STS.
Integer relation of RF frequencies at KEK LINAC . . . . . . . . . . . . .
Bucket selection frequencies at KEK LINAC . . . . . . . . . . . . . . . . .
The relation between injection opportunity and bucket number. . . . . . .
Summary of beam gate signals. . . . . . . . . . . . . . . . . . . . . . . . .

4.1
4.2
4.3
4.4
4.5
4.6

Beam properties of 5 rings. . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Beam modes and event codes defined at KEK LINAC. . . . . . . . . . . . 50
DR operation modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DR storage time is affected by KBP mode repetition rate and 2-pulse mode. 57
Injection delay and corresponding DR bucket for LER bucket “#0”. . . . 60
Available RF buckets for DR operation. . . . . . . . . . . . . . . . . . . . 61

5.1
5.2
5.3
5.4

The time interval between 50 Hz pulse and 44.1 Hz pulse. . . . . . . . . .
Two kinds of sequence type. . . . . . . . . . . . . . . . . . . . . . . . . . .
RF bucket offset, event clock offset and ∆T for different RF phase shift
type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optional DR buckets for different RF phase shift type. . . . . . . . . . . .

6.1

Analysis of the decision making of the sequence shift. . . . . . . . . . . . . 88

7.1

Tagged data for different log systems. . . . . . . . . . . . . . . . . . . . . 104

xv

32
37
38
40
46

64
65
77
78

Abbreviations
HER

High Energy Ring

LER

Low Energy Ring

MR

Main RingDR

Damping Ring

RF

Radio frequency

FC

Flux Concentrator

EPICS

Experimental Ehysics and Industrial Control System

OPI

Operator Interface

IOC

Input/Output Controller

CA

Channel AccessDB

Database

BRR

Beam Repetition Rate

EBTS

Event-based Timing System

TBTS

Timestamp-based timing system

MRF

Micro-Research Finland

EVG

Event Generator

EVR

Event Receiver

DBus

Distrubuted Bus

WRWhite Rabbit

TDC

Time-to-Digital Converter

MTG

Master Trigger Generator

RFM

reflective Memory

MTS

Main Timing Station

MO

Master Oscillator

MMO

Main Master OscillatorxviiAbbreviations

xviii

SHB

Subharmonic Buncher

BSC

Bucket Selection Cycle

BCE

Bunch Current Equalizer

BCM

Bunch Current Monitor

CCB

Central Control Building

PPM

Pulse-to-pulse Modulation

IP-GEN

Injection Pattern Generator

Chapter1
Introduction
1.1

Accelerator Complex at KEKe-LER
SuperKEKB

e+

HER

7 GeV

LER

4 GeV

DR

1.1 GeVPF-AR

6.5 GeVPF

2.5 GeV

PF-AR
HER
PF e+ Damping Ring

Figure 1.1: Overview of the LINAC, SuperKEKB and PF/PF-AR.

The accelerator complex at KEK consists of an injector linear accelerator (LINAC), an
electron/positron double-ring collider SuperKEKB, and two synchrotron light source
facilities (PF and PF-AR). The SuperKEKB is an upgrade project of KEKB which
operated at KEK from 1998 to 2010 and achieved the world-highest peak luminosityof 2.018 × 1034 cm−2 s−1 . SuperKEKB is designed to aim at peak luminosity of 8 ×1

Chapter 1. Introduction
1035 cm−2 s−1 which is 40 times higher than the KEKB [4]. The beams which are stored
in two main rings (MRs), a 7 GeV high energy electron ring (HER) and a 4 GeV low
energy positron ring (LER), collide at the interaction point and are detected by the BelleII detector. The physics goal of the Belle II experiment is to search for new physics inthe flavor sector at the luminosity frontier. A low-emittance beam is indispensable toimplement the nano-beam scheme for higher SuperKEKB collision efficiency. Apartfrom supplying beams for the SuperKEKB collider the LINAC also provides beams for
two light source facilities, 2.5 GeV Photon Factory (PF) and 6.5 GeV Photon Factory
Advanced Ring (PF-AR) [5, 6]. The schematic view of the accelerator complex is shownin Fig. 1.1.

Figure 1.2: Schematic layout of 600-m injector LINAC.

A schematic layout of LINAC is shown in Fig. 1.2. The 600-m LINAC is composedof 60 high-power radio frequency (RF) accelerating units distributed at eight sectors(sector A-C and 1-5). The requirements for the LINAC are full energy injection into
the SuperKEKB rings with an energy spread of 0.1%. A photo-cathode high-current
RF gun generates a high-charge electron bunch (up to 4 nC) into the SuperKEKB highenergy ring (HER) while the thermionic gun is adopted for generating electron beams
for PF, PF-AR, as well as for positron beam generation. The low-emittance and highcurrent positron beam is generated by a positron target located between sector “2” andsector “3”. After a flux concentrator (FC) and large-aperture accelerating structures, thebeam is then transferred by a beam switchyard and damped to low emittance through adamping ring (DR). Finally, the positron beam re-enters LINAC and is accelerated up
to 4 GeV.
The LINAC RF system converts the high voltage pulses from the modulator into pulsed
RF power and sends them to the accelerating units to set up an electric field which isused for charged particle acceleration. The bunches inside MRs perform a longitudinal
2

EPICS
synchrotron oscillation and are contained inside a stable area called an RF bucket. The
number of MR RF buckets is determined by the RF frequency and circumference of
MR. The bunch will gradually become lost if the injection timing cannot match thesynchronous phase between the LINAC and MR. To equalize the bunch distribution inside the ring as well as avoid strong coupled-bunch instabilities, the injection RF bucket
should be selected based on the timing system. This procedure is called bucket selection. The bucket selection is one of the main tasks of the accelerator timing system. In
addition, the timing system controls the injection by synchronizing all the relevant components to operate at a scheduled sequence. For example, the timing system provides
trigger signals for the low-level and high-power RF systems, pulsed magnets, electron
guns, injection systems, and beam instrumentation at LINAC. A precise RF synchronization should be provided to allow particles to pass between accelerators. To satisfy theflexibility requirements of series accelerators, a strategy called pulse-to-pulse modulation(PPM) was proposed at CERN to achieve the control of a time-shared injection [7]. Asa multi-accelerator facility, the PPM is imperative to avoid accelerator dead-time andthis method is also implemented at the KEK accelerator complex to modulate the beam
properties for SuperKEKB, PF, and PF-AR. The modulated items include the beammode, bucket number, RF phase in LINAC, and many other control parameters.

1.2

EPICS

The operation of particle accelerators requires high-performance electronics for beamdiagnostics, data acquisition, and machine control. These electronics should integratewith several control subsystems to consist of a common architecture. Consequently,
the Experimental Physics and Industrial Control System (EPICS) is employed as ade-facto standard in the community of accelerator control system. EPICS is a generalpurpose control system framework that is maintained by an international joint development project called EPICS collaboration. Before the 1990s, the accelerator control
system is usually accelerator-specific. Many home-grown controllers, cables as well as
various data transmission protocols are utilized at different institutes. Thus, it is difficult to share common-used components among institutes via collaboration. To increase
the high availability, scalability, and flexibility, EPICS was initially developed by Los
Alamos National Laboratory (LANL) and Argonne National Laboratory (ANL) for the3Chapter 1. Introduction
construction of control systems in 1987 [8]. Owing to its high-reliable, powerful, anddistributed attributes, EPICS now is chosen at many institutes all over the world, such
as SLAC, BNL, FNAL, DESY, PSI, and KEK [9].
The basic components of EPICS consist of Operator Interface (OPI), Input/Output
Controller (IOC), and LAN (Local Area Network). EPICS is based on the multi-layerarchitecture, in which the lower layer is responsible for the I/O with different piecesof hardware, and the upper layer is designed to provide hardware-independent services
to the OPI layer. EPICS uses Client/Server techniques to communicate between OPI
and IOC through an Ethernet-based network. From a software architecture perspective,
EPICS IOC consists of the followings:• EPICS base, the core software of EPICS which includes the application programming interface (API), EPICS database access, standard EPICS record support anddevice support, several tools for building EPICS application and EPICS extensions.
The base is normally provided by EPICS collaboration.
• EPICS application, which usually includes EPICS IOC, a user-defined EPICS
database to control the hardware components, a Channel Access (CA) server which
provides remote control through TCP/IP network. The application is used tocontrol dedicated hardware.
• EPICS extension, which includes function-enhancement applications not included in EPICS base, such as the EPICS sequencer, AutoSave, and procServer.
The extensions are developed by worldwide institutes and shared via collaboration.

Accelerator components such as magnet, vacuum, are controlled by IOC database (DB),which is unlike a relational database. IOC DBs are instances of different data structures
called EPICS records and each record type has one or more associated sets of record
support routines. Each record has its record type and dedicated behavior. The fieldof the record is the basic unit for EPICS DB. One of the most important fields is the“VAL” field, which typically holds the data for device input/output or some intermediate
calculation results. Records can communicate with each other through a reference linkcalled DB link or through CA link [10]. For example, when writing a value to the “VAL”
field of analog output (“ao”) record, it performs the engineering unit convert and then4Reliability Engineering
calls the correspondent device-specific support routine to perform the I/O with thedevice. Then it can trigger the process of another analog input (“ai”) record to set thereadback value into the “VAL” field to check whether the command is executed.
A channel-based data exchange protocol called CA serves as the communication protocol
between IOC and OPI. One channel corresponds to a combination of record name andfield name like “record name.field name”. The IOC DB information is published toclients using the CA network protocol. The basic actions of CA are “Get”, “Put”, and“Monitor”, which allow the client to read, write and monitor the data inside one IOC.

1.3

Reliability Engineering

Several conceptions should be clarified and defined before further discussion on a reliabletiming system. From the perspective of reliability engineering, reliability is the abilityof a system or component to perform as designed, which means without failure, in an
operational environment for a specified period [11]. The term “perform as designed”
means the system is supposed to meet system requirements. The system requirements
can be derived from different subjects,• Function requirements care about what a system is supposed to do.
• Performance requirements concern the efficiency (i.e., time consumed) of a system.
• Physical requirements relate to the physical entity such as size and weight of thedevices as well mechanical and electrical characteristics.
• Safety requirements focus on the protection of human life and machine while thesystem is under operational.

The reliability of a timing system mainly concerns function requirements and performance requirements while physical requirements and safety requirements are implicitin the personnel protection system (PPS) and machine protection system (MPS) [12].
The functional requirements of a timing system regulate whether the timing system realizes three basic functionalities which include RF synchronization, trigger delivery, andbucket selection. The performance requirements examine the precision and accuracy oftrigger signals as well as the response delay of the system.
5

Chapter 1. Introduction
According to the definition of reliability, the reliability requirements are distinct fromthe system requirements which not only refer to the system requirements but also careabout the operating conditions and period during normal operation. The reliability
requirements do not force the system to operate under any circumstance or function
well forever. On the contrary, the reliability requirements only need to satisfy certain
conditions and in a fixed period. For example, the timing system at KEK LINAC does
not guarantee a stable operation when an earthquake occurs. Owing to two times yearly
maintenance, the timing system is required to work 24 hours a day, 7 days a week,
constantly for 6 months. The reliability requirements can be evaluated through several
factors which include,• frequency of failures,• how long do outages last,• costs,• impact of failures.

The failure is defined as the violation of one or more system requirements and outage
is the period following a failure. The occurrence of a failure represents the start of an
outage, and the outage persists until the recovery is done. The failure can be further
divided into “hard failures” and “soft failures” based on the severity of consequence. For
example, in an accelerator timing system, there is often a trigger precision requirement,
for example, a jitter of less than 30 ps (r.m.s) for SuperKEKB MR [1, 13, 14]) is required.
The violation of the jitter requirement in a single pulse may not cease the operation of
the timing system or beam operation if the beam quality is acceptable for the ring.
On the other hand, the suspending of delivery of event timing signals caused by wrong
programming logic stops the timing system as well as beam operation. The former canbe regarded as a “soft failure” while the latter is a “hard failure”.
The words failure mode, failure mechanism and failure cause are used to describe theattribute of failure. For instance, the pause of event codes delivery in an event-basedtiming system is a failure mode. The vibration of the event generator module, CPU
module, and transmission cable is a failure mechanism. The failure cause is used todescribe the root reason, e.g., earthquake. By analyzing the failure mode, the deduced
6Motivation of this study
failure mechanisms are a chain of causes, and the root cause becomes the failure cause.
The failure is corrected by applying suitable countermeasures based on the failure cause.
While it is a fundamental goal to meet the reliability requirements in reliability engineering, maintainability and supportability also play a significant role in reliability. Many
factors involved in prompting system reliability are listed below.

• Failure location diagnostics,• Technical documentation and message sharing,• Workflow management,• Data and information acquisition,• Failure monitoring and report• Software review and audit,• Spare parts stocking and inventory management,

A universal procedure for reliability analysis starts from the system requirements analysis. After what the system does and how the system responds are thoroughly comprehended, the maintainability and supportability methods, such as failure location identification and failure data monitoring, are deployed to contribute to the failure mode
analysis. The reliability requirements evaluation is also reported based on failure data.
These steps are discussed in Section 6 as an example for reliability analysis of the timing
system at LINAC.

1.4

Motivation of this study

The goal of this thesis is to give an insight into the reliability of an accelerator timing
system and stabilize the timing system for SuperKEKB injector LINAC. Apart fromthe normal implementation of an accelerator timing system, several specific requirements demand the architecture of the timing system at KEK. These requirements andcorresponding solutions are discussed in this work. During the operation, the failureof the timing system significantly affects the physics run. A thorough analysis of the7Chapter 1. Introduction
failure effects and causes becomes urgent to increase the beam operation time and thus
contributing to the luminosity goal of the SuperKEKB collider.
Firstly, the event codes and timestamps should be recorded as these data are basic
evidence to identify the timing system error. To construct an event code log system, thedriver for the event timing module (i.e., EVR) is modified. The logging speed must be
carefully considered since the event clock is 144.24 MHz. After the trial of an EPICSbased event code log system, a relatively low-level log system is tested and successfullysaves the event codes without data loss. The AC50 arrival timing log is also developedsince the arrival timing of AC50 is a significant fiducial point during sequence shift.
Finally, we found that most of the timing failure is caused by strong AC50 drift by
identifying the failure mode and analyzing the failure mechanisms. The degree of AC50
fluctuation is measured and provides a quantitative assessment of failure frequency.
Several solutions by decreasing the length of sequence are proposed to solve the AC50
drift problem. An AC50 regulator is used to mask the strong AC50 drift. This method
degrades the beam quality and prohibits the injection of PF. Though it stabilizes thetiming system, the possibility of a fully functional timing system is discussed. The
method is to shorten sequence length by examining the possibility of removing thedependency between DR injection and extraction either through decreasing maximum
DR storage time or through shifting the downstream LINAC RF phase. The beamenergy deviation and operation stability of some hardware are tested. By shortening thesequence length and improving the sequence shift algorithm, the newer timing system canhandle extremely strong AC50 drift. Finally, the timing system should be stable enoughto provide trigger signals for accelerator devices and serves as a reliable component of
the accelerator control system.

1.5

Structure of Thesis

The thesis consists of eight chapters. The basic structure of this thesis is given as follows:• Chapter 2 gives the overview of the accelerator timing system and introduce
different classifications of timing system which mainly include event-based timing
system and timestamp-based timing system.
8

Structure of Thesis• Chapter 3 introduces the basic blocks of the timing system at the KEK accelerator complex. Some major hardware and basic parameters of the timing system
are introduced.
• Chapter 4 discusses the main requirements of the timing system at KEK LINAC.
These requirements come from either the hardware, such as klystron and pulsed
kicker magnet, or the systematic structure, such as DR operation and pulse-topulse modulation process.
• Chapter 5 talks about the detailed implementation of the timing system at KEK
LINAC which includes the reason for the sequence shift scheme and sequence
shift algorithm. The core part of the LINAC timing system, i.e., the main timing
station, is also analyzed and the control logic is displayed. The solution of bucket
selection limit caused by 2-bunch and 2-pulse DR operation is evaluated using
LINAC RF phase shift.
• Chapter 6 shows the failure modes during the timing system operation and failurecauses are discussed. The failure mechanism about how the timing system isaffected by strong AC50 drift is demonstrated and further analysis of AC50 drift
is done in this chapter.
• Chapter 7 illustrates the attempt to stabilize the timing system and propose thepossible timing system upgrade.
• Chapter 8 summarizes the thesis.

9Chapter2
Accelerator Timing System
2.1

RF Synchronization and Bucket Selection

For a larger experimental physics accelerator, the basic idea of a timing system is tobroadcast a timing clock and a master trigger signal. The timing clock can be thoughtof as a sinuous wave that decides the timing system resolution. The master trigger
which usually originates from external stimulus is synchronized with the timing clock
by a counter counting ticks of the clock from a fiducial point. A typical timing system
consists of three parts, generation, transmission, and receiving:• The main timing station with a master oscillator for RF clock synchronization andmaster trigger signal generation.
• A long-distance signal transmission network with low loss and good phase stability.
• A local timing station with receiver modules and delay modules where the trigger
signal is detected and delayed device-dependent pulsed timing is outputted to the
instruments.

A representative scenario of an accelerator timing system starts with the trigger of apulsed magnet power supply to maintain a stable flat top magnetic field, the gun is11

Chapter 2. Accelerator Timing Systemthen fired to generate the particles while the RF system must follow a proper phaserelation with the beam to achieve the desired accelerating effect. In addition, the bunch
injection timing needs to be sufficiently precise to meet the storage ring requirement andthe diagnostic devices, such as beam feedback systems and beam monitors, which mustmatch its measurement window with the beam arrival timing.
One should keep in mind that a constant time deviation, for example, the beam travelingtime in a beam transport line, is insignificant if this time interval is known and simply
compensated through programmable delay generator modules. The fixed transmission
delay value is usually calculated by physics simulation and observation of the real beam
arrival time. The fixed transmission delay is neglected in later descriptions for simplicity.
However, the variable transmission delay caused by the thermal effect of cable is nonnegligible for jitter consideration.

Figure 2.1: Timing sequence.

High precision RF synchronization can be accomplished through stable master oscillators, phase-locked loops (PLLs) and frequency synthesizers which includes integer-Nand fractional-N type. Apart from the distribution of RF signals, one major task of theaccelerator timing system is to calculate the bucket selection delay. Bucket selection isimportant for top-up injection to equate bunch current and maximize the usage of RF
power. To ensure that the circulated particles always see an accelerating RF field, thering RF frequency must be an integer multiple of the ring revolution frequency. The
relation is expressed in Eq. 2.1.

frf = h ∗ frev

12

(2.1)

RF Synchronization and Bucket Selection
The symbol h is known as the harmonic number, which also represents total RF bucket
numbers inside a storage ring. The revolution frequency frev is determined by the speedof the particle and the circumference of the ring. frev can be acquired by dividing theaccelerating RF frequency frf by harmonic number h. The obtained clock also assigns
one out of the h RF buckets, which can be defined as bucket “#0”. As Fig. 2.1 shows,
if injection is performing under frev , bucket “#0” is injected every time. By shiftingticks of frf , another RF bucket can be defined as “#0” and this technique is usefulduring the collision point tuning for double rings. After bucket “#0” is defined, an
arbitrary RF bucket can be selected by delaying proper pulses of the ring RF clock
period. The frequency during which all the RF buckets can be filled once is defined as abucket selection cycle (BSC), denoted as fBS . Also, note that fBS should be integrally
related with frev if there is no phase shift either in the ring or LINAC. For example, thecoefficient between fBS and fref in Fig. 2.1 is “1”, which means fBS = frev .
For a better illustration of the RF synchronization and bucket selection scheme, let
us consider a virtual electron accelerator complex that has a linear accelerator (LI), a
damping ring (DR), and the main storage ring (MR). The RF frequencies are expressed
as fLI−RF , fDR−RF and fM R−RF respectively. fDR−REV and fM R−REV stand for the
revolution frequency of DR and MR. hDR and hM R are the harmonic number of DR
and MR.

Figure 2.2: The injection opportunity is decided by fLI−RF and fM R−RF .

First, let us omit the DR and consider the beam injection between LI and MR. The
beam should sit at the same accelerating RF phase both in the LI accelerating structure
13Chapter 2. Accelerator Timing System
and MR. As Fig. 2.2 shows, if fLI−RF is an integer multiple of fM R−RF , the injection
opportunity appears every tick of fM R−RF . Otherwise, if fLI−RF and fM R−RF satisfy
the relation,
fLI−RF ∗ m = fM R−RF ∗ n(2.2)

where two integers m and n are mutually prime. The injection opportunity appears
in the greatest common frequency of fLI−RF and fM R−RF . This injection frequency is
described as fLI−M R−CF . The common frequency may be referred as other names, suchas coincidence frequency or intermediate frequency. The value of fLI−M R−CF can becalculated from,fLI−M R−CF =fM R−RFfLI−RF
=
m
n

(2.3)

Thus, from Eq. 2.3, the BSC for MR (fLI−M R−BS ) is derived as,
fLI−M R−BS =fM R−RF
fLI−M R−CF=hM R
m ∗ hM R(2.4)

The bucket “#0” can be filled if the injection is performing based on fLI−M R−BS . Thena delay may be added to select a bucket in the MR. The delay value should be an integer
multiple of fLI−M R−CF .
Next, let us omit the LI and consider the synchronization between DR extraction and
MR injection. Similarly, to transfer the beam from DR to MR, the common frequency
fDR−M R−CF between revolution frequencies of two rings should be used,
fDR−M R−CF =fDR−REVfM R−REV
=
p
q

(2.5)

where p and q are integers. For lepton accelerators, the RF frequencies for DR and
MR are usually the same. Thus, according to Eq. 2.1, p/q is the ratio of MR and DR
harmonic number. The BSC for DR and MR fDR−M R−BS is the same as fDR−M R−CF .
Finally, considering LI, DR and MR together, the overall BSC for DR and MR fLI−DR−M R−BS
is derived as,
fLI−DR−M R−BS =fM R−RFfDR−M R−CF=m
q ∗ m ∗ hM R

(2.6)

For our virtual accelerator, to synchronize the beam injection of LI, DR, and MR,
fLI−DR−M R−BS or any integer multiple of it should be used. The Eq. 2.6 is applicable14Classification of Timing System
for most electron colliders and synchrotron light sources. However, there exist several
exceptions, for example, the phase shift of accelerators, particle type changing at transfer
line, or hadron accelerators with slow beam velocity which induces an “inconstant” ringRF frequency, to break this rule. These restrictions are typically accelerator-dependent,
and examples can be found at CERN accelerators [15].

2.2Classification of Timing System

2.2.1

Fast Timing and Slow Timing

Based on different criteria, the timing system can be categorized into different groups.
One of the most intuitive aspects is the timescale. Several dividing lines exist as thereference and separates the timing system as “fast timing” and “slow timing”. The
timescale in a normal accelerator is listed in descending order.

1. Beam repetition rate
2. Storage ring revolution frequency
3. Single bunch monitoring
4. RF accelerating phase

The beam repetition rate (BRR), which is limited by pulsed devices, like modulators ofhigh-power RF system, should usually follow the AC power grid line, such as 60 Hz in
USA and Canada, 50 Hz in European and Eastern Japan, to stabilize the klystron beam
current heated by AC power line on consecutive triggers. The storage ring revolution
frequency is of great importance to the beam current measurement as well as the injection
matching between the injector linear accelerator and storage ring. The bunch control
usually lies at the nanosecond timescale. A fine adjustment of the RF accelerating phaseshould achieve a precision of femtoseconds. Often for colliders and synchrotron lightsource facilities, the boundary between “fast timing” and “slow timing” is usually thatthe “slow timing” handles timing signals slower than one storage revolution frequency
while the “fast timing” is responsible for a single bunch level.

15Chapter 2. Accelerator Timing System
A representative example of this classification is the timing system of Transposable
Ring Intersecting STorage Accelerator in Nippon (TRISTAN) project, which is theformer project before KEKB accelerator. The “fast timing” supplies timing signals forbeam monitors and beam feedback systems. The timing resolution is 1.5 ns for a 508
MHz main ring and RF bucket matching precision between the accumulation ring andthe main ring can achieve within ±6 ps through RF synthesizers and PLL circuit. The“slow timing” for TRISTAN is relaxed to 100 Hz for controlling operation mode or RF
accelerating voltage. It is achieved using a serial bus using Manchester II code, basedon the standard MIL/STD-1553B [16–18].
Now, the dividing line between “fast timing” and “slow timing” is vaguer with theevolution of high-precision electronics. For example, at KEK LINAC, the BRR is 50
Hz, the SuperKEKB MR revolution period is around 10 µs, the bunch spacing inside
the MR is about 2 ns, and the timing jitter of injection should be less than 30 ps. All
these trigger signals can be provided by an event-based timing system.

2.2.2

Analogue Timing and Digital Timing

Figure 2.3: The 50 Hz timing trigger signal (up) and 571.2 MHz clock signal (down)
were generated at the LINAC main timing station and distributed to the remote stations
through coaxial cable in the KEKB project era [1].

16Classification of Timing System
The transmission method of timing signal also leads to another classification method of
the timing system. As Fig. 2.3 shows, by combining the RF clock signal and master timing trigger, the analog signal transmission timing system is utilized. The RF frequency
that is served as a carrier wave and a timing trigger signal is overlaid in a transmittermodule and distributed to the facility through a coaxial cable. The RF frequency isthen regenerated through a bandpass filter in the local receiver module while the mastertrigger signal is detected by a voltage discriminator circuit. The master trigger signal
is used for a start pulse of a delay module which is driven by a recovered RF clock.
This method can achieve very high precision and is wildly used for accelerator facilities
before the 1990s [1]. However, there exists several drawbacks of analog timing transmission. One of the problems is the signal attenuation of coaxial cable during long-distancetransmission. Thus, many cascaded fanout modules, receivers, as well as cabling are
required to maintain a satisfactory signal accuracy which results in a high cost [19].
Another disadvantage is the difficulty of diagnosing the timing system since no extra
information such as timestamp, beam mode, and beam properties, are provided to thedevice. Lack of flexibility is also a troublesome issue for operation. For example, it
is difficult to switch the device seamlessly if machine study and beam operation are
performed continuously.
By encoding the trigger messages onto a synchronized RF carrier clock, the digitaltransmission is used to broadcast the data stream called timing events from one masterstation to all the local stations. The transmitter is responsible for modulating thenumeric codes while the receiver performs demodulation. Due to the stability of thedigital signal, a good quality twisted pair cabling or optical fiber can replace the coaxing
cable to construct the timing network. The main advantages of the digital transmission
compared with the analog transmission are,

• The flexibility of device control is extended for future upgrades.
• Increase the stability of long-distance (km range) transmission through opticalfiber-based timing network.
• The field wiring is simplified and the cost is reduced.
• Communication standards can be agreed to maintain a universal solution andshared among scientific facilities.
17

Chapter 2. Accelerator Timing System• Encoded digital data through line code technology enhances the error detection
ability.
• Timestamp information for diagnosis can be encoded and sent from the master toslave nodes.

Note that it is difficult to achieve RF synchronization and low-level RF (LLRF) control
by adding digital delay to the electronics because of the strict RF phase stability requirement. The analog timing and digital timing approaches are combined for nowadays
accelerators.

2.2.3

Event-based Timing and Timestamp-based Timing

Imagine somebody wants many pulsed magnets to trigger all at midday exactly in a
sub-nanosecond timescale. One solution, called event-based timing system (EBTS), is
to distribute event messages through Fan-Out units that are generated at a master event
generator module, to which the event receiver modules would respond to the messages
by producing pulses with carefully calculated delay to drive the pulsed magnets. The
event generator module is also responsible for clock synchronization and encoding of
event codes. The event receiver module is responsible for decoding the optical signal
and producing output signals.
Another common and straightforward strategy, called timestamp-based timing system(TBTS), which is quite like the event-based timing system, works by transmitting thetimestamp information over the timing network using techniques that we will describe
later, to synchronize the internal notion of time typing in a nanosecond resolution. Afterthe receiver modules are all time-locked, the instruction for firing the pulsed magnets
at midday is broadcasted before midday. Then, the receiver modules generate output
pulses to the devices when the local timestamp matches the timing decoded from the
instruction.

18

EBTS

2.3

EBTS

Though many accelerators started to distribute timing events using digital transmission,
such as the Large Electron–Positron Collider (LEP) project at CERN and the TRISTAN project at KEK, the attempt of designing a modularized EBTS was implemented
for the Tevatron project at Fermilab [17, 20]. The highly integrated Fermilab event receiver modules can decode the events using modified Manchester encoding, recover the
global event clock, generate programmable VME interrupts, save the event codes into
an event FIFO memory together with a high-resolution timestamp, and output pulse to
the device. The event system developed by Frank R. Lenkszus and Robert Laird at theAdvanced Photon Source (APS) in 1994 is another elegant example [21]. As shown in
Fig. 2.4, the APS EBTS consists of a VME event generator card that receives hardware
and software trigger inputs and converts them to 8-bit event codes using 8b/10b encoding [22]. The event codes are stored at two sequence RAM and sent sequentially underthe external clock rate. The receiver card has several outputs which include 14 fixeddelay outputs, 7 set-reset flipflop outputs, and 4 delayed-pulse outputs. Other features
include the heartbeat event code transmission, event code priority encoder for collision
avoiding, event and timestamp FIFO for buffering, EPICS environment integration, andtimestamp synchronization. The APS EBTS design was also selected for the Swiss Light
Source (SLS) with several important feature upgrades like the “distributed bus (DBus)”
transmission function.
With the practice of these projects, a generic toolkit of EBTS evolves gradually basedon worldwide collaboration. One of the most popular and representative EBTS implementations is developed by Micro-Research Finland (MRF) company which focuseson timing systems for particle accelerators. The MRF EBTS consists of a family of
products for different event generators (EVGs) and event receivers (EVRs) like VME,
CompactPCI, and MicroTCA. The topology of the MRF event timing network is shownin Fig. 2.5. We will briefly illustrate the key features of MRF EVG and EVR and thedetailed specification can be referred from the official manuals. Note that several newfeatures like delay compensation are brought into the newly released products, the discussion in this section mainly focuses on the VME-EVG-230 and VME-EVR-230, which
are currently used at KEK LINAC.

19

Chapter 2. Accelerator Timing System

Figure 2.4: EBTS for APS. Two event generators are cascaded and transmit eventcodes as well as periodic timestamp events to an array of event receivers through fiber
optic links.

Figure 2.5: A typical layout of event timing system.

2.3.1

RF Clock and Event ClockAll operations on EVG and EVR are synchronized to the event clock which ranges between 50 MHz and 125 MHz. The event codes are transferred through optical fiber underthe event clock which is regenerated on local EVRs. The event clock is derived from

20

EBTS
either an external RF clock or from an onboard fractional synthesizer. The maximum
RF frequency is limited by the internal circuit at 1.6 GHz.

Figure 2.6: The event stream consist of a combination of 8-bit event codes and data
sent out at the event clock.

2.3.2

Event Stream

The limitation of the APS EBTS is that only one event can be transmitted at one event
clock period. To overcome this, as shown in Fig. 2.6, MRF EBTS uses a 16-bit frame(called an event stream) to send the data together with the 8-bit event codes. The 8-bit
data can be taken from either the DBus or from an optional 2 kB dual-port memory
called Data Buffer. Eight DBus data are transmitted simultaneously either with theevent clock time resolution or half which depends on whether Data Buffer is enabled.
The 8B10B protocol is used for parallel/serial conversion, in that the serial clock is 20
times of event clock.

2.3.3

AC Trigger

It is usually necessary to synchronize the timing trigger with the AC power line to keep
many devices operate at a constant AC phase, e.g., at the zero-crossing point. Normally21

Chapter 2. Accelerator Timing Systema repetition rate generator module should be developed to provide the trigger signal.
Thus, the EVG module provides the functionality of synchronization between the AC
power line and the event clock. The synchronized signal can be used to trigger thesequence RAM (see Section 2.3.6) or a trigger event.

Figure 2.7: Sub-components inside the MRF EVG.

2.3.4

Event Codes Generation

As Fig. 2.7 shows, 256 event codes originate from several sources are sorted at a priority
encoder to avoid the collision. 8 trigger events are sent out on a stimulus from a multiplexed counter, an external TTL level signal, or the AC power line synchronization
logic output signal. Two sequence RAMs also provide a method of easily transmittingor playback a set of event codes. We will discuss this part later in Section 2.3.6. Mostof the event codes can be defined by the user. However, several special event codes are
already occupied by the system. The predefined event codes are list in Table 2.1.

2.3.5

Timestamp Synchronization

As shown in Fig. 2.8, the implementation of timestamp synchronization by the MRF
hardware consists of a 32-bit seconds register (SecReg) and a 32-bit timestamp register(TsReg). EVG receives the time source either from an external GPS or from a Network
Time Protocol (NTP) server. The value of SecReg is changed with 32 special codes
22

EBTS
Code
0x00
0x70
0x71
0x7A
0x7B
0x7C
0x7D
0x7F

Meaning
Idle, or null, event. Send when nothing happens.
Shift 0 into EVR timestamp shift register
Shift 1 into EVR timestamp shift register
Reset EVR heartbeat timeout counter
Reset all EVR dividers. Synchronize global phase
Increment EVR timestamp counter (depending on mode)
Reset timestamp counter
End of sequence (not transmitted).
Table 2.1: Special event codes for MRF EBTS.

(either event “0x70” or event “0x71”) sent from the EVG while the TsReg is maintainedby each EVR and incremented at an integer divisor of the event clock rate or the special
event code “0x7C”.

Figure 2.8: Timestamp synchronization logic.

Note that the timestamps for receiver modules with a long-distance, e.g., 10 km, maydiffer in a microsecond scale due to the delay caused by the transmission medium. This
problem can be palliated either by newer hardware with a delay compensation function
like MRF EVM-300 module or by TBTS (see Section 2.4).

23

Chapter 2. Accelerator Timing System

2.3.6

Event Sequencer

The sequencer holds up to 2048 pairs of event code and timestamps. The contents of asequencer can be altered via VME access. The sequencer may be triggered from several
sources including external TTL input, software triggering by VME access, AC powerline logic, or a multiplexed counter output. When the sequencer is triggered, an internalcounter starts on a sequencer clock rate which can be down-converted from the event
clock with a prescaler. When the timestamp matches the counter value, the attachedevent code is sent out.

2.4

TBTS

Figure 2.9: IEEE 1588 synchronisation mechanism and delay calculation.

Unlike the EBTS that needs an external stimulus to trigger, the TBTS broadcasts an
instruction message with an action and correspondent timestamp after a common notionof time is reached through the timing network. The microsecond timing synchronization
can be achieved by the Precision Time Protocol (PTP, IEEE1588) [23].

24Examples of Accelerator Timing system
As depicted in Fig. 2.9, to synchronize the timestamp between master and slave, byassuming that the link is symmetric, the delay δ can be calculated with the time tags
t1 , t2 , t3 and t4 through,δ=(t4 − t1 ) − (t3 − t2 )
2

(2.7)

One example of such implementation is the White Rabbit (WR) project designed by
CERN, GSI, and others. Two main technologies are used at WR,• Synchronous Ethernet, all network devices can have the same clock, recovered from the timing master. The clock is encoded in the Ethernet package andrecovered by the PLL of the Ethernet physical layer to alleviate the clock skew
effect.
• WR PTP, the WR PTP detects the phase offset between local clocks and masterclock and compensates for the delays introduced by the link.

However, two non-deterministic factors, thermal change of transmission medium andasymmetric link delays limit the WR accuracy of around 1 ns, which is basically at thesame scale of EBTS.

2.5

Examples of Accelerator Timing system

2.5.1

BEPC II

The Beijing Electron Positron Collider II (BEPC II) is a double-ring electron-positron
collider with a 202 m long LINAC. It can either serves as a collider or a light source
facility with its outer ring for a storage ring [24]. The key timing system parameters of
the BEPC II collider mode are shown in Table 2.2.
Since the beam is directly injected into the main ring from LINAC, the RF frequencies
of LINAC and MR should match relation of,
2856 ∗ 7 = 499.8 ∗ 40

(2.8)

25

Chapter 2. Accelerator Timing System
Parameter
LINAC RFMR RF
MR harmonic number
MR circumference
MR revolution frequency
Common frequency for LINAC and MR

Value
2856 MHz499.8 MHz
396
237.5 m1.26 MHz
71.4 MHz

Table 2.2: Timing system parameters of BEPC II

The greatest common frequency for BEPC II bucket selection is 71.4 MHz which can beobtained through a divide-by-7 divider of MR RF according to Eq. 2.3. However, thefrequency divider factor of the old version of the MRF EVG 200 module only supports
4, 5, 6, 8, and 10 [25]. Given this context, fM R−RF /5 is first selected as the event
clock inside the EVG and then the common frequency of fM R−RF /35 for BEPC II
BSC is generated through the multiplexed counter component inside the EVG. Though
the period for selection of all RF buckets becomes 5 times longer, this period is still
acceptable while comparing to the 50 Hz BRR.

2.5.2

SLS Timing System

Figure 2.10: Layout of SLS.

26

Examples of Accelerator Timing system
Like other third-generation light source facilities, the SLS projects consist of an injector
LINAC, a Booster, and a storage ring (SR), as Fig. 2.10 shows. The EBTS at SLS is
responsible for synchronizing the RF clock and AC power line, distributing event codes,
and control the machine operation sequencing. The injection cycle is 320 ms (3.125
Hz) which comes from the synchronization of AC power line (50 Hz) and common
frequency [26]. The timing system parameters of the SLS are listed in Table 2.3.
Parameter
LINAC RF
Booster RF
Booster harmonic number
Booster circumference
Booster revolution frequency
SR RF
SR harmonic number
SR circumference
SR revolution frequency
Common frequency for booster and SR

Value
2997.6 MHz
499.6 MHz450
270 m
1.11 MHz499.6 MHz480
288 m
1.04 MHz69.44 kHz

Table 2.3: Timing system parameters of the Swiss Light Source.

The RF frequency for SLS LINAC is exactly six times of SR RF frequency at SLS, whichmeans the parameters m and n in Eq. 2.3 are “1” and “6”, respectively. Consequently,
consideration should only be given into synchronization between Booster and SR. The
ratio of Booster harmonic and SR harmonic, i.e., p/q in Eq. 2.5, is 16/15, which means if
having had “#0” bucket in alignment, “#0” bucket will be in alignment again every 16
Booster revolution cycles or 15 SR revolution cycles [27]. Thus, the common frequency
can be derived according to Eq. 2.6.
Since the Booster revolution frequency is used to trigger the EVG sequence RAM. By
moving the event one position later in the sequence RAM, the injection bucket to SR
shifts by 30 buckets. That means the “#0” bucket bunch in Booster is injected into“#450” in SR.

27

Chapter3
Overview of Timing System at
KEK LINAC
3.1

Hardware and Software

The timing system at KEK LINAC consists of much hardware. Some of them are inherited from the timing system at the KEKB era while some are newly installed to improve
the stability and extend the functionality [28, 29]. For example, the event generator
module (VME-EVG-230) and event receiver module (VME-EVR-230RF) produced by
MRF company still serves as the core timing system part during the past ten years. On
the other hand, several new modules, such as time-to-digital converter (TDC), reflective memory (RFM), and master trigger generator (MTG), are introduced to meet new
requirements for SuperKEKB as well as extending the system functionality.
A schematic view of the event timing system currently used at LINAC is shown in
Fig. 3.1. The timing station which generates the master trigger event signal is called
Main Timing Station (MTS). Three MRF-VME-EVG230 modules and an MVME6100
CPU module are installed at MTS [30]. The main timing station delivers events to
20 local EVR stations at KEK LINAC. Besides MTS, many sub-timing stations with
29

Chapter 3. Overview of Timing System at KEK LINAC

1

1

2

KL_B5/B6

SB_B

A1

1
GU_AT

Thermionic gun

1
Sector B

3
Sector R

A1_RF_Gun

EVR Station
PhotocathodeRF gunMain Timing Station

VME chassis

Number of EVR modules

EVG
EVG
EVR
TDC
EVG
CPU

Cont
ABC

Sector A

As of June 2021

2
TMDR

1

1

2

SB_C

SB_1

SB_2

Sector C

Sector 1

1

Main TrigDR

Sector 2

2

1

2

1

SB_3

SB_4

SB_5

KL_61

Sector 3

Sector 4

Sector 5

2

1

1

1

1

Cont 1

Cont 2

Cont 3

Cont 4

Cont 5Figure 3.1: Layout of timing stations at LINAC [2].

EVRs mounted in the VME64x subrack are connected to the EVG with fiber-optic
links in a star-like topology. The EVR can receive an event stream from the EVG at a
speed of 57.12 MB/s. There are six local EVR stations installed at sub-control rooms,
eight stations located at sub-booster stations, and other local timing stations, which are
distributed along the LINAC beamline. Two of the most important sub-timing stations
are the MR Sub-timing Station (MR-STS) and DR Sub-timing Station (DR-STS).
EPICS is selected as the control system framework of KEK LINAC, and the timing
system modules also integrate with the EPICS environment through some device supportand driver support libraries. In addition, the event stream of 8b/10b encoding can also
be decoded by user-defined field-programmable gate array (FPGA) board [31]. The RF
monitor system is a good illustration of event stream recognition, which integrates the
EVR function inside the Virtex-6 FPGA to acquire the beam mode, RF phase, andother necessary data are sent from EVG.

3.1.1

Event Modules

As Fig. 3.2 show, MTS IOC consists of three VME-EVG-230 modules, one TDC module,
one VME-EVR-230RF module and one RFM module [2, 32–34]. These modules, which
are in a VME64x subrack with MVME6100 CPU, collaborate to generate synchronizedtiming signals from 50 Hz AC power line (AC50) and BSC. Then, these signals are
distributed to event receiver stations. The receiver station is composed of an MVME5500
CPU, because of the relatively relaxed CPU load, VME-EVR-230RF module, and several
I/O modules [35]. MTS IOC uses VxWorks 6.8.3 as a real-time operating system andruns EPICS version 3.14.12.
30

Hardware and Software

Figure 3.2: Event modules installed at MTS.

Besides the MRF event modules, Shanghai Institute of Applied Physics (SINAP) event
modules are also used. The specifications of MRF event modules and SINAP event
modules are summarized in Table 3.1. The trigger signals for MR BPMs are required
to synchronize with the MR revolution frequency which cannot be acquired directlyfrom MTS. Consequently, an extra module is necessary to supply the trigger signal.
SINAP event modules mainly include VME-EVO and VME-EVE. The VME-EVO canbe configured as EVG, EVR, or FANOUT by software while VME-EVE could only be
used as EVR [36]. The VME-EVO module is compatible with the MRF module andprovides the functionality to synchronize with another RF input. Thus, with the help of
SINAP modules, it is convenient to both receive the data from MRF-EVG and supply
MR-synchronized signals for BPMs. The connection between MRF modules and SINAP
modules is shown in Fig. 3.3. MRF-VME-EVG located at MTS sends event codes to both
MRF-VME-EVR and SINAP-VME-EVO. SINAP-VME-EVO also receives the input of
MR RF frequency and sends event codes to SINAP-VME-EVE [37, 38]. Therefore, alloutputs from SINAP-VME-EVE are synchronized with the MR RF clock with a jitter
31

Chapter 3. Overview of Timing System at KEK LINAC

Figure 3.3: Schematic view of MR Sub-timing Station.

of about 10 ps.
MRF
EVR-230RF
114.24 MHzAC
Up-link event
Event Clock Event Clock/40∼30 psEVG-230
Event Clock
Trigger
Resolution
Jitter

SINAP
EVE
99.39 kHz
Up-link event Up-link event
Event Clock
Event Clock/20∼10 psEVO

Table 3.1: Specifications of MRF and SINAP VME event modules used for MR-STS.

An EPICS driver for VME and PCI cards from MRF for event timing systems called
mrfioc2 is used to integrate the device control with EPICS environment [39]. For SINAP
devices, a dedicated EPICS driver is also developed. Consequently, the timing adjustment can be controlled based on EPICS. Two standard “waveform” records are used to
manage event codes and correspondent delays. The value of these records is loaded into
the sequencer RAM of EVG and delivered to EVRs. The timing system control logic,
such as the beam mode switch, is also implemented inside the MTS IOC through EPICS
records.

3.1.2

MTG

The MTG module is responsible for generating a master trigger signal at the same
phase of the AC power line to keep the stability of some power-sensibility devices, such
32

Hardware and Software

Figure 3.4: MTG module (right) in a NIM crate.

as pulsed magnets for MR injection. The AC power used at KEK LINAC is provided
by Tokyo Electric Power Company. This commercial frequency will fluctuate at around50±0.2 Hz.
The implementation logic of the MTG module is intuitive. Basic circuits of the MTG
module consist of an AC-DC converter, a voltage comparator, and a monostable multivibrator to generate the 50 Hz TTL type output signal. Fig. 3.4 shows the MTG module
installed in the NIM crate.

3.1.3

TDC

To quantify the time duration of several trigger signals, a 16-channel FPGA-based TDC
has been developed on a Xilinx Spartan-6 FPGA equipped on a VME board with aresolution of 1 ns [2]. The TDC module developed at KEK LINAC is shown in Fig. 3.5.
It serves as the major hardware to measure the AC50 arrival time, which is crucial since
LINAC needs to operate on the same phase of AC50. It can also be used for measuring
the output from EVR. Since the event clock resolution is 8.75 ns, a resolution of 1 ns and33

Chapter 3. Overview of Timing System at KEK LINAC
a dynamic range greater than 20 ms are required for the time-duration measurementsin the TDC.

Figure 3.5: TDC module.

The VME-based TDC has a common start channel and 16 stop channels. The input
signal is based on a Nuclear Instrumentation Module (NIM) standard with a 50-Ω input
impedance [40]. The reference signal is fed into the common start channel, and thedelayed trigger pulses are fed into the stop channels. Thus, the time duration between thestart channel and stop channel can be measured with 32-bit counters with a resolutionof 1 ns. Therefore, the maximal measurement range is 4.3 s. The accuracies of the timeduration measurements are less than 1 ns and 2.6 ns within dynamic ranges of 7.5 ms and20 ms, respectively [2]. Every channel supports the multi-stop function which provides
the ability to measure delay timings of up to 4 successive trigger pulses. This is an
important specification required for the two-bunch operation mode at LINAC, in which
the time duration between two bunches is exactly 96.3 ns. The 1000Base-T Ethernet
connection also enables fault diagnosis and data acquisition for the TDC without theinterfere of VME CPUs.
The EPICS driver of the TDC module is developed to read the content of the buffer
data in the FPGA via an A32/D32 VME64x interface. The measured data is saved in
an EPICS “waveform” record with 64 elements and can be accessed remotely throughthe EPICS CA protocol.

34

Hardware and Software

3.1.4

RFM

The reflective memory (RFM) module (Also known as “Shared Memory”) is a real-time
fiber-optic network product that is mainly used to share data regardless of architecturesand operating systems. The VME-5565 module provides a method of fast communication among VME computers. The data stored in the local RFM will be automaticallybroadcasted over a 2 Giga Baud high-speed and low latency link to other RFM nodes,
and this process is software transparent. The RFM network supports up to 256 nodes
and connection distance can reach up to 300 m with multimode fiber and up to 10 kmwith single-mode fiber, respectively. The dynamic packet size, 4 to 64 bytes of data,
achieves a network transfer rate of 43 Mbytes/s to 170 Mbytes/s [34].

Figure 3.6: Reflective memory module (VME-5565).

Another useful functionality is network interruption transmission. Four general-purpose
network interrupts with 32 bits of data each can be directed to a specific node or broadcast globally to all nodes on the network. Any of the four possible network interrupts
can also generate a host VMEbus interrupt at each receiving node.
Two kinds of network topology are supported for the RFM module. By simply connecting
every module as a ring, it is easy to construct a light-weighted network that avoids thecomplexities of queuing and checking data packets. On the other hand, with the help of afiber-optic hub, a star topology enhances the network availability and system robustness
35

Chapter 3. Overview of Timing System at KEK LINAC
since the network will continue to operate even if one module fails. The ACC-5595 RFM
hub has 8 ports, and each port regenerates the serial optical signal, eliminating cableattenuation problems as well as reducing jitter [41].

Figure 3.7: ACC-5595 Reflective Memory Hub.

The RFM 5565 module and ACC-5595 RFM hub used at SuperKEKB bucket selection
system are shown in Fig. 3.6 and Fig. 3.7.

3.2

RF Synchronization at LINAC

Fig. 3.8 shows the RF frequency synchronization of the LINAC timing system which
equips several frequency multipliers/dividers and phase shifters. “Rev” indicates therevolution frequency, “BS” indicates the bucket selection, “E/O” indicates the electrical/optical converter and vice-versa, and “Acc.” indicates the accelerator structure.
The LINAC master oscillator (LINAC-MO) is synchronized to the MR master oscillator(MR-MO) and DR master oscillator (DR-MO) by the external 10 MHz references generated by a frequency division of the 510 MHz main oscillators (MMO). LINAC-MO,
DR-MO, and MR-MO belong to the commercial Agilent E8663 series [42]. The phasedrift caused by the long-distance transmission is compensated by phase monitoring anddirect sampling technique [43]. The slow drift of the beam energy caused by phase drift
is suppressed.
36

RF Synchronization at LINAC
PLL

Main MO
510 MHz510 MHz

1/51
10 MHzLinac-MO
571.2 MHz114.2 MHz

10.385 MHz

Linac
Gallery

EVG

MTG

EVR

114.2 MHz
2856 MHz
10.385 MHz

44 Hz Trigger

10 MHz

Event
Timing
System

Triple Sync. AC Trigger
Module for PF

Triple Sync. AC Trigger
Module for AR

MR-MO
508.89 MHz
EVG

TDC

EVG

DR-MR-BS Cycle
44 Hz

1/46

Freq Multi/Div 2
OpticalFanoutUp

Down

2856 MHz114.2 MHz

571.2 MHz

OpticalFanout

MR-BS Cycle
2 kHz

O/E
Upstream
EVRs

Acc.

Downstream
EVRs

For Gun, Klystrons, BPMs,
Pulsed Magnets, etc

DR

For Klystrons, BPMs, Pulsed
Magnets, Kicker, etc

RF Gun2856 MHz

Linac

MR Rev
99.39 kHz

Kicker,
SeptumAcc.

1/5120

Down

Up

Thermionic
Gun

SHB1

1/49

DR-MO
508.89 MHz

E/O
SHB2

1/51

AR RevPF Rev

TDC Start

TDC Stop

Freq
Multi/Div 1

Event Clock
AC Line
Input

IP

LER

MR

HER

2856 MHz
Acc.

Figure 3.8: Block diagram of synchronization system for LINAC, DR, and MR.

The fundamental frequency between LINAC-MO and MR-MO is 10.385 MHz, whichmeans 55 cycles of LINAC-MO covers exactly 49 cycles of MR-MO. For laser oscillationof the RF gun, a supply of 10.38 MHz, 114.24 MHz, and 2856 MHz are required fromthe main drive system. The 11th harmonic (114.24 MHz) and 55th harmonic (571.2
MHz) of the fundamental frequency are used to drive two subharmonic bunchers (SHBs)
immediately after the electron gun [44]. The 2856 MHz RF field is used to drive theaccelerator structures. Both DR and MR use 508.89 MHz as the ring RF frequency.
The integer relation of RF frequencies is shown in Table 3.2.
Frequency
10.385 MHz
114.24 MHz
571.2 MHz
2856 MHz508.89 MHz

Ratio
×11
×55
×275
×49

PurposeRF GunLINAC SHB1 & RF Gun
LINAC SHB2
LINAC Main RF & RF Gun
DR & MR RF

Table 3.2: Integer relation of RF frequencies at KEK LINAC

However, the PF and the PF-AR are not synchronized to LINAC because the two
accelerators use independent RFs. Thus, the chance coincidence of LINAC RF (114.24
MHz and 10.385 MHz) and PF/PF-AR RF revolution frequency is utilized through the37

Chapter 3. Overview of Timing System at KEK LINAC
triple sync module (shown in Fig. 3.8). The output of the triple sync module is used as
the main trigger of PF/PF-AR injection timing [45].

3.3

Bucket Selection for SuperKEKB

3.3.1

Delay Calculation of RF Buckets

RF frequencies are also used for driving the timing system at KEK LINAC. The timing
system uses 114.24 MHz as the event clock to deliver the event codes, and the beam
repetition rate (BRR) is 50 Hz. The harmonic number for DR and MR is 230 and
5120, respectively. Note that there only exists a positron DR, the synchronization between LINAC and HER is simple. The bucket selection cycle (BSC) for LINAC andHER fLI−HER−BS can be easily derived as 2.03 kHz based on Eq. 2.4. Thus, we will
mainly focus on the BSC of LER. According to Section 2.1, several significant frequencies for timing system can be calculated in Table 3.3. Note that the BSC for DR onlyis practically useful when performing DR-injection-only mode for beam study.
Frequency
2856 MHz508.89 MHz
114.24 MHz
2.21 MHz
99.39 kHz45.15 kHz2.03 kHz88.19 Hz
50 Hz

Period350 ps
1.97 ns
8.75 ns
452 ns10.06 µs
22.15 µs
493 µs
11.34 ms
20 ms

Remarks
RF frequency for LINAC
RF frequency for DR & LER
Event clock
DR revolution frequency
LER revolution frequency
BSC for DR only
BSC for LER only
BSC for DR and LER
BRR

Table 3.3: Bucket selection frequencies at KEK LINAC

The integer relation between LINAC RF and LER RF is 275/49. Thus, the positron
beam injection opportunity appears either every 49 ticks of 508.89 MHz or every 275
ticks of 2856 MHz. Furthermore, after waiting for 49 ticks of LER revolution frequency,
the same LER RF bucket can be injected again. Similarly, the ratio of DR harmonic
number and LER harmonic number is 23/512 which means the same combination of
DR RF bucket and LER RF bucket can be selected every 512 cycles of DR or 23 cycles
of LER. Concerning the LINAC synchronization, the overall BSC becomes 88.19 Hz as
shown in Fig. 3.9.
38

Bucket Selection for SuperKEKB

Figure 3.9: Bucket selection for DR and LER.

The relation between injection delay and bucket number in LER and DR can be describedas following,
Tdelay ∗ 49
NLER = M OD
, 5120
96.3(3.1)

Tdelay ∗ 49
NDR = M OD
, 230
96.3

(3.2)









where NLER and NDR represent the bucket number in LER and DR, respectively. Table 3.4 also shows the relation between injection opportunity and bucket number. The
calculation is based on Eq. 3.1 and Eq. 3.2. After 11.34 ms, both DR RF bucket “#0”and LER RF bucket “#0” can be filled again. By adding a proper delay value (must be
an integer multiplication of 96.3 ns) based on BSC, arbitrary LER RF buckets can be
filled. Note that the BSC of 22.68 ms (i.e., 44 Hz) is used because we want to decrease
the interrupt handling times and simplify the system.
Figure 3.10 shows the simplified procedure of delay calculation for DR and LER. First,
the bucket number for LER is designated (for example, bucket “#49” will be filled),
and then the delay value Tdelay2 for LER can be acquired by Eq. 3.1. Since Tdelay2 also
represents the DR extraction timing, thus, the DR bucket number is obtained. The delay
value for DR injection is periodic based on Eq. 3.1 and the Tdelay1 is selected because of
the DR storage time limit. The detailed calculation process can be referred to in [46].
In practice, the calculation of bucket selection delay for LER is tougher because the
DR storage time should be taken into consideration. The minimal damping time isdetermined to be 40 ms, which is longer than 20 ms, owing to the requirement of position
39

Chapter 3. Overview of Timing System at KEK LINAC
Injection opportunity
0
1
2
3
..
230
..
5120
..
20771
20772
..
117760Delay
0 ns
96.3 ns
192.6 ns288.9 ns..
22.1 µs..
493 µs..
1.99 ms
2 ms..
11.34 ms

DR Bucket
0
49
98
147
..
0
..
180
..
29
78
..
0

MR Bucket
0
49
98
147
..
1030
..
0
..
4019
4068
..
0

Table 3.4: The relation between injection opportunity and bucket number.

Figure 3.10: Delay calculation for DR and LER.

emittance. As a result, the injection and extraction of DR are separated into two pulses
and should be controlled by two EVGs. Thus, the LINAC is virtually divided into twoparts, which include the “Upstream LINAC” and “Downstream LINAC”. Apart from thebasic accelerator devices at LINAC, such as klystrons and BPMs, the major differenceof controlled hardware between “Upstream LINAC” and “Downstream LINAC” is thatthe “Upstream LINAC” includes the electron gun and injection magnets at DR, the“Downstream LINAC” includes the extraction magnets at DR and injection magnets of
MR. In other words, the former is responsible for DR injection with the “Upstream EVG”
while the latter controls the DR extraction and MR injection through “Downstream
40

Bucket Selection for SuperKEKB
EVG”. We will fully discuss this part in Section 4.3.

3.3.2

Decision Making of Injection Bucket

Several factors are known to play a role in determining which RF bucket should be filled.
For example, continuous injection into the same RF bucket or adjacent RF buckets
should be avoided. If the same RF bucket is selected, the bunch stored in that RF
bucket is repeatedly kicked in 50 Hz. As a result, there is not enough time to damp
the bunch by the transverse radiation damping effect. The coupled bunch instability,
heating of the beam pipes, and degradation of the vacuum caused by high beam current
would also raise the difficulty of short spacing RF buckets selection [47].

Figure 3.11: An example of fill pattern in LER during KEKB era.

Also, the transverse coupled-bunch instabilities caused by the fast-ion instability can bealleviated through the multi-trains filling. When a train of electrons passes a point in
the ring, each bunch ionizes the residual-gas [48, 49]. These ions are accumulated as
trailing bunches pass the point and cleared out during the training gap. Consequently,
a fill pattern is necessary to carefully determine the multi-trains filling scheme. The fillpattern decides,
41

Chapter 3. Overview of Timing System at KEK LINAC• the number of the trains• the number of bunches per train• the bunch spacing

As Fig. 3.11 shows, bunches in HER are divided into 32-trains, 40 bunches per train,
and 6 ns bunch spacing.
To cure the instabilities, the bunch-by-bunch feedback system is also developed to kickthe beam and damp the oscillation [50, 51]. The feedback system achieved a satisfactory
effect in the SuperKEKB era and normally 2-trains filling is used (Fig. 3.12). The gaps
shown in Fig. 3.12 comes from the abort system. The beam abort system is constructed
at SuperKEKB to protect the accelerator components, Belle II detector, as well as
ensuring the radiation safety [52]. A fast response is required to quickly deliver thestored beam into a beam dump and prevent spewing the beam everywhere in the ring.
Because of this, the stored bunches are separated into several trains to reserve adequate
bunch spacing as the abort gap. The beam abort gap is designed to be less than 200 ns(around 100 RF buckets). The requirement comes from the luminosity degradation due
to beam-loading effects as well as the requirement for the stable operation of RF cavities.

Figure 3.12: Fill pattern during SuperKEKB era for HER.

42

Bucket Selection for SuperKEKB
The bunch currents inside the RF buckets become different since the beam lifetime varies
with the position of the stored RF bucket. The lowest bunch current bucket should beselected for injecting to save the beam and increase the luminosity. This function iscalled “Bunch Current Equalizer (BCE)”. The bunch-by-bunch current monitor, as aby-product of the bunch-by-bunch feedback system, provides the beam current dataof every stored RF bucket with an 8-bit ADC. The implementation of beam current
monitor is described in [51]. However, “BCE” is restricted when “2-bunch” mode isselection, i.e., , two bunches are formed every injection pulse with a 96.3 ns bunch
spacing. Therefore, other than the fill mode of “BCE”, a fill mode of “star” type is
supported for the “2-bunch” operation. The fill mode of “star” needs to memorize thepreviously filled RF bucket and selects the RF bucket with a proper distance to the lastfilled bucket. The bucket spacing is carefully chosen to obey the fill pattern rule. By
performing the “2-bunch” injection of “star” mode first and single bunch “BCE” mode
later, the bunch current in the stored RF buckets can be equalized. An illustration of“star” fill mode is shown in Fig. 3.13.

Figure 3.13: Bucket selection fill mode of “star” type.

43

Chapter 3. Overview of Timing System at KEK LINAC
Consequently, the decision on which bucket should be filled is done based on the following
information:

1. fill pattern,
2. fill mode and associated parameters,
3. bunch current information of each RF bucket,
4. number of bunches,
5. the bucket address last filled.

3.3.3

Constituents of Bucket Selection System

The bucket selection system currently used for SuperKEKB is inherited from the KEKB
bucket selection system, which started in 1998 [53]. Although the hardware and software
evolved a lot, the fundamentals of the bucket selection system remained as a triangle
structure as shown in Fig. 3.14. The MTS node located at LINAC first generates aninterrupt to Central Control Building (CCB) node. The CCB node decides the RF
bucket which would be injected based on either “BCE” fill mode or “star” fill mode.
The bunch currents for the RF buckets measured by Bunch Current Monitor (BCM)
node are required if the “BCE” fill mode is selected. The delay value of that RF bucket
is subsequently calculated at CCB and is transferred to the MTS node to finish thebucket selection process [54, 55].
All these nodes equipped the RFM module which connects through a dedicated fiberbased communication network. The RFM network topology can be selected for eithera ring topology or star topology. Through the fiber-optic HUB-5595 module, a star
topology RFM network is configured to increase the robustness of the bucket selection
system at SuperKEKB. The RFM network will continue to operate even if one RFM
node is power cycled. This is extremely helpful because, in principle, an extra RFM
monitoring node to diagnose the bucket selection program can be commissioned without
affecting the beam operation.
Besides the high-speed data-sharing of the RFM module, the network interrupts delivering function is utilized to implement the control logic. After finishing the bucket
44

Beam Gate Control

Figure 3.14: Bucket selection system with three functional nodes and one monitor
node.

selection delay calculation, the CCB can send an interrupt to the MTS and the RFM
module at the MTS can generate the VME interrupt to start the injection control process
after receiving the network packets.

3.4

Beam Gate Control

The beam gate system, which integrates with the timing system, extends the flexibilityof a stable injection to the SuperKEKB because it provides the ability to disable thetrigger of some crucial hardware without needing to stop the timing signal [56]. There
are occasions when the beam delivery should be prohibited or some devices should avoid
blank firing to save the hardware lifetime. Thus, the “scheduled pause” or “immediateclose” operation should be provided [38, 57]. For example, the “scheduled pause” option for electron gun is demanded during the injection pattern switch process since thepreparation event timing signal is wrongly sent out to the newly-set injection pattern
and the erroneous trigger should be canceled by masking with “beam gate close” signal.
A detailed description of this situation is introduced in Section 4.1. The “immediateclose” is required for the beam abort system when some emergent circumstances happen,
such as earthquake or beam loss.
The DBus feature of the event module is utilized to deliver the beam gate signal. The
DBus accepts 8 TTL inputs that are then converted into one-byte data and transferred
45

Chapter 3. Overview of Timing System at KEK LINAC
TargetLER GunDR Injection Kicker
DR Injection Septum
DR Extraction Kicker
DR Extraction Septum
LER Injection Hardware
HER GunHER Injection Hardware

DBus bit
None
Upstream EVG DBus bit4
Upstream EVG DBus bit5
Downstream EVG DBus bit4
Downstream EVG DBus bit5
Downstream EVG DBus bit1
None
Downstream EVG DBus bit3

Table 3.5: Summary of beam gate signals.

through an event link with the speed of 57 MHz, i.e., half of the event clock. The actual
trigger generation at local EVRs depends on the event code receiving as well as thestatus of specific DBus bit through the “AND” logic gate. The “AND” circuit assuresthat the pulse is sent to hardware only if the beam gate is “open”.
The beam gate scheme is advantageous to the DR operation. We have mentioned that
two EVGs are used to perform the DR injection and extraction. Consequently, two EVGs
deliver different beam gate statuses with their DBus circuit. The DBus bit informationis shown in Table 3.5. The beam gate system is also well-integrated with EPICS througha dedicated “bgate” EPICS record. The “bgate” record receives the beam gate statusfrom Belle II and SuperKEKB.

46

Chapter

4
Requirement of Timing System at
KEK LINAC
4.1

PPM

The fundamental features of the timing system which include the RF synchronization
and bucket selection have been discussed in Chapter 3. However, there exist several
special requirements for the timing system at KEK LINAC. One of these requirements
comes from the pulse-to-pulse modulation (PPM) process.
Several concepts should be clarified before discussing the PPM. As Fig. 4.1 shows, every
pulse includes several event codes for controlling the RF gun, the kicker or septum
magnet, klystron, and preparation event code for the beam mode of the next pulse. A
fixed-length beam mode that is written into the EVG sequence RAM is defined as an
injection sequence which is significant for the implementation of sequence shift. For
example, a 4 pulses sequence and a 2 pulses sequence are shown in Fig. 4.1. Whereas
the sequence only includes part of the beam modes, all beam modes consist of a basic
operation repetition unit called an injection pattern. The injection pattern can beseparated into several sequences to increase the flexibility of the EVG setting. The
47

Chapter 4. Requirement of Timing System at KEK LINAC
injection pattern plays back continuously until an operator, or an automatic injection
program changes the pattern.
Sequence
RAM

Event
Code

Delay of
Event clock

1

0x20

500

2

0x2a

1000

3

0x24

1001

4

0x3c

2000

…

…

…

HER

PF

DR injecon

PF-AR

DR extraconand LER injeconNo-injecon

20 ms pulse

4-pulses sequence

2-pulses sequence

Beam Injecon pa!ern

Figure 4.1: Injection pattern, sequence, beam mode, and event codes.

4.1.1

Simultaneous Injection
Event-based
Control System
Every
20 ms

e- GunARC

PF Injectione (2.5GeV, 0.2nC)

e- GunARC

Damping ring

SuperKEKB-LER Injectione(3.5GeV, 10nC)
e+ Targete+ (4GeV, 4nC)

e- GunARC

SuperKEKB-HER Injectione (7GeV, 4nC)
e- GunARC

PF-AR Injection
e (6.5GeV, 0.2nC)

Figure 4.2: PPM operation for 4 (+1) rings at LINAC [3].

The event timing system is required to perform the simultaneous injection to several
rings. The event codes and their relative delays are basically fixed for accelerators witha single kind of beam mode. However, it is significant at multi-accelerator facilities, such48

PPM
as KEK LINAC, to switch the beam mode quickly because different beam modes areused. The accelerator devices need to be capable of pulsed operation while the trigger
signals and control parameters derived from the timing system should change accordingly
based on the beam repetition rate (BRR). The 50 Hz PPM successfully shares the
LINAC between 4 destination rings (PF, PF-AR, and SuperKEKB HER/LER) and anintermediate DR for LER with quite different energies and bunch charges (See Fig. 4.2).
The beam properties of 4 (+1) target rings of LINAC is shown in Table 4.1. By changing
hundreds of parameters through PPM, the simultaneous top-up injection to 4 rings isaccomplished to contribute to the physics experiment. The PPM at LINAC is achieved
through the event-based control system which manages the injection pattern, generates
different event codes for different beam modes, and supplies trigger signals to accelerator
components with specific delays.
Direction
SuperKEKB-LER
SuperKEKB-DR
SuperKEKB-HER
PF
PF-AR

Particle
e+
e+
e−
e−
e−

Energy (GeV)
4.0
1.1
7.0
2.5
6.5

Charge (nC)
4.0
4.0
4.0
0.2
0.2

# of bunches
2
2
2
1
1

Table 4.1: Beam properties of 5 rings.

4.1.2

Beam Mode and Injection Pattern

The PPM is conducted every pulse which represents different kinds of beam modes. At
LINAC, a total of 12 beam modes are defined which include 5 beam modes for normal
beam operation, 5 beam modes for corresponding beam study, one beam mode for “noinjection mode (NIM)” and one for “no trigger mode (NTM)”. The beam modes definedat LINAC are shown in Table 4.2. The KBE and KBP mode is the most frequently usedbeam modes for electron beam and positron beam, respectively. Both NIM and NTM
mode prohibits the beam generation from the particle source and provides trigger signals
for the klystron. The difference is that the former mode is used to fill up the empty
pulses of the injection pattern and the latter beam mode is set during the initialization
period of the timing system and provides a less-frequent signal to warm up the klystron.
The beam-mode-dependent event codes are arranged in a series of sequences and transferred in a single pulse every 20 ms. Several beam modes constitute an injection pattern
49

Chapter 4. Requirement of Timing System at KEK LINAC

Figure 4.3: The GUI of IP-GEN program.

Beam Mode
KBE
KBP
PFE
QFE
ARE
JBE
JBP
RFE
SFE
ZRE
NIM
NTM

Event codes
30∼39
40∼49
50∼59
60∼69
70∼79
130∼139140∼149150∼159160∼169170∼179180∼189190∼199

Meaning
HER injection
LER injection
PF injection
PF injection
PF-AR injection
HER injection study
LER injection study
PF injection study
PF injection study
PF-AR injection study
No injection mode
No trigger mode

Table 4.2: Beam modes and event codes defined at KEK LINAC.

that is produced by a software named injection pattern generator (IP-GEN). The IPGEN reads the beam mode frequency values specified from downstream rings and/or
human operators, and then it generates the real injection pattern with a length up to 10s (500∗20 ms) through some rules such as the pre-assigned beam mode priorities. The
location of each beam mode inside the injection pattern can also be manually configuredby the operator. All the beam modes inside an injection pattern are delivered one by one
and the whole pattern is repeated until a new pattern is set at the end of the previous
pattern. An example of the injection pattern is shown in Fig. 4.3. The 5 Hz KBE mode50

PPM
and 1 Hz QFE mode are selected while the other 44 Hz is taken up by the NIM mode.
The injection order of the beam mode can be determined not only by the beam modepriorities but also by the manual selection of the box in the GUI program of IP-GEN.

Figure 4.4: The repetition rate of beam modes in IP-GEN program.

The injection pattern can be automatically changed when the operator changes some parameters through the GUI program (see Fig. 4.4). For example, if the operator decreases
the HER mode repetition rate, the non-injection mode repetition rate would increase
accordingly. Similarly, if the sum of the repetition rates of different beam modes exceeds
the limits, the repetition rate of the lower priority beam mode will decrease automatically. These parameters mainly include the following:

1. RF gun operation mode
2. Kicker magnet operation mode
3. Septum magnet operation mode
4. Beam mode repetition rate
5. Beam mode priority
51

Chapter 4. Requirement of Timing System at KEK LINAC
6. Positron bunch storage time at DR

4.1.3

Dependency between Pulses

It is not an effortless task to change the beam mode pulse-to-pulse because of the existence of some requirements that originates from the injection and extraction hardware,i.e., pulsed kicker magnet at DR. Apart from the main-trigger signal, the kicker magnet
needs some charge time which results in the requirement of the preparation trigger (pretrigger) event. The pre-trigger should be delivered precisely before the main trigger, forexample, 12 ms earlier than the main trigger for the DR kicker magnet with a precisionof 0.1 ns [58]. The main-trigger timing changes every pulse owing to the bucket selection.
Consequently, the pre-trigger timing changes per pulse accordingly.

Figure 4.5: Schematic view of pre-trigger generation.

The logic used for pre-trigger generation are shown in Fig. 4.5. At first, it is necessary
to calculate the main-trigger delay Dmain in the current pulse and next pulse basedon which RF bucket is selected by the bucket selection scheme (see Section 3.3). The
pre-trigger timing is denoted as Dpre and can be calculated through the fixed charging
time (Tcharge ) and the main-trigger delay. Since the charging time for the DR kicker
magnet (12 ms) is close to the LINAC BRR, the pre-trigger is produced at the previous
pulse. As a result, the pre-trigger for “pulse #2” is generated at “pulse #1”. There are
two kinds of methods to generate the pre-trigger signal and they are demonstrated as in52

AC50 Synchronization
Eq. 4.1 and Eq. 4.2, respectively. The number “20” in the equations represents 20 ms
and it is intuitive to derive the equation from Fig. 4.5.
Both delay values of pre-trigger are calculated inside the EVG, and the difference isthat Dpre2 value is transferred through the data buffer feature of EVG, and the trigger
delay is set at local EVR while the delay time of Dpre3 is counted by EVG and trigger
is distributed to EVR through a dedicated event code. The advantage of pre-trigger
calculation through Eq. 4.2 is that we could avoid the restriction of uncertainty of Dmain
since Dpre2 timing is dependent on Dmain1 timing. As we have introduced in Section 3.2
before, PF/PF-AR use different RF frequency with LINAC. The main triggers of PF/PFAR injection cannot be calculated precisely since a chance coincidence algorithm between
LINAC RF, and PF/PF-AR RF is utilized. Thus, the PF/PF-AR beam mode must notprecede the LER beam mode if the method in Eq.4.1 is used.

Dpre2 = Dmain2 − Dmain1 + 20 − Tcharge(4.1)

Dpre3 = Dmain3 + 20 − Tcharge(4.2)

Another kind of cross-pulses dependency originates from the DR operation, we will
discuss it later in Section 4.3.

4.2

AC50 Synchronization

As previously stated, the event timing triggering signal comes from AC50. It is usuallynecessary to maintain the beam intensity and quality on the same level for consecutive
triggers. Some devices are sensitive to the AC line phase and might not satisfy thestability requirement when working at different AC line phases. The klystron is a good
illustration of this. Some klystrons use the AC-powered filament or heater to heatthe electron cathode, and the changing AC phase might generate a magnetic field thateventually affects the velocity modulation process of the klystron. Another measurementof the RF power and phase stability caused by the AC power line can be referred to53

Chapter 4. Requirement of Timing System at KEK LINAC
from [59]. Apart from the klystron, the power supply of the pulsed injection magnet
also needs a stable AC phase to achieve the higher precision of magnetic field [4].

Figure 4.6: Charging time of PFN.

Another restriction of trigger interval comes from the klystron modulator. 60 highpower klystron units are installed at LINAC to accelerator the beam. The power supplyof klystron, also known as klystron modulator, uses a charging power supply, a Pulse
Forming Network (PFN), a thyratron switch, and a pulse transformer to provide 44 kV
charging voltage to klystron [60]. The waveform of the charging gate signal in Fig. 4.6
shows that the ordered charging period is 18 ms to supply stable power for klystron.
Therefore, the timing system is required to provide the trigger with an interval of atleast 18 ms.
In the ordinary situation, the AC50 synchronization of the timing system for HER
injection can be accomplished through the flip-flop circuit inside the MRF EVG module.
The output of the synchronized signal is then used for triggering the sequence RAM
which includes the event codes and delays. Both the AC50 synchronization and constrainof 18 ms trigger interval can be achieved. However, the BSC for LER is 22.68 ms, whichcannot coincide with AC50 for every pulse. As Fig. 4.7 shows, the real trigger must
appear in the 2 ms range near AC50 to satisfy both the AC50 trigger and 18 ms pulseinterval restriction. The range of 2 ms is used for bucket selection purposes. This
constrains conflicts with one cycle of the LER injection period.

54

DR Operation

Figure 4.7: Synchronization between AC50 and BSC for LER cannot be achieved
every pulse.

4.3

DR Operation

To increase the luminosity of SuperKEKB, the emittance of the injected positron beam
should be small enough to be accepted in the aperture of the LER. The adoption of a
new collision scheme called “nano-beam” requires the construction of DR [61]. Thus, thetiming system needs to consider the operation of DR. Several new restrictions further
increase the complexity of system implementation.

4.3.1

Dependency between Injection and Extraction Pulse

The pre-trigger of the kicker magnet at DR brings the dependency between subsequent
pulses. Meanwhile, the DR operation brings the dependency between injection pulse
and extraction pulse. At least 40 ms DR storage time is needed to achieve a satisfactory
damping effect. Consequently, two pulses, which include one pulse for DR injection and
one pulse for DR extraction, are needed to fully finish one time of LER injection. We
have mentioned that two EVGs collaborate to control the injection process. Based on
the repetition rate of LER injection and DR storage time, there are three DR operation
modes. These DR operation modes can be categorized like Table 4.3.

55

Chapter 4. Requirement of Timing System at KEK LINAC
Beam Mode
KBP
KBPu
KBPd

Beam Gate
Injection Extraction
Open
Open
Open
Close
Close
Open

Use
Continuous injection
Gun firing and DR injection
DR extraction and LER injection

Table 4.3: DR operation modes.

KBPu mode stands for the upstream LINAC operation for positron beam delivering.
The electron gun is fired, and the electron beam bombards a tungsten target to generate
a positron beam which is then injected into DR through DR injection kicker and septum.
On the other hand, KBPd mode means that stored beam in DR is extracted but there
is no newly injected beam for DR. KBP mode is normally used for continuous injection
to LER which means both extraction and injection are performed in a single pulse.
The delay value of trigger signal in KBPd pulse is calculated at several pulses before, i.e.,
in KBPu pulse, because of the bucket selection process. After deciding the LER bucket
number with the help of either the “BCE” or “star” scheme, the delay for LER injection,
also known as the delay for DR extraction, can be calculated. The DR bucket number
is then derived based on the DR storage time. Finally, the delay for DR injection is
acquired and set in the upstream EVG. After DR storage time has passed, the delay for
LER injection is used for extracting the stored bunch in DR.

4.3.2

DR Storage TimeThe minimal DR storage timing Tstorage is limited to 40 ms while the maximal DR
storage time is decided to owe to another consideration [4]. Because of the hardware
at downstream LINAC, the DR extraction timing must also refer to the AC50 phase.
Note that the DR extraction timing is calculated based on the AC50 in the DR injection
pulse, the extraction timing has a relative drift to AC50 since the AC50 always drifts.
Figure 4.8 shows time difference between DR extraction timing and AC50 measured
in 2018 [46]. The time difference becomes larger when Tstorage becomes longer. The
maximal DR storage time, Tmax , is decided to be 200 ms.

Tstorage = M in(npulse ∗ Trep , Tmax )

56

(4.3)

DR Operation

Figure 4.8: Time difference between DR extraction trigger and AC50.

The 2-pulse injection is implemented by storing bunches of two LINAC pulses in DR to
improve the DR operation efficiency. Both 2-pulse operation mode and LER injection
repetition rate (frep ) affect the real Tstorage . The calculation can be referred in Eq. 4.3.
Table 4.4 lists several calculation examples of DR storage time.
frep [Hz]
50
25
25
12.5
12.5
10
10
5
1

Trep [ms]
20
40
40
80
80
100
100
200
1000

npulse
2
2
1
2
1
2
1
1
1

Tmax [ms]
200
200
200
200
200
200
200
200
200

Tstorage [ms]
40
80
40
160
80
200
100
200
200

Table 4.4: DR storage time is affected by KBP mode repetition rate and 2-pulse
mode.

4.3.3

2-bunch and 2-pulse operation

2-bunch operation is adopted to increase the LINAC operation efficiency since the chargeof high intensity, single-bunched primary electron beam for positron production has
almost approached the beam blow-up threshold due to single-bunch transverse wakefield
effects [62]. To inject two bunches into the DR, the DR kicker needs to supply a magnetic
57

Chapter 4. Requirement of Timing System at KEK LINAC

Figure 4.9: DR kicker magnets are active due to the power supply rising and falling
time of 100 ns.

field with two peaks and the distance should be exactly 96.3 ns. As shown in Fig. 4.9, theDR kicker magnet power supply provides the required bi-peak shape of the magnetic
field. The rising and falling time before and after the bi-peak output will affect thestored bunches when the 2-bunch injection is performing. As a result, the RF buckets,that are at a distance of fewer than 100 ns to stored bunches, should not be selected [4].
Figure 4.10 shows the 2-bunch and 1-pulse operation of DR. The DR storage time is
40 ms and the KBP repetition rate is 25 Hz. During the DR extraction pulse, thestored 2 bunches which are injected two pulses before are first extracted and then two
new bunches are injected into DR. All the DR RF buckets can be selected under thiscircumstance.
Another situation is described in Fig. 4.11. If DR storage time is increased to 80 ms,
the 2-bunch and 2-pulse operation become necessary. Considering the 96 ns (49 RF
buckets) bunch space of 2-bunch beam and 100 ns kicker magnet field rising time (50RF buckets), only 31 DR RF buckets can be selected for the newly injected bunch
during the 2-bunch and 2-pulse operation. For example, if DR bucket “#0” and “#49”are already occupied, newly injected two bunches can only select the range between“#100 (#149 for the second bunch)” and “#130 (#179 for the second bunch)”.
When this restriction comes together with the 2 ms injection window limit caused by the58

DR Operation

Figure 4.10: DR operation with 2-bunch and 1-pulse injection.

Figure 4.11: DR operation with 2-bunch and 2-pulse injection.

klystron modulator, the available LER RF buckets number is also affected. For example,
if we want to inject into LER bucket “#0”, the DR-LER bucket combination for can becalculated based on Eq. 3.1 and Eq. 3.1. There exist a total of 23 BSC for LER cycles
to inject into the same LER bucket. Table 4.5 shows the relation between cycle number,
injection opportunity, delay time and DR RF bucket. All 23 DR RF buckets that can
inject into the LER RF bucket “#0” are listed.
Figure 4.12 shows the time chart of DR bucket selection during 2-bunch and 2-pulse
operation. The AC50 comes in the middle of cycle “#5” and cycle “#6”. The 2 ms
injection window restricts the candidate DR RF bucket number. If we want to inject
into LER bucket “#0” and DR bucket “#0” and “#49” are already occupied, the possible
DR RF buckets are between “#100” and “#130”. However, as Fig. 4.12 shows, only DR

59

Chapter 4. Requirement of Timing System at KEK LINAC
Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Injection opportunity0
5120*15120*25120*35120*45120*55120*65120*75120*85120*95120*105120*115120*125120*135120*145120*155120*165120*175120*18
5120*19
5120*205120*215120*22

Delay [µs]
0
493*1
493*2
493*3
493*4
493*5
493*6
493*7
493*8
493*9
493*10493*11493*12493*13493*14493*15493*16493*17493*18493*19493*20493*21
493*22LER Bucket
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

DR Bucket
0
180
130
80
30
210
160
110
60
10
190
140
90
40
220
170
120
70
20
200
150
100
50

Table 4.5: Injection delay and corresponding DR bucket for LER bucket “#0”.

RF buckets “#80”, “#30”, “#210” and “#160” can be used. Under this circumstance,
the LER RF bucket “#0” cannot be injected into this pulse.

Figure 4.12: The 2 ms injection windows comes together with 2-bunch and 2-pulse
operation.

Note that, this restriction appears not only when 2-bunch and 2-pulse operation is used.
Because of the shape of the DR kicker magnet field, this restriction exists for 1-bunchand 2-pulse operations. The optional DR buckets are 81 [63]. Appendix A.1 shows
the simulation process through a python program. The results are listed in Table 4.6.

60

DR Operation
There are only 2798 LER RF buckets that can be selected for 2-bunch and 2-pulse mode.
Almost half of the LER RF buckets cannot be selected during the operation.
DR,MR
Bunch

1
2

Pulse
1
2
230,5120 80,5120
230,5120 31,2798

Table 4.6: Available RF buckets for DR operation.

61

Chapter5
Implementation of Timing
System at KEK LINAC
5.1

Sequence Shift

We have already mentioned in Section 4.2 that the difficulty in finding the coincidence
between AC50 and BSC for DR and LER every 50 Hz. The basic BSC for DR andLER is 88.19 Hz according to Section 3.3.1 and half of the frequency is used in practicesince it is easy to implement. Thus, 44.1 Hz is used as the real repetition rate for LER
bucket selection. The period of 44.1 Hz is 22.68 ms. As shown in Fig. 3.8, this signal isgenerated from the 508.89 MHz MR-MO and used for the master trigger of MTS.
One possible solution is to utilize the method called “sequence shift” by grouping several
strict 50 Hz pulses as a sequence. The sequence itself is triggered every 22.68 ms andthe actual event timing triggers, which follow the AC50 phase, happens at every pulse
inside a sequence. Furthermore, two sequences of uneven length switch alternately toadjust the arriving timing of AC50.

63

Chapter 5. Implementation of Timing System at KEK LINAC

Figure 5.1: Time difference between BSC and 50 Hz.

5.1.1

8/9 Pulses Sequence Shift

Figure 5.1 shows the time difference between BSC and 50 Hz. The distance between
50 Hz trigger point and 44.1 Hz point can be calculated through Table 5.1. After 8
50-Hz pulses, the 44.1 Hz signal comes 1.25 ms earlier than the next 50 Hz pulse. In
contrast, after 9 50-Hz pulses, the 44.1 Hz signal comes 1.4 ms later than the next 50
Hz pulse. As a result, all pulses inside an 8/9 pulses sequence can find the coincidence
position with 44.1 Hz based on the fixed pulse length and pulse number. For example,
the injection into LER at pulse “#2” (see Fig. 5.1) can be done by setting the sum of
bucket selection delay value and 2.68 ms as the real trigger delay value.
# of 50 Hz pulse
1
2
3
4
5
6
7
8
9

Sequence length [ms]
20
40
60
80
100
120
140
260
180

Distance [ms]
+2.68
+5.36
+8.04
+10.72
-9.28
-6.6
-4.02
-1.25
1.4

Table 5.1: The time interval between 50 Hz pulse and 44.1 Hz pulse.

To deliver the injection triggers on the same phase of AC50, the TDC is used to assure
the arrival time of AC50. The TDC receives the start signal at the pulse start point every
20 ms. The stop channel uses AC50 which originates from the MTG module. Thus,
the AC50 delay is measured by the TDC module every pulse, as shown in Fig. 5.2. We
manage the length of the sequence for modulating the AC50 position. At the end of the
9 pulses sequence, the next sequence is launched 1.4 ms later and that means the startsignal of TDC comes 1.4 ms later. In other words, the AC50 comes 1.4 ms earlier in the
new sequence compared with the old 9 pulses sequence. In practice, the AC50 should64Sequence Shiftalways appear in the middle of every pulse to keep a stable operation, and this can beaccomplished through the sequence shift algorithm (see Section 5.1.2).

Figure 5.2: AC50 position manipulation by sequence shift.

Figure 5.3 shows the overall hierarchy of the timing chart at MTS. The injection patternis divided into two kinds of sequences with 8/9 pulses. All sequences are trigged by a44.1 Hz signal transferred from MR to synchronize with the BSC for DR and MR. Eachpulse is strictly 20 ms and the main timing trigger happens together with the AC50
phase in a 2 ms window. Inside one 11.34 ms cycle, two fragment methods divide thecycle as 23 pieces of 493 µs or 512 pieces of 22.15 µs. As a result, the bucket selection
delay for DR and MR can be acquired easily by two fragment methods. This processrepeats after the sequence shift.

5.1.2

Sequence Shift Algorithm

During the start period of every pulse, hundreds of PPM parameters are changed toprepare the event delivery. Thus, the AC50 signal is required to come in the middle ofevery pulse to avoid interference from software processing. The sequence shift algorithm
serves as a method to decide the next sequence length and its purpose is to keep theAC50 sit in the middle of every pulse.
Sequence typeType A
Type B

Length89Shit Value
1.25 ms-1.4 ms

Table 5.2: Two kinds of sequence type.

65

Chapter 5. Implementation of Timing System at KEK LINAC

Figure 5.3: Logic of sequence shift.

The implementation of sequence shift requires several modules to provide adequate information. An MTG module with a voltage comparator circuit was manufactured togenerate the AC50 signal at the fixed phase from the AC power line. A time-to-digitalconverter (TDC), which receives the “TDC start” and “TDC stop” signal, is used tomeasure the AC50 delay time with a resolution of 1 ns [2].
44 Hz BSC

44 Hz BSC

44 Hz BSC

160 ms (20 * 8)

180 ms (20 * 9)

158.75 ms (22.68 * 7)
Sequence #1
8-pulse sequence

1.25 ms

181.4 ms (22.68 * 8)
Sequence #2
9-pulse sequence

1.4 ms

2
1𝑇

1
1𝑇

AC50

3
1𝑇

AC50 arrives timing
becomes 1.4 ms early‘TDC start signal’ triggers
1.25 ms early, AC50 arrival
timing becomes 1.25 ms late𝑦𝑥𝑇Sequence Shift
AC50

AC50

AC50

20 ms

20 ms

20 ms

1
1𝑇

1
2𝑇

1
3𝑇

TDC stop

Δ𝐴𝐶 : 𝐴𝐶 𝑑𝑟𝑖𝑓𝑡 𝑣𝑎𝑙𝑢𝑒
Δ𝐴𝐶 = 12𝑇 − 11𝑇

Measured AC50 value at pulse “#x” of sequence “#y”

𝑦𝑥𝑇𝑒𝑠𝑡 Estimated AC50 value at pulse “#x” of sequence “#y”

Start at first pulseof a sequence

𝑆𝑦

Length of sequence “#y”

𝑆𝑦𝑦

TDC start

Sequence #3
8-pulse sequence

Use 1𝑇 to estimate

𝑦+1
1𝑇𝑒𝑠𝑡

𝒚+𝟏
𝟏𝑻𝒆𝒔𝒕 < 𝑻𝒓𝒆𝒇noyes
𝑺𝒚+𝟏 = 9

𝑺𝒚+𝟏 = 8

Shift value at the end of sequence9

1.25 ms 1.4 ms

Example:Use 11𝑇 to calculate 21𝑇𝑒𝑠𝑡
2
1
1𝑇𝑒𝑠𝑡 = 1𝑇 + 1.25
Then, compare estimated AC50 value with referencevalue
2
1𝑇𝑒𝑠𝑡 < 𝑇𝑟𝑒𝑓
Then, Length of sequence #2 is set to 9

Figure 5.4: The schematic view of the sequence shift.

66

8Sequence Shift
The schematic view of 8/9-pulse sequence shift is shown in Fig. 5.4. The sequence length
was selected to 8 pulses and 9 pulses in 2015 [30]. Inside the 8/9-pulse sequence, therequirements for synchronizing to both 44 Hz BSC and AC50 are fulfilled at every pulse.
The timing system starts with the 44 Hz BSC which serves as the fiducial point of bucket
selection. Note that 44 Hz (i.e., 22.68 ms) rather than 88 Hz BSC is used because it
is close to 20 ms and simplifies the system design. The pulse length is ideal 20 ms anddifferent beam properties are modulated pulse-to-pulse. The AC50 arrival delay at every
pulse is measured by the TDC module and is used for generating an AC50-synchronizedbeam timing signal. The range of AC50 arrival delay values is from 0 to 20 ms. The
time distance between the fiducial point of bucket selection and AC50 in every pulse
can be easily calculated based on the pulse number. For example, if the AC50 arrival
delay measured in the third pulse is 10 ms, the overall bucket selection delay is 50 ms.
Then, the DR and LER bucket number can be acquired through the formulas describedin [46].
As shown in in Fig. 5.4, after an 8-pulse sequence, the discrepancy between ideal 20
ms pulse and 44 Hz BSC is 1.25 ms. The sequence “#2” is launched 1.25 ms earlier toresynchronize with 44 Hz BSC. Accordingly, the AC50 arrival delay at the first pulse of
sequence “#2” becomes 1.25 ms later because the “TDC start” signal comes 1.25 ms
earlier. Similarly, the sequence “#3” is launched 1.4 ms later after a 9-pulse sequence.
As the AC50 always drifts, the AC50 arrival timing can be out of the boundary in apulse and break the synchronization requirement. The sequence shift algorithm is thenused for compensating the AC50 drift and keeping AC50 arrival timing appear in the
middle of a pulse. To explain the sequence shift algorithm, Let xy T denote the AC50
arrival delay which is measured by TDC at pulse “#x” of sequence “#y’, xy T est denotethe estimated AC50 value at pulse “#x” of sequence “#y’, Sy denote length of sequence“#y” and Tref denote the reference value for AC50 arrival delay. The value of Sy iseither 8 or 9 which corresponds to AC50 shift value of 1.25 ms and 1.4 ms, respectively.
The value of Tref is usually selected to be around 10 ms. The AC50 drift value ∆AC
can be expressed by the discrepancy of the AC50 arrival delay values for two continuous
pulses.
The main purpose of sequence shift algorithm is to decide the length of next sequenceand keep xy T be close to Tref . For example, the type of sequence “#2” is decided at
67

Chapter 5. Implementation of Timing System at KEK LINAC
the first pulse of sequence “#1”. The estimated AC50 arrival timing 21 T est is derived
from the TDC measurement value 11 T and sequence shift value (i.e., 1.25 ms). If 21 T est issmaller than Tref , the type of next sequence is selected as 9-pulse sequence; otherwise,
8-pulse sequence is selected.

Fluctuation of AC50

After 8-pulse
sequence, AC50
jumps 1.25 ms up
After 9-pulse
sequence, AC50
jumps 1.4 ms down

Figure 5.5: Example of sequence shift under two kinds of AC50 frequencies.

Figure 5.5 illustrates the example sequence shift under different AC50 frequencies. Everypoint represents the measured AC50 arrival delay in an injection pulse. The AC50 drift
value ∆AC is 40 µs and 80 µs for the AC line frequency of 49.9 and 49.8 Hz, respectively.
The initial AC50 arrival timing is 9.5 ms and the AC50 reference value Tref is 9.85 ms.
Two different decisions on the length of the next sequence are made at the first pulseof the second sequence. Larger AC50 arrival timing caused by fluctuation of AC50 iscorrected by sequence shift. Consequently, the AC50 arrival delay value oscillates aroundthe Tref . The long-term stability of the 8/9-pulse sequence shift was studied in 2015
and loss of triggers was not observed [30].

5.1.3

16/18 Pulses Sequence Shift

According to Section 4.3.2, the maximal DR storage time is chosen to be 200 ms. The
maximal pulse discrepancy between DR injection and DR extraction is also 200 ms which
is longer than the sequence length (i.e., 160 ms for 8 pulses sequence and 180 ms for 9
pulses sequence).

68

Structure of Main Timing Station

Figure 5.6: The conflict between 8/9 pulses sequence and DR storage time.

Figure 5.6 shows the problem when DR storage time of 200 ms is utilized. Both the
DR injection and extraction delay are calculated in the DR injection pulse to keep thesynchronization between DR and LER. If DR is injected at the end pulse of sequence“#1”, the extraction timing happens 200 ms later, which is the first pulse of sequence“#3”, should be determined also at the injection pulse. However, the sequence type of“#3” will not be decided until the delivery of sequence “#2”. As a result, the extraction
delay for MR is uncertain. Finally, the sequence length is enlarged to 16/18 pulses
sequence to handle the 200 ms DR storage time and the sequence shift value changes to
2.8 ms and 2.5 ms.

Structure of Main Timing Station
44 Hz

AC line

20 ms

20 ms

20 ms

AC50

Readback

44 Hz

16/18 pulses

44 Hz

AC50

5.2

20 ms

EVG

EVR

BS
delay
Upstream
Linac

Downstream
Linac
EVR

Readback

Readback

3.5 msdelay

Seq Trigger

EVG

Readback

Readback

AR
Trigger

3.5 msdelay

Seq Trigger from PF/AR

EVG

PF
Trigger

Seq Trigger

AR
Trigger Trigger

TDC

TDC Start
3.5 msdelay

AC50
TDC Stop TDC Start PF

AC50

Preparation
event

Seq Trigger

MTG

AC50

Main event

3.5 msdelay

EventdeliveryFigure 5.7: Schematic view of MTS.

69

Chapter 5. Implementation of Timing System at KEK LINAC
Figure 5.7 shows the structure of MTS. Three EVGs and two EVRs are utilized togenerate event codes and control the injection procedure [64]. The MTG and TDC
module provide the ability to measure the AC50 arrival timing and supply the AC50
value for the decision-making of the sequence shift algorithm.
One upper-level EVG is triggered by the 44.1 Hz signal transmitted from SuperKEKB
to synchronize the injection procedure between DR and LER. It carefully separates
the injection pattern into 16/18 pulses sequence and delivers the main event and preevent to the middle EVR every 20 ms. A fiber-based event link is used for event codestransmission. The main event and pre-event are then used for controlling two lower-level
EVGs.
The middle EVR is responsible for generating pulses from the main event and preevent. The pulse generated on the arrival of the main event triggers both the TDC
and sequencer of two lower-level EVG. The trigger for TDC happens immediately andthe trigger for two lower-level EVG happens after a 3.5 ms delay. This 3.5 ms delay isachieved by the pulse generator in EVR and this period is used to reserve the running
time of beam mode change logic. The pre-event changes the contents of the sequencer
called “software sequencer”, which include beam mode of the next pulse as well as thesequencer trigger source. Note that, these changes only happen at the software level andneed to be loaded later into the “hardware sequencer” to take effect.
Two lower-level EVGs send 12 or 13 event codes every pulse to all local EVRs all over
the accelerator. One of the EVGs controls the upstream LINAC hardware while anothermanages the downstream LINAC. The events are changed based on the beam mode arrangement and the bucket selection delays are read from the RFM module which arecalculated two pulses before. The trigger source of two lower-level EVGs switches isbased on the beam mode. If the current beam mode is PF/PF-AR, then the trigger
directly comes from the change coincidence between LINAC RF and PF/PF-AR revolution frequency. Other beam modes use the output pulse from EVR as a sequencer
trigger.
A local EVR receives the event codes and sends a “readback” to upper-level EVG toassure that current event codes are successfully delivered. This “readback” signal rearms
the “hardware sequencer” of two lower-level EVGs, whose contents are already changedon the pre-event triggering several milliseconds before. Then, these event codes inside70

RF Phase Shift of LINAC
the “hardware sequencer” are sent out with defined delay when trigger signals come in
the next pulse. It also triggers the processing of bucket selection of the next-next pulse
by sending a network interrupt to the CCB node in SuperKEKB through the RFM
module.

Figure 5.8: Sequence of 3 important triggers happening in one MTS pulse.

Figure 5.8 shows the sequence of 3 important signal for EVG sequencer. The content
of “software sequencer” is changed upon the pre-event. Later, the real sequence trigger
signal sends out the event codes in the “hardware sequencer”. After the local EVR
confirms the successful delivery of the event, the “readback” signal loads the content
from “software sequencer” to “hardware sequencer”.
With the help of this architecture, the requirements originate from double-ring bucket
selection and AC50 synchronization are fulfilled.

5.3

RF Phase Shift of LINAC

5.3.1

Implementation of RF Phase Shift

The constriction discussed in Section 4.3.3 can be handled through a method like asequence shift. By shift, the RF phase of “downstream LINAC”, the extraction opportunities for bunches stored in DR are increased. Figure 5.9 shows the schematic diagram
71Chapter 5. Implementation of Timing System at KEK LINAC

Figure 5.9: RF phase shift of downstream LINAC.

of RF phase shift. The coincidence relationship between three RF frequencies is listed.
All the event timing system trigger signals should be delivered based on the 114.24 MHz
event clock, i.e., 8.75 ns. In the event cycle of the DR/MR RF clock, a bucket can be
filled. The coincidence points between DR/MR RF and LINAC RF appear every 49
cycles of the DR/MR RF clock or every 11 cycles of the event clock. Without RF phaseshift, the distance between two contiguously injected RF buckets is 49. After bucket“#0” in DR/MR can is filled at the trigger point, the next injection opportunity appears
at 96.3 ns later.

Figure 5.10: Schematic view of RF phase shift in downstream LINAC.

72

RF Phase Shift of LINAC
To increase the coincidence relation between ring RF and LINAC RF, we can shift
LINAC RF to synchronize with ring RF again. As shown in Fig. 5.9, by shifting 220.4◦
of LINAC RF, RF bucket “#1” is synchronized with LINAC RF again and can beextracted into LINAC from DR. The time interval between event clock trigger point
and real beam timing becomes 1.965 ns. Similarly, if we generate a trigger signal at
one event cycle later (i.e., 8.75 ns later), RF bucket “#4” and “#5” can be extracted
from DR into LER by shifting LINAC RF -0.893 ns (161.633◦ ) and 1.072 ns (22.04◦ ),respectively.
Consider LER bucket “#m0 ” injection example in Section 4.3.3 again, if we want toinject into LER bucket “#0” and DR buckets “#0” and “#49” are already occupied,
range of optional DR buckets are between “#100” and “#130”. However, only “#80”,“#30”, “#210” and “#160” are available in 2 ms injection windows. As Fig. 5.10 shows,the normal injection points without RF phase shift allow us to inject into LER bucket“#0” through DR bucket “#30”. By shifting the RF phase and generator the trigger
for one event clock (8.75 ns) later, DR bucket “#5” can be extracted into LINAC andinjected into LER bucket “#35”. Based on the combination of DR bucket “#5” andLER bucket “#35”, the current cycle of BSC for LER only can be determined throughTable 3.4. Thus, the timing for LER bucket “#0” through DR bucket “#120” is acquired.
DR bucket “#120” is also available under the restriction of 2 ms injection window and2-bunch and 2-pulse operation. The overall effect is also demonstrated in Fig. 5.11.
The BSC cycle is shifted when the “downstream LINAC” RF phase is shifted, and theirrelation can be calculated.

Figure 5.11: Equivalent view of BSC cycle shift by RF phase shift.

73Chapter 5. Implementation of Timing System at KEK LINAC
The calculation of new LER-DR bucket combination is described in Fig 5.12. After
deciding the LER bucket number M0 by bucket selection scheme, the bucket selection
delay clock0 and DR bucket number D0 are calculated through the method described in
Section 3.3.1. Then we check whether D0 is available during the 2-bunch and 2-pulse
operation. If D0 can be selected, the LER injection is successfully performed without
RF phase shift in “downstream LINAC”. On the contrary, the RF phase in “downstream
LINAC” is shifted to coincide with RF bucket M0 + n and D0 + n. The corresponding
event timing shift value is k cycles of event clock Tevent , i.e., k ∗ 8.75 ns. Note that,
there are small time differences, which is denoted as ∆T between beam trigger andevent timing trigger. We will discuss the impact of ∆T later. According to the bucket
combination of M0 + n and D0 + n, it is easy to find the delay value Delay[M0 + n] basedon Table 3.4. The delay value Delay[M0 + n] represents the time interval between LERDR combination of (0, D1 ) and (M0 + n, D0 + n). Similarly, the delay value Delay[M0 ]represents the time interval between LER-DR combination of (0, D1 ) and (M0 , D2 ).
What we finally want to know is the DR bucket D2 and the bucket selection delay
clock1 . By setting delay value of clock1 , LER bucket M0 can be injected through DR
bucket D2 . Then, we could check whether D2 is available during 2-bunch and 2-pulse
operation.

Figure 5.12: Calculation process of new DR bucket under RF phase shift.

clock1 = clock0 + Tevent ∗ k − Delay[M0 + n] + Delay[M0 ]

D2 = M OD

74

clock1 ∗ 49
, 230
96.3

(5.1)



(5.2)

RF Phase Shift of LINAC
The delay value of clock1 can be calculated through Eq. 5.1 and DR bucket D2 can becalculated through Eq. 5.2.

5.3.2

Balance of DR Bucket Selection

Although another DR RF bucket can be selected with the help of RF phase shift, there
are some compromises on the decision of the extent of phase shifting, which mainly
includes,• Time difference ∆T ,• Injection window,• optional DR bucket numbers.

Figure 5.13: Optional DR buckets numbers.

Figure 5.13 shows the elective DR RF bucket numbers are affected by ∆T and injection
window size. Five injection window sizes, which include 493 µs, 986 µs, 1479 µs, 1972
µs and 2465 µs, are displayed. The source data can be acquired in Appendix A.2.
The time difference ∆T between DR/LER RF phase and event clock is inevitable if the“downstream LINAC” RF phase is shifted. Most hardware at “downstream LINAC”
75

Chapter 5. Implementation of Timing System at KEK LINAC
accepts the time difference and for those needing high precision trigger signal, the finedelay output channel of EVR must be used to provide 20 times finer delay than the114.24 MHz event clock. Apart from the trigger signal, the impact on beam energy
and injection efficiency must be considered. By increasing ∆T , the coincidence points
between DR and LINAC increase. But the time difference between beam trigger andevent timing signal is also enlarged.
Other elective DR buckets can be acquired if we add or subtract some BSC cycles forLER (i.e., 493 µs). For example, Fig. 5.11 shows that DR RF bucket “#120” can beused to inject into LER RF bucket “#0” after RF phase shift. Meanwhile, DR bucket“#70” is also optional if we wait for 493 µs, and bucket “#170” is optional if the trigger
starts 493 µs earlier. Since the injection window restriction is 2 ms, four DR RF buckets
distributed in four cycles are all optional. However, the larger the injection windows
are, the more severe the injection trigger fluctuates.
To inject into the same LER RF bucket, 23 DR RF buckets can be used in total. FourDR buckets are elective without RF phase shift or with RF phase shift. All the nonrepetitive buckets consist of the optional DR buckets list. The perfect situation is thatall 23 DR buckets are elective. The bucket restriction for 2-bunch and 2-pulse operations
is 31. That means if we want to select one of the DR buckets locates inside the 31 buckets
range, the optional buckets should have a bucket distance of at least 30.
Considering all the three factors, the optional RF phase types are listed in Table 5.3 andTable 5.4. To simplify the explanation, the calculation is based on the injection point of
LER bucket “#0” through DR bucket “#0”. Table 5.3 shows all the RF shift types withthe restriction of 2.144 ns maximal ∆T value. The ∆T of RF shift types between “#0”and “#18” are less than 1.608 ns while the last 6 RF shift types are larger than 1.608 ns.
Since the RF phase shift itself will generate a variation at a size of 493 µs, the maximal
injection window becomes 1476 µs. If we want to select all 23 combinations in one pulse,the ∆T of 2.144 ns becomes necessary. The advantage of selecting all 23 combinations in
one pulse is that we can separate the DR injection pulse and extraction pulse thoroughly.
The DR extraction delay timing is calculated in the extraction pulse rather than during
the injection pulse and the maximal DR storage time limit is removed.
Table 5.4 shows all the optional DR buckets under different RF phase shift. The “nearest
cycle” represents the 493 µs cycle that is nearest to the AC50 and “Cycle-1” means one
76

RF Phase Shift of LINAC
RF Shift Type
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Bucket Offset
+0
+4
+5
+9
+13
+14
+17
+18
+22
+23
+26
+27
+31
+32
+35
+36
+40
+44
+45
+1
+8
+10
+39
+41
+48

Event Clock Offset
+0
+1
+1
+2
+3
+3
+4
+4
+5
+5
+6
+6
+7
+7
+8
+8
+9
+10
+10
+0
+2
+2
+9
+9
+11

∆T [ns]+0-0.893196+1.07183+0.178639-0.714556+1.25047-1.60775+0.357278-0.535917+1.42911-1.42911+0.535917-0.357278+1.60775-1.25047+0.714556-0.178639-1.07183+0.893196+1.965115-1.786468+2.143762-2.143762+1.786468-1.965115

Table 5.3: RF bucket offset, event clock offset and ∆T for different RF phase shift
type.

BSC for the LER cycle before. If we set the injection window size as 986 µs, 19 out of
23 RF buckets can be selected.

77

Chapter 5. Implementation of Timing System at KEK LINAC

RF Shift Type
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Cycle-2
+100
+80
+190
+170
+150
+30
+130
+220
+220
+100
+150
+30
+10
+120
+220
+100
+80
+60
+170
+210
+60
+50
+200
+190
+20

Cycle-1
+50
+30
+140
+120
+100
+210
+80
+190
+170
+50
+100
+210
+190
+70
+170
+50
+30
+10
+120
+160
+10
+0
+150
+140
+220

Nearest Cycle
+0
+210
+90
+70
+50
+160
+30
+140
+120
+0
+50
+160
+140
+20
+120
+0
+210
+190
+70
+110
+190
+180
+100
+90
+170

Cycle+1
+180
+160
+40
+20
+0
+110
+210
+90
+70
+180
+0
+110
+90
+200
+70
+180
+160
+140
+20
+60
+140
+130
+50
+40
+120

Table 5.4: Optional DR buckets for different RF phase shift type.

78

Cycle+2
+130
110
+220
+200
+180
+60
+160
+40
+20
+130
+180
+60
+40
+150
+20
+130
+110
+90
+200
+10
+90
+80
+0
+220
+70

Chapter

6
Reliability Analysis of Timing
System
6.1

System Requirements

Figure 6.1: Timing system requirements.

79

Chapter 6. Reliability Analysis of Timing System
We have introduced the function requirements of the timing system at LINAC and thearchitecture of timing system implementation. The overview of system requirements issummarized in Fig. 6.1. The AC50 synchronization requirement brings the sequence
shift method which compensates for the effect of AC50 drift, and the sequence lengthis decided to be 16 and 18 owing to mildly AC50 drift. Another limit caused by bucket
selection in DR 2-bunch and 2-pulse operation can be solved by RF phase shift indownstream LINAC. By applying the RF phase shift, the dependency between DR
injection and LER injection is removed and consequently, the maximal DR storage time
limit is removed. It increases the reliability to switch the sequence length from 16/18 to
8/9 since the compensation frequency for AC50 becomes twice fast.
The system requirements that originate from hardware and software-based implementations which include PPM, sequence shift, and bucket selection eventually increase thesystem complexity. Long-term stability is a crucial factor for a reliable timing systemat LINAC.
The timing system, which satisfies the requirements to operate the DR for the positron
injection, was installed and commissioned in 2018 [46]. As the growth of the systemcomplexity comes from the bucket selection and 16/18-pulse sequence shift, several failure modes of the timing system are observed. An event code log system, which monitorsand saves all event codes received in EVR, is developed to diagnose the failure modes
in 2019 [65]. The severity of some timing system failures is minimal because the trigger
signals for devices are masked and inhibited by beam gate system [56] when some abnormal events are transmitted. On the other hand, a timing system failure that stops
the delivery of event codes for a few minutes is severe for physics runs because it usuallytriggers the beam abort system to dump all the beams at SuperKEKB. It normally takes
10 minutes for the operator to check the status of the accelerator and restart the injection. Thus, it is urgent and significant to understand the failure cause and stabilize theoperation. To further analyze the failure mode and failure mechanism, data acquisitionof timing system is developed to diagnose the system and identify the failure cause.

80Data and Information Acquisition

6.2

Data and Information Acquisition

Failure location identification and failure data monitoring are the fundamental concerns
when performing failure mode analysis. The event code log system is beneficial tounderstand what happens during the failure.

6.2.1

Event Code Log

Figure 6.2: Two EVRs are used for event code log.

The most intuitive method for understanding the failure mechanism of event delivery
is to log all the event codes and timestamps in local EVR. Since two sets of eventcodes are transferred to upstream LINAC and downstream LINAC hardware, two local
EVRs, i.e., upstream EVR and downstream EVR are necessary to completely monitor
the event code delivery status. Figure 6.2 shows the hardware of the event code log
system. It consists of the MVME-5500 on-board CPU controller with the operation
system of VxWorks 6.8.3 and two VME-EVR-230-RF modules from the MRF company.
The EPICS-based timing system allows the operator to modify the timing parametersand monitor system status remotely. The device support for MRF event timing modules
called “mrfioc2” is maintained by the EPICS community and provides the interface
81Chapter 6. Reliability Analysis of Timing System
between hardware and EPICS record. For example, the delay time and width for the
output pulse of an EVR can be changed through “Channel Access” commands. The
event codes received in an EVR are put into the event FIFO memory with the 64-bit
timestamp information. The 80-bit wide FIFO can hold up to 511 events. The driverprogram of “mrfioc2” writes event code from the FIFO into the “VAL” field of an EPICS
record and sets the “TIME” field of the record as the timestamp from the register upon
the trigger of the VME interrupt generated by EVR. This record can be monitored
through the “camonitor” command.
The difficulty to log all the event codes through the record provided by “mrfioc2” liesat the processing speed of CA transmission. The minimal interval between event codesis 8.75 ns since the event clock is 114.24 MHz. According to the IOC performancemeasurement in cite2005xuRealTimePerformance, the latency of EPICS IOC is at the
microsecond level. Thus, it is reluctant for event code logging by directly monitoring
the EPICS IOC. Another architecture for CA-based event code log system is describedin Fig. 6.3. By grouping the event codes into a “waveform” record, the CA transmissioninterval is enlarged. Every time the record triggered by EVR is processed, it sends
the event code and timestamp to the “waveform” record. To store the event codeand timestamp information inside the “waveform” record, the EPICS device driver ismodified. With the help of a new device driver, the “waveform” record, which contains
1600 sets of event code and correspondent timestamp, is processed every 5 seconds. Thenall values are received through “camonitor” at the CA client side. After the eliminationof duplication, the event codes and timestamp are saved to disk and successfully logged.

Figure 6.3: Architecture of CA-based event code log system.

82

Data and Information Acquisition
However, data loss was found in the client during periodically scanning of the “waveform”
record. The reason comes from the high CPU load according to Fig. 6.4. The scan-5
task is responsible for the “waveform” record processing and the delay for this task isaround 4.5 ms. In other words, if the delay of the scan-5 task is longer than 5 s, the“waveform” record wound is not scanned and event codes are lost in the client [66].

Figure 6.4: VxWorks task delay information.

The overhead for CA is too high. To tackle this problem, we decide to modify the“mrfioc2” driver by adding a new larger buffer to perform the time-memory tradeoff [67]. A new VxWorks task called “evtlog” is also created to directly write the eventcodes to disk rather than through CA to decrease the computation time and network
connection cost. One task created by the original “mrfioc” driver reads the event codeand timestamp from EVR FIFO and puts them into an “epicsRingBuffer”. Then all thecontents inside the “epicsRingBuffer” are drained out by the “evtlog” task to disk. The
CPU load through the low-level interface method is dramatically decreased and all eventcodes are logged without data lost.
The source code of this modification can be referred to from [68]. This event codelog system works well after the deployment in June 2019 and event codes information
for both upstream LINAC and downstream LINAC can be fully stored to disk. The
event log system is important for us to locate the error of timing signals and help up tosummarize the failure modes.
83Chapter 6. Reliability Analysis of Timing System

6.2.2

AC50 Log

Figure 6.5: Histogram of AC50 drift
value in 24 hours.

Figure 6.6: AC50 drift value in ∼5
minutes.

According to the Tokyo Electric Power Company, the AC power line used at KEK
fluctuates within 50±0.2 Hz (i.e., AC50 fluctuates within ±80 µs) to balance the supply
and demand requirement of the electricity market [69]. Since the sequence shift alsouses AC50 arrival timing as the reference, we need to understand the arrival timing of
AC50 and deduce the procedure inside one pulse.
The AC50 log system is much easier than the event code log since the update frequency(50 Hz) is relatively slow. As a result, EPICS CA is stable enough to monitor the AC50
arrival timing. The AC50 arrival time in a pulse is measured by TDC and saved in an
EPICS “waveform” through the device driver program. The length of this “waveform”
is 64 to hold 16 channels stop signal and 4 measurements for each channel. A python
client program is developed to save the TDC measurement results for every pulse.
Based on the AC50 log, the status of AC50 drift is visualized in Fig. 6.5 and Fig. 6.6.
The drift value of less than 80 µs is observed.
The AC50 log is also connected with the LINAC operation log by monitoring the abnormal AC50 value. If such an error is observed, a warning message is written into theoperation log database to help the operator understand the situation.

6.3

Failure Mode of Timing System

The event code log and AC50 log record the significant information of the timing system.
Based on the analysis of the log data, some abnormal behaviors of the event timing
84

Failure Mode of Timing Systemsystem are observed [65]. In principle, the event timing system failure modes mainly
include,1. Event Code Anomaly. The event codes received at EVR are not as expected.
Some of the event codes in a single pulse might be missing or duplicated.
2. Delay Anomaly. The time sequence of event codes is wrong. The events are notreceived at the correct time, which is calculated based on the bucket selection andAC50 phase.

The partition is somewhat rough since both event code and delay could be wrong during
the operation (or even worse, the event codes are not sent out). Here we will discuss
two representative failure modes.

6.3.1

Beam Mode Replacement

Figure 6.7: Failure mode of beam mode replacement.

Figure 6.7 shows the one kind of the failure mode. The beam mode for LER should betransferred in pulse “#3” but beam mode for HER is sent. The contents of “software

85

Chapter 6. Reliability Analysis of Timing Systemsequencer” and “hardware sequencer” are modulated pulse by pulse and the description
can be referred to in Section 5.2.
Owing to the drastic drift of AC50 and the shift of 16/18 pulses sequence, the AC50
signal comes very late inside the 50 ms pulse. Thus, the “readback” signal is delayed accordingly. If the “readback” signal comes later than pre-event, the pre-event first changes
the “software sequencer” to the value of the next beam mode and then “readback” signal loads “software sequencer” value to “hardware sequencer”. Then, the “hardware
sequencer” is triggered by the delay of the main event in the same pulse. The overall
effect is that the beam mode in pulse “#3” is replaced by pulse “#4”.

6.3.2

Redundant Beam Mode

Figure 6.8: Failure mode of beam mode redundancy.

When the event code log is checked, sometimes an extra beam mode of PF/PF-AR
is inserted between LER mode and a PF/PF-AR mode. As Fig. 6.8 shows, the LER“readback” signal in pulse “#3” comes too early and causes the “hardware sequencer”
change the beam mode and trigger source to the next pulse, i.e., PF beam mode. Notethe “hardware sequencer” trigger source for LER comes from the main event in middle
86Failure Mechanism and Failure Cause
EVR and for PF the source is obtained from the change coincidence between PF revolution frequency and LINAC RF frequency. Consequently, the “hardware sequencer” istriggered twice in a single pulse.
This failure mode is induced by abnormal bucket selection delay and the failure causecomes from the software bug in the bucket selection algorithm or injection pattern switch.
The mechanism of the latter is explained in Section 6.4.2.

6.4

Failure Mechanism and Failure Cause

6.4.1

AC50 Drift

The failure beam mode replacement is mainly caused by undesirable AC50 arrival timing.
Thus, the AC50 drift speed and the AC50 drift tolerance of the sequence shift algorithm
are investigated to understand the failure mechanism.
According to the AC50 log, the status of AC50 fluctuation can be visualized. Two situations of the drift speed of AC50 are shown in Fig. 6.9 and Fig. 6.10. The horizontal axis
stands for the AC50 drift value and the vertical axis represents the time of occurrence.
In most situations, AC50 drifts mildly in 50±0.1 Hz, i.e., 40µs in 20 ms.

Figure 6.9: AC50 drifts mildly in 24h.

Figure 6.10: AC50 drifts strongly in
24 h.

The timing of the AC50 position in a pulse can be acquired from the AC50 log. As
Fig. 6.11 shows, the AC50 arrival timing chart shows that AC50 might come late whenstrong AC50 fluctuation happens.
Since the estimated AC50 is used in the sequence shift algorithm to judge the sequence
type of the next pulse. The estimated AC50 is different from the real AC50, and the87Chapter 6. Reliability Analysis of Timing System

AC50 islarger
than
15 ms

16
15

Timing of AC50 (ms)

14
13
12

2.5 ms11

AC50 ﬂuctua"on- 2.8 ms

10
9
8
7
6
0

20

40

60

80

100

120

140

160

180

Measurement Point
Figure 6.11: Drift of AC50.

discrepancy becomes larger when AC50 drifts drastically. Table 6.1 compares the ideal
and real cases. The reference value for sequence shift algorithm Tref is set to 10 ms as
it is easy for calculation.
For example, the AC50 arrival timing of the first pulse in sequence #1 X1 determines
the type of sequence #2 S2 by calculating estimated value E2 . Since E2 is 9.9 which issmaller than Tref , the sequence type of #2 is decided to be 2.5, the AC50 should jump
up 2.5 ms in sequence #3. This decision works well for mildly AC50 drift or without
AC50 drift. However, if AC50 drifts for 60 µs per pulse, E2 is far away from the real
AC50 value. The AC50 fluctuation is then reflected at the end of sequence #3, where
the AC50 drift becomes 15.6 ms, which enters the race condition. If the timing system
goes into the race condition, then the normal processing logic is messed up and thevarious abnormal situation will appear.
Sequence #
1
2
3
4
..

Without AC50 drift
Sn Xn
Yn En+1-2.8 12.7 12.7
9.9
2.5 9.9
9.9
12.4-2.8 12.4 12.4
9.4
2.5 9.4
9.4
11.9
..
..
..
..

With AC50 drift
Sn Xn
Yn En+1-2.8 12.7 13.8
9.9
2.5 11.1 12
13.6-2.8 14.5 15.6 11.7
-2.8 12.9 14.8 10.1..
..

Table 6.1: Analysis of the decision making of the sequence shift.

To quantify the possibility of the relationship between timing system error and AC50
drift, the limit of the race condition is chosen to be less than 4.5 ms and larger than 15
88

Failure Mechanism and Failure Cause

Figure 6.12: The relation between time to failure and of extend of AC50 drift for
16/18 pulses sequence shift.

ms, which is decided based on the operational experience. According to the algorithm,
we can simulate the process of a sequence shift using computer code. Figure 6.12 shows
the simulation result of 16/18-pulse sequence shift. The initial AC50 arrival timing is 10
ms, and Tref is 9.85 ms. If |∆AC | <= 40µs, the 16/18-pulse sequence shift can always
compensate for the AC50 drift, and race conditions will not happen. While ∆AC is ∼45µs, the timing system goes into race condition after ∼130 s. If ∆AC becomes larger,e.g., 60 µs, the timing for race condition only requires ∼0.6 s. Note that the figure isasymmetric because both the sequence shift value (2.5 and 2.8 ms) and boundary forrace conditions (4.5 and 15 ms) are different. The source code of simulation can bereferred to in Appendix A.3.
Similarly, for 8/9 pulses sequence shift, the tolerance of AC50 drift improves as shownin Fig. 6.13. The threshold for AC50 drift becomes ∼120 µs.

6.4.2

Injection Pattern Switch

We have mentioned that the failure mode of the redundant beam mode is caused by
an abnormal bucket selection delay. The program bug for bucket selection is one of thepossibilities since the bucket selection program needs too many conditions to handle.
89

Chapter 6. Reliability Analysis of Timing System

Figure 6.13: 8/9 pulses sequence shift method is able to handle lager AC50 drift
value.

And that is the reason why the bucket selection log is planned to quickly diagnose theprogram and fix the bug.

Figure 6.14: Injection pattern switch error caused by DR operation.

Apart from the random error during the program running, another kind of bucket selection delay error is caused by the injection pattern switch. As the Fig. 6.14 shows,the injection pattern switches from “injection pattern A” to “injection pattern B”. Bothpatterns constitute 50 pulses.
The “injection pattern A” performs 1 Hz LER injection by setting beam mode of pulse“#2” and pulse “#4” to KBPu and KBPd, respectively. In other words, pulse “#2”90

Reliability Requirements Evaluation
injects positron beam into DR, and pulse “#4” extract the beam to LER.
The “injection pattern B” operates at a higher LER injection repetition rate, i.e., 25
Hz. Every pulse for LER combines KBPu and KBPd which means both extraction andinjection happen in the KBP pulse. The extraction bucket selection delay for pulse “#4”is decided in pulse “#2”. Similarly, the beam injected in pulse “#50” should be extracted
in pulse “#2”. However, at the initial period of “injection pattern B”, the extraction
delay remains unknown. There are two possibilities to set the extraction delay value forpulse “#2”,• Reset the extraction delay value to a default value, e.g., 5 ms, during injection
pattern switch.
• Use the extraction delay value of the last injection pattern. Here means the delay
value of pulse “#4” of “injection pattern A”.

Both situations result in the abnormal bucket selection delay hence the failure mode of
redundant beam mode. The root reason for this situation is the cross-pattern dependency of LER injection which means the DR injection pulse and DR extraction pulse
occur in a different cycle of injection pattern. This one-pulse error does not affect thebeam since there is no beam in DR. However, the trigger signal is delivered to devices
like klystron and this trigger might violate the 18 ms trigger interval requirement of the
klystron.
As we have summarized in Table 4.4, whether LER injection can be finished in a single
cycle of current injection pattern depends on the DR storage time, KBP mode repetition
rate, DR 2-pulse storage mode, and length of injection pattern.

6.5

Reliability Requirements Evaluation

The reliability requirements of the timing system at KEK LINAC can be evaluatedbased on how often the failures appear, how long do the outages continue and what is
the impact of failures and outages.

91

Chapter 6. Reliability Analysis of Timing System
Figure 6.12 demonstrates the threshold for risky AC50 drift value is 60 µs every 20
ms. Therefore, counts of AC50 drift which is larger than 60 µs and counts of maximal
continuous large AC50 drift are shown in Fig. 6.15.

Figure 6.15: Counts of large AC50 drift from June, 2019 to April, 2021.

There are many abnormal AC50 drift situations from October 2020 to December 2020
but these drifts were not continuous. These data are thus considered outliers. The countsof maximal continuous large AC50 drift increase from February 2021. The occurrenceof such kind of failure is not often (i.e., 9 times) in 2020. However, the number of
failures increases to 18 times in a month since the 2021 spring, and the beam operation
is frequently interrupted.

Figure 6.16: Maximal AC50 drift value in a day from June, 2019 to April, 2021.

92

Reliability Requirements Evaluation
The maximal AC50 drift value in a single day is also displayed in Fig. 6.16. As shownin the figure, the AC50 drifts severely on some days which could cause problems since
the timing system relies on the AC50 to function normally.
Different impacts exist for the various timing system failure modes. There is a highpossibility that the timing system stops the delivery of the events if the AC50 arrival
time is less than 4.5 ms or larger than 15 ms. If this situation happens during the physics
run, then the klystron will be down and cause the beam to abort. Another minor failure
happens when the bucket selection delay value is wrong. This failure does not affectthe beam since either the beam gate is closed or there is no beam in DR. However, theklystron is triggered with an unexpected interval and the DR kicker is blank fired.

93

Chapter

7
Reliability Improvement andFuture Prospects
7.1

Reliability Improvement

To guarantee a stable timing system and avoid the race condition, the following measurements can be considered.

7.1.1

AC50 Independent Operation

An intuitive method is to remove the AC50 dependency since the failure of the timing
system is caused by AC50 fluctuation. It is possible to evaluate the performance ofsignificant hardware in different AC50 arrival timing and consider the possibility toreplace the hardware that has a strong dependency on AC50; currently, the quality ofthe power supply has improved significantly, and some accelerator facilities are using
AC50-independent devices, for example, the J-PARC timing is independent with ACline [70]. Thus, an experiment is performed to evaluate the effect of AC50-independent
operation.

95

Chapter 7. Reliability Improvement and Future Prospects
An experiment was conducted by replacing the AC50 trigger from the MTG modulewith a strictly 50 Hz trigger. The bema position can be measured using BPM. Theenergy jitter is then calculated through the dispersion function in Eq. 7.1, where δx(s)is the horizontal beam position, D(s) is the dispersion function and ∆P/P represents
the energy jitter.
∆x(s) = D(s)

∆P
P

(7.1)

Energy jitter

0.0086% rms

AC50 dependent

0.014% rms

AC50 independent

Time (4 hours)

Figure 7.1: Change of energy jitter at the beam transport line of LINAC.

After replacing the MTG module with a strictly 50 Hz signal generator, the timing
trigger signal is delivered at a different phase of the AC line. The hardware at LINAC
works under the AC50-independent mode. The energy jitter of electron bunch at thebeam transport line of LINAC is measured and the results are displayed in Fig. 7.1.
The average energy jitter for AC50-dependent mode is 0.0086% (r.m.s) and it increases
to 0.014% (r.m.s) after switching to the AC50-independent mode. Though the beam
quality is indeed related to AC line frequency, the overall energy jitter (0.079%) is still
acceptable for SuperKEKB MR since the required energy spread in the current operation
stage is 0.1% [71]. Consequently, the injection for SuperKEKB rings can be performed
without synchronizing to the AC line.
Another hardware experiment was also done by measuring the klystron output and AC50
timing. Figure 7.2 shows the relation between AC50 and RF power. Still, no strong
relation between RF power and AC50 was found.
However, during the experiment, a strong dependency between AC line frequency andthe power supply of the injection kicker magnets at PF are observed. The timing trigger
96

Reliability Improvement

Figure 7.2: Relation between klystron output and AC50 arrival timing.

for PF ring injection must synchronize with the AC power line. Figure 7.3 shows thevariance between 4 PF kickers.

Figure 7.3: Schematic diagram of AC50 regulator module.

97Chapter 7. Reliability Improvement and Future Prospects
Operation mode of AC50 regulator
20 ms
20 - ttolerance
20 + ttolerance

Input from AC-GEN
Output of AC50
regulator

AC linettolerance
Previous
AC50
pulse
AC50 - ttolerance < 𝛥𝐴𝐶 < ttolerance

Synchronousmode

AC-GEN

Same as interval of AC50

PF injection enable

AC50 regulator

OutputOutputAC50

Asynchronousmode
PF injection disable

20 - ttolerance

TDC

OutputOutputAC50

Beam Gate
system for PF

Asynchronousmode
PF injection disable

20 + ttolerance
OutputOutputFigure 7.4: Schematic diagram of AC50 regulator module.

7.1.2

Partially AC50 Independent Operation

Considering that strong AC50 drift occurrence is rather rare according to the datameasured by TDC, a CompactRIO-based module called AC50 regulator is designed toswitch between the AC50-dependent and AC50-independent modes. As Fig. 7.4 shows,the AC50 regulator module is inserted between the MTG and TDC modules. It supports
two operation modes, synchronous mode, an asynchronous mode, which corresponds toAC50-dependent and AC50-independent operation, respectively. Under synchronousmode, the AC50 regulator module directly passes the AC50 signal to the TDC module.
On the other hand, the module generates outputs with a fixed interval to TDC when the
AC50 drift value is large. The timing system starts to operate under AC50-independent
mode in a short period. When the AC50 drift value becomes smaller, the module switches
to synchronous mode within several seconds, and the timing system trigger synchronizes
with the AC line again.
A parameter called ttolerance , which is decided based on the simulation result of sequence
shift (see Fig. 6.12), is used to determine the maximal AC50 drift value that the AC50
regulator permits. If AC50 drift value |∆AC | is larger than ttolerance , the module enters
asynchronous mode. The range of output interval is restricted to be 20 − ttolerance or
20 + ttolerance . Meanwhile, the PF injection is disabled by sending a signal to the beam
98

Reliability Improvement
gate system. Combining the simulation results and data analysis, the value of ttolerance
is set to 40 µs at LINAC. The output interval of the AC50 regulator is within 20±0.04
ms. About 1% pulses are prohibited for PF injection.

7.1.3

Performance of AC50 regulator

Output of AC50 regulator

19.96 ms

20.04 ms

Output of MTG

Figure 7.5: Comparison of AC50 regulator and MTG output.

The AC50 regulator module is installed and tested in the 2021 spring. Since then, thetiming system failure caused by strong AC50 fluctuation never happens. The processing
delay of the AC50 regulator is ∼500 ns. The long-term stability of the AC50 regulator
module is studied by measuring the output signal interval of the AC50 regulator and
MTG module. The histogram shown in Fig. 7.5 indicates that the range of the AC50
regulator output is guaranteed within 20±0.04 ms.
The AC50 regulator must switch back to synchronous mode after strong AC drift stops.
There are only theoretical possibilities that the frequencies of AC line and regulator output are the same, though remaining at a different phase. In practice, the AC line always
drifts, and it will catch up with regulator output after a short period. According to thedata measured by TDC in one month, the average transition time from asynchronousmode to synchronous mode is ∼31 s. Figure 7.6 displays an example of the transition
process. The red dots are the arrival time of regulator output while the blue dots are
the arrival time of AC50. The asynchronous mode lasts for ∼80 s and it takes ∼20 s toresynchronize with the AC line after strong AC drift stops.

99Chapter 7. Reliability Improvement and Future Prospects

Asynchronous mode
Synchronousmode

Synchronousmode

Figure 7.6: Resynchronization to AC50 after strong AC50 fluctuation stops.

7.1.4

Improvement for sequence shift

The AC50 regulator stabilizes the timing system and reduces the accelerator failure
time at LINAC. However, there are still concerns about the degradation of the beam
quality. To operate the timing system under AC50-dependent mode, two sequence shift
improvements are proposed to optimize the timing system.
16/18-pulse sequence

8/9-pulse sequence

16/18-pulse sequence

Figure 7.7: Comparison of AC50 arrival timing between 16/18-pulse sequence and8/9-pulse sequence.

As Fig. 7.7 shows, compared with the 16/18-pulse injection sequence, the 8/9-pulse injection sequence increases the robustness of the sequence shift algorithm. Switching to
the 8/9-pulse injection sequence is a possible method to solve the timing failure because
the AC50 adjustment speed is faster. The restriction of the sequence length originates

100Reliability Improvementfrom the DR storage time and the root reason is the coupling of DR injection and extraction. The DR extraction delay is calculated at the injection pulse, which results in theextraction timing having a time difference with the drifted AC50. Shifting the RF phaseat the downstream LINAC is an efficient way to increase the DR extraction opportunity
and relieve the stress of long sequence management. Under these circumstances, thedependency between DR and MR injections can be removed (See Section 5.3 for detail).
The operation of an 8/9-pulse sequence shift is possible as the injection and extraction
delay calculations can be separated.

Figure 7.8: Extremely strong AC50 drift recorded by TDC.

Apart from the 8/9-pulse sequence shift, the sequence shift algorithm can be further
improved by considering the AC50 drift value. Currently, the estimated AC50 arrival
time is used to determine the next sequence type. If strong AC50 drift happens, theestimated value has a large deviation from the real value. The timing system could
enter race conditions when an inappropriate sequence type is selected. To avoid sucha situation, the sequence shift algorithm is modified and the average AC50 drift value
in recent pulses is utilized to help the sequence shift algorithm to estimate the AC50
arrival time. Figure 7.8 shows a timing system failure that is caused by the extremely
strong AC50 drift. The AC50 drift value reached 120 µs and lasted for several seconds.
Figure 7.9, 7.10, 7.11 compare three sequence shift schemes which include, 16/18-pulse

101Chapter 7. Reliability Improvement and Future Prospects
sequence shift which is currently using, 8/9-pulse sequence shift and 8/9 pulse sequence
shift with a functionality of making use of the AC drift value.

Figure 7.9: 16/18-pulse sequence shift data measured by TDC.

Figure 7.10: Simulation of 8/9 pulse sequence shift.

The 8/9-pulse sequence operation with recent AC50 drift value compensation has beenplanned for 2021 summer.

102

Future prospects

Figure 7.11: Simulation of 8/9 pulse sequence shift with considering the AC drift.

7.2

Future prospects

7.2.1

Log Data Synchronization

Figure 7.12: Abort Trigger System log displayed in Grafana.

103

Chapter 7. Reliability Improvement and Future Prospects
Apart from the trigger delivery function, the timing system also needs to provide theability to correlate the log data from different sub-systems. Normally timestamps or a tag
called pulse ID are used to identify which pulse the data comes from. Figure 7.12 shows
the abort trigger system displayed in Grafana [72], which is a popular dashboard for log
data visualization. The abort request timestamp and related pulse ID are recorded for
diagnosis purpose [73]. Thus, it is significant to analyze the data based on device log-in
during that short period. The timestamp of the abort trigger system is received from
MTS and synchronized with the event timing system, and it is simple to identify theevent codes through timestamp. However, other log systems are not correlated with thetimestamp from event timing. These log systems are listed in Table 7.1.
Log System
Abort
Pulsed Magnet
BPM
RF Monitor
Event Code
Data Buffer

Data Format
Json
CSV
Plain text (bz2 compressed)
Plain text (bz2 compressed)
Plain text
CSVTag
EVG timestamp & 16-bit pulse ID
NTP timestamp & 32-bit pulse ID
32-bit pulse ID
32-bit pulse ID
EVG timestamp
EVG & NTP timestamp & 32-bit pulse ID

Table 7.1: Tagged data for different log systems.

7.2.2

Smooth Pattern Switch

Figure 7.13: Injection pattern switch times in November, 2020.

The beam operation must stop during the injection pattern switch period to avoid theabnormal event timing signal is applied to hardware. Though closing the beam gate
brutally can avoid bad beam generation, a smooth way should be used to change the104

Future prospects
injection pattern reliably. One of the concerns on beam gate closing is that the beamgate closing action is done by the operator. The pattern switch times in November 2020are shown in Fig. 7.13. The action of thousands of times per day should be manipulatedby an automatic program to avoid human error.
Another concern is about the injection pattern switch error caused by DR operation as
we have discussed in Section 6.4.2. Though this error does not affect the beam since
the beam gate is closed (or since there is no beam in DR, depending on the operationmode), the trigger signal is still delivered to some devices like klystrons and kicker
magnets. Thus, the 18 ms klystron trigger interval may be broken. We may consider
some methods in the future to avoid this situation. For example, by adding somepseudo pulses during the injection pattern switch to allow the pseudo pulses to perform
preparation trigger calculation.

105

Chapter

8
Conclusion
From the demand for stable operation and maintenance, the timing system takes animportant role in the accelerator. This thesis mainly introduces the basic parts of thetiming system, which include,• RF synchronization,• Trigger delivery,• Bucket selection.

RF synchronization is necessary to inject the beam from LINAC into the storage ring.
The relation between LINAC RF frequency and ring RF frequency is also discussed. Ifthese two frequencies match an integer multiple relations, the synchronization is simple
and easy to achieve. Otherwise, the greatest common frequency is used to find thecoincidence point for injection.
Apart from the synchronization between LINAC and ring, synchronization between
multi-rings bring new requirement. These three RF synchronization schemes are compared with the example of SLS timing, BEPC II timing, and SuperKEKB timing. Several concepts about RF frequency synchronization are also introduced, like revolution
107

Chapter 8. Conclusion
frequency and bucket selection repetition rate. These concepts are crucial for those whowant to design a timing system or understand the existent timing system.
The goal of the timing system is to provide a precise trigger signal for hardware ina scheduled sequence. The evolution of trigger delivery is introduced based on thehistoric order. From various kinds of timing modules for different institutes to de-facto
standard event modules among accelerator facilities, the timing system becomes much
more flexible and scalable. The basic block of EVG and EVR are talked to understandhow a timing system in modern accelerator complete the control mission.
One of the most significant targets for a timing system is Bucket selection. There
are several schemes to decide which RF bucket should be injected. At SuperKEKB, the“BCE” and “star” schemes are commonly utilized to accommodate the physics run. Afterthe RF bucket number is determined, the bucket selection delay should be calculated andset at EVG. The delay calculation for the selected RF bucket should base on a fiducial
point. Usually, the revolution frequency functions as the fiducial point. Arbitrary RF
buckets can be filled through the revolution frequency fiducial and bucket delay value.
Recently, another timing system implementation (i.e., White Rabbit project) rather thana traditional event-based timing system is developed from CERN. The timestamp-basedtiming system provides other thoughts to coordinate the devices. Several key technologies, like frequency synchronization through Sync-E protocol and PHY, timestamp
synchronization through IEEE-1588, are also introduced. The precision of a timestampbased timing system is nearly the same as an event-based timing system which provides
an extra option to build a timing system. Furthermore, the timestamp-based timing
system is inherent in the ability to perform log data synchronization while an extra tag
is needed for an event-based timing system.
In practice, the timing system is constrained by hardware. At LINAC, the timing system
must satisfy three major requirements,• PPM,• AC50 synchronization,• DR operation.

108

It is inevitable to choose PPM since KEK LINAC needs to provide a beam for 4 rings.
Accordingly, the timing system must switch the beam mode and control parameters turnby-turn. To keep the hardware, operate in good stability, the AC50 synchronization is
also mandatory. Concerning AC50 drift, these restrictions eventually force us to develop
several modules, such as the TDC and MTG module, to perform AC50 synchronization
every pulse.
The operation of DR increases the dependency between DR injection pulse and DR
extraction pulse. Besides that, the preparation trigger for the injection magnet requires
a timing system to provide trigger one pulse before. The pre-trigger requirement conflicts
with the PF/PF-AR beam mode since the chance coincidence is used to generate a trigger
signal for PF/PF-AR. As a result, the implementation of pre-event is changed from data
buffer transmission to event code delivery to tackle the conflict.
The detailed implementation of the timing system at KEK LINAC is also discussed. The
reason for sequence shift and how to sequence shift is achieved are thoroughly analyzed.
Another conceivable restriction between 8/9 pulses sequence shift and DR storage timeis described and a solution of 16/18 pulses sequence shift scheme is chosen to be thebasic structure of the main timing station.
There are obstacles to limit the LER RF bucket selection number which comes from the
DR injection kicker magnet during DR two-bunch and two-pulse operation. We choose
to shift the RF phase in downstream LINAC to solve the restriction. By shifting the RFphase, the chance for extraction from DR increases, and all the LER RF buckets can beselected.
All these restrictions raise the complexity of the timing system. Thus, it is difficult tounderstand what was happening in the timing system behaves abnormally. To locate theproblem source and quickly handle the error, several log systems for the timing system
are newly constructed. Firstly, the event code log system is implemented by a low-level
driver program for EVR, and it works well during the elapsed two years. Then, theAC50 log system is regarded as necessary after some brief analysis of the timing system.
Finally, two basic failure modes are summarized to describe the timing system error.
The theoretical failure recurrence is done based on the timing log and the error source
is located.

109

Chapter 8. Conclusion
Most of the timing system errors are caused by AC50 drift. Through the computer
simulation, the sequence shift algorithm is designed to handle mildly AC50 drift (i.e.,
50±0.1 Hz) but sometimes the AC50 sharply fluctuates in 50±0.2 Hz. The strong AC50
drift destroys the PPM logic and generates an abnormal trigger signal to hardware.
The beam operation must stop when these signals are received by some timing-sensitive
hardware, such as the klystron modulator.
Several solutions are proposed to solve this problem. The temporary solution is touse an AC50 regulator module to perform a partially AC50-dependent operation. The
performance of the AC50 regulator is tested and it successfully solves the timing system
failure caused by strong AC drift. However, this method causes the degradation of beam
quality as well as the efficiency of LINAC.
The ultimate solution is RF phase shift for downstream LINAC and upgrade of sequence
shift. The functionality of phase shift for downstream LINAC has been tested recently
and is able to increase the RF bucket number for two-bunch and two-pulse operations.
The physics commissioning is still undergoing. The 8/9 pulses sequence shift can only
increase the tolerance of AC50 drift level and if AC50 fluctuations in 50±0.4 Hz, thefailure will occur again. Thus, we propose the idea of adding the information of recent
AC drift value to estimate the AC50 arrival time in the future. In this way, the sequence
shift becomes more intelligent. The construction and test of the new sequence shift
scheme are scheduled for 2021 summer.

110

Appendix

A
Source Code
A.1
1

DR Buckets for 2-bunch and 2-pulse# / usr / bin / python323

def cal_bs_delay ( harm_dr , dr_occupied_bkt , kicker_delay_bkt ) :4

mr_avail_one_bunch , dr_avail_one_bunch = set () , set ()5

mr_avail_two_bunch , dr_avail_two_bunch = set () , set ()6idx = 07

mr_rf = 114.24/11.0*49

8delay_period = (1 / mr_rf ) * 49000

9

harm_mr = 5120

10

delay = idx * delay_period

11

while delay <= 2000000:

12

mr_bkt = idx * 49 % harm_mr13

dr_bkt = idx * 49 % harm_dr

1415# bkt number ranges from 0 -229

16

# bkt 0 and 49 are occupied , from bkt 49 , wait for ‘
kicker_delay_bkt ‘ bucket

17
18# for one bunch injection

19

if dr_occupied_bkt + kicker_delay_bkt < dr_bkt < harm_dr - 49 kicker_delay_bkt + dr_occupied_bkt :111

Appendix A. Source Code20

mr_avail_one_bunch . add ( mr_bkt )21

dr_avail_one_bunch . add ( dr_bkt )22# for two bunch injection

23

if dr_occupied_bkt + 49 + kicker_delay_bkt < dr_bkt < harm_dr 49 - kicker_delay_bkt + dr_occupied_bkt :24

mr_avail_two_bunch . add ( mr_bkt )25

dr_avail_two_bunch . add ( dr_bkt )26

idx += 1

27

delay = idx * delay_period

28

print ( " * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * " )29

print ( " one_bunch : MR : " , len ( mr_avail_one_bunch ) , " DR : " , len (d r_a va il_one_bunch ) )30

print ( " * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * " )31print ( " two_bunch MR : " , len ( mr_avail_two_bunch ) , " DR : " , len (d r_a va il_two_bunch ) )

32
33
34

if __name__ == ’ __main__ ’:# note , the logic does not consider occupied bucket other than 0 and

35

49.
36

cal_bs_delay (230 , 0 , 50)

Listing A.1: Available DR buckets for 2-bunch and 2-pulse injection.

A.2

Available DR buckets for RF Phase Shift1# / usr / bin / python3

2# 8.75 ns

3

Event_CLk = 1000 / 114.24

4# 1.965 ns

5

MR_Clk = 1000 / (114.24 / 11 * 49)

678

def cal_delay ( mr_bkt , dr_bkt ) :for i in range (0 , 5120 * 23) :9

if i * 49 % 5120 == mr_bkt and i * 49 % 230 == dr_bkt :10
11cycle = int ( i / 5120)

12

oppo = i % 5120

13

# print (i , cycle , oppo )14

dr_for_ler0 = cycle * 49 * 5120 % 230

112

Available DR buckets for RF Phase Shift15# print ( dr_for_ler0 )16

return dr_for_ler0

17
18
19

def cal_delta_t ( delta_t ) :20_all_delta = set ()21_res = []22

for bkt_num in range (0 , 49) :23

for evt_clk in range (0 , 12) :24

delta = abs ( round ( MR_Clk * bkt_num - Event_CLk * evt_clk , 4) )25

if delta < delta_t :26_all_delta . add ( delta )27

dr_bkt = cal_delay ( bkt_num , bkt_num )28_res . append ([ bkt_num , delta , ( dr_bkt + 100) % 230 , ( dr_bkt + 50)

29% 230 , dr_bkt , ( dr_bkt - 50 + 230) % 230 ,( dr_bkt - 100 + 230) % 230])

30# print ( bkt_num , dr_bkt , delta )31
32

return sorted ( _all_delta ) , _res

33
34
35
36

def cal_dr_bkt ( delta , data : [[]]) :dr_cand_493 , dr_cand_986 , dr_cand_1479 , dr_cand_1972 , dr_cand_2465 =[] , [] , [] , [] , []37
38

for i in range ( len ( delta ) ) :temp1 , temp2 , temp3 , temp4 , temp5 = set () , set () , set () , set () ,set ()

39
40
41

for j in data :if j [1] <= delta [ i ]:temp1 . add ( j [4])4243

temp2 . add ( j [4])44

temp2 . add ( j [5])4546

temp3 . add ( j [3])47

temp3 . add ( j [4])48

temp3 . add ( j [5])4950

temp4 . add ( j [3])51

temp4 . add ( j [4])52

temp4 . add ( j [5])113Appendix A. Source Codetemp4 . add ( j [6])

53
54
55

temp5 . add ( j [2])56

temp5 . add ( j [3])57

temp5 . add ( j [4])58

temp5 . add ( j [5])59

temp5 . add ( j [6])60dr_cand_493 . append ( len ( temp1 ) )61

dr_cand_986 . append ( len ( temp2 ) )62

dr_cand_1479 . append ( len ( temp3 ) )63

dr_cand_1972 . append ( len ( temp4 ) )64

dr_cand_2465 . append ( len ( temp5 ) )65

return dr_cand_493 , dr_cand_986 , dr_cand_1479 , dr_cand_1972 ,66

dr_cand_2465
67
68
69

if __name__ == ’ __main__ ’:70# cal_delay (23 , 23)71

all_delta , res = cal_delta_t (4)72print ( all_delta )73

for ii in cal_dr_bkt ( all_delta , res ) :print ( ii )74

Listing A.2: Available DR buckets for RF Phase Shift

A.3

Sequence Shift Simulation

1# / usr / bin / python32

import numpy as np

3

import matplotlib . pyplot as plt

45

freq = 114.24 / 11 / 5120 / 46 * 1000000

6

period = 1 / freq * 1000

7

seq = [0 , 1]

# Unit Hz# Unit [ ms ]8910

def s e q _ s hift_simulation ( speed , ref , loop , seq_type , l_bound , r_bound ) :if seq_type == " 16/18 " or seq_type == 0:11seq_length = [18 , 16]

12

114

Sequence Shift Simulation
seq_shift = [ -2.854830 , 2.50202]

13
14else :

15

seq_length = [9 , 8]16

seq_shift = [ -2.854830 / 2 , 2.50202 / 2]17y_pre = 1018

y_max = 019s_pre = 020

s_cur = 1

21

time_passed = 0

22

failure_time = 0

23

failure_happened = 0

24

for i in range (0 , loop ) :if ( y_pre + seq_shift [ s_pre ] + seq_shift [ s_cur ]) > ref :25

s_next = 026else :

27

s_next = 128

y_cur = y_pre + speed + seq_shift [ s_pre ] + seq_length [ s_cur ] *

29

speed
30

time_passed += seq_length [ s_cur ] * 20 - seq_shift [ s_cur ]31

if y_cur > y_max :32

y_max = y_cur
if failure_happened == 0 and ( y_cur > r_bound or y_cur < l_bound )

33

:
34

failure_time = round ( time_passed / 1000 , 3)35

failure_happened = 136y_pre = y_cur

37

s_pre = s_cur

38

s_cur = s_next

39

return failure_time

40
41
42

if __name__ == ’ __main__ ’:43idx1 = np . arange ( -80 , 80 , 0.1)

44

idx2 = np . arange ( -160 , 160 , 0.1)45

left_boundary = 4.5

46

right_boundary = 1547

ref_value = 9.85

48

thresh_1 , thresh_2 = [] , []49

plt . figure ( figsize =(6 , 4) , dpi =200)

50

plt . grid ( True )

51

115

Appendix A. Source Codefor i in idx1 :52thresh_1 . append (53

seq_shift_simulation ( speed = i / 1000 , ref = ref_value , loop =500 ,54

seq_type =0 , l_bound = left_boundary ,r_bound = right_boundary ) )55
56

thresh_1 = np . array ( thresh_1 )57

mask1 = thresh_1 > 0

58

fig_title1 = f " Simulation of AC50 drift with 16/18 pulses sequence ({left_boundary } , { right_boundary }) "59

label1 = f " Ref : { ref_value } "60# plt . title ( fig_title1 )61

plt . scatter ( idx1 [ mask1 ] , thresh_1 [ mask1 ] , marker = " x " , color = ’ blue ’ , s=5 , label = label1 )62
63# for i in idx2 :

64

#

65

#

thresh_2 . append (seq_shift_simulation ( speed = i / 1000 , ref = ref_value , loop

=500 , seq_type =1 , l_bound = left_boundary ,66#

r_bound = right_boundary ) )67# thresh_2 = np . array ( thresh_2 )68# mask2 = thresh_2 > 0

69# fig_title2 = f " Simulation of AC50 drift with 8/9 pulses sequence ({left_boundary } , { right_boundary }) "70

# label2 = f " Ref : { ref_value }"71# # plt . title ( fig_title2 )72# plt . scatter ( idx2 [ mask2 ] , thresh_2 [ mask2 ] , marker =" x " , color = ’ blue ’,s =5 , label = label2 )73
74# plt . xticks ( fontsize =18)75

# plt . yticks ( fontsize =18)

76

plt . xlabel ( " AC50 drift value [ $ \\ mu$s ] " , fontsize =14)

77

plt . ylabel ( " Timing for race condition [ s ] " , fontsize =14)

78
79

plt . legend ()80

plt . show ()Listing A.3: Sequence Shift Simulation

116

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