PCI-DAS6070
Analog Input and Digital I/OSpecifications

Document Revision 1.3
December 2012
© Copyright 2012

PCI-DAS6070 Specifications
All specifications are subject to change without notice.
Typical for 25 °C unless otherwise specified.
Specifications in italic text are guaranteed by design.

Analog input
Table 1. Analog input specifications
Parameter

Specification

A/D converter type
Maximum sample rate
Resolution
Number of channels
Input ranges

Successive approximation
1.25 MS/s
12 bits, 1-in-4096
16 single-ended / 8 differential, software selectable
Bipolar:±10V, ±5V, ±2.5V, ±1V, ±0.5V, ±0.25V, ±0.1V, ±0.05V,
Unipolar:0 to 10V, 0 to 5V, 0 to 2V, 0 to 1V, 0 to 0.5V, 0 to 0.2V, 0 to 0.1V
Software selectable
Internal counter – ASIC. Software selectable time base: Internal 40 MHz, 50ppm stability
 External source via AUXIN<5:0>, software selectable.
External convert strobe:
A/D CONVERT
Software paced
Software selectable option, burst rate = 800 nS
External digital:
A/D GATE
External analog:
ATRIG input
CH0 IN through CH15 IN
External digital:
Programmable, active high or active low, level or edge
External analog:
Refer to Analog trigger on page 9External digital:
A/D START TRIGGER
A/D STOP TRIGGER
External analog:
ATRIG input
CH0 IN through CH15 IN
External digital:
Software-configurable for rising or falling edge.
External analog:
Refer to Analog trigger on page 9Pre-/Post-trigger:
Unlimited number of pre-trigger samples, 16 Meg
post-trigger samples.
Available at user connector: A/D PACER OUT
8 K samples
DMA
Programmed I/ODemand or non-demand using scatter gather.
Up to 8 K elements. Programmable channel, gain, and offset
1.25 MS/s, system dependent

A/D pacing(SW programmable)

Burst mode
A/D gate sources

A/D gating modes
A/D trigger sources

A/D triggering modes

ADC pacer out
RAM buffer size
Data transfer
DMA modes
Configuration memory
Streaming-to-disk rate

Accuracy
1.25 MS/s rate, single channel operation and a 15-minute warm-up. Accuracies listed are for measurements
made following an internal calibration. They are valid for operational temperatures within ±1°C of internal
calibration temperature and ±10°C of factory calibration temperature. Calibrator test source high side tied to
Channel 0 high and low side tied to Channel 0 low. Low-level ground is tied to Channel 0 low at the user
connector.

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Specifications

PCI-DAS6070

Table 2. Absolute accuracy specifications
Range

Absolute Accuracy (LSB)

±10 V
±5 V
±2.5 V±1 V±500 mV±250 mV±100 mV±50 mV
0 to 10 V
0 to 5 V
0 to 2 V
0 to 1 V
0 to 500 mV
0 to 200 mV
0 to 100 mV

±2.9
±2.1
±3.0
±3.0
±3.0
±3.1
±3.3
±3.7
±2.8
±4.4
±4.4
±4.5
±4.6
±4.8
±5.2
Table 3. Absolute accuracy components specifications - all values are (±)

Range

±10 V
±5 V
±2.5 V±1 V±500 mV±250 mV±100 mV±50 mV
0 to 10 V
0 to 5 V
0 to 2 V
0 to 1 V
0 to 500 mV
0 to 200 mV
0 to 100 mV% ofReading

Offset(mV)

Noise + Quantization (mV)Single Pt

Averaged(Note 1)0.07140.03140.07140.07140.07140.07140.07140.07140.03140.07140.07140.07140.07140.07140.0714

6.38
3.20
1.61
0.653
0.335
0.176
0.081
0.049
3.20
1.61
0.653
0.335
0.176
0.081
0.049

6.10
3.05
1.53
0.610
0.305
0.208
0.098
0.071
3.05
1.53
0.610
0.305
0.208
0.098
0.071

0.846
0.423
0.211
0.085
0.042
0.024
0.011
0.007
0.423
0.211
0.085
0.042
0.024
0.011
0.007

Temp Drift(%/DegC)

Absolute
Accuracy at
FS (mV)

0.00100.00050.00100.00100.00100.00100.00100.00100.00050.00100.00100.00100.00100.00100.001014.369
5.193
3.605
1.452
0.735
0.379
0.163
0.091
6.765
5.391
2.167
1.092
0.558
0.235
0.127

Note 1: Averaged measurements assume dithering and averaging of 100 single-channel readings.

Each PCI-DAS6070is tested at the factory to ensure that the overall board error does not exceed absoluteaccuracy limits described in Table 2.

3

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PCI-DAS6070

Table 4. Relative accuracy specifications - all values are (±)
Range

±10 V
±5 V
±2.5 V±1 V±500 mV±250 mV±100 mV±50 mV
0 to 10 V
0 to 5 V
0 to 2 V
0 to 1 V
0 to 500 mV
0 to 200 mV
0 to 100 mV

Relative Accuracy (mV)Single Point

Averaged (Note 2)

7.37
3.68
1.84
0.737
0.368
0.238
0.111
0.082
3.68
1.84
0.737
0.368
0.238
0.111
0.082

1.11
0.557
0.278
0.111
0.056
0.032
0.015
0.009
0.557
0.278
0.111
0.056
0.032
0.015
0.009

Note 2: Averaged measurements assume dithering and averaging of 100 single-channel readings.

Relative accuracy is defined as the measured deviation from a straight line drawn between measured endpointsof the transfer function. ADC resolution, noise and front-end non-linearity are included in this measurement.
Table 5. Differential non-linearity specifications
All ranges±0.5 LSB typ±1.0 LSB max

4Specifications

PCI-DAS6070

Settling time
Settling time is defined here as the time required for a channel to settle to within a specified accuracy inresponse to a full-scale (FS) step. Two channels are scanned at a specified rate. A –FS DC signal is presented to
Channel 1; a +FS DC signal is presented to Channel 0.
Table 6. Settling time specifications
Accuracy
Condition

Range

Same range to same
range

±10 V
±5 V
±2.5 V±1 V±500 mV±250 mV±100 mV±50 mV

0 to 10 V
0 to 5 V
0 to 2 V
0 to 1 V
0 to 500 mV
0 to 200 mV
0 to 100 mV±0.012%(±0.5 LSB)

±0.024%(±1.0 LSB)

±0.098%(±4.0 LSB)

Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max

2.0 µS3.0 µS2.0 µS3.0 µS2.0 µS3.0 µS2.0 µS3.0 µS2.0 µS3.0 µS2.0 µS3.0 µS2.0 µS3.0 µS2.0 µS3.0 µS1.5 µS2.0 µS1.5 µS2.0 µS1.5 µS2.0 µS1.5 µS2.0 µS1.5 µS2.0 µS1.5 µS2.0 µS1.5 µS2.0 µS1.5 µS2.0 µS1.5 µS2.0 µS1.3 µS1.5 µS0.9 µS
1.0 µS0.9 µS
1.0 µS0.9 µS
1.0 µS0.9 µS
1.0 µS0.9 µS
1.0 µS
1.0 µS1.5 µS

Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Typ
Max

2.0 µS3.0 µS2.0 µS3.0 µS2.0 µS3.0 µS2.0 µS3.0 µS2.0 µS3.0 µS2.0 µS3.0 µS2.0 µS3.0 µS1.5 µS2.0 µS1.5 µS2.0 µS1.5 µS2.0 µS1.5 µS2.0 µS1.5 µS2.0 µS1.5 µS2.0 µS1.5 µS2.0 µS1.3 µS1.5 µS0.9 µS
1.0 µS0.9 µS
1.0 µS0.9 µS
1.0 µS0.9 µS
1.0 µS0.9 µS
1.0 µS
1.0 µS1.5 µS

5

Specifications

PCI-DAS6070

Parametrics
Table 7. Parametric specifications
Parameter

Specification

Max working voltage(signal + common-mode)
CMRR @ 60 Hz

Input must remain within ±11V of ground

Small signal bandwidth, all ranges
Large signal bandwidth, all ranges
Input coupling
Input impedance
Input bias current
Input offset current
Absolute maximum input voltage

Power on and reset state
Crosstalk, DC to 100 kHz

±10 V
95 dB
±5 V, 0 to 10V
100 dBAll other ranges
106 dB
1.6 MHz
1.0 MHzDC
100 GΩ in parallel with 100 pF in normal operation.
±200 pA±100 pA
Power ON: ±25 V, Power OFF: ±15 V (±20 mA Note 3)
Protected inputs: CH<15:0> IN
 AISENSE
CH0 IN, single-ended mode, 0 V to 0.1 V input range (Note 4)
Adjacent channels: –75dB
All other channels: –90dB

Note 3: The analog input sink/source current must be limited to an maximum of ±20 mA in the power OFF

state to prevent damage to the board. A 1000 Ω (¼ W) current limiting resistor should be placed inseries with each analog input channel being used in applications where the power OFF statesink/source current into the board can exceed ±20 mA. Resistance values >1000 Ω may adversely
affect the noise and settling time performance of the board.
Note 4: Care should be taken to avoid the application of an input voltage to CH0 IN that could overdrive theanalog input circuit. Any unused analog input channel should be connected to LLGND.

Noise performance
Table 8 summarizes the noise performance for the PCI-DAS6070. Noise distribution is determined by gathering
50 K samples with inputs tied to ground at the user connector. Samples are gathered at the maximum specified
single-channel sampling rate. Specification applies to both single-ended and differential modes of operation.
Table 8. Analog input noise performance specifications (not including quantization)
Range

CountsDithered

LSBrmsDitheredCounts
Undithered

LSBrms
Undithered

±10 V
±5 V
±2.5 V±1 V±500 mV±250 mV±100 mV±50 mV
0 to 10 V
0 to 5 V
0 to 2 V
0 to 1 V
0 to 500 mV
0 to 200 mV

5
5
5
5
6
6
7
9
5
5
5
6
6
7

0.5
0.5
0.5
0.5
0.5
0.6
0.7
0.9
0.5
0.5
0.5
0.5
0.6
0.7

3
3
3
3
3
4
5
8
3
3
3
3
4
5

0.25
0.25
0.25
0.25
0.25
0.4
0.5
0.8
0.25
0.25
0.25
0.25
0.4
0.5

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Specifications

PCI-DAS6070

Range

CountsDithered

LSBrmsDitheredCounts
Undithered

LSBrms
Undithered

0 to 100 mV

9

0.9

8

0.8

Analog output
Table 9. AO specifications
Parameter

Specification

D/A converter type
Resolution
Number of channels
Voltage range
Monotonicity
Slew rate
Settling time (full scale step)
Noise
Glitch energy
Current drive
Output short-circuit duration
Output coupling
Output impedanceGain temperature coefficient, internal or externalreference
Offset temperature coefficientPower up and reset

Double-buffered, multiplying
12-bits, 1-in-4096
2 voltage output±10 V, 0 to 10 V, ±EXT REF., 0 to EXT REF., software selectable12-bits, guaranteed
20 V/µs min
3.0 µS to ±0.5 LSB accuracy
200 µVrms, DC to 1 MHz BW±20 mV @ 1.5 µS duration measured at mid-scale transition.
±5 mA
Indefinite @ 25 mADC
0.1 Ω max
25 ppm/°C±50 µV/°C
DACs cleared to 0 volts ±200 mV max

Table 10. Absolute accuracy specifications
Range

Absolute Accuracy (LSB)±10 V
0 to 10 V±1.7 LSB±2.3 LSB
Table 11. Absolute accuracy components specifications

Range% of Reading

Offset(mV)

Temp Drift(%/DegC)

Absolute Accuracy at FS
(mV)

±10V
0 to 10V±0.0219±0.0219

±5.93
±3.49

±0.0005±0.0005±8.127±5.685

Each PCI-DAS6070is tested at the factory to assure the board’s overall error does not exceed the limits listed inTable 10.
Table 12. Relative accuracy specifications
Range

Relative Accuracy

All ranges±0.3 LSB, typ±0.5 LSB, max

Relative accuracy is defined as the measured deviation from a straight line drawn between measured endpointsof the transfer function.
Table 13. Differential non-linearity specifications
All ranges±0.3 LSB, typ±1.0 LSB, max

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Specifications

PCI-DAS6070

Analog output pacing and triggering
Table 14. AO pacing and triggering specifications
Parameter

Specification

DAC pacing(software programmable)

Internal counter – ASIC. Selectable time base: Internal 40 MHz
 External source via AUXIN<5:0>, SW selectable.
External convert strobe:
D/A UPDATE
Software paced
External digital:
D/A START TRIGGER
External analog:
ATRIG input
CH0 IN through CH15 IN
Software gatedExternal digital:
 Programmable, active high or active low, level or edge
External analog:
Refer to Analog trigger on page 9External digital:
D/A START TRIGGER
External analog:
ATRIG input
CH0 IN through CH15 IN
Software triggered
External digital: Software-configurable for rising or falling edge.
External analog:
Refer to Analog trigger on page 9
Available at user connector: D/A PACER OUT
16 K samples
DMA
Programmed I/OUpdate DACs individually or simultaneously, software selectable.
Demand or non-demand using scatter gather.
1 MS/s max per channel, 2 channels simultaneous

DAC gate source(software programmable)

DAC gating modes

DAC trigger sources

DAC triggering modes
DAC pacer out
RAM buffer size
Data transfer

DMA modes
Waveform generation throughput

Analog output external reference input (D/A EXTREF)
Table 15. External reference input (D/A EXTREF) specifications
Parameter

Specification

Range
Overvoltage protection
Input impedance
Bandwidth (–3 dB)
Gain error – EXTREF mode

±11 V
±25 V powered on, ±15 V powered off
10 kΩ
1 MHz
0 to 0.5%, not adjustable.

8Specifications

PCI-DAS6070

Analog trigger
Table 16. Analog trigger specifications
Parameter

Specification

Analog trigger sources
Software selectable
Analog trigger levels

External:

ATRIG input
CH0 IN through CH15 IN, first channel in scan

ATRIG input: ±10V
CH0 IN through CH15 IN: ± Full-scale, range dependent
External analog: Software-configurable for:
 Positive or negative slope
External analog: Software-configurable for:
 Above or below reference Positive or negative hysteresis
 In or out of window

Analog trigger modes
Analog gate modes

Resolution
Accuracy
Bandwidth (–3 dB)

8-bits, 1-in-256±5% full-scale range max
ATRIG input
CH0 IN through CH15 IN

1.3 MHz
2.0 MHz

Analog I/O calibration
Table 17. Analog I/O calibration specifications
Parameter

Specification

Recommended warm-up time
Calibration

15 minutes
Auto-calibration, calibration factors for each range stored on board in non-volatileRAM.
DC Level: 5.000 V± 2.5 mv. Actual measured values stored in EEPROM.
Tempco: 5 ppm/°C max, 2 ppm/°C typ
Long-term stability: 20ppm, T = 1000 hrs, non-cumulative
1 yearOnboard calibration reference

Calibration interval

Digital I/O
Table 18. DIO calibration specifications
Parameter

Specification

Digital type
Number of I/O
Configuration

Discrete, 5V/TTL compatible
8
8 bits, independently programmable for input or output. All pins pulled up to +5 V via
47 K resistors (default). Positions available for pull-down to ground.
Hardware selectable via solder gap.
2.0 V min, 7.0 V absolute max
0.8 V max, –0.5 V absolute min
3.80 V min, 4.20 V typ

Input high voltage
Input low voltage
Output high voltage(IOH = -32 mA)
Output low voltage(IOL = 32 mA)
Data transfer
Power-up / reset state0.55 V max, 0.22 V typ
Programmed I/O
Input mode (high impedance)

9Specifications

PCI-DAS6070

Interrupts
Table 19. Interrupt specifications
Parameter

Specification

Interrupts
Interrupt enable
ADC interrupt sources(software programmable)

PCI INTA# - mapped to IRQn via PCI BIOS at boot-time
Programmable through PLX9080
DAQ_ACTIVE: Interrupt is generated when a DAQ sequence is active.
DAQ_STOP:Interrupt is generated when A/D Stop Trigger In is detected.
DAQ_DONE: Interrupt is generated when a DAQ sequence completes.
DAQ_FIFO_1/4_FULL:
Interrupt is generated when ADC FIFO is ¼ full.
DAQ_SINGLE: Interrupt is generated after each conversion completes.
DAQ_EOSCAN: Interrupt is generated after the last channel is converted in multichannel scans.
DAQ_EOSEQ: Interrupt is generated after each interval delay during multi-channelscans.
DAC_ACTIVE: Interrupt is generated when DAC waveform circuitry is active.
DAC_DONE:Interrupt is generated when a DAC sequence completes.
DAC_FIFO_1/4_EMPTY:Interrupt is generated DAC FIFO is ¼ empty.
DAC_HIGH_CHANNEL:
Interrupt is generated when the DAC high channel output is
updated.

DAC interrupt sources(software programmable)

Counters
Table 20. Counter specifications
Parameter

Specification

User counter type
Number of channels
Resolution
Compatibility
CTRn base clock source(software selectable)
Internal 10 MHz clock source
stability
Counter n gate
Counter n output
Clock input frequency
High pulse width (clock input)
Low pulse width (clock input)
Gate width highGate width low
Input low voltage
Input high voltage
Output low voltage
Output high voltage

82C54
216-bits
5V/TTLInternal 10 MHz, internal 100 kHz, or external connector (CTRn CLK)50 ppmAvailable at connector (CTRn GATE).
Available at connector (CTRn OUT).
10 MHz max
15 ns min
25 ns min
25 ns min
25 ns min
0.8 V max
2.0 V min
0.4 V max
3.0 V min10

Specifications

PCI-DAS6070

Configurable AUXIN<5:0>, AUXOUT<2:0> external trigger/clocks
The PCI-DAS6070provides nine user-configurable trigger/clock pins available at the 100-pin I/O connector. Of
these, six are configurable as inputs while three are configurable as outputs.
Table 21. Configurable triggers/clocks specifications
Parameter

Specification

AUXIN<5:0> sources (software
selectable)

A/D CONVERT:
A/D TIMEBASE IN:
A/D START TRIGGER:
A/D STOP TRIGGER:
A/D PACER GATE:
D/A START TRIGGER:
D/A UPDATE:
D/A TIMEBASE IN:
STARTSCAN:SSH:

AUXOUT<2:0> sources(software selectable)

Default selections

Compatibility
Edge-sensitive polarity
Level-sensitive polarity
Minimum pulse width

External ADC convert strobe
External ADC pacer timebase
ADC Start Trigger
ADC Stop Trigger
External ADC gate
DAC trigger/gate
DAC update strobe
External DAC pacer time base
A pulse indicating start of conversion
Active signal that terminates at the start of the lastconversion in a scan.
Indicates end of scan
ADC convert pulse
Delayed version of ADC convert
CTR1 clock source
D/A update pulse
CTR2 clock source
ADC Start Trigger Out
ADC Stop Trigger Out
External ADC gate
DAC Start Trigger Out
A/D CONVERT
A/D START TRIGGER
A/D STOP TRIGGER
D/A UPDATE
D/A START TRIGGER
A/D PACER GATE
D/A UPDATE
A/D CONVERTSCANCLK

A/D STOP:
A/D CONVERT:SCANCLK:CTR1 CLK:
D/A UPDATE:CTR2 CLK:
A/D START TRIGGER:
A/D STOP TRIGGER:
A/D PACER GATE:
D/A START TRIGGER:
AUXIN0:
AUXIN1:
AUXIN2:
AUXIN3:
AUXIN4:
AUXIN5:
AUXOUT0:
AUXOUT1:
AUXOUT2:
5V/TTL
Rising/falling, software selectable
Active high/active low, software selectable
3.75 nS

11

Specifications

PCI-DAS6070

DAQ-Sync inter-board triggers/clocks
The DAQ-Sync bus provides inter-board triggering and synchronization capability. Five trigger/strobe I/O pins
and one clock I/O pin are provided on a 14-pin header. The DAQ-Sync signals use dedicated pins. Only the
direction may be set.
Table 22. DAQ-Sync signal specifications
Connector

Signal name

DAQ-Sync

DS A/D START TRIGGER
DS A/D STOP TRIGGER
DS A/D CONVERTDS D/A UPDATEDS D/A START TRIGGERSYNC CLKPower consumption
Table 23. Power consumption specifications
Parameter

Specification+5 V+5 V available at I/O connector

0.9 A typ, 1.1 A max. Does not include power consumed through the I/O connector.
1 A max, protected with a resettable fuse

Environmental
Table 24. Environmental specifications
Parameter

Specification

Operating temperature range
Storage temperature range
Humidity

0 °C to 55 °C–20 to 70 °C
0% to 90% non-condensing

Mechanical
Table 25. Mechanical specifications
Parameter

Specification

Card dimensions (L × W × H)

PCI half card: 174.4 (6.87) × 106.9 (4.21) × 11.65 mm (0.46 in.)

DAQ-Sync connector
Table 26. DAQ-Sync connector specifications
Parameter

Specification

Connector typeCompatible cables

14-pin right-angle 100mil box header
MCC p/n: CDS-14-x, 14-pin ribbon cable.
x = number of boards (2 to 5)

12

Specifications

PCI-DAS6070

Table 27. DAQ-Sync connector pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Signal NameDS A/D START TRIGGER
GND
DS A/D STOP TRIGGER
GND
DS A/D CONVERTGND
DS D/A UPDATEGND
DS D/A START TRIGGER
GND
RESERVEDGND
SYNC CLKGNDSCSI connector
Table 28. SCSI connector specifications
Parameter

Specification

Connector typeCompatible cables

Shielded SCSI 100 D-type
C100HD50-x, unshielded ribbon cable. x = 3 or 6 feet
C100MMS-x, shielded round cable. x = 1, 2, or 3 meters
ISO-RACK16/P
ISO-DA02/P
BNC-16SE
BNC-16DI
CIO-MINI50
CIO-TERM100
SCB-50
SCB-100

Compatible accessory products(with the C100HD50-x cable)

Compatible accessory products(with the C100MMS-x cable)

13Specifications

PCI-DAS6070

Table 29. 8-channel differential mode pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Signal Name
LLGND
CH0 IN HI
CH0 IN LO
CH1 IN HI
CH1 IN LO
CH2 IN HI
CH2 IN LO
CH3 IN HI
CH3 IN LO
CH4 IN HI
CH4 IN LO
CH5 IN HI
CH5 IN LO
CH6 IN HI
CH6 IN LO
CH7 IN HI
CH7 IN LO
LLGND
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
AISENSED/A OUT 0
D/A GND
D/A OUT1
PC +5 V
AUXOUT0 / D/A PACER OUT
AUXOUT1 / A/D PACER OUT
AUXOUT2 / SCANCLKAUXIN0 / A/D CONVERT / ATRIG
D/A EXTREF
AUXIN1 / A/D START TRIGGER
AUXIN2 / A/D STOP TRIGGER
AUXIN3 / D/A UPDATEAUXIN4 / D/A START TRIGGER
AUXIN5 / A/D PACER GATE
GND

Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

14

Signal Name
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
CTR1 CLK
CTR1 GATE
CTR1 OUTGND
CTR2 CLK
CTR2 GATECTR2 OUT
GND

Specifications

PCI-DAS6070

Table 30. 16-channel single-ended mode pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Signal Name
LLGND
CH0 IN
CH8 IN
CH1 IN
CH9 INCH2 IN
CH10 IN
CH3 IN
CH11 IN
CH4 IN
CH12 IN
CH5 IN
CH13 IN
CH6 IN
CH14 IN
CH7 IN
CH15 IN
LLGND
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
AISENSED/A OUT 0
D/A GND
D/A OUT1
PC +5 V
AUXOUT0 / D/A PACER OUT
AUXOUT1 / A/D PACER OUT
AUXOUT2 / SCANCLKAUXIN0 / A/D CONVERT / ATRIG
D/A EXTREF
AUXIN1 / A/D START TRIGGER
AUXIN2 / A/D STOP TRIGGER
AUXIN3 / D/A UPDATEAUXIN4 / D/A START TRIGGER
AUXIN5 / A/D PACER GATE
GND

Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

15

Signal Name
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
CTR1 CLK
CTR1 GATE
CTR1 OUTGND
CTR2 CLK
CTR2 GATECTR2 OUT
GND

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