7210-TQFP-R

IEEE 488.2 Controller chip – replacement for NEC µPD7210

7210-TQFP-R

RoHS-compliant
Pin-compatible with NEC µPD7210
Software-compatible with NEC µPD7210
Low power consumption
Meets all IEEE 488.2 requirements:○ Bus line monitoring○ Preferred implementation of requesting service○ Sends no messages when there are no listeners
Performs all IEEE 488.1 interface functions SH1,AH1, T5 or TE5, L3 or LE3, SR1, RL1, PP1, PP2,DC1, DT1, C1, C2, C3, C4, C5
Reduces driver overhead

Overview
Measurement Computing Corporation's 7210-TQFP-R is a44-pin DIP replacement part for the NEC µPD7210. The7210-TQFP-R is 100% register-compatible and pincompatible with the NEC µPD7210 on power up. The
7210-TQFP-R performs all of the interface functions definedby the ANSI/IEEE Standard 488.1-1987, and it meets theadditional requirements and recommendations of ANSI/IEEE
Standard 488.2-1987. The 7210-TQFP-R performs complete
IEEE 488 talker, listener, and controller functions.
On power up, the 7210-TQFP-R contains the complete registerset of the NEC µPD7210, but can perform complete IEEE488.2 controller functions through software.
If you are an instrument developer, you can take advantage ofIEEE 488.2 with minimal software modifications yet keep the44-pin hardware configuration. The default clock input is
8 MHz, but increased performance is available from the7210-TQFP-R through software-selectable input values up to20 MHz.
If you are an IEEE 488 instrument manufacturer looking foralternatives to existing NEC µPD7210 chip suppliers orplanning to upgrade your designs to IEEE 488.2 without
hardware changes, consider using the 7210-TQFP-R. Becausethe 7210-TQFP-R accepts faster clock inputs, performanceincreases without many firmware changes.


Does not lose a data byte if ATN is asserted whiletransmitting data
Static interrupt status bits that do not clear when read
Programmable data transfer rate
(T1 delays of 350 ns, 500 ns, 1.1 µs, and 2 µs)
Automatic EOS and/or NL message detection
Direct memory access (DMA)
Automatically processes IEEE 488 commands andreads undefined commands
Programmable compatible with bus transceivers (T1,National Semiconductor, Motorola, and Intel)
TTL-compatible CMOS device
Programmable clock rate up to 20 MHz

GeneralThe 7210-TQFP-R manages the IEEE 488 bus. You program
the IEEE 488 bus by writing control words into theappropriate registers. CPU-readable status registers supply
operational feedback. The 7210-TQFP-R mode determines thefunction of these registers. When in 7210 mode, the registers
resemble the µPD7210 register set with additional registers
that supply extra functionality and IEEE 488.2 compatibility.
In this mode, the 7210-TQFP-R is completely pin-compatible
with the NEC µPD7210. Figure 1 shows the key componentsof the 7210-TQFP-R.

RoHS Compliance
The 7210-TQFP-R is available from MCC as a RoHScompliant chip. The chip is marked with an e3 inside anellipse to indicate a matte pure tin finish on the leads, inaccordance with the marking recommendations defined in
JEDEC JESD97.
The RoHS-compliant 7210-TQFP-R meets industry
requirements for baking and maximum solder reflow
temperature. The baking requirements are outlined in JEDEC
J-STD-033. MCC recommends using the solder reflow profileas shown in IPC/JEDEC J-STD-020C with a peak temperatureof 260 °C, the maximum temperature they can withstand.

Ordering Information
RoHS-compliant chip
44-pin LQFP package

MCC Part number
7210-TQFP-R

August 2019. Rev 2
DS 7210-TQFP-R.docx

Copyright © Measurement Computing Corporation

Block Diagram

Figure 1. 7210-TQFP-R block diagram
Page 2

Pin Descriptions

22212019181716151413121234567891011343536373839404142
43
44

REN
IFC
RS2RS1RS0
GND
+5
D7
D6
D5
D4DRQ
DACKCS
RDWR
GND
INT
D0
D1
D2
D3DAV
NRFD
NDAC
EOI+5GND
T/R1T/R2
CLKRESET
T/R33332313029282726252423

DIO8
DIO7
DIO6
DIO5
DIO4
GND
DIO3
DIO2
DIO1
SRQ
ATN

The following table describes the 7210-TQFP-R pins.

Figure 2. 7210-TQFP-R pin configuration

Pin Identification
Pin #1
2

Table 1. 7210-TQFP-R pin configuration

I

Description
DMA Request. Requests data transfer. Becomes low on input of DMA acknowledge signal DACK.
DMA Acknowledge. (Active low) Signal connects the computer system data bus to the data register of the7210-TQFP-R.
Chip Select. (Active low) Enables access to the register selected by RS0-RS2 (read or write operation).

I

Read. (Active low) Places contents of read register specified RS0-RS2 on D0-D7 (computer bus).

WRGND
INT

I

Write. (Active low) Writes data on D0-D7 into the write register specified by RS0-RS2.

8-15
16, 38
18-20
21

D0-D7+5 (VCC )RS0-RS2

I/O
I/O
I
I/O

GroundInterrupt Request. (Active high/low) Becomes active due to any 1 of 13 internal interrupt conditions(unmasked). Active state software configurable. Active high on chip reset.
Data Bus. 8-bit bidirectional data bus for interface to the computer system.
+5 VDC (±5%)
Register Select. These lines select one of eight read (write) registers during a read (write) operation.
Interface Clear. Control line used for clearing the interface functions.

22REN

I/O

Remote Enable. Control line used to enable remote operation of the devices.

ATN

I/O

SRQ

I/O

Attention. Control line which indicates whether data on DIO lines is an interface message or device
dependent message.
Service Request. Control line used to request service from the controller.

DIO1- DIO8I/OData Input/Output. 8-bit bi-directional bus for transfer of message.

DAVI/O

Data Valid. Handshake line indicating that data on DIO lines is valid.

NRFD

I/O

Ready for Data. Handshake line indicating that device is ready for data.

NDAC

I/O

Data Accepted. Handshake line indicating completion of message reception.

EOI

I/O

T/R1
T/R2

OO

42

CLKI

End or Identity. Control line used to indicate the end of multiple byte transfer sequence or to execute aparallel polling in conjunction with ATN.
Transmit/Receive Control. Input/output control signal for the GPIB bus transceivers.
Transmit/Receive Control. The values of T/R2 and T/R3 are determined by the values of the Address
Mode register bits TRM1, and TRM0.
Clock. 1 MHz to 20 MHz reference clock for generating the state change prohibit times T1, T6, T7, T9
specified in IEEE Standard 488.2-1992.

4344

RESET
T/R3IO345
6, 17, 28, 39
7

23
24
25-33
34
35
36
37
40
41

Page 3

Mnemonic I/O
DRQOIDACKCSRDIFCOReset. Resets the 7210-TQFP-R to an idle state when high (active high).
Transmit/Receive Control. See T/R2 (pin 41).

Mechanical Data
Controlling dimensions are in millimeters.

Figure 3. Package outline

Page 4

7210 Mode Registers

DC Characteristics

In 7210 mode, the 7210-TQFP-R registers include all the NECµPD7210 registers plus two types of additional registers –extra auxiliary registers and paged-in registers. You write theextra auxiliary registers in the same way as standard µPD7210
auxiliary registers. Upon issuing an auxiliary page-incommand, the paged-in registers appear at the same offsets asexisting µPD7210 registers. At the end of the next CPU
access, the chip pages out the paged-in registers. The
following table lists the registers in the 7210 mode register set.

7210 Register SetRegister

Page-InUX
UA(2-0)

WR*

RD*

CS*

DACK*

Data-in000
100
1
Data-inXXX
10
X
0Command/data000
0
10
1out
Command/dataX
XXX
01
X
0out
Interrupt status1
U001
1001
Interrupt mask1
U001
0101
Interrupt status2
U010
1001
Interrupt mask2
U010
0101
Serial poll statusN011
1001
Serial poll modeN0110101VersionP011
1001
Initial counter2
P011
0101Address statusU
1001001Address mode
U
1000101Command passN
101
1001throughAuxiliary mode
U
101
0
101
Source/acceptor
P1011001status†
Address 0
N
1101001AddressN110
0101Interrupt statusP
110
10010†
Interrupt mask 0†P
1100101Address†
N
111
100
1End-of-stringN
111
0101Bus status†
P
111
1001Bus control†
P
111
0101Notes for the Page-In column:
U = The page-in auxiliary command does not affect the register.
N = The register offset is always valid except for immediately after apage-in auxiliary command.
P = The register is valid only immediately after a page-in auxiliarycommand.
The † symbol indicates features that are not available in the µPD7210,
such as register and auxiliary commands.

Page 5

Parameter

SymbolLimitsUnit

Max+0.8

V

Test
Conditions

Voltage input
lowVILMin-0.5

Voltage input
highVoltage output
low

VIH+2.0

VCCVVOL00.4V

Voltage output
highInput/output
leakagecurrent
Input/output
leakagecurrent
SupplyCurrent
Output current
low (all pinsexcept T/R1)
T/R1
Input current
low/high
Output current
highSupplyvoltage

VOH+2.4

VCC

V

-10

+10µA

w/o internal
pull-up-200+200µA

withinternal
pull-up

45mA

IOL

2IOL
IIL

4

IOH

-1

mA

VCC

4.75

5.25

-0.5

mA

VOL=0.4 V

mA
mA

VOL=0.4 V

V0H=VCC0.5 V
VCapacitanceTA0 to 70 °C; Vcc= 5 V ±5%
Parameter
Input
capacitance
OutputcapacitanceI/Ocapacitance

SymbolLimits

UnitMax
10pF

Cout

10pF

CI/O

10pF

CinMinTest Conditions

Absolute Maximum Ratings
Property

Test Conditions

Supply voltage, VCC-0.5 to +6.0 V
Input voltage, VI-0.5 to VCC +0.5
Operating temperature,
0 to +70 °C
TOPR
Storage temperature,-40 to +125 °C
TSTG
Caution: Exposing the device to stresses above those listed could
cause permanent damage. The device is not meant to be operated
under conditions outside the operational limits. Exposure to absolutemaximum rating conditions for extended periods may affect reliability.

AC Characteristics
TA0 to 70 °C; Vcc= 5 V ±5%Parameter

Sym.

LimitsAddress hold fromRD ↑ WR ↑tAHtAS

0Data float from RD ↑

tDF

25

ns

tDR

80

ns

tDUtRD85

25
nsns
CS=0tRR
tRWtWS

120
85
60

nsns
nstWH

0ns

Address setup to RD ↓WR ↓Data delay from RD ↓DRQ unassertion
Data delay from RD ↓RD recovery width
RD pulse width
Data setup to WR ↑Data hold from WR ↑Max

Figure 5. DMA ReadPage 6

TestConditions

nsns

Timing Waveforms

Figure 4. CPU Read

UnitMin0Figure 6. CPU Write

Figure 7. DMA Write

DACK=0Source Handshake
Parameter

Response to ATN

Sym.

NDAC ↑ to DAV ↑tND

NDAC ↑ to INT ↑ orDRQ ↑tNI

LimitsMin

Test Conditions

Max4040

WR ↑ to DAV ↓tWD

2,000

2,125

WR ↑ to DAV ↓tWD

1,125

1,250

WR ↑ to DAV ↓tWD

500625WR ↑ to DAV ↓tWD

375500INT (DO IE Bit = 1)
DRQ (DMAO Bit = 1)2 µs T1(8 MHz, 50% duty)
1.1 µs T1(8 MHz, 50% duty)
500 ns T1(8 MHz, 50% duty)
350 ns T1(8 MHz, 50% duty)

Parameter

Sym.

Limits
MinMax35

Test Conditions

ATN ↑ to NRFD ↓t∆FtAN

35

Acceptor handshake
Holdoff
AIDS → ANRSATN ↓ to TE ↓tAT

30

TACS → TADS

ATN ↓ to NDAC ↓Figure 10. Response to ATN

Parallel Poll
Parameter

Figure 8. Source Handshake

Acceptor Handshake
Parameter

Sym.

DAV ↓ to NDAC ↑tDD

Limits
MinMax225

DAV ↑ to NDAC ↓tDD

20tNI

116

DAV ↓ to NRFD ↓tDR

25tNR

30

DAV ↓ to INT ↑ orDRQ ↑RD ↑ to NRFD ↑EOI ↓ to TE ↑EOI ↑ to TE ↓LimitsPPSS › PPAStET25

PPSS › PPAStTE25

PPAS › PPSS

8 MHz, 50% duty
INT (DIIE Bit = 1)
DRQ (DMAI Bit = 1)
Read of DIR, not in
Holdoff state

Test Conditions

Max90

tFD

Min

Test Conditions

Figure 9. Acceptor Handshake

Page 7

EOI ↓ to DIO valid

Sym.

Figure 11. Parallel Poll

Typical System

Figure 12. Typical CPU System with the 7210-TQFP-R

Contact usContact us if you need assistance in developing the interface to your particular system. Our engineering staff will work with you toensure that your 7210-TQFP-R interface is simple, efficient and allows access to all chip features.
Page 8Phone: 508-946-5100 and follow the instructions for reaching Tech Support
Fax: 508-946-9500 to the attention of Tech Support
Email: techsupport@mccdaq.com

Measurement Computing Corporation
10 Commerce Way
Norton, Massachusetts 02766(508) 946-5100
E-mail: info@mccdaq.com
www.mccdaq.com

NI Hungary Kft
H-4031 Debrecen, Hátar út 1/A, Hungary
Phone: +36 (52) 515400
Fax: +36 (52) 515414
hungary.ni.com/debrecen