DATA SHEET
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Integrated Driver and
MOSFET
NCP302150
PQFN31 5X5, 0.5P
CASE 483BR

The NCP302150 integrates a MOSFET driver, high−side MOSFET
and low−side MOSFET into a single package.
The driver and MOSFETs have been optimized for high−current
DC−DC buck power conversion applications. The NCP302150
integrated solution greatly reduces package parasitics and board spacecompared to a discrete component solution.

MARKING DIAGRAM

NCP
302150AWLYYWW

Features• Capable of Average Currents up to 50 A
• Capable of Switching at Frequencies up to 2 MHz• Compatible with 3.3 V or 5 V PWM Input• Responds Properly to 3−level PWM Inputs• Option for Zero Cross Detection with 3−level PWM• Internal Bootstrap Diode• Undervoltage Lockout• Supports Intel® Power State 4• Thermal Warning Output• Thermal Shutdown

A
WL
YY
WW

= Assembly Location= Wafer Lot= Year= Work Week

PWM

32
AGND

Converters

PWM from controller
SMOD from controller

DISB#

SMOD#
VSW

VOUT

PGND

19

20

21

22

VSW

VSW

VSW

VSW

VSW

VSW

PGND
GL
VSW
VSW
VSW

23
VSW

18

VCCD

© Semiconductor Components Industries, LLC, 2018

DevicePackage

Shipping†

NCP302150MNTWG

PQFN315x53000 / Tape &Reel†For information on tape and reel specifications,
including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

Figure 1. Application SchematicJanuary, 2024 − Rev. 7

17

THWN

ORDERING INFORMATION

BOOT

PWM

CGND

16

DISB#

VIN
THWN

DRVON from controller

15

PGND

14

PGND

VSW

PGND

5V

VCCD VCC

PGND

13DC−DC Converters• High−Current DC−DC Point−of−Load Converters• Small Form−Factor Voltage Regulator Modules

33
GL

12

• Desktop and All−in−One Computers, V−Core and Non−V−Core

31

1

30

SMOD#
2

29

VCC
3

28

CGND
4

27

BOOT
5

26

nc
6

25

PHASE
7

11

VIN

8

24

VIN

10

• Notebook, Tablet PC and Ultrabook• Servers and Workstations, V−Core and Non−V−Core DC−DC

9

Applications

VIN

VIN

PINOUT DIAGRAM

1

Publication Order Number:
NCP302150/D

NCP302150
VCCD 29

VCC

5 BOOT

3
VCC

SMOD#

2

PWM

1

8−11 VIN

LEVEL
SHIFT

UVLO

16−26 VSW

7 PHASEDEAD
TIME
CONTROLSHUTDOWNTEMPWARNING SENSEDISB# 31

LEVEL
SHIF
28 PGNDTHWN 30

12−15 PGND
27 GL

AGND 32
CGND

33 GL

ZCD
CONTROL

4

Figure 2. Block Diagram

Table 1. PIN LIST AND DESCRIPTION
Pin No.

SymbolDescription

1

PWM

PWM Control Input and Zero Current Detection Enable

2

SMOD#

Skip Mode pin. 3−state input (see Table 6):
SMOD# = High ³ State of PWM determine whether the NCP302150 performs ZCD or not.
SMOD# = Mid ³ Connects PWM to internal resistor divider placing a bias voltage on PWM pin.
Otherwise, logic is equivalent to SMOD# in the high state.
SMOD# = Low ³ Placing PWM into mid−state pulls GH and GL low without delay.
There is an internal pull−up resistor to VCC on this pin.

3

VCC

4, 32

CGND, AGND

5

BOOT

Bootstrap Voltage

6ncOpen pin (not used)

7

PHASE

8−11

VIN

Conversion Supply Power Input

12−15, 28

PGND

Power Ground

16−26

VSW

Switch Node Output

27, 33GL

Low Side FET Gate Access (pin 27 and pad 33 are internally connected)

29

VCCD

Driver Power Supply Input

30

THWN

Thermal warning indicator. This is an open−drain output. When the temperature at the driver die
reaches TTHWN, this pin is pulled low.

31

DISB#

Output disable pin. When this pin is pulled to a logic high level, the driver is enabled. There is aninternal pull−down resistor on this pin.

Control Power Supply Input
Signal Ground (pin 4 and pad 32 are internally connected)

Bootstrap Capacitor Return

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NCP302150
Table 2. ABSOLUTE MAXIMUM RATINGS (Electrical Information − all signals referenced to PGND unless noted otherwise)
Min

Max

Unit

VCC, VCCD

−0.3

6.5

V

VIN

−0.3

30

V

VIN to PHASE (DC)

−0.3

30

V

Pin Name / Parameter

VIN to PHASE (< 5 ns)

35

V

BOOT (DC)

−0.3

35

V

BOOT (< 20 ns)

−0.3

40

V

BOOT to PHASE (DC)

−0.3

6.5

V

BOOT to PHASE (< 20 ns)

−0.3

9.0

V

VSW, PHASE (DC)

−0.3

30

V

VSW, PHASE (< 20 ns)

−5

35

V

PHASE (< 5 ns)

−15

35

V

All Other Pins

−0.3

VVCC + 0.3

V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

Table 3. THERMAL INFORMATION
RatingSymbol

Value

Unit

qJA

12.4

_C/W

qJ−PCB

1.8_C/W

Operating Junction Temperature Range (Note 1)

TJ−40 to +150

_C

Operating Ambient Temperature RangeTA−40 to +125

_C

Maximum Storage Temperature Range

TSTG−55 to +150

_C

10.5

W

Thermal Resistance (under On Semi SPS Thermal Board)

Maximum Power Dissipation
Moisture Sensitivity Level

MSL

1

1. The maximum package power dissipation must be observed.
2. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
3. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM

Table 4. RECOMMENDED OPERATING CONDITIONSParameter

Pin Name

Conditions

Min

Typ

Max

Unit

Supply Voltage Range

VCC, VCCD

4.5

5.0

5.5

V

Conversion Voltage

VIN

4.5

12

20

V

FSW = 1 MHz, VIN = 12 V, VOUT = 1.0 V, TA = 25_C

45

A

FSW = 300 kHz, VIN = 12 V, VOUT = 1.0 V, TA = 25_C

50

A

Duration = 5 ms, Period = 10 ms

85

A

125

_C

Continuous Output Current
Peak Output Current
Junction Temperature−40

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

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NCP302150
Table 5. ELECTRICAL CHARACTERISTICS(VVCC = VVCCD = 5.0 V, VVIN = 12 V, VDISB# = 2.0 V, CVCCD = CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid for thetemperature range −40°C ≤ TJ ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
Parameter

SymbolConditions

Min.

Typ.

Max.

Unit

1

2

mA

VCC SUPPLY CURRENT
Operating

DISB# = 5 V, PWM = 400 kHz−

No switching

DISB# = 5 V, PWM = 0 V

−

−

2

mA

Disabled

DISB# = 0 V, SMOD# = VCC

−

0.4

1

mA

6

13

mA

2.89

−

3.37

V

150

−

−

mV

DISB# = 0 V, SMOD# = GNDUVLO Start Threshold

VUVLO

VCC rising

UVLO Hysteresis
VCCD SUPPLY CURRENT
Enabled, No switching

DISB# = 5 V, PWM = 0 V,
VPHASED = 0 V

−

175

300

mA

Disabled

DISB# = 0 V

−

0.4

1

mA

Operating

DISB# = 5 V, PWM = 400 kHz

−

−

20

mA

DISB# = 5 V, PWM = 400 kHz

−

467

−

kW

DISB# INPUT
Input ResistanceUpper Threshold

VUPPER

DISB# = 5 V, PWM = 0 V

−

−

2.0

V

Lower Threshold

VLOWER

DISB# = 5 V, PWM = 0 V

0.8

−

−

V

Hysteresis

DISB# = 5 V, PWM = 400 kHz

200

−

−

mV

Enable Delay Time

DISB# = 5 V, PWM = 0 V

−

−

40

ms

Disable Delay Time

DISB# = 5 V, PWM = 0 V

−

21

50

ns

SMOD# INPUT
SMOD# Input Voltage HighVSMOD_HI

2.65

−

−

V

SMOD# Input Voltage Mid−state

VSMOD#_MID

1.4

−

2.0

V

SMOD# Input Voltage Low

VSMOD_LO

−

−

0.7

V

SMOD# Input Resistance

RSMOD#_UP

Pull−up resistance to VCC

−

455

−

kW

SMOD# Propagation Delay, Falling

TSMOD#_PD_F

SMOD# = Low to GL = 90%,
PWM = MID

−

34

42

ns

SMOD# Propagation Delay, Rising

TSMOD#_PD_R

SMOD# = High to GL = 10%,PWM = MID

−

22

30

ns

PWM INPUT
Input Voltage HighVPWM_HI

2.65

−

−

V

Input Mid−state Voltage

VPWM_MID

1.4

−

2.0

V

Input Low Voltage

VPWM_LO

−

−

0.7

V

Input Resistance

RPWM_HIZ

SMOD# = VSMOD#_HI or
VSMOD#_LO

10

−

−

MW

Input Resistance

RPWM_BIAS

SMOD# = VSMOD#_MID

−

68

−

kW

PWM Input Bias Voltage

VPWM_BIAS

SMOD# = VSMOD#_MID

−

1.7

−

V

Non−overlap Delay, Leading Edge

TNOL_LGL Falling = 1 V to GH−VSW Rising = 1 V

−

13

−

ns

Non−overlap Delay, Trailing Edge

TNOL_T

GH−VSW Falling = 1 V to
GL Rising = 1 V

−

12

−

ns

PWM Propagation Delay, Rising

TPWM,PD_R

PWM = High to GL = 90%

−

13

35

ns

PWM Propagation Delay, Falling

TPWM,PD_F

PWM = Low to SW = 90%

−

47

52

ns

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NCP302150
Table 5. ELECTRICAL CHARACTERISTICS(VVCC = VVCCD = 5.0 V, VVIN = 12 V, VDISB# = 2.0 V, CVCCD = CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid for thetemperature range −40°C ≤ TJ ≤ 125°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.)
Parameter

SymbolConditions

Min.

Typ.

Max.

Unit

Exiting PWM Mid−state Propagation Delay, Mid−to−Low

TPWM_EXIT_L

PWM = Mid−to−Low to GL = 10%

−

14

25

ns

Exiting PWM Mid−state Propagation Delay, Mid−to−High

TPWM_EXIT_H

PWM = Mid−to−High to SW = 10%

−

13

25

ns

ZD FUNCTION
Zero Cross Detect Threshold

VZCD

−

−6

−

mV

ZCD Blanking + Debounce Time

tBLNK

−

330

−

ns

−

150

−

_C

−

15

−

_C

−

180

−

_C

THERMAL WARNING & SHUTDOWN
Thermal Warning Temperature

TTHWN

Temperature at Driver Die

Thermal Warning Hysteresis

TTHWN_HYS

Thermal Shutdown Temperature

TTHDN

Thermal Shutdown Hysteresis

TTHDN_HYS

−

25

−

_C

THWM Open Drain Current

ITHWN

−

−

5

mA

Forward Bias Current = 2.0 mA

−

380

−

mV

Source Current = 100 mA

−

0.9

−

W

−

2

−

A

−

0.7

−

W

−

2.5

−

A

Temperature at Driver Die

BOOSTSTRAP DIODE
Forward Voltage
HIGH−SIDE DRIVER
Output Impedance, Sourcing

RSOURCE_GH

Output Sourcing Peak Current

ISOURCE_GH

Output Impedance, Sinking

RSINK_GH

Output Sinking Peak Current

ISINK_GH

Sink Current = 100 mA

LOW−SIDE DRIVER
Output Impedance, Sourcing

RSOURCE_GL

Source Current = 100 mA

−

0.9

−

W

Output Sourcing Peak Current

ISOURCE_GL

GL = 2.5 V

−

2

−

A

Output Impedance, Sinking

RSINK_GL

Sink Current = 100 mA

−

0.4

−

W

Output Sinking Peak Current

ISINK_GL

GL = 2.5 V

−

4.5

−

A

GL Rise Time

TR_GL

GL = 10% to 90%, CLOAD = 3.0 nF

−

12

−

ns

GL Fall Time

TF_GL

GL = 90% to 10%, CLOAD = 3.0 nF

−

6

−

ns

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.

Table 6. LOGIC TABLE
INPUT TRUTH TABLE
DISB#

PWM

SMOD# (Note 4)

GH (not a pin)

GL

L

X

X

L

L

H

H

X

H

L

H

L

X

L

H

H

MID

H or MID

LZCD (Note 5)

H

MID

L

L

L (Note 6)

4. PWM input is driven to mid−state with internal divider resistors when SMOD# is driven to mid−state and PWM input is undriven externally.
5. GL goes low following 80 ns de−bounce time, 250 ns blanking time and then SW exceeding ZCD threshold.
6. There is no delay before GL goes low.

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NCP302150
TYPICAL PERFORMANCE CHARACTERISTICS
Test Conditions: VIN = 12 V, VCC = VCCD = 5 V, VOUT = 1 V, LOUT = 250 nH, TA = 25 °C and natural convection cooling, unlessotherwise noted.

Figure 3. Efficiency − 19 V Input, 1.0 V Output

Figure 4. Efficiency − 19 V Input, 1.8 V Output

Figure 5. Efficiency − 12 V Input, 1.0 V Output

Figure 6. Efficiency − 12 V Input, 1.8 V Output

Figure 7. Power losses vs. Output Current, 12Vin

Figure 8. Power losses vs. Output Current, 19Vin

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NCP302150
TYPICAL PERFORMANCE CHARACTERISTICS
Test Conditions: VIN = 12 V, VCC = PVCC = 5 V, VOUT = 1 V, LOUT = 250 nH, TA = 25 °C and natural convection cooling, unlessotherwise noted.

Figure 9. Power Loss vs. Switching Frequency

Figure 10. Power Loss vs. Input Voltage

Figure 11. Power Loss vs. Driver Supply Voltage

Figure 12. Power Loss vs. Output Voltage

Figure 13. Driver Supply Current vs. Switching
Frequency

Figure 14. Driver Supply Current vs. Driver
Supply Voltage

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NCP302150
Theory of Operation

Safety Timer and Overlap Protection Circuit

The NCP302150 is an integrated driver and MOSFET
module designed for use in a synchronous buck converter
topology. The NCP302150 supports numerous application
control definitions including ZCD (Zero Current Detect)and alternately PWM Tristate control. A PWM input signal
is required to control the drive signals to the high−side andlow−side integrated MOSFETs.

It is important to avoid cross−conduction of the two
MOSFETS which could result in a decrease in the power
conversion efficiency or damage to the device.
The NCP302150 prevents cross−conduction bymonitoring the status of the MOSFETs and applying theappropriate amount of non−overlap (NOL) time (the time
between the turn−off of one MOSFET and the turn−on of theother MOSFET). When the PWM input pin is driven high,
the gate of the low−side MOSFET (LSGATE) goes low after
a propagation delay (tpdlGL). The time it takes for thelow−side MOSFET to turn off is dependent on the total
charge on the low−side MOSFET gate.
The NCP302150 monitors the gate voltage of both
MOSFETs and the switch node voltage to determine theconduction status of the MOSFETs. Once the low−side
MOSFET is turned off an internal timer delays (tpdhGH) theturn−on of the high−side MOSFET. When the PWM input
pin goes low, the gate of the high−side MOSFET (HSGATE)
goes low after the propagation delay (tpdlGH). The time toturn off the high−side MOSFET (tfGH) is dependent on the
total gate charge of the high−side MOSFET. A timer istriggered once the high−side MOSFET stops conducting, todelay (tpdhGL) the turn−on of the low−side MOSFET.

Low−Side DriverThe
low−side
driverdrivesaninternal,
ground−referenced low−RDS(on) N−Channel MOSFET.
The voltage supply for the low−side driver is internallyconnected to the VCCD and PGND pins.
High−Side Driver

The high−side driver drives an internal, floating
low−RDS(on) N−channel MOSFET. The gate voltage for thehigh side driver is developed by a bootstrap circuit
referenced to Switch Node (VSW and PHASE) pins.
The bootstrap circuit is comprised of the integrated diodeand an external bootstrap capacitor and resistor. When the
NCP302150 is starting up, the VSW pin is at ground,allowing the bootstrap capacitor to charge up to VCCD
through the bootstrap diode (See Figure 1). When the PWM
input is driven high, the high−side driver turns on thehigh−side MOSFET using the stored charge of the bootstrap
capacitor. As the high−side MOSFET turns on, the voltage
at the VSW and PHASE pins rises. When the high−side
MOSFET is fully turned on, the switch node settles to VIN
and the BST pin settles to VIN + VCCD (excluding parasitic
ringing).

Zero Current Detect

The bootstrap circuit relies on an external charge storage
capacitor (CBST) and an integrated diode to provide current
to the HS Driver. A multi−layer ceramic capacitor (MLCC)
with a value greater than 100 nF should be used as thebootstrap capacitor. An optional 1 to 4 W resistor in series
with the bootstrap capacitor decreases the VSW overshoot.

The Zero Current Detect PWM (ZCD_PWM) mode isenabled when SMOD# is high (see Tables 6 and 8).
With PWM set to > VPWM_HI, GL goes low and GH
goes high after the non−overlap delay. When PWM is driven
to < VPWM_HI and to > VPWM_LO, GL goes high after
the non−overlap delay, and stays high for the duration of the
ZCD blanking timer (TZCD_BLANK) and an 80 ns de−bounce
timer. Once this timer expires, VSW is monitored for zerocurrent detection, and GL is pulled low once zero current is
detected. The threshold on VSW to determine zero current
undergoes an auto−calibration cycle every time DISB# isbrought from low to high. This auto−calibration cycle
typically takes 25 ms to complete.

Power Supply Decoupling

PWM Input

Bootstrap Circuit

The PWM Input pin is a tri−state input used to control the
HS MOSFET ON/OFF state. It also determines the state of
the LS MOSFET. See Table 6 for logic operation. The PWM
in some cases must operate with frequency programming
resistances to ground. These resistances can range from
10 kW to 300 kW depending on the application. When
SMOD# is set to > VSMOD#_HI or to < VSMOD#_LO, theinput impedance to the PWM input is very high in order toavoid interferences with controllers that must use
programming resistances on the PWM pin.
If SMOD# is set to < VSMOD#_HI and > VSMOD#_LO(Mid−State), the PWM pin undriven default voltage is set toMid−State with internal divider resistances.

The NCP302150 sources relatively large currents into the
MOSFET gates. In order to maintain a constant and stablesupply voltage (VCCD) a low−ESR capacitor should beplaced near the power and ground pins. A multi−layer
ceramic capacitor (MLCC) between 1 mF and 4.7 mF istypically used.
A separate supply pin (VCC) is used to power the analog
and digital circuits within the driver. A 1 mF ceramic
capacitor should be placed on this pin in close proximity to
the NCP302150. It is good practice to separate the VCC andVCCD decoupling capacitors with a resistor (10 W typical)
to avoid coupling driver noise to the analog and digital
circuits that control the driver function (See Figure 1).

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NCP302150
Disable Input (DISB#)

Thermal Warning/Thermal Shutdown Output

The DISB# pin is used to disable the GH to the High−Side
FET to prevent power transfer. The pin has a pull−downresistance to force a disabled state when it is left
unconnected. DISB# can be driven from the output of a logic
device or set high with a pull−up resistance to VCC.

The THWN pin is an open drain output. When thetemperature of the driver exceeds TTHWN, the THWN pin ispulled low indicating a thermal warning. At this point, thepart continues to function normally. When the temperaturedrops TTHWN_HYS below TTHWN, the THWN pin goes high. If
the driver temperature exceeds TTHDN, the part entersthermal shutdown and turns off both MOSFETs. Once thetemperature falls TTHDN_HYS below TTHDN, the part resumes
normal operation.

VCC Undervoltage Lockout

The VCC pin is monitored by an Undervoltage Lockout
Circuit (UVLO). VCC voltage above the rising thresholdenables the NCP302150.

Skip Mode Input (SMOD#)The SMOD# tri−state input pin has an internal pull−up
resistance to VCC. When driven high, the SMOD# pinenables the low side synchronous MOSFET to operate
independently of the internal ZCD function. When the
SMOD# pin is set low during the PWM cycle it disables thelow side MOSFET to allow discontinuous mode operation.
The NCP302150 has the capability of internallyconnecting a resistor divider to the PWM pin. To engage thismode, SMOD# needs to be placed into mid−state. While in
SMOD# mid−state, the IC logic is equivalent to SMOD#
being in the high state.

Table 7. UVLO/DISB# LOGIC TABLE
UVLO

DISB#

Driver StateL

X

Disabled (GH = GL = 0)

H

L

Disabled (GH = GL = 0)

H

H

Enabled (See Table 1)

H

Open

Disabled (GH = GL = 0)

NOTE: If the Zero Current Detect circuit detects zero current after the ZCD Wait timer period, the GL is driven low by
the Zero Current Detect signal.
If the Zero Current Detect circuit detects zero current before the ZCD Wait timer period expires, the Zero Current
detect signal is ignored and the GL is driven low at the end of the ZCD Wait timer period.
NOTE: If the SMOD# input is driven low at any time after the GL has been driven high, the SMOD# Falling edge
triggers the GL to go low.
If the SMOD# input is driven low while the GH is high, the SMOD# input is ignored.

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NCP302150
Inductor
Current

PWM

GH
SMOD#
triggered

GL

SMOD#

Figure 15. SMOD# Timing Diagram

NOTE: If the SMOD# input is driven low at any time after the GL has been driven high, the SMOD# Falling edge
triggers the GL to go low.
If the SMOD# input is driven low while the GH is high, the SMOD# input is ignored.
For Use with Controllers with 3−State PWM
Controllers Detection Capability
Table 8. LOGIC TABLE − 3−STATE PWM CONTROLLERS WITH NO ZCD
PWM

SMOD#

GH (not a pin)

GL

H

H

ON

OFF

M

H

OFF

ZCD

L

H

OFF

ON

and low states. To enter into DCM, PWM needs to be
switched to the mid−state.
Whenever PWM transitions to mid−state, GH turns off
and GL turns on. GL stays on for the duration of thede−bounce timer and ZCD blanking timers. Once thesetimers expire, the NCP302150 monitors the SW voltage andturns GL off when SW exceeds the ZCD threshold voltage.
By turning off the LS FET, the body diode of the LS FET
allows any positive current to go to zero but prevents
negative current from conducting.

This section describes operation with controllers that arecapable of 3 states in their PWM output and relies on the
NCP302150 to conduct zero current detection during
discontinuous conduction mode (DCM).
The SMOD# pin needs to either be set to 5 V or left
disconnected. The NCP302150 has an internal pull−up
resistor that connects to VCC that sets SMOD# to the logic
high state if this pin is disconnected.
To operate the buck converter in continuous conduction
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NCP302150

Figure 16. Timing Diagram − 3−state PWM Controller, No ZCD

FOR USE WITH CONTROLLERS WITH 3−STATEPWM CONTROLLERS DETECTION CAPABILITY:
Table 9. LOGIC TABLE − 3−STATE PWM CONTROLLERS WITH ZCD
PWM

SMOD#

GH (not a pin)

GL

H

L

ON

OFF

M

L

OFF

OFF

L

L

OFF

ON

This section describes operation with controllers that arecapable of 3 PWM output levels and have zero current
detection during discontinuous conduction mode (DCM).
The SMOD# pin needs to be pulled low (below

and low states. During DCM, the controller is responsiblefor detecting when zero current has occurred, and thennotifying the NCP302150 to turn off the LS FET. When thecontroller detects zero current, it needs to set PWM tomid−state, which causes the NCP302150 to pull both GH
and GL to their off states without delay.

VSMOD#_LO).

To operate the buck converter in continuous conduction
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NCP302150
SMOD# = Low

Controller detects zero current →Sets
PWM to mid−state.

PWM in mid−state pulls GL
low.

Figure 17. Timing Diagram − 3−state PWM Controller, with ZCD

Figure 18. Top Copper Layer

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NCP302150

Figure 19. Bottom Copper Layer

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NCP302150
RECOMMENDED PCB FOOTPRINT(Option 1)

LAND PATTERN
RECOMMENDATIONRECOMMENDED MOUNTING FOOTPRINT
For additional information on our Pb-Free strategy and soldering
details, please download the onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

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NCP302150
RECOMMENDED PCB FOOTPRINT(Option 2)

LAND PATTERN
RECOMMENDATIONRECOMMENDED MOUNTING FOOTPRINT
For additional information on our Pb-Free strategy and soldering
details, please download the onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONSPQFN31 5X5, 0.5P
CASE 483BR
ISSUE DDATE 13 FEB 2023

SCALE 2.5:1

MILLIMETERS

DIM

MIN.

NOM.

MAX.

A

0.70

0.75

0.80

A1

0.00

−

0.05

A3

0.15

0.20

0.25

b

0.20

0.25

0.30

b1

0.13

0.18

0.30

D

4.90

5.00

5.10

D2

3.70

3.80

3.90

D3

0.75

0.85

0.95

D4

1.88

1.98

2.08

D5

1.22

1.32

1.42

D6

0.45

0.55

0.65

0.38 REF

D7

C.L.
16 17 181920

C.L.

C.L.
23

2122

16 17 181920

9

8

7

6

5

4

DOCUMENT NUMBER:DESCRIPTION:

3

2

1.03

1.13

E4

0.93

1.03

1.13

E5

0.93

1.03

1.13

E6

0.20

0.30

0.40

E7

0.22 REF

e

0.50 BSC

e/2

0.25 BSC

e/3

0.25 BSC

e/4

0.75 BSC

e/5

0.25 BSC
0.40 REF
0.45 REF

25

14

25

26

13

26

k3

0.40 REF

k4

0.30 REF

27
28

32

0.93

k1
14

10

2.02

E3

k2

13

C.L.

12

11

30

10

31

9

1

98AON13680G
PQFN31 5X5, 0.5P

33

27

32

8

7

6

5

4

3

2

1

5.10

k5

0.55 REF

29

k6

0.50 REF

30

k7

31

L

0.30

0.40

0.50

L1

0.30

0.40

0.50

L2

0.15

0.25

0.35

28

29

11

5.00
1.92

24

24

33

4.90
1.82

15

15

12

23

2122

E
E2

0.40 REF

m

0.15 REF

n0.80 REF

p

2.28 REF

q

2.38 REF

r

0.80 REF

z

0.625 REF

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

onsemi andare trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2018www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONSPQFN31 5X5, 0.5P
CASE 483BR
ISSUE D

8

DATE 13 FEB 2023

1
31

9
32

11
12

33

27
26

15

24

16

23

8

1

9

31
32

11

33

33

12

27
26
24

15

16

GENERICMARKING DIAGRAM*XXXXXXXXXXXXXXXXAWLYYWWGG

DOCUMENT NUMBER:DESCRIPTION:

23

XXXX = Specific Device CodeA
= Assembly Location
WL = Wafer Lot
YY= YearWW = Work Week
G
= Pb−Free Package(Note: Microdot may be in either location)

98AON13680G
PQFN31 5X5, 0.5P

*This information is generic. Please refer todevice data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

onsemi andare trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2018www.onsemi.com

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