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Eclypse Platform MCU Specification
Revised January 23, 2020

Table of Contents
Table of Contents .................................................................................................................. 1
Overview............................................................................................................................... 2
1

MCU .............................................................................................................................. 3

2

Clocking ......................................................................................................................... 3

3

SmartVIO Controller ....................................................................................................... 3

4

Temperature Probes ...................................................................................................... 6

5

Fans ............................................................................................................................... 76

PMU Interface................................................................................................................ 97

SOC/FPGA I2C Interface ............................................................................................... 12
7.1

Configuration Register Set Summary ............................................................................. 14

8

Optional Features ........................................................................................................ 21

9

Board Documentation Tables ....................................................................................... 22

DOC#: ###-###

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Page 1 of 22

Eclypse Platform MCU Specification

Overview
The Syzygy specification requires all pods (peripherals) to include a peripheral microcontroller unit with nonvolatilememory that has been programmed to contain a variety of hardware parameters that may be retrieved by a
“SmartVIO controller” utilizing a shared I2C bus. These parameters include the load requirements for the fixed 5.0
and 3.3V supplies, the load requirements for the adjustable VIO supply, a set of supported VIO supply voltage
ranges, as well as other optional things such as a manufacturer name string, product name string, model number,etc, and make up what is known as a pod’s “DNA”. Any carrier board that includes a Syzygy port is required
implement a SmartVIO controller that, at a minimum, will retrieve the current and voltage requirements for all
attached pods and only enable power to the VIO pins of the port after having determined a common voltage thatis supported by the carrier and all pods which share the same VIO group, or supply. Each Syzygy port may have its
own dedicated VIO power supply or two or more ports may share the same VIO power supply. Additionally, each
Syzygy port may share the same fixed 5.0V and 3.3V supplies, or they may have their own dedicated supplies. A
pod can consume up to 2.0 amps from any of the 3 supply rails (5.0V, 3.3V, and VIO) but a carrier is not required tosupply a minimum current on any of these rails.
The primary purpose of the Eclypse Platform MCU is to implement a SmartVIO controller to enumerate any Syzygy
ports present on the board, retrieve the voltage and current requirements for each pod that is connected to thoseports, determine the required VIO voltage for each VIO group, and then configure the associated PowerManagement Unit (PMU) to supply those voltages. The Eclypse Platform MCU is also capable of performing othertasks such as monitoring analog temperature probes, monitoring and/or controlling onboard fans, andimplementing an I2C Slave interface that can be used by a SOC/FPGA to determine the configuration of the board,as well as change some settings. The following list provides a high-level overview of the functionality provided by
the Eclypse Platform MCU.
•

•
•

•
•
•
•

Integrated SmartVIO controller with support for up to 8 SmartVIO portso Supports Standard and Transceiver SYZYGY Ports and is expandable to support FMC
o Supports up to 8 SmartVIO groups (independent VIO supply rails)o Supports driving up to 8 enable signals associated with PMU’s for each VIO groupo Supports monitoring up to 8 power good signals associated with each VIO groupo Supports up to 4 independent 5.0V supply rails for SmartVIO portso Supports up to 4 independent 3.3V supply rails for SmartVIO ports
o Option to enforce or ignore 5.0V, 3.3V, and VIO current limits▪ Configuration stored in EEPROM
Supports up to 4 analog Temperature Probes
Supports up to 4 Fan Headerso Optional RPM measurement for Fans 1 and 2
o Optional power on/off control for all four fanso Optional speed control for all four fanso Fan configuration is stored in EEPROM
Optional support for setting DDRVCC voltage based on jumper/switch setting
Optional support for holding INIT_B low to delay SOC/FPGA configuration
Optional support for configuring Microchip USB251xB USB Hub using SMBUS (I2C)
Provides a configuration interface with SOC/FPGA via I2C bus

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Other product and company names mentioned may be trademarks of their respective owners.

Page 2 of 22

Eclypse Platform MCU Specification

1

MCU

The Eclypse Platform MCU is implemented using the Atmel ATmega328PB-AU.

2

Clocking

The PMCU utilizes an 8 MHz crystal connected to the XTAL1 and XTAL2 pins to generate an 8 MHz system clock
used by the CPU and the peripherals. This allows for accurate measurement (1µs resolution) of the pulse width
output by an optional fan connected to the FAN header. Additionally, it provides the ability to communicate with
I2C devices with clock frequencies of 100 KHz (TWBR = 32, TWPS = 0) and 400 KHz (TWBR = 2, TWPS = 0).

3

SmartVIO Controller

The SmartVIO Controller implemented by the Eclypse Platform MCU firmware can support up to 4 independent
5.0V supplies, up to 4 independent 3.3V supplies, up to 8 independent VIO (VADJ) supplies, and up to 8 SmartVIO.
Each VIO supply may have one or more SmartVIO ports associated with it, may have an enable signal associatedwith it, and may have a power good signal associated with it. However, there are no hard requirements for any VIO
supply to have a SmartVIO port associated with it, or for enable or power good signals to be present. These are all
optional features that are specific to each board variant. The number of 5.0V supplies, 3.3V supplies, VIO (VADJ)
supplies, and SmartVIO ports that a specific board variant contains can be determined by reading the
5V0_GROUP_COUNT, 3V3_GROUP_COUNT, VADJ_GROUP_COUNT, and SMARTVIO_PORT_COUNT configuration
registers through the use of the SOC/FPGA I2C Slave Interface.
Each SmartVIO port has six read-only configuration registers associated with it. Five of the six registers are used to
specify the board-specific configuration of the port, which includes its I2C address (PORT_n_I2C_ADDRESS), the
5V0 group that it belongs to (PORT_n_5V0_GROUP), the 3V3 group that it belongs to (PORT_n_3V3_GROUP), theVIO (VADJ) group that it belongs to (PORT_n_VIO_GROUP), and its physical port type (PORT_n_TYPE). The sixth
configuration register indicates the status of the port, which includes bitfields to indicate if a pod/mezzanine cardis present, if it is within the current limits specified for the associated supply rails, if a double-wide module isinstalled, and if the associated VIO supply is allowed to be enabled (PORT_n_STATUS).
PORT_n_TYPE
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ptype
ptype

Port Type
0: None. Reserved for SmartVioPort entries that correspond to an entire VIO group
1: Syzygy Standard port with Syzygy default standard port pinout
2: Syzygy Transceiver-2 (TXR-2) port, 2-lane transceiver port
3: Syzygy Transceiver-4 (TXR-4) port, 4-lane transceiver port
All other values are reserved for future use

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Page 3 of 22

Eclypse Platform MCU Specification
PORT_n_STATUS
Bit 7
fAllowVioEnable

Bit 6
RSV2
fPresent

fDW

Bit 5
RSV1
Present
1:
0:

Bit 4
fVioInLimit

Bit 3
f3v3InLimit

Bit 2
f5v0InLimit

Bit 1
fDW

Bit 0
fPresent

A pod or mezzanine card is present at this port
No pod or mezzanine card is present at this port

Doublewide
1: The pod or mezzanine card is a double-wide module
0: The pod or mezzanine card is not a double-wide module

f5v0InLimit

5V0 current within limit
1: This port’s current requirements are within limit for the associated 5V0 supply
0: This port’s current requirements are not within limit for the associated 5V0 supply

f3v3InLimit

3V3 current within limit
1: This port’s current requirements are within limit for the associated 3V3 supply
0: This port’s current requirements are not within limit for the associated 3V3 supply

fVioInLimit

VIO current within limit
1: This port’s current requirements are within limit for the associated VIO supply
0: This port’s current requirements are not within limit for the associated VIO supply

RSV1

Reserved for future use

RSV2

Reserved for future use

fAllowVioEnable

Allow VIO supply to be enabled
1: Allow this port’s associated VIO supply to be enabled
0: Do NOT allow this port’s associated VIO supply to be enabled

After each power on or reset event has occurred, the PMCU firmware initializes its SmartVIO and configuration
registers (in RAM) with default values defined for the specific board variant. Any configuration settings that are
stored in nonvolatile memory are read from the EEPROM and used to initialize the associated configuration
registers/variables. The firmware then proceeds to initialize the peripherals that are utilized by the specific board
variant. It then waits 100 milliseconds, as per the Syzygy specification, to allow all 3.3V supplies to become stable.
Once 100 milliseconds have passed, the firmware proceeds to configure the TWI1 peripheral as a master andutilizes it to attempt to retrieve the Syzygy DNA header from each SmartVIO port that has been designated as a
Syzygy port. If a pod is present and its DNA header has been successfully retrieved then the maximum 5V load
current, maximum 3.3V load current, maximum VIO load current, the attribute flags, and the four VIO voltage
ranges will be parsed from the header and used to update the SmartVIO configuration associated with the port.
After the firmware is done populating the SmartVIO configuration structure with information parsed from the DNA
headers of any installed pods, it determines the minimum and maximum voltage that can be set for each VIOgroup based on the requirements of any pods that are present and members of the same group. Once the voltage
requirements are known for each VIO group the firmware proceeds to determine the current requirement for each
5V0 group, 3V3 group, and VIO group and make sure that each is within spec for the associate power supplies. If
the sum of current required for all pods within a VIO group is within the limit for any enforced current limit (5V0,
3V3, or VIO) then the PMCU firmware will designate the VIO supply as being allowed to enable power.

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Page 4 of 22

Eclypse Platform MCU Specification

PLATFORM_CONFIGURATION
Byte 1
pcfgMSB
pcfgLSB

Bits 7:4
RSV1

Byte 0pcfgLSB
Bit 3
fPerformCrcCheckBit 2
fEnforceVioCurLimit

Bit 1
fEnforce3v3CurLimit

Bit 0
fEnforce5v0CurLimitfEnforce5v0CurLimit

Enforce current limits for 5V0 supplies
1: Enforce the current limits for the 5V0 supplies
0: Do not enforce the current limits for the 5V0 supplies

fEnforce3v3CurLimit

Enforce current limits for 3V3 supplies
1: Enforce the current limits for the 3V3 supplies
0: Do not enforce the current limits for the 3V3 supplies

fEnforceVioCurLimit

Enforce current limits for VIO supplies
1: Enforce the current limits for the VIO supplies
0: Do not enforce the current limits for the VIO supplies

fPerformCrcCheck

Perform CRC check over DNA header when reading the DNA header
1: Perform CRC check
0: Skip CRC check

RSV1 Reserved for future use
Note: changes made to the fEnforce5v0CurLimit, fEnforce3v3CurLimit, fEnforceVioCurLimit, andfPerformCrcCheck fields have no immediate impact and don’t take effect until the next time the processor isreset. To apply changes immediately, issue a reset command after writing any changes to the
PLATFORM_CONFIGURATION register.
pcfgMSB

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

RSV2
RSV2

Reserved for future use

Once the current limits have been checked, all PORT_n_STATUS, all 5V0_n_CURRENT_REQUESTED, all
3V3_n_CURRENT_REQUESTED, and all VADJ_n_CURRENT_REQUESTED configuration registers will be updated. The
firmware will then proceed to set the VADJ voltage to midpoint of the supported VIO voltage range for all VIO
supplies that can be enabled and enable those supplies. The associated VADJ_n_VOLTAGE registers will be updated
and the VADJ_STATUS register is updated to reflect the status of the VIO supplies. At this point, the firmware
proceeds to reconfigure the TWI1 peripheral as a slave listening at I2C address 0x60 and enters the main loop,
where it listens for commands, captures temperature readings, captures fan speed readings, and executes any
specified commands as needed until power is removed or until a reset command is received over the I2C slaveinterface.
Once the PMCU has entered the main loop, it becomes capable of responding to I2C read/write requests from any
SOC/FPGA connected to the SYZYGY I2C bus. The SOC/FPGA acts as a bus master and may read and/or write any
configuration registers that are defined for the SOC/FPGA I2C Slave Interface. Additionally, the SOC/FPGA may
send a reset command, which will cause the PMCU to perform a software reset, reinitialize all peripherals andconfiguration registers, reperform the SmartVIO discovery process and reconfigure the PMUs.

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Page 5 of 22

Eclypse Platform MCU Specification

4

Temperature Probes

The Eclypse Platform MCU supports reading temperature measurements from up to 4 analog temperature probes
connected to its analog input pins. The ADC is configured to utilize the internal bandgap reference (1.1V) and tooperate in single conversion mode using the slowest conversion clock available to the Atmega328PB (62.5KHz).
ADC conversions are initiated at a rate that results in the voltage of each supported temperature probe being
sampled and converted one time per second. The firmware saves the conversion result and adjusts the analog
input mux (as necessary) to measure the next channel. The ADC sample values are converted into temperature
measurements and loaded into user-readable registers.
Each new temperature measurement is stored in a configuration register associated with the probe and can be
retrieved by the SOC/FPGA by reading the TEMPERATURE_n register, where n corresponds to the probe number(1, 2, 3, or 4). Each temperature probe has an attribute register associated with it, TEMPERATURE_n_ATTRIBUTES,
that specifies if the probe is present on the board, the point of measurement for the probe, and the format of thetemperature as stored in the TEMPERATURE_n register.
The TEMPERATURE_PROBE_COUNT register may be read to determine how many probes a board contains. If aboard contains less than 4 probes, then the lowest ordinal registers will correspond to the probes that are present.
For example, if a board only contains 2 temperature probes then the TEMPERATURE_1 and TEMPERATURE_2
registers will contain the temperature measurements for those probes, and the TEMPERATURE_3 andTEMPERATURE_4 will always return 0 when read.

TEMPERATURE_n_ATTRIBUTES
Bit 7
Bit 6
RSV1

Bit 5
Bit 4
DataFormat
fPresent

MeasurementPoint

DataFormat

RSV1

Bit 3

Bit 2
MeasurementPoint

Bit 1

Bit 0
fPresent

Present
1: This temperature probe is present
0: This temperature probe is not present
Probe point of measurement
0: FPGA / CPU 1
1: FPGA / CPU 2
2: PCB Location 1
3: PCB Location 2
All other settings reserved for future use
Temperature measurement data format
0: Degrees C, signed decimal
1: Degrees C, signed 10.6 fixed point
2: Fahrenheit, signed decimal
3: Fahrenheit, signed 10.6 fixed point
Reserved for future use

TEMPERATURE_n
Byte 1
tempMSB
tempLSB
tempMSB

Byte 0tempLSB

Least significant byte of 16-bit temperature measurement
Most significant byte of 16-bit temperature measurement

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Page 6 of 22

Eclypse Platform MCU Specification

5

Fans

The Eclypse Platform MCU can control and/or monitor up to 4 fans. The number of fans supported by a board is
hard coded into the firmware at compile time and may be determined by reading the FAN_COUNT register. Eachfan has 3 registers associated with it. The FAN_n_CAPABILITIES register contains bitfields that indicate what
functionality is supported by the fan, including the ability to enable/disable the fan, the ability to set the fan’s
speed, and the ability to measure the fan’s RPM. Some fans may support all these features, while others may only
support a subset of this functionality.
Each fan has a configuration register associated with it that may be used to specify certain things about its
configuration, such as if the fan is enabled or disabled, its speed, and which temperature probe is utilized forautomatic speed control when the fan is configured for automatic speed control. Some, all, or none of a fan’s
configuration may be modified by writing its associated FAN_n_CONFIGURATION register. A fan’s supported
capabilities are defined in its associated FAN_n_CAPABILITIES register. Any attempt to specify an unsupported
configuration will result in the unsupported changes being ignored. When a FAN_n_CONFIGURATION register iswritten, any accepted changes are also written to EEPROM. The PMCU firmware will read the EEPROM each time it
initializes, allowing for changes to a fan’s configuration to persist across power cycles and resets.
A fan that supports the speed selection capability can be configured to operate at one of three fixed speeds:
minimum, medium, and maximum. These different speed settings may be achieved by adjusting a fan’s supply
voltage, or they may be achieved by sending a fan control signal (PWM) to adjust its speed. What a specific speed
setting equates to in RPM and decibel level is application specific and is not specified by this document. If a fan
supports the speed selection capability, then the fcapSetSpeed bit will be set to a ‘1’ in the associated
FAN_n_CAPABILITIES register.
In addition to supporting settable fixed speeds, some fans may also support automatic speed control, where fan
speed is determined automatically based on the temperature measured by the temperature probe specified as thetemperature source for the fan. If a fan supports automatic speed control, then both the fcapSetSpeed andfcapAutoSpeed bits will be set to ‘1’ in the FAN_n_CAPABILITIES register. Automatic speed control can be enabledby specifying a value of ‘3’ for FanSpeed field in the FAN_n_CONFIGURATION register. The temperature probe
utilized to implement automatic speed fan control can be specified by writing a ‘1’, ‘2’, ‘3’, or a ‘4’ to theTemperatureProbeSelected field of the FAN_n_CONFIGURATION register.
If a fan supports RPM measurement then the fcapMeasureRpm bit will be set to a ‘1’ in the associated
FAN_n_CAPABILITIES and the measured RPM will be stored as an unsigned 16-bit integer and may be retrieved by
the SOC/FPGA by reading the FAN_n_RPM register. If RPM measurement isn’t supported, then the associated RPM
register will always return 0 when read. The current implementation of the PMCU has optional support formeasuring RPM for Fan 1 and Fan 2 and if those features are enabled then the FAN_n_RPM registers are updatedwith a new RPM measurement once per second.
The RPM of each fan is measured by using a timer to count the number of rising edges produced by the fan
feedback sensor over a given period. The timer output is captured once per second, and converted to RPM using
the formula 𝑅𝑃𝑀 = 30 × 𝑐𝑜𝑢𝑛𝑡_𝑟𝑖𝑠𝑖𝑛𝑔_𝑒𝑑𝑔𝑒 × (1𝑡_𝑛) where 𝑡_𝑛 is the period over which the count value wasmeasured. Therefore, the formula for calculating RPM simplifies to 𝑅𝑃𝑀 = 30 × 𝑐𝑜𝑢𝑛𝑡_𝑟𝑖𝑠𝑖𝑛𝑔_𝑒𝑑𝑔𝑒.

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Page 7 of 22

Eclypse Platform MCU Specification

FAN_n_CAPABILITIES
Bit 7
Bit 6

Bit 5

Bit 4

RSV1
fcapEnable

fcapSetSpeed

fcapAutoSpeed

fcapMeasureRpm

RSV1

FAN_n_CONFIGURATION
Bit 7
Bit 6
RSV1

Bit 3
fcapMeasureRpm

Bit 2
fcapAutoSpeed

Bit 1
fcapSetSpeed

Bit 0
fcapEnable

Enable / Disable Fan
1: This fan supports enable / disable functionality
0: This fan does not support enable / disable functionality
Fan Speed Selection
1: This fan supports speed selection
0: This fan’s speed is fixed
Fan Automatic Speed Control
1: This fan supports temperature-based automatic speed control
0: This fan does not support automatic speed control
Fan RPM Measurement
1: This fan supports RPM measurement
0: This fan does not support RPM measurement
Reserved for future use

Bit 5
fEnableFanSpeed

TemperatureProbeSelected

RSV1

Bit 4
Bit 3
TemperatureProbeSelected

Bit 2

Bit 1
FanSpeed

Bit 0
fEnableEnable / Disable Fan
1: Turn on the fan
0: Turn off the fan
Fan Speed Selection
0: Minimum speed
1: Medium speed
2: Maximum speed
3: Automatic speed control (temperature-based)
Temperature Probe used for automatic fan speed control
0: None1: Temperature Probe 1
2: Temperature Probe 2
3: Temperature Probe 3
4: Temperature Probe 4
All other settings reserved for future use
Reserved for future use

FAN_n_RPM
Byte 1rpmMSB
rpmLSB
rpmMSB

Byte 0rpmLSB

Least significant byte of unsigned 16-bit RPM measurement
Most significant byte of unsigned 16-bit RPM measurement

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Page 8 of 22

Eclypse Platform MCU Specification

6

PMU Interface

The PMCU interfaces with the PMUs using the TWI0 (I2C) peripheral, which is connected to the PMU’s I2C bus
through a level translator (PMU_SCL_LS and PMU_SDA_LS). Once the PMCU has powered on and initialized it willattempt to read the DNA of any SYZYGY pod that is attached to the SYZYGY connectors. Assuming that the DNA has
been successfully retrieved, and the onboard supplies can be configured to meet the requirements of any attachedpod(s), the PMCU will use the appropriate I2C interface to configure the PMU with the correct VADJn supply
voltages, then drive a ‘1’ onto the VADJn_PWR_EN net to enable the supplies. The associated VADJ_n_VOLTAGE
registers will be updated to contain the voltage that has been set, and the VADJ_STATUS register will be updated
to reflect the enable/disable status for each supply.
The SOC/FPGA may write the VADJ_n_OVERRIDE register using the SOC/FPGA I2C Slave Interface to override thevoltage and enable settings for each individual VIO supply. Each time one of these registers is written the PMCU
firmware checks to see if the specified configuration is valid. If the default VADJ settings are being overridden to
enable a VIO supply then the PMCU will check to make sure that it’s safe to enable the supply and that the
specified voltage is within the allowable range for the VIO group based on all pods/mezzanine cards connected toany ports that are a member of the VIO group, as well as any board/port specific voltage restrictions. If thespecified voltage is outside of the allowable range, then it is forced to be the minimum or maximum allowed
voltage for that VIO group. PMU commands are queued and processed in the main loop.
The firmware regularly checks the PMU command queue for new commands and monitors the status of any power
good signals that may be connected to the MCU. The associated power good bit is updated in the VADJ_STATUS
register any time the state of a power good signal changes. Additionally, any optional SYZYGY_n_DET signal that
may be present is driven to the appropriate state to indicate if a pod is present.
5V0_n_CURRENT_ALLOWED
Byte 1

Byte 0crntAllowed

crntAllowed

16-bit unsigned maximum steady state current (DC) that the supply can provide in milliamps

5V0_n_CURRENT_REQUESTED
Byte 1

Byte 0crntRequested

crntRequested

16-bit unsigned total current (in milliamps) requested by all SmartVIO ports associated with this supply

3V3_n_CURRENT_ALLOWED
Byte 1

Byte 0crntAllowed

crntAllowed

16-bit unsigned maximum steady state current (DC) that the supply can provide in milliamps

3V3_n_CURRENT_REQUESTED
Byte 1

Byte 0crntRequested

crntRequested

16-bit unsigned total current (in milliamps) requested by all SmartVIO ports associated with this supply

VADJ_n_CURRENT_ALLOWED
Byte 1

Byte 0crntAllowed

crntAllowed

16-bit unsigned maximum steady state current (DC) that the supply can provide in milliamps

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Page 9 of 22

Eclypse Platform MCU Specification
VADJ_n_CURRENT_REQUESTED
Byte 1

Byte 0crntRequested

crntRequested

16-bit unsigned total current (in milliamps) requested by all SmartVIO ports associated with this supply

VADJ_n_VOLTAGE
Byte 1

Byte 0vltgApplied

vltgApplied

16-bit unsigned voltage applied by the supply, specified in 10mV increments

VADJ_n_OVERRIDE
Byte
Bit

15
fOverride

14
fEnablevltgSet10mV
RSV1
fEnable

13

1
12
11
RSV1

10

9

8

7

6

0
5
4
3
vltgSet10mV

2

1

0

10-bit unsigned voltage to set, specified in 10mV increments
Reserved for future use
Enable or disable the supply
1: Enable (turn on) the supply
0: Disable (turn off) the supply

Override this supply’s voltage setting and enable/disable state
1: Override this supply’s settings with the settings specified in this register0: Do not override this supply’s settings
Note: the settings in this register have no effect unless the fOverride field is set to a ‘1’.
fOverride

VADJ_STATUS
Byte 1
fsPgoodfsEnable

Byte 0fsEnablefVadjHEnfVadjGEnfVadjFEnfVadjEEn

fVadjAEn

VADJA Power Enable / Disable Status
1: Power supply is enabled
0: Power supply is disabledfVadjBEn

VADJB Power Enable / Disable Status
1: Power supply is enabled
0: Power supply is disabledfVadjCEn

VADJC Power Enable / Disable Status
1: Power supply is enabled
0: Power supply is disabledfVadjDEn

VADJD Power Enable / Disable Status
1: Power supply is enabled
0: Power supply is disabledfVadjEEn

VADJE Power Enable / Disable Status
1: Power supply is enabled
0: Power supply is disabledfVadjFEnVADJF Power Enable / Disable Status
1: Power supply is enabled
0: Power supply is disabledfVadjGEnVADJG Power Enable / Disable Status
1: Power supply is enabled
0: Power supply is disabledfVadjDEn

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fVadjCEnfVadjBEnfVadjAEn

Page 10 of 22

Eclypse Platform MCU Specification

fsPgoodfVadjHEnVADJH Power Enable / Disable Status
1: Power supply is enabled
0: Power supply is disabledfVadjHPg

fVadjGPg

fVadjAPgVADJA Power Good Status
1: Power supply is on and within normal operating parameters
0: Power supply is off or outside of normal operating parameters

fVadjBPgVADJB Power Good Status
1: Power supply is on and within normal operating parameters
0: Power supply is off or outside of normal operating parameters

fVadjCPgVADJC Power Good Status
1: Power supply is on and within normal operating parameters
0: Power supply is off or outside of normal operating parameters

fVadjDPg

VADJD Power Good Status
1: Power supply is on and within normal operating parameters
0: Power supply is off or outside of normal operating parameters

fVadjEPgVADJE Power Good Status
1: Power supply is on and within normal operating parameters
0: Power supply is off or outside of normal operating parameters

fVadjFPgVADJF Power Good Status
1: Power supply is on and within normal operating parameters
0: Power supply is off or outside of normal operating parameters

fVadjGPgVADJG Power Good Status
1: Power supply is on and within normal operating parameters
0: Power supply is off or outside of normal operating parameters

fVadjHPg

VADJH Power Good Status
1: Power supply is on and within normal operating parameters
0: Power supply is off or outside of normal operating parameters

fVadjFPg

fVadjEPg

fVadjDPg

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fVadjCPg

fVadjBPg

fVadjAPg

Page 11 of 22

Eclypse Platform MCU Specification

7

SOC/FPGA I2C Interface

Both the Eclypse Platform MCU (PMCU) and the primary SOC/FPGA share the same I2C bus with any Syzygy or FMC
ports that are included on the board. Shortly after power-on/reset the PMCU firmware connects to I2C bus as abus master and attempts to discover any pods / mezzanine cards that are connected to the board’s expansion
ports. Once the PMCU is done enumerating the onboard ports, it updates the power supply configuration asnecessary, then switches the TWI1 (I2C) peripheral to slave mode and listens for bus address 0x60. The PMCU
firmware then enters the main loop where it listens for and executes commands and maintains automatically
updated registers. Once the PMCU firmware reaches this state, the primary SOC/FPGA can communicate with the
PMCU using the I2C bus. Since the PMCU does not operate in multi-master mode the SOC/FPGA should wait aminimum of 500 milliseconds before taking control of the I2C bus in order to avoid causing the PMCU to lose
arbitration and failing to enumerate the SmartVIO ports.
Once 500 milliseconds elapses, the SOC/FPGA may communicate with the PMCU using register read and register
write transactions. A register write transaction is performed using the following sequence:
1. SOC/FPGA places start condition on the I2C bus
2. SOC/FPGA sends SLA+W
3. SOC/FPGA writes high byte of the 16-bit address
4. SOC/FPGA writes low byte of the 16-bit address
5. SOC/FPGA writes up to 2 bytes of data
6. SOC/FPGA places stop condition on the I2C bus
Note: Some registers are 8-bits wide, while others are 16-bits wide. The PMCU firmware buffers the data that it
receives from the master and doesn’t write it to the addressed register until a STOP or Repeated Start condition isdetected on the I2C bus.
Register read transactions are performed using the following sequence:
1. SOC/FPGA places start condition on the I2C bus
2. SOC/FPGA sends SLA+W
3. SOC/FPGA writes high byte of the 16-bit address
4. SOC/FPGA writes low byte of the 16-bit address
5. SOC/FPGA places repeated start condition on the I2C bus
6. SOC/FPGA sends SLA+R
7. SOC/FPGA reads up to 32 bytes of data
8. SOC/FPGA places stop condition on the I2C bus
Note: When the PMCU firmware detects an SLA+R that matches its I2C address, it copies 32 bytes of theconfiguration register space to a temporary buffer, starting at the last address that was received from the
SOC/FPGA. If copying 32 bytes from the current register address results in exceeding the implemented register
space, then the PMCU firmware will wrap around to register address 0x0000 and continue copying from there until
the buffer contains 32 bytes. This allows the SOC/FPGA to read up to 32 coherent bytes while other PMCU tasks arefree to update the temperature, fan, and other registers in the background without causing data corruption. If the
SOC/FPGA attempts to read more than 32 bytes in a single transaction, then the PMCU will return 0xFF for all
additional bytes that are read.
The PMCU address space is split into three different sections, which are detailed in the table below:
Register Space
PDID
Firmware Version
Reserved for future use
Reset Register
Configuration Registers

Start Address
0x00000x00040x00060x7FFF0x8000

Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.

End Address
0x00030x00050x7FFE
0x7FFF
0xFFFF

Page 12 of 22

Eclypse Platform MCU Specification
The PMCU can be reset by writing a non-zero value to the Reset Register. If the SOC/FPGA writes a non-zero value
to the Reset Register, then it should release the I2C bus and wait 500 milliseconds before attempting to utilize thebus again.

Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.

Page 13 of 22

Eclypse Platform MCU Specification

7.1

Configuration Register Set Summary

Configuration Register Set Summary (starting at 0x8000)
Register
Address
Offset0x00000x0002

Register Name

Size
[Bytes]R/W

RESERVED1
Configuration Version

2
2

R
R

0x0004

PLATFORM_CONFIGURATION

2

R/W

0x00060x00070x00080x00090x000A
0x000B
0x000CTEMPERATURE_PROBE_COUNTFAN_COUNT
5V0_GROUP_COUNT
3V3_GROUP_COUNTVADJ_GROUP_COUNTSMARTVIO_PORT_COUNTTEMPERATURE_1_ATTRIBUTES

1
1
1
1
1
1
1

R
R
R
R
R
R
R

0x000D
0x000FTEMPERATURE_1
TEMPERATURE_2_ATTRIBUTES

2
1

R
R

0x00100x0012TEMPERATURE_2
TEMPERATURE_3_ATTRIBUTES

2
1

R
R

Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.

Description

Reserved for future use (should read 0xFFFF)
Platform MCU Configuration Revision
Lower Byte = VMIN
Upper Byte = VMJR
[0] = Enforce 5V0 Current Limit[1] = Enforce 3V3 Current Limit[2] = Enforce VIO Current Limit[3] = Perform CRC Check of DNA Header[15:4] = Reserved
Note: the contents of this register are stored in
EEPROM
Number of Temperature Probes
Number of Fan Connectors
Number of 5V0 Supplies
Number of 3V3 Supplies
Number of Adjustable VIO Supplies
Number of Expansion Ports
Temperature Probe 1 Attributes[0] = Present[3:1] = Probe Measurement Point
0b000 = FPGA/CPU 1
0b001 = FPGA/CPU 2
0b010 = External 1
0b011 = External 20b1xx = Reserved[5:4] = Data Format
0b00 = Decimal, Degrees C
0b01 = Fixed Point, Degrees C
0b10 = Decimal, Degrees F,
0b11 = Fixed Point, Degrees F[7:6] = Reserved
Temperature Measurement 1
Temperature Probe 2 Attributes[0] = Present[3:1] = Probe Measurement Point
0b000 = FPGA/CPU 1
0b001 = FPGA/CPU 2
0b010 = External 1
0b011 = External 20b1xx = Reserved[5:4] = Data Format
0b00 = Decimal, Degrees C
0b01 = Fixed Point, Degrees C
0b10 = Decimal, Degrees F,
0b11 = Fixed Point, Degrees F[7:6] = Reserved
Temperature Measurement 2
Temperature Probe 3 Attributes[0] = Present[3:1] = Probe Measurement Point
0b000 = FPGA/CPU 1
0b001 = FPGA/CPU 2
0b010 = External 1
0b011 = External 2

Page 14 of 22

Eclypse Platform MCU Specification

0x00130x0015TEMPERATURE_3
TEMPERATURE_4_ATTRIBUTES

2
1

R
R

0x00160x0018TEMPERATURE_4
FAN_1_CAPABILITIES

2
1

R
R

0x0019FAN_1_CONFIGURATION

1

R/W

0x001A
0x001C

FAN_1_RPM
FAN_2_CAPABILITIES

2
1

R
R

0x001D

FAN_2_CONFIGURATION

1

R/W

Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.

0b1xx = Reserved[5:4] = Data Format
0b00 = Decimal, Degrees C
0b01 = Fixed Point, Degrees C
0b10 = Decimal, Degrees F,
0b11 = Fixed Point, Degrees F[7:6] = Reserved
Temperature Measurement 3
Temperature Probe 4 Attributes[0] = Present[3:1] = Probe Measurement Point
0b000 = FPGA/CPU 1
0b001 = FPGA/CPU 2
0b010 = External 1
0b011 = External 20b1xx = Reserved[5:4] = Data Format
0b00 = Decimal, Degrees C
0b01 = Fixed Point, Degrees C
0b10 = Decimal, Degrees F,
0b11 = Fixed Point, Degrees F[7:6] = Reserved
Temperature Measurement 4
Fan 1 Capabilities[0] = Enable/Disable[1] = Set Fixed Speed[2] = Automatic Speed Control[3] = RPM Measurement[4:7] = Reserved
Fan 1 Configuration[0] = Enable/Disable[2:1] = Fan Speed0b00 = Minimum Speed0b01 = Medium Speed0b10 = Maximum Speed0b11 = Auto (Temperature Based)[5:3] = Temperature Source
0b000 = None0b001 = Temperature Probe 1
0b010 = Temperature Probe 20b011 = Temperature Probe 30b100 = Temperature Probe 4[7:6] = reserved
Note: the contents of this register are stored in
EEPROM and read each POR
Fan 1 Speed (RPM)
Fan 2 Capabilities[0] = Enable/Disable[1] = Set Fixed Speed[2] = Automatic Speed Control[3] = RPM Measurement[4:7] = Reserved
Fan 2 Configuration[0] = Enable/Disable[2:1] = Fan Speed0b00 = Minimum Speed0b01 = Medium Speed0b10 = Maximum Speed0b11 = Auto (Temperature Based)[5:3] = Temperature Source
0b000 = None

Page 15 of 22

Eclypse Platform MCU Specification

0x001E
0x0020

FAN_2_RPM
FAN_3_CAPABILITIES

2
1

R
R

0x0021

FAN_3_CONFIGURATION

1

R/W

0x00220x0024

FAN_3_RPM
FAN_4_CAPABILITIES

2
1

R
R

0x0025

FAN_4_CONFIGURATION

1

R/W

0x00260x00280x002A
0x002C
0x002E0x00300x00320x0034

FAN_4_RPM
5V0_A_CURRENT_ALLOWED
5V0_A_CURRENT_REQUESTED
5V0_B_CURRENT_ALLOWED
5V0_B_CURRENT_REQUESTED
5V0_C_CURRENT_ALLOWED
5V0_C_CURRENT_REQUESTED
5V0_D_CURRENT_ALLOWED

2
2
2
2
2
2
2
2

R
R
R
R
R
R
R
R

0b001 = Temperature Probe 1
0b010 = Temperature Probe 20b011 = Temperature Probe 30b100 = Temperature Probe 4[7:6] = reserved
Note: the contents of this register are stored in
EEPROM and read each POR
Fan 2 Speed (RPM)
Fan 3 Capabilities[0] = Enable/Disable[1] = Set Fixed Speed[2] = Automatic Speed Control[3] = RPM Measurement[4:7] = Reserved
Fan 3 Configuration[0] = Enable/Disable[2:1] = Fan Speed0b00 = Minimum Speed0b01 = Medium Speed0b10 = Maximum Speed0b11 = Auto (Temperature Based)[5:3] = Temperature Source
0b000 = None0b001 = Temperature Probe 1
0b010 = Temperature Probe 20b011 = Temperature Probe 30b100 = Temperature Probe 4[7:6] = reserved
Note: the contents of this register are stored in
EEPROM and read each POR
Fan 3 Speed (RPM)
Fan 4 Capabilities[0] = Enable/Disable[1] = Set Fixed Speed[2] = Automatic Speed Control[3] = RPM Measurement[4:7] = Reserved
Fan 4 Configuration[0] = Enable/Disable[2:1] = Fan Speed0b00 = Minimum Speed0b01 = Medium Speed0b10 = Maximum Speed0b11 = Auto (Temperature Based)[5:3] = Temperature Source
0b000 = None0b001 = Temperature Probe 1
0b010 = Temperature Probe 20b011 = Temperature Probe 30b100 = Temperature Probe 4[7:6] = reserved
Note: the contents of this register are stored in
EEPROM and read each POR
Fan 4 Speed (RPM)
5V0 Supply A Current Allowed
5V0 Supply A Current Requested
5V0 Supply B Current Allowed
5V0 Supply B Current Requested
5V0 Supply C Current Allowed
5V0 Supply C Current Requested
5V0 Supply D Current Allowed

Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.

Page 16 of 22

Eclypse Platform MCU Specification
0x00360x00380x003A
0x003C
0x003E0x00400x00420x00440x00460x00480x004A
0x004C0x004E

5V0_D_CURRENT_REQUESTED
3V3_A_CURRENT_ALLOWED
3V3_A_CURRENT_REQUESTED
3V3_B_CURRENT_ALLOWED
3V3_B_CURRENT_REQUESTED
3V3_C_CURRENT_ALLOWED
3V3_C_CURRENT_REQUESTED
3V3_D_CURRENT_ALLOWED
3V3_D_CURRENT_REQUESTEDVADJ_A_CURRENT_ALLOWEDVADJ_A_CURRENT_REQUESTEDVADJ_A_VOLTAGE
VADJ_A_OVERRIDE

2
2
2
2
2
2
2
2
2
2
2
2
2

R
R
R
R
R
R
R
R
R
R
R
R
R/W

0x00500x00520x00540x0056

VADJ_B_CURRENT_ALLOWEDVADJ_B_CURRENT_REQUESTEDVADJ_B_VOLTAGE
VADJ_B_OVERRIDE

2
2
2
2

R
R
R
R/W

0x00580x005A
0x005C
0x005E

VADJ_C_CURRENT_ALLOWEDVADJ_C_CURRENT_REQUESTEDVADJ_C_VOLTAGE
VADJ_C_OVERRIDE

2
2
2
2

R
R
R
R/W

0x00600x00620x00640x0066

VADJ_D_CURRENT_ALLOWEDVADJ_D_CURRENT_REQUESTEDVADJ_D_VOLTAGE
VADJ_D_OVERRIDE

2
2
2
2

R
R
R
R/W

0x00680x006A
0x006C
0x006E

VADJ_E_CURRENT_ALLOWEDVADJ_E_CURRENT_REQUESTEDVADJ_E_VOLTAGE
VADJ_E_OVERRIDE

2
2
2
2

R
R
R
R/W

0x00700x00720x00740x0076

VADJ_F_CURRENT_ALLOWEDVADJ_F_CURRENT_REQUESTEDVADJ_F_VOLTAGE
VADJ_F_OVERRIDE

2
2
2
2

R
R
R
R/W

0x00780x007A
0x007CVADJ_G_CURRENT_ALLOWEDVADJ_G_CURRENT_REQUESTEDVADJ_G_VOLTAGE

2
2
2

R
R
R

Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.

5V0 Supply D Current Requested
3V3 Supply A Current Allowed
3V3 Supply A Current Requested
3V3 Supply B Current Allowed
3V3 Supply B Current Requested
3V3 Supply C Current Allowed
3V3 Supply C Current Requested
3V3 Supply D Current Allowed
3V3 Supply D Current Requested
VADJ A Supply Current Allowed
VADJ A Supply Current Requested
VADJ A voltage in 10 mV
OVERRIDE VADJ Voltage Selection[9:0] = VADJ Voltage in 10mV
[13:10] = RESERVED[14] = ENABLE_VADJ[15] = OVERRIDEVADJ B Supply Current Allowed
VADJ B Supply Current Requested
VADJ B voltage in 10 mV
OVERRIDE VADJ Voltage Selection[9:0] = VADJ Voltage in 10mV
[13:10] = RESERVED[14] = ENABLE_VADJ[15] = OVERRIDEVADJ C Supply Current Allowed
VADJ C Supply Current Requested
VADJ C voltage in 10 mV
OVERRIDE VADJ Voltage Selection[9:0] = VADJ Voltage in 10mV
[13:10] = RESERVED[14] = ENABLE_VADJ[15] = OVERRIDEVADJ D Supply Current Allowed
VADJ D Supply Current Requested
VADJ D voltage in 10 mV
OVERRIDE VADJ Voltage Selection[9:0] = VADJ Voltage in 10mV
[13:10] = RESERVED[14] = ENABLE_VADJ[15] = OVERRIDEVADJ E Supply Current Allowed
VADJ E Supply Current Requested
VADJ E voltage in 10 mV
OVERRIDE VADJ Voltage Selection[9:0] = VADJ Voltage in 10mV
[13:10] = RESERVED[14] = ENABLE_VADJ[15] = OVERRIDEVADJ F Supply Current Allowed
VADJ F Supply Current Requested
VADJ F voltage in 10 mV
OVERRIDE VADJ Voltage Selection[9:0] = VADJ Voltage in 10mV
[13:10] = RESERVED[14] = ENABLE_VADJ[15] = OVERRIDEVADJ G Supply Current Allowed
VADJ G Supply Current Requested
VADJ G voltage in 10 mVPage 17 of 22

Eclypse Platform MCU Specification
0x007E

VADJ_G_OVERRIDE

2

R/W

0x00800x00820x00840x0086

VADJ_H_CURRENT_ALLOWEDVADJ_H_CURRENT_REQUESTEDVADJ_H_VOLTAGE
VADJ_H_OVERRIDE

2
2
2
2

R
R
R
R/W

0x0088

VADJ_STATUS

2

R

0x008A
0x008B
0x008C0x008D
0x008E0x008F

PORT_A_I2C_ADDRESSPORT_A_5V0_GROUPPORT_A_3V3_GROUPPORT_A_VIO_GROUPPORT_A_TYPE
PORT_A_STATUS

1
1
1
1
1
1

R
R
R
R
R
R

0x00900x00910x00920x00930x00940x0095

PORT_B_I2C_ADDRESSPORT_B_5V0_GROUPPORT_B_3V3_GROUPPORT_B_VIO_GROUPPORT_B_TYPE
PORT_B_STATUS

1
1
1
1
1
1

R
R
R
R
R
R

0x00960x0097

PORT_C_I2C_ADDRESSPORT_C_5V0_GROUP

1
1

R
R

Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.

OVERRIDE VADJ Voltage Selection[9:0] = VADJ Voltage in 10mV
[13:10] = RESERVED[14] = ENABLE_VADJ[15] = OVERRIDEVADJ H Supply Current Allowed
VADJ H Supply Current Requested
VADJ H voltage in 10 mV
OVERRIDE VADJ Voltage Selection[9:0] = VADJ Voltage in 10mV
[13:10] = RESERVED[14] = ENABLE_VADJ[15] = OVERRIDE
Bitfield indicating the status of the VADJ
supplies[0] = VADJ_A_EN[1] = VADJ_B_EN[2] = VADJ_C_EN[3] = VADJ_D_EN[4] = VADJ_E_EN[5] = VADJ_F_EN[6] = VADJ_G_EN[7] = VADJ_H_EN[8] = VADJ_A_PGOOD[9] = VADJ_B_PGOOD[10] = VADJ_C_PGOOD[11] = VADJ_D_PGOOD[12] = VADJ_E_PGOOD[13] = VADJ_F_PGOOD[14] = VADJ_G_PGOOD[15] = VADJ_H_PGOOD
I2C Address associated with Port A
5V0 group associated with Port A
3V3 group associated with Port A
VIO group associated with Port A
Port A Port Type
Bitfield indicating the status of Port A.
[0] = Present (1 if present)[1] = DW (1 if doublewide)[2] = 5V0_CURRENT_IN_LIMIT[3] = 3V3_CURRENT_IN_LIMIT[4] = VIO_CURRENT_IN_LIMIT[5] = RSV1
[6] = RSV2
[7] = ALLOW_VIO_ENABLE
I2C Address associated with Port B
5V0 group associated with Port B
3V3 group associated with Port B
VIO group associated with Port B
Port B Port Type
Bitfield indicating the status of Port B.
[0] = Present (1 if present)[1] = DW (1 if doublewide)[2] = 5V0_CURRENT_IN_LIMIT[3] = 3V3_CURRENT_IN_LIMIT[4] = VIO_CURRENT_IN_LIMIT[5] = RSV1
[6] = RSV2
[7] = ALLOW_VIO_ENABLE
I2C Address associated with Port C
5V0 group associated with Port C

Page 18 of 22

Eclypse Platform MCU Specification
0x00980x00990x009A
0x009B

PORT_C_3V3_GROUPPORT_C_VIO_GROUPPORT_C_TYPE
PORT_C_STATUS

1
1
1
1

R
R
R
R

0x009C0x009D
0x009E0x009F
0x00A00x00A1

PORT_D_I2C_ADDRESSPORT_D_5V0_GROUPPORT_D_3V3_GROUPPORT_D_VIO_GROUPPORT_D_TYPE
PORT_D_STATUS

1
1
1
1
1
1

R
R
R
R
R
R

0x00A20x00A30x00A40x00A50x00A60x00A7

PORT_E_I2C_ADDRESSPORT_E_5V0_GROUPPORT_E_3V3_GROUPPORT_E_VIO_GROUPPORT_E_TYPE
PORT_E_STATUS

1
1
1
1
1
1

R
R
R
R
R
R

0x00A80x00A90x00AA
0x00AB
0x00AC
0x00AD

PORT_F_I2C_ADDRESSPORT_F_5V0_GROUPPORT_F_3V3_GROUPPORT_F_VIO_GROUPPORT_F_TYPE
PORT_F_STATUS

1
1
1
1
1
1

R
R
R
R
R
R

0x00AE
0x00AF
0x00B00x00B10x00B20x00B3

PORT_G_I2C_ADDRESSPORT_G_5V0_GROUPPORT_G_3V3_GROUPPORT_G_VIO_GROUPPORT_G_TYPE
PORT_G_STATUS

1
1
1
1
1
1

R
R
R
R
R
R

Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.

3V3 group associated with Port C
VIO group associated with Port C
Port C Port Type
Bitfield indicating the status of Port C.
[0] = Present (1 if present)[1] = DW (1 if doublewide)[2] = 5V0_CURRENT_IN_LIMIT[3] = 3V3_CURRENT_IN_LIMIT[4] = VIO_CURRENT_IN_LIMIT[5] = RSV1
[6] = RSV2
[7] = ALLOW_VIO_ENABLE
I2C Address associated with Port D
5V0 group associated with Port D
3V3 group associated with Port D
VIO group associated with Port D
Port D Port Type
Bitfield indicating the status of Port D.
[0] = Present (1 if present)[1] = DW (1 if doublewide)[2] = 5V0_CURRENT_IN_LIMIT[3] = 3V3_CURRENT_IN_LIMIT[4] = VIO_CURRENT_IN_LIMIT[5] = RSV1
[6] = RSV2
[7] = ALLOW_VIO_ENABLE
I2C Address associated with Port E
5V0 group associated with Port E
3V3 group associated with Port E
VIO group associated with Port E
Port E Port Type
Bitfield indicating the status of Port E.
[0] = Present (1 if present)[1] = DW (1 if doublewide)[2] = 5V0_CURRENT_IN_LIMIT[3] = 3V3_CURRENT_IN_LIMIT[4] = VIO_CURRENT_IN_LIMIT[5] = RSV1
[6] = RSV2
[7] = ALLOW_VIO_ENABLE
I2C Address associated with Port F
5V0 group associated with Port F
3V3 group associated with Port F
VIO group associated with Port F
Port F Port Type
Bitfield indicating the status of Port F.
[0] = Present (1 if present)[1] = DW (1 if doublewide)[2] = 5V0_CURRENT_IN_LIMIT[3] = 3V3_CURRENT_IN_LIMIT[4] = VIO_CURRENT_IN_LIMIT[5] = RSV1
[6] = RSV2
[7] = ALLOW_VIO_ENABLE
I2C Address associated with Port G
5V0 group associated with Port G
3V3 group associated with Port G
VIO group associated with Port GPort G Port Type
Bitfield indicating the status of Port G.

Page 19 of 22

Eclypse Platform MCU Specification

0x00B40x00B50x00B60x00B70x00B80x00B9

PORT_H_I2C_ADDRESSPORT_H_5V0_GROUPPORT_H_3V3_GROUPPORT_H_VIO_GROUPPORT_H_TYPE
PORT_H_STATUS

1
1
1
1
1
1

R
R
R
R
R
R

Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.

[0] = Present (1 if present)[1] = DW (1 if doublewide)[2] = 5V0_CURRENT_IN_LIMIT[3] = 3V3_CURRENT_IN_LIMIT[4] = VIO_CURRENT_IN_LIMIT[5] = RSV1
[6] = RSV2
[7] = ALLOW_VIO_ENABLE
I2C Address associated with Port H
5V0 group associated with Port H
3V3 group associated with Port H
VIO group associated with Port H
Port H Port Type
Bitfield indicating the status of Port H.
[0] = Present (1 if present)[1] = DW (1 if doublewide)[2] = 5V0_CURRENT_IN_LIMIT[3] = 3V3_CURRENT_IN_LIMIT[4] = VIO_CURRENT_IN_LIMIT[5] = RSV1
[6] = RSV2
[7] = ALLOW_VIO_ENABLE

Page 20 of 22

Eclypse Platform MCU Specification

8

Optional Features

The Platform MCU can set the DDRVCC voltage based on the logic level established by a jumper or a switch.
Additionally, it can delay the SOC/FPGA configuration by holding the INIT_B pin low.
If the board variant supports the PMCU’s control of DDRVCCSEL, then the PMU will read the state of the
DDRVCCSEL pin during initialization and configure the appropriate channel of the PMU to output 1.5V or 1.35V
based on the state of the pin. A logic ‘1’ will result in DDRVCC being set to 1.5V, whereas a logic ‘0’ results in it
being set to 1.35V.
If the board variant supports the PMCU’s control of INIT_B and DDRVCCSEL, then the PMCU will conditionallyconfigure the pin attached to INIT_B as an output and drive it low during the early portion of device initialization toprevent the FPGA/SOC from being configured prior to DDRVCC being set to the voltage specified by ajumper/switch. If INIT_B is driven low during early initialization, then it will remain low until after all the PMCU
submodules have initialized and that the 100-millisecond delay required by the SYZYGY specification has elapsed.
Afterwards, the pin connected to INIT_B will be reconfigured as an input and the SOC/FPGA will be allowed toinitiate its configuration process. The MCU pin connected to INIT_B may only be configured as output and driven
low when the MCU’s reset source is Power-On-Reset or Brown-Out-Reset. If an external or software reset occurs,
then it is assumed that DDRVCC has already been configured and that there is no reason to delay SOC/FPGA
configuration. In fact, driving INIT_B low under these circumstances would clear the SOC/FPGA configuration and istherefore undesirable.

Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.

Page 21 of 22

Eclypse Platform MCU Specification

9

Board Documentation Tables

In order to present which features of the Eclypse Platform MCU are available for a board variant utilizing the
PMCU, standard documentation for that board is to include the tables below:
Table #: Platform MCU Connectivity Map

Interface
TEMPERATURE_1
PORT_A, VADJ_A
PORT_B, VADJ_B
FAN_1
FAN_2

Connection
Zynq Die
Temperature
Zmod A
Zmod BFPGA Fan
Case Fan

Table #: Supported Platform MCU Optional Features

Optional Feature
DDRVCCSEL Control
INIT_B Control
USB Hub Support

Supported
No
No
No

Table #: Supported Platform MCU Fan Control Features

Fan Header
Enable / Disable
Fixed Speed Control
Automatic Speed Control
RPM Measurement1
2

FAN_1 (FPGA Fan)
Yes
Yes
Yes
Yes, if supported by installed
fan1

FAN_2 (Case Fan)No
No
No
Yes, if supported by installed
fan2

The optional FPGA fan included with the Eclypse Z7 supports RPM measurement
The case fan included in the Eclypse Z7 Enclosure Kit does not support RPM measurement
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