Engineer-to-Engineer Note

EE-418

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ADSP-2156x Board Design Guidelines for Dynamic Memory Controller
Contributed by Nishant Singh, Sachin-V Kumar

Rev 2– September 10, 2020

Introduction

This EE-note provides recommended board
design practices for interfacing DDR memory andachieving expected performance from thecontroller. These guidelines should be used inaddition to standard board-level design practices.

The PCB trace characteristic impedance must
be 50 Ω for single-ended signals and 100 Ω fordifferential signals, with a 5% tolerance.

Route all DDR signals as a group in every
layer to avoid a mismatch in trace impedance
and propagation delay. Keep all groupedsignals on the same layer. For example, theDMC_DQ00-07,
DMC_LDQS,
andDMC_LDQM signals should be routed as agroup, in the same layer and having the sameground reference. Changing the groundreference plane can change the trace
impedance.

To avoid crosstalk, ensure that all DDR
signals have center-to-center spacing of atleast 3W between DDR signals and 4W toother signals, where W is the trace width.

Maintain perpendicularity between DMC
signals routing for different DMC signals
routed in adjacent layers. This configuration
reduces crosstalk, as signals on adjacent layers
will not be parallel to each other.

Avoid test points on the DDR signals, as theycreate stubs which can act as EMI sources.
Instead, use vias for probing. It is also
acceptable to use JEDEC-recommended
methods that test vendors offer fordiagnostics.

Placement and General RoutingGuidelines
Use the following guidelines when designing PCB
stack up, trace routing and component placement:Place the ADSP-2156x device and thememory as close as possible to each otherwhile minimizing routing length.

The ADSP-2156x DMC interface supports
only point-to-point design and does notsupport fly-by topology.

Plan the PCB stack-up such that all the DMC
signals (address, command and control) havecontinuous reference planes (ground planes)on an immediately adjacent layer. Ensure thatthese signals do not travel across splits in thepower/ground planes. It is better to increase
the distance between the signal and its
relevant planes than to implement the “crosssplit” routing.
For better signal integrity, avoid power-planeto-signal-plane and power-plane-to-powerplane coupling. Strive to minimize thiscoupling.

To simplify routing, entire byte lanes canbe swapped, but it should be ensured thatall DQ , DQS, DM signals are substituted
with each other (For example, DQ (7-0)
 DQ (15-8), DMC_LDQS DMC_UDQS,/DMC_LDQS.

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/DMC_UDQS,
DMC_UDM
DMC_LDM). Within a byte lane, databits can be swapped, with the exceptionof the lowest order bit (for example, DQ0
should be connected to DQ0 of theprocessor if lane swapping is not done).
Swapping of address lines is not allowed.

Trace Length-Matching Criteria
The routing of all the DDR interface signals mustbe length-matched to avoid set-up and hold time
violations due to propagation delay.

for improved signal integrity. The DDR3/DDR3L
data group signals do not require externaltermination because they have ODT.
The termination guidelines are as follows:
Install external series termination resistors on
all address and control signals and place themas close as possible to the processor.

The recommended value of the series
termination resistors is 100 Ω. This value canvary based on board routing.



Select appropriate series termination resistor
values, as well as ODT values, based on
simulation results of the board.

The length-matching criteria are as follows:Match the trace length of all address (DMC_A[nn],DMC_BA[n])andcommand(DMC_CKE, DMC_CS[n], DMC_ODT,DMC_RAS, DMC_RESET, DMC_WE)
signals within +/- 40 mils relative to the
DMC_CK signal.

Match the trace length of all data (DMC_DQ[nn]) and data mask (DMC_UDM,DMC_LDM) signals within +/- 40 mils
relative to their corresponding DQS signal.
For example, match the trace length of thelower order data byte (DMC_DQ00 DMC_DQ07) and the corresponding datamask (DMC_LDM) signals with the lowerorder strobe (DMC_LDQS) signal.

Match the trace length of differential signals
such as clock (DMC_CK and /DMC_CK) andDQS pairs (DMC_LDQS and /DMC_LDQS,DMC_UDQS and /DMC_UDQS) within +/10 mils. For example, match the trace lengthof the DMC_CK and /DMC_CK signals
within +/- 10 mils relative to each other.

VTT Termination
Use the following guidelines for VTT
termination. These guidelines can differ fromvendor to vendor.
For DDR3/3L, VTT termination isrecommended by JEDEC, as this mitigates
signal reflection. The primary purpose of a
VTT island is to prevent reflections at thememory device. Removing the VTT
termination results in signal reflections. The
removal can lead to higher than nominal
voltages at the memory address or command
input pins, which can damage or reduce thelifetime of the memory. Check with theappropriate memory vendor for devicespecific information.

Implement VTT termination for the addressand command lines as shown in Figure 1,
Where RN1 is a resistor pack.

The maximum allowed trace length for DDR
signals is 2 inches.

Interface Termination
All DDR interface signals without on-dietermination (ODT) require external termination
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Perform a decoupling analysis of the VTTplanes.

DMC Power (VDD_DMC)
Decoupling
Use the following guidelines for DMC power
decoupling:The DMC interface should have enoughdecoupling on the VDD_DMC rail and thememory power rail to avoid data corruption.

Refer to the DDR memory data sheet or
consult the DDR memory vendor to identify
the decoupling capacitor requirement for theDDR memory power rails. A criticalparameter is Idd7, which defines the peakcurrent during multi-bank operations anddepends on the speed grade and ambient
temperature of the DDR memory.

Place all the decoupling capacitors very close
to the VDD_DMC power rail and use solid
power and ground planes.

Ensure that the power and ground planes are
adjacent to each other to provide the shortest
return path and better power integrity.

Isolate the DDR power planes from othersupply planes. If this is not possible, separate
them as much as possible and avoidoverlapping them.

Place individual power and ground vias fromevery power and ground pin of the ADSP2156x processor and the memory device to its
associated plane.

Place decoupling capacitors for theVDD_DMC power rail as close as possible tothe actual power pins. This is very importantbecause DDR signal slew rates are aggressive.
Placing these capacitors close to the pin ismandatory. Provide dedicated power andground vias for each decoupling capacitor pin,wherever possible.

Figure 1. VTT Termination for Address and CommandLineThe DMC_CK and /DMC_CK signals must
be terminated using a differential termination
scheme as shown in Figure 2.

Figure 2. DMC clock differential termination


VTT termination does not play a major role
for the ADSP-2156x processor. It is mainly arequirement from the memory device. Anyalternative that prevents reflections on theaddress or command bus is an acceptable
substitute for VTT termination at theprocessor.
Separate VTT and VREF islands by aminimum of 150 mils if placed on the same
PCB layer. Placing the islands on different
layers is preferred.
Place VTT islands as close as possible to thememory device.

VTT islands require at least two additional
decoupling capacitors (4.7μF) and two bulk
capacitors (100μF) at each end as shown inFigure 3.

VTT island surface trace must have aminimum width of 150 mil minimum. A widthof 250 mil is preferred.

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Ideally, the trace length from the power via tothe processor pad should not exceed 30 mils.
The maximum trace length from each powervia to its decoupling capacitor is 60 mils. Themaximum trace length from each power via toits power ball pad is 35 mils.

Placement of the mid-bulk bypass capacitors(~10 μF) is not critical. They can be placed toaccommodate other circuitry with moreconstrainedplacement
androuting
requirements.

Figure 3. VTT Supply and Decoupling Scheme

guard traces have sufficient ground vias
stitched to the main ground plane.

DMC_VREF Voltage Supply
DMC_VREF acts as a voltage reference forDDR3/DDR3L data signals and compares thedifference between a steady reference voltage(DMC_VREF) and the signal received foridentifying the logic. Hence, it is recommended tominimize noise on DMC_VREF.
Provide adequate decoupling near theDMC_VREF pins of the ADSP-2156x
processor, as well as at the memory device.

Keep the DMC_VREF trace as short aspossible, with a width of at least 20 mils.

Route the DMC_VREF trace at least 40 mil
away from high-speed signals and noisypower supply traces.

Recommended ADSP-2156x
DMC_VREF Filtering Scheme

Guard traces can be provided around the
DMC_VREF trace, if required. Ensure that theFigure 4 shows the RCR filtering scheme on
DMC_VREF that is recommended for ADSP-ADSP-2156x Board Design Guidelines for Dynamic Memory Controller (EE-418)

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Place the C (100 pF)-R (2 kΩ) portion of the
RCR network as close as possible to theADSP-2156x DMC_VREF pin.

2156x processors. As shown, DMC_VREF0 and
DMC_VREF1 can be shorted together.

PCB Placement and Routing
Guidelines for the DMC_VREF
Filter NetworkUse a small package, preferably the 0402 size,for the 100pF capacitor to guarantee a highself-resonant frequency.

Route the entire RCR network on one layer
with no vias in the traces.

Use the following guidelines for the DMC_VREF
filter network placement:Place the recommended RCR network
between the DMC_VREF supply paths fromthe memory to the processor.

Figure 4. DMC_VREF Filtering Network

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Figure 5. Recommended VREF Supply Circuitcurrent requirement of the DDR. Figure 5shows the recommended VREF supply circuit
for a DDR3 memory device.

Memory-Side Recommendations
for VREF Supply
Use the following guidelines for DMC_VREF
supply placement on the memory side. Therequirements apply to both DDR3 and DDR3L.






DDR3 memory has two VREF pins: VREFCAand VREFDQ. VREFCA serves as thereference for clock, address, command, andcontrol signals. VREFDQ serves as thereference for strobe, data, and data masksignals
VREFCA and VREFDQ can have a common
supply source,but should be “STAR” routedand decoupled at the dedicated DRAM pins.
Place two decoupling capacitors, 0.1 μF and
0.01 μF, for each VREF pin (VREFCA andVREFDQ).
Place the 0.01 μF capacitor closer to theDRAM pin, followed by the 0.1 μF capacitor.

Routing Guidelines for Other
High-Speed Interfaces
Use the following recommendations for the highspeed peripherals (QSPI, Link Port, SPORT)
signals routing.
The recommendation for maximum trace
length is 4 inches.

The trace length should be matched within +/3 mils, between the clock and all other signals.
This ensures that all the signals are fulfilling
the required timings.

The clock signal should be routed 3 times thetrace width away from all other signals. Thissafeguard the clock signal from noisecoupling.

Keep the length from the decoupling capacitor
to the DRAM supply pin as short as possible.
Maintain the trace width based on the peak

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References[1] Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx Processors (EE-387). Rev. 3, April 2018. Analog
Devices, Inc.
[2] ADZS-21569 EZ-Kit® Schematic, Rev B, Sep 2017. Analog Devices, Inc.

Document History
RevisionDescription

Rev 2 – September 10, 2020
by Sachin-V Kumar

Added new section “Routing Guidelines for Other High-Speed Interfaces”
Minor changes in “VTT Termination”
Added a new note in “Placement and General Routing Guidelines”
Minor changes in “Figure 3”

Rev 1 – January 15, 2020
by Sachin-V Kumar

Initial Release

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