The 19th KEKB Accelerator Review Committee (2014.03.04)

Status of LLRF System~ KEKB LLRF Team ~T. Kobayashi, K. Akai, K. Ebihara,
A. Kabe, K. Nakanishi, M. Nishiwaki, J. Odagiri

1Outline
1. Overview & Status
2. Klystron Phase Lock Loop (KLY-PLL)
3. Response (Frequency) Property of FB control
4. Bunch Gap Transient Effect
5. Schedule & Summary
Given comments in the report of last KEKB ARC
1. What happens if the LLRF system doesn’t boot up orload the FPGA properly, or somesoftware process hangs up? (Interlocks should be very robust and not a software function).
2. Dynamic responses of the closed loop system? (information in the frequency domain?)
3. Bunch gap transient effects? Is the shift of the IP (the difference between the HER andLER) acceptably small?
2

New LLRF System for SuperKEKB
Preset analog systems will be replaced by new digital ones step-by-step.

A new LLRF system has been developed andthe performance was evaluated.

New LLRF System for one klystron(EIA-19” rack)
Mitsubishi Electric TOKKI System Corp.

Cavity FB Control

Tuner Control

I/L Control& VSWR MonitorµTCA crate
uTCA-platform
FPGA Boards(AMC Card)

16-bit ADC x 4ch,
16-bit DAC x 2ch

Each board has a CPU (PPC), and the EPICS-IOC
on Linux-OS is embedded.
EPICS control on FPGA core and PLC••This system consists of µTCA-based FPGA boards & PLC.
EPICS-IOC on Linux-OS is embedded in each of them. They
can be operated remotely via EPICS-Channel Access.

•Hardware is common for both of ARES & SC Cavity. (Alsoboth softwares are much the same.)•Feb. 16, 2010

RF Overview (K. Akai)

 Klystrons (LLRF) : Cavity unit = 1 : 1 (SuperKEKB)

3

Block Diagram of FB&Tuner Controlfor ARES

Reported ’13

ADC CLK4 x IFIF-Q

IQ-I

4

RF System Arrangement for Phase-I
In the beginning, New LLRF systems will be applied to 9 stations at D4&D5
Installation
2014/06

7Gev

D11

New LLRF

e+e4GeV

D4
Installation
2014/03

Super Conducting Cavity

New LLRF

ARES Cavity

D10

Present status

D8Klystron + LLRF

D5D7• Now the mass production of 8 systems is in progress as scheduled. And the prototype model (β-version)is also used for the operation at D4. They will be installed in March at D5 and in June at D4.
• The other stations are still driven by existing analogue systems.

• The DR-LLRF system will be produced next JFY. It is almost the same as MR one, except 3-cavity vectorsum control is needed.

5

Reliability of FPGA for Inter Lock
Reported ’13

DET
x 8ch

x 8ch

FPGA
ADC comp.

RF signal

ARC
light

Detector outputs are A/Dconverted on FPGA at 40MHz.

PD

x 8ch 14bit ADC

ADC
Optical Fibercomp.

x 8ch 14bit ADC

RFSW-OFF
Waveforms at I/L event can beobtained like an oscilloscope. Itis very useful for flexible filtering.
Ext. Trig. is also available.

Given comment
What happens if the LLRF system doesn’t boot up or load the FPGA properly, or some software process
hangs up? (Interlocks should be very robust and not a software function).

Our viewpoint
FPGA is generally regarded as the same as hardware system,
so it is very reliable.
It has accomplished solid performance in many fields.
It is hard to expect simultaneous hang-up of all FPGAs.
All boards have some I/L function (multiplexed). Any FPGA (orPLC) might detect some abnormal.

Kly-Out Level
Cav-In Level•Cav-Refl.
ArcVSWR••Kly-Out Refl.
•Kly-In Level•Dummy Load (Refl.)•C-cav Damper+ PLC I/L (Vac. water, etc..)

6

Reported ’13

Klystron Phase Change
due to Anode Voltage Control

For efficiency optimization, the anodevoltage is controlled depending on klystron
input power to reduce the collector loss.

Klystron Input-Output Characteristics

KLY Anode Voltage

80 deg.
Input PowerThe kly. output phaseshifts largely inresponse to input/output power.

This phase change is unexpectedly-large.
The loop phase shift of 80 deg. will be criticalproblem for I/Q FB control technique.
( Acceptable phase change is about +/-60 deg. )Klystron Phase Lock Loop
(KLY-PLL) is necessary.
7Implementation of Klystron PLL in FPGA

Required loop bandwidth : <1kHz (The anode voltage response : about 1Hz.)
8

KLY-PLL Test Result with ARES-FB Control
in 100-W Driving

Cavity-FB & KLY-PLL acting together
CLKFPGA

Phase shift in the loop：90deg.@1HzRFIQ-Mod.

DACDAC

Cav-FB&Kly-PLL
ADCADCLOFunc.
Gen.

Phase
Shifter

1Hz

Phase Shift
Cavity Pick-up
under FB-Control

90deg.

±0.1deg.

Driver Amp.

LO100W

ARES
ARES
CavityCavity1s(2.7kS/s)

KLY-PLL works successfully,
and the cavity FB control is still normally stable.
w/o KLY-PLL, cavity FB control is broken with oscillation.

High-power test with klystron is not yet done.

9Response Property -Klystron Bandwidth(open loop)

Measured Result
Amplitude @dBD
1010k

100k

Magnitude

1M

Frequency @HzD

Modulation Frequency [Hz]Td : Delay

Magnitude [dB]0fitting curve with

H kly [s] =-10-20

11+ s / ω kly + s 2 / αωkly=130 kHz

Phase

Td=650ns
α=2.1x1012-30

Phase@deg.D
180i e− s⋅Td

10k

100k

1M

Frequency @HzD
Phase@deg.D
18010k100k

1M

Frequency @H

Phase [deg.]

90900-90

Phase（delay=0）0-90-180-180

10Response Property

Bode Plot of Closed Loop for ARES

⎡ xI ⎤⎢x ⎥⎣ Q⎦

Ref +-PI-cont.

KLY

Delay
H cav =Delay⎡ yI ⎤⎢y ⎥⎣ Q⎦

Cavity⎛ s + ω 1/2
ω 1/22 ⎜Δω 2 + ( s + ω 1/2 ) ⎝ Δω⎞⎟s + ω 1/2 ⎠−Δω

y=Hclose[s]x⎛ h11[s] h12 [s] ⎞H close [s] = ⎜⎟h[s]h[s]2122⎝⎠Calculation of Trans. Func. & Measured Result in High Power Test

Amplitude @dBD
Magnitude(h)1110Magnitude [dB]

1k

for Tuned Cavity

P20,I160
10k

without IIR filter-20Open Loop(KLY + Cavity)-30

β=3,QL=28000, Δω=0
Loop Delay=2us

-40
-50

1M

Phase@deg.D180

P20,I800-10100k

Pactual = P 8

Frequency @HzD

P20,I20
P8, I40
P: Pgain
I: Igain

1k

10k

100k

1M100k1M

Frequen

P20,I20900-90

Phase-180

Gain Margin of Pactual : ~10 (w/o filter)

I actual = I × 2 −15 × ( CLK = 85MHz )Phase@deg.D
18090

1k10k

Frequency @P8, I400-90

Sync. Osc.
fs

Revolution

-180

11

Disturbance Rejection Characteristics
xfN++KLY

Delay

PI-cont+Cavity
Delayin the closed loopyy=H[s]•x

Ref.
Amplitude @dBD
Magnitude(h11)10Magnitude [dB]01k

Calculation & Measurement
10k

100k

Frequency @HzD

1M Phase@deg.D180OpenLoop

1k90

Frequency

10k

100k

1M

10k100k

1M

Phase-10-20

0P20,I20-90-30

P8, I40-40

P20,I20-180

Phase@deg.D180P20,I80

1kFrequenc

90-50

0P8, I40-90

Sync. Osc.

fs

Revolution-180

12Disturbance Rejection Property for Beam
Cavityx f +y
B+

Delay

KLY

Calculation Only
Amplitude @dBD
Magnitude(h11)Magnitude [dB]

OpenLoop

Revolution

fs

1k

10k-501M

P8, I40
P20,I20
P40,I40-30
-40

100k

Frequency @HzD

Just Cavity Property-10-20Ref

y=H[s]•xSync. Osc.

100- Delay+

PI-Cont

P20,I80
adopted for operation
13Simulation ofPhase Modulation due to Bunch Gap (LER)
Time-domain simulation of ARES (LER) for bunch gap transient
Including 3-cav. structure of the ARES

Ib=3.6 A(ultimate stage)

Cavity Param.
β: 5 , QL: 18000 (Qs=1.6x105, Qc=50, Qa=2.5x104)
Pc: 140 kW , Pb: 460 kW
Φacc: 74.5 deg.
A-cav detuning: -280 kHz

Gap 2%FB Param.
Pgain: 20 (Pactual=2.5)
Igain: 80 (Iactual=2x105)
Loop delay: 2 us
KLY band : 100 kHz

Amplitude

Phase10us (100kHz)

2.0deg.
Bunch gap 2%

Phase (zoom)

0.8%
Δφeff = Δφ +ΔV
1V tan (φs )100ns(50 bunches)

agree well withΔV ω rf ⎛ R ⎞=I b Δt ⋅ tan φsVc 2Vc ⎜⎝ Q ⎟⎠Δφ =ω rf ⎛ R ⎞I b Δt2Vc ⎜⎝ Q ⎟⎠FB-control effective is small against gap transient. (almost cavity response)
FF-control compensation is impossible (Bandwidth of >1MHz is needed).
KLY-BW is ~100kHz

attributed to0 & π mode of ARES

Leading bunch of
the train

14

Simulation of

Phase Modulation due to Bunch Gap (HER)

Time-domain simulation of SCC & ARES for HER bunch gap transient
HER : Ib=2.6 A(ultimate stage)

SCC
Q0:1e9, QL: 50000
Vc: 1.5MV
Pb: 600 kW
Φacc: 84 deg.
Detuning: -44 kHz

Amplitude

Phase

2.6%

3.0deg.

Gap 2%

8xARES (0.5MV)+
8xSCC (1.5MV)
Vector SUM of Vc
Phase Shift

Pgain: 800 (100)
Igain: 4000 (107)
Loop delay: 2 us+=ARESβ: 5 , QL: 18000
Pc: 150 kW
Pb:600 kW
Φacc: 62.5 deg.
Detuning: -180 kHz

Amplitude

2.6 deg.

Phase
1.4deg.

1.1%

Pgain: 20 (2.5)
Igain: 80 (2x105)
Loop delay: 2 us15

Estimation of Relative Phase Shift@IP between HER & LER
due to 2%-bunch gap in the ultimate stage
Bunch Length: σz=6mm (3.7deg.)

ARES
SCC

βx*~30mm

e-e+7Gev, 2.6A
Vc =1.5 MV/cav.
ΔΦ = 3.0

D11

Vc =1.5 MV/cav.
ΔΦ = 3.0

D104GeV, 3.6A

ΔΦrelative = ±0.15 deg.
(Δzrelative = ±0.25 mm)
LER

ΔΦ = 1.4HER

D4(ARES/SCC)

Beam Current [A]

3.62.6Pb /kly [kW]460

600 / 400Number of Cavity

228/8

Φacc [deg.]

74.5

62.5 / 84.0

Detuning [kHz]2218 / 44ΔΦ (p-p) /cav. * [deg.]

2.01.4 / 3.0

ΔΦ (p-p) * [deg.]

2.02.6

ΔΦ@IP (relative) ** [deg.]

Vc=0.5MV/cav.

Vc=0.43 MV/cav.
ΔΦ = 2.0

D5±0.15 ( Δz = ±0.25 mm)* Excluding the leading part of the bunch train.
** (ΔΦHER- ΔΦLER)/40.43 MV/cav.

D8ΔΦ = 2.0

0.43MV/cav.

ΔΦ = 2.0D716

Schedule of Production and Installation*based on the original schedule for the operation.
H26

JFY20134567H27

JFY201489 10 11 12 123456

JFY2015789 10 11 12123456789 10 11 12Acc. Operation
Beam Operation
DR Beam Operation

MR LLRF System
Quantity Production ( 8 Systems )Installation @ D5
Cabling@ D4
System Calibration & Op. Test
RF Conditioning

Damping Ring LLRF
Designing
Production
Installation
Cabling
System Calibration & Op. Test
RF Conditioning

Reference Distribution
Opt. Transceiver System (Optical Delay Controller, E/O, O/E etc..）
Production
Installation &Tuning
Optical Cables

Installation of Opt. Cableｓ• Mass production of 8 systems is now in progress for D4&D5, and will be installedon March and June in this year.
• RF conditioning is scheduled in November & December JFY2014.
• DR-LLRF designing has been completed, and the production will be JFY2014.
17

Summary• Now the mass production of new LLRF system is in progress on schedule.
They will be applied at D4 and D5 sections.

• Newly klystron phase lock loop was implemented in the FPGA, andsuccessfully worked. But high power test is not yet.

• RF phase modulation due to the bunch gap transient was estimated. Therelative phase shift between both rings at IP is expected to be acceptably
small. However, large-phase displacement appears at the leading part ofthe bunch train.

• DR-LLRF system will be produced next JFY.
18

Thank you for your attention !

19

Followed by Backup Slides

20

SB Phase Noise of ARES under FB control.
P20, I80

RMS Jitter: 71fs

-100dBc/Hz-150dBc/Hz

100Hz

1kHz

10kHz

100kHz1MHz21

Features

RF Reference Distribution• Optical distribution by means of “Star” configuration from the central control room (CCR).
• “Phase Stabilized Optical Fiber (PSOF)”, which has small thermal coefficient, is adapted : < 1ppm/°C (5 ps/km//°C)• Furthermore, optical delay control of thermal drift compensation is applied at CCR for all transfer lines.
• The optical transceivers (E/O and O/E) are the same as J-PARC Linac; They have practical accomplishment of seven-year operation, quite low
jitter and high thermal stability with Pertie device.

Status• Installation of the PSOF cables to all RF sections and Tsukuba-B3 was completed.
• Optical transceivers and the drift compensation system will be install in this month.
• Connection into the electronics hut of the Belle-II and extension to the DR will be done this year (next JFY).

Short term stability (time jitter) : ~0.1 ps (rms)Long term stability (pk-pk) : ±0.1° @508.9MHz = ±0.55 pswith the optical delay control.

22

Low-level RF for KEKB Superconducting cavity

KEKB-LLRF Systeminterlocks

from RFreference line

Phase Lock Loop
combiner for klystron

klystron circulator

Tuning Control LoopSW
outoutFBC

FBC

FBC

FB

ref.

φ det.

FBref.

FB

φ det.

FBC

Existing LLRF
System of the KEKB( for one klystron )TunerController

FBklystron outtunerout

FBCVc set

KLYcont.
Gain
Controlfor klystron
LopoutK. Akai et al. / Nuclear Instruments and Methods in Physics Research A 499 (2003) 45–65

ref.
offsetφ det.

DLbeamFBcavity

Direct RF
RF Feedback
DirectFeedackSW

pick up (Vc)

Amplitude
Amplitudecont.
Control Loop
for VcFig. 2. RF station for the SCC cavities.

Phase Lock Loop for Vc

Phase Lock Loop

RF input

S-cav

A-cav

coupling
acceleratingcavity
cavitystorage cavity

ARES Tuner Control
Configuration

c-dampers-tunerBPF(RF ON)

beam signal

BPF

ref.

outa-tuner
BPF

BPF

BPF

φsg
φsb(RF OFF)φacfor ALC and PLL

Fig. 3. Tuning control.

23

The -1 mode feedback
In the KEKB Operation• Beam current was limited due to the -1 mode
instability at 1 A in LER and 1.2 A in HER, muchlower current than expected.
• The -1 mode digital feedback selectively reduces
impedance at the driving frequency.
• After the -1 mode feedback was installed, thebeam current could be successfully increased.

1600
1400
1200
1000

Stored beam current

800
600
4002000Feedback off
3:30 PM
03.6.30

Feedback on

3:45 PM

4:00 PMDate

FB OFFƒrf - ƒrev-40

ƒrf - ƒrev + ƒs(a)

-0.97

-0.95

-60
-80
-100-120-1-0.99

-0.98

-0.96

Frequency Δƒ/ƒrev

-1 mode sideband

FB ON
ƒrf - ƒrev

-40

(b)

-60

ƒrf - ƒrev + ƒs-80-100-1-0.99

-0.98

-0.97

-0.96

Frequency Δƒ/ƒrev

-0.9524