Power Modeling12PowerGeneration••

3 Types of Power
Generators in VisualSim
Power Profiles can be
defined with constant orvariable charge capacity(Watt-Hr)

PowerStorage•••••

Instantaneous energycapacity
Battery Life Remaining
Total Battery Consumption
Charge drop due to power
surge
Battery Low Warnings

43••

PowerConsumption

PowerManagement

State based power consumptionof both electronics (controller,SOC) and Mechanical parts(brakes, wheels)
Average Power, Instantaneous
Power and Cumulative Powerreport••ThermalManagement
based onaverage powerand power statechanges

Downstream Integration

Verification and Debugging
Decide on power management algorithms based on power consumption
Sizing of power generators
Debugging power spikes
Understanding power consumed by the software application
Power Consumption overhead due Voltage and Frequency Transition time

ThermalManagement

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PowerStates canbe defined using
PowerTable orusing a statechange diagram5•••

Generate UPF format with power domains andassociated voltage levels
Generate systemVerilog power testbenchGenerate powerState change VCD dump fordebugging

Concept of VisualSim Power Technology
Incorporate hardware, software and network

Power changes based on Workloads and use-cases

Power for each devices modeled as states at each clock cycle
Task -based power, transitions and management logic

Hierarchical power management with each H block owning an
individual Power Table
Next-level Power Table cumulates all lower-level power devices

Looks at each of the entities in detail◦ Generation- Multiple sources- wind, solar, motor, constant andcustom◦ Storage- Types of batteries◦ Consumption at various rates by multiple devices with different
clock speeds◦ Management based on time and custom logic

Generate UPF power profile for downstream test
and SystemVerilog Testbench for Power
Reports are average, instant, battery life, usage,comparison between input, available and consumed
Functional
PortionTiming and Resource
Portion

Function 1

Timing 1

Function 2

Timing 2.
.
.

Transition Time

Function N.
.
.

Timing N

Block Functional and Timing Diagram

Block Power Mode Diagram

Power is now an integral part of Architecture Exploration

Power Generator
Time-Energy◦ Constant Power Source◦ File Based◦ Time Based

Motor-Energy◦ Motor Based Power Generation◦ Wind Based Power Generation

Time-Energy Settings
Using Trace file fromexisting system
Using Time-based
1. Duration is the period
2. Setup has % of time in thePeriod of each time
3. Charge can increase orreduce during the period
4. Efficiency is amount of charge
converted
Constant output at
the set rate

Motor-Energy Settings
Compute the Wind Power basedon air speed and efficiency

Motor based on RPM

Power Storage - Battery
Used to capture◦ Rate of consumption◦ Impact of continuous charging◦ Lifecycle loss due to power spikes and thermal shock◦ (Experimental) Heat and Temperature

Types of batteries support◦ Battery database support NiCd, Li-Ion, NiMh, LdAcid

Activities modeled◦ Charging- SOC threshold, Turbo charge, all input charge◦ Discharge- From the PowerTable◦ Lifecycle, discharge

Battery Block - Parameters
Requires Unique nameDefault database provided
Select battery type
Default charging is the value arrive. Click to Custom
State of Charge for charging to resume.
Enable Turbo charging
Time taken to get to each level of charge. Similarto phone battery chargers

Note:Power generated when not charging is wasted.
User can add items to the database
Edit the instance to add the new battery types

Block Ports
Connect
1. Power Generator
2. Aging input in %3. Power Table
Instantaneous power
port
ChargeFromGenerator_Port
SimulateShocks_Port
Consumption_Input_Port

Connect Output Ports toTimeDataPlotter and
TextDisplay
Current Energy
Capacity output port
Battery life
remaining Output
Port
Battery Stats Output Port

Power Management

Power TablePower State Table Entry• Manager_Name: Unique name for this Power Manager• Manager_Setup parameter :✔ Architecture block : Lists the devices supported by power table. A device can be divided into multiple sub-components with a unique line for each(Example-DRAM)✔ Power States: (Minimum list; Additional states added per need)❖ Standby: Power consumption when device is idle
❖ Active: Power consumption when device is processing a task
❖ Wait: Power Consumption when device is waiting for a response❖ Idle: Power consumption during Off state of the device

Transition Details✔ Operating State:❖ Existing: Initial state of the device❖ OffState: Off state of the device❖ OnState: Active/ON state of the device✔State Transitions❖ t_OnOff: transition time delay from one state to another. Value can be modified dynamically❖ “t_OnOff can be used to specify the time it will take to reach the peak power level once the change of state hasbeen made.

Power Table Parameters✔Optional Parameters❖ Mhz: used for computation done in Expression List
❖ Volts: used for computation done in Expression List
❖ More variables can be added. The values can be dynamicPower Management & Dynamic Compute● Delay_to_State_Change is the power control state machine that changes state if the device has been in a particularstate for a time period. The format is"<Device_Name><State><Time_or_Expression> <Next_State>"● Expression_List define expressions for State values and can be computed dynamically. The format is"<Name><value or expression> ; “Power Table – Custom States and Other Options
User can define Power Equations or any
other variables in the system and then use
it in Manager_Setup• Generates UPF File with Domains and Voltages Allotted based on Power Entry• Generates System Verilog Behavioural description of PowerManager Block andSystem Verilog test bench based on the PowerState transitions in the model Custom states define dhere can be used in operating states Custom equations can be used in place of power number values, voltage, frequency

Configuring the Power Table
Minimum information◦ List of states and associated power values◦ Power values can be double or a complex expression that has variables

Each device◦ Define power (in watts/mW/uW) for all the states (Active, Standby, Idle etc.)

VisualSim Power PlotsDetailed Power StatsPower State Transition Log – PowerTablerd
3 port output
Power in Watts
Current power state
Device nameCurrent TimeGNU Plot – Detailed power plot
Device activity
graph – identify
when each of thedevices areactive and theirsequence ofoperation.

Power Management for Custom Blocks
using Regex
Manager Setup for Custom Blocks

Regex Used :Defining Power States using State Diagram

Control System Design – state machines
Bluetoothmodule in IoTDemo model

2/2/2021

MIRABILIS DESIGN INC.

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Dynamic Power Analysis

Dynamic Power Analysis

Architectural Layer -> 2Cores and a sharedmemoryModel location:
Attached

Algorithm  Script is used totrack Utilization_Mean andthrottle Voltage and Frequency
based on that
Application Layer -> Each Task
takes certain percentage time on
the Resource, determined byPTPX input dataResults

Frequency and Voltage Scaling Up/down based onCore Utilization

Frame_Rate = 0.3fps

Frame_Rate = 30fps

Cumulative Power Report

Frame_Rate = 0.3fps

Frame_Rate = 30fps

Results and Downstream Integration

Power ModelingUPF file and System Verilog files• High level UPF containing Domain and Voltage information Power test bench basedon the state transitions of the blocks in the model) are also generated in the model
Results Directory.
• To enable, select the Generate_UPF_TB option in the power Table.

UPF File

Power domains added
based on ‘Domain’column in powerTable

Supply nets and ports
based on ‘Voltage”
column in powerTable

Power switch added bydefault for all domains– swctrl can be used intestbench to enable ordisable the switch

Value from “Volts” will
be added for Active
state of the port. Othervalues are default
Power state table basedon all the supply ports

VCD Output from System Verilog Files
VCD file having input and output signal transitions for that model can be generated by using pmu.sv and testbench.sv
in any of the opensource or commercial EDA tools that support System Verilog
The user can observe the States that each of theResources were in throughout the simulation.
Signals:
1. Change_State = when it is high, the Power Manager
applies the transition from current state to next state forthat Block
2. Next_State = This signal holds the binary equivalent of
the next state (Example: 00, 01, 10,11 – active, standby,wait, idle)
3. Set_State = This signal will indicate that the transition iscomplete successfully to the new intended state
The user can observe the delay between transitions byzooming in the waveform.

Note: These files can be useful for downstream

integration in the RTL power verification
environment.

Power Perf Tradeoff Analysis

SoC Architecture for Media Application
ARM
CortexA9Target
SoC Power Target < 1.5W
No. of Frames in 20 msec>= 18K

AXI

AXI

AXI

Power and Performance Trade-off must be done concurrently

Model SoC Architecture and Map the MPEG Application
Processor

Bus Topology

MemoryController

MPEG Application
IP or ARM level•••

Evaluate pipeline stages
Width, Speed
Number of execution units,
Levels of cacheSoC•••

HardwareAccelerators

Number of ARM cores
Accelerators
Cache memory hierarchy andcoherence

System level•

Use Cases
Mirabilis Design Inc.

Development of an IoT device,
ECU or an integrated platform

36

CASE 1: Run all tasks on SW(on A9 core)
Observations:
1. Avg power consumption
within requirements(<1.5 W)
2. Performance requirement
not achieved (Only a maxof 15K frames)Sequence diagram
Rotate Frametask is found to
be resource
intensiveCASE 2: Run Rotate Frame task on HW Acc
Observations:
1. Avg power consumption
requirement not met(>1.5 W)
2. Performance requirement
achieved ( max of 19 Kframes)•The Avg power consumption is greater than the threshold•Options for the Architect:•Use HW accelerator from another vendor•Use same HW accelerator, but apply power management•From the power plot for HW accelerator, it could be observed thatthe HW accelerator is active only for a short period of time

CASE 3: Run Rotate Frame task on HW Acc+ Power management
Power management being applied across HW
accelerator -> If Hardware Accelerator is instandby state for more than 1 msec, then it ismoved to Idle state
Observations:
1. Avg power consumption
requirement met (<1.5W)
2. Performancerequirement achieved (max of 19.4K frames)