ADuCM3027/ADuCM3029 User Guide
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One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

How to Set Up and Use the ADuCM3027/ADuCM3029
INTRODUCTIONFEATURESThis user guide provides detailed information of the
ADuCM3027/ADuCM3029 microcontroller functionality andfeatures. Each section describes a different feature.

System features that are common across the ADuCM3027/
ADuCM3029 devices include the following:
Up to 26 MHz ARM Cortex®-M3 processor
Up to 256 kB of embedded flash memory with error
correction code (ECC)
Optional 4 kB cache for lower active power
64 kB system SRAM with parity
Power management unit (PMU)
Multilayer advanced microcontroller bus architecture(AMBA) bus matrix
Central direct memory access (DMA) controller.
Beeper interface
Serial port (SPORT), three serial peripheral interfaces (SPIs),
inter integrated circuit (I2C), and universal asynchronousreceiver/transmitter (UART) peripheral interfaces
Cryptographic hardware support with advanced encryption
standard (AES) and secure hash algorithm (SHA) −256
Two real-time clocks (RTCs)
Three general-purpose timers and one watchdog timer
Programmable general-purpose input/output (GPIO) pins
Hardware cyclical redundancy check (CRC) calculator with
programmable generator polynomial
Power-on-reset (POR) and power supply monitor (PSM)
12-bit successive approximation register (SAR) ADC

GENERAL DESCRIPTION
The ADuCM3027/ADuCM3029 processor is an ultra low
power, integrated, mixed signal, microcontroller system used
for processing, control, and connectivity. The MCU subsystem
is based on the ARM® Cortex™-M3 processor, a collection ofdigital peripherals, cache embedded SRAM and flash memory,and an analog subsystem, which provides clocking, reset, andpower management capabilities along with the analog-to-digitalconverter (ADC).
The ADuCM3027/ADuCM3029 processor provides a collectionof power modes and features, such as dynamic and software
controlled clock gating and power gating, to support extremely
low dynamic and hibernate power management.
Full specifications on the ADuCM3027/ADuCM3029 areavailable in the product data sheet and the ADuCM302x Ultra
Low Power ARM Cortex-M3 MCU with Integrated PowerManagement Hardware Reference Manual.

ADuCM3027/ADuCM3029 FUNCTIONAL BLOCK DIAGRAM
26MHz CORE RATEPLLSERIAL WIREINSTRUCTION
RAM/CACHE(32kB)HF XTALLF XTALARM
CORTEX-M3

HF OSCNVIC
LF OSCREF BUFFER

MPU

TEMPERATURESENSORADC

WIC

MULTILAYER
AMBA
BUS
MATRIX

SPORT

SRAM0
(16kB)POWER
MANAGEMENT
BUCK

SRAM1
(16kB)DMA
CRYPTO(AES 128/256,
SHA 256)

FLASH(256kB)

UART

TMR0

TMR1

RTC0

RTC1

TMR2

WDT

BEEPERGPIO

TRNG

PROGRAMMABLE
CRC POLYNOMIAL

SPI

SPI

SPI

I 2C

Figure 1.

See the last page for an important warning and disclaimers.

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ADuCM3027/ADuCM3029 User Guide

TABLE OF CONTENTS
Introduction ...................................................................................... 1

Flash Controller .......................................................................... 30

General Description ......................................................................... 1

Effects of Cache .......................................................................... 30

Features .............................................................................................. 1

Current Consumption Comparison ........................................ 32

ADuCM3027/ADuCM3029 Functional Block Diagram ............ 1

Dual RTC Feature in the ADuCM3027/ADuCM3029 ............. 33

Revision History ............................................................................... 2

Comparison of the RTC Features............................................. 33

Getting Started .................................................................................. 3

Power Considerations ................................................................ 33

Software Installation .................................................................... 4

Conclusion .................................................................................. 33

IAR Configuration ....................................................................... 5

Benefits of the ADuCM3027/ADuCM3029 DC-to-DC
Converter ......................................................................................... 34

Building Demo Projects............................................................... 7
Power Optimization for the ADuCM3027/ADuCM3029
Processors ........................................................................................ 11

DC-to-DC Basics........................................................................ 34

ADuCM3029/ADuCM3027 Processor Power Management 11

Conclusions ................................................................................. 37

ADuCM3029/ADuCM3027 Processor Power Modes .......... 11

UART Software Flow Control ....................................................... 39

Fast Wake Up from Hibernate Mode ........................................... 17

UART Flow Control ................................................................... 39

Flash Memory and Instruction SRAM .................................... 17

System Description .................................................................... 40

Normal Wake Up ........................................................................ 17

Data Capture ............................................................................... 44

Fast Wake Up .............................................................................. 17

SPI Flow Control Methods ............................................................ 45

Using the ADuCM3029/ADuCM3027 Processor Boot Kernel .... 20

SPI Read Command Mode ....................................................... 45

Boot Kernel Overview ............................................................... 20

Flow Control Modes .................................................................. 47

UART Downloader .................................................................... 23

Conclusions ................................................................................. 49

Read Protection Key and Hashing ........................................... 26

Sleep on Exit .................................................................................... 50

Memory Configuration ............................................................. 27

Benefits ........................................................................................ 50

Handling CRC in the IAR Workbench .................................... 28

Enabling the Sleep on Exit Feature .......................................... 50

Cache Memory in the ADuCM3027/ADuCM3029 .................. 30

System Control Register in the ADuCM3027/ADuCM3029 ... 51

Capacitors vs. Inductor Converters ......................................... 36

Block Diagram ............................................................................ 30

REVISION HISTORY
1/2019—Rev. A to Rev. B
Changed EZ-Kit to EV-COG-AD3029 ....................... Throughout
Change to Software Installation Section ....................................... 4
Changed ADuCM3027/ADuCM3029 Board Support Package(BSP) Section to ADuCM3027/ADuCM3029 Device Family
Pack (DFP)......................................................................................... 5
Changes to ADuCM3027/ADuCM3029 Device Family Pack
(DFP) and EV-COG-AD3029 Board Support Package (BSP)
Section ................................................................................................ 5
Replaced Figure 5 and Figure 6 ...................................................... 5
Changes to IAR Provided Code Section ........................................ 7
Changes to Running an Example Project Section ........................ 9
Changes to Figure 59 ...................................................................... 40

9/2017—Rev. 0 to Rev. A
Changes to Buck Converter Section ............................................ 12
Added Fast Wake Up from Hibernate Mode Section, Figure 37,
and Figure 38; Renumbered Sequentially ................................... 17
Added Table 3 and Figure 39 ........................................................ 18
Added Figure 40 ............................................................................. 19
Changes to Effects of Cache on the Speed of Execution Section,
Cache Key Register Section, and Cache Setup Register
Section .............................................................................................. 31
Added Table 14 and Table 15 ........................................................ 31
Changes to Figure 58...................................................................... 40
Changes to System Control Registers in the ADuCM3027/
ADuCM3029 Section ..................................................................... 51
Added Table 24 ............................................................................... 51
3/2017—Revision 0: Initial Version

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GETTING STARTEDThis section works as a tutorial by describing different steps indeveloping an application by using the IAR workbench as anintegrated development environment (IDE). This section also
describes how to download and run sample codes provided
with the board support package (BSP) drivers.

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This section introduces the tools and support packages required
to develop an application for the ADuCM3027/ADuCM3029
microcontrollers. This section describes how to download,
install, and configure the programs used to program the
ADuCM3027/ADuCM3029.

Figure 2. IAR Embedded Workbench

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ADuCM3027/ADuCM3029 User Guide
4.
5.

SOFTWARE INSTALLATIONThe software tools required to develop applications with the
ADuCM3027/ADuCM3029 are available for download at the
EV-COG-AD3029 product page.

Plug in the emulator board and open the device manager.
Check that the emulator board appears in the Windows®
device manager in the USB controllers lists (see Figure 4).

Table 1. Required Software Tools

ADuCM3027/
ADuCM3029
BSP Drivers

Functions
Used for compiling, debugging, and codedevelopment
J-Link software and documentation packincludes USB drivers for the emulator, J-Link
Commander, and so on
Includes ADuCM3027/ADuCM3029
peripheral drivers and libraries, IAR
configuration files, and example programs
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Tool
IAR Embedded
Workbench
Segger J-Link
SoftwareInstalling the Segger J-Link Driver
The Segger J-Link USB driver must be installed before using a
serial wire interface, such as the interface of the IAR embedded
workbench, to download and debug code.
Use the following procedure to install the J-Link USB driver:2.
3.

After following the software installation procedures, the USB
driver for the J-Link is installed and verified.

IAR Tools Installation

Download the latest Segger J-Link software anddocumentation pack.
Open the executable software installer on the download
directory.
Follow the on-screen instructions to complete the installation.
Ensure that the Install USB Driver for J-Link option ischecked, as shown in Figure 3.

The IAR embedded workbench and the included IAR C/C++
compiler generates the fastest performing, most compact codein the industry for ARM-based applications. Therefore, Analog
Devices, Inc., created the BSP drivers for the ADuCM3027/
ADuCM3029 for the IAR workbench.
The KickStart edition is a free starter kit and evaluation versionof IAR. This edition has limitations, both in code size (32 kB)
and in the service and support provided.
The IAR software is available for download on the IAR website.
Download a free trial to download the software.
For a detailed procedure on installing the IAR and adding
license details if required, refer to the Installation and Licensing
Guide for IAR Embedded Workbench®, available from the IAR
website.
Note that the BSP examples are for IAR Version 7.40.2. Projectcompatibility issues may occur when using different versions.

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1.

Figure 4. Device Manager

Figure 3. Segger J-Link Driver Installation Options

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ADuCM3027/ADuCM3029 Device Family Pack (DFP) and
EV-COG-AD3029 Board Support Package (BSP)

4.

The ADuCM3027/ADuCM3029 DFP provides the configuration,
support files and components required to ease the developmentof the ADuCM3027/ADuCM3029.

Click the Install local pack file button in the CMSIS Pack
Manager window (see Figure 6) and browse to thedownloaded Analog Devices.ADuCM302x_DFP.x.x.x.
pack file to install the file.

Additionally, BSP is required to access all the necessary onboard peripheral drivers for the EV-COG-AD3029 evaluation
board.


Source files for the device drivers and services for use on
the ADuCM3027/ADuCM3029 processor.
Examples for devices drivers and services.
Tool chain support. These components are installed in the
IAR embedded workspace to configure the tool chain torecognize the ADuCM3027/ADuCM3029.
Documentation.

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The contents of the DFP are as follows:

Figure 6. Install Local Pack File Option in CMSIS Pack Manager

5.
6.

Note that the IAR embedded workbench must be installed
before installing the DFP and BSP.
Use the following procedure to install the BSP:

2.

3.

Download the ADuCM3027/ADuCM3029 DFP and BSP
from the EV-COG-AD3029 product page.
Select the latest version of the Analog Devices
ADuCM302x Device Support and Examples from thesoftware section of the product page. This is a Cortex
microcontroller software interface standard (CMSIS) packfile that must be installed in IAR Embedded WorkbenchVersion 8.11.3 and above.
Open the IAR embedded workbench integrated
development environment (IDE) and select the CMSISPack Installer, as shown in Figure 5.

IAR CONFIGURATIONThis section describes the IAR configuration procedure for proper
operation of the ADuCM3027/ADuCM3029. Only the sections
that must be modified from the default values are described.
1.

2.

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1.

Complete the installation process. The user can view thelatest DFP under Pack > Analog Devices (see Figure 6).
Install the latest Download Software - Analog Devices
EV-COG-AD3029 Off-Chip Drivers and Examples for
the EV-COG-AD3029 with the same installation
procedure.

Figure 5. CMSIS Pack Installer

Ensure that, in the general options, the Analog Devices
ADuCM3029/ADuCM3027 device option is selected as thetarget.
Under C/C++ Compiler > Optimizations, select different
optimization options for speed, code size, balance, and soon, depending on the application needs. Sometimes, thecompiler identifies the writes of a register as eligible to be
optimized, which may cause unexpected behavior. In suchsituations, it is recommended to protect configuration
functions from being optimized by using following code:#pragma optimize=none

3.

Rev. B | Page 5 of 51

Under C/C++ Compiler > Preprocessor, include the pathof the included directories, depending on the code to be run.

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ADuCM3027/ADuCM3029 User Guide
Select J-Link/J-Trace as the debugger under the Driver
dropdown menu. Verify that both the Verify download
and Use flash loader(s) boxes are checked on the Debugger >Download menu as shown in Figure 9 and Figure 10.

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5.

Figure 8. Linker > Extra Options Configuration Tab

Rev. B | Page 6 of 51

Figure 9. Debugger > Setup Tab

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A 32-bit CRC checksum stored in the signature field allows
the user code to request an integrity check of the user space.
Therefore, it is necessary to configure the checksum as shownin Figure 7 and Figure 8, both configurations in the Linker
menu.

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4.

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Figure 7. Linker > Checksum Configuration Tab

Figure 10. Debugger > Download Tab

ADuCM3027/ADuCM3029 User Guide
Figure 11 and Figure 12 show the J-Link/J-trace
configuration. Be sure to use the Halt after bootloader
target reset strategy under the Reset dropdown menu,
otherwise a kernel corruption occurs and the device locks
down. To recover from this corruption, the kernel must be
reflashed.

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6.

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Figure 13. Opening the IAR Workspace

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Several relevant projects are available within the examples folderof the BSP, as shown in Figure 14.

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Figure 11. J-Link/J-Trace > Setup Configuration Tab

Figure 12. J-Link/J-Trace > Connection Configuration Tab

BUILDING DEMO PROJECTSIAR Provided CodeSeveral example projects are available in the examples folder,
located in the ADuCM3027/ADuCM3029 BSP directories asfollows:

BSP Install Folder > \ADuCM302x_EZ_Kit_Lite >examples.
BSP Install Folder> \EV-COGAD3029LZ_BSP>version>Boards>examples

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Figure 14. Available Projects in the BSP Folder

To open an example project, from the File menu, choose Open >Workspace…, and navigate to the workspace file.

Each example includes a comprehensive, low level, peripheral
library that can be used to interface to the peripherals of the
ADuCM3027/ADuCM3029. Comprehensive documentation
for both the libraries and the examples are included.

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To change projects, right click on a different project in theworkspace and click Set as Active from the menu that appears(see Figure 15).

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Changing Projects

Figure 17. Building an Application Using the IAR Make Toolbar Button

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To rebuild the full application code, click Project > Rebuild All.
This action cleans, recompiles, and links all the project files.

Figure 18. Building an Application Using Rebuild All

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In all cases, it is possible to compile code without errors, as
shown in Figure 19.

Figure 15. Changing Projects

Building the Application

Figure 16. Building an Application Using Project > Make

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To build or compile the application code, the user can either
click Project > Make (or press F7) as shown in Figure 16, or
click the make button, shown in Figure 17.

Figure 19. Recompiling Projects
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Downloading the Application CodeRunning an Example Project

To download the code, click Project > Download > Download
active application.

The ADuCM3027/ADuCM3029 BSP has many sample projects
to test and evaluate the microcontroller. In this user guide, the
EV-COG-AD3029LZ evaluation board and IAR workbench areused to run a sample project from the BSP package.
The LED_polled_button example project is used in this section.
This example uses the GPIO service to configure the push buttons(the GPIO is configured as an input) and the LEDs (the GPIO isconfigured as an output) on the EV-COG-AD3029LZ board.
To execute the LED_polled_button project,
Navigate to Project > Add Existing Project….

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1.

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Figure 20. Downloading the Application

After power cycling the device, the code runs on the
ADuCM3027/ADuCM3029.

Figure 24. Add Existing Project… Menu Option

Debugging the Application Code2.

Use the following procedure to download and debug a project:
Click debug. Debugging of the code is executed at the
beginning of the main function. The following debugging
features are available: single step, step over, and breakpoint.

2.

Begin debugging by either clicking the go icon in the
toolbar as shown in Figure 22, or by navigating to Debug >Go (or by or pressing F5) as shown in Figure 23. The code
then executes on the ADuCM3027/ADuCM3029.

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1.

In the file selection dialogue box, go to the BSP folder, then
go to the examples folder. In the examples folder, go to gpio\
LED_button_polled\ADuCM3029\iar. Click the LED_
button_polled.ewp file and then click the Open button(see Figure 25).

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Figure 21. IAR Debug Toolbar Button

Figure 25. Project Selection Dialogue Box

3.

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Figure 22. IAR Go Toolbar Button

Figure 23. Debug > Go

Rev. B | Page 9 of 51

Build the project by clicking the Project dropdown menu
and navigating to Make. There are no error or warning
messages on the build console.

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To debug the application, click the Project dropdown menu
and navigate to Download and Debug or press Ctrl + D(see Figure 26). After downloading the application, the IDE
switches to debug mode and displays other windows, suchas the Disassembly window, the debug toolbar, and the
debug logger. Click Debug > Go to run the application.

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4.

ADuCM3027/ADuCM3029 User Guide

Figure 26. Download and Debug

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ADuCM3027/ADuCM3029 User Guide

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POWER OPTIMIZATION FOR THE ADuCM3027/ADuCM3029 PROCESSORS
The power consumption of an MCU largely depends on two
factors: the operating voltage and the frequency at which thesystem operates. The ADuCM3027/ADuCM3029 processors
incorporate several power modes that are useful in building
battery-powered or self powered (energy harvesting) applications.

Choosing a low power MCU is a difficult task because it
involves reviewing data sheets to analyze electrical specifications. It
is often difficult to relate these specifications to applicable,
system level use cases.
Evaluating various power modes while considering peripheral
operations emulating real use case scenarios is an essential stepin choosing the right MCU for a power sensitive application.
Key aspects to evaluate when choosing an MCU for low power
applications include the following:
•
•
•
•

•
•
•
•
•

•

This section discusses the power modes of the ADuCM3027/
ADuCM3029 processors in detail and provides example power
measurements for several scenarios, with the intent of helping
developers choose the power modes that best fit low power
application requirements.

Availability of low power modes and the impact of thesemodes on the ability to retain the contents of SRAM.
Power consumption with the RTC running while the restof the system is in low power mode.
Wake-up times from low power mode(s).
Supply voltage range from an application standpoint. The
designer can adjust and select the system supply voltage,
depending on the component requirements.
Power consumption in active mode.
Core activity—example algorithm processing.
Peripheral activity—DMA operations.
Simultaneous core and peripheral activity.
Flexibility in choosing core and peripheral clock frequencies
that meet system requirements while keeping the power
consumption low.
Hardware DMA blocks that enable the CPU to be in low
power mode during peripheral activity.

ADuCM3029/ADuCM3027 PROCESSOR POWER
MANAGEMENT
The ADuCM3029/ADuCM3027 processors incorporate ahighly customizable power management and clocking systemthat offers application developers the flexibility to balance
power and performance. The power management blocks consistof integrated regulators, a clock gating scheme, and switches
applicable to numerous application scenarios.
The power management system features include the following:•

An integrated 1.2 V LDO and an optional capacitive buckregulator.
Integrated power switches for low standby current inhibernate mode.
Power gating to reduce leakage in sleep modes.
A power supply monitor with a selectable voltage range.

•••

ADuCM3029/ADuCM3027 PROCESSOR POWER
MODES

The ADuCM3027/ADuCM3029 processors are an Ultra low
power, integrated, mixed signal, MCU system for processing,
control, and connectivity. The MCU system is based on an
ARM® Cortex®-M3 processor, offering up to 33 MIPS of peak
performance at 26 MHz, combined with a collection of digital
peripherals, embedded SRAM and flash memories, and ananalog subsystem that provides clocking, reset, and power
management capability in addition to an ADC subsystem.

The power management system provides the following low
power modes:••••

The ADuCM3027/ADuCM3029 processors are two of the few
low power MCUs on the market that offer a cache controller.
Programs that repeatedly access the same data or instructions
make effective use of cache memory, thereby reducing theoverall power consumption.

Active mode with customized clock gating features.
Flexi™ mode with smart peripherals.
Hibernate mode with optional SRAM retention capability.
Shutdown mode without SRAM retention.

Each mode provides a low power benefit with potentialfunctionality trade-offs. Table 2 summarizes the status of thesystem blocks in each low power mode.

Table 2. Power Mode System Block States
Functional Block ARM Cortex-M3 Core Buck
Active Mode
On
User 1
Flexi Mode

Off

Hibernate Mode

Off

User1
Off

Shutdown Mode

Off

Off

1
2

PERIPHERAL -DMA HF-XTAL HFOSC LFXTAL PLL

SRAM FLASH
On
On

User1
Off

LFOSC RTC0 RTC1 ADC
On
User1 User1 User1
On
User1 User1 User1
On
User1 User1 Off

Off

Off

1

User

1

User

1

User

1

User

User

User1
Off

User1
Off

User1
Off

User1
User

Off

Off

Off

User

In the user application code, this functional block can be configured to be on or off.
The retainable SRAM size is configurable.

Rev. B | Page 11 of 51

1

User1

Off

Off

On

On

On 2

Off

Off

Off

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ADuCM3027/ADuCM3029 User Guide

Active Mode

Figure 28 compares the power consumption of the ADuCM3027/
ADuCM3029 processors when computing prime numbers withthe following conditions:

In active mode (also called full on mode), the ARM Cortex-M3
is active and executes instructions from flash memory and/or
SRAM. All peripherals can be enabled or disabled at the discretionof the user, and active mode power can be enhanced by
optimized clock management.
Several power saving options are available in active mode:

VBAT = 3.0 V
HCLK = PCLK = 26 MHz
Cache memory disabled

The buck converter impacts current consumption positively athigher VBAT values. Specifically, there is roughly a 50%
decrease in the active current when VBAT ≥ 3 V.

Using the buck converter.
Enabling the cache.
Dynamic clock scaling.
Clock gating.

3.0
BUCK OFF
2.5

Buck Converter
The optional integrated buck converter feature saves power in
active mode. The buck converter powers the linear regulator,
which powers the digital core domain. The buck converter
enters bypass mode after the battery voltage (VBAT) falls below~2.3 V. After entering bypass mode, the buck converter output
follows the input. Figure 27 shows the external circuitry
recommended for buck converter enabled designs.

IBAT (mA)

2.0

1.0

0.5

0

VDCDC_CAP1P

VBAT
BUCK
(ENABLED)VDCDC_CAP1N

1.7

0.1µF

2.3

2.5

2.7

2.9

3.1

3.3

3.5

3.7

Cache memory reduces the average time to access data fromflash memory. For scenarios where the CPU is required to run
an algorithm, or when the same data must be accessed repeatedly,
cacheable memory can reduce the power consumption because
execution is from the internal instruction SRAM. When thecache controller is enabled, 4 kB of instruction SRAM isreserved as cache memory.

VDCDC_CAP2P
0.1µF

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VLDO_OUT
0.47µF

2.1

Figure 28. Impact of the Buck Converter on Active Mode Power Consumption
Enabling Cache Memory

0.47µF

LDO

1.9

VBAT (V)VDCDC_OUTVDCDC_CAP2NBUCK ON

1.5

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•
•
•
•

•
•
•

Cache memory is disabled at startup by default. Use thefollowing procedure to enable the cache memory:

Figure 27. External Circuitry for Buck Converter Enabled Designs

For designs in which the optional buck converter is not used,
the VDCDC_CAP1P, VDCDC_CAP1N, VDCDC_OUT,VDCDC_CAP2P, and VDCDC_CAP2N pins must be left
unconnected.
The buck converter is solely for processor usage. An externalload cannot be connected to the buck converter output.

1.

2.

Read the cache enable status bit (Bit 0 in the
FLCC0_CACHE_STAT register) to ensure that cachememory is disabled. Poll this bit until it clears.
Write the user key to the FLCC0_CACHE_KEY register.
For example, write*pREG_FLCC0_CACHE_KEY = 0xF123F456;

Enable the buck converter by setting the CTL1.HPBUCKEN bit
per the following code:

3.

*pREG_PMG0_CTL1 |= (1<<BITP_PMG_CTL1_HPBUCKEN);*pREG_FLCC0_CACHE_SETUP |= (1 <<BITP_FLCC_CACHE_SETUP_ICEN);

Rev. B | Page 12 of 51

Set the instruction cache enable bit (ICEN in the
FLCC0_CACHE_KEY register) as follows:ADuCM3027/ADuCM3029 User Guide

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Figure 29 compares the power consumption of the ADuCM3027/
ADuCM3029 processors when computing prime numbers withthe following conditions:
•
•
•

3.0

2.5

VBAT = 3.0 V
HCLK = PCLK = 26 MHz
Buck converter disabled

IBAT (mA)

2.0

3.0

1.5

1.0
CACHE OFF
2.5

0.5
CACHE ON

0

10

20

15

25

HCLK (MHz)Figure 30. Impact of Core Clock Frequency on Active Mode Power
Consumption

1.0

As can be expected, power dissipation decreases as core clock
frequency decreases.

0.5

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

3.5

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0
3.7

VBAT (V)Figure 29. Impact of Cache Memory on Active Mode Power Consumption

Enabling the cache memory reduces the average active current
consumption by ~18%.

Dynamic Clock Scaling
Dynamic clock/frequency scaling is a proven method to reduce
power consumption. The ADuCM3027/ADuCM3029 processors
have a flexible clock architecture that allows dynamic modificationof the CPU and peripheral clock frequencies. A combination ofclock dividers and a phase-locked loop (PLL) provides flexibility inderiving an optimum system clock frequency that guarantees
system performance while keeping the power consumption low,
as compared to a fixed clock scheme. Programmable clock dividers
are available to generate the clocks in the system, and thedivisors can be configured on-the-fly.
Figure 30 plots the power consumption of the ADuCM3027
ADuCM3029 processors when computing prime numbers withthe following conditions:
VBAT = 3.0 V
HCLK = PCLK (the source of the root clock is HFOSC)
Buck converter disabled
Cache disabled

Clock Gating
The system is heavily clock gated and uses automatic clock
gating techniques. Most peripherals are automatically clockgated when the peripheral is disabled, such that the clock is
running only when the peripheral is enabled. The exceptions
are I2C, GPIO, and the general-purpose timer (GPTMR). These
blocks must be manually clock gated using the CLKCON5 register.
Gate the peripheral clock completely by setting the
CLKCON5.PERCLKOFF bit.
Any access to the clock gated peripherals overrides the clockgate settings in the CLKCON5 register.
For application scenarios where the core is processing data andno peripheral activity is desired, the peripheral clock (PCLK)
can be turned off to save power. Figure 31 shows the power
consumption of the ADuCM3027/ADuCM3029 processors
when computing prime numbers with the following conditions:••••

VBAT = 3.0 V
Buck converter disabled
Cache memory disabled
HCLK = PCLK = 26 MHz
3.0
PCLK ON
2.5
PCLK OFF
2.0

IBAT (mA)

•
•
•
•

5

1.5

15388-104

0

1.5

1.0

0.5

0
1.7

1.9

2.1

2.3

2.5

2.7
VBAT (V)

2.9

3.1

3.3

3.5

3.7

15388-105

IBAT (mA)

2.0

Figure 31. Impact of Peripheral Clock Gating on Active Mode Power Consumption
Rev. B | Page 13 of 51

UG-1091

ADuCM3027/ADuCM3029 User Guide•••

As shown in Figure 31, a ~0.2 mA reduction in the active
current is observed when the peripheral clock is gated.
In active mode, the four techniques described in this section
can be combined to achieve maximum power savings.

Cache memory disabled
PCLK = 6.5 MHz
SPI_DIV = 49
0.5

Flexi Mode

BUCK OFF

•
•
•
•
•

VBAT = 3.0 V
Buck converter disabled
Cache disabled
PCLK = 6.5 MHz
SPI_DIV = 49

IBAT (mA)

0.8

0.6
FLEXI MODE
0.4

0
2.3

2.5

2.7

2.9

3.1

3.3

3.5

VBAT (V)

3.7

15388-106

0.2

2.1

Figure 32. Impact of Flexi Mode on Power Consumption

As shown in Figure 32, there is nearly a 66% savings in power
when Flexi mode is used while the DMA is ongoing, rather thankeeping the core in active mode.
There are a number of wake-up sources that can be used to exit
Flexi mode (for example, DMA interrupts, external interrupts,
timer interrupts, and so on), and it typically takes only one CPU
clock cycle to exit.

0.1

0
1.7

1.9

2.1

2.3

2.5

2.7
VBAT (V)

2.9

3.1

3.3

3.5

3.7

Figure 33. Impact of the Buck Converter on Flexi Mode Power Consumption

As seen in Figure 33, a similar power improvement pattern to theimpact of the buck converter in active mode is shown in Figure 28.
Specifically, when VBAT ≥ 3 V, a 50% improvement in power isobserved.

Before entering hibernate mode, most of the enabled peripherals
must be programmed to undergo a specific sequence to properly
enter or exit hibernate mode, and several system memory map
registers (MMRs) and peripheral registers are retained while inhibernate mode. For more details, refer to the relevant peripheral
information in the ADuCM302x Ultra Low Power ARM CortexM3 MCU with Integrated Power Management Hardware
Reference.

Configurable Retainable SRAM
The ADuCM3027/ADuCM3029 processors support SRAM
block sizes of 8 kB (default), 16 kB, 24 kB, and 32 kB to beretained while in hibernate mode. The more SRAM that must
be retained, the higher the power consumption is while inhibernate mode, as shown in Figure 34.

The buck converter can also be enabled in Flexi mode to save
additional power. Figure 33 shows the power consumption of
the ADuCM3027/ADuCM3029 processor across VBAT in Flexi
mode with the buck converter on while transferring data over
the SPI using DMA accesses with the following conditions:•

0.2

In hibernate mode, the ARM Cortex-M3 core and all digital
peripherals are off with configurable SRAM retention, port pin
retention, a limited number of wake-up interrupts, and,optionally, an active RTC. All GPIO pin states are retained inhibernate mode. The ADuCM3027/ADuCM3029 processors
also incorporate the SensorStrobe™ mechanism in the RTC
block, which enables ultra low power sensor data measurement.

ACTIVE MODE

1.9

BUCK ON

Hibernate Mode

1.0

1.7

0.3

15388-107

Consider a scenario where the CPU configures an SPI DMA
and must wait for the DMA to complete. Figure 32 shows thepower consumption of the ADuCM3027/ADuCM3029
processors transferring data over the SPI using DMA accesses
with the following conditions:

0.4

IBAT (mA)

Flexi mode is a flexible sleep mode useful in scenarios where
the core must wait for a peripheral data transfer to complete
before it can start processing. In Flexi mode, the core is clockgated and the remainder of the system is active. Flexi mode canbe used to substantially reduce active power when a very low
speed activity is expected to complete (for example, reading acertain number of bytes from a sensor) before the processor
must be woken up to process the data.

VBAT = 3.0 V
Rev. B | Page 14 of 51

ADuCM3027/ADuCM3029 User Guide

UG-1091
1.2

32k
24k
16k
8k

1.0

IBAT (µA)

0.8

LFOSC

0.6

0.6

0.2

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

3.5

3.7

VBAT (V)0
1.7

The SRAM retention size can be configured by setting theappropriate bits in the SRAMRET register. For example, toenable 32 kB of SRAM to be retained while in hibernate mode,use the following code in the SRAMRET register:*pREG_PMG_PWRKEY = 0x4859;*pREG_PMG_SRAMRET |=((1 << BITP_PMG_SRAMRET_SRAM_RET1_EN)|(1 << BITP_PMG_SRAMRET_SRAM_RET2_EN));If parity is enabled, initialization of nonretained SRAM regions
may be required upon waking from hibernate mode.

Wake-Up Sources

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

3.5

3.7

VBAT (V)Figure 34. Current on the VBAT Supply Pin (IBAT) for Various Retained SRAM
ValuesFigure 35. Hibernate Current with RTC1 as the Wake-Up Source (LFOSC vs.
LFXTAL)

SensorStrobe
The SensorStrobe mechanism allows the ADuCM3027/
ADuCM3029 processor to be used as a programmable clock
generator in all power modes, including hibernate mode. In
this way, the external sensors can have their timing domains
mastered by the ADuCM3027/ADuCM3029 processors because
the SensorStrobe output is a programmable divider from
FLEX_RTC, which can operate up to a resolution of 30.7 µs.
The sensors and microcontroller are synchronous, whichremoves the need for additional resampling of data to time alignthe microcontroller and the sensors.

Shutdown Mode

The following events are capable of waking the devices up fromhibernate mode:
External Interrupt 0 to External Interrupt 3
RTC0 and RTC1 interrupt
Battery voltage range interrupt
UART Rx pin activity

Of the two real-time clocks, RTC1 is the recommended wakeup source from hibernate mode because, in an application where
both hibernate mode and shutdown mode must be used, only
RTC0 can be used for exiting shutdown mode.
The wake-up time from hibernate mode from any of these
events is ~14 µs when executing from flash, and ~10 µs when
executing from SRAM.

RTC Clock Sources
The ADuCM3027/ADuCM3029 processors offer two clock
choices for the RTC1 block:
•
•

0.8

0.4

0.5

•
•
•
•

LFXTAL

0.7

15388-108

IBAT (µA)

0.9

1.0

15388-109

1.1

A low power internal RC oscillator (LFOSC)
An external crystal oscillator (LFXTAL)

Choosing to implement either LFOSC or LFXTAL is a trade-off
between accuracy and power consumption. LFXTAL is moreaccurate (depending on the crystal manufacturer) compared to the
LFOSC, but LFOSC dissipates less power, as shown in Figure 35.

Shutdown mode is the deepest sleep mode, in which digital andanalog circuits are powered down. The state of the digital core
and the SRAM memory content is not retained; however, thestate of the pads is preserved, as is the wake-up interrupt
configuration.
The configuration of the pads is preserved and locked after
waking up from shutdown mode. The user must unlock thestate of the pads by writing 0x58FA to the PGM_TST_CLR_
LATCH_GPIOS register, preferably inside the ISR routine:*pREG_PMG0_TST_CLR_LATCH_GPIOS = 0x58FA;

Additionally, the user must configure the appropriate wake-up
source, choosing from the following options:••••

External Interrupt 0 to External Interrupt 2External reset
Battery falling below 1.6 V
RTC0 timer

The RTC0 block can (optionally) be enabled in this mode,
which allows the processor to be periodically woken up by the
RTC0 interrupt.
The clock source for RTC0 must be the LFXTAL because the
LFOSC is disabled in shutdown mode.

Rev. B | Page 15 of 51

UG-1091

ADuCM3027/ADuCM3029 User Guide

Because the RTC0 block must be powered to serve as a wake-up
source, it adds to the power dissipation while in shutdown
mode, as shown in Figure 36.

400

SHUTDOWN + RTC
300
250

IBAT (nA)

200
150
100

SHUTDOWN

50
0
1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

3.5

3.7

VBAT (V)Figure 36. Shutdown Mode Current (External Sources vs. RTC0)

Rev. B | Page 16 of 51

15388-110

When the device wakes up from shutdown mode, the POR
sequence is followed, and code execution starts from the
beginning.

350

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UG-1091

FAST WAKE UP FROM HIBERNATE MODE
FLASH MEMORY AND INSTRUCTION SRAM
Flash memory is the long-term storage medium for any microcontroller. Because the flash memory is nonvolatile, it is used
for storage of constant data and program code of the
microcontroller. Due to the nature of flash memories, memory
access is slow compared to SRAM, cache, and other registers.
The latency takes effect during the execution of a looping codethat performs real-time calculations.

Figure 37 shows the delay time from triggering an external
wake-up signal to microcontroller response by lighting up alight emitting diode. The red trace is the signal from the pushbutton that triggers an external interrupt signal to wake up the
microcontroller. The blue trace is the GPIO toggling indicatingthat the microcontroller is awake; that is, the first instruction
executed is a GPIO_TGL. The entire wake-up process takes
about 10 µs to complete.

The ADuCM3027/ADuCM3029 microcontroller has thecapacity to execute instructions in SRAM. Instruction SRAM(iSRAM) is a portion of the ADuCM3027/ADuCM3029
microcontroller dedicated to be a temporary program code andinstruction storage. It is used when the program must execute alooping code faster and does not want the flash latency to affect theexecution. The iSRAM is small (up to 32 kB) compared to the
flash memory (128 kB and 256 kB on the ADuCM3027 and
ADuCM3029, respectively); therefore, only important code andinstructions must use the iSRAM.

1
2

An interrupt from one of the allowed wake-up sources bootsthe microcontroller from hibernate to active mode to service
the interrupt. Refer to Hardware Reference Manual document
for further information about the possible interrupt wake-up
sources. During the transition from hibernate to active mode,the microcontroller reinitializes the digital peripherals that are
off during hibernate before it executes the first instruction on
the interrupt service routine (ISR).

CH1 1.00V
0mV OFFSET

CH2 1.00V
0mV OFFSETTIMEBASE –8.00µs
2.0µs/DIV
50.0kS 2.5GSPS

TRIGGER C1 DC
STOP 0.00V
EDGE NEGATIVE

Figure 37. Normal Wake Up from Hibernate Mode Response

FAST WAKE UP
One way to wake up from hibernate faster is to move therequired functions and instructions to iSRAM. The microcontroller
code starts earlier, because the code must not wait for thecompletion of the flash memory initialization.
Figure 38 shows the delay time from triggering an external
wake-up signal to microcontroller response with fast wake-up
procedure. The red trace is the signal from the push button, andthe blue trace is the GPIO toggled as first instruction after
waking up.
The wake-up time is reduced to 5 µs; this supposes a 50%
improvement with respect to normal wake up.

The flash memory, where the program code is located, is also
off during hibernate mode. Upon microcontroller wake up, thecore turns on the flash memory. The flash memory initialization isslow, and it takes about 5.7 µs to complete before it can takecommands from the controller.

1
2

CH1 1.00V
0mV OFFSET

CH2 1.00V
0mV OFFSETTIMEBASE –8.00µs
2.0µs/DIV
50.0kS 2.5GSPS

TRIGGER C1 DC
STOP 0.00V
EDGE NEGATIVE

Figure 38. Fast Wake Up from Hibernate Mode Response

Rev. B | Page 17 of 51

15388-802

The Cortex-M3 core and all the digital peripherals (except someuser-selectable SRAM blocks) are turned off during hibernate.
The real-time clocks (RTCs) can be configured by the user
program to turn off during hibernate. (RTC0 and/or RTC1 may
be on, depending on the user configuration.) Registers of thedigital peripherals are also turned off, which ensures the low
current consumption of the microcontroller during hibernatemode, though some registers are retained to allow the device towake up in the same status it was in when it went to sleep.

15388-801

NORMAL WAKE UP

UG-1091

ADuCM3027/ADuCM3029 User Guide

Table 3. Wake-Up Times with Different Peripherals
ADuCM3029 Peripheral Activity
Pin Toggle (Lighting an LED)I2C Clock (First Edge, 400 kHz)SPI Clock (First Edge, 400 kHz)

Normal Wake-Up Time (µs)
9.9
12.5
12.7

Fast Wake-Up Time (µs)
4.7
7.3
7.5

Table 3 shows a comparison of the wake-up times to different
peripherals. The wake-up time is measured from the falling edge ofthe external wake-up signal to the first rising edge of the serial
clocks (as for I2C and SPI) or the rising edge of the pin connectedto the light emitting diode.

Interrupt Vector Table Relocation
The interrupt vector table (IVT) lists the different interrupt
sources for the ADuCM3027/ADuCM3029 microcontroller.
The following events are capable of waking the MCU up fromhibernate mode:

The steps to perform fast wake up from hibernate mode are as
follows:

•
•
•
•

1.
2.
3.
4.

Initialize the iSRAM.
Modify the linker script to add the section for thefunctions and to remap the addresses.
Relocate the interrupt vector table (VTOR) from flash to
SRAM.
Place the required functions and interrupt handlers in
iSRAM.

Initialization of the iSRAM.
To use the iSRAM, take the following steps:
1.
2.

Enable the iSRAM bank by asserting the
PMG0_TST_SRAM_CTL.INSTREN bit field.
Retain the half of the iSRAM by asserting the
PMG0_TST_SRAM_CTL.BNK2EN bit.

External Interrupt 0 to External Interrupt 3
RTC0 and RTC1 interrupt
Battery voltage range interrupt
UART receiver (Rx) pin activity

For fast wake up, move the IVT from flash to SRAM. In thisway, the microcontroller does not have to wait for the flash
initialization to check the location of the interrupt handler ofthe wake-up source.
Copy the IVT to SRAM and update the SCB register to VTORof the address of interrupt vector in SRAM. If using the board
support package of ADuCM3027/ADuCM3029, declare
RELOCATE_IVT by adding it to the C/C++ Compiler/
Preprocessor tab (see Figure 39) to activate the relocation code
built-in in the board support package.

Modification of the Linker Script
Modify the linker script to help the linker place the code in thecorrect place in the memory map. Remap the addresses and add
the required sections for the location of the program code andinterrupt handlers to iSRAM.
If using the IAR embedded workbench, apply the followingchanges to the linker script:
1.

Remap of SRAM addresses. Search for the following line in
the linker script:
define symbol USER_SRAM_MODE = 0;// iSRAM section for placing code in SRAM
place in SRAM_CODE {section ISRAM_REGION };15388-803

2.

Change the value of the USER_SRAM_MODE to 0 or 1.
Add section for iSRAM. Search the linker script for thefollowing lines:

Figure 39. IAR C/C++Compiler Options—RELOCATE_IVT Directive in the
Defined Symbols Textbox

initialize by copy {section ISRAM_REGION };Modify the lines to include the .textrw section. IAR linker
places the instructions for SRAM in the section .textrw.
// ISRAM section for placing code in SRAM
place in SRAM_CODE {section ISRAM_REGION,
section .textrw};
initialize by copy {section ISRAM_REGION,
section .textrw};
Rev. B | Page 18 of 51

ADuCM3027/ADuCM3029 User Guide

UG-1091

Placement of Program Code to SRAM
The procedure of placing the program code to SRAM is
dependent on the compiler used.
For most compilers, use the following line before the function
definition to tell the location of the defined function:#pragma location=”<linker_section>”
15388-804

For IAR Embedded Workbench, use the __ramfunc keyword
before the function (see Figure 40).
Figure 40. Sample for Appending __ramfunc Directive to a Function

Note that the iSRAM only retains half of its memory from
0x1000_0000 to 0x1000_3fff during hibernate. The memory
outside this range is not retained; therefore, do not put thecodes outside the retained region.

Rev. B | Page 19 of 51

UG-1091

ADuCM3027/ADuCM3029 User Guide

USING THE ADuCM3029/ADuCM3027 PROCESSOR BOOT KERNEL
0x407FFINFORMATION SPACE(2kB)

DEVICE INFORMATIONBOOT KERNEL
0x40000
0x3FFFF

USER SPACE(UP TO 256kB)

0x000015388-601

USER APPLICATION CODE

Figure 41. Flash Information Memory Space

The ADuCM3029/ADuCM3027 processors feature integrated
flash memory that contains the user application code (userspace) and a dedicated 2 kB bank of memory, information spacearranged as shown in Figure 41.
Some devices feature 128 kB of user space. Refer to the
ADuCM3027/ADuCM3029 data sheet for details.
As shown in Figure 41, the information space block is further
broken down into the boot kernel, residing in the upper 2 kB of
flash memory, and the device information. The boot kernel is
responsible for implementing a secure environment, where user
application code can optionally be read and/or write protected,
and executes the application from flash memory upon reset.
The boot kernel also provides a mechanism to upgrade thefirmware through a UART downloader.
This section describes the information space region of the onchip flash memory, as well as both the boot process and how to
use the UART downloader to perform field upgrades to theprocessor firmware.

BOOT KERNEL OVERVIEW
The boot kernel switches to the user application after
performing certain checks (including the CRC integrity of theuser application), or the boot kernel enters UART downloader
mode to upgrade the user application in flash memory, dependingon the SYS_BMODE0 boot mode pin state at reset.
The boot kernel supports in field updates to the user application
through the UART port. For security reasons, the boot kernel
itself does not provide the flash programming feature; however,it allows the firmware update code, which has flash driver codefor updating the user flash, to be downloaded to the device over
the UART port. This code is referred to as a second stage loader(SSL) and is run from SRAM. The SSL must be authenticatedbefore it can be provided run access. The security scheme
implemented is discussed in the following sections, describing
the critical part of the kernel to provide the secure environment
in which the user code can be read and/or write protected,
allowing intellectual property security.

The serial download capability allows developers to reprogram
the device while it is soldered directly onto the target system,
avoiding the need for an external device programmer andremoving the need to swap the device out of the system. The
serial download feature also enables system upgrades to be
performed in the field, provided the hardware infrastructure
involving the SYS_BMODE0 pin and the UART port are
implemented on the target board.

Configuring Security Options
The boot kernel provides the flexibility to configure the security
options of the device by allowing the user to program certain
keys and parameters in predefined locations in Page 0 of theuser flash memory. The kernel provides the user code security
and integrity, which depends on the number of user-definedparameters in the first page of the user flash memory. Table 4summarizes the list of keys and parameters, as well as theirlocations in the user flash memory.
Table 4. List of Keys and Parameters
Address Range
0x0000_0180 to
0x0000_018F
0x0000_0190 to
0x0000_0193
0x0000_0194 to
0x0000_0197

Size
128 bits(16 bytes)
32 bits(4 bytes)
32 bits(4 bytes)

0x0000_0198 to
0x0000_019B
0x0000_019C to
0x0000_019F

32-bitword
32-bitword

Description
Read protection key hash
CRC of read protection key hash
Length of user boot loader or
entire user code (used for CRC
verification before boot)In-circuit write protection if set
to NOWRCPU write protection ofindividual flash blocks

Read Protection Key Hash
Program the 128-bit read protection key hash at
Address 0x00000180 in the first page of the user flash memory.
The value of this hash depends on the kind of security desiredin the system because this security defines the read accessibility
to the device. The key hash defines the state of the serial wire
debugger (SWD), as well as the access permission of the SSL
downloaded for upgrades via the UART:•••

Rev. B | Page 20 of 51

The reset state of the flash memory of all logic high memory
cells (along with a valid key hash CRC) indicates that theuser does not desire read protection. In this case, the SWD
interface is automatically enabled during booting.
Any nonreset value results in the SWD being locked;
therefore, there is no SWD access to the device.
The key hash is the 128-bit, truncated secure hash algorithm(SHA-256) of the user key (which is 128 bits in length), which
can be sent along with the SSL during the UART download
phase. If the user key is valid and the hash of the received
key matches the key hash stored, the SSL runs with all
permissions. If the user key fails the key hash check, the
SSL only has write permission to the user flash.

ADuCM3027/ADuCM3029 User Guide

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Key Hash CRC

User Code CRC

The key hash has a 32-bit CRC checksum stored at
Address 0x00000190. The key hash is valid only if the associated4-byte checksum is valid. The key hash has a separate key hashto protect it against flash tempering attacks. For all practical
purposes, the user must ensure that a valid CRC for the key
hash is stored along with the key hash itself.

The user code CRC is stored at the end of Page N. The 32-bit
CRC (MSB first) with a polynomial of 0x4C11DB7 is expectedby the kernel. If the page number is N, the CRC is expected toreside at flash memory address (N × 0x800) + 0x7FC. For example,
if N = 5, a total of six pages are CRC protected, and the CRC isstored at Address 0x2FFC. There is an option to disable the
CRC check by programming 0xFFFFFFFF to the expected CRC
location. After the kernel sees this value in the CRC location, it
skips the CRC check.

In-Circuit Write Protect Key
The 32-bit in-circuit write protect key at Address 0x00000198 of
the user flash memory prevents in-circuit programming of thedevice. To disable in-circuit reprogramming, program thehexadecimal value of the NoWr ASCII string (without theterminating null character) to this address. In this case, SWD
access to the device is locked, and the only way to update thedevice code is via the UART downloader.
Use in-circuit write protection along with read protection(providing both read and write protection). In-circuit write
protection alone does not have any significance.

Write Protection
Pages can be locked to prevent code from accidentally erasing
and reprogramming critical flash memory blocks (such as theuser code boot loader). There is a hardware register in the flash
controller that disables the programming of pages grouped into
blocks. This register is not automatically loaded via the hardware;rather, it is written to via the kernel. The kernel reads the write
protection word from the user flash address, Address 0x0000019C,
and writes it to the write protection register in the flash controller.
The user can write the appropriate word to this location, dependingon the pages that are intended to be protected against accidental
writes. The pages are protected in groups of four, with each bit
in the 32-bit word corresponding to four continuous flash
pages. Refer to the ADuCM302x Ultra Low Power ARM CortexM3 MCU with Integrated Power Management Hardware
Reference Manual for details.

User Code Length
There is a 32-bit value stored at a flash memory address,
Address 0x00000194, that defines the CRC protected user code
length. The value programmed in this field defines the page
number of the user flash memory up to which the CRC
protection is desired by the user. The value of N means that
CRC protection is desired from Page 0 to Page N of the flash
memory, protecting a total of N + 1 pages.
Valid values for the field in Address 0x00000194 are 0 to 127 forthe 256 kB ADuCM3029 processor, and 0 to 63 for the 128 kB
ADuCM3027 processor. Any value outside this range is treatedas invalid and results in a CRC check failure.

Boot Code Flow
This section describes how the kernel operates, based on theuser programmable parameters described previously. Figure 42
shows a flowchart of the boot code.
After reset, the boot kernel inspects all the parameters stored inPage 0 of the user flash memory. The user has not requested theread protection if the user read protection key hash is not programmed (meaning that it is set to all FFs) and the key hash CRC isvalid. As such, the SWD is enabled; however, flash access may
be protected, depending on the state of the user code CRC.
If the CRC is valid, access to user flash memory is unrestricted.
If the user disables the CRC by programming 0xFFFFFFFF to
the CRC location, access to the user flash memory is alsounrestricted.
If the CRC is invalid, the user flash memory is protected withno read or write access allowed. Only the flash mass erasecommand is allowed. In this case, user code execution is notallowed.
Take care to program a valid CRC (or 0xFFFFFFFF) in thedefined CRC location; otherwise, the user flash memory is readprotected by the kernel. In this case, flash-based applications
fail to load unless the user flash memory is mass erased.
If the user read protection key hash is programmed with anonreset value, meaning that the read protection is enabled, orif the key hash CRC is invalid, the SWD is disabled by the
kernel and SWD access to the device is not possible. Perform
this programming only after product development is complete
and SWD access is not intended in the field. However, whenread protection is enabled, the SWD is opened up only if CRC
protection is enabled and the CRC is corrupted, which allows
device recovery when the CRC is accidentally corrupted. In thiscase, the SWD is opened up, but the user flash memory is protectedwith no read, write, or page erase accessibility (to maintain theuser code confidentiality while allowing device recovery). However,mass erase is still possible, which results in the user flash
memory being open again (with read and write access).

Rev. B | Page 21 of 51

UG-1091

ADuCM3027/ADuCM3029 User Guide
After the device is programmed via the SWD, the user flash
memory is no longer blank, and the kernel relies on the state of
the SYS_BMODE0 pin to decide if the user code must be
executed (after performing all the previously explained checks),
or if the boot kernel must enter the UART downloader mode.

The user flash memory (user space) is completely blank whenshipped; therefore, none of the security keys and parameters areprogrammed. Therefore, most of the parameters, such as the
key hash CRC and the user code length, have invalid values,
meaning the parameters are all set to 0xFF. In this case, thekernel performs a check of the user flash memory to identify if
it is blank or completely unprogrammed. If the user flash isblank, the kernel skips all the checks and opens up the SWD. In
addition to opening up the SWD, which allows users to connect
to the device through SWD for their development, the bootkernel also enters the UART downloader mode and awaits
reception of the SSL.

If the SYS_BMODE0 pin is asserted (low), the kernel enters the
UART downloader and waits for the SSL to be downloaded.
If the SYS_BMODE0 pin is deasserted (high), the kernel jumps
to the user reset vector in the user flash memory after
performing all the security checks.
The only case where the kernel enters the UART download
mode without sampling the SYS_BMODE0 pin is when the user
flash memory is blank.

ADI
BOOT LOADER
ENTRY

POINT VTORTO INFO AREA AND
REMAP FLASHKEY HASH
ALL ONES AND
HASH CRC
VALID?

YES

ENABLESWD

YES

ENTER UARTDOWNLOADER

READ PROTECTIONNOT ENABLED

NO

BOOT PINASSERTED?

NO

CRC LENGTHVALID?

NO

USER FLASHENTIRELYBLANK?

CRC ALL ONES?

ENABLE SERIAL WIRETO PERMIT CUSTOMERTO RECOVER BAD CRC

NO
USER
BOOT BLOCKCHECKSUM
VALID?
YES

BOOT USER CODENOBAD CRC
OR LEN

IN-CIRCUITWRITE PROTECTENABLED?
NO SWD ACCESSIF ICWP ISYESENABLEDNOENTER UARTDOWNLOADERLOAD FLASHWRITE PROTECTREAD PROTECTUSER FLASHENABLESWD

ENABLE
SWD

WAIT FORSWD CONNECTION

POINT VTORTO USER AREA

15388-602

SKIP
CRC CHECKBLANK DUT, TYPICALDEVELOPMENT/MANUFACTURE

NO

YES

YES

YES

EXECUTEUSER CODE

Figure 42. Boot Kernel Flowchart
Rev. B | Page 22 of 51

ADuCM3027/ADuCM3029 User Guide

UG-1091
with the kernel and the SSL is uniform). The details of the
protocol are discussed in the following sections.

SSL code that is downloaded over the UART must be mapped to
the SRAM. In UART downloader mode, the SSL is loaded to the
SRAM and has flash programming capabilities. The kernel
authenticates the SSL and allows execution only if authentication is
successful. This code is responsible for downloading and upgrading
the actual firmware (for example, the user application) in theuser flash memory. The kernel does not support direct updates
to the user flash memory; therefore, the SSL is required toperform such actions.

UART DOWNLOADER
The ADuCM3027/ADuCM3029 processors enter UART
downloader mode if the SYS_BMODE0 pin (GPIO17) is pulled
low. If this condition is detected by the device at power-on or
hard reset, the device enters serial download mode. In this mode,an on-chip loader routine in the kernel is initiated, which configures the UART port of the device and, via a specific serial
download protocol, communicates with a host to manage thefirmware upgrade process. Figure 43 shows the UART
downloader flow.

The kernel follows a specific protocol to download the SSL tothe processor, which must be adhered to by the transmitting
host. If the SSL follows the same packet protocol as the kernel,
the host interface is simplified (for example, communication

UART
DOWNLOADEREMPTY‘\r’ OR ‘\n’?

YESNOWAIT FORAUTOBAUD CHARACTERINFOCOMMAND?

SENDPART NUMBER,SERIAL NUMBER,
KEY_HASH,
USER CODE STATUS

YES

CONFIGURE UARTNOGET COMMANDDOWNLOAD
COMMAND?

NOSEND NAK(INVALID
COMMAND)NOSEND NAK(INVALID
COMMAND)YES
ERROR
DETECTED?
(UART BREAKOR FRAMING)YESWAIT FOR START(UART RE-AUTOBAUD)DOWNLOAD
CODE TO SRAMNORUNCOMMAND?
YESPERMISSIONVALID?

NOIS ICWPENABLED?

YES

SEND NAKNOEXECUTE CODEIN SRAMUNRESTRICTEDREAD PROTECTUSER FLASHEXECUTE CODEIN SRAM

Figure 43. UART Downloader Flowchart

Rev. B | Page 23 of 51

GET
COMMAND

15388-603

PROCESS RX
COMMAND

UG-1091

ADuCM3027/ADuCM3029 User Guide

Protocolmemory, and security restrictions. After the autobaud
acknowledgement, the data transfer itself can begin, as
governed by the communications data transport packet format
shown in Table 6.

After the serial downloader is triggered by asserting the
SYS_BMODE0 pin, the kernel waits for the host to send acarriage return character (ASCII 0x0D, as shown in Figure 44)
to initiate the UART autobaud process.

Packet Start ID Field, ID0 and ID1

The kernel makes use of the UART autobaud feature to detect
the baud rate of the host and to subsequently configure the
UART port to transmit or receive, at thebaud rate of the host,with eight data bits and no parity. Due to the 6.5 MHz reset
peripheral clock (PCLK), the UART can be configured by the
kernel to support baud rates up to 230,400 bps. Baud rates greater
then this value contain more errors and may result in an unreliabledata transfer. However, after loading the SSL, higher baud rates
are possible if the SSL increases the PCLK (up to 26 MHz) andperforms a second autobaud detection via the UART.

The first transfer field is the two-byte packet start ID field (ID0and ID1), comprised of two start characters (0x07 for ID0 and
0x0E for ID1). These bytes are constant and are used by theloader to detect the beginning of a valid data packet.

Number of Data Bytes Field
The next transfer field is the total number of data bytes field,
which includes the 1-byte command (CMD), the 4-byte address(value), and the remaining payload (data). The minimum
number of data bytes is five, which corresponds to a command
and address only. The maximum number of data bytes is 255,
supporting a command, an address, and up to 250 bytes of data.

After receiving the autobaud character, the kernel calculates therequired clock divisor values and configures the UART, at which
point the kernel sends the device information as part of a 57-byte
ID data packet, as shown in Table 5, to acknowledge that the
autobaud detection process is successful.

Command Function Field (CMD), Data Byte 1

Packet Structure

The command function field describes the function of the data
packet. Three commands are supported by the kernel,
represented in ASCII format:

In addition to indicating to the host that the processor is now
ready to communicate, the autobaud acknowledgement also
contains information about the device, the state of the user flash•••

W (0x57)—write command
R (0x52)—run commandI (0x45)—information command

CR = ‘\r’ = 0x0D
D0

D1

D2

D3

D4

D5

D6

D7

STOP
15388-604

START

8-BIT MEASUREMENT TIME

Figure 44. Autobaud Character

Table 5. Autobaud Response
Bytes
1 to 15
16 to 18
19
20
21
22
23
24 to 55
56
57

Contents
Product identifier: ADuCM302xand six spaces, where x = 7 or 9
Hardware and firmware version numbers
User code blank; x means the code to execute, and a dash (-) means the user code is blank
User code checksum; P means that the checksum passed, and F means that the checksum failed
Write protection enabled; W means that write protection is disabled, and a dash (-) means that the write protection is enabled
Read protection enabled; R means that read protection is disabled, and a dash (-) means that read protection is enabledSpace
128-bit serial number, as a 32-digit uppercase hexadecimal number (for example, 0123456789ABCDEF0123456789ABCDEF)
Line feed
Carriage return

Table 6. UART Packet Structure
ID0
0x07

ID1
0x0E

Number of Data Bytes
5 to 255

CMD
W, R, or I

Rev. B | Page 24 of 51

Valueh, u, m, l

Data
xx

ChecksumCS

ADuCM3027/ADuCM3029 User Guide

UG-1091

Write Command

Run Command

The write command packet shown in Table 7 includes thenumber of data bytes (5 + n, where n is the payload size in bytes),
the write command (W), the 32-bit start address to write to, andthe n data bytes in the payload.

After the host transmits all the data packets to the kernel, it cansend a final packet instructing the kernel to start executing
code. This final packet is achieved by sending the run command
packet, which is comprised of the run command (R) and the32-bit address to begin running from, as shown in Table 8.

When a write command packet is received by the kernel, thepayload bytes are placed sequentially in the SRAM as they arrive,
beginning at the start address. The kernel sends a no acknowledgecommand if the checksum is incorrect or if the received address
is out of range. If the host receives a no acknowledge from theloader, abort and restart the download process.

When the kernel receives a run command packet, it jumps tothe address supplied in the packet only after the permission
checks pass.

Information Command
The host can send the information command packet shown in
Table 9 at any time; this packet is comprised of the command(I) and a 32-bit address. Though the value field is required forthe packet to be properly received by the kernel, the content of
the value field is irrelevant.
When the kernel receives the information command packet, it
responds with the 57-byte ID packet (see Table 10).

Table 7. Write Command Packet
ID0
0x07

ID1
0x0E

Number of Data Bytes
5+nCMD
W (0x57)

Value
Start addressDatan bytes

ChecksumCS

CMD
R (0x52)

Value
Start address

ChecksumCS

CMD
I (0x52)

Value
0xXXXXXXXX

ChecksumCS

Table 8. Run Command Packet
ID0
0x07

ID1
0x0E

Number of Data Bytes
5

Table 9. Information Command Packet
ID0
0x07

ID1
0x0E

Number of Data Bytes
5

Rev. B | Page 25 of 51

UG-1091

ADuCM3027/ADuCM3029 User Guide

Value Field (Data Byte 2 to Data Byte 5)
The value field contains a 32-bit address that includes h, u, m,and locations. The MSB is in the h location (Data Byte 2) andthe LSB is in the l location (Data Byte 5). As described
previously,•••

In a write command packet, the value field indicates thestart address in memory to which the data payload is
written.
In a run command packet, the value field indicates theaddress in SRAM where the SSL code begins.
In an information command packet, the value field has no
meaning.

Data Field (Data Byte 6 Data Byte 255)
User code is downloaded one byte at a time, and the data field
can contain a maximum of 250 bytes. The data is normally
stripped out of the Intel® HEX extended 16-byte record format,
reassembled by the host, and then sent in packet form using aseries of write command packets to the ADuCM3027/
ADuCM3029 processors.

Checksum Field (CS)The data packet checksum is written to the checksum field. This
twos complement checksum is calculated from the summationof the hexadecimal values that span the number of bytes field tothe end of the data field. Thus, the 8-bit LSB of the sum of all
the bytes in the packet from the number of data bytes field, up
to and including the checksum field, is 0.

Acknowledge of Command
The loader routine issues a no acknowledge command (0x07) asa negative response, or an acknowledge (0x06) as a positive
response to each data packet received.
The loader transmits a no acknowledge if it meets any offollowing conditions:•••

The loader receives an incorrect checksum.
A UART framing or break error occurs (this error may notreach the host if the UART link is invalid).
The SRAM code verification fails.

If any one of these conditions is met, it is required to reset thetarget and restart the firmware upgrade process. If none of these
conditions are met, an acknowledge command is transmitted.

READ PROTECTION KEY AND HASHING
The read protection key can be used to allow access to the device
during failure analysis. If the device is read protected and failure
analysis of the current flash memory content is necessary, enable
the SWD interface by sending the key corresponding to thehash stored in the user flash memory. It is recommended thatthe key be unique to the device and be based on the unique
identifier of the device (for example, serial number stored in
the information space).

A hash is stored in the user flash memory after the interrupt
vectors. This is the hash of a secret customer key. It is strongly
recommended that this key be unique to the device for security
reasons, and that the unlock key is valid for that one specificdevice. To maintain a unique key per device, there must be adevice identifier to associate which key belongs to a particulardevice. For simple key management, it is advised to make the
key a hash of a master secret and the device identifier. For
example,Read Protection Key = Hash (Master Secret || Unique
Device Identifier);
Key Hash = Hash (Read Protection Key)When the kernel is in UART loader mode, it can accept the readprotection key. Then, the boot loader performs a hash of theread protection key and compares it to the stored key hash.
Upon a successful match, the bootloader permits the downloaded
SSL code in the SRAM to be executed with all the permissions
enabled. If the key hash check fails, then the kernel checks the
ICWP key in the user flash memory. If ICWP is turned off by
the user by programming any value to Address 0x00000198
other than the hexadecimal equivalent of the NoWr ASCII
string, then the SSL is allowed to run after protecting the flash
against read and write accesses. In this case, the SSL must firstissue a mass erase of the user flash memory before attempting
to perform any access to the user flash memory space. If ICWP
is also enabled by the user, then the SSL is not granted permission
to run unless the key hash authentication passes.
The 128-bit read protection key is passed as a part of the SRAM
code. This key must be stored in big endian format in the
SRAM as a data payload starting at Address 0x20000180, andmust be oriented is a specific fashion in the memory for the
kernel to parse it correctly. Specifically, if the read protection
key is represented as ABCDEFGHIJKLMNOP, where each letter
represents one byte (with A being the first byte and P being thelast byte), the required arrangement of the bytes in memory is
shown in Table 10.
Table 10. Read Protection in SRAM
Address
0x20000180
0x20000184
0x20000188
0x2000018C

Byte 0D
H
L
P

Byte 1CGKO

Byte 2B
F
J
N

Byte 3A
E
I
M

For example, if the read protection key is 0x000102030405060708090A0B0C0D0E0F, then Table 11 shows how the memory must
be written.
Table 11. Example Read Protection Key in SRAM
Address
0x20000180
0x20000184
0x20000188
0x2000018C

Rev. B | Page 26 of 51

Byte 0
0x03
0x07
0x0B
0x0F

Byte 1
0x02
0x06
0x0A
0x0E

Byte 2
0x01
0x05
0x09
0x0D

Byte 3
0x00
0x04
0x08
0x0C

ADuCM3027/ADuCM3029 User Guide

UG-1091

The kernel computes the SHA-256 hash of this key, truncates it
to a 128-bit hash, and then compares it to the hash stored inPage 0 of the user flash memory at Address 0x00000180. The
user must store the 128-bit truncated hash of the key to the
flash memory using a similar pattern. The SHA-256 hash for theexample key shown in Table 11 is 0xBE45CB2605BF36BEBDE684841A28F0FD43C69850A3DCE5FEDBA69928EE3A8991,
which means the 128-bit truncated hash that must be stored
properly to the user flash memory space is 0x43C69850A3DCE5FEDBA69928EE3A8991, arranged as shown in Table 12.

The CRC32 of the key hash is calculated with a polynomial of
0x04C11DB7 and a seed value of 0xFFFFFFFF, and it is storedin LSB format in the flash memory space at Address 0x00000190.

MEMORY CONFIGURATION
Table 13 summarizes the different keys and parameters stored
in Page 0 of the user flash memory, the associated addresses,
and the values programmed to Page 0 when creating a projectwith the default startup file.

Table 12. Example Read Protection Key Hash in Flash Memory
Address
0x00000180
0x00000184
0x00000188
0x0000018C

Byte 0
0x50
0xFE
0x28
0x91

Byte 1
0x98
0xE5
0x99
0x89

Byte 2
0xC6
0xDC
0xA6
0x3A

Byte 3
0x00
0xA3
0xDB
0xEE

Table 13. Page 0 Memory Configuration
Content
Vector Table
Read Protection Key Hash

Address Range
Start Address End Address
0x0000_0000 0x0000_017F
0x0000_0180 0x0000_018F

Size(Bytes)384
16Section Name
.intvec
ReadProtection KeyHash

CRC of Read Protection
0x0000_0190
Key
Number of Pages the CRC 0x0000_0194
Computes
Checksum
0x0000_07FC

0x0000_0193

40x0000_0197

4

CRC_ReadProtection
KeyHashNumCRCPages

0x0000_07FF

4

ChecksumPage 0 User Memory

0x0000_07FC

1628

Page0_region

0x0000_01A0

Rev. B | Page 27 of 51

Default Content
Vector table
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xA79C3203
0
Checksum of 0 to 0x7FB (if enabled
in tools by the user)
User application

UG-1091

ADuCM3027/ADuCM3029 User Guide

HANDLING CRC IN THE IAR WORKBENCH
Calculate the CRC from part of the application image to beloaded into the first several pages of the flash memory. Store thepage number of the last page involved in the CRC calculation at
Address 0x194 as a 32-bit integer. For example, if only Page 0 is
involved in the CRC calculation, store the value of 0x00 at
Address 0x194. If the CRC is calculated for the first three pages,
the value must be 0x02.

The standard CRC calculation is CRC32 with a polynomial of
0x04C11DB7, stored in MSB first format, with an initial valueof 0xFFFFFFFF. The unit size is 32 bits, which means the tool
must read 32 bits at one time from the image when calculating
the CRC.

Checksum Tab
There is a Checksum tab under the Linker category in the IAR
tools, which can be used to generate the CRC of the user
application code. To store the correct CRC, the following
settings must be used (see Figure 45):









Check the Fill unused code memory box.
Set the End address: field to 0x7FB (this value changes
depending on the page number).
Check the Generate checksum box.
Select the 4 bytes option from the Checksum size: pulldown menu
Set the Alignment: field to 4 (which indicates 4 bytes).
Select the CRC32 option from the Algorithm: pull-downmenu.
Set the Initial value field to 0xFFFFFFFF and ensure that
the Use as input box is not checked.
Select the 32-bit option from the Checksum unit size:
pull-down menu.

15388-609

When the CRC is calculated, the last four bytes of the last page
included in the CRC calculation are excluded. These four bytes
are used for storing the CRC value itself. For example, if the last
page is Page 0, the CRC is calculated from Address 0x000 up to
and including Address 0x7FB. The tool stores the calculated
CRC value at Address 0x7FC as a 32-bit integer.
Figure 45. Checksum Settings

CrossCore Serial Flash Programmer
The CrossCore® Serial Flash Programmer (CCSFP) is a PCbased host utility, provided by Analog Devices, that can be used
to upgrade the user code over the UART port. CCSFP provides
a graphical user interface (GUI) to provide the following
options for the UART upgrade:







Target processor
UART PC port number
Baud rate
SSL hexadecimal file to be used for the upgrade
User application hexadecimal file to be upgraded
Key to authenticate the SSL

Figure 46 shows the GUI for the CCSFP. The user must provide
the SSL in the Second stage kernel field, which is first downloaded
into the SRAM of the processor and then is executed before theuser application in the File to download field is sent to flash,based on the authentication. The 128-bit key for the authentication
can be entered in the Key field.

Rev. B | Page 28 of 51

ADuCM3027/ADuCM3029 User Guide

UG-109115388-610

Figure 47 shows the SSL executing on the device, receiving theuser application, and writing it to the user flash memory space.

The Status window shows the state of the UART download
process, device related information, and the status of thecommands as returned by the kernel. As shown in Figure 46,
the Status window shows the device information sent by the
kernel, showing the product ID, serial number, and user code
status. After the SSL is downloaded, as indicated by the Download
completed message displayed in the Status window, the SSL isthen authenticated by the kernel and the actual user applicationis sent.

15388-611

Figure 46. CrossCore Serial Flash Programmer GUI

Figure 47. User Application Code Being Written by the SSL to User Flash
Memory via the CCSFP

Rev. B | Page 29 of 51

UG-1091

ADuCM3027/ADuCM3029 User Guide

CACHE MEMORY IN THE ADuCM3027/ADuCM3029

The cache in the ADuCM3027/ADuCM3029 consists of a lower
power cache controller for the instruction code (ICODE) and datacode (DCODE) accesses, a 4 kB instruction cache with 2-way
associativity, and a line size of 256 bits. The instruction cache hasa least recently used replacement policy. The cache writes to flash,and the core can issue writes to the flash only through the advanced
peripheral bus (APB) interface of the flash controller. If the code isplaced in the flash, enabling the cache helps the speed of execution.
For more information, see the Effects of Cache on the Speed of
Execution section. For details on current consumption, see theCurrent Consumption Comparison section.

FLASH CONTROLLER
The flash controller is coupled with a cache controller module,
which provides two advanced microcontroller bus architecture
high performance bus (AMBA AHB) ports; one port for reading
data (DCODE), the other for reading instructions (ICODE). The
flash controller supports simultaneous ICODE and DCODE readaccesses. DCODE has priority on contention.
The flash controller implements a prefetch mechanism to optimize
ICODE read performance. This mechanism provides optimal
performance when reading consecutive addresses on the ICODE
interface. Simultaneous reads are possible if the ICODE read
returns buffered data from prefetch.
READ PATHAHB ICODEAHB DCODECACHECONTROLLERCUSTOM
INTERFACE
FLASH
CONTROLLER

This section highlights the use of an on-board cache controller to
use a portion of the SRAM as instruction and data cache foruser code that otherwise executes from the flash memory.

APB

BLOCK DIAGRAMWRITE PATH

15388-702

The memory in the ADuCM3027/ADuCM3029 has up to 256 kBof embedded flash memory within the ECC, a 32 kB data static
random access memory (SRAM) with parity, and 32 kB user
configurable instruction and data SRAM with parity. Fourkilobytes of SRAM can be used as cache memory to reduce active
power consumption by reducing access to the flash memory.

Figure 49. Flash and Cache Controllers

FLASH

EFFECTS OF CACHE
Effects of Cache on the Speed of Execution
CACHE
SRAM

The flash memory and the SRAM memory have distinct power
and performance profiles.

15388-701

MICROPROCESSOR

Figure 48. Block Diagram

The ADuCM3027/ADuCM3029 cache architecture consists of adigital cache controller, a cache memory implemented as part ofthe system SRAM, a digital flash controller, and a flash memory.
The cache architecture decreases the average latency of instruction
and data accesses by utilizing the faster SRAM memory, anddecreases the frequency of accesses to the relatively higher power
flash memory.
When code is executed from the flash memory with the cacheenabled, frequently used instructions are automatically cached
in a dedicated region of the SRAM. In most applications, no further
user effort is required, though locking and control features areprovided.

The cache architecture copies a portion of user code into the SRAM
during execution where instruction and data read latency is lower.
For every instruction or data read that is satisfied by the cachememory, the overall system performance is improved.
When using the cache along with the flash, the increase in speed
depends on the type of code. Generally observing real code, fora loop code that fits into the cache completely, the speed of access is
15% to 20% faster than using only flash. For a linear code thatcannot fit into the cache, the speed of access can increase by 10%
to 15%.
Using the cache generally increases the speed of execution;
however, the extent of increase depends on the type of code used.
If the code has loops that fit completely into the cache, thespeed of execution increases significantly, because the majority
of instruction accesses is served from the faster SRAM memory.
If the code is generally linear and/or jumps between segments toolarge to fit into the cache, the speed of execution is not significantly
improved, because the majority of instruction accesses is served
from the slower flash memory.

Rev. B | Page 30 of 51

ADuCM3027/ADuCM3029 User Guide

UG-1091

Each cache miss results in a cache line fill consisting of four 64-bit
reads from the flash memory.

2.

The details of the FLCC0_CACHE_SETUP register are shown
this section.

*pREG_FLCC0_CACHE_SETUP |= (1 <<BITP_FLCC_CACHE_SETUP_ICEN);

Follow these instructions to enable or disable the cache:1.

To enable to the ICACHE, set the ICEN bit in the
FLCC0_CACHE_SETUP register. Clear this bit to disable
the ICACHE.

The instruction cache (ICACHE) is disabled by default. To
enable the ICACHE or toggle, the 0xF123F456 key must to
be written into the FLCC0_CACHE_KEY register.

*pREG_FLCC0_CACHE_KEY = 0xF123F456;

Cache Key Register
Address: 0x40018060, Reset: 0x00000000, Name: FLCC0_CACHE_KEY
15

14 13 12

11 10

9

8

7

6

5

4

3

2

1

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0[ 1 5 :0 ] VALUE[ 1 5 :0 ] ( W )Cache Ke y Re g iste r
3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 19 18 17 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0[ 3 1 :1 6 ] VALUE[ 3 1 :1 6 ] ( W )Cache Ke y Re g iste r

Table 14. Bit Descriptions for FLCC0_CACHE_KEY
Bits[31:0]

Bit Name
VALUE

Description
Cache Key Register. Enter 0xF123_F456 to set the UserKey. Returns 0x0 if read. The key is cleared
automatically after writing to FLCC_SETUP register.

Reset
0x0

Access
W

Reset
0x0
0x0

AccessR
R/W

Cache Setup Register
Address: 0x04001805C, Reset: 0x00000000, Name: FLCC0_CACHE_SETUP
Cache User key is required to enable a write to this location. Key will be cleared after a write to this register.
15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0[ 1 5 :1 ] RESERVED[ 0 ] ICEN ( R/W )I-Cache Enab le3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 19 18 17 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0[ 3 1 :1 6 ] RESERVED

Table 15. Bit Descriptions for FLCC0_CACHE_SETUP
Bits[31:1]
0

Bit Name
RESERVED
ICEN

Description
Reserved.
I-Cache Enable. If this bit set, then I-Cache is enabled for AHB accesses. If 0, then I-Cache isdisabled, and all AHB accesses will be via Flash memory.

Rev. B | Page 31 of 51

UG-1091

ADuCM3027/ADuCM3029 User Guide

Effects of Cache on Current
When it comes to current consumption, SRAM accesses consumeless current than flash accesses. Therefore, when the cache isenabled during the execution of code from the flash memory, thecurrent consumption is generally between that of code executing
directly from the flash or directly from the SRAM, unless the codeis such that every cache access is a miss. In this case, the current
is higher than executing from flash alone: cache line fills result inapproximately 2× more flash reads than occur if executing
directly from the flash. This read rate is 4× more, if not for the
prefetch buffer in the flash also performing a read, which must
miss too, if the cache misses.
CurrentSRAM ≤ CurrentCACHE
When using the cache, the current consumption is proportional tothe cache miss rate. This result is because of a scalar current
reduction for each cache hit, because the data or code access isserved from the lower current SRAM, rather than the higher
current flash memory. Therefore, code consisting of many smallloops is more greatly affected than linear code or code
consisting of segments too large to fit into the cache memory.
The cache usage can also be inferred from the current
consumption. If the current consumption using cache and flash
is nearer to the current consumption when using the SRAM, thecache hit rate must be high. If the current consumption using cacheand flash is nearer to the current consumption when using only
the flash, the cache hit rate must be low.

CURRENT CONSUMPTION COMPARISON
For a loop code (prime number code in this example), it is seen thatthe current consumption using the flash and cache (980 µA) isvery close to the current consumption in the SRAM (950 µA).
This result is because the code consists of many loops each smallenough to fit into the cache. Therefore, the accesses to the flash
are relatively rare and the code mostly executes from the relatively
low power cache. Accesses are minimal, therefore a minimal
increase in the current consumption in flash and cache comparedto the current consumption using the SRAM is seen.
For a linear code (ULPBench code in this example) it is seen thatthe current consumption using the flash and cache deviates awayfrom the current consumption seen using only the SRAM. This
result is because the ULPBench code is mostly linear and does
not fit well into the cache, and therefore there is still a similar
number of accesses into the flash memory as there are when
executing directly from the flash. The cache misses are too high;therefore, the current consumption deviates away to a greater
extent.

Table 16. Current Consumption Comparison
Type of CodeLoop code (prime number)
Linear code (ULPBench)

SRAM (μA)
950
911

Flash (μA)
1280
1493

Flash and Cache (μA)
980
1083

Rev. B | Page 32 of 51

Cache Misses (~12 sec of Execution)
24~800000

ADuCM3027/ADuCM3029 User Guide

UG-1091

DUAL RTC FEATURE IN THE ADuCM3027/ADuCM3029
In many applications, an RTC is used to time stamp sensor data.
The RTC must run even when the MCU is in a deep sleep mode. A
low power RTC is crucial to achieving a long battery life.
Notable features of ADuCM3027/ADuCM3029 RTCs include
the following:••

A dual RTC (RTC0 and RTC1). Both RTCs can be used as
wake-up timers.
SensorStrobe and input capture features.

This section provides guidelines for choosing between RTC0
and RTC1, depending on the power modes and functionality
required.

•••

Scenario 2. The device switches between the active andhibernate power modes, and the application does not
require high time accuracy. Either RTC0 or RTC1 can beused in this scenario, but using RTC1 is recommended
from a power point of view because RTC1 uses less power.
Scenario 3. The device switches between the active andshutdown power modes. Only RTC0 can be used in this
scenario.
Scenario 4. The device switches between the active, shutdown,
and hibernate power modes. Only RTC0 can be used, in
this scenario because RTC1 is not active in shutdown mode.

The ADuCM3027/ADuCM3029 has two RTCs, RTC0 and
RTC1 (also named FLEX_RTC). Table 17 shows differences
between RTC0 and RTC1.

A basic program comprised of an RTC alert to wake up the
ADuCM3027/ADuCM3029 microcontroller from low powermode and to toggle an LED was used for measuring current in
the sleep power mode (hibernate or shutdown mode,
depending on the scenario).

POWER CONSIDERATIONSCONCLUSION

Table 18 shows current consumption when using RTC0 and
RTC1 in different use cases. Four scenarios are considered asfollows:

Use RTC0 in applications that use shutdown mode and require
an RTC.

COMPARISON OF THE RTC FEATURES•

Scenario 1. The device switches between the active andhibernate power modes, and the application requires hightime accuracy. Either RTC0 or RTC1 can be used in this
scenario, but using RTC1 is recommended from a power
point of view because RTC1 uses less power.

RTC1 is a feature rich RTC that enables ultra low power
consumption in applications that only use the hibernate mode,in addition to active or Flexi modes. Typical applications forwhich RTC1 is suited are applications where the ADuCM3027/
ADuCM3029 microcontroller sends output pulses to externalsensors via a general-purpose input/output. Note that the
SensorStrobe mechanism is only available in RTC1.

Table 17. Summary of the Differences Between RTC0 and RTC1
FeatureResolution of the Time
Base (Prescaling)
Wake-Up Timer
Number of Alarms
Power Domain
SensorStrobe and Input
Capture Features
Source Clock

RTC0
RTC0 counts time at 1 Hz in units ofseconds only
The wake-up time is specified in unitsof seconds
1 alarm only, which uses an absolute,
nonrepeating alarm timePowered off VBAT domain and isalways on; RTC0 can function in all
power modes
Not supported
Low frequency crystal (LFXTAL)

RTC1
RTC1 can prescale the clock by any power of 2 from 1 to 15,
counting time in units of any of these 15 possible prescale settings
The wake-up time can be specified in units of any power of 2
multiple of 30.7 µs up to 1 second
2 alarms: one absolute alarm time and one periodic alarm, repeating
every 60 prescaled time units
Powered off 1.2 V (VREG) domain; RTC1 can function in all power
modes, except shutdown mode
Supports four input capture channels and one SensorStrobe
channel; refer to AN-1427 for further information on these features
Depending on the low frequency multiplexer (LFMUX) configuration,
the RTC is clocked by LFXTAL or the low frequency oscillator (LFOSC)

Table 18. Comparison of Current Consumption in Different Use Case Scenarios
Scenario Number
1
2
3
4
1

Use Case 1
Active to hibernate
Active to hibernate
Active to shutdown
Active to hibernate

Recommended RTC
RTC1 (LFXTAL)
RTC1 (LFOSC)
RTC0 (LFXTAL)
RTC0 (LFXTAL)The device switches between the modes listed in this column.

Rev. B | Page 33 of 51

Sleep Mode Current (nA)
830
750
330
830

UG-1091

ADuCM3027/ADuCM3029 User Guide

BENEFITS OF THE ADuCM3027/ADuCM3029 DC-TO-DC CONVERTERThis section discusses the advantages and disadvantages ofcharge pump converters vs. inductor converters, the latter ofwhich are frequently used. This section demonstrates why thisarchitecture is used on the ADuCM3027/ADuCM3029
microcontroller, accounting for advantages in many aspects
such as price, area, simplicity, and ease of use.
Direct current-to-direct current (dc-to-dc) converters are key
blocks in designs where it is required to manage different
voltage domains, such as in the ADuCM3027/ADuCM3029
microcontrollers.
Methods of dc-to-dc conversion are briefly explained in thissection to provide users with context. A charge pump converter
is chosen for use in the ADuCM3027/ADuCM3029 because of
its advantages when compared to other configurations.
The purpose of this section is to help users understand why thecapacitive dc-to-dc converter is a better alternative to inductive
conversion solutions in the ultra low power applications forwhich the ADuCM3027/ADuCM3029 is intended.
This section provides details and examples to prove the qualities
and benefits of this charge pump converter solution. Figure 50
shows the buck enabled design present in the ADuCM3027/
ADuCM3029 microcontrollers. The ADuCM3027/ADuCM3029
uses a charge pump converter, which is not used in the majorityof microcontrollers with similar characteristics available on themarket; these other microcontrollers tend to use traditional
inductor converter architectures.
VDCDC_CAP1P

VBAT

VDCDC_CAP1N 0.1µF
BUCK(ENABLED)VDCDC_OUT

DC-TO-DC BASICS
The ADuCM3027/ADuCM3029 processors are intended for
ultra low power applications. Power efficiency is one of the key
considerations in such applications; therefore, using a dc-to-dc
converter is crucial in designs where power must be used as
efficiently as possible.
There are different ways to perform dc-to-dc voltage conversions;such conversions involve stepping up or stepping down the dc
voltage used to power the device.

DC-to-DC Conversion Methods
The most extensively used methods for regulating the different
power domains of a system are switching conversion and linear
regulation. Select the method that best meets the requirementsof the design or application.

Linear Regulators
Linear regulators consist of a network of resistive dividers thatdissipate excess voltage. Linear regulators are widely used due tothe ease of use and implementation, as well as the low cost.
In ultra low power applications, linear regulators are less efficientwhen compared to switching converters. In a linear regulator,
the output current is approximately the same as the input current,
and its operating principle is to dissipate any leftover voltage.
Switching converters perform the same action more efficiently.
The ADP165/ADP166 devices are very low quiescent current,
low dropout (LDO), linear regulators. The ground current
represents the difference between input and output currents.
Figure 51 represents the ADP165/ADP166 ground current vs.
the load current (ILOAD), showing the small difference incurrents in a linear regulator.

0.47µF100

VDCDC_CAP2PGROUND CURRENT (µA)

VDCDC_CAP2N 0.1µF

VLDO_OUT
LDO

10

1

Figure 50. ADuCM3027/ADuCM3029 Buck Enabled Design

0.1
0.001

0.01

0.1

1

10

100

1000

ILOAD (mA)

Figure 51. ADP165/ADP166 Ground Current vs. Load Current (ILOAD)

Rev. B | Page 34 of 51

15388-202

15388-201

0.47µF

ADuCM3027/ADuCM3029 User Guide

UG-1091

Efficiency =Energy Output
Energy Input
I OUT × VOUT × t
I IN × VIN × t

Linear Regulator Efficiency =× 100%(1)× 100%(2)

1×1× t1× 3 × t

× 100% = 33%(3)

As observed in these two graphs, charge pump converters areless efficient than inductor converters due to the output shapefor output load currents. In contrast, charge pump converters
are an appropriate solution to low load current applications.
100

Using a switching converter instead of a linear regulator, theinput current is 1/3 µA, leading to 100 % efficiency in an ideal
performance, as shown in Equation 4.
1/ 3 × 3 × t

× 100% = 100%

(4)

In general, switching converters are more efficient than linear
regulators. Moreover, losses in efficiency produce an increase intemperature that is much higher in linear regulators because
their dissipation must be larger to achieve the same conversion.
Additionally, linear regulators require more investment inmanagement to reduce temperature.

80
70
EFFICIENCY (%)

Efficiency =1×1× t

VIN = 5.5V
VIN = 4.2V
VIN = 3.6V
VIN = 2.3V

90

60
50
40
30
20
10
0
0.001

Traditionally, Analog Devices used linear regulators in designs
that precede the ADuCM3027/ADuCM3029 microcontrollers
because of their simplicity and low cost. Currently, it iscommon to locate linear regulators at the output of charge
pump converters to stabilize their rippled output.

0.01

0.1

Figure 52. ADP2503/ADP2504 Efficiency vs. Output Current (IOUT)
120
V+ = +6.5V

V+ = +5.5V

100

V+ = +4.5V

EFFICIENCY (%)

Switching Converters
Switching converters use switches and components with low
losses, such as inductors or capacitors, to regulate voltage.
Typically, these components are charged and discharged byswitching transistors. This section discusses two types ofswitching converters: charge pump converters and inductor
converters.

1

IOUT (A)80

V+ = +3.5V

60
V+ = +1.5V

V+ = +2.5V

40

20

Inductor converters are among the most commonly usedconverters in microcontroller designs to achieve ultra low
power with high efficiency. This efficiency and the wide gain
range make this architecture desirable.
The charge pump, or switched capacitor converter, is analternative to inductive converters. The charge pump process iscarried out by connecting and disconnecting switches to charge
and discharge capacitors. This process is achieved without
inductors, which saves space and costs.

0
0

20

40

60

80

100

LOAD CURRENT (mA)

15388-204

Efficiency =The ADP2503/ADP2504 are high efficiency inductor convertersthat can operate at input voltages greater than, less than, or equal to
the regulated output voltage. The ADM660/ADM8660 are charge
pump voltage converters that can achieve efficiency greaterthan 90% with low output currents (up to 50 mA). Figure 52 andFigure 53 show the efficiency for a given input voltage and output
currents for the ADP2503/ADP2504 devices andADM660/ADM8660 devices, respectively.

15388-203

To analyze the power efficiency of the solution, consider atypical application based on linear regulators. For an input
voltage of 3 V, an output voltage of 1 V, and an output current of
1 µA, the input current is approximately 1 µA. This scenario
results in 33% efficiency (see Equation 3).

Figure 53. ADM660/ADM8660 Efficiency vs. Load Current

The ADuCM3027/ADuCM3029 microcontrollers have a linear
regulator at the charge pump converter output to adjust andstabilize the supply of the digital core and memories. Furthermore,
the devices have the ability to bypass the charge pump converter
to only use the linear regulator to reduce and adjust the voltage.
This feature allows the user to decide between using a traditional
solution or to improve efficiency and increase power savings using
the charge pump block at the expense of two extra 0.1 µF
capacitors.

Rev. B | Page 35 of 51

UG-1091

ADuCM3027/ADuCM3029 User Guide

In general, inductor converters do not require a linear regulator
at their output; this is inconvenient in charge pump converter
designs. However, some microcontrollers available on themarket that use an inductor converter solution include a linear
regulator in the inductor converter. Despite this disadvantage,
charge pump converters offer a breadth of advantages to beconsidered (as follows):







Area
Thickness
Price
Design simplicity
Ease of use
Electromagnetic interference (EMI)As expected, the area in a charge pump converter is smaller
because this type of converter employs fewer and smaller
components than inductive solutions. Inductor converters use
more than the double the area of charge pump converters.
In inductor converters solutions, the thickness is determined by
the inductors, because inductors are thicker than capacitors—
0.55 mm vs. 0.3 mm.
Inductors are higher than capacitors along the three dimensions;
therefore, inductors determine and increase the area of the design.
Regarding this approach, it is possible to look throughmicroscopes to see this evident difference in dimensions.
Figure 54 and Figure 55 compare the dimensions of a 2.2 μH
inductor and a 0.1 μF capacitor.

The following section discusses each advantage of charge pumpconverters when compared to inductor converters.

CAPACITORS vs. INDUCTOR CONVERTERS
Area

This section compares the components required for using the
ADuCM3027/ADuCM3029 charge pump converter against
inductor converters used in other similar solutions available
on the ultra low power microcontroller market. The components
required in these architectures are included in their respective
data sheets.

15388-205

Charge pump converters do not require inductors to accomplish
dc-to-dc voltage conversion, whereas inductor converters
require inductors, capacitors, and other components, such as
resistors, to fulfill this task. This fact allows the design ofsmaller printed circuit boards (PCBs), saving area and cost.

Figure 54. Length Comparison of a 0.1 µF Capacitor (Bottom) vs. a 2.2 µH
Inductor (Top)The two bill of materials shown in Table 19 and Table 20
demonstrate that charge pump converter covers less area than
the inductive converters. The dimensions of capacitors(length × width × thickness) are 0.6 mm × 0.3 mm × 0.3 mm;
the dimensions for inductors are 1 mm × 0.5 mm × 0.55 mm.
Both capacitors and inductors are in 0603 packages.
Table 19. Area of Charge Pump Converter Components in
the ADuCM3027/ADuCM3029
Value (μF)
0.1
0.47

Quantity
2
1

Area (mm2)
0.36
0.18
0.52

Table 20. Area of Inductor Converters Components
Component
Capacitor
Inductor
Total

Value
1 μF
2.2 μH

Quantity
2215388-206

Component
Capacitor
Capacitor
Total

Figure 55. Width Comparison of a 0.1 µF Capacitor (Right) vs. a 2.2 µH
Inductor (Left)

Area (mm2)
0.36
1
1.36

Rev. B | Page 36 of 51

ADuCM3027/ADuCM3029 User Guide

UG-1091

Price
Issues to consider when working with inductor converters
include the large number of components and the cost of thesecomponents. The capacitance of capacitors is larger and theprice of inductors is much greater than the price of capacitors.
Table 21 and Table 22 show the price of the ADuCM3027/
ADuCM3029 solution and an inductor based solution,
respectively.
Table 21. Price of Charge Pump Converter Components for
the ADuCM3027/ADuCM3029
Component
Capacitor
Capacitor
Total

Value (µF)
0.1
0.47

Quantity
2
1

Price ($)
0.10460.459
0.5636Value
1 µF
2.2 µH

Quantity2
2

By setting the appropriate configuration, charge pumpconverters are able to change their gain according to the
input/output voltage ratio (VIN/VOUT). This process improves
efficiency to achieve the same performance available withinductor converters.
Inductor based solutions use pulse-width modulation (PWM)
to adjust the duty cycle to achieve suitable gain. Through thisregulation, high efficiency is obtained, which decreases when
the load lowers. Noise effects also appear during PWM, which
results in increased cost for more expensive inductors.
If integration is required in inductor converter designs,
embedded inductors require high frequency switching to work.
High frequency switching results in power dissipation andefficiency losses, which is an undesirable outcome.

Table 22. Price of Inductor Converters Components
Component
Capacitor
Inductor
Total

which is easily achieved by applying integration in an ultra low
power application. The lower the required load, the better
integration and efficiency are in charge pump converters.

Price ($)
1.068
0.538
1.606

Electromagnetic Interference (EMI)

When considering both lists of materials, note that thedifference in the price of each component is around $1. This
amount, though seemingly small, produces a notable impact
when multiplying the cost across many products; the differencein price is incremented because, in inductor designs, morecomponents are present and the engaged area is wider. Allowing
smaller PCB designs contributes to a reduction in cost.
Note that prices are based on the cheapest and smallest
components available; this lack of inductor quality may lead toincreased power dissipation and a degradation in efficiency.
Therefore, the use of cheap inductors prevents the designer
from taking advantage of inductor-based performance. In
contrast, avoiding this constraint implies another increase in
price for inductor converters.
There are clear advantages in area and price when comparing
charge pump converters and conventional inductor-based
solutions.

Efficiency
As with the opportunity to reduce area, there also exists anopportunity to improve integration employing embedded
components. This is a suitable scenario for charge pumpconverters to enhance efficiency, rather than inductors.
It is thought that charge pump converters are less efficient than
inductor converters, which can be true when input voltages andloads change.
In charge pump converters, load changes are not a problem inultra low power applications where low loads are managed.
Optimal efficiency is achieved with low load currents. Charge
pump converters perform proper efficiencies with low loads,

In charge pump converters, electromagnetic emissions are not
relevant. Such radiation is not a cause for concern, unlike
inductor magnetic radiation.
EMI becomes inconvenient when using inductors, even more so
if they are switched inductors with behavior similar to an emitting
antenna. Unpredictable interferences can occur in other parts ofthe design or the board. Furthermore, it becomes a sensitive
problem if radio frequency tasks are being performed.
Inductor converters replace PWM with pulse frequency
modulation (PFM) when low loads are required to improve
efficiency. If PWM is performed, switching noise and output
voltage ripple are easily improved by a simple filter at the output
voltage of the converter. However, the PFM method has a variablefrequency band and may produce the resonance frequency of
the filter. In addition, this wide frequency spectrum also resultsin high EMI.

CONCLUSIONS
Inductor converters are not suitable solutions in many senses
when considering ultra low power applications. Inductor
converters lose efficiency as load decreases, their area is larger,
which can lead to expensive components and greater costs,
inductor radiation poses a problem, EMI is more likely to occur
at low loads, and so on.
Table 23 summarizes the advantages and disadvantages of three
types of dc-to-dc converters. Evaluate the specific type of
converter that best suits the application in question.
In conclusion, charge pump converters are the best solution in
ultra low power applications. While other solutions worsen withlow loads, charge pump converters are even better than in othersituations.

Rev. B | Page 37 of 51

UG-1091

ADuCM3027/ADuCM3029 User Guide

Table 23. Comparison of Different Types of DC-to-DC Converters
Type of Converter
LDO

Charge Pump

Inductive

Advantages
SimpleLow cost
No inductor
No EMI
SimpleLow cost
No inductor
Cheaper than inductive
Low loads
Small area
More efficient than LDO
Low EMI
Most efficient (not in low loads)

Disadvantages
Less efficient than charge pumps and inductives

Less efficient than inductive at high loads
EMI (less than inductive)

EMI
Area
Cost
Poor efficiency at low loads
Complex design

Rev. B | Page 38 of 51

ADuCM3027/ADuCM3029 User Guide

UG-1091

UART SOFTWARE FLOW CONTROL
Tx

Rx

Rx

GROUND

DEVICE B

GROUND

15388-301

DEVICE A

Tx

Figure 56. Software Flow Control Block Diagram

UART flow control is a method for slow and fast devices tocommunicate with each other over the UART without the risk oflosing data. Consider the case where two units are communicatingover the UART. A transmitter, Tx, is sending a long stream ofbytes to a receiver, Rx. Rx is a slower device than Tx and atsome point Rx cannot keep up with the speed of the data beingtransmitted. Therefore, Rx must either process some of the dataor empty buffers before it can continue to receive data. Rx must
instruct Tx to stop transmitting until Rx is ready to accept data.
This method of waiting to transmit is known as flow control.
Flow control requires extra signaling to inform the transmitterto stop (pause) or start (resume) the transmission. The traditional
hardware flow control in UART requires two extra signals: request
to send (RTS) and clear to send (CTS). The logic level on thesesignals defines whether the transmitter continues to send dataor must stop sending data. With software flow control, special
characters are sent over the normal data lines to start or stop thetransmission, thus using fewer signals.
This section describes the UART software flow control
mechanism using the ADuCM3027/ADuCM3029.

UART FLOW CONTROL
Hardware Flow Control
The hardware flow control mechanism uses out of bandsignaling to control the flow of data. In addition to the data
signals, two extra signals—RTS and CTS—are required. Theseflow control signals are cross coupled between the two devices,with RTS on one device being connected to CTS on the remotedevice, and vice versa.

Each device uses the RTS to signal if it is ready to accept new
data, and reads the CTS signal to check if it is allowed to senddata to the other device. As long as a device is ready to accept
more data, the RTS signal is kept asserted. The device deasserts
the RTS signal when its receive buffer is full.
The other device is required to respect the flow control signal
and pause the transmission until the RTS signal is asserted again.

DEVICE A

Tx

Tx

Rx

Rx

CTS

CTS

RTS

RTS

GROUND

DEVICE B

GROUND

15388-302

Flow control is the process of managing the rate of datatransmission between two nodes to prevent a fast transmitterfrom overwhelming a slow receiver. Flow control provides amechanism for the receiver to control the transmission speed, sothat the receiving node is not overwhelmed with data from thetransmitting node.

Figure 57. Hardware Flow Control

The flow control is bidirectional, meaning that both devices canrequest a halt in transmission. If one of the devices never requests a
stop in transmission (for example, if the device is fast enough toalways receive data), the CTS signal on the other device can betied to the asserted logic level. Thus, the RTS pin on the fastdevice can become free to perform other functions.

Software Flow Control Using the XON and XOFF Signals
Software flow control does not require extra out of band signals.
Only three signals are required: Rx, Tx, and ground. Software
flow control is achieved by using special control flow characters.
The control flow characters are sent over the normal Tx and Rx
lines. These characters are typically ASCII codes, specifically
XON (0x11) and XOFF (0x13), for resuming and halting thetransfer, respectively.
If Device A sends XOFF to Device B, Device B halts transmission
to Device A until Device B receives an XON character from
Device A. If the data contains the XON and/or XOFF character,
insert an escape character before the XON and/or XOFF character.
The escape character used in this case is \ with ASCII Value 92(0x5C). When this escape character is encountered, the character
following it is considered to be a data character, not a flow
control signal. If the data itself contains an escape character,ensure that another escape character precedes the present
escape character that is present in the data.

Rev. B | Page 39 of 51

UG-1091

ADuCM3027/ADuCM3029 User Guide

Sequence Diagram

SYSTEM DESCRIPTION

Consider data communication between two devices—the
ADuCM3027/ADuCM3029 MCU and a peer—where the MCU
is transmitting and the peer is receiving. If the peer is slower
than the MCU, the data transmission overwhelms the peer.
At this stage, the peer sends an XOFF character to pause thetransmission until the peer is able to process the data again. The
MCU waits to receive a XON character from the peer. When thepeer is ready to receive the data, it sends an XON character,
instructing the MCU to resume transmission. In this way, using
software flow control ensures that no data is lost. Figure 58
shows the sequence diagram of this described communication.

Demonstration of UART software flow control using the
ADuCM3027/ADuCM3029 is performed using the EV-COGAD3029 evaluation kit. A PC with a terminal program running(such as HyperTerminal) is connected to the EV-COG-AD3029
UART port.

ADuCM3027/
ADuCM3029

PC RUNNINGTERMINAL PROGRAM
15388-304

UART

Figure 59. Connection Diagram

PEER

Handling Flow Control Signals from a Peer Device

DATA

The ADuCM3027/ADuCM3029 BSP contains drivers for all
the peripherals, including UART. The software flow control
mechanism is implemented in addition to the available UART
driver functions.

COLLECT DATATRANSMITTING
DATA

EV-COG-AD3029

DATA
COLLECT DATA

The adi_uart_Write_fc function sends the XOFF and XON
characters, and the UART interrupt service routine processes
the XON and XOFF signals received from the PC.

DATA

COLLECT DATA

adi_uart_Write_fc Function
OVERWHELMEDBY DATA

When a write is issued using the adi_uart_Write_fc function,
the global RECV_XON flag is checked to be aware whether thepeer is ready to accept data. If the RECV_XON flag is false, itmeans that an XOFF signal is received, the peer cannot accept
data, and, therefore, a failure is returned. If the RECV_XON flag istrue, the peer is ready to accept data. The data is transmitted
and a success is returned.

SEND XOFF
XOFF

PAUSE
TRANSMISSIONREADY TOACCEPT DATAWAIT FORXON

SEND XONXON

RESUME
TRANSMISSIONDATACOLLECT DATA

15388-303

TRANSMITTINGDATA

Figure 58. Software Flow Control Sequence Diagram

Rev. B | Page 40 of 51

ADuCM3027/ADuCM3029 User Guide

UG-1091

Example Code for Flow Control
The following code is used to transmit data using flow control:
ADI_UART_RESULT adi_uart_Write_fc(
ADI_UART_HANDLE const hDevice, void *const pBuffer, uint32_t nBufSize){/* Return code */ADI_UART_RESULT eResult;/* If there is no XOFF received, safe to transmit data */if(RECV_XON == true)eResult = adi_uart_Write (hDevice, pBuffer, nBufSize);/* If XOFF is received, return fail */else
eResult = ADI_UART_FAILED;
return eResult;}Rev. B | Page 41 of 51

UG-1091

ADuCM3027/ADuCM3029 User Guide

Figure 60 shows the design of adi_uart_Write_fc function.
When a write is issued, the RECV_XON flag is checked and, if
the flag is true, the write is processed. If the flag is not true, it
returns a failure. The RECV_XON == TRUE block in Figure 60
indicates the checking of the RECV_XON flag.

Data Processing Code Example
The following code processes the data that is received.
switch (readVal){/* If an escape is received */case FCESCAPE:WRITEREQUEST/* If escape already received,
consider it as data */if(bEscFlag == true)bEscFlag = false;
else

RECV_XON == TRUE

bEscFlag = true;NO

break;/* If an XON is received */case XON:

YES/* If escape received before,
consider it as data */if(bEscFlag == true)
TRANSMITDATA

RETURNFAILUREbEscFlag = false;/* Valid control signal,
update send flag */else
RECV_XON = true;break;

15388-305

RETURN
SUCCESS/* If an XOFF is received */case XOFF:

Figure 60. Flowchart of the adi_uart_Write_fc Function/* If escape received before,

Processing Control Signals from the Peer Through an
Interrupt Service Routine (ISR)

consider it as data */if(bEscFlag == true)

The data received through the UART is monitored to check if it
is a control signal or data. If the data received is an escapecharacter, an escape flag (bEscFlag) is asserted so that the data
following it is to be considered data and not as a control signal.
If an XOFF or XON signal is received, it is checked to confirm if
the escape flag is set. If the escape flag is not set, a global flag
(RECV_XON) is updated.
When receiving an XOFF signal without the escape flag set, theRECV_XON flag is deasserted, meaning that it received an
XOFF signal and data transmission must not happen. In thesame way, the RECV_XON flag is asserted when receiving an
XON signal without the escape flag set.

bEscFlag = false;/* Valid control signal,
update send flag */else
RECV_XON = false;
break;
default:
break;}

Rev. B | Page 42 of 51

ADuCM3027/ADuCM3029 User Guide

UG-1091

Figure 61 shows the design of the algorithm that handles andprocesses the flow control signals from the peer. The data
received is first checked for an escape character; if it is an escapecharacter, the data following it is considered to be data and not

a control signal. The received data is then checked for XON andXOFF control signals and the global RECV_XON flag is updated
accordingly. The gray blocks in Figure 61 indicate the updatingof the RECV_XON flag.

READ
REQUEST

Readval =read_data_from_uart_rx()

readVal ==ESC_CHARYES

bEscFlag = TRUE

NO

YES

XOFF

bEscFlag== TRUE

NO

YES

NO

RETURN
readValreadVal ==XON

RECV_XON=FALSEYES

bEscFlag== TRUENO

YES

RETURN
Readval

RETURN
readVal

RETURNNO

RECV_XON= TRUE

RETURN

Figure 61. Flowchart of the Control Signals in the ISR Being Processed

Rev. B | Page 43 of 51

15388-306

readVal ==UG-1091

ADuCM3027/ADuCM3029 User Guide

DATA CAPTURE

Controlling the Received Data Flow

In the setup for data capture, the MCU is connected to a PC andis communicating with a terminal program running on the PC.
A UART sniffer, such as the serial port monitor, monitors thedata communication occurring at a Baud rate of 9600. The data
capture is performed using the sniffer, as discussed in this section.

A simple procedure is implemented when controlling thereceived data flow to send the control signals from the
ADuCM3027/ADuCM3029 MCU. In this case, the MCU isslower compared to the peer. The mechanism to send the control
signals from the MCU is application specific and the user canwrite their own algorithm for sending the control signals.

Handling Flow Control Characters in the ADuCM3027/
ADuCM3029
Figure 62 shows an example of handling the flow control signals
from the peer.

As shown in Figure 63, an XOFF signal is sent after every fivetransmissions sent from the MCU. An XON signal is sent after ashort interval of time. This implementation is an example and is
described only for demonstration purposes. The user can develop
their own mechanism to handle the data and to send XON andXOFF signals.

DATA SENTCONTINUOUSLYBY MCUDATA SENTCONTINUOUSLYBY MCUXOFF RECEIVEDXOFF SENTAFTER EVERY
5 TRANSMITSNO TRANSMISSIONBY MCU UNTIL
ANXON IS RECEIVEDXON RECEIVED
TRANSMISSIONCONTINUES AFTERXON IS RECEIVEDNO DATA CAN BE
RECEIVED

ESCAPERECEIVEDXON SENT AFTER A
SMALL WAIT PERIODXOFF RECEIVED
BUT TRANSMISSIONIS NOT STOPPEDDATATRANSMISSIONCONTINUES

Figure 63. ADuCM3027/ADuCM3029 Transmitting Control Signals
15388-307

XON RECEIVED
BUT TRANSMISSIONIS UNALTERED

15388-308

ESCAPERECEIVED

Figure 62. Data Capture Using a Sniffer Program

Rev. B | Page 44 of 51

ADuCM3027/ADuCM3029 User Guide

UG-1091

SPI FLOW CONTROL METHODS
CS

CS

SCK

SCK

MOSI

MOSI

SPI
SLAVE

MISO/RDY

15388-401

SPI
MASTERMISO/RDY

Figure 64. SPI Signals

ADuCM3027/
ADuCM3029

SERIAL FLASH
W25Q32
15388-402

SPI

Figure 65. Application Block Diagram

The SPI is an industry-standard, synchronous serial link thatallows full duplex operation to other SPI-compatible devices.

provide the clock, which is typically initiated when the data
must be sent on the MOSI line.

The ADuCM3027/ADuCM3029 SPI has enhanced modes ofoperation that provide the user the flexibility of half duplex
operation and flow control options. The SPI data transfers use
DMA transactions, allowing the ADuCM3027/ADuCM3029
core to be in sleep mode. Along with multibyte transfers in half
duplex mode, this reduction in power consumption offers
power savings that are essential for battery-powered designs,
such as in wireless sensor networks.

Most SPI slaves mandate a protocol that must be used by themater for successful communication. The protocol can be as
simple as a command, followed by an address (optional), anddata (optional).

Some notable features of the ADuCM3027/ADuCM3029 SPI
are as follows:








Continuous transfer mode.
Read command mode for half duplex operation.
Flow control.
CS software override.
Support for 3-pin SPI master or slave mode.
LSB first transfer option.
Interrupt mode. An interrupt is available after 1, 2, 3, 4, 5,
6, 7, or 8 bytes.

This section provides an understanding of the read commandmode and flow control methods. These methods help lower thesystem power consumption when used with SPI slaves such as
sensors, serial flash devices, ADCs, and RF transceivers.

SPI READ COMMAND MODE
Standard SPI masters communicate with slaves using the serial
clock (SCK), master out, slave in (MOSI), master in, slave out(MISO), and chip select (CS) lines. The SCK, MOSI, and MISO
signals can be shared by slaves, whereas each slave has a unique
CS line. During an SPI transfer, data is simultaneously transmitted
and received. The serial clock line synchronizes shifting andsampling of the information on the two serial data lines.
SPI transfers are typically full duplex. The transfers are controlled
by the master. To receive data from the slave, the master must

For example, a write command is unidirectional and typicallyinvolves the master transmitting the command, address (optional),
and the data to be written to the address in the slave.
A read command requires the master to transmit the command
and address (optional), and then reads the data associated withthe address from the slave. If the data is multibyte, then the software on the master must write dummy data on the MOSI, whichkeeps the clock alive, to successfully read all the data bytes.
However, some SPI slaves require that, after the transmission of
the read command byte on the MOSI, the data be read on
MISO in a single CS transaction. An example of thisrequirement is shown in Figure 66.
The ADuCM3027/ADuCM3029 provides the read commandmode to support such half duplex operations. The readcommand mode helps reduce the burden on the software andthereby the core execution cycles. In this mode, the user mustspecify the number of bytes to be transmitted and the numberof bytes to be received in a transaction. It is also possible tospecify if the data on the MISO must be ignored when thetransmission on MOSI is in progress.
Using the read command mode allows the user to transmit asingle byte and receive a set of data bytes from the slave, which
is useful when the slave is a sensor or ADC providing a set ofmeasured and processed data.
An application scenario is described in the System Description
section, wherein the ADuCM3027/ADuCM3029 is the SPI
master and a serial flash, W25Q32, is the SPI slave, as shown in
Figure 65. Read command mode is helpful when pages of data
must be read from the flash memory.

Rev. B | Page 45 of 51

UG-1091

ADuCM3027/ADuCM3029 User Guide

CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

1

0

16

17

18

7

6

5

19

20

21

22

23

2

1

0

SCK

INSTRUCTION
MOSI

0

0

0

0

1

8-BIT ADDRESS
0

1

1

7

6

5

4

3

2

4

3

15388-403

DATA OUT
MISO

Figure 66. Read Command Mode

System Description



Firmware—power-on self test application from the
ADuCM3027/ADuCM3029 BSP for IAR.
Hardware—EV-COG-AD3029 board.

An oscilloscope is connected to the SPI lines to capture thesignals. The oscilloscope plots, Figure 67 to Figure 71, show the
SPI transfer between the ADuCM3027/ADuCM3029 as the SPI
master, and a serial flash W25Q32 as the SPI slave.
It is up to the user application to decide the transactions inwhich to use the read command mode.

1

CS

2

MOSI

3

MISO

4

SCK

CH1 2.00VCH3 2.00V

Without Read Command ModeIn the reference application, the erase process of a 4 kB sector of
the flash memory does not use read command mode. The absenceof this mode can be observed from the transfer of the erasecommand and the address in individual chip select frames in
Figure 67 and Figure 68.

2

M40.0µs
T
16µs

CH4

0V

Figure 68. Sector Erase—Single CS Frame CaptureWith Read Command Mode
Figure 69 shows one page read from the external flash. The sizeof one page of the flash is 256 bytes. This read sequence uses theread command mode and the entire read of the page happens in
one CS transaction.

CS
1

CS

2

MOSI

3

MISO

MOSI

3

MISO

4

SCK

CH1 2.00VCH3 2.00V

CH2 2.00V Ω
CH4 2.00V Ω

M2.00ms
T
16µs

CH4

0V

4

15388-404

1

CH2 2.00V
CH4 2.00V

SCK
CH1 2.00VCH3 2.00V

Figure 67. Sector Erase

Figure 68 shows a single CS frame capture in the entire erase
sequence. The CS line is toggled for the transfer of every
command byte.

CH2 2.00V
CH4 2.00V

M4.00ms
T
16µs

CH4

0V

15388-406



15388-405

To showcase the read command mode, the following setup is used:

Figure 69. Page Read Sequence

Figure 70 shows the start of the page read sequence where the
ADuCM3027/ADuCM3029 transfers the command and address
bytes. This transfer is followed by the page data from the serial
flash memory.

Rev. B | Page 46 of 51

ADuCM3027/ADuCM3029 User Guide

The flow control modes are described in the following sections
in more detail. The mode field in the SPI flow control register(SPI_FLOW_CTL) configures the flow control mode to any oneof the three modes.

CS

1

2

UG-1091

MOSI

Note that flow control mechanisms can be used only when the
ADuCM3027/ADuCM3029 is configured as an SPI master.

MISO

Pin-Based Flow Control
Using a Separate RDY Pin

3

4

CH1 2.00VCH3 2.00V

CH2 2.00V Ω
CH4 2.00V Ω

M100µs
T
16µs

CH4

0V

15388-407

SCK

Figure 70. Page Read Start Sequence (Command and Address Bytes)

For example, the CAT64LC40 serial flash uses a dedicated
RDY pin to signal the availability of data to the SPI master.

Figure 71 shows a single-byte read, which is part of the page
read sequence.

The RDY pin of the ADuCM3027/ADuCM3029 can be wired
to an interrupt pin of the SPI slave in case the slave does notsupport a dedicated RDY pin. The slave uses the RDY pin to
indicate that the acquisition and data processing is complete.
The master does not provide SPI clock until it sees an active
level on this pin.

CS
1

MOSI
2

The user can configure the number of bytes to be read when the
RDY pin is asserted. Perform this is configuration by setting the
RDBURSTSZ field in the SPI flow control register(SPI_FLOW_CTL). After receiving this burst of bytes on MISO,
the SPI master continues to wait for the next RDY pin assertion
to receive the next set of bytes. This process is repeated until all
bytes as set in the SPI count register (SPI_CNT) are received.

MISO
3

4

CH1 2.00VCH3 2.00V

CH2 2.00V
CH4 2.00V

M10.0µs
T
16µs

CH4

0V

15388-408

SCK

Figure 71. Page Read—Single Data Byte

FLOW CONTROL MODES
Flow control is necessary to synchronize the data flow between
a master and slave. The ADuCM3027 provides flow control as adifferentiating feature in the SPI. Along with read commandmode, flow control can be used to receive multiple data bytes.
With flow control, the data transfer between the SPI master andslave is controlled based on the application requirements interms of periodic data or demand-based data read.
The SPI master in the ADuCM3027/ADuCM3029 supports thefollowing modes of flow control.
••Some SPI slaves have a dedicated RDY pin that is connected to
the SPI_RDY pin of the SPI master, which in this case is the
ADuCM3027/ADuCM3029. The SPI_RDY pin is a dedicatedpin (as an alternate functionality to a GPIO) for every SPI instance.

Pin-based flow control, controlled by the SPI slave.
Timer-based flow control, controlled by the SPI master.

Note that using read command mode, a maximum of 16 bytes
can be transmitted. This transmission is configured using the
TXBYTES field of the SPI read control register (SPI_RD_CTL).
The number of bytes received in one burst when using flow
control is set in the RDBURSTSZ field of the SPI flow control
register (SPI_FLOW_CTL) however, the total number of bytes
to be received does not have an imposed maximum limit.

Using the MISO Pin
Some SPI slaves do not have a dedicated RDY pin but have aprovision to reuse the MISO pin to inform the SPI master thatthe data is ready to be sent on MISO.
The ADuCM3027/ADuCM3029 SPI master waits for an active
level transition on the MISO line and, when this is detected,
reads RDBURSTSZ + 1 number of bytes and then goes back to a
wait state until another active level is detected on MISO.
The polarity of the MISO/RDY pin can be configured using the
POL field of the SPI flow control register (SPI_FLOW_CTL).

Rev. B | Page 47 of 51

UG-1091
0x9F

ADuCM3027/ADuCM3029 User Guide
0x00

0x00

0x00

0x05
SPI_WAIT_TMR
SCK CYCLESSPI_WAIT_TMR
SCK CYCLES

SCK

MOSI
0xEF

0x40

0x16

0xFF
15388-409

0xFF
MISO

Figure 72. Software Flow Control with Timer

Timer-Based Flow Control
For slaves that do not have a dedicated pin to inform the availabilityof data to the master, the microcontroller uses a 16-bit timer tointroduce wait states while reading data. When the timer triggers,
the master reads a burst of bytes (RDBURSTSZ + 1) and thenrestarts the timer. The timer is clocked at the SPI clock rate (SCK)
and the number of SCK cycles to wait before the timer istriggered can be set using the SPI_WAIT_TMR register. An
example of this operation is shown in Figure 72.
When this scheme is used to stall and drive SCK for flow
control, take care to ensure that the last SCK edge is a samplingedge. After the stall period is over, an SCK driving edge thencauses the next data transfer.

System Description

The flow control and read command modes in the ADuCM3027/
ADuCM3029 enhances the efficiency of this process by offloading
the MCU further. The system is put into Flexi mode, whichkeeps the core asleep and the SPI peripheral and the DMA active.
The sensor measures the data and uses the RDY pin to strobe
the SPI peripheral of the data availability. There is a dedicated
SPI_RDY pin (alternate functionality of a GPIO) for every SPI
instance in the ADuCM3027/ADuCM3029 MCU.
Without waking up the MCU, the SPI then reads the data set
using the read command mode. The sensor must be capable ofmultibyte data transfer to use this scheme effectively. In case ofan accelerometer sensor, the x-, y-, and z-axis readings are sent
as six bytes over the SPI.
DMA can be used to transfer the data into an allocated memory
space without CPU intervention.

This section uses the hardware flow control mode to
demonstrate how the flow control feature can contribute to
power savings in a system.

The application can collect the data instantaneously after every
measurement, or can collect buffered data from the slave after aconfigured number of bytes are collected by the sensor.

The system used to demonstrate this process consists of the
ADuCM3027/ADuCM3029 MCU and a sensor (such as anaccelerometer) connected over the SPI.
To design a power efficient system, it is essential to put the corein sleep mode whenever there is no processing required. In sucha system, after a sensor reading is available, the core is woken
up to receive and process the data from the sensor.

After the user defined set of bytes are collected, the SPI
peripheral or the DMA can wake up the MCU to process thesensor data.

Rev. B | Page 48 of 51

ADuCM3027/ADuCM3029 User Guide

UG-1091

Figure 73 shows the application flow diagram for an SPI dataread from an accelerometer every time an activity is detected. In
sensors such as the ADXL345, the data ready interrupt can beused to read the x-, y-, and z-axis readings in one SPI transaction.
In other sensors, a FIFO configuration can be performed tostore a number of samples in the sensor until the master reads
the FIFO.

CONCLUSIONS
The different features of the ADuCM3027/ADuCM3029 SPI,
such as read command mode and flow control, make the devices
ideal for use in battery-powered systems where the SPI peripheral
offloads the MCU and can be independently used for datacollection.

ADuCM3029

SENSOR

POWER UPDEVICE INITIALIZATIONPOWER UPDEVICE INITIALIZATIONCONFIGURE SPI WITH FLOWCONTROL AND IN READ
COMMAND MODE

SETUP SENSOR(CONFIGURE FIFO MODE,SAMPLES, MEASUREMENTMODE AND RANGE)CONFIGURE INT2 TO
GENERATE DATA READY/
WATERMARK INTERRUPTThis device suitability a significant advantage in wireless sensor
networks where the battery life of the sensor is critical in systemdesign. This also serves as a building block for designing smart
sensors with on-board data acquisition, as well as sensor data
analytics.

SPI

ENTER FLEXI MODESENSOR SETUP

ACTIVITY DETECTED

MEASURE DATASIGNAL ON SPI_RDY

SPI READ AND DMA
TRANSFER
ACTIVITY DETECTED

MEASURE DATASIGNAL ON SPI_RDY

SPI READ AND DMA
TRANSFERENTER ACTIVE MODE

Figure 73. Application Flowchart

Rev. B | Page 49 of 51

15388-410

DMA DONE IRQ
WAKE UP MCU

UG-1091

ADuCM3027/ADuCM3029 User Guide

SLEEP ON EXIT

The MCU subsystem of the ADuCM3027/ADuCM3029
processor is based on the ARM® Cortex™-M3 processor. The
sleep on exit feature saves power when the microcontroller issleeping and in interrupt handlers.

Figure 74 shows the flowchart when using the sleep on exitfeature. The procedure for using this feature is as follows:
1.
2.
3.
4.
5.

When sleep on exit is enabled, the processor enters directly tosleep when the ISR is finished. Interrupts are nested in casethere is more than one interrupt. After the execution of theseinterrupts, the processor returns automatically to sleep mode.

The program starts.
Sleep mode is invoked by a wait for interrupt (WFI) or a
wait for events (WFE) instruction.
The system enters sleep mode.
The device is woken up by an interrupt or an event.
The system returns automatically to sleep mode when theinterrupt is finished if the SLEEPONEXIT bit is set.
START

BENEFITSWFI/WFE

The sleep on exit feature presents some benefits in interrupt
driven applications, where the system is sleeping and it only
wakes up to run interrupts.

SLEEP

When sleep on exit is disabled, the workflow when an interrupt
arrives involves more time spent executing instructions.

WAKE UP TOEXECUTE THE INTERRUPTThe steps to perform the interrupt with sleep on exit featuredisabled are as follows:
1.
2.
3.
4.
5.

YES

Wake up the processor.
Push all the necessary information and the current state on
the stack.
Pun the interrupt code.
Pop the information on the stack to restore the registers.
Return to sleep mode.

There are many instructions to run an interrupt. Therefore, oninterrupt driven applications, the time spent on context switching
is not optimal because the core pushes instructions in the stackand, subsequently, the core pops them again.
The process is simplified by enabling the sleep on exit feature.
The processor immediately goes to sleep after finishing theinterrupt. The device does not return to the normal thread andkeeps the interrupt configuration, which avoids including pushand pop tasks into the stack, saving the energy and clock cycles
necessary to execute unnecessary instructions.

SLEEPONEXIT = 1?
NONEXT INSTRUCTION

13588-002

The ARM® Cortex™-M processors are ideal for low power
applications due to their balance between energy and efficiency.
These processors have a feature known as sleep on exit thatallows saving clock cycles and energy.

Figure 74. Sleep on Exit Flowchart

ENABLING THE SLEEP ON EXIT FEATURE
The ARM® Cortex™-M nested vector interrupt controller(NVIC) has a system control register with a bit field called
SLEEPONEXIT. To enable the sleep on exit feature, it is only
necessary to set the SLEEPONEXIT bit.
The address of the system control register is 0xE000ED10.
The System Control Register in the ADuCM3027/ADuCM3029
section shows this register and its bit fields in the ADuCM3027/
ADuCM3029 microcontroller.

Rev. B | Page 50 of 51

ADuCM3027/ADuCM3029 User Guide

UG-1091

SYSTEM CONTROL REGISTER IN THE ADuCM3027/ADuCM3029
Address: 0xE000ED10, Reset: 0x0000, Name: INTCON0
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

[ 1 5 : 3 ] R ES ER V E D[ 0 ] R ES ER V ED

[ 2 ] S L EEP D EEP ( R / W )d e e p s le e p fla g f o r H IBERNATE m o d e[ 1 ] S L EE P O N EX I T ( R /W )S le e p s th e c o r e o n e x it fr o m a n ISR

Table 24. Bit Descriptions for INTCON0
Bits[15:3]
2

Bit Name
RESERVEDSLEEPDEEP1SLEEPONEXIT

0

RESERVED

Description
Reserved.
Deep sleep flag for HIBERNATE mode.
0: Sleep Deep is not enabled.
1: Sleep Deep is enabled.
Sleeps the core on exit from an ISR.
0: Sleep On Exit is not enabled.
1: Sleep On Exit is enabled.
Reserved.

Reset
0x0
0x0

Access
R
R/W

0x0

R/W

0x0

R

ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
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UG15388-0-1/19(B)Rev. B | Page 51 of 51