Blackfin
Embedded Processor
ADSP-BF512/BF514/BF516/BF518
FEATURESPERIPHERALSUp to 400 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages. See Operating Conditions
Qualified for Automotive Applications. See Automotive
Products
168-ball CSP_BGA or 176-lead LQFP_EP (with exposed pad)IEEE 802.3-compliant 10/100 Ethernet MAC with IEEE 1588
support (ADSP-BF518 only)
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
2 dual-channel, full-duplex synchronous serial ports(SPORTs), supporting 8 stereo I2S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
2 memory-to-memory DMAs with external request lines
Event handler with 56 interrupt inputs
2 serial peripheral interfaces (SPI)
Removable storage interface (RSI) controller for MMC, SD,
SDIO, and CE-ATA
2 UARTs with IrDA support
2-wire interface (TWI) controller
Eight 32-bit timers/counters with PWM support
3-phase 16-bit center-based PWM unit
32-bit general-purpose counter
Real-time clock (RTC) and watchdog timer
32-bit core timer
40 general-purpose I/Os (GPIOs)
Debug/JTAG interface
On-chip PLL capable of frequency multiplication

MEMORY
116K bytes of on-chip memory
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from OTP memory, external
SPI/parallel memories, or from SPI/UART host devices
Code security with Lockbox secure technology
One-time-programmable (OTP) memory
Memory management unit providing memory protection

RTC

WATCHDOG TIMEROTPPERIPHERALACCESS BUS
COUNTERJTAG TEST AND EMULATION

3-PHASE PWM
TIMER7–0

B

TWI

INTERRUPTCONTROLLER

SPORT1-0
RSI (SDIO)

L1
INSTRUCTIONMEMORYL1DATAMEMORYDMACONTROLLER

PORTS

PPI
UART1–0

16

DMA CORE BUS

EXTERNAL ACCESS BUS

DMA
EXTERNAL
BUS

EMAC
SPI1

EXTERNAL PORT FLASH,
SDRAM CONTROL

BOOT
ROM

SPI0

Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. E

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ADSP-BF512/BF514/BF516/BF518
TABLE OF CONTENTS
Features ................................................................. 1

Additional Information ........................................ 16

Memory ................................................................ 1

Related Signal Chains ........................................... 16

Peripherals ............................................................. 1

Signal Descriptions ................................................. 17

Table of Contents ..................................................... 2

Specifications ........................................................ 20

Revision History ...................................................... 2

Operating Conditions ........................................... 20

General Description ................................................. 3

Electrical Characteristics ....................................... 22

Portable Low Power Architecture ............................. 3

Absolute Maximum Ratings ................................... 25

System Integration ................................................ 3

ESD Sensitivity ................................................... 25

Blackfin Processor Core .......................................... 3

Timing Specifications ........................................... 26

Memory Architecture ............................................ 5

Output Drive Currents ......................................... 49

Event Handling .................................................... 6

Test Conditions .................................................. 51

DMA Controllers .................................................. 6

Thermal Characteristics ........................................ 55

Processor Peripherals ............................................. 7

176-Lead LQFP_EP Lead Assignment ......................... 56

Lockbox Secure Technology Disclaimer ................... 11

168-Ball CSP_BGA Ball Assignment ........................... 58

Dynamic Power Management ................................ 11

Outline Dimensions ................................................ 60

Voltage Regulation Interface .................................. 12

Surface-Mount Design .......................................... 61

Clock Signals ..................................................... 12

Automotive Products .............................................. 62

Booting Modes ................................................... 14

Ordering Guide ..................................................... 63

Instruction Set Description ................................... 15
Development Tools ............................................. 15

REVISION HISTORY
6/20—Rev. D to Rev. E
This Rev E product data sheet removes the Flash Memory section, flash memory specifications, and all obsolete models that
include 16M bit SPI flash memory.
These changes are reflected in the following sections:
Changes to Memory ................................................. 1
Changes to Peripherals .............................................. 1
Changes to Functional Block Diagram .......................... 1
Changes to Processor Comparison ............................... 3
Changes to Power Domains ...................................... 12
Changes to Booting Modes ....................................... 14
Changes to Signal Descriptions ................................. 17
Changes to Operating Conditions .............................. 20
Changes to Electrical Characteristics ........................... 22
Changes to 176-Lead LQFP_EP Lead Assignment .......... 56
Changes to 168-Ball CSP_BGA Ball Assignment ............ 58
Changes to Ordering Guide ...................................... 63

Rev. E |Page 2 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
GENERAL DESCRIPTION
The ADSP-BF512/ADSP-BF514/ADSP-BF516/ADSP-BF518
processors are members of the Blackfin® family of products,
incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-ofthe-art signal processing engine, the advantages of a clean,orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities
into a single instruction-set architecture.

PORTABLE LOW POWER ARCHITECTURE

Memory (bytes)

ADSP-BF518

FeatureIEEE-1588
Ethernet MAC
RSI
TWI
SPORTs
UARTs
SPIs
GP Timers
Watchdog Timers
RTC
PPI
Rotary Counter
3-Phase PWM Pairs
GPIOs
L1 Instruction SRAM
L1 Instruction SRAM/Cache
L1 Data SRAM
L1 Data SRAM/Cache
L1 Scratchpad
L3 Boot ROM
Maximum Speed Grade
Package Options

ADSP-BF516

SYSTEM INTEGRATIONADSP-BF514

Table 1. Processor Comparison
ADSP-BF512

The processors are completely code compatible with otherBlackfin processors.

Blackfin processors provide world-class power management
and performance. They are produced with a low power and low
voltage design methodology and feature on-chip dynamic
power management, which is the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. This capability can result in a substantial reduction in power consumption, compared with just varying thefrequency of operation. This allows longer battery life forportable appliances.

–
–
–
1
2
2
2
8
1
1
1
1
3
40

–
–
1
–
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
3
3
3
40
40
40
32K
16K
32K
32K
4K
32K
400 MHz
176-Lead LQFP_EP (withExposed Pad)
168-Ball CSP_BGA

By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice fornext-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal
processing in one integrated package.

The ADSP-BF51x processors are highly integrated system-on-achip solutions for the next generation of embedded network
connected applications. By combining industry-standard interfaces with a high performance signal processing core, costeffective applications can be developed quickly, without theneed for costly external components. The system peripherals
include an IEEE-compliant 802.3 10/100 Ethernet MAC with
IEEE-1588 support (ADSP-BF518 only), an RSI controller, a
TWI controller, two UART ports, two SPI ports, two serial ports(SPORTs), nine general-purpose 32-bit timers (eight with PWM
capability), 3-phase PWM for motor control, a real-time clock, awatchdog timer, and a parallel peripheral interface (PPI).

BLACKFIN PROCESSOR COREAs shown in Figure 2, the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. Whenperforming compute operations on 16-bit operand data, theregister file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in eachcycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
The ALUs perform a traditional set of arithmetic and logicaloperations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,16-bit and 8-bit adds with clipping, 8-bit average operations,and 8-bit subtract/absolute value/accumulate (SAA) operations.
The compare/select and vector search instructions are also
provided.
For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.

Rev. E |Page 3 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
ADDRESS ARITHMETIC UNIT

32

DA0

32

L3

B3

M3

I2

L2

B2

M2

I1

L1

B1

M1

I0

L0

B0

M0

SP
FP
P5
DAG1

P4
P3

DAG0

P2
P1
P0

TO MEMORY

DA1

I3

32
PREG

32
RAB

SD
LD1
LD0

32
32
32

ASTAT

32
32

SEQUENCER
R7.H
R6.H

R7.L
R6.L

R5.H

R5.L

R4.H

R4.L

R3.H

R3.L

R2.H

R2.L

R1.H

R1.L

R0.H

R0.L

16

ALIGN

16

8

8

8

8
DECODEBARRELSHIFTER

40
40

A0

32

40

40

LOOP BUFFER

A1

CONTROL
UNIT

32
DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

The 40-bit shifter can perform shifts and rotates and is used tosupport normalization, field extract, and field deposit
instructions.

memory holds instructions only. The two data memories holddata, and a dedicated scratchpad data memory stores stack andlocal variable information.

The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative andindirect conditional jumps (with static branch prediction), andsubroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning thatthe programmer need not manage the pipeline when executing
instructions with data dependencies.

In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individualtasks that may be operating on the core and can protect system
registers from unintended access.

The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction

Rev. E |The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing aprotected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized sothat 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit
instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the coreresources in a single instruction cycle.

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ADSP-BF512/BF514/BF516/BF518
The on-chip L1 memory system is the highest-performance
memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132M bytes ofphysical memory.

The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE
The ADSP-BF51x processors view memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performancebalance of some very fast, low-latency on-chip memory as cacheor SRAM, and larger, lower-cost and performance off-chip
memory systems. The memory map for both internal and external memory space is shown in Figure 3.

The memory DMA controller provides high bandwidth datamovement capability. It can perform block transfers of code ordata between the internal memory and the external
memory spaces.

Internal (On-Chip) Memory
The ADSP-BF51x processors have three blocks of on-chip
memory that provide high bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
48K bytes SRAM, of which 16K bytes can be configured as afour-way set-associative cache. This memory is accessed at fullprocessor speed.

0xFFFF FFFF
CORE MMR REGISTERS (2M BYTES)The second on-chip memory block is the L1 data memory, consisting of up to two banks of up to 32K bytes each. Each memorybank is configurable, offering both cache and SRAM functionality. This memory block is accessed at full processor speed.

0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTES)
0xFFC0 0000
RESERVED
0xFFB0 1000SCRATCHPAD SRAM (4K BYTES)
0xFFB0 0000
RESERVED
0xFFA1 4000

INTERNAL MEMORY MAP

INSTRUCTION BANK C SRAM/CACHE (16K BYTES)
0xFFA1 0000
RESERVED
0xFFA0 8000
INSTRUCTION BANK B SRAM (16K BYTES)
0xFFA0 4000
INSTRUCTION BANK A SRAM (16K BYTES)
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM / CACHE (16K BYTES)
0xFF90 4000
DATA BANK B SRAM (16K BYTES)
0xFF90 0000

External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The SDRAM controller can be programmed to interface to up
to 128M bytes of SDRAM. A separate row can be open for each
SDRAM internal bank, and the SDRAM controller supports up
to four internal SDRAM banks, improving overall performance.

RESERVED
0xFF80 8000
DATA BANK A SRAM / CACHE (16K BYTES)
0xFF80 4000
DATA BANK A SRAM (16K BYTES)
0xFF80 0000
RESERVED
0xEF00 8000
BOOT ROM (32K BYTES)EXTERNAL MEMORY MAP

0xEF00 0000
RESERVED
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTES)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTES)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTES)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTES)
0x2000 0000
0x08 00 0000

The third memory block is a 4K byte scratchpad SRAM whichruns at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.

RESERVEDSDRAM MEMORY (16M BYTES - 128M BYTES)

0x0000 0000

Figure 3. ADSP-BF51x Internal/External Memory Map

Rev. E |The asynchronous memory controller can be programmed tocontrol up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, sothat these banks are only contiguous if each is fully populatedwith 1M byte of memory.

One-Time Programmable Memory
The processors have 64K bits of one-time programmable nonvolatile memory that can be programmed by the developer only
once. It includes the array and logic to support read access andprogramming. Additionally, its pages can be write protected.
The OTP memory allows both public and private data to be
stored on-chip. In addition to storing public and private key
data for applications requiring security, OTP allows developers
to store completely user-definable data such as customer ID,
product ID, and MAC address. Therefore, generic parts can besupplied which are then programmed and protected by thedeveloper within this non-volatile memory.

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ADSP-BF512/BF514/BF516/BF518
I/O Memory SpaceCore Event Controller (CEC)

The processors do not define a separate I/O space. All resources
are mapped through the flat 32-bit address space. On-chip I/O
devices have their control registers mapped into memorymapped registers (MMRs) at addresses near the top of the
4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.

The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority
interrupts (IVG15–14) are recommended to be reserved forsoftware interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the processors. The inputs
to the CEC, identifies their names in the event vector table(EVT), and lists their priorities are described in the
ADSP-BF51x Blackfin Processor Hardware Reference Manual“System Interrupts” chapter.

Booting from ROM

System Interrupt Controller (SIC)

The processors contain a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the processors
are configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more
information, see Booting Modes.

The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to theprioritized general-purpose interrupt inputs of the CEC.
Although the processors provide a default mapping, the user
can alter the mappings and priorities of interrupt events by
writing the appropriate values into the interrupt assignment
registers (SIC_IARx). See the ADSP-BF51x Blackfin Processor
Hardware Reference Manual “System Interrupts” chapter for the
inputs into the SIC and the default mappings into the CEC.

EVENT HANDLINGThe event controller handles all asynchronous and synchronous
events to the processor. The processors provide event handlingthat supports both nesting and prioritization. Nesting allows
multiple event service routines to be active simultaneously.
Prioritization ensures that servicing of a higher priority event
takes precedence over servicing of a lower priority event.
The controller provides support for five different types of
events:• Emulation—An emulation event causes the processor toenter emulation mode, allowing command and control ofthe processor through the JTAG interface.
• Reset—This event resets the processor.
• Nonmaskable Interrupt (NMI)—The NMI event can begenerated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shutdown of the system.
• Exceptions—Events that occur synchronously to program
flow; that is, the exception is taken before the instruction isallowed to complete. Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts—Events that occur asynchronously to program
flow. They are caused by input signals, timers, and otherperipherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. Whenan event is triggered, the state of the processor is saved on the
supervisor stack.
The event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The
core event controller works with the system interrupt controller
to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are thenrouted directly into the general-purpose interrupts of the CEC.

Rev. E |The SIC allows further control of event processing by providing
three pairs of 32-bit interrupt control and status registers. Eachregister contains a bit corresponding to each of the peripheral
interrupt events. For more information, see the ADSP-BF51x
Blackfin Processor Hardware Reference Manual “System Interrupts” chapter.

DMA CONTROLLERSThe ADSP-BF51x processors have multiple independent DMA
channels that support automated data transfers with minimal
overhead for the processor core. DMA transfers can occur
between the processor's internal memories and any of its DMAcapable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals andexternal devices connected to the external memory interfaces,
including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the Ethernet
MAC, RSI, SPORTs, SPIs, UARTs, and PPI. Each individual
DMA-capable peripheral has at least one dedicated DMA
channel.
The processors’ DMA controller supports both one-dimensional (1-D) and two-dimensional (2-D) DMA transfers. DMA
transfer initialization can be implemented from registers orfrom sets of parameters called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, thecolumn step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature isespecially useful in video applications where data can be deinterleaved on the fly.

Page 6 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
Examples of DMA types supported by the DMA controller
include:minute, hour, or day clock ticks, interrupt on programmablestopwatch countdown, or interrupt at a programmed alarmtime.

• A single, linear buffer that stops upon completion

The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consistsof four counters: a 60-second counter, a 60-minute counter, a24-hour counter, and an 32,768-day counter.

• A circular, auto-refreshing buffer that interrupts on eachfull or fractionally full buffer• 1-D or 2-D DMA using a linked list of descriptors• 2-D DMA using an array of descriptors, specifying only thebase DMA address within a common pageIn addition to the dedicated peripheral DMA channels, there are
two memory DMA channels that transfer data between the various memories of the processor system. This enables transfers ofblocks of data between any of the memories—including external
SDRAM, ROM, SRAM, and flash memory—with minimal
processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by astandard register-based autobuffer mechanism.
The processors also have an external DMA controller capability
via dual external DMA request signals when used in conjunction with the external bus interface unit (EBIU). Thisfunctionality can be used when a high speed interface isrequired for external FIFOs and high bandwidth communications peripherals. It allows control of the number of datatransfers for memory DMA. The number of transfers per edge is
programmable. This feature can be programmed to allow memory DMA to have an increased priority on the external bus
relative to the core.

When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in thealarm control register. There are two alarms: The first alarm isfor a time of day. The second alarm is for a day and time ofthat day.
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch isenabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the processor
from sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from deep sleep mode or cause a transition from the hibernate
state.
Connect RTC signals RTXI and RTXO with external components as shown in Figure 4.
RTXO

RTXI
R1

PROCESSOR PERIPHERALSX1

The ADSP-BF51x processors contain a rich set of peripherals
connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overallsystem performance (see Figure 2). The processors contain dedicated network communication modules and high speed serial
and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or externalsources, and power management control functions to tailor the
performance and power characteristics of the processor and system to many application scenarios.
All of the peripherals, except for the general-purpose I/O, rotary
counter, TWI, three-phase PWM, real-time clock, and timers,
are supported by a flexible DMA structure. There are also separate memory DMA channels dedicated to data transfers
between the processor's various memory spaces, including
external SDRAM and asynchronous memory. Multiple on-chipbuses provide enough bandwidth to keep the processor corerunning along with activity on all of the on-chip and external
peripherals.

Real-Time Clock
The real-time clock (RTC) provides a robust set of digital watch
features, including current time, stopwatch, and alarm. The
RTC is clocked by a 32.768 kHz crystal external to the processors. The RTC peripheral has a dedicated power supply so that it
can remain powered up and clocked even when the rest of theprocessor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per second,
Rev. E |C1

C2SUGGESTED COMPONENTS:
X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR
EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22 pF
C2 = 22 pF
R1 = 10 M:
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

Figure 4. External Components for RTC

Watchdog Timer
The ADSP-BF51x processors include a 32-bit timer that can beused to implement a software watchdog function. A software
watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset,
nonmaskable interrupt (NMI), or general-purpose interrupt, if
the timer expires before being reset by software. The programmer initializes the count value of the timer, enables theappropriate interrupt, then enables the timer. Thereafter, thesoftware must reload the counter before it counts to zero fromthe programmed value. This protects the system from remaining in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.

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ADSP-BF512/BF514/BF516/BF518
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine if the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK) at a maximum
frequency of fSCLK.

TimersThere are nine general-purpose programmable timer units in
the ADSP-BF51x processors. Eight timers have an external signal that can be configured either as a pulse width modulator(PWM) or timer output, as an input to clock the timer, or as amechanism for measuring pulse widths and periods of external
events. These timers can be synchronized to an external clock
input to the several other associated PF signals, an external
clock input to the PPI_CLK input signal, or to the internal
SCLK.
The timer units can be used in conjunction with the two UARTs
to measure the width of the pulses in the data stream to providea software auto-baud detect function for the respective serial
channels.
The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the eight general-purpose programmable timers,a ninth timer is also provided. This extra timer is clocked by theinternal processor clock and is typically used as a system tickclock for generation of operating system periodic interrupts.

3-Phase PWM• Output polarity and clock gating control• Dedicated asynchronous PWM shutdown signal

General-Purpose (GP) Counter
A 32-bit GP counter is provided that can sense 2-bit quadratureor binary codes as typically emitted by industrial drives or manual thumb wheels. The counter can also operate ingeneral-purpose up/down count modes. Then, count direction
is either controlled by a level-sensitive input signal or by twoedge detectors.
A third input can provide flexible zero marker support and canalternatively be used to input the push-button signal of thumbwheels. All three signals have a programmable debouncing
circuit.
An internal signal forwarded to the GP timer unit enables one
timer to measure the intervals between count events. Boundary
registers enable auto-zero operation or simple system warning
by interrupts when programmable count values are exceeded.

Serial Ports
The ADSP-BF51x processors incorporate two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial andmultiprocessor communications. The SPORTs support the following features:
Serial port data can be automatically transferred to and fromon-chip memory/external memory via dedicated DMA channels. Each of the serial ports can work in conjunction withanother serial port to provide TDM support. In this configuration, one SPORT provides two transmit signals while the other
SPORT provides the two receive signals. The frame sync andclock are shared.

The processors integrate a flexible and programmable 3-phase
PWM waveform generator that can be programmed to generate
the required switching patterns to drive a 3-phase voltage
source inverter for ac induction (ACIM) or permanent magnet
synchronous (PMSM) motor control. In addition, the PWM
block contains special functions that considerably simplify thegeneration of the required PWM switching patterns for controlof the electronically commutated motor (ECM) or brushless dc
motor (BDCM). Software can enable a special mode forswitched reluctance motors (SRM).

Serial ports operate in five modes:

Features of the 3-phase PWM generation unit are:

The processors have two SPI-compatible ports (SPI0 and SPI1)
that enable the processor to communicate with multiple SPIcompatible devices.

• 16-bit center-based PWM generation unit
• Programmable PWM pulse width• Single/double update modes• Programmable dead time and switching frequency• Twos-complement implementation which permits smoothtransition to full ON and full OFF states• Possibility to synchronize the PWM generation to an external synchronization• Special provisions for BDCM operation (crossover andoutput enable functions)• Standard DSP serial mode
• Multichannel (TDM) mode
• I2S mode
• Packed I2S mode
• Left-justified mode

Serial Peripheral Interface (SPI) Ports

The SPI interface uses three signals for transferring data: twodata signals (master output-slave input–MOSI, and master
input-slave output–MISO) and a clock signal (serial
clock–SCK). An SPI chip select input signal (SPIxSS) lets other
SPI devices select the processor, and multiple SPI chip selectoutput signals let the processor select other SPI devices. The SPI
select signals are reconfigured general-purpose I/O signals.
Using these signals, the SPI port provides a full-duplex, synchronous serial interface, which supports both master/slavemodes and multimaster environments.

• Wide variety of special switched reluctance (SR) operating
modes
Rev. E |Page 8 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
The SPI port baud rate and clock phase/polarities are programmable, and it has an integrated DMA channel, configurable tosupport transmit or receive data streams. The DMA channel ofthe SPI can only service unidirectional accesses at any giventime.

• A ten-signal external interface with clock, command, andup to eight data lines• Card detection using one of the data signals• Card interface clock generation from SCLK• SDIO interrupt and read wait features

UART Ports
The processors provide two full-duplex universal asynchronousreceiver/transmitter (UART) ports, which are fully compatible
with PC-standard UARTs. Each UART port provides asimplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers ofserial data. A UART port includes support for five to eight data
bits, and none, even, or odd parity. Optionally, an additional
address bit can be transferred to interrupt only addressed nodes
in multi-drop bus (MDB) systems. A frame is terminates by one,
one and a half, two or two and a half stop bits.
The UART ports support automatic hardware flow control
through the Clear To Send (CTS) input and Request To Send
(RTS) output with programmable assertion FIFO levels.

• CE-ATA command completion signal recognition anddisable10/100 Ethernet MAC
The ADSP-BF516 and ADSP-BF518 processors offer the capability to directly connect to a network by way of an embedded
fast Ethernet media access controller (MAC) that supports both
10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec) operation. The 10/100 Ethernet MAC peripheral on the processor isfully compliant to the IEEE 802.3-2002 standard and it provides
programmable features designed to minimize supervision, bususe, or message processing by the rest of the processor system.
Some standard features are:• Support of MII and RMII protocols for external PHYs

To help support the Local Interconnect Network (LIN) protocols, a special command causes the transmitter to queue a breakcommand of programmable bit length into the transmit buffer.
Similarly, the number of stop bits can be extended by a programmable inter-frame space.

• Full duplex and half duplex modes• Data framing and encapsulation: generation and detectionof preamble, length padding, and FCS• Media access management (in half-duplex operation): collision and contention handling, including control ofretransmission of collision frames and of back-off timing

The capabilities of the UARTs are further extended with support for the Infrared Data Association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.

• Flow control (in full-duplex operation): generation anddetection of pause frames

2-Wire Interface (TWI)
The processors include a TWI module for providing a simple
exchange method of control data between multiple devices. The
TWI is compatible with the widely used I2C® bus standard. The
TWI module offers the capabilities of simultaneous master andslave operation, support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two signals fortransferring clock (SCL) and data (SDA) and supports the protocol at speeds up to 400k bits/sec. The TWI interface signals
are compatible with 5 V logic levels.

• Station management: generation of MDC/MDIO frames
for read-write access to PHY registers• Operating range for active and sleep operating modes, see
Table 39 and Table 40• Internal loopback from transmit to receive
Some advanced features are:

Additionally, the processor’s TWI module is fully compatible
with serial camera control bus (SCCB) functionality for easiercontrol of various CMOS camera sensor devices.

• Buffered crystal output to external PHY for support of asingle crystal system• Automatic checksum computation of IP header and IP
payload fields of Rx frames• Independent 32-bit descriptor-driven receive and transmit
DMA channels

Removable Storage Interface (RSI)The RSI controller, available on the ADSP-BF514/ADSPBF516/ADSP-BF518 processors, acts as the host interface formulti-media cards (MMC), secure digital memory cards (SDCard), secure digital input/output cards (SDIO), and CE-ATA
hard disk drives. The following list describes the main featuresof the RSI controller.
• Support for a single MMC, SD memory, SDIO card or CEATA hard disk drive• Frame status delivery to memory through DMA, including
frame completion semaphores for efficient buffer queue
management in software• Tx DMA support for separate descriptors for MAC header
and payload to eliminate buffer copy operations• Convenient frame alignment modes support even 32-bitalignment of encapsulated receive or transmit IP packet
data in memory after the 14-byte MAC header• Support for 1-bit and 4-bit SD modes• Support for 1-bit, 4-bit and 8-bit MMC modes• Support for 4-bit and 8-bit CE-ATA hard disk drives

Rev. E |Page 9 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518• Programmable Ethernet event interrupt supports any combination of:• Selected receive or transmit frame status conditions• PHY interrupt condition• Wakeup frame detected• Selected MAC management counter(s) at half-full• DMA descriptor error• 47 MAC management statistics counters with selectable
clear-on-read behavior and programmable interrupts on
half maximum value• Programmable receive address filters, including a 64-bin
address hash table for multicast and/or unicast frames, andprogrammable filter modes for broadcast, multicast, unicast, control, and damaged frames• Advanced power management supporting unattended
transfer of receive and transmit frames and status to/fromexternal memory via DMA during low power sleep mode

General-Purpose I/O (GPIO)
The ADSP-BF51x processors have 40 bidirectional, generalpurpose I/O (GPIO) signals allocated across three separate
GPIO modules—PORTFIO, PORTGIO, and PORTHIO, associated with Port F, Port G, and Port H, respectively. Each
GPIO-capable signal shares functionality with other peripherals
via a multiplexing scheme; however, the GPIO functionality is
the default state of the device upon power-up. Neither GPIO
output nor input drivers are active by default. Each general-purpose port signal can be individually controlled by manipulationof the port control, status, and interrupt registers.

Parallel Peripheral Interface (PPI)The ADSP-BF51x processors provide a parallel peripheral interface (PPI) that can connect directly to parallel analog-to-digitaland digital-to-analog converters, ITU-R-601/656 video encoders and decoders, and other general-purpose peripherals. The
PPI consists of a dedicated input clock signal, up to three frame
synchronization signals, and up to 16 data signals.

• Support for 802.3Q tagged VLAN frames

In ITU-R-656 modes, the PPI receives and parses a data streamof 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information
is supported.

• Programmable MDC clock rate and preamble suppression

Three distinct ITU-R-656 modes are supported:• System wakeup from sleep operating mode upon magic
packet or any of four user-definable wakeup frame filters• In RMII operation, seven unused signals may be configured as GPIO signals for other purposes• Active video only mode—The PPI does not read in any
data between the End of Active Video (EAV) and Start of
Active Video (SAV) preamble symbols, or any data present
during the vertical blanking intervals. In this mode, thecontrol byte sequences are not stored to memory; they arefiltered by the PPI.

IEEE 1588 Support
The IEEE 1588 standard is a precision clock synchronization
protocol for networked measurement and control systems. The
ADSP-BF518 processor includes hardware support for IEEE
1588 with an integrated precision time protocol synchronization engine (PTP_TSYNC). This engine provides hardware
assisted time stamping to improve the accuracy of clock synchronization between PTP nodes. The main features of the
PTP_SYNC engine are:

• Vertical blanking only mode—The PPI only transfers vertical blanking interval (VBI) data, as well as horizontal
blanking information and control byte sequences on
VBI lines.
• Entire field mode—The entire incoming bitstream is readin through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded
in horizontal and vertical blanking intervals.

• Support for both IEEE 1588-2002 and IEEE 1588-2008 protocol standards• Hardware assisted time stamping capable of up to 12.5 ns
resolution• Lock adjustment• Programmable PTM message support• Dedicated interrupts• Programmable alarm• Multiple input clock sources (SCLK, MII clock, external
clock)

Though not explicitly supported, ITU-R-656 output functionality can be achieved by setting up the entire frame structure(including active video, blanking, and control information) inmemory and streaming the data out the PPI in a frame sync-lessmode. The processor’s 2-D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.
The general-purpose modes of the PPI are intended to suit awide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:• Programmable pulse per second (PPS) output• Auxiliary snapshot to time stamp external eventsPorts• Data receive with internally generated frame syncs

Because of the rich set of peripherals, the processors group themany peripheral signals to four ports—port F, port G, port H,
and port J. Most of the associated pins/balls are shared by multiple signals. The ports function as multiplexer controls.

• Data receive with externally generated frame syncs

Rev. E |Page 10 of 63 |• Data transmit with internally generated frame syncs• Data transmit with externally generated frame syncs

June 2020

ADSP-BF512/BF514/BF516/BF518
These modes support ADC/DAC connections, as well as videocommunication with hardware signaling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data.

Code Security with Lockbox Secure Technology
A security system consisting of a blend of hardware and software provides customers with a flexible and rich set of code
security features with Lockbox® secure technology. Key features
include:• OTP memory• Unique chip ID• Code authentication• Secure mode of operation
The security scheme is based upon the concept of authentication of digital signatures using standards-based algorithms andprovides a secure processing environment in which to executecode and protect assets.

LOCKBOX SECURE TECHNOLOGY DISCLAIMER
Analog Devices does not guarantee that the Code Security with
Lockbox Secure Technology described herein provides absolute
security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIEDWARRANTIES THAT THE SECURITY FEATURES CANNOT BE BREACHED, COMPROMISED, OR OTHERWISE
CIRCUMVENTED AND IN NO EVENT SHALL ANALOG
DEVICES BE LIABLE FOR ANY LOSS, DAMAGE,
DESTRUCTION, OR RELEASE OF DATA, INFORMATION,
PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY.

Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. Thisis the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled
peripherals run at full speed.

Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In thismode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode isentered. DMA access is available to appropriately configured
L1 memories.
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.

Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity wakes up the processor.
When in the sleep mode, asserting wakeup causes the processor
to sense the value of the BYPASS bit in the PLL control register(PLL_CTL). If BYPASS is disabled, the processor transitions to
the full on mode. If BYPASS is enabled, the processor transitions to the active mode.
System DMA access to L1 memory is not supported insleep mode.

Deep Sleep Operating Mode—Maximum Dynamic Power
Savings

DYNAMIC POWER MANAGEMENT
The ADSP-BF51x processors provide four operating modes,
each with a different performance/power profile. In addition,
dynamic power management provides the control functions todynamically alter the processor core supply voltage, further
reducing power dissipation. When configured for a 0 V coresupply voltage, the processor enters the hibernate state. Control
of clocking to each of the processor peripherals also reduces
power consumption. See Table 2 for a summary of the power
settings for each mode.
Table 2. Power Settings

Mode/State PLL

Core
PLL
Clock
Bypassed (CCLK)

SystemClock(SCLK)

Full On

EnabledNo

Enabled Enabled On

ActiveEnabled/ Yes
Disabled

Enabled Enabled On

Sleep

Enabled—Disabled Enabled On

Deep Sleep

Disabled —Disabled Disabled On

Hibernate

Disabled —Disabled Disabled Off

The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to allsynchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but cannot access internal
resources or external memory. This powered-down mode canonly be exited by assertion of the reset interrupt (RESET) or by
an asynchronous interrupt generated by the RTC. When in deep
sleep mode, an RTC asynchronous interrupt causes the processor to transition to the Active mode. Assertion of RESET while
in deep sleep mode causes the processor to transition to the fullon mode.

Hibernate State—Maximum Static Power Savings
Core
Power

Rev. E |The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and system
blocks (SCLK). Any critical information stored internally (forexample memory contents, register contents) must be written toa non-volatile storage device prior to removing power if theprocessor state is to be preserved. Writing b#00 to the FREQ bitsin the VR_CTL register also causes the EXT_WAKE signal totransition low, which can be used to signal an external voltage
regulator to shut down.

Page 11 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
Since VDDEXT is still supplied in this mode, all of the external signals three-state, unless otherwise specified. This allows otherdevices that may be connected to the processor to still havepower applied without drawing unwanted current.
The Ethernet module can signal an external regulator to wakeup using the EXT_WAKE signal. If PF15 does not connect as a
PHYINT signal to an external PHY device, it can be pulled low
by any other device to wake the processor up. The processor canalso be woken up by a real-time clock wakeup event or by asserting the RESET pin. All hibernate wakeup events initiate thehardware reset sequence. Individual sources are enabled by the
VR_CTL register. The EXT_WAKE signal is provided to indicate the occurrence of wakeup events.

Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings
can be dramatic, as shown in the following equations.
Power Savings Factor
V DDINTRED 2
f CCLKREDT RED= --------------------------   --------------------------------   ---------------  T NOM 
f CCLKNOM  V DDINTNOM% Power Savings =  1 – Power Savings Factor   100%
where the variables in the equations are:fCCLKNOM is the nominal core clock frequency

With the exception of the VR_CTL and the RTC registers, allinternal registers and memories lose their content in the hibernate state. State variables may be held in external SRAM or
SDRAM. The SCKELOW bit in the VR_CTL register controls
whether or not SDRAM operates in self-refresh mode, whichallows it to retain its content while the processor is in hibernation and through the subsequent reset sequence.

Power Savings
As shown in Table 3, the processors support up to six different
power domains, which maximizes flexibility while maintaining
compliance with industry standards and conventions. By isolating the internal logic of the processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of dynamic power management without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains, but all domains
must be powered according to the appropriate Specifications
table for processor Operating Conditions; even if the feature/peripheral is not used.
Table 3. Power Domains

fCCLKRED is the reduced core clock frequency
VDDINTNOM is the nominal internal supply voltage
VDDINTRED is the reduced internal supply voltage
TNOM is the duration running at fCCLKNOM
TRED is the duration running at fCCLKREDVOLTAGE REGULATION INTERFACEThe ADSP-BF51x processors require an external voltage regulator to power the VDDINT domain. To reduce standby power
consumption in the hibernate state, the external voltage regulator can be signaled through EXT_WAKE to remove power fromthe processor core. The EXT_WAKE signal is high-true forpower-up and may be connected directly to the low-true shut
down input of many common regulators.
The Power Good (PG) input signal allows the processor to start
only after the internal voltage has reached a chosen level. In thisway, the startup time of the external regulator is detected after
hibernation. For a complete description of the PG functionality,refer to the ADSP-BF51x Blackfin Processor Hardware Reference.

Power Domain

VDD Range

CLOCK SIGNALS

All internal logic, except RTC, Memory, OTP

VDDINT

RTC internal logic and crystal I/O

VDDRTC

Memory logic

VDDMEM

The ADSP-BF51x processors can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived froman external clock oscillator.

OTP logic

VDDOTP

All other I/O

VDDEXTThe dynamic power management feature of the processor
allows both the processor’s input voltage (VDDINT) and clock frequency (fCCLK) to be dynamically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation, while reducing thevoltage by 25% reduces dynamic power dissipation by morethan 40%.

Rev. E |If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the specified frequency during normal operation. This signal isconnected to the processor CLKIN signal. When an external
clock is used, the XTAL pin/ball must be left unconnected.
Alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. For fundamental
frequency operation, use the circuit shown in Figure 5. A parallel-resonant, fundamental frequency, microprocessor-grade
crystal is connected across the CLKIN and XTAL pins/balls. The
on-chip resistance between the CLKIN pin/ball and the XTAL
pin/ball is in the 500 kΩ range. Further parallel resistors are typically not recommended. The two capacitors and the series
resistor shown in Figure 5 fine tune phase and amplitude of thesine frequency.

Page 12 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
The capacitor and resistor values shown in Figure 5 are typicalvalues only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive levelspecified by the crystal manufacturer. The user should verify thecustomized values based on careful investigations on multiple
devices over temperature range.

reflects the SCLK frequency to the off-chip world. It belongs to
the SDRAM interface, but it functions as a reference signal inother timing specifications as well. While active by default, it
can be disabled using the EBIU_SDGCTL and EBIU_AMGCTL
registers.
“FINE” ADJUSTMENTREQUIRES PLL SEQUENCING“COARSE” ADJUSTMENT
ON-THE-FLY

BLACKFIN
CLKOUT
TO PLL CIRCUITRY

CLKIN

EN

PLL
5u to 64u

÷ 1, 2, 4, 8

CCLK

÷ 1 to 15

SCLK

VCO

CLKBUF
560 ⍀EN

330 ⍀*

18 pF *

Figure 6. Frequency Modification Methods

XTAL

CLKIN

All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output(VCO) and the system clock. SCLK divider values are 1 through15. Table 4 illustrates typical system clock ratios.

FOR OVERTONEOPERATION ONLY:

18 pF *

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTEDRESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀.

Table 4. Example System Clock Ratios

Signal Name
SSEL3–0

Example Frequency Ratios
Divider Ratio (MHz)VCO/SCLK
VCO
SCLK

0010

2:1

0110

6:1

300

50

1010

10:1

400

40

Figure 5. External Crystal Connections

A third-overtone crystal can be used for frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit asshown in Figure 5. A design procedure for third-overtone operation is discussed in detail in application note (EE-168) Using
Third Overtone Crystals with the ADSP-218x DSP on the Analog
Devices website (www.analog.com)—use site search on“EE-168.”
The CLKBUF signal is an output signal, which is a buffered version of the input clock. This signal is particularly useful in
Ethernet applications to limit the number of required clock
sources in the system. In this type of application, a single
25 MHz or 50 MHz crystal may be applied directly to the processor. The 25 MHz or 50 MHz output of CLKBUF can then beconnected to an external Ethernet MII or RMII PHY device.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 6, the core clock (CCLK) andsystem peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable 5× to 64× multiplication
factor (bounded by specified minimum and maximum VCO
frequencies). The default multiplier is 6×, but it can be modified
by a software instruction sequence.
On-the-fly frequency changes can be done simply by writing to
the PLL_DIV register. The maximum allowed CCLK and SCLK
rates depend on the applied voltages VDDINT, VDDEXT, and
VDDMEM, and the VCO is always permitted to run up to the frequency specified by the part’s speed grade. The CLKOUT signal
Rev. E |100

50Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can bechanged dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamicallychanged by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 5. This programmable core clock capability is useful forfast core frequency modifications.
Table 5. Core Clock Ratios

Signal Name
CSEL1–0

Example Frequency Ratios
Divider Ratio (MHz)VCO/CCLK
VCO
CCLK

00

1:1

300

300

01

2:1

300

150

10

4:1

400

100

11

8:1

200

25

Page 13 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518• Boot from external SPI EEPROM or flash(BMODE = 0x3)—8-bit, 16-bit, 24-bit or 32-bit addressable devices are supported. The processor uses the PG15
GPIO signal (at SPI0SEL2) to select a single SPI
EEPROM/flash device connected to the SPI0 interface;then submits a read command and successive address bytes(0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device
is detected. Pull-up resistors are required on the SSEL andMISO signals. By default, a value of 0x85 is written to the
SPI0_BAUD register.

The maximum CCLK frequency not only depends on the part’s
speed grade (see Page 63), it also depends on the applied VDDINT
voltage. See Table 9 for details. The maximal system clock rate
(SCLK) depends on the chip package and the applied VDDINT,VDDEXT, and VDDMEM voltages (see Table 11).

BOOTING MODES
The processor has several mechanisms (listed in Table 6) for
automatically loading internal and external memory after areset. The boot mode is defined by three BMODE input bits
dedicated to this purpose. There are two categories of bootmodes. In master boot modes the processor actively loads datafrom parallel or serial memories. In slave boot modes the processor receives data from external host devices.

• Boot from SPI0 host device (BMODE = 0x4)—The processor operates in SPI slave mode and is configured to receive
the bytes of the LDR file from an SPI host (master) agent.
In the host, the HWAIT signal must be interrogated by thehost before every transmitted byte. A pull-up resistor isrequired on the SPI0SS input. A pull-down on the serial
clock may improve signal quality and booting robustness.

The boot modes listed in Table 6 provide a number of mechanisms for automatically loading the processor’s internal andexternal memories after a reset. By default, all boot modes use
the slowest meaningful configuration settings. Default settings
can be altered via the initialization code feature at boot time orby proper OTP programming at pre-boot time. The BMODE
bits of the reset configuration register, sampled during poweron resets and software-initiated resets, implement the modes
shown in Table 6.

• Boot from OTP memory (BMODE = 0x5)—This provides
a stand-alone booting method. The boot stream is loaded
from on-chip OTP memory. By default the boot stream is
expected to start from OTP page 0x40 on and can occupy
all public OTP memory up to page 0xDF. This is 2560
bytes. Since the start page is programmable the maximum
size of the boot stream can be extended to 3072 bytes.

Table 6. Booting Modes• Boot from SDRAM (BMODE = 0x6)—This is a warm bootscenario, where the boot kernel starts booting from address
0x0000 0010. The SDRAM is expected to contain a valid
boot stream and the SDRAM controller must be configuredby the OTP settings.

BMODE2–0 Description
000

Idle - No boot001

Boot from 8- or 16-bit external flash memory

010

Reserved

011

Boot from external SPI memory (EEPROM or flash)

100

Boot from SPI0 host101

Boot from OTP memory

110

Boot from SDRAM

111

Boot from UART0 Host

• Boot from UART0 host (BMODE = 0x7)—Using an autobaud handshake sequence, a boot-stream formatted
program is downloaded by the host. The host selects a bit
rate within the UART clocking capabilities.
When performing the autobaud, the UART expects a “@”(0x40) character (eight bits data, one start bit, one stop bit,no parity bit) on the RX0 signal to determine the bit rate.
The UART then replies with an acknowledgment composed of 4 bytes (0xBF—the value of UART0_DLL and
0x00—the value of UART0_DLH). The host can thendownload the boot stream. To hold off the host the Blackfin
processor signals the host with the boot host wait
(HWAIT) signal. Therefore, the host must monitor
HWAIT before every transmitted byte.

• Idle/no boot mode (BMODE = 0x0)—In this mode, theprocessor goes into idle. The idle boot mode helps recoverfrom illegal operating modes, such as when the user has
mis configured the OTP memory.
• Boot from 8-bit or 16-bit external flash memory(BMODE = 0x1)—In this mode, the boot kernel loads thefirst block header from address 0x2000 0000 and—depending on instructions containing in the header—the bootkernel performs 8-bit or 16-bit boot or starts program execution at the address provided by the header. By default, allconfiguration settings are set for the slowest device possible(3-cycle hold time, 15-cycle R/W access times, 4-cycle
setup).
The ARDY is not enabled by default, but it can be enabled
by OTP programming. Similarly, all interface behavior andtimings can be customized by OTP programming. This
includes activation of burst-mode or page-mode operation.
In this mode, all signals belonging to the asynchronousinterface are enabled at the port muxing level.

Rev. E |For each of the boot modes, a 16-byte header is first read froman external memory device. The header specifies the number ofbytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences fromthe address stored in the EVT1 register.
Prior to booting, the pre-boot routine interrogates the OTP
memory. Individual boot modes can be customized or even disabled based on OTP programming. External hardware,
especially booting hosts may watch the HWAIT signal to determine when the pre-boot has finished and the boot kernel starts

Page 14 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
the boot process. By programming OTP memory, the user can
instruct the preboot routine to also customize the PLL, theSDRAM Controller, and the Asynchronous Interface.
The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in thelater case. Bits 6-4 in the system reset configuration (SYSCR)
register can be used to bypass pre-boot routine and/or boot kernel in case of a software reset. They can also be used to simulate
a wakeup-from-hibernate boot in the software reset case.
The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to configure
the SDRAM controller or to speed up booting by managing
PLL, clock frequencies, wait states, or serial bit rates.
The boot ROM also features C-callable function entries that canbe called by the user application at run time. This enables second-stage boot or boot management schemes to be
implemented with ease.

INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding andreadability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles toa very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor(O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core
processor resources.
The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:• Seamlessly integrated DSP/MCU features are optimized forboth 8-bit and 16-bit operations.
• A multi-issue load/store modified-harvard architecture,
which supports two 16-bit MACs or four 8-bit ALUs plus
two load/store plus two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified programming model.
• Microcontroller features, such as arbitrary bit and bit-fieldmanipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user andsupervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encodedin 16 bits.

Rev. E |DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line ofsoftware and hardware development tools, including integrated
development environments (which include CrossCore® Embedded Studio and/or VisualDSP++®), evaluation products,
emulators, and a wide variety of software add-ins.

Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, anddebug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the
EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studioseamlessly integrates available software add-ins to support realtime operating systems, file systems, TCP/IP stacks, USB stacks,algorithmic software modules, and evaluation hardware board
support packages. For more information visit
www.analog.com/cces.
The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDKreal time operating system and an open source TCP/IP stack.
For more information, visit www.analog.com/visualdsp. Notethat VisualDSP++ will not support future Analog Devices
processors.

EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide rangeof EZ-KIT Lite® evaluation boards. Including the processor andkey peripherals, the evaluation board also supports on-chipemulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders®, which aredaughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.

EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board flash device to store user-specific boot code,
enabling standalone operation. With the full version of CrossCore Embedded Studio or VisualDSP++ installed (soldseparately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices
processors.

Page 15 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
Software Add-Ins for CrossCore Embedded StudioAnalog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.

Board Support Packages for Evaluation Hardware
Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download
area of the product web page.

For details on target board design issues including mechanicallayout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices
JTAG Emulation Technical Reference on the Analog Devices
website (www.analog.com)—use site search on “EE-68.” This
document is updated regularly to keep pace with improvements
to emulator support.

ADDITIONAL INFORMATION
The following publications that describe ADSP-BF512/ADSP-BF514/ADSP-BF516/ADSP-BF518 processors (andrelated processors) can be accessed electronically on our
website:• Getting Started With Blackfin Processors• ADSP-BF51x Blackfin Processor Hardware Reference• Blackfin Processor Programming Reference• ADSP-BF512/BF514/BF516/BF518 Blackfin Processor
Anomaly List

Middleware Packages

RELATED SIGNAL CHAINS

Analog Devices separately offers middleware add-ins such asreal time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information see the following web
pages:

A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with theoutput of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications togather and process data or to apply system controls based on
analysis of real-time phenomena.

• www.analog.com/ucos3• www.analog.com/ucfs• www.analog.com/ucusbd• www.analog.com/lwip

Algorithmic Modules
To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These areavailable for use with both CrossCore Embedded Studio andVisualDSP++. For more information visit www.analog.com andsearch on “Blackfin software modules” or “SHARC softwaremodules”.

Analog Devices eases signal processing system development by
providing signal processing components that are designed towork together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
The Application Signal Chains page in the Circuits from the
LabTM site (www.analog.com/circuits) provides:

Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via theprocessor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports
connection of the JTAG port of the DSP to the emulator.

Rev. E |Page 16 of 63 |• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications• Drill down links for components in each chain to selection
guides and application information• Reference designs applying best practice design techniques

June 2020

ADSP-BF512/BF514/BF516/BF518
SIGNAL DESCRIPTIONS
The processors’ signal definitions are listed in Table 7. In orderto maintain maximum function and reduce package size andsignal count, some signals have dual, multiplexed functions. In
cases where signal function is reconfigurable, the default state isshown in plain text, while the alternate function is shown initalics.
All pins are three-stated during and immediately after reset,with the exception of the external memory interface, asynchronous and synchronous memory control, and the buffered XTAL
output pin (CLKBUF). On the external memory interface, thecontrol and address lines are driven high, with the exception of
CLKOUT, which toggles at the system clock rate. During hibernate all outputs are three-stated unless otherwise noted inTable 7.
All I/O signals have their input buffers disabled with the exception of the signals noted in the data sheet that need pull-ups orpull downs if unused.

The SDA (serial data) and SCL (serial clock) pins/balls are open
drain and therefore require a pullup resistor. Consult version
2.1 of the I2C specification for the proper resistor value.
It is strongly advised to use the available IBIS models to ensurethat a given board design meets overshoot/undershoot and signal integrity requirements. If no IBIS simulation is performed, it
is strongly recommended to add series resistor terminations for
all Driver Types A, C and D. The termination resistors shouldbe placed near the processor to reduce transients and improvesignal integrity. The resistance value, typically 33 Ω or 47 Ω,should be chosen to match the average board trace impedance.
Additionally, adding a parallel termination to CLKOUT may
prove useful in further enhancing signal integrity. Be sure toverify overshoot/undershoot and signal integrity specifications
on actual hardware.

Table 7. Signal Descriptions
Type Function

DriverType1

ADDR19–1

O

Address Bus

A

DATA15–0

I/O

Data BusA

Signal Name
EBIU

ABE1–0/SDQM1–0

O

Byte Enable or Data Mask

A

AMS1–0O

Asynchronous Memory Bank Selects (Require pull-ups if hibernate is used)

A

ARE

O

Asynchronous Memory Read Enable

A

AWE

O

Asynchronous Memory Write Enable

A

SRAS

O

SDRAM Row Address Strobe

A

SCAS

O

SDRAM Column Address Strobe

A

SWE

O

SDRAM Write Enable

A

SCKE

O

SDRAM Clock Enable (Requires a pull-down if hibernate with SDRAM self-refresh A
is used)

CLKOUTOSDRAM Clock Output

B

SA10

O

SDRAM A10 Signal

A

SMS

O

SDRAM Bank SelectA

PF0/ETxD2/PPI D0/SPI1SEL2/TACLK6I/O

GPIO/Ethernet MII Transmit D2/PPI Data 0/SPI1 Slave Select 2/Timer6 Alternate
Clock

C

PF1/ERxD2/PPI D1/PWM AH/TACLK7I/O

GPIO/Ethernet MII Receive D2/PPI Data 1/PWM AH Output/Timer7 Alternate Clock C

PF2/ETxD3/PPI D2/PWM AL

I/OGPIO/Ethernet Transmit D3/PPI Data 2/PWM AL Output

PF3/ERxD3/PPI D3/PWM BH/TACLK0I/O

GPIO/Ethernet MII Data Receive D3/PPI Data 3/PWM BH Output/Timer0 Alternate C
Clock

PF4/ERxCLK/PPI D4/PWM BL/TACLK1I/O

GPIO/Ethernet MII Receive Clock/PPI Data 4/PWM BL Out/Timer1 Alternate CLKC

PF5/ERxDV/PPI D5/PWM CH/TACI0I/O

GPIO/Ethernet MII Receive Data Valid/PPI Data 5/PWM CH Out/Timer0 Alternate Capture InputC

PF6/COL/PPI D6/PWM CL/TACI1I/O

GPIO/Ethernet MII Collision/PPI Data 6/PWM CL Out/Timer1 Alternate Capture Input C

PF7/SPI0SEL1/PPI D7/PWMSYNC

I/O

GPIO/SPI0 Slave Select 1/PPI Data 7/PWM Sync

Port F: GPIO and Multiplexed Peripherals

Rev. E |Page 17 of 63 |June 2020CCADSP-BF512/BF514/BF516/BF518
Table 7. Signal Descriptions (Continued)
Signal Name

Type Function

Driver
Type1

PF8/MDC/PPI D8/SPI1SEL4

I/O

GPIO/Ethernet Management Channel Clock/PPI Data 8/SPI1 Slave Select 4C

PF9/MDIO/PPI D9/TMR2

I/O

GPIO/Ethernet Management Channel Serial Data/PPI Data 9/Timer 2

C

PF10/ETxD0/PPI D10/TMR3

I/O

GPIO/Ethernet MII or RMII Transmit D0/PPI Data 10/Timer 3

C

PF11/ERxD0/PPI D11/PWM AH/TACI3I/O

GPIO/Ethernet MII Receive D0/PPI Data 11/PWM AH output/Timer3 Alternate Capture Input

C

PF12/ETxD1/PPI D12/PWM AL

I/OGPIO/Ethernet MII Transmit D1/PPI Data 12/PWM AL Output

C

PF13/ERxD1/PPI D13/PWM BH

I/O

GPIO/Ethernet MII or RMII Receive D1/PPI Data 13/PWM BH Output

C

PF14/ETxEN/PPI D14/PWM BL

I/OGPIO/Ethernet MII Transmit Enable/PPI Data 14/PWM BL Out

CPF152/RMII PHYINT/PPI D15/PWM_SYNCA

I/O

GPIO/Ethernet MII PHY Interrupt/PPI Data 15/Alternate PWM Sync

C

PG0/MIICRS/RMIICRS/HWAIT 3/SPI1SEL3

I/O

GPIO/Ethernet MII or RMII Carrier Sense or RMII Data Valid/HWAIT/SPI1 Slave Select3 C

PG1/ERxER/DMAR1/PWM CH

I/O

GPIO/Ethernet MII or RMII Receive Error/DMA Req 1/PWM CH Out

CGPIO/Ethernet MII or RMII Reference Clock/DMA Req 0/PWM CL Out

CPort G: GPIO and Multiplexed Peripherals

PG2/MIITxCLK/RMIIREF_CLK/DMAR0/PWM CL I/O
PG3/DR0PRI/RSI_DATA0/SPI0SEL5/TACLK3I/O

GPIO/SPORT0 Primary Rx Data/RSI Data 0/SPI0 Slave Select 5/Timer3 Alternate CLK C

PG4/RSCLK0/RSI_DATA1/TMR5/TACI5I/O

GPIO/SPORT0 Rx Clock/RSI Data 1/Timer 5/Timer5 Alternate Capture Input

D

PG5/RFS0/RSI_DATA2/PPICLK/TMRCLKI/OGPIO/SPORT0 Rx Frame Sync/RSI Data 2/PPI Clock/External Timer ReferenceC

PG6/TFS0/RSI_DATA3/TMR0/PPIFS1I/O

GPIO/SPORT0 Tx Frame Sync/RSI Data 3/Timer0/PPI Frame Sync1

C

PG7/DT0PRI/RSI_CMD/TMR1/PPIFS2I/O

GPIO/SPORT0 Tx Primary Data/RSI Command/Timer 1/PPI Frame Sync2

C

PG8/TSCLK0/RSI_CLK/TMR6/TACI6I/O

GPIO/SPORT0 Tx Clock/RSI Clock/Timer 6/Timer6 Alternate Capture InputD

PG9/DT0SEC/UART0TX/TMR4I/O

GPIO/SPORT0 Secondary Tx Data/UART0 Transmit/Timer 4C

PG10/DR0SEC/UART0RX/TACI4I/O

GPIO/SPORT0 Secondary Rx Data/UART0 Receive/Timer4 Alternate Capture Input C

PG11/SPI0SS/AMS2/SPI1SEL5/TACLK2I/O

GPIO/SPI0 Slave Device Select/Asynchronous Memory Bank Select 2/SPI1 Slave
Select 5/Timer2 Alternate CLKC

PG12/SPI0SCK/PPICLK/TMRCLK/PTP_PPS

I/O

GPIO/SPI0 Clock/PPI Clock/External Timer Reference/PTP Pulse Per Second Out

D

PG13/SPI0MISO4/TMR0/PPIFS1/PTP_CLKOUT

I/O

GPIO/SPI0 Master In Slave Out/Timer0/PPI Frame Sync1/PTP Clock OutC

PG14/SPI0MOSI/TMR1/PPIFS2/PWM TRIP
/PTP_AUXIN

I/O

GPIO/SPI0 Master Out Slave In/Timer 1/PPI Frame Sync2/PWM Trip/PTP Auxiliary
Snapshot Trigger Input

C

PG15/SPI0SEL2/PPIFS3/AMS3I/O

GPIO/SPI0 Slave Select 2/PPI Frame Sync3/Asynchronous Memory Bank Select 3C

PH0/DR1PRI/SPI1SS/RSI_DATA4I/OGPIO/SPORT1 Primary Rx Data/SPI1 Device Select/RSI Data 4C

PH1/RFS1/SPI1MISO/RSI_DATA5I/OGPIO/SPORT1 Rx Frame Sync/SPI1 Master In Slave Out/RSI Data 5C

PH2/RSCLK1/SPI1SCK/RSI DATA6I/OGPIO/SPORT1 Rx Clock/SPI1 Clock/RSI Data 6

D

Port H: GPIO and Multiplexed Peripherals

PH3/DT1PRI/SPI1MOSI/RSI DATA7I/OGPIO/SPORT1 Primary Tx Data/SPI1 Master Out Slave In/RSI Data 7C

PH4/TFS1/AOE/SPI0SEL3/CUD

I/O

GPIO/SPORT1 Tx Frame Sync/Asynchronous Memory Output Enable/SPI0 Slave
Select 3/Counter Up Direction

C

PH5/TSCLK1/ARDY/PTP_EXT_CLKIN/CDG

I/O

GPIO/SPORT1 Tx Clock/Asynchronous Memory Hardware Ready Control/
External Clock for PTP TSYNC/Counter Down GateD

PH6/DT1SEC/UART1TX/SPI1SEL1/CZM

I/O

GPIO/SPORT1 Secondary Tx Data/UART1 Transmit/SPI1 Slave Select 1/Counter Zero Marker

C

PH7/DR1SEC/UART1RX/TMR7/TACI2I/O

GPIO/SPORT1 Secondary Rx Data/UART1 Receive/Timer 7/Timer2 Alternate Clock C
Input

Rev. E |Page 18 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
Table 7. Signal Descriptions (Continued)
Signal Name

Driver
Type1

Type Function

Port J
PJ0:SCLE
I/O 5V TWI Serial Clock (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I2C specification for the proper resistor value.)

PJ1:SDAE
I/O 5V TWI Serial Data (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I2C specification for the proper resistor value.)

Real Time Clock
RTXII

RTC Crystal Input (This ball should be pulled low when not used.)

RTXO

O

RTC Crystal Output (Does not three-state during hibernate)

TCK

I

JTAG ClockTDOOJTAG Serial Data Out

TDII

JTAG Serial Data In

JTAG Port
C

TMS

I

JTAG Mode Select

TRST

I

JTAG Reset (This signal should be pulled low if the JTAG port is not used.)

EMU

O

Emulation Output

C

Clock
CLKIN

I

Clock/Crystal Input

XTAL

O

Crystal Output (If CLKBUF is enabled, does not three-state during hibernate)

CLKBUFO

Buffered XTAL Output (If enabled, does not three-state during hibernate)

RESET

I

Reset

NMI

I

Non-maskable Interrupt (This signal should be pulled high when not used.)

BMODE2-0

I

Boot Mode Strap 2-0

PG

IPower Good (This signal should be pulled low when not used.)

EXT_WAKEO

Wake up Indication (Does not three-state during hibernate)

C

Mode Controls

Voltage Regulation Interface
C

ALL SUPPLIES MUST BE POWERED See Operating Conditions.

Power Supplies
VDDEXTP

I/O Power Supply

VDDINTPInternal Power Supply

VDDRTCPReal Time Clock Power Supply

VDDMEMP

MEM Power Supply

VPPOTPPOTP Programming Voltage

VDDOTPPOTP Power Supply

GND

G

Ground for All Supplies

1

See Output Drive Currents for more information about each driver type.
When driven low, the PF15 signal can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as PHYINT. If the pin/ballis used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the signal with a resistor.
3
Boot host wait is a GPIO signal toggled by the boot kernel. The mandatory external pull-up/pull-down resistor defines the signal polarity.
4
A pull-up resistor is required for the boot from external SPI EEPROM or flash (BMODE = 0x3).
2Rev. E |Page 19 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
SPECIFICATIONSNote that component specifications are subject to change
without notice.

OPERATING CONDITIONSParameter
VDDINT Internal Supply Voltage
Internal Supply Voltage
Internal Supply Voltage
1, 2
VDDEXT External Supply Voltage
External Supply Voltage
External Supply Voltage
3
VDDMEM MEM Supply Voltage
MEM Supply Voltage
MEM Supply Voltage
4
VDDRTC RTC Power Supply Voltage
VDDOTP1 OTP Supply Voltage
VPPOTP OTP Programming Voltage
For Reads1
For Writes5
VIH
High Level Input Voltage6, 7High Level Input Voltage6, 8High Level Input Voltage6, 8
VIHTWI
High Level Input Voltage
Low Level Input Voltage6, 7
VIL
Low Level Input Voltage6, 8
Low Level Input Voltage6, 8
VILTWI
Low Level Input Voltage
Junction Temperature
Junction Temperature
Junction Temperature
Junction Temperature

Conditions
Industrial Models
Commercial Models
Automotive Models
1.8 V I/O, Nonautomotive Models
2.5 V I/O, Nonautomotive Models
3.3 V I/O, All Models
1.8 V I/O, Nonautomotive Models
2.5 V I/O, Nonautomotive Models
3.3 V I/O, All Models

Min
1.14
1.10
1.33
1.7
2.25
3.0
1.7
2.25
3.0
2.25
2.25

Nominal

1.8
2.5
3.3
1.8
2.5
3.3
2.5

2.25
2.5
6.9
7.0
1.2
1.7
2
0.7 × VBUSTWIVDDEXT/VDDMEM = 1.90 V
VDDEXT/VDDMEM = 2.75 V
VDDEXT/VDDMEM = 3.6 V
VDDEXT = 1.90 V/2.75 V/3.6 V
VDDEXT/VDDMEM = 1.7 V
VDDEXT/VDDMEM = 2.25 V
VDDEXT/VDDMEM = 3.0 V
VDDEXT = Minimum
168-Ball CSP_BGA @ TAMBIENT = 0°C to +70°C
0168-Ball CSP_BGA @ TAMBIENT = –40°C to +85°C –40
176-Lead LQFP_EP @ TAMBIENT = 0°C to +70°C 0
176-Lead LQFP_EP @ TAMBIENT = –40°C to +85°C –40

1

Max
1.47
1.47
1.47
1.9
2.75
3.6
1.9
2.75
3.6
3.6
2.75

Unit
V
V
V
V
V
V
V
V
V
V
V

2.75
7.1

V
V
V
V
V
V
V
V
V
V
°C
°C
°C
°C

VBUSTWI9
0.6
0.7
0.8
0.3 × VBUSTWI10
+95
+105
+95
+105

Must remain powered (even if the associated function is not used).
VDDEXT is the supply to the GPIO.
3
Pins/balls that use VDDMEM are DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AMS1–0, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These pins/balls are not tolerant
to voltages higher than VDDMEM. When using any of the asynchronous memory signals AMS3–2, ARDY, or AOE VDDMEM and VDDEXT must be shorted externally.
4
If not used, power with VDDEXT.
5The VPPOTP voltage for writes must only be applied when programming OTP memory. There is a finite amount of cumulative time that this voltage may be applied (dependent
on voltage and junction temperature) over the lifetime of the part.
6
Parameter value applies to all input and bidirectional pins/balls except SDA and SCL.
7
Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF51x processors are
2.5 V tolerant (always accept up to 2.7 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage.
8
Bidirectional pins/balls (PF15–0, PG15–0, PH7–0) and input pins/balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF51x are
3.3 V tolerant (always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage.
9
The VIHTWI min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See VBUSTWI min and max values in Table 8.
10
SDA and SCL are pulled up to VBUSTWI. See Table 8.
2

Rev. E |Page 20 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
Table 8 shows settings for TWI_DT in the NONGPIO_DRIVE
register. Set this register prior to using the TWI port.
Table 8. TWI_DT Field Selections and VDDEXT/VBUSTWITWI_DT
000 (default)
001
010
011
100
101
110
111 (reserved)

VDDEXT Nominal
3.3
1.8
2.5
1.8
3.3
1.8
2.5
—

VBUSTWI Minimum
2.97
1.7
2.97
2.97
4.5
2.25
2.25
—

VBUSTWI Nominal
3.3
1.8
3.3
3.3
5
2.5
2.5
—

VBUSTWI Maximum
3.63
1.98
3.63
3.63
5.5
2.75
2.75
—

Unit
V
V
V
V
V
V
V
—

Clock Related Operating Conditions
Table 9 describes the timing requirements for the processor
clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as
not to exceed the maximum core clock and system clock.
Table 10 describes phase-locked loop operating conditions.
Table 9. Core Clock (CCLK) Requirements
Parameter
fCCLK

NominalVoltage Setting
Core Clock Frequency (VDDINT =1.33 V Minimum, All Models)
1.400 V
Core Clock Frequency (VDDINT =1.23 V Minimum, Industrial/Commercial Models)
1.300 V
Core Clock Frequency (VDDINT = 1.14 V Minimum, Industrial Models Only)
1.200 V
Core Clock Frequency (VDDINT = 1.10 V Minimum, Commercial Models Only)
1.150 V

Maximum
400
300
200
200

Unit
MHz
MHz
MHz
MHz

Table 10. Phase-Locked Loop Operating Conditions
Parameter
fVCO

1

Min

Max

Unit
1

MHz
MHz

Voltage Controlled Oscillator (VCO) Frequency(Commercial/Industrial Models)

72

Instruction Rate

Voltage Controlled Oscillator (VCO) Frequency(Automotive Models)

84

Instruction Rate1

For more information, see Ordering Guide.

Table 11. SCLK Conditions

Parameter1

VDDEXT/VDDMEM
1.8 V Nominal

VDDEXT/VDDMEM
2.5 V or 3.3 V Nominal

Max

Max

Unit

fSCLK

CLKOUT/SCLK Frequency (VDDINT ≥ 1.230 V
Minimum)

80

100

MHz

fSCLK

CLKOUT/SCLK Frequency (VDDINT < 1.230 V)

80

80

MHz

1

fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 24.

Rev. E |Page 21 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
ELECTRICAL CHARACTERISTICS
Parameter

Conditions

Min

High Level Output Voltage

VDDEXT /VDDMEM = 1.7 V,
IOH = –0.5 mA

1.35

V

High Level Output Voltage

VDDEXT /VDDMEM = 2.25 V,
IOH = –0.5 mA

2

VHigh Level Output Voltage

VDDEXT /VDDMEM = 3.0 V,
IOH = –0.5 mA

2.4

V

VOL

Low Level Output Voltage

VDDEXT /VDDMEM = 1.7/2.25/3.0 V,
IOL = 2.0 mA

0.4

V

IIH1

High Level Input Current

VDDEXT /VDDMEM =3.6 V, VIN = 3.6 V

10μA

Low Level Input Current

VDDEXT /VDDMEM =3.6 V, VIN = 0 V

10μAHigh Level Input Current JTAG VDDEXT = 3.6 V, VIN = 3.6 V

75

μA

Three-State Leakage Current

VDDEXT /VDDMEM= 3.6 V, VIN = 3.6 V

10

μA

VOH

IIL1
IIHP

2
3

IOZH

IOZHTWI

4

TypicalMax

Unit

Three-State Leakage Current

VDDEXT =3.0 V, VIN = 5.5 V

10

μA

IOZL3

Three-State Leakage Current

VDDEXT /VDDMEM= 3.6 V, VIN = 0 V

10μA

CIN5, 6

Input CapacitancefIN = 1 MHz, TAMBIENT = 25°C,
VIN = 2.5 V

8pF

CINTWI4, 6

Input CapacitancefIN = 1 MHz, TAMBIENT = 25°C,
VIN = 2.5 V

15pF

IDDDEEPSLEEP7VDDINT Current in Deep Sleep
Mode

VDDINT = 1.3 V, fCCLK = 0 MHz,fSCLK = 0 MHz, TJ = 25°C,
ASF = 0.00

2.1

mA

IDDSLEEPVDDINT Current in Sleep ModeVDDINT = 1.3 V, fSCLK = 25 MHz,
TJ = 25°C

5.5mA

IDD-IDLE

VDDINT Current in Idle

VDDINT = 1.3 V, fCCLK = 50 MHz,fSCLK = 25 MHz, TJ = 25°C,
ASF = 0.41

12mA

IDD-TYP

VDDINT Current

VDDINT = 1.3 V, fCCLK = 300 MHz,fSCLK = 25 MHz, TJ = 25°C,
ASF = 1.00

77mA

IDD-TYP

VDDINT Current

VDDINT = 1.4 V, fCCLK = 400 MHz,fSCLK = 25 MHz, TJ = 25°C,
ASF = 1.00

108

mA

IDDHIBERNATE8Hibernate State Current

VDDEXT =VDDMEM =VDDRTC = 3.3 V
VDDOTP =VPPOTP =2.5 V, TJ = 25°C,
CLKIN = 0 MHz

40μA

IDDRTCVDDRTC Current

VDDRTC = 3.3 V, TJ = 25°C

20μA

VDDINT Current in Sleep ModefCCLK = 0 MHz, fSCLK > 0 MHz

Table 13 +(0.20 × VDDINT × fSCLK)mA10IDDDEEPSLEEP8, 10 VDDINT Current in Deep Sleep
Mode

fCCLK = 0 MHz, fSCLK = 0 MHz

Table 13mA

IDDINT10, 11

fCCLK > 0 MHz, fSCLK  0 MHz

Table 13 +(Table 14 × ASF) +(0.20 × VDDINT × fSCLK)mA

IDDSLEEP8, 9

VDDINT Current

Rev. E |Page 22 of 63 |5June 2020

ADSP-BF512/BF514/BF516/BF518
Parameter

Conditions

Min

TypicalMax

Unit

IDDOTP

VDDOTP Current

VDDOTP = 2.5 V, TJ = 25°C,
OTP Memory Read

2mA

IDDOTP

VDDOTP Current

VDDOTP = 2.5 V, TJ = 25°C,
OTP Memory Write

2mA

IPPOTPVPPOTP Current

VPPOTP = 2.5 V, TJ = 25°C,
OTP Memory Read

100

μA

IPPOTPVPPOTP Current

VPPOTP = Table 17 V, TJ = 25°C,
OTP Memory Write

3

mA

1

Applies to input balls.
Applies to JTAG input balls (TCK, TDI, TMS, TRST).
3
Applies to three-statable balls.
4
Applies to bidirectional balls SCL and SDA.
5
Applies to all signal balls, except SCL and SDA.
6
Guaranteed, but not tested.
7
See the ADSP-BF51x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.
8
Includes current on VDDEXT, VDDMEM, VDDOTP, and VPPOTP supplies. Clock inputs are tied high or low.
9
Guaranteed maximum specifications.
10
Unit for VDDINT is V (Volts). Unit for fSCLK is MHz.
11
See Table 12 for the list of IDDINT power vectors covered.
2

Total Power Dissipation

The ASF is combined with the CCLK Frequency and VDDINT
dependent data in Table 14 to calculate this part. The second
part is due to transistor switching in the system clock (SCLK)
domain, which is included in the IDDINT specification equation.

Total power dissipation has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and processor activity. Electrical Characteristics shows the current
dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP specifies
static power dissipation as a function of voltage (VDDINT) andtemperature (see Table 13), and IDDINT specifies the total power
specification for the listed test conditions, including the
dynamic component as a function of voltage (VDDINT) and frequency (Table 14).
There are two parts to the dynamic component. The first part isdue to transistor switching in the core clock (CCLK) domain.
This part is subject to an Activity Scaling Factor (ASF) which
represents application code running on the processor core andL1 memories (Table 12).

Table 12. Activity Scaling Factors (ASF)1
IDDINT Power Vector
IDD-PEAK
IDD-HIGH
IDD-TYP
IDD-APPIDD-NOP
IDD-IDLE
1

Activity Scaling Factor (ASF)
1.29
1.25
1.00
0.85
0.70
0.41

See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors(EE-297). The power vector information also applies to the ADSP-BF51x
processors.

Table 13. Static Current—IDD-DEEPSLEEP (mA)1

TJ (°C)
–40
–20
0
25
40
55
70

1.10 V
0.9
1.0
1.2
1.8
2.4
3.3
4.6

1.15 V
1.0
1.1
1.3
1.9
2.6
3.5
5.0

1.20 V
1.0
1.2
1.4
2.1
2.8
3.8
5.4

1.25 V
1.1
1.3
1.6
2.3
3.0
4.3
6.0

Rev. E |Voltage (VDDINT)11.30 V
1.35 V
1.1
1.2
1.4
1.6
1.8
2.0
2.5
2.8
3.3
3.7
4.6
5.0
6.4
7.0

Page 23 of 63 |June 2020

1.40 V
1.3
1.7
2.2
3.1
4.0
5.5
7.7

1.45 V
1.7
1.9
2.3
3.3
4.4
6.1
8.4

1.50 V
1.9
2.0
2.5
3.7
4.9
6.7
9.2

ADSP-BF512/BF514/BF516/BF518
Table 13. Static Current—IDD-DEEPSLEEP (mA) (Continued)
1

TJ (°C)
85
100
105
1

1.10 V
6.5
9.2
10.3

1.15 V
7.1
10.0
11.1

1.20 V
7.7
10.8
12.1

1.25 V
8.3
11.7
13.1

Voltage (VDDINT)11.30 V
1.35 V
9.1
9.9
12.7
13.7
14.2
15.3

1.40 V
10.8
15.0
16.6

1.45 V
11.8
16.1
18.0

1.50 V
12.8
17.5
19.4

1.40 V
102.1
90.1
78.1
66.1
54.1
42.1
30.1

1.45 V
106.5
94.0
81.5
69.0
56.5
44.0
31.5

1.50 V
111.0
98.0
85.0
71.9
58.9
45.9
33.0

Valid frequency and voltage ranges are model-specific. See Operating Conditions.

Table 14. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)1fCCLK(MHz)2
400
350
300
250
200
150
100
1
2

1.10 V
N/A
N/A
N/A
N/A
N/A
31.1
22.0

1.15 V
N/A
N/A
N/A
N/A
42.5
32.9
23.4

1.20 V
N/A
N/A
N/A
N/A
44.7
34.7
24.7

1.25 V
N/A
N/A
N/A
57.5
47.0
36.5
26.0

Voltage (VDDINT)2
1.30 V
1.35 V
N/A
N/A
N/A
86.2
71.4
74.7
60.4
63.2
49.4
51.7
38.4
40.2
27.4
28.7

The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics.
Valid frequency and voltage ranges are model-specific. See Operating Conditions.

Rev. E |Page 24 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
ABSOLUTE MAXIMUM RATINGS

Table 17. Maximum OTP Memory Programming TimeStresses greater than those listed in Table 15 may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Table 15. Absolute Maximum Ratings

Temperature
VPPOTP
Voltage (V)

25°C

85°C

110°C

6.9

6000 sec

100 sec

25 sec7.0

2400 sec

44 sec12 sec7.11000 sec

18 sec

4.5 sec

Table 18 and Table 19 specify the maximum total source/sink(IOH/IOL) current for a group of pins. Permanent damage canoccur if this value is exceeded. To understand this specification,
if pins PF9, PF8, PF7, PF6, and PF5 from Group 1 in Table 19
table were sourcing or sinking 2 mA each, the total current for
those pins would be 10 mA. This would allow up to 70 mA totalthat could be sourced or sunk by the remaining pins in thegroup without damaging the device. Note that the VOH and VOL
specifications have separate per-pin maximum current requirements as shown in the Electrical Characteristics table.

Parameter

RatingInternal Supply Voltage (VDDINT)–0.3 V to +1.50 V

External (I/O) Supply Voltage(VDDEXT/VDDMEM)–0.3 V to +3.8 V

Input Voltage1, 2–0.5 V to +3.6 V

Input Voltage1, 3–0.5 V to +5.5 V

Output Voltage Swing–0.5 V to
VDDEXT/VDDMEM +0.5 V

IOH/IOL Current per Pin Group4

80 mA (max)Table 18. Total Current Pin Groups–VDDMEM Groups

Storage Temperature Range–65°C to +150°C

Junction Temperature While biased+110°C

Group
1
2
3
4
5
6
7
8

1

Applies to 100% transient duty cycle. For other duty cycles see Table 16.
Applies only when VDDEXT is within specifications. When VDDEXT is outside specifications, the range is VDDEXT ± 0.2.
3
Applies to signals SCL, SDA.
4
For more information, see the information preceding Table 18 and Table 19.
2

Table 16. Maximum Duty Cycle for Input Transient Voltage1
VIN Min (V)2

VIN Max (V)2

Maximum Duty Cycle3

–0.50

+3.80

100%

–0.70

+4.00

40%

–0.80

+4.10

25%

–0.90

+4.20

15%

–1.00

+4.30

10%

Pins in GroupDATA15, DATA14, DATA13, DATA12, DATA11, DATA10DATA9, DATA8, DATA7, DATA6, DATA5, DATA4
DATA3, DATA2, DATA1, DATA0, ADDR19, ADDR18
ADDR17, ADDR16, ADDR15, ADDR14, ADDR13
ADDR12, ADDR11, ADDR10, ADDR9, ADDR8, ADDR7
ADDR6, ADDR5, ADDR4, ADDR3, ADDR2, ADDR1
ABE1, ABE0, SA10, SWE, SCAS, SRAS
SMS, SCKE, AMS1, ARE, AWE, AMS0, CLKOUT

Table 19. Total Current Pin Groups–VDDEXT Groups

1

Applies to all signal pins/balls with the exception of CLKIN, XTAL.
2
The individual values cannot be combined for analysis of a single instance ofovershoot or undershoot. The worst case observed value must fall within one ofthe voltages specified and the total duration of the overshoot or undershoot(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
3
Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. It is equivalent to the measured duration of a single instance ofovershoot or undershoot as a percentage of the period of occurrence.

Group
1
2
3
4
5
6
7

Pins in Group
PF9, PF8, PF7, PF6, PF5, PF4, PF3, PF2
PF1, PF0, PG15, PG14, PG13, PG12, PG11, PG10
PG9, PG8, PG7, PG6, PG5, PG4, PG3, PG2, BMODE0,BMODE1, BMODE2
PG1, PG0, TDO, EMU, TDI, TCK, TRST, TMSRESET, NMI, CLKBUF
PH7, PH6, PH5, PH4, PH3, PH2, PH1, PH0
PF15, PF14, PF13, PF12, PF11, SDA, SCL, PF10ESD SENSITIVITY
When programming OTP memory on the ADSP-BF51x processor, the VPPOTP pin/ball must be set to the write value specified in
the Operating Conditions. There is a finite amount of cumulative time that the write voltage may be applied (dependent on
voltage and junction temperature) to VPPOTP over the lifetime ofthe part. Therefore, maximum OTP memory programmingtime for the processor is shown in Table 17.

Rev. E |Page 25 of 63 |ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.

June 2020

ADSP-BF512/BF514/BF516/BF518
TIMING SPECIFICATIONSClock and Reset Timing
Table 20 and Figure 7 describe clock and reset operations. Per
the CCLK and SCLK timing specifications in Table 9, Table 10,
and Table 11, combinations of CLKIN and clock multipliersmust not select core/peripheral clocks in excess of the processor’s speed grade.
Table 20. Clock and Reset Timing
Parameter
Min
Timing Requirements
CLKIN Frequency (Commercial/Industrial Models1, 2, 3, 4 12
fCKIN
fCKIN
CLKIN Frequency (Automotive Models)1, 2, 3, 4
14
1
tCKINL
CLKIN Low Pulse
10
tCKINH
CLKIN High Pulse1
10tWRST
RESET Asserted Pulse Width Low5
11 × tCKIN
Switching CharacteristictBUFDLAY
CLKIN to CLKBUF Delay

Max

Unit

50
50

MHz
MHz
ns
ns
ns

11

ns

1

Applies to PLL bypass mode and PLL nonbypass mode.
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 9 through Table 11.
3
The tCKIN period (see Figure 7) equals 1/fCKIN.
4
If the DF bit in the PLL_CTL register is set, the minimum fCKIN specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.
5
Applies after power-up sequence is complete. See Table 21 and Figure 8 for power-up reset timing.
2

tCKIN
CLKIN

tCKINLtBUFDLAY

tCKINHCLKBUF

tWRST
RESET

Figure 7. Clock and Reset Timing

Rev. E |Page 26 of 63 |June 2020

tBUFDLAYADSP-BF512/BF514/BF516/BF518
Table 21. Power-Up Reset Timing
Parameter

Min

Max

Unit

Timing Requirements
tRST_IN_PWR

RESET Deasserted after the VDDINT, VDDEXT, VDDRTC, VDDMEM, VDDOTP, and CLKIN Pins are
Stable and Within Specification
tRST_IN_PWR
RESET

CLKIN
V

DD_SUPPLIES

Figure 8. Power-Up Reset Timing

Rev. E |Page 27 of 63 |June 2020

3500 × tCKIN

ns

ADSP-BF512/BF514/BF516/BF518
Asynchronous Memory Read Cycle Timing
Table 22. Asynchronous Memory Read Cycle Timing
VDDMEM
1.8V Nominal
Parameter

Min

Max

VDDMEM
2.5 V/3.3V Nominal
Min

Max

Unit

Timing RequirementstSDAT

DATA15–0 Setup Before CLKOUT

2.1

2.1

ns

tHDAT
tSARDYDATA15–0 Hold After CLKOUT

1.2

0.8

ns

ARDY Setup Before CLKOUT

4

4

ns

tHARDYARDY Hold After CLKOUT

0.2

0.2

ns

Switching Characteristics
tDO

Output Delay After CLKOUT1

tHO

1

1

Output Hold After CLKOUT

6

6

0.8

0.8

ns

Output pins/balls include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.

SETUP
2 CYCLESPROGRAMMED READACCESS 4 CYCLESACCESS EXTENDED
3 CYCLESHOLD
1 CYCLE

CLKOUT

tDO

tHO

AMSx

ABE1–0ADDR19–1

AOE

tDO

tHO

ARE

tSARDYtHARDYARDYtSARDYtHARDYDATA 15–0

Figure 9. Asynchronous Memory Read Cycle Timing

Rev. E |Page 28 of 63 |June 2020

tSDAT
tHDAT

ns

ADSP-BF512/BF514/BF516/BF518
Asynchronous Memory Write Cycle Timing
Table 23. Asynchronous Memory Write Cycle Timing
Parameter

Min

Max

Unit

Timing Requirements
tSARDYARDY Setup Before CLKOUT

4

ns

tHARDYARDY Hold After CLKOUT

0.2

ns

Switching Characteristics
tDDAT

DATA15–0 Disable After CLKOUT

tENDATDATA15–0 Enable After CLKOUT

0

1

tDO

Output Delay After CLKOUT

tHO

Output Hold After CLKOUT 1

1

6

Output pins/balls include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
PROGRAMMEDWRITEACCESSACCESSEXTEND HOLD
2 CYCLES
1 CYCLE 1 CYCLE

SETUP
2 CYCLES
CLKOUT

tDO

tHO

AMSx

ABE1–0ADDR19–1

tHO

tDO
AWE

tSARDYtHARDYARDYtENDATns
6

0.8

tSARDYtHARDYtDDATDATA 15–0

Figure 10. Asynchronous Memory Write Cycle Timing

Rev. E |Page 29 of 63 |June 2020

ns
ns
ns

ADSP-BF512/BF514/BF516/BF518
SDRAM Interface Timing
Table 24. SDRAM Interface Timing
VDDMEM
1.8V Nominal
Parameter

Min

Max

VDDMEM
2.5 V/3.3V Nominal
Min

Max

Unit

Timing Requirements
tSSDAT

Data Setup Before CLKOUT

1.5

1.5

ns

tHSDAT

Data Hold After CLKOUT

1.3

0.8

ns

Switching CharacteristicstSCLKCLKOUT Period1

12.5

10

ns

tSCLKH

CLKOUT Width High

5

4

ns

tSCLKL

CLKOUT Width Low

5

4

ns

tDCAD

Command, Address, Data Delay After CLKOUT

tHCAD

Command, Address, Data Hold After CLKOUT2tDSDAT

Data Disable After CLKOUTtENSDAT

Data Enable After CLKOUT

1
2

2

5

4

1

1

ns

5.5

5

0

0

tSCLK
CLKOUTtHSDATtSCLKLtSCLKHDATA (IN)tENSDAT

tDCAD

tHCAD

DATA (OUT)

tDCAD

tHCAD

COMMAND,
ADDRESS(OUT)NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

Figure 11. SDRAM Interface Timing

Rev. E |Page 30 of 63 |June 2020

ns
ns

The tSCLK value is the inverse of the fSCLK specification discussed in Table 11. Package type and reduced supply voltages affect the best-case value listed here.
Command pins/balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

tSSDAT

ns

tDSDATADSP-BF512/BF514/BF516/BF518
External DMA Request Timing
Table 25 and Figure 12 describe the External DMA Request
operations.
Table 25. External DMA Request Timing1
VDDMEM/VDDEXT
2.5 V/3.3 V NominalVDDMEM/VDDEXT
1.8 V Nominal
Parameter

Min

Max

Min

Max

Unit

Timing Requirements
tDS

DMARx Asserted to CLKOUT High Setup

9

7.2

ns

tDH

CLKOUT High to DMARx Deasserted Hold Time

0

0

ns

tDMARACTDMARx Active Pulse WidthtSCLK + 1

tSCLK + 1

ns

tDMARINACT

DMARx Inactive Pulse Width

1.75 × tSCLK

1.75 × tSCLK

ns

1

Because the external DMA control pins are part of the VDDEXT power domain and the CLKOUT signal is part of the VDDMEM power domain, systems in which VDDEXT and
VDDMEM are NOT equal may require level shifting logic for correct operation.

CLKOUTtDS

tDH

DMAR0/1(ACTIVE LOW)tDMARACTtDMARINACT

DMAR0/1(ACTIVE HIGH)

Figure 12. External DMA Request Timing

Rev. E |Page 31 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
Parallel Peripheral Interface Timing
Table 26 and Figure 13 through Figure 17 and describe parallel
peripheral interface operations.
Table 26. Parallel Peripheral Interface Timing
VDDEXT
2.5 V/3.3 V Nominal

VDDEXT
1.8 V Nominal
Parameter

Min

Max

Min

Max

Unit

Timing Requirements
tPCLKW

PPI_CLK WidthtSCLK – 1.5

tSCLK – 1.5

ns

tPCLK

PPI_CLK Period

2 × tSCLK – 1.5

2 × tSCLK – 1.5

nsTiming Requirements - GP Input and Frame Capture ModestPSUD

External Frame Sync Startup Delay1

4 × tPCLK

4 × tPCLKnstSFSPE

External Frame Sync Setup Before PPI_CLK(Nonsampling Edge for Rx, Sampling Edge for Tx)

6.7

6.7

ns

tHFSPE

External Frame Sync Hold After PPI_CLK

1.75

1.75

ns

tSDRPE

Receive Data Setup Before PPI_CLK

4.1

3.5

ns

tHDRPE

Receive Data Hold After PPI_CLK

2

1.6

ns

Switching Characteristics - GP Output and Frame Capture ModestDFSPEInternal Frame Sync Delay After PPI_CLKtHOFSPEInternal Frame Sync Hold After PPI_CLK

tDDTPE

Transmit Data Delay After PPI_CLKtHDTPE

Transmit Data Hold After PPI_CLK

8

8

1.7

1.7
8.2

ns
8

2.3

1.9

1

ns
ns
ns

The PPI port is fully enabled 4 PPI clock cycles after the PAB write to the PPI port enable bit. Only after the PPI port is fully enabled are external frame syncs and data words
guaranteed to be received correctly by the PPI peripheral.

PPI_CLKtPSUD
PPI_FS1/2

Figure 13. PPI with External Frame Sync Timing
DATA SAMPLED /FRAME SYNC SAMPLEDDATA SAMPLED /FRAME SYNC SAMPLED

PPI_CLKtSFSPEtPCLKW

tHFSPEtPCLK

PPI_FS1/2

tSDRPEtHDRPEPPI_DATA

Figure 14. PPI GP Rx Mode with External Frame Sync Timing

Rev. E |Page 32 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
DATA DRIVEN /FRAME SYNC SAMPLED
PPI_CLKtSFSPEtHFSPEtPCLKWtPCLK

PPI_FS1/2

tDDTPEtHDTPEPPI_DATA

Figure 15. PPI GP Tx Mode with External Frame Sync Timing

FRAME SYNC
DRIVENDATASAMPLEDPPI_CLKtHOFSPEtDFSPEtPCLKWtPCLK

PPI_FS1/2

tSDRPEtHDRPEPPI_DATA

Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing

FRAME SYNC
DRIVENDATA
DRIVENtPCLK

PPI_CLKtHOFSPEtDFSPEtPCLKW

PPI_FS1/2

tDDTPEtHDTPEPPI_DATA

Figure 17. PPI GP Tx Mode with Internal Frame Sync Timing

Rev. E |Page 33 of 63 |June 2020

DATA
DRIVENADSP-BF512/BF514/BF516/BF518
RSI Controller Timing
Table 27 and Figure 18 describe RSI controller timing. Table 28
and Figure 19 describe RSI controller (high speed) timing.
Table 27. RSI Controller Timing
Parameter
Timing Requirements
Input Setup Time
tISU
tIH
Input Hold Time
Switching Characteristics
Clock Frequency Data Transfer Mode
fPP1
fOD
Clock Frequency Identification Mode
Clock Low TimetWL
Clock High Time
tWH
tTLH
Clock Rise Time
Clock Fall TimetTHL
Output Delay Time During Data Transfer Mode
tODLY
tODLY
Output Delay Time During Identification Mode
1
2

Min

Max

5.6
2
0
1002
10
10

Unit
ns
ns

25
400

10
10
14
50

MHz
kHz
ns
ns
ns
ns
ns
ns

tPP = 1/fPP
Specification can be 0 kHz, which means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.

VOH (MIN)

tPP
SD_CLK

tTHL

tISU

tTLH
tWL

tWH

INPUT

tODLY
OUTPUTNOTES:
1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

Figure 18. RSI Controller Timing

Rev. E |Page 34 of 63 |June 2020

tIH

VOL (MAX)ADSP-BF512/BF514/BF516/BF518
Table 28. RSI Controller Timing (High Speed Mode)
Parameter
Timing Requirements
Input Setup Time
tISU
Input Hold Time
tIH
Switching Characteristics
Clock Frequency Data Transfer ModefPP1tWL
Clock Low Time
Clock High TimetWH
Clock Rise Time
tTLH
tTHL
Clock Fall Time
Output Delay Time During Data Transfer ModetODLYOutput Hold Time
tOH
1

Min

Max

Unit

5.6
2
0
7
7

ns
ns
50

MHz
ns
ns
ns
ns
ns
ns

3
3
4
2.75

tPP = 1/fPP

VOH (MIN)

tPP
SD_CLK

tTHL

tISU

tTLH
tWL

tIH

VOL (MAX)

tWH

INPUT

tODLY

tOH

OUTPUTNOTES:
1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

Figure 19. RSI Controller Timing (High Speed Mode)Rev. E |Page 35 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
Serial Ports
Table 29 through Table 32 and Figure 20 through Figure 23
describe serial port operations.
Table 29. Serial Ports—External ClockVDDEXT
1.8V Nominal
Parameter

Min

Max

VDDEXT
2.5 V/3.3V Nominal
Min

Max

Unit

Timing Requirements
tSFSE1

TFSx/RFSx Setup Before TSCLKx/RSCLKx

3

3

ns

tHFSE1tSDRE1

TFSx/RFSx Hold After TSCLKx/RSCLKx

3

3

ns

Receive Data Setup Before RSCLKx

3

3

ns

tHDRE1

Receive Data Hold After RSCLKx

3.5

3

ns

tSCLKEWTSCLKx/RSCLKx Width

7

4.5

ns

tSCLKETSCLKx/RSCLKx Period

2 × tSCLK

2 × tSCLKns

tSUDTE2

Start-Up Delay From SPORT Enable To First External TFSx

4 × tSCLKE

4 × tSCLKE

ns

tSUDRE2

Start-Up Delay From SPORT Enable To First External RFSx

4 × tSCLKE

4 × tSCLKE

ns

Switching Characteristics
tDFSE3TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)tHOFSE3

TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated 0
TFSx/RFSx)

tDDTE3

Transmit Data Delay After TSCLKxtHDTE3

Transmit Data Hold After TSCLKx

10

10
0

ns

10
0

ns

10
0

ns
ns

1

Referenced to sample edge.
2
Verified in design but untested.
3
Referenced to drive edge.

Table 30. Serial Ports—Internal ClockVDDEXT
2.5 V/3.3V Nominal

VDDEXT
1.8V Nominal
Parameter

Min

Max

Min

Max

Unit

Timing Requirements
tSFSI1

TFSx/RFSx Setup Before TSCLKx/RSCLKx

tHFSI1tSDRI1tHDRI1

TFSx/RFSx Hold After TSCLKx/RSCLKx

–1.5

–1.5

ns

Receive Data Setup Before RSCLKx

11

9.6

ns

Receive Data Hold After RSCLKx

–1.5

–1.5

ns

11

9.6

ns

Switching Characteristics
tDFSI2TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)tHOFSI2

TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated 2
TFSx/RFSx)

tDDTI2

Transmit Data Delay After TSCLKx

2Transmit Data Hold After TSCLKx

1.8

1.5

ns

TSCLKx/RSCLKx Width

10

8

ns

tHDTI

tSCLKIW
1
2

3

3
1

3

Referenced to sample edge.
Referenced to drive edge.

Rev. E |Page 36 of 63 |June 2020

ns
ns

3

ns

ADSP-BF512/BF514/BF516/BF518
DATA RECEIVE—INTERNAL CLOCKDATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE

DRIVE EDGESAMPLE EDGESAMPLE EDGEtSCLKEtSCLKEWtSCLKIWRSCLKxRSCLKx

tDFSE

tDFSI
tHOFSItHOFSERFSx(OUTPUT)RFSx(OUTPUT)

tSFSI

tHFSI

RFSx
(INPUT)

tSFSE

tHFSE

tSDRE

tHDRE

RFSx
(INPUT)

tSDRI

tHDRI
DRx

DRx

DATA TRANSMIT—INTERNAL CLOCKDATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGESAMPLE EDGE

DRIVE EDGEtSCLKIWSAMPLE EDGEt SCLKEWTSCLKxtSCLKETSCLKxtD FSItDFSE

tHOFSItHOFSETFSx(OUTPUT)TFSx(OUTPUT)

tSFSI

tHFSI

TFSx
(INPUT)tSFSE
TFSx(INPUT)

tDDTI

tDDTE

tHDTI

tHDTE

DTx

DTx

Figure 20. Serial PortsTSCLKx(INPUT)tSUDTETFSx(INPUT)RSCLKx(INPUT)tSUDRERFSx(INPUT)
FIRST

Figure 21. Serial Port Start Up with External Clock and Frame Sync

Rev. E |Page 37 of 63 |June 2020

tHFSE

ADSP-BF512/BF514/BF516/BF518
Table 31. Serial Ports—Enable and Three-State1
Parameter

Min

Max

Unit

Switching Characteristics
tDTENE

Data Enable Delay from External TSCLKxtDDTTE

Data Disable Delay from External TSCLKxtDTENI

Data Enable Delay from Internal TSCLKxtDDTTI

Data Disable Delay from Internal TSCLKx

1

0

ns
tSCLK + 1

–2.0

nstSCLK + 1

Referenced to drive edge.

DRIVE EDGE

DRIVE EDGETSCLKxtDTENE/I

tDDTTE/I

DTx

Figure 22. Enable and Three-State

Rev. E |Page 38 of 63 |June 2020

ns
ns

ADSP-BF512/BF514/BF516/BF518
Table 32. External Late Frame Sync
VDDEXT
1.8V Nominal
Parameter

Min

Max

VDDEXT
2.5 V/3.3V Nominal
Min

Max

Unit

10

ns

Switching Characteristics
tDDTLFSE1, 2

Data Delay from Late External TFSx or External RFSx with
MCE = 1, MFD = 0

tDTENLFSE1, 2

Data Enable from Late FS or MCE = 1, MFD = 0

12
0

0

1

MCE = 1, TFSx enable and TFSx valid follow tDDTENFS and tDDTLFSE.
2
If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2 then tDDTTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFS apply.

EXTERNAL RFSx IN MULTI-CHANNEL MODESAMPLE
DRIVE
EDGE
EDGE

DRIVE
EDGE

RSCLKxRFSxtDDTLFSE
tDTENLFSE
1ST BITDTx

LATE EXTERNAL TFSx
DRIVE
EDGE

SAMPLE
EDGE

DRIVE
EDGE

TSCLKxTFSxtDDTLFSE
1ST BITDTx

Figure 23. External Late Frame Sync

Rev. E |Page 39 of 63 |June 2020

ns

ADSP-BF512/BF514/BF516/BF518
Serial Peripheral Interface (SPI) Port—Master Timing
Table 33 and Figure 24 describe SPI port master operations.
Table 33. Serial Peripheral Interface (SPI) Port—Master Timing
VDDEXT
2.5 V/3.3V Nominal

VDDEXT
1.8V Nominal
Parameter

Min

Max

Min

Max

Unit

Timing Requirements
tSSPIDM

Data Input Valid to SCK Edge (Data Input Setup)

11.6

9.6

ns

tHSPIDMSCK Sampling Edge to Data Input Invalid

–1.5

–1.5

ns

Switching Characteristics
tSDSCIMSPISELx low to First SCK Edge

2 × tSCLK –1.5

2 × tSCLK –1.5

ns

tSPICHM

Serial Clock High Period

2 × tSCLK –1.5

2 × tSCLK –1.5

ns

tSPICLM

Serial Clock Low Period

2 × tSCLK –1.5

2 × tSCLK –1.5

ns

tSPICLK

Serial Clock Period

4 × tSCLK

4 × tSCLK

ns

tHDSM

Last SCK Edge to SPISELx High

2 × tSCLK –1.5

2 × tSCLK –1.5

nstSPITDM

Sequential Transfer Delay

2 × tSCLK–1.5

tDDSPIDMSCK Edge to Data Out Valid (Data Out Delay)tHDSPIDMSCK Edge to Data Out Invalid (Data Out Hold)

2 × tSCLK –1.5
6

–1

ns
6

–1

ns

SPIxSELy(OUTPUT)tSDSCIMtSPICLMtSPICHMtSPICLKtHDSM

SPIxSCK(OUTPUT)tDDSPIDMtHDSPIDM
SPIxMOSI(OUTPUT)tSSPIDM

CPHA = 1

tHSPIDM

SPIxMISO(INPUT)tDDSPIDMtHDSPIDM
SPIxMOSI(OUTPUT)CPHA = 0

tSSPIDMtHSPIDM

SPIxMISO(INPUT)

Figure 24. Serial Peripheral Interface (SPI) Port—Master Timing

Rev. E |Page 40 of 63 |June 2020

ns

tSPITDMADSP-BF512/BF514/BF516/BF518
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 34 and Figure 25 describe SPI port slave operations.
Table 34. Serial Peripheral Interface (SPI) Port—Slave Timing
VDDEXT
2.5 V/3.3V Nominal

VDDEXT
1.8V Nominal
Parameter

Min

Max

Min

Max

Unit

Timing Requirements
tSPICHS

Serial Clock High Period

2 × tSCLK –1.5

2 × tSCLK –1.5

ns

tSPICLS
tSPICLK

Serial Clock Low Period

2 × tSCLK –1.5

2 × tSCLK –1.5

nsSerial Clock Period

4 × tSCLK –1.5

4 × tSCLK –1.5

ns

tHDS

Last SCK Edge to SPISS Not Asserted

2 × tSCLK –1.5

2 × tSCLK –1.5

nstSPITDS

Sequential Transfer Delay

2 × tSCLK –1.5

2 × tSCLK –1.5

ns

tSDSCISPISS Assertion to First SCK Edge

2 × tSCLK –1.5

2 × tSCLK –1.5

nstSSPID

Data Input Valid to SCK Edge (Data Input Setup)

1.6

1.6

ns

tHSPIDSCK Sampling Edge to Data Input Invalid

2

1.6

ns

Switching CharacteristicstDSOE

SPISS Assertion to Data Out Active

0

tDSDHISPISS Deassertion to Data High Impedance

0

tDDSPIDSCK Edge to Data Out Valid (Data Out Delay)tHDSPIDSCK Edge to Data Out Invalid (Data Out Hold)

12

0

10.3

ns

11

0

9

ns

10

ns

10
0

0

ns

SPIxSS(INPUT)tSDSCItSPICLS

tSPICHStHDStSPICLKSPIxSCK(INPUT)tDSOEtDDSPID

tDDSPIDtHDSPIDtDSDHISPIxMISO(OUTPUT)CPHA = 1

tSSPIDtHSPID

SPIxMOSI(INPUT)tDSOEtHDSPID

tDDSPIDtDSDHISPIxMISO(OUTPUT)CPHA = 0

tSSPIDtHSPID

SPIxMOSI(INPUT)

Figure 25. Serial Peripheral Interface (SPI) Port—Slave Timing

Universal Asynchronous Receiver-Transmitter(UART) Ports—Receive and Transmit Timing
The UART ports receive and transmit operations are describedin the ADSP-BF51x Hardware Reference Manual.

Rev. E |Page 41 of 63 |June 2020

tSPITDSADSP-BF512/BF514/BF516/BF518
General-Purpose Port Timing
Table 35 and Figure 26 describe general-purpose
port operations.
Table 35. General-Purpose Port Timing
VDDEXT
2.5 V/3.3V Nominal

VDDEXT
1.8V Nominal
Parameter

Min

Max

Min

Max

Unit

Timing Requirement
tWFI

General-Purpose Port Signal Input Pulse WidthtSCLK + 1

tSCLK + 1

ns

Switching CharacteristictGPOD

General-Purpose Port Signal Output Delay from CLKOUT Low 0

11

0

8.5

ns

Min

Max

Unit

12

ns

CLKOUTtGPOD
GPIO OUTPUTtWFI
GPIO INPUT

Figure 26. General-Purpose Port Timing

Timer Clock Timing
Table 36 and Figure 27 describe timer clock timing.
Table 36. Timer Clock Timing
Parameter
Switching Characteristic
tTODP

Timer Output Update Delay After PPICLK HighPPI_CLK

tTODP
TMRx OUTPUT

Figure 27. Timer Clock Timing

Rev. E |Page 42 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
Timer Cycle Timing
Table 37 and Figure 28 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and“external clock mode” and has an absolute maximum input frequency of (fSCLK/2) MHz.
Table 37. Timer Cycle Timing
VDDEXT
2.5 V/3.3V Nominal

VDDEXT
1.8V Nominal
Parameter

Min

Max

Min

Max

Unit

Timing Characteristics
tWL1

Timer Pulse Width Input Low (Measured In SCLK Cycles)

tSCLK

tSCLK

ns

1

Timer Pulse Width Input High (Measured In SCLK Cycles)

tSCLK

tSCLK

ns

Timer Input Setup Time Before CLKOUT Low

10

7

ns

Timer Input Hold Time After CLKOUT Low

–2

–2

ns

tWH

tTIS2
tTIH

2

Switching Characteristics
tHTO

Timer Pulse Width Output (Measured In SCLK Cycles)tTOD

Timer Output Update Delay After CLKOUT HightSCLK – 1.5(232–1)tSCLK
61tSCLK – 1

(232–1)tSCLK

ns

6

ns

The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
2
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.

CLKOUT

tTOD
TMRx OUTPUT

tTIS

tTIH

tHTO

TMRx INPUT

tWH,tWL

Figure 28. Timer Cycle Timing

Rev. E |Page 43 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
Up/Down Counter/Rotary Encoder Timing
Table 38. Up/Down Counter/Rotary Encoder Timing

Parameter
Timing Requirements
tWCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width
Counter Input Setup Time Before CLKOUT Low1
tCIS
tCIH
Counter Input Hold Time After CLKOUT Low1
1

VDDEXT
1.8V NominalMin
Max

VDDEXT
2.5 V/3.3V Nominal
Min
Max
Unit

tSCLK + 1
90tSCLK + 1
7
0

ns
ns
ns

Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.

CLKOUT

tCIS
tCIH
CUD/CDG/CZMtWCOUNT

Figure 29. Up/Down Counter/Rotary Encoder Timing

10/100 Ethernet MAC Controller Timing
Table 39 through Table 44 and Figure 30 through Figure 35
describe the 10/100 Ethernet MAC Controller operations.
Table 39. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
VDDEXT
1.8V Nominal
Parameter1

VDDEXT
2.5 V/3.3V Nominal

Min

Max

Min

Max

Unit

Timing Requirements
tERXCLKF

ERxCLK Frequency (fSCLK = SCLK Frequency)

None

25 + 1%None

25 + 1%MHz

tERXCLKWERxCLK Width (tERxCLK = ERxCLK Period)tERxCLK × 40%

tERxCLK × 60%

tERxCLK × 35%

tERxCLK × 65%

ns

tERXCLKISRx Input Valid to ERxCLK Rising Edge (Data In Setup)

7.5

7.5

ns

tERXCLKIH

ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)

7.5

7.5

ns

1

MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.

tERXCLKtERXCLKW

ERx_CLK

ERxD3–0
ERxDV
ERxER

tERXCLKIStERXCLKIH

Figure 30. 10/100 Ethernet MAC Controller Timing: MII Receive Signal

Rev. E |Page 44 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
Table 40. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
VDDEXT
2.5 V/3.3V Nominal

VDDEXT
1.8V Nominal
Parameter1

Min

Max

Min

Max

Unit

Switching Characteristics
tETF

ETxCLK Frequency (fSCLK = SCLK Frequency)

None

25 + 1%None

25 + 1%MHz

tETXCLKWETxCLK Width (tETxCLK = ETxCLK Period)tETxCLK × 40%

tETxCLK × 60%

tETxCLK × 35%

tETxCLK × 65%

ns

tETXCLKOVETxCLK Rising Edge to Tx Output Valid (Data Out Valid)

20

ns

tETXCLKOH

ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold) 0

1

20
0

ns

MII outputs synchronous to ETxCLK are ETxD3–0.

tETXCLK
MIITxCLKtETXCLKWtETXCLKOH

ETxD3–0ETxEN

tETXCLKOV

Figure 31. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal

Table 41. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
VDDEXT
2.5 V/3.3V Nominal

VDDEXT
1.8V Nominal
Parameter1

Min

Max

Min

Max

Unit

None

50 + 1%None

50 + 1%MHz

Timing Requirements
tEREFCLKF

REF_CLK Frequency (fSCLK = SCLK Frequency)tEREFCLKWEREF_CLK Width (tEREFCLK = EREFCLK Period)tEREFCLK × 40% tEREFCLK × 60%

tEREFCLK × 35% tEREFCLK × 65%

ns

tEREFCLKISRx Input Valid to RMII REF_CLK Rising Edge (Data In
Setup)

4

4

ns

tEREFCLKIH

RMII REF_CLK Rising Edge to Rx Input Invalid (Data In 2
Hold)

2

ns

1

RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.

tREFCLK
tREFCLKWRMII_REF_CLK

ERxD1–0
ERxDV
ERxER

tREFCLKIStREFCLKIH

Figure 32. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal

Rev. E |Page 45 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
Table 42. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
Parameter1

Min

Max

Unit

8.1

ns

Switching Characteristics
tEREFCLKOVRMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid)tEREFCLKOH

RMII REF_CLK Rising Edge to Tx Output Invalid (Data Out Hold)

1

2

RMII outputs synchronous to RMII REF_CLK are ETxD1–0.

tREFCLKRMII_REF_CLKtREFCLKOH
ETxD1–0ETxEN

tREFCLKOV

Figure 33. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal

Rev. E |Page 46 of 63 |June 2020

ns

ADSP-BF512/BF514/BF516/BF518
Table 43. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
Parameter

Min

Max

Unit

Timing Requirements
tECOLH

COL Pulse Width High1

tETxCLK × 1.5
tERxCLK × 1.5

nsnstECOLLCOL Pulse Width Low1

tETxCLK × 1.5
tERxCLK × 1.5

nsnstECRSHCRS Pulse Width High2

tETxCLK × 1.5

ns

tECRSLCRS Pulse Width Low2

tETxCLK × 1.5

ns1

MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to boththe ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
2
The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.

MIICRS, COLtECRSHtECOLHtECRSLtECOLL

Figure 34. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal

Table 44. 10/100 Ethernet MAC Controller Timing: MII Station Management
Parameter1

Min

Max

Unit

Timing Requirements
tMDIOSMDIO Input Valid to MDC Rising Edge (Setup)

11.5

ns

tMDCIHMDC Rising Edge to MDIO Input Invalid (Hold)0ns

Switching Characteristics
tMDCOVMDC Falling Edge to MDIO Output ValidtMDCOHMDC Falling Edge to MDIO Output Invalid (Hold)

1

25
–1.25

ns
ns

MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multipleof the system clock SCLK. MDIO is a bidirectional data line.

MDC (OUTPUT)

tMDCOHMDIO (OUTPUT)

tMDCOVMDIO (INPUT)

tMDIOStMDCIH

Figure 35. 10/100 Ethernet MAC Controller Timing: MII Station Management

Rev. E |Page 47 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
JTAG Test And Emulation Port Timing
Table 45 and Figure 36 describe JTAG port operations.
Table 45. JTAG Port Timing
Parameter

Min

Max

Unit

Timing Requirements
tTCK

TCK Period

20

ns

tSTAP

TDI, TMS Setup Before TCK High

4

ns

tHTAP

TDI, TMS Hold After TCK High4

ns

tSSYS1

System Inputs Setup Before TCK High4

ns

tHSYS1

System Inputs Hold After TCK High5ns

tTRSTW

2

4

TCK

TRST Pulse Width (measured in TCK cycles)

Switching Characteristics
tDTDO

TDO Delay from TCK Low

tDSYS3

System Outputs Delay After TCK Low

0

1

10

ns

13

ns

System Inputs = DATA15–0, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH7–0, MDIO, TD1, TMS, RESET, NMI, BMODE2–0.
50 MHz Maximum.
3
System Outputs = DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AMS1–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, TSCLK0, TFS0, RFS0, RSCLK0,DT0PRI, DT0SEC, PF15–0, PG15–0, PH7–0, MDC, MDIO.
2

tTCK
TCK

tSTAP

tHTAP

tSSYS

tHSYS

TMS
TDI

tDTDO
TDO

SYSTEM
INPUTStDSYS
SYSTEMOUTPUTS

Figure 36. JTAG Port Timing

Rev. E |Page 48 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
OUTPUT DRIVE CURRENTS
Figure 37 through Figure 51 show typical current-voltage characteristics for the output drivers of the ADSP-BF51x processors.

The curves represent the current drive capability of the output
drivers. See Table 7 for information about which driver typecorresponds to a particular ball.

200
160

240
200

VDDEXT = 3.0V @ 105°C

120
80

0
–40
–80
VOL

–120

VDDEXT = 3.0V @ 105°C

120

VOH

40

VDDEXT = 3.6V @ – 40°C
VDDEXT = 3.3V @ 25°C

160
SOURCE CURRENT (mA)

SOURCE CURRENT (mA)VDDEXT = 3.6V @ – 40°C
VDDEXT = 3.3V @ 25°C

–160

80

VOH

40
0
–40
–80
–120

VOL

–160
–200

–200
0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

–240
0

SOURCE VOLTAGE (V)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)Figure 37. Driver Type A Current (3.3V VDDEXT/VDDMEM)

Figure 40. Driver Type B Current (3.3V VDDEXT/VDDMEM)
160
VDDEXT = 2.75V @ – 40°C
120

160

VDDEXT = 2.5V @ 25°C

VDDEXT = 2.75V @ – 40°C

VDDEXT = 2.25V @ 105°C

120

VDDEXT = 2.5V @ 25°C

80

VDDEXT = 2.25V @ 105°C

40
VOH
0
–40
–80
VOL
–120

SOURCE CURRENT (mA)

SOURCE CURRENT (mA)

80

40
VOH
0
–40
–80
VOL
–120
–160

–160
0

0.5

1.0

1.5

2.0

2.5

–200
0

SOURCE VOLTAGE (V)

0.5

1.0

1.5

2.0

2.5

SOURCE VOLTAGE (V)Figure 38. Driver Type A Current (2.5V VDDEXT/VDDMEM)

Figure 41. Driver Type B Current (2.5V VDDEXT/VDDMEM)
80
60

VDDEXT = 1.9V @ – 40°C

80

VDDEXT = 1.8V @ 25°C
VDDEXT = 1.7V @ 105°C

60

VDDEXT = 1.9V @ – 40°C
VDDEXT = 1.8V @ 25°C
VDDEXT = 1.7V @ 105°C

40

VOH

20
0
–20

VOL

–40
–60

SOURCE CURRENT (mA)

SOURCE CURRENT (mA)

40

VOH

20
0
–20
–40

VOL

–60
–80

–80
0

0.5

1.0

1.5

–100
0.5

0

SOURCE VOLTAGE (V)

1.0

1.5

SOURCE VOLTAGE (V)Figure 39. Driver Type A Current (1.8V VDDEXT/VDDMEM)

Figure 42. Driver Type B Current (1.8V VDDEXT/VDDMEM)

Rev. E |Page 49 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
100

160
120

VDDEXT = 3.3V @ 25°C

60

VDDEXT = 3.0V @ 105°C

40
VOH
20
0
–20
–40
VOL

–60

VDDEXT = 3.3V @ 25°C
VDDEXT = 3.0V @ 105°C

80
SOURCE CURRENT (mA)

SOURCE CURRENT (mA)VDDEXT = 3.6V @ – 40°C

VDDEXT = 3.6V @ – 40°C

80

VOH

40
0
–40
–80

VOL
–120

–80
–100

–160
0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0

0.5

1.0

1.5

SOURCE VOLTAGE (V)Figure 43. Driver Type C Current (3.3V VDDEXT/VDDMEM)

3.0

3.5

120

VDDEXT = 2.75V @ – 40°C

VDDEXT = 2.75V @ – 40°C

100

VDDEXT = 2.5V @ 25°C

VDDEXT = 2.5V @ 25°C

80

VDDEXT = 2.25V @ 105°C
40

VDDEXT = 2.25V @ 105°C

60

20
VOH
0
–20
–40
VOL

SOURCE CURRENT (mA)

SOURCE CURRENT (mA)

2.5

Figure 46. Driver Type D Current (3.3V VDDEXT/VDDMEM)

80
60

2.0

SOURCE VOLTAGE (V)

40
VOH

20
0
–20
–40
–60

VOL

–80

–60

–100
–80

–120
0

0.5

1.0

1.5

2.0

2.5

0

0.5

1.0

SOURCE VOLTAGE (V)Figure 44. Drive Type C Current (2.5V VDDEXT/VDDMEM)

2.5

60

VDDEXT = 1.9V @ – 40°C

VDDEXT = 1.9V @ – 40°C

VDDEXT = 1.8V @ 25°C
VDDEXT = 1.7V @ 105°C

VDDEXT = 1.8V @ 25°C
VDDEXT = 1.7V @ 105°C

40

VOH

10
0
–10

VOL
–20

SOURCE CURRENT (mA)

20
SOURCE CURRENT (mA)

2.0

Figure 47. Driver Type D Current (2.5V VDDEXT/VDDMEM)

40
30

1.5

SOURCE VOLTAGE (V)

20
VOH
0

–20
VOL
–40

–30
–40
0

0.5

1.0

–60

1.5

0

0.5

SOURCE VOLTAGE (V)

1.0

1.5

SOURCE VOLTAGE (V)Figure 45. Driver Type C Current (1.8V VDDEXT/VDDMEM)

Rev. E |Figure 48. Driver Type D Current (1.8V VDDEXT/VDDMEM)

Page 50 of 63 |June 2020

2

ADSP-BF512/BF514/BF516/BF518
TEST CONDITIONS60
VDDEXT = 3.6V @ – 40°C

50

VDDEXT = 3.3V @ 25°C

40

VDDEXT = 3.0V @ 105°C

SOURCE CURRENT (mA)

30
20
10

All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 52
shows the measurement point for ac measurements (except output enable/disable). The measurement point VMEAS is VDDEXT/2
or VDDMEM/2 for VDDEXT/VDDMEM (nominal) = 1.8 V/2.5 V/3.3 V.

0
–10
–20
–30

INPUT
OR
OUTPUT

VOL

–40

VMEAS

VMEAS

–50
–60
0

0.5

1.0

1.5

2.0

2.5

3.0

Figure 52. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)

3.5

SOURCE VOLTAGE (V)Output Enable Time Measurement

Figure 49. Driver Type E Current (3.3V VDDEXT/VDDMEM)40
VDDEXT = 2.75V @ – 40°C
30

VDDEXT = 2.5V @ 25°C
VDDEXT = 2.25V @ 105°C

SOURCE CURRENT (mA)

20
10
0

Output signals are considered to be enabled when they havemade a transition from a high impedance state to the point
when they start driving.
The output enable time tENA is the interval from the point whena reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 53.

–10
VOL

REFERENCE
SIGNAL–20–30

tDIS_MEASURED
tDIS

–40
0

0.5

1.0

1.5

2.0

3.0

2.5

3.5

VOH
(MEASURED)

SOURCE VOLTAGE (V)Figure 50. Driver Type E Current (2.5V VDDEXT/VDDMEM)tENA_MEASURED
tENA

VOL
(MEASURED)

VOH (MEASURED) - ΔV

VOH(MEASURED)VTRIP(HIGH)

VOL (MEASURED) + ΔVVTRIP(LOW)
VOL (MEASURED)tDECAY

20tTRIP

VDDEXT = 1.9V @ – 40°C
15

VDDEXT = 1.8V @ 25°C
VDDEXT = 1.7V @ 105°C

OUTPUT STOPS DRIVING

SOURCE CURRENT (mA)10

OUTPUT STARTS DRIVINGHIGH IMPEDANCE STATE

5

Figure 53. Output Enable/Disable

0
–5
VOL
–10
–15
–20
0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)Figure 51. Driver Type E Current (1.8V VDDEXT/VDDMEM)

The time tENA_MEASURED is the interval from when the reference
signal switches to when the output voltage reaches VTRIP(high)or VTRIP(low). For VDDEXT (nominal) = 1.8 V, VTRIP (high) is
0.95 V, and VTRIP (low) is 0.85 V. For VDDEXT (nominal) = 2.5 V,
VTRIP (high) is 1.3 V and VTRIP (low) is 1.2 V. For VDDEXT (nominal) = 3.3 V, VTRIP (high) is 1.7 V, and VTRIP (low) is 1.6 V. TimetTRIP is the interval from when the output starts driving to when
the output reaches the VTRIP(high) or VTRIP(low) trip voltage.
Time tENA is calculated as shown in the equation:t ENA = t ENA_MEASURED – t TRIP
If multiple signals (such as the data bus) are enabled, the measurement value is that of the first signal to start driving.

Rev. E |Page 51 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
Output Disable Time Measurement

TESTER PIN ELECTRONICS

Output signals are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay fromtheir output high or low voltage. The output disable time tDIS isthe difference between tDIS_MEASURED and tDECAY as shown on theleft side of Figure 53.

50:
VLOAD

T1

70:
ZO = 50:(impedance)
TD = 4.04 ± 1.18 ns

50:

t DIS = t DIS_MEASURED – t DECAY

0.5pF

4pF

2pF

The time for the voltage on the bus to decay by V is dependent
on the capacitive load CL and the load current IL. This decay
time can be approximated by the equation:

400:

t DECAY =  C L V   I L

NOTES:THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USEDFOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

The time tDECAY is calculated with test loads CL and IL and with
V equal to 0.25 V for VDDEXT/VDDMEM (nominal) = 2.5 V/3.3 V
and 0.15 V for VDDEXT/VDDMEM (nominal) = 1.8 V.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVENSYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

The time tDIS_MEASURED is the interval from when the reference
signal switches to when the output voltage decays V from themeasured output high or output low voltage.

Figure 54. Equivalent Device Loading for AC Measurements(Includes All Fixtures)

Example System Hold Time Calculation

Capacitive Loading

12

10
tRISE
RISE AND FALL TIME (ns)

To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose V
to be the difference between the ADSP-BF51x processor’s output voltage and the input threshold for the device requiring thehold time. CL is the total bus capacitance (per data line), and IL is
the total leakage or three-state current (per data line). The holdtime is tDECAY plus the various output disable times as specified
in the Timing Specifications (for example tDSDAT for an SDRAM
write cycle as shown in SDRAM Interface Timing).

Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all balls (see Figure 54). VLOAD is equalto (VDDEXT/VDDMEM)/2. The graphs of Figure 55 throughFigure 66 show how output rise time varies with capacitance.
The delay and hold specifications given should be derated by afactor derived from these figures. The graphs in these figures
may not be linear outside the ranges shown.

Rev. E |DUT
OUTPUT

45:

Page 52 of 63 |

8
tFALL
6

4

2

tRISE = 1.8V @ 25°C
tFALL = 1.8V @ 25°C

0
0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 55. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT/VDDMEM)

June 2020

250

8

7

7

6

6

tRISE

RISE AND FALL TIME (ns)

RISE AND FALL TIME (ns)

ADSP-BF512/BF514/BF516/BF518

5
tFALL
4
3
2
1

200

150

tFALL
3
2

tRISE = 2.5V @ 25°C

0

0
100

4

tFALL = 2.5V @ 25°C

tFALL = 2.5V @ 25°C
50

tRISE

1

tRISE = 2.5V @ 25°C

0

5

0

250

50

100

250

LOAD CAPACITANCE (pF)

LOAD CAPACITANCE (pF)

Figure 56. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V VDDEXT/VDDMEM)

Figure 59. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V VDDEXT/VDDMEM)

6

6

5

5
RISE AND FALL TIME (ns)tRISE
RISE AND FALL TIME (ns)

200

150

4
tFALL
3

2

tRISE
4
tFALL
3

2

1

1

tRISE = 3.3V @ 25°C

tRISE = 3.3V @ 25°C
tFALL = 3.3V @ 25°C

0
0

50

100

200

150

tFALL = 3.3V @ 25°C

0
0

250

50

100

200

150

250

LOAD CAPACITANCE (pF)

LOAD CAPACITANCE (pF)

Figure 60. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V VDDEXT/VDDMEM)

Figure 57. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V VDDEXT/VDDMEM)

25

9
8
tRISE

20
RISE AND FALL TIME (ns)

RISE AND FALL TIME (ns)

7
6
tFALL
5
4
3
2

tRISE
15

tFALL

10

5
tRISE = 1.8V @ 25°C

tRISE = 1.8V @ 25°C

1

tFALL = 1.8V @ 25°C

tFALL = 1.8V @ 25°C

0

0
0

50

100

150

200

250

0

50

100

150

200

LOAD CAPACITANCE (pF)

LOAD CAPACITANCE (pF)

Figure 61. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT/VDDMEM)

Figure 58. Driver Type B Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT/VDDMEM)

Rev. E |Page 53 of 63 |June 2020

250

ADSP-BF512/BF514/BF516/BF518
16

10

14

9

RISE AND FALL TIME (ns)

RISE AND FALL TIME (ns)

8

12
tRISE
10
tFALL
8
6
4
2

tRISE = 2.5V @ 25°C

100

150

200

tFALL

5
4
3
2
tRISE = 2.5V @ 25°C
tFALL = 2.5V @ 25°C

0
50

tRISE

6

1

tFALL = 2.5V @ 25°C
0

7

0

250

0

50

LOAD CAPACITANCE (pF)

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 62. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V VDDEXT/VDDMEM)

Figure 65. Driver Type D Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (2.5V VDDEXT/VDDMEM)
8

14

7

RISE AND FALL TIME (ns)

RISE AND FALL TIME (ns)

12
tRISE
10
8
tFALL
6
4

6

tRISE

5
tFALL
4
3

2
1

2

tRISE = 3.3V @ 25°C

0

50

100

200

150

tFALL = 3.3V @ 25°C

0tFALL = 3.3V @ 25°C

0tRISE = 3.3V @ 25°C

0250

LOAD CAPACITANCE (pF)

14
12
RISE AND FALL TIME (ns)

tRISE
10
tFALL
8
6
4

tRISE = 1.8V @ 25°C
tFALL = 1.8V @ 25°C

0
0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 64. Driver Type D Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT/VDDMEM)

Rev. E |

100

150

200

LOAD CAPACITANCE (pF)

Figure 66. Driver Type D Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V VDDEXT/VDDMEM)

Figure 63. Driver Type C Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (3.3V VDDEXT/VDDMEM)

2

50Page 54 of 63 |June 2020

250

ADSP-BF512/BF514/BF516/BF518
THERMAL CHARACTERISTICS

Table 46. Thermal Characteristics for SQ-176-2 Package

To determine the junction temperature on the application
printed circuit board use:

Parameter

Condition

TypicalUnit

θJA

0 Linear m/s Airflow

17.4

°C/W

θJMA

1 Linear m/s Airflow

14.8

°C/W

θJMA

2 Linear m/s Airflow

14.0

°C/W

where:θJC

Not Applicable

7.8

°C/W

TJ = Junction temperature (°C)ΨJT

0 Linear m/s Airflow

0.28

°C/W

TCASE = Case temperature (°C) measured by customer at top
center of package.

ΨJT

1 Linear m/s Airflow

0.39

°C/W

ΨJT

2 Linear m/s Airflow

0.48

°C/W

T J = T CASE +   JT  P D 

ΨJT = From Table 47
Table 47. Thermal Characteristics for BC-168-1 Package

PD = Power dissipation (see Total Power Dissipation for the
method to calculate PD)
Values of θJA are provided for package comparison and printed
circuit board design considerations. JA can be used for a firstorder approximation of TJ by the equation:
T J = T A +   JA  P D 
where:TA = Ambient temperature (°C)
Values of θJC are provided for package comparison and printed
circuit board design considerations when an external heat sink
is required.

Parameter

Condition

TypicalUnit

θJA

0 Linear m/s Airflow

30.5

°C/W

θJMA

1 Linear m/s Airflow

27.6

°C/W

θJMA

2 Linear m/s Airflow

26.3

°C/W

θJC

Not Applicable

11.1

°C/W

ΨJT

0 Linear m/s Airflow

0.20

°C/W

ΨJT

1 Linear m/s Airflow

0.35

°C/W

ΨJT

2 Linear m/s Airflow

0.45

°C/W

Values of θJB are provided for package comparison and printed
circuit board design considerations.
In Table 47, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-casemeasurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
The LQFP_EP package requires thermal trace squares and thermal vias to an embedded ground plane in the PCB. The paddle
must be connected to ground for proper operation to data sheet
specifications. Refer to JEDEC standard JESD51-5 for more
information.

Rev. E |Page 55 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
176-LEAD LQFP_EP LEAD ASSIGNMENT
Table 48 lists the LQFP_EP leads by lead number.
Table 48. 176-Lead LQFP_EP Pin Assignment (Numerical by Lead Number)
Lead No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Lead No.
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
GND
* Pin no. 177 is the GND supply (see Figure 68) for the processor; this pad must be robustly connected to GND.

1

Signal
GND
GND
PF9
PF8
PF7
PF6
VDDEXTVPPOTP
VDDOTP
PF5
PF4
PF3
PF2
VDDINT
GND
VDDEXT
VDDEXT
PF1
PF0
PG15
PG14
GND
VDDINT
VDDEXT
PG13
PG12
PG11
PG10
VDDEXT
VDDINT
PG9
PG8
PG7
PG6
VDDEXT
PG5
PG4
PG3
PG2
BMODE2
BMODE1
BMODE0
GND
GND

Lead No.
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88

Signal
GND
GND
PG1
PG0
VDDEXT
TDO
EMU
TDI
TCK
TRST
TMS
D15
D14
D13
VDDMEM
D12D11D10
VDDINT
D9D8D7GND
VDDMEM
D6
D5
D4
D3
D2
D1
VDDMEM
D0
A19
A18
VDDINT
A17
A16
VDDMEM
GND
A15
A14
A13
GND
GND

Lead No.
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132

Do not make any electrical connection to this pin.

Rev. E |Page 56 of 63 |June 2020

Signal
GND
GND
A12
A11
A10
A9
VDDMEM
A8
A7
VDDINT
GND
VDDINT
A6
A5A4
VDDMEM
A3
A2
A1
ABE1
ABE0
SA10
GND
VDDMEM
SWE
SCAS
SRAS
VDDINT
GND
SMS
SCKE
AMS1
ARE
AWE
AMS0
VDDMEM
CLKOUT
VDDEXTNC1
VDDEXT
VDDEXT
EXT_WAKE
GND
GND

SignalGND
GND
PG
VDDEXT
GND
VDDINT
GND
RTXO
RTXI
VDDRTCCLKIN
XTAL
VDDEXTRESET
NMI
VDDEXTGND
CLKBUFGND
VDDINT
PH7
PH6
PH5
PH4
GND
VDDEXT
PH3
PH2
PH1
PH0
GND
VDDINT
PF15
PF14
PF13
PF12
GND
VDDEXT
PF11
SDA
SCL
PF10
GND
GND
177*

ADSP-BF512/BF514/BF516/BF518
Figure 67 shows the top view of the LQFP_EP lead configuration. Figure 68 shows the bottom view of the LQFP_EP leadconfiguration.
PIN 176

PIN 133

PIN 1

PIN 132

PIN 1 INDICATORADSP-BF51X
176-LEAD LQFP_EP
TOP VIEWPIN 44

PIN 89
PIN 45

PIN 88Figure 67. 176-Lead LQFP_EP Lead Configuration (Top View)

PIN 133

PIN 176

PIN 132

PIN 1

ADSP-BF51X
176-LEAD
LQFP_EPBOTTOM VIEW

GND PAD(PIN 177)

PIN 1 INDICATORPIN 89

PIN 44
PIN 88

PIN 45Figure 68. 176-Lead LQFP_EP Lead Configuration (Bottom View)

Rev. E |Page 57 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
168-BALL CSP_BGA BALL ASSIGNMENT
Table 49 lists the CSP_BGA by ball number.
Table 49. 168-Ball CSP_BGA Ball Assignment (Numerical by Ball Number)
Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name
A1

GND

C1

PF4

E10

VDDINT

H1

PG12

K6

VDDMEM

N1

BMODE1

A2

SCL

C2

PF7

E12

VDDMEM

H2

PG13

K7

VDDMEM

N2

PG1

A3

SDA

C3

PF8

E13

ARE

H3

PG11

K8

VDDMEM

N3

TDO

A4

PF13

C4

PF10

E14

AWE

H5

VDDEXTK9

VDDMEM

N4

TRST

A5

PF15

C5

VDDEXT

F1

PF0

H6

GND

K10

VDDMEM

N5

TMS

A6

PH2

C6

VDDEXT

F2

PF1

H7

GND

K12

A8

N6

D13

A7

PH1

C7

PF11

F3

VDDINT

H8

GND

K13

A2

N7

D9

A8

PH5

C8

VDDEXTF5

VDDEXT

H9

GND

K14

A1

N8

D5

A9

PH6

C9

VDDINT

F6

GND

H10

VDDINT

L1

PG5

N9

D1

A10

PH7

C10

VDDEXT

F7

GND

H12

A3

L2

PG3

N10

A18

A11

CLKBUF

C11

RTXI

F8

GND

H13

ABE0

L3

PG2

N11

A16

A12

XTAL

C12

RTXO

F9

GND

H14

SCAS

L12

A9

N12

A14

A13

CLKIN

C13

PG

F10

VDDINT

J1

PG10

L13

A6

N13

A11

A14

GND

C14

NC1

F12

SMS

J2

VDDEXT

L14

A4

N14

A7

B1

VDDOTP

D1

PF3

F13

SCKE

J3

PG9

M1

PG4

P1

GND

B2

GND

D2

PF5

F14

AMS1

J5

VDDMEM

M2

BMODE2

P2

TDI

B3

PF9

D3

VPPOTP

G1

PG15

J6

GND

M3

BMODE0

P3

TCK

B4

PF12

D12

VDDEXT

G2

PG14

J7

GND

M4

PG0

P4

D15

B5

PF14

D13

CLKOUTG3

VDDINT

J8

GND

M5

EMU

P5

D14

B6

PH0

D14

AMS0

G5

VDDEXT

J9

GND

M6

D12

P6

D11

B7

PH3

E1

VDDEXT

G6

GND

J10

VDDINT

M7

D10

P7

D8

B8

PH4

E2

PF2

G7

GND

J12

A15

M8

D2

P8

D7

B9

VDDEXT

E3

PF6

G8

GND

J13

ABE1

M9

D0

P9

D6

B10

RESET

E5

VDDEXT

G9

GND

J14

SA10

M10

A17

P10

D4

B11

NMI

E6

VDDEXTG10

VDDINT

K1

PG6

M11

A13

P11

D3

B12

VDDRTCE7

VDDINT

G12

SWE

K2

PG8

M12

A12

P12

A19

B13

VDDEXTE8

VDDINT

G13

SRAS

K3

PG7

M13

A10

P13

GND

B14

EXT_WAKE

E9

VDDINT

G14

GND

K5

VDDMEM

M14

A5

P14

GND

1

Do not make any electrical connection to this pin.

Rev. E |Page 58 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
Figure 69 shows the top view of the CSP_BGA ball configuration. Figure 70 shows the bottom view of the CSP_BGA
ball configuration.

A1 BALL PAD CORNER

A
B

NC

C
D
E
F
KEY

G
H

V

DDINT

J
K

V

DDEXT

L

GND

V

I/O

V

DDMEM
DDRTC

M
N
P
1

2

3

4

5

6

7

8

9

10 11 12 13 14

TOP VIEW

Figure 69. 168-Ball CSP_BGA Ball Configuration (Top View)

A1 BALL PAD CORNER

A
B
C

NC

D

KEY

E
V

F

DDINT

GND

V

I/O

V

DDMEM

G
V

H

DDEXT

J
K
L
M
N
P
14 13 12 11 10

9

8

7

6

5

4

3

2

1

BOTTOM VIEW

Figure 70. 168-Ball CSP_BGA Ball Configuration (Bottom View)

Rev. E |Page 59 of 63 |June 2020

DDRTCADSP-BF512/BF514/BF516/BF518
OUTLINE DIMENSIONS
Dimensions in Figure 71 are shown in millimeters.
26.20
26.00 SQ
25.80
0.75
0.60
0.45
1.00 REF

1.60
MAX

NOTE: THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND
THERMALLY CONNECTED TO GND. IMPLEMENT THIS BYSOLDERING THE EXPOSED PAD TO A GND PCB LAND THAT IS
THE SAME SIZE AS THE EXPOSED PAD. THE GND PCB LANDSHOULD BE ROBUSTLY CONNECTED TO THE GND PLANE IN
THE PCB WITH AN ARRAY OF THERMAL VIAS FOR BESTPERFORMANCE.

24.10
24.00 SQ
23.90
133
132

176
1

133
132

176
1

PIN 1

12°

1.45
1.40
1.35

0.15
0.10
0.05

SEATING
PLANE

0.20
0.15
0.09
7°
0°
0.08 MAX
COPLANARITY

5.80 REFSQEXPOSEDPAD

TOP VIEW(PINS DOWN)

BOTTOM VIEW(PINS UP)

89

44
45

VIEW A

88

0.50
BSC
LEAD PITCH

89
88

0.27
0.22
0.17

VIEW AROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD

Figure 71. 176-Lead Low Profile Quad Flat Package [LQFP_EP](SQ-176-2)
Dimensions shown in millimeters

Rev. E |Page 60 of 63 |June 2020

45

44

EXPOSED PAD IS CENTERED ON
THE PACKAGE.

ADSP-BF512/BF514/BF516/BF518
A1 BALLCORNER

12.10
12.00 SQ
11.90

A
B
C
D
E
F
G
H
J
K
L
M
N
P

10.40
BSC SQ
0.80
BSC

0.80
REF

TOP VIEW

1.50
1.40
1.30

A1 BALLCORNER14 13 12 11 10 9 8 7 6 5 4 3 2 1

BOTTOM VIEW

DETAIL A
0.70
REF

DETAIL A

1.12
1.06
1.00
0.34 NOM
0.29 MIN

0.36
REF
SEATING
PLANE

0.50
COPLANARITY
0.45
0.20
0.40
BALL DIAMETERCOMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.

Figure 72. 168-Ball Chip Scale Package Ball Grid Array [CSP_BGA](BC-168-1)
Dimensions shown in millimeters

SURFACE-MOUNT DESIGN
Table 50 is provided as an aid to PCB design. For industry
standard design recommendations, refer to IPC-7351, GenericRequirements for Surface Mount Design and Land PatternStandard.
Table 50. BGA Data for Use with Surface-Mount Design
Package

Package Ball Attach Type

Package Solder Mask
Opening

Package Ball Pad Size

168-Ball CSP_BGA

Solder Mask Defined

0.35 mm diameter

0.48 mm diameter

Rev. E |Page 61 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
AUTOMOTIVE PRODUCTS
The ADBF512W and ADBF518W models are available with
controlled manufacturing to support the quality and reliability
requirements of automotive applications. Note that these automotive models may have specifications that differ from thecommercial models and designers should review the productSpecifications section of this data sheet carefully. Only theautomotive grade products shown in Table 51 are available foruse in automotive applications. Contact your local ADI accountrepresentative for specific product ordering information and toobtain the specific Automotive Reliability reports for thesemodels.

Table 51. Automotive Products
Automotive Models1,2

Temperature
Range3

Processor Instruction
Rate (Max)

Package Description

Package
OptionADBF512WBBCZ4xx–40ºC to +85ºC

400 MHz

168-Ball CSP_BGA

BC-168-1

ADBF518WBBCZ4xx–40ºC to +85ºC

400 MHz

168-Ball CSP_BGA

BC-168-1

ADBF512WBSWZ4xx–40ºC to +85ºC

400 MHz

176-Lead LQFP_EP

SQ-176-2

ADBF518WBSWZ4xx–40ºC to +85ºC

400 MHz

176-Lead LQFP_EP

SQ-176-2

1

Z = RoHS Compliant Part.
The use of xx designates silicon revision.
3
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions for junction temperature (TJ) specification
which is the only temperature specification.
2

Rev. E |Page 62 of 63 |June 2020

ADSP-BF512/BF514/BF516/BF518
ORDERING GUIDE

Model1

Temperature Range2

Processor Instruction
Rate (Max)

Package Description

Package Option

ADSP-BF512BBCZ-3–40ºC to +85ºC

300 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF512BBCZ-4–40ºC to +85ºC

400 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF512BSWZ-3–40ºC to +85ºC

300 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF512BSWZ-4–40ºC to +85ºC

400 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF512KBCZ-3

0ºC to +70ºC

300 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF512KBCZ-4

0ºC to +70ºC

400 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF512KSWZ-30ºC to +70ºC

300 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF512KSWZ-40ºC to +70ºC

400 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF514BBCZ-3–40ºC to +85ºC

300 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF514BBCZ-4–40ºC to +85ºC

400 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF514BSWZ-3–40ºC to +85ºC

300 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF514BSWZ-4–40ºC to +85ºC

400 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF514KBCZ-3

0ºC to +70ºC

300 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF514KBCZ-4

0ºC to +70ºC

400 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF514KSWZ-30ºC to +70ºC

300 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF514KSWZ-40ºC to +70ºC

400 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF516KSWZ-30ºC to +70ºC

300 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF516KBCZ-3

0ºC to +70ºC

300 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF516KSWZ-40ºC to +70ºC

400 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF516KBCZ-4

0ºC to +70ºC

400 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF516BBCZ-3–40ºC to +85ºC

300 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF516BBCZ-4–40ºC to +85ºC

400 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF516BSWZ-3–40ºC to +85ºC

300 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF516BSWZ-4–40ºC to +85ºC

400 MHz

176-Lead LQFP_EP

SQ-176-2

ADSP-BF518BBCZ-4–40ºC to +85ºC

400 MHz

168-Ball CSP_BGA

BC-168-1

ADSP-BF518BSWZ-4–40ºC to +85ºC

400 MHz

176-Lead LQFP_EP

SQ-176-2

1
2

Z = RoHS compliant part.
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions for junction temperature (TJ) specification
which is the only temperature specification.

©2020 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.
D08574-6/20(E)Rev. E |Page 63 of 63 |June 2020