Engineer-to-Engineer NoteaEE-308

Technical notes on using Analog Devices DSPs, processors and development tools
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Estimating and Optimizing Booting Time for Blackfin® Processors
Contributed by Jiang Wu

Introduction
This EE-Note describes how to estimate,measure, and optimize the booting time of aBlackfin® processor-based system. A Booting
Time Estimation Tool (BTET) is included tohelp with the analysis of booting time. Though
all measurements and testing described in thisEE- Note were performed on an ADSP-BF533
EZ-KIT Lite® board, and all the descriptions arespecific to ADSP-BF533 Blackfin processors,
the methodology can be readily applied to othertarget Blackfin systems as well.

Booting TimeThe booting time of an ADSP-BF533 Blackfin
processor-based system is defined as the time
between the deassertion of the processor’s/RESET pin and the execution of the first line ofapplication code. Its composition depends on theselected booting mode of the processor. There
are four boot modes supported by theprocessor[1]:Execution from external memoryBoot from flashBoot from SPI slave modeBoot from SPI serial EEPROM master mode

In this EE-Note, the two most common bootmodes will be the focus: boot from flash andboot from SPI serial EEPROM master mode. In
this note, we will only discuss the case where theRev 1 – December 4, 2006

processor boots into L1 memory, though some
applications may boot into SDRAM.
For these two boot modes, the booting time
consists of the time to:Run the built-in Boot ROM



Load data/code from external memory space(flash memory or SPI serial EEPROM) to theprocessor’s L1 memory

Zero-fill the non-initialized dataExecute initialization code, if there is anyInitialization code is usually application-specific,
so it is assumed that there is no initialization
code in the application.

Booting Process
Upon the deassertion of /RESET, the processor
starts the boot process by executing the on-chipboot ROM, which determines the boot mode
(flash or SPI serial EEPROM), sets up the proper
DMA channels (read from external memory toL1 memory), and then puts the processor in anidle state awaiting for the completion of a DMA
read transaction. After parsing the block of bytes
read by the DMA, the boot ROM initiates
another DMA transaction to load more bytes
until all the bytes have been read. Note that thebooting routine is executed from the boot ROM,
which is slower than L1 memory.
Figure 1 graphically shows the boot process.

Copyright 2006, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application ofcustomers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are propertyof their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however
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aA header includes:
ADDRESS (4 bytes) — the address to which

the block will be loaded to within the internalmemory.
COUNT (4 bytes) — the number of bytes of theblock.
FLAG (2 bytes) — block type and control

commands.
Among the 16 bits of the FLAG word, only three
are used for boot time estimation:
Bit 1: ZEROFILL — Indicates that the block is adata buffer with zeros and no actual block
follows. It simply instructs the on-chip bootROM to zero COUNT bytes starting from ADDRESS
in memory. No data transfer from flash/SPI serial
EEPROM is needed for this block.

Figure 1. Booting Process Using On-Chip Boot ROM

The content of the flash/SPI serial EEPROM isthe loader image (.ldr), which is created by theVisualDSP++® loader utility (elfloader.exe),
based on one or more Blackfin executable(.dxe) files. It is organized as header/block
pairs, as shown in Figure 2. A header is ten bytes
long and provides the information about theblock that follows. The boot ROM extracts thisblock of information by parsing headers and thendetermines what to do with the corresponding
blocks.

Bit 3: INIT — Indicates that the block is an
initialization block, which the boot ROM willcall after loading into the internal memory (theinitialization code must have an RTS at the end).
Bit 15: FINAL — Indicates that the following
block is the last one. After processing a FINALblock, the boot ROM jumps to the reset vector
address stored in the EVT1 register.
The on-chip boot ROM implements zero-fillingusing memory DMA transfers. The source is asingle boot ROM memory location set to zero,and the destination is the data block specified bythe header. For a complete description of theheader format, refer to ADSP-BF533 Blackfin
Booting Process (EE-240) [2].

Measurement of Boot Time

Figure 2. Structure of Loader File in Flash/EEPROM

To measure the boot time of a Blackfin
processor-based system, a code snippet, shown in
Listing 1, must be compiled into the loader fileand programmed/burned to the flash/SPI serial
EEPROM of the target system by the Flash
Programmer tool provided with VisualDSP++.
The system must be configured as “boot fromflash” or “boot from SPI serial EEPROM” by

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asetting the BMODE[1:0] pins properly. Then,
upon a system reset, the code is brought in by theboot ROM to the beginning of L1 memory(0xFFA00000). It first sets up one of the
programmable flags (PF0) as an output, and thentoggles it.
#include <defBF533.h>#define RESERVE_SIZE /* depending on
the size of data file startup.dat */#define FILL_SIZE 10 /* in KByte */.section program;start:
p0.h = hi(FIO_DIR);
p0.l = lo(FIO_DIR);
r0.l = 0x0001;
w[p0] = r0.l; /* set the flag */p0.l = lo(FIO_FLAG_T);
w[p0] = r0.l; /* toggle PF0 */On the ADSP-BF533 EZ-KIT Lite board, these
two signals (/RESET and PF0) can be accessed
through the extension U-connector on the bottomof the board. The booting time will be the time
gap between the rising edge of /RESET and thetoggling edge of PF0. The execution time of thecode snippet is negligible in comparison to theloading time and boot ROM execution time.
The reserve and fill buffers (defined in thecode snippet of Listing 1) are used to change thesize of the flash/SPI serial EEPROM loading andzero-filling, therefore facilitating the simulationof the impact of code sizes on booting time.
The /RESET pin pulse and flag pin toggle can berecorded by an oscilloscope's single trigger mode
— /RESET as trigger source with positive edge, as
shown in Figure 3.

wait_loop:
jump wait_loop;
start.end: nop;
#ifdef FILL_SIZE.section data1.byte fill[FILL_SIZE*1024];#endif#ifdef RESERVE_SIZE.byte reserve[] = "startup.dat";#endifListing 1. Code Snippet for Measuring Booting Time

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aFigure 3. Oscilloscope Waveforms of /RESET and PF0 for Measuring Booting Time

Estimating Boot Time
It is possible to estimate the boot time of an
ADSP-BF533 Blackfin processor, given thecrystal frequency and the .ldr file. Among thefour components of the boot time, boot ROM
execution time (TROM) is relatively constant.
Although it may vary with regard to loader filecontents, the deviation is usually small enough tobe ignored. The execution time of initialization
code (TInit) entirely depends on the specificapplication, and it can be estimated separately.
The data/code loading time can be estimated by
Equation 1, where TSCLK is the period of thesystem clock, NLoading is the number of bytes tobe loaded, and PMem is the number of system
clocks needed to read one byte from external
memory, whether flash or SPI serial EEPROM.

TLoading = TSCLK × N Loading × PMem
Equation 1. Estimation of Loading TimeThe zero-filling time can be estimated byEquation 2, where TCCLK is the period of the coreclock, NFilling is the number of bytes to be zerofilled, and PFilling is the number of core clocks
needed for zero-filling one byte.

TFilling = TSCLK × N Filling × PFilling
Equation 2. Estimation of Zero-Filling TimeThe boot time (TBooting) can be estimated by thesum of the above four times, as shown inEquation 3.

TBooting = TROM + TInit + TLoading + TFilling
Equation 3. Estimation of Boot Time

Table 1 summarizes the values of the neededparameters for ADSP-BF533 processors. Theloading size (NLoading) and zero-filling size(NFilling) can be extracted by parsing .ldr files. A
detailed description of loader file format can beEstimating and Optimizing Booting Time for Blackfin® Processors (EE-308)

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afound in ADSP-BF533 Blackfin Booting Process(EE-240). The core clock (TCCLK) and systemclock (TSCLK) can be obtained easily by thecrystal clock frequency and the processor’s
default PLL settings, which can be found in theprocessor's Hardware Reference [3].
FlashSPI Serial EEPROM

TROM

3360 core clocks

90000 core clocks

PMem

22266

PFilling

11TInit

Application Specific

Application Specificspeed and calls it. The default speed for aBlackfin processor is 10 * CLKIN for the coreclock and 2 * CLKIN for the SCLK. After thereturn from initialization subroutine, the bootROM continues the booting process for theremaining code/data in external memory at ahigher speed with the changed settings.
However, the improved booting time comes withan added latency — the loading and running timeof the initialization code, which includes a PLL
relock sequence. In addition, the changed
settings must not exceed the maximum ratings ofthe processor and the flash/SPI serial EEPROM
devices. The limitations are:
Maximum core clock and system clock forBlackfin processors

Minimum setup/access/hold times of flashmemory

Maximum baud rate for the SPI serial
EEPROM

Table 1. Estimation Parameter Summary

Optimization of Boot Time
From the above section, it can be seen that all thecomponents of boot time are proportionallyrelated to the processor’s core/system clock,given the crystal clock and loader file. However,the default clock setting of the processor isdesigned to accommodate the slowest flash/SPI
serial EEPROM devices. Furthermore, the coredoes not run at its maximum frequency bydefault. One solution to expedite the booting
process is to add a short piece of initialization
code which changes the processor’s settings tomake it run the boot process at the maximum
speed. The changeable settings include:PLL’s multiplier select MSEL in the PLL_CTLregister

Clock divider selects (CSEL and SSEL) in the
PLL_DIV register

SPI baud rate setting in the SPI_BAUD register

Asynchronous memory control settings in theEBIU_AMBCTLx registers

The booting process with initialization code isshown in Figure 4. Upon reset, the boot ROM
first loads the initialization code at the default

As a result, a constrained optimization problem
must be solved in order to achieve the shortest
boot time. The BTET, introduced in thefollowing section, can be used to find thesolution.

Figure 4. Booting Process with Initialization Code

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aBooting Time Estimation Tool(BTET)
The booting time estimation tool (BTET.exe) is a
console-based software tool developed to parse
loader files to estimate and optimize bootingtime. Taking a loader file as input, it can provide
thedefault
bootingtimeandgive
recommendations on processor setting changes
needed to achieve the shortest boot time. Bothflash and SPI serial EEPROM boot modes aresupported. The tool is fully controlled by a userdefined configuration file. The user can apply
this tool to the application’s loader file toestimate the time for the system to boot up, andthen use the recommended settings to obtain afaster startup.



MIN_SCLK — Minimum period ofsystem clock in µs

FlashLimit section


FLASH_SETUP — Minimum setup timeof flash in µs

FLASH_ACCESS—Minimumread/write access time of flash in µsFLASH_HOLD — Minimum hold timeof flash in µs

SPIBaudLimit sectionSPIBaudLimit — Maximum SPI baudin MHzLThe configuration file (BTET.cfg) must
be in the same directory as BTET.exe.

BTET Configuration FileAs shown in Appendix A – BTET Configuration
File: BTET.cfg, the configuration file(BTET.cfg) consists of two parts — user-definedvariables, and system-defined variables. Eachgroup is divided into several sections. Users
should change only the user-defined variables,
according to the specific application, and leave
the system-defined variables untouched. The
variables are explained as follows.
BTET can be run in Console page of the Output
window in two ways:
It can take the loader file’s name as its
parameter in the command line, as shown in
Listing 2.

BTET my_loader_file.ldr
Listing 2. BTET Command-Line Example

Mode section


FLASH — Determines whether to do
optimization for flashSPI — Determines whether to do
optimization for SPI serial EEPROM. Ifneither is specified, only analyze theloader file.

Crystal sectionRunning BTET

Tcrystal — Period of crystal clock(CLKIN) in µs

SystemLimit section

MIN_CCLK — Minimum period of coreclock in µs

If the command line does not provide theloader file name, the BTET will prompt youto type it in, as shown in Listing 3.

WARNING: loader file not specified,
type in its name>>>Listing 3. BTET Prompt

BTET Output

BTET outputs its analysis and optimization
results to both the console and to the log file(BTET.log). The explanation of each part of theoutput is illustrated in Appendix B – Output ofBTET.

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aAdding Initialization CodeSample initialization code accompanies thisdocument in the associated .ZIP file[4]. If theadvice given by BTET is taken, the macros in thesample code can be changed to the recommended
settings or customized initialization code can beused.
The initialization code must be compiled into a.dxe file. Then, in VisualDSP++, change theproject’s load options by adding -init
InitCode.dxe in the Additional options fieldof the Project Options dialog box (Figure 5),
which you open by choosing Project Options
from the Project menu.
Figure 5. Adding Init Code to Project

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aAppendix A – BTET Configuration File: BTET.cfg# Configuration for Booting Time Estimation Tool
# Variables needing to be defined in configuration file# if no configuration file is found, the hard-wired values are used
# USER DEFINED VARIABLES #[Mode]
FLASH = 1
# do FLASH optimization
SPI = 1# do SPI optimization# if neither is specified, only analyze the loader file[Crystal]Tcrystal = 0.03
# in us, 1.0/33 us for 33MHz[SystemLimit]
MIN_CCLK = 0.002
MIN_SCLK = 0.011# in us, 1/500.0 us# in us, 1/90.0 us[FlashLimit]
FLASH_SETUP = 0.022
FLASH_ACCESS = 0.036
FLASH_HOLD = 0.011# in us, 22/1000.0 us# in us, 36/1000.0 us# in us, 11/1000.0 us[SPIBaudLimit]
SPIBaudLimit = 1.5# in MHz# SYSTEM DEFINED VARIABLES ## ! DO NOT CHANGE#[InitCode]
PLLCount = 512
InitCodeSize = 202
InitCodeRun = 5076
[KernelNature]
FILL_PER_BYTE = 5
BOOT_FLASH_RUN = 3360
BOOT_SPI_RUN = 90000[DefaultSystemSetting]
MSEL = 10
CSEL = 1
SSEL = 5[DefaultFlashSetting]
FLASH_SETUP = 3
FLASH_ACCESS = 15
FLASH_HOLD = 4[DefaultSPIBaudSetting]
SPIBaudSetting = 133;
[Console]
Quiet = 0
LogFileName = "BTET.log"

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aAppendix B – Output of BTET

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aReferences[1] ADSP-BF533 Blackfin Embedded Processor Data Sheet. Rev C, May 2006. Analog Devices, Inc.
[2] ADSP-BF533 Blackfin Booting Process (EE-240). Rev 3, January 2005. Analog Devices, Inc.
[3] ADSP-BF533 Blackfin Processor Hardware Reference. Rev 3.2, July 2006. Analog Devices, Inc.
[4] Associated .ZIP File (EE-308). Rev 1, November, 2006. Analog Devices, Inc.

Document History
Revision

Description

Rev 1 – December 4, 2006
by Jiang Wu

Initial release.

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