Engineer-to-Engineer NoteaEE-228

Technical notes on using Analog Devices DSPs, processors and development tools
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Switching Regulator Design Considerations for ADSP-BF533 Blackfin®
Processors
Contributed by Bob Libert, Brian Erisman, and Joe Beauchemin

Introduction
The Blackfin® embedded processor’s on-chip
voltage regulator is a switching buck regulator
that requires external components to function
properly. This application note describes howbuck converters work and provides guidelines forchoosing the external components for the control
circuit to work with ADSP-BF531 / ADSPBF532 / ADSP-BF533 Blackfin processors.
Since the design of the internal voltage regulator
is similar to other Blackfin processors, this note
applies to the ADSP-BF534 / ADSP-BF536 /ADSP-BF537 and the ADSP-BF561 processors
as well.

Internal Voltage Regulator
The internal voltage regulator on Blackfin
processors is a buck converter that reduces theinput voltage, which can range from 2.25 V to3.6 V, to the voltage applied to the core, which isprogrammable from 0.8 V to 1.2 V.

Rev 1 – February 2, 2005

A buck converter consists of a switch, aninductor, a diode, a capacitor, and a pulse-widthmodulator (PWM), as shown in Figure 1.
The PWM controller is internal to Blackfin
processors, and the rest of the components areexternal.
A control loop senses the regulator voltage andsets the duty ratio (D) of the PWM to generate
the programmed voltage, where D isapproximately:

As can be seen in this equation, the forward
voltage of the diode (Vd) contributes to bothterms. Variations in the diode’s forward voltage
and input and output voltages cause D to range
from approximately 30% to 63%.

Figure 1. Basic Buck Converter
Figure 2. Internal Voltage Regulator Circuit

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aThe internal voltage regulator circuit (Figure 2)
consists of a voltage reference, an error
amplifier, a ramp generator, a comparator, and adriver.

Another parameter introduced in Figure 5 is theinductor ripple current (∆ILpp). This is the peakto-peak measurement of current values that canbe expected to flow through the inductor.

There are two states for the switch, closed (Ton)and open (Toff), where D is defined as:

The real circuit will also contain a number ofparasitic elements associated with the external
components. The PMOS FET has two parasitic
elements which reduce its efficiency. The first isRDS(on), the resistance between the drain and thesource. The power lost between the drain and thesource (PRDS) is the power dissipated within thechannel of the FET itself, which is present only
during the Ton period, and is simply:

During Ton, the switch connects the supply
voltage (Vin) to the inductor (L), causing thecurrent in the inductor to ramp up.

PRDS = Iload2 * RDS(on) * D

Figure 3. Switch Behavior During Ton

During Toff, the switch is off and the diode turns
on, which results in a negative voltage across theinductor. This, in turn, causes the current todecrease.

The second parameter affecting the FET'sefficiency is its gate charge (QG). The loss due to
QG (PQG) occurs during both switching periods,
when the gate driver charges and discharges thegate (Vgs). The value of PQG depends on theswitching frequency (fSW) and the turn on (Tr)and turn off (Tf) times of the gate, and is definedas:
PQG = fSW * ((Vin/2)*(Iload*(Tr+Tf)) + (QG*Vgs))
The inductor has a DC resistance (RL). The loss
due to RL (PRL) is defined as:

Figure 4. Switch Behavior During Toff

The average current is load current (Iload). The
waveforms for the inductor current (Iinductor) andthe voltage at the input to the inductor (Vin)should resemble Figure 5.

PRL = Iload2 * RL
The largest contributor to overall loss is within
the diode. The diode limits its efficiency (PD)because it has a forward voltage (Vd) that is on
during the Toff time and is dependent on Iload. The
efficiency degradation caused by the diode is
implicit in the equation:
PD = Iload * Vd * (1 – D)

Figure 5. Inductor Wave Forms

The output filter capacitor has a parasitic
inductance (LESL) and resistance (RESR). Parasitic
inductance has no first-order effect on efficiency,
but degrades the filter performance by increasing
the output ripple and raising the burden on otherload bypass capacitors. Parasitic resistance

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adegrades efficiency and directly translates
inductor ripple current into what is usually thedominant component of output ripple voltage.
The power loss due to RESR is given by:
PESR = (∆ILpp 2 * RESR) / 12
Analyzing the loss models for the two switchstates yields two simple observations. Figure 6
shows the equivalent circuit diagram with theswitch on, which eliminates the diode.

Buck converters usually work in what is called
the continuous mode. In the continuous mode ofoperation, the current through the inductor rises
during the Ton state and falls during the Toff state,
and the switching frequency (fSW) spans the twostates:
fSW = 1 / (Ton + Toff)
The voltage regulator runs in continuous mode
during normal Blackfin processor operation (i.e.,
in Full On mode and Active mode).

Figure 6. On-State Loss Model

Figure 6 shows that the switch’s on-state loss isin series with the input source Vin, therefore, anequivalent voltage loss term, Vds, can be
subtracted from the input voltage in the Dequation:

The other mode of operation, discontinuous
mode, is the mode in which there is a period oftime after Toff when there is no current flowing in
the inductor. This occurs when the Blackfin
processor is in a low-power state with a low
voltage on the core supply. Usually, this is amode to be avoided because it changes the loop
characteristics. Figure 8 shows the impact on
inductor current for the two modes of operation:

Similarly, Figure 7 depicts the equivalent circuitdiagram with the switch open:

Figure 7. Off-State Loss Model

Here, the observation can be made that theoutput inductance loss is in series with theoutput, so an equivalent voltage loss term can beadded to the output, and is simply the inductor’sequivalent resistance (RL) multiplied by the load
current (Iload). Thus, the D equation becomes:

Figure 8. Continuous IL vs Discontinuous IL

In the discontinuous plot above, the space
between Toff and the subsequent Ton is referred toas “dead time”.

Switching Regulator Design Considerations for ADSP-BF533 Blackfin® Processors (EE-228)

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aExternal Component Selection

Inductor

The four external components of the regulator
and the bypass capacitor on the input supply
voltage need to be chosen to fit the operation of
the Blackfin processor’s internal switchingregulator. Tradeoffs can be made with respect tocost or efficiency. Each component has parasiticelements. Reducing these parasitics usually
improves efficiency, but may add cost.

Given a pre-selected switching frequency andfixed PWM control, the inductor controls theamount of current ripple, the response of thecontrol loop, and whether the regulator runs incontinuous mode or discontinuous mode. The
minimum value for the inductor (Lmin) can becalculated from the following equation:

Power Transistor (FET)The gate drive inside the Blackfin processor’s
internal regulator was designed to provide amaximum drive current of 200 mA. A smallinternal current-limiting resistor, parasitics frombond wires, and package leads limit the actual
charge time and reduce the efficiency. The FET
to be chosen should have a gate charge (QG) ofless than 20 nC.
The other critical parameter of the FET is its
RDS(on). In general, lower is better; however,since the supply voltage (Vgs) can vary from
2.25 V to 3.6 V, be sure to examine the RDS(on)vs. Vgs curve in the FET data sheet. Check theRDS(on) component for the minimum Vgs.
The breakdown voltage (BVDSS) should not be aproblem, since most FETs have breakdowns
greater than 12 V. Since the maximum Vin is
3.63 V, the expected diode voltage should resultin a total voltage of around 4 V. Being ultraconservative, the specified BVDSS should exceed
roughly twice this value. The power dissipationon the switch should be specified to be greaterthan 0.5 W.
In summary, the FET should meet theseminimum requirements:RDS(on) @Vgs = 2.5V or less

< 0.2Ω

Gate charge< 20nCPower dissipation> 0.5W

BVDSS> 10V

Recall that the ∆ILpp term is the peak-to-peakmagnitude of the ripple current in the inductor,
which, under steady-state conditions, is thecurrent that flows into the output capacitor.
Under steady-state conditions, the duty ratio (D)is adjusted by the feedback loop in such a waythat the magnitude of ramp-up and ramp-downcurrents in the inductor will be equal (Figure 8).
However, note that a minimum load current isnecessary to keep the regulator in continuous
mode. This current is known as the criticalcurrent, and is represented as Icritical. Figure 9
depicts how Icritical relates to ∆ILpp:

Figure 9. Inductor Current

For minimal inductance values, ∆ILpp is assumed
to be twice Icritical.
Because of the wide range of operating
conditions, the choice of inductor involves somecompromise. The calculated values for all loadconditions range from 0.9 µH to 68 µH. One
value will not allow continuous operation or fast
response to transients. A 10 µH inductor waschosen to cover most of the operating range atthe 1 MHz default clock frequency.

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aChoosing the inductor value alone is not
sufficient, as there are other parameters thatshould also be considered when selecting theinductor for the regulator circuit.
Minimize the DC resistance in the inductor (RL)
to about 0.1-0.25 Ω (typical). The inductor’sresistance (RL) and load impedance (R) also
affect the DC gain.
The RMS current rating (Irms) must be able tohandle the maximum current expected from theBlackfin processor. Refer to the application note
Estimating Power for ADSP-BF533 Blackfin
Processors (EE-229) [1] for details regarding how
to compute this value.
The saturation current (Isat) must be greater thanthe Irms plus ½ ∆ILpp plus a safety margin. Some
Isat maximum specifications state that themaximum is when the inductance is reduced by10%.
Finally, the inductor should be specified for
1 MHz to support all three programmableswitching frequencies.
Capacitors

Two capacitors must be specified, each with its
own requirements.
The first capacitor is the power supply bypass
capacitor. Because of the switching transientsthat may adversely affect the power supply, alow ESR (RESR), >68 µF electrolytic capacitor
and a 0.01 µF (or 0.1 µF) ceramic capacitor must
be connected as close as possible to the source ofthe switching FET.
The filter capacitor should have RESR in the rangeof 20 to 40 mΩ, because the RESR adds zero tothe loop response, which cancels one of the LCpoles. This restriction is true by virtue of voltage
mode control use:

The RESR also contributes to the ripple:∆Vout = ∆ILpp * RESR
One equation for the minimum value (Cmin) of
the filter capacitor is:

However, since the value of the capacitor also
affects the loop response, a minimal value may
cause excess ripple and/or oscillations. To meetthe loop response criteria and provide goodtransient response, the inductor value should benear its minimum and the capacitor/inductor poleshould be set to about 10 kHz. The zero from theRESR and capacitor should be about three to fivetimes the pole frequency.
DiodeA Schottky diode is recommended to reduce theloss associated with the forward diode voltage(Vd), although any switching diode can be usedwith a reduction in efficiency. The diode should
also be able to handle the maximum load current.

Design Example
The following is a sample design that can beused as a reference. The sample has thefollowing parameters:Vin = 3.3V
Vout = 1.2V (default)
fSW = 1MHz (default)
Iload = 300mA∆ILpp = 30% of Iload (ripple current)∆Vout <10mV (ripple voltage)
RL = 0.046Ω
RDS(on) = 0.18Ω
QG = 8.5nC

Switching Regulator Design Considerations for ADSP-BF533 Blackfin® Processors (EE-228)

Page 5 of 8aTr = Tf = 35ns
Vd = 375mV
RESR = ~60mΩ
Some of the above specifications are taken fromdata sheets of specifically chosen components.
For this design example, the following
components are being used:
Inductor – Miller PM3316 15µH [2]Note that this D value falls within the expected
range of 30% to 63%.
The second unknown in the Lmin equation is theripple current:∆ILpp = 30% * Iload∆ILpp = 0.3 * 300mA = 90mA
This value can be substituted into the Lminequation along with D:

FET – Fairchild FDS9431A [3]Diode – Zetex ZHCS1000 [4]Capacitor – Tantalum 100µF
From this particular design example’s sample
characteristics and the specifications given by thechosen components, the theories discussed in thisnote can be applied to obtain values forminimum inductance (Lmin) and minimum
capacitance (Cmin).
From there, the polefrequency (Fpole), the capacitor and RESR zerofrequency (Fzero), and efficiency (η) can becalculated as well.

Lmin > 10.27µΗ
A 15 µH inductor satisfies the above Lminrequirement. If a 15 µH inductor is chosen, theripple current then becomes:

In addition to the parameters detailed above, theduty ratio and ripple current must first be
obtained before using the given equations for theinductor and capacitor.
Before solving for D, Vds must first be obtained:
Vds = Iload * RDS(on)Vds = 300mA * 0.18Ω
Vds = 54mV

∆ILpp = 62mA
Now the minimum capacitance can be computed.
Knowing that the 10 mV specification is amaximum voltage ripple number, the Cminequation can be used:

This Vds value is then substituted into the Dequation:

Cmin = 6.2µF
D = 0.44

The transient response depends on the output
impedance of the filter (Z), which is:

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PRDS = 300mA * 0.18Ω * 0.44
PRDS = 7.1mW
Computing PQG:
Z = 1.56Ω
To reduce the output impedance and improve thetransient response, the cap is increased to100 µF. Z then becomes 0.39 Ω.
Next, the pole (Fpole) can be calculated:

PQG = fSW * ((Iload * (Tr + Tf)) + (QG *Vgs))
PQG = 1MHz*((300mA*(35ns+35ns))+(8.5nC*3.3V))
PQG = 49mW
Computing PRL:PRL = Iload2 * RL
PRL = 300mA2 * 0.046Ω
PRL = 4.1mW
Computing PD:
PD = Iload * Vd * Toff

Fpole = 4109 Hz = ~5kHzAnd the zero (Fzero) becomes:

PD = 300mA*375mV*(1-0.44)
PD = 63mW
Computing PESR:PESR = (∆ILpp 2 * RESR) / 12
PESR = (62mΑ2 * 60mΩ) / 12
PESR = 0.02mW

Fzero = 26.5kHz
These Fpole and Fzero values are within the desired
limit for stability.
To address efficiency, the total power loss in thecircuit must be accounted for and subtracted
from the total power output (Pout) at the load:

The final loss comes from the power required todrive the PWM switcher itself (PLPWM), which is
0.5 mW. Taking all these losses into
consideration, the total power loss (PLTOT) canbe described by the following:
PLTOT = PRDS + PQG + PRL + PD + PESR + PLPWM

Pout = Vout * Iload

PLTOT= (7.1 + 49 + 4.1 + 63 + 0.02 + 0.5)mW

Pout = 1.2V * 300mA

PLTOT= 124mW

Pout = 360mW
The losses in the circuit, as described previously,
are PRDS, PQG, PRL, PD, and PESR.
Computing PRDS:
PRDS = Iload2 * RDS(on) * D

After calculating the total power loss, theefficiency (η) of the circuit can be calculated:η = Pout / (Pout + PLTOT)
η = 360mW / (360mW + 124mW)
η = 74.4%

Switching Regulator Design Considerations for ADSP-BF533 Blackfin® Processors (EE-228)

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aThe efficiency will be lower at low load currents
because the 49 mW switching loss is independentof load.

connected to the same supply. The connection
paths to the FET's drain, the diode, inductor, andcapacitors should be as short as possible and able
to handle the load current.

Board Layout Considerations

The same is true for the ground connections,since they will carry the same load currents as
the supply during the Toff time (the load current
through the diode) and the gate switching current
during Ton.

The board layout must minimize the connection
between the VROUT[1:0] pins and the gate pin of
the FET. The trace resistance and inductancemust be low enough to handle 1 MHz switching
speeds and 200 mA of switching current. The
traces to and from the FET's source and theVDDEXT supply pin on the Blackfin processor
should, if possible, be Kelvined to their power
supply to avoid transient effects on other devices

Lastly, locate the electrolytic capacitors at theFET source and the output side of the inductor.
Add ceramic 0.1 or 0.01 µF capacitors in parallel
to reduce the high frequency impedance.

References[1] Estimating Power for ADSP-BF533 Blackfin® Processors (EE-229). Rev 1, February 2004. Analog Devices, Inc.
[2] PM3316-100M Inductor Data Sheet. J.W. Miller Magnetics.
[3] FDS9431A P-Channel 2.5V Specified MOSFET Data Sheet. September 1999. Fairchild Semiconductor.
[4] ZHCS1000 Schottky Rectifier Diode Data Sheet. Zetex Semiconductors.

Document History
Revision

Description

Rev 1 – February 2, 2005
by Bob Libert, Brian Erisman,and Joe Beauchemin

Initial Release

Switching Regulator Design Considerations for ADSP-BF533 Blackfin® Processors (EE-228)

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