SHARC+ Single CoreHigh Performance DSP (Up to 1 GHz)ADSP-21562/21563/21565/21566/21567/21569
SYSTEM FEATURESMEMORY

Enhanced SHARC+ high performance floating-point core
Up to 1 GHz
5 Mb (640 kB) Level 1 (L1) SRAM memory with parity(optional ability to configure as cache)32-bit, 40-bit, and 64-bit floating-point support
32-bit fixed point
Byte, short word, word, long word addressed
Powerful DMA system
On-chip memory protection
Integrated safety features
17 mm × 17 mm, 400-ball CSP_BGA (0.8 mm pitch), RoHS
compliant
120-lead LQFP_EP (0.4 mm pitch), RoHS compliant
Low system power across automotive temperature range

Large on-chip Level 2 (L2) SRAM with ECC protection, up to
8 Mb (1 MB)
One Level 3 (L3) interface optimized for low system power,
providing 16-bit interface to DDR3/DDR3L SDRAM devices

ADDITIONAL FEATURES
Security and Protection
Crypto hardware accelerators
Fast secure boot with IP protection
Enhanced FIR and IIR accelerators running up to 1 GHz
AEC-Q100 qualified for automotive applications

APPLICATIONS
Automotive: audio amplifier, head unit, ANC/RNC, rear seatentertainment, digital cockpit, ADAS
Consumer: speakers, sound bars, AVRs, conferencing systems, mixing consoles, microphone arrays, headphones

SYSTEM CONTROLSECURITY AND PROTECTIONSHARC+ CORE

SYSTEM PROTECTION UNIT (SPU)SYSTEM MEMORYPROTECTION UNIT (SMPU)
ENCRYPTION/DECRYPTION

UP TO
1 GHz
FLOATING-POINTDSPSDUAL CRC (WITH MemDMA)PERIPHERALSACCELERATORSFAULT MANAGEMENT (FMU)

SIGNAL ROUTING UNIT (SRU)
FIR

IIR

(UP TO
1 GHz)(UP TO
1 GHz)

2×2 PRECISION CLOCK
GENERATORSL1 SRAM (PARITY)

WATCHDOGS

5 Mb (640 kB)

OTP MEMORY

SRAM/CACHE

2×4 ASRCPAIRS

THERMAL MONITOR UNIT (TMU)

6× I2CSYSTEM CROSSBAR AND DMA SUBSYSTEM

1× SPI + 2× QUAD SPI +1× OCTAL SPI

TRIGGER ROUTING UNIT (TRU)
3× UARTs
2× LINK PORTS

CLOCK, RESET, AND POWER
CLOCK GENERATION UNIT (CGU)
CLOCK DISTRIBUTION UNIT (CDU)
RESET CONTROL UNIT (RCU)
DYNAMIC POWER MANAGEMENT
(DPM)

24–28

2×1 S/PDIF Rx/Tx

PROGRAM FLOWSYSTEM EVENT CONTROLLER(SEC)

2x DAI
FULL SPORT 2x PIN
2×4
BUFFER

L3 MEMORY
INTERFACESSYSTEM
L2 MEMORY

DDR3/DDR3L

SRAM
(ECC)
UP TO 8 Mb (1 MB)

G
P
I
O

22–40

10× TIMERS + 1× COUNTER
4× CORE FLAGS I/O

BGA ONLY

MLB 3-PIN
HADC (4 CHAN, 12-BIT)
2–4

DEBUG UNIT
Arm ® CoreSightTM
DEBUG AND TRACE

16
DATA

SYSTEM WATCHPOINT UNIT
(SWU)

Figure 1. ADSP-21569 (Full-Featured Model) Processor Block Diagram
SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. D

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implicationor otherwise under any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the property of their respective owners.

One Analog Way, Wilmington, MA 01887 U.S.A.
©2023 Analog Devices, Inc. All rights reserved.

Technical Support

www.analog.com

ADSP-21562/21563/21565/21566/21567/21569
TABLE OF CONTENTS
System Features ....................................................... 1

ADSP-2156x Designer Quick Reference ....................... 36

Memory ................................................................ 1

Specifications ........................................................ 44

Additional Features .................................................. 1

Operating Conditions ........................................... 44

Applications ........................................................... 1

Electrical Characteristics ....................................... 47

Table of Contents ..................................................... 2

HADC .............................................................. 51

Revision History ...................................................... 2

TMU ................................................................ 51

General Description ................................................. 3

Absolute Maximum Ratings ................................... 52

SHARC Processor ................................................. 4

ESD Caution ...................................................... 52

SHARC+ Core Architecture .................................... 6

Timing Specifications ........................................... 53

System Infrastructure ............................................. 8

Output Drive Currents ......................................... 86

System Memory Map ............................................. 8

Test Conditions .................................................. 87

Security Features ................................................ 11

Environmental Conditions .................................... 88

Security Features Disclaimer .................................. 12

ADSP-2156x 400-Ball BGA Ball Assignments ................ 89

Safety Features ................................................... 12

Numerical by Ball Number .................................... 89

Processor Peripherals ........................................... 13

Alphabetical by Pin Name ..................................... 92

System Acceleration ............................................ 16

Configuration of the 400-Ball CSP_BGA ................... 95

System Design .................................................... 16

ADSP-2156x 120-Lead LQFP Lead Assignments ............ 96

System Debug .................................................... 19

Numerical by Lead Number ................................... 96

Development Tools ............................................. 19

Alphabetical by Pin Name ..................................... 97

Additional Information ........................................ 20
Related Signal Chains .......................................... 20

Configuration of the 120-Lead LQFP Lead
Configuration .................................................. 98

ADSP-2156x Detailed Signal Descriptions ................... 21

Outline Dimensions ................................................ 99

400-Ball CSP_BGA Signal Descriptions ....................... 24

Surface-Mount Design ........................................ 100

GPIO Multiplexing for 400-Ball CSP_BGA Package ....... 30

Automotive Products ............................................ 101

120-Lead LQFP Signal Descriptions ........................... 32

Ordering Guide ................................................... 102

GPIO Multiplexing for 120-Lead LQFP Package ............ 35

REVISION HISTORY
6/2023—Rev. C to Rev. D
Changes to Footnote 2 and Footnote 3 in LPs—Receive ... 55
Change to coplanarity dimension from 0.12 mm to 0.20 mm
for BC-400-3 BGA in Outline Dimensions ................... 99

Rev. D |Page 2 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
GENERAL DESCRIPTIONSHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous
SHARC products.

Reaching speeds of up to 1 GHz, the ADSP-2156x processors
are members of the SHARC® family of products. The ADSP2156x processor is based on the SHARC+® single core. The
ADSP-2156x SHARC processors are members of the SIMDSHARC family of digital signal processors (DSPs) that feature
Analog Devices, Inc., Super Harvard Architecture. These 32bit/40-bit/64-bit floating-point processors are optimized forhigh performance audio/floating-point applications with large
on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, andinnovative digital audio interfaces (DAI). New additions to the

By integrating a rich set of industry-leading system peripherals
and memory (see Table 1), the SHARC+ processor is the platform of choice for applications that require programmability
similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one
integrated package. These applications span a wide array ofmarkets, including automotive, professional audio, and industrial-based applications that require high floating-point
performance.

Table 1. Processor Features1
Processor Feature
SHARC+ Core (MHz Maximum)2
SHARC L1 SRAM (kB)
System Memory
L2 SRAM (kB)
DDR3 and DDR3L Controller (16-Bit)
DAI (Includes SRU)
Full SPORTs
S/PDIF Rx/Tx
ASRCs
Precision Clock Generators
Buffers
Hardware Accelerators
FIR/IIR
Security Crypto Engine
I2C (TWI)SPI
Quad SPI
Octal SPI
UARTs
Link Port
General-Purpose Timer3
General-Purpose Counter
Multichannel 12-bit ADC
Watchdog Timer
MLB 3-pin
GPIO Ports
GPIO + DAI Pins
Package Options

ADSP-21562 ADSP-21563 ADSP-21565 ADSP-21566 ADSP-21567 ADSP-21569
400
600, 800
800, 1000
400
600, 800
800, 1000
640
256

512
N/A

1024

256

512
1

2
2×4
2×1
2×4
2×2
2 × 12

2 × 14
Yes
Yes

4

6
1
2
1

2
0
6

3
2
10
1

2-ch

4-ch
2
Automotive models only

Port A to Port B
22 + 24120-lead LQFP_EP

1

N/A means not applicable.
The values refer to different speed grades.
3
Refer to Table 14 for internal timer signal routing.
2

Rev. D |Page 3 of 102 |June 2023

Port A to Port C
40 + 28400-ball CSP_BGA1024

ADSP-21562/21563/21565/21566/21567/21569
SHARC PROCESSORThe SHARC processor supports a modified Harvard architecture in combination with a hierarchical memory structure. L1
memories typically operate at the full processor speed with little
or no latency.

The SHARC processor integrates a SHARC+ SIMD core, L1
memory crossbar, I-cache/D-cache controller, L1 memory
blocks, and the requester/completer ports, as shown in Figure 2.
The SHARC+ SIMD core block diagram is shown in Figure 3.

B2
RAM

B2
B1
RAM

S

P-CACHE
B0
RAM
B2
RAM

SIMD Processor
CCLK DOMAIN

B0 (64)B3RAM

B1 (64)

D-CACHEP-CACHEB2 (64)

P-CACHED-CACHEB3 (64)

I-CACHEI/O (32)COMPLETER
PORT 1

I/O (32)

INTERNAL MEMORY INTERFACE (IMIF)I-CACHE/D-CACHE CONTROLCOMPLETER
PORT 2(MDMA ANDACCELERATORS)

PM (64)

DM (64)I/O (32)

I/O (32)

SYSTEM FABRICSYSCLK
DOMAIN

CORE
MMR
(32)
DM (64)
CMD (64)
REQUESTER
PORT DATA

PM (64)®

SHARC+SIMD CORE

CMI (64)

PS (64/48)
REQUESTER
PORT INSTRUCTION

INTERRUPTSYSTEM
EVENT
CONTROLLER

Figure 2. SHARC Processor Block Diagram

The SRAM of the processor can be configured as a maximum of
160k words of 32-bit data, 320k words of 16-bit data,
106.7k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 5 Mb. All of the memory
can be accessed as 8-bit, 16-bit, 32-bit, 48-bit, or 64-bit words.
Support of a 16-bit floating-point storage format doubles theamount of data that can be stored on chip.

L1 Memory
Figure 4 shows the ADSP-2156x memory map. The SHARC+
core has a tightly coupled 5 Mb L1 SRAM. The SHARC+ core
can access code and data in a single cycle from this memory
space.
In the SHARC+ core private address space, the core has L1
memory.
SHARC+ core memory-mapped register (CMMR) address
space is 0x0000 0000 through 0x0003 FFFF in normal word
(32-bit). Each block can be configured for different combinations of code and data storage. Of the 5 Mb SRAM, up to 1 Mb
can be configured for data memory (DM), program memory(PM), and instruction cache each. Each memory block supports
single-cycle, independent accesses by the core processor and I/Oprocessor. The memory architecture, in combination with its
separate on-chip buses, allows two data transfers from the coreand one from the direct memory access (DMA) engine in asingle cycle.

Rev. D |Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. Whereas
each memory block can store combinations of code and data,
accesses are most efficient when one block stores data using the
DM bus for transfers, and the other block stores instructions
and data using the PM bus for transfers.
Using the DM and PM buses, with each bus dedicated to amemory block, assures single-cycle execution with two datatransfers. In this case, the instruction must be available in thecache. The system configuration is flexible, but a typical configuration is 512 kb DM, 128 kb PM, and 128 kb of instruction

Page 4 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
S
SIMD Core

DEBUG
TRACE

BTB
BP

CEC

FLAGS

CONFLICTCACHEPM DATA 48

DMD/PMD 64

11-STAGE
PROGRAM SEQUENCER
PM ADDRESS 24

DAG1
16 × 32DAG2
16 × 32
PM ADDRESS 32
SYSTEM
I/F

DM ADDRESS 32
PM DATA 64

TO
IMIF

USTAT
PX

DM DATA 64

MULTIPLIER

MRF
80-BITSHIFTER

MRB
80-BIT

ALU

PEx
DATA
REGISTER
Rx
16 × 40-BIT

DATA
SWAP

PEy
DATA
REGISTER
Sx
16 × 40-BIT

ASTATxASTATy

STYKx

STYKy

ALU

SHIFTER

MULTIPLIER

MSB
80-BIT

MSF
80-BIT

Figure 3. SHARC+ SIMD Core Block Diagram

cache, with the remaining L1 memory configured as SRAM.
Each addressable memory space outside the L1 memory can beaccessed either directly or via cache.

L1 On-Chip Memory Bandwidth

The memory map in Table 2 gives the L1 memory address spaceand shows multiple L1 memory blocks offering a configurable
mix of SRAM and cache.

The internal memory architecture allows programs to have fouraccesses at the same time to any of the four blocks, assuming noblock conflicts. The total bandwidth is realized using both the
DMD and PMD buses (2 × 64-bits CCLK speed and 2 × 32-bit
SYSCLK speed).

L1 Requester and Completer Ports

Instruction and Data Cache

The SHARC+ core has two requester/completer ports to andfrom the system fabric. One requester port fetches instructions.
The second requester port drives data to the system world.
Completer Port 1 together with Completer Port 2 memory
direct memory access (high speed MDMA) run conflict freeaccess to the individual memory blocks. For the completer portaddresses, refer to the L1 memory address map in Table 2.

The ADSP-2156x processors also include a traditional instruction cache (I-cache) and two data caches (D-caches, one eachfor PM/DM) with parity support for all caches. These caches
support one instruction access and two data accesses over the
DM and PM buses per CCLK cycle. The cache controllers automatically manage the configured L1 memory. The system canconfigure part of the L1 memory for automatic management by
the cache controllers. The sizes of these caches are independently configurable from 0 to 128 kB each. The memory not
managed by the cache controllers is directly addressable by theprocessors. The controllers ensure the data coherence between

Rev. D |Page 5 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
SHARC+ CORE ARCHITECTURE
0x FFFF FFFF

The ADSP-2156x processors are assembly code compatible withall previous SHARC processors featuring the SHARC or
SHARC+ core, beginning with the first generation ADSP-2106x
SHARC processors and including the ADSP-2116x, ADSP2126x, ADSP-213xx, ADSP-214xx, and ADSP-SC5xx/ADSP215xx processors.

RESERVED
0x C000 0000
DMC0 (1GB)
0x 8000 0000
SPI2/OSPI0 FLASH ADDRESS SPACE (512MB)
0x 6000 0000
0x 5000 0000

The SIMD architecture featured on the ADSP-2156xprocessors
is identical to all previous SIMD SHARC processors, namely the
ADSP-2116x, ADSP-2126x, ADSP-213xx, ADSP-214xx, and
ADSP-SC5xx/ADSP-215xx processors, as shown in Figure 3
and as described in the following sections.

0x 4C00 0000
RESERVED
0x 4800 0000
0x 4400 0000
0x 4000 0000

RESERVED

0x 2840 0000
0x 2824 0000

SHARC1 L1 ADDRESS SPACE VIACOMPLETER PORT 1/COMPLETER PORT 2
RESERVEDUNIFIED BYTE ADDRESS SPACESYSTEM MMR
0x 3000 0000

Single-Instruction, Multiple Data (SIMD) Computational
EngineThe SHARC+ core contains two computational processing elements that operate as a single-instruction, multiple data (SIMD)
engine.
The processing elements are referred to as PEx and PEy, eachcontaining an arithmetic logic unit (ALU), multiplier, shifter,and register file. PEx is always active, and PEy is enabled by setting the PEYEN mode bit in the mode control register(MODE1).

0x 202B FFFF
0x 2028 0000
RESERVED
0x 2011 8000
L2 BOOT ROM 2 (0.25Mb)

SIMD mode allows the processors to execute the same instruction in both processing elements, but each processing element
operates on different data. This architecture efficiently executes
math intensive DSP algorithms. In addition to all the features ofprevious generation SHARC cores, the SHARC+ core also provides a new and simpler way to execute an instruction only on
the PEy data register.

0x 2011 0000
L2 BOOT ROM 1 (0.25Mb)
0x 2010 8000
L2 BOOT ROM 0 (0.25Mb)
0x 2010 0000
L2 SRAM (8Mb)
0x 2000 0000
RESERVED
0x 0039 FFFF
L1 BLOCK 3 SRAM (1Mb)

SIMD mode also doubles the bandwidth between memory andthe processing elements, as required for sustained computational operation of two processing elements. When using thedata address generators (DAGs) to transfer data in SIMD mode,two data values transfer with each memory or register fileaccess.

0x 0038 0000
0x 0031 FFFF
L1 BLOCK 2 SRAM (1Mb)
0x 0030 0000
RESERVED
0x 002E FFFFSHARC PRIVATEADDRESS SPACERESERVED

L1 BLOCK 1 SRAM (1.5Mb)
0x 002C 0000

Independent Parallel Computation UnitsRESERVED
0x 0026 FFFF
L1 BLOCK 0 SRAM (1.5Mb)
0x 0024 0000
0x 0000 0000

RESERVED/CORE MMRs/
OTHER MEMORY ALIASES

Figure 4. ADSP-2156x Memory Map

the two data caches. The caches provide user controllable features such as full and partial locking, range bound invalidation,and flushing.

Core Memory-Mapped Registers (CMMR)
The core memory-mapped registers control the L1 instruction
and data cache, branch target buffer (BTB), parity error, system
control, debug, and monitor functions.

Rev. D |Within each processing element is a set of pipelined computational units. The computational units consist of a multiplier, an
ALU, and a shifter. These units are arranged in parallel, maximizing computational throughput. These computational units
support IEEE 32-bit single-precision floating-point; 40-bit
extended-precision floating-point; IEEE 64-bit double-precision floating-point; and 32-bit fixed-point data formats.
A multifunction instruction set supports parallel execution of
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing elements per core.
All processing operations take one cycle to complete. For all
floating-point operations, the processor takes two cycles tocomplete in case of data dependency. Double-precision floating-point data take two to six cycles to complete. The processor
stalls for the appropriate number of cycles for an interlocked
pipeline plus data dependency check.

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ADSP-21562/21563/21565/21566/21567/21569
Core Timer
The SHARC+ processor core includes an extra timer. This extra
timer is clocked by the internal processor clock and is typicallyused as a system tick clock for generating periodic operating
system interrupts.

Data Register File
Each processing element contains a general-purpose data register file. The register files transfer data between the computation
units and the data buses, and store intermediate results. These
10-port, 32-register register files (16 primary, 16 secondary),
combined with the enhanced Harvard architecture of the processor, allow unconstrained data flow between computation
units and internal memory. The registers in the PEx data register file are referred to as R0–R15 and in the PEy data register fileas S0–S15.

Context Switch

Additionally, the double-precision floating-point instruction set
is new to the SHARC+ core, as compared with the previous
SHARC core.

Variable Instruction Set Architecture (VISA)
In addition to supporting the standard 48-bit instructions fromprevious SHARC core processors, the SHARC+ core processors
support 16-bit and 32-bit opcodes for many instructions, formerly 48-bit in the ISA. This variable instruction set
architecture (VISA) feature drops redundant or unused bits
within the 48-bit instruction to create more efficient and compact code. The program sequencer supports fetching these
16-bit and 32-bit instructions from both internal and external
memories. VISA is not an operating mode; rather, it is address
dependent (refer to the ISA/VISA address spaces in Table 5).
Finally, the processor allows jumps between ISA and VISA
instruction fetches.

Single-Cycle Fetch of Instructional Four Operands

Many of the registers of the processor have secondary registers
that can activate during interrupt servicing for a fast context
switch. The data, DAG, and multiplier result registers have secondary registers. The primary registers are active at reset,
whereas control bits in MODE1 activate the secondary registers.

Universal Registers
General-purpose tasks use the universal registers. The four universal status (USTAT) registers allow easy bit manipulations(set, clear, toggle, test, XOR) for all control and status peripheral
registers.
The data bus exchange register (PX) permits data to passbetween the 64-bit PM data bus and the 64-bit DM data bus or
between the 40-bit register file and the PM or DM data bus.
These registers contain hardware to handle the data widthdifference.

Data Address Generators (DAG) With Zero Overhead
Hardware Circular Buffer Support
For indirect addressing and implementing circular data buffersin hardware, the ADSP-2156x processor uses two data address
generators (DAGs). Circular buffers allow efficient programming of delay lines and other data structures required in digital
signal processing and are commonly used in digital filters andfast Fourier transforms (FFT). The DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16primary register sets and 16 secondary sets). The DAGs automatically handle address pointer wraparound, reduce overhead,
increase performance, and simplify implementation. Circularbuffers can start and end at any memory location.

Flexible Instruction Set Architecture (ISA)The ADSP-2156x processors feature an enhanced Harvardarchitecture in which the DM bus transfers data and the PM bus
transfers both instructions and data.
With the separate program memory bus, data memory buses,
and on-chip instruction conflict cache, the processor can simultaneously fetch four operands (two over each data bus) and one
instruction from the conflict cache in a single cycle.

Core Event Controller (CEC)The SHARC+ core event controller (CEC) can be configured toservice various interrupts generated by the core (including
arithmetic and circular buffer instruction flow exceptions) andsystem event controller (SEC) events (peripheral interrupt
request, debug or monitor, and software-raised), responding
only to interrupts enabled in the IMASK register. The output of
the SEC is forwarded to the CEC to respond directly to any
enabled system interrupts. For all SEC channels, the processor
automatically stacks the arithmetic status (ASTATx and
ASTATy) registers and mode (MODE1) register in parallel withinterrupt servicing.

Instruction Conflict Cache
The processors include a 32-entry instruction cache that enables
three-bus operation for fetching an instruction and four data
values. The cache is selective—only the instructions that require
fetches conflict with the PM bus data access cache. This cacheallows full speed execution of core looped operations, such as
digital filter multiply accumulates and FFT butterfly processing.
The conflict cache serves for bus conflicts within the SHARC+
core only.

Addressing Spaces

The flexible instruction set architecture (ISA), a 48-bit instruction word, accommodates various parallel operations for
concise programming. For example, the processors can conditionally execute a multiply, an add, and a subtract in bothprocessing elements while branching and fetching up to four
32-bit values from memory—all in a single instruction.

Rev. D |In addition to traditionally supported long word, normal word,
extended precision word, and short word addressing aliases, theprocessors support byte addressing for the data and instructionaccesses. The enhanced ISA/VISA provides new instructions foraccessing all sizes of data from byte space, as well as converting
word addresses to byte addresses and byte addresses to word
addresses.

Page 7 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
Branch Target Buffer (BTB)/Branch Predictor (BP)Implementation of a hardware-based branch predictor (BP) andbranch target buffer (BTB) reduce branch delay. The program
sequencer supports efficient branching using the BTB for conditional and unconditional instructions.

SHARC Fabricsupport concurrent access to the L2 memory ports. Memory
accesses to the L2 memory space are multicycle accesses by the
SHARC+ core.
The memory space is used for various situations including• Accelerator and peripheral sources and destination memory to avoid accessing data in the external memory• A location for DMA descriptors

The FIR/IIR accelerators on the ADSP-2156x processors areintegrated closely with the SHARC+ core with the help of a dedicated SHARC fabric and run at CCLK speed. This allows the
FIR/IIR accelerator requester ports to directly access the
SHARC L1 memory with reduced latency, as these accesses do
not go through the main system fabric. These accesses are arbitrated between both the SHARC+ core completer ports.The
SHARC+ core can also access the FIR/IIR accelerator MMR registers directly.

See the System Memory Protection Unit (SMPU) section for
options in limiting access by the core and DMA requesters.

Additional Features

One Time Programmable Memory (OTP)

To enhance the reliability of the application, L1 data RAMs support parity error detection for every byte, and illegal opcodes arealso detected (core interrupts flag both errors). Requester portsof the core also detect failed external accesses.

The processors feature 7 kb of one time programmable (OTP)
memory that is memory-map accessible. This memory can be
programmed with custom keys and supports secure boot andsecure operation.

SYSTEM INFRASTRUCTURE

I/O Memory Space

The following sections describe the system infrastructure of the
ADSP-2156x processors.

• Storage for additional data for the SHARC+ core to avoid
external memory latencies and reduce external memory
bandwidth• Storage for data coefficient tables cached by the
SHARC+ core

Mapped I/Os include SPI2 or OSPI0 memory address spaces(see Table 5).

System L2 Memory
A system L2 SRAM memory of up to 8 Mb (1 MB) is available to
the SHARC+ core and the system DMA channels (see Table 3).
The L2 SRAM block is subdivided into up to eight banks to

SYSTEM MEMORY MAP
Table 2. L1 Block 0, Block 1, Block 2, and Block 3 SHARC+® Addressing Memory Map (Private Address Space)
Memory
L1 Block 0 SRAM
(1.5 Mb)
L1 Block 1 SRAM
(1.5 Mb)
L1 Block 2 SRAM
(1 Mb)
L1 Block 3 SRAM
(1 Mb)Long Word (64 Bits)
0x00048000–
0x0004DFFF
0x00058000–
0x0005DFFF
0x00060000–
0x00063FFF
0x00070000–
0x00073FFF

Extended Precision/
ISA Code (48 Bits)
0x00090000–
0x00097FFF
0x000B0000–
0x000B7FFF
0x000C0000–
0x000C5554
0x000E0000–
0x000E5554

Rev. D |Normal Word (32 Bits)
0x00090000–
0x0009BFFF
0x000B0000–
0x000BBFFF
0x000C0000–
0x000C7FFF
0x000E0000–
0x000E7FFF

Page 8 of 102 |June 2023

Short Word/
VISA Code (16 Bits)
0x00120000–
0x00137FFF
0x00160000–
0x00177FFF
0x00180000–
0x0018FFFF
0x001C0000–
0x001CFFFF

Byte Access (8 Bits)
0x00240000–
0x0026FFFF
0x002C0000–
0x002EFFFF
0x00300000–
0x0031FFFF
0x00380000–
0x0039FFFFADSP-21562/21563/21565/21566/21567/21569
Table 3. L2 Memory Addressing Map
Byte Address Space
Memory1
SHARC+ Data Access
L2 RAM (2 Mb) 0x200C0000–
0x200FFFFF
L2 RAM (4 Mb) 0x20080000–
0x200FFFFF
L2 RAM (8 Mb) 0x20000000–
0x200FFFFF
SHARC/DMA:
L2 Boot ROM0 0x20100000–0x20107FFF
L2 Boot ROM1 0x20108000–
0x2010FFFF
L2 Boot ROM2 0x20110000–
0x20117FFF
1

Normal Word Address SpaceSHARC+ Data Address
0x08030000–
0x0803FFFF
0x08020000–
0x0803FFFF
0x08000000–
0x0803FFFF
0x08040000–
0x08041FFF
0x08042000–
0x08043FFF
0x08044000–
0x08045FFF

VISA Address SpaceSHARC+ Instruction Fetch
0x00BE0000–
0x00BFFFFF
0x00BC0000–
0x00BFFFFF
0x00B80000–
0x00BFFFFF
0x00B20000–
0x00B23FFF
0x00B00000–
0x00B03FFF
0x00B40000–
0x00B43FFF

ISA Address SpaceSHARC+ Instruction Fetch
0x005E0000–
0x005EAAAA
0x005D5556–
0x005EAAAA
0x005C0000–
0x005EAAAA
0x00580000–
0x00581555
0x00500000–
0x00501555
0x00540000–
0x00541555

The L2 RAM blocks are subdivided into banks—the 8 Mb L2 models have eight banks, the 4 Mb models have four banks, and there are two banks for the 2 Mb models.

Table 4. SHARC+® L1 Memory SpaceL1 Memory Space Address via Completer1
Port/Completer2 Port

MemoryBlock
Block 0Block 1
Block 2Block 3

Byte Address Space SHARC+
0x28240000–0x2826FFFF
0x282C0000–0x282EFFFF
0x28300000–0x2831FFFF
0x28380000–0x2839FFFF

Normal Word Address Space SHARC+
0x0A090000–0x0A09BFFF
0x0A0B0000–0x0A0BBFFF
0x0A0C0000–0x0A0C7FFF
0x0A0E0000–0x0A0E7FFF

Table 5. Memory Map of Mapped I/Os1

SPI2/OSPI0
Memory(512 MB)1

Byte Address SpaceSHARC+ Data Access
0x60000000–0x600FFFFF
0x60100000–0x602FFFFF
0x60300000–0x6FFFFFFF
0x70000000–0x7FFFFFFF

Normal Word Address SpaceSHARC+ Data Access0x04000000–0x07FFFFFF
Not applicable

VISA Address SpaceSHARC+ Instruction Fetch
0x00F80000–0x00FFFFFF
Not applicableNot applicableNot applicable

ISA Address SpaceSHARC+ Instruction Fetch
0x00780000–0x007FFFFF
Not applicableNot applicable

The SHARC+ VISA/ISA address space for instruction fetch and the normal word address space for data access do not cover the entire byte address space.

Table 6. DMC Memory Map1

DMC0 (1 GB)

1

Byte Address SpaceSHARC+ Data Access
0x80000000–0x805FFFFF
0x80600000–0x809FFFFF
0x80A00000–0x80FFFFFF
0x81000000–0x9FFFFFFF
0xA0000000–0xBFFFFFFF

Normal Word Address SpaceSHARC+ Data Access

0x10000000–0x17FFFFFF

Not applicable

VISA Address SpaceSHARC+ Instruction Fetch
Not applicableNot applicable
0x00800000–0x00AFFFFF
Not applicableNot applicable

ISA Address SpaceSHARC+ Instruction Fetch
0x00400000–0x004FFFFF
Not applicableNot applicableNot applicableNot applicable

The SHARC+ VISA/ISA address space for instruction fetch and the normal word address space for data access do not cover the entire byte address space.

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System Crossbars (SCBs)
The system crossbars (SCBs) are the fundamental building
blocks of a switch fabric style for on-chip system bus interconnection. The SCBs connect system bus requesters to system bus
completers, providing concurrent data transfer between multiple bus requesters and multiple bus completers. A hierarchicalmodel—built from multiple SCBs—provides a power and area
efficient system interconnection.

• The 1D DMA uses a linked list of four-word descriptor setscontaining a link pointer, an address, a length, and aconfiguration• The 2D DMA uses an array of one-word descriptor sets,
specifying only the base DMA address• The 2D DMA uses a linked list of multiword descriptor
sets, specifying all configurable parameters
Memory Direct Memory Access (MDMA)

The SCBs provide the following features:

The processor supports various memory direct memory access(MDMA) operations, including,• Highly efficient, pipelined bus transfer protocol for sustained throughput• Enhanced bandwidth MDMA channels with cyclic redundancy check (CRC) protection (32-bit bus width, run on
SYSCLK)• Full-duplex bus operation for flexibility and reduced
latency• Concurrent bus transfer support to allow multiple bus
requesters to access bus completers simultaneously• Protection model (secure) support for selective bus interconnect protection

Direct Memory Access (DMA)• Enhanced bandwidth MDMA channel (32-bit bus width,runs on SYSCLK)• Maximum bandwidth MDMA channel (64-bit bus width,runs on SYSCLK)
Extended Memory DMA

The processors use direct memory access (DMA) to transfer
data within memory spaces or between a memory space and aperipheral. The processors can specify data transfer operations
and return to normal processing while the fully integrated DMA
controller carries out the data transfers independent of processor activity.
DMA transfers can occur between memory and a peripheral or
between one memory and another memory. Each memory tomemory DMA stream uses two channels: the source channel
and the destination channel.
All DMA channels can transport data to and from all on-chipand off-chip memories. Programs can use two types of DMA
transfers: descriptor-based or register-based. Register-based
DMA allows the processors to program DMA control registers
directly to initiate a DMA transfer. On completion, the DMA
control registers automatically update with original setup values
for continuous transfer. Descriptor-based DMA transfers
require a set of parameters stored within memory to initiate a
DMA sequence. Descriptor-based DMA transfers allow
multiple DMA sequences to be chained together. Program a
DMA channel to set up and start another DMA transfer automatically after the current sequence completes.
The DMA engine supports the following DMA operations:• A single linear buffer that stops on completion

Extended memory DMA supports various operating modes,
such as delay line (which allows processor reads and writes toexternal delay line buffers and to the external memory), withlimited core interaction and scatter/gather DMA (writes to andfrom noncontiguous memory blocks).

Cyclic Redundancy Check (CRC) Protection
The cyclic redundancy check (CRC) protection modules allow
system software to calculate the signature of code, data, or bothin memory, the content of memory-mapped registers, or periodic communication message objects. Dedicated hardware
circuitry compares the signature with precalculated values andtriggers appropriate fault events.
For example, the system software initiates the signature calculation of the entire memory contents every 100 ms and compares
this with expected, precalculated values. If a mismatch occurs, afault condition is generated through the processor core or thetrigger routing unit.
The CRC is a hardware module based on a CRC32 engine thatcomputes the CRC value of the 32-bit data-words presented toit. The source channel of the memory to memory DMA (inmemory scan mode) provides data. The data can be optionallyforwarded to the destination channel (memory transfer mode).
The main features of the CRC peripheral are as follows:• A linear buffer with negative, positive, or zero stride length• Memory scan mode

• A circular autorefreshing buffer that interrupts when eachbuffer becomes full

• Memory transfer mode

• A similar circular buffer that interrupts on fractional buffers, such as at the halfway point• Data fill mode

• The 1D DMA uses a set of identical ping pong buffers
defined by a linked ring of two-word descriptor sets, eachcontaining a link pointer and an address

Rev. D |• Data verify mode
• User-programmable CRC32 polynomial• Bit and byte mirroring option (endianness)• Fault and error interrupt mechanisms

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ADSP-21562/21563/21565/21566/21567/21569• 1D and 2D fill block to initialize an array with constants

Trigger Routing Unit (TRU)• 32-bit CRC signature of a block of memory or an MMR
block

The trigger routing unit (TRU) provides system-level sequencecontrol without core intervention. The TRU maps trigger
generators to trigger receivers. Trigger receivers can be configured to respond to triggers in various ways. Common
applications enabled by the TRU include,

Event Handling
The processors provide event handling that supports both nesting and prioritization. Nesting allows multiple event service
routines to be active simultaneously. Prioritization ensures that
servicing a higher priority event takes precedence over servicing
a lower priority event.

• Automatically triggering the start of a DMA sequence after
a sequence from another DMA channel completes• Software triggering• Synchronization of concurrent activities

The processors provide support for four different types of
events:SECURITY FEATURES• An emulation event causes the processors to enter emulation mode, allowing command and control of theprocessors through the JTAG interface.

The following sections describe the security features of the
ADSP-2156x processors.

• A reset event resets the processors.

Cryptographic Hardware Accelerators• An exception event occurs synchronously to program flow(in other words, the exception is taken before the instruction is allowed to complete). Conditions triggered by the
SHARC+ core, such as data alignment (SIMD or longword) or compute violations (fixed or floating point) andillegal instructions, cause core exceptions. Conditions triggered by the SEC, such as error correcting code (ECC),
parity, watchdog, or system clock, cause system exceptions.

The ADSP-2156x processors support standards-based hardware
accelerated encryption, decryption, authentication, and true
random number generation.

• AES in ECB, CBC, ICM, and CTR modes with 128-bit,
192-bit, and 256-bit keys
• DES in ECB and CBC mode with 56-bit key• An interrupt event occurs asynchronously to program
flow. Interrupts are caused by input signals, timers, andother peripherals, as well as by an explicit software
instruction.

• 3DES in ECB and CBC mode with 3x 56-bit key• ARC4 in stateful, stateless mode, up to 128-bit key
Support for the hardware accelerated hash functions includes
the following:

System Event Controller (SEC)The SHARC+ core event controller receives interrupt requests
from the system event controller (SEC). The SEC features
include the following:• Comprehensive system event source management, including interrupt enable, fault enable, priority, and sourcegrouping• A distributed programming model where each system
event source control and all status fields are independent ofeach other• Determinism where all system events have the same propagation delay and provide unique identification of a specificsystem event source• A completer control port that provides access to all SEC
registers for configuration, status, and interrupt and fault
services

Support for the hardware accelerated cryptographic ciphers
includes the following:• SHA-1• SHA-2 with 224-bit and 256-bit digests• HMAC transforms for SHA-1 and SHA-2• MD5
Public key accelerator (PKA) is available to offload computation
intensive public key cryptography operations.
Both a hardware-based nondeterministic random number generator and pseudorandom number generator are available.
Secure boot is also available with 224-bit and 256-bit elliptic
curve digital signatures ensuring integrity and authenticity ofthe boot stream. Optionally, ensuring confidentiality throughAES-128 encryption is available.

• Global locking that supports a register level protection
model to prevent writes to locked registers• Fault management including fault action configuration,
time out, external indication, and system reset

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ADSP-21562/21563/21565/21566/21567/21569
SAFETY FEATURES

Employ secure debug to allow only trusted users to access thesystem with debug tools.

CAUTION
This product includes security features that can beused to protect embedded nonvolatile memory
contents and prevent execution of unauthorized
code. When security is enabled on this device(either by the ordering party or the subsequent
receiving parties), the ability of Analog Devices to
conduct failure analysis on returned devices islimited. Contact Analog Devices for details on the
failure analysis limitations for this device.

The ADSP-2156x processors are designed to support functionalsafety applications. Whereas the level of safety is mainly dominated by the system concept, the following primitives areprovided by the processors to build a robust safety concept.

Multiparity Bit Protected SHARC+ Core L1 Memories
In the SHARC+ core L1 memory space, whether SRAM or
cache, multiple parity bits protect each word to detect the single
event upsets that occur in all RAMs. Parity also protects thecache tags and BTB.

Error Correcting Code (ECC) Protected L2 Memories
System Protection Unit (SPU)
The system protection unit (SPU) guards against accidental or
unwanted access to an MMR space of the peripheral by providing a write protection mechanism. The user can choose andconfigure the protected peripherals as well as configure which of
the three system MMR requesters (SHARC+ core, memory
DMA, and Arm® CoreSightTM debug) the peripherals are
guarded against.
The SPU is also part of the security infrastructure. Along with
providing write protection functionality, the SPU is employed
to define which resources in the system are secure or nonsecure
as well as block access to secure resources from nonsecure
requesters.

Error correcting code (ECC) corrects single event upsets. A single error correct/double error detect (SEC/DED) code protects
the L2 memory. By default, ECC is enabled, but it can be disabled on a per bank basis. Single-bit errors correcttransparently. If enabled, dual-bit errors can issue a system
event or fault. ECC protection is fully transparent to the user,
even if L2 memory is read or written by 8-bit or 16-bit entities.

Parity Protected Peripheral Memories
Parity protection is added to the following peripheral memories:• ASRC• IIR• FIR• CRYPTO

System Memory Protection Unit (SMPU)
The system memory protection unit (SMPU) provides memory
protection against read and/or write transactions to defined
regions of memory. There are SMPU units in the ADSP-2156x
processors for each memory space, except for SHARC L1
memory.
The SMPU is also part of the security infrastructure. It allows
the user to protect against arbitrary read and/or write transactions and allows regions of memory to be defined as secure andprevent nonsecure requesters from accessing those memory
regions.

SECURITY FEATURES DISCLAIMER
Analog Devices does not guarantee that the Security Featuresdescribed herein provide absolute security. ACCORDINGLY,ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL
EXPRESS AND IMPLIED WARRANTIES THAT THE
SECURITY FEATURES CANNOT BE BREACHED,COMPROMISED, OR OTHERWISE CIRCUMVENTED AND
IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR
ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF
DATA, INFORMATION, PHYSICAL PROPERTY, OR
INTELLECTUAL PROPERTY.

Rev. D |• MLB• TRACE

Cyclic Redundancy Check (CRC) Protected Memories
Whereas parity bit and ECC protection mainly protect against
random soft errors in L1 and L2 memory cells, the CRC engines
can protect against systematic errors (pointer errors) and static
content (instruction code) of L1, L2, and even L3 memories(DDR3, DDR3L). The processors feature two CRC engines thatare embedded in the memory to memory DMA controllers.
CRC checksums can be calculated or compared automaticallyduring memory transfers. Alternatively, single or multiple
memory regions can be continuously scrubbed by a single DMA
work unit as per DMA descriptor chain instructions. The CRC
engine also protects data loaded during the boot process.

Signal Watchdogs
The 10 general-purpose timers feature modes to monitor offchip signals. The watchdog period mode monitors whether
external signals toggle with a period within an expected range.
The watchdog width mode monitors whether the pulse widthsof external signals are within an expected range. Both modes
help detect undesired toggling or lack of toggling of system levelsignals.

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System Event Controller (SEC)
Besides system events, the system event controller (SEC) further
supports fault management, including fault action configuration as timeout, internal indication by system interrupt, or
external indication through the SYS_FAULT pin and system
reset.

Memory Error Controller (MEC)
The memory error controller (MEC) manages memory parity/ECC errors and warnings from the cores and peripherals
and sends out interrupts and triggers.

PROCESSOR PERIPHERALSThe following sections describe the peripherals of the ADSP2156x processors.

frame sync comprise a SPORT half. The data lines can be programmed to either transmit or receive data, and each SPORT
half has a dedicated DMA channel.
An individual SPORT module consists of two independently
configurable SPORT halves with identical functionality. Twobidirectional data lines—primary (0) and secondary (1)—areavailable per SPORT half and are configurable as either transmitters or receivers. Therefore, each SPORT half permits two
unidirectional streams into or out of the same SPORT. Thisbidirectional functionality provides greater flexibility for serial
communications. For full-duplex configuration, one half
SPORT provides two transmit data signals, and the other half
SPORT provides two receive data signals. The frame sync andclock are shared.
Serial ports operate in the following six modes:

Dynamic Memory Controller (DMC)• Standard DSP serial mode

The 16-bit dynamic memory controller (DMC) interfaces to• Multichannel time division multiplexing (TDM) mode
• I2S mode

• DDR3 (JESD79-3), 512 Mb to 8 Gb

• Packed I2S mode

• DDR3L (JESD79-3-1A), 512 Mb to 8 Gb

• Left justified mode

See Table 6 for the DMC memory map.

• Right justified mode

Digital Audio Interface (DAI)The processors support two digital audio interface (DAI) units.
The DAI can connect various peripherals to any of the DAI
pins.
The application code makes these connections using the signal
routing unit (SRU), shown in Figure 1.
The SRU is a matrix routing unit (or group of multiplexers) thatenables the peripherals provided by the DAI to interconnect
under software control. This functionality allows easy use of the
DAI associated peripherals for a wider variety of applications byusing a larger set of algorithms than is possible with nonconfigurable signal paths.
The DAI includes the peripherals described in the following sections (SPORTs, ASRC, S/PDIF, and PCG). DAI Pin Buffer 20
and DAI Pin Buffer 19 can change the polarity of the input signals. Most signals of the peripherals belonging to different DAIs
cannot be interconnected, with few exceptions.
The DAI_PINx pin buffers may also be used as GPIO pins. DAI
input signals allow the triggering of interrupts on the risingedge, falling edge, or both.
See the ADSP-21562/3/5/6/7/9 SHARC+ Processor Hardware
Reference manual for complete information on the use of the
DAIs and SRUs.

Serial Port (SPORT)The processors feature eight synchronous serial ports(SPORTs), providing an inexpensive interface to a wide variety
of digital and mixed-signal peripheral devices. These devices
include Analog Devices AD19xx and ADAU19xx families ofaudio codecs, analog-to-digital converters (ADCs) and digitalto-analog converters (DACs). Two data lines, a clock, and aRev. D |Asynchronous Sample Rate Converter (ASRC)
The asynchronous sample rate converter (ASRC) contains eight
ASRC blocks. The ASRC provides up to 140 dB signal-to-noise
ratio (SNR). The ASRC block performs synchronous or asynchronous sample rate conversion across independent stereo
channels, without using internal processor resources. The ASRC
blocks can also be configured to operate together to convert
multichannel audio data without phase mismatches. Finally, theASRC can clean up audio data from jittery clock sources such as
the S/PDIF receiver.

S/PDIF-Compatible Digital Audio Receiver/Transmitter
The Sony/Philips Digital Interface Format (S/PDIF) is a standard audio data transfer format that allows the transfer of digitalaudio signals from one device to another. There are two S/PDIF
transmit/receive blocks on the processor. The digital audio
interface carries three types of information: audio data, nonaudio data (compressed data), and timing information.
The S/PDIF interface supports one stereo channel or compressed audio streams. The S/PDIF transmitter and receiver are
AES3 compatible and support the sample rate from 24 kHz to
192 kHz. The S/PDIF receiver supports professional jitter
standards.
The S/PDIF receiver/transmitter has no separate DMA channels. The S/PDIF transmitter receives audio data in serial format
and converts it into a biphase encoded signal. The serial data
input to the transmitter can be formatted as left justified, I2S, or
right justified with word widths of 16, 18, 20, or 24 bits. The
S/PDIF receiver converts a biphase encoded signal into I2S serial
format.The serial data, clock, and frame sync outputs/inputs
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ADSP-21562/21563/21565/21566/21567/21569
SRU. They can be connected to various peripherals, such as the
SPORTs, external pins, and the precision clock generators(PCGs), and are controlled by the SRU control registers.

Precision Clock Generators (PCG)
The precision clock generators (PCG) consist of four units: Unit
A and Unit B located in the DAI0 block, and Unit C and Unit D
located in the DAI1 block. The PCG can generate a pair of signals (clock and frame sync) derived from a clock input signal(SCLK0, SYS_CLKIN0, or DAI pin buffer). Each unit can also
output to the pin buffers of the opposite DAI unit. All units are
identical in functionality and operate independently of eachother. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.

Universal Asynchronous Receiver/Transmitter(UART) Ports
The processors provide full-duplex universal asynchronousreceiver/transmitter (UART) ports, fully compatible with PC
standard UARTs. Each UART port provides a simplified UART
interface to other peripherals or hosts, supporting full-duplex,
DMA supported, asynchronous transfers of serial data. A UART
port includes support for five to eight data bits as well as no parity, even parity, or odd parity.

devices, acting as either a master device or a slave device. In a
multimaster environment, the SPI peripheral uses open-drain
outputs to avoid data bus contention. The flow control features
enable slow slave devices to interface with fast master devices by
providing an SPI ready pin (SPI_RDY), which flexibly controls
the transfers.
The baud rate and clock phase and polarities of the SPI port areprogrammable. The port has integrated DMA channels for bothtransmit and receive data streams.

Octal Serial Peripheral Interface (OSPI) PortThe octal serial peripheral interface (OSPI) port provides anincreased external memory data bus width (up to eight bits inparallel). The OSPI port supports DDR modes of operation,
which enable the transfer of up to 16 bits of data each clock
cycle. The OSPI port provides overall data throughput and performance improvement, including faster boot time.
Features of the OSPI port include:• Support for single-, dual-, quad-, or octal-I/O transfers• Multiple modes of operation including direct and software
triggered instruction generator (STIG)• Support for execute in place (XIP): continuous mode

Optionally, an additional address bit can be transferred to interrupt only addressed nodes in multidrop bus (MDB) systems. A
frame is terminated by a configurable number of stop bits.

• Programmable page and block sizes

The UART ports support automatic hardware flow control
through the clear to send (CTS) input and request to send (RTS)
output with programmable assertion first in, first out (FIFO)
levels.

• Support for DDR commands

To help support the Local Interconnect Network (LIN) protocols, a special command causes the transmitter to queue a breakcommand of programmable bit length into the transmit buffer.
Similarly, the number of stop bits can be extended by a programmable interframe space.

• Programmable write protected regions• Programmable memory timing

Link Port (LP)Two 8-bit wide link ports (LP) for the BGA package can connect
to the link ports of other DSPs or peripherals. Link ports arebidirectional and have eight data lines, an acknowledge line, anda clock line.

TimersSerial Peripheral Interface (SPI) Ports

The processors include several timers that are described in thefollowing sections.

The processors have four industry-standard SPI-compatible
ports that allow the processors to communicate with multiple
SPI-compatible devices.

General-Purpose (GP) Timers (TIMER)

The baseline SPI peripheral is a synchronous, 4-wire interface
consisting of two data pins, one device select pin, and a gatedclock pin. The two data pins allow full-duplex operation toother SPI-compatible devices. An extra two (optional) data pins
are provided to support quad-SPI operation. Enhanced modesof operation, such as flow control, fast mode, and dual-I/O
mode (DIOM), are also supported. DMA mode allows for transferring several words with minimal central processing unit
(CPU) interaction.
With a range of configurable options, the SPI ports provide aglueless hardware interface with other SPI-compatible devices
in master mode, slave mode, and multimaster environments.
The SPI peripheral includes programmable baud rates, clockphase, and clock polarity. The peripheral can operate in a
multimaster environment by interfacing with several otherRev. D |There is one general-purpose (GP) timer unit, providing 10
general-purpose programmable timers. Each timer has an external pin that can be configured as PWM or timer output, as an
input to clock the timer, or as a mechanism for measuring pulse
widths and periods of external events. These timers can be synchronized to an external clock input on the TM_TMR[n] pins,
an external TM_CLK input pin, or to the internal SCLK0.
These timer units can be used in conjunction with the UARTs tomeasure the width of the pulses in the data stream to provide a
software autobaud detect function for the respective serial
channels.
The GP timers can generate interrupts to the processor core,providing periodic events for synchronization to either the system clock or to external signals. Timer events can also trigger

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other peripherals via the TRU (for instance, to signal a fault).
Each timer can also be started and stopped by any trigger generator without core intervention.

Figure 5 shows the channel multiplex diagram for the HADC
input pins for the BGA package (ADSP-21566, ADSP-21567,
and ADSP-21569).

Watchdog Timer (WDT)
Two on-chip software watchdog timers (WDT) can be used by
the SHARC+ core. A software watchdog can improve system
availability by forcing the processors to a known state, via a general-purpose interrupt, or a fault, if the timer expires before
being reset by software.

HADC_VIN0
HADC_VIN1ADC SAMPLING CAP
HADC_VIN2
HADC_VIN3

The programmer initializes the count value of the timer, enables
the appropriate interrupt, then enables the timer. Thereafter,
the software must reload the counter before it counts down tozero from the programmed value, protecting the system fromremaining in an unknown state where software that normally
resets the timer stops running due to an external noise condition or software error.

General-Purpose Counters (CNT)HADC_REFN

Figure 5. Channel Multiplex of HADC Input Pins for BGA Package

Figure 6 shows the channel multiplex diagram for the HADC
input pins for the LQFP package (ADSP-21562, ADSP-21563,
and ADSP-21565).

A 32-bit general-purpose counter (CNT) is provided that canoperate in general-purpose up/down count modes and cansense 2-bit quadrature or binary codes as typically emitted byindustrial drives or manual thumbwheels. Count direction iscontrolled by a level-sensitive input pin or by two edge
detectors.

HADC_VIN0
HADC_VIN1ADC SAMPLING CAP

A third counter input can provide flexible zero marker support
and can input the push button signal of thumbwheel devices. All
three CNT0 pins have a programmable debouncing circuit.
Internal signals forwarded to a GP timer enable the timer tomeasure the intervals between count events. Boundary registers
enable auto-zero operation or simple system warning by interrupts when programmed count values are exceeded.

HADC_REFN

Housekeeping Analog-to-Digital Converter (HADC)
Figure 6. Channel Multiplex of HADC Input Pins for LQFP Package

The housekeeping analog-to-digital converter (HADC) provides a general-purpose, multichannel successive
approximation ADC. It supports the following set of features:

Figure 7 shows the input impedance of the HADC, represented
with internal resistance and capacitance. The VIN signal represents the HADC input pins (HADC_VINx).

• 12-bit ADC core with built in sample and hold.
• Four single-ended input channels for the BGA package;
two single-ended input channels for the LQFP package.

MAX RESISTANCE (INCLUDING CHANNEL-MUX)• Throughput rates up to 1 MSPS.

VIN• Single external reference with analog inputs between
0 V and 1.8 V.

PIN + PAD

• Selectable ADC clock frequency including the ability toprogram a prescaler.

2.5pF• Adaptable conversion type; allows single or continuous
conversion with option of autoscan.

ADC SAMPLING CAP
10pF

Figure 7. HADC Internal Circuit Schematic• Autosequencing capability with up to four autoconversions
in a single session. Each conversion can be programmed to
select one to four input channels.
• Four data registers for the BGA package and two data registers for the LQFP package (all individually addressable) tostore conversion values.

Rev. D |1kȍ

Media Local Bus (MediaLB)
The automotive model has a Microchip MediaLB (MLB) device
interface that allows the processors to function as a media local
bus device. It includes support for 3-pin media local bus

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ADSP-21562/21563/21565/21566/21567/21569
protocols. The MLB 3-pin configuration supports speeds up to1024 × FS. The MLB also supports up to 64 logical channels
with up to 468 bytes of data per MLB frame.

latches, regardless of whether the interrupt is masked. Most
control registers feature multiple MMR address entries to writeone-to-set or write-one-to-clear them individually.

The MLB interface supports MOST25, MOST50, and MOST150
data rates and operates in device mode only.

Core Flags I/O Pins

2-Wire Controller Interface (TWI)
The processors include 2-wire interface (TWI) modules thatprovide a simple exchange method of control data between multiple devices. The TWI module is compatible with the widelyused I2C bus standard. The TWI module offers the capabilities
of simultaneous controller and target operation and support for
both 7-bit addressing and multimedia data arbitration. The
TWI interface utilizes two pins for transferring clock(TWI_SCL) and data (TWI_SDA) and supports the protocol at
speeds up to 400 kbps. The TWI interface pins are compatible
with 3.3 V logic levels.
Additionally, the TWI module is fully compatible with serial
camera control bus (SCCB) functionality for easier control ofvarious CMOS camera sensor devices.

General-Purpose I/O (GPIO)
Each general-purpose port pin can be individually controlled bymanipulating the port control, status, and interrupt registers:• The GPIO direction control register specifies the directionof each individual GPIO pin as input or output.
• GPIO control and status registers have a write-one-tomodify mechanism that allows any combination of individual GPIO pins to be modified in a single instruction,
without affecting the level of any other GPIO pins.
• GPIO interrupt mask registers allow each individual GPIO
pin to function as an interrupt to the processors. GPIO pins
defined as inputs can be configured to generate hardwareinterrupts, whereas output pins can be triggered by software interrupts.
• GPIO interrupt sensitivity registers specify whether individual pins are level or edge sensitive and specify, if edge
sensitive, whether the rising edge or both the rising andfalling edges of the signal are significant.

The processor features four flag I/O pins, which allow for external control and monitoring of the SHARC+ core FLAGS
register. User code can write to bits in this register to be driven
to pins configured as outputs, and code execution can be madeconditional based on the settings of the pins configured as
inputs.

SYSTEM ACCELERATION
The following sections describe the system acceleration blocksof the ADSP-2156x processors.

Finite Impulse Response (FIR) Accelerator
The finite impulse response (FIR) accelerator consists of a1024 word coefficient memory, a 1024 word deep delay line forthe data, and four multiplier-accumulator (MAC) units. A controller manages the accelerator. The FIR accelerator runs at thecore clock frequency. The FIR accelerator can access all memory
spaces and can run concurrently with the IIR accelerator on theprocessor.

Infinite Impulse Response (IIR) Accelerator
The infinite impulse response (IIR) accelerator consists of a1440 word coefficient memory for storage of biquad coefficients, a data memory for storing the intermediate data, and one
MAC unit. A controller manages the accelerator. The IIR
accelerator runs at the core clock frequency. The IIR accelerator
can access all memory spaces and run concurrently with theother accelerators on the processor.
In addition to operating at core clock, the FIR/IIR accelerators
support various enhanced features, including the ability to halt
the accelerator for dynamic queuing of unlimited FIR/IIR channels, selective interrupt generation for each channel, and trigger
requester/completer support.

SYSTEM DESIGNThe following sections provide an introduction to system design
features and power supply issues.

Pin Interrupts
Every port pin on the processors can request interrupts in either
an edge sensitive or a level sensitive manner with programmablepolarity. Interrupt functionality is decoupled from GPIO operation. Three system-level interrupt channels (PINT0–PINT2) arereserved for this purpose. Each of these interrupt channels canmanage up to 32 interrupt pins. The assignment from pin tointerrupt is not performed on a pin by pin basis. Rather, groupsof eight pins (half ports) are flexibly assigned to interrupt
channels.

Clock Management

Every pin interrupt channel features a special set of 32-bit memory-mapped registers that enable half port assignment andinterrupt management. This functionality includes masking,identification, and clearing of requests. These registers alsoenable access to the respective pin states and use of the interrupt

Reset is the initial state of the whole processor, or the core, andis the result of a hardware or software triggered event. In thisstate, all control registers are set to default values and functional
units are idle. Exiting a full system reset begins with the core
ready to boot.

Rev. D |The processors provide three operating modes, each with a different performance and power profile. Control of clocking toeach of the processor peripherals reduces power consumption.
The processors do not support any low power operation modes.
Control of clocking to each of the processor peripherals can
reduce the power consumption.

Reset Control Unit (RCU)

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ADSP-21562/21563/21565/21566/21567/21569
The reset control unit (RCU) controls how all the functional
units enter and exit reset. Differences in functional requirements and clocking constraints define how reset signals are
generated. Programs must guarantee that none of the resetfunctions put the system into an undefined state or cause
resources to stall. This requirement is particularly importantwhen the core resets (programs must ensure that there is no
pending system activity involving the core when it is reset).

System Crystal Oscillator

From a system perspective, reset is defined by both the reset target and the reset source.
The reset target is defined as the following:• System reset—all functional units except the RCU are set todefault states.

The processor can be clocked by an external crystal (seeFigure 8), a sine wave input, or a buffered, shaped clock derived
from an external clock oscillator. If using an external clock, it
must be compatible with the VIHCLKIN and VILCLKIN specifications and must not be halted, changed, or operated below thespecified frequency during normal operation (see the Operating
Conditions section). When using an external clock, the clock
signal is connected to the SYS_CLKIN0 pin of the processor andthe SYS_XTAL0 pin must be left unconnected. Alternatively,
because the processor includes an on-chip oscillator circuit, an
external crystal can be used.
SHARC® PROCESSOR• Hardware reset—all functional units are set to default states
without exception. History is lost.

TO PLLCIRCUITRY• Core only reset—affects the core only. When in reset state,
the core is not accessed by any bus requester.
The reset source is defined as the following:• System reset—can be triggered by software (writing to the
RCU_CTL register) or by another functional unit, such as
the dynamic power management (DPM) unit or any of theSEC, TRU, or emulator inputs.

SYS_CLKIN0Nȍ*• Hardware reset—the SYS_HWRST input signal asserts
active (pulled down).

27pF*• Core only reset—can be triggered by software (writing to
the RCU_CTL register).

Nȍ *

27pF*

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. ANALYZE CAREFULLY. VALIDFREQUENCY RANGE IS 20 MHz TO 30 MHz FOR SYS_CLKIN0.

• Trigger request (peripheral).

Clock Generation Unit (CGU)The ADSP-2156x processors support two independent PLLs.
Each PLL is part of a clock generation unit (CGU). Each CGU isdriven externally by the same clock source, thus providing flexibility in determining the internal clocking frequencies for eachclock domain.
Frequencies generated by each CGU are derived from a common multiplier with different divider values available for each
output.
The CGU generates all on-chip clocks and synchronization signals. Multiplication factors are programmed to define the
PLLCLK frequency.
Programmable values divide the PLLCLK frequency to generate
the core clock (CCLK), the system clocks, the DDR3/DDR3L
clock (DCLK), and the output clock (OCLK). For more information on clocking, see the ADSP-21562/3/5/6/7/9 SHARC+
Processor Hardware Reference manual.
Writing to the CGU control registers does not affect the behavior of the PLL immediately. Registers are first programmed witha new value and the PLL logic executes the changes to ensure asmooth transition from the current conditions to the newconditions.

Rev. D |SYS_XTAL0

Figure 8. External Crystal Connection

For fundamental frequency operation, use the circuit shown in
Figure 8. A parallel resonant, fundamental frequency, microprocessor grade crystal is connected across the SYS_CLKIN0
pin and the SYS_XTAL0 pin.
The two capacitors and the series resistor, shown in Figure 8,
fine tune phase and amplitude of the sine frequency. The capacitor and resistor values shown in Figure 8 are typical values
only. The capacitor values are dependent upon the load
capacitance recommendations of the crystal manufacturer andthe physical layout of the printed circuit board (PCB). The resistor value depends on the drive level specified by the crystal
manufacturer. The user must verify the customized values basedon careful investigations on multiple devices over the required
temperature range.

Clock Distribution Unit (CDU)
The two clock generation units each provide outputs that feed aclock distribution unit (CDU). The clock outputs
CLKO0–CLKO1 and the clock generation unit outputs are connected to various targets. For more information, refer to the
ADSP-21562/3/5/6/7/9 SHARC+ Processor Hardware Reference manual.

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Clock Out/External Clock

Power Supplies

The SYS_CLKOUT output pin has programmable options to
output divided down versions of the on-chip clocks. By default,
the SYS_CLKOUT pin drives a buffered version of the
SYS_ CLKIN0 input. Refer to the ADSP-21562/3/5/6/7/9
SHARC+ Processor Hardware Reference manual to change thedefault mapping of clocks.

The processors have separate power supply connections for• Internal (VDD_INT)• External I/O (VDD_EXT)• External I/O Reference (VDD_REF)• HADC/TMU (VDD_ANA)

Booting• DMC (VDD_DMC)

The processors have several mechanisms for automatically loading internal and external memory after a reset. The boot mode isdefined by the SYS_BMODE[n] input pins. There are two categories of boot modes. In flash boot modes, the processors
actively load data from serial memories. In external host bootmodes, the processors receive data over a serial interface froman external host device.
The boot modes are shown in Table 7. These modes are implemented by the SYS_BMODE[n] bits of the reset configuration
register and are sampled during power-on resets and software
initiated resets.

Power Management
As shown in Table 8, the processors support five different power
domains, which maximizes flexibility while maintaining compliance with industry standards and conventions.
The power dissipated by a processor is largely a function of theclock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation.
Table 8. Power Domains

Table 7. Boot Modes
SYS_BMODE[n] Setting1
000
001
010
011
100
1012
110
111
1
2

Boot ModeNo boot
SPI2 flash
External SPI2 hostExternal UART0 hostExternal LP0 host
Octal SPI flash
Reserved
Reserved

1

HADC/TMUVDD_ANAVDD_REF1

VDD_REF requires a minimum of 10 nF and 100 nF decoupling capacitance tomeet source/sink requirements.

Power-Up and Power-Down Sequencing

Thermal Monitoring Unit (TMU)
The thermal monitoring unit (TMU) provides on-chip temperature measurement for applications that require substantial
power consumption. The TMU is integrated into the processor
die and digital infrastructure using an MMR-based systemaccess to measure the die temperature variations in real-time.

• Programmable over temperature and under temperature
limitsVDD_INTVDD_DMCSYS_CLKIN0

In the ADSP-2156x processors, the SHARC+ core controls theboot process, including loading all internal and external memory. The option for secure boot is available on all models.

• On-chip temperature sensing

VDD Range

All Internal Logic
DDR3/DDR3L

All Other I/O (Includes SYS, JTAG, and VDD_EXT
Ports Pins Except SYS_CLKIN0)

SYS_BMODE2 pin is applicable only for the BGA package.
Though octal SPI flash boot is not supported on the LQFP package, it is available
through the ROM API.

TMU features include the following:

Power Domain

At all times (including during power-up/power-down sequencing), the VDD_REF, VDD_ANA, and VDD_EXT supplies muststay within the VDELTA_EXT_REF specification listed in the Operating Conditions table. SYS_XTAL0 oscillations (SYS_CLKIN0)
start when power is applied to the VDD_REF pins. The risingedge of SYS_HWRST initiates the PLL locking sequence. The
rising edge of SYS_HWRST must occur after all voltage supplies
and SYS_CLKIN0 oscillations are valid. For further details andinformation, see the Power-Up Reset Timing section.

Target Board JTAG Emulator Connector
The Analog Devices DSP tools product line of JTAG emulators
uses the IEEE 1149.1 JTAG test access port of the processors tomonitor and control the target board processor during emulation. The Analog Devices DSP tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and processor stacks. The processor JTAG interface ensures the emulator
does not affect target system loading or timing.
For information on JTAG emulator operation, see the appropriate emulator hardware user’s guide at SHARC Processors
Software and Tools.

• Programmable conversion rate
• Averaging feature available

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ADSP-21562/21563/21565/21566/21567/21569
SYSTEM DEBUG
The processors include various features that allow easy system
debug. These are described in the following sections.

System Watchpoint Unit (SWU)
The system watchpoint unit (SWU) is a single module that connects to a single system bus and provides transaction
monitoring. One SWU is attached to the bus going to eachsystem completer. The SWU provides ports for all system bus
address channel signals. Each SWU contains four match groupsof registers with associated hardware. These four SWU matchgroups operate independently but share common event (forexample, interrupt and trigger) outputs.

Debug Access Port (DAP)The debug access port (DAP) provides IEEE 1149.1 JTAG interface support through the JTAG debug. The DAP provides anoptional instrumentation trace for both the core and system. It
provides a trace stream that conforms to MIPI System Trace
Protocol version 2 (STPv2).

DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line ofsoftware and hardware development tools, including an integrated development environment, evaluation products,
emulators, and a variety of software add-ins.

execute, and debug programs. It also supports in-circuit programming of the on-board flash memory device to store userspecific boot code, enabling standalone operation.
Each EZ-KIT purchased includes an evaluation license for
CCES. The CCES evaluation license type restricts CCES features
to specific evaluation systems. With the full CCES license type(sold separately), engineers can develop software for any of the
CCES-supported evaluation boards (including the SOM whenused standalone or when connected to a different carrier board)or any custom system designed around supported Analog
Devices processors. The full CCES license type also enables useof ICE-2000 or ICE-1000 emulators for higher performance
debugging via JTAG.
When a SOM board is mounted to a SOM carrier board,embedded system evaluation can be performed. The EZ-KIT
SOM carrier board provides an evaluation platform for various
system peripherals including audio, S/PDIF, CAN, MLB, USB,
10/100/1000 Ethernet, and A2B, as well as an OSPI flash memory. The EZ-KIT SOM carrier board also features the USB
Debug Agent, which allows for debug and evaluation of the fullsystem (including the processor/memory on the SOM module)
without an emulator.
For further information, see:• www.analog.com/cces• www.analog.com/EV-21569-SOM• www.analog.com/EV-SOMCRR-EZKIT

Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, anddebug support, Analog Devices offers the CrossCore® Embedded Studio (CCES) integrated development environment (IDE).
CCES is based on the Eclipse framework. Supporting most Analog Devices processor families, CCES is the IDE of choice forprocessors, including multicore devices.
CCES seamlessly integrates available software add-ins to support real-time operating systems, file systems, TCP/IP stacks,
USB stacks, algorithmic software modules, and evaluation hardware board support packages (BSPs). For more information,
visit www.analog.com/cces.

EZ-KIT Evaluation System
For processor evaluation, Analog Devices provides an EZ-KIT®
evaluation system (EV-21569-EZKIT), which is a bundle comprised of a System on Module (SOM) board (EV-21569-SOM)
and an EZ-KIT SOM carrier board (EV-SOMCRR-EZKIT).
SOM boards are small and low cost. The EV-21569-SOM board
has the ADSP-21569 processor, SDRAM and QSPI flash memories, JTAG debug connection, FTDI USB-to-UART, and USB
power. SOM boards can be used alone or in combination with a
SOM carrier board. SOM carrier boards have high speed connectors for the SOM, a comprehensive set of peripherals, and an
on-board emulator. Each SOM carrier board also comes with apower supply.
The USB controller on the SOM carrier board connects to the
USB port of the user’s PC, enabling CCES to emulate the onboard processor in circuit. This permits users to download,

Rev. D |Software Add-Ins for CCES
Analog Devices offers software add-ins which seamlessly integrate with CCES to extend the capabilities and reduce
development time. Add-ins include BSPs for evaluation hardware, various middleware packages, and algorithmic modules.
Documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through the CCESIDE upon add-in installation.

Board Support Packages (BSPs) for Evaluation Hardware
Software support for the EZ-KIT evaluation systems is provided
by software add-ins called board support packages (BSPs). The
BSPs contain the required drivers, pertinent release notes, andselect example code for the given evaluation hardware. A download link for a specific BSP is located on the web page for the
associated SOM product.

Middleware Packages
Analog Devices offers middleware add-ins such as real-time
operating systems, file systems, USB stacks, and TCP/IP stacks.
For more information, see the Operating Systems and Middleware page.

Algorithmic Modules
To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These areavailable for use with CCES. For more information, visit the
Design Center.

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Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG test access port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The
emulator accesses the internal features of the processor via the
TAP, allowing the developer to load code, set breakpoints, andview variables, memory, and registers.
The processor must be halted to send data and commands, but
after an operation is completed by the emulator, the DSP system
is set to run at full speed with no impact on system timing. The
emulators require the target board to include a header that supports connection of the JTAG port of the DSP to the emulator.
For details on target board design issues including mechanicallayout, single processor connections, signal buffering, signal termination, and emulator pod logic, see Analog Devices JTAG
Emulation Technical Reference (EE-68).

ADDITIONAL INFORMATIONThis data sheet provides a general overview of the ADSP-2156x
architecture and functionality. For detailed information on thecore architecture and instruction set, refer to the SHARC+ Core
Programming Reference.

RELATED SIGNAL CHAINS
A signal chain is a series of signal conditioning electronic components that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with theoutput of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications togather and process data or to apply system controls based on
analysis of real-time phenomena.
Analog Devices eases signal processing system development by
providing signal processing components that are designed towork together. A tool for viewing relationships between specificapplications and related components is available atwww.analog.com\circuits.
The application signal chains page in the Circuits from the Lab®
site (www.analog.com\circuits) provides the following:• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications• Drill down links for components in each chain to selection
guides and application information• Reference designs applying best practice design techniquesRev. D |Page 20 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
ADSP-2156x DETAILED SIGNAL DESCRIPTIONS
Table 9 provides a detailed description of each pin.
Table 9. ADSP-2156x Detailed Signal Descriptions
Signal Name
C0_FLG[n]CNT_DG

Direction
InOut
Input

CNT_UDInput

CNT_ZM

Input

DAI_PIN[nn]InOut

DMC_A[nn]DMC_BA[n]OutputOutput

DMC_CAS

Output

DMC_CK
DMC_CK
DMC_CKE
DMC_CS[n]DMC_DQ[nn]DMC_LDM

OutputOutputOutputOutput
InOut
Output

DMC_LDQS

InOut

DMC_LDQSDMC_ODT

InOut
Output

DMC_RAS

Output

DMC_RESETDMC_RZQDMC_UDM

Output
InOut
Output

DMC_UDQS

InOut

DMC_UDQSDMC_VREF
DMC_WE

InOut
Input
Output

HADC_EOC_DOUT

OutputDescription
Core 0 FLAGS I/O n. External pins associated with the core FLAGS register on SHARC+ core 0.
Count Down and Gate. Depending on the mode of operation, this input acts either as a count down
signal or a gate signal.
Count down—this input causes the GP counter to decrement.
Gate—stops the GP counter from incrementing or decrementing.
Count Up and Direction. Depending on the mode of operation, this input acts either as a count up
signal or a direction signal.
Count up—this input causes the GP counter to increment.
Direction—selects whether the GP counter is incrementing or decrementing.
Count Zero Marker. Input that connects to the zero marker output of a rotary device or detects thepressing of a pushbutton.
Pin n. The digital applications interface (DAI0) connects various peripherals to any of the DAI0_PINxx
pins. Programs make these connections using the signal routing unit (SRU).
Address n. Address bus.
Bank Address n. Defines which internal bank an activate, read, write, or precharge command isapplied to on the dynamic memory. Bank Address n also defines which mode registers (MR, EMR,
EMR2, and/or EMR3) load during the load mode register command.
Column Address Strobe. Defines the operation for external dynamic memory to perform inconjunction with other DMC command signals. Connect to the CAS input of dynamic memory.
Clock. Outputs DCLK to external dynamic memory.
Clock (Complement). Complement of DMC_CK.
Clock Enable. Active high clock enable. Connects to the CKE input of the dynamic memory.
Chip Select n. Commands are recognized by the memory only when this signal is asserted.
Data n. Bidirectional data bus.
Data Mask for Lower Byte. Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled
on both edges of the data strobe by the dynamic memory.
Data Strobe for Lower Byte. DMC_DQ07:DMC_DQ00 data strobe. Output with write data. Input withread data. Can be single-ended or differential depending on register settings.
Data Strobe for Lower Byte (Complement). Complement of DMC_LDQS.
On Die Termination. Enables dynamic memory termination resistances when driven high (assuming
the memory is properly configured). ODT is enabled or disabled regardless of read or write commands.
Row Address Strobe. Defines the operation for external dynamic memory to perform in conjunction
with other DMC command signals. Connect to the RAS input of dynamic memory.
Reset.
External Calibration Resistor Connection.
Data Mask for Upper Byte. Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled
on both edges of the data strobe by the dynamic memory.
Data Strobe for Upper Byte. DMC_DQ15:DMC_DQ08 data strobe. Output with write data. Input withread data. Can be single-ended or differential depending on register settings.
Data Strobe for Upper Byte (Complement). Complement of DMC_UDQS.
Voltage Reference. Connects to half of the VDD_DMC voltage. Applies to the DMC0_VREF pins.
Write Enable. Defines the operation for external dynamic memory to perform in conjunction withother DMC command signals. Connect to the WE input of dynamic memory.
End of Conversion/Serial Data Out. Transitions high for one cycle of the HADC internal clock at theend of every conversion. Alternatively, HADC serial data out can be seen by setting the appropriate
bit in HADC_CTL.

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Table 9. ADSP-2156x Detailed Signal Descriptions (Continued)
Signal Name
HADC_VIN[n]HADC_VREFN

Direction
Input
Input

HADC_VREFPInput

JTG_TCKJTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
LP_ACK

Input
Input
Output
Input
Input
InOut

LP_CLK

InOut

LP_D[n]MLB_CLK
MLB_DATMLB_SIGOSPI_CLKOSPI_D2
OSPI_D3
OSPI_D4OSPI_D5OSPI_D6OSPI_D7OSPI_MISO

InOut
InOut
InOut
InOut
Output
InOut
InOut
InOut
InOut
InOut
InOut
InOut

OSPI_MOSIInOutOSPI_SEL[n]P_[nn]

OutputInOut

SPI_CLKSPI_D2
SPI_D3
SPI_MISO

Output
InOut
InOut
InOut

SPI_MOSIInOut

SPI_RDY
SPI_SEL[n]SPI_SS

InOut
OutputInput

SPT_ACLKInOut

SPT_AD0

InOut

Description
Analog Input at Channel n. Analog voltage inputs for digital conversion.
Ground Reference for ADC. Connect to an external voltage reference that meets data sheet
specifications.
External Reference for ADC. Connect to an external voltage reference that meets data sheet
specifications.
JTAG Clock. JTAG test access port clock.
JTAG Serial Data In. JTAG test access port data input.
JTAG Serial Data Out. JTAG test access port data output.
JTAG Mode Select. JTAG test access port mode select.
JTAG Reset. JTAG test access port reset.
Acknowledge. Provides handshaking. When the link port is configured as a receiver, LP_ACK is an
output. When the link port is configured as a transmitter, LP_ACK is an input.
Clock. When the link port is configured as a receiver, LP_CLK is an input. When the link port isconfigured as a transmitter, LP_CLK is an output.
Data n. Data bus. Input when receiving, output when transmitting.
Single-Ended Clock.
Single-Ended Data.
Single-Ended Signal.
SPI Master Clock Output. SPI master clock output.
Data 2. Transfers serial data in quad and octal modes.
Data 3. Transfers serial data in quad and octal modes.
Data 4. Transfers serial data in octal mode.
Data 5. Transfers serial data in octal mode.
Data 6. Transfers serial data in octal mode.
Data 7. Transfers serial data in octal mode.
Master In, Slave Out. Transfers serial data. Operates in the same direction as SPI_MOSI in dual andquad modes.
Master Out, Slave In. Transfers serial data. Operates in the same direction as SPI_MISO in dual andquad modes.
Slave Select Output n. Used in master mode to enable the desired slave.
Position n. General-purpose input/output. See the ADSP-21562/3/5/6/7/9 SHARC+ Processor
Hardware Reference manual for programming information.
SPI Master Clock Output. SPI master clock output.
Data 2. Transfers serial data in quad modes.
Data 3. Transfers serial data in quad modes. Open-drain when ODM mode is enabled.
Master In, Slave Out. Transfers serial data. Operates in the same direction as SPI_MOSI in dual andquad modes. Open-drain when ODM mode is enabled.
Master Out, Slave In. Transfers serial data. Operates in the same direction as SPI_MISO in dual andquad modes. Open-drain when ODM mode is enabled.
Ready. Optional flow signal. Output in slave mode, input in master mode.
Slave Select Output n. Used in master mode to enable the desired slave.
Slave Select Input.
Slave mode—acts as the slave select input.
Master mode—optionally serves as an error detection input for the SPI when there are multiple
masters.
Channel A Clock. Data and frame sync are driven or sampled with respect to this clock. This signal
can be either internally or externally generated.
Channel A Data 0. Primary bidirectional data I/O. This signal can be configured as an output totransmit serial data or as an input to receive serial data.

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ADSP-21562/21563/21565/21566/21567/21569
Table 9. ADSP-2156x Detailed Signal Descriptions (Continued)
Signal NameSPT_AD1

Direction
InOut

SPT_AFSInOut

SPT_ATDV

Output

SPT_BCLKInOut

SPT_BD0

InOut

SPT_BD1

InOut

SPT_BFSInOut

SPT_BTDV

Output

SYS_BMODE[n]SYS_CLKIN0SYS_CLKOUT

Input
Input
Output

SYS_FAULTInOut

SYS_FAULTInOut

SYS_HWRST
SYS_RESOUTSYS_XTAL0
TM_ACI[n]TM_ACLK[n]TM_CLK
TM_TMR[n]TRACE_CLKTRACE_D[nn]TWI_SCL
TWI_SDAUART_CTSUART_RTS
UART_RX

Input
OutputOutput
Input
Input
Input
InOut
OutputOutput
InOut
InOut
Input
OutputInput

UART_TX

OutputDescription
Channel A Data 1. Secondary bidirectional data I/O. This signal can be configured as an output totransmit serial data or as an input to receive serial data.
Channel A Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
Channel A Transmit Data Valid. This signal is optional and only active when SPORT is configured in
multichannel transmit mode. It is asserted during enabled slots.
Channel B Clock. Data and frame sync are driven or sampled with respect to this clock. This signal
can be either internally or externally generated.
Channel B Data 0. Primary bidirectional data I/O. This signal can be configured as an output totransmit serial data or as an input to receive serial data.
Channel B Data 1. Secondary bidirectional data I/O. This signal can be configured as an output totransmit serial data or as an input to receive serial data.
Channel B Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
Channel B Transmit Data Valid. This signal is optional and only active when SPORT is configured in
multichannel transmit mode. It is asserted during enabled slots.
Boot Mode Control n. Selects the boot mode of the processor.
Clock/Crystal Input.
Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the ADSP21562/3/5/6/7/9 SHARC+ Processor Hardware Reference manual for more details.
Active, High, Fault Output. Indicates internal faults or senses external faults depending on theoperating mode.
Active, Low, Fault Output. Indicates internal faults or senses external faults depending on theoperating mode.
Processor Hardware Reset Control. Resets the device when asserted.
Reset Output. Indicates the device is in the reset state.
Crystal Output.
Alternate Capture Input n. Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.
Alternate Clock n. Provides an additional time base for an individual timer.
Clock. Provides an additional global time base for all GP timers.
Timer n. The main input/output signal for each timer.
Trace Clock. Clock output.
Trace Data n. Unidirectional data bus.
Serial Clock. Clock output when controller, clock input when target.
Serial Data. Receives or transmits data.
Clear to Send. Flow control signal.
Request to Send. Flow control signal.
Receive. Receives input. Typically connects to a transceiver that meets the electrical requirements ofthe device with which it is communicating.
Transmit. Transmits output. Typically connects to a transceiver that meets the electrical requirementsof the device with which it is communicating.

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400-BALL CSP_BGA SIGNAL DESCRIPTIONS
The processor pin definitions are shown in Table 10 for the
400-ball CSP_BGA package. The columns in this table provide
the following information:• The signal name column includes the signal name for every
pin and the GPIO multiplexed pin function, whereapplicable.
• The description column provides a descriptive name foreach signal.
• The port column shows whether a signal is multiplexedwith other signals on a general-purpose I/O port pin.

• The pin name column identifies the name of the packagepin (at power-on reset) on which the signal is located (if asingle function pin) or is multiplexed (if a general-purpose
I/O pin).
• The DAI pins and their associated signal routing units(SRUs) connect inputs and outputs of the DAI peripherals(SPORT, ASRC, S/PDIF, and PCG). See the ADSP21562/3/5/6/7/9 SHARC+ Processor Hardware Reference
manual for complete information on the use of the DAI
and SRUs.

Table 10. ADSP-2156x 400-Ball CSP_BGA Signal Descriptions
Signal Name
C0_FLG0
C0_FLG1
C0_FLG2
C0_FLG3
CNT0_DG
CNT0_UD
CNT0_ZM
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN19
DAI1_PIN20

Description
SHARC+ Core 0 FLAGS I/O 0
SHARC+ Core 0 FLAGS I/O 1
SHARC+ Core 0 FLAGS I/O 2
SHARC+ Core 0 FLAGS I/O 3
CNT0 Count Down and Gate
CNT0 Count Up and Direction
CNT0 Count Zero Marker
DAI0 Pin 1
DAI0 Pin 2
DAI0 Pin 3
DAI0 Pin 4
DAI0 Pin 5
DAI0 Pin 6
DAI0 Pin 7
DAI0 Pin 8
DAI0 Pin 9
DAI0 Pin 10
DAI0 Pin 11
DAI0 Pin 12
DAI0 Pin 19
DAI0 Pin 20
DAI1 Pin 1
DAI1 Pin 2
DAI1 Pin 3
DAI1 Pin 4
DAI1 Pin 5
DAI1 Pin 6
DAI1 Pin 7
DAI1 Pin 8
DAI1 Pin 9
DAI1 Pin 10
DAI1 Pin 11
DAI1 Pin 12
DAI1 Pin 19
DAI1 Pin 20

Rev. D |

Port
A
A
B
B
B
B
B
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed

Page 24 of 102 |June 2023

Pin Name
PA_12
PA_13
PB_03
PB_02
PB_05
PB_03
PB_04
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN19
DAI1_PIN20ADSP-21562/21563/21565/21566/21567/21569
Table 10. ADSP-2156x 400-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CK
DMC0_CKE
DMC0_CS0DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODTDMC0_RAS
DMC0_RESET
DMC0_RZQDMC0_UDM

Description
DMC0 Address 0
DMC0 Address 1
DMC0 Address 2
DMC0 Address 3
DMC0 Address 4
DMC0 Address 5
DMC0 Address 6
DMC0 Address 7
DMC0 Address 8
DMC0 Address 9
DMC0 Address 10
DMC0 Address 11
DMC0 Address 12
DMC0 Address 13
DMC0 Address 14
DMC0 Address 15
DMC0 Bank Address Input 0
DMC0 Bank Address Input 1
DMC0 Bank Address Input 2
DMC0 Column Address Strobe
DMC0 Clock
DMC0 Clock (Complement)
DMC0 Clock Enable
DMC0 Chip Select 0
DMC0 Data 0
DMC0 Data 1
DMC0 Data 2
DMC0 Data 3
DMC0 Data 4
DMC0 Data 5
DMC0 Data 6
DMC0 Data 7
DMC0 Data 8
DMC0 Data 9
DMC0 Data 10
DMC0 Data 11
DMC0 Data 12
DMC0 Data 13
DMC0 Data 14
DMC0 Data 15
DMC0 Data Mask for Lower Byte
DMC0 Data Strobe for Lower Byte
DMC0 Data Strobe for Lower Byte (Complement)
DMC0 On-die Termination
DMC0 Row Address Strobe
DMC0 Reset (DDR3 Only)
DMC0 External Calibration Resistor Connection
DMC0 Data Mask for Upper Byte

Rev. D |Page 25 of 102 |June 2023

Port
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed

Pin Name
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CK
DMC0_CKE
DMC0_CS0DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODTDMC0_RAS
DMC0_RESET
DMC0_RZQDMC0_UDMADSP-21562/21563/21565/21566/21567/21569
Table 10. ADSP-2156x 400-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
DMC0_UDQS
DMC0_UDQS
DMC0_VREF
DMC0_WE
HADC0_EOC_DOUT
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VREFN
HADC0_VREFPJTG_TCKJTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
LP0_ACK
LP0_CLK
LP0_D0LP0_D1
LP0_D2
LP0_D3
LP0_D4
LP0_D5
LP0_D6
LP0_D7
LP1_ACK
LP1_CLK
LP1_D0LP1_D1LP1_D2
LP1_D3
LP1_D4
LP1_D5
LP1_D6
LP1_D7
MLB0_CLK
MLB0_DAT
MLB0_SIGOSPI0_CLKOSPI0_D2
OSPI0_D3
OSPI0_D4
OSPI0_D5
OSPI0_D6
OSPI0_D7
OSPI0_MISO/D1
OSPI0_MOSI/D0

Description
DMC0 Data Strobe for Upper Byte
DMC0 Data Strobe for Upper Byte (Complement)
DMC0 Voltage Reference
DMC0 Write Enable
HADC0 End of Conversion / Serial Data Out
HADC0 Analog Input at channel 0
HADC0 Analog Input at channel 1
HADC0 Analog Input at channel 2
HADC0 Analog Input at channel 3
HADC0 Ground Reference for ADC
HADC0 External Reference for ADC
JTAG Clock
JTAG Serial Data In
JTAG Serial Data Out
JTAG Mode Select
JTAG Reset
LP0 Acknowledge
LP0 ClockLP0 Data 0
LP0 Data 1
LP0 Data 2
LP0 Data 3
LP0 Data 4LP0 Data 5
LP0 Data 6
LP0 Data 7
LP1 Acknowledge
LP1 ClockLP1 Data 0
LP1 Data 1
LP1 Data 2
LP1 Data 3
LP1 Data 4
LP1 Data 5
LP1 Data 6
LP1 Data 7
MLB0 Single-Ended Clock
MLB0 Single-Ended Data
MLB0 Single-Ended Signal
OSPI0 Clock
OSPI0 Data 2
OSPI0 Data 3
OSPI0 Data 4
OSPI0 Data 5
OSPI0 Data 6
OSPI0 Data 7
OSPI0 Master In, Slave Out
OSPI0 Master Out, Slave In

Rev. D | Page 26 of 102 | June 2023

Port
Not Muxed
Not Muxed
Not Muxed
Not MuxedA
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
B
B
B
B
B
B
B
B
B
B
B
C
B
C
C
C
C
C
C
C
B
B
B
A
A
A
A
A
A
A
A
A

Pin Name
DMC0_UDQS
DMC0_UDQS
DMC0_VREF0, DMC0_VREF1
DMC0_WE
PA_11
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VREFN
HADC0_VREFPJTG_TCKJTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PB_04
PB_06
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_02
PC_07
PB_15
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PB_02
PB_00
PB_01
PA_04
PA_02
PA_03
PA_06
PA_07
PA_08
PA_09
PA_00
PA_01

ADSP-21562/21563/21565/21566/21567/21569
Table 10. ADSP-2156x 400-Ball CSP_BGA Signal Descriptions (Continued)
Signal NameOSPI0_SEL1
OSPI0_SEL2
OSPI0_SEL3
SPI0_CLK
SPI0_MISO
SPI0_MOSISPI0_RDY
SPI0_SEL1
SPI0_SEL2
SPI0_SEL3
SPI0_SEL4
SPI0_SS
SPI1_CLK
SPI1_D2
SPI1_D3
SPI1_MISO
SPI1_MOSISPI1_RDY
SPI1_SEL1
SPI1_SEL2
SPI1_SEL3
SPI1_SEL4
SPI1_SEL5
SPI1_SEL6
SPI1_SEL7
SPI1_SS
SPI2_CLK
SPI2_D2
SPI2_D3
SPI2_MISOSPI2_MOSISPI2_RDY
SPI2_SEL1
SPI2_SEL2
SPI2_SEL3
SPI2_SEL4
SPI2_SEL5
SPI2_SEL6
SPI2_SEL7
SPI2_SSSYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0SYS_CLKOUT
SYS_FAULTSYS_FAULTSYS_HWRST

Description
OSPI0 Slave Select Output 1
OSPI0 Slave Select Output 2
OSPI0 Slave Select Output 3
SPI0 Clock
SPI0 Master In, Slave Out
SPI0 Master Out, Slave In
SPI0 Ready
SPI0 Slave Select Output 1
SPI0 Slave Select Output 2
SPI0 Slave Select Output 3
SPI0 Slave Select Output 4
SPI0 Slave Select Input
SPI1 Clock
SPI1 Data 2
SPI1 Data 3
SPI1 Master In, Slave Out
SPI1 Master Out, Slave In
SPI1 Ready
SPI1 Slave Select Output 1
SPI1 Slave Select Output 2
SPI1 Slave Select Output 3
SPI1 Slave Select Output 4
SPI1 Slave Select Output 5
SPI1 Slave Select Output 6
SPI1 Slave Select Output 7
SPI1 Slave Select Input
SPI2 Clock
SPI2 Data 2
SPI2 Data 3
SPI2 Master In, Slave Out
SPI2 Master Out, Slave In
SPI2 Ready
SPI2 Slave Select Output 1
SPI2 Slave Select Output 2
SPI2 Slave Select Output 3
SPI2 Slave Select Output 4
SPI2 Slave Select Output 5
SPI2 Slave Select Output 6
SPI2 Slave Select Output 7
SPI2 Slave Select Input
Boot Mode Control Pin 0
Boot Mode Control Pin 1
Boot Mode Control Pin 2
Clock/Crystal Input
Processor Clock Output
Active, High, Fault Output
Active, Low, Fault Output
Processor Hardware Reset Control

Rev. D |Page 27 of 102 |

Port
A
C
C
A
A
A
B
A
B
B
B
A
A
A
A
A
A
C
A
B
B
C
B
C
B
A
A
A
A
A
A
B
A
B
B
C
B
C
B
A
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not MuxedC
Not Muxed
Not Muxed

June 2023

Pin Name
PA_05
PC_04
PC_05
PA_06
PA_07
PA_08
PB_11
PA_09
PB_05
PB_14
PB_15
PA_09
PA_10
PA_14
PA_15
PA_11
PA_12
PC_06
PA_13
PB_10
PB_13
PC_00
PB_06
PC_02
PB_08
PA_13
PA_04
PA_02
PA_03
PA_00
PA_01
PB_05
PA_05
PB_03
PB_12
PC_01
PB_07
PC_03
PB_09
PA_05
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0SYS_CLKOUT
PC_07
SYS_FAULTSYS_HWRSTADSP-21562/21563/21565/21566/21567/21569
Table 10. ADSP-2156x 400-Ball CSP_BGA Signal Descriptions (Continued)
Signal NameSYS_RESOUTSYS_XTAL0
TM0_ACI0
TM0_ACI1
TM0_ACI2
TM0_ACI3
TM0_ACI4
TM0_ACLK1
TM0_ACLK2
TM0_ACLK3
TM0_ACLK4
TM0_CLK
TM0_TMR0
TM0_TMR1
TM0_TMR2
TM0_TMR3
TM0_TMR4
TM0_TMR5
TM0_TMR6
TM0_TMR7
TM0_TMR8
TM0_TMR9TRACE0_CLK
TRACE0_D00
TRACE0_D01
TRACE0_D02
TRACE0_D03
TRACE0_D04
TRACE0_D05
TRACE0_D06
TRACE0_D07
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
TWI2_SCL
TWI2_SDA
TWI3_SCL
TWI3_SDA
TWI4_SCL
TWI4_SDA
TWI5_SCL
TWI5_SDAUART0_CTS
UART0_RTS
UART0_RX
UART0_TX
UART1_CTS

Description
Reset Output
Crystal Output
TIMER0 Alternate Capture Input 0
TIMER0 Alternate Capture Input 1
TIMER0 Alternate Capture Input 2
TIMER0 Alternate Capture Input 3
TIMER0 Alternate Capture Input 4
TIMER0 Alternate Clock 1
TIMER0 Alternate Clock 2
TIMER0 Alternate Clock 3
TIMER0 Alternate Clock 4
TIMER0 Clock
TIMER0 Timer 0
TIMER0 Timer 1
TIMER0 Timer 2
TIMER0 Timer 3
TIMER0 Timer 4
TIMER0 Timer 5
TIMER0 Timer 6
TIMER0 Timer 7
TIMER0 Timer 8
TIMER0 Timer 9
TRACE0 Trace Clock
TRACE0 Trace Data 0
TRACE0 Trace Data1
TRACE0 Trace Data2
TRACE0 Trace Data 3
TRACE0 Trace Data4
TRACE0 Trace Data5
TRACE0 Trace Data6
TRACE0 Trace Data 7
TWI0 Serial Clock
TWI0 Serial Data
TWI1 Serial Clock
TWI1 Serial Data
TWI2 Serial Clock
TWI2 Serial Data
TWI3 Serial Clock
TWI3 Serial Data
TWI4 Serial Clock
TWI4 Serial Data
TWI5 Serial Clock
TWI5 Serial Data
UART0 Clear to Send
UART0 Request to Send
UART0 Receive
UART0 Transmit
UART1 Clear to Send

Rev. D |Page 28 of 102 |Port
Not Muxed
Not Muxed
A
A
B
B
A
A
A
A
B
B
A
A
A
B
B
B
B
B
C
C
B
B
B
B
B
C
C
C
C
A
A
B
B
A
A
A
A
C
C
C
C
A
A
A
A
B

June 2023

Pin Name
SYS_RESOUTSYS_XTAL0
PA_07
PA_14
PB_11
PB_00
PA_11
PA_06
PA_08
PA_02
PB_02
PB_01
PA_10
PA_12
PA_13
PB_03
PB_04
PB_05
PB_08
PB_09
PC_05
PC_07
PB_06
PB_07
PB_08
PB_09
PB_10
PC_00
PC_01
PC_02
PC_03
PA_10
PA_11
PB_00
PB_01
PA_14
PA_15
PA_02
PA_03
PC_00
PC_01
PC_02
PC_03
PA_09
PA_08
PA_07
PA_06
PB_01

ADSP-21562/21563/21565/21566/21567/21569
Table 10. ADSP-2156x 400-Ball CSP_BGA Signal Descriptions (Continued)
Signal NameUART1_RTS
UART1_RX
UART1_TX
UART2_CTS
UART2_RTS
UART2_RX
UART2_TX

Description
UART1 Request to Send
UART1 Receive
UART1 Transmit
UART2 Clear to Send
UART2 Request to Send
UART2 Receive
UART2 Transmit

Rev. D | Page 29 of 102 |

Port
B
A
A
B
B
B
B

June 2023

Pin Name
PB_00
PA_14
PA_15
PB_14
PB_13
PB_11
PB_12

ADSP-21562/21563/21565/21566/21567/21569
GPIO MULTIPLEXING FOR 400-BALL CSP_BGA PACKAGE
Table 11 through Table 13 identify the pin functions that are
multiplexed on the general-purpose I/O pins of the 400-ball
CSP_BGA package.
Table 11. Signal Multiplexing for Port A
Signal Name
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15

Multiplexed
Function 0
SPI2_MISOSPI2_MOSISPI2_D2
SPI2_D3
SPI2_CLK
SPI2_SEL1
SPI0_CLK
SPI0_MISO
SPI0_MOSISPI0_SEL1
TWI0_SCL
TWI0_SDA
C0_FLG0
C0_FLG1
TWI2_SCL
TWI2_SDA

Multiplexed
Function 1
OSPI0_MISO/D1
OSPI0_MOSI/D0
OSPI0_D2
OSPI0_D3
OSPI0_CLKOSPI0_SEL1
UART0_TX
UART0_RX
UART0_RTS
UART0_CTS
SPI1_CLK
SPI1_MISO
SPI1_MOSISPI1_SEL1
SPI1_D2
SPI1_D3

Multiplexed
Function 2

Multiplexed
Function 3

TWI3_SCL
TWI3_SDA

Multiplexed
Function Input Tap

TM0_ACLK3

SPI2_SS
TM0_ACLK1
TM0_ACI0
TM0_ACLK2
SPI0_SSOSPI0_D4
OSPI0_D5
OSPI0_D6
OSPI0_D7
TM0_TMR0
HADC0_EOC_DOUT
TM0_TMR1
TM0_TMR2
UART1_RX
UART1_TX

TM0_ACI4
SPI1_SS
TM0_ACI1

Table 12. Signal Multiplexing for Port B
Signal Name
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
PB_06
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15

Multiplexed
Function 0MLB0_DAT
MLB0_SIG
MLB0_CLK
TM0_TMR3
TM0_TMR4
TM0_TMR5
LP0_CLK
LP0_D0LP0_D1
LP0_D2
LP0_D3
LP0_D4
LP0_D5
LP0_D6
LP0_D7
LP1_D0Multiplexed
Function 1
TWI1_SCL
TWI1_SDA
C0_FLG3
C0_FLG2
SPI1_RDY
SPI2_RDY
SPI1_SEL5
SPI2_SEL5
SPI1_SEL7
SPI2_SEL7
SPI1_SEL2
SPI0_RDY
SPI2_SEL3
SPI1_SEL3
SPI0_SEL3
SPI0_SEL4

Rev. D |Multiplexed
Function 2
UART1_RTS
UART1_CTS
LP1_ACKSPI2_SEL2
LP0_ACKSPI0_SEL2

TM0_TMR6
TM0_TMR7

Page 30 of 102 |June 2023

Multiplexed
Function 3

TRACE0_CLK
TRACE0_D00
TRACE0_D01
TRACE0_D02
TRACE0_D03
UART2_RX
UART2_TX
UART2_RTS
UART2_CTS

Multiplexed
Function Input Tap
TM0_ACI3
TM0_CLK
TM0_ACLK4
CNT0_UD
CNT0_ZM
CNT0_DG

TM0_ACI2ADSP-21562/21563/21565/21566/21567/21569
Table 13. Signal Multiplexing for Port C
Signal Name
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
1

Multiplexed
Function 0
LP1_D1LP1_D2
LP1_D3
LP1_D4
LP1_D5
LP1_D6
LP1_D7
LP1_CLK

Multiplexed
Function 1
TWI4_SCL
TWI4_SDA
TWI5_SCL
TWI5_SDAOSPI0_SEL2
OSPI0_SEL3
SPI1_RDY

Multiplexed
Function 2
TRACE0_D04
TRACE0_D05
TRACE0_D06
TRACE0_D07

Multiplexed
Function 3
SPI1_SEL4
SPI2_SEL4
SPI1_SEL6
SPI2_SEL6

TM0_TMR8
TM0_TMR9SYS_FAULT1

The default PC_07 pin function is SYS_FAULT until the PORTC_FER and PORTC_MUX registers are explicitly programmed to change it.

Table 14 shows the internal timer signal routing. This tableapplies to both the 400-ball CSP_BGA and 120-lead LQFP
packages.
Table 14. Internal Timer Signal Routing
Timer Input Signal
TM0_ACLK0
TM0_ACI5
TM0_ACLK5
TM0_ACI6
TM0_ACLK6
TM0_ACI7
TM0_ACLK7
TM0_ACI8
TM0_ACLK8
TM0_ACI9
TM0_ACLK9Internal Source
SYS_CLKIN0
DAI0_PB04_O
DAI0_PB03_O
DAI1_PB04_O
DAI1_PB03_O
CNT0_TO signal
SYS_CLKIN0
DAI0_PB06_O
DAI0_PB05_O
DAI1_PB06_O
DAI1_PB05_O

Rev. D |Page 31 of 102 |June 2023

Multiplexed
Function Input Tap

ADSP-21562/21563/21565/21566/21567/21569
120-LEAD LQFP SIGNAL DESCRIPTIONS
The processor pin definitions are shown Table 15 for the
120-lead LQFP package. The columns in this table provide thefollowing information:• The signal name column includes the signal name for every
pin and the GPIO multiplexed pin function, whereapplicable.
• The description column provides a descriptive name foreach signal.
• The port column shows whether or not a signal is multiplexed with other signals on a general-purpose I/O port
pin.

• The pin name column identifies the name of the packagepin (at power on reset) on which the signal is located (if asingle function pin) or is multiplexed (if a general-purpose
I/O pin).
• The DAI pins and their associated signal routing units(SRUs) connect inputs and outputs of the DAI peripherals(SPORT, ASRC, S/PDIF, and PCG). See the Digital Audio
Interface (DAI) chapter of the ADSP-21562/3/5/6/7/9
SHARC+ Processor Hardware Reference manual for complete information on the use of the DAIs and SRUs.

Table 15. ADSP-2156x 120-Lead LQFP Signal Descriptions
Signal Name
C0_FLG0
C0_FLG1
C0_FLG2
C0_FLG3
CNT0_DG
CNT0_UD
CNT0_ZM
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN19
DAI1_PIN20
HADC0_EOC_DOUT
HADC0_VIN0
HADC0_VIN1
HADC0_VREFN

Description
SHARC+ Core 0 FLAGS I/O 0
SHARC+ Core 0 FLAGS I/O 1
SHARC+ Core 0 FLAGS I/O 2
SHARC+ Core 0 FLAGS I/O 3
CNT0 Count Down and Gate
CNT0 Count Up and Direction
CNT0 Count Zero Marker
DAI0 Pin 1
DAI0 Pin 2
DAI0 Pin 3
DAI0 Pin 4
DAI0 Pin 5
DAI0 Pin 6
DAI0 Pin 7
DAI0 Pin 8
DAI0 Pin 9
DAI0 Pin 10
DAI0 Pin 19
DAI0 Pin 20
DAI1 Pin 1
DAI1 Pin 2
DAI1 Pin 3
DAI1 Pin 4
DAI1 Pin 5
DAI1 Pin 6
DAI1 Pin 7
DAI1 Pin 8
DAI1 Pin 9
DAI1 Pin 10
DAI1 Pin 19
DAI1 Pin 20
HADC0 End of Conversion / Serial Data Out
HADC0 Analog Input at channel 0
HADC0 Analog Input at channel 1
HADC0 Ground Reference for ADC
Rev. D |Page 32 of 102 |

Port
A
A
B
B
B
B
B
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not MuxedA
Not Muxed
Not Muxed
Not Muxed
June 2023

Pin Name
PA_12
PA_13
PB_03
PB_02
PB_05
PB_03
PB_04
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN19
DAI1_PIN20
PA_11
HADC0_VIN0
HADC0_VIN1
HADC0_VREFNADSP-21562/21563/21565/21566/21567/21569
Table 15. ADSP-2156x 120-Lead LQFP Signal Descriptions (Continued)
Signal Name
HADC0_VREFPJTG_TCKJTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
MLB0_CLK
MLB0_DAT
MLB0_SIGOSPI0_CLKOSPI0_D2
OSPI0_D3
OSPI0_D4
OSPI0_D5
OSPI0_D6
OSPI0_D7
OSPI0_MISO/D1
OSPI0_MOSI/D0
OSPI0_SEL1
SPI0_CLK
SPI0_MISO
SPI0_MOSISPI0_SEL1
SPI0_SEL2
SPI0_SS
SPI1_CLK
SPI1_D2
SPI1_D3
SPI1_MISO
SPI1_MOSISPI1_RDY
SPI1_SEL1
SPI1_SS
SPI2_CLK
SPI2_D2
SPI2_D3
SPI2_MISOSPI2_MOSISPI2_RDY
SPI2_SEL1
SPI2_SEL2
SPI2_SSSYS_BMODE0
SYS_BMODE1
SYS_CLKIN0SYS_CLKOUT
SYS_FAULTSYS_HWRST

Description
HADC0 External Reference for ADC
JTAG Clock
JTAG Serial Data In
JTAG Serial Data Out
JTAG Mode Select
JTAG Reset
MLB0 Single-Ended Clock
MLB0 Single-Ended Data
MLB0 Single-Ended Signal
OSPI0 Clock
OSPI0 Data 2
OSPI0 Data 3
OSPI0 Data 4
OSPI0 Data 5
OSPI0 Data 6
OSPI0 Data 7
OSPI0 Master In, Slave Out
OSPI0 Master Out, Slave In
OSPI0 Slave Select Output 1
SPI0 Clock
SPI0 Master In, Slave Out
SPI0 Master Out, Slave In
SPI0 Slave Select Output 1
SPI0 Slave Select Output 2
SPI0 Slave Select Input
SPI1 Clock
SPI1 Data 2
SPI1 Data 3
SPI1 Master In, Slave Out
SPI1 Master Out, Slave In
SPI1 Ready
SPI1 Slave Select Output 1
SPI1 Slave Select Input
SPI2 Clock
SPI2 Data 2
SPI2 Data 3
SPI2 Master In, Slave Out
SPI2 Master Out, Slave In
SPI2 Ready
SPI2 Slave Select Output 1
SPI2 Slave Select Output 2
SPI2 Slave Select Input
Boot Mode Control
Boot Mode Control
Clock/Crystal Input
Processor Clock Output
Active-Low Fault Output
Processor Hardware Reset Control

Rev. D |Page 33 of 102 |Port
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
A
A
A
A
B
A
A
A
A
A
A
A
B
A
B
A
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed

June 2023

Pin Name
HADC0_VREFPJTG_TCKJTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PB_02
PB_00
PB_01
PA_04
PA_02
PA_03
PA_06
PA_07
PA_08
PA_09
PA_00
PA_01
PA_05
PA_06
PA_07
PA_08
PA_09
PB_05
PA_09
PA_10
PA_14
PA_15
PA_11
PA_12
PB_04
PA_13
PA_13
PA_04
PA_02
PA_03
PA_00
PA_01
PB_05
PA_05
PB_03
PA_05
SYS_BMODE0
SYS_BMODE1
SYS_CLKIN0SYS_CLKOUT
SYS_FAULTSYS_HWRSTADSP-21562/21563/21565/21566/21567/21569
Table 15. ADSP-2156x 120-Lead LQFP Signal Descriptions (Continued)
Signal NameSYS_RESOUTSYS_XTAL0
TM0_ACI0
TM0_ACI1
TM0_ACI3
TM0_ACI4
TM0_ACLK1
TM0_ACLK2
TM0_ACLK3
TM0_ACLK4
TM0_CLK
TM0_TMR0
TM0_TMR1
TM0_TMR2
TM0_TMR3
TM0_TMR4
TM0_TMR5
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
TWI2_SCL
TWI2_SDA
TWI3_SCL
TWI3_SDAUART0_CTS
UART0_RTS
UART0_RX
UART0_TX
UART1_CTS
UART1_RTS
UART1_RX
UART1_TX

Description
Reset Output
Crystal Output
TIMER0 Alternate Capture Input 0
TIMER0 Alternate Capture Input 1
TIMER0 Alternate Capture Input 3
TIMER0 Alternate Capture Input 4
TIMER0 Alternate Clock 1
TIMER0 Alternate Clock 2
TIMER0 Alternate Clock 3
TIMER0 Alternate Clock 4
TIMER0 Clock
TIMER0 Timer 0
TIMER0 Timer 1
TIMER0 Timer 2
TIMER0 Timer 3
TIMER0 Timer 4
TIMER0 Timer 5
TWI0 Serial Clock
TWI0 Serial Data
TWI1 Serial Clock
TWI1 Serial Data
TWI2 Serial Clock
TWI2 Serial Data
TWI3 Serial Clock
TWI3 Serial Data
UART0 Clear to Send
UART0 Request to Send
UART0 Receive
UART0 Transmit
UART1 Clear to Send
UART1 Request to Send
UART1 Receive
UART1 Transmit

Rev. D |Page 34 of 102 |Port
Not Muxed
Not Muxed
A
A
B
A
A
A
A
B
B
A
A
A
B
B
B
A
A
B
B
A
A
A
A
A
A
A
A
B
B
A
A

June 2023

Pin Name
SYS_RESOUTSYS_XTAL0
PA_07
PA_14
PB_00
PA_11
PA_06
PA_08
PA_02
PB_02
PB_01
PA_10
PA_12
PA_13
PB_03
PB_04
PB_05
PA_10
PA_11
PB_00
PB_01
PA_14
PA_15
PA_02
PA_03
PA_09
PA_08
PA_07
PA_06
PB_01
PB_00
PA_14
PA_15

ADSP-21562/21563/21565/21566/21567/21569
GPIO MULTIPLEXING FOR 120-LEAD LQFP PACKAGE
Table 16 and Table 17 identify the pin functions that are multiplexed on the general-purpose I/O pins of the 120-lead LQFP
package.
Table 16. Signal Multiplexing for Port A
Signal Name
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15

Multiplexed Function 0
SPI2_MISOSPI2_MOSISPI2_D2
SPI2_D3
SPI2_CLK
SPI2_SEL1
SPI0_CLK
SPI0_MISO
SPI0_MOSISPI0_SEL1
TWI0_SCL
TWI0_SDA
C0_FLG0
C0_FLG1
TWI2_SCL
TWI2_SDA

Multiplexed Function 1
OSPI0_MISO/D1
OSPI0_MOSI/D0
OSPI0_D2
OSPI0_D3
OSPI0_CLKOSPI0_SEL1
UART0_TX
UART0_RX
UART0_RTS
UART0_CTS
SPI1_CLK
SPI1_MISO
SPI1_MOSISPI1_SEL1
SPI1_D2
SPI1_D3

Multiplexed Function 2

Multiplexed Function Input Tap

TWI3_SCL
TWI3_SDA

TM0_ACLK3

Multiplexed Function 1
TWI1_SCL
TWI1_SDA
C0_FLG3
C0_FLG2
SPI1_RDY
SPI2_RDY

Multiplexed Function 2
UART1_RTS
UART1_CTSOSPI0_D4
OSPI0_D5
OSPI0_D6
OSPI0_D7
TM0_TMR0
HADC0_EOC_DOUT
TM0_TMR1
TM0_TMR2
UART1_RX
UART1_TX

SPI2_SS
TM0_ACLK1
TM0_ACI0
TM0_ACLK2
SPI0_SS
TM0_ACI4
SPI1_SS
TM0_ACI1

Table 17. Signal Multiplexing for Port B
Signal Name
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05

Multiplexed Function 0MLB0_DAT
MLB0_SIG
MLB0_CLK
TM0_TMR3
TM0_TMR4
TM0_TMR5

Rev. D |SPI2_SEL2
SPI0_SEL2

Page 35 of 102 |June 2023

Multiplexed Function Input Tap
TM0_ACI3
TM0_CLK
TM0_ACLK4
CNT0_UD
CNT0_ZM
CNT0_DGADSP-21562/21563/21565/21566/21567/21569
ADSP-2156x DESIGNER QUICK REFERENCE
Table 18 provides a quick reference summary of pin related
information for circuit board design. The columns in this tableprovide the following information:• The signal name column includes the signal name for every
pin and the GPIO multiplexed pin function, whereapplicable.
• The type column identifies the I/O type or supply type of
the pin. The abbreviations used in this column are analog(a), supply (s), ground (g) and Input, Output, and InOut.
• The driver type column identifies the driver type used by
the corresponding pin. The driver types are defined in the
Output Drive Currents section of this data sheet.
• The internal termination column specifies the termination
present after the processor is powered up (both duringreset and after reset).

• The reset termination column specifies the termination
present when the processor is in the reset state.
• The reset drive column specifies the active drive on the signal when the processor is in the reset state.
• The power domain column specifies the power supply
domain in which the signal resides.
• The description and notes column identifies any special
requirements or characteristics for a signal. These recommendations apply whether or not the hardware blockassociated with the signal is featured on the product. If no
special requirements are listed, the signal can be left unconnected if it is not used. For multiplexed GPIO pins, thiscolumn identifies the functions available on the pin.

Table 18. ADSP-2156x Designer Quick Reference
Signal Name
DAI0_PIN01

Type
InOut

DAI0_PIN02

InOut

DAI0_PIN03

InOut

DAI0_PIN04

InOut

DAI0_PIN05

InOut

DAI0_PIN06

InOut

DAI0_PIN07

InOut

DAI0_PIN08InOut

DAI0_PIN09

InOut

DAI0_PIN10InOut

DAI0_PIN11

InOut

DAI0_PIN12InOut

DAI0_PIN19

InOut

DAI0_PIN20

InOut

DAI1_PIN01

InOut

Driver Internal
ResetType Termination
Termination Reset Drive Power Domain Description and Notes
A
Programmable
None
None
VDD_EXT
Desc: DAI0 Pin 1
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: DAI0 Pin 2
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: DAI0 Pin 3
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: DAI0 Pin 4
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: DAI0 Pin 5
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: DAI0 Pin 6
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: DAI0 Pin 7
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: DAI0 Pin 8
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: DAI0 Pin 9
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: DAI0 Pin 10
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: DAI0 Pin 11
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: DAI0 Pin 12
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: DAI0 Pin 19
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: DAI0 Pin 20
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: DAI1 Pin 1
pull-up/pull-down1
Notes: See note2

Rev. D |Page 36 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
Table 18. ADSP-2156x Designer Quick Reference (Continued)
Signal Name
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10

Driver Internal
ResetType Termination
Termination Reset Drive Power Domain Description and Notes
A
Programmable
None
None
VDD_EXT
Desc: DAI1 Pin 2
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: DAI1 Pin 3
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: DAI1 Pin 4
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: DAI1 Pin 5
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: DAI1 Pin 6
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: DAI1 Pin 7
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: DAI1 Pin 8
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: DAI1 Pin 9
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: DAI1 Pin 10
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: DAI1 Pin 11
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: DAI1 Pin 12
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: DAI1 Pin 19
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: DAI1 Pin 20
pull-up/pull-down1
Notes: See note2
Output B
None
None
L
VDD_DMC
Desc: DMC0 Address 0
Notes: No notes
Output B
None
None
L
VDD_DMC
Desc: DMC0 Address 1
Notes: No notes
Output B
None
None
L
VDD_DMC
Desc: DMC0 Address 2
Notes: No notes
Output B
None
None
L
VDD_DMC
Desc: DMC0 Address 3
Notes: No notes
Output B
None
None
L
VDD_DMC
Desc: DMC0 Address 4
Notes: No notes
Output B
None
None
L
VDD_DMC
Desc: DMC0 Address 5
Notes: No notes
Output B
None
None
L
VDD_DMC
Desc: DMC0 Address 6
Notes: No notes
Output B
None
None
L
VDD_DMC
Desc: DMC0 Address 7
Notes: No notes
Output B
None
None
L
VDD_DMC
Desc: DMC0 Address 8
Notes: No notes
Output B
None
None
L
VDD_DMC
Desc: DMC0 Address 9
Notes: No notes
Output B
None
None
L
VDD_DMC
Desc: DMC0 Address 10
Notes: No notes
Type
InOut

Rev. D |Page 37 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
Table 18. ADSP-2156x Designer Quick Reference (Continued)
Signal Name
DMC0_A11

Driver Internal
TypeType Termination
Output B
None

Reset
Termination Reset Drive Power Domain Description and Notes
None
L
VDD_DMC
Desc: DMC0 Address 11
Notes: No notes
None
L
VDD_DMC
Desc: DMC0 Address 12
Notes: No notes
None
L
VDD_DMC
Desc: DMC0 Address 13
Notes: No notes
None
L
VDD_DMC
Desc: DMC0 Address 14
Notes: No notes
None
L
VDD_DMC
Desc: DMC0 Address 15
Notes: No notes
None
L
VDD_DMC
Desc: DMC0 Bank Address Input 0
Notes: No notes
None
L
VDD_DMC
Desc: DMC0 Bank Address Input 1
Notes: No notes
None
L
VDD_DMC
Desc: DMC0 Bank Address Input 2
Notes: No notes
None
L
VDD_DMC
Desc: DMC0 column address strobe
Notes: No notes
None
L
VDD_DMC
Desc: DMC0 clock
Notes: No notes
None
H
VDD_DMC
Desc: DMC0 clock (complement)
Notes: No notes
None
L
VDD_DMC
Desc: DMC0 clock enableNotes: No notes
None
L
VDD_DMC
Desc: DMC0 Chip Select 0
Notes: No notes
None
None
VDD_DMC
Desc: DMC0 Data 0
Notes: No notes

DMC0_A12

Output B

None

DMC0_A13

Output B

None

DMC0_A14

Output B

None

DMC0_A15

Output B

None

DMC0_BA0

Output B

None

DMC0_BA1

Output B

None

DMC0_BA2

Output B

None

DMC0_CAS

Output B

None

DMC0_CK

Output C

None

DMC0_CK

Output C

None

DMC0_CKE

Output B

None

DMC0_CS0

Output B

None

DMC0_DQ00

InOut

B

DMC0_DQ01

InOut

B

DMC0_DQ02

InOut

B

DMC0_DQ03

InOut

B

DMC0_DQ04

InOut

B

DMC0_DQ05

InOut

B

DMC0_DQ06

InOut

B

Internal logic
ensures that input
signal does not float
Internal logic
Noneensures that input
signal does not float
Internal logic
Noneensures that input
signal does not float
Internal logic
Noneensures that input
signal does not float
Internal logic
Noneensures that input
signal does not float
Internal logic
Noneensures that input
signal does not float
Internal logic
Noneensures that input
signal does not float

Rev. D |None

VDD_DMC

Desc: DMC0 Data 1
Notes: No notes

None

VDD_DMC

Desc: DMC0 Data 2
Notes: No notes

None

VDD_DMC

Desc: DMC0 Data 3
Notes: No notes

None

VDD_DMC

Desc: DMC0 Data 4
Notes: No notes

None

VDD_DMC

Desc: DMC0 Data 5
Notes: No notes

None

VDD_DMC

Desc: DMC0 Data 6
Notes: No notes

Page 38 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
Table 18. ADSP-2156x Designer Quick Reference (Continued)

DMC0_LDM

Driver Internal
ResetType Termination
Termination
B
Internal logic
Noneensures that input
signal does not float
InOut B
Internal logic
Noneensures that input
signal does not float
InOut B
Internal logic
Noneensures that input
signal does not float
InOut B
Internal logic
Noneensures that input
signal does not float
InOut B
Internal logic
Noneensures that input
signal does not float
InOut B
Internal logic
Noneensures that input
signal does not float
InOut B
Internal logic
Noneensures that input
signal does not float
InOut B
Internal logic
Noneensures that input
signal does not float
None
InOut B
Internal logic
ensures that input
signal does not float
Output B
None
None

DMC0_LDQS

InOut

C

Internal logic
Noneensures that input
signal does not float

None

VDD_DMC

DMC0_LDQS

InOut

C

Internal logic
Noneensures that input
signal does not float

None

VDD_DMC

DMC0_ODTOutput B

None

None

L

VDD_DMC

DMC0_RAS

Output B

None

None

L

VDD_DMC

DMC0_RESET

Output B

None

None

L

VDD_DMC

DMC0_RZQ

a

B

None

None

None

VDD_DMC

DMC0_UDM

Output B

None

None

L

VDD_DMC

Signal Name
DMC0_DQ07

DMC0_DQ08

DMC0_DQ09

DMC0_DQ10

DMC0_DQ11

DMC0_DQ12

DMC0_DQ13

DMC0_DQ14

DMC0_DQ15

Type
InOut

Rev. D |Reset Drive Power Domain Description and Notes
None
VDD_DMC
Desc: DMC0 Data 7
Notes: No notes
None

VDD_DMC

Desc: DMC0 Data 8
Notes: No notes

None

VDD_DMC

Desc: DMC0 Data 9
Notes: No notes

None

VDD_DMC

Desc: DMC0 Data 10
Notes: No notes

None

VDD_DMC

Desc: DMC0 Data 11
Notes: No notes

None

VDD_DMC

Desc: DMC0 Data 12
Notes: No notes

None

VDD_DMC

Desc: DMC0 Data 13
Notes: No notes

None

VDD_DMC

Desc: DMC0 Data 14
Notes: No notes

None

VDD_DMC

Desc: DMC0 Data 15
Notes: No notesL

VDD_DMC

Desc: DMC0 data mask for lower
byte
Notes: No notes
Desc: DMC0 data strobe for lower
byte
Notes: No notes
Desc: DMC0 data strobe for lower
byte (complement)
Notes: No notes
Desc: DMC0 on-die termination
Notes: No notes
Desc: DMC0 row address strobe
Notes: No notes
Desc: DMC0 reset (DDR3 only)
Notes: No notes
Desc: DMC0 external calibration
resistor connection
Notes: 34 Ω external pull-down
must be added
Desc: DMC0 data mask for upper
byte
Notes: No notes

Page 39 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
Table 18. ADSP-2156x Designer Quick Reference (Continued)
Signal Name
DMC0_UDQS

Type
InOut

DMC0_UDQS

InOut

DMC0_VREF

Driver Internal
ResetType Termination
Termination Reset Drive Power Domain
C
Internal logic
None
None
VDD_DMC
ensures that input
signal does not float
C

Internal logic
Noneensures that input
signal does not float

None

VDD_DMC

a

None

None

None

VDD_DMC

DMC0_WE

Output B

None

None

L

VDD_DMC

GND

g

None

None

None

HADC0_VIN0

a

NA

none

none

none

VDD_ANA

HADC0_VIN1

a

NA

none

none

none

VDD_ANA

HADC0_VIN2

a

NA

none

none

none

VDD_ANA

HADC0_VIN3

a

NA

none

none

none

VDD_ANA

HADC0_VREFN s

NA

none

none

none

VDD_ANA

HADC0_VREFP

s

NA

none

none

none

VDD_ANA

JTG_TCK

Input

Pull-up

Pull-upNone

VDD_EXTJTG_TDI

Input

Pull-up

Pull-upNone

VDD_EXTJTG_TDO

Output A

None

None

JTG_TMS

InOut

Pull-up

Pull-up

High-Z when VDD_EXT
JTG_TRST islow, notaffected by
SYS_HWRSTNone
VDD_EXTJTG_TRST

Input

Pull-down

Pull-down

None

VDD_EXT

PA_00

InOut

A

ProgrammableNonepull-up/pull-down1

None

VDD_EXT

PA_01

InOut

A

ProgrammableNonepull-up/pull-down1

None

VDD_EXT

A

Rev. D |Page 40 of 102 |June 2023

Description and Notes
Desc: DMC0 data strobe for upper
byte
Notes: No notes
Desc: DMC0 data strobe for upperbyte (complement)
Notes: No notes
Desc: DMC0 voltage reference
Notes: No notes
Desc: DMC0 write enableNotes: No notes
Desc: Ground
Notes: No notes
Desc: HADC0 Analog Input atchannel 0
Notes: Connect to GND if not used3.
Desc: HADC0 Analog Input atchannel 1
Notes: Connect to GND if not used3
Desc: HADC0 Analog Input atchannel 2
Notes: Connect to GND if not used3
Desc: HADC0 Analog Input atchannel 3
Notes: Connect to GND if not used3
Desc: HADC0 Ground Reference for
ADC
Notes: Connect to GND if not used3
Desc: HADC0 External Reference
for ADC
Notes: Connect to VDD_REF if
HADC/TMU is not used.
Desc: JTAG clock
Notes: See note2
Desc: JTAG serial data in
Notes: See note2
Desc: JTAG serial data out
Notes: No notes

Desc: JTAG mode selectNotes: See note2
Desc: JTAG reset
Notes: See note2
Desc: Port A Position 0
Notes: See note2
Desc: Port A Position 1
Notes: See note2

ADSP-21562/21563/21565/21566/21567/21569
Table 18. ADSP-2156x Designer Quick Reference (Continued)
Signal Name
PA_02

Type
InOut

PA_03

InOut

PA_04

InOut

PA_05

InOut

PA_06

InOut

PA_07

InOut

PA_08

InOut

PA_09

InOut

PA_10

InOut

PA_11

InOut

PA_12

InOut

PA_13

InOut

PA_14

InOut

PA_15

InOut

PB_00

InOut

PB_01

InOut

PB_02

InOut

PB_03

InOut

PB_04

InOut

PB_05

InOut

PB_06

InOut

PB_07

InOut

PB_08

InOut

PB_09

InOut

Driver Internal
ResetType Termination
Termination Reset Drive Power Domain Description and Notes
A
Programmable
None
None
VDD_EXT
Desc: Port A Position 2
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port A Position 3
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port A Position 4
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port A Position 5
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port A Position 6
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port A Position 7
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port A Position 8
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port A Position 9pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port A Position 10
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port A Position 11
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port A Position 12
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port A Position 13
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port A Position 14
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port A Position 15
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port B Position 0
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port B Position 1
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port B Position 2
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port B Position 3
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port B Position 4
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port B Position 5
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port B Position 6
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port B Position 7
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port B Position 8
pull-up/pull-down1
Notes: See note2
A
Programmable
None
None
VDD_EXT
Desc: Port B Position 9pull-up/pull-down1
Notes: See note2

Rev. D |Page 41 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
Table 18. ADSP-2156x Designer Quick Reference (Continued)
Signal Name
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07

SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0SYS_CLKOUT
SYS_FAULTSYS_HWRST

SYS_RESOUT

Driver Internal
ResetType Termination
Termination Reset Drive Power Domain Description and Notes
A
Programmable
None
None
VDD_EXT
Desc: Port B Position 10
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: Port B Position 11
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: Port B Position 12
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: Port B Position 13
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: Port B Position 14
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: Port B Position 15
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: Port C Position 0
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: Port C Position 1
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: Port C Position 2
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: Port C Position 3
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: Port C Position 4
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: Port C Position 5
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: Port C Position 6
pull-up/pull-down1
Notes: See note2
InOut A
Programmable
None
None
VDD_EXT
Desc: Port C Position 7 (default ispull-up/pull-down1
SYS_FAULT)
Notes: External pull-down required
to keep signal in deasserted state
Input NA
None
None
None
VDD_EXT
Desc: Boot Mode Control 0
Notes: Cannot be left unconnected
Input NA
None
None
None
VDD_EXT
Desc: Boot Mode Control 1
Notes: Cannot be left unconnected
Input NA
None
None
None
VDD_EXT
Desc: Boot Mode Control 2
Notes: Cannot be left unconnected
a
NA
None
None
None
VDD_REF
Desc: Clock/crystal input
Notes: Cannot be left unconnected
a
A
None
None
None
VDD_EXT
Desc: Processor clock output
Notes: No notes
InOut A
None
None
None
VDD_EXT
Desc: Active low fault output
Notes: External pull-up required tokeep signal in deasserted state
Input NA
None
None
None
VDD_EXT
Desc: Processor hardware reset
control
Notes: Cannot be left unconnected
Output A
None
None
L
VDD_EXT
Desc: Reset output
Notes: No notes
Type
InOut

Rev. D |Page 42 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
Table 18. ADSP-2156x Designer Quick Reference (Continued)
Driver Internal
Type Termination
NA
None

Signal NameSYS_XTAL0TypeaVDD_ANAsnone

VDD_DMCs

None

VDD_EXTs

None

VDD_INTs

None

VDD_REF

s

None

Reset
Termination Reset Drive Power Domain Description and Notes
None
None
VDD_REF
Desc: Crystal output
Notes: Leave unconnected if an
oscillator provides SYS_CLKIN0
none
none
Desc: Analog VDD
Notes: VDD_REF can be used tosource the VDD_ANA power supply
for HADC and TMU.
None
None
Desc: DMC voltage domain
Notes: No notes
None
None
Desc: External voltage domain
Notes: No notes
None
None
Desc: Internal voltage domain
Notes: No notes
None
None
Desc: External voltage reference
Notes: VDD_REF can be used tosource the VDD_ANA power supply
for HADC and TMU.

1

Disable by default.
When present, the internal pull-up/pull-down design holds the internal path from the pins at the expected logic levels. To pull up or pull down the external pads to the expected
logic levels, use external resistors.
3
All HADC0_VINx pins and the HADC0_VREFN pin can be connected directly to GND if HADC and TMU are not used.
2

Rev. D |Page 43 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
SPECIFICATIONSSpecifications are subject to change without notice. For information about product specifications, contact your Analog Devices, Inc.,
representative.

OPERATING CONDITIONSAll specifications and characteristics apply across the entire operating conditions range unless otherwise noted.
Parameter

Conditions

Internal (Core) Supply Voltage
External (I/O) Supply Voltage
Analog Power Supply Voltage
DDR3L Controller Supply Voltage
DDR3 Controller Supply Voltage
External (I/O) Reference Supply Voltage
VDD_REF2
DDR3 Reference Voltage
VDDR_VREF3
4
VDELTA_EXT_REF (VDD_EXT – VDD_REF) and (VDD_EXT – VDD_ANA)
HADC Reference Voltage
VHADC_REF5
HADC Input Voltage
VHADC0_VINxHigh Level Input Voltage
VIH6
2
High Level Clock Input Voltage
VIHCLKIN
Low Level Input Voltage
VIL6
Low Level Clock Input Voltage
VILCLKIN2
7
Low Level Input Voltage
VIL_DDR3L
Low Level Input Voltage
VIL_DDR37
High Level Input Voltage
VIH_DDR3L7
7High Level Input Voltage
VIH_DDR3
CONSUMER GRADE
Junction Temperature
TJ
400-Ball CSP_BGA
Junction Temperature
TJ
120-Lead LQFP_EP
INDUSTRIAL GRADE
Junction Temperature
TJ
400-Ball CSP_BGA
Junction Temperature
TJ
120-Lead LQFP_EP
AUTOMOTIVE GRADE8
TJ
Junction Temperature
400-Ball CSP_BGA
TJ
Junction Temperature
120-Lead LQFP_EP

400 MHz ≤ CCLK ≤ 1 GHz 0.95
1.00
1.05
V
3.13
3.30
3.47
V
1.71
1.80
1.89
V
1.283
1.350
1.418
V
1.425
1.500
1.575
V
1.71
1.80
1.89
V
0.49 × VDD_DMC
0.50 × VDD_DMC 0.51 × VDD_DMC V
–1.89
+1.89
V
1.71
1.80
VDD_ANAV
0
VHADC_REF + 0.09 V
VDD_EXT = 3.47 V
2.0V
VDD_REF = 1.89 V
0.65 × VDD_REF
VDD_REFV
VDD_EXT = 3.13 V
0.8V
VDD_REF = 1.71 V–0.30+0.35 × VDD_REF V
VDD_DMC = 1.283 V
VDDR_VREF – 0.175 V
VDD_DMC = 1.425 V
VDDR_VREF – 0.175 V
VDD_DMC = 1.418 V
VDDR_VREF + 0.175
V
VDD_DMC = 1.575 V
VDDR_VREF + 0.175
V

VDD_INTVDD_EXTVDD_ANAVDD_DMC1Min

Nominal

Max

Unit

0

110

°C

0

110

°C

–40

+125

°C

–40

+125

°C

–40

+125

°C

–40

+125

°C

1

Applies to DDR3L/DDR3 signals.
Applies to SYS_CLKIN0 pin.
3
Applies to DMC0_VREF pins.
4
See Figure 11.
5
VHADC_VREF must always be less than VDD_ANA.
6
Parameter value applies to all input and bidirectional pins except the DMC pins.
7
This parameter applies to all DMC0 pins.
8
Automotive application use profile only. Not supported for nonautomotive use. Contact Analog Devices for more information.
2

Rev. D | Page 44 of 102 | June 2023

ADSP-21562/21563/21565/21566/21567/21569
Clock Related Operating Conditions
Table 19 describes the core clock, system clock, and peripheral clock timing requirements. The data presented in the table applies to all
speed grades except where noted.
Table 19. Clock Operating Conditions
Parameter
fCCLKCore Clock (CCLK) Frequency

fSYSCLKSYSCLK Frequency

fSCLK0

SCLK0 Frequency

fSCLK1

SCLK1 Frequency

ConditionsMin

fCCLK = 2 × fSYSCLK

400
200

500

MHz

fSYSCLK = N × fSCLK0
where N = 2 or 4 or 6

30

125

MHz

250

MHz

667

MHz

125

MHz

1

Typ

fSYSCLK ≥ fSCLK1
2

fDCLK

DDR3 Clock (DCLK) Frequency

fOCLK

Output Clock (OCLK) Frequency3

All combinations are supported
except for:[fCCLK > 800 MHz and Tj < 0°C andfCCLK:fDCLK = 2:1]

4, 5

fSYS_CLKOUTJ

SYS_CLKOUT Period Jitter

fLCLKTPROG

Programmed Link Port Transmit ClockfLCLKREXT

External Link Port Receive Clock6, 7

fSPTCLKPROG

300

Max

Unit

1000

MHz

±1

%
125

MHz

125

MHz

Programmed SPT Clock When Transmitting Data
and Frame Sync

62.5

MHz

fSPTCLKPROG

Programmed SPT Clock When Receiving Data or
Frame Sync

31.25

MHz

fSPTCLKEXT

External SPT Clock When Receiving Data andFrame Sync6, 7

fSPTCLKEXT ≤ fSCLK0

62.5

MHz

fSPTCLKEXT

External SPT Clock Transmitting Data or
Frame Sync6, 7

fSPTCLKEXT ≤ fSCLK0

31.25

MHz

fSPICLKPROG

Programmed SPI Clock When Transmitting DatafSPICLK:fSCLK0 ratio = 1:1

75

MHz

fSPICLKPROG

Programmed SPI Clock When Receiving DatafSPICLK:fSCLK0 ratio = 1:1

75

MHz

fSPICLKPROG

Programmed SPI Clock When Transmitting DatafSPICLK:fSCLK0 ratio = 1:2

62.5

MHz

fSPICLKPROG

Programmed SPI Clock When Receiving DatafSPICLK:fSCLK0 ratio = 1:2

62.5

MHz

fLCLKREXT ≤ fOCLK_0

6, 7

fSPICLKEXT

External SPI Clock When Receiving DatafSPICLKEXT ≤ fCDU_CLKO0

62.5

MHz

fSPICLKEXT

External SPI Clock When Transmitting Data6, 7

fSPICLKEXT ≤ fCDU_CLKO0

45

MHz

fTMRCLKEXT

External Timer Clock (TMx_CLK)fTMRCLKEXT ≤ fSCLK0 / 4

31.25

MHz

1

When using MLB, there is a requirement that the fSYSCLK value must be a minimum of 100 MHz for 3-pin mode and for all supported speeds.
To ensure proper operation of the DDR3/3L, all the DDR3/3L guidelines must be strictly followed. See ADSP-2156x Board Design Guidelines for Dynamic Memory Controller(EE-418).
3
fOCLK must not exceed fSCLK0 when selected as SYS_CLKOUT.
4
SYS_CLKOUT jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the SYS_CLKIN source. Dueto the dependency on these factors, the measured jitter may be higher or lower than this typical specification for each end application.
5
The value in the Typ field is the percentage of the SYS_CLKOUT period.
6
The maximum achievable frequency for any peripheral in external clock mode is dependent on being able to meet the setup and hold times in the ac timing specifications
section for that peripheral.
7
The peripheral external clock frequency must also be less than or equal to the frequency that clocks the peripheral.
2

Rev. D | Page 45 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
Table 20. Phase-Locked Loop (PLL) Operating Conditions
Parameter
fPLLCLKMin
1.20

PLL Clock Frequency

CSEL

SYSSELSYS_CLKIN

Max
2.00

CCLK

SYSCLK

S0SEL

SCLK0

PLLCLK
PLL
S1SEL
DSEL

DCLK

SCLK1
S1SELEXOSELOUTCLKS1SELEXEN

REFER TO THE ADSP-2156x SHARC+ PROCESSOR HARDWARE REFERENCEFOR INFORMATION ABOUT ALLOWED DIVIDER VALUES AND PROGRAMMING MODELS.

Figure 9. Clock Relationships and Divider Values

Rev. D | Page 46 of 102 | June 2023

Unit
GHz

ADSP-21562/21563/21565/21566/21567/21569
ELECTRICAL CHARACTERISTICS
All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.
Parameter

Conditions

Min
2.4

VOH

High Level Output Voltage

VDD_EXT = minimum,(IOH = –2.0 mA, DS1)1, (IOH = –4.0 mA, DS2)2VOL

Low Level Output Voltage

VDD_EXT = minimum,(IOL = 2.0 mA, DS1)1, (IOL = 4.0 mA, DS2)2

VOH_XTAL3High Level Output Voltage

VDD_REF = minimum, IOH = –1.0 mA

3

Low Level Output Voltage

VDD_REF = minimum, IOL = 1.0 mA

VOL_XTAL

Typ

Max

Unit
V

0.4
1.26

V
V

0.45

V

VOH_DDR3L4

High Level Output Voltage for VDD_DDR = minimum, IOH = –1.0 mA
DDR3L Drive Strength =100 Ω

VOL_DDR3L4

Low Level Output Voltage for VDD_DDR = minimum, IOL = 1.0 mA
DDR3L Drive Strength =100 Ω

VOH_DDR35

High Level Output Voltage for VDD_DDR = minimum, IOH = –1.0 mA
DDR3 Drive Strength = 100 Ω

VOL_DDR35

Low Level Output Voltage for VDD_DDR = minimum, IOL = 1.0 mA
DDR3 Drive Strength = 100 Ω

IIH6High Level Input Current

VDD_EXT = maximum, VIN = VDD_EXT maximum

10

μA

IIL6

Low Level Input Current

VDD_EXT = maximum, VIN = 0 V

10μA

IIL_PU7

Low Level Input Current
Pull-UpVDD_EXT = maximum, VIN = 0 V

200

μA

IIH_PD8High Level Input Current
Pull-Down

VDD_EXT = maximum, VIN = VDD_EXT maximum

200

μA

IOZH9

Three-State Leakage Current

VDD_EXT/VDD_DDR = maximum,
VIN = VDD_EXT/VDD_DDR maximum

10

μA

IOZL9

Three-State Leakage Current

VDD_EXT/VDD_DDR = maximum, VIN = 0 V

10

μA

10

0.963

V
0.32

1.105

V
V

0.32

V

CIN

Input Capacitance

TJ = 25°C

IDD_IDLE

VDD_INT Current in Idle

fCCLK = 1000 MHz
ASFSHARC = 0.35
fSYSCLK = 500 MHz
fSCLK0 = 125 MHzfSCLK1 = 250 MHz(Other clocks are disabled)
No peripheral or DMA activity
TJ = 25°C
VDD_INT = 1.0 V

654

mA

IDD_TYPVDD_INT Current

fCCLK = 1000 MHz
ASFSHARC = 1.0
fSYSCLK = 500 MHz
fSCLK0 = 125 MHzfSCLK1 = 250 MHz(Other clocks are disabled)
DMA data rate = 456 MB/s
TJ = 25°C
VDD_INT = 1.0 V

1157

mA

Rev. D | Page 47 of 102 |5June 2023

pF

ADSP-21562/21563/21565/21566/21567/21569
Parameter

Conditions

Min

Typ

Max

Unit

IDD_IDLE

VDD_INT Current in Idle

fCCLK = 800 MHz
ASFSHARC = 0.35
fSYSCLK = 400 MHz
fSCLK0 = 100 MHz
fSCLK1 = 228.6 MHz(Other clocks are disabled)
No peripheral or DMA activity
TJ = 25°C
VDD_INT = 1.0 V

535

mA

IDD_TYPVDD_INT Current

fCCLK = 800 MHz
ASFSHARC = 1.0
fSYSCLK = 400 MHz
fSCLK0 = 100 MHz
fSCLK1 = 228.6 MHz(Other clocks are disabled)
DMA data rate = 456 MB/s
TJ = 25°C
VDD_INT = 1.0 V

946

mA

IDD_IDLE

VDD_INT Current in Idle

fCCLK = 600 MHz
ASFSHARC = 0.35
fSYSCLK = 300 MHz
fSCLK0 = 75 MHzfSCLK1 = 240 MHz(Other clocks are disabled)
No peripheral or DMA activity
TJ = 25°C
VDD_INT = 1.0 V

417

mA

IDD_TYPVDD_INT Current

fCCLK = 600 MHz
ASFSHARC = 1.0
fSYSCLK = 300 MHz
fSCLK0 = 75 MHzfSCLK1 = 240 MHz(Other clocks are disabled)
DMA data rate = 456 MB/s
TJ = 25°C
VDD_INT = 1.0 V

735

mA

Rev. D | Page 48 of 102 | June 2023

ADSP-21562/21563/21565/21566/21567/21569
Parameter

Conditions

Min

Typ

Max

Unit

IDD_IDLE

VDD_INT Current in Idle

fCCLK = 400 MHz
ASFSHARC = 0.35
fSYSCLK = 200 MHz
fSCLK0 = 100 MHz
fSCLK1 = 250 MHz(Other clocks are disabled)
No peripheral or DMA activity
TJ = 25°C
VDD_INT = 1.0 V

311

mA

IDD_TYPVDD_INT Current

fCCLK = 400 MHz
ASFSHARC = 1.0
fSYSCLK = 200 MHz
fSCLK0 = 100 MHz
fSCLK1 = 250 MHz(Other clocks are disabled)
DMA data rate = 456 MB/s
TJ = 25°C
VDD_INT = 1.0 V

536

mA

IDD_INT11

VDD_INT Current

fCCLK 0 MHz
fSCLK0/1  0 MHz

IDD_INT_TOT
mA
See equation in
the TotalInternal Power
Dissipation
section.

1

Applies to all output and bidirectional pins operating at less than or equal to 62.5 MHz, except DMC and SYS_XTAL0.
Applies to all output and bidirectional pins operating above 62.5 MHz and less than or equal to 125 MHz, except DMC.
3
Applies to SYS_XTAL0 pin.
4
Applies to all DMC output and bidirectional signals in DDR3L mode.
5
Applies to all DMC output and bidirectional signals in DDR3 mode.
6
Applies to input pins: SYS_BMODE2-0, SYS_CLKIN, and SYS_HWRST.
7
Applies to input pins with internal pull-ups: JTG_TDI, JTG_TMS, and JTG_TCK.
8
Applies to JTAG_TRST signal.
9Applies to signals: PA15 to PA0, PB15 to PB0, PC7 to PC0, DAI0_PINx, DAI1_PINx, DMC0_DQx, DMC0_LDQS, DMC0_UDQS, DMC0_LDQS, DMC0_UDQS,
SYS_FAULT, and JTG_TDO.
10
Applies to all signal pins.
11
See Estimating Power for ADSP-2156x SHARC+ Processors (EE-414) for further information.
2

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ADSP-21562/21563/21565/21566/21567/21569
Total Internal Power Dissipation

Application Dependent Current

Total power dissipation has two components:

The application dependent currents include the dynamic current in the core clock domain of the SHARC+ core, as well as
the dynamic current in the accelerator block.

• Static, including leakage current• Dynamic, due to transistor switching characteristics foreach clock domain

Dynamic current consumed by the core is subject to an activity
scaling factor (ASF) that represents application code running on
the processor core (see Table 22). The ASF is combined with the
CCLK frequency and VDD_INT dependent dynamic current data
in Table 23 to calculate this portion of the total dynamic power
dissipation component.

Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and processor activity. The following equation describes the internalcurrent consumption.
IDD_INT_TOT = IDD_INT_STATIC + IDD_INT_CCLK_SHARC_DYN +IDD_INT_DCLK_DYN + IDD_INT_SYSCLK_DYN +IDD_INT_SCLK0_DYN + IDD_INT_SCLK1_DYN +IDD_INT_OCLK_DYN + IDD_INT_ACCL_DYN +IDD_INT_DMA_DR_DYN

IDD_INT_CCLK_SHARC_DYN = Table 23 × ASFSHARC
Table 22. Activity Scaling Factors for the SHARC+® Core
(ASFSHARC)

where IDD_INT_STATIC is the sole contributor to the static power
dissipation component and is specified as a function of voltage(VDD_INT) and junction temperature (TJ) in Table 21.

IDD_INT Power Vector

ASF

IDD-LS

0.21

IDD-IDLE

0.35

Table 21. Static Current—IDD_INT_STATIC (mA)IDD-NOP

0.68

IDD-TYP_3070

0.81

Voltage (VDD_INT)
TJ (°C)

0.95 V

1.00 V

1.05 VIDD-TYP_5050

0.92

–45

12

15

18

IDD-TYP_7030

1.00

–40

13

15

19

IDD-PEAK_100

1.09

–20

17

21

27

–10

21

26

32

Table 23. Dynamic Current for SHARC+®Core(mA, with ASF = 1.00)

0

26

32

39

+10

33

40

49

fCCLK (MHz)0.95 V

1.00 V

1.05 V

+25

48

58

70

400

271

285

299

+40

71

84

102

450

305

321

337

+55

105

124

148

500

339

357

374

+70

157

184

217

550

373

392

412

+85

235

272

318

600

406

428

449

+100

347

401

465

650

440

463

487

+105

397

457

530

700

474

499

524

+115

515

591

683

750

508

535

561

+125

665

762

880

800

542

570

599

850

576

606

636

900

610

642

674

950

643

677

711

1000

677

713

749

Voltage (VDD_INT)The other eight addends in the IDD_INT_TOT equation comprisethe dynamic power dissipation component and fall into four
broad categories: application dependent currents, clock currents, currents from high speed peripheral operation, and datatransmission currents.

Rev. D |Page 50 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
HADC DC Accuracy

Clock Current
The dynamic clock currents provide the total power dissipatedby all transistors switching in the clock paths. The power dissipated by each clock domain is dependent on voltage (VDD_INT),
operating frequency, and a unique scaling factor.

Table 25. HADC DC Accuracy1
Parameter
Resolution
No Missing Codes (NMC)
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
Offset Error Matching
Gain Error
Gain Error Matching

IDD_INT_SYSCLK_DYN (mA) = 0.626 × fSYSCLK (MHz) ×
VDD_INT (V)IDD_INT_SCLK0_DYN (mA) = 0.23 × fSCLK0 (MHz) × VDD_INT (V)IDD_INT_SCLK1_DYN (mA) = 0.018 × fSCLK1 (MHz) ×
VDD_INT (V)IDD_INT_DCLK_DYN (mA) = 0.125 × fDCLK (MHz) × VDD_INT (V)IDD_INT_OCLK_DYN (mA) = 0.048 × fOCLK (MHz) × VDD_INT (V)1

Data Transmission Current

2

The data transmission current represents the power dissipatedwhen moving data throughout the system via DMA. This current is proportional to the data rate. Refer to the power
calculator available with Estimating Power for ADSP-2156x
SHARC+ Processors (EE-414) to estimate IDD_INT_DMA_DR_DYN
based on the bandwidth of the data transfer.

IDD_HADC_ACTIVE

Conditions
Current consumption on
VDD_HADC
HADC is powered on, but notconverting
Current consumption on
VDD_HADC during a conversion

Parameter
Conversion Time1
Throughput Range
TWAKEUP1

Typ Unit
2.0 mASee the Operating Conditions section for the HADC0_VINx specification.
LSB = HADC0_VREFP ÷ 1024.

Table 26. HADC Timing Specifications

HADC Electrical Characteristics

Parameter
IDD_HADC_IDLE

Unit2
Bits
Bits
LSB
LSB
LSB
LSB
LSB
LSB

HADC Timing Specifications

HADC

Table 24. HADC Electrical Characteristics

Typ
10
10
±2
±1
±5
±5
±3
±3

Typ
20 × TSAMPLE

Max
1
100

Unit
μs
MSPS
μs

Refer to the ADSP-21562/3/5/6/7/9 SHARC+ Processor Hardware Reference for
additional information about TSAMPLE.

TMU
TMU Characteristics

2.5 mAIDD_HADC_POWERDOWN Current consumption on
40
VDD_HADC
Analog circuitry of the HADC ispowered down

μA

Table 27. TMU Characteristics
Parameter
Resolution
Accuracy

Typ
1
±6

Unit
°C
°C

Table 28. TMU Gain and Offset
Junction Temperature Range TMU_GAIN
TMU_OFFSET–40°C to +40°C
Contact Analog Devices, Inc.
40°C to 85°C
Contact Analog Devices, Inc.
85°C to 125°C
Contact Analog Devices, Inc.

Rev. D |Page 51 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed in Table 29 may cause permanent damage to the product. This is a stress rating only;
functional operation of the product at these or any other conditions above those indicated in the operational section of thisspecification is not implied. Operation beyond the maximum
operating conditions for extended periods may affect productreliability.
Table 29. Absolute Maximum Ratings
Parameter
Internal (Core) Supply Voltage(VDD_INT)
External (I/O) Supply Voltage(VDD_EXT)
External (I/O) Reference Supply
Voltage (VDD_REF)(VDD_EXT – VDD_REF) and(VDD_EXT – VDD_ANA) (VDELTA_EXT_REF)
DDR3 Controller Supply Voltage(VDD_DMC)
Analog Supply Voltage (VDD_ANA)
HADC Reference Voltage (VHADC_REF)
DDR3 Input Voltage1
Digital Input Voltage1, 2
TWI Input Voltage1, 3Output Voltage Swing
Analog Input Voltage4
IOH/IOL Current per Signal2
Storage Temperature Range
Junction Temperature While Biased

Rating–0.3 V to +1.05 V

Table 30. Maximum Duty Cycle for Input Transient Voltage
for VDD_INT and VDD_EXT
VDD_INT (V)1
1.120
1.103
1.086
1.077
1.065
1.056
1.050

VDD_EXT (V)1

3.470

Maximum Duty Cycle2
5%
10%
20%
30%
50%
75%
100%

1

The individual values cannot be combined for analysis of a single instance ofovershoot or undershoot. The worst case observed value must fall within one ofthe voltages specified and the total duration of the overshoot or undershoot(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
2
Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. This is equivalent to the measured duration of a single instance ofovershoot or undershoot as a percentage of the period of occurrence.

–0.3 V to +3.47 V–0.3 V to +1.89 V–1.89 V to +1.89 V

Table 31. Maximum Duty Cycle for Input Transient Voltage–0.3 V to +1.60 V–0.3 V to +1.89 V–0.3 V to +1.89 V–0.3 V to +1.60 V–0.3 V to +3.47 V–0.3 V to +3.47 V–0.3 V to VDD_EXT +0.5 V–0.2 V to VDD_ANA +0.09 V
6 mA (maximum)–65C to +150C
125C

3.3 V VIN Max (V)1 1.8 V VIN Max (V)1 Maximum Duty Cycle2
3.47
1.89
100%
1

The individual values cannot be combined for analysis of a single instance ofovershoot or undershoot. The worst case observed value must fall within one ofthe voltages specified and the total duration of the overshoot or undershoot(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
2
Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. This is equivalent to the measured duration of a single instance ofovershoot or undershoot as a percentage of the period of occurrence.

ESD CAUTION
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.

1

Applies only when the related power supply (VDD_DMC or VDD_EXT) is within
specification. When the power supply is below specification, the range is thevoltage being applied to that power domain ± 0.2 V.
2Applies to 100% transient duty cycle.
3
Applies to TWI_SCL and TWI_SDA.
4
Applies only when VDD_ANA is within specifications and ≤ 1.8 V. When VDD_ANA
is within specifications and > 1.8 V, the maximum rating is 1.89 V. WhenVDD_ANA is below specifications, the range is VDD_ANA ± 0.09 V.

Rev. D |Page 52 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
TIMING SPECIFICATIONSAll specifications and characteristics apply across the entire operating conditions range unless otherwise noted.

Power-Up Reset Timing
Table 32 and Figure 10 show the relationship between power supply startup and processor reset timing, as relating to the clock generation
unit (CGU) and the reset control unit (RCU).
In Figure 10, the VDD_SUPPLIES are VDD_INT, VDD_EXT, VDD_DMC, VDD_REF, and VDD_ANA. There are some considerations that systemdesign must take into account:.
1. The VDELTA_EXT_REF specification must be met at all times, including during power-up reset and when powering down the device(Figure 11).
2. Any I/O pin operating in the VDD_EXT power domain, such as SYS_HWRST, SYS_RESOUT, and so on, may actually momentarily
drive until the VDD_SUPPLIES rail is powered up. Systems sharing these signals on the board must determine if there are any issues thatneed to be addressed based on this behavior.
Table 32. Power-Up Reset Timing
Parameter

Min

Max

Unit

Timing Requirements
tRST_IN_PWR

SYS_HWRST Deasserted after VDD_SUPPLIES (VDD_INT, VDD_EXT, VDD_DMC, VDD_REF,
VDD_ANA) and SYS_CLKIN0 are Stable and Within Specification

11 × tCKIN

ns

tPWR_UPVDD_SUPPLIES Power Ramp Up

100

μs

tPWR_DOWNVDD_SUPPLIES Power Ramp Down

100

μs

SYS_HWRSTtRST_IN_PWR
SYS_CLKIN0V
DD_SUPPLIESVDD_SUPPLIESt PWR_DOWNt PWR_UP

Figure 10. Power-Up Reset Timing

VDD_EXTVDD_EXT ‫ ޤ‬VDD_REF AND VDD_EXT ‫ ޤ‬VDD_ANA
MUST NOT EXCEED VDELTA_EXT_REF AT ANY TIME.
VDD_REF,VDD_ANA

0V
POWER-UP

OPERATIONAL

Figure 11. Power-Up and Power-Down Voltage Delta Requirement

Rev. D | Page 53 of 102 |June 2023

POWER-DOWN

ADSP-21562/21563/21565/21566/21567/21569
Clock and Reset Timing
Table 33 and Figure 12 describe clock and reset operations related to the CGU and RCU. Per the CCLK, SYSCLK, SCLKx, DCLK, andOCLK timing specifications in Table 19 (Clock Operating Conditions), combinations of SYS_CLKIN0 and clock multipliers must notselect clock rates in excess of the maximum instruction rate of the processor.
Table 33. Clock and Reset Timing
Parameter

Min

Max

Unit

20

30

MHz

30

MHz

Timing Requirements
fCKIN

SYS_CLKIN0 Frequency (Crystal)1, 2
1, 2

SYS_CLKIN0 Frequency (External SYS_CLKIN0)20

tCKINLSYS_CLKIN0 Low Pulse1

16.67

tCKINH

SYS_CLKIN0 High Pulse

1

16.67

ns

tWRST

RESET Asserted Pulse Width Low3

11 × tCKIN

ns

ns

1

Applies to PLL bypass mode and PLL nonbypass mode.
The tCKIN period (see Figure 12) equals 1/fCKIN.
3Applies after power-up sequence is complete. See Table 32 and Figure 10 for power-up reset timing.
2

tCKIN
SYS_CLKIN0tCKINLtCKINHtWRST
SYS_HWRST

Figure 12. Clock and Reset Timing

Dynamic Memory Controller (DMC)—Clock, Control, Write and Read Cycle Timing
The DMC clock, control, write and read timings comply with the JEDEC standards. To ensure proper operation of the DDR3/3L, all
DDR3/3L guidelines must be strictly followed. See ADSP-2156x Board Design Guidelines for Dynamic Memory Controller (EE-418).

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ADSP-21562/21563/21565/21566/21567/21569
Link Ports (LPs)In LP receive mode, the LP clock is supplied externally and is called fLCLKREXT, therefore the period can be represented by1t LCLKREXT = --------------f LCLKREXTIn LP transmit mode, the programmed LP clock (fLCLKTPROG) frequency in megahertz is set by the following equation where VALUE is afield in the LP_DIV register that can be set from 1 to 255:
f OCLK_0
f LCLKTPROG = ---------------------

 VALUE  2 

In the case where VALUE = 0, fLCLKTPROG = fOCLK_0. For all settings of VALUE, the following equation is true:
1t LCLKTPROG = -----------------f LCLKTPROG
Calculation of the link receiver data setup and hold relative to the link clock is required to determine the maximum allowable skew thatcan be introduced in the transmission path length difference between LPx_Dx and LPx_CLK. Setup skew is the maximum delay that canbe introduced in LPx_Dx relative to LPx_CLK (setup skew = tLCLKTWH minimum – tDLDCH – tSLDCL). Hold skew is the maximum delaythat can be introduced in LPx_CLK relative to LPx_Dx (hold skew = tLCLKTWL minimum – tHLDCH – tHLDCL). See Table 35 for LP transmit
timing.
Table 34. LPs—Receive1
Parameter

Min

Max

Unit

125

MHz

Timing Requirements
fLCLKREXT

LPx_CLK FrequencytSLDCL

Data Setup Before LPx_CLK Low

1.5

ns

tHLDCL

Data Hold After LPx_CLK Low

1.4

ns

2

tLCLKEW

LPx_CLK PeriodtLCLKREXT – 1

nstLCLKRWL

LPx_CLK Width Low2

0.5 × tLCLKREXTns

tLCLKRWH

LPx_CLK Width High2

0.5 × tLCLKREXT

ns

Switching CharacteristictDLALC

LPx_ACK Low Delay After LPx_CLK Low3

1.5 × tOCLK_0 + 4

1

2.5 × tOCLK_0 + 12

nsSpecifications apply to LP0 and LP1.
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external LPx_CLK. For the external
LPx_CLK ideal maximum frequency, see the fLCLKREXT specification in Table 19. For LPx_CLK generated by ADSP-215xx link ports transmit and connected to link ports
receive, the width or period requirement can be taken from Table 35, LPs–Transmit.
3
LPx_ACK goes low with tDLALC relative to fall of LPx_CLK after first byte, but does not go low if the link buffer of the receiver is not about to fill.
2

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ADSP-21562/21563/21565/21566/21567/21569
tLCLKEWtLCLKRWHtLCLKRWL

LPx_CLKtHLDCLtSLDCLLPx_D7–0

IN

tDLALC
LPx_ACK (OUT)

Figure 13. LPs—Receive

Table 35. LPs—Transmit1
Parameter

Min

Max

Unit

Timing Requirements
tSLACH

LPx_ACK Setup Before LPx_CLK Low

2 × tOCLK_0 + 13.5

ns

tHLACH

LPx_ACK Hold After LPx_CLK Low

–2.5

ns

Switching Characteristics
tDLDCH

Data Delay After LPx_CLK HightHLDCH

Data Hold After LPx_CLK High

–1.04

2

LPx_CLK Width Low

0.4 × tLCLKTPROG

0.6 × tLCLKTPROG

ns

tLCLKTWH2

LPx_CLK Width High

0.4 × tLCLKTPROG

0.6 × tLCLKTPROG

ns

LPx_CLK Period

N × tLCLKTPROG – 0.7

LPx_CLK Low Delay After LPx_ACK HightOCLK_0 + 4

tLCLKTWLtLCLKTW
tDLACLK

2

2.23

ns
ns

ns
2 × tOCLK_0 + 1 × tLPCLK + 10

1

Specifications apply to LP0 and LP1.
2
See Table 19 for details on the minimum period that can be programmed for fLCLKTPROG.

tLCLKTWHtLCLKTWLLAST BYTE
TRANSMITTEDFIRST BYTE
TRANSMITTED1

LPx_CLKtDLDCHtHLDCH

LPx_Dx(DATA)OUT

tSLACH

tHLACH

tDLACLK

LPx_ACK (IN)NOTES
The tSLACH and tHLACH specifications apply only to the LPx_CLK falling edge. If these specifications are met,
LPx_CLK extends and the dotted LPx_CLK falling edge does not occur as shown. The position of thedotted falling edge can be calculated using the tLCLKTWH specification. tLCLKTWH Min must be used for tSLACH
and tLCLKTWH Max for tHLACH.

Figure 14. LPs—Transmit

Rev. D | Page 56 of 102 | June 2023

ns

ADSP-21562/21563/21565/21566/21567/21569
Serial Ports (SPORTs)
To determine whether a device is compatible with the SPORT at clock speed n, the following specifications must be confirmed: frame sync
delay and frame sync setup and hold; data delay and data setup and hold; and serial clock (SPTx_CLK) width. In Figure 15, either the rising edge or the falling edge of SPTx_A/BCLK (external or internal) can be used as the active sampling edge.
When externally generated, the SPORT clock is called fSPTCLKEXT:
1t SPTCLKEXT = ----------------------f SPTCLKEXT

When internally generated, the programmed SPORT clock (fSPTCLKPROG) frequency in megahertz is set by the following equation:f SCLK0
f SPTCLKPROG = -----------------------

 CLKDIV + 1 

1t SPTCLKPROG = -------------------------f SPTCLKPROG

where CLKDIV is a field in the SPORT_DIV register that can be set from 0 to 65,535.
Table 36. SPORTs—External Clock1
Parameter

Min

Max

Unit

Timing Requirements
tSFSE

Frame Sync Setup Before SPTx_CLK
2(Externally Generated Frame Sync in Either Transmit or ReceiveMode)2ns

tHFSE

Frame Sync Hold After SPTx_CLK
3(Externally Generated Frame Sync in Either Transmit or ReceiveMode)2

ns

tSDRE

Receive Data Setup Before Receive SPTx_CLK2

2

ns

tHDRE

Receive Data Hold After SPTx_CLK2

3

ns

3

tSPTCLKWSPTx_CLK WidthtSPTCLK

SPTx_CLK Period3

0.5 × tSPTCLKEXT – 1.5

nstSPTCLKEXT – 1.5

ns

Switching Characteristics
tDFSE

Frame Sync Delay After SPTx_CLK(Internally Generated Frame Sync in Either Transmit or ReceiveMode)4tHOFSE

Frame Sync Hold After SPTx_CLK(Internally Generated Frame Sync in Either Transmit or ReceiveMode)4tDDTE

Transmit Data Delay After Transmit SPTx_CLK4

tHDTE

Transmit Data Hold After Transmit SPTx_CLK4

11

2

ns

11
2

1

ns

ns
ns

Specifications apply to all four SPORTs.
Referenced to sample edge.
3
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the ideal maximum external SPTx_CLK.
For the external SPTx_CLK ideal maximum frequency, see the fSPTCLKEXT specification in Table 19.
4
Referenced to drive edge.
2

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ADSP-21562/21563/21565/21566/21567/21569
Table 37. SPORTs—Internal Clock1
Parameter

Min

Max

Unit

Timing Requirements
tSFSI

tHFSI

tSDRI
tHDRI

Frame Sync Setup Before SPTx_CLK(Externally Generated Frame Sync in Either Transmit or
Receive Mode)2

12

Frame Sync Hold After SPTx_CLK(Externally Generated Frame Sync in Either Transmit or
Receive Mode)2–0.5

Receive Data Setup Before SPTx_CLK2

3.4

ns

2

ns

Receive Data Hold After SPTx_CLK

2

ns

ns

Switching Characteristics
tDFSI

Frame Sync Delay After SPTx_CLK (Internally Generated
Frame Sync in Transmit or Receive Mode)3

3.5

tHOFSI

Frame Sync Hold After SPTx_CLK (Internally Generated
Frame Sync in Transmit or Receive Mode)3

tDDTI

Transmit Data Delay After SPTx_CLK3

tHDTI

Transmit Data Hold After SPTx_CLK3–3nstSPTCLKIWSPTx_CLK Width4

0.5 × tSPTCLKPROG – 2

nstSPTCLKWISPTx_CLK Period4tSPTCLKPROG – 1.5

ns

–3

ns
3.5

1

Specifications apply to all four SPORTs.
Referenced to the sample edge.
3
Referenced to drive edge.
4
See Table 19 for details on the minimum period that can be programmed for fSPTCLKPROG.
2

Rev. D | Page 58 of 102 | June 2023

ns

ns

ADSP-21562/21563/21565/21566/21567/21569
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGEDATA RECEIVE—EXTERNAL CLOCKSAMPLE EDGE

DRIVE EDGEtSPTCLKIWSPTx_A/BCLK(SPORT CLOCK)SPTx_A/BCLK(SPORT CLOCK)

tDFSI

tDFSE
tSFSI

tHOFSI

tHFSI

tSFSE

tHFSE

tSDRE

tHDRE

tHOFSE
SPTx_A/BFS(FRAME SYNC)

SPTx_A/BFS(FRAME SYNC)

tSDRI

tHDRI
SPTx_A/BDx(DATA CHANNEL A/B)

SPTx_A/BDx(DATA CHANNEL A/B)

DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGEDATA TRANSMIT—EXTERNAL CLOCKSAMPLE EDGE

DRIVE EDGEtSPTCLKIWSAMPLE EDGEtSPTCLKWSPTx_A/BCLK(SPORT CLOCK)SPTx_A/BCLK(SPORT CLOCK)

tDFSI

tDFSE

tHOFSI

tSFSI

tHFSI

tSFSE

tHOFSE
SPTx_A/BFS(FRAME SYNC)

SPTx_A/BFS(FRAME SYNC)

tDDTI

tDDTE

tHDTI
SPTx_A/BDx(DATA CHANNEL A/B)

SAMPLE EDGEtSPTCLKWtHDTE
SPTx_A/BDx(DATA CHANNEL A/B)

Figure 15. SPORTs

Rev. D | Page 59 of 102 |June 2023

tHFSE

ADSP-21562/21563/21565/21566/21567/21569
Table 38. SPORTs—Enable and Three-State1
Parameter

Min

Max

Unit

Switching Characteristics

1
2

tDDTEN

Data Enable From External Transmit SPTx_CLK22

tDDTTE

Data Disable From External Transmit SPTx_CLK

tDDTIN

Data Enable From Internal Transmit SPTx_CLK2

tDDTTI

2

Data Disable From Internal Transmit SPTx_CLK

1

ns
14

–2.5

ns
2.8

Specifications apply to all four SPORTs.
Referenced to drive edge.

DRIVE EDGE

DRIVE EDGE

SPTx_CLK(SPORT CLOCK EXTERNAL)tDDTENtDDTTE

SPTx_A/BDx(DATA CHANNEL A/B)

DRIVE EDGE

DRIVE EDGE

SPTx_CLK(SPORT CLOCK INTERNAL)tDDTIN
SPTx_A/BDx(DATA CHANNEL A/B)

Figure 16. SPORTs—Enable and Three-State

Rev. D | Page 60 of 102 | June 2023

ns

tDDTTIns

ADSP-21562/21563/21565/21566/21567/21569
The SPTx_TDV output signal becomes active in SPORT multichannel mode. During transmit slots (enabled with active channel selection
registers) the SPTx_TDV is asserted for communication with external devices.
Table 39. SPORTs—Transmit Data Valid (TDV)1
Parameter

Min

Max

Unit

Switching Characteristics

1
2

tDRDVEN

Data Valid Enable Delay From Drive Edge of External Clock2

tDFDVEN

Data Valid Disable Delay From Drive Edge of External Clock2tDRDVIN

Data Valid Enable Delay From Drive Edge of Internal Clock2

tDFDVIN

Data Valid Disable Delay From Drive Edge of Internal Clock2

2
14
–2.5

DRIVE EDGE

DRIVE EDGE

SPTx_CLK(SPORT EXTERNAL CLOCK)tDRDVENtDFDVEN

SPTx_A/BTDVDRIVE EDGE

DRIVE EDGE

SPTx_CLK(SPORT INTERNAL CLOCK)tDRDVINtDFDVIN

SPTx_A/BTDV

Figure 17. SPORTs—Transmit Data Valid Internal and External Clock

June 2023

ns
ns

3.5

Specifications apply to all four SPORTs.
Referenced to drive edge.

Rev. D | Page 61 of 102 |ns

ns

ADSP-21562/21563/21565/21566/21567/21569
Table 40. SPORTs—External Late Frame Sync1
Parameter

Min

Max

Unit

14

ns

Switching Characteristics
tDDTLFSE

Data Delay From Late External Transmit Frame Sync or External Receive Frame
Sync with SPORT_MCTL_A/B bits MCE = 1, MFD = 02

tDDTENFS

Data Enable for SPORT_MCTL_A/B bits MCE = 1, MFD = 02

0.5

ns

1

Specifications apply to all four SPORTs.
2
The tDDTLFSE and tDDTENFS parameters apply to left justified as well as standard serial mode and MCE = 1, MFD = 0.

DRIVE

SAMPLEDRIVE

SPTx_A/BCLK(SPORT CLOCK)tHFSE/ItSFSE/I
SPTx_A/BFS(FRAME SYNC)

tDDTE/ItDDTENFS
SPTx_A/BDx(DATA CHANNEL A/B)

tHDTE/I
1ST BITtDDTLFSE

Figure 18. External Late Frame Sync

Rev. D | Page 62 of 102 | June 2023

2ND BITADSP-21562/21563/21565/21566/21567/21569
Asynchronous Sample Rate Converter (ASRC)—Serial Input Port
The ASRC input signals are routed from the DAI0_PINx pins using the SRU. Therefore, the timing specifications provided in Table 41 arevalid at the DAI0_PINx pins.
Table 41. ASRC, Serial Input Port
Parameter

Min

Max

Unit

Timing Requirements
tSRCSFS1

Frame Sync Setup Before Serial Clock Rising Edge

4

ns

1

Frame Sync Hold After Serial Clock Rising Edge

5.5

ns

1

tSRCHFS

Data Setup Before Serial Clock Rising Edge

4ns

tSRCHD1

Data Hold After Serial Clock Rising Edge

5.5

ns

tSRCCLKW

Clock WidthtSCLK0 – 1

ns

tSRCCLK

Clock Period

2 × tSCLK0nstSRCSD1

The serial clock, data, and frame sync signals can originate from any of the DAI pins. The serial clock and frame sync signals can also originate via PCG or SPORTs. The
input of the PCG can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

DAI0_PIN20–1(SCLK0)tSRCCLKtSRCCLKWtSRCSFStSRCHFS

DAI0_PIN20–1(FS)

tSRCSDtSRCHD

DAI0_PIN20–1(SDATA)

Figure 19. ASRC Serial Input Port Timing

Rev. D | Page 63 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
Asynchronous Sample Rate Converter (ASRC)—Serial Output Port
For the serial output port, the frame sync is an input and it must meet setup and hold times with regard to SCLK0 on the output port. The
serial data output has a hold time and delay specification with regard to the serial clock. The serial clock rising edge is the sampling edge,
and the falling edge is the drive edge.
Table 42. ASRC, Serial Output Port
Parameter

Min

Max

Unit

Timing Requirements
tSRCSFS1

Frame Sync Setup Before Serial Clock Rising Edge

4ns

tSRCHFS

Frame Sync Hold After Serial Clock Rising Edge

5.5

ns

tSRCCLKW

Clock WidthtSCLK0 – 1

ns

tSRCCLK

Clock Period

2 × tSCLK0

ns1

Switching CharacteristicstSRCTDD1

Transmit Data Delay After Serial Clock Falling Edge

1

Transmit Data Hold After Serial Clock Falling EdgetSRCTDH
1

13
1

ns
ns

The serial clock, data, and frame sync signals can originate from any of the DAI pins. The serial clock and frame sync signals can also originate via PCG or SPORTs. The inputof the PCG can be either CLKIN, SCLK0, or any of the DAI pins.

SAMPLE EDGEtSRCCLKtSRCCLKWDAI0_PIN20–1(SCLK0)tSRCSFStSRCHFS

DAI0_PIN20–1(FS)

tSRCTDDtSRCTDH
DAI0_PIN20–1(SDATA)

Figure 20. ASRC Serial Output Port Timing

Rev. D | Page 64 of 102 | June 2023

ADSP-21562/21563/21565/21566/21567/21569
SPI Port—Master Timing
SPI0, SPI1, and SPI2
Table 43 and Figure 21 describe the SPI port master operations.
When internally generated, the programmed SPI clock (fSPICLKPROG) frequency in megahertz is set by the following equation:
f CDU_CLKO0
f SPICLKPROG = ---------------------

 BAUD + 1 

1t SPICLKPROG = -------------------------f SPICLKPROG

where BAUD is a field in the SPIx_CLK register that can be set from 0 to 65,535.
Note that• In dual-mode data transmit, the SPIx_MISO signal is also an output.
• In quad-mode data transmit, the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are also outputs.
• In dual-mode data receive, the SPIx_MOSI signal is also an input.
• In quad-mode data receive, the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are also inputs.
• Quad mode is supported by SPI1 and SPI2.
• CPHA is a configuration bit in the SPI_CTL register.
Table 43. SPI Port—Master Timing1
Parameter

Min

Max

Unit

Timing Requirements
tSSPIDM

Data Input Valid to SPIx_CLK Edge (Data Input Setup)

3.5

ns

tHSPIDM

SPIx_CLK Sampling Edge to Data Input Invalid

2

ns

tSPICLKPROG – 5

ns

Switching Characteristics
tSDSCIM

SPIx_SEL Low to First SPI_CLK Edge for CPHA = 12
SPIx_SEL Low to First SPI_CLK Edge for CPHA = 0

2

1.5 × tSPICLKPROG – 5

nstSPICHM

SPIx_CLK High Period3

0.5 × tSPICLKPROG – 1.5

ns

tSPICLM

SPIx_CLK Low Period

3

0.5 × tSPICLKPROG – 1.5

ns

tSPICLKSPIx_CLK Period3

tSPICLKPROG – 1.5

nsLast SPIx_CLK Edge to SPIx_SEL High for CPHA = 1

2

1.5 × tSPICLKPROG – 5

ns

Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 0

2

tSPICLKPROG – 5

nstSPICLKPROG – 1.5

ns

tHDSM
tSPITDM

Sequential Transfer Delay2, 4

tDDSPIDM

SPIx_CLK Edge to Data Out Valid (Data Out Delay)tHDSPIDM

SPIx_CLK Edge to Data Out Invalid (Data Out Hold)

2.7
–3.75

1

All specifications apply to SPI0, SPI1, and SPI2.
Specification assumes the LEADX and LAGX bits in the SPI_DLY register are 1.
3
See Table 19 for details on the minimum period that can be programmed for tSPICLKPROG.
4
Applies to sequential mode with STOP ≥ 1.
2

Rev. D | Page 65 of 102 |June 2023

ns
ns

ADSP-21562/21563/21565/21566/21567/21569
SPIx_SEL(OUTPUT)tSDSCIMtSPICLMtSPICHMtSPICLKtHDSM

SPIx_CLK(OUTPUT)tHDSPIDM

tDDSPIDMDATA OUTPUTS(SPIx_MOSI)tSSPIDM

CPHA = 1

tHSPIDMDATA INPUTS(SPIx_MISO)tHDSPIDMDATA OUTPUTS(SPIx_MOSI)CPHA = 0

tSSPIDMtHSPIDMDATA INPUTS(SPIx_MISO)

Figure 21. SPI Port—Master Timing

Rev. D | Page 66 of 102 | June 2023

tDDSPIDMtSPITDMADSP-21562/21563/21565/21566/21567/21569
SPI Port—Slave Timing
SPI0, SPI1, and SPI2
Table 44 and Figure 22 describe SPI port slave operations. Note that
• In dual-mode data transmit, the SPIx_MOSI signal is also an output.
• In quad-mode data transmit, the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are also outputs.
• In dual-mode data receive, the SPIx_MISO signal is also an input.
• In quad-mode data receive, the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are also inputs.
• In SPI slave mode, the SPI clock is supplied externally and is called fSPICLKEXT:
1
t SPICLKEXT = ---------------------f SPICLKEXT• Quad mode is supported by SPI1 and SPI2.
• CPHA is a configuration bit in the SPI_CTL register.
Table 44. SPI Port—Slave Timing1
Parameter

Min

Max

Unit

Timing Requirements
tSPICHSSPIx_CLK High Period2

0.5 × tSPICLKEXT – 1.5

ns

tSPICLS

SPIx_CLK Low Period2

0.5 × tSPICLKEXT – 1.5

ns

2

tSPICLKSPIx_CLK PeriodtSPICLKEXT – 1.5

ns

tHDS

Last SPIx_CLK Edge to SPIx_SS Not Asserted

5

ns

tSPITDS

Sequential Transfer DelaytSPICLKEXT – 1.5

ns

tSDSCI

SPIx_SS Assertion to First SPIx_CLK Edge

11.7

ns

tSSPID

Data Input Valid to SPIx_CLK Edge (Data Input Setup)

2

ns

tHSPID

SPIx_CLK Sampling Edge to Data Input Invalid

1.6

ns

Switching CharacteristicstDSOE

SPIx_SS Assertion to Data Out Active

0

14.12

ns

tDSDHI

SPIx_SS Deassertion to Data High Impedance

0

12.6

ns

tDDSPID

SPIx_CLK Edge to Data Out Valid (Data Out Delay)

14.16

ns

tHDSPID

SPIx_CLK Edge to Data Out Invalid (Data Out Hold)

1
2

1.5

ns

All specifications apply to SPI0, SPI1, and SPI2.
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPIx_CLK. For the external
SPIx_CLK ideal maximum frequency, see the fSPICLKTEXT specification in Table 19.

Rev. D | Page 67 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
SPIx_SS(INPUT)tSDSCItSPICLS

tSPICHStHDStSPICLKSPIx_CLK(INPUT)tDSOEtDDSPID
tDDSPIDtHDSPIDtDSDHIDATA OUTPUTS(SPIx_MISO)CPHA = 1

tSSPIDtHSPIDDATA INPUTS(SPIx_MOSI)tDSOEtHDSPID

tDDSPIDtDSDHIDATA OUTPUTS(SPIx_MISO)CPHA = 0tHSPIDtSSPIDDATA INPUTS(SPIx_MOSI)

Figure 22. SPI Port—Slave Timing

Rev. D | Page 68 of 102 | June 2023

tSPITDSADSP-21562/21563/21565/21566/21567/21569
SPI Port—SPIx_RDY Slave Timing
SPIx_RDY provides flow control. CPOL, CPHA, and FCCH are configuration bits in the SPIx_CTL register.
Table 45. SPI Port—SPIx_RDY Slave Timing1
Parameter

Conditions

Min

Max

Unit

FCCH = 0

3 × tCDU_CLKO0

4 × tCDU_CLKO0 + 10

ns

FCCH = 1

4 × tCDU_CLKO0

5 × tCDU_CLKO0 + 10

ns

Switching CharacteristictDSPISCKRDYS SPIx_RDY Deassertion From Last Valid Input SPIx_CLK Edge
1

All specifications apply to all three SPIs.

tDSPISCKRDYSSPIx_CLK(CPOL = 0)
CPHA = 0
SPIx_CLK(CPOL = 1)

SPIx_CLK(CPOL = 0)
CPHA = 1
SPIx_CLK(CPOL = 1)

SPIx_RDY (O)Figure 23. SPIx_RDY Deassertion from Valid Input SPIx_CLK Edge in Slave ModeRev. D | Page 69 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
SPI Port—Open Drain Mode (ODM) Timing
In Figure 24 and Figure 25, the outputs can be SPIx_MOSI, SPIx_MISO, SPIx_D2, and/or SPIx_D3, depending on the mode of operation.
CPOL and CPHA are configuration bits in the SPI_CTL register.
Table 46. SPI Port—ODM Master Mode Timing1
Parameter

Min

Max

Unit

Switching Characteristics

1

tHDSPIODMM

SPIx_CLK Edge to High Impedance From Data Out ValidtDDSPIODMM

SPIx_CLK Edge to Data Out Valid From High Impedance

–1.5

ns
6

ns

Max

Unit

11

ns

All specifications apply to all three SPIs.

tHDSPIODMMtHDSPIODMM

SPIx_CLK(CPOL = 0)

SPIx_CLK(CPOL = 1)

OUTPUT(CPHA = 1)
OUTPUT(CPHA = 0)tDDSPIODMM

tDDSPIODMM

Figure 24. ODM Master Mode

Table 47. SPI Port—ODM Slave Mode1
Parameter

Min

Timing Requirements

1

tHDSPIODMS

SPIx_CLK Edge to High Impedance From Data Out ValidtDDSPIODMS

SPIx_CLK Edge to Data Out Valid From High Impedance0ns

All specifications apply to all three SPIs.

tHDSPIODMS
SPIx_CLK(CPOL = 0)

SPIx_CLK(CPOL = 1)

OUTPUT(CPHA = 1)
OUTPUT(CPHA = 0)tDDSPIODMStDDSPIODMS

Figure 25. ODM Slave ModeRev. D | Page 70 of 102 | June 2023

tHDSPIODMSADSP-21562/21563/21565/21566/21567/21569
SPI Port—SPIx_RDY Master Timing
SPIx_RDY is used to provide flow control. CPOL and CPHA are configuration bits in the SPIx_CTL register, whereas LEADX, LAGX,and STOP are configuration bits in the SPIx_DLY register.
Table 48. SPI Port—SPIx_RDY Master Timing1
Parameter

Conditions

Min

Max

Unit

Timing RequirementtSRDYSCKM

Setup Time for SPIx_RDY
Deassertion Before Last Valid
Data SPIx_CLK Edge

(2 + 2 × BAUD2) × tCDU_CLKO0 + 11

ns

Switching Characteristic
tDRDYSCKM3Assertion of SPIx_RDY to FirstBAUD = 0, CPHA = 0 4.5 × tCDU_CLKO0
SPIx_CLK Edge of Next Transfer
BAUD = 0, CPHA = 1 4 × tCDU_CLKO02

BAUD > 0, CPHA = 0 (1 + 1.5 × BAUD ) × tCDU_CLKO02

BAUD > 0, CPHA = 1 (1 + 1 × BAUD ) × tCDU_CLKO0
1

All specifications apply to all three SPIs.
BAUD value is set using the SPIx_CLK.BAUD bits. BAUD value = SPIx_CLK.BAUD bits + 1.
3
Specification assumes the LEADX, LAGX, and STOP bits in the SPI_DLY register are zero.
2tSRDYSCKM

SPIx_RDY

SPIx_CLK(CPOL = 0)

SPIx_CLK(CPOL = 1)

Figure 26. SPIx_RDY Setup Before SPIx_CLK

Rev. D | Page 71 of 102 |June 2023

5.5 × tCDU_CLKO0 + 11

ns

5 × tCDU_CLKO0 + 11

ns

2

(2 + 2.5 × BAUD ) × tCDU_CLKO0 + 11 ns(2 + 2 × BAUD2) × tCDU_CLKO0 + 11 ns

ADSP-21562/21563/21565/21566/21567/21569
tDRDYSCKM

SPIx_RDY

SPIx_CLK(CPOL = 0)
CPHA = 0
SPIx_CLK(CPOL = 1)

SPIx_CLK(CPOL = 0)
CPHA = 1
SPIx_CLK(CPOL = 1)

Figure 27. SPIx_CLK Switching Diagram after SPIx_RDY AssertionRev. D | Page 72 of 102 | June 2023

ADSP-21562/21563/21565/21566/21567/21569
OSPI Port—Master Timing
OSPI0
Table 49 and Figure 28 describe the OSPI port master operations. Slave mode is not supported for OSPI.
When internally generated, the programmed SPI clock (fSPICLKPROG) frequency in megahertz is set by the following equation:f
SYSCLK
f SPICLKPROG = ----------------------PRG_MBD

1t SPICLKPROG = --------------------------------------f
SPICLKPROG

where PRG_MBD is the master mode baud rate divisor.
Note that• In dual-mode data transmit, the OSPI0_MISO signal is also an output.
• In quad-mode data transmit, the OSPI0_MISO, OSPI0_D2, and OSPI0_D3 signals are also outputs.
• In octal-mode data transmit, the OSPI0_MISO, OSPI0_D2, OSPI0_D3, OSPI0_D4, OSPI0_D5, OSPI0_D6, and OSPI0_D7 signals
are also outputs.
• In dual-mode data receive, the OSPI0_MOSI signal is also an input.
• In quad-mode data receive, the OSPI0_MOSI, OSPI0_D2, and OSPI0_D3 signals are also inputs.
• In octal-mode data receive, the OSPI0_MISO, OSPI0_D2, OSPI0_D3, OSPI0_D4, OSPI0_D5, OSPI0_D6, and OSPI0_D7 signals arealso outputs.
• CPHA is a configuration bit in the OSPI0_CTL register.
Table 49. OSPI0 Port—Master Timing1
Parameter
Timing Requirements
tSSPIDM
Data Input Valid to OSPI0_CLK Sampling
Edge (Data Input Setup) 2
tHSPIDMOSPI0_CLK Sampling Edge to Data Input
Invalid (Data Input Hold)2
Switching Characteristics
OSPI0_SEL Low to First OSPI0_CLK Edge3tSDSCIMOSPI0_CLK High Period4
tSPICHMtSPICLMOSPI0_CLK Low Period4
OSPI0_CLK Period4
tSPICLK
Last OSPI0_CLK Edge to OSPI0_SEL
tHDSM
High for Mode = 05
Last OSPI0_CLK Edge to OSPI0_SEL
High for Mode = 35, 6
tDDSPIDM OSPI0_CLK Edge to Data Out Valid to
Driving Edge (Data Out Delay)7tHDSPIDM OSPI0_CLK Edge to Data Out Invalid to
Driving Edge (Data Out Hold)7tPD
OSPI0_CLK Internal to OSPI0_CLK Output
Delay (Propagation Delay)

Min

Max

Unit

tSYSCLK + 2

ns

1

ns

0.5 × tSPICLKPROG + PRG_CSSOT × tSYSCLK – 1.5
0.5 × tSPICLKPROG – 1.5
0.5 × tSPICLKPROG – 1.5
tSPICLKPROG – 1.5
PRG_CSEOT × tSYSCLK – 1

ns
ns
ns
ns
ns

PRG_CSEOT × tSYSCLK + 0.5 × tSPICLKPROG – 1

ns(PRG_WRHLD + 1) × tSYSCLK + 2.5 ns

PRG_WRHLD × tSYSCLK – 1
2.2

5.5

1

All specifications apply to OSPI0 only.
tSSPIDM and tHSPIDM specifications are characterized for OSPI0_RDC settings of 2 for DDR mode and 4 for SDR mode.
3
PRG_CSSOT = chip select start of transfer (defined in OSPI0_DLY[7:0]).
4
See Table 19 for details on the minimum period that can be programmed for tSPICLKPROG.
5
PRG_CSEOT = chip select end of transfer (defined in OSPI0_DLY[15:8]).
6Mode = clock phase and clock polarity bits (defined inOSPI0_CTL[2:1]).
7
PRG_WRHLD = transmit delay to improve output hold (defined in OSPI0_RDC[19:16]).
2

Rev. D | Page 73 of 102 |ns

June 2023

ns

ADSP-21562/21563/21565/21566/21567/21569
OSPI0_SEL(OUTPUT)OSPI0_CLK(INTERNAL)tPDtSDSCIMtSPICLMtSPICHMtSPICLKtHDSM

OSPI0_CLK(OUTPUT)tHDSPIDM

tDDSPIDMDATA OUTPUTS(OSPI0_MOSI)tSSPIDM

CPHA = 1

tHSPIDMDATA INPUTS(OSPI0_MISO)tHDSPIDMDATA OUTPUTS(OSPI0_MOSI)CPHA = 0

tSSPIDMtHSPIDMDATA INPUTS(OSPI0_MISO)

Figure 28. OSPI Port—Master Timing

Rev. D | Page 74 of 102 | June 2023

tDDSPIDMADSP-21562/21563/21565/21566/21567/21569
Precision Clock Generator (PCG) (Direct Pin Routing)This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes inputs directly from the DAI
pins (via pin buffers) and sends outputs directly to the DAI pins. For the other cases, where the PCG inputs and outputs are not directly
routed to/from DAI pins (via pin buffers), there is no timing data available. All timing parameters and switching characteristics apply to
external DAI pins (DAI0_PINx).
Table 50. PCG (Direct Pin Routing)Parameter

Min

Max

Unit

Timing Requirements
tPCGIP

Input Clock PeriodtSCLK0 × 2

nstSTRIG

PCG Trigger Setup Before Falling Edge of PCG Input 4.5
Clock

ns

tHTRIG

PCG Trigger Hold After Falling Edge of PCG Input
Clock

ns

3

Switching Characteristics
tDPCGIO
tDTRIGCLKtDTRIGFS

1tPCGOW2
1
2

PCG Output Clock and Frame Sync Active Edge Delay 2
After PCG Input Clock10ns

PCG Output Clock Delay After PCG Trigger

2 + (2.5 × tPCGIP)

13.5 + (2.5 × tPCGIP)ns

PCG Frame Sync Delay After PCG Trigger

2.5 + ((2.5 + D – PH) × tPCGIP)

13.5 + ((2.5 + D – PH) × tPCGIP) ns

Output Clock Period

2 × tPCGIP – 1

ns

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-21562/3/5/6/7/9 SHARC+ Processor Hardware Reference.
Normal mode of operation.

tSTRIGtHTRIG

DAI0_PIN20–1
PCG_TRIGx_I

DAI0_PIN20–1
PCG_EXTx_I(CLKIN)tPCGIP

tDPCGIO
DAI0_PIN20–1
PCG_CLKx_O

tDTRIGCLKtDPCGIO

DAI0_PIN20–1
PCG_FSx_O

tDTRIGFS

Figure 29. PCG (Direct Pin Routing)Rev. D | Page 75 of 102 |June 2023

tPCGOWADSP-21562/21563/21565/21566/21567/21569
General-Purpose IO Port Timing
Table 51 and Figure 30 describe I/O timing, related to the general-purpose ports (PORT).
Table 51. General-Purpose Port Timing
Parameter

Min

Max

Unit

Timing Requirement
tWFI

General-Purpose Port Pin Input Pulse Width

2 × tSCLK0 – 1.5

ns

tWFI
GPIO INPUT

Figure 30. General-Purpose Port Timing

General-Purpose I/O Timer Cycle Timing
Table 52, Table 53, and Figure 31 describe timer expired operations related to the general-purpose timer (TIMER0). The width value is thetimer period assigned in the TMx_TMRn_WIDTH register and can range from 1 to 232 – 1. When externally generated, the TMx_CLK
clock is called fTMRCLKEXT:
1t TMRCLKEXT = -----------------------f TMRCLKEXT

Table 52. Timer Cycle Timing—Internal Mode
Parameter
Min
Timing RequirementstWL
Timer Pulse Width Input Low (Measured In SCLK0 Cycles)1 2 × tSCLK0tWHTimer Pulse Width Input High (Measured In SCLK0 Cycles)1 2 × tSCLK0
Switching CharacteristictHTO
Timer Pulse Width Output (Measured In SCLK0 Cycles)2tSCLK0 × WIDTH – 1.7
1
2

Max

Unit
ns
ns

tSCLK0 × WIDTH + 1.5

ns

The minimum pulse width applies for timer signals in width capture and external clock modes.
WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 2 to 232 – 1).

Table 53. Timer Cycle Timing—External Mode
Parameter
Min
Timing RequirementstWL
Timer Pulse Width Input Low (Measured In EXT_CLK Cycles)1 2 × tEXT_CLKtWH
Timer Pulse Width Input High (Measured In EXT_CLK Cycles)1 2 × tEXT_CLKtEXT_CLK
Timer External Clock Period2
tTMRCLKEXT
Switching CharacteristictHTO
Timer Pulse Width Output (Measured In EXT_CLK Cycles)3
tEXT_CLK × WIDTH – 1.5
1

Max

Unit
ns
ns
ns

tEXT_CLK × WIDTH + 1.5

ns

The minimum pulse width applies for timer signals in width capture and external clock modes.
2This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external TMR_CLK. For the external
TMR_CLK maximum frequency, see the fTMRCLKEXT specification in Table 19.
3
WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 1 to 232 – 1).

Rev. D | Page 76 of 102 | June 2023

ADSP-21562/21563/21565/21566/21567/21569
TMR OUTPUTtHTO
TMR INPUT

tWH, tWL

Figure 31. Timer Cycle Timing

DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block)
Table 54 and Figure 32 describe I/O timing related to the digital audio interface (DAI) for direct pin connections only (for example,
DAIx_PB01_I to DAIx_PB02_O).
Table 54. DAI Pin to DAI Pin Routing
Parameter
Switching CharacteristictDPIO
Delay DAI Pin Input Valid to DAI Output Valid

Min

Max

Unit

1.5

12

ns

DAIx_PINntDPIO

DAIx_PINm

Figure 32. DAI Pin to DAI Pin Direct Routing

Up/Down Counter/Rotary Encoder Timing
Table 55 and Figure 33 describe timing related to the general-purpose counter (CNT).
Table 55. Up/Down Counter/Rotary Encoder Timing
Parameter

Min

Max

Unit

Timing Requirement
tWCOUNT

Up/Down Counter/Rotary Encoder Input Pulse Width

2 × tSCLK0

CNT0_UD
CNT0_DG
CNT0_ZMtWCOUNT

Figure 33. Up/Down Counter/Rotary Encoder Timing

Rev. D | Page 77 of 102 |June 2023

ns

ADSP-21562/21563/21565/21566/21567/21569
Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
The UART ports receive and transmit operations are described in the ADSP-21562/3/5/6/7/9 SHARC+ Processor Hardware Reference.

Sony/Philips Digital Interface (S/PDIF) Transmitter
Serial data input to the S/PDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16, 18, 20, or 24 bits.
The following sections provide timing for the transmitter.
S/PDIF Transmitter Serial Input Waveforms
Table 56 and Figure 34 show the right justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on
the rising edge of the serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from aframe sync transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is right justified to the next
frame sync transition.
Table 56. S/PDIF Transmitter Right Justified Mode
Parameter
Timing RequirementtRJD
Frame Sync to MSB Delay in Right Justified Mode

Conditions

NominalUnit

16-bit word mode
18-bit word mode
20-bit word mode
24-bit word mode

16
14
12
8

SCLK0
SCLK0
SCLK0
SCLK0

LEFT/RIGHT CHANNELDAI_P20–1
FS

DAI_P20–1
SCLK0

tRJD
DAI_P20–1
SDATA

LSB

MSB

MSB–1

MSB–2

Figure 34. Right Justified ModeRev. D | Page 78 of 102 | June 2023

LSB+2

LSB+1

LSB

ADSP-21562/21563/21565/21566/21567/21569
Table 57 and Figure 35 show the default I2S justified mode. The frame sync is low for the left channel and high for the right channel. Datais valid on the rising edge of the serial clock. The MSB is left justified to the frame sync transition but with a delay.
Table 57. S/PDIF Transmitter I2S Mode
Parameter
Timing Requirement
tI2SD

Frame Sync to MSB Delay in I2S Mode

Nominal

Unit

1

SCLK0

LEFT/RIGHT CHANNELDAI_P20–1(FS)

DAI_P20–1(SCLK0)tI2SD
DAI_P20–1(SDATA)

MSB

MSB–1

MSB–2

LSB+2

LSB+1

LSB

Figure 35. I2S Justified Mode

Table 58 and Figure 36 show the left justified mode. The frame sync is high for the left channel and low for the right channel. Data is valid
on the rising edge of the serial clock. The MSB is left justified to the frame sync transition with no delay.
Table 58. S/PDIF Transmitter Left Justified Mode
Parameter
Timing Requirement
tLJD

Frame Sync to MSB Delay in Left Justified Mode

DAI_P20–1(FS)

LEFT/RIGHT CHANNELDAI_P20–1(SCLK0)tLJD
DAI_P20–1(SDATA)

MSB

MSB–1

MSB–2

LSB+2

LSB+1

Figure 36. Left Justified ModeRev. D | Page 79 of 102 |June 2023

LSB

Nominal

Unit

0

SCLK0

ADSP-21562/21563/21565/21566/21567/21569
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given in Table 59. Input signals are routed to the DAI0_PINx pins using the SRU.
Therefore, the timing specifications provided below are valid at the DAI0_PINx pins.
Table 59. S/PDIF Transmitter Input Data Timing
Parameter

Min

Max

Unit

Timing Requirements
tSISFS1

Frame Sync Setup Before Serial Clock Rising Edge

3.4

ns

tSIHFS

Frame Sync Hold After Serial Clock Rising Edge

3

ns

tSISD1

Data Setup Before Serial Clock Rising Edge

3

ns

1

tSIHD

1

1

Data Hold After Serial Clock Rising Edge

3

ns

tSITXCLKW

Transmit Clock Width

9

nstSITXCLK

Transmit Clock Period

20

nstSISCLKW

Clock Width

36

ns

tSISCLK

Clock Period80ns

The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The input of the
PCG can be either CLKIN or any of the DAI pins.

SAMPLE EDGEtSITXCLKWtSITXCLK

DAI0_PIN20–1(TxCLK)tSISCLKtSISCLKWDAI0_PIN20–1(SCLK0)tSISFStSIHFS

DAI0_PIN20–1
(FS)

tSISD

tSIHD

DAI0_PIN20–1(SDATA)

Figure 37. S/PDIF Transmitter Input Timing

Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter requires an oversampling clock input. This high frequency clock (TxCLK) input is divided down to generate theinternal biphase clock.
Table 60. Oversampling Clock (TxCLK) Switching Characteristics
Parameter
Switching Characteristics
fTXCLK_384
Frequency for TxCLK = 384 × Frame Sync
fTXCLK_256
Frequency for TxCLK = 256 × Frame Sync
fFS
Frame Rate (FS)

Max

Unit

Oversampling ratio × frame sync ≤ 1/tSITXCLK
49.2
192.0

MHz
MHz
kHz

Rev. D | Page 80 of 102 | June 2023

ADSP-21562/21563/21565/21566/21567/21569
S/PDIF Receiver
The following section describes timing as it relates to the S/PDIF receiver.
Internal Digital PLL ModeIn the internal digital PLL mode, the internal digital PLL generates the 512 × FS clock.
Table 61. S/PDIF Receiver Internal Digital PLL Mode Timing
Parameter

Min

Max

Unit

5

ns

5

ns

Switching Characteristics
tDFSI

Frame Sync Delay After Serial ClocktHOFSI

Frame Sync Hold After Serial ClocktDDTI

Transmit Data Delay After Serial ClocktHDTITransmit Data Hold After Serial Clock

DRIVE EDGE

–2
–2

SAMPLE EDGE

DAI0_PIN20–1(SCLK0)tDFSItHOFSI
DAI0_PIN20–1
(FS)

tDDTI
tHDTI
DAI0_PIN20–1(DATA CHANNEL A/B)

Figure 38. S/PDIF Receiver Internal Digital PLL Mode Timing

Rev. D | Page 81 of 102 |June 2023

ns
ns

ADSP-21562/21563/21565/21566/21567/21569
MediaLB (MLB)All the numbers shown in Table 62 are applicable for all MLB speed modes (1024 FS, 512 FS, and 256 FS) for the 3-pin protocol, unlessotherwise specified. Refer to the Media Local Bus Specification Version 4.2 for more details.
Table 62. 3-Pin MLB Interface Specifications
ParametertMLBCLK

tMCKL

tMCKH

tMCKR

tMCKF

tMPWV1tDSMCFtDHMCF
tMCFDZtMCDRVtMDZH2

CMLB

1
2

Min
MLB Clock Period
1024 FS
512 FS
256 FSMLBCLK Low Time1024 FS
512 FS
256 FSMLBCLK High Time1024 FS
512 FS
256 FSMLBCLK Rise Time (VIL to VIH)
1024 FS
512 FS/256 FS
MLBCLK Fall Time (VIH to VIL)
1024 FS
512 FS/256 FS
MLBCLK Pulse Width Variation
1024 FS
512 FS/256
DAT/SIG Input Setup Time
DAT/SIG Input Hold Time
DAT/SIG Output Time to Three-State
DAT/SIG Output Data Delay From MLBCLK Rising EdgeBus Hold Time1024 FS
512 FS/256
DAT/SIG Pin Load
1024 FS
512 FS/256

Typ

Max

20.3
40
81

Unit
ns
ns
ns

6.1
14
30

ns
ns
ns

9.3
14
30

ns
ns
ns

1
2
0

1
3

ns
ns

1
3

ns
ns

0.7
2.0

nspp
nspp

15
8

ns
ns
ns
ns

2
4

ns
ns
40
60

pf
pf

Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in nanoseconds peak-to-peak.
Board designs must ensure the high impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while
meeting the maximum capacitive load listed.

Rev. D | Page 82 of 102 | June 2023

ADSP-21562/21563/21565/21566/21567/21569
MLB_SIG/
MLB_DAT(Rx, Input)

VALID

tDHMCFtDSMCFtMCKH

MLB_CLK

tMCKR

tMCKL

tMCKF
tMLBCLKtMCDRVtMCFDZtMDZHMLB_SIG/
MLB_DAT(Tx, Output)

VALID

Figure 39. MLB Timing (3-Pin Interface)

Rev. D | Page 83 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
Program Trace Macrocell (PTM) Timing
Table 63 and Figure 40 provide I/O timing related to the PTM.
Table 63. TRACE0 Timing
Parameter

Min

Max

Unit

Switching Characteristics
tDTRD

TRACE0 Data Delay From Trace Clock MaximumtHTRD

TRACE0 Data Hold From Trace Clock Minimum

0.5 × tSCLK0 – 2

0.5 × tSCLK0 + 3

ns

tPTRCK

TRACE0 Clock Period Minimum

2 × tSCLK0 – 1

ns

tPTRCK

TRACE0_CLK
tHTRD

D0

TRACE0_DX

tDTRD

tHTRD
D1

tDTRD

Figure 40. Trace Timing

Rev. D | Page 84 of 102 | June 2023

ns

ADSP-21562/21563/21565/21566/21567/21569
Debug Interface (JTAG Emulation Port) Timing
Table 64 and Figure 41 provide I/O timing related to the debug interface (JTAG emulator port).
Table 64. JTAG Emulation Port Timing
Parameter

Min

Max

Unit

Timing RequirementstTCK

JTG_TCK Period

20

ns

tSTAP

JTG_TDI, JTG_TMS Setup Before JTG_TCK High

4

ns

tHTAP

JTG_TDI, JTG_TMS Hold After JTG_TCK High

4

ns

tSSYS

System Inputs Setup Before JTG_TCK High1

4

ns

tHSYS

System Inputs Hold After JTG_TCK High1

4

ns

4

TCK

2

JTG_TRST Pulse Width (Measured in JTG_TCK Cycles)tTRSTW

Switching Characteristics
tDTDO

JTG_TDO Delay From JTG_TCK Low

12

ns

tDSYS

System Outputs Delay After JTG_TCK Low3

17

ns

1

System Inputs = DAI0_PIN20-19, DAI0_PIN12-1, DAI1_PIN20-19, DAI1_PIN12-1, DMC0_A15-0, DMC0_DQ15-0, DMC0_RESET, PA_15-0, PB_15-0, PC_7-0,
SYS_BMODE2-0, SYS_FAULT.
2
50 MHz maximum.
3
System Outputs = DMC0_A15-0, DMC0_BA2-0, DMC0_CAS, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQ15-0, DMC0_LDM, DMC0_LDQS, DMC0_ODT,DMC0_RAS, DMC0_RESET, DMC0_UDM, DMC0_UDQS, DMC0_WE, PA_15-0, PB_15-0, PC_7-0, SYS_CLKOUT, SYS_FAULT, SYS_RESOUT.

tTCK
JTG_TCK

tSTAP

tHTAP

tSSYS

tHSYS

JTG_TMS
JTG_TDItDTDO
JTG_TDOSYSTEM
INPUTStDSYS
SYSTEMOUTPUTS

Figure 41. JTAG Port Timing

Rev. D | Page 85 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
OUTPUT DRIVE CURRENTS

2050
VDD = 3.47V AT –40°C
VDD = 3.30V AT +25°C
VDD = 3.13V AT +125°C

40

SOURCE CURRENT (mA)30
VOH

VDD = 1.575V AT –40°C
VDD = 1.500V AT +25°C
VDD = 1.425V AT +125°C

18
16
SOURCE CURRENT (mA)

Figure 42 through Figure 47 show typical current voltage characteristics for the output drivers of the ADSP-2156x processors.
The curves represent the current drive capability of the output
drivers as a function of output voltage.

20

VOH

14
12
10
8
6
4

10

2

0

0

VOL

–10

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

SOURCE VOLTAGE (V)–20

Figure 44. Driver Type B and Driver Type C (DDR3 Drive Strength 100 Ω)

–30
–40

0
–50
0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

VDD = 1.575V AT –40°C
VDD = 1.500V AT +25°C
VDD = 1.425V AT +125°C–2
SOURCE CURRENT (mA)

SOURCE VOLTAGE (V)Figure 42. Driver Type A Current for All Pins Operating
at Less Than or Equal to 62.5 MHz (3.3 V VDD_EXT)50
VDD = 3.47V AT –40°C
VDD = 3.30V AT +25°C
VDD = 3.13V AT +125°C

40
VOH

VOL
–6
–8
–10
–12

20
–14
10
–16

0

0

0.2

0.4

VOL

–10

0.6

0.8

1.0

1.2

1.4

1.6

1.8

SOURCE VOLTAGE (V)Figure 45. Driver Type B and Driver Type C (DDR3 Drive Strength 100 Ω)

–20
–30

18

–40

VDD = 1.418V AT –40°C
VDD = 1.350V AT +25°C
VDD = 1.285V AT +125°C

16

–50
0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

SOURCE VOLTAGE (V)Figure 43. Driver Type A Current for All Pins Operating Above62.5 MHz and Less Than or Equal to125 MHz (3.3 V VDD_EXT)

14
SOURCE CURRENT (mA)

SOURCE CURRENT (mA)

30

–4

VOH
12
10
8
6
4
2
0
0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

SOURCE VOLTAGE (V)Figure 46. Driver Type B and Driver Type C (DDR3L Drive Strength100 Ω)

Rev. D |Page 86 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
0

SOURCE CURRENT (mA)

REFERENCE
SIGNALVDD = 1.418V AT –40°C
VDD = 1.350V AT +25°C
VDD = 1.285V AT +125°C

–2
–4

tDIS

tENA

VOL

–6
–8
–10
–12

OUTPUT STOPS DRIVING–14

OUTPUT STARTS DRIVINGHIGH IMPEDANCE STATE

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

Figure 49. Output Enable/Disable

SOURCE VOLTAGE (V)Figure 47. Driver Type B and Driver Type C (DDR3L Drive Strength 100 Ω)

TEST CONDITIONS
All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 48
shows the measurement point for ac measurements (except output enable/disable). The measurement point, VMEAS, isVDD_EXT/2 for VDD_EXT (nominal) = 3.3 V.

INPUT
OR
OUTPUT

VMEAS

Output Disable Time Measurement
Output pins are considered disabled when they stop driving,
enter a high impedance state, and start to decay from the output
high or low voltage. The output disable time, tDIS, is the intervalfrom when a reference signal reaches a high or low voltage levelto the point when the output stops driving, as shown on the left
side of Figure 49).

Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 50). VLOAD is equal
to VDD_EXT/2. Figure 51 through Figure 54 show how output
rise time varies with capacitance. The delay and hold specifications given must be derated by a factor derived from thesefigures. The graphs in Figure 51 through Figure 54 cannot belinear outside the ranges shown.

VMEAS

Figure 48. Voltage Reference Levels for AC Measurements(Except Output Enable/Disable)

TESTER PIN ELECTRONICS

Output Enable Time Measurement

50:
VLOAD

Output pins are considered enabled when they make a transition from a high impedance state to the point when they startdriving.

T1
45:

DUT
OUTPUT70:

The output enable time, tENA, is the interval from the point
when a reference signal reaches a high or low voltage level to thepoint when the output starts driving, as shown on the right sideof Figure 49. If multiple pins are enabled, the measurement
value is that of the first pin to start driving.

ZO = 50:(impedance)
TD = 4.04 r 1.18 ns

50:
0.5pF

4pF

2pF
400:

NOTES:THE WORST-CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USEDFOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVENSYSTEM REQUIREMENT. IF NECESSARY, THE SYSTEM CAN INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

Figure 50. Equivalent Device Loading for AC Measurements(Includes All Fixtures)Rev. D |Page 87 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
6

4

tRISE = 1.35V AT +25°C
tFALL = 1.35V AT +25°C
tRISE = 1.283V AT +125°C
tFALL = 1.283V AT +125°C
tRISE = 1.418V AT –40°C
tFALL = 1.418V AT –40°C

1.0
RISE AND FALL TIMES (ns)5
RISE AND FALL TIMES (ns)

1.2

tRISE = 3.3V AT +25°C
tFALL = 3.3V AT +25°C
tRISE = 3.135V AT +125°C
tFALL = 3.135V AT +125°C
tRISE = 3.465V AT –40°C
tFALL = 3.465V AT –40°C

3

2

1

0.8

0.6

0.4

0.2

0
0

5

10

15

20

25

0

30

0

1

2

3

4

5

6

LOAD CAPACITANCE (pF)

LOAD CAPACITANCE (pF)

Figure 51. Driver Type A Rise and Fall Times (10% to 90%) vs. Load
Capacitance for All Pins Operating Above 62.5 MHz andLess Than or Equal to 125 MHz

Figure 54. Driver Type B and Driver Type C Rise and Fall Times(10% to 90%) vs. Load Capacitance for DDR3L at 100 Ω

ENVIRONMENTAL CONDITIONS
8RISE AND FALL TIMES (ns)

The ADSP-2156x processors are rated for performance over thetemperature range specified in Operating Conditions.

tRISE = 3.3V AT +25°C
tFALL = 3.3V AT +25°C
tRISE = 3.135V AT +125°C
tFALL = 3.135V AT +125°C
tRISE = 3.465V AT –40°C
tFALL = 3.465V AT –40°C

7
6Application system thermal simulation is required for accurate
temperature analysis. The thermal simulation must account for
all specific 3D system design features, including, but not limited
to other heat sources, use of heat sinks, use of thermal interface
materials, and the system enclosure details. Thermal models of
the package are available from Analog Devices under the Tools
and Simulations tab of the product web page. The thermal
model(s) are compatible with all major thermal simulation
tools.

5
4
3
2
1
0
0

5

10

15

20

25

30

LOAD CAPACITANCE (pF)

Figure 52. Driver Type A Rise and Fall Times (10% to 90%) vs. Load
Capacitance for All Pins Operating at Less Than or Equal to 62.5 MHz
1.2“This methodology is not meant to and will not predict theperformance of a package in an application-specificenvironment.”tRISE = 1.5V AT +25°C
tFALL = 1.5V AT +25°C
tRISE = 1.425V AT +125°C
tFALL = 1.425V AT +125°C
tRISE = 1.575V AT –40°C
tFALL = 1.575V AT –40°C

1.0
RISE AND FALL TIMES (ns)The use of JEDEC JA, JC, or JT thermal parameters forapplication system thermal estimates is not recommended asindicated in the JEDEC51 specifications:

0.8

0.6

0.4

0.2

0
0

1

2

3

4

5

6

LOAD CAPACITANCE (pF)

Figure 53. Driver Type B and Driver Type C Typical Rise and Fall Times(10% to 90%) vs. Load Capacitance for DDR3 at 100 ΩRev. D |Page 88 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
ADSP-2156x 400-BALL BGA BALL ASSIGNMENTS
The ADSP-2156x 400-Ball BGA Ball Assignments (Numericalby Ball Number) table lists the 400-ball BGA package by ballnumber.

The ADSP-2156x 400-Ball BGA Ball Assignments (Alphabeticalby Pin Name) table lists the 400-ball BGA package by pin name.

ADSP-2156x 400-BALL BGA BALL ASSIGNMENTS (NUMERICAL BY BALL NUMBER)
Ball No.
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20

Pin Name
GND
DMC0_DQ11
DMC0_DQ10
DMC0_UDQS
DMC0_DQ15
DMC0_UDM
PB_00
SYS_BMODE2
SYS_HWRST
JTG_TRSTSYS_FAULTDMC0_WE
DMC0_A14
DMC0_A13
DMC0_A10
DMC0_A08
DMC0_BA1
DMC0_A07
DMC0_A04
GND
GND
GND
DMC0_DQ12
DMC0_UDQS
DMC0_DQ14
DMC0_DQ13
PB_04
PB_02
SYS_BMODE1
SYS_BMODE0
JTG_TCK
DMC0_RESET
DMC0_A15
DMC0_A12
DMC0_A11
DMC0_A09
DMC0_BA0DMC0_A06
GND
DMC0_A05

Ball No.
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20

Pin Name
DMC0_LDM
DMC0_DQ08
GND
GND
GND
GND
PB_03
PB_05
PB_01
SYS_RESOUTJTG_TDO
JTG_TMS
JTG_TDI
GND
GND
GND
GND
GND
DMC0_A03
DMC0_A02
DMC0_DQ07
GND
DMC0_DQ09
GND
GND
GND
GND
VDD_EXTVDD_EXTVDD_EXTVDD_EXT
GND
GND
GND
GND
GND
GND
GND
DMC0_A00
DMC0_A01

Ball No.
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20

Rev. D | Page 89 of 102 |Pin Name
DMC0_DQ05
DMC0_DQ06
GND
VDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTGND
DMC0_BA2
DMC0_CAS
DMC0_LDQS
DMC0_LDQS
GND
VDD_INTVDD_INTVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_INTVDD_INTGND
DMC0_RAS
DMC0_CS0

June 2023

Ball No.
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20

Pin Name
DMC0_DQ04
DMC0_DQ02
GND
VDD_INTVDD_INTVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_REFVDD_REFVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_INTVDD_INTGND
DMC0_RZQDMC0_VREF
DMC0_DQ03
GND
GND
VDD_INTVDD_INTVDD_DMCVDD_DMC
GND
GND
GND
GND
GND
GND
VDD_DMCVDD_DMCVDD_INTVDD_INTGND
DMC0_ODTDMC0_CKEADSP-21562/21563/21565/21566/21567/21569
Ball No.
J01
J02
J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
L01
L02
L03
L04
L05
L06
L07
L08

Pin Name
DMC0_DQ01
DMC0_DQ00
GND
DMC0_VREF
VDD_INTVDD_DMCVDD_DMC
GND
GND
GND
GND
GND
GND
VDD_INTVDD_INTVDD_INTVDD_INTGND
DMC0_CK
DMC0_CK
GND
GND
GND
VDD_EXTVDD_INTVDD_INTVDD_DMC
GND
GND
GND
GND
GND
GND
VDD_INTVDD_INTVDD_INT
GND
GND
GND
GND
SYS_XTAL0
GND
GND
VDD_EXTVDD_INTVDD_INTVDD_INT
GND

Ball No.
L09
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
N16

Pin Name
GND
GND
GND
GND
GND
VDD_INTVDD_INTGND
GND
HADC0_VREFNVDD_ANA
HADC0_VREFP
GND
GND
SYS_CLKOUT
VDD_EXTVDD_INTVDD_INTVDD_INT
GND
GND
GND
GND
GND
GND
VDD_INTVDD_REFVDD_EXTGND
GND
HADC0_VIN2
HADC0_VIN3
SYS_CLKIN0
GND
PA_00
VDD_EXTVDD_REFVDD_INTVDD_INT
GND
GND
GND
GND
GND
GND
VDD_INTVDD_REFVDD_EXT

Ball No.
N17
N18
N19
N20
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
T01
T02
T03
T04

Pin Name
GND
GND
HADC0_VIN0
HADC0_VIN1
GND
PA_02
PA_01
VDD_EXTVDD_REFVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_REFVDD_EXTGND
DAI1_PIN02
GND
GND
PA_04
GND
PA_03
VDD_EXTVDD_REFVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_REFVDD_EXTGND
DAI1_PIN03
DAI1_PIN08
DAI1_PIN01
GND
PA_05
PA_06
GND

Rev. D | Page 90 of 102 | June 2023

Ball No.
T05
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12

Pin Name
VDD_EXTVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_EXTGND
DAI1_PIN09
DAI1_PIN06
DAI1_PIN04
GND
PA_10
PA_08
GND
GND
VDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTGND
GND
DAI1_PIN10
DAI1_PIN07
DAI1_PIN05
PA_07
PA_09
GND
GND
PB_06
PB_09
PB_12
PA_11
DAI0_PIN02
DAI0_PIN06
DAI0_PIN09
DAI0_PIN20ADSP-21562/21563/21565/21566/21567/21569
Ball No.
V13
V14
V15
V16
V17
V18
V19
V20
W01
W02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20

Pin Name
PC_00
PC_05
GND
GND
DAI1_PIN19
GND
DAI1_PIN11
DAI1_PIN12
GND
GND
PB_08
PB_07
PB_13
PA_12
PA_14
PA_15
DAI0_PIN03
DAI0_PIN05
DAI0_PIN08
DAI0_PIN12
DAI0_PIN19
PB_15
PC_01
PC_03
PC_06
DAI1_PIN20
GND
GND
GND
GND
PB_10
PB_11
GND
PA_13
GND
DAI0_PIN01
DAI0_PIN04
DAI0_PIN07
DAI0_PIN10
DAI0_PIN11
GND
PB_14
PC_02
GND
PC_04
PC_07
GND
GND
Rev. D | Page 91 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
ADSP-2156x 400-BALL BGA BALL ASSIGNMENTS (ALPHABETICAL BY PIN NAME)
Pin Name
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0DMC0_BA1

Ball No.
Y08
V09
W09
Y09
W10
V10
Y10
W11
V11
Y11
Y12
W12
W13
V12
R20
P18
R18
T20
U20
T19
U19
R19
T18
U18
V19
V20
V17
W18
D19
D20
C20
C19
A19
B20
B18
A18
A16
B16
A15
B15
B14
A14
A13
B13
B17
A17

Pin Name
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CK
DMC0_CKE
DMC0_CS0DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODTDMC0_RAS
DMC0_RESET
DMC0_RZQDMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_VREF
DMC0_VREF
DMC0_WE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

Ball No.
E19
E20
J19
J20
H20
F20
J02
J01
G02
H01
G01
E01
E02
D01
C02
D03
A03
A02
B03
B06
B05
A05
C01
F01
F02
H19
F19
B12
G19
A06
A04
B04
G20
J04
A12
A01
A20
B01
B02
B19
C03
C04
C05
C06
C14
C15

Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

Rev. D | Page 92 of 102 | June 2023

Ball No.
C16
C17
C18
D02
D04
D05
D06
D07
D12
D13
D14
D15
D16
D17
D18
E03
E18
F03
F18
G03
G18
H02
H03
H08
H09
H10
H11
H12
H13
H18
J03
J08
J09
J10
J11
J12
J13
J18
K01
K02
K03
K08
K09
K10
K11
K12

Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

Ball No.
K13
K17
K18
K19
K20
L02
L03
L08
L09
L10
L11
L12
L13
L16
L17
M01
M02
M08
M09
M10
M11
M12
M13
M17
M18
N02
N08
N09
N10
N11
N12
N13
N17
N18
P01
P17
P19
P20
R02
R17
T01
T04
T17
U01
U04
U05

ADSP-21562/21563/21565/21566/21567/21569
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VREFN
HADC0_VREFPJTG_TCKJTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
PB_00
PB_01

Ball No.
U16
U17
V03
V04
V15
V16
V18
W01
W02
W19
W20
Y01
Y02
Y05
Y07
Y13
Y16
Y19
Y20
N19
N20
M19
M20
L18
L20
B11
C13
C11
C12
A10
N03
P03
P02
R03
R01
T02
T03
V01
U03
V02
U02
V08
W06
Y06
W07
W08
A07
C09

Pin Name
PB_02
PB_03
PB_04
PB_05
PB_06
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0SYS_CLKOUT
SYS_FAULTSYS_HWRST
SYS_RESOUTSYS_XTAL0
VDD_ANAVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMC

Ball No.
B08
C07
B07
C08
V05
W04
W03
V06
Y03
Y04
V07
W05
Y14
W14
V13
W15
Y15
W16
Y17
V14
W17
Y18
B10
B09
A08
N01
M03
A11
A09
C10
L01
L19
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
G06
G07
G08
G09
G12
G13

Pin Name
VDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_DMCVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INT

Rev. D | Page 93 of 102 |June 2023

Ball No.
G14
G15
H06
H07
H14
H15
J06
J07
K07
D08
D09
D10
D11
K04
L04
M04
M16
N04
N16
P04
P16
R04
R16
T05
T16
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16

Pin Name
VDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INT

Ball No.
E17
F04
F05
F16
F17
G04
G05
G16
G17
H04
H05
H16
H17
J05
J14
J15
J16
J17
K05
K06
K14
K15
K16
L05
L06
L07
L14
L15
M05
M06
M07
M14
N06
N07
N14
P06
P07
P08
P09
P10
P11
P12
P13
P14
R06
R07
R08
R09

ADSP-21562/21563/21565/21566/21567/21569
Pin Name
VDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REF

Ball No.
R10
R11
R12
R13
R14
G10
G11
M15
N05
N15
P05
P15
R05
R15
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15

Rev. D | Page 94 of 102 | June 2023

ADSP-21562/21563/21565/21566/21567/21569
CONFIGURATION OF THE 400-BALL CSP_BGA
Figure 55 shows an overview of signal placement on the 400-ball CSP_BGA.
TOP VIEW

A1 BALLCORNER

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A
B
C
D
E
F
G

GND

H

I/O SIGNALSJ

VDD_EXTK

VDD_INTL

VDD_DMCM

VDD_REFN

VDD_ANAP

DMC0_VREF

R
T
U
V
W
Y

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

A1 BALLCORNER

1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y

BOTTOM VIEW

Figure 55. 400-Ball CSP_BGA ConfigurationRev. D | Page 95 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
ADSP-2156x 120-LEAD LQFP LEAD ASSIGNMENTS
The ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) table lists the 120-lead LQFP package bylead number.

The ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) table lists the 120-lead LQFP package by pin
name.

ADSP-2156x 120-LEAD LQFP LEAD ASSIGNMENTS (NUMERICAL BY LEAD NUMBER)
Lead No.
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Pin Name
VDD_INTGND
VDD_INTVDD_INTSYS_CLKIN0
SYS_XTAL0VDD_REFVDD_INTGND
SYS_CLKOUT
VDD_REFVDD_EXTVDD_INT
PA_00
PA_01
PA_02
VDD_INT
PA_03
PA_04
PA_05
PA_06
VDD_INTVDD_REFVDD_EXT
PA_07
PA_08
PA_09
PA_10
VDD_INT
GND
GND
VDD_INTVDD_INT
PA_11
PA_12
PA_13
PA_14
VDD_EXTVDD_REF
PA_15

Lead No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

Pin Name
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
VDD_INTVDD_INT
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
VDD_EXTVDD_REF
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN19
DAI0_PIN20
VDD_INTGND
VDD_INTVDD_INTVDD_INTGND
DAI1_PIN20
DAI1_PIN19
DAI1_PIN10
DAI1_PIN09
VDD_REFVDD_EXTVDD_INT
DAI1_PIN08
DAI1_PIN07
DAI1_PIN06
DAI1_PIN05
DAI1_PIN04
DAI1_PIN03
DAI1_PIN02
DAI1_PIN01
VDD_EXTVDD_REFVDD_INT

Lead No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120

Pin Name
HADC0_VIN0
HADC0_VIN1
HADC0_VREFP
HADC0_VREFNVDD_ANA
GND
VDD_INTVDD_INTVDD_INTGND
VDD_INTGND
VDD_INTVDD_INTVDD_INTJTG_TDI
JTG_TCKJTG_TMS
JTG_TDOVDD_REFVDD_EXTSYS_FAULTJTG_TRSTSYS_HWRST
SYS_BMODE0
SYS_BMODE1
SYS_RESOUT
PB_00
PB_01
VDD_INTVDD_EXTVDD_REF
PB_02
PB_03
PB_04
PB_05
VDD_INTVDD_INTVDD_INT
GND

Rev. D | Page 96 of 102 | June 2023

Lead No. Pin Name
1211
GND
1

Pin121 is the GND supply (see Figure 57)
for the processor; this pad must connect
to GND.

ADSP-21562/21563/21565/21566/21567/21569
ADSP-2156x 120-LEAD LQFP LEAD ASSIGNMENTS (ALPHABETICAL BY PIN NAME)
Pin Name
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN19
DAI1_PIN20
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HADC0_VIN0
HADC0_VIN1
HADC0_VREFN
HADC0_VREFPJTG_TCKJTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PA_00
PA_01
PA_02

Lead No.
41
42
43
46
47
48
49
52
53
54
55
56
77
76
75
74
73
72
71
70
66
65
64
63
02
09
30
31
58
62
86
90
92
120
1211
81
82
84
83
97
96
99
98
103
14
15
16

Pin Name
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
SYS_BMODE0
SYS_BMODE1
SYS_CLKIN0SYS_CLKOUT
SYS_FAULTSYS_HWRST
SYS_RESOUTSYS_XTAL0
VDD_ANAVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_EXTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INT

Lead No.
18
19
20
21
25
26
27
28
34
35
36
37
40
108
109
113
114
115
116
105
106
05
10
102
104
107
06
85
12
24
38
50
68
78
101
111
01
03
04
08
13
17
22
29
32
33
44

Pin Name
VDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_INTVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REFVDD_REF
1

Lead No.
45
57
59
60
61
69
80
87
88
89
91
93
94
95
110
117
118
119
07
11
23
39
51
67
79
100
112

Pin121 is the GND supply (see Figure 57)
for the processor; this pad must connect
to GND.

Rev. D | Page 97 of 102 |June 2023

ADSP-21562/21563/21565/21566/21567/21569
CONFIGURATION OF THE 120-LEAD LQFP LEAD CONFIGURATION
Figure 56 shows the top view of the 120-lead LQFP lead configuration and Figure 57 shows the bottom view of the 120-lead LQFP leadconfiguration.

LEAD 120LEAD 91
LEAD 90

LEAD 1LEAD 1
INDICATOR

120-LEAD LQFPTOP VIEWLEAD 30LEAD 61LEAD 31LEAD 60

Figure 56. 120-Lead LQFP Lead Configuration (Top View)

LEAD 120LEAD 91

LEAD 1LEAD 90

120-LEAD LQFP
BOTTOM VIEW

GND PAD(LEAD 121)LEAD 30LEAD 61LEAD 60

LEAD 31

Figure 57. 120-Lead LQFP Lead Configuration (Bottom View)

Rev. D | Page 98 of 102 | June 2023

ADSP-21562/21563/21565/21566/21567/21569
OUTLINE DIMENSIONS
Dimensions in Figure 58 (for the 400-ball BGA) and Figure 59 (for the 120-lead LQFP) are shown in millimeters.

A1 BALL
INDICATOR
AREA

17.10
17.00 SQ
16.90

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

A1 BALLCORNER
1
A
B
C
D
E
F
G
H

15.20 REF
SQ

J
K
L
M
N

0.80
BSC

P
R
T
U
V
W
Y

0.90
REF

TOP VIEW

1.38
1.28
1.19
SEATING
PLANE

DETAIL A
SIDE VIEW

BOTTOM VIEW

0.990
0.940
0.890

DETAIL A
0.390
0.343
0.300
0.50
Ø 0.450.40

COMPLIANT TO JEDEC STANDARDS MO-275-MMAB-1

Figure 58. 400-Ball Chip Scale Package Ball Grid Array [CSP_BGA](BC-400-3)
Dimensions shown in millimeters

Rev. D | Page 99 of 102 |June 2023

COPLANARITY
0.20

ADSP-21562/21563/21565/21566/21567/21569
16.20
16.00 SQ
15.80
0.75
0.60
0.45

1.60
MAX
120

11.60 REF
SQ
91

120

91
90

1

1.00 REFSEATING
PLANE

14.10
14.00 SQ
13.90

90

PIN 1
INDICATOR

1

U-GROOVEPIN 1
INDICATOREXPOSED
PAD

0.10 REF

5.40 REF
SQ

12°
1.45
1.40
1.35

0.20
0.15
0.09
7°
0°

0.15
0.10
0.05

0.08
COPLANARITY

VIEW A

30

61
31

60

TOP VIEW

VIEW A(PINS DOWN)

0.40
BSC
LEAD PITCH

61

30
31

60

BOTTOM VIEW(PINS UP)

0.23
0.18
0.13

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BEE-HD

Figure 59. 120-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP](SW-120-4)
Dimensions shown in millimeters

SURFACE-MOUNT DESIGN
Table 65 is provided as an aid to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for
Surface-Mount Design and Land Pattern Standard.
Table 65. CSP_BGA Data for Use with Surface-Mount Design
PackageBC-400-3

Package Ball Attach Type
Solder Mask Defined

Package Solder Mask Opening
0.4 mm Diameter

Rev. D | Page 100 of 102 |June 2023

Package Ball Pad Size
0.5 mm DiameterADSP-21562/21563/21565/21566/21567/21569
AUTOMOTIVE PRODUCTS
The following models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the nonautomotive models; therefore designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown in Table 66 are available
for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering informationand to obtain the specific Automotive Reliability reports for these models.
Table 66. Automotive Products
Model1, 2
ADSP-21562WCSWZ4ADSP-21562WCSWZ4RL
ADSP-21563WCSWZ6ADSP-21563WCSWZ6RL
ADSP-21563WCSWZ8ADSP-21563WCSWZ8RL
ADSP-21565WCSWZ8ADSP-21565WCSWZ8RL
ADSP-21565WCSWZ10ADSP21565WCSWZ10RL
ADSP-21566WCBCZ4
ADSP-21566WCBCZ4RL
ADSP-21567WCBCZ6
ADSP-21567WCBCZ6RLADSP-21567WCBCZ8ADSP-21567WCBCZ8RLADSP-21569WCBCZ8ADSP-21569WCBCZ8RLADSP-21569WCBCZ10ADSP21569WCBCZ10RL

Processor Instruction
Rate (Max)400 MHz
400 MHz
600 MHz
600 MHz
800 MHz
800 MHz
800 MHz
800 MHz
1000 MHz
1000 MHz
400 MHz
400 MHz
600 MHz
600 MHz
800 MHz
800 MHz
800 MHz
800 MHz
1000 MHz
1000 MHz

Temperature
Range3–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C–40°C to +125°C

External
Memory Port
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1

1

Package Description
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA

Z =RoHS compliant part.
RL = Supplied on Tape and Reel.
3
Referenced temperature is junction temperature. See Operating Conditions for junction temperature (TJ) specification.
2

Rev. D | Page 101 of 102 |June 2023

Package
OptionSW-120-4
SW-120-4
SW-120-4
SW-120-4
SW-120-4
SW-120-4
SW-120-4
SW-120-4
SW-120-4
SW-120-4
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3

ADSP-21562/21563/21565/21566/21567/21569
ORDERING GUIDE
Model1ADSP-21562BSWZ4ADSP-21562KSWZ4ADSP-21563BSWZ8ADSP-21563KSWZ8ADSP-21565BSWZ8ADSP-21565BSWZ10ADSP-21565KSWZ8ADSP-21565KSWZ10ADSP-21566BBCZ4ADSP-21566KBCZ4ADSP-21567BBCZ6ADSP-21567BBCZ8ADSP-21567KBCZ6ADSP-21567KBCZ8ADSP-21569BBCZ8ADSP-21569BBCZ10ADSP-21569KBCZ8ADSP-21569KBCZ10
1
2

Processor Instruction
Rate (Max)400 MHz
400 MHz
800 MHz
800 MHz
800 MHz
1000 MHz
800 MHz
1000 MHz
400 MHz
400 MHz
600 MHz
800 MHz
600 MHz
800 MHz
800 MHz
1000 MHz
800 MHz
1000 MHz

Temperature
Range2–40°C to +125°C
0°C to +110°C–40°C to +125°C
0°C to +110°C–40°C to +125°C–40°C to +125°C
0°C to +110°C
0°C to +110°C–40°C to +125°C
0°C to +110°C–40°C to +125°C–40°C to +125°C
0°C to +110°C
0°C to +110°C–40°C to +125°C–40°C to +125°C
0°C to +110°C
0°C to +110°C

External
Memory Port
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1

Package Description
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
120-Lead LQFP_EP, Exposed Pad
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA
Pad 400-Ball CSP_BGA

Z =RoHS compliant part.
Referenced temperature is junction temperature. See Operating Conditions for junction temperature (TJ) specification.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2023 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.
D21778-6/23(D)Rev. D|

Page 102 of 102 | June 2023

Package
OptionSW-120-4
SW-120-4
SW-120-4
SW-120-4
SW-120-4
SW-120-4
SW-120-4
SW-120-4
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3
BC-400-3