REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVED

Prepared in accordance with ASME Y14.24

Vendor Item Drawing

Revision Status of Sheets
REV
SHEET
REV
SHEET

1

PMIC N/A
Original date ofdrawing
YY-MM-DD

24-02-27

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PREPARED BY
Taysa T. Markus

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DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

https://www.dla.mil/landandmaritime
CHECKED BY
Taysa T. Markus
APPROVED BY
Muhammad A. Akbar
SIZE

CAGE CODE

A
REV

16236

TITLE

MICROCIRCUIT, LINEAR, BiCMOS, RADIATIONTOLERANT 1.5 V TO 7 V, 6 A CONTINUOUS
SWITCH CURRENT eFUSE, MONOLITHIC SILICONDWG NO.

V62/23608
PAGE

AMSC N/A

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

1 OF 205962-V105-23

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance radiation-tolerant 1.5 V to 7 V, 6 A maximum
continuous switch current eFuse microcircuit, with an operating temperature range of -55C to +125C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:

V62/23608-

Drawing
number01

X

E

Device type
(See 1.2.1)

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic

Circuit function

01

TPS7H2201-SEP

Radiation hardness assurance (RHA) 6 A
maximum continuous switch current eFuse

1.2.2 Case outline(s). The case outline(s) are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

X

32

See figure 1

Package style
TSSOP – Thin Shrink Small Outline
Package with thermal pad

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

Material

A
B
C
D
E
F
Z

DLA LAND AND MARITIMECOLUMBUS, OHIO

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy (BGA/CGA)
Other

SIZE
A

CAGE CODE
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PAGE 2

1.3 Absolute maximum ratings.

1/ 2/

Input voltage range (VIN) ........................................................................................... -0.3 V to 7.5 V
Output voltage range (VOUT) .................................................................................... -0.3 V to 7.5 V
Enable and over voltage protection pins (EN, OVP) .................................................. -0.3 V to 7.5 V
Current sense, current limit timer, retry timer, current limit andsoft start pins (CS, ILTIMER, RTIMER, IL, SS) ...................................................... -0.3 V to VIN + 0.3 V
Maximum continuous switch current (I MAX) ................................................................ 9.0 A
Maximum pulsed switch current (t≤5µs) (IPLS) ............................................................ 45 A
Maximum junction temperature range (TJ) ................................................................. -55°C to 150°C
Storage temperature range (TSTG) ............................................................................. -65C to 150C
Electrostatic discharge (ESD) rating:
Human body model (HDM), per ANSI/ESDA/JEDEC JS-001, all pins ................... 4000 V 3/
Charge device model (CDM) per JEDEC JESD22-C101, all pins .......................... 750 V 4/
1.4 Recommended operating conditions.
Input voltage range (VIN) ........................................................................................... 1.5 V to 7.0 V
Maximum input voltage slew rate (SRVIN) .................................................................. 0.01 V/µs
Output voltage range (VOUT) .................................................................................... 0.0 V to 7.0 V 5/
Maximum continuous switch current (IMAX) ................................................................ 6.0 A
Operating junction temperature range (TJ) ................................................................. -55C to +125C 6/
Thermal characteristics: 7/

Package Thermal metric

SymbolCase X

Unit

Thermal resistance, junction-to-ambient

RJA

23.5

C/W

Thermal resistance, junction-to-case (top)RJC(top)

11.2

C/W

Thermal resistance, junction-to-board

RJB

5.4

C/W

Characterization parameter, junction-to-top

JT

0.1

C/W

Characterization parameter, junction-to-board

JB

5.4

C/W

Thermal resistance, junction-to-case (bottom)

RJC(bot)

0.5

C/W

_________
1/

2/
3/
4/
5/
6/

7/

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These arestress ratings only, which do not imply functional operation of the device at these or any other conditions beyond thoseindicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods
may affect device reliability.
All voltage values are with respect to network ground pin.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Manufacturing with less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Manufacturing with less than 250-V CDM is possible with the necessary precautions.
This maximum VOUT voltage is only applicable when the device is disabled (EN = Low). When the device is enabled(EN = High), the maximum VOUT voltage is the input voltage, VIN.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient
temperature may have to be derated. Maximum ambient temperature [T A(max)] is dependent on the maximum operating junction
temperature [TJ(max)], the maximum power dissipation of the device in the application [P D(max)], and the junction-to-ambient
thermal resistance of the part/package in the application (θJA), as given by the equation: TA(max) = TJ(max) – (θJA x PD(max)).
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

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1.5 Radiation Features.
Maximum total ionizing dose (TID) available (dose rate = 50 – 300 rad(Si)/s)............................ 50 krads(Si) 8/
Heavy ion single event phenomenon (SEP):No SEL occurs at effective linear energy transfer (LET) ( see 4.3)........................................ ≤ 48 MeV·cm2/mg 9/
No SEB observe at effective LET (see 4.3) .......................................................................... ≤ 48 MeV·cm2/mg 9/
No SEGR observe at effective LET (see 4.3) ....................................................................... ≤ 48 MeV·cm2/mg 9/_________
8/

9/

Device type 01 supplied to this drawing have been tested total ionizing dose (TID) test at high dose rate (HDR) condition A
per MIL-STD-883, method 1019. The TID test is performed as radiation lot acceptance testing of these devices to TID level
50 krads(Si) as specified herein. For more information on TID test report, please contact the manufacturer.
Heavy ion single event effects (SEE) test was performed using the 15-A MeV cocktail and K500 beam line at TAMU Cyclotron
Institute Radiation Effects Facility. No single event latch-up (SEL) was occurred under Ag ions at Vmax supply voltage andoperating temperature 125°C corresponding to an effective LET of 48 Mev-cm2/mg. For more information on SEE/SEP test
please contact device manufacturer.

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2. APPLICABLE DOCUMENTS
DEPARTMENT OF DEFENSE STANDARDSMIL-STD-883 - Test Method Standard Microcircuits.
(Copies of these documents are available online at https://quicksearch.dla.mil.)
JEDEC Solid State Technology Association
JEDEC PUB 95 –Registered and Standard Outlines for Semiconductor Devices
JEDEC JEP 155 –Recommended ESD Target Levels for HBM/MM Qualification
JEDEC JEP 157 –Recommended ESD-CDM Target Levels
JEDEC JS-001–
Human Body Model Testing of Integrated Circuits
JEDEC JS-002−
Electrostatic Discharge Sensitivity Testing - Charge Device Model (CDM)
JESD22-C101–
Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-WithstandThresholds of Microelectronics Components(Copies of these documents are available online at https://www.jedec.org.)
ASTM INTERNATIONAL (ASTM)
ASTM F1192
Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion
Irradiation of Semiconductor Devices.
(Copies of this document is available online at https://www.astm.org/.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3.
3.5.4 EN signal low time to restart device diagram. The EN signal low time to restart device diagram shall be as shown in figure 4.
3.5.5 Turn-on (tON), turn-off (tOFF) and VOUT fall time (tF) waveforms diagram. The turn-on (tON), turn-off (tOFF) and VOUT fall time(tF) waveforms diagram shall be as shown in figure 5.
3.5.6 OVP assert (tASSERT) and OVP deassert (tDEASSERT) waveforms diagram. The OVP assert (tASSERT) and OVP deassert(tDEASSERT) waveforms diagram shall be as shown in figure 6.
3.5.7 tCSEN waveforms diagram. The tCSEN waveforms diagram shall be as shown in figure 7.
3.5.8 Internal ILTIMER waveforms diagram. The internal ILTIMER waveforms diagram shall be as shown in figure 8.
3.5.9 VOUT current to CS change delay time diagram. The VOUT current to CS change delay time diagram shall be as shown infigure 9.

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PAGE 5TABLE IA. Electrical performance characteristics. 1/
Test

SymbolConditions 2/

Subgroup Device
type

LimitsMin

Power supplies and currents
Internal VIN UVLO voltage,
VINHUVLO
rising

Unit

Max

01

1.32 typicalV

VINLUVLO

01

1.23 typical

V

Internal VIN UVLO
hysteresis

HYSTVIN-UVLO

01

92 typicalmV

Quiescent current

IQ

IOUT = 0 mA,
VIN = EN = 5 V, CS resistor of 20 kΩ to GND

1, 2, 3

01

6.5

mA

VIN to VOUT forward
leakage currentIF

1.5 V≤ VIN ≤ 7 V
EN = VOUT = GND,
measured VOUT current VIN = 1.5 V

1, 2, 3

01

250

µA

Internal VIN UVLO voltage,
falling

VIN off-state supply current

ISD VIN

EN = GND,
IOUT = 0 mA,
measured VIN current

3.27 typical

VIN = 1.8 V

3.35 typical

VIN = 3.3 V

3.62 typical

VIN = 5.0 V

4.11 typical

VIN = 7.0 V

6.82 typical

VIN = 5.0 V

1, 2, 3IRCP

33

VIN = 1.8 V

3After TID = 100 krads,
VIN = 1.8 V, 3.3 V,
and 5 V
Reverse current protection
leakage current

01

VIN = 3.3 V

EN = 0 V, VIN = 0 V to 7 V,
VOUT = 0 V to 7 V for VOUT > VIN

1

mA

3.1

1, 2, 3

01

2.5

mA

1, 2, 3

01

83

µA

01

295 typicalEN = 7 V, VIN = 0 V,
VOUT = 0 V to 7 VSoft startSoft start charge currentISS

1 V on SS pin

Soft start slew rate

SRSS

SS pin floating, COUT = 10 µF

See footnotes at end of table.

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PAGE 6mV/µs

TABLE IA. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions

2/

Subgroup Device
type

Limits

Unit

Min

Max

Enable and undervoltage lockout (EN/UVLO) input
EN/UVLO thresholdvoltage, rising

VIHEN

1, 2, 3

01

0.56

0.65

V

EN/UVLO threshold,voltage, falling

VILEN

1, 2, 3

01

0.47

0.55

V

EN/ULVO hysteresis
voltage

HYSTEN1, 2, 3

01

124

mV

9, 10, 11

01

20

µs

4, 5, 601

75%

1, 2, 301

EN signal low time during
cyclingtLOW

VIN percentage for enable
3/

VINEN

EN pin input leakage
current

IEN

RTIMER = GND, IL = 1 A,
IVOUT = 2 A

See Figure 6

EN = VIN = 5 V

12nAOvervoltage protection (OVP)OVPR threshold voltage,rising

VOVPR

1, 2, 3

01

0.52

0.63

V

OVPF threshold voltage,
falling

VOVPF

1, 2, 3

01

0.50

0.59

V

OVP hysteresis voltage

HYSTOVP

1, 2, 3

01

55

mV

OVP pin input leakage
current

IOVP

1, 2, 3

01

15

nA

9, 10, 11

01

5

ms

1, 2, 301

1.6 V < VIN < 7 V

Current limit and current senseTime for valid CS output
after enable

tCSEN

CSS = 120 nF

Minimum VOUT current forvalid CS output

750

mA

VOUT current change to
CS change delay time

0.5-A rising step, 100 mA/µs, 1.5 V ≤ VIN ≤ 7 V

9, 10, 11

01

74

µs

VOUT current change to
CS change delay time

0.5-A falling step, 100 mA/µs, 1.5 V ≤ VIN ≤ 7 V

9, 10, 11

01

73

µs

CS pin accuracy

0.75 A ≤ IVOUT ≤ 7.5 A

4, 5, 601

10%

CS pin voltage

0.75 A ≤ IVOUT ≤ 7.5 A, no OCP

1, 2, 3

01

VIN
– 0.4

V

IVOUT ≤ 1 A

1, 2, 3

01

IVOUT
+ 0.5
IVOUT
+1
IVOUT
+ 1.5

4, 5, 6

01

-20

20

%

01

22 typicalA

Current limit setting

IIL

1 A < IVOUT ≤ 3 A
IVOUT > 3 A
Programmable current limit
accuracy

1.5 V ≤ VIN ≤ 7 V

Fast trip off current limit

VIN = 5 V, 10 mΩ short in 10 µs-10A

See footnotes at end of table.

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TABLE IA. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions

2/

Subgroup Device
type

Limits

Unit

Min

Max

0.7

1.38

µA

153

Ω

1.38

µA

TimersILTIMER charge current

IILTIMERILTIMER internal pull-downresistance

PDILTIMER

RTIMER charge current

IRTIMERRTIMER internal pull-downresistancePDRTIMER

40 mV on ILTIMER pin

40 mV on RTIMER pin

1, 2, 301

1, 2, 301

1, 2, 301

1, 2, 3

01

153

Ω

0.7

Thermal shutdown
Thermal shutdown

VIN = 5 V01

175 typical°C

Thermal shutdown
hysteresis

VIN = 5 V01

20 typical°C

01

61 typicalµs

Current limit and current sense
Fast trip off off-time

VIN = 5 V, CSS = 2.7 nF

9, 10, 11Internal current limit timer(fast trip off current limit)

VIN = 5 V, IVOUT = 3 A, IL = 6 A,
ILTIMER = VIN, 10-mΩ short in 10 µs

9, 10, 11

15 typicalResistance characteristics
ON-state resistance, lead
length = 2.5 mm

RON

VIN = 7 V, IIL = 7.5 A

VIN = 5 V, IIL = 7.5 A

VIN = 3.3 V, IIL = 7.5 A-55°C

1, 2, 3

01

17

-40°C

16.9 typical

25°C

21

85°C

22.9 typical

125°C

27

-55°C

1, 2, 3

01

18

-40°C

18 typical

25°C

23

85°C

24.8 typical

125°C

29

-55°C

1, 2, 3

-40°C

01

21
20.4 typical

25°C

26

85°C

28.5 typical

125°C

33

See footnotes at end of table.

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PAGE 8mΩ

TABLE IA. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions

2/

Subgroup Device
type

Limits
Min

Unit
Max

Resistance characteristics - Continued
VIN = 1.8 V, IIL = 7.5 A

ON-state resistance, lead
length = 2.5 mm

VIN = 1.5 V, IIL = 7.5 A-55°C

1, 2, 3

01

29

-40°C

28.7 typical

25°C

37

85°C

41 typical

125°C

48

-55°C

1, 2, 3

01

mΩ

36

-40°C

35 typical

25°C

46

85°C

46.2 typical

125°C

59

Switching characteristics: VIN = EN = 5 V, T A = 25°C (unless otherwise noted)
Turn-on timetON

RL = 10 Ω, CL = 10 µF, CSS = 1000 pF

9, 10,1101

208 typicalµs

Turn-off timetOFF

RL = 10 Ω, CL = 10 µF, CSS = 1000 pF

9, 10,1101

60 typicalµs

VOUT fall timetF

RL = 10 Ω, CL = 10 µF, CSS = 1000 pF

9, 10,1101

90 typicalµs

OVP assert timetASSERT

RL = 10 Ω, CL = 10 µF, CSS = 1000 pF

9, 10,1101

4.5 typicalµs

OVP deassert timetDEASSERTRL = 10 Ω, CL = 10 µF, CSS = 1000 pF

9, 10,1101

9.6 typicalµs

Switching characteristics: VIN = EN = 1.5 V, TA = 25°C (unless otherwise noted)
Turn-on timetON

RL = 10 Ω, CL = 10 µF, CSS = 1000 pF

9, 10,1101

173 typicalµs

Turn-off timetOFF

RL = 10 Ω, CL = 10 µF, CSS = 1000 pF

9, 10,1101

64 typicalµs

VOUT fall timetF

RL = 10 Ω, CL = 10 µF, CSS = 1000 pF

9, 10,1101

70 typicalµs

OVP assert timetASSERT

RL = 10 Ω, CL = 10 µF, CSS = 1000 pF

9, 10,1101

2.65 typicalµs

OVP deassert timetDEASSERTRL = 10 Ω, CL = 10 µF, CSS = 1000 pF

9, 10,1101

6.56 typical

µs

1/

2/
3/

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance overthe specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters
may not necessarily be tested. In the absence of specific parametric testing, product performance is assured bycharacterization and/or design.
Over operating free-air temperature range (unless otherwise noted).
VIN must be ≥ 75 % of its final value before EN is asserted only if VINSR > VOUTSR.

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Table IB. SEP test limit. 1/ 2/ 3/
Devicetype

SEP/SEE

Temperature
(TC)

VIN

Effective linear energy transfer
(LET)

01

No SEL

125°C

7V

LETeff ≤ 48 MeV·cm2/mg

No SEB/SEGR

25°C

7V

LETeff ≤ 48 MeV·cm2/mg

1/ For single event phenomena (SEP) test conditions, see 4.3 herein.
2/ Technology characterization and model verification supplemented by in-line data may be usedin lieu of end of line testing. Test plan must be approved by the technical review board andqualifying activity.
3/ Heavy ion single event effects (SEE) test was performed at TAMU Cyclotron Institute Radiation
Effects Facility in accordance with ASTM F1192 or JESD57. No single event latch-up (SEL),
single event burn-out (SEB) and single event gate rupture (SEGR) were observed under 109Ag
ions at Vmax supply voltage (7.0 V), flux of 105 ions/cm2·s, fluences of 107 ions/cm2 corresponding
to an effective LET of 48 Mev·cm2/mg. For more information on SEP test results, customers arerequested to contact the manufacturer.

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PAGE 10Case XFIGURE 1. Case outline.

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PAGE 11Case X - continued

Dimensions
SymbolMillimeters
Minimum

MaximumA

InchesMinimum

1.20

Maximum
0.0472

A1

0.05

0.15

0.00200.0059

b

0.19

0.30

0.00750.0118c0.15 TYP

0.0059 TYP

D

10.90

11.10

0.42910.4370

D1

5.10

6.00

0.20080.2362D2

0.2 TYP

0.0079 TYP

E

7.90

8.30

0.31100.3268

E1

6.00

6.20

0.23620.2441

E2

3.00

3.90

0.11810.1535E30.90 TYP

0.0354 TYP

e0.65 BSC

0.0256 BSC

e1

9.75 BSC

0.3839 BSC

L

0.50

0.75

0.01970.0295NOTES:
1. All linear dimensions are in millimeters, inch dimensions are given for reference only. Any dimensions inparenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs
shall not exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ and may not be present.

FIGURE 1. Case outline - Continued.

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PAGE 12FIGURE 2. Terminal connections.

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Device type

01

Case outline

X

Terminal number Terminal symbol

1/
2/

I/O 1/

Description

1-10

VIN

I

Switch input. Input bypass capacitor recommended for minimizing V IN dip.

11

CS

O

Current sense pin proportional to output current. Connect a resistor to GND.

12

EN

I

Active high switch control input. Do not leave floating.

13

OVP

I

Overvoltage protection. Programmable using an external resistor divider.
If no OVP is desired, this pin should be connected to GND.

14

NC

−

No connect. This pin is not internally connected. It is recommended toconnect these pins to GND to prevent charge buildup; however, these pins
can also be left open or tied to any voltage between GND and VIN.

15

GND

−

Device ground. 2/

16, 17NC−

No connect. This pin is not internally connected. It is recommended toconnect these pins to GND to prevent charge buildup; however, these pins
can also be left open or tied to any voltage between GND and VIN.

18

RTIMER

I/O

Capacitor programmed fault timer control during disable and retry mode.
Connecting this pin to GND holds the switch disable until the EN pin iscycled. Do not float this pin or connect it to VIN.

19

NC

−

No connect. This pin is not internally connected. It is recommended toconnect these pins to GND to prevent charge buildup; however, these pins
can also be left open or tied to any voltage between GND and VIN.

20

IL

I/O

Current limiter control. Programmable using an external resistor to GND.
Do not float this pin

21

ILTIMERI

Capacitor programmed fault timer control during current limiting mode.
Connecting this pin to VIN uses the internal current limit timer and connecting
this pin to GND disables the internal current limit timer and connecting thispin to GND disables the internal timer functionality for the ILTIMER as well as
retry mode. In this case, the device will remain at programmed current limit
indefinitely in the event of a short without going into retry mode. Do not float
this pin.

22

SS

I/O

Switch slew rate control.

23-32

VOUT

O

Switch output. A minimum 10-µF output capacitor is recommended.

−

Thermal pad−

Thermal pad (exposed center pad) for heat dissipation purposes. Thermal
pad is internally connected to seal ring and GND

I = Input, O = Output, I/O = Input or Output, − = Other
Thermal pad is internally connected to the seal ring.

FIGURE 2. Terminal connections – Continued.

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PAGE 14

FIGURE 3. Functional Block diagrams.

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FIGURE 4. EN signal low time to restart device (tLOW).

FIGURE 5. Turn-on (tON), turn-off (tOFF) and VOUT fall time (tF) waveforms.

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FIGURE 6. OVP assert (tASSERT) and OVP deassert (tDEASSERT) waveforms.

FIGURE 7. tCSEN waveforms.

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FIGURE 8. Internal ILTIMER waveforms.

FIGURE 9. VOUT current to CS change delay time.

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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices ,classification, packaging, and labeling of moisture sensitive devices, as applicable.
4.2 Total dose irradiation testing. Total ionizing dose irradiation testing shall be performed in accordance with MIL-STD-883 method
1019, condition A for device type 01 and as specified in 1.5 herein.
4.3 Single event phenomena (SEP). SEP testing was performed on two units per the conditions in table IB. The recommended test
conditions for SEP are as follows:a.

The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive (i.e.,0°≤angle≤60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.

b.

The fluence shall be ≥ 100 errors or ≥ 10 7 ions/cm2.

c.

The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by measuring
the cross-section at two flux rates which differ by at least an order of magnitude.

d.

The particle range shall be ≥ 20 micron in silicon.

e.

The test temperature shall be +125°C ± 10% for SEL.

f.

For SEP test limits, see table IB

5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Manufacturers performed devices electrostatic discharge sensitive rate with Human body model (HDM) and classified as
ESDS class 1 minimum 2000 V and also performed ESDS rate with Charge device model (CDM) and classified as ESDS is 250 V.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are prov ided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

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Vendor item drawing
administrative control
number 1/

Devicemanufacturer
CAGE code

Mode oftransportationand quantity

V62/23608-01XE

01295

Small tape andreel, 250 units

Top sidemarking

Vendor part number

TPS7H2201

TPS7H2201MDAPTSEP 2/

1/ The vendor item drawing establishes an administrative control number
for identifying the item on the engineering documentation.
2/ This device has been marked RHA TID level 50 krads(Si) with L level(see paragraph 1.5 herein).

CAGE code

Source of supply

01295

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

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