Data Sheet SHF 12105 A
SHF Communication Technologies AG

Data SheetSHF 12105 A

Bit Pattern Generator

SHF reserves the right to change specifications and design without notice
V007 - April. 22, 2024 - Page 1

Data Sheet SHF 12105 A
SHF Communication Technologies AG

Description
The SHF 12105 A is a synchronized multi-channel 64 Gbps bit pattern generator (BPG). It generates digital bit
sequences such as pseudo-random bit sequences (PRBS) or user defined bit patterns.
Operating bit rates from 6 to 64 Gbps, continuously without gaps, is covered by the generated data patterns.
Depending on the configuration, the instrument features up to eight independent 64 Gbps differential
channels (16 outputs).
The operating bit rate is set by the clock signal from an external clock source. The outputs can operate atboth full clock and half clock, e.g., either a 64 GHz or a 32 GHz clock signal can be used for 64 Gbps operation.
The SHF 12105 A can be controlled remotely via an Ethernet interface either by use of the SHF Control Center
software provided by SHF or by custom software.
Further to the mode of operation as a multi-channel binary BPG, the functionality can be easily extended byattaching one of SHF’s extender heads:

By using high resolution DAC such as the SHF 6-Bit DAC the easy-to-use graphical user interface
enables the generation of arbitrary signals and the system becomes a fully functional AWG.
In case a multiplexer (MUX) extender head is attached, 120 Gbps NRZ signals can be brought as close
as possible to the DUT.
PAM4 Signal up to 128 GBaud (256 Gbps) can be generated by attaching the PAM4 multiplexer (PAMMUX).

Features

Four, six or eight 64 Gbps high quality differential data output channels



Broadband operation up to an aggregated bit rate of 512 Gbps



Built-in PRBS patterns and 8 Gbit user pattern per channel to support user defined patterns

Standard Patterns such as JP03A, JP03B, QPRBS13, PRBS13Q, PRBS31Q, SSPRQ, Transmitter
Linearity, SSPR, etc. are included and can be generated with combined signalsAll channels synchronized and independentOutputs adjustable up to -10 dB

All outputs can be used single ended or differential

Skew adjustment for each differential output



Bit shift for each differential output

Frame trigger output

Error injection capabilities

Controlled by intuitive graphical user interface SHF Control CenterRemote control over Ethernet

DC Offset (available with ‘Option HV’)

Clock distribution for trigger signals and DUTs



Jitter transparent output signals

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

Applications
The SHF 12105 A is the ideal pattern source for many R&D or production applications which require highspeed test data streams for electrical/optical components or transmission systems. The flexible channel
configurations, the wide gap-free data rate coverage and the advanced features make this BPG the perfect
fit for

single channel applications,e.g., OC-768/STM-256 (using 40G NRZ, DPSK), Fiber Channel®, PCI Express, Serial ATA

multi-channel applications,e.g., OC-768/STM-256 (using 40GBaud QPSK), 100GbE (using 4x32G DP-QPSK)

multi-level1 multi-channel applications ore.g., for 400G & 1TB DWDM (e.g., using DP-16QAM or 56G PAM4)



AWG applications
the SHF 12105 A + DAC combination is a full “remote head” non-interleaved AWG (Arbitrary
Waveform Generator) at a speed of up to 64 GBaud

Configurations
The SHF 12105 A can be equipped in a variety of different configurations.


Oct 64Hex 64
Quad 64– Eight differential outputs from 6 to 64 Gbps (sixteen single-ended outputs in total)– Six differential outputs from 6 to 64 Gbps (twelve single-ended outputs in total)– Four differential outputs from 6 to 64 Gbps (eight single-ended outputs in total)

Figure 1 - Front panel of the SHF 12105 A in config. Oct 64 and incl. Opt. AddClock1

up to 64 level signals can be generated with the help of one of SHF’s external DAC modules.

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

Options
Option HV - High Output Voltage
Maximum output amplitude of a 64 Gbps data output channel isinternally amplified to 2 V.
Option DC Offset – Output Offset Adjust
A DC offset output voltage can be adjusted internally or by applying an
external voltage to the front panel connector. This integrated Bias-T isonly available with ‘Option HV’.

Figure 2 - SHF 12105 A with extender heads

Option AddClock – Two additional full clock outputs
The option AddClock adds two additional full clock outputs, for example to drive the extender heads.
Option Extender SHF C603 A
Two output channels can be multiplexed externally to a data stream up to 120 Gbps by use of a SHF C603 A
2:1 multiplexer. For details please be referred to the data sheet of the SHF C603 A.
Option Extender DAC (e.g., SHF 613 A, SHF 614 C, SHF 615 B)
Operating the SHF 12105 A together with SHF DAC will make the system a 60 GSa/s Arbitrary Waveform
Generator (AWG). The vertical resolution is depending on the number of BPG outputs and DAC inputs bits.
Example applications include PAM4 with pre-emphasis. For details, please refer to the data sheet of the DACs
and the chapters AWG & User-Defined Waveform Capabilities and PAM4 Mode in this document.
Option Extender SHF 616 B
Four output channels can be multiplexed and combined externally to a PAM4 data stream up to 128 GBaudby use of a SHF 616 B. For details please be referred to the data sheet of the SHF 616 B.

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

Block Diagram

Figure 3 - Block diagram of the SHF 12105 A

The pattern generator consists of up to 32 16 Gbps pattern generation blocks which are synchronized to eachother. Four outputs of the pattern generation blocks are 4:1 multiplexed to generate one 64 Gbps data
output steam. Each data output module includes two data output channels consisting of a delay line for skew
control, a 4:1 MUX and optional amplifiers (Option HV) to raise the output amplitude to 2 V.
The clock distribution section processes the incoming clock signal to generate the clock out, clock/2 out,
clock/4 out, selectable clock out and word frame signals. With option AddClock, two additional full clock
outputs are provided, for example to drive the optional available extender heads. Internally the SHF 12105 A
works in half clock mode. To enable full clock operation, the incoming clock is divided by 2 by selecting fullclock mode in the software.

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

Specifications
Absolute Maximum Ratings
Parameter

Unit

SymbolClock Input VoltagemV

Vclk in

External DC Voltage on
RF Clock Input Port

V

VDCin

External DC Voltage on
RF Clock Output PortsV

External DC Voltage on
RF Data Output Ports

V

Min

Typ

Max

Comment

900

Peak-to-Peak

-10

+10

AC coupled input

VDCin

-10

+10

AC coupled outputs

-10

+10

with Option HV

VDCin

none2

none2

with Option HV & Offset

none2

none2

without Option HVExternal DC Voltage on
DC Offset PortsV

VOff,Ext-4+4

with Option HV & Offset

External DC Current on
DC Offset PortsmA

AOff,Ext

-110

+110

with Option HV & Offset

2 DC-coupled RF data outputs must not be charged by an external DC voltage

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

64 Gbps Data Output Specifications (without Option HV)Parameter

Unit

Minimum Bit Rate

Gbps

Maximum Bit Rate

Gbps

Maximum Output Level

mV

Symbol

Min

Typ

Max

4

63

64

65

650
1300

730
1460

800
1600

Vout

Comment

Single ended
Differential
Eye amplitude;
Adjustable by up to -10 dB; DC
coupled ground referenced CMLinterface@ 50 Ω load;

Output DC Level
Jitter (RMS)
on scope display4
Jitter (RMS)
deconvolved5
Jitter (PP)
Rise/Fall Timeon scope display6
Rise/Fall Timedeconvolved7

3
4

mv

VDCOut

fs

-500

-600

JRMS

500

650

fs

JRMS

460

620

ps

JPP

2.5

4

ps

tr/tf

9

11

20%...80%

ps

tr/tf

8.2

10.4

20%...80%

50

55

Crossing%

Duty Cycle%

Skew Control

psInter-Channel Skew

ps

Connector Type

Ω

-400

46

of two consecutive eyes;

50
-25

50

constant when adjusting output
amplitude

software adjustable+25

adjustable in 0.1 ps-steps

3

at 64 Gbps with skew control set
to 0 ps
1.85 mm (V);female connector

By use of the “Bitrate Divider” – function the minimum output bit rate can be reduced further down to 1.5 Gbps (see page 14)
Measured with a 70 GHz sampling head and precision time base triggered by Clk or Clk/2 output, using PRBS 231-1
200

5 Calculation based on typical jitter from oscilloscope data sheet:
6

Measured with a 70 GHz sampling head and precision time base triggered by Clk or Clk/2 output, using PRBS 231-1

7

Calculation based on typical rise/fall times from oscilloscope data sheet:.

3.68 #

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

64 Gbps Data Output Specifications (with Option HV)Parameter

Unit

Minimum Bit Rate

Gbps

Maximum Bit Rate9Gbps

Maximum Output Level

mV

Symbol

Min

64

Vout

Typ

Max

4

68

Comment

65

2000

Single ended

4000

Differential
Eye amplitude; AC coupled
Adjustable by up to -10 dB

Jitter (RMS)
10

On scope display
Jitter (RMS)
Deconvolved

11

Jitter (PP)

Rise/Fall TimeOn scope display12

Rise/Fall Time
Deconvolved13

fs

JRMS

fs

JRMS

ps

JPP

500

650

Vout ≥ 500 mV

600

1000

Vout < 500 mV

460

620

Vout ≥ 500 mV

570

980

Vout < 500 mV

2.5

4

Vout ≥ 500 mV

3

5

Vout < 500 mV
20%...80%

ps

tr/tf

9

11

Vout ≥ 500 mV

10

12

Vout < 500 mV
20%...80%

ps

8.2

10.4

Vout ≥ 500 mV

9.3

11.4

Vout < 500 mV

46

54

Vout ≥ 1000 mV

40

60

Vout < 1000 mV

53

of two consecutive eyes;
software adjustable+25

adjustable in 0.1 ps-steps

3

at 60 Gbps with skew control set
to 0 pstr/tf

Crossing%

Duty Cycle%

47

Skew Control

ps

-25

Inter-Channel Skew

ps

Connector Type

Ω

50

50

1.85 mm (V);female connector

8

By use of the “Bitrate Divider” – function the minimum output bit rate can be reduced further down to 1.5 Gbps (see page 14)

9

Measured with PRBS 231-1, BER < 1e-12

10Measured with Tektronix DSA8300 with 70 GHz sampling head and phase reference triggered by Clk or Clk/2 output, using PRBS 231-1
200

11 Calculation based on typical jitter from oscilloscope data sheet:
12

Measured with a 70 GHz sampling head and precision time base triggered by Clk or Clk/2 output, using PRBS 231-1

13

Calculation based on typical rise/fall times from oscilloscope data sheet:.

3.68 #

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

DC Offset Specifications (with Option DC Offset)
Parameter

14

Unit

SymbolMin

DC Offset Voltage(internal supply)V

VOff,IntDC Offset Current(internal supply)mA

DC Offset Voltage(external supply)
DC Offset Current(external supply)Max

Conditions-2.514,15+2.514,15

software adjustable;@ load current = 50 mA(Rload = 50 Ω)

AOff,Int-5014,15+5014,15

V

VOff,Ext-3.515,16+3.515,16mA

AOff,Ext

10015,16+10015,1

applied to “DC Offset“connector

6

DC Offset voltage on the RF output port varies with the external load resistance; internal bias-t resistance is ~6.4 Ohm

15 Consideration of16

Typthe application note „Impact of Bias Tees on Communication Signals“ from www.shf-communication.com recommended

DC Offset voltage on the RF output port varies with the external load resistance; internal bias-t resistance is ~3.9 Ohm

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

64 Gbps Data Output Specifications (with Option HV)Parameter

Unit

Symbol

Min

Typ

Max

Connector Type1.85 mm (V)female connector
1.85 mm (V)female connector
1.85 mm (V)female connector
2.92 mm (K)female connector
2.92 mm (K)female connector
2.92 mm (K)female connector

Clock Input
Clock Output
Optional Clock Output
Ω

50

Clock/2
Clock/4
Sel. Clock Output
Minimum Clock Input
Frequency

3
6

GHz

fin_clockGHz

fin_clock32
64

Input LevelmVpp

Vin_clock630

Output Level
Clock
Clock/2
Clock/4
Selectable ClockmVpp

Vout_clock

Maximum
Frequency

Clock

Input

Output Frequency
Clock
Clock/2
Clock/4
Selectable Clock

GHz
GHz
GHz
GHz

Word Frame Trigger

MHz

17

fout_clock

450
500
500
250
3
1.5
0.75
0.006

Comment

half clock mode17
full clock mode17
half clock mode17
full clock mode17

700
800
800
450

1000

AC coupled

1000
1000
1000
600

AC coupled, @ Pin=0 dBm
AC coupled
AC coupled
AC coupled

64
32
16
16

same as input frequency
half of input frequency
quarter of input frequency
input frequency/N(N= 4, 8, 16, 32, 64, 128, 256, 512,
1024)

500

The operating bit rate is determined by a clock signal from an external clock source which is not part of the pattern generator. The outputs can operate
at both full clock and half clock, so e.g., a 20 GHz or a 40 GHz signal is required for 40 Gbps operation.

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

General Specifications
Parameter

Unit

Symbol

Min

Typ

Max

Conditions

Weightkg

m

45

Fully Equipped

Dimensions

mm

WxDxH

Operating Temperature

°C

TOP

10

35

Storage Temperature

°C

TST

-20

70

@ 95 % RH max.

Working Humidity

%

20

90

Non condensing

Conditions

600x480x150

Rear Panel Connections
Parameter

Unit

SymbolPower Supply

V

U

Power Consumption

W

P

Min

Typ

Max

100

110

135

210

230

240
400

50…60 HzMax. Configuration@110-230 V

Power Supply Connector

IEC-60320 C14

Common Ground Connector

4 mm socket

Network Connectors

RJ-45 Ethernet

Front Panel Connections
Parameter

Unit

SymbolMin

TypDC Offset Connectors
Auxiliary Power Outputs

Max

Conditions
Lemo EPZ.0B.309.HLN

V

U

–5
+5
+12

Max. 1.5 A
Max. 1.5 A
Max. 1.7 A

Auxiliary Power Connectors

Lemo EPG.OB.304.HLN

Common Ground Connector

4 mm socket

Network Connector

RJ-45 Ethernet

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

Patterns
Pattern

Polynomial

PRBS 27-1

G(x) = 1 + x6 + x7

PRBS 29-1

G(x) = 1 + x5 + x9

PRBS 210-1

G(x) = 1 + x7 + x10

PRBS 211-1

G(x) = 1 + x9 + x11

132

Reference

ITU-T O.150 5.1
IEEE 802.3 68.6.1

12

ITU-T O.150 5.2

PRBS 2 -1

G(x) = 1 + x + x + x + x

PRBS 215-1

G(x) = 1 + x14 + x15

PRBS 220-1

G(x) = 1 + x3 + x20

PRBS 223-1

G(x) = 1 + x18 + x23

13IEEE 802.3 94.3.10.8
ITU-T O.150 5.3

ITU-T O.150 5.6

User Pattern Capabilities
Parameter

Unit

User Pattern Memory size

Symbol

Min

Typ

Max

Conditions

8

Per channel

Gbit

User Pattern Granularity

Bit

512

For more details see Chapter
User Pattern Capabilities

Example Patterns Provided
Pattern
SSPR

Polynomial

18

OIF-CEI-03.1 Annex 2.D.2

JP03A18IEEE 802.3 94.2.9.1

JP03B18QPRBS13IEEE 802.3 94.2.9.2
18IEEE 802.3 94.2.9.3

Transmitter Linearity18

IEEE 802.3 94.2.9.4

PRBS13Q18

IEEE 802.3 120.5.11.2.1

SSPRQ

18

IEEE 802.3 120.5.11.2.3

Square Wave Quaternary18

18

IEEE 802.3 120.5.11.2.4

Is a PAM4 pattern and can be generated by combining the BPG output signals with a DAC

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

Output Adjustment Capabilities

Figure 4 - SHF Control Center window for the SHF 12105 A

Bit Rate
The bit rate of all outputs is continuously adjustable by a single external clock signal.
Clock Input
In full clock mode, the BPG will need a 64 GHz clock signal to generate a 64 Gbps data signal. In half clockmode, a 32 GHz clock signal will be needed to generate a 64 Gbps data signal. Internally the SHF 12105 A
operates in half clock mode. When selecting full clock mode, a divider is used to generate the half clock
needed internally from the externally provided full clock.
Selectable Clock
The selectable clock output provides a divided clock signal derived from the clock input signal. A divider ratioof 1/n with n = 4, 8, 16, 32, 64, 128, 256, 512 or 1024 can be selected.
Word Frame
To display the pattern trace on the oscilloscope the word frame signal can be used to trigger the oscilloscope.
The word frame can be set to one of the PRBS word lengths or to a user defined value.
AUX Power
This control is needed to enable the aux power voltages provided on the front panel.
Group Synchronization
The data outputs can be grouped. All data outputs of one group are bit synchronized to enable AWG
functionality together with a DAC, cross talk measurements and PRBS conformed multiplexing.

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

Pattern Type
Pre-defined PRBS patterns from 27-1, 29-1, 210-1, 211-1, 213-1, 215-1, 220-1, 223-1 and 231-1 are available. Userdefined binary patterns can be loaded from file in single column text file format. All PRBS and user patterns
can be assigned individually to each channel.

Figure 5 - SHF Control Center upload GUI for binary user patterns

Pattern Polarity
All patterns can be inverted by use of this function
Bit Delay / Bit Shift
In case two or more PRBS patterns of the same length are selected it is possible to control the starting pointof each bit sequence (in 1 bit steps up to the total PRBS length).
Bit Rate Divider
The ‘bit rate divider’ is a software function to transmit the same bit multiple times and thus reduces the data
rate (divided by 2 or 4).
Error Injection
For testing purposes, a fixed error rate can be added to the date stream.
Duty Cycle
The duty cycle of two consecutive eyes/bits is automatically set to 50%. However, in case the application
requires a modification or a further optimization, this could be done with a few clicks.
Skew
The timing of every output channel can be adjusted individually in 0.1 ps steps (please see chapter Skew
Control Function for more details).
DC Offset
The DC offset of a high voltage RF output port can be switched between an internal generated DC voltage
and an external supplied DC voltage.
Amplitude
The output amplitude of each channel is adjustable independently.
Output On/Off
The outputs can be turned on and of individually. During and after start up these are turned off to preventany damage to the DUTs attached.

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

AWG & User-Defined Waveform Capabilities
The SHF 12105 A and a SHF DAC are not just two discrete modules connected together. The SHF Control
Center software provides a variety of features which can be used in case a SHF DAC is connected to the BPG.
The software offers an interface for user defined signals by use of the Python programming language or theuser may load externally generated signals from software like Matlab. A set of commonly used signals isprovided with the SHF Control Center. The software only needs to know which BPG output is physicallyconnected to which DAC input. The SHF Control Center will calculate the user pattern for each channel in a
way that the DAC generates the desired arbitrary signal.
The best results are achieved with the SHF 614 C 6-Bit DAC and a SHF 12105 A with at least 6 channels as thisarchitecture provides a vertical resolution of 26=64 steps reducing quantization errors.

Figure 6 – Arbitrary Waveform Generator Interface

The SHF 12105 A has 8 Gbit of built-in user pattern memory for each output channel. Due to the memory
width of 512 bits, there is a granularity requirement of 512 bits which can be overcome by repeating thepattern until the least common multiple of the pattern length and 512 is met.
The SHF Control Center software supports creating, editing and converting different formats of user pattern
files to be used with the SHF 12105 A. It will handle all user patterns.
For example, it will repeat automatically user patterns not fulfilling the granularity requirement until the
granularity of 512 is met. For patterns up to 16 Mbit this is always possible. Patterns larger than 16 Mbit haveto fulfill the following prerequisites:
Pattern length
up to
16 Mbit
32 Mbit
64 Mbit
128 Mbit
256 Mbit
512 Mbit
1 Gbit2 Gbit
4 Gbit
8 GbitPattern length has
to be a multiple of
1
2
4
8
16
32
64
128
256
512

Two BPG output channels (1&5, 2&6, 3&7 and 4&8) share one common memory controller, so that theirpatterns need to be of the same length or need to be repeated until the least common multiple is met. For
most applications like PAM, AWG, DACs and Muxes the patterns need to be of the same length anyway.

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

PAM4 ModeFor binary data a BPG has obvious advantages over an AWG as the bit/baud rate always equals the sample
rate (no fractional oversampling) and as logical pattern generation techniques can be applied without
utilizing a rather slow and small memory. With the SHF 12105 A these advantages do also apply to a BPG/DAC
combination when generating PAM4 signals where even the individual eye heights or pre-emphasis can beachieved and adjusted on the fly without waiting for the memory to be loaded and by still transmitting very
long patterns (e.g., PRBS 231-1 or PRBS31Q).

No issues with long
patterns (e.g. PRBS
231-1) as the pre-coding isdone in hardware!

Individual eye heights canbe set without utilizing thememory.

Pre-Emphasis (FIR Filter)can be set without utilizing
the memory.

Figure 7 - SCC in PAM Mode

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

Jitter Transparency
By modulating the clock input signal with a low frequency signal, one can quickly and easily create jitteredclock signals with complex properties to drive the SHF 12105 A to emulate jittered high speed NRZ data
(Fig.8). Adding a DAC gives the possibility to generate jittered PAM4 signals (Fig. 9 & 10), ensuring the setup
is ready for the increase in modulation orders and lane rates for the anticipated serial data protocols to come.
For more information see Application Note “Creating Complex Jittered Test Patterns” on SHFs web page.

Figure 8 – Sine-jittered data output signal from SHF 12105 A

Figure 9 – Sine-jittered data output signal (MSB) from a SHF DAC

Figure 10 – Sine-jittered data output signal (PAM4) from a SHF DAC

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

Skew Control and Bit Delay Functions
The skew control and bit delay functions allow adjustment of the channel timing relative to each other. As aresult, timing delays between individual output channels can be adjusted in 0.1 ps steps (using skew control),as well as over many integer bit periods (using the bit delay function). The figures below show the SHF Control
Center with this feature and an example of delay between two channels for skew within a bit and more than
one bit.

+5 ps

-5 ps

0 ps

+5 ps
+2 bits+5 ps

Figure 11 – Skew control & integer bit delay

Bit Delay
Control

Skew
Control

Figure 12 – Bit delay and skew control software representation

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

Typical Output Waveforms
Data Output Signals (without Option HV)

68 Gbps output at maximum output level

64 Gbps output at maximum output level

60 Gbps output at maximum output level

50 Gbps output at maximum output level

40 Gbps output at maximum output level

32 Gbps output at maximum output level

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

20 Gbps output at maximum output level

16 Gbps output at maximum output level

10 Gbps output at maximum output level

3 Gbps output at maximum output level

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

Data Output Signals - Amplitude Adjustment (without Option HV)

64 Gbps output at 730 mV

64 Gbps output at 600 mV

64 Gbps output at 500 mV

64 Gbps output at 400 mV

64 Gbps output at 300 mV

64 Gbps output at 200 mVSHF reserves the right to change specifications and design without notice
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Data Sheet SHF 12105 A
SHF Communication Technologies AG

Data Output Signals (with Option HV)

64 Gbps output at maximum output level

60 Gbps output at maximum output level

56 Gbps output at maximum output level

50 Gbps output at maximum output level

40 Gbps output at maximum output level

32 Gbps output at maximum output level

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

20 Gbps output at maximum output level

16 Gbps output at maximum output level

10 Gbps output at maximum output level

6 Gbps output at maximum output level

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Data Sheet SHF 12105 A
SHF Communication Technologies AG

Data Output Signals - Amplitude Adjustment (with Option HV)

60 Gbps output at 2000 mV

60 Gbps output at 1000 mV

60 Gbps output at 1500 mV

60 Gbps output at 500 mVSHF reserves the right to change specifications and design without notice
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Data Sheet SHF 12105 A
SHF Communication Technologies AG

Data Output Signals (with Option HV & Bias-T)

64 Gbps output at maximum output level

60 Gbps output at maximum output level

56 Gbps output at maximum output level

50 Gbps output at maximum output level

40 Gbps output at maximum output level

32 Gbps output at maximum output level

SHF reserves the right to change specifications and design without notice
V007 - April. 22, 2024 - Page 25

Data Sheet SHF 12105 A
SHF Communication Technologies AG

20 Gbps output at maximum output level

16 Gbps output at maximum output level

10 Gbps output at maximum output level

6 Gbps output at maximum output level

SHF reserves the right to change specifications and design without notice
V007 - April. 22, 2024 - Page 26

Data Sheet SHF 12105 A
SHF Communication Technologies AG

73.1
57.3

Outline Drawing – Front Panel

4x 15mm

7x 15mm

15mm

54.6
144.5

7x 15mm
274.8
315.1

All dimensions are specified in millimeters (mm).

SHF reserves the right to change specifications and design without notice
V007 - April. 22, 2024 - Page 27

Data Sheet SHF 12105 A
SHF Communication Technologies AG

132.5
57.16

Outline Drawing – Case

482.2

148.4

599.1
558.1

555.1

447.7

All dimensions are specified in millimeters (mm).

SHF reserves the right to change specifications and design without notice
V007 - April. 22, 2024 - Page 28

Data Sheet SHF 12105 A
SHF Communication Technologies AG

SHF Communication Technologies AG
Wilhelm-von-Siemens-Str. 23 D | 12277 Berlin | Germany+49 30 772 051 0
sales@shf-communication.com
www.shf-communication.com

SHF reserves the right to change specifications and design without notice
V007 - April. 22, 2024 - Page 29