Evaluation Board User Guide
UG-119One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

ADAU1361 Evaluation Board
PACKAGE CONTENTS

GENERAL DESCRIPTIONADAU1361 evaluation board
USBi control interface board
USB cable
Evaluation board documentation/quick-start guideThis user guide explains the design and setup of the ADAU1361
evaluation board.
The EVAL-ADAU1361Z includes both single-ended and differential stereo line-level analog audio inputs as well as a digitalaudio interface. Single-ended and differential analog outputs arealso provided, as well as a stereo capless headphone output.

SUPPORTING DOCUMENTATIONADAU1361 data sheet
AN-1056 Application Note, Capless Headphone Virtual Ground
Short-Circuit Protection for the ADAU1361 and ADAU1761
AN-1006 Application Note, Using the EVAL-ADUSB2EBZ
AN-1007 Application Note, Using the ADAU1761 in DSP
Bypass Mode to Emulate an ADAU1361
SigmaStudio Help (included in software installation)

The USBi provides power and the I2C communications interface tothe evaluation board. A switch allows the ADAU1361 to operate ateither 3.3 V or 1.8 V. The SigmaStudio™ programming software isused for all register controls and SigmaDSP® core programming.
A header is included for interfacing to stereo digital microphones.

EVALUATION BOARD BLOCK DIAGRAM

I2C COMMUNICATIONSINTERFACE (USBi)

POWER
SUPPLYDIGITALMIC
INPUTSANALOG
AUDIO
INPUTSANALOGAUDIOOUTPUTS

08957-001

ADAU1361

Figure 1.

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.

Rev. 0 | Page 1 of 12

UG-119

Evaluation Board User Guide

TABLE OF CONTENTS
Package Contents .............................................................................. 1

Using the Evaluation Board .............................................................5

Supporting Documentation ............................................................ 1

ADAU1361 Low-Power Codec ...................................................5

General Description ......................................................................... 1

Power...............................................................................................5

Evaluation Board Block Diagram ................................................... 1

Analog Audio Input ......................................................................5

Revision History ............................................................................... 2

Analog Audio Output ...................................................................5

Setting Up the Evaluation Board—Quick Start ............................ 3

Clocking the Evaluation Board ...................................................6

SigmaStudio Software Installation ............................................. 3

External Digital Audio Header ....................................................6

Hardware Setup, USBi.................................................................. 3

Digital Microphone and Jack Detection Input ..........................6

Powering the Board ...................................................................... 3

I2C Communications Header ......................................................6

Connecting Audio Cables ........................................................... 3

Evaluation Board Schematics and Artwork ...................................7

Switch and Jumper Settings......................................................... 3

Ordering Information .................................................................... 10

Setting Up the Registers in SigmaStudio ................................... 4Bill of Materials ........................................................................... 10

REVISION HISTORY
3/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 12

Evaluation Board User Guide

UG-119SETTING UP THE EVALUATION BOARD—QUICK START
SigmaStudio SOFTWARE INSTALLATIONSWITCH AND JUMPER SETTINGS

To install the SigmaStudio software, follow these steps:

To configure the board for stereo analog input and output, makesure that the switches and jumpers are set as follows (see Figure 2).

1.

2.
3.

Open the provided .zip file and extract the files to your PC.
Alternately, insert the SigmaStudio CD into the PC opticaldrive and locate the SigmaStudio folder on the CD.
If Microsoft® .NET Framework Version 2.0 is not alreadyinstalled on the PC, install it by double-clicking dotnetfx.exe.
Install SigmaStudio by double-clicking setup.exe andfollowing the prompts. A computer restart is not required.

HARDWARE SETUP, USBi
To set up the USBi hardware, follow these steps:
1.
2.
3.

Plug the USBi ribbon cable into Header J1.
Connect the USB cable to your computer and to the USBi.
When prompted for drivers, follow these steps:
a)
b)
c)
d)
e)
f)
g)

•
•
•
•
•
•

•

The ADAU1361 uses the on-board oscillator as a masterclock source (S5 switched to OSC).
Regulator output VDD is set for 3.3 V operation(S1 switched to 3.3 V).
Power is supplied by USB (J5 is connected with a jumper).
AVDD is connected to VDD (J17 connected).
IOVDD and AVDD operate at VDD (J16 connected).
DAC_SDATA and ADC_SDATA are tied together to loopback data from ADC to DAC (jumper across two bottom
right pins of J6).
I2C control mode is hardwired on board.

Choose Install from a list or a specific location.
Choose Search for the best driver in these locations.
Check the box for Include this location in the search.
The USBi driver is located in C:\Program Files\
Analog Devices Inc\Sigma Studio\USB drivers.
Click Next.
If prompted to choose a driver, select CyUSB.sys.
If the PC is running Windows® XP and you receive themessage that the software has not passed Windows
Logo testing, click Continue Anyway.

POWERING THE BOARD
The board can be powered either by the USBi or by an external
power supply. For the board to run independently from thecomputer, disconnect Jumper J5 and connect the power supply
at J2. The power indicator LED D1 should now be lit.

CONNECTING AUDIO CABLES
In this example, the board is set up for stereo analog inputs andstereo analog outputs, using 3.5 mm (1/8”) cables.
Connect the audio source to Input Jack J24.
Connect Output Jack J19 to your headphones.

08957-002

1.
2.

Figure 2. Evaluation Board Setup and ConfigurationRev. 0 | Page 3 of 12

UG-119

Evaluation Board User Guide
1.

SETTING UP THE REGISTERS IN SigmaStudioThis section details how to pass an audio signal from the ADC
inputs to the DAC outputs using the headphone drivers. The
codec is configured with SigmaStudio.

3.

2.

Start playing the audio source; you should hear audio on the
outputs.

Your screen should now resemble Figure 3.

08957-004

2.

Create a new project. The Hardware Configuration
tab opens.
Drag an ADAU1361 cell and a USBi cell into the blankwork area.
Connect the USBi cell to the ADAU1361 cell by clicking
and dragging from the top blue output pin of the USBi cellto the green input pin of the ADAU1361 cell.

This locks the PLL and sets up the registers for proper
routing of the record and playback paths. If the PLL has
successfully locked, then the box under PLL Lock Bit
should turn from red to green.

Figure 4. Hardware Configuration Tab—Register Setup

08957-003

1.

In the IC1-ADAU1361 Register Controls tab, select the 3
and 4 in Capless HP Out option from the Automatic
Startup list and click Load Preset (see Figure 4).

Figure 3. Hardware Configuration Tab

Rev. 0 | Page 4 of 12

Evaluation Board User Guide

UG-119USING THE EVALUATION BOARD
ADAU1361 LOW-POWER CODEC
The ADAU1361 is a low power, stereo audio codec that
supports stereo 48 kHz record and playback at 14 mW from a
1.8 V analog supply. The stereo audio ADCs and DACs support
sample rates from 8 kHz to 96 kHz as well as a digital volume
control.
The SigmaStudio graphical development tool is used to configure
the ADAU1361. SigmaStudio’s outputs can be used to easily
integrate the ADAU1361 in a system.
The record path includes an integrated microphone bias circuitand six inputs. The inputs can be mixed and muxed before the
ADC, or they can be configured to bypass the ADC. The
ADAU1361 includes a stereo digital microphone input.
The ADAU1361 includes five high power output drivers (twodifferential and three single-ended) that support stereo headphones, an earpiece, or other output transducers. AC-coupledor capless configurations are supported. Individual fine level
controls are supported on all analog outputs. The output mixer
stage allows for flexible routing of audio.

L1 and C24 are connected to the AVDD pin of the ADAU1361
and function as an L-C filter to reject high frequency power
supply noise common in GSM mobile applications. This filter
is tuned to approximately 1.5 GHz.

ANALOG AUDIO INPUTThe EVAL-ADAU1361Z has three ac-coupled 1/8” input jacks:
two mono differential jacks and one stereo single-ended jack.
The tips of the differential input jacks, J20 and J22 (labeled IN 1
and IN 2), are connected to the negative input of the ADAU1361,
and the rings are connected to the positive input. The stereo
single-ended input on J24 (labeled IN 3) is connected to the
LAUX and RAUX inputs of the ADAU1361. IN 1 and IN 2 canalso be configured to bias a microphone. This is enabled byconnecting the MICBIAS pin of the ADAU1361 to the tip of the
input connectors with Jumper J15 and Jumper J18.
At VDD = 3.3 V, the full-scale analog input level of the EVALADAU1361Z is 1.0 V rms (1.0 V rms on the single-ended
inputs and 0.5 V rms on each of the two pins of the differential
inputs). The full-scale input level scales with VDD.

POWERANALOG AUDIO OUTPUT

The evaluation board uses the ADP3336 low dropout voltage
regulator to generate either 3.3 V or 1.8 V for the board. The
output voltage VDD of the ADP3336 is set with external resistors
that can be switched with S1 to select either 3.3 V or 1.8 V
outputs (see Table 1).

The EVAL-ADAU1361Z has four 1/8” output jacks: twomono differential, one stereo single-ended, and one stereo
capless headphone output. The differential outputs on J21
and J25 (labeled DIFF OUT L and DIFF OUT R, respectively,
are biased at AVDD/2 V. The tips of the differential output jacks
are connected to the positive output of the ADAU1361, and therings are connected to the negative outputs. J23 is a stereo,
single-ended, ac-coupled output.

Table 1. VDD Voltage Settings
Voltage Regulator Output (V)3.3
1.8

S1 Setting
Up
Down

At VDD = 3.3 V, the full-scale analog output level of the
EVAL-ADAU1361Z is 1.0 V rms (1.0 V rms on the single-ended
outputs and 0.5 V rms on each of the two pins of the differential
outputs). The differential line outputs of the ADAU1361 caneach be boosted by 6 dB to 2.0 V rms. The full-scale output level
scales with VDD.

The maximum operating current draw from this board isapproximately 75 mA. This maximum value is reached with
VDD = 3.3 V, headphone outputs enabled, and all LEDs
enabled.
Typically, the regulator input comes from the USBi 5 V dc USB
supply on Header J1. This supply is enabled with a jumper on
J5. To use another 5 V dc supply source, remove the jumper
on J5 and connect the other supply either on the J2 power jack(positive tip) or via soldering leads from a supply such as abattery to J3. On J3, Pin 1 (square pad) is ground, and Pin 2(circle pad) is the power connection.
When the ADP3336 is outputting a regulated voltage, LED D1
is illuminated red.
VDD is connected to the AVDD pin of the ADAU1361 with
Jumper J17. To connect the ADAU1361 IOVDD pin to the same
supply, connect J16, also. These headers can also be used toseparate the supplies of the ADAU1361 from the rest of theboard and to connect an external supply to the ADAU1361.

Note that Jack J21 and Jack J25 tie the ring to the sleeve, resulting
in a floating ground output. Be aware of this when connecting
to these outputs.
Table 2. Analog and Digital Audio Connectors
Jack
J4
J6
J19
J20
J21
J22
J23
J24
J25

Rev. 0 | Page 5 of 12

Function
Stereo digital microphone input
Serial data port input/output
Capless headphone output
Left differential input
Left differential output
Right differential input
Stereo single-ended line output
Stereo single-ended line input
Right differential output

UG-119

Evaluation Board User Guide

CLOCKING THE EVALUATION BOARD

Table 3. Master Clock Source Settings
Clock Source
Do Not Use—Function Disabled on USBi
MCLK from Header J6
On-Board 12.288 MHz Clock Oscillator (U3)S5 Setting
Up
Middle
Down

J7

J8

08957-006

The EVAL-ADAU1361Z requires a master clock to operate. The
source of this clock is set by Switch S5 (see Table 3).

Figure 6. Jumper Settings (J7 and J8) for Jack Detection (Low Signal Detected)

EXTERNAL DIGITAL AUDIO HEADER

Figure 7. Jumper Settings (J7 and J8) for Jack Detection (High Signal Detected)

DIGITAL MICROPHONE AND JACK DETECTIONINPUT

I2C COMMUNICATIONS HEADER

A pair of digital microphones can be connected to the evaluation board on Header J4. The pin connections for J4 aredetailed on the evaluation board silkscreen.

J8

The I2C communications header, J1, provides an interface to the
ADAU1361 communications port. This header connects to theUSBi board (EVAL-ADUSB2), which controls communication
between the evaluation board and SigmaStudio on the PC.
Additionally, a DSP reset line and USB bus power line areprovided. The SigmaStudio hardware configuration for thissetup is shown in Figure 8.

08957-005

J7J808957-008

J7 and J8 set up the routing of signals to the JACKDET/MICIN
pin of the ADAU1361. These jumper settings are shown in
Figure 5, Figure 6, and Figure 7; they are also shown on the PCBsilkscreen. Toggling the jack detection signal can be simulated
by setting up the jack detect function on the ADAU1361 andthen inserting and removing Jumper J8 with J7-B (lower
connection) connected.

J708957-007

The LRCLK, BCLK, ADC_SDATA, and DAC_SDATA pins of
the ADAU1361 can be connected to external devices with the
5 × 2 header, J6. The pins on the top row of J6 are connected to
ground; the pins on the bottom row are the signals indicated on
the silkscreen.

Figure 5. Jumper Settings (J7 and J8) for Stereo Digital Microphone Input

Figure 8. Using the EVAL-ADAU1361Z and the USBi with SigmaStudioRev. 0 | Page 6 of 12

J24

C2

1kΩ

R27

1kΩ

R24

0Ω

R16

0Ω

C12
0.10µFR200Ω

R8 0.10µF

0Ω

R11

C3
OPEN

C25
OPEN

C27
OPEN

C13
OPEN

C19
OPEN

C6
OPEN

49.9kΩ RESISTORS ON INPUTS REFERENCE AC COUPLINGCAPACITORS TO GROUND PREVENTING POPS WHEN
'HOT-PLUGGING' INPUTS. NOT NECESSARY FOR
HARDWIRED DESIGN.

2kΩ

R15

MIC_BIAS

DIFFERENTIAL INPUT 2

STEREO SINGLE-ENDED INPUT

J22

J20

2kΩ

R7

MIC_BIAS

J15

J18

R12
R9

DIFFERENTIAL INPUT 1

49.9kΩ
49.9kΩ
49.9kΩ

10µF
C7
10µF
C5

SCL

SDA

MONOOUT 21
LHP 20

ADDR0/CLATCH
MCLK

2SCL/CCLKSDA/COUTADDR1/CDATAJACKDET/MICIN

3

32

31

30

4

14
RAUX

7

12.288MHZ
4 VDD
OE 1
3
49.9Ω OUTPUT U3
2 GND
R47

EXT_MCLK23

4

USB_CLK

1

CM

10kΩ
R46

C39
0.10µFC18
0.10µF

BCLK

LRCLK

6
8

5
7

1

S5-B

C21
10µF

DAC_SDATALRCLK 29BCLK 28

ADC_SDATA

L2
2

R5

R3
OPEN

R13
OPEN

R29
OPEN

R18
10kΩ

100Ω

R19

R22
10kΩ

100Ω

R23

R2
OPEN

0Ω

IOVDD
IOVDD

VDD

R26
OPEN

10µF

C17

10µF

C23

R14
OPEN

OPEN

0Ω

R10
C4
+

OPEN
0Ω

C1
R6 +

R4
OPEN

CAPLESSHEADPHONE OUTPUT

BOARD IS SHIPPED IN CAPLESS MODE.
TO CONVERT TO AC-COUPLED,REMOVE 0Ω RESISTORS FROM R5, R6, AND R10;
ADD 220µF CAPACITORS TO C1 AND C4 AND 0Ω RESISTOR TO R4.

DAC_SDATA 27

2

C24
9.1PF

26

ADC_SDATA

RHP 1912
LOUTN 17
LOUTP 18
16
ROUTN
ROUTP 15U1
ADAU1361

C220.10µFL1

RINP
6 LAUX

LINP

LINN

C16
0.10µF

1
1.2nH

VDD

C14
10µF

RINN

13

10

11

C10
0.10µF

DVDD

TP5

S5-A

JACKDET/MICIN

MIC_BIAS

0.10µF

C31

10µF
C8
10µF
C11
MICBIAS 5

IOVDD

25 DGND

10µF
C20
10µF
C15
10µF
C26

IOVDD 1

J17
AVDD 8

AGND

9

AGND
22

R21
R17
R25

49.9kΩ
49.9kΩ

R28

Rev. 0 | Page 7 of 12
49.9kΩ

Figure 9. Board Schematics, Page 1
10µF
C28

24
DVDDOUT

J16
23
AVDD

TP3

MONO DIFFERENTIAL OUTPUT RIGHT

J25

J23

STEREO SINGLE-ENDED OUTPUT

J21

MONO DIFFERENTIAL OUTPUT LEFT

J19

Evaluation Board User Guide
UG-119EVALUATION BOARD SCHEMATICS AND ARTWORK
08957-009

Rev. 0 | Page 8 of 12

2
3
1
RAPC722X

J2

Figure 10. Board Schematics, Page 2
OPEN

K

BRD_RESETA

D4+5V SUPPLY FROM USBi

BATTERY INPUT

+5V

J3

J5

C34
0.10µF

R32
10kΩ

C32
10µF
TP2

C33
0.10µF

4

TP1 TP4

U2

ADP3336
7 IN
OUT 1
8 IN
OUT 2
6 SD
OUT 3
5
GND FB

J4

12
10
8
6
4
2

TP6

R33
147kΩ

10kΩ

R37

VDD

169kΩ

R34

140kΩ

R35

C35

10nF

SPDT

R39

M2

3V3

C36
0.10µF

C37
10µF

VDD

POLARIZING PLUG 100ΩJUMPER2SIP3
J7
A B

IOVDD

RED DIFFUSED

D1

100Ω

C29
0.10µFC30
0.10µF

SCL
SDA

C40
0.10µF

1
3
5
7
9

R31
10kΩ

C41
0.10µF

J6

2x5
9
7
5
3
1

SERIAL DATA INTERFACE

10
8
6
4
2

+5V
J1 USB_CLK246810 BRD_RESETHEADER_10WAY_POL

R30
10kΩ

IOVDD

CONTROL PORT INTERFACE

LRCLK
BCLK
DAC_SDATAADC_SDATA
49.9Ω

R38

PLANE DECOUPLING

EXT_MCLKBCLK

JACKDET/MICIN

R48

J8

R1

10kΩ

S1 1V8

DIGITAL MICROPHONE INPUT

SOCKET_12WAY_UNSHROUD

10kΩ

11
9
7
5
3
1

DVDD = +1.8V (SHOWN) OR +3.3 V SUPPLY

M1

POLARIZING PLUG

R36

RIGHT DMICLEFT DMICJACK DETECT SIGNAL

C38
0.10µF

UG-119Evaluation Board User Guide08957-010

UG-11908957-011

Evaluation Board User Guide

Figure 11. Board Silkscreen and Parts Placement

Rev. 0 | Page 9 of 12

UG-119

Evaluation Board User Guide

ORDERING INFORMATIONBILL OF MATERIALS
Table 4.
Qty
2
12

6
14

1
4
1
1
1
1
1
1
1
6
1
1
7
1
1
4
7
7
2
6
9
2
1
1
1
2
1
1
6
1
1
1

Designator
C1, C4
C2, C10, C12, C16, C18,
C22, C31, C33, C34, C36,
C38, C39
C3, C6, C13, C19, C25, C27
C5, C7, C8, C11, C14,
C15, C17, C20, C21, C23,
C26, C28, C32, C37
C24
C29, C30, C40, C41
C35
D1
D4
J1
J2
J3
J4
J5, J8, J15 to J18J6J7J19 to J25
L1
L2
R1, R19, R23, R48
R2 to R4, R13, R14,
R26, R29
R5, R6, R8, R10, R11,
R16, R20
R7, R15
R9, R12, R17, R21,
R25, R28
R18, R22, R30 to R32,
R36, R37, R39, R46
R24, R27
R33
R34
R35
R38, R47
S1
S5
TP1 to TP6
U1
U2
U3

Description
Capacitor (open)
Capacitor, multilayer ceramic, 0.10 μF, 50 V, X7R, 0603

Manufacturer

Part Number

Panasonic

ECJ-1VB1H104K

Capacitor (open)
Capacitor, multilayer ceramic, 10 μF, 10 V, X7R, 0805

Murata

GRM21BR71A106KE51L

Capacitor, multilayer ceramic, 9.1 pF, 50 V, NP0, 0603
Capacitor, multilayer ceramic, 0.10 μF, 16 V, X7R, 0402
Capacitor, multilayer ceramic, 10 nF, 25 V, NP0, 0603
LED, red diffused, 6 millicandela, 635 nm, 1206
Schottky diode, 30 V, 0.5 A, SOD-123
Header, 10-way (2 × 5), shrouded, polarized
Mini power jack, 0.08”, R/A T/H
Open
Header, 12-way (2 × 6), socket, unshrouded
Header, 2-pin, unshrouded, 2-jumper, 0.10”(use Tyco shunt, 881545-2)
Header, 10-way (2 × 5), unshrouded
Header, 3-position, SIP
Stereo mini jack, SMT
Inductor, 1.2 nH
Chip ferrite bead, 600 Ω @ 100 MHz
Chip resistor, 100 Ω, 1%, 100 mW, thick film, 0603
Resistor, open

MurataPanasonic
TDK
Lumex
ON Semiconductor
3M
Switchcraft, Inc.

GQM1885C1H9R1CB01D
ECJ-0EX1C104K
C1608C0G1E103J
SML-LX1206IW-TR
MBR0530T1G
N2510-6002RB
RAPC722X

Sullins Connector Solutions
Sullins Connector Solutions

PPPC062LFBN-RC
PBC02SAAN

Sullins Connector Solutions
Sullins Connector Solutions
CUI Inc.
Jaro Components, Inc.
TDK
Panasonic

PBC05DAAN
PBC03SAAN
SJ-3523-SMT
HFI-160808-1N2S
MPZ1608S601A
ERJ-3EKF1000V

Chip resistor, 0 Ω, 5%, 100 mW, thick film, 0603

Panasonic

ERJ-3GEY0R00V

Chip resistor, 2 kΩ, 1%, 100 mW, thick film, 0603
Chip resistor, 49.9 kΩ, 1%, 100 mW, thick film, 0603

Panasonic
Panasonic

ERJ-3EKF2001V
ERJ-3EKF4992V

Chip resistor, 10 kΩ, 1%, 100 mW, thick film, 0603

Panasonic

ERJ-3EKF1002V

Chip resistor, 1 kΩ, 1%, 100 mW, thick film, 0603
Chip resistor, 147 kΩ, 1%, 100 mW, thick film, 0603
Chip resistor, 169 kΩ, 1%, 100 mW, thick film, 0603
Chip resistor, 140 kΩ, 1%, 100 mW, thick film, 0603
Chip resistor, 49.9 Ω, 1%, 100 mW, thick film, 0603
Slide switch, SPDT, PC mount, L = 2 mm
Slide switch, DP3T, PC mount, L = 4 mm
Mini test point, white, 0.1” OD
SigmaDSP codec
Adjustable low dropout voltage regulator
SMD oscillator, 12.288 MHz, fixed, 1.8 VDC to 3.3 VDC

Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
E-Switch
E-Switch
Keystone Electronics
Analog Devices
Analog Devices
Abracon Corporation

ERJ-3EKF1001V
ERJ-3EKF1473V
ERJ-3EKF1693V
ERJ-3EKF1403V
ERJ-3EKF49R9V
EG1271
EG23055002
ADAU1361BCPZ
ADP3336ARMZ
AP3S-12.288MHz-F-J-B

Rev. 0 | Page 10 of 12

Evaluation Board User Guide

UG-119NOTES

Rev. 0 | Page 11 of 12

UG-119

Evaluation Board User Guide

NOTES

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions
By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions
set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc.
(“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal,
temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional
limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term
“Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including
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not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees topromptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any
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