VISUALSIM TRAINING

Training: Planning, Modeling, Simulation, Advanced Features
Planning
Goals &Requirements

Tasks orOperations

Workloads orTraffic

Hardware or
Platform

Collaboration& Sharing

DataManagement

SupportLook & feelFlow- System,
Beh-Arch,
Data flow

Performance
Power
Functionality

Hierarchical/
Class/ DI
BlocksTraffic/
Results

Hardware/
Software/
Network

Abstraction

Algorithms

Task Graph

Checking

Graphical/
Batch/ MultiCore

Debugging/
Verification

Requirements

PostSimulation

Types of Plots

Advanced
StudiesAccuracy

CompareGeneration

Encryption

Modeling
Parameters/
Variables/ DS/
FieldsSimulation and Analysis
Types ofStudiesParameterRanges

Advanced Features
FailureIntegration

Agenda- Part 3: Simulation and Analysis
 Types of Studies
 Batch Mode/Multi-Core Simulation
 Debugging
 Verification
 Requirements
 Advanced Studies
 Accuracy

Types of Studies

Behavioral Studies
Behavioral Studies: When studying the behavior of a system, we might focus on functional
aspects such as how different components interact with each other to achieve specific tasks.
Blocks representing functionalities or modules within the system could be analyzed tounderstand their behavior under different conditions or inputs.

Architectural Studies
In architectural studies, the emphasis is on the structure and organization of the system. This
involves selecting appropriate components and arranging them to meet the system's
requirements while optimizing for performance, power, cost, etc. Components like processors,
memory, and interconnects are essential in architectural studies as they define the overallsystem architecture.

Network Studies
Network studies involve analyzing the communication infrastructure within a system, including
data flow, bandwidth requirements, latency, etc. Components such as interconnects, interfaces,
are critical in network studies as they determine how data is transmitted and routed within thesystem.

Workload Analysis
Workload analysis focuses on understanding the patterns of resource utilization within a system.
This includes analyzing the types of tasks or processes being executed, their frequency, and theirresource requirements. Traffic patterns and processing activities on components like processors
and memory are important considerations in workload analysis.

Performance Analysis
Performance analysis involves evaluating the efficiency and effectiveness of the system in termsof its speed, throughput, latency, etc.
Components such as processors, memory, and interconnects are analyzed to identify potential
bottlenecks and optimize system performance.

Event Driven Simulation

Discrete-Event Simulator and Block Execution

Models of Computation

Discrete EventSimulator Object

Synchronous Data Flow
Simulator Object

Analog Simulator
ObjectTimed Simulation

Untimed DSP Algorithms

Analog Simulation

Batch/Multi-core Simulation

Assemble a Model with Architecture andBehavior

Model Location:$VS/demo/Software_Devl/software_methodology/software_tasks_w_Power_Requirement_Batch.xml

Post Processor to run multi coresimualtion

Configure Model  select model with PlotManager
Add PlotManager -- > Set Plot_Path

Post Processor to View Simulated Results

Open Plot Index

Select Parameters and Select plotFAQS regarding batch simulation
1. How do we run a batch simulation by changing parameters that are not at the top level?
The Post Processor only recognizes the top level parameters. This is to make sure only the key or parameters ofimportance are used. User has 2 options
a.Bring the hierarchical parameters to the top level. Thiscan be done by creating new parameters at the top level
and linking them to the hierarchical parameter.

Continued….
b. Manually edit the batch script (Sim_Batch_Run.bat/.sh) which was created by post processor. We can configure
the parameters within hierarchical blocks or even block parameters by following the format shown below:- Hierarchical Block Name.Parameter Name (Eg: -TG.Input_Rate)

Continued …
2. The post processor seems to only have options for Range and step. How do I specify discrete set of values?
For defining discrete set of values, user can define the values separated by comma in the “Range” and keep“Step” as -1

Continued …

3. Batch simulation does not print out the system stats from all blocks like DRAM controller. How do we enable this?
When we configure the model using Post Processor, user need to enable “Save” option for the text displays andplotters that are required.

Continued ….
4. If we want to send statistics or any data to the system stats module globally, how do we do this?
Send the stats to Architecture Setup block
We need to have Architecture_Setup block in the demo model. We can send the statistics to the Architecture_Setup
block by using a RegEx called sendStatsToArchSetup(). The format is:
sendStatsToArchSetup(<Architecture Setup Block Name>, Statistics)

Debugging

Various methods to Debug a particularmodel• Trace Tracking• Variable Dump

• Animation• RegEx• Listen to Port

• Script Debugging• Listen to Block• Data Structure Fields• Listen to Simulator• Plotters & Text Display• Digital Debugger• Error Messages

Debugging ProcedureDuring and End of Simulation
1.

Error Message◦
Identify the block listed in the Error Description and the Block Highlight in the block diagramview◦
Review Possible Solution description to resolve

2.

Listen to Block to see if the sequence of execution is correct3.

Listen to Port to see if the input and output field values are correct

4.

Variable Dump block and see the values of the memory

5.

View Command Line at the end of the simulation for the summary of total Simulator events,synchronous event, asynchronous mix events, time taken and memory used

Follow the Data Flow
If TextDisplays has no output◦ Check the block before it and follow up with each prior block◦ Listen to Port to check the output values

Make sure the transaction is arriving from the correct source and going to expected destination
Does the Transaction ID sequence make sense?
Any special Transaction flags set, indicating mode of operation that is inconsistent with current
blockAnimate Execution• To view the dynamic operation of the model• The Executing Block gets highlighted• The time to highlight a block is in milliseconds•

To Start Animation:
Debug -> Animate Execution• To Stop Animation:
Debug -> Stop AnimatingText Display, Plotters, Statistics• To graphically display and analyze data collectedfrom the simulation.
• Helps to detect any errors in the behavior• Statistics Generators - Generates statistics of all
resources and hardware blocks• Extracts the appropriate fields in the data structureor the entire object and display them.
• Plotter – Latency, throughput, etc• Text Display – Entire Data Structure, any value
coming in the input port

Statistics to Identify Behavior Errors
Resource statistics

Architecture Setup

Listen to Port
• Displays each token passing through the port
• Used to check whether the data is flowing through the particular port
• If no data on the "Listen to Port" window , it indicates that the model did
not generate any output from that block.
• If there is no data, then one needs to check the ports, or virtualconnections driving this block to see that they are being activated correctly.
• Helps to debug errors in connections, routing and conditional branches.
•Usage• Right click the required port and select Listen to Port

Listen to Block• Gives more insight into the internal block operation• Shows the sequence of execution, entry/exit, virtualSend, threads
Support coverage• All blocks except• Hierarchical blocks• instantiated hierarchical class• Provides simulator level information relative tomethods being fired, and so on. Simulator information
is most useful for evaluating custom blocks in thesimulation environment.
• Right click on the block and select Listen to BlockError Message
Message• Highlight Error Block• And Error Message

Mirabilis Design Inc.

32

Fields of the Data Structure• Each Data Structure (DS) has header fields thatprovide information as to its source, ID increment,and time created.
• Traffic field list the originating block• ID indicates the sequence of generation• TIME is a generation time stamp• These are valuable clues if a request does not
arrive or arrives out of order.

Time and Task Tracer fields• Set of arrays that are updated with the name and time stamp every time theData Structure enters or departs a Resource or Architecture block.

Memory Dump/Variable Dump
• This outputs the current value of all the global andlocal variables in the model• The output is a data structure with each field
representing one of the memories.
• Full Library ->Model-> Utility-> Checkers->
Variable_Dump

RegEx• Provides status and visibility into resource andhardware blocks in the execution flow.

✔readAllVirtual( ) - Provides the List of virtual Blocks in the model.

✔readAllMemory( ) - Provides a output of all local and global memories and their current value.
✔getBlockStatus( ) - The statistics for the blocks are generated using the getblockStatus RegEx
function with the type, length, stats etc.,✔getResourceActivity( ) - Used to access the information in the database block. It returns anarray of the current queue length of the resources listed in the named column.

Script Debugging•Right Click on Script -- > Customise -- > Configure•This will list down the parameters

Script Tracer• Enables the capture of execution of multiple Scripts fromone location and the content is written to a field.
• Helps to check the interaction between scripts and if thesequence of execution of instructions is correct.
• Data is written into a file called VisualSimTraceLog.txt which
can be seen under users/user folder/.VisualSim/

Listen to Simulator- Digital Debugger• Provides a sequence of execution for theselected simulation.
• Integrated with Digital Debugging utility inthe Digital simulator.
• This window displays the usage statistics,
current block execution, and modelsummary information.
• Debug -> Listen to Simulator

Digital Debugger parameters• Off – Disables the Debugging Mode
• Pause – Turns the Debugger to Stop at every block in the model Flow. Provides summary at the endof Simulation• Run – Records the order in which each block is fired in the model. Provides summary at the end ofsimulation.

• Summary Only – Generates the List of all the blocks at the current level of simulation and the levels
below

For each Block✔ Records the number of time each block is fired in the model✔ Average execution time for each firing✔ Total time spent in each Block✔It also lists the Blocks that are not executed in the modelPause and Resume• Saves the simulation data, events and status in a file• Handy to debug simulations that run for a large period of time.
• User can analyze system behavior at various points in the simulation.
• User can pause at a timestamp and analyze the system response and continue simulation step by step from that pointonwards.
• The system can be analyzed for required functionality and also helps the designer to identify if the crucial tasks arebeing executed within the deadlines.

Verification

Latency Measurement and identifying thebottleneck
Using Time Array and Trace Array :1.

The Time_Array gives the timestamps at which the packet reached a particular Block and the Block names
are given by the trace array.

2.

This information can be used to identify latency bottlenecks

3.

The same information can be written to an excel and this process can be automated using a Script blockCase Study – latency Induced bandwidth loss Consider a flow where the packets travel from Block 1 to Block 4.
 Although most part of the Latency seems to be due to Block4, Block1 has a linearly increasing latency.
 The Packets are getting buffered at Block 1 itself without being immediately transferred to the next nodes.
 There is a possibility to achieve a better throughput if can transfer the packets without buffering, depending on thedestination data size, processing speed and buffer size.
 But buffering it at the source reduces the maximum achievable bandwidthPower Verification
Using Power Log from third port of power table – explained in Power Modeling PPTUsing the VCD Dump obtained by executing the systemVerilog testbench generated out of
VisualSim in an EDA tool that supports systemVerilog.

Case 1: VCD can be used to verify whether the Block is switching it’s PowerState as expected and also thedelay between tranisitons due to capacitancePower Verification - Power State Coverage

Case 2 : VCD can be used to verify whether the test case is covering all the possible States for a given domain/block. Thisis important because for the verification to be complete, all the power states with their power consumption andtransitions have to be verified.
In this particular case, we can notice that the test case does not cover the states 3,4 and 6.

Requirements

Diagnostic Block – Add Design Constraints

Model Location:$VS/demo/Software_Devl/software_methodology/software_tasks_w_Power_Requirement_Batch.xml

Requirements/Design Constraints Input

Design Constraint Example

Requirements CSV – How to Populate?
Min, Max, Mean
(Average), All(instantaneous)values are supported
Constraint can be any ofthese options
1. If Using Variables that are manipulated Script/ExpressionList,declare them as Global variables within the Model and use“Global” for BLOCK Column
2. If Using Standard Block, add the Block name underBLOCK

1. All the Variables can beused here
2. Only Latency, Buffer
Occupancy and Utilization aresupported

Requirements Output
CSV Path :<Model_path>_results

Failing Case :BUS1_Clk_Speed= 200,
BUS2_Clk_Speed = 200

Passing Case:
BUS1_Clk_Speed= 400,
BUS2_Clk_Speed = 400

Conduct Parameter Sweep

Different parameter combinations based on theconfigured ranges are generated and simulated

Diagnostic Block – Requirement tracker output forparameter sweep••Requirements being evaluated for each simulation
run in the parameter sweep

Run number 19 – clock
frequency at 1000 MHz satisfied
the performance requirements
we had set.
Since the frequency wasincreased from 600 MHz, thetotal power consumption went
up while running the system at1000 MHz• Architect can evaluate
different processing
resources – DSP vs Fabricvs cores vs AI Tils if they
have stringent power
thresholds

Overall Results – We can identify the simulation runs which meet therequirements and select the right configuration after considering cost vsperformance trade-offs

Accuracy

VisualSim Accuracy (Performance-level)
Deficit RR-based Router◦ (Simulated vs. expected)◦ 100% for throughput, latency & algorithm◦ Input and output rates matched

MPEG Encoder on TI DSP (Software model)◦ Customer Feedback◦ 100% matched DSP utilization◦ 98% of time for end-to-end latency

VisualSim Bus Accuracy (PCI)
Burst 64

ActualVisualSim

Accuracy

Latency

2.16 us1.97 us91.29%

Throughput

107 MBps

111.3 MBps

95.92%

Burst 32

ActualVisualSim

Accuracy

Latency

1.20 us1.06 us88.33%

Throughput

96 MBps

102 MBps

93.75%

Data 256

Data 128

VisualSim Power Accuracy (Architecture-level)
Power Consumption◦ MPEG II running on ARM 7◦ Tested on Samsung KS32C50100◦ With SRAM, accuracy was 86%◦ Actual= 217 vs. VisualSim=188 mW◦ With internal Cache, accuracy was 89%◦ Actual=180 vs. VisualSim=199 mW

ARM Cortex M4
Run Detail

ARM Model – Latency(Cycles)

VisualSim Model - Latency(Cycles)

Delta (%)

M4 with AHB Cache – 2KB

150471150121

0.232

M4 with 0 wait state SRAM

84254

81293

3.5

M4 with 4 wait state SRAM

296931333203

12.2

ARM Cortex A53
BenchmarkFPGA

VisualSim

Difference

Comments

ED1

5.94ms

6.425ms

7.55%

Integer processing

MM

12.084ms

11.863ms

1.08%

Most load operations withrandom addresses

MM_st13.984ms

14.65ms

4.5%

Most store operations withrandom addresses

Test System
Xilinx Ultrascale+ Zynq® UltraScale+ XCZU9EG-2FFVB1156E MPSoC running on the ZCU102 board
Specification: 4 core ARM Cortex A53 at 1200Mhz; 32KiB i-cache; 32KiB d-cache, 1MiB L2; 2GB DDR4DRAM 2400

Comparing Power for ARM Cortex A53
Frequency

Simulated PowerReal (Measured) Power

Delta percentage

500.0 Mhz

0.037 W

0.038 W

2.63%

600.0 Mhz

0.053 W

0.051 W

-3.92%

700.0 Mhz

0.073 W

0.080 W

8.75%

800.0 Mhz

0.097 W

0.090 W

-7.77%

1000.0 Mhz

0.157 W

0.159 W

1.25%

1100.0 Mhz

0.193 W

0.188 W

-2.65%

1200.0 Mhz

0.233 W

0.227 W

-2.64%

1300.0 Mhz

0.277 W

0.269 W

-2.97%

Source: Anandtech.com
Over 97% accuracyComparing different Cores- Dhrystone
Processor

Instructions

Latency

Max MIPSARM Cortex A53~ 56,66,0000.0055846~ 1039ARM Cortex A77~ 44,78,0000.0011795~ 3960

RISC-V u74~ 60,58,0000.007726~ 797

Processor

MoP HitRatio

MoP Mean
Latency

I1 Hit Ratio

I1 MeanLatency

D1 HitRatio

D1 MeanLatency

L2 HitRatio

L2 MeanLatency

DSU HitRatio

DSU Mean
Latency

ARM Cortex
A53--99.97

1.93E-09

99.98

2.02E-09

18.75

9.33E-08--

ARM Cortex
A77

99.90

1.75E-09

67.22

6.25E-08

99.96

7.32E-10

14.19

1.82E-07

6.96

2.05E-09

RISC-V u74

--

99.98

4.15E-09

99.98

1.86E-09

39.58

5.25E-08--

Cycle Accurate Vs Stochastic DRAM –Accuracy Comparision
Cycle Accurate DRAM

Flow_Latency

Stochastic DRAM

DeltaMinMax

Mean

MinMaxMean

MinMaxMean

0.002360.009408

0.005789

0.002270.010197

0.0058332%8%1%