VisualSim Training

Training: Planning, Modeling, Simulation, Advanced Features
Planning
Goals &
Requirements

Tasks orOperations

Workloads orTraffic

Hardware or
Platform

Collaboration& Sharing

Data
Management

SupportLook & feelFlow- System,
Beh-Arch,
Data flow

Performance
Power
Functionality

Hierarchical/
Class/ DI
BlocksTraffic/
Results

Hardware/
Software/
Network

Abstraction

Algorithms

Task Graph

Checking

Graphical/
Batch/ MultiCore

Debugging/
Verification

Requirements

PostSimulation

Types of Plots

Advanced
StudiesAccuracy

CompareGeneration

Encryption

Modeling
Parameters/
Variables/ DS/
FieldsSimulation and Analysis
Types ofStudiesParameter
RangesAdvanced Features
FailureIntegration

Agenda- Part 2: Modeling Basic Components for hardware modeling Performance, Power and Functionality
 Performance and power Metrics
 Library components and important parameters which affectperformancePerformance, Power and Functionality
 VisualSim provides an integrated solution for performance, power and functionalmodeling The details regarding Power modeling have been dealt in a separate presentation
 The functional modeling aspect is covered in modeling the task graphs section
 The user can also perform functional verification by observing the input, output
values, checking for their correctness
 Custom algorithms or functional flows can also be define dusing the Script BlockBasic Components for Hardware ModelingArchitecture Library Overview•Generate architecture with parameterized blocks•Define hardware and software components•Create proposed or derivative architectures in few
minutes•Rapidly define application flow diagram and behavior•Optimize architecture and functionality mapping
combination

Hardware Modeling LibraryBasic Components to define
1. Hardware modeling requires Architecture_Setup block - has the routing information of all hardware
blocks in the model
2. If using Traffic or other custom block to connect to a Bus, use theDevice_Interface block in front of the
Bus port.
◦ Also true for AXI, PCIe and NoC◦ Not required for Standard Blocks Like Processor

3. Processor block requires Instruction_Set

ArchitectureSetup Block givesout statistics for all the
hardware blocks in the model

Use of Device Interface

Processor Blocks with
InstructionSet

Architecture Setup
All Bus and Hardware block must associate with Architecture Setup
This Block Handles⮚Routing⮚Plotting⮚Statistics⮚Debugging for all the Hardware components

1. There can be multiple architecture setup blocks
2. Each block must have unique nameNote: this Block can be used as it is after updating the Architecture_Name field
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Custom Routing Table Construction - in Architecture Setup
Format Sample:
Source_Node

Destination_Node

Hop

Source_Port

SourceProcessor

Destination
DRAM

Next Block
Port_1

Out Port
bus_out

Add entries using RegEX
addToRoutingTable (Architecture_Name, Source_Name, Destination_Name, Hop_Name, Source_Port_Name)

Delete entries using RegEX
removeFromRoutingTable (Architecture_Name, Source_Name, Destination_Name, Hop_Name,
Source_Port_Name)
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DeviceInterface Block• Can be used to define the Source Name, data
size, command type and destination for a Master• Can be used to define the Device name on the
Slave side
• Add the Master or Slave block to the Linear Bus,
Bridge and AHB Buses automatically✔ Generate Hello Messages✔ Eliminates the need for a RegEx functions or
manually generate Hello message• Map fields of other data structure formats to thecorresponding fields of the Processor_DS• Used to connect only in the presence of the
Linear Bus, AHB and bridge blocks.
• Not useful with a single AXI or a single PCIe

Set field values here or
keep default to use
existing field values

Stochastic Components in the Library

Concept of System Resource
Concept◦ Split operation into two parts◦ Behavior or mapper◦ Resource (similar to Server)

Blocks◦ Behavior: Mapper, SoftwareMapper, DynamicMapper◦ Architecture: SystemResource_Extend, SystemResource◦ Notify: SystemResource_Done

Multiple concurrent requests

Architecture
Behavior◦ Send from Mapper (Behavior) to the SystemResource with the delay
information◦ Can be static or dynamic reference◦ Scheduler: First Come-First Serve, Round-Robin, Preemption, NonLocking

SystemResource_Done block◦ Release appropriate SystemResource_Extend block by signaling thecompletion of an external task

SoftwareMapper

DynamicMapper

12Mapper to System Resource•

Mapper blocks define the connectivity between the behavior flow and the architecture flow,
and within the architecture flow using a named connection• The block takes the incoming Data Structure and send it to the Scheduler virtually• This block can send a request to either the SystemResource or SystemResource_Extend.

SystemResource_Extend

HW
SW

RequestTask
IN

MapperMapperTC

SystemResource_Done

System_Resource
Task
Done

System ResourceThis is the name of this
SystemResource block and is used byMappers, RegEx and other
SystemResource block to call thisblock to execute a transaction.

Next_Resource is the name of thenext hierarchical System Resource,which can be SystemResource or
SystemResource_Extend block.

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System Resource (Cont.)
Time the scheduler will devote toeach task for Round Robin

Application comparisons

Set Scheduler type from the rangeof schedulers

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System Resource Extended- Double click to configure

Application comparisonsMirabilis Design Inc.

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ReturnWhat is Mapper?

Connect behavior flow with architecture resources▪ Takes incoming Data Structure and sends to▪ SystemResource▪ SystemResource_Extend blocks▪ Placed in the behavior flow where timed resources required▪ Consumes zero time, no queue, no arbitration
Mapper

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Software Mapper

Hardware or Software Task issuer▪ Sends tasks to SystemResource or SystemResource_Extend based on Target_Resource▪ Block can either Queue incoming Data Structure or send to SystemResource immediately

Attributes to issue
the task to
System Resource

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Lock out all other tasks frompreempting this Task at the
SystemResource

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Example Model 1 – System Resource

3 tasks competing for thesame resource$VS/doc/Training_Material/Tutorial/General/System_Resources/Scheduler_Sw_2.xml

Plots and Stats for Example Model 1

Tasks are notconcurrent

Different Types of Scheduling Algorithms in SystemResource

Scheduler_FCFS

Scheduler_RR

FCFS+ Preempt – Start at different times with Context Switching- 1 Sec

Scheduler_FCFS+PreemptExample Model – System Resource Extend

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QueueProvides the priority number
for reordering the queue.

Set how the packets shouldflow

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ReturnQueue – First Token Flow ThroughTime = 0.0

Time=200
Time=300
Time=500
Time=700
msec
Time=600
Time=400msec

Packet– P1

P1
Queue=
1

Packet– P2

P2
Queue=
1
P3
Queue=
1

Packet–P3
P7Time=100 msec
“Queue”
Queue Number = 1
P1
P2
Position=
1
P3
Position=2
Position=
P4
3
Position=
P5
4 osition=
P
P6
5
Only first packet goes out without
any pop input. Other packets need
pop input

P1

P7
RejectedQueue – First token Enqueue• pop_input is required to send all the packets including thefirst one

Multiple number of Queues

Internally, it look like this“Queue”

Pos=
1
Pos= 2
Pos= 3
Pos= 4

Q Num=1 Q Num=2 Q Num=3
P1
P5
P3
P2
P4

Pos= 5

pop_input value can be 1, 2 or 3

Queue Operation - Summary•••

Data Structures are queued based on priority from high to low number
Data Structures in the queue are arranged based on FIFO or LIFO setting
Number_of_Queues defines the number of parallel queues contained by asingle Queue block• Queue Number Field selects the queue to place• To pop a packet– From the head of a queue, Queue_Number must be sent to pop_input port.

• When Maximum_Queue_Length is reached, packets are Rejected based on
Rejection_Mechanism and sent to Reject_output• Based on initial Queue State parameter,– Enqueue: First Transaction can be enqueued and wait for the pop– First_Packet_Flow_Through: First transaction send without pop. After first packet, head ofqueue sent if prior was acknowledged with pop

Server• Define multiple {queues + time delay}• Active Resource• DataStructures queued in FIFO or LIFO order• Processing time is known in advance• Provided along with the transaction to this block.
• SLOT• Special operation mechanism• Models any slot-based architecture such as multiple
virtual RTOS, TDMA etc.

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Server

Server has a special
parameter called “Timefield” to delay head of queue
before sending out

Number_of_Queues can be
multiple in the Server as wellMirabilis Design Inc.

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Server - Summary• Queue_Number_Field selects the queue• Queue is reordered based on Priority field• Queue data in FIFO or LIFO based on Queue_Type• Delayed by Time_Field value at head of queue andsent out• Packet is sent to reject_output when
Max_Queue_Length reachedPerformance and Power Metrics• Common Statistics✔ End-to-end latency and Task Delay✔ Throughput (MIPS or MB/s), Utilization (%)✔ Minimum, maximum, mean and standard deviation statistics✔ Power – Instantaneous, Average and Cumulative✔ Battery – Current Capacity(Watt - Hr), Battery Life Remaining (%)• Processor✔ Individual statistics for Caches, Execution Units and Pipeline Stages✔ Flush Time, Stall (%), Thread swaps and Context switching✔ Listener for Real-Time pipeline activity• Cache✔ Hit-miss Ratio✔ Requests, utilization, evictions, prefetches and latency and throughput

Hardware Statistics
Name

Value

Name

Value

Bus_1_Utilization_Pct_Max

10.1,

Bus_1_Delay_Max

3.600004E-8,

Cache_1_Utilization_Pct_StDev

1.05689435, Bus_1_IOs_per_sec_StDev

634428.24721,

Processor_1_D_1_Utilization_Pct_Max

1.45,

32.0,

Processor_1_INT_1_Utilization_Pct_StDev

0.10969973, Bus_1_Preempt_Buffer_Occupancy_in_Words_StDev

Processor_1_INT_2_Utilization_Pct_Max

24.55,

Processor_1_I_1_Utilization_Pct_StDev

0.01500007, Cache_1_Delay_Time_StDev

Processor_1_L_2_Utilization_Pct_Max

3.1,

Processor_1_PROC_Utilization_Pct_StDev

0.03489914, Cache_1_Memory_Used_By_Processor_1_MB_StDev

Processor_1_Pipeline_Utilization_Pct_Max

Bus_1_Input_Buffer_Occupancy_in_Words_Max

Bus_1_Throughput_MBs_Max

Cache_1_Hit_Ratio_Max

Cache_1_Memory_Used_By_SDRAM_1_MB_Max

50.2,

Processor_1_Register_Rd_Utilization_Pct_StDev 0.19330594, Cache_1_Memory_Used_By_Total_MB_StDev

Name

Value

Processor_1_D_1_Hit_Ratio_Max

100.0,

Processor_1_D_1_KB_per_Thread_StDev

0.0,

Processor_1_I_1_Hit_Ratio_Max

100.0,

Processor_1_I_1_KB_per_Thread_StDev

0.0,

Processor_1_L_2_Hit_Ratio_Max

100.0,

176.0,

Processor_1_L_2_KB_per_Thread_StDev

0.0,

1.499871E-8,

Processor_1_Stall_Time_Pct_Max

1.35,

100.0,

Processor_1_Task_Delay_StDev

2.9502E-7,

SDRAM_1_Delay_Time_Max

1.5E-7,SDRAM_1_Memory_Used_By_Processor_1_MB_StDev

0.0,

SDRAM_1_Memory_Used_By_Total_MB_Max

2.56E-4,

SDRAM_1_Throughput_MBs_StDev

0.0,

0.0,

8.455181E-5,
2.56E-4,
8.455151E-5,

Processor_1_Register_Wr_Utilization_Pct_Max

49.55,

Cache_1_Throughput_MBs_Max

116.0,

DMA_IO_per_sec_Max

7.45E6,SDRAM_1_Utilization_Pct_StDev

1.91E-07

Processor_1_Context_Switch_Time_Pct_StDev

0.0,

DMA_Throughput_MBs_StDev

3.463999999,

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Analyzing Performance in VisualSim – Important Parametersin Library ComponentsHybrid Processor

Unique Name

Processor
Key Parameters to modify

Required

Number of
Pipeline
Stages isimportant

Outstanding_Req_Count is used
for External CacheProcessor – Internal Cache Configuration

Micro Architecture details – Number
of Registers, ROB size, Number ofRegisters

Hit_Ratio bydefault will be
0.99

Mention next Level
Cache to beaccessed in case of
missesProcessor Instruction Set

Processor name

Execution and LoadStore Units within
RISCV and thecorresponding
instruction groups
they execute

begin execUnit_config
Queue_Size INT_1
Queue_Size INT_2
Queue_Size INT_3
Queue_Size INT_4
Queue_Size INT_5
Queue_Size FP_1
Queue_Size FP_2
Queue_Size INT_6
Queue_Size INT_7
end execUnit_config

Instruction Group

Instruction width in bits canvary for different load/store
instructions

16
16
16
16
16
16
16
12
12

;
;
;
;
;
;
;
;
;
;
;

Queue_Sizefor each
InstructionGroupExample of Pipeline usage

A condition can be
specified forExternal Resource

There can be multiple rows for each pipeline
stage, but the last row number should be equal to
the Number_of_Pipeline_Stages

Execution_Location can be:
1. Internal to the Processor (configured inProcessor_Setup)
2. External Resource (typically a System Resource Block )

1.

2.

3.
4.

5.

Req port receives request fromthe source (Traffic generator inthis case). It will be connected to
DeviceInterface
Ack port will have transactions
received with additional fields
like Time_Array, Trace_Arrayuseful for debug
Ack and Din are connected tothe output blocks via
DeviceInterface or directly
Dout carries response from
output devices like Memory.
Connected to Bus,
DeviceInterface or Memory
Dout will have Task_Latency andTask_Throughpout as additional
fieldsUse Input (none) while using data
structure and database name whenusing DMA database
Required

Per channel, num sent before Ack

Input toDMA blockIf the user wants to define actions for the DMA from Data
structure fields, then above fields are necessary

DMA Controller Block

Match input fields

Sequence
Operation

Destination

Send asBurst size

ChannelNumberTransfer
SizeModel Location :$VS/doc/Training_Material/Tutorial/Architecture/DMA/DMA_Demo_Model_Field_n_DB.xml

Model Location :$VS/doc/Training_Material/Tutorial/Architecture/DMA/Processor_DMA.xml

Unique Name

Required

List all devices connected via
this port. Index is in order ofname- Port_1, Port_2 etc{Read, Write}

Model Location :$VS/doc/Training_Material/Architecture/AHB_AXI/Bus_Arbiter_Read_Write.xml

1. Source (master devices that request data) like Processor and DMA (standard blocks) have to be connected to the masterports via TileLink_Client (Library -- > Interfaces and Buses --> Tilelink --> TileLink_Client)2. If the Master device is designed with simple library block (as logic) then user has toinclude Device Interface block to provide the interface with master.

3. If the TileLink_Client is connecting to another BUS like PCIe or AMBA-AXI, then the user has
to use a Bridge ( Library --> HardwareDevices --> Bridge)

Required

TileLink_Clientrefers to how many times a TileLink client will attempt tosend a burst of data to a target device before giving up
and retrying the transaction.

All thefields are
Required

TileLink Block

TileLink_Manager
From Architecture Setup

Model Location : $VS/demo/Bus_Std/TileLink_Models/TileLink_RISCV_SoC_Approach.xml

Timing Diagram for TileLink Bus showing themessages that were sent during the transactions

Processor Stats

Channel wise Occupancy and
Delay for TileLink

• Support 16 masters and 8
slaves• Master and slave ports can beincreased if it is required. Eg:
AXI_16_x16 block• Master and Slave Ports :• Port type – Multi Port (input and output in asingle port)• Port data type – general• Support only 2 wire connection per port (input
and output)• Input ports: Accept read/write requests frommaster devices and forward read/write respons tomaster devices• Output ports: Forward read/write requests to slave
devices and accept read/write response from slave
devices.
• Stats_out: provide debug messages during thesimulation if “DEBUG” parameter is set.
• Plot_out: Not used in the current version.

• AXI_Speed_Mhz: Bus speed in Mhz• Bus_Width: Width of the AXI Data and response
channel• Read_Threshold: Total number of outstanding reads
in each slave ports.
• Write_Threshold: Total number of outstanding writes
in each slave ports if A_Task_Flag is true.
• Master_Request_Threshold: Input queue size ofmaster ports.

• Device_Attached_to_Slave_by_Port:
List of slave devices connected ineach slave port.
• Arbiter_FIX_1_RR_2_CUSTOM_3:
Arbitration algorithm for multi mastersingle slave cases. (fixed priority uses
Fixed_Priority_Array parameter)

Model Location : $VS/demo/memory/Cache_Demo.xml

• Support existing AMBA AXI protocol.
• Coherency can be enabled for specific masters• If coherency is not enabled for any master, bus acts likea AXI bus and performs non coherent data transfer• Coherency channels will not be used.

Lis of coherent masters in anarray.
Empty array is acceptable, andit implies none of the masters
are coherentModel Location : $VS/demo/Coherency/Snooping_Protocol.xml (2340 version)

••

Blocking
Delay is variable based on data size and speed

Unique Name

Bridge synchronization clock
Width of the bridge

Model Location :$VS/doc/Training_Material/Architecture/bus/AHB_AXI/AHB_AXI_Bus.xml

Blocking◦ Single interconnect◦ 4 connected Devices and can add more
◦ Single-cycle delay for Read and Multi-cycle delay for Write
Non blocking◦ Point-to-point mesh with multiple channels per wire
◦ Basic block contains for 4 device connections; Can be expanded◦ Single-cycle delay for Read and Multi-cycle delay for WriteWidth of the switch

Blocking or non blocking mode
Unique NameModel Location :$VS/doc/Training_Material/Architecture/Processor/Cortex_M0/ARM_CortexM0_Demo.xml

• Master devices can be connectedto the top multi ports of the block• Slave blocks can be connected tothe bottom multi ports of theblock• The packet can reach a slave
device that is in different
crossbar by hopping through thecrossbar according to theconfiguration in Crossbar_Setup
block.

Width of the crossbar
Crossbar QoS – Rate Regulation orBandwidth limitation
Buffer Size – Max number of frames thatcan be stored at the port interface
Routing option – Address based orinterleave (detailed configuration in
Crossbar_Setup)

Specifies the Crossbar routing andbandwidth configuration

Specifies the addressing parameters
and interleave settings

Model Location :$VS/demo/NoC/Crossbar/20220527_5M_4S_CX_Demo_Model_17.xml

Router

RN Array Path, RNI, HNI and SNF
Number of
Virtual channel

VC size anddevice interface
queue size
RouterCoordinates
Router width in
bytes

Interface buffer size

HN Array path
HNF cache nameModel Location : $VS/demo/networking/Noc/NoC_Demo_Updated.xml

NIU (Network Interface
Unit)
Flit Size in bytes

Switch (Router)
Request andresponse queuesize
RouterCoordinates

Wire
Routerconnections

Device Interface
and Virtual Channel
Buffer Size

Wire ID if power
enabledWire width in bits

Model Location : $VS/demo/NoC/Arteris/Noc_Arteris_Demo.xml

RNF, RNI, HNI and SNF

No of VC in the routerDevice buffer size

Packet Priority

XP (Router)
Size of Virtual Channel anddevice interface queue

HNF

Flit size in bytes
HNF input Queuesize

Bit error ratio
Number of VC

HNF cache size

Router Coordinates

Wire
Router connections

Delay cycle for flits

Model Location : $VS/demo/NoC/Corelink/CMN600_with_A77_DDR5.xml

Master and slave ports are multi
port connections.
Msg_out: provides debug
messages of PCIeStats_out: not used in the current
versionCan be common or array for each port in order starting from
top-left and continuing through top-right

Required: List of all the Devices
connected to each End-Point

Required: Determines speed

Model Location : $VS/doc/Training_Material/Architecture/bus/PCIe/PCIe_DMA.xml

Master and slave connections
use multi port for input andoutput.
Debug_port: provides debug
message of the PCIe6 bus

Maximum request size of a packet
Number of Lanes
Maximum bytes that can be
stored in Rx and Tx buffer
List of Devices connected to eachof the portModel Location : $VS/doc/Training_Material/Architecture/bus/PCIe6/PCIe6_Device
Interface2x2_base_model.xml

Integrated Cache
Integrated Cache can be used as L1(Instruction and/or Data), L2 and L3 cache in both stochastic andcycle accurate mode.
Stochastic Mode:◦ Hit or miss of input request will be determined by the instruction hit ratio/data hit ratio.
◦ If it is a hit, request will be processed and response will be returned to the source. If it is a miss, request
will be sent to next level cache or memory to fetch whole block of data, while the request is waiting in
the buffer,.
Address_Based Mode
◦ Hit or miss of the input request will be determined by the availability of the requested address in thecache.
◦ If it is a hit, request will be processed and response to the requested address will be returned. If it is a
miss, whole block of address range will be fetched from next block of memory and the request waitingin the buffer will be processed.
Flow control:◦ User can run the model either with flow control or without flow control. By default block will be used inwithout flow control.
◦ Input flow control can be achieved by including a field named “Event_Name” in the input data structure
and a TIMEQ to trigger the next request. The next request will be triggered only when the data isprocessed by the cache.
◦ Output flow control can be achieved by setting the “Output_Flow_Control” parameter as true.

Required Parameters• Outstanding_Requests• Number of Outstanding
misses and prefetches• Number of Hit before
Prefetch

Integrated Cache Statistics
Number of Statistics samples canbe generated during the simulation
time using the parameter“No_of_Statistics’Stochastic Cache
Emulate a cache in stochastic architecture mode where
addresses are not available- Used with hit=ratio
Handleso Request are Queued
o Measures actual Cache hit-miss ratioo Cache Prefetch,o Read/Writeo Cache miss activity to the next level of memory

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Configuration
Route the requests to the next level ofmemory to access when a cache missoccurs or a prefetch is requested

Number of outstanding requests thatneed to be processed

Cache_Speedis necessary

Expression for the cache hit using RegEx
language.
• true, then the task had a cache hit• else a miss occurred.

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Stochastic Memory

Required fieldIn ns for one width access
Activate & Overhead cycles
Value is expression, variable or
field

For SRAM, set to false

RAM
1. Models the memory controller and memory array
2. Handles◦ Read◦ Write◦ Refresh◦ Erase

3. Applications⮚ ROM, RAM, SRAM, DRAM or SDRAM⮚ DDR, DDR2, DDR3
⮚ SDR, QDR⮚ VRAM, Direct Rambus, PSRAM, SGRAM⮚ NAND and NOR flash

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Important Concepts
1. Controller Time – Scheduling + Activation▪ Cycle Time = 1/Memory Speed Mhz

2. Access Time▪ Access time for Read, Write, Prefetch and Erase is in nanoseconds
Example : Read 1000.0/Memory_Speed_Mhz▪ Default value▪ Read 5.0▪ Prefetch 6.0▪ Write 7.0▪ ReadWrite 8.0▪ Erase 9.0

Request goes as a Read,
Response returns as a Write

Read Operation
Input

Request goes as a Write,
Ack returns as a Read

Outputinputcc
output• The On chip network (pinksurface) is designed as per
the Mask R-CNN
specification• The Task Graph in thebottom defines the
behavioral flow for softwareand trigger the hardware
devices.

• Each of the layers are defined as
different tasks in the task graph and thedependency between them is modeled.
• A database is used to list thelayers/functions and the parameters
associated with them.
• These will be used to determine
the number of Multiply Accumulate(MAC) operations corresponding toeach layer/functionModel Location : $VS/demo/DNN /DNN_Model_Mask_R_CNN.xml