SHF Communication Technologies AG
Wilhelm-von-Siemens-Str. 23D • 12277 Berlin • Germany
Phone ++49 30 / 772 05 10 • Fax ++49 30 / 753 10 78
E-Mail: sales@shf.de • Web: http://www.shf.deDatasheet
SHF 12103 A128 Gbps Bit Pattern Generator

SHF reserves the right to change specifications and design without notice – SHF 12103 A - V007 – Sep. 13, 2012

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Description
The SHF 12103 A is a 128 Gbps bit pattern generator plug-in, which can be fitted into the SHF 10000
Series mainframes. It generates digital bit sequences such as standard pseudo-random bit sequences(PRBS) or user defined bit patterns at the data outputs. Many applications in research and development
require these data streams for testing electrical/optical components or transmission systems for highspeed digital data communication. A wide range of operating bit rates from 3-56 Gbps is covered by thegenerated data patterns. Depending on the configuration, the instrument features up to two 56 Gbps
and/or up to four 32 Gbps outputs. An optional skew control is available for all configurations of the subrate data outputs.
The operating bit rate is determined by a clock signal from an external clock source which is not part of thepattern generator. The dual 56 Gbps outputs can operate at both full clock and half clock, so either a28 GHz or a 56 GHz signal is required for 56 Gbps operation. The quad 32 Gbps outputs operate at fullclock, so a 32 GHz signal is required for 32 Gbps operation.

Features








Multiple synchronized but independent channels with high quality adjustable output signals
Broadband operation up to aggregated 128 Gbps
Eight built-in PRBS patterns and 1 Gbit user pattern memory to support user defined patterns
Skew adjustment for subrate outputs
Pattern hardware pre-coding for DQPSK transmission on subrate outputs
Frame trigger output
Operation by intuitive graphical user interface

Configurations and Options
Data Outputs

Subrate Data Outputs(Dual 56 in this example)(Quad 28 or Quad 32 in this example)

Configurations of Data Outputs
Single 56
Dual 56– One differential output from 6 to 56 Gbps (two outputs in total)– Two differential outputs from 6 to 56 Gbps (four outputs in total)

Configurations of Subrate Data Outputs

Dual 28
Quad 28
Dual 32
Quad 32– Two differential outputs from 3 to 28 Gbps (four outputs in total)– Four differential outputs from 3 to 28 Gbps (eight outputs in total)– Two differential outputs from 3 to 32 Gbps (four outputs in total)– Four differential outputs from 3 to 32 Gbps (eight outputs in total)

All combinations of full and sub rate data outputs are possible. A later upgrade to the higher bit rate limit
1at the sub rate outputs and retrofitting additional outputs is possible at any time .
Options

1SC2
SC4– Skew control for sub-rate outputs (dual-channel version)– Skew control for sub-rate outputs (quad-channel version)

In case the maximum number of outputs is not already exceeded.

SHF reserves the right to change specifications and design without notice – SHF 12103 A - V007 – Sep. 10, 2010

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Specifications
Parameter

Symbol

Unit

Min.

Gbps

6mV

600

Typ.

Max.

Comment56 Gbps Data Outputs
Bit Rate
Maximum Output Level(Eye Amplitude)

Vout

Jitter (RMS)

JRMS

fs

Rise/Fall Time

tr/f

ps56650350
290700adjustable by up to -3 dB
DC coupled groundreferenced CML interface

550515

measured at 56 Gbps
2on scope display
3
deconvoluted

10.6
1020%...80%
2
on scope display
4
deconvolutedCrossing

%

4650

54

at full output swing

Duty Cycle

%

4750

53

of two consecutive eyes
could be further optimized
manually by software controlConnector TypeΩruggedized 1.85 mm (V)male connector

50

28/32 Gbps Subrate Data Outputs
Bit RateGbps

328/32

Maximum Output Level(Eye Amplitude)

VoutmV900

Jitter (RMS)

JRMSfs450
4006005655053

Crossing%

Duty Cycle%

Connector Type

ΩRise/Fall Time

tr/tf

Inter-Channel Skew

474750depending on configuration
adjustable by up to -6 dB
AC coupled55350

measured at 32 Gbps
2
on scope display
3
deconvolutedof two consecutive eyes
could be further optimized
manually by software control
2.92 mm (K) female

ps12.61220%...80%
2
on scope display
4
deconvoluted%

10of bit period @ bitrate2

Measured with Agilent 86100A with 70 GHz sampling head and precision time base triggered by Clk or Clk/2 output

3

Calculation based on typical jitter from oscilloscope data sheet :4

Calculation based on typical rise/fall times from oscilloscope data sheet:

5For PRBS patterns only. Due to the AC coupling certain user patterns may result in eye amplitudes of up to 2 V.

√√
√

√

SHF reserves the right to change specifications and design without notice – SHF 12103 A - V007 – Sep. 10, 2010

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Parameter

Symbol

Unit

Min.

Typ.

Max.

Comment0+25

adjustable in 0.1 ps-steps

500
460

650620measured at 32 Gbps
2on scope display
3deconvoluted

Skew Control for 28/32 Gbps Subrate Data Outputs (optional)
Skew Control Range

Jitter (RMS)ps

JRMS-25

fsClockConnector TypeClock Input

ruggedized 1.85 mm (V)male connector
ruggedized 1.85 mm (V)male connector
ruggedized 2.92 mm (K)male connector
ruggedized 2.92 mm (K)male connector

Clock Output
Ω50

Clock/2
Sel. Clock Output

Clock Input Frequency

fin_clock

GHz

363

Input Level

Vin_clock

mVpp

600

Output Level
ClockClock/2
Selectable Clock

Vout_clockmVpp

fout_clock

GHzGHzGHz

Output Frequency
ClockClock/2
Selectable Clock

500500
500

600
600
600

31.50.003

2856
28/32
1000

half clock mode
full clock mode
sub clock mode

1000
1000
1000

AC coupled
AC coupled
AC coupled

56
28
14

same as input frequency
half of input frequency
input frequency/N(N= 4, 8, 16, 32, 64, 128,256, 512, 1024)

Pattern
ITU-T (CCITT) conform
PRBS patterns at a length of7
91011
15
2 -1, 2 -1, 2 -1, 2 -1, 2 -1,20
23
31
2 -1, 2 -1 & 2 -1 plus user
defined patterns

Output Pattern

User Pattern Memory
6SizeGbit

User Pattern Granularity

Bit1024

Connector TypeΩ

50

SMA female

Output Level FramemV800

AC coupled

1

Frame Trigger Output

6

See chapter User Pattern Capabilities for more details on the user pattern.

SHF reserves the right to change specifications and design without notice – SHF 12103 A - V007 – Sep. 10, 2010

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Block Diagram

The pattern generator consists of two 4x16 Gbps pattern generation blocks which are synchronized toeach other. The outputs of each pattern generation block are 2:1 multiplexed to generate two 32 Gbps
outputs. In parallel the outputs of each pattern generation block are 4:1 multiplexed to generate the56 Gbps outputs. In any configuration where 32 Gbps and 56 Gbps outputs are present at the same time,the 56 Gbps outputs will run at double the speed of the 32 Gbps outputs.
Up to 1 Gbit of user pattern will be stored in a 1024 bit wide memory. Each pattern generation blockincludes the multiplexers to generate the 4x16 Gbps data streams from the incoming 512 bit wide userpattern data.
The DQPSK precoders are part of the pattern generation blocks, so there is one DQPSK precoder forchannels A and C and another one for channels B and D.
The clock distribution section processes the incoming clock signal to generate the clock out, clock/2 out,
selectable clock out and word frame signals. Furthermore all clocks needed for the internal components
will be generated here.

SHF reserves the right to change specifications and design without notice – SHF 12103 A - V007 – Sep. 10, 2010

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Output Adjustment Capabilities

Controlling the quad 32 Gbps outputs

Controlling the dual 56 Gbps outputs

Data Rate
The data rate of all outputs is continuously adjustable by a single external clock signal applied to theappropriate input. The 56 Gbps data outputs are always running at a data rate of twice the speed of thesubrate outputs.
Output Amplitude
The output amplitude of each channel is adjustable independently.
Pattern TypeAll PRBS and user patterns can be assigned individually to each channel.
The patterns of the 32 Gbps subrate outputs are depending on the 56 Gbps outputs; or vice versa (pleaserefer to above block diagram). In case both, 32 Gbps and 56 Gbps outputs are used simultaneously each
56 Gbps output pattern will be virtually 2:1 multiplexed by two 32 Gbps outputs.
Inter-Channel Bit Delay
In case two or more PRBS patterns of the same length are selected it is possible to amend the starting
point of each bit sequence (in 1 bit steps up to the total PRBS length).
Inter-Channel Skew (optional)
The timing of each of the 32 Gbps subrate channels can individually be fine adjusted in 0.1 ps steps(please see chapter Skew Control Function for more details).
Duty Cycle
The duty cycle of two consecutive eyes/bits is automatically set to 50%. However, in case the application
requires a modification or a further optimization, this could be done with a few clicks.
Hardware DQPSK Precoding
When this checkmark is activated for a pair of 32 Gbps outputs it allows the user to run an error analyzer
in PRBS mode while transmitting the data in a DQPSK modulation scheme.
SHF reserves the right to change specifications and design without notice – SHF 12103 A - V007 – Sep. 10, 2010

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User Pattern Capabilities
The SHF 12103 A has a built-in 1 Gbit user pattern memory which is attached to the pattern generation
blocks by a 1024 bit wide interface to the pattern generation blocks. Data from the user pattern memory
will be multiplexed to generate the 56 Gbps and 32 Gbps output data streams. Thus the pattern length of
any user pattern uploaded to the user pattern memory has to be a multiple of 1024. User patterns not
fulfilling this prerequisite will be repeated automatically by the provided Bert Control Center (BCC)
software until the granularity of 1024 is met. For patterns up to 1 Mbit this is always possible. Patterns
larger than 1 Mbit have to fulfill the following prerequisites:
Pattern length up to1 Mbit
2 Mbit4 Mbit
8 Mbit
16 Mbit
32 Mbit
64 Mbit
128 Mbit
256 Mbit
512 Mbit
1 GbitPattern length has
to be a multiple of
1
2
4816
32
64
128
256
512
1024

To load individual user patterns for each channel, the patterns have to be merged to upload these into theuser pattern memory. This will be handled by the BCC software automatically. The user patterns of allchannels have to be of the same size. This will be achieved by the software by repeating the user pattern
for each channel until each pattern length is equal to the least common multiple of all patterns lengths.
With all patterns having the same length, the BCC software will merge the patterns and will repeat theresulting pattern as described above until the granularity of 1024 bit is met.

SHF reserves the right to change specifications and design without notice – SHF 12103 A - V007 – Sep. 10, 2010

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Skew Control Function (Optional)
The skew control function allows adjusting the channel timing relative to each other. This is an extra
feature on top of the integer bit delay that is already available. As a result, timing delay between individual
subrate output channels can be extended greatly over many bit periods, with the skew function for fineadjustment. The figure below shows the BCC control software with this feature, and an example of delay
between two subrate channels for skew within a bit and more than one bit.

+10 psBit Delay
Control

+5 ps

Skew
Control
0 ps+5 ps+5 ps+2 bits
Skew control software representation

Integer bit delay & skew control

SHF reserves the right to change specifications and design without notice – SHF 12103 A - V007 – Sep. 10, 2010

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Typical Output Waveforms
28/32 Gbps Data Output Signals

32 Gbps output eye at maximum output level

32 Gbps output eye at minimum output level

28 Gbps output eye at maximum output level

28 Gbps output eye at minimum output level

20 Gbps output eye at maximum output level

20 Gbps output eye at minimum output level

SHF reserves the right to change specifications and design without notice – SHF 12103 A - V007 – Sep. 10, 2010

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56 Gbps Data Output Signals

56 Gbps output eye at maximum output level

56 Gbps output eye at minimum output level

50 Gbps output eye at maximum output level

50 Gbps output eye at minimum output level

40 Gbps output eye at maximum output level

40 Gbps output eye at minimum output level

SHF reserves the right to change specifications and design without notice – SHF 12103 A - V007 – Sep. 10, 2010

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