REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVEDA

Update boilerplate to current MIL-PRF-38535 requirements. - PHN

18-04-16

Thomas M. HessB

Update boilerplate paragraphs to current VID description requirements.
- PHN

23-09-18

Muhammad A. Akbar

Prepared in accordance with ASME Y14.24

Vendor Item Drawing

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PMIC N/A
Original date of drawing
YY MM DD

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

PREPARED BY
Phu H. Nguyen

TITLE

CHECKED BY
Phu H. Nguyen
APPROVED BY

12-12-10

https://www.dla.mil/landandmaritime
MICROCIRCUIT, LINEAR-DIGITAL, DUAL-CORE
MICROCONTROLLER, MONOLITHIC SILICON

Thomas M. HessSIZE

CAGE CODE

A

REV B

16236

DWG NO.

PAGE

V62/12621

1 OF 23AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

5962-V156-23

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance mixed signal microcontrollers microcircuit, with
an operating temperature range of -40ºC to +125ºC.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/12621-

Drawing
number01

X

E

Device type(see 1.2.1)

Case outline(see 1.2.2)

Lead finish(see 1.2.3)

1.2.1 Device type(s).
Device type

Generic

Circuit function

01

MSP430G2231-EP

Mixed signal microcontroller

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

Package style

X

8

JEDEC MO-153

Plastic small outline

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

Material

A
B
C
D
E
F
Z

DLA LAND AND MARITIMECOLUMBUS, OHIO

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy
Other

SIZE
A

CAGE CODE
16236
REV

B

DWG NO.
V62/09618
PAGE 2

1.3 Absolute maximum ratings.

1/

Voltage applied at VCC to VSS ............................................................................................... -0.3 V to 4.1 V
Voltage applied to any pin .................................................................................................... -0.3 V to VCC +0.3 V 2/
Diode current at any device terminal .................................................................................... ±2 mA
Storage temperature: 3/
Unprogrammed device .................................................................................................. -55°C to 150°C
Programmed device ...................................................................................................... -55°C to 150°C
1.4 Recommended operating conditions.
Supply voltage, (VCC):
During program execution ............................................................................................. 1.8 V to 3.6 V
During flash program/erase ........................................................................................... 2.2 V to 3.6 V
Supply voltage, (VSS) .......................................................................................................... 0 V
Operating free air temperature, (TA) ..................................................................................... -40°C to 125°C
Processor frequency (Maximum MCLK frequency) 4/ 5/
VCC = 1.8 V, Duty cycle = 50% ±10% ............................................................................ dc to 6 MHz
VCC = 2.7 V, Duty cycle = 50% ±10% ............................................................................ dc to 12 MHz
VCC = 3.3 V, Duty cycle = 50% ±10% ............................................................................ dc to 16 MHz
2. APPLICABLE DOCUMENTSJEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)JEP95
J-STD-020––

Registered and Standard Outlines for Semiconductor Devices
Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state surface
mount devices.

(Copies of these documents are available online at https://www.jedec.org.)________________
1/

2/
3/
4/
5/

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
All voltage values referenced to VSS. The JTAG fuse blow voltage, VFB is allowed to exceed the absolute maximum rating. The
voltage is applied to the TEST pin when blowing the JTAG fuse..
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of thespecified maximum frequency.
Modules might have different maximum input clock specification. See the specification from the manufacturer data sheet.

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PAGE 3

3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1

Case outline. The case outline shall be as shown in 1.2.2 and figure 1.

3.5.2

Terminal connections. The terminal connections shall be as shown in figure 2.

3.5.3

Terminal function. The terminal function shall be as shown in figure 3.

3.5.4

Functional block diagram. The functional block diagram shall be as shown in figure 4.

3.5.5

Safe operating area. The safe operating area shall be as shown in figure 5.

3.5.6

POR/Brownout Reset (BOR) vs Supply voltage. The POR/Brownout Reset (BOR) vs Supply voltage shall be as shown infigure 6.

3.5.7

VCC(drop) level with a Square voltage drop to gernerate a POR/Brownout signal. The VCC(drop) level with a Square voltage drop
to gernerate a POR/Brownout signal shall be as shown in figure 7.

3.5.8

VCC(drop) level with a Triangle voltage drop to gernerate a POR/Brownout signal. The VCC(drop) level with a Triangle voltage
drop to gernerate a POR/Brownout signal shall be as shown in figure 8.

3.5.9

DCO wake-up time from LPM3/4 vs DCO frequency. The DCO wake-up time from LPM3/4 vs DCO frequency waveforms
shall be as shown in figure 9.

3.5.10

USI low level output voltage vs output current. The USI low level output voltage vs output current shall be as shown infigure 10.

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PAGE 4TABLE I. Electrical performance characteristics. 1/
Test

SymbolConditions

VCC

TA

2/ 3/ 4/
Active mode supply current into VCC excluding external current
Active mode (AM)
IAM, 1MHz
fDCO = fMCLK = fSMCLK = 1 MHz,
current (1 MHz)fACLK = 32768 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,CPUOFF = 0, SCG0 = 0
SCG1 = 0, OSCOOFF = 0

2.2 V

3V

Low power mode Supply current (into VCC) Excluding external current
ILPM0, 1MHz fMCLK = 0 MHz,fSMCLK = fCDO = 1 MHz,fACLK = 32,768 Hz,
Low power mode 0(LPM0) current
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,CPUOFF = 1, SCG0 = 0,
5/
SCG1 = 0, OSCOFF = 0
Low power mode 2
ILPM2
fMCLK = fSMCLK = 0 MHz,(LPM2) current
fCDO = 1 MHz,fACLK = 32,768 Hz,
6/BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,CPUOFF = 1, SCG0 = 0,
SCG1 = 1, OSCOFF = 0
Low power mode 3(LPM3) current

ILPM3, LFXT1

6/
Low power mode 3(LPM3) current
6/

Low power mode 4(LPM4) current
7/

ILPM3, VLO

ILPM4

Lim itsMinµA

65 TYP

µA

25°C

2.2 V

22 TYP

µA

46

µA

2.2 V

1.5

µA

21

µA

2.2 V

0.7

µA

9.3

µA

0.5

µA

85°C

1.5

µA

125°C

7.1

µA

125°C

fDCO = fMCLK = fSMCLK = 0 MHz,fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 1

390

µA

2.2 V

25°C

fDCO = fMCLK = fSMCLK = 0 MHz,fACLK = from internal LF oscillator (VLO),CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0

220 TYP

25°C

125°C

fDCO = fMCLK = fSMCLK = 0 MHz,fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0

Unit
Max

25°C

125°C
25°C

2.2 V

See footnote at end of table.

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PAGE 5TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolVCC

Conditions
2/

Schmitt Trigger inputs (Port Px) 42/
Positive going input threshold voltage

VIT+

Negative going input threshold voltage

VIT-

Input voltage hysteresis (VIT+ - VIT-)

Vhys

Pullup/pulldown resistor

RPull

Input capacitance
Leakage current (Port Px)
High impedance leakage current

CI

3V

Ilkg(Px.y)

Lim itsMax

0.45 VCC

0.75 VCC

V

1.35

2.25

V

0.25 VCC

0.55 VCC

V

3V

0.75

1.65

V

3V

0.3

1.0

V

For pullup: VIN = VSS
For pulldown: VIN = VCC
VIN = VSS or VCC

3V

20

50

kΩ

TA = 125°C

3V

8/

9/

5 TYP

TA = -40°C to 105°C
8/ 9/

Outputs (Port Px)
High level output voltage

Unit

Min

pF

+120

nA

±50

nA

VOH

I(OHmax) = -6 mA 10/

3V

VCC – 0.3

TYP

V

VOL

I(OLmax) = 6 mA 10/

3V

VCC + 0.3

TYP

V

fPx.y

3V

12

TYP

MHz

fPort°CLK

Px.y, CL = 20 pF, RL = 1
kΩ 11/ 12/
Px.y, CL = 20 pF 12/

3V

16

TYP

MHz

See figure 10

VCC(start)dVCC/dt ≤ 3 V/s

TYPV

See figure 10 through figure 12

V(B_IT-)

dVCC/dt ≤ 3 V/s

1.35 TYPV

See figure 10

Vhys(B_IT-)

dVCC/dt ≤ 3 V/s

130 TYPmV

See figure 10td(BOR)�����/NMI pin to
Pulse length needed at RST
accept reset internallyt(reset)Low level output voltage
Output frequency (Port Px)
Port output frequency (with load)
Clock output frequency
POR/Brownout reset (BOR)

13/

42/

0.7 x V(B_IT-)

2000
2.2V/3 V

2µsµs

See footnote at end of table.

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PAGE 6

TABLE I. Electrical performance characteristics - Continued. 1/
Test
DCO frequency
Supply voltage

SymbolVCC

Conditions

VCC

Lim its

Unit

Min

Max

RSELx < 14

1.8

3.6

V

RSELx = 14

2.2

3.6

V

RSELx = 15

3.0

3.6

V

2/

DCO frequency (0, 0)

fDCO(0,0)

RSELx = 0, DCOx = 0, MDDx = 0

3V

0.096

TYP

MHz

DCO frequency (0, 3)

fDCO(0,3)

RSELx = 0, DCOx = 3, MDDx = 0

3V

0.12

TYP

MHz

DCO frequency (1, 3)

fDCO(1,3)

RSELx = 1, DCOx = 3, MDDx = 0

3V

0.15

TYP

MHz

DCO frequency (2, 3)

fDCO(2,3)

RSELx = 2, DCOx = 3, MDDx = 0

3V

0.21

TYP

MHz

DCO frequency (3, 3)

fDCO(3,3)

RSELx = 3, DCOx = 3, MDDx = 0

3V

0.30

TYP

MHz

DCO frequency (4, 3)

fDCO(4,3)

RSELx = 4, DCOx = 3, MDDx = 0

3V

0.41

TYP

MHz

DCO frequency (5, 3)

fDCO(5,3)

RSELx = 5, DCOx = 3, MDDx = 0

3V

0.58

TYP

MHz

DCO frequency (6, 3)

fDCO(6,3)

RSELx = 6, DCOx = 3, MDDx = 0

3V

0.80

TYP

MHz

DCO frequency (7, 3)

fDCO(7,3)

RSELx = 7, DCOx = 3, MDDx = 0

3V

0.80

DCO frequency (8, 3)

fDCO(8,3)

RSELx = 8, DCOx = 3, MDDx = 0

3V

1.6

TYP

MHz

DCO frequency (9, 3)

fDCO(9,3)

RSELx = 9, DCOx = 3, MDDx = 0

3V

2.3

TYP

MHz

DCO frequency (10, 3)

fDCO(10,3)

RSELx = 10, DCOx = 3, MDDx = 0

3V

3.4

TYP

MHz

DCO frequency (11, 3)

fDCO(11,3)

RSELx = 11, DCOx = 3, MDDx = 0

3V

4.25

TYP

MHz

DCO frequency (12, 3)

fDCO(12,3)

RSELx = 12, DCOx = 3, MDDx = 0

3V

4.3

DCO frequency (13, 3)

fDCO(13,3)

RSELx = 13, DCOx = 3, MDDx = 0

3V

7.8

DCO frequency (14, 3)

fDCO(14,3)

RSELx = 14, DCOx = 3, MDDx = 0

3V

8.6

13.9

MHz

DCO frequency (15, 3)

fDCO(15,3)

RSELx = 15, DCOx = 3, MDDx = 0

3V

15.25

TYP

MHz

DCO frequency (15, 7)

fDCO(15,7)

RSELx = 15, DCOx = 7, MDDx = 0

3V

21

TYP

MHz

Frequency step between range
RSEL and RSEL + 1
Frequency step between tap
DCO and DCO + 1
Duty cycle

SRESL

SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)

3V

1.35

TYP

ratio

SDCO

SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)

3V

1.08

TYP

ratio

3V

50

TYP

%

1.50

7.30
TYP

MHz

MHz
MHz

See footnote at end of table.

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PAGE 7

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolCalibrated DCO frequencies – Tolerance

1 MHz tolerance over VCC

1 MHz tolerance overall

Wake up from Lower Power Models (LPM3/4)
DCO clock wake up time from
tDCO,LPM3/4
LPM3/415/
CPU wake up time from LPM3/4
tCPU,LPM3/4
16/
Crystal oscillator, XT1, low frequency mode
LFXT1 oscillator crystal
fLFXT1,LF
frequency,
LF mode 0, 1
LFXT1 oscillator logic level
fLFXT1,LF,logic
square wave input frequency, LF
mode
LFXT1 oscillator logic level
fLFXT1,LF,logic
square wave input frequency, LF
mode

Integrated effective load

OALF

CL,eff

TA = -40°C to 105°C
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
TA = 30°C
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
TA = -40°C to 105°C
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V

Lim its

Unit

Min

Max

3V

-3

3

%

1.8 V to
3.6 V

-3

3

%

1.8 V to
3.6 V

-6

6

%

3V

1.5 P

TYP

µs

1 / fMCLK + TYP
tClock,LPM3/4

µs

2/

42/

1 MHz tolerance overtemperature 14/

Oscillation allowance for LF
crystals

VCC

Conditions

BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,17/
42/
XTS = 0, LFXT1Sx = 0 or 1

1.8 V to
3.6 V

32768

TYP

Hz

XTS = 0, XCAPx = 0, LFXT1Sx = 3

1.8 V to
3.6 V

10000

50000

Hz

XTS = 0, XCAPx = 0, LFXT1Sx = 3,
TA = -40°C to 125°C

1.8 V to
3.6 V

32768

TYP

Hz

XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0

500

TYP

kΩ

200

TYP

kΩ

1

TYP

pF

XTS = 0, XCAPx = 1

5.5

TYP

pF

capacitance, LF mode 18/

XTS = 0, XCAPx = 2

8.5

TYP

pF

Duty cycle, LF mode

XTS = 0, Measured at P2.0/ACLK,fLFXT1,LF = 32768 Hz
XTS = 0, XCAPx = 0, LFXT1Sx = 3
20/

XTS = 0, XCAPx = 3

Oscillator fault frequency, LF
mode
19/

fFault,LF

11

TYP

pF

2.2 V

30

70

%

2.2 V

10

10000

Hz

See footnote at end of table.

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PAGE 8TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolVCC

Conditions

Internal Very Low power Low frequency Oscillator (VLO)
VLO frequency
fVLO
TA = -40°C to 85°C

Lim its
Max

3V

4

20

kHz

23

kHz

3V

0.5

TYP

1.8 V to 3.6 V

4

TYP

%/°C
%/V

TA = 125°C
VLO frequency temperature drift

dfVLO/dT

TA = -40°C to 125°C

VLO frequency supply voltage drift
Timer_A

dfVLO/dVCC

TA = 25°C

Timer_A input clock frequency

fTA

Timer_A capture timing
USI, Universal Serial Interface
USI clock frequency

fTA,cap

Low level output voltage on SDA
and SCL

VOL,I2C

fUSI

Internal: SMCLK,ACLK
External: TACLK, INCLK
Duty cycle = 50% ±10%TA0, TA1
External: SCLK,
Duty cycle = 50% ±10%
SPI slave mode
USI module in I2C mode,
I(OLmax) = 1.5 mA

Unit

Min

2/

3V

fSYSTEM TYP

MHz

20

ns

fSYSTEM

3V

VSS

TYP

MHz

VSS + 0.4

V

See footnote at end of table.

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PAGE 9TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions

10 Bit ADC, Power supply and input range conditions

TA

2/ 3/ 4/21/

Analog supply voltage

VCC

VSS = 0

Analog input voltage 22/

VAx

ADC10 supply current

IADC10All Ax terminal, Analog inputs
selected in ADC10AE register
fADC10CLK = 5.0 MHz,ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1, ADC10SHT1 = 0,
ADC10DIV = 0
fADC10CLK = 5.0 MHz,ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
fADC10CLK = 5.0 MHz,ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
fADC10CLK = 5.0 MHz,ADC10ON = 0, REFON = 1,

23/

Reference supply current,
reference buffer disabled

IREF+

24/
Reference buffer supply
current with ADC10SR = 0

IREFB,024/
Reference buffer supply
current with ADC10SR = 1

IREFB,124/
Input capacitance

CI

Input MUX ON resistance

RI

VCC

REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
fADC10CLK = 5.0 MHz,ADC10ON = 0, REFON = 1,

3V

2.2

3.6

V

0

VCC

V

3v

1.64

mA

-40°C to
125°C

3V

0.84

mA

3v

0.84

mA

3V

3.8

mA

1.4

mA

0.9

mA

0.7

mA

3V

27

pF

3v

2000

Ω

-40°C to
125°C

-40°C to125°C

3v

-40°C to85°C
-40°C to
125°C
-40°C to125°C

0 V ≤ VAX ≤ VCC

Unit
Max

-40°C to
125°C

-40°C to85°C

REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
Only one terminal Ax can beselected at one time

Lim itsMin

See footnote at end of table.

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PAGE 10

TABLE I. Electrical performance characteristics - Continued. 1/
Test

Symbol10 bit ADC, Built in voltage reference
Positive built in reference analog

VCC

Conditions
2/

VCC, REF+

IVREF+ ≤ 1 mA, REF2_5V = 0
IVREF+ ≤ 1 mA, REF2_5V = 1

Positive built in reference voltage

IVREF+ ≤ IVREF+ max, REF2_5V = 0

VREF+ load regulation

ILD,VREF+

44/

VREF+ load regulation response time
44/ 45/
Maximum capacitance at pin VREF+
44/ 45/Temperature coefficient

CVREF+
TCREF+

Setting time of internal reference
voltage to 99.9% VREF
44/ 45/tREFON

Setting time of reference buffer to
99.9% VREF
44/ 45/

tREFBURST

10 Bit ADC, External reference

25/ 42/

1.59

V

2.34

2.65

v

3V
IVREF+ = 500 µA,
Analog input voltage VAx ≠ 0.75 V,
REF2_5V = 0
IVREF+ = 500 µA ±100 µA
Analog input voltage VAx ≠ 1.25 V,
REF2_5V = 1
IVREF+ = 100 µA → 900 µA
VAx ≠ 0.5 V x VREF+,
Error conversion result ≤ 1 LSB,
ADC10SR = 0
IVREF+ ≤ 1 mA, REFON = 1,
REFOUT = 1
IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1
mA
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 → 1
IVREF+ = 0.5 mA,
REF2_5V = 1, REFON = 1
REFBURST = 1, ADC10SR = 0

V

1.4

±1

mA
LSB

±2
3V
LSB
±2
ns
3V

400

3V

100

pF

3V

±190

ppm/°C

3.6 V

30

µs

3V

2

µs

1.4

VCC

V

1.4

3

V

VEREF-VEREF+ > VEREF-,
SREF1 = 1, SREF0 = 0
VEREF- ≤ VEREF+ ≤ VCC – 0.15 V,
SREF1 = 1, SREF0 = 1
27/
VEREF+ > VEREF-

0

1.2

V

ΔVEREFVEREF+ > VEREF- 29/

1.4

VCC

V

3V

±1

TYP

µA

3V

0

TYP

µA

3V

±1

TYP

µA

Positive external reference input
voltage range 26/

VEREF+

Negative external reference input
voltage range 28/
Differential external reference input
voltage range,
ΔVEREF = VEREF+ - VEREFStatic input current into VEREF+

IVEREF+

Static input current into VEREF-

V

3
3V

IVREF+ ≤ IVREF+ max, REF2_5V = 1
Maximum VREF+ load current 44/ 45/

Unit
Max

2.2

supply voltage range
VREF+

LimitsMin

IVEREF-

0 V ≤ VEREF+ ≤ VCC ,SREF1 = 1, SREF0 = 0
0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3
V,
SREF1 = 1, SREF0 = 1
27/
0 V ≤ VEREF- ≤ VCC

See footnote at end of table.

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PAGE 11TABLE I. Electrical performance characteristics - Continued. 1/
Test

Symbol10 Bit ADC, Timing parameters
ADC10 input clock
frequency

2/

42/

fADC10CLKADC10 built in oscillator
frequency

fADC10OSC

Conversion timetCONVERT

Turn on setting time of thetADC10ON
ADC
10 Bit ADC, Linearity parameters 42/
Integral linearity error
EI

VCC

Conditions

Limits

Unit

Min

Max

0.45

6.3

0.45

1.5

For specified performance ADC10SR = 0
of ADC10 linearity
parameters
ADC10SR = 1

3V

MHz

ADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
ADC10 built in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
fADC10CLK from ACLK, MCLK, or SMCLK:ADC10SSELx ≠ 0
30/

3V

3.7

6.3

MHz

3V

2.06

3.51

µs

13 x ADC 10DIV x
1/fADC10CLK
100

µs

3V

±1

LSB

3V

±1

LSB

3V

±1

LSB

ns

Differential linearity error

ED

Offset error

EO

Gain error

EG

3V

±2

LSB

Total unadjusted error
ET
10 Bit ADC, Temperature sensor and built in VMID 42/
Temperature sensor supply
ISENSOR REFON = 0, INCHx = 0Ah,
current 31/
TA = 25°C
TCSENSOR ADC10ON = 1 INCHx = 0Ah

3V

±5

LSB

3V

60 TYPµA

3.55 TYP

mV/°Cµs

Source impedance RS < 100 Ω

32/

3V
3V

ple)

ADC10ON = 1 INCHx = 0Ah,
Error of conversion result ≤ 1 LSB

IVMID

ADC10ON = 1 INCHx = 0Bh

3V

VMID

ADC10ON = 1 INCHx = 0Bh,
VMID ≠ 0.5 x VCC
ADC10ON = 1 INCHx = 0Bh,
Error of conversion result ≤ 1 LSB

3VSample time required ifchannel 10 is selected
33/
Current into divider atchannel 11
VCC divider at channel 11

tSensor(samSample time required ifchannel 11 is selected
35/

tVMID(sample)

3V

30
34/
1.5 TYP
1220

DLA LAND AND MARITIMECOLUMBUS, OHIOCAGE CODE
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See footnote at end of table.

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PAGE 12TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolFlash memory
42/
Program and erase supply voltage

VCC

Conditions
2/

VCC(PGM/ERASE)

Limits

Unit

Min

Max

2.2

3.6

V

257

476

kHz

5

mA

Flash timing generator frequency

fFTG

Supply current from VCC during program

IPGM

Supply current from VCC during erase

IERASE

3V

7mA

Cumulative program timetCPT

2.2 V/3.6 V

10

ms

36/

Cummulative mass erase time

3V

tCMErase

Program/erase endurance

20

ms-40°C < TJ < 105°C

2.2 V/3.6 V

104cyclesData retention durationtRetentiontWord

TJ = 25°C
37/

15

Word or byte program time

30

TYP

tFTG

Block program time for first byte or word

tBlock, 0

37/

25

TYP

tFTG

Block program time for each additional byte
or word
Block program end sequence wait time

tBlock, 1-63

37/

18

TYP

tFTG

tBlock, End

37/

6

TYP

tFTG

Mass erase time

tMass Erase

37/

10593

TYP

tFTG

Segment erase timeRAM
RAM retention supply voltage 38/
JTAG and Spy-Bi-Wire Interface
Spy-Bi-Wire input frequency

tSeg Erase

37/

4819

TYP

tFTG

V(RAMh)CPU halted

1.6

fSBW

2.2 V/3 V

020

Spy-Bi-Wire low clock pulse lengthtSBW,Low

2.2 V/3 V

0.025

15

µs

Spy-Bi-Wire enable time
(Test high to acceptance of first clock edge
39/)
Spy-Bi-Wire return to normal operation time

tSBW,En

2.2 V/3 V

1µs

tSBW,RetTCK input frequency

40/

Internal pulldown resistance on TEST

years

V
MHz

2.2 V/3 V

15

100

µs

fTCK

2.2 V

0

5

MHz

3V

0

10

MHz

RInternal

2.2 V/3 V

25

90

kΩ

TA = -40°C to
105°C

TA = -40°C to
105°C

See footnote at end of table.

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PAGE 13TABLE I. Electrical performance characteristics - Continued. 1/
Test
JTAG fuse 41/ 43/
Supply voltage during fuse blow condition
Voltage level on TEST for fuse blow

1/

2/
3/
4/
5/
6/
7/
8/
9/
10/
11/
12/
13/
14/
15/
16/
17/

SymbolConditions

VCC

2/

LimitsMin

VCC(FB)

2.5

VFB

6

Unit
Max
V
7

V

Supply current into TEST during fuse blow

IFB

100

mA

Time to blow fuse

tFB

1

ms

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may notnecessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
Over recommended operating free air temperature range (unless otherwise noted).
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal andexternal load capacitance is chosen closely match the required 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor isdisabled.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
A resistive divider with 2 x 0.5 kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of thedivider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-)
Vhys(B_IT-) is ≤ 1.8 V.
+
This is the frequency change from the measured frequency at 30°C over temperature.
The DCO clock wake up time is measured from the edge of an external wake up signal (for example, port interrupt) to the first clockedge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
To improve EMI on the XT1 oscillator, the following guide lines should be observed.
a) Keep the trace between the device and the crystal as short as possible.
b) Design a good ground plane around the oscillator pins.
c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in otherdocumentation. This signal is no longer required for the serial programming adapter.

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18/
19/
20/
21/
22/
23/
24/
25/
26/
27/
28/
29/
30/
31/
32/
33/
34/
35/
36/
37/
38/
39/
40/
41/
42/
43/
44/
45/

Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For acorrect set up, the effective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic level input frequency but also applies to operation with crystals.
The leakage current is defined in the leakage current table with Px.y/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion result.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied by terminal VCC. Consumption is independent of the ADC10ON control bit, unless aconversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow therecommendations on analog source impedance to allow the charge to settle for 10 bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer
supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be appliedwith reduced accuracy requirements.
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are
already settled.
The sensor current ISENSOR is consuimed if (ADC10ON = 1 and REFON = 1) or (ADC10ON =1 and INCH = 0Ah and sample signal
is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature
sensor input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor, typ = TCSensor (273 + T[°C] + VOffset,sensor[mV] or
VSensor, typ = TCSensor T[°C] + VSensor(TA = 0°C)[mV].
The typical equivalent is impedance of the sensor is 51 kΩ. The sample time required includes the sensor on time tSENSOR(on).
No additional current is needed. The VMID is used during sampling.
The on time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
The cumulative program time must not be exceeded when writing to a 64 byte flash block. This parameter applies to all
programming methods: individual word/byte write and block write modes.
These values are hardwired into the Flash controller’state machine (tFTG = 1/fFTG).
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
Once the fuse is blown, no further access to the JATG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched
to bypass mode.
Over recommended ranges of supply voltage and up to operating free air temperature, TA = 105°C (unless otherwise noted).
Over recommended ranges of supply voltage, TA = 25°C (unless otherwise noted).
Minimum and maximum parameters are characterized up to TA = 105°C (unless otherwise noted).
characterized at TA = -40°C to 105°C only.

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PAGE 15

Case Xbe

140.10(.004)

M

8

c
0°-8°

E E1

1

GAGE
PLANE

7

0.25(.010)

L

DETAIL A
D
SEE
DETAIL A
A1

A

SEATING
PLANE

SymbolAA1bcD

0.10(.004)

Dimen sions
Millim eters
Symbol
Min
Max
1.20
0.05
0.15
0.19
0.30
0.15 NOM
4.90
5.10

E
E1
e
L

Millim eters
Min
Max
4.30
6.20
0.65
0.50

4.50
6.60
BSC
0.75

NOTES:
1. All linear dimensions are in millimeters (inches).
2. This drawing is subject to change without notice.
3. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006
0.15 each side.
4. Body width does not include interlead flash. Interlead flash shall not exceed 0.25 each side.
5. Fall within JEDEC MO-153

FIGURE 1. Case outline.

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PAGE 16

Terminal
numberTerminal symbol

Terminal
numberTerminal symbol

1
2
3
4
5
6
7

DVCC
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
P1.2/TA0.1/A2
P1.3/ADC10CLK/A3/VREF-/VEREFP1.4/SMCLK/A4/VREF+/VEREF+/TCK
P1.5/TA0.0/A5/SCLK/TMS

8
9
10
11
12
13
14

P1.6/TA0.1/A6/SDO/SCL/TDI/TCLK
P1.7/A7/SDI/SDA/TDO/TDI�����/NMI/SBWTDIORSTTEST/SBWTCKXOUT/P2.7
XIN/P2.6/TA0.1
DVSS

FIGURE 2. Terminal connections.

Terminal
Name
P1.0/
TA0CLK/
ACLK
A0
P1.1/
TA0.0/A1
P1.2/
TA0.1/A2
P1.3/
ADC10CLK/
A3/
VREF-/VEREFP1.4/
SMCLK/A4/
VREF+/VEREF+/
TCK
P1.5/
TA0.0/
A5/
SCLK/
TMS

I/O

Description

No.
2

I/O

3

I/O

4

I/O

5

I/O

6

I/O

7

I/O

General purpose digital I/O pin
Timer0_A, clock signal TACLK input
ACLK signal output
ADC10 analog input A0 1/
General purpose digital I/O pin
Timer0_A, capture:CCI0A input, compare: Out0 output
ADC10 analog input A1 1/
General purpose digital I/O pin
Timer0_A, capture:CCI1A input, compare: Out1 output
ADC10 analog input A2 1/
General purpose digital I/O pin
ADC10, conversion clock output 1/
ADC10 analog input A3
1/
ADC10 negative reference voltage
1/
General purpose digital I/O pin
SMCLK signal output
ADC10 analog input A41/
ADC10 positive reference voltage 1/
JTAG test clock, input terminal for device programming and test
General purpose digital I/O pin
Timer0_A, compare: Out0 output
ADC10 analog input A5
USI: clock input in I2C mode; clock input/output in SPI mode
JTAG test data input or test clock input during programming and test

See footnote at end of table.

FIGURE 3. Terminal function.

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PAGE 17

Term inal
Name

1/
2/
3/

I/O

Description

No.

P1.6/
TA0.1/
A6/
SDO/
SCL/
TDI/TCLK
P1.7/
A7/
SDI/
SDA/
TDO/TDI 2/

8

I/O

9

I/O

XIN/
P2.6/
TA0.1
XOUT/
P2.7
�����
RST/
NMI/
SBWTDIOTEST/SBWTCK

13

I/O

12

I/O

10

I

11

I

DVCC
DVSS
QFN Pad

1
14

N/A
N/A
N/A

General purpose digital I/O pin
Timer0_A, capture: CCI1A input, compare Out1 output
ADC10 analog input A6
USI: Data output in SPI mode
USI: I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
General purpose digital I/O pin
ADC10 analog input A7 1/
USI: Data output in SPI mode
USI: Data i2c in I2C mode
JTAG test data output terminal or test data input during programming and
test
Input terminal of crystal oscillator 3/
General purpose digital I/O pin
Timer0_A, compare: Out1 output
Output terminal of crystal oscillator 3/
General purpose digital I/O pin
Reset imput
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
Select test mode for JTAG pins on Port 1. The device protection fuse isconnected to TEST.
Spy-Bi-Wire test clock input during programming and test.
Supply voltage
Ground reference
QFN package pad connection to VSS recommended.

MSP430G2x31 only.
TDO and TDI is selected via JTAG instruction.
If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driverconnection to this pad after reset.

FIGURE 3. Terminal function - Continued.

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PAGE 18

DVCC
XIN

P1.x

DVSS

P2.x

XOUT
8

FLASH

RAM

ADC

2 kB

128 B

8 CHANNEL

2

PORT P1

PORT P2

ACLK
CLOCK

10-BITSYSTEM
SMCLK

1 kB

AUTOSCAN
1 ch DMA

MCLK

16 MHz

8 I/O

2 I/O

INTERRUPTINTERRUPTCAPABILITYCAPABILITY

PULL-UP/DOWN

PULL-UP/DOWNRESISTORSRESISTORSTIMER0_A2

USI

2 CC

UNIVERSAL

MAB

CPU

INCL 16REGISTERSMDBEMULATION
2BP

WATCHDOGWDT+JTAGINTERFACEBROWNOUTPROTECTION

15-BITREGISTERSSERIAL
INTERFACE
SPI,I2C

SPY-BI WIRE

RST/NMIFIGURE 4. Functional block diagram.

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LEGEND:SYSTEM FREQUENCY-MHz

16 MHz

SUPPLY VOLTAGE RANGE,DURING FLASH MEMORYPROGRAMMING

12 MHz

SUPPLY VOLTAGE RANGE,DURING PROGRAM EXECUTION

6 MHz

1.8 V

2.2 V

2.7 V

3.3 V

3.6 V

SUPPLY VOLTAGE-V

NOTE:
1. Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
FIGURE 5. Safe operating area.

VCC
Vhys(B_IT-)

V(B_IT-)
VCC(START)

10td(BOR)

FIGURE 6. POR/Brownout Reset (BOR) vs Supply voltage.

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PAGE 20

V
2

t

CC

PW

3V
V

CC

=3 V

TYPICAL CONDITIONS

-V

1.5

V CC(drop)

1V

CC(drop)

.5

0
.001

1

1000
1 ns

1 ns
tpw -PULSE WIDTH-s
tpw -PULSE WIDTH-s

FIGURE 7. VCC(drop) level with a Square voltage drop to generate a POR/Brownout signal.

V
2

t

CC

PW

3V
V

CC

=3 V

TYPICAL CONDITIONSV CC(drop)

-V

1.5

1
V

CC(drop)

.5

t
f

=t
r

0
.001

1
tpw -PULSE WIDTH-

1000

t
f

t
r

s
s

tpw -PULSE WIDTH-

FIGURE 8. VCC(drop) level with a Triangle voltage drop to generate a POR/Brownout signal.

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PAGE 21

DCO WAKE TIME-us

10.00

RSELx=0...11

1.00

.10
.10

RSELx=12...15

1.00

10.00

DCO FREQUENCY-MHz

FIGURE 9. DCO wake-up time from LPM3/4 vs DCO frequency.

5.0

5.0

VCC =3 V

TA =25° C

4.0

I OL -LOW-LEVEL OUTPUT VOLTAGE-mA

I OL -LOW-LEVEL OUTPUT VOLTAGE-mA

VCC =2.2 V

3.0
TA =85° C
2.0

1.0

0.0
0.0

0.2

0.4

0.6

0.8

4.0

3.0

TA =85° C

2.0

1.0

0.0
0.0

1.0

TA =25° C

0.2

0.4

0.6

0.8

V -LOW-LEVEL OUTPUT VOLTAGE-V
OL

V -LOW-LEVEL OUTPUT VOLTAGE-V
OL

FIGURE 10. USI low level output voltage vs output current.

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PAGE 221.0

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.
Vendor item drawing
administrative control
number 1/

Devicemanufacturer
CAGE code

Top sidemarking

Transport media

Vendor part number

V62/12621-01XE

01295

G2231EP

Tape and real

MSP430G2231QPW1REPTube

MSP430G2231QPW1EP

1/ The vendor item drawing establishes an administrative control number for identifying the item on theengineering documentation.

CAGE code

Source of supply

01295

DLA LAND AND MARITIMECOLUMBUS, OHIO

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZE
A

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PAGE 23