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Document: EVG-MRM-0005.doc
Date: 19 September 2011
Issue: 1
Page: 1 of 51
Author: Jukka Pietarinen

Event Generator
cPCI-EVG-220, cPCI-EVG-230, cPCI-EVG-300 and VMEEVG-230
Modular Register Map Firmware Version 0005

Contents
Introduction ................................................................................................................................4
Event Stream Details ...............................................................................................................4
Event Codes ........................................................................................................................4
Distributed Bus and Data Transmission ...............................................................................5
Event Sources .........................................................................................................................5
Trigger Events.....................................................................................................................5
Upstream Events .................................................................................................................6
Event Sequencer..................................................................................................................7
Distributed Bus .......................................................................................................................8
Timestamping Inputs ...........................................................................................................9
Timestamp Generator ..........................................................................................................9Multiplexed Counters ............................................................................................................10
Configurable Size Data Buffer...............................................................................................10
Programmable Front Panel Connections ............................................................................12
AC Line Synchronisation ......................................................................................................12
Event Clock ..........................................................................................................................12
RF Clock and Event Clock ....................................................................................................13
Fractional Synthesiser........................................................................................................14
Connections ..............................................................................................................................15
cPCI-EVG-2x0 Front Panel Connections ...............................................................................15
VME-EVG-230 Front Panel Connections ..............................................................................16
VME-EVG-230 VME P2 User I/O Pin Configuration ........................................................17cPCI-EVG-300 Front Panel Connections ...............................................................................17
Programming Details ................................................................................................................19
VME-EVG-230 CR/CSR Support .........................................................................................19
Function 0/1/2 Registers ....................................................................................................19
VME-EVG-230 Network Interface............................................................................................21
Assigning an IP Address to the Module .................................................................................21
Using Telnet to Configure Module ........................................................................................21
Boot Configuration (command b) ......................................................................................21
Memory dump (command d) .............................................................................................22
Memory modify (commands d and m) ...............................................................................22
Upgrading IP2022 Microprocessor Software (command u) ................................................23
Linux.................................................................................................................................23

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Document: EVG-MRM-0005.doc
Date: 19 September 2011
Issue: 1
Page: 2 of 51
Author: Jukka Pietarinen

Windows ...........................................................................................................................23
Upgrading FPGA Configuration File .....................................................................................23
Linux.................................................................................................................................23
Windows ...........................................................................................................................23
Linux.................................................................................................................................24
Windows ...........................................................................................................................24
UDP Remote Programming Protocol .....................................................................................24
Read Access (Type 0x01) ..................................................................................................25
Write Access (Type 0x02) .................................................................................................25
Register Map.........................................................................................................................26
Application Programming Interface (API) .................................................................................42
Function Reference ...............................................................................................................42
int EvgOpen(struct MrfEgRegs **pEg, char *device_name); .............................................42
int EvgClose(int fd); ..........................................................................................................42
int EvgEnable(volatile struct MrfEgRegs *pEg, int state);..................................................42
int EvgGetEnable(volatile struct MrfEgRegs *pEg); ..........................................................43
int EvgRxEnable(volatile struct MrfEgRegs *pEg, int state); .............................................43
int EvgRxGetEnable(volatile struct MrfEgRegs *pEg);......................................................43
int EvgGetViolation(volatile struct MrfEgRegs *pEg, int clear); ........................................43
int EvgSWEventEnable(volatile struct MrfEgRegs *pEg, int state); ...................................43
int EvgGetSWEventEnable(volatile struct MrfEgRegs *pEg); ...........................................44
int EvgSendSWEvent(volatile struct MrfEgRegs *pEg, int code);......................................44
int EvgEvanEnable(volatile struct MrfEgRegs *pEg, int state);..........................................44
int EvgEvanGetEnable(volatile struct MrfEgRegs *pEg); ..................................................44
void EvgEvanReset(volatile struct MrfEgRegs *pEg); .......................................................44
void EvgEvanResetCount(volatile struct MrfEgRegs *pEg);..............................................45
int EvgEvanGetEvent(volatile struct MrfEgRegs *pEg, struct EvanStruct *evan);..............45
int EvgSetMXCPrescaler(volatile struct MrfEgRegs *pEg, int mxc, unsigned int presc); ...45
int EvgSetMxcTrigMap(volatile struct MrfEgRegs *pEg, int mxc, int map);......................45
void EvgSyncMxc(volatile struct MrfEgRegs *pEg);.........................................................45
void EvgMXCDump(volatile struct MrfEgRegs *pEg); .....................................................46
int EvgSetDBusMap(volatile struct MrfEgRegs *pEg, int dbus, int map); ..........................46
void EvgDBusDump(volatile struct MrfEgRegs *pEg); .....................................................46
int EvgSetACInput(volatile struct MrfEgRegs *pEg, int bypass, int sync, int div, int delay);..........................................................................................................................................46
int EvgSetACMap(volatile struct MrfEgRegs *pEg, int map);............................................47
void EvgACDump(volatile struct MrfEgRegs *pEg);.........................................................47
int EvgSetRFInput(volatile struct MrfEgRegs *pEg, int useRF, int div); ............................47
int EvgSetFracDiv(volatile struct MrfEgRegs *pEg, int fracdiv); .......................................47
int EvgSetSeqRamEvent(volatile struct MrfEgRegs *pEg, int ram, int pos, unsigned int
timestamp, int code); .........................................................................................................47
void EvgSeqRamDump(volatile struct MrfEgRegs *pEg, int ram); ....................................48
int EvgSeqRamControl(volatile struct MrfEgRegs *pEg, int ram, int enable, int single, int
recycle, int reset, int trigsel);..............................................................................................48
int EvgSeqRamSWTrig(volatile struct MrfEgRegs *pEg, int trig);.....................................48
void EvgSeqRamStatus(volatile struct MrfEgRegs *pEg, int ram); ....................................48
int EvgSetUnivinMap(volatile struct MrfEgRegs *pEg, int univ, int trig, int dbus);............49
void EvgUnivinDump(volatile struct MrfEgRegs *pEg); ...................................................49

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Document: EVG-MRM-0005.doc
Date: 19 September 2011
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Author: Jukka Pietarinen

int EvgSetTriggerEvent(volatile struct MrfEgRegs *pEg, int trigger, int code, int enable);.49
void EvgTriggerEventDump(volatile struct MrfEgRegs *pEg);..........................................49
int EvgSetUnivOutMap(volatile struct MrfEgRegs *pEg, int output, int map);...................49
int EvgSetDBufMode(volatile struct MrfEgRegs *pEg, int enable); ...................................50
int EvgGetDBufStatus(volatile struct MrfEgRegs *pEg);...................................................50
int EvgSendDBuf(volatile struct MrfEgRegs *pEg, char *dbuf, int size); ...........................50

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Introduction
The Event Generator is responsible of creating and sending out timing events to an array of Event
Receivers. High configurability makes it feasible to build a whole timing system with a single
Event Generator without external counters etc.
Events are sent out by the event generator as event frames (words) which consist of an eight bit
event code and an eight bit distributed bus data byte. The event transfer rate is derived from anexternal RF clock or optionally an on-board clock generator. The optical event stream transmitted
by the Event Generator is phase locked to the clock reference.
There are several sources of events: trigger events, sequence events, software events and events
received from an upstream Event Generator. Events from different sources have different priority
which is resolved in a priority encoder.
In addition to events the Event Generator enables the distribution of eight simultaneous signals
sampled with the event clock rate, the distributed bus. Distributed bus signals may be provided
externally or generated on-board by programmable multiplexed counters.

Event Stream Details
The structure of the event stream is described to help understand the functioning of the event
system. The event stream should be considered as a continuous flow of event frames which
consist of two bytes, the event code and distributed bus data byte.
Event Receiver
0

1

1

2

2

3

3

4

4

5

5

6

6

7

8B10B
encoding

Fiber Optic
Transmitter

Fiber Optic
Receiver

8B10B
decoding

Distributed Bus Bits

Distributed Bus Bits

Event Generator
0

7

E
v
e
n
t

E
v
e
n
t

C
o
d
e

C
o
d
e

Figure 1: Event Frame

Event Codes
There are 256 event codes from which a few have special functions. The special function eventcodes are listed below. Only one event code may be transferred at a time. If there is no event code
to be transferred, the null event code (0x00) is transmitted. Every now and then a special 8B10B

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character K28.5 is transmitted instead of the null event code. The K28.5 comma character istransmitted to allow the event receivers to synchronise on the correct word boundary is the serial
bit stream.
Event Code
0x00
0x01 – 0x6F
0x70

Code Name
Null Event Code
Seconds ‘0’

EVG Function
User Defined-

0x71

Seconds ‘1’-0x72 – 0x79
0x7A
0x7B

Heartbeat
Synchronise Prescalers

User Defined-

0x7C

Timestamp Counter
Increment
Timestamp Counter Reset
End of Sequence
-

-

0x7D
0x7F
0x80-FF

Stop Sequence
User Defined

EVR Function
User Defined
Shift in ‘0’ to LSB ofSeconds Shift Register
Shift in ‘1’ to LSB ofSeconds Shift Register
User Defined
Reset Heartbeat Monitor
Synchronise Prescaler
Outputs
Increment Timestamp
Counter
Reset Timestamp Counter
User DefinedDistributed Bus and Data Transmission
The distributed bus allows transmission of eight simultaneous signals with the event clock rate
time resolution (10 ns at 100 MHz event clock rate). The source for distributed bus signals may
come from an external source or the signals may be generated with programmable multiplexedcounters (MXC) inside the event generator. The distributed bus signals may be programmed to beavailable as hardware outputs on the event receiver.
In latest firmware versions the distributed bus bandwidth may be shared by transmission of aconfigurable size data buffer to up to 2 kbytes. When data transmission is enabled the distributed
bus bandwidth is halved. The remaining bandwidth is reserved for transmitting data with a speed
up to 50 Mbytes/s (event clock rate divided by two).

Event Sources
Trigger Events
There are eight trigger event sources that send out an event code on a stimulus. Each trigger event
has its own programmable event code register and various enable bits. The event code transmitted
is determined by contents of the corresponding event code register. The stimulus may be a
detected rising edge on an external signal or a rising edge of a multiplexed counter output.

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TEVx
event
code
reg.
TTL trigger input x
to priority
encoderminimum width 10 ns

rising-edge detector
enablemultiplexedcounter x

enableENEVx
Trigger Eventenable bit

rising-edge detector
MXCEVx

Trigger
event 0only

AC mains
voltage sync.
logic

enablerising-edge detector
ACEV0

Figure 2: Trigger Events

Trigger Event 0 has also the option of being triggered by a rising edge of the AC mains voltage
synchronization logic output signal.
The external input accepts TTL level signals. The input logic is edge sensitive and the signals aresynchronized internally to the event clock.

Upstream Events
Event Generators may be cascaded. The event generator receiver includes a first-in-first-out(FIFO) memory to synchronize incoming events which may be synchronized to a clock unrelated
to the event clock. Usually there are no events in the FIFO. An event code from an upstream EVG
is transmitted as soon as there is no other event code to be transmitted.

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fifo full flag
FF
e
v
e
n
t

from
upstream
EVG

512-event
event FIFO

to priority
encodercode
RSFIFO DFIFO
reset disable
FIFO
FIFO

Figure 3: Upstream Event FIFO

Event Sequencer
Event sequencers provide a method of transmitting or playing back sequences of events stored in
random access memory with defined timing. In the event generator there are two event
sequencers. The 8-bit event codes are stored in a RAM table each attached with a 32-bit
timestamp relative to the start of sequence. Both sequencers can hold up to 2048 event code –timestamp pairs.
ram address

32 bits

8 bits0

event address / timestampcode

1. event

1

event address / timestampcode

2. event2

event address / timestampcode

3. event

2047

event address / timestampcode

2048. event

Figure 4: Sequencer RAM Structure

The contents of a sequencer RAM may be altered at any time, however, it is recommended only
to modify RAM contents when the RAM is disabled. The sequencer runs at the event clock rate to
up to 100 MHz.
The Sequencers may be triggered from several sources including software triggering, triggering
on a multiplexed counter output or AC mains voltage synchronization logic output.
The sequencers are enabled by writing a ‘1’ bit to SQxEN in the Sequence RAM control Register.
The RAMs may be disabled any time by writing a ‘1’ to SQxDIS bit. Disabling sequence RAMsdoes not reset the RAM address and timestamp registers. By writing a ‘1’ to the bit SQxRES in
the Control Register the sequencer is both disabled and the RAM address and timestamp register
is reset.
When the sequencer is triggered the internal event address counters starts counting. The countervalue is compared to the event address of the next event in the RAM table. When the countervalue matches or is greater than the timestamp in the RAM table, the attached event code isDocument: EVG-MRM-0005.doc
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Micro-Research Finland Oy
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sequence clock cycles i.e. the internal event address counter rolls over when to 0 when 0xffffffff
is reached.
There are two special event codes which are not transmitted, the null event code 0x00 and end
sequence code 0x7f. The null event code may be used if the time between two consecutive eventsshould exceed 232 event clock cycles by inserting a null event with a timestamp value of
0xffffffff. The end sequence code resets the sequencer RAM table address and timestamp registerand depending on configuration bits, disables the sequencer (single sequence, SQxSNG=1) orrestarts the sequence either immediately (recycle sequence, SQxREC=1) or waits for a new
trigger (SQxREC=0).
sequencer disabledsequencer enabled
enablesequencer
disabledsequencer
stoppeddisabletriggerreset
address

resetsequence

sequence
runningend
sequencecode (0x7f)

when timestamps
match
send event code(not null, freeze
end sequence) &increment addr.

not single and recycle
SSEQx=0 and RCYLx=1
not single and notrecycle SSEQx=0
and RCYLx=0

singlesequence
SSEQx=1

reset
address

Figure 5: Sequencer Control

Sequencer Interrupt Support
The sequencers provide two interrupts: a sequence start and sequence stop interrupt. The
sequence start interrupt is issued when a sequencer is in enabled state, gets triggered and was notrunning before the trigger.
A sequence stop interrupt is issued when the sequence is running and reaches the ‘end of
sequence’ code.

Distributed Bus
The bits of the distributed bus are sampled at the event rate from external signals; alternatively
the distributed bus signals may be generated by multiplexed counter outputs. If there is an
upstream EVG, the state of all distributed bus bits may be forwarded by the EVG.

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Distributed bus
signal x fromupstream EVG

1
0Distributed bus
TTL input x

Distributed
bus transmit

D
Q

0
DBUS

event clk
1
multiplexedcounter output x

MXDENxFigure 6: Distributed Bus

Timestamping Inputs
Starting from firmware version E306 a few distributed bus input signals have dual function:transition board input DBUS5-7 can be used to generate special event codes controlling thetimestamping in Event Receivers.
DBUS5
timestamp resete.g. 1 Hz

trigger event code 0x7D

DBUS4
timestamp clocke.g. 1 MHz

distributed bus bit 4

DBUS6
seconds counter'0' input

trigger event code 0x70

DBUS7
seconds counter'1' input

trigger event code 0x71

Figure 7: Timestamping Inputs

The two clocks, timestamp clock and timestamp reset clock, are assumed to be rising edgealigned. In the EVG the timestamp reset clock is sampled with the falling edge of the timestamp
clock. This is to prevent a race condition between the reset and clock signals. In the EVR the reset
is synchronised with the timestamp clock.
The two seconds counter events are used to shift in a 32-bit seconds value between consecutive
timestamp reset events. In the EVR the value of the seconds shift register is transferred to theseconds counter at the same time the higher running part of the timestamp counter is reset.
The distributed bus event inputs can be enabled independently through the distributed bus event
enable register. The events generated through these distributed bus input ports are given lowest
priority.

Timestamp Generator
Logic has been added to automatically increment and send out the 32-bit seconds value. Using
this feature requires the two externally supplied clocks as shown above, but the events 0x70 and
0x71 get generated automatically.

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After the rising edge of the slower clock on DBUS4, the internal seconds counter is incremented
and the 32 bit binary value is sent out LSB first as 32 events 0x70 and 0x71. The seconds countercan be updated by software by using the TSValue and TSControl registers.

Multiplexed Counters
Eight 32-bit multiplexed counters generate clock signals with programmable frequencies fromevent clock/232-1 to event clock/2. Even divisors create 50% duty cycle signals. The counter
outputs may be programmed to trigger events, drive distributed bus signals and trigger sequenceRAMs. The output of multiplexed counter 7 is hard-wired to the mains voltage synchronization
logic.
32-bit prescaler register
odd cycle extend by one
reload

event
clock

&

31-bit count-down counter=0

ortoggleFF
resetext. reset
SW reset

outputFigure 8: Multiplexed Counter

Each multiplexed counter consists of a 32-bit prescaler register and a 31-bit count-down counter
which runs at the event clock rate. When count reaches zero, the output of a toggle flip-flopchanges and the counter is reloaded from the prescaler register. If the least significant bit of theprescaler register is one, all odd cycles are extended by one clock cycle to support odd dividers.
Prescaler value

Duty Cycle

0, 1 not allowed
2
3
4
5
…
232 – 1

undefined
50/50
33/66
50/50
40/60
…
approx. 50/50

Frequency at 125 MHz Event
Clock
Undefined
62.5 MHz41.7 MHz
31.25 MHz
25 MHz…
0.029 HzThe multiplexed counters may be reset by software or hardware input. The reset state is definedby the multiplexed counter polarity register.

Configurable Size Data Buffer
Starting from firmware version E305 transmission of a configurable size data buffer over the
event system link is possible. The buffer size can be programmed in four byte increments (longwords) from 4 bytes to 2048 bytes.

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memoryaccess

2 kbytedual ported
data transmit
bufferDocument: EVG-MRM-0005.doc
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transmit
engine andchecksumming

distributed
bus interface

enabletriggerbufsize_words
tx_running
tx_complete

Figure 9: Configurable size transmit data buffer

When the EVG is configured for data transmission (mode = 1 in data buffer control register) the
bandwidth of the distributed bus is shared with data transmission: half of the bandwidth remains
for the distributed bus and the other half is reserved for data transmission.
The data to be transmitted is stored in a 2 kbyte dual-ported memory starting from the lowest
address 0. This memory is directly accessible from VME. The transfer size is determined bybufsize register bits in four byte increments. The transmission is trigger by software. Two flags
tx_running and tx_complete represent the status of transmission.
Transmission utilises two K-characters to mark the start and end of the data transfer payload, theprotocol looks following:
Table 1: Data Transmission Protocol

8B10B-character
K28.0
Dxx.x
Dxx.x
Dxx.x
Dxx.x
…
Dxx.x
K28.1
Dxx.x
Dxx.x

Description
Start of data transfer
1st data byte (address 0)
2nd data byte (address 1)
3rd data byte (address 2)
4th data byte (address 3)…
nth data byte (address n-1)
End of data
Checksum (LSB)
Checksum(MSB)

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Programmable Front Panel Connections
The front panel outputs are programmable: multiplexed counters and distributed bus bits can bemapped to any output. The mapping is shown in table below.
Table 2: Signal mapping IDs

Mapping ID
0 to 31
32
…
39
40
…
47
48 to 61
62
63

Signal(Reserved)
Distributed bus bit 0 (DBUS0)…
Distributed bus bit 7 (DBUS7)
Multiplexed Counter 0…
Multiplexed Counter 7(Reserved)
Force output high (logic 1)
Force output low (logic 0)

AC Line Synchronisation
The Event Generator provides synchronization to the mains voltage frequency or another external
clock. The mains voltage frequency can be divided by an eight bit programmable divider. The
output of the divider may be delayed by 0 to 25.5 ms by a phase shifter in 0.1 ms steps to be able
to adjust the triggering position relative to mains voltage phase. After this the signal synchronized
to the event clock or the output of multiplexed counter 7.

ACINTTL input
50-60 Hz mains
voltage freq.

divide by
1 to 256

delay of0 to 25.5 ms
in 0.1 ms steps

8-bit
prescaler

phase
shifter

ACDIV

ACDEL

trigger1

multiplexedcounter 7
event clock

1

D
Q

0

RAM sequence 1
RAM sequence 2
Trigger event 0

ACSQ1
ACSQ2
ACEV0

0

ACBYP
ACSYNC

Figure 10: AC Input´
The phase shifter operates with a clock of 1 MHz which introduces jitter. If the prescaler andphase shifter are not required this circuit may be bypassed. This also reduces jitter because theexternal trigger input is sampled directly with the event clock.

Event ClockAll operations on the event generator are synchronised to the event clock which is derived froman externally provided RF clock. For laboratory testing purposes an on-board fractional

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synthesiser may be used to deliver the event clock. The serial link bit rate is 20 times the event
clock rate. The acceptable range for the event clock and bit rate is shown in the following table.

Minimum
Maximum

Event Clock
50 MHz
125 MHz

Bit Rate
1.0 Gb/s
2.5 Gb/s

Note: maximum event clock for cPCI-EVG-220 is 100 MHz with 2.0 Gb/s bit rate

During operation the reference frequency should not be changed more than ±100 ppm.

RF Clock and Event Clock
The event clock may be derived from an external RF clock signal. The front panel RF input is 50
ohm terminated and AC coupled to a LVPECL logic input, so either an ECL level clock signal orsine-wave signal with a level of maximum +10 dBm can be used.
Divider
÷1
÷2
÷3
÷4
÷5
÷6
÷7
÷8
÷9
÷ 10
÷ 11
÷ 12
÷ 14
÷ 15
÷ 16
÷ 17
÷ 18
÷ 19
÷ 20
÷ 21
÷ 22
÷ 23
÷ 24
÷ 25
÷ 26
÷ 27
÷ 28
÷ 29
÷ 30
÷ 31
÷ 32

RF Input Frequency
50 MHz – 125 MHz
100 MHz – 250 MHz
150 MHz – 375 MHz
200 MHz – 500 MHz
250 MHz – 625 MHz
300 MHz – 750 MHz
350 MHz – 875 MHz
400 MHz – 1.0 GHz
450 MHz – 1.125 MHz
500 MHz – 1.25 GHz
550 MHz – 1.375 GHz
600 MHz – 1.5 GHz
700 MHz – 1.6 GHz *)750 MHz – 1.6 GHz *)800 MHz – 1.6 GHz *)850 MHz – 1.6 GHz *)900 MHz – 1.6 GHz *)950 MHz – 1.6 GHz *)1.0 GHz – 1.6 GHz *)1.05 GHz – 1.6 GHz *)1.1 GHz – 1.6 GHz *)1.15 GHz – 1.6 GHz *)1.2 GHz – 1.6 GHz *)1.25 GHz – 1.6 GHz *)1.3 GHz – 1.6 GHz *)1.35 GHz – 1.6 GHz *)1.4 GHz – 1.6 GHz *)1.45 GHz – 1.6 GHz *)1.5 GHz – 1.6 GHz *)1.55 GHz – 1.6 GHz *)1.6 GHz *)Event Clock
50 MHz – 125 MHz
50 MHz – 125 MHz
50 MHz – 125 MHz
50 MHz – 125 MHz
50 MHz – 125 MHz
50 MHz – 125 MHz
50 MHz – 125 MHz
50 MHz – 125 MHz
50 MHz – 125 MHz
50 MHz – 125 MHz
50 MHz – 125 MHz
50 MHz – 125 MHz
50 MHz – 114 MHz
50 MHz – 107 MHz
50 MHz – 100 MHz
50 MHz – 94 MHz
50 MHz – 88 MHz
50 MHz – 84 MHz
50 MHz – 80 MHz
50 MHz – 76 MHz
50 MHz – 72 MHz
50 MHz – 69 MHz
50 MHz – 66 MHz
50 MHz – 64 MHz
50 MHz – 61 MHz
50 MHz – 59 MHz
50 MHz – 57 MHz
50 MHz – 55 MHz
50 MHz – 53 MHz
50 MHz – 51 MHz
50 MHzBit Rate
1.0 Gb/s – 2.5 Gb/s
1.0 Gb/s – 2.5 Gb/s
1.0 Gb/s – 2.5 Gb/s
1.0 Gb/s – 2.5 Gb/s
1.0 Gb/s – 2.5 Gb/s
1.0 Gb/s – 2.5 Gb/s
1.0 Gb/s – 2.5 Gb/s
1.0 Gb/s – 2.5 Gb/s
1.0 Gb/s – 2.5 Gb/s
1.0 Gb/s – 2.5 Gb/s
1.0 Gb/s – 2.5 Gb/s
1.0 Gb/s – 2.5 Gb/s
1.0 Gb/s – 2.286 Gb/s
1.0 Gb/s – 2.133 Gb/s
1.0 Gb/s – 2.0 Gb/s
1.0 Gb/s – 1.882 Gb/s
1.0 Gb/s – 1.777 Gb/s
1.0 Gb/s – 1.684 Gb/s
1.0 Gb/s – 1.600 Gb/s
1.0 Gb/s – 1.523 Gb/s
1.0 Gb/s – 1.454 Gb/s
1.0 Gb/s – 1.391 Gb/s
1.0 Gb/s – 1.333 Gb/s
1.0 Gb/s – 1.280 Gb/s
1.0 Gb/s – 1.230 Gb/s
1.0 Gb/s – 1.185 Gb/s
1.0 Gb/s – 1.142 Gb/s
1.0 Gb/s – 1.103 Gb/s
1.0 Gb/s – 1.066 Gb/s
1.0 Gb/s – 1.032 Gb/s
1.0 Gb/s

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Note: maximum event clock for cPCI-EVG-220 is 100 MHz with 2.0 Gb/s bit rate

Fractional Synthesiser
For laboratory testing purposes the event clock may be generated on-board the event generator
using a fractional synthesiser. A Micrel (http://www.micrel.com) SY87739L Protocol
Transparent Fractional-N Synthesiser with a reference clock of 24 MHz is used. The following
table lists programming bit patterns for a few frequencies.
Event Rate
499.8 MHz/4= 124.95 MHz
499.654 MHz/4= 124.9135 MHz
476 MHz/4= 119 MHz106.25 MHz(fibre channel)
499.8 MHz/5= 99.96 MHz
50 MHz499.8 MHz/10= 49.98 MHz
499.654 MHz/4= 124.9135 MHz
50 MHzConfiguration Bit
Pattern
0x00FE816D

Reference Output
124.95 MHz

Precision(theoretical)
00x0C928166

124.907 MHz-52 ppm

0x018741AD

119 MHz00x049E81AD

106.25 MHz

00x025B41ED

99.956 MHz-40 ppm

0x009743AD
0x025B43AD

50.0 MHz49.978 MHz

0-40 ppm

0x0C928166

124.907 MHz-52 ppm

0x009743AD

50.0 MHz0Micro-Research Finland Oy
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Connections
cPCI-EVG-2x0 Front Panel Connections

LNK

RX

OFF

EVT

RF

TX

TRIG

PXI-EVG-220

Micro-Research

The front panel of the Event Generator and its optional side-by-side module is shown in Figure 11
and Figure 12.

UNIV0

UNIV1

UNIV2

UNIV3

PXI-EVSBS-220

Micro-Research

Figure 11: Event Generator Front Panel

UNIV4

UNIV5

UNIV6

UNIV7

UNIV8

UNIV9

Figure 12: Optional Side-by-side Module Front Panel

The front panel of the Event Generator includes the following connections and status leds:
Connector / Led
LNK

Style
Red/Green
Led

EVT

Red/Green
Led

TX
RX
RF
TRIG
UNIV0/1
UNIV2/3
UNIV4/5
UNIV6/5
UNIV8/9LC
LC
LEMO-EPY
LEMO-EPY
Universal slot
Universal slot
Universal slot
Universal slot
Universal slot

Level

opticalopticalRF
TTL

Description
Red: receiver violation detectedGreen: RX link OK, violation flagclearedGreen: link OK, flashes when eventcode received
Red: Flashes on led event
Transmit Optical Output (TX)
Receiver Optical Input (RX)RF/event clock input
AC Trigger input
Universal Input 0/1
Universal Input 2/3
Universal Input 4/5
Universal Input 6/7
Universal Input 8/9

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Micro-Research Finland Oy
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VME-EVG-230 Front Panel Connections

10/100

TX

RX

TTL

TTL

TTL

OUT4 OUT5

OUT3
OUT2

TTL

TTL

UNIV0

UNIV1

UNIV2

UNIV3

Micro
Research

10baseT

OUT0 OUT1ENA OUT ERR ACT

VME-EVG-230

IN0

ACIN

RX EVENT RX
FAIL LINK IN FAIL RUN
OFF

IN1

RFIN

The front panel of the Event Generator is shown in Figure 11.

COM

Figure 13: Event Generator Front Panel

The front panel of the Event Generator includes the following connections and status leds:
Connector / Led
FAIL
OFFRX LINKENA
EVENT IN
EVENT OUT
RX FAIL
ERR
RUN
ACT

Style
Red LedBlue Led
Green Led
Green Led
Yellow Led
Yellow Led
Red LedRed LedGreen Led
Yellow Led

Level

10baseT

RJ45

10baseT

10/100
TX
RX
ACIN
RFIN
IN0
IN1
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
UNIV0
UNIV1
UNIV2
UNIV3
COM

RJ45
LC
LC
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
LEMO-EPY
Universal I/O
Universal I/O
Universal I/O
Universal I/O
RJ45

opticalopticalTTL
RF +10 dBm
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

RS232

Description
Module Failure
Module Powered Down
Receiver Link Signal OK
Event Generator Enabled
Incoming Event (RX)Outgoing Event (TX)
Receiver Violation
SY87739L reference not locked
Ubicom IP2022 Running
Ubicom IP2022 Telnet connection
activeUbicom 10baseT Ethernet
Connection with link (green) andactive (amber) leds
(reserved)
Transmit Optical Output (TX)
Receiver Optical Input (RX)
Trigger input
RF Reference Input
Configurable front panel input
Configurable front panel input
Configurable front panel output
Configurable front panel output
Configurable front panel output
Configurable front panel output
Configurable front panel output
Configurable front panel output
Configurable Universal I/O input
Configurable Universal I/O input
Configurable Universal I/O input
Configurable Universal I/O input
Reserved

Micro-Research Finland Oy
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VME-EVG-230 VME P2 User I/O Pin Configuration
The following table lists the connections to the VME P2 User I/O Pins.
Pin
A1
A2
A3-A10
A11
A12
A13-A15
A16
A17-A26
A27-A31
A32
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12 – C27
C28
C29
C30
C31
C32

SignalTransition board ID0
Transition board ID1
GroundTransition board ID2
Transition board ID3
GroundTransition board handle switch
Ground+5V
Power control for transition board
Transition board input 0
Transition board input 1
Transition board input 2
Transition board input 3
Transition board input 4
Transition board input 5
Transition board input 6
Transition board input 7
Transition board input 8
Transition board input 9
Transition board input 10(reserved input)
Transition board input 11
Transition board input 12
Transition board input 13
Transition board input 14
Transition board input 15

cPCI-EVG-300 Front Panel Connections

Figure 14: cPCI-EVG-300 Event Receiver Front Panel

Connector / Led
UNIV0/1
UNIV2/3
UNIV4/5
UNIV6/7

Style
Universal slot
Universal slot
Universal slot
Universal slot

Level

Description
Universal Output 0/1
Universal Output 2/3
Universal Output 4/5
Universal Output 6/7

Micro-Research Finland Oy
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UNIV8/9
UNIV10/11
USB
10/100
TRIG
RF
Link TX (SFP)
Link RX (SFP)

Universal slot
Universal slot
USB
RJ45
Lemo
Lemo
LC
LC

TTL
RF +10 dBm
Optical 850 nm
Optical 850 nm

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Universal Output 8/9
Universal Output 10/11(USB Serial Port, reserved)(10/100 Ethernet, reserved)
TTL AC Trigger Input
RF Reference Input
Event link Transmit
Event link ReceiverMicro-Research Finland Oy
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Programming Details
VME-EVG-230 CR/CSR Support
The VME Event Generator module provides CR/CSR Support as specified in the VME64x
specification. The CR/CSR Base Address Register is determined after reset by the inverted stateof VME64x P1 connector signal pins GA4*-GA0*. In case the parity signal GAP* does notmatch the GAx* pins the CR/CSR Base Address Register is loaded with the value 0xf8 whichcorresponds to slot number 31.
Note: the board can be used in standard VME crates where geographical pins do not exist, in thiscase the user may either insert jumpers to set the geographical address or use the default setting
when the board’s CR/CSR base address will be set to 0xf8.
After power up or reset the board responds only to CR/CSR accesses with its geographicaladdress. Prior to accessing Event Generator functions the board has to be configured by accessing
the boards CSR space.
The Configuration ROM (CR) contains information about manufacturer, board ID etc. to identify
boards plugged in different VME slots. The following table lists the required field to locate an
Event Generator module.
CR address
0x27, 0x2B, 0x2F
0x33, 0x37, 0x3B, 0x3F

Register
Manufacturer’s ID (IEEE OUI)Board ID

EVG
0x000EB20x454700E6

For convenience functions are provided to locate VME64x capable boards in the VME crate.
STATUS vmeCRFindBoard(int slot, UINT32 ieee_oui, UINT32 board_id,
int *p_slot);

To locate the first Event Generator in the crate starting from slot 1, the function has to be called
following:#include “vme64x_cr.h”
int slot = 1;
int slot_evg;
vmeCRFindBoard(slot, 0x000EB2, 0x454700E6, &slot_evg);

or
vmeCRFindBoard(slot, MRF_IEEE_OUI, MRF_4CHTIM_BID, &slot_evg);

If this function returns OK, an Event Generator board was found in slot slot_evg.

Function 0/1/2 Registers
The Event Generator specific register are accessed via Function 0, 1 or 2 as specified in the
VME64x specification. To enable Function 0, the address decoder compare register for Function
0 in CSR space has to be programmed. For convenience a function to perform this is provided:
STATUS vmeCSRWriteADER(int slot, int func, UINT32 ader);Micro-Research Finland Oy
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To configure Function 0 of an Event Generator board in slot 3 to respond to A16 accesses at theaddress range 0x1800-0x1FFF the function has to be called with following values:
vmeCSRWriteADER(3, 0, 0x18A4);ADER contents are composed of the address mask and address modifier, the above is the sameas:vmeCSRWriteADER(3, 0, (slot << 11) | (VME_AM_SUP_SHORT_IO << 2));

To get the memory mapped pointer to the configured Function 0 registers on the Event Generator
board the following VxWorks function has to be called:
MrfEvgStruct *pEvg;
sysBusToLocalAdrs(VME_AM_SUP_SHORT_IO, (char *) (slot << 11),
(void *) pEvg);

Note: using the data transmission capability requires reserving more than 4 kbytes for function 0
i.e. use of addressing mode A24 is suggested, following:
vmeCSRWriteADER(3, 0, (slot << 19) | (VME_AM_STD_USR_DATA << 2));

MrfEvgStruct *pEvg;
sysBusToLocalAdrs(VME_AM_STD_USR_DATA, (char *) (slot << 19),
(void *) pEvg);

Micro-Research Finland Oy
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VME-EVG-230 Network Interface
A 10baseT network interface is provided to upgrade the FPGA firmware and set up boot options.
It is also possible to control the module over the network interface.

Assigning an IP Address to the Module
By default the modules uses DHCP (dynamic host configuration protocol) to acquire an IP
address. In case a lease cannot be acquired the IP address set randomly in the 169.254.x.x subnet.
The board can be programmed to use a static address instead if DHCP is not available.
The module can be located looking at the lease log of the DHCP server or using a Windows tool
called Locator.exe.

Using Telnet to Configure Module
To connect to the configuration utility of the module issue the following command:telnet 192.168.1.32 23

The latter parameter is the telnet port number and is required in Linux to prevent negotiation oftelnet parameters which the telnet server of the module is not capable of.
The telnet server responds to the following commands:
Commandbdh/?
im <address> [<data>]rsuqDescription
Show/change boot parameters, IP address etc.
Dump 16 bytes of memory
Show Help
Read & show dynamic configuration values from FPGA
Read/Write FPGA CR/CSR, Function 0
Reset Board
Save boot configuration & dynamic configuration values into nonvolatile memory
Update IP2022 software
Quit Telnet

Boot Configuration (command b)
Command b displays the current boot configuration parameters of the module. The parameter
may be changed by giving a new parameter value. The following parameters are displayed:
Parameter
Use DHCP
IP address
Subnet mask
Default GW
FPGA mode

Description
0 = use static IP address, 1 = use DHCP to acquire address, net masketc.
IP address of module
Subnet mask of module
Default gateway
FPGA configuration mode
0 – FPGA is not configured after power upMicro-Research Finland Oy
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1 – FPGA configured from internal Flash memory
2 – FPGA is configured from FTP server
FTP server IP address where configuration bit file resides
FTP server username
FTP server password
FTP server configuration file name
Configuration file name on internal flash
Integer divider to get from event clock to 1MHz, e.g. 125 for124.9135 MHz
Micrel SY87739UMI fractional divider configuration word to set
refenrence for event clock

FTP server
Username
Password
FTP Filename
Flash Filenameµs divider
Fractional divider
configuration word

Note that after changing parameters the parameters have to be saved to internal flash by issuing
the Save boot configuration (s) command. The changes are applied only after resetting themodule using the reset command or hardware reset/power sequencing.

Memory dump (command d)This command dumps 16 bytes of memory starting at the given address, if the address is omitted
the previous address value is increased by 16 bytes.
The most significant byte of the address determines the function of the access:Address
0x00000000
0x80000000

Function
CR/CSR space access
EVG registers accessTo dump the start of the EVG register map issue the ‘d’ command from the telnet prompt:
VME-EVG-230 -> d 80000000 ↵Addr 80000000: d000 0001 0000 0000 0000 0000 0000 0000
VME-EVG-230 -> d ↵Addr 80000010: 0000 0000 0000 0000 0000 0000 0000 0000
VME-EVG-230 ->Memory modify (commands d and m)
The access size is always a short word i.e. two bytes.
To check the status register from the telnet prompt:
VME-EVG-230 -> m 80000000 ↵Addr 80000000 data d000
VME-EVG-230 ->To enable the EVG issue:
VME-EVG-230 -> m 80000000 0000 ↵Addr 80000000 data 4001
VME-EVG-230 ->Micro-Research Finland Oy
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Upgrading IP2022 Microprocessor Software (command u)
To upgrade the Ubicom IP2022 microprocessor software download the upgrade image containing
the upgrade to the module using TFTP:LinuxIn Linux use e.g. interactive tftp:$ tftp 192.168.1.32
tftp> bintftp> put upgrade.bin /fw
tftp> quit

Windows
In Windows command prompt issue the following command:
C:\> tftp –i 192.168.1.32 PUT upgrade.bin /fw

When the upgrade image has been downloaded and verified, enter at the telnet prompt following:
VME-EVG-230 -> u ↵Really update firmware (yes/no) ? yes ↵Self programming triggered.

The Event Generator starts programming the new software and restarts.

Upgrading FPGA Configuration File
When the FPGA configuration file resides in internal flash memory a new file system image has
to be downloaded to the module. This is done using TFTP protocol:

Linux
In Linux use e.g. interactive tftp:$ tftp 192.168.1.32
tftp> bintftp> put filesystem.bin /tftp> quit

Windows
In Windows command prompt issue the following command:
C:\> tftp –i 192.168.1.32 PUT filesystem.bin /Now the FPGA configuration file has been upgraded and the new configuration is loaded after
next reset/power sequencing.
Note! Due to the UDP protocol it is recommended to verify (read back and compare) the
filesystem image before restarting the module. This is done following:Micro-Research Finland Oy
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Linux
In Linux use e.g. interactive tftp:$ tftp 192.168.1.32
tftp> bintftp> get / verify.bin
tftp> quit
$ diff filesystem.bin verify.bin$

If files differ you should get following message:
Binary files filesystem.bin and verify.bin differ

Windows
In Windows command prompt issue the following command:
C:\> tftp –i 192.168.1.32 GET / verify.bin
C:\> fc /b filesystem.bin verify.bin
Comparing files filesystem.bin and verify.bin
FC: no differences encountered

UDP Remote Programming Protocol
The VME-EVG can be remotely programmed using the 10baseT Ethernet interface with aprotocol over UDP (User Datagram Protocol) which runs on top of IP (Internet Protocol). The
default port for remote programming is UDP port 2000. The UDP commands are built upon thefollowing structure:access_type (1 byte)

status (1 byte)
address (4 bytes)
ref (4 bytes)

data (2 bytes)

The first field defines the access type:access_type
0x01
0x02

Description
Read Register from module
Write and Read back Register from module

The second field tells the status of the access:Status0-1-2-3

Description
Command OK
Bus ERROR (Invalid read/write address)
Timeout (FPGA did not respond)
Invalid command

The access size is always a short word i.e. two bytes. The most significant byte of the address
determines the function of the access:Address

Function

Micro-Research Finland Oy
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0x00000000
0x80000000

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CR/CSR space access
EVG registers access

Read Access (Type 0x01)
The host sends a UDP packet to port 2000 of the VME-EVG with the following contents:
access_type (1 byte)
0x01

status (1 byte)
data (2 bytes)
0x00
0x0000address (4 bytes)
0x80000000 (Control and Status register Function 0 address)
ref (4 bytes)
0x00000000

If the read access is successful the VME-EVG replies to the same host and port the message camefrom with the following packet:
access_type (1 byte)
0x01

status (1 byte)
data (2 bytes)
0x00
0xD000address (4 bytes)
0x80000000 (Control and Status register Function 0 address)
ref (4 bytes)
0x00000000

Write Access (Type 0x02)
The host sends a UDP packet to port 2000 of the VME-EVG with the following contents:
access_type (1 byte)
0x02

status (1 byte)
data (2 bytes)
0x00
0x0001
Address (4 bytes)
0x80000002 (Event enable register Function 0 address)
ref (4 bytes)
0x00000000

If the write access is successful the VME-EVG replies to the same host and port the message
came from with the following packet:
access_type (1 byte)
0x02

status (1 byte)
data (2 bytes)
0x00
0x0001address (4 bytes)
0x80000002 (Event enable register Function 0 address)
ref (4 bytes)
0x00000000

Notice that in the reply message the data returned really is the data read from the address
specified in the address field so one can verify that the data really was written ok.

Micro-Research Finland Oy
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Register Map
Address
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x020
0x024
0x028
0x02C
0x034
0x038
0x04C
0x050
0x060
0x064

Register
StatusControl
IrqFlag
IrqEnable
ACControl
ACMap
SWEvent
DataBufControl
DBusMap
DBusEvents
FWVersion
TSControl
TSValue
UsecDivider
ClockControl
EvanControl
EvanCodeType
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32

0x068
0x06C
0x070
0x074
0x080

EvanTimeHigh
EvanTimeLow
SeqRamCtrl0
SeqRamCtrl1
FracDiv

UINT32
UINT32
UINT32
UINT32
UINT32

0x100
0x104
0x108
0x10C
0x110
0x114
0x118
0x11C
0x180
0x184
0x188
0x18C
0x190
0x194
0x198
0x19C

EvTrig0
EvTrig1
EvTrig2
EvTrig3
EvTrig4
EvTrig5
EvTrig6
EvTrig7
MXCCtrl0
MXCPresc0
MXCCtrl1
MXCPresc1
MXCCtrl2
MXCPresc2
MXCCtrl3
MXCPresc3

UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32

Description
Status Register
Control Register
Interrupt Flag Register
Interrupt Enable RegisterAC divider control
AC trigger event mapping
Software event register
Data Buffer Control Register
Distributed Bus Mapping Register
Distributed Bus Timestamping Events Register
Firmware Version Register
Timestamp event generator control register
Timestamp event generator value register
Divider to get from Event Clock to 1 MHz
Event Clock Control Register
Event Analyser Control Register
Event Analyser Distributed Bus and Event
Code Register
Event Analyser Time Counter (bits 63 – 32)
Event Analyser Time Counter (bits 31 – 0)
Sequence RAM 0 Control Register
Sequence RAM 1 Control Register
Micrel SY87739L Fractional Divider
Configuration Word
Event Trigger 0 Register
Event Trigger 1 Register
Event Trigger 2 Register
Event Trigger 3 Register
Event Trigger 4 Register
Event Trigger 5 Register
Event Trigger 6 Register
Event Trigger 7 Register
Multiplexed Counter 0 Control Register
Multiplexed Counter 0 Prescaler Register
Multiplexed Counter 1 Control Register
Multiplexed Counter 1 Prescaler Register
Multiplexed Counter 2 Control Register
Multiplexed Counter 2 Prescaler Register
Multiplexed Counter 3 Control Register
Multiplexed Counter 3 Prescaler Register

Micro-Research Finland Oy
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0x1A0
0x1A4
0x1A8
0x1AC
0x1B0
0x1B4
0x1B8
0x1BC
0x400
0x402
0x404
0x406
0x440
0x442
0x444
0x446
0x448
0x44A
0x44C
0x44E
0x450
0x452
0x500
0x504
0x540
0x544
0x548
0x54C
0x550
0x554
0x558
0x55C
0x560
0x564
0x600
0x604
0x608
0x60C
0x610
0x614
0x618
0x61C
0x620
0x624

MXCCtrl4
MXCPresc4
MXCCtrl5
MXCPresc5
MXCCtrl6
MXCPresc6
MXCCtrl7
MXCPresc7
FPOutMap0
FPOutMap1
FPOutMap2
FPOutMap3
UnivOutMap0
UnivOutMap1
UnivOutMap2
UnivOutMap3
UnivOutMap4
UnivOutMap5
UnivOutMap6
UnivOutMap7
UnivOutMap8
UnivOutMap9FPInMap0
FPInMap1
UnivInMap0
UnivInMap1
UnivInMap2
UnivInMap3
UnivInMap4
UnivInMap5
UnivInMap6
UnivInMap7
UnivInMap8
UnivInMap9
TBInMap0
TBInMap1
TBInMap2
TBInMap3
TBInMap4
TBInMap5
TBInMap6
TBInMap7
TBInMap8
TBInMap9

UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT16
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32
UINT32Document: EVG-MRM-0005.doc
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Multiplexed Counter 4 Control Register
Multiplexed Counter 4 Prescaler Register
Multiplexed Counter 5 Control Register
Multiplexed Counter 5 Prescaler Register
Multiplexed Counter 6 Control Register
Multiplexed Counter 6 Prescaler Register
Multiplexed Counter 7 Control Register
Multiplexed Counter 7 Prescaler Register
Front Panel Output 0 Mapping Register
Front Panel Output 1 Mapping Register
Front Panel Output 2 Mapping Register
Front Panel Output 3 Mapping Register
Universal Output 0 Mapping Register
Universal Output 1 Mapping Register
Universal Output 2 Mapping Register
Universal Output 3 Mapping Register
Universal Output 4 Mapping Register
Universal Output 5 Mapping Register
Universal Output 6 Mapping Register
Universal Output 7 Mapping Register
Universal Output 8 Mapping Register
Universal Output 9 Mapping Register
Front Panel Input 0 Mapping Register
Front Panel Input 1 Mapping Register
Front Panel Universal Input 0 Map Register
Front Panel Universal Input 1 Map Register
Front Panel Universal Input 2 Map Register
Front Panel Universal Input 3 Map Register
Front Panel Universal Input 4 Map Register
Front Panel Universal Input 5 Map Register
Front Panel Universal Input 6 Map Register
Front Panel Universal Input 7 Map Register
Front Panel Universal Input 8 Map Register
Front Panel Universal Input 9 Map Register
Transition Board Input 0 Mapping Register
Transition Board Input 1 Mapping Register
Transition Board Input 2 Mapping Register
Transition Board Input 3 Mapping Register
Transition Board Input 4 Mapping Register
Transition Board Input 5 Mapping Register
Transition Board Input 6 Mapping Register
Transition Board Input 7 Mapping Register
Transition Board Input 8 Mapping Register
Transition Board Input 9 Mapping Register

Micro-Research Finland Oy
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0x628
0x62C
0x630
0x634
0x638
0x63C
0x800 –
0xFFF
0x8000 –0xBFFF
0xC000 –0xFFFF

TBInMap10
TBInMap11
TBInMap12
TBInMap13
TBInMap14
TBInMap15
DataBuf

UINT32
UINT32
UINT32
UINT32
UINT32
UINT32Document: EVG-MRM-0005.doc
Page: 28 of 51

Transition Board Input 10 Mapping Register
Transition Board Input 11 Mapping Register
Transition Board Input 12 Mapping Register
Transition Board Input 13 Mapping Register
Transition Board Input 14 Mapping Register
Transition Board Input 15 Mapping Register
Data Buffer Transmit Memory

SeqRam0

Sequence RAM 0

SeqRam1

Sequence RAM 1

Status Register
address
0x000

bit 31
RDB7

bit 30
RDB6

bit 29RDB5

Bit 28RDB4

bit 27RDB3

bit 26RDB2

bit 25RDB1

bit 24RDB0

address0x001

bit 23
TDB7

bit 22
TDB6

bit 21
TDB5

bit 20
TDB4

bit 19TDB3

bit 18TDB2

bit 17TDB1

bit 16
TDB0

Bit
RDB7
RDB6
RDB5
RDB4
RDB3
RDB2
RDB1
RDB0
TDB7
TDB6
TDB5
TDB4
TDB3
TDB2
TDB1
TDB0

Function
Status of received distributed bus bit 7 (from upstream EVG)
Status of received distributed bus bit 6 (from upstream EVG)
Status of received distributed bus bit 5 (from upstream EVG)
Status of received distributed bus bit 4 (from upstream EVG)
Status of received distributed bus bit 3 (from upstream EVG)
Status of received distributed bus bit 2 (from upstream EVG)
Status of received distributed bus bit 1 (from upstream EVG)
Status of received distributed bus bit 0 (from upstream EVG)
Status of transmitted distributed bus bit 7
Status of transmitted distributed bus bit 6
Status of transmitted distributed bus bit 5
Status of transmitted distributed bus bit 4
Status of transmitted distributed bus bit 3
Status of transmitted distributed bus bit 2
Status of transmitted distributed bus bit 1
Status of transmitted distributed bus bit 0

Control Register
address
0x004

bit 31
EVGEN

bit 30
RXDIS

bit 29bit 28RXPWD FIFORS

bit 27

bit 26SRST

bit 25LEMDE

bit 24MXCRES

address
0x005

bit 23

bit 22

bit 21

bit 19bit 18bit 17

bit 16SRALT

Bit

Function

bit 20Document: EVG-MRM-0005.doc
Page: 29 of 51

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EVGEN
RXDIS
RXPWD
FIFORSSRSTLEMDEEvent Generator Master enable
Disable event reception
Receiver Power down
Reset RX Event Fifo
Soft reset IP
Little endian mode (cPCI-EVG-300)
0 – PCI core in big endian mode (power up default)
1 – PCI core in little endian mode
MXCRES Write 1 to reset multiplexed counters
SRALT(reserved)

Interrupt Flag Register
address
0x008

bit 31

bit 30address
0x00a

bit 15address
0x00b

bit 29bit 28bit 27

bit 26bit 25

bit 14

bit 13
bit 12IFSSTO1 IFSSTO0

bit 11

bit 10

bit 9
bit 8
IFSSTA1 IFSSTA0

Bit 7

bit 6
IFEXT

bit 5
IFDBUF

bit 3

bit 2

bit 1
IFFF

bit 0
IFVIO

Bit
IFSSTO1IFSSTO0IFSSTA1IFSSTA0IFEXTIFDBUFIFFF
IFVIOFunction
Sequence RAM 1 sequence stop interrupt flag
Sequence RAM 0 sequence stop interrupt flag
Sequence RAM 1 sequence start interrupt flag
Sequence RAM 0 sequence start interrupt flag
External Interrupt flag
Data buffer flag
RX Event FIFO full flag
Receiver violation flag

bit 25bit 24Bit 4

bit 24

Interrupt Enable Register
address
0x00c

bit 31
IRQEN

bit 30
PCIIE

address
0x00e

bit 15address
0x00f

Bit 7

Bit
IRQEN
PCIIE

bit 29bit 28bit 27

bit 26bit 14

bit 13
bit 12IESSTO1 IESSTO0

bit 11

bit 10

bit 9
bit 8
IESSTA1 IESSTA0

bit 6
IEEXT

bit 5
IEDBUF

bit 3

bit 2

bit 1
IEFF

Bit 4

bit 0
IEVIO

Function
Master interrupt enable
PCI core interrupt enable (cPCI-EVG-300)
This bit is used by the low level driver to disable further interrupts before
the first interrupt has been handled in user space
IESSTO1 Sequence RAM 1 sequence stop interrupt enableMicro-Research Finland Oy
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IESSTO0IESSTA1IESSTA0IEEXTIEDBUFIEFF
IEVIO

Document: EVG-MRM-0005.doc
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Sequence RAM 0 sequence stop interrupt enable
Sequence RAM 1 sequence start interrupt enable
Sequence RAM 0 sequence start interrupt enable
External interrupt enable
Data buffer interrupt enable
Event FIFO full interrupt enable
Receiver violation interrupt enable

AC Trigger Control Register
address
0x011

bit 23

bit 22

bit 21

bit 20address
0x012

bit 15

Bit 14

bit 13

bit 12
bit 11
bit 10AC Trigger Divider

bit 9

bit 8

address
0x013

Bit 7

bit 6

bit 5

Bit 4
bit 3
bit 2
AC Trigger Phase Shift

bit 1

bit 0

Bit
ACBYP

Function
AC divider and phase shifter bypass (0 = divider/phase shifter enabled, 1= divider/phase shifter bypassed)
Synchronization select (0 = event clock, 1 = multiplexed counter 7
output)ACSYNCbit 19bit 18bit 17
bit 16ACBYP ACSYNC

AC Trigger Mapping Register
address
0x017

Bit 7
ACM7

bit 6
ACM6

bit 5
ACM5

Bit 4
ACM4

bit 3
ACM3

Bit
ACM7
ACM6
ACM5
ACM4
ACM3
ACM2
ACM1
ACM0

Function
If set AC circuit triggers Event Trigger 7
If set AC circuit triggers Event Trigger 6
If set AC circuit triggers Event Trigger 5
If set AC circuit triggers Event Trigger 4
If set AC circuit triggers Event Trigger 3
If set AC circuit triggers Event Trigger 2
If set AC circuit triggers Event Trigger 1
If set AC circuit triggers Event Trigger 0

bit 2
ACM2

bit 1
ACM1

bit 0
ACM0

Software Event Register
address
0x01A

bit 15

bit 14

bit 13address
0x01B

Bit 7

bit 6

bit 5

bit 12

bit 11

bit 10

Bit 4
bit 3
bit 2
Event Code to be sent out

bit 9
bit 8
SWPEND SWENA
bit 1

bit 0

Bit
Function
SWPEND Event code waiting to be sent out (read-only). A new event code may be
written to the event code register when this bit reads ‘0’.

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SWENA

Document: EVG-MRM-0005.doc
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Enable software event

Data Buffer Control Register
address
0x021

bit 23

bit 22

bit 21

bit 20

bit 19bit 18address
0x022

bit 15

Bit 14

bit 13

bit 12

bit 11

bit 10bit 9
DTSZ(10:8)

bit 8

address
0x023

Bit 7

bit 6

bit 5
Bit 4
DTSZ(7:2)

bit 3

bit 2

bit 1
0

bit 0
0

TXCPT TXRUN TRIG

Bits
TXCPT
TXRUN
TRIG
ENA

MODE

DTSZ(10:8)

bit 17

bit 16ENA

MODE

Function
Data Buffer Transmission Complete
Data Buffer Transmission Running – set when datatransmission has been triggered and has not been completed yet
Data Buffer Trigger Transmission
Write ‘1’ to start transmission of data in buffer
Data Buffer Transmission enable‘0’ – data transmission engine disabled‘1’ – data transmission engine enabled
Distributed bus sharing mode‘0’ – distributed bus not shared with data transmission‘1’ – distributed bus shared with data transmission
Data Transfer size 4 bytes to 2k in four byte increments

Distributed Bus Mapping Register
address
0x024

bit 31

bit 30
bit 29DBMAP7(3:0)

bit 28bit 27

bit 26bit 25
DBMAP6(3:0)

bit 24address
0x025

bit 23

bit 22
bit 21DBMAP5(3:0)

bit 20

bit 19bit 18bit 17
DBMAP4(3:0)

bit 16

address
0x026

bit 15

Bit 14
bit 13
DBMAP3(3:0)

bit 12

bit 11

bit 10
bit 9
DBMAP2(3:0)

bit 8address
0x027

Bit 7

bit 6
bit 5
DBMAP1(3:0)

Bit 4

bit 3

bit 2
bit 1
DBMAP0(3:0)

bit 0

Bits
Function
DBMAP7(3:0) Distributed Bus Bit 7 Mapping:
0 – Off, output logic ‘0’
1 – take bus bit from external input
2 – Multiplexed counter output mapped to distributed bus bit
3 – Distributed bus bit forwarded from upstream EVG

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DBMAP6(3:0)
DBMAP5(3:0)
DBMAP4(3:0)
DBMAP3(3:0)
DBMAP2(3:0)
DBMAP1(3:0)
DBMAP0(3:0)

Distributed Bus Bit 7 Mapping (see above for mappings)
Distributed Bus Bit 7 Mapping (see above for mappings)
Distributed Bus Bit 7 Mapping (see above for mappings)
Distributed Bus Bit 7 Mapping (see above for mappings)
Distributed Bus Bit 7 Mapping (see above for mappings)
Distributed Bus Bit 7 Mapping (see above for mappings)
Distributed Bus Bit 7 Mapping (see above for mappings)

Distributed Bus Event Enable Register
address
0x02B

bit 7
DBEV7

bit 6
DBEV6

Bits
DBEV5
DBEV6
DBEV7

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

DBEV5

Function
Distributed bus input 5 “Timestamp reset” 0x7D event enable
Distributed bus input 6 “Seconds ‘0’” 0x70 event enable
Distributed bus input 7 “Seconds ‘1’” 0x71 event enable

FPGA Firmware Version Register
address
0x02C

bit 31address
0x02D

bit 23address
0x02F

bit 7

bit 27

bit 26bit 24

EVG = 0x2

Form Factor
bit 8
Reserved
bit 0
Version ID

Bits

Function

Form Factor

0 – CompactPCI 3U
1 – PMC
2 – VME64x
3 – CompactRIO
4 – CompactPCI 6U

Timestamp Generator Control Register
address
0x037

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

TSGENA TSGLOAD
Bits
TSGENATSGLOAD

Function
Timestamp Generator Enable (‘0’ = disable, ‘1’ = enable)
Timestamp Generator Load new value into Timestamp Counter
Write ‘1’ to load new value

Document: EVG-MRM-0005.doc
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Microsecond Divider Register
address
0x04e

bit 15bit 0
Rounded integer value of 1 µs * event clock

For 100 MHz event clock this register should read 100, for 50 MHz event clock this registershould read 50. This value is used e.g. for the phase shifter in the AC input logic.

Clock Control Register
address
0x050

bit 31

bit 30address
0x051

bit 23

bit 22address
0x052
address
0x053

bit 29bit 28bit 27

bit 21
bit 20
bit 19RFDIV5 RFDIV4 RFDIV3

bit 26bit 25bit 24EXTRF

bit 18bit 17
RFDIV2 RFDIV1

bit 16
RFDIV0

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

RECDCM
RUN

RECDCM
INITDONERECDCM
PSDONE

EVDCM
STOPPED

EVDCM
LOCKED

EVDCM
PSDONECGLOCK

RECDCM
PSDEC

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

RECDCM
PSINC

RECDCM
RES

EVDCM
PSDEC

EVDCM
PSINC

EVDCM
SRUN

EVDCM
SRES

EVDCM
RES

RXCLKSEL

Bit

Function

RFSEL5-0

External RF divider select:
000000 – RF/1
000001 – RF/2
000010 – RF/3
000011 – RF/4
000100 – RF/5
000101 – RF/6000110 – RF/7000111 – RF/8
001000 – RF/9001001 – RF/10
001010 – RF/11001011 – RF/12001100 – OFF
001101 – RF/14
001110 – RF/15
001111 – RF/16
010000 – RF/17
010001 – RF/18
010010 – RF/19
010011 – RF/20
010100 – RF/21
010101 – RF/22
010110 – RF/23

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010111 – RF/24
011000 – RF/25
011001 – RF/26
011010 – RF/27
011011 – RF/28
011100 – RF/29
011101 – RF/30
011110 – RF/31
011111 – RF/32
EXTRF

CGLOCK

RF reference select:
0 – Use internal reference (fractional synthesizer)
1 – Use external RF reference
Micrel SY87739L locked (read-only)

Event Analyser Control Register
address
0x063

bit 7

Bits
EVANE

EVARS

EVAOF

EVAEN

EVACR

bit 6

bit 5

bit 4
EVANE

bit 3
EVARS

bit 2
EVAOF

bit 1
EVAEN

bit 0
EVACR

Function
Event Analyser FIFO not empty flag:
0 – FIFO empty
1 – FIFO not empty, events in FIFO
Event Analyser Reset
0 – not in reset
1 – reset
Event Analyser FIFO overflow flag:
0 – no overflow
1 – FIFO overflow
Event Analyser enable
0 – Event Analyser disabled
1 – Event Analyser enabled
Event Analyser 64 bit counter reset
0 – Counter running
1 – Counter reset to zero.

Event Analyser Data Register
address
0x066

bit 15bit 8(reserved)

bit 7

bit 0
Event CodeEvent Analyser Counter Registers
address
0x068

bit 31address

bit 31

bit 0
Event Analyser Counter Register (bits 63 – 32)
bit 0

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0x06C

Document: EVG-MRM-0005.doc
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Event Analyser Counter Register (bits 31 – 0)

Sequence RAM Control Registers
address
0x070

bit 31address
0x071

bit 23address
0x072

bit 15address
0x073

bit 30

bit 28bit 27

bit 26bit 25bit 24SQ0RUN

SQ0ENAbit 21

bit 20

bit 19bit 18bit 17

bit 16

SQ0SWT

SQ0SNG

SQ0RECSQ0RES

SQ0DIS

SQ0EN

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

bit 7

bit 6

bit 5

bit 4
bit 3
SQ0TSEL

bit 2

bit 1

bit 0

address
0x074

bit 31

bit 30

bit 29bit 28bit 26

address
0x075

bit 23

Address
0x076

bit 15Address
0x077

bit 7

Bit
SQxRUNSQxENASQxSWTSQxSNG
SQxREC
SQxRES
SQxDIS
SQxEN
SQxTSELbit 22

bit 29bit 22

bit 27

bit 25bit 24SQ1RUN

SQ1ENAbit 21

bit 20

bit 19bit 18bit 17

bit 16SQ1SWT

SQ1SNG

SQ1RECSQ1RES

SQ1DIS

SQ1EN

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

bit 6

bit 5

bit 4
bit 3
SQ1TSEL

bit 2

bit 1

bit 0

Function
Sequence RAM running flag (read-only)
Sequence RAM enabled flag (read_only)
Sequence RAM software trigger, write ‘1’ to trigger
Sequence RAM single mode
Sequence RAM recycle mode
Sequence RAM reset, write ‘1’ to reset
Sequence RAM disable, write ‘1’ to disable
Sequence RAM enable, write ‘1’ to enable/arm
Sequence RAM trigger select:
0 – trigger from MXC0
1 – trigger from MXC1
2 – trigger from MXC2
3 – trigger from MXC3
4 – trigger from MXC4
5 – trigger from MXC5
6 – trigger from MXC6
7 – trigger from MXC7
16 – trigger from AC synchronization logic
17 – trigger from sequence RAM 0 software trigger

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Document: EVG-MRM-0005.doc
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18 – trigger from sequence RAM 1 software trigger
24 – trigger from sequence RAM 0 external trigger
25 – trigger from sequence RAM 1 external trigger
31 – trigger disabled (default after power up)

SY87739L Fractional Divider Configuration Word
address
0x080

bit 31

bit 0
SY87739L Fractional Divider Configuration Word

Configuration Word
0x0C928166
0x0C9282A6
0x009743AD
0xC25B43AD
0x0176C36D

Frequency with 24 MHz reference oscillator
124.907 MHz
62.454 MHz
50 MHz49.978 MHz
49.965 MHz

Event Trigger Registers
Address
0x102

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8
EVEN0

Address
0x103

bit 7

bit 6

bit 5

bit 4
bit 3
EVCD0(7:0)

bit 2

bit 1

bit 0

Address
0x106

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8
EVEN1

Address
0x107

bit 7

bit 6

bit 5

bit 4
bit 3
EVCD1(7:0)

bit 2

bit 1

bit 0

Address
0x10A

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8
EVEN2

Address
0x10B

bit 7

bit 6

bit 5

bit 4
bit 3
EVCD2(7:0)

bit 2

bit 1

bit 0

Address
0x10E

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8
EVEN3

Address
0x10F

bit 7

bit 6

bit 5

bit 4
bit 3
EVCD3(7:0)

bit 2

bit 1

bit 0

Address
0x102

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8
EVEN4

Address
0x103

bit 7

bit 6

bit 5

bit 4
bit 3
EVCD4(7:0)

bit 2

bit 1

bit 0

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Address
0x106

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8
EVEN5

Address
0x107

bit 7

bit 6

bit 5

bit 4
bit 3
EVCD5(7:0)

bit 2

bit 1

bit 0

Address
0x10A

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8
EVEN6

Address
0x10B

bit 7

bit 6

bit 5

bit 4
bit 3
EVCD6(7:0)

bit 2

bit 1

bit 0

Address
0x10E

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8
EVEN7

Address
0x10F

bit 7

bit 6

bit 5

bit 4
bit 3
EVCD7(7:0)

bit 2

bit 1

bit 0

bit 26bit 25bit 24

Bit
EVENx
EVCDx

Function
Enable Event Trigger x
Event Trigger Code for Event trigger x

Multiplexed Counter Registers
address
0x180

bit 31
MXC0

bit 30
MXP0

bit 29bit 28bit 27address
0x183

Bit 7

bit 6

bit 5

Bit 4

Bit 3

bit 2

bit 1

bit 0

MX0EV7

MX0EV6

MX0EV5

MX0EV4

MX0EV3

MX0EV2

MX0EV1

MX0EV0address
0x184

bit 31

bit 0

address
0x188

bit 31MXC1address
0x18B

Bit 7

bit 6

bit 5

Bit 4

Bit 3

bit 2

bit 1

bit 0

MX1EV7

MX1EV6

MX1EV5

MX1EV4

MX1EV3

MX1EV2

MX1EV1

MX1EV0Multiplexed Counter 0 prescaler
bit 30
MXP1

bit 29bit 28bit 27

bit 26bit 25bit 24address
0x18C

bit 31

bit 0

Address
0x190

bit 31MXC2

Address
0x193

Bit 7

bit 6

bit 5

Bit 4

Bit 3

bit 2

bit 1

bit 0

MX2EV7

MX2EV6

MX2EV5

MX2EV4

MX2EV3

MX2EV2

MX2EV1

MX2EV0Multiplexed Counter 1 prescaler
bit 30
MXP2

bit 29bit 28bit 27

bit 26bit 25bit 24

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address
0x194

bit 31

bit 0

Address
0x198

bit 31MXC3

Address
0x19B

Bit 7

bit 6

bit 5

Bit 4

Bit 3

bit 2

bit 1

bit 0

MX3EV7

MX3EV6

MX3EV5

MX3EV4

MX3EV3

MX3EV2

MX3EV1

MX3EV0Multiplexed Counter 2 prescaler
bit 30
MXP3

bit 29bit 28bit 27

bit 26bit 25bit 24address
0x19C

bit 31

bit 0

Address
0x1A0

bit 31MXC4Address
0x1A3

Bit 7

bit 6

bit 5

Bit 4

Bit 3

bit 2

bit 1

bit 0

MX4EV7

MX4EV6

MX4EV5

MX4EV4

MX4EV3

MX4EV2

MX4EV1

MX4EV0Multiplexed Counter 3 prescaler
bit 30
MXP4

bit 29bit 28bit 27

bit 26bit 25bit 24address
0x1A4

bit 31

Bit 0

Address
0x1A8

bit 31MXC5Address
0x1AB

Bit 7

bit 6

bit 5

Bit 4

Bit 3

bit 2

bit 1

bit 0

MX5EV7

MX5EV6

MX5EV5

MX5EV4

MX5EV3

MX5EV2

MX5EV1

MX5EV0Multiplexed Counter 4 prescaler
bit 30
MXP5

bit 29bit 28bit 27

bit 26bit 25

Bit 24address
0x1AC

bit 31

bit 0

Address
0x1B0

bit 31MXC6

Address
0x1B3

Bit 7

bit 6

bit 5

Bit 4

Bit 3

bit 2

bit 1

bit 0

MX6EV7

MX6EV6

MX6EV5

MX6EV4

MX6EV3

MX6EV2

MX6EV1

MX6EV0Multiplexed Counter 5 prescaler
bit 30
MXP6

bit 29bit 28bit 27

bit 26bit 25bit 24address
0x1B4

bit 31address
0x1B8

bit 31
MXC7

address
0x1BB

Bit 7

bit 6

bit 5

Bit 4

Bit 3

bit 2

bit 1

bit 0

MX7EV7

MX7EV6

MX7EV5

MX7EV4

MX7EV3

MX7EV2

MX7EV1

MX7EV0address
0x1BC

bit 0
Multiplexed Counter 6 prescaler
bit 30
MXP7

bit 29bit 28bit 27

bit 26

bit 31

bit 25bit 24

Bit 0
Multiplexed Counter 7 prescaler

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Bit
MXCx
MXPx
MXxEV7MXxEV6MXxEV5MXxEV4MXxEV3MXxEV2MXxEV1
MXxEV0Document: EVG-MRM-0005.doc
Page: 39 of 51

Function
Multiplexed counter output status (read-only)
Multiplexed counter output polarity
Map rising edge of multiplexed counter x to send out event trigger 7
Map rising edge of multiplexed counter x to send out event trigger 6
Map rising edge of multiplexed counter x to send out event trigger 5
Map rising edge of multiplexed counter x to send out event trigger 4
Map rising edge of multiplexed counter x to send out event trigger 3
Map rising edge of multiplexed counter x to send out event trigger 2
Map rising edge of multiplexed counter x to send out event trigger 1
Map rising edge of multiplexed counter x to send out event trigger 0

Front Panel Output Mapping Registers
address
0x401
0x403
0x405
0x407

Bit 7

bit 6
bit 5
Bit 4
bit 3
bit 2
bit 1
Front panel OUT0 Mapping ID (see Table 2 for mapping IDs)
Front panel OUT1 Mapping ID
Front panel OUT2 Mapping ID
Front panel OUT3 Mapping ID

bit 0

Notes:cPCI-EVG does not have any Front panel outputs.
VME-EVG-230 has four Front panel outputs OUT0 to OUT3.

Universal Output Mapping Registers
address
0x441
0x443
0x445
0x447
0x449
0x44B
0x44D
0x44F
0x451
0x453

Bit 7

bit 6
bit 5
Bit 4
bit 3
bit 2
bit 1
Universal I/O OUT0 Mapping ID (see Table 2 for mapping IDs)
Universal I/O OUT1 Mapping ID
Universal I/O OUT2 Mapping ID
Universal I/O OUT3 Mapping ID
Universal I/O OUT4 Mapping ID
Universal I/O OUT5 Mapping ID
Universal I/O OUT6 Mapping ID
Universal I/O OUT7 Mapping ID
Universal I/O OUT8 Mapping ID
Universal I/O OUT9 Mapping ID

bit 0

Notes:cPCI-EVG has a maximum of four Universal I/O outputs and six additional outputs are provided by the optional side-by-side module.
VME-EVG-230 has a maximum four Universal I/O outputs.

Front Panel Input Mapping Registers
address
0x500

address
0x501
address
0x502

bit 31

bit 30

bit 29bit 28bit 27

bit 26bit 25bit 24
FP0IRQbit 23

bit 22

bit 21

bit 20

bit 19bit 18bit 17

bit 16

FP0DB7

FP0DB6

FP0DB5

FP0DB4

FP0DB3

FP0DB2

FP0DB1

FP0DB0

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

FP0SEQ1

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Address
0x503

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

FP0EV7

FP0EV6

FP0EV5

FP0EV4

FP0EV3

FP0EV2

FP0EV1FP0EV0address
0x505

bit 23

bit 22

bit 21

bit 20

bit 19bit 18bit 17

bit 16

FP1DB7

FP1DB6

FP1DB5

FP1DB4

FP1DB3

FP1DB2

FP1DB1FP1DB0Address
0x507

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

FP1EV7

FP1EV6

FP1EV5

FP1EV4

FP1EV3

FP1EV2

FP1EV1FP1EV0Bit
FPxIRQFPxDB7
FPxDB6FPxDB5FPxDB4
FPxDB3
FPxDB2FPxDB1FPxDB0FPxSEQ1
FPxSEQ0
FPxEV7
FPxEV6
FPxEV5
FPxEV4
FPxEV3
FPxEV2
FPxEV1
FPxEV0Function
Map Front panel Input x to External Interrupt
Map Front panel Input x to Distributed Bus bit 7
Map Front panel Input x to Distributed Bus bit 6
Map Front panel Input x to Distributed Bus bit 5
Map Front panel Input x to Distributed Bus bit 4
Map Front panel Input x to Distributed Bus bit 3
Map Front panel Input x to Distributed Bus bit 2
Map Front panel Input x to Distributed Bus bit 1
Map Front panel Input x to Distributed Bus bit 0
Map Front panel Input x to Sequence Trigger 1
Map Front panel Input x to Sequence Trigger 0
Map Front panel Input x to Event Trigger 7
Map Front panel Input x to Event Trigger 6
Map Front panel Input x to Event Trigger 5
Map Front panel Input x to Event Trigger 4
Map Front panel Input x to Event Trigger 3
Map Front panel Input x to Event Trigger 2
Map Front panel Input x to Event Trigger 1
Map Front panel Input x to Event Trigger 0

Universal Input Mapping Registers
address
0x540
address
0x541
address
0x542
Address
0x543

bit 31

bit 30

bit 29bit 28bit 27

bit 26bit 25bit 24
UI0IRQbit 23

bit 22

bit 21

bit 20

bit 19bit 18bit 17

bit 16

UI0DB7

UI0DB6

UI0DB5UI0DB4UI0DB3

UI0DB2

UI0DB1UI0DB0

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

UI0SEQ1

UI0SEQ0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

UI0EV7

UI0EV6

UI0EV5

UI0EV4

UI0EV3

UI0EV2

UI0EV1UI0EV0Bit
UIxIRQUIxDB7

Function
Map Universal Input x to External Interrupt
Map Universal Input x to Distributed Bus bit 7

Micro-Research Finland Oy
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Map Universal Input x to Distributed Bus bit 6
Map Universal Input x to Distributed Bus bit 5
Map Universal Input x to Distributed Bus bit 4
Map Universal Input x to Distributed Bus bit 3
Map Universal Input x to Distributed Bus bit 2
Map Universal Input x to Distributed Bus bit 1
Map Universal Input x to Distributed Bus bit 0
Map Front panel Input x to Sequence Trigger 1
Map Front panel Input x to Sequence Trigger 0
Map Universal Input x to Event Trigger 7
Map Universal Input x to Event Trigger 6
Map Universal Input x to Event Trigger 5
Map Universal Input x to Event Trigger 4
Map Universal Input x to Event Trigger 3
Map Universal Input x to Event Trigger 2
Map Universal Input x to Event Trigger 1
Map Universal Input x to Event Trigger 0

Note: all enabled input signals are OR’ed together. So if e.g. distributed bus bit 0 has two sourcesfrom universal input 0 and 1, if either of the inputs is active high also the distributed bus is active
high.

Transition Board Input Mapping Registers
address
0x540
address
0x541
address
0x542
Address
0x543

bit 31

bit 30

bit 29bit 28bit 27

bit 26bit 25bit 24
TI0IRQbit 23

bit 22

bit 21

bit 20

bit 19bit 18bit 17

bit 16

TI0DB7

TI0DB6

TI0DB5

TI0DB4

TI0DB3

TI0DB2

TI0DB1

TI0DB0

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

TI0SEQ1

TI0SEQ0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

TI0EV7

TI0EV6

TI0EV5

TI0EV4

TI0EV3

TI0EV2

TI0EV1

TI0EV0Bit
TIxIRQTIxDB7TIxDB6TIxDB5TIxDB4TIxDB3TIxDB2TIxDB1TIxDB0TIxSEQ1TIxSEQ0TIxEV7TIxEV6Function
Map Universal Input x to External Interrupt
Map Universal Input x to Distributed Bus bit 7
Map Universal Input x to Distributed Bus bit 6
Map Universal Input x to Distributed Bus bit 5
Map Universal Input x to Distributed Bus bit 4
Map Universal Input x to Distributed Bus bit 3
Map Universal Input x to Distributed Bus bit 2
Map Universal Input x to Distributed Bus bit 1
Map Universal Input x to Distributed Bus bit 0
Map Front panel Input x to Sequence Trigger 1
Map Front panel Input x to Sequence Trigger 0
Map Universal Input x to Event Trigger 7
Map Universal Input x to Event Trigger 6

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TIxEV5TIxEV4TIxEV3TIxEV2TIxEV1TIxEV0

Map Universal Input x to Event Trigger 5
Map Universal Input x to Event Trigger 4
Map Universal Input x to Event Trigger 3
Map Universal Input x to Event Trigger 2
Map Universal Input x to Event Trigger 1
Map Universal Input x to Event Trigger 0

Note: all enabled input signals are OR’ed together. So if e.g. distributed bus bit 0 has two sourcesfrom universal input 0 and 1, if either of the inputs is active high also the distributed bus is active
high.

Application Programming Interface (API)A Linux device driver and application interface is provided to setup up the Event Generator.

Function Reference
int EvgOpen(struct MrfEgRegs **pEg, char *device_name);
Description
Parameters

struct MrfEgRegs **pEg

char *device_name

Return value

Opens the EVG device for access. Simultaneousaccesses are allowed.
EvgOpen returns pointer to EVG registers bymemory mapping the I/O registers into user
space.
Holds the device name of the EVG, e.g.
/dev/ega3. The device names are set up by themodule_load script of the device driver.
Return file descriptor on success.
Returns -1 on error.

int EvgClose(int fd);
Description
Parameters
Return value

int fdCloses the EVG device after opening by
EvgOpen.
File descriptor returned by EvgOpen
Returns zero on success.
Returns -1 on error.

int EvgEnable(volatile struct MrfEgRegs *pEg, int state);
Description
Parameters

volatile struct MrfEgRegs *pEg
int state

Return value

Enables the EVG and allows sending eventcodes.
Pointer to memory mapped EVG registerbase.
0: disable
1: enable
Returns zero when EVG disabled
Returns non-zero when EVG enabledMicro-Research Finland Oy
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int EvgGetEnable(volatile struct MrfEgRegs *pEg);
Description
Parameters

volatile struct MrfEgRegs *pEg

Return value

Retrieves state of the EVG.
Pointer to memory mapped EVG register
base.
Returns zero when EVG disabled
Returns non-zero when EVG enabled

int EvgRxEnable(volatile struct MrfEgRegs *pEg, int state);
Description
Parameters

volatile struct MrfEgRegs *pEg
int state

Return value

Enables/disables the EVG receiver.
Pointer to memory mapped EVG registerbase.
0: disable
1: enable
Returns zero when RX disabled
Returns non-zero when RX enabled

int EvgRxGetEnable(volatile struct MrfEgRegs *pEg);
Description
Parameters

volatile struct MrfEgRegs *pEg

Return value

Retrieves state of the EVG receiver.
Pointer to memory mapped EVG register
base.
Returns zero when RX disabled
Returns non-zero when RX enabled

int EvgGetViolation(volatile struct MrfEgRegs *pEg, int clear);
Description
Parameters

volatile struct MrfEgRegs *pEg
int clear

Return value

Get/clear EVG RX link violation status.
Pointer to memory mapped EVG registerbase.
0: don’t clear
1: clear status
Returns 0 when no violation detected.
Return non-zero when violation detected.

int EvgSWEventEnable(volatile struct MrfEgRegs *pEg, int state);
Description
Parameters

volatile struct MrfEgRegs *pEg
int state

Return value

Enable sending of software event codes.
Pointer to memory mapped EVG registerbase.
0: disable
1: enable
Returns zero when EVG SW events disabled
Returns non-zero when EVG SW events
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int EvgGetSWEventEnable(volatile struct MrfEgRegs *pEg);
Description
Parameters

volatile struct MrfEgRegs *pEg

Return value

Retrieve state of software event codes.
Pointer to memory mapped EVG register
base.
Returns zero when EVG SW events disabled
Returns non-zero when EVG SW events
enabledint EvgSendSWEvent(volatile struct MrfEgRegs *pEg, int code);
Description
Parameters

volatile struct MrfEgRegs *pEg
int code

Return value

Send software event code.
Pointer to memory mapped EVG register
base.
Event code to be sent out
Returns code sent out.

int EvgEvanEnable(volatile struct MrfEgRegs *pEg, int state);
Description
Parameters

volatile struct MrfEgRegs *pEg
int state

Return value

Enable/disable EVG event analyzer.
Pointer to memory mapped EVG registerbase.
0: disable
1: enable
Returns zero when EVG event analyzer
disabled
Returns non-zero when EVG SW event
analyzer enabled

int EvgEvanGetEnable(volatile struct MrfEgRegs *pEg);
Description
Parameters

volatile struct MrfEgRegs *pEg

Return value

Get EVG event analyzer state.
Pointer to memory mapped EVG register
base.
Returns zero when EVG event analyzer
disabled
Returns non-zero when EVG SW event
analyzer enabled

void EvgEvanReset(volatile struct MrfEgRegs *pEg);
Description
Parameters
Return value

volatile struct MrfEgRegs *pEg

Reset EVG event analyzer state.
Pointer to memory mapped EVG register
base.
none

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void EvgEvanResetCount(volatile struct MrfEgRegs *pEg);
Description
Parameters

volatile struct MrfEgRegs *pEg

Return value

Reset EVG event analyzer time countervalue.
Pointer to memory mapped EVG register
base.
None

int EvgEvanGetEvent(volatile struct MrfEgRegs *pEg, struct
EvanStruct *evan);Description
Parameters

volatile struct MrfEgRegs *pEg
struct EvanStruct *evan

Return value

Retrieve one event from event analyzer.
Pointer to memory mapped EVG register
base.
Pointer to event analyzer structure to store
one event. (see egapi.h for structure details).
Returns zero on success.
Returns -1 if no events available in event
analyzer.

int EvgSetMXCPrescaler(volatile struct MrfEgRegs *pEg, int mxc,
unsigned int presc);
Description
Parameters

volatile struct MrfEgRegs *pEg
int mxc
unsigned int presc

Return value

Set multiplexed counter prescaler.
Pointer to memory mapped EVG register
base.
Multiplexed counter number 0-7.
32-bit prescaler value.
Returns zero on success.
Returns -1 on error.

int EvgSetMxcTrigMap(volatile struct MrfEgRegs *pEg, int mxc, intmap);
Description
Parameters

volatile struct MrfEgRegs *pEg
int mxc
int map

Return value

Set multiplexed counter to event trigger
mapping.
Pointer to memory mapped EVG register
base.
Multiplexed counter number 0-7.
Number of event trigger to map to.
Returns zero on success.
Returns -1 on error.

void EvgSyncMxc(volatile struct MrfEgRegs *pEg);
Description
Parameters

volatile struct MrfEgRegs *pEg

Synchronize multiplexed counters.
Pointer to memory mapped EVG registerbase.

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None

Return value

void EvgMXCDump(volatile struct MrfEgRegs *pEg);
Description
Parameters

volatile struct MrfEgRegs *pEg

Return value

Dump multiplexed counter registers.
Pointer to memory mapped EVG register
base.
None

int EvgSetDBusMap(volatile struct MrfEgRegs *pEg, int dbus, intmap);
Description
Parameters

volatile struct MrfEgRegs *pEg
int dbus
int map

Return value

Set distributed bus bit mappings.
Pointer to memory mapped EVG register
base.
Distributed bus bit number 0-7.
Distributed bus bit source:
C_EVG_DBUS_SEL_OFF: bit tied to zero
C_EVG_DBUS_SEL_EXT: external input
C_EVG_DBUS_SEL_MXC: multiplexedcounter
C_EVG_DBUS_SEL_FORWARD: fromupstream EVG
Returns zero on success.
Returns -1 on error.

void EvgDBusDump(volatile struct MrfEgRegs *pEg);
Description
Parameters

volatile struct MrfEgRegs *pEg

Return value

Dump distributed bus registers.
Pointer to memory mapped EVG register
base.
None

int EvgSetACInput(volatile struct MrfEgRegs *pEg, int bypass, int
sync, int div, int delay);
Description
Parameters

volatile struct MrfEgRegs *pEg
int bypass
int sync
int div
int delay

Return value

Set AC input parameters.
Pointer to memory mapped EVG registerbase.
0: use AC sync logic
1: bypass phase shifter and divider
0: don’t synchronize to MXC7
1: synchronize to MXC7
Divider 1 – 255
Phase shift in approx. 0.1 ms steps
Returns zero on success.
Returns -1 on error.

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int EvgSetACMap(volatile struct MrfEgRegs *pEg, int map);
Description
Parameters

volatile struct MrfEgRegs *pEg
int map

Return value

Set AC input event trigger mapping.
Pointer to memory mapped EVG register
base.
Number of event trigger to map to.
Returns zero on success.
Returns -1 on error.

void EvgACDump(volatile struct MrfEgRegs *pEg);
Description
Parameters

volatile struct MrfEgRegs *pEg

Return value

Dump AC input registers.
Pointer to memory mapped EVG register
base.
None

int EvgSetRFInput(volatile struct MrfEgRegs *pEg, int useRF, int div);
Description
Parameters

volatile struct MrfEgRegs *pEg
int useRF

int div

Return value

Set up event clock RF input.
Pointer to memory mapped EVG registerbase.
0: use internal reference (fractional
synthesizer)
1: use external RF input
C_EVG_RFDIV_1,
C_EVG_RFDIV_2, etc. see egapi.h fordetails.
Returns zero on success.
Returns -1 on error.

int EvgSetFracDiv(volatile struct MrfEgRegs *pEg, int fracdiv);
Description
Parameters

volatile struct MrfEgRegs *pEg
int fracdiv

Return value

Set fractional divider control word which
provides reference frequency for receiver.
Pointer to memory mapped EVG register
base.
Fractional divider control word
Returns control word written

int EvgSetSeqRamEvent(volatile struct MrfEgRegs *pEg, int ram, int
pos, unsigned int timestamp, int code);
Description
Parameters

volatile struct MrfEgRegs *pEg
int ramint pos

Write one event into Sequence RAM.
Pointer to memory mapped EVG register
base.
Number of Sequence RAM
0: RAM0
1: RAM1
Event position in memory: 0 – 2047

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unsigned int timestamp
int code
Return value

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Timestamp of event (32-bit)
Event code (8-bit)
Returns zero on success.
Returns -1 on error.

void EvgSeqRamDump(volatile struct MrfEgRegs *pEg, int ram);
Description
Parameters

volatile struct MrfEgRegs *pEg

Return value

Dump Sequence RAM registers.
Pointer to memory mapped EVG register
base.
None

int EvgSeqRamControl(volatile struct MrfEgRegs *pEg, int ram, int
enable, int single, int recycle, int reset, int trigsel);
Description
Parameters

volatile struct MrfEgRegs *pEg
int ramint enable
int single
int recycle
int reset
int trigsel
Return value

Setup Sequence RAM
Pointer to memory mapped EVG register
base.
Number of Sequence RAM
0: RAM0
1: RAM1
0: disable RAM
1: enable RAM
0: multi-sequence
1: single sequence
0: trigger mode
1: recycle mode (loop)
1: reset RAM
See egapi.h
Returns zero on success.
Returns -1 on error.

int EvgSeqRamSWTrig(volatile struct MrfEgRegs *pEg, int trig);
Description
Parameters

volatile struct MrfEgRegs *pEg
int trig

Return value

Software trigger Sequence RAM.
Pointer to memory mapped EVG registerbase.
0: software trigger 0
1: software trigger 1
Returns 0 on success.
Returns -1 on error.

void EvgSeqRamStatus(volatile struct MrfEgRegs *pEg, int ram);
Description
Parameters
Return value

volatile struct MrfEgRegs *pEg

Dump Sequence RAM status.
Pointer to memory mapped EVG register
base.
None

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int EvgSetUnivinMap(volatile struct MrfEgRegs *pEg, int univ, int trig,
int dbus);
Description
Parameters

volatile struct MrfEgRegs *pEg
int univ
int trig
int dbus

Return value

Set up universal input mappings.
Pointer to memory mapped EVG register
base.
Number of universal input (0-3 for EVG, 4-9
for side-by-side module)
Number of event trigger to map to.
Number of external distributed bus input to
map to.
Returns 0 on success.
Returns -1 on error.

void EvgUnivinDump(volatile struct MrfEgRegs *pEg);
Description
Parameters

volatile struct MrfEgRegs *pEg

Return value

Dump Universal input mappings.
Pointer to memory mapped EVG register
base.
None

int EvgSetTriggerEvent(volatile struct MrfEgRegs *pEg, int trigger, int
code, int enable);
Description
Parameters

volatile struct MrfEgRegs *pEg
int trigger
int code
int enable

Return value

Set up trigger events.
Pointer to memory mapped EVG register
base.
Number of trigger event
Event code
0: disable
1: enable
Returns 0 on success.
Returns -1 on error.

void EvgTriggerEventDump(volatile struct MrfEgRegs *pEg);
Description
Parameters

volatile struct MrfEgRegs *pEg

Return value

Dump Event trigger settings.
Pointer to memory mapped EVG register
base.
None

int EvgSetUnivOutMap(volatile struct MrfEgRegs *pEg, int output, intmap);
Description
Parameters

volatile struct MrfEgRegs *pEg

Set up universal output mappings.
Pointer to memory mapped EVG registerbase.

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int output
int map
Return value

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Universal Output number
Signal mapping (see egapi.h for details)
Returns 0 on success, -1 on error

int EvgSetDBufMode(volatile struct MrfEgRegs *pEg, int enable);
Description

Parameters

volatile struct MrfEgRegs *pEg
int enable

Return value

Enable/disable transmitter data buffer mode.
When data buffer mode is enabled every
other distributed bus byte is reserved for datatransmission thus the distributed bus
bandwidth is halved.
Pointer to memory mapped EVG registerbase.
0 – disable transmitter data buffer mode
1 – enable transmitter data buffer mode
Transmit data buffer status (see Error!
Reference source not found. on page
Error! Bookmark not defined. for bit
definitions).

int EvgGetDBufStatus(volatile struct MrfEgRegs *pEg);
Description

Parameters

volatile struct MrfEgRegs *pEg

Return value

Get transmit data buffer status. When data
buffer mode is enabled every other
distributed bus byte is reserved for datatransmission thus the distributed bus
bandwidth is halved.
Pointer to memory mapped EVG register
base.
Transmit data buffer status (see Error!
Reference source not found. on page
Error! Bookmark not defined. for bit
definitions).

int EvgSendDBuf(volatile struct MrfEgRegs *pEg, char *dbuf, int size);
Description

Parameters

volatile struct MrfEgRegs *pEg
char *dbuf
int size

Return value

Get transmit data buffer status. When data
buffer mode is enabled every other
distributed bus byte is reserved for datatransmission thus the distributed bus
bandwidth is halved.
Pointer to memory mapped EVG register
base.
Pointer to local data buffer
Size of data in bytes to be transmitted:
4, 8, 12, …, 2048.
Size of buffer being sent.
-1 on error.

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