AN-1549
APPLICATION NOTEOne Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Performance Optimization of the Integrated ADC on the ADuCM4050
INTRODUCTION
Many applications, such as vital signal monitoring, temperaturesensing, and imaging, require high resolution analog-to-digitalconverters (ADCs) with high dynamic range, which are costly
and power consuming.
This application note discusses oversampling and averaging
techniques and the effect of sampling clock and voltage
reference selection in optimizing the performance of the 12-bit
ADC in the ADuCM4050 system. This application note also
discusses the programming flow and an example applicationthat implements the oversampling and averaging technique on
the samples obtained from the ADC in the ADuCM4050.

ABOUT THE ADUCM4050
The ADuCM4050 microcontroller unit (MCU) is an ultra low
power, integrated mixed-signal microcontroller system forprocessing, control, and connectivity. The MCU system is based on
the Arm® Cortex-M4F processor. The MCU also has a collectionof digital peripherals, embedded static random access memory(SRAM) and flash memory, and an analog subsystem that provides
clocking, reset, and power management capabilities in addition
to an ADC subsystem.

The ADuCM4050 MCU provides a collection of power modes
and features such as dynamic and software controlled clock
gating and power gating to support extremely low dynamic andhibernate power.
Full specifications for the ADuCM4050 are available in the
ADuCM4050 data sheet.

ADC OPTIMIZATIONThe ADuCM4050 microcontrollers incorporate a fast, multichannel 12-bit ADC capable of operating up to a maximum of
1.8 MSPS. The ADC controller can be set up to perform a seriesof conversions and transfer data to the system using a dedicateddirect memory access (DMA) channel. This setting allows theprocessor to be in Flexi™ mode (minimizing the overall device
power consumption) and to perform other tasks.
The performance of the ADC can be improved in terms of oversampling and averaging, selection of the voltage reference, selectionof the sampling clock, and power consumption.

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Application Note

TABLE OF CONTENTS
Introduction ...................................................................................... 1

Selecting Sampling Clock Source ................................................6

About the ADuCM4050 .................................................................. 1

Power Optimization ..........................................................................7

ADC Optimization ........................................................................... 1

Low Power Mode in the Reference Buffer .................................7

Revision History ............................................................................... 2

Flexi Mode ......................................................................................7

Oversampling and Averaging.......................................................... 3

High Power Buck ...........................................................................7

Oversampling Concept ................................................................ 3
Selection of the Reference Voltage ................................................. 4

Implementation of the Oversampling and Averaging Technique..............................................................................................................8Internal Reference Voltage .......................................................... 4

Programming Flow .......................................................................8

Fast Discharge of the Internal Reference Buffer....................... 4

Application Example Overview .................................................... 11External Reference Voltage ......................................................... 4

Results .............................................................................................. 12

VBAT as Reference Voltage ............................................................ 4

References ........................................................................................ 13

PCB Recommendation ................................................................ 4
Selection of the Sampling Clock ..................................................... 6

REVISION HISTORY
7/2018—Revision 0: Initial Version

Rev. 0 | Page 2 of 13

Application Note

AN-1549OVERSAMPLING AND AVERAGING
The oversampling technique is one solution for effectively using
the integrated 12-bit ADC in applications.

This technique filters out the noise outside the signal bandwidth,
which increases the dynamic range by 10log10M, and increases
the ENOB by √√M, for an oversampling factor of M.

The ADC subsystem in the ADuCM4050 microcontrollers has
an option to implement the oversampling and averaging technique in a hardware controller without the need to have dedicatedsoftware running in the MCU. The ADC subsystem therefore
reduces the processor overhead and the energy spent in computing
the algorithm. The Oversampling Concept section explores theperformance improvement of the ADC using the oversampling
and averaging techniques.

Generally, for every doubling of the sampling frequency, the
SNR increases by 3 dB and the ENOB improves by 0.5 bits.
For example, in an ideal case, averaging the four 12-bit ADC
samples increases the ENOB by one bit and improves the
dynamic range by 6 dB.
Generally, an ADC has quantization noise, thermal noise, distortions due to the nonlinearity of the ADC, and some external
noise due to various factors such as clock and reference. Due tothese noises, the actual performance measures are not as exact
as the theoretical values. Consider a 12-bit ADC that has
10.5 noise free bits at 50 kSPS. Averaging two adjacent samples ofan input signal reduces the effective sampling frequency to 25 kSPS
and increases the noise free bits to 11 bits. Further averaging thefour adjacent samples reduces the effective sampling rate to12.5 kSPS and increases the noise free bits to 12.5 bits.

OVERSAMPLING CONCEPT
Oversampling is a process of sampling the input signal with afrequency higher than the Nyquist frequency, fS/2, where fS is
the sampling frequency.
Sample the input signal at M × fS and then average M samples toobtain one sample. The factor M is referred to as the oversampling
factor.
Consider an ideal n-bit ADC that has the quantization noise
distributed uniformly within the Nyquist band dc to fS/2, asshown in Part A of Figure 1. Sampling an input signal with thisADC at a much higher sampling rate (MfS) distributes the noiseover a wide bandwidth from dc to MfS/2, as shown in Part B of
Figure 1. Averaging every M sample acts as a digital filter andremoves much of the wideband noise without affecting the
input signal bandwidth. This process results in an increase in
the signal-to-noise ratio (SNR) in decibels, as shown in thefollowing equation:
SNR = 6.02N + 1.76 + 10log10M

Averaging adjacent samples reduces only the uncorrelated noisepresent in the signal, which reduces the noise floor of the ADC
and improves the SNR. However, the integral nonlinearity remains
unchanged. This technique can therefore be used to effectively
increase the dynamic range of the ADC at the expense of theoverall output sampling rate and extra digital hardware.
If the noise seen by the ADC is only the quantization noise,averaging does not improve the performance. In this case, introducing a small amount of white noise, known as dither, on the
input helps achieve a higher resolution by means of averaging. The
introduced noise must be uncorrelated to the input signal andmust be of sufficient amplitude to randomly toggle the converted
output. The histogram of the converted samples for such dithered
input follows a Gaussian distribution. Averaging on these samples
acts as a low-pass filter, which filters the noise and increases the
SNR.

(1)

where N is the effective number of bits (ENOB) of an ideal ADC.
Thus, a high resolution analog-to-digital conversion can beaccomplished with a low resolution ADC.
QUANTIZATION NOISE = q/ 12
q = 1 LSBPART AfS

NYQUISTOPERATION

Even if sufficient noise is introduced on the input and averaging
is performed on the oversampled values, the noise free bits may
not be as exact as the theoretical values. This limitation is due tothe total harmonic distortion (THD) of the converter.

ADC

M fS
ADC

OVERSAMPLING+ AVERAGING

2fS
DIGITAL FILTERREMOVED NOISEAVERAGING M
SAMPLES

fS
2

MfS
2

MfS

16622-001

PART BfS

Figure 1. Effect of Oversampling and Averaging in Frequency Domain

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AN-1549

Application Note

SELECTION OF THE REFERENCE VOLTAGE
Proper selection of the reference voltage is an important factor
in the ADC performance.
The ADuCM4050 microcontroller integrates a reference bufferthat can generate either 2.50 V or 1.25 V as the reference using
the integrated band gap reference. The battery voltage (VBAT) or
external voltage can also be selected as the reference. These settings
are mutually exclusive. Selecting both the internal buffer and VBAT
as the reference source disables the internal reference buffer andselects VBAT as the reference voltage.

INTERNAL REFERENCE VOLTAGE
Depending on the battery range indicated by the power supply
monitor status register (PMG_PSM_STAT, as shown in Figure 2),
either 2.5 V or 1.25 V can be selected as the reference in the
ADC configuration register (Register ADC_CFG, Bit VREFSEL,
as shown in Figure 3).
If the battery voltage is above 2.75 V, select 2.5 V or 1.25 V as theinternal ADC reference. If the battery voltage is less than 2.75 V,
select 1.25 V as the reference.

FAST DISCHARGE OF THE INTERNAL REFERENCE
BUFFER
The ADuCM4050 MCU allows fast switching from a higher to alower reference voltage. Perform this switching by enabling the fast
discharge bit in the ADC configuration register (set Register ADC_
CFG, Bit FAST_DISCH to 1).
The fast discharge can be enabled when switching•••

From 2.5 V to 1.25 V.
From VBAT to 1.25 V.
From VBAT to 2.5 V (if VBAT > 2.5 V).

EXTERNAL REFERENCE VOLTAGE
To select an external reference voltage, disable the internal reference
buffer by setting the internal reference enable bit in the ADC
configuration register (Register ADC_CFG, Bit REFBUFEN) to 0.
The external reference must not be more than the battery voltage.
The external reference source must be connected to the VREFP_ADC pin. While using the internal buffer, the VREFP_ADC pin
must be floating. The external reference source must be noise free
to improve the performance of the ADC.

VBAT AS REFERENCE VOLTAGE
The ADuCM4050 MCU has a special feature that switches theinternal reference to VBAT. This feature allows the ADC to use
the VBAT supply as the voltage reference and avoids the need toconnect an additional external source to the VREFP_ADC pin or
an on-board wire connection from the supply pin to the
VREFP_ADC pin.
To enable VREFP_ADC as VBAT, set the Bit VREFVBAT in
Register ADC_CFG to 1. Wait for a minimum of 700 μs andthen set the Bit VREFVBAT_DEL to 1. The delay of at least
700 μs is essential for proper switchover of internal reference to
VBAT.

PCB RECOMMENDATION
It is recommended to decouple the VREFP_ADC pin with a
4.7 µF capacitor in parallel with a 0.1 µF capacitor close to the
GND_VREFADC pin, which in turn must be tied to GND_DIG,
GND_ANA, and the exposed pad on the ADuCM4050. To achieve
the best performance from these decoupling components, the capacitors must be placed as close as possible to the device, ideallyright up against the device.

For example, when switching from 2.5 V to 1.25 V at room temperature, the switchover time reduces by 2% (from 45 ms to 0.9 ms).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VBATUNDR (R/W1C)
STATUS BIT INDICATING AN ALARM
THAT BATTERY IS BELOW 1.80V

RORANGE3 (R)VBAT RANGE3 (2.30V TO 1.6V)
RORANGE2 (R)VBAT RANGE2 (2.75V TO 2.30V)

VREGUNDR (R/W1C)
STATUS BIT FOR ALARM INDICATING
VREG IS BELOW 1VRORANGE1 (R)VBAT RANGE1 (>2.75V)

VREGOVR (R/W1C)
STATUS BIT FOR ALARM INDICATINGOVERVOLTAGE FOR VREG

RANGE3 (R/W1C)
VBAT RANGE3 (2.30V TO 1.60V)
RANGE2 (R/W1C)
VBAT RANGE2 (2.75V TO 2.30V)

RANGE1 (R/W1C)
VBAT RANGE1 (>2.75V)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 2. PMG_PSM_STAT Register

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16622-002

WICENACK (R)WIC ENABLE ACKNOWLEDGE
FROM CORTEXApplication Note

AN-1549
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VREFVBAT_DEL (R/W)
SET TO 1 AFTER MINIMUM DELAY OF 700µs
FROM VREFBAT FIELD BEING SET TO 1

PWRUP (R/W)
POWERING UP ADC
VREFSEL (R/W)
TO SELECT VREF AS 1.25V OR 2.5V

FAST_DISCH (R/W)
FOR FAST SWITCHOVER OF VREF FROM
2.5V TO 1.25V

REFBUFEN (R/W)
TO ENABLE INTERNAL REFERENCE BUFFER

TMPEN (R/W)
TO POWER UP TEMPERATURE SENSORVREFVBAT (R/W)
VREF VBATSINKEN (R/W)
TO ENABLE ADDITIONAL 50µA SINK CURRENTCAPABILITY AT 1.25V, 100µA CURRENTCAPABILITY AT 2.5V

EN (R/W)
TO ENABLE ADC SUBSYSTEM

16622-017

RST (R/W)
RESET INTERNAL BUFFERS AND REGISTERS
WHEN HIGHSTARTCAL (R/W)
TO START A NEW OFFSET CALIBRATION CYCLE

Figure 3. ADC_CFG Register

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AN-1549

Application Note

SELECTION OF THE SAMPLING CLOCK
The quality of the sampling clock in terms of jitter determines
the ADC performance. Optimal selection of the sampling clockis critical based on the choice of application. Jitter is the variation of
the placement of the clock edges, which results in a samplingtime error. This uncertainty in the sampling edges leads to nonuniformly spaced samples and degrades the converter noise
performance.
Estimate the clock jitter by observing the degradation in thenoise performance of the converter. Determine the SNR
limitations due to jitter by using the following equation:

Refer to the AN-756 Application Note, Sampled Systems and the
Effects of Clock Phase Noise and Jitter, for more information.
0
–20

(2)

CLOSE IN

BROADBAND

–120

–180
0.1

1

10

100

1000

FREQUENCY (Hz)Figure 5. Effect of ADC Clock Jitter on ADC Samples in Frequency Domain,
Jitter ≈ 4 ns
0
–20
–40
–60
–80
–100
–120
–140

16622-003

fS

–100

–160

f

SAMPLING CLOCK
WITH PHASE NOISE

–80

–140

AMPLITUDE (dB)A traditional way of observing clock jitter is by looking at clock
jitter spectrally, as shown in Figure 4. In Figure 4, because of thejitter present in the sampling clock, the ideal impulse responseis spread out, resulting in spectral leakage. Much of the energy
is distributed close to the desired frequency (known as close innoise), and much of the energy is also contained in the wide
bandwidth broadband (known as wideband noise). The close inphase noise smears the fundamental signal into a number of
frequency bins, which reduces the overall spectral resolution.

–60

16622-004

For an ideal 12-bit ADC with a sampling rate of 154 kSPS, theclock jitter requirement is approximately 412 ps for an input
frequency of 70 kHz, whereas if the input frequency is 300 Hz,
the jitter requirement is approximately 105 ns.

–40
AMPLITUDE (dB)

where:
fIN is the input frequency.
tJITTER(RMS) is the rms jitter of the sampling clock.

–160

Figure 4. Sampling Clock with Jitter in Frequency Domain

The sampling process is a multiplication of the sampling clock andthe analog input signal. This multiplication in the time domain
is equivalent to convolution in the frequency domain. Therefore,
when the spectrum of the sampling clock is convolved with a puresinewave input signal spectrum, the resultant spectrum also contains the spectral leakage of the sampling clock spectrum. Due tothis leakage, the noise performance of the converter isdegraded.
Figure 5 and Figure 6 show the effects of clock jitter on the
spectrum of ADC samples. The ADC is enabled in oversampling
mode to obtain 16-bit samples, and an input signal of 157 Hz is
sampled at 604 SPS. When a free running oscillator with a jitter

–180
0.1

1

10

100

FREQUENCY (Hz)1000

16622-005

SNR = −20log(2πfINtJITTER(RMS)) dB

of approximately 4 ns over a period of 1 sec is used to sample
the input frequency, the SNR of the sampled signal is degraded,
as shown in Figure 5. In the same setup, if a clock source withconsiderably less jitter (approximately 200 ps) is used to sample
the input signal, the degradation seen in the spectrum for theprevious case is not observed (as shown in Figure 6).

Figure 6. Effect of ADC Clock Jitter on ADC Samples in Frequency Domain,
Jitter ≈ 200 ps

SELECTING SAMPLING CLOCK SOURCEThe MCU allows the sampling clock source to be selected aseither the internal 26 MHz oscillator or the external 26 MHz
crystal oscillator. See the ADuCM4050 Ultra Low Power Arm
Cortex-M4F MCU with Integrated Power Management
Hardware Reference for details.

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Application Note

AN-1549

POWER OPTIMIZATION
When considering a system that uses an MCU with an integrated
ADC and that interfaces with many external sensors, using thelow power capability of the ADuCM4050 MCU enhances theperformance of the ADC in terms of reducing the overall noise
seen by the ADC subsystem. Enabling low power options also
optimizes the power consumption of the MCU. The Low Power
Mode in the Reference Buffer section, the Flexi Mode section,and the High Power Buck section describe the various features
present in the ADuCM4050 microcontroller.

LOW POWER MODE IN THE REFERENCE BUFFER
The internal reference buffer is capable of operating in low powermode when the ADC sampling rate is less than 100 kSPS. In low
power mode, the buffer consumes approximately 100 μA lesscurrent than in the regular mode of operation. Enable low powermode by setting the RBUFLP bit field of the reference buffer, lowpower mode register (Register ADC_CFG1) to 1.

Flexi MODE
While ADC is converting multiple samples, enable the DMA totransfer the samples from the ADC output buffer to the memory.
During this time, the Arm Cortex-M4F core can be put into Flexi
mode or can be used for any other functions, thereby reducing theoverall power consumption.
In Flexi mode, the peripherals and DMA are still clocked while
the core is sleeping. Therefore, DMA transfers can continue
between peripheral and memory as well as from one memory
location to another memory location. This low power MCU mode
also ensures a noise free environment during ADC conversions.

HIGH POWER BUCKThe high power buck (HP buck) is a capacitive buck converter
that reduces the overall current consumption of the device basedon the VBAT level. For battery voltages greater than 2.8 V, thecurrent consumption of the device decreases by approximately
50%.

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AN-1549

Application Note

IMPLEMENTATION OF THE OVERSAMPLING AND AVERAGING TECHNIQUE
PROGRAMMING FLOW3.

The following steps describe how to perform averaging overmultiple conversions on a single channel:

ACLK =WAIT (R/W)
PROGRAM THIS WITH 526/PCLKDIVCNT

Figure 8. ADC_PWRUP Register

Root ClockACLKDIV(3)

where Root Clock is the root clock frequency (26 MHz) andcan be sourced from high frequency oscillator, highfrequency crystal, phase-locked loop (PLL), or an external
general-purpose input/output (GPIO) clock source. Bydefault, the root clock is HFOSC. Ensure that ACLK ≤PCLK and ACLK ≤ HCLK. The maximum configured
ACLK must be 26 MHz.

4.

5.
6.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
PCLKDIVCNT (R/W)
PCLK DIVIDE COUNTPower-up wait is necessary for proper functioning of the
ADC. If Register CLKG_CLK_CTL1, Bit PCLKDIVCNT is 1,
the maximum power-up wait time needed for the ADC is526 clock cycles.
Select the internal 1.25 V or 2.5 V reference buffer as thereference voltage using the VREFSEL bit in Register ADC_
CFG.
Enable the internal reference buffer by setting the
REFBUFEN bit in Register ADC_CFG.
Enable low power mode for the reference buffer by setting
the RBUFLP bit in Register ADC_CFG1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

HCLKDIVCNT (R/W)
HCLK DIVIDE COUNTRBUFLP (R/W)
ENABLE LOW POWER MODE FOR
REFERENCE BUFFER
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Figure 9. ADC_CFG1 Register Diagram

7.

16622-006

ACLKDIVCNT (R/W)
ACLK DIVIDE COUNT

8.

Figure 7. CLKG_CLK_CTL1 Register

The sampling rate of the ADC is internally calculated from
ACLK, in which the acquisition phase is Register ADC_
CNV_TIME, Bit SAMPTIME + 1 ACLK cycle, and theconversion phase is 13 ACLK cycles taken by successive
approximation. The conversion phase is initiated at the endof the acquisition phase. Calculate the sampling rate byusing the following equation:

9.

ADC Sampling Rate =Root Clock ÷ ACLKDIV((14 + Sampling Time )× Oversampling Factor )(4)

The oversampling factor determines the number of samples tobe oversampled and averaged. The oversampling factor canaccept values from 1 to 256.
If the delay time is given in between ADC samples, use
Equation 5 to calculate the sampling rate.
2.

10.
11.
12.
13.

Note that the Delay Time cannot be a value less than 1.
Set the power-up ADC bit in the ADC configuration
register (Register ADC_CFG, Bit PWRUP) to 1 to power
up the ADC (see Figure 3).

ADC Sampling Rate =16622-008

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0

Set the ADC clock divider in the clock control register(Register CLKG_CLK_CTL1, Bit ACLKDIVCNT) todefine the ADC clock, ACLK, as determined by thefollowing equation:

16622-009

1.

Set the wait bit fields of the ADC power-up time register(Register ADC_PWRUP, wait bit fields) as 526 divided byRegister CLKG_CLK_CTL1, Bit PCLKDIVCNT.

Root Clock ÷ ACLKDIV

Enable the ADC subsystem by setting the EN bit inRegister ADC_CFG.
Wait at least 3.5 ms. This wait time is required by the internalreference buffer to reach the set reference buffer voltage level(1.25 V or 2.5 V). One of the general-purpose (GP) timers canbe used to wait for 3.5 ms. During this wait period, the device
can be put into Flexi mode to save system power and canbe woken up by the GP timer interrupt.
Check the state of the ADC ready to start converting the
bit on the ADC status register (Bit RDY, Register
ADC_STAT). If the bit is 1, the ADC is ready to start
converting.
Write 1 to clear the RDY bit on Register ADC_STAT (seeFigure 11).
Set the STARTCAL bit on Register ADC_CFG to start thecalibration cycle (see Figure 3).
Check the CALDONE bit on Register ADC_STAT. If the
bit is asserted, write 1 to clear the bit (see Figure 11).
Set the SEL bits in the ADC conversion configuration
register, Register ADC_CNV_CFG (see Figure 12), toselect a channel for conversion. For example, writing 1 tothese bits selects Channel 0.

( (14 + Sampling Time ) × Oversampling Factor ) + ( Delay Time + 2 )Rev. 0 | Page 8 of 13(5)

Application Note

AN-1549

DLY (R/W)
DELAY BETWEEN TWOCONSECUTIVE CONVERSIONSIN TERMS OF NUMBER OFACLK CYCLESSAMPTIME (R/W)
NUMBER OF CLOCKCYCLES (ACLK) REQUIREDFOR SAMPLING

16622-101

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0

Figure 10. ADC_CNV_TIME Register Diagram
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RDY (R/W1C)
INDICATES ADC IS READY TO
START CONVERTING, WHEN
USING EXTERNAL REFERENCE
BUFFERCALDONE (R/W1C)
INDICATES CALIBRATION IS DONE

DONE0 (R/W1C)
INDICATES CONVERSION DONE ON CHANNEL 0

TMP2DONE (R/W1C)
INDICATES CONVERSION IS DONE FORTEMPERATURE SENSING 2

DONE3 (R/W1C)
INDICATES CONVERSION DONE ON CHANNEL 3

DONE1 (R/W1C)
INDICATES CONVERSION DONE ON CHANNEL 1
DONE2 (R/W1C)
INDICATES CONVERSION DONE ON CHANNEL 2

DONE4 (R/W1C)
INDICATES CONVERSION DONE ON CHANNEL 4

TMPDONE (R/W1C)
INDICATES CONVERSION IS DONE FORTEMPERATURE SENSING

DONE5 (R/W1C)
INDICATES CONVERSION DONE ON CHANNEL 5BATDONE (R/W1C)
INDICATES CONVERSION DONE FOR BATTERYMONITORING

16622-010

DONE7 (R/W1C)
INDICATES CONVERSION DONE ON CHANNEL 7
DONE6 (R/W1C)
INDICATES CONVERSION DONE ON CHANNEL 6

Figure 11. ADC_STAT Register Diagram
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MULTI (R/W)
SET TO START MULTIPLECONVERSIONSSEL (R/W)
TO SELECT CHANNEL(S) TO CONVERTBAT (R/W)
TO ENABLE BATTERY MONITORINGSINGLE (R/W)
SET TO START SINGLECONVERSION

TMP2 (R/W)
TO SELECT TEMPERATURE MEASUREMENT 2

AUTOMODE (R/W)
TO ENABLE AUTO MODE

16622-011

TMP (R/W)
TO SELECT TEMPERATURE MEASUREMENT 1

DMAEN (R/W)
TO ENABLE DMA CHANNEL

Figure 12. ADC_CVN_CFG Register Diagram

RESULT (R)REGISTER TO STORE CONVERSIONRESULT FOR DMA

16622-102

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

Figure 13. ADC_DMA_OUT Register Diagram

14. Set the CNVDONE bit to 1 in the ADC interrupt enableregister (Register ADC_IRQ_EN) to enable the interrupt
function when the conversion is complete (see Figure 14).
15. Set the OS bit and the EN bit to 1 in the ADC averaging
configuration register (ADC_AVG_CFG) to enable
oversampling and averaging (see Figure 15).
16. Set the oversampling and averaging factor (M) in the factor
bit fields in the ADC averaging configuration register(ADC_AVG_CFG). Table 1 lists the factor that must be
programmed for a particular required resolution.
17. Set the single bit in Register ADC_CNV_CFG to 1 to starta single conversion (see Figure 12).

18. The conversion done interrupt is generated if the CNVDONE
bit in the ADC_IRQ_EN register is set. Check the conversion
done bit in the ADC_STAT register for the corresponding
channel (for example, Register ADC_STAT, Bit DONE0)
when the conversion done interrupt is generated.
19. Read the conversion output from the conversion result
register of the corresponding channel (for example,
ADC_CH0_OUT).
20. Write 1 to clear the conversion done bit in the ADC_STAT
register (for example, set Bit DONE0 to 1).
21. To obtain multiple oversampled and averaged samples,
repeat Step 1 to Step 15.

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AN-1549

Application Note•

22. Set the following DMA configurations:••••

DMA count = 9 for 10 conversions (DMA count =number of conversions − 1).
Source address is the address of the ADC_DMA_OUT
register (see Figure 13).
Source size is the half word.
Set the destination address of DMA as the SRAM
memory location address to store the conversion result.

Program the required increment in the destination
address.

23. Set the DMAEN bit in Register ADC_CNV_CFG to 1 in the
ADC conversion configuration register and enable the DMA.
24. Set the MULTI bit in Register ADC_CNV_CFG to 1 in the
ADC conversion configuration register to start the conversion.
25. When the DMA_DONE interrupt is generated, clear the
MULTI bit to disable further conversions in the interrupt
service routine (see Figure 16).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RDY (R/W)
SET TO ENABLE INTERRUPTWHEN ADC IS READY TO
CONVERT
ALERT (R/W)
SET TO ENABLE INTERRUPT ON
CROSSING LOWER OR HIGHER
LIMIT
OVF (R/W)
SET TO ENABLE INTERRUPT IN
CASE OF OVERFLOWCNVDONE (R/W)
SET IT TO ENABLE TO INTERRUPTAFTER CONVERSION IS DONE

16622-012

CALDONE (R/W)
SET IT TO ENABLE INTERRUPT FOR
CALIBRATION DONE

Figure 14. ADC_IRQ_EN Register Diagram

EN (R/W)
TO ENABLE AVERAGING
ON CHANNELS ENABLED
IN ENABLE REGISTER
OS (R/W)
ENABLE OVERSAMPLING

FACTOR (R/W)
PROGRAM AVERAGING
FACTOR FOR AVERAGINGENABLED CHANNELS(1 TO 256)

16622-013

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0

Figure 15. ADC_AVG_CFG Register Diagram

Table 1. Oversampling and Averaging Factor for Enhanced Resolution
Resolution Required
13-Bit14-Bit15-Bit16-BitOversampling and Averaging Factor (M)
0x02
0x08
0x20
0x80

Rev. 0 | Page 10 of 13

Number of Samples Used for Averaging
4
16
64
256

Application Note

AN-1549

APPLICATION EXAMPLE OVERVIEWThis section describes an application sequence to perform ADC
oversampling and averaging in power optimized mode.

receiver/transmitter (UART) interface. During ADC conversion
and DMA transfers, the core is in Flexi mode.

In this example, the ADC is enabled in oversampling andaveraging mode. The oversampling factor (M) is set at 256 toobtain 16-bit samples. The DMA is configured to capture andstore 1024 16-bit samples in SRAM locations. The samples arelater obtained by means of the universal asynchronous

Figure 16 shows the application flow for oversampling in
multiconversion mode.
Figure 17 shows the application sequence.

POWER-UPSTART

INITIALIZE ADC IN OVERSAMPLING
AND AVERAGING MODECONFIGURE DMA TO TRANSFER 1024
SAMPLES FROM ADC TO SRAMSTART DMA AND ADC CONVERSIONIN MULTI MODE

ENTER Flexi™

DMA_DONE INTERRUPTINITIATE UART AND DMA TO FETCH
THE SAMPLES FROM SRAM

EXIT

16622-014

WAKE UP FROM Flexi™

Figure 16. Application Flow for Oversampling in Multiconversion Mode

CM4 IN Flexi™ MODESRAM

ADC SUBSYSTEMANALOG INPUTCONVERT TO DIGITALANALOG INPUTANALOG INPUTON ADC INPUT
CHANNELANALOG INPUTAFTER 256 SAMPLES, ADC
SUBSYSTEM PERFORMS
AVERAGING, WHICH RESULTS
IN A SINGLE 16-BIT SAMPLEDMA—THE 16-BIT SAMPLE IS
STORED IN SRAM

1024 SAMPLES ARE
STORED IN SRAM

DMA—WAKE UP CM4
16622-015

CM4 WAKES UP.
THE DATA AVAILABLE
ON THE SRAM CAN BE
PROCESSED FURTHER
OR CAN BE SET OUT
ON UART

Figure 17. Application Sequence

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AN-1549

Application NoteRESULTSFor each oversampling factor (M), the ADC clock frequency isadjusted such that the throughput is always 604 SPS.

12.5

VREF = 2.5V (INT)VREF = 1.25V (INT)

12.0
11.5

ENOB

Figure 18 shows the ADC performance measurement describing
ENOB vs. the oversampling and averaging factor. Because the
ADC is not ideal, the ENOB is calculated based on the SNR in
Equation 1. The SNR is obtained by inputting a sinewave signal
with a frequency of 157 Hz from a signal generator to ADC
Channel 0.

11.0
10.5
10.0

9.0
1

4

16

64

OVERSAMPLING AND AVERAGING FACTOR

Figure 18. ENOB vs. Oversampling and Averaging Factor

Rev. 0 | Page 12 of 13

256

16622-016

9.5

Application Note

AN-1549

REFERENCES
Brannon, Brad. AN-756 Application Note. Sampled Systems
and the Effects of Clock Phase Noise and Jitter. Analog Devices,
2004.
Kester, Walt. “ADC Input Noise: The Good, the Bad, and the
Ugly. Is No Noise Good Noise?” Analog Dialogue Vol. 40,
February 2006.

Kester, Walt. 2005. The Data Conversion Handbook. Analog
Devices.
Reeder, Rob, Wayne Green, and Robert Shillito. “Analog-toDigital Converter Clock Optimization: A Test Engineering
Perspective.” Analog Dialogue Vol. 42, February 2008.

©2018 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.
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