VISUALSIM TRAINING

Agenda- Part 5: Software andNetworking Modeling
Software Modeling 578-586
Networking Modeling 587-609
Audio Video Bridging 610-621
TSN, Ethernet, Gateway 622-634
Integration 635-657
Version control- 658-664
Using Eclipse Debugger- 665-672
Use Cases 673-690

Software ModelingDefining Software Functionality❖ At a statistical-level, a delay value for each function is sufficient to trigger the traffic on thebus and the memory devices.
❖ At the hardware-level, an application-specific instruction allocation called instruction-mix
table provides an extremely accurate representation of a software task.
❖ Annotate performance-intensive portions of the code and generate instruction trace duringexecution. This last technique is good to test the architecture behavior for a benchmark or
set of benchmark. This is also good to evaluate how a piece of code will behave in a multicore environment.

Mapping Behavior to Architecture•SystemResources✔Mappers have cycles/time being fed to SystemResources✔Build a hierarchical SystemResource for emulating RTOS + Processor✔Extend SystemResource_Extend using the External_Port•Computed time used as service time in Timed/Shared Queue✔Queue + Server to emulate any processing resource•Architecture Library✔Use SoftwareMapper, Script or Input Port to trigger processing in hardware✔Create hardware platform using Hardware blocks•Using Script✔Script has a Timed_Queue and wait for delays, Queue for action and Scheduler callModeling Abstraction- Software-Level● Instruction Set Simulator provides the user the ability to load the Operating System and execute thecompiled code. This is a good solution for early software debugging. But it is not a good solution while
experimenting new architectures such as a new bus topology, different memory hierarchy, or processor
clock speed sizing.
● At the hardware-level, an application-specific instruction allocation called instruction-mix table provides
an extremely accurate representation of a software task.
● The application-specific instruction allocation technique is the most versatile and can be used forsoftware testing, hardware verification and architecture optimization.
● Using instruction-mix table method of software emulation, the designer can view the depth of thepipeline identify the cause of a stall, power management algorithm impact, memory hierarchy
operation, performance slowdown of load/store requests, and cache coherency algorithm quality. The
simulation reports provide significant visibility into the architecture operation and allow for great
optimization of the system throughput.

Instruction Mix Table● Each software task or thread has a number of
instructions and percentage of different types of
instructions.
Instruction Mix Table for a Software Task
● In the case of My_Task_1, we have 10% of
integer, 48% floating point, 10% logical, 7%
load-store, and 25% brand instructions.
● This table is fed into a software generator blockthat generates the instruction sequence basedon an intelligent algorithm.
● This sequence is used for the hardware testing,thus providing a more realistic test of theplatform architecture.
● One can modify the task instruction mix andstudy the impact on your architecture by simply
modifying the percentage table.

Modeling Software Blocks
Delays through the hardware platform
UML or Flow Chart model of the software with profiles
Generate instruction sequence◦ Synthetic or profile-driven
Link code execution with hardware model execution

Modeling Results• Software Tasks per Second (Min, Mean, StDev, Max)
• Software Deadlines Exceeded per Second (Min, Mean, StDev, Max)
• System Response Time vs. (Simulation Time, Histogram)• System Throughput vs. (Simulation Time, Histogram)• Hardware Efficiency (Utilization Summary)Software-based engineering discipline which involves◦ Modeling a system◦ Simulating and visualizing its behavior under real-world operating conditions◦ Refining its design through an iterative process
To be truly effective, it must include◦ Task graph analysis◦ Mapping of behavior to architecture◦ Extremely accurate representation of a software task
◦ Generating timing, power and behavior correctness

Solutions
Current solution◦ Software is defined as a task graph, traffic, trace file and profile-based task generator◦ Execute software on a device, FPGA or emulator

New solution◦ Using GEM5 to create a architectural prototype

Network ModelingOverview of the Network Block
Library• Used to tune the parameters of a computer network, design
the topology, develop new protocols and evaluate theapplication of a protocol for an application• Library provides the infrastructure to handle the routing,
Ethernet layer, fragmentation, retransmission, protocol
delays and network delays• Library also offers the user the ability construct custom

protocols of a particular layer of the protocol and use theinfrastructure to emulate the others• Links can be connected or connection-less• Multiple routing tables can exist in a single model

Network Library Location
Interfaces and Buses-> Networking

Fields Necessary for Network blocks• Task_Source: Source• Task_Destination: Destination• Task_Size: Data Size

• Task_Layer: Overhead Size

• Task_Hop: Next Node or if going up/down, it lists this as Up.

• Task_Number: Unique number over the whole model• Task_Trace: Array of all the Nodes that this transaction goes through“ Task_Class” DataStructure consists of the fields necessary for networking

Routing Table• Provides information for the network✔ Routing_Algorithm, Routing_Algorithm_Cost
Routing_Latencies, or Routing_Configuration• Must be instantiated with Database

Routing_Table Block Parameters• Routing_Table_Name: Routing table name must be unique• Propagation_Constant_C: This is a multiple of C where C is the speed of light. Thisis used for computing the link delay based on
Distance/(Propagation_Constant_C*C)• Routing_Algorithm: The default routing algorithm is the Dykstra algorithm. User
defined (i.e., custom) algorithms can be used as well.
• Routing_Algorithm_Cost: The type of cost function used in the determination ofpath• Routing_Latencies: Must be renamed to Distance Units

Database• Routing Table is defined• Must have the same name as that of the
Routing Table BlockNODE Block• Defines a basic Node within a large network• Finds the next hop in the network using
Routing Table• Can operate in Two modes✔ Connected Routing Table Mode
✔ Connectionless Routing Table Mode

• Used Network Message field to identify Retryand Drop• Two delays-✔ Data Transfer on the link (Task_Size/Bandwidth)✔ Propagation Delay (Distance/(Speed of Light *Propagation Constant)

Operation• The data can arrive at the Node from the Layer or from another node.
• When it arrives from another node, it checks the Network_Message == Retry or Drop_Packet. In thatcase, it checks whether the current node is the Source. If so, it sends it directly to the Layers. If it is not
the Source, it sends out to the next Hop. It does not send it to the Layers.
• If the Node cannot find the Next Hop to the Destination, it sends the packet back to the Source Node.
• If it comes from the Layers and a path exists, it updates Task_Hop and then sends it to the next Node.
• If it came from another Node, it sends it to the Layer.
• If this is the Destination, it immediately sends it to the Layer.

Node Block Parameters• Node Name: Name of this block. Required field
and must be unique• Routing Table Name: Name of the associatedrouting table

NODE- Statistics• Generated using✔ RegEX✔ NODE master• getBlockStatus("RT", "stats", 0) -> Returns subnet statistics forrouting table domain
getBlockStatus("RT", "stats", 1) -> Returns routing table for routing
table domain
getBlockStatus("RT", "stats", -1) ->Resets the routing table statistics
getRoutingTableHop("RT","Node_1","Node_2") -> Returns the next
node hop, if there is no hop, then this RegEx will return "none"NODE Master• Used to manipulate the operation of a networkfrom a central location✔ Add Link
✔ Remove Link
✔ Recompute the Routing table• Generates Statistics and current Routing tableNode Master Block Parameters• Routing Table Name: Name of the associated routing table• Link_Src_dest_Dist_BW: Specifies where the block will get the link information• Dynamic Routing: Specifies whether to add or remove a network link, or create a new routingtableLayer Table• Defines the characteristics of Protocol Layer✔ Fragmentation✔ Latency✔ Queueing

Layer Table Parameters• Layer Table Name: Name of Layer, such as MAC (name must be unique)• Layer Number: Number corresponding to layer, 1 through 7 valid
entries. Used internally be retry mechanism.
• Layer MBytes_Sec: Speed. This is the layer throughput in the upward or
downward direction in MBytes per second• Layer_Frame_Size_Bytes: This is maximum frame size that can betransmitted in the upward or downward direction• Layer_Header_Trailer_Bytes: Header/Trailer Bytes for
Layer_Frame_Size_Bytes• Layer_Queue_Size_Frames: Queue length of upward or downward
flow. This length equates to sessions.

Layer Protocol• Used to define each layer of Network Protocol
stack• Each Layer_Protocol must reference one
Layer_Table block• A layer block can add/remove the necessary
overhead bytes for header and trailers, delay theblock for the processing time, queue, force a retry,
and add custom logic and timing• Two delays✔ Data Transfer delay✔ Processing Delay (internal or external)

ds_dn_input

dn_ext_output
ds_dn_output

ds_up_output

up_ext_output
ds_up_input

External processing• Layer Configuration parameter must be set to External
Delay in Layer Table• Sends the data structure to the ports called'up_ext_output' (going up the stack) and'dn_ext_output' (going down the stack) to implement
the external delay• External process must be terminated with aLayer_Complete block, which returns the packet to theLayer_Protocol block to resume either up or down thelayer stack• Internal Delays are ignored

Statistics for Layer Protocol• Generate statistics using the RegEX function✔ getBlockStatus("MAC_1","Any Value", "stats", 1,"Any Integer") - stats✔ getBlockStatus("MAC_1","Any Value", "stats", -1,"Any Integer") - reset stats✔ getBlockStatus("MAC_1","Any Value", "length", 1,Any Integer) – up queue
length✔ getBlockStatus("MAC_1","Any Value", "length", 2,Any Integer) –down queue
lengthMulticast• Simulates Internet Multicast Protocol. Performs
Multicast and Broadcast• Spanning Tree algorithm for routing of packets• The Signal that has to be multicasted must havethe Network_Message field with the name of themulticast
Network_Message = “Multicast_1”• Configurations for Multicast must be done in
Variable List BlockNetworking Nodes
NODE N_4

NODE N_1

Routing_Table
NODE N_3

NODE N_2

RT

NODE N_5

Connected and Connectionless Nodes

Processing
Connected

NODE

NODE

ConnectionlessNetwork Node Layers
Network
Data Link
Physical

Layer

Layer

Layer

Layer

NODE

NODE

Layer_TableLT
Routing_Table
RTNetwork Node Layers (continued)
Functionality and Delay

Functionality and Delay

Network

Layer

Layer

Data Link

Layer

Layer

NODE

NODE

PhysicalNetwork Node Layers ( continued)

Routing Algorithms
Shortest Path First -- Dijkstra Algorithm◦

Static Routing

NODE

NODE

N_1

N_4

Routing_Table
NODE N_3

NODE

N_2

RT

NODE

N_5

Networking Library
Audio Video Bridging

Audio Video Bridging Library• Library of components that emulates the AVB operation at the Talker, Bridge and Listener
locations• Works in conjunction with the existing Networking library• Provides traffic generator, protocol additions, and statistics reporters• Tested to meet the specification and experimental data
• Easily extendable for future enhancements

Audio-Video Bridging- Standards
Supported• IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications (gPTP),• IEEE 802.1Qat: Stream Reservation Protocol (SRP),• IEEE 802.1Qav: Forwarding and Queuing for Time-Sensitive Streams (FQTSS), and• IEEE 802.1BA: Audio Video Bridging Systems

AVB Library Usage• Assemble a complete end-to-end automotive
applications with multiple sub-systems, ECU
hardware, cameras and other devices connected
via AVB over Ethernet✔Determine the network and the hardware
configurations required to meet the latency,
throughput and power requirements• Assemble a network of recording equipment,
displays, projectors and other audio/video
equipment in a professional studio or concert hall.

✔Configure the network architecture to ensure lowlatency and synchronized streaming operation

AVB Library

Using AVB Blocks- Rules to be Followed• All rules of the Network Node blocks apply here
• AVB_Config_Tables and AVB_Setup are required blocks for all AVB Models• AVB_Config_Table contains the Routing_Table block and the Link_Setup blocks. One
set is sufficient• If using Ethernet_Traffic block to generate Ethernet traffic, then the Traffic Table issufficient. The Stream block is not required.
• Each Ethernet_Traffic block must have a unique Traffic table• Each AVB stream must have a unique ID in the stream table.
• If using AVB streams, then all the blocks in the AVB_Config_Table are required.
• Bandwidth assigned to all Type classes on a link should not exceed link bandwidth• All links at a bridge have the same bandwidth assignment for the Type classes

Required Blocks to configure
the network, bandwidth
allocation. AVB attributes andtraffic

AVB Library Example
Top-level parameters
to ensure all blocks
Use same names andSimulation end time

Generates both
AVB and Ethernet
Traffic

Manages the• Generation of Talker Advertise• Handles algorithm to respondto Talker Failure• Generate Deregister messages

Display Latency as a Timedplot and Histogram per
Stream terminating at thisnode.
Latency and Throughput
Statistics for all the Streams
Trace information for themessages and transfers

Connects theNodes in a
network andthe routing
between the Nodes

Ethernet,
Traffic Shaping andClock Sync Messages

AVB Flow Diagram- Stream Reservation
Procedure
Bridge 1

TalkerLink Delay
No

Check
5 Steps

Bridge 2

Listener

Yes
Link Delay
No

Check
5 Steps

Link Delay

Yes
Link Delay
No

Alloc
BW

Alloc
BW
Link Delay

Traffic
Shaping

Alloc
BW

Traffic
Shaping

Check
5 Steps
Yes

Link Delay

Alloc
BW

Ethernet Traffic Shaping Algorithm• Uses Leaky Bucket for AVB streams• Bandwidth is for a fixed time period of 100 frames of 1500 bytes each
• Bandwidth credit assigned to each Type as a percentage of this period• Each successful AVB stream is assigned bandwidth as a percentage of the Type bandwidth• After the end of this period, bandwidth credit reset for all the types

Ethernet and AVB- Traffic Shaping• Requires the Stream, Type_to_BW and Class_to_Type tables• Priority is higher for the higher number• Queue for each Type• Unassigned bandwidth kept in Type 8• Period duration for ensuring bandwidth is 100 frames of 1500 bytes or 150,000 bytes
transfer time
• For a 100 Mbps, this is 12ms and for 1Gbps it is 1.2 ms• Bandwidth allocated is reset at the end of the period.

AVB and Ethernet- Traffic Shaping
Algorithm• Starts with the highest Type with assigned bandwidth• If bandwidth is available, a packet will be transmitted, even if the credit goes to negative• If Packet Available, packet selection✔ If Class A or B, then one of the AVB streams in the queue is sent out first✔ If there is no AVB or it is not a Class A or B, then the head of the queue for that type is sent out• If packet not available✔ The scheduler does a best effort✔ First it searches for a Class A and then a Class B AVB packet✔ If no AVB is available, it goes through from 7 to 0
✔ To ensure fairness, the next time, the sequence will start from 6-0,7 and so on✔ Credit is not decremented in this case
• When packet is sent out, the scheduler moves to the next lower Type• When Type 0 is complete, the scheduler goes to Type 8. This goes Type 7 to 0. The next time, the Scheduler starts from next lower one.
• When all credit has expired, the credit are reset for all the Types

Stream Reservation checks and Failure
Codes• AVB allocated bandwidth exceeds the threshold for the Class = 1• Worst case Execution Time (WCET) is greater than 2ms for Class A and 50 ms for Class B = 2• Next Bridge has a different type for the Class A or B = 3• Optional check where the listener has not buffer capacity = 4 (Currently not used)• Maximum number of Hops Exceeds 7 = 5

AVB_Config_Tables• Link Setup- Associated with the Node and Routing activities• Routing Table- Required for Routing between Network Nodes• Traffic Table- Requires one per Traffic block in the model• Stream- Required if AVB stream exists in the model• Type_to_BW- Bandwidth allocation by type for Nodes and Bridges• Class_to_Type- Class A and B assignment to a Type for Nodes and Bridges

Networking Library
TSN, Gateway, Ethernet
Semiconductor Device

Automotive Network containing TSN
Switch, Gateway and CAN Buses
CAN
Bus
•
•
•
•

11 bit and 29
bitPower calc
Bus off
Data Frame,
Remoteframe,
Overload
Frame , Error
Frame

Entire end to end
system can beassembled in a go
• Provides the
support for
TCP/IP or UDP• User canconfigure each
Layer as per
theirrequirement•••

Parameters

Database
BWs allocations
Time Aware Shaper
specifications
Signal vs Message routing

•
•

Each
Linked toa feature
Ease ofevaluation

Library provides various
types of schedulers
Gateway••

Ethernet as backbone
IEEE 802.1 (TSN)•
TAS•
Redundancy•
Credit shaper•
BW checks

•
•
•
•
•
•
•
•

IEEE 802.1Q
compliant
WFQ
WRR
DRR
Strict Priority
FCFS
RR
RR Priority

Standards supported Automotive libraryBus standards

TSN

IEEE 802.1Qbv
IEEE 802.1Qbu
IEEE 802.3br
IEEE 802.1Qca
IEEE 802.1Qcc
IEEE 802.1Qci
IEEE 802.1QCBIEEE 802.1Qch
IEEE 802.1AS•

CAN A and CAN B•
Data Frame•
Remote Frame•
Overload Frame•
Error Frame•
BusOff•Manual/Automatic Restart•Power Calculation•
Filtering•
Fast Data rate

TSN Stats Generated

Evaluation of an Error in the TSN Scheduler
Latency for CDT spiked

Latency ( Sec )•Evaluation on BW,MIF,TAS,CBS gives us
idea on what could happen with a worst
case scenario

Simulation Time ( Sec )CDT frame misses the time slot

CAN Bus••••

Different parameters for toggling between functionalities
Drop down menu for selecting 11 bit or 29 bit
Filtering DB can be modified to select required messages
Manual or Automatic restart can be selected just by checking
the boxCAN Bus Modules can beaccessed simply by going into
the CAN folder

We just have to dragand drop them on thewindow

Ethernet Switch – Semi abstract

Store and Forward or Cut
through can be
implemented here

Different Policing
schemes of interest canbe implemented here

Different shapers of interest ,Different Scheduling algorithm
like WRR can be selected here

TSN SWITCH , GATEWAY

Block Diagram
CAN BusCAN BusGateway

UDP
Traffic
UDP
Traffic

TSN Compliant
SwitchTSN Compliant
SwitchEndpoint

VisualSim ModelGateway
UnpackSoftwareIngress
BufferIngress Buffer Scheduler• Round Robin• FCFS• Strict Priority• Deficit RR• Weighted Fair Queuing

Routingcomputation

Pack
SoftwareProtocolTranslation
SoftwareEgress
BufferVisualSim Gateway Overview

TSN compliant Ether switch design
TCP IP Protocol –Transport Layer

Security Protocols

TSN Scheduler

Physical Layer

VisualSim ModelIntegration

Hardware in the loop - Goals•Create a test case where synthetic traffic generated from VisualSim Environment is sent to theexternal Hardware and use the response from the external hardware as input to the VisualSim
environment.
•Two modes of operation:• Once we press a dedicated button on FPGA, constant SRAM values are read out• Otherwise, a normal Read operation is done

•Plots for Read and Write throughput as well as for the data value

Block Diagram
Traffic Rate =600 MHz
Data Size = 16
Bytes
Traffic Rate =650 MHz
Data Size = 16
Bytes
Traffic Rate =750 MHz
Data Size = 16
Bytes
Traffic Rate =800 MHz
Data Size = 16
Bytes

Traffic Gen

Traffic Gen
ARM
AMBA
AXI BusConnection to FPGA

Traffic Gen

Traffic Gen

AXI Bus speed = 800 MHz
Bus Width = 8 Bytes

Block diagram realized in VisualSim
Platform

Integration with GEM5

Purposes of the Integration
GEM5 users◦ Extend research to cycle-models of the processor, cache, bus and memory

VisualSim users◦ Test processor models with instruction sequence from real code execution

VisualSim provides◦ Fully tested and commercially supported models of processor cores, cache, buses
and memories

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What is GEM5
Provides instruction set simulators for ARM, RISC-V, GPU, Power and x86◦ Load Linux/Windows/Android and execute the compiled software code.
◦ Verify the correctness of code behavior on the target instruction set, not on a specific core

Simple branch predictor provided, not match vendor implementation
Unlike Fast models, GEM5 has an experimental platform with templates for caches, buses, memory
and branch prediction◦ User can customize the processor and peripherals to create proprietary version

Does not provide a specific processor core implementation◦ Code execution is identical for ARM v8.1A in ARM Cortex A53, A72, A76 and A78

Common usage◦ Academic research and teaching purposes◦ Software development◦ Creating customized research platform

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Advantages & Disadvantages with GEM5
Advantages◦ Large user community◦ Support for ISS from ARM v8, Power, x86, RISC-V and GPU(AMD)

Disadvantage◦ Lack of support◦ Accuracy has not been tested

VisualSim with GEM5
Goal

◦ Execute software code on an emulated hardware system◦ Test the software against the full system◦ Current focus is performance and power of the full system◦ Future focus is correctness of action◦ Triggered the right device or sent data to the right interface

VisualSim-GEM5 Integration
Two modes of operation
Mode 1: GEM5 Wrapper◦ Generate batches of requests to cache and memory◦ GEM5 executes the code and wrapper feeds the addresses to VisualSim model

Mode 2: Trace File

◦ GEM5 writes the list of instructions and addresses to a file
◦ VisualSim reads the file using TrafficReader and provides this as input to the VisualSim Processor block

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Mode 1: Wrapper

VisualSim GEM5 Wrapper Parameters

Double click on the block ,to edit the pipePathPrefix

User has to provide the path to the GEM5 directory where gem5 build is done

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Mode 2: Traces generated from GEM5 – in shared file

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Model 2: Trace file Converted to VisualSim Format
Cache and Memory
stats

Demo output csv
from gem5 traces.

Different cpu coresstats
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Mode 2: Using Trace in VisualSim

These instructions read via TrafficReader as input to theProcessor blockLinking GEM5 to VisualSim
Application(Web, Map, Youtube, etc)
Lib

OS or System SW Platform
GEM5
Cycle
Counter

ARM/uP
ISA

ARM

VisualSim
FB

LCD

MMU

KEY

Cache

Touch
Screen
WiFi
Speaker

MemoryMic

Representative Example on VisualSim
Hardware Platform on VisualSim

How this works
VisualSim triggers the software to execute
GEM5 executes for a time duration
Output the addresses, service time and the time stamp
GEM5 can be triggered on a fixed schedule like real-time software or can be triggered after theoperation is completed in VisualSim

VisualSim
Trigger @ CLK

GEM5 ISS

VisualSim

Debug Software in System Context

Integrate Debugging and System Analysis

Enhancements
GEM5◦ Multi-core with different software on each core
◦ Add RISC-V and GPU models◦ Trigger software instances as opposed to full program◦ Add support for more debuggers

Provide services to develop new ISS
Integrate ARM Fast Models
SystemC package to add processors like CEVA and Tensilica◦ Using existing SystemC integrate

Integration with SystemC•

Full Library -> Hardware Language -> SystemC ->SC_Sim•Provides timed interface between VisualSim andSystemC•

Timed interface - Synchronization between
VisualSim and SystemC simulator

SystemC model- Example

Integration with Verilog• Full Library -> Hardware Language -> Verilog> Verilog_Sim• Provides timed interface between Visualsim
and Verilog• Timed interface - Synchronization between
VisualSim and Verilog simulator

Verilog model- Example

Version Control

Version Control•

Version Control and VisualSim Architect✔ Library Structure and Self-Contained Classes•

Issues in Version Control✔ Consistent library structure (for a given design)
amongst all team members✔ Self-contained classes••

One potential self-contained library structure✔ Icons✔ Components✔ Designs

Self-contained classes✔ Must only contain references to internal constructs (e.g., parameters, Variables, virtualconnections, etc.)✔ Must NOT contain references or have dependencies on external parameters, variables,
virtual connections, etc.

Version Control and VisualSim Architect
Custom Icons and Library Structure

Version Control and VisualSim Architect
Version Control using SVN• Step 1: Create a new repository✔ cd /var/svn✔ svnadmin create repos• Step 2: Import local tree of data for the first time
✔ svn import <Path to MyProject>
file:///var/svn/repos/<MyProject> -m “initial import”• Step 3: Checkout MyProject✔ svn checkout file:///var/svn/repos/<MyProject><MyProject>• Other commands✔ svn diff
✔ svn commit✔ svn update

Version Control Using CLASSPATH• Select the Master Directory and the Working Directory✔The Working directory would typically be on the desktop or local to the user.
✔The Master directory will be central and accessible by all users.

• Update VS_Model_Library setting in the VisualSim.bat and VisualSim.sh.
✔Make sure to enter the working directory first and then the Master directory(before) set VS_Model_Library=%INSTALL_PATH%\User_Library(after) :: For Working Directory setting
set WORKING_PATH= C:\Users\MYName\Desktop:: For Master Directory setting
set MASTER_PATH=C:\Master:: For adding Working Directory first and then the Master directory
set VS_Model_Library=%INSTALL_PATH%\User_Library;%WORK_PATH%;%MASTER_PATH%

Continued• Now create a class Block1 and store in path below the Master Directory. The file will
called Block1.xml.
An example of the location would be <<Master
Directory>>/Level1/Block1.xml✔Note: One caveat is that the class hierarchy structure in the file system structure must be
identical from the base of the relative path of the Working and Master settings in the
VS_Model_Library. The class must not be an absolute folder definition.
◦ It means that location of Block 1.xml should be<<Master Directory>>/Level1/Block1.xml<<Working Directory>>/Level1/Block1.xml

Continued• Now create Model_A and Instantiate Class Block1.
• Save this model anywhere.
• Now copy Block1.xml to the <<Working Directory>>/Level1/Block1.xml.
• Now re-open the model. Open Block of the Class and you will see that it references the Working
Directory file.
• Now edit the class Block1.xml in the Working Directory.
• When the Edit has been completed, copy the Block1.xml in working Directory to Masterdirectory and delete the class in the Working Directory.
• Now open the model. You will see that the Class references Master directory location.

ECLIPSE DEBUGGER SETUP

Eclipse Debugger Setup
Create a new Java project

Set project name and JRE(JDK 1.6).

Eclipse Debugger Setup
Configure all necessary libraries

Set proper order of libraries. The
sources should be on top.

Eclipse Debugger Setup
Update VisualSim start script• Add compiled classes to the class path

✔ set CLASSPATH=<path to complied classes>;%CLASSPATH%• Prepare Java debug settings✔ set dbg=-Xdebug -Xnoagent -Djava.compiler=NONE-Xrunjdwp:transport=dt_socket,server=y,suspend=n, address=<debug
port>• Modify java command✔ java %dbg% … VisualSim.ModelBuilder.ModelBuilderApplication

Eclipse Debugger Setup
Path to compiled classes is full path to“Default output folder”• Run the VisualSim using the script.
• Java is listening on debug port.
Debugger is able to attach to theport.

Eclipse Debugger Setup
Setup debug configuration

Eclipse Debugger Setup• Choose Remote Java Application. You can use
default settings. Port should correspond to<debug port> in Java debug options.
• Click Debug

Eclipse Debugger Setup
Now you can debug the code

97Use Cases and Examples

Use cases
20% NETWORK CAPACITY

VisualSim ModelResults

Use cases
80% NETWORK CAPACITY

Results
Total bytes
increased

Increased
LatencyUse cases
80% NETWORK CAPACITY AND TCP FRAMES

Results

Congestion and
Retransmissions

Use cases
TCP, UDP AND CAN FRAMESREARRANGING WORK LOADSVisualSim ModelResults

Use cases
TCP FRAMESCAN TO ETHERNET

Results

Use cases
CONNECT TO DATACENTRE

Datacenter modelling – Block diagram
Interface 1

Interface 2
Automotive
Network

Interface 3.
.
.

Interface n

Proc
Core1

OS1

Proc
Core2

OS2
Task
lookupHypervisor
OS3

Proc
Core3
Proc
Core4

OSn
Datacenter

Proc
Core n

SSD1
SSD2
SSD
n
HDD
1
HDD
2
HDD
n

VisualSim ModelResults

VISUALSIM TRAINING