IP Based Design 2002
Session : 4A. IP Business Models
Cryptographically Enforced Pay-Per-Use Licensing of FPGA Design Intellectual Property
Tom Kean, Algotronix Ltd., Edinburgh UK(tom@algotronix.com)

Abstract :At present FPGA IP vendors cannot determine how
many times their design has been programmed into
an FPGA by a customer. This has forced them toadopt an up-front charging model where a customer
obtains unlimited use of an IP block for a single
relatively large payment. This pricing model isfundamentally unsuited to the FPGA market since
the basic motivation for using an FPGA rather thanan ASIC is to trade off a higher per-unit cost toavoid a large up front NRE payment. This paper
suggests upgrading the cryptographic circuitry
presently included on FPGAs to prevent bitstream
piracy so that it can also support pay-per-use
royalty collection on FPGA IP cores and entire
FPGA designs.

INTRODUCTION

Even though ‘platform’ FPGAs such as Xilinx’s
Virtex II Pro family have now reached densities ashigh as 8 million ‘system gates’ and FPGAs
continue to take market share from conventional
ASICs the Intellectual Property industry supporting
FPGAs is commercially insignificant.
FPGAIntellectual Property is a sideline for a few
Semiconductor Intellectual Property (SIP) vendors
and some design services companies. The FPGAvendors themselves also have internal IP
development functions which generate little revenue
and are subsidised by their chip sales.
At first sight FPGA IP vendors appear to haveconsiderable technical advantages over Silicon IPvendors. Not only are FPGAs taking an everincreasing share of the total ASIC market but there

are no testing issues, no manufacturing yield issues
and no electrical compatibility issues for FPGA IP
providers. Moreover, while a System on Chip
designer working at 0.13um may be risking $700K in
NRE and a six month delay on their project if theychoose the wrong IP vendor the risks for an FPGA
designer are much lower. Nevertheless, the FPGA
IP industry has been even less successful than theSilicon IP industry. There is a simple reason for this:the up-front license fee business model the industry
has adopted does not fit the low volume
applications and constrained development budgetsof FPGA designers. After all, a designer turns toFPGAs precisely because they prefer higher per-unit
costs to up-front Non-Recurring Engineering (NRE)
payments. Therefore, it is not surprising that theyalso resist paying NREs for intellectual property.
This poor match between business model andcustomer base has deterred companies fromentering the FPGA IP core market and, at present, ahigh percentage of the available cores are suppliedby the FPGA vendors – either free of charge or for
nominal fees – in order to stimulate chip sales. As
FPGA densities continue to increase it will become
impossible for FPGA vendors to provide all thenecessary cores free of charge. It is in everyone’s
interest: FPGA customers, FPGA vendors and third
party IP suppliers to find a sustainable andenforceable ‘pay-per-use’ business model in orderto create a viable market for FPGA IP cores.
The pay-per-use model also enables companies
to offer complete FPGA design bitstreams as ‘virtualASSPs’ to address applications which due to small
volume or low gate count cannot be addressed
economically by custom chips. Such virtual ASSPs,
just as conventional ASSPs, can be used by board
level designers without any FPGA design expertiseor FPGA design tools.
Xilinx has recently implemented cryptographic
circuitry on its Virtex-II Pro family of FPGAs in orderto prevent ‘cloning’ and reverse engineering of
bitstreams containing user designs by pirates [2].
Several patent applications [3,4,5,6] and technicalpapers on alternative schemes for protecting FPGA
bitstreams have also been published [1,7].

IP Based SoC Design 2002 - October 30-31, 20021Extensions of these schemes allow thecryptographic element not only to protect against
reverse engineering and piracy but also to protect
bitstreams during in-the-field downloads of new
configurations.

between the TEP and the FPGA which can beused to encrypt communications between them.
The TEP’s key database allows it to establish
secure communications with any FPGA at a later
date using this shared secret.

This paper will show how on-chip cryptographic
circuitry, in conjunction with an e-commerce server
computer operated by the FPGA vendor or a trusted
third party can also enforce a pay-per-use licensing
model for FPGA intellectual property withoutinconveniencing the user of the IP [7].

The structure of the ‘token’ is shown in figure 1.
If the triple DES cipher is used the IV andchecksum fields are 8 bytes long and the TEP key
is 24 bytes. The field labelled IV is a random‘Initial Value’ used in the industry standard
Cipher Block Chaining (CBC) mode of encryption.
The purpose of the IV is to ensure that if two
identical pieces of data are encrypted there is nocorrelation between the corresponding encrypted
data. This increases the ciphers ability to resist
chosen plaintext attacks.

SECURITY PROTOCOL
The proposed IP licensing protocol involves a
Trusted External Party (TEP) which operates the ecommerce servers which implement the licensing
scheme and is trusted by the FPGA vendor, FPGA
customers and IP vendors to operate fairly.
Although the TEP is logically an externalorganisation for the purposes of the protocol inpractice the FPGA vendor may choose to offer thisservice itself.
The protocol has several phases starting at the time
when the FPGA is manufactured.
1.

2.

Each FPGA is manufactured with a secret‘chip’ key and a non-secret but difficult toalter unique chip identifier embedded on thechip. Various technologies are available toencode these numbers including anti-fuseand Flash EPROM – only a few hundred
bits of non-volatile memory are required.
The secret key need not be stored
anywhere outside the FPGA and all recordof it can be destroyed as soon as it isprogrammed into the chip. This key does
not even need to be unique.
During product testing the FPGA
manufacturer allows a computer owned by
the TEP to connect to each FPGA’s JTAG
interface. This computer creates a random‘trusted external party’ (TEP) key andpresents it to the FPGA via JTAG whichthen returns its chip identifier and the TEP
key encrypted using its on-chip secret key.
The TEP key and the encrypted TEP key
are stored in a database indexed by the chipidentifier.

The encrypted TEP key is called a ‘token’: it canbe freely stored in insecure memories (e.g. Flashmemories in user equipment) and communicatedover insecure channels but when presented tothe FPGA it allows the FPGA to calculate its
secret TEP key. The TEP key is a shared secretAnyone who has the FPGA in their possession
can present it with a new key and obtain a token
and the tokens can be used for other purposes
than IP licensing. Creating a token is a general
purpose mechanism which allows someone inpossession of the FPGA to initiate securecommunications with it in the future. For
example, an equipment manufacturer might create
tokens to support secure download of bitstreams
to upgrade a product in the field. The only
difference between this and the TEP is that theTEP’s relationship with the FPGA manufacturer
allows it to obtain a token for every FPGAmanufactured not just those it purchases.
As well as a database of tokens allowing it tocommunicate securely with every FPGA chip theTEP also needs a database of information aboutIP cores.
3.

IP vendors communicate design
identification, security information andpricing information on their cores to theTEP.

The next phase of the protocol concerns what
happens when a customer makes use of alicensed core.
4.

When a customer wishes to use an IP thecore vendor supplies the IP design
information in an encrypted format. FPGA
implementation tools supplied by the FPGAvendor process a design containing
licensed IP as normal except that bitstream
files (and other files containing low level
design information like netlist files) arecreated in an encrypted format whichcannot be used directly to program anFPGA. This encrypted bitstream also

IP Based SoC Design 2002 - October 30-31, 2002

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contains copyright information on all
licensable cores within the design. Thiscopyright information is secured against
tampering using cryptographic checksums
but need not be encrypted.
The next phase of the protocol concerns making
use of the bitstream to configure individualFPGAs. This is the point at which pay-per-use
licensing fees are collected.
5.

6.

7.

8.

During manufacturing of equipment
containing an FPGA trusted programming
software supplied by the FPGA vendor
reads in the encrypted design bitstream
from the CAD tools and extracts thecopyright information identifying thelicensed cores. It also communicates with
the FPGA via JTAG and obtains its unique
identifier.
The trusted programming softwarecommunicates via the internet using astandard secure protocol such as SSL witha server owned by the TEP and supplies thename of the customer using theprogramming software, the copyrightinformation from the bitstream and theFPGA unique identifier. The TEP server
indexes its database using the FPGA’s
unique identifier to obtain thecorresponding TEP key and token which itsupplies to the trusted programmingsoftware.
The TEP server bills the account of thecustomer requesting that the FPGA be
programmed and credits the accounts of theIP core suppliers.
The trusted programming software decrypts
the encrypted bitstream and re-encrypts itwith the TEP key for this particular FPGA.
It then prepends the token obtained fromthe TEP server to the beginning of thebitstream. This complete encrypted
bitstream is stored in non-volatile memory
within the product containing the FPGA.
The next phase of the protocol takes place
whenever the FPGA chip loads its
encrypted bitstream from local memory.

9.

When the FPGA finally reads in thebitstream it uses its on chip secret key to recalculate its own TEP key by decrypting thetoken at the beginning of the bitstream.
Using this TEP key it can successfully
decrypt the bitstream information andprogram its configuration memory. No
other FPGA can successfully decrypt thetoken to determine the correct key todecrypt the bitstream. Therefore thecustomer must make a request to the TEP
server each time they wish to program anFPGA chip with licensed IP.
OVERHEAD OF THE PROTOCOL
When considering a scheme such as this it isimportant that the additional costs andinconvenience it causes are outbalanced by its
benefits.
This scheme requires encryption circuitry oneach chip and that each chip has an individuallyprogrammed secret key and identifier. The largest
vendor of FPGAs, Xilinx Inc., already includes asuitable triple-DES encryption circuit on its chips toprevent bitstream piracy. Therefore, it would be asmall step to provide the additional on-chipfunctionality required by this scheme. The main
additional capability required is a small non-volatileon-chip memory since the battery-backed on-chip
key register provided by Xilinx is not suitable forthis application. The extension to the on-chip
circuitry has the additional benefit of supporting
secure download of bitstream information to FPGAs
in the field.
The scheme requires a method of supplying
encrypted IP core design information to FPGAdesigners. Several methods have been proposedand some are in common use to allow evaluation ofIP cores prior to purchase. Most such schemes, forexample Altera’s OpenCore [9], prevent generationof bitstream information from encrypted IP, where
this scheme allows bitstream information to begenerated but encrypts it. No information on theuser design beyond a list of the licensed IP cores it
contains is provided to the TEP.
The scheme requires a secure e-commerce server
computer.
The database of tokens, unique
identifiers and keys would likely require only a fewgigabytes of disk space.
The scheme requires secure programming
software be used to deal with encrypted bitstreams
containing IP cores. This is a relatively simple andstraightforward application which could easily run
on a personal computer. All recent FPGA families
use JTAG interfaces for programming and so therequirement that the FPGA report its unique
identifier over JTAG to the programming software iseasily met.
Naturally, should a user design not contain any
licensed IP the FPGA software would create anormal un-encrypted bitstream file so customers
who do not use licensed IP can program their

IP Based SoC Design 2002 - October 30-31, 2002

3FPGAs in the normal manner without any contact
with the TEP.
The scheme as described above relies on secure
software running on the users computer to protect
design information. A potential drawback of thismethod is that a hacker may try to reverse engineer
and circumvent the protection methods in thesoftware. One way of reducing this risk this is tocomplement the software with tamper resistanthardware (such as a dongle) which implements
cryptographic functions. Another approach is tocarry out operations involving the licensed IP files
on the TEP server rather than the user’s computer.
This would provide better security for the IP but islikely to be less convenient for the FPGA customers.
CUSTOMER BENEFITS

from piracy coupled with a secure e-commerceserver and small changes to the design flow FPGA
vendors can enforce pay-per use licensing of IPcores. This will support the development of a viable
IP industry to serve their customers while creating aworthwhile additional revenue stream forthemselves. Many extensions and variations of theprotocol outlined here are discussed in [6].

REFERENCES
1.
2.

The cryptographic circuitry on the FPGA
protects bitstreams from reverse engineering andpiracy and provides a mechanism for secure
download of bitstreams to devices in the field.
These benefits, rather than the ability to enforce a
pay-per use IP licensing scheme, will provide theinitial motivation to add the necessary hardware toFPGA chips.
An enforceable pay-per-use IP licensing scheme
will allow IP vendors to make their IP available
without large up-front charges. This will make using
IP much more attractive to the majority of FPGA
customers who have designs with small or medium
volumes. Further, there is no longer a need forspecial ‘evaluation’ arrangements prior to purchasesince no substantial costs are incurred until a large
number of chips are programmed.
Pay-per-use licensing ties IP costs directly tosales and reduces business risk for all IP users. It isto be expected that pay-per-use licensing will allow
the FPGA IP industry to achieve significantly higher
revenues compared to up-front licensing fees. This
will benefit FPGA users by increasing the amount ofhigh-value proprietary IP being made available onFPGAs. It will also potentially create a market forcomplete FPGA designs sold as ’Virtual’Application Specific Standard Products to systemcompanies with no in-house FPGA design
capability.

3.

4.

5.

6.

7.

8.

9.

Dipert, B., "Cunning Circuits Confound Crooks",
EDN Magazine, October 12, 2000.
Xilinx Inc., "Using Bitstream Encryption", in
Chapter 2 of the Virtex II Platform FPGA Handbook
available from www.xilinx.com.
Austin, K., "Data Security Arrangements for
Semiconductor Programmable Devices", US Patent
5,388,157Algotronix Ltd., "Method and Apparatus for SecureConfiguration of a Field Programmable Gate Array",
US Patent Application 21015919A1.
Algotronix Ltd., "Method of using a Mask
Programmed Key to Securely Configure a Field
Programmable Gate Array",European PatentApplication, EP01244330A2
Algotronix Ltd. “Method of Protecting Intellectual
Property Cores on Field Programmable Gate Array”,
Unpublished Pending US Patent Application.
Kean, T. “Cryptographic Rights Management ofFPGA Intellectual Property Cores”, Proceedings
ACM Conference on FPGAs, FPGA 2002
Monterey CA, Feb 2002.
Kean T. “ Secure Configuration of Field
Programmable Gate Arrays”, Proceedings FPL 2001,
Belfast UK, September 2001.
Altera Inc., “Evaluating AMPP and MegaCore
Functions”, Application Note 125, Version 2.0,April 2001.

FPGA companies will benefit by increased salesof FPGA chips and a reduced requirement todevelop IP in house to supply free of charge to theircustomers. If they choose to take on the role of TEP
themselves they would also create a revenue stream
from transaction fees.

IVTEP KeySUMMARY
By making use of cryptographic circuits within
the FPGA originally created to protect bitstreams

IP Based SoC Design 2002 - October 30-31, 2002

CryptographicChecksum4

Encrypted with Chip Key
FIGURE 1. Format of shared secret ‘Token’

IP Based SoC Design 2002 - October 30-31, 2002

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