MVME5500
Single-Board Computer

Programmer’s Reference
Guide
V5500A/PG2
October 2003 Edition© Copyright 2003 Motorola Inc.
All rights reserved.
Printed in the United States of America.
Motorola and the stylized M logo are trademarks of Motorola, Inc., registered in the U.S.
Patent and Trademark Office.
All other product or service names mentioned in this document are the property of theirrespective owners.

Safety Summary
The following general safety precautions must be observed during all phases of operation, service, and repair of
this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual
could result in personal injury or damage to the equipment.
The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as
the user of the product, should follow these warnings and all other safety precautions necessary for the safe
operation of the equipment in your operating environment.

Ground the Instrument.
To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If theequipment is supplied with a three-conductor AC power cable, the power cable must be plugged into an approved
three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground(safety ground) at the power outlet. The power jack and mating plug of the power cable meet International
Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.

Do Not Operate in an Explosive Atmosphere.
Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes.
Operation of any electrical equipment in such an environment could result in an explosion and cause injury or
damage.

Keep Away From Live Circuits Inside the Equipment.
Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or otherqualified service personnel may remove equipment covers for internal subassembly or component replacement
or any internal adjustment. Service personnel should not replace components with power cable connected. Undercertain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, such
personnel should always disconnect power and discharge circuits before touching components.

Use Caution When Exposing or Handling a CRT.
Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To
prevent CRT implosion, do not handle the CRT and avoid rough handling or jarring of the equipment. Handlingof a CRT should be done only by qualified service personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.
Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local
Motorola representative for service and repair to ensure that all safety features are maintained.

Observe Warnings in Manual.
Warnings, such as the example below, precede potentially dangerous procedures throughout this manual.
Instructions contained in the warnings must be followed. You should also employ all other safety precautions
which you deem necessary for the operation of the equipment in your operating environment.

Warning

Warning

To prevent serious injury or death from dangerous voltages, use extreme
caution when handling, testing, and adjusting this equipment and its
components.

Flammability
All Motorola PWBs (printed wiring boards) are manufactured with a flammability ratingof 94V-0 by UL-recognized manufacturers.

EMI Caution
Caution!
CautionThis equipment generates, uses and can radiate electromagnetic energy. It
may cause or be susceptible to electromagnetic interference (EMI) if not
installed and used with adequate EMI protection.

Lithium Battery Caution
This product contains a lithium battery to power the clock and calendar circuitry.
Caution!
CautionCaution!
Attention

Caution!
Vorsicht

Danger of explosion if battery is replaced incorrectly. Replace battery onlywith the same or equivalent type recommended by the equipment
manufacturer. Dispose of used batteries according to the manufacturer’s
instructions.
Il y a danger d’explosion s’il y a remplacement incorrect de la batterie.
Remplacer uniquement avec une batterie du même type ou d’un typeéquivalent recommandé par le constructeur. Mettre au rebut les batteries
usagées conformément aux instructions du fabricant.
Explosionsgefahr bei unsachgemäßem Austausch der Batterie. Ersatz nur
durch denselben oder einen vom Hersteller empfohlenen Typ. Entsorgung
gebrauchter Batterien nach Angaben des Herstellers.

CE Notice (European Community)
Warning!
Warning

This is a Class A product. In a domestic environment, this product may
cause radio interference, in which case the user may be required to takeadequate measures.

Motorola Computer Group products with the CE marking comply with the EMC Directive(89/336/EEC). Compliance with this directive implies conformity to the following
European Norms:
EN55022 “Limits and Methods of Measurement of Radio Interference Characteristics
of Information Technology Equipment”; this product tested to Equipment Class A
EN55024 “Information technology equipment—Immunity characteristics—Limits andmethods of measurement”
Board products are tested in a representative system to show compliance with the above
mentioned requirements. A proper installation in a CE-marked system will maintain therequired EMC performance.
In accordance with European Community directives, a “Declaration of Conformity” hasbeen made and is available on request. Please contact your sales representative.

Notice
While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. assumes no liability resulting from any omissions in this document, or fromthe use of the information obtained therein. Motorola reserves the right to revise thisdocument and to make changes from time to time in the content hereof without obligationof Motorola to notify any person of such revision or changes.
Electronic versions of this material may be read online, downloaded for personal use, orreferenced in another document as a URL to the Motorola Computer Group Web site. The
text itself may not be published commercially in print or electronic form, edited, translated,or otherwise altered without the permission of Motorola, Inc.
It is possible that this publication may contain reference to or information about Motorola
products (machines and programs), programming, or services that are not available in yourcountry. Such references or information must not be construed to mean that Motorola
intends to announce such Motorola products, programming, or services in your country.

Limited and Restricted Rights Legend
If the documentation contained herein is supplied, directly or indirectly, to the U.S.
Government, the following notice shall apply unless otherwise agreed to in writing byMotorola, Inc.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth insubparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.
1995) and of the Rights in Noncommercial Computer Software and Documentation clauseat DFARS 252.227-7014 (Jun. 1995).
Motorola, Inc.
Computer Group
2900 South Diablo Way
Tempe, Arizona 85282

Contents
About This Guide
Summary of Changes ............................................................................................... xiii
Overview of Contents .............................................................................................. xiii
Comments and Suggestions ......................................................................................xiv
Conventions Used in This Manual ............................................................................xiv
CHAPTER 1

Board Description and Memory Maps

Introduction .............................................................................................................. 1-1
Overview .................................................................................................................. 1-1
Memory Maps .......................................................................................................... 1-5
Default Processor Memory Map ....................................................................... 1-5
MOTLoad’s Processor Memory Map ............................................................... 1-6
Default PCI Memory Map ................................................................................ 1-7
MOTLoad’s PCI Memory Maps ....................................................................... 1-9
PCI I/O Space Maps .......................................................................................... 1-9
System I/O Memory Map ............................................................................... 1-10
System Status Register 1 ..................................................................................1-11
System Status Register 2 ................................................................................. 1-13
System Status Register 3 ................................................................................. 1-15
Presence Detect Register ................................................................................. 1-16
Configuration Header/Switch Register (S1) ................................................... 1-17
Time Base Enable Register ............................................................................. 1-18
Geographical Address Register (S2) ............................................................... 1-18
COM1 & COM2 Universal Asynchronous Receiver/Transmitter (UART) ... 1-20
Real-Time Clock and NVRAM ...................................................................... 1-20
ISA Local Resource Bus ........................................................................................ 1-20
CHAPTER 2

Programming Details

Introduction .............................................................................................................. 2-1
PCI Configuration Space and IDSEL Mapping ....................................................... 2-1
Interrupt Controller .................................................................................................. 2-3
Two-Wire Serial Interface ........................................................................................ 2-5
GT-64260B Initialization .......................................................................................... 2-7
GT-64260B GPP Configuration ............................................................................... 2-7

vii

GT-64260B Reset Configuration .............................................................................. 2-9
GT-64260B Device Controller Bank Assignments ................................................. 2-11
System Clock Generators ....................................................................................... 2-13
VPD and User Configuration EEPROMs ............................................................... 2-14
Temperature Sensor ................................................................................................ 2-14
Flash Memory ......................................................................................................... 2-14
PCI Arbitration Assignments .................................................................................. 2-14
Other Software Considerations ............................................................................... 2-15
CPU Bus Mode ................................................................................................ 2-15
Processor Type Identification .......................................................................... 2-16
Processor PLL Configuration .......................................................................... 2-16
L1, L2, L3 Cache ............................................................................................. 2-16
APPENDIX A

Vital Product Data

Flash Memory Configuration Data .......................................................................... A-1
L3 Cache Configuration Data .................................................................................. A-3
APPENDIX B

Related Documentation

Motorola Computer Group Documents ................................................................... B-1
Manufacturers’ Documents ..................................................................................... B-2
Related Specifications ............................................................................................. B-5

viii

List of Figures
Figure 1-1. MVME5500 Block Diagram ................................................................ 1-4

ix

List of Tables
Table 1-1. MVME5500 Features Summary ............................................................ 1-2
Table 1-2. Default Processor Memory Map ............................................................ 1-5
Table 1-3. MOTLoad’s Processor Memory Map .................................................... 1-6
Table 1-4. Default PCI Memory Map ..................................................................... 1-7
Table 1-5. MOTLoad’s PCI 0 Domain Memory Map ............................................. 1-9
Table 1-6. MOTLoad’s PCI 1 Domain Memory Map ............................................. 1-9
Table 1-7. PCI 0 Domain I/O Map .......................................................................... 1-9
Table 1-8. PCI 1 Domain I/O Map ........................................................................ 1-10
Table 1-9. Device Bank 1 I/O Memory Map ........................................................ 1-10
Table 1-10. System Status Register 1 .....................................................................1-11
Table 1-11. System Status Register 2 .................................................................... 1-13
Table 1-12. System Status Register 3 .................................................................... 1-15
Table 1-13. Presence Detect Register .................................................................... 1-16
Table 1-14. Configuration Header/Switch Register .............................................. 1-17
Table 1-15. TBEN Register ................................................................................... 1-18
Table 1-16. Geographical Address Register .......................................................... 1-19
Table 2-1. IDSEL Mapping for PCI Devices .......................................................... 2-2
Table 2-2. GT-64260B External GPP Interrupt Assignments ................................. 2-4
Table 2-3. I2C Bus Device Addressing ................................................................... 2-6
Table 2-4. GT-64260B GPP Pin Function Assignments ......................................... 2-7
Table 2-5. GT-64260B Power-Up Configuration Settings .................................... 2-10
Table 2-6. Device Bank Assignments ................................................................... 2-12
Table 2-7. Device Bank Timing Parameters ......................................................... 2-12
Table 2-8. PCI Arbiter Assignments ..................................................................... 2-15
Table 2-9. Processor L3CR Register Assignments ............................................... 2-16
Table A-1. Flash 0 Memory Configuration Data ....................................................A-1
Table A-2. Flash 1 Memory Configuration Data ....................................................A-2
Table A-3. L3 Cache Configuration Data ...............................................................A-3
Table B-1. Motorola Computer Group Documents .................................................B-1
Table B-2. Manufacturers’ Documents ...................................................................B-2
Table B-3. Related Specifications ...........................................................................B-5

xi

About This Guide
The MVME5500 Single-Board Computer Programmer’s Reference Guide
provides general programming information, including memory maps,
interrupts, and register data for the MVME5500 family of boards. This
document should be used by anyone who wants general, as well as
technical information about the MVME5500 products.
As of the printing date of this manual, the MVME5500 supports themodels listed below.
Model Number

Description

MVME5500-0161

1 GHz MPC7455 processor, 512MB SDRAM,
Scanbe handles

MVME5500-0163

1 GHz MPC7455 processor, 512MB SDRAM,IEEE handles

Summary of Changes
This is the second edition of the Programmer’s Reference Manual. It
supersedes the August 2003 edition and incorporates the followingchanges.
Date
October
2003

Changes
Corrected the PCI 0 and 1 domain memory space sizes in Table
1-3 on page 1-6.

Overview of Contents
This manual is divided into the following chapters and appendices:
Chapter 1, Board Description and Memory Maps, provides a brief productdescription and a block diagram. The remainder of the chapter provides
information on memory maps and system and configuration registers.

xiiiChapter 2, Programming Details, provides additional programming
information including IDSEL mapping, interrupt assignments for the
GT-64260B system processor, two-wire serial interface addressing, andother device and system considerations.
Appendix A, Vital Product Data, provides a listing of vital product data
(VPD) related to this product.
Appendix B, Related Documentation, provides a listing of related
Motorola manuals, vendor documentation, and industry specifications.

Comments and Suggestions
Motorola welcomes and appreciates your comments on its documentation.
We want to know what you think about our manuals and how we can makethem better. Mail comments to:
Motorola Computer Group
Reader Comments DW164
2900 S. Diablo Way
Tempe, Arizona 85282
You can also submit comments to the following e-mail address:
reader-comments@mcg.mot.com
In all your correspondence, please list your name, position, and company.
Be sure to include the title and part number of the manual and tell how you
used it. Then tell us your feelings about its strengths and weaknesses andany recommendations for improvements.

Conventions Used in This Manual
The following typographical conventions are used in this document:bold
is used for user input that you type just as it appears; it is also used forcommands, options and arguments to commands, and names ofprograms, directories and files.

xivitalic
is used for names of variables to which you assign values, for function
parameters, and for structure names and fields. Italic is also used forcomments in screen displays and examples, and to introduce newterms.
courieris used for system output (for example, screen displays, reports),
examples, and system prompts.
<Enter>, <Return> or <CR>
represents the carriage return or Enter key.
Ctrl
represents the Control key. Execute control characters by pressing theCtrl key and the letter simultaneously, for example, Ctrl-d.

xv

1Board Description and Memory
Maps

1

Introduction
This chapter briefly describes the board level hardware features of the
MVME5500 single-board computer, including a table of features and a
block diagram. The remainder of the chapter provides memory map
information including a default memory map, MOTLoad’s processor
memory map, a default PCI memory map, MOTLoad’s PCI memory map,a PCI I/O memory map, and system I/O memory maps.
Programmable registers in the GT-64260B system controller are
documented in publication MV-S100414-00 Rev A, which is obtainablefrom Marvell Technologies, Ltd. Refer to Appendix B, Related
Documentation for more information.

Overview
The MVME5500 is a single-board computer based on the PowerPC
MPC7455 processor and the Marvell GT-64260B host bridge with a dual
PCI interface and memory controller. On-board payload includes two
PMC slots, two SDRAM banks, an expansion connector for two additionalbanks of SDRAM, 8MB boot Flash ROM, one 10/100/1000 Ethernet port,
one 10/100 Ethernet port, 32MB expansion Flash ROM, two serial ports,
and an NVRAM and real-time clock.

1-1

1

Board Description and Memory Maps

The following table lists the features of the MVME5500.

Table 1-1. MVME5500 Features Summary
FeatureDescription

Processor– Single 1 GHz MPC7455 processor– Bus clock frequency at 133 MHz

L3 Cache– 2MB using DDR SRAM
– Bus clock frequency at 200 MHz

Flash– 8MB Flash soldered on board– 32MB expansion Flash soldered on board

System Memory– Two banks on-board for 512MB using 256Mb devices– Expansion connector for a mezzanine board with two banks for
512MB using 256Mb devices– Double-bit-error detect, single-bit-error correct across 72 bits
– Bus clock frequency at 133 MHz

Memory Controller– Provided by GT-64260B– Supports one to four banks of SDRAM at up to 1GB per bank

Processor Host Bridge– Provided by GT-64260B– Supports MPX mode or 60x mode

PCI Interfaces– Provided by GT-64260B– Two independent 64-bit interfaces, one compliant to PCI spec rev
2.1 (Bus 0.0) and the other compliant to PCI spec rev 2.2 (Bus 1.0)
– Bus clock frequency at 66 MHz– Provided by the HiNT PCI 6154 secondary interface– One 64-bit interface, compliant to PCI spec rev 2.1 (Bus 0.1)
– Bus clock frequency at 33 MHz

Interrupt Controller– Provided by GT-64260B– Interrupt sources internal to GT-64260B– Up to 32 external interrupt inputs– Up to seven interrupt outputs

Counters/Timers– Eight 32-bit counters/timers in GT-64260B

1-2

Computer Group Literature Center Web Site

Overview

Table 1-1. MVME5500 Features Summary (continued)
FeatureDescription

I2C– Provided by GT-64260B– Master or slave capable– On-board serial EEPROMs for VPD, SPD, GT-64260B init, anduser data storage

NVRAM– 32KB provided by MK48T37

Real Time Clock– Provided by MK48T37

Watchdog Timers– One in GT-64260B– One in MK48T37– Each watchdog timer can generate interrupt or reset, software
selectable

On-board Peripheral
Support– One 10/100/1000BaseT Ethernet interface, one 10/100BaseT
Ethernet interface– Dual 16C550 compatible UARTs

PCI Mezzanine Cards– Two PMC sites (one shared with the expansion memory and has
IPMC capability)

PCI Expansion– One expansion connector for interface to PMCspan

Miscellaneous– Reset/Abort switch– Front panel status indicators, Run and Board Fail

Form Factor– Standard VME

http://www.motorola.com/computer/literature

1-3

1

1

Board Description and Memory Maps

Figure 1-1. MVME5500 Block Diagram

1-4

Computer Group Literature Center Web Site

Memory Maps

Memory Maps
Default Processor Memory Map
When power is first applied or a hard reset has occurred, the GT-64260B
has a default address map. Table 1-2 shows the default processor memory
map.

Table 1-2. Default Processor Memory Map
Processor Address
Start

End

Size

Definition

0000 0000

007F FFFF

8MB

SDRAM Bank 00080 0000

00FF FFFF

8MB

SDRAM Bank 10100 0000

017F FFFF

8MB

SDRAM Bank 20180 0000

01FF FFFF

8MB

SDRAM Bank 30200 0000

0FFF FFFF

224MB

Unassigned

1000 0000

11FF FFFF

32MB

PCI Bus 0 I/O Space

1200 0000

13FF FFFF

32MB

PCI Bus 0 Memory Space 0

1400 0000

1BFF FFFF

128MB

Unassigned

1C00 0000

1C7F FFFF

8MB

Device Port CS0

1C80 0000

1CFF FFFF

8MB

Device Port CS1

1D00 0000

1DFF FFFF

16MB

Device Port CS2

1E00 0000

1FFF FFFF

32MB

Unassigned

2000 0000

21FF FFFF

32MB

PCI Bus 1 I/O

2200 0000

23FF FFFF

32MB

PCI Bus 1 Memory Space 02400 0000

25FF FFFF

32MB

PCI Bus 1 Memory Space 1

2600 0000

27FF FFFF

32MB

PCI Bus 1 Memory Space 22800 0000

29FF FFFF

32MB

PCI Bus 1 Memory Space 3

2A00 0000

F0FF FFFF

3184MB

Unassigned

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Notes

1-5

1

1

Board Description and Memory Maps

Table 1-2. Default Processor Memory Map (continued)
Processor Address
Start

End

Size

Definition

Notes

F100 0000

F100 FFFF

64KB

Internal Registers

1

F101 0000

F1FF FFFF

16MB 64KB

Unassigned

F200 0000

F3FF FFFF

32MB

PCI Bus 0 Memory Space 1

F400 0000

F5FF FFFF

32MB

PCI Bus 0 Memory Space 2F600 0000

F7FF FFFF

32MB

PCI Bus 0 Memory Space 3

F800 0000

FEFF FFFF

112MB

Unassigned

FF00 0000

FF7F FFFF

8MB

Device Port CS3

FF80 0000

FFFF FFFF

8MB

Boot Flash Bank

Notes

2

1. Set by configuration resistors.
2. Selects Flash 0 or Flash 1 depending on the state of the Flashboot bank select jumper.

MOTLoad’s Processor Memory Map
MOTLoad’s processor memory map is given in the following table.

Table 1-3. MOTLoad’s Processor Memory Map
Processor Address
Start

End

Size

Definition

Notes

0000 0000

7FFF FFFF

2GB

On-Board SDRAM

1

8000 0000

DFFF FFFF

1.5GB

PCI 0 Domain Memory Space

E000 0000

EFFF FFFF

256MB

PCI 1 Domain Memory Space

F000 0000

F07F FFFF

8MB

PCI 0 Domain I/O Space2

F080 0000

F0FF FFFF

8MB

PCI 1 Domain I/O Space2

1-6

Computer Group Literature Center Web Site

Default PCI Memory Map

Table 1-3. MOTLoad’s Processor Memory Map (continued)
Processor Address
Start

End

Size

Definition

F100 0000

F10F FFFF

1MB

GT-64260B Internal Registers

F110 0000

F11F FFFF

1MB

GT-64260B Device Bus Registers

F120 0000

F1FF FFFF

14MB

Reserved

F200 0000

FE00 0000

32MB

Flash Bank 0

4FF80 0000

FFFF FFFF

8MB

Flash Bank 1

4

Notes

Notes

3

1. Maximum size is 2GB. Actual size depends on the amountof memory installed.
2. Zero-based I/O space.
3. Device chip select 1.
4. Flash 0/Flash 1 can be mapped to device chip select 0 or
BOOT chip select depending on the state of the Flash bootbank select header.

Default PCI Memory Map
Table 1-4 is the default PCI memory map for each PCI bus following reset.

Table 1-4. Default PCI Memory Map
PCI Address
Start

End

Size

Definition

0000 0000

007F FFFF

8MB

SDRAM Bank 00080 0000

00FF FFFF

8MB

SDRAM Bank 10100 0000

017F FFFF

8MB

SDRAM Bank 20180 0000

01FF FFFF

8MB

SDRAM Bank 30200 0000

0FFF FFFF

224MB

Unassigned

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1-7

1

1

Board Description and Memory Maps

Table 1-4. Default PCI Memory Map (continued)
PCI Address
Start

End

Size

Definition

1000 0000

11FF FFFF

32MB

PCI Bus 1 P2P I/O Space

1200 0000

13FF FFFF

32MB

PCI Bus 1 P2P Memory Space 0

1400 0000

1400 FFFF

64KB

Internal Registers

1401 0000

1BFF FFFF

128MB 64KB

Unassigned

1C00 0000

1C7F FFFF

8MB

Device Port CS0

1C80 0000

1CFF FFFF

8MB

Device Port CS1

1D00 0000

1DFF FFFF

16MB

Device Port CS2

1E00 0000

1FFF FFFF

32MB

Unassigned

2000 0000

21FF FFFF

32MB

PCI Bus 0 P2P I/O Space

2200 0000

23FF FFFF

32MB

PCI Bus 0 P2P Memory Space 02400 0000

25FF FFFF

32MB

PCI Bus 0 P2P Memory Space 1

2600 0000

F1FF FFFF

3264MB

Unassigned

F200 0000

F3FF FFFF

32MB

PCI Bus 1 P2P Memory Space 1

F400 0000

FEFF FFFF

176MB

Unassigned

FF00 0000

FF7F FFFF

8MB

Device Port CS3

FF80 0000

FFFF FFFF

8MB

Boot Flash Bank

1-8

Computer Group Literature Center Web SiteMOTLoad’s PCI Memory Maps

MOTLoad’s PCI Memory Maps
MOTLoad’s PCI memory map for each PCI domain is shown in thefollowing tables.

Table 1-5. MOTLoad’s PCI 0 Domain Memory Map
PCI 0 Memory Address
Start

End

Size

Definition

0000 0000

7FFF FFFF

2GB

On-Board SDRAM

8000 0000

DFFF FFFF

768MB

Local PCI 0 Domain Memory Space

F000 0000

FFFF FFFF

256MB

Reserved

Table 1-6. MOTLoad’s PCI 1 Domain Memory Map
PCI 1 Memory Address
Start

End

Size

Definition

0000 0000

7FFF FFFF

2GB

On-Board SDRAM

E000 0000

EFFF FFFF

1GB

Local PCI 1 Domain Memory Space

F000 0000

FFFF FFFF

256MB

Reserved

PCI I/O Space Maps
The PCI I/O space map for each PCI domain is shown in the following
tables.

Table 1-7. PCI 0 Domain I/O Map
PCI 0 I/O Address
Start

End

Size

Definition

0000 0000

007F FFFF

8MB

Local PCI Domain I/O Space

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1-9

1

1

Board Description and Memory Maps

Table 1-8. PCI 1 Domain I/O Map
PCI 1 I/O Address
Start

End

Size

Definition

0000 0000

007F FFFF

8MB

Local PCI Domain I/O Space

System I/O Memory Map
System resources for the MVME5500 board including system control andstatus registers, NVRAM/RTC, and the 16550 UARTs are mapped into a
1MB address range assigned to device bank 1. The region defined bydevice bank 1 resides within the GT-64260B device bus register’s space
listed in Table 1-3 on page 1-6. The memory map is defined in thefollowing table:

Table 1-9. Device Bank 1 I/O Memory Map

1-10

Device Bank1
Address Offset

Definition

0 0000

System Status Register 1

0 0001

System Status Register 2

0 0002

System Status Register 3

0 0003

Reserved

0 0004Presence Detect Register

0 0005

Software Readable Header/Switch

0 0006

Timebase Enable Register

0 0007

Geographical Address Register (VME board)

0 0008 - 0 FFFF

Reserved for future on-board registers

1 0000 - 1 7FFF

M48T37V NVRAM/RTC

2 0000 - 2 0FFF

COM1 16550 UART

2 1000 - 2 1FFF

COM2 16550 UART

2 4000 - F FFFF

Reserved (undefined)

Computer Group Literature Center Web Site

System Status Register 1

System Status Register 1
The MVME5500 board system status register 1 is used to provide board
status information and software control of Abort.

Table 1-10. System Status Register 1
REG
BIT

System Status Register 1 - Offset 0x0 0000
7

6

5

4

3

2

1

0

REF_CLKBANK_SEL

SAFE_START

ABORT_FLASH_BSY_

FUSE_STAT

RSVD

RSVD

FIELD

OPER

R

R

R

R/W

R

R

R

R

RESET

X

X

X

1

X

X

0

0

REF_CLK
Reference clock. This bit reflects the current state of the 28.8 KHz
reference clock derived from the 1.8432 MHz UART oscillator
divided by 64. This clock may be used as a fixed timing reference.
BANK_SEL
Boot Flash bank select. This bit reflects the current state of the bootFlash bank select jumper. A cleared condition indicates that Flash 0 is
the boot bank. A set condition indicates that Flash 1 is the boot bank.
SAFE_START
ENV safe start. This bit reflects the current state of the ENV safe start
select jumper. A cleared condition indicates that the ENV settings
programmed in NVRAM, VPD, and SPD should be used by thefirmware. A set condition indicates that firmware should use the safe
ENV settings.

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1-11

1

1

Board Description and Memory Maps

ABORT_
This bit reflects the current state of the on-board abort signal. Writinga 0 at this bit position asserts the abort interrupt output signal, whilewriting a 1 at this bit position clears the abort interrupt output signal.
Reading a 1 at this bit position indicates that the abort switch isdeasserted, while reading a 0 at this bit position indicates that the abortswitch is asserted.
FLASH_BSY_
Flash busy. This bit provides the current state of the Flash 0
StrataFlash device status pins. These two open drain output pins arewire ORed. Refer to the appropriate Intel StrataFlash data sheet for a
description on the function of the status pin.
FUSE_STAT
Fuse status. This bit indicates the status of the soldered, on-board fuses(R199 and R188). A cleared condition indicates that one of the fusesis open. A set condition indicates that all fuses are functional.

1-12

Computer Group Literature Center Web Site

System Status Register 2

System Status Register 2
The MVME5500 board system status register 2 provides board control andstatus bits.

Table 1-11. System Status Register 2
REG
BIT

System Status Register 2 - Offset 0x0 0001
7

6

5

4

3

2

1

0

BD_FAIL

EEPROM_WP

FLASH_WP

TSTAT_MASKRSVD

PCI 0.1_M66EN

PCI 1.0_M66EN

PCI 0.0_M66EN

FIELD

OPER

R/W

R/W

R/W

R/W

R

R

R

R

RESET

1

1

1

1

0

0

X

X

BD_FAIL
Board fail. This bit is used to control the board fail LED. A set
condition illuminates the front-panel LED and a cleared condition
extinguishes the front-panel LED.
EEPROM_WP
EEPROM write protect. This bit is to provide protection against
inadvertent writes to the on-board EEPROM devices. Clearing the bit
enables writes to the EEPROM devices. Setting this bit write protects
the devices. The devices are write protected following a reset.
FLASH_WP
Flash write protect. This bit is used to provide protection against
inadvertent writes to both Flash 0 and Flash 1 memory devices.
Clearing this bit enables writes to the Flash devices. Setting this bit
write protects the devices. This bit is set during reset and must be
cleared by the system software to enable writing of the Flash devices.

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1-13

1

1

Board Description and Memory Maps

TSTAT_MASK
Thermostat mask. This bit is used to mask the DS1621 temperature
sensor thermostat output. If this bit is cleared, the thermostat output isenabled to generate an interrupt on GPP 3. If the bit is set, thethermostat output is disabled from generating an interrupt.
PCI0.1_M66EN
PCI Bus 0.1 M66EN. This bit reflects the state of the PCI Bus 0.1
M66EN pin. A cleared condition indicates that PCI Bus 0.0 is
operating at 33 MHz. A set condition indicates that the bus is operating
at 66 MHz. This bit is always cleared on the MVME5500.
PCI1.0_M66EN
PCI Bus 1.0 M66EN. This bit reflects the state of the PCI Bus 1.0
M66EN pin. A cleared condition indicates that PCI Bus 1.0 is
operating at 33 MHz. A set condition indicates that the bus is operating
at 66 MHz.
PCI0.0_M66EN
PCI Bus 0.0 M66EN. This bit reflects the state of the PCI Bus 0.0
M66EN pin. A cleared condition indicates that PCI Bus 0 is operating
at 33 MHz. A set condition indicates that the bus is operating at
66 MHz.

1-14

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System Status Register 3

System Status Register 3
The MVME5500 board system status register 3 provides the board
software-controlled reset functions.

Table 1-12. System Status Register 3
REG
BIT

System Status Register 3 - Offset 0x0 0002
7

6

5

4

3

2

1

0

BRD_RST

RSVD

RSVD

RSVD

ABT_INT_MASK

RSVD

RSVD

RSVD

FIELD

OPER

W

R

R

R

R/W

R

R

R

RESET

0

0

0

0

1

0

0

0

BRD_RST
Board reset. Setting this bit forces a hard reset of the MVME5500
board. This bit clears automatically when the board reset is complete.
ABT_INT_MASK
Abort interrupt mask. This bit is used to mask the abort interrupt. If
this bit is set, the abort interrupt is masked so the abort interrupt is not
generated. If the bit is cleared, the abort interrupt may be generated.

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1-15

1

Board Description and Memory Maps

Presence Detect Register
The MVME5500 board contains a presence detect register that may beread by the system software to determine the presence of optional devices.

Table 1-13. Presence Detect Register
REG
BIT

Presence Detect Register - Offset 0x0 0004h
7

6

5

4

3

2

1

0

RSVD

RSVD

RSVD

RSVD

PMC_SPANP_PMC2P_

PMC1P_

FIELD

RSVD

1

OPER

R

R

R

R

R

R

R

R

RESET

1

1

1

1

1

X

X

X

PMC_SPANP_
PMC expansion module present. If set, there is no PMC expansion
module installed. If cleared, the PMC expansion module is installed.
PMC2P_
PMC module 2 present. If set, there is no PMC module installed inposition 2. If cleared, the PMC module is installed.
PMC1P_
PMC module 1 present. If set, there is no PMC module installed inposition 1. If cleared, the PMC module is installed.

1-16

Computer Group Literature Center Web Site

Configuration Header/Switch Register (S1)

Configuration Header/Switch Register (S1)The MVME5500 board has an 8-bit header or switch that may be read by
the software.

Table 1-14. Configuration Header/Switch Register

BIT

7

6

5

4

3

2

1

0

FIELD

CFG_6

CFG_5

CFG_4

CFG_3

CFG_2

CFG_1

CFG_0

Configuration Header/Switch Register - Offset 0x0 0005h

CFG_7

REG

OPER

R

R

R

R

R

R

R

R

RESET

X

X

X

X

X

X

X

X

CFG[7-0]
Configuration bits 7-0. These bits reflect the position of the switch
installed in the software readable header location. A cleared conditionindicates that the switch is ON for the header position associated withthat bit and a set condition indicates that the switch is OFF.
1

16

1

8

CFG_7 = 0

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CFG_5 = 1
CFG_6 = 1

87

CFG_6 = 0

CFG_4 = 1

7

6

CFG_5 = 0

CFG_3 = 1

65

CFG_4 = 0

CFG_2 = 1

5

4

CFG_3 = 0

CFG_1 = 1

4

3

CFG_2 = 0

CFG_0 = 1

3

2

CFG_1 = 0

162

CFG_0 = 0

ON
1

1

ON

CFG_7 = 1

1-17

1

Board Description and Memory Maps

Time Base Enable Register
The time base enable (TBEN) register provides the means to control theprocessor’s TBEN input.

Table 1-15. TBEN Register
REG
BIT

1

0
TBEN0

2

RSVD

3

RSVD

4

RSVD

5

RSVD

6

RSVD

7

RSVD

FIELD

TBEN Register- Offset 0x0 0006

RSVD

1

OPER

R

R

R

R

R

R

R

R/W

RESET

0

0

0

0

0

0

0

1

TBEN0
Processor time base enable. When this bit is cleared, the TBEN pin of
the processor is driven low. When this bit is set, the TBEN pin is driven
high.

Geographical Address Register (S2)This register reflects the inverted states of the geographical address pins at
the 5-row, 160-pin P1 connector. Applications not using the 5-row
backplane can use a planar switch (same type as the Configuration
Header/Switch Register (S1) on page 1-17) to assign a geographicaladdress according to the following diagram.

1-18

Computer Group Literature Center Web Site

Geographical Address Register (S2)Note

The switch positions must all be turned off when the
MVME5500 is used in a 5-row backplane.

Table 1-16. Geographical Address Register

1

BIT

7

6

5

4

3

2

1

0

FIELD

VMEGA1_VMEGA2_VMEGA3_VMEGA4_

RSVD

RSVD

VMEGAP_

Geographical Address Register - 0xFF100007

VMEGA0_

REG

OPER

R

R

R

R

R

R

R

R

RESET

X

X

X

X

X

X

X

X

16

1

8

GA0* = 0

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GA2* = 1
GA1* = 18

7

GA1* = 0

GA3* = 1

7

6

GA2* = 0

GA4* = 1

6

5

GA3* = 0

Not used

5

4

GA4* = 0

Not used4

3

Not used

GAP* = 1

3

2

Not used

16

2

GAP* = 0

ON
1

1

ON

GA0* = 1

1-19

1

1

Board Description and Memory Maps

COM1 & COM2 Universal Asynchronous
Receiver/Transmitter (UART)
COM1 and COM2 are PC16550 Universal Asynchronous
Receiver/Transmitter (UART) to provide an asynchronous serial interface
for test/debug purposes. To facilitate proper baud rate generation, thefrequency of the input clock for the PC16550 UART is fixed at
1.8432 MHz. For additional programming details, refer to the PC16550
Data Sheet.

Real-Time Clock and NVRAM
The SGS-Thomson M48T37 is used by the MVME5500 board to provide
32KB of non-volatile static RAM, real-time clock, and watchdog timer
functions. The device is accessed as linear memory. Refer to the MK48T37
Data Sheet for programming information.

ISA Local Resource Bus
The ISA local resources exist only if an IPMC712/761 module is mounted
on the MVME5500. Refer to the IPMC712/761 I/O Module Installationand Use, listed in Appendix B, Related Documentation.

1-20

Computer Group Literature Center Web Site

2Programming Details

2

Introduction
This chapter includes additional programming information for the
MVME5500 single-board computer. Items discussed include:❏ PCI Configuration Space and IDSEL Mapping on page 2-1❏ Interrupt Controller on page 2-3❏ Two-Wire Serial Interface on page 2-5❏ GT-64260B Initialization on page 2-7❏ GT-64260B GPP Configuration on page 2-7❏ GT-64260B Reset Configuration on page 2-9❏ GT-64260B Device Controller Bank Assignments on page 2-11
❏ System Clock Generators on page 2-13
❏ VPD and User Configuration EEPROMs on page 2-14
❏ Temperature Sensor on page 2-14
❏ Flash Memory on page 2-14
❏ PCI Arbitration Assignments on page 2-14
❏ Other Software Considerations on page 2-15

PCI Configuration Space and IDSEL Mapping
Each PCI device has an associated address line connected via a resistor to
its IDSEL pin for configuration space accesses. Table 2-1 shows the
IDSEL assignments for the PCI devices on each of the PCI buses on the
MVME5500 board along with the corresponding interrupt assignment to
the general-purpose port (GPP) pins. Refer to the GT-64260B System
Controller for PowerPC Processors Data Sheet and the PCI 6154 (HB2)
PCI-to-PCI Bridge Data Book, both listed in Appendix B, Related

2-1Programming Details

Documentation, for details on generating configuration cycles on each of
the PCI buses.

2

Table 2-1. IDSEL Mapping for PCI Devices
Device INT# to GPP Interrupt
Input

PCI
Bus

DeviceNumber Field

PCI
AD
Line

0.0

0b0_0001

AD11

IPMC

11

0b0_0110

AD16

PMC 1
(J11,12,13,14)

80b0_0111

AD17

PMC 1 IDSEL B

0b0_1010

AD20

HiNT PCI 6154
Bridge0b1_0101

AD31

GT-64260B PCI
Bridge0b0_0000

AD16

CA91C142D VME
VLINT0

12

CA91C142D VME
VLINT1

13

CA91C142D VME
VLINT2

14

CA91C142D VME
VLINT315

PMC Expansion

12

0.1

0b0_0100

AD20

Physical PCI
Device

INTA#

INTB#

INTC#

INTD#

9

10

11

13

14

15

Note Device-specific interrupt
routing is established on the PMCspanboard. Refer to the PMCspan PMC
Adapter Carrier Board Installationand Use manual, listed in Appendix
B, Related Documentation.

2-2

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Interrupt Controller

Table 2-1. IDSEL Mapping for PCI Devices (continued)

PCI
Bus

DeviceNumber Field

PCI
AD
Line

1.0

0b0_0110

AD16

PMC 2
(J21,22,23,24)0b0_0111

AD17

PMC 2 IDSEL B

0b0_1010

AD20

82C544 Ethernet 10b1_0101

AD31

GT-64260B PCI
BridgePhysical PCI
Device2

Device INT# to GPP Interrupt
Input
INTA#

INTB#

INTC#

INTD#

16

17

18

19

20

Interrupt Controller
The MVME5500 uses the GT-64260B interrupt controller to handle
interrupts internal to the GT-64260B, as well as the external interrupt
sources. The GT-64260B has a limited number of directly triggerable
interrupt inputs. Each of the GPP pins can be configured for an interrupt
input, but the inputs are combined internally in groups of eight inputs (onefor each byte lane) for one interrupt source. Therefore, interrupt inputs ineach byte lane are essentially shared. Currently defined externalinterrupting devices and GPP interrupt assignments are shown in Table
2-2.
The GT-64260B has one dedicated processor interrupt output, CPUINT_,
which is connected to the primary processor CPU0 INT_L input. Refer tohttp://www.motorola.com/computer/literature

2-3

Programming Details

the GT-64260B System Controller for PowerPC Processors Data Sheet,
listed in Appendix B, Related Documentation, for details.

2

Table 2-2. GT-64260B External GPP Interrupt Assignments
GPP
Group

GPP #

Edge/
Level

Polarity

Interrupt Source

0

0

Level

High

COM1 || COM2

1

Level

Low

Not Used. Pulled High.

2

Level

Low

Abort Switch

3

Level

Low

RTC || Thermostat Output

4

Level

Low

Not Used. Pulled high, tied to GPP27.

5

Level

Low

Not Used. Pulled high, tied to GPP28.

6

Level

Low

GT-64260B WDMNI Interrupt. Tied to GPP24.

7

Level

Low

LXT971A Interrupt (10/100Mbit PHY)

8

Level

Low

PMC 1 Interrupt INT A

9

Level

Low

PMC 1 Interrupt INT B

10

Level

Low

PMC 1 Interrupt INT C

11

Level

Low

PMC 1 Interrupt INT D || IPMC INT

12

Level

Low

VME Interrupt VLINT0

13

Level

Low

VME Interrupt VLINT1

14

Level

Low

VME Interrupt VLINT2

15

Level

Low

VME Interrupt VLINT3

1

2-4

Computer Group Literature Center Web SiteTwo-Wire Serial Interface

Table 2-2. GT-64260B External GPP Interrupt Assignments (continued)
GPP
Group

GPP #

Edge/
Level

Polarity

Interrupt Source

2

16

Level

Low

PMC 2 Interrupt INT A

17

Level

Low

PMC 2 Interrupt INT B

18

Level

Low

PMC 2 Interrupt INT C

19

Level

Low

PMC 2 Interrupt INT D

20

Level

Low

82544 Interrupt

21

Level

Low

Not Used. Pulled High.

22

Level

Low

Not Used. Pulled High.

23

Level

Low

Not Used. Pulled High.

3

24

Watchdog Timer NMI Output WDNMI# to
GPP6

25

Watchdog Timer Expired Output WDE#

26

GT-64260B SROM Initialization Active InitAct

27

Level

Low

Not Used. Pulled high, tied to GPP4.

28

Not Used. Pulled high, tied to GPP5.

29

Optional External PPC Bus Arbiter BG1 Enable

30

Unused. Pulled High.

31

Unused. Pulled High.

Two-Wire Serial Interface
A two-wire serial interface for the MVME5500 board is provided by an
I2C compatible serial controller integrated into the GT-64260B system
controller. The I2C serial controller provides two basic functions. The firstfunction is to provide GT-64260B register initialization following a reset.
The GT-64260B can be configured (by jumper setting) to automaticallyread data out of a serial EEPROM following a reset and initialize any
number of internal registers. In the second function, the controller is usedby the system software to read the contents of the VPD EEPROM

http://www.motorola.com/computer/literature

2-52Programming Details

contained on the MVME5500 board, along with the SPD EEPROMs, tofurther initialize the memory controller and other interfaces. For additional
details regarding the GT-64260B two-wire serial controller operation, referto the GT-64260B System Controller for PowerPC Processors Data Sheet,
listed in Appendix B, Related Documentation.

2

Table 2-3 shows the I2C devices used for the MVME5500 and the assigned
device IDs.

Table 2-3. I2C Bus Device Addressing

Device Function

Size

DeviceAddress(A2A1A0)

Memory SPD (On-board. Banks A and B.)

256 x 8

000b

$A0

1, 2

Memory SPD (On mezzanine. Banks C and D.)

256 x 8

001b

$A2

1

IPMC VPD

256 x 8010b

$A4GT-64260B Fixed Initialization

256 x 8

011b

$A6

2

Configuration VPD

8K x 8

100b

$A8

2, 3

User VPD

8K x 8

101b

$AA

2, 3

Not Used

NA

110b

$AC

Not Used

NA

111b

$AE

DS1621 Temperature Sensor

NA

000b

$90

Notes

I2C BUS
Address

Notes

1. Each SPD defines the physical attributes of each bank orgroup of banks, that is, if both banks of a group are
populated, they will be the same speed and memory size.
2. This device can be write-protected by either setting the
EEPROM_WP bit of SSR2 or by placing a jumper on the
EEPROM write protect header. The hardware jumper
mechanism always takes precedence over the softwaresetting. For 8KB sized parts, only the upper 2KB are writeprotectable.
3. This is a 2-byte address serial EEPROM (AT24C64).

2-6

Computer Group Literature Center Web Site

GT-64260B Initialization

GT-64260B Initialization

2

Serial EEPROM devices are provided to support optional initialization of
the GT-64260B (enabled by an on-board jumper). Using the SROM
initialization method, any of the GT-64260B internal registers or othersystem components (that is, devices on the PCI bus) can be initialized.
Initialization takes place by sequentially reading 8-byte address/data pairs
from the SROM and writing the 32-bit data to the decoded 32-bit addressuntil the data pattern matching the last serial data item register is read for
the SROM (default value = 0xffffffff). The on-board reset logic keeps theprocessor reset asserted until this initialization process is completed.

GT-64260B GPP Configuration
The GT-64260B contains a 32-bit GPP. The GPP pins can be configured as
general-purpose I/O pins, as external interrupt inputs, or as specificcontrol/status pins for one of the GT-64260B internal devices. After reset,
all GPP pins default to general-purpose inputs. Software must thenconfigure each of the pins for the desired function. The following tabledefines the function assigned to each GPP pin on the MVME5500 board.

Table 2-4. GT-64260B GPP Pin Function Assignments
GPP Number

Input/Output

Function0ICOM1/COM2 interrupts (ORed)

1

I

Not Used. Pulled High.

2

I

Abort Interrupt

3

I

RTC and Thermostat Interrupts (ORed)

4O

Not Used. Pulled high, tied to GPP27.

5I

Not Used. Pulled high, tied to GPP28.

6I

GT-64260B WDMNI Interrupt. Tied to GPP24.

7

I

LXT971A Interrupt (10/100Mbit PHY)

8I

PMC 1 Interrupt INT A

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2-7

Programming Details

2

Table 2-4. GT-64260B GPP Pin Function Assignments (continued)

2-8

GPP Number

Input/Output

Function

9I

PMC 1 Interrupt INT B

10I

PMC 1 Interrupt INT C

11I

PMC 1 Interrupt INT D/IPMC INT

12IVME Interrupt 0

13

I

VME Interrupt 1

14I

VME Interrupt 2

15I

VME Interrupt 3

16

I

PMC 2 Interrupt INT A

17I

PMC 2 Interrupt INT B

18

I

PMC 2 Interrupt INT C

19I

PMC 2 Interrupt INT D

20

I82544 Interrupt

21

I

Not Used. Pulled High.

22

I

Not Used. Pulled High.

23

I

Not Used. Pulled High.

24

O

Watchdog Timer NMI Output WDNMI# to GPP6

25

O

Watchdog Timer Expired Output WDE#

26

O

GT-64260B SROM Initialization Active InitAct

27

I

Not Used. Pulled high, tied to GPP4.

28

O

Not Used. Pulled high, tied to GPP5.

29

O

Optional external PPC Bus Arbiter BG1 Enable.

30

I

Not Used. Pulled High.

31

I

Not Used. Pulled High.

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GT-64260B Reset Configuration

GT-64260B Reset Configuration

2

The GT-64260B supports two methods of device initialization following
reset:❏ Pins sampled on the deassertion of reset❏ Partial pin sample on deassertion of reset plus serial ROM
initialization via the I2C bus
The MVME5500 board supports both options listed above. An on-board
jumper setting is used to select the option. If the pin-sample-only method
is selected, then states of the various pins on the device AD bus are
sampled when reset is deasserted to determine the desired operating
modes. Table 2-5 on page 2-10 describes the configuration options.
Combinations of pullups, pulldowns, and jumpers are used to set theoptions. Some options are fixed and some are selectable at build time byinstalling the proper pullup/pulldown resistor. Finally, some options may
be selected using on-board jumpers.
Using the SROM initialization method, any of the GT-64260B internalregisters or other system components (that is, devices on the PCI bus) canbe initialized. Initialization takes place by sequentially reading 8-byte
address/data pairs from the SROM and writing the 32-bit data to thedecoded 32-bit address until the last serial data item of 0xffffffff is read. If
the SROM initialization option is selected, the following pins are stillsampled to determine certain operating parameters:❏ AD(1) – SROM byte offset width❏ AD(3:2) – SROM address❏ AD(4) – CPU endianess

http://www.motorola.com/computer/literature

2-9Programming Details❏ AD(30:28) – PLL settings

2❏ AD(31) – CPU interface voltage

Table 2-5. GT-64260B Power-Up Configuration Settings
Device AD
Bus Signal

SelectOptionDefault
Power-Up
Setting

Description

State of Bit vs. Function

AD[0]Jumperx

SROM Initialization0

No SROM
Initialization

1

SROM Initialization
EnabledAD[1]Resistor

0

SROM Byte Offset
Width

0

Up to 8 Bits

AD[3:2]

Resistors

11

SROM Device
Address

11

1010011 ($A6)

AD[4]

Fixed

0

CPU Data Endianess0

Must be Pulled Down

AD[5]

Fixed

1

CPU Interface Clock1

CPU Interface
Synchronous with
TClk

AD[6]

Jumperx

CPU BusConfiguration

0

60x Bus Mode

1

MPX Bus ModeAD[8]Resistor

1

Internal 60x Bus
Arbiter

1

Internal Arbiter
Enabled

AD[9]

Fixed

0

Multiple GT-64260B
Support0

Not Supported

AD[11:10]

Fixed

11

Multiple GT-64260B
Address ID

11

GT Responds to CPU
Address A[5:6] = 11

AD[12]Fixed

0

SDRAM UMA

0

Not Supported

AD[13]Fixed0

UMA Device Type

0

UMA MasterAD[15:14]

Fixed

10

BootCS* Device
Width

10

32 Bits

AD[16]

Resistor

1

PCI Retry1

Enable2-10Computer Group Literature Center Web Site

GT-64260B Device Controller Bank Assignments

Table 2-5. GT-64260B Power-Up Configuration Settings (continued)
Device AD
Bus Signal

SelectOptionDefault
Power-Up
SettingAD[17]

Fixed

AD[18]

Description

State of Bit vs. Function0

PCI_0 Expansion
ROM

0

Not Supported

Fixed

0

PCI_1 Expansion
ROM

0

Not Supported

AD[22:19]

Fixed

0000

Reserved

0000

Must be Pulled Down

AD[23]

Fixed

1

SDClkIn/
SDClkOut Select1

SDClkIn

AD[24]

Resistor

1

Internal Space Default
Address

1

0xf100.0000

AD[27:25]

Fixed

000

Reserved

000

Must be Pulled Down

AD[28]

Resistor

0

PLL Tune0

Tuning Option 0

AD[29]

Resistor0

PLL Divider

0

Divider Option 0AD[30]

Resistor

0

PLL Bypass

0

PLL Enabled

AD[31]Fixed

0

CPU Interface Voltage

0

2.5V

GT-64260B Device Controller Bank
Assignments
The MVME5500 board uses three of the GT-64260B device controllerbanks for interfacing to various devices. The following tables define thedevice bank assignments and the programmable device bank timing
parameters required for each of the banks used. Note that all device bank

http://www.motorola.com/computer/literature

2-11

2

Programming Details

timing parameters, except BAdrSkew, have an extension bit that forms themost significant bit of the timing parameter.

2

Table 2-6. Device Bank Assignments
Device Bank

Data Width

Function

Note0

32 bitFlash 0 Soldered Flash or Flash
1 Soldered Flash

1

1

8 bit

I/O Devices

2NA

Not used3

NA

Not usedBoot

32 bitFlash 1 Soldered Flash or Flash0 Soldered Flash

Note

1

1. Determined by Flash boot bank select jumper.

Table 2-7. Device Bank Timing Parameters

BAdrSkew

WrHighExt - WrHigh

WrLowExt - WrLow

ALE2WrExt - ALE2Wr

TurnOff Ext - TurnOff

GT-64260B
Tclk Clock
Freq.

Acc2NextExt - Acc2Next

DeviceBank

Acc2FirstExt - Acc2First

Device Bank Timing Parameter Min. Value

Flash 0(150 ns)

100 MHz

1-1

0-3

0-6

0-3

0-7

0-4

0

133 MHz

1-6

0-4

0-8

0-3

1-2

0-5

0

Flash 0(120 ns)

100 MHz

0-e

0-3

0-6

0-3

0-7

0-4

0

133 MHz

1-2

0-4

0-8

0-3

1-2

0-5

0

2-12

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System Clock Generators

Table 2-7. Device Bank Timing Parameters (continued)

2

BAdrSkew

WrHighExt - WrHigh

WrLowExt - WrLow

ALE2WrExt - ALE2Wr

TurnOff Ext - TurnOff

GT-64260B
Tclk Clock
Freq.

Acc2NextExt - Acc2Next

DeviceBank

Acc2FirstExt - Acc2First

Device Bank Timing Parameter Min. Value

Flash 0(100 ns)

100 MHz

0-c

0-3

0-6

0-3

0-7

0-4

0

133 MHz

1-0

0-4

0-8

0-3

1-2

0-5

0

DeviceBank1
I/O

100 MHz

0-c

0-a

0-5

0-3

1-0

0-4

0

133 MHz

1-0

0-e

0-7

0-3

1-3

0-6

0

Flash 1(90 ns)100 MHz

0-b

0-9

0-3

0-3

0-4

0-3

0

133 MHz

0-e

0-c

0-4

0-3

0-5

0-4

0

Note

Flash 0 contains 100 ns, 120 ns, or 150 ns StrataFlash devices.
Device speed can be determined from VPD.

System Clock Generators
The system clock generator functions generate and distribute all of theclocks required for system operation. The clocks for the processor,
memory, and PCI devices consist of a clock tree derived from a 66 MHz
oscillator and a series of PLL clock generators. The clock tree is designed
in such a manner as to maintain the strict edge-to-edge jitter and low clockto-clock skew required by these devices. Additional clocks required byindividual devices are generated near the devices using individual
oscillators.

http://www.motorola.com/computer/literature

2-13

Programming Details

2

VPD and User Configuration EEPROMs
The MVME5500 board contains an Atmel AT24C64 vital product data
(VPD) EEPROM containing configuration information specific to theboard. Typical information that may be present in the VPD is:
manufacturer, board revision, build version, date of assembly, memory
present, options present, L3 cache information, etc. A second AT24C64
device is available for user data storage.

Temperature Sensor
The MVME5500 board contains a Maxim DS1621 digital temperature
sensor with an I2C serial bus interface. This device may be used to provide
a measure of the ambient temperature of the board.

Flash Memory
The MVME5500 contains two banks of Flash memory accessed via thedevice controller contained within the GT-64260B. Flash 1 consists of two
soldered 32Mb devices (E28F320J3A) to give a minimum of 8MB Flashmemory. Flash 0 consists of two Intel StrataFlash 3.3 volt devices,configured to operate in 16-bit mode, to form a 32-bit Flash port. This bankcontains 64Mb devices (E28F128J3A) for 32MB of Flash.
There is a Flash boot bank select jumper on board, which selects either
Flash 0 or Flash 1 as the boot bank. No jumper or a jumper installed
between pins 1 and 2 selects Flash 0 as the boot bank. A jumper installed
between pins 2 and 3 selects Flash 1 as the boot bank.

PCI Arbitration Assignments
PCI arbitration for PCI Bus 0.0 and PCI Bus 1.0 is handled using logic
implemented in PLDs. These arbiters use a rotating priority scheme forfairness and bus parking will always be on the GT-64260B. There are nosoftware programmable modes to these arbiters.

2-14

Computer Group Literature Center Web SiteOther Software Considerations

PCI arbitration for PCI Bus 0.1 is provided by the HiNT PCI 6154
secondary side arbiter.

2

Table 2-8. PCI Arbiter Assignments
PCI BusNumber

REQ/GNTPair

PCI Device

0.0

0GT-64260B Host

1

PMC Req 1

2

PMC Req 2

3

PCI-to-PCI Bridge(HiNT PCI 6154)

4

Not Used

0

PCI/PMC Expansion

1

VME Controller0GT-64260B Host

1

PMC Req 1

2

PMC Req 2

3

82544

4

Not Used

0.1

1.0

Other Software Considerations
The following subsections discuss software aspects of the CPU bus,
processor, and cache that can have an influence on the MVME5500.

CPU Bus Mode
The CPU bus operating mode (60x or MPX) is determined by reading the
BMODE bits (bits 16-17) in the processor’s Memory Subsystem Control
Register (MSSCR0). The power-up state of the BMODE(0:1) pins is
captured in these register bits. Refer to the MPC7450 RISC

http://www.motorola.com/computer/literature

2-15

Programming Details

Microprocessor User’s Manual, listed in Appendix B, Related
Documentation, for details.

2

Processor Type Identification
Software can determine the processor version through the version register.
The most significant 16 bits (0:15) of the MPC7455 processor version
register reads as 0x8001.

Processor PLL Configuration
The processor internal clock frequency (core frequency) is a multiple ofthe system bus frequency. The processor has five configuration pins,
PLL_EXT and PLL_CFG[0:3], for hardware strapping of the processor
core frequency (between 2x and 16x of the system bus frequency).

L1, L2, L3 Cache
The processors support on-chip L1 and L2 caches and external L3 cache.
L3 cache supports 1 or 2MB in a variety of SRAM device types. Eachprocessor L3 interface on the MVME5500 consists of two 8Mb devices(K7D803671B-HC30) providing a total of 2MB of L3 cache. Data parity
checking should be enabled. The following processor L3CR registersettings assume a processor speed of 933 MHz and L3 clock speed of
233 MHz.

Table 2-9. Processor L3CR Register Assignments

2-16

Apollo L3CR
Register

Description

Value

L3SIZ

L3 Size, 2 MB

1

L3RT

L3 SRAM Type, DDR SRAM

00

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L1, L2, L3 Cache

Table 2-9. Processor L3CR Register Assignments
Apollo L3CR
Register

Description

Value

L3PE

L3 Data Parity Checking Enable, ON

1

L3CLK

L3 Clock Speed; 233 MHz, Divide by 4 110

L3CKSP

L3 Clock Sample Point, 2 Clocks

TBD

L3PSP

L3 P-Clock Sample Point, 3 Clocks

TBD

http://www.motorola.com/computer/literature

2

2-17

AVital Product Data

A

This appendix gives an overview of the vital product data (VPD) required
for the MVME5500.

Flash Memory Configuration Data
The Flash memory configuration data packet consists of byte fields thatindicate the size/organization/type of the Flash memory array. Table A-1
and Table A-2 further describe the Flash memory configuration VPD data
packet.

Table A-1. Flash 0 Memory Configuration Data
Byte
OffsetField Size
(Bytes)Field Mnemonic

Field Description

00

2

FMC_MID

Manufacturer’s Identifier

02

2

FMC_DID

Manufacturer’s Device Identifier04

1

FMC_DDW

Device Data Width (16 bits on MVME5500)

051

FMC_NOD

Number of Devices Present(two on MVME5500)

061

FMC_NOC

Number of Columns (Interleaves)(two on MVME5500)

071

FMC_CW

Column Width in Bits (16 on MVME5500)
This will always be a multiple of the device’s
data width.

A-1

A

Vital Product Data

Table A-1. Flash 0 Memory Configuration Data (continued)
Byte
OffsetField Size
(Bytes)Field Mnemonic

Field Description

08

1

FMC_WEDW

Write/Erase Data Width (16 on MVME5500)
The Flash memory devices must be
programmed in parallel when the write/erase
data width exceeds the device’s data width.

09

1

FMC_BANKBank Number of Flash Memory Array: 0 for
this bank

0A

1

FMC_SPEEDROM Access Speed in Nanoseconds

0B

1

FMC_SIZE

Total Bank Size (Should agree with thephysical organization above):
07 = 32M

Table A-2. Flash 1 Memory Configuration Data
Byte
OffsetField Size
(Bytes)Field Mnemonic

Field Description

00

2

FMC_MID

Manufacturer’s Identifier(FFFF = Undefined/Not-Applicable)

02

2

FMC_DID

Manufacturer’s Device Identifier(FFFF = Undefined/Not-Applicable)

04

1

FMC_DDW

Device Data Width (16 bits on MVME5500)

051

FMC_NOD

Number of Devices Present(two on MVME5500)

061

FMC_NOC

Number of Columns (Interleaves)(two on MVME5500)

071

FMC_CW

Column Width in Bits (16 on MVME5500)
This will always be a multiple of the device’s
data width.

A-2

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L3 Cache Configuration Data

Table A-2. Flash 1 Memory Configuration Data (continued)
Byte
OffsetField Size
(Bytes)Field Mnemonic

Field Description

08

1

FMC_WEDW

Write/Erase Data Width (16 on MVME5500)
The two memory devices must be
programmed in parallel when the write/erase
data width exceeds the device’s data width.

09

1

FMC_BANKBank Number of Memory Array: 1 for this
bank

0A

1

FMC_SPEEDROM Access Speed in Nanoseconds

0B

1

FMC_SIZE

Total Bank Size (Should agree with thephysical organization above):
03 = 2M for this bank

L3 Cache Configuration Data
The L3 cache configuration data packet consists of byte fields that indicate
the size/organization/type of the L3 cache memory array. Table A-3 further
describes the L3 cache memory configuration VPD data packet.

Table A-3. L3 Cache Configuration Data
Byte Offset

Field Size (Bytes)

Field Description

00

1Which processor is cache connected to:
01 - 1st Processor

011

Cache size:
01 - 2MB02

1

L3 cache core to cache ratio:(Backside Configurations - setting depends on processor core
speed and SRAM capability)
06 - 4:1 (4)031Cache clock sample point:
02 - 4 clocks

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A-3

A

A

Vital Product Data

Table A-3. L3 Cache Configuration Data (continued)
Byte Offset

Field Size (Bytes)

Field Description

04

1

Processor clock sample point:
03 - 3 clocks

05

1

Sample point override:
00 - sample point override disabled

06

1

SRAM clock control:
00 - SRAM clock control disabled

07

1

SRAM type:
00 - MSUG2 DDR SRAM

08

1

Data bus error detection type:01 - parity

09

1

Address bus error detection type:
00 - None

A-4

Computer Group Literature Center Web Site

BRelated Documentation

B

Motorola Computer Group Documents
The Motorola publications listed below are referenced in this manual. You
can obtain electronic copies of Motorola Computer Group publications by:❏ Contacting your local Motorola sales office❏ Visiting Motorola Computer Group’s World Wide Web literaturesite, http://www.motorola.com/computer/literature

Table B-1. Motorola Computer Group Documents
Document Title

Motorola Publication
Number

MVME5500 Single-Board Computer Installationand Use

V5500A/IH

MVME761 Transition Module Installation and Use

VME761A/IH

MVME712M Transition Module Installation andUse

VME712MA/IH

MOTLoad Firmware Package User’s Manual

MOTLODA/UM

IPMC712/761 I/O Module Installation and Use

VIPMCA/IH

PMCspan PMC Adapter Carrier Board Installationand UsePMCSPANA/IH

To obtain the most up-to-date product information in PDF or HTML
format, visit http://www.motorola.com/computer/literature

B-1

Related Documentation

B

Manufacturers’ Documents
For additional information, refer to the following table for manufacturers’
data sheets or user’s manuals. As an additional help, a source for the listed
document is provided. Please note that, while these sources have beenverified, the information is subject to change without notice.

Table B-2. Manufacturers’ Documents
Document Title and Source

Publication Number

MPC7450 RISC Microprocessor User’s Manual
Literature Distribution Center for Motorola
Telephone: 1-800- 441-2447
FAX: (602) 994-6430 or (303) 675-2150

MPC7450UM/D Rev 2

Web Site: http://ewww.motorola.com/webapp/sps/library/prod_lib.jsp
E-mail: ldcformotorola@hibbertco.com
MPC7450 RISC Microprocessor Hardware Specification
Literature Distribution Center for Motorola
Telephone: 1-800- 441-2447
FAX: (602) 994-6430 or (303) 675-2150

MPC7450EC/D Rev 3

Web Site: http://ewww.motorola.com/webapp/sps/library/prod_lib.jsp
E-mail: ldcformotorola@hibbertco.com
GT-64260B System Controller for PowerPC Processors Data Sheet

MV-S100414-00B

Marvell Technologies, Ltd.
Web Site: http://www.marvell.com
Intel 82544EI Gigabit Ethernet Controller with Integrated PHY Data
Sheet82544.pdf

Intel Corporation
Literature Center
19521 E. 32nd Parkway
Aurora CO 80011-8141
Web Site: http://www.intel.com/design/litcentr/index.htm

B-2

Computer Group Literature Center Web Site

Manufacturers’ Documents

Table B-2. Manufacturers’ Documents (continued)
Document Title and Source

Publication Number

LXT971A 10/100Mbit PHY Datasheet

24941402.pdf

BIntel Corporation
Literature Center
19521 E. 32nd Parkway
Aurora CO 80011-8141
Web Site: http://www.intel.com/design/litcentr/index.htm
3 Volt Synchronous Intel StrataFlash Memory 28F640K3,
28F640K18, 28F128K3, 28F128K18, 28F256K3,

290737-003

28F256K18 (x16)Intel Corporation
Literature Center
19521 E. 32nd Parkway
Aurora CO 80011-8141
Web Site: http://www.intel.com/design/litcentr/index.htm
3 Volt Intel StrataFlash Memory
28F128J3A, 28F640J3A, 28F320J3A

290667-005

Intel Corporation
Literature Center
19521 E. 32nd Parkway
Aurora CO 80011-8141
Web Site: http://www.intel.com/design/litcentr/index.htm
PCI 6154 (HB2) PCI-to-PCI Bridge Data Book
PLX Technology, Inc.
870 Maude Avenue
Sunnyvale, California 94085
Web Site: http://www.hintcorp.com/products/hint/default.asp

http://www.motorola.com/computer/literature

6154_DataBook_v2.0.pdf

B-3Related Documentation

Table B-2. Manufacturers’ Documents (continued)

B

Document Title and Source

Publication Number

TL16C550C Universal Asynchronous Receiver/Transmitter

SLLS177E

Texas Instruments
P. O. Box 655303
Dallas, Texas 75265
Web Site: http://www.ti.com
M48T37V

3.3V-5V 256Kbit (32Kx8) Timekeeper SRAM
ST Microelectronics
1000 East Bell Road
Phoenix, AZ 85022
Web Site: http://eu.st.com/stonline/index.shtml

AT24C02
AT24C04
AT24C64
AT24C256
AT24C512

2-Wire Serial CMOS EEPROM
Atmel Corporation
San Jose, CA
Web Site: http://www.atmel.com/atmel/support/
Universe II User Manual
Tundra Semiconductor Corporation
Web Site:
http://www.tundra.com/page.cfm?tree_id=100008#Universe II(CA91C042)

B-4

8091142_MD300_01.pdf

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Related Specifications

Related Specifications

B

For additional information, refer to the following table for related
specifications. For your convenience, a source for the listed document isalso provided. It is important to note that in many cases, the information ispreliminary and the revision levels of the documents are subject to change
without notice.

Table B-3. Related Specifications
Document Title and Source
VITA

Publication Number

http://www.vita.com/

VME64 Specification

ANSI/VITA 1-1994

VME64 Extensions

ANSI/VITA 1.1-1997

2eSST Source Synchronous Transfer

VITA 1.5-199x

PCI Special Interest Group (PCI SIG) http://www.pcisig.com/
Peripheral Component Interconnect (PCI) Local Bus Specification,
Revision 2.0, 2.1, 2.2

http://www.motorola.com/computer/literature

PCI Local Bus
Specification

B-5

IndexB
block diagram 1-4

Ccache 2-16comments, sending xiv
config switch register 1-17
conventions used in the manual xiv
core frequency 2-16
CPU bus mode 2-15

D
default PCI memory map 1-7
default processor memory map 1-5
documentation, related B-1

F

interrupt controller 2-3

L
L1, L2, L3 cache 2-16
L3 cache config data A-3

Mmanual conventions xiv
manufacturers’ documents B-2
memory maps
default PCI 1-7
default processor 1-5
MOTLoad’s PCI 1-9
MOTLoad’s processor 1-6
system I/O 1-10
MOTLoad’s PCI memory map 1-9
MOTLoad’s processor memory map 1-6

features 1-2
Flash memory 2-14
config data A-1

N

G

P

geographical address register 1-18
GT-64260B system controller 2-1
device bank timing 2-12
device controller banks 2-11
GPP config 2-7
GPP interrupts 2-4
I2C 2-5
initialization 2-7
interrupt controller 2-3
power-up config 2-10
reset config 2-9

PCI arbiter 2-15
PLL clock generators 2-13
presence detect register 1-16
processor bus mode 2-15
processor version register 2-16

I
I2C 2-5
IDSEL mapping 2-2

NVRAM 1-20

R
real-time clock 1-20
registers
config switch register 1-17
geographical address register 1-18
presence detect register 1-16
system status register 1 1-11
system status register 2 1-13
system status register 3 1-15

IN-1

time base enable register 1-18
related documentation B-1

time base enable register 1-18

S

typeface, meaning of xiv

suggestions, submitting xiv
system clock generators 2-13
system I/O memory map 1-10
system status register 1 1-11
system status register 2 1-13
system status register 3 1-15

two-wire serial interface 2-5

U
UART 1-20

V
vital product data (VPD) 2-14, A-1

T

Flash memory A-1

temp sensor 2-14

L3 cache A-3

I
N
D
E
X

IN-2

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