Proceedings of LINAC 2004, Lübeck, Germany

CONTROL OF THE LOW LEVEL RF SYSTEM FOR THE J-PARC LINAC
S. Anami#, E. Kadokura, S. Michizono, S. Yamaguchi, KEK, 1-1 Oho, Tsukuba, Ibaraki, 3050801,Japan; E. Chishiro, T. Kobayashi, H. Suzuki, JAERI, 2-4 Shirakata-Shirane, Tokai, Naka,Ibaraki, 319-1195, Japanand analog monitors and a klystron driver, are controlled
by a system controller with interfaces for local and remote
operation. We adopt a programmable logic controller(PLC) as the main system controller.

Abstract
The J-PARC 181-Mev proton linac requires twentyfour RF systems, which operate at a 620-µs pulse width,
50-Hz repetition rate, and 324-MHz frequency. The
required basic functions of the low level RF (LLRF)
control system for the klystron RF source are: fieldcontrol, high-power protection, analog and status monitor
and klystron drive. To perform these functions a
programmable logic controller (PLC) is used as the main
system controller. The PLC will be locally operated by atouch panel on PLC LAN and remotely by an EPICS
Operator Interface (OPI) on EPICS LAN. This paper
describes the LLRF hardware configurations and thesystem control using the PLC.

OVERVIEW OF THE LLRF SYSTEM
There are twenty-four LLRF systems corresponding toeach of the solid-state and klystron amplifier stations. Ablock diagram of the LLRF system for the klystron station,
including an interface with the EPICS control system(VME/IOC and NIM/Timing), is shown in Figure 1. The
required fundamental functions for the LLRF system are:1) generation of the accelerating RF (324 MHz) and clock(12 MHz, 48 MHz and 312 MHz) signals phase-lockedwith a 12-MHz optical signal provided with the rf
reference distribution system [3], 2) cavity field andtuning control (cPCI/Digital FB), 3) high-powerprotection and RF monitor (Fast Interlock, Arc Detectorand VSWR Meter), and 4) klystron drive (Analog FB, 20dB and 40-W amplifiers).
The signal generation and the cavity field and tuning
control are performed by a cPCI crate system, which iscomposed of a host CPU module, a control input/output
module (CTRL I/O), a mixer and I/Q modulator module(MIX&I/Q-M), a DSP module attached with a FPGA
mezzanine card, and an RF and clock generator module(RF&CLK). All of the LLRF hardware components
which are listed in Table 1 are installed in two 19”

INTRODUCTION
The RF source of the J-PARC 181-MeV proton Linac
is composed of four solid-state amplifiers and twenty
klystron amplifiers. In each RF source, the cavity field
will be stabilized within an accuracy of ± 1% in amplitudeand ± 1° in phase. This field control, which is
implemented by a combination of feedback (FB) andfeed-forward (FF) algorithms, is the most important key
function in the low level RF (LLRF) system, and requires
much of our efforts [1][2]. However, seeing from theviewpoint to control the whole LLRF system, the field
control is one embedded system, all of the LLRF
components, such as a high power protection unit, status
EPICS LAN
PLC LANFA-Link
EPICS CTRL System
Timing Signals

VME/IOC

12 MHz CLKNIM/TimingEthernet × 2
FA-Bus × 1
FA-Link × 1
PC Link × 1 (2CH)
RS-232C × 2
D/I × 1, D/O × 1
ADC × 1LLRF PLC
Yokogawa
FA-M3 F3SP53

12-bits 8-CH

PC Link

RS-232C

D/O

cPCI/Digital-FB

O/E
RF &CLKJ5324 MHz

12MHz

DSP
I/Q M
DAC
FPGAADCcPCI
DSP

Analog FB

A

20 dB

40 W

I/Q M

AA

PID

CTRL from PLC

BUS(FB ON/OFF, PID Param.)+Tank1 & 2 Vc
Tank1 & 2 Pf
324 MHz Ref____________________________________________

Arc
Detector
VSWRMeter• Kly Pf, Pr• Tank1 Pf, Pr• Tank2 Pf, Pr• Tank1 Vc, Tank2 Vc

FastInterlock

Trombone Phase Shifter

I/Q

-I/Q

Klystron
Arc

Tank1

Tank1Pf Pr

Circulator

KlyPf PrTo Beam Monitor

Figure 1: Block diagram of LLRF System.

1TunerPLC

ArcTuner

MTuner

M

Tank1
Vc

Arc

3dB

Tank2

Arc

Kly Pf#anami@post.kek.jp

Tank
PLC

M Driver• Kly Arc• Circ Arc• Tank1 Arc• Tank2 Arc

12-bits 8-CH

20 dB
Pulse M

Kly-PS
PLC

Touch
Panel

D/I

D I/O
Pulse Gate

12 MHz
312 MHzFA-BusSet Param

CPU
I/O

FA-Link

PPS, etc.
Tuning

PLC Bus Ext.
To Next LLRF

FA-Bus

Tank2
Pf Pr

Tank2
Vc

Proceedings of LINAC 2004, Lübeck, Germany

standard racks (1400W × 800D × 2000H).
Table 1: LLRF hardware components and their unit size
Chassis Unit

7cPCI Crate

8VSWR Meter
40-W Amp.
40-W Output Unit
Tromb. Phase Shifter
Temp. Module Panel
I/O Connector Panels
1-GHz Oscilloscope
OthersOperation
Setting
Monitor

Height(unit)

PLC and Touch Panel

NIM Bins

PLC

5×2
34Touch Panel mounted on PLC
chassis front panel
covered with noise-shield casewith fansPulse Mod, 3-CH 20-dB Amp,
Fast INT, Arc Detect., Analog
FB CTRL, Osc. Trig Delay

I/O Module
Remote CTRLVME/IOCLocal CTRLTouch Panel

Ethernet × 2D/I

Interlock/In

Fast Interlock
PPS
Other Hardware

Status/In

FA-Link
D/Iwith peak power meter function

include dc power supply
monitor couplers, circulator,
2coaxial SWside panel motor driven (20 cm × 80 cm)
rear panel 4 thermocouple modules
main purpose for ground sink
3×2
7waveform and phase read-out
10
2 fan units, MCCB

SerialData/In
ADC

L
DSL
L
L
DSS

A

Control/Out
ON/OFF
Setting

CONTROL COMPONETS OF THE LLRF
SYSTEM

D/O

D

SerialDDS

The components for controlling the LLRF system, as
shown in Figure 1, are the PLC, Touch Panel, EPICS
Control System, cPCI System, and Fast Interlock. The
hardware configuration and control function for each ofthese components are described as follows:

cPCI/CTRL I/OSA

FA-Link

Kyl-PS PLC
Tank PLC
Tuner PLC

cPCI/CPUVSWR Meter
Water Temp
Tank Vacuum
Pulse Mod
Kly Input S/W
Analog PID
Trombone

Figure 2: Control flow from/to the PLC.

Touch Panel
The Touch Panel (TP) provides a GUI for local
operation and all the functions necessary to control theentire LLRF system. In addition important data such as
the field amplitude and phase, the cavity tuning angle andvacuum, and the klystron output power are displayed in
the trend graph.

PLC
Though it isn't shown in Figure 1, there are two typesof PLCs: a main unit which has a CPU module in its backplane bus, and a subunit which doesn't have a CPU and isconnected on the expansion bus of the main unit by anFA-Link module. The main unit is one rate in foursystems, thus, one CPU works four system tasks. Figure 1
shows the case that PLC is a main unit. Differences
between the subunit and the main unit are two points: thesubunit has no connection to LANs and no link with otherPLCs. All others are similar system configurations. Thefollowings are explained about the system whose PLC is amain unit, as well as the paragraph mentioned above.
The modules used in the PLC are shown in Figure 1.
Control functions of the PLC can be depicted in Figure 2.
In order to operate the system and provide remote andlocal access to the PLC, there are the EPICS VME/IOC
and the Touch Panel (TP). Two types of modules forserial (RS-232C) communication are used: one is a 2channel PC-Link module which is implemented by aclient program for communication with the cPCI/CPUmodule and the cPCI/DSP module routed through thecPCI/CTRL I/O module, and the other is Ladder Program
Communication modules which are implemented by PLC
ladder programs for communication with the VSWR
Meter and the Trombone Phase Shifter. As a control
output from the PLC, ON/OFF commands are transmitted
to the cPCI/FPGA through the cPCI/CTRL I/O, Pulse
Modulator, Klystron Input SW, and Analog PID. In
addition parameter settings are transmitted to the Tuner
PLC, cPCI/CPU, Analog PID, and Trombone Phase Sifter.

EPICS VME/IOC
The EPICS VME/IOC is an I/O interface with EPICS
which is supported by the linac control group. The PLC isremotely controlled by reading and writing from EPICS
to the PLC register. The required timing signals for theLLRF system are provided by the EPICS NIM Timingsystem. In addition the high-refresh-rate dada from theVSWR Meter (8-CH 12-bit, 50 Hz) are saved in to theEPICS database.

cPCI System
The cPCI system composed of five modules and one
mezzanine board (FPGA) is shown in Figure 3. In thesemodules only the CPU and DSP modules utilize the PCIsystem bus (J1 and J2), while the other modules utilize
only the user bus (F3 and J5) and, thus, merely make useof its standard module case. The boards (CPU, DSP,FPGA and CTL I/O) relevant to control are explained asfollows:
A CPU module used as a cPCI system host is a general
purpose Pentium CPU board (ACP-128-1, AVALDATA
Co., PentiumM/1.6GHz). On the front panel the PC
standard communication and device I/O ports, such as
Ethernet (×2), COM, keyboard, display and etc., areprovided, which make it easy to locally debug anddiagnose the software and system. The COM port is used
for the communication of all the control data required for2

Proceedings of LINAC 2004, Lübeck, Germany

Ethernet 1
Ethernet 2COM 1
Display/Key-Board/Mouse

CPU ACP-128-1

PentiumM/1.6GHz
Slot 1
J1

J2

the PLC and J5 bus are RF ON/OFF, FB ON/OFF, fault
latch Reset, host CPU Reset, FPGA OK, DSP OK, etc.
The timing signals are FPGA pulse control Start/Stop, RFON Gate, Beam ON Gate, Beam Chopper Clock (~1MHz), etc.

EPICS LAN
PLC LANPLC PC Link 2

J5CPU ResetControlTrig/GateSerialCTRL I/O

Slot 2J1J2J3J5J3J5

PLC D/I, D/O
NIM/Timing
PLC PC Link 1

Fast Interlock
In order to protect the high-power components such as
RF windows in case of RF discharge and over RF
reflection, we must shut off the RF drive to the klystronas soon as possible. The Fast Interlock (Fast INT) module
provides the high-power protection function bycontrolling a gate signal to the RF switch of the Pulse
Mod module. The Fast INT module has many input
signals, as shown in Figure 4: four arc detection signals
from the Arc Detector (klystron, circulator, tank-1 input
port and tank-2 input port), three set signals of an overforward power (Pf), over reflection power (Pr) andVSWR (5-µs delay for processing) from the VSWR
Meter, and the RF Out Enable signal from the machine
protection system (MPS).
The Fast INT module also has an output function of the“RF Acc OK” signal which informs the RF source readyfor beam acceleration to the MPS.

DSP Barcelona
DSP1 DSP2
PEM

PEM

DSP3

DSP4PEM

PEM

FPGA1
ADC1

ADC2

DAC1JN4FPGA2ADC3DAC3DAC2ADC4DAC4Slot 3J5

MIX & I/Q M

324 MHz

I/Q M

Tank 1 Vc
Tank 2 Vc
Tank 1 Pf
Tank 2 Pf

I/Q M

324 MHz RFOutput

Slot 4J5RF & CLK
324 MHz
312 MHz48 MHz CLKSlot 5O/E
12 MHz48 MHz
312 MHz324 MHz

12 MHz CLK
12 MHz CLK
48 MHz CLK
312 MHz CLK
324 MHz RF

Figure 3: Block diagram of the cPCI modules.
Fast Interlock

the field control from/to the PLC. One Ethernet port is forthe transmission of waveform data to the EPICS OPI as aFTP server. Another Ethernet port is connected to PLC
LAN and served the network boot and the download ofDSP execute and FPGA configuration files.
We adopt a Barcelona DSP board (Spectrum Signal
Processing Inc., TMS320C6701 × 4). Each of the DSPs
has an I/O port called “PEM” on the board which
provides a high-speed dataflow (400 MB/s) from/to amezzanine board inserted into the PEM connectors. Thewaveform data from the mezzanine (FPGA) board can be
stored directly in lots of memories (512-kB SSRAM, 16MB SDRAM) on each DSP local bus by a DMA engine,and, after processed by DPSs, transferred to the hostmemory on the PCI memory address space.
Besides J1 and J2 this DSP board has the J3 and J5 user
bus connectors: J3 is for DSP global interrupts and serial
communication, and J5 for user free I/O lines, whichroute a path to a 64-pin connector (JN4) on the board. We
use JN4 as a signal path from the CTRL I/O to FPGAboards.
The FPGA board installed on the DSP board as its
mezzanine board consists of two FPGAs (Xilinx Virtex-E
XCV600E (FG676)), four ADCs (AD6644) and fourDACs (AD9764). By equipping the FPGA board with all
the PEM and JN4 ports, we obtain the expansible
usability. The configuration PROMs on the board can berewritten through the DSP serial port in the PEM ports, aswell as the JTAG port, therefore we can download FPGA
configuration files sent from the PC server on PLC LAN.
The Control I/O (CTRL I/O) board provides the signal
paths from the PLC and NIM/Timing to the J3 and J5
cPCI user bus connectors. The digital I/O signals between

Reset

Arc 4 CH (kly, Circ, tank-1, tank-2)

From PLC D/OTo PLC D/I
RF ON from PLC

Kly Pf, Pr, VSWR

RF SW Gate
To Pulse Mod

Tank-1 Pf, Pr, VSWR
Tank-2 Pf, Pr, VSWR
RF Out Enable (from MPS)

RF Acc OK for MPS
Fast INT
Tank-1 Vc (from VSWR)
RF Acc OK
To MPS

Tank-2 Vc (from VSWR)cPCI OK (from CTRL I/O)
PLC RF OK (from PLC D/O)

Figure 4: Block diagram of the Fast Interlock module.

CURRENT STATUS
Two prototypes of the LLRF system based on analog
feedback have been operated at the DTL-1 RF station andthe SDTL high-power test station in the 60-MeV test linac.
All twenty-four LLRF systems will be delivered at theend of March 2005. We are developing the PLC program
which includes the auto-recover process from fault down
and the auto-conditioning process for cavities.

REFERENCES[1] S. Michizono, et al, “Digital RF Control System for
400-MeV proton Linac of JAERI/KEK Joint
Project,” Linac 2002, Gyeongju, Korea, Aug. 2002.
[2] S. Michizono, et al, “Digital Feedback System for JPARC Linac RF Source,” this conference.
[3] T. Kobayashi, et al, “RF Reference Distribution
System for J-PARC Linac,” this conference.

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