Data sheet

RAA270000KFT(RAA270000KFT#BA2)

General purpose Power Management IC

R02DS0021EJ0100
Rev1.00
2020.1

Description
The RAA270000KFT is a general purpose Power Management IC (PMIC), and suitable for RENESAS’
microcontroller RH850 series. The features and detail information of the PMIC are described in thisdocument.
The PMIC contains two current mode DCDC converters, four low dropout linear regulators (LDO) and two
linear trackers. The switching frequency of DCDC is typical 2.1MHz.
In order to monitor internal status, monitor function is implemented. The input voltage, output of all
regulators, and internal analog voltage corresponding to temperature are monitored through ADC in
microcontroller. For testing ADC in microcontroller, reference voltage can be monitored as well.
Since this PMIC includes a power-up/down sequence controller, it allows user not to build externalsequence circuit.

Features• Input range: 6.0V to 18.5V to perform specified characteristics.
5.4V~: Power rails, 5V/3.3V/1.25V and trackers functional (Not detect low voltage)
3.9V~: Not issues reset.
• 2 switching regulators,
For point of load: 5.7V/1000mA
For MCU core: 1.25V/700mA• 4 linear regulators,
For MCU : 3.3V/10mA, 5.0V/300mA, 3.3V/160mA, 5.0V/60mA• 2 linear trackers,
150mA ability with short protection to battery• Automatic power sequence• Watchdog timer• Analog multiplexer• Interrupt request• Thermal shut down
• Reset generator• Exposed die pad, QFP package, 64pin 12mm x 12mm

Applications• Automotive applications• Industrial applications• Ideal power supply for RENESAS’ microcontroller, RH850 E1x and C1x series.

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RAA270000KFT data sheet

Table of Contents
1 Absolute Maximum Rating .............................................................................................. 4
1.1 Absolute maximum rating * .................................................................................... 4
2 Pin Configuration ............................................................................................................. 5
2.1 Pin configuration ....................................................................................................... 5
2.2 Pin list ....................................................................................................................... 6
3 Internal Block Diagram .................................................................................................... 9
4 PMIC Function ............................................................................................................... 11
4.1 Abstract of the PMIC............................................................................................... 11
4.1.1 PMIC operation ............................................................................................... 11
4.1.2 Pin setting ....................................................................................................... 12
4.1.3 Operating input voltage................................................................................... 13
4.1.4 Configuration register ..................................................................................... 13
4.1.5 Product code ................................................................................................... 14
4.1.6 Pin monitor ...................................................................................................... 14
4.2 Serial Interface........................................................................................................ 15
4.2.1 Signal format ................................................................................................... 15
4.2.2 Ensuring communication ................................................................................ 16
4.2.3 Secured request ............................................................................................. 16
4.2.4 Register........................................................................................................... 16
4.2.5 Register table .................................................................................................. 17
4.2.6 Electrical characteristics ................................................................................. 18
4.3 Reference Voltage .................................................................................................. 19
4.3.1 Electrical characteristics ................................................................................. 19
4.4 LDO......................................................................................................................... 20
4.4.1 Output protect function ................................................................................... 21
4.4.2 Electrical characteristics ................................................................................. 22
4.5 Tracker .................................................................................................................... 23
4.5.1 Register........................................................................................................... 23
4.5.2 Electrical characteristics ................................................................................. 23
4.6 DCDC...................................................................................................................... 25
4.6.1 Output protect function ................................................................................... 26
4.6.2 Register........................................................................................................... 28
4.6.3 Electrical characteristics ................................................................................. 28
4.7 Power Rail Sequence ............................................................................................. 29
4.7.1 Power up sequence ........................................................................................ 29
4.7.2 Power down sequence ................................................................................... 31
4.8 Watchdog (WD) Timer ............................................................................................ 34
4.8.1 Window WDT .................................................................................................. 34
4.8.2 WDT operation ................................................................................................ 34
4.8.3 Advanced mode .............................................................................................. 36
4.8.4 Register........................................................................................................... 39
4.8.5 Electrical characteristics ................................................................................. 41
4.9 Reset ....................................................................................................................... 42
4.9.1 Reset factor..................................................................................................... 42
4.9.2 Reset factor register ....................................................................................... 42
4.9.3 Software reset ................................................................................................. 44
4.9.4 External reset .................................................................................................. 44
4.9.5 Electrical characteristics ................................................................................. 44
4.10 Specified Output Pins .......................................................................................... 46
4.10.1 Register ...................................................................................................... 47
4.10.2 Electrical characteristics............................................................................. 48

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RAA270000KFT data sheet
4.11 Interrupt Signal .................................................................................................... 49
4.11.1 Interrupt control .......................................................................................... 49
4.11.2 Interrupt factor ............................................................................................ 49
4.11.3 Register ...................................................................................................... 50
4.12 Functional Safety ................................................................................................. 55
4.12.1 Voltage detection........................................................................................ 55
4.12.2 PMIC behavior after unusual detection ...................................................... 56
4.12.3 Self-diagnosis ............................................................................................. 56
4.12.4 Electrical characteristics............................................................................. 57
4.13 Temperature Sensor ............................................................................................ 59
4.13.1 Thermal shut down ..................................................................................... 59
4.13.2 Register ...................................................................................................... 59
4.14 Monitoring Function ............................................................................................. 61
4.14.1 Monitoring internal analog voltage ............................................................. 61
4.14.2 Monitoring digital output ............................................................................. 61
4.14.3 Register ...................................................................................................... 62
4.14.4 Electrical characteristics............................................................................. 63
5 Application Diagram ...................................................................................................... 64
5.1 Layout guide lines ................................................................................................... 65
6 Electrical Characteristics ............................................................................................... 66
6.1 Recommended operating condition ........................................................................ 66
6.2 Electrical characteristics ......................................................................................... 66
6.2.1 DC characteristics........................................................................................... 66
7 Package Information...................................................................................................... 67

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RAA270000KFT data sheet

1 Absolute Maximum Rating
1.1 Absolute maximum rating *Items
VINR, VINPDC1A/B
VDDIO
VIN3V
VINP1/2, VINPTRQ1/2,
VINPDC2A/B
PGND1/2, AGND1/2
FBDC1, FBDC2A/B

Comment
Supply power for internal circuits
Supply power for internal circuits

All ground pins
Feedback pins for DCDC

MIN
-0.3
-0.3
-0.3

MAX
26 ***
6.0
4.0

Unit
V
V
V

-0.3

19

V

-0.3
-0.3

V
V

Analog output pin

-0.3

0.3
19
VINPDC1A/B+0.3
VINPDC2A/B+0.3
6.0
VINR+0.3
VINR+0.3
VINP1+0.3
VINP2+0.3
VIN3V+0.3
VINPTRQ1+0.3
VINPTRQ2+0.3
VADC+0.3

Digital input pins

-0.3

VDDIO+0.3

V

Digital output pins

-0.3

VDDIO+0.3

VJunction to ambient
Junction to case (Top)
Junction to case (Bottom)

19.4 ****
17.3 ****
0.98 ****
-40
150
-55
150

LX1A/B-1.0 **

LX2A/B-1.0 **

TREF1/2
EN0/1, LDO0EN
VOUT0
VOUT1, VADC
VOUT2
VOUT0SW, BUFAD

Input pins for trackers

-0.3
-0.3
-0.3
-0.3
-0.3
-0.3

VTRQ1

-0.3

VTRQ2

-0.3

MUXOUTERROR1/2, WDI, WDENB,SPISDI,SPICLK, SPICSBSPISDO, RSTB, INTOUT, SUSPFSOUT, EXCNT
Thermal resistance (Typical)
Junction Temperature *****
Storage Temperature Range

V
V
V
V
V
V
V
V
V
V
V

°C/W
°C
°C

*: Stress beyond those listed under Absolute Maximum Rating may cause permanent damage to thedevice. Exposure to any Absolute Maximum Rating condition for extended periods may affect device
reliability and lifetime.
**: Not allowed to apply continuous voltage.
***: Maximum voltage is 40V under load dump condition. (Duration time is 400ms.)****: Simulation value based on JEDEC-2S2P condition.
*****: The PMIC includes over temperature protection that is intended to protect the device during momentary
over load condition. Junction temperature will exceed the maximum operating junction temperaturewhen over temperature is achieved. Continuous operating above specified maximum operating junction
temperature may impair device reliability.

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RAA270000KFT data sheet

2 Pin Configuration
2.1 Pin configuration

BUFAD
TREF2
VTRQ2
VINPTRQ2
N.C
VINPTRQ1
VTRQ1
TREF1
AGND1
VADC
VINP1
N.C
VOUT1
VOUT2
N.C
VINP2

Pin configuration is shown in below figure. The package is 64pin exposed die pad QFP.

33

48

MUXOUTN.C
SPISDOSPICLKSPISDISPICSB
VDDIO
AGND2
FSOUT
EXCNT
N.C
VOUT0SW
VIN3V
N.C
VOUT0
N.C

49

32

64

17
16

TEST1
EN0
TEST2
LDO0EN
EN1
VINR
N.C
N.C
VINPDC1A
VINPDC1B
N.C
LX1A
LX1B
PGND1
FBDC1
ERROR11SUSP
INTOUT
RSTB
WDENB
WDI
N.C
FBDC2BFBDC2A
PGND2
LX2B
LX2A
N.C
VINPDC2B
VINPDC2A
N.C
ERROR2

Fig. 2 Pin configuration (Top view)

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R02DS0021EJ0100 Rev.1.00
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VINPDC1A

VINPDC1B

N.C

LX1A

LX1B

PGND1

FBDC1

ERROR1

9

10

11

12

13

14

15

16

VINPDC2B

N.C

8

20

N.C

7

VINPDC2A

VINR

6

19

EN1

5

N.C

LDO0EN

4

18

TEST2

3

ERROR2

EN0

2

17

TEST1

PIN name

1

PIN #

-

Not connected.

-

Not connected.

Power supply for DCDC2.

Power supply for DCDC2.

DigitalDigitalInput for monitor signal of microcontroller.

Input for monitor signal of microcontroller.

Analog-

DCDC1 Feedback from VD1.

Ground.

Analog-Power supply for DCDC1.

DCDC1 Inductor driver output.

-

Power supply for DCDC1.

Analog-Not connected.

DCDC1 Inductor driver output.

-

Not connected.

DigitalPower enable of the PMIC.
(High : Enable the PMIC, Low : Disable the PMIC)-

DigitalPower enable of LDO0 without EN0 or EN1.
(High : Enable LDO0, Low : Disable LDO0)

Power supply for LDO0.

-

Digital-Note: AGND1/2 and PGND1/2 are connected in the PMIC.

page 6 of 68

Power

Power

-

Input

Input

Input

GroundOutputOutput

-

Power

Power

-

-

Power

Input

Input

-

Input

-

Analog or I/O/P/G
DigitalFor test. It should be connected to ground.

Power enable of the PMIC.
(High : Enable the PMIC, Low : Disable the PMIC)

For test. It should be connected to ground.

Pin function

-

-

-

CMOS

CMOS

-

-

-

-

-

-

-

-

-

-

NMOS

NMOS

-

NMOS

-

Interface
level

-

-

-

VDDIO

VDDIO

-

-

-

-

-

-

-

-

-

-

VINR

VINR

VIN3V

VINR

VIN3V

PGND1/2

PGND1/2-

AGND1/2

AGND1/2

AGND1/2-

PGND1/2

PGND1/2-

PGND1/2

PGND1/2--

PGND1/2

AGND1/2

AGND1/2

AGND1/2

AGND1/2

AGND1/2

GND name

Protect circuit to
VDD name

Should be open.

Included pull-down resister.

Included pull-down resister.

Should be open.

Should be open.

Should be open.

Included pull-down resister.

Included pull-down resister.

Should be connected to GND.

Included pull-down resister.

Should be connected to GND.

Remarks

RAA270000KFT data sheet

2.2 Pin list
The pin list table is shown below.

R02DS0021EJ0100 Rev.1.00
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WDENB

RSTB

INTOUT

SUSP

VINP2

N.C

VOUT2

VOUT1

N.C

VINP1

29

30

31

32

33

34

35

36

37

38

VTRQ1

WDI

28

42

N.C

27

TREF1

FBDC2B

26

41

FBDC2A

25

AGND1

PGND2

24

40

LX2B

23

VADC

LX2A

22

39

N.C

PIN name

21

PIN #

-

Not connected.

Power supply for LDO1.

AnalogAnalogTRACK1 output.

-

Input reference for TRACK1.

Ground.

AnalogAnalogLDO1 output.

LDOAD output.

AnalogLDO2 output.

DigitalLow voltage indicator of LDO1.

-DigitalInterrupt signal output.

Not connected.

DigitalReset output.

-

DigitalWatch dog enable.

Power supply for LDO2.

DigitalClear watch dog timer.

-

Analog

DCDC2 Feedback from VD2.

Not connected.

Analog

DCDC2 Feedback from VD2.

-

Analog

DCDC2 Inductor driver output.

Ground.

Analog

-

CMOS

CMOS

-

-

-

-

-

-

-

Interfacelevel

Note: AGND1/2 and PGND1/2 are connected in the PMIC.

page 7 of 68

OutputInput

GroundOutputPower-

OutputOutput-Power

OutputOutput

-

-

-

-

-

-

-

-

-

-

CMOS

CMOS

Output Open drain

Input

Input

-

Input

Input

GroundOutputOutput-Analog or I/O/P/G
Digital

DCDC2 Inductor driver output.

Not connected.

Pin function

-

-

-

VINP1

-

-

VINP1

VINP2

-

-

VDDIO

VDDIO

VDDIO

VDDIO

VDDIO

-

-

-

-

-

-

-

AGND1/2

AGND1/2-

AGND1/2

AGND1/2-

AGND1/2

AGND1/2-

AGND1/2

AGND1/2

AGND1/2

AGND1/2

AGND1/2

AGND1/2-

AGND1/2

AGND1/2-

PGND1/2

PGND1/2-

GND name

Protect circuit to
VDD name

Should be open.

Should be open.

Included pull-down resister.

Included pull-down resister.

Should be open.

Should be open.

Remarks

RAA270000KFT data sheet

Pin list (Continued)

R02DS0021EJ0100 Rev.1.00
2020.1N.C

SPISDOSPICLKSPISDISPICSB

VDDIO

AGND2

FSOUT

EXCNT

N.C

VOUT0SW

50

51

52

53

54

55

56

57

58

59

60

N.C

MUXOUT

49

64

BUFAD

48

VOUT0

TREF2

47

63

VTRQ2

46

N.C

VINPTRQ2

45

62

N.C

44

VIN3V

VINPTRQ1

43

61

PIN name

PIN #AnalogAnalog multiplexer output.

DigitalDigital-Serial interface data input.

Serial interface chip select input.

Power supply for I/O of the PMIC.

Analog-Not connected.

LDO0 output.

Not connected.

AnalogPower supply for internal circuit.

LDO0 output through internal switch.

-

DigitalSpecified digital output.

Not connected.

DigitalSpecified digital output.

-

DigitalSerial interface clock input.

Ground.

DigitalSerial interface data output.

-

AnalogVoltage reference output.

Not connected.

AnalogInput reference for TRACK2.

-Power supply for TRACK2.
Analog-Not connected.

TRACK2 output.

-

Note: AGND1/2 and PGND1/2 are connected in the PMIC.

page 8 of 68-

Output-Power

Output-OutputOutputGround

Power

Input

Input

Input

Output-OutputOutputInput

Output

Power

-

Power

Analog or I/O/P/G
DigitalPower supply for TRACK1.

Pin function

-

-

-

-

-

-

CMOS

CMOS

-

-

CMOS

CMOS

CMOS

CMOS

-

-

-

-

-

-

-

-

Interface
level

-

VINR

-

-

-

-

VDDIO

VDDIO

-

-

VDDIO

VDDIO

VDDIO

VDDIO

-

VADC

-

-

-

-

-

-

AGND1/2

AGND1/2-

AGND1/2

AGND1/2-

AGND1/2

AGND1/2-

AGND1/2

AGND1/2

AGND1/2

AGND1/2

AGND1/2-

AGND1/2

AGND1/2

AGND1/2

AGND1/2

AGND1/2-

AGND1/2

GND name

Protect circuit to
VDD name

Should be open.

Should be open.

Should be open.

Included pull-up resister.

Included pull-down resister.

Included pull-down resister.

Should be open.

Should be open.

Remarks

RAA270000KFT data sheet

Pin list (Continued)

RAA270000KFT data sheet

3 Internal Block Diagram
The PMIC block diagram is shown in below figure.

BUFAD
VINR
VINPDC1A/B
BGR

VREF

DCDC1
LX1A/B
FBDC1
VINP1

VOUT0

LDO0

VIN3V

LDO1

VOUT1

LDOAD

VADC

Internal
power

VOUT0SW
VINP2SPICSBSPICLKSPISDISPISDOSPI I/F

WDENB
WDI

WDT

LDO2

VOUT2
VINPDC2A/B

DCDC2

LX2A/BFBDC2A/B

RSTB

VINPTRQ1

Sequencer
TRACK1LDO0EN
EN0
EN1
SUSP
FSOUT
ERROR1ERROR2EXCNTINTOUT

OSC

VTRQ1
TREF1
VINPTRQ2

Operation
control

ThermalShut-down

TRACK2

VTRQ2
TREF2

Analog multiplexer
Interrupt control

Power supply for I/Os

MUXOUT
VDDIO

Fig. 3 The PMIC block diagram

The abstractive descriptions are here. Please refer to each section for more detail.
◆ LDO0
LDO0 is a low drop output regulator. It generates 3.3V power. The output current ability is 10mA.
◆ LDO1
LDO1 is a low drop output regulator. It generates 5.0V power. The output current ability is 300mA.
◆ LDO2
LDO2 is a low drop output regulator. It generates 3.3V power. The output current ability is 160mA.

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RAA270000KFT data sheet◆ LDOADLDOAD is a low drop output regulator. It generates 5.0V power. The output current ability is 60mA.
◆ TRACK1TRACK1 is a voltage tracker. The output tracks input voltage applied on TREF1. The current ability is
150mA.
◆ TRACK2TRACK2 is a voltage tracker. The output tracks input voltage applied on TREF2. The current ability is
150mA◆ DCDC1
DCDC1 is a switching regulator. It generates 5.7V power. The output current ability is 1000mA.
◆ DCDC2
DCDC2 is a switching regulator. It generates 1.25V power. The output current ability is 700mA.
◆ Band gap reference (BGR)
BGRs generate reference voltage for the regulators.
◆ VREF
VREF generates necessary voltage for regulators. To reduce noise of LDO1 and LDOAD, an external
capacitor can be added.
◆ Analog multiplexer
An analog multiplexer outputs internal analog voltage of the PMIC.
◆ SPI interface
SPI receives requests from microcontroller. Or it also sends register setting.
◆ Watch dog timer (WDT)
WDT monitors system operating. WDT can be controlled by WDI pin or via SPI.
◆ Sequencer
It controls power up/down of the regulators.
◆ Operation control
It controls operation of the PMIC and external pins.
◆ Interrupt control
It controls interrupt operations.
◆ OSC
2.1MHz oscillator for sequencer and DCDC. No external part needed.
◆ Thermal shut-down
It monitors temperature on the die. If the temperature rises higher than designated value, it informs to
the sequencer.

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RAA270000KFT data sheet

4 PMIC Function
4.1 Abstract of the PMIC
In order to supply power to microcontroller or ASIC, the PMIC contains two current mode DCDC converters(DCDC) and four LDOs. The DCDC1’s output is supposed to be used for all LDOs’ and DCDC2’s powersources. When battery voltage is applied to the PMIC, the regulators rise up automatically in accordancewith designated sequence. And after all outputs of the regulators power up successfully, the “INTOUT” signal
is released.
The PMIC also has a watchdog timer (WDT). When timer in the WDT expires, a reset signal occurs. The
WDT is refreshed by a request via WDI pin or SPI.
When the junction temperature reaches over Tsd, a reset occurs and all regulators would be forced to
power down immediately.

4.1.1 PMIC operation
The principal operate transitions and conditions are illustrated in below state diagram.
EN0 or EN1 is enables operation of the PMIC. If EN0 and EN1 are set low, the PMIC enters “Stand-by”
state.
(EN0=1 or EN1=1
or LDO0EN=1)& VINR > Vrb

Power down
(EN0=0 & EN1=0& LDO0EN=0)or VINR < Vdb

Tj < Trls
EN0=0 & EN1=0

Stand-by
RSTB=L

EN0=0 & EN1=0
Tj < Trls

EN0=1 or EN1=1

Cool down

Self-diagnosis
EN0=1 or EN1=1

Tj < Tsd

Tj > TsdP/U sequence

Tj > TsdP/D sequence 2

Tj > Tsd

Reset 2

EN0=0 & EN1=0
Tj > TsdP/D sequence 1

Normal
RSTB=H
EN0=0 & EN1=0
or VOUT1 < Vd1l2

Reset 1

Fig.4 State diagram◆ Power down
In this state, no block in the PMIC operates.
◆ Stand-by
In this state, the PMIC executes initial reset of internal registers and RSTB pin is asserted low. Only
LDO0 operates in this state.
◆ Self-diagnosis
If EN0 or EN1 is set 1, self-diagnostic starts. In this state, over/under voltage detector in the regulatorsand the internal logic circuit are checked. If junction temperature is higher than Tsd, then it enters “Reset2”
state.
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RAA270000KFT data sheet◆ P/U sequence
After executing self-diagnostic, this state is automatically entered. Even if one of regulators doesn’t riseup, it stays in this state. After all regulators rise up and it passed 12ms, reset is released. WDENB is
detected in this state.
◆ Normal
After reset is released, this state is automatically entered. If WDENB is detected as low in this state,system monitor is started with using the WD function. If WDENB is detected as high, the WDT doesn’trun. And also the PMIC monitors junction temperature.
◆ Reset 1
RSTB asserts low by setting low both EN0 and EN1, or low voltage detection of VOUT1 immediately.
◆ P/D sequence 1
This state is automatically entered from “Reset 1” state. All regulators except LDO0 start to fall down indesignated order. Junction temperature is checked. If junction temperature is higher than Tsd, then it
enters “Cool down” state. If lower than Trls, it enters back “Stand-by” state.
◆ Reset 2
When Tj comes over Tsd, RSTB pin asserts low.
◆ P/D sequence 2This state is automatically entered from “Reset 2” state. All regulators except LDO0 start to fall down indesignated order.
◆ Cool down
The PMIC checks if junction temperature is lower than Trls. If junction temperature is higher than Tsd,the PMIC wait until junction temperature cools down. After junction temperature comes below Trls, itenters “Stand-by” state.

4.1.2 Pin setting
The PMIC has several pins to define PMIC operation. For proper operation, these pins should be set toappropriate level. Appropriate setting voltages are described in “6. Electrical Characteristics”◆ The PMIC enabling
User can control the PMIC by EN0 or EN1 pin. And it also makes only LDO0 power on by LDO0EN.
These pins can be connected to battery.

EN0
0
0
0
1
1

Table 4-1 Setting PMIC operation
EN1
LDO0ENPMIC operation
0
0
Disenable
01
Only LDO0 operates
1*
The PMIC operates
0*
The PMIC operates
1*
The PMIC operates*: Don’t care

Note: If EN0 or EN1 is asserted high after LDO0EN=1, please keep VINR > Vrb.
In the condition of VINR < Vrb, the state is shifted to power down.
◆ WDT enabling
User can stop WDT operation by setting WDENB pin. When WDENB is set to disenable, the WDT stops
operation. Below setting is defined at before start of P/U sequence.
Table 4-2 Setting WDT operation
WDENB
WDT operation
0
Enable1
Disenable

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RAA270000KFT data sheet
4.1.3 Operating input voltage
The PMIC operates different mode in accordance with its input voltage. The PMIC operation in input
voltage range is shown in below table.

Operation mode
Full operation
Partial operation
Lingering mode

Table 4-3 The PMIC operation mode
Function
All regulators operate normaly.
DCDC1 stops switching, but all LDOs, DCDC2 andtrackers operate normaly. (Not issue low voltage
detection.)
Not issue reset.

Input range
6.0V ~
5.4V ~
3.9V ~

4.1.4 Configuration register
In order to configure functional operation of the PMIC, it needs to set in this register. For more setting
information, please refer to each described section.
➢ Configuration register
This register is a secured register. It is necessary to enter “key” code, before entering this request.
(See “4.2.3 Secured request”.) Brief explanations of register contents are described in below of thetable following;◼ Address (CONF) : 10H
A5
A4
A3
A2
A1
A0
0
1
0
0
0
0
◼ Register
D7
D6
D5
D4
D3
D2
D1
D0
RSTBER WDTCNT DL2RSTB ADVWD CWRSTB◼ Setting contents
Setting
Register nameControl contents
1
0
RSTBER
D4
Reset assertion by ERROR1/2 inputOn
Off *WDTCNT
D3
Select WDT clear input channel
SPI
WDI *
DL2RSTB
D2
Reset by DETDC2L or DET2L
On
Off *
ADVWD
D1
Advanced mode for WD operating
EnableDisable *CWRSTB
D0
Reset by WD trigger in close window.
On
Off ** Default setting
Note1: This register is not initialized by RSTB.
Note2: Advanced mode for WD is effective when SPI is selected to refresh WDT.
RSTBER: The register can set to relate with ERROR1/2. After setting “On”, RSTB asserts low
when ERROR indicates error.
WDTCNT: Select WDT clear input. To clear WDT through SPI, it needs to set this bit.
DL2RSTB: The register can set to make reset when low voltage of DCDC2 or LDO2 is detected.
After setting “On”, reset is generated by low voltage of DCDC2 or LDO2.
ADVWD: The register can set to operate WDT in advanced mode. After setting “Enable”, WD
operates in advanced mode. Please refer to “4.8 Watchdog timer”.
CWRSTB: The register can set to make reset when a trigger occurs in close window.

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RAA270000KFT data sheet
4.1.5 Product code
In order to identify the PMIC, product code can be read from the PMIC.
➢ Product code
In order to identify the PMIC, each product has ID code. It can be read via SPI.
◼ Address (CHIPID) : 00H
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
◼ Register (Below bits are read only.)
D7
D6
D5
D4
1
0
1
1

D3
1

D2
1

D1
1

D0
1

4.1.6 Pin monitor
WDENB and ERROR1/2 are significant pins related to PMIC behavior. These pins are monitored in thisregister.
➢ Pin monitor register
This register is monitoring WDENB and ERROR1/2 pins.
◼ Address (PINMON) : 02H
A5
A4
A3
A2
A1
A0
0
0
0
0
1
0
◼ Register (Below bits are read only.)
D7
D6
D5
D4
D3
D2
PWDENB◼ Setting contents
Register name
Monitor pin
PWDENBD2
WDENB pin’s level
PERR2
D1
ERROR2 pin’s level
PERR1
D0
ERROR1 pin’s level

D1
PERR2

D0
PERR1

Bit
Contents0
Low level1High level
Note1: Above WDENB is identified at “P/U sequence” state.
Note2: The PMIC starts to monitor ERROR1/2 after reset is released and sampled every 100μs.

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RAA270000KFT data sheet

4.2 Serial Interface
In order to request to the PMIC, the PMIC includes serial to peripheral interface. (SPI)
User can set or request following things. For more detail contents, please refer to each section.
➢ WDT operation (If SPI control is selected.)➢ Control the monitor function➢ Interrupt control, read factor, write interrupt clear➢ TRACK1/2 power control➢ Change shutdown or warning temperature

4.2.1 Signal format
The bit length of the communication is 16bits, and signal format is illustrated in below figures.
The data should be transmitted as MSB first. For this SPI, one SPICSB active is for one request.
Therefore, it is necessary to make SPICSB rise up after transmitted data.

SPICSBSPICLKSPISDI

W

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

Do1

Do0

P

Invalid

SPISDO

Fig. 4-2-1 SPI format (Write)

SPICSBSPICLKSPISDIR

A5A4SPISDO

A3

A2

A1

A0

Invalid

Do7

Do6

Do5

Do4

Do3

Do2

P

Fig. 4-2-2 SPI format (Read)
Caution: In the PMIC, entered data is latched by rising edge of SPICSB.
Caution: SPISDO pin should be terminated with pull-up resister to VOUT1.
◆ W/R
This bit indicates write or read registers. To write register, bit W/R should be set 0. To read register, bit
W/R should be set 1. When user wants to read register, Do7-Do0 bits indicate contents. (D7-D0 bits are
ignored in the PMIC.)◆ A5-A0
The PMIC contains several registers. The addresses are described in these bits. Every registers canbe read to confirm its content.
◆ D7-D0
These bits describe control bits of the PMIC to write into the PMIC.
◆ Do7-Do0
These bits describe content bits or flag bits to read from the PMIC.

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RAA270000KFT data sheet◆P
This bit indicates parity bit. It is calculated based on the number of logic contained in bits except parity
bit itself.
SPISDO terminal stays Hi-Z during transmitting “W/R” bit and address bits, A5-A0. But parity bit ofread data is calculated with considering “W/R” bit and all address bits as 1. Therefore, pull-up resistershould be placed between SPISDO and VOUT1.
Bit P must be set 0 if the number of 1 is odd.
Bit P must be set 1 if the number of 1 is even.

4.2.2 Ensuring communication
To ensure the communication between the PMIC and microcontroller, the PMIC checks the SPI signal offollowing accesses. The PMIC counts how many times below access happen.
➢ Number of SPICLKThe PMIC counts SPICLK clocks while SPICSB is low. If the number of clock is not 16, it is considered
as a communication error. The PMIC ignores this command or request.
➢ Not related address
When unrelated address is transmitted, the PMIC ignores this address’ contents.
➢ Parity bit
The SPI format includes a parity bit. The PMIC checks the parity bit and if transmitted bits are notbased on the parity bit, it is considered as a communication error. The PMIC ignores this command orrequest.

4.2.3 Secured request
There are some registers which need to be careful when register’s content is changed. When it needs tochange following contents, microcontroller needs to request code as a “key” to the PMIC. And write below
address with a “key” code at once before changing contents. Without a “key” code, the request would be
ignored. To execute software reset, obtained “key” should be combined instead of sending protect code
address.
➢ Configuration register (Address : 10H)
➢ DCDC protect operation setting (Address : 1BH)
➢ Power control for TRACK1/2 (Address : 1AH)
➢ Window time setting for WD timer (Address : 17H)
➢ Interrupt mask register (Address : 0CH-0FH)➢ Reset mask register (Address : 14H)
➢ Temperature setting for thermal shut down (Address: 1EH)
➢ Software reset (Address: 1DH)

4.2.4 Register
The contents of SPI setting are described in this section.
➢ Protect remove code
◼ Address (PRTCT) : 11H
A5
A4
A3
A2
A1
A0
0
1
0
0
0
1
◼ Register
Before access secured register, need to obtain below random code by read mode.
Do7
Do6
Do5
Do4
Do3
Do2
Do1
Do0
RDMKEY(Do7:Do0)
It needs to enter the obtained data before microcontroller enters request.
D7
D6
D5
D4
D3
D2
D1
D0
RDMKEY(D7:D0)◼ Setting contents• RDMKEY(Do7:Do0) : Random code from the PMIC
• RDMKEY(D7:D0) : Copy RDMO(Do7:Do0)
Note：Read PRTCT register to get key and write it back to PRTCT register before modify those function
protect registers, instead of write the key to those function protect registers.
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RAA270000KFT data sheet
4.2.5 Register table
The registers which can be set in the PMIC are summarized in below table with its address and data.
Detail contents are described in each section.

Note: The initial value of PINMON is set with according to level of the pins.
The initial value of “PRTCT” register is unknown.
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RAA270000KFT data sheet
4.2.6 Electrical characteristics
Parameter
SPICLK delay
SPICLK periodHigh period of SPICLK
Low period of SPICLK
Rise time of SPICLK/SDI
Fall time of SPICLK/SDI
Command set-up
Data set-up
Data hold
Data access time
Read data Hi-Z timeHigh width of SPICSB

Symbol
tdck
tcyc
thigh
tlow
tr
tf
tcmsu
tsu
thd
tacc
thiz
twidthConditions
From SPICSB fall

MIN
400
800
320
320
400
100
100
2800

From last SPICLK rise
Before SPICLK rise
After SPCLK rise
From last address clock fall

TYP
-

MAX
10
10
50
50
-

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

tr

tf
SPICSB
tdck

tcyc

tcmsu

SPICLK
tlow

thd

tsu

SPISDI

Fig. 4-2-3 SPI write timing
twidthSPICSB
thigh

tf

tr

SPICLK
thiz

tacc

SPISDO

Fig. 4-2-4 SPI read timing

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RAA270000KFT data sheet

4.3 Reference Voltage
Below figure shows simplified reference voltage generator block.

BGR3
VREF1
(Reference voltage for DCDC1/2,
LDO2 )

Power control for internal
circuit. And it makes internal
reset.
DET0O

EN0
EN1
LDO0EN

Reference for LDO1, LDOAD
BUFAD
0.1μF

BGR2

BGR1
VREF0
(Reference voltage for LDO0)

Power control for LDO0

Fig 4-3 REF block diagram
There are three Band Gap Reference (BGR) circuits in the PMIC. In the upper figure, if BGR1 or BGR2
has damage, the PMIC would not power up. And if BGR3 suffers damage, all regulators except LDO0 would
not power up.
BUFAD is reference voltage for LDO1 and LDOAD. In order to apply “clear” supply for ADC in
microcontroller, 0.1μF capacitor is recommended to connect to ground.

4.3.1 Electrical characteristics
Below table shows characteristic of reference output.
C0=0.1μF (ESR=0~0.1Ω)Parameter
SymbolConditions
Output voltage
VBUF

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MIN
1.176

TYP
1.200

MAX
1.224

Unit
V

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RAA270000KFT data sheet

4.4 LDOThe PMIC includes four LDOs. Each LDO needs a ceramic capacitor on its output. This allows
improvement of output transient response. The gain stage of LDOs except LDO0 is operated with 3.3V
generated by LDO0. And each input of power stage is supposed to be connected to DCDC1’s output .All
LDOs have protection circuit with fold back characteristics.
◆ LDO0
Typically, the LDO0 output should be used as
power supply for internal circuit of the PMIC. The
typical output voltage is 3.3V.
It contains output voltage detector.
Especially, when over voltage is detected, thepower line switch for internal circuit of the PMIC
will be cut off supply power. Or when low voltage
is detected, it makes reset and initializes internalregister. The detect voltages are described in
section 4.12.4

VINR
VREF0
VOUT0
1μF
Protect
Trimming
DET0U
Detector

DET0O

GND
DET0L

Fig. 4-4-1 LDO0 block diagram◆ LDO1
Typically, the LDO1 output should be used as
power supply for I/O of microcontroller. The
typical output voltage is 5.0V.
It includes output voltage detector. If output
voltage comes across unexpected voltage, a flagis set into register and INTOUT asserts low.
Especially, when DET1L1 is detected, SUSP isasserted as warning. And when DET1L2 isdetected, RSTB is asserted. The detect voltages
are described in section 4.12.4.

VINP1
BUFAD
VOUT1
10μF
Protect

DET1U
DET1L1DET1L2Detector

Trimming
GND
SUSP

Fig. 4-4-2 LDO1 block diagram◆ LDO2
The LDO2 output is used as power supply foranalog part of microcontroller. The typical output
voltage is 3.3V.
It includes output voltage detectors. If output
voltage comes across unexpected voltage, a flagis set into register and INTOUT asserts low. The
detect voltages are described in section 4.12.4.
If over voltage is detected, it forces DCDC1 toenter protect mode. For more detail DCDC1’s
behavior, please refer to section 4.6.1.
Low voltage detection can be added to reset
condition by setting configuration register. When
low voltage is detected, reset occurs immediately.
Reset asserts low while VOUT2 is below low
voltage detection level. After VOUT2 comes up
usual output and 12ms passes, the reset isreleased.

VINP2
VREF1
VOUT2
10μF
Protect

DET2U
DET2L

Detector
Trimming

GND

Fig. 4-4-3 LDO2 block diagram

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RAA270000KFT data sheet◆ LDOAD
Typically, the LDOAD output is used as power
supply for ADC of microcontroller. The typical
output voltage is 5.0V.
It includes output voltage detectors. If output
voltage comes across unexpected voltage, a flagis set into register and INTOUT asserts low.
Actual detect voltage is described in section
4.12.4.

VINP1
BUFAD
VADC
1μF
Protect

DETADUDETADL

Detector
Trimming

GND

Fig. 4-4-4 LDOAD block diagram◆ VOUT0SW
VOUT0SW is a pin which applies voltage for retention area of microcontroller. The output voltage comesthrough internal switch. In order to prevent to apply unusual high voltage of LDO0, the switch is controlled
by over voltage detect of LDO0.
If output voltage comes down unexpected low voltage, a flag is set into register and INTOUT asserts
low. Actual detect voltage is described in section 4.12.4.
VOUT0

LDO0
DET0U

To power line ofInternal circuit

VIN3V

DELAY
To power terminal of
microcontroller (SYSVCC)

DET0SWL
VOUT0SW

Fig. 4-4-5 Internal switch of VOUT0SW

4.4.1 Output protect function
When something wrong like solder bridge happens, huge current flows to ground. This may cause heatissue. To prevent flowing over current from the output, all LDOs have a current limit function. Fold-backcharacteristic is illustrated in below figure.
In this figure, “Io” is a guaranteed current which maintains specified output voltage. For more than “Io”
current, the more output current flows, the lower output voltage goes down with decreasing output current.

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RAA270000KFT data sheet
Output voltage

Increasing current

Output current
Short current

Io

Fig. 4-4-6 Fold-back characteristic

4.4.2 Electrical characteristics
Characteristics noted under conditions GND=0V, unless otherwise noted. The condition is Tj=-40 to
150°C, unless otherwise specified.
◆ LDO0C0=1μF (ESR=0~0.1Ω)Parameter
Output voltage
Short current

SymbolVo0
Is0

Conditions
Io=0~10mA (DC)
Vo=0V

MIN
3.250
-

TYP
3.300
-

◆ LDO1C1=10μF (ESR=0~0.1Ω)Parameter

Symbol

Vo12
Vo13
Is1

Conditions
Io=0~150mA (DC)Io=150~300mA (DC)
VINP1=4.95V, Io=150mA (DC)
VINP1=3.5V, Io=150mA (DC)
Vo=0V

MIN
4.90
4.85 *
4.75
3.18
-

TYP
MAX
Unit
5.00
5.10
V
5.10
4.95
V
3.50
V
80
mA
* Guaranteed by design.

◆ LDO2C2=10μF (ESR=0~0.1Ω)Parameter
Output voltage
Short current

SymbolVo2
Is2

Conditions
Io=0~160mA (DC)
Vo=0V

MIN
3.234
-

TYP
3.300
-

MAX
3.366
80

Unit
V
mA

◆ LDOAD
CAD=1μF (ESR=0~0.1Ω)Parameter
Output voltage
Short current

SymbolVoA1
IsA

Conditions
5.0V setting, Io=0~60mA (DC)
Vo=0V

MIN
4.95
-

TYP
5.00
-

MAX
5.05
30

Unit
V
mA

Vo11
Output voltage
Short current

MAX
3.399
20

Unit
V
mA

Note: “(DC)” means it doesn’t include AC factor like transient response.

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RAA270000KFT data sheet

4.5 Tracker
The PMIC includes two trackers. Each tracker needs a ceramic capacitor on its output. And each input of
power stage is supposed to be connected to DCDC1’s output.
◆ TRACK1/2
TRACK1 and TRACK2 are auxiliary power rails.
The output voltage is set by input voltage. Powerup control is set via SPI. These trackers have highvoltage protect function to prevent reverse
current from the output. When outputs touch highvoltage like battery, this circuit stops reverse
current toward the PMIC.
The trackers have protect function as same as
LDO’s fold-back characteristic.

TREF1/2
VINPTRQ1/2

High voltage
Protect

VTRQ1/2
2.2μF

Protect

DETTRQ1/2U
DETTRQ1/2L

Detector

Fig. 4-5 Voltage tracker diagram

4.5.1 Register
The content of TRACK1/2 setting is only for power control.
➢ TRACK1/2 power control◼ Address (TRQCNT) : 1AH
A5
A4
A3
0
1
1
◼ Register
D7
D6
D5◼ Setting contents
Register name
VTRQ2CNT
VTRQ1CNT

D1
D0

A2
0

A1
1

A0
0

D4
--

D3
-

D2
-

Control contents
TRACK2 on/off
TRACK1 on/off

D1
VTRQ2CNT

D0
VTRQ1CNT

Setting
1
0
On
Off *
On
Off *
* Default setting

4.5.2 Electrical characteristics
Characteristics noted under conditions GND=0V, unless otherwise noted. The condition is Tj=-40 to 150°C,
unless otherwise specified.
◆ TRACK1
CTRQ1=2.2μF (ESR=0~0.1Ω)Parameter
SymbolConditions
Matching output errordVTR1
5V input, Io=150mA (DC)Short current
IsTR1
Vo=0V
Power on time *Trtrq1
5V input voltage, 90% output* Guaranteed by design.
Note: “(DC)” means it doesn’t include AC factor like transient response.

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MIN
-10
-

TYP
1.78

MAX
10
80
2.34

Unit
mV
mA
ms

page 23 of 68

RAA270000KFT data sheet◆ TRACK2
CTRQ2=2.2μF (ESR=0~0.1Ω)Parameter
SymbolConditions
Matching output errordVTR2
5V input, Io=150mA (DC)Short current
IsTR2
Vo=0V
Power on time *Trtrq2
5V input voltage, 90% output* Guaranteed by design.
Note: “(DC)” means it doesn’t include AC factor like transient response.

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MIN
-10
-

TYP
1.78

MAX
10
80
2.34

Unit
mV
mA
ms

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RAA270000KFT data sheet

4.6 DCDC
The PMIC includes two DCDCs. Internal high-side PMOS power stages are implemented in each DCDC
to reduce the PCB space. Each DCDC needs schottky diode, inductor and ceramic capacitor on its output
like the diagram. Analog processing circuit except power PMOS is operated with the 3.3V generated by
LDO0. Two DCDCs include output voltage detectors. The detectors monitor over voltage and lower voltage,and have output protect function and over current protection.
◆ DCDC1The DCDC1 operates with current mode control. And it is supposed to supply power as intermediate
power supply. This means all regulators’ power input should be connected to DCDC1’s output. (Except
LDO0) The DCDC1 includes output voltage detector. If output voltage comes across unexpected voltage,
the flag is set into register and INTOUT signal occurs. Actual detect voltage is described in section 4.12.4.
Hereafter, VD1 refers to as the output of DCDC1.

VREF1

Detector

DETDC1U

VINPDC1A/B

Over current

DETDC1L

FBDC1Error amp

VREF1

R

Σ

Q
D
R
V

S
SLOPE

4.7μH
VD1

LX1A/BPWM OSC
2.1MHz4.7μFX2

Trimming
GND

Fig.4-6-1 DCDC1 block diagram◆ DCDC2The DCDC2 also operates with current mode. The DCDC2 is supposed to supply power tomicrocontroller’s core circuit. The DCDC2 includes output voltage detector. If output voltage comes acrossunexpected voltage, the flag is set into register and INTOUT signal occurs as well. Actual detect voltage
is described in section 4.12.4.
Hereafter, VD2 refers to as the output of DCDC2.

VINPDC2A/B
VREF1

Detector

DETDC2U
DETDC2L

Over current

FBDC2A/B

VREF1

Error amp
R

Σ

S

Q
D
R
V

SLOPE

Trimming

PWM OSC
2.1MHz

4.7μH
LX2A/B

VD2

10μF

GND

Fig.4-6-2 DCDC2 block diagram

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RAA270000KFT data sheet
4.6.1 Output protect function
To operate the PMIC safety, interval operation would start in the case of output abnormal conditions.
Each DCDC operation is as follows.
◆ DCDC1When DCDC1 fall into unusual condition, DCDC1 enters to protect mode.
The protection circuit monitors output current and output voltage. In the case that over voltage is
detected on DCDC1, it would force to stop the DCDC1’s and DCDC2’s switching. When over current or
low voltage are detected with taking over detect mask time, then DCDC1 would enter interval operation.
The mask time of over current detection can be set via SPI. During protect mode, the DCDC1 tries toresume its operation regularly. The interval time of resuming can be set via SPI as well. When root causeof unusual condition is taken away, the DCDC1 comes to operate normally.
And when over voltage is detected in either DCDC2 or LDO2, DCDC1 would operate in protect mode
as well. Before DCDC1’s operation comes into protect mode, INTOUT asserts low.
The operation timing is shown in below figure. And detect mask times are described in next table.
Voltage drop due to LX1A/B switching off
VD2
Detect over voltage
Release voltage

VD1
Stop switching

Resume

LX1A/B
DetectOver voltage detect(Internal signal)

Clear interrupt

INTOUTFig.4-6-3 DCDC1 protect function behavior 1

NormalOutput condition

Over-current
or low voltage
or DCDC2 over voltage
or LDO2 over voltage

NormalDetectOver-current or low
voltage detect(DETDC1L)

Detect mask time

Normaloperation

VD1

Normaloperationinterval operation

LX1A/B
122μs

Clear interrupt
Interval time

INTOUTFig.4-6-4 DCDC1 protect function behavior 2Over current detect
Variable

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Table 4-6-1 Detect mask time
Low voltage detect
DCDC2 detect
92μs
92μs

page 26 of 68

RAA270000KFT data sheet◆ DCDC2
DCDC2’s protect operation is almost same as DCDC1’s.
The protection circuit monitors load current and output voltage. When over current or low voltage is
detected with taking over detect mask time, then DCDC2 would enter interval operation. The mask timeof over current detection can be set via SPI. During protect mode, the DCDC2 tries to resume its
operation regularly. The interval time of resuming can be also set via SPI. In the case of over voltage is
detected, it would force to stop switching of both DCDC1 and DCDC2. Before DCDC2’s operation comes
into protect mode, INTOUT asserts low.
The operation timing is shown in below figure. And detect mask times are described in below table.
Low voltage detection can be added to reset condition by setting configuration register.
When low voltage is detected, reset occurs immediately. Reset asserts low while VD2 is below low
voltage detection level. After VD2 comes up usual output and 12ms passes, the reset is released.

Output condition

Over current or low
voltage detect(DETDC2L)
VD2Over-current
or low voltage detect

NormalNormalDetectDetect mask time

Normaloperation

Normaloperationinterval operation

LX2A/B
122μs
Interval time

INTOUT
12ms

RSTB

Fig.4-6-5 DCDC2 protect function behavior 1(In case of DL2RSTB bit in CONF register is set “1”.)Voltage drop due to LX1A/B switching off
VD1
Detect voltage

Detect over voltage

Output voltage

Stop switching

Resume

LX2A/B
DetectOver voltage detect(Internal signal)

Clear interrupt

INTOUTFig.4-6-6 DCDC2 protection behavior 2

Table 4-6-2 Protect detect mask time
Over current detect
Low voltage detect
Variable
92μs

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RAA270000KFT data sheet
4.6.2 Register
The contents of protect function setting are described here.
➢ DCDC protection mode setting◼ Address (DCLIM) : 1BH
A5
A4
A3
A2
A1
A0
0
1
1
0
1
1
◼ Register
D7
D6
D5
D4
D3
D2
D1
D0
INTIME2(1:0)
DTIME2(1:0)
INTIME1(1:0)
DTIME1(1:0)◼ Setting contents
Interval time and over current detect mask time for DCDC2.
INTIME2(1:0)
DTIME2(1:0)
Interval time
Detect mask time
D7
D6
D5
D4
0
0
15.6ms00122μs *
01
31.2ms *
0
1
122μs
1
0
124.9ms
1
0
610μs
1
1
249.9ms
1
1
1098μs* Default setting
Interval time and over current detect mask time for DCDC1.
INTIME1(1:0)
DTIME1(1:0)
Interval time
Detect mask time
D3
D2
D1
D0
0
0
15.6ms00122μs *
01
31.2ms *
0
1
122μs
1
0
124.9ms
1
0
610μs
1
1
249.9ms
1
1
1098μs* Default setting
Note1: This register is not initialized by RSTB.

4.6.3 Electrical characteristics
Characteristics noted under conditions, GND=0V, unless otherwise noted. The condition is Tj=-40 to 150°C,
unless otherwise specified.
◆ DCDC1
Co=4.7μFx2 (ESR=0.0~0.1Ω), L=3.3/4.7μH
Parameter
SymbolConditions
MIN
TYP
MAX
Unit
Output voltage
VoDC1
Io=0~1000mA (DC)
5.40
5.70
6.00
V
OSC frequency
Fosc1
1890
2100
2310
kHz
◆ DCDC2
Co=10μF (ESR=0.0~0.1Ω), L=3.3/4.7μH
Parameter
SymbolConditions
MIN
TYP
MAX
Unit
Output voltage
VoDC2
Io=0~700mA (DC)
1.225
1.25
1.275
V
OSC frequency
Fosc2
1890
2100
2310
kHz
Note: “(DC)” means it doesn’t include AC factor like transient response.

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RAA270000KFT data sheet

4.7 Power Rail Sequence
When battery voltage is applied to the PMIC, the LDO0 rises up first. After the LDO0 rises up, the otherregulators are powered up in the sequence automatically. Therefore, user doesn’t need to consider power
rail sequence at all. After all regulators rise up, reset signal is released.

4.7.1 Power up sequence
After the PMIC is applied supply voltage, all regulators rise up automatically. Difference of rise up time
between regulators is suitable for RENESAS MCUs.
◆ Power up with using EN0 or EN1
While supply voltage is applied, the PMIC can be controlled by EN0 or EN1 pin. After EN0 or EN1 isentered, self-diagnosis execution starts first. The order of each regulator’s rising is controlled by internalsequencer. After all regulators rise up, interrupt signal is released. Further 12ms passes, reset signal isreleased as well. Each timing specification is specified in the below table and guaranteed by design.

Fig. 4-7-1 Power up timing (with EN0/1 setting)

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RAA270000KFT data sheet◆ Power up without using EN0 or EN1
When EN0 and/or EN1 are connected to supply voltage and supply voltage comes up, power up
sequence starts automatically. Power up sequence behavior is same as using EN0 or EN1. Each timing
specification is specified in the below table and guaranteed by design.

Fig. 4-7-2 Power up timing (Supply power coming up)◆ Power up after LDO0EN
While supply voltage is applied to the PMIC, only LDO0 can rise up with using LDO0EN control. The
PMIC executes self-diagnosis after either EN0 or EN1 rises. After either EN0 or EN1 set up, selfdiagnosis of detectors are executed and power-up sequence starts. Each timing specification is specified
in the below table and guaranteed by design.

Fig. 4-7-3 Power up timing (Supply power coming up)
Note: Please make EN0 or EN1 high in the condition of VINR > Vrb.
Otherwise, the state is shifted to power down.

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RAA270000KFT data sheet
4.7.2 Power down sequence
When the PMIC powers down, all regulators fall down automatically. Difference of fall down time between
regulators is suitable for RENESAS MCUs.
◆ Power down with using EN0 or EN1
When the PMIC is stopped operating by EN0 or EN1, interrupt and reset signal would be asserted.
After the PMIC sets RSTB to low, power down sequence starts automatically. If the system needs tomaintain VOUT0 output, LDO0EN should be set high before LDO0 power down. The time deviation in
below figure is +/-10%. That value is guaranteed by design.

EN0=0 and
EN1=0
Invalid

LDO0EN
VOUT0

1ms

VOUT0SW

1ms

VD1

1ms

VD2

50μs

VOUT1
100μs

VOUT2

50μs

VADC

1ms

INTOUT
100μs

RSTB

Fig. 4-7-4 Power down timing (with EN0/1 setting)

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RAA270000KFT data sheet◆ Power down without using EN0 or EN1
Output behavior in low supply voltage is shown in below figure. Even though the supply voltage of the
PMIC goes down lower than the output voltage, regulators can generate output voltage. But output
voltage becomes to be almost same as supply voltage.
When supply voltage falls down and LDO1 goes across Vd1l1, the PMIC asserts SUSP signal as awarning. Further the supply voltage falls down across Vdb, the PMIC asserts RSTB and all regulators
except LDO0 fall down.

VINR
VINPDC1A/B

Vdb

VOUT0
VOUT0SW

VD1

VD2
Vd1l1

VOUT1

VOUT2
VADC
INTOUT
RSTB

Fig. 4-7-5 Power down timing (Supply voltage falling down)

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RAA270000KFT data sheet◆ Power down except LDO0
LDO0 and output part of DCDC1 have terminal for supply voltage respectively. Below figure shows the
behavior of cutting off supply voltage for DCDC1. Since supply voltage maintains for the LDO0, the outputof LDO0 generates its output. On the other hand, supply voltage of DCDC1 is cut off, the outputs ofregulators which powered by DCDC1 fall down. Turn-off time of regulators is controlled by the sequencer.
The time deviation in below figure is +/-10%.That value is guaranteed by design.

VINR

VINPDC1A/B

VOUT0
1ms

VD1
1ms

VD2
Vd1l1

50μs
Vd1l2

VOUT1
100μs

VOUT2
50μs

VADC
INTOUT
RSTB

Fig. 4-7-6 Power down timing (VINPDC1A/B falling down)

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RAA270000KFT data sheet

4.8 Watchdog (WD) Timer
The watchdog (WD) timer can be used for monitoring the system health to prevent a runaway operation.
In order to refresh WD timer (WDT), a trigger via SPI or on WDI pin is needed.
Further, to improve functional safety, it can be done with logical operation to monitor microcontroller’s
operation. And also watchdog time can be set via SPI.
In order to operate WD, WDENB should be set low at “P/U sequence” state. Once WD starts its operation,
WDENB setting can’t stop WD function. WDENB setting in the PMIC can be set in any state except “Normal”
state.
◆ WDI pin or SPI control
There are two ways to start WD operating or refresh the timer. One way is to use WDI pin, and the otherone is to use SPI. It can select WDI pin or SPI by setting configuration register. To use WDI pin is default
setting.

4.8.1 Window WDT
Window WDT is implemented in the PMIC. It needs a trigger to start WD operation during first window(FW) in “Normal” state. If the trigger is not executed, a reset pulse occurs and the PMIC wait for a FW trigger
again. After WD starts operating in “System monitor” state, a trigger should not be executed during Close
Window (CW). If a trigger is executed, INTOUT would be asserted and enter Open Window (OW). A trigger
should be executed to refresh the timer during OW. If the refreshing is not executed within designated time,a reset pulse occurs. While WDT is operating and when SUSP is asserted, WDT would stop its operating.
And when SUSP is released, then WDT resumes from “Normal” state.
CW time and OW time are programmed via SPI.

4.8.2 WDT operation
Detail WD operation is described in this section. In order to clear the timer, toggling on WDI or SPI isneeded.
◆ Operation in normal
Below figure shows normal operation of WDT when the trigger from WDI pin or SPI is entered within
designated time. Certified point as a trigger is the changing point of WDI or rising edge of SPICSB.
Tcw

< Tfw

INTOUT
WDI

Request to start(FW trigger)< Tow

Certified point

Request to refresh

SPICSBSPISPICLK
Trigger(Internal)
RSTB

Fig.4-8-1 WDT normal operation◆ Behaviors in unusual operation
When the trigger is not executed and the timer expires, then a reset occurs.
(1) No trigger in FW
When the trigger is not entered in FW, reset would occur. After that, if the triggers aren’t entered, reset
occurs regularly.

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RAA270000KFT data sheet
INTOUT

Tfw

Tfw

Trigger(Internal)

No trigger happened
Twrstb

RSTB

Fig.4-8-2 No trigger in FW(2) A Trigger in CW
When the trigger is entered in CW, INTOUT would assert low.
< Tfw

< Tcw

< Tow
Clear interrupt

INTOUT
Trigger(Internal)

Miss trigger

RSTB

Fig.4-8-3 Trigger in CW 1
And when the configuration register is set to make reset, WD behavior is show in below figure.
< Tfw

< Tcw

< Tfw
Clear interrupt

INTOUT
Trigger(Internal)

Miss trigger

RSTB

Fig.4-8-4 Trigger in CW 2
(3) No trigger in OW
When the trigger is not entered in OW, the timer expires and reset would be asserted. After reset isreleased, WD starts from FW again and the PMIC maintains asserting low so that microcontroller isable to know that the reset is caused by timer expire.
< Tfw

Tcw

Tow

INTOUT
Request to start

Trigger
Twrstb

RSTB

Fig.4-8-5 No trigger in OW◆ Suspend WD operating
When the output voltage on VOUT1 comes down and SUSP asserts low, then WD stops its operation.
And SUSP changed to high, WD resumes operation form FW.

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RAA270000KFT data sheet
< Tfw

SUSP
Clear interrupt

INTOUT
TriggerFig.4-8-6 Suspend WD operating

4.8.3 Advanced mode
To use advanced mode, it needs to set configuration register, “SPI mode” and “Advanced mode”. Thisfunctionality is for using SPI. In this mode, it can monitor microcontroller’s and PMIC’s operation each other.
After WD operation starts, microcontroller needs to obtain a “question” to send an “answer” to the PMIC.
(QA monitoring) The “question” contains operand and objective data. The microcontroller should send arequest to refresh WD timer with data of the “answer”. The “answer” is in accordance with the operand in
the previous “question”. The PMIC refresh the WD timer and gives a point for the “answer”, and then it stores
and accumulates the points to evaluation register. When accumulated point reaches designated value, areset would happen.
If “Advanced mode” is not selected, only refreshing the WD timer is executed.
Note: In the advanced mode, CW rate to watchdog time is fixed 50%.

RSTB

Set “SPI mode”, “Advanced mode”.

SPICSBSPISDISPISDO

Add. Data

Add. Data

Add. (Read)

WD timer starts.

Evaluation
register

Data

Add. Data

Write an “answer”.

Add. (Read)

Add. Data

Data

Read a “question”.
Evaluate an “answer”.
Initial value is 0

Fig.4-8-7 QA monitoring operation◆ Procedure
Below figure illustrates procedure in accordance with Fig.4-8-5 and behavior scenario is described in
below.
• Select “SPI mode” and “Advanced mode”
In order to control WD via SPI and use advanced mode, it needs to set configuration register first.
In above example, D3 bit and D1 bit are set 1.
• Request to start
In order to start WD function, WD trigger address is needed to enter. The data accompanied with WD
trigger address is not defined, but parity bit is checked.
• Read “question”
The PMIC generates random data as a question containing 2bit operand and 6bit objective data.
Microcontroller must read the question to respond with an answer.
• Write “answer”
Microcontroller should enter an answer to the obtained data. The address data to enter an answer issame as a WD trigger address and refresh the WD timer simultaneously. The data contains 2bit operandand 6bit data operated along with the operand.

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RAA270000KFT data sheet
Data

Address

Set “SPI mode”,“Advanced mode”

Request to start

Read “question”

R/W A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1

D0 P

0

0

0

1

0

0

0

0

0

0

0

1

0

D0 P
0

0

1

0

1

1

0

0

0

0

0

0

0

0

0

R/W A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1

D0 P

1

0

1

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

0

0

1

0

0

1

0

D0 P

0

0

0

1

0

1

1

0

1

1

1

1

0

1

1

Refresh timer

0

R/W A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1

D0 P

1

0

1

0

1

1

0

0

0

0

0

0

0

0

0

1

1

0

1

1

0

0

1

0

0

R/W A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1

D0 P

0

1

0

1

0

1

1

0

1

0

WD start

Random data

R/W A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1“Question” data

Write “answer”

00Operand

Read “question”

1

R/W A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1“Question” data

Write “answer”

0

0

1

1

0

0

0

Refresh timer

Fig.4-8-8 Refresh procedure of advanced mode
◆ Evaluation register
The PMIC gives a point to the entered answer and has a register to accumulate the points. The
accumulated value is read via SPI. The value to occur reset can be set in a register. When the WD starts,
accumulated point is 0. Or evaluation is executed in OW.
• Right answer
When an answer is entered to the PMIC and it is expected, it gives “-1” point to evaluation register. If
accumulated value in evaluation register is 0, it maintains the value 0.
In below example, a right answer A1 is entered as a response of Q1. And then, “-1” is added to current
value of evaluation register.
Write right answer, A1

SPISDI

Add. (Read)

SPISDO

Q1

Add.

Write right answer, A2
A1

Add. (Read)

Add.

Read question, Q1

Read question, Q2
Q2

Add point -1

Add point -1

Evaluation
register

N

A2

N-1

N-2

Fig.4-8-9 Evaluation for entered answer (Right answer)

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RAA270000KFT data sheet• Wrong answer
When the answer is not expected answer, it gives “+2” point to evaluation register. And next questionis same as previous one.
In below example, a wrong answer Ax is entered as a response of Q1. And then, “+2” is added tocurrent value of evaluation register. In spite of wrong answer, the PMIC refreshes the WD timer.
Write wrong answer, Ax

SPISDI

Add. (Read)

SPISDO

Q1

Add.

Write right answer, A1
Ax

Add. (Read)

Add.

Read question, Q1

Read question, Q1
Q1

Add point -1

Add point +2

Evaluation
register

A1

N

N+2

N+1

Fig.4-8-10 Evaluation for entered answer (Wrong answer)• All answer bits are zero
When entered bits of the answer are all 0, the PMIC gives “+3” point to evaluation register. Of course,
the PMIC never create a question which leads the answer’s bits are all 0.
All answer bits 0

SPISDI

Add. (Read)

SPISDO

Q1

Write right answer, A1

Add.

Add. (Read)

Add.

Read question, Q1

Read question, Q1
Q1

Add point +3

Evaluation
registerA1

Add point -1
N+3

N

N+2

Fig.4-8-11 Evaluation for entered answer (All answer bits are zero)• Evaluation term
The answer is evaluated in OW. The answer in CW is ignored whether the answer is right or wrong.
And it makes INTOUT assert low.
Refresh timer

Write right answer, A1

SPISDI

Add. (Read)

SPISDO

Q1

CW
Add.

A1

Add. (Read)

Add.

A2

Read question, Q1
Q2

Add point -1

Evaluation
registerN

Not affect
N-1
Clear INTOUTINTOUTFig.4-8-12 Evaluation for entered answer (In appropriate term)

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RAA270000KFT data sheet• Reset by accumulated value
Through QA monitoring, when accumulated value is more than designated value, then reset occurs.
In below example, reset value of evaluation register is more than “N+1”. It assumes that the current
value of the evaluation register is “N”. When a wrong answer is entered, the value comes up to “N+2”.
Eventually, reset occurs after 4μs passes. Pulse width of the reset is 2ms.
Write wrong answer, Ax

SPISDI

Add. (Read)

SPISDO

Q1

Add.

Ax

Read question, Q1
Add point +2

Evaluation
register

N

N+2

0

4μs
2ms

RSTB

Fig.4-8-13 Evaluation for entered answer (In appropriate term)

4.8.4 Register
The contents of WDT setting are described in this section.
➢ WD trigger
If advanced mode is not selected in configuration register, only entering address allows refresh thetimer. (The data (D7-D0) is ignored but parity bit is checked.)◼ Address (WDTRG) : 16H
A5
A4
A3
A2
A1
A0
0
1
0
1
1
0
◼ RegisterTo evaluate “answer”, microcontroller should enter below data in accordance with the question.
D7
D6
D5
D4
D3
D2
D1
D0
OPE(1:0)
Data with requested operation
Microcontroller should obtain below “question”.
Do7
Do6
Do5
Do4
Do3
Do2
Do1
Do0
OPE(1:0)
SUBJ(5:0)◼ Contents
Microcontroller should operate with below received D5-D0 bits.
OPE(1:0)
Control contents
Do7
Do6
0
0
Copy Do5-Do0 bits for D5-D0
0
1
Shift D05-Do0 bits to the 1bit left for D5-D0
1
0
Shift Do5-Do0 bits to the 1bit right for D5-D0
1
1
Invert Do5-Do0 bits for D5-D0 ** Default setting
Subjected data bits are created by the PMIC.
SUBJ(5:0)
Control contents
Do5-Do0
Random data
Note: Default data is all “1” in SUBJ(5:0).
Note: When data is shifted to left or right, “0” is inserted into empty Do0 or Do5.

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RAA270000KFT data sheet➢ Watch dog time
This register can set watch dog time and rate of close window to watchdog time.
This register is a secured register. It is necessary to enter “key” code before enter this request. (See
“4.2.3 Secured request”.)◼ Address (WDTIME) : 17H
A5
A4
A3
A2
A1
A0
0
1
0
1
1
1
◼ Register
D7
D6
D5
D4
D3
D2
D1
D0
CWSET(1:0)
WDTIME(1:0)◼ Setting contents
Below table shows OW and CW time setting.
CWSET(1:0)
WDTIME(1:0)
Setting time
D3
D2
D1
D0
0
0
CW rate : 0% *0001
CW rate : 25%01
10
CW rate : 50%
10
1
1
CW rate : 75%
1
1* Default setting
Caution: CWSET is not available in “Advanced mode”.
Warning: Please do not change setting during WD running.
➢ Evaluation value
The accumulated value of QA monitoring is read via this register.
◼ Address (QAEVA) : 19H
A5
A4
A3
A2
A1
A0
0
1
1
0
0
1
◼ Register (Below bits are read only.)
Do7
Do6
Do5
Do4
Do3
Do2
Do1
ACCVA(7:0)

Setting time
WD time : 8ms
WD time : 16ms
WD time : 32ms
WD time : 64ms ** Default setting

Do0➢ Accumulated value for reset
This register can set a value to occur reset.
◼ Address (RSTVA) : 1CH
A5
A4
A3
A2
A1
A0
0
1
1
1
0
0
◼ Register
D7
D6
D5
D4
D3
D2
D1
D0
SETVA(7:0)◼ Setting contents
Any numbers is allowed to set this register. The default value of this register is “255”.
But setting number of “zero” is prohibited. Since reset always occurs when “Advanced mode” isselected in configuration register.

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RAA270000KFT data sheet
4.8.5 Electrical characteristics◆ Watchdog time
ParameterFirst window time
Watch dog time1
Watch dog time2
Watch dog time3
Watch dog time4◆ WDI pulse
Parameter
Rise time
Fall time
Pulse width

Symbol
Tfw
Twd1
Twd2
Twd3
Twd4

Conditions
Setting: WDTIME(1:0)=(0,0)
Setting: WDTIME(1:0)=(0,1)
Setting: WDTIME(1:0)=(1,0)
Setting: WDTIME(1:0)=(1,1)

Symbol
trwdi
tfwdi
twwdi

Conditions

twwdi
trwdi

MIN
230.4
7.2
14.4
28.8
57.6

TYP
256.0
8.0
16.0
32.0
64.0

MAX
281.6
8.8
17.6
35.2
70.4

Unit
ms
ms
ms
ms
ms

MIN
2.0

TYP
-

MAX
10
10
-

Unit
ns
ns
μs

tfwdi

WDI

Fig.4-8-14

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RAA270000KFT data sheet

4.9 Reset
The PMIC generates reset signal. RSTB pin should be connected to an external pull-up resistor. The pullup resister can be connected to 5V or 3.3V level.

4.9.1 Reset factor
There are several cases to force reset happen. Reset signal would happen by following case.
➢ LDO1 output
The output voltage downs to Vd1l2 (3.09V typ) supply voltage down such as crank pulse situation orover current sinks from LDO1’s output. These situations are regarded as unusual condition so that the
PMIC generate reset signal. Please refer to “4.7 Power rail sequence”.
➢ No first trigger to start WDT operation
After initial reset is released, the WDT needs 1st trigger to start its operation. If the trigger is notentered, it generates 2ms reset pulse. Please refer to “4.8 Watchdog Timer”.
➢ WD timer expires in Open Window and Close window
After WDT starts to operate, the system should enter a request to refresh WD timer. If no trigger isentered and the timer expires, then it generates 2ms reset pulse. And when configuration register isset, it makes reset by trigger in close window. Please refer to “4.8 Watchdog Timer”.
➢ Reach the designated number in QA monitoring
In “Advanced mode” of WDT operation, evaluation register has accumulated evaluation value. If thevalue reaches designated number, it generates 2ms reset pulse. Please refer to “4.8.3 Advanced mode”.
➢ Microcontroller’s safety monitor
The PMIC monitors ERROR1/2 pins indicating microcontroller’s safety operation. If the system needs
reset when ERROROUT1 or ERROROUT2 pin of microcontroller indicates something happens, itneeds to set configuration register. Please refer to “4.10 Specified Output Pins”.
➢ EN0, EN1
Once either EN0 or EN1 are set 1, the PMIC starts its operation. When both EN0 and EN1 turn to 0,
reset occurs. Please refer to “4 PMIC function”.
➢ Thermal shut down
Before the PMIC enters thermal shut down, reset occurs and set the register as a reset factor.
➢ Low voltage detection in DCDC2 and LDO2
It needs to set “configuration register”. Detail is described in “4.1.4 Configuration register”.
➢ Low voltage of supply voltage
In order to prevent malfunction of the PMIC, the PMIC asserts reset below Vdb (3.7V typ.) supply
voltage.

4.9.2 Reset factor register
The PMIC provides reset factor which indicates what caused abnormal reset. These registers are initialized
by DET0O which indicates LDO0 powered up. In other words, the registers are initialized only when the
PMIC starts to operate.

Reset factor
Low voltage detection on VOUT1
Low voltage detection on VD2Expired watch dog time
Thermal shut down
Low voltage detection on VOUT2

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Table 4-9 Reset factor
SymbolNote
LVLDO1LVDC2With setting configuration register
WDEXP
TSDTMPLVLDO2
With setting configuration register

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RAA270000KFT data sheet➢ Reset factor
The factors which cause occurring reset are lined up in this register. Even after reset is released, it
can recognize what factor causes reset.
◼ Address (RSTFAC) : 12H
A5
A4
A3
A2
A1
A0
0
1
0
0
1
0
◼ Register (Below bits are read only.)
Do7
Do6
Do5
Do4
Do3
Do2
Do1
Do0
LVLDO2 TSDTMP WDEXP LVDC2 LVLDO1◼ Contents
Bit
Contents0
No interrupt request *1
Interrupt request* Default setting
Note1: This register is not initialized by RSTB.
Note2: If “CWRSTB” bit in CONF register is set “1”, “WDEXP” bit will be set “1” as well when WD
trigger is executed during CW.
➢ Reset factor clear
Reset factor clear for “RSTFAC” register is placed in this address. If all contents of this address arecleared, “INTRSFG” bit of “INTFAC” register is cleared, too.
◼ Address (RSTFCL) : 13H
A5
A4
A3
A2
A1
A0
0
1
0
0
1
1
◼ Register
D7
D6
D5
D4
D3
D2
D1
D0
CLLVLDO2 CLTSDTMP CLWDEXP CLLCDC2 CLLVLDO1◼ Contents
Bit
Contents
0
No change *1
Clear interrupt* Default setting➢ Reset factor mask
Reset factor mask for “RSTFAC” register is placed in this address.
◼ Address (RSTFMSK) : 14H
A5
A4
A3
A2
A1
A0
0
1
0
1
0
0
◼ Register
D7
D6
D5
D4
D3
D2
D1
MSKLVLDO2 MSKTSDTMP MSKWDEXP MSKLVDC2◼ Contents
Bit
Contents0
No mask *1
Execute mask
* Default setting

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RAA270000KFT data sheet
4.9.3 Software reset
Even though no reset factors exist, the PMIC can make reset pulse via SPI. To prevent unexpected reset,
it needs one request to execute reset.
➢ Software reset
This register is a secured register. It is necessary to enter with “key” code. (See “4.2.3 Secured
request”.)◼ Address (SFTRST) : 1DH
A5
A4
A3
0
1
1
◼ Register
Do7
Do6
Do5

A2
1

A1
0

A0
1

Do4
Do3
RDMKEY(7:0)

Do2

Do1

Do0

◼ Setting content• Should enter RDMKEY data which is obtained by reading PRTCT register.

4.9.4 External reset
RSTB should be pulled up to a power rail with resister. Since RSTB is O/D, RSTB is able to be wired toreset pin of other device. (See below figure. The other reset should be also O/D.) To avoid accidental resetof other device, more than 400μs of forced reset is needed.
A power rail
The PMIC

RSTB
a

MCU

400μs

b

RSTB

Other device

a

Reset

RSTB

Reset

b

(a) Wired reset
Fig. 4-9-1 Wired reset(b) Narrow reset pulse

4.9.5 Electrical characteristics◆ Reset timing 1
Parameter
Reset release time
Reset pulse width
Forced reset period

Symbol
TdrstbTwrstbTintrstb

Conditions
From initial INTOUT rise
External forced reset

MIN
0
1.8
360

TYP
2.0
400

MAX
2.2
440

◆ Reset timing 2
Parameter
SymbolConditions
MIN
TYP
MAX
Detect to reset
Tuv
60
Reset
Tuvrst12
Caution: The reset caused by VD2 and VOUT2 low voltage needs to set “Configuration Register”.

Unit
ms
ms
μs

Unit
μs
ms

INTOUT
Twrstb

Tdrstb
RSTB

Fig. 4-9-2 RSTB timing 1

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RAA270000KFT data sheet

Tintrstb

In case ofForced reset period < Tintrstb

RSTB
Twrstb

Fig. 4-9-3 Forced reset duration for internal reset

VD2 or VOUT2Tuv
INTOUT

RSTB

TuvrstFig. 4-9-4 RSTB timing 2

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RAA270000KFT data sheet

4.10 Specified Output Pins
The PMIC has some specified digital output pins. These pins serve safety operation in entire system.
Operation of each pin is described in below.
◆ Low voltage indicator (SUSP)
When VOUT1 which applies for MCU’s I/O goes down low voltage Vd1l1 level, it asserts SUSP low.
Detail detect level is shown in 4.12.4.
Additionally, it can set High/Low level via a register. This setting can be done after SUSP pin asserts
high.
50μs

Vd1l1
VOUT1

Vd1l2

SUSP
INTOUT
RSTB

Fig. 4-10-1 SUSP timing◆ Safety management (FSOUT)
Safety management is a function realized with microcontroller. RENESAS’ microcontroller has output
pins which indicate that unusual situation happens in the microcontroller. For more detail, please refer touser’s manual of RENESAS’ microcontroller.
The PMIC has ERROR1/2 pin to receive the error indication signals of microcontroller. When ERROR1
or ERROR2 signal indicates error, the PMIC makes FSOUT assert low. If system needs reset when the
PMIC detects unusual situation in microcontroller, it needs to set configuration register. (The behavior is
illustrated as dot line in the next figure)
There are two kinds of format in unusual signal. One is static operation and the other one is dynamic
operation. To determine unusual situation in microcontroller, it needs to select signal format. If static levelis selected, low level on ERROR1 or ERROR2 indicates error occurs in microcontroller. And the PMIC
detects low, it makes RSTB assert low. If dynamic mode, no toggling indicates error occurs inmicrocontroller. And the PMIC detects no toggling during 100μs or 200μs, it makes RSTB assert low as
well. In initial operation, after ERROR1/2 signal rises, the PMIC starts monitoring ERROR1/2 pins.
There is a case that microcontroller assigns one monitor pin. If then, remaining pin should be connect
to both ERROR1/2 pins on PWB.
When RSTB= Low, FSOUT will be also low level.
Note1: Toggling time needs to be 100μs+/-10μs or 200μs+/-20μs.
2ms

2ms

RSTB

RSTB

ERROR1ERROR1ERROR2ERROR2

FSOUT

FSOUT
Start monitoring

Start monitoring
100μs(a) Static mode

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Fig. 4-10-2 Safety guardian operation

page 46 of 68

RAA270000KFT data sheet◆ External control (EXCNT)In order to control another device through the PMIC, the PMIC has a specified output pin, EXCNT.
After WDT is requested to start, EXCNT is set to high. When reset occurs by expired WD or otherreasons, EXCNT asserts low. And it can control the pin via SPI. And occurring reset makes EXCNT
assert low. In “Advanced mode” for WD, EXCNT asserts high after QA monitoring starts. Pin control canbe done via SPI as well.
In the case not to occur reset by setting reset mask register MSKWDEXP, when WDT expires then only
EXCNT pin asserts low until the trigger is applied to start WDT. (Fig.4-10-3 (c))
Additionally, in the case to make reset by a trigger during CW, EXCNT pin asserts low by unexpected
trigger in CW as well.
When WDT suspends by SUSP=Low (DET1L detection), EXCNT will be also low level.
WD expired
RSTB
WD timer start

Set to low

Set to high

SPI
EXCNT

(a) In WD normal mode
Reached .reset value in RSTVA
RSTBWrite first answer

Set to low

Set to high

SPI
EXCNT

WD timer start(b) In WD “Advanced mode”
RSTB

MSKWDEXP=1

WDT expires

WD timer start

SPI
WD timer start
EXCNT(c) Set reset mask register not to occur reset
Fig. 4-10-3 EXCNT operation

4.10.1 Register➢ Select pin level and microcontroller’s error indication signal mode
◼ Address (PINSET) : 15H
A5
A4
A3
A2
A1
A0
0
1
0
1
0
1
◼ Register
D7
D6
D5
D4
D3
D2
SETSUSP SETEXCNT◼ Setting contents
Register name
SETSUSPSETEXCNT
SELDT
EMODE

D5
D4
D1
D0

Control contents
SUSP pin control
EXCNT pin control
ERROR toggle expire timeError indication mode

D1
D0
SELDT EMODE
Setting
1
0
Set high *Set low
Set high *Set low
100μs
200μs *
Dynamic
Static ** Default setting

Note1: SETEXCNT setting is available after WD timer starts.
Note2: Setting of the SELDT bit is effective at EMODE=1 (dynamic mode).
Note3: When EMODE=0(static mode), expire time is 100μs fixing.
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RAA270000KFT data sheet
4.10.2 Electrical characteristics◆ External control (EXCNT)Parameter
SymbolDelay time 1
Tdexcnt1
Delay time 2
Tdexcnt2

Conditions
From SPICSB rise
From RSTB fall

SPICSB
Tdexcnt1

RSTB

MIN
-

TYP
-

MAX
3.0
1.0

Unit
μs
μs

Tdexcnt2

EXCNT

EXCNT

(a) Low setting via SPI(b) Asserting low by reset

Fig. 4-10-4 EXCNT delay

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RAA270000KFT data sheet

4.11 Interrupt Signal
The purpose of interrupt signal is to inform what happened inside the PMIC to microcontroller. The INTOUT
pin indicates that interrupt factor occurs and microcontroller can identify what interrupt factor is via SPI.

4.11.1 Interrupt control
When interrupt factor happens, interrupt signal is asserted. The information of interrupt factor is stored into
interrupt register and microcontroller can read what the interrupt factor is. User can clear the interrupt
register by writing clear register. If several interrupt factors are stored, it needs to clear all clear registers
which cause interrupt assertion.
Interrupt informing can be suspended by setting interrupt mask registers. After setting these registers,interrupt is not asserted even though interrupt factor occurs.
Clear timing

INTOUTINTOUTSPICSBSPISPICLK
Clear request

Fig. 4-11-1 Interrupt clear timing

4.11.2 Interrupt factor

Interrupt factor 3Interrupt factor 2Interrupt factor 1

The interrupt factors are listed below. Interrupt bit names are indicated as symbol.
After 500μs passed from the point where interrupt clear was executed, if interrupt factor remains suchsituation, INTOUT asserts low again.
Table 4-11 List of interrupt factor
Interrupt factor
SymbolOver voltage detection on VTRQ2
DETTRQ2UOver voltage detection on VTRQ1
DETTRQ1UOver voltage detection on VADC
DETADUOver voltage detection on VOUT2DET2U
Over voltage detection on VOUT1
DET1UOver voltage detection on VD2
DETDC2UOver voltage detection on VD1
DETDC1U
Low voltage detection on VOUT0SW
DET0SWL
Low voltage detection on VTRQ2
DETTRQ2L
Low voltage detection on VTRQ1
DETTRQ1L
Low voltage detection on VADC
DETADLLow voltage detection on VOUT2
DET2L
Low voltage detection on VOUT1
DET1L
Low voltage detection on VD2
DETDC2L
Low voltage detection on VD1
DETDC1L
High temperature warning at TRACK1/2
WRTMP2High temperature warning at DCDC1 or LDO1 WRTMP1
WD trigger in CW
WRWDT
Self-diagnosis of detectors of LDO0 and BGR DETREF
Detection of VINR low voltage
DETBAT1
Detection of DCDC2 over current
DETDC2OC
Detection of DCDC1 over current
DETDC1OC

R02DS0021EJ0100 Rev.1.00
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Enters protect function
Stops its switching

Enters protect function
Enters protect function

Enters protect function
Enters protect function

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RAA270000KFT data sheet

Interrupt factor 4Interrupt factor (Continued)
Interrupt factor
Intentional interrupt
Self-diagnosis of oscillator
Self-diagnosis of state machine
Self-diagnosis of VOUT0SW
Monitoring of digital output, FSOUT pin
Monitoring of digital output, EXCNT pin
Monitoring of digital output, SUSP pin
Monitoring of digital output, RSTB pin

Interrupt factor

Symbol
DUMMY
SDOSC
SDSTA
SD0SW
PFSOUTPEXCNT
PSUSP
PRSTB

Note
Checks connection to MCU

Checks connection to VIN3V

Interrupt factor occurs
500μs

INTOUT

Clear interrupt

Fig. 4-11-2 INTOUT behavior when interrupt factor continues
Note: Once INTOUT is cleared, occurring interrupt factor doesn’t make INTOUT assert low during 500μs.

4.11.3 Register
Interrupt register indicates the factor that causes INTOUT assertion. Even one or more interrupt factor
occurs, INTOUT would assert low.
➢ Interrupt factor
This register indicates what interrupt register occurs so that it can read interrupt factor directly.
For INTSD register, it indicates fail occurred in self-diagnosis. And if the factor belonged in eachinterrupt request address failed in self-diagnosis, D3-D0 is set “1” simultaneously. For INTRSFG
register, it indicates the factor which makes reset exists. The factors are collected in INTRSFG register.
In order to clear this register, it needs to clear all interrupt factors.
◼ Address (INTFAC) : 03H
A5
A4
A3
A2
A1
A0
0
0
0
0
1
1
◼ Register (Below bits are read only.)
Do7
Do6
Do5
Do4
Do3
Do2
Do1
Do0
INTRSFG INTSD INTR4 INTR3 INTR2 INTR1◼ Contents
Setting
Register nameControl contents
1
0
INTRSFG
D5
Flags of reset factor
OccursNone *INTSD
D4Interrupt factor in self diagnosis
OccursNone *INTR4
D3
Interrupt factor in INTREQ4
OccursNone *
INTR3
D2
Interrupt factor in INTREQ3
OccursNone *INTR2
D1
Interrupt factor in INTREQ2
OccursNone *INTR1
D0
Interrupt factor in INTREQ1
OccursNone ** Default setting
Note1: This register is not initialized by RSTB.

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RAA270000KFT data sheet➢ Interrupt request 1
Interrupts of over voltage detection are collected in this address.
When fail is detected in self-diagnosis, interrupt request occurs in corresponding block as well.
◼ Address (INTREQ1) : 04H
A5
A4
A3
A2
A1
A0
0
0
0
1
0
0
◼ Register (Below bits are read only.)
Do7
Do6
Do5
Do4
Do3
Do2
Do1
Do0
DETTRQ2U DETTRQ1U DETADU DET2U DET1U DETDC2U DETDC1U◼ Contents
Bit
0
1

Contents
No interrupt request *Interrupt request* Default setting
Note: This register is not initialized by RSTB.

➢ Interrupt request 2
Interrupts of low voltage detection are collected in this address.
When fail is detected in self-diagnosis, interrupt request occurs in corresponding block.
◼ Address (INTREQ2) : 05H
A5
A4
A3
A2
A1
A0
0
0
0
1
0
1
◼ Register (Below bits are read only.)
Do7
Do6
Do5
Do4
Do3
Do2
Do1
Do0
DET0SWL DETTRQ2L DETTRQ1L DETADL DET2L DET1L DETDC2L DETDC1L
Note: In the case that DET2L is added to reset factor, if DET2L causes reset, DET2L bit remains
even after reset is released.
◼ Contents
Bit
Contents0
No interrupt request *1
Interrupt request* Default setting
Note: This register is not initialized by RSTB.
➢ Interrupt request 3
Other interrupt factors are collected in this address.
◼ Address (INTREQ3) : 06H
A5
A4
A3
A2
A1
A0
0
0
0
1
1
0
◼ Register (Below bits are read only.)
Do7
Do6
Do5
Do4
Do3
WRTMP2 WRTMP1 WRWDT DETREF◼ Contents
Bit
Contents0
No interrupt request *1
Interrupt request* Default setting
Note: This register is not initialized by RSTB.

R02DS0021EJ0100 Rev.1.00
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Do1
DETDC2OC

Do0
DETDC1OC

page 51 of 68

RAA270000KFT data sheet➢ Interrupt request 4
Interrupts of diagnosis are collected in this address.
◼ Address (INTREQ4) : 07H
A5
A4
A3
A2
A1
A0
0
0
0
1
1
1
◼ Register
Below bits are read only except “DUMMY” bit. In order to make intentional assertion, only DUMMY
bit is allowed to be written. (It also can be read.)
D7
Do6
Do5
Do4
Do3
Do2
Do1
Do0
DUMMY SDOSC SDSTA SD0SW PFSOUT PEXCNT PSUSP PRSTB◼ Contents
Bit
Contents0
No interrupt request *1
Interrupt request* Default setting
Note: This register is not initialized by RSTB.
After INTOUT occurs by the DUMMY bit, please set 0 as the DUMMY bit, directly. After that,set 1 as the CLDUMMY bit.
➢ Interrupt clear 1
Clear for “INTREQ1” register is placed in this address. If all contents of this address are cleared,“INTR1” bit in “INTFAC” register is clear, too.
◼ Address (INTCL1) : 08H
A5
A4
A3
A2
A1
A0
0
0
1
0
0
0
◼ Register (Below bits are written only.)
D7
D6
D5
D4
D3
D2
D1
D0
CLTRQ2U CLTRQ1U CLADU CL2U
CL1U CLDC2U CLDC1U◼ Contents
Bit
Contents
0
No change *1
Clear interrupt* Default setting➢ Interrupt clear 2
Clear for “INTREQ2” register is placed in this address. If all contents of this address are cleared,“INTR2” bit of “INTFAC” register is clear, too.
◼ Address (INTCL2) : 09H
A5
A4
A3
A2
A1
A0
0
0
1
0
0
1
◼ Register (Below bits are written only.)
D7
D6
D5
D4
D3
D2
D1
D0
CL0SWL CLTRQ2L CLTRQ1L CLADL
CL2L
CL1L CLDC2L CLDC1L◼ Contents
Bit
Contents
0
No change *1
Clear interrupt* Default setting

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RAA270000KFT data sheet➢ Interrupt clear 3
Clear for “INTREQ3” register is placed in this address. If all contents of this address are cleared,“INTR3” bit of “INTFAC” register is clear, too.
◼ Address (INTCL3) : 0AH
A5
A4
A3
A2
A1
A0
0
0
1
0
1
0
◼ Register (Below bits are written only.)
D7
D6
D5
D4
D3
D2
D1
D0
CLTMP2 CLTMP1 CLWDT CLREF CLBAT1 CLDC2OC CLDC1OC◼ Contents
Bit
Contents
0
No change *1
Clear interrupt* Default setting➢ Interrupt clear 4
Clear for “INTREQ4” register is placed in this address. If all contents of this address are cleared,“INTR4” bit of “INTFAC” register is clear, too.
◼ Address (INTCL4) : 0BH
A5
A4
A3
A2
A1
A0
0
0
1
0
1
1
◼ Register (Below bits are written only.)
D7
D6
D5
D4
D3
D2
D1
D0
CLDUMMYCLSTA CL0SW CLPFSOUT CLPEXCNT CLPSUSP CLPRSTB
Note: After INTOUT occurs by the DUMMY bit, please set 0 as the DUMMY bit, directly. After that,set 1 as the CLDUMMY bit.
◼ Contents
Bit
Contents
0
No change *1
Clear interrupt* Default setting➢ Interrupt mask 1
Interrupt mask for “INTR1” register is placed in this address.
◼ Address (INTMSK1) : 0CH
A5
A4
A3
A2
A1
A0
0
0
1
1
0
0
◼ Register
D7
D6
D5
D4
D3
D2
D1
D0
MSKTRQ2U MSKTRQ1U MSKADU MSK2U MSK1U MSKDC2U MSKDC1U◼ Contents
Bit
Contents0
No mask *1
Execute mask
* Default setting

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RAA270000KFT data sheet➢ Interrupt mask 2
Interrupt mask for “INTR2” register is placed in this address.
◼ Address (INTMSK2) : 0DH
A5
A4
A3
A2
A1
A0
0
0
1
1
0
1
◼ Register
D7
D6
D5
D4
D3
MSK0SWL MSKTRQ2L MSKTRQ1L MSKADL MSK2L◼ Contents
Bit
Contents0
No mask *1
Execute mask
* Default setting

D2
MSK1L

D1
D0
MSKDC2L MSKDC1L➢ Interrupt mask 3
Interrupt mask for “INTR3” register is placed in this address.
◼ Address (INTMSK3) : 0EH
A5
A4
A3
A2
A1
A0
0
0
1
1
1
0
◼ Register
D7
D6
D5
D4
D3
D2
MSKTMP2 MSKTMP1 MSKWDTMSKBAT1◼ Contents
Bit
Contents0
No mask *1
Execute mask
* Default setting

D1
D0
MSKDC2OC MSKDC1OC➢ Interrupt mask 4Interrupt mask for “INTR4” register is placed in this address.
◼ Address (INTMSK4) : 0FH
A5
A4
A3
A2
A1
A0
0
0
1
1
1
1
◼ Register
D7
D6
D5
D4
MSKDUMMY MSKOSC MSKSTA◼ Contents
Bit
Contents0
No mask *1
Execute mask
* Default setting

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D3
D2
D1
MSKPFSOUT MSKPEXCNT MSKPSUSPD0MSKPRSTB

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RAA270000KFT data sheet

4.12 Functional Safety
In order to protect microcontroller or the PMIC from extraordinary accident, the PMIC has a sort of protectfunction.

4.12.1 Voltage detection
All regulators in the PMIC have voltage detector to its output. And battery voltage detector has samefunction as well. The voltage-detect function operates after self-diagnosis completes.
◆ High and low voltage detection 1
High and low voltage detect behavior is shown in below figure. When high or low voltage is detected, it
makes INTOUT assert low.
Regulator output
Detect voltage
Release voltage
Release voltage
Detect voltage

Detector output(Low)
Detector output(High)

Fig. 4-12-1 High and low voltage detector’s behavior◆ High and low voltage detection 2
In DCDC2, high and low voltage detect policy are different from above behavior.
The detectors have no release level. Instead, they have anti glitch circuit to prevent nuisance reset. If
any transient on the output with continuing more than designated duration is monitored, then it makes
INTOUT assert low.
It can be set to generate reset when low voltage is detected. Please refer to “4.1.4 Configuration
register”.
Regulator output

Detect voltage

Detect voltage

tuv

tuv

Detector output(Low)
Detector output(High)

Fig. 4-12-2 High and low voltage detector’s behavior in DCDC2

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RAA270000KFT data sheet
4.12.2 PMIC behavior after unusual detection
The all the regulators have high or low voltage detectors. Some of detection may lead serious situation,other of them does not affect whole system. The behaviors in case of unusual detections are summarized
below table. The behavior to temperature detection is described as well.
Table 4-12 Listed PMIC behavior
Description
Behavior of the PMICINTOUT would be asserted
DETBAT1
Low voltage detection of battery
All regulator will stop operating
DCDC1/2 stops switching behavior
DETDC1UOver voltage detection of DCDC1
INTOUT would be asserted
DCDC1 enters interval operating
DETDC1L
Low voltage detection of DCDC1
INTOUT would be asserted
DCDC1 enters interval operating
DETDC1OCOver current detection of DCDC1
INTOUT would be asserted
DET0SWL
Low voltage detection of VOUT0SW INTOUT would be asserted
DET1U
Over voltage detection of LDO1INTOUT would be asserted
DET1L1Low voltage detection of LDO1
SUSP, INTOUT would be asserted
DET1L2
Low voltage detection of LDO1
Reset occurs
INTOUT would be asserted
DET2U
Over voltage detection of LDO2
DCDC1 enters interval operating
DET2L
Low voltage detection of LDO2INTOUT would be asserted
DETADUOver voltage detection of LDOAD
INTOUT would be asserted
DETADLLow voltage detection of LDOAD
INTOUT would be asserted
DCDC2 stops switching
DETDC2UOver voltage detection of DCDC2
DCDC1 enters interval operating
INTOUT would be asserted
DCDC2 enters interval operating
DETDC2L
Low voltage detection of DCDC2
INTOUT would be asserted
DCDC2 enters interval operating
DETDC2OCOver current detection of DCDC2
INTOUT would be asserted
DETTRQ1UOver voltage detection of TRACK1
INTOUT would be asserted
DETTRQ1L
Low voltage detection of TRACK1
INTOUT would be asserted
DETTRQ2UOver voltage detection of TRACK2INTOUT would be asserted
DETTRQ2L
Low voltage detection of TRACK2INTOUT would be asserted
WRTMP1/2
Warning temperature detection
INTOUT would be asserted
Force to stop PMIC operation
TSDTMP
Shut down temperature detection
INTOUT would be asserted
In above table, when the PMIC detect low voltage of DCDC2, it leads to enter protect mode and asserted
INTOUT.
Unusual detection

4.12.3 Self-diagnosis
Built-in-self-test is implemented in the PMIC so that self-diagnostic of the PMIC’s function is executedduring initial reset. The self-diagnostic is done to prevent serious situation such as applying unexpectedvoltage to MCU or communication disability with microcontroller. The following blocks are checked as selfdiagnostic.
➢ Detectors: Confirm detect function➢ Logic circuit: Confirm timer function➢ Oscillator: Confirm if oscillation frequency is expected➢ Temperature sensor: Confirm the function of thermal shutdown◆ Detectors
To make sure output voltage of each regulator, detect functionality is tested before regulators power
up. A voltage for comparator test is applied to the detector part. During diagnosis execution, detect
function is checked by changing comparator’s input. If error is detected, INTOUT is asserted.

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RAA270000KFT data sheet◆ Logic circuit
The logic circuit in the PMIC is checked before reset is released. Self-diagnosis is done by test circuit
implemented in the PMIC. If error is detected in self-diagnosis, the PMIC does not start to operate.
◆ Oscillator
The oscillator is used for not only switching in DCDC but also state machine. Damage in the oscillator
may affect PMIC function.
There are two oscillators which have quite same operation. They monitor oscillation each other, and if
unusual oscillation is detected then switched to the oscillator which acts usual operation. And then the
PMIC informs INTOUT assertion. If unusual oscillation is detected, INTOUT is asserted.
◆ Temperature sensor
The temperature sensor senses a voltage corresponding to the die temperature. During self-diagnosis
period, thermal shutdown function is checked. If error is detected, INTOUT is asserted.
Note : When errors were detected by self-diagnostic before power supply start, INTOUT is kept low level.

4.12.4 Electrical characteristics
Detect level of each regulators are shown in below tables.
The condition is Tj=-40 to 150°C, unless otherwise specified.
◆ Battery voltage detector
Table 4-12-1 Detect level of battery
Parameter
SymbolCondition
DETBAT1
Detect voltage
Vdb
Release voltage
Vrb

MIN

TYP

MAX

Unit

3.50
5.70

3.70
6.00

3.90
6.30

V
V

Table 4-12-2 Detect level of DCDC1
SymbolCondition

MIN

TYP

MAX

Unit

Vdd1u
Vrd1u

6.500
6.200

6.750
6.450

7.000
6.700

V
V

Vdd1l
Vrd1l

2.700
4.800

2.850
5.000

3.000
5.200

V
V

Table 4-12-3 Detect level of DCDC2
SymbolCondition

MIN

TYP

MAX

Unit

Vdd2u

1.350

1.380

1.410

V

More than 60μs duration time

1.150

1.174

1.197

V

Table 4-12-4 Detect level of LDO0
SymbolCondition

MIN

TYP

MAX

Unit

Vd0u
Vr0u

3.432
3.366

3.531
3.465

3.630
3.564

V
V

Vd0l
Vr0l

2.970
3.069

3.053
3.152

3.135
3.234

V
V

◆ Detector in DCDC1
Parameter
DETDC1U
Detect voltage
Release voltage
DETDC1L
Detect voltage
Release voltage◆ Detector in DCDC2
Parameter
DETDC2U
Detect voltage
DETDC2L
Detect voltage

Vdd2l◆ Detector in LDO0
Parameter
DET0U
Detect voltage
Release voltage
DET0L
Detect voltage
Release voltage

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RAA270000KFT data sheet◆ Detector in VOUT0SW
Parameter
DET0SWL
Detect voltage
Release voltage

Table 4-12-5 Detect level of VOUT0SW
SymbolCondition
MIN

TYP

MAX

Unit

Vd0sw
Vr0sw

3.000
3.073

3.075
3.150

3.150
3.227

V
V

Table 4-12-6 Detect level of LDO1
SymbolCondition

MIN

TYP

MAX

Unit

Vd1u
Vr1u

5.200
5.100

5.350
5.250

5.500
5.400

V
V

Vd1l1
Vr1l1

4.500
4.650

4.625
4.775

4.750
4.900

V
V

Vd1l2

3.000

3.090

3.180

V

Table 4-12-7 Detect level of LDO2
SymbolCondition

MIN

TYP

MAX

Unit

Vd2u
Vr2u

3.402
3.366

3.500
3.465

3.598
3.564

V
V

Vd2l
Vr2l

3.006
3.069

3.090
3.152

3.174
3.234

V
V

Table 4-12-8 Detect level of LDOAD
SymbolCondition

MIN

TYP

MAX

Unit

Vdadu
Vradu

5.200
5.100

5.350
5.250

5.500
5.400

V
V

Vdadl
Vradl

4.500
4.650

4.625
4.775

4.750
4.900

V
V

Table 4-12-9 Detect level of TRACK1/2
SymbolCondition
MIN

TYP

MAX

Unit

Vdtrq1u
Vrtrq1u

Based on input voltage
Based on input voltage

104.0
102.1

107.0
105.0

110.0
108.0

%
%

Vdtrq1l
Vrtrq1l

Based on input voltage
Based on input voltage

90.0
93.0

92.5
95.5

95.0
98.0

%
%

◆ Detector in LDO1
Parameter
DET1U
Detect voltage
Release voltage
DET1L1
Detect voltage
Release voltage
DET1L2Detect voltage◆ Detector in LDO2
Parameter
DET2U
Detect voltage
Release voltage
DET2L
Detect voltage
Release voltage◆ Detector in LDOAD
Parameter
DETADU
Detect voltage
Release voltage
DETADL
Detect voltage
Release voltage◆ Detector in TRACK1/2
Parameter
DETTRQ1/2U
Detect voltage
Release voltage
DETTRQ1/2L
Detect voltage
Release voltage

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RAA270000KFT data sheet

4.13 Temperature Sensor
Temperature sensors are implemented in the PMIC. In order to sense temperature at several points ofPMIC, several sensors are placed.

4.13.1 Thermal shut down
For product safety, a thermal shutdown function is implemented. Temperature sensors detect a voltage
corresponding to internal temperature. When warning temperature is detected, INTOUT asserts low. Further,when shutdown temperature is detected, it forces the PMIC execute power down sequence.
Four temperature sensors are placed near by DCDC1, TRACK1, TRACK2, and LDO1. If one of thesesensors detects high temperature, detection behavior occurs.
After the temperature goes down across the release temperature, the PMIC restart in the power-up
sequence. But TRACK1 and TRACK2 need request to resume operation.
Table 4-13 Thermal detect temperature
Items
SymbolConditions
MIN
TYP
MAX Unit
Warning temperature
Twng
140
160
180
Shutdown temperature
Tsd
160
180
200
°C
Release temperature
Trls
125
145
165
Warning release temperature
Twrls
115
135
155
Note: Above values are guaranteed by design.
Relationship of above temperature order maintains anytime.
Temperature
Shutdown Temp.
Warning Temp.
Release Temp.
Warning release
TimeInterrupt condition

Interrupt

Regulators
Power down sequence

Power up sequenceFig. 4-13 Thermal shutdown function

4.13.2 Register
It can change temperature setting of both detect and release temperature.
➢ Temperature settingThis register is a secured register. It is necessary to enter “key” code before enter this request. (See
“4.2.3 Secured request”.)◼ Address (SENTMP) : 1EH
A5
A4
A3
A2
A1
A0
0
1
1
1
1
0
◼ Register
D7
D6
D5
D4
D3
D2
D1
D0
WARREL(1:0)
THREL(1:0)
WARDET(1:0) THDET◼ Setting contents
Setting
Register nameControl contents
1
0
THDET
D1
Thermal shutdown temperature
170°C
180°C *
* Default setting

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RAA270000KFT data sheet
WARDET(1:0)
D3
D2
0
0
0
1
1
0
1
1

WARREL(1:0)
D7
D6
0
0
0
1
1
0
1
1

Warning temp.
170°C
160°C *
150°C
140°C
* Default setting

THREL(1:0)
D5
D4
0
0
0
1
1
0
1
1

Shutdown release
155°C
145°C *
135°C
125°C
* Default setting

Warning release

155°C
145°C
135°C *
125°C
* Default setting
Note: This register is not initialized by RSTB.

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RAA270000KFT data sheet

4.14 Monitoring Function
The PMIC has monitoring function.
Analog monitoring function is indicates internal analog voltage. Digital monitoring function is monitoring
digital output pins.

4.14.1 Monitoring internal analog voltage
The PMIC has an analog monitoring function. It outputs the regulator level of the PMIC or internal analog
voltage with using operational amplifier. The voltage to output is selected via SPI. Microcontroller can readthese analog voltages through its ADC and can understand PMIC’s situation. Power on and off, output selectare done by setting register.
Temp1-4
VOUT0
VOUT1
VOUT2
VADC
VTRQ1

MUXOUT

VTRQ2
FBDC1
FBDC2
VINR
VREF1

Multiplexer decoder
Fig.4-14-1 Diagram of analog monitoring

4.14.2 Monitoring digital output
The PMIC has a digital monitoring function. It compares with output and control signal of digital output
buffer. If differentiation is detected, it makes INTOUT assert low.
The objective outputs are FSOUT, EXCNT, SUSP, and RSTB pins. But INTOUT pin can’t be monitored.
In order to check INTOUT pin, “DUMMY” bit in interrupt register, address 07H, is recommended to set.
Microcontroller can asserts INTOUT pin low by setting “DUMMY” bit. If microcontroller can’t recognize
interruption, something happens on INTOUT.
Delay
Interrupt control

Output signal

Digital output
Output buffer

Fig.4-14-2 Diagram of digital monitoring◆ Monitoring delay time
The output transition time depends on external environment. In order to make sure certain comparison,
the monitoring function compares with delayed output signal. The delay time is 1μs except RSTB. In
particular, dependency of external element on RSTB is large. Therefore, the delay time of RSTB is 100μs.

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RAA270000KFT data sheet
4.14.3 Register
Operation setting for monitoring function is described in this section.
➢ Signal select◼ Address (MUXCNT) : 18H
A5
A4
A3
A2
0
1
1
0
◼ Register
D7
D6
D5
D4
MUXCNT◼ Setting contents
This bit controls on and off control.
Register name
MUXCNT

D6

A0
0
D3

D2
D1
MUXSEL(3:0)

Control contents
On/Off control

These bits control output channel.
MUXSEL(3:0)
D3
D2
D1
D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1

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0

D0

Setting
1
On

0
Off *
* Default setting

Monitoring name
GND *
VINR
VOUT0
VOUT1
VOUT2
GND
VADC
VTRQ1
VTRQ2
FBDC1
FBDC2A/B
TEMP1 (Near DCDC1)
TEMP2 (Near LDO1)
TEMP3 (Near TRACK1)
TEMP4 (Near TRACK2)
VREF1* Default setting

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RAA270000KFT data sheet
4.14.4 Electrical characteristics
Electrical characteristic on recommended operating condition.
Parameter
SymbolConditions
Voinr
Selected VINR *1
Voldo0
Selected VOUT0
Voldo1
Selected VOUT1
Voldo2
Selected VOUT2
VoldoadSelected VADC
Votrack1
Selected VTRQ1
Votrack2
Selected VTRQ2
Output voltage
Vodc1
Selected FBDC1
Vodc2
Selected FBDC2A/B
Votmp1
Votmp2
At 25°C
Votmp3
Votmp4
Vref
Selected VREF1*2
Output stable time
tstb
From SPICSB rising

MIN
TYP
MAX
Unit
1.16
1.2
1.24
1.57
1.65
1.73
2.41
2.5
2.59
1.59
1.65
1.71
2.44
2.5
2.56
2.46
2.5
2.54
2.46
2.5
2.54
V
2.64
2.85
3.06
1.207
1.25
1.293
0.62
0.67
0.72
0.62
0.67
0.72
0.62
0.67
0.72
0.62
0.67
0.72
1.159
1.2
1.241
40
μs
*1 Applied VINR voltage is 12V.
*2 Guaranteed by design.

tstb

MUXOUTSPICSBSPICLK

Fig. 4-14-3 Output timing◆ Output of temperature sensor
The outputs of temperature depend on junction temperature. For reference, output temperature
characteristic is shown in below figure.
The approximate equation of the output voltage is as follow. And output deviation is +/-50mV for every
temperature.

Output (mV)

Votmp1-4 = 718-1.9*T (mV) where “T” is Tj.

Maximum line

Minimum line

Junction Temperature (°C)

Fig. 4-14-4 Output of temperature sensor
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RAA270000KFT data sheet

5 Application Diagram
Below figure shows typical application diagram which contains elements around the PMIC.
Battery (12V)

C9
2.2μF

C16 1μF

VINPTRQ1
VTRQ1

C13
1μF

VDDIO

SYSVCC
TREF1

C12
0.1μF

VINP1

VINPTRQ2
VTRQ2

EVCC

VOUT1
C6
10μF

TREF2
C10
2.2μF

C8
1μF

EN0
EN1
LDO0EN

VINP2

BUFAD

VOUT2

C11
0.1μF

VINPDC2A/B
C15
1μF

VINR
VIN3V

FBDC2A/B

VOUT0

LX2A/B

C5
1μF

L2 4.7μH

10kΩ

VDD
D2

VINPDC1A/B
C1
4.7μF

FBDC1
L1 4.7μH

LX1A/BMUXOUT

C4
10μF

FSOUT
TEST1
TEST2
AGND1
AGND2
PGND1
PGND2

ADCA

SPICSBSPICLKSPISDISPISDOCSIHOTCSSCSIHOTSCKCSIHOTSOCSIHOTSIINTOUT

IRQ0 etc

ERROR1ERROR2ERROROUT_M
ERROROUT_C

D1
C3
4.7μFX2pcs

PLLVCCVCC
LVDVCCTTLVCC

C141μF

10μF C7

VOUT0SW

C2
4.7μF

AVCC

VADC

3.3kΩ

C17
1μF

SUSP

NMI

WDI
WDENB

GPIOn

RSTB
EXCNT

RSTB

To control other device
D1,2 M1FS4 (SHINDENGEN)
L1,2 CLF6045T-4R7-H (TDK)
C1,C2 GCM32ER71H475K (MURATA)
C3 GCM31CR71C475K (MURATA)
C4,C6,C7 GCM21BR70J106K (MURATA)
C5 GCM219R71C105K(MURATA)
C8 GCM188C71A105K (MURATA)
C9,C10 GCM21BR71C225K (MURATA)
C11,C12 GCM188R71C104K (MURATA)
C13-17 GCM219R71C105K (MURATA)

Fig.5 Application circuit
Note: This is a very simplified example of an application. The function must be verified in the realapplication.
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RAA270000KFT data sheet

5.1 Layout guide lines
Important thing to consider the layout is component placement on the PCB. Please take into accountfollowing things for PCB trace design.
◆ For proper operation and to prevent EMI radiation, the freewheeling diode and inductor have to beplaced as close as possible to the PMIC. Also output capacitors have to be placed near by the inductor.
◆ The feedback trace of DCDC converter never crosses the inductor, and recommended connection pointis near output capacitor.
◆ For DCDC converter, GND connection of components is important. GNDs of input capacitor, output
capacitor, and freewheeling diode are connected to the same point.
◆ For LDO, in order to avoid influence of stray resistance on the PCB, output capacitor has to be placed
as close as possible to the PMIC.
◆ If application needs to apply power supply for multi devices, power distribution at output capacitor ofeach regulator is recommended.
◆ In order to maximum heat spread performance, the exposed pad on the backside of the package isrecommended to make soldering to GND plane.
◆

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RAA270000KFT data sheet

6 Electrical Characteristics
6.1 Recommended operating condition
Parameter
Input voltage
LDO power line
Digital I/O power
Circuit power line
Operational temp.

SymbolPin name
MIN
TYP
VBAT
VINR,VINPDC1A/B
6.0 *
12.0
VPLDO VINP1/2,VINPTRQ1/2,VINPDC2A/B
5.4
5.7
VDDIO VDDIO
4.5
5.0
VIN
VIN3V
3.0
3.3
Ta
-40
25
Rpur
RSTB
3.3
Pull up resistor
Rpus
SPISDO10* After the PMIC starts to operate, the PMIC keeps operate down to this voltage.

MAX
18.5
6.0
5.5
3.6
125
-

Unit
V
V
V
V
°C
kΩ
kΩ

6.2 Electrical characteristics
6.2.1 DC characteristics◆ Digital input
DC characteristics of digital pins are shown in below table.
Parameter
SymbolCondition
High level input voltage 1
VIH1 EN0/1, LDO0EN
High level input voltage 2
VIH2 ERROR1/2
High level input voltage 3
VIH3 Below pin group
Low level input voltage 1
VIL1 EN0/1, LDO0EN
Low level input voltage 2
VIL2 ERROR1/2
Low level input voltage 3
VIL3 Below pin group
Pin group: SPICSB, SPICLK, SPISDI, WDI, WDENB◆ Digital output
DC characteristics of digital pins are shown in below table.
Parameter
SymbolCondition
High level output voltage
VoH
IoH=2mA, below pin group
Low level output voltage
VoL1
IoL=-2mA, below pin group
Low level output voltage
VoL2
IoL=-2mA, SUSP only
Low level output voltage
VoLr
RSTB pin, IoL=-2mA
RSTB output leakIlkrstb Hi-Z, RSTB pin
Pin group: INTOUT, SPISDO, FSOUT, EXCNT,SUSP(VoH)◆ Switch resistanceParameter
VOUT0SW

SymbolRonsw

Condition
From VIN3V to VOUT0SW◆ Pull up/down resistor
Parameter
SymbolCondition
Pull up resistor
Rpu
SPICSB
Pull down resistor 1
Rpd1
EN0, EN1, LDO0EN
Pull down resistor 2
Rpd2
Below pin group
Pin group: SPICLK, SPISDI, ERROR1/2, WDI, WDENB

MIN
2.5
0.7*VIN3V
0.7*VDDIO
-0.3
-0.3
-0.3

TYP
-

MAX
Unit
VBAT+0.3
VDDIO+0.3 V
VDDIO+0.3
1.0
0.3*VIN3V
V
0.3*VDDIO

MIN
0.8*VDDIO
-

TYP
-

MAX
Unit
V
0.2*VDDIO V
0.13*VDDIO V
0.4
V
10
μA

MIN
-

TYP
-

MAX
8

Unit
Ω

MIN
76
390
76

TYP
100
100

MAX
127
127

Unit
kΩ
kΩ
kΩ

◆ Operating current (VINR and VINPDC1A/B = 12V, No load current on each regulators)
Parameter
SymbolCondition
MIN
TYP
MAX
Unit
Stand by current
Iddoff EN0/1=0 and LDO0EN=01640μA
EN0/1=0 and LDO0EN=1
Operating current 1
Idd1
210
300
μA
Ta=+25°C and VIN3V=3.3V
Operating current 2 *Idd2
EN0=1 or EN1=1
2.7
4.5
mA
Operating current 3 *Idd3
Including trackers’ current
4.9
14.0
mA
* Except external diode leakage current
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RAA270000KFT data sheet

7 Package Information

Fig.7 Package diagram
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RAA270000KFT data sheet

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