APPLICATION NOTESLOC™ TW3801-C1, TW3811- C1 Design Guide

AN1804
Rev. 0.00
November 27, 2012

SLOC™ TW3801-C1, TW3811- C1 Design Guide

AN1804 Rev. 0.00
November 27, 2012

Page 1 of 26

SLOC™ TW3801-C1, TW3811- C1 Design Guide

Table of Contents
Introduction ..................................................................................................................................................................................... 3
SLOC System Operation ................................................................................................................................................................. 3
Hardware Design Guide .................................................................................................................................................................. 4
SLOC Operating Mode Selection ................................................................................................................................................ 4
Ethernet PHY Interface Mode ........................................................................................................................................ 4
SOC(MAC) Interface Mode.............................................................................................................................................. 4
SLOC Pass-Through Mode .............................................................................................................................................. 5
SLOC Downlink/Uplink Throughput Settings ........................................................................................................................... 7
Data Rate Vs Cable Length ......................................................................................................................................................... 8Mode Selection by Pin Strap ...................................................................................................................................................... 9
COAX Pin Application ................................................................................................................................................................. 10
TW3811 CVBS Output Circuit ................................................................................................................................................... 11
Ethernet PHY Interfacing ........................................................................................................................................................... 12
MII Interface with Ethernet PHY .................................................................................................................................. 12
RMII Interface with Ethernet PHY ............................................................................................................................... 13
PHY Address Settings ................................................................................................................................................... 15
Ethernet PHY Reset Application .................................................................................................................................. 15
SOC (CODEC) Chip Interfaces ................................................................................................................................................... 16
MII Interface with SOC .................................................................................................................................................. 16
RMII Interface with SOC ............................................................................................................................................... 16
ESD/EMI Solution ....................................................................................................................................................................... 17
SLOC Firmware .............................................................................................................................................................................. 18
SLOC Performance Check ............................................................................................................................................................ 20
PER (Packet Error Rate) Measurement .................................................................................................................................. 20
Downlink PER ................................................................................................................................................................. 20
Uplink PER ...................................................................................................................................................................... 20
SLOC Signals Evaluation ........................................................................................................................................................... 20
PCB Layout Guide.......................................................................................................................................................................... 21
COAX_OUT and COAX_IN ........................................................................................................................................................... 21
LOAD_DRV (Pin 66) .................................................................................................................................................................... 22
CVBS Input for TW3801 ............................................................................................................................................................ 22
CVBS Output for TW3811 ......................................................................................................................................................... 22Power Distribution ...................................................................................................................................................................... 23
Decoupling Capacitors for Power Pins .................................................................................................................................... 24
Ground Considerations .............................................................................................................................................................. 24
Multi-Channel Design ................................................................................................................................................................. 25

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

Introduction
This application note provides TW3801/TW3811 hardware design and PCB layout guide. It also includes SLOC link flow
control (state machine). For ESD and EMI solution, the guidelines to select the components are provided.

SLOC System Operation
A SLOC system is a pair of TW3801 and TW3811 chips connected via COAX cable. The TW3801 (the “SLOC™
transmitter”) is placed at the IP camera end, and the TW3811 (the “SLOC™ receiver”) is placed at the NVR/DVR end. The
downlink IP packets (typically compressed video data) from the camera are modulated and transmitted “downstream”
with the CVBS signal over the COAX connection. The uplink IP packets (PTZ control signals, etc.) from the NVR are
modulated and transmitted “upstream” through the COAX cable.
The SLOC signals are composed of base-band composite video and modulated downlink and uplink signals. Thesesignals covered a 42MHz bandwidth as shown in Figure 1.

5.4MHz14.75MHz22.75MHz

37.75MHz

40.25MHz

8MHz

2.5MHzDownlink

Uplinkf (MHz)Base-band CVBS

FIGURE 1. SLOC SIGNAL SPECTRUM

Since SLOC is intended to operate with conventional 75Ω COAX cable, the COAX input and output impedances should bematched to the cable impedance to minimize reflection. The COAX_O pin uses a current-mode driver circuit (highimpedance output), and therefore requires a 75Ω resistor to ground to generate the final signal with a 75Ω source
impedance. The COAX_I/O and overall SLOC system configuration are shown in Figure 2.

10µF

10µF

0.1µF

0.1µF

COAX_I
CVBS_I

COAX_I
470µF/10V

COAX cable

COAX_O

COAX_OTW3801

CVBS_O

470µF/10V

75R0

75R0

MII/RMII

TW3811
MII/RMIIFIGURE 2. SLOC COAX I/O CONFIGURATION

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

Hardware Design Guide
SLOC Operating Mode Selection
The SLOC chips can be embedded in an IP Camera/NVR system or used to create “dongle” adapters. Depending on thesystem requirements, the SLOC chip can operate in one of three different modes. The first is the Ethernet PHY interface
mode, which is most often used in a SLOC dongle application. The second is the SOC (System-On-a-Chip, also called MAC)
interface mode, for SLOC-embedded systems. The third is a pass-through mode that directs MII data from the SOC toflow directly through the SLOC IC and into an Ethernet PHY. This mode allows the camera to operate as a traditional IP
camera when not connected to a SLOC receiver.

ETHERNET PHY INTERFACE MODE
The TW38x1 MIIA pins are designed to connect to a Fast Ethernet PHY or Switch (PHY Mode). The MII Tx/Rx clocks are
generated by the PHY chip, and connect to the TW38x1’s TX_CLK/RX_CLK input pins. This mode can be selected by tying
TW38x1 pin 93 (MODE_S3) to ground or by setting register 0x01 bits[4:3] = 00 with register 0x01 bit[0] = 1. A 1.5kΩ
pull-up resistor on MDIO is required in this mode to support the Ethernet PHY link status check. The application diagram
is shown in Figure 3.

MIIA
SLOC COAX I/O

Fast
Ether
PHY

TW38x1
MODE_S3

RJ45

IP CAMOr
NVR

FIGURE 3. ETHERNET PHY INTERFACE MODE FOR DONGLE SOLUTION

SOC(MAC) INTERFACE MODE
This mode is used for SLOC embedded systems. The MIIB pins interface with SOC (System-On-a-Chip, for example a
codec) chips. This mode can be selected by tying pin number 93 (MODE_S3) to 3.3V with a 10kΩ pull-up resistor or by
setting register 0x01 bit[4:3] = 01 with register 0x01 bit[0] = 1. The application diagram is shown in Figure 4.

3.3V

SLOC COAX I/O

TW38x1
MODE_S3

MIIB

SOC
(MAC)

FIGURE 4. SOC INTERFACE MODE FOR EMBEDDED SYSTEM

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SLOC™ TW3801-C1, TW3811- C1 Design Guide
If the SOC (Codec) chip doesn’t provide a TX_ER (Transmit Error) signal, just leave the TX_ER_B (Pin# 26) pin
unconnected. Since the MDC and MDIO management signals are not used in this mode, they should be tied to 3.3V with10kΩ pull-up resistors.

SLOC PASS-THROUGH MODE
Even with a TW3801 SLOC transmitter chip embedded into an IP camera, the camera can still provide a legacy RJ45
Ethernet interface with a minimum of additional components. In this mode, the SLOC IP modulation/demodulation
processes are disabled, and the MII signals are passed between the MII A and MIIB interfaces. The block diagram of a
SLOC-embedded IP camera with this RJ45 pass-through mode is shown in Figure 5.

MIIA
SLOC I/O
to NVR sidewith
TW3811

Fast
Ether
PHY

TW3801
MIIB

CAT5
NVR

ISP/SOC(MAC)

FIGURE 5. SLOC EMBEDDED IP CAMERA DESIGN BLOCK

The MII connections for pass-through mode are shown in Figure 6.
3_3VD

10kΩ

1.5kΩ

MDIO
MDC

SOC (CODEC)

TX_ER
TX_EN
TXD0
TXD1
TXD2
TXD3

TX_CLK
RX_CLK
RX_ER
RX_DV
RXD0
RXD1
RXD2
RXD3

3_3VD

3_3V

10kΩ
330Ω

MDIO
MDC

4
3
26
29
30
31
32
33
37
36
38
39
40
41
44
45

MDIO
MDC

TW3801

LED_0

TX_ER_B
TX_EN_B
TX_D0_B
TX_D1_B
TX_D2_B
TX_D3_B

TX_ER_A
TX_EN_A
TX_D0_A
TX_D1_A
TX_D2_A
TX_D3_A

TX_CLK_B
RX_CLK_B

TX_CLK_A
RX_CLK_A

RX_ER_B
RX_DV_B
RX_D0_B
RX_D1_B
RX_D2_B
RX_D3_B

RX_ER_A
RX_DV_A
RX_D0_A
RX_D1_A
RX_D2_A
RX_D3_A

53

MDIO
MDC
LED

17
14
18
19
20
21

Transmit Enable
Transmit Data 0
Transmit Data 1
Transmit Data 2
Transmit Data 3

25
22Transmit Clock
Receiver Clock

6
5
7
10
11
12

Receiver Error
Receiver Data Valid
Receiver Data 0
Receiver Data 1
Receiver Data 2
Receiver Data 3

MDIO
MDC
TXEN
TXD0
TXD1
TXD2
TXD3
TXC
RXC

Ethernet PHY or
Switch (PHY Mode)

RXER
RXDV
RXD0
RXD1
RXD2
RXD3
CRS
COL

NOTE:
1. LED_0 : MII mode selection
2. Set register 0x01[4:3] = 10 and register 0x01[0] = 1

FIGURE 6. SLOC PASS-THROUGH MODE WITH MII INTERFACE

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SLOC™ TW3801-C1, TW3811- C1 Design Guide
The RMII connections for pass-through mode are shown in Figure 7.

3_3V

330Ω
3_3VD
3_3VD
10kΩ

10kΩ

LED

1.5kΩ

MDIO
MDC

TW3801
MDIO
MDC

4
3

MDIO
MDC

LED_0

53
4.7kΩ

SOC (CODEC)
TX_EN
TXD0
TXD1
RX_ER
RX_DV
RXD0
RXD1
TX_CLK

29
30
31
38
39
40
41

TX_EN_B
TX_D0_B
TX_D1_B

TX_EN_A
TX_D0_A
TX_D1_A

RX_ER_B
RX_DV_B
RX_D0_B
RX_D1_B

RX_ER_A
RX_DV_A
RX_D0_A
RX_D1_A
TX_CLK_A

10kΩ

2
1
2N3906314
18
19Transmit Enable
Transmit Data 0
Transmit Data 1

6
5
7
10

Receive Error
Receive Data Valid
Receive Data 0
Receive Data 1

25

50MHz Reference clock

MDIO
MDC

MDIO
MDC

TXEN
TXD0
TXD1

Ethernet PHY or
Switch (PHY Mode)RXER
CRS_DV
RXD0
RXD1
TXC

NOTE:
1. LED_0 : RMII mode selection
2. Set register 0x01[4:3] = 10 and register 0x01[0] = 1.
3. Set register 0x01[6] = 0 for 50MHz reference clock output from pin #50
FIGURE 7. SLOC PASS-THROUGH MODE WITH RMII INTERFACE

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

SLOC Downlink/Uplink Throughput Settings
SLOC link transmission speed can be selected by the logic level of the MODE_S0 and MODE_S1 external pins, or byregister 0x0A. When register 0x01[0] = 0, link speed is determined by the pins. When register 0x01[0] = 1, link speed isdetermined by register0x0A. By default (since the default setting of register 0x01[0] is 0), the speed after a reset or
power-on is determined by the external pins. The available speeds and settings are shown in Table 1. The speed setting
for the TW3801 determines downlink throughput and the setting for the TW3811 defines uplink throughput. The
recommended settings (in bold) are 36Mbps downstream (for maximum video throughput), and 4Mbps upstream (since
there is very little upstream data, lowering the maximum rate from 11Mbps has no performance impact on an IP
camera, while the lower 4Mbps rate enables slightly longer cable lengths than 11Mbps).
TABLE 1. SLOC LINK DATA RATE SETTINGS

TW3801 (DOWNLINK THROUGHPUT)

TW3811 (UPLINK THROUGHPUT)SPEED

REGISTER 0X0A

EXTERNAL PINSSPEED

REGISTER 0X0A

EXTERNAL PINS

36Mbps0x13

MODE_S0 = 0
MODE_S1 = 0

11Mbps0x13

MODE_S0 = 0
MODE_S1 = 0

32Mbps0x12-

10Mbps0x12-

28Mbps0x11

MODE_S0 = 1
MODE_S1 = 0

9Mbps

0x11

MODE_S0 = 1
MODE_S1 = 0

25Mbps0x0C

MODE_S0 = 0
MODE_S1 = 1

7.5Mbps

0x0C-

23Mbps

0x0B

-

7Mbps

0x0B

-

21Mbps0x0A

MODE_S0 = 1
MODE_S1 = 1

6.5Mbps

0x0A-

19Mbps

0x09

-

6Mbps

0x09

-

14Mbps0x08-

4.5Mbps

0x08-

12Mbps

0x04

-

4Mbps

0x04

MODE_S0 = 0
MODE_S1 = 1

11Mbps0x03-

3.5Mbps

0x03-

10Mbps

0x02

-

3Mbps

0x02

MODE_S0 = 1
MODE_S1 = 1

9Mbps

0x01

-

2.5Mbps

0x01

-

7Mbps

0x00

-

2Mbps

0x00

-

NOTE: Register 0x0A settings are valid and override external pin values when register 0x01[0] = 1.

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

Data Rate Vs Cable Length
Since SLOC™ transmits at higher frequencies than analog video; the maximum cable length is a function of the cablequality and composition. The following tables show examples of cable distance vs. downstream and upstream data rates
for copper-core RG59 and the less-expensive SYV75-3 (64) cable. The SLOC compliance test measures upstream data
rate at 4Mbps, while downstream data rate is 36Mbps for 500m RG59 Belden #543945 cable.
Downstream Upstream
Data Rate Data Rate

RG59 Belden #543945

36Mbps 11Mbps
9Mbps
4Mbps
3Mbps
28Mbps 11Mbps
9Mbps
4Mbps
3Mbps
25Mbps 11Mbps
9Mbps
4Mbps
3Mbps
21Mbps 11Mbps
9Mbps
4Mbps
3Mbps
0

150

300

450

600

750

200
300
Length in Meters

400

500

Length in Meters

SYV75-3 (64)Downstream Upstream
Data Rate Data Rate
36Mbps 11Mbps
9Mbps
4Mbps
3Mbps
28Mbps

11Mbps
9Mbps
4Mbps
3Mbps

25Mbps

11Mbps
9Mbps
4Mbps
3Mbps

21Mbps

11Mbps
9Mbps
4Mbps
3Mbps
0

VENDOR
Shenzhen
Shuangying Cable Co.

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100

STYLE

CONDUCTOR
NO./MM

DIAMETER IN
INSULATION (mm)OUTER
CONDUCTOR
BRAIDING

STANDARDCOMPLIANCE

SYV75-3 (3C-2V)

Bare Copper 1/0.5

364

GB/T14864-93

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

Mode Selection by Pin Strap
For stand-alone operation without a microcontroller, the critical mode selections can be set with the external pins. After
power-on or after a hardware reset (pin number 98 is de-asserted), the status of these pins is latched to set the operating
modes. This mode table is valid with register 0x01[0] = 0 (default value, a safe assumption if there is no microcontroller).
TABLE 2. STRAPPING PINSFUNCTIONPIN NAMESPIN#PIN TYPEDESCRIPTION-SLOC Mode

MODE_S393

Input

Operatingmode

MODE_S2

92

Input

MODE_S1

91

Input

MODE_S088

Input

SLOC datatransmission speed-Low: MIIA connection mode for Ethernet PHY chipinterface. The TX_CLK and RX_CLK are input
High: MIIB connection mode for SOC (Codec) chipinterface. The TX_CLK and RX_CLK are output
TW3801: tie to GND
TW3811: tie to 3.3V with 4.7kΩ

TW3801: determine downlink (IP CAM -> NVR) speed
TW3811: determine uplink (NVR  IP CAM) speed- For speed details, refer to “SLOC Downlink/UplinkThroughput Settings” on page 7.
The address is determined as follows:

A056

InputPD

Device I2C
address
A1

MII / RMII

LED_0

57

53

InputPD

IPU/O

0

0
-

1

1

1

A1

A0

R/W

A1 = 0 and A0 = 0: 0x38
A1 = 0 and A0 = 1: 0x3A
A1 = 1 and A0 = 0: 0x3C
A1 = 1 and A0 = 1: 0x3E

Pin strap- High(>2.0V): MII interface mode (Default with pin open)- Low(<0.8V): RMII interface mode
Normal operation as output pin- SLOC link LED indicator. A low output indicates SLOC linkconnected

NOTES:
1. IPU/O: Input with 57kΩ pull-up resistor/output.
2. InputPD: Input with 57kΩ pull-down resistor.

The LED_0 pin serves two functions: MII mode-strapping function (only after power-on or a RESET) and SLOC linkindicator. Since the LED indicator is active low, and there is a pull-down resistor inside the pin, one of the schematics ofFigure 8 should be used to set the initial voltage (depending on whether you need a logic high or logic low at start-up).

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

MII mode(pin high at reset)

RMII mode
FIGURE 8. LED_0 PIN APPLICATIONCOAX Pin Application
For both the TW3801 and the TW3811, the SLOC signal is transmitted through the COAX_O pin and received throughCOAX_I.
C3
10µF
COAX_IN

78

SLOC IN/OUT
COAX_I

C8
100nF

CON2
BNC
5 4

COAX_O
LOAD_DRV

TW38x1C1

67
66+

COAX_OUTDRLOADC9470µF/16
V
R13
75Ω

R14
75Ω

1
3 2

D1
ESD

L32
150nH

FIGURE 9. SLOC COAX I/O CIRCUIT

Since the SLOC signal includes base-band CVBS and must drive 75Ω, a 470µF AC-coupling capacitor is required to passfrequencies down to 50Hz (PAL vertical sync) and prevent a sagging. However, large-value electrolytics do not have very
good high-frequency performance, so a 100nF is placed in parallel to accurately pass the 12MHz to 42MHz IP signal.
Adding the 150nH inductor is recommended for better return loss performance. In the receive path, a 10µF AC-coupling
capacitor adequately passes both the video and IP frequencies into the higher-impedance COAX_I pin.

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

TW3811 CVBS Output Circuit
To drive the CVBS signal onto a 75Ω cable, the video amplitude should be 2VP-P with a 75Ω series source terminating
resistor. Since the signal from the TW3811 is inverted and ≈0.83 VP-P, an inverting amplifier with x2.4 gain is required.
The low-cost solution with clamping circuit is shown in Figure 10. With this circuit, brief brightness changes may be seen
for mostly-black to mostly-white (and vice-versa) scene transitions.

AVD_A

24kΩ

R6

68
CVBS_OUT

R10
DNP

C5
47µF/10
V

CON1
2
10kΩ

R3

5 4

4 -

+

1

1

3 +
AVD_A

SOT23-5
EL8101
U13

5
R7
DNP

D7
BAT54HT1G

R4
4.7kΩ

R8
100Ω

R5
1.5kΩ

C7
4.7µF

C10
470µF /16V

R1
75Ω

3 2

AVD_A

TW3811-C1
C31
100nF

FIGURE 10. LOW-COST CVBS OUTPUT CIRCUIT

The best solution is to use a video driver with integrated DC-restore, as shown in Figure 11.

R6

CVBS_OUT

68

C547µF/10V

R3
10kΩ

12kΩ

2
4 1

AVD_A
C57
0.1µF

U10
ISL59110
1

3 +
AVD_A
5
R4
10kΩ

U13
EL8101
SOT23-5

2
3

IN+
GND
SAG

VS+
EN
OUT

6

C7
0.1µF

5 4

4

C51 47µF
C1206
R5
10kΩ

CON1

5

AVD_A

TW3811-C1

C55
0.1uF

1
C52
100µF
C1206

R13
75Ω

3 2

C31
0.1µF

FIGURE 11. BETTER CVBS OUTPUT CIRCUITAN1804 Rev. 0.00
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SLOC™ TW3801-C1, TW3811- C1 Design Guide

Ethernet PHY Interfacing
MII INTERFACE WITH ETHERNET PHY
The MII interface is selected if pin 53 is high at start-up (as described in Table 2), or if register 0x01[5] = 1 and register0x01[0] = 1. The PHY interface mode is determined by the logic level of pin 93 or register 0x01[4:3] = 00 when register0x01[0] = 1. The MII pins connect to the Ethernet PHY, as shown in Figure 12.
1.5kΩ
MDIO
MDC

TW38x1

RX_DV_A
RX_ER_A
RX_D0_A
RX_D1_A
RX_D2_A
RX_D3_A
RX_CLK_A
TX_CLK_A
TX_ER_A
TX_EN_A
TX_D0_A
TX_D1_A
TX_D2_A
TX_D3_A

3_3V

4
3

MDIO
MDC

5
6
7
10
11
12

Receiver Data Valid
Receiver Error
Receiver Data 0
Receiver Data 1
Receiver Data 2
Receiver Data 3

22
25

Receiver ClockTransmit Clock

17
14
18
19
20
21

Transmit Enable
Transmit Data 0
Transmit Data 1
Transmit Data 2
Transmit Data 3
3_3V

LED_0
MODE_S3

53
93
LED

RXDV
RXER
RXD0
RXD1
RXD2
RXD3

Ethernet PHY or

RXC
TXC

Switch (PHY Mode)

TXEN
TXD0
TXD1
TXD2
TXD3
CRS
COL

330Ω

NOTE:
1. LED_0 : MII mode selection and SLOC link indicator
2. MODE_S3: Ethernet PHY interface mode
FIGURE 12. MII INTERFACE WITH ETHERNET PHY

If the PHY chip doesn’t provide the TX_ER pin, leave pin 17 (TX_ER_A) unconnected. The SLOC MII interface doesn’t
support the CRS (carrier sense) and COL (collision detect) signals; refer to the datasheet for the PHY for instructions onwhat to do with those pins.

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

RMII INTERFACE WITH ETHERNET PHY
Some multi-channel PHY chips use the RMII interface instead of MII. RMII can be selected by keeping pin 53 (LED_0) low
at power-on/after reset or by setting register 0x01[5] = 0 with register 0x01[0] = 1. There are two different designs
depending on the source of the 50MHz RMII reference clock. If the 50MHz reference clock is coming from the Ethernet
PHY, connect as shown in Figure 13. Register 0x01[6] must be set to 1 to use external PHY clock (that is its default
setting).
1.5kΩ
MDIO
MDC
RX_DV_A
RX_ER_A
RX_D0_A
RX_D1_A

4
3
5
6
7
10

TW38x1 TX_CLK_A 25
TX_EN_A
TX_D0_A
TX_D1_A

3_3V

14
18
19

MDIO
MDC
Receive Data Valid
Receive Error
Receive Data 0
Receive Data 1

CRS_DV
RXER
RXD0
RXD1

50MHz Clock Reference
Transmit Enable
Transmit Data 0
Transmit Data 1

TXC

Ethernet PHY or

TXEN
TXD0
TXD1

Switch (PHY Mode)

3_3V

330Ω

LED
MODE_S3

93
2

LED_0

10kΩ

53

1
2N3906

4.7kΩ

3

NOTE:
1. LED_0 : RMII mode selection and SLOC link indicator
2. MODE_S3: Ethernet PHY interface mode
FIGURE 13. RMII INTERFACE WITH 50MHz REFERENCE CLOCK GENERATED BY PHY

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SLOC™ TW3801-C1, TW3811- C1 Design Guide
If the 50MHz reference clock is not provided from the Ethernet PHY, the SLOC chip can supply the clock from pin 50(TEST_IO/CLK50M) with register 0x01[6] = 0. The RMII connections with 50MHz clock from SLOC chip are shown in
Figure 14.
1.5kΩ

MDIO
MDC

TW38x1

RX_DV_A
RX_ER_A
RX_D0_A
RX_D1_A

TX_CLK_A
TEST_IO/CLK50M
TX_EN_A
TX_D0_A
TX_D1_A

3_3V

4
3

MDIO
MDC

5
6
7
10

Receive Data Valid
Receive Error
Receive Data 0
Receive Data 1

25
50

50MHz Clock Reference

14
18
19

Transmit Enable
Transmit Data 0
Transmit Data 1

CRS_DV
RXER
RXD0
RXD1
TXC
TXEN
TXD0
TXD1

Ethernet PHY or
Switch (PHY Mode)

3_3V

330Ω

MODE_S3

LED

93

2
LED_0

10kΩ

53

1
2N3906

4.7kΩ

3

NOTE:
1. LED_0 : RMII mode selection and SLOC link indicator
2. MODE_S3: Ethernet PHY interface mode
3. Set register 0x01[6] = 0 for 50MHz reference clock output from pin #50
FIGURE 14. RMII INTERFACE WITH 50MHz REFERENCE CLOCK GENERATED BY SLOC

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

PHY ADDRESS SETTINGS
When SLOC is in the PHY interface mode, the internal SLOC link state machine periodically checks the PHY link-status
register via the MDC/MDIO management signals. In the MDIO read sequence, the Ethernet PHY address is required.
SLOC generates the address of the PHY chip as a function of the SLOC chip’s I2C address and the value in register 0x1E,
bits[6:4] as follows:
Ethernet PHY address = SLOC register 0x1E bits[6:4] + logic level of Pins 57 and 56
Table 3 shows the first 8 of the 32 possible PHY addresses. The PHY address should be set per the PHY’s datasheet tomatch the SLOC PHY address.
TABLE 3. ETHERNET PHY ADDRESSETHERNET PHY ADDRESSREG0X1E BIT 6-4

PIN # 57

PIN# 56

0000

0 (Low)

0 (Low)

1000

0 (Low)

1 (High)

2000

1 (High)0 (Low)

3000

1 (High)

1 (High)

4001

0 (Low)

0 (Low)

5001

0 (Low)

1 (High)

6001

1 (High)0 (Low)

7001

1 (High)

1 (High)

8010

0 (Low)

0 (Low)

…

…

…

…

ETHERNET PHY RESET APPLICATION
In early revisions of the SLOC IC, SLOC controlled the reset of the Ethernet PHY chip through pin 13. The TW3801C1 andTW3811C1 do not need to control the PHY reset. Pin 13 can be left disconnected.

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

SOC (CODEC) Chip Interfaces
MII INTERFACE WITH SOC
The MII interface mode is entered by taking pin 53 high during reset/power-on (see Figure 8) or setting register0x01[5] = 1 with register 0x01[0] = 1. The SOC (CODEC) interface mode is set by tying pin 93 (MODE_S3) to 3.3V orsetting register 0x01[4:3] = 01 with register 0x01[0] = 1. The MII connections to the SOC should use the MIIB pins, as
shown in Figure 15. In this mode, the management interface (MDC/MDIO) is not required and the pins should be tiedhigh to 3.3V with 10kΩ resistors.

3_3VD
4
3

MDIO
MDC

TW38x1

TX_ER_B
TX_EN_B
TX_D0_B
TX_D1_B
TX_D2_B
TX_D3_B
TX_CLK_B
RX_CLK_B
RX_ER_B
RX_DV_B
RX_D0_B
RX_D1_B
RX_D2_B
RX_D3_B

10kΩ

26
29
30
31
32
33

10kΩ
Transmit Error
Transmit Enable
Transmit Data 0
Transmit Data 1
Transmit Data 2
Transmit Data 3

37
36Transmit Clock
Receiver Clock

38
39
40
41
44
45

Receiver Error
Receiver Data Valid
Receiver Data 0
Receiver Data 1
Receiver Data 2
Receiver Data 3

TX_ER
TX_EN
TXD0
TXD1
TXD2
TXD3
TX_CLK
RX_CLKSOC (CODEC)

RX_ER
RX_DV
RXD0
RXD1
RXD2
RXD3

3_3V
LED_0
MODE_S3

53

LED

330Ω

93
4.7kΩ

NOTE:
1. LED_0 : MII mode selection and SLOC link indicator
2. MODE_S3: SOC (CODEC) interface mode
FIGURE 15. MII INTERFACE WITH SOC (CODEC) MODE

RMII INTERFACE WITH SOC
RMII mode is entered by taking pin 53 low during reset/power-on (see Figure 8) or setting register 0x01[5] = 0 withregister 0x01[0] = 1. Since a SOC (CODEC) chip typically doesn’t provide 50MHz reference clock, the 50MHz clock output
from pin 50 should be enabled with register 0x01[6] = 0. In this application, the 50MHz clock should also be sent to the
MIIA TX_CLK (pin 25) as shown in Figure 16.

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SLOC™ TW3801-C1, TW3811- C1 Design Guide
3_3VD
MDIO
MDC
TX_EN_B
TX_D0_B
TX_D1_B
TX_CLK_A
TEST_IO/CLK50M

TW38x1

RX_ER_B
RX_DV_B
RX_D0_B
RX_D1_B

10kΩ

4
3

10kΩ
Transmit Enable
Transmit Data 0
Transmit Data 1

29
30
31

TX_EN
TXD0
TXD1

25
50

50MHz Clock Reference

38
39
40
41

Receiver Error
Receiver Data Valid
Receiver Data 0
Receiver Data 1

TX_CLK
RX_ER
RX_DV
RXD0
RXD1

SOC (CODEC)

3_3V

330

3_3V
MODE_S3

93

LED

4.7kΩ
2

LED_0

10kΩ

53

1
2N3906

4.7kΩ

3

NOTE:
1. LED_0 : RMII mode selection and SLOC link indicator
2. MODE_S3: SOC(CODEC) interface mode
3. Set register 0x01[6] = 0 for 50MHz reference clock output from pin 50
FIGURE 16. RMII INTERFACE WITH SOC (CODEC) MODE

ESD/EMI Solution
The SLOC chip will withstand electrostatic discharge up to 2kV (human body model). For higher protection on the
COAX_I/O pins, additional ESD protection can be added, as shown Figure 9. Since the SLOC signal range extends to over
40MHz, low capacitance ESD devices are required to avoid signal degradation. The capacitance of the devices should notexceed 3pF. Two ESD devices have been tested and verified to work with SLOC: EZAEG3A (Panasonic)
 BV03CL (Bencent, China)
If EMI reduction is needed, an EMI filter can be placed on the SLOC_I/O port as well. When choosing any EMI/EMC
components, check the attenuation vs. frequency characteristics, and look for frequency-dependent impedance. The
SLOC signal should not be attenuated at 50MHz and below. To verify proper operation in COAX_IO path, contact Intersil
application team.

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

SLOC Firmware
The TW3801 and TW3811 have been designed to work stand-alone (without an external micro-controller) in many
applications. The default register settings are optimized for stand-alone operation, with external pins available to change
the most popular settings.
However, it is possible to program additional registers inside the TW3801 and TW3811 using the I2C interface, including
override the settings set by the external pins. Table 4 (TW3801) and Table 5 (TW3811) explain how to change theinterface mode via software (vs the hardware pins as described in “SLOC Downlink/Uplink Throughput Settings” onpage 7 and “Data Rate Vs Cable Length” on page 8). After the new interface mode is programmed, the device must be“soft” reset by writing a 1 to register 0 bit 0 before the new interface mode will be used. Please refer to the datasheet for
additional information on user I2C registers.
TABLE 4. TW3801 DEVICE

INTERFACEOPERATING MODE

Ethernet PHY interface Mode

Register 0x01 = 0x61
Register 0x0A = 0x13: required manual speed setting(e.g. 36Mbps)
Register 0x00 = 0x01: soft reset

SOC interface Mode

Register 0x01 = 0x69
Same settings are required in Reg0x0A/0x00

Pass-Through Mode

Register 0x01 = 0x71
Same settings are required in Reg0x0A/0x00

Ethernet PHY interface Mode

Register 0x01 = 0x01
Same settings are required in Reg0x0A/0x00

SOC interface Mode

Register 0x01 = 0x09
Same settings are required in Reg0x0A/0x00

Pass-Through Mode

Register 0x01 = 0x11
Same settings are required in Reg0x0A/0x00

Ethernet PHY interface Mode

Register 0x01 = 0x41
Same settings are required in Reg0x0A/0x00

SOC interface Mode

Register 0x01 = 0x49
Same settings are required in Reg0x0A/0x00

Pass-Through Mode

Register 0x01 = 0x51
Same settings are required in Reg0x0A/0x00

MII interface

RMII interface withinternal 50MHz clock

RMII interface withexternal 50MHz clock

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I2C SETTINGS PROCEDURE

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SLOC™ TW3801-C1, TW3811- C1 Design Guide
TABLE 5. TW3811 DEVICE

INTERFACEOPERATING MODEI2C SETTINGS PROCEDURE

Ethernet PHY interface Mode

Register 0x01 = 0x63
Register 0x0A = 0x03: required manual speed setting (e.g.
3Mbps)
Register 0x00 = 0x01: soft reset

SOC interface Mode

Register 0x01 = 0x6B
Same settings are required in Reg0x0A/0x00

Pass-Through Mode

Register 0x01 = 0x73
Same settings are required in Reg0x0A/0x00

Ethernet PHY interface Mode

Register 0x01 = 0x03
Same settings are required in Reg0x0A/0x00

SOC interface Mode

Register 0x01 = 0x0B
Same settings are required in Reg0x0A/0x00

Pass-Through Mode

Register 0x01 = 0x13
Same settings are required in Reg0x0A/0x00

Ethernet PHY interface Mode

Register 0x01 = 0x43
Same settings are required in Reg0x0A/0x00

SOC interface Mode

Register 0x01 = 0x4B
Same settings are required in Reg0x0A/0x00

Pass-Through Mode

Register 0x01 = 0x53
Same settings are required in Reg0x0A/0x00

MII interface

RMII interface withinternal 50MHz clock

RMII interface withexternal 50MHz clock

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

SLOC Performance CheckPER (Packet Error Rate) Measurement
The SLOC chip can measure PER to check for any errors which may have occurred across the COAX link.

DOWNLINK PER
The PER should be measured in TW3811 with below register settings after the SLOC link is completed (The LED from
LED_0 Pin# 53 is turned on or register 0x44 bit[5] = 1).
1. Write register 0x27 to 0x00 (Reset the PER measurement)
2. Write packet counter number into register 0x27. The number indicates 65536 packets per value. If 0x05 in theregister is written, a total 327680 (5 x 65536) packets are measured.
3. Monitor register 0x43 bit[0] if it is 1. If it is 0, the error measurement is not completed.
4. After confirmed register 0x43 bit[0] = 1, read register 0x42 to 0x40. The return values of the registers are thepacket error number.
 Register 0x40[7:0] = Error count[7:0] Register 0x41[7:0] = Error count[15:8]
 Register 0x42[7:0] = Error count[23:16]
5. The values should be all zero. If not, the SLOC link generates an error and some video data will be lost.

UPLINK PER
The PER should be measured in TW3801 after the SLOC link is completed. The process to evaluate the error packets issame as downlink PER one.

SLOC Signals Evaluation
For SLOC signal evaluation, refer to the SLOC compliance document.

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

PCB Layout Guide
COAX_OUT and COAX_IN
The SLOC ICs generate a wide-band multiplexed signal consisting of two modulated signals and base-band CVBS
extending over a 0 to 42MHz range. It is important to route the signal traces carefully to minimize distortion andcrosstalk, and achieve maximum COAX cable length.
Routing advice:Place components (coupling capacitors and load resistor) so that the traces are as straight and short as possible.



Avoid right-angle bends in the traces to minimize signal reflection. Use a 45° design rule.

Traces should have a characteristic impedance of 75Ω impedance. Other than 75Ω will increase reflections andaffect signal quality.



Breaks in the ground plane can also cause impedance mismatch – make sure all high speed signals run over aconstant ground plane.



Avoid vias – they also introduce impedance mismatch.



Avoid routing the traces near digital signals and clock traces.

To avoid unwanted coupling between COAX_OUT and COAX_IN traces, keep the spacing as far apart as possible
until they are combined (after the coupling capacitors)

COAX_INWIDENSPACING

COAX_OUT

Don’t make a “T” as shown below. This degrades return loss and may reduce maximum COAX cable length.

DON’T MAKE BRANCH WITHIN TRACEBAD EXAMPLE

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

LOAD_DRV (Pin 66)
The signal on this pin generates the output current that is mirrored onto the COAX_OUT pin. If the LOAD_DRV signal
couples into the COAX_OUT signal, SLOC performance can be degraded.
Place the 75Ω LOAD_DRV resistor on the bottom side of the PCB and route the trace in the opposite direction of the
COAX_OUT trace. This will minimize interference between both signals.

Place the resistor as closely to the pin as possible, as shown below.

PLACE THE RESISTOR ON
BOTTOM OF PCB

CVBS Input for TW3801


Place the 75Ω termination resistor as closely as possible to the TW3801 and use a ceramic AC-coupling capacitor tominimize reflection caused by impedance mismatch.



Avoid routing any digital, COAX_OUT, or COAX_IN signals near the CVBS_IN trace (even if CVBS_IN runs on adifferent PCB layer).

CVBS Output for TW3811
CVBS_OUT (pin 68) is located between COAX_OUT and COAX_IN, but should be as isolated from both COAX_OUT and
COAX_IN as possible.
Route the trace in a perpendicular direction to COAX_OUT and COAX_IN on a different layer to reduce cross-coupling
effects each other.

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

Power Distribution
The SLOC ICs require two regulated supply voltages: 1.8V for digital core and 3.3V for analog and digital I/O. Since the
3.3V for analog and digital I/O usually comes from the same regulator, the power traces (or planes) should be designed
to minimize the common impedance. Also, the spacing between the digital and analog power traces (or plane) should beenough to reduce unwanted coupling (25mils or more).
COMMON
IMPEDANCEFERRITE
BEAD

3.3V
REGU.

TW38x1

DIGITAL I/O 3.3V

ANALOG 3.3V

POOR EXAMPLEMINIMIZECOMMON
IMPEDANCEFERRITE
BEAD

3.3V
REGU.

TW38x1

DIGITAL I/O 3.3V

BETTER EXAMPLE

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ANALOG 3.3V
TAKE ENOUGHSPACE BETWEENPOWER PLANES

Page 23 of 26

SLOC™ TW3801-C1, TW3811- C1 Design Guide

Decoupling Capacitors for Power Pins
All power pins should have a 0.1µF capacitor decoupling on their supply lines, with the capacitors placed as close to the
VDD and analog power pins as possible. When power is supplied through a via, avoid placing the via between thecapacitor and the power pin. Current should flow from power plane (trace) -> decoupling capacitor -> power pin, as shown
below.

DECOUPLING CAPACITOR

TW3801/11

CLOSE

Ground Considerations
Intersil recommends a single ground under the TW3801/TW3811 to avoid ground potential differences between analog
and digital ground pins. However, it is also important to prevent the ground current from one source (such as the crystal
oscillator) to couple into the ground current of another group (i.e. analog). To satisfy both requirements, one technique isto partially split the GND plane around a noise source to direct the current. For example:

SPLIT GND ABOVENOISE SOURCESINGLE GND
UNDER CHIP

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

Multi-Channel Design
For a multi-channel (NVR. DVR, etc.) SLOC design, additional steps should be taken to achieve the best performance. It is
important to avoid coupling not only between up- and down-link signals, but also between each channel. Separate powerand ground planes between each channel, joined together at the common point (in this case the switch) are necessary.

Ether
PHY

TW3811

DON’T USECOMMON GROUNDBETWEEN
CHANNELSWIDENSPACINGBETWEEN
EACH CHANNELSLOC SIGNALS

Ether
PHY

TW3811

SwitchGROUND…
MULTI CHANNEL GROUND PLANE

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SLOC™ TW3801-C1, TW3811- C1 Design Guide

REGULATORFERRITEBEAD

TW3811Ether
PHY

SWITCH

TW3811Ether
PHY

TAKE ENOUGH GAP BETWEENPOWER PLANES TO MINIMIZE THE
COUPLING
MULTI CHANNEL POWER PLANE

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