Timing Fabric forCommunications Equipment
CLOCKS AND TIMING|INTERFACE AND CONNECTIVITY|MEMORY AND LOGIC|POWER MANAGEMENT

Backplane
Timing Bus
82V2082

Timing Card 1 (active)

ActiveClockOutput82P33731

19.44 MHzT1/E1/J1
Dual LIU
From
BITS-1/SSU

RF PRODUCTS

Line Card 1
8T49N286

DPLL1
DPLL2

Rx recovered ETH CKTx ETH CK

10GEthernet
PHY

T0 DPLL
T4 DPLLTo
BITS/SSU

82V2082|SETS PLL

Timing Card 2 (stby)

T1/E1/J1
Dual LIU
From
BITS-1/SSU
To
BITS/SSU

82P33731

Line Card 1
Stand By
Clock
Output19.44 MHz8T49N286

DPLL1
DPLL2

Rx recovered ETH CKTx ETH CK10GEthernet
PHYT0 DPLL
T4 DPLL

SETS PLL

Switch Fabric and Timing Card, 2 per box

Figure 1 - Timing Fabric Architecture - Timing Cards and Line Cards

IDT LINE CARD SOLUTIONS:Line Card PLL Features• Dual PLL chip: one can be used for the transmit
path and the other for the receive path
• Programmable DPLL bandwidth• Supports automatic hitless reference switching• Generates output clocks for Synchronous Ethernet,SONET, SDH, BITS, GPS, 3G and GSM components• Available in QFN, lead-free packages
Jitter Attenuator Features• FemtoClock® product is a frequency multiplierand jitter attenuator component that generates
low jitter Ethernet clocks and can easily meet
10 Gigabit Ethernet requirements• Optimized for 10G Ethernet jitter attenuation• Attenuates the phase jitter of the input clockby using a low-cost pullable fundamental mode
VCXO crystal• Available in QFN lead-free packages
IDT TIMING CARD SOLUTIONSIDT SETS PLL Features• Up to 14 total inputs and 14 outputs• IEEE 1588 Support (External DCO Control)• 2 independent DPLL + APLL paths− T0 path for node timing synchronization− T4 path for equipment synchronization• Frequency Range: 1 Hz to 650 MHz• Phase noise <1 ps RMS (12 kHz to 20 MHz)ARCHITECTURE OVERVIEW
Communication equipment requires synchronization to transport multiple services (voice, data andvideo) over Carrier networks. The timing fabric, as illustrated in Figure 1 and Figure 2, enables equipment
such as routers, multi-service switching platforms, PON (Passive Optical Network) and DSLAM(Digital Subscriber Line Access Multiplexer), to meet the stringent synchronization requirements ofcommunication networks.
The architecture in Figure 1 segments the timing fabric into 2 major elements: timing cards and linecards. On the timing cards, the SETS PLLs are primarily responsible for compliance with synchronization
standards. The T1/E1 LIUs receive external BITS/SSU references for the T0 DPLLs which generate
standards compliant synchronous clocks and distribute them to the backplane for the line cards.
Recovered clocks from the line card PHYs are used as references by the T4 DPLLs which rate convert
them for the T1/E1 LIU transmitters that provide line references to the external BITS/SSU. On the linecards DPLLs select a backplane reference from one of the timing cards, the reference is rate converted
and jitter attenuated to meet the needs of the specific PHYs used on these cards. Depending on thenumber of PHY reference clocks required on each line card a discrete fan-out buffer may also beneeded. Recovered clocks from line card PHYs are rate converted to a backplane frequency (8 kHz,19.44 MHz, or 25 MHz) and sent to the backplane for the T4 DPLLs on the timing cards.
The architecture in Figure 2 has the timing fabric in one up-link transmission card. Both the traditional
timing card and line card functionality are combined into one card. The recovered clock from the PHY issent to the SETS PLL for filtering, frequency translation and generation of backplane clocks. The clock
generated by the SETS PLL used as a transmitting clock for the PHY + Framer.
As the only supplier with all of the different timing components to provide complete solutions, IDT is
uniquely positioned to meet the needs of communication equipment suppliers and offer compelling
solutions for all timing fabric architectures.
• Standards compliant SETS PLLs (EEC, PEC-S-F*, SEC, ST3/SMC [ITU-T G.8263, G.8262,G.813 & Telcordia GR-253-CORE, GR-1244-CORE])• Standards compliant SMU PLLs (independent SETS PLL plus T-BC, T-TSC [ITU-T G.8273.2] PLL)
• T1/E1 Dual LIUs
• Line card PLLs
• Jitter attenuators and frequency translators• Differential fanout buffers with low additive RMS phase jitter• Backplane interface / translators (as needed)* With supporting 1588 filtering algorithm software

IDT | INTEGRATED DEVICE TECHNOLOGY

TIMING FABRIC FOR COMMUNICATIONS EQUIPMENT OVERVIEW1

Timing Fabric for Communications Equipment®

CLOCKS AND TIMING|INTERFACE AND CONNECTIVITY||MEMORY AND LOGIC|POWER MANAGEMENT

RF PRODUCTS

Clk Output

IDT T1/E1 LIU Features• Dual and Single channel LIU devices available• Supports Hitless Protection Switching for 1+1
protection without external relays• Receiver sensitivity exceeds -36 db @ 772 kHz
and -43 dB @ 1024 kHz• Programmable T1/E1/J1 switchability allows
one bill of material for any line condition• Loss of signal (LOS) and Alarm Indication
Signal (AIS) detection• JTAG interface• Available in TQFG or FPBGA lead-free packages

SETS PLLDSL or PON Line Card

Up-link Transmission Card

82P33731

Rx ClkDigital
PLL Core

DSL or PON Line Card

PHY +Framer

Tx ClkDSL or PON Line Card

Up-link Transmission Card, 1 to 2 per box

Figure 2 - Timing Fabric Architecture (Up-link Transmission Card)Line Card Components
PartNumber

Product Type

Outputs & Types

Output Frequencies(MHz)

Inputs & Type

Phase Jitter Typ
RMS (ps)

Pkg.
Dimensions

8T49N241FemtoClock® NG Universal
Frequency Translator

4 HCSL, LVCMOS,LVDS, LVPECL”

0.008 to 1000

2 HCSL, LVCMOS, LVDS,LVHSTL, LVPECL, LVTTL

0.35

6.0 x 6.0 x 0.9

8T49N242

FemtoClock NG Universal
Frequency Translator

4 HCSL, LVCMOS,LVDS, LVPECL

0.008 to 1000

2 HCSL, LVCMOS, LVDS,LVHSTL, LVPECL, LVTTL”

0.35

6.0 x 6.0 x 0.9

8T49N285

FemtoClock NG Universal
Frequency Translator(2-in/1-PLL/8-out)

8 HCSL, LVCMOS,LVDS, LVPECL

0.008 to 1000

2 HCSL, LVCMOS, LVDS,LVHSTL, LVPECL

0.28

8.0 x 8.0 x 0.85

8T49N286

FemtoClock NG Universal
Frequency Translator(4-in/2-PLL/8-out)

8 HCSL, LVCMOS,LVDS, LVPECL

0.008 to 1000

4 HCSL, LVCMOS, LVDS,LVHSTL, LVPECL, LVTTL

0.28

10.0 x 10.0 x 1

8T49N287

FemtoClock NG Universal
Frequency Translator(2-in/2-PLL/8-out)

8 HCSL, LVCMOS,LVDS, LVPECL

0.008 to 1000

2 HCSL, LVCMOS, LVDS,LVHSTL, LVPECL, LVTTL

0.28

8.0 x 8.0 x 0.85

8V89308i

Jitter Attenuator &FemtoClock Multiplier

2 LVPECL

25.0 to 156.25

1 LVDS, LVPECL

0.223

5.0 x 5.0 x 1

Outputs
Diff.
(#)
Outputs

Timing Card/Up-link Transmission Card Component
PartNumber

Product TypeClock Support

82P33714

Synchronous
Equipment
Timing Source
for Synchronous
Ethernet

G.813 (SEC), G.8262(EEC), GR-253-CORE(SONET ST3/SMC),
GR-1244-CORE (ST3/ST4/ST4E)

82P33731

Synchronous
Equipment
Timing Sourcefor 10G to 40G
Synchronous
Ethernet

G.813 (SEC), G.8262(EEC), GR-253-CORE(SONET ST3/SMC),
GR-1244-CORE (ST3/ST4/ST4E)

Channels Inputs Diff.
(#)(#)
Inputs22614

Input Freq.
Range Type

Output Freq.
Range Type

Phase Jitter
Typ RMS (ps)4

1 Hz to 650 MHz

1 Hz to 650 MHz

0.56

124

6

1 Hz to 650 MHz, 1 Hz to 650 MHz,Composite
Composite
Clock
Clock
(G.703 64 kbps)(G.703 64 kbps)

0.23

146To request samples, download documentation, or learn more, visit: idt.com/go/sync
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating
parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particularpurpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of anIDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names,logos and designs, are the property of IDT or their respective third party owners. © Copyright 2015. All rights reserved.

OV_TIMINGFABRIC_REVB_1215

IDT | INTEGRATED DEVICE TECHNOLOGY

TIMING FABRIC FOR COMMUNICATIONS EQUIPMENT OVERVIEW 2