R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

PRELIMINARY DATASHEET

Preliminary Datasheet

R2A25110KSPIntelligent Power Device for IGBT Drive with Micro Isolator
1. Description
The R2A25110KSP device is an intelligent power device for IGBT gate-drive in the high voltage inverter
application. The Micro Isolator with the coreless transformer structure is adopted for data transfer withhigh voltage isolation between the primary circuit (MCU side) and the secondary circuit (IGBT side).
This device contains IGBT gate drive circuit, Miller clamp circuit, soft turn-off circuit as well as several
types of protection circuits such as IGBT temperature detection. This device also supports driving parallel
IGBTs.

1.1. Features• On-chip Micro Isolator (isolated circuit)High voltage isolation: 2500VRMS➢ High Common Mode Rejection (CMR): over 35kV/us• High output gate drive circuit➢ Gate drive output resistance: 1.0 ohm max (IGBT parallel connection supported)➢ On-chip active Miller clamp function➢ On-chip soft turn-off function• Various on-chip protection circuits➢ IGBT emitter current detection circuit: 2 channels
Over current detection (threshold voltage: 0.25 V typ.), short circuit detection(threshold voltage: 0.5 V typ.)Over current detection function can be enabled/disabled (SEL pin)
➢ IGBT temperature detection circuit: 2 channels➢ On-chip under voltage lockout circuit
VCC1 (5 V system): 4.1 V typ.
VCC2 (15 V system): 10 V typ.
➢ On-chip over temperature protection circuit (200 degC)➢ FAULT feedback
Adjustable FAULT hold time with the external capacitor• Operating temperature: - 40 to 125 degC (junction temperature: 150 degC max)
• On-chip 5 V regulator

1.2. Applications• Main inverters for EV/HEV in automotive applications• Converters for EV/HEV in automotive applications• Inverters and converters for industrial instruments, etc.

Note: The information contained in this document is the one that was obtained when the document wasissued, and may be subject to change.

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2. Block Diagram

Figure 1: Block Diagram

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3. Pin Arrangement

Secondary(IGBT Side)

Primary(MCU Side)

Figure 2: SSOP48 (Top View)

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Table 1: Pin List (1/2)

1

GND2

Referencepin－－

Secondary GND

2
3

CS1
CS2

GND2
GND2

－
－

Emitter current detection input (ch1)
Emitter current detection input (ch2)

4
5

VCC2
SOFT

－
－

Secondary power supply input (15 V typ.)Soft turn-off output

6
7

GND2
GND2

GND2
PGND2
－
－

－
－

Secondary GND
Secondary GND

8
9

CLAMP
PGND2

PGND2
－

－
－

Active Miller clamp output
Secondary power GND

10
11

PGND2
OUTL

－

－
－

Secondary power GND
Low side gate drive output

12
13

N.C.
OUTH

PGND2

－
－

Non Connection
High side gate drive output

14
15

PVCC2
TREF

PGND2
GND2

－
－

Secondary power supply input (15 V typ.)Constant current setting pin connected to resistor
for IGBT temp detection

16

CTEMP

GND2

－

17

GND2

－

－

IGBT temp detection period setting pin connected
to capacitor
Secondary GND

18
19

TEMP1
TEMP2

GND2
GND2

－
－

IGBT temp detection input (ch1)
IGBT temp detection input (ch2)20

TEMPVL

GND2

－

21

SEL

GND2

PD

IGBT temp voltage detection threshold value
input (lower limit)
Selection of over current detection function(GND2: Enabled, VREG: Disabled)

22
23

N.C.
VREG

－

－
－

Non Connection
5 V regulator output

24
25

GND2
N.C.

GND2
－
－

－
－

Secondary GND
Non Connection

26
27

N.C.
N.C.

－
－

－
－

Non Connection
Non Connection

28
29

N.C.
GND1

－
－

－
－

Non Connection
Primary GND

30
31

N.C.
N.C.

－
－

－
－

Non Connection
Non Connection

32
33

N.C.
TEMPOUT－－－Non Connection
IGBT temp detection output

34
35

N.C.
VCC1

－
－

Non Connection
Primary power supply input (5 V typ.)

36
37

N.C.
INB

－

38
39
40
41

PIN No.

PIN NAME

PGND2
－

GND1
－
GND1
－

PU/PD

Functions

GND1

PU

Non Connection
Inverted gate drive input

INA
GND1

GND1
－

PD
－

Non-inverted gate drive input
Primary GND

FHT1
FO

GND1
GND1

－
PU

Fault hold time setting pin connected to capacitor
Non-inverted fault output (H level output at error)

PU

Inverted fault output (L level output at error)

42
FO_B
GND1
Remark: PD - Pull down resistor / PU- Pull up resistor
N.C. pins in open state is recommended.

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Table 1: Pin List (2/2)

43
44

N.C.
GND1

Reference
pin
－
－

45
46

N.C.
N.C.

47
48

N.C.
N.C.

PIN No.

PIN NAME

PU/PD

Functions－－

Non Connection
Primary GND

－
－

－
－

Non Connection
Non Connection

－
－

－
－

Non Connection
Non Connection

Remark: PD - Pull down resistor / PU- Pull up resistor
N.C. pins in open state is recommended.

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4. Functional Description
4.1 Power Supply
The primary circuit has the power supply pin (VCC1) which supplies 5 V power reference to GND1.
The secondary circuit has two types of power supply pins VCC2 and PVCC2, and two types of GND
pins GND2 and PGND2. VCC2 supplies 15 V power reference to GND2 to the control circuit of thesecondary side, and PVCC2 supplies 15 V power reference to PGND2 to the gate drive circuit. The IGBT
gate voltage is applied from PVCC2 at the ON state and from PGND2 at the OFF state. VCC2 and
PVCC2 should be externally short-circuited and GND2 and PGND2 should also be externally shortcircuited.
The IC incorporates a 5-V output regulator, and outputs 5 V from the VREG pin. This regulator iscapable of supplying a maximum of 5-mA current to the external circuits, thus being useful for setting the
IGBT temperature detection circuit and other circuits. Even when the 5-V power is not necessary forexternal circuits, the 0.022-uF capacitor should be connected to the VREG pin to stabilize the internal
voltage.
4.2 Inverted input/Non-inverted input
The IGBT gate can be turned on or off by either non-inverted logic (active high) input or inverted logic(active low) input. The IGBT gate is turned on only when the INA= high (H) and INB= low (L) (refer totable 2).
When the non-inverted logic is used, the input signal should be applied to the INA pin with the INB pin
fixed to the low level.
When the inverted logic is used, the input signal should be applied to the INB pin with the INA pin fixed
to the high level.
The INA and INB pins are internally pulled down and pulled up, respectively. Therefore, the IGBT isturned off when one of the INA and INB pins are open.
4.3 Gate Driver
The gate driver charges or discharges the IGBT gate pins. Figure 3 shows a block diagram of thecircuit.
To turn on the IGBT, the OUTH pin is short-circuited to the PVCC2 pin via a 1.0 Ohm or smallertransistor; and the OUTL pin is driven to the high-impedance state.
To turn off the IGBT, the OUTL pin is short-circuited to the PGND2 pin via a 1.0 Ohm or smallertransistor; and the OUTH pin is driven to the high-impedance state.
Since the high-side gate drive output pin OUTH and the low-side gate drive output pin OUTL are
independent of each other, the slew rates of the rise and fall of the gate voltage can be separately
adjusted using the external resistors (RGH and RGL). The OUTH and OUTL pins should be provided
with individual gate resistors and connected to the IGBT. The external resistor values (RGH and RGL)
should be determined so that the peak current does not exceed the absolute maximum ratings (IOUTH
and IOUTL) while the IGBT is being charged or discharged.
Table 2: I/O Truth Table
INA

INB

OUTH

OUTL

IGBT State

L

X

Hi-Z

L

OFF

X
H

H
L

Hi-Z
H

L
Hi-Z

OFF
ON

4.4 Active Miller Clamp
The active Miller clamp is the feature to prevent the self-turn-on of the IGBT due to the coupling
capacitance between the IGBT gate and collector. Figure 3 shows a block diagram of the circuit.
The CLAMP pin also serves as the input pin to detect the IGBT gate voltage. If the CLAMP pin voltage
falls below VCLAMP (3.0 V typ.) while the input signal to turn off the IGBT is applied to the INA or INB pin,
the IGBT gate is short-circuited to the PGND2 pin with 1.0 Ohm or lower.
With the CLAMP pin, the gate can be connected to the PGND2 pin with the lower impedance than the
OUTL pin to which the gate resistor (RGL) is connected. Therefore, self-turn-on of the IGBT can beprevented more effectively, compared to the case in which only the OUTL pin is used to ground the gate.
The active Miller clamp not only works at normal turn-off operation of the IGBT as shown in the timing
chart in figure 12 but also works at soft turn-off operation as shown in figures 13 to 17.
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Gate driver

Active Miller clamp

Figure 3: Gate Driver and Active Miller Clamp Circuit
4.5 Soft Turn-off

The soft turn-off is the feature to lower the gate voltage of the IGBT gradually and turn it off when anyof the following abnormal states is detected on the secondary circuit: low voltage, over current, shortcircuit, over temperature (IGBT and IC), TEMP1 or TEMP2 open, and timeout (communication error).
Figure 4 shows a block diagram of the soft turn-off circuit.
If a fault such as over current occurs and the IGBT is turned off immediately, the IGBT may bedestroyed due to the excessive voltage applied between the collector and emitter of the IGBT. To prevent
this, the IGBT gate is discharged slowly using the soft turn-off pin instead of using a high current gate
driver or active Miller clamp. The turn-off time can be adjusted by the resistor (RSOFT) connected between
the SOFT pin and the IGBT gate pin.

(Controller)

Gate driver+
Active Miller clamp

Normal -> Low
Fault -> HighSoft turn-off circuit

Figure 4: Soft Turn-off Circuit

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4.6 Abnormal State Detection
This product can detect various abnormal states (faults) and externally output the associated fault
signals. The following types of abnormal states can be detected:
1. IGBT over current and short circuit
2. IGBT over temperature and temperature sense diode open
3. Low voltage (UVLO)
4. Timeout
5. Over temperature of the product (TSD)
Sections 4.6.1 to 4.6.6 describe the above functions.
4.6.1 IGBT Over Current and Load Short Circuit Detection
This feature turns off the output from the gate driver if the over current or short-circuit current in the IGBT
is detected. Figure 5 shows a block diagram of the circuit. Since two CS pins (CS1 and CS2) are provided,
it is possible to separately detect the emitter current of the two IGBTs connected in parallel.
By applying the pin voltage of the shunt resistor connected to the IGBT emitter pin to the CS1 or CS2
pin, it is possible to detect whether the IGBT emitter is in the over current state or load short circuit state.
The over current detection threshold can be set through the shunt resistor value.
The IGBT is soft turned-off if the voltage applied to the CS1 or CS2 pin rises beyond the thresholdvoltage* when the IGBT is in the on-state. At this time, the high level is output to the FO pin and the lowlevel is output to the FO_B pin of the primary circuit.
*Over current detection voltage (Voc): 0.25 V typ.; filtering time 1 us typ.
* Short circuit current detection voltage (Vsc): 0.5 V typ.
The over current detection function is enabled when the SEL pin is open or connected to the GND2
pin; to disable the function, connect the SEL pin to the VREG pin (5 V typ.).
VREG
5V

23

21

SEL

100k

C

IGBT
Short circuit current

G

GND2

detection (SC)
短絡電流検出(SC)

SE

CS1

E

2

VSC(0.5V)
Low：正常Low: Normal
High：フォールト
High: Fault

Filter
1us

RCS1
GND2

VOC(0.25V)

PGND2

Over
current detection
過電流検出(OC)(OC)

Figure 5: Over Current and Short Circuit Current Detection Circuit
4.6.2 IGBT Temperature Detection
Figure 6 shows the IGBT temperature detection circuit. This circuit outputs the constant current (ITEMP= 4/RTREF) from the TEMP pin to the temperature sense diode incorporated in the IGBT. The forward
voltage of the temperature sense diode (IGBT chip temperature voltage) is input to the IGBT temperaturedetection circuit via the TEMP pin, converted to the PWM signal having the duty cycle proportional to thevoltage, and finally output from the TEMPOUT pin via the Micro Isolator.
Since two TEMP pins (TEMP1 and TEMP2) are provided, it is possible to separately monitor thetemperature of the two IGBTs connected in parallel. In this case, the lower TEMP pin voltage (the higher
IGBT chip temperature) of the two is selected and output.
When the temperature of only one IGBT is to be monitored, connect the TEMP1 and TEMP2 pins inparallel. In this case, the sum of the TEMP1 and TEMP2 pin current flows in the IGBT temperature sense
diode connected to the TEMP pins. Therefore, appropriately adjust the current value using the external
RTREF.
The CTEMP pin is used to set the frequency of the PWM signal output from the TEMPOUT pin.
Connect the capacitor Ctemp to the CTEMP pin. The frequency of the PWM signal fTEMPOUT can be
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determined by the equation shown in figure 7.
Figure 8 shows the relationship between the temperature sense voltage input to the TEMP pin and the
duty cycle of the PWM signal output from the TEMPOUT pin. Based on the VL and VH determined by
the equation below, the duty cycle linearly changes from 10% to 90% when the TEMP pin voltage is in arange from VL to VH. When the TEMP pin voltage is lower than VL, the duty cycle is limited to 10% andwhen the TEMP pin voltage is higher than VH, the duty cycle is limited to 90%.
VL = 0.1×VTEMPVH + 0.9×VTEMPVL
VH = 0.9×VTEMPVH + 0.1×VTEMPVL(VTEMPVH = 3.8 V; VTEMPVL is set using the TEMPVL pin.)
The TEMPOUT pin output is fixed to the low level (GND1) if the voltage for under-voltage lock out(VCC1, VCC2) is detected.

RTREF(0.4V)

TREF

GND2
15

VREG

VREG
5V

VTEMPVH=3.8V

23(5.0V)VREG
ITEMP = 4.0/RTREF(ITEMP)

GND2

TEMP1

(PWM)

18

Duty
Duty制限Limitation(10%/90％)(10%/90%)

GND2
VTEMPVH=3.8V

TEMPVL(VTEMPVL)GND2(VTEMPVL)

20

Charge(充電)
Oscillator
発振回路

CTEMP
16

Discharge
(放電)

CTEMP

GND2

GND2

TEMPOUT Frequency

Figure 6: IGBT Temperature Detection Circuitf TEMPOUT =1
2  50k  Ctemp

10kHz

2.5kHz
1kHz

1nF

4nF

10nF

CTEMP

Figure 7: CTEMP-TEMPOUT Frequency

Figure 8: Relation between TEMP1 and TEMP2 Voltages
and PWM Output Duty Cycle

4.6.3 IGBT Over Temperature Detection and Detection of Temperature Sense Diode OpenThis feature turns off the IGBT if over temperature of the IGBT is detected. This feature is included inRev. 5.2 E R33DS0010EJ0520
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If the TEMP1 or TEMP2 pin voltage falls below the over temperature detection threshold (VOT = VTEMPVL- 0.1 V typ.), the IGBT is soft turned off. At this time, the high level is output to the FO pin and the lowlevel is output to the FO_B pin of the primary circuit.
In addition, if the TEMP1 or TEMP2 pin voltage rises beyond the open detection threshold (VOP = 4.25
V typ.), the temperature sense diode is determined to be open. At this time, the IGBT is soft turned off
and the high level is output to the FO pin and the low level is output to the FO_B pin of the primary circuit.
4.6.4 Under Voltage Lock Out (UVLO) Circuit
This feature turns off the IGBT to prevent the damage on the IGBT due to malfunctioning of the IC
when the supply voltage goes low.
The primary circuit is equipped with a UVLO that detects a voltage drop of VCC1, and the UVLO turns
off the IGBT (this is a normal turn-off operation different from a soft turn-off) when the VCC1 voltage
drops below 4.1 V. At this time, the high level is output to the FO pin and the low level is output to the
FO_B pin of the primary circuit.
The secondary circuit is equipped with a UVLO that detects the voltage drop of VCC2 and a UVLO
that detects the voltage drop of VREG (output from 5 V regulator). The IGBT is soft turned off if the VCC2
voltage drops below 10 V or the VREG voltage drops below 4.1 V. At this time, the high level is output tothe FO pin and the low level is output to the FO_B pin of the primary circuit.
4.6.5 Timeout Detection
The timeout detection is a feature that outputs a fault status when the data transfer via Micro Isolator
is not correctly performed.
For example, a timeout is detected at the secondary circuit when a signal transferred from the primarycircuit to the secondary circuit via Micro Isolator is not detected in a certain period of time. The IGBT issoft turned off if a timeout is detected at the secondary circuit. At this time, the high level is output to theFO pin and the low level is output to the FO_B pin of the primary circuit.
Also, a timeout is detected at the primary circuit when a signal transferred from the secondary circuit
to the primary circuit via Micro Isolator is not detected in a certain period of time. When a timeout isdetected at the primary circuit, the high level is output to the FO pin and the low level is output to the
FO_B pin of the primary circuit. The IGBT is not forcibly turned off in this condition.
4.6.6 Internal Over Temperature Detection (TSD)
This feature turns off the IGBT to prevent the damage on the IGBT due to malfunctioning of the IC
when an extraordinary over heat (200 degC) is detected in the IC (thermal shut down: TSD). The
operation is resumed when the IC temperature is decreased by the TSD hysteresis temperature (30degC).
Temperature sense diodes are placed at the three positions that tend to be heated in the IC (near the
OUTH, OUTL and CLAMP pins). The IGBT is soft turned off if the temperature of the driver transistor in
the IC exceeds a threshold value due to the over load or the increased ambient temperature. At this time,
the high level is output to the FO pin and the low level is output to the FO_B pin of the primary circuit.
In addition, another temperature sense diode is placed near the VREG pin. Output from the 5 V
regulator is stopped when the temperature of the 5 V regulator exceeds a threshold value due to the overload on the VREG pin (5 V output) or the increased ambient temperature. A temperature sense signal
from the 5 V regulator does not directly soft turn off the IGBT or output a fault signal to the primary circuit.
However, when the regulator stops and the VREG voltage drops to 4.1 V or less, the under voltage lockout circuit starts operation and soft turns off the IGBT. At this time, the high level is output to the FO pin
and the low level is output to the FO_B pin of the primary circuit.
4.7 Fault Signal Output HoldThis feature holds a fault signal output in a certain period of time when any of the following abnormal
states is detected on the secondary circuit: under voltage, over current/short circuit, over temperature(IGBT over temperature, IC internal over temperature), TEMP1 and TEMP2 pin open, or timeout. Figure
9 is a fault signal output circuit. Figure 10 is a fault signal output hold time setting circuit.
While a fault signal output is held, the high level and the low level are output from the non-inverted
fault output pin (FO) and the inverted fault output pin (FO_B) on the primary circuit, respectively, and the
IGBT is forcibly turned off. The IGBT cannot be turned on again until the end of the fault signal output
hold time.
The time for which a fault signal output is held can be set by the capacitor CFHT1 connected to the FHT1
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pin. Table 3 shows the relationship between the hold time of a fault signal output on the primary circuit(MCU side) and the hold time of a soft turn-off output on the secondary circuit (IGBT side).
Table 11 shows the relationship between the capacitance of CFHT1 and the fault signal hold time tFHT.
In addition, since the secondary circuit includes a 100 us timer, the fault signal output hold time tFHT is
100 us when the value of CFHT1 is smaller than 100 us. Refer to table 4 for the conditions needed to reseta fault signal output after the detection of an abnormal state.

Fault signal
Low: Normal
High: Fault

ON: Normal state or state after a fault is reset
OFF: State in which a fault is held

Note: Output from the FO_B pin (35) is theinverted logic of the FO pin (34).

Figure 9: Fault Signal Output Circuit
Fault signal
Low: Normal
High: Fault

Fault occurs

Fault reset

ON: Normal state or state after a fault is reset
OFF: State in which a fault is held

Figure 10: Fault Signal Output Hold Time Setting Circuit
Table 3: Fault Signal Output Hold Time (tFHT)
Hold time for fault signal output and IGBT soft turnoff

Without CFHT1
MCU-sidefault signal
output holdtime (FO &FO_B)

With CFHT1

Greater value oftFHT1 or 100 us

tFHT = Fixed to 100 us

IGBT-sidesoft turn-off
hold time

Note: tFHT1 is fixed to 100 us when tFHT1≦100us.

Figure 11: Relationship between Capacitor Value
Connected to FHT1 Pin and Fault Signal Output
Hold Time

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Table 4: Abnormal State Detecting Conditions and Fault Signal Output Hold Resetting Conditions
Out Pins

Fault “SET” conditions

Fault “RESET” conditions

FO
FO_B

At least one of the following conditions occurs• Over Current: CS1/2 > 0.25V (When IGBT=ON)• Short Circuit: CS1/2 > 0.5V (When IGBT=ON)• TEMP1/2 < VTEMPVL-0.1V• TEMP1/2 > 4.25V• VCC2 < 10V• VREG < 4.1V
• Driver temperature > 200C• No signal from MCU-side to IGBT-side• No signal from IGBT-side to MCU-side• VCC1 < 4.1V

All the following conditions are satisfied• All the fault “SET” conditions cleared• 100us (typ.) elapsed since fault occurred• tFHT1 elapsed since fault occurred• INA=L or INB=H• Signal from IGBT-side detected

Note: All of the values in the table are typical.
Table 5 shows a list of abnormal states and the operations when those abnormal states are detected.
If an abnormal state detection signal is instantaneously kept shorter than the filtering time, it is ignored
as a noise.

Table 5: List of Abnormal States (When SEL Pin Input Level is Low (= GND2))
IGBT-Side Fault

Input conditions

NormalCondition

Short
CircuitOver
IGBT
TEMP1/2
Current
Over Temp. OpenNote)

MCU-Side Fault

VCC2
UVLO

VREG
UVLO

Timeout

TSD

VCC1
UVLO

Timeout

VCC2

VREG

Internal

Internal

VCC1Internal> 4.25< 10V< 4.1VNo Signal>200C< 4.1VNo Signal

Monitor
Pin

-

Fault
Criteria-> 0.5V> 0.25V

Filter Time

-

None

1us

10us

10us

25us

2us

20us

2us

2us

20us

L

H

H

H

H

H

H

H

H

H

H

MCU-Side
Output

H

L

L

L

L

L

L

L

L

L

L

IGBT-Side
Operation

IGBT
On / OffCS1/2

TEMP1/2< VTEMPVL0.1

FO

Outputs

MCU-Side
Output

FO_B

IGBT Soft IGBT Soft IGBT Soft IGBT Soft IGBT Soft IGBT Soft IGBT Soft IGBT Soft IGBT Turn
Turn Off Turn Off Turn Off Turn Off Turn Off Turn Off Turn Off Turn Off
Off-: Not related-

Values are typical

Note: When the SEL pin input level is high (= VREG), the IGBT over current detection function is disabled(4.6.1).

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>4.2V

>20us

<4.1V

>4.2V

<20us

<4.1V

VCC1

H

X

X

X

L

X

L

H

X

INB

X

INA

MCU-side inputs

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>11V

>25us

<10V

X

>11V

VCC2

X: Don’t care

>4.2V

<4.1V

X

>4.2V

VREG

X

>0.5V

>1.0us>0.25Vand<0.5V<0.25V

X

CS1/2

X

L

H

X

SEL

IGBT-side inputs>10us>4.25V>10us<VTEMPVL-0.1V

X<4.25V

and>VTEMPVL-0.1V

TEMP1/2

High-Z

L

High-Z

L

High-Z

L

High-Z

L

Values are typical

>3.0V

<3.0V

>3.0V

<3.0V

>3.0V

<3.0V

>3.0V

<3.0V

High-Z

L

<3.0V
>3.0V

High-Z

>3.0V

L

<3.0V

L

High-ZL

OUTL

High-Z

High-Z

High-Z

L

High-Z

L

High-Z

L

CLAMP

>3.0V

<3.0V

X

>3.0V

<3.0V

>3.0V

<3.0V

>3.0V

<3.0V

CLAMP

High-Z

H

High-Z

OUTH

IGBT-side outputs

L

High-Z

SOFT

PWM
OutputL

PWM
OutputL

TEMPOUT

H

L

H

FO

L

H

L

FO_B

MCU-side outputs

ChargeL

ChargeFHT1Open IGBT temp diode
MCU-side fault output
IGBT soft turn-off

IGBT over-temp
MCU-side fault output
IGBT soft turn-off

VCC2 under voltage
MCU-side fault output
IGBT soft turn-off

VREG under voltage
MCU-side fault output
IGBT soft turn-off

VCC1 under voltage
MCU-side fault output
Communication timeout
IGBT soft turn-off

Short circuit
MCU-side fault output
IGBT soft turn-off

Over current
MCU-side fault output
IGBT soft turn-off

IGBT Normal turn-on

IGBT Normal turn-off

VCC1 under voltage
MCU-side fault output
IGBT turn-off

Note

R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator
PRELIMINARY DATASHEET

Table 6: I/O Truth Table

R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

PRELIMINARY DATASHEET

5. Electrical Characteristics
5.1 Absolute Maximum Ratings
Ta = -40 to 125 degC, PGND2 = GND2=0V, PVCC2 = VCC2, unless otherwise specified.
No.

Symbol

A1

VISO1

A2

VISO2

A3
A4

ParameterPin, Conditions

Values

Units

Min.

Typ.

Max.

Maximum Isolation (t=60sec)

2500

-

-

VRMS

Maximum Isolation (t=1sec)

3000

-

-

VRMS

VISO3

Maximum Isolation DC

650

VCMR

Common Mode Rejection

35

-

-

KV/us

A5

VCC1

Positive Power Supply MCU-side

VCC1

-0.3

-

6.5

V

A6

VCC2

Positive Power Supply IGBT-side

VCC2, PVCC2

-0.3

-

40

V

A7

VOUT2

Gate Driver Output Voltage

OUTH, OUTL, CLAMP, SOFT

-0.3

-

VCC2+0.3

V

A8

IOUTH

Gate Driver High-Side Peak
Current

OUTH

-10

-

0

A

A9

IOUTL

Gate Driver Low-Side Peak
Current

OUTL, CLAMP

0

-

10

A

A10

ISOFT

Soft Turn Off Peak Current

SOFT

0

-

1.0

A

A11

VREG

Regulator Output Voltage

VREG

-0.3

-

6.5

V

A12

IREG

Regulator Output Current

VREG

-10

-

0

mA

A13

VOCD

Overcurrent Sense Input Voltage

CS1, CS2-0.3-

VCC2+0.3

V

VIN2

IGBT-Side Input Voltage

TEMP1,TEMP2,SEL,TEMPVL, TREF, CTEMP

-0.3

-

VREG+0.3

V

A15

VIN1

MCU-Side Input Pin Voltage

INA, INB-0.3-

VCC1+0.3

V

A16

VOUT1

Fault Output Voltage

FO, FO_B-0.3-

VCC1+0.3

V

A17

VTOUT

Temp Monitor Output Voltage

TEMPOUT-0.3-

VCC1+0.3

V

A18

VFHT1

MCU-Side Fault Hold Timer Input
Voltage

FHT1

-0.3

-

VCC1+0.3

V

A19

VESD1

ESD Capability (HBM)

FO, FO_B

-1

-

1

kV

Other Pins

-2

-

2

kV

A20

VESD2

ESD Capability (MM)All Pins

-200

-

200

V

All Pins

-500

-

500

Corner Pins

-750

-

750

A14

fISO=10kHz, t=1us
fISO=10kHz, t=1us

V

A21

VESD3

ESD Capability (CDM)

V

A22

Pd

Power Dissipation

Rj-a=83.3℃/W Note1

-

-

0.30

W

A23

TA

Ambient Temperature

-

-40

-

125

°C

A24

TJ

Junction Temperature

-

-40

-

150

°C

A25

TSTG

Storage Temperature

-

-55

-

150

°C

Current flowing directions are:
Plus (+) or none: from outside to IC, Minus (–): from IC to outside
Note1 : Mounted on FR4 board. IC stand alone. JEDEC compliant

5.2 Recommended Operating Conditions
PGND2 = GND2 = 0 V, PVCC2 = VCC2, unless otherwise specified.
No.

SymbolParameter

B1

VCC1

Positive Power Supply MCU-side

B2

VCC2

Positive Power Supply IGBT-side

B3

VTEMPVL_R

B4

fISO

B5
B6
B7

TA

Pin, Conditions

ValuesTyp.

Pin: VCC1

4.5

5.0

5.5

V

Pin: VCC2, PVCC2

12.5

15

21.5

V

TEMPVL Input Voltage Range

Pin: TEMPVL

0.5

-

2.4

V

Signal Frequency

Pin: INA, INB

-

15

100

kHz

tIN

Minimum Input Pulse Width

Pin: INA, INB

-

20

-

ns

fTEMPOUTTEMPOUT Output Frequency

Pin: TEMPOUT

1

-

10

kHz

Ambient Temperature

-

-40

-

125

°C

Rev. 5.2 E
2020.04.23

R33DS0010EJ0520

Max.

Units

Min.

Page 14 of 38

R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

PRELIMINARY DATASHEET

5.3. Power Supply
Ta = -40 to 125 degC, GND1 = GND2 = PGND2 = 0 V, VCC1 = 4.5 to 5.5 V, VCC2 = PVCC2 = 12.5 to 21.5 V, unless otherwise
specified.
Typ.

Max.

Unit
s

Pin: VCC1
INA, INB=GND1 or VCC1

-

3.1

5.5

mA

VCC1 Operation Supply
Current

Pin: VCC1
INA=15kHz, INB=GND1

-

3.5

6.0

mA

ICC2Q

VCC2 Quiescent Supply
Current

Pin: VCC2
INA, INB=GND1 or VCC1

-

6.3

9.0

mA

ICC2_15k

VCC2 Operation Supply
Current

Pin: VCC2, INA=15kHz,
INB=GND1, No Load

-

6.8

12.0

mA

-40℃～125℃

4.7

5.0

5.3

VREG Output Voltage

Pin:
VREG,
IREG=0mA

25℃

4.8

5.0

5.2

Pin: VREG, IREG=-5mA

4.7

5.0

5.3

SymbolParameterPin, Conditions

V1

ICC1Q

VCC1 Quiescent Supply
Current

V2

ICC1_15k

V3
V4

V5
V6

Values
Min.

No.

VREG1
VREG2

VREG Output Voltage

Note

V
V

Current flowing directions are:
Plus (+) or none: from outside to IC, Minus (–): from IC to outside

5.4. Logic Input/Output
Ta = -40 to 125 degC, GND1 = GND2 = PGND2 = 0 V, VCC1 = 4.5 to 5.5 V, VCC2 = PVCC2 = 12.5 to 21.5 V, unless otherwise
specified.
Pin, Conditions

ValuesNo.

SymbolParameter

L1

VINL

Low Level Input Voltage

Pin: INA, INB

-

L2

VINH

High Level Input Voltage

Pin: INA, INB

0.7 x VCC1L3

VINHYS

Input Hysteresis

Pin: INA, INB

L4

RINA

L5

RINB

L6

ROL_FO

L7
L8

Min.

Typ.

Max.

Units

0.3 x VCC1

V

-

-

V

-

0.12 x VCC1-V

INA Pull-down Resistance Pin: INA,

50

100

200

kΩ

INB Pull-up Resistance

50

100

200

kΩ

FO/FOB Low Level Output
Pin: FO, FO_B, IO=2mA
Resistance

-

20

100

Ω

ROH_FO

FO/FOB High Level Output
Pin:FO,FO_B, IO= -10uA
Resistance

50

100

250

kΩ

IOFF_FO

Off Leak Current

-1

-

1

uA

Pin: INB,

Pin: FO, FO_B
FO=FO_B=VCC1

Current flowing directions are:
Plus (+) or none: from outside to IC, Minus (–): from IC to outside

Rev. 5.2 E
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Page 15 of 38

Note

R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

PRELIMINARY DATASHEET

5.5. Gate Driver
Ta = -40 to 125 degC, GND1 = GND2 = PGND2 = 0 V, VCC1 = 4.5 to 5.5 V, VCC2 = PVCC2 = 12.5 to 21.5 V, unless otherwise
specified.
No.

SymbolParameter

D1

RO_OUTHOUTH High Level Output
Resistance

D2

IOL_OUTH

D3

Pin, Conditions

Values

Units

Min.

Typ.

Max.

Pin: OUTH,
IO=-100mA

-

0.5

1.0

Ω

OUTH Low Level Leak
Current

Pin: OUTH,
OUTH=PGND2

-10

-

-

uA

RO_OUTLOUTL Low Level Output
Resistance

Pin: OUTL,
IO=100mA

-

0.5

1.0

Ω

D4

IOH_OUTLOUTL High Level Leak
Current

Pin: OUTL,OUTL=PVCC2

-

-

10

uA

D5

tPLH

INA High to OUTH 10%
Propagation Delay

Pin: INA, OUTH,
RGH=5.1Ω，RGL=5.1Ω

30

70

140

ns

D6

tPHL

INA Low to OUTL 90%
Propagation Delay

Pin: INA, OUTL,
RGH=5.1Ω，RGL=5.1Ω

30

70

140

ns

Note

Current flowing directions are:
Plus (+) or none: from outside to IC, Minus (–): from IC to outside

5.6. Active Miller Clamp
Ta = -40 to 125 degC, GND1 = GND2 = PGND2 = 0 V, VCC1 = 4.5 to 5.5 V, VCC2 = PVCC2 = 12.5 to 21.5 V, unless otherwise
specified.
No.

SymbolParameter

M1

RO_CLAMP

CLAMP Low Level
Output Resistance

M2

IOH_CLAMP

M3
M4

Pin, Conditions

Values

Units

Min.

Typ.

Max.

Pin: CLAMP,
IO=100mA

-

0.5

1.0

Ω

CLAMP High Level Leak
Current

Pin: CLAMP,
CLAMP=PVCC2

-

-

10

uA

VCLAMP

CLAMP Trip Voltage

Pin: CLAMP

2.7

3.0

3.3

V

tCLAMP

Active Mirror Clamp
Delay Time

Pin: CLAMP

20

70

140

ns

Note

Current flowing directions are:
Plus (+) or none: from outside to IC, Minus (–): from IC to outside

5.7. Soft Turn-off
Ta = -40 to 125 degC, GND1 = GND2 = PGND2 = 0 V, VCC1 = 4.5 to 5.5 V, VCC2 = PVCC2 = 12.5 to 21.5 V, unless otherwise
specified.
No.

SymbolParameter

S1

Ro_SOFTSOFT Low Level Output
ResistanceS2

IOH_SOFTSOFT High Level Leak
Current

Pin, Conditions

ValuesTyp.

Max.

Pin: SOFT,
Io=0.1A

-

3.5

8.5

Ω

Pin: SOFT,
SOFT=PVCC2

-

-

3

uA

Current flowing directions are:
Plus (+) or none: from outside to IC, Minus (–): from IC to outside

Rev. 5.2 E
2020.04.23

R33DS0010EJ0520

Units

Min.

Page 16 of 38

Note

R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

PRELIMINARY DATASHEET

5.8. UVLOTa = -40 to 125 degC, GND1 = GND2 = PGND2 = 0 V, VCC1 = 4.5 to 5.5 V, VCC2 = PVCC2 = 12.5 to 21.5 V, unless otherwise
specified.
ValuesNo.
SymbolParameterPin, Conditions
Units
Min.
Typ.
Max.
U1

VUVLO_VCC1T

VCC1 UVLO Trip
Voltage

Pin: VCC1

3.8

4.1

4.4

V

U2

VUVLO_VCC1R

VCC1 UVLO Recovery
Voltage

Pin: VCC1

3.9

4.2

4.5

V

U3

VUVLO_VCC1H

VCC1 UVLO
Hysteresis

Pin: VCC1

-

0.1

-

V

U7

VUVLO_VCC2T

VCC2 UVLO Trip
Voltage

Pin: VCC2

9

10

11

V

U8

VUVLO_VCC2R

VCC2 UVLO Recovery
Voltage

Pin: VCC2

10

11

12

V

U9

VUVLO_VCC2H

VCC2 UVLO
Hysteresis

Pin: VCC2

-

1.0

-

V

U13

VUVLO_VREGT

VREG UVLO Trip
Voltage

Pin: VREG

3.8

4.1

4.4

V

U14

VUVLO_VREGR

VREG UVLO
Recovery Voltage

Pin: VREG

3.9

4.2

4.5

V

U15

VUVLO_VREGH

VREG UVLO
Hysteresis

Pin: VREG

-

0.1

-

V

Current flowing directions are:
Plus (+) or none: from outside to IC, Minus (–): from IC to outside

Note
1.

Guaranteed by design and not subject to production testing.

Rev. 5.2 E
2020.04.23

R33DS0010EJ0520

Page 17 of 38

Note

R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

PRELIMINARY DATASHEET

5.9. Over Current (OC) Detection/Short Circuit (SC) Detection
Ta = -40 to 125 degC, GND1 = GND2 = PGND2 = 0 V, VCC1 = 4.5 to 5.5 V, VCC2 = PVCC2 = 12.5 to 21.5 V, unless otherwise
specified.
No.

SymbolParameter

C1

ICSL

CS Low Level Input
Current

C2

ICSH

CS High Level Input
Current

C3

VOC

OC Threshold Voltage

C4

tOC-OUTH

OC Sense to 90%
OUTH Delay

C5

tOC-SOFT

C6

tOC-FO_B

C7

VSC

C8

tSC-OUTHSC Sense to 90%
OUTH Delay

C9tSC-SOFTC10tSC-FO_B

Pin, Conditions

Values

Units

Typ.

Max.

Pin: CS1, CS2
CS1, CS2=GND2

-1

-

-

uA

Pin: CS1, CS2
CS1, CS2=VREG

-

-

1

uA

0.22

0.25

0.28

V

Pin: CS1, CS2, OUTH,SEL=GND2，RL=1kΩ

-

1.2

2.4

us

OC Sense to 90%
SOFT Delay

Pin: CS1, CS2, SOFT,
SEL=GND2, RSOFT=1kΩ

-

1.2

2.4

us

OC Sense to 10%
FO_B Delay

Pin: CS1, CS2, FO_B,
SEL=GND2，RFO=3kΩ

-

1.2

2.4

us

0.44

0.5

0.56

V

Pin: CS1, CS2, OUTH,
SEL=VREG, RL=1kΩ

-

100

400

ns

1

SC Sense to 90%
SOFT Delay

Pin: CS1, CS2, SOFT,
SEL=VREG，RSOFT=1kΩ

-

100

400

ns

1

SC Sense to 10%
FO_B Delay

Pin: CS1, CS2, FO_B,
SEL=VREG, RFO=3kΩ

-

100

400

ns

1

100

200

kΩ

SC Threshold Voltage

Pin: CS1, CS2
SEL=GND2

Pin: CS1, CS2
SEL=VREG

C11

RSEL

SEL Pull-down
Resistance

Pin: SEL50

C12VINL_SEL

Low Level Input
Voltage at SEL

Pin: SEL-

0.3 x VREGV

C13

VINH_SELHigh Level Input
Voltage at SEL

Pin: SEL

0.7 x VREG-

V

Current flowing directions are:
Plus (+) or none: from outside to IC, Minus (–): from IC to outside
Note
1.

Guaranteed by design and not subject to production testing.

Rev. 5.2 E
2020.04.23

Note

Min.

R33DS0010EJ0520

Page 18 of 38

R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

PRELIMINARY DATASHEET

5.10. Temperature Monitor
Ta = -40 to 125 degC, GND1 = GND2 = PGND2 = 0 V, VCC1 = 4.5 to 5.5 V, VCC2 = PVCC2 = 12.5 to 21.5 V, unless otherwise
specified.
No.

SymbolT1

VTREF

TREF Output
Voltage

T2

VTEMPVH

IGBT Temperature
Monitor High Limit
Input Voltage

T3

ITEMP

Parameter

TEMP Bias Current

DOUT

PWM On DutyPWM On Duty
Upper LimitPWM On Duty
Lower Limit
TEMPVL Input
Current

Units

Min.

Typ.

Max.

Pin: TREF
ITREF= -100uA

0.36

0.40

0.44

V

(IC internal)

3.50

3.80

4.10

V

ITREF= -10uA

-107

-100

-93

uA

ITREF= -100uA

-1070

-1000

-930

uA

TEMP=1.16V

13

20

27

%

-40℃~125℃

43

50

57

%

25℃

45

50

55

%

TEMP=3.14V

73

80

87

%

TEMP>3.6V

83

90

97

%

TEMP<0.7V

3

10

17

%

Pin: TEMPVL

-1.0

-

1.0

uA

Pin:
TEMP1,TEMP2
VTEMP1=3.0V
VTEMP2=3.0V

T4

ValuesPin, Conditions

Pin:
TEMPOUTTEMPVL=0.5V

TEMP=2.15V

T5

DOUT_UL

T6

DOUT_LLT7

ITEMPVL

T8

FTEMPOUTTEMPOUT Output
Frequency

Pin: TEMPOUTTEMPVL=0.5V
CTEMP=4.7nF

1

2

4

kHz

T9

VOL_TO

Low Level Output
Voltage

Pin: TEMPOUT, IO=1mA--

0.20 x
VCC1

V

T10

VOH_TOHigh Level Output
Voltage

Pin: TEMPOUT, IO=-1mA0.80 x
VCC1

-

-

V

T11

VOT

OT Detect Threshold
Voltage

Pin: TEMP1, TEMP2,TEMPVL=0.5V

0.36

0.4

0.44

V

T12

VOP

OPEN Detect
Threshold Voltage

Pin: TEMP1, TEMP2

3.85

4.25

4.65

V

T13

tOT-OUTHOT Sense to 90%
OUTH Delay

Pin: TEMP1, TEMP2, OUTH,
RL=1kΩ

5

10

20

us

T14

tOT-SOFTOT Sense to 90%
SOFT Delay

Pin: TEMP1, TEMP2, SOFT,RSOFT=1kΩ

5

10

20

us

T15

tOT-FOOT Sense to 10%
FO Delay

Pin: TEMP1, TEMP2, FO,
RFO=3kΩ

5

10

20

us

T16

tOP-OUTH

OPEN Sense to 90%
OUTH Delay

Pin: TEMP1, TEMP2, OUTH,
RL=1kΩ

5

10

20

us

T17

tOP-SOFTOPEN Sense to 90%
SOFT Delay

Pin: TEMP1, TEMP2, SOFT,RSOFT=1kΩ

5

10

20

us

T18

tOP-FOOPEN Sense to 10%
FO Delay

Pin: TEMP1, TEMP2, FO,
RFO=3kΩ

5

10

20

us

Current flowing directions are:
Plus (+) or none: from outside to IC, Minus (–): from IC to outside
Note
1.

Guaranteed by design and not subject to production testing.

Rev. 5.2 E
2020.04.23

R33DS0010EJ0520

Page 19 of 38

Note

1

R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

PRELIMINARY DATASHEET

5.11. Fault Signal Output Hold Timer
Ta = -40 to 125 degC, GND1 = GND2 = PGND2 = 0 V, VCC1 = 4.5 to 5.5 V, VCC2 = PVCC2 = 12.5 to 21.5 V, unless otherwise
specified.
No.

SymbolParameter

F1

VFHT1

Fault Hold Timer
Threshold Voltage

F2

ICHG_FHT1

F3

Pin, Conditions

Values

Units

Min.

Typ.

Max.

Pin: FHT1

1.75

2

2.35

V

Fault Hold Timer
Charge Current

Pin: FHT1,
FHT1=1V

-6

-4.5

-2.5

uA

IDSCHG_FHT1

Fault Hold Timer
Discharge Current

Pin: FHT1,
FHT1=1V

1.0

3.6

-

mA

F4

tFHT0

Fault Hold Time 0

50

100

200

us

F5

tFHT1

Fault Hold Time 1

15

21

45

ms

Pin: FO, FO_B,SOFT
RFO=3kΩ, CFHT1=0
Pin: FO, FO_B
RFO=3kΩ, CFHT1=0.047uF

Current flowing directions are:
Plus (+) or none: from outside to IC, Minus (–): from IC to outside

Rev. 5.2 E
2020.04.23

R33DS0010EJ0520

Page 20 of 38

Note

R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

PRELIMINARY DATASHEET

6. Timing Chart
6.1 Normal Gate Drive Output

Figure 12: Normal IGBT ON and OFF Operation
6.2 Gate Drive Output at Detection of Abnormal State

Figure 13: Operation When an Abnormal State is detected with IGBT being ON (Fault Signal Output
Cleared by FHT1 Hold Time)
Rev. 5.2 E
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R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

PRELIMINARY DATASHEET

Figure 14: Operation When an Abnormal State is detected with IGBT being OFF (Fault Signal Output
Cleared by FHT1 Hold Time)

Rev. 5.2 E
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R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

PRELIMINARY DATASHEET

Figure 15: Fault Signal Output Cleared by Edge of INA INB

Figure 16: Fault Signal Output Cleared by Falling of Error Input Signal

Rev. 5.2 E
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R33DS0010EJ0520

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R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

PRELIMINARY DATASHEET

Figure 17: In Case of Uncompleted Soft Turn-off

Rev. 5.2 E
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Page 24 of 38

R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

PRELIMINARY DATASHEET

6.3 Timing Charts for Detections of Various Abnormal States

Figure 18: Short Circuit (SC) Detection

Figure 19: Over Current (OC) Detection

Rev. 5.2 E
2020.04.23

R33DS0010EJ0520

Page 25 of 38

R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

PRELIMINARY DATASHEET( ) indicates an IC internal voltage.

Figure 20: IGBT Temperature Monitor

Figure 21: Secondary 5 V UVLO

Rev. 5.2 E
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R33DS0010EJ0520

Page 26 of 38

R2A25110KSP Intelligent Power Device for IGBT drive with Micro Isolator

VCC2

VREG

PRELIMINARY DATASHEETVUVLO_VCC2R
11V

VUVLO_VCC2T
10V

VUVLO_VREGT
4.1V

Internal
Error Signal

Filter time: See Table 5

PVCC2tUVCC2-OUTH

90%

OUTH

tUVCC2-SOFT

90%

SOFT

50%

50%
PGND2

tFHT0

FO

tUVCC2-FO

tFHT1
VFHT1
2.0V

FHT1
TEMPOUT=L
while 15V UVLO is detected

TEMPOUT

Figure 22: Secondary 15 V UVLO

Figure 23: Primary UVLO

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7. Package

Figure 24: SSOP48 Package

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8. Application Examples
Figure 25 shows a circuit example including two IGBTs connected in parallel. In this example, thesecondary power supply (VCC2) is 15 V. The primary power supply (VCC1) voltage is the same as thepower supply voltage of the MCU (VDD).
For the gate pins of the IGBT, 5.1 ohms are inserted between that and OUTH of the IC (R GH) andbetween that and OUTL (RGL), respectively. To the gate pins of the IGBT, the SOFT and CLAMP pins of
the IC are directly connected via 47 ohms (RSOFT), respectively.
For over current and load short-circuit current detection, the emitter current is detected by a
combination of the multi-emitter output IGBT and shunt resistors. In this example, the shunt resistors(RCS) to be connected to the CS1 and CS2 pins are 15 ohms. By this setting, when current flowing into
the shunt resistor exceeds 16.7 mA for 1 us or more, it is detected as the over current state; when
exceeding 33.3 mA, it is detected as the load short-circuit state immediately (detected as an abnormal
state).
For IGBT temperature detection, the TEMP1 and TEMP2 pins are connected to the temperature sense
diodes implemented in the IGBTs. Normally, a PWM signal with the on-duty ratio corresponding to a lower
voltage of either the TEMP1 or TEMP2 pin is sent out from the TEMPOUT pin to the MCU. Since 4.7 nF
is connected with the CTEMP pin, a frequency of the PWM signal to be sent out becomes 2.1 kHz. Since
0.5 V obtained by dividing the VREG pin output is applied to the TEMPVL pin, when either the TEMP1or TEMP2 pin falls short of 0.4 V (VOT = VTEMPVL - 0.1) or exceeds 4.25 V (VOP), it is detected as anabnormal state.
If an abnormal state is detected, the gate of the IGBT is soft turned off, and a fault signal is sent out
from the FO pin to the MCU at the same time. Since 0.047 uF is connected with the FHT1 pin, the fault
signal is held for about 21 ms.
25 N.C.

GND2 24

26 N.C.

VREG 23

27 N.C.

N.C. 22

22nF

0.1uF

TEMPVL 20

30 N.C.

TEMP2 19

31 N.C.

TEMP1 18

32 N.C.
33 TEMPOUT

IN2

VDD

OUT

IN1

GND

3kΩ

100pF

0.047uF
100pF

5V

0.022uF
0.1uF

0.022uF

GND2 17
4.7nF

CTEMP 16

34 N.C.

TREF 15

35 VCC1

PVCC2 1436 N.C.

OUTH 1337 INB

N.C. 1238 INAOUTL 1139 GND1

PGND2 1040 FHT1

PGND2 941 FO

CLAMP 842 FO_B

GND2 7

43 N.C.

GND2 644 GND1

SOFT 545 N.C.

VCC2 446 N.C.

CS2 3

47 N.C.

CS1 2

48 N.C.

GND2 110kΩ
15V
RGL:5.1Ω

1uF
RGH:5.1Ω

100pF
0.1uF
100pF

RGE:15kΩ

MCU

SEL 2129 GND1

20kΩ

RGE:15kΩ

28 N.C.

180kΩ

RSOFT:
47Ω

100Ω
100Ω

RCS
15Ω

Figure 25: Circuit Example around the IC

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8.1 Circuit Example of Power Supply and GND Pins
Figure 26 shows the circuit example of the power supply and GND pins. Two GND1 pins (pin 25 andpin 37) must be short-circuited outside the IC. The GND2 pins (pin 5 and pin 14) and PGND2 pins (pin 8
and pin 7) must be short-circuited outside the IC. The bypass capacitor should be placed near eachpower supply pin as close as possible.

Figure 26: Circuit Example of Power Supply Pins

8.2 Circuit Examples of Inverted/Non-inverted Input Pins
Figure 27 shows the examples in which the inverted input pin and the non-inverted input pin are used.
Figure 27 (a) is an example in which the non-inverted input (INA) is used as a gate control signal of the
IGBT. The IGBT is tuned on when INA is high. The unused INB pin must be connected to GND1.
Figure 27 (b) is an example in which the inverted input (INB) is used as a gate control signal of the
IGBT. IGBT is turned on when INB is low. The unused INA pin must be connected to VCC1.
Figure 27 (c) is an example in which both the non-inverted input (INA) and the inverted input (INB) areused. The IGBT is turned on only when INA = high and INB = low.

Figure 27: Circuit Examples of Inverted/Non-inverted Input Pins

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8.3 Circuit Examples of Gate Driver Output Pins
Figure 28 shows circuit examples of the gate driver output pins. As shown in figure 28 (a), each of the
OUTH pin and the OUTL pin must be connected to the gate resistor. Do not short-circuit between the
OUTH and OUTL pins as in figure 28 (b).

Figure 28: Circuit Examples of Gate Driver Output Pins

8.4 Circuit Examples of Soft Turn-off Output Pin
Figure 29 shows circuit examples of the soft turn-off pin.
As in figure 29 (a), the SOFT pin is connected to the gate pin of the IGBT via the resistor (RSOFT). The
soft turn-off time of the IGBT is adjusted by the value of this resistor (RSOFT).
Figure 29 (b) is a circuit example that uses a circuit outside the IC to realize the soft turn-off function.
For example, a fault signal (inverted logic: L at fault) can be output at the detection of an abnormal
condition by connecting the SOFT pin to the pull-up resistor.

Figure 29: Circuit Examples of Soft Turn-off Output Pin

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8.5 Circuit Examples of Over Current/Load Short Circuit Detection Pins
Figure 30 (a) is a circuit example of the over current detection pins when driving the IGBTs in parallel
connection. Each of the CS1 pin and the CS2 pin is connected to the shunt resistor for each emitter. In
this example, the SEL pin is left open and the over current detection function is enabled.
Figure 30 (b) is a circuit example of the CS1 and CS2 pins when driving a single IGBT. An unused CS
pin must be connected to GND2.
Figure 30 (c) is a circuit example when both over current and load short circuit are not detected. Both
the CS1 and CS2 pins must be grounded to GND2.

Figure 30: Circuit Examples of Over Current Detection Pins

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8.6 Circuit Examples of IGBT Temperature Sense Input
Figure 31 (a) shows the circuit example of detecting the IGBT chip temperature by each of thetemperature sense diodes implemented in the IGBTs connected in parallel. The TEMP1 and TEMP2 pinsare connected to the anodes of the temperature sense diodes, and the cathodes of the diodes areclamped to GND2. To the TEMPVL pin, the voltage obtained by dividing 5 V output from the VREG pin
by the resistors (RTMP1, RTMP2, RTMP3) is applied. When the constant current set by the external
resistor of the TREF pin flows from the TEMP1 and TEMP2 pins into the temperature sense diodes in
the IGBTs, voltages of the TEMP1 and TEMP2 pins will become forward voltages VF of the diodes. Since
VF falls as the temperature rises, voltages of the TEMP1 and TEMP2 pins fall. When the voltage of the
TEMP1 or TEMP2 pin becomes further 0.1 V lower than the voltage of the TEMPVL pin, the fault signal
is generated.
Figure 31 (b) shows the circuit example of using the NTC thermistor for temperature detection. By
outputting the constant current to the NTC thermistor, voltages of the TEMP1 and TEMP2 pins fall as thetemperature rises.
Figure 31 (c) shows the circuit example of detecting the chip temperature of a single IGBT by the diodeimplemented in there. Both the TEMP pins should be short-circuited before use.
Figure 31 (d) shows the circuit example of disabling the IGBT temperature detection function. The
TREF pin is connected to the VREG pin, and the voltage obtained by dividing the VREG output by theresistor is applied to the TEMPVL pin. For the TEMP1 and TEMP2 pins, the voltage obtained by dividing
the VREG output by the resistor is applied so that the applied voltage may range between the TEMPVL
pin voltage and VTEMPVH (3.8 V). The CTEMP pin is pulled down with about 100 ohms. In this case,
the TEMPOUT pin output is fixed at the high level (VCC1).

Figure 31: Circuit Examples of IGBT Temperature Sense Input
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8.7 Circuit Examples of Fault Signal Output Hold Time Setting Pin
Figure 32 shows the circuit example of the control pin (FHT1) for fault hold time.
Figure 32 (a) shows the circuit example of setting the fault hold time. The fault hold time tFHT is the time
tFHT1 that is computed from 444 x 103 x CFHT1 [F] by the capacitor CFHT1 connected with the FHT1 pin. If
CFHT1 is set to make tFHT1 less than 100 us, tFHT is fixed at 100 us.
Figure 32 (b) shows that nothing is connected with the FHT1 pin. When the FHT1 pin is not used, itshould be open or pulled up to the 5 V power supply via the resistor. The fault hold time is set to 100 us
by the timer inside the IC.

Figure 32: Circuit Examples of Fault Signal Output Hold Time Setting Pin

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8.8 Circuit Examples of Fault Signal Output Pins
Figure 33 shows circuit examples of fault output pins. Each fault output pin of FO and FO_B has aninternal 100-kohm pulled-up resistor inside the IC, which enables a fault signal to be output without anexternal resistor as in figure 33 (a). However, it is recommended to externally connect a pull-up resistor
with less than 100 k ohms as in figure 33 (b). Since the addition of a pull-up resister lowers the output
impedance, the high level output voltage is more stable and the rise time of a fault signal is reduced.
Because the FO_B pin outputs the low level at the occurrence of a fault, FO_B is useful for connecting
fault output pins of multiple ICs in parallel as in figure 33 (c). In this case, the fault bus is in the high level
when all the ICs are operating normally and in the low level when a fault signal is output from one ormore IC(s).

Figure 33: Circuit Examples of Fault Signal Output Pins

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9. 端子等価回路図 (Equivalent Circuit of terminals)
9.1 電源系(Power Supply)
35(VCC1)
35(VCC1)

29, 39, 44(GND1)

4(VCC2),14(PVCC2)14(PVCC2)4(VCC2)
電源間保護

Power Supply
Protection

電源間保護Power Supply
Protection

電源間保護Power Supply
Protection

電源間保護Power Supply
Protection

1,7,17,24(GND2)6(GND2D)
9,10(PGND2)

23(VREG)(VCC2)

amp

23(VREG)(GND2)

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9.2

PRELIMINARY DATASHEET

I/O 系(Input/Output)
2(CS1), 3(CS2)(VCC2)(VREG)

2(CS1)
3(CS2)(GND2)

5(SOFT)、8(CLAMP)、11(OUTL)(PVCC2)5(SOFT)
8(CLAMP)11(OUTL)(PGND2)13 (OUTH)(PVCC2)13(OUTH)(PGND2)

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15(TREF)(VCC2)(VREG)

15(TREF)(GND2)

16 (CTEMP)(VCC2)(VREG)

16(CTEMP)(GND2)

18(TEMP1)、19 (TEMP2)(VCC2)(VREG)

18(TEMP1)
19(TEMP2)(GND2)

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20 (TEMPVL)(VCC2)(VREG)

20(TEMPVL)(GND2)

33 (TEMPOUT)(VCC1)

33(TEMPOUT)(GND1)

37 (INB)、38 (INA)(VCC1)

38(INA)
37(INB)(GND1)

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40 (FHT1)(VCC1)

40(FHT1)(GND1)

41 (FO) ,42(FO_B)(VCC1)

41(FO)
42(FO_B)(GND1)

21(SEL)(VCC2)(VREG)

21(SEL)(GND2)

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