Article

Experimental Verification of Fault Tolerant Operation
Focusing on DC-Bus Battery Failure in Dual Inverter
Motor Drive
Yoshiaki Oto *, Toshihiko Noguchi and Melinda Badriatul Fauziah
Department of Electrical and Electronics Engineering, Shizuoka University, Hamamatsu 432-8561, Japan;
noguchi.toshihiko@shizuoka.ac.jp (T.N.); melinda.badriatul.fauziah.18@shizuoka.ac.jp (M.B.F.)* Correspondence: ohto.yoshiaki.15@shizuoka.ac.jp
Received: 15 September 2019; Accepted: 15 October 2019; Published: 18 October 2019


Abstract: Recently, a dual inverter motor drive feeding an open-end winding permanent magnet(PM) motor has been studied, aiming for the improvement of total efficiency and a fault tolerant
function of hybrid and electric vehicles. The authors have studied the fault tolerant operation of theDC-bus battery, where the failed inverter is operated only with a capacitor across the DC-bus anda space vector modulation (SVM) is employed to regulate the capacitor voltage. In our previous
research, the SVM techniques for the fault tolerant operation in a low-modulation-index have been
proposed. However, it was difficult to have fault tolerance in a high-modulation-index case. The
voltage margin in the fault situation is limited because the failed inverter is operated with the capacitor.
In this paper, the SVM technique to achieve the fault tolerant operation in the high-modulation-index
state is investigated. The novel point of this paper is that the proposed technique introduces afield-weakening control in order to reduce the command voltage vector within the controllable
voltage region. The proposed technique was verified through experimental tests and its operational
characteristics were compared with the normal operation, from the viewpoints of the total harmonic
distortion (THD) and the efficiencies of the inverters and the motor.
Keywords: dual inverter motor drive; space vector modulation; fault tolerant operation; capacitor
voltage control; open-end winding PM motor

1. Introduction
Recently, a dual inverter motor drive feeding an open-end winding PM motor has been focusedon, aiming for improvement of a total efficiency and a fault tolerant function of hybrid and electricvehicles. The dual inverter motor drive is expected to improve the efficiency of the system, because it
can generate multilevel voltage waveforms across the motor windings by adding the output voltagesof the inverters [1–6]. In addition, the dual inverter motor drive, where a DC-bus battery of one of theinverters is replaced with a capacitor, has also been studied [7–12]. In particular, it has advantages inmany of the modern current hybrid and electric vehicles, over the C-segment. Most of all, the hybrid
vehicles such as the Prius, Lexus, Camry and so forth, of the Toyota Motor Corporation employ thecircuit topology depicted in Figure 1, using the voltage-boost chopper. Therefore, it is difficult toimprove the total efficiency due to the significant power loss of the voltage-boost chopper and it canno longer continue to drive the motor, if either the chopper or the inverter fails. On the other hand, as
shown in Figure 2, the dual inverter motor drive does not require any voltage-boost converter to apply
the high voltage to the motor by adding the output voltages of both inverters. In addition, in the dual
inverter motor drive studied in this paper, the DC-bus batteries are isolated in order to secure a fault
tolerant function.

World Electric Vehicle Journal 2019, 10, 65; doi:10.3390/wevj10040065

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So
Sofar,
far,thethefault
faulttolerant
tolerantoperation
operationwith
withthethedualdualinverter
invertermotor
motordrive—which
drive—whichfocuses
focuseson
onfailures
failuresofof thetheswitchingswitching devices—havedevices—have been
been studiedstudied [13–15].
[13–15]. However,
However, thethe fault
fault tolerant
tolerant operation
operation ofof thetheDC-busDC-bus battery
battery has
has not
not been
beenconsidered
considered inindetail
detail[16,17].
[16,17]. Therefore,
Therefore, thethe authors
authors have
have focused
focused on
on aa
redundancy
switchingstatesof theinverter
motormotor
drive andhave
the faultthe
tolerant
redundancyininthe
theswitchingstatesof dualthe dual
inverterdrive
andstudied
have studied
fault
operationof the DC-bus
the studied
operation,
the failed
is isolatedwith atolerant operationof the battery
DC-bus[18,19].
batteryIn[18,19].
In the studied
operation,
thebattery
failed battery
is isolated
relay,
some
failureit isdetected
battery the
management
system. Then,the failure
with aftera relay,after
some
failureit isthroughdetectedthethroughbattery management
system.
Then,sidetheinverteris operated
onlywith a capacitor
acrossDC-bus,insteadthe isolated
battery.
In thiscase,
failure side
inverteris operated
only witha thecapacitor
acrosstheofDC-bus,
insteadof theisolatedthecapacitor
voltageof thefailure side
inverterbe controlled
at half
thebattery voltage
battery.
In thiscase, thecapacitor
voltageof themust
failureside inverter
mustofbe
controlled
at half ofof thetheotherinverterin thenormaloperationand discharging
thecharging
capacitor.and
The discharging
topology of thebattery
voltageof theother
inverterbyincharging
the normal
operation bytheoperation
thetopology
fault situation
the sameinasthe
thefault
dualsituation
inverter motor
drive,as
where
one inverterof the DC-bus
capacitor.inTheof the isoperationis the samethe dual
motor
batteries
is replaced
the capacitor.
However,in theconventional
techniques,thevoltagedrive, where
one of with
the DC-bus
batteries
is replacedwiththe capacitor.
However,
incapacitor
the conventional
istechniques,controlled constantly,
while
generating
the multilevel
voltage
waveforms
acrossmotor windings
the capacitor
voltageis controlled
constantly,
while
generating
thethemultilevel
voltage
by
the
phase
differenceofthefundamental
voltagecomponents
betweenthetwoinverters[7–12].
waveforms across the motor windings by the phase difference of the fundamental voltageOnthe other hand,in ourtechnique,a spaceis employed
thecomponents
betweenthe studied
two inverters[7–12].
On thevector
othermodulation
hand, in our(SVM)
studiedtechnique,anda spaceredundancyof the dual
inverter
motoranddrive
utilized. In ofparticular,
the capacitor
bevector modulation(SVM)
is employed
theisredundancy
the dual inverter
motorvoltage
drive ismust
utilized.
discharged
down
to half of thebattery
voltageof the otherinvertersituation,
immediately
In particular,
the capacitor
voltagemust
be discharged
down
to halfinofthe
thefault
battery
voltageof the otherafter
the battery
failureis detected,
because bothhavebeenisoperated
withthe battery
and theinverterin the fault
situation,
immediately
afterinverters
the battery
failuredetected,
becauseboth inverters
battery
voltages
havewith
beenthesamein thenormaloperation.
We haveproposed
SVM
techniquesto switch
have been
operated
battery
andthe battery
voltages
been thesamein thenormal operation.
over
the systemthe
to theoperationin thetofault
caseoversmoothlyat a low-modulation-index
We proposed
SVM
techniques
switchthe system
to the operation in[20].
the However,
fault caseitsmoothly
was difficult
achieve the fault tolerant
operation
at aithigh-modulation-index,
becausethe DC-bus
at atolow-modulation-index[20].
However,
was difficult to achieve
the fault
tolerant
voltageof theside inverter is reducedby half,
other words,
marginthe faultis
operation
at afailure
high-modulation-index,
becausethe inDC-busvoltagetheof voltage
the failure
sideofinverter
tolerant
limited.
reducedoperationby half, inisotherwords, the voltage margin of the fault tolerant operation is limited.
In
fault
tolerant
operation
at atthethehigh-modulation-index
isInthisthispaper,
paper,thetheSVM
SVMtechnique
techniquefor
forthethefaulttolerant
operation
high-modulation-index
newly
proposed,
whichwhich
controls
the voltage
commandwithin thewithin
limitedthe
voltageregionby employingais newly
proposed,controls
the voltage
commandlimitedvoltageregion by
field-weakening
control technique.
However,it hasHowever,the problem
unexpected
pulseserror
areemploying a field-weakening
control
technique.
it thathas theproblemerrorthat voltage
unexpectedvoltage pulses
generatedin thewaveforms
multilevelduring
voltage
waveforms
duringIna thisdeadtime it[21,22].
In thisgeneratedin thearemultilevel
voltagea deadtime [21,22].
paper,
is confirmed
paper, itexperimental
is confirmedtests
throughtests tolerant
that the operations
proposed fault
operations at thethroughthat experimental
the proposed fault
at thetoleranthigh-modulation-index
high-modulation-index
continue
to driveone
theofmotor
even thoughof thefails.
inverterDC-buscancontinue to drive thecan
motor
even though
the inverter
DC-busonebatteries
In addition,batteries
fails.characteristics
In addition, thecharacteristics
in thefault
are compared
the normaltheoperation
inoperation
the fault caseare comparedwiththecasenormaloperationwith
characteristics,
operationsome
characteristics,
techniques
reduce the error voltage pulses.
applying
techniquesapplying
to reducesome
the error
voltagetopulses.

Three-Phase
Three-Wire Motor

Chopper

InverterFigure 1. Circuit configuration of conventional single inverter motor drive.
Figure 1. Circuit configuration of conventional single inverter motor drive.

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Relay

Capacitor

Open-EndWinding Motor

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Capacitor Relay

Battery

Battery

INV1 (u1, v1, w1)(u2, v2, w2)’INV2

Figure 2. Circuit configuration of dual inverter motor drive.
Figure 2. Circuit configuration of dual inverter motor drive.

2. Dual Inverter Motor Drive
2. Dual Inverter Motor Drive
2.1. Circuit Configuration

2.1. Circuit
Configuration
The dual
inverter motor drive feeds the open-end winding permanent magnet (PM) motor with
two Theinverters,
where theleft drive
inverteris INV1,
the right
one is INV2
and theswitchingthedual inverter
motor
feeds
the open-end
winding
permanent
magnet(PM)statesmotorofwith
bothinverters
aredescribed
like
(u1,
v1,
w1)
(u2,
v2,
w2)’,
as
shown
in
Figure2.
Intheswitchingstate,
two inverters, where the left inverter is INV1, the right one is INV2 and the switching states of the“1”
upper arm
turnedandvice
leg is operated
Thebothindicates
invertersthat
arethedescribed
likeis (u1,
v1,on
w1)
(u2,
v2,versa.
w2)’,Eachas shown
in Figurecomplementally.
2. In the switchingDC-busofeachinverterhasabattery,acapacitor
and
a
relay
to
isolatethefailedbattery
in
case
that
state, “1” indicates that the upper arm is turned on and vice versa. Each leg is operated
some failure is detectedin the battery.
The dualhas
invertermotor
drive can andgenerate
thetomultilevelcomplementally.
The DC-busof each invertera battery,a capacitor
a relay
isolate thevoltage
failedwaveforms
acrossmotor
windings
by synthesizing
theTheoutputvectors
the twobattery
in casethatthesomefailureis detectedin the battery.
dualvoltage
inverter
motorofdrive
can inverters.
generate
It ismultilevel
expected to
improvethe total acrossharmonic(THD) by
andsynthesizing
the dv/dt of thethe output
output voltage
voltagethevoltage
waveforms
the distortion
motor windings
waveforms,
comparedwith theconventional
2-levelmotor drive.
It is also
expectedtovectorsof thetwo inverters.
It isexpected tosingle
improvethe inverter
total harmonic
distortion(THD)
and theimprovethetotalefficiency
of
the
motor
drive
system,becauseitdoes
notrequireany
voltage-boost
dv/dt of the output voltage waveforms, compared with the conventional single 2-level inverter motor
converter
usedexpected
in manytoofimprove
the hybrid
and electricvehiclesover theC-segment.
Furthermore,thedrive.
It is also
the total
efficiencyof the motor
drive
system, because
it does notdual inverter
motor drive has
redundancy
switchingstates, whichmeans vehicles
that thereoverare several
requireany voltage-boost
converterused inin themanyof the hybrid
and electric
the Cdifferent
switchingstatestogenerateaparticularvoltage
vector.
The
redundancy
makesitpossibletosegment. Furthermore, the dual inverter motor drive has redundancy in the switching states, which
achievethat
somefaultaretolerant
the dualstates
inverterdrive.
means
there
severaloperations
different ofswitching
to motor
generatea particular voltage vector. The

redundancy makes it possible to achieve some fault tolerant operations of the dual inverter motor
2.2. Fault Tolerant Operation of DC-Bus Battery
drive.
2.2.1. Operation Principle
2.2. Fault Tolerant Operation of DC-Bus Battery
In this paper, the fault tolerant operation of the DC-bus Battery is focused on, where it is assumed
that
thebattery of
INV2 fails. In the fault situation, the DC-bus battery of the INV2 is isolated with the
2.2.1. Operation
Principle
relay, if some failure occurs in the battery. Then, the failed INV2 is operated only with the capacitor,
In this paper, the fault tolerant operation of the DC-bus Battery is focused on, where it isinstead of the isolated battery. In this case, it is necessary to control the capacitor voltage constantly andassumed that the battery of INV2 fails. In the fault situation, the DC-bus battery of the INV2 is isolated
to generate multilevel voltage waveforms across the motor windings at the same time. Figure 3 showswith the relay, if some failure occurs in the battery. Then, the failed INV2 is operated only with thethe output voltage vectors and the switching states of the dual inverter motor drive from 0 to 60 degrees,
capacitor, instead of the isolated battery. In this case, it is necessary to control the capacitor voltage
where the capacitor charging and the discharging modes are also described. As shown in Figure 3
constantly and to generate multilevel voltage waveforms across the motor windings at the same time.
and described in Reference [19], the 1:0.5 DC-bus voltage ratio is employed and the capacitor voltage
Figure 3 shows the output voltage vectors and the switching states of the dual inverter motor driveof the INV2 is controlled at half of the battery voltage of the INV1 in the fault situation, because it
from 0 to 60 degrees, where the capacitor charging and the discharging modes are also described. As
cannot switch over the charging mode and discharging mode redundantly in the case of the 1:1 DC-bus
shown in Figure 3 and described in Reference [19], the 1:0.5 DC-bus voltage ratio is employed andvoltage ratio. However, the longest voltage vectors which configure the most outer region do not havethe capacitor voltage of the INV2 is controlled at half of the battery voltage of the INV1 in the fault
the redundancy, even if the 1:0.5 ratio is employed. Therefore, in the fault tolerant operation of thesituation, because it cannot switch over the charging mode and discharging mode redundantly in the
DC-bus battery, the longest voltage vectors cannot be used for the SVM, in other words, the operationcase of the 1:1 DC-bus voltage ratio. However, the longest voltage vectors which configure the mostvoltage region of the fault condition of the DC-bus battery is limited within the modulation-index
outer region do not have the redundancy, even if the 1:0.5 ratio is employed. Therefore, in the fault
m = 0.5.
tolerant operation of the DC-bus battery, the longest voltage vectors cannot be used for the SVM, inother words, the operation voltage region of the fault condition of the DC-bus battery is limited
within the modulation-index m = 0.5.

World Electric Vehicle Journal 2019, 10, x FOR PEER REVIEWWorld Electric Vehicle Journal 2019, 10, 65
World Electric Vehicle Journal 2019, 10, x FOR PEER REVIEW(000)(001)’(-) (110)(001)’(-)(111)(001)’(-) (110)(001)’(-)(000)(001)’(-)(010)(011)’(-)(111)(001)’(-)(100)(101)’(-)(010)(011)’(-)(110)(000)’(0)(100)(101)’(-)(110)(111)’(0)(110)(000)’(0)(110)(111)’(0)(000)(000)’(0)(000)(111)’(0)(000)(000)’(0)(111)(000)’(0)(000)(111)’(0)(111)(111)’(0)(111)(000)’(0)(001)(001)’(0)(111)(111)’(0)(010)(010)’(0)(001)(001)’(0)(100)(100)’(0)(010)(010)’(0)(011)(011)’(0)(100)(100)’(0)(101)(101)’(0)(011)(011)’(0)(110)(110)’(0)(101)(101)’(0)(110)(110)’(0)4 of 15
4 of 15
4 of 15(100)(001)’(-)(110)(011)’(-)(100)(001)’(-)(110)(011)’(-)(110)(000)’(0) (110)(001)’(-)(110)(111)’(0)(110)(001)’(-)(110)(000)’(0)(110)(011)’(-)(000)(001)’(-)(110)(111)’(0)(110)(011)’(-)(100)(101)’(0)(111)(001)’(-)(000)(001)’(-)(110)(010)’(0)(100)(101)’(0)(110)(110)’(+)(111)(001)’(-)(110)(010)’(0)(000)(000)’(0)(110)(110)’(+)(100)(001)’(-)(000)(111)’(0)(000)(000)’(0)(100)(001)’(-)(111)(000)’(0) m = 0.25 m = 0.5 m = 0.75(000)(111)’(0)(111)(111)’(0)(111)(000)’(0)(100)(011)’(-)
m = 0.25 m = 0.5 m= 0.75(000)(011)’(-)(100)(000)’(0)(111)(111)’(0)(100)(011)’(-)(111)(011)’(-)(000)(011)’(-) (100)(000)’(0)(100)(111)’(0)(100)(100)’(+) (100)(111)’(0)(111)(011)’(-)(+): Charging Mode(100)(100)’(+)(‐): Charging
Discharging
Mode
(+):
Mode
(0): Discharging
Holding Mode
(‐):
Mode
(0): Holding Modem = 0.5m = 1.0(000)(011)’(-)
m = 0.5 (100)(011)’(-)
m = 1.0(111)(011)’(-) (100)(011)’(-)(000)(011)’(-)(101)(001)’(-)(111)(011)’(-)(110)(010)’(-)(101)(001)’(-)(100)(000)’(0)(110)(010)’(-)(100)(111)’(0)(100)(000)’(0)(100)(111)’(0)(a) 1:1 DC-bus voltage ratio(a) 1:1 DC-bus voltage ratio(b) 1:0.5 DC-bus voltage ratio(b) 1:0.5 DC-bus voltage ratio

Figure 3. Redundant switching states and capacitor charging and discharging modes.
FigureFigure 3.
3. Redundant
Redundant switchingswitching statesstates andand capacitor
capacitor charging
charging andand discharging
discharging modes.
modes.

2.2.2. Capacitor Voltage Control with SVM
Capacitor Voltage
Voltage Control with SVM
2.2.2. Capacitor
In this system, the SVM is employed to achieve both of the capacitor voltage control and theIn thisvoltage
system,waveformthe SVM generation
is employedto achieve bothof switching
the capacitor
voltagemultilevel
simultaneously.
The
sequenceof control
the SVMand
canthebemultilevel
voltage
waveform
generation
simultaneously.
The
switchingsequence
of
the
SVM
can
be
configured flexibly. Therefore, when the command voltage vector is generated with the SVM, theconfigured
flexibly.
Therefore,
whenthecommandvoltageisgenerated
withthe SVM,
thewhich
SVM
configured
flexibly.theTherefore,
whenthecommandvoltage
vectoris generated
with
the
SVM,
the
SVM can control
capacitor
voltagebyselectingthevector
mostappropriate
switchingstate
cancontrol
the capacitor
voltageby appropriately
selectingthe most
appropriate
switchingstate4whichchargesor
SVM
canorcontrol
the thecapacitor
voltageby selecting
themost appropriate
switching
state
which
chargesdischarges
capacitor
in theredundant
states. Figure
assumesthatthedischarges
thecapacitor
appropriately
intheredundant
states.
Figure4assumes
that
the
dual
inverterchargesordischarges
thecapacitor
appropriately
intheredundant
states.
Figure4assumesthatthedual inverter motor drive generates the command voltage vector v* in the hatched sector with the
motor
drive
generates
thethreecommandvoltage
vectorv*voltagein thesectorwiththe hatched
SVM,
forsector
example.
dual
motorThe
drive
generatesthecommandvectorv*
in thehatchedsectorwith
the
SVM,inverterforexample.
voltage
vectors
V0, V0inandhatched
V30 surrounding
the
are
The
three
voltage
vectors
V0,
V0in
and
V30
surroundingthehatchedsectorareutilized
tosynthesize
SVM,
for
example.
The
threevoltage
vectors
V0,
V0in
and
V30
surroundingthehatchedsectorareutilized to synthesize the v*. In the SVM, the time durations of each voltage vector utilized in thethev*.areIntoalsothe
SVM,
thethetime
ofswitchingeach
vectorcase
utilized
involtage
the SVM
are also
calculated.
utilized
synthesize
v*.durations
Inthe SVM,
the voltage
timesequence
durationsof eachutilizedin theSVM
calculated.
The
particularof theSVM
isvector
consideredin FigureThe
particularswitchingsequence
case
of
the
SVM
is
consideredin
Figure
5.
As
shown
in
Figure5,SVMalsoincalculated.
The particularswitchingsequencecase of the SVM
is considered
Figure5. As areshown
Figure 5, whenthe voltage
vector V0inis generated,discharging
mode isinselectedwhenthevector
V0inbecauseisthe discharging
isthe
selected
among
thevalue.
redundant
5.
As shown
in Figure
5,states
whenthegenerated,voltage
vectorV0in
is generated,discharging
mode
is selectedamong
thevoltage
redundant
the capacitor
voltageismodehigherthan
its commandThen,statesbecausethecapacitor
voltageishigherthanitscommandvalue.
Then,
when
the
next
voltageamongthenext
redundant
the capacitor
is higher
its command
value.
Then,
when thevoltagestates
vectorbecause
V30 is generated,thevoltage
charging
mode isthan
selected
because thecapacitor
vectorV30
is generated,thecharging
mode Inis selected
becausethe capacitor
voltage
lower
than
when
the
voltage
vector
V30 is value.
generated,theway,charging
mode
isvoltage
selected
becausethe capacitor
voltageis next
lower
than thecommandthisthe capacitor
can
be is
controlled
at thethecommandvalue.
In
this
way,
the
capacitor
voltagecanbecontrolledatthecommandvalue,
while
voltage
is
lower
than
the
commandvalue.
In
this
way,
the
capacitor
voltagecanbecontrolledatthecommand value, while generating the multilevel voltage waveforms to the motor simultaneously
generating
the multilevel
voltage waveforms
to thevoltage
motor simultaneously
withmotor
the SVM.
commandvalue,
while generating
the multilevel
waveforms to thesimultaneouslywith the SVM.
with the SVM.

V60
V60
V30
V30m = 0.5

V60in
V60in
Vz
Vz

v*
v*

V0in
V0in

m = 0.5

V0
V0

Figure 4. Operation principle of support vector machine (SVM).
Figure 4. Operation principle of support vector machine (SVM).
Figure 4. Operation principle of support vector machine (SVM).

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SVM 1 Period

V0

V0in

V0

(000)(011)’(-)
V0in(100)(000)’(0)(111)(011)’(-)(100)(111)’(0)(100)(100)’(+)(100)(000)’(0)SVMV301 Period

V0in

V30

(000)(011)’(-)
V0in(110)(010)’(-)(000)(011)’(-)(100)(111)’(0)(000)(011)’(-)(100)(101)’(+)(111)(011)’(-)(100)(100)’(+)(100)(100)’(+)

Discharge

Hold(+): Charging Mode

Discharging(+): (-):
Charging
Mode Mode
Discharge(-): (0):Discharging
HoldingMode
Mode
Discharge (0): Holding Mode

ChargeDischarge

・・・(111)(011)’(-)(100)(101)’(+)(100)(100)’(+)

Hold

・・・

(111)(011)’(-)(110)(010)’(-)

ChargeCapacitor Voltage

Capacitor Voltage Command

Capacitor Voltage

Capacitor Voltage Command

FigureFigure 5.
5. Redundant switching states andand capacitor
capacitor charging
charging andand discharging
discharging operation.
operation.
Figure 5. Redundant switching states and capacitor charging and discharging operation.

However,theinstantaneous
factorhasananimpact
impactcapacitor
However,thetheinstantaneous
motor
power
factorhas
voltagecontrol.
However,
instantaneousmotor
motorpower
power factor
on onthethecapacitor
voltagecontrol.
Figure6shows
thevoltage
vectorsofthedual
inverter
motor
drive
from
−60
to
120
degrees,which
isFigure6shows
thevoltage
vectorsofthedual
inverter
motor
drive
from
−60
degrees,which
isFigure 6 shows the voltage vectors of the dual inverter motor drive from −60 to 120 degrees, which is
the
same
case
as
Figure4.
Inthefigure,thecurrent
polarityisalso
described,
which
isdefinedbythethe same
as Figure
is is
also
described,
which
is definedby theby thethe same
casecase
as Figure4. 4. In the figure, the current
currentpolarity
polarity
also
described,
which
is defined
directions
of
the
motor
linecurrents.
currents.
The capacitor
charging
anddischarging
modesof switchingeach
directions
ofofthemotor
linelinecurrents.
The capacitor
chargingand discharging
modes
ofmodeseach
directions
the
motor
The
capacitor
charging
anddischarging
of eachswitching
state
can
be
determinedbythecurrent
directionofthecapacitor,
that
is,
the
current
polarity.
state
can
be
determinedbythecurrent
directionofthecapacitor,
that
is,
the
current
polarity.
Since
theswitching state can be determined by the current direction of the capacitor, that is, the current polarity.
Since
the
motor
is
assumedtobeaninductive
load,
the
phase
of
the
motor
line
current
vectorismotor
is assumed
be an inductive
load,
the phaseof thevectordelayedvector
at mostSince themotor istoassumed
to be aninductive
load,
themotorphaselineof current
the motor
lineiscurrent
isdelayedat most 90 degreewithrespect
to the output voltage
On the inother hand,in themaximum
case
90
degreeto theoutputvoltagethevector.
other
hand,
casehand,that
delayedatwithmostrespect
90 degreewithrespect
to thevector.
outputOn
voltage
vector.
On thetheotherin the casethat maximum torque per ampere (MTPA) control or field-weakening control is employed, the phasetorqueper ampere(MTPA)
control(MTPA)or field-weakening
control is employed,phase of thecurrent
that ofmaximum
torqueper ampere
control or field-weakening
controlthe
is employed,
the
phase
the current vector is advanced with respect to the output voltage vector. Therefore, the current
vectorisadvancedwithrespect to withthe output
voltage
vector.
Therefore,
the current
polarity
can beof thecurrent
vectorisadvancedrespecttotheoutputvoltage
vector.
Therefore,
thecurrent
polarity can be classified to F, A, B or C, in the case that the voltage vector v* is generated with theclassified
toF,
B orshows
C, in
the
case
that
the
voltage
vectoris generated
with
the SVM.
Figure6polaritybeA,
classified
to theF, A,
B or
C,voltagein thecase thatthev*
voltagev* isswitching
generatedwith theSVM.canFigure6 alsocapacitor
control
modes
of
the
twovector
redundant
states
also
shows
the
capacitor
voltagecontrol
modes
of
the
two
redundant
switchingstatesgenerating
the
SVM.
Figure 6 thealsovoltage
showsvector
the capacitor
voltage control
theistwo
redundant modeswitching
generating
V30. The switchingstate (1,modes
1, 0) (0, of
1, 0)’
the discharging
in the states
voltage
vector
V30.
The
switchingstate1, 0) (0, the1,0)’is thedischarging
mode
in charging
the current
polarity
current
polarityA andF, forV30.
example.
However,
identical
switching
state
the
mode
generatingthevoltage
vectorThe (1,switching
state
(1,
1, 0)
(0, 1, 0)’ is
theisdischarging
mode
in theinthecurrent
polarityB
andF.
Therefore,
theinstantaneous
motor
power
factormust
beconsidered
A
and
F,
for
example.
However,theidentical
switching
state
is
the
charging
mode
in
the
current
current polarity A and F, for example. However, the identical switching state is the charging modeto current
selectthecharging
or discharging
mode among
redundant
statesinthe capacitor
polarity
B andF.capacitor
Therefore,
theinstantaneous
motor
power thefactormust befactor
considered
select thein thepolarity
B and
F. Therefore,
the instantaneous
motor
power
must
betoconsidered
voltagecontrolasdescribed
inReference[18].
capacitor
charging
or discharging
mode
among theredundant
in the capacitorasto select thecapacitor
charging ordischarging
mode
amongstates
the redundantstatesvoltage
in the control
capacitor
described
inReference[18].
voltage control as described in Reference [18].
Redundant switching states generating V30
Current
Polarity C
U－
Current
V＋
PolarityW
C−

U－
V120
V＋
W−

V60

ic

V60inV60

V120inic

V120in

V60in

ib

*

ia

V0in

Vz
V300in

if

V0in

Vz
＋: Current direction from INV1 to INV2－: Current direction from INV2 to INV1

V300in V300
if＋: Current direction from INV1 to INV2－: Current direction from INV2 to INV1

Current
Polarity

C

U＋
V＋
W−

ib

V120

Current
Polarity

Current
Polarity B
U＋
Current
V＋
Polarity
W− B

ia

v

v*

C

V30
Current
Polarity A
U＋V－
Current
W−

B

Polarity A
U＋
V330
V0
V－
W−
Current
Polarity F
U＋
VV330
−
W＋

Current
Polarity F(1, 1, 0) (0, 1, 0)’
V＋

U－
W－

A

F

V－

W－

V＋

Charging

W－

V＋
U＋

Discharging
V－

V＋
Discharging

WCharging
－

W－

V－

V－

U＋

U＋

Charging

Charging

W－

U＋

W＋

W－
W＋

Discharging

V＋
U＋

Discharging

Discharging
V－

F power factor.
Figure 6. Impact of instantaneous motor
U＋
V300
V−
W＋

U＋

Charging

U＋A(1, 0, 0) (1, 0, 1)’
U － Discharging

Charging W －
V＋
U＋

U＋

W－

W－

Charging

U －V ＋

U＋W－

B(1, 0, 0) (1, 0, 1)’
U－

DischargingV30
Redundant switching states generating

W－

V30
V0

(1, 1, 0) (0, 1, 0)’
V＋

U＋

W＋

Discharging

Figure 6.
6. Impact of instantaneous motor power
power factor.
factor.
FigureV－
UV＋－

Charging

W＋
V－World Electric Vehicle Journal 2019, 10, x FOR PEER REVIEWWorld Electric Vehicle Journal 2019, 10, x FOR PEER REVIEWWorld Electric Vehicle Journal 2019, 10, 65

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6 of 15

2.3. Switching Over Techniques for Fault Tolerant Operation of DC-Bus Battery
2.3. Switching Over Techniques for Fault Tolerant Operation of DC-Bus Battery
2.3. Switching
Techniques
for for
Fault
Tolerant
Operationof DC-Bus
Battery
2.3.1.
SwitchingOver
Over
Technique
Fault
Tolerant
Operation
at Low-Modulation-Index
2.3.1. Switching Over Technique for Fault Tolerant Operation at Low-Modulation-Index
this section,
theTechniquefailure of thebatteryOperationin the INV2
assumed. In the normal operation
2.3.1.InOver
for DC-bus
Fault
Tolerant
at is
Low-Modulation-Index
InSwitching
this section,
the failure of theDC-busbattery in the INV2
is assumed. In the normal operationof the dual inverter motor drive, both of the DC-bus battery voltages are same. However, once theof theIndual
inverterthe
motor drive,
bothof the DC-bus
battery
voltagesare same.
However,
once thethis section,of theDC-busin theINV2
is assumed.
In theisnormaloperationoffailureoccurs,the INV2failure
is operated
with thebattery
capacitorandthe capacitor
voltagecontrolled
at half
failureoccurs,theINV2isoperatedwiththecapacitorandthecapacitor
voltageiscontrolled
at
half
the
dual
invertermotor
drive,
bothof
theDC-busbattery
voltagesaresame.
However,once
thefailureof the battery voltage of the INV1, in order to take advantage of the redundancy in the switchingof
the battery
voltageof the INV1,
in capacitor
order to takeadvantageof voltage
the redundancy
in theswitchingoccurs,the Therefore,
INV2
is operated
with theandthecapacitor
controlled
at half
of thethestates[19].
it is required
to discharge
thecapacitor
voltage ofis theINV2 down
tostates[19].
Therefore,
itisrequiredtodischarge
thecapacitor
voltage
of
the
INV2
down
to
the
battery voltage
the INV1, inafterorder
tofailed
take advantageof theredundancy
the switchingstates [19].
commandvalue,ofimmediately
thebattery of theINV2
is isolatedinwith
the relay. However,commandvalue,
immediately
after thefailedbatteryof the ofINV2isisolatedwiththe command
relay. However,
Therefore,
itisrequiredtodischarge
thecapacitor
voltage
the
INV2
down
to
the
value,
in this time, a current flows into the battery of the INV1, which is in the normal condition, in order
to
in
this
time,
a
current
flows
into
the
battery
of
the
INV1,
which
is
in
the
normalcondition,
in
order
to
immediately
after
the
failedbattery
of
the
INV2
is
isolatedwiththerelay.
However,
in
this
time,
discharge the capacitor voltage of the INV2. Besides, the amplitude and the phase of the voltagea
discharge
thecapacitor
voltage
of
the
INV2.
Besides,theamplitude
and
the
phase
of
the
voltagecurrent generated
flows into theof inverter
the INV1,motor
whichdrive
is in thenormal condition,in orderto discharge
vectors
by battery
the dual
is changed
because thecapacitor
voltagetheisvectors
generatedbythedualBesides,
inverterthe
motor
drive andis changed
becausethe capacitor
voltageiscapacitor
voltage
of
the
INV2.
amplitude
the
phase
of
the
voltage
vectors
generateddischarged. Therefore, it is necessary to select the voltage vectors which synthesize the command
discharged.
Therefore,
it isdrive
necessaryto select
the thevoltage
vectorswhich
synthesize the commandby the dual
invertermotor
is changed
becausecapacitor
voltageis discharged.
it isvoltage
vectorand tocalculatethetime durationsof eachvoltage
vector,considering Therefore,
the capacitor
voltage
vectorandtocalculatethetimedurationsofeach
voltage
vector,considering
thecapacitor
necessarytoselectthevoltage
vectorswhich
synthesize
thecommandvoltage
vectorandtocalculatevoltage.
voltage.
the timedurationsof eachvoltagethecapacitor
voltage.
Figure7 and Figure
8 show
thevector,
voltageconsideringvectors from0 to
60 degrees
in the case of the modulationFigure
7
andFigure8
showthevoltage
vectors
from
0
to
60
degreesin theofcasethe modulationFigures
7
and
8
show
the
voltage
vectors
from
0
to
60
degreesinthetheofmodulation-index
index 0 < m ≤ 0.25 and 0.25 < m ≤ 0.5, respectively. In both figures, the casecommandvoltage vector is
index
0
<
m
≤
0.25
and
0.25
<
m
≤
0.5,
respectively.
In
bothfigures,thecommandvoltage
vector is
0 < m ≤ 0.25<m≤
0.5, respectively.
both figures,commandvectorareis generated
generatedin andthe 0.25
hatchedsector.
The voltageInvectorsof the thedual
invertervoltage
motor drive
variable
generatedin thehatchedsector. vectors
The voltage
vectorsof themotor
dual inverter
motor drive
are variablein the hatched
The voltage
inverterareofvariable
dependingonare
thedependingon sector.
the capacitor
voltage, thatof
is,thethedualamplitude
and thedrivephase
each voltage
vectordependingon the thatcapacitor
voltage,thatandis, theamplitude
andvoltage
the phaseof eachvoltage vector
arecapacitor
voltage,is,theamplitude
the
phase
of
each
vectorarechanged.
Therefore,changed. Therefore, the SVM must be implemented, considering the capacitor voltage, as describedchanged.
Therefore,
the SVM must
be implemented,
considering
the capacitor
voltage,as described
theReference
SVM must
be In
implemented,
considering
the capacitor
voltage,
described
Reference[20].the
In
in
[20].
the case of themodulation-index
0<m≤ 0.25,asthe
SVM is inconducted
within
Reference
[20].
In
the
case
of
the
modulation-index
0
<
m
≤
0.25,
the
SVM
is
conducted
withthethe caseof themodulation-index
0 <Onm≤thehand,SVMin
is theconducted
withthe three voltage0.25
vectors
three
voltage
vectorsVz, Va and Vb.
the0.25,
othercase of themodulation-index<mthreevoltage
vectorsVz,otherVa andVb. inOnthethecaseother
hand,
in the case of the modulation-index
0.25
<m
Vz,
Va
and
Vb.
On
the
hand,
of
the
modulation-index
0.25
<
m
≤
0.5,
the
SVM
≤ 0.5, the SVM is conducted with the three voltage vectors selected among the six voltage vectors Va,is≤0.5, the SVM
isthe
conducted
with thethreeselectedvoltage among
vectors theselected
amongvectors
the six Va,
voltage
vectors
conducted
threevoltage
vectors
voltageVa’,
Vb,
Vb’,Va,Vc
Va’,
Vb, Vb’,with
Vc andVc’. Theswitchingover operation
for thesix
fault
tolerant functionof theDC-bus
Va’,
Vb,
Vb’,
Vc
and
Vc’.
The
switchingoveroperation
for
the
fault
tolerant
functionoftheDC-busand Vc’.inTheover operationmfor
tolerant
function
theSVM
DC-busthebattery
the switching
low-modulation-index≤ the
0.5 fault
can beachieved
withoftheby battery
selectingin thebatteryin the low-modulation-indexm ≤ 0.5 withcan beachievedwith the theSVM
by selecting
thelow-modulation-index
m
≤
0.5
can
be
achieved
theSVM
byselectingappropriate
voltageappropriate voltage vectors which discharge the capacitor voltage and calculating the time durations
appropriate
voltage
vectors
which discharge
thevoltage and calculating the time durations
vectorswhich
discharge
the capacitor
voltageandcapacitor
calculatingofeach voltage
vector, dependingon thecapacitor
voltage. the time durations of each voltage vector,ofeachvoltage
vector,dependingonthecapacitor
voltage.
depending on the capacitor voltage.

Vb
Vb
|v*|
|v*|
Vz
Vz

Vb
Vb

Vb
Vb
Vz
Vz

Vz
Vz

Va
Va
Vdc2 = Vdc1
Vdc2 = Vdc1

Va
Va

Vb
Vb
Vz
Vz
Va
Va

Va
Va
Vdc2 = Vdc1/2
Vdc2 = Vdc1/2

Figure 7.
7. Switching
Switchingover
overtechnique
techniquefor
forfault
faulttolerant
tolerantoperation
operation inin casecase ofof 00 <<mm≤≤0.25.
0.25.
FigureFigure 7. Switching over technique for fault tolerant operation in case of 0 < m ≤ 0.25.

Vb,Vb’,Vc’
Vb,Vb’,Vc’
|v*|
|v*|
Vz
Vz
Va,Va’,Vc
Va,Va’,Vc
Vdc2 = Vdc1
Vdc2 = Vdc1

Vc
Vc

Vb’
Vb’Vc’
Vc’
Vb
Vb
Vc
Vc

Va Va’Va Va’Va Va’Va Va’

Vb’
VbVb’ Vc’
Vc’
Vb

Vb’
Vb’
Vb
Vc,Vc’
Vb
Vc,Vc’Va Va’Va Va’
Vdc2 = Vdc1/2
Vdc2 = Vdc1/2

FigureFigure 8. Switching
Switching over
over technique
technique forfor fault
fault tolerant
tolerant operation
operation in case of 0.25 <<mm≤≤0.5.
0.5.
Figure 8. Switching over technique for fault tolerant operation in case of 0.25 < m ≤ 0.5.

World Electric Vehicle Journal 2019, 10, 65

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2.3.2. Switching Over Technique for Fault Tolerant Operation Employing Field-Weakening Control at
High-Modulation-Index
The voltage region for the fault tolerant operation is limited within the modulation-index m ≤ 0.5,
because the voltage vectors that configure the most outer region have no redundancy as described in
Section 2.2.1. In other words, it is difficult to switch over the dual inverter motor drive to the fault
situation at the high-modulation-index m > 0.5, while providing the constant output power to themotor. Therefore, in this paper, the SVM technique employing the field weakening control for the fault
tolerant operation in the high-modulation-index is newly proposed. In the proposed technique, theamplitude of the command voltage vector is reduced within the controllable voltage region of thefault tolerant operation by weakening magnetic flux of the PM motor with the d-axis current. The
d-axis current command i∗d is determined by the Equation (2), which is calculated from the generalvoltage equation of the motor (1). In the equations, |v∗f w | indicates the amplitude of the voltage vector
command with the field-weakening, vd and vq indicate the d-axis and the q-axis voltages, iq indicatesthe q-axis current, Ld and Lq indicate the d-axis and the q-axis inductances, R, ω and Ψ indicate thephase resistance, the rotating speed and the number of a flux linkage of the motor, respectively. The|v∗f w | is determined to be controllable by the fault tolerant operation, that is, the modulation-index
m < 0.5. However, in the Equation (2), the nominal values of the Ld and the Lq are used to calculate thei∗d and the calculation of the i∗d is implemented with an open loop. In this case, the calculation of thei∗d cannot be implemented accurately, because the Ld and the Lq can be fluctuated due to a magnetic
saturation. Therefore, the accurate identification of the Ld and the Lq is necessary to calculate i∗d in the
proposed fault tolerant operation in the high-modulation-index case. In Reference [23], an on-line
identification technique of the Ld and the Lq is presented. The accurate calculation of the i∗d can beachieved with the identification technique but the practical application of the identification technique
is one of our future works.
"

vd
vq

#

"

=

R + pLd
ωLd−ωLq
R + pLq

#"

id
iq

#

"

+

v
u
u

2
u
u
u
!
t v∗ 
Lq 2 2
 f w Ψ∗
id = − ± i − ωLd 
Ld
Ld q

0
ωΨ

#
(1)

(2)

Then, after the voltage vector command is controlled to be within the modulation-index m < 0.5
with the proposed SVM technique, the dual inverter motor drive in the fault situation is controlleddepending on the SVM technique for the fault tolerant operation in the low-modulation-index.
However, in the case that the negative d-axis current flows, the phase of the motor line current vector
is advanced with respect to the command voltage vector. Therefore, the capacitor voltage control
with the SVM must be conducted, considering the phase difference between the line current and thecommand voltage vectors as described in Section 2.2.2.
2.4. Impact of Dead Time in Dual Inverter Motor Drive
2.4.1. Error Voltage Vector During Dead Time
The SVM of the fault tolerant operation of the DC-bus battery in the dual inverter motor drive has
particular switching transitions, which generates unexpected error voltage pulses in the multilevel
voltage waveforms during a dead time. For example, synchronously turning off of upper arms in thesame phase of both inverters is shown in Figure 9, where the devices in the same phase are switchedover from the switching state A to the switching state B. In the designed SVM sequence, the switchingstate A must be changed to state B directly. However, unexpected error voltages can be generated
during a dead time. The switching state during the dead time is determined by the motor line current
direction, because the gate signal “0” are inputted to the switching devices of upper and lower arms ofWorld Electric Vehicle Journal 2019, 10, x FOR PEER REVIEW

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World Electric Vehicle Journal 2019, 10, x FOR PEER REVIEW

8 of 15

motor line current direction, because the gate signal “0” are inputted to the switching devices ofWorld Electric Vehicle Journal 2019, 10, 65
8 of 15
upperof bothbecause
inverters.
devices
areswitchingturned ondevices
with themotor andline lower
currentarms
direction,
the Therefore,gate signalthe“0”switchingare inputtedto theofdiodethe deadIn theswitchingstate during
the dead timeof theupperduring
and lower
armstime.
of bothinverters.
Therefore,
the switching
devicesare synchronously
turned on withturn
thebothasinverters.
Therefore,
the Inswitching
are turned
on
with
diode
duringtheofdead
time.
In
off,
shown
Figureupper
armdevicesof thestate
INV1
is turned
off thebuttimethe ofupper
arm
the INV2
isdiodeduring inthedead 9,time.
the switching
duringthedead
the synchronously
turntheswitchingstate
during
the
dead
time
of
the
synchronously
turn
off,
as
shown
in
Figure9,
theupper
turned
on,
which
is
an
unexpectedswitchingstate
during
the
dead
time.
The
unexpectedswitchingoff, as shown in Figure 9, the upper arm of the INV1 is turned off but the upper arm of the INV2 isarm oftheINV1
off butinthearm
the INV2
is turned
which
an unexpectedstatecauseserror isvoltagepulsestheuppermultilevel
voltage
waveforms
ason,
shown
in is
Figure10.
In theturnedon, whichisturned
an unexpectedswitchingstateofduringthe deadtime.
The
unexpectedswitchingswitchingstate
during
the
dead
time.
The
unexpectedswitchingstatecauseserror
voltagepulsescaseofgenerating
thecommandvoltage
vectorinthehatchedsector,thethreevoltage
vectors
state causes error voltage pulses in the multilevel voltage waveforms as shown in Figure 10. InV30,
thein thewaveforms
asand
shown
in
10.
In sector,
the iscaseofthreegenerating
thecommand
V60
and
V60in arevoltage
utilized
for the voltage
SVM
the switchingsequence
configured
as shown
in Figurecase
ofmultilevel
generating
the command
vectorinFigure
the hatchedthevoltage
vectors
V30,
voltage
vectorthehatchedtheandthree
vectors
V30,
V60
and
V60in
areshown
utilized
the10,
example.
The
designed
SVM
sequence
isvoltage“V60in
→ V30
→
V60
V60in
∙∙∙”, however,
the
error
V60forand
V60ininareutilized
forsector,
the SVM
theswitchingsequence
is→configuredasin forFigureSVM
andtheswitchingsequenceisconfigured
as
shown
in
Figure10,
forexample.
The
designed
SVM
voltage
vectorssuch
as
V120in,
V0
and
Va
are
generated
during
the
dead
time
due
to
the
particular
10, for example. The designed SVM sequence is “V60in → V30 → V60 → V60in ∙∙∙”, however, the error
sequence
is “V60in
→ V60
···”,
however,during
the error
vectorssuch
V120in,switchingtransitions.
voltage
vectorssuch→
asV30
V120in,V0 →andV60in
Va aregeneratedthe voltage
dead time
due tothe asparticular
V0
and
Va
are
generated
during
the
dead
time
due
to
the
particularswitchingtransitions.
switching transitions.
INV1
1
1

INV1

INV2
i

INV2
1

i

1
0

0
0

INV1

Switching State A
Switching State A

0

0
INV2

0

i

INV2
1

1

i

1

1

INV1
0
0

INV1

0

1
1

Dead-Time

INV1

INV2
i

INV2
0

i

0
1

Switching State B

1

Switching State B

0

Dead-Time
Figure 9. Synchronously switching transitions in same phase of dual inverter motor drive.
Figure 9. Synchronously switching transitions in same phase of dual inverter motor drive.
Figure 9. Synchronously switching transitions in same phase of dual inverter motor drive.

Figure10.
10.Error
Errorvoltage
voltagevectors
vectorsduring
duringdead
deadtimetimeofofsynchronously
synchronouslyturn
turnononor
oroff.
off.
FigureFigure 10. Error voltage vectors during dead time of synchronously turn on or off.

World Electric Vehicle Journal 2019, 10, 65

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2.4.2. SVM Techniques to Reduce Error Voltages
The dead time scheme to avoid the error voltage vectors during the dead time is introduced in
Reference [21]. In order to avoid the error voltage vectors, the dead time of each inverter is generated
alternately as shown in Table 1, where the synchronously turn off is also assumed. The p1 and the p2
indicate the gate signals of the upper arms of the INV1 and the INV2 and the n1 and the n2 indicate
the gate signals of the lower arms of the INV1 and the INV2, respectively. Moreover, the line current
is assumed to flow from the INV1 to the INV2. In the state #2, a first dead time is generated to theinverter where the line current flows into, that is, the INV2. In the state, the upper arm of the INV1
keeps turn on and the upper arm of the INV2 is also turned on with the diode because the INV2 isduring the first dead time. Then, at the end of the first dead time, a second dead time is generated tothe other inverter, that is, the INV1. In state #3, the lower arm of the INV1 is turned on with the diode,because the INV1 is during the second dead time. On the other hand, the lower arm of the INV2 is also
turned on, because the INV2 is after the first dead time. That is, the switching states in the same phaseof the both inverters are changed from “1” to “0” directly. In this way, the dual inverter motor drive
can be synchronously turned on or off without the error voltage vectors during the dead time.
Table 1. Dead time scheme of dual inverter motor drive.
INV1

State
#1
#2
#3
#4

INV2

Phase Voltage

p1

n1

p2

n2

1
1
0
0

0
0
0
1

1
0
0
0

0
0
1
1

Vdc1 − Vdc2
Vdc1 − Vdc200

The error voltage vectors are generated in other particular switching transitions, for example, theswitching devices in the several phases of one inverter are synchronously turned on or off, even if
the above dead time scheme is employed. Figure 11 shows the same situation as Figure 10. It also
describes whether the error voltage vectors are generated during the dead time of every switchingtransition, where “#” means that the error voltages are not generated and the “×” means that the error
voltages are generated even if the above dead time scheme is employed. As shown in Figure 11, theerror voltage vector is sure to be generated in the switching transition between V60 and V60in.
A conventional SVM sequence, which is based on a general triangular-wave pulse widthmodulation (PWM), has seven switching states in one control period, that is, it cannot avoid theswitching transition between V60 and V60in. On the other hand, it is possible to avoid the transition by
designing the SVM sequence to have five states as described in Reference [22]. The block diagram andthe algorithm of the SVM sequence which has five states are the same as the conventional sequence,for example, the capacitor charging or discharging mode of each switching state. Only the calculation
method of the time durations of the voltage vectors used in the SVM is different from the conventionalsequence. In this system, both the dead time scheme and the SVM sequence that has five states are
employed, in order to reduce the error voltage vectors in the multilevel voltage waveforms.

World Electric Vehicle Journal 2019, 10, 65
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Figure 11.
11. SVM
SVM sequence
sequence toto reduce
reduce error
error voltage
voltage vector
vector during
during deadFiguredead time.
time.

3. Experimental Results and Discussion
3. Experimental Results and Discussion
3.1. Experimental Setups
3.1. Experimental Setups
Experimental setups of the dual inverter motor drive are conducted as shown in Figure 12 andExperimentalof the dual
invertermotor
drive13.
areTheconducted
shown
in Figure
12 andTable 2. The controlsetups
brock diagram
is alsoshown
in Figurespeed ofas
thetest motor
is regulated
Table
2.
The
controlbrock
diagram
is
also
shown
in
Figure
13.
The
speed
of
the
test
motor
is
regulated
at 1180 r/min with the load motor which is connected to the test motor. The test motor with theat1180 r/min
with themotor
is connected control
to the test
motor.
The test
motor with
theopenopen-end
windings
is loadoperatedbywhichthe field-oriented(vectorcontrol)algorithm
with
the
two
end
windings
isoperatedbythefield-oriented
control(vectorcontrol)algorithm
with
the
two
inverters. The rated output power of the test motor and the inverters are 1 kW and 5 kW, respectively.
inverters.
rated
outputpowertheof DC-bus
the test motor
the inverters
are In1 kW
5 kW,
respectively.
The
INV2 The
has therelay
to isolate
batteryand
acrossthe DC-bus.
the andnormaloperation,
both
The
INV2
has
the
relay
to
isolatetheDC-busbattery
acrosstheDC-bus.
Inthenormaloperation,bothinverters are operated with the battery across each DC-bus whose voltages are set at 100 V and the test
inverters
are operated
thecontrol
batteryeach condition
DC-bus whose
are set at 100
andthemotor is operated
with with
MTPA
inacrossthe normal
at the voltages
modulation-index
m =V
0.8.
Then,
test
motor
is
operated
with
MTPA
controlinthenormalconditionatthemodulation-indexm=
0.8.
after the fault signal is detected, the system is switched over to the fault situation where the INV2 is
Then,
after
thewithfaultthesignalis detected,
systemis switched
over
fault
where
operated
onlycapacitor.
In this thetime,
the capacitor
voltageof tothetheINV2
is situation
discharged
downthetoINV2
isoperated
only
with
the
capacitor.
In
this
time,
the
capacitor
voltage
of
the
INV2
is
discharged
50 V with the SVM and the test motor is operated by field-weakening control utilizing the negativedown
to 50 V inwiththetoSVM
andthetheamplitude
test motorofisthe
operatedby field-weakening
controlthed-axis current
order
reducecommandvoltage vector within
theutilizing
controllable
negativeregion
d-axisof
current
in order to reduce
amplitudeof thecommandvoltage
vector
withinandthevoltagethe modulation-index
m <the0.5.
On the otherhand,
the q-axis
current
commandcontrollable
voltageregionofthemodulation-index
m
<
0.5.
On
the
other
hand,
the
q-axiscurrent
the motor rotating speed are constant between the normal operation and the fault tolerant operation;commandand themotor rotating
are inverter
constantmotor
betweenthenormal operation and the fault
in other words,
the output
power ofspeed
the dual
drive
is constant.
tolerant operation; in other words, the output power of the dual inverter motor drive is constant.

World Electric Vehicle Journal 2019, 10, 65
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11 of 15
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Figure 12. Experimental setup.
Table 2. Experimental conditions.
Table 2. Experimental conditions.
Items
Items

ValuesValuesSwitching
Switchingfrequency
frequency
DC-bus battery voltages in normal situation
DC-bus battery voltages in normal situation
Capacitor voltage command in fault situation
Capacitor
voltagecommandin fault
situation
Capacitanceof capacitor
acrossDC-busCapacitanceofcapacitor
acrossDC-busMotor rotating speed
Deadtime speedMotorrotating
d-axis current commandin normal situation
Dead time
q-axis current command in normal situation
d-axis current command in normal situation
d-axis current command in fault situation
q-axiscurrent
infault
normalsituation
q-axiscurrentcommand
command insituation

10
10kHz
kHz
100 V
100 V
50 ± 5 V50
5V1330± µF1330
µF1180 r/min
4 µs
1180
r/min
−0.14
4 µsA
0.99 A−0.14 A
−6.33 A
0.99AA
0.99

d-axis current command in fault situation−6.33 A
Number of poles8
q-axis current command in
fault
situation
0.99WA
Rated
power
1000
Numberof poles8
Rated speed
2000 r/min
Rated
torque
4.78
Nm
Rated power
1000 W
Motor parameters
Rated
3.7 r/minA
Ratedcurrent
speed
2000
Number of flux linkage
0.174 Wb
Rated torque4.78 Nm
Armature resistance
1.1 Ω
Motor parameters
Rated
current
3.7mH
Ad-axisinductance
11.0
Numberflux linkage
0.174mHWb
q-axis of
inductance
25.0
Armature resistance
1.1 Ωd-axis inductance
11.0 mH
Figure 14 shows a configuration of the controller. The controller has a digital signal processor
q-axis inductance
25.0 mH(DSP: TMS320C6657) and a field-programmable gate array (FPGA: XS6SLX45-2FGG676C). The SVM
algorithm is implemented in the DSP, where the voltage vectors are selected to synthesize the command
Figure 14 shows a configuration of the controller. The controller has a digital signal processor
voltage vector and the time durations of each voltage vectors are calculated. In this SVM algorithm,(DSP: TMS320C6657) and a field-programmable gate array (FPGA: XS6SLX45-2FGG676C). The SVM
the three voltage vectors which are nearest the command voltage vector are selected according toalgorithm is implemented in the DSP, where the voltage vectors are selected to synthesize thea map created beforehand. Then, the appropriate switching states generating each voltage vector
command voltage vector and the time durations of each voltage vectors are calculated. In this SVM
are selected among the redundant states to reduce the number of the switching transitions and toalgorithm, the three voltage vectors which are nearest the command voltage vector are selectedavoid the unexpected error voltage. In particular, the calculation of the time durations is conductedaccording to a map created beforehand. Then, the appropriate switching states generating eachdepending on the capacitor voltage in the fault situation. However, the SVM is required to switch overvoltage vector are selected among the redundant states to reduce the number of the switching
the switching devices of the inverters with a high-time-resolution. Therefore, the FPGA, which cantransitions and to avoid the unexpected error voltage. In particular, the calculation of the time
generate the gate signals to the gate drivers of both inverters with the time-resolution of 100 MHz
durations is conducted depending on the capacitor voltage in the fault situation. However, the SVM
according to the calculation results of the DSP, is employed. In addition, the compensation technique
is required to switch over the switching devices of the inverters with a high-time-resolution.
to reduce the error voltage vectors during the dead time is also implemented in the FPGA.
Therefore, the FPGA, which can generate the gate signals to the gate drivers of both inverters withthe time-resolution of 100 MHz according to the calculation results of the DSP, is employed. In
addition, the compensation technique to reduce the error voltage vectors during the dead time is also
implemented in the FPGA.

World ElectricVehicle
Vehicle Journal2019,2019, 10,x65
WorldWorldElectricElectric VehicleJournal
Journal 2019,10,
10, xFOR
FORPEERPEERREVIEWREVIEW

ωω

**
mm
＋＋
－－

**

iqiq
T*
PIPI T* 1/PΨ
1/PΨ

Field
Field
Weakening
WeakeningCont
Controlrol

**
dd

ii

＋＋－
－
＋＋ －
－

12 of 1512
12ofof15
15

PIPI

sw
swu1u1sw
swv1v1vαv*α*
dqdq *
*
↓↓ vv
ββ

**
d
PIPI d
**
qq

vv
vv

αβαβ
−1
tan
tan−1
−1
tan
tan−1

θθ
θθi*i*
**
vv

sw
sw
w1
w1
SS
VV
MM

VVcap
cap

Fault
Fault
SignalSignal

ωωmm

idid
iqiq

iαiα

αβαβ
↓↓
dqdq

iβiβ

iuiu

INV1
INV1

iviv

iwiw

PM
PM

Motor
sw
Motor
swu2u2sw
swv2v2INV2
INV2sw
sww2w2

11
ss

uvw
uvw
↓↓
αβαβ

FigureFigure13.
Control
block
diagram.
Figure13.
13.Control
Controlblock
blockdiagram.
diagram.
Switching
SwitchingSignals
Signals
OutputOutputVoltage
VoltageVector
VectorTime
TimeDuration
Duration
66bitbit
DSP
DSP

Gate
Gate
Driver1
Driver1

INV1
INV1
66bitbit

FPGA
FPGA

3232bitbit
TITI
XilinxXilinxTMS320C6657
XC6SLX45TMS320C6657
XC6SLX45(1.25
2FGG676C(1.25GHz)
GHz)
2FGG676C(100(100MHz)MHz)

66bitbit

Gate
Gate
Driver2
Driver2

INV2
INV2
66bitbit

Figure 14.Configuration
Configuration of controller.
FigureFigure14.
14. Configurationofofcontroller.
controller.

3.2. Experimental Results and Discussions
3.2.
3.2.Experimental
ExperimentalResults
Resultsand
andDiscussions
Discussions
The experimental results are shown in Figure 15 and Table 3. In Figure 15, the fault signal of theThe
resultsareshown
FigureTable
Figurefault
ofofthe
Theexperimental
experimental
resultsthe
arecapacitor
shownininvoltage
Figure15
15and
andINV2,
Table3.
3.InIn
Figure15,
15,thethefaultsignal
signaltheDC-busbatteryof the INV2,
of
the
the
three-phasecurrentsof the motor,
DC-busbattery
of
the
INV2,
the
capacitor
voltage
of
the
INV2,
the
three-phasecurrents
ofthemotor,
DC-busbatteryof thethe
INV2,
the capacitor
voltagethe INV2,
the INV2
three-phasecurrentsIn
ofthe
the normal
motor,
the voltage
betweenU-phaseterminalsof theofINV1
and theare depicted.
thevoltage
betweentheU-phaseterminals
ofofthe
INV1
and
the
INV2
are
depicted.
Inthenormalthevoltage
betweentheU-phaseterminals
the
INV1
and
the
INV2
are
depicted.
Inthenormalsituation, the fault signal is 5 V, the capacitor voltage of the INV2 keeps at 100 V, the three-phasesituation,
thesignalcapacitor
voltageof the INV2
keeps atat100
V,
situation,
thefault
fault
signalisis5with
5V,
V,the
the
capacitorvalue
voltage
100voltage
V,thethethree-phase
three-phasemotor currents
are balanced
the effective
irmsof= the0.59INV2
A andkeeps
the 9-level
waveformismotorcurrentsarebalancedwiththeeffective
value
i
rms
=
0.59
A
and
the
9-levelvoltage
waveformisis
motor
currents
the effective
value
irmsthe= 0.59A and the9-levelwaveform
generated
acrossarethebalanced
U-phasewith
windingof the motorwithmeasured
THD
13.7%.voltage
Then, after
the fault
generated
acrossU-phase winding
ofofthewith
THD
13.7%.
Then, afterthegenerated
acrossthethethemotor
motor
withthethemeasured
measured
THDwith
13.7%.
afterSVM
thesignal is detected,
theU-phasesystem iswinding
switched
overto the fault
situationsmoothly
the Then,proposedfault
signalisdetected,thesystemisswitched
over
to
the
fault
situationsmoothly
withtheproposedfault
signal is
the system is switchedto thefault
situationsmoothlywiththe proposed
techniques
in detected,
the high-modulation-index
case.overOn theother
hand,
the fault
tolerant
operationof theSVM
techniques
ininthehigh-modulation-index
case.
On
the
other
hand,
the
fault
tolerant
operation
SVM
techniquesthehigh-modulation-index
case.
On
the
other
hand,
the
fault
tolerant
operation
DC-bus battery in the case of the low-modulation-index was also verified by the authors withseveralofoftheinintheofofthelow-modulation-index was
also
verifiedwith
theDC-bus
DC-busbattery
battery
thecase
case
the
also
verifiedby
bythe
theauthors
authorswith
experimental
test
conditions,which
waslow-modulation-index
published in Referencewas[20].
However,thecapacitor
voltageseveralexperimental
test
conditions,
which
was
publishedinReference[20].
However,thecapacitor
severaltesttheconditions,which waspublished
in Reference
the capacitor
starts toexperimental
decrease before
SVM is switchedoverto the fault
situation. [20].
In theHowever,experimental
setup, involtagestarts
totodecrease
beforethe
SVM
isisswitchedovertotothefault
situation.
Intheexperimental
voltagestartsdecrease
beforetheSVM
switched
over
the
fault
situation.
Intheexperimental
order to detect the fault signal of the DC-bus battery in the INV2, an analog circuit is connected acrosssetup,
ininorder
totodetect
the
fault
ofofthebattery
inintheINV2,
circuitsetup,
order
detecttheDC-bus
faultsignal
signaltheDC-bus
DC-busbatterywith
theINV2,anananalog
analogcircuitisis
the relaytoisolatethefailedbattery,which
is configured
Schmitt-triggers
and RC-filters.
connected
acrosstherelaytoisolatethefailedDC-busbattery,which
isconfiguredwithSchmittconnected
relay
to isolate
failedDC-busbattery, whichis configured
with SchmittTherefore, acrossit takesthetime
to output
the thefault
signalto the controller.
The dual
inverter motor
drive istriggers
andRC-filters.
Therefore,
itittakes
timetotooutput
the
fault
signaltotothecontroller.
The
triggers
andRC-filters.
Therefore,
takes
time
outputthefaultsignalthecontroller.
Thedualdual
operated with the SVM for the normal operation, until the fault signal is given to controller.
As ainverter
motor
drive
is
operated
with
the
SVM
for
the
normaloperation,
until
the
fault
signalis
given
inverter
motor
drive
is
operated
with
the
SVM
for
the
normaloperation,
until
the
fault
signalis
given
result, the capacitor voltage cannot be controlled and is reduced before the operation is switched over
toto controller.
As
the capacitor
voltagecannotbeandisis reduced
before thecontroller.
As aa result,result,voltagecannotbe controlledandreducedthea
to thefault situation.
In fact,thethe capacitor
time to detect
the fault
signaliscontrolled
reduced byusing
a voltage before
sensor inoperation
isisswitchedovertotothefault
situation.
In
fact,
the
time
totodetect
the
fault
signalisisreduced
operation
switched
over
the
fault
situation.
In
fact,
the
time
detectthefaultsignalreducedbattery management system of the Li-ion battery across the inverter DC-bus.
byaavoltagebyusingusing
voltagesensor
sensorininaabattery
batterymanagement
managementsystemsystemofofthe
theLi-ion
Li-ionbattery
batteryacrossacrossthetheinverter
inverterIn the fault situation of the DC-bus battery in the INV2—as shown in Figure 15—the capacitor
DC-bus.
DC-bus.
voltage of the INV2 is regulated at 50 ± 5 V by charging and discharging the capacitor with theIn
Inthethefault
faultsituation
situationofofthe
theDC-bus
DC-busbattery
batteryininthe
theINV2—as
INV2—asshown
shownininFigure
Figure15—the
15—thecapacitor
capacitor
SVM, the three-phase motor currents are balanced with the effective value irms = 3.74 A and thevoltage
of
the
INV2
is
regulated
at
50
±
5
V
by
charging
anddischarging
thecapacitor
withthevoltage of the INV2 is regulated at 50 ± 5 V by charging and discharging the capacitor with theSVM,
SVM,
thethethree-phase
three-phasemotor
motorcurrents
currentsare
arebalanced
balancedwith
withthetheeffective
effectivevalue
valueirms
irms==3.74
3.74AAandandthethe9-level
9-levelWorld Electric Vehicle Journal 2019, 10, 65

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World Electric Vehicle Journal 2019, 10, x FOR PEER REVIEW

13 of 15

9-level voltage
waveformis generated
acrossthe U-phasewindingof the motorwiththe measured
voltage
waveformis generated
across the
U-phasewindingof the motorwith themeasured
THD
THD
13.0%.
The
outputvoltage
waveform
in
the
fault
situation
still
has
error
voltagepulsesbut
13.0%. The output voltage waveform in the fault situation still has error voltage pulses but achieves
achieves
the approximately
THD
as thenormal waveform
operation by
waveformby employing
the SVM
theapproximately
same THDsameas thenormaloperation
employing
the SVM techniques
techniquestoreducetheerrorvoltages
during
the
dead
time.
The
error
voltagepulsescausedby
to reduce the error voltages during the dead time. The error voltage pulses caused by thethesynchronous
switchingtransition
in
the
same
phasesofbothinverters
canbeimproved,ifthesynchronous switching transition in the same phases of both inverters can be improved, if thecorresponding semiconductor
turningonon
or or
off.off.
However,thecorresponding
semiconductordevices
devicescarry
carryout
outperfectly
perfectlysimultaneous
simultaneous
turning
However,
perfect
simultaneous
switchingisactually
difficultbecausethephasecurrent
flows
throughthediode
the perfect simultaneous switching is actually difficult because the phase current flows through thein oneinside
deviceand theandinsulatedgate bipolar(IGBT) in(IGBT)
the othersideotherdevice.
Therefore,
diode
one
side device
the insulated
gate transistor
bipolar transistor
in theside
device.
the switchingis different
the twoinverters.
Besides,
the error
voltage
Therefore,
the transition
switchingtime
transition
time between
is different
betweenthe twoinverters.
Besides,
thepulses
error
can
be
generated
at
the
point
of
the
transitions
betweenthecapacitor
charging
andthedischarging
voltage pulses can be generated at the point of the transitions between the capacitor charging and themodes and betweenof the SVM,
for example.
Therefore,
it is difficult
to eliminate
discharging
modes theandoperating
between regions
the operating
regionsof the SVM,
for example.
Therefore,
it is
the
voltageripplecompletely.
difficult to eliminate the voltage ripple completely.
The efficiency
efficiency measured
measured results
results ofof thethe INV1
INV1 andand thethe motor
motor areare deteriorated
deterioratedby
by7.9%
7.9%andand90.2%,
90.2%,
The
respectively. The
The reason
reason why
why thethe measured
measured efficiency
efficiency of thethe INV1
INV1 isis deteriorated
deteriorated isis thatthat thetheswitchingswitchingrespectively.
loss
and
the
conduction
loss
areincreasedue
tothed-axiscurrent
inthefield-weakening
control.
loss and the conduction loss are increase due to the d-axis current in the field-weakening control.
Moreover, themotorefficiency
is deteriorated
is thatthe d-axis
current
does
Moreover,the reason
reasonwhy
whythethemeasured
measuredmotor
efficiency
is deteriorated
is thatthe d-axis
current
not contributeto thetomotor
torqueand themotor
rotating
speed,speed,that is,that
theis,
outputpowerpowerof the ofmotor.
does
not contributethe motor
torqueandthe motor
rotating
the output
theHowever,itisdifficulttomeasuretheefficiency
of
the
INV2
in
the
fault
situation,
becausetheINV2
motor. However, it is difficult to measure the efficiency of the INV2 in the fault situation, because theutilizes
only aonly
reactive
power.power.
INV2
utilizesa reactive

U-Phase Voltage
Vu (V)

Motor Line
Current (A)Capacitor Voltage
Vcap (V)

Fault Signal

10

5

0
120
100
80
60
40
20
0
6
4
2

iu
iv
iw

0
-2
-4
-6
200
100
0
-100
-200

0

50

100

150

Time (ms)Figure15.
15.Experimental
Experimentalresult
resultof
offault
faulttolerant
tolerantoperation
operationof
ofDC-busDC-busbattery.
battery.
FigureTable 3. Measurement results.

Normal situation
Fault situation
1

THD of Vu [%]irms [A]

13.7
13.0

0.59
3.74

INV1
96.0
88.4

Efficiencies [%]
INV2
Motor
96.4
42.0
No data 1
4.1

INV2 utilizes only reactive power in fault situation.

200

World Electric Vehicle Journal 2019, 10, 65

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Table 3. Measurement results.
THD of Vu [%]Normalsituation
Fault situation

Efficiencies [%]irms [A]
INV1

INV2

Motor

13.7

0.59

96.0

96.4

42.0

13.0

3.74

88.4

No data 1

4.1

1 INV2 utilizes only reactive power in fault situation.

4. Conclusions
This paper describes the fault tolerant operation of the dual inverter motor drive focusing on
the DC-bus battery failure with the SVM. The SVM technique for the fault tolerant operation in thehigh-modulation-index is proposed for the first time in this paper. The proposed technique was verified
through experimental tests and the operation characteristics of the fault situation were assessed andcompared with the normal operation from the viewpoints of the measured THD and the efficiencies of
the inverter and the motor.
Author Contributions: Conceptualization, Y.O. and T.N.; methodology, Y.O., T.N. and M.B.F.; software, Y.O.;
validation, Y.O., T.N. and M.B.F.; formal analysis, Y.O.; investigation, Y.O. and M.B.F.; data curation, Y.O.;
writing—original draft preparation, Y.O.; writing—review and editing, Y.O. and T.N.; visualization, Y.O.;
supervision, T.N.; project administration, T.N.; funding acquisition, T.N.
Funding: This work was supported by the New Energy and Industrial Technology Development Organization(NEDO), Grant-in-Aid for Scientific Research from the National Government and Ministry of Economy, Trade andIndustry, Japan.
Conflicts of Interest: The authors declare no conflict of interest.

References
1.
2.

3.

4.
5.
6.

7.

8.
9.
10.

Kiadehi, A.D.; Drissi, K.E.K.; Pasquier, C. Voltage THD Reduction for Dual-Inverter Fed Open-End Loadwith Isolated DC Sources. IEEE Trans. Ind. Electron. 2017, 64, 2102–2111. [CrossRef]
Wu, D.; Wu, X.; Su, L.; Yuan, X.; Xu, J. A Dual Three-Level inverter -Based Open-End Winding Induction
Motor Drive with Averaged Zero-Sequence Voltage Elimination and Neutral-Point Voltage Balance.
IEEE Trans. Ind. Electron. 2016, 63, 4783–4795. [CrossRef]
Somasekhar, V.T.; Srinivas, S.; Kumar, K.K. Effect of Zero-Vector Placement in a Dual -Inverter Fed Open-End
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