CONFIDENTIALDATA BRICK DS-VU3P-PCIE
user's manual
02/09/2017

Design Service Division

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Revision History
The following table shows the revision history for this document.
version

Revision

Date

Updater

Remarks

0.0

New

01/23/2017

Inohara―1.0

Initial release

02/09/2017

Yanase―2 / 17PALTEK CORPORATION
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Table of Contents
1.

Introduction ...............................................................................................................................4

1.1.

Board features .................................................................................................................................. 4

2.

Feature desqription....................................................................................................................42.1.

PCB information .............................................................................................................................. 4

2.2.

Physical Specifications .................................................................................................................... 5

3.

Functional Description ..............................................................................................................6

3.1.

FMC connector ................................................................................................................................ 6

3.2.

Power input ...................................................................................................................................... 7

3.3.

SW/LED/test terminal ...................................................................................................................... 8

3.4.

DDR4-SODIMM ............................................................................................................................. 9

3.5.

BPI Flash Memory ........................................................................................................................... 9

3.6.

FPGA XCVU3P-2FFVC1517 ........................................................................................................ 10

3.7.

PCIexpress

3.8.

FireFly connector ........................................................................................................................... 11

3.9.

Oscillator........................................................................................................................................ 123.10.

Clock system diagram .................................................................................................................... 13

3.11.

Power supply.................................................................................................................................. 14

3.12.

Power system diagram ................................................................................................................... 16

3.13.

Miscellaneous ................................................................................................................................ 17×16 ........................................................................................................................... 113 / 17
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1.

Introduction
TM
R UltraScale+
The DS-VU3P-PCIE is featuring a Xilinx VIRTEX○
FPGA.

1.1.

Board features
TM
R UltraScale+・VIRTEX○(XCVU3P-2FFVC1517) is mounted on the PCIe Mother Board v0.7.

・Input Voltage : 12V
・Power : 0.85V, 0.9V, 1.2V, 1.5V, 1.8V, 3.3V(Linear Technology)
・Board size conforms to PCI-Express.

・SAMTEC FireFly ×4
・16 lanes with PCI - Express 3.0.
・DDR4 Memory MT2400 8GB(with ECC)up to 16GB (without ECC,option)

2.

Feature desqription

2.1.

PCB information
Figure 1 shows the DS-VU3P-PCIE. Each numbered feature that is referenced in Figure 1 is described inTable 1.

2354716138141210915716 1711Figure 1 Product Photo

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Table 1 Board Component Descriptions

2.2.

Callout

Component Description

Page Number

1BPI Memory for Configuration and JTAG

9 (Only BPI)

2FMC-1 HPC Connector

63for FMC-1 JTAG connection

64FMC-2 HPC Connector

65for FMC-2 JTAG connection

666pinATX-PCIe12V IN

77

SW/LED/test terminal

88DCDC, LT PowerPlay connector

149DDR4-SODIMM

910XCVU3P-2FFVC1517

1011PCIexpress ×161112

FireFly connector

1113

OSC1 100MHz oscillator for Configuration

1214

OSC2 Si570 GTY Reference Clock

1215

OSC3 200MHz Reference Clock for MIG

1216

OSC4 100MHz oscillator for user logic

1217

OSC5 Si570 oscillator for user logic

12

Physical Specifications
DS-VU3P-PCIE complies with PCI - Express 3.0.

Figure 2 Mechanical Dimensions (mm)5 / 17PALTEK CORPORATION
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Functional Description

3.1.

FMC connector
・When FMC card is implemented and PRSNT_M2C_L terminal is not connected to GND on a board, theuser cannot use the TDO-TDI chain of the JTAG signal.
・JTAG of the Mezzanine side and JTAG chain of the Mother board side are constructed byshort-circuiting with a jumper terminal implemented beside a connector in the case of the above.
・If the user is connecting the PRSNT_M2C_L to the GND on the mezzanine card side and the mezzaninecard side where the JTAG is not used, make the TDO-TDI short on the mezzanine card side.( *Overall
JTAG chain cuts.)
・FMC transceiver (GTY)ch(dp0) attaches the iBERT sample design using the loopback card (cyberTateno).
→The above statement confirmed movement to 16Gbps.

Figure 3 FMC-1 connector (CN13) and JTAG connection jumper (J2)

Figure 4 FMC-2 connector (CN14) and JTAG connection jumper (J3)

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3.2.

Power input
The user connects 6pin connector for PCI-Express cards by ATX power supply.

Figure 5 About ATX PCIe 6pin power supply connection connectors(CN1).

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3.3.

SW/LED/test terminal
・The left switch is Re- CONFIG.
・As for the switch for user logics, it is not done PULLUP on a board. Therefore, please do PULLUP in
the FPGA inside.
・It is assigned BANK47/VCCO=1.8V.
SW1

Switch for user logic

CONFIG switch

SW2～SW5

Table 2 Pin assignment

Figure 6 Switches
・The left LED is CONFIG_DONE. When configuration of FPGA is completed, LED turn on.
・The user LED turns on with "1". (ActiveHI)
CONFIG_DONE

LED for user logic

LED1

SW2～SW5

Table 3 Pin assignment

Figure 7 LEDs
・The test terminal is connected to VCCO(Bank47) of 1.8V. It is not 3.3V interface.
Table 4 Pin assignment

test terminal pin1,3,5,7,9

GND pin2,4,6,8,10

Figure 8 Test terminal8 / 17
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3.4.

DDR4-SODIMM
・Part number : MTA18ASF2G72HZ-2GB3 (Micron)・MT-2400・Supports 8GB(with ECC) and 16GB(w/o ECC) modules.
・Sample design (MIG-example Design) attachment using the 16G module.
→The design which uses 16G/72bit module (MTA18ASF2G72HZ-2GB3)

3.5.

BPI Flash Memory
・Part number : MT28GU01GAAA1EGC-0SIT (Micron)・Supply voltage : 1.8V
・Data Path width : 16bit
・Device Density : 1Gb

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3.6.

FPGA XCVU3P-2FFVC1517
・The device name on VIVAD is XCVU3P-FFVC1517.
・The BANK layout diagram of the FPGA used for this board and its application are shown below.

Figure 9 BANK layout diagram

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3.7.

PCIexpress ×16
・Supports Gen3.
・PCIe endpoint Example-Design generated in IP catalog.
→Device drivers are not attached to the above design.
→Property check is possible on the device manager of WIN 10.
→Internal status signal can be checked on VIVADO's Hardware-Manager.

3.8.

FireFly connector
・Supports ECUE (28 Gbps 300 mm) and ECUO(optical module 14 Gbps) of SAMTEC Fire-Flyconnector.
・iBERT sample design combined with transceiver ch on FMC.
・The reference clock is connected to REFCLK 0 of each QUAD.

TX-1
Transmitter 8lane
QUAD125,126

RX-1
Receiver 8lane

OSC2

QUAD125,126

GTY Reference Clock Si570
10-810MHz
Startupfrequency=200MHz
I2C-Address=60H

TX-2
Transmitter 8lane
QUAD127,128

RX-2
Receiver 8lane
QUAD127,128

Figure 10 FireFly connector

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3.9.

Oscillator
・Five oscillators are mounted on the board, and OSC 4 (fixed 100 MHz) and OSC 5 (variable Si 570) arefor user logic.

Table 5 Oscillator description table

OSC1100MHz EMC Clock forconfiguration

OSC2Si570 reference Clockfor GTY-QUAD125-128

OSC3OSC4

OSC5200MHz fixation reference Clock

100MHz fixation Clock

Si570 Variable Clockfor MIG(DDR4)

for user logic

for user logic

Figure 11 Oscillators

10-810MHz
Startupfrequency=200MHz

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I2C-Address=60H

CONFIDENTIAL
3.10. Clock system diagram
The clock system diagram of this board is shown below.

Figure 12 clock system diagram

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3.11. Power supply・DCDC modules (Linear Technology).
And it can set output voltage and current limit etc from PC software.
・"Address" in the figure is the I2C address of DCDC that can be checked from the LTPowerPlay software.
I2C cannot connect from the FPGA.
・At the time of shipment, appropriate and minimum setting (output voltage, startup time, etc.) on thisboard is applied to each DCDC.
・DCDC setting project file for LTPowerPlay software is attached.
・When changing the setting of DCDC, short program J1 (for safety) and do the program.
・Also, during normal operation user can check the output state and temperature of the chip on the PC.
Jumper for stopping DCDC output (J1)FMC2*Short during DCDC program.

Jumper for Power supply setting (JP3/JP4)

Programming Adaptor
LTC DC2086

FMC14pin connector

Jumper for Powersupply setting(JP1/JP2)

FMC1/2
Output: General-purpose3.3V
Output: 1.2/1.5/1.8V
Address=4Eh
Address=45h

Output: 1.2V/1.8V
Output: MGT-AVCC0.9V

Address=47h

Address=42h

Output: VCCINT0.85V

Output: MGT-AVTT1.2V

Address=40h

Address=44h

Figure 13 Power supply

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・The VADJ voltage setting of FMC1/2 becomes able to set it from an outside jumper not ROM data in
DCDC.
・The output voltage is decided by the pair of the short position of JP1 and JP2, JP3 and JP4.

Table 6 FMC1 setting * The output is determined by combination (mV).

Figure 14 JP1 and JP2Table 7 FMC2 setting * The output is determined by combination (mV).

Figure 15 JP3 and JP415 / 17
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3.12. Power system diagram
The power supply system diagram of this board is shown below.

Figure 16 Power system diagram
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3.13. Miscellaneous
・An XDC file for pin location for VIVADO is attached.
・A sample design generated from IP catalog is attached.
→DDR4-2133 MIG Example Design→PCIe x16 endpoint Example Design→FireFly , GTY-iBERT Example Design for FMC1/2

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