EMAX2SPC-0001
Ver.1.0: Oct. 20 2012
Ver.1.1: Mar. 10 2013

EMAX2/intel ARCHITECTURE HANDBOOK(Energy-aware Multimode Accelerator eXtension)

Nara Institute of Science and Technology
Computing Architecture Laboratory
Accelerator Group

Copyright Yasuhiko NAKASHIMA. All Rights Reserved.

1

Table of contents

Table of contents
1 Hardware structure

7

1.1

Basic function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7

1.2

Basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7

2 Software specification

11

2.1

Instruction format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11

2.2

ALU OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13

2.3

MEM OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16

2.4

RGI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16

2.5

LMM CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16

2.6

Hints for sophisticated use of hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17

2.7

Application Binary Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18

2.8

Configuration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19

2.9

Initial Values of Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21

2.10 LMM Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21

3 Examples

23

3.1

tone curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23

3.2

hokan1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24

3.3

hokan2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25

3.4

hokan3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

26

4 Control

27

4.1

LMM の仕様 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27

4.2

使用するメモリ空間. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28

4.3

各 UNIT に対する制御情報の伝達 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29

4.3.1

Idle (pe0 status=STATUS IDLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29

4.3.2

Unit configuration in progress (pe0 status=STATUS CONF) . . . . . . . . . . . .

30

4.3.3

Register initialization in progress (pe0 status=STATUS REGV) . . . . . . . . . .

31

4.3.4

LMM tag initialization in progress (pe0 status=STATUS LMMI) . . . . . . . . . .

32

4.3.5

LMM loading in progress (pe0 status=STATUS LMM LOAD) . . . . . . . . . . .

33

4.3.6

Start execution (pe0 status=STATUS START) . . . . . . . . . . . . . . . . . . . .

33

4.3.7

Execution in progress (pe0 status=STATUS EXEC) . . . . . . . . . . . . . . . . .

33

4.3.8

LMM drainage in progress (pe0 status=STATUS LMM DRAIN) . . . . . . . . . .

34

4.3.9

Terminate execution (pe0 status=STATUS TERM) . . . . . . . . . . . . . . . . .

34

5 How to use EMAX2 simulator

35

5.1

Compiling application programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35

5.2

Executing application programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential

Table of contents

2

A 評価システム
A.1 GP6X760MP システムの構成 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

37
37

A.2 プロセッサ機能と HOST 機能のインタフェース . . . . . . . . . . . . . . . . . . . . . . . .
A.3 プロセッサ機能と DDR3 のインタフェース . . . . . . . . . . . . . . . . . . . . . . . . . . .

40
41

B ASIC 拡張機能
B.1 QFP208 パッケージ用インタフェース . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

45
45

C References
C.1 GP6X760 documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

49
49

C.2 EMAX2 documents/sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.3 EMAX2 toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

49
50

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EMAX2 ARCHITECTURE HANDBOOK

3

List of Figures

List of Figures
1.1

EMAX2 basic function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9

1.2
1.3

Interconnection of functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMAX2 basic unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9
10

1.4

Interconnection of units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10

2.1

Instruction format for each unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12

2.2
2.3

Format of ALU operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lower level configuration data (1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13
19

2.4

Lower level configuration data (2/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20

2.5
2.6

Initial Values of Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LMM Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21
21

4.1
4.2

Structure of LMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing chart of LMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27
27

4.3
4.4

General control information of EMAX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
conf[][] → unit[][] のタイミングチャート . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29
30

4.5
4.6

regv[][] → unit[][] のタイミングチャート . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
lmmi[][] → ctl new[][]/ddr3 tlb[][] のタイミングチャート . . . . . . . . . . . . . . . . . . . .

31
32

4.7
4.8

source DDR3 → lmm[][] のタイミングチャート . . . . . . . . . . . . . . . . . . . . . . . . .
lmm[][] → result DDR3 のタイミングチャート . . . . . . . . . . . . . . . . . . . . . . . . .

33
34

A.1 全体構成 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2 プロセッサ制御インタフェースのタイミングチャート (WRITE/READ) . . . . . . . . . . .

3840

A.3 DDR3 インタフェースのタイミングチャート (WRITE) . . . . . . . . . . . . . . . . . . . .

41

A.4 DDR3 インタフェースのタイミングチャート (WRITE バーストモード) . . . . . . . . . . .
A.5 DDR3 インタフェースのタイミングチャート (READ) . . . . . . . . . . . . . . . . . . . . .

4243

A.6 DDR3 インタフェースのタイミングチャート (READ バーストモード) . . . . . . . . . . . .

44

B.1 GP6X760 ボードの構成. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

46

B.2 QFP208 のピン配置（周辺の記号は XILINX の対応ピン番号（現状は仮）） . . . . . . . . .

47

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential

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List of Tables

List of Tables
2.1

EX1 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14

2.2
2.3

EX2 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFT operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15
15

2.4

Memory operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16

4.1

初期モデルにおけるメモリ空間の運用 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28

A.1 制御レジスタ空間と DDR3 空間 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

39

A.2 プロセッサ-HOST 機能のインタフェース信号（ASIC インタフェースとしては 40 本） . . .
A.3 プロセッサ-DDR3 のインタフェース信号（ASIC インタフェースとしては 82 本） . . . . .

40
41

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential

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CHAPTER 1. HARDWARE STRUCTURE

Chapter 1

Hardware structure
1.1

Basic function

The basic function of a minimal component of EMAX2 is shown in Figure 1.1. At the first stage, thevalues stored in six input registers are read and transferred to second level intermediate registers dedicatedto each fixed portion of EX1 (ALU) or EAG (Effective Address Generator) through four internal databus (IXB). At the second stage, one of the registers at the same portion group is selected among neighborcomponents and transferred to third level intermediate registers through 6 external data bus (ETB). The
main role of second and third level registers is to transfer any input registers in neighbor components toany portion of EX1 or EAG across different components. Two stage pipelining is employed to reduce theimpact on frequency caused by the delay of long wires and many selectors connecting the components.
At the third stage, EX1 (3-in ALU) and EAG (2-in adder) produce the results and write into fourthlevel intermediate registers dedicated to each of EX1 and EAG. At the fourth stage, EX2 (2-in ALU) getsthe result of EX1, produces final result and writes into final (fifth) level dedicated register. In the sameway, when a load instruction is allocated to the component, LMM (Local Memory Module) produces theload data and writes into final level dedicated register.
Each of final level registers can select the input from dedicated EX2/LMM or dedicated FIFO. EachFIFO is filled with the data supplied from some neighbor LMM through an external data bus (EMB).
When tri-state buffer between EMB is cut off, each component can use EMB independently, so that each
LMM can supply the data to EX2 FIFO in the same component. When tri-state buffer between EMB
is opened, neighbor FIFOs can share the output of some neighbor LMM connected to the EMB. The
main usage of FIFOs is executing some kind of "load (I-12); load (I-8); load (I-4); load (I)"
instructions in the same row.
The combination of EX1 and EX2 is suitable for multimedia or floating-point add/multiply operations.
Moreover, the combination of EX1, EAG and local memory module can directly execute some kind of"store (A+B+C)->(base+offset)" instructions.

1.2

Basic structure

Many minimal components are connected to form EMAX2 as shown in Figure 1.2. For the pipelined
execution, the third level registers in the first components (colored with black) are merged into the firstlevel registers in the second components (colored with red). Also the outputs of final level registers
in the first components are connected to IDB and EDB in the second components and to IXB in thethird components (colored with green). In the same way, the outputs of final level registers in the final
components (colored with purple) are connected to IDB and EDB in the first components and to IXB in
the second components. Consequently, EMAX2 has a vertical ring network of ALUs and local memory

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential1.2. BASIC STRUCTURE

8modules.
However, it is difficult to design the hardware of EMAX2 from the view of the function, because
several components in different levels are mixed in the same physical area as shown in Figure 1.2. For
alleviating this complexity, ”unit” which is a folded form of function is introduced as shown in Figure 1.3.
From the view of unit, each unit has single lane of intermediate registers and single lane of final registers.
All data is supplied from the final registers in the previous units and EX1, EX2, EAG and local memory
module finally store the results into the final registers. The whole structure of EMAX2 based on unit isshown in Figure 1.4.
Above array structure is specially designed for executing a loop with no dependency between different
iterations. After each of the registers and the instructions for a loop are mapped on each unit, EMAX2
can execute all instruction in a loop simultaneously and can produce the result of each iteration every
cycle.

Y.Nakashima Proprietary & Confidential

EMAX2 ARCHITECTURE HANDBOOK

9

CHAPTER 1. HARDWARE STRUCTURE

IXB(Internal bus)
1st stage

LAPP:MUX# 13in*15

13-1

13-1

13-1

13-1

EMAX:MUX# 5in*24 5-1

5-1

5-1

5-1

5-1

2nd stage

1st stage

ETB(External bus)

2nd stage

EDB(External bus)

13-1

5-1

IDB(Internal bus)

AL1-3

MEDIA1-4

3rd stage

EAG

EX1

Local-MEM

EAG

Local-MEM

EX2+SFT

3rd stage

EMB(External bus)

4th stage
EX2_FIFO

LMM_FIFO

oop0

Figure.1.1: EMAX2 basic function.

EX1

EAG

EX1

EAG

EX1

EAG

EX1

EAG

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

EX1

EAG

EX1

EAG

EX1

EAG

EX1

EAG

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

EX1

EAG

EX1

EAG

EX1

EAG

EX1

EAG

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

EX1

EAG

EX1

EAG

EX1

EAG

EX1

EAG

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

EX1

EAG

EX1

EAG

EX1

EAG

EX1

EAG

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

Figure.1.2: Interconnection of functions.

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential

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1.2. BASIC STRUCTURE

oop0

1st stage
2nd stage
3rd stage
13-1

13-1

MEDIA1-4

13-1

13-1

AL1-3

13-1

13-1

EAG

13-1

Local-MEM
oop0

LAPP:MUX# 13in*15
IXB
IDB
EDB

1st stage
5-1

EMAX:MUX# 5in*24

5-1

5-1

EX1

5-1

5-1

3rd stage

5-1

EAG

Intermediate registers

Local-MEM

EX2+SFTEMB
ETB

2nd stage 4th stage

tx1

tx2

oex

tx3

tm1

tm2

EX2_FIFO

olm

tm3

Final registers

LMM_FIFO

Figure.1.3: EMAX2 basic unit.

tx1

tx1

tx1

tx1

tx1

tx2

tx2

tx2

tx2

tx2

EX1

EAG

EX1

EAG

EX1

EAG

EX1

EAG

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

oex

tx3

tm2

olm

tm3

tx1

tx2

oex

tx3

tm1

tm2

olm

tm3

tx1

tx2

oex

tx3

tm1

tm2

olm

tm3

tx1

tx2

oex

tx3

tm1

tm2

olm

tm3

EX1

EAG

EX1

EAG

EX1

EAG

EX1

EAG

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

oex

tx3

tm1

tm2

olm

tm3

EX1

EAG

EX2

Local-MEM

oex

tx3

tm1

tm2

olm

tm3

tx1

tx1

tx2

tx2

oex

tx3

tm1

tm2

olm

tm3

EX1

EAG

EX2

Local-MEM

oex

tx3

tm1

tm2

olm

tm3

tx1

tx1

tx2

tx2

oex

tx3

tm1

tm2

olm

tm3

EX1

EAG

EX2

Local-MEM

oex

tx3

tm1

tm2

olm

tm3

tx1

tx1

tx2

tx2

oex

tx3

tm1

tm2

olm

tm3

EX1

EAG

EX2

Local-MEM

oex

tx3

tm1

tm2

olm

tm3

EX1

EAG

EX1

EAG

EX1

EAG

EX1

EAG

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

EX2

Local-MEM

oex

oex

tm1

tx3

tm1

tm2

olm

tm3

EX1

EAG

EX2

Local-MEM

tx3

tm1

tm2

olm

tm3

tx1

tx1

tx2

tx2

oex

tx3

tm1

tm2

olm

tm3

EX1

EAG

EX2

Local-MEM

oex

tx3

tm1

tm2

olm

tm3

tx1

tx1

tx2

tx2

oex

oex

tx3

tm1

tm2

olm

tm3

EX1

EAG

EX2

Local-MEM

tx3

tm1

tm2

olm

tm3

tx1

tx1

tx2

tx2

oex

oex

tx3

tm1

tm2

olm

tm3

EX1

EAG

EX2

Local-MEM

tx3

tm1

tm2

olm

tm3

Figure.1.4: Interconnection of units.

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EMAX2 ARCHITECTURE HANDBOOK

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CHAPTER 2. SOFTWARE SPECIFICATION

Chapter 2

Software specification
2.1

Instruction format

The instruction format for each unit is shown in Figure 2.1. Case 1 includes both of ALU operationand memory operation. Case 2 includes only ALU operation and case 3 includes only memory operation.
The header specifies the target unit to be initialized, row-distance from previous instruction mapping(should be used to effectively reuse LMMs which are not affected by the row-distance) and execution
count (number of cycles) the unit should work. ALU OP specifies each operation of EX1 (3-in ALU)
and EX2 (2-in ALU and 2-in shifter are cascaded), register numbers and some sort of attributes. Initialvalues of the registers can be specified by RGI. MEM OP also specifies the load/store operation andthe register numbers. In the same way as ALU, initial values of the registers can be specified by RGI.
LMM CONTROL specifies how to transmit data between main memory of host computer and local
memory module including FIFO.

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential12

2.1. INSTRUCTION FORMAT

Case 1: @row#,col#,dist [count] ALU_OP rgi[labelX:,labelY:] & MEM_OP rgi[labelX:,labelY:] LMM_CONTROL
Case 2: @row#,col#,dist [count] ALU_OP rgi[labelX:,labelY:]
Case 3: @row#,col#,dist [count]& MEM_OP rgi[labelX:,labelY:] LMM_CONTROL┌────┐┌─┬─┬─┬──┬─┬─┬─────┬─┬─────┬─────┬┬──┬┬──┬┬───┬┐┌────┐┌────┐│row#col#││ EX1 │EX2 SFT│ U│ I│fhl:2 Xr:5│ I│fhl:2 Yr:5│fhl:2 Zr:5│││││Dw Dw:5 Cw││initX ││initY ││dist││ opcd │opcd│ P│ N│
│ N│
│
│v
│v
│v
v││init-val││init-val││count │││opcd│ D│ I││ I│││simm13│ imm5│││││of Xr││ofYr/imm│└────┘└─┴─┴─┴──┴─┴─┴─────┴─┴─────┴─────┴┴──┴┴──┴┴───┴┘└────┘└────┘
32
1 6 3
3
1 1
7
1
7
7
14
6
7
32
32
----------------------------------------------------------------------------------------------------32bit
64bit
64bit
┌──┬─┬─┬──┬─┬──────┬──────┐┌────┐┌────┐┌─┬───────────┬─────┐┌────┐│MEM │ U│ I│Xr:5│ I│sufix:3 Yr:5│thru:1 Zr:5││initX ││initY ││ v│
len│
dist ││prefetch││opcd│ P│ N││ N││││init-val││init-val││ │││││││ D│ I││ I││││
of Xr││ofYr/imm││ ││││top_addr│└──┴─┴─┴──┴─┴──────┴──────┘└────┘└────┘└─┴───────────┴─────┘└────┘
10
1 1
5
1
8
6
32
32
3
20
9
32
-----------------------------------------------------------------------------------------------32bit
64bit
32bit
32bit









struct insn { /* EMAX2 instruction format */struct header {Uint v: 1; /* insn on */Uint insn_row: 6; /* max 64 */Uint insn_col: 3; /* max 8 */Uint insn_dist: 6; /* max 64 */Uint count: 16; /* max 65536 */} header;struct alu {Uint ex1_use_regZ : 1;
Uint ex1_op : 6; /* 0:ex2_op use regX others:ex2_op use (-) */Uint ex2_op : 3;
Uint sft_op : 3;
Uint upd: 1;
Uint Xini: 1; /* 0:noinit 1:ri*/Uint Xfhl: 2; /*
1:SUFLO 2:SUFHI 3:ri/SUFFL */Uint Xr: 5;
Uint Yini: 1; /* 0:noinit 1:ri/imm */Uint Yfhl: 2; /* 0:imm 1:SUFLO 2:SUFHI 3:ri/SUFFL */Uint Yr: 5;
Uint Zfhl: 2; /*
1:SUFLO 2:SUFHI 3:SUFFL */Uint Zr: 5;
Uint simmS_v: 1; /* 0:simmS is not used */Uint simmS : 13;
Uint immT_v : 1; /* 0:immT is not used */Uint immT: 5;
Uint Dw_v: 1; /* 0:Dr is not used */Uint Dw: 5;
Uint Cw_v: 1; /* 0:CC is not used */Uint initX;
Uint initY;} alu;
struct mem {Uint op: 10;
Uint upd: 1;
Uint Xini: 1; /* 0:noinit 1:ri*/Uint Xr: 5;
Uint Yini: 1; /* 0:noinit 1:ri/imm */Uint Ysuffix: 3; /* 0:imm 1:SUFLO 2:SUFHI 3:SUFFL 4:SUFB0 5:SUFB1 6:SUFB2 7:SUFB3 */Uint Yr: 5;
Uint Zthru : 1; /* for EX1->store 0:none 1:thru */Uint Zr: 5;
Uint initX;
Uint initY;} mem;
struct ctl {Uint v: 3; /* 0:nop, 1:LMR, 2:LMW, 3:LMX, 5:LMF(force read) */Uint len : 20;
Uint dist : 9;
Uint top;} ctl;} insn[INSN_DEPTH][INSN_WIDTH]; /* 10words/unit */Figure.2.1: Instruction format for each unit.

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2.2

ALU OP

The format of ALU operations is shown in Figure 2.2. EX1, EX2 and SFT are mnemonic such as
add/sub/and. Xr, Yr and Zr are register numbers (r0-r31) of source operands. “−” means the output of
EX1 is used as the first operand of EX2. Imm32, simm13 and imm5 are 32bit immediate, 13bit signed
immediate and 5bit unsigned immediate values respectively. The combination of “−expr”, “∼expr”,“(expr<<expr)” and “(expr>>expr)” are also allowed. “|” indicates following mnemonic is assigned toEX2. In the case that only SFT operation is required, use "or (Xr, 0) SFT Zr/imm5" (type-8 and 9).
type-1: EX1 (Xr, Yr/imm32)| EX2 (-,Zr) [SFT imm5], Dw Cw
type-2: EX1 (Xr, Yr/imm32)| EX2 (-,
simm13) [SFT Zr], Dw Cw
type-3: EX1 (Xr, Yr/imm32)| EX2 (-,
simm13) [SFT imm5], Dw Cw
type-4: EX1 (Xr, Yr/imm32)| EX2 (-)[SFT Zr], Dw Cw
type-5: EX1 (Xr, Yr/imm32)| EX2 (-)[SFT imm5], Dw Cw
type-6: EX1 (Xr, Yr/imm32, Zr) | EX2 (-,simm13) [SFT imm5], Dw Cw
type-7: EX1 (Xr, Yr/imm32, Zr) | EX2 (-)[SFT imm5], Dw Cw
type-8:| EX2 (Xr, Yr/imm32) [SFT Zr], Dw Cw
type-9:| EX2 (Xr, Yr/imm32) [SFT imm5], Dw Cw
type-a:| EX2 (Xr)
[SFT Zr], Dw Cw
type-b:| EX2 (Xr)
[SFT imm5], Dw Cw
type-c: EX1 (Xr, Yr/imm32), Dw Cw
type-d: EX1 (Xr, Yr/imm32, Zr), Dw Cw
type-e: EX1 (Xr, Yr/imm32)
type-f: EX1 (Xr, Yr/imm32, Zr)

Figure.2.2: Format of ALU operation.
Dw and Cw are register numbers (r0-15 and c0) of destination registers. If Dw is omitted, no register
is updated (type-e and f). This instruction format is used to pass the result of EX1 to the input of a store
operation (one of memory operations). In the same way, if Cw is omitted, no condition code register is
updated. Condition code register (only c0 is available) has 4bit information (Negative, Zero, oVerflow
and Carry) and is updated only by add or sub instruction.
In the case that a floating-point or load operation is specified in EX1, no EX2/SFT operation can be
specified. EX1, EX2 and SFT operations are listed in Table 2.1, Table 2.2 and Table 2.3 respectively.

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2.2. ALU OP

Table.2.1: EX1 operations
32bit operations
add
add3

(Xr[+=], Yr/imm32)(Xr[+=], Yr/imm32, Zr)

Xr+Yr or Xr+imm32 (∗)
Xr+Yr+Zr or Xr+imm32+Zr (∗)

sub
sub3

(Xr[+=], Yr/imm32)(Xr[+=], Yr/imm32, Zr)

Xr-Yr or Xr-imm32 (∗)
Xr-Yr-Zr or Xr-imm32-Zr (∗)

16bit[2] operations
mauh
mauh3

(Xr.{fhl}, Yr.{fhl})(Xr.{fhl}, Yr.{fhl}, Zr.{fhl})

16bit[2] Xr+Yr (†)
16bit[2] Xr+Yr+Zr (†)

msuh
msuh3

(Xr.{fhl}, Yr.{fhl})(Xr.{fhl}, Yr.{fhl}, Zr.{fhl})

16bit[2] Xr-Yr (†)
16bit[2] Xr-Yr-Zr (†)

misc operations
mluh
mmrg3

(Xr.{fhl}, Yr.{fhl})(Xr, Yr, Zr)

10bit[2]*9bit ⇒ 16bit[2]merge Xr.byte3 | Yr.byte2 | Zr.byte1 | 0

msad
minl

(Xr, Yr)(Xr, Yr)sum-of-absolute-difference 8bit[4] ⇒ 16bit[2]select Xr or Yr based on min(Xr.L16bit,Yr.L16bit)

minl3
mh2bw

(Xr, Yr, Zr)(Xr, Yr)merge min(Zr.H16bit,Zr.L16bit) and Xr.H16bit or Yr.H16bit
merge sat(Xr.H16bit),sat(Xr.L16bit),sat(Yr.H16bit),sat(Yr.L16bit) (‡)

mcas
mmid3

(Xr, Yr)(Xr, Yr, Zr)(Xr<Yr) ? 0 : 0xff
bytewise compare and collect middle value

mmax
mmax3

(Xr, Yr)(Xr, Yr, Zr)

bytewise compare and collect maximum value
bytewise compare and collect maximum value

mmin
mmin3

(Xr, Yr)(Xr, Yr, Zr)

bytewise compare and collect minimum value
bytewise compare and collect minimum value

load from FIFO
ldb
ldub

(Xr[+=], Yr/imm32)(Xr[+=], Yr/imm32)

load signed byte from EX2 FIFO
load unsigned byte from EX2 FIFO

ldh
lduh

(Xr[+=], Yr/imm32)(Xr[+=], Yr/imm32)

load signed half from EX2 FIFO
load unsigned half from EX2 FIFO

ld

(Xr[+=], Yr/imm32)

load word from EX2 FIFO

floating-point operations
fmul(Xr, Yr)floating-point multiply

fma3
fadd

(Xr, Yr, Zr)(Xr, Yr)floating-point multiply and add
floating-point add(∗) += ... Get source from previous result of EX1 after first cycle. rgi[ ] should also be specified.
(†) {fhl} ... f:fullword h:byte3,byte2 ⇒ H16bit,L16bit l:byte1,byte0 ⇒ H16bit,L16bit(‡) sat ... Saturate 16bit ⇒ 8bit.

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Table.2.2: EX2 operations
32bit operations
andor(-/Xr, Zr/simm13/Yr/imm32)(-/Xr, Zr/simm13/Yr/imm32)

Xr and Zr/simm13/Yr/imm32
Xr or Zr/simm13/Yr/imm32

xor(-/Xr, Zr/simm13/Yr/imm32)

Xr xor Zr/simm13/Yr/imm32

16bit[2] operations
sumh(-/Xr)

H16bit+L16bit ⇒ H16bit

suml(-/Xr)

H16bit+L16bit ⇒ L16bit

Table.2.3: SFT operations
shift operations<<

Zr/imm5

logical shift to left>>
>M

Zr/imm5
Zr/imm5

logical shift to rightlogical shift high/low 16bit to right>A>B

Zr/imm5
Zr/imm5

arithmetic shift to right (original bit31 is sign extended)arithmetic shift to right (original bit23 is sign extended)>C>D

Zr/imm5
Zr/imm5

arithmetic shift to right (original bit15 is sign extended)arithmetic shift to right (original bit07 is sign extended)

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2.3. MEM OP

MEM OP

2.3

Memory operations are listed in Table 2.4.
Table.2.4: Memory operations
load from LMM or LMM FIFO
ldb
ldub

(Xr[+=], Yr.suffix/imm32), Dw(Xr[+=], Yr.suffix/imm32), Dw

load signed byte from LMM or LMM FIFO (∗)(†)
load unsigned byte from LMM or LMM FIFO (∗)(†)

ldh
lduh

(Xr[+=], Yr.suffix/imm32), Dw(Xr[+=], Yr.suffix/imm32), Dw

load signed half from LMM or LMM FIFO (∗)(†)
load unsigned half from LMM or LMM FIFO (∗)(†)

ld(Xr[+=], Yr.suffix/imm32), Dw

load word from LMM or LMM FIFO (∗)(†)

store to LMM
stb-/Zr, (Xr[+=], Yr.suffix/imm32)

store byte to LMM (∗)(†)

sthst-/Zr, (Xr[+=], Yr.suffix/imm32)-/Zr, (Xr[+=], Yr.suffix/imm32)

store half to LMM (∗)(†)
store word to LMM (∗)(†)

cst-/Zr, (Xr[+=], Yr.suffix/imm32)

if (c0.Z==1) store word to LMM (∗)(†)(∗) += ... Get source from previous result of EAG after first cycle. rgi[ ] should also be specified.
(†) suffix ... f:fullword h:H16bit l:L16bit 3:byte3 2:byte2 1:byte1 0:byte0

2.4

RGI

Each of ALU OP and MEM OP has dedicated rgi[labelX:, labelY:] section for initializing Xr and Yr.
RGI is just used for inserting labels at the location of initX and initY in each instruction, so that hostcomputer can identify the location where some initial value should be set before the instructions are sent
to EMAX2 device driver. Then, labelX and labelY should be unique name among the program. Noticethat even when same constant values should be set to several places, each location should have different
label each other.
In the case of register with an initial value, no register number is required because there is no register
dependency between such type of register and previous instructions. For saving the register numbers, “ri”
can be used instead of “r0-31”. Typical usage of “ri” is "ld (ri+=,4),r0 rgi[array_A_minus_4:,]"for sequential load starting at address array A. Notice that “the address of array A minus 4” should be
stored at label “array A minus 4:” because the first result of EAG is “ri+4”

2.5

LMM CONTROLLMM CONTROL specifies the type, start address, length, distance and some timing adjustment
information for transmitting data between main memory of host computer and local memory module
including FIFO. The format of LMM CONTROL depends on the type field which should be one of“lmr”, “lmw” , “lmx” or “lmf” (lmp and lmd are reserved for future extention).
lmr [ label:, len, dist ]This format is used for reading data from main memory of host computer to local memory module
including FIFO. “label:” corresponds to the start address of an array in main memory. “len” is thenumber of words to prefetch. “dist” expresses the distance between elements of array by 4<<dist.
In the case of normal array with single words, dist should be 0.
lmw [ label:, len, dist ]This format is used for writing data from local memory module to main memory of host computer

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after array execution completes.
lmx [ label:, len, dist ]This format is used when the local memory module should execute both of reading and writing.
lmf [ label:, len, dist ]This format is the same as “lmr” except the data in LMM is never reused, so that to read the latest
value of the same location.
lmp [ label:, len, dist ]This format is used for overlapping array execution and prefetching (reserved for future extension:macro-pipelining).
lmd [ label:, len, dist ]This format is used to write back (drain) LMM to host memory (reserved for future extension:macro-pipelining).

For the correct and effective control of FIFO, it is important to carefully combine a base register
number (Xr) of load operation, rgi specification and lmr/lmf.

@2,0,0 [320] ld (r12,0),r0 & ld (r12+=,4),r31 rgi[A_minus_4:,] lmr[A:,320,0]@2,1,0 [320]& ld (r12, 4),r1@2,2,0 [320]& ld (r12, 8),r2@2,3,0 [320]& ld (r12, 12),r3

In the case of above instructions, unit@2,1, unit@2,2, unit@2,3 have no lmr specification. The load
instruction without lmr is scheduled to get data from neighbor LMM through EMB and FIFO. The
appropriate source LMM is determined only by the base register number (r12). In this case, the memory
operation in unit@2,0 should be "ld (r12+=,4)", because "ld (ri+=,4)" gives no information about
connecting LMM and FIFOs. However, r12 in "ld (r12+=,4)" with rgi specification does not mean thevalue of previous r12. It just works as a marker to show the LMM is a source for FIFOs of neighborunits using the same base register r12. Note that the value of the base register r12 in the load instruction
without rgi specification is supplied from previous r12 (different from the value of r12 in "ld (r12+=,4)").

2.6

Hints for sophisticated use of hardware

Following is an example of image processing. The EAG part of each load and the destination registerof each sad are omitted to focus on the register dependency between load and sad. In this case, each resultof load instructions in @2,X is referred by sad at different column in @5,X. EMAX2 tries to route thedependency using several ETBs in @4,X. However, the routing is failed because each ETB is dedicatedto the same portion to simplify the switching network and only a path can be used to route the second
operand of sad (Yr). If "sad (r1,r26)" is changed to "sad (r26,r1)", other ETB in @4,X is used andthe routing is successfully completed.

@2,3,0 ld->r28 & ld ->r27@3,3,0
ld ->r3@4,3,0sad (r3,r27)@5,3,0sad (r3,r28)@2,2 ld ->r26@3,2 ld ->r2
@4,2 sad (r2,r26)@5,2 sad (r2,r27)@2,1 ld ->r25@3,1 ld ->r1
@4,1 sad (r1,r25)@5,1 sad (r1,r26)@2,0 ld ->r24@3,0 ld ->r0
@4,0 sad (r0,r24)@5,0 sad (r0,r25)However, following is more sophisticated scheduling. This example swaps @2.X and @3.X, @4.X and@5.X respectively. This means cross-column dependency should be put into adjacent row to save ETB
resource.

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2.7. APPLICATION BINARY INTERFACE

@2,3,0
ld ->r3@3,3,0 ld->r28 & ld ->r27@4,3,0sad (r3,r28)@5,3,0sad (r3,r27)

2.7@2,2 ld ->r2
@3,2 ld ->r26@4,2 sad (r2,r27)@5,2 sad (r2,r26)@2,1 ld ->r1
@3,1 ld ->r25@4,1 sad (r1,r26)@5,1 sad (r1,r25)@2,0 ld ->r0
@3,0 ld ->r24@4,0 sad (r0,r25)@5,0 sad (r0,r24)

Application Binary Interface

Application programs should be written according to the interface provided by EMAX2 device driver.
Following is a typical style for calling EMAX. “call emax2 start” is a function leading to pwritev(usb,iov, iovcnt, 0x10000100) system call. The first argument (.emax wvect) is the address of write vector andthe second argument (2) is the number of elements in the vector. The first element of write vector is apair of the start address of EMAX2 instructions (.emax wctrl) and its length in bytes (.emax wctrl end.emax wctrl). The second element of write vector is a pair of the start address of data to be transmitted
to EMAX2 and its length (320*4). Additional pair of the start address of read vector (.emax rvect) andthe number of elements (1) should be attached next to the final element of write vector, so that EMAX2
can setup some address translation information for writing the result back to the host computer througha buffer memory (DDR3 located between LMM and host computer is smaller than the main memory).
“call emax2 end” is a function leading to preadv(usb, iov, iovcnt, 0x10000100+read vect offset) system call. The first argument (.emax rvect) is the address of read vector and the second argument (1) is
the number of elements in the vector. The first element of read vector is a pair of the start address ofdata to be transmitted from EMAX2 and its length (320*4).

movl
movl
movl
movl
movl
addl
movl
movl



8(%ebp),%eax%eax,.emax_mmr04%eax,.emax_lmr04%eax,.emax_mmw08%eax,.emax_lmw08$-4,%eax%eax,.emax_rgi04%eax,.emax_rgi08

pushl $2
pushl $.emax_wvect
call emax2_start
addl $8, %esp
pushl $1
pushl $.emax_rvect
call emax2_end
addl $8, %esp
.data.p2align 4.emax_wvect: .long .emax_wctrl, .emax_wctrl_end-.emax_wctrl.emax_mmr04: .long 0x00000000, 320*4.emax_rvtlb: .long .emax_rvect, 1.emax_wctrl://EMAX2 @3,0 [320]& ld (ri+=,4),r11 rgi[.emax_rgi04:,] lmr[.emax_lmr04:,320,0]//EMAX2 @4,0 [320] minl (r10,r11) & st -,(ri+=,4)
rgi[.emax_rgi08:,] lmw[.emax_lmw08:,320,0].emax_wctrl_end:.emax_rvect:.emax_mmw08: .long 0x00000000, 320*4



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CHAPTER 2. SOFTWARE SPECIFICATION

2.8

Configuration data

The binary data of the instructions is not directly sent to each unit. Each unit requires lower level
information representing selection signal of each selectors and tri-state buffers as shown in Figure 2.3 andFigure 2.4, so that no complicated instruction decoder is required on each unit. Such binary translationfrom the instructions to the configuration data will be executed in EMAX2 device driver which canmemorize many configuration data and reuse them to speed up the translation.


struct conf { /* final information for EMAX2 hardware *//* struct ixbc: select any portion in the same unit */Uint ixbc0_sel_r : 4; /* 0:off 1:ex2.p1 2:ex2.p2 3:ex2.p3 4:mem.p1 5:mem.p2 6:mem.p3 8:ex2.d 9:mem.d */Uint ixbc1_sel_r : 4; /* 0:off 1:ex2.p1 2:ex2.p2 3:ex2.p3 4:mem.p1 5:mem.p2 6:mem.p3 8:ex2.d 9:mem.d */Uint ixbc2_sel_r : 4; /* 0:off 1:ex2.p1 2:ex2.p2 3:ex2.p3 4:mem.p1 5:mem.p2 6:mem.p3 8:ex2.d 9:mem.d */Uint ixbc3_sel_r : 4; /* 0:off 1:ex2.p1 2:ex2.p2 3:ex2.p3 4:mem.p1 5:mem.p2 6:mem.p3 8:ex2.d 9:mem.d *//* struct ixcc: select any portion in the same unit */Uint ixcc0_sel_r : 4; /* 0:off 7:prev_mem.pc 10:prev_ex2.c *//* struct idbc: dedicated to prev_ex2.d and prev_mem.d */Uint idbc0_sel_r : 1; /* 0:off 1:on */Uint idbc1_sel_r : 1; /* 0:off 1:on *//* struct idcc: dedicated to prev_ex2.d and prev_mem.d */Uint idcc0_sel_r : 1; /* 0:off 1:on *//* struct edbc: select dst portion among neighbor units */Uint edbc0_sel_r : 4; /* 0:off 8:prev_ex2.d 9:prev_mem.d */Uint edbc0_dir_r : 2; /* 0:off 1:to-left 2:to-right 3:inhibited */Uint _dmy0: 3;
Uint edbc1_sel_r : 4; /* 0:off 8:prev_ex2.d 9:prev_mem.d */Uint edbc1_dir_r : 2; /* 0:off 1:to-left 2:to-right 3:inhibited *//* struct edcc: select dst portion among neighbor units */Uint edcc0_sel_r : 4; /* 0:off 10:prev_ex2.c */Uint edcc0_dir_r : 2; /* 0:off 1:to-left 2:to-right 3:inhibited */Uint ex1c_s1_r: 3; /* 5to1 selector 0:prev_p1 1:self_loop 2:idb0 3:idb1 4:edb0 5:edb1 */Uint ex1c_s1_fhl : 2; /*1:SUFLO 2:SUFHI 3:ri/SUFFL */Uint ex1c_s2_r: 3; /* 5to1 selector 0:prev_p2
2:idb0 3:idb1 4:edb0 5:edb1 */Uint ex1c_s2_fhl : 2; /* 0:imm 1:SUFLO 2:SUFHI 3:ri/SUFFL */Uint ex1c_s3_r: 3; /* 5to1 selector 0:prev_p3
2:idb0 3:idb1 4:edb0 5:edb1 */Uint ex1c_s3_fhl : 2; /*1:SUFLO 2:SUFHI 3:ri/SUFFL */Uint ex1c_urZ_r : 1; /* opcd-extension */Uint _dmy1: 4;/* struct ex1c */Uint ex1c_op_r: 6;
Uint ex1c_px1_r : 2;
Uint ex1c_px2_r : 2;
Uint ex1c_x1_r: 3;
Uint ex1c_x2_r: 3;
Uint ex1c_x3_r: 3;/* struct ex2c */Uint ex2c_simmS_r:13;
Uint ex2c_immT_r : 5;
Uint ex2c_s1_r: 3;
Uint ex2c_s2_r: 3;
Uint ex2c_s3_r: 3;
Uint ex2c_op_r: 3;
Uint ex2c_sft_r : 3;
Uint ex2c_dsel_r : 1;
Uint ex2c_x1_r: 2;
Uint ex2c_x2_r: 2;
Uint ex2c_x3_r: 2;
Uint _dmy3: 5;/* ex1_opcd *//* 0:off 2:s2 *//* 0:off 3:s3 *//* 5to1 selector 0:prev_p[p] 4:ixb0 5:ixb1 6:ixb2 7:ixb3 *//* 5to1 selector 0:prev_p[p] 4:ixb0 5:ixb1 6:ixb2 7:ixb3 *//* 5to1 selector 0:prev_p[p] 4:ixb0 5:ixb1 6:ixb2 7:ixb3 *//* 0:d_r(ex1) 4:dx1_r(ex1) 5:dx2_r(ex1) 6:simmS_r 7:immT_r *//* 0:d_r(ex1) 4:dx1_r(ex1) 5:dx2_r(ex1) 6:simmS_r 7:immT_r *//* 0:d_r(ex1) 4:dx1_r(ex1) 5:dx2_r(ex1) 6:simmS_r 7:immT_r *//* ex2_opcd *//* sft_opcd *//* ex2-selector 0:ex2 direct 1:fifo *//* ex2-output-selector 0:fixed_for_constant 1:t1_direct 2:from etb[] *//* ex2-output-selector 0:fixed_for_constant 1:t2_direct 2:from etb[] *//* ex2-output-selector 0:fixed_for_constant 1:t3_direct 2:from etb[] */Figure.2.3: Lower level configuration data (1/2).

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2.8. CONFIGURATION DATA/* struct eagc */Uint eagc_s1_r: 3; /* 5to1 selector 0:prev_p1 1:self_loop 2:idb0 3:idb1 4:edb0 5:edb1 */Uint eagc_s2_r: 3; /* 5to1 selector 0:prev_p2
2:idb0 3:idb1 4:edb0 5:edb1 */Uint eagc_s2_suffix:3; /* 0:imm 1:SUFLO 2:SUFHI 3:SUFFL 4:SUFB0 5:SUFB1 6:SUFB2 7:SUFB3 */Uint eagc_s3_r: 3; /* 5to1 selector 0:prev_p3
2:idb0 3:idb1 4:edb0 5:edb1 */Uint eagc_sc_r: 3; /* 3to1 selector 0:prev_c2:idc0
4:edc0*/
Uint eagc_op_r: 10; /* mem_opcd */Uint eagc_x1_r: 3; /* 5to1 selector 0:prev_p[p] 4:ixb0 5:ixb1 6:ixb2 7:ixb3 */Uint eagc_x2_r: 3; /* 5to1 selector 0:prev_p[p] 4:ixb0 5:ixb1 6:ixb2 7:ixb3 */Uint _dmy4: 1;

Uint eagc_x3_r: 3; /* 5to1 selector 0:prev_p[p] 4:ixb0 5:ixb1 6:ixb2 7:ixb3 */Uint eagc_xc_r: 1; /* 2to1 selector 0:prev_p[p] 1:ixc0 *//* struct lmmc */Uint lmmc_ssel_r : 1; /* lmem-selector */Uint lmmc_dsel_r : 1; /* lmm-selector 0:lmm direct 1:fifo */Uint lmmc_x1_r: 2; /* mem-output-selector 0:fixed_for_constant 1:t1_direct 2:from etb[] */Uint lmmc_x2_r: 2; /* mem-output-selector 0:fixed_for_constant 1:t2_direct 2:from etb[] */Uint lmmc_x3_r: 2; /* mem-output-selector 0:fixed_for_constant 1:t3_direct 2:from etb[] */Uint lmmc_xc_r: 2; /* mem-output-selector
1:tc_direct 2:from etc[] */Uint lmmc_pc_r: 4; /* mem output(data) *//* struct embc: select memory portion among neighbor units */Uint embc0_sel_r : 1; /* 0:off 1:lmem */Uint embc0_dir_r : 2; /* 0:off 1:to-left
2:to-right
3:inhibited */Uint etbc0_sel_r : 1; /* 0:off 1:t[1-3] */Uint etbc0_dir_r : 2; /* 0:off 1:to-left
2:to-right
3:inhibited */Uint etbc1_sel_r : 1; /* 0:off 1:t[1-3] */Uint etbc1_dir_r : 2; /* 0:off 1:to-left
2:to-right
3:inhibited */Uint etbc2_sel_r : 1; /* 0:off 1:t[1-3] */Uint etbc2_dir_r : 2; /* 0:off 1:to-left
2:to-right
3:inhibited */Uint _dmy5: 2;
Uint etbc3_sel_r : 1; /* 0:off 1:t[1-3] */Uint etbc3_dir_r : 2; /* 0:off 1:to-left
2:to-right
3:inhibited */Uint etbc4_sel_r : 1; /* 0:off 1:t[1-3] */Uint etbc4_dir_r : 2; /* 0:off 1:to-left
2:to-right
3:inhibited *//* struct etbc: select same portion among neighbor units */Uint etbc5_sel_r : 1; /* 0:off 1:t[1-3] */Uint etbc5_dir_r : 2; /* 0:off 1:to-left
2:to-right
3:inhibited *//* struct etcc: select same portion among neighbor units */Uint etcc0_sel_r : 1; /* 0:off 1:c */Uint etcc0_dir_r : 2; /* 0:off 1:to-left
2:to-right
3:inhibited */Uint _dmy6: 20;
Uint v1: 1; /* unit 1/2 (ex1/eag) on */Uint v2: 1; /* unit 2/2 (ex2/lmm) on */Uint dist: 6; /* unit_map distance */Uint count: 16;
Uint _dmy7: 8;} conf[UNIT_DEPTH][UNIT_WIDTH]; /* 221bit(8words)/unit */

Figure.2.4: Lower level configuration data (2/2).

Y.Nakashima Proprietary & Confidential

EMAX2 ARCHITECTURE HANDBOOK

21

CHAPTER 2. SOFTWARE SPECIFICATION

2.9

Initial Values of Registers

Unlike the configuration data, the initial values of registers should be transmited to EMAX2 every
time before starting execution. The initial values of registers shown in Figure 2.5 are calculated by
EMAX2 device driver and transmitted to EMAX2 with other source data.
struct regv { /* final information for EMAX2 hardware */struct ex2v {/* inputs are connected to ex1.d*_r */Uint p1_r : 32; /* ex2 output(prop) */Uint p2_r : 32; /* ex2 output(prop) */} ex2v; /* 64bit */struct lmmv {Uint p1_r : 32; /* mem output(prop) */Uint p2_r : 32; /* mem output(prop) */} lmmv; /* 64bit */} regv[UNIT_DEPTH][UNIT_WIDTH]; /* 128bit(4words)/unit */

Figure.2.5: Initial Values of Registers.

2.10

LMM Information

Unlike the configuration data, LMM information should be transmited to EMAX2 every time before
starting execution. LMM information shown in Figure 2.6 are calculated by EMAX2 device driver andtransmitted to EMAX2 with other source data.
struct lmmi {struct ctl ctl; /* 2words */struct ddr3_tlb { /* DDR3 address translation (aligned by DDR3_MINALIGN) */Uint v: 2; /* 0:nop, 1:LMR, 2:LMW, 3:LMX */Uint msksft: 4;
Uint base : 12; /* ddr3 = (ddr3_base*DDR3_MINALIGN)|(intel_addr&((DDR3_MINALIGN<<ddr3_msksft)-1)) */Uint _dmy1 : 14;
Uint _dmy2 : 32;} ddr3_tlb; /* 2word */} lmmi[UNIT_DEPTH][UNIT_WIDTH]; /* 128bit(4words)/unit */

Figure.2.6: LMM Information.

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential

23

CHAPTER 3. EXAMPLES

Chapter 3

Examples3.1

tone curvefor(i=0; i<HT; i++)tone_curve( &R[i*WD], &D[i*WD], lut );//-----------------------------------------------------------------------------.text.p2align 2.globl tone_curve.type
tone_curve,@function
tone_curve: // void tone_curve(r, d, t) unsigned int *r, *d; unsigned char *t;// int j;// for (j=0; j<WD; j++) {//*d = ((t)[*r>>24])<<24 | (t[256+((*r>>16)&255)])<<16 | (t[512+((*r>>8)&255)])<<8;//
r++; d++;// }pushl %ebp
movl %esp,%ebp
pushl %edi/* reg for any */pushl %esi/* reg for any */pushl %ebx/* reg for any */movl 8(%ebp),%eax
movl %eax,.emax_mmf00_tone_curve /* MMFILL src Outer-Loop */movl %eax,.emax_lmf00_tone_curve /* LMFILL src Inner-Loop */addl $-4,%eax
movl %eax,.emax_rgi00_tone_curve /* RGINIT src Inner-Loop */movl 16(%ebp),%eax
movl %eax,.emax_mmr01_tone_curve /* MMFILL table Outer-Loop */movl %eax,.emax_lmr01_tone_curve /* LMFILL table Inner-Loop */movl %eax,.emax_rgi01_tone_curve /* RGINIT table Inner-Loop */addl $256,%eax
movl %eax,.emax_lmr02_tone_curve /* LMFILL table Inner-Loop */movl %eax,.emax_rgi02_tone_curve /* RGINIT table Inner-Loop */addl $256,%eax
movl %eax,.emax_lmr03_tone_curve /* LMFILL table Inner-Loop */movl %eax,.emax_rgi03_tone_curve /* RGINIT table Inner-Loop */movl 12(%ebp),%eax
movl %eax,.emax_mmw04_tone_curve /* MDRAIN dst Outer-Loop */movl %eax,.emax_lmw04_tone_curve /* LDRAIN dst Inner-Loop */addl $-4,%eax
movl %eax,.emax_rgi04_tone_curve /* RGINIT dst Inner-Loop */pushl $3
pushl $.emax_wvect_tone_curve
call emax2_start
addl $8, %esp
pushl $1
pushl $.emax_rvect_tone_curve
call emax2_end
addl $8, %esp
popl %ebx
popl %esi
popl %edi
leave
ret
.data
.p2align 4.emax_wvect_tone_curve: .long .emax_wctrl_tone_curve, .emax_wctrl_end_tone_curve-.emax_wctrl_tone_curve.emax_mmf00_tone_curve: .long 0x00000000, 320*4.emax_mmr01_tone_curve: .long 0x00000000, 768.emax_rvtlb_tone_curve: .long .emax_rvect_tone_curve, 1.emax_wctrl_tone_curve://EMAX2 @0,0,0 [320]& ld(ri+=,4),r9
rgi[.emax_rgi00_tone_curve:,] lmf[.emax_lmf00_tone_curve:,320,0]//EMAX2 @1,0,0 [320]& ldub (ri,r9.3),r10 rgi[.emax_rgi01_tone_curve:,] lmr[.emax_lmr01_tone_curve:, 64,0]//EMAX2 @1,1,0 [320]& ldub (ri,r9.2),r11 rgi[.emax_rgi02_tone_curve:,] lmr[.emax_lmr02_tone_curve:, 64,0]//EMAX2 @1,2,0 [320]& ldub (ri,r9.1),r12 rgi[.emax_rgi03_tone_curve:,] lmr[.emax_lmr03_tone_curve:, 64,0]//EMAX2 @2,0,0 [320] mmrg3 (r10,r11,r12) rgi[,] & st-,(ri+=,4)
rgi[.emax_rgi04_tone_curve:,] lmw[.emax_lmw04_tone_curve:,320,0].emax_wctrl_end_tone_curve:.emax_rvect_tone_curve:.emax_mmw04_tone_curve: .long 0x00000000, 320*4



EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential24

3.2. HOKAN1

3.2

hokan1for (i=4; i<HT-4; i++) { /* scan-lines */for (k=-4; k<4; k++)hokan1(&W[i*WD], &R[(i+k)*WD], SAD1->SAD1[i/4][k+4]);}//-----------------------------------------------------------------------------.text.p2align 2.globl hokan1.type
hokan1,@function
hokan1: // void hokan1(c, p, s) unsigned int *c, *p; unsigned short *s;// int j;// for (j=0; j<WD; j++) {//int j2 = j/4*4;//
int k = j%4*2;//* s+= df(c[j2],p[j2+k-4]) + df(c[j2+1],p[j2+k-3]) + df(c[j2+2],p[j2+k-2]) + df(c[j2+3],p[j2+k-1]); p[-4],p[-3],p[-2],p[-1] -> p[-2],p[-1],p[0],p[1]//*(s+1) += df(c[j2],p[j2+k-3]) + df(c[j2+1],p[j2+k-2]) + df(c[j2+2],p[j2+k-1]) + df(c[j2+3],p[j2+k ]); p[-3],p[-2],p[-1],p[ 0] -> p[-1],p[ 0],p[1],p[2]//s += 2;// }pushl %ebp
movl %esp,%ebp
pushl %edi/* reg for any */pushl %esi/* reg for any */pushl %ebx/* reg for any */movl 8(%ebp),%eax
addl $16,%eax
movl %eax,.emax_mmr00_hokan1 /* MMFILL src1 Outer-Loop */movl %eax,.emax_lmr00_hokan1 /* LMFILL src1 Inner-Loop */addl $-4,%eax
movl %eax,.emax_rgix0_hokan1 /* LMFILL src2 Inner-Loop */addl $-12,%eax
movl %eax,.emax_rgi00_hokan1 /* RGINIT src1 Inner-Loop */movl 12(%ebp),%eax
addl $16,%eax
movl %eax,.emax_mmr01_hokan1 /* MMFILL src2 Outer-Loop */movl %eax,.emax_lmr01_hokan1 /* LMFILL src2 Inner-Loop */addl $-4,%eax
movl %eax,.emax_rgix1_hokan1 /* LMFILL src2 Inner-Loop */addl $-12,%eax
movl %eax,.emax_rgi01_hokan1 /* RGINIT src2 Inner-Loop */movl 16(%ebp),%eax
movl %eax,.emax_mmf02_hokan1 /* MMFILL src3 Outer-Loop */movl %eax,.emax_lmf02_hokan1 /* LMFILL src3 Inner-Loop */movl %eax,.emax_mmw05_hokan1 /* MDRAIN dst Outer-Loop */movl %eax,.emax_lmw05_hokan1 /* LDRAIN dst Inner-Loop */addl $-4,%eax
movl %eax,.emax_rgi02_hokan1 /* RGINIT src3 Inner-Loop */movl %eax,.emax_rgi05_hokan1 /* RGINIT dst Inner-Loop */movl $-1,%eax
movl %eax,.emax_rgi03_hokan1 /* loop_counter */movl %eax,.emax_rgi04_hokan1 /* loop_counter */pushl $4
pushl $.emax_wvect_hokan1
call emax2_start
addl $8, %esp
pushl $1
pushl $.emax_rvect_hokan1
call emax2_end
addl $8, %esp
popl %ebx
popl %esi
popl %edi
leave
ret
.data
.p2align 4.emax_wvect_hokan1: .long .emax_wctrl_hokan1, .emax_wctrl_end_hokan1-.emax_wctrl_hokan1.emax_mmr00_hokan1: .long 0x00000000, 320*4.emax_mmr01_hokan1: .long 0x00000000, 320*4.emax_mmf02_hokan1: .long 0x00000000, 320*4.emax_rvtlb_hokan1: .long .emax_rvect_hokan1, 1.emax_wctrl_hokan1: /* +=は self_loop 指示 *///EMAX2 @0,0,0 [320] add (ri+=,1) | and (-,~3)<<2,r12 rgi[.emax_rgi03_hokan1:,]//EMAX2 @0,1,0 [320] add (ri+=,1) | and (-, 3)<<3,r13 rgi[.emax_rgi04_hokan1:,]//EMAX2 @1,0,0 [320] add (ri,r12),r12
rgi[.emax_rgi00_hokan1:,]//EMAX2 @1,1,0 [320] add3 (ri,r12,r13),r13
rgi[.emax_rgi01_hokan1:,]//EMAX2 @2,0,0 [320]ld (r12, 0),r0 & ld (r12+=,4),r31 rgi[.emax_rgix0_hokan1:,] lmr[.emax_lmr00_hokan1:,320,0]//EMAX2 @2,1,0 [320]& ld (r12, 4),r1//EMAX2 @2,2,0 [320]& ld (r12, 8),r2//EMAX2 @2,3,0 [320]& ld (r12, 12),r3//EMAX2 @3,0,0 [320]ld (r13,-16),r24 & ld (r13+=,4),r31 rgi[.emax_rgix1_hokan1:,] lmr[.emax_lmr01_hokan1:,320,0]//EMAX2 @3,1,0 [320]& ld (r13,-12),r25//EMAX2 @3,2,0 [320]& ld (r13, -8),r26//EMAX2 @3,3,0 [320]ld (r13, 0),r28 & ld (r13, -4),r27//@2.3
ld ->r3@2.2 ld ->r2
@2.1 ld ->r1
@2.0 ld ->r0//
@3.3 ld->r28 & ld ->r27@3.2 ld ->r26@3.1 ld ->r25@3.0 ld ->r24//@4.3
sad (r3,r28) @4.2 sad (r2,r27) @4.1 sad (r1,r26) @4.0 sad (r0,r25)//@5.3
sad (r3,r27) @5.2 sad (r2,r26) @5.1 sad (r1,r25) @5.0 sad (r0,r24)//EMAX2 @4,0,0 [320] msad (r0,r25),r11//EMAX2 @4,1,0 [320] msad (r1,r26),r13 ! swap r1 and r26 to avoid collision of pos2//EMAX2 @4,2,0 [320] msad (r2,r27),r15//EMAX2 @4,3,0 [320] msad (r3,r28),r17//EMAX2 @5,0,0 [320] msad (r0,r24),r10//EMAX2 @5,1,0 [320] msad (r1,r25),r12//EMAX2 @5,2,0 [320] msad (r2,r26),r14//EMAX2 @5,3,0 [320] msad (r3,r27),r16//EMAX2 @6,0,0 [320] mauh (r10,r12),r10//EMAX2 @6,1,0 [320] mauh (r11,r13),r11//EMAX2 @6,2,0 [320] mauh (r14,r16),r14//EMAX2 @6,3,0 [320] mauh (r15,r17),r15//EMAX2 @7,0,0 [320] mauh (r10,r14) | suml (-),r10//EMAX2 @7,1,0 [320] mauh (r11,r15) | sumh (-),r11//EMAX2 @7,2,0 [320]& ld (ri+=,4),r0 rgi[.emax_rgi02_hokan1:,] lmf[.emax_lmf02_hokan1:,320,0]//EMAX2 @8,0,0 [320] mauh3 (r0,r10,r11)& st -,(ri+=,4) rgi[.emax_rgi05_hokan1:,] lmw[.emax_lmw05_hokan1:,320,0].emax_wctrl_end_hokan1:.emax_rvect_hokan1:.emax_mmw05_hokan1: .long 0x00000000, 320*4



Y.Nakashima Proprietary & ConfidentialEMAX2 ARCHITECTURE HANDBOOK

25

CHAPTER 3. EXAMPLES

3.3

hokan2for (i=4; i<HT-4; i+=4) { /* scan-lines */for (k=-4; k<4; k++)hokan2(SAD1->SAD1[i/4][k+4], &W[i*WD], (((k/2)&0xff)<<16)); /* 8 回走査して SAD 最小位置を求める */}//-----------------------------------------------------------------------------.text.p2align 2.globl hokan2.type
hokan2,@function
hokan2: //void hokan2(s, sminxy, k) unsigned short *s; unsigned int *sminxy; int k;// int j;// for (j=0; j<WD; j++) { /* j%4==0 の時のみ sminxy[j] に有効値．他はゴミ *///if ((sminxy[j]&0xffff) > *(s )) sminxy[j] = ((-2)<<24)|k|*(s );//if ((sminxy[j]&0xffff) > *(s+1)) sminxy[j] = ((-1)<<24)|k|*(s+1);//
if ((sminxy[j]&0xffff) > *(s+2)) sminxy[j] = ((-1)<<24)|k|*(s+2);//
if ((sminxy[j]&0xffff) > *(s+3)) sminxy[j] = (( 0)<<24)|k|*(s+3);//
if ((sminxy[j]&0xffff) > *(s+4)) sminxy[j] = (( 0)<<24)|k|*(s+4);//
if ((sminxy[j]&0xffff) > *(s+5)) sminxy[j] = (( 0)<<24)|k|*(s+5);//
if ((sminxy[j]&0xffff) > *(s+6)) sminxy[j] = (( 1)<<24)|k|*(s+6);//
if ((sminxy[j]&0xffff) > *(s+7)) sminxy[j] = (( 1)<<24)|k|*(s+7);//
s += 2;// }pushl %ebp
movl %esp,%ebp
pushl %edi/* reg for any */pushl %esi/* reg for any */pushl %ebx/* reg for any */movl 8(%ebp),%eax
addl $8,%eax
movl %eax,.emax_mmr03_hokan2 /* MMFILL src1 Outer-Loop */movl %eax,.emax_lmr03_hokan2 /* LMFILL src1 Inner-Loop */addl $-12,%eax
movl %eax,.emax_rgi00_hokan2 /* RGINIT src1 Inner-Loop */addl $4,%eax
movl %eax,.emax_rgi01_hokan2 /* RGINIT src1 Inner-Loop */addl $4,%eax
movl %eax,.emax_rgi02_hokan2 /* RGINIT src1 Inner-Loop */addl $4,%eax
movl %eax,.emax_rgi03_hokan2 /* RGINIT src1 Inner-Loop */movl 12(%ebp),%eax
movl %eax,.emax_mmf04_hokan2 /* MMFILL src2 Outer-Loop */movl %eax,.emax_lmf04_hokan2 /* LMRENEW src2 Inner-Loop */movl %eax,.emax_mmw08_hokan2 /* MDRAIN dst Outer-Loop */movl %eax,.emax_lmw08_hokan2 /* LDRAIN dst Inner-Loop */addl $-4,%eax
movl %eax,.emax_rgi04_hokan2 /* RGINIT src2 Inner-Loop */movl %eax,.emax_rgi08_hokan2 /* RGINIT dst Inner-Loop */movl 16(%ebp),%eax
movl %eax,.emax_rgi05_hokan2 /* RGINIT src3 Inner-Loop */movl %eax,.emax_rgi06_hokan2 /* RGINIT src3 Inner-Loop */movl %eax,.emax_rgi07_hokan2 /* RGINIT src3 Inner-Loop */movl %eax,.emax_rgi10_hokan2 /* RGINIT src3 Inner-Loop */movl %eax,.emax_rgi11_hokan2 /* RGINIT src3 Inner-Loop */movl %eax,.emax_rgi12_hokan2 /* RGINIT src3 Inner-Loop */pushl $3
pushl $.emax_wvect_hokan2
call emax2_start
addl $8, %esp
pushl $1
pushl $.emax_rvect_hokan2
call emax2_end
addl $8, %esp
popl %ebx
popl %esi
popl %edi
leave
ret
.data
.p2align 4.emax_wvect_hokan2: .long .emax_wctrl_hokan2, .emax_wctrl_end_hokan2-.emax_wctrl_hokan2.emax_mmr03_hokan2: .long 0x00000000, 320*4.emax_mmf04_hokan2: .long 0x00000000, 320*4.emax_rvtlb_hokan2: .long .emax_rvect_hokan2, 1.emax_wctrl_hokan2: /* +=は self_loop 指示 *///EMAX2 @0,0,0 [320] |or (ri,(-2<<24)),r28 rgi[.emax_rgi05_hokan2:,] & ld (r31+=,4),r10 rgi[.emax_rgi00_hokan2:,]//EMAX2 @0,1,0 [320] |or (ri,(-1<<24)),r29 rgi[.emax_rgi06_hokan2:,] & ld (r31+=,4),r12 rgi[.emax_rgi01_hokan2:,]//EMAX2 @0,2,0 [320] |or (ri,( 1<<24)),r31 rgi[.emax_rgi07_hokan2:,] & ld (r31+=,4),r14 rgi[.emax_rgi02_hokan2:,]//EMAX2 @0,3,0 [320]& ld (r31+=,4),r16 rgi[.emax_rgi03_hokan2:,] lmr[.emax_lmr03_hokan2:,320,0]//EMAX2 @1,0,0 [320] minl3 (r29,r28,r10),r10//EMAX2 @1,1,0 [320] minl3 (ri,r29, r12),r12 rgi[.emax_rgi10_hokan2:,]//EMAX2 @1,2,0 [320] minl3 (ri, ri, r14),r14 rgi[.emax_rgi12_hokan2:,.emax_rgi11_hokan2:]//EMAX2 @1,3,0 [320] minl3 (r31,r31,r16),r16//EMAX2 @2,0,0 [320] minl (r10,r12),r10//EMAX2 @2,2,0 [320] minl (r14,r16),r14//EMAX2 @3,0,0 [320] minl (r10,r14),r10& ld (ri+=,4),r11 rgi[.emax_rgi04_hokan2:,] lmf[.emax_lmf04_hokan2:,320,0]//EMAX2 @4,0,0 [320] minl (r10,r11)& st -,(ri+=,4)
rgi[.emax_rgi08_hokan2:,] lmw[.emax_lmw08_hokan2:,320,0].emax_wctrl_end_hokan2:.emax_rvect_hokan2:.emax_mmw08_hokan2: .long 0x00000000, 320*4



EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential26

3.4. HOKAN3

3.4

hokan3for (i=0; i<HT; i++) { /* scan-lines */for (k=-2; k<2; k++)hokan3(&W[(i/4*4)*WD], &R[(i+k)*WD], &D[i*WD], k);}//-----------------------------------------------------------------------------.text.p2align 2.globl hokan3.type
hokan3,@function
hokan3: //void hokan3(sminxy, r, d, k) unsigned int *sminxy; unsigned int *r, *d; int k;// int j;// for (j=0; j<WD; j++) {//int x = (int) sminxy[j/4*4]>>24;//
int y = (int)(sminxy[j/4*4]<<8)>>24;//
if (y == k) d[j] = r[j+x];// }pushl %ebp
movl %esp,%ebp
pushl %edi/* reg for any */pushl %esi/* reg for any */pushl %ebx/* reg for any */movl 8(%ebp),%eax
movl %eax,.emax_mmr00_hokan3 /* MMFILL src1 Outer-Loop */movl %eax,.emax_lmr00_hokan3 /* LMFILL src1 Inner-Loop */movl %eax,.emax_rgi00_hokan3 /* RGINIT src1 Inner-Loop */movl 12(%ebp),%eax
movl %eax,.emax_mmr01_hokan3 /* MMFILL src2 Outer-Loop */movl %eax,.emax_lmr01_hokan3 /* LMFILL src2 Inner-Loop */movl %eax,.emax_rgi01_hokan3 /* RGINIT src2 Inner-Loop */movl 16(%ebp),%eax
movl %eax,.emax_mmx02_hokan3 /* RGINIT src3 Inner-Loop */movl %eax,.emax_lmx02_hokan3 /* RGINIT src3 Inner-Loop */movl %eax,.emax_mmx08_hokan3 /* MDRAIN dst Outer-Loop */addl $-4,%eax
movl %eax,.emax_rgi02_hokan3 /* RGINIT src3 Inner-Loop */movl 20(%ebp),%eax
movl %eax,.emax_rgi03_hokan3 /* RGINIT src3 Inner-Loop */movl $-1,%eax
movl %eax,.emax_rgi04_hokan1 /* loop_counter */movl %eax,.emax_rgi05_hokan1 /* loop_counter */pushl $4
pushl $.emax_wvect_hokan3
call emax2_start
addl $8, %esp
pushl $1
pushl $.emax_rvect_hokan3
call emax2_end
addl $8, %esp
popl %ebx
popl %esi
popl %edi
leave
ret
.data
.p2align 4.emax_wvect_hokan3: .long .emax_wctrl_hokan3, .emax_wctrl_end_hokan3-.emax_wctrl_hokan3.emax_mmr00_hokan3: .long 0x00000000, 320*4.emax_mmr01_hokan3: .long 0x00000000, 320*4.emax_mmx02_hokan3: .long 0x00000000, 320*4.emax_rvtlb_hokan3: .long .emax_rvect_hokan3, 1.emax_wctrl_hokan3: /* +=は self_loop 指示 *///EMAX2 @0,0,0 [320] add (ri+=,1) | and (-,~3)<<2,r12 rgi[.emax_rgi04_hokan3:,]//EMAX2 @0,1,0 [320] add (ri+=,1) | or (-, 0)<<2,r14 rgi[.emax_rgi05_hokan3:,]//EMAX2 @1,0,0 [320]& ld (ri,r12),r16 rgi[.emax_rgi00_hokan3:,] lmr[.emax_lmr00_hokan3:,320,0]//EMAX2 @2,0,0 [320] add (ri,r14),r13
rgi[.emax_rgi01_hokan3:,]//EMAX2 @2,1,0 [320] |and (r16,0xff000000)>A22,r17 ! >A は SRA//EMAX2 @2,2,0 [320] |and (r16,0x00ff0000)>B16,r18 ! >B は bit23 を符号拡張 >C は bit15 を符号拡張 >D は bit7 を符号拡張//EMAX2 @3,0,0 [320] sub (r18,ri),r0 c0
rgi[,.emax_rgi03_hokan3:] & ld (r13,r17),r16 rgi[,]lmr[.emax_lmr01_hokan3:,320,0]//EMAX2 @4,0,0 [320]& cst r16,(ri+=,4) rgi[.emax_rgi02_hokan3:,] lmx[.emax_lmx02_hokan3:,320,0].emax_wctrl_end_hokan3:.emax_rvect_hokan3:.emax_mmx08_hokan3: .long 0x00000000, 320*4



Y.Nakashima Proprietary & ConfidentialEMAX2 ARCHITECTURE HANDBOOK

27

CHAPTER 4. CONTROL

Chapter 4

Control
評価システムおよび ASIC 拡張機能のハードウェア仕様については付録を参照のこと．

LMM の仕様4.1

図 4.1 と図 4.2 に，LMM の構造およびタイミングチャートを示す．
edb0[31:0]0edb1[63:0]
eagc_s3_r

EAGfrom EX1
skip
lmmc_ssel_ra[12:3]

di[63:32]

di[31:0]

wide

wex

en

clk

if (wide=0) select low-word else high-word
if ((wide=1 | (wide=0 & a[2]=1)) & wex=0) we=1 else 0
if ((wide=1 | (wide=0 & a[2]=0)) & wex=0) we=1 else 0
addr[9:0]

din[31:0] we en clk

addr[9:0]

din[31:0] ween clk

RAM-4KB

RAM-4KB

dout[31:0]

dout[31:0]

if (wide=0 & a[2]=1) select high-word else low-word

do[63:32]

do[31:0]
emb[63:0]

Figure.4.1: Structure of LMM.

clk
en
wex

write

read

wide
a[12:3]

A1

di[63:0]

D1

do[63:0]

A2

D1

D2

Figure.4.2: Timing chart of LMM.

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential4.2. 使用するメモリ空間

4.2

28

使用するメモリ空間

前述した制御情報（conf[][]，regv[][]，および，lmmi[][]）は，演算対象データ（wdata 群）とともに，HOST
から DDR3 へ転送される．メモリマップを表 4.1 に示す．なお，EMAX2 の初期モデルでは，PE0 に対応する空間のみが使用される．
┌USB0─────────────────────────────────────────┐│││命令変換/TLB生成後││usb_space_mem_writev(usb, iov, iovcnt, ddr3_atop=10000100);││
iov[0].iov_base = ddr3_wlist[]={10002000,10004000,10006000,10100000,...}││
iov[0].iov_len = (iovcnt-1+readiov)*4││
iov[1].iov_base = conf[][]->10002000││
iov[1].iov_len = sizeof(conf)││iov[2].iov_base = regv[][]->10004000││
iov[2].iov_len = sizeof(regv)││
iov[3].iov_base = lmmi[][]->10006000││
iov[3].iov_len = sizeof(lmmi)││
iov[4].iov_base = wdata1[]->10100000││
iov[4].iov_len = bytes1││
iov[5].iov_base = wdata2[]->10200000││
iov[5].iov_len = bytes2
│
│
:
│
│
│
│usb_space_mem_pe0_l2ct0000.l2ct0000.m_stat = 3;│
│usb_space_mem_write(usb, &usb_space_mem_pe0_l2ct0000, 4, USB_SPACE_MEM_PE0_L2CT0000); ││0x10000078 ││do {││ usb_space_mem_read(usb, &usb_space_mem_pe0_l2ct0000, 4, USB_SPACE_MEM_PE0_L2CT0000); ││} while (usb_space_mem_pe0_l2ct0000.l2ct0000.m_stat != 1);0x10000078 ││││usb_space_mem_readv(usb, iov, iovcnt, ddr3_atop=10000100+readiovoffset);││iov[0].iov_base = ddr3_rlist[]={10300000,...} iovcnt-1││
iov[0].iov_len = (iovcnt-1)*4││
iov[1].iov_base = rdata1[]<-10300000││
iov[1].iov_len = bytes1││
iov[2].iov_base = rdata2[]<-10400000││
iov[2].iov_len = bytes2││:│├───────────────────────────────────────────┤│ 0x0000003f-0x00000000:DMA制御││ 0x0000017f-0x00000100:PE0.REG││[ 0x000001ff-0x00000180:PE1.REG] reserved││ 0x1000007f-0x10000000:PE0.L2CT││[ 0x100000ff-0x10000080:PE1.L2CT] reserved││--0x1fffffff-0x10000100:USER----------------------------------------------------------││ 0x10003fff-0x10002000:PE0.emax_wctrl(8KB) for conf│
│ 0x10005fff-0x10004000:PE0.emax_wregv(8KB) for regv│
│ 0x10007fff-0x10006000:PE0.emax_wlmmi(8KB) for lmmi│
│ 0x17ffffff-0x10100000:PE0.data(1MB*127)
for data││[ 0x18003fff-0x18002000:PE1.emax_wctrl(8KB) ] reserved││[ 0x18005fff-0x18004000:PE1.emax_wregv(8KB) ] reserved││[ 0x18007fff-0x18006000:PE1.emax_wlmmi(8KB) ] reserved││[ 0x1fffffff-0x18100000:PE1.data(1MB*127) ] reserved││[ 0x2fffffff-0x20000000:other-side-DDR3] (unused)│└───────────────────────────────────────────┘┌USB1─────────────────────────────────────────┐│ 0x0000003f-0x00000000:DMA制御││[ 0x0000017f-0x00000100:PE2.REG] reserved││[ 0x000001ff-0x00000180:PE3.REG] reserved││[ 0x1000007f-0x10000000:PE2.L2CT] reserved││[ 0x100000ff-0x10000080:PE3.L2CT] reserved││--0x1fffffff-0x10000100:USER----------------------------------------------------------││[ 0x10003fff-0x10002000:PE2.emax_wctrl(8KB) ] reserved││[ 0x10005fff-0x10004000:PE2.emax_wregv(8KB) ] reserved││[ 0x10007fff-0x10006000:PE2.emax_wlmmi(8KB) ] reserved││[ 0x17ffffff-0x10100000:PE2.data(1MB*127) ] reserved││[ 0x18003fff-0x18002000:PE3.emax_wctrl(8KB) ] reserved││[ 0x18005fff-0x18004000:PE3.emax_wregv(8KB) ] reserved││[ 0x18007fff-0x18006000:PE3.emax_wlmmi(8KB) ] reserved││[ 0x1fffffff-0x18100000:PE3.data(1MB*127) ] reserved││[ 0x2fffffff-0x20000000:other-side-DDR3] PE0空間を参照可能│└───────────────────────────────────────────┘

Table.4.1: 初期モデルにおけるメモリ空間の運用

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29

CHAPTER 4. CONTROL

4.3

各 UNIT に対する制御情報の伝達struct emax2 {Uint pe0_status
Uint unit_offset


:
:

4;
4; /* current mapped insn_row[0] */Uint unit_edb_cmd: 3; /* 0:idle, 1:conf, 2:regv, 3:lmmi, 4:lmm_load, 5:exec, 6:lmm_drain */Uint unit_edb_cmd_d1: 3; /* delay1 */Uint unit_edb_cmd_d2: 3; /* delay2 */Uint unit_ctl_count: 7; /* unit counter */Uint unit_select_row: 16; /* bitmap 0:off 1:selected */Uint unit_select_col: 4; /* bitmap 0:off 1:selected */Uint unit_select_row_d1: 16; /* delay1 */Uint unit_select_col_d1: 4; /* delay1 */Uint unit_edb_valid: 1; /* edb_valid (for HDL only) */Uint unit_edb0: 32; /* write_data regno/lmm_address */Ull unit_edb1: 64; /* config/write_data to unit */Uint unit_emb_valid: 1; /* emb_valid (for HDL only) */Ull unit_emb: 64; /* read_data from unit */struct ctl
ctl_old[UNIT_DEPTH][UNIT_WIDTH];
struct ctl
ctl_new[UNIT_DEPTH][UNIT_WIDTH];
struct ddr3_tlb ddr3_tlb[UNIT_DEPTH][UNIT_WIDTH];
Uint prev2_status;
Ull unit1_status[UNIT_WIDTH]; /* 1bit corresponds to each unit (ex1,eag), 0:stop 1:run */Uint prev1_status;
Ull unit2_status[UNIT_WIDTH]; /* 1bit corresponds to each unit (ex2,lmm), 0:stop 1:run */} emax2;

Figure.4.3: General control information of EMAX2.
HOST により DDR3 に格納された制御情報を各 unit に伝達するために使用する制御信号を図 4.3 に示す．各制御信号は，pe0 status の値に応じて以下のように動作する．

4.3.1

Idle (pe0 status=STATUS IDLE)

M STAT が 3 でない場合は状態を維持する．M STAT が 3 の場合，pe0 status=STATUS CONF に遷
移し，unit edb cmd および wrdyc（カウンタ）を 0 にリセットする．

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential4.3. 各 UNIT に対する制御情報の伝達

4.3.2

30

Unit configuration in progress (pe0 status=STATUS CONF)

conf[][] を元に各 unit の構成を変更する．conf[][] 再利用機構が有効である場合，DDR3 は参照せず，
EMAX2 内部のシフト機構により conf[][] を再利用する（初期モデルでは本機構は無効である）．DDR3
を参照する場合，M WEX=1，M BSTMX=0 （バーストリード）を使用して DDR3 から conf[][] を読み出す．各 unit は，unit edb cmd，unit edb valid，行指定ビットマップ（unit select row）の該当行ビット，
および，列指定ビットマップ（unit select col）の該当列ビットを監視しており，unit edb cmd=1，かつ，unit edb valid=1，かつ，該当ビットが 1 の場合に，EDB0[1:0] の内容を書き込み先構成情報レジスタグルー
プ識別子（0-3），EDB1[63:0] の内容を構成情報レジスタ値として書き込みを行う．全ての unit に対して書き込みが完了すると，pe0 status=STATUS REGV に遷移する．タイミングチャートを図 4.4 に示す．
CK
Mx_ADSX
Mx_AD

A

Mx_WEX

Read

D1

Mx_BSTMX

Burst

Mx_XREQ+0

Mx_XGNT

+1

+2

+3

+4

待ち

+5

+6

+7

1

2

3

4

5

0

1

2

3

0

バースト中に待たせるケース

Mx_RRDY
Mx_BSYX
wrdyc

0

unit_edb0
READ_DATAラッチ

unit_edb1

6
1

7

8

2

3

D1

unit_edb_valid
unit_cmd

10

unit_select_row

0000000000000000

0000000000000001

unit_select_col

0000

0001

1000000000000000…

conf_registers

1000

D1

Figure.4.4: conf[][] → unit[][] のタイミングチャート

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EMAX2 ARCHITECTURE HANDBOOK

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CHAPTER 4. CONTROL

4.3.3

Register initialization in progress (pe0 status=STATUS REGV)

regv[][] を元に各 unit のレジスタ値を初期化する．M WEX=1，M BSTMX=0（バーストリード）を使用して DDR3 から regv[][] を読み出す．各 unit は，unit edb cmd，unit edb valid，行指定ビットマップ（unit select row）の該当行ビット，および，列指定ビットマップ（unit select col）の該当列ビットを監視しており，unit edb cmd=2，かつ，unit edb valid=1，かつ，該当ビットが 1 の場合に，EDB0[0] の内容を書き込み先レジスタグループ識別子（0-1），EDB1[63:0] の内容をレジスタ値として書き込みを行う．全ての unit に対して書き込みが完了すると，pe0 status=STATUS LMMI に遷移する．タイミングチャート
を図 4.5 に示す．
CK
Mx_ADSX
Mx_AD

A

Mx_WEX

Read

D1

Mx_BSTMX

Burst

Mx_XREQ+0

Mx_XGNT

+1

+2

+3

+4

待ち

+5

+6

+7

1

2

3

4

5

0

1

0

1

0

バースト中に待たせるケース

Mx_RRDY
Mx_BSYX
wrdyc

0

unit_edb0
READ_DATAラッチ

unit_edb1

6
1

7

8

0

1

D1

unit_edb_valid
unit_cmd

20

unit_select_row

0000000000000000

unit_select_col

0000

0000000000000001

1000000000000000…

target_registers

0001

0010

0100

1000

D1

Figure.4.5: regv[][] → unit[][] のタイミングチャート

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential4.3. 各 UNIT に対する制御情報の伝達

4.3.4

32

LMM tag initialization in progress (pe0 status=STATUS LMMI)

conf[][] を元に LMM タグ情報（unit 毎ではなく全体に１つ存在）を初期化する．M WEX=1，M BSTMX=0（バーストリード）を使用して DDR3 から lmmi[][] を読み出す．EDB0[0] の内容を書き込み先識別子（0 の場合 ctl new，1 の場合 ddr3 tlb），EDB1[63:0] の内容を設定値として書き込みを行う．全ての lmmi[][] の書き込みが完了すると，pe0 status=STATUS LMM LOAD に遷移する．タイミングチャートを図 4.6 に示す．
CK
Mx_ADSX
Mx_AD

A

Mx_WEX

Read

D1

Mx_BSTMX

Burst

Mx_XREQ+0

Mx_XGNT

+1

+2

+3

+4

待ち

+5

+6

+7

1

2

3

バースト中に待たせるケース

Mx_RRDY
Mx_BSYX
wrdyc

0

4

5

6

7

8
stop

ctl_new[row][col]D1

ddr3_tlb[row][col]Figure.4.6: lmmi[][] → ctl new[][]/ddr3 tlb[][] のタイミングチャート

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CHAPTER 4. CONTROL

4.3.5

LMM loading in progress (pe0 status=STATUS LMM LOAD)

前述の ctl new 情報に基づき，1 つの LMM 毎に，M WEX=1，M BSTMX=0（バーストリード）を使用して DDR3 から各 unit の LMM に初期値をロードする．なお，前回実行時に使用した ctl new[][] がctl old[][] に保存されており，該当 unit に対応する，ctl old[i][j].top = ctl new[i][j].top，ctl old[i][j].len ≥ctl new[i][j].len，かつ，ctl old[i][j].dist = ctl new[i][j].dist の場合は LMM の内容を再利用できるためロードが省略される．各 unit は，unit edb cmd，unit edb valid，行指定ビットマップ（unit select row）の該当行
ビット，および，列指定ビットマップ（unit select col）の該当列ビットを監視しており，unit edb cmd=4，
かつ，unit edb valid=1，かつ，該当ビットが 1 の場合に，EDB0[12:3] の内容を書き込み先アドレス（最大 1K ダブルワード），EDB1[63:0] の内容を LMM 値として書き込みを行う．1 つの LMM の更新が完了する度に，該当する ctl new[][] の内容が ctl old[][] に保存される．必要な LMM の書き込みが完了すると，

pe0 status=STATUS START に遷移する．タイミングチャートを図 4.7 に示す．
CK
Mx_ADSX

ddr3_tlb[i][j].base*DDR3_MINALIGN) | ((ctl_new[i][j].top+wrdyc*8)&(DDR3_MINALIGN-1))

Mx_AD

A

Mx_WEX

Read

D1

Mx_BSTMX

Burst

Mx_XREQ+0

Mx_XGNT

+1

+2

+3

+4

待ち

+5

+6

+7

1

2

3

4

5

+8

+8

+8

+8

バースト中に待たせるケース

Mx_RRDY
Mx_BSYX
wrdyc

0

unit_edb0

ctl_new[i][j].top+wrdyc*8

A1

unit_edb1

READ_DATAラッチ

D1

6
+8

7

8

+8

+8

unit_edb_valid
unit_cmd

40

unit_ctl_count0

unit_select_row

0000000000000000

unit_select_col

0000

…

63
10...

…

1000

clk
en
write

wex

write

wide
a[12:3]

A1

di[63:0]

D1

do[63:0]

+8

+8

+8

+8

+8

+8

+8

D1

Figure.4.7: source DDR3 → lmm[][] のタイミングチャート

4.3.6

Start execution (pe0 status=STATUS START)EMAX2 の演算を開始する．各 unit は，unit edb cmd，unit edb valid，行指定ビットマップ（unit select row）の該当行ビット，および，列指定ビットマップ（unit select col）の該当列ビットを監視しており，unit edb cmd=5，
かつ，該当ビットが 1 の場合に，連続演算の起点として，当該 unit が起動する．なお，本状態に遷移した
次のサイクルにおいて，pe0 status=STATUS EXEC に遷移する．

4.3.7

Execution in progress (pe0 status=STATUS EXEC)

unit edb cmd=5 を維持したまま，EMAX2 の連続演算を継続する．全 unit の演算が完了した場合，
pe0 status=STATUS LMM DRAIN に遷移する．

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential4.3. 各 UNIT に対する制御情報の伝達

34

LMM drainage in progress (pe0 status=STATUS LMM DRAIN)

4.3.8

前述の ctl new 情報に基づき，1 つの LMM 毎に，M WEX=0，M BSTMX=0（バーストライト）を使用して各 unit の LMM から DDR3 に演算結果をストアする．各 unit は，unit edb cmd，unit edb valid，
行指定ビットマップ（unit select row）の該当行ビット，および，列指定ビットマップ（unit select col）の該当列ビットを監視しており，unit edb cmd=6，かつ，unit edb valid=1，かつ，該当ビットが 1 の場合に，EDB0[12:3] の内容を読み出し元アドレス（最大 1K ダブルワード），EMB0[63:0] を LMM 値として読み出しを行う．必要な LMM の読み出しが完了すると，pe0 status=STATUS TERM に遷移する．タイミ
ングチャートを図 4.8 に示す．
wrdyc

0

unit_edb0

1

2

3

4

5

6

7

A1

+8

+8

+8

+8

+8

+8

8
+8

9
+8

+8

ctl_new[i][j].top+wrdyc*8

unit_edb_valid
unit_cmd

6

unit_ctl_count00…

unit_select_row

0000000000000000

unit_select_col

0000

63
10...

…

1000

clk
en
wex
wide
a[12:3]

+8

+8

+8

+8

+8

+8

+8

do[63:0]

A1

D1

D2

D3

D4

D5

D6

D7

D8

+8

unit_emb0

READ_DATAラッチ

D1

D2

D3

D4

D5

D6

D7

+8
D9

D8

D10
D9

D10

unit_emb_valid
drain_buf0

drain_buf2
drain_buf3

D5
Mx再開時に供給

Mx停止時にバッファリング

D4

drain_buf1

D6
D7
4サイクル停止に対して4個のバッファで吸収できる

CK
Mx_ADSX

ddr3_tlb[i][j].base*DDR3_MINALIGN) | ((ctl_new[i][j].top+rrdyc*8)&(DDR3_MINALIGN-1))

Mx_AD

A

D1

Mx_WEX

D2

D3

D4

D5

D6

D7

D8

D9

D10

+3

+4

+5

+6

+7

+8

+9

D3

D4

D5

D6

D7

D8

D9

更新せず

Write

Mx_BSTMX

Burst

Mx_XREQ
Mx_XGNT

バースト中に待たせるケース

Mx_WRDY

書き込み完了

+0

+1 待ち
D1

D2

+2

D10

Mx_BSYX

Figure.4.8: lmm[][] → result DDR3 のタイミングチャート

4.3.9

Terminate execution (pe0 status=STATUS TERM)

M STAT に 1 を書き込み，unit offset を更新し，pe0 status=STATUS IDLE に遷移する．

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35

CHAPTER 5. HOW TO USE EMAX2 SIMULATOR

Chapter 5

How to use EMAX2 simulator
5.1

Compiling application programs

See “all:” tag in proj-emax/sample/filter/Makefile-emax2.

5.2

Executing application programs

See ”run:” tag in proj-emax/sample/filter/Makefile-emax2. For monitoring the internal status of
EMAX2, insert following code in the application program. These functions are defined in emax2.c.


emax2_show_status_start(); /* detailed information */emax2_show_demo_start();/* full-screen summary of execution */EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & ConfidentialAPPENDIX A. 評価システム

37

Appendix A

評価システムA.1

GP6X760MP システムの構成

GP6X760MP システムは，XC6V760 × 1，ASIC ソケットボード× 4，256MB-DDR3 × 2，および，USB3.0 インタフェース× 2 を備え，2 本の USB ケーブルにより PC/AT 互換機（HOST）に接続される．
プロセッサ機能（以下 PE）を FPGA または ASIC ソケットボード上に，メモリ機能を DDR3 上に，また，
主記憶機能および入出力機能を HOST 上に各々対応付けることにより，全体として実用アプリケーションを走行できる装置である．図 A.1 に全体構成，表 A.1 に，USB 毎に HOST に写像されるアドレス空間を示す．
各 USB インタフェースには，256MB の DDR3 および 2 組の PE が対応付けられる．
「PE0/1 からの参照」列は，PE に許可されるアクセス種別，「HOST からの参照」列は，HOST に許可されるアクセス種別を示す．なお，HOST が pe reset に非ゼロの 16 ビット値を書き込んだ場合，PE に至る PE0 RESET 信号
が HIGH となる．pe reset が毎サイクルデクリメントされて 0 に達した後に PE0 RESET 信号が LOW に復帰する．

HOST が h p に対して非ゼロの制御コマンドを書き込んだ場合， f stat に 1 （STATUS BUSY）がセッ
トされ，その後，各機能毎に規定された値がセットされる．h s に対して非ゼロの制御コマンドを書き込んだ場合，s stat に 1 （STATUS BUSY）がセットされ，その後，各機能毎に規定された値がセットされる．

PE は，HOST からの h p または h s への書き込みに伴って LOW になる C XINT 信号により，h p または
h s の更新を検知し，Cx *を用いて制御レジスタを直接参照することにより，h p，h s，h param，h controlを受け取る．PE が Cx XINT を検出し Cx XACK を LOW にした時点で，Cx XINT は HIGH にならなけ
ればならない．Cx XREQ は PE が制御レジスタに対して書き込みまたは読み出しを行う際に LOW にする信号線である．ただし，EMAX2 の初期モデルでは，本 HOST インタフェースは使用されない．

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential

Figure.A.1: 全体構成

38

EMAX2 ARCHITECTURE HANDBOOK

266M 50/40M
↓
↓
┌───┐
┌──┐
┌┴──┬┴──┐┌───────────────┐┌───────────────┐│HOST │││┌┤266M │50/40M●─────────────●PE0 FMC*2 are used(72*2pin) │ ┌──────────●PE1 FMC*2 are used(72*2pin) ││││││├───┘ ↑ │┐CLK(50/40M) →in │FPGA->MICTOR=14│ │CLK(50/40M) →in │FPGA->MICTOR
=14
│
│
│
│
│
││
32bit│●─ RST→in │ASIC-PIN(42+82+5)=129│─┘RST→in │ASIC-PIN(42+82+5)=129
│
│
│
│
│
││
││
│
│
│
│
│
│
│
│
││
││
C0_XINT→in │ ┌───sub board ────┐│C1_XINT→in │ ┌───sub board ────┐│
│
│
│
│
││
32bit
││
C0_XACK←out│ │*CLK*M_XREQ││C1_XACK←out│ │*CLK*M_XREQ│││││││├───↑───┤│
C0_XREQ←out│ │*RST*M_XGNT││C1_XREQ←out│ │*RST*M_XGNT
││
│
│
│
│
││
c_reg[] ││C0_A[3:0]←out│ │*C_XINT*M_WEX││
C1_A[3:0]←out│ │*C_XINT*M_WEX│││││PIO │││
s_reg[] ││C0_WEX←out│ │*C_XACK*M_BSTMX││
C1_WEX←out│ │*C_XACK*M_BSTMX││││USB0│DMA │LBUS0 │└┬──────┘│
C0_D_OEX[31:0] ←out│ │*C_XREQ
M_BEX[7:0] ││C1_D_OEX[31:0] ←out│ │*C_XREQ
M_BEX[7:0] │││mmap()├──┤CORE├───┤ └───────┘
C0_D_OUT[31:0] ←out│ │*C_A[3:0] *M_ADSX││
C1_D_OUT[31:0] ←out│ │*C_A[3:0] *M_ADSX│││ 512MB││││┌───┬───┐
C0_D_IN [31:0] →in │ │*C_WEX
M_AD[63:0] ││C1_D_IN [31:0] →in │ │*C_WEX
M_AD[63:0] ││││││└┤266M │50/40M●─────────────● │ C_D[31:0] *M_WRDY││ ┌──────────● │ C_D[31:0] *M_WRDY
││
│
│
│
│
├───┴───┤┐
M0_XREQ←out│ │
*M_RRDY││ │M1_XREQ←out│ │
*M_RRDY
││
│
│
│
│
│
M_STAT│●─ M0_XGNT→in │ │
*M_BSYX││─┘M1_XGNT→in │ │
*M_BSYX
││
│
│
│
│
│
↑ ││
M0_WEX←out│ │
*M_STAT[1:0]││
M1_WEX←out│ │
*M_STAT[1:0]││
│
│
│
│
│
64bit││
M0_BSTMX←out│ │││
M1_BSTMX←out│ │││││││└┬──────┘│
M0_BEX[7:0]←out│ │TDI
above*20->MICTOR││
M1_BEX[7:0]←out│ │TDI
above*20->MICTOR││││││└──┬────┘
M0_ADSX←out│ │TDO
MICTOR.CLK0<-CLK││
M1_ADSX←out│ │TDO
MICTOR.CLK0<-CLK││││││┌───┴───┐
M0_AD_OEX[63:0]←out│ │TMS
MICTOR.CLK1<-RST││
M1_AD_OEX[63:0]←out│ │TMS
MICTOR.CLK1<-RST││
│
│
│
│
│
32bit
│
M0_AD_OUT[63:0]←out│ │TCK
rest*14pin<-FPGA││
M1_AD_OUT[63:0]←out│ │TCK
rest*14pin<-FPGA││││││├───↑───┤
M0_AD_IN [63:0]→in │ │TRST
total*34->MICTOR││
M1_AD_IN [63:0]→in │ │TRST
total*34->MICTOR││
│
│
│
│
│400M
│
M0_WRDY→in │ └────────────┘│
M1_WRDY→in │ └────────────┘│││└──┘│ DDR3#0 256MB │M0_RRDY→in └───────────┬──┬┘
M1_RRDY→in └┬──┬───────────┘││││
M0_BSYX→in
CH1[0-13]│ CH2│
M1_BSYX→in │CH1 │CH2[0-13]││└───────┘
M0_STAT[1:0] →in same pin# are connected││
M1_STAT[1:0] →in ││same pin# are connected│││└──────────────┘│││CH2[0-13]│ CH1┌──────────────┐CH2 │CH1[0-13]││┌──┐┌───┬───┐┌───────────┴──┴┐┌┴──┴───────────┐││││┌┤266M │50/40M●─────────────●PE2 FMC*2 are used(72*2pin) │ ┌──────────●PE3 FMC*2 are used(72*2pin) ││││││├───┘│┐│FPGA->MICTOR
=14
│ │
│
FPGA->MICTOR
=14
│
│
│
│
│
││
c_reg[] │●────────────│
ASIC-PIN(42+82+5)=129│─┘│
ASIC-PIN(42+82+5)=129││││PIO │││
s_reg[] ││
C2_*
│
│
C3_*
│
│
│
│USB1│DMA │LBUS1 │└┬──────┘││ ┌───sub board ────┐││ ┌───sub board ────┐││mmap()├──┤CORE├───┤ └───────┘
│ │
││
│ │
││
│ 512MB││││┌───┬───┐
│ │
││
│ │
││
│
│
│
│
└┤266M │50/40M●─────────────● │││ ┌──────────● │
││
│
│
│
│
├───┴───┤┐
│ │
││ │
│ │
││
│
│
│
│
│
M_STAT│●────────────│ │
││─┘
│ │
││
│
│
│
│
└┬──────┘│
M2_*
│ │
││
M3_*
│ │
││
│
│
│
│
└──┬────┘
│ │
││
│ │
││
│
│
│
│
┌───┴───┐│ └────────────┘││ └────────────┘│
└───┘
└──┘
│400M
│
└───────────────┘└───────────────┘│ DDR3#1 256MB │└───────┘

A.1. GP6X760MP システムの構成

Y.Nakashima Proprietary & Confidential※ M_AD[27:3] is valid when M_ADSX=0 (M_AD holds the address for 64bit data bus of DDR3).
※ M_AD_OEX is connected to (M_ADSX & M_WEX). ※ C_D_OEX is connected to C_WEX.

APPENDIX A. 評価システム

39

Table.A.1: 制御レジスタ空間と DDR3 空間┌────────┬───────────────┬──────────────┬──────────────┐│HOST address
│
Notes
│
from PE0/1│
from HOST-PC│├────────┼───────────────┼──────────────┼──────────────┤│0x0000003f - 000│DMA control registers│-- out of space│RW│├────────┼───────────────┼──────────────┼──────────────┤│0x00000043 - 040│reset & status register│-- out of space│RW│││ GRST
bit0││W:1 start reset│││││R:1 reset in progress│┝━━━━━━━━┿━━━━━━━━━━━━━━━┿━━━━━━━━━━━━━━┿━━━━━━━━━━━━━━┥│0x0000013f - 100│HOST->PE0 control registers │R C_A[3:0]=0-7│RW│├────────┼───────────────┼──────────────┼──────────────┤│0x00000107 - 100│ h_p
bit15- 4│R│RW:non-0 write ->f_stat=1 │││ h_s
bit31-16│R│RW:non-0 write ->s_stat=1 ││0x0000010f - 108│ h_param
lower 4bytes │R│RW││0x00000117 - 110│ h_control
lower 4bytes │R│RW││0x0000011f - 118│
-N.A.│-N.A.│RW-N.A.││0x00000127 - 120│ pe_reset
bit15- 0│-│RW:non-0 write -> PEx-reset ││0x0000013f - 128│
-N.A.│-N.A.│-N.A.│┝━━━━━━━━┿━━━━━━━━━━━━━━━┿━━━━━━━━━━━━━━┿━━━━━━━━━━━━━━┥│0x0000017f - 140│PE0->HOST status registers│RW C_A[3:0]=8-15│R│├────────┼───────────────┼──────────────┼──────────────┤│0x00000147 - 140│ f_stat
bit15-10│RW│R:h_p non-0 write -> 1││
│ s_statbit23-16│RW│R:h_s non-0 write -> 1│
│0x0000014f - 148│ p_param
lower 4bytes │RW│R││0x0000017f - 150│
-N.A.│-N.A.│-N.A.│┝━━━━━━━━┿━━━━━━━━━━━━━━━┿━━━━━━━━━━━━━━┿━━━━━━━━━━━━━━┥│0x000001bf - 180│HOST->PE1 control registers │R C_A[3:0]=0-7│RW│├────────┼───────────────┼──────────────┼──────────────┤│0x00000187 - 180│ h_p
bit15- 4│R│RW:non-0 write ->f_stat=1 │││ h_s
bit31-16│R│RW:non-0 write ->s_stat=1 ││0x0000018f - 188│ h_param
lower 4bytes │R│RW││0x00000197 - 190│ h_control
lower 4bytes │R│RW││0x0000019f - 198│
-N.A.│-N.A.│RW-N.A.││0x000001a7 - 1a0│ pe_reset
bit15- 0│-│RW:non-0 write -> PEx-reset ││0x000001bf - 1a8│
-N.A.│-N.A.│-N.A.│┝━━━━━━━━┿━━━━━━━━━━━━━━━┿━━━━━━━━━━━━━━┿━━━━━━━━━━━━━━┥│0x000001ff - 1c0│PE1->HOST status registers│RW C_A[3:0]=8-15│R│├────────┼───────────────┼──────────────┼──────────────┤│0x000001c7 - 1c0│ f_stat
bit15-10│RW│R:h_p non-0 write -> 1││
│ s_statbit23-16│RW│R:h_s non-0 write -> 1│
│0x000001cf - 1c8│ p_param
lower 4bytes │RW│R││0x000001ff - 1d0│
-N.A.│-N.A.│-N.A.│┝━━━━━━━━┿━━━━━━━━━━━━━━━┿━━━━━━━━━━━━━━┿━━━━━━━━━━━━━━┥│0x1fffffff │local DDR3 space(256MB)│RW M_A│RW││
0x10000000││ burst mode│
PIO/DMA│├────────┼───────────────┼──────────────┼──────────────┤│0x10000077 - 000│ 通常データ│PE0用RW│RW││0x1000007f - 078│ PE0.L2CT_0000 bit5-4│W:0書き込み時M_STAT=0│W:0書き込み時M_STAT=0││││W:1書き込み時M_STAT=1│W:2書き込み時M_STAT=2│││││W:3書き込み時M_STAT=3││││ バースト時も上記機能は有効│
DMA時も上記機能は有効│├────────┼───────────────┼──────────────┼──────────────┤│0x100000f7 - 080│ 通常データ│PE1用RW│RW││0x100000ff - 0f8│ PE1.L2CT_0000 bit5-4│W:0書き込み時M_STAT=0│W:0書き込み時M_STAT=0││││W:1書き込み時M_STAT=1│W:2書き込み時M_STAT=2│││││W:3書き込み時M_STAT=3││││ バースト時も上記機能は有効│
DMA時も上記機能は有効│┝━━━━━━━━┿━━━━━━━━━━━━━━━┿━━━━━━━━━━━━━━┿━━━━━━━━━━━━━━┥│0x2fffffff │other DDR3 space(256MB)│RW M_A│RW││
0x20000000││ burst mode│
他系USBからのみPIO/DMA可 │└────────┴───────────────┴──────────────┴──────────────┘

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & ConfidentialA.2. プロセッサ機能と HOST 機能のインタフェース

A.2

40

プロセッサ機能と HOST 機能のインタフェース

表 A.2 に PE と HOST 機能のインタフェース，図 A.2 にタイミングチャートを示す．ただし，EMAX2の初期モデルでは，本 HOST インタフェースは使用されない．

Table.A.2: プロセッサ-HOST 機能のインタフェース信号（ASIC インタフェースとしては 40 本）
信号名
説明
Cx XINT(in)HOST からのリクエスト信号，Active-LOWCx XACK(out)プロセッサからの INT 受付け信号，Active-LOW

Cx XREQ(out)プロセッサからのレジスタ参照信号，Active-LOW

Cx A[3:0](out)アドレス，A3-0

Cx WEX(out)

書き込みイネーブル，Active-LOW

Cx D OEX[31:0](out) Cx D OUT の各 bit に対応する出力イネーブル， Active-LOW．全
bit に Cx WEX を 2 サイクル遅延させた信号が接続される．
Cx D OUT[31:0](out) 出力データ，D31-0
Cx D IN([31:0]in)

入力データ，D31-0

CLK
Cx_A

a

b

c

e

f

f

Cx_XREQ
Cx_WEX
Cx_WEXを2サイクル遅延させた信号

Cx_D_OEX
Cx_D

Wa Wb Rc
write write read

Re
Wf
Rf
read write read
Wfの値がRfに読み出される

Figure.A.2: プロセッサ制御インタフェースのタイミングチャート (WRITE/READ)

Y.Nakashima Proprietary & Confidential

EMAX2 ARCHITECTURE HANDBOOKAPPENDIX A. 評価システム

41

A.3

プロセッサ機能と DDR3 のインタフェース

表 A.3 に PE と DDR3 のインタフェース，図 A.3 から図 A.6 にタイミングチャートを示す．

Table.A.3: プロセッサ-DDR3 のインタフェース信号（ASIC インタフェースとしては 82 本）
信号名
方向 説明
Mx XREQ

out

DDR3 参照要求信号，Active-LOW

Mx XGNTin

要求受付完了信号，Active-LOW．バースト時，次のデータを送信できることを示す

Mx WEXout

書き込みイネーブル，Active-LOW

Mx BSTMX

out

バーストモード，Active-LOW．HIGH 復帰後の最初の CLK ↑がバースト転送の最終回

Mx BEX[7:0]outMx AD OUT がデータである場合の byte 単位書き込みイネーブル，
Active-LOW

Mx ADSX

out

0 の場合 Mx AD OUT はアドレス，1 の場合データ

Mx AD OEX[63:0]

out

Mx AD OUT の各 bit に対応する出力イネーブル, Active-LOW．全
bit に (Mx ADSX & Mx WEX) が接続される

Mx AD OUT[63:0]

out

Mx ADSX が 0 の場合アドレス (bit27-3 のみ有効)，1 の場合データ

Mx AD IN[63:0]

in

入力データ

Mx WRDY

in

書き込み完了信号，Active-HIGH．本信号のカウントによりプロセッ
サは書き込み完了を知る

Mx RRDYin

読 み 出 し 完 了 信 号 ，Active-HIGH．本 信 号 に よ り プ ロ セッサ は

Mx AD IN の有効値を取り込む
Mx BSYXin

Mx STAT[1:0]in

動作中を示すビジー信号，Active-LOW．HIGH 時は次の参照要求を発行できることを示す
状態表示信号，STAT1-0（0:empty 2:OP-ok 3:IF-ok）は，特定アドレスへの書き込み値を反映する

CK
Mx_ADSX
Mx_AD

A

Mx_WEXWriteD
XGNTを待たずにMx_Dを変化させるということ（プロセッサ優先）

Mx_BSTMX

プロセッサがXGNT数に基づき制御

Mx_XREQ
Mx_XGNT
Mx_WRDY+0
書き込み完了Mx_BSYX
次のXREQ発行不可

Figure.A.3: DDR3 インタフェースのタイミングチャート (WRITE)

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & ConfidentialA.3. プロセッサ機能と DDR3 のインタフェース

42

CK
Mx_ADSXMx_ADAD
XGNTを待たずにMx_Dを変化させるということ（プロセッサ優先）

Write

Mx_WEX
Mx_BSTMX

Burst

プロセッサがXGNT数に基づき制御

Mx_XREQ+0

Mx_XGNT

+1

+2

+3

+4

+5

Mx_WRDY

書き込み完了Mx_BSYX

次のXREQ発行不可

+6

+7

+5

+6

非BURSTとして有効な最終REQ

CK
Mx_ADSX
Mx_AD

A

D
Write

Mx_WEX

更新せず

Mx_BSTMX

Burst

Mx_XREQ
Mx_XGNT

待ち

+0

+1

+2

+3

+4

+7

書き込み完了

Mx_WRDY
Mx_BSYX

開始直後に待たせるケース
CK
Mx_ADSX
Mx_AD

A

D
更新せず

Write

Mx_WEX
Mx_BSTMX

Burst

Mx_XREQ+0

Mx_XGNT

+1

+2

+3

+4

待ち

+5

+6

+7

書き込み完了

Mx_WRDY
Mx_BSYX

バースト中に待たせるケース
CK
Mx_ADSX
Mx_AD

A

D
更新せず

Write

Mx_WEX
Mx_BSTMX

Burst

Mx_XREQ
Mx_XGNT

+0

+1

+2

+3

+4

+5

+6

待ち

+7

書き込み完了

Mx_WRDY
Mx_BSYX

バースト停止直後に待たせるケース

Figure.A.4: DDR3 インタフェースのタイミングチャート (WRITE バーストモード)

Y.Nakashima Proprietary & Confidential

EMAX2 ARCHITECTURE HANDBOOKAPPENDIX A. 評価システム

43

CK
Mx_ADSXREAD_DATAラッチ

Mx_AD

A

Mx_WEX

Read

D

Mx_BSTMX

プロセッサがXGNT数に基づき制御

Mx_XREQ
Mx_XGNT+0
読み出し完了Mx_RRDY
Mx_BSYX
次のXREQ発行不可

Figure.A.5: DDR3 インタフェースのタイミングチャート (READ)

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & ConfidentialA.3. プロセッサ機能と DDR3 のインタフェース

44

CK
Mx_ADSXREAD_DATAラッチ

Mx_AD

A

Mx_WEX

Read

D

Mx_BSTMX

Burst

プロセッサがXGNT数に基づき制御

Mx_XREQ+0

Mx_XGNT

+1

+2

+3

+4

+5

Mx_RRDY+6+7

非BURSTとして有効な最終REQ

読み出し完了Mx_BSYX
次のXREQ発行不可
CK
Mx_ADSXREAD_DATAラッチ

Mx_AD

A

Mx_WEX

Read

D

Mx_BSTMX

Burst

Mx_XREQ
Mx_XGNT

待ち

+0

+1

+2

+3

+4

+5

+6

+7

Mx_RRDY
Mx_BSYX

開始直後に待たせるケース
CK
Mx_ADSXREAD_DATAラッチ

Mx_AD

A

Mx_WEX

Read

D

Mx_BSTMX

Burst

Mx_XREQ+0

Mx_XGNT

+1

+2

+3

+4

待ち

+5

+6

+7

Mx_RRDY
Mx_BSYX

バースト中に待たせるケース
CK
Mx_ADSXREAD_DATAラッチ

Mx_AD

A

Mx_WEX

Read

D

Mx_BSTMX

Burst

Mx_XREQ
Mx_XGNT

+0

+1

+2

+3

+4

+5

+6

待ち

+7

Mx_RRDY
Mx_BSYX

バースト停止直後に待たせるケース

Figure.A.6: DDR3 インタフェースのタイミングチャート (READ バーストモード)

Y.Nakashima Proprietary & Confidential

EMAX2 ARCHITECTURE HANDBOOKAPPENDIX B. ASIC 拡張機能

45

Appendix B

ASIC 拡張機能
B.1

QFP208 パッケージ用インタフェース

XC6V760 と各 GPSUB-ASICEDB(ドータボード) の物理インタフェースは，ローカルメモリインタフェー
ス信号（82 本），および，プロセッサ制御インタフェース信号（40 本）の合計 122 本を収容する．さらに，スキャン用信号 5 本，クロック，リセットの 2 本を加えた合計 129 本が ASIC に接続される I/O である．
また，図 A.1 に示すように，129 本のうち 20 本は MICTOR コネクタに接続され，MICTOR コネク
タの残り 14 本には，FPGA のピンが 1 対 1 に接続される．すなわち，129+14=143 本が，XC6V760 と各GPSUB-ASICEDB を接続する信号線である．
さらに，図 A.1 に示すように，ドータボード間接続用に，CH0 および CH1（各 14 本）が設けられている．CH0 と CH1 の同一番号ピンがケーブルにより直接接続され， CH0-CH0 間，または，CH1-CH1 間が接続されることはない．

ASIC（ROHM/TSMC：QFP208）のピン配置制約は次の通り．
• VDD(1.8V)：計 12 ピン（11，32，52，63，84，104，115，136，156，167，188，208）• VDDO(3.3V)：計 12 ピン（1，21，42，53，73，94，105，125，146，157，177，198）• VSS：計 24 ピン（2，12，22，31，41，51，54，64，74，83，93，103，106，116，126，135，145，
155，158，168，178，187，197，207）• JTAG 用 TDI，TDO，TMS，TCK，TRST：計 5 ピン（未使用時はプルアップ）• クロック，リセット入力ピン：計 2 ピン
• 一般信号用：残り 153 ピン．同時スイッチングする出力ピンおよび双方向ピンは，電源ピンに近接配置．電源ピンごとに分散配置．電源グループに対する同時スイッチング出力バッファの許容本数を守る．同時スイッチングする出力バッファや，その近傍の出力バッファを他 LSI のクロック入力としない．また，ドライバビリティの大きな出力ピンは中央に配置．
コア電圧は 1.8V．I/O は 3.3V．電源ピンを除く合計 160 ピンのうち 129 本が FPGA に接続される．

ASIC の I/O には，駆動力 2mA のドライバを推奨する．なお，ROHM0.18 μの I/O バッファには以下を推奨する．TSMC0.18 μについても同様の駆動能力を推奨する．

• PC30B01 入出力用．出力用 I ピンおよび OEN の容量は各 22fF（INV × 3 に相当）．OEN × 8 ピンを駆動するには 8 倍 INV が必要．
• PC30D01 入力専用．PAD から CIN の遅延は負荷 FO4/FO32 で約 200ps/300ps．INV × 32 まで直接駆動可能．
• PC30O01 出力専用．I から PAD の遅延は負荷 20pF/60pF で 5ns/10ns．

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential

Logic Analizer
34signals

PE0

PE1

B.1. QFP208 パッケージ用インタフェース

USB0

To Config-PC

1

CH1
CH2
14 1
14

1

CH1
CH2
14 1
14

XILINX
red-box

POWER
UNIT

14
1 14
1
CH2
CH1

14
1 14
1
CH2
CH1

PE2

PE3

Logic Analizer
34signals

Logic Analizer
34signals

USB1

46

EMAX2 ARCHITECTURE HANDBOOK

Figure.B.1: GP6X760 ボードの構成

Y.Nakashima Proprietary & Confidential

To HOST

Logic Analizer
34signals

AB25
AC25
AC34
AD34
AC33
AD33
AC29
AD29

V31
U31
U34
U33
AB28
AC28
AB26
AC26

T24
U24
T25
U25
U26
U27
T29
U29

T33
R34
R27
T27
U28
T28
U30
T30

M_AD[39](IO)
M_AD[38](IO)
M_AD[37](IO)
M_AD[36](IO)
M_AD[35](IO)
M_AD[34](IO)
M_AD[33](IO)
M_AD[32](IO)

M_AD[47](IO)
M_AD[46](IO)
M_AD[45](IO)
M_AD[44](IO)
M_AD[43](IO)
M_AD[42](IO)
M_AD[41](IO)
M_AD[40](IO)

CH0[7](IO)
CH0[6](IO)
CH0[5](IO)
CH0[4](IO)
CH0[3](IO)
CH0[2](IO)
CH0[1](IO)
CH0[0](IO)

M_AD[55](IO)
M_AD[54](IO)
M_AD[53](IO)
M_AD[52](IO)
M_AD[51](IO)
M_AD[50](IO)
M_AD[49](IO)
M_AD[48](IO)

TCK(IN)GND
TDI(IN)
TRST(IN)TMS(IN)TDO(OUT)GND
CLK(IN)C_XINT(IN)
C_XACK(OUT)
C_XREQ(OUT)
C_A[3](OUT)
C_A[2](OUT)
C_A[1](OUT)
C_A[0](OUT)
C_WEX(OUT)

VDDI(1.8V)
VDDE(3.3V)
VSS

M_BEX[0](OUT)
M_BEX[1](OUT)
M_BEX[2](OUT)
M_BEX[3](OUT)
M_BEX[4](OUT)
M_BEX[5](OUT)
M_BEX[6](OUT)
M_BEX[7](OUT)

C_D[15](IO)
C_D[14](IO)
C_D[13](IO)
C_D[12](IO)
C_D[11](IO)
C_D[10](IO)
C_D[09](IO)
C_D[08](IO)

Rohm-0.18 5x5mm:1 milion gates
QFP208

M_AD[24](IO)
M_AD[25](IO)
M_AD[26](IO)
M_AD[27](IO)
M_AD[28](IO)
M_AD[29](IO)
M_AD[30](IO)
M_AD[31](IO)

C_D[07](IO)
C_D[06](IO)
C_D[05](IO)
C_D[04](IO)
C_D[03](IO)
C_D[02](IO)
C_D[01](IO)
C_D[00](IO)

M_STAT[0](IN)
M_STAT[1](IN)CH1[8](IO)
CH1[9](IO)
CH1[10](IO)
CH1[11](IO)
CH1[12](IO)
CH1[13](IO)

104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53

AD26
AE26
AD25
AE24
AE33
AF34
AG33
AF33
AG32
AF32
AG31
AF31
AE29
AF29
AE27
AF27
AE25
AF25
AF30
AG30
AF28
AG28
AF26
AG26
AG29
AH29
AH34
AJ34
AH33
AJ33
AH32
AJ32
AK31
AJ31
AK34
AL34
AK33
AL33
AK32
AL32

1
2
3
L31
M31 4
5
L26
6
K26
7
L25
8
K24
9
K30
K31 10
11
12
K29 13
L30 14
K28 15
L28 16
K27 17
J26 18J33 19K33 2021
22
J30 23
H30 24
J28 25
J27 26
H33 27
J34 28H32 29J32 3031
32
H31 33
J31 34
H28 35
J29 36
G30 37
F30 38G29 39H29 4041
42
F34 43
G34 44
F33 45
G33 46
F32 47
G32 48
E31 49F31 50
51
52

M27
L27
L34
M34
L33
M33
L32
M32

C_D[23](IO)
C_D[22](IO)
C_D[21](IO)
C_D[20](IO)
C_D[19](IO)
C_D[18](IO)
C_D[17](IO)
C_D[16](IO)

M_AD[16](IO)
M_AD[17](IO)
M_AD[18](IO)
M_AD[19](IO)
M_AD[20](IO)
M_AD[21](IO)
M_AD[22](IO)
M_AD[23](IO)

N26
M26
N25
M25
M29
L29
M28
N28

PE0_RESET(IN)
M_BSYX(IN)
M_WEX(OUT)
M_BSTMX(OUT)
M_XREQ(OUT)
M_XGNT(IN)
M_WRDY(IN)
M_RRDY(IN)CH1[0](IO)
CH1[1](IO)
CH1[2](IO)
CH1[3](IO)
CH1[4](IO)
CH1[5](IO)
CH1[6](IO)
CH1[7](IO)

N33
P33
N32
P32
N31
P31
N30
P30

M_ADSX(OUT)

C_D[31](IO)
C_D[30](IO)
C_D[29](IO)
C_D[28](IO)
C_D[27](IO)
C_D[26](IO)
C_D[25](IO)
C_D[24](IO)

CH0[8](IO)
CH0[9](IO)
CH0[10](IO)
CH0[11](IO)
CH0[12](IO)
CH0[13](IO)

M_AD[08](IO)
M_AD[09](IO)
M_AD[10](IO)
M_AD[11](IO)
M_AD[12](IO)
M_AD[13](IO)
M_AD[14](IO)
M_AD[15](IO)

R25
P25
P29
N29
P27
N27
N34
P34

157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208

M_AD[00](IO)
M_AD[01](IO)
M_AD[02](IO)
M_AD[03](IO)
M_AD[04](IO)
M_AD[05](IO)
M_AD[06](IO)
M_AD[07](IO)

R32
T32
R31
T31
R29
R28
R26
P26

M_AD[63](IO)
M_AD[62](IO)
M_AD[61](IO)
M_AD[60](IO)
M_AD[59](IO)
M_AD[58](IO)
M_AD[57](IO)
M_AD[56](IO)

156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105

AC27
AD27
AD32
AE31
AD30
AE30
AD28
AE28

APPENDIX B. ASIC 拡張機能

47

Figure.B.2: QFP208 のピン配置（周辺の記号は XILINX の対応ピン番号（現状は仮））EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential

49

APPENDIX C. REFERENCES

Appendix C

References
本章では，関連仕様書・規格，参考文献，関連ソースプログラム，および，EMAX2 ツールチェインを
列挙する．

C.1

GP6X760 documents• GP6X760 PIO-DMA コア概要仕様書.pdf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-gp6x760/doc/GP6X760 用 PIO-DMA コア概要仕様書.pdf• ChipScope 概要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-gp6x760/doc/ChipScope.pdf• TB-6V-LX760-LSI ハードユーザマニュアル. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-gp6x760/doc/TB-6V-LX760-LSI HWUserManual 3.01.pdf• TB-6V-LX760-LSI 回路図. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-gp6x760/doc/TB-6V-LX760-LSI Schematic 2.00.pdf• TB-6V-LX760-LSI USB-DDR3 スタートアップガイド. . . . . . . . . . . . . . . . . . . . . . . . proj-gp6x760/doc/TB-6V-LX760-LSI USB-DDR3 StartUpGuide 1.01.pdf• TB-FMCH-CONNECTER 回路図. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .proj-gp6x760/doc/TB-FMCH-CONNECTER Schematic 2.00.pdf• TB-FMCH-STACK 回路図. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-gp6x760/doc/TB-FMCH-STACK Schematic 2.00.pdf• TB-FMCL-USB30 動作確認済み PC 一覧. . . . . . . . . . . . . . . . . . . . . . . . . . proj-gp6x760/doc/TB-FMCL-USB30 Checked PC information 1.00.pdf• TB-FMCL-USB30 ハードユーザマニュアル. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-gp6x760/doc/TB-FMCL-USB30 HWUserManual 1.00.pdf• TB-FMCL-USB30 回路図. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-gp6x760/doc/TB-FMCL-USB30 Schematic 1.09.pdf• TB-FMCL-USB30 スタートアップガイド. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-gp6x760/doc/TB-FMCL-USB30 StartupGuide 1.00.pdf• uSD CONF ユーザーズガイド. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-gp6x760/doc/uSD CONF UserManuarl V6LSI 2.00.pdf

C.2

EMAX2 documents/sources• EMAX2 アイデア履歴 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/doc/IDEA*• EMAX2 基本特許 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/doc/pat33.tgz• EMAX2 科研基盤 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/doc/kaken2012.tgz

EMAX2 ARCHITECTURE HANDBOOKY.Nakashima Proprietary & Confidential

C.3. EMAX2 TOOLCHAINS

50• Autovectorization in GCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/doc/vectorization.pdf• gcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/src/gcc-4.4.6.tgz• gmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/src/gmp-4.3.2.tgz• mpfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/src/mpfr-3.0.1.tgz• EMAX2 ディレクティブ解析 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/src/conv-a2i/*• binutils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/src/binutils-2.21.tgz• EMAX2 RTL シミュレータ（xsim 部分） . . . . . . . . . . . . proj-emax/src/xsim/emax2.*,soft monitor.c• EMAX2 性能・電力評価 RTL シミュレータ（filter 部分） . . . . . . . . . . . . . .proj-emax/sample/filter/*• GP6X760-EMAX2 FreeBSD 用ドライバ . . . . . . . . . . . . . . . . . . proj-emax/src/xsim/GP6X760-Driver.c• GP6X760-EMAX2 FreeBSD 用ユーザ関数およびヘッダ . . . . . . . . . . . proj-emax/src/xsim/gp6x760.c• GP6X760-EMAX2 簡易試験ツール . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/src/xsim/gp6x760-test.c

C.3

EMAX2 toolchains• EMAX2 FORTRAN コンパイラ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/bin/gfortran• EMAX2 C プリプロセッサ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/bin/cpp• EMAX2 C コンパイラ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/bin/gcc• EMAX2 ライブラリ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/lib/*• EMAX2 ディレクティブ解析 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/src/conv-a2i/conv-a2i• EMAX2 アセンブラ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/bin/as• EMAX2 リンカ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/bin/ld• EMAX2 逆アセンブラ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/bin/objdump• EMAX2 性能・電力評価 RTL シミュレータ（filter） . . . . proj-emax/sample/filter/frontend-emax2• EMAX2 Intel 比較用バイナリ（filter） . . . . . . . . . . . . . . . . . . . . . proj-emax/sample/filter/frontend-sse• GP6X760-EMAX2 Verilog 雛型 . . . . . . . . . . . . . . . . . . . . . . . . . . . . proj-emax/fpga/step4000-GP6X-4way• GP6X760-EMAX2 コンフィグレーションツール . . . . . . . . . . . . . proj-emax/src/xsim/Config-gp6x760

Y.Nakashima Proprietary & Confidential

EMAX2 ARCHITECTURE HANDBOOK