Benefits and Costs ofOverstress Testing(HALT)
Nahum Meadowsong & Edmond L. Kyser
Cisco Systems, Inc.

The partnership of Design and Manufacturing is central to the process of bringing
a product to market. The impact of problems in either of these stages can increase
exponentially if they go unnoticed until after the product reaches the customer.
Overstress Test (tests using stresses beyond the design limit of the product) is successfulat uncovering such faults in both product design and the manufacturing process andinsures the overall robustness of the product. The benefits of Overstress Test include:
•••••
•
••

Rapid design and process maturation
Reduced total engineering time and cost
Reduced production and warranty costs
Earlier and mature product introduction (yields stabilized)
Higher MTBF
Greatly reduced manufacturing screening costs
Faster corrective action for design and process problems
Delighted Customers

HALT
HALT is a ‘step-stress to fail’ destruct test which gradually increases the environmental
stresses to determine the operational limits and to find any design faults. The process is
one of test, fail, and corrective action to prevent possible field failures. HALT is not acompliance test, and is not limited by component or product specifications. All products
are candidates for HALT. In the case of systems, the HALT test will find defects in theweakest subsystem. Production should be delayed until HALT results are satisfactory.
HASS testing, which is a non-destructive Manufacturing screen or process, will bediscussed in a following article.
HALT Stress Overview
The following stresses are capable, both alone and in corporation, of identifying productweaknesses. When available, each of these stresses should be used in HALT test design.

• Temperature
Operation under prolonged elevated temperatures can uncover marginal design, badcomponents, or process problems inherent in the product. Temperature cycling
detects weak solder joints, IC package integrity, TCE mismatch, and PCB processing
and mounting problems; problems that will show up over time once a product is in
the field.
• Vibration
Vibration is useful for testing a product’s robustness during shipping and poor solder
conditions. Cold / Insufficient solder connections can be stressed to failure withvibration levels which will not harm good connections.
• Voltage Margining
Voltage margining can be useful in the identification of marginal components andmarginal design, especially when used in conjunction with temperature.
• Frequency Margining
Frequency margining is not always an option but if the circuit under test allows for it,
it can be useful in identifying marginal components.
• Functional Stresses
The most abstract and sophisticated aspect of HALT test design is the functional testof the product. The goal is to have the product endure the combination ofenvironmental and electrical stress while operating at peak processor utilization,
bandwidth etc. Functional test should simulate this ‘worse-case real world’ as
accurately as possible to insure that no product functionality goes untested.

HALT Profile
There exists no industry standard HALT profile. The HALT profile should be tailored tothe needs of the specific program. Our experience with testing telecommunications
products at Cisco has lead to the design of the following three phase profile.
•Hot Step: Two hours at each temperature step; one hour high voltage margin,
one hour low voltage margin. Power Cycle after each temperature step. First stepis 60°C and last meaningful step is 90°C (The temperature may continue to be
stepped however failures become less and less meaningful after a certaintemperature. The point of diminishing returns is around 90°C).

HALT Hot Step

Chamber Temp
Vol tage Mar gi n100

17.5

15PWR

PWR

PWR

PWR

ON

CYCLE

CYCLE

CYCLE

80

12.5

70

10

60

7.5

50

5

40

2.5

30

0

20

-2.5

10-50% Voltage Margin

Temperature (C)90-7.5
00.5

11.5

22.5

3

3.5

4

4.5

5

5.5

66.5

77.5

8Test Time (hrs.)•Cold Step: Similar to hot step. First step is at -10°C and last meaningful step is 40°C.

HALT Cold StepChamber Temp
Vol tage Mar gi n7.54052.5300- 2.520- 10Test Time (hrs.)

0- 12.5- 15Margin- 7.5% Voltage

Temperature (C)-510- 17.5- 10- 20- 22.5-20- 25- 27.5

-30
PWR
ON-40PWR
CYCLE

PWR
CYCLE

PWR
CYCLE

- 30
- 32.5- 35-50•- 37.5Vibration: Vibration is stepped 5 Grms/hr until the maximum capabilities of thevibration table are reached. For the Qualmark OVS4 chambers we use this valueis 60 Grms. Accelerometers should be used in order to determine the amount ofvibration incident on the UUT. Generally, and especially when the UUT is part ofa larger system, only a fraction of the table vibration is transmitted to the testsubject.

HALT Vibration Step

7060

50

4030PWR
ON
20

1000

12

345678910

1112Test Time (hrs)

Determinants of HALT Success
For a HALT test to be successful the closed loop corrective action process must befollowed. If failure analysis is not carried through to root cause, the benefits of HALT
are lost. To be effective, results must be:•••

Fed back to design to make a circuit design change, select a different supplier, orimprove the existing suppliers process.
Fed back to manufacturing for a process change.
Used to determine the production test profile.

Another key for success is the intimate involvement by members of several key areas.
These include:••

Management – Management must allocate sufficient resources, time, and funds
for HALT testing to take place. They must also provide support during the failure
analysis phase in order to get closed loop corrective action in a timely fashion.
Development / Engineering – Design Engineering needs to be immediately
available to troubleshoot failures which can sometimes be beyond the scope of theHALT Test Engineers.

•Suppliers – Suppliers must be willing and able to provide component failure
analysis in order to obtain root cause.

Other key factors to success include the placement of HALT in the product development
timeline, sample size, the perceived relevance of failures, and failure reporting. A HALTtest should begin as soon as HW and SW is available and stable. The testing should use
as many units as possible, as the probability of uncovering a defect increases with sample
size. Failures that occur during testing should be treated as relevant and pursued to root
cause. Finally, failure reporting must be visible enough to prevent the failures andsolutions gleaned from HALT from being overlooked.

MTBR Prediction Using HALT Margin
Can HALT be used to predict a product’s MTBR? If so, then we are in a good position toestimate the benefits of HALT – and thus also the cost effectiveness of HALT.
The data that follows was collected from multiple HALT tests of similar Cisco
telecommunications products. Accurate data collection for MTBR and RMA requiresthat this quality data be tracked for a year past the completion of the HALT testing. The
following chart shows the correlation between MTBR (the actual field performance of theproduct) and HALT margin. In this data, the HALT margin is the smallest margin indegrees C between operating specifications and any HALT failure. Vibration failures are
not considered.
HALT Margin vs. Normalized MTBR

Normalized MTBR

1.00.8y = 0.0131x + 0.0876

0.60.40.20.001020304050

HALT MARGIN (°C)

Here the correlation is strong and intuitive. MTBR can be predicted based on thefollowing least squares fit:

60

MTBR = ((0.0131)(HM) + (.0876))*(NF)
where• HM = Halt Margin for product• NF = Normalization Factor used for the above chart

Economic Justification for HALT
Having obtained the relationship between HALT margin and MTBR, we are able toassess the cost effectiveness of HALT. For HALT to be cost effective the cost must be
less than the anticipated benefits. HALT requires destruction of at least one prototype ata critical stage, and prototype build is a leading cost item in product development. Also,
there are other costs such as the manpower required to conduct HALT, the depreciationof test equipment, consumable costs, and corrective action costs. The cost justification
model for HALT follows.

Cost Justification: Improve Reliability
From the above graph of RMA rate vs. HALT margin, if the operating margin isincreased n °C, the normalized RMA rate is reduced 0.0192 n. Also, each RMA costs
approximately WPC dollars, where WPC is the cost of producing the board (wholeproduct cost). The benefit of a HALT test is:
Benefit = (# of RMAs prevented)(cost of an RMA)
= N(0.0192)(RMA intercept)(Pvol)(WPC)$
where• Pvol is the annual production volume.

The cost of a HALT test is:
Cost = (WPC + Esalary + DEP + CON + CA)$
where
• Esalary = fully burdened weekly salary• DEP= Weekly Depreciation of equipment• COM = Consumable costs• CA= Corrective action costs

The break-even point is where costs equal benefits. For a HALT test to be cost effective,it must, on average, increase the operating margin n °C. Setting costs equal to benefits
we can solve for the margin n necessary to justify the cost of HALT.
n = (WPC + Esalary + DEP + CON + CA)/[(0.0192)(RMA intercept)(Pvol)(WPC)]

Additional potential HALT benefits
A HALT test is not a highly accelerated life test. In fact, it is not a life test at all. Thereis no appropriate acceleration algorithm or acceleration factor. The deliverables of aHALT test are operating margin and failure modes. However, operating margin is anindicator of field performance. Low margins indicate poor performance (short life) andhigh margins indicate good performance (long life). A HALT program with few tests
under it’s belt does not have the data necessary to correlate HALT performance to fieldperformance. That is not to say that a correlation does not exist – quite the contrary. A
seasoned HALT program which has conducted multiple tests on similar products could
possibly predict MTBR more accurately than current predictors in use such as those
based on component count and individual component field data. This may be because
current predictors do not factor in any aspects of the actual product design into theircalculations whereas HALT margin is specific to the product under test.
Consider the following comparison of RDT using traditional methods and RMA aspredicted by HALT margin.

This chart shows the required test time for an 80% confidence level in an MTBF
prediction greater than 75000 hours. The dashed blue line shows that RDT requires 40boards tested for 10 weeks (assuming 1 failure and Arrhenius acceleration due to 50°C
test temperature). RDT is a very time consuming test and requires equipment and laborthat would otherwise be used for production.
The same prediction using HALT margin requires as little as 1 board for 1 week. In thefollowing chart showing RMA rate vs. HALT margin the dashed blue line shows an 80%
confidence for an operating margin of 30°C indicating normalized RMA rate below 0.55.

The traditional MTBF predictor may be improved by factoring HALT margin into theMTBF calculation. This will be the subject of a paper soon to be published.

Conclusions
In this paper we have shown the benefits obtained from a well designed HALT program:•••

HALT process is adept at finding and correcting design faults and determining
design margins
The costs of HALT can be justified in terms of improved margin
HALT margin may also be used to estimate MTBR (and thus obviate traditionalRDT) and to improve traditional MTBF prediction

Acronyms
AST-(Accelerated Stress Test) - Overstress Test

HALT HASS HW ICMTBF MTBR ORT PCB RDT RMA SW TCE UUT -Highly Accelerated Life Test
Highly Accelerated Stress Screen
HardwareIntegrated Circuit(predicted) Mean Time Between Failures
Mean Time Between Returns
Ongoing Reliability Testing
Printed Circuit Board
Reliability Determination Test
Return Material Authorization
SoftwareTemperature Coefficient of Expansion
Unit Under Test

Acknowledgments
The test data serving as the basis for this paper was obtained at the Cisco HALTLaboratory, San Jose, CA. For this data, we are indebted to the efforts of Todd Broome,Hung La, Sheryl Spake, and Ken Miu. Field data was obtained with the help of Henry
Bertram of the Cisco Quality organization. The QualMark Corporation has been
supportive and helpful throughout our 4 year history of HALT at Cisco.

References[1] Edmond L. Kyser and Nahum Meadowsong, ‘Economic Justification of HALT Tests:
The Relationship Between Operating Margin, Test Costs, and The Costs of Field
Returns’, Proc. IEEE/CPMT Workshop on AST 2002
[2] Eugene R. Hnatek and Edmond L. Kyser, ‘Straight Talk About Accelerated StessTesting (HALT and ESS) – Lessons Learned’, Proc. Future Circuits Intlernational 2000
[3] Mike Silverman, ‘Why HALT Cannot Produce A Meaningful MTBF Number And
Why This Should Not Be A Concern’, QualMark Corporation, Santa Clara ARTC
Division (available on the QualMark website,
http://qualmark.com/content/OurLibrary_CaseStudies.html.