WIZ812MJ Datasheet(Ver. 1.1)

© 2008 WIZnet Inc. All Rights Reserved.
For more information, visit our website at www.wiznet.co.kr

WIZ812MJ Datasheet

Document History Information
RevisionVer. 1.0
Ver. 1.1

Data
September 17, 2008
January 28, 2009

Description
Release with WIZ812MJ Launching
Added temperature specification

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WIZ812MJ Datasheet

WIZnet’s Online Technical Support
If you have something to ask about WIZnet Products, Write down your question
on Q&A Board in WIZnet website (www.wiznet.co.kr). WIZnet Engineer will give ananswer as soon as possible.

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WIZ812MJ Datasheet

Table of Contents

1.

Introduction .............................................................................. 5
4
1.1.
1.2.
1.3.

2.

Pin Assignments & descriptions ................................................... 7
2.1.
2.2.
2.3.
2.4.

3.

Features ............................................................................. 5
Block Diagram ...................................................................... 5
Difference between WIZ811MJ and WIZ812MJ .............................. 6Pin Assignments ................................................................... 7
Power & Ground ................................................................... 8
MCU Interfaces ..................................................................... 8
Miscellaneous Signals ............................................................ 9

Timing Diagrams ..................................................................... 103.1.
3.2.
3.3.
3.4.

Reset Timing .................................................................... 10Register/Memory READ Timing ............................................... 10Register/Memory WRITE Timing .............................................. 11
SPI Timing......................................................................... 114.

Dimensions ............................................................................. 12

5.

Schematic .............................................................................. 13

6.

Partlist ................................................................................... 14© Copyright 2008 WIZnet Inc. All rights reserved

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WIZ812MJ Datasheet

1. Introduction
WIZ812MJ is the network module that includes W5100 (TCP/IP hardwired chip, include PHY),
MAG-JACK (RJ45 with X’FMR) with other glue logics. It can be used as a component and noeffort is required to interface W5100 and Transformer. The WIZ812MJ is an ideal option for users
who want to develop their Internet enabling systems rapidly.
For the detailed information on implementation of Hardware TCP/IP, refer to the W5100
Datasheet.
WIZ812MJ consists of W5100 and MAG-JACK.
 TCP/IP, MAC protocol layer: W5100
 Physical layer: Included in W5100
 Connector: MAG-JACK(RJ45 with Transformer)

1.1. Features

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

Supports 10/100 Base TX
Supports half/full duplex operation
Supports auto-negotiation and auto cross-over detection
IEEE 802.3/802.3u Compliance
Operates 3.3V with 5V I/O signal tolerance
Supports network status indicator LEDs
Includes Hardware Internet protocols: TCP, IP Ver.4, UDP, ICMP, ARP, PPPoE, IGMP
Includes Hardware Ethernet protocols: DLC, MAC
Supports 4 independent connections simultaneously
Supports MCU bus Interface and SPI Interface
Supports Direct/Indirect mode bus access
Supports Socket API for easy application programming
Interfaces with two 2.54mm pitch 2 x 10 header pin
Temperature : 0 ~ 70℃ (Operation), -40 ~ 85℃ (Storage)

1.2. Block Diagram© Copyright 2008 WIZnet Inc. All rights reserved

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1.3. Difference between WIZ811MJ and WIZ812MJ
WIZ811MJ

WIZ812MJ

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Two 2.54mm pitch 10x2 header

The same pin-header is mounted
but pin description is different
J2:9
GND -> RX_LED
J2:10 GND -> TX_LED
J2:19 GND -> /LINKLED

Two PCB Through Hole(Ø 3.00mm)

Four PCB Through Hole(Ø 3.00mm)

55.5 x 25 x 23.5mm (W x H x D)

The same size

LINKLED : Active low in link state indicates agood status for 10/100M.
It is always ON when the link is OK and it flashes
while in a TX or RX state.

/LINKLED : Active low in link state indicates agood status for 10/100M.
It is always ON when the link is OK.
It does not flashes while in a TX or RX state.
ACT_LED : Active low in active state indicates agood status for 10/100M.
It is always ON when the link is OK and it flashes
while in a TX or RX state.

© Copyright 2008 WIZnet Inc. All rights reserved

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2. Pin Assignments & descriptions
2.1.

Pin Assignments

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WIZ812MJ Datasheet

I : Input
I/O : Bi-directional Input and output

O : Output
P : Power

2.2. Power & GroundSymbol

TypePin No.

Description

3V3DP

J1:12 ,

J2:1

Power : 3.3 V power supply

GND

P

J1:11,

J2:20

Ground8TOP

2.3. MCU Interfaces
SymbolSCLK

TypeIPin No.

Description

J2:3

SCLK(Serial Clock)This pin is used to SPI Clock Signal pin.

/SCSI

J2:4/SCS (Slave Select) *This pin is used to SPI Slave Select signal Pin.
This pin controls SPI_EN signal of W5100. When/SCS signal assert low, W5100 drive SPI mode by
SPI_EN signal toggled high.

MOSII

J1:1

MOSI (Master Out Slave In) *This pin is used to SPI MOSI signal pin.

MISO

I/O

J1:2

MISO (Master In Slave Out) *This pin is used to SPI MISO signal pin.

A14~A8I

A7~A0I

J2:11 ~ J2:18

Address
Used as Address[7-0] pin

D7~D0I/O

J1:3 ~ J1:10

Data
8 bit-wide data bus

/CSI

J2:7

Module Select : Active low.
/CS of W5100

/RDI

J2:6

Read Enable : Active low.
/RD of W5100

/WRI

J2:5

Write Enable : Active low/WR of W5100

J2:8Interrupt : Active low
After reception or transmission it indicates that theW5100 requires MCU attention.
By writing values to the Interrupt Status Registerof W5100 the interrupt will be cleared.
All interrupts can be masked by writing values tothe IMR of W5100 (Interrupt Mask Register).
For more details refer to the W5100 Datasheet/INTO

J1:13 ~ J1:19© Copyright 2008 WIZnet Inc. All rights reserved

Address
Used as Address[14-8] pin

WIZ810MJ
DatasheetWIZ812MJ Datasheet

2.4. Miscellaneous Signals
SymbolTypePin No.

Description/RESET

I

J2:2

Reset : This pin is active low input toinitialize or re-initialize W5100.
By asserting this pin low for at least 2us,
all internal registers will be re-initialized
to their default states.

RX_LEDO

J2:9

RX_LED : Receive activity LED
Active low indicates the presence ofreceiving activity.

TX_LEDO

J2:10

TX_LED : Transmit activity LED
Active low indicates the presence oftransmitting activity.

/LINKLEDOJ2:19LINKLED : Active low in link state
indicates a good status for 10/100M.
It is always ON when the link is OK.
It does not flashes while in a TX or RXstate.

NC-J1 : 20Not Connect© Copyright 2008 WIZnet Inc. All rights reserved

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3. Timing Diagrams
WIZ812MJ provides following interfaces of W5100.
-. Direct/Indirect mode bus access-. SPI access

Reset Timing

3.1.

10TOP12

3.2.

Description
Reset Cycle Time/RESET to internal PLOCK

Min2 us-Max
10 ms

Register/Memory READ Timing123456

Description
Read Cycle Time
Valid Address to /CS low time
/CS low to /RD low time
/RD high to /CS high time
/RD low to Valid Data Output time
/RD high to Data High-Z Output time

© Copyright 2008 WIZnet Inc. All rights reserved

Min
80 ns
8 ns
-Max
1 ns
1 ns
80 ns
1 ns

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WIZ812MJ Datasheet

3.3.

Register/Memory WRITE Timing

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123456

3.4.

123456

Description
Write Cycle Time
Valid Address to /CS low time
/CS low to /WR high time
/CS low to /WR low time
/WR high to /CS high time
/WR low to Valid Data time

Min70 ns
7 ns
70 ns-Max
1 ns
1 ns
14 ns

Min
21 ns
7 ns
28 ns
7 ns
21 ns
70 ns

Max
14 ns
-

SPI Timing

Description/SS low to SCLK
Input setup time
Input hold time
Output setup time
Output hold time
SCLK time© Copyright 2008 WIZnet Inc. All rights reserved

Mode
Slave
Slave
Slave
Slave
Slave
Slave

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4. Dimensions

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Datasheet

Symbols

Dimensions (mm)AB
CDEFGH
IJKL
M
N

25.00
22.86
17.00
3.00
4.00
52.00
3.20
33.02
9.00
2.54
2.54
15.90
13.50
6.00

© Copyright 2008 WIZnet Inc. All rights reserved

WIZ812MJ Datasheet

5. Schematic

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WIZ812MJ Datasheet

6. Partlist
Item
1Q.ty
2

2

14

3
4
5

2
1
1

Reference
C1,C2
C3,C4,C5,C6,
C10,C12,C13,C14,C15,16,
C17,C18,C19,C20
C7,C11C8C96

2

FB2,FB172

J1,J28910111213141516171819201421111111111R1
R2,R3,R8,R9
R4,R5
R6R7R11U1U2U4U5U6U7Y1211Part
27pF

Tech. Characteristics
50V-20% Ceramic

Package
CASE 0603

0.1uF

50V-20% Ceramic

CASE 0603

4.7uF/16V
1uF/16V
0.01uF
1uH
Chip
FerriteInductor
2X10 20PIN 2.54mm
DIP STRAIGHT Header
1M
51 1%
200
12K (1%)300 (1%)
4.7K
W5100
RJ113BZ
SN74LVC2G14DCK
SN74LVC1G79DCK
SN74LVC1G32DCK
SN74LVC2G08DCT
25MHz (SMD)
WIZ812MJ REV1.0 1.6T
4LAYER

16Vmin 10%
16Vmin 10%
50V-20% Ceramic

EIA/IECQ 3216
EIA/IECQ 3216
CASE 0603

1uH, 50mA

CASE 0805© Copyright 2008 WIZnet Inc. All rights reserved

2 X 10 2.54mm pitch
1/10W-5% SMD
1/10W-1% SMD
1/10W-5% SMD
1/10W-1% SMD
1/10W-1% SMD
1/10W-5% SMD
WIZnet Hardware TCP/IP
Transformer + RJ45
Dual Inverting Buffer (vendor : TI)
D-type Flip Flop (vendor : TI)
OR-Gate (vendor : TI)
Dual AND-Gate (vendor : TI)
SMD Type
PRINTED CIRCUIT BOARD

CASE 0603
CASE 0603
CASE 0603
CASE 0603
CASE 0603
CASE 0603
LQFP80SC70-6
SC70-5
SC70-5
SM8
SX-1

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