INTEGRATED CIRCUITSERRATA SHEET
Date:
Document Release:
Device Affected:

2007 September 21
Version 1.5
LPC2378

This errata sheet describes both the functional deviations and any deviations from the electrical specifications
known at the release date of this document.
Each deviation is assigned a number and its history is tracked in a table at the end of the document.

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LPC2378 Erratasheet

Document revision history
RevDate

1.5

September 21 2007

1.4

August 7 2007

1.3

July 20 2007

1.2

June 7 2006

1.1

March 22 2007

1.0November 14 2006

2007 September 21Description
1. Added Rev B
2. Removed Rev A from ESD.1. ESD.1 does not appear in
Rev A. It was accidentally listed in version 1.4
1. Re-added EMC.1. While releasing version 1.3, EMC.1
was accidentally deleted
1. Added Ethernet.3
2. Added Deep Power Down Mode.1
3. Updated Flash.1
4. Updated Ethernet.1
1. Added Rev A
2. Added Flash.1, MAM.1 and CAN.1
1. Corrected the value of M in PLL.1
2. Updated ESD.1
3. Added core.1
First version

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LPC2378 Erratasheet

Identification
The typical LPC2378 devices have the following top-side marking:
LPC2378xxx
xxxxxxx
xxYYWW R[x]The last/second to last letter in the third line (field ‘R’) will identify the device revision. This Errata Sheet covers thefollowing revisions of the LPC2378:

Revision Identifier (R)
‘-’
‘A’
‘B’

Comment
Initial device revision
Second device revision
Third device revision

Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured
during that year.

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LPC2378 Erratasheet

Errata Overview - Functional Problems

FunctionalProblem
ADC.1
Ethernet.1
Ethernet.2
Ethernet.3
I2S.1
PLL.1
SRAM.1
USB.1
USB.2
USB.3
WDT.1
EMC.1
Core.1
Flash.1
MAM.1
CAN.1
Deep Power
Down.1

Short Description
ADDRx read conflicts with hardware setting of DONE bit
Setting up the Ethernet interface in RMII mode
Ethernet SRAM disabled
RxDescriptor number cannot be greater than 4
I2S DMA can stall
PLL output is limited to 290 MHz
16 kB SRAM can not be used for code executionUSB_NEED_CLK is always asserted
U1CONNECT is not functional
VBUS status input is not functional
Accessing non-Watchdog APB registers in the middle of the feed
sequence causes a reset
Write operation cannot be performed on the external memorybus
Incorrect update of the Abort Link register in Thumb state
Operating speed out of on-chip flash is restricted
Code execution failure can occur with MAM Mode 2
Data overrun condition can lock the CAN controller
Deep Power Down mode is not functional

Errata occurs indevice revision-, A, B-, A-, A-, A, B-, A, B

Errata Overview - AC/DC Deviations

AC/DC
Deviation
ESD.1

Short Description
2 kV ESD requirements are not met on the RTCX1 pin

Errata Notes

NoteNA

2007 September 21

Short Description
NA4

Errata occurs indevice revision-NXP Semiconductors

LPC2378 Erratasheet

Functional Deviations of LPC2378
ADC.1:ADDRx read conflicts with hardware setting of the DONE bit

Introduction:

The LPC2378 has a 10-bit ADC, which can be used to measure analog signals and convert thesignals into a 10-bit digital result. There are eight A/D channels and each channel has its own
individual A/D Data Register (ADDR0 to ADDR7). The A/D Data Register holds the result when an
A/D conversion is complete, and also includes the flags that indicate when a conversion has been
completed (DONE bit) and when a conversion overrunhas occurred. The DONE bit is cleared
when the respective A/D Data Register is read.

Problem:

If a software read of ADDRx conflicts with the hardware setting of the DONE bit in the same register (once a conversion is completed) then the DONE bit gets cleared automatically, thereby clearing
the indication that a conversion was completed.

Workarounds: For software controlled mode or burst mode with only one channel selected, the DONE bit in theA/D Global Data Register (located at 0xE003 4004) can be used instead of the individual ADDRx
result register with no impact on performance.
For burst mode with multiple channels selected, the DONE bit together with the CHN field in theA/D Global Data Register can be used with some impact on throughput.

Ethernet.1:

Setting up the Ethernet interface in RMII mode

Introduction:

The LPC2468 has an Ethernet interface, which can be interfaced with an off-chip PHY using theRMII interface.

Problem:

The default configuration of the device does not enable the RMII interface.

Workaround:To use the Ethernet interface in RMII mode write a 1 to bit 12 (P1.16) in PINSEL2 register (locatedat 0xE002 C008). This workaround only applies for Rev ‘-’ devices and does not apply for Rev ‘A’and newer devices. In order to have both Rev ‘-’ and other revisions coexist in the same piece ofsoftware, the MAC module ID can be used to identify the part and determine if port pin P1.6 needs
to be set or not.
Here are the steps (along with some sample code) to initialize the MAC based on the module ID:
1. In master header file lLPC24xx.h, make sure Module ID is defined (Please note, this ID register
is not documented in the User's Manual).
#define MAC_BASE_ADDR
0xFFE00000#define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR +0xFFC)) /* Module ID reg (RO) */2. In the beginning of the MAC initialization file, add below definition:#define OLD_EMAC_MODULE_ID((0x3902 << 16) | 0x2000)

3. In MAC initialization routine, right after setting the EMAC clock in the PCONP register, add a few
lines as below:/* Turn on the ethernet MAC clock in PCONP, bit 30 */regVal = PCONP;
regVal |= PCONP_EMAC_CLOCK;PCONP = regVal;

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LPC2378 Erratasheet/*-----------------------------------------------------* Write to PINSEL2/3 to select the PHY functions on P1[17:0]* P1.6, ENET-TX_CLK, has to be set for Rev '-' devices and it* must not be set for Rev 'A’ and newer devices*------------------------------------------------------*/
regVal = MAC_MODULEID;
if ( regVal == OLD_EMAC_MODULE_ID ){/* On Rev. '-', MAC_MODULEID should be equal to
OLD_EMAC_MODULE_ID, P1.6 should be set. */PINSEL2 = 0x50151105;/* selects P1[0,1,4,6,8,9,10,14,15] */}else{/* on rev. 'A', MAC_MODULEID should not equal to
OLD_EMAC_MODULE_ID, P1.6 should not be set. */PINSEL2 = 0x50150105;/* selects P1[0,1,4,8,9,10,14,15] */}PINSEL3 = 0x00000005;/* selects P1[17:16] */Ethernet.2:

Ethernet SRAM disabled

Introduction:

The LPC2378 has an Ethernet interface, which has a dedicated 16 kB SRAM.

Problem:

When the Ethernet block is disabled (in the PCONP register located at 0xE01F C0C4), the Ethernet
SRAM is also disabled.

Workaround:

Enable the Ethernet block by setting the PCENET bit (bit no 30) in the PCONP register. The
Ethernet SRAM is now enabled.

Ethernet.3

Receive Status registers will not function correctly if RxDescriptor number is greater than 4

Introduction:

The Receive number of Descriptors register (RxDescriptor-0xFFE0 0110) defines the number ofdescriptors in the Descriptor array. Each receive descriptor element in the Descriptor array has an
associated status field which consists of the HashCRC word and Status Information word.

Problem:

The status words are updated incorrectly if the number of Descriptors set in the Receive number of
Descriptors register is greater than or equal to 5.

Workaround:

Define 4 or less in the Receive number of Descriptors register.

I2S.1:

I2S DMA interface is non-operational

Introduction:

The LPC2378 has an I2S interface, which can be used for audio devices. The I2S interface wasinitially designed to operate with the general purpose DMA controller.

Problem:

The DMA controller cannot access the I2S interface.

Workaround:No known workaround.

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LPC2378 Erratasheet

PLL.1:PLL output (FCCO) is limited to 290 MHz

Introduction:

The PLL input, in the range of 32 KHz to 50 MHz, may initially be divided down by a value “N”, which
may be in the range of 1 to 256. Following the PLL input divider is the PLL multiplier. This canmultiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value“M”, in the range of 1 through 32768. The resulting frequency, FCCO must be in the range of275 MHz to 550 MHz.This frequency can be divided down (using the Clock Divider registers) to get
the desired clock frequencies for the core and peripherals.

Problem:

The maximum output of the CCO within the PLL block is limited to 290 MHz.

Workaround:

Care should be taken while programming the PLL so that Fcco resides in the desired range. Thesuggested setting is to use a 12 MHz external crystal. Use a PLLdivider (N) of 1 and PLL multiplier(M) of 12. Putting the values in the equation:
FCCO = (2 × M × FIN) / N
Fcco = 288 MHz
The CPU Clock Configuration register (located at 0xE01F C104) can then be used to divide thisfrequency by 4 to produce the maximum CPU speed of 72 MHz (except on Rev ‘-’ and Rev ‘A’, seeFlash.1).

SRAM.1:

16 kB SRAM cannot be used for code execution

Introduction:

The LPC2378 has 16 kB of SRAM on the AHB2 bus, which would generally be used by the Ethernetblock.

Problem:

The 16 kB of SRAM can only be used as data RAM. Code can not be executed from this memory.

Workaround:No known workaround.

USB.1:

USB_NEED_CLK is always asserted

Introduction:

The USB_NEED_CLK signal is used to facilitate going into and waking up from chip Power Down
mode. USB_NEED_CLK is asserted if any of the bits of the USBClkSt register are asserted.

Problem:

The USB_NEED_CLK bit of the USBIntSt register (located at 0xE01F C1C0) is always asserted,
preventing the chip from entering Power Down mode when the USBWAKE bit is set in theINTWAKE register (located at 0xE01F C144).

Workaround:

After setting the PCUSB bit in PCONP (located at 0xE01F C0C4), write 0x1 to address
0xFFE0C008. The USB_NEED_CLK signal will now function correctly. Writing to address
0xFFE0C008 only needs to be done once after each chip reset.

USB.2:

U1CONNECT signal is not functional

Introduction:

U1CONNECT Signal (alternate function of P2.9) is part of the SoftConnect USB feature, which isProblem:

used to switch an external 1.5 KΩ resistor under the software control.
The USB U1CONNECT alternate function does not work as expected.

Workaround:

Configure P2.9 as a GPIO pin, and use it to enable the pull-up resistor on the U1D+ pin.

USB.3:

VBUS status input is not functional

Introduction:

The VBUS signal indicates the presence of USB bus power.

Problem:

The VBUS status input is not functional.

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LPC2378 Erratasheet
Workaround:

Configure P1.30 as a GPIO pin, and poll it to determine when VBUS goes to 0, signalling a
disconnect event.

WDT.1:

Accessing non-Watchdog APB registers in the middle of the feed sequence causes a reset.

Introduction:

The Watchdog timer can reset the microcontroller within a reasonable amount of time if it entersan erroneous state.
After writing 0xAA to WDFEED, any APB register access other than writing 0x55 to WDFEED may
cause an immediate reset.

Problem:
Workaround:

Avoid APB accesses in the middle of the feed sequence. This implies that interrupts and theGPDMA should be disabled while feeding the Watchdog.

EMC.1:Introduction:
Problem:
Workarounds:

Write operation cannot be performed on the external memory bus
The External Memory Controller supports asynchronous static memory device support including
RAM, ROM, and Flash, with or without asynchronous page mode.
Write operation is not operational.
Using all the EMC pins as GPIO pins, the write operation can be simulated in software.

Core.1

Incorrect update of the Abort Link register in Thumb state

Introduction:

If the processor is in Thumb state and executing the code sequence STR, STMIA or PUSH followed
by a PC relative load, and the STR, STMIA or PUSH is aborted, the PC is saved to the abort linkregister.

Problem:In this situation the PC is saved to the abort link register in word resolution, instead of half-wordresolution.
Conditions:
The processor must be in Thumb state, and the following sequence must occur:<any instruction><STR, STMIA, PUSH> <---- data abort on this instruction
LDR rn, [pc,#offset]
In this case the PC is saved to the link register R14_abt in only word resolution, not half-wordresolution. The effect is that the link register holds an address that could be #2 less than it shouldbe, so any abort handler could return to one instruction earlier than intended.

Work around:

In a system that does not use Thumb state, there will be no problem.
In a system that uses Thumb state but does not use data aborts, or does not try to use data aborts
in a recoverable manner, there will be no problem.
Otherwise the workaround is to ensure that a STR, STMIA or PUSH cannot precede a PC-relativeload. One method for this is to add a NOP before any PC-relative load instruction. However this iswould have to be done manually.

Flash.1
Introduction:
Problem:

Operating speed out of on-chip Flash is restricted
The operating speed of this device out of internal Flash/ SRAM is specified at 72MHz.
Code execution from internal Flash is restricted depending upon the device revision:
1. Rev ‘A’ devices: Code execution from internal flash is restricted to a maximum of 60MHz.

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LPC2378 Erratasheet

Work around:MAM.1:
Introduction:

Problem:

Workaround:

CAN.1:
Introduction:

Problem:
Workaround:

For example, use a PLL output frequency of Fcco=360MHz and divide it by 6 (CCLKSEL=5) togenerate 60MHz CPU clock (Do not use even values for CCLKSEL).
2. Rev ‘-’ devices: Code execution from internal flash is restricted to a maximum of 60MHz also.
However, this device revision has one more restriction in terms of the PLL output frequency (FccoPlease refer to PLL.1 above). Fcco is limited to 290MHz.
Considering the same example in PLL.1 (Input crystal-12MHz, N=1, M =12): Fcco = 288 MHz
The CPU Clock Configuration register (located at 0xE01F C104) can then be used to divide thisfrequency by 6 (CCLKSEL=5) to achieve 48MHz. Since this register only accepts odd values for
CCLKSEL, a division by 5 (CCLKSEL=4) is not a valid option.
In both the above revisions, code can still execute out of SRAM at up to 72 MHz.
None.
Under certain conditions in MAM Mode 2 code execution out of internal Flash can fail.
The MAM block maximizes the performance of the ARM processor when it is running code inFlash memory. It includes three 128-bit buffers called the Prefetch Buffer, the Branch Trail Buffer
and the data buffer. It can operate in 3 modes; Mode 0 (MAM off), Mode 1 (MAM partially enabled)and Mode 2 (MAM fully enabled).
Under certain conditions when the MAM is fully enabled (Mode 2) code execution from internal
Flash can fail. The conditions under which the problem can occur is dependent on the code itself
along with its positioning within the Flash memory.
If the above problem is encountered then Mode 2 should not be used. Instead, partially enable theMAM using Mode 1.
Data Overrun condition can lock the CAN controller
Each CAN controller provides a double Receive Buffer (RBX) per CAN channel to store incoming
messages until they are processed by the CPU. Software task should read and save received data
as soon as a message reception is signaled.
In cases, where both receive buffers are filled and the contents are not read before the third message comes in, a CAN Data Overrun situation is signaled. This condition is signaled via the Status
register and the Data Overrun Interrupt (if enabled).
In a Data Overrun condition, the CAN controller is locked from further message reception.
1. Recovering from this situation is only possible with a soft reset to the CAN controller.
2. If software cannot read all messages in time before a third message comes in, it is recommend
to change the acceptance filtering by adding further acceptance filter group(s) for messages,
which are normally rejected. With this approach, the third incoming message is accepted and theData Overrun condition is avoided. These additional messages are received with the corresponding group index number can be easily identified and rejected by software.

Deep Power Down Mode.1:
Deep Power Down mode is not functionalIntroduction:
Deep Power Down mode is like Power Down mode, but the on-chip regulator that supplies
power to internal logic is also shut off. This produces the lowest possible power
consumption without actually removing power from the entire chip.
Problem:

The power consumption in Deep Power Down mode does not meet the specifications.

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LPC2378 Erratasheet
Workaround:

None.

Electrical and Timing Specification Deviations of LPC2378
ESD.1:The LPC2378 does not meet the 2 kV ESD requirements on the RTCX1 pin

Introduction:

The LPC2378 is rated for 2 kV ESD.The RTCX1 pin is the input pin for the RTC oscillator circuit.

Problem:

The LPC2378 does not meet the required 2 kV ESD specified.

Workarounds: Observe proper ESD handling precautions for the RTCX1 pin.

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LPC2378 Erratasheet
Errata Notes
No known Errata Notes

2007 September 2111