LTC2947
30A Power/Energy Monitor
with Integrated Sense Resistor
Features

Description

Measures Current, Voltage, Power, Charge, Energy
nn ±30A Current Range with Low 9mA Offset
nn Integrated 300µΩ Sense Resistor
nn 0V to 15V Input Range Independent of Supply Voltage
nn Instantaneous Multiplication of Voltage and Current
nn 0.5% Voltage Accuracy
nn 1% Current and Charge Accuracy
nn 1.2% Power and Energy Accuracy
nn Alerts When Thresholds Exceeded
nn Stores Maximum and Minimum Values
nn Shutdown Mode with I < 10μA
Q
nn I2C/SPI Compatible Interface
nn Available in 32-Lead 4mm × 6mm QFN Package

The LTC®2947 is a high precision power and energy monitor with an internal sense resistor supporting up to ±30A.
Three internal No Latency Δ∑™ ADCs ensure accurate
measurement of voltage and current, while high-bandwidth
analog multiplication of voltage and current provides accurate power measurement in a wide range of applications.
Internal or external clocking options enable precise chargeand energy measurements.

Applications

All measured quantities are stored in internal registers accessible via the selectable I2C/SPI interface. The LTC2947
features programmable high and low thresholds for all
measured quantities to reduce digital traffic with the host.

nnServers
Telecom Infrastructure
nn Industrial
nn Electric Vehicles
nn Photovoltaicsnn
nn

An internal 300µΩ, temperature-compensated sense
resistor minimizes efficiency loss and external components, simplifying energy measurement applications while
enabling high accuracy current measurement over the fulltemperature range.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and No
Latency ∆∑ and QuikEval are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents, including 8907703,
8841962.

Typical Application
300µΩ

IP

0V TO 15V
–30A TO 30A

Energy Measurement Total Unadjusted
Error vs Current, VP – VM = 12V

IM

0.5
1µF

1µF

1µF
1µF

AVCC
AGND
DVCC

LTC2947
VM

CFP

OVDD
SCL
SDI
SDO
ALERT

CFM
BYP
AD1
AD0
CLKI

0.3

LOAD

DGND

INTERNAL CLOCK
EXTERNAL CLOCK

0.4

VP

5V
SDI
SDA

0.2
TUE (%)5V

I2C
INTERFACE

0.1
0.0
–0.1
–0.2
–0.3
–0.4

CLKO

–0.5

0

10

20
ISENSE (A)302947 TA01b

2947 TA01a

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LTC2947
Table of Contents
Description......................................................................................................................... 1
Absolute Maximum Ratings...................................................................................................... 3
Order Information.................................................................................................................. 3
Pin Configuration.................................................................................................................. 3
Electrical Characteristics......................................................................................................... 4
Timing Diagrams.................................................................................................................. 7
Typical Performance Characteristics........................................................................................... 8
Pin Functions......................................................................................................................10
Block Diagram.....................................................................................................................11
Operation..........................................................................................................................12
Overview................................................................................................................................................................ 12
Modes of Operation............................................................................................................................................... 12
Current, Voltage and Temperature Measurement................................................................................................... 14Power Measurement.............................................................................................................................................. 14
Charge, Energy Measurement and Accumulated Time .......................................................................................... 14
Applications Information........................................................................................................15
TimeBase: Internal/External Clock/Crystal............................................................................................................ 15
Configuring the GPIO Pin....................................................................................................................................... 15
Internal Sense Resistor.......................................................................................................................................... 16
Current and Voltage Input Filtering........................................................................................................................ 16
Layout Considerations........................................................................................................................................... 17
Digital Interface...................................................................................................................19
Selecting SPI or I2C Serial Interface...................................................................................................................... 19
SPI Mode .............................................................................................................................................................. 19
I2C Mode .............................................................................................................................................................. 22
Register Map......................................................................................................................25
Register Description.............................................................................................................26
Register Naming Conventions............................................................................................................................... 26
Paging Mechanism................................................................................................................................................ 26
PAGE Control......................................................................................................................................................... 26
Operation Control.................................................................................................................................................. 26
Register Map PAGE0.............................................................................................................................................. 27
Register Map PAGE1.............................................................................................................................................. 38
Typical Applications..............................................................................................................40
Package Description.............................................................................................................42
Revision History..................................................................................................................43
Typical Application...............................................................................................................44
Related Parts......................................................................................................................4422947faFor more information www.linear.com/LTC2947

LTC2947
Absolute Maximum Ratings

Pin Configuration(Notes 1, 2)
VP

VM

CFP

CFM

CLKI

CLKO

TOP VIEW

32 31 30 29 28 27
IM 1

26 IP

IM 2

25 IP

IM 3

24 IP

33

IM 4

23 IP

IM 5

22 IP

IM 6

21 IP

AGND 7

20 AVCC

DGND 819 DNC

34
DGND

AD0 9

18 DVCC
17 BYP

AD1/CS 10

OVDD

SDI

SDO

SCL

GPIO

11 12 13 14 15 16
ALERT

Supply Pins:
AVCC to AGND Voltage........................... –0.3V to 20V
DVCC to DGND Voltage........................... –0.3V to 20V
DGND to AGND Voltage.......................... –0.1V to 0.1V
Digital Input/Output Pins:
OVDD to DGND Voltage......................... –0.3V to 5.5V
SCL, SDI, SDO, GPIO, ALERT, AD1,
AD0 to DGND Voltage..........................–0.3V to VOVDD
CLKI to DGND Voltage........................... –0.3V to 5.5V
Analog Pins
VP, VM to AGND Voltage......................... –0.3V to 20V
VP to VM Voltage.................................... –0.3V to 20V
IP, IM Total Current (for 1ms)................... –50A to 50A
IP, IM Total Current (Note 6).................... –36A to 36A
IP, IM Current Per Pin (for 1ms)............. –8.3A to 8.3A
IP, IM Current Per Pin (Note 6).................... –6A to 6A
CFP, CFM, BYP, CLKO..................................... (Note 3)
Operating Ambient Temperature Range
LTC2947I................................................ –40° to 85°C
Storage Temperature Range..................... –65° to 150°C

UFE PACKAGE
VARIATION: UFE32MA
32-LEAD PLASTIC QFN (4mm × 6mm)
TJMAX = 125°C, θJA = 50°C/W
EXPOSED PAD (PIN 33); DO NOT CONNECTEXPOSED PAD (PIN 34) IS DGND, MAY BE CONNECTED TO DGND OR LEFT FLOATING

Order Information http://www.linear.com/product/LTC2947#orderinfo
TUBE

TAPE AND REELPART MARKING*PACKAGE DESCRIPTIONTEMPERATURE RANGE

LTC2947IUFE#PBF

LTC2947IUFE#TRPBF

2947

32-Lead (4mm × 6mm) Plastic QFN–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

2947faFor more information www.linear.com/LTC2947

3

LTC2947
Electrical Characteristics

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOLPARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

Power Supply
VAVCC, VDVCC Supply Voltage

l

4.5

15

V

l

1.8

5.5

V

4.5

V

3
0.2
0.3
0.3

3.5
0.3
0.5
1

mA
mA
μA
µA

6
6
7
7

8
8
9.5
90

mA
mA
μA
µA

VOVDD

Supply Voltage of Digital Interface

VUVLO

VAVCC, VDVCC Undervoltage Lockout
Threshold

VAVCC, VDVCC Falling

l

IAVCC

Supply Current Analog Section

Continuous Mode
Idle Mode
Shutdown Mode
Shutdown Mode

l
l

IDVCC

Supply Current Digital Section

Continuous Mode
Idle Mode
Shutdown Mode
Shutdown ModellDelay of VAVCC,DVCC to VOVDD at
Power-Up

VOVDD, VAVCC, VDVCC ≥ 0.9 • VOVDDfinal(Note 8)l0ns(Note 5)

l

15

Bit

l

l

Current Sense (IP, IM) ADC
Resolution (No Missing Codes)
ISENSE

Input Current Through IP and IM(Note 6)l

RSENSEInternal Sense Resistor(Note 7)lSense Resistor Voltage

Current through IP and IM = 30A

Common Mode Input Voltage Range
LSBI

140

300

l

–0.1

Current Sense Quantization Step

mV
15.5

3

INLI

Current Integral Nonlinearity(Note 6)

TUEI

Total Unadjusted Error|I| ≥ 6A (Note 6)

Input DC Common Mode Rejection

V
mA

l

±0.75
±1

% of reading% of reading

l

±3
±5

LSB
LSB

l

±0.3

%

l

±1
±1.5

% of reading% of reading

Current Offset

RMS NoiseAµΩ

9Current Gain Error
IOS

±30
450

l

120

(Note 5)

Sampling Rate

dB
320

nV

10.5

MHz

Voltage Sense (VP, VM) ADC
Resolution (No Missing Codes)(Note 5)

Common Mode Voltage
VD

Input Differential Voltage Range

VVP – VVM

l

14

l

0

l

–0.3

VD Quantization Step

bit
15.5
15.5
2

V
V
mV

Voltage Gain Error

l

±0.4

% of reading

Voltage Offset

l

±2

LSB

INLV

Voltage Integral Nonlinearity

l

±2

LSB

TUEV

Voltage Total Unadjusted Error±0.5% of reading

Input DC Voltage Common Mode
Rejection

VD ≥ 4.0Vll

Sampling Rate

4

70

dB
5.25

MHz

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LTC2947
Electrical Characteristics

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOLPARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

Power Measurement
Resolution (No Missing Codes)(Note 5)

l

18

bit

Full-Scale Power450

WPower Quantization Step

50

mW

l

±0.8
±1

% of reading% of reading

l

±4
±6

LSB
LSB

l

±0.3
±0.5

% of reading% of reading

l

±1.2
±1.5

% of reading% of reading

Power Gain Error
Power Offset
INLP
TUEP

Power Integral Nonlinearity
Power Total Unadjusted Error|I| ≥ 6A, VD ≥ 12V (Note 6)|I| ≥ 6A, VD ≥ 12V (Note 6)

Sampling Rate

5.25

MHz

TimingTUETBTime Base Total Unadjusted Error

Internal Clock
Ideal External Clock or Ideal 4MHz
Crystal (Note 5)

tUPDATE

Update Time of Result Registers

l

±0.5
±1

% of reading% of reading

l

±340

ppm

105

ms

l

95

100

Energy Measurement
TUEE

Energy Total Unadjusted Error|I| ≥ 6A, VD ≥ 12V, Ideal External Clock(Note 6)

l

±1.2
±1.5

% of reading% of reading|I| ≥ 6A, VD ≥ 12V, Internal Clock(Note 6)

l

±1.5
±2.5

% of reading% of reading

l

±1
±1.5

% of reading% of reading

l

±1.5
±2.5

% of reading% of reading

Charge Measurement
TUEC

Charge Total Unadjusted Error|I| ≥ 6A, Ideal External Clock (Note 6)|I| ≥ 6A, Internal Clock (Note 6)

Temperature Measurement ADC
Resolution (No Missing Codes)(Note 5)l13

Temperature Quantization Step
Temperature Error(Note 5)

bit
0.204

°C

±5

K

Digital Inputs and Digital Outputs SCL, SDI, GPIO, ALERT, SDO, CS, CLKI, ADO
VITH

Logic Input Threshold

IIN

Input Current SCL, SDI, GPIO

CIN

Input Capacitance

VOL
VOH

SCL, SDI, GPIO, CS, ADO

0.7 • VOVDD

V

l

±1

μA

(Note 5)

l

10

pF

Low Level Output Voltage SDO, GPIO,ALERT

VOVDD ≥ 3.3V, IPIN = 3mA
1.8V ≤ VOVDD < 3.3V, IPIN = 1mA

l
l

0.4
0.4

V
V

High Level Output Voltage (SDO)

ISDAO = –0.5mAl

0.3 • VOVDDl

VOVDD – 0.5

CLKI Input Thresholdl

0.4

External Clock Frequency on Pin CLKI

l

0.2

V
0.7

2

V

25

MHz

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LTC2947
Electrical Characteristics

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOLPARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

500

Ω

500

kΩ

100

pF

AD1, AD0
Resistance Allowed on AD1 and AD0
See Table 3
When They Are Tied to OVDD or DGND
to Set a Valid L or H LevellResistance to DGND to Set a Valid R
Level

l

External Capacitive Load Allowed on
AD1 and AD0 to Set a Valid R Level

l

20

100

I2C Bus Timing
fSCL(MAX)

Maximum SCL Clock Frequency

l

400

900

kHz

tBUF(MIN)Bus Free Time Between STOP/START

l

1.3

µs

tSU,STA(MIN)

Minimum Repeated START Setup Time

l

600

ns

tHD,STA(MIN)

Minimum Hold Time (Repeated)
START Condition

l

600

ns

tSU,STO(MIN)

Minimum Set-Up Time for STOP
Condition

l

600

ns

tSU,DAT(MIN)

Minimum Data Set-Up Time Input

l

100

ns

tHD,DAT(MIN)

Minimum Data Hold Time Input

l

0

ns

tHD,DATO

Data Hold Time Output

l

300

tRST

Stuck Bus Reset TimeSCL or SDI Held Low

l

25

tOF

Data Output Fall Time

(Notes 4, 5)l

20 + 0.1 • CB

900
50

ns
ms
ns

SPI Bus TimingtSPIDS(MIN)

Minimum SDI to SCL Data Setup

l

100

ns

tSPIBUF(MIN)

Minimum SPI Bus Free Time Between
Two CS Active States

l

4

µs

tSPIDH(MIN)

Minimum SDI to SCL Data Hold

l

100

ns

tSPICH(MIN)

Minimum SCL high state duration

l

500

ns

tSPICL(MIN)

Minimum SCL low state duration

l

500

ns

tSPIA1S(MIN)

Minimum CS to First SCL Setup Time

l

50

ns

tSPIA1H(MIN)

Minimum CS to Last SCL Hold Time

l

50

ns

tHDSDOSDO to SCL High to Low Output Hold
Time

l

350

ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Positive currents flow into pins; negative currents flow out of pins.
Minimum and maximum values refer to absolute values.
Note 3: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only. Pin CLKO may also be connected toa crystal as desired. Otherwise permanent damage may occur.

650Note 4: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF).
Note 5: Guaranteed by design and characterization, not subject to test.
Note 6: Guaranteed by design and test correlation.
Note 7: RSENSE value is internally compensated for the actual value of thesense resistor.
Note 8: VOVDDfinal is the supply voltage value at OVDD at the end of its
settling at power-up.

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LTC2947
Timing Diagrams
Definition of Timing on I2C Bus
tof
SDA
tSU, DATtSU, STA

tHD, DATO,
tHD, DATI

tHD, STAtBUFtSU, STO

2947 TD1SCLtHD, STASTARTCONDITIONREPEATED START
CONDITIONSTOPCONDITION

STARTCONDITION

Definition of SPI Timing

SDO

SCL
tSPICLtSPICH

AD1/CStSPIA1StHDSDOtSPIA1HtSPIDHtSPIBUFSDItSPIDS2947 TD2

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LTC2947
Typical Performance Characteristics TA = 25°C, unless otherwise noted.
AVCC Supply Current Continuous
Mode vs Temperature

AVCC Supply Current vs Temperature
0.40

0.20

0.35

0.15

0.30

0.10

0.25

0.05

0.20

0
–50

–25

0
25
50
TEMPERATURE (°C)

5

3

2

1

0.15
100

75

Continuous Mode, VAVCC = VDVCC = 15V

4

IAVCC (µA)

IAVCC (mA)

0.25

0.45

Idle Mode, VAVCC = VDVCC = 15V
Shutdown Mode, VAVCC = VDVCC = 15V

IAVCC (mA)

0.30

0
–50

–25

0
25
50
TEMPERATURE (°C)

2947 G01

Current Measurement Total
Unadjusted Error

6

25

5

20

4

15

3

10

–25

0
25
50
TEMPERATURE (°C)

10.0

0.75

7.5

0.50

5.0

0.25

2.5

0
–0.25

5
100

75

1.00

–5.0

–0.75

–7.5

–1.00
0.1

10

50

10

1.00

0.25
0
–0.25
–0.50

6

4

–0.75
100
2947 G06

8

0–5 –4 –3 –2 –1 0 1 2
OFFSET (LSB)010ISENSE (A)20302947 G05

435 DEMOBOARDS

2

75

–10

Current Measurement Offset
vs Temperature

8

0.50

–20

2947 G04

0.75

0
25
50
TEMPERATURE (°C)

–10.0
–30

Current Measurement Offset
Distribution

NUMBER OF PARTS

CURRENT MEASUREMENT GAIN ERROR (%)

1
IIP (A)

Current Measurement Gain Error
vs Temperature

–25

–2.5

–0.50

2947 G03

–1.00
–50

0

CURRENT MEASUREMENT OFFSET (LSB)

2–50

Current Measurement Integral
Nonlinearity

INL (LSB)30IDVCC (µA)

IDVCC (mA)

7

35

TUE (%)

Idle, Cont. Mode, VAVCC = VDVCC = 15V
Shutdown Mode, VAVCC = VDVCC = 15V

1002947 G02

DVCC Supply Current
vs Temperature
8

75

3

4

5

2947 G07

3
2
1
0
–1
–2
–3
–4
–50

–25

0
25
50
TEMPERATURE (°C)

75

1002947 G08

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LTC2947
Typical Performance Characteristics TA = 25°C, unless otherwise noted.
Power Measurement Total
Unadjusted Error

Power Measurement Gain Error
vs Temperature

TUE (%)

0
–0.5
–1.0
–1.5
–2.0

1

10

100

ISENSE (A)

1.00

1.00

0.75

0.75

0.50

0.50

0.25

0.25

0
–0.25

–0.25

–0.50

–0.50

–0.75

–0.75

–1.00
–50

0.75

3

0.50

2

0.25

1

INL (LSB)VOLTAGE MEASUREMENT GAIN ERROR (%)

4

–0.25

–0.75

–3

1.00

0.5

0.75

0.4

5.0
7.5
10.0
VD = VP – VM (V)

12.5

INTERNAL CLOCK
EXTERNAL CLOCK

025
50
TEMPERATURE (°C)

75

1002947 G15

7.5
VD (V)

10

12.5

15
2947 G14

1.50

0.1
0.0
–0.1

–0.5

5

ACCELERATED LOAD LIFE TESTDATA SCALED TO TJ = 85°C

1.75

1.25
1.00
0.75
0.50
0.25

–0.4
–25

2.5

Sense Resistor Stability
2.00

–0.3

–0.75

0

2947 G13

–0.2

–0.50

10

0

15

∆R/RO (%)

TUE (%)TUE (%)

2.5

0.2

0.25

IVP = –IVM

5

0.3

0.50

15
2947 G11

15

Charge Measurement Total
Unadjusted Error vs Current

Time Base Total Unadjusted Error
vs Temperature

–0.25

5
10
VD = (VVP – VVM) (V)

20

–4
0.0

100

0

0

25

2947 G12

–1.00
–50

–1.00

VP, VM Input Current vs
VP, VM Sense Voltage

–1
–2

75

100

0

–0.50

0
25
50
TEMPERATURE (°C)

75

Voltage Measurement Integral
Nonlinearity

1.00

–25

0
25
50
TEMPERATURE (°C)

2947 G10

Voltage Measurement Gain Error
vs Temperature

–1.00
–50

–25

2947 G0900

INPUT CURRENT (µA)

0.5

POWER MEASUREMENT GAIN ERROR (%)

VD = 12V
VD = 5V
VD = 3.3V

TUE (%)

1.0

Voltage Measurement ADC Total
Unadjusted Error

0

10

20
ISENSE (A)302947 G16

0

0

2

4
6
TIME (Years)

8102947 G17

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LTC2947
Pin Functions
IM (Pins 1, 2, 3, 4, 5, 6): Negative Current Input. Connects to internal current sense resistor. All six pins mustbe tied together.

BYP (Pin 17): Internal 2.5V Voltage Supply for Powering
Internal Circuitry. Do not load. Connect a 1μF bypass
capacitor to DGND.

AGND (Pin 7): Analog Ground. See Layout Considerationsin the Applications Information section.

DVCC (Pin 18): Digital Power Supply. Connect a 1μF
bypass capacitor from DVCC to DGND. AVCC and DVCC
should be connected together.

DGND (Pin 8): Digital Ground. See Layout Considerationsin the Applications Information section.
AD0 (Pin 9): Address Input 0. To select SPI mode, tie AD0
to OVDD. For I2C mode, tie AD0 to ground, either directly(L) or through a 100kΩ resistor (R), to select one of six
I2C addresses. See Table 3 in the Applications Information
section for details.
AD1/CS (Pin 10): Address Input 1 / Chip Select. In SPI
mode, this is the Chip Select input, active low. In I2C mode,tie to OVDD (H), DGND (L), or through a 100kΩ resistor to
ground (R) to select one of six I2C addresses. See Table 3
in the Applications Information section for details.
GPIO (Pin 11): General Purpose I/O (Open Drain). Connect
through a pull-up resistor to OVDD. Tie to ground if unused.
ALERT (Pin 12): Alert Output. ALERT behaves as an opendrain logic output that pulls to ground if an unmasked
Threshold register is exceeded or an unmasked error
condition is detected. When the interface is operating in
I²C mode, the ALERT pin follows the SMBus ARA (Alert
Response) protocol. See the I2C Mode section for more
information. Tie ALERT to ground if unused.
SCL (Pin 13): Serial Clock. Serial clock input in both I2C
and SPI Modes.
SDO (Pin 14): Serial Data Output. Data output in both I2C
and SPI modes. In I2C mode, this pin may be tied to SDI
to act as a standard bidirectional SDA pin, or kept separate
to ease opto-isolation.
SDI (Pin 15): Serial Data Input. Data input in both I2C and
SPI modes. In I2C mode, this pin may be tied to SDO toact as a standard bidirectional SDA pin, or kept separate
to ease opto-isolation.
OVDD (Pin 16): Digital Interface Supply. Connect a 1μF
bypass capacitor from OVDD to DGND. The voltage at
OVDD must reach 90% of its final value at the same time or
before the voltage at AVCC/DVCC reaches this voltage level.

10

DNC (Pin 19): Do Not Connect.
AVCC (Pin 20): Analog Power Supply. Connect a 1μF
bypass capacitor from AVCC to AGND. AVCC and DVCC
should be connected together.
IP (Pins 21, 22, 23, 24, 25, 26): Positive Current Input.
Connects to internal current sense resistor. All six pins
must be tied together.
VP (Pin 27): Positive Voltage Sense Input. Connect tothe positive terminal of the voltage to be measured. A
22Ω series resistor and a 2.2µF bypass capacitor to VM
is recommended.
VM (Pin 28): Negative Voltage Sense Input. Connect tothe negative terminal of the voltage to be measured. A
22Ω series resistor and a 2.2µF bypass capacitor to VP
is recommended.
CFP (Pin 29): Positive Filter Pin. Connect a 1µF bypass
capacitor between CFP and CFM and a 0.1μF common
mode capacitor from CFP to AGND.
CFM (Pin 30): Negative Filter Pin. Connect a 1µF bypass
capacitor between CFP and CFM and a 0.1μF common
mode capacitor from CFM to AGND.
CLKI (Pin 31): Clock Input. Connect to ground if theinternal clock is used. For improved accuracy, connect acrystal between CLKI and CLKO and matching capacitors
to ground, or drive CLKI with an external clock. See theTimebase Control section for more information.
CLKO (Pin 32): Clock Output. Connect a crystal between
CLKO and CLKI if used; leave floating otherwise.
EXPOSED PAD 1 (Pin 33): Internal current sense resistor. Do
not connect to any metal or other conducting material. See
the Layout Considerations section for more information.
DGND (Pin 34): Exposed Pad. Connect to DGND or leave
floating.
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LTC2947
Block Diagram
LTC2947OVDD
LOGIC & MEMORYSTATUSCONTROLSCLCURRENT THRESHOLDS
CFP
IP
IM

SDO

CURRENT50Ω
RSENSE
300µΩ

I

50Ω

CURRENT TRACKING∑∆
1ST ORDER
MODULATORLPF

POWER THRESHOLDSI2C OR
SPI I/O

SDI
AD1/CS

POWER

CFM

AD0

POWER TRACKINGVOLTAGE THRESHOLDS
P

VP
VM

VOLTAGE∑∆
1ST ORDER
MODULATOR

LPF

ALERT

VOLTAGE TRACKING

M1
NMOS

TEMP. THRESHOLDSAUXTEMPSENSORTEMPERATURE∑∆
1ST ORDER
MODULATOR

TEMP. TRACKINGLPF

CURRENT HISTORYCHARGE THRESHOLDS

AVCC

LDO1

LDO2
DVCC

LDO3

LDO4

CHARGE 1 & 2

3.3V

3.3V

1.2V

GPO/ALERTCONTROL

DGND

M2
NMOS
GPIO

CHARGE TRACKINGREFERENCE

OSC

ENERGY THRESHOLDSENERGY 1 & 2

SHUTDOWN DOMAIN SUPPLYENERGY TRACKINGTIME 1 & 2

2.5V... SEE REGISTER MAP...

BYP
AGND

CLKI

CLKO
2947 BD

2947faFor more information www.linear.com/LTC2947

11

LTC2947
Operation
Overview

Single Shot (SSHOT):The LTC2947 is a high precision power and energy meterwith integrated sense resistor for currents up to ±30A
and voltages as high as 15V. It measures a total of sevenparameters: current, voltage, power, charge (coulombs),
energy, and run time, as well as its own chip temperature.

When the SSHOT bit in the Operation Control register
is set, the LTC2947 takes four measurements (current,
voltage, power, and temperature), and updates the corresponding registers and the Minimum/Maximum andThreshold registers. No time measurements are made andthe Charge and Energy registers are not updated. It thenclears the SSHOT bit in the Operation Control register, sets
the UPDATE bit in Status register and returns to the IDLE
mode. One single shot measurement cycle takes 100ms.
The host can poll the UPDATE bit in the Status register todetect the completion of the measurement cycle.

It includes three No Latency Δ∑ analog-to-digital converters to simultaneously measure current, voltage, andpower. It also measures die temperature and derives theaccumulated quantities charge, energy, and time using
an external clock or an on-board oscillator. It stores thesevalues in internal registers that can be read out via theserial interface, configurable as either I2C or SPI.
The LTC2947 keeps track of the minimum and maximum
measured values for each of the measured quantities.
Thresholds can be set for each parameter, and the LTC2947
will set the corresponding bit in the Alert register andoptionally alert the host by pulling low on the ALERT pin
when a threshold is exceeded.
A GPIO pin is included that can be used for four different
purposes. It can be configured as a general-purpose-logic
input or output, as an output to automatically control a
fan based on the LTC2947’s internal silicon temperature
measurement or as an input to enable and disable accumulation of charge, energy, and time.
Modes of Operation

When the CONT bit in the Operation Control register is set,the LTC2947 repeatedly measures current, voltage, power,
and temperature, recalculates energy, charge, time andupdates the Minimum/Maximum Tracking and Thresholdregisters. Each measurement cycle takes about 100ms.
The current and power ADCs run continuously in thismode, ensuring that no charge or energy is missed. The
LTC2947 remains in continuous mode until bit CONT of
the Operation Control register is reset by the user. If the
SSHOT bit is set while in continuous mode, the LTC2947
completes the current measurement cycle and then enters
single shot mode, clearing the CONT bit in the Operation
Control register.
Shutdown (SHDN):

Power Up
When all power supply voltages have risen above theirUVLO thresholds, the LTC2947 boots up, sets all registers to their default state, and enters IDLE mode, where it
waits for further instructions from the host. The LTC2947
requires about 100ms to boot up and enter the IDLE mode.
IDLE
In IDLE mode, all internal circuitry is active but no measurements are being made. From IDLE, the LTC2947 can be
instructed to go into single shot, continuous, or shutdown
modes via the Operation Control control register.

12

Continuous Measurement Mode (CONT)

When the SHDN bit in the Operation Control register isset, the LTC2947 goes into shutdown mode, and supply
current reduces to about 10µA. If the device is in the
middle of a measurement cycle, in either single shot orcontinuous mode, it completes the cycle before entering
shutdown and clearing the SSHOT or CONT bits. Shutdown
clears the voltage, current, and temperature results, but
preserves the values of the accumulated quantities chargeand energy and all threshold and tracking values.
While in shutdown mode, the LTC2947 continues to monitor
the serial interface. In SPI mode, the LTC2947 transitions
from shutdown to IDLE when CS goes low. In I2C mode,

2947faFor more information www.linear.com/LTC2947

LTC2947
Operation
the LTC2947 transitions to IDLE after acknowledging thecorrect slave address. The LTC2947 requires about 100ms
to wake up from shutdown. During this time, it ignores
register writes and responds to register reads with 0x01.
Once awake, the LTC2947 goes into IDLE mode and waits
for further instructions. The host can poll the Operation
Control register and watch for a 0x00 response to determinethat the LTC2947 is awake and in IDLE mode.

UVLOSTBY bit and the PORA bit are only set if the supply
voltage at AVCC/DVCC drops below VUVLO and a power-on
reset has occurred.

In shutdown mode, the internal analog and digital supplies
are switched off. This causes the UVLOA and UVLOD bits
to be set when the LTC2947 resumes from shutdown. The

Switching between operating modes can require up to
100ms if a measurement cycle is in progress.

The state diagram (Figure 1) summarizes the different
modes of operation of LTC2947. Transitions and control
bit settings initiated by the user are marked in black whiletransitions and control bit settings caused by the device
are marked in blue.

POR

IDLE

SHDN=0SHDN=1SSHOT=1

CONT=1SSHOT=0

SHDN=1, SSHOT=0
SINGLE SHOT

CONT=0SHUTDOWNSHDN=1, CONT=0

SSHOT = 1, CONT=0

CONTINUOUS

2947 F01

Figure 1. Modes of Operation

2947faFor more information www.linear.com/LTC2947

13

LTC2947
Operation

A second ADC sequentially measures both temperatureand differential voltage between the VP and VM pins while
the current measurement is being made. The temperature
measurement is both reported to the host and used internally by the LTC2947 to compensate for the temperaturedrift of the internal current sense resistor, resulting in very
stable current measurements. The voltage measurement
has a 2mV resolution and temperature has a 0.204°C
resolution. The differential voltage measurement range(VP-VM) ranges from –0.3V to 15.5V, independent of
supply voltage.
Note that the temperature measurement is made witha sensor on the die, which can vary significantly fromambient temperature if the current in the internal sense
resistor is high. A high supply voltage at AVCC/DVCC
increases the internal power and will also increase theinternal temperature.
Power Measurement
The LTC2947 measures power with a third ADC that multiplies voltage (VP-VM) and current at the full 5MHz sampling
frequency, prior to any averaging due to the analog-todigital conversion. This maintains accuracy even if current
and voltage change in phase during the 100ms conversion
time, which can happen if the power is drawn from a sourcewith significant impedance, such as a battery. Figure 2
shows an example of a 12V supply dropping to 11V due tointernal series resistance when 9A current pulses are drawn

14

30

13

25

12

20

11

15

10

10

9

5

8

0

0

0.2

0.4
0.6
TIME (s)0.81VOLTAGE (V)The LTC2947 measures each input with an ADC specificallytailored for the task. Current through the internal sense
resistor is measured with a ∆∑ ADC that has a measurement
range of ±30A and a resolution of 3mA. The common mode
voltage can range from 100mV below GND up to 15.5V,
regardless of the supply voltage at AVCC. This ADC uses
a first-order architecture and continuous offset calibration
to ensure that all input samples are averaged with equal
weight and none are missed—the current ADC is never“blind.” A 10MHz sampling rate maintains averaging accuracy for all current waveforms including harmonics up
to 2.5MHz. A new average value is reported every 100ms.

by a load. In this example, the multiplication of average
current with average voltage would lead to a 6% error in
the calculated power as the voltage is significantly lower
than the average voltage at the moments where the current is drawn. The scheme used by the LTC2947 avoids
this error, maintaining specified accuracy with signals up
to 50kHz.

CURRENT (A)Current, Voltage and Temperature
Measurement

72947 F02

Figure 2. Power Measurement of Transient Signals

Charge, Energy Measurement andAccumulated Time
The LTC2947 integrates the current and power measurements over time to calculate charge and energy flowing toor from the load. It also keeps track of total accumulated
time used for the integration. The integration time basecan be provided by the internal clock, an external clockattached to CLKI, or an external crystal connected to CLKI
and CLKO. If an external clock is used, the LTC2947 presents
time, charge and energy as a mathematical relationshipto the external clock period.
For each of the quantities charge, energy, and time, theLTC2947 provides two sets of registers. Each register set
can be separately configured to accumulate either basedon the sign of the measured current, or by the level of the
GPIO pin, or by the Control register settings. This allows
the first set of accumulation registers to be configured
to always integrate while the second set only integrates
if current is positive (to account for battery charging efficiency, for example). A minimum current threshold canalso be set below which integration is stopped.
2947faFor more information www.linear.com/LTC2947

LTC2947
Applications Information
TimeBase: Internal/External Clock/Crystal

Table 1. Parameter PRE with External ClockAccurately measuring charge and energy by integrating
current and power requires a precise timing. The LTC2947
uses either a trimmed internal oscillator or an external
clock as the time base for determining the integration
period. It can use either an external square wave clockin a frequency range between 200kHz and 25MHz or a
4MHz crystal as an external clock input. If an externalsquare wave is used, it should be connected to the CLKI
pin and the CLKO pin should be left floating. Figure 3
shows the recommended circuit if a crystal is used togenerate the reference clock.

fREF

PRE

2PRE

PRE[2:0]

0.1MHz ≤ fREF ≤ 1MHz

0

1

000

1MHz < fREF ≤ 2MHz

1

2

001

2MHz < fREF ≤ 4MHz

2

4

010

4MHz < fREF ≤ 8MHz

3

8

011

8MHz < fREF ≤ 16MHz

4

16

100

16MHz < fREF ≤ 25MHz

5

32

101

Internal

7

–

111

When the internal clock is used, tie CLKI to DGND andleave CLKO floating.

⎛
⎞
fREF
DIV = floor ⎜ PRE⎟• 32768Hz ⎠⎝2

LTC2947

CLKO

CLKI
X1

33pF

The second stage of the prescaler then divides the result
by a factor DIV. DIV is set between 0 and 31 by bits [7:3]of the Timebase Control register. DIV should be set to thenext lower integer value of the ratio between the outputof the first stage of the prescaler (fREF_1 = fREF/2PRE) and
32768Hz or, in other terms:

If a 4MHz crystal is used, the values are: PRE=2, DIV=30.
33pF
X1: ABLS2-4.000MHZ-D4Y-T2947 F03

Figure 3. Reference Clock with a Crystal

Timebase Control
The LTC2947 uses the internal oscillator by default. If
an external clock or a crystal is used, the PRE and DIVparameters in the Timebase Control register need to be
set appropriately. The LTC2947 then compares its internal
clock to the external frequency and represents time, charge,
and energy as multiples of the external clock period. To
accommodate the large range of allowed external frequencies, an internal pre-scaler must be configured via the
Timebase Control register (0xE9).
The prescaler consists of 2 stages, with the first dividing
the external frequency fREF by a factor 2PRE, and the second
by a factor DIV. PRE is set between 0 and 5 with bits [2:0]of the Timebase Control register (0xE9). PRE should be
set to the lowest value that gives less than 1MHz when
dividing the external frequency by 2PRE as shown in Table 1:

The QuikEval™ software for the LTC2947 contains aneasy-to-use calculator for these parameters.
Table 2 gives a few examples for common frequencies:
Table 2. Timebase Settings For Common Frequencies
fREF
(MHz)

PRE

2PRE

fREF_1(MHz)DIV

TIMEBASE
CONTROL [7:0]

1MHz

0

1

1

30

1111 0000

1.5MHz

1

2

0.75

22

1011 0001

4MHz

2

4

1

30

1111 0010

10MHz

4

16

0.625

19

1001 1100

20MHz

5

32

0.625

19

1001 1101

25MHz

5

32

0.781

23

1011 1101

Internal

7

–

–

X

XXXX X111

Configuring the GPIO Pin
The LTC2947 has one GPIO pin that can be configured
to be a general purpose input or a general purpose open
drain output by means of the bit GPOEN in the GPIO Status
and Control register (0x67)[0].
2947faFor more information www.linear.com/LTC2947

15

LTC2947
Applications Information
When the GPIO pin is configured as an input by setting
0x67[0]=0, the status of the GPIO pin is reported by the
GPI bit of the GPIO Status and Control register at (0x67)[4]. The state of the general purpose input pin can beused to control the accumulation of charge, energy andtime by means of the Accumulator Control GPIO register(0xE3). This accumulation function can be enabled separately for each of the two sets of accumulation registers.
Setting bits (0xE3)[1:0] to [01] enables accumulationof Charge1, Energy1 and Time1 when GPIO is 1, whilesetting bits (0xE3)[1:0] to [10] enables accumulation ofCharge1, Energy1 and Time1 when GPIO is 0. Setting bits
(0xE3)[1:0] to [00] disables the accumulation control of
the first set of accumulation registers by the GPIO level.
Similarly, accumulation of Charge2, Energy2 and Time2
can be controlled by bits (0xE3)[3:2] of the accumulation
control GPIO Register.
When the GPIO pin is configured as an open drain output
by setting (0x67)[0]=[1], it can be pulled low by writing
bit GPO in the GPIO Status and Control register (0x67)[5] to 0 or released high by writing bit GPO to 1. As an
open drain output, the GPIO pin can also be configured
to control a fan as a function of measured temperatureby setting bit FANEN (0x67)[6] to 1. Then, the GPIO pin
becomes active as soon as a temperature measurement
result is above the threshold TFANH written at (page1.0x9C)
and (page1.0x9D), and is deactivated if the temperature
falls below the threshold TFANL written at (page1.0x9E)
and (page1.0x9F). The polarity of the GPIO pin can be
configured by setting bit FANPOL at (0x67)[7] to 0 or
1, respectively. The GPIO output level is maintained in
shutdown. Since the internal sampling rate of the GPIO
state is 100ms the reaction on any change of that state
as input or output may be in this time range.

Internal Sense Resistor
The LTC2947 uses proprietary techniques to compensate
for the internal sense resistor's temperature coefficient. A
factory trim of both absolute value and tempco compensation, together with an ultralow offset ADC, contribute to the
LTC2947's superior accuracy when current measurement
is involved (i.e. current, power, charge, energy).
Like all sense resistors, the integrated sense resistor in the
LTC2947 will exhibit minor long-term resistance shifts.
See the Typical Performance Characteristics section for
expected resistor drift performance under worst-caseconditions. Drift will be much less at lower temperatures
and/or currents.
Current and Voltage Input Filtering
To ensure the full electrical performance of the ADCs
for current, power and voltage, apply the input filtering
circuitry as shown in Figure 4 to pins CFP, CFM, VP and
VM. These components provide optimum input filtering
for noise reduction. Equal time constants at the current
and voltage inputs minimize errors in power measurementof transient signals due to different delays in each path.

V+ TO BEMEASURED

22Ω

V– TO BE

22Ω

VP

0.1µF
2.2µF
0.1µF

LTC2947
VM

MEASURED

AGND
CFP

0.1µF
1µF
0.1µF

CFM
2947 F04

Figure 4. Input Filtering

162947faFor more information www.linear.com/LTC2947

LTC2947
Applications Information
Layout Considerations

If thinner traces are used, Figure 6 shows the correction
factor with which the Current LSB is to be multiplied toincrease the accuracy. Since the Current reading is involved
also in Power, Charge and Energy reading, the correction
factor is to be taken into account in these quantities, too.

Lowering the electrical resistance of the PCB traces tothe IP and IM pins minimizes heating of the area near the
LTC2947 and the temperature increase of the LTC2947
itself. Methods to lower the electrical resistance of the
PCB traces include increasing the width of these traces
and the number of PCB layers and including a sufficientnumber of vias as shown in Figure 5.

The exposed pad between IP and IM must not have contact
or be soldered to any electrically conducting PCB pad or
track.

When connecting to the IP and IM pins, it is recommended
to use PCB traces with a 70µm minimum thickness orgreater. The current reading value is slightly dependent
on the thickness of IP and IM PCB traces below 70µm.

USE SEVERAL LAYERS

AVCC/DVCCUSE SEVERAL LAYERS

SUPPLY-STARPOINT

DGND
AGND

The input filter common-mode capacitors and pins CFP and
CFM should be star-connected directly to the AGND pin.
Any unrelated ground currents in this connection will cause
measurement errors. This can be achieved by combining

C8
GROUNDSTARPOINT

DVCC
C7

DGND

AVCC

AGND
IP

IM

IP

IM

IP

IM

IP

IM

IP

IM

IP
VP VM CFP CFM

IM

C1
C4
C5
C2

C3

C6

R1

INNER LAYERTOP LAYER

R22947 F05

Figure 5. Recommended Layout of Current Tracks, Voltage Input and Ground2947faFor more information www.linear.com/LTC2947

17

LTC2947
Applications Information
the ground tracks of the capacitors at CFP, CFM including
the AGND pin to a separate small plane and connecting
this plane at one point to the ground of the PCB. Figure
5 sketches this star connection concept; the interference
to the ADC inputs is minimized. In the same way, a small
separate plane can collect the ground connections of thecapacitors attached to DVCC, OVDD, including the DGND
pin, and be connected to the same ground-starpoint as
the AGND plane to the ground of the PCB.

The crystal oscillator’s clock amplitude is sensitive toparasitics such as stray capacitance on the CLKOUT pin
and coupling between the CLKIN and CLKOUT pins. It is
recommended that the CLKIN and CLKOUT traces fromthe LTC2947 to the crystal oscillator network be as shortas practical, with the load capacitors placed next to the
crystal. To minimize stray capacitances, avoid large groundplanes and digital signals near the crystal network.

The supplies of AVCC and DVCC pins should also be starrouted. The decoupling caps should be placed closer tothese pins than the supply-starpoint.

CURRENT LSB CORRECTION FACTOR

1.002
1.000
0.998
0.996
0.994
0.992
0.990

20

35
50
65
80
95
PCB LAYER THICKNESS (µm)

1102947 F06

Figure 6. Current LSB Correction
Factor vs PCB Thickness

18

2947faFor more information www.linear.com/LTC2947

LTC2947
Digital Interface
Selecting SPI or I2C Serial Interface

Write Protocol

The serial interface of the LTC2947 can operate in either
SPI or I2C mode. To select SPI mode, tie AD0 to OVDD.
To select I2C mode, connect AD0 according to Table 3.
The LTC2947 selects SPI or I2C mode by reading pin AD0
when DVCC is powered up. To ensure proper mode detection, OVDD should be powered up before DVCC.

The master writes to the LTC2947 by sending 0x00 as thefirst byte in a transaction followed by the address of thefirst register to be written. The next transmitted byte will
be written to this address. The LTC2947 increments its address pointer after each byte is received, so multiple bytes
can be written as part of a single transaction. Incomplete
bytes are discarded.

SPI Mode

Read Protocol

Physical Layer
In SPI mode, the LTC2947 acts as a SPI slave, with theAD1 pin acting as CS (chip select, active low). Logic input
thresholds and output swings are set by the voltage at the
OVDD pin, which should be connected to the same supply as the SPI master device. A 1µF bypass capacitor isrecommended from OVDD to DGND. The SDI pin is often
referred to as MOSI, the SDO pin as MISO. The LTC2947
samples data at SDI on the rising edge of SCL and changes
data at SDO on the falling edge of SCL (often referred toas CPHA=0, CPOL=0).
Data Layer
All data sent to the LTC2947 is transmitted in 8-bit bytes,
MSB first. The LTC2947 returns data in this same format.
Multiple bytes can be sent in a single transaction. Figure 8
and Figure 9 show typical write and read transactions.

The master reads from the LTC2947 by sending 0x01
as the first byte in a transaction followed by the addressof the first register to be read. The LTC2947 sends databytes starting from that address, incrementing the address
pointer after each byte sent. Any number of bytes can beread; if the address pointer reaches address 0xFF, it willroll over to address 0x00. Any data on the SDI line after
the register address is ignored by the LTC2947.
SPI Alert Handling
The LTC2947 can be configured to generate alerts via
the ALERT pin when a variety of events occur. To enable
alerts, set bit ALERTBEN in the Alert Master Control Enable register (0xE8)[0] (this is the default setting). Selectwhich events trigger alerts by clearing bits in the Mask
registers (addresses 0x88 to 0x8F).
If an alert is enabled, the corresponding event causes the
ALERT pin to pull low. To release the ALERT pin in SPI
mode, the master must read the Status, Threshold andOverflow Alert registers (0x80 to 0x87).

2947faFor more information www.linear.com/LTC2947

19

LTC2947
Digital Interface

X: DON'T CARE
Z: HIGH IMPEDANCESCL

AD1/CS

SDI/MOSI

X

1

2

3

4

5

6

7

8

SDO/MISO

Z

1

2

3

4

5

6

7

8

X

Z
2947 F07

Figure 7. General Data Transfer Over SPI

20

2947faFor more information www.linear.com/LTC2947

LTC2947
Digital Interface

FROM MASTER TO SLAVE
SDI/MOSI0 0 0 0 0 0 0 0
READ/WRITE

a7 : a0d7 : d0

d7 : d0

d7 : d0

REGISTERADDRESS A

DATA TOADATA TO
A+1

DATA TO
A+2

SDO/MISOFROM SLAVE TO MASTER...

HIGH IMPEDANCE

AD1/CS2947 F08

Figure 8. SPI Write Protocol

READ/WRITE
SDI/MOSI

SDO/MISO0 0 0 0 0 0 0 1

REGISTERADDRESS A
a7 : a0

HIGH IMPEDANCE

DON'T CARE

d7 : d0

d7 : d0

d7 : d0

DATA FROMADATA FROM
A+1

DATA FROM
A+2...

AD1/CS2947 F09

Figure 9. SPI Read Protocol

2947faFor more information www.linear.com/LTC2947

21

LTC2947
Digital Interface
I2C ModeAcknowledge

I2C Device Addressing

An acknowledge signal is used for handshaking between
the master and the slave. When receiving data, the LTC2947
will pull the SDA line low every ninth clock cycle to acknowledge each data byte. If the slave fails to acknowledge byleaving SDA high, the master should abort the transmission by generating a STOP condition. Similarly, when themaster is receiving data from the slave, it must generateacknowledge pulses by pulling down the SDA line every
9th clock. After the last byte has been received by themaster, it may leave the SDA line high (not acknowledge)
and issue a STOP condition to terminate the transmission.

If AD0 is not tied high at power up, the LTC2947 operates in I2C mode. The I2C address can be configured byconnecting AD1 and AD0 as shown in Table 3. The levels
are: L: low, tie to DGND, H: high, tie to OVDD, R: resistor,
connect to DGND with a 100kΩ resistor. The LTC2947 will
check AD0 and AD1 at the beginning of each I2C transaction
and respond to the corresponding I2C address.
START and STOP Conditions
When the I2C bus is idle, both SCL and SDA are in the HIGH
state. The master signals the beginning of a transmission
with a START condition by transitioning SDA from high to
low while SCL stays high. When the master has finishedcommunicating with the slave, it issues a STOP condition
by transitioning SDA from LOW to high while SCL stays
high. The bus is then free for another transmission.
Stuck-Bus Reset
The LTC2947 I2C interface includes a stuck-bus timer toprevent it from holding the bus lines low indefinitely if the
SCL signal is interrupted during a transfer. The timer starts
when either SCL or SDI is low, and resets when both SCL
and SDI are high. If either SCL or SDI stay low for morethan 50ms, the stuck-bus timer will reset the internal I2C
interface to release the bus. Normal communication will
resume at the next START command.

Write Protocol
The master begins a write operation with a START condition
followed by the 7-bit slave address with the R/W bit set tozero. If the slave address matches the address programmed
at its AD0/AD1 pins, the LTC2947 acknowledges the address byte. The master then sends a register address bytethat indicates which internal register the master wishes towrite. The LTC2947 acknowledges again and latches theregister address into its internal register address pointer.
The master then sends the data byte(s) and the LTC2947
acknowledges and writes the data into the selected internalregister. The register address pointer will automaticallyincrement by one as each byte is acknowledged. The write
operation terminates and the register address pointerresets to 00h when the master sends a STOP condition.

Table 3. I2C Addresses
AD0

AD1

8-BIT ADDRESSBYTE READ

8-BIT ADDRESSBYTE WRITE

7-BIT DEVICEADDRESS
a6:a0

a6

a5

a4

a3

a2

a1

a0

R/W

L

L

0xB8

0xB9

0x5C

1

0

1

1

1

0

0

1/0

L

H

0xBA

0xBB

0x5D

1

0

1

1

1

0

1

1/0

BINARY DEVICE ADDRESS

L

R

0xBC

0xBD

0x5E

1

0

1

1

1

1

0

1/0

R

L

0xC8

0xC9

0x64

1

1

0

0

1

0

0

1/0

R

H

0xCA

0xCB

0x65

1

1

0

0

1

0

1

1/0

R

R

0xCC

0xCD

0x66

1

1

0

0

1

1

0

1/0

Note 10: L: tie to DGND, H: tie to OVDD, R: resistor, connect to DGND with a 100kΩ resistor.

22

2947faFor more information www.linear.com/LTC2947

LTC2947
Digital Interface
SDA

a6-a0

SCL

b7-b0

1-7

8

9

b7-b0

1-7

8

9

1-7

8

9

S

P

START
CONDITION

ADDRESS

R/ W

ACK

DATA

ACK

DATA

ACK

START
CONDITION
2947 F10

Figure 10. General Data Transfer Over I2C

S

ADDRESS W
a6:a0

0

A

REGISTER

A

DATA

A

0

b7:b0

0

b7:b0

0

FROM MASTER TO SLAVEPFROM SLAVE TO MASTER
2947 F11

Figure 11. I2C Write Byte Protocol

A: ACKNOWLEDGE (LOW)
A: NOT-ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W: WRITE BIT (LOW)S

ADDRESS W
a6:a0

0

A

REGISTER

A

DATA

A

DATA

A

...

DATA

A

0

b7:b0

0

b7:b0

0

b7:b0

0

...

b7:b0

0

S: START CONDITION
P: STOP CONDITIONP
2947 F12

Figure 12. I2C Write Multiple Bytes Protocol

S

ADDRESS W
a6:a0

0

A

REGISTER

A

0

b7:b0

0

S

ADDRESS

R

A

DATA

A

a6:a0

1

0

b7:b0

1
2947 F13

Figure 13. I2C Read Byte Protocol

S

ADDRESS W
a6:a0

0

A

REGISTER

A

0

b7:b0

0

S

P

ADDRESS

R

A

DATA

A

DATA

A

...

DATA

A

a6:a0

1

0

b7:b0

0

b7:b0

0

...

b7:b0

1

Figure 14. I2C Read Multiple Bytes Protocol

P2947 F142947faFor more information www.linear.com/LTC2947

23

LTC2947
Digital Interface
Read Protocol
The master begins a read operation with a START condition
followed by the 7-bit slave address with the R/W bit set tozero. If the slave address matches the address programmed
at its AD0/AD1 pins, the LTC2947 acknowledges and themaster sends a register address byte that indicates whichinternal register the master wishes to read. The LTC2947
acknowledges again and latches the register address byte
into its internal register address pointer. The master thensends a repeated START condition followed by the same
7-bit address with the R/W bit now set to 1. The LTC2947
acknowledges one more time and then sends the contentsof the requested register. If the master acknowledges, theLTC2947 will increment the register address pointer andsend the contents of the next register, and send out databytes. The read operation terminates and the register
address pointer resets to 00h when the master sends a
STOP condition.
SMBus Alert Response Protocol
The LTC2947 uses the SMBus alert response protocol(ARA) to manage alerts in I2C mode. To enable alerts, set
the ALERTBEN bit in the Alert Master Control Enable register

24

S

ALERT RESPONSE
ADDRESS
R
0001100

1

A
0

DEVICEADDRESS W
a6:a0

0

A

P

1
2947 F15

Figure 15. Serial Bus I2C Alert Response Protocol(0xE8)[0]—this is the default setting. Select which events
trigger alerts by clearing bits in the Alert Mask registers(addresses 0x88 to 0x8F).
If two or more devices on the same bus are generating
alerts when the ARA is broadcasted, standard I2C arbitration causes the device with the highest priority (lowest
address) to reply first and the device with the lowest priority (highest address) to reply last. The bus master will
repeat the alert response protocol until the ALERT line isreleased. Once the device causing the alert is identified,
the master may read the Status, Threshold and Overflow
Alert registers (0x80 to 0x87) to determine what caused
the fault. In SPI mode, reading the Status or Alert registers
will release the ALERT pin. In I2C mode, the ALERT pin
is released using the SMBus ARA protocol; reading the
Status or Alert registers will not release ALERT.

2947faFor more information www.linear.com/LTC2947

LTC2947
Register Map
The LTC2947 is configured and communicates with thehost system through its internal registers, addressed
via the serial interface. There are a total of 496 register
addresses arranged as two 256-byte pages in the LTC2947
register map, not all of which are used (Figure 16).

platform, are available at the LTC2947’s Linduino Sketch
Webpage (http://www.linear.com/product/LTC2947#code).
The headers provide register address definitions, register
bit mask definitions, LSB values for RAW quantities, PRE/
DIV calculation from external oscillator frequencies, andLSB values for accumulated quantities depending on user
defined PRE/DIV values.

In order to facilitate the embedding of the LTC2947 intoa system, C/C++ code examples targeting the Linduino,Linear Technology’s Arduino compatible development

OFFSET
0

1

2

3

4

5

6

7

8

BASE

9

A

B

C

D

E

F

PAGE 00x00

C1[47:0]E1[47:0]

TB1[31:0]

0x10

C2[47:0]E2[47:0]

TB2[31:0]

0x20
0x30
0x40

IMAX[15:0]

IMIN[15:0]

PMAX[15:0]

PMIN[15:0]

0x50

VMAX[15:0]

VMIN[15:0]

TEMPMAX[15:0]

TEMPMIN[15:0]

0x60

VDVCCMAX[15:0]

VDVCCMIN[15:0]

GPIOSTATCTL

0x70
0x80

STATUS

0x90

STATVTSTATIP

STATC

I[23:0]0xA0V[15:0]

0xB0

STATE

STATCEOF STATTBSTATVDVCCSTATUSMSTATVTM STATIPMSTATCM

STATEM

STATCEOFM STATTBMSTATVDVCCM

P[23:0]
TEMP[15:0]

VDVCC[15:0]

IH1[23:0]

IH2[23:0]

ACCICTLACCGPCTL ACCIDB

IH3[23:0]

IH4[23:0]

IH5[23:0]

0xC0
0xD0
0xE0
0xF0

ALERTBCTL

TBCTL

OPCTL

PGCTL
PAGE 10x00

C1TH[47:0]

C1TL[47:0]

0x10

E1H[47:0]

E1TL[47:0]

0x20

C2TH[47:0]

C2TL[47:0]0x30

E2TH[47:0]

E2TL[47:0]

TB1TH[31:0]
TB2TH[31:0]

0x40
0x50
0x60
0x70
0x80

ITH[15:0]

ITL[15:0]

PTH[15:0]

PTL[15:0]0x90

VTH[15:0]

VTL[15:0]

TEMPTH[15:0]

TEMPTL[15:0]

VDVCCTH[15:0]

VDVCCTL[15:0]

TEMPFANH[15:0]

TEMPFANL[15:0]

8

A

C

E

0xA0
0xB0
0xC0
0xD0
0xE0
0xF0

OPCTL
0

PGCTL
1

2

3

4

5

6

7

9

B

D

F

OFFSET

Figure 16. Register Map
2947faFor more information www.linear.com/LTC2947

25

LTC2947
Register Description
Register Naming Conventions
RW
RO
COR
DEF
SI
UI

Read-Write
Read Only
Clear on Read
Default Value
Signed Integer
Unsigned Integer

Paging Mechanism
The memory map of the LTC2947 is organized into two pages, PAGE0 and PAGE1. PAGE0 contains all quantity, control
and status registers while PAGE1 contains all threshold registers. Each page has a register address space ranging from
0x00 to 0xEF, with each register consisting of one 8-bit byte of data. Multiple-byte data is stored with most significant
byte at the lowest address (little-endian). For instance, the MSB C1[47:40] of the quantity C1 is stored at address 0x00
in PAGE0.
Some addresses in the register map are not used and are reserved. Bits in non-reserved registers that are not explicitly described are also reserved. Writing to unused reserved registers or reserved bits in non-reserved registers may
result in unwanted behavior of the LTC2947; writing 0 to reserved bits in non-reserved registers is allowed. Readingof unused registers is generally harmless but will return random data.
Addresses in the range 0xF0 to 0xFF are used to control page access and are common to both pages. These registers(OPCTL (0xF0) and PGCTL (0XFF)) must be written with single byte transactions. Do not write as part of a multiplebyte write.
PAGE Control
The Page Control register (0xFF) selects the active memory page.
Table 4. Page Control PGCTL (0xFF)
BIT

SYMBOL

TYPE

COR

0

PAGE

RW

N

DEFAULT OPERATION
0Memory Map Page Select.
0: PAGE0 of the memory map is selected.
1: PAGE1 of the memory map is selected.

Operation Control
The Operation Control register OPCTL (0xF0) sets the operating mode of the LTC2947, clears its accumulation and tracking registers and resets the part. There are two operating modes, single-shot and continuous, and a shutdown mode.
Table 5. Operation Control OPCTL (0xF0)
BIT

SYMBOL

TYPE

COR

0

SHDN

RW

N

26

DEFAULT OPERATION0

0: Normal operation
1: Shutdown. The LTC2947 will exit shutdown in SPI mode if the pin AD1/CS is pulled low
and in I2C mode if it receives the correct I2C address (programmed at the ADx pins).

2947faFor more information www.linear.com/LTC2947

LTC2947
Register Description
Table 5. Operation Control OPCTL (0xF0) (continued)
BIT

SYMBOLTYPE

COR

DEFAULT OPERATION

1

CLR

RW

N

0

1: Clear. The accumulation and tracking (max/min) registers are cleared: C1, E1, TB1, C2,
E2, TB2, IMAX, IMIN, PMAX, PMIN, VMAX, VMIN, TEMPMAX, TEMPMIN, VDVCCMAX,VDVCCMIN. (Note 11)

2

SSHOT

RW

N

0

1: Single Shot Measurement. A single set of measurements of current, voltage, power,
temperature and VDVCC are performed and the result registers updated. If CONT is set,
it is cleared after completion of any conversion cycle in progress and the single shotmeasurement is executed. SSHOT is cleared after the single measurement cycle iscomplete.

3

CONT

RW

N

0

0: Continuous measurement is disabled
1: Continuous measurement is enabled. Measurement cycles run continuously. Chargeand energy measurements are only active in continuous mode.

7

RST

RW

N

0

Global Reset. When set, the 2947 is reset and all registers are set to their default values.

Note 11: Continuous mode must be disabled to ensure proper behavior of the CLR function. To execute a CLR when continuous mode is active, clear
the CONT bit, wait 100ms and then poll the UPDATE bit in the Status register(0x80)[4] to ensure that all measurement cycles have completed. Once bit
UPDATE is set to 1 by the LTC2947, the master can set bit CLR and CONT can then be re-enabled.

Register Map PAGE0
Table 6. PAGE0 Registry Summary
ADDRESS

NAME

TYPE

COR

DEFAULT

PARAMETER

TABLE

PAGE

Accumulated Results
0x00

C1[47:0]

RW

N

0x00

Charge1

7,8

28

0x06

E1[47:0]

RW

N

0x00

Energy1

7,8

28

0x0C

TB1[31:0]

RW

N

0x00

Time1

7,8

28

0x10

C2[47:0]

RW

N

0x00

Charge2

7,8

28

0x16

E2[47:0]

RW

N

0x00

Energy2

7,8

28

0x1C

TB2TH[31:0]

RW

N

0x00

Time2

7,8

28

IMAX[15:0]RW

N0x8000Maximum Current

1030

Tracking
0x40
0x42IMIN[15:0]

RW

N

0x7FFF

Minimum Current

10

30

0x44

PMAX[15:0]RW

N0x8000Maximum Power

10

30

0x46

PMIN[15:0]

RW

N

0x7FFF

Minimum Power

10

30

0x50

VMAX[15:0]RW

N0x8000Maximum Voltage VD

10

30

0x52

VMIN[15:0]

RW

N

0x7FFF

Minimum Voltage VD

10

30

0x54

TEMPMAX[15:0]RW

N0x8000Maximum Temperature

10

30

0x56

TEMPMIN[15:0]

RW

N

0x7FFF

Minimum Temperature

10

30

0x58

VDVCCMAX[15:0]RW

N0x8000Maximum Voltage at DVCC

10

30

0x5A

VDVCCMIN[15:0]

RW

N

0x7FFF

Minimum Voltage at DVCC

10

30

0x67

GPIOSTATCTL

RW

N

0x00

GPIO Status and Control

11

30

0x80

STATUS

RO

Y

0x0F

Status

17

32

GPIO
Status

2947faFor more information www.linear.com/LTC2947

27

LTC2947
Register Description
Table 6. PAGE0 Registry Summary (continued)
Threshold And Overflow Alerts
0x81

STATVT

RO

Y

0x00

Voltage, Temperature Threshold Alerts

18

33

0x82

STATIP

RO

Y

0x00

Current, Power Threshold Alerts

19

33

0x83

STATC

RO

Y

0x00

Charge Threshold Alerts

20

33

0x84

STATE

RO

Y

0x00

Energy Threshold Alerts

21

34

0x85

STATCEOF

RO

Y

0x00

Charge, Energy Overflow Alerts

22

34

0x86

STATTB

RO

Y

0x00

Timebase Alerts

23

34

0x87

STATVDVCC

RO

Y

0x00

VDVCC Threshold Alerts

24

34

Mask
0x88

STATUSM

RW

N

0x79

Status Mask

25

34

0x89

STATVTM

RW

N

0x3F

Voltage, Temperature Threshold Alert Mask

26

35

0x8A

STATIPM

RW

N

0xF

Current, Power Threshold Alert Mask

27

35

0x8B

STATCM

RW

N

0x3F

Charge Threshold Alerts Mask

28

36

0x8C

STATEM

RW

N

0x3F

Energy Threshold Alerts Mask

29

36

0x8D

STATCEOF

RW

N

0x33

Charge, Energy Overflow Alerts Mask

30

36

0x8E

STATTBM

RW

N

0x33

Timebase Alerts Mask

31

37

0x8F

STATVDVCCM

RW

N

0x03

VDVCC Threshold Alerts Mask

31

37

Non Accumulated Results
0x90

I[23:0]

RO

N

0x00

Current

9

29

0x93

P[23:0]

RO

N

0x00

Power

9

29

0xA0

V[15:0]

RO

N

0x00

Voltage

9

29

0xA2

TEMP[15:0]

RO

N

0x00

Temperature

9

29

0xA4

VDVCC[15:0]

RO

N

0x00

Voltage at DVCC

9

29

0xB0

IH1[23:0]

RO

N

0x00

Current History 1

9

29

0xB3

IH2[23:0]

RO

N

0x00

Current History 2

9

29

0xB6

IH3[23:0]

RO

N

0x00

Current History 3

9

29

0xB9

IH4[23:0]

RO

N

0x00

Current History 4

9

29

0xBC

IH5[23:0]

RO

N

0x00

Current History 5

9

29

0xE1

ACCICTL

RW

N

0x00

Accumulator Control Current Polarity

12

31

Control
0xE3

ACCGPCTL

RW

N

0x00

Accumulator Control GPIO

13

31

0xE4

ACCIDB

RW

N

0x00

Accumulation Deadband

14

31

0xE8

ALERTBCTL

RW

N

0x01

Alert Master Control Enable

15

31

0xE9

TBCTL

RW

N

0x07

Timebase Control

16

32

0xF0

OPCTL

RW

N

0x00

Operation Control

5

25

0xFF

PGCTL

RW

N

0x00

Page Control

4

25

28

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LTC2947
Register Description
Accumulated Result Registers
The registers in Tables 7 and 8 contain two sets of the accumulated quantities charge, energy and time. The time registers are unsigned integer values while the charge and energy registers are two's complement signed integer values.
The value of each accumulated quantity can be determined by multiplying the respective register value with the corresponding LSB value from Tables 7 or 8. If the internal clock or a 4MHz crystal is used as a reference clock, use the
LSB values in Table 7. If an external reference clock is used, calculate the LSB values according to Table 8. The valuesof PRE(0xE9)[2:0] and DIV(0xE9)[7:3] should be set according to the Timebase Control section.
Table 7. Accumulated Results Register Parameters for Use with Crystal or Internal Clock
ADDRESS

NAME

TYPE

COR DEFAULT

0x00

C1[47:0]

RW

N

0x00

PARAMETERLSB (CRYSTAL = 4MHz
OR INTERNAL CLOCK)PRE(CRYSTAL =
4MHz)

DIV
(CRYSTAL =
4MHz)

UNIT

SI/UI

Charge1=C1•LSBC1

LSBC1 = 1.193E-06

2

30

A•s

SI

0x06

E1[47:0]

RW

N

0x00

Energy1=E1•LSBE1

LSBE1 = 19.89E-06

2

30

W•s

SI

0x0C

TB1[31:0]

RW

N

0x00

Time1=TB1•LSBTB1

LSBTB1 = 397.8E-06

2

30

s

UI

0x10

C2[47:0]

RW

N

0x00

Charge2=C2•LSBC2

LSBC2 = 1.193E-06

2

30

A•s

SI

0x16

E2[47:0]

RW

N

0x00

Energy2=E2•LSBE2

LSBE2 = 19.89E-0

2

30

W•s

SI

0x1C

TB2[31:0]

RW

N

0x00

Time2=TB2•LSBTB2LSBTB2 = 397.8E-06

2

30

s

UI

When the internal clock is used, PRE and DIV should be set to their default values which is done by writing 0x07 toregister (0xE9) (see Table 16).
Table 8. Accumulated Results Register Parameters for Use with External Clock
ADDRESS

NAME

TYPE

COR DEFAULTPARAMETERLSB• 2PRE • (DIV+1)

PRE, DIV

UNIT

SI/UI

0x00

C1[47:0]

RW

N

0x00

Charge1=C1•LSBC1

LSBC1 = 0.0385 • 1/fEXT

Note 12

A•s

SI

0x06

E1[47:0]

RW

N

0x00

Energy1=E1•LSBE1

LSBE1 = 0.6416 • 1/fEXT • 2PRE • (DIV+1)

Note 12

W• s

SI

0x0C

TB1[31:0]

RW

N

0x00

Time1=TB1•LSBTB1

LSBTB1 = 12.83 • 1/fEXT • 2PRE • (DIV+1)

Note 12s

UI• 2PRE • (DIV+1)

0x10

C2[47:0]

RW

N

0x00

Charge2=C2•LSBC2

LSBC2 = 0.0385 • 1/fEXT

Note 12

A•s

SI

0x16

E2[47:0]

RW

N

0x00

Energy2=E2•LSBE2

LSBE2 = 0.6416 • 1/fEXT • 2PRE • (DIV+1)

Note 12

W•s

SI

0x1C

TB2[31:0]

RW

N

0x00

Time2=TB2•LSBTB2LSBTB2 = 12.83 • 1/fEXT • 2PRE • (DIV+1)

Note 12s

UI

Note 12: Values of PRE and DIV should be calculated according to Timebase Control section.

For instance, an external clock frequency of 10MHz would require values PRE to be set to 4 and DIV to be set to 19.
With fEXT=10MHz, LSBC1 is calculated as 1.23418E-06A•s. To get the Charge1 value, the register content of C1 ismultiplied with LSBC1. In this case, a C1 register value of 0x7B A2 92 results in a Charge1 value of 10.0A•s. For a C1
register value of 0xFF FF FF 84 5D 6E, the resulting Charge1 is –10.0A•s.
LSB values may be calculated easily using the QuikEval software for the LTC2947.
The registers for charge, energy and time can be preset to a non-zero initial value. All bytes of the respective quantity
should be written in the same multi-byte transaction. For instance, to set a start value of 10.0W•s (assuming an externalreference clock of 10MHz) for Energy1, all 6 bytes 0x00 00 00 07 6B 08 should be written to registers E1(0x06-0x0B)
as one transaction.

2947faFor more information www.linear.com/LTC2947

29

LTC2947
Register Description
Non-Accumulated Result Registers
Registers in Table 9 contain measured values of current, power, voltage, temperature, and VDVCC. All quantities are
represented as two's complement signed integer values.
Current is the current I flowing through pins IP and IM. Voltage is the differential voltage VD across pins VP and VM.
Power is the instantaneous multiplication of voltage VD and current I. Temperature is the temperature of the on-silicontemperature sensor. VDVCC is the voltage across pins DVCC and DGND. The Current History registers store the 5 current readings prior to the most recent reading; Current History 1 is the most recent previous current result, Current
History 2 is the current result prior to Current History 1, and so on.
All measured values are scaled with the LSB values from Table 9. To calculate the physical value of the measured
parameter except for temperature, multiply the register value by the appropriate LSB value. To calculate temperature,
multiply the TEMP register value by 0.204°C and add 5.5°C.
Table 9. Non-Accumulated Results Registers
ADDRESS

NAME

TYPE

COR

DEFAULT PARAMETER

LSB

UNIT

SI/UI

0x90

I[23:0]

RO

N

0x00

Current

3

mA

SI

0x93

P[23:0]

RO

N

0x00

Power

50

mW

SI

0xA0

V[15:0]RO

0xA2

TEMP[15:0]

RO

N

0x00

Voltage

2

mV

SI

N

0x00

Temperature = TEMP • 0.204 + 5.5

–

°C

SI

0xA4

VDVCC[15:0]

RO

N

0xB0

IH1[23:0]

RO

N

0x00

Voltage at DVCC

145

mV

SI

0x00

Current History 1 (prev. result) = I • LSBI

3

mA

SI

0xB3

IH2[23:0]

RO

N

0x00

Current History 2 (prev. result – 1) = I • LSBI

3

mA

SI

0xB6

IH3[23:0]

RO

0xB9

IH4[23:0]

RO

N

0x00

Current History 3 (prev. result – 2) = I • LSBI

3

mA

SI

N

0x00

Current History 4 (prev. result – 3) = I • LSBI

3

mA

SI

0xBC

IH5[23:0]

RO

N

0x00

Current History 5 (prev. result – 4) = I • LSBI

3

mA

SI

For example: Table 9 gives LSBI = 3mA. For an I register value I(0x90-0x92) of 0x00 0B B8, the resulting current is
9.0A. For a register value of 0xFF F4 48, the resulting current is –9.0A.
For a TEMP register value TEMP(0xA2-0xA3) of 0x00 78, the resulting temperature is 30°C. For a register value of
0xFF 52, the resulting temperature is –30°C.
Additional power resolution can be obtained by reading the results of registers V(0xA0-0xA1) and I(0x90-0x92) in one
multi-byte transaction and multiplying them externally in the host. In this case the LSB of the resulting power value is
6µW instead of 50mW. The bandwidth in this mode is significantly reduced.
Tracking Registers
The Tracking registers keep track of the maximum and minimum values of all conversions since the last reset. Valuescaling is done in the same manner as the Non Accumulated Results register values, using LSB values from Table 10.
Negative values are treated as smaller (more minimum) than positive values as the minimum registers are updated.
For example: A register value PMAX(0x44-0x45) of 0x01 F4 indicates a measured maximum power of 500 • 0.2W =100W. A register value PMIN(0x46-0x47) 0xFA 24 indicates a measured minimum power of –1500 • 0.2W = –300W.
The calculation of the other tracked parameter values is done the same way with the corresponding LSB values.

30

2947faFor more information www.linear.com/LTC2947

LTC2947
Register Description
Table 10. Tracking Registers
ADDRESS

NAME

TYPE

COR

DEFAULT PARAMETER

0x40

IMAX[15:0]

0x42

IMIN[15:0]

0x44

PMAX[15:0]

0x46
0x50
0x52

LSB

UNIT

SI/UI

RW

N

0x8000Maximum Current

12

mA

SI

RW

N

0x7FFF

Minimum Current

12

mA

SI

RW

N

0x8000Maximum Power

0.2

W

SI

PMIN[15:0]

RW

N

0x7FFF

Minimum Power

0.2

W

SI

VMAX[15:0]RW

N0x8000Maximum Voltage VD

2

mV

SI

VMIN[15:0]

RW

N

0x7FFF

Minimum Voltage VD

2

mV

SI

0x54

TEMPMAX[15:0]RW

N0x8000Maximum Temperature = TEMPMAX • 0.204 + 5.5

–

°C

SI

0x56

TEMPMIN[15:0]

RW

N

0x7FFF

Minimum Temperature = TEMPMIN • 0.204 + 5.5

–

°C

SI

0x58

VDVCCMAX[15:0]RW

N0x8000Maximum Voltage at DVCC

145

mV

SI

0x5A

VDVCCMIN[15:0]

RW

N

0x7FFF

Minimum Voltage at DVCC

145

mV

SI

Note that the Tracking registers for current and power report only the 16MSBs of the respective 18-bit result registers.
Control Registers
The Control registers control the accumulation of charge, energy and time, configure the GPIO pin, and setup the
timebase if an external clock is used.
For details see the GPIO control section.
Table 11. GPIO Status and Control GPIOSTATCTL(0x67)
BIT

SYMBOL

TYPE

COR

0

GPOEN

RW

N

DEFAULT OPERATION
0Pin GPIO configured as input or output
0: Input
1: Output

4

GPI

RW
(Note 13)N

0This register shows the applied level at pin GPIO
0: Logical level 0 at pin GPIO
1: Logical level 1 at pin GPIO

5

GPO

RW

N

0

This register sets the level at GPIO if set as output provided there is a pull-up resistor
at GPIO
0: Pin GPIO is set to 0 if set as output
1: Pin GPIO is set to 1 if set as output

6

FANEN

RW

N

0

GPIO fan control enable
0: GPIO level controlled by GPO
1: GPIO level controlled by temperature measurement against fan temperaturethreshold high/low registers TEMPFANH (page1.0x9C) and TEMPFANL (page1.0x9E)

7

FANPOL

RW

N

0GPIO polarity if GPIO fan control enable FANEN (bit 6) is enabled
0: GPIO is low active
1: GPIO is high active
GPIO gets active when temperature measurement is higher than TEMPFANH(page1.0x9C). GPIO gets inactive when temperature measurement is lower than
TEMPFANL (page1.0x9E). If temperature measurement is between TEMPFANH and
TEMPFANL, GPIO does not change its level.

Note 13: If GPIO status and control is written and pin GPIO is configured as input, the register reporting bit GPI (0x67)[4] is set/cleared by this byte write.
If the electrical input at pin GPIO is different than the value of the write, the GPI bit is updated after the next operation cycle(100ms(typ)).

2947faFor more information www.linear.com/LTC2947

31

LTC2947
Register Description
The Accumulator Control Current Polarity register sets the polarity of current that is accumulated to calculate chargeand energy. For example, one set of registers (e.g. Charge1, Energy1) can be configured to accumulate the total chargeand energy, and the second set (e.g. Charge2 and Energy2) to only accumulate the negative charge and energy. This
allows a system to keep track of total charge as well as charge into a battery, for example.
Table 12. Accumulator Control Current Polarity ACCICTL(0xE1)
BIT

SYMBOL

TYPE

COR

[1:0]

ACC1I[1:0]

RW

N

DEFAULT OPERATION
00

[3:2]

ACC2I[1:0]

RW

N

00

Accumulation control of Charge1/Charge2 and Energy1/Energy2 by current polarity
00: Accumulation takes place always
01: Only if the current is positive
10: Only if the current is negative
11: No accumulation takes place

The Accumulator Control GPIO register allows the GPIO pin to enable or disable the accumulated results registers.
Table 13. Accumulator Control GPIO ACCGPCTL(0xE3)
BIT

SYMBOL

TYPE

COR

[1:0]

ACC1GP[1:0]

RW

N

DEFAULT OPERATION
00

[3:2]

ACC2GP[1:0]

RW

N

00

Accumulation control of Charge1/Charge2, Energy1/Energy2 and TIME1/TIME2 by pin GPIO
00: Accumulation takes place always
01: Only if pin GPIO is 1
10: Only if pin GPIO is 0
11: Reserved

The Accumulation Dead Band register allows to set the level of current below which no accumulation takes place.
Table 14. Accumulation Deadband ACCIDB(0xE4)
BIT

SYMBOL

TYPE

COR

[7:0]

ACCIDB

RWN

DEFAULT OPERATION
0

Deadband current for accumulation
If the absolute current value is higher than or equal this value, accumulationof Charge1/Charge2 and Energy1/Energy2 and comparison to their respective
threshold takes place. If lower, Charge1/Charge2 and Energy1/Energy2 values are
not accumulated and there is no comparison against thresholds.
Unit is the same as LSB of current I(0x90): 3mA

The Alert Master Control Enable register allows the general enabling/disabling of the pin alert.
Table 15. Alert Master Control Enable ALERTBCTL(0xE8)
BIT

SYMBOLTYPE

COR

DEFAULT0

ALERTBEN

RWN

1OPERATION
0: Unmasked alerts (see MASK registers) are not forwarded to ALERT pin
1: Unmasked alerts (see MASK registers) are forwarded to ALERT pin.

The Time Base Control register selects between the internal and an external reference clock, and sets the time baseparameters when an external reference clock is used. Set PRE[2:0] = 111b or 0x07 (default) to enable the internalreference clock. To use an external reference clock, set the values of PRE[2:0] and DIV[4:0] according to the external
clock frequency; see the TimeBase: Internal/External Clock/Crystal section.

32

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LTC2947
Register Description
Table 16. Timebase Control TBCTL (0xE9), DEFAULT VALUE: 0x07
BIT

SYMBOLTYPE

COR

DEFAULT0

PRE[0]RW

N

1

OPERATION (Note 14)
Prescaler value bit 0, binary coded1

PRE[1]RW

N

1

Prescaler value bit 1, binary coded2

PRE[2]RW

N

1

Prescaler value bit 2, binary coded3

DIV[0]RW

N

0

Divider value bit 0, binary coded4

DIV[1]RW

N

0

Divider value bit 1, binary coded5

DIV[2]RW

N

0

Divider value bit 2, binary coded6

DIV[3]RW

N

0

Divider value bit 3, binary coded7

DIV[4]RW

N

0

Divider value bit 4, binary coded

Note 14: For switching between internal and external clock the LTC2947 must be in Idle Mode.

Status Register
The Status register reports the status of register updates, undervoltage lockout, and reference clock errors. On powerup, all undervoltage lockouts and the power-on reset bits [3:0] are set to 1. After exit from shutdown, bits UVLOA[0]and UVLOD[3] are set, all other bits are cleared and ALERT is released if the reason of being asserted before shutdown
were only bits UVLOAO[0] and UVLOD[3]. This allows the system to distinguish between these two cases. In bothcases, the bits can be cleared by reading the Status register. After they are cleared, the undervoltage registers and
PORA are set again if an undervoltage event occurs at the AVCC/DVCC supply pins. Events can also trigger the ALERT
pin if enabled in the Alert Master Control Enable register(0xE8) and the Status Mask register(0x88).
Bit[4] UPDATE is set to 1 when the LTC2947 has finished a measurement cycle and updated the Result registers,
the Accumulation registers, and the Tracking registers. Measurement completion can be observed by polling bit[4]UPDATE or by using the alert mechanism via the ALERT pin. In case Threshold and Overflow Alert registers (0x81 to0x87) are configured and used, the Status (0x80) and all Alert registers (0x81 to 0x87) must be read in one multi-bytetransaction. This includes the above described polling of the UPDATE bit.
Bit[5] ADCERR is set to 1 if the supply voltage at AVCC is too low for proper operation of the ADCs. The values in the
result registers are not valid and should be discarded if ADCERR is set.
Bit[6] TBERR is set to 1 if the internal time base overflows. This indicates an incorrect setting of the values PRE andDIV with respect to the external clock at CLKI. The values of Accumulated Results registers should be discarded if
TBERR is set.
Table 17. Status STATUS (0x80)
BIT

SYMBOLTYPE

COR DEFAULT OPERATION

0

UVLOA

RO

Y

1

1: Undervoltage in the analog domain including ADCs during a conversion

1

PORA

RO

Y

1

1: Power-on reset has occurred due to undervoltage in the analog domain

2

UVLOSTBYRO

Y

1

1: Undervoltage in the standby domain

3

UVLOD

RO

Y

1

1: Undervoltage in the digital domain

4

UPDATERO

Y

0

1: Result registers have been updated

5

ADCERRROY

0

1: The ADC conversion is not valid due to undervoltage during a conversion

6

TBERR

RO

Y

0

1: Overflow of the internal timebase register. The values of accumulated result registers are invalid

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33

LTC2947
Register Description
Threshold and Overflow Alert Registers
Threshold and Overflow Alert registers are set when the respective threshold values are exceeded or when registers
overflow. Thresholds are set in the Threshold Registers section.
The accumulated quantities are continuously checked against guard values to warn that a register is nearing overflow,
nominally set to 90% of each register’s maximum value. When any quantity crosses its guard threshold, the LTC2947
sets the corresponding overflow bit in the Status register, generates an alert (if enabled) and then continues accumulation. At the maximum current and voltage inputs, rollover typically happens several hours after an overflow alert issignaled, allowing the host time to take action to avoid data loss. The overflow threshold for 32-bit quantities (time)
is 0xE6 66 66 65 LSB, the one for 48-bit quantities (charge, energy) is ±73 33 33 33 33 32 LSB.
The threshold and overflow comparators for accumulated quantities charge, energy and time use a floating point format
internally. This can appear to cause slight bit-level comparison discrepancies, but the comparisons between Accumulated Result registers and their respective Threshold registers will always have an accuracy of better than 0.001%.
An alert condition needs to be present for at least 200ms to be reported by the Alert registers (0x81 to 0x87).
When Threshold and Overflow Alert registers (0x81 to 0x87) are configured and used, the Status (0x80) and all Alertregisters (0x81 to 0x87) must be read in one multi-byte transaction.
Table 18. Voltage, Temperature Threshold Alerts STATVT (0x81)
BIT

SYMBOLTYPE

COR

DEFAULT

0

VH

RO

Y

0

1: Voltage VD high threshold exceeded

OPERATION

1

VL

RO

Y

0

1: Voltage VD low threshold exceeded

2

TEMPH

RO

Y

0

1: Temperature high threshold exceeded

3

TEMPL

RO

Y

0

1: Temperature low threshold exceeded

4

FANH

RO

Y

0

1: Fan high temperature threshold exceeded

5

FANL

RO

Y

0

1: Fan low temperature threshold exceeded

Table 19. Current, Power Threshold Alerts STATIP (0x82)
BIT

SYMBOLTYPE

COR

DEFAULT

0

IH

RO

Y

0

OPERATION
1: Current high threshold exceeded

1

IL

RO

Y

0

1: Current low threshold exceeded

2

PH

RO

Y

0

1: Power high threshold exceeded

3

PL

RO

Y

0

1: Power low threshold exceeded

Table 20. Charge Threshold Alerts STATC (0x83)
BIT

SYMBOLTYPE

COR

DEFAULT

0

C1H

RO

Y

0

1: Charge1 high threshold exceeded

1

C1L

RO

Y

0

1: Charge1 low threshold exceeded

2

C2H

RO

Y

0

1: Charge2 high threshold exceeded

3

C2L

RO

Y

0

1: Charge2 low threshold exceeded

34

OPERATION

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LTC2947
Register Description
Table 21. Energy Threshold Alerts STATE (0x84)
BIT

SYMBOLTYPE

COR

DEFAULTOPERATION

0

E1H

RO

Y

0

1: Energy1 high threshold exceeded

1

E1L

RO

Y

0

1: Energy1 low threshold exceeded

2

E2H

RO

Y

0

1: Energy2 high threshold exceeded

3

E2L

RO

Y

0

1: Energy2 low threshold exceeded

Table 22. Charge, Energy Overflow Alerts STATCEOF (0x85)
BIT

SYMBOLTYPE

COR

DEFAULTOPERATION

0

C1OF

RO

Y

0

1: Charge1 overflow alert

1

C2OF

RO

Y

0

1: Charge2 overflow alert

4

E1OF

RO

Y

0

1: Energy1 overflow alert

5

E2OF

RO

Y

0

1: Energy2 overflow alert

Table 23. Time Base Alerts STATTB (0x86)
BIT

SYMBOLTYPE

COR

DEFAULTOPERATION

0

TB1TH

RO

Y

0

1: Time1 threshold exceeded

1

TB2TH

RO

Y

0

1: Time2 threshold exceeded

4

TB1OF

RO

Y

0

1: Time1 overflow

5

TB2OF

RO

Y

0

1: Time2 overflow

Table 24. VDVCC Threshold Alerts STATVDVCC (0x87)
BIT

SYMBOLTYPE

COR

DEFAULT0VDVCCHRO

Y

0

OPERATION
1: Voltage at DVCC high threshold exceeded

1

VDVCCLRO

Y

0

1: Voltage at DVCC low threshold exceeded

Mask Registers
The Mask registers allow control of which alerts trigger the ALERT pin. If a Mask register bit is reset to 0, exceeding of the respective threshold causes the ALERT pin to pull low if ALERTBEN in the Alert Master Control Enable
ALERTBCTL(0xE8) register is set to 1.
When a bit of the Status Mask register STATUSM is set to 0, the corresponding bits of register STATUS (0x80) will
generate an alert.
For example, when the UPDATEM bit in Status Mask register(0x88) is reset to 0 and the ALERTBEN bit in the
ALERTBCTL(0xE8) register is set, every update of the result registers will cause the ALERT pin to pull low.
Table 25. Status Mask STATUSM(0x88), DEFAULT VALUE 0x79
BIT

SYMBOLTYPE

COR

DEFAULT0UVLOAM

RW

N

1

Mask UVLOA of STATUS(0x80)
0: Mask disabled
1: Mask enabled

OPERATION

3

UVLODM

RW

N

1

Mask UVLOD of STATUS(0x80)
0: Mask disabled
1: Mask enabled
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35

LTC2947
Register Description
Table 25. Status Mask STATUSM(0x88), DEFAULT VALUE 0x79 (continued)
4

UPDATEM

RW

N

1

Mask UPDATE of STATUS(0x80)
0: Mask disabled
1: Mask enabled

5

ADCERRM

RW

N

1

Mask ADCERR of STATUS(0x80)
0: Mask disabled
1: Mask enabled

6

TBCERRM

RW

N

1

Mask TBCERR of STATUS(0x80)
0: Mask disabled
1: Mask enabled

When bits of STATVTM are set to 0, corresponding bits of register STATVT (0x81) generate an alert.
Table 26. Voltage, Temperature Threshold Alert Mask STATVTM(0x89), DEFAULT VALUE 0x3F
BIT

SYMBOLTYPE

COR

DEFAULT

0

VHM

RW

N

1

1

VLM

RW

N

1

2

TEMPHM

RW

N

1

3

TEMPLM

RW

N

1

4

FANHM

RW

N

1

5

FANLM

RW

N

1

OPERATION
Mask VH of STATVT(0x81)
0: Mask disabled
1: Mask enabled
Mask VL of STATVT(0x81)
0: Mask disabled
1: Mask enabled
Mask TEMPH of STATVT(0x81)
0: Mask disabled
1: Mask enabled
Mask TEMPL of STATVT(0x81)
0: Mask disabled
1: Mask enabled
Mask FANH of STATVT(0x81)
0: Mask disabled
1: Mask enabled
Mask FANL of STATVT(0x81)
0: Mask disabled
1: Mask enabled

When bits from STATIPM are set to 0, bits from register STATIP(0x82) generate an alert.
Table 27. Current, Power Threshold Alert Mask STATIPM(0x8A), DEFAULT VALUE 0xF
BIT0

SYMBOL
IHM

TYPE
RW

COR
N

DEFAULT
1

1

ILM

RW

N

1

2

PHM

RW

N

1

3

PLM

RW

N

1

36

OPERATION
Mask IH of STATIP(0x82)
0: Mask disabled
1: Mask enabled
Mask IL of STATIP(0x82)
0: Mask disabled
1: Mask enabled
Mask PH of STATIP(0x82)
0: Mask disabled
1: Mask enabled
Mask PL of STATIP(0x82)
0: Mask disabled
1: Mask enabled

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LTC2947
Register Description
When bits from STATCM are set to 0, bits from register STATC(0x83) generate an alert.
Table 28. Charge Threshold Alerts Mask STATCM(0x8B), DEFAULT VALUE 0x3F
BIT
0SYMBOL
C1HM

TYPE
RW

COR
N

DEFAULT
1

1

C1LM

RW

N

1

2

C2HM

RW

N

1

3

C2LM

RW

N

1

OPERATION
Mask C1H of STATC(0x83)
0: Mask disabled
1: Mask enabled
Mask C1L of STATC(0x83)
0: Mask disabled
1: Mask enabled
Mask C2H of STATC(0x83)
0: Mask disabled
1: Mask enabled
Mask C2L of STATC(0x83)
0: Mask disabled
1: Mask enabled

When bits from STATEM are set to 0, bits from register STATE(0x84) generate an alert.
Table 29. Energy Threshold Alerts Mask STATEM(0x8C), DEFAULT VALUE 0x3F
BIT
0SYMBOL
E1HM

TYPE
RW

COR
N

DEFAULT
1

1

E1LM

RW

N

1

2

E2HM

RW

N

1

3

E2LM

RW

N

1

OPERATION
Mask E1H of STATE(0x84)
0: Mask disabled
1: Mask enabled
Mask E1L of STATE(0x84)
0: Mask disabled
1: Mask enabled
Mask E2H of STATE(0x84)
0: Mask disabled
1: Mask enabled
Mask E2L of STATE(0x84)
0: Mask disabled
1: Mask enabled

When bits from STATCEOFM are set to 0, bits from register STATCEOF(0x85) generate an alert.
Table 30. Charge, Energy Overflow Alerts Mask STATCEOFM(0x8D), DEFAULT VALUE 0x33
BIT

SYMBOLTYPE

COR

DEFAULT

0

C1OFM

RW

N

1

1

C2OFM

RW

N

1

2

E1OFM

RW

N

1

3

E2OFM

RW

N

1

OPERATION
Mask C1OF of STATCEOF(0x85)
0: Mask disabled
1: Mask enabled
Mask C2OF of STATCEOF(0x85)
0: Mask disabled
1: Mask enabled
Mask E1OF of STATCEOF(0x85)
0: Mask disabled
1: Mask enabled
Mask E2OF of STATCEOF(0x85)
0: Mask disabled
1: Mask enabled

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37

LTC2947
Register Description
When bits from STATTBM are set to 0, bits from register STATTB(0x86) generate an alert.
Table 31. Timebase Alerts Mask STATTBM(0x8E), DEFAULT VALUE 0x33
BIT

SYMBOLTYPE

COR

DEFAULTOPERATION

0

TB1THM

RW

N

1

Mask TB1TH of STATTB(0x86)
0: Mask disabled
1: Mask enabled

1

TB2THM

RW

N

1

Mask TB2TH of STATTB(0x86)
0: Mask disabled
1: Mask enabled

4

TB1OFM

RW

N

1

Mask TB1OF of STATTB(0x86)
0: Mask disabled
1: Mask enabled

5

TB2OFM

RW

N

1

Mask TB2OF of STATTB(0x86)
0: Mask disabled
1: Mask enabled

When bits from STATDVCCM are set to 0, bits from register STATDVCC(0x87) generate an alert.
Table 32. VDVCC Threshold Alerts Mask STATVDVCCM(0x8F), DEFAULT VALUE 0x3
BIT

SYMBOLTYPE

COR

DEFAULT0VDVCCHM

RW

N

1

Mask TB1TH of STATVDVCC(0x87)
0: Mask disabled
1: Mask enabled

OPERATION

1VDVCCLM

RW

N

1

Mask TB1TH of STATVDVCC(0x87)
0: Mask disabled
1: Mask enabled

Register Map PAGE1
Threshold Registers
The Threshold registers set threshold values for each measured quantity. When a measured value exceeds its threshold,an alert is triggered and the corresponding bits in the Threshold and Overflow Alert registers(0x81 to 0x87) are set.
When enabled in the Alert Master Control Enable register ALERTBCTL(0xE8) and the Mask registers(0x88 to 0x8F),
the ALERT pin is also pulled low.
Value scaling is done in the same manner as in the corresponding Result register values, using LSB values from Table 33.
Table 33. Threshold Registers
ADDRESS

NAME

TYPE

COR

DEFAULT

PARAMETER

Page1.0x00

C1TH[47:0]RW

N

0x7F FF FF FF FF FF

Charge1 threshold high

LSB

UNIT

see C1 (0x00)

A•s

Page1.0x06

C1TL[47:0]

RW

N

0x80 00 00 00 00 00

Charge1 threshold low

see C1 (0x00)

A•s

Page1.0x0C

TB1TH[31:0]

RW

N

0xFF FF FF FF

Time1 threshold highsee TB1 (0x0C)s

Page1.0x10

E1TH[47:0]RW

N

0x7F FF FF FF FF FF

Energy1 threshold highsee E1 (0x06)

W•s

Page1.0x16

E1TL[47:0]

RW

N

0x80 00 00 00 00

Energy1 threshold low

see E1 (0x06)

W•s

Page1.0x20

C2TH[47:0]RW

N

0x7F FF FF FF FF FF

Charge2 threshold highsee C2 (0x10)

A•s

38

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LTC2947
Register Description
Table 33. Threshold Registers (continued)
ADDRESS

NAME

TYPE

COR

DEFAULTPage1.0x26

C2TL[47:0]

RW

N

0x80 00 00 00 00 00

Page1.0x2C

TB2TH[31:0]

RW

N

Page1.0x30

E2TH[47:0]

RW

N

PARAMETER

LSB

UNIT

Charge2 threshold low

see C2 (0x10)

A•s

0xFF FF FF FF

Time2 threshold highsee TB2 (0x1C)

s

0x7F FF FF FF FF FF

Energy2 threshold highsee E2 (0x16)

W•s

Page1.0x36

E2TL[47:0]

RW

N

0x80 00 00 00 00 00

Energy2 threshold low

see E2 (0x16)

W•s

Page1.0x80

ITH[15:0]RW

N

0x7F FF

Current threshold high

0.012

A

Page1.0x82

ITL[15:0]RW

N

0x80 00

Current threshold low

0.012

A

Page1.0x84

PTH[15:0]RW

N

0x7F FFPower threshold high0.2

W

Page1.0x86

PTL[15:0]RW

N

0x80 00

Power threshold low

0.2

W

Page1.0x90

VTH[15:0]RW

N

0x7F FFV threshold high2

mV

Page1.0x92

VTL[15:0]RW

N

0x80 00

V threshold low

2

mV

Page1.0x94

TEMPTH[15:0]

RW

N

0x7F FF

Temperature threshold high =TEMPTH • 0.204 + 5.5°C

Page1.0x96

TEMPTL[15:0]

RW

N0x80 00

Temperature threshold low =TEMPTL • 0.204 + 5.5°C

Page1.0x98

VDVCCTH[15:0]

RW

N

0X7F FFVDVCC threshold high

145

mV

Page1.0x9A

VDVCCTL[15:0]

RW

N

0X80 00

VDVCC threshold low

145

mV

Page1.0x9C

TEMPFANH[15:0]

RW

N

0x7F FFFan temperature threshold high =TEMPFANH • 0.204 + 5.5°C

Page1.0x9E

TEMPFANL[15:0]

RW

N0x80 00

Fan temperature threshold low =TEMPFANL • 0.204 + 5.5°C

The threshold comparators for accumulated quantities charge, energy and time use a floating point format internally.
This can appear to cause slight bit-level comparison discrepancies, but the comparisons between Accumulated Results
registers and their respective threshold registers will always have an accuracy of better than 0.001%.
Note that the threshold registers for current and power report only the 16 MSBs of the respective 18-bit result registers.

2947faFor more information www.linear.com/LTC2947

39

LTC2947
Typical Applications
C2
0.1µF

C1
1µF

CFP
IP
AVCC

VIN 12VIIN –30A to 30A
C7
1µF

C3
0.1µF

CFM

LTC2947
AGND

OVDD
DGND

C10
1µF

SCL
SDI
SDO
ALERT
GPIO
CLKO

BYP
AD1
AD0
CLKI
X1

C11
33pF

R1
22Ω

VP
VM

DVCC

C8
1µF

IM

C4
R2
2.2µF 22Ω

LOAD
3.3V

C9
1µF

R4
2k

R5
2k

R7
2k

VDD
SCL
SDA µP
INT GND

I2C
INTERFACE

C12
33pF

X1: ABLS2-4.000MHZ-D4Y-T2947 F17

Figure 17. 12V, 30A Bidirectional Power, Energy and Charge Monitor with I2C Interface and High Side Sense

40

2947faFor more information www.linear.com/LTC2947

LTC2947
Typical Applications
C2
0.1µF

VIN 48V

IP

R1
22Ω

IIN –30A to 30A
R10
1091Ω

R2
22Ω

C3
0.1µF

C1
1µF

CFP

CFM

3.3V

OVDD

VP
C4
2.2µF

VOUT

IM
R7
2k

R6
2k

C9
1µF

LTC2947

Z1*

VDD

M1
BSP135
R12
60k

PNP
Q1
2N6520R13
10k

ACPL-064L

SDA

3.3V

AGND

µP
MC74VHC1G07

SDO
CLKO
ACPL-064L

ALERT
BYP

FGND
R14
100Ω

R5
1k

SCL

DVCC
AVCC

DGND
AD1
AD0
GPIO
CLKI

Q2
2N3904

R4
1k

SCL
SDI

C7
1µF

R9
0.47k

VM

R11
12k

C8
1µF

R8
0.47k

INT

GND

C10
1µF

M2
BSP135Q3
2N3904*DDZ9689, 5.1V, DIODES INC.
2947 F18

Figure 18. 48V Bidirectional Power, Energy and Charge Monitor with Isolated I2C Interface and High Side Sense

2947faFor more information www.linear.com/LTC2947

41

LTC2947
Package Description

Please refer to http://www.linear.com/product/LTC2947#packaging for the most recent package drawings.
UFE Package
Package
UFE
Variation:
Variation: UFE32MA
UFE32MA
32-LeadPlastic QFNQFN (4mm
32-Lead Plastic(4mm ××6mm)
6mm)(ReferenceLTC
LTC DWG
DWG ## 05-08-1938(Reference
05-08-1938Rev
RevB)B)
1.5
REF
0.70 ±0.05

4.50 ±0.05

2.70 ±0.05

3.10 ±0.05

2.50 REF

1.70 ±0.05

PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC

2.55 ±0.05
3.25 ±0.05
4.50 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONSAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

4.00 ±0.10

0.75 ±0.05

R = 0.125 TYP
27

32
1

26

PIN 1
TOP MARK(NOTE 6)2.70 ±0.10
1.40 ±0.102.75 ±0.10

1.0 REF
4.50 REF

6.00 ±0.10

0.35 ±0.10

1.5 REF

1.70 ±0.102.70 ±0.10

0.28

10
0.40 ±0.10

0.200 REF

0.25 ±0.05

0.00 – 0.05

0.50 BSC(UFE32MA) QFN 0516 REV B

2.50 REF
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATIONON THE TOP AND BOTTOM OF PACKAGE

42

2947faFor more information www.linear.com/LTC2947

LTC2947
Revision History
REV

DATE

DESCRIPTION

A

02/17

Modified OVDD pin description.

PAGE NUMBER
102947faInformation furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnectionof its circuits
as describedherein will not infringe on existing patent rights.
For more
informationwww.linear.com/LTC2947

43

LTC2947
Typical Application
12V, 30A Bidirectional Power, Energy and Charge Monitor with SPI Interface

C2
0.1µF

C1
1µF

CFP

VIN 12V

C3
0.1µF

CFM

IP

IIN –30A to 30A

IM

R1
22Ω

AVCC
C7
1µF

LTC2947

VP

AGND
VM
C8
1µF

C10
1µF

C4
R2
2.2µF 22Ω

LOAD
3.3V

DVCC
OVDD
AD0

DGND
BYP
ALERT

C9
1µF

R3
2k

SCL
SDI
SDO
AD1/CS
GPIO

CLKI

CLKO

10MHz CLOCK

VDD
SCLK
MOSI µP
MISO
CS
GND

SPI
INTERFACE
2947 TA02

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2.9V to 15V Operation, 4mΩ MOSFET Including RSENSE

1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2947(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2947

2947faLT 0217 REV A • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2016