Low Noise, Low Drift, Low Power,
3-Axis MEMS Accelerometers
ADXL356/ADXL357

Data SheetFEATURESFUNCTIONAL BLOCK DIAGRAMSV1P8DIG

V1P8ANALDO

VSUPPLY

RANGE

POWER
MANAGEMENT

LDO

XOUT

Y
X

ANALOGFILTER

YOUT

ST1

Z

3-AXISSENSORZOUTTEMP
SENSORADXL356
VSSIO

ST2
STBY
VDDIO
15429-001

TEMP

CONTROLLOGIC

VSS

Figure 1. ADXL356
V1P8ANALDO

VSUPPLY

V1P8DIG

LDO

VDDIO

ADXL357

POWER
MANAGEMENT

ADC

Y
X
Z

3-AXISSENSORANALOGFILTERADC

DIGITALFILTERCONTROL
LOGIC

ADC
TEMP
SENSOR

ADC

FIFO

VSSIO

VSS

SERIAL
I/O

INT1
INT2
DRDY
CS/SCL
SCLK/VSSIOMOSI/SDAMISO/ASEL

15429-002

Hermetic package offers excellent long-term stability
0 g offset vs. temperature (all axes): 0.75 mg/°C maximum
Ultralow noise density (all axes): 80 µg/√Hz
Low power, VSUPPLY (LDO enabled)
ADXL356 in measurement mode: 150 µA
ADXL357 in measurement mode: 200 µA
ADXL356/ADXL357 in standby mode: 21 µA
ADXL356 has user adjustable analog output bandwidth
ADXL357 digital output features
Digital serial peripheral interface (SPI)/limited I2C
interfaces supported
20-bit analog-to-digital converter (ADC)
Data interpolation routine for synchronous sampling
Programmable high- and low-pass digital filters
Integrated temperature sensor
Voltage range options
VSUPPLY with internal regulators: 2.25 V to 3.6 V
V1P8ANA, V1P8DIG with internal low dropout (LDO) regulator
bypassed: 1.8 V typical ± 10%
Operating temperature range: −40°C to +125°C
14-terminal, 6 mm × 5.6 mm × 2.05 mm, LCC package, 0.26 g

Figure 2. ADXL357

APPLICATIONSInertial measurement units (IMUs)/altitude and headingreference systems (AHRSs)
Platform stabilization systems
Structural health monitoring
Seismic imaging
Tilt sensing
Robotics
Condition monitoring

GENERAL DESCRIPTION
The analog output ADXL356 and the digital output ADXL357
are low noise density, low 0 g offset drift, low power, 3-axis
accelerometers with selectable measurement ranges. The
ADXL356B supports the ±10 g and ±20 g ranges, theADXL356C supports the ±10 g and ±40 g ranges, and the
ADXL357 supports the ±10.24 g, ±20.48 g, and ±40.96 g ranges.
The ADXL356/ADXL357 offer industry leading noise, minimal
offset drift over temperature, and long-term stability, enabling
precision applications with minimal calibration.

1

The low drift, low noise, and low power ADXL357 enables
accurate tilt measurement in an environment with highvibration, such as airborne IMUs. The low noise of the
ADXL356 over higher frequencies is ideal for wireless condition
monitoring.
The ADXL357 multifunction pin names may be referenced onlyby their relevant function for either the SPI or limited I2C
interface.

Protected by U.S. Patents 8,472,270; 9,041,462; 8,665,627; 8,917,099; 6,892,576; 9,297,825; and 7,956,621.

Rev. 0Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or otherrights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700©2017 Analog Devices, Inc. All rights reserved.
www.analog.com
Technical Support

ADXL356/ADXL357

Data SheetTABLE OF CONTENTS
Features .............................................................................................. 1

FIFO_FULL................................................................................. 29

Applications ....................................................................................... 1

FIFO_OVR .................................................................................. 29

Functional Block Diagrams ............................................................. 1

Activity ......................................................................................... 29

General Description ......................................................................... 1

External Synchronization and Interpolation .......................... 29

Revision History ............................................................................... 2

ADXL357 Register Map ................................................................. 32

Specifications..................................................................................... 3

Register Definitions........................................................................ 33

Analog Output for the ADXL356 ............................................... 3

Analog Devices ID Register ...................................................... 33

Digital Output for the ADXL357................................................ 4

Analog Devices MEMS ID Register......................................... 33

SPI Digital Interface Characteristics for the ADXL357........... 6

Device ID Register ..................................................................... 332

I C Digital Interface Characteristics for the ADXL357 ........... 7

Product Revision ID Register ................................................... 33

Absolute Maximum Ratings ............................................................ 8

Status Register ............................................................................. 33

Thermal Resistance ...................................................................... 8

FIFO Entries Register ................................................................ 34

Recommended Soldering Profile ............................................... 8

Temperature Data Registers ...................................................... 34

ESD Caution .................................................................................. 8

X-Axis Data Registers ................................................................ 34

Pin Configurations and Function Descriptions ........................... 9Y-Axis Data Registers ................................................................ 35

Typical Performance Characteristics ........................................... 11

Z-Axis Data Registers ................................................................ 35

Root Allan Variance (RAV) ADXL357 Characteristics ......... 19

FIFO Access Register ................................................................. 36

Theory of Operation ...................................................................... 20

X-Axis Offset Trim Registers .................................................... 36

Applications Information .............................................................. 21

Y-Axis Offset Trim Registers .................................................... 36

Analog Output ............................................................................ 21

Z-Axis Offset Trim Registers .................................................... 37

Digital Output ............................................................................. 21

Activity Enable Register ............................................................ 37

Axes of Acceleration Sensitivity ............................................... 22

Activity Threshold Registers ..................................................... 37

Power Sequencing ...................................................................... 22

Activity Count Register ............................................................. 37

Power Supply Description ......................................................... 22

Filter Settings Register ............................................................... 38

Overrange Protection................................................................. 22

FIFO Samples Register .............................................................. 38

Self Test ........................................................................................ 22

Interrupt Pin (INTx) Function Map Register ........................ 38

Filter ............................................................................................. 23

Data Synchronization ................................................................ 39

Serial Communications ................................................................. 25

I2C Speed, Interrupt Polarity, and Range Register ................. 39

SPI Protocol ................................................................................. 25

Power Control Register.............................................................. 39

2

I C Protocol ................................................................................. 26

Self Test Register ......................................................................... 40

Reading Acceleration or Temperature Data from the Interface....................................................................................................... 26

Reset Register .............................................................................. 40
PCB Footprint Pattern ................................................................... 41

FIFO ................................................................................................. 28

Outline Dimensions ....................................................................... 42

Interrupts ......................................................................................... 29

Ordering Guide .......................................................................... 42

DATA_RDY................................................................................. 29
DRDY Pin .................................................................................... 29

REVISION HISTORY
2/2017—Revision 0: Initial Version

Rev. 0 | Page 2 of 42

Data SheetADXL356/ADXL357

SPECIFICATIONSANALOG OUTPUT FOR THE ADXL356
TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 g, z-axis acceleration = 1 g, and full-scale range = ±10 g, unlessotherwise noted.
Table 1.
Parameter
SENSOR INPUT
Output Full-Scale Range (FSR)
Resonant Frequency1
Nonlinearity
Cross Axis Sensitivity
SENSITIVITY
Sensitivity at XOUT, YOUT, ZOUT

Sensitivity Change due to Temperature
0 g OFFSET
0 g Output for XOUT, YOUT, ZOUT
0 g Offset vs. Temperature (X-Axis, Y-Axis, and Z-Axis)2
Vibration Rectification Error (VRE)3
NOISE DENSITY
X-Axis, Y-Axis, and Z-Axis
Velocity Random WalkBANDWIDTH
Internal Low-Pass Filter Frequency
SELF TEST
Output Change
Z-AxisPOWER SUPPLY
Voltage Range
VSUPPLY4VDDIO
V1P8ANA, V1P8DIG with Internal Low Dropout
Regulator (LDO) Bypassed
Current
Measurement ModeVSUPPLY (LDO Enabled)
V1P8ANA (LDO Disabled)
V1P8DIG (LDO Disabled)Standby ModeVSUPPLY (LDO Enabled)
V1P8ANA (LDO Disabled)
V1P8DIG (LDO Disabled)
Turn On Time5OUTPUT AMPLIFIER
Swing

Test Conditions/Comments
Each axis
ADXL356B, supports two ranges
ADXL356C, supports two ranges

Min

Max

Unit
g
g
kHz
%
%

±10/±20±10/±40
5.5
0.1
1

±10 g
Ratiometric to V1P8ANA
±10 g
±20 g
±40 g
TA = −40°C to +125°C
Each axis, ±10 g
Referred to V1P8ANA/2
TA = −40°C to +125°C
Offset due to 7.5 g rms vibration,±10 g range, in a 1 g orientation
±10 g

Typ

73.6
36.8
18.4

80
40
20
±0.01

86.4
43.2
21.6

mV/g
mV/g
mV/g
%/°C

−375
−0.75

±125
±0.5
<0.1

+375
+0.75

mg
mg/°C
g

80
45
65

µg/√Hzµm/sec/√Hrµm/sec/√Hr

Fixed frequency, 50% response
attenuation

1500

Hz

±10 g range

1.25

g

X-axis and y-axis
Z-axisVSUPPLY = 0 V

2.25
V1P8DIG1.62

10 g range
Power-off to standby
No loadOutput Series Resistance

2.5
2.5
1.8

V
V
V

150
138
12

µA
µA
µA

21
7
10
<10
<10

µA
µA
µA
ms
ms

0.03

V1P8ANA −0.03
32Rev. 0 | Page 3 of 42

3.6
3.6
1.98

V
kΩ

ADXL356/ADXL357
Parameter
TEMPERATURE SENSOR
Output at 25°C
Scale Factor
TEMPERATURE
Operating Temperature Range

Data Sheet
Test Conditions/Comments

Min

Typ

Max

892.2
3.0
−40

Unit
mV
mV/°C

+125

°C

1

The resonant frequency is a sensor characteristic. An integrated analog 1.5 kHz (−6 dB) sinc low-pass filter that cannot be bypassed limits the actual output response.
The temperature change is −40°C to +25°C or +25°C to +125°C.
The VRE measurement is the shift in dc offset while the device is subject to 12.5 g rms of random vibration from 50 Hz to 2 kHz. The device under test (DUT) is
configured for the ±10 g range and an output data rate of 4 kHz. The VRE scales with the range setting.
4
When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS.
5
Standby to measurement mode; valid when the output is within 5 mg of the final value.
2
3

DIGITAL OUTPUT FOR THE ADXL357
TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 g, z-axis acceleration = 1 g, full-scale range = ±10.24 g, andoutput data rate (ODR) = 500 Hz, unless otherwise noted. Note that multifunction pin names may be referenced only by their relevant
function.
Table 2.
Parameter
SENSOR INPUT
Output Full Scale Range (FSR)

Test Conditions/Comments
Each axis
User selectable

Nonlinearity
Cross Axis Sensitivity
SENSITIVITY
X-Axis, Y-Axis, and Z-Axis Sensitivity±10 g

X-Axis, Y-Axis, and Z-Axis Scale Factor

Sensitivity Change due to Temperature
0 g OFFSET
X-Axis, Y-Axis, and Z-Axis 0 g Output
0 g Offset vs. Temperature (X-Axis, Y-Axis, and Z-Axis)1
Vibration Rectification Error (VRE) 2
NOISE DENSITY
X-Axis, Y-Axis, and Z-Axis
Velocity Random WalkOUTPUT DATA RATE AND BANDWIDTHADC Resolution
Low-Pass Filter Passband Frequency
High-Pass Filter Passband Frequency When Enabled(Disabled by Default)
SELF TEST
Output Change
Z-AxisEach axis
±10 g
±20 g
±40 g
±10 g
±20 g
±40 g
TA = −40°C to +125°C
Each axis, ±10 g
TA = −40°C to +125°C
Offset due to 7.5 g rms vibration,±10 g range, in a 1 g orientation
±10 g

Min

Typ

Max

g
g
g
% FSR
%

±10.24±20.48±40.960.1
147,10423,552
11,776

51,20025,60012,800
19.5
39
78
±0.01

55,296
27,64813,824

LSB/g
LSB/g
LSB/g
µg/LSBµg/LSBµg/LSB
%/°C

−375
−0.75

±125
±0.50
<0.1

+375
+0.75

mg
mg/°C
g

80
45
65

X-axis and y-axis
Z-axisµg/√Hzµm/sec/√Hrµm/sec/√Hr

20
User programmable, Register 0x28
User programmable, Register 0x28
for 4 kHz ODR±10 g range

Rev. 0 | Page 4 of 42

Unit

1
0.0095

1000
10

1.25

bits
Hz
Hz

g

Data SheetParameter
POWER SUPPLY
Voltage Range
VSUPPLY Operating3
VDDIO
V1P8ANA and V1P8DIG with Internal LDO Bypassed
Current
Measurement ModeVSUPPLY (LDO Enabled)
V1P8ANA (LDO Disabled)
V1P8DIG (LDO Disabled)Standby ModeVSUPPLY (LDO Enabled)
V1P8ANA (LDO Disabled)
V1P8DIG (LDO Disabled)
Turn On Time4

ADXL356/ADXL357
Test Conditions/Comments

Min

Typ

Max

Unit

VSUPPLY = 0 V

2.25
V1P8DIG
1.62

2.5
2.5
1.8

3.6
3.6
1.98

V
V
V

±10 g range
Power-off to standby

TEMPERATURE SENSOR
Output at 25°C
Scale Factor
TEMPERATURE
Operating Temperature Range

−40

1

200
160
35.5

µA
µA
µA

21
7
10
<10
<10

µA
µA
µA
ms
ms

1852
−9.05

LSB
LSB/°C+125°C

The temperature change is −40°C to +25°C or +25°C to +125°C.
The VRE measurement is the shift in dc offset while the device is subject to 12.5 g rms random vibration from 50 Hz to 2 kHz. The DUT is configured for the ±2 g range
and an output data rate of 4 kHz. The VRE scales with the range setting.
3
When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS.
4
Standby to measurement mode; valid when the output is within 1 mg of final value.
2

Rev. 0 | Page 5 of 42

ADXL356/ADXL357

Data SheetSPI DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL357
Note that multifunction pin names may be referenced by their relevant function only.
Table 3.
Parameter
DC INPUT LEVELS
Input Voltage
Low Level
High Level
Input Current
Low Level
High Level
DC OUTPUT LEVELS
Output Voltage
Low Level
High Level
Output Current
Low Level
High Level
AC INPUT LEVELSSCLK Frequency
SCLK High TimeSCLK Low Time
CS Setup TimeCS Hold Time
CS Disable Time
Rising SCLK Setup TimeMOSI Setup TimeMOSI Hold TimeAC OUTPUT LEVELS
Propagation Delay
Enable MISO Time
Disable MISO Time

SymbolTest Conditions/Comments

VIL
VIH

Min

Typ

Max

Unit

0.3 × VDDIO

V
V

0.7 × VDDIO

IIL
IIH

VIN = 0 V
VIN = VDDIO

VOL
VOH

IOL = IOL, MIN
IOH = IOH, MAX

IOL
IOH

VOL = VOL, MAX
VOH = VOH, MIN−0.1

0.2 × VDDIO
0.8 × VDDIO
−10

0.1
40
40
20
20
40
20
20
20
CLOAD = 30 pF

10

MHz
ns
ns
ns
ns
ns
ns
ns
ns

30

ns
ns
ns

30
20
tCSD

CS

tCSS

tHIGH

tLOW

tCSH

tSCLKS

SCLK

tSU

tHD

MOSI

tP

tDIS
15429-003

tEN
MISO

Figure 3. SPI Interface Timing Diagram

Rev. 0 | Page 6 of 42

V
V
mA
mA

4

tHIGH
tLOW
tCSS
tCSH
tCSD
tSCLKS
tSU
tHD
tP
tEN
tDIS

µA
µA

0.1

Data SheetADXL356/ADXL357

I2C DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL357
Note that multifunction pin names may be referenced only by their relevant function.
Table 4.
Parameter
DC INPUT LEVELS
Input Voltage
Low Level
High Level
Hysteresis of Schmitt
Triggered Inputs
Input Current
DC OUTPUT LEVELS
Output Voltage
Low Level

Symbol

VIL
VIH
VHYS
IIL

VOL1
VOL2

Output Current
Low Level

IOL

AC INPUT LEVELSSCL Frequency
SCL High Time
SCL Low Time
Start Setup Time
Start Hold TimeSDA Setup TimeSDA Hold Time
Stop Setup TimeBus Free TimeSCL Input Rise TimeSCL Input Fall TimeSDA Input Rise TimeSDA Input Fall Time
Width of Spikes to
SuppressAC OUTPUT LEVELS
Propagation Delay
Data
Acknowledge
Output Fall Time

Test Conditions/
Comments

tHIGH
tLOW
tSUSTAtHDSTAtSUDATtHDDATtSUSTO
tBUF
tRCL
tFCL
tRDA
tFDA
tSP

Min

I2C_HS = 0 (Fast Mode)
Typ Max

I2C_HS = 1 (High Speed Mode)
Min
Typ
Max

0.3 × VDDIO
0.7 × VDDIO
0.05 × VDDIO
0.1 × VDDIO < VIN <0.9 × VDDIO

V
VµA

0.7 × VDDIO
0.1 × VDDIO−10IOL = 3 mA
VDDIO > 2 V
VDDIO ≤ 2 V
VOL = 0.4 V
VOL = 0.6 V

0.3 × VDDIO

+10

µA

0.4
0.2 × VDDIO

V
V

20
6

mA
mA

0
260
500
260
260
50
0
260
500

1

0
60
160
160
160
10
0
160

3.4

120
120
120
120
50

Not shown in Figure 4

MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

80
80
160
160
10

CLOAD = 500 pF
tVDDATtVDACKtF

97
Not shown in Figure 4

450
450
120

20 ×
(VDDIO/5.5)

27

tFDA

135

tRDA

ns
ns
ns

tBUF

SDA

tVDDATtSUDATtHDDATtLOWtVDDAT
SCL

Figure 4. I2C Interface Timing Diagram

Rev. 0 | Page 7 of 42tVDACK
tFCL

tHIGH

tRCL

tSUSTOtSUSTA
15429-004

tSUSTA tHDSTAUnitADXL356/ADXL357

Data Sheet

ABSOLUTE MAXIMUM RATINGSRECOMMENDED SOLDERING PROFILE

Table 5.

Figure 5 and Table 7 provide details about the recommended
soldering profile.

Rating5000 g
5.4 V
1.98 V

RAMP-UP−0.3 V to VDDIO + 0.3 V

TSMIN

tS

−40°C to +125°C−55°C to +150°C

RAMP-DOWN

t25°C TO PEAK
TIME

Thermal performance is directly linked to printed circuit board(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.

Figure 5. Recommended Soldering Profile

Table 7. Recommended Soldering Profile
Profile Feature
Average Ramp Rate from Liquid
Temperature (TL) to Peak
Temperature (TP)Preheat
Minimum Temperature(TSMIN)
Maximum Temperature(TSMAX)Time from TSMIN to TSMAX (tS)TSMAX to TL Ramp-Up Rate

Table 6. Thermal Resistance

1

tL

TSMAX

PREHEATTHERMAL RESISTANCE

θJA
42

TL

15429-005−0.3 V to VDDIO + 0.3 V−0.3 V to V1P8ANA + 0.3 V

Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at theseor any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Package TypeE-14-11CRITICAL ZONETL TO TPtP

TP

TEMPERATURE

Parameter
Acceleration (Any Axis, 0.1 ms)
VSUPPLY, VDDIO
V1P8ANA, V1P8DIG Configured as Inputs
ADXL356
Digital Inputs (RANGE, ST1, ST2, STBY)
Analog Outputs (XOUT, YOUT, ZOUT, TEMP)ADXL357
Digital Pins (CS/SCL, SCLK/VSSIO,MOSI/SDA, MISO/ASEL, INT1, INT2,
DRDY)
Operating Temperature Range
Storage Temperature Range

Liquid Temperature (TL)
Time Maintained Above TL (tL)

Unit
°C/W

Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with four thermal vias. See JEDEC JESD51.

Peak Temperature (TP)Time of Actual TP − 5°C (tP)
Ramp-Down Rate
Time from 25°C to Peak
Temperature (t25°C TO PEAK)

ESD CAUTION

Rev. 0 | Page 8 of 42

Condition
Sn63/Pb37
Pb-Free
3°C/sec
3°C/sec
maximum
maximum

100°C

150°C

150°C

200°C

60 sec to
120 sec
3°C/sec
maximum
183°C
60 sec to150 sec
240°C +
0°C/−5°C
10 sec to
30 sec6°C/sec
maximum
6 minutes
maximum

60 sec to
180 sec
3°C/sec
maximum
217°C
60 sec to150 sec
260°C +
0°C/−5°C
20 sec to
40 sec6°C/sec
maximum
8 minutes
maximumData SheetADXL356/ADXL357

12 XOUTY

11 VSUPPLYRANGE 1
ST1 2

ADXL356

10 V1P8ANA

ST2 3TOP VIEW(Not to Scale)

9

VSS

8

V1P8DIGXZSTBY 7VSSIO 6

VDDIO 5

TEMP 4

15429-006

13 YOUT14 ZOUTPIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 6. ADXL356 Pin Configuration

Table 8. ADXL356 Pin Function Descriptions
Pin No.
1

Mnemonic
RANGE

2
3
4
5
6
7

ST1
ST2
TEMP
VDDIO
VSSIO
STBY

8

V1P8DIG

910

VSS
V1P8ANA11

VSUPPLY

12
13
14

XOUT
YOUT
ZOUT

Description
Range Selection Pin. Set this pin to ground to select the ±10 g range, or set this pin to VDDIO to select the±20 g or ±40 g range. This pin is model dependent (see the Ordering Guide section).
Self Test Pin 1. This pin enables self test mode.
Self Test Pin 2. This pin activates the electromechanical self test actuation.
Temperature Sensor Output.
Digital Interface Supply Voltage.
Digital Ground.
Standby or Measurement Mode Selection Pin. Set this pin to ground to enter standby mode, or set this pin
to VDDIO to enter measurement mode.
Digital Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to thispin externally.
Analog Ground.
Analog Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to thispin externally.
Supply Voltage. When VSUPPLY equals 2.25 V to 3.6 V, VSUPPLY enables the internal LDO regulators to generate
V1P8DIG and V1P8ANA. For VSUPPLY = VSS, V1P8DIG and V1P8ANA are externally supplied.
X-Axis Output.
Y-Axis Output.
Z-Axis Output.

Rev. 0 | Page 9 of 42

12 INT1Y

11 VSUPPLY

CS/SCL 1
SCLK/VSSIO 2

ADXL357

10 V1P8ANA

MOSI/SDA 3

TOP VIEW(Not to Scale)

9

VSS

8

V1P8DIGX
Z

RESERVED 7VSSIO 6

VDDIO 5

MISO/ASEL 415429-007

13 INT2

Data Sheet
14 DRDYADXL356/ADXL357

Figure 7. ADXL357 Pin Configuration (SPI/I2C)

Table 9. ADXL357 Pin Function Descriptions
Pin No.
1

Mnemonic
CS/SCL2

SCLK/VSSIO

3

MOSI/SDA

4

MISO/ASEL

5
6
7
8

VDDIO
VSSIO
RESERVED
V1P8DIG

910

VSS
V1P8ANA11

VSUPPLY

12
13
14

INT1
INT2
DRDY

Description
Chip Select for SPI (CS).
Serial Communications Clock for I2C (SCL).
Serial Communications Clock for SPI (SCLK).
I2C Mode Enable (VSSIO). Connect this pin to Pin 6 (VSSIO) to enable I2C mode.
Master Output, Slave Input for SPI (MOSI).
Serial Data for I2C (SDA).
Master Input, Slave Output for SPI (MISO).
Alternate I2C Address Select for I2C (ASEL).
Digital Interface Supply Voltage.
Digital Ground.
Reserved. This pin can be connected to ground or left open.
Digital Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to thispin externally.
Analog Ground.
Analog Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to thispin externally.
Supply Voltage. When VSUPPLY equals 2.25 V to 3.6 V, VSUPPLY enables the internal LDOs to generate V1P8DIG and
V1P8ANA. For VSUPPLY = VSS, V1P8DIG and V1P8ANA are externally supplied.
Interrupt Pin 1.
Interrupt Pin 2.
Data Ready Pin.

Rev. 0 | Page 10 of 42

Data SheetADXL356/ADXL357

TYPICAL PERFORMANCE CHARACTERISTICS
All figures include data for multiple devices and multiple lots, and they were taken in the ±10 g range, unless otherwise noted.

1

100

1k

10k

FREQUENCY (Hz)

0.01
10

Figure 8. ADXL356 Frequency Response for X-Axis

1k

10k

Figure 9. ADXL356 Frequency Response for Y-Axis

0.1

0.01
10

100

1k

10k

FREQUENCY (Hz)15429-012

Y-AXIS RESPONSE (dB)10015429-009

Y-AXIS RESPONSE (dB)1

FREQUENCY (Hz)Figure 12. ADXL357 Normalized Frequency Response for Y-Axis at 4 kHz ODR
1Z-AXIS RESPONSE (dB)

10

1

100

1k

FREQUENCY (Hz)Figure 10. ADXL356 Frequency Response for Z-Axis

10k

0.1

0.01
10

15429-010

Z-AXIS RESPONSE (dB)

10k

Figure 11. ADXL357 Normalized Frequency Response for X-Axis at 4 kHz ODR

1

0.1
10

1k

FREQUENCY (Hz)

10

0.1
10

100

100
FREQUENCY (Hz)

1k

10k

15429-013

0.1
10

0.1

15429-011

X-AXIS RESPONSE (dB)115429-008

X-AXIS RESPONSE (dB)10

Figure 13. ADXL357 Normalized Frequency Response for Z-Axis at 4 kHz ODRRev. 0 | Page 11 of 42

ADXL356/ADXL357

Data Sheet

75

1.0

CHANGE IN SENSITIVITY (%)

OFFSET NORMALIZED (mg)

50

25

0

–25

0.5

0

–0.5

–25

–10

5

20

35

50

65

80

95

110

125

TEMPERATURE (°C)

–1.0
–40

15429-014

–75
–40

–25

–10

5

20

35

50

65

80

95

110

125

TEMPERATURE (°C)

15429-017–50

Figure 17. ADXL356 X-Axis Change in Sensitivity Relative to 25°C vs.
Temperature

Figure 14. ADXL356 X-Axis Zero g Offset Normalized Relative to 25°C vs.
Temperature

1.0

75

CHANGE IN SENSITIVITY (%)

OFFSET NORMALIZED (mg)

50

25

0

–25

0.5

0

–0.5

–25

–10

5

20

35

50

65

80

95

110

125

TEMPERATURE (°C)

–1.0
–40

15429-015

–75
–40

–25

–10

5

20

35

50

65

80

95

110

125

TEMPERATURE (°C)

15429-018–50

Figure 18. ADXL356 Y-Axis Change in Sensitivity Relative to 25°C vs.
Temperature

Figure 15. ADXL356 Y-Axis Zero g Offset Normalized Relative to 25°C vs.
Temperature

1.0

75

CHANGE IN SENSITIVITY (%)

OFFSET NORMALIZED (mg)

50

25

0

–25

0.5

0

–0.5

–25

–10

5

20

35

50

65

TEMPERATURE (°C)

80

95

110

125

Figure 16. ADXL356 Z-Axis Zero g Offset Normalized Relative to 25°C vs.
Temperature

Rev. 0 | Page 12 of 42

–1.0
–40

–25

–10

5

20

35

50

65

80

95

110

125

TEMPERATURE (°C)

Figure 19. ADXL356 Z-Axis Change in Sensitivity Relative to 25°C vs.
Temperature

15429-019–75–4015429-016–50

0Z-AXIS OFFSET AT 25°C (mg)0Figure 20. ADXL356 Zero g Offset Histogram at 25°C, X-Axis
Figure 23. ADXL356 Sensitivity Histogram at 25°C, X-Axis

20

15

10

5

15

10

5

X-AXIS OFFSET AT 25°C (V/g)

30

25

0

Figure 21. ADXL356 Zero g Offset Histogram at 25°C, Y-Axis
Figure 24. ADXL356 Sensitivity Histogram at 25°C, Y-Axis
Y-AXIS OFFSET AT 25°C (V/g)

25

25

0

Figure 22. ADXL356 Zero g Offset Histogram at 25°C, Z-Axis

Figure 25. ADXL356 Sensitivity Histogram at 25°C, Z-Axis

Rev. 0 | Page 13 of 42

Z-AXIS OFFSET AT 25°C (V/g)

15429-023

1015429-024

1515429-025

20

0.07360.07400.07440.07480.07520.0756
0.07600.07640.07680.07720.07760.07800.07840.07880.07920.07960.08000.08040.08080.08120.08160.08200.08240.08280.08320.08360.08400.08440.08480.08520.08560.08600.086425

PERCENT OF POPULATION (%)

30

0.07360.07400.07440.07480.07520.0756
0.07600.07640.07680.07720.07760.07800.07840.07880.07920.07960.08000.08040.08080.08120.08160.08200.08240.08280.08320.08360.08400.08440.08480.08520.08560.08600.086425

PERCENT OF POPULATION (%)

15429-020

375

325

275

225

175

125

75

25

–25

–75

–125

–175

–225

–275

–325

–375

PERCENT OF POPULATION (%)
40

0.07360.07400.07440.07480.07520.0756
0.07600.07640.07680.07720.07760.07800.07840.07880.07920.07960.08000.08040.08080.08120.08160.08200.08240.08280.08320.08360.08400.08440.08480.08520.08560.08600.086420

PERCENT OF POPULATION (%)

Y-AXIS OFFSET AT 25°C (mg)15429-021

375

325

275

225

175

125

75

25

–25

–75

–125

–175

–225

–275

X-AXIS OFFSET AT 25°C (mg)15429-022

375

325

275

225

175

125

75

25

–25

–75

–125

–175

–225

–275

–325

–375

0

–325

PERCENT OF POPULATION (%)
0–375

PERCENT OF POPULATION (%)

Data SheetADXL356/ADXL357

25

35

20

15

10

5

5

20

15

10

5

20

15

10

5

ADXL356/ADXL357

Data Sheet

0.20

0.10

0.15
0.05
OFFSET SHIFT (g)OFFSET SHIFT (g)

0.10
0.05
0
–0.05

0

–0.05

–0.10

0

2

4

6

8

10

INPUT VIBRATION (g rms)

–0.10

15429-026

–0.20

0

5

10

15

20

25

INPUT VIBRATION (g rms)

Figure 26. ADXL356 Vibration Rectification Error (VRE),
X-Axis Offset from +1 g, ±10 g Range, X-Axis Orientation = −1 g

15429-029–0.15

Figure 29. ADXL356 Vibration Rectification Error (VRE),
X-Axis Offset from +1 g, ±40 g Range, X-Axis Orientation = −1 g

0.20

0.2

0.15
0.1
OFFSET SHIFT (g)OFFSET SHIFT (g)

0.10
0.05
0
–0.05

0

–0.1

–0.10

0

2

4

6

8

10

INPUT VIBRATION (g rms)

–0.2

15429-027

–0.20

0

5

10

15

20

25

INPUT VIBRATION (g rms)

Figure 27. ADXL356 Vibration Rectification Error (VRE),
Y-Axis Offset from +1 g, ±10 g Range, Y-Axis Orientation = +1 g

15429-030–0.15

Figure 30. ADXL356 Vibration Rectification Error (VRE),
Y-Axis Offset from +1 g, ±40 g Range, Y-Axis Orientation = +1 g
0.2

0.20
0.15

0.1
OFFSET SHIFT (g)

0.05
0
–0.05

0

–0.1

–0.10

–0.20
0

2

4

6

8

10

INPUT VIBRATION (g rms)

Figure 28. ADXL356 Vibration Rectification Error (VRE),
Z-Axis Offset from +1 g, ±10 g Range, Z-Axis Orientation = +1 g

–0.2
0

5

10

15

20

25

INPUT VIBRATION (g rms)

Figure 31. ADXL356 Vibration Rectification Error (VRE),
Z-Axis Offset from +1 g, ±40 g Range, Z-Axis Orientation = +1 g

Rev. 0 | Page 14 of 42

15429-031–0.15
15429-028

OFFSET SHIFT (g)0.10

Data SheetADXL356/ADXL357

75

1.0
0.8
CHANGE IN SENSITIVITY (%)

OFFSET NORMALIZED (mg)

50

25

0

–25

–50

0.6
0.4
0.2
0
–0.2
–0.4
–0.6

15

30

45

60

75

90

105 120 135

TEMPERATURE (°C)

–1.0
–40

15429-032

0

–25

–10

5

20

35

50

65

80

95

110

125

TEMPERATURE (°C)

15429-035–0.8–75–45 –30 –15

Figure 35. ADXL357 X-Axis Change in Sensitivity Relative to 25°C vs.
Temperature

Figure 32. ADXL357 X-Axis Zero g Offset Normalized Relative to 25°C vs.
Temperature

1.0

75

0.8
CHANGE IN SENSITIVITY (%)

OFFSET NORMALIZED (mg)

50

25

0

–25

–50

0.6
0.4
0.2
0
–0.2
–0.4
–0.6

–25

–5

15

35

55

75

95

115

TEMPERATURE (°C)

–1.0
–40

15429-033

–75
–45

–25

–10

5

20

35

50

65

80

95

110

125

TEMPERATURE (°C)

15429-036–0.8

Figure 36. ADXL357 Y-Axis Change in Sensitivity Relative to 25°C vs.
Temperature

Figure 33. ADXL357 Y-Axis Zero g Offset Normalized Relative to 25°C vs.
Temperature

1.0

75

0.8
CHANGE IN SENSITIVITY (%)

OFFSET NORMALIZED (mg)

50

25

0

–25

–50

0.6
0.4
0.2
0
–0.2
–0.4
–0.6

–5

15

35

55

TEMPERATURE (°C)

75

95

115

Figure 34. ADXL357 Z-Axis Zero g Offset Normalized Relative to 25°C vs.
Temperature

Rev. 0 | Page 15 of 42

–1.0
–40

–25

–10

5

20

35

50

65

80

95

110

125

TEMPERATURE (°C)

Figure 37. ADXL357 Z-Axis Change in Sensitivity Relative to 25°C vs.
Temperature

15429-037–25

15429-034

–0.8

–75
–45

Data Sheet
40

30

35

35
30
25
20
15

54784

54272

53760

53248

52736

52224

51712

51200

50688

50176

49664

49152

48640

48128

47616

15429-039

375

325

275

225

175

125

75

25

–25

–75

–125

–175

–225

0

–275

0

–325

5

47104

10

5

Y-AXIS OFFSET AT 25°C (mg)Y-AXIS SENSITIVITY AT 25°C (LSB/g)

Figure 42. ADXL357 Sensitivity Histogram at 25°C, Y-Axis

25

30

Z-AXIS OFFSET AT 25°C (mg)

10

54784

54272

53760

53248

52736

52224

51712

51200

50688

50176

49664

49152

48640

5

0
15429-040

375

325

275

225

175

125

75

25

–25

–75

–125

–175

–225

–275

–325

0

–375

5

15

48128

10

20

47616

15

25

47104

PERCENT OF POPULATION (%)

Figure 39. ADXL357 Zero g Offset Histogram at 25°C, Y-Axis

20

15429-04240

1015429-043

35

15

55296

45

20

15429-041

54784

40

PERCENT OF POPULATION (%)

Figure 41. ADXL357 Sensitivity Histogram at 25°C, X-Axis

25

55296

X-AXIS SENSITIVITY AT 25°C (LSB/g)

Figure 38. ADXL357 Zero g Offset Histogram at 25°C, X-Axis

30

55296

54272

53760

53248

52736

52224

51712

51200

50688

50176

49664

375

15429-038

325

275

225

175

75

125

25

–25

–75

–125

–175

–225

0

–275

0

–325

5

–375

PERCENT OF POPULATION (%)

10

5

X-AXIS OFFSET AT 25°C (mg)

PERCENT OF POPULATION (%)

15

49152

10

20

48640

15

25

48128

20

30

47616

25

47104

PERCENT OF POPULATION (%)

35

–375

PERCENT OF POPULATION (%)

ADXL356/ADXL357

Z-AXIS SENSITIVITY AT 25°C (LSB/g)

Figure 43. ADXL357 Sensitivity Histogram at 25°C, Z-Axis

Figure 40. ADXL357 Zero g Offset Histogram at 25°C, Z-Axis

Rev. 0 | Page 16 of 42

ADXL356/ADXL357

0.5

0.20

0

0.15
0.10

–0.05
OFFSET SHIFT (g)

–0.10
–0.15
–0.20

–0.05

2

4

6

8

10

INPUT VIBRATION (g rms)

–0.20

15429-044

0

0

5

10

15

20

25

INPUT VIBRATION (g rms)

Figure 44. ADXL357 Vibration Rectification Error (VRE),
X-Axis Offset from +1 g, ±10 g Range, X-Axis Orientation = −1 g

15429-047

–0.15

–0.30

Figure 47. ADXL357 Vibration Rectification Error (VRE),
X-Axis Offset from +1 g, ±40 g Range, X-Axis Orientation = −1 g

0.5

0.20

0

0.15
0.10

–0.05
OFFSET SHIFT (g)

–0.10
–0.15
–0.20

0.05
0
–0.05
–0.10

–0.25

–0.15

0

2

4

6

8

10

INPUT VIBRATION (g rms)

–0.20

15429-045

–0.30

0

5

10

15

20

25

INPUT VIBRATION (g rms)

Figure 45. ADXL357 Vibration Rectification Error (VRE),
Y-Axis Offset from +1 g, ±10 g Range, Y-Axis Orientation = +1 g

15429-048

OFFSET CHANGE (g)

0

–0.10

–0.25

Figure 48. ADXL357 Vibration Rectification Error (VRE),
Y-Axis Offset from +1 g, ±40 g Range, Y-Axis Orientation = +1 g

0.5

0.20

0

0.15
0.10
OFFSET SHIFT (g)

–0.05
–0.10
–0.15
–0.20

0.05
0
–0.05
–0.10

–0.25

–0.15

–0.30
0

2

4

6

8

10

INPUT VIBRATION (g rms)

15429-046

OFFSET CHANGE (g)0.05

Figure 46. ADXL357 Vibration Rectification Error (VRE),
Z-Axis Offset from +1 g, ±10 g Range, Z-Axis Orientation = +1 g

–0.20
0

5

10

15

20

25

INPUT VIBRATION (g rms)

Figure 49. ADXL357 Vibration Rectification Error (VRE),
Z-Axis Offset from +1 g, ±40 g Range, Z-Axis Orientation = +1 g

Rev. 0 | Page 17 of 42

15429-049

OFFSET CHANGE (g)Data SheetADXL356/ADXL357

Data Sheet
2300

0.00201.1

0.00151.00.00100.9

0.0005LINEAR OFFSET (V)

0.002500.8–0.0005
0.7
–40

20

40

60

80

100

15429-050–0.0010
0

–20

120

TEMPERATURE (°C)

Figure 50. ADXL356 Temperature Sensor Output and Linearity Offset vs.
Temperature

6

2100
4
1900
2
1700
1500

0

1300
–2

LINEAR OFFSET (V)TEMPERATURE SENSOR OUTPUT (LSB)

0.0030

1.2

1100
–4
900

TEMPERATURE SENSOR OUTPUT
LINEAR OFFSET

700
–40

–20

0

20

40

60

80

100

120

–6

TEMPERATURE (°C)

Figure 53. ADXL357 Temperature Sensor Output and Linearity Offset vs.
Temperature

35

30

20
15
10

TOTAL SUPPLY CURRENT AT 25°C (µA)

15429-051

0

125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175

5

Figure 51. ADXL356 Total Supply Current, 3.3 V

30
25
20
15
10

15429-052

4200

4160

4120

4080

4040

4000

3960

3920

3880

3840

3800

5

ODR FREQUENCY (Hz)

20

15

10

5

0

TOTAL SUPPLY CURRENT AT 25°C (µA)

Figure 54. ADXL357 Total Supply Current, 3.3 V

35

0

25

Figure 52. ADXL357 Internal ODR Frequency Histogram

Rev. 0 | Page 18 of 42

15429-054

25

175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225

PERCENT OF POPULATION (%)

PERCENT OF POPULATION (%)

30

PERCENT OF POPULATION (%)

TEMPERATURE SENSOR OUTPUT (V)TEMPERATURE SENSOR OUTPUT
LINEAR OFFSET

15429-053

0.0035

1.3

Data SheetADXL356/ADXL357

ROOT ALLAN VARIANCE (RAV) ADXL357 CHARACTERISTICS
Figure 55 to Figure 57 include data for multiple devices and multiple lots, and they were taken in the ±10 g range, unless otherwise noted.
1000

10

1
0.01

0.1

1

10

100

1000

INTEGRATION TIME (Seconds)

Figure 55. ADXL357 Root Allan Variance (RAV), X-Axis

10

1

10

100

INTEGRATION TIME (Seconds)

1000

15429-056

ROOT ALLAN VARIANCE (µg)

100

0.1

10

1
0.01

0.1

1

10

100

INTEGRATION TIME (Seconds)

Figure 57. ADXL357 Root Allan Variance (RAV), Z-Axis

1000

1
0.01

100

Figure 56. ADXL357 Root Allan Variance (RAV), Y-Axis

Rev. 0 | Page 19 of 42

1000

15429-057

ROOT ALLAN VARIANCE (µg)

10015429-055

ROOT ALLAN VARIANCE (µg)

1000

ADXL356/ADXL357

Data Sheet

THEORY OF OPERATIONThe ADXL356 is a complete 3-axis, ultralow noise and ultrastableoffset MEMS accelerometer with outputs ratiometric to the analog
1.8 V supply, V1P8ANA. The ADXL357 adds three high resolution
ADCs that use the analog 1.8 V supply as a reference to provide
digital outputs insensitive to the supply voltage. The ADXL356B
is pin selectable for ±10 g or ±20 g full scale, the ADXL356C is pin
selectable for ±10 g or ±40 g full scale, and the ADXL357 is
programmable for ±10.24 g, ±20.48 g, and ±40.96 g full scale.
The ADXL357 offers both SPI and I2C communications ports.
The micromachined, sensing elements are fully differential,
comprising the lateral x-axis and y-axis sensors and the vertical,
teeter totter z-axis sensors. The x-axis and y-axis sensors andthe z-axis sensors go through separate signal paths that minimize
offset drift and noise. The signal path is fully differential, except

for a differential to single-ended conversion at the analog
outputs of the ADXL356.
The analog accelerometer outputs of the ADXL356 are ratiometricto V1P8ANA; therefore, carefully digitize them correctly. The temperature sensor output is not ratiometric. The XOUT, YOUT, and ZOUT
analog outputs are filtered internally with an antialiasing filter.
These analog outputs also have an internal 32 kΩ series resistor
that can be used with an external capacitor to set the bandwidthof the output.
The ADXL357 includes antialias filters before and after the highresolution Σ-Δ ADC. User-selectable output data rates and filter
corners are provided. The temperature sensor is digitized with a
12-bit successive approximation register (SAR) ADC.

Rev. 0 | Page 20 of 42

Data SheetADXL356/ADXL357

APPLICATIONS INFORMATIONANALOG OUTPUT

and noise reduction prior to the external ADC. The antialias
filter cutoff frequency must be significantly higher than thedesired signal bandwidth. If the antialias filter corner is too low,ratiometricity can degrade where the signal attenuation isdifferent from the reference attenuation.

Figure 58 shows the ADXL356 application circuit. The analog
outputs (XOUT, YOUT, and ZOUT) are ratiometric to the 1.8 V
analog voltage from the V1P8ANA pin. V1P8ANA can be poweredwith an on-chip LDO regulator that is powered from VSUPPLY.
V1P8ANA can also be supplied externally by forcing VSUPPLY to VSS,
which disables the LDO regulator. Due to the ratiometricresponse, the analog output requires referencing to the V1P8ANA
supply when digitizing to achieve the inherent noise and offset
performance of the ADXL356. The 0 g bias output is nominallyequal to V1P8ANA/2. The recommended option is to use the
ADXL356 with a ratiometric ADC (for example, the Analog
Devices, Inc., AD7682) with V1P8ANA providing the voltage
reference. This configuration results in self cancellation oferrors due to minor supply variations.

DIGITAL OUTPUT
Figure 59 shows the ADXL357 application circuit with therecommended bypass capacitors. The communications interface
is either SPI or I2C (see the Serial Communications section for
additional information).
The ADXL357 includes an internal configurable digital bandpass filter. Both the high-pass and low-pass poles of the filter
are adjustable, as detailed in the Filter Settings Register section
and Table 44. At power-up, the default conditions for the filters
are as follows:•••

2.25V TO 3.6V

0.1µF

11 VSUPPLYRANGE 1

1µF

10 V1P8ANA

ST1 2
ST2 3

High-pass filter (HPF) = dc (off)Low-pass filter (LPF) = 1000 Hz
Output data rate = 4000 Hz

12 XOUT14 ZOUTVDDIO (±20g, ±40g)
GND ( ±10g)

13 YOUTThe ADXL356 outputs two forms of filtering: internal antialiasing filtering with a cutoff frequency of approximately 1.5 kHz,and external filtering. The external filter uses a fixed, on-chip,
32 kΩ resistance in series with each output in conjunction withthe external capacitors to implement the low-pass filter antialiasing

0.1µF

ADXL356

STBY 7VSSIO 6

VDDIO 5

TEMP 49VSS

8

V1P8DIG

1µF

ADC VREF

VDDIO (MEASUREMENT)GND (STANDBY)

1µF

1µF

0.1µF

0.1µF

15429-058

2.25V TO 3.6V

1µF

10 V1P8ANAADXL357

0.1µF

TOP VIEW(Not to Scale)

9

VSS

8

V1P8DIG

1µF

1µF

1µF

0.1µF

0.1µF

2.25V TO 3.6V

Figure 59. ADXL357 Application Circuit
Rev. 0 | Page 21 of 42

15429-060

RESERVED 7VSSIO 6

MISO/ASEL 4

VDDIO 5SPI/I2C
INTERFACE

MOSI/SDA 3

0.1µF

11 VSUPPLY

CS/SCL 1
SCLK/VSSIO 2

2.25V TO 3.6V

12 INT1

13 INT2

14 DRDY

Figure 58. ADXL356 Application Circuit

ADXL356/ADXL357

Data Sheet

AXES OF ACCELERATION SENSITIVITY
Figure 60 shows the axes of acceleration sensitivity. Note thatthe output voltage increases when accelerated along thesensitive axis.
Z

external ADCs, use V1P8ANA as the reference voltage. The digital
output ADXL357 includes ADCs that are ratiometric to V1P8ANA,
thereby rendering offset and sensitivity insensitive to the valueof V1P8ANA. V1P8ANA can be an input or an output as defined by thestate of the VSUPPLY voltage.

V1P8DIGY

V1P8DIG is the supply voltage for the internal logic circuitry. A
separate LDO regulator decouples the digital supply noise fromthe analog signal path. V1P8ANA can be an input or an output as
defined by the state of the VSUPPLY voltage. If driven externally,
V1P8DIG must be the same voltage as the V1P8ANA voltage.

X

15429-059

VDDIO

Figure 60. Axes of Acceleration Sensitivity

POWER SEQUENCING
There are two methods for applying power to the device.
Typically, internal LDO regulators generate the 1.8 V power forthe analog and digital supplies, V1P8ANA and V1P8DIG, respectively.
Optionally, connecting VSUPPLY to VSS and driving V1P8ANA andV1P8DIG with an external supply can supply V1P8ANA and V1P8DIG.
When using the internal LDO regulators, connect VSUPPLY to a
voltage source between 2.25 V to 3.6 V. In this case, VDDIO andVSUPPLY can be powered in parallel. VSUPPLY must not exceed the
VDDIO voltage by greater than 0.5 V. If necessary, VDDIO can be
powered before VSUPPLY.
When disabling the internal LDO regulators and using an external
1.8 V supply to power V1P8ANA and V1P8DIG, tie VSUPPLY to ground,and set V1P8ANA and V1P8DIG to the same final voltage level. In thecase of bypassing the LDOs, the recommended power sequence isto apply power to VDDIO, followed by V1P8DIG approximately 10 µs
later, and then V1P8ANA approximately 10 µs later. If necessary,
V1P8DIG and VDDIO can be powered from the same 1.8 V supply,
which can also be tied to V1P8ANA with proper isolation. In thiscase, proper decoupling and low frequency isolation is important
to maintain the noise performance of the sensor.

POWER SUPPLY DESCRIPTION
The ADXL356/ADXL357 have four different power supply
domains: VSUPPLY, V1P8ANA, V1P8DIG, and VDDIO. The internal
analog and digital circuitry operates at 1.8 V nominal.

VSUPPLYVSUPPLY is 2.25 V to 3.6 V, which is the input range to the two
LDO regulators that generate the nominal 1.8 V outputs for
V1P8ANA and V1P8DIG. Connect VSUPPLY to VSS to disable the LDO
regulators, which allows driving V1P8ANA and V1P8DIG from anexternal source.

V1P8ANA
All sensor and analog signal processing circuitry operates inthis domain. Offset and sensitivity of the analog output
ADXL356 are ratiometric to this supply voltage. When using

The VDDIO value determines the logic high levels. On the analog
output ADXL356, VDDIO sets the logic high level for the self test
pins, ST1 and ST2, as well as the STBY pin. On the digital output
ADXL357, VDDIO sets the logic high level for communications
interface ports, as well as the interrupt and DRDY outputs.
The LDO regulators are operational when VSUPPLY is between
2.25 V and 3.6 V. V1P8ANA and V1P8DIG are the regulator outputs inthis mode. Alternatively, when tying VSUPPLY to VSS, V1P8ANA andV1P8DIG are supply voltage inputs with a 1.62 V to 1.98 V range.

OVERRANGE PROTECTION
To avoid electrostatic capture of the proof mass when theaccelerometer is subject to input acceleration beyond its fullscale range, all sensor drive clocks turn off for 0.5 ms. In the±10 g/±10.24 g range setting, the overrange protection activates
for input signals beyond approximately ±40 g (±25%), and forthe ±20 g/±20.48 g and ±40 g/±40.95 g range settings, thethreshold corresponds to about ±80 g (±25%).
When overrange protection occurs, the XOUT, YOUT, and ZOUT pinson the ADXL356 begin to drive to midscale. The ADXL357
floats toward zero, and first in, first out (FIFO) buffer begins
filling with this data.

SELF TESTThe ADXL356 and ADXL357 incorporate a self test featurethat effectively tests the mechanical and electronic system.
Enabling self test stimulates the sensor electrostatically to
produce an output corresponding to the test signal applied aswell as the mechanical force exerted. Only the z-axis response isspecified to validate device functionality.
In the ADXL356, drive the ST1 pin to VDDIO to invoke self test
mode. Then, by driving the ST2 pin to VDDIO, the ADXL356
applies an electrostatic force to the mechanical sensor andinduces a change in output in response to the force. The self test
delta (or response) is the difference in output voltage in thez-axis when ST2 is high vs. ST2 is low, while ST1 is asserted.
After the self test measurement is complete, bring both pins low
to resume normal operation.
The self test operation is similar in the ADXL357, except ST1and ST2 can be accessed through the SELF_TEST register(Register 0x2E).

Rev. 0 | Page 22 of 42

Data SheetADXL356/ADXL357

The ADXL356/ADXL357 use an analog, low-pass, antialiasing
filter to reduce out of band noise and to limit bandwidth. The
ADXL357 provides further digital filtering options to maintainexcellent noise performance at various ODRs.
The analog, low-pass antialiasing filter in the ADXL356/
ADXL357 provides a fixed bandwidth of approximately
1.5 kHz, the frequency at which the output response isattenuated by approximately 50%. The shape of the filter
response in the frequency domain is that of a sinc3 filter.
The ADXL356 x-axis, y-axis, and z-axis analog outputs include
an amplifier followed by a series 32 kΩ resistor, and output tothe XOUT, the YOUT, and the ZOUT pins, respectively.
The ADXL357 provides an internal 20-bit, Σ-Δ ADC to digitize
the filtered analog signal. Additional digital filtering (beyond theanalog, low-pass, antialiasing filter) consists of a low-pass digitaldecimation filter and a bypassable high-pass filter that supports
output data rates between 4 kHz and 3.906 Hz. The decimation
filter consists of two stages. The first stage is fixed decimation
with a 4 kHz ODR with a low-pass filter cutoff (50% reductionin output response) at about 1 kHz. A variable second stage
decimation filter is used for the 2 kHz output data rate and below(it is bypassed for 4 kHz ODR). Figure 61 shows the low-passfilter response with a 1 kHz corner (4 kHz ODR) for the
ADXL357. Note that Figure 61 does not include the fixed
frequency analog, low-pass, antialiasing filter with a fixedbandwidth of approximately 1.5 kHz.
0The ADXL357 also includes an interpolation filter, after thedecimation filters, that produces oversampled/upconverted dataand provides an external synchronization option. See the Data
Synchronization section for more details. Table 12 shows thedelay and attenuation relative to the programmed ODR.
0
–3
–10

–20

–30

–40

–50
0

9.8801100
FREQUENCY (kHz)15429-062

FILTER

The ADXL357 also includes an optional digital high-pass filter
with a programmable corner frequency. By default, the highpass filter is disabled. The high-pass corner frequency, where
the output is attenuated by 50%, is related to the ODR, and the
HPF_CORNER setting in the filter register (Register 0x28,
Bits[6:4]). Table 11 shows the HPF_CORNER response. Figure 62
and Figure 63 show the simulated high-pass filter response anddelay for a 10 Hz cutoff.

AMPLITUDE RELATIVE TO FULL SCALE (dB)The self test feature rejects externally applied acceleration andonly responds to the self test force, which allows an accurate
measurement of the self test, even in the presence of externalmechanical noise.

Figure 62. High-Pass Filter Pass-Band Response for a 4 kHz ODR and an
HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])

Group delay is the digital filter delay from the input to the ADC
until data is available at the interface (see the Filter section).
This delay is the largest component of the total delay fromsensor to serial interface.
40

32.2122–20

DELAY (ODR CYCLES)

DIGITAL LPF RESPONSE (dB)

–10

–30
–40
–50

30

20

10

1

10

100
INPUT FREQUENCY (Hz)

1k

10k

Figure 61. ADXL357 Digital Low-Pass Filter (LPF) Response for 4 kHz ODRThe ADXL357 pass band of the signal path relates to the
combined filter responses, including the analog filter previously
described, and the digital decimation filter/ODR setting. Table 10shows the delay associated with the decimation filter for eachsetting and provides the attenuation at the ODR/4 corner.
Rev. 0 | Page 23 of 42

1
0

0

100

9.8801FREQUENCY (kHz)

Figure 63. High-Pass Filter Delay Response for a 4 kHz ODR and an
HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])

15429-063–7015429-061–60

ADXL356/ADXL357

Data Sheet

Table 10. Digital Filter Group Delay and Profile
Delay
ODR (Cycles)
Time (ms)
2.52
0.63
2.00
1.00
1.78
1.78
1.63
3.26
1.57
6.27
1.54
12.34
1.51
24.18
1.49
47.59
1.50
96.25
1.50
189.581.50
384.31

Programmed ODR (Hz)4000
4000/2 = 2000
4000/4 = 1000
4000/8 = 500
4000/16 = 250
4000/32 = 125
4000/64 = 62.5
4000/128 ~ 31
4000/256 ~ 16
4000/512 ~ 8
4000/1024 ~ 4Attenuation
Decimator at ODR/4 (dB)
Full Path at ODR/4 (dB)
−3.44
−3.63
−2.21
−2.26
−1.92
−1.93
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83

Table 11. Digital High-Pass Filter Response
HPF_CORNER Register Setting(Register 0x28, Bits[6:4])
000
001
010
011
100
101
110

HPF_CORNER Frequency, −3 dB Point Relative to ODR Setting
Not applicable, no high-pass filter enabled
247 × 10−3 × ODR
62.084 × 10−3 × ODR
15.545 × 10−3 × ODR
3.862 × 10−3 × ODR
0.954 × 10−3 × ODR
0.238 × 10−3 × ODR−3 dB at 4 kHz ODR (Hz)
Off
9.88
2.48
0.62
0.15450.038160.00952

Table 12. Combined Digital Interpolation Filter and Decimation Filter Response
Interpolator Data Rate Resolution
Relative to 64 × ODR (Hz)64 × 4000 = 256000
64 × 2000 = 128000
64 × 1000 = 64000
64 × 500 = 32000
64 × 250 = 16000
64 × 125 = 8000
64 × 62.5 = 4000
64 × 31.25 = 2000
64 × 15.625 = 1000
64 × 7.8125 = 500
64 × 3.90625 = 250

Combined Interpolator/
Decimator Delay (ODR Cycles)
3.51661
3.01262.752
2.6346
2.57732.54732.53257
2.52452
2.520452.51942.51714

Combined Interpolator/
Decimator Delay (ms)
0.88
1.51
2.75
5.27
10.31
20.38
40.52
80.78
161.31
322.48644.39Rev. 0 | Page 24 of 42

Combined Interpolator/Decimator
Output Attenuation at ODR/4 (dB)
−6.18
−4.93
−4.66
−4.58
−4.55
−4.55
−4.55
−4.55
−4.55
−4.55
−4.55

Data SheetADXL356/ADXL357

SERIAL COMMUNICATIONSADXL357

SPI PROTOCOL
Wire the ADXL357 for SPI communication as shown in theconnection diagram in Figure 64. The SPI protocol timing isshown in Figure 65 to Figure 68. The timing scheme follows theclock polarity (CPOL) = 0 and clock phase (CPHA) = 0. The
SPI clock speed ranges from 100 kHz to 10 MHz.

PROCESSOR

CS

DOUT

MOSI

DOUT

MISO

DIN

SCLK

DOUT

15429-064

The 4-wire serial interface communicates in either the SPI or
I2C protocol. It affectively autodetects the format being used,requiring no configuration control to select the format.

Figure 64. 4-Wire SPI Connection

CS
1

2

3

4

5

6

7

8

A6

A5

A4

A3

A2

A1

A0 RW

9

10

11

12

13

14

15

16

D7

D6

D5

D4

D3

D2

D1

D0

15

16

MOSI
MISO

15429-065

SCLK

Figure 65. SPI Timing Diagram—Single-Byte Read

CS
1

2

3

A6

A5 A4

4

5

6

7

8

10

9

11

12

13

14

MOSI

A3 A2

A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0

MISO

15429-066

SCLK

Figure 66. SPI Timing Diagram—Single-Byte Write

CS
1

2

3

A6

A5 A4

4

5

6

7

8

9

10

11

12

13

14

15

16

17

SCLK
A3 A2

A1 A0 RWBYTE nBYTE 1D7 D6 D5 D4 D3 D2 D1 D0 D7

MISO

D0 D7 D6 D5 D4 D3 D2 D1 D0

15429-067

MOSI

Figure 67. SPI Timing Diagram—Multibyte Read

CS
1

2

3

A6

A5 A4

4

5

6

7

8

9

10

11

12

13

14

15

16

17

SCLK

A3 A2

A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0 D7

D0 D7 D6 D5 D4 D3 D2 D1 D0

MISO

Figure 68. SPI Timing Diagram—Multibyte Write

Rev. 0 | Page 25 of 42

15429-068

BYTE nBYTE 1MOSIADXL356/ADXL357

Data Sheet

I2C PROTOCOL

Figure 69 to Figure 71 detail the I2C protocol timing. The I2C
interface can be used on most buses operating in I2C standard
mode (100 kHz), fast mode (400 kHz), fast mode plus (1 MHz),and high speed mode (3.4 MHz). The ADXL357 I2C device ID
is as follows:

The ADXL357 supports point to point I2C communication.
However, when sharing an SDA bus, the ADXL357 may prevent
communication with other devices on that bus. If at any point,even when the ADXL357 is not being addressed, the 0x3A and
0x3B bytes (when the ADXL357 device ID is set to 0x1D), or
the 0xA6 and 0xA7 bytes (when the ADXL357 device ID is set
to 0x53) are transmitted on the SDA bus, the ADXL357 respondswith an acknowledge bit and pulls the SDA line down. For
example, this response can occur when reading or writing thedata bytes (0x3A/0x3B or 0xA6/0xA7) to another sensor on thebus. When the ADXL357 pulls the SDA line down, communication with other devices on the bus may be interrupted. To
resolve this, the ADXL357 must be connected to a separate SDA
bus, or the SCL pin must be switched high when communication
with the ADXL357 is not desired (it is normally grounded).

••

If other devices are connected to the same I2C bus, the nominal
operating voltage level of these other devices cannot exceed
VDDIO by more than 0.3 V. External pull-up resistors, RP, arenecessary for proper I2C operation.

READING ACCELERATION OR TEMPERATUREDATA FROM THE INTERFACE
Acceleration data is left justified and has a register address
order of most significant data to least significant data, whichallows the user to use multibyte transfers and to take only as
much data as required—either 8 bits, 16 bits, or 20 bits, plus themarker. Temperature data is 12 bits unsigned, right justified.
The ADXL357 temperature value is split over two bytes, but is
not double-buffered, meaning the value can update between
readings of the two registers. The data in XDATA, YDATA, andZDATA is always the most recent available. It is not guaranteedthat XDATA, YDATA, and ZDATA form a set corresponding to
one sample point in time. The routine used to retrieve the datafrom the device controls this data set continuity. If data transfers
are initiated when the DATA_RDY bit goes high and completes
in a time approximately equal to 1/ODR, XDATA, YDATA, andZDATA apply to the same data set.

The ADXL357 supports standard (100 kHz), fast (up to 1 MHz)and high speed (up to 3.4 MHz) data transfer modes when thebus parameters in Table 4 are met. There is no minimum SCL
frequency, with the exception that, when reading data, the clock
must be fast enough to read an entire sample set before new data
overwrites it. Single- or multiple-byte reads/writes are supported.
With the ASEL pin low, the I2C address for the device is 0x1D
and an alternate I2C address of 0x53 can be chosen by pulling
the ASEL pin high.
There are no internal pull-up or pull-down resistors for any
unused pins; therefore, there is no known state or default state
for the pins if left floating or unconnected. It is required that
SCLK/VSSIO be connected to ground when communicating to
the ADXL357 using I2C.

For multibyte read or write transactions through either serialinterface, the internal register address auto-increments. Whenthe top of the register address range, 0x3FF, is reached the autoincrement stops and does not wrap back to Hexadecimal
Address 0x00.

Due to communication speed limitations, the maximum output
data rate when using the 400 kHz I2C mode is 800 Hz, and it
scales linearly with a change in the I2C communication speed.
For example, using I2C at 100 kHz limits the maximum ODR to
200 Hz. Operation at an output data rate above the recommended
maximum may result in an undesirable effect on the acceleration
data, including missing samples or additional noise.

1

2

3

4

5

6

7

8

9

ASEL (pin) = 0, device address = 0x1D
ASEL (pin) = 1, device address = 0x53

The address auto-increment function disables when the FIFO
address is used, so that data can be read continuously from the
FIFO as a multibyte transaction. In cases where the starting
address of a multibyte transaction is less than the FIFO address,
the address auto-increments until reaching the FIFO address,
and then stops at the FIFO address.

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

SCL
REGISTER ADDRESS

A6 A5 A4 A3 A2 A1 A0 RW AK

0

REPEATSTART

A6 A5 A4 A3 A2 A1 A0 AK

DATA BYTE

DEVICE ADDRESS
A6 A5 A4 A3 A2 A1 A0 RW AK

0

STOP

D6 D5 D4 D3 D2 D1 D0

SINGLE BYTE READ

INDICATE SDA ISCONTROLLED BY ADXL357

2

Figure 69. I C Timing Diagram—Single-Byte Read

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

SCL
START

SDA

AK

DEVICE ADDRESSREGISTER ADDRESS

A6 A5 A4 A3 A2 A1 A0 RW AK

0DATA BYTE

A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK

Figure 70. I2C Timing Diagram—Single-Byte Write
Rev. 0 | Page 26 of 42

STOP

15429-069

SDA

DEVICE ADDRESS

15429-070

START

Data Sheet
1

2

3

ADXL356/ADXL357
4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 19

START

SDA

DEVICE ADDRESS
A6 A5 A4 A3 A2 A1 A0 RW AK

REGISTER ADDRESS0DATA BYTE 1

A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK D7

Figure 71. I2C Timing Diagram—Multibyte Write

Rev. 0 | Page 27 of 42

DATA BYTE n
D0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK

15429-071

SCL

ADXL356/ADXL357

Data Sheet

FIFO
Figure 72 shows the organization of the data in the FIFO. The
acceleration data is twos complement, 20-bit data. The FIFO
control logic inserts the two virtual bits (0b00) between the databits and the empty indicator bit. Bit 1 indicates that an attempt
was made to read an empty FIFO, and that the data is not valid
acceleration data. Bit 0 is a marker bit to identify the x-axis,
which allows a user to verify that the FIFO data was correctly
read. An acceleration data point for a given axis occupies one
FIFO location. The read pointer, RD_PTR, points to the oldest
stored data that was not read already from the interface (seeFigure 72). There are no physical x-acceleration, y-acceleration, or
z-acceleration data registers. This data also comes directly fromthe most recent data set in the FIFO, which points to by thez pointer, Z_PTR (see Figure 72).

FIFO operates in a stream mode; that is, when the FIFO
overruns new data overwrites the oldest data in the FIFO. A
read from the FIFO address guarantees that the three bytes
associated with the acceleration measurement on an axis allpertain to the same measurement. If the FIFO never overflows,
the data is always taken out in sets (multiples of three data
points).
There are 96 21-bit locations in the FIFO. Each location
contains 20 bits of data and a marker bit for the x-axis data. A
single-byte read from the FIFO address pops one location fromthe FIFO. A multibyte read to the FIFO location pops the FIFO
on the read of the first byte and every third byte read thereafter.

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

Z_PTR

Z19 Z18 Z17 Z16 Z15 Z14 Z13 Z12

Z11 Z10

Z9

Z8

Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

0

0

Z_PTR – 1

Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12

Y11 Y10 Y9

Y8

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

0

0

Z_PTR – 2

X19 X18 X17 X16 X15 X14 X13 X12

X11 X10 X9

X8

X7

X6

X5

X4

X3

X2

X1

X0

0

1

Z19 Z18 Z17 Z16 Z15 Z14 Z13 Z12

Z11 Z10

Z9

Z8

Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

0

0

Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12

Y11 Y10 Y9

Y8

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

0

0

X19 X18 X17 X16 X15 X14 X13 X12

X11 X10 X9

X8

X7

X6

X5

X4

X3

X2

X1

X0

0

1

RD_PTRVIRTUAL BITS
(NOT ALLOCATED IN THE FIFO)ACCELERATION DATAEMPTY INDICATOR
X-AXIS MARKER
ASCENDING SPI ADDRESSES

Figure 72. FIFO Data OrganizationRev. 0 | Page 28 of 42

15429-072

DATA SET. SAMPLE POINT
ASCENDINGIS THE SAME ACROSSA SINGLE X-AXIS, Y-AXIS, SPI ADDRESSESAND Z-AXIS DATA SET.

ASCENDING FIFO ADDRESSESZ_PTR + 1

Data SheetADXL356/ADXL357

INTERRUPTS
The status register (Register 0x04) contains five individual bits,
four of which can be mapped to either the INT1 pin, the INT2 pin,or both. The polarity of the interrupt, active high or active low,
is also selectable via the INT_POL bit in the range (Register 0x2C)
register. In general, the status register clears when read, but thisis not the case if the condition that caused the interrupt persists
after the read of the register. The definition of persist varies
slightly in each case, but it is described in the DATA_RDY,
DRDY Pin, FIFO_FULL, FIFO_OVR, and Activity sections.
The DRDY pin is similar to an interrupt pins (INTx) but clears
very differently. This case is also described.

DATA_RDY
The DATA_RDY bit is set when new acceleration data isavailable to the interface. It clears on a read of the status register.
It is not set again until acceleration data that is newer than thestatus register read is available.
Special logic on the clear of the DATA_RDY bit covers thecorner case where new data arrives during the read of the status
register. In this case, the data ready condition may be missedcompletely. This logic results in a delay of the clearing of
DATA_RDY of up to four 512 kHz cycles.

DRDY PIN
The DRDY pin is not a status register bit; it instead behaves
similar to an unmaskable interrupt. DRDY is set when new
acceleration data is available to the interface. It clears on a readof the FIFO, on a read of XDATA, YDATA, or ZDATA, or by anautoclear function that occurs approximately halfway between
output acceleration data sets.
DRDY is always active high. The INT_POL bit does not affect
DRDY. In external sync modes (EXT_SYNC = 01, EXT_SYNC =10), the first few DRDY pulses after initial synchronization canbe lost or corrupted. The length of this potential corruption isless than the group delay.

FIFO_FULL
The FIFO_FULL bit is set when the entries in the FIFO areequal to the setting of the FIFO_SAMPLES bits. It clears as
follows:••

A read of the status register clears FIFO_OVR. It is not set again
until data is lost subsequent to this data register read.

ACTIVITY
The activity bit (Register 0x04, Bit 3) is set when the measured
acceleration on any axis is above the ACT_THRESH bits for
ACT_COUNT consecutive measurements. An overthresholdcondition can shift from one axis to another on successive
measurements and is still counted toward the consecutive
ACT_COUNT count.
A read of the status register clears the activity bit (Register 0x04,
Bit 3), but it sets again at the end of the next measurement if theactivity bit (Register 0x04, Bit 3) conditions are still satisfied.

NVM_BUSY
The NVM_BUSY bit indicates that the nonvolatile memory(NVM) controller is busy, and it cannot be accessed to read,
write, or generate an interrupt.
A status register read that occurs after the NVM controller is nolonger busy clears NVM_BUSY.

EXTERNAL SYNCHRONIZATION AND
INTERPOLATION
There are three possible synchronization options for the ADXL357,
shown in Figure 73 to Figure 75. For clarity, the clock frequencies
and delays are drawn to scale. The labels in Figure 73 to Figure 75
are defined as follows:•••

Internal ODR is the alignment of the decimated output
data based on the internal clock.
ADC CLK shows the internal master clock rate
DRDY is an output indicator signaling a sample is ready.

The three modes are as follows:•••

No external synchronization (internal clocks used)
Synchronization with interpolation filter enabled
Sync with an external sync and clock signals, nointerpolation filter

EXT_SYNC = 00—No External Sync or Interpolation

If the number of entries in the FIFO is less than thenumber of samples indicated by the FIFO_SAMPLES bits,
which is only the case if sufficient data is read from the
FIFO.
On a read of the status register, but only when the entries
in the FIFO are less than the FIFO_SAMPLES bits.

FIFO_OVRThe FIFO_OVR bit is set when the FIFO is so far overrange thatdata is lost. The specified size of the FIFO is 96 locations. The
FIFO_OVR is set only when there is an attempt to write pastthis 96 location limit.

For this case, an internal clock that serves as the synchronization
master generates the data. No external signals are required, andthis is used commonly when the external processor retrieves
data from the device asynchronously and absolute synchronization
to an external source is not required. Use Register 0x28 to program
the ODR.
The device outputs a DRDY (active high) to signal that a new
sample is available, and data is retrieved from the real-timeregisters or the FIFO. The group delay is based on thedecimation setting as shown in Table 10.

Rev. 0 | Page 29 of 42

ADXL356/ADXL357

Data Sheet

EXT_SYNC = 10—External Sync with Interpolation

EXT_SYNC = 01—External Sync and External Clock, No
Interpolation Filter

In this case, the internal clock generates data; however, aninterpolation filter provides additional time resolution of 64
times the programmed ODR. Synchronization using interpolation
filters and an external ODR clock is commonly used when theexternal processor can provide a synchronization signal (whichis asynchronous to the internal clock) at the desired ODR.
Synchronization with the interpolation filter enabled(EXT_SYNC = 10) allows the nonsynchronous external clock to
output data most closely associated with the external clock
rising edge. The interpolation filter provides a frequency
resolution related to ODR (see Table 12).

In this case, an external source provides an external clock at afrequency of 4 × 64 × ODR. The external clock becomes themaster clock source for the device. In addition, an external
synchronization signal is needed to align the decimation filter
output to a specific clock edge, which provides full external
synchronization and is commonly used when a fixed external
clock captures and processes data, and asynchronous clocks are notallowed. When using multiple sensors, synchronization with an
external master clock is beneficial and requires time alignment.
When configured for EXT_SYNC = 01 with an ODR of 4 kHz,the user must supply an external clock at 1.024 MHz (64 × 4 ×
4 kHz) on the INT2 pin (Pin 13), and an external synchronization
on DRDY pin (Pin 14), as shown in Table 14.

The advantage of this mode is that data is available at a user definedsample rate and is asynchronous to the internal oscillator. The
disadvantage of this mode is that the group delay is increased,with increased attenuation at the band edge. Additionally,
because there is a limit to the time resolution, there is some
distortion related to the mismatch of the external sync relative
to the internal oscillator. This mismatch degrades spectral
performance. The group delay is based on the decimation
setting and interpolation setting (see Table 12). Table 13 shows
the delay between the SYNC signal (input) to DRDY (output).

Special restrictions when using this mode include the following:••••

Table 13. EXT_SYNC = 10, DRDY Delay
ODR_LPF
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0x10

Delay (Oscillator Cycles)
8
10
14
22
38
70
134
262
1031
2054
4102

An external clock (EXT_CLK) must be provided as well as
an external sync.
The frequency of EXT_CLK must be exactly 4 × 64 × ODR.
The width of sync must be a minimum of four EXT_CLK
periods.
The phase of sync must meet an approximate 25 ns setup
time to the EXT_CLK rising edge.

When using the EXT_SYNC mode and without providing sync,
the device runs on its own synchronization. Similarly, after
synchronization, the device continues to run synchronized to
the last sync pulse it received, which means that EXT_SYNC = 01
mode can be used with only a single synchronization pulse.
The interpolation filter provides a frequency resolution related to
the ODR (see Table 12). In this case, the data provided corresponds
to the external signal, which can be greater than the set ODR,
but the output pass band remains the same it was prior to theinterpolation filter.

Table 14. Multiplexing of INT2 and DRDY
EXT_CLK
0
0
1
1
0
0
1
1

Register or Bit Fields
EXT_SYNC[1:0]
INT_MAP[7:4]
00
0000
00
Not 000000
0000
00
Not 00002
01
0000
011
Not 0000
011
0000
011
Not 00002

INT2 (Pin 13)
Low
INT2
EXT_CLK
EXT_CLK
DRDY
INT2
EXT_CLK
EXT_CLK

0
0
1
1

10
101
101
101

DRDY
INT2
EXT_CLK
EXT_CLK1
20000
Not 0000
0000
Not 0000

Pins
DRDY (Pin 14)
DRDY
DRDY
DRDY
DRDY
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC

No DRDY.
No INT2, even though it is enabled.
Rev. 0 | Page 30 of 42

Comments
Synchronization is to the internal clocks, and there is no
external clock synchronization.

These options reset the digital filters on every
synchronization pulse and are not recommended.
External synchronization, no interpolation filter, andDRDY (active high) signals that data is ready. Data
represents a sample point group delay earlier in time.
External synchronization, interpolation filter, and DRDY
(active high) signals that data is ready. Data sample
group delay earlier in time.

Data SheetADXL356/ADXL357
SAMPLE POINTGROUP DELAY(FIXED RELATIVE TO DRDY)

INTERNAL ODR
15429-073

ADC MOD. CLK.
64× ODR
DRDY

Figure 73. External Synchronization Option—EXT_SYNC = 00, Internal Sync

SAMPLE POINTGROUP DELAY(FIXED RELATIVE TO SYNC)

INTERFACE SYNCHRONIZATION DELAY

INTERNAL ODR

15429-074

INTERPOLATOR
64× ODR
SYNC
110% ODRDRDYFigure 74. External Synchronization Option—EXT_SYNC = 10, External Sync, External Clock, Interpolation Filter

GROUP DELAY(FIXED RELATIVE TO SYNC)SAMPLE POINT
INTERNAL ODR
EXT_CLK(4 × 64) × SYNC
SYNCHRONIZE
LOST SAMPLE
DRDY

Figure 75. External Synchronization Option—EXT_SYNC = 01, External Sync, No Interpolation Filter

Rev. 0 | Page 31 of 42

15429-075

SYNC

ADXL356/ADXL357

Data SheetADXL357 REGISTER MAP
Note that while configuring the ADXL357 in an application, all configuration registers must be programmed before enabling measurementmode in the POWER_CTL register. When the ADXL357 is in measurement mode, only the following configurations can change: the
HPF_CORNER bits in the filter register, the INT_MAP register, the ST1 and ST2 bits in the SELF_TEST register, and the reset register.
Table 15. ADXL357 Register Map
Hex.
Addr.
0x00
0x01
0x02
0x03
0x04

Register Name
DEVID_AD
DEVID_MSTPARTIDREVID
Status

Bit 7

0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F

FIFO_ENTRIES
TEMP2
TEMP1
XDATA3XDATA2XDATA1YDATA3YDATA2YDATA1ZDATA3ZDATA2ZDATA1
FIFO_DATAOFFSET_X_H
OFFSET_X_L
OFFSET_Y_H
OFFSET_Y_L
OFFSET_Z_H
OFFSET_Z_L
ACT_EN
ACT_THRESH_H
ACT_THRESH_L
ACT_COUNTFilter
FIFO_SAMPLES
INT_MAP
Sync
Range
POWER_CTL
SELF_TEST
Reset

Reserved

Reserved
Reserved
ACT_EN2I2C_HS

Bit 6

Bit 5

Bit 4

Bit 3
Bit 2
Bit 1
Bit 0
DEVID_AD
DEVID_MSTPARTID
REVID
Reserved
NVM_
Activity
FIFO_OVR
FIFO_FULL DATA_RDY
BUSY
FIFO_ENTRIESReserved
Temperature, Bits[11:8]
Temperature, Bits[7:0]
XDATA, Bits[19:12]
XDATA, Bits[11:4]
XDATA, Bits[3:0]
Reserved
YDATA, Bits[19:12]
YDATA, Bits[11:4]
YDATA, Bits[3:0]
Reserved
ZDATA, Bits[19:12]
ZDATA, Bits[11:4]
ZDATA, Bits[3:0]
Reserved
FIFO_DATAOFFSET_X, Bits[15:8]
OFFSET_X, Bits[7:0]
OFFSET_Y, Bits[15:8]
OFFSET_Y, Bits[7:0]
OFFSET_Z, Bits[15:8]
OFFSET_Z, Bits[7:0]
Reserved
ACT_Z
ACT_Y
ACT_X
ACT_THRESH, Bits[15:8]
ACT_THRESH, Bits[7:0]
ACT_COUNTHPF_CORNERODR_LPFFIFO_SAMPLESOVR_EN2 FULL_EN2 RDY_EN2 ACT_EN1 OVR_EN1
FULL_EN1 RDY_EN1
Reserved
EXT_CLK
EXT_SYNC
INT_POL
Reserved
Range
Reserved
DRDY_OFF TEMP_OFF Standby
Reserved
ST2
ST1
Reset

Rev. 0 | Page 32 of 42

Reset
0xAD
0x1D
0xED
0x01
0x00

R/W
R
R
R
R
R

0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x60
0x00
0x00
0x81
0x01
0x00
0x00

R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W

Data SheetADXL356/ADXL357

REGISTER DEFINITIONSThis section describes the functions of the ADXL357 registers. The ADXL357 powers up with the default register values, as shown in the
Reset column of Table 15.

ANALOG DEVICES ID REGISTER
This register contains the Analog Devices ID, 0xAD.

Address: 0x00, Reset: 0xAD, Name: DEVID_AD
Table 16. Bit Descriptions for DEVID_AD
Bits
[7:0]

Bit Name
DEVID_AD

Settings

Description
Analog Devices ID

Reset
0xAD

AccessR

ANALOG DEVICES MEMS ID REGISTER
This register contains the Analog Devices MEMS ID, 0x1D.

Address: 0x01, Reset: 0x1D, Name: DEVID_MST
Table 17. Bit Descriptions for DEVID_MST
Bits
[7:0]

Bit Name
DEVID_MST

Settings

Description
Analog Devices MEMS ID

Reset
0x1D

AccessR

DEVICE ID REGISTER
This register contains the device ID, 0xED (355 octal).

Address: 0x02, Reset: 0xED, Name: PARTID
Table 18. Bit Descriptions for PARTID
Bits
[7:0]

Bit Name
PARTID

Settings

Description
Device ID (355 octal)

Reset
0xED

AccessR

PRODUCT REVISION ID REGISTER
This register contains the product revision ID, beginning with 0x00 and incrementing for each subsequent revision.

Address: 0x03, Reset: 0x01, Name: REVID
Table 19. Bit Descriptions for REVID
Bits
[7:0]

Bit Name
REVID

Settings

Description
Mask revision

Reset
0x01

AccessR

STATUS REGISTER
This register includes bits that describe the various conditions of the ADXL357.

Address: 0x04, Reset: 0x00, Name: Status
Table 20. Bit Descriptions for Status
Bits
[7:5]
4
3
2
1
0

Bit Name
Reserved
NVM_BUSY
Activity
FIFO_OVR
FIFO_FULLDATA_RDY

Settings

Description
Reserved.
NVM controller is busy with either refresh, programming, or built in, self test (BIST).
Activity, as defined in the ACT_THRESH_x and ACT_COUNT registers, is detected.
FIFO has overrun, and the oldest data is lost.
FIFO watermark is reached.
A complete x-axis, y-axis, and z-axis measurement was made and results can be read.

Rev. 0 | Page 33 of 42

Reset
0x0
0x0
0x0
0x0
0x0
0x0

AccessR
R
R
R
R
R

ADXL356/ADXL357

Data Sheet

FIFO ENTRIES REGISTER
This register indicates the number of valid data samples present in the FIFO buffer. This number ranges from 0 to 96.

Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES
Table 21. Bit Descriptions for FIFO_ENTRIES
Bits
7
[6:0]

Bit Name
Reserved
FIFO_ENTRIES

Settings

Description
Reserved
Number of data samples stored in the FIFO

Reset
0x0
0x0

AccessR
R

TEMPERATURE DATA REGISTERS
These two registers contain the uncalibrated temperature data. The nominal intercept is 1852 LSB at 25°C and the nominal slope is−9.05 LSB/°C. TEMP2 contains the four most significant bits, and TEMP1 contains the eight least significant bits of the 12-bit value. The
ADXL357 temperature value is not double-buffered, meaning the value can update between reading of the two registers.

Address: 0x06, Reset: 0x00, Name: TEMP2
Table 22. Bit Descriptions for TEMP2
Bits
[7:4]
[3:0]

Bit Name
Reserved
Temperature, Bits[11:8]

Settings

Description
Reserved.
Uncalibrated temperature data

Reset

Access0x0

R

Description
Uncalibrated temperature data

Reset
0x0

AccessR

Address: 0x07, Reset: 0x00, Name: TEMP1
Table 23. Bit Descriptions for TEMP1
Bits
[7:0]

Bit Name
Temperature, Bits[7:0]

Settings

X-AXIS DATA REGISTERS
These three registers contain the x-axis acceleration data. Data is left justified and formatted as twos complement.

Address: 0x08, Reset: 0x00, Name: XDATA3
Table 24. Bit Descriptions for XDATA3
Bits
[7:0]

Bit Name
XDATA, Bits[19:12]

Settings

Description
X-axis data

Reset
0x0

AccessR

Description
X-axis data

Reset
0x0

AccessR

Description
X-axis data
Reserved

Reset
0x0
0x0

AccessR
R

Address: 0x09, Reset: 0x00, Name: XDATA2Table 25. Bit Descriptions for XDATA2
Bits
[7:0]

Bit Name
XDATA, Bits[11:4]

Settings

Address: 0x0A, Reset: 0x00, Name: XDATA1
Table 26. Bit Descriptions for XDATA1
Bits
[7:4]
[3:0]

Bit Name
XDATA, Bits[3:0]
Reserved

Settings

Rev. 0 | Page 34 of 42

Data SheetADXL356/ADXL357

Y-AXIS DATA REGISTERS
These three registers contain the y-axis acceleration data. Data is left justified and formatted as twos complement.

Address: 0x0B, Reset: 0x00, Name: YDATA3
Table 27. Bit Descriptions for YDATA3
Bits
[7:0]

Bit Name
YDATA, Bits[19:12]

Settings

Description
Y-axis data

Reset
0x0

AccessR

Description
Y-axis data

Reset
0x0

AccessR

Description
Y-axis data
Reserved

Reset
0x0
0x0

AccessR
R

Address: 0x0C, Reset: 0x00, Name: YDATA2Table 28. Bit Descriptions for YDATA2
Bits
[7:0]

Bit Name
YDATA, Bits[11:4]

Settings

Address: 0x0D, Reset: 0x00, Name: YDATA1
Table 29. Bit Descriptions for YDATA1
Bits
[7:4]
[3:0]

Bit Name
YDATA, Bits[3:0]
Reserved

Settings

Z-AXIS DATA REGISTERS
These three registers contain the z-axis acceleration data. Data is left justified and formatted as twos complement.

Address: 0x0E, Reset: 0x00, Name: ZDATA3
Table 30. Bit Descriptions for ZDATA3
Bits
[7:0]

Bit Name
ZDATA, Bits[19:12]

Settings

Description
Z-axis data

Reset
0x0

AccessR

Description
Z-axis data

Reset
0x0

AccessR

Description
Z-axis data
Reserved

Reset
0x0
0x0

AccessR
R

Address: 0x0F, Reset: 0x00, Name: ZDATA2Table 31. Bit Descriptions for ZDATA2
Bits
[7:0]

Bit Name
ZDATA, Bits[11:4]

Settings

Address: 0x10, Reset: 0x00, Name: ZDATA1
Table 32. Bit Descriptions for ZDATA1
Bits
[7:4]
[3:0]

Bit Name
ZDATA, Bits[3:0]
Reserved

Settings

Rev. 0 | Page 35 of 42

ADXL356/ADXL357

Data Sheet

FIFO ACCESS REGISTER
Address: 0x11, Reset: 0x00, Name: FIFO_DATA
Read this register to access data stored in the FIFO.
Table 33. Bit Descriptions for FIFO_DATA
Bits
[7:0]

Bit Name
FIFO_DATA

Settings

Description
FIFO data is formatted to 24 bits, 3 bytes, most significant byte first. A read to thisaddress pops an effective three equal byte words of axis data from the FIFO. Two
subsequent reads or a multibyte read completes the transaction of this data onto theinterface. Continued reading or a sustained multibyte read of this field continues to
pop the FIFO every third byte. Multibyte reads to this address do not increment theaddress pointer. If this address is read due to an auto-increment from the previous
address, it does not pop the FIFO. Instead, it returns zeros and increments onto thenext address.

Reset
0x0

Access
R

Reset
0x0

Access
R/W

Reset
0x0

Access
R/W

Reset
0x0

Access
R/W

Reset
0x0

AccessR/W

X-AXIS OFFSET TRIM REGISTERS
Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H
Table 34. Bit Descriptions for OFFSET_X_H
Bits
[7:0]

Bit Name
OFFSET_X,
Bits[15:8]

Settings

Description
Offset added to x-axis data after all other signal processing. Data is in twos complement
format. The bit significance of OFFSET_X[15:0] matches the significance of XDATA[19:4].

Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L
Table 35. Bit Descriptions for OFFSET_X_L
Bits
[7:0]

Bit Name
OFFSET_X,
Bits[7:0]

Settings

Description
Offset added to x-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_X[15:0] matches the significance of XDATA[19:4].

Y-AXIS OFFSET TRIM REGISTERS
Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H
Table 36. Bit Descriptions for OFFSET_Y_H
Bits
[7:0]

Bit Name
OFFSET_Y,
Bits[15:8]

Settings

Description
Offset added to y-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Y[15:0] matches the significance of YDATA[19:4].

Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L
Table 37. Bit Descriptions for OFFSET_Y_L
Bits
[7:0]

Bit Name
OFFSET_Y,
Bits[7:0]

Settings

Description
Offset added to y-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Y[15:0] matches the significance of YDATA[19:4].

Rev. 0 | Page 36 of 42

Data SheetADXL356/ADXL357

Z-AXIS OFFSET TRIM REGISTERS
Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H
Table 38. Bit Descriptions for OFFSET_Z_H
Bits
[7:0]

Bit Name
OFFSET_Z,
Bits[15:8]

Settings

Description
Offset added to z-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Z[15:0] matches the significance of ZDATA[19:4].

Reset
0x0

Access
R/W

Reset
0x0

AccessR/W

Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L
Table 39. Bit Descriptions for OFFSET_Z_L
Bits
[7:0]

Bit Name
OFFSET_Z,
Bits[7:0]

Settings

Description
Offset added to z-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Z[15:0] matches the significance of ZDATA[19:4].

ACTIVITY ENABLE REGISTER
Address: 0x24, Reset: 0x00, Name: ACT_EN
Table 40. Bit Descriptions for ACT_EN
Bits
[7:3]
2
1
0

Bit Name
Reserved
ACT_Z
ACT_Y
ACT_X

Settings

Description
Reserved.
Z-axis data is a component of the activity detection algorithm.
Y-axis data is a component of the activity detection algorithm.
X-axis data is a component of the activity detection algorithm.

Reset
0x0
0x0
0x0
0x0

Access
R
R/W
R/W
R/W

ACTIVITY THRESHOLD REGISTERS
Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H
Table 41. Bit Descriptions for ACT_THRESH_H
Bits
[7:0]

Bit Name
ACT_THRESH[15:8]

Settings

Description
Threshold for activity detection. Acceleration magnitude must be above
ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned
magnitude. The significance of ACT_THRESH[15:0] matches the significanceof XDATA[18:3], YDATA[18:3], and ZDATA[18:3].

Reset
0x0

Access
R/W

Reset
0x0

Access
R/W

Reset
0x1

AccessR/W

Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L
Table 42. Bit Descriptions for THRESH_ACT_X_L
Bits
[7:0]

Bit Name
ACT_THRESH[7:0]

Settings

Description
Threshold for activity detection. The acceleration magnitude must be greaterthan the value in ACT_THRESH to trigger the activity counter. ACT_THRESH isan unsigned magnitude. The significance of ACT_THRESH[15:0] matches thebit significance of XDATA[18:3], YDATA[18:3], and ZDATA[18:3].

ACTIVITY COUNT REGISTER
Address: 0x27, Reset: 0x01, Name: ACT_COUNT
Table 43. Bit Descriptions for ACT_COUNT
Bits
[7:0]

Bit Name
ACT_COUNT

Settings

Description
Number of consecutive events above threshold (from ACT_THRESH) required todetect activity

Rev. 0 | Page 37 of 42

ADXL356/ADXL357

Data SheetFILTER SETTINGS REGISTER
Address: 0x28, Reset: 0x00, Name: Filter
Use this register to specify parameters for the internal high-pass and low-pass filters.
Table 44. Bit Descriptions for Filter
Bits
7
[6:4]

Bit Name
Reserved
HPF_CORNER

Settings

000
001
010
011
100
101
110
[3:0]

ODR_LPF
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010

Description
Reserved−3 dB filter corner for the first-order, high-pass filter relative to the ODR
Not applicable, no high-pass filter enabled
247 × 10−3 × ODR
62.084 × 10−3 × ODR
15.545 × 10−3 × ODR
3.862 × 10−3 × ODR
0.954 × 10−3 × ODR
0.238 × 10−3 × ODRODR and low-pass filter corner4000 Hz and 1000 Hz
2000 Hz and 500 Hz
1000 Hz and 250 Hz
500 Hz and 125 Hz
250 Hz and 62.5 Hz
125 Hz and 31.25 Hz
62.5 Hz and 15.625 Hz
31.25 Hz and 7.813 Hz
15.625 Hz and 3.906 Hz
7.813 Hz and 1.953 Hz
3.906 Hz and 0.977 Hz

Reset
0x0
0x0

Access
R
R/W

0x0

R/W

FIFO SAMPLES REGISTER
Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES
Use the FIFO_SAMPLES value to specify the number of samples to store in the FIFO. The default value of this register is 0x60 to avoid
triggering the FIFO watermark interrupt.
Table 45. Bit Descriptions for FIFO_SAMPLES
Bits
7
[6:0]

Bit Name
Reserved
FIFO_SAMPLES

Settings

Description
Reserved.
Watermark number of samples stored in the FIFO that triggers a FIFO_FULL condition.
Values range from 1 to 96.

Reset
0x0
0x60

AccessR
R/W

INTERRUPT PIN (INTx) FUNCTION MAP REGISTER
Address: 0x2A, Reset: 0x00, Name: INT_MAP
The INT_MAP register configures the interrupt pins. Bits[7:0] select which functions generate an interrupt on the INT1 and INT2 pins.
Multiple events can be configured. If the corresponding bit is set to 1, the function generates an interrupt on the interrupt pins.
Table 46. Bit Descriptions for INT_MAP
Bits
7
6
5
4
3
2
1
0

Bit Name
ACT_EN2OVR_EN2
FULL_EN2
RDY_EN2
ACT_EN1OVR_EN1
FULL_EN1
RDY_EN1

Settings

Description
Activity interrupt enable on INT2
FIFO_OVR interrupt enable on INT2
FIFO_FULL interrupt enable on INT2
DATA_RDY interrupt enable on INT2
Activity interrupt enable on INT1
FIFO_OVR interrupt enable on INT1
FIFO_FULL interrupt enable on INT1
DATA_RDY interrupt enable on INT1
Rev. 0 | Page 38 of 42

Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0

Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Data SheetADXL356/ADXL357

DATA SYNCHRONIZATION
Address: 0x2B, Reset: 0x00, Name: Sync
Use this register to control the external timing triggers.
Table 47. Bit Descriptions for Sync
Bits
[7:3]
2

Bit Name
Reserved
EXT_CLK[1:0]

EXT_SYNC

Settings

00
01
10
11

Description
Reserved.
Enable external clock. See Table 14. Multiplexing of INT2 and DRDY Table 14 forconfiguration details.
Enable external sync control.
Internal sync.
External sync, no interpolation filter. After synchronization, and for EXT_SYNC within
specification, DATA_RDY occurs on EXT_SYNC.
External sync, interpolation filter, next available data indicated by DATA_RDY 14 to8204 oscillator cycles later (longer delay for higher ODR_LPF setting), data represents
a sample point group delay earlier in time.
Reserved.

Reset
0x0
0x0

Access
R
R/W

0x0

R/W

I2C SPEED, INTERRUPT POLARITY, AND RANGE REGISTER
Address: 0x2C, Reset: 0x81, Name: Range
Table 48. Bit Descriptions for Range
Bits
7

Bit Name
I2C_HS

Settings
1
0

6

INT_POL
0
1

[5:2]
[1:0]

Reserved
Range
01
10
11

Description
I2C speed.
High speed mode.
Fast mode.
Interrupt polarity.
INT1 and INT2 are active low.
INT1 and INT2 are active high.
Reserved.
Range.
±10 g.
±20 g.
±40 g.

Reset
0x1

Access
R/W

0x0

R/W

0x0
0x1

R
R/W

POWER CONTROL REGISTER
Address: 0x2D, Reset: 0x01, Name: POWER_CTL
Table 49. Bit Descriptions for POWER_CTL
Bits
[7:3]
2
1

Bit Name
Reserved
DRDY_OFF
TEMP_OFF0StandbySettings

1

0

Description
Reserved.
Set to 1 to force the DRDY output to 0 in modes where it is normally signal data ready.
Set to 1 to disable temperature processing. Temperature processing is also disabled
when standby = 1.
Standby or measurement mode.
Standby mode. In standby mode, the device is in a low power state, and thetemperature and acceleration datapaths are not operating. In addition, digital
functions, including FIFO pointers, reset. Changes to the configuration setting of thedevice must be made when standby = 1. An exception is a high-pass filter that can bechanged when the device is operating.
Measurement mode.

Rev. 0 | Page 39 of 42

Reset
0x0
0x0
0x0

Access
R
R/W
R/W

0x1

R/W

ADXL356/ADXL357

Data Sheet

SELF TEST REGISTER
Address: 0x2E, Reset: 0x00, Name: SELF_TEST
Refer to the Self Test section for more information on the operation of the self test feature.
Table 50. Bit Descriptions for SELF_TEST
Bits
[7:2]
1
0

Bit Name
Reserved
ST2
ST1

Settings

Description
Reserved.
Set to 1 to enable self test force
Set to 1 to enable self test mode

Reset
0x0
0x0
0x0

AccessR
R/W
R/W

RESET REGISTER
Address: 0x2F, Reset: 0x00, Name: Reset
Table 51. Bit Descriptions for Reset
Bits
[7:0]

Bit Name
Reset

Settings

Description
Write Code 0x52 to resets the device, similar to a power-on reset (POR)

Rev. 0 | Page 40 of 42

Reset
0x0

AccessW

Data SheetADXL356/ADXL357

PCB FOOTPRINT PATTERN
Figure 76 shows the PCB footprint pattern and dimensions in millimeters.
3.22mm0.68mm
0.70mm

3.80mm14 PLCS
1.8mm × 0.68mm

3.80mmFigure 76. PCB Footprint Pattern and Dimensions in Millimeters

Rev. 0 | Page 41 of 42

15429-076

4.5mm

0.70mmADXL356/ADXL357

Data SheetOUTLINE DIMENSIONSDETAIL A

6.25
6.00 SQ
5.85

0.80
BSC

2.25
2.05
1.85

1.674 BSC
0.510 REF

0.30 SQ
12(PIN 1 INDEX)

14

11

1

DETAIL A

5.60
SQ

3.81
REF

0.508
BSC
4

8
7

PKG-004554

R 0.25(4 PLCS)TOP VIEW

0.10 BSC

R 0.203(14 PLCS)

0.15
BSC

5

BOTTOM VIEW

SIDE VIEW

2.20 REF

2.54 REF

0.914
BSC
05-27-2016-B

R 0.103(14 PLCS)

Figure 77. 14-Terminal Ceramic Leadless Chip Carrier [LCC](E-14-1)
Dimensions shown in millimeters

ORDERING GUIDE
Model1
ADXL356BEZADXL356BEZ-RL
ADXL356BEZ-RL7
ADXL356CEZADXL356CEZ-RL
ADXL356CEZ-RL7
ADXL357BEZADXL357BEZ-RL
ADXL357BEZ-RL7
EVAL-ADXL356BZ

OutputMode
AnalogAnalogAnalogAnalogAnalogAnalogDigitalDigitalDigitalMeasurement
Range (g)±10, ±20±10, ±20±10, ±20±10, ±40±10, ±40±10, ±40±10.24, ±20.48, ±40.96±10.24, ±20.48, ±40.96±10.24, ±20.48, ±40.96

Specified
Voltage (V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3

Temperature Range−40°C to +125°C−40°C to +125°C−40°C to +125°C−40°C to +125°C−40°C to +125°C−40°C to +125°C−40°C to +125°C−40°C to +125°C−40°C to +125°C

EVAL-ADXL356CZEVAL-ADXL357Z
1

Z = RoHS Compliant Part.

©2017 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.
D15429-0-2/17(0)Rev. 0 | Page 42 of 42

Package Description
14-Terminal LCC
14-Terminal LCC, 13” Reel
14-Terminal LCC, 7” Reel
14-Terminal LCC
14-Terminal LCC, 13” Reel
14-Terminal LCC, 7” Reel
14-Terminal LCC
14-Terminal LCC
14-Terminal LCC
Evaluation Board for
ADXL356B
Evaluation Board for
ADXL356C
Evaluation Board for ADXL357

Package
OptionE-14-1
E-14-1
E-14-1
E-14-1
E-14-1
E-14-1
E-14-1
E-14-1
E-14-1