Novel Trench Power MOSFETs and Structure‑based
Compact Model for High Efficiency Electronics
Application
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その他のタイトル

学位授与年度
学位授与番号URL

小林 研也
高効率エレクトロニクス応用のための新構造トレン
チパワーMOSFETと素子構造に基づいたコンパクトモ
デルの開発
令和元年度
17104甲工第477号
http://hdl.handle.net/10228/00007860

Academic Year 2019 DISSERTATION

Novel Trench Power MOSFETs andStructure-based Compact Model for High
Efficiency Electronics Application
高効率エレクトロニクス応用のための新構造トレンチパワーMOSFET と素子構造に基づいたコンパクトモデルの開発

Kenya Kobayashi

Graduate School of Engineering,
Kyushu Institute of Technology
1-1 Sensui-cho, Tobata-ku, Kitakyushu-city, 804-8550, JAPANA dissertation submitted in partial fulfillment of the requirements
for the degree of Doctor of Philosophy
Copyright © 2019 by Kenya Kobayashi

ACKNOWLEDGEMENTFirst of all, I would like to express my sincere gratitude to my supervisors.
Prof. Ichiro Omura gave me an opportunity to study and provided a research theme.
When he invited me as a doctoral course student, in Bruges, I felt much honored. His
motivation, knowledge, and continuous support helped and promoted my hard study. I
could not complete this dissertation without his patient direction for six years.
Prof. Satoshi Matsumoto gave me various advices with his expertise. He generously
supported me by the end of public hearing and final examination. I was very glad forbeing helped by him who met in a same committee of the IEEJ in the 2000s.
I would like to thank my co-advisors: Prof. Mengu Cho and Prof. Kazuhiro Toyoda,
for their insightful comments to deepen my research.
I was encouraged by Prof. Hiroshi Kaneta, Associate Prof. Kazunori Hasegawa,
Assistant Prof. Akihiko Watanabe, and Associate Prof. Seiya Abe, whenever I visited to
Tobata campus or Wakamatsu campus. I thank for their warmth.
I would specially like to thank Associate Prof. Masanori Tsukuda and Dr. Masahiro
Tanaka; they were senior students of the doctoral course. They encouraged me every
time in various place, e.g., venues of international or domestic conference, a private
drinking party. Their individual supports and advices were essential to me from entrance
examination to during long student life.
I would greatly like to thank Ms. Miyo Iwahori. Because I could not go to thelaboratory very well, she contacted me frequently and took care of me every time: a lotof documentation, payment of expenses, campus life guide, cheering message, etc.
I also would like to thank Mr. Masaki Sudo who was co-researcher and supported
me by TCAD simulation and Mathcad calculation.
I would like to thank my former Prof. Akihiko Yoshikawa and former mentor Dr.
Shigeki Yamaga in Chiba University; they directed me firstly toward a science world.
I thank my colleagues in Toshiba Electronic Devices & Storage Corporation: Mr.
Hiroaki Kato, Mr. Toshifumi Nishiguchi, Ms. Saya Shimomura, Mr. Tetsuya Ohno, Dr.
Tatsuya Nishiwaki, Mr. Kikuo Aida, Mr. Kentaro Ichinoseki, Mr. Kohei Oasa, Mr.
Shunsuke Katoh, Mr. Takahiro Kawano, Mr. Yoshitaka Hokomoto, Mr. Yusuke
Kawaguchi, and a lot of engineers, for their great cooperation and useful discussions inithe FP-MOSFET R&D. Furthermore, I thank my current/former colleagues: Dr. Daiki
Iino, Dr. Tomoko Matsudai, and Prof. Wataru Saito for their encouragement andsuggestions to manage both doctoral course and company's work.
I also thank my current/former bosses in Toshiba Electronic Devices & Storage
Corporation: Mr. Sadayuki Jimbo, Mr. Hiroyuki Kamijo, Mr. Akihiko Osawa, and Dr.
Naoto Miyashita, for their warm encouragement throughout six years.
I also thank my former co-workers and bosses in NEC corporation, NEC Electronics
Corporation, and Renesas Electronics Corporation: Dr. Yoshinao Miura, Mr. Hitoshi
Ninomiya, Dr. Yoshiya Kawashima, Mr. Hisanori Okubo, Mr. Satoru Tokuda, Mr. Takuya
Yamaguchi, Mr. Shinzo Tsuboi, and Mr. Masami Sawada, for the SJ-UMOSFETs and theFP-MOSFETs R&D; Mr. Atsushi Kaneko, Mr. Yoshimitsu Murase, Mr. Hideo Yamamoto,
Mr. Kazumi Yamaguchi, Mr. Michiaki Maruoka, Mr. Yasuhito Ninomiya, Mr. Mitsuasa
Takahashi, Mr. Keizo Hagimoto, and Mr. Tomonobu Yoshitake, for the U-MOSFETs andthe D-MOSFETs R&D; Mr. Tomohiro Hamajima, Mr. Kensuke Okonogi, Mr. Hiroaki
Kikuchi, Mr. Tomohisa Kitano, Mr. Kenichi Arai, Mr. Tsukasa Ohoka, and Mr. Junichi
Takahashi, for the SOI power devices R&D; and a lot of engineers and researchers. They
kindly helped me, encouraged me, or discussed a lot with me, during the time we spent
together.
Finally I am grateful to my wife, daughters, parents, sister, and house cat: Hiromi,
Rio, Mano, Yoshitada, Kesami, Keiko, and Panda, for their cheering during six years.
Their relaxed expectation made me patient and I could finally complete this hard work.

ii

ABSTRACT
Actions for sustainable society realization, that is a global climate change mitigation
and related energy problem solutions, are being executed in various fields. It is publicly
said that it is necessary to reduce emissions of a carbon dioxide (CO2) to approximately
50% of the present level by 2050. Among various measures for accomplishment of the
scenario, an improvement effect by the contribution of power electronics is greatly
expected, as an electric energy sector. A power semiconductor device is a fundamental
device underpinning the power electronics technology. The power semiconductor devices
are widely used in many applications, and the device performance is being improved
continually to get the high efficiency. In a category of low-voltage (10–250 V) and highfrequency (10 kHz–1 MHz) operation, silicon power MOSFETs (Metal Oxide Field EffectTransistors) are widely used. For the market demand for low power loss and highefficiency, the power MOSFETs' research and development in many aspects including adevice structure, a manufacturing process, and a packaging technology are performed
continuously. In this study, novel structures to achieve the low-power-loss MOSFET were
proposed and experimented. In addition, structure-based compact models to enable thepower loss calculation were newly constructed.
In chapter 1, performance requirements for the power MOSFETs were revealed, andthe elements which decide the power loss in an application circuit were classified.
Challenges for the low power loss in the low-voltage devices and directions for the novel
structure development were described. In addition to a conduction loss improvement thatcomes from an on-resistance (RONA) reduction with a necessary breakdown voltage
maintained, it was pointed out that the electric charge accumulated to an output
capacitance, which affects to a switching loss, was significant issue particularly in highspeed switching. In the low-power-loss structure design, it was described that theconstruction of the capacitance model is very important as well as the RONA model.
In chapter 2, in a planar gate double-diffused MOSFET (D-MOSFET) and a trenchgate MOSFET (U-MOSFET), the basic structures and the RONA components were
described. The conventional RONA models were analyzed, restructured, classified, andcompared with developed devices. Moreover, the device performance limit was indicated.
In chapter 3, in a superjunction U-MOSFET (SJ-UMOSFET) and a field-plate UMOSFET (FP-MOSFET) which are evolution structure of the U-MOSFET, the basic
structures, the basic principles, and the RONA components were described. The
conventional RONA models were analyzed, restructured, newly classified, and comparedwith developed devices. Moreover, the device performance limit was indicated.
iii

In chapter 4, components of the parasitic capacitances that are important to theswitching loss design of the low-voltage MOSFET were clarified. For the latest slant FPMOSFET that structure was complicated, model equations of output capacitance (Coss)and reverse transfer capacitance (Crss) were constructed based on the device structuralparameters.
In chapter 5, a validity of the model that derived in chapter 4 was verified. Drain
voltage dependences of Coss and Crss, for 100-V-class D-MOSFET and slant FP-MOSFET,
were analyzed. An accuracy of the model was identified using simulation results of TCAD
(Technology Computer Aided Design). In addition, each component for the switching loss
analysis was derived from the constructed capacitance model.
In chapter 6, the power loss analysis of the slant FP-MOSFET was carried out basedon the models described in previous chapters, and the results were compared with theconventional device. It was revealed that the performance of the slant FP-MOSFET was
superior in high-frequency use. In addition, by adopting a gate connection field-plate
structure, it was found that the high efficiency is achieved in low-frequency and highcurrent use.
In chapter 7, by utilizing the RONA models and the capacitance models of the slant
FP-MOSFET, the device performance limit was pursued. As a result, it became clear thatthe efficiency for the high-frequency switching application can be improved by over 50%
and that for the low-frequency and high-current application can be improved by over70%.
In chapter 8, as conclusion, the proposal of the novel FP-MOSFET structure, theconstruction of the compact model, and the possibility of the device performance
improvement that is greater than 50% were described.
This dissertation describes, for the low-power-loss MOSFET that is key device toprevent the CO2 emission, the construction of the device physics based compact model,
which can design in short term without experiment and simulation. This indicates a
guiding principle of the future low-power-loss MOSFET design by the compact model forthe first time. By applying the proposed compact model, it becomes clear that the FPMOSFET structure has an enough room for the performance improvement and thisdevice should advance the research and development. It is expected this compact model
can greatly contribute to higher efficiency power electronics.

iv

日本語概要地球規模の気候変動抑制やエネルギー問題への対応など、持続可能社会の実現に向けての取り組みが様々な分野で行われており、2050 年までに二酸化炭素排出量を現状レベルの約 50%まで削減する必要があると公的に言われている。この目標達成に向けた施策の中で、電気エネルギーのセクターでは、パワーエレクトロニクスの貢献による効率改善効果が大きく期待されている。パワーエレクトロニクス技術を支える基幹デバイスがパワー半導体デバイスである。パワー半導体デバイスは広範囲なシステムや機器に使用されおり、高効率化に向けてデバイス性能改善が継続的に行われている。パワー半導体デバイスの中でも低 電 圧 (数 10V ～250V)、 高 周 波数 動 作 (数 10kHz～ 1MHz)の カテ ゴ リで は 、 パワ ー
MOSFET(金属酸化膜電界効果トランジスタ)が広く使用されており、低損失・高効率化に向けて、デバイス構造、製造プロセス、実装技術など多方面での研究が行われている。本研究では、パワーMOSFET の低損失化を実現する新デバイス構造を提案し、試作を行うとともに、損失計算を可能とする新しいコンパクトモデルを構築した。
本論文の 1 章では、パワーMOSFET への要求性能を明らかにし、想定する応用回路において損失を決定する要素を分類、低耐圧デバイスの低損失化に必要な課題を明らかにし、新構造開発に向けての指針を示した。また、必要な耐圧を維持しつつオン抵抗を改善する導通損失の低減に加え、スイッチング損失の中でも特に出力容量に蓄積する電荷が高速動作
時の課題になることを指摘し、オン抵抗モデルだけでなく容量モデルの構築が低損失化において重要であることを示した。
2 章では、プレーナゲート二重拡散 MOSFET(D-MOSFET)およびトレンチゲート
MOSFET(U-MOSFET)の基本構造とオン抵抗の構成要素を述べ、従来のオン抵抗モデルを解析、再構成、分類するとともに試作デバイスと比較し、その限界を明らかにした。
3 章では、U-MOSFET の進化構造であるスーパージャンクション MOSFET(SJUMOSFET)とフィールドプレート MOSFET(FP-MOSFET)の基本構造と基本原理、オン抵抗の構成要素を述べ、従来のオン抵抗モデルを解析、再構成、分類するとともに試作デバイ
スと比較し、その限界を明らかにした。
4 章では、低耐圧 MOSFET のスイッチング損失設計に重要な寄生容量の構成要素を明らかにし、構造が複雑な最新の傾斜 FP-MOSFET について、デバイス構造パラメータをもとにした出力容量(Coss)と帰還容量(Crss)のモデル式を構築した。
5 章では、4 章で導出したモデルの妥当性を検証した。100V クラスの D-MOSFET と傾斜 FP-MOSFET について Coss、Crss のドレイン電圧依存性を解析し、TCAD(Technology
Computer Aided Design)によるシミュレーション結果を用いてモデルの精度を確認した。
また、構築した容量モデルからスイッチング損失解析のための各要素を導出した。

v

6 章では、前章のモデルをもとに傾斜 FP-MOSFET の解析を行い、従来デバイスと比較した。高周波では FP-MOSFET が優位であり、また低周波・大電流用途ではゲート接続型の FP 構造を採用することで高効率化が可能であることを明らかにした。
7 章では、傾斜 FP-MOSFET 構造のオン抵抗モデルと容量モデルを活用し、性能限界を追求した。その結果、高周波スイッチング用途で 50％、低周波スイッチング用途で 70％の効率改善が可能であることが判明した。
8 章では、本論文の結論として、新しい FP-MOSFET 構造の提案とコンパクトモデルの構築、さらに今後 50％以上の性能向上が可能であることを述べた。
本論文は、二酸化炭素排出量の抑制に対してキーデバイスとなるパワーMOSFET の低損失化に向け、試作やシミュレーション等を行うことなく短期間で設計可能なデバイス物
理に基づくコンパクトモデルの構築、そしてコンパクトモデルによる今後の低損失化設計の指導原理を初めて示したものである。本提案のコンパクトモデル適用により、 FPMOSFET 構造での性能改善余地が十分あること、研究・開発を推進すべきデバイスであることが明らかになり、パワーエレクトロニクスの更なる高効率化に大いに貢献できることが期待される。

viTable of Contents
Acknowledgement .................................................................................................................. i
Abstract................................................................................................................................. iii
日本語概要 ...............................................................................................................................v
Table of Contents ................................................................................................................ vii
Background and Objective ............................................................................................ 1
Overview of power electronics in our society and role of power semiconductor
devices ................................................................................................................................ 1
Applications and market demands for power MOSFETs .................................... 4
Classification of power MOSFETs......................................................................... 6
Challenges on power MOSFETs for the low-voltage application ........................ 7
Necessity of improving tradeoff characteristics ............................................ 7
Minimization of power loss to improve energy use efficiency ...................... 8
Objective of this study .......................................................................................... 12
Development of Advanced Low Power Loss D-MOSFETs and U-MOSFETs .......... 14
Earlier studies in LV-MOSFETs Development .................................................. 14
Improvement of planar gate double-diffused MOSFET (D-MOSFET) ............. 15
Basic structure and on-resistance (RONA) components of D-MOSFET ..... 15
List of on-resistance model ........................................................................... 21
On-resistance reduction techniques for 60-V D-MOSFET ......................... 22
Validation of on-resistance model ................................................................ 25
Improvement of parasitic capacitance by partially thick gate-oxide
structure ....................................................................................................................... 27
High-density trench gate MOSFET (U-MOSFET) ............................................ 29
Basic structure and on-resistance (RONA) components of U-MOSFET ..... 29
List of on-resistance model ........................................................................... 33
Cell pitch shrinking by double trenches structure ..................................... 34
30-V sub-micron cell pitch U-MOSFET applying by burying interlayer
dielectric inside trench .............................................................................................. 36
Validation of on-resistance model ................................................................ 49
Summary ............................................................................................................... 52
Development of Novel Charge Compensation Devices: SJ-UMOSFETs and FPMOSFETs ............................................................................................................................ 53
Charge compensation structures for LV-MOSFETs ........................................... 53
Basic principles of superjunction devices. ................................................... 55
vii

Basic principles of field-plate devices .......................................................... 56
Superjunction U-MOSFET (SJ-UMOSFET) featuring a low-voltage device ... 57
Basic structure and on-resistance (RONA) components of SJ-UMOSFET 57
List of on-resistance model ........................................................................... 63
60-V narrow pitch SJ-UMOSFET applying multiple-ion-implantation .. 65
Validation of on-resistance model ................................................................ 77
Field-plate MOSFET (FP-MOSFET) approaching ultimate structure ............ 79
Basic structure and on-resistance (RONA) components of FP-MOSFET ... 79
List of on-resistance model ........................................................................... 86
100-V multiple-stepped-oxide GFP-MOSFET ........................................... 88
Validation of on-resistance model .............................................................. 100
100-V two-step-oxide SFP-MOSFET ........................................................ 102
18-V sub-micron cell pitch GFP-MOSFET ................................................ 107
Summary ............................................................................................................. 109
Structure-Based Capacitance Modeling for the Latest FP-MOSFET Comparing with
D-MOSFET ......................................................................................................................... 111
Overview of structure-based capacitance modeling .......................................... 111
D-MOSFET model ............................................................................................... 111
Structural parameters and basic characteristics for motif device ........... 111
Components of output capacitance (Coss) ..................................................114
Drain–source capacitance (Cds) ...................................................................114
Gate–drain capacitance (Cgd) ......................................................................114
List of capacitance model.............................................................................115
FP-MOSFET model .............................................................................................116
Structural parameters and basic characteristics for motif device ...........116
Components of the output capacitance (Coss) ...........................................118
pn-Junction capacitance ..............................................................................118
Oxide and depletion layer capacitance along field plate .......................... 121
Trench bottom capacitance ......................................................................... 122
Gate–drain capacitance (Cgd) ..................................................................... 123
List of capacitance model............................................................................ 124
Comparison of SFP-MOSFET and GFP-MOSFET models ............................. 125
Structural parameters and basic characteristics for motif device .......... 125
Components of output capacitance (Coss) and reverse transfer capacitance(Crss)

127
pn-Junction capacitance ............................................................................. 128
viii

Gate–drain capacitance (Cgd) ..................................................................... 129
Oxide and depletion layer capacitance along field plate .......................... 129
Trench bottom capacitance ......................................................................... 130
List of capacitance model............................................................................ 131
Summary ............................................................................................................. 131
Validation of Capacitance Model by Comparing Calculated MOSFET Characteristics
and TCAD Simulations ..................................................................................................... 132
100-V-class D-MOSFET and FP-MOSFET ..................................................... 132

Coss–Vds curves ............................................................................................. 132
Output charge (Qoss) and stored energy (Eoss) ........................................... 134

Crss–Vds curves ............................................................................................. 136
Gate–drain charge (Qgd).............................................................................. 137
Switching waveforms .................................................................................. 138
Application to other FP-MOSFET structures ........................................... 139
60-V-class SFP-MOSFET and GFP-MOSFET.................................................. 140

Coss–Vds and Crss–Vds curves ....................................................................... 140
Output charge (Qoss) and stored energy (Eoss) ........................................... 141
Gate–drain charge (Qgd).............................................................................. 142
Switching waveforms .................................................................................. 143
Case study for cell pitch shrinking of 100-V-class FP-MOSFET .................... 144

Coss–Vds curves ............................................................................................. 144
Coss and Qoss ................................................................................................. 144
Summary ............................................................................................................. 147
Power Loss Analysis for the Latest FP- MOSFETs................................................. 148
100-V-class D-MOSFET and FP-MOSFET ..................................................... 148
Assuming circuit and power loss components........................................... 148
Power loss estimation by the proposed model........................................... 148
60-V-class SFP-MOSFET and GFP-MOSFET ................................................ 150
Assuming circuit and power loss components........................................... 150
Power loss estimation by the proposed model for high frequency use .... 150
Power loss estimation by the proposed model for low current use .......... 152
Summary ............................................................................................................. 154
Proposal of Ultimate Structure for High Efficiency Power MOSFET ................... 155
Assumptions for ultimate structure proposal of FP-MOSFET ....................... 155
Consideration of each parameter limitation .................................................... 157
MOS channel and p–base region................................................................ 157
ix

Field-plate and n–drift region .................................................................... 159
Prediction of realistic/ultimate limit of FP-MOSFET performance ............... 162
Structural, electrical, and physical parameters ....................................... 162
Predicted performances: RONA and RON·Qoss ............................................. 164
Predicted performances: Power loss .......................................................... 169
Summary ............................................................................................................. 172
Conclusions ................................................................................................................ 173
List of Tables ..................................................................................................................... 176
List of Figures ................................................................................................................... 178
References .......................................................................................................................... 188
Research History ............................................................................................................... 198
Publication ..................................................................................................................... 198
International Conferences ............................................................................................ 198
Related Papers ............................................................................................................... 198
Related Patents ............................................................................................................. 200
About the Author............................................................................................................... 201

Dissertation Committee:
Supervisor Prof. Ichiro Omura
Prof. Satoshi Matsumoto
Co-advisor

Prof. Mengu Cho
Prof. Kazuhiro Toyodax

BACKGROUND AND OBJECTIVE
Overview of power electronics in our society and role of power
semiconductor devices
Actions for sustainable society realization, that is a global climate change mitigation
and related energy problem solutions, are being executed in various fields. To suppress
a temperature rise after the Industrial Revolution to less than 2 degrees Celsius is theparticularly important numerical target, which was concluded in Paris agreement(December 2015). In order to achieve the target, it is said that it is necessary to reduce a
carbon dioxide (CO2) emissions to approximately 50% of the present level by 2050. An
improvement effect by the contribution of power electronics is greatly expected in ameasure for the scenario accomplishment.
The World Energy Outlook (WEO) 2017 has shown that an efficiency will realize
over 40% of the CO2 emissions reductions, among the combination of other measures [1].
It means the contribution of an energy use efficiency in various electronics system will
be larger rather than increasing the supply of renewable energy, as shown in Fig. 1-1 [2].

Source: IEA (2018) Energy efficiency 2018. All rights reserved.
Fig. 1-1. Global carbon dioxide (CO2) emissions reductions in the World Energy Outlook(WEO) 2017 [1] New Policies and Sustainable Development Scenarios. [2]1A key device supporting this power electronics technology is a power semiconductor
device. The power semiconductor devices are used to a great variety of: the large-scale
application such as a power generation, a power transmission and distribution, and a
train system; medium and small-size application such as an industrial equipment, a car,a home electric appliance, a mobile device (Fig. 1-2).
There are several kinds of power semiconductor devices, and those are selected
corresponding to a power capacity and a switching frequency as follows.
Power MOSFET (Metal Oxide Field Effect Transistor): low power, medium to highfrequency.
IGBT (Insulated Gate Bipolar Transistor): medium to high power, low to medium
frequency.
GTO (Gate Turn-Off Thyristor): high power, low frequency.
Thyristor: high to ultra-high power, low frequency.

Source of illustrations: Renesas Electronics Corporation, http://www.renesas.com/jp/ja/

Fig. 1-2. Power semiconductor devices application map.

2

The power semiconductor devices are contributing to the reduction of energy
consumption in many applications from very small portable devices to very large-scale
power electronics systems. In other words, the power semiconductor devices have big
responsibilities to the CO2 emission reductions in each category of the electronics
system/unit/equipment. This image can be shown in Fig. 1-3 [3] [4]. Although the CO2
reduction rate per unit is very high in the large-scale application such as the power plant,
the contribution is restrictive. On the other hand, large number of small end-use units
has big contribution that cannot be ignored at all.

From “Scaling up demand-side energy efficiency improvements through programmatic CDM”

Energy Sector Management Assistance Program and The World Bank Carbon Finance Unit , p. 8,
2007, [3] (modified).

Fig. 1-3. Schematics of volume of the CO2 emission reductions in each category of theelectronics system/unit/equipment. [4] © 2012 IEEE.

3

Applications and market demands for power MOSFETs
In the power semiconductor device which is categorized into low-voltage (12–250 V)
and high frequency (10 kHz–1 MHz) application, silicon power MOSFET is used in somany applications: e.g., mobile and portable equipment, personal computers andperipheral devices, automotive electronics units, power tools, high-end servers for data
center and other facilities, home appliances, lightning equipment, audio and visualequipment, photovoltaic inverter on solar panel, and so on. Fig. 1-4 is the power
MOSFETs application map shown in the matrix of the rated-voltage (VDSS) and the ratedcurrent (ID(DC)). From a viewpoint of the industry, the power MOSFET is a business field
having a big market of approximately 7000 million dollars.

Source of illustrations: Renesas Electronics Corporation, http://www.renesas.com/jp/ja/

Fig. 1-4. Power MOSFETs application map.

4

For various market demands such as low cost, high productivity, small size, lightweight, high efficiency, low power consumption, high power rating, stability, and safety
operation, the power MOSFETs' research and development (R&D) in many aspects
including a material, a manufacturing process, a device structure, a package, a
packaging method, a reliability technology, a design technology, and a measurement
technology are performed continuously (Fig. 1-5).
As the device performance that contributes directly to high efficiency and low power
consumption of the application, a low-power-loss technology of the power MOSFET isvery important. Therefore, a new structure, a new process, a design technique, and anevaluation technique, which can embody the low power loss, are strongly demanded andthat is responsibilities for the R&D.

Fig. 1-5. Market demands to electronics equipment and responsibilities as powerdevices R&D.

5

Classification of power MOSFETs
The power MOSFETs are classified into two rated-voltage ranges: 12–250 V as lowvoltage (LV) and 400–800 V as high-voltage (HV). Historically, planar gate doublediffused MOSFETs (D-MOSFETs) [5] [6] and trench gate MOSFETs (U-MOSFETs) [7]were developed in the 1970s–1980s, respectively, and they are currently used as matured
low-cost devices. As great advancement of the power MOSFETs in terms of performance,
field-plate trench MOSFETs (FP-MOSFETs) [8], superjunction MOSFETs (SJMOSFETs) [9], and superjunction U-MOSFETs (SJ-UMOSFETs) [10] were devised in
the 1990s–2000s. The development history and the device structure are described in
sections 2.1 and 3.1.
D-MOSFETU-MOSFETFP-MOSFET

SJ-UMOSFET[5] © 1975 IEEE

[7] © 1985 IEEE[8] © 1992 IEEE

[10] © 2004 IEEE

Lowvoltage
12–250V

D-MOSFETSJ-MOSFET[6] Copyright 1982,[9] © 1997 IEEE

The Japan Society ofHigh-

Applied Physics

voltage
400–800V

Fig. 1-6. Classification of power MOSFETs. Rows show range of rated-voltage, andcolumns show cell structures which has been proposed in each early development stage.

6

Challenges on power MOSFETs for the low-voltage application
Necessity of improving tradeoff characteristics
As mentioned the above (Fig. 1-5), market demands for the power MOSFETs areincluding many different things. There is various tradeoff relationship each other,between device performances, device size, ease of use, manufacturing cost, productivity,and so on. To overcome the various tradeoff and to provide advanced high performance
products are big challenge in power MOSFET development.
In all power MOSFETs dealing with high current, an on-resistance (RON) reduction
to minimize the power loss and a high breakdown voltage (VB) maintaining arefundamental tradeoff. The RON is mainly occupied by drift layer length and the impurity
concentration, which also determine the VB. The RON is derived by [11] and expressed as
below.
𝑅𝑂𝑁 ≈4𝑉𝐵 2
𝜇𝑛 𝜀𝐸𝐶 3(1-1)

Here, n is the electron mobility,  is the permittivity of semiconductor, and EC is thecritical electric field. The higher the VB is, the more the RON increases, therefore the RON–

VB tradeoff is a still significant issue on the power MOSFETs development.
The power MOSFET has parasitic capacitances itself: gate–source capacitance (Cgs),
gate–drain capacitance (Cgd), and drain–source capacitance (Cds). The parasitic
capacitances affect to switching loss. There is a simple tradeoff between the chip size andthe capacitances; the larger the chip size, the more the capacitances increase. In addition,in unit cell structure of the power MOSFET, there are various cases that a reduction
method of the capacitance affects to the VB increase or the RON increase. Thus, to makesure of the relationship between the RON and the capacitance properties, figures-of-merit(FOMs) are discussed, especially in considering a switching performance.

7

Minimization of power loss to improve energy use efficiency
The LV-MOSFETs, which are generally classified into rated-voltage in the range
from 12–250 V, are applied in various power electronics circuits, e.g., as shown in Fig.
1-7, Fig. 1-8, and Fig. 1-9.

Fig. 1-7. Example of application circuit topology (1). Isolated DC-DC converter block
having full bridge for primary-side and synchronous rectification for secondary-side.

Fig. 1-8. Example of application circuit topology (2). Motor drive unit having threephase inverter.

8

Fig. 1-9. Example of application circuit topology (3). Lithium-ion battery cellcharging/discharging control and protection circuit.

In the distributed power supply systems, there is an isolated DC-DC converter block
having full bridge for primary-side and synchronous rectification for secondary-side, as
shown in Fig. 1-7. Corresponding to the DC input voltage, 80–150-V-rated power
MOSFETs are used in both primary-side and secondary-side. When the DC output
voltage is set to 12 V, a 30-V-rated power MOSFET is used in the next stage.
In the motor drive unit as shown in Fig. 1-8, three-phase inverter circuit is consistsof six power MOSFETs. For example, in the automobile electronic unit, corresponding to
the battery voltage, 30–100-V-rated power MOSFETs are used in the inverter circuit.
In the lithium-ion battery pack, which is incorporated in large quantities in manykinds of portable equipment, 12–20-V-rated power MOSFETs are used in the battery cellcharging/discharging control and protection circuit (Fig. 1-9).
In such an energy conversion, a load drive, or a switching operation, an energy loss
is caused generally. In a switching circuit using the power MOSFET as shown in Fig.
1-10, the power loss occurs during both conduction and switching period. The general
power loss consists of the following components [12] [13].

PGD

Gate drive loss

PCON

Conduction loss

PSW(on)Turn-on loss

PSW(off) Turn-off loss
PQrr

Diode reverse recovery charge (Qrr) loss

PQoss

Output charge (Qoss) loss

9

Fig. 1-10. Simplified switching test circuit (left figure) and switching waveform (rightfigure).

VIN: input (supply) voltage, Vgs: gate voltage, Rg: gate resistance, L: inductance, Vds:
drain–source voltage, Id: drain current, ION: on-state current, VON: on-state voltage,

ton: turn-on switching time, toff: turn-off switching time, fSW: switching frequency, and
D: duty ratio.

Components of power loss originated from the power MOSFET characteristics in anassumption of the switching test circuit in Fig. 1-10 and formula of each power loss areshown in Fig. 1-11. In each power loss component, individual improvement methods are
considered as described below.

PGD reduction is depending on a gate driver technology. It is expected that PGD canbe minimized by very low impedance condition and very high current gate drive [14] [15][16].

PCON is proportional to the RON. Ultralow RON MOSFET can directly reduce PCON.
PSW(on) and PSW(off) increase in proportion to the switching time (turn-on switchingtime (ton) and turn-off switching time (toff)) and the switching frequency (fSW). Meanwhile,

ton and toff are defined by both gate–source capacitance (Cgs) and gate–drain capacitance(Cgd). Low gate–source charge (Qgs) and low gate–drain charge (Qgd) MOSFET is the mostdesirable solution. Both PSW(on) and PSW(off) can be also minimized by very low impedance
condition and very high current gate drive. Moreover, in particular, PSW(on) can be
drastically reduced by a circuit control technology such as zero-voltage-switching (ZVS)

PQrr is defined by the reverse recovery charge (Qrr) of body diode, which is formed by
pn-junction of the MOSFET. Low-recovery-charge Shottky barrier diodes (SBD) can
improve PQrr drastically.

PQoss is caused by the period of output charge (Qoss) charging and discharging bydrain current (Id). Qoss is influenced by drift layer design that determines the VB.

10

Regarding advanced power MOSFETs, it is obvious that there is a potential toreduce PCON, PSW(on), and PSW(off) drastically, and several power loss analysis has beenreported so far [17] [18] [19] [20] [21] [22] [23]. However, owing to the VB maintained
structure, the Qoss increase which leads to PQoss is a significant issue, especially in thecase of megahertz switching.

Fig. 1-11. Components of power loss originated from the power MOSFET
characteristics in an assumption of the switching test circuit in Fig. 1-10. Each power
loss is expressed by general formula. In addition, improvement methods for eachpower loss are described.

VIN: input (supply) voltage, Vgs: gate voltage, Rg: gate resistance, Qg: gate charge, Vds:
drain–source voltage, Id: drain current, ION: on-state current, ton: turn-on switchingtime, toff: turn-off switching time, fSW: switching frequency, D: duty ratio, Qrr: reverse
recovery charge, Qgs: gate–source charge, Qgd: gate–drain charge, and Coss: .output
capacitance.
11

Objective of this study
1. Development of novel structures for low-voltage power MOSFETs to achieve low
power loss.
2. Construction of structure-based compact model to enable the power loss analysis.
3. Proposal of an ultimate power MOSFET structure by using the compact modeland prediction of the performance.
For the key device to prevent the CO2 emission, low-power-loss technologies of thepower MOSFETs are strongly required to realize high efficiency and low power
consumption in various application. In this dissertation, several kinds of new structures
for the low-power-loss LV-MOSFETs are proposed and are demonstrated with fabricateddevices.
In addition, to enable a new device design without experiment and simulation, adevice-physics-based compact model for the LV-MOSFET are constructed. It is expectedthat the compact model can calculate and predict significant number of the new designed
devices in very short term. Fig. 1-12 shows schematics of procedure from the device
structure design to the device performance evaluation/prediction, for the case of a real
device, a TACD simulation, and a calculation by using the compact model.
As the compact model, specific on-resistance (RONA) models, which are necessary forthe calculation of the conduction loss, are described in detail for each LV-MOSFET
structure. It needs to be considered carefully that not only the RONA components in eachstructure but also the current spreading in vertical direction will change by the structure
design or the layout design.
Moreover, especially in high current or high frequency switching application,parasitic capacitances in the LV-MOSFET are necessary for the calculation of theswitching loss. The capacitance models are described by structural parameters, which
are unit-cell geometries, impurity doping concentration, and dimensions of the device
structure. In the modeling, the components of capacitance for both standard DMOSFETs and the latest FP-MOSFETs are considered and the derivation of model
equations is studied in detail.
By utilizing the compact model, it enables to predict an ultimate structure for nextgeneration LV-MOSFET. It makes clear that the latest FP-MOSFET structure has anenough room for the performance improvement and the device should advance theresearch and development. It is expected this compact model can greatly contribute tohigher efficiency power electronics.
12

Fig. 1-12. Schematics of procedure from device structure design to device performance
evaluation/prediction: for real device, TACD simulation, and compact model.

13

DEVELOPMENT OF ADVANCED LOW POWER LOSS DMOSFETS AND U-MOSFETS
Earlier studies in LV-MOSFETs Development
For the most basic structure of modern power MOSFETs, which drain current flows
vertically between front-surface and back-surface in semiconductor die, planar gate
double-diffused MOSFETs (D-MOSFETs) were developed in the mid-1970s [5] andcommercialized in the late 1970s. The D-MOSFETs applied fundamental technology
called Diffusion Self-Aligned (DSA), which was devised in the late 1960s [24].
Trench D-MOSFETs were developed in the mid-1980s [7] and commercialized in theearly 1990s, respectively. The trench gate D-MOSFETs which have U-grooved structure,
are also called U-MOSFETs, and currently being used as matured low-cost devices. As
great advancements of LV-MOSFETs in terms of performance, field-plate U-MOSFETs(FP-MOSFETs) and superjunction U-MOSFETs (SJ-UMOSFETs) were developed andcommercialized in the early to mid-2000s. Regarding SJ-UMOSFETs and FP-MOSFETs,
the details are described in chapter 3.
Fig. 2-1 shows technology development history of vertical power MOSFETs.

Fig. 2-1. Technology development history for vertical power MOSFETs.
Highlights show author’s research.
14

Improvement of planar gate double-diffused MOSFET (D-MOSFET)
Basic structure and on-resistance (RONA) components of D-MOSFET
Schematic cross-sectional unit-cell structure of D-MOSFET is shown in Fig. 2-2. Fig.
2-2(a) shows a distribution of electric field Ey of drift layer in vertical direction y, whenreverse bias applies to drain. In the D-MOSFET, breakdown voltage (VB) of onedimensional plane pn-junction is determined by the area of this triangle electric field.
When a gate width is relatively short, i.e., a lateral distance between p–base layers isnarrow enough, the VB of the D-MOSFET is approximated as
1
𝑉𝐵 ≈ 𝐸𝐶 𝐿𝑑𝑒𝑝 ,
2

(2-2)

where EC is a critical electric field and Ldep is a depletion layer length in y. In an
assumption, if a depletion layer length in the p–base region is negligible a slope of theelectric field in the n–drift layer is expressed as
𝐸𝐶
𝑞𝑁𝐷
=−
,
𝐿𝑑𝑒𝑝
𝜀𝑆𝑖 𝜀0(2-3)

where q is the elementary charge, ND is the n–drift layer concentration, andSi0 is thepermittivity of silicon. By substituting Eq. (2-3) into Eq. (2-2), the VB can be obtained as𝑉𝐵 ≈𝜀𝑆𝑖 𝜀0 𝐸𝐶 2
.
2𝑞𝑁𝐷

(2-4)

The VB is inversely proportional to the ND. On the other hand, the ND is one of the main
influence parameter of on-resistance (RONA), especially in drift layer resistance (RDA) as
described below. Therefore, the VB and the RDA has a tradeoff relationship, and it has
been described as RDA ∝ VB2.5 in [11].
Fig. 2-2(b) shows on-state current paths and on-resistance components of the DMOSFET. The RONA of the D-MOSFET (RONDMOSA) is described as follows.
𝑅𝑂𝑁 𝐷𝑀𝑂𝑆 A ≅ 𝑅𝑁+ 𝐴 + 𝑅𝐶𝐻 𝐴 + 𝑅𝐴 𝐴 + 𝑅𝐽𝐹𝐸𝑇 𝐴 + 𝑅𝐷 𝐴 + 𝑅𝑆𝑈𝐵 𝐴(2-5)

Here, RN+ is n+–source layer resistance, RCH is channel resistance, RA is accumulation
layer resistance under the gate, RJFET is junction FET (JFET) resistance, RD is n–drift

15

(a)

(b)

Fig. 2-2. Schematic cross-sectional structure of D-MOSFET, which shows unit-cell area.
(a) Electric field distribution in vertical direction of off-state. (b) On-state current paths
and components of on-resistance.
layer resistance and RSUB is n+–substrate resistance. All the components indicate theresistance of unit area “A”, which means the product of “unit width” and “unit length”.
Whereas RN+A is relatively small, thus RONDMOSA can be approximated by using main
components,
𝑅𝑂𝑁 𝐷𝑀𝑂𝑆 A ≈ 𝑅𝐶𝐻 𝐴 + 𝑅𝐴 𝐴 + 𝑅𝐽𝐹𝐸𝑇 𝐴 + 𝑅𝐷 𝐴 + 𝑅𝑆𝑈𝐵 𝐴.

(2-6)

In Eq. (2-6), each of the resistance except RDA is expressed by analytical model as
below [25] [26] [27].
𝑅𝐶𝐻 A =𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙
2𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )𝑅𝐴 A = 𝐾𝐴(2-7)

𝐿𝐴 𝑊𝐶𝑒𝑙𝑙
2𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠(2-8)

𝜌𝐷 𝑋𝐽𝐵 𝑊𝐶𝑒𝑙𝑙
2𝐿𝐴

(2-9)

𝑅𝐽𝐹𝐸𝑇 A =16

(2-10)𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵

Here each structural parameter is shown in Fig. 2-3 and defined as follows. WCell is cellwidth, WG is gate width, LCH is channel length, LA is accumulation layer length, XJB isjunction depth of p–base layer, XJB_l is lateral expansion width of the p–base layer, D is
resistivity of n–drift layer, SUB is resistivity of n+–substrate, and TSUB is thickness of then+–substrate. In addition, ni is electron mobility of inversion layer, na is electron
mobility of accumulation layer, CGOX is gate oxide capacitance, Vgs is gate voltage, andVTH is threshold voltage. KA is a coefficient of considering current spreading from theaccumulation region to the JFET region [25] [26]. KA is assumed to be around 0.6.
Moreover, Cgox, D and SUB are expressed as
𝐶𝐺𝑂𝑋 =𝜌𝐷 =𝜌𝑆𝑈𝐵 =𝜀𝑂𝑋 𝜀0𝑇𝐺𝑂𝑋(2-11)

1(2-12)

𝑞𝜇𝑛_𝐷 𝑁𝐷

1

(2-13)

𝑞𝜇𝑛_𝑆𝑈𝐵 𝑁𝑆𝑈𝐵

where OX0 is the permittivity of silicon dioxide (SiO2), TGOX is the gate oxide thickness,and NSUB is n+–substrate concentration. In addition, q is elementally charge, n_D iselectron mobility of n–drift layer, and n_SUB is electron mobility of n+–substrate.
In the n–drift layer, current flow from the corner of the p–base layer spreads in angleof 45 degrees. RDA model is divided into two cases, i.e., 𝑊𝐶𝑒𝑙𝑙 ≥ 2(𝐿𝐷 + 𝐿𝐴 ) or 𝑊𝐶𝑒𝑙𝑙 <2(𝐿𝐷 + 𝐿𝐴 ), and expressed as follows.
𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 𝐿𝐷 + 𝐿𝐴
ln
,
2
𝐿𝐴
𝑅𝐷 A =
𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 𝑊𝐶𝑒𝑙𝑙
𝑊𝐵ln+ 𝜌𝐷 (𝐿𝐷 −− 𝑋𝐽𝐵_𝑙 ) ,
{ 2
2𝐿𝐴
2

17

𝑊𝐶𝑒𝑙𝑙 ≥ 2(𝐿𝐷 + 𝐿𝐴 )𝑊𝐶𝑒𝑙𝑙 < 2(𝐿𝐷 + 𝐿𝐴 )(2-14)

(a)(bFig. 2-3. (a) Top view of unit-cell layout [28] [29], © 1995 IEICE, and (b) structuralparameters of D-MOSFET.
a: Half of gate poly-silicon width (1/2WG).
b: p–Base width (WB).
c: Distance between gate poly-silicon and contact.
d: n+–Source contact width.
e: p+–Body contact width.

By the way, Eqs. (2-7)–(2-9) and (2-14) show the case of the stripe geometry of the
D-MOSFET as a simplified. For example, in the RCHA (Eq. (2-7)), channel width per unit
area A is given as 2𝑊𝐶𝑒𝑙𝑙 ⁄𝑊𝐶𝑒𝑙𝑙 2 = 2⁄𝑊𝐶𝑒𝑙𝑙 in stripe geometry. On the other hand, that isgiven as 4𝑊𝐵 ⁄𝑊𝐶𝑒𝑙𝑙 2 in square cell geometry shown as Fig. 2-3(a). Each of the resistanceincluded in Eq. (2-6) in the square cell geometry is expressed by amended model as below.
𝑅𝐶𝐻 A =𝑅𝐴 A = 𝐾𝐴

𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙 2
4𝑊𝐵 𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )𝐿𝐴 𝑊𝐶𝑒𝑙𝑙 24(𝑊𝐵 + 2𝑋𝐽𝐵_𝑙 )𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠

18(2-15)(2-16)

𝑅𝐽𝐹𝐸𝑇 A =𝜌𝐷 𝑋𝐽𝐵 𝑊𝐶𝑒𝑙𝑙 2
𝑊𝐶𝑒𝑙𝑙 2 − (𝑊𝐵 + 2𝑋𝐽𝐵_𝑙 )2(2-18)𝑅𝐷 A = 𝑅𝐷1 𝐴 + 𝑅𝐷2 𝐴,

𝑊𝐶𝑒𝑙𝑙 ≥ 2(𝐿𝐷 + 𝐿𝐴 )𝑊𝐶𝑒𝑙𝑙
𝑅𝐷2 A = {𝜌𝐷 (𝐿𝐷 −+ 𝐿𝐴 ) ,2

𝑊𝐶𝑒𝑙𝑙 < 2(𝐿𝐷 + 𝐿𝐴 )0

𝑅𝐷1 A =

𝑅𝐷1_𝐺 A =𝑅𝐷1_𝐺 𝐴 ∙ 𝑅𝐷1_𝐵 𝐴
𝑅𝐷1_𝐺 𝐴 + 𝑅𝐷1_𝐵 𝐴

𝑊𝐶𝑒𝑙𝑙 2𝑊𝐺

𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 3

𝑊𝐶𝑒𝑙𝑙
𝜌𝐷 (
− 𝐿𝐴 )
2

𝑊𝐶𝑒𝑙𝑙 ≥ 2(𝐿𝐷 + 𝐿𝐴 )𝑊𝐶𝑒𝑙𝑙
2
2 ln 2𝐿 ,{ 2(𝑊𝐶𝑒𝑙𝑙 − 𝑊𝐺 )𝐴

𝑊𝐶𝑒𝑙𝑙 < 2(𝐿𝐷 + 𝐿𝐴 )22(𝑊𝐶𝑒𝑙𝑙 − 𝑊𝐺 )ln𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 3(2-19)(2-20)𝐿𝐷 + 𝐿𝐴,𝐿𝐴

2

𝑅𝐷1_𝐵 A =2

(2-17)(2-21)(2-22)

Here, RD1A, RD2A, RD1_GA and RD1_BA are components of the RDA shown in Fig. 2-4. As
expressed in Eq. (2-20), RD1A is expressed as a parallel resistance of RD1_GA and RD1_BA.

RD1_GA in Eq. (2-21) expresses a component of the drift layer resistance under the gateintersection. In the same way, RD1_BA in Eq. (2-22) expresses another component of thedrift layer resistance, which is spreading from the end of the JFET region to under the
p–base layer in angle of 45 degrees.

RD1_BA and RD2A models are divided into two cases as same as the case of the stripe
geometry, i.e., 𝑊𝐶𝑒𝑙𝑙 ≥ 2(𝐿𝐷 + 𝐿𝐴 ) or 𝑊𝐶𝑒𝑙𝑙 < 2(𝐿𝐷 + 𝐿𝐴 ).
To improve the RONDMOSA with necessary VB maintained, all the components of

RONDMOSA have to be reduced by individual appropriate techniques.

19

(a)

(b)

(c)

Fig. 2-4. (a) Top view of D-MOSFET for square cell layout. Schematic cross-sectional
structure, which shows components of the n–drift layer resistance (RD1_B, RD1_G, RD2).
(b) Current flow spreading in 45 degrees underneath p-base layer. (c) Current flow
under gate intersection.

20

List of on-resistance model

Table 2-1. List of RONA model equations for D-MOSFET (stripe and square cell design).
Stripe𝑅𝐶𝐻 A =

Square cell

𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙

𝑅𝐶𝐻 A =

2𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙 2
4𝑊𝐵 𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )𝑅𝐴 A = 𝐾𝐴

𝐿𝐴 𝑊𝐶𝑒𝑙𝑙
2𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠

𝑅𝐴 A = 𝐾𝐴

𝑅𝐽𝐹𝐸𝑇 A =𝜌𝐷 𝑋𝐽𝐵 𝑊𝐶𝑒𝑙𝑙
2𝐿𝐴

𝑅𝐽𝐹𝐸𝑇 A =𝑅𝐷 A =

𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 𝑊𝐶𝑒𝑙𝑙
𝑊𝐵ln+ 𝜌𝐷 (𝐿𝐷 −− 𝑋𝐽𝐵𝑙 )2
2𝐿𝐴
2

𝐿𝐴 𝑊𝐶𝑒𝑙𝑙 24(𝑊𝐵 + 2𝑋𝐽𝐵_𝑙 )𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠
𝜌𝐷 𝑋𝐽𝐵 𝑊𝐶𝑒𝑙𝑙 22𝑊𝐶𝑒𝑙𝑙 2 − (𝑊𝐵 + 2𝑋𝐽𝐵_𝑙 )𝑅𝐷 A = 𝑅𝐷1 𝐴 + 𝑅𝐷2 𝐴
𝑅𝐷1 A =

𝑊𝐶𝑒𝑙𝑙 < 2(𝐿𝐷 + 𝐿𝐴 )𝑅𝐷1_𝐺 𝐴 ∙ 𝑅𝐷1_𝐵 𝐴
𝑅𝐷1_𝐺 𝐴 + 𝑅𝐷1_𝐵 𝐴

𝑅𝐷1_𝐺 A =𝑅𝐷1_𝐵 A =𝑊𝐶𝑒𝑙𝑙 2
𝑊𝐺

2

𝑊𝐶𝑒𝑙𝑙
𝜌𝐷 (
− 𝐿𝐴 )
2

𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 3222(𝑊𝐶𝑒𝑙𝑙 − 𝑊𝐺 )𝑅𝐷2 A = 𝜌𝐷 (𝐿𝐷 −

ln

𝑊𝐶𝑒𝑙𝑙
2𝐿𝐴

𝑊𝐶𝑒𝑙𝑙
+ 𝐿𝐴 )
2

𝑊𝐶𝑒𝑙𝑙 < 2(𝐿𝐷 + 𝐿𝐴 )𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵

𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵

21

On-resistance reduction techniques for 60-V D-MOSFETIn the RONA of the D-MOSFET, there are main five components with comparatively
high value; RCHA, RAA, RJFETA, RDA and RSUBA, as shown in Eq. (2-6). Reduction of thewhole RONA is achieved by improving those components individually. In this subsection,
two process techniques, which are unit-cell shrinking and shallow pn-junction formation,
are applied to 60-V-class D-MOSFET and achieved results are described [28] [29].
Unit-cell shrinking by utilizing advanced design rule
It can consider from Eqs. (2-7) and (2-8) that both RCHA and RAA are reduced byshrinking the unit-cell. By utilizing advanced design rule, e.g., 1.2-m rule in mid-1990s,
both WG and WB can be shrunk compared with those in conventional 2.5-m rule. In the
D-MOSFET cell layout shown in Fig. 2-3(a), each parameter is designed to an optimum
dimension, e.g., (a) the WG defined by the poly-silicon etching, (c) sufficient isolation
distance between the gate poly-silicon and the contact, (d) n+–source contact width
keeping low-resistance, and (e) p+–body contact width having stable VB.
Shallow pn-junction formation by PSG sidewall process
The RJFET region is made up of the p–base layer and the n–drift layer under the gateelectrode. Therefore, it can consider from Eq. (2-9) that the RJFETA becomes smaller as
the distance between the p–base layers (2×LA) becomes wider, or as the p–base layers
depth (XJB) becomes shallower.
The RD region is under the JFET region and the p–base layers. The RDA becomes
smaller as the LD becomes thinner. The necessary value of the LD determined by the VB
in Eq. (2-2) has to consider the expansion of p–base layer diffusion and the extension of
the high-density layer from the n+–substrate after passing through the device fabrication
process. Thus, the shallow p–base layer formation by adopting less annealing process iseffective as a method to reduce the LD.
Even when the XJB is formed shallower, the LCH has to keep a necessary length toprevent punch-through phenomenon, which leads to degrade the VB. Therefore the XJS,
which is junction depth of the n+–source layer, has to be moved away from the p–baselayer edge in lateral direction at the same time. This can be achieved by using sidewall
process and self-aligning n+–diffusion layer, where PSG (phosphor-silicate glass)sidewalls are formed on both sides of the gate poly-silicon, as shown in Fig. 2-5.
22

Fig. 2-5. Sidewall self-aligned process for n+ source layer formation. [29] © 1995 IEICE.
(PSG: phosphor-silicate glass.)

Experimental results of RONA reduction
In order to evaluate the RONA reduction with newly developed process, a testelement group (TEG), which plural 2×2 mm2 chips were arranged, was fabricated. As
evaluation of the TEG of D-MOSFET, both WG and XJB dependences of RONA, and bothD and XJB dependences of RONA were shown in Fig. 2-6(a) and Fig. 2-6(b), respectively.
In a viewpoint of minimizing RONA, an optimum WG became smaller with shallowing
the XJB. When the WB was constant value of 6 m and XJB was 1.5 m, the optimum WG
was approximately 5.5 m. In the case that the WG was narrower than the optimum
value, the RONA increased because the RJFETA component became large. However, therate of RONA increase were suppressed enough with respect to the shallower XJB. It canmention that such a shallow pn-junction formation has advantage as a robust design
regarding the WG variation in the D-MOSFET cell.
In the case of lower D, not only the RONA decreased but also the VB decreased.
Therefore, in order to satisfy both sufficient high VB and smaller RONA, it was found that
the VB maintained by slightly high D with shallow XJB was better choice than that bydeeper XJB.
23

(a)

(b)

Fig. 2-6. (a) WG and XJB dependences of RONA, and (b) D and XJB dependences of RONA
in fabricated TEG of D-MOSFET. [29] (modified).

Moreover, in this experiment, impurity doping of n+–substrate was changed from
phosphorus to arsenic to reduce the RSUBA. As the effect, the SUB was reduced to onethirds and it was less than 6 m·cm.
As the experimental result shown in Fig. 2-7, RONA of 130 m·mm2 with VB of 70 V
was achieved by adopting process techniques and optimization described in subsections
2.2.3.1–2.2.3.1.

Fig. 2-7. Experimental result of relationship between RONA and VB in fabricated TEG
of D-MOSFET. [29] (modified).
24

Validation of on-resistance modelFig. 2-8 shows the RONA of developed 60-V-class D-MOSFET compared with that ofboth analytical model and TCAD simulation. The structural parameters, electricalparameters and physical constants are indicated in Table 2-2, Table 2-3 and Table 2-4.
For the stripe geometry, the RONA calculated by the model corresponded to the TCAD
result with only 2.4% error. For the square cell geometry, the RONA calculated by themodel corresponded to the experimental result with only 4.2% error.

Fig. 2-8. Experimental result of RONA for developed 60-V-class D-MOSFET comparedwith that of both analytical model and TCAD simulation.

25

Table 2-2. Structural parameters of 60-V-class D-MOSFET to calculate RONA.
Symbol

WCell
WG
WB
LCH
LA
KA
TGOX
XJS
XJB
XJB_l
LD
D
ND
TSUB
SUB
NSUB

Parameters

Numerics

Unit

Cell width

11.5

m

Gate width

5.50

m

p–Base width

6.00

m

Channel length

1.00

m

Accumulation length

1.48

m

Coefficient of current spreading in
the accumulation region
Gate oxide thickness

0.60



0.05

m

n+–Source junction depth

0.50

m

p–Base junction depth

1.50

m

p–Base junction lateral length

1.28

m

n–Drift layer length

5.00

m

0.85
5.76 × 1015

•cm
atoms/cm3

250

m

0.006
9.70 × 1018

•cm
atoms/cm3

Resistivity of n–drift layer
Drift layer concentration
n+–Substrate thickness
Resistivity of n+–substraten+–Substrate concentration

Table 2-3. Electrical parameters of 60-V-class D-MOSFET to calculate RONA.
Symbol

Vgs
VTH
ni
na
n_D
n_SUB

Parameters
Gate–source voltage
Threshold voltage
Electron mobility of inversion layer

Numerics
10.0
1.50
550

Unit
V
V
cm2/VsElectron mobility of accumulation
layerElectron mobility of n–drift layer

1000

cm2/Vs1250

cm2/VsElectron mobility of n+–substrate

109

cm2/VsTable 2-4. Physical constants to calculate RONA.
Symbol

q
0
Si
OX

Description

Property

Elementary charge
Permittivity in vacuum

1.60 × 10
8.854 × 10−14

Dielectric constant of Si

11.7

Dielectric constant of SiO2

3.9

−19

26

Unit
C
F/cm

Improvement of parasitic capacitance by partially thick gate-oxide structure
Reduction of RONA for D-MOSFET was achieved by unit-cell shrinking, shallow pnjunction formation, and high impurity doping of n+–substrate. On the other hand,parasitic capacitances of the D-MOSFET are improved by other design approach. Fig.
2-9(a) shows the parasitic capacitances of the D-MOSFET: input capacitance (Ciss),
output capacitance (Coss), and reverse transfer capacitance (feedback capacitance) (Crss).
Among those, gate–drain capacitance Cgd can be reduced by partially thick gate-oxide
structure as shown in Fig. 2-9(b).

(a)

(b)

Fig. 2-9. (a) Parasitic capacitances of D-MOSFET. (b) Partially thick .gate oxide
structure for D-MOSFET. [29] © 1995 IEICE.

Crss equals to Cgd, and both Ciss and Coss include Cgd. Therefore, in the experimental
results, all parasitic capacitances were reduced by the partially thick gate-oxide
structure, as shown in Fig. 2-10.

27

Fig. 2-10. Vds dependence of capacitances (Ciss, Coss, and Crss) in D-MOSFETs. In
comparison of conventional structure and fabricated partially thick gate oxide
structure. [29] © 1995 IEICE.

28

High-density trench gate MOSFET (U-MOSFET)
Basic structure and on-resistance (RONA) components of U-MOSFET
Schematic cross-sectional structure of U-MOSFET for two unit-cells area is shownin Fig. 2-11. Fig. 2-11(a) shows a distribution of electric field Ey of drift layer in verticaldirection y, when reverse bias applies to drain. In the U-MOSFET, VB of one-dimensional
plane pn-junction is determined by the area of this triangle electric field in a similarmanner to the D-MOSFET. When a trench gate penetration from a p–base layer isrelatively short, the VB of the U-MOSFET is approximated as same Eqs. (2-2)–(2-4).
Fig. 2-11(b) shows on-state current paths and on-resistance components of the UMOSFET. The RN+A is more negligible than that of the D-MOSFET, and the RONA of the
U-MOSFET (RONUMOSA) can be approximated by using main components,(2-23)𝑅𝑂𝑁 𝑈𝑀𝑂𝑆 A ≈ 𝑅𝐶𝐻 𝐴 + 𝑅𝐴 𝐴 + 𝑅𝐷 𝐴 + 𝑅𝑆𝑈𝐵 𝐴.

(a)

(b)

Fig. 2-11. Schematic cross-sectional structure of U-MOSFET, which shows two unitcells area. (a) Electric field distribution in vertical direction of off-state. (b) On-state
current paths and components of on-resistance.
29

In Eq. (2-23), RCHA, RAA and RDA are divided into two cases, i.e., the U-MOSFET
design is stripe geometry or square cell geometry. Fig. 2-12(a) shows structuralparameters of the U-MOSFET. As shown in Fig. 2-12(b) and Fig. 2-12(c), channel width
per unit area “A” is shown as 2𝑊𝐶𝑒𝑙𝑙 ⁄𝑊𝐶𝑒𝑙𝑙 2 = 2⁄𝑊𝐶𝑒𝑙𝑙 in stripe cell design, or
4𝑊𝑀𝑒𝑠𝑎 ⁄𝑊𝐶𝑒𝑙𝑙 2 in square cell design. Here, WCell is cell width and WMesa is mesa width.

RCHA, RAA and RSUBA in Eq. (2-23) are expressed by analytical model as below.
𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙
𝑅𝐶𝐻 A =

2𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 ),𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙 2{4𝑊𝑀𝑒𝑠𝑎 𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )in stripe cell
(2-24),(2𝐿𝐴 + 𝑊𝑇 )𝑊𝐶𝑒𝑙𝑙,
4𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠
𝑅𝐴 A =(2𝐿𝐴 + 𝑊𝑇 )𝑊𝐶𝑒𝑙𝑙 2𝐾𝐴,{ 8𝑊𝑀𝑒𝑠𝑎 𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠
𝐾𝐴in square cellin stripe cell
(2-25)
in square cell

(2-26)𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵

Here, WT is trench width and other same symbols are the same as those of subsection
2.2.1, i.e., LCH is channel length, LA is accumulation length, D is resistivity of n–drift
layer, SUB is resistivity of n+–substrate, TSUB is thickness of the n+–substrate, ni is
electron mobility of inversion layer, na is electron mobility of accumulation layer, CGOX
is gate oxide capacitance, Vgs is gate voltage, and VTH is threshold voltage. KA is acoefficient of considering current spreading from the accumulation region to the drift
region [25] [26]. In Eq. (2-25), the total accumulation length of the unit cell is given by
2𝐿𝐴 + 𝑊𝑇 . KA is assumed to be around 0.6.
In addition, RDA in Eq. (2-23) is consists of sub-components which are RD1A, RD2A,

RD1_TA and RD1_MA as shown in Fig. 2-13, and is expressed by analytical model as below.
𝑅𝐷 A = 𝑅𝐷1 𝐴 + 𝑅𝐷2 𝐴

𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 𝑊𝐶𝑒𝑙𝑙
ln
,
2
𝑊𝑇
𝑅𝐷1 A = 𝑅
𝐷1_𝑇 𝐴 ∙ 𝑅𝐷1_𝑀 𝐴,{𝑅𝐷1_𝑇 𝐴 + 𝑅𝐷1_𝑀 𝐴

30(2-27)

in stripe cell
(2-28)
in square cell

𝑊𝑀𝑒𝑠𝑎)2(2-29)

𝑊𝑀𝑒𝑠𝑎
2(2-30)𝑅𝐷2 A = 𝜌𝐷 (𝐿𝐷 − 𝐿𝐴 −𝑅𝐷1_𝑇 A =𝑅𝐷1_𝑀 A =𝑊𝐶𝑒𝑙𝑙 2𝑊𝑇

2

𝜌𝐷𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 3222(𝑊𝐶𝑒𝑙𝑙 − 𝑊𝑇 )

ln

𝑊𝐶𝑒𝑙𝑙
𝑊𝑇

(2-31)As expressed in Eq. (2-28), RD1A is a drift layer resistance spreading from under the
trench to center of the mesa. Moreover, in the square cell, RD1A is expressed as a parallel
resistance of RD1_TA and RD1_MA. RD1_TA in Eq. (2-30) expresses a component of the drift
layer resistance under the trench intersection. In the same way, RD1_MA in Eq. (2-31)
expresses another component of the drift layer resistance, which is spreading from foursides surrounding the square mesa region.

(a)

(b)

(c)

Fig. 2-12. (a) Structural parameters of U-MOSFET. Top view of U-MOSFET unit-celllayout for (b) square cell design and (c) stripe cell design.
31

To improve the RONUMOSA with necessary VB maintained, all the components of

RONUMOSA have to be reduced by individual appropriate techniques.
In the case of n+/p+ interactive layout pattern, RCHA is expressed as below.
𝑅𝐶𝐻 A =(a)

𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙1
𝑅𝑎𝑡𝑖𝑜
2𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )𝑛𝑝(2-32)

∙

(b)

(c)

Fig. 2-13. (a) Top view of U-MOSFET for square cell layout. Schematic cross-sectional
structure, which shows components of the n–drift layer resistance (RD1_M, RD1_T, RD2).
(b) Current flow spreading in 45 degrees from four sides surrounding the square mesa
region. (c) Current flow under trench intersection.

32

List of on-resistance model

Table 2-5. List of RONA model equations for U-MOSFET (stripe and square cell design).
Stripe𝑅𝐶𝐻 A =

Square cell

𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙

𝑅𝐶𝐻 A =

2𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )[𝑅𝐶𝐻 A =4𝑊𝑀𝑒𝑠𝑎 𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )1]2𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 ) 𝑅𝑎𝑡𝑖𝑜𝑛𝑝

𝑅𝐴 A = 𝐾𝐴

𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙

𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙 2∙(2𝐿𝐴 + 𝑊𝑇 )𝑊𝐶𝑒𝑙𝑙
4𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠

𝑅𝐴 A = 𝐾𝐴

𝑅𝐷 A = 𝑅𝐷1 𝐴 + 𝑅𝐷2 𝐴
𝑅𝐷1 A =𝑅𝐷 A = 𝑅𝐷1 𝐴 + 𝑅𝐷2 𝐴

𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 𝑊𝐶𝑒𝑙𝑙ln
2
𝑊𝑇

𝑅𝐷2 A = 𝜌𝐷 (𝐿𝐷 − 𝐿𝐴 −

(2𝐿𝐴 + 𝑊𝑇 )𝑊𝐶𝑒𝑙𝑙 2
8𝑊𝑀𝑒𝑠𝑎 𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠

𝑅𝐷1 A =

𝑊𝑀𝑒𝑠𝑎)
2

𝑅𝐷1_𝑇 𝐴 ∙ 𝑅𝐷1_𝑀 𝐴
𝑅𝐷1_𝑇 𝐴 + 𝑅𝐷1_𝑀 𝐴

𝑅𝐷1_𝑇 A =𝑅𝐷1_𝑀 A =𝑊𝐶𝑒𝑙𝑙 2
𝑊𝑇

2

𝜌𝐷

𝑊𝑀𝑒𝑠𝑎
2

𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 322(𝑊𝐶𝑒𝑙𝑙 − 𝑊𝑇 )𝑅𝐷2 A = 𝜌𝐷 (𝐿𝐷 − 𝐿𝐴 −𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵

𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵

33

2

ln

𝑊𝑀𝑒𝑠𝑎
)
2

𝑊𝐶𝑒𝑙𝑙
𝑊𝑇

Cell pitch shrinking by double trenches structure
Fig. 2-14 shows a U-MOSFET structure designed to square cell. In this design, theWCell can be drastically shrunk by adopting double trenches process, which means
formation of trench gate and trench contact. The trench contact structures with metalplug have been reported [7] [30] [31] and 1.6–2.0 m cell pitches have already beenrealized [32] [33]. In the U-MOSFET, the WG in the case of the D-MOSFET is reduced toa WT due to vertical trench gate electrode, and the WB in the case of the D-MOSFET is
also reduced to a WMesa due to adopting narrow trench contact opening width.

Fig. 2-14. Bird’s eye view of U-MOSFET structure designed to square cell, which has
double trenches in unit cell. (Source and drain metals are not shown.) [40] © 2007 IEEE,[41]
The representative process flow of the U-MOSFET having double trenches isdisclosed in [34], and shown in Fig. 2-15(a)–(k).
(a) An n−–epitaxial layer on n+–substrate.
(b) Deposition of insulating layers consisted of silicon dioxide and silicon nitride,
followed by trench forming by photo-lithography and reactive ion-etching (RIE).
(c) Rounding treatment of the trench corners by sacrificial oxidation or chemical dry
etching (CDE).
(d) Gate poly-silicon deposition by low-pressure chemical vapor deposition (LP-CVD).
(e) Gate poly-silicon filling down to appropriate depth inside trench by RIE. Then, p–base and n+–source formation by ion-implantation, followed by thermal annealing.
(f) Inter-layer insulating film deposition by LP-CVD, followed by thermal annealing.
(g) Trench contact forming by photo-lithography and RIE down to appropriate depth d.
(h) p+–Body layer formation by ion-implantation and thermal annealing. Then barrier
metal (like titanium nitride) sputtering.
34

(i) Forming contact plug material (like tungsten) by CVD.
(j) Etching-back the contact plug material.
(k) Thick metal (like aluminum) formation on the device surface, followed by source/gateelectrodes patterning by photo-lithography and RIE. Then grinding and polishingback-surface, followed by back-surface metal formation for drain electrode.

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h)

(i)

(j)

(k)

Fig. 2-15. Process flow of U-MOSFET having double trenches [34].
3530-V sub-micron cell pitch U-MOSFET applying by burying interlayer
dielectric inside trench 1
For the low-voltage U-MOSFETs, various unit cell structures have been proposed toshrink the cell size and to achieve high performance. Self-aligned contact structures
realized by burying interlayer dielectric above poly-silicon gate inside trench waspresented in [35] [36] [37]. High density trench structures around 1.0-m-pitch wererealized in p-channel U-MOSFET firstly [38] and accumulation-mode n-channel UMOSFET also [39].
In this subsection, a newly developed sub-micron cell pitch 30-V-class n-channel UMOSFETs are described [40] [41]. In the narrow pitch U-MOSFET structure, a plural
layered oxide as interlayer dielectric (ILD) inside trench and the self-aligned contact are
adopted. This structure accomplishes the unit cell pitch less than 1.0 m. In addition,
structural parameters are optimized to achieve the lowest on-resistance performance forboth new rectangular cell design and stripe cell design.
Unit-cell design for total channel width maximization
As described in subsection 2.3.2, in the square cell design, although the unit cell size
is defined by WT and WMesa, the WMesa consists of three critical dimensions which are thetrench contact width and the n+–source width in both sides of the trench contact.
Fig. 2-16(a) shows the fabricated n-channel U-MOSFET structure of rectangular cell
design, where n+–source regions are divided by a p+–body region in a cell. In addition,
Fig. 2-16(b) shows the stripe cell design with alternatively arranged n+/p+ pattern inlonger direction of trench. In both structures, since the ILD is completely buried inside
trench, the surface of mesa region, which consists of n+–source and p+–body, can contact
directly to source metal (not shown in the figures). Thus the self-aligned contact
structure is realized in these cell design. Moreover, the unit cell size is given by sum ofjust two parameters, i.e., WT and WMesa which equals to the contact width.
In the rectangular cell design, adjacent cells are arranged each other with a half
pitch shift of the cell in longer direction. In this design, cross points of the orthogonal
trenches, which form depressions above the gate poly-silicon, are avoided.

1 Subsection 2.3.4 is reproduction of [40] chapter II and III, © 2007 IEEE, and a part of description ismodified and comprehensive explanations are additionally provided.

36

(a) Rectangular cell design.

(b) Stripe cell design.
Fig. 2-16. Bird’s eye view of newly developed U-MOSFETs structures. (Source and drain
metals are not shown.) Dx is trench pitch in narrower direction for both rectangular celland stripe cell. Dy is unit-cell length for rectangular cell. [40] © 2007 IEEE, [41]Fig. 2-17(a) shows the U-MOSFET unit-cell layout of 2.0-m-pitch square cell design,
which structure corresponds to Fig. 2-14. The channel width of the unit square cell issum of four sides surrounding trenches. Fig. 2-17(b) shows sub-micron-pitch rectangularcell design, which structure corresponds to Fig. 2-16(a). The channel width of the unit
rectangular cell is double of sum of three sides surrounding trenches. Fig. 2-17(c) shows
sub-micron-pitch stripe cell design, which structure corresponds to Fig. 2-16(b). The
channel width of the unit stripe cell is double of sum of two sides along trenches.

37

(a)

(b)

(c)

Fig. 2-17. Top views of U-MOSFET unit-cell layout for (a) 2-m-pitch square cell design,(b) sub-micron-pitch rectangular cell design, and (c) sub-micron-pitch stripe cell design.

Fig. 2-18(a) and Fig. 2-18(b) show calculated total channel width in 7.5 mm2 chiparea for the rectangular cell design and the stripe cell design, respectively. In therectangular cell, the total channel width increases with longer unit-cell length Dy in allinvestigated trench pitch Dx (0.8–1.2 m). In the stripe cell, the total channel width
becomes larger with respect to narrower trench pitch Dx.
The total channel width of the above two structures are compared with that of 2.0m square cell for the same chip area. The channel density of the rectangular cell exceedsthat of the square cell at Dy > 2.8 m (Dx = 1.0 m), and thus, the channel resistance canbe reduced. For the stripe design, almost the same effect is obtained at Dx < 1.0 m (Dy= 2.8 m). In both cases, p+–pitch (Dy) and p+–width are designed to maintain theavalanche robustness.

38

(a) Rectangular cell design(b) Stripe cell design
Fig. 2-18. Calculated total channel width in 7.5 mm2 chip area for (a) rectangular cell
design, which depends on Dy, and (b) stripe cell design, which depends on Dx and p+–
pitch. Channel width of 2-m square cell is indicated in both graphs for comparison.
[40] © 2007 IEEE (modified), [41].

39Fig. 2-19(a)–(c) show the simulated potential contours for narrow pitch U-MOSFETs
for Dx = 0.8 m, 1.0 m, and 1.2 m, respectively. In each simulation, the electricalpotential under the trench bottom level was uniformly distributed, and the VB was over
30 V. In the narrow pitch rectangular cell (or the stripe cell), the narrow space between
trenches causes uniform potential distribution and the resulting VB is higher than thatof the square cell. In the present structure, the epi-thickness can be reduced by 0.2 mand the epi-resistance component of the U-MOSFET can also be reduced.

(a)

(b)

(c)

(d)

Fig. 2-19. Simulated potential contours for U-MOSFETs. In short side (Dx) direction,
half size of (a) 0.8-m pitch, (b) 1.0-m pitch and (c) 1.2-m pitch, which correspond toboth stripe and rectangular cell, are simulated at p+–region. In long side (Dy) direction,(d) half size of rectangular cell is simulated. [40] (c) 2007 IEEE (modified), [41] (modified).

40

Process flow and essential process evaluation
The representative process flow of narrow pitch rectangular cell U-MOSFET isdisclosed in [42], and shown in Fig. 2-20(a)–(g) and Fig. 2-21(h)–(i).
(a) An n−–epitaxial layer on n+–substrate.
(b) Deposition of insulating layers consisted of silicon dioxide and silicon nitride,
followed by trench forming by photo-lithography and reactive ion-etching (RIE).
(c) Rounding treatment of the trench corners by sacrificial oxidation or chemical dry
etching (CDE).
(d) Gate oxidation and gate poly-silicon deposition by low-pressure chemical vapor
deposition (LP-CVD).
(e) Gate poly-silicon filling down to appropriate depth inside trench by RIE.
(f) Inter-layer insulating film deposition by LP-CVD, followed by planarization by
thermal annealing and etching-back to silicon surface by RIE.
(g) p–Base formation by ion-implantation, followed by thermal annealing. Then n+–source formation by photo-lithography and ion-implantation.
(h) p+–Body formation by photo-lithography and ion-implantation, followed by thermal
annealing.
(i) Barrier metal (like titanium nitride) and thick metal (like aluminum) sputtering on
the device surface, followed by source / gate electrodes patterning by photolithography and RIE.
Then grinding and polishing back-surface, followed by back-surface metal formation
for drain electrode.
The main points of the sub-micron cell pitch U-MOSFET are described below. The
trenches are formed by 0.25-m design rule process and have 1.0-m deep. The interlayer
dielectric between the gate poly-silicon and the source metal is fabricated by two typesof oxide. Firstly, Tetraethyl Orthosilicate (TEOS) is formed for good step coverage. Then,
Boron-Phosphor Silicate Glass (BPSG) is deposited, which has good reflow properties infollowing thermal annealing.

41

(a)

(b)

(c)

(d)

(e)

(f)

(g)
Fig. 2-20. Process flow of narrow pitch rectangular cell U-MOSFET. [42]

42

(h)

(i)
Fig. 2-21. Process flow of narrow pitch rectangular cell U-MOSFET. [42]43The cross-sectional SEM photograph of the fabricated 0.92-m pitch U-MOSFET isshown in Fig. 2-22(a). The interlayer dielectric is filled inside trenches, which is slightly
lower than silicon surface. Fig. 2-22(b) shows top view of the rectangular cells of the UMOSFET.

(a)

(b)

Fig. 2-22. SEM photograph of fabricated 0.92-m pitch UMOSFET. (a) Cross-sectionalview of an area including four trenches, observed by tilting angle of 45 degrees [40] ©
2007 IEEE (modified), [41]. (b) Top view of plural rectangular cells.

Fig. 2-23 shows gate leakage current as a function of the gate electric field for single
TEOS oxide and double layered oxide (TEOS and BPSG). The single TEOS oxide
property was not satisfactory due to occurrence of a weak spot of reduced thickness. In
contrast, in the case of the double oxide (TEOS and BPSG), ideal gate oxide properties
were observed, i.e., small leakage current of 1 nA at 6.6 MV/cm and high breakdown
electric field over 9.4 MV/cm. This demonstrates that the double oxide has a sufficientinsulation capability.

44

9.4 MV/cm

1.E-03
1.E-04Gate Leakage Current (A) .

1.E-05
1.E-06ILD

ILD

TEOS oxide

1.E-07TEOS oxide + BPSG

1.E-08
1.E-09

1 nA
at 6.6 MV/cm

1.E-101.E-11
1.E-12
0

1

2

3

4

5

6

7

8

9

10

11

12

Gate Electric Field (MV/cm)

Fig. 2-23. Comparison of gate leakage current as a function of the gate electric field for
fabricated UMOSFETs. [40] © 2007 IEEE (modified), [41]45Experimental results of device performance
A. On-resistance and principal characteristics
Fig. 2-24(a) and (b) show the cell dimension dependences of measured VB and RONA
at Vgs = 4.5 V for the rectangular cell and the stripe cell, respectively. The VB was over
30 V in all evaluated devices, and was independent of Dx and Dy.
The RONA of the rectangular cell was saturated for larger Dy (at Dx = 0.92 m andDx = 0.96 m). The tendency corresponded to the total channel width dependence shownin Fig. 2-18(a). The lowest RONA of the rectangular cell was obtained at Dx = 0.96 m andDy = 3.6 m. For this structure, the total channel width increased by 10% compared withthat of the 2.0-m square cell as shown in Fig. 2-18(a).
In the stripe cell, the RONA decreased with decrease in Dy monotonously (for p+–pitchof 3.2 m and 2.4 m). However, the RONA of the stripe depended on the dimensions
sensitively than that of the rectangular cell. It was found that the proposed rectangularcell has the advantages of process margin and RONA stability over the stripe structure.
The principal characteristics of the rectangular cell and the stripe cell are shown in
Table 2-6. The lowest RONA of 4.3 m·mm2 at Vgs = 10 V and 5.0 m·mm2 at Vgs = 4.5 V
were achieved in the rectangular cell with VTH = 0.94 V and VB = 30.5 V. For gate charge(Qg), almost the same RON·Qg performance was obtained for both structures.
In additionally fabricated rectangular cell U-MOSFET, the VB of 39 V, RONA of 8.1
m·mm2 at Vgs = 10 V, and 9.0 m·mm2 at Vgs = 4.5 V were obtained.

46

(a) Rectangular cell design(b) Stripe cell design
Fig. 2-24. Measured RONA and VB dependences on Dx, Dy and p+–pitch. [40] © 2007 IEEE
(modified), [41]47Table 2-6. Electrical characteristics of 30-V-class U-MOSFET for the rectangular cell andthe stripe cell. [40] [41]SymbolVB
VTHCharacteristics

Conditions

Rectangularcell

Stripecell

Unit

Breakdown
voltageThresholdvoltage

Id = 250 A

30.5

31.0

V

Vds = 10 V, Id = 1mA

0.94

0.94

V

RONA
RONA

On-resistanceOn-resistanceVgs = 10 V
Vgs = 4.5 V

4.3

4.5

m·mm25.0

5.3

m·mm2Qg
Qgd

Gate charge
Gate–drainchargeFOM

Vds = 15 V, Vgs = 5 V
Vds = 15 V

9.8
4.1

9.5
3.6

nC/mm2nC/mm2

42.1

42.8

m·pF

FOM

17.6

16.2

m·pF

Gate resistance

1.4

3.8



RON·Qg
RON·QgdRg

B. Avalanche capability
Fig. 2-25 shows waveforms of unclamped inductive switching (UIS) for fabricatedrectangular cell U-MOSFET (Dx = 1.0 m, Dy = 3.0 m) with VB of 39 V. In avalanche
capability examination, sufficient current density over 12 A/mm2 was confirmed, for Dx
range of 0.8–1.0 m and Dy range of 1.6–3.0 m in the rectangular cell chip of 7.5 mm2.

(a)

(b)

Fig. 2-25. Avalanche capability of fabricated rectangular cell UMOSFET for Dx = 1.0
m and Dy = 3.0 m. (a) Test circuit of unclamped inductive switching (UIS). (b)Waveforms of UIS for L = 100 H. [40] © 2007 IEEE (modified), [41]48Validation of on-resistance modelFig. 2-26 shows the RONA of developed 30-V-class U-MOSFET compared with thatof both analytical model and TCAD simulation. The structural parameters, electricalparameters and physical constants are indicated in Table 2-7, Table 2-8 and Table 2-4.
In the case of stripe cell that has continuous channel in longer direction of trench, the

RONA at Vgs = 4.5 V calculated by the model is 4.87 m·mm2, which corresponds to TCAD
result of 4.82 m·mm2 very well.
When the developed U-MOSFET that has n+/p+ patterns alternately in longer
direction of trench, the RONA, especially RCHA, increases according to a ratio of n+–lengthand p+–pitch (Rationp). In the case of stripe cell with Rationp = 0.7, the RONA at Vgs = 4.5
V calculated by the model is 5.25 m·mm2, which corresponds to the experimental resultof 5.2 m·mm2, with less than 1.0% error.

49

Specific on-resistance (m•mm2)

7

Specific on-resistance (m•mm2)

7

6
5
4
3

2
1
0

Vgs=4.5V

5.25

4.82

4.87

0.92

0.90

0.27

0.31

0.31

RD A

2.14

2.16

2.16

RSUBA

1.50

1.50

1.50

RCHA
RA A

5.2

1.28

TCAD Model Model Exp.
stripe stripe stripe stripe
0.92um 0.92um 0.92um 0.92um
n/p=0.7 n/p=0.7

6

Vgs=10V

5

4.34

4.18

4.19

0.36
0.18

0.35
0.14

0.50
0.14

3

RCHA
RA A

RD A

2.15

2.16

2.16

2

RSUBA

1.50

1.50

1.50

4

1
0

4.5

TCAD Model Model Exp.
stripe stripe stripe stripe
0.92um 0.92um 0.92um 0.92um
n/p=0.7 n/p=0.7

Fig. 2-26. Experimental results of RONA for developed 30-V-class U-MOSFET comparedwith that of both analytical model and TCAD simulation. Under the condition of Vgs =4.5 V, 10 V.

50

Table 2-7. Structural parameters of 30-V-class U-MOSFET to calculate RONA.
Symbol

WCell
WT
WMesa
DT
LCH
LA
KA
TGOX
XJS
XJB
p+ pitch
Rationp
LD
D
ND
TSUB
SUB
NSUB

Parameters

Numerics

Unit

Cell width

0.92

m

Trench width

0.44

m

Mesa width

0.48

m

Trench depth

1.00

m

Channel length

0.40

m

Accumulation length

0.07

m

Coefficient of current spreading in
the accumulation region
Gate oxide thickness

0.60



0.03

m

n+–Source junction depth

0.50

m

p–Base junction depth

0.90

m

p+–Pitch

3.20

m

Ratio of n+–length / p+–pitch
n–Drift layer length

0.70
1.00

m

Resistivity of n–drift layer

0.21
2.89 × 1015

•cm
atoms/cm3100

m0.0015
4.63 × 1019

•cm
atoms/cm3

Drift layer concentration
n+–Substrate thickness
Resistivity of n+–substraten+–Substrate concentration

Table 2-8. Electrical parameters of 30-V-class U-MOSFET to calculate RONA.
Symbol

Vgs
VTH
ni
na
n_D
n_SUB

Parameters
Gate–source voltage
Threshold voltage
Electron mobility of inversion layer

Numerics
4.5, 10
0.94
500

Unit
V
V
cm2/VsElectron mobility of accumulation
layerElectron mobility of n–drift layer

500

cm2/Vs1000

cm2/VsElectron mobility of n+–substrate

72

cm2/Vs51

Summary
In chapter 2, as improvement of the power loss for the LV-MOSFET, planar gate
double-diffused MOSFET (D-MOSFET) and trench gate MOSFET (U-MOSFET) were
described. The RONA models of both D-MOSFETs and U-MOSFETs were detailed for two
different surface patterns (stripe and square cell), respectively. In addition, each
improvement structure, fabrication process, and evaluation result of the fabricateddevices were described. In the validation of the RONA models, the real device andcalculated results by the model were compared for both 60-V D-MOSFET and 30-V UMOSFET, and it was confirmed they showed good agreement.
As a summary of the development of the advanced low-power-loss MOSFETs, theperformances are compared each other due to benchmarking of U-MOSFETs. The
tradeoff between the VB and the RONA for 20–40-V-class U-MOSFETs is shown in Fig.
2-27. As reference line, one-dimensional (1-D) silicon-limit [11] is indicated. The
developed rectangular cell U-MOSFETs’ performances [40] [41] are superior to the
published data [32] [33] [39] [43] [44] [45] [46] by approximately 30%.

Fig. 2-27. Tradeoff between RONA and VB for U-MOSFETs by published data [32] [33][39] [43] [44] [45] [46] and author’s research [40] [41].

52DEVELOPMENT OF NOVEL CHARGE COMPENSATION
DEVICES: SJ-UMOSFETS AND FP-MOSFETS
Charge compensation structures for LV-MOSFETs
As great advancements of LV-MOSFETs in terms of performance, field-plate UMOSFETs (FP-MOSFETs) [8] [47] [48] [49] [50] [51] [52] and superjunction U-MOSFETs(SJ-UMOSFETs) [53] [54] [55] [56] [57] were developed and commercialized in the early
to mid-2000s.
The FP-MOSFETs applied fundamental technology called Reduced Surface Field(RESURF), which was devised for high-voltage lateral devices in 1979 [58] [59], tovertical direction. On the other hand, the theory of superjunction has been introduced in
1997 [60] and the SJ-MOSFET has firstly developed as HV-MOSFET, which was 600-Vclass, by multiple-epitaxial technology [9]. After that the principle of superjunction
applied to LV-MOSFETs, by changing the method to form the superjunction structure.
In both types of MOSFETs, on-resistance (RONA) could be drastically reduced witha high breakdown voltage (VB) maintained. In particular, the FP-MOSFETs achieved not

Fig. 3-1. Technology development history for vertical power MOSFETs.
Highlights show author’s research. (Re-publication of Fig. 2-1)
53

only ultralow RONA but also very low reverse transfer capacitance (Crss) and gate–draincharge (Qgd) owing to the shielded-gate structure. Therefore, the FP-MOSFETs are
currently the mainstream of high-performance applications and their advancement is
continuing.
Fig. 3-1 shows technology development history of vertical power MOSFETs.

(a)

(b)

(c)

Fig. 3-2. Charge compensation for SJ-UMOSFET. Depletion layer formation when (a)low voltage and (b) high voltage are applying. (c) Charge compensation by p/n–columns.

(a)

(b)

(c)

Fig. 3-3. Charge compensation for FP-MOSFET. Depletion layer formation when (a) low
voltage and (b) high voltage are applying. (c) Charge compensation by using field-plate.
54

Basic principles of superjunction devices.
Superjunction structure has been originally proposed for high-voltage devices, andthe (high-voltage) SJ-MOSFET structure actually achieved the significant improvementof tradeoff between RONA and VB [60] [9], which exceeded 1-D silicon-limit [11].
Fig. 3-2(a)–(c) explains charge compensation principle in the (low-voltage) SJUMOSFET structure. In this structure, p–columns and n–columns are alternately
arranged in the drift layer in lateral direction. When a voltage is applied to the drainelectrode, boundaries of each p/n–column begin to form the depletion layer in a low
voltage (Fig. 3-2(a)) and full depletion layer is formed with increasing the voltage (Fig.
3-2(b)). At the time, charge in the drift layer is compensated between the p/n–columns(Fig. 3-2(c)). Thus, high VB is guaranteed even in a high n–column layer impurity
concentration for the superjunction structure.
Due to the fully-depleted drift layer, an ideal VB of the SJ-UMOSFET (which is sameas that of the SJ-MOSFET) can be given by simplified expression.
(3-1)

𝑉𝐵 (ideal, SJ) ≈ 𝐸𝐶 𝑇𝑆𝐽

Here, EC is a critical electric field and TSJ is a thickness of the p/n–column. To simplify
calculation of the drift layer resistance (RDA), it assumes both width of p–column (WP)
and n–column (WN) are same. Then an ideal RDA is expressed as
𝑅𝐷 A(ideal, SJ) ≈2𝑇𝑆𝐽,𝑞𝜇𝑒 𝑁𝐷(3-2)

where q is the elementary charge, ND is the n–column layer concentration, ande is
electron mobility in the n–column layer. Meanwhile the charge balance condition
between the p/n–columns and the optimum charge density, which is lead from Poisson's
equation, are given by the following [11] [59] [60].
𝑁𝐷𝑊𝑁𝑊𝑃 𝜀𝑆𝑖 𝜀0 𝐸𝐶
= 𝑁𝐴
=
2
2
𝑞

(3-3)

Here NA is the p–column layer concentration and Si0 is the permittivity of silicon. By
substituting Eqs. (3-1) and (3-3) into Eq. (3-2), the ideal RDA can be obtained
𝑅𝐷 A(ideal, SJ) ≈𝑉𝐵 𝑊𝑁
𝜇𝑒 𝜀𝑆𝑖 𝜀0 𝐸𝐶 2

55

.

(3-4)

Basic principles of field-plate devices
Field-plate technology bases on the RESURF principle [58] [59], and the FPMOSFET is applying it in each unit cell structure in vertical direction. The FP-MOSFET
has also achieved the significant improvement of tradeoff between RONA and VB in underthe 100-V-class [50] [51], which exceeded 1-D silicon-limit [11].
Fig. 3-3(a)–(c) explains charge compensation principle in the FP-MOSFET structure.
When a voltage is applied to the drain electrode, the field-plate inside the trench gives
electric field effect to silicon mesa region through thick oxide. Therefore, in a low voltage,
the depletion layer expands from both boundaries of pn-junction and oxide/silicon mesa
(Fig. 3-3(a)). Then, full depletion layer is formed with increasing the voltage (Fig. 3-3(b)).
At the time, charge in the drift layer is compensated by the field-plate [61] (Fig. 3-3(c)).
Thus, like the SJ-UMOSFET, high VB is guaranteed even in a high n–drift layer impurity
concentration for the FP-MOSFET structure.
Due to the fully-depleted drift layer, an ideal VB of the FP-MOSFET can be given bysimplified expression.
(3-5)

𝑉𝐵 (ideal, FP) ≈ 𝐸𝐶 𝐿𝐷

Here, LD is a length of the n–drift layer. To simplify calculation of the drift layer
resistance (RDA), it assumes both width of trench (WT) and silicon mesa (WMesa) are same.
Then an ideal RDA is expressed as
𝑅𝐷 A(ideal, FP) ≈2𝐿𝐷,
𝑞𝜇𝑒 𝑁𝐷(3-6)

The charge balance condition of the FP-MOSFET is accomplished by the optimum charge
density, which is lead from Poisson's equation, and is given by the following [11] [59] [60].
𝑁𝐷

𝑊𝑀𝑒𝑠𝑎 𝜀𝑆𝑖 𝜀0 𝐸𝐶
=
2
𝑞

(3-7)

By substituting Eqs. (3-5) and (3-7) into Eq. (3-6), the ideal RDA can be obtained
𝑅𝐷 A(ideal, FP) ≈𝑉𝐵 𝑊𝑀𝑒𝑠𝑎
𝜇𝑒 𝜀𝑆𝑖 𝜀0 𝐸𝐶 2

56

.

(3-8)

Superjunction U-MOSFET (SJ-UMOSFET) featuring a low-voltage
deviceBasic structure and on-resistance (RONA) components of SJ-UMOSFET
Schematic cross-sectional structure of SJ-UMOSFET for two unit-cells area isshown in Fig. 3-4. Fig. 3-4(a) shows a distribution of electric field Ey of drift layer invertical direction y, when a reverse bias applies to the drain. In an ideal SJ-UMOSFET,
the Ey is distributed like a trapezoid and a critical electric field EC is nearly uniform,
which are different from those of the D-MOSFET or the U-MOSFET. VB of twodimensional superjunction is determined by the area of this electric field and is given by
𝐿𝑑𝑒𝑝

𝑉𝐵 ≈ ∫

𝐸𝑦 𝑑𝑦.

(3-9)

0Here Ldep is depletion layer length in y. In assumption, if a depletion layer length in thep–base region is negligible, the VB of SJ-UMOSFET is approximated as
1
𝑉𝐵 ≈ 𝐸𝐶 (𝑇𝑆𝐽 − 𝑇𝐵𝑈𝐹 ) + 𝐸𝐶 𝑇𝐵𝑈𝐹 ,2(3-10)

where TSJ is p–column thickness and TBUF is buffer layer thickness under the p–column,
which shares a part of the VB. The VB of SJ-UMOSFET is independent from ND, which
is different from the case of the D-MOSFET or the U-MOSFET. The VB and the RDA has
a nearly linear relationship that is described as RDA ∝ VB1.1 in [60].
Fig. 3-4(b) shows on-state current paths and on-resistance components of SJUMOSFET. The RN+A is negligible as well as that of U-MOSFET. The RONA of SJUMOSFET (RONSJUMOSA) can be approximated by using main components,
𝑅𝑂𝑁 𝑆𝐽𝑈𝑀𝑂𝑆 A ≈ 𝑅𝐶𝐻 𝐴 + 𝑅𝐴 𝐴 + 𝑅𝐷1 𝐴 + 𝑅𝐷2 𝐴 + 𝑅𝑆𝑈𝐵 𝐴.

(3-11)In Eq. (3-11), RCHA and RAA are divided into three cases, i.e., the SJ-UMOSFET
design is stripe geometry, square cell geometry, or square p–column in stripe trench. Fig.
3-5(a) shows structural parameters of SJ-UMOSFET. As shown in Fig. 3-5(b) and Fig.
3-5(c), channel width per unit area “A” is shown as 2𝑊𝐶𝑒𝑙𝑙 ⁄𝑊𝐶𝑒𝑙𝑙 2 = 2⁄𝑊𝐶𝑒𝑙𝑙 in stripe cell
design, or 4𝑊𝑀𝑒𝑠𝑎 ⁄𝑊𝐶𝑒𝑙𝑙 2 in square cell design. Here, WCell is cell width and WMesa ismesa width.

57

(a)

(b)

Fig. 3-4. Schematic cross-sectional structures of SJ-UMOSFET, which shows two unitcells area. (a) Electric field distribution in vertical direction of off-state. (b) On-state
current paths and components of on-resistance.

RCHA, RAA and RSUBA in Eq. (3-11) are expressed by analytical model as below.
𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙,in stripe cell
2𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙,in stripe cell (square p − column)
2𝜇𝑛𝑖 𝐶𝑔𝑜𝑥 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )𝑅𝐶𝐻 A =𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙 2{

4𝑊𝑀𝑒𝑠𝑎 𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 ),(3-12)

in square cell

(2𝐿𝐴 + 𝑊𝑇 )𝑊𝐶𝑒𝑙𝑙,in stripe cell
4𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠(2𝐿𝐴 + 𝑊𝑇 )𝑊𝐶𝑒𝑙𝑙𝐾𝐴,
in stripe cell (square p − column)
𝑅𝐴 A =
4𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠(2𝐿𝐴 + 𝑊𝑇 )𝑊𝐶𝑒𝑙𝑙 2𝐾𝐴,in square cell
8𝑊𝑀𝑒𝑠𝑎 𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠{(3-13)𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵

(3-14)

𝐾𝐴

58

(a)

(b)

(c)

Fig. 3-5. (a) Structural parameters of SJ-UMOSFET. Top view of SJ-UMOSFET unitcell layout for (b) square cell design and (c) stripe cell design.

Here, WT is trench width and other same symbols are the same as those of subsection
2.2.1, i.e., LCH is channel length, LA is accumulation length, SUB is resistivity of n+–
substrate, TSUB is thickness of the n+–substrate, ni is electron mobility of inversion layer,

na is electron mobility of accumulation layer, CGOX is gate oxide capacitance, Vgs is gate
voltage, and VTH is threshold voltage. KA is a coefficient of considering current spreadingfrom the accumulation region to the drift region [25] [26]. In Eq. (3-13), the total
accumulation length of the unit cell is given by 2𝐿𝐴 + 𝑊𝑇 . KA is assumed to be around
0.7.
In addition, RD1A and RD2A in Eq. (3-11) are also divided into three cases, i.e., theSJ-UMOSFET design is stripe geometry, square cell geometry or square p–column in
stripe trench. By using other components which are RD_PA, RD_TA and RD_NA as shownin Fig. 3-6 and Fig. 3-7, RDA is expressed by analytical model as below.
𝑅𝐷 A = 𝑅𝐷1 A + 𝑅𝐷2 A

59(3-15)

𝑅𝐷_𝑃 A,𝑅𝐷 A =

in stripe cell

𝑅𝐷_𝑁 𝐴 ∙ 𝑅𝐷_𝑃 𝐴,
in stripe cell (square p − column)
𝑅𝐷_𝑁 𝐴 + 𝑅𝐷_𝑃 𝐴
𝑅𝐷_𝑇 𝐴 ∙ 𝑅𝐷_𝑃 𝐴,
in square cell𝑅{
𝐷_𝑇 𝐴 + 𝑅𝐷_𝑃 𝐴

𝑅𝐷1_𝑃 A + 𝑅𝐷2_𝑃 A,
in stripe cell
𝑊𝐶𝑒𝑙𝑙
(𝑅𝐷1_𝑃 A + 𝑅𝐷2_𝑃 A),
in stripe cell (square p − column)
𝑅𝐷_𝑃 A = 𝑊𝑃
𝑊𝐶𝑒𝑙𝑙 2
(𝑅𝐷1_𝑃 A + 𝑅𝐷2_𝑃 A),
in square cell
𝑊𝐶𝑒𝑙𝑙 2 − 𝑊𝑇 2{

𝑅𝐷1_𝑃 A =𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 𝑊𝑁 − 𝑊𝑑𝑒𝑝_𝑁
ln
2
𝑊𝑇𝑊𝑀𝑒𝑠𝑎 − 𝑊𝑃 − 𝑊𝑑𝑒𝑝_𝑁
𝜌𝐷 𝑊𝐶𝑒𝑙𝑙+(𝑇𝑆𝐽 − 𝐿𝐴 −)𝑊𝑁 − 𝑊𝑑𝑒𝑝_𝑁
2

𝑅𝐷2_𝑃 A =𝑊𝑃 + 𝑊𝑑𝑒𝑝_𝑁
𝜌𝐷 𝑊𝐶𝑒𝑙𝑙𝑊𝐶𝑒𝑙𝑙ln+ 𝜌𝐷 (𝑇𝐵𝑈𝐹 −)2
𝑊𝑁 − 𝑊𝑑𝑒𝑝_𝑁
2

𝑅𝐷_𝑇 A =𝑅𝐷_𝑁 A =𝑊𝐶𝑒𝑙𝑙 2𝑊𝑇 2

𝜌𝐷 (𝑇𝑆𝐽 − 𝐿𝐴 + 𝑇𝐵𝑈𝐹 )𝑊𝐶𝑒𝑙𝑙𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 𝑊𝐶𝑒𝑙𝑙
𝑊𝑀𝑒𝑠𝑎ln+ 𝜌𝐷 (𝑇𝑆𝐽 − 𝐿𝐴 −+ 𝑇𝐵𝑈𝐹 )][𝑊𝑁 − 𝑊𝑑𝑒𝑝_𝑁
2
𝑊𝑇
2(3-16)(3-17)(3-18)(3-19)(3-20)(3-21)

Here, D is resistivity of n–drift layer, WP is p–column width and WN is n–column width
which equals to a distance between p–columns. Moreover, Wdep_N is depletion layer widthat p–column/n–column junction and is given by

2𝜀𝑆𝑖 𝜀0 (𝑉𝑏𝑖 + 𝑉𝑂𝑁 )𝑁𝐴
𝑊𝑑𝑒𝑝_𝑁 = √[],𝑞
𝑁𝐷 (𝑁𝐴 + 𝑁𝐷 )(3-22)

where q is the elementary charge, Si0 is the permittivity of silicon, Vbi is built-in
potential at the pn-junction, VON is on-state voltage, ND is n–drift layer concentration
and NA is p–column layer concentration.

60

In stripe cell, the RDA is series resistance of RD1_PA and RD2_PA, as expressed in Eqs.
(3-16)–(3-19), and shown in Fig. 3-4(b). The RD1_PA is a drift layer resistance between p–
columns, which is spreading from under the trench to p–columns. The RD2_PA is a buffer
layer resistance, which is spreading to under p–columns.
In square cell, the RDA is parallel resistance of RD_PA and RD_TA, as expressed in
Eqs. (3-16)–(3-20), and shown in Fig. 3-6(a). The RD_PA is a part of drift layer resistancewhich is between p–columns, as shown in Fig. 3-7(b). The RD_TA is another part of drift
layer resistance which is under trench intersection, as shown in Fig. 3-6(c).
In stripe cell with square p–column, the RDA is parallel resistance of RD_PA and

RD_NA, as expressed in Eqs. (3-16)–(3-19) and (3-21), and shown in Fig. 3-7(a). The RD_PA
is a part of drift layer resistance which is between p–columns under the trench, as shownin Fig. 3-7(b). The RD_NA is remaining part of drift layer resistance, as shown in Fig.
3-7(c).
To improve the RONSJUMOSA with necessary VB maintained, all the components of

RONSJUMOSA have to be reduced by individual appropriate techniques.

61

RD1_T

WP
WN

RD1_P

WT

WCell

WCell

WT WMesaLA

WT WMesa½(WMesa-WP)

RD1_P

n

45o



n D
W P WN

TSJ

RD2_P

(a)

(b)

TBUF

n

RD_T

(c)

Fig. 3-6. (a) Top view of SJ-UMOSFET for square cell layout. Schematic cross-sectional
structure, which shows components of the n–drift layer resistance (RD1_P, RD2_P, RD_T).
(b) Current flow spreading in 45 degrees from four sides surrounding the square p–
column. (c) Current flow under trench intersection.

(a)

(b)

(c)

Fig. 3-7. (a) Top view of SJ-UMOSFET for square p–column in stripe cell layout.
Schematic cross-sectional structure, which shows components of the n–drift layer
resistance (RD1_P, RD2_P, RD_N). (b) Current flow spreading in 45 degrees from both sidesof the square p–column. (c) Current flow spreading in 45 degrees in n–drift region.
62

List of on-resistance model

Table 3-1. List of RONA model equations for SJ-UMOSFET (stripe and square cell design).
Stripe𝑅𝐶𝐻 A =

Square cell

𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙

𝑅𝐶𝐻 A =

2𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )𝑅𝐴 A = 𝐾𝐴(2𝐿𝐴 + 𝑊𝑇 )𝑊𝐶𝑒𝑙𝑙
4𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠

4𝑊𝑀𝑒𝑠𝑎 𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )𝑅𝐴 A = 𝐾𝐴

𝑅𝐷 A = 𝑅𝐷1_𝑃 A + 𝑅𝐷2_𝑃 A
𝑅𝐷1_𝑃 A =𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙 2

𝑅𝐷 A =

𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 𝑊𝑁 − 𝑊𝑑𝑒𝑝_𝑁
ln
2
𝑊𝑇𝜌𝐷 𝑊𝐶𝑒𝑙𝑙+(𝑇 − 𝐿𝐴𝑊𝑁 − 𝑊𝑑𝑒𝑝_𝑁 𝑆𝐽
𝑊𝑀𝑒𝑠𝑎 − 𝑊𝑃 − 𝑊𝑑𝑒𝑝_𝑁−)2(2𝐿𝐴 + 𝑊𝑇 )𝑊𝐶𝑒𝑙𝑙 2
8𝑊𝑀𝑒𝑠𝑎 𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠

𝑅𝐷_𝑇 𝐴 ∙ 𝑅𝐷_𝑃 𝐴
𝑅𝐷_𝑇 𝐴 + 𝑅𝐷_𝑃 𝐴

𝑅𝐷_𝑇 A =𝑊𝐶𝑒𝑙𝑙 2𝑊𝑇 2

𝜌𝐷 (𝑇𝑆𝐽 − 𝐿𝐴 + 𝑇𝐵𝑈𝐹 )𝑅𝐷_𝑃 A = 𝑅𝐷1_𝑃 A + 𝑅𝐷2_𝑃 A
𝑅𝐷1_𝑃 A =𝜌𝐷 𝑊𝐶𝑒𝑙𝑙
𝑊𝐶𝑒𝑙𝑙
𝑅𝐷2_𝑃 A =ln
2
𝑊𝑁 − 𝑊𝑑𝑒𝑝_𝑁
𝑊𝑃 + 𝑊𝑑𝑒𝑝_𝑁+ 𝜌𝐷 (𝑇𝐵𝑈𝐹 −)2

𝑅𝐷2_𝑃 A =𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵

𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 𝑊𝑁 − 𝑊𝑑𝑒𝑝_𝑁
ln
2
𝑊𝑇𝜌𝐷 𝑊𝐶𝑒𝑙𝑙+(𝑇 − 𝐿𝐴𝑊𝑁 − 𝑊𝑑𝑒𝑝_𝑁 𝑆𝐽
𝑊𝑀𝑒𝑠𝑎 − 𝑊𝑃 − 𝑊𝑑𝑒𝑝_𝑁−)2
𝜌𝐷 𝑊𝐶𝑒𝑙𝑙𝑊𝐶𝑒𝑙𝑙ln2
𝑊𝑁 − 𝑊𝑑𝑒𝑝_𝑁
𝑊𝑃 + 𝑊𝑑𝑒𝑝_𝑁+ 𝜌𝐷 (𝑇𝐵𝑈𝐹 −)2𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵

63

Table 3-2. List of RONA model equations for SJ-UMOSFET (square p–column in stripe
trench).
Stripe (square p–column)
𝑅𝐶𝐻 A =𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙
2𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )𝑅𝐴 A = 𝐾𝐴
𝑅𝐷 A =(2𝐿𝐴 + 𝑊𝑇 )𝑊𝐶𝑒𝑙𝑙
4𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠

𝑅𝐷_𝑁 𝐴 ∙ 𝑅𝐷_𝑃 𝐴
𝑅𝐷_𝑁 𝐴 + 𝑅𝐷_𝑃 𝐴

𝑅𝐷_𝑁 A =𝑊𝐶𝑒𝑙𝑙𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 𝑊𝐶𝑒𝑙𝑙
𝑊𝑀𝑒𝑠𝑎
[
ln
+ 𝜌𝐷 (𝑇𝑆𝐽 − 𝐿𝐴 −+ 𝑇𝐵𝑈𝐹 )]𝑊𝑁 − 𝑊𝑑𝑒𝑝_𝑁
2
𝑊𝑇
2

𝑅𝐷_𝑃 A = 𝑅𝐷1_𝑃 A + 𝑅𝐷2_𝑃 A
𝑅𝐷1_𝑃 A =𝑊𝑀𝑒𝑠𝑎 − 𝑊𝑃 − 𝑊𝑑𝑒𝑝_𝑁
𝜌𝐷 𝑊𝐶𝑒𝑙𝑙 𝑊𝑁 − 𝑊𝑑𝑒𝑝_𝑁
𝜌𝐷 𝑊𝐶𝑒𝑙𝑙ln+(𝑇 − 𝐿𝐴 −)2
𝑊𝑇𝑊𝑁 − 𝑊𝑑𝑒𝑝_𝑁 𝑆𝐽
2

𝑅𝐷2_𝑃 A =𝑊𝑃 + 𝑊𝑑𝑒𝑝_𝑁
𝜌𝐷 𝑊𝐶𝑒𝑙𝑙𝑊𝐶𝑒𝑙𝑙ln+ 𝜌𝐷 (𝑇𝐵𝑈𝐹 −)2
𝑊𝑁 − 𝑊𝑑𝑒𝑝_𝑁
2

𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵

64

60-V narrow pitch SJ-UMOSFET applying multiple-ion-implantation 2
The RONA of the LV-MOSFET can be drastically reduced by adopting superjunction(SJ) consisting of repeated deep p/n–columns [62] [63]. For the superjunction structuressatisfying charge balance condition, the higher performance is obtained for the narrower
pn-junction pitch. However, in the conventional D-MOSFETs with narrow cell pitch, themerit of the superjunction introduction would be reduced, because the RJFETA becomesdominant as the cell pitch is scaled down.
In this subsection, the superjunction concept combined with the U-MOSFET, which
is ideal structure for future scaling, is described [10] [64]. The superjunction structurewith deep p–columns is formed by multiple boron implantations with varied energies up
to 2.0 MeV. This technique enables to make narrow pitch pn-junctions, which arefavorable to reduce the RONA.
Firstly, simulated properties of the multiple boron implantations are described,
followed by electrical characteristics of the simulated SJ-diodes and SJ-UMOSFETs.
Then, the experimental results on the fabricated SJ-diodes is presented. Finally, theperformance of the proposed SJ-UMOSFETs is demonstrated.
Unit-cell structure design and device simulation
Schematic cross-sectional structures of the basic unit cell for the SJ-UMOSFETs areshown in Fig. 3-8(a) and (b). The p–columns are formed in n–epitaxial layer (n–epi layer)
by high energy boron ion implantations through mask windows. The ions are injectedvertically to the silicon wafers. The implantation process is divided into multiple
injections with different energies up to maximum value of 2.0 MeV. Depending on thenumber of the boron ion implantations, three types of structures, which is single p–
column, split p–column, or continuous p–column, can be fabricated, as shown in Fig. 3-9.
In the case of the split p–column or the continuous p–column, the middle energies
are chosen to equalize peak separation in the boron doping profile. The resultant p–column region is 2.5–3.0-m deep and 1.0–2.0-m wide, depending on the mask window
widths and the maximum implantation energies. The impurity concentrations in the n–
epi layer and the boron dose are varied to optimize charge balance between the depletedn– and p–regions under reverse biases.

2

Subsection 3.2.3 is reconstruction of [10] chapter II–IV, © 2004 IEEE, and [64] chapter II–IV, © 2005
IEEE. A part of description is modified and comprehensive explanations are additionally provided.

65

(a) Number of p–columns N = 4.

(b) Number of p–columns N = 2.

Fig. 3-8. Schematic cross-sectional structures of developed SJ-UMOSFETs fabricatedby using multiple-ion-implantation. (a) Continuous p–column [10] © 2004 IEEE
(modified). (b) Split p–column [64] © 2005 IEEE (modified).

(a) Single p–column.
(N = 1)(b) Split p–column.
(N = 2)(c) Continuous p–column.
(N = 4).

Fig. 3-9. Number of the ion-implantations for SJ-UMOSFETs fabrication.
66

To evaluate the properties of the present superjunction structures, process anddevice simulations are performed. The Monte Carlo method is used to simulate the boron
implantations for deep p–column formation.
The VB dependence on boron doping profile was investigated for two-dimensional
SJ-diode structures. The profile is changed by number of boron injections, defined by N,
keeping the total dose constant. In evaluating the SJ-UMOSFET performance,
superjunction structures are added to the optimized U-MOSFET structures, which havea cell size of 3.0 or 4.0 m.
Fig. 3-10 shows boron doping profiles along the center of the p–column. For a single
injection (N = l), the boron doping profile has a peak at 2.5 m in depth. As the numberof injections increases, the profile gets more uniform, as expected.
Fig. 3-11 shows the dependence of the VB on the number of injections. The VB
increases rapidly from N = 0 (non-SJ) to N = 2, while it saturates for N ≥ 3. This resultmeans that the boron profile for N = 4 in Fig. 3-10 is sufficiently uniform to achieve amaximum VB under a given charge balance condition. It would be appropriate to set N =2–4 to reduce the cost performance in the SJ-UMOSFET fabrication processes.

Fig. 3-10. Simulated boron doping profiles along the p–column center. The profiles fordifferent number of boron injections are compared. [64] © 2005 IEEE (modified).
67

Fig. 3-11. Dependence of the simulated VB on the number of boron injections for aconstant total dose of 1.2×1013 cm−2 and a common maximum energy of 1.5 MeV.
[10] © 2004 IEEE.
Next, performances of the SJ-UMOSFET adopting the above p–columns (N = 4) areinvestigated. Fig. 3-12 shows drain current characteristics (Id-Vds) at the Vgs of 10 V for
4.0-m cell U-MOSFET and SJ-UMOSFET, which have the VB of approximately 80 V. By
introducing the superjunction structure, the drain current increased drastically, while
the VB is maintained almost constant. This is because the resistivity and the thicknessof the n–epi layer could be reduced by 40% and 20%, respectively. The RONA reduction isover 30% at Vgs = 10 V.

Fig. 3-12. Simulated Id–Vds characteristics of the SJ-UMOSFET and conventional UMOSFET are compared for 4-m cell devices. [10] © 2004 IEEE.
68

Fig. 3-13 shows avalanche current flow lines at room temperature of the SJUMOSFETs for N = 4, in comparison of two different p–column dose conditions. To
ensure the high avalanche immunity, the avalanche current through the p–column ispreferred, but not vicinity of the trench gate. When the p–column dose is enough high,the preferable current flow is confirmed as shown in Fig. 3-13(b).

(a) N = 4, p–column: 2.0×1012 cm−2, (b) N = 4, p–column: 2.5×1012 cm−2,and room temperature.

and room temperature.

Fig. 3-13. Simulated avalanche current flow lines at room temperature of the SJUMOSFETs for N = 4, in comparison of two different p–column dose conditions. [10] ©
2004 IEEE (modified).

It is better to use a higher dose for the p–column, however, since the avalanche
current causes self-heating, the current path should be characterized at a higher
temperature. Fig. 3-14(a) shows the avalanche current flow lines at room temperature
for N = 2. In this structure, the current flows through the p–column region. This meansthat gate oxide damage can be avoided when breakdown occurs at room temperature.
Fig. 3-14(b) shows the lateral distribution of the avalanche current that flows at
150°C across the horizontal plane in the middle depth of the p–column. At thistemperature, the current flows mainly through the p–column for N = 2, while it flows
preferably along the trench gate for N = 4. This difference can be explained by the factthat higher impurity concentration causes higher field modulation at the bottoms of thep–column regions.
69

(a) N = 2, p–column: 2.5×1012 cm−2,(b) 150°C

and room temperature
Fig. 3-14. (a) Simulated avalanche current flow lines at room temperature of the SJUMOSFET for N = 2. (b) Avalanche current density at 150°C across the horizontal planein the middle depth of the p–column, in comparison of N =2 and N = 4. [64] © 2005 IEEE
(modified).

The simulated results demonstrate that the present device structures are quite
promising to achieve ultra-low on-resistance. Further, the multiple implantation
technique would be suitable for the SJ-UMOSFET fabrication, because the superjunction
structures can be modified flexibly by altering implantation conditions to achieve better
device performance and higher reliability.
As shown in Fig. 3-8(b), the SJ-UMOSFET with split p–column structures consistsof p–islands separated by small distances in the n–epi layer. The structure is shown tohave good avalanche current properties, and it is expected that ultralow RONA and good
dynamic properties can be achieved.

70Fig. 3-15 shows the VB and the RONA for N = 4, 2, and 1, in comparison of two typesof n–epi layers. The VB dependence on N indicates that the superjunction effect is large
as compared with conventional U-MOSFETs without p–column (N = 0), which are 52.4
V and 35.8 V. It is notable that the VB of N = 2 are as high as those of N = 4 for both typesof n–epi layers, while the VB of N = l is significantly lower than those of the formers. On
the other hand, the RONA does not change depending on N.
In this way, the simulated results demonstrate that the split p–column structure iseffective for improving the avalanche current properties, without sacrificing the benefitsof the superjunction structure.

(a)

(b)

Fig. 3-15. (a) VB and (b) RONA of optimized SJ-UMOSFETs for N = 4, 2, and 1, incomparison of two types of n–epi layers. [64] (modified).

71Process evaluation for superjunction structure
As previous evaluation of the SJ-UMOSFET, a simple SJ-diode consisting of deep p–columns in n–epi layers was fabricated. The p–columns with 3-m pitch were formed bymultiple boron implantations using mask patterns. The maximum implantation energies
were set at 1.5 MeV and 2.0 MeV, with N = 4 and N = 5 injections, respectively. The
thickness and impurity concentrations in the n–epi layers were varied to evaluate thecharge balance conditions.
Fig. 3-16 shows the cross-sectional scanning capacitance microscopy (SCM) image of
the SJ-diodes fabricated by boron implantations up to 2.0 MeV. The p–columns areindicated by the vertically expanding bright regions with depth of 3.0 m and width of
1.0 m. Dark lines clearly defining the p/n interfaces suggest that abrupt pn-junctions
are formed throughout the SJ-diode process. This shape indicates that the sidewalls of
the pn-junction are free from laterally swelling geometries, which should appear after
excessive annealing. The ion scattering at the window edges is thought to play a crucialrole in forming flat and abrupt pn-junctions, which are favorable characteristics to
reduce the RONA.

Fig. 3-16. SCM image of SJ-diode with cell pitch of 3.0 m. [10] © 2004 IEEE.

72

Experimental results of device performance
Fabricated 3.0-m pitch SJ-UMOSFET with split p–column structures using themultiple-ion-implantations method was evaluated. The p–columns were arranged
symmetrically in trench gate patterns. The maximum energy of the implantation energy
was set at 1.5 MeV and the number of implantations at N = 2. In this fabricated SJUMOSFET, the VB was 68.8 V.
A. Repetitive inductive switching properties
To investigate the avalanche robustness of the SJ-UMOSFET, it was examined how
the device properties are affected by repetitive avalanche stress, where pulsed avalanche
currents are repetitively forced to flow in the device under controlled maximum channel
temperatures. The repetitive avalanche test was performed by packaged device. The
maximum channel temperature was set at 175°C, and avalanche current at 25 A, by
adjusting the pulse width and frequency calculated from the measured thermal
resistance values. The inductance load was 10 H.
Fig. 3-17(a) shows the VB and the VTH as a function of stress duration time up to 168
hours. In this test, any change in both properties was not observed. To check theavalanche damage more sensitively, capacitance–voltage (C–V) curve shifts of the gate
oxide after the avalanche current stress were examined. The C–V measurements at 100
kHz were performed for the devices with a biased gate and with a grounded source anddrain. As shown in Fig. 3-17(b), no C–V curve shifts after the 168 hours stress wasobserved. This means that the avalanche current did not cause any charges in the gate
oxide.
These results support that the present SJ-UMOSFET has strong immunity against
repetitive inductive switching, because of preferential avalanche current path throughthe p–columns.

73

(a)

(b)

Fig. 3-17. (a) Time dependence of the VB and the VTH, after the repetitive avalanchestress. (b) C–V curves before and after the repetitive avalanche stress, for 168 hours at
175°C. [64] © 2005 IEEE (modified).

B. Reverse recovery properties
Modification of the p–column structure would possibly change the body diodeproperties. To investigate such effects, reverse recovery properties of the body diode forthree kinds of SJ-UMOSFETs corresponding to N = 4, 2, and 1 were measured. The VBof the devices with N = 4, 2, and 1 were 77.4 V, 68.8 V, and 55.4 V, respectively. Fig.
3-18(a) shows the time dependence of the reverse current under the condition of di/dt at
100 A/s. For all curves, slight current enhancement takes place with onset point ataround 20 ns. Since the reverse voltage starts to increase at this onset point, the excess
current component is attributed to the depletion charge. The maximum reverse voltage
is in the small voltage range (~1.5 V), the relevant change is originated from thedepletion region along the pn-junction.
In Fig. 3-18(b), the calculated reverse recovery time (trr) and reverse recovery charge(Qrr) were compared for N = 4, 2, and 1. No significant difference among the samples wasobserved. This means that the split p–column structure brings no harmful effects on thereverse recovery properties.

74

(a)

(b)

Fig. 3-18. (a) Time dependence of the reverse current of body diode under the conditionof di/dt at 100 A/s, and (b) reverse recovery time and reverse recovery charge of body
diode, for SJ-UMOSFETs fabricated with N = 4, 2, and 1 [64] © 2005 IEEE (modified).

C. On-resistance
The tradeoff relationship between the VB and the RONA is shown in Fig. 3-19. By
optimizing the SJ-UMOSFET design with N = 2, the performance was improved byapproximately 25% compared with that with N = 4. The best performance with RONA of
28.7 m·mm2 at Vgs of 10 V for VB of 68.0 V for the split p–column structure.
The best performances obtained from the simulation for various epi-layer designs
were also plotted in Fig. 3-19. These data strongly suggests that the proposed split p–column structure is quite effective to achieve high performance of 40–80-V-rated LVMOSFETs.

75

Fig. 3-19. Tradeoff between VB and RONA for 3.0-m pitch SJ-UMOSFETs. The
measured best performance shows RONA = 28.7 m·mm2 and VB = 68.0 V. [64] © 2004
IEEE (modified).

76Validation of on-resistance modelFig. 3-20 shows the RONA of developed 60-V-class SJ-UMOSFET compared with thatof both analytical model (Eqs. (3-11)–(3-22)) and TCAD simulation. The structuralparameters, electrical parameters and physical constants are indicated in Table 3-3,
Table 3-4 and Table 2-4. In the case of stripe cell that has both continuous channel andcontinuous p–column in longer direction of trench, the RONA at Vgs = 10 V calculated by
the model is 31.7 m·mm2, which corresponds to TCAD result of 31.6 m·mm2 very well.
In this developed SJ-UMOSFET structure, Eq. (3-18) is amended to Eq. (3-23) because
current flow at the top of n–column layer is assumed full expansion rather than 45
degrees.
𝑅𝐷1_𝑃 A =𝜌𝐷 𝑊𝐶𝑒𝑙𝑙(𝑇 − 𝐿𝐴 )𝑊𝑁 − 𝑊𝐷𝑒𝑝_𝑁 𝑆𝐽(3-23)

Moreover, actual developed SJ-UMOSFET has the square cell geometry, as shownin Fig. 3-6(a). In the case of square cell, the RONA at Vgs = 10 V calculated by the modelis 29.6 m·mm2, which corresponds to the experimental result of 28.7 m·mm2, with
only 3.1% error.

Fig. 3-20. Experimental results of RONA for developed 60-V-class SJ-UMOSFET
compared with that of both analytical model and TCAD simulation. Under the conditionof Vgs = 10 V.
77

Table 3-3. Structural parameters of 60-V-class SJ-UMOSFET to calculate RONA.
Symbol

WCell
WT
WMesa
DT
LCH
LA
KA
TGOX
XJS
XJB
WP
WN
TSJ
TBUF
D
ND
NA
TSUB
SUB
NSUB

Parameters

Numerics

Unit

Cell width

3.00

m

Trench width

0.50

m

Mesa width

2.50

m

Trench depth

1.00

m

Channel length

0.40

m

Accumulation length

0.35

m

Coefficient of current spreading in
the accumulation region
Gate oxide thickness

0.70



0.05

m

n+–Source junction depth

0.20

m

p–Base junction depth

0.60

m

p–Column width

1.00

m

n–Column width

2.00

m

p–Column layer thickness

1.90

m

n–Buffer thickness

1.50

m

0.50
1.04 × 1016
1.60 × 1016

•cm
atoms/cm3
atoms/cm3200

m

0.0016
4.32 × 1019

•cm
atoms/cm3

Resistivity of n–Drift layer
Drift layer concentration
p–Column layer concentration
n+–Substrate thickness
Resistivity of n+–substraten+–Substrate concentration

Table 3-4. Electrical parameters of 60-V-class SJ-UMOSFET to calculate RONA.
Symbol

Vgs
VTH
ni
na
n_D
n_SUB
Vbi
VON

Parameters
Gate–source voltage
Threshold voltage
Electron mobility of inversion layer

Numerics
10
3.05
500

Unit
V
V
cm2/VsElectron mobility of accumulation
layerElectron mobility of n–drift layer

550

cm2/Vs1000

cm2/VsElectron mobility of n+–substrate

76.6

cm2/VsBuilt-in potential between p–
column and n–column
On-state voltage

0.70

V

0.10

V

78

Field-plate MOSFET (FP-MOSFET) approaching ultimate structure
The FP-MOSFET has the field plate inside the trench and the field plate isconnected to the gate or the source electrode. They are distinguished to gate field-plate(GFP) structure and source field-plate (SFP) structure, respectively, as needed. In theoff-state, an electric field in the drift region between trenches is reduced by the fieldplate effect through a thick oxide. Therefore, despite the higher doping concentration of
the drift layer than that in the D-MOSFET, high VB and low RONA can be obtained at thesame time. Among the LV-MOSFETs' rated-voltage, 60–150 V FP-MOSFETs, which
could obtain relatively large effect, were reported in early development stage [8] [50] [49][51] [17], subsequently the applied devices were expanded to lower rated-voltage [52].
On the other hand, the process technology to realize the device structure is more
complex than not only the U-MOSFET but also the SJ-UMOSFET. Thus, a uniform thickoxide which separates the field-plate and the mesa region is applied as standard
structure. However, as one of the advanced FP-MOSFET, a slant field-plate structure
has been devised and its superior RONA–VB characteristics were reported as simulation
results [65] [66] [67] [68]. In the slant field-plate structure having a gradient thick oxide,
the electric field of the mesa region is distributed more uniformly in the vertical direction,and the structure can achieve high MOSFET performance.
Basic structure and on-resistance (RONA) components of FP-MOSFET
Schematic cross-sectional structure of FP-MOSFET for two unit-cells area is shownin Fig. 3-21(a) shows a distribution of electric field Ey of drift layer in vertical directiony, when reverse bias applies to drain. In an ideal FP-MOSFET, the Ey is distributed likea trapezoid and a critical electric field EC is nearly uniform, which are the almost sameas those of the SJ-UMOSFET.
Since VB of two-dimensional is determined by the area of this electric field, the VB
of FP-MOSFET is approximated as
𝐿𝑑𝑒𝑝

𝑉𝐵 ≈ ∫

𝐸𝐶 𝑑𝑦.

(3-24)

0

Here Ldep is the depletion layer length in the depth y direction. In assumption, if thedepletion layer length in the p–base region is negligible, the VB of FP-MOSFET isapproximated as

79

(a)

(b)

Fig. 3-21. Schematic cross-sectional structures of FP-MOSFET, which shows two unitcells area. (a) Electric field distribution in vertical direction of off-state. (b) On-state
current paths and components of on-resistance.
1
𝑉𝐵 ≈ 𝐸𝐶 (𝐿𝐷 − 𝑇𝐵𝑈𝐹 ) + 𝐸𝐶 𝑇𝐵𝑈𝐹 ,2(3-25)

where LD is the n–drift layer length and TBUF is the buffer layer thickness under the
trench, which shares a part of the VB. The VB of FP-MOSFET is independent from ND insame manner to the SJ-MOSFET. The VB and the RDA has a nearly linear relationshipthat is described as RDA ∝ VB1.1 in [60].
Fig. 3-21(b) shows on-state current paths and on-resistance components of the FPMOSFET. The RN+A is negligible as like that of the U-MOSFET or the SJ-UMOSFET.
The RONA of FP-MOSFET (RONFPMOSA) can be approximated by using main components,
𝑅𝑂𝑁 𝐹𝑃𝑀𝑂𝑆 A ≈ 𝑅𝐶𝐻 𝐴 + 𝑅𝐴 𝐴 + 𝑅𝐷 𝐴 + 𝑅𝑆𝑈𝐵 𝐴.

(3-26)

Fundamentally, the FP-MOSFETs are classified to two different types: gate fieldplate (GFP) structure [8] [50] [49] [51] [17], as shown in Fig. 3-22(a), and source fieldplate (SFP) structure [52] [69] [70] [71], as shown in Fig. 3-22(b). In the GFP-MOSFET,
the field plate is being continuous to the gate electrode as one body, so that the GFPMOSFET has lower RONA due to an accumulation channel effect along the trench
80sidewall in the mesa region. However, higher gate–drain capacitance (Cgd) is one of thedisadvantage. On the other hand, in the SFP-MOSFET, the field plate is separated fromthe gate electrode and connected to the source electrode in the device termination region.
Thus, the gate electrode inside the trench is shielded from the drain region by thegrounded field-plate. Therefore, the SFP-MOSFET has very small Cgd, however, the

RONA is slightly higher than that of the GFP-MOSFET.

(a)

(b)

(c)

(d)

Fig. 3-22. Classification of FP-MOSFETs. (a) GFP-MOSFET with flat field-plate, (b)SFP-MOSFET with flat field-plate, (c) GFP-MOSFET with slant field-plate, and (d)SFP-MOSFET with slant field-plate.

Fig. 3-23 shows structural parameters of SFP-MOSFET. Each of the resistances
included in Eq. (3-26) is expressed by analytical model as below.
𝑅𝐶𝐻 𝐴 =𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙
2𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )(3-27)𝐿𝐴 𝑊𝐶𝑒𝑙𝑙
2𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠(3-28)𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵

(3-29)𝑅𝐴 𝐴 =

81

(a)

(b)

Fig. 3-23. Structural parameters of SFP-MOSFET (a) with flat field-plate and (b) withslant field-plate.

Here, WCell is the unit cell width and other same symbols are the same as those of
subsection 2.2.1, i.e., LCH is the channel length, LA is the accumulation length, SUB is
the resistivity of n+–substrate, TSUB is the thickness of the n+–substrate, ni is theelectron mobility of inversion layer, na is the electron mobility of accumulation layer,

CGOX is the gate oxide capacitance, Vgs is the gate voltage, and VTH is the thresholdvoltage.
In addition, RDA in Eq. (3-26) consists of different components depending on thefield-plate structure, as shown in Fig. 3-24(a)–(c), RDA is expressed by analytical model
as below.
𝑅𝐷1 𝐴 ∙ 𝑅𝐴_𝐹𝑃 𝐴+ 𝑅𝐷2 𝐴,in GFP − MOSFET
𝑅𝐷 𝐴 = {𝑅𝐷1 𝐴 + 𝑅𝐴_𝐹𝑃 𝐴
𝑅𝐷1 𝐴 + 𝑅𝐷2 𝐴,
in SFP − MOSFET(3-30)

𝑊𝑇
𝑊𝐶𝑒𝑙𝑙 (𝐿𝐷 − 𝐿𝐴 − 𝑇𝐹𝑃𝑂𝑋 ) + 𝐾𝐴 (𝑇𝐹𝑃𝑂𝑋 + 2 )𝑅𝐴_𝐹𝑃 A =∙2
𝜇𝑛𝑎 𝐶𝐹𝑃𝑂𝑋 𝑉𝑔𝑠(3-31)

82

𝑅𝐷1 A =𝑊𝐶𝑒𝑙𝑙
𝜌 (𝐿 − 𝐿𝐴 )𝑊𝑀𝑒𝑠𝑎 𝐷 𝐷

(3-32)

𝜌𝐷 𝑇𝐵𝑈𝐹 ,in GFP − MOSFET
𝑊𝐶𝑒𝑙𝑙
𝑊𝐶𝑒𝑙𝑙
𝑊𝑇
𝑊𝑇
𝜌𝐷 ln
+ 𝜌𝐷 (𝑇𝐵𝑈𝐹 −) , 𝑇𝐵𝑈𝐹 ≥, in SFP − MOSFET
2
𝑊𝑀𝑒𝑠𝑎
2
2
𝑅𝐷2 𝐴 =
𝑊𝐶𝑒𝑙𝑙
𝑊𝑀𝑒𝑠𝑎 + 𝑇𝐵𝑈𝐹
𝑊𝑇𝜌𝐷 ln
, 0 < 𝑇𝐵𝑈𝐹 <,in SFP − MOSFET
{{ 2
𝑊𝑀𝑒𝑠𝑎
2

(3-33)

Here, RD1A is the drift layer resistances in the mesa region, RD2A is the drift layer
resistances in the buffer layer, and RA_FPA are the accumulation resistance along thefield plate. It is noted that the accumulation layer of the GFP-MOSFET is divided into
three portions: along the gate oxide, along the field plate of the mesa region, and along
the field plate at bottom corner of the trench. KA is a coefficient of considering current
spreading from the accumulation region to the drift region [25] [26]. In Eq. (3-31), thetotal accumulation length of the unit cell is given by 2𝑇𝐹𝑃𝑂𝑋 + 𝑊𝑇 . KA is assumed to bearound 0.6. In addition, D is the resistivity of n–drift layer and CFPOX is the field-plate
oxide capacitance. CFPOX is calculated by using TFPOX, which is the thickness of the fieldplate oxide, and given by

(a)

(b)

(c)

Fig. 3-24. (a) Top view of FP-MOSFET for stripe cell layout. Schematic cross-sectional
structure, which shows components of the accumulation layer and n–drift layer
resistance (RA, RA_FP, RD1 and RD2), for (b) GFP-MOSFET and (c) SFP-MOSFET withflat field-plate. Current flow spreading along the field plate in the mesa region and thebuffer layer is showing.
83

𝐶𝐹𝑃𝑂𝑋 =𝜀𝑂𝑋 𝜀0.
𝑇𝐹𝑃𝑂𝑋(3-34)In the GFP-MOSFET, the first term of Eq. (3-30) is parallel resistance of RD1A and

RA_FPA, thus the RDA can be reduced by the accumulation effect. Moreover, as the RD2A
region, the current flows in whole buffer layer because the accumulation layer of thetrench bottom helps it, as shown in Fig. 3-24(b). On the other hand, in the SFP-MOSFET,
the RDA is simply expressed as series resistance of RD1A and RD2A in Eq. (3-30). However,in the RD2A region, the current flow is spreading in 45 degrees from the bottom of themesa region, as shown in Fig. 3-24(c). Therefore, the RDA of the SFP-MOSFET showsslightly disadvantage compared with that of the GFP-MOSFET.
As another classification of the FP-MOSFETs, there are two different field-plate
shapes: flat field-plate structure described the above, as shown in Fig. 3-22(a)–(b), andslant field-plate structure [65] [66] [67] [68] [72], as shown in Fig. 3-22(c)–(d). In theslant field-plate structure, thick oxide between the mesa region and the field plate has aslope and the thickness increases gradually toward the trench bottom. The ideal FPMOSFET, which has nearly uniform electric field distribution in the mesa region asshown in Fig. 3-21, is achieved by the slant field-plate structure rather than the flat
field-plate structure [72].
In the slant field-plate structure, the current flow spreading in the accumulation
layer and the n–drift layer is the same as that of the flat field-plate structure, as shownin Fig. 3-25(a)–(c). However, in the case of the slant GFP-MOSFET, the accumulation
effect along the field plate varies by the field-plate depth. Therefore, the first term in Eq.
(3-31) is expressed as
𝑅𝐴_𝐹𝑃(1) A =𝐿𝐷 −𝐿𝐴 −𝑇𝐹𝑃𝑂𝑋_𝑏
𝑊𝐶𝑒𝑙𝑙
1
1
∙
∙∫
𝑑𝑦.
2
𝜇𝑛𝑎 𝑉𝑔𝑠 0
𝐶𝐹𝑃𝑂𝑋 (𝑦)(3-35)

Here TFPOX_b is thickness of the field-plate oxide at bottom position. The field-plate oxide
capacitance depending the depth CFPOX(y) is expressed by using TFPOX(y), which is
thickness of the field-plate oxide depending the depth.
𝐶𝐹𝑃𝑂𝑋 (y) =𝜀𝑂𝑋 𝜀0.
𝑇𝐹𝑃𝑂𝑋 (𝑦)The TFPOX(y) is given by84(3-36)

(a)

(b)

(c)

Fig. 3-25. (a) Top view of FP-MOSFET for stripe cell layout. Schematic cross-sectional
structure, which shows components of the accumulation layer and n–drift layer
resistance (RA, RA_FP, RD1 and RD2), for (b) GFP-MOSFET and (c) SFP-MOSFET withslant field-plate. Current flow spreading along the field plate in the mesa region andthe buffer layer is showing.

𝑇𝐹𝑃𝑂𝑋 (y) = y ∙𝑇𝐹𝑃𝑂𝑋_𝑏 − 𝑇𝐹𝑃𝑂𝑋_𝑡+ 𝑇𝐹𝑃𝑂𝑋_𝑡 .
𝐿𝐷 − 𝐿𝐴(3-37)

where TFPOX_t is thickness of the field-plate oxide at top position. By substituting Eqs. (336)–(3-37) into Eq. (3-35), the following is obtained.
𝑅𝐴_𝐹𝑃(1) A =𝑊𝐶𝑒𝑙𝑙(𝐿𝐷 − 𝐿𝐴 − 𝑇𝐹𝑃𝑂𝑋_𝑏 )(𝑇𝐹𝑃𝑂𝑋_𝑏 + 𝑇𝐹𝑃𝑂𝑋_𝑡 )∙2𝜇𝑛𝑎 𝜀𝑂𝑋 𝜀0 𝑉𝑔𝑠
2(3-38)

Therefore, in the slant GFP-MOSFET, RA_FPA in Eq. (3-31) has to be amended model as
below.
𝑅𝐴_𝐹𝑃 A =𝑊𝐶𝑒𝑙𝑙
(𝐿𝐷 − 𝐿𝐴 − 𝑇𝐹𝑃𝑂𝑋_𝑏 )(𝑇𝐹𝑃𝑂𝑋_𝑏 + 𝑇𝐹𝑃𝑂𝑋_𝑡 )[2𝜇𝑛𝑎 𝜀𝑂𝑋 𝜀0 𝑉𝑔𝑠
2
𝑊𝑇+ 𝐾𝐴 (𝑇𝐹𝑃𝑂𝑋_𝑏 +) 𝑇𝐹𝑃𝑂𝑋_𝑏 ]2(3-39)

To improve the RONFPMOSA with necessary VB maintained, all the components of

RONFPMOSA have to be reduced by individual appropriate techniques.
85

List of on-resistance model

Table 3-5. List of RONA model equations for GFP-MOSFET and SFP-MOSFET with flat
field-plate (stripe cell design).
Flat GFP-MOSFET, stripe
𝑅𝐶𝐻 A =

Flat SFP-MOSFET, stripe

𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙

𝑅𝐶𝐻 A =

2𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )𝑅𝐴 A =𝐿𝐴 𝑊𝐶𝑒𝑙𝑙
2𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠

𝑅𝐷 A =𝑅𝐷1 𝐴 ∙ 𝑅𝐴_𝐹𝑃 𝐴+ 𝑅𝐷2 𝐴
𝑅𝐷1 𝐴 + 𝑅𝐴_𝐹𝑃 𝐴

𝑅𝐷1_𝑃 A =𝑅𝐴 A =

2𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )𝐿𝐴 𝑊𝐶𝑒𝑙𝑙
2𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠

𝑅𝐷 A = 𝑅𝐷1 𝐴 + 𝑅𝐷2 𝐴
𝑅𝐷1 A =𝑊𝐶𝑒𝑙𝑙
𝜌 (𝐿 − 𝐿𝐴 )𝑊𝑀𝑒𝑠𝑎 𝐷 𝐷

𝑊𝐶𝑒𝑙𝑙
𝜌 (𝐿 − 𝐿𝐴 )𝑊𝑀𝑒𝑠𝑎 𝐷 𝐷

𝑊𝐶𝑒𝑙𝑙
𝑊𝐶𝑒𝑙𝑙
𝑊𝑇
𝜌𝐷 ln
+ 𝜌𝐷 (𝑇𝐵𝑈𝐹 −
)
2
𝑊𝑀𝑒𝑠𝑎
2
𝑊𝑇
, 𝑇𝐵𝑈𝐹 ≥2
𝑅𝐷2 A =
𝑊𝐶𝑒𝑙𝑙
𝑊𝑀𝑒𝑠𝑎 + 𝑇𝐵𝑈𝐹
𝜌𝐷 ln
2
𝑊𝑀𝑒𝑠𝑎
𝑊𝑇
, 0 < 𝑇𝐵𝑈𝐹 <{2

𝑅𝐷2_𝑃 A = 𝜌𝐷 𝑇𝐵𝑈𝐹
𝑅𝐴_𝐹𝑃 A=

𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙

𝑊𝑇
𝑊𝐶𝑒𝑙𝑙 (𝐿𝐷 − 𝐿𝐴 − 𝑇𝐹𝑃𝑂𝑋 ) + 𝐾𝐴 (𝑇𝐹𝑃𝑂𝑋 + 2 )∙2
𝜇𝑛𝑎 𝐶𝐹𝑃𝑂𝑋 𝑉𝑔𝑠

𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵

𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵

86

Table 3-6. List of RONA model equations for GFP-MOSFET and SFP-MOSFET with slant
field-plate (stripe cell design).
Slant GFP-MOSFET, stripe
𝑅𝐶𝐻 A =

Slant SFP-MOSFET, stripe

𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙

𝑅𝐶𝐻 A =

2𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )𝑅𝐴 A =𝐿𝐴 𝑊𝐶𝑒𝑙𝑙
2𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠

𝑅𝐷 A =𝑅𝐷1 𝐴 ∙ 𝑅𝐴_𝐹𝑃 𝐴+ 𝑅𝐷2 𝐴
𝑅𝐷1 𝐴 + 𝑅𝐴_𝐹𝑃 𝐴

𝑅𝐴 A =𝐿𝐶𝐻 𝑊𝐶𝑒𝑙𝑙
2𝜇𝑛𝑖 𝐶𝐺𝑂𝑋 (𝑉𝑔𝑠 − 𝑉𝑇𝐻 )𝐿𝐴 𝑊𝐶𝑒𝑙𝑙
2𝜇𝑛𝑎 𝐶𝐺𝑂𝑋 𝑉𝑔𝑠

𝑅𝐷 A = 𝑅𝐷1 𝐴 + 𝑅𝐷2 𝐴
𝑅𝐷1 A =𝑊𝐶𝑒𝑙𝑙
𝑅𝐷1_𝑃 A =
𝜌 (𝐿 − 𝐿𝐴 )𝑊𝑀𝑒𝑠𝑎 𝐷 𝐷

𝑊𝐶𝑒𝑙𝑙
𝜌 (𝐿 − 𝐿𝐴 )𝑊𝑀𝑒𝑠𝑎 𝐷 𝐷

𝑊𝐶𝑒𝑙𝑙
𝑊𝐶𝑒𝑙𝑙
𝑊𝑇
𝜌𝐷 ln
+ 𝜌𝐷 (𝑇𝐵𝑈𝐹 −
)
2
𝑊𝑀𝑒𝑠𝑎
2
𝑊𝑇
, 𝑇𝐵𝑈𝐹 ≥2
𝑅𝐷2 A =
𝑊𝐶𝑒𝑙𝑙
𝑊𝑀𝑒𝑠𝑎 + 𝑇𝐵𝑈𝐹
𝜌𝐷 ln
2
𝑊𝑀𝑒𝑠𝑎
𝑊𝑇
, 𝑇𝐵𝑈𝐹 <{2

𝑅𝐷2_𝑃 A = 𝜌𝐷 𝑇𝐵𝑈𝐹

𝑅𝐴_𝐹𝑃 A
𝑊𝐶𝑒𝑙𝑙
(𝐿𝐷 − 𝐿𝐴 − 𝑇𝐹𝑃𝑂𝑋_𝑏 )(𝑇𝐹𝑃𝑂𝑋_𝑏 + 𝑇𝐹𝑃𝑂𝑋_𝑡 )=[2𝜇𝑛𝑎 𝜀𝑂𝑋 𝜀0 𝑉𝑔𝑠
2
𝑊𝑇+ 𝐾𝐴 (𝑇𝐹𝑃𝑂𝑋_𝑏 +) 𝑇𝐹𝑃𝑂𝑋_𝑏 ]2

𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵

𝑅𝑆𝑈𝐵 A = 𝜌𝑆𝑈𝐵 𝑇𝑆𝑈𝐵87

100-V multiple-stepped-oxide GFP-MOSFET 3
Applying the FP-MOSFET is expanding to improve the performances in wide range
LV-MOSFETs products this decade. As described above, the slant FP-MOSFET which
has an ideal field-plate structure has been devised, however, the real device and theelectrical characteristics were not reported so far, because of difficulty of the fabrication
process. As one of the approach to realize the slant FP-MOSFET, a multiple steppedoxide FP-MOSFET (MSO-FP-MOSFET), which is extremely close to ideal gradient oxide
structure, is proposed [72] [73].
In the following, firstly, 100-V-class device structure design is described. Then,
optimization of each design parameter by TCAD simulation is discussed. Moreover,realizable fabrication process flow and experimental results of the device are described.
Unit-cell structure design
Fig. 3-26(a)–(c) show schematic cross-sectional structures of conventional FPMOSFET with uniform thick oxide, ideal slant FP-MOSFET with gradient oxide, andproposed MSO-FP-MOSFET. The MSO-FP-MOSFET structure has multiple small
stepped oxide film and stepped single domain polycrystalline-silicon field-plate in the
trench (Fig. 3-26(c)).
The basic design parameter to achieve VB of over 100 V is described below. In an
ideal FP-MOSFET, the electric field distribution of the mesa region is expected to beuniform in vertical direction in order to maximize the VB, as shown in Fig. 3-21(a).
However, it is difficult to realize completely uniform electric field distribution because apeak of the electric field appears at pn-junction or trench bottom region. Therefore, theVB in Eq. (3-24) is expressed as
𝑉𝐵 = 𝐸𝐶 𝐿𝐷 𝛽,(3-40)

where  is a field coefficient (0 <  < 1) [66]. The EC is gradually varied by the necessary

VB, and it becomes higher in lower voltage [11].
𝐸𝐶 = 8.2 × 105 ∙ 𝑉𝐵 −0.2 (𝑉/𝑐𝑚)

3(3-41)

Subsection 3.3.3 is reconstruction of [72] chapter II–IV, © 2015 IEEE, and [73] chapter 2–5. A part ofdescription is modified and comprehensive explanations are additionally provided. Eqs. (2)–(4) of [72]and Eqs. (3)–(5) of [73] are modified to take account of the mesa region against both sides’ field-plates.

88

(a)

(b)

(c)

Fig. 3-26. Schematic cross-sectional structures of (a) conventional FP-MOSFET withuniform thick oxide, (b) ideal slant FP-MOSFET with gradient oxide, and (c) proposed
multiple-stepped-oxide (MSO) FP-MOSFET. [72] © 2015 IEEE (modified), [73].
The EC is estimated at 3.20×105 V/cm to obtain 110 V, which is added 10% margin to therated-voltage. When  is assumed to 0.75, necessary LD is calculated as
𝐿𝐷 =𝑉𝐵= 4.58 × 10−4 (𝑐𝑚) = 4.58 (𝜇𝑚).
𝐸𝐶 𝛽(3-42)

An optimum charge density QOpt in the mesa region against both sides’ field-plates islead from Poisson's equation [11] [59] [72] [74]. Applying the above EC, the QOpt is given
by
𝑄𝑂𝑝𝑡 =

2𝐸𝐶 𝜀𝑆𝑖 𝜀0= 4.15 × 1012 (𝑎𝑡𝑜𝑚𝑠/𝑐𝑚2 ).
𝑞(3-43)

Then, when the WMesa is assumed to 1.2 m, the ND is calculated as
𝑁𝐷 =

𝑄𝑂𝑝𝑡
4.15 × 1012=
= 3.46 × 1016 (𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3 ).
𝑊𝑀𝑒𝑠𝑎
1.2 × 10−4

(3-44)

As basic design of the MSO-FP-MOSFET, the trench depth is determined to 5.5 m whichis added a fabrication process margin to the calculated LD (4.58 m), whereas the cell
pitch is determined to 3.0 m in consideration of the WMesa and necessary field-plate
oxide thickness inside the trench.
89

Validation and optimization of design parameters by TCAD simulation
A. Validation of electric potential and electric field distribution
Behavior of the field-plate effect for both conventional FP-MOSFET and MSO-FPMOSFET is compared by TCAD simulation. In both MOSFETs, the design parameters,
as shown in Fig. 3-23 and Fig. 3-25, are basically same. The field-plate oxide thickness
at top position (TFPOX_t) and at bottom position (TFPOX_b) are considered as design
parameter optimization. In Fig. 3-26, it is noted that the symbols TFPOX_t and TFPOX_b are
expressed as tOX,t and tOX,b.
When a high reverse bias is applied to drain–source, a depletion layer expands
vertically in the mesa region. Fig. 3-27(a)–(i) show two-dimensional (2-D) potential
contours and one-dimensional (1-D) electric field distributions at the VB under thecondition of three different ND, in both conventional FP-MOSFET and MSO-FPMOSFET.
For low ND condition (1.0×1016 /cm3), in both structures, the potential lines are dense
at bottom of the trench and sparse at upper region of the mesa (Fig. 3-27(a)–(c)). Thus,
the field-plate effect is not enough for the mesa region and the VB is restricted by thepunch-through phenomenon.
For medium ND condition (2.0×1016 /cm3), the potential lines are distributed more
uniformly compared with the low ND case, therefore the VB increases in both structures(Fig. 3-27(d)–(f)).

Fig. 3-27. 2-D potential contours at 5-V intervals and 1-D vertical electric field
distributions along the trench sidewall. ND dependence of the potential: (a), (d), and(g) for conventional FP-MOSFETs; and (b), (e), and (h) for MSO-FP-MOSFETs.
(c), (f), and (i): ND dependence of the electric field for conventional FP-MOSFETs (reddashed lines) and MSO-FP-MOSFETs (blue solid lines). [72] © 2015 IEEE, [73].
90For high ND condition (3.0×1016 /cm3), the VB decreases in the conventional structure
because the depletion layer no longer expands enough (Fig. 3-27(g)–(i)). On the other
hand, in the MSO-FP-MOSFET, the two peaks of the electric field are nearly equal, andfairly uniform electric field distribution in the vertical direction can be seen. This effectis explained below. The potential lines in the stepped oxide region are distribute laterallywith relatively uniform and high density from the bottom to the top, compared with theconventional thick oxide case. Therefore, the potential lines in the mesa region also
distribute vertically with approximately equal intervals. In this validated condition, the

VB of 114.8 V can be achieved at 1.5 times higher ND than that of the conventional FPMOSFET.
B. Optimization of design parameters
In the FP-MOSFETs shown in Fig. 3-26, the field-plate oxide slope K is defined by
𝐾=

𝐿𝐹𝑃
,
𝐿
𝑇𝐹𝑃𝑂𝑋_𝑏 + 𝐹𝑃 − 𝑇𝐹𝑃𝑂𝑋_𝑡tan 𝛼(3-45)

where LFP is the poly-Silicon field-plate length and  is the trench angle. Regarding
significant design parameters (ND, TFPOX_t, TFPOX_b, and K) which make the VB change,
simulation results are described below.
Fig. 3-28 shows the TFPOX_b (tOX,b) dependence of the VB for various ND, which isranged from 1.0×1016 to 3.0×1016 /cm3, for the conventional FP-MOSFETs. A basic
dependence is seen that the thicker TFPOX_b (tOX,b) can rise the VB. On the other hand,when the ND increases, a peak VB decreases.

Fig. 3-28. Simulated TFPOX_b (tOX,b) dependence of VB for various ND in the case of
conventional FP-MOSFETs. [73] (modified).
91Then, in the MSO-FP-MOSFETs that the TFPOX_b (tOX,b) is fixed to 700 nm, the TFPOX_t(tOX,t) dependence corresponding to varying K (from 5.5 to 15.5) is simulated. In thesimulated conventional FP-MOSFET, K is calculated as 50. As shown in Fig. 3-29,
depending on the K, the ND which obtains the maximum VB is varied. When the K issmaller, the peak VB moves to higher ND side. However, at the same time, the peak VB
decreases in smaller K. Moreover, when the ND exceeds the peak VB, the VB decreases
steeply in larger K.
Thus, by adopting the small K, the field-plate effect to reduce the electric field in themesa region can be achieved, even in the case of the high ND. It can be seen also in Fig.
3-30. In addition, it is possible that the VB margin expands to the higher ND side because
the EC becomes gradually high in the higher ND [60].
K=50 15.5 12 9.5
8.2

7
6.2

K=50

5.5

K=5.5~15.5

K

K
ND

ND

Fig. 3-29. Simulated ND dependence of VB for MSO-FP-MOSFETs (K = 5.5–15.5) andconventional FP-MOSFET (K = 50). [73] (modified).

Fig. 3-30. 2-D simulation results for MSO-FP-MOSFETs (K = 5.5–15.5). Depletion
layer (white lines), potential contours at 5-V intervals (black lines), and electric field
distributions (color) are shown in each half-cell structure.
92

The RONA which is dominant for the drift layer resistance decreases corresponding
to the ND increase, as shown in Fig. 3-31. In addition, thinner TFPOX_t (tOX,t) has anadvantage to reduce RONA because of an increase of the accumulation effect, in particularalong the upper side of the trench.

Fig. 3-31. Simulated ND dependence of RONA for MSO-FP-MOSFETs (K = 5.5–15.5)
and conventional FP-MOSFET (K = 50). [73] (modified).

Based on approximately same VB margin to the rated-voltage (100 V), bothconventional FP-MOSFET and MSO-FP-MSFET has to be compared from the simulation
results. In the conventional FP-MOSFET, the VB is 113.3 V under the conditions of K =50 and ND = 2.0×1016 /cm3, and the RONA becomes 38.2 m·mm2. In the MSO-FPMOSFET, the VB is 111.7 V under the conditions of K = 7 and ND = 3.0×1016 /cm3, andultralow RONA of 29.1 m·mm2 can be achieved. Here, RONA is including 1.0 m·mm2
substrate resistance.
The simulated RONA of the MSO-FP-MOSFET (29.1 m·mm2) indicates 25%
reduction compared to that of the conventional FP-MOSFET (38.2 m·mm2) in the same

VB range.

93

Fig. 3-32. Simulated K dependence of VB process margin over 100 V. And K
dependence of RONA; at ND = 3.0×1016 /cm3 for MSO-FP-MOSFETs and at ND =2.0×1016 /cm3 for conventional FP-MOSFET. Reconstructed from Fig. 3-29 and Fig.
3-31. [73] (modified).

Fig. 3-32 shows the simulated VB process margin and the RONA at the ND with the

VB margin maintained, for the MSO-FP-MOSFETs and the conventional FP-MOSFET.
Those data can read from Fig. 3-29 and Fig. 3-31, and shown as the K dependence. The

VB process margin represents a range that satisfies both VB > 100 V and ND > 3.0×1016/cm3 for the MSO-FP-MOSFETs; or both VB > 100 V and ND > 2.0×1016 /cm3 for theconventional FP-MOSFET.
The VB margin to maintain over 100 V of the conventional FP-MOSFET is 30%. In
the MSO-FP-MOSFET, it is found that the smaller the K, the larger the VB margin.
When the K is 7, 26.7% margin, which is approximately same as the conventional one,is maintained.

94

Fig. 3-33. Simulated ND dependence of VB process margin up to 100 V and RONA for
MSO-FP-MOSFETs and conventional FP-MOSFETs. Reconstructed from Fig. 3-29
and Fig. 3-31. [73] (modified).

Fig. 3-33 shows the simulated VB process margin over 100 V and the RONA, at K = 7
for the MSO-FP-MOSFETs, and at K = 50 for the conventional FP-MOSFET. Those data
can read from Fig. 3-29 and Fig. 3-31, and shown as the ND dependence. The VB process
margin represents a range that satisfies only VB > 100 V for the MSO-FP-MOSFETs; orboth VB > 100 V and ND > 2.0×1016 /cm3 for the conventional FP-MOSFET.
If the higher ND, which means the VB process margin decrease, is permitted, it ispossible to decrease the RONA more. For example, when the margin is 16.9%, VB = 112.9
V and RONA = 27.5 m·mm2 can be obtained, or when the margin is 8.6%, VB = 114.1 V
and RONA = 26.7 m·mm2 can be obtained
As mentioned above, the VB process margin was discussed about the ND, however,
the tolerance of other parameters such as TFPOX_b, TFPOX_t, and WMesa have to beconsidered in real device manufacturing.

95

Process flow and essential process evaluation
To realize the MSO-FP-MOSFET cell structure, two types of the fabrication process
are proposed. They are named Stepped Oxide Deposition (SOD) process and Stepped
Oxide Etch-off (SOE) process, respectively.
Fig. 3-34(a)–(h) shows the SOD process for the case of five-step field-plate structure.
(a) Trench forming by photo-lithography and reactive ion-etching (RIE), followed by firstthin oxide film deposition by chemical vapor deposition (CVD).
(b) Sacrificial layer formation and etching it back down to first depth, followed by the
first oxide film etching(c) Second oxide film deposition and second sacrificial layer formation to second depth,
followed by the second oxide film etching.
(d) Third oxide film deposition and third sacrificial layer formation to third depth,
followed by the third oxide film etching.
(e) Fourth oxide film deposition and fourth sacrificial layer formation to fourth depth,
followed by the fourth oxide film etching.
(f) Fifth oxide film deposition and fifth sacrificial layer formation to fifth depth, followedby the fifth oxide film etching.
(g) The sacrificial layer etching, followed by gate oxidation.
(h) Poly-silicon deposition as gate electrode.

Fig. 3-34. Part of fabrication process flow of MSO-FP-MOSFET, named Stepped Oxide
Deposition (SOD) process. (From trench formation to field-plate formation.) [72] ©
2015 IEEE, [73].

96After the process step (h), followed by p–base / n+–source formation, inter-layer
insulating film deposition, contact hole etching, metallization for source electrode, andback-surface metal formation for drain electrode.
Fig. 3-35(a)–(h) shows the SOE process for the case of five-step field-plate structure.
(a) Trench forming by photo-lithography and reactive ion-etching (RIE), followed by firstthick oxide film deposition by chemical vapor deposition (CVD).
(b) Sacrificial layer formation and etching it back to first depth, followed by the firstoxide film etching(c) The sacrificial layer etching to second depth, followed by second oxide film etchingslightly(d) The sacrificial layer etching to third depth, followed by third oxide film etchingslightly(e) The sacrificial layer etching to fourth depth, followed by fourth oxide film etchingslightly(f) The sacrificial layer etching to fifth depth, followed by fifth oxide film etching slightly(g) The sacrificial layer etching, followed by gate oxidation.
(h) Poly-silicon deposition as gate electrode.
After the process step (h), followed by p–base / n+–source formation, inter-layer
insulating film deposition, contact hole etching, metallization for source electrode, andback-surface metal formation for drain electrode.

Fig. 3-35. Part of fabrication process flow of MSO-FP-MOSFET, named Stepped Oxide
Etch-off (SOE) process. (From trench formation to field-plate formation.) [72] © 2015
IEEE, [73].

97Experimental results of device performanceFig. 3-36 shows cross-sectional SEM photograph of fabricated MSO-FP-MOSFET,
which corresponds to field-plate (gate electrode) formation step of SOE process. It isobserved that smooth four-step oxide and field-plate are formed successfully in 5.5-m
deep trench.

Fig. 3-36. Cross-sectional SEM photograph of fabricated MSO-FP-MOSFET, whichcorresponds to field-plate formation step of SOE process. [72] © 2015 IEEE, [73].

To demonstrate basic characteristics of the MSO-FP-MOSFET for the first time, testelement group (TEG) having a diode and a resistance were fabricated on 3.73-mm2 chip.
As the diode TEG structure, p–base layer and p+–contact layer were formed at top of n–
drift layer of the surface of the mesa region. As the resistance TEG structure, n+–contact
layer were formed at top of n–drift layer of the surface of the mesa region. The polysilicon, which acts as the field-plate, was connected to the source (anode) electrode.
In the evaluation samples, observed TFPOX_t (tOX,t), TFPOX_b (tOX,b) and WMesa were 310
nm, 580 nm and 1.4 m, respectively.
By the diode TEG measurement, maximum VB of 114.8 V was confirmed at
approximately 1.5 times higher ND than that of the conventional flat oxide structure, as
shown in Fig. 3-37(a). However, the diode had a leakage current which wasapproximately five orders of magnitude higher than the simulated FP-MOSFET. This isbecause the device termination design was not optimized in this TEG.
On the other hand, by the resistance TEG measurement, 30% reduction of the oncurrent was confirmed under the condition of 40% higher ND than that of theconventional flat oxide structure, as shown in Fig. 3-37(b). It is noted that there aredifferences between the resistance TEG and the MOSFET simulation; e.g., the TEG
98

includes a packaging resistance, the TEG does not include the channel resistance of the
MOSFET that leads to RON increase, and the TEG does not include the accumulation
effect of the MOSFET that leads to RON decrease.

(a)

(b)

Fig. 3-37. (a) ID–VDS characteristics of the measured diode TEG, in comparison of thesimulated MSO-FP-MOSFET. (b) ID–VDS characteristics of the measured resistivity
TEG. [73]99Validation of on-resistance modelFig. 3-38 shows the RONA of simulated 100-V-class FP-MOSFETs (the conventional
FP-MOSFET and the MSO-FP-MOSFET) compared with those of analytical model (theflat FP-MOSFET and the slant FP-MOSFET) in Eqs. (3-26)–(3-39). The structuralparameters, electrical parameters, and physical constants are indicated in Table 3-7,
Table 3-8, and Table 2-4.
In the case of the conventional/flat FP-MOSFETs, the RONA at Vgs = 10 V calculatedby the model is 37.5 m·mm2, which corresponds to the TCAD result of 37.5 m·mm2
completely. In the case of the slant/MSO-FP-MOSFETs, the RONA at Vgs = 10 V calculatedby the model is 28.2 m·mm2, which corresponds to the TCAD result of 28.4 m·mm2
with less than 1.0% error. It is noted that, in order to adjust to the model, RN+A
component was subtracted from the RONA of the original TCAD results.

Fig. 3-38. RONA of simulated 100-V-class FP-MOSFETs (conventional FP-MOSFET and
MSO-FP-MOSFET) compared with those of analytical model (flat FP-MOSFET andslant FP-MOSFET). Under the condition of Vgs = 10 V.

100

Table 3-7. Structural parameters of 100-V-class FP-MOSFETs to calculate RONA.
Symbol

WCell
WT
WMesa
DT
LCH
LA
KA
TGOX
XJS
XJB
TFPOX
TFPOX_t
TFPOX_b
LD
TBUF
D
ND
TSUB
SUB
NSUB

Flat FPMOSFET

MSO-FPMOSFET

Unit

Cell width

3.00

3.00

m

Trench width

1.80

1.80

m

Mesa width

1.20

1.20

m

Trench depth

5.50

5.50

m

Channel length

0.30

0.30

m

Accumulation length
Coefficient of current spreadingin the accumulation region

0.20

0.20

m

0.60

0.60



Gate oxide thickness

0.075

0.075

m

n+–Source junction depth

0.25

0.25

m

p–Base junction depth

0.55

0.55

m

Field-plate oxide thickness

0.70

N/A

m

N/A

0.25

m

N/A

0.70

m

4.95

4.95

m

Parameters

Field-plate oxide thickness(top)
Field-plate oxide thickness(bottom)n–Drift layer lengthn–Buffer thickness
Resistivity of n–drift layer
Drift layer concentration
n+–Substrate thickness
Resistivity of n+–Substraten+–Substrate concentration

0.90

0.90

m

0.284
2.0 × 1016

0.204
3.0 × 1016

•cm
atoms/cm3

50

50

m

0.00203.43 × 1019

0.00203.43 × 1019

•cm
atoms/cm3

Table 3-8. Electrical parameters of 100-V-class FP-MOSFETs to calculate RONA.
SymbolParameters

Vgs
VTH

Gate–source voltage
Threshold voltage
Electron mobility of inversion
layerElectron mobility ofaccumulation layer
Electron mobility of n–drift
layerElectron mobility of n+–
substrate
On-state voltage

ni
na
n_D
n_SUB
VON

101

Flat FPMOSFET

MSO-FPMOSFET

Unit

10
2.63

10
2.28

V
V

500

500

cm2/Vs550

550

cm2/Vs1000

1000

cm2/Vs

77.6

77.6

cm2/Vs

0.10

0.10

V

100-V two-step-oxide SFP-MOSFET 4
Unit-cell structure design
In subsection 3.3.3, the MSO-FP-MOSFET, which is close to the ideal field-plate
structure, was proposed. However, there is an issue which needs to the complicatedprocess. Thus, in this subsection, a simplified field-plate structure is proposed. In
addition, the source field-plate structure is applied to newly developed device to promise
lower Qgd, as mentioned in subsection 3.3.1 [74].
In Fig. 3-49, three kinds of FP-MOSFET structures are compared. The conventional
FP-MOSFET has uniform field-plate oxide and straight poly-Si field-plate in the trench(Fig. 3-49(a)). This field-plate is connected to the source electrode at the termination
region of the chip. This field-plate structure is standard in current commercial product.
The MSO-FP-MOSFET is constructed by five-step oxide and tapered poly-Si field-plate(Fig. 3-49(b)). As shown in Fig. 3-49(c), proposed two-step FP-MOSFET is formed by two
steps of thick oxide and two steps of field-plate poly-silicon to simplify the structure andfabrication process.

(a)

(b)

(c)

Fig. 3-39. Schematic cross-sectional structures of (a) conventional FP-MOSFET withuniform thick oxide, (b) multiple-stepped-oxide (MSO) FP-MOSFET, and (c) proposed
2-step FP-MOSFET. [74] (c) 2019 IEEE.
4 Subsection 3.3.5 is reproduction of [74] chapter II–V, © 2019 IEEE, and a part of description ismodified and comprehensive explanations are additionally provided.

102

Optimization of design parameters by TCAD simulation
As initial study for the three structures, off-state potential and electric field
distribution are simulated. As design parameters, WCell = 3 m, DT = 5.5 m, and ND =1×1016 – 3×1016 /cm3 are chosen. Basically, the field plate inside the trench has effect torelax electric field in mesa region. Under the lower ND condition (1×1016 /cm3),
approximately 100-V VB is obtained for all three structures. However, Under the higher

ND condition (3×1016 /cm3), as shown in Fig. 3-40, the VB goes down to 52 V for theconventional FP-MOSFET because of high electric field at upper mesa region.
In contrary, both MSO and 2-step FP-MOSFETs realize over 110 V at the high ND
condition. Especially in the 2-step FP-MOSFET, it seems that the equipotential lines areapproximately equal intervals. Also, the electric field is closer to uniform distribution. In
a detail observation of the distribution, an inflection point at the oxide step position canbe seen. As a result, it is found that the ND can be designed to 1.5 times higher thanconventional FP-MOSFET, which is the same effect as the MSO-FP-MOSFET as
described in subsection 3.3.3.2.

Fig. 3-40. Simulated 2-D potential contours (black lines), for (a) conventional, (b)MSO, and (c) 2-step FP-MOSFETs. (d) 1-D vertical electric field distributions along
trench sidewall for conventional FP-MOSFETs (red dotted line), MSO-FP-MOSFETs(green dashed line), and 2-step FP-MOSFET (blue solid line). Under the condition of

ND = 3.0×1016 /cm3. [74] (c) 2019 IEEE.

The field-plate oxide thickness at top position (TFPOX_t) and at bottom position(TFPOX_b) are considered as design parameter optimization. In Fig. 3-39, it is noted thatthe symbols TFPOX_t and TFPOX_b are expressed as tOX,t and tOX,b. The field-plate oxide slope

K is defined by Eq. (3-45). When the ND, which can obtain a peak VB (VB,peak), is around103

3.5×1016 – 3.75×1016 /cm3, minimum RONA can achieve at K = 8–9.7 in the 2-step FPMOSFET.
Fig. 3-41 shows WMesa dependences of the VB,peak and “ND at VB,peak” for K = 9.2. The“ND at VB,peak” increases by decreasing WMesa. This is because an optimum charge isdefined by the product of the ND and the WMesa, as shown in Eq. (3-43). On the other
hand, by increasing the WMesa, the VB increases slightly. From these results, considering
to easiness of fabrication process, the WMesa is selected to 1 m, in following experiment.

Fig. 3-41. Simulated WMesa dependences of VB,peak and “ND at VB,peak” for 2-step FPMOSFETs. (tOX,b = 600 nm, K = 9.2). [74] © 2019 IEEE (modified).

Process flow and fabricated device structure
Representative process steps for the 2-step FP-MOSFET are shown in Fig. 3-42. (a)The trench of around 5.5-m depth is formed by reactive ion etching (RIE), and followedby first thick oxidation. (b) By using sacrificial layer inside the trench, the thick oxide isetched down to approximately half-depth of the trench, and followed by second thickoxidation. (c) Polysilicon field-plate is formed by chemical vapor deposition (CVD) and
RIE. (d) First interlayer oxide is filled in the trench by CVD and etched back toappropriate depth. (e) Gate oxidation and gate poly-silicon CVD are performed
continuously. (f) The gate poly-silicon is etched. After that, following process steps such
as p–base, n+–source, p+–body, second interlayer oxide, contact, surface metallization,
wafer thinning and back-side metallization are performed.
Transmission Electron Microscope (TEM) photograph of a unit cell structure offabricated 2-step FP-MOSFET is shown in Fig. 3-42(g). To relax a strong stress inside
the trench during the gate poly-silicon forming, U-shaped gate structure is applied.

104

(g)

Fig. 3-42. (a)–(f) Part of fabrication process flow of 2-step FP-MOSFET (from thickoxide formation to gate electrode formation.). (g) TEM photograph of fabricated 2-step
FP-MOSFET (unit cell). [74] (c) 2019 IEEE.

Experimental results of device performance
A. Breakdown voltage and on-resistanceIn the fabricated 2-step FP-MOSFET, average of VB at Id = 10 mA was 109.9 V andthe standard deviation was 0.50 V, with the target design and the center process
conditions. RON packaged in 8-pin Small Outline Package (SOP-8) was measured under
the condition of Vgs = 10 V and Id = 30 A. The RONA obtained by deduction of the package
resistance indicated average value of 27.7 m·mm2 and good deviation of 0.46 m·mm2,
as shown in Fig. 3-43. This RONA of the 2-step FP-MOSFET is ultralow in ever reported
100-V-class device and improved by 16.6% compared with that of the conventional FPMOSFET.
B. Figure-of-merit
When the FP-MOSFET is applied in high efficiency switching circuit, gate charge
properties, i.e., gate–source charge (Qgs), gate–drain charge (Qgd), total gate charge (Qg)and output charge (Qoss), are very important. Moreover, as an indicator of the switchingproperty, Qsw is defined by sum of the Qgs after threshold voltage and the Qgd. Fig. 3-44
compares figure-of-merit (FOM) of the conventional and the 2-step FPMOSFET, under
the conditions of Vds = 50 V and Id = 35 A as the gate charge measurement.
105

It was confirmed that RON·Qg and RON·Qsw were reduced by 27.1% and 4.7%,
respectively, compared with those of the conventional device. The effect of the Qg
reduction includes modification of the gate–source insulating film structure in the
fabricated device. On the other hand, RON·Qoss was increased. The Qoss is calculated byvoltage integral of drain–source capacitance Cds. In the 2-step FP-MOSFET, the ND wasincreased to improve the RONA, so that depletion capacitance component of the Cds wasincreased and it affected to the Qoss. Thus, improvement of the tradeoff between RONA
and Qoss is further challenge to realize ultimate FP-MOSFET.

Fig. 3-43. Measured RONA distribution of 2-step FP-MOSFETs fabricated by target
design & center process conditions. [74] (c) 2019 IEEE.

Fig. 3-44. Comparison of FOM for conventional and 2-step FP-MOSFETs.
Measurement conditions: Vgs = 10 V and Id = 30 A for RON, and Vds = 50 V and Id = 35
A for Qg, Qsw, and Qoss. [74] (c) 2019 IEEE.
106

18-V sub-micron cell pitch GFP-MOSFET
Unit-cell structure design
Applying the FP-MOSFET is expanding to improve the performances in wide range
LV-MOSFETs. The lower the rated-voltage of MOSFET, the smaller the RDA contribution.
In short, the effect of the field-plate structure becomes small. In the lower voltage
MOSFET such as 12–20-V, however, there is little room to reduce the RONA, in current
advanced U-MOSFET technology, as shown in Fig. 3-45. Thus, each main component
should be reduced as possible. As shown in Fig. 3-46, sub-micron cell pitch and the gate
field plate are applied to an 18-V FP-MOSFET to reduce both RCHA and RDA [75].

Fig. 3-45. Ratio of RONA components for 20–60-V U-MOSFETs. [75] (modified).

(a)

(b)

Fig. 3-46. (a) Schematic cross-sectional structure and (b) SEM photograph of fabricated18-V sub-micron cell pitch FP-MOSFET. [75] (modified).
107

Experimental results of fabricated device
Representative characteristics of fabricated 0.92-m-pitch 18-V FP-MOSFET aredescribed below. Active area is 2.3 mm2. The leakage current of the gate oxide was 1 nA
at 7 MV/cm, and the electric field that leads to a breakdown was over 10 MV/cm. It
showed ideal insulation properties and a smoothness of the connection between the gate
oxide and the field-plate oxide (Fig. 3-47(a)). The VB of 18 V (Fig. 3-47(b)), the RONA of
2.1 m·mm2 at Vgs = 10 V and 2.6 m·mm2 at Vgs = 4.5 V were obtained (Fig. 3-48(a)).
The capacitances as a function of the Vds were showed in Fig. 3-48(b) for reference.

(a)

(b)

Fig. 3-47. (a) Gate leakage current as a function of the gate electric field and (b) offstate Id–Vds characteristic of fabricated 18-V FP-MOSFET. [75] (modified).

(a)

(b)

Fig. 3-48. (a) On-state Id–Vds characteristic [75] and (b) capacitances (Ciss, Coss, andCrss) as a function of Vds of fabricated 18-V FP-MOSFET.
108

Summary
In chapter 3, superjunction U-MOSFET (SJ-UMOSFET) and field-plate U-MOSFET(FP-MOSFET), which are evolution structure of U-MOSFET, were described. The RONA
models of both SJ-UMOSFETs and FP-MOSFETs were detailed for three different
surface patterns (stripe, square cell, and square p–column in stripe trench) in the SJUMOSFETs and four different structures (flat GFP, flat SFP, slant GFP, and slant SFP)
in the FP-MOSFETs, respectively.
In addition, each improvement structure, fabrication process, and evaluation resultof the fabricated devices were described. In the validation of the RONA models, the real
device and calculated results by the model were compared for both 60-V SJ-UMOSFET
and 100-V FP-MOSFET, and it was confirmed they showed good agreement.
As a summary of the development of the novel SJ-UMOSFETs and FP-MOSFETs,
the performances are compared each other. Fig. 3-49 shows the benchmarking of the
tradeoff characteristics between the RONA and the VB for 18–100-V-class FP-MOSFETs[8] [49] [50] [51] [52] [71] and SJ-UMOSFETs [55] [56] [57] [76] by published data andauthor’s research [10] [64] [72] [74] [75] [77]. As reference lines, 1-D silicon-limit [11] andSJ-limit [60] for half-cell pitch w = 2–0.5 m are also indicated.
In the developed novel devices, which are the continuous p–column SJ-UMOSFET[10], the split p–column SJ-UMOSFET [64] [77], the MSO-GFP-MOSFET [72], the 2step SFP-MOSFET [74], and the sub-micron-pitch GFP-MOSFET [75], superior
performances were demonstrated against the published data.

109

(a)

(b)
Fig. 3-49. Tradeoff characteristics between RONA and VB for FP-MOSFETs and SJUMOSFETs; by published data [8] [49] [50] [51] [52] [55] [56] [57] [71] [76] andauthor’s research [10] [64] [72] [74] [75] [77]. (a) Including 100-V MSO-FP-MOSFET
and (b) including 100-V 2-step FP-MOSFET. [72] (modified).

110

STRUCTURE-BASED CAPACITANCE MODELING FOR THE
LATEST FP-MOSFET COMPARING WITH D-MOSFET
Overview of structure-based capacitance modeling
Several analytical capacitance models for different vertical power device structures
have been reported, e.g., those for silicon D-MOSFETs [78], silicon U-MOSFETs [79] [80][81], and silicon carbide (SiC) D-MOSFETs [82]. In those reports, however, since the Cosscomponents of D-MOSFETs and U-MOSFETs are relatively simple, those modelingmethods are not applied to complex-structured FP-MOSFETs
In this chapter, firstly, the capacitance model for the D-MOSFET is described.
Subsequently, the capacitance model and the modeling method for the latest slant FPMOSFET are detailed comprehensively.

D-MOSFET model
Structural parameters and basic characteristics for motif device
This subsection describes a 100-V-class D-MOSFET as a motive device for thecapacitance modeling [83] [84]. Fig. 4-1(a) shows schematic cross section andrepresentative structural parameters of the D-MOSFET to describe the capacitancemodel. Fig. 4-1(b) shows components of output capacitance (Coss) and reverse transfer
capacitance (Crss) of the D-MOSFET.
The capacitance model can be described by structural parameters such as detailed
cell structure dimensions and impurity doping concentrations, as shown in Table 4-1. It
does not require any measurement of electrical characteristics. Physical constants usedin the modeling are the same as those shown in Table 4-2. As shown in Table 4-1, theunit cell width (WCell) of the D-MOSFET is set to 6.0 m, which can be obtained the VBof 100 V, as described later.

111

(a)

(b)

Fig. 4-1. (a) Schematic cross sections and representative structural parameters of DMOSFET. (b) Components of output capacitance (Coss) and reverse transfer capacitance(Crss) for D-MOSFET. [83] [84] Copyright (2018) The Japan Society of Applied Physics.

Table 4-1. Structural parameters of 100-V-class D-MOSFET to calculate capacitances.
[84] (modified).
Symbol

WCell
WG
WB
TGOX
XJB
XJB_l
ND
NA

Parameters

Unit

Cell width

Numerics
6.00

Gate width

3.40

m

p–Base width

2.60

m

Gate oxide thickness

0.05

m

p–Base junction depth

0.75

m

0.60
2.8 × 1015
5.0 × 1016

m
atoms/cm3
atoms/cm3

p–Base junction lateral length
Drift layer concentration
p–Base layer concentration

112

m

Table 4-2. Physical constants to calculate capacitances.
Symbol

q
k
T
ni

0
Si
OX

Description

Property

Elementary charge
Boltzmann’s constantAbsolute temperature
Intrinsic carrier density

Unit
C
J/K
K
atoms/cm3−191.60 × 10
1.38 × 10−23

Permittivity in vacuum

300
1.50 × 1010
8.854 × 10−14

Dielectric constant of Si

11.7

Dielectric constant of SiO2

3.9

F/cm

Before the capacitance modeling, basic characteristics of D-MOSFET was confirmed
using the TCAD simulator named Sentaurus Device [85]. As a result, the D-MOSFET
showed a sufficient VB of 111.3 V and an RONA of 199.1 m·mm2, as shown in Table 4-3.

Table 4-3. TCAD simulated basic characteristics for 100-V-class D-MOSFET. [84](modified).
SymbolVBs
VTH

Characteristics
Breakdown voltage
Threshold voltage

RONA

On-resistance

RON·Crss
RON·Coss
RON·Qoss

FOM_1
FOM_2
FOM_3

Conditions

Jd = 1A/mm2

111.3

Unit
V

Vds = 10 V, Jd = 1mA/mm2
Vgs = 10 V, Vds = 0.1 V

2.09

V

199.1

m·mm2

1364

m·pF

4205

m·pF

390

m·pF

Vds = 50 V
Vds = 50 V
Vds = 50 V

113

Components of output capacitance (Coss) 5
Fig. 4-1(b) shows the components of Coss in the D-MOSFET. Coss is simply expressed
as sum of drain–source capacitance Cds and gate–drain capacitance Cgd.
𝐶𝑜𝑠𝑠 𝐷𝑀𝑂𝑆 = 𝐶𝑑𝑠 + 𝐶𝑔𝑑(4-1)

Drain–source capacitance (Cds)
The Cds is a pn-junction capacitance and it is varied by the drain–source voltage Vds.

𝑞𝑁𝐷 𝜀𝑆𝑖 𝜀0 (𝑊𝐵 + 2𝑋𝐽𝐵_𝑙 )𝐶𝑑𝑠 = √∙
2(𝑉𝑑𝑠 + 𝑉𝑏𝑖 )
𝑊𝐶𝑒𝑙𝑙

(4-2)

Here, q is the elementary charge, Si0 is the permittivity of silicon, WB is the p–basewidth, and XJB_l is the lateral expansion length of the p–base junction. The built-in
potential Vbi is given by
𝑉𝑏𝑖 =𝑘𝑇 𝑁𝐴 𝑁𝐷
ln
,
𝑞
𝑛𝑖 2

(4-3)

where k is Boltzmann’s constant, T is the absolute temperature, ni is the intrinsic carrier
density of Si, and NA is a p–base layer concentration.
Gate–drain capacitance (Cgd)
The Cgd is a series connection of a gate oxide capacitance (CGOX) and a depletion layer
capacitance (Cdep). Since Crss is equal to Cgd, Crss is written as
𝐶𝑟𝑠𝑠 = 𝐶𝑔𝑑 =𝐶𝐺𝑂𝑋 𝐶𝑑𝑒𝑝.
𝐶𝐺𝑂𝑋 + 𝐶𝑑𝑒𝑝

(4-4)

Furthermore, CGOX and Cdep are expressed as

𝐶𝐺𝑂𝑋 =𝜀𝑂𝑋 𝜀0 (𝑊𝐺 − 2𝑋𝐽𝐵_𝑙 )
∙
,
𝑇𝐺𝑂𝑋
𝑊𝐶𝑒𝑙𝑙

(4-5)

5 Subsections 4.2.2–4.2.4 are reproduction of [84] section 3.1, Copyright (2018) The Japan Society ofApplied Physics, and a part of description is modified.

114

𝐶𝑑𝑒𝑝 =𝜀𝑆𝑖 𝜀0 (𝑊𝐺 − 2𝑋𝐽𝐵_𝑙 )∙,𝑊𝑑_𝑚𝑜𝑠
𝑊𝐶𝑒𝑙𝑙

(4-6)

where OX0 is the permittivity of SiO2, TGOX is the gate oxide thickness, and WG is thegate width. Wd_mos is the depletion layer width beneath the gate electrode and is given
by [86]

𝑊𝑑_𝑚𝑜𝑠 =𝜀𝑆𝑖 𝑇𝐺𝑂𝑋
2𝑉𝑑𝑠 𝜀𝑂𝑋 2 𝜀0
+ 1 − 1).
(√𝜀𝑂𝑋𝑞𝑁𝐷 𝜀𝑆𝑖 𝑇𝐺𝑂𝑋 2(4-7)

By substituting Eqs. (4-5)–(4-7) into Eq. (4-4), the Crss model can be obtained.
𝐶𝑟𝑠𝑠 𝐷𝑀𝑂𝑆 = 𝐶𝑔𝑑 =𝜀𝑂𝑋 𝜀02𝑉 𝜀 2 𝜀√ 𝑑𝑠 𝑂𝑋 0
𝑞𝑁𝐷 𝜀𝑆𝑖+ 𝑇𝐺𝑂𝑋 2∙

𝑊𝐺 − 2𝑋𝐽𝐵_𝑙
𝑊𝐶𝑒𝑙𝑙

(4-8)

Finally, by substituting Eqs. (4-2), (4-3) and (4-8) into Eq. (4-1), the Coss model can beobtained.

𝐶𝑜𝑠𝑠 𝐷𝑀𝑂𝑆 =√𝑊𝐵 + 2𝑋𝐽𝐵_𝑙𝑞𝑁𝐷 𝜀𝑆𝑖 𝜀0𝜀𝑂𝑋 𝜀0∙+𝑘𝑇 𝑁𝐴 𝑁𝐷𝑊
2𝑉 𝜀 2 𝜀𝐶𝑒𝑙𝑙
2 (𝑉𝑑𝑠 + 𝑞 ln)
√ 𝑑𝑠 𝑂𝑋 0 + 𝑇𝐺𝑂𝑋 2
𝑛𝑖 2
𝑞𝑁𝐷 𝜀𝑆𝑖∙

𝑊𝐺 − 2𝑋𝐽𝐵_𝑙
𝑊𝐶𝑒𝑙𝑙

List of capacitance model
Table 4-4. List of Coss and Crss model equations for D-MOSFET. [84] (modified).
𝜀𝑂𝑋 𝜀0

𝐶𝑟𝑠𝑠 𝐷𝑀𝑂𝑆 =√𝐶𝑜𝑠𝑠 𝐷𝑀𝑂𝑆 =2𝑉𝑑𝑠 𝜀𝑂𝑋 2 𝜀0
+ 𝑇𝐺𝑂𝑋 2
𝑞𝑁𝐷 𝜀𝑆𝑖√∙

𝑊𝐺 − 2𝑋𝐽𝐵_𝑙
𝑊𝐶𝑒𝑙𝑙

𝑞𝑁𝐷 𝜀𝑆𝑖 𝜀0
𝑊𝐵 + 2𝑋𝐽𝐵_𝑙∙+ 𝐶𝑟𝑠𝑠 𝐷𝑀𝑂𝑆
𝑘𝑇 𝑁𝐴 𝑁𝐷𝑊
𝐶𝑒𝑙𝑙
2 (𝑉𝑑𝑠 +
ln
)
𝑞
𝑛𝑖 2

115

(4-9)

FP-MOSFET model
Structural parameters and basic characteristics for motif device
This subsection describes a 100-V-class slant FP-MOSFET which is the latest LVMOSFET structure, as a motive device for the capacitance modeling [83] [84]. Fig. 4-2(a)shows schematic cross section and representative structural parameters of the slant FPMOSFET. Fig. 4-2(b) shows comprehensive structural parameters of the slant FPMOSFET to describe the capacitance model.
The capacitance model can be described by structural parameters such as detailed
cell structure dimensions and impurity doping concentrations, as shown in Table 4-5. It
does not require any measurement of electrical characteristics. Physical constants usedin the modeling are the same as those shown in Table 4-2. As shown in Table 4-5, theunit cell width (WCell) of the FP-MOSFET is set to 2.6 m, which is smaller than that of

(a)

(b)

(c)

Fig. 4-2. (a) Schematic cross sections and representative structural parameters of slant
FP-MOSFET. (b) Comprehensive structural parameters of FP-MOSFET (half-cellstructure) to describe capacitance model. (c) Components of output capacitance (Coss)and reverse transfer capacitance (Crss) for FP-MOSFET. [83] [84] Copyright (2018) The
Japan Society of Applied Physics.

116

D-MOSFET (6.0 m) in subsection 4.2.1. Despite its smaller WCell, it has a drift layer
concentration (ND) that is ten times higher than that of the D-MOSFET.

Table 4-5. Structural parameters of 100-V-class FP-MOSFET to calculate capacitances.
[84] (modified).
Symbol

WCell
WT
WMesa
DT
DG
TGOX
TFPOX_t
TFPOX_b
TFPOX_c
XJB
ND
NA

Parameters

Numerics

Unit

Cell width

2.60

m

Trench width

1.50

m

Mesa width

1.10

m

Trench depth

6.00

m

Gate depth

1.00

m

Gate oxide thickness

0.05

m

Field-plate oxide thickness (top)

0.10

m

Field-plate oxide thickness (bottom)

0.75

m

Field-plate oxide thickness (center)

0.75

m

0.90
3.0 × 1016
1.0 × 1017

m
atoms/cm3
atoms/cm3

p–Base junction depth
Drift layer concentration
p–Base layer concentration

Before the capacitance modeling, basic characteristics of the FP-MOSFETs wereconsidered by using TCAD simulation as shown in Table 4-6. As a result, the FPMOSFET showed a sufficient VB of 110.1 V and an ultralow RONA of 32.8 m·mm2, which
was approximately one-sixth of that of the D-MOSFET, described in subsection 4.2.1.
Moreover, in the FP-MOSET, a very small RON·Crss, which is approximately onetwentieth of that of the D-MOSFET, was confirmed. Those indicate good features of the
FP-MOSFET. However, RON·Qoss is still high. Therefore, the capacitance modeling
especially for Coss, which is required to the analysis of PQoss, is important.

Table 4-6. TCAD simulated basic characteristics for 100-V-class FP-MOSFET. [84](modified).
SymbolVB
VTHCharacteristics
Breakdown voltage
Threshold voltage

RONA

On-resistance

RON·Crss
RON·Coss
RON·Qoss

FOM_1
FOM_2
FOM_3

Jd = 1A/mm2
Vds = 10 V, Jd = 1mA/mm2
Vgs = 10 V, Vds = 0.1 V

Conditions
110.1

Unit
V

2.03

V

32.8

m·mm2

Vds = 50 V
Vds = 50 V
Vds = 50 V

5.7

m·pF

2040

m·pF

309

m·pF

117

Components of the output capacitance (Coss) 6
As an approach to capacitance modeling in the complex FP-MOSFET structure, four
components of Coss, as shown in Fig. 4-2(c), are considered. The Coss in the FP-MOSFET
is simply expressed as
𝐶𝑜𝑠𝑠 𝐹𝑃𝑀𝑂𝑆 = 𝐶𝑑𝑠1 + 𝐶𝑑𝑠2 + 𝐶𝑑𝑠3 + 𝐶𝑔𝑑 .

(4-10)

Here, Cds1 is the depletion layer capacitance of the pn-junction, Cds2 is a series connectionof a field-plate oxide capacitance and a depletion layer capacitance along the trench side
wall, and Cds3 is the trench bottom capacitance including the field-plate oxide anddepletion layers. In the FP-MOSFET, however, Cgd is negligible in the case of Cosscalculation, because the area of the parallel-plate capacitor is usually very small for
optimized cell design.
Fig. 4-3 show the TCAD-simulated FP-MOSFET half-cell structures, which show
the Vds dependence of equal-potential contours. The potential contours of 5-V intervals
and the depletion layer boundaries are shown as black and white lines, respectively. In
each figure, the dominant capacitance components are Cds1, Cds2, and Cds3, respectively.
pn-Junction capacitanceIn the region of Cds1 (Fig. 4-3(a)), the depletion layer of the pn-junction extends down
to the vertical direction with increasing Vds. However, the capacitance width in thelateral direction decreases because of the expansion of another depletion layer along thetrench side wall caused by the field-plate effect. It is considered that this pn-junction
capacitance Cj is divided into Cj0 and Cj1 according to the Vds condition.
𝐶𝑗0 ,𝐶𝑑𝑠1 = 𝐶𝑗 = {𝐶𝑗1 ,𝑉𝑑𝑠 < 1(𝑉)𝑉𝑑𝑠 ≥ 1(𝑉)

(4-11)

Cj0 is the capacitance at an early voltage including the built-in potential Vbi. Cj0 ismodeled similarly to Eq. (4-2) for the Cds of the D-MOSFET.

𝑞𝑁𝐷 𝜀𝑆𝑖 𝜀0 𝑊𝑀𝑒𝑠𝑎
𝐶𝑗0 = √⋅
2(𝑉𝑑𝑠 +𝑉𝑏𝑖 ) 𝑊𝐶𝑒𝑙𝑙(4-12)

6 Subsections 4.3.2–4.3.6 are reproduction of [84] section 3.2, Copyright (2018) The Japan Society ofApplied Physics, and a part of description is modified and Eq. (29) is corrected.

118

(a)

(b)

(c)

Fig. 4-3. TCAD-simulated FP-MOSFET half-cell structures, which represent Vds
dependence of equal-potential contours. Potential contours and depletion layerboundaries are shown as black lines and white lines, respectively. Three capacitancecomponents are shown as dominant regions: (a) main pn-junction, (b) field-plate oxideand depletion layer along trench side wall, and (c) field-plate oxide and depletion layerof trench bottom. [84] Copyright (2018) The Japan Society of Applied Physics.
where WMesa is the mesa width, ND is the n–drift layer concentration, and Vbi is the builtin potential.
Before Cj1 modeling, some parameters shown in Fig. 4-2(b) are additionallyexplained.  is the angle of the field plate and it is given by
𝑇𝐹𝑃𝑂𝑋_𝑏 − 𝑇𝐹𝑃𝑂𝑋_𝑡𝜃2 = tan−1 (),
𝐷𝑇 − 𝑋𝐽𝐵 − 𝑋 − 𝑇𝐹𝑃𝑂𝑋_𝑐(4-13)

where TFPOX_t and TFPOX_b are the lateral field-plate oxide thicknesses at top and bottom
positions, respectively, TFPOX_c is the vertical field-plate oxide thickness of the center of
the trench bottom, DT is the trench depth, XJB is the p–base junction depth, and X is thelength between the XJB and the horizontal position of the top of the field plate.

 is the direction of the electric line of force and it is given by119𝜃1 = tan−1 (𝜀𝑆𝑖tan 𝜃2 ).
𝜀𝑂𝑋(4-14)

T(y) and W(y) are used to calculate the charge densities in the field-plate oxide andthe silicon mesa region, respectively, and are given by𝑇(𝑦) = 𝑇𝑂𝑋 (𝑦)cos 𝜃2 ,𝑊(𝑦) =𝑊𝑆𝑖 (𝑦),cos 𝜃1(4-15)(4-16)

where y is the depth from the top of the field plate, TOX(y) is the field-plate oxide
thickness at the position y and WSi(y) is the depletion layer width of the mesa region
along the slant field plate at the position y. TOX(y) is expressed as
𝑇𝑂𝑋 (𝑦) =𝑇𝐹𝑃𝑂𝑋_𝑏 − 𝑇𝐹𝑃𝑂𝑋_𝑡
𝑦 + 𝑇𝐹𝑃𝑂𝑋_𝑡 .
𝐷𝑇 − 𝑋𝐽𝐵 − 𝑋 − 𝑇𝐹𝑃𝑂𝑋_𝑐(4-17)

Although W(y) varies with Vds, it has to be considered that Vds is shared by thevoltage of the field-plate oxide (VOX) and the voltage of the silicon mesa (VSi). The
relationship between VOX, VSi, T(y), and W(y) are expressed as
𝑉𝑑𝑠 = 𝑉𝑆𝑖 + 𝑉𝑂𝑋 ,(4-18)

1
𝑉𝑆𝑖 = 𝐸𝑆𝑖 𝑊(𝑦),2(4-19)𝑉𝑂𝑋 = 𝐸𝑂𝑋 𝑇(𝑦),(4-20)𝜀𝑆𝑖 𝐸𝑆𝑖 cos 𝜃1 = 𝜀𝑂𝑋 𝐸𝑂𝑋 cos 𝜃2,(4-21)

𝐸𝑆𝑖 =

𝑞𝑁𝐷
𝑊(𝑦),
𝜀𝑆𝑖 𝜀0(4-22)

where ESi and EOX are the electric field strengths of the silicon mesa region and fieldplate oxide region, respectively. W(y) is derived by solving Eqs. (4-18)–(4-22). Since yvaries with Vds, W(y) is exactly expressed as W(Vds,y) and can be described as

120

2

𝜀𝑆𝑖 𝑐𝑜𝑠 𝜃1
𝜀𝑆𝑖 𝑐𝑜𝑠 𝜃1
2𝜀𝑆𝑖 𝜀0𝑊(𝑉𝑑𝑠 , 𝑦) = −∙ 𝑇(𝑦) + √(∙ 𝑇(𝑦)) +∙ 𝑉𝑑𝑠 .
𝜀𝑂𝑋 𝑐𝑜𝑠 𝜃2
𝜀𝑂𝑋 𝑐𝑜𝑠 𝜃2
𝑞𝑁𝐷(4-23)

Cj1 includes the effect of capacitance width decrease by W(Vds,y) and is described as𝐶𝑗1 =𝜀𝑆𝑖 𝜀0 𝑊𝑀𝑒𝑠𝑎 − 2𝑊(𝑉𝑑𝑠 , 𝑦)⋅.
𝑦0 + 𝑋
𝑊𝐶𝑒𝑙𝑙(4-24)

Oxide and depletion layer capacitance along field plate
In the region of Cds2 (Fig. 4-3(b)), the initial Cds2 is nearly equal to the field-plate
oxide capacitance CFPOX. With increasing Vds, the mesa region is depleted linearly owing
to the relation 𝑦0 ∝ 𝑉𝑑𝑠 in the vertical direction, and the lateral depletion width under
the position of y0 expands gradually by W(Vds,y). Thus, Cds2 is divided into two
components according to the Vds condition.
𝐶,
𝐶𝑑𝑠2 = { 𝐹𝑃𝑂𝑋
𝐶𝐹𝑃 (𝑉𝑑𝑠 ),𝑉𝑑𝑠 < 1(𝑉)𝑉𝑑𝑠 ≥ 1(𝑉)

(4-25)CFPOX is provided by integrating field-plate oxide thickness in the depth direction.
𝐶𝐹𝑃𝑂𝑋 =

2(𝐷𝑇 − 𝑋𝐽𝐵 − 𝑋 − 𝑇𝐹𝑃𝑂𝑋_𝑐 )𝜀𝑂𝑋 𝜀0
𝑊𝐶𝑒𝑙𝑙 (𝑇𝐹𝑃𝑂𝑋_𝑏 − 𝑇𝐹𝑃𝑂𝑋_𝑡 )⋅ 𝑙𝑛

𝑇𝐹𝑃𝑂𝑋_𝑏
𝑇𝐹𝑃𝑂𝑋_𝑡(4-26)At an arbitrary position y, the charge, which is across the field plate and thedepletion layer in the mesa region, is defined as dQ. Differential equation of dQ expresses
a voltage change of the drain–source electric charge and described as
𝑑𝑄
𝑑
= 𝑞𝑁𝐷
𝑊(𝑉𝑑𝑠 , 𝑦).
𝑑𝑉𝑑𝑉(4-27)The voltage dependence capacitance CFP(Vds) is provided by integrating Eq. (4-27)
from y0 to yb, which is the end of the depletion layer and is described as𝑦

𝐶𝐹𝑃 (𝑉𝑑𝑠 ) =2 ∙ ∫𝑦 𝑏 𝑞𝑁𝐷
0𝑑(𝑊(𝑉𝑑𝑠 , 𝑦))𝑑𝑦
𝑑𝑉
.
𝑊𝐶𝑒𝑙𝑙

(4-28)

Finally, by substituting Eqs. (4-15), (4-17) and (4-23) into Eq. (4-28), CFP(Vds) can beobtained.
121

𝐶𝐹𝑃 (𝑉𝑑𝑠 )
=

𝑦𝑏
2
∫
𝑊𝐶𝑒𝑙𝑙 𝑦0𝜀𝑆𝑖 𝜀0
2𝑦(𝑇𝐹𝑃𝑂𝑋_𝑡 − 𝑇𝐹𝑃𝑂𝑋_𝑏 )2
2√𝜀𝑆𝑖 cos 𝜃1 [𝑇𝐹𝑃𝑂𝑋_𝑡 + 𝑋𝐽𝐵 + 𝑋 + 𝑇𝐹𝑃𝑂𝑋_𝑏 − 𝐷𝑇 ]2𝜀 𝜀0 𝑉𝑑𝑠
+ 𝑆𝑖
𝑞𝑁𝐷
𝜀𝑂𝑋 2 cos4 𝜃2𝑑𝑦(4-29)

Trench bottom capacitanceIn the region of Cds3 (Fig. 4-3(c)), when Vds increase, at last y0 reaches almost thesame depth as that of bottom of field plate. Cds2 decreases continuously in the model (Eqs.
(4-25) and (4-29)). Therefore, the trench bottom capacitance Cds3 has to be included as acomponent of total Coss.
In the trench bottom region, the depletion layer Wbtm(Vds,l) begins to expand slightly
when Vds is greater than approximately 60 V. Wbtm(Vds,l) can be described similarly to
Eq. (4-23).
2

𝜀𝑆𝑖 𝑐𝑜𝑠 𝜃3
𝜀𝑆𝑖 𝑐𝑜𝑠 𝜃32𝜀𝑆𝑖 𝜀0
𝑊𝑏𝑡𝑚 (𝑉𝑑𝑠 , 𝑙) = −∙ 𝑇(𝑙) + √(∙ 𝑇(𝑙)) +∙ 𝑉𝑑𝑠
𝜀𝑂𝑋 𝑐𝑜𝑠 𝜃4
𝜀𝑂𝑋 𝑐𝑜𝑠 𝜃4𝑞𝑁𝐷(4-30)

Here, l is the length from the center of the trench, T(l) is the oxide thickness of the trenchbottom, and 4 and 3 are given by𝑙𝜃4 = tan−1 (),
𝑇𝐹𝑃𝑂𝑋_𝑐(4-31)𝜀𝑆𝑖tan 𝜃4 ).
𝜀𝑂𝑋(4-32)

𝜃3 = tan−1 (Thus, Cds3 is provided by integrating Wbtm(Vds,l) in the direction of the trench widthfrom 0 to TFPOX_b and is described as𝑇

𝐶𝑑𝑠3 =𝑑(𝑊 (𝑉 , 𝑙))𝑑𝑙𝑑𝑉 𝑏𝑡𝑚 𝑑𝑠.
𝑊𝐶𝑒𝑙𝑙

2 ∙ ∫0 𝐹𝑃𝑂𝑋_𝑏 𝑞𝑁𝐷

122(4-33)

Gate–drain capacitance (Cgd)
As mentioned above, in the FP-MOSFET, Cgd is negligible small, which isapproximately two to three orders of magnitude lower than Coss. However, to compare itwith the D-MOSFET, simplified modeling for Cgd were carried out. As shown in Fig.
4-2(b), the Cgd of the FP-MOSFET is the series connection of CGOX and Cdep, which is thesame as in the case of the D-MOSFET. In the FP-MOSFET, CGOX and Cdep are expressedas𝜀𝑂𝑋 𝜀0 2(𝐷𝐺 − 𝑋𝐽𝐵 )
∙
,
𝑇𝐺𝑂𝑋
𝑊𝐶𝑒𝑙𝑙

(4-34)𝜀𝑆𝑖 𝜀0 2(𝐷𝐺 − 𝑋𝐽𝐵 )∙.
𝑊𝑑_𝑚𝑜𝑠𝑊𝐶𝑒𝑙𝑙(4-35)𝐶𝐺𝑂𝑋 =

𝐶𝑑𝑒𝑝 =

Here, DG is the gate depth, XJB is the p–base junction depth, and TGOX is the gate oxide
thickness.
By substituting Eqs. (4-7), (4-34), and (4-35) into Eq. (4-4), the initial capacitance

Cgd0 can be obtained as

𝐶𝑔𝑑0 =𝜀𝑂𝑋 𝜀02𝑉 𝜀 2 𝜀√ 𝑑𝑠 𝑂𝑋 0
𝑞𝑁𝐷 𝜀𝑆𝑖∙+ 𝑇𝐺𝑂𝑋 2

2(𝐷𝐺 − 𝑋𝐽𝐵 ).
𝑊𝐶𝑒𝑙𝑙(4-36)

Unlike the D-MOSFET, in the FP-MOSFET, the capacitance width of Cgd isdrastically reduced by the factor of W(Vds,y), as shown in Eq. (4-23). Thus, finally, theCrss model is described as
𝐶𝑟𝑠𝑠 𝐹𝑃𝑀𝑂𝑆 = 𝐶𝑔𝑑0 ∙𝑊𝑀𝑒𝑠𝑎 − 2𝑊(𝑉𝑑𝑠 , 𝑦)𝑊𝑀𝑒𝑠𝑎
𝜀𝑂𝑋 𝜀0=√2𝑉𝑑𝑠 𝜀𝑂𝑋 2 𝜀0
2𝑞𝑁𝐷 𝜀𝑆𝑖 + 𝑇𝐺𝑂𝑋∙

2(𝐷𝐺 − 𝑋𝐽𝐵 ) 𝑊𝑀𝑒𝑠𝑎 − 2𝑊(𝑉𝑑𝑠 , 𝑦)
∙
.
𝑊𝐶𝑒𝑙𝑙
𝑊𝑀𝑒𝑠𝑎

123

(4-37)

List of capacitance model

Table 4-7. List of Coss and Crss model equations for FP-MOSFET. [84] (modified).
𝜀𝑂𝑋 𝜀0

𝐶𝑟𝑠𝑠 𝐹𝑃𝑀𝑂𝑆 =√2𝑉𝑑𝑠 𝜀𝑂𝑋 2 𝜀0
+ 𝑇𝐺𝑂𝑋 2
𝑞𝑁𝐷 𝜀𝑆𝑖∙2(𝐷𝐺 − 𝑋𝐽𝐵 ) 𝑊𝑀𝑒𝑠𝑎 − 2𝑊(𝑉𝑑𝑠 , 𝑦)
∙
𝑊𝐶𝑒𝑙𝑙
𝑊𝑀𝑒𝑠𝑎
2

𝜀𝑆𝑖 𝑐𝑜𝑠 𝜃1
𝜀𝑆𝑖 𝑐𝑜𝑠 𝜃1
2𝜀𝑆𝑖 𝜀0𝑊(𝑉𝑑𝑠 , 𝑦) = −∙ 𝑇(𝑦) + √(∙ 𝑇(𝑦)) +∙ 𝑉𝑑𝑠
𝜀𝑂𝑋 𝑐𝑜𝑠 𝜃2
𝜀𝑂𝑋 𝑐𝑜𝑠 𝜃2
𝑞𝑁𝐷
𝐶𝑜𝑠𝑠 𝐹𝑃𝑀𝑂𝑆 = 𝐶𝑑𝑠1 + 𝐶𝑑𝑠2 + 𝐶𝑑𝑠3 + 𝐶𝑔𝑑

𝐶𝑑𝑠1 =𝑞𝑁𝐷 𝜀𝑆𝑖 𝜀0 𝑊𝑀𝑒𝑠𝑎
𝐶𝑗0 = √⋅
2(𝑉𝑑𝑠 +𝑉𝑏𝑖 ) 𝑊𝐶𝑒𝑙𝑙,

𝑉𝑑𝑠 < 1(𝑉)𝜀𝑆𝑖 𝜀0 𝑊𝑀𝑒𝑠𝑎 − 2𝑊(𝑉𝑑𝑠 , 𝑦)𝐶 =⋅,{ 𝑗1 𝑦0 + 𝑋
𝑊𝐶𝑒𝑙𝑙

𝑉𝑑𝑠 ≥ 1(𝑉)𝐶𝑂𝑋 =2(𝐷𝑇 − 𝑋𝐽𝐵 − 𝑋 − 𝑇𝐹𝑃𝑂𝑋_𝑐 )𝜀𝑂𝑋 𝜀0⋅ 𝑙𝑛𝑊𝐶𝑒𝑙𝑙 (𝑇𝐹𝑃𝑂𝑋_𝑏 − 𝑇𝐹𝑃𝑂𝑋_𝑡 )𝐶𝑑𝑠2 =𝑦𝑑2 ∙ ∫𝑦 𝑏 𝑞𝑁𝐷(𝑊(𝑉𝑑𝑠 , 𝑦))𝑑𝑦𝑑𝑉
0
𝐶𝐹𝑃 (𝑉𝑑𝑠 ) ={𝑊𝐶𝑒𝑙𝑙

𝑇𝐹𝑃𝑂𝑋_𝑏,
𝑇𝐹𝑃𝑂𝑋_𝑡

𝑉𝑑𝑠 < 1(𝑉),𝑉𝑑𝑠 ≥ 1(𝑉)2

𝜀𝑆𝑖 𝑐𝑜𝑠 𝜃1
𝜀𝑆𝑖 𝑐𝑜𝑠 𝜃1
2𝜀𝑆𝑖 𝜀0𝑊(𝑉𝑑𝑠 , 𝑦) = −∙ 𝑇(𝑦) + √(∙ 𝑇(𝑦)) +∙ 𝑉𝑑𝑠
𝜀𝑂𝑋 𝑐𝑜𝑠 𝜃2
𝜀𝑂𝑋 𝑐𝑜𝑠 𝜃2
𝑞𝑁𝐷
𝑇

𝐶𝑑𝑠3 =𝑑(𝑊 (𝑉 , 𝑙))𝑑𝑙𝑑𝑉 𝑏𝑡𝑚 𝑑𝑠
𝑊𝐶𝑒𝑙𝑙

2 ∙ ∫0 𝐹𝑃𝑂𝑋_𝑏 𝑞𝑁𝐷

2

𝜀𝑆𝑖 𝑐𝑜𝑠 𝜃3
𝜀𝑆𝑖 𝑐𝑜𝑠 𝜃32𝜀𝑆𝑖 𝜀0
𝑊𝑏𝑡𝑚 (𝑉𝑑𝑠 , 𝑙) = −∙ 𝑇(𝑙) + √(∙ 𝑇(𝑙)) +∙ 𝑉𝑑𝑠
𝜀𝑂𝑋 𝑐𝑜𝑠 𝜃4
𝜀𝑂𝑋 𝑐𝑜𝑠 𝜃4
𝑞𝑁𝐷
𝐶𝑔𝑑 ~0124

Comparison of SFP-MOSFET and GFP-MOSFET models
Structural parameters and basic characteristics for motif device
This subsection describes a comparison between source field-plate (SFP) and gate
field-plate (GFP) MOSFETs (cf. subsection 3.3.1) regarding the capacitance modeling[87]. 60-V-class slant FP-MOSFET which is the latest LV-MOSFET structure is chosen
as a motive device, which are shown in Fig. 4-4(a) and (b). Comprehensive structuralparameters of both FP-MOSFETs to describe the capacitance model are shown in Fig.
4-4(c).
The capacitance model can be described by structural parameters such as detailed
cell structure dimensions and impurity doping concentrations, as shown in Table 4-8.
Physical constants used in the modeling are the same as those shown in Table 4-2.

(a)

(b)

(c)

Fig. 4-4. Schematic cross-sectional structures for (a) SFP-MOSFET and (b) GFPMOSFET. (c) Comprehensive structural parameters of FP-MOSFET (half-cellstructure) to describe capacitance model. [87] (modified).
125

Table 4-8. Structural parameters of 60-V-class SFP/GFP-MOSFETs to calculate
capacitances. [87] (modified).
Symbol

WCell
WT
WMesa
DT
DG
TGOX
TFPOX_t
TFPOX_b
TFPOX_c
XJB
ND
NA

Numerics

Unit

Cell widthParameters

1.60

m

Trench width

0.80

m

Mesa width

0.80

m

Trench depth

3.50

m

Gate depth

1.00

m

Gate oxide thickness

0.05

m

Field-plate oxide thickness (top)

0.05

m

Field-plate oxide thickness (bottom)

0.35

m

Field-plate oxide thickness (center)

0.40

m

0.90
6.0 × 1016
2.2 × 1017

m
atoms/cm3
atoms/cm3

p–Base junction depth
Drift layer concentration
p–Base layer concentration

Before the comparison of capacitance model, basic characteristics of both FPMOSFETs were simulated by TCAD. As a result in Table 4-9, both FP-MOSFETs showeda sufficient VB of 67.4 V, and standard VTH of 1.67–1.69 V, which can be driven by 5-V
logic-level voltage. Ultralow RONA of 10.9 m·mm2 and 8.7 m·mm2 were obtained for
the SFP-MOSEFT and the GFP-MOSFET, respectively. The reason of the RONA of the
GFP-MOSFET which is 20% lower than that of the SFP-MOSFET is due to the smaller
drift layer resistance RDA, as shown in Eq. (3-30). In contrary, in the SFP-MOSET, a Crsswhich is approximately two orders of magnitude lower than that of the GFP-MOSFET,
was confirmed. Those indicate good features of both SFP-MOSFET and GFP-MOSFET.

Table 4-9. TCAD simulated basic characteristics for 60-V-class SFP/GFP-MOSFETs. [87](modified).
SFPMOSFETGFPMOSFET

Unit

Jd = 1A/mm2
Vds = 10 V,
Jd = 1mA/mm2
Vgs = 10 V,
Vds = 0.1 V

67.4

67.4

V

1.69

1.67

V

10.9

8.70

m·mm2

Vds = 30 V
Vds = 30 V

821
147

827
147

pF/mm2
pF/mm2

Vds = 30 V

1.36

144

pF/mm2

SymbolCharacteristics

Conditions

VB

Breakdown voltage

VTH

Threshold voltage

RONA

On-resistance

Crss/A
Coss/A

Input capacitance
Output capacitance
Reverse transfer
capacitance

Crss/A126

As described above, there is a possibility that the SFP-MOSFET and the GFPMOSFET are selected according to the application. Therefore the capacitance modeling
especially for both Coss and Crss, which are required to the analysis of PQoss and PSW, areimportant.
Components of output capacitance (Coss) and reverse transfer capacitance (Crss)7

Fig. 4-5 shows parasitic capacitance components of both SFP-MOSFET and GFPMOSFET, which are shown on the TCAD simulated unit cell structures.
Both Coss and Crss models for the SFP-MOSFET were described in section 4.3. It isconsidered that the capacitance components of the SFP-MOSFET can be replaced withthose of the GFP-MOSFET.
For the SFP-MOSFET, the Coss and the Crss are given by
𝐶𝑜𝑠𝑠 𝑆𝐹𝑃𝑀𝑂𝑆 = 𝐶𝑑𝑠1 + 𝐶𝑑𝑠2 + 𝐶𝑑𝑠3 + 𝐶𝑔𝑑 ,(4-38)

𝐶𝑟𝑠𝑠 𝑆𝐹𝑃𝑀𝑂𝑆 = 𝐶𝑔𝑑 ,(4-39)For the GFP-MOSFET, the Coss and the Crss are given by
𝐶𝑜𝑠𝑠 𝐺𝐹𝑃𝑀𝑂𝑆 = 𝐶𝑑𝑠 + 𝐶𝑔𝑑1 + 𝐶𝑔𝑑2 + 𝐶𝑔𝑑3 ,(4-40)

𝐶𝑟𝑠𝑠 𝐺𝐹𝑃𝑀𝑂𝑆 = 𝐶𝑔𝑑1 + 𝐶𝑔𝑑2 + 𝐶𝑔𝑑3 ,(4-41)

Regarding those components: Cds1, Cds2, Cds3, Cgd, Cds, Cgd1, Cgd2, and Cgd3 aredescribed in the following.

7

Subsections 4.4.2–4.4.5 are reproduction of [87] chapter 3, and a part of description is modified andcomprehensive explanations of the equations are additionally provided.

127

(a)

(b)

Fig. 4-5. Parasitic capacitance components for (a) SFP-MOSFET and (b) GFP-MOSFET.
White lines indicate depletion layer boundaries at Vds = 10 V by TCAD simulation.
[87] (modified).
pn-Junction capacitanceCds1 of the SFP-MOSFET and Cds of the GFP-MOSFET are expressed as same
equation which is a pn-junction capacitance Cj of mesa region. In the region, thedepletion layer of the pn-junction extends down to vertical direction of the drift layer as
increasing Vds. However, it is considered that this pn-junction capacitance Cj is divided
into Cj0 and Cj1 according to the Vds condition, as described in subsection 4.3.3. The Cj isgiven by the following in same manner to Eqs. (4-11)–(4-24).

𝐶𝑑𝑠1 = 𝐶𝑑𝑠 = 𝐶𝑗 =𝑞𝑁𝐷 𝜀𝑆𝑖 𝜀0 𝑊𝑀𝑒𝑠𝑎
𝐶𝑗0 = √⋅
2(𝑉𝑑𝑠 +𝑉𝑏𝑖 ) 𝑊𝐶𝑒𝑙𝑙,𝜀𝑆𝑖 𝜀0 𝑊𝑀𝑒𝑠𝑎 − 2𝑊(𝑉𝑑𝑠 , 𝑦)
𝐶𝑗1 =
⋅
,
{
𝑦0 + 𝑋𝑊𝐶𝑒𝑙𝑙

𝑉𝑑𝑠 < 1.5 (𝑉)(4-42)

𝑉𝑑𝑠 ≥ 1.5 (𝑉)Here, WCell is the cell width, WMesa is the mesa width, ND is the n–drift layer
concentration, Vbi is the built-in potential, y0 is the depletion layer depth of center of themesa, and X is the length between the p–base layer depth and the horizontal position of
the top of the field plate.

128

In Eq. (4-42), W(Vds,y) is the depletion layer width in the mesa region along thesloping field-plate, and is functional equation of the Vds and y. Here, y is the depth from
top of the field-plate. The W(Vds,y) is expressed as below, which is the same as Eq. (4-23).
2

𝜀𝑆𝑖 𝑐𝑜𝑠 𝜃1
𝜀𝑆𝑖 𝑐𝑜𝑠 𝜃1
2𝜀𝑆𝑖 𝜀0𝑊(𝑉𝑑𝑠 , 𝑦) = −∙ 𝑇(𝑦) + √(∙ 𝑇(𝑦)) +∙ 𝑉𝑑𝑠
𝜀𝑂𝑋 𝑐𝑜𝑠 𝜃2
𝜀𝑂𝑋 𝑐𝑜𝑠 𝜃2𝑞𝑁𝐷(4-43)In Eq. (4-42), Cj0 is the capacitance at an early voltage including the Vbi, and Cj1
includes the effect of capacitance width decrease by W(Vds,y). In the case of the 60-Vclass FP-MOSFET, the boundary voltage between Cj0 and Cj1 is estimated as 1.5 V by
TCAD simulation.
Gate–drain capacitance (Cgd)

Cgd of the SFP-MOSFET and Cgd1 of the GFP-MOSFET can be calculated as seriesconnection of a gate oxide capacitance CGOX and a depletion layer capacitance Cdep, andare described as
𝐶𝑔𝑑 = 𝐶𝑔𝑑1 =𝐶𝐺𝑂𝑋 𝐶𝑑𝑒𝑝.
𝐶𝐺𝑂𝑋 + 𝐶𝑑𝑒𝑝

(4-44)

Finally, both Cgd and Cgd1 models are described as the following in same manner to
Eq. (4-37).

𝐶𝑔𝑑 = 𝐶𝑔𝑑1 =𝜀𝑂𝑋 𝜀02𝑉 𝜀 2 𝜀√ 𝑑𝑠 𝑂𝑋 0
𝑞𝑁𝐷 𝜀𝑆𝑖+ 𝑇𝐺𝑂𝑋 2∙

2(𝐷𝐺 − 𝑋𝐽𝐵 ) 𝑊𝑀𝑒𝑠𝑎 − 2𝑊(𝑉𝑑𝑠 , 𝑦)
∙
.
𝑊𝐶𝑒𝑙𝑙
𝑊𝑀𝑒𝑠𝑎

(4-45)

Here, DG is the gate depth, XJB is the p–base junction depth, and TGOX is the gate oxide
thickness.
Oxide and depletion layer capacitance along field plateCds2 of the SFP-MOSFET and Cgd2 the GFP-MOSFET are also expressed as same
equation of a series connection of the field-plate oxide and the depletion layer capacitancealong the trench side wall.
In the region of Cds2 and Cgd2 (Fig. 4-5), the initial capacitance is nearly equal to thefield-plate oxide capacitance CFPOX. With increasing the Vds, the mesa region is depleted
129

gradually in lateral direction by the field-plate effect, and is linearly depleted in verticaldirection. This capacitance is defined as the voltage dependence capacitance CFP(Vds) (cf.
subsection 4.3.4).
Thus, both Cds2 and Cgd2 are divided into two components according to the Vds
condition, and expressed as the following in same manner to Eqs. (4-25)–(4-29).
𝐶𝑑𝑠2 = 𝐶𝑔𝑑2
𝐶𝐹𝑃𝑂𝑋 =

2(𝐷𝑇 − 𝑋𝐽𝐵 − 𝑋 − 𝑇𝐹𝑃𝑂𝑋_𝑐 )𝜀𝑂𝑋 𝜀0⋅ 𝑙𝑛𝑊𝐶𝑒𝑙𝑙 (𝑇𝐹𝑃𝑂𝑋_𝑏 − 𝑇𝐹𝑃𝑂𝑋_𝑡 )=𝑦𝑑2 ∙ ∫𝑦 𝑏 𝑞𝑁𝐷(𝑊(𝑉𝑑𝑠 , 𝑦))𝑑𝑦𝑑𝑉
0
𝐶𝐹𝑃 (𝑉𝑑𝑠 ) ={𝑊𝐶𝑒𝑙𝑙

𝑇𝐹𝑃𝑂𝑋_𝑏,
𝑇𝐹𝑃𝑂𝑋_𝑡

𝑉𝑑𝑠 < 1.5 (𝑉),𝑉𝑑𝑠 ≥ 1.5 (𝑉)(4-46)

Here, DT is the trench depth, TFPOX_t and TFPOX_b are the lateral field-plate oxide
thicknesses at top and bottom positions, respectively, and TFPOX_c is the vertical fieldplate oxide thickness of the center of the trench bottom. Differential equation of W(Vds,y)expresses a voltage change of the electric charge in the region.
Trench bottom capacitanceCds3 of the SFP-MOSFET and Cgd3 of the GFP-MOSFET are the trench bottom
capacitance including the field-plate oxide and depletion layers. Both Cds3 and Cgd3
models are described as the following in same manner to Eq. (4-33).
𝑇

𝐶𝑑𝑠3 = 𝐶𝑔𝑑3 =𝑑(𝑊 (𝑉 , 𝑙))𝑑𝑙𝑑𝑉 𝑏𝑡𝑚 𝑑𝑠
𝑊𝐶𝑒𝑙𝑙

2 ∙ ∫0 𝐹𝑃𝑂𝑋_𝑏 𝑞𝑁𝐷(4-47)

Here, l is the length from the center of the trench and T(l) is the oxide thickness of thetrench bottom. In addition, the depletion layer of the trench bottom Wbtm(Vds,l) is given
by Eq. (4-30).

Cds3 and Cgd3 are simply calculated as 0.59 nF/cm2.

130

List of capacitance model

Table 4-10. List of Coss and Crss model equations for SFP-MOSFET and GFP-MOSFET.
𝐶𝑜𝑠𝑠 𝑆𝐹𝑃𝑀𝑂𝑆 = 𝐶𝑑𝑠1 + 𝐶𝑑𝑠2 + 𝐶𝑑𝑠3 + 𝐶𝑔𝑑 ,𝐶𝑟𝑠𝑠 𝑆𝐹𝑃𝑀𝑂𝑆 = 𝐶𝑔𝑑 ,𝐶𝑜𝑠𝑠 𝐺𝐹𝑃𝑀𝑂𝑆 = 𝐶𝑑𝑠 + 𝐶𝑔𝑑1 + 𝐶𝑔𝑑2 + 𝐶𝑔𝑑3 ,𝐶𝑟𝑠𝑠 𝐺𝐹𝑃𝑀𝑂𝑆 = 𝐶𝑔𝑑1 + 𝐶𝑔𝑑2 + 𝐶𝑔𝑑3 ,𝐶𝑑𝑠1 = 𝐶𝑑𝑠 = 𝐶𝑗 =
{

𝐶𝑗1 =

𝐶𝐹𝑃𝑂𝑋 =𝑞𝑁𝐷 𝜀𝑆𝑖 𝜀0 𝑊𝑀𝑒𝑠𝑎⋅
2(𝑉𝑑𝑠 +𝑉𝑏𝑖 ) 𝑊𝐶𝑒𝑙𝑙,

𝑉𝑑𝑠 < 1.5 (𝑉)𝜀𝑆𝑖 𝜀0 𝑊𝑀𝑒𝑠𝑎 − 2𝑊(𝑉𝑑𝑠 , 𝑦)⋅,𝑦0 + 𝑋
𝑊𝐶𝑒𝑙𝑙

𝑉𝑑𝑠 ≥ 1.5 (𝑉)𝐶𝑗0 = √

2(𝐷𝑇 − 𝑋𝐽𝐵 − 𝑋 − 𝑇𝐹𝑃𝑂𝑋_𝑐 )𝜀𝑂𝑋 𝜀0⋅ 𝑙𝑛𝑊𝐶𝑒𝑙𝑙 (𝑇𝐹𝑃𝑂𝑋_𝑏 − 𝑇𝐹𝑃𝑂𝑋_𝑡 )𝐶𝑑𝑠2 = 𝐶𝑔𝑑2 =𝑦𝑑2 ∙ ∫𝑦 𝑏 𝑞𝑁𝐷(𝑊(𝑉𝑑𝑠 , 𝑦))𝑑𝑦𝑑𝑉
0
𝐶𝐹𝑃 (𝑉𝑑𝑠 ) ={𝑊𝐶𝑒𝑙𝑙

𝑉𝑑𝑠 < 1.5 (𝑉),𝑉𝑑𝑠 ≥ 1.5 (𝑉)𝑑(𝑊 (𝑉 , 𝑙))𝑑𝑙𝑑𝑉 𝑏𝑡𝑚 𝑑𝑠
𝑊𝐶𝑒𝑙𝑙𝑇

𝐶𝑑𝑠3 = 𝐶𝑔𝑑3 =𝑇𝐹𝑃𝑂𝑋_𝑏,
𝑇𝐹𝑃𝑂𝑋_𝑡

2 ∙ ∫0 𝐹𝑃𝑂𝑋_𝑏 𝑞𝑁𝐷𝜀𝑂𝑋 𝜀0𝐶𝑔𝑑 = 𝐶𝑔𝑑1 =√2𝑉𝑑𝑠 𝜀𝑂𝑋 2 𝜀0
+ 𝑇𝐺𝑂𝑋 2
𝑞𝑁𝐷 𝜀𝑆𝑖∙2(𝐷𝐺 − 𝑋𝐽𝐵 ) 𝑊𝑀𝑒𝑠𝑎 − 2𝑊(𝑉𝑑𝑠 , 𝑦)
∙
𝑊𝐶𝑒𝑙𝑙
𝑊𝑀𝑒𝑠𝑎

Summary
In chapter 4, components of the parasitic capacitances that are important to aswitching loss design of the LV-MOSFET were described. The modeling for the latest
slant FP-MOSFET, which structure was complicated, was studied in detail based on the
D-MOSFET capacitance model. Output capacitance Coss was divided into three elements(the pn-junction capacitance, the oxide film and depletion layer capacitance along thetrench, and the oxide film and depletion layer capacitance of the trench bottom) of drain–source capacitance Cds and the element of gate–drain capacitance Cgd in total. Eachmodel equation was derived based on physical constants and device structuralparameters.

131

VALIDATION OF CAPACITANCE MODEL BY COMPARINGCALCULATED MOSFET CHARACTERISTICS AND TCAD
SIMULATIONS
100-V-class D-MOSFET and FP-MOSFET 8
As described in sections 4.2 and 4.3, the capacitances (Coss, Crss) for both D-MOSFET
and FP-MOSFET can be modeled as shown in Table 4-4 and Table 4-7 [83] [84]. To
validate an accuracy of the proposed model, some important characteristics related tothe capacitances are compared between calculation by the model and TCAD simulation,
which are using same structural parameters.

Coss–Vds curves
Firstly, Coss–Vds curves of the FP-MOSFET are calculated for each capacitanceregion. Fig. 5-1 shows the Vds dependence of calculated Coss and each component of the
FP-MOSFET; Cj (= Cj0 + Cj1), CFPOX, CFP(Vds), and Cds3 are drawn as the capacitances ofa unit device area (1 cm2).

Fig. 5-1. Coss components of 100-V-class FP-MOSFET calculated using proposed modelcompared with TCAD simulation results. [84] Copyright (2018) The Japan Society of Applied
Physics.
8

Section 5.1 is reproduction of [84] sections 4.1, 4.2 and 4.4, Copyright (2018) The Japan Society ofApplied Physics, and a part of description is modified and comprehensive explanations are additionallyprovided.

132

In the low-voltage region of Vds < 1V, Cj and CFPOX were the dominant components of
total Coss, and the sum of Cj and CFPOX corresponded well to TCAD results. This initial
capacitance region is very important for calculating Qoss and Eoss. The total Coss curves,which consist of all components, in the region of Vds ≥ 1V, also showed good agreementwith TCAD results.
Then, Coss–Vds curves of both D-MOSFET and FP-MOSFET are compared. As
described in subsections 4.2.1 and 4.3.2, it is obviously that the Coss of the FP-MOSFET
is larger than that of the D-MOSFET in the case of the same active area. However, each

RON·Coss is approximately same in both MOSFETs, as shown in Table 4-3 and Table 4-6.
Therefore, each active area is calculated as considering the reduction effect of the RON.
The active area A is calculated considering 10% RON margin for the actual productdesign.
𝐴=

𝑅𝑂𝑁 𝐴
𝑅𝑂𝑁 × 0.9

(5-1)

Fig. 5-2(a) and (b) show the calculated Coss for the D-MOSFET and the FP-MOSFET
with TCAD simulation results, respectively. Here, each active area was designed toachieve same RON = 10 m; therefore, 22.1 mm2 for the D-MOSFET and 3.67 mm2 for
the FP-MOSFET were defined.

(a)

(b)

Fig. 5-2. Coss–Vds curves calculated using proposed model compared with TCAD resultsfor 100-V-class D-MOSFET and FP-MOSFET. (a) Vds linear scale and (b) Vds log scalein X-axis. Each active area is designed for the same RON of 10m. [84] Copyright (2018)
The Japan Society of Applied Physics.

133In both Vds linear scale (Fig. 5-2(a)) and Vds log scale (Fig. 5-2(b)), the Coss curves ofboth MOSFETs corresponded well qualitatively to TCAD results. In the detailed
comparison for the FP-MOSFET, errors of 14 and 10% were seen at approximately Vds =1 and 60 V, respectively, and another region showed less than 5%. These results indicatethat the error occurred at the point where the Vds condition changed, as shown in Eqs.
(4-11), (4-25), and (4-33). In the D-MOSFET, a maximum error of 24% was seen at Vds =0.1 V; however, another region showed good results of less than 5%. The reason
considered why the early voltage region has the error is that the spherical pn-junction of
the p–base is not modeled very well.
Output charge (Qoss) and stored energy (Eoss)
By using the proposed model, the output charge Qoss and the stored energy Eoss inthe output capacitance are calculated as
𝑄𝑜𝑠𝑠 = ∫ 𝐶𝑜𝑠𝑠 (𝑉𝑑𝑠 )𝑑𝑉(5-2)

𝐸𝑜𝑠𝑠 = ∫ 𝐶𝑜𝑠𝑠 (𝑉𝑑𝑠 )𝑉𝑑𝑠 𝑑𝑉(5-3)

As mentioned above, this study especially focuses on the PQoss of the FP-MOSFET.
Fig. 5-3(a) and (b) explain the switching operation concerning Coss. When the MOSFET
is turned-off, Coss stores charges. Then, during the turn-on sequence, the on-current ION
is consumed by discharging of Qoss. This becomes the energy loss Eoss, which is the Qoss
loss of one switching cycle.

Fig. 5-3. Explanation of switching operation concerning Coss and Qoss. [84] Copyright(2018) The Japan Society of Applied Physics.

134

Fig. 5-4(a) and (b) show the calculated Qoss–Vds and Eoss–Vds curves compared with
TCAD simulation results, for the D-MOSFET and the FP-MOSFET, respectively. Eachactive area was designed for the same RON of 10 m.
These modeled curves corresponded well qualitatively to TCAD curves. In an
application circuit for 100-V-rating device, an input voltage (VIN) of 50 V is assumed
generally. In the comparison between the modeled Qoss and the TCAD results at Vds = 50
V, only 6 and 7% errors were seen for the FP-MOSFET and D-MOSFET, respectively. In
addition, in the case of the Eoss, there were 5 and 10% errors for the FP-MOSFET and DMOSFET, respectively. Therefore, it is recognized that these results are sufficient to use
for power loss analysis.

(a)

(b)

Fig. 5-4. (a) Qoss–Vds and (b) Eoss–Vds curves calculated using proposed model comparedwith TCAD results for 100-V-class D-MOSFET and FP-MOSFET. Each active area isdesigned for the same RON of 10m. [83] [84] Copyright (2018) The Japan Society of Applied
Physics.

135

Crss–Vds curves
As additional validation data, the calculated Crss–Vds curves compared with TCAD
simulation results for the D-MOSFET and the FP-MOSFET, respectively, are shown in
Fig. 5-5(a) and (b). Each active area was designed for the same RON of 10 m. In both Vds
linear scale (Fig. 5-5(a)) and Vds log scale (Fig. 5-5(b)), the Crss curves of the D-MOSFET
corresponded well qualitatively to TCAD results. However, there were relatively large
errors with the maximum of 32% at approximately Vds = 0.1 and 10 V. The reason was
the same as in the case of Coss modeling, as mentioned in subsection 5.1.1. On the other
hand, in the case of the Crss curves of the FP-MOSFET, errors of less than 10% were seen
at Vds ≤ 1 V, and errors of less than 35% were seen at 1 V < Vds ≤ 10 V. However, larger
errors occurred in the high-Vds region because of the small value of Cgd, which isapproximately two to three orders of magnitude lower than Coss, as mentioned insubsection 4.3.6.

(a)

(b)

Fig. 5-5. (a) Crss–Vds curves calculated using proposed model compared with TCAD
results for 100-V-class D-MOSFET and FP-MOSFET. (a) Vds linear scale and (b) Vds log
scale in X-axis. Each active area is designed for the same RON of 10m [84] Copyright(2018) The Japan Society of Applied Physics.

136

Gate–drain charge (Qgd)
By using the proposed model, the gate–drain charge Qgd is calculated as
𝑄𝑔𝑑 = ∫ 𝐶𝑟𝑠𝑠 (𝑉𝑑𝑠 )𝑑𝑉(5-4)

Fig. 5-6 show the calculated Qgd–Vds curves compared with TCAD simulation results,
for the D-MOSFET and the FP-MOSFET, respectively. Each active area was designed
for the same RON of 10 m. These modeled curves corresponded well qualitatively to
TCAD curves. In an application circuit for 100-V-rating device, an input voltage (VIN) of
50 V is assumed generally. In the comparison between the modeled Qdg and the TCAD
results at Vds = 50 V, 15 and 11% errors were seen for the FP-MOSFET and the DMOSFET, respectively. Although these errors are relatively large, it is possible that thecalculated results are used for power loss analysis for the FP-MOSFET because theabsolute value of the Qgd is approximately one order of magnitude lower than the Qoss.

Fig. 5-6. Qgd–Vds curves calculated using proposed model compared with TCAD resultsfor 100-V-class D-MOSFET and FP-MOSFET. Each active area is designed for the same

RON of 10 m.

137

Switching waveforms
Turn-off switching waveform can be simply calculated using the Crss model. During
the turn-off period, the gate voltage Vgs is maintained as the mirror voltage, the gate
current Ig is constant, and the Crss (Cgd) is charged by the Ig. On the other hand, the Vds
is varied by dVds/dt and increases to the input voltage VIN. Thus the Ig is given by
𝐼𝑔 = 𝐶𝑟𝑠𝑠 (𝑉𝑑𝑠 )

𝑑𝑉𝑑𝑠
.
𝑑𝑡

(5-5)

In this period, time t is expressed by using dVds/dt as below
𝑡=∫

𝑑𝑡
𝑑𝑉.
𝑑𝑉𝑑𝑠

(5-6)

Therefore, the turn-off time toff is given by
𝑉𝐼𝑁

𝑡𝑜𝑓𝑓 = ∫0

𝐶𝑟𝑠𝑠 (𝑉𝑑𝑠 )
𝑑𝑉 .
𝐼𝑔

(5-7)

Fig. 5-7(a) and (b) are the calculated turn-off switching waveforms for the DMOSFET and the FP-MOSFET, respectively, under the conditions of VIN = 50 V, on-state
current ION = 10 A, gate resistance Rg = 1.5 , and Ig = 0.83 A. As a result, toff = 18.5 ns
for the D-MOSFET and toff = 1.1 ns for the FP-MOSFET were calculated using the
proposed model. In the calculation, gate–source charge (Qgs), circuit resistance (Rc), andstray inductance (Ls) are not considered.

(a)

(b)

Fig. 5-7. Turn-off switching waveforms calculated using proposed model for (a) DMOSFET and (b) FP-MOSFET. VIN = 50 V, ION = 10 A, Rg = 1.5 , and Ig = 0.83 A. [84]Copyright (2018) The Japan Society of Applied Physics.

138

Application to other FP-MOSFET structures
As mentioned above, the proposed model for the slant FP-MOSFET was validated.
In the case of the conventional flat FP-MOSFET structure, which has a nearly uniform
field-plate oxide thickness, the model may be applied. In particular, the results ofcalculation of Eqs. (4-17) and (4-26) change depending on both TFPOX_t and TFPOX_b. In a
future work, a wider application range of the proposed model has to be investigated.

139

60-V-class SFP-MOSFET and GFP-MOSFETIn section 4.4, the comparison of SFP-MOSFET and GFP-MOSFET models were
described. The calculated characteristics, using the capacitance model shown in Table
4-10 and the parameters shown in Table 4-8, are validated in the following. [87]Coss–Vds and Crss–Vds curves
Fig. 5-8(a) and (b) show the Coss–Vds and Crss–Vds curves calculated using proposedmodel compared with TCAD results, for 60-V-class SFP-MOSFET and GFP-MOSFET.
As shown in Table 4-10, there are the following equivalent relations: Cds1 SFPMOS = Cds
GFPMOS, Cds2 SFPMOS = Cgd2 GFPMOS, Crss SFPMOS = Cgd1 GFPMOS, and Coss SFPMOS = Coss GFPMOS.

Here, Cds3 and Cgd3, which are trench bottom capacitances, are simply calculated as 0.59
nF/cm3, however, they are recognized negligible small.
In the Coss–Vds curves, it was confirmed that the calculated results showed good
agreement qualitatively to TCAD simulation except for higher voltage region (> 50 V).
Numerically, error of 38% were seen at Vds = 30 V. On the other hand, in the Crss–Vds
curve of the SFP-MOSFET, errors of less than 5% were seen at Vds ≤ 15 V. However,larger errors occurred in the high-Vds region because of the small value of Cgd, which isapproximately two orders of magnitude lower than Coss, as mentioned in subsection 5.1.1.

(a)

(b)

Fig. 5-8. (a) Coss–Vds and Crss–Vds curves calculated using proposed model comparedwith TCAD results for 60-V-class SFP-MOSFET. (b) Coss–Vds and Crss–Vds curves
calculated using proposed model compared with TCAD results for 60-V-class GFPMOSFET. [87]140Output charge (Qoss) and stored energy (Eoss)
To calculate power loss in same condition as described later, an active area of the
SFP-MOSFET and the GFP-MOSFET were defined to 6.06 mm2 and 4.83 mm2,
respectively, to achieve same RON of 1.8 m (cf. Eq. (5-1)). The RONA of the GFP-MOSFET
is 20% lower than that of the SFP-MOSFET as described in subsection 4.4.1, therefore
the smaller active area can be realized for the GFP-MOSFET.
Fig. 5-9 (a) and (b) show the calculated Qoss–Vds and Eoss–Vds curves (using Eqs. (52) and (5-3)) compared with TCAD simulation results, for the SFP-MOSFET and the
GFP-MOSFET, respectively. It was obviously that both Qoss and Eoss could be lower in
the GFP-MOSFET due to the smaller active area. In addition, those values corresponded
very well to those of TCAD results. In the SFP-MOSFET, numerically, errors of 7 and 8%
were seen at Vds = 30 V for the Qoss and Eoss, respectively. Also in the GFP-MOSFET,
numerically, errors of 7 and 8% were seen at Vds = 30 V for the Qoss and Eoss, respectively.

(a)

(b)

Fig. 5-9. (a) Qoss–Vds and (b) Eoss–Vds curves calculated using proposed model comparedwith TCAD results for 60-V-class SFP-MOSFET and GFP-MOSFET. Each active area
is designed for the same RON of 1.8 m. [87]141Gate–drain charge (Qgd)
Fig. 5-10 shows the calculated Qgd–Vds curves (using Eq. (5-4)) compared with TCAD
simulation results, for the SFP-MOSFET and the GFP-MOSFET, respectively. Eachactive area was designed for the same RON of 1.8 m. The calculated curves corresponded
well qualitatively to TCAD results. In an application circuit for 60-V-rating device, theinput voltage (VIN) of 30 V is assumed generally. In the comparison between the modeledQdg and the TCAD results at Vds = 30 V, 2.5 and 8.6% errors were seen for the SFPMOSFET and the GFP-MOSFET, respectively. It is recognized that these results are
sufficient to use for power loss analysis for both FP-MOSFETs.

Fig. 5-10. Qgd–Vds curves calculated using proposed model compared with TCAD resultsfor 60-V-class SFP-MOSFET and GFP-MOSFET. Each active area is designed for thesame RON of 1.8 m.

142

Switching waveforms
Simplified turn-off waveforms could be calculated by using the Crss model. Under
the condition of Vds=30 V as the VIN and the drain current Id = 70 A, the toff in Eq. (5-7)
of the SFP-MOSFET was less than one-tenth of that of the GFP-MOSFET, as shown in
Fig. 5-11 (a) and (b). High speed turn-off property of the SFP-MOSFET, which is due tothe small Crss (Fig. 5-8) and small Qgd (Fig. 5-10), was expressed in the switching
waveforms.

(a)

(b)

Fig. 5-11. Turn-off switching waveforms calculated using proposed model for (a) SFPMOSFET and (b) GFP-MOSFET. VIN = 30 V, ION = 70 A, Rg = 3 , and Ig = 0.83 A. [87]143Case study for cell pitch shrinking of 100-V-class FP-MOSFETAs other case study, the characteristics regarding the WCell shrinking of the 100-Vclass FP-MOSFET are validated. The capacitance model shown in Table 4-5 and thecommon parameters shown in Table 4-7 are used in the following calculation.

Coss–Vds curves
In the FP-MOSFET, the WCell can be shrunk by narrower WT or narrower WMesa.
Regarding the proposed capacitance model described in sections 4.3 and 4.4, it isnecessary to take the parameters of the mesa region into account. Here, the WCell isshrunk from 3.0 to 2.0 m by changing the WMesa from 1.5 to 0.5 m.
Fig. 5-12 and Fig. 5-13 are WCell dependences of Coss–Vds curve calculated using
proposed model compared with TCAD results for 100-V-class FP-MOSFETs. It is notedthat Cds3, which is the trench bottom capacitance, is not calculated in this validation,
because Coss–Vds beyond 50 V does not need to the Qoss calculation. In the comparison of
those Coss–Vds curves, it can be seen that the TCAD results and the calculated results
are good agreement.

Coss and Qoss
Table 5-1 shows TCAD simulated basic characteristics (VB, RONA, Coss and Qoss) andcalculated Coss and Qoss by proposed model for 100-V-class FP-MOSFETs, when the WCellvaries from 3.0 to 2.0 m. As the accuracy of the model, errors of less than 10% and 8%
are confirmed for the Coss and Qoss, respectively. There is not significant problem in thecase of the narrow WMesa calculation, up to 0.5 m.

144

Fig. 5-12. WCell dependences of Coss–Vds curve calculated using proposed modelcompared with TCAD results for 100-V-class FP-MOSFETs. WCell is shrunk from 3.0 to
2.6 m by changing WMesa from 1.5 to 1.1 m. In each row, left figure shows Vds linear
scale and right figure shows Vds log scale in X-axis.

145

Fig. 5-13. WCell dependences of Coss–Vds curve calculated using proposed modelcompared with TCAD results for 100-V-class FP-MOSFETs. WCell is shrunk from 2.4 to
2.0 m by changing WMesa from 0.9 to 0.5 m. In each row, left figure shows Vds linear
scale and right figure shows Vds log scale in X-axis.

146

Table 5-1. TCAD simulated basic characteristics and calculated Coss and Qoss by proposedmodel for 100-V-class FP-MOSFETs. Other necessary parameters except WCell, WT, WMesa
and ND are the same as those of Table 4-7.
WCell

WT

WMesa

ND

(m)

(m)

(m)

(atoms/cm3)

3.0
2.8
2.6
2.4
2.2
2.0

1.5
1.5
1.5
1.5
1.5
1.5

1.5
1.3
1.1
0.9
0.7
0.5

2.20 × 1016
2.54 × 1016
3.00 × 1016
3.67 × 1016
4.71 × 1016
6.60 × 1016

VB

RONA

Coss/A

Qoss/A

Coss/A

Qoss/A(V)(m·mm2)(pF/mm2)(nC/mm2)(pF/mm2)(nC/mm2)

Vgs=10V

Vds=50V

Vds=50V

Vds=50V

Vds=50V

TCAD

TCAD

TCAD

TCAD

model

model

112.9
111.6
110.1
108.2
105.7
102.5

37.5
35.0
32.8
30.8
29.1
28.2

58.7
60.6
62.5
64.5
66.6
68.7

8.14
8.72
9.39
10.2
11.1
12.2

59.7
59.8
59.7
59.5
65.8
75.9

8.17
8.62
9.16
9.71
10.4
11.3

Summary
In chapter 5, the accuracy of the model that derived in chapter 4 was validated.
Firstly, drain voltage dependences of Coss and Crss, for 100-V-class D-MOSFET and slant
FP-MOSFET, were calculated. Then, 60-V-class GFP-MOSFET and SFP-MOSFET werealso calculated. Moreover, the cell-pitch shrinking of the 100-V-class FP-MOSFET werestudied. The calculated capacitance curves by the proposed model indicated good
agreement with the results of TCAD simulation. In addition, output charge Qoss, stored
energy Eoss, and turn-off switching time, which are necessary for the switching loss
analysis, were calculated from the proposed model and were illustrated.

147

POWER LOSS ANALYSIS FOR THE LATEST FP- MOSFETS
100-V-class D-MOSFET and FP-MOSFET 9
Assuming circuit and power loss components
As a comprehensive evaluation of the proposed model, we estimated the power loss
assuming a low-side MOSFET of a buck converter circuit for the D-MOSFET and FPMOSFET, described in section 5.1 [84]. Each active area was designed for the same RONof 10 m. The operation conditions were VIN = 50 V, output current IO = 10 A, duty ratio

D = 80%, and switching frequency fSW = 100 kHz to 2 MHz. Here, the calculated
conduction loss PCON, turn-off loss PSW(off), and output charge loss PQoss are given by
𝑃𝐶𝑂𝑁 = 𝐼𝑂 2 𝑅𝑂𝑁 𝐷,
𝑡𝑜𝑓𝑓

𝑃𝑆𝑊(𝑜𝑓𝑓) = 𝑓𝑆𝑊 ∫(6-1)

𝐼𝑂 𝑉𝑑𝑠 𝑑𝑡,(6-2)

𝐶𝑜𝑠𝑠 (𝑉𝑑𝑠 )𝑉𝑑𝑠 𝑑𝑉 .

(6-3)

0

𝑉𝐼𝑁

𝑃𝑄𝑜𝑠𝑠 = 𝑓𝑆𝑊 𝐸𝑜𝑠𝑠 = 𝑓𝑆𝑊 ∫0

Power loss estimation by the proposed model
As shown in Fig. 6-1(a) and (b), all PCON values were constant at 0.8 W in both
MOSFETs because of the same RON. PSW(off) was greatly influenced by Crss. Thus, in the
D-MOSFET, PSW(off) was the most dominant component and increased to 7.56 W at 2 MHz,because of the large RON·Crss, as shown in Table 4-3. On the other hand, in the FPMOSFET, the total power loss was drastically suppressed by the low RON·Crss, as shownin Table 4-6, and was mainly increased by PQoss, which depended on fSW. This analysis
reveals that PQoss may become a significant issue in the case of high-frequency operation,in not only the latest FP-MOSFETs but also next generation FP-MOSFETs.

9

Section 6.1 is reproduction of [84] section 4.3, Copyright (2018) The Japan Society of Applied Physics,
and a part of description is modified.

148

(a)

(b)

Fig. 6-1. Estimated power losses for 100-V-class (a) D-MOSFET and (b) FPMOSFET,
assuming 50-V input, 10-A output, 80% duty ratio, and 100 kHz–2 MHz switching
operation. Each active area is designed for the same RON of 10 m. [84] (modified).

149

60-V-class SFP-MOSFET and GFP-MOSFET 10
Assuming circuit and power loss components
Utilizing the proposed model, main power loss in assumption of an automotive
application circuit can be estimated. In the automotive use, there are various
specifications of power MOSFETs. For example, 40-V, 60-V and 100-V-rating products
are used for 12-V, 24-V and 48-V battery systems. Output current ratings of 5–200 A are
needed for various sized motor drive. Though switching frequency (fSW) depends on
applied circuit block, 10–100 kHz operation is general. In this subsection, 60-V-class
SFP-MOSFET and GFP-MOSFET described in section 5.2 are compared each other [87].
Power loss estimation by the proposed model for high frequency use
In the case of 30-V supply voltage, 50-A load current, and 50% duty ratio, the power
loss related to the FP-MOSFET’’s features were estimated in various fSW ranged from 20
to 200 kHz, as shown in Fig. 6-2 (a) and (b). The PCON was constant because of same RON
for both devices. In contrary, the PSW(off) which was component of the PSW increased
depending on the fSW, especially in the GFP-MOSFET. In the SFP-MOSFET which hadvery low Crss, total power loss was affected by neither Poff nor PQoss in this frequency(a)(b)
Fig. 6-2. Estimated power
losses for 60-V-class (a) SFP-MOSFET
and (b) GFPMOSFET, assuming 30-V input, 50-A output, 50% duty ratio, and 20–200 kHz switching
operation. Each active area is designed for the same RON of 1.8 m.
[87] (modified).
10

Section 6.2 is reproduction of [87] section 4.2, and a part of description is modified andcomprehensive explanations are additionally provided.

150

range. Therefore, it is obvious that the SFP-MOSFET has great advantage comparedwith the GFP-MOSFET in the case of 1.8-m class product.
Moreover, the power loss of the fSW ranged from 200 kHz to 2 MHz were estimatedfor reference. In the GFP-MOSFET shown in Fig. 6-3(b), the PSW(off) increased extremely
depending on the frequency, and reached to 95 W in fSW = 2 MHz. On the other hand, in
the SFP-MOSFET shown in Fig. 6-3(a), although both PSW(off) and PQoss increased
continuously depending on the frequency, total power loss was suppressed to double of
the PCON even in the case of fSW = 2 MHz. It was additionally confirmed that the SFPMOSFET was appropriate device for mega-hertz-switching application.

(a)

(b)

Fig. 6-3. Estimated power losses for 60-V-class (a) SFP-MOSFET and (b) GFPMOSFET, assuming 30-V input, 50-A output, 50% duty ratio, and 200 kHz–2 MHz
switching operation. Each active area is designed for the same RON of 1.8 m.
[87] (modified).

151

Power loss estimation by the proposed model for low current use
In the case that the fSW is low or the load current is low, which means an applicationthat ultralow RON is not necessary, the power loss is additionally analyzed.
Fig. 6-4(a) show the active area dependence of the power losses for 60-V-class SFPMOSFET and GFP-MOSFET in fSW ranged from 20 to 200 kHz. Those were calculated
under the condition of 30-V supply voltage, 70-A load current, and 50% duty ratio.
Especially in the GFP-MOSFET, the larger the active area, the higher the PSW(off), which
could be predicted by Fig. 6-2(b). In the case of smaller active area for both FP-MOSFETs,the total power loss continuously went up due to the PCON increase, which was natural
understanding for the higher RON. That could be also seen in Fig. 6-4(b).
Meanwhile, in a circuit block which does not need ultralow RON, a power MOSFET
product of as low cost as possible is selected in a viewpoint of total system cost. For
example, as shown in Fig. 6-4(c), when the fSW was 20 kHz, 3.7-mm2 active area whichcorresponds to 2.35 m was boundary for the device selection. Likewise, there would beselectable area under 2.3-mm2 (corresponds to 3.78 m) in 50 kHz and under 1.65-mm2(corresponds to 5.27 m) in 100 kHz. In those case, the GFP-MOSFET, which active area
is 20% smaller than that of the SFP-MOSFET, would be preferred (cf. Table 4-9).

152

(a)

(b)

(c)
Fig. 6-4. (a) Active area dependence of power losses for 60-V-class SFP-MOSFET and
GFP-MOSFET in fSW ranged from 20 to 200 kHz, 30-V supply voltage, 70-A load
current, and 50% duty ratio. (b) Distinguished to individual losses in 20 kHz. (c)Enlarged view of small active area (< 5 mm2). [87] (modified).

153

Summary
In chapter 6, the power loss analysis of the slant FP-MOSFET by the proposed
capacitance model was carried out. The power loss calculation that assumed a 100-Vrating device application was performed, and it was confirmed that the performance ofthe slant FP-MOSFET was superior in high-frequency switching up to 2 MHz.
In addition, the power loss of the 60-V-rating device application was calculated.
Source connection field-plate structure (SFP-MOSFET) was effective to a high-current
and high-frequency switching use (e.g., 20 kHz–2 MHz). On the other hand, in viewpointof the device cost, gate connection field-plate structure (GFP-MOSFET) was effective toa low-current use (which means an application that ultralow RON is not necessary). The
active area of the GFP-MOSFET can make 20% reduction compared to that of the SFPMOSFET, because of the advantage of the small RONA. Moreover, when the application
is not high-frequency switching use, the GFP-MOSFET would be very effective as thehigh-current use.

154

PROPOSAL OF ULTIMATE STRUCTURE
EFFICIENCY POWER MOSFET

FOR

HIGH

As high performance LV-MOSFETs, many R&D achievement for the SJ-UMOSFET
and the FP-MOSFET have been reported this decade. It is considered this trend
advancing toward so-called “ultimate MOSFET” [88] as low-voltage silicon power device.
As one of the approach for the ultimate structure realization, the slant FP-MOSFET thatis extremely close to ideal gradient oxide structure was described in section 3.3. Moreover,the structure-based on-resistance models and capacitance models were described in
sections 3.3, 4.3, and 4.4.
In this chapter, firstly, a limit of the FP-MOSFET structure is considered.
Subsequently, the limitations for structural, electrical, and physical parameters arestudied regarding a realistic limit and an ultimate limit. Finally, the performances ofboth realistic limit and ultimate limit of the FP-MOSFET are predicted.

Assumptions for ultimate structure proposal of FP-MOSFETFirstly, as the general power loss in a switching circuit, only conduction loss PCON
and output charge loss PQoss are considered because other power loss components are
independent from the drift layer structure. Thus total power loss PLoss is expressed as
𝑃𝑇𝑜𝑡𝑎𝑙 ≈ 𝑃𝐶𝑂𝑁 + 𝑃𝑄𝑜𝑠𝑠 .

(7-1)

Secondly, PCON is determined by RONA, as shown in Eq. (6-1) , therefore, a limit
structural parameter to minimize the RONA is considered. In the FP-MOSFET structure,

RAA and RSUBA can be ignored because those are independent from the VB design. Thusa limit RONFPMOSA is determined as
𝑅𝑂𝑁 𝐹𝑃𝑀𝑂𝑆 A ≈ 𝑅𝐶𝐻 𝐴 + 𝑅𝐷 𝐴.

(7-2)

Thirdly, PQoss is calculated by Coss–Vds characteristic, as shown in Eq. (6-3), therefore,
a limit structural parameter to minimize the Qoss (or the Eoss) is considered. In the FPMOSFET structure, Cgd can be ignored, because it is independent from the VB design. In
addition, Cds3 can be also ignored, because trench bottom region is cut in ultimate design.
Thus a limit CossFPMOS is determined as
𝐶𝑜𝑠𝑠 𝐹𝑃𝑀𝑂𝑆 ≈ 𝐶𝑑𝑠1 + 𝐶𝑑𝑠2 .

155

(7-3)

Finally, regarding the VB, it assumes that an ideal rectangular distribution of thevertical electric field Ey of the drift layer can be achieved (cf. Fig. 3-21(a)). That means
field coefficient  is 1 (cf. Eq. (3-40)). Moreover, the buffer layer TBUF is not necessary (cf.
Eq. (3-25)). Thus the VB is obtained as
𝑉𝐵 = 𝐸𝐶 𝐿𝐷 ,(7-4)

(𝐸𝑦 = 𝐸𝐶 ).

In real products, the target VB is designed to add the rated-voltage of the drain (VDSS).
For example, in the case of the VDSS of 100 V, the target VB is designed to 110 V including
10% margin. In this assumption, the target VB is decided to 100 V. Actually, the supply
voltage is generally restricted to half of the VDSS in the application circuit.
Fig. 7-1(a) and (b) show structure comparison of the latest slant FP-MOSFET and a
proposed ultimate FP-MOSFET. The proposed ultimate FP-MOSFET does not has n+–
substrate and has very narrow mesa width. Moreover, each structural parameter isscaled down to limit dimension. Even if the mesa width is extremely narrow, n+/p+interactive pattern has to be on the top of the mesa region in order to maintain thestability of the VB.
In next section, each parameter limitation is considered.

(a)

(b)

Fig. 7-1. Schematic cross sections of (a) the latest slant FP-MOSFET and (b) proposed
ultimate FP-MOSFET.
156

Consideration of each parameter limitation
MOS channel and p–base region
Rated-voltage of gate VGSS and gate oxide thickness TGOX
When the gate oxide thickness TGOX is designed, the rated-voltage of the gate (VGSS)
and a gate oxide integrity in the process have to be carefully considered. In mature SiO2
process, a dielectric breakdown of SiO2 occurs at an electric-field greater than at least 8
MV/cm, even in the relatively thick oxide film (e.g., 30–50 nm) of the power device [40][75]. If the necessary VGSS is 20 V, i.e., required for the automobile battery use, the TGOX
is designed to 50 nm by the following design concept,
𝑇𝐺𝑂𝑋 =

2 × 𝑉𝐺𝑆𝑆= 50 (𝑛𝑚).
8 × 106 (𝑉/𝑐𝑚)(7-5)

Here, 2× in the denominator means a safe design of the gate oxide to guarantee longterm reliability. Actual dielectric breakdown voltage is greater than 40 V under thecondition of TGOX = 50 nm. As according to the gate-drive voltage Vgs of 5 V that is generallogic level of CMOS-IC (complementary MOS integrated circuit), the VGSS is defined to 5
V. In this case, the TGOX in this assumption is decided as below.
𝑇𝐺𝑂𝑋 =

2 × 𝑉𝐺𝑆𝑆= 12.5 (𝑛𝑚).
8 × 106 (𝑉/𝑐𝑚)(7-6)

In this condition of TGOX = 12.5 nm, actual dielectric breakdown voltage is greater than
10 V.
Threshold voltage VTH and p–base concentration NA
When the Vgs is fixed as 5 V, the threshold voltage VTH can be lowered from 2.0 to
1.0 V. The VTH is defined by the following.

𝑉𝑇𝐻 = 𝑉𝐹𝐵 + 𝜓𝑠 +√2𝜀𝑆𝑖 𝜀0 𝑞𝑁𝐴 𝜓𝑠,
𝐶𝐺𝑂𝑋

𝑉𝐹𝐵 = 𝜙𝑚𝑠 −

𝑄𝑓
,
𝐶𝐺𝑂𝑋

157

(7-7)

(7-8)

𝜓𝑠 =

2𝑘𝑇
𝑁𝐴
ln ( )𝑞𝑛𝑖(7-9)

Here, VFB is flat band voltage, S is surface potential in strong inversion case, ms is work
function difference, and Qf is fixed oxide charge. From the text book [89], ms = −1.02 V
for n+–poly-Si on p–Si of NA = 5×1017 atoms/cm3 and Qf = q×5×1011 C are used for the VTH
calculation. By substituting TGOX of 12.5 nm, NA of 5×1017 atoms/cm3, and the calculated
results of Eqs. (7-8)–(7-9) into Eq. (7-7), the VTH is obtained as 0.95 V. It is noted that theNA has to be increased according to the TGOX thinning, despite of the VTH lowering.
Channel length LCH
To investigate a possibility of the channel length LCH shortening, a depletion layer
width is calculated in the case of the increased NA and ND conditions. The LCH has to belonger than a depletion width of p–base layer side, to prevent the VB degradation by thepunch-though phenomenon.
When the maximum voltage, which equals to the VDSS, applies to drain–source, a
depletion layer expands at p–base and n–drift junction. The depletion layer Wdep_pn isgiven by the following,

2𝜀𝑆𝑖 𝜀0 𝑁𝐴 + 𝑁𝐷
𝑊𝑑𝑒𝑝_𝑝𝑛 = √∙() ∙ (𝑉𝑏𝑖 + 𝑉𝑑𝑠 ).
𝑞
𝑁𝐴 𝑁𝐷(7-10)On the other hand, the depletion layer mainly expands to lightly-doped concentrationside that is the n–drift layer. The depletion layer width of the n–drift layer side Wdep_n isexpressed as,

2𝜀𝑆𝑖 𝜀0
𝑊𝑑𝑒𝑝_𝑛 = √∙ (𝑉𝑏𝑖 + 𝑉𝑑𝑠 ).
𝑞𝑁𝐷(7-11)

Accordingly, a depletion layer, which expands to the p–base layer side, Wdep_p isestimated as the following,
𝑊𝑑𝑒𝑝_𝑝 = 𝑊𝑑𝑒𝑝_𝑝𝑛 − 𝑊𝑑𝑒𝑝_𝑛(7-12)

By substituting NA of 5×1017 atoms/cm3 and ND of 4.23×1017 atoms/cm3 into Eqs. (7-10)–(7-12), the Wdep_p is obtained as 0.20 m. Therefore, it can assume that the LCH is158

shortened to approximately 0.2 m. It is noted that the increased ND will be derived by
the following subsection 7.2.2.3.
Field-plate and n–drift region
Drift layer length LD
As mentioned the above, since the target VB is 100 V, EC is calculated by Eq. (3-41).
𝐸𝐶 = 8.2 × 105 ∙ 𝑉𝐵 −0.2 = 3.26 × 105 (𝑉/𝑐𝑚)(7-13)

When  is 1, the necessary LD is calculated by Eqs. (7-4) and (7-13).
𝐿𝐷 =𝑉𝐵= 3.06 × 10−4 (𝑐𝑚) = 3.06 (𝜇𝑚)𝐸𝐶

(7-14)

Here, LD includes the field-plate length LFP, the bottom thickness of the field-plate oxide

TFPOX_c. and the distance between the p–base layer and the upper position of the fieldplate.
Mesa width WMesa
To decide a mesa width WMesa limit, a necessary width in the channel region isconsidered in the case of the increased NA conditions. When the interface between thegate oxide and the p–base surface is strong inversion case, a depletion layer Wd_inv, whichwidth is greater than the inversion layer width (~10 nm), expands to the p–base surfaceof the mesa region. Wd_inv is given by the following.

2𝜀𝑆𝑖 𝜀0 𝜓𝑠
𝜀𝑆𝑖 𝜀0 𝑘𝑇
𝑁𝐴
𝑊𝑑_𝑖𝑛𝑣 = √= 2√ 2ln ( )
𝑞𝑁𝐴
𝑞 𝑁𝐴𝑛𝑖(7-15)

When the NA is 5×1017 atoms/cm3, the Wd_inv is obtained as 0.048 m (48 nm). Therefore,
it can be considered that the WMesa limit is approximately 0.1 m.

159

Drift layer concentration ND
Optimum charge density QOpt in the mesa region (cf. Eq. (3-43)) is re-calculated by
the above EC.
𝑄𝑂𝑝𝑡 =

2𝐸𝐶 𝜀𝑆𝑖 𝜀0= 4.23 × 1012 (𝑎𝑡𝑜𝑚𝑠/𝑐𝑚2 ).
𝑞(7-16)

Then, when the WMesa is assumed to 0.1 m, the ND is calculated as
𝑁𝐷 =

𝑄𝑂𝑝𝑡
4.15 × 1012=
= 4.23 × 1017 (𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3 ).
𝑊𝑀𝑒𝑠𝑎
1.0 × 10−5

(7-17)

Electron mobility of n–drift layer n_D
It is known that the electron mobility is varied by the doping concentration in silicon.
From the text book [86], an electron mobility of n–drift layer n_D at room temperature
as a function of the ND is given by the following.
𝜇𝑛_𝐷 =

5.10 × 1018 + 92𝑁𝐷 0.91
3.75 × 1015 + 𝑁𝐷 0.91

(7-18)

Field-plate oxide thickness TFPOXAs the field-plate oxide thickness TFPOX of the 100-V-class FP-MOSFET, 580-nm
thick is confirmed to achieve VB of over 110 V [72], as described in subsection 3.3.3.4. If
an insulator of low dielectric constant is adopted instead of the current field-plate oxide(SiO2), the TFPOX can be thinned. The low dielectric constant insulator is called low-k
dielectric film. Here, the dielectric constant of a low-k dielectric film is i.
For example of the low-k material, carbon doped SiO2 (SiOC), which can be formedby plasma enhanced chemical vapor deposition (PECVD), has been developed to utilize
for back end of line (BEOL) process of ultra-large-scale integrated circuit (ULSI) in the
2000s [90] [91] [92] [93]. Objective of the low-k SiOC was to decrease the metal interlayer
capacitance of the ULSI in the 90–32 nm technology node, and low-k properties of i =2.0–2.9 were actually realized. However, it is noted that such a low-k material isrestricted to relatively low temperature process, e.g., less than approximately 400
degrees Celsius.
160

If a material of i = 2.0 is adopted in the FP-MOSFET process, the TFPOX can bethinned as below.
𝑇𝐹𝑃𝑂𝑋 = 580 ×

𝜀𝑖= 297 (𝑛𝑚).
𝜀𝑂𝑋(7-19)

Therefore, the TFPOX limit can be designed to 300 nm.
In addition, as an ultimate low-k material, if the field-plate oxide were replaced toan air-gap (i = 1.0) in a future process technology, the TFPOX can be thinned to 150 nm
as below.
𝑇𝐹𝑃𝑂𝑋 = 580 ×

𝜀𝑖= 149 (𝑛𝑚).
𝜀𝑂𝑋

161

(7-20)

Prediction of realistic/ultimate limit of FP-MOSFET performance
Structural, electrical, and physical parameters
Based on the consideration of each parameter limitation in section 7.2, necessary
parameters to predict both realistic limit and ultimate limit for 100-V-class FP-MOSFET
are shown in Table 7-1 and Table 7-2.

Table 7-1. Representative structural parameters of 100-V-class slant FP-MOSFETs topredict realistic limit and ultimate limit.
Symbol

WCell
WT
WMesa
LCH
LA
TGOX
NA
TFPOX_t
TFPOX_b
TFPOX_c
LFP
LDCell width

2.60

Trench width

1.50

Realisticlimit
𝑊𝑇 + 𝑊𝑀𝑒𝑠𝑎
2 × 𝑇𝐹𝑃𝑂𝑋_𝑏

Mesa width

1.10

𝑊𝑀𝑒𝑠𝑎

𝑊𝑀𝑒𝑠𝑎

m

Channel length

0.30

0.20

0.20

m

Accumulation length

0.10

0

0

Gate oxide thickness
p–Base layer
concentration
Field-plate oxide
thickness (top)Field-plate oxide
thickness (bottom)
Field-plate oxide
thickness (center)
Field-plate length

50

12.5

12.5

m
nm

2.0 × 1017

5.0 × 1017

5.0 × 1017

atoms/cm3

100

100

100

nm

580

580 ×

580

N/A

Parameters

n–Drift layer length

Currenttechnology𝜀𝑖
𝜀𝑂𝑋Ultimatelimit
𝑊𝑇 + 𝑊𝑀𝑒𝑠𝑎
2 × 𝑇𝐹𝑃𝑂𝑋_𝑏

580 ×

𝜀𝑖
𝜀𝑂𝑋

Unit
m
m

nm

N/A

nm

4.15

N/A

N/A

m

4.93

3.06
𝑄𝑂𝑝𝑡
𝑊𝑀𝑒𝑠𝑎

3.06
𝑄𝑂𝑝𝑡
𝑊𝑀𝑒𝑠𝑎

m

ND

n–Drift layer
concentration

3.0 × 1016

QOpt

Optimum charge ofn–drift layer

3.3 × 1012

4.23 × 1012

4.23 × 1012

atoms/cm2

0.90

0

0

m

50

0

0

m

TBUF
TSUB

n–Buffer thickness
n+–Substrate
thickness

162

atoms/cm3

Table 7-2. Electrical and physical parameters of 100-V-class slant FP-MOSFETs topredict realistic limit and ultimate limit.
Symbol

VDSS
VB

VGSS
Vgs
VBD
VTH
VON
ni
n_D
OX
i

Parameters
Rated-voltage ofdrain
Target breakdown
voltage of drain
Field coefficient
Rated-voltage of gate
Gate-drive voltage
Minimum dielectric
breakdown voltage
Threshold voltage
On-state voltage
Electron mobility of
inversion layer
Electron mobility ofn–drift layer
Dielectric constant ofgate oxide (SiO2)
Dielectric constant offield-plate insulator

Currenttechnology

Realistic
limit

Ultimate
limit

Unit

100

100

100

V

110

100

100

V

0.75

1

1

20
5~12

5
5

5
5

V
V

40

10

10

V

2.0
0.10

1.0
0.10

1.0
0.10

V
V

500

500

500

cm2/Vs1096

Depends
on ND

Depends on

3.9

3.9

3.9

3.9

2.0 ~

1.0 ~

163

ND

cm2/VsPredicted performances: RONA and RON·Qoss
As mentioned in section 7.1, RONA is calculated by sum of RCHA in Eq. (3-27) and

RDA in Eq. (3-30). Because both LA and TBUF are zero, RDA is simplified by Eq. (3-32) as
below.
𝑅𝐷 𝐴 = 𝑅𝐷1 𝐴 =

𝑊𝐶𝑒𝑙𝑙
𝜌 𝐿
𝑊𝑀𝑒𝑠𝑎 𝐷 𝐷

(7-21)

By substituting Eq. (2-12) into Eq. (7-21),
𝑅𝐷 𝐴 =𝐿𝐷

𝑊𝐶𝑒𝑙𝑙.
𝑞𝜇𝑛_𝐷 𝑁𝐷 𝑊𝑀𝑒𝑠𝑎(7-22)

Likewise, as mentioned in section 7.1, Coss/A is calculated by sum of Cds1 and Cds2 asshown in Table 4-7. Moreover, Qoss/A and Eoss/A are derived by Eqs. (5-2) and (5-3).
In the realistic/ultimate limit calculation, WT is given by 2×TFPOX_b as shown in Table
7-1. Thus, an optimum WCell is found out by changing WMesa. Fig. 7-2 (a)–(c) show the

WCell dependences of RONA, Qoss/A, and RON·Qoss for realistic limit and ultimate limit
prediction of 100-V-class slant FP-MOSFETs. Those prediction is compared with a 2.6m-pitch FP-MOSFET, which can be fabricated by current technology (cf. Table 3-7 andTable 4-5). The RONA reaches minimum at WCell = 0.95 m and WCell = 0.55 m, for therealistic limit and the ultimate limit, respectively. The Qoss increase monotonically inthose WCell range. Consequently, RON·Qoss, which is one of the FOMs, is minimized at alarger WCell than that of the RONA. Those are at WCell = 1.55 m and WCell = 1.05 m forthe realistic limit and the ultimate limit, respectively.
Table 7-3 shows calculated RONA, RON·Qoss, and RON·Eoss of 100-V-class slant FPMOSFETs as realistic limit and ultimate limit. Those results are compared with thecurrent technology. As realistic limit, RONA and RON·Qoss are drastically reduced to 5.82m·mm2 and 53.5 m·nC, respectively. Those are 78.2% and 71.5% reduction from thoseof the current technology. In addition, as ultimate limit, RONA and RON·Qoss are
drastically reduced to 3.87 m·mm2 and 49.1 m·nC, respectively. Those are 85.5% and73.8% reduction from those of the current technology.

164

(a)

(b)

(c)
Fig. 7-2. WCell dependences of (a) RONA, (b) Qoss/A, and (c) RON·Qoss for realistic limit andultimate limit prediction of 100-V-class slant FP-MOSFETs. These prediction are using
structural parameters in Table 7-2 and Table 7-1.

165

Table 7-3. Calculated RONA, RON·Qoss, and RON·Eoss of 100-V-class slant FP-MOSFETs as
realistic limit and ultimate limit. (Bold and underline).
SymbolConditions

WCell
RONA
RON·Qoss
RON·Eoss

Vgs = 10 V,
VON = 0.1 V
Vds = 50 V
Vds = 50 V

Currenttechnology

Realistic limit

Ultimate limit

Unit

2.6 m

0.95 m

1.55 m

0.55 m

1.05 m

26.7

5.82

7.04

3.87

5.05

m·mm2

187.5

61.7

53.5

57.6

49.1

m·nC

3.54

0.93

0.71

0.98

0.71

m·J

Fig. 7-3 shows the components of the predicted RONA of 100-V-class slant FPMOSFETs, for the realistic/ultimate limit, comparing with those of the current
technology. The structural and physical parameters, which minimize each RONA, areadopted as shown in Table 7-4.

Fig. 7-3. Components of predicted RONA limit for 100-V-class slant FP-MOSFETs. In
comparison of current technology (Wcell = 2.6 m), realistic limit (Wcell = 0.95 m), andultimate limit (Wcell = 0.55 m). Under the condition of Vgs = 10 V.
166

Table 7-4. Representative structural and physical parameters of 100-V-class slant FPMOSFETs, which minimize RONA, for realistic limit and ultimate limit.
Symbol

WCell
WT
WMesa
LCH
LA
TGOX
NA
TFPOX_t
TFPOX_b
TFPOX_c
LFP
LD
ND
QOpt
TBUF
TSUB
nD
i

Currenttechnology

Realistic
limit

Ultimate
limit

Unit

Cell width

2.60

0.95

0.55

m

Trench width

1.50

0.60

0.30

m

Mesa width

1.10

0.35

0.25

m

Channel length

0.30

0.20

0.20

m

Accumulation length

0.10

0

0

Gate oxide thickness
p–Base layer
concentration
Field-plate oxide
thickness (top)Field-plate oxide
thickness (bottom)
Field-plate oxide
thickness (center)
Field-plate length

50

12.5

12.5

m
nm

2.0 × 1017

5.0 × 1017

5.0 × 1017

atoms/cm3

100

100

100

nm

580

300

150

nm

580

N/A

N/A

nm

4.15

N/A

N/A

m

4.93

3.06

3.06

m

3.0 × 1016

1.21 × 1017

1.69 × 1017

atoms/cm3

3.3 × 1012

4.23 × 1012

4.23 × 1012

atoms/cm2

0.90

0

0

m

50

0

0

m

1096

747

651

cm2/Vs

3.9

2.0

1.0

Parameters

n–Drift layer lengthn–Drift layer
concentration
Optimum charge ofn–drift layer
n–Buffer thickness
n+–Substrate
thickness
Electron mobility ofn–drift layer
Dielectric constant offield-plate insulator

167

Fig. 7-4(a) and (b) show the tradeoff relationship between RON and Qoss of 100-V-classslant FP-MOSFETs, in comparison of the current technology, the realistic limit, and theultimate limit.

(a)

(b)

Fig. 7-4. Prediction of tradeoff relationship between RON and Qoss of 100-V-class slant
FP-MOSFETs. (a) Log scale and (b) linear scale in X-/Y-axis.
In comparison of current technology (Wcell = 2.6 m, RON·Qoss = 187.5 m·nC), realistic
limit (Wcell = 1.55 m, RON·Qoss = 53.5 m·nC), and ultimate limit (Wcell = 1.05 m,

RON·Qoss = 49.1 m·nC).

168

Predicted performances: Power loss
Utilizing the calculated RONA and RON·Qoss of the realistic/ultimate limit for the 100V-class FP-MOSFET, main power loss (MOSFET power loss) in assumption of a 48-V
power supply circuit is additionally predicted. One is a high current automotive
application and the other is high switching frequency power supply.
Power loss in high current automotive application
In the automotive use, 100-V-rating power MOSFETs are used for 48-V battery
systems. High output current over 100 A is required in e.g., an electronic power steering(EPS) or a generator unit. In the case of the three-phase inverter as shown in Fig. 1-8,
the circuit consists of six power MOSFETs (three legs × two MOSFETs), which are ofsame electrical properties. As an assumption for the power loss of one leg, a high-side
MOSFET and a low-side MOSFET, which are turned-on/off alternately with duty ratioof 50%, are studied. The switching frequency (fSW) is defined to 100 kHz. As mentioned
in section 7.1, only PCON and PQoss are considered.

Fig. 7-5. Predicted power loss of 100-V-class FP-MOSFET in high current application.
In comparison of current technology (Wcell = 2.6 m, RONA = 26.7 m·mm2), realistic
limit (Wcell = 0.95 m, RONA = 5.82 m·mm2), and ultimate limit (Wcell = 0.55 m, RONA
= 3.87 m·mm2). Assuming 48-V input, 100-A output, 50% duty ratio, and 100 kHz
switching operation. Each active area is the same as that of current technology FPMOSFET.
169

Results shows in Fig. 7-5. The PCON occupies main loss. It is confirmed that therealistic limit FP-MOSFET can achieve 71.7% reduction and the ultimate limit FPMOSFET can achieve 73.8% reduction, for individual MOSFET. It is noted that eachactive area of the FP-MOSFET is the same as that of current technology FP-MOSFET.
That is, RON of 1.0 m with 26.7 mm2 for the current technology, 0.22 m with 26.7 mm2
for the realistic limit, and 0.14 m with 26.7 mm2 for the ultimate limit.
Power loss in high switching frequency power supply
In the power converter circuit of the distributed power supply as shown in Fig. 1-7,
48-V input, 12-V output, and high frequency switching up to 1 MHz are assumed. This
circuit consists of four power MOSFETs (two legs × two MOSFETs) in primary side.
Corresponding to a step-down ratio VOUT/VIN, each duty ratio for the high-side and thelow-side MOSFETs is determined. In this assumption, those are 25% and 75%,
respectively. As an appropriate output current, 30-A is assumed. As well as the previous
subsection, only PCON and PQoss are considered.
Results shows in Fig. 7-6(a)–(c). In these case, same RON of 3.33 m is designed for
all high-side MOSFETs to obtain the effect of very small Qoss. In addition, same active
area of 8.01 mm2 is designed for all low-side MOSFETs to obtain the effect of ultralow

RONA. Therefore, the PQoss is improved drastically in the high-side and the PCON is
improved drastically in the low-side. As a result, it is confirmed that the realistic limit
FP-MOSFET can achieve 54.0% reduction and the ultimate limit FP-MOSFET canachieve 50.9% reduction, for sum of the high-side and the low-side MOSFETs.
In the case of the above assumption, it is noted that the realistic limit FP-MOSFET
is slightly superior to the ultimate limit FP-MOSFET. This means the realistic limit
structure is sufficiently competitive to the ultimate limit structure. Moreover, it issuggesting that the realizable structure can advance the low-voltage FP-MOSFET
performance in near future.

170

(a)

(b)

(c)
Fig. 7-6. Predicted power losses of 100-V-class FP-MOSFETs in high frequency
application, for (a) high-side, (b) low-side, and (c) sum of high-side and low-side. In
comparison of current technology (Wcell = 2.6 m), realistic limit (Wcell = 1.55 m), andultimate limit (Wcell = 1.05 m). Assuming 48-V input, 12-V/30-A output, 1 MHz
switching operation, and 25%/75% duty ratio for high-side/low-side. Same RON of 3.33
m is designed for high-side and same active area of 8.01 mm2 is designed for low-side.

171

Summary
In chapter 7, by utilizing the RONA model and the capacitance model of the slant FPMOSFET, a realistic limit and an ultimate limit of the low-voltage MOSFET
performance were considered. The proposed ultimate FP-MOSFET does not has n+–
substrate and has very narrow mesa width. Moreover, each structural parameter isscaled down to limit dimension.
As the realistic limit, RONA and RON·Qoss are drastically reduced by 78.2% and 71.5%,
respectively, from those of the current technology. In addition, as the ultimate limit,

RONA and RON·Qoss are more drastically reduced by 85.5% and 73.8%, respectively, fromthose of the current technology.
In the prediction of power loss for the high current automotive application, therealistic and the ultimate limit FP-MOSFETs can achieve 71.7% and 73.8% reduction,
respectively, in the individual MOSFET of the circuit. In the prediction of power loss forthe high switching frequency power supply, it is confirmed that the realistic limit FPMOSFET can achieve 54.0% reduction and the ultimate limit FP-MOSFET can achieve
50.9% reduction, for sum of the high-side and the low-side MOSFETs.
In the assumption, the power loss of the realistic limit is slightly superior to that of
the ultimate limit. This means the realistic limit structure is sufficiently competitive tothe ultimate limit structure. Moreover, it is suggesting that the realizable structure canadvance the FP-MOSFET performance in near future.

172

CONCLUSIONSThe power semiconductor devices are contributing to improve the energy use
efficiency in many electronics applications. In particular, silicon power MOSFETs
categorized into low-voltage and high-frequency application use are still progressing tomeet various market demands. As the device performance that contributes directly tothe efficiency, a low-power-loss technology of the power MOSFET is very important.
Throughout this research, the plenty of the advanced structures were developed and thesuperior performances were demonstrated for the low-power-loss MOSFETs. In addition,
as important part of this dissertation, the structure-based compact models to enable thepower loss calculation in the latest MOSFET structures were newly constructed.
Chapter 1 pointed out that, in addition to the conduction loss improvement by the

RONA reduction, the electric charge accumulated to the output capacitance, which affects
to the switching loss, was significant issue particularly in high-frequency switching.
Chapter 2 described the restructured RONA models of both D-MOSFETs and UMOSFETs, which were respectively classified into two different patterns: stripe andsquare cell. The calculated RONA by the model were compared with the developed devices.
In the square cell of the 60-V D-MOSFET, the calculated RONA corresponded to theexperimental result (130 m·mm2) with only 4.2% error. In the stripe cell of the 30-V UMOSFET, the calculated RONA corresponded to the experimental result (5.2 m·mm2)
with less than 1.0% error. Thus it was confirmed those showed good agreement.
Meanwhile, in the benchmarking of the tradeoff between the VB and the RONA for 20–
40-V-class U-MOSFETs, the developed 30-V sub-micron-pitch U-MOSFETs showedsuperior performance to the published data by approximately 30%.
Chapter 3 described the restructured RONA models, firstly for the SJ-UMOSFETs,
which were classified into three different patterns: stripe, square cell, and square p–
column in stripe trench. Then, the models of the FP-MOSFETs were classified into four
different structures: flat GFP, flat SFP, slant GFP, and slant SFP. The calculated RONA
by the model were compared with the developed devices. In the square cell of the 60-V
SJ-UMOSFET, the calculated RONA corresponded to the experimental result (28.7m·mm2) with only 3.1% error. In the stripe cell of the 100-V FP-MOSFET, thecalculated RONA corresponded to the TCAD simulation (28.2 m·mm2) with less than
1.0% error. Thus it was also confirmed those showed good agreement. Meanwhile, thebenchmarking of the tradeoff between the VB and the RONA, for 18–100-V-class SJUMOSFETs and FP-MOSFETs, were performed. In the developed novel devices, which
are the 60-V split p–column SJ-UMOSFET, the 100-V MSO-GFP-MOSFET, the 100-V 2173

step SFP-MOSFET, and the 18-V sub-micron-pitch GFP-MOSFET, each superior
performance was demonstrated against the published data.
Chapter 4 described the modeling for the latest slant FP-MOSFET having complex
structure, and clarified the components of the parasitic capacitances that are importantto the switching loss design of the power MOSFET. The Coss was divided into threeelements of Cds and an element of Cgd in total. The model equations of both Coss and Crsswere constructed based on physical constants and the device structural parameters.
Chapter 5 verified the validity of the constructed models. Firstly, the Vds
dependences of Coss and Crss, for both 100-V-class D-MOSFET and slant FP-MOSFET,
were calculated. Then, the 60-V-class GFP and SFP-MOSFETs were also calculated.
Moreover, the cell-pitch shrinking of the 100-V-class FP-MOSFET was studied. The
calculated capacitance curves by the model indicated good agreement with the results ofTCAD simulation. In addition, Qoss, Eoss, and turn-off switching time, which arenecessary for the switching loss analysis, were calculated from the model.
Chapter 6 performed the power loss analysis that assumed the 100-V and 60-Vrating device applications based on the models of RONA and capacitances. It was revealed
that the performance of the slant SFP-MOSFET was superior in high-frequency use(calculation up to 2 MHz), compared with the conventional device. On the other hand, inviewpoint of the system cost, the GFP-MOSFET had advantage for low-current use. The
active area of the GFP-MOSFET can make 20% reduction compared to that of the SFPMOSFET. Moreover, when the application is not high-frequency, the GFP-MOSFET
would be effective as high-current use.
Chapter 7 pursued the device performance limit of the slant FP-MOSFET byutilizing the models. In conceivable two case, a realistic limit and an ultimate limit, thedevice performances were predicted. The RONA and the RON·Qoss are drastically reduced
by 78.2–85.5% and 71.5–73.8%, respectively, from those of the current technology. As aresult, it became clear that the efficiency for the high-frequency switching application
can be improved by 50.9–54.0% and that for the low-frequency and high-current
application can be improved by 71.7–73.8%. The prediction means the realistic limit
structure is sufficiently competitive to the ultimate limit structure.
This dissertation indicated the principle of the future low-power-loss power
MOSFET design by utilizing the compact model, which can design in short term without
experiment and simulation. Moreover, it revealed that the FP-MOSFET structure hasan enough room for the performance improvement and this research area should be
advanced more. It is expected this compact model can greatly contribute to higher
efficiency power electronics.
174

Future challenges and perspective are described in the following.


Large-scale calculation with this compact model, e.g., by utilizing neural network,
would be able to find an optimum solution in very short time. Specifically, e.g., in acircuit including high-side/low-side MOSFETs, plural calculation by structuralparameters, load current, switching frequency, duty ratio, etc., is performed at one
time. To perform such a demonstration is desirable in the future work.

In this research, the components of the power loss were discussed focusing on the
MOSFET properties. Even in the case that uses SBD in the converter, the dioderecovery loss (PQrr) does not become zero completely. Modelling of the body-diode or
the SBD are one of the important challenges to predict the PQrr accurately.

In the total power loss in the circuit level, voltage over-shoot or current oscillation,
which are affected by stray inductances, have to be considered. Coupled analysis byusing both semiconductor device and circuit models would become significant more
and more.



It is recognized that there is a strong demand to expand the compact model to otherpower devices such as silicon carbide (SiC) or gallium nitride (GaN). The researchers
have to face for the challenge.

175

LIST OF TABLES
Table 2-1. List of RONA model equations for D-MOSFET (stripe and square cell
design). .................................................................................................................. 21
Table 2-2. Structural parameters of 60-V-class D-MOSFET to calculate RONA...... 26
Table 2-3. Electrical parameters of 60-V-class D-MOSFET to calculate RONA. ...... 26
Table 2-4. Physical constants to calculate RONA. ...................................................... 26
Table 2-5. List of RONA model equations for U-MOSFET (stripe and square cell
design). .................................................................................................................. 33
Table 2-6. Electrical characteristics of 30-V-class U-MOSFET for the rectangular celland the stripe cell. [40] [41] ................................................................................. 48
Table 2-7. Structural parameters of 30-V-class U-MOSFET to calculate RONA. .... 51
Table 2-8. Electrical parameters of 30-V-class U-MOSFET to calculate RONA. ...... 51
Table 3-1. List of RONA model equations for SJ-UMOSFET (stripe and square cell
design). .................................................................................................................. 63
Table 3-2. List of RONA model equations for SJ-UMOSFET (square p–column in
stripe trench). ....................................................................................................... 64
Table 3-3. Structural parameters of 60-V-class SJ-UMOSFET to calculate RONA. 78
Table 3-4. Electrical parameters of 60-V-class SJ-UMOSFET to calculate RONA. . 78
Table 3-5. List of RONA model equations for GFP-MOSFET and SFP-MOSFET withflat field-plate (stripe cell design). ...................................................................... 86
Table 3-6. List of RONA model equations for GFP-MOSFET and SFP-MOSFET withslant field-plate (stripe cell design). .................................................................... 87
Table 3-7. Structural parameters of 100-V-class FP-MOSFETs to calculate RONA.
............................................................................................................................. 101
Table 3-8. Electrical parameters of 100-V-class FP-MOSFETs to calculate RONA.
............................................................................................................................. 101
Table 4-1. Structural parameters of 100-V-class D-MOSFET to calculate
capacitances. [84] (modified)...............................................................................112
Table 4-2. Physical constants to calculate capacitances. .........................................113
Table 4-3. TCAD simulated basic characteristics for 100-V-class D-MOSFET. [84](modified). ............................................................................................................113
Table 4-4. List of Coss and Crss model equations for D-MOSFET. [84] (modified). .115
Table 4-5. Structural parameters of 100-V-class FP-MOSFET to calculate
capacitances. [84] (modified)...............................................................................117
Table 4-6. TCAD simulated basic characteristics for 100-V-class FP-MOSFET. [84]176

(modified). ............................................................................................................117
Table 4-7. List of Coss and Crss model equations for FP-MOSFET. [84] (modified).
............................................................................................................................. 124
Table 4-8. Structural parameters of 60-V-class SFP/GFP-MOSFETs to calculate
capacitances. [87] (modified).............................................................................. 126
Table 4-9. TCAD simulated basic characteristics for 60-V-class SFP/GFP-MOSFETs.
[87] (modified). .................................................................................................... 126
Table 4-10. List of Coss and Crss model equations for SFP-MOSFET and GFPMOSFET.............................................................................................................. 131
Table 5-1. TCAD simulated basic characteristics and calculated Coss and Qoss byproposed model for 100-V-class FP-MOSFETs. Other necessary parameters
except WCell, WT, WMesa and ND are the same as those of Table 4-7. .............. 147
Table 7-1. Representative structural parameters of 100-V-class slant FP-MOSFETs
to predict realistic limit and ultimate limit. ..................................................... 162
Table 7-2. Electrical and physical parameters of 100-V-class slant FP-MOSFETs topredict realistic limit and ultimate limit. ......................................................... 163
Table 7-3. Calculated RONA, RON·Qoss, and RON·Eoss of 100-V-class slant FPMOSFETs as realistic limit and ultimate limit. (Bold and underline)........... 166
Table 7-4. Representative structural and physical parameters of 100-V-class slant
FP-MOSFETs, which minimize RONA, for realistic limit and ultimate limit. 167

177

LIST OF FIGURES
Fig. 1-1. Global carbon dioxide (CO2) emissions reductions in the World Energy

Outlook (WEO) 2017 [1] New Policies and Sustainable Development Scenarios.
[2] ............................................................................................................................. 1
Fig. 1-2. Power semiconductor devices application map............................................. 2
Fig. 1-3. Schematics of volume of the CO2 emission reductions in each category of
the electronics system/unit/equipment. [4] © 2012 IEEE. .................................. 3
Fig. 1-4. Power MOSFETs application map................................................................. 4
Fig. 1-5. Market demands to electronics equipment and responsibilities as powerdevices R&D. ........................................................................................................... 5
Fig. 1-6. Classification of power MOSFETs. Rows show range of rated-voltage, andcolumns show cell structures which has been proposed in each early
development stage. ................................................................................................. 6
Fig. 1-7. Example of application circuit topology (1). Isolated DC-DC converter block
having full bridge for primary-side and synchronous rectification for secondaryside........................................................................................................................... 8
Fig. 1-8. Example of application circuit topology (2). Motor drive unit having threephase inverter. ........................................................................................................ 8
Fig. 1-9. Example of application circuit topology (3). Lithium-ion battery cellcharging/discharging control and protection circuit. ........................................... 9
Fig. 1-10. Simplified switching test circuit (left figure) and switching waveform(right figure).......................................................................................................... 10
Fig. 1-11. Components of power loss originated from the power MOSFET
characteristics in an assumption of the switching test circuit in Fig. 1-10. Eachpower loss is expressed by general formula. In addition, improvement methods
for each power loss are described. ........................................................................ 11
Fig. 1-12. Schematics of procedure from device structure design to device
performance evaluation/prediction: for real device, TACD simulation, andcompact model. ..................................................................................................... 13
Fig. 2-1. Technology development history for vertical power MOSFETs................. 14
Fig. 2-2. Schematic cross-sectional structure of D-MOSFET, which shows unit-cellarea. (a) Electric field distribution in vertical direction of off-state. (b) On-state
current paths and components of on-resistance................................................. 16
Fig. 2-3. (a) Top view of unit-cell layout [28] [29], © 1995 IEICE, and (b) structuralparameters of D-MOSFET. .................................................................................. 18
178

Fig. 2-4. (a) Top view of D-MOSFET for square cell layout. Schematic cross-sectional
structure, which shows components of the n–drift layer resistance (RD1_B, RD1_G,

RD2). (b) Current flow spreading in 45 degrees underneath p-base layer. (c)Current flow under gate intersection.................................................................. 20
Fig. 2-5. Sidewall self-aligned process for n+ source layer formation. [29] © 1995
IEICE..................................................................................................................... 23
Fig. 2-6. (a) WG and XJB dependences of RONA, and (b) D and XJB dependences of

RONA in fabricated TEG of D-MOSFET. [29] (modified). .................................. 24
Fig. 2-7. Experimental result of relationship between RONA and VB in fabricatedTEG of D-MOSFET. [29] (modified). ................................................................... 24
Fig. 2-8. Experimental result of RONA for developed 60-V-class D-MOSFET
compared with that of both analytical model and TCAD simulation. .............. 25
Fig. 2-9. (a) Parasitic capacitances of D-MOSFET. (b) Partially thick .gate oxide
structure for D-MOSFET. [29] © 1995 IEICE. ................................................... 27
Fig. 2-10. Vds dependence of capacitances (Ciss, Coss, and Crss) in D-MOSFETs. In
comparison of conventional structure and fabricated partially thick gate oxide
structure. [29] © 1995 IEICE............................................................................... 28
Fig. 2-11. Schematic cross-sectional structure of U-MOSFET, which shows two unitcells area. (a) Electric field distribution in vertical direction of off-state. (b) Onstate current paths and components of on-resistance. ...................................... 29
Fig. 2-12. (a) Structural parameters of U-MOSFET. Top view of U-MOSFET unitcell layout for (b) square cell design and (c) stripe cell design. ......................... 31
Fig. 2-13. (a) Top view of U-MOSFET for square cell layout. Schematic crosssectional structure, which shows components of the n–drift layer resistance(RD1_M, RD1_T, RD2). ................................................................................................ 32
Fig. 2-14. Bird’s eye view of U-MOSFET structure designed to square cell, which has
double trenches in unit cell. (Source and drain metals are not shown.) [40] ©
2007 IEEE, [41] .................................................................................................... 34
Fig. 2-15. Process flow of U-MOSFET having double trenches [34]. ....................... 35
Fig. 2-16. Bird’s eye view of newly developed U-MOSFETs structures. (Source anddrain metals are not shown.) Dx is trench pitch in narrower direction for both
rectangular cell and stripe cell. Dy is unit-cell length for rectangular cell. [40] ©
2007 IEEE, [41] .................................................................................................... 37
Fig. 2-17. Top views of U-MOSFET unit-cell layout for (a) 2-m-pitch square cell
design, (b) sub-micron-pitch rectangular cell design, and (c) sub-micron-pitch
stripe cell design. .................................................................................................. 38
179

Fig. 2-18. Calculated total channel width in 7.5 mm2 chip area for (a) rectangularcell design, which depends on Dy, and (b) stripe cell design, which depends on

Dx and p+–pitch. Channel width of 2-m square cell is indicated in both graphs
for comparison. [40] © 2007 IEEE (modified), [41].......................................... 39
Fig. 2-19. Simulated potential contours for U-MOSFETs. In short side (Dx) direction,
half size of (a) 0.8-m pitch, (b) 1.0-m pitch and (c) 1.2-m pitch, whichcorrespond to both stripe and rectangular cell, are simulated at p+–region. Inlong side (Dy) direction, (d) half size of rectangular cell is simulated. [40] (c) 2007
IEEE (modified), [41] (modified). ........................................................................ 40
Fig. 2-20. Process flow of narrow pitch rectangular cell U-MOSFET. [42] ............. 42
Fig. 2-21. Process flow of narrow pitch rectangular cell U-MOSFET. [42] ............. 43
Fig. 2-22. SEM photograph of fabricated 0.92-m pitch UMOSFET. (a) Crosssectional view of an area including four trenches, observed by tilting angle of 45
degrees [40] © 2007 IEEE (modified), [41]. (b) Top view of plural rectangularcells. ....................................................................................................................... 44
Fig. 2-23. Comparison of gate leakage current as a function of the gate electric field
for fabricated UMOSFETs. [40] © 2007 IEEE (modified), [41] ......................... 45
Fig. 2-24. Measured RONA and VB dependences on Dx, Dy and p+–pitch. [40] © 2007
IEEE (modified), [41] ........................................................................................... 47
Fig. 2-25. Avalanche capability of fabricated rectangular cell UMOSFET for Dx = 1.0
m and Dy = 3.0 m. (a) Test circuit of unclamped inductive switching (UIS). (b)Waveforms of UIS for L = 100 H. [40] © 2007 IEEE (modified), [41] ............. 48
Fig. 2-26. Experimental results of RONA for developed 30-V-class U-MOSFET
compared with that of both analytical model and TCAD simulation. Under thecondition of Vgs = 4.5 V, 10 V. ............................................................................... 50
Fig. 2-27. Tradeoff between RONA and VB for U-MOSFETs by published data [32][33] [39] [43] [44] [45] [46] and author’s research [40] [41]. .............................. 52
Fig. 3-1. Technology development history for vertical power MOSFETs................. 53
Fig. 3-2. Charge compensation for SJ-UMOSFET. Depletion layer formation when(a) low voltage and (b) high voltage are applying. (c) Charge compensation by
p/n–columns. ......................................................................................................... 54
Fig. 3-3. Charge compensation for FP-MOSFET. Depletion layer formation when (a)low voltage and (b) high voltage are applying. (c) Charge compensation by using
field-plate. ............................................................................................................. 54
Fig. 3-4. Schematic cross-sectional structures of SJ-UMOSFET, which shows twounit-cells area. (a) Electric field distribution in vertical direction of off-state. (b)180On-state current paths and components of on-resistance. ................................ 58
Fig. 3-5. (a) Structural parameters of SJ-UMOSFET. Top view of SJ-UMOSFET
unit-cell layout for (b) square cell design and (c) stripe cell design.................. 59
Fig. 3-6. (a) Top view of SJ-UMOSFET for square cell layout. Schematic crosssectional structure, which shows components of the n–drift layer resistance(RD1_P, RD2_P, RD_T). ............................................................................................... 62
Fig. 3-7. (a) Top view of SJ-UMOSFET for square p–column in stripe cell layout.
Schematic cross-sectional structure, which shows components of the n–drift
layer resistance (RD1_P, RD2_P, RD_N). (b) Current flow spreading in 45 degrees
from both sides of the square p–column. (c) Current flow spreading in 45 degrees
in n–drift region.................................................................................................... 62
Fig. 3-8. Schematic cross-sectional structures of developed SJ-UMOSFETs
fabricated by using multiple-ion-implantation. (a) Continuous p–column [10] ©
2004 IEEE (modified). (b) Split p–column [64] © 2005 IEEE (modified). ........ 66
Fig. 3-9. Number of the ion-implantations for SJ-UMOSFETs fabrication. ........... 66
Fig. 3-10. Simulated boron doping profiles along the p–column center. The profiles
for different number of boron injections are compared. [64] © 2005 IEEE
(modified). ............................................................................................................. 67
Fig. 3-11. Dependence of the simulated VB on the number of boron injections for aconstant total dose of 1.2×1013 cm−2 and a common maximum energy of 1.5 MeV.
............................................................................................................................... 68
Fig. 3-12. Simulated Id–Vds characteristics of the SJ-UMOSFET and conventional
U-MOSFET are compared for 4-m cell devices. [10] © 2004 IEEE. ............... 68
Fig. 3-13. Simulated avalanche current flow lines at room temperature of the SJUMOSFETs for N = 4, in comparison of two different p–column dose conditions.
[10] © 2004 IEEE (modified). ............................................................................... 69
Fig. 3-14. (a) Simulated avalanche current flow lines at room temperature of the SJUMOSFET for N = 2. (b) Avalanche current density at 150°C across thehorizontal plane in the middle depth of the p–column, in comparison of N =2
and N = 4. [64] © 2005 IEEE (modified). ............................................................ 70
Fig. 3-15. (a) VB and (b) RONA of optimized SJ-UMOSFETs for N = 4, 2, and 1, incomparison of two types of n–epi layers. [64] (modified). .................................. 71
Fig. 3-16. SCM image of SJ-diode with cell pitch of 3.0 m. [10] © 2004 IEEE. .... 72
Fig. 3-17. (a) Time dependence of the VB and the VTH, after the repetitive avalanchestress. (b) C–V curves before and after the repetitive avalanche stress, for 168
hours at 175°C. [64] © 2005 IEEE (modified). ................................................... 74
181

Fig. 3-18. (a) Time dependence of the reverse current of body diode under thecondition of di/dt at 100 A/s, and (b) reverse recovery time and reverse recovery
charge of body diode, for SJ-UMOSFETs fabricated with N = 4, 2, and 1 [64] ©
2005 IEEE (modified). .......................................................................................... 75
Fig. 3-19. Tradeoff between VB and RONA for 3.0-m pitch SJ-UMOSFETs. The
measured best performance shows RONA = 28.7 m·mm2 and VB = 68.0 V. [64]© 2004 IEEE (modified). ...................................................................................... 76
Fig. 3-20. Experimental results of RONA for developed 60-V-class SJ-UMOSFET
compared with that of both analytical model and TCAD simulation. Under thecondition of Vgs = 10 V. ......................................................................................... 77
Fig. 3-21. Schematic cross-sectional structures of FP-MOSFET, which shows twounit-cells area. (a) Electric field distribution in vertical direction of off-state. (b)On-state current paths and components of on-resistance. ................................ 80
Fig. 3-22. Classification of FP-MOSFETs. (a) GFP-MOSFET with flat field-plate, (b)SFP-MOSFET with flat field-plate, (c) GFP-MOSFET with slant field-plate, and(d) SFP-MOSFET with slant field-plate. ............................................................ 81
Fig. 3-23. Structural parameters of SFP-MOSFET (a) with flat field-plate and (b)with slant field-plate. ........................................................................................... 82
Fig. 3-24. (a) Top view of FP-MOSFET for stripe cell layout. Schematic crosssectional structure, which shows components of the accumulation layer and n–
drift layer resistance (RA, RA_FP, RD1 and RD2), for (b) GFP-MOSFET and (c) SFPMOSFET with flat field-plate. Current flow spreading along the field plate in
the mesa region and the buffer layer is showing. .............................................. 83
Fig. 3-25. (a) Top view of FP-MOSFET for stripe cell layout. Schematic crosssectional structure, which shows components of the accumulation layer and n–
drift layer resistance (RA, RA_FP, RD1 and RD2), for (b) GFP-MOSFET and (c) SFPMOSFET with slant field-plate. Current flow spreading along the field plate in
the mesa region and the buffer layer is showing. .............................................. 85
Fig. 3-26. Schematic cross-sectional structures of (a) conventional FP-MOSFET withuniform thick oxide, (b) ideal slant FP-MOSFET with gradient oxide, and (c)proposed multiple-stepped-oxide (MSO) FP-MOSFET. [72] © 2015 IEEE
(modified), [73]. ..................................................................................................... 89
Fig. 3-27. 2-D potential contours at 5-V intervals and 1-D vertical electric field
distributions along the trench sidewall. ND dependence of the potential: (a), (d),and (g) for conventional FP-MOSFETs; and (b), (e), and (h) for MSO-FPMOSFETs. ............................................................................................................. 90
182

Fig. 3-28. Simulated TFPOX_b (tOX,b) dependence of VB for various ND in the case of
conventional FP-MOSFETs. [73] (modified). ...................................................... 91
Fig. 3-29. Simulated ND dependence of VB for MSO-FP-MOSFETs (K = 5.5–15.5) andconventional FP-MOSFET (K = 50). [73] (modified).......................................... 92
Fig. 3-30. 2-D simulation results for MSO-FP-MOSFETs (K = 5.5–15.5). Depletion
layer (white lines), potential contours at 5-V intervals (black lines), and electricfield distributions (color) are shown in each half-cell structure. ...................... 92
Fig. 3-31. Simulated ND dependence of RONA for MSO-FP-MOSFETs (K = 5.5–15.5)
and conventional FP-MOSFET (K = 50). [73] (modified). ................................. 93
Fig. 3-32. Simulated K dependence of VB process margin over 100 V. And K
dependence of RONA; at ND = 3.0×1016 /cm3 for MSO-FP-MOSFETs and at ND =2.0×1016 /cm3 for conventional FP-MOSFET. Reconstructed from Fig. 3-29 andFig. 3-31. [73] (modified). ..................................................................................... 94
Fig. 3-33. Simulated ND dependence of VB process margin up to 100 V and RONA for
MSO-FP-MOSFETs and conventional FP-MOSFETs. Reconstructed from Fig.
3-29 and Fig. 3-31. [73] (modified). ..................................................................... 95
Fig. 3-34. Part of fabrication process flow of MSO-FP-MOSFET, named Stepped
Oxide Deposition (SOD) process. (From trench formation to field-plate
formation.) [72] © 2015 IEEE, [73]. .................................................................... 96
Fig. 3-35. Part of fabrication process flow of MSO-FP-MOSFET, named Stepped
Oxide Etch-off (SOE) process. (From trench formation to field-plate formation.)[72] © 2015 IEEE, [73]. ........................................................................................ 97
Fig. 3-36. Cross-sectional SEM photograph of fabricated MSO-FP-MOSFET, whichcorresponds to field-plate formation step of SOE process. [72] © 2015 IEEE, [73].
............................................................................................................................... 98
Fig. 3-37. (a) ID–VDS characteristics of the measured diode TEG, in comparison of
the simulated MSO-FP-MOSFET. (b) ID–VDS characteristics of the measured
resistivity TEG. [73] ............................................................................................. 99
Fig. 3-38. RONA of simulated 100-V-class FP-MOSFETs (conventional FP-MOSFET
and MSO-FP-MOSFET) compared with those of analytical model (flat FPMOSFET and slant FP-MOSFET). Under the condition of Vgs = 10 V........... 100
Fig. 3-39. Schematic cross-sectional structures of (a) conventional FP-MOSFET withuniform thick oxide, (b) multiple-stepped-oxide (MSO) FP-MOSFET, and (c)proposed 2-step FP-MOSFET. [74] (c) 2019 IEEE. .......................................... 102
Fig. 3-40. Simulated 2-D potential contours (black lines), for (a) conventional, (b)MSO, and (c) 2-step FP-MOSFETs. (d) 1-D vertical electric field distributions
183

along trench sidewall for conventional FP-MOSFETs (red dotted line), MSO-FPMOSFETs (green dashed line), and 2-step FP-MOSFET (blue solid line). Under
the condition of ND = 3.0×1016 /cm3. [74] (c) 2019 IEEE. ................................. 103
Fig. 3-41. Simulated WMesa dependences of VB,peak and “ND at VB,peak” for 2-step FPMOSFETs. (tOX,b = 600 nm, K = 9.2). [74] © 2019 IEEE (modified)................ 104
Fig. 3-42. (a)–(f) Part of fabrication process flow of 2-step FP-MOSFET (from thickoxide formation to gate electrode formation.). (g) TEM photograph of fabricated2-step FP-MOSFET (unit cell). [74] (c) 2019 IEEE. ......................................... 105
Fig. 3-43. Measured RONA distribution of 2-step FP-MOSFETs fabricated by target
design & center process conditions. [74] (c) 2019 IEEE. ................................. 106
Fig. 3-44. Comparison of FOM for conventional and 2-step FP-MOSFETs.
Measurement conditions: Vgs = 10 V and Id = 30 A for RON, and Vds = 50 V and Id= 35 A for Qg, Qsw, and Qoss. [74] (c) 2019 IEEE. .............................................. 106
Fig. 3-45. Ratio of RONA components for 20–60-V U-MOSFETs. [75] (modified).. 107
Fig. 3-46. (a) Schematic cross-sectional structure and (b) SEM photograph offabricated 18-V sub-micron cell pitch FP-MOSFET. [75] (modified). ............. 107
Fig. 3-47. (a) Gate leakage current as a function of the gate electric field and (b) offstate Id–Vds characteristic of fabricated 18-V FP-MOSFET. [75] (modified).. 108
Fig. 3-48. (a) On-state Id–Vds characteristic [75] and (b) capacitances (Ciss, Coss, andCrss) as a function of Vds of fabricated 18-V FP-MOSFET................................ 108
Fig. 3-49. Tradeoff characteristics between RONA and VB for FP-MOSFETs and SJUMOSFETs; by published data [8] [49] [50] [51] [52] [55] [56] [57] [71] [76] andauthor’s research [10] [64] [72] [74] [75] [77]. (a) Including 100-V MSO-FPMOSFET and (b) including 100-V 2-step FP-MOSFET. [72] (modified). ........110
Fig. 4-1. (a) Schematic cross sections and representative structural parameters of DMOSFET. (b) Components of output capacitance (Coss) and reverse transfer
capacitance (Crss) for D-MOSFET. [83] [84] Copyright (2018) The Japan Societyof Applied Physics. ...............................................................................................112
Fig. 4-2. (a) Schematic cross sections and representative structural parameters ofslant FP-MOSFET. (b) Comprehensive structural parameters of FP-MOSFET(half-cell structure) to describe capacitance model. (c) Components of output
capacitance (Coss) and reverse transfer capacitance (Crss) for FP-MOSFET. [83][84] Copyright (2018) The Japan Society of Applied Physics. ..........................116
Fig. 4-3. TCAD-simulated FP-MOSFET half-cell structures, which represent Vds
dependence of equal-potential contours. Potential contours and depletion layerboundaries are shown as black lines and white lines, respectively. Three184

capacitance components are shown as dominant regions: (a) main pn-junction,(b) field-plate oxide and depletion layer along trench side wall, and (c) field-plate
oxide and depletion layer of trench bottom. [84] Copyright (2018) The Japan
Society of Applied Physics...................................................................................119
Fig. 4-4. Schematic cross-sectional structures for (a) SFP-MOSFET and (b) GFPMOSFET. (c) Comprehensive structural parameters of FP-MOSFET (half-cellstructure) to describe capacitance model. [87] (modified). .............................. 125
Fig. 4-5. Parasitic capacitance components for (a) SFP-MOSFET and (b) GFPMOSFET. White lines indicate depletion layer boundaries at Vds = 10 V by
TCAD simulation. ............................................................................................... 128
Fig. 5-1. Coss components of 100-V-class FP-MOSFET calculated using proposedmodel compared with TCAD simulation results. [84] Copyright (2018) The
Japan Society of Applied Physics. ..................................................................... 132
Fig. 5-2. Coss–Vds curves calculated using proposed model compared with TCAD
results for 100-V-class D-MOSFET and FP-MOSFET. (a) Vds linear scale and (b)Vds log scale in X-axis. Each active area is designed for the same RON of 10m.
[84] Copyright (2018) The Japan Society of Applied Physics. ......................... 133
Fig. 5-3. Explanation of switching operation concerning Coss and Qoss. [84] Copyright(2018) The Japan Society of Applied Physics. .................................................. 134
Fig. 5-4. (a) Qoss–Vds and (b) Eoss–Vds curves calculated using proposed modelcompared with TCAD results for 100-V-class D-MOSFET and FP-MOSFET.
Each active area is designed for the same RON of 10m. [83] [84] Copyright(2018) The Japan Society of Applied Physics. .................................................. 135
Fig. 5-5. (a) Crss–Vds curves calculated using proposed model compared with TCAD
results for 100-V-class D-MOSFET and FP-MOSFET. (a) Vds linear scale and (b)Vds log scale in X-axis. Each active area is designed for the same RON of 10m
[84] Copyright (2018) The Japan Society of Applied Physics. ......................... 136
Fig. 5-6. Qgd–Vds curves calculated using proposed model compared with TCAD
results for 100-V-class D-MOSFET and FP-MOSFET. Each active area isdesigned for the same RON of 10 m. ................................................................ 137
Fig. 5-7. Turn-off switching waveforms calculated using proposed model for (a) DMOSFET and (b) FP-MOSFET. VIN = 50 V, ION = 10 A, Rg = 1.5 , and Ig = 0.83
A. [84] Copyright (2018) The Japan Society of Applied Physics. .................... 138
Fig. 5-8. (a) Coss–Vds and Crss–Vds curves calculated using proposed model comparedwith TCAD results for 60-V-class SFP-MOSFET. (b) Coss–Vds and Crss–Vds curves
calculated using proposed model compared with TCAD results for 60-V-class185

GFP-MOSFET. [87] ............................................................................................ 140
Fig. 5-9. (a) Qoss–Vds and (b) Eoss–Vds curves calculated using proposed modelcompared with TCAD results for 60-V-class SFP-MOSFET and GFP-MOSFET.
Each active area is designed for the same RON of 1.8 m. [87]....................... 141
Fig. 5-10. Qgd–Vds curves calculated using proposed model compared with TCAD
results for 60-V-class SFP-MOSFET and GFP-MOSFET. Each active area isdesigned for the same RON of 1.8 m. ............................................................... 142
Fig. 5-11. Turn-off switching waveforms calculated using proposed model for (a) SFPMOSFET and (b) GFP-MOSFET. VIN = 30 V, ION = 70 A, Rg = 3 , and Ig = 0.83
A. [87] .................................................................................................................. 143
Fig. 5-12. WCell dependences of Coss–Vds curve calculated using proposed modelcompared with TCAD results for 100-V-class FP-MOSFETs. WCell is shrunkfrom 3.0 to 2.6 m by changing WMesa from 1.5 to 1.1 m. In each row, left figure
shows Vds linear scale and right figure shows Vds log scale in X-axis. ........... 145
Fig. 5-13. WCell dependences of Coss–Vds curve calculated using proposed modelcompared with TCAD results for 100-V-class FP-MOSFETs. WCell is shrunkfrom 2.4 to 2.0 m by changing WMesa from 0.9 to 0.5 m. In each row, left figure
shows Vds linear scale and right figure shows Vds log scale in X-axis. ........... 146
Fig. 6-1. Estimated power losses for 100-V-class (a) D-MOSFET and (b) FPMOSFET,
assuming 50-V input, 10-A output, 80% duty ratio, and 100 kHz–2 MHz
switching operation. Each active area is designed for the same RON of 10 m.
[84] (modified). .................................................................................................... 149
Fig. 6-2. Estimated power losses for 60-V-class (a) SFP-MOSFET and (b) GFPMOSFET, assuming 30-V input, 50-A output, 50% duty ratio, and 20–200 kHz
switching operation. Each active area is designed for the same RON of 1.8 m.
............................................................................................................................. 150
Fig. 6-3. Estimated power losses for 60-V-class (a) SFP-MOSFET and (b) GFPMOSFET, assuming 30-V input, 50-A output, 50% duty ratio, and 200 kHz–2
MHz switching operation. Each active area is designed for the same RON of 1.8
m. ...................................................................................................................... 151
Fig. 6-4. (a) Active area dependence of power losses for 60-V-class SFP-MOSFET and
GFP-MOSFET in fSW ranged from 20 to 200 kHz, 30-V supply voltage, 70-A load
current, and 50% duty ratio. (b) Distinguished to individual losses in 20 kHz. (c)Enlarged view of small active area (< 5 mm2). [87] (modified). ...................... 153
Fig. 7-1. Schematic cross sections of (a) the latest slant FP-MOSFET and (b)proposed ultimate FP-MOSFET. ....................................................................... 156
186

Fig. 7-2. WCell dependences of (a) RONA, (b) Qoss/A, and (c) RON·Qoss for realistic limit
and ultimate limit prediction of 100-V-class slant FP-MOSFETs. These
prediction are using structural parameters in Table 7-2 and Table 7-1. ....... 165
Fig. 7-3. Components of predicted RONA limit for 100-V-class slant FP-MOSFETs. In
comparison of current technology (Wcell = 2.6 m), realistic limit (Wcell = 0.95m), and ultimate limit (Wcell = 0.55 m). Under the condition of Vgs = 10 V. 166
Fig. 7-4. Prediction of tradeoff relationship between RON and Qoss of 100-V-class slant
FP-MOSFETs. (a) Log scale and (b) linear scale in X-/Y-axis. ........................ 168
Fig. 7-5. Predicted power loss of 100-V-class FP-MOSFET in high current application.
In comparison of current technology (Wcell = 2.6 m, RONA = 26.7 m·mm2),
realistic limit (Wcell = 0.95 m, RONA = 5.82 m·mm2), and ultimate limit (Wcell= 0.55 m, RONA = 3.87 m·mm2). Assuming 48-V input, 100-A output, 50%
duty ratio, and 100 kHz switching operation. Each active area is the same asthat of current technology FP-MOSFET. .......................................................... 169
Fig. 7-6. Predicted power losses of 100-V-class FP-MOSFETs in high frequency
application, for (a) high-side, (b) low-side, and (c) sum of high-side and low-side.
In comparison of current technology (Wcell = 2.6 m), realistic limit (Wcell = 1.55m), and ultimate limit (Wcell = 1.05 m). Assuming 48-V input, 12-V/30-A
output, 1 MHz switching operation, and 25%/75% duty ratio for high-side/lowside. Same RON of 3.33 m is designed for high-side and same active area of 8.01
mm2 is designed for low-side. ............................................................................ 171

187

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Aida, K. Ichinoseki, K. Oasa and Y. Kawaguchi, "100-V class two-step-oxide fieldplate trench MOSFET to achieve optimum RESURF effect and ultralow onresistance," Proceedings of the 31st International Symposium on Power

Semiconductor Devices & ICs (ISPSD), pp. 99-102, 2019.
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[77] H. Okubo, K. Kobayashi and Y. Kawashima, "Ultralow on-resistance 30-40 V
UMOSFET by 2-D scaling of ion-implanted superjunction structure," Proceedingsof the 25th International Symposium on Power Semiconductor Devices and ICs(ISPSD), pp. 87-90, 2013.
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RESEARCH HISTORY
Publication1.

Kenya Kobayashi, Masaki Sudo and Ichiro Omura, “Structure-based capacitancemodeling and power loss analysis for the latest high-performance slant field-plate
trench MOSFET,” Japanese Journal of Applied Physics, vol. 57, no. 04FR14, pp. 1-8,
Mar. 2018.

International Conferences
1.

Kenya Kobayashi, Masaki Sudo and Ichiro Omura, “Structure based compact modelfor output capacitance of trench field-plate MOSFET to enable power loss prediction,”

Extended abstracts of the International Conference on Solid State Devices andMaterials (SSDM), pp. 709-710, Sep. 2017.
2.

Kenya Kobayashi, Masaki Sudo and Ichiro Omura, “Power loss analysis of 60 V
trench field-plate MOSFETs utilizing structure based capacitance model for
automotive application,” Proceedings of the 10th International Conference on

Integrated Power Electronics Systems (CIPS), pp. 122-127, Mar. 2018.

Related Papers
1.

K. Kobayashi, Y. Ninomiya, M. Takahashi and M. Maruoka, “Development of process
for low on-resistance vertical power MOSFETs,” NEC Research & Development, vol.
35, no. 4, pp. 433-437, Oct. 1994.

2.

T. Hamajima, K. Kobayashi, H. Kikuchi, K. Okonogi, K. Arai, Y. Ninomiya and M.
Takahashi, “Void-free bonded SOI substrates for high voltage, high current vertical
DMOS type power ICs,” Japanese Journal of Applied Physics, vol. 34, part 1, no. 2B,
pp. 848-853, 1995.

3.

K. Kobayashi, T. Hamajima, H. Kikuchi, M. Takahashi and K. Arai, “An intelligent
power device using poly-Si sandwiched wafer bonding technique,” Proceedings of the

7th International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp.
58-62, 1995.
4.

K. Kobayashi, T. Hamajima, H. Kikuchi, M. Takahashi and T. Kitano,“Applicationof partially bonded SOI structure to an intelligent power device having vertical
DMOSFET,” Proceedings of the 9th International Symposium on Power198

Semiconductor Devices and ICs (ISPSD), pp. 309-312, 1997.
5.

H. Ninomiya, Y. Miura and K. Kobayashi, “Ultra-low on-resistance 60-100 V
superjunction UMOSFETs fabricated by multiple ion-implantation,” Proceedings ofthe 16th International Symposium on Power Semiconductor Devices and ICs(ISPSD), pp. 177-180, 2004.
6.

Y. Miura, H. Ninomiya and K. Kobayashi, ”High performance superjunction
UMOSFETs

with

split

p-columns

fabricatedbymulti-ion-implantations,”

Proceedings of the 17th International Symposium on Power Semiconductor Devices
and ICs (ISPSD), pp. 39-42, 2005.
7.

K. Kobayashi, A. Kaneko, Y. Murase and H. Yamamoto, ”Sub-micron cell pitch 30 V
n-channel UMOSFET with ultra low on-resistance,” Proceedings of the 19thInternational Symposium on Power Semiconductor Devices and ICs (ISPSD), pp.
205-208, May 2007.
8.

H. Okubo, K. Kobayashi and Y. Kawashima, ”Ultralow on-resistance 30-40 V
UMOSFET by 2-D scaling of ion-implanted superjunction structure,” Proceedings ofthe 25th International Symposium on Power Semiconductor Devices and ICs(ISPSD), pp. 87-90, 2013.
9.

K. Kobayashi, T. Nishiguchi, S. Katoh, T. Kawano and Y. Kawaguchi, ”100 V classmultiple stepped oxide field plate trench MOSFET (MSO-FP-MOSFET) aimed toultimate structure realization,” Proceedings of the 27th International Symposium

on Power Semiconductor Devices and ICs (ISPSD), pp. 141-144, 2015.
10. T. Nishiwaki, S. Katoh, K. Kobayashi and Y. Hokomoto, “Breakdown voltage
instability mechanism and improving ruggedness in trench field plate power
MOSFET,” Proceedings of the 28th International Symposium on Power

Semiconductor Devices and ICs (ISPSD), pp. 215-218, 2016.
11. T. Nishiwaki, K. Kobayashi and Y. Kawaguchi, “Modeling of time dependent
breakdown voltage degradation in trench field plate power MOSFET,” Proceedingsof the 29th International Symposium on Power Semiconductor Devices and ICs(ISPSD), pp. 463-466, 2017.
12. H. Kato, K. Kobayashi, T. Nishiguchi, and S. Shimomura, “Process control techniqueto reduce wafer warpage for trench field plate power MOSFET,” Proceedings of theInternational Symposium on Semiconductor Manufacturing (ISSM), PC-O-26, pp. 14, 2018.
13. K. Kobayashi, H. Kato, T. Nishiguchi, S. Shimomura, T. Ohno, T. Nishiwaki, K. Aida,
K. Ichinoseki, K. Oasa and Y. Kawaguchi, ”100-V class two-step-oxide field-plate
trench MOSFET to achieve optimum RESURF effect and ultralow on-resistance,”
199

Proceedings of the 31st International Symposium on Power Semiconductor Devices& ICs (ISPSD), pp. 99-102, 2019.
14. S. Shimomura, H. Kato. T. Shiraishi, T. Ohno, T. Nishiguchi, K. Miyashita and K.
Kobayashi, “Process control technique to dramatically reduce voids in phosphorusdoped poly-silicon for trench field-plate MOSFETs,” Proceedings of the Joint

International Symposium on e-Manufacturing & Design Collaboration (eMDC) &Semiconductor Manufacturing (ISSM), N5, pp. 1-4, 2019.

Related Patents
United States Patent:
No. 6888196, “Vertical MOSFET produced in cell size and method of producing the same,”2005.
No. 7332770, “Semiconductor device,” 2008.
No. 7429768, “Method of manufacturing a semiconductor device having a trenchsurrounding plural unit cells,” 2008.
No. 7508030, “Semiconductor device with vertical MOSFET and method of
manufacturing the same,” 2009.
No. 7622351, “Method of manufacturing Semiconductor device and Semiconductor
device,” 2009.
No. 7776693, “Method of manufacturing semiconductor apparatus,” 2010.
No. 7893489, “Semiconductor device having vertical MOSFET and method of
manufacturing the same,” 2011.
No. 8361865, “Method of manufacturing a semiconductor device having vertical
MOSFET,” 2013.
No. 9525059, “Semiconductor device with graded drift region,” 2016.
No. 9536959, “Power semiconductor device having field plate electrode,” 2017.
No. 9871131, “Semiconductor device with insulating section of varying thickness,” 2017.
No. 9716009, “Semiconductor device with insulating section of varying thickness” 2017.
No. 9947751, “Semiconductor device and method of manufacturing the same,” 2018.
No. 9954055, “Vertical power MOSFET device,” 2018.

200

ABOUT THE AUTHOR
Kenya Kobayashi was born in Nagano, Japan on February 17, 1969. He received
Bachelor degree in electrical engineering from Chiba University, Chiba, Japan, in 1991.
He joined NEC Corporation, Kawasaki, Japan, in 1991 and was engaged in thesemiconductor devices development, e.g., power MOSFETs, power ICs, high-voltage
bipolar ICs, and high-voltage CMOS ICs, for eleven years. He belonged to NEC
Electronics Corporation, Kawasaki, Japan, in 2002–2010, and Renesas Electronics
Corporation, Kawasaki, Japan, in 2010–2013. He advanced R&D of the power MOSFETs
and commercialized many products for eleven years. In October 2013, he moved to
Toshiba Corporation, Ishikawa, Japan and he is currently with Advanced Discrete
Development Center in Toshiba Electronic Devices & Storage Corporation as a senior
manager of the development of power devices process integration technology. He is aholder of 60 U.S. patents, 11 Chinese patents, and 25 Japanese patents.
Since October 2013, he has concurrently been a doctoral course student in Graduate
School of Engineering, Kyushu Institute of Technology, Kitakyushu, Japan. His interests
are advanced power semiconductor devices, fabrication process technologies, processdevice simulations, and compact modeling for them.
He was a member of the technical program committee (TPC) of the IEEE
International Symposium on Power Semiconductor Devices & ICs in 2010–2013, and heis currently belonging to the TPC since 2016. He was also a member of the programcommittee of the International Conference on Solid State Devices and Materials, theJapan Society of Applied Physics in 2016–2017. He is a member of the IEEE Electron
Devices Society.

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