LPS35HW
MEMS pressure sensor: 260-1260 hPa absolute digital output
barometer with water resistant package
Datasheet - production data

Applications
Wearable devices
Altimeter and barometer for portable devices
GPS applications
Weather station equipment

Description
The LPS35HW is an ultra-compact piezoresistive
pressure sensor which functions as a digital
output barometer. The device comprises a
sensing element and an IC interface which
communicates through I2C or SPI from thesensing element to the application.

Features
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Pressure sensor with water resistantpackage
260 to 1260 hPa absolute pressure range
Current consumption down to 3 µA
High overpressure capability: 20x full scale
Embedded temperature compensation
24-bit pressure data output
16-bit temperature data output
ODR from 1 Hz to 75 Hz
SPI and I²C interfaces
Embedded FIFOInterrupt functions: Data Ready, FIFO flags,pressure thresholds
Supply voltage: 1.7 to 3.6
ECOPACK® lead-free compliant

The sensing element, which detects absolutepressure, consists of a suspended membrane
manufactured using a dedicated processdeveloped by ST.
The LPS35HW is available in a holed ceramic
LGA package. It is guaranteed to operate over atemperature range extending from -40 °C to +85°C. The package is holed to allow externalpressure to reach the sensing element.
Table 1: Device summary table
Order code
LPS35HWTR

DocID029129 Rev 1

This is information on a product in full production.

Package

Packing

CCLGA10L

Tape
and reel

CCLGA10LTray-40 to +85 °C
LPS35HW

July 2016

Temperature
range [°C]1/48
www.st.com

Contents

LPS35HW

Contents
1

Block diagram and pin description ................................................ 6

2

Mechanical and electrical specifications ....................................... 8
2.1

Mechanical characteristics ................................................................ 8

2.2

Electrical characteristics .................................................................... 9

2.3

Communication interface characteristics ........................................... 9

2.4

3

4

5

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SPI serial peripheral interface ............................................................ 9

2.3.2

I2C inter - IC control interface .......................................................... 10

Absolute maximum ratings .............................................................. 12

Functionality .................................................................................. 13
3.1

Sensing element ............................................................................. 13

3.2

IC interface ...................................................................................... 13

3.3

Factory calibration ........................................................................... 13

3.4

How to interpret pressure readings ................................................. 13

FIFO ................................................................................................ 15
4.1

Bypass mode .................................................................................. 15

4.2

FIFO mode ...................................................................................... 16

4.3

Stream mode................................................................................... 16

4.4

Dynamic-Stream mode ................................................................... 17

4.5

Stream-to-FIFO mode ..................................................................... 18

4.6

Bypass-to-Stream mode ................................................................. 19

4.7

Bypass-to-FIFO mode ..................................................................... 20

4.8

Retrieving data from FIFO ............................................................... 20

Application hints ........................................................................... 21
5.1

6

2.3.1

Soldering information ...................................................................... 22

Digital interfaces ........................................................................... 23
6.1

IC serial interface ............................................................................ 23

6.2

I2C serial interface .......................................................................... 23

6.3

I2C operation................................................................................... 24

6.4

SPI bus interface ............................................................................. 25

6.5

SPI read .......................................................................................... 26

6.6

SPI write .......................................................................................... 27

6.7

SPI read in 3-wire mode .................................................................. 28
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LPS35HW

Contents

7

Registers address map ................................................................. 29

8

Register description ...................................................................... 31

9

10

8.1

INTERRUPT_CFG (0Bh) ................................................................ 31

8.2

THS_P_L (0Ch)............................................................................... 32

8.3

THS_P_H (0Dh) .............................................................................. 32

8.4

WHO_AM_I ..................................................................................... 32

8.5

CTRL_REG1 (10h).......................................................................... 33

8.6

CTRL_REG2 (11h).......................................................................... 34

8.7

CTRL_REG3 (12h).......................................................................... 35

8.8

FIFO_CTRL (14h) ........................................................................... 36

8.9

REF_P_XL (15h) ............................................................................. 37

8.10

REF_P_L_16h................................................................................. 37

8.11

REF_P_H_17h ................................................................................ 37

8.12

RPDS_L_18h .................................................................................. 38

8.13

RPDS_H_19h.................................................................................. 38

8.14

RES_CONF_1Ah ............................................................................ 38

8.15

INT_SOURCE_25h ......................................................................... 39

8.16

FIFO_STATUS_26h ........................................................................ 39

8.17

STATUS_27h .................................................................................. 40

8.18

PRESS_OUT_XL_28h .................................................................... 40

8.19

PRESS_OUT_L_29h ...................................................................... 42

8.20

PRESS_OUT_H_2Ah ..................................................................... 42

8.21

TEMP_OUT_L_2Bh ........................................................................ 42

8.22

TEMP_OUT_H_2Ch ....................................................................... 43

8.23

LPFP_RES_33h .............................................................................. 43

Package information ..................................................................... 44
9.1

CCLGA10L package information..................................................... 44

9.2

CCLGAA10L packing information ................................................... 45

Revision history ............................................................................ 47

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List of tables

LPS35HW

List of tables
Table 1: Device summary table .................................................................................................................. 1
Table 2: Pin description .............................................................................................................................. 7
Table 3: Pressure and temperature sensor characteristics ........................................................................ 8
Table 4: Electrical characteristics ............................................................................................................... 9
Table 5: SPI slave timing values ................................................................................................................. 9
Table 6: I2C slave timing values................................................................................................................ 10
Table 7: Absolute maximum ratings ......................................................................................................... 12
Table 8: Serial interface pin description.................................................................................................... 23
Table 9: I2C terminology ........................................................................................................................... 23
Table 10: SAD+Read/Write patterns ........................................................................................................ 24
Table 11: Transfer when master is writing one byte to slave ................................................................... 24
Table 12: Transfer when master is writing multiple bytes to slave ........................................................... 24
Table 13: Transfer when master is receiving (reading) one byte of data from slave ............................... 25
Table 14: Transfer when master is receiving (reading) multiple bytes of data from slave ....................... 25
Table 15: Registers address map ............................................................................................................. 29
Table 16: INTERRUPT_CFG (0Bh) register ............................................................................................. 31
Table 17: WHO_AM_I register .................................................................................................................. 32
Table 18: CTRL_REG1 (10h) register ...................................................................................................... 33
Table 19: Output data rate bit configurations ........................................................................................... 33
Table 20: Low-pass filter configurations ................................................................................................... 34
Table 21: CTRL_REG3 (12h) register ...................................................................................................... 35
Table 22: Interrupt configurations ............................................................................................................. 35
Table 23: CTRL_REG3 (12h) register ...................................................................................................... 36
Table 24: FIFO mode selection ................................................................................................................ 36
Table 25: REF_P_XL (15h) register ......................................................................................................... 37
Table 26: REF_P_L (16h) register ............................................................................................................ 37
Table 27: REF_P_H (17h) register ........................................................................................................... 37
Table 28: RPDS_L (18h) register ............................................................................................................. 38
Table 29: RPDS_H (19h) register ............................................................................................................. 38
Table 30: RES_CONF (1Ah) register ....................................................................................................... 38
Table 31: INT_SOURCE (25h) register .................................................................................................... 39
Table 32: FIFO_STATUS (26h) register ................................................................................................... 39
Table 33: FIFO_STATUS example: OVR/FSS details ............................................................................. 39
Table 34: STATUS (27h) register ............................................................................................................. 40
Table 35: PRESS_OUT_XL (28h) register ............................................................................................... 40
Table 36: PRESS_OUT_L (29h) register.................................................................................................. 42
Table 37: TEMP_OUT_L (2Bh) register ................................................................................................... 42
Table 38: TEMP_OUT_H (2Ch) register................................................................................................... 43
Table 39: CCLGA (3.5 x 3.5 x 1.85 mm) package mechanical data ........................................................ 44
Table 40: Reel dimensions for carrier tape of CCLGA10L package ........................................................ 46
Table 41: Document revision history ........................................................................................................ 47

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LPS35HW

List of figures

List of figures
Figure 1: Block diagram .............................................................................................................................. 6
Figure 2: Pin connections (bottom view) ..................................................................................................... 6
Figure 3: SPI slave timing diagram ........................................................................................................... 10
Figure 4: I2C slave timing diagram ........................................................................................................... 11
Figure 5: Pressure readings ..................................................................................................................... 14
Figure 6: Bypass mode ............................................................................................................................. 15
Figure 7: FIFO mode................................................................................................................................. 16
Figure 8: Stream mode ............................................................................................................................. 17
Figure 9: Dynamic-Stream mode .............................................................................................................. 18
Figure 10: Stream-to-FIFO mode ............................................................................................................. 18
Figure 11: Bypass-to-Stream mode .......................................................................................................... 19
Figure 12: Bypass-to-FIFO mode ............................................................................................................. 20
Figure 13: LPS35HW electrical connections (top view) ............................................................................ 21
Figure 14: Read and write protocol ........................................................................................................... 25
Figure 15: SPI read protocol ..................................................................................................................... 26
Figure 16: Multiple byte SPI read protocol (2-byte example) ................................................................... 27
Figure 17: SPI write protocol .................................................................................................................... 27
Figure 18: Multiple byte SPI write protocol (2-byte example) ................................................................... 27
Figure 19: SPI read protocol in 3-wire mode ............................................................................................ 28
Figure 20: "Threshold based" interrupt event ........................................................................................... 32
Figure 21: Interrupt events on INT_DRDY pin .......................................................................................... 36
Figure 22: Ceramic CCLGA 10L package outline .................................................................................... 44
Figure 23: CCLGA - 10L (3.5 x 3.5 x 1.85 mm) water resistance details ................................................. 45
Figure 24: Carrier tape information for CCLGA10L package ................................................................... 45
Figure 25: CCLGA10L tape and reel package orientation........................................................................ 46
Figure 26: Reel information carrier tape CCLGA10L package ................................................................. 46

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Block diagram and pin description

1

LPS35HW

Block diagram and pin description

MUX

Sensing
element

ADC+ digital filter

Low noiseanalog front endpQuadratic temperature
Compensation
32 Samples FIFO
Filter (32 samples average)

Figure 1: Block diagram

DSP for

Temperature
Compensation

I2C
SPI

Temperature
sensorVoltage andcurrent bias

Clock and timing

Sensor bias

Vdd_IO

SCL/SPC

Figure 2: Pin connections (bottom view)

1

2
3

RES

GND

9

4

SDA/SDI/SDO

GND

8

5

SDO/SA0

7

6
CS

10

INT_DRDYVDD

GAMS20160304EC-1016

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LPS35HW

Block diagram and pin description
Table 2: Pin descriptionPinnumberName

Function1

Vdd_IOPower supply for I/O pins

2

SCL SPCI2C serial clock (SCL)
SPI serial port clock (SPC)

3Reserved

Connect to GND

4

SDA
SDI
SDI/SDOI2C serial data (SDA)
4-wire SPI serial data input (SDI)
3-wire serial data input/output (SDI/SDO)

5

SDO SA0

4-wire SPI serial data output (SDO)
I2C less significant bit of the device address (SA0)6CS

SPI enable
I2C/SPI mode selection(1: SPI idle mode / I2C communication enabled; 0: SPI communication
mode / I2C disabled)

7

INT_DRDY

Interrupt or Data Ready8

GND

0 V supply

9

GND

0 V supply

10

VDD

Power supply

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Mechanical and electrical specifications

LPS35HW

2

Mechanical and electrical specifications

2.1

Mechanical characteristics
VDD= 1.8 V, T = 25 °C, unless otherwise noted.
Table 3: Pressure and temperature sensor characteristics
SymbolParameter

Test condition

Min.

Typ. aMax.

Unit

Pressure sensor characteristics
PTop

Operating temperature range

-40

+85

°C

PTfullFull accuracy temperature
range

0

+65

°C

Pop

Operating pressure range

260

1260

hPa

Pbits

Pressure output data

24

bits

Psens

Pressure sensitivity

4096

LSB/
hPa

PAccRelRelative accuracy overpressureb

P= 800 - 1100 hPa
T = 25 °C

±0.1

hPa

Pop
T= 0 to 65 °C
After OPC c±1

Pop
T= 0 to 65 °C no
OPCc

±4

PAccT

ODRPresAbsolute accuracy overtemperature

hPa

1
10
25
50
75

Pressure output data ratea

Hz

Temperature sensor characteristics
Top

Operating temperature range

Tsens

Temperature sensitivity

Tacc

Temperature absoluteaccuracy-40

T= 0 to 65 °C

a Typical specifications are not guaranteed.
b By design.
c OPC: One Point Calibration, see registers RPDS_L/H (18h,19h).

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°C

100

LSB/°C±1.5°CLPS35HW

Mechanical and electrical specifications
SymbolODRT

2.2

Parameter

Test condition

Min.

Typ. a

Max.

Unit

1
10
25
50
75

Output temperature data ratea

HzElectrical characteristics
VDD= 1.8 V, T = 25 °C, unless otherwise noted.
Table 4: Electrical characteristics
SymbolParameter

VDD

Supply voltage

Vdd_IOIO supply voltage

Test condition

Min.

Max.

Unit

1.7

3.6

V

1.7

Vdd+0.1

V@ODR 1 Hz
LC_EN bit =0
Idd

15

Supply currentµA@ODR 1 Hz
LC_EN bit =1

IddPdnTyp. b3

Supply current in power-down mode

1µA

1. Typical specifications are not guaranteed.

2.3

Communication interface characteristics

2.3.1

SPI serial peripheral interface
Subject to general operating conditions for Vdd and TOP.
Table 5: SPI slave timing values
ValuecSymbolParametertc(SPC)SPI clock cyclefc(SPC)SPI clock frequency

tsu(CS)

CS setup time6th(CS)

CS hold time

8

tsu(SI)SDI input setup time

5th(SI)SDI input hold time

15

Min.

Max.

100

Unit
ns

10

MHz

ns

a Output data rate is configured acting on ODR[2:0] in CTRL_REG1 (10h)b Typical specifications are not guaranteed.
c Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization

results, not tested in production.

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Mechanical and electrical specifications

LPS35HW
ValuecSymbolParametertv(SO)

SDO valid output timeth(SO)SDO output hold timetdis(SO)SDO output disable time

Min.

Unit

Max.
50

9
50

Figure 3: SPI slave timing diagram

GAMS20160304EC-1139

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

2.3.2

I2C inter - IC control interface
Subject to general operating conditions for Vdd and TOP.
Table 6: I2C slave timing values
SymbolParameter

I2C standard
modea

I2C fast modeb

Min.

Max.

Min.

Max.

100

0

400

f(SCL)SCL clock frequency0tw(SCLL)

SCL clock low time

4.7

1.3

tw(SCLH)

SCL clock high time

4.0

0.6

tsu(SDA)

SDA setup time

250

100

th(SDA)SDA data hold time

0.01

Unit
kHz
µs

3.45

a Data based onstandard I2C protocol requirement, not tested in production.
b Cb = total capacitance of one bus line, in pF.

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0

ns
0.9

µs

LPS35HW

Mechanical and electrical specifications
I2C standard
Symbolmodea

ParameterMin.

I2C fast modeb

Unit

Max.

Min.

Max.

tr(SDA)tr(SCL)SDA and SCL rise time

1000

20+
0.1Cb(2)300tf(SDA)tf(SCL)SDA and SCL fall time300

20+ 0.1C
(2)
b

300

th(ST)START condition hold time4

0.6

tsu(SR)

Repeated START condition setup
time

4.7

0.6

tsu(SP)

STOP condition setup time4

0.6

tw(SP:SR)Bus free time between STOP and
START condition

4.7

1.3

ns

µs

Figure 4: I2C slave timing diagram
REPEATED
START
START

tsu(SR)
tw(SP:SR)

SDA

tf(SDA)tsu(SDA)

tr(SDA)

STARTth(SDA)tsu(SP)STOP

SCLth(ST)

tw(SCLL)

tw(SCLH)

tr(SCL)tf(SCL)GAMS20160304EC-1156

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

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Mechanical and electrical specifications

2.4

LPS35HW

Absolute maximum ratings
Stress above those listed as “Absolute maximum ratings” may cause permanent damage tothe device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 7: Absolute maximum ratings
SymbolRatings

Maximum value

Unit

Vdd

Supply voltage-0.3 to 4.8

V

Vdd_IOI/O pins supply voltage-0.3 to 4.8

V

Vin

Input voltage on any control pin-0.3 to Vdd_IO +0.3

VP

Overpressure

2

MPa

TSTG

Storage temperature range-40 to+125

°C

ESD

Electrostatic discharge protection

2 (HBM)kV

Note: Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause
permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling cancause permanent damage to the part.

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3Functionality

Functionality
The LPS35HW is a high resolution, digital output pressure sensor packaged in an HLGA
full- mold package. The complete device includes a sensing element based on a
piezoresistive Wheatstone bridge approach, and an IC interface which communicates adigital signal from the sensing element to the application.

3.1

Sensing element
An ST proprietary process is used to obtain a silicon membrane for MEMS pressure
sensors. When pressure is applied, the membrane deflection induces an imbalance in the
Wheatstone bridge piezoresistances whose output signal is converted by the IC interface.

3.2

IC interface
The complete measurement chain is composed of a low-noise amplifier which converts theresistance unbalance of the MEMS sensors (pressure and temperature) into an analog
voltage using an analog-to-digital converter. The pressure and temperature data may beaccessed through an I²C/SPI interface thus making the device particularly suitable for directinterfacing with a microcontroller. The LPS35HW features a Data-Ready signal whichindicates when a new set of measured pressure and temperature data are available, thus
simplifying data synchronization in the digital system that uses the device.

3.3

Factory calibration
The trimming values are stored inside the device in a non-volatile structure. When thedevice is turned on, the trimming parameters are downloaded into the registers to be
employed during the normal operation which allows the device to be used without requiring
any further calibration.

3.4

How to interpret pressure readings
The pressure data are stored 3 registers: PRESS_OUT_H (2Ah), PRESS_OUT_L (29h),and PRESS_OUT_XL (28h). The value is expressed as 2’s complement. To obtain thepressure in hPa, take the two’s complement of the complete word and then divide by
4096LSB/hPa.

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Functionality

LPS35HW
Figure 5: Pressure readings

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LPS35HW

4

FIFO

FIFO
The LPS35HW embeds a 32-slot of 40-bit data FIFO to store the pressure and temperature
output values. This allows consistent power saving for the system, since the host processor
does not need to continuously poll data from the sensor, but it can wake up only whenneeded and burst the significant data out from the FIFO. This buffer can work according toseven different modes: Bypass mode, FIFO mode, Stream mode, Dynamic-Stream mode,
Stream-to-FIFO mode, Bypass-to-Stream and Bypass-to-FIFO mode. The FIFO buffer isenabled when the FIFO_EN bit in CTRL_REG2 (11h) is set to '1' and each mode isselected by the FIFO_MODE[2:0] bits in FIFO_CTRL (14h). Programmable FIFO thresholdstatus, FIFO overrun events and the number of unread samples stored are available in the
FIFO_STATUS (26h) register and can be set to generate dedicated interrupts on the
INT_DRDY pad using the CTRL_REG3 (12h) register.
FIFO_STATUS(FTH_FIFO) goes to '1' when the number of unread samples(FIFO_STATUS(FSS5:0)) is greater than or equal to WTM[4:0] in FIFO_CTRL (14h). If
FIFO_CTRL(WTM4:0) is equal to 0, FIFO_STATUS(FTH_FIFO) goes to '0'.
FIFO_STATUS(OVRN) is equal to '1' if a FIFO slot is overwritten. FIFO_STATUS(FSS5:0)
contains stored data levels of unread samples; when FSS[5:0] is equal to '000000' FIFO isempty, when FSS[5:0] is equal to '100000' FIFO is full and the unread samples are 32.
To guarantee the switching into and out of FIFO mode, discard the first sample acquired.

4.1

Bypass mode
In Bypass mode (FIFO_CTRL(FMODE2:0)=000), the FIFO is not operational and it
remains empty.
Bypass mode is also used to reset the FIFO when in FIFO mode.
As described in the next figure, for each channel only the first address is used. When new
data is available, the older data is overwritten.
Figure 6: Bypass mode

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FIFO

4.2

LPS35HWFIFO mode
In FIFO mode (FIFO_CTRL(FMODE2:0) = 001) data from the output
PRESS_OUT_H(2Ah), PRESS_OUT_L(29h), PRESS_OUT_XL(28h) andTEMP_OUT_H(2Ch), TEMP_OUT_L(2Bh) are stored in the FIFO until it is overwritten.
To reset FIFO content, Bypass mode the value '000' must be written in
FIFO_CTRL(FMODE2:0). After this reset command it is possible to restart FIFO mode
writing the value '001' in FIFO_CTRL(FMODE2:0).
FIFO buffer memorizes 32 levels of data but the depth of the FIFO can be resized by
setting the CTRL2(STOP_ON_FTH) bit. If the STOP_ON_FTH bit is set to '1', FIFO depth
is limited to FIFO_CTRL(WTM4:0) + 1 data.
A FIFO threshold interrupt can be enabled (F_OVR bit in CTRL3(12h) in order to be raised
when the FIFO is filled to the level specified by the WTM4:0 bits of FIFO_CTRL(14h).
When a FIFO threshold interrupt occurs, the first data has been overwritten and the FIFO
stops collecting data from the input pressure and temperature.
Figure 7: FIFO mode

4.3

Stream mode
Stream mode (FIFO_CTRL(FMODE2:0) = 010) provides continuous FIFO update: as new
data arrive, the older is discarded.
Once the entire FIFO has been read, the last data read still remains in the FIFO and hence
once a new sample is acquired, the FIFO_STATUS(FSS5:0) value rises from 0 to 2.
An overrun interrupt can be enabled, CTRL3(F_OVR) = '1', in order to inform when the
FIFO is full and eventually read its content all at once. If an overrun occurs, the oldest
sample in FIFO is overwritten, so if the FIFO was empty, the lost sample has already been
read.

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LPS35HW

FIFO
Figure 8: Stream mode

In the latter case reading all FIFO content before an overrun interrupt has occurred, the firstdata read is equal to the last already read in the previous burst, so the number of new data
available in FIFO depends on the previous reading.

4.4

Dynamic-Stream mode
In Dynamic-Stream mode (FIFO_CTRL(FMODE2:0) = 110) after emptying the FIFO, thefirst new sample that arrives becomes the first to be read in a subsequent read burst. In
this way the number of new data available in FIFO does not depend on the previous
reading.
In Dynamic-Stream mode FIFO_STATUS(FSS5:0) is the number of new pressure andtemperature samples available in the FIFO buffer.
Stream Mode is intended to be used reading all 32 samples of FIFO within an ODR after
receiving an overrun signal.
Dynamic-Stream is intended to be used to read FIFO_STATUS(FSS5:0) samples when it is
not possible to guarantee reading data within an ODR.
Also, a FIFO threshold interrupt on the INT_DRDY pad through CTRL3(F_FTH) can be
enabled in order to read data from the FIFO and leave free memory slots for incoming data.

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FIFO

LPS35HW
Figure 9: Dynamic-Stream mode

4.5

Stream-to-FIFO mode
In Stream-to-FIFO mode (FIFO_CTRL(FMODE2:0) = 011), FIFO behavior changes
according to the INT_SOURCE(IA) bit. When INT_SOURCE(IA) bit is equal to '1', FIFO
operates in FIFO mode. When the INT_SOURCE(IA) bit is equal to '0', FIFO operates in
Stream mode.
An interrupt generator can be set to the desired configuration through
INTERRUPT_CFG(0Bh).
The INTERRUPT_CFG(LIR) bit should be set to '1' in order to have latched interrupt.
Figure 10: Stream-to-FIFO mode

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4.6

FIFO

Bypass-to-Stream mode
In Bypass-to-Stream mode (FIFO_CTRL(FMODE2:0) = '100'), data measurement storage
inside FIFO operates in Stream mode when INT_SOURCE(IA) is equal to '1',otherwise
FIFO content is reset (Bypass mode). An interrupt generator can be set to the desiredconfiguration through INTERRUPT_CFG(0Bh).
The INTERRUPT_CFG(LIR) bit should be set to '1' in order to have latched interrupt.
Figure 11: Bypass-to-Stream mode

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FIFO

4.7

LPS35HW

Bypass-to-FIFO mode
In Bypass-to-FIFO mode (FIFO_CTRL(FMODE2:0) = '111'), data measurement storage
inside FIFO operates in FIFO mode when INT_SOURCE(IA) is equal to '1', otherwise FIFO
content is reset (Bypass mode). An interrupt generator can be set to the desiredconfiguration through INTERRUPT_CFG(0Bh).
The INTERRUPT_CFG (LIR) bit should be set to '1' in order to have latched interrupt.
Figure 12: Bypass-to-FIFO mode

4.8

Retrieving data from FIFO
FIFO data is read through PRESS_OUT_H(2Ah), PRESS_OUT_L(29h),
PRESS_OUT_XL(28h) and TEMP_OUT_H(2Ch), TEMP_OUT_L(2Bh) registers.
Each time data is read from the FIFO, the oldest data are placed in the
PRESS_OUT_H(2Ah), PRESS_OUT_L(29h), PRESS_OUT_XL(28h),TEMP_OUT_H(2Ch)
and TEMP_OUT_L(2Bh) registers and both single-read and read-burst operations can beused. The reading address is automatically updated by the device and it rolls back to 28hwhen register 2Ch is reached. In order to read all FIFO levels in a multiple byte reading,
160 bytes (5 output registers by 32 levels) must be read.

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5Application hints

Application hints
Figure 13: LPS35HW electrical connections (top view)The device power supply must be provided through the VDD line; power supply decoupling
capacitor C1 (100 nF) must be placed as near as possible to the supply pads of the device.
Depending on the application, an additional capacitor of 4.7 µF could be placed on VDD
line.The functionality of the device and the measured data outputs are selectable andaccessible through the I²C/SPI interface. When using the I2C, CS must be tied to Vdd_IO.
All the voltage and ground supplies must be present at the same time to have proper
behavior of the IC (refer to Figure 13: "LPS35HW electrical connections (top view)"). It is
possible to remove VDD while maintaining Vdd_IO without blocking the communicationbus, in this condition the measurement chain is powered off.

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Application hints

5.1

LPS35HW

Soldering information
The HLGA package is compliant with the ECOPACK® standard and it is qualified forsoldering heat resistance according to JEDEC J-STD-020.

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Digital interfaces

6

Digital interfaces

6.1

IC serial interface
The registers embedded in the LPS35HW may be accessed through both the I²C and SPI
serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wireinterface mode. The serial interfaces are mapped onto the same pads. To select/exploit theI²C interface, the CS line must be tied high (i.e. connected to Vdd_IO).
Table 8: Serial interface pin description

6.2

Pin name

Pin descriptionCS

SPI enable
I²C/SPI mode selection (1: SPI idle mode /I2Ccommunication enabled; 0: SPI
communication mode / I2C disabled)

SCL/SPCI²C serial clock (SCL)
SPI serial port clock (SPC)SDA SDI
SDI/SDOI²C serial data (SDA)
4-wire SPI serial data input (SDI)
3-wire serial data input /output (SDI/SDO)

SDO
SAO

SPI serial data output (SDO)
I²C less significant bit of the device address (SA0)

I2C serial interface
The LPS35HW I²C is a bus slave. The I²C is employed to write data into registers whose
content can also be read back.
The relevant I²C terminology is given in Table 9: "I2C terminology".
Table 9: I2C terminology
Term

Description

Transmitter

The device which sends data to the bus

ReceiverThe device which receives data from the bus

Master

The device which initiates a transfer, generates clock signals and terminates a transfer

Slave

The device addressed by the master

There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bi-directional line used for sending and receiving the data
to/from the interface. Both lines have to be connected to Vdd_IO through pull-up resistors.
The I²C interface is compliant with fast mode (400 kHz) I²C standards as well as with thenormal mode.

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6.3

LPS35HWI2C operation
The transaction on the bus is started through a START (ST) signal. A start condition isdefined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next data byte
transmitted after the start condition contains the address of the slave in the first 7 bits andthe eighth bit tells whether the master is receiving data from the slave or transmitting data
to the slave. When an address is sent, each device in the system compares the first sevenbits after a start condition with its address. If they match, the device considers itself
addressed by the master.
The slave address (SAD) associated to the LPS35HW is 101110xb. The SDO/SA0pad canbe used to modify the less significant bit of the device address. If the SA0 pad is connected
to voltage supply, LSb is ‘1’ (address 1011101b), otherwise if the SA0 pad is connected to
ground, the LSb value is ‘0’ (address 1011100b). This solution permits to connect andaddress two different LPS35HW devices to the same I²C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that itremains stable low during the HIGH period of the acknowledge clock pulse. A receiver
which has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded inside the ASIC behaves like a slave device and the following protocol
must be adhered to. After the start condition (ST) a slave address is sent, once a slaveacknowledge has been returned (SAK), an 8-bit sub-address will be transmitted (SUB): the7 LSB represent the actual register address while the MSB has no meaning. The
IF_ADD_INC bit in CTRL2 register (11h) enables sub-address auto increment(IF_ADD_INC is '1' by default), so if IF_ADD_INC = '1' the SUB (sub-address) will be
automatically increased to allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’(Write) the master will transmit to the slave with direction unchanged. Table 10:"SAD+Read/Write patterns" explains how the SAD+read/write bit pattern is composed,
listing all the possible configurations.
Table 10: SAD+Read/Write patterns
CommandSAD[6:1]

SAD[0]=SA0

R/W

SAD+R/W

Read

1011100

110111001 (B9h)

Write1011100010111000 (B8h)

Read1011101

110111011 (BBh)Write1011101

010111010 (BAh)Table 11: Transfer when master is writing one byte to slave
MasterST

SAD +W

SUB

Slave

DATA

SAK

SP

SAK

SAK

Table 12: Transfer when master is writing multiple bytes to slave
Master
Slave

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ST

SAD+ W

SUB
SAK

DATA
SAK

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Digital interfaces
Table 13: Transfer when master is receiving (reading) one byte of data from slave

MasterST

SAD+ W

Slave

SUB
SAK

SR

SAD+ R

SAK

NMAK
SAK

SP

DATA

Table 14: Transfer when master is receiving (reading) multiple bytes of data from slave
Mast
er
Slave

S
T

SAD+
W

SU
B
SA
K

S
R
SA
K

SAD+
R

MA
K
SA
K

DAT
A

MA
K
DAT
A

NMA
K

S
P

DAT
A

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The numberof bytes transferred per transfer is unlimited. Data is transferred with the most significant bit(MSb) first. If a receiver can’t receive another complete byte of data until it has performedsome other functions, it can hold the clock line, SCL LOW to force the transmitter into a
wait state. Data transfer only continues when the receiver is ready for another byte andreleases the data line. If a slave receiver does not acknowledge the slave address (i.e. it is
not able to receive because it is performing some real-time function) the data line must be
kept HIGH by the slave. The master can then abort the transfer. A LOW-to-HIGH transitionon the SDA line while the SCL line is HIGH is defined as a STOP condition. Each datatransfer must be terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes incrementing the register address, it is necessary to assert
the most significant bit of the sub-address field. In other words, SUB(7) must be equal to 1
while SUB(6-0) represents the address of the first register to be read.
In the presented communication format MAK is Master acknowledge and NMAK is nomaster acknowledge.

6.4

SPI bus interface
The LPS35HW SPI is a bus slave. The SPI allows writing to and reading from the registersof the device.The serial interface interacts with the outside world with 4 wires: CS, SPC,SDI and SDO.
Figure 14: Read and write protocol

CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of
the transmission and returns to high at the end. SPC is the serial port clock and it iscontrolled by the SPI master. It is stopped high when CS is high (no transmission). SDI andSDO are respectively the serial port data input and output. Those lines are driven at thefalling edge of SPC and should be captured at the rising edge of SPC. Both the read
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LPS35HW
register and write register commands are completed in 16 clock pulses or in multiples of 8
in the case of multiple read/write bytes. Bit duration is the time between two falling edges of
SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS
while the last bit (bit 15, bit 23,...) starts at the last falling edge of SPC just before the risingedge of CS.bit0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, thedata DO(7:0) from the device is read. In the latter case, the chip will drive SDO at the startof bit 8.
bit1-7: address AD(6:0). This is the address field of the indexed register.
bit8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods are added. When the
IF_ADD_INC bit is 0, the address used to read/write data remains the same for every
block. When the IF_ADD_INC bit is 1, the address used to read/write data is incremented
at every block.
The function and the behavior of SDI and SDO remain unchanged.

6.5

SPI read
Figure 15: SPI read protocol

The SPI read command is performed with 16 clock pulses. The multiple byte readcommand is performed by adding blocks of 8 clock pulses to the previous one.
bit0: READ bit. The value is 1.
bit1-7: address AD(6:0). This is the address field of the indexed register.
bit8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
bit16-...: data DO(...-8). Further data in multiple byte reads.

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Digital interfaces
Figure 16: Multiple byte SPI read protocol (2-byte example)

6.6

SPI write
Figure 17: SPI write protocol

CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0

The SPI write command is performed with 16 clock pulses. The multiple byte write
command is performed by adding blocks of 8 clock pulses to the previous one.bit0: WRITE
bit. The value is 0.bit1-7: address AD(6:0). This is the address field of the indexed register.
bit8-15: data DI(7:0) (write mode). This is the data that is written in the device (MSb first).
bit16-...: data DI(...-8). Further data in multiple byte writes.
Figure 18: Multiple byte SPI write protocol (2-byte example)

CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0

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Digital interfaces

6.7

LPS35HWSPI read in 3-wire mode
A 3-wire mode is entered by setting bit SIM to ‘1’ (SPI serial interface mode selection) in
CTRL_REG1.
Figure 19: SPI read protocol in 3-wire mode

CS
SPC
SDI/O
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

RWMS
AD6 AD5 AD4 AD3 AD2 AD1 AD0

The SPI read command is performed with 16 clock pulses:
bit0: READ bit. The value is 1.
bit1-7: address AD(6:0). This is the address field of the indexed register.
bit8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.

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7Registers address map

Registers address map
Table 15 provides a quick overview of the 8-bit registers embedded in the device.
Table 15: Registers address map
Register name

Type

Reserved

Register address

Default

Hex

Binary00 -0A-

Function and comment
Reserved

INTERRUPT_CFG

R/W

0B

00000000

THS_P_L

R/W

0C

00000000

THS_P_H

R/W

0D

00000000Reserved-

0E-

Reserved

WHO_AM_I

R

0F

10110001

Who am I

CTRL_REG1

R/W

1000000000CTRL_REG2R/W

1100010000CTRL_REG3R/W

1200000000Interrupt control

Reserved-

13-

Reserved

FIFO_CTRL

R/W

1400000000

REF_P_XL

R/W

1500000000

REF_P_L

R/W

1600000000

REF_P_H

R/W

1700000000

RPDS_L

R/W

1800000000

RPDS_H

R/W

1900000000RES_CONF

R/W

1A

00000000Reserved-

1B- 24-

INT_SOURCE

R

25

-

FIFO_STATUS

R

26

-

STATUS

R

27-

PRESS_OUT_XL

R

28

-

PRESS_OUT_L

R

29

-

PRESS_OUT_H

R

2A

-

TEMP_OUT_L

R

2B

-

TEMP_OUT_H

R

2C

-

Reserved-

2D- 32-

LPFP_RES

R

33-

Reserved

Reserved

Registers marked as Reserved must not be changed. Writing to those registers may cause
permanent damage to the device.

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Registers address map
LPS35HW
To guarantee the proper behavior of the device, all register addresses not listed in theabove table must not be accessed and the content stored in those registers must not bechanged.
The content of the registers that are loaded at boot should not be changed. They containthe factory calibration values. Their content is automatically restored when the device ispowered up.

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8Register description

Register description
The device contains a set of registers which are used to control its behavior and to retrievepressure and temperature data. The register address, made up of 7 bits, is used to identify
them and to read/write the data through the serial interface.

8.1

INTERRUPT_CFG (0Bh)
Table 16: INTERRUPT_CFG (0Bh) register
7

6

5

4

AUTORIFPRESET_ARP

AUTOZEROAUTORIFPAUTORIFP: AutoRifP function enable. Default value: 0. (0: normal mode; 1:AutoRifP
enabled)RESET_ARPReset AutoRifP function. Default value: 0.(0: normal mode; 1: reset AutoRifP
function)

AUTOZERO

Autozero enable. Default value: 0.
(0: normal mode; 1:Autozero enabled)

RESET_AZ

Reset Autozero function. Default value: 0. (0: normal mode; 1: reset Autozero
function)

DIFF_EN

Interrupt generation enable. Default value: 0(0: interrupt generation disabled; 1: interrupt generation enabled)

LIR

Latch interrupt request to the INT_SOURCE register. Default value: 0. (0: interrupt
request not latched; 1: interrupt request latched)

PLE

Enable interrupt generation on differential pressure low event. Default value: 0.(0:disable interrupt request; 1: enable interrupt request on measured differential
pressure value lower than preset threshold)

PHE

Enable interrupt generation on differential pressure high event. Default value: 0. (0:disable interrupt request; 1: enable interrupt request on measured differential
pressure value higher than preset threshold)

RESET_AZ

3

2

1

0

DIFF_EN

LIR

PLE

PHE

To generate an interrupt event based on a user defined threshold, DIFF_EN bit must be set
to '1' and the threshold values stored in THS_P_L (0Ch) and THS_P_H (0Dh).
When DIFF_EN = '1', PHE bit or PLE bit or both bits have to be enabled. PHE and PLE bits
enable the interrupt generation on the positive or negative event respectively.
When DIFF_EN is enabled and AUTOZERO or AUTORIFP is enabled, the definedpressure threshold values in THS_P (0Ch, 0Dh) is compared with:
P_DIFF_IN=measured pressure - pressure reference
The value of pressure reference is assigned depending on the AUTOZERO and
AUTORIFP modes reported in the next two paragraphs.

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Figure 20: "Threshold based" interrupt event

If AUTOZERO bit is set to '1', the measured pressure is used as reference on the register
REF_P (15h, 16h and 17h). From now on, the output pressure registers PRESS_OUT(PRESS_OUT_H(2Ah), PRESS_OUT_L(29h) and PRESS_OUT_XL(28h)) are updated
and the same value is also used for the interrupt generation: PRESS_OUT = measured
pressure - REF_P
After the first conversion AUTOZERO bit is automatically set to '0'. To return back tonormal mode, RESET_AZ bit has to be set to '1'. This reset also the content of the REF_P
registers. If AUTORIFP bit is set to '1', the measured pressure is used as reference on theregister REF_P (15h, 16h and 17h). The output registers PRESS_OUT(PRESS_OUT_H(2Ah), PRESS_OUT_L(29h) and PRESS_OUT_XL(28h)) show thedifference between the measured pressure and the content of the RPDS registers (18h and19h): PRESS_OUT = measured pressure - RPDS*256
After the first conversion AUTORIFP bit is automatically set to '0'. To return back to normalmode, RESET_ARP bit has to be set to '1'.

8.2

THS_P_L (0Ch)
Least significant bits of the threshold value for pressure interrupt generation.

8.3

THS_P_H (0Dh)
Most significant bits of the threshold value for pressure interrupt generation.
7

6

5

THS15

THS14

THS13

THS[15:8]

8.4

4
THS12

3

2

1

0

THS11

THS10

THS9

THS8

This register contains the high part of threshold value for pressure interrupt generation.
Refer to Section 10.2: "THS_P_L (0Ch)"

WHO_AM_I
Device Who am I
Table 17: WHO_AM_I register
7
1

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6
0

5
1

4
1

3
0

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0

1
0

0
1

LPS35HW

8.5

Register description

CTRL_REG1 (10h)Control register 1
Table 18: CTRL_REG1 (10h) register
7

6

5

4

0a

ODR2

ODR1

ODR0

3

2

1

0

EN_LPFPLPFP_CFGBDUSIM

ODR [2:0]

Output data rate selection. Default value: 000 Refer to Table 19: "Output data rate bit
configurations".

EN_LPFP

Enable low-pass filter on pressure data. Default value: 0 (0: Low-pass filter disabled; 1:
Low-pass filter enabled)

LPFP_CFG

LPF_CFG: Low-pass configuration register. Default value:0 Refer to Table 20: "Lowpass filter configurations".

BDUb

Block data update. Default value: 0 (0: continuous update;
1:output registers not updated until MSB and LSB have been read)SIM

SPI Serial Interface Mode selection. Default value: 0(0: 4-wire interface; 1: 3-wireinterface)

ODR2

ODR1

ODR0

Pressure (Hz)

0

0

0

Power down / One shot mode enabled

0

0

1

1 Hz

1 Hz

0

1

0

10 Hz

10 Hz

0

1

1

25 Hz

25 Hz

1

0

0

50 Hz

50 Hz

1

0

1

75 Hz

75 Hz

Table 19: Output data rate bit configurations
Temperature (Hz)When ODR bits are set to '000' the device is in Power down mode. When the device is in
power-down mode, almost all internal blocks of the device are switched off to minimize
power consumption. I2C interface is still active to allow communication with the device. The
configuration registers content is preserved and output data registers are not updated,
therefore keeping the last data sampled in memory before going into power- down mode.
If ONE_SHOT bit in CTRL_REG2(11h) is set to '1', One-shot mode is triggered and a newacquisition starts when it is required. This enabling is effective only if the device waspreviously in power-down mode (ODR bits set to '000'). Once the acquisition is completed
and the output registers updated, the device automatically enters in power down mode.
ONE_SHOT bit self-clears itself.
When ODR bits are set to a value different than '000', the device is in Continuous mode
and automatically acquires a set of data (pressure and temperature) at the frequency
selected through ODR[2,0] bits.

aThis bit must be set to ‘0’ for proper operation of the deviceb To guarantee the correct behavior of BDU feature, th PRESS_OUT_H (2Ah) must be the last address read.

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Register description
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Once the additional low pass filter has been enable through the EN_LPFP bit, it is possible
to configure the device bandwidth acting on LPFP_CFG bit. Refer to Table 20: "Low-passfilter configurations".
Table 20: Low-pass filter configurations
EN_LPFPLPFP_CFG

Additional low pass filter status

Device bandwidth0xDisabled

ODR/2

1

0

Enabled

ODR/9

1

1

EnabledODR/20

The BDU bit is used to inhibit the update of the output registers between the reading ofupper and lower register parts. In default mode (BDU = ‘0’), the lower and upper registerparts are updated continuously. When the BDU is activated (BDU = ‘1’), the content of theoutput registers is not updated until PRESS_OUT_H is read, avoiding the reading of values
related to different samples.

8.6

CTRL_REG2 (11h)Control register 2
7

6

5

4

BOOT

FIFO_EN

STOP_ON_FTH

IF_ADD_INC

3

2

1

0

I2C_DISSWRESET0a

ONE_SHOTBOOT

Reboot memory content. Default value: 0.
(0: normal mode; 1: reboot memory content). The bit is self-cleared when the
BOOT is completed.

FIFO_EN

FIFO enable. Default value: 0.(0: disable; 1: enable)

STOP_ON_FTH

Stop on FIFO threshold. Enable FIFO watermark level use. Default value 0 (0:disable; 1: enable)

IF_ADD_INC

Register address automatically incremented during a multiple byte access with aserial interface (I2C or SPI). Default value 1.
(0: disable; 1enable)

I2C_DIS

Disable I2C interface. Default value 0. (0: I2C enabled;1: I2C disabled)

SWRESET

Software reset. Default value: 0.
(0: normal mode; 1: software reset).
The bit is self-cleared when the reset is completed.

ONE_SHOTOne-shot enable. Default value: 0.
(0: idle mode; 1: anew dataset is acquired)

The BOOT bit is used to refresh the content of the internal registers stored in the Flashmemory block. At device power-up the content of the Flash memory block is transferred tothe internal registers related to the trimming functions to allow correct behavior of thedevice itself. If for any reason the content of the trimming registers is modified, it issufficient to use this bit to restore the correct values. When the BOOT bit is set to ‘1’, thecontent of the internal Flash is copied inside the corresponding internal registers and isused to calibrate the device. These values are factory trimmed and they are different fora This bit must be set to ‘0’ for proper operation of the device.

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Register description
every device. They allow correct behavior of the device and normally they should not bechanged. At the end of the boot process the BOOT bit is set again to ‘0’ by hardware. The
BOOT bit takes effect after one ODR clock cycle.
SWRESET is the software reset bit. The following device registers (INTERRUPT_CFG,
THS_P_L, THS_P_H, CTRL_REG1, CTRL_REG2, CTRL_REG3, FIFO_CTRL,
RIF_P_XL,RIF_P_L,RIF_P_H) are reset to the default value if the SWRESET bit is set to'1'. SWRESET bit comes back to '0' by hardware.
The ONE_SHOT bit is used to start a new conversion when the ODR[2,0] bits in
CTRL_REG1(10h)are set to ‘000’. Writing a ‘1’ in ONE_SHOT triggers a single
measurement of pressure and temperature. Once the measurement is done, the
ONE_SHOT bit will self-clear, the new data are available in the output registers, and the
STATUS_REG bits are updated.

8.7

CTRL_REG3 (12h)Control register 3 - INT_DRDY pin control register
Table 21: CTRL_REG3 (12h) register
7

6

5

4

INT_H_L

PP_OD

F_FSS5

INT_H_LInterrupt active-high/low. Default value: 0.(0: active high; 1: active low)

PP_OD

Push-pull/open drain selection on interrupt pads. Default value: 0. (0: push-pull; 1: open
drain)F_FSS5

FIFO full flag on INT_DRDY pin. Default value: 0. (0: Disable; 1: Enable)

F_FTH

FIFO threshold (Watermark) status on INT_DRDY pin. Default value: 0. (0: Disable; 1:
Enable)F_OVR

FIFO overrun interrupt on INT_DRDY pin. Default value: 0. (0: Disable; 1: Enable)

DRDY

Data-ready signal on INT_DRDY pin. Default value: 0. (0: Disable; 1: Enable)

INT_S[2:1]

Data signal on INT_DRDY pin control bits. Default value: 00. Refer to Table 22:"Interrupt configurations".

INT_S2

INT_S100Data signal (in order of priority: PTH_DRDY or F_FTH or
F_OVR or F_FSSS5

0

1

Pressure high (P_high)10Pressure low (P_low)

1

1

Pressure low OR high

F_FTH

3

2

1

0

F_OVR

DRDY

INT_S2

INT_S1

Table 22: Interrupt configurations
INT_DRDY pin configuration

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Figure 21: Interrupt events on INT_DRDY pin

8.8

FIFO_CTRL (14h)
FIFO control register
Table 23: CTRL_REG3 (12h) register
7

6

5

4

F_MODE2

F_MODE1

F_MODE0

F_MODE[2:0]

FIFO mode selection. Default value: 000.
Refer to Table 24: "FIFO mode selection"and Section 6: "FIFO" for additional details.

WTM[4:0]

FIFO watermark level selection.

WTM4

3

2

1

0

WTM3

WTM2

WTM1

WTM0

Table 24: FIFO mode selection

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F_MODE2

F_MODE1

F_MODE0000

Bypass mode

0

0

1

FIFO mode010Stream mode

0

1

1

Stream-to-FIFO mode

1

0

0

Bypass-to-Stream mode

1

0

1

Reserved1

1

0

Dynamic-Stream mode

1

1

1

Bypass-to-FIFO mode

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8.9

Register description

REF_P_XL (15h)Reference pressure (LSB data)
Table 25: REF_P_XL (15h) register
7

6

5

REFL7

REFL6

REFL5

REFL[7:0]

4
REFL4

3

2

1

0

REFL3

REFL2

REFL1

REFL0

This register contains the low part of the reference pressure value.

The Reference pressure value is a 24-bit data and it is composed of Section 10.11:"REF_P_H_17h", Section 10.10: "REF_P_L_16h" and Section 10.9: "REF_P_XL (15h)".
The value is expressed as 2’s complement.
The reference pressure value is used when AUTOZERO or AUTORIFP function isenabled(refer to the Section 10.7: "CTRL_REG3 (12h)" register) and for the Autozero
function (refer to the Section 10.1: "INTERRUPT_CFG (0Bh)" register).

8.10

REF_P_L_16h
Reference pressure (middle part)
Table 26: REF_P_L (16h) register
7

6

5

4

REFL15

REFL14

REFL13

REFL12

3

2

1

0

REFL11

REFL10

REFL9

REFL8

This register contains the mid part of the reference pressure value.
REFL[15:8]

8.11

Refer to Section 10.9: "REF_P_XL (15h)".

REF_P_H_17h
Reference pressure (MSB part)
Table 27: REF_P_H (17h) register
7

6

5

4

REFL23

REFL22

REFL21

REFL20

3

2

1

0

REFL19

REFL18

REFL17

REFL16This register contains the high part of the reference pressure value.
REFL[23:16]

Refer to Section 10.9: "REF_P_XL (15h)".

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Register description

8.12

LPS35HW

RPDS_L_18h
Pressure offset (LSB data)
Table 28: RPDS_L (18h) register
7

6

5

RPDS7

RPDS6

RPDS5

RPDS[7:0]

4
RPDS4

3

2

1

0

RPDS3

RPDS2

RPDS1

RPDS0

This register contains the low part of the pressure offset value.

If, after the soldering of the component, a residual offset is still present, it can be removed
with a one-point calibration.
After the soldering, the measured offset can be stored in the Section 10.13:"RPDS_H_19h" and Section 10.12: "RPDS_L_18h" registers and automatically subtracted
from the pressure output registers: the output pressure register PRESS_OUT (28h, 29h
and 2Ah) is provided as the difference between the measured pressure and the content of
the register 256*RPDS (18h, 19h)*.
*DIFF_EN = '0', AUTOZERO = '0', AUTORIFP = '0'

8.13

RPDS_H_19h
Pressure offset (MSB data)
Table 29: RPDS_H (19h) register
7

6

5

4

RPDS15

RPDS14

RPDS13

RPDS123

2

1

0

RPDS11

RPDS10

RPDS9

RPDS8

This register contains the high part of the pressure offset value.
RPDS[15:8]

8.14

Refer to Section 10.12: "RPDS_L_18h"

RES_CONF_1Ah
Low-power mode configuration
Table 30: RES_CONF (1Ah) register
7

6

5

0

0

0

(1)

(1)

(1)

4
0

(1)

3

2

1

0

0

Reserved

(1)

(1)

0
(2)

LC_EN

Notes:(1)These bits must be set to ‘0’ for proper operation of the device.
(2)The content of this bit must not be modified for proper operation of the device

Low current mode enable. Default 0.
LC_EN (1)0: Normal mode (low-noise mode); 1: Low-current mode).

Notes:(1)The LC_EN bit must be changed only with the device in power down and not during operation. Once LC_EN bit

is configured, it affects both One-shot mode and Continuous mode.

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LPS35HW

8.15

Register description

INT_SOURCE_25h
Interrupt source
Table 31: INT_SOURCE (25h) register

8.16

7

6

5

BOOT_STATUS

0

0

4
0

3

2

1

0

0

IA

PL

PH

BOOT_STATUS

If ‘1’ indicates that the Boot (Reboot) phase is running.

IAInterrupt active.
(0: no interrupt has been generated;
1: one or more interrupt events have been generated).

PL

Differential pressure Low.
(0: no interrupt has been generated;
1: Low differential pressure event has occurred).

PH

Differential pressure High.
(0: no interrupt has been generated;
1: High differential pressure event has occurred).

FIFO_STATUS_26h
FIFO status
Table 32: FIFO_STATUS (26h) register
7

6

5

FTH_FIFO

OVR

FSS5

4
FSS4

3

2

1

0

FSS3

FSS2

FSS1

FSS0

FIFO threshold status.
FTH_FIFO(0: FIFO filling is lower than treshold level,
1: FIFO filling is equal or higher than treshold level).

OVR

FIFO overrun status.
(0: FIFO is not completely full;
1: FIFO is full and at least one sample in the FIFO has been overwritten).

FSS[5:0]

FIFO stored data level.
(000000: FIFO empty, 100000: FIFO is full and has 32 unread samples).

Table 33: FIFO_STATUS example: OVR/FSS details
FTH

OVRN

FSS5

FSS4

FSS3

FSS2

FSS1

FSS0

Description

0

0

0

0

0

0

0

0

FIFO empty-- (1)

0

0

0

0

0

0

1

1 unread sample

0

1

0

0

0

0

0

32 unread sample

...
--(1)

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Register description

LPS35HW

FTH

OVRN

FSS5

FSS4

FSS3

FSS2

FSS1

FSS0

1

1

1

0

0

0

0

0

Description
At least one sample have been
overwritten

Notes:(1)When the number of unread samples in FIFO is greater than the threshold level set in register Section 10.8:"FIFO_CTRL (14h)", FTH value is ‘1’.

8.17

STATUS_27h
Status register
Table 34: STATUS (27h) register
7

6

5

4

--

--

T_OR

P_OR

3

2

1

0

--

--

T_DA

P_DA

Temperature data overrun.
T_OR(0: no overrun has occurred;
1: a new data for temperature has overwritten the previous one)

P_OR

Pressure data overrun.
(0: no overrun has occurred;
1: new data for pressure has overwritten the previous one)

T_DA

Temperature data available.
(0: new data for temperature is not yet available;
1: new data for temperature is available)

P_DA

Pressure data available.
(0: new data for pressure is not yet available;
1: new data for pressure is available)

This register is updated every ODR cycle.

8.18

PRESS_OUT_XL_28h
Pressure output value (LSB)
Table 35: PRESS_OUT_XL (28h) register
7

6

5

POUT7

POUT6

POUT5

POUT[7:0]

4
POUT4

3

2

1

0

POUT3

POUT2

POUT1

POUT0

This register contains the low part of the pressure output value.

The pressure output value is a 24-bit data that contains the measured pressure. It is
composed of Section 10.20: "PRESS_OUT_H_2Ah", Section 10.19: "PRESS_OUT_L_29h"
and Section 10.18: "PRESS_OUT_XL_28h" . The value is expressed as 2’s complement.
The output pressure register PRESS_OUT is provided as the difference between themeasured pressure and the content of the register RPDS (18h, 19h)*.
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Register description
Please refer to section Section 5.4: "How to interpret pressure readings" for additional info.
*DIFF_EN = '0', AUTOZERO = '0', AUTORIFP = '0'

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Register description

8.19

LPS35HWPRESS_OUT_L_29h
Pressure output value (mid part)
Table 36: PRESS_OUT_L (29h) register
7

6

5

POUT15

POUT14

POUT13

4
POUT123

2

1

0

POUT11

POUT10

POUT9

POUT8

This register contains the mid part of the pressure output value.
POUT[15:8]

8.20

Refer to Section 10.18: "PRESS_OUT_XL_28h".

PRESS_OUT_H_2Ah
Pressure output value (MSB)
7

6

5

4

POUT23

POUT22

POUT21

POUT203

2

1

0

POUT19POUT18

POUT17

POUT16This register contains the low part of the pressure output value.
POUT[23:16]

8.21

Refer to Section 10.18: "PRESS_OUT_XL_28h".

TEMP_OUT_L_2Bh
Temperature output value (LSB)
Table 37: TEMP_OUT_L (2Bh) register
7

6

5

TOUT7

TOUT6

TOUT5

TOUT[7:0]

4
TOUT4

3

2

1

0

TOUT3

TOUT2

TOUT1

TOUT0

This register contains the low part of the temperature output value.

The temperature output value is a 16-bit data that contains the measured temperature. It is
composed of Section 10.22: "TEMP_OUT_H_2Ch", and Section 10.21:"TEMP_OUT_L_2Bh". The value is expressed as 2’s complement.

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8.22

Register description

TEMP_OUT_H_2Ch
Temperature output value (MSB)
Table 38: TEMP_OUT_H (2Ch) register
7

6

5

TOUT15

TOUT14

TOUT13

TOUT[15:8]

4
TOUT123

2

1

0

TOUT11

TOUT10

TOUT9

TOUT8

This register contains the high part of the temperature output value.

The temperature output value is a 24-bit data that contains the measured temperature. It is
composed of Section 10.20: "PRESS_OUT_H_2Ah", and Section 10.18:"PRESS_OUT_XL_28h". The value is expressed as 2’s complement.

8.23

LPFP_RES_33h
Low-pass filter reset register.
If the LPFP is active, in order to avoid the transitory phase, the filter can be reset byreading this register before getting out pressure measurements.

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Package information

9

LPS35HW

Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

9.1

CCLGA10L package information
Figure 22: Ceramic CCLGA 10L package outline

Table 39: CCLGA (3.5 x 3.5 x 1.85 mm) package mechanical data

44/48

Item

Dimension (mm)Tolerance (mm)Length

3.5

±0.15

Width

3.5

±0.15

Height

1.85

±0.15

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LPS35HW

Package information
Figure 23: CCLGA - 10L (3.5 x 3.5 x 1.85 mm) water resistance details

9.2

CCLGAA10L packing information
Figure 24: Carrier tape information for CCLGA10L package

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Package information

LPS35HW
Figure 25: CCLGA10L tape and reel package orientation

Figure 26: Reel information carrier tape CCLGA10L package
T

40mm min.
Access hole atslot location
B
C

A

N

D

G measured at hub

Full radius

Tape slot
in core fortape start
2.5mm min. width

Table 40: Reel dimensions for carrier tape of CCLGA10L package
Reel dimensions (mm)46/48

A (max)330

B (min)1.5

C

13 ±0.25

D (min)20.2

N (min)60

G12.4 +2/-0

T (max)18.4

DocID029129 Rev 1

LPS35HW

10

Revision history

Revision history
Table 41: Document revision history
Date

VersionChanges

18-Jul-2016

1

Initial release.

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LPS35HWIMPORTANT NOTICE – PLEASE READ CAREFULLYSTMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, andimprovements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or thedesign of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2016 STMicroelectronics – All rights reserved

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