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for multi-path execution

Yuichiro Ajima, Tomohiro Nakamura, Kenji Kise, Hidenori Tsuji, Hidehiko Tanaka
University of Tokyo, Graduate School of Engineering
It is pointed out in several papers that it is possible to gain higher
IPC(Instructions Per Cycle) by speculative multi-path execution. However, because past micro-processors were designed for single-path execution, new architecture for speculative multi-path execution is required. In this paper, we discussproblems of applying existing exception recovery mechanism to multi-path execution, and propose a new exception recovery and operand supply model to solve
the problems.

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X\JU[1] James E.Smith: \Implementation ofPrecise Interrupts in Pipelined Processors.", Proc.12th ISCA, pp.36-44(1985)[2] Wen-mei W.Hwu and Yale N.Patt:\Checkpoint Repair for Out-oforder Execution Machines." Proc.14thISCA, pp.18-26 (1987)[3] Mike Johnson: \Superscalar Microprocessor Design", Prentice-Hall (1991)[4] Augustus K.Uht and Vijay Sindagi:\Disjoint Eager Execution: An Optimal Form of Speculative Execution",
MICRO-28, pp.313-325 (1995)[5]

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