SCIMA 1 4857  6 9231V  y L  My

 Oyy  N y¨©«½®¹¹ª³½¥¹ÉÎº°±µ Í­¦¶§¤ÀäôËñøÊËÓ»ÂÍñøÏÍùëãçÊÄÈºâü#Í!æÕ£¤¬þÌàöÄÆ°±µØÚé¬¸ ¤Í½¥
£² SCIMA (Software Controlled Integrated Memory Architecture) ÀÜ ÃÔÈ¿Ó»ðÖÉÎº HPC ¬µ½´¹Í!ÇÉ¾Ó"ÛÍ0áò÷êÞÕ SCIMA ¯³·½¢þÉå%ÄºSCIMA ÍÆÒÍ¡«¦ÙÝ$ãçÕìíÅÓ»Software Optimization Methods for SCIMA Architecture
Minoru Nakamura,y Makoto Iwashita,yy Shuichi Sakaiyand Hidehiko Tanakay
Memory system has been a performance bottleneck in High Performance Computing World.
To solve this problem, SCIMA (Software Controlled Integrated Memory Architecture) which
integrates controllable SRAM memory inside the processor chip, has been proposed. In thispaper, we examineproblem, evaluate performance ofSCIMA architecture, and propose software optimization methods for SCIMA architecture.

Space Radiative Transfer Calculation

|µ HPC u|©ª°{z]¥±]¢³{7ÀSp(Dyãµvx\uW¶
HPC e¨{z¢°¹®´|/yy¹]^`µ¹«¬{«¬§¹]`xµSp{*;?`P]W¶fy«¬éyji¯|´Ü@ (line con ict) |ãµx§uW¶ Line con ict {YptÄj{µøyqtWh self-interference yâgt|µ cache blocking _{  }~z0 <Øp usidv]@ puW¶g\gµ,xtÄáuWh cross-interference| s·s= idv| k uW¶ Cache { ¹·´S  D cn{  }~z0 < Øp|X`r ZtX]µ w{ Øp HPC z¢°¹®´y5i¹·´SÚ\g^dv]u^xX¶ lduµ cache y  on-chipmemory [Zn©ª°Q¢³ {z¹«uW SCIMA(Software Controlled Integrated Memory Architecture) ],'ftXñò ñò óPô ¶95;7Kn{¢³|µ¯´àç5{Nlµ³ÝrQ{D]!g`µ¹¯ VLIWy]f¡Â²£±gÄS{Ú´y7ÀpÀ]cyDgtX¶g\gµ©ª°y[Xt|²¾£ u| Zª/ yNlgtX{{µ25£¢ I/O Q{D]¢³
{SpDy(X`XtXxX{]tHuW¶d{nµ©ª°z]¥±vxdv]â¶\Æ.f4bt^n¶d{§siny«¬é]`Át^tX¶«¬|I8S{X¹ógtÖë:\2x©ª°¿.yÐb/y¹gµ©ª°z{2<P¶g\gµ©ª°z
¹´yqt|¹{·´SvyÁYdv]ä¶jµ\ZqtSp{*;?Xtg YvX
YU2ÌqtX¶d{§|µ| ¹¦´´¬¹{´(HPC) ZtX`yWnqtµfyãµuW¶ly !') ')R +)#$ U1.

99)

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u|µ SCIMA z¹«yås`¢³u{ }~z0<ØpZainyµ HPCz¢°¹®´{/ruW3{õÔ«ýSÀ{§§¬²¹®´g^>i¶Graduate school of Engineering, The University ofTokyoyy2000)

!') ')R 04Q%3U)$ U

Graduate school of Frontier Scientces, The Universityof Tokyo1öü÷úøùûSCIMA |t[@·Îv]NtX HPC b{©ª°Q¢³{z¹«uW¶cache vDy software control @px2x S-RAMê¤y¢Dyi2uW¶ìu|µl{Ñµæ¶
2.1 On-chip memory
SCIMA ¢³{¢D{©ª° ((;µ onchip memory) |Öë:vc/{z²MáÌpµ¢³ ¯¨\ load/store ¡Ây'êy·´idv]@puW (P 1)¶ On-chip memory |«¬Ívc³y 1 º Q|±j{²|´u load/store ]@pvx¶
2.

SCIMA

registerdirecton-chipmemory

off-chip memory

62

SCIMA

SCIMA

9  ]ä¶¶dyµ·´S]xX¹] cache8ñidvçJ/yadv]@pvx¶2.3 SCIMA '8<?B,
Dë{Yxf#Ìr SCIMA ¢³³²£±u§¬²¹®´i§¬²¹ (scim)]ÎvftXñò ¶d {  §¬ ²¹  u |µ SCIMA ¢ ³   {ISA(Instruction Set Architecture) vgtµ MIPS4R10000 { ISA £¹vgt SCIMA ´{Ó"¡Â?Zn¡Â+ïgtX¶nogµ MIPS4 u|Æ¸²{Q|UQµab>Qvy 32 uW]µ SCIMA ¢³u|d8`{Q{²&Z (Ó{Q|§¬²¹y¯©¹uÆ+i)¶Ó"¡Â²{Ó"|µ MIPS4 u|+ïftX] R10000 u|Óü { lwc2µ ldc2 xw{ _V¡Â·´gtÓti¶d{_V¡Ây ib§¬²¹0u+ïgtX¶(;µ§¬²¹{Öxf#æ¶ ¹¹¯¶ reservation station é y ås` out-of-order issueµ out-of-order execution
Y¶ 100% eæ°1T~{GYu§¬²¹®´¶
 Instruction cache | 100 % i{vi¶ ©ª°Ïù| L1 data cacheµ on-chip memoryµÖë: (o -chip memory) {Ò¹}~zyrXt§¬²¹®´i¶ cache | lock-up free«¬vx¶ L2 data cache |ÌnxX¶HC8EIMQKSDRF
õÔD-|3{Ïù{ÿ{/ruWµ4r·¦|³r·èÐò·@Ê}·ÈÐò· X ò· òxw{³¸xr%.{õÔvµd=ÜgnnÔgnidÒv{ûz´ uW¶õÔ¼ ÀØ {SÀ|µ(;{ 3 r{¢yeb¶( 1 ) õÔ«ýo-ÑË`( 2 ) ? qnõÔE\õÔ{ª¹©´SÀi2000)

61

cache

8"*1nµ on-chip memory v register le á|X´c  ëbdv]@ p x{uµ load/store { ±¹¢ cache `u^¶On-chip memory v Ð` b ©ª° ((;µ o -chipmemory) v{á{¹1ý|ï´¡Â]ëbtX¶ d{ ï´¡Â page-load/store |µ o -chipmemory áv on-chip memory {á¯|c
rbt{/Ù 1ý]@pvxqtX¶1ýf¹
¾|@iuW]µ cache { line size ^X)u{¹1ý÷X o -chip \{¹1ý¹<i¶ nµ on-chip memory |¤¹)uß¸f (1 ¤¹| 128 |-5)¶,x¤¹y i load/store ¡Âµ page-load/store ¡Â|zXycÍÓidv]@puW¶l{nµ¹1ý¡Â vl{ 7 {7 À¡Â out-of-order ÓyãI<gµ²|´{2hPdv]@puW¶
2.2 Controllable Data Cache
SCIMA { data cache |µ¢³ ¯¨ \ «¬f¿.vfxX¿.Æ+@px controllablecache uW¶o -chip memory  = ú ë : { ¤¹   ) u
cacheable/uncacheable 3S  Æ+ u^ é  [Z¶·´S]*X¹| uncacheable 3Srbdvuµ cache ÉfxX direct access Ydv

3.

2

õÔ{ª¹©´õÔ¼ o-ÑË`d{uåvx{|µ 1. {õÔ«ýo-ÑË`dvuW¶lduu|µ8ÎqõÔ«ý§§¬²¹®´i¶
3.1 TV[]1_eõÔ|/yyµõÔE5vx}kÎq)ûMá
»hÎqt)Má½hÎq4b¾Má¼D{¯¹â
Q I (x,n,) »x: hÎq{)£±µ n: gÎq{õÔo£±µ : õÔ{LbQ¼u]tf¶õÔ«ýo-Ñv|µÎ{Yx 6 ÎqMáj{o-ÑuW¶(3)}

3.2 rvF3w}
õÔ¾SÀ{7À|jÕKb (({ iteration loopvx) {Nkg]åÿvx¶ Iteration loop|ÒÔÅQ{ç{ÌQeNkfµÓÌQ] N {¹¹vx (oy7¸6<]idv]W]Ò/y|chW)¶qtÓÍá{xd{be]îdvyxµ iteration loop {7¸2<idv]ö {7¸{2<yrx]¶Iteration loop ju&YiQ|, (;{YyeÁ@puW¶( 1 ) o]/+uW}/+{uWµÌNkgÁ´fiQ( 2 ) loop juSÀf¿A loop j {uµÛöxI8SÌriQ( 3 ) ·´f ug}`Íá]\\dv{WtÄ
SCIMA z¹«Znv^µDë{ 1. <~ 2. |l{fS\µ cache yk¹vi^uW¶d{¹¾|µSuQ KB ynxX¶ 3. {tÄyâgt|µ Chi· Eta· I· t {ir{tÄ]W]µ Chi· Eta· I yâgt|·´{fo]ö`chuWµ t yâgt| X¶d{ tÄ| öt LbQv Má) { iÎqtÄ uW¶g\gõÔ{ LbQy i gºS ·´i}µMá){hÎqtÄvgt&Ydv]@puW¶nµ Chi· Eta yâgt| read-only uWvXY f#]Wµ/+o·LbQ^n{¿AÌQ]jÌv
V qtX¶qtµjÌ{¿A]nl{¿.yÎx load idv]@puWµ¹/y
on-chip memory ·´idv]@puW¶nµõÔ¾SÀ{oyjµ blocking |^xB]WvZ¶ Cache y[Xt|µ Blocking  Z} cache-miss { vW  Ts idv]@ p uW¶ On-chip memory y[Xt| page-load {ystride cÆ+u^nµx line access |WhxX]µ blocking y¹{I8SDcdv]@pxn blocking |®uW¶lduµ Chi·
Eta· I· t xw{ tÄbe  block  )u é  × 
on-chip memory ykvXYð»×¶d{ 0 < oO u|µ·´S y ¥ gt ¹
 cacheable/uncacheable yebvXY SCIMA {controllable cache |Á´gxX¶
3.3 +50 !rvF
3.2 ì{ð»yås^µõÔ¾SÀ{tÄö 0^x^fy blocking i¶ block ju\µyx¹
 page-load ¡Âu on-chip memory y/Ùgt1ýi7¸µ on-chip memory j{Fm{u7ÀY7¸µ7À]ßqn¹ page-store ¡Âu6n 1 rI (x; n;  ) = 0(x; n;  ) + (x; n;  ) (1)ddu (x; n;  )µ(x; n;  ) |lm) çWn{=ÜOQ[~nÔ¹uWµQSÀy[Xt|d|èâQvxi¶l (x) xw{:d¸¾|I ?dv]u^¶qtµÕvxSÀ|µ±Zn  v  y gt 1ÑçegtÒ) x y[bÒov n LbQ  y 9iõÔE5 I ?dvvx¶õÔ«ýo-Ñ (1) y[Xt  v  ]èuWE
µo n [~LbQ  ],x{yrXt|õÔ
E5 I |zXygºvx¶/o) x yâgt|, õÔ{3qi;¼0|D¼0y*5gtXnµ\jD¼0\;¼0y\qtSÀNz}xxX¶ÔÅpyås^õÔ«ýo-Ñ (1) Ë`opvgt
Short Characteristics p´Xmn ¶(;yµ X oy\YE{õÔ«ýSÀ{¢³¯¨{ÔÏi¶/* NX, NY, NZ Îèûúßÿ */99)

for (ix = 1; ix < NX; iz++){for (iy = 1; iy < NY; iy++){for (iz = 1; iz < NX; ix++){/*start of iteration loop*/îÑ×ÐÔÓïoôõ¼
Eta[ix-1][iy][iz], Eta[ix-1][iy-1][iz]Eta[ix-1][iy][iz-1],Eta[ix-1][iy-1][iz-1]
Chi[ix-1][iy][iz], Chi[ix-1][iy-1][iz]Chi[ix-1][iy][iz-1],Chi[ix-1][iy-1][iz-1]
I[ix-1][iy][iz],I[ix-1][iy-1][iz]I[ix-1][iy][iz-1], I[ix-1][iy-1][iz-1]
Chi[ix][iy][iz],t[ix-1][iy][iz],Eta[ix][iy][iz]RadJ[ix][iy][iz]ýÁ×ÐÔÓïoôõ¼
I[ix][iy][iz],RadJ[ix][iy][iz]}}t[ix][iy][iz]/*end of iteration loop*/3o -chip memory y9^¦i7¸{ 3 ÙÁ|¢¯|´<i (P 3)¶¨y[b cross interference Z (7{iQ{5G| Êi)¶for (x = 0; x < N-1; x++)for (y = 0; y < N-1; y++)for (z = 0; z < N-1; z++){/* A[ix][iy][iz],A[ix+1][iy][iz],B[ix][iy][iz],B[ix+1][iy][iz]*/}Õó¿ÆêÞ

6 3 S7&8/block { ÔÅ|  N vgn EµtÄ Chi·Eta· I |d fÔÅ ^X (N + 1) { ¹µ t | (N + 1) 3 N { ¹µ RadJ | N {¹h×\µ]W¶ page-load/store ¡Â| ¯|zy 1ý ]ÆÏ u^{uµlm{ tÄ ] N + 1 n| N Ì { page-load¡Â { Ó y ¹1ý ]@ p uW¶ nogSCIMA ¢³|µ page-load/store ¡Âvl{7{7À¡Â out-of-order yÓ@pu|W]µ¾{ page-load/store ¡ÂÅ4gtvgD_v
Reservation Station {´°]Wt¹±gtg Y¶lduµ page-load ¡Â|/5y Å4gtvi{u|x`µ¡³j{/XÐ0{±¹¢yktÎyvgtX`{vi¶¹{9^¦gY page-store ¡Âc³uW¶I¢³ ¯¨|o<~LbQy+gtµ 1 PU yt)Máö {õÔ¾SÀYv=+gt§¬²¹®´gn¶tµõÔ¾SÀ{§{ê¤|MáÔÅQ 256 (DuW¶g\gµ8µ©ª°¾<~§¬²¹®´ÓÍá{R©yµMáÔÅQ|32 yRvgtX¶SCIMA ¢³ v{ Y× { nyµ on-chipmemory  Ì nxX cache {{ ¢³  ´+gµlmy cache blocking· on-chip memory
blocking 0<qn¢³ ¯¨Óib§¬²¹®´gn¶4.1 [{:;>&)3UZõÔ¾SÀ|MáÔÅQ N=256 (D{SÀ]\µvftX¶/oµ¢Dy@px SRAM |Qá MB vx\)guW¶§¬²¹®´| N=32uYnµd{v^y¢D{©ª°¾w`Xygt^>Y^\Zai\µ]W¶cache { line con ict v g t self interference v
cross interference ]W]µ self interference yâgt| blocking uTs]@pxnµ cross interference{yâgtZ¶dduhÎqtÄ A[N][N][N]µ B[N][N][N](N | linesize áe^Xvi) ´XnµõÔ{¢³ ¯¨{tÄ{zà»<gª±<gn¢³ ¯ÔÅQ] N vivµ 3 ÎqtÄ A[N][N][N] Zvµ jµ (x,y,z)=(0,0,0) y[Xt A[1][0][0] {line ] cache y ¶d{ line D{ ¹] Îy¿Af{|µ (x,y,z)=(1,0,0) {v^uWµd{v^tÄ B ] self interference ìdgtXxXviv
cache ytÄ B { line Q| 2 3 N 3 N=linesize v
x¶ dµ cache { miss ¹ |d{ GY y[Xt| N { ¹¹ yâ Yv  Z¶ ( D µN=256 u{SÀy gtµ N=32 u§¬²¹®´
Yv^| 128KB º 256KB -5]9^uW¶lduµ cache {[Zn¢³u| 128KB{ L1 data cache µ On-chip memory [Zn¢³u|¯¹iQ«¬i{y>v\µ x 8KB { data cache v 128KB { on-chipmemory Ìr{vi¶
nµ cache { [ Zn ¢³ | 4-way set
associative cacheµ on-chip memory  [ Zn ¢³
| 2-way set associtative cache v`b¶

3

3

2

3

2

4.

4.2 6@$=93sdetµ SCIMA ¢³´{´|¯| ox
X¶l{n§¬²¹ylÀi¢³ ¯¨|µ(;{Ø6uTi¶( 1 ) §¬²¹®´ C¢³ ¯¨ C u Ti (page-load xw|îËâQvgtëæi)¶( 2 ) SGI MIPS pro C ´|¯yz´¡¯Ti¶( 3 ) ¯´²¹yqtîËâQ§¬²¹u+ïfnÓ"¡ÂyiÞi¶cÍyµab>Q2²Q{Ó"X spill code =Ai¶( 4 ) ØHy¡Â{¬¹°´ Y¶( 5 ) z´¡¯yqt|°Ti¶
4.3 bG6@$=9Cache Only

On-chip memory Ì nxX Cache {´Xn0<¶ cache blocking qtX¶Scima Opt.1 (No Prefetch)í³¹xX on-chip memory ´Xn
0<¶/j{ÔÅ] 8 {|u¡³<i¶4¡³ju\µyx¹|µ\µyxqn
2u page-load gtX¶ Cache Only v,xµ 1 Ìu 500 º 650 |{¹]1ýf¶On-chip memory | 128KB {Yp 26KB ÁqtX¶Scima Opt.2 (Prefetch)í³¹qn on-chip memory ´Xn
0<¶/j{ÔÅ] 8 {|u¡³<i¶¡³{7ÀqtXáyµÎ{¡³u\µyx¹í³¹i¶On-chip memory | 128KB {Yp 77KB ÁqtX¶

6 4 9 8, 8T (2(32)

Ideal

Scima Opt.2 {¢³ ¯¨µ o -chip memory{ ²|´ ] 0µ´c ] Ó vµcache size vµ full-associative cache vXY¸úH uÓgnWB¿{ny?Z¶ §¬ ²¹ ® ´ {  yµ cache sizeµ on-chipmemory sizeµ cache associativity  ¯©¹ v
gt@i ygt Y× Y¶ nµab>Q2 7À­{Q 2 º 8 {áui<fktX¶l{7{ÒGY|(;{Yyë+gn¶¢³bÝrQjb 2GHzÐb 1GHz´c16 bytes
UQ²Q
32ab>Q²Q
64
Cache line size
On-chip memory page size
UQ7À unit
O -chip memory L/S Unit
Cache y i L/S Unit

658, 8T(2nuW¶ÃZ}µ FPU 2µ o -chip memory ²|´ 0 {GYu|µöÓ|±\wivµí³¹|© 65,000 |±ôyÎÄftXdvyx¶Cache Onlyµ Scima Opt.2 | Dyí³¹¢Ï/yxX¢³ ¯¨uW¶½¢³ ¯¨vo -chip memory {²|´yYÃgtÓ|
±J}gtX]µl{P^y|]W¶d|µCache Only ] cache line size  ) (32 |) u{¹1ýqtX{y gtµ Scima Opt.2 ]page-load ¡Ây 500 º 650 |/Ùgt1ýinµ¢° ~{B]ätXnuW¶

32 bytes
128 bytes
142

J6OG
Cache Onlyµ Scima Opt.1µ Scima Opt.2 {Ò¢³ ¯¨§¬²¹®´gnWB P 4 yWi¶ nµ Scima Opt.2 {ÓWB|P 5 yÓgtWi¶
Cache Onlyµ Scima Opt.1µ Scima Opt.2 v
o -chip memory {²´´] 0 {GYu|chÓ|±uÓftX]µ²|´]þ?
y i ¯ {P^| Cache Onlyµ Scima Opt.1µ
Scima Opt.2 {6u^`xqt`¶¯ {P^\wivµ Scima Opt.2 | o chip memory {²|´{5GvwÚbtXxX¶d|µ page-load yí³¹]ÛöyXt¹1ý²|´{2hyT~gtX
5.

Scima Opt. 2)

ab>Q2­ (FPU) {Q 2 wµ 4 wµ 8 w
vi<fknE{SpDyrXtvµ FPU 
2 ¾ 4 u| 20% -5 {SpD] e{y gtµ 4 ¾ 8 u| 3% -5{SpDg\exX¶
SpD]iir0|µ SCIMA ´{ï´´|¯]tx` MIPSpro C Compiler {äÀ·´ gtXnµ Instruction scheduling· Register
allocation ] SCIMA y0<ftXxXdv]Bc¶5

Scima Opt.2 { FPU 8 {Eyµ Reservation Sta- [K` 99] K`VB, -Þ/, ¯, 6#A-.6:;>5^ý0 HPC 6@*.&3UZ Fm7¸ØÊtion {´°Q$Ugtµ load/store {´°[@Êm,1999 n 3 XQ 8 \ 32 y$Uivfy 14 % {SpÍõ]\n (] 6)¶¹y gt|µå¡³ju{ Instruction scheduling qtX]µdobu|áeuxXdv]e¶GYL/S { RS ´° 8
L/S { RS ´° 32

Ó|±3,014,058
2,594,630

66
8.-8, Ó{¹|µ iteration loop 1 Ì{yµGYeæ 1 rv 2 n| 3 Ì{ exp âQ{x~ägãuX¶SpD ¥Æ iy|µ ./µâQá u{
Instruction scheduling Y\µ]W¶:6;6PN8KF
u|µ HPC e¨¹ygt[@·ÎvftX SCIMA z¹«y gtõÔ«ý§ }~z0<gµ SCIMA §¬²¹
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