Low-Power LSI Technology of0.15 µm FD- SOI
Koichi Morikawa
Mutsumi Mitarashi
Recently, there has been an increasing demand forportable, battery-operated devices like cellular phones.
Achieving low-power, high-speed LSIs is essential tominiaturize these devices and improve performance andextend battery life. In order to meet such demands, wehave applied the 0.35µm and 0.20µm Fully Depleted SOICMOS device to LSIs, and low-power LSI technology has
been developed.
This paper describes the development of the 0.15µm
FD-SOI CMOS device fabricated for the purpose ofminiaturization and speed improvement, and theperformance of digital circuits using this device. First ofall, the methods used to achieve a low-power LSI will bedescribed. Secondly, the structure and electricalcharacteristics of the 0.15µm FD-SOI CMOS device withmultiple threshold voltages, will be described. Finally, theexperimental results of low-voltage digital circuits aredescribed.

Yoko Kajita

order to realize an FD-SOI CMOS device with a multiple
threshold voltage, it is necessary to develop simple andstable processes with a consideration for quality and cost
concerns for each threshold voltages device.

PolySOIBOXSub.

Low-Power design methodology
Many general methods to reduce the power of LSIs
have been proposed from algorithm- level to processlevel1) and applied to LSIs. Common standard methods
that can be applied to most LSIs are lowering the supply
voltage and using CMOS devices. Lowering the supply
voltage is the most effective and direct way to achieve
low-power LSIs because the power consumption is
proportional to the square of the supply voltage.
Therefore, the LSI which operates at a frequency of100MHz at a supply voltage of 1V or less are being
widely studied and developed2) 3).
FD-SOI CMOS is superior to conventional bulk
CMOS for low-voltage operation, because the parasitic
capacitance is reduced and the subthresholdcharacteristics of the transistor are precipitous. We
developed a 0.15µm FD-SOI CMOS device with multiple
threshold voltages, which made it possible to reduce theleakage current and improve speed.

Development of 0.15µm FD-SOI CMOS device
Due to the shrinkage of the gate length of the MOS
device, the drivability is improved, but a short channel
effect occurs, which results in the lowering of thethreshold voltage. Through the increase of the channel
impurity concentration to suppress this effect, a reduction
in drivability will occur. This cycle is a common issue insubmicron MOS devices. On the other hand, the increaseof the channel impurity concentration leads to a partial
depletion, which deteriorates the superiority of the FDSOI CMOS that was described previously in this paper. In

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October 2003/Issue 196 Vol.70 No.4

Fig. 1 Cross-sectional TEM photograph of a 0.15µm FD-SOItransistor

FD-SOI MOS transistor. Bonded SOI wafer was used.
The thickness of the SOI on the buried oxide (BOX) andthe thickness of the gate oxide are 40nm and 2.5nm,
respectively. Since the FD-SOI CMOS is fabricated on
the extremely thin SOI layers, we developed a totalprocess, which suppresses the thinning of SOI for thesource/drain region. In the 0.15µm SOI process, thebackend process (BEP) is the same as the 0.16µm logic
process used in our Fab., for the purpose of making
effective use of our existing process technology anddesign kit.
(1) Thin-film SOI process technology
It is necessary to confirm the minimum thickness of
the SOI layer from a viewpoint of the reduction of thediffusion layer resistance by applying the self-aligned
silicide (salicide) technology to thin-film SOI devices.
Figure 2 shows the dependence of a Co silicide sheet
resistance on the width of the patterned N+ diffusion
layer with a various thickness of SOI (tsoi).
tSOI is defined as the thickness of the SOI layer under
the gate electrode. The SOI film for the source/drain
region is thinner than that for the channel. In the case ofthis 4 nm thick Co, the sheet resistance for various
patterned width are low enough when the SOI thickness
is thicker than 30nm. On the other hand, the sheet
resistance increases on 25nm thick SOI. This increase of
sheet resistance is explained by the remaining CoSi afterSpecial issue on devices

and increases the substrate impurity concentration only
near the gate edge. As shown in Figure 4, the thresholdvoltage roll-off is improved by the pocket ion implantation.
Although the variation of the threshold voltage for thefluctuation of 0.02µm gate length was maximally 270mV,
without the pocket ion implantation, it dramaticallydecreases to approximately 30mV with the pocket ionimplantation. The short channel effect was sufficiently
suppressed in both the NMOS and PMOS.
In order to increase the driving current, the S/D
extension structure is introduced instead of the LDD
structure, which is used in 0.20µm FD-SOI CMOS
devices. This structure achieves the higher impurity
concentration with a shallow junction between thechannel and the source/drain region. As a result, theparasitic resistance was decreased, which made it
possible to obtain an increase in the driving current by
about 15%, thereby making acceleration of the device
processing speed possible.
The I-V characteristics of each transistor are shown inFigure 5.

the 2nd RTA, due to a lack of Si for the transition fromCoSi to CoSi2.
In the Co salicide process, there was the other issueof BOX leakage failure, which occurred because of anelectrical short between the SOI and substrate due to apinhole made by over-etching at the contact opening.
This issue was improved by the optimization of a contacthole etching process and the adoption of the Contact
Hole Etching Prior to the Second Annealing (CHEPSA),
in which the contact-hole etching is performed prior to the2nd RTA for the transition form CoSi to CoSi2. Figure 3
shows the distribution of the BOX leakage current. If thecurrent determines the failure over 1x10-11A, it isindicated that the BOX yield will be improved from 20% to100% by using CHEPSA. From the TEM image of figure
1, it is confirmed that a 25nm thick cobalt silicide isformed over the diffusion layer and the gate and that thecontact hole etching is stopped above the silicide layer.
(2) Optimization of transistors
In order to suppress the short channel effect, we used
a pocket ion implantation, which is used for bulk devices
1200.4Threshold voltage (V)

80
60
40
20

0.2
0.0-0.2-0.4-0.6

0.1

1
Wiring width (µm)

0.101010-2

Drain current (A/um)

1050.5 VDS =0.1,1.0V

1010-6PMOS

10-876mV/dec

73mV/dec

10-1073mV/dec

78mV/dec

NMOS

S=S=

00.4

Gate voltage (V)10-8

1010-4BOX leakage current (A)Fig. 3 Cobalt salicide process comparison of thedistribution of the BOX leakage current

 VGS =0.2 to 1.2V

W=10um-4

10-12-1.2 -0.8 -0.4

1-120.25

Fig. 4 The dependence of the threshold voltage on thegate length and effect of the pocket ion implantation(S/D extension structure transistors)

conv.

CHEPSA

0.20

Gate length (µm)

Fig. 2 The dependence of a Co silicide sheet
resistance on the width of patterned N+ diffusion
layer with various thickness of SOI999590807060504030
200.150.8Drain current (mA/um)

0Cumulative frequency (%)

With pocket ion
implantation

0.6

40nm
35nm
30nm
25nm

100
Sheet resistance (Ω/ )Without pocket ion
implantationt SOI

4nm cobalt spatter

1.2

0.4

NMOS

step 0.2V

0.3
PMOS
0.2
0.1
0.0-1.2 -0.8 -0.4

00.4

0.8

1.2

Drain voltage (V)Low threshold voltage transistor
High threshold voltage transistor

Fig. 5 I-V characteristics of 0.15µm FD-SOI-CMOS

OKI Technical Review
October 2003/Issue 196 Vol.70 No.461

Low-voltage digital circuits
We verified the performance of digital circuits using
0.15µm FD-SOI CMOS. The circuits include a 32-bit
adder circuit, 64Kb SRAMs, and a 16-bit DSP core thatuses these functional blocks.
(1) 32-bit adder
In order to evaluate the performance of thefundamental arithmetic circuit, we fabricated a 32-bit
adder using a binary carry look ahead architecture6). The
architecture can improve the speed of the adder with along bit length such as 32-bit because the carry of each
bit is generated from the propagate and the generatesignals with a binary tree. Further, it is suitable for theadder with a long bit length because the speed is
proportional to the logarithm (log2) of the bit length.
Figure 6 shows measured delay time and power
consumption of the 32-bit adder. The delay time of 1.9ns
and the power consumption of 1.9µW/MHz wereobtained at a supply voltage of 1V. Further, the minimum
operating voltage was confirmed to be 0.4V.

The features of the MT-CMOS configuration is that
low threshold transistors are used in the peripheral circuitand high threshold transistors in the memory cell. The
peripheral circuit is connected to the power source viathe power switch with high threshold transistors. Since
the memory cell needs to preserve data while in thestandby mode, it is connected directly to a power supplyline.
Figures 7 and 8 show measured clock access timeand standby leakage current of the 64Kb SRAM
respectively. The clock access time of the MT-CMOS
configuration is 2.9ns at a supply voltage of 1V. A speed
improvement of approximately 50% was obtained ascompared with the SRAM configured with high threshold
transistors that is 5.3ns. Further, the standby leakage
current of the MT-CMOS configuration is 2.6µA. It is areduction by about 1/1000 lower than the SRAM
configured with low threshold transistors that are 0.9mA.
From these results, we confirmed the effectiveness of theMT-CMOS configuration that can achieve high-speed andlow standby leakage current.

15Low VthClock access time [ns]The subthreshold factor is approximately 75mV/dec
for all transistors. This value is adequately smaller thanthat of bulk CMOS or partially-depleted SOI CMOS in thesame generation (about 85mV/dec or higher). It is
confirmed that this 0.15µm SOI device shows fullydepleted characteristics. The kink characteristics5)
appear in high threshold voltage NMOS transistors. The
reason is considered to be the substrate floating effectdue to holes, which are generated by the hot carrierseffect.

(2) 64Kb SRAM
For the purpose of comparison an SRAM configured
with a low threshold transistor, an SRAM configured witha high threshold transistor, and an SRAM configured with
MT-CMOS1), were contained on the test chip.

High VthMT-CMOS

105

00.0

0.5

1.086442

200
1.5

0.5

1
Supply voltage [V]Fig. 6 Measured delay time and power consumption ofthe 32-bit adder versus supply voltage

1.0E+01

Standby leakage current [mA]

Delay timePower consumption

62.0

Fig. 7 Measured clock access time of the 64Kb SRAM withvarious transistor configurations versus supply voltage

Power consumption [u W/MHz]

Delay time [ns]81.5Supply voltage [V]\1.0E+00

Low VthHigh VthMT-CMOS

1.0E-01
1.0E-02
1.0E-03
1.0E-04
0.0

0.5

1.0

1.5

2.0

Supply voltage [V]Fig. 8 Measured standby leakage current of the 64Kb
SRAM with various transistor configurations
versus supply voltage

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October 2003/Issue 196 Vol.70 No.4

Special issue on devices(3) 16-bit DSP core
Further, we fabricated the 16-bit DSP core using
these functional blocks. As shown in Figure 9, the 16-bit
DSP core is configured by the 256Kb (64Kb x 4) data
memory, data pointer, and the multiplier accumulator,
which consists of a 16-bit multiplier circuit and a 32-bit
adder circuit. It reads two sets of 16-bit data from thedata memory, and executes a calculation of the sum ofproducts with the multiplier accumulator.

DPA

13DMA

DMB

16REG

16REG

161613DPB

MPY

Conclusion
This paper described the development of the 0.15µm
FD-SOI CMOS device with multiple threshold voltages
and the experimental results of low-voltage digital
circuits. We confirmed the operation of the 32-bit adder,
down to 0.4V, and achieved a power consumption of9mW (@100MHz/0.8V) with a 16-bit DSP core, andverified that FD-SOI CMOS is effective for low-power
operation. In the future, we intend to develop the analog
circuit and the RF circuit etc and evolve these efforts intoa low-power system LSI by utilizing the characteristics ofthe FD-SOI, which is effective for low-voltage operation.
This study was undertaken as part of the research
initiative “Research and Development of ultra-low-power
LSIs for information terminals” sponsored by the New
Energy and Industrial Technology Development
Organization (NEDO).

References

32
REG
32

32
ADDER

32
REG
Fig. 9 Block diagram of the 16-bit DSP core1) Sakurai:“Low-powerandHigh-speed
LSITechnology”, SIPEC Corporation (formerly known as“Realize-sha”), 1998.
2) Yamada: “Research and Development of Low-Power
LSI”, NTT R&D, Vol. 49, No. 9, pp. 482-488, 2000.
3) Douseki: “Extremely Low-voltage Digital Circuit
Technology”, NTT R&D, Vol. 50, No. 11, pp. 885-889,2001.
4) Ichimori: “Advanced Performance of FD SOIMOSFET Through the Silicide Conversion of All
Layers of Source and Drain Elements”, Technical
Report of IEICE, Institute of Electronics, Informationand Communication Engineers (IEICE), SDM2000249, p. 61, March 2001.
5) J.P. Colinge: “Silicon-on-Insulator Technology:
Materials to VLSI”, Kluwer Academic Publishers, p.
139, 1991.
6) Fujishima, et al: “Configurations of AcceleratedAdders and Counters Using a New Binary Carry LookAhead”, Fall Convention of the Institute of Electronics,
Information and Communication Engineers (IEICE),
pp. 5-105, 1991.

Authors
Koichi Morikawa: Silicon Solutions Company, DesignDiv., Design System Dept., Low Power Library Team
Yoko Kajita: Silicon Solutions Company, Research Div.,FeRAM Product Development Dept., FeRAM ResearchTeam-1
Mutsumi Mitarashi: Silicon Solutions Company, DesignDiv., Design System Dept., ManagerFig. 10 SHMOO plotting of the 16-bit DSP core

Measurement plotting (SHMOO plotting) of theoperable range for the power voltage and clock cycle timeis shown in Figure 10. The 16-bit DSP core wasfabricated using a 0.15µm FD-SOI CMOS device. An
operating frequency of 100MHz and a power
consumption of 9mW were obtained at a supply voltageof 0.8V.

OKI Technical Review
October 2003/Issue 196 Vol.70 No.463