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Scheduling Based on Execution Cycle Estimation
Naoya Hattori Takuya Araki Shuichi Sakai Hidehiko Tanaka
Graduate School of Engineering, University of Tokyo
Abstract

Global instruction scheduling is a technique to improve parallel execution in processsors by moving instructions between basic blocks. As processor resource is limited,
we need an ecient selection algorithm to choose which instructions to move. Previously proposed selection algorithms have limitations in (1) Not considering data
dependency between instructions in di erent basic blocks, or (2) Not considering
either type or number of execution units available in processors. In this paper,
we propose a new scheduling technique which overcomes the limitations describedabove. Compared with non-scheduled code performance, we get 10 % improvement.

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[1] UltraSPARCTM User's Manual.

[2] Mike Johnson. Superscalar Micropeocessor Design.
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, Vol. 19, No. 6,
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m;j° e, 4VCâÉ"@ 1.10 S:i, 2- [4] David L. Weavar and Tom Germond.
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ACM Transaction on Pro-gramming Languages and Systems

The SPARC

Architecture Manual Version 9