%RQDYHQWXUD'U6DQ-RVH&$7HO²)D[ZZZ[VFDQLPDJLQJFRP/LQHDU;5D\3KRWRGLRGH'HWHFWRU$UUD\ZLWK6LJQDO$PSOLILFDWLRQ

;%6HULHV

An X-Scan Imaging XB8850 linear detector array is constructed of CMOS silicon photodiode array detector
chips mounted on a single printed-circuit board. The imaging circuit of each detector chip consists of acontiguous linear array of photodiodes, a timing generator, digital scanning shift register, an array of chargeintegrating amplifiers, sample-and-hold circuits, and signal amplification chain. Each detector array generates an
End-Of-Scan (EOS) pulse that can be used to initiate the scanning of the next detector array. Thus, a longer,
continuous detector array can be formed from a daisy chain of smaller detector arrays.
For x-ray scanning applications, a scintillator material tailored to the user’s application is attached to the surfaceof the detector array to convert x-ray photons into visible light for detection by the photodiode array. TheXB8850 photodiode array is uniquely designed and processed to reduce radiation damage from the x-ray flux.
The signal processing circuits are positioned 2 mm away from the photodiode array. These circuits are shieldedfrom direct x-ray radiation using an external heavy-metal shield. The precision alignment of the metal shieldwith respect to the signal processing circuits is performed at the factory using a special molded housing and chipon-board (COB) technology.

Key Features• Small element pitch with two selectable resolution modes: 50 ȝm and 100 ȝm• A large selection of lengths at multiples of 0.5 inches:o 0.5 inches (256 pixels at 50 ȝm, 128 pixels at 100 ȝm)
o 1.0 inch (512 pixels at 50 ȝm, 256 pixels at 100 ȝm)
o 1.5 inches (768 pixels at 50 ȝm, 384 pixels at 100 ȝm)
o 2.0 inches (1024 pixels at 50 ȝm, 512 pixels at 100 ȝm)o etc.
• 5-V power supply operation• Simultaneous integration by using an array of charge integrating amplifiers• Sequential readout with a digital scanning shift register (Data rate: 1 MHz max.)• Integrated CDS circuits allow low noise and wide dynamic range up to > 4000
• User-specified scintillator material GOS, CsI(Tl), CdWO4, etc.

Applications• Linear x-ray imaging for industrial inspection• Linear x-ray imaging for biological and industrial CT;6FDQ,PDJLQJ&RUS

-DQ5HY

3KRWRGLRGH'HWHFWRUZLWK6LJQDO$PSOLILFDWLRQ;%6HULHV Ŷ Mechanical specifications
Parameter

SymbolElement pitch
Element diffusion width
Element height
Number of elements
Active area length

PW
H––i

XB8850-6.0Gii
100 ȝmiv50 umv

XB8850-12.0Giii
100 ȝmiv
50 umv

Unit

100
40×275
1536
153.6

100
40×275
3072
307.2

ȝm
ȝmȝm–mm5040753072
153.6

5040756144
307.2

i

Refer to enlarged view of active area figure.
6-inch long detector is specified here. Other lengths (at multiples of 0.5 inches) are available upon request.
iii
12-inch long detector is specified here. Other lengths (at multiples of 0.5 inches) are available upon request.
iv
When RS (pin 12) is tied to GND, the detector operates in the 100-ȝm resolution mode. There are 1536 pixels in a 6-inch 100-ȝmdetector; there are 3072 pixels in a 12-inch 100-ȝm detector.
v
When RS (pin 12) is tied to VDD, the detector operates in the 50-ȝm resolution mode. There are 3072 pixels in a 6-inch 50-ȝm
detector; there are 6144 pixels in a 12-inch 50-ȝm detector.
iiHŶ Enlarged view of active area

WPHOTODIODE DIFFUSION AREAPŶ Absolute maximum ratings
Electronic device sensitive to electrostatic discharge and x-ray radiation. Although this device features ESD
protection circuitry, permanent damage ranging from subtle performance degradation to complete device failure
may occur on devices subjected to high-energy electrostatic discharges. Furthermore, although this device
features radiation shielding for protection against anticipated x-ray radiation, permanent damage ranging from
subtle performance degradation to complete device failure may occur on devices subjected to unanticipated xray radiation (e.g. off-axis or extremely high energy radiation). Therefore, proper precautions against ESD and
x-ray radiation must be taken during handling and storage of this device.

Parameter
Supply voltage
Reference voltage
Digital input voltages
Operating temperaturevi
Storage temperaturevi

ToprTstg

Min
–0.3
–0.3
–0.3
–5–10Max+6VDD + 0.3
VDD + 0.3
+60+70

Unit
VV
VoCoC

Humidity must be controlled to prevent the occurrence of condensation.

Symbol
VDD
VREF

 -DQ5HY3KRWRGLRGH'HWHFWRUZLWK6LJQDO$PSOLILFDWLRQ;%6HULHV Ŷ Recommended terminal voltage
Parameter
Supply voltage
Reference voltage

Symbol
VDD
VREF

Min.
4.75
–

Typ.
53.00

Max.
5.25
–

Unit
V
V

Symbol

Min.

Typ.

Max.

Unit

f(CLK)
Vih
Vil
Ci
Ii
VohVolCo

40
4.00––10
4.25
0––VDD
040+10
VDD
0–

4000
VDD
0.4––
VDD
0.450KHz
VVpFȝAVVpF

Rref––

1
0.5––KK

Cfhs–0.1–pF

Cfls–0.4–pF

Zv
Cv––1––100

K
pF

P––

600
1200

––mW
mW

Ŷ Electrical characteristics [Ta = 21oC, VDD = 5 V]
Parameter
DigitalClock pulse frequencyvii
Digital input voltageviii

High level
Low level

Digital input capacitance
Digital input leakage current
High level
Digital output voltageix
Low level
Digital output load capacitanceAnalogReference voltage input 6.0G
impedancex
12.0G
High
sensitivity
Charge amplifier
xi
feedback capacitanceLowsensitivity
Video output impedanceVideo output load capacitancePower6.0G
Power consumption
12.0G
vii

Video rate is 1/4 of clock pulse frequency f(CLK).
Digital inputs include CLK, RESET, EXTSP, VMS, SNS, and RS (see pin connections).
ix
Digital outputs include Trig and EOS (see pin connections).
x
Reference voltage input impedance is dependent on length of detector. For a 6-inch detector (XB8850-6.0G), the input impedance is1 Kȍ. For a 12-inch detector (XB8850-12.0G), the input impedance is 0.5 Kȍ.
xi
The sensitivity selection pin (see SNS in pin connections) controls the sensitivity of the detector by selecting whether the pixel
charge amplifier feedback capacitance is Cfhs or Cfls. At Cfhs, the detector has high sensitivity. At Cfls, the detector has low
sensitivity.
viii -DQ5HY

3KRWRGLRGH'HWHFWRUZLWK6LJQDO$PSOLILFDWLRQ;%6HULHV Ŷ Electro-optical characteristics [Ta = 21oC, VDD = 5 V, V(SNS) = 5 V (High sensitivity), 0 V (Lowsensitivity)]

Parameter

SymbolOutput reference voltagexii

VosHigh sensitivity
Low sensitivity
High sensitivity
X-ray sensitivityxiv
Low sensitivity
Photo response non-uniformityxv
High sensitivity
Noisexvi
Low sensitivity
Saturation output voltage
Dark signal voltagexiii

VdS
PRNU
N
Vsat

XB8850-6.0 /12.0(100 um mode)Min.
Typ. Max.
VRE
––F
–70
–
160
–90
–
70
–
200
––
50
––10
–
10–
2.5
––
1.5
–
2.8
––

XB8850-6.0/12.0(50 um mode)Min.
Typ. Max.
VRE––F–90
–
70
–100
–70
–100
––25
––10
–10–
2.5
––
1.5
–
2.8
––UnitV
mV
V/R%
mVrms
Vxii

Video output is negative-going output with respect to the output offset voltage.
Difference between output reference voltage and absolute output voltage with an integration time of 25 ms.
xiv
Measured with tube energy of 50KVp. Other scintillations with different sensitivity are available.
xv
Measured without scintillation. When the photodiode array is exposed to uniform light which is 50% of the saturation exposure, thePhoto Response Non Uniformity (PRNU) is defined as follows:
PRNU = ǻX ÷ X × 100%
where X is the average output of all elements and ǻX is the difference between the maximum and minimum outputs.
xvi
Measured with a video data rate of 750 KHz and an integration time of 25 ms in dark state.
xiii

Ŷ Output waveform of one element
Dark State

Saturation Output
Voltage (Vsat)

Output Offset
Voltage (Vos)

Saturation StateGND -DQ5HY

3KRWRGLRGH'HWHFWRUZLWK6LJQDO$PSOLILFDWLRQ;%6HULHV Ŷ Block diagram

EXTSP
4RESET 1VMS

VDD

GND

567Timing Generator

3 TRIG

CLK 2Shift Register

8 EOS

VREF 10

Hold Circuit

9 VIDEO

SNS 11

Charge Amplifier Array

1RS 122345N-1

N

Photodiode ArrayŶ Timing chartxvii
123 20 21 22 231234567

CLK

tplw (RESET)
RESET

tphw (RESET)~6.5 Clocks~2.5 Clocks
Integration Time
Video Output Period
VIDEO

12n-1nTRIG

EOS -DQ5HY

3KRWRGLRGH'HWHFWRUZLWK6LJQDO$PSOLILFDWLRQ;%6HULHV 
tf (CLK)

tr (CLK)

tplw (CLK)thtphw (CLK)
thts

ts

tplw (RESET)

tf (RESET)

Parameter
Clock pulse low/high width
Clock pulse rise/fall times
Reset pulse low widthxviii
Reset pulse high widthxix
Reset pulse rise/fall times
Reset pulse setup timexx
Reset pulse hold time

tphw (RESET)

tr (RESET)

Symboltplw (CLK), tphw (CLK)tr (CLK), tf (CLK)tplw (RESET)
tphw (RESET)
tr (RESET), tf (RESET)
tsthMin.
100
012/ f(CLK)2004040Typ.
–2016 / f(CLK)–20––Max.
–
30
––
30
––

Unit
nsnsmsμs
nsns
nsxvii

The falling of Video just before the 23th falling edge of CLK after transition of RESET from Low to High corresponds to the firstpixel. The video output for the first pixel should be read around the 24th falling edge and before the subsequent rising CLK edge while
Trig is high. After the first pixel, a pixel output appears on Video at every 4th clock cycle.
Care should be taken to prevent the rising edge of the RESET during the video output. Improper positioning of the RESET edges
can lead to interference with the read-out.
The falling edge of the RESET should follow the last pixel of the previous line’s read-out. Thus, one cycle of RESET pulses cannot
be set shorter than the time equal to (34 + 4 × N) clock cycles, where N is the number of pixels.
EOS of each detector chip appears during the output of the last pixel.
xviii
RESET must stay Low [tplw(RESET)] for at least twelve clock cycles; the low pulse width tplw(RESET) should be an integer
multiple of four clock cycles [4/f(CLK)].
xixThe falling edge of RESET pulse determines the end of the integration time, while the rising edge of the RESET pulse determines
the start of the integration time and the start of signal read-out. As a result, the signal-charge integration time can be controlled
externally with the width of the RESET pulse [tphw(RESET)]. However, the charge integration does not start at the rise of a RESET
pulse but starts at the 2nd falling edge of clock after the rise of the RESET pulse and ends at the 7th falling edge of clock after the fall ofthe RESET pulse.
xxThe rising and falling edges of RESET must observe the setup and hold time requirements around the falling edges of CLK.

 -DQ5HY

3KRWRGLRGH'HWHFWRUZLWK6LJQDO$PSOLILFDWLRQ;%6HULHV Ŷ Mechanical drawingsxxi

xxi

Unit: Dimensions are in millimeters (mm).
Board: FR4 epoxy resin bonded glass fabric.
Connector: BISON Advanced Technology Corp., Ltd. (www.bison-protech.com), P101-RGP-060/030-12 or similar.

Ŷ Pin connections

PinNo.
12345Symbol

Name

Description

RESET
CLKTRIG
EXTSP
VMS

Reset Pulse
Clock Pulse
Trigger Pulse
External Start Pulse
Master/Slave
Selection Voltage

67891011VDD
GND
EOS
VIDEO
VREF
SNS

Supply Voltage
GroundEnd of Scan
Video Output
Reference Voltage
Sensitivity Selection

12RS

Resolution Selection

Negative-going pulse input
Pulse input
Positive-going pulse output
Pulse/voltage input
Voltage input:
See Master/slave selection voltage VMS and external start pulse EXTSP
settings note
5-V supply voltage
Common ground voltage
Negative-going pulse output
Negative-going output with respect to VREF
Voltage input
Voltage input:
High (VDD) for high sensitivity (Cfhs)
Low (GND) for low sensitivity (Cfls)
Voltage input:
High (VDD) for 50-um pitch
Low (GND) for 100-um pitch -DQ5HY

3KRWRGLRGH'HWHFWRUZLWK6LJQDO$PSOLILFDWLRQ;%6HULHV Ŷ Master/slave selection voltage VMS and external start pulse EXTSP settings
For most applications, multiple detectors are read out in parallel. To ensure parallel read out, set the VMS
input of all detectors to VDD (A in the table below).
In applications where two or more linearly connected detectors are read out sequentially (in series), set theVMS input of the first detector to VDD and the VMS input of each subsequent (second and later) detector toGND while connecting the EXTSP input of each subsequent detector to the EOS output of each respective
preceding detector (B in the table below). The CLK and RESET pulses should be shared among all detectors
and the Video output terminals of all detectors are connected together. The maximum number of detectorsthat can be daisy-chained together is limited by the maximum Video output capacitance requirement.

AB

Operation Mode
Master configuration:
Parallel readout: all detectors
Serial readout: 1st detector only
Slave configuration:
Serial readout: 2nd and later detectors

VMS

EXTSP

VDD

Don’t care

GND

Preceding detector’s EOS should be input

Ŷ Readout circuit
In order to minimize noise and to maximize performance, an operational amplifier should be placed as close
to the detector to amplify the Video signal.

,QIRUPDWLRQIXUQLVKHGE\;6FDQ,PDJLQJLVEHOLHYHGWREHDFFXUDWHDQGUHOLDEOH+RZHYHUQRUHVSRQVLELOLW\LVDVVXPHGE\;6FDQ,PDJLQJ&RUSRUDWLRQIRULWVXVH
8VHUVDUHUHVSRQVLEOHIRUWKHLUSURGXFWVDQGDSSOLFDWLRQVXVLQJ;6FDQ,PDJLQJFRPSRQHQWV7RPLQLPL]HWKHULVNVDVVRFLDWHGZLWKXVHUV¶SURGXFWVDQGDSSOLFDWLRQVXVHUVVKRXOGSURYLGHDGHTXDWHGHVLJQDQGRSHUDWLQJVDIHJXDUGV1RUHVSRQVLELOLW\LVDVVXPHGE\;6FDQ,PDJLQJ&RUSRUDWLRQIRUDQ\LQIULQJHPHQWVRISDWHQWVRURWKHUULJKWVRIWKLUGSDUWLHVWKDWPD\UHVXOWIURPWKHXVHRIWKHLQIRUPDWLRQ1ROLFHQVHLVJUDQWHGE\LPSOLFDWLRQRURWKHUZLVHXQGHUDQ\SDWHQWRUSDWHQWULJKWVRI;
6FDQ,PDJLQJ&RUSRUDWLRQ;6FDQ,PDJLQJ&RUS
7HO%RQDYHQWXUD'U6DQ-RVH&$86$)D[ 

ZZZ[VFDQLPDJLQJFRP-DQ5HY