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A double-sided silicon micro-strip Super-Module for the ATLAS Inner Detector upgrade in theHigh-Luminosity LHCThis content has been downloaded from IOPscience. Please scroll down to see the full text.
2014 JINST 9 P02003(http://iopscience.iop.org/1748-0221/9/02/P02003)
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P UBLISHED BY IOP P UBLISHING FOR S ISSA M EDIALABR ECEIVED: September 11, 2013
R EVISED: January 8, 2014
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S. Gonzalez-Sevilla,a,1 A.A. Affolder,b P.P. Allport,b F. Anghinolfi,c G. Barbier,aR. Bates,d G. Beck,e V. Benitez, f J. Bernabeu,g G. Blanchot,c I. Bloch,h A. Blue,dP. Booker,i R. Brenner, j C. Buttar,d F. Cadoux,a G. Casse,b J. Carroll,b I. Church,iJ.V. Civera,g A. Clark,a P. Dervan,b S. Dı́ez,k M. Endo,l V. Fadeyev,m P. Farthouat,cY. Favre,a D. Ferrere,a C. Friedrich,h R. French,n B. Gallop,i C. Garcı́a,g M. Gibson,iA. Greenall,b I. Gregor,h A. Grillo,m C.H. Haber,k K. Hanagaki,l K. Hara,o M. Hauser, p
S. Haywood,i N. Hessey,q J. Hill,i L.B.A. Hommels,r G. Iacobucci,a Y. Ikegami,sT. Jones,b J. Kaplon,c S. Kuehn, p C. Lacasta,g D. La Marra,a D. Lynn,tK. Mahboubin, p R. Marco,g S. Martı́-Garcı́a,g F. Martı́nez-McKinney,m J. Matheson,iS. McMahon,i D. Nelson,u F.M. Newcomer,v U. Parzefall, p P.W. Phillips,iH.F.-W. Sadrozinski,l D. Santoyo,g A. Seiden,m U. Soldevila,g E. Spencer,mM. Stanitzki,h P. Sutcliffe,b Y. Takubo,s S. Terada,s P. Tipton,w I. Tsurin,b M. Ullán, f
Y. Unno,s E.G. Villani,i M. Warren,x M. Weber,a I. Wilmut,i S. Wonsak,b,p R. Witharmk
and M. Wormaldb
a DPNC University of Geneva, Geneva, Switzerlandb Oliver Lodge Laboratory, The University of Liverpool, Liverpool, U.K.
c Europen Organization for Nuclear Research (CERN), Geneva, Switzerland
d The University of Glasgow, Glasgow, U.K.
e Queen Mary, University of London, U.K.
f Centro Nacional de Microelectrónica (IMB-CNM, CSIC), Barcelona, Spaing Instituto de Fı́sica Corpuscular (IFIC, Universitat de València-CSIC), Valencia, Spainh The Deutsches Elektronen-Synchrotron (DESY), Hamburg, Germany
i Rutherford Appleton Laboratory (RAL), Didcot, U.K.
j Uppsala University, Uppsala, Swedenk Lawrence Berkeley National Laboratory (LBNL), Berkeley (CA), U.S.A.
l Osaka University, Osaka, Japan
1 Corresponding author.

c CERN 2014, published under the terms of the Creative Commons Attribution 3.0
License by IOP Publishing Ltd and Sissa Medialab srl. Any further distribution of thiswork must maintain attribution to the author(s) and the published article’s title, journal citation and DOI.

doi:10.1088/1748-0221/9/02/P02003

2014 JINST 9 P02003

A double-sided silicon micro-strip Super-Module for
the ATLAS Inner Detector upgrade in theHigh-Luminosity LHC

m University of California Santa Cruz (SCIPP-UCSC), Santa Cruz (CA), U.S.A.
n The University of Sheffield, Sheffield, U.K.
o University of Tsukuba, Tsukuba, Japanp University of Freiburg, Freiburg, Germany
q National Institute for Nuclear and High energy physics (NIKHEF), Amsterdam, Netherlandsr Cavendish Laboratory, University of Cambridge, Cambridge, U.K.
s High Energy Accelerator Research Organization (KEK), Tsukuba, Japant Brookhaven National Laboratory (BNL), Upton (NY), U.S.A.
u SLAC National Accelerator Laboratory, Menlo Park (CA), U.S.A.

w Yale University, New Haven (CT), U.S.A.
x University College London, London, U.K.

E-mail: Sergio.Gonzalez.Sevilla@cern.ch
A BSTRACT: The ATLAS experiment is a general purpose detector aiming to fully exploit the discovery potential of the Large Hadron Collider (LHC) at CERN. It is foreseen that after several yearsof successful data-taking, the LHC physics programme will be extended in the so-called HighLuminosity LHC, where the instantaneous luminosity will be increased up to 5 × 1034 cm−2 s−1 .
For ATLAS, an upgrade scenario will imply the complete replacement of its internal tracker, as theexisting detector will not provide the required performance due to the cumulated radiation damage and the increase in the detector occupancy. The current baseline layout for the new ATLAS
tracker is an all-silicon-based detector, with pixel sensors in the inner layers and silicon micro-strip
detectors at intermediate and outer radii.
The super-module is an integration concept proposed for the strip region of the future ATLAS
tracker, where double-sided stereo silicon micro-strip modules are assembled into a low-mass local
support structure. An electrical super-module prototype for eight double-sided strip modules has
been constructed. The aim is to exercise the multi-module readout chain and to investigate thenoise performance of such a system. In this paper, the main components of the current supermodule prototype are described and its electrical performance is presented in detail.
K EYWORDS : Particle tracking detectors; Si microstrip and pad detectors; Performance of HighEnergy Physics Detectors

2014 JINST 9 P02003

v University of Pennsylvania, Philadelphia (PA), U.S.A.

Contents
Introduction

1

2

The double-sided silicon micro-strip module
2.1 Silicon sensor
2.2 Readout ASIC
2.3 Hybrids
2.4 Baseboard and AlN facings

3
4
6
7
8

3

The super-module electrical prototype
3.1 Service buses
3.2 DC-DC power converters
3.3 Buffer Control Chip (BCC) board
3.4 Super-Module board (SMB)
3.5 Power supplies
3.6 Data Acquisition System

9
10
11
12
13
14
15

4

Electrical performance
4.1 Leakage current
4.2 Study of electromagnetic interference emissions
4.3 Principle of the front-end calibration
4.3.1 Calibration delay
4.3.2 Single channel threshold correction
4.4 Gain and noise
4.5 Noise occupancy
4.6 Double-trigger noise

15
15
17
20
21
22
23
27
29

5

Prospects of a future module design30

6Summary

33

1

Introduction

The ATLAS experiment [1] is a general purpose detector installed at the CERN Large Hadron
Collider (LHC). During 2012, the LHC has delivered proton-proton collisions at a centre-of-mass√energy of s = 8 TeV, with total integrated and peak luminosities for ATLAS of ∼21.7 fb−1 and∼7.7 × 1033 cm−2 s−1 respectively. A major luminosity upgrade of the LHC (the so-called High
Luminosity LHC or HL-LHC) is foreseen for ∼2022, where the instantaneous luminosity willreach up to 5 × 1034 cm−2 s−1 . With a target of collecting a cumulated integrated luminosity of–1–2014 JINST 9 P02003

1

3000 fb−1 after ten years of operation at the HL-LHC, the ATLAS experiment will continue toexplore the origin of the electroweak symmetry breaking mechanism at the highest energy frontier.
The HL-LHC will allow for a rich physics programme, including high-precision measurements andsearches for new physics beyond the Standard Model.

Although the final layout has not been fixed yet, most probably the new ATLAS tracker (Inner Tracking Detector or ITK) will be an all-silicon system with new detector technologies andincreased granularity [2, 3]. Its design must ensure radiation hardness, low detector occupancy andexcellent tracking performance in a high pile-up environment. At present, the ITK baseline layout
consists of pixel detectors in the innermost layers and silicon micro-strip detectors at intermediateand outer radii. In the barrel region, at least 4 pixel layers (with a pixel size of 25 × 150 µm2 and50 × 250 µm2 in the two inner and two outer pixel layers, respectively) are followed by 5 doublesided stereo silicon micro-strip layers. The innermost 3 strip layers consist of short-strip (SS)sensors (∼24 mm strip-length), while long-strips (LS) detectors (of ∼48 mm strip-length) are used
for the two outermost layers. The whole pixel detector would extend up to a radius R ∼ 250 mm,
with the innermost layer being located at R ∼ 33 mm to be as close as possible to the beam-pipe.
The forward region is covered with 6 pixel and 7 strip disks, extending up to |Z| ∼ 1.7 m and|Z| ∼ 3 m respectively with equivalent granularities. This layout ensures an 11 hit coverage in thepseudo-rapidity range of |η| < 2.7 for interactions within |Z| < 15 cm.
Concerning the future micro-strip detector, one integration concept for the barrel region is theso-called stave concept [4], in which a common mechanical structure integrates the sensors, theelectrical lines (bus cable) and the cooling circuit. The stave is a ∼1.2 m long object that has acentral core composed of a spacing material (carbon-foam or honeycomb) and carbon fiber facings
glued on both sides of it. A bus cable for the electrical signals is laminated on top of the facings.
Single-sided silicon micro-strip detectors are glued over the bus cable and hybrids carrying thefront-end electronics are glued on top of the sensitive side of the sensors.
1 Assuming a 25 ns bunch-spacing configuration, it is expected a mean number of interactions per crossing of ∼140

and more than 1000 tracks per unit rapidity at an instantaneous luminosity of 5 × 1034 cm−2 s−1 .

–2–2014 JINST 9 P02003

As a consequence of the the increased instantaneous luminosity expected at the HL-LHC, allmajor ATLAS sub-systems (from the detectors to the trigger and DAQ systems) must be upgraded.
In particular, a complete replacement of the ATLAS internal tracker, the Inner Detector (ID), isalready anticipated. The current ID combines high resolution discrete silicon detectors (pixel andmicro-strips) at the inner and intermediate layers, with a gaseous straw-tubes detector at the largest
radii. It is composed of three sub-systems, namely from the inside: the Pixel detector, the Semiconductor Tracker (SCT) and the Transition Radiation Tracker (TRT). A central superconducting
solenoid magnet surrounding the TRT provides a 2 T solenoidal magnetic field. Although the ID
has been designed to operate ten years at the peak luminosity of 1034 cm−2 s−1 , its performance
will degrade with the cumulated effects of radiation damage and ageing, and it will approach theend of its lifetime by the end of the LHC programme (where the luminosity is expected to reach2 × 1034 cm−2 s−1 ). Moreover, due to the very high density of particles that will be produced at the
HL-LHC,1 the current ID would suffer from a large increase in both the integrated radiation damage and the detector occupancy, compromising its tracking capabilities far beyond an acceptablelevel [2].

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Hybrids

AlN facing
Washers

ABCN FE chips

Silicon sensor

The super-module is another, more conservative, integration concept in which double-sided
silicon micro-strip modules are mounted in a light, stable carbon-carbon local support structure.
In this case, a module is considered to be the minimal detector unit. The heat generated from thefront-end electronics is transferred to the cooling pipes located in the lateral sides of the support
frame. The local support is designed to hold at least 12 modules (depending on the layout), enablinga full coverage in both φ and Z coordinates (dead-space between adjacent sensors is avoided bystaggering the modules along the Z-axis) for the barrel region.
Both approaches allow the end insertion of the support into the overall barrel structure, asolution providing flexibility for integration, commissioning and rework.
This paper is organized as follows. In section 2 the double-sided silicon strip module is introduced. Its main components are briefly described. The super-module electrical prototype, an eightmodule setup developed to demonstrate the feasibility of a strip tracker based in the double-sided
strip module concept, is presented in section 3. The main electrical interfaces are explained. In
section 4, electrical results from the multi-module setup are shown. Prospects for a future module
design, using the next generation of readout ASICs, are presented in section 5. Finally, a summaryis given in section 6.

2

The double-sided silicon micro-strip module

The double-sided silicon micro-strip module (DSM) [5] is proposed as the minimal detecting unit
for the short-strip region of the future ATLAS ITK. Figure 1 shows a schematic layout of the current module design including its main components. The DSM is a top-bottom symmetric object
composed of two ∼ 10 × 10 cm2 n-on-p silicon micro-strip sensors glued back-to-back to a central Thermo-Pyrolitical-Graphite (TPG) baseboard, four bridged hybrids (each holding 20 readout
ASICs arranged in two columns of ten) placed by pairs on both sides of the module, and twoaluminium-nitride (AlN) ceramic facing plates located at each far-end of the baseboard. Eachhybrid is bridged on top of the AlN facings using a carbon-carbon sheet glued underneath theflex circuit so that the hybrids remain mechanically, electrically and thermally decoupled from thesilicon sensors. The TPG provides to the module the mechanical stability and ensures excellent–3–2014 JINST 9 P02003

Figure 1. Overview of the main components of the short-strip double-sided module (prototype version using
ABCN-25 readout ASICs, see section 2.2).

thermal contact for optimum dissipation of the heat generated by the front-end electronics. Precision washers accurately position the module on the local support structure. Figure 2 shows afully-assembled prototype module.
The main advantages of this module design include:• the two sensors mounted back-to-back allowing an accurate space-point reconstruction witha relative sensor alignment at the micron level. The modules are then centred and aligned
precisely on the local support structure.
• independent hybrid and sensor thermal paths and usage of low thermal expansion materials
with good thermal conductivity to minimize deformations during temperature cycling.
• optimization of the module design for easy handling during prototyping and quality assurance studies, these being key aspects for a large-scale production.
The thermal and thermo-mechanical performance of the current DSM prototype has been studied in detail with Finite Element Analysis (FEA) simulations under different load cases and convection effects. The reader may refer to [6] for further details.
2.1

Silicon sensor

The detectors currently used in the DSM prototypes are single-sided AC-coupled sensors with ntype readout strips in a p-type silicon bulk [7]. The n-on-p technology benefits from not suffering
type-inversion after irradiation in the n-type bulk and the sensors remain operative even if biased
under partial-depletion voltage. Figure 3 shows the mask layout of the detector. The sensors,
manufactured in a 6-inch (150 mm diameter) wafers by Hamamatsu Photonics, HPK [8], have an
area of 97.54 × 97.54 mm2 and a thickness of 320 µm. The distance from the sensitive region to thephysical cut edge is 980 µm. The bulk substrate is float zone (FZ) p-type with a crystal orientation
h1 0 0i. The n+ implants are 16 µm wide and are biased through polysilicon resistors and ACcoupled to 22 µm wide aluminium readout strips. The n+ -strips are isolated by a common p-stop–4–2014 JINST 9 P02003

Figure 2. Photograph of a real prototype double-sided module.

structure against possible shorts by surface charges. The sensors with p-stop isolation have shownbreakdown at higher bias voltages, and also better n+ -strip isolation after irradiation [9], than thosewith p-spray isolation.
The detector comprises four segments, two with axial strips parallel to the sensor edges andtwo with stereo strips inclined by an angle of 40 mrad, being the average strip length and pitchof 2.38 cm and 74.5 µm respectively.2 With 1280 strips per segment, each DSM has a total of
10240 readout strip channels. By integrating both axial and stereo strips in the same wafer, andfrom the small distance between sensors (∼400 µm from the thickness of the baseboard), true 3D
space-points are naturally created by gluing identical but 180◦ -rotated wafers on each side of thebaseboard. This facilitates the module assembly (an asset during the full-mass module production
stage), as there is no need to implement a relative stereo rotation between the two detectors as in
the case of using axial-only sensors.
Extensive tests have been performed to study the characteristics of the sensor prototypes both
before and after irradiation [10–12]. The sensors are found to satisfy all the electrical pre-irradiation
specifications in terms of full depletion voltage (FDV) and leakage current,3 as well as for coupling capacitance, bias resistance or inter-strip capacitance and resistance. The performance of
2 In the case of the modules for the long-strip region, the sensor will have just two segments of longer (4.78 cm) strips,

as the requirements in terms of channel occupancy are less stringent.
3 For a non-irradiated sensor, the FDV is specified to be less than 500 V and the leakage current must not exceed
200 µA at 20◦ C.

–5–2014 JINST 9 P02003

Figure 3. Mask layout of the short-strip silicon sensor. The main detector (largest area in the mask) is
divided into four segments. The top and second from top segments have axial strips; the bottom and second
from bottom segments have stereo strips (inclined by an angle of 40 mrad). The 6-inch wafer also contains 24
miniature sensors (P1 to P24) with different isolation structures each (p-stop, p-spray, etc.). The miniature
sensors (100 mm2 total area, 104 axial readout strips with a strip pitch of 74.5 µm) are used for pre andpost-irradiation performance studies.

1 × 1 cm2 miniature sensors irradiated to the maximum fluences (2 × 1015 1-MeV-neutrons equivalent neq /cm2 for the innermost barrel strip layer, including a safety factor of 2) has been evaluatedin terms of surface and bulk damage, charge collection efficiency and signal-to-noise (S/N) ratio. A
S/N of at least 23:1 has been measured, well above the 10:1 requiremement for an efficient tracking
at the HL-LHC.
2.2

Readout ASIC

The current prototype of the readout chip is the 128-channel ATLAS Binary Chip Next (ABCN)
produced in 0.25 µm IBM CMOS technology (hence the chip will be referred hereafter as ABCN25 [13]). Conceptually, it is very similar to the ABCD3TA chips used in the current ATLAS SCT
strip tracker [14]. An evolution of this chip using 130 nm IBM CMOS technology (the 256-channel
ABCN-13) has been recently submitted for fabrication and is intended for future evolutions of the
prototype programme.
A simplified block-diagram of the ABCN-25 chip is shown in figure 4. The chip handles thereadout of 128 channels with a binary architecture. The per-channel analogue stage comprises preamplification, shaping and differential discrimination. The binary data at the discriminator output
is latched at every clock cycle to the input register and then buffered in a 256-cell (6.4 µs) pipeline.
Upon the reception of a L1 trigger, the data corresponding to three bunch-crossings is transferred
to a second-level derandomizer buffer with 128 bits depth (43 events). Data is then transferred to
the readout buffer and compressed according to given selection criteria.
The configuration of the different chip parameters is made using read/write registers. A 128bit Mask register is used to disable bad or noisy channels to avoid an increased data rate due tofalse hits. The ABCN-25 chip receives two clock inputs, the main Bunch-Crossing clock (always
running at 40 MHz in synchronization with the beam crossing rate) and the readout clock used fordata throughput. The front-end (FE) can be configured to operate at two different readout clock
frequencies, either 40 or 80 MHz. A maximum data readout speed of 160 Mbits/s can thus beachieved avoiding deadtime. Multiplexing the data of several modules into a single optical link caneasily increase the rate to the order of several Gbits/s (with current technologies).

–6–2014 JINST 9 P02003

Figure 4. ABCN-25 ASIC block diagram.

2.3

Hybrids

A four-layer copper-polyimide (Cu/PI) flexible circuit hybrid has been designed by KEK [16] andproduced by Taiyo Industrial Co. [17]. The current hybrid layout is shown in figure 5. The size ofthe flex-circuit is 136 × 28 cm2 . The first two layers, L1 and L2, carry the main circuit patterns forthe front-end chips, including redundancy lines, while layers L3 and L4 are used for respectively
the power distribution and grounding. All Cu/PI sheets are made with adhesive-less technology,
being the thickness of the polyimide and copper sheet of 25 and 12 µm respectively. Electricalconnections among different layers are realized by either through-holes, penetrating all layers, orlaser-cut via-holes between two adjacent layers. The usage of the button plating technology (plating
in a limited area around the holes instead of having a whole plated surface) allowed to reduce by∼ 40% the weight of the bare flexible circuit with respect to the standard panel plating technique,achieving a final weight for the hybrid of 1.90 g.
A 400 µm thick and 112 mm wide carbon-carbon (CC) sheet made of uni-directional fibres isglued underneath the flex circuit to bridge the hybrid over the silicon sensor, avoiding any interference with the detector surface and allowing for a separate cooling path. Figure 6 shows photographsof the bare flex circuit top and bottom sides, and after adding the CC sheet on the bottom side. The
main functions of the CC bridge are to provide mechanical rigidity to the hybrid, to improve its
4 The space available is constrained to the current ATLAS Inner Detector volume, as the calorimeters themselves will

not be replaced for the HL-LHC operation.

–7–2014 JINST 9 P02003

The current powering scheme for the ATLAS SCT is based on parallel powering from offdetector power supplies. The increase in the number of readout channels for the upgraded ITK (anexpected increase of a factor of ∼10) imposes severe constraints for the future powering strategy.
More power must be delivered without increasing the cable density because of the lack of physicalspace4 and because of the goal of minimising the material inside the tracker. Two different lowvoltage powering schemes are currently being investigated: serial powering and parallel powering
using DC-DC voltage converters. In the serial powering scheme, several modules are suppliedwith a common constant current source and the required voltage levels are provided by shunt andvoltage regulators. In the parallel DC-DC scheme, a unique high (typically 10–12 V) input voltage
line supplies the modules, and the operating low voltage (typically 2.5 V) is obtained typicallythrough an inductor-based buck converter with a high conversion ratio and high efficiency [15].
The ABCN-25 chip implements a new power management block with two prototypes of distributed
shunt regulator circuits for the serial powering scheme, and a low drop voltage regulator to supply
the analog front-end voltage from the digital input. The nominal consumption of the analogue
front-end is 0.7 mW per channel. The digital supply current typically is ∼90 mA at 2.5 V (40 MHz).
Each channel of the front-end has an internal calibration circuit that can be used to inject atest charge into the analogue chain. Upon reception of a specific command, the voltage pulse isgenerated by a chopper circuit and injected into the channel through a calibration capacitor. Measurements of the basic analogue front-end parameters have been performed by mounting ABCN-25
chips on different test board PCBs and prototype multi-chip flex hybrids. The resulting values forthe input noise and gain (without input load), ∼400 electrons Equivalent Noise Charge (ENC(e))
and 100 mV/fC respectively, are in excellent agreement with the design values of the ASIC.

has two sets of bus lines for the redundancy operation. There
are two data links. Each link (Link0: U1-U10 and Link1:
U11-U20) handles 10 chips in the normal data flow. If U9 chipis dead, link0 handles 8 chips (U1-U8) and link1 handles 11
chips (U11-U20 and U10) via unusual U10-U11 data path.
Thus we can achieve dead chip bypass scheme. Various
powering and grounding schemes can be investigated bychanging wire bonding on the hybrid and applying external

Fig.3 layer structure of the f

Figure 5. Layout of the KEK hybrid. The four circuit layers are labelled L1 (top) to L4 (bottom).

thermal performance and in addition to reinforce the mechanical rigidity of the module once thehybrids are glued on the AlN facings of the baseboard. Seventeen thermal through-holes are added
underneath the analogue part of each ASIC. These vertical copper holes are filled with thermallyand electrically conducting glue. This ensures thermal and electrical connections between eachchip and the CC bridge. The effective thermal conductivity of these pillars is ∼40 W/m K. The
large thermal conductivity (∼670 W/m K) of the CC-sheet allows the efficient transfer of the heatgenerated by the readout chips to the heat sink located at the bridge legs. At the last stage of hybrid
assembly, a 0.8 mm pitch miniature connector is mounted at one end of the circuit layers to routethe LVDS signals towards the data acquisition system. The total weight of the hybrid, includingflex-circuit layers and CC-bridge but excluding electrical components (connector, SMDs, ASICs)
is 5.0 g, corresponding to 0.20% X0 equivalent radiation length, normalized to the sensor area.
2.4

Baseboard and AlN facings

The baseboard, currently consisting of a rectangular 127 × 79 mm2 sheet of Thermal Pyrolytical
Graphite (TPG), acts as the thermo-mechanical core of the DSM. The TPG is a pyrolitic carbonbased anisotropic material with a high in-plane thermal conductivity of ∼1800 W/m · K and low
radiation length. As the baseboard is used in direct contact to the silicon sensors, the TPG iscoated with a thin film (∼20 µm thick) of Parylene allowing for a complete electric insulation withrespect to the HV sensor backplane. The Parylene deposition is performed with a chemical vapor
deposition technique, and it includes an additional 50–80 µm glue/air matrix layer.
On each side of the baseboard, two ∼20 µm thick and 14.5 mm wide aluminium-nitride (AlN)
ceramic pieces are glued at the two far-ends. The AlN facings have a relatively high thermal
conductivity ∼180 W/m · K for an electrical insulating ceramic. Because of the choice of materials
with high thermal conductivity (to help in the power dissipation), low thermal expansion coefficient–8–2014 JINST 9 P02003

Fig.2 Layout of flexible circuit layer

mm, respectively. These rules are thecurrent SCT flexible circuit.
Fig.3 shows layer structure of thestarting core for build-up is a double-sid
sheet in the middle. A single-sided Cu/
each side of the core sheet. The thicknes
base film is 12 um and 25 um, respectiv
the top and bottom copper layers are
thickness of hybrid part and of cable p
0.165 mm, respectively. Electricaldifferent layers are realized by epenetrating all layers, or laser-cut via
adjacent layers. All Cu/PI sheets are matechnology. We adopt button plating,and low mass, an optimal heat path, allowing for an efficient flow from the parts acting as heatsources (front-end chips through the hybrid bridge feet, silicon sensors) to the cooling contacts, isensured. Furthermore, the use of the AlN facings increases the module stiffness that is reinforced
later-on once the two silicon detectors are glued to the baseboard and the bridged hybrids are glued
on top of the facings during the assembly process of the module.

3

The super-module electrical prototype

Based on the double-sided strip module (DSM) concept explained previously, a super-module (SM)electrical prototype has been developed, aimed to demonstrate the feasibility of this tracker designfor the HL-LHC and its validity even at the prototype stage. Although the different components
are in most cases first prototype versions subject to further future developments, it is important todemonstrate a common readout in a multi-module setup. The identification of the possible issues ordrawbacks while assessing the electrical response of such a large system will be helpful to improve
future prototypes for an optimum performance. A realistic local-support structure, optimized interms of component integration, material budget and thermo-mechanical performance (based on
detailed FEA simulations), has been developed separately [18].
Several DSMs have already been constructed by the University of Geneva (Switzerland) andKEK (Japan) in a joint R&D programme. Eight of these modules have been installed in the SM
electrical prototype, as shown in figure 7. The overall support structure is made in aluminium, with
inlets and manifolds for both liquid cooling and dry-air flushing. During operation, the boxed-frame
remains closed in all sides to ensure a light-tight environment and minimum relative humidity inside (∼5%). The heat generated from the front-end electronics and the detectors is transferred tothe cooling pipes running along the lateral sides of the structure. The silicon modules are mountedwith alternating sides and overlapping along the SM-length, emulating a longitudinal overlap along
the Z-direction (beam-axis direction) of the mechanical SM structure. The signals required to control the ASICs and the high-voltage lines needed to bias the sensors are driven through dedicatedmulti-layer service buses (see section 3.1). The digital low-voltage required to power the read-–9–

2014 JINST 9 P02003

Figure 6. Photographs of the bare flex printed circuit front (top) and back-side (middle), and after mounting
the carbon-carbon sheet and the 0.8 mm-pitch miniature Samtec connector (bottom).

cooling inlet

double-sided silicon modules

dry-air inlet

aluminum support frame

coolingpath

SMB-power

HV-busdata-bus

LV-bus

DC-DC converters

BCC board

SMB #2 (bottom)

(a)

(b)

Figure 7. (a) Components of the super-module electrical prototype. Only the top-side is shown. The
same components (SMB, service buses, BCCs and DC-DC converters) are installed on the bottom side.
(b) Photograph of the super-module with eight double-sided modules installed. The total length of thealuminium boxed-frame is ∼110 cm.

out ASICs is provided by prototype DC-DC converters (see section 3.2). The analog voltage forthe front-ends is obtained from the digital voltage via the ABCN25 on-chip linear voltage regulators. For each hybrid, a dedicated Buffer-Control-Chip (BCC, see section 3.3) multiplexes thedata-signals coming from the two columns of ten ABCN-25 chips into a single data-stream. A
Super-Module-Board (SMB, see section 3.4) not only receives each multiplexed data-stream coming from up to 16 BCCs and interfaces them to the external Data Acquisition (DAQ) system (seesection 3.6), but it also provides the interface between the different voltage buses and the external
power supplies.
3.1

Service buses

The electrical SM comprises two identical sets of a first version prototype service buses (one set
is located on each side of the SM). These are ∼765 mm long double copper-layer flexes designed– 10 –

2014 JINST 9 P02003

SMB #1 (top)Table 1. Parameters of the service buses. Thicknesses and widths are given in mm. † Data bus trace widths(mm): 0.10 (point-to-point), 0.12 (multi-drop) and 0.20 (rest). ∗ LV bus trace widths (mm): 6.8 (10–12 V),
2.2 (3.3 V) and 9.5 (GND).

HV

Data

LV

2

2

2

• Layer 1

8

28

2

• Layer 2

8

28

1

Trace width

0.2

0.1 - 0.2†

2.2 - 9.5∗

Cu-layer thickness

0.035

0.035

0.2

9.6 / 22.3

16.0 / 26.0

10.0 / 10.0

Total number of layers
Total number of traces:and produced at CERN. Each set is composed of a High-Voltage (HV) bus, a Data bus and a LowVoltage (LV) bus. The main parameters of the buses are listed in table 1. In most cases, the top
layer contains a certain number of traces for the signals and the bottom copper (Cu) layer is usuallyused as a common ground plane for the given bus. The distance between the two layers is 200 µm.
• The HV bus drives the HV supply and return lines for up to 8 silicon sensors.
• The LV bus drives the 10–12 V voltage required to operate the DC-DC converters, and the
3.3 V supply for the different components of the BCC board. The 10 mm-wide and 200 µm
thick LV bus Cu bottom-plane is a ground plane common to the 10–12 V and 3.3 V supplies,
able to stand a maximum current of ∼16 A.
• The Data bus has 16 Low Voltage Differential Signaling (LVDS) pair lines (2 per module
side, one for each hybrid for the two-column multiplexed data stream) connected point-topoint from each BCC board to the SMB, and three multi-drop LVDS lines from the SMB
to each BCC board (for clock and command signals). The widths of the LVDS traces (100and 120 µm respectively for the point-to-point and the multidrop traces) have been optimized from simulations with Cadence OrCAD Signal Explorer [19] in order to achieve aline impedance of 120 Ω, being the termination resistor of 100 Ω (best results in terms of
maximum signal amplitude and minimum reflections). Additional lines (200 µm wide) include a 1-wire bus, the reference voltage for the thermistor located in each hybrid and thecorresponding voltage (i.e. temperature) return line.
Both the HV and data-buses are connected to one SMB board via Samtec connectors. Due tothe high-current load, the two large traces of the LV-bus are directly soldered to a simple PCB (socalled SMB-power board as shown in figure 7).
3.2

DC-DC power converters

The prototype DC-DC power converter used in the electrical SM is the SM01C module developedat CERN [20]. It is a low noise plug-in converter module (see figure 8) based on a buck con-

– 11 –

2014 JINST 9 P02003

Minimum / Maximum bus width

!"#$%&'%('%&%)*+,-.,-&
Datasheet V1Georges.blanchot@cern.ch"/0*&1,/.2-,3&&12*4.0)*/5&'0/6-/
VIN

ENABL
PGOOD
Figure8)9,-&:*.,-;/4,!

The SM01C power converter is a pluggable power module

The power interface ismodule through a high dmale type FTE-116-03-G
mounted on the receivin
G-DV-A from Samtec.

based
the Linear Technology
LTC3605 buckcontroller. Its
Figure 8. SM01C DC-DC converter without (left) and with (right)
itsonpolyethylene
shieldingbox.

Non isolated DC to DC synchronous buck converter.
Wide input voltage range: 7V to 15V.
Fixed 2.5V output voltage.
High switching frequency: 2 MHz.
Output current up to 5A.
High efficiency, typically 85% at 2A output current.
Very low conducted and radiated noise.
Compatible for operation in high DC magnetic fields.
Thermal interface for optimal conduction cooling.
Enable function input pin.
Power good monitoring pin.
Compact design.

Figure 9. Photograph of several DC-DC converters already mounted in the SM over support-brackets. The
cooling circuit, running along the lateral side of the SM frame and going through the interface between top
and bottom brackets, is visible.

troller ASIC, and containing a coreless (air-core) toroidal inductor to store the energy in the formof a magnetic field, and to be compatible with the magnetic environment within the tracker. The
converter operates with an input voltage of 10–12 V and provides a regulated 2.5 V with a maximum current of 5 A and a nominal conversion efficiency of ∼80% [20], enough to power a fully
populated hybrid with 20 ABCN-25 readout ASICs. While the DC-DC converter provides the digital voltage needed to operate the DSM readout chips, the analog voltage for the FE is produced - 1 internally by the ABCN-25 on-chip voltage regulator.
In order to limit the effect of electromagnetic emissions from the converter, a polyethylene(PE) shielding box with a 10 µm coated Cu-layer is used (see figure 8, right). The coated PE
box was measured to provide an effective shielding effectiveness similar to the one obtained withthe baseline shield assembly (35 µm copper foil box), resulting in a magnetic field attenuation of∼32 dB [20].
The converters are mounted over L-shaped aluminium support-brackets attached to the SMframe. An insulating thermally conducting sheet is placed in between each bracket and the corresponding converter backplane to optimize the heat flow. A cooling circuit runs through the interface
between all support-brackets (see figure 9).
3.3

Buffer Control Chip (BCC) board

The BCC board (see figure 10) is a 80 × 48 mm2 PCB that serves as the interface between the
hybrids and the service buses. It contains two Buffer Control Chip (BCC) ASICs (one per hybrid),
packaged in a 7 × 7 mm2 LLP48 (Lead-less Lead-frame Package). The BCC is a dedicated ASIC
produced by TSMC [21] in a 250 nm technology. Its purpose, limited to prototype studies only, is– 12 –

2014 JINST 9 P02003

design is optimized to operate from a 10V input voltage,
delivering a regulated 2.5V output up to 5A output current. Its
layout is optimized to achieve very low levels of conducted andradiated noise, making it compatible for the powering of highly
sensitive front-end electronics in physics experiments. The useof non ferromagnetic materials makes it suitable for operation inpresence of strong DC magnetic fields. A cooling thermal pad isprovided for conductive cooling. The converter is fitted with a 32
pins high density Samtec connector used as input and output
power board interface; it integrates also enable and monitoringlines.

Figure 2: Top view and p

Pin Number
1,3,4,5,6
21,22,23,24,25,26
28,29,30,31
7,8,9,10,11,12,13
15,16,17,18,19,20
32
2

The ground pins are com
ports and they must be dreceiving board. It mustfull output current and th
must be done through vi
The same rules must b
input voltage and output
pads are preferred over

HV-busHybrid 2

48 mm

Hybrid 1

BCC 1

BCC 2

80 mm
DC-DC 1

LV-bus

DC-DC 2

Figure 10. The BCC board, serving for the control and readout of two hybrids. It contains two LLP48packaged BCC ASICs.

two-fold: multiplexing the data coming from the two columns of ten ABCN-25 ASICs into a single
data stream and providing an 80 MHz readout clock through a clock-multiplication circuitry.
The BCC chip receives three LVDS input signals through the multi-drop lines of the Data bus:
the main 40 MHz Bunch-Crossing clock, the Command line and the L1R5 line. Before being distributed to each BCC chip, the clock and command signals pass through LVDS drivers-repeaters(implemented on the BCC board) for an optimum signal quality. Upon reception of a L1 trigger,
the readout sequence of the ABCN-25 chips starts sequentially, using a token-passing mechanism
for the data transmission. The data coming from each of the two columns of ten ABCN-25 chips
is multiplexed by the BCC into a single data-stream at twice the readout clock (maximum rate of
160 Mbps). The multiplexed stream is then transmitted towards the SMB board via the corresponding point-to-point line of the Data bus. The address of each BCC chip is uniquely set via a DIP
switch.
The BCC board also implements the required connections for the plugin DC-DC power converters. A DS2408 1-wire chip is used to monitor and control the state line (enable / disable) of
each individual DC-DC module through a custom LabVIEW [22] application. A low-power comparator is used to implement a logic circuit that automatically disables the DC-DC converters if thehybrid temperature (as measured with a thermistor located in each hybrid flex) is above a given
threshold.
3.4

Super-Module board (SMB)The Super-Module board (SMB) interfaces the off-detector high and low-voltage power lines andexternal clock and control signals to the service-buses. A single SMB (see figure 11) serves one
side of the SM prototype, i.e., a single-side of up to 8 DSMs.
5 A multiplexed signal containing both the L1 trigger and the RESET signals.

– 13 –

2014 JINST 9 P02003

DS2408 1-wiredata-busElectrical interfaces
High-voltage

M-LVDS driver(CLK, COM, L1R)
Data
(50-pin)

HV-bus

140 mm

RJ11 interface for
1-wire control

Data-bus

LVDS repeaters (data)

84 mm

Figure 11. The Super-Module board (SMB). The top and bottom-sides of the SMB are shown in the left andright images respectively.

The board contains eight LEMO connectors to drive the HV for the sensor bias. The control
and data LVDS signals are interfaced to the external DAQ through 0.050” 40/50-pins connectors.
Sergio GonzalezWeek - 130513
SergioTheboardGonzalez-Sevilla
implements 16 LVDS buffers, one for ATLAS
eachUpgrade
data-line
connected point-to-point from eachSevillaBCC-board to the SMB. Three M-LVDS drivers are used for the multi-drop LVDS signals. The
adoption of the M-LVDS driver was motivated by the observed improvement in the quality of themulti-drop signal along the data-bus if compared with standard LVDS repeaters. An RJ11 interface
located in the backplane of the SMB is directly connected to the control PC via an iButton USBbridge [23] to control the 1-Wire R network.
3.5

Power supplies

For the HV power-supply (PS), an ISeg ECH224 [24] crate equipped with two 6U Eurocard format
8-channel HV-modules (EHS-8210n-F) is used. Each HV-module provides 8 independent output channels with controllable voltage and current control. The HV output per channel is madethrough isolated built-in SHV connectors, adapted to LEMO format connecting to the SMB. A
CAN-to-USB interface from PEAK System [25] provides one high-speed CAN channel for thecontrol through an external PC via a USB port. A custom LabVIEW application implements thecommunication with the hardware and is used to monitor the status of the HV-modules and to
perform I-V measurements.
The 10–12 V common input line for the DC-DC converters is provided by a commercial TDKLambda Genesys power supply [26], a source able to deliver a constant output voltage up to 20 V
with a maximum current of 76 A. The PS features voltage protection levels (over and under-voltage
limits), an embedded microprocessor controller and voltage (and current) high resolution adjustment by digital encoders. The output load wires are connected to the PS rear panel bus-bars throughscrewed terminal lugs and routed to a home-made power distribution board with two separated outputs (one for each of the two LV-buses).

– 14 –

2014 JINST 9 P02003

Temps(40-pin)1

41 cm

8 cm

Interface board

20 cm

32.5 cm

Figure 12. The HSIO main board (32.5 × 20 cm2 ) together with its interface card (41 × 8 cm2 ).

3.6

Data Acquisition System

The Data Acquisition System (DAQ) used for the results presented in this paper is the so-called
High Speed Input Output (HSIO), a generic DAQ developed at SLAC to provide signal processing
capabilities for various silicon tracking upgrade projects (Pixel and Strips) in ATLAS. The HSIODAQ (see figure 12) is composed of a generic main board implementing a Xilinx Virtex 4 Field
Programmable Gate Array (FPGA) for data acquisition and processing, and of an Interface Card
(Rear Transition Module in the ATCA standard) containing the specific connectors and buffering
to interface to the FE electronics via the two SMB boards. Several NIM I/O ports allow to monitor
the state of specific LVDS lines, and ADCs are used for the readout of the hybrid thermistors.
The analysis software is based on the SCTDAQ package [27], a set of C++ routines and libraries
interfaced to the ROOT analysis framework [28] developed in the past for the electrical tests of thecurrent ATLAS SCT modules.
The HSIO system implements 32 MB DDR SDRAM, several standard network connections(RJ45, Giga-Ethernet, SFP, XFP) and USB interface chips. For the communication with the control
PC, a small form-factor pluggable (SFP) transceiver module is used with an Ethernet networking
cable. The network interface uses raw Ethernet protocol without any UDP or TCP/IP layers on top.

4

Electrical performance

4.1

Leakage current

The IV characteristics of the silicon sensors are measured at different stages of the module assembly
process. Figure 13 shows typical IV-curves of one double-sided module prototype. The leakage
current is measured as a function of the reverse bias voltage, with probe-needles before bonding
and through a dedicated PCB once the module has been completed. The current specification, set– 15 –

2014 JINST 9 P02003

Main board

-Ileak [nA]

1000
900

W51 - HPK

W69 - HPK800

W51 - Wafer

W69 - Wafer

W51 - Wafer glued (top)W69 - Wafer glued (bottom)

W51 - Hybrid glued (top)W69 - Hybrid glued (bottom)

700
600

Module

500
400
300

100
0
0

200

400

600

800

1000
Vbias [V]Ileak [nA]

Figure 13. IV characteristics at different stages of the assembly of a typical module (silicon wafers W51
and W69 were used for the top and bottom sides respectively). The leakage current of the module is the sumof that of both sensors.

103

DSM 1 - top
DSM 1 - bot
DSM 2 - top+bot
DSM 3 - top
DSM 3 - bot
DSM 4 - top+bot

102

0

200

400

600

DSM 5 - top
DSM 5 - bot
DSM 6 - top+bot
DSM 7 - top
DSM 7 - bot
DSM 8 - top
DSM 8 - bot

800

1000
Vbias [V]Figure 14. IV characteristics of all eight double-sided modules installed into the SM protoype.

with large margin, is that the leakage current must not exceed 200 µA for a bias voltage of 600 V(20 ◦ C). The results for the bare sensors are in good agreement with the measurements performedby the fabricant [8], all of them well below the current limit. No significant increase of current isobserved after gluing the sensor to the baseboard.
Figure 14 shows the IV characteristics of all eight double-sided modules after being installed
into the SM electrical prototype. The high-voltage is driven by the HV-bus through the SMB cards.
In some cases an electrical coupling is observed between both sensors of the same module, thesource of which could not yet be identified. As mentioned in section 2.4, the TPG baseboard is– 16 –

2014 JINST 9 P02003

200

H

coated with a thin Parylene coating with an additional glue/air matrix layer for electrical insulation.
Although having local defects (pin-holes) that could create electrical insulation weaknesses can
not be excluded (e.g. due to some surface damage handling or encapsulated carbon debris), thatpossibility is thought to be unlikely. In any case, a common bias of the two sensors does not
represent an issue for the module electrical performance.
In future module designs, several possibilities are currently being investigated, e.g increasing
the thickness of the Parylene coating, combining the HV supply to both sensors of the same module
or even several sensors from different modules (in order to further reduce the number of required
HV-lines).
4.2

Study of electromagnetic interference emissions

Since the SM prototype remains a complex system with many electrical components susceptible
to transmit externally generated noise, it remains of particular importance to minimize the electromagnetic interference (EMI) from the High-Frequency (HF) emissions from both the surrounding equipment and the DC-DC power converters in the system under test. Several measurements
have been performed with a ZVL-6 Rohde & Schwarz [29] (R&S) analyzer, together with the
R&S R HZ-14 probe set (see figure 15, left) for electric and magnetic near-field measurements.
The H-field passive probe used covers the frequency range 9 kHz to 30 MHz. It has a directivity
loop antenna and it is electrically shielded so that capactive coupling is suppressed and the electricfields are rejected. The omnidirectional capacitively coupled active E-field probe covers the entire
frequency range.
The principle of the measurement of the magnetic field is sketched in figure 15 (right). A
time-varying current in the conductor under test will cause a small amount of power to be radiated,
the power being proportional to the current and the dimensions of the conductor itself. The radiatedmagnetic field (H) passing though the end-face of the probe generates a voltage at the probe output.
The voltage is proportional to the change of magnetic flux though the circuit loop, thus allowing
to measure the component of the field that is perpendicular to the probe end-face. An averageantenna-factor has been used for the range of frequencies of interest (between 1 and 10 MHz).
Radiations from the DC-DC power converters. The SM01C DC-DC power converter comprises an air-core toroidal inductor to store the energy. Although most of the field is well confined– 17 –

2014 JINST 9 P02003

Figure 15. R&S R HZ-14 probe set (left) and operating principle of the field-measurement (right).

#2

y
z

40
H-field component

30

Hx
Hy

20

Hz

10

-20

-20

-30

-30

-40

-40
5

-50
1

2

3

4

5

6
7 8 9 10Frequency [MHz]~Figure 16. Components of the H-field
as a function of frequency as measured on top of two DC-DC power
converters (each with its shielding box). DC-DC #2 and #11 ae shown on the left and right plots, respectively.
In each case, the the top schema shows the definition of the coordinate system (the z-axis points inwards,
perpendicularly to the plane of the page).

within the coil volume, there is a parasitic magnetic field emitted through the central hole of thetoroid [30] (equivalent to a single-turn coil of diameter equal to the central toroidal hole). The
shielding-box around the toroid allows to efficiently reduce the radiated emissions without affect~ field as a function of frequency
ing the inductance. Figure 16 shows the three components of the H
as measured on top of two random DC-DC converters. The orientation of the probe was changed~
to measure qualitatively the different components of the H-field.
As expected, the field peaks atevery harmonic of the 2 MHz carrier of the DC-DC converter.
Figure 17 shows for all DC-DC
q power converters the three different components of the H-field~
and the total magnitude |H| = Hx2 + Hy2 + Hz2 as measured as the amplitude of the first harmonicpeak (∼2 MHz).
Two different configurations are compared to check the effect of surrounding converters: all
16 converters of either the top or bottom-sides of the Super-Module (SM) enabled, and all 32
converters enabled. Although no conclusive statement can be raised with respect to the dominantfield-component, as both the orientation of the air-core toroid inside each DC-DC converter6 andthe orientation of the probe itself7 have a direct impact in the measurements, it can be seen thatsome DC-DC power converters have a stronger emission than others. In general the Hx and Hy
components are higher than Hz . There are no significant changes in the radiated fields when all 32
converters are enabled, if compared with the case when 16 converters are enabled.
Common-mode conducted noise. Due to the compact topology of the service buses it was notpossible to measure the individual contribution of each DC-DC power converter in the SM except by modifying the LV-bus. Figure 18 shows the overall common-mode conducted noise fromthe TDK-Lambda power-supply (PS) used to provide the 10–12 V input line required by DC-DC
power converters. The measurement is performed at the input of the SM with a common-mode
6 Every inductor in the DC-DC power converter can have a slightly different tilting angle with respect to its supporting

PCB (see figure 8a).
7 Despite the authors took care of always trying to achieve the same spatial orientation of the probe, a small deviation
with respect to any of the three directions can lead to a non-maximal coupling of the field.

– 18 –

2014 JINST 9 P02003

6
7 8 9 10Frequency [MHz]

Hz

10
0

4

Hx
Hy

20

-10

3

x

H-field component

30

0

2

z

40

-10

-50
1

y

Service bus

x
H-field [A/m]

H-field [A/m]Service bus#11Hx [A/m]Hx [A/m]

15
16 DC-DCs enabled (SM top-side)
32 DC-DCs enabled (SM top & bottom-sides)

15
16 DC-DCs enabled (SM bottom-side)
32 DC-DCs enabled (SM top & bottom-sides)

10

10

5

5

0

0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Hy [A/m]Hy [A/m]

DC-DC power converter

16 DC-DCs enabled (SM top-side)
32 DC-DCs enabled (SM top & bottom-sides)

15
16 DC-DCs enabled (SM bottom-side)
32 DC-DCs enabled (SM top & bottom-sides)

10

10

5

5

0

0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

DC-DC power converter
Hz [A/m]

Hz [A/m]

DC-DC power converter
15
16 DC-DCs enabled (SM top-side)
32 DC-DCs enabled (SM top & bottom-sides)

15
16 DC-DCs enabled (SM bottom-side)
32 DC-DCs enabled (SM top & bottom-sides)

10

10

5

5

0

0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

16 DC-DCs enabled (SM top-side)
32 DC-DCs enabled (SM top & bottom-sides)

15
16 DC-DCs enabled (SM bottom-side)
32 DC-DCs enabled (SM top & bottom-sides)

10

10

5

5

0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DC-DC power converter

Htot [A/m]

Htot [A/m]DC-DC power converter15

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DC-DC power converter0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DC-DC power converter~
Figure 17. Amplitude for all DC-DC power converters of the different components of the H-field,
Hx (top),Hy (middle-top)q and Hz (middle-bottom), as measured at the first harmonic-peak. The magnitude of the total~
field |H| = Hx2 + Hy2 + Hz2 is shown in the bottom-plot. Two cases are compared: when all 16 DC-DC
power converters (open markers) of a given SM-side are enabled (SM top and bottom-sides shown on theleft and right hand-side plots, respectively), and when all 32 DC-DC power converters are enabled (filledmarkers).

– 19 –

2014 JINST 9 P02003

DC-DC power converter15

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Table 2. Configurations used to study the common-mode conducted noise from the Low-Voltage PowerSupply (LV PS) used for the supply of the DC-DC power converters.

LV configuration

Description
LV PS switched OFF

LV-CFG-1

LV PS switched ON, output OFF

LV-CFG-2

LV PS switched ON, output ON, all 32 DC-DC power converters disabled

LV-CFG-3

LV PS switched ON, output ON, all 32 DC-DC power converters enabled

LV-CFG-0

0

LV-CFG-1
LV-CFG-2-2050Noise [dB]20

LV-CFG-1 - LV-CFG-0

4030

LV-CFG-2 - LV-CFG-0
LV-CFG-3 - LV-CFG-0

LV-CFG-3

-40

20

-60

10

-80

0

-100

-10

-120

-20

1

2

3

4

5 6 7 8 910

20

30

40 50

Frequency [MHz]

1

2

3

4

5 6 7 8 910

20

30

40 50

Frequency [MHz]Figure 18. Common mode conducted noise (left) from the LV PS used for the supply of the DC-DC power
converters for different configurations (left) and difference of configurations LV-CFG-1 to LV-CFG-3 withrespect to LV-CFG-0 (right). See table 2 for a description of the corresponding configurations.

current probe encircling all the LV wires entering into the SMB-power board. The four different
configurations listed in table 2 are compared. A significant increase of the noise can be observed
around 5 MHz just when the PS is switched-on (but still without driving any current, and the output
switched-off). Several additional noisy peaks are visisble at ∼ 20 MHz and ∼45 MHz. Enabling
the DC-DC power converters does not produce a noise increase, so the input-filter located in each
DC-DC is found to be adequate in this respect.
Electric field. Figure 19 shows the electric field as measured on a particular strip module flex
hybrid, for different configurations of the HSIO DAQ as summarized in table 3. The main HSIODAQ board contains some internal DC-DC front-end converters that appear quite noisy between 1
and 10 MHz. An external noise at ∼13.5 MHz, for which the source could not be identified, is also
visible. When the DAQ is powered-on, a spike at ∼42 MHz is visible, corresponding to the 40 MHz
data-bus clock signal. The measurements presented in the following sections were performed after
by-passing the HSIO DAQ internal converters with an external laboratory-standard power-supply.
4.3

Principle of the front-end calibration

The electrical performance of the strip module is evaluated by analyzing the data coming fromparameter scans. In a scan, a parameter is varied according to a defined range and step. The mostcommonly used is the threshold scan: the discriminator threshold is varied and a fixed calibration– 20 –

2014 JINST 9 P02003

Noise [dB*0.1A]

LV-CFG-0

Table 3. Configurations set to study the electric field on a particular flex hybrid.

Description

DAQ-CFG-0

HSIO DAQ switched OFF

DAQ-CFG-1

HSIO DAQ switched ON, internal 12 V converters

DAQ-CFG-2

HSIO DAQ switched ON, external 12 V supply

40
30

50

Noise [dB]50
DAQ-CFG-0
DAQ-CFG-1

DAQ-CFG-1 - DAQ-CFG-0

40
DAQ-CFG-2 - DAQ-CFG-0

30

DAQ-CFG-2

20
10

20

0

10

-10

0

-20
-10

-30
-40
1

-20
2

3

4

5 6 7 8 910

20

30

40 50

1

2

3

4

5 6 7 8 910

Frequency [MHz]

20

30

40 50

Frequency [MHz]Figure 19. Electric field as measured in a strip-module flex hybrid for different DAQ configurations (left)and difference of configurations DAQ-CFG-1 and DAQ-CFG-2 with respect to DAQ-CFG-0 (right). See
table 3 for a description of the corresponding configurations.

charge is sent many times at each threshold point. The hit occupancy (normalized count rate) isthen determined as the fraction of input signal pulses exceeding the threshold. Although ideally thehit occupancy would follow a step function, in reality the distribution is smeared by the electronicnoise. Figure 20 illustrates a threshold scan in which a calibration pulse is convoluted with aGaussian-distributed electronic noise.
Assuming the input charge distribution is described by a Gaussian probability distributionfunction f (x) of mean µ and variance σ 2 , with x being the calibration signal amplitude, then theprobability p(τ) that the signal is larger than a given threshold τ is:Z ∞p(τ) =

Z ∞f (x) dx ∝

τ

τ





(x − µ)2
τ −µ
√
exp −
dx ∝ erfc
2σ 22σwhere erfc is the complementary error function. The resulting occupancy-versus-threshold curveis hence called an s-curve, as due to the characteristic S-shape of the erfc function. The thresholdat which the occupancy is 50% is called the vt50 point, and it corresponds to the input charge
amplitude (i.e. the mean value of the Gaussian distribution). The width of the distribution gives ameasurement of the noise amplitude at the discriminator output. The threshold difference between
the 16% and 84% hit occupancies corresponds to 2σ .
4.3.1

Calibration delay

The calibration of the FE of the ABCN-25 ASIC is performed by injecting test charges into theanalog circuitry. Each of the 128 channels has an internal calibration capacitor connected to its in-– 21 –

2014 JINST 9 P02003

E-field [dB V/m]

DAQ configuration

Occupancy

2σ

1
84%

0.8
0.6
50%

0.4
16%

0

vt 50

τ

Threshold

Figure 20. Illustration of threshold scan. The threshold is varied in steps and a calibration pulse is injecteda certain number of times at each threshold point. The total input signal results from the convolution of thecalibration pulse and some electronic noise that is described by a Gaussian distribution function. For a given
threshold τ, the hit occupancy corresponds to the fraction of signals above the threshold (dashed area). vt50
is the threshold for which the occupancy is 50%.

put. A specific command triggers the generation of a pulse that simulates a hit in a strip (equivalent
to the charge collected after the passage of a charged particle through the silicon sensor). Both theamplitude and the delay of the calibration pulse with respect to the clock phase (the relative delayof the rising edges) are controlled by a specific register (CalDelay) of the ABCN-25 ASIC. Within
the chip there are a total of four calibration lines; every fourth strip is connected to same line, sothat 32 channels can be tested simultaneously. The preamplifier-shaper circuit delivers a signal
with a peaking time of 25 ns (including the effect of charge collection time), which is enough toensure that the discriminator timewalk is less than 16 ns [13].
The optimization of the delay between the calibration charge and the clock is achieved bycomputing the channel occupancy for different settings of the CalDelay register. Figure 21 shows
an example for a single channel. The optimum delay corresponds to the DAC value for which thesampling is done at the maximum of the signal (maximum occupancy at the plateau). A uniquedelay is set in a chip-basis corresponding to the mean of the distribution of the optimum delays for
all channels within that chip.
4.3.2

Single channel threshold correction

The discriminator is used to discard signals with an amplitude not exceeding a given threshold.
The threshold is common for all channels within the ABCN-25 ASIC, and it is set as a differential
voltage adjustable by an internal DAC with 8-bit resolution. To compensate for channel-to-channel
threshold variations (each channel has a particular offset of its discriminator with respect to thecommon chip threshold), a 5-bit DAC (TrimDAC) is used to set an individual threshold correction
for each channel, guaranteeing uniformity across the chip. The TrimDAC has eight selectable
voltage ranges, with 32 steps (or settings) available within a given range. It is expected that the– 22 –

2014 JINST 9 P02003

0.2
p( τ)

Occupancy

1

0.8
0.6
0.4

0

0

10

20

30

40

50
60
CalDelay [DAC]

Figure 21. Occupancy as a function of the calibration delay setting (DAC units) for a single channel. EachDAC unit corresponds to 1 ns.

TrimDAC would be adjusted to higher ranges along the life of the experiment, to compensate forthe increase of the offset spread induced by radiation damage to both detectors and electronics.
The trimming procedure aims to determine the individual channel threshold correction settings. For each channel and for all ranges, a fixed calibration charge is injected into the analog
circuit and threshold scans are taken for different settings of the TrimDAC. The vt50 thresholds are
extracted by fitting the s-curves and then a linear fit is performed to the vt50 versus trim-setting.
For several threshold targets, the number of trimmable channels is computed. A channel is said
to be trimmable if the setting that needs to be applied to correct for the offset with respect to thetarget lies in the available range of the DAC. Typically the target is chosen as the minimum value
for which a maximum number of trimmable channels within a given column is found. Once thetarget selected, the individual channel threshold correction (i.e, a specific step of the TrimDAC
for the selected range) is computed. Figure 22 shows a threshold scan for a column of ten chips
before and after applying the trimming procedure. An excellent threshold uniformity is achieved
after trimming. Figure 23 shows, for a particular chip, the resulting s-curves after projection of
the occupancy to the threshold axis in the threshold-scan plot (Figure 22). Typically, the thresholdspread is reduced from 7–8 mV to 1–2 mV after the trimming corrections are applied.
4.4

Gain and noise

The gain and noise at each strip-channel discriminator input can be determined by performing
threshold scans for different input charges injected through the internal ABCN-25 FE calibration
circuit. In the case of injecting three input charges (so-called Three-Point-Gain test), for eachreadout channel a linear fit is performed to the vt50 threshold points versus charge, so that the slope
and intercept of the fit correspond respectively to the gain and threshold offset. As the readoutchips produce a signal proportional to the input charge, the 50% threshold values increase withhigher amplitudes of the calibration charge. The standard deviation of the s-curve is an effective
measurement of the noise at the discriminator output for that charge. The input noise, typically– 23 –

2014 JINST 9 P02003

0.2

0.8

220

0.7

200

0.6

180

0.5
0.4

160

0.3

140

0.2

120

0.1

100
0

200

400

600

800

1000

1200
Channel number

0

1

240

0.9

220

0.8

200

0.7
0.6

180

0.5

160

0.4

140

0.3

120

0.2
0.1

100
0

200

400

600

800

1000

1200
Channel number

0

20

15

0.8

60

0.6
20

5

0.4

0.4
0
120

0.2
0

80

40

10

0.6

1

Entries / 2 mV

0.8

Occupancy

1

Entries / 2 mV

Occupancy

Figure 22. Threshold scan for 1 fC input charge for all 1280 channels of one column of ten chips, before(top) and after (bottom) trimming. The horizontal axis is the channel number, the left-vertical axis is thethreshold [mV] and the right-vertical color-scale is the channel occupancy.

100

200

140

0
140

160
180
vt50 [mV]

0.2
0

300
Threshold (mV)

100

200

160

180
200
vt50 [mV]300
Threshold (mV)

Figure 23. S-curves for all 128 channels of a chip before (left) and after (right) applying the individual
channel threshold correction. The measurements correspond to a threshold scan for a 1 fC input charge. The
data-points are fit to a complementary error function. In each case, the inset shows the distribution of thevt50 point obtained from the S-curves.

given in electrons Equivalent Noise Charge (ENC(e)), is simply calculated as the output noise
divided by the amplifier gain. Figure 24 shows an example of the resulting distributions of gain,
threshold offset, output noise and input noise for all channels within a single column of ten ABCN-– 24 –

2014 JINST 9 P02003

Threshold (mV)

Occupancy

0.9

240

Occupancy

Threshold (mV)1260

Table 4. Different operating configurations used to test the electrical Super-Module.
Run configuration

Description# DC-DCs power
converters enabled

RUN-CFG-0
RUN-CFG-1-top
RUN-CFG-1-bot- 8 module-sides (SM top-side) tested simultaneously- DC-DC power converters on opposite sides disabled- 8 module-sides (SM bottom-side) tested simultaneously- DC-DC power converters on opposite sides disabled- 8 module-sides (SM top and bottom-sides) tested simultaneously- DC-DC power converters on opposite sides enabled

2
16
16
32

25 ASICs after trimming. The uniformity of gain and noise is very good. The average gain is invery good agreement with the nominal ABCN-25 design value of 100 mV/fC, and the input noise
matches very well the expected ∼600 ENC(e) (from the current short-strip input capacitance).
Figure 25 shows the input noise as a function of temperature for two different hybrids. The
chiller temperature was varied from 28 ◦ C to -4 ◦ C (in steps of 4 ◦ C). Enough time was allowed
to reach a steady thermal equilibrium. The temperature of each hybrid was measured via its corresponding thermistor. In each case, the input noise is obtained from a Three-Point-Gain test and it
corresponds to the mean value of a Gaussian fit to the average of that of the two hybrid columns.
The vertical error bar at each data point corresponds to the standard deviation of a Gaussian fit to
the noise distribution for the corresponding hybrid. A linear fit indicates a small dependence of thenoise with respect to the temperature, with a variation of ∼ 1.4 ENC(e) / ◦ C. Similar results are
obtained for other hybrids. As the maximum temperature variation accross hybrids is ∼15 ◦ C, any
temperature-dependence of the noise is well covered by the noise uncertainty (typically ∼25–30
ENC(e)), and no temperature-dependent correction was applied in subsequent tests.
Figure 26 shows the input noise as a function of the bias voltage of the sensors for all eight
double-sided modules. In each case, results for the module top-side silicon sensor are shown. As
expected, the noise is larger for low bias voltages, and decreases with increasing bias. A plateau
is reached when full depletion is achieved (∼200 V). Unless stated otherwise, the results shown in
the following correspond to a sensor bias voltage of 250 V.
Figure 27 shows the average gain and input noise for all eight-modules installed in the SM
prototype. Three different cases are compared as summarized in table 4. The results show that there
is not a significant noise increase while comparing cases from RUN-CFG-0 and from RUN-CFG1-top/bot, so that radiated fields from surrounding DC-DC converters have only a small impact on
the sensors located on the same side of the SM-prototype. However, while testing 8 single-side
modules with the DC-DC power converters of the opposite sides being enabled (RUN-CFG-2), thenoise increases significantly, in the range of [∼10 ENC(e); ∼60 ENC(e)]. The gain is consistent
with the design values in all cases.
There is particular case (module 6) which presents a large noise increase that can’t be correlated with any particularly noisy DC-DC converter. Therefore, while testing a large number ofsingle-side modules does not cause any significant degradation in the noise performance of the– 25 –

2014 JINST 9 P02003

RUN-CFG-2- A single side of each module tested individuallyEntries / 1 [mV/fC]

Gain [mV/fC]

100<µ > = 109.4300

σ = 1.5

200

50
100

0
0

200

400

600

800

1000

0
90

1200

100

110

Entries / 1 [mV]

Offset [mV]

60

130

300
<µ > = 34.6
σ = 1.8

200

40
100

20

0
0

200

400

600

800

1000

0
20

1200

30

40

Entries / 0.2 [mV]

Output noise [mV]30

20<µ > = 10.1
σ = 0.4

200

100

10

0
0

200

400

600

800

1000

0

1200

6

8

Entries / 8 [ENC(e)]Input noise [ENC(e)]

800

600

400

10

12

14

Output noise [mV]Channel number<µ > = 575

150

σ = 25

100

50

200

0
0

50

Offset [mV]Channel number

200

400

600

800

1000

1200

Channel number

0
400

500

600

700

800

Input noise [ENC(e)]Figure 24. From top to bottom: distribution of gain, threshold offset, output noise and input noise as
obtained from a Three-Point-Gain test for 0.5 fC, 0.75 fC and 1.0 fC input charges (see text for details). The
left plots show the distributions as a function of all 1280 channels within a single hybrid column (ten readout
ASICs). The right plots show the corresponding histograms. The mean hµi and sigma σ of a Guassian fit tothe histogrammed distributions are also shown. The silicon sensor was biased at 250 V.

– 26 –

2014 JINST 9 P02003

80

120

Gain [mV/fC]

Channel number

Input noise [ENC(e)]Input noise [ENC(e)]680

Slope = 1.37 [ENC(e) / degree]

660
640
620
600

680

640
620
600

580

580

560

560

540

540

520
20

Slope = 1.34 [ENC(e) / degree]

660

520
25

30

35

40

20

25

Hybrid temperature [C]

30

35

40

Hybrid temperature [C]

700
600

800
700
600

5000

100

5000

200
300
Bias voltage [V]

100

900
800
700
600

100

200
300
Bias voltage [V]

900
800
700

5000

700

100

200
300
Bias voltage [V]

700

100

200
300
Bias voltage [V]1000

Module 7
900
800
700

5000

800

5000

200
300
Bias voltage [V]

600

100

Module 4
900

600

1000

Module 6

600

5000

800

5000

200
300
Bias voltage [V]1000

Module 5900600

Input noise [ENC(e)]1000

Input noise [ENC(e)]Input noise [ENC(e)]

900

1000

Module 3

Input noise [ENC(e)]800

Module 2

Input noise [ENC(e)]

900

1000

Input noise [ENC(e)]1000

Module 1

Input noise [ENC(e)]Input noise [ENC(e)]1000

Module 8
900
800
700
600

100

200
300
Bias voltage [V]

5000

100

200
300
Bias voltage [V]Figure 26. Input noise as a function of bias voltage for all eight modules (top-side sensor). In each case, theaverage noise of the two hybrids of the module top-side is shown.

system, there is a clear interplay between top and bottom-sides of the SM-prototype that requires
further investigation.
4.5

Noise occupancy

The noise occupancy (NO) is defined as the probability for a strip to give a hit in a certain event only
due to noise. The NO is determined by performing a threshold scan without any input charge being
injected into the analog stage. The number of triggers sent is raised progressively with increasing
thresholds. Figure 28 shows a typical threshold scan obtained from a NO test.
Figure 29 shows for all eight modules the projection to the treshold axis of a treshold scanobtained from a NO test. The configurations RUN-CFG-1-top/bot and RUN-CFG-2 as describedin the previous section are compared. It is observed that in most cases there is not a significant
increase in the noise occupancy when enabling all 32 DC-DC power converters (RUN-CFG-2).
The threshold at which the hybrids are typically trimmed, and corresponding to 1 fC charge (this– 27 –

2014 JINST 9 P02003

Figure 25. Input noise as a function of hybrid temperature, for two different hybrids. In each case, theaverage noise of the two chip columns is shown.

140

Gain [mV / fC]

Gain [mV / fC]

140
RUN-CFG-0
RUN-CFG-1-top
RUN-CFG-2

120

RUN-CFG-0
RUN-CFG-1-bot
RUN-CFG-2

120

100

100

80

1

2

3

4

5

6

7

80

8

1

2

3

4

5

6

7

Input niose [ENC(e)]1000
RUN-CFG-0
RUN-CFG-1-top

900

RUN-CFG-2

800
700

8
Module1000

600

RUN-CFG-0
RUN-CFG-1-bot

900

RUN-CFG-2

800
700
600

500

1

2

3

4

5

6

7

500

8

1

2

3

4

Module5678Module1140 [Module 1, hybrid 1, column 0]
RUN-CFG-1-top, 16 DC-DCs enabled
120

0.9
0.8
0.7

100

Occupancy

Threshold [mV]Figure 27. Gain (top) and input noise (bottom) for all eight strip-modules. See table 4 for the different configurations being compared. The vertical error bar at each data point corresponds to the standard deviationof a Gaussian fit to the noise distribution for the two hybrids of a given sensor.

10

10-2

0.6
80

0.5

60

0.4

40

0.3

10

-3

10-4
10

-5

10

-6

0.2

20
0

1
-1

0.1
200

400

600

800

1000

1200

Channel number0

0 20 40 60 80 100120 140
Threshold [mV]Figure 28. Threshold scan from a Noise Occupacy test (left) and projection to the threshold axis (right) for
all channels of a column of ten chips of a given hybrid.

is the threshold at which unirradiated modules are expected to be operated in the future tracker),is ∼130–150 mV. The occupancies typically reach 10−8 around 100 mV (in the worst case scenario when all 32 DC-DC power converters converters are enabled). The bottom-side of module 7
shows a significant increase in the occupancy in RUN-CFG-2. Figure 30 shows the corresponding
threshold scan for ten chips of a hybrid located in that side. A large common-mode noise can beclearly observed, probably originated from the coupled effect of the top and bottom-side DC-DC
converters.

– 28 –

2014 JINST 9 P02003

Input niose [ENC(e)]ModuleRUN-CFG-2

10-2
-3

1

Module 2
RUN-CFG-1-top

10-1

RUN-CFG-2

10-2

1

Module 3
RUN-CFG-1-top

10-1

RUN-CFG-2

10-2

-3

-3

Occupancy

RUN-CFG-1-top

Occupancy

Module 1

Occupancy

Occupancy

1

10-1

1

10

10

10-4

10-4

10-4

10-4

10

-6

10-7

10

10

-6

10-7
-8

20

40

60

80 100 120 140

10 0Module 5
RUN-CFG-1-top
RUN-CFG-2

10-2

10

-5

10-7

10-7

-6

40

60

80 100 120 140

10 0

-8

20

40

60

1

Module 6
RUN-CFG-1-top

10-1

RUN-CFG-2

10-2

10 0

1

Module 7
RUN-CFG-1-top

10-1

RUN-CFG-2

-3

1

10-4

10-4

10-4

10-4

-6

10-7
-8

10 0

-5

10

10

-6

10-7
-8

20

40

60

80 100 120 140

10 0

-5

10

10

-6

10

40

60

80 100 120 140

10-7

10-7

10 0

RUN-CFG-1-top
RUN-CFG-2

-5
-6

-8

20

Threshold [mV]Module 8

-3

10

10

80 100 120 140

10-2

10

10

60

10-1

10

-5

40

Threshold [mV]

10

10

20

Threshold [mV]

10-2

-3

80 100 120 140

-8

20

40

60

Threshold [mV]

80 100 120 140

10 0

20

40

60

80 100 120 140

Threshold [mV]Threshold [mV]RUN-CFG-1-bot
RUN-CFG-2

10-2
-3

1

Module 2
RUN-CFG-1-bot

10-1

RUN-CFG-2

10-2

1

Module 3
RUN-CFG-1-bot

10-1

RUN-CFG-2

10-2

-3

-3

Occupancy

Module 1

Occupancy

110-1

Occupancy

Occupancy(a) Comparison of the NO as obtained with configurations RUN-CFG-1-top and RUN-CFG-2.

1

10

10

10-4

10-4

10-4

10-4

10

-6

10-7

10

10

-6

10-7
-8

20

40

60

80 100 120 140

10 0Module 5
RUN-CFG-1-bot
RUN-CFG-2

10-2
-3

-6

10

-5

10-7

10-7

-6

40

60

80 100 120 140

10 0

-8

20

40

60

Threshold [mV]Occupancy

Occupancy

1

10

10

-8

20

Threshold [mV]

10-1

-5

1

Module 6
RUN-CFG-1-bot

10-1

RUN-CFG-2

10-2

1

Module 7
RUN-CFG-1-bot

10-1

RUN-CFG-2

10-2

-3

80 100 120 140

10 0

-3

1

10-4

10-4

10-4

10-4

-6

10-7
-8

10 0

-5

10

10

-6

10-7
-8

20

40

60

80 100 120 140

10 0Threshold [mV]

-5

10

10

-6

10

40

60

80 100 120 140

10-7

10-7

10 0

Threshold [mV]RUN-CFG-1-bot
RUN-CFG-2

-5
-6

-8

20

Module 8

-3

10

10

80 100 120 140

10-2

10

10

60

10-1

10

-5

40

Threshold [mV]

10

10

20

Threshold [mV]Occupancy

-8

10 0

-5

Occupancy

10

RUN-CFG-2

-3

10

-5

RUN-CFG-1-bot

10-2

10

10

Module 4

10-1

-8

20

40

60

80 100 120 140

10 0

20

40

60

80 100 120 140

Threshold [mV]Threshold [mV](b) Comparison of the NO as obtained with configurations RUN-CFG-1-bot and RUN-CFG-2.

Figure 29. Noise occupancy for all eight double-sided strip-modules. See table 4 for the different configurations being compared. For each module, the average occupancy of the two same-side hybrids is shown.

4.6

Double-trigger noise

During the aforementioned Three-Point-Gain test (section 4.4), the input noise is accurately determined from calibration charges injected into the analog FE with the ABCN-25 internal calibration
circuit. The delay between the test charges and the clock is optimized to sample at the maximumof the signal. However, during real operating conditions of the tracker, the trigger is random andnoise pick-up can occur for closely spaced triggers. In the so-called Double-Trigger-Noise (DTN)
test, two triggers, separated by a specified number of clock periods are sent to the modules. The– 29 –

2014 JINST 9 P02003-3-6

Threshold [mV]Occupancy

Occupancy

1

10

10

-8

20

Threshold [mV]

10-1

-5

Occupancy

-8

10 0

-5

Occupancy

10

RUN-CFG-2

-3

10

-5

RUN-CFG-1-top

10-2

10

10

Module 4

10-1

0.8

1

10

-1

10-2

100
0.6
80
60

0.4

40
0.2

20
0

Occupancy

Threshold [mV]

1
140 [Module 7, hybrid 3, column 1](SM top and bottom-sides enabled)
120

200

400

600

800

1000

1200

-3

10-4
10

-5

10

-6

10-7
0 20 40 60 80 100120 140
Threshold [mV]Figure 30. Threshold scan from a Noise Occupacy test (left) and projection to the threshold axis (right) for
all channels of a column of ten chips of module 7, hybrid 3, column 0. During this test, all 32 DC-DC power
converters were enabled.

first event is rejected and the second is being readout. For a spacing close or equal to the pipeline
length, the second event records the occupancy of the module as the readout cycle of the first event
starts [31].
Figure 31 shows the results of a DTN test for three different thresholds corresponding to
1.0 fC, 0.75 fC and 0.50 fC charges. The spacing between the two triggers was varied from 120
to 150 clock periods, centered around the pipeline length. In each case, the total number of hits
recorded in the two hybrids of the corresponding module-side is shown. Ideally, as no charge is
injected the total number of hits should be zero for all thresholds. This is the case for almost all
modules for thresholds corresponding to 1 fC and 0.75 fC. However, for RUN-CFG-2 (32 DC-DC
converters enabled) and a threshold corresponding to 0.50 fC, a large increase in the number of hits
is observed, clearly indicating common-mode noise pick-up by the system. Figure 32 shows someparticular examples for modules 1 and 6. In the case of module 7, the same common-mode pick-up
as recorded during the NO test (see figure 30) was observed.

5

Prospects of a future module design

The results presented in the paper are from a module design based in the ABCN-25 readout ASIC.
The total radiation length of the current prototype is 2.44% X0 , with a total estimated weight of
58.7 g [6]. For a hybrid fully populated (including SMD components and ASICs), the calculated
radiation length is 0.33% X0 with a total estimated weight of 7.1 g. A stuffed-hybrid with SMD
components but without readout ASICs is estimated to weight 5.9 g. The measured weights ofhybrids and modules agree with the calculations within 1% and 3% respectively. The two microstrip sensors and the 80 ABCN-25 ASICs represent respectively 28% and 7% out of the total
module material budget. The four stuffed hybrids (without ASICs, including passive components
and the carbon-carbon bridges), correspond to 1.04% X0 , which is almost 43% of the total ofthe module. The TPG baseboard and the facings represent respectively 13% and 5% of the totalmaterial budget.
A new version of the ABCN chip, with 256 channels, has been submitted in 130 nm CMOS
technology (so-called ABCN-13). A new module design is already in progress, mainly focused on– 30 –

2014 JINST 9 P02003

Channel number

010Threshold corresponding to 1.0 fC input charge

Hits

Hits

2000

RUN-CFG-1-top

1500

2000

Threshold corresponding to 1.0 fC input charge

RUN-CFG-1-bot

1500

RUN-CFG-2

RUN-CFG-2

1000

1000

500

500

0

0
1

2

3

4

5

6

7

8

1

2

3

4

Threshold corresponding to 0.75 fC input charge

RUN-CFG-1-top

1500

2000

RUN-CFG-1-bot

1500

RUN-CFG-2

1000

1000

500

500

0

0
1

2

3

4

5

6

7

8

1

2

3

4

Module (SM top-side)
Threshold corresponding to 0.50 fC input charge

RUN-CFG-1-top

1500

5

6

7

8

Module (SM bottom-side)

Hits

Hits

8

Threshold corresponding to 0.75 fC input charge

RUN-CFG-2

2000

7

Module (SM bottom-side)

Hits

Hits

2000

6

2000

Threshold corresponding to 0.50 fC input charge

RUN-CFG-1-bot

1500

RUN-CFG-2

RUN-CFG-2

1000

1000

500

500

0

0
1

2

3

4

5

6

7

8

1

Module (SM top-side)

2

3

4

5

6

7

8

Module (SM bottom-side)

Figure 31. Results from the Double-Trigger-Noise test. Results for thresholds corresponding to 1.0 fC (top),
0.75 fC (middle) and 0.50 fC (bottom) charges are shown. In each plot, the y-axis shows the sum of hits
for the two-hybrids of the corresponding module-side. See table 4 for the different configurations being
compared. In the bottom-right plot, the results for modules 1 and 7 are out-of scale.

the hybrid layout adapted to the new readout electronics and including a single DC-DC powering
unit per module-side. The design evolution will continue to pursue a minimal material budget while
ensuring excellent thermal management and optimal electrical performance. Figure 33 shows the
future double-sided module design based in the ABCN-13 ASIC. Because of the increased number of channels in the chip, the hybrid witdth can be reduced by a factor of ∼ 2. If the hybrid
width is 12 mm wide, the weight of hybrid excluding electrical components is 1.9 g and 0.08% X0– 31 –

2014 JINST 9 P02003

Module (SM top-side)5

16[Module 1, hybrid 3, column 1]

145(SM bottom-side, RUN-CFG2)

14
12

140

Trigger delay

Trigger delay

150

18

150
[Module 6, hybrid 1, column 0]

145

16

(SM bottom-side, RUN-CFG1-bot)

14
12

140

10
135

8
6

130

10
135
8
130

6

4
125

4

125
2

120

200

400

600

800

2
120

200

400

600

800

1000
1200
Channel number

0

Figure 32. Particular examples from a DTN test for a threshold corresponding to 0.50 fC input charge. Twocolumns of ten chips of two different modules (module 1, hybrid 3, column 1, and module 6, hybrid 1,
column 0) are shown. The y and z axes show respectively the time spacing (in 25 ns units) between the two
triggers sent and the number of hits recorded from the second trigger. In the left-plot, a coherent commonmode noise is observed for all channels for a particular trigger spacing; in the right-plot, the noise pick-up
is concentrated in a particular readout chip (128 channels) for several different delays.

Figure 33. Module design concept with 256-channel ABCN-13 readout ASICs and shielded DC-DC power
unit (left) and integration and overlapping of 12 double sided module together with the service bus and the
SMC card at the two sides (right).

equivalent radiation length, normalized to the sensor area. The two per-module hybrids will have acommon electrical supply with a U-shape connection holding the DC-DC power unit, the latter being integrated close to the ASIC columns and to the module facings to optimize the heat-exchange
to the cooling plates. The interconnection of the module will be made with one pigtail per side thatwill directly connect to a service bus running along the Super-Module. As a consequence, the total
radiation length of the new module is expected to be ∼ 1.6% X0 or less. A new very compact andlow-mass service bus will be developed. The current design prospects foresees a significant width
reduction by implementing all electrical lines within 20 mm. A second-generation local support
structures will be fabricated, together with their services. The total radiation length of the new
local supports including the service bus would be ∼ 0.6% X0 or less.

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1000
1200
Channel number06Summary

Acknowledgments
This research was partly supported by the Grant-in-Aid for Scientific Research (A) (Grant
no. 20244038), Research (C) (Grant no. 20540291) and Research on Priority Area (Grant
no. 20025007), in Japan. We also acknowledge the financial support of the State Secretariat for
Education, Research and Innovation, the Swiss National Science Foundation and the Canton of
Geneva, Switzerland.

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UPGRADE-PUB-2012-004 (2012).

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2014 JINST 9 P02003

A super-module electrical prototype for eight double-sided silicon strip modules has been presented. Each silicon module is composed by two n-on-p silicon micro-strip sensors glued back-toback to a central baseboard and four bridged kapton-flex hybrids each with twenty 128 channels
ABCN-25 readout ASICs. The eight modules have been installed in an aluminimum support structure that includes a cooling circuit, two sets of multi-layer service buses, two SMB boards and 16
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2014 JINST 9 P02003[8] Hamamatsu Photonics, 325-6, Sunayama-cho, Hamamatsu City, Sizuoka Pref, 430-0193, Japan.

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