Sinusoidal 3-phase Brushless Motor Drivers
with Sensorless Vector Control

SX68200M Series

Data Sheet

Description

Package

The SX68200M series are 3-phase brushless motor
drivers in which output transistors, pre-drive circuits,bootstrap diodes with current-limiting resistors arehighly integrated. Employing a sinusoidal driving
strategy with a sensorless vector control, the SX68200M
series brings a small-sized, high-efficient, and low-noise
motor controlling into your application.
These products can run on a 3-shunt current detection
system and optimally control the inverter systems of
medium-capacity motors that require universal input
standards.

SOP36

Features● Pb-free (RoHS Compliant)● UL-recognized: UL 60730-1 File No.:E99992(SX68204M UL Recognition Pending)● Sinusoidal Current Waveform (Low Noise, High
Efficiency)
Sensorless Vector Control (High Efficiency at Load
Variation, Small Size)● Built-in Bootstrap Diodes with Current-limiting
Resistors● EEPROM as a Control Parameter Storage● Two Speed Control (PI Control) Modes:- Analog Voltage Control (VSP Pin)
- Serial Communications Control (I2C Compatible)● 3-shunt Current Detection● DIAG Pin Fault Signal Output● Protections Include:- V3 Pin Undervoltage Protection- Watchdog Timeout Detection- Memory Error Detection- Overvoltage Protection and Undervoltage Lockoutfor Main Power Supply (VM Pin)
- Soft Overcurrent Protection- Hard Overcurrent Protection- Thermal Warning- Thermal Shutdown- Undervoltage Lockout for Logic Supply- Loss-of-Synchronization Protection

Not to scale

Selection Guide
Part Number

VDSS

IO

SX68201M

250 V

2.0 A

SX68204M*

600 V

1.5 A

SX68205M
600 V* Under development

2.0 A

Applications
For motor drives such as:● Fan Motor for Air Conditioner● Fan Motor for Air Purifier and Electric Fan

Typical Application
VCC1

VCC

1

V3
36
RESETn
DIR

VDC

COM
V3

CB2

7

29

9

Controller

Gate Driver

27

CSCOM

CSW
CSV
CSU
VCC2

U
CB1

LS1
26
VB1
25

11

23
DIAG

CB3

VBB

10

CVPP
FG

V1

8

CV3
VPP

CDC

W1
34
VB3
33
VB2
32

3

31

SDA

VDC
CS

VSP
4
VM
5
TEST 6

SCL

VBB

2

V2

M

12
13

21

14

20

15
19

16

LS2
LS3

W2

17
18
RCS1

RCS2
RCS3

CCS3 CCS2 CCS1

SX68200M-DSE Rev.2.1
SANKEN ELECTRIC CO., LTD.
May 19, 2023
https://www.sanken-ele.co.jp/en© SANKEN ELECTRIC CO., LTD. 2019

RS3 RS2 RS1

1

SX68200M Series
Contents
Description ------------------------------------------------------------------------------------------------------ 1
Contents --------------------------------------------------------------------------------------------------------- 2
1. Absolute Maximum Ratings----------------------------------------------------------------------------- 4
2. Recommended Operating Conditions ----------------------------------------------------------------- 5
3. Electrical Characteristics -------------------------------------------------------------------------------- 6
3.1. Characteristics of Control Parts------------------------------------------------------------------ 6
3.2. Serial Communications ---------------------------------------------------------------------------- 8
3.3. Transistor Characteristics ------------------------------------------------------------------------- 9
3.3.1. SX68201M -------------------------------------------------------------------------------------- 9
3.3.2. SX68204M ------------------------------------------------------------------------------------ 10
3.3.3. SX68205M ------------------------------------------------------------------------------------ 10
3.4. Bootstrap Diode Characteristics --------------------------------------------------------------- 11
3.5. Thermal Resistance Characteristics ----------------------------------------------------------- 11
4. Mechanical Characteristics --------------------------------------------------------------------------- 11
5. Reference Register Value ------------------------------------------------------------------------------ 12
6. Block Diagram ------------------------------------------------------------------------------------------- 14
7. Pin Configuration Definitions------------------------------------------------------------------------- 15
8. Typical Application ------------------------------------------------------------------------------------- 16
9. Physical Dimensions ------------------------------------------------------------------------------------ 17
10. Marking Diagram --------------------------------------------------------------------------------------- 18
11. Functional Descriptions -------------------------------------------------------------------------------- 19
11.1. Basic Operation ------------------------------------------------------------------------------------ 19
11.2. Pin Descriptions ----------------------------------------------------------------------------------- 19
11.2.1. VCC1 and VCC2 ---------------------------------------------------------------------------- 19
11.2.2. RESETn --------------------------------------------------------------------------------------- 19
11.2.3. DIR --------------------------------------------------------------------------------------------- 19
11.2.4. VSP --------------------------------------------------------------------------------------------- 20
11.2.5. VM --------------------------------------------------------------------------------------------- 20
11.2.6. TEST ------------------------------------------------------------------------------------------- 20
11.2.7. SCL--------------------------------------------------------------------------------------------- 20
11.2.8. SDA -------------------------------------------------------------------------------------------- 21
11.2.9. COM ------------------------------------------------------------------------------------------- 21
11.2.10. V3 ----------------------------------------------------------------------------------------------- 21
11.2.11. VPP--------------------------------------------------------------------------------------------- 21
11.2.12. FG ---------------------------------------------------------------------------------------------- 21
11.2.13. DIAG------------------------------------------------------------------------------------------- 21
11.2.14. CSCOM --------------------------------------------------------------------------------------- 22
11.2.15. CSU, CSV, and CSW ----------------------------------------------------------------------- 22
11.2.16. VBB -------------------------------------------------------------------------------------------- 22
11.2.17. VB1, VB2, and VB3 ------------------------------------------------------------------------- 22
11.2.18. U, V1, V2, W1, and W2 -------------------------------------------------------------------- 22
11.2.19. LS1, LS2, and LS3 -------------------------------------------------------------------------- 22
11.3. Closed-loop Speed Control ---------------------------------------------------------------------- 23
11.4. Startup----------------------------------------------------------------------------------------------- 23
11.5. Windmilling ---------------------------------------------------------------------------------------- 24
11.6. Motor Control-------------------------------------------------------------------------------------- 24
11.7. Motor Speed Setting ------------------------------------------------------------------------------ 25
11.8. Low Power Consumption Mode ---------------------------------------------------------------- 26
11.9. PWM Control -------------------------------------------------------------------------------------- 26
11.10.Dead Time ------------------------------------------------------------------------------------------ 26

SX68200M-DSE Rev.2.1
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May 19, 2023
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SX68200M Series
11.11.PWM Switching Mode --------------------------------------------------------------------------- 26
11.12.Charging of Bootstrap Capacitors ------------------------------------------------------------- 27
11.13.Current Detection --------------------------------------------------------------------------------- 27
11.14.Diagnostic Function ------------------------------------------------------------------------------- 28
11.14.1. DIAG Pin Output --------------------------------------------------------------------------- 28
11.14.2. Diagnostic Register-------------------------------------------------------------------------- 28
11.14.3. Protective Operations at Fault Detection ----------------------------------------------- 28
11.14.4. Fault Mask Setting -------------------------------------------------------------------------- 29
11.15.Protection Functions ------------------------------------------------------------------------------ 29
11.15.1. V3 Pin Undervoltage Protection ---------------------------------------------------------- 29
11.15.2. Watchdog Timeout -------------------------------------------------------------------------- 29
11.15.3. Memory Error ------------------------------------------------------------------------------- 29
11.15.4. Overvoltage Protection and Undervoltage Lockout for Main Power Supply --- 30
11.15.5. Overcurrent Protections ------------------------------------------------------------------- 30
11.15.6. Soft Overcurrent Protection -------------------------------------------------------------- 30
11.15.7. Hard Overcurrent Protection ------------------------------------------------------------- 31
11.15.8. Thermal Warning and Thermal Shutdown -------------------------------------------- 31
11.15.9. Undervoltage Lockout for Logic Supply ------------------------------------------------ 31
11.15.10. Loss-of-Synchronization Protection------------------------------------------------- 32
11.16.Serial Communications -------------------------------------------------------------------------- 33
11.17.EEPROM ------------------------------------------------------------------------------------------- 36
11.17.1. Register Data Saving------------------------------------------------------------------------ 36
11.17.2. Locking by Password ----------------------------------------------------------------------- 36
11.18.Register Overview --------------------------------------------------------------------------------- 37
11.19.Register Map --------------------------------------------------------------------------------------- 38
11.20.Configuration Registers -------------------------------------------------------------------------- 39
11.20.1. System Configuration Registers ---------------------------------------------------------- 39
11.20.2. Startup Setting Registers ------------------------------------------------------------------ 42
11.20.3. Motor Control Setting Registers --------------------------------------------------------- 43
11.20.4. Speed Setting Registers--------------------------------------------------------------------- 48
11.20.5. Internal Control Setting Registers ------------------------------------------------------- 51
12. Design Notes ---------------------------------------------------------------------------------------------- 55
12.1. Notes on the Sequences for Turning On/Off the IC ---------------------------------------- 55
12.2. PCB Pattern Layout ------------------------------------------------------------------------------ 55
12.3. Considerations in IC Characteristics Measurement --------------------------------------- 55
13. Calculating Power Losses and Estimating Junction Temperature ---------------------------- 56
13.1. Power MOSFET Steady-state Loss, PRON ---------------------------------------------------- 56
13.2. Power MOSFET Switching Loss, PSW --------------------------------------------------------- 57
13.3. Body Diode Steady-state Loss, PSD ------------------------------------------------------------- 57
13.4. Estimating Junction Temperature of Power MOSFET------------------------------------ 57
14. Performance Curves ------------------------------------------------------------------------------------ 58
14.1. Transient Thermal Resistance Curves -------------------------------------------------------- 58
14.2. Allowable Effective Current Curves----------------------------------------------------------- 60
14.2.1. SX68201M ------------------------------------------------------------------------------------ 60
14.2.2. SX68204M ------------------------------------------------------------------------------------ 61
14.2.3. SX68205M ------------------------------------------------------------------------------------ 61
14.3. Performance Curves of Output Parts --------------------------------------------------------- 62
14.3.1. Output Transistor Performance Curves ------------------------------------------------ 62
14.3.2. Switching Loss Curves --------------------------------------------------------------------- 64
15. Pattern Layout Example ------------------------------------------------------------------------------- 66
16. Typical Motor Driver Application ------------------------------------------------------------------- 68
Important Notes ---------------------------------------------------------------------------------------------- 70

SX68200M-DSE Rev.2.1
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May 19, 2023
https://www.sanken-ele.co.jp/en© SANKEN ELECTRIC CO., LTD. 20193

SX68200M Series
1. Absolute Maximum Ratings
Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C.
Parameter
SymbolConditions
Rating
Unit
Remarks
Power MOSFET
Breakdown Voltage

VDSS
VCC

Logic Supply Voltage
VBS

Output Current(1)

IO

250

VCC = 15 V,
ID = 100 µA

600

VCC1–COM,
VCC2–COM
VB1–U,
VB2–V1,VB3–W1

V

20
V
20
1.5

TC = 25 °C,
TJ < 150 °C

2.0A

Logic Output Voltage

VO

VPP Pin Voltage

VPP

TC = 25 °C,
VCC = 15 V,
pulse width ≤ 100 µs,
duty cycle = 1%
DIR–COM,
SCL–COM,
SDA–COM
VSP–COM
FG–COM,
DIAG–COM
VPP–COMRESETn Pin Voltage

VRST

RESETn–COM−0.3 to 5.5

V

VM Pin Voltage

VVM−0.3 to 4

V

Input Pin Voltage for
Current-sensing
Operational Amplifier

VCSX

VM–COM
CSU–COM,
CSV–COM,
CSW–COM,
CSCOM–COM
TA = 25 °C; when
mounted on a board(2)−2 to 2V

3.5

W

Output Current (Pulse)

Logic Input Voltage

IOP

VIN(1)
VIN(2)

2.25
3

A−0.3 to 5.5

V−0.3 to 8.5

V−0.3 to V3 + 0.3

V−0.3 to 28

V

Allowable Power
Dissipation
Operating Case
Temperature(3)Junction Temperature(4)TC(OP)−25 to 100

°C

TJ

150

°C

Storage Temperature

TSTG−40 to 150°CPD

SX68201M
SX68204M
SX68205M

SX68204M
SX68201M
SX68205M
SX68204M
SX68201M
SX68205M(1)

Should be derated depending on an actual case temperature. See Section 14.2.
Refers to a 1.6 mm thick CEM3 glass with 35 μm thick copper foil; measured under natural air-cooling without
silicone potting.
(3)
Refers to a case temperature measured during IC operation.
(4)
Refers to the junction temperature of each chip built in the IC, including the control stage, gate drive stage, power
MOSFETs, and bootstrap diodes.
(2)

SX68200M-DSE Rev.2.1
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SX68200M Series
2.

Recommended Operating Conditions
Parameter

Main Supply Voltage

Symbol
VDC

Typ.

Max.

—

140

200

Unit
V

280

400

13.5

—

16.5

V

13.5

—

16.5

V

0

—

5.0

V

0

—

5.88

V

VPP

—

24

—

V

tPRS

50

—

—

ms

VM

0

—

1.8

V

1.5

—

—

μs

1

—

10

μF

IOP ≤ 3.0 A

0.22

—

—

IOP ≤ 2.25 A

0.29

—

—

IOP ≤ 3.0 A

0.22

—

—

Logic Supply Voltage
VBS

VIN(1)
VIN(2)EEPRM Write Supply
Voltage
Wait Time for
Programming Supply
Voltage Setup
VM Pin Input Voltage
Range for Main Supply
Dead Time of Input SignaltDEAD

Bootstrap Capacitor

CBOOT

Shunt Resistor*

VBB–COM

Min.
—

VCC

Input Voltage

Conditions

RSx

VCC1–COM,
VCC2–COM
VB1–U,
VB2–V1,VB3–W1
DIR–COM,
SCL–COM,
SDA–COM
VSP–COM

DT[5:0] = [011110]

Remarks
SX68201M
SX68204M
SX68205M

SX68201M
Ω

SX68204M
SX68205M* Refers to the reference values calculated with a minimum value of VTRIPH; should be a low-inductance resistor.

SX68200M-DSE Rev.2.1
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SX68200M Series
3.

Electrical Characteristics

Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C, VCC = 15 V.

3.1.

Characteristics of Control Parts
Parameter

SymbolConditions

Min.

Typ.

Max.

Unit

10.5

11.5

12.5

V

10.0

11.0

12.0

V

9.5

10.5

11.5

V

9.0

10.0

11.0

V

—

—

30

mA

—

—

150

μA

40

120

350

μA

3

3.3

3.7

V

Power Supply Operation
VCCx Pin Logic Operation Start
Voltage

VCC(ON)

VCCx Pin Logic Operation Stop
Voltage

VCC(OFF)VBx Pin Logic Operation Start
VoltageVBx Pin Logic Operation Stop
Voltage

VBS(ON)VBS(OFF)

VCCx Pin Logic Supply Current(in Operation)

ICC

VCCx Pin Logic Supply Current(in Low Power Consumption Mode)

ICCSTBY

VCC rising;
VCC1–COM,
VCC2–COM
VCC falling;
VCC1–COM,
VCC2–COM
VBS rising;
VB1–U, VB2–V1, VB3–W1
VBS falling;
VB1–U, VB2–V1, VB3–W1
VSP > VSSX with nooscillation; VCC1 = VCC2,
VCC pin current in 3-phase
operation
VSP < VVSSNVBS = 15 V, VSP = 5.4 V;
VBx pin current in 1-phase
operation
No loadVBx Pin Logic Supply Current

IBS

Regulator Output Voltage
Input Current for EEPROM Write
Supply Voltage
VM Pin Input Voltage Range

V3
IPP

—

7

—

mA

VM

0

—

1.8

V

VM Pin Input Current

IVM

0 < VM < 1.8 V

−2.5

—

2.5

µA

VSP Pin Input Current

IVSP

VSP = 5.5 V

10

—

45

µA

Input Signal
DIR Pin Low Level Input Voltage(1)

VIL1

—

—

0.76

V

(1)

VIH1

2.04

—

—

V

DIR Pin Internal Pull-down Resistor
RESETn Pin Low Level Input
Voltage(1)RESETn Pin High Level Input
Voltage(1)RESETn Pin Internal Pull-up
Resistor
FG Pin High Level Output Voltage

RPD

25

50

75

kΩ

VILR

—

—

0.3

V

VIHR

2.3

—

—

V

RPU

—

90

—

kΩ

V3

V

DIR Pin High Level Input Voltage

DIAG Pin Internal Pull-up Resistor
DIAG Pin, FG Pin Low Level Output
Voltage(1)

VOH

IOH = −1 mA

ROH
VOL1

IOH = 1 mA

V3 − 0.5 V3 − 0.2
—

10

—

kΩ

—

0.2

0.45

V

When applying an external voltage, be sure to set the DIR and RESETn pins to logic low during IC startup (i.e., until
the V3 pin voltage is established).

SX68200M-DSE Rev.2.1
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SX68200M Series
Parameter

SymbolConditions

Min.

Typ.

Max.

Unit

1.13

1.26

1.4

V

Motor Control
VSP Pin Startup Voltage

VSSX

VSP rising

Hold Time for Initial Positioning(2)

tHOLD

282

353

424

ms

Dead Time

DT

1.425

1.5

1.575

µs

ILIM

78

80

82

% IFS

Protection
Current Limiting Value(2)OCP Threshold Voltage(2)

VTRIPS

0.39

0.40

0.41

V

VM Pin OVP Threshold Voltage

(2)

VOVM

1.1

1.24

1.35

V

VM Pin UVP Threshold Voltage

(2)

VUVM

0.20

0.29

0.38

V

—

2.8

—

V

V3 Pin UVP Threshold Voltage

V3UV

V3 Pin UVP Hysteresis
HOCP Threshold Current

V3UVHYS

—

175

—

mV

(2)

IHOCP

130

150

165

% IFS

(2)

VTRIPH

650

750

825

mV

tHOCPF

0.75

1.00

1.25

µs

TDHD

120

130

—

°C

TDHYSD

—

40

—

°C

TWHC

125

135

—

°C

TWHYS

—

15

—

°C

TDHC

135

150

—

°C

TDHCHYS

—

35

—

°C

HOCP Threshold Voltage
HOCP Filtering Time

(2)

TSD Temperature (Gate-drive MIC)
TSD Hysteresis Temperature(Gate-drive MIC)
Thermal Warning Temperature(Control MIC)
Thermal Warning Temperature
Hysteresis (Control MIC)TSD Temperature (Control MIC)TSD Temperature Hysteresis(Control MIC)
(2)

V3 falling

Reference value

SX68200M-DSE Rev.2.1
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SX68200M Series
3.2.

Serial Communications
tSU:STA tHD:STA

tSU:DATtHD:DATtSU:STO

tBUF

SDA

SCL
tLOW

tHIGH

Figure 3-1. Serial Communications Timings

Parameter

Min.

Typ.

Max.

Unit

—

—

—

50

ns

SCL Pin Clock Frequency

fCLK

0

—

400

kHz

Falling Time of Output

tOF

—

—

250

ns

Stop-to-Start Bus-free Time

tBUF

1.3

—

—

Start Condition Hold TimetHD:STA

0.6

—

—

µs
µs

Start Condition Setting TimetSU:STA

0.6

—

—

µs

SCL Pin Low Level Time

tLOW

1.3

—

—

µs

SCL Pin High Level Time

tHIGH

0.6

—

—

µs

Data Setup TimetSU:DAT

100

—

—

ns

Data Hold TimetHD:DAT

0

—

900

ns

Stop Condition Setting TimetSU:STO

0.6

—

—

µs

SDA Pin Low Level Output Voltage

VOL

—

—

0.45

V

SDA Pin Output Leakage Current

IO

−2.5

—

2.5

µA

VIL

—

—

0.76

V

VIH

2.04

—

—

V

RPU_S

45

90

105

kΩ

Glitch Suppression Filter

Symbol(1)

SDA or SCL Pin Low Level Input
Voltage
SDA or SCL Pin High Level Input
Voltage (2)SCL Pin Input Pull-up Resistor(2)(1)(2)

Conditions

C = 400 pF,
Vpull-up = 3 V to 3.3 V

IOL = 3 mA
VO = 0 V to 5.5 V,
V3 = 0 V to 3.3 V

Refers to a pulse width for suppressing spike noise.
When applying an external voltage, be sure to set the SDA and SCL pins to logic low during IC startup (i.e., until theV3 pin voltage is established).

SX68200M-DSE Rev.2.1
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SX68200M Series
3.3.

Transistor Characteristics

Figure 3-2 provides the definitions of switching characteristics described in this and the following sections. VGS
represents the voltage between the gate and source of an internal power MOSFET.

VGS
0

trr

tf

tr

ID

90%
10%

0

VDS

0

Figure 3-2. Switching Characteristics Definitions

3.3.1. SX68201M
Parameter

SymbolDrain-to-Source Leakage Current

IDSS

Drain-to-Source On-resistanceSource-to-Drain Diode Forward
Voltage
High-side Switching
Source-to-Drain Diode Reverse
Recovery Time*
Rise Time*

Min.

Typ.

Max.

Unit

VDS = 250 V

—

—

100

μA

RDS(ON)

ID = 1 A

—

1.25

1.5

Ω

VSD

ISD = 1 A

—

1.1

1.5

V

trr

VDC = 150 V,
VCC = 15 V,
ID = 1.0 A, TJ = 25 °C,
inductive load

—

75

—

ns

—

45

—

ns

—

40

—

ns

VDC = 150 V,
VCC = 15 V,
ID = 1.0 A, TJ = 25 °C,
inductive load

—

70

—

ns

—

50

—

ns

—

20

—

ns

tr

Fall Time*tf

Low-side Switching
Source-to-Drain Diode Reverse
Recovery Time*
Rise Time*

trr

Fall Time*tftr

Conditions* Guaranteed by design.

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SX68200M Series
3.3.2. SX68204M
Parameter

SymbolDrain-to-Source Leakage Current

IDSS

Drain-to-Source On-resistanceSource-to-Drain Diode Forward
Voltage
High-side Switching
Source-to-Drain Diode Reverse
Recovery Time*
Rise Time*

Min.

Typ.

Max.

Unit

VDS = 600 V

—

—

100

μA

RDS(ON)

ID = 0.75 A

—

2.9

3.6

Ω

VSD

ISD = 0.75 A

—

0.95

1.5

V

trr

VDC = 300 V,
VCC = 15 V,
ID = 0.75 A, TJ = 25 °C,
inductive load

—

125

—

ns

—

60

—

ns

—

25

—

ns

—

130

—

ns

—

65

—

ns

—

30

—

ns

Min.

Typ.

Max.

Unit

tr

Conditions

Fall Time*tf

Low-side Switching
Source-to-Drain Diode Reverse
Recovery Time*
Rise Time*

trr

Fall Time*tf

VDC = 300 V,
VCC = 15 V,
ID = 0.75 A, TJ = 25 °C,
inductive load

Parameter

SymbolConditions

Drain-to-Source Leakage Current

IDSS

VDS = 600 V

—

—

100

μA

Drain-to-Source On-resistanceSource-to-Drain Diode Forward
Voltage
High-side Switching
Source-to-Drain Diode Reverse
Recovery Time*
Rise Time*

RDS(ON)

ID = 1 A

—

2.0

2.5

Ω

VSD

ISD = 1 A

—

1.1

1.6

V

trr

VDC = 300 V,
VCC = 15 V,
ID = 1.0 A, TJ = 25 °C,
inductive load

—

115

—

ns

—

50

—

ns

—

45

—

ns

VDC = 300 V,
VCC = 15 V,
ID = 1.0 A, TJ = 25 °C,
inductive load

—

115

—

ns

—

55

—

ns

—

40

—

ns

tr

3.3.3. SX68205M

tr

Fall Time*tf

Low-side Switching
Source-to-Drain Diode Reverse
Recovery Time*
Rise Time*

trr

Fall Time*

tf

tr

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SX68200M Series
3.4.

Bootstrap Diode Characteristics
Parameter

SymbolBootstrap Diode Forward Voltage

VFB

Bootstrap Diode Series Resistor

RBOOT

3.5.

(3)

Min.

Typ.

Max.

Unit

—

1.0

1.3

V

45

60

75

Ω

IFB = 0.15 A

Thermal Resistance Characteristics

Parameter
Junction-to-Case Thermal
Resistance(2)Junction-to-Ambient Thermal
Resistance(2)

Conditions

SymbolConditions

Min.

Typ.

Max.

Unit

RJ-C

All power MOSFETs
operating; when mounted
on a board(3)

—

—

10

°C/W

—

—

35

°C/W

RJ-A

Refers to a case temperature at the measurement point described in Figure 3-3.
Refers to a 1.6 mm thick CEM3 glass with 35 μm thick copper foil; measured under natural air cooling without
silicone potting.

9.6 mmMeasurement point

36

19

4 mm

1

18

Figure 3-3. Case Temperature Measurement Point

4.

Mechanical Characteristics
Parameter

Conditions

Package Weight

SX68200M-DSE Rev.2.1
SANKEN ELECTRIC CO., LTD.
May 19, 2023
https://www.sanken-ele.co.jp/en© SANKEN ELECTRIC CO., LTD. 2019

Min.

Typ.

Max.

Unit

—

1.4

—

g

11

SX68200M Series
5.

Reference Register Value

The table below lists the reference values to be written to the registers. All the values in parentheses are expressed inhexadecimal. The values listed in the table below are only the parameters that the GUI initially displays.

15

14

13

12

11

10

Config 0
Ref. Value (0047)

0

0

0

0

0

0

Config 1
Ref. Value (01E9)

0

0

0

0

0

0

Config 2
Ref. Value (0363)

0

0

0

0

0

0

0

0

0

0

0

0

Config 4
Ref. Value (0054)

0

0

0

0

0

0

Config 5
Ref. Value (0104)

0

0

0

0

0

0

Config 6
Ref. Value (0005)

0

0

0

0

0

0

Config 7
Ref. Value (00D5)

0

0

0

0

0

0

Config 8
Ref. Value (0106)

8

7

6

5

4

3

2

1

0

CR1

CR0

PR7

PR6

PR5

PR4

PR3

PR2

PR1

PR0

0

0

0

1

0

0

0

1

1

1

DT5

DT4

DT3

DT2

DT1

DT0

0

1

1

1

1

0

CMS1 CMS0 RSN1 RSN0 OCF1 OCF0

Config 3
Ref. Value (0160)

9

0

0

0

0

0

0

Ref. Value (00C6)

0

0

0

0

0

0

Ref. Value (00C6)

0

0

0

0

0

0

Config 11
Ref. Value (0000)

0

0

0

0

0

0

0

0

0

0

0

0

Config 13
Ref. Value (000D)

0

0

0

0

0

0

0

0

0

0

0

0

Config 15
Ref. Value (0209)

0

0

0

0

0

0

CD1

CD0

0

0

1

1

MO1

0

1

0

1

1

0

0

0

0

0

HT5

HT4

HT3

HT2

HT1

HT0

HD3

HD2

HD1

HD0

0

0

0

1

0

1

0

1

0

0

STS4

STS3

STS2

STS1

0

1

0

0

0

0

0

1

0

0

LS5

LS4

LS3

LS2

LS1

LS0

HS3

HS2

HS1

HS0

0

0

0

0

0

0

0

1

0

1

IM4

IM3

IM2

IM1

IM0

IO4

IO3

IO2

IO0

IO0

0

0

1

1

0

1

0

1

0

1

UVS

HR3

HR2

HR1

HR0

FGS

SI3

SI2

SI1

SI0

0

1

0

0

0

0

0

1

1

0

CP3

CP2

CP1

CP0

ETR

CI3

CI2

CI1

CI0

0

1

1

0

0

0

1

1

0

TP3

TP2

TP1

TP0

TI3

TI2

TI1

TI0

0

1

1

0

0

1

1

0

0

MO0 BCG2 BCG1 BCG0 IWM1 IWM0

IHO

STS0 STD4 STD3 STD2 STD1 STD0

0

0

0

0

0

0

0

0

0

0

0

LW9

LW8

LW7

LW6

LW5

LW4

LW3

LW2

LW1

LW0

0

0

1

1

0

0

1

0

0

0

FW5

FW4

FW3

FW2

FW1

FW0

0

0

0

0

0

0

1

1

0

1

DTC

VMC

DG3

DG2

DG1

DG0

DM3

DM2

DM1

DM0

0

1

0

0

0

0

0

0

0

0

PN3

PN2

PN1

PN0

SU3

SU2

SU1

SU0

0

0

0

0

1

0

0

1

1

0

SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
SRH9 SRH8 SRH7 SRH6 SRH5 SRH4 SRH3 SRH2 SRH1 SRH0
0

0

0

0

0

0

0

0

0

0

0

0

Config 17
Ref. Value (0000)

CD2

MO2

SCS

Config 16
Ref. Value (001E)

CD3

MO3

XWM1 XWM0 LHT1 LHT0

Config 14
Ref. Value (0100)

1

PWD9 PWD8 PWD7 PWD6 PWD5 PWD4 PWD3 PWD2 PWD1 PWD0

Config 12
Ref. Value (00C8)

00

Config 10

0

0

1

0

1

1

1

Config 91

OHT3 OHT2 OHT1 OHT0

0

0

0

0

0

1

1

1

1

0

SRL9 SRL8 SRL7 SRL6 SRL5 SRL4 SRL3 SRL2 SRL1 SRL0000

SX68200M-DSE Rev.2.1
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0

0

0

0

0

0

0

12

SX68200M Series
15

14

13

12

11

10

Config 18
Ref. Value (0366)

0

0

0

0

0

0

Config 19
Ref. Value (01B3)

0

0

0

0

0

0

Config 20
Ref. Value (015C)

0

0

0

0

0

0

Config 21
Ref. Value (00AE)
Register 28 Write
EEPROM Control
Register 28 Read
EEPROM Count
Register 29
Fault Mask
Ref. Value (0000)

9

8

7

6

5

4

3

2

1

0

VX9

VX8

VX7

VX6

VX5

VX4

VX3

VX2

VX1

VX0

1

1

0

1

1

0

0

1

1

0

VS9

VS8

VS7

VS6

VS5

VS4

VS3

VS2

VS1

VS0

0

1

1

0

1

1

0

0

1

1

VN9

VN8

VN7

VN6

VN5

VN4

VN3

VN2

VN10

VN0

0

1

0

1

0

1

1

1

0

0

VC9

VC8

VC7

VC6

VC5

VC4

VC3

VC2

VC11

VC0

0

0

0

0

0

0

0

0

1

0

1

0

1

1

1

0

0

0

0

0

0

0

SAV

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

NVC9 NVC8 NVC7 NVC6 NVC5 NVC4 NVC3 NVC2 NVC1 NVC0

0

0

0

0

0

0

TW

OT

LOS

PMF

HOC

0

0

0

0

0

Register 30 Write

OVM UVM
0

0

0

0

0

0

0

0

0

0

DIAG4 DIAG3 DIAG2

Ref. Value (0000)

0

0

0

0

0

0

0

0

0

0

0

Register 30 Read
Diagnostic

FF

POR

ME

WD

OC

EE

TW

OT

LOS

PMF

HOC

OVM UVM

RDG

PMR

STM

ESF

RSC

BRK

DIR

RUN

1

0

0

1

0

0

1

0

Register 31 Run

DIAG1 DIAG0

Ref. Value (0092)

0

0

0

0

0

0

Register Read

FF

POR

ME

WD

OC

EE

0

0

SX68200M-DSE Rev.2.1
SANKEN ELECTRIC CO., LTD.
May 19, 2023
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0

0

13

SX68200M Series
6.

Block Diagram
VCC2 18
VCC1 1
V3 10
VPP 11

25 VB1
32 VB2
33 VB3Controller
DIAG 13

Watchdog

TEST 6

DIR 3
RPD
FG 12
RESETn 2

V3
RPU

Gate Driver
NVM

Program
Supply36 VBBUVLO(VCC, 5 V)

MotionControl

High-side
Driver

HIN1
HIN2
HIN3

and
PWM

Start
Sequence

V3

and

RPU_S

CommandDecode29 VBB

LIN1
LIN2
LIN3

27 U
31 V1
34 W1
23 V2
19 W2

Low-side
Driver

MUX
VSP

UVLO
(VB)

3-phaseSine Generator

Data Buffer

SDA 8

VSP 4

VREG

Configuration
Registers

Vector
Motor
Controller

SCL 7

Logic
SupplyInput Logic

Diagnostics
andProtection

ADC

Control
Logic

TSD

26 LS121 LS220 LS315 CSW
16 CSVVM 5
COM 9

SX68200M-DSE Rev.2.1
SANKEN ELECTRIC CO., LTD.
May 19, 2023
https://www.sanken-ele.co.jp/en© SANKEN ELECTRIC CO., LTD. 201917 CSU
14 CSCOM

14

SX68200M Series
7.

Pin Configuration Definitions
Top View

1

VCC1

2

RESETn

3

DIR

W1

34

4

VSP

VB3

33

5

VM

VB2

32

6

TEST

V1

31

7

SCL

8

SDA

9

COM

10

V3

U

27

11

VPP

LS1

26

12

FG

VB1

25

13

DIAG

14

CSCOM

15

CSW

16

CSV

LS2

21

17

CSU

LS3

20

18

VCC2

W2

19

VBB

36
35

30

VBB

29
28

24

V2

23
22

Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Pin
Name
VCC1
RESETn
DIR
VSP
VM
TEST
SCL
SDA
COM
V3
VPP
FG
DIAG
CSCOM
CSW
CSV
CSU
VCC2
W2
LS3
LS2
—
V2
—
VB1
LS1
U
—
VBB
—
V1
VB2

33

VB3

34
35
36

W1
—
VBB

Description
Logic supply voltage input 1
Reset signal input
Motor direction setting signal input
Motor speed control signal input
Main supply voltage detection signal input
Test input
Serial clock input
Serial data input
Logic ground
Internal regulator ( i.e., V3 regulator) output
EEPROM write supply voltage input
Motor rotation pulse output
Fault signal output
Current detection reference voltage input
W-phase current detection signal input
V-phase current detection signal input
U-phase current detection signal input
Logic supply voltage input 2
W-phase output (connected to W1 externally)
W-phase low-side power MOSFET source
V-phase low-side power MOSFET source
Pin removed
V-phase output (connected to V1 externally)
Pin removed
U-phase high-side floating supply voltage input
U-phase low-side power MOSFET source
U-phase output
Pin removed
Positive DC bus supply voltage
Pin removed
V-phase output (connected to V2 externally)
V-phase high-side floating supply voltage input
W-phase high-side floating supply voltage
input
W-phase output (connected to W2 externally)
Pin removed
Positive DC bus supply voltage

SX68200M-DSE Rev.2.1
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May 19, 2023
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SX68200M Series
8.

Typical Application
VCC1

VCC

1

V3
36
RESETn
DIR

VDC

2

CS

CB2

31

SDA

COM
V3

7

29

9

Controller

Gate Driver

27

CSCOM

CSW
CSV
CSU
VCC2

CB3

VBB

U
CB1

LS1
26
VB1
25

11

23
DIAG

V1

10

CVPP
FG

CDC

8

CV3
VPP

VDC

W1
34
VB3
33
VB2
32

3

VSP
4
VM
5
TEST 6

SCL

VBB

V2

M

12
13

21

14

20

15
19

16

LS2
LS3

W2

17
18
RCS1

RCS2
RCS3

CCS3 CCS2 CCS1

RS3 RS2 RS1Figure 8-1. Typical Application

SX68200M-DSE Rev.2.1
SANKEN ELECTRIC CO., LTD.
May 19, 2023
https://www.sanken-ele.co.jp/en© SANKEN ELECTRIC CO., LTD. 201916

SX68200M Series
9.

Physical Dimensions● SOP36 Package
22 ±0.2(Includes mold flash)
+0.15

1

18

P=1.2 ±0.2A

2.1 ±0.2

1.05 ±0.2

14.1 ±0.3

1911.4 ±0.2

36(Excludes mold flash)0.25 -0.05+0.15
0.4 -0.05

0 to 0.2

+4°

6°-6°

0.7 ±0.3(R-end)0.8 ±0.2(From backside to root of pin)

Enlarged view of A (S = 20/1)
NOTES:● Dimensions in millimeters● Pb-free (RoHS compliant)● When soldering the products, it is required to minimize the working time within the following limits:
Reflow (MSL3):
Preheating: 180 °C / 90 ± 30 s
Solder heating: 250 °C / 10 ± 1 s (260 °C peak, 2 times)
Soldering iron: 380 ± 10 °C / 3.5 ± 0.5 s, 1 time

SX68200M-DSE Rev.2.1
SANKEN ELECTRIC CO., LTD.
May 19, 2023
https://www.sanken-ele.co.jp/en© SANKEN ELECTRIC CO., LTD. 201917

SX68200M Series● Land Pattern Example

Unit: mm

10. Marking Diagram36

19

SX 68 20 x M

Part Number
Quality Approval MarkYM DD XX1

18

Pin 1 Indicator

Lot Number:
Y is the last digit of the year of manufacture (0 to 9)
M is the month of the year (1 to 9, O, N, or D)
DD is the day of the month (01 to 31)
XX is the control number

SX68200M-DSE Rev.2.1
SANKEN ELECTRIC CO., LTD.
May 19, 2023
https://www.sanken-ele.co.jp/en© SANKEN ELECTRIC CO., LTD. 201918

SX68200M Series
11. Functional Descriptions
Unless specifically noted, this section uses thefollowing definitions:● All the characteristic values given in this section are
typical values.
● For pin and peripheral component descriptions, thissection employs a notation system that denotes a pin
name with the arbitrary letter “x”, depending oncontext. Thus, “the VCCx pin” is used when referring
to either or both of the VCC1 and VCC2 pins.

bootstrap capacitors. In addition, the VCCx pin voltage
is internally stepped down (i.e., V3 regulator) to be used
as a logic power supply. A 26 V Zener diode isinternally connected between the VCCx and COM pins.
The VCC1 and VCC2 pins must be externallyconnected on a PCB because they are not internallyconnected. To prevent malfunction induced by supply
ripples or other factors, put a capacitor of about 0.01 μF
to 0.22 μF, CVCC, near these pins. Voltages to be applied
between the VCCx and COM pins should be about 15 V.

11.2.2. RESETn
11.1.

Basic Operation

The IC is a 3-phase brushless motor driver operated
with sinusoidal current waveforms, where the rotor
position is estimated by a sensorless vector control
strategy. The rotor positioning system is based on
calculations from the voltages applied to the 3-phasemotor and the currents through each phase, thus
requiring no external position sensor. The internal power
MOSFETs consisting of 3-phase bridges supply thecurrents to the motor. The serial communications featureprovides reliable access to the extensive collection ofsettings pertaining to control systems and diagnostic
features. The IC integrates a non-volatile memory(EEPROM), which stores register data, to operate
independently of external communications.
The IC has the motor speed control system whosereference speed settings are programmable through theserial communications or by an analog voltage input. In
an overcurrent condition, the IC puts a certain limit on
the motor current level with its protection function.
The startup operation uses the parameters settable via
the serial communications, thus permitting the IC tosupport a wide range of the combinations of motors andloads. Moreover, the built-in watchdog timer allows the
IC to stop the present motor run as the protection against
chip-level damage, e.g., a control part in a freeze state.
The fault detection and diagnosis on operational faults
such as the VCCx or V3 pin undervoltage protection,
thermal shutdown, and so on are carried out based on thedetailed diagnostic information accessible through theserial communications. The DIAG pin operates as thefault signal output, whose settings are also
programmable by the diagnostic register.
For thorough functional descriptions, see thefollowing sections.

This pin operates to reset the diagnostic register.
When the RESETn pin becomes logic low, the motor
operation stops, and the diagnostic register is cleared.
Then, the DIAG pin is reset to logic high.
The RESETn pin is internally pulled up to the V3
regulator by the resistor. The RESETn pin should benormally left open.
If any noise-induced malfunction occurs, add RRST
and CRST as shown in Figure 11-1. When turning on theIC, be sure to check that the RESETn pin is held at logic
low. In particular, when applying an external voltage on
the RESETn pin, be sure to set the RESETn pin to logic
low until the V3 pin voltage is established.
V3
RRST

10
88 kΩ

RESETn

2 kΩ

2
6V

CRST

6V

COM
9

Figure 11-1. Internal Circuit Diagram of RESETn Pin

11.2.3. DIRThis is the signal input pin to switch the direction of
motor rotation. The motor direction is determined by the
logical EXOR (exclusive OR) of the DIR bit in theinternal register and the DIR logic input, as in Table
11-1.
Table 11-1. Logic Levels Defined for Motor Direction

11.2.

Pin Descriptions

11.2.1. VCC1 and VCC2
These are the logic supply pins for the built-in control
ICs. The VCCx pin voltage is used for charging

DIR Bit00
1
1

SX68200M-DSE Rev.2.1
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May 19, 2023
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DIR Pin
L
H
L
H

Motor Direction
Forward
Reverse
ReverseForward

19

SX68200M Series
The DIR pin is internally pulled down to the COM pinwith the internal resistor. To set the DIR pin to logic low,normally leave the pin open. If any noise-induced
malfunction occurs, connect the DIR pin to the COM pin.
To set the DIR pin to logic high, pull up the pin to theV3 pin with RDIR, as shown in Figure 11-2. If any noiseinduced malfunction occurs, add CDIR between the DIR
and COM pins.
When turning on the IC, be sure to check that the DIR
pin is held at logic low. In particular, when applying an
external voltage on the DIR pin, be sure to set the DIR
pin to logic low until the V3 pin voltage is established.
Note that the motor operation must be stopped forswitching the logic level of input signals to the DIR pin.
V3
RDIR

Analogmultiplexer

50 kΩ

VM 5
6V

COM

6V

9

Figure 11-4. Internal Circuit Diagram of VM Pin

10

DIR

as the absolute maximum rating (−0.3 V to 4 V). The
VM pin also has the overvoltage protection and theundervoltage lockout. For more details, see Section
11.15.4.

2 kΩ

3

11.2.6. TEST
6V

CDIR

48 kΩ

6V

COM
9

Figure 11-2. Internal Circuit Diagram of DIR Pin

This is the input pin designed for test use only, not for
motor control. When using the TEST pin in yourapplication, leave the pin open or connect a resistor of
about 10 kΩ between the pin and the ground (COM).
If you have any questions about using the TEST pin,please contact our sales representative or distributor.

11.2.4. VSP

11.2.7. SCLThis is the input pin of reference voltage to set the
speed of motor rotation. Figure 11-3 shows an internal
circuit diagram of the VSP pin.
The reference voltage is input between the VSP and
COM pins. When the VSP pin is held at logic low for acertain period of time, the IC enters the low power
consumption mode.

This pin operates as the clock input pin for the serial
communications. Figure 11-5 is an internal circuit
diagram describing the SCL pin.
While the serial communications are being performed,
the power supply (3.3 V to 5.0 V) of the master device
must be used. Care must be taken in supplying power tothe subordinate and master devices. Be sure to turn on
the IC (subordinate) first, and then turn on the masterdevice. The SCL pin should be normally left open.
If any noise-induced malfunction occurs, add RSCL
and CSCL as shown in Figure 11-5.
When turning on the IC, be sure to check that the SCL
pin is held at logic low.

Analogmultiplexer

120 kΩ

VSP 4
9V

50 kΩ

6V

V3
COM

9

10
88 kΩ

RSCL

SCL

2 kΩ

7

Figure 11-3. Internal Circuit Diagram of VSP Pin

6V

CSCL

11.2.5. VM
This pin monitors the motor driving voltage, VDC. VDC
divided by a resistive voltage divider is applied to theVM pin. Figure 11-4 illustrates an internal circuit
diagram of the VM pin.
The resistor should be set within the range specified

6V

COM
9

Figure 11-5. Internal Circuit Diagram of SCL Pin

SX68200M-DSE Rev.2.1
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May 19, 2023
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SX68200M Series
11.2.8. SDA

11.2.11. VPP

This is the data input/output pin for the serial
communications. Figure 11-6 is an internal circuit
diagram describing the SDA pin.
While the serial communications are being performed,
the power supply (3.3 V to 5.0 V) of the master device
must be used. Care must be taken in supplying power tothe subordinate and master devices. Be sure to turn on
the IC (subordinate) first, and then turn on the masterdevice. When turning on the IC, be sure to check that the
SDA pin is held at logic low.
The SDA pin should be normally left open. If any
noise-induced malfunction occurs, connect a resistor of
about 10 kΩ between the SDA and COM pins.

This pin is the input of the programming voltage
supply. Writing to the EEPROM requires a
programming voltage; therefore, connect a capacitor,
CVPP, of about 0.1 µF and apply a voltage of 24 V to it.
The IC uses the VPP pin voltage smoothed by theinternal regulator. A 30 V Zener diode is internallyconnected to the VPP pin. When not using the VPP pin,connect the pin to the VCCx or COM pin (no CVPP
required).

V3

SDA

2 kΩ

8
75 Ω
6V

11.2.12. FG
While internal signals of the IC and the motor rotationsynchronizes, the FG pin outputs pulses proportionallyto a preset motor electrical cycle frequency. The pulse
frequency of the FG pin output is set ×1 or ×3 of the
motor electrical cycle frequency by the FGS bit in theconfiguration register 8 (Config 8). Figure 11-8 shows
an internal circuit diagram of the FG pin

6V

V3

COM 9
25 Ω

Figure 11-6. Internal Circuit Diagram of SDA Pin

FG

12
6V

COM

11.2.9. COM
This is the logic ground pin for the built-in control ICs.
Varying electric potential of the logic ground can be acause of improper operations. Therefore, connect thelogic ground as close and short as possible to shunt
resistors, RSx, at a single-point ground (or star ground)which is separated from the power ground (see Figure11-7).
U1

VBB 29VDC
CS

LS1 26LS2 219 COM

LS3 20RS19Figure 11-8. Internal Circuit Diagram of FG Pin

11.2.13. DIAG
The DIAG pin outputs fault signals. Figure 11-9 is aninternal circuit diagram illustrating the DIAG pin.
For more details, see Section 11.14.1.

CDC

Analogmultiplexer

RS2

V3

RS3

Create a single-point
ground (a star ground) near
RSx, but keep it separated
from the power ground.

Figure 11-7. Connections to Logic Ground11.2.10. V3

2 kΩ

26 Ω

DIAG 13

10 kΩ

6V

COM

9

Figure 11-9. Internal Circuit Diagram of DIAG Pin

This pin is the output of the 3.3 V internal regulator.
A 6 V Zener diode is internally connected to the V3 pin.
Connect a capacitor of about 1.0 μF (≥0.47 μF) between
the V3 and COM pins.

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SX68200M Series
11.2.14. CSCOM

11.2.17. VB1, VB2, and VB3

This pin serves as the reference input for current
detection. Connect the CSCOM pin as close as possible
to shunt resistors, RSx, whose traces are separated fromthe common ground.

The VB1, VB2, and VB3 pins are connected tobootstrap capacitors, CBx, for the high-side floating
supply. For proper startup, turn on the low-side
transistors first, then fully charge the bootstrap
capacitors, CBx. Section 11.4 describes the startup
sequences of the IC in detail; Section 11.12 explains theprocedures to charge the bootstrap capacitors.
CBx of about 1 μF must be placed near the IC, andconnected between the VBx and output (U, V1, W1)
pins with a minimal length of traces.

U1
17 CSU
16 CSV
15 CSW
14 CSCOMVDC

VBB 29CS
LS1 26RS2

LS2 219 COM

RS3

LS3 20

RCS3
RCS2

Create a single-point
Ground (a star ground)near R Sx, but keep it
separated from thecommon ground.

RCS1

CCS1 CCS2CCS3

Figure 11-10.

CDC

RS1

Connections to CSCOM Pin

11.2.15. CSU, CSV, and CSWThis is the input pin of current detection signals.
Figure 11-11 illustrates an internal circuit diagram of the
CSx and CSCOM pins.
The CSU, CSV, and CSW pins are, directly but
separately, connected to each current detection resistorof the U-, V-, and W-phases. To eliminate signal ringing
which may be induced by parasitic capacitance and theimpedance in the detection resistors, add an RC low passfilter (i.e., RCSx and CCSx in Figure 11-10) as needed.
4 kΩ

CSx

4 kΩ

CSCOM 14
6V

6V

6V

COM

9

Figure 11-11.

Internal Circuit of CSx and CSCOM
Pins

11.2.18. U, V1, V2, W1, and W2
These pins are the outputs of the three phases, andserve as the connection terminals to the 3-phase motor.
The V1 and W1 pins must be connected to the V2 andW2 pins on a PCB, respectively. The U, V, and W1 pins
are the grounds for the VB1, VB2, and VB3 pins. The U,
V1, and W1 pins are connected to the negative nodes ofbootstrap capacitors, CBx. Since high voltages areapplied to these output pins (U, V1, V2, W1, W2), it isrequired to take measures for insulating as follows:● Keep enough distance between the output pins andlow-voltage traces.
● Coat the output pins with insulating resin.

11.2.19. LS1, LS2, and LS3
The LS1, LS2, and LS3 pins are internally connectedto the low-side power MOSFET sources of the U-, V-,
and W-phases, respectively. For current detection, theLSx pin should be externally connected to shunt
resistors, RSx. When connecting a shunt resistor, use a
resistor with low inductance (required), and place it asnear as possible to the IC with a minimum length oftraces to the LSx and COM pins. Otherwise, malfunction
may occur because a longer circuit trace increases its
inductance and thus increases its susceptibility to
improper operations. In applications where long PCB
traces are required, add a fast recovery diode, DRSx,
between the LSx and COM pins in order to prevent the
IC from malfunctioning (see Figure 11-12).

11.2.16. VBB

VDC

VBB 29CS

This is the input pin for the main supply voltage, i.e.,
the positive DC bus. All of the power MOSFET drainsof the high-side are connected to this pin. Voltages
between the VBB pin and the ground (COM) should be
set within the recommended range of the main supply
voltage, VDC, given in Section 2.
To suppress surge voltages, put a 0.01 μF to 0.1 μF
bypass capacitor, CS, near the VBB pin and anelectrolytic capacitor, CDC, with a minimal length of
PCB traces to the VBB pin.

U1

DRS1

LS1 26DRS2

LS2 21
9 COM

CDC
RS1

DRS3 RS2

LS3 20
RS3

Put a shunt resistor near
the IC with a minimum
length to the LSx pin.

Add a fast recovery
diode to a long trace.

Figure 11-12.

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Connections to LSx Pin

22

SX68200M Series
11.3.

Closed-loop Speed Control

In addition to the vector control system, which is acore element in the control systems, the IC also
incorporates a closed-loop speed control. The closedloop speed control uses a preset reference speed as atarget motor speed, determined by a frequency of the 3phase waveforms (an electrical angle of 360°). The
reference speed, fREF, is input by either of the following
two methods (for the motor speed setting, see Section
11.7):● Directly inputting the relevant parameter via the serial
communications● Inputting the linear voltage that is proportional to themotor speed into the VSP pin
The reference speed, fREF, and the feedback speed,
fFBK, are compared inside the IC to obtain a speed
difference, fERR. fERR is then fed into the integrating
controller to calculate a reference driving torque used foraccelerating or decelerating the motor.
The following bits are for setting the speed control
method, reference speed range, and the reference speed,
respectively:● Config 15
SCS
Speed control method selection
SU[3:0] Speed range multiplier● Config 16
SR[9:0] Reference motor speed
The integral gain, KI, used for the speed control is canbe adjusted to yield optimum performance by using the
SI variable. The rotational inertia of motor load shaft
and the desired mechanical response speed determine
the SI variable. The following bit is for the SI variablesetting:● Config 8
SI[3:0] Integral gain constant, KI, for speed control

11.4.

Startup

For proper startup, apply voltages to the main power
supply of the motor, the VCC pin, and the VSP pin, inthat order. The motor starts to operate with the startup
sequence (defined below) depending on the VSP pin
voltage levels.
Figure 11-13 explains the startup sequence; Table
11-2 provides the operation modes definitions.
The IC has two startup modes: the DC alignment startmode and the ramp-up start mode. The STM bit in the
Run register (Register 31) selects which mode to beenabled. Note that the motor may still be coasting or
may be forced to rotate by the operation of a motor load
before the startup. Therefore, either of the two startup
modes requires the motor to be as stationary as possible
in its very first stage. To apply a braking force to thestop the motor, the IC increases the duty cycle of apredetermined PWM period and turns on all the low-side
power MOSFETs. During this braking operation, the IC
monitors and limits the currents through the motor. The
braking force maximizes at the duty cycle increased up
to 100%. When the current detected reaches zero, thebraking operation completes. The operations after thebraking operation are as follows:● DC Alignment Start Mode
As soon as the braking period ends, the direct currentof a preset value flows through the motor coil for apredefined hold time. The direct current increases fromzero to a maximum value (i.e., the hold current) andremains in this condition for the hold time. This allows
the rotor to be aligned to an initial position. In the DCalignment start mode, the hold time and hold current
must be large enough to align the rotor to the initial
position.
After the hold time ends, the motor rotates at aconstant speed which is controlled with a PWM duty
cycle generated by the closed-loop speed control system.
The initial value of the PWM duty cycle must be set togenerate an average voltage equal to the BEMF
amplitude at the startup speed.
● Ramp-up Start Mode
The ramp-up start mode operation follows the braking
period. During the period internally set to about 5
seconds, the excitation switching speed of phase currents
gradually increases from 25% to 100% of the start speed(this is defined as a ramp-up period). During the rampup period, the rotor position is controlled without
feedback. When the excitation switching speed reaches
the maximum startup speed, the IC estimates a rotor
position by its internal circuits.
After the ramp-up period ends, the motor rotates at aconstant speed which is controlled with a PWM duty
cycle generated by the closed-loop speed control system.
In the ramp-up start mode, the startup speed mainly
depends on the rotational inertia and load of the motor.
The ramp-up current generates a rotating force, whichmust be large enough to overcome static friction androtate the rotor at the startup speed.
The startup parameters are also programmable via theserial communications. The user-settable bits in theconfiguration registers are as follows:● Register 31 (Run)STM
Startup mode selection● Config 8
HR[3:0] Startup ramp-up period● Conig 4
HT[5:0] Startup hold timeHD[3:0] Startup hold current● Config 5
STS[4:0] Startup speed
STD[4:0] Startup duty cycle/ramp-up current

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SX68200M Series
To turn off the IC, be sure to decrease the VSP pin
voltage first.
VCC Pin
Voltage VCC(ON)0tUC_BRAKEVSP Pin
VoltageRun

VSSTUC-Brk

VSSX
Low power
consmp.
0

V3 PinVoltage0

Operation
Mode

Low power
consmp.

All
off

BT- WMChg Brk

Startuphold

Startupdrive

increase in the duty cycle. The low-side duty cycle
increases up to the level where the current reaches alimiting value. The IWM[1:0] bits in the configuration
register 3 (Config 3) are for setting a limiting value ofthe windmill braking current.
The motor BEMF lowers with a decrease in the motor
speed induced by the windmill braking current.
Eventually, the motor BEMF becomes too low tomaintain the windmill braking current even with the
low-side power MOSFETs at a 100% duty cycle, andthen the windmill braking current decreases. The motor
is considered to be stopped as the windmill braking
current falls below its minimum threshold. The
XWM[1:0] bits in the configuration register 13 (Config
13) are for setting the minimum threshold of thewindmill braking current.
After the motor stops, the IC starts the startup
sequence.

Run

11.6.
Figure 11-13.

Startup Sequence

Table 11-2. Operation Modes in Startup Sequence
OperationMode

Description

The braking operation when the VSP
pin voltage is set within the UC-Brk
UC-Brk*voltage range(UC-Brk: User Commanded Brake)
ALL OFF
Initializing
Charging the bootstrap capacitors
BT-Chg(BT-Chg: Bootstrap Charge)
The braking operation prior to
WM-Brkexcitation start(WM-Brk: Windmill Brake)
Startup hold
Aligning the rotor to initial position
Startup drive
Rotating (without feedback)
RUN
Rotating* At startup, the VSP pin voltage crosses over thevoltage range specified for the UC-Brk operation.
However, when tUC_BRAKE is shorter than about 200 ms,
the UC-Brk operation is skipped.

11.5.

Windmilling

In the application where a BLDC motor drives a fan,the startup failure may occur if a motor shaft rotates
before the IC attempts the startup sequence. To avoid
such failure, the IC performs the braking operation(WM-Brk) prior to the startup sequence to bring the
motor to a standstill.
When the WM-Brk operation starts, the duty cycle ofthe low-side power MOSFETs will gradually increase.
The windmill braking current gradually rises with anMotor Control

The motor running state is controlled by a
combination of the register bits set via the serial
communications. The Run register (Register 31)
contains the following four bits to control motor
operations: RUN, DIR, BRK, and RCS.
● Motor Start/Stop
The RUN bit receives the signals that start and stop a
motor run. When RUN = 1, the IC enters an operatingstate and starts a motor run or the startup sequence.
When RUN = 0, the IC turns off the power MOSFETs of
the three phases and allows the motor to coast (i.e., coastmode). This state overrides all other control inputs;
therefore, neither the motor run nor the startup sequence
takes place.
● Motor Direction
Table 11-3 is the logical EXOR (exclusive OR) truth
table defining the DIR bit statuses and the logic input
levels of the DIR pin, which determine the direction of
motor rotation. In a forward rotation, 3-phase currents IU,
IV, and IW are 120° ahead of the currents IV, IW, and IU,
respectively. In a reverse rotation, 3-phase currents IU, IV,
and IW are 120° behind the currents IV, IW, and IU,
respectively.
Table 11-3. Motor Direction Definitions
DIR Bit00
1
1

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DIR Pin
L
H
L
H

Motor Direction
Forward
Reverse
ReverseForward24

SX68200M Series● Motor Speed
The voltage applied to the VSP pin is used for the
motor speed setting (see Section 11.7). The motor speed
can be determined by monitoring the FG pin output.
While the IC drives under the sensorless control system,
the FG pin outputs pulses at a frequency proportional tothe motor speed.
● Loss of Synchronization
While the motor is in a running state, the IC monitorsa loss-of-synchronization (LOS) condition. Upon LOS
detection, the LOS bit in the diagnostic register is set to“1”. When the motor is not in the running state or whenin the braking state, the LOS bit is set to “0”.

11.7.

Motor Speed Setting

The IC controls the speed of motor rotation with thebuilt-in closed-loop speed control circuit. To enable a
motor run, set BRK = 0 and RUN = 1. The SCS bit in
the configuration register 15 (Config 15) selects either ofthe following speed control methods:● SCS = 1
Controlled by the internal register settings (directly
input the SR parameter via the serial communications)● SCS = 0
Controlled by externally inputting the linear voltage
proportional to the motor speed into the VSP pin(external mode)
When SCS = 1, the parameter is directly input via theserial communications. The IC then ignores the VSP pin
input but only uses the value input to the SR[9:0] bits inthe configuration register 16 (Config 16). The SR[9:0]bits are for setting the frequency of motor excitation.
When SCS = 0, the IC uses the value of the voltage
applied to the VSP pin as a default value. Figure 11-14
shows a relation between the reference motor speed andthe VSP pin input voltage. The relation between the VSP
pin voltage and the motor speed is defined by the six
variable parameters (listed in Table 11-4) and aninternally fixed voltage, VSSX.
VSSX represents the releasing voltage of the low power
consumption mode, i.e., a voltage of an internally preset
value.
fRH

Reference Speed, fREF

● Braking Operation
The BRK bit controls the braking operation, which
decelerates the speed of motor rotation to stop the motor
run. The braking operation is enabled only when
RUN = 1. During the braking operation, all the low-side
power MOSFETs turn on to short the motor windings.
The rotation-induced BEMF causes currents to flow
through the motor winding of each phase. And thisgenerates a braking torque. The braking torque always
opposes the motor direction. Strength of the braking
torque varies according to the motor parameters. Notethat the current control is not available during thebraking operation due to no excitation exerted on the
motor. Be sure to maintain the braking current not toexceed the rating of the low-side power MOSFETs.

UC-BrkLow power consmp.

fRL
0

VSSN

VSSX

VSMN VSSTVSMX

VSP Pin Input Voltage, VSP

Figure 11-14.

Reference Speed, fREF vs. VSP Pin Input
Voltage, VSP

Table 11-4. VSP Input Register
Variable

Symbol

VX[9:0]

VSMX

VN[9:0]VSMN

VS[9:0]VSST

VC[9:0]VSSN

SRH[9:0]

fRH

Description
VSP pin voltage at maximum
speed
VSP pin voltage at minimum
speed
Excitation start voltage
Low power consumption modetransition voltage
Maximum reference speed

SRL[9:0]fRL

Minimum reference speed

When the VSP pin input voltage, VSP, reaches zero,
the IC turns off the power MOSFETs of the three phases
and allows the motor to coast. Then, the IC enters thelow power consumption mode (see Section 11.8). When
VSP ≤ VSSX, the IC stays in the low power consumption
mode. When VSP > VSSX, the IC is initialized and goes
into a braking operation state (shown in Figure 11-13).
When the IC shifts into the braking operation statefrom the low power consumption mode, the power
MOSFETs of the three phases are held turned off until
the IC initialization completes. The braking operation(UC-Brk) continues until VSP rises above the excitation
start voltage, VSST. When VSP > VSST, the IC enters in arunning state (Run mode) and starts the startup sequence.
The motor is controlled according to the fREF vs. VSP
relationship, as described in Figure 11-14. And thisrelationship is determined by VSMN and VSMX,
representing the VSP input voltages at minimum andmaximum speeds, respectively.
fRL and fRH, representing minimum and maximum
reference speeds, are defined by the SRL, SRH, and SU
parameters set in the configuration registers (Config 15

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SX68200M Series
to 17). fRL and fRH are given by the following equations
using these parameters:fRL = SRL × SU × 0.1 (Hz) , and(1)

fRH = SRH × SU × 0.1 (Hz) .

(2)

Where VSP = VSMN and fREF = fRL.
The fREF vs. VSP relationship is then defined as:
fREF = (S × VSP ) + Z .

(3)

Where Z is obtained by:
Z = fRH − (VSMX × S) .

(4)

(5)

The actual motor speed, S, depends on the number ofpole pairs in the rotor, NPP, as defined by:S=(fREF × 60)
.
NPP

(6)

Here, fREF is in Hz and S is in rpm.
Once the motor starts running, the fREF vs. VSP
relationship is valid for all the VSP values that fall into
the range between VSMN and VSMX. In the range where
VSP > VSMX, the motor speed is always determined by
fRH. The motor continues running until VSP becomes
lower than VSMN.

11.8.

PWM Control

The PWM generator built in the IC provides all thetimings associated with the PWM control of motor
currents through the internal MOSFETs. The PWM
generator also controls PWM frequency, duty cycle,
dead time, and current sampling time. PWM signals of
the three phases have the same frequency but have
independent duty cycles. Note that switching loss,
audible noise, and duty cycle accuracy must be taken
into account in setting a PWM frequency.
The PR[7:0] bits in the configuration register 0(Config 0) are for setting a PWM period for all the threephases. These 8 bits contain a positive integer. The
PWM period can be adjusted in units of 8 cycles of thesystem clock. The equation below defines the PWM
period, TPR:
TPR (µs) = 30.5 + (n × 0.4) .

Let S be the motor speed given by:(fRH − fRL )S=.
VSMX − VSMN

11.9.

Low Power Consumption Mode

The IC incorporates the low power consumption
mode function. When the VSP pin voltage, VSP, remains
at a voltage not exceeding the lower power consumption
mode transition voltage, VSSN, for a certain time, the IC
transits to the low power consumption mode. In the low
power consumption mode, the IC suppresses the VCCx
pin supply current as much as possible by clearing thefault flags set by the diagnostic register and by stopping
the internal circuit operations. To return from the low
power consumption mode, hold the outputs with off
status by the protection until the IC initialization
completed.
Note that VSSN must be set to a voltage lower than thereleasing voltage, VSSX; otherwise, VSSN will have noeffect. In the case where VSSN is set to a voltage higher
than VSSX, the IC ignores the VSSN setting and enters thelow power consumption mode even when VSP ≤ VSSX.

(7)

Where n is a positive integer determined by thePR[7:0] bits. For example, when PR[7:0] = [0100 0111](i.e., 71 in decimal) then TPR = 58.9 µs (typ.).

11.10. Dead TimeIn case any high-side power MOSFET of the threephases and the corresponding low-side power MOSFET
turn on at the same time, a short-circuit condition may
occur. For protecting all the 3-phase power MOSFETs
from such abnormal condition, a dead time must be set
between a turn-off of each high- or low-side power
MOSFET and the next turn-on of its pairing low- or
high-side power MOSFET.
The DT[5:0] bits in the configuration register 1(Config 1) are for setting a dead time for the threephases. Be sure to set the tDEAD so that it falls within therecommended operating range (i.e., ≥1.5 μs).The
equation below defines the dead time, tDEAD:t DEAD = n × 50 ns .

(8)

Where n is a positive integer determined by theDT[5:0] bits. A minimal value of tDEAD is 100 ns. For
example, when DT[5:0] = [01 1110] (i.e., 30 in decimal)
then tDEAD = 1.5 µs (typ.).

11.11. PWM Switching Mode
The IC has the following four PWM switching modes.
The 2-phase PWM switching mode decreases switchingloss by about 33% but results in less-accurate phasecurrent at low motor speed. In general, therefore,
operating the IC at lower speed and current requires the
3-phase PWM switching mode, whereas operating the
IC at higher speed and current demands the 2-phase
PWM switching mode.

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SX68200M Series
The CMS[1:0] bits in the configuration register(Config 2) is for setting which mode to be enabled.
● CMS[1:0] = [00]: 2-phase PWM switching● CMS[1:0] = [01]: 3-phase switching● CMS[1:0] = [10]:IC operation shifts from 3-phase to 2-phase switchingat a modulation index of ≥50%. IC operathion shifts
back to the 3-phase switching at a modulation index
of <50%.
● CMS[1:0] = [11]:IC operation shifts from 3-phase to 2-phase PWM
switching at a modulation index of ≥50%. IC
operation shifts back to 3-phase PWM switching at a
modulation index of <25%.

11.12. Charging of Bootstrap Capacitors
To start up the IC properly, turn on the low-side
power MOSFETs first and fully charge bootstrap
capacitors. The BCG[2:0] bits in the configuration
register 3 (Config 3) are for setting the charging time ofbootstrap capacitors, tBCG. tBCG should range from 1 ms
to 100 ms. When BCG[2:0] = 0, the charging operation
is disabled.

11.13. Current Detection
Current detection resistors, RSx, should be connected
between the low-side power MOSFET sources and theground. This connection allows only phase currents toflow through the current detection resistors when the
low-side power MOSFETs turn on. Which means thatcurrents are detectable only when the low-side power
MOSFETs are on. Section 11.2.15 describes the pins
used for current detection, the CSU, CSV, and CSW
pins. Section 11.2.14 gives details on the CSCOM pin
used as the reference input for current detection.
The PWM generator produces a current detection
signal for each phase at the timing of the midpoint ofeach low-side power MOSFET on-time. To detect stablecurrents, the IC needs a certain period of on-time (i.e.,
minimum on-time) from a turn-on of the low-side power
MOSFET until when currents are settled. If a low-side
on-time is too short to allow currents to settle in time,
the IC fails to perform current sampling. The minimum
on-time for current detection can be set through theserial communications. The MO[3:0] bits in theconfiguration register 3 (Config 3) are for setting theminimum on-time. These 4 bits contain a positive
integer. The equation below defines the minimum ontime, tMO:t MO = n × 400 ns .

(9)Where n is a positive integer determined by theMO[3:0] bits. For example, when MO[3:0] = [1010] (i.e.,

10 in decimal) then tMO = 4.0 µs (typ.).
When an RC filter is added to the input side of thecurrent-sensing operational amplifier, an additional
delay time will occur due to filtering. The timing ofcurrent detection can be delayed from the midpoint of an
on-time produced by the PWM generator. The CD[3:0]bits in the configuration register 2 (Config 2) are forsetting the current detection delay time, tCD.
The equation below defines the current detection
delay time, tCD:
t CD = n × 200 ns .

(10)

Where n is a positive integer determined by theCD[3:0] bits. For example, when CD[3:0] = [0101] (i.e.,
5 in decimal) then tCD = 1.0 µs (typ.).
The IC detects a phase current with the voltage acrossthe current detection resistor, RSx. The current-sensing
operational amplifier has the four input voltage ranges
selectable by the CR[1:0] bits in the configuration
register 0 (Config 0). Table 11-5 shows the maximum
input voltage ranges defined for the current-sensing
operational amplifier, with the corresponding maximum
current ranges, IFS. Table 11-6 lists resistances in the
maximum input voltage ranges, with the corresponding
current ranges as examples.
The maximum operating current, IMX, is a limitation
value of a target current required for the closed-loop
speed control. When the current needed for the speed
control exceeds IMX, the IC fails to maintain the speed
control due to the current limitation.
IMX is expressed as a percentage of the maximum
current range, IFS. The equation below defines IMX:
IMX = [38 + (n × 2)](%) × IFS .

(11)

Where n is a positive integer determined by theIM[4:0] bits in the configuration register 7 (Config 7).
For example, when IM[4:0] = [0 0110] (i.e., 6 indecimal) then IMX = 50% IFS. IMX should range from
38% to 100% of IFS.
Table 11-5. Maximum Input Ranges for Current-sensing
Operational Amplifier

1

Maximum Input
Voltage Range(mV)−500 to 500

Maximum Current
Range, IFS(A)±500 / RS00−250 to 250±250 / RS

1

1−125 to 125±125 / RS

CR1

CR0

0

1
0
−62.5 to 62.5
±62.5 / RS
RS represents a resistance of RSx, measured in mΩ.

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SX68200M Series
Table 11-6. Current Range vs. Example Sensing Resistor

11.14.2. Diagnostic Register

Maximum
Accuracy
PLOSS
Current Range, IFS
(mA)
(W)
(A)
CR[1:0] = [00] (Input Voltage Range ± 500 mV)

The detailed diagnostic information contained in the
diagnostic register (Register 30) can be read via theserial communications at any time. When a fault status
occurs, the corresponding bit in the diagnostic register is
set to “1” and is then held in this setting. The fault flag iscleared when either of the following conditions is met:

RS
(mΩ)

100

−5 to 5

±25

2.50

200

−2.5 to 2.5

±13

1.25

500

−1 to 1

±5

0.50

1000

−0.5 to 0.5

±3

0.25

CR[1:0] = [01] (Input Voltage Range ± 250 mV)
40−6.3 to 6.3

±31

1.56

100

−2.5 to 2.5

±13

0.63

200

−1.3 to 1.3

±6

0.31

500

−0.5 to 0.5

±3

0.13

CR[1:0] = [10] (Input Voltage Range ± 125 mV)
10−12.5 to 12.5

±63

1.56

20

−6.3 to 6.3

±31

0.79

50

−2.5 to 2.5

±13

0.31

100

−1.3 to 1.3

±6

0.17

CR[1:0] = [11] (Input Voltage Range ± 62.5 mV)
2−31.3 to 31.3

±156

1.95

5

−12.5 to 12.5

±63

0.78

10

−6.3 to 6.3

±31

0.39

50

−1.3 to 1.3

±6

0.08

11.14. Diagnostic Function
The IC includes the diagnostic function whichindicates a detected fault status. The fault status isavailable from the following two sources: the DIAG
output and the serial interface.

11.14.1. DIAG Pin Output
The DIAG pin outputs a fault signal when the IC
detects any fault status and the corresponding fault flagin the diagnostic register is set. When the diagnostic
function is disabled by the mask register (Register 29),
the DIAG pin outputs no fault signal. However, theDIAG pin outputs a fault signal even when the outputs
are off due to a short-circuit condition. The DIAG[4:0]bits in the Registers 30 and 31 define the detailed
settings of the DIAG pin output.
The DIAG pin is logic high in normal operation, andis logic low in fault signal output operation.

- When the reading from the diagnostic registercompletes- When the RESETn pin is held at logic low for theduration longer than a minimum reset pulse width
When an IC-specific fault state persists even after the
diagnostic register is cleared (e.g., when the IC still
remains in a high-temperature state), the diagnostic
register does not accept the clearing operation and keep
the fault flag being set.
The higher 6 bits contained in all the registers,
including the diagnostic register, always indicate serious
faults (i.e., critical fault flags). Among these bits, theMSB (bit 15) is the FF bit which indicates a common
fault flag. The FF bit is set to “1” in either of thefollowing conditions: when any of the bits (except for
the EE bit) in the diagnostic register is set; when a write
operation via the serial communications fails. The FF bit
is cleared only when the fault flag set by the diagnostic
register is cleared. The FF bit provides an indication thata fault has occurred since the last fault flag clear.
At power-on or after a power-on reset, the FF and
POR bits are set to “1” to indicate a critical fault flag,
whereas all other bits in the diagnostic register are
cleared. This fault status indicates that a power-on reset
has occurred and all the registers are reset to default.
Note that only a power-on reset occurs when the V3 pin
voltage exceeds the V3 Pin UVP Threshold Voltage,
V3UV. The occurrence of a power-on reset is not subject
to the VCCx pin voltage level.

11.14.3. Protective Operations at Fault
Detection
Table 11-7 lists the fault statuses and thecorresponding protective operations at fault detection.
The IC turns off all the power MOSFETs regardlessof the ESF bit setting when the IC detects the following
faults: V3 pin undervoltage (power-on reset), watchdog
timeout, memory error, soft overcurrent, and hard
overcurrent.
The EFS bit in the Run register (Register 31) sets
which protective operation to be performed when the IC
detects the following faults: power module fault, loss ofsynchronization, and thermal shutdown. When ESF = 1,
the IC turns off all the power MOSFETs and allows the
motor to coast upon detection of any of the three faults
mentioned above. While a soft overcurrent condition isdetected, the IC keeps all the power MOSFETs turned
off until any of the following conditions is met:

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SX68200M Series- The RESETn pin becomes logic low- A serial read operation completes- A power-on reset occurs

disabled because the accuracy of the diagnostic function
and the output control depend on the V3 pin voltage.

When ESF = 0, the IC never stops its operations evenafter the diagnostic register has set a fault flag.
Consequently, the IC and the motor must be controlledwith the master controller or an external circuit toprevent any damage.
Table 11-7. Fault Statuses and Protective Operations
Fault Status
No Fault
Power Module Fault
EEPROM Overwrite
V3 Pin Undervoltage(POR)
Watchdog Timeout
Memory Error
Loss of
Synchronization
Thermal Warning
Thermal Shutdown

Outputs Disabled
ESF = 0 ESF = 1
No
No
No
Yes*
No
No

11.15. Protection Functions
This section describes the various protections
provided in the SX68200M series. The embedded
protections monitor the parameters (e.g., V3 pin[regulator] voltage, watchdog timer, driving current)
fundamental to drive the IC and the motor reliably andsafely.

Latched
―
No
Yes

Yes*

Yes*

No

Yes*
Yes*

Yes*
Yes*

Yes
Yes

No

Yes*

No

No
No

No
Yes*

Soft Overcurrent

Yes*

Yes*

Hard Overcurrent

Yes*

Yes*

VM Pin Overvoltage
No
VM Pin Undervoltage
No* All the power MOSFETs off.

Yes*
Yes*

No
No
Only when
ESF = 1
Only when
ESF = 1NoNo

11.14.4. Fault Mask Setting
The mask register (Register 29) determines which
fault status not to be diagnosed (i.e., mask setting).
Extreme care must be taken, however, in disabling theindividual diagnostic parameters to protect the IC frompotentially damaging conditions.
When any given bit in the mask register is set to “1”,the corresponding diagnostic parameter is completely
disabled. According to the disabled diagnostic parameter,neither fault flag setting nor fault signal output from the
DIAG pin takes place. The maskable fault statuses andthe corresponding fault mask bits are as follows:● TW: Thermal warning● OT: Thermal shutdown● LOS: Loss of synchronization● PMF: Power module fault● HOC: Hard overcurrent● OVM: VM pin overvoltage● UVM: VM pin undervoltage
Note that the V3 undervoltage protection cannot be

11.15.1. V3 Pin Undervoltage Protection
The IC monitors the V3 pin voltage, V3, to ensure its
correct logical operation. When V3 decreases to the V3
Pin UVP Threshold Voltage (V3UV = 2.8 V) or less, all
the power MOSFETs turn off immediately. Then, the IC
enters a power-down state and stops all the internal
operations other than the V3 pin voltage monitoring.
When V3 increases to V3UV + V3UVHYS or more, the IC
performs a power-on reset, causing all the configuration
registers to be reset to their power-on states. The higher
6 bits contained in all the registers are also cleared at
this time. The FF and POR bits are set to “1” to indicate
the critical fault flag showing that a power-on reset has
occurred. The IC performs the same power-on reset
sequence at power-on or V3 brown-out (where only V3drops below V3UV momentarily).

11.15.2. Watchdog Timeout
The IC integrates a watchdog timer separated from theinternal oscillator. The watchdog timer is a clock whichis independent of the main controller system clock, andused for monitoring a latch-up state caused on the main
controller. The main controller regularly resets thewatchdog counter. When the counter enters a timeout
state without clearing, the FF and WD bits are set to “1”to indicate a critical fault flag.
When a watchdog timeout state occurs, the IC turns
off all the power MOSFETs and allows the motor tocoast because no accurate motor operation is guaranteed.
This strategy ensures the safe operations of the internal
power MOSFETs and the motor.
The watchdog timeout state persists until the RESETnpin becomes logic low, or a power-on reset occurs.

11.15.3. Memory Error
The IC integrates a non-volatile memory (EEPROM)
which stores register data. Each time the active registers
are read, the IC verifies the data stored in the EEPROM.
When verifying the stored data, the IC uses additional
parity bits to detect a data error. This data check is

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SX68200M Series
performed each time a read from the EEPROM or a
copy to the active registers takes place.
When the IC detects a memory error, all the power
MOSFETs turn off then the FF and ME bits are set to “1”to indicate a critical fault flag. All the operations otherthan this protective operation continue as normal.
In case of memory error, turn off the IC first, and thenturn on the IC again. This protective operation resets the
IC and enables reading the EEPROM data. After the
power-on reset, the ME bit is cleared. When the data isthen read correctly, the ME bit remains to be cleared. Incase a memory error reoccurs after the power-on reset,
the active registers must be reset to the correct values via
the serial communications. These correct values should
be rewritten to the EEPROM to overwrite the previously
saved data. After the rewrite operation, the EEPROM
should be read and transferred back to the active
registers. And this data check sequence permits the IC torecheck the present state of the stored data. When the
ME bit is cleared after the data recheck results in noerror, the IC continues operating. This state, however,indicates that a soft data error has occurred.
If the ME bit remains set at “1” even after the data
recheck, the IC is no longer usable due to a hard error
caused by the EEPROM.

11.15.4. Overvoltage Protection andUndervoltage Lockout for
Main Power Supply
The IC monitors the Main Supply Voltage, VDC,
supplied for driving the motor, with the VM pin to
detect an overvoltage or undervoltage condition. VDC
divided by a resistive voltage divider is applied to theVM pin.
Along with an increase in VDC, when the VM pin
voltage also increases to the VM Pin OVP Threshold
Voltage (VOVM = 1.24 V) or more, the FF and OVM bitsin the diagnostic register are set to “1”. In addition tothis state, all the power MOSFETs turn off when
ESF = 1.
Along with a decrease in VDC, when the VM pin
voltage also decreases to the VM Pin UVP Threshold
Voltage (VUM = 0.3 V or 0.6 V) or less, the FF andUVM bits in the diagnostic register are set to “1”. In
addition to this condition, the IC turns off all the power
MOSFETs when ESF = 1. VUM is a user-settableparameter by the UVS bit in the configuration register 8(Config 8) to 0.3 V or 0.6 V.

11.15.5. Overcurrent Protections
Two overcurrent protections are incorporated in the
IC: the soft overcurrent protection and the hard
overcurrent protection. Figure 11-15 shows operational
waveforms of these functions.
Restart

FG PinVoltage

Restart0

Phase
Current
0

CSx Pin
Voltage
VTRIPHVTRIPS
0

DIAG Pin
Voltage

6PWM(max.)

tOCF
tHOC

0

t

Figure 11-15. Operational Waveforms of SOCP
(ESF = 0) and HOCP (ESF = 0, HOC = 0)

11.15.6. Soft Overcurrent Protection
The IC uses a user-settable soft overcurrent thresholdcurrent, ILIM, expressed as a percentage of the maximum
current range, IFS. The soft overcurrent protection(SOCP) monitors a load short or loop control failure.
When the IC detects a current exceeding ILIM, the FF
and OC bits are set to “1” to indicate a critical fault flag
and all the power MOSFETs turn off for protecting the
motor driving system.
The ESF bit in the Run register determines whether tolatch the power MOSFET turn-off operation after the
SOCP detection.
When ESF = 1, the IC keeps all the power MOSFETs
turned off and the motor stopped (i.e., latch operation)
until a restart after the detected error has been eliminated.
When ESF = 0, the IC turns off all the power
MOSFETs upon SOCP detection. When phase currents
fall below ILIM, the IC restarts to operate.
The equation below defines the SOCP thresholdcurrent, ILIM:
ILIM = [38 + (n × 2)](%) × IFS .

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(12)

30

SX68200M Series
Where n is a positive integer determined by the
IO[4:0] bits in the configuration register 7 (Config 7).
For example, when IO[4:0] = [1 0101] (i.e., 21 indecimal) then ILIM = 80% IFS.
When IO[4:0] = 0, the SOCP function is disabled.
This setting does not protect the internal power
MOSFETs and the load; therefore, alternative measures
must be taken to protect the IC and the motor from any
damage due to large currents.

11.15.7. Hard Overcurrent Protection
The hard overcurrent protection (HOCP) consists ofan independent monitoring circuit in order to promptly
offer the protection against overcurrents. The HOCP
function detects a load short or loop control failure.
When the IC detects a current exceeding the HOCP
Threshold Current, IHOC, the IC turns off all the power
MOSFETs to protect the motor driving system, and thensets FF and HOC bits in the diagnostic register to “1”.
Moreover, the IC has a propagation delay of <10 µs
between the overcurrent detection to the HOCP
activation.
The IHO bit in the configuration register 3 (Config 3)
sets IHOC, either to 150% or 200% of the maximum
current detection range, IFS.
The HOCP circuit also has a digital low pass filter
that avoids itself from responding to an instantaneous
overcurrent induced by power MOSFET switching.
Thus, the IC does not detect an overcurrent of less thantOCF, 0.5 µs to 2 µs, settable by the OCF[1:0] bits in theconfiguration register 2 (Config 2).
The ESF bit in the Run register determines whether tolatch the power MOSFET turn-off operation after the
HOCP detection.
When ESF = 1, the IC keeps all the power MOSFETs
turned off and the motor stopped (i.e., latch operation)
until a restart after the detected error has been eliminated.
When ESF = 0, the IC turns off all the power
MOSFETs for a period of an HOCP hold time, tHOC,
upon HOCP detection. The IC then resumes monitoring
the currents after a lapse of tHOC. When an HOCP
condition is detected again, the IC turns off all the power
MOSFETs. After a period of tHOC, the IC restarts
monitoring the current. This sequence continues until astop command is asserted by an external controller. The
equation below defines the HOCP hold time, tHOC:
t HOC = (1 + n) × 100 ms .

(13)

Where n is a positive integer determined by the
OHT[3:0] bits in the configuration register 1 (Config 1).
For example, when OHT[3:0] = [1001] (i.e., 9 indecimal) then tHOC = 1.0 s.

11.15.8. Thermal Warning and
Thermal Shutdown
The IC has the thermal shutdown (TSD) circuit for
both of the built-in control MIC and gate-drive MIC.
The control MIC has two thermal thresholds for thethermal warning and TSD. The gate-drive MIC has one
thermal threshold for the TSD. Among these threethermal thresholds, the gate-drive TSD threshold is set
to the lowest value. Hence, the IC is basically protectedby the TSD of the gate-drive MIC.
When a junction temperature of the gate-drive MIC
increases to the gate-drive MIC TSD temperature, TDHD
or more, the DIAG pin becomes logic low and the PFM
bit in the diagnostic register is set to “1”. In addition tothis state, all the power MOSFETs turn off when
ESF = 1.
When the junction temperature of the gate-drive MIC
decreases to TDHD − TDHYSD or less, the DIAG pin
becomes logic high. But the state of the PMF bit in the
diagnostic register remains unchanged until a reset
operation occurs.
Phase
Current0Gate-drive
MIC TJTJW

TJW − TJWHYS

0DIAG Pin
Voltage0tFigure 11-16. TSD Operational Waveforms ofGate-drive MIC (ESF = 1, PMF = 0)

11.15.9. Undervoltage Lockout for
Logic Supply
To prevent permanent damage due to an undervoltage
condition in the logic power supply, the SX68200M
series has the undervoltage lockout (UVLO) circuits forboth of the high- and low-side power supplies.
As Figure 11-17 shows, when the voltage between the
VBx and output (U, V1, or W1) pins, VBS, decreases to
VBS(OFF) or less, the high-side UVLO gets activated andall the power MOSFETs turn off. When VBS increases to
VBS(ON) or more after that, the IC restarts to operate.
During the high-side UVLO operation, the DIAG pin
outputs no fault signals.
As Figure 11-18 shows, when the voltage between the

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SX68200M Series
VCCx and COM pins, VCC, decreases to VCC(OFF) or less,the low-side UVLO gets activated. During the low-side
UVLO operation, the PMF bit in the diagnostic register
is set to “1” and the DIAG pin becomes logic low. In
addition to this condition, the IC turns off all the power
MOSFETs when ESF = 1. When VCC increases to
VCC(ON) or more after that, the IC restarts to operate.
Phase
Current
0

VBS

As described in Section 11.3, the IC estimates the
motor speed as part of the closed-loop speed control
system. The IC recognizes a loss-of-synchronization
condition, in which a sensorless signal and a motor
rotational frequency are asynchronous, when theestimated speed is lower than a lowest speed threshold,fLS, or higher than a highest speed threshold, fHS.
The LS[5:0] bits and HS[3:0] bits in the configuration
register 6 (Config 6) are for setting the lowest and higher
speed thresholds, fLS and fHS, respectively.
The equation below defines the lowest speed
threshold, fLS:
fLS = n × 0.8 Hz .

VBS(OFF)

Where n is a positive integer determined by theLS[5:0] bits. For example, when LS[5:0] = [00 0000](i.e., 0 in decimal) then fLS = 0 Hz. When fLS = 0, thelowest speed detection is disabled.

DIAG Pin
Voltage0tHigh-side UVLO Operational
Waveforms

0

VCC
VCC(ON)0

DIAG Pin
Voltage
0

Figure 11-18. Low-side UVLO Operational
Waveforms (PMF = 0)

The equation below defines the highest speed
threshold, fHS:
fHS = n × 102.4 Hz .

Phase
Current

VCC(OFF)(14)

VBS(ON)0

Figure 11-17.

11.15.10. Loss-of-Synchronization
Protection

t

(15)

Where n is a positive integer determined by theHS[3:0] bits. For example, when HS[3:0] = [0101] (i.e.,
5 in decimal) then fHS = 512 Hz.
After the LOS detection, the FF and LOS bits in the
diagnostic register are set to “1”. When DIAG[4:0] = 0
or 1, the DIAG pin becomes logic low. In addition tothis state, all the internal power MOSFETs are turned off(i.e., coast mode) when ESF = 1.
The RSC bit is the reset bit. When RSC = 0, the IC
holds the coast mode until a stop command is asserted
by an external controller. When RSC = 1, the IC
increments a reset counter and starts the startup
sequence. When the startup fails and an LOS condition
reoccurs, the reset counter is incremented again. And the
IC repeats the startup sequence. This operation continues
until the reset counter reaches the upper limit number ofrestarts, determined by the RSN[1:0] bits in theconfiguration register 2 (Config 2), or until a stop
command is asserted. When the reset counter reaches thepredetermined upper limit number of resets, the IC holds
the coast mode until a stop command is asserted by oneof the control inputs. When RSN[1:0] = [11], the IC
repeats the startup sequence indefinitely until terminatedwith a stop command asserted by the control inputs.
Figure 11-19 to Figure 11-21 illustrate operation
sequences after LOS detection.

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SX68200M Series
Start command input

Sync. lost

DIAG Pin
VoltageStartupsucceeded

Stop command input● Address Cycle
0

Control
State

Run

Figure 11-19.

DIAG Pin
Voltage

LOS

Coast

Stop

Start

Run

Restart by Command Input (RSC = 0,
ESF = 1, DIAG[4:0] = 1)

Startup succeeded

Sync. lost
Resynchronization
attempt continues

Run

LOS

Run

Figure 11-20. Restart by Sustained LOS Operation(RSC = 1 or 0, ESF = 0, DIAG[4:0] = 1)

DIAG Pin
VoltageStartup succeeded

Sync. lost

0
Start

LOS Coast: Init

- Register Address: 7 Bits
The 7-bit address. The first 2 bits, A[6:5], must be set
to 0. The remaining 5 bits, A[4:0], select the register
address for the first register access. The address istransferred MSB first.
- R/W Bit: 1 Bit (Read = 1, Write = 0)

- Acknowledge Bit: 1 Bit
The master device uses an acknowledge bit to check if
the subordinate is responding to the address and data.
● Data Cycle
The 8-bit data following an acknowledge bit. A single
register transfer requires 2 data cycles. The data istransferred MSB first.

Startup failed

Run LOS Coast: Init

An address cycle consists of the 7-bit register address,
the R/W bit, and the acknowledge bit (see Figure 11-23)
as follows:

The R/W bit defines the direction of data transfer.
When R/W = 1, the master device reads one or morebytes from the IC. When R/W = 0, the master device
writes one or more bytes to the IC. The register is
updated only when two complete bytes are received.

0

Control
State

ControlStatethe occurred start condition by resetting the data transfer
sequence with ignoring all data from any incomplete
register write.

Start

Run

Figure 11-21. Restart by Auto-restart Sequence(RSC = 1, ESF = 1, DIAG[4:0] = 1)

11.16. Serial Communications
The IC has access to the internal registers through theserial communications, which uses two bus lines, SCL
and SDA. Through these data lines, data is exchanged
between the microcontroller as a master device and the
IC as a subordinate device. The SCL (input) clock isgenerated in the master device. The SCL and SDA lines
have a hysteresis-based glitch suppression circuit toenhance their noise immunities. The control sequencesof communications are consist of the several steps listed
below:● Start Condition
A start condition is defined by a falling edge of the
SDA line while the SCL line is high. The master device
always initiates a start condition.
A start condition is permitted to occur at any time
timing during a data transfer. The IC always responds● Stop Condition
A stop condition is defined by a rising edge of the
SCL line while the SDA line is high.
Except for when indicating a start/stop condition, themaster device must hold the SDA line to be low or highwhile the master device clock is high. The SDA line canbe changed only when the SCL line is low.
When performing a write, the master device releases
the SDA line to receive the acknowledgement during the
9th clock cycle following each data byte. After 2-byte
data is received, the data is transferred to the register in
the IC.
When reading the data from the IC, the master device
acknowledges the address in the same manner as thewrite sequence. While the IC transmits the data to themaster device, the master device holds the SDA line
release state. The data transmission of the first 8 bits arecompleted, the master device puts the SDA line to low
before the 9th clock cycle so that the master device canacknowledge the data. When the IC detects that the SDA
line is low during the 9th clock cycle, the IC responds bytransmitting the 2nd data byte to the master device. Then,the data byte is transmitted in pairs to the master device
until the master device puts the SDA line to low. Whenthe IC detects that the SDA line becomes low, the IC
stops the data transfer and waits for a stop condition

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SX68200M Series
signal.
At power-on, when the V3 pin voltage increases to theV3 Pin UVP Threshold Voltage, V3UV or more, the IC
responds to the data transfer sequence. When the V3 pin
voltage is less than V3UV, the IC never respond to any
request for the serial communications.
When writing to an arbitrary register, the IC ignoresthe first 6 bits, D[15:10].
When a read from an arbitrary register takes place, thefirst 6 bits contain the critical fault flags (i.e., same as
the higher 6 bits in the Register 30). The remaining 10

Stop

Start

Register Address

Driving
SDA

bits, D[9:0], are the contents of the register address atthat moment (except for the Register 28 and 30). When aread from the Register 28 takes place, the 10 bits,
NVC[9:0], which follow the critical fault flags are thecontents of the EEPROM write cycle counter. Whenreading the Register 30, the 7 bits which follow thecritical fault flags are fault flags, including TW, OT,
LOS, PMF, HOC, OVM, UVM. The remaining 3 bits
are 0.
Figure 11-22 to Figure 11-27 are examples of theserial communications sequences.

SDA

0

0

A4

A3

A2

A1

A0

SCL

1

2

3

4

5

6

7

R

W

1

0

R

W

AK

NAK

AK

MAK

MNK

SAK

SNK

Master
Acknowledge

Master Noacknowledge

Sub.
Acknowlege

Sub. Noacknowlege

MasterIC
Address

Start

Read

Figure 11-22.

Start

IDL
Idle

Acknowledge
from master
Data (MS Byte)

Register Address

Stop

Serial Communications Sequence

Acknowledge
from IC

Driving
SDA

NAK

No acknowledge
from master
Stop

Data (LS Byte)

R

SDA

0

0

A4

A3

A2

A1

A0

1

AK D15 D14 D13 D12 D11 D10 D9

SCL

1

2

3

4

5

6

7

8

9

D8 AK

D7

D6

D5

D4

D3

D2

D1

D0 NAK

MasterIC

Figure 11-23.

Single Word Read from Register
Write to register

Acknowledge
from IC
Start

Driving
SDA

Register Address

Acknowledge
from IC
Data (MS Byte)

W

SDA

0

0

A4

A3

A2

A1

A0

0

AK D15 D14 D13 D12 D11 D10 D9

SCL

1

2

3

4

5

6

7

8

9

Acknowledge
from IC
Stop

Data (LS Byte)
D8

AK

D7

D6

D5

D4

D3

D2

D1

D0

AK

MasterIC

Figure 11-24.

Single Word Write to Register

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SX68200M Series

Register nStart

MS Byte from
Register n

LS Byte from
Register n

MS Byte from
Register n+1

Register n

LS Byte from
Register n+2

MS Byte from
Register n+3

Multiple Reads from Register

Write to Register n

Write to Register n+1

Write to Register n+2

S
S
S
S
S
S
S
Address W A MS Write A LS Write A MS Write A LS Write A MS Write A LS Write A Stop
K
K
K
K
K
K
K

Figure 11-26.

Register nStart

MS Byte from
Register n+2

S
M
M
M
M
M
M
M
Address R A MS Read A LS Read A MS Read A LS Read A MS Read A LS Read A MS Read N Stop
K
K
K
K
K
K
K
K

Figure 11-25.

Start

LS Byte from
Register n+1

Multiple Writes to Register

Register n

Write to Register nSSS
Address W A MS Write A LS Write A StopK
K
K

Figure 11-27.

IDL

Start

MS Byte from
Register n

LS Byte from
Register nSMM
Address R A MS Read A LS Read N Stop
K
K
K

Write then Read Register

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SX68200M Series
11.17. EEPROM

output or the FF bit in the diagnostic register.

The IC integrates a non-volatile memory (EEPROM)
which stores register data, thus enabling passwordprotected security.

11.17.2. Locking by Password

11.17.1. Register Data Saving
The parameter settings are written to the EEPROM by
setting the SAV bit in the Register 28 from “1” to “0”.
The register settings are read from the EEPROM after a
power-on reset.
All the register settings are read from/written to the
EEPROM as a single operation. Writing to/reading fromthe values of only a single register is not permitted.
Writing (saving data) to the EEPROM requires the
EEPROM Write Supply Voltage, VPP, to be applied to
the VPP pin. For a stable voltage supply to the
EEPROM, VPP stepped down by the internal linear
regulator is applied to the EEPROM.
Before a save sequence proceeds, VPP must be applied
within a specified period of time, tPRS, and becontinuously applied until the sequence completes.
When no data save to the EEPROM is needed, the VPP
pin may be left applied from VPP, connected to theground, or left open.
When the motor is still running at the time the savesequence proceeds, the IC turns off the power
MOSFETs and enters the coast mode to stop the motor
run. At this time, the IC ignores the inputs to the VSP
pin and the motor control commands entered through theserial communications. Any changes occurred during thesave sequence may or may not be written to the
EEPROM. Reading from the Register 28 is the only
recommended serial communications operation during
the save sequence. The save sequence takes 700 ms(typ.) to complete.
When the save sequence completes successfully, thewrite count stored to the NVC[9:0] bits in the Register
28 is incremented and all the fault flag bits are cleared.
An increment in the value of the NVC[9:0] bits indicatesa successful save sequence completion; therefore, it isnecessary to read the NVC value in the Register 28
before and after the save sequence.
The higher 6 bits in the Register 28 contain the criticalfault flags. When the save sequence fails and a fault
condition occurs, the FF bit is set to “1” to indicate acritical fault flag.
For data retention reliability, the guaranteed numberof EEPROM writes should be set to less than 1000 times.
When the EEPROM write cycle counter exceeds 1023,
the EE bit in the diagnostic register (Register 30) is
permanently set to “1”, indicating the EEPROM
overwrite fault flag. The write cycle counter then resets
the existing count and continues counting from 0 to1023. Once the EE bit is set to “1”, the write cycle
counter stops when reaching 1023. Note that the EE bit
does not affect the states of the DIAG pin fault signal

To protect the EEPROM from an overwrite or read
operation, enable the password setting with thePWD[9:0] bits in the configuration register 11 (Config
11). Setting the PWD[9:0] bits to an arbitrary number
other than 0 protects the EEPROM from any
unauthorized access. When the PWD[9:0] bits are
initially passed, the IC is capable of reading the
EEPROM contents via the serial communications and ofsaving the configuration register contents to the
EEPROM.
When the PWD[9:0] bits are set to 0, the IC is put intoa password-unlocked state and thus becomes capable ofreading from/writing to the configuration register
contents (i.e., unlocked mode). In the unlocked mode,
the IC performs the motor speed control with both of the
VSP pin voltage and the configuration register contents.
When the PWD[9:0] bits are set to an arbitrary
number other than 0 (but within the specified range), theIC enters a password-locked state, i.e., locked mode,
immediately after a power-on reset or a return from thelow power consumption mode. In the locked mode,reading from the EEPROM via the serial
communications results in the state that IC outputs
random numbers, except for the Registers 28, 30, and
the PN[3:0] bits in the Config 15. The IC also performs
the motor speed control with the VSP pin voltage only,
according to the parameter settings previously stored in
the EEPROM. In this operation, the IC ignores any
changes to the configuration register contents.
● Locking Procedure
To enable the locked mode, follow the procedure
below:● Apply 15 V to the VCCx pin and 24 V to the VPP pin.
● Enter a password to the PWD[9:0] bits.
● Set the SAV bit from “1” to “0” in order to save thepassword to the EEPROM.
● Power off the VCCx and VPP pin voltages. The ICthen operates in the locked mode.
● Unlocking Procedure
To release the locked mode, follow the procedure
below:● Apply 15 V to the VCCx pin and 24 V to the VPP pin.
● Enter the password to the PWD[9:0] bits, and wait for
15 seconds to clear the password.
● Power off the VCCx and VPP pin voltages. The ICthen operates in the unlocked mode.

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SX68200M Series
Table 11-8. Protection Mode Definitions
Function

Locked Mode

Serial Write

Disabled(1)Random number
output(2)EnabledWrite only

Read/Write

Read only

Read/Write

Read only

Read only

Read only

Read only

VSP

VSP/Serial
communications

Serial Read
Password:
PWD[9:0]
ID Number:PN[3:0]Register 30(Diagnostic)
Register 29(EEPROM)
Speed Control(1)(2)

Unlocked Mode

EnabledExcept for the PWD[9:0] bits.
Except for the PN[3:0] bits in the Config 15, and theRegisters 28, 30.

11.18. Register Overview
The order of serial data transfer is MSB first in unitsof 16 bits. The first 5 bits are assigned as register
addresses. The IC employs the registers consisting of:- 22 system configuration registers- 1 EEPROM setting register- 2 diagnostic registers- 1 motor operation setting register
The registers are grouped by their functions, as amply
described in Section 11.20:● System Configuration Registers
Config 0: PWM Frequency
Config 1: Basic Timing
Config 2: Detection Timing
Config 3: HOCP Detection Timing● Startup Setting Registers
Config 4: Startup Hold
Config 5: Startup Timing● Motor Control Setting Registers
Config 6: Rotation Limitation
Config 7: Current Limitation
Config 8: Speed Control Gains, KI
Config 9: Current Control Gains, KCP and KCI
Config 10: Phase Angle Control Gains, KTP and KTI
Config 11: EEPROM Security Password
Config 12: Motor Coil Inductance MultiplierConfig 13: Magnetic Field Control
Config 14: Dead Time Compensation● Speed Setting Register
Config 15: Speed Limitation
Config 16: Speed Reference
Config 17: Minimum Reference Speed
Config 18: Maximum Speed Voltage
Config 19: Excitation Start Voltage
Config 20: Minimum Speed Voltage
Config 21: Low Power Consumption Mode Transition
Voltage● Internal Control Setting Registers
Register 28: EEPROM Control
Register 29: Diagnostic Register Fault Mask
Register 30: Diagnostic Register
Register 31: Run Register

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SX68200M Series
11.19. Register Map
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Config 0

0

0

0

0

0

0

CR1

CR0

PR7

PR6

PR5

PR4

PR3

PR2

PR1

PR0

Config 1

0

0

0

0

0

0

DT5

DT4

DT3

DT2

DT1

DT0 OHT3 OHT2 OHT1 OHT0

Config 2

0

0

0

0

0

0

CMS1 CMS0 RSN1 RSN0 OCF1 OCF0

Config 3

0

0

0

0

0

0

MO3

MO2

MO1

MO0 BCG2 BCG1 BCG0 IWM1 IWM0 IHO

Config 4

0

0

0

0

0

0

HT5

HT4

HT3

HT2

Config 5

0

0

0

0

0

0

STS4 STS3 STS2 STS1 STS0 STD4 STD3 STD2 STD1 STD0

Config 6

0

0

0

0

0

0

LS5

LS4

LS3

LS2

LS1

LS0

HS3

HS2

HS1

HS0

Config 7

0

0

0

0

0

0

IM4

IM3

IM2

IM1

IM0

IO4

IO3

IO2

IO1

IO0

Config 8

0

0

0

0

0

0

UVS

HR3

HR2

HR1

HR0

FGS

SI3

SI2

SI1

SI0

Config 9

0

0

0

0

0

0

0

CP3

CP2

CP1

CP0

ETR

CI3

CI2

CI1

CI0

Config 10

0

0

0

0

0

0

―

TP3

TP2

TP1

TP0

―

TI3

TI2

TI1

TI0

Config 11

0

0

0

0

0

0

PWD9 PWD8 PWD7 PWD6 PWD5 PWD4 PWD3 PWD2 PWD1 PWD0

Config 12

0

0

0

0

0

0

LW9

LW6

LW5

LW4

LW3

LW2

LW1

LW0

Config 13

0

0

0

0

0

0

XWM1 XWM0 LHT1 LHT0

FW5

FW4

FW3

FW2

FW1

FW0

Config 14

0

0

0

0

0

0

DTC

―

DG3

DG2

DG1

DG0

DM3

DM2

DM1

DM0

Config 15

0

0

0

0

0

0

SCS

―

PN3

PN2

PN1

PN0

SU3

SU2

SU1

SU0

Config 16

0

0

0

0

0

0

SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
SRH9 SRH8 SRH7 SRH6 SRH5 SRH4 SRH3 SRH2 SRH1 SRH0

Config 17

0

0

0

0

0

0

SRL9 SRL8 SRL7 SRL6 SRL5 SRL4 SRL3 SRL2 SRL1 SRL0

Config 18

0

0

0

0

0

0

VX9

VX8

VX7

VX6

VX5

VX4

VX3

VX2

VX1

VX0

Config 19

0

0

0

0

0

0

VS9

VS8

VS7

VS6

VS5

VS4

VS3

VS2

VS1

VS0

Config 20

0

0

0

0

0

0

VN9

VN8

VN7

VN6

VN5

VN4

VN3

VN2

VN1

VN0

Config 21

0

0

0

0

0

0

VC9

VC8

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

0

0

0

0

0

0

SAV

―

―

―

―

―

―

―

―

―

0

0

0

0

0

0

NVC9 NVC8 NVC7 NVC6 NVC5 NVC4 NVC3 NVC2 NVC1 NVC0

0

0

0

0

0

0

TW

OT

LOS

PMF

HOC OVM UVM

0

0

0

0

0

0

―

―

―

―

―

FF

POR

ME

WD

OC

EE

TW

OT

LOS

PMF

HOC OVM UVM

0

0

0

0

0

0

DIAG1 DIAG0 RDG

PMR

STM

FF

POR

ME

WD

OC

EE

Register 28 Write
EEPROM Control
Register 28 Read
EEPROM Count
Register 29
Fault Mask
Register 30 Write
Register 30 Read
Diagnostic
Register 31
Run
Register Read

LW8

LW7

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HT1

HT0

CD3

HD3

CD2

HD2

―

RSC

HD1

CD0

HD0

―

―

―

―

―

―

―

BRK

DIR

RUN

DIAG4 DIAG3 DIAG2

ESF

CD1

38

SX68200M Series
11.20. Configuration Registers
This section describes the register contents. The checkmark in the Ref. column indicates the row that contains thereference register values (i.e., the parameters that the GUI initially displays) tabulated in Section 5.

11.20.1. System Configuration Registers
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Config 0

0

0

0

0

0

0

CR1

CR0

PR7

PR6

PR5

PR4

PR3

PR2

PR1

PR0

Config 1

0

0

0

0

0

0

DT5

DT4

DT3

DT2

DT1

DT0 OHT3 OHT2 OHT1 OHT0

Config 0: PWM Frequency

Config 1: Basic TimingCR[1:0]DT[5:0]

The CR[1:0] bits are for setting the maximum input
range of the current-sensing operational amplifiers. For
more details, see Section 11.13.

The DT[5:0] bits are for setting a dead time, tDEAD. Be
sure to set the tDEAD so that it falls within therecommended operating range (i.e., ≥1.5 μs).
The equation below defines tDEAD, which should range
from 100 ns to 3.15 µs in increments of 50 ns:

CR1
0
0
1
1

CR0
0
1
0
1

Maximum Input Range−500 mV to 500 mV−250 mV to 250 mV−125 mV to 125 mV−62.5 mV to 62.5 mV

Ref.
✓

(17)

Where n is a positive integer determined by theDT[5:0] bits. A minimal value of tDEAD is 100 ns. For
example, when DT[5:0] = [01 1110], tDEAD = 1.5 µs.

PR[7:0]

OHT[3:0]

The PR[7:0] bits are for setting a PWM period, TPR,
used for the PWM current control for motor control
system. For more details on the PWM control, see
Section 11.9.
The equation below defines TPR, which should range
from 30.5 µs to 132.5 µs:
TPR (µs) = 30.5 + (n × 0.4) .

t DEAD = n × 50 ns .

(16)

Where n is a positive integer determined by thePR[7:0] bits. For example, when PR[7:0] = [0100 0111],
TPR = 58.9 µs.

The OHT[3:0] bits are for setting a hold time of thehard overcurrent protection, tHOC. For more details on
the HOCP function, see Section 11.15.7.
The equation below defines tHOC, which should range
from 100 ms to 1.6 s in increments of 100 ms:
t HOC = (1 + n) × 100 ms .

(18)

Where n is a positive integer determined by the
OHT[3:0] bits. For example, when OHT[3:0] = [1001],
tHOC = 1.0 s.

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SX68200M Series

Config 2

15

14

13

12

11

10

0

0

0

0

0

0

9

8

7

6

5

4

CMS1 CMS0 RSN1 RSN0 OCF1 OCF0

3

2

1

0

CD3

CD2

CD1

CD0

Config 2: Detection Timing

CMS[1:0]

RSN[1:0]

Select the PWM switching mode to be enabled by
setting the CMS[1:0] bits as defined below. For moredetails on the PWM switching modes, see Section 11.11.

Select the number of restarts allowed after a startup
failure by setting the RSN[1:0] bits as defined below.

CMS1
0
0
1

1

CMS0
PWM Switching Mode02-phase PWM switching
13-phase PWM switching0
Prohibited
Automatically shifts between
2-/3-phase PWM switchingmodes
1- Shifts from 3-phase to 2phase PWM switching at a
modulation index of ≥50%
- Shifts from 2-phase to 3phase PWM switching at a
modulation index of <25%

Ref.

RSN1
0

RSN0
0

Number of Restarts Allowed
5 times

Ref.

0

1

10 times

✓

1
1

0
1

20 times
Infinite

OCF[1:0]✓

Select an HOCP filtering time, tOCF, by setting the
OCF[1:0] bits as defined below. For more details on the
HOCP function, see Section 11.15.7.
OCF1
0
0

OCF0
0
1

Filtering Time, tOCF
2.0 µs
1.5 µsRef.

10

1.0 µs✓1

1

0.5 µsCD[3:0]
The CD[3:0] bits are for setting a current detection
delay time, tCD, which starts later than the midpoint of apredetermined PWM period. For more details, see
Section 11.13. The equation below defines tCD, whichshould range from 0 µs to 3 µs:
t CD = n × 200 ns .

(19)

Where n is a positive integer determined by theCD[3:0] bits. For example, when CD[3:0] = [0011],
tCD = 0.6 µs.

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SX68200M Series

Config 3

15

14

13

12

11

10

9

8

7

0

0

0

0

0

0

MO3

MO2

MO1

6

5

4

3

2

1

0

MO0 BCG2 BCG1 BCG0 IWM1 IWM0 IHO

Config 3: HOCP Detection Timing
MO[3:0]

IWM[1:0]

The MO[3:0] bits are for setting a minimum on-time,
tMO, for current detection. The equation below defines
tMO, which should range from 0 µs to 6 µs:

Select a windmill braking current, IWM, by setting theIWM[1:0] bits as defined below. IMX represents a
maximum operating current.
Windmill Braking Current,
IWM1 IWM0
Ref.
IWMt MO = n × 400 ns .

(20)

Where n is a positive integer determined by theMO[3:0] bits. For example, when MO[3:0] = [0101],tMO = 2.0 µs.

0025% IMX

0
1
1

1
0
1

50% IMX
75% IMX
100% IMX✓

BCG[2:0]
Select a charging time of bootstrap capacitor, tBCG, by
setting the BCG[2:0] bits as defined below. For moredetails, see Section 11.12.
BCG2

BCG1

BCG0

Charging Time, tBCG

0

0

0

No bootstrap
charging

0
0
0

0
1
1

1
0
1

1 ms
2 ms
5 ms

1

0

0

10 ms

1
1
1

0
1
1

1
0
1

20 ms
50 ms
100 msRef.

IHO
The IHO bit is for setting an HOCP threshold current,
IHOC. Select either 150% or 200% of the maximum
current detection range, IFS, by setting the IHO bit as
defined below.
IHO
HOCP Threshold Current
Ref.
0150% IFS

1

200% IFS✓✓

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SX68200M Series
11.20.2. Startup Setting Registers
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Config 4

0

0

0

0

0

0

HT5

HT4

HT3

HT2

HT1

HT0

HD3

HD2

HD1

HD0

Config 5

0

0

0

0

0

0

STS4 STS3 STS2 STS1 STS0 STD4 STD3 STD2 STD1 STD0

Config 4: Startup Hold

Config 5: Startup Timing

HT[5:0]STS[4:0]

The HT [5:0] bits are for setting a startup hold time,
tHOLD. The following equations define tHOLD according toa PWM period, TPR, determined by the PR[7:0] bits.

The STS[4:0] bits are for setting a driving frequency
at startup, fST. The equation below defines fST, whichshould range from 0 Hz to 49.6 Hz:● When TPR = 125.3 µs to 132.5 µs:t HOLD = TPR × n × 400 ms .

fST = n × 1.6 Hz .
(21)

(26)

Where n is a positive integer determined by theSTS[4:0] bits. For example, when STS[4:0] = [0 1000],
fST = 12.8 Hz.

● When TPR = 62.5 µs to 124.9 µs:t HOLD = TPR × n × 800 ms .

(22)

● When TPR = 41.7 µs to 62.1 µs:
t HOLD = TPR × n × 1200 ms .

(23)

(24)

Where n is a positive integer determined by theHT[5:0] bits. For example, when PR[7:0] = [0100 0111]
and HT[5:0] = [00 0101], TPR = 58.9 µs as calculated by
Equation (16). Thus, tHOLD = 353.4 ms based on
Equation (22).
HD[3:0]
The HD[3:0] bits are for setting the duty cycle of astartup hold current, DHOLD. The equation below defines
DHOLD with the maximum current detection range, IFS.
DHOLD should range from 0% to 22.89%.
DHOLD = n × 1.525% .

The STD[4:0] bits are for setting parameters for thetwo startup modes: a duty cycle at startup, DST, for theDC alignment start mode; a driving current, IRAMP, forthe ramp-up start mode.
The equation below defines DST, which should range
from 0% to 48.44%:
DST = n × 1.5625% .

● When TPR = 30.5 µs to 41.3 µs:t HOLD = TPR × n × 1600 ms .

STD[4:0](27)

Where n is a positive integer determined by the
STD[4:0] bits. For example, when STD[4:0] = [0 0100],
DST = 6.3%.
The equation below defines IRAMP, which should range
from 0% IFS to 48.44% IFS:IRAMP = n × 1.5625% × IFS .

(28)

Where n is a positive integer determined by the
STD[4:0] bits. For example, when STD[4:0] = [0 0100],
IRAMP = 6.3% IFS.

(25)

Where n is a positive integer determined by theHD[3:0] bits. For example, when HD[3:0] = [0100],
DHOLD = 6.1%.

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SX68200M Series
11.20.3. Motor Control Setting Registers
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Config 6

0

0

0

0

0

0

LS5

LS4

LS3

LS2

LS1

LS0

HS3

HS2

HS1

HS0

Config 7

0

0

0

0

0

0

IM4

IM3

IM2

IM1

IM0

IO4

IO3

IO2

IO1

IO0

Config 6: Rotation Limitation

Config 7: Current Limitation

Section 11.15.10 explains the loss-of-synchronization
protection in detail.

IM[4:0]LS[5:0]
The LS[5:0] bits are for setting a lowest speed
threshold, fLS. The equation below defines fLS, whichshould range from 0 Hz to 50.4 Hz. When fLS = 0, thelowest speed detection is disabled.

The IM[4:0] bits are for setting a maximum operating
current, IMX. For more details, see Section 11.13.
The equation below defines IMX with the maximum
current detection range, IFS. IMX should range from 38%
IFS to 100% IFS.
IMX = [38 + (n × 2)](%) × IFS .

fLS = n × 0.8 Hz .

(31)

(29)

Where n is a positive integer determined by theLS[5:0] bits. For example, when LS[5:0] = [00 0000],
fLS = 0 Hz.

Where n is a positive integer determined by theIM[4:0] bits. For example, when IM[4:0] = [0 0110],
IMX = 50% IFS.
IO[4:0]HS[3:0]
The HS[3:0] bits are for setting a highest speed
threshold, fHS. The equation below defines fHS, whichshould range from 0 Hz to 1536 Hz. When fHS = 0, thehighest speed detection is disabled.
fHS = n × 102.4 Hz .

(30)

Where n is a positive integer determined by theHS[3:0] bits. For example, when HS[3:0] = [0101],
fHS = 512 Hz.

The IO[4:0] bits are for setting an SOCP thresholdcurrent, ILIM. When IO[4:0] = 0, the SOCP function isdisabled. For more details, see Section 11.15.6.
The equation below defines ILIM with the maximum
current detection range, IFS. ILIM should range from
38% IFS to 100% IFS.
ILIM = [38 + (n × 2)](%) × IFS .

(32)

Where n is a positive integer determined by the
IO[4:0] bits. For example, when IO[4:0] = [1 0101],
ILIM = 80% IFS.

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SX68200M Series

Config 8

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

UVS

HR3

HR2

HR1

HR0

FGS

SI3

SI2

SI1

SI0

Config 8: Speed Control Gains, KI

UVS

SI[3:0]The UVS bit is for setting a motor undervoltage
threshold, VUM (i.e., the VM pin threshold voltage used
for detecting a voltage drop in VDC; see Section 11.15.4).
Select either a 0.3 V or 0.6 V threshold voltage by
setting the UVS bit as defined below.

The SI[3:0] bits are for setting a constant of theintegral gain constant, KI, used for the speed control.
The equation below defines KI, which should range from
1/128 KNSI to 256 KNSI:K I = 2(n−7) × K NSI .

UVSVM Pin UVP Threshold Voltage

Ref.

0

0.3 V

✓４

1

0.6 V

(34)

Where n is a positive integer determined by theSI[3:0] bits, and KNSI is a fixed integral gain of the speed
control.
For example, when SI[3:0] = [0110], KSI = 0.5 KNSI.

HR[3:0]
The HR[3:0] bits are for setting a ramp-up time of thehold current, tHRMP.
The equation below defines tHRMP, which should range
from 0% tHOLD to 93.75% tHOLD:t HRMP = (n × 6.25) (%) × t HOLD .

(33)

Where n is a positive integer determined by theHR[3:0] bits. For example, when HR[3:0] = [1000],tHRMP = 50% tHOLD.
FGSThe FGS bit is for setting an output pulse frequencyof the FG pin. Select either a ×1 or ×3 motor electricalcycle frequency by setting the FGS bit as defined below.
FGS

FG Pin Output Pulse Frequency

Ref.

0

Motor electrical cycle frequency: ×1✓

1

Motor electrical cycle frequency: ×3

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SX68200M Series
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Config 9

0

0

0

0

0

0

0

CP3

CP2

CP1

CP0

ETR

CI3

CI2

CI1

CI0

Config 10

0

0

0

0

0

0

―

TP3

TP2

TP1

TP0

―

TI3

TI2

TI1

TI0

Config 9: Current Control Gains, KCP and KCI

Config 10: Phase Angle Control Gains, KTP and KTI

CP[3:0]TP[3:0]

The CP[3:0] bits are for setting a constant of the
proportional gain, KCP, used for the current control. The
equation below defines KCP, which should range from
1/128 KNCP to 256 KNCP:The TP[3:0] bits are for setting a constant of the
proportional gain, KTP, used for phase angle control. The
equation below defines KTP, which should range from
1/128 KNTP to 256 KNTP:

K CP = 2(n−7) × K NCP .

(35)

K TP = 2(n−7) × K NTP .

(37)

Where n is a positive integer determined by theCP[3:0] bits, and KNSI is a fixed proportional gain of thecurrent control.
For example, when CP[3:0] = [0110], KCP = 0.5 KNCP.

Where n is a positive integer determined by theTP[3:0] bits, and KNTP is a fixed proportional gain of thesensorless control.
For example, when TP[3:0] = [0110], KTP = 0.5 KNTP.

ETR

TI[3:0]The ETR bit is for setting a ramp-up current for motor
restart.

The TI[3:0] bits are for setting a constant of theintegral gain, KTI, used for phase angle control. The
equation below defines KTI, which should range from
1/128 KNTI to 256 KNTI:

ETR

Ramp-up Current Setting

Ref.

0

Restart with fixed ramp-up current✓

1

Restart with spread ramp-up current

CI[3:0]
The CI[3:0] bits are for setting a constant of theintegral gain, KCI, used for the current control. The
equation below defines KCI, which should range from
1/128 KNCI to 256 KNCI:K CI = 2(n−7) × K NCI .

K TI = 2(n−7) × K NTI .

(38)

Where n is a positive integer determined by the
TI[3:0] bits, and KNTI is an integral gain of the sensorless
control.
For example, when TI[3:0] = [0110], KTI = 0.5 KNTI.

(36)

Where n is a positive integer determined by theCI[3:0] bits, and KNCI is a fixed integral gain of thecurrent control.
For example, when CI[3:0] = [0110], KCI = 0.5 KNCI.

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SX68200M Series
15

14

13

12

11

10

9

8

Config 11

0

0

0

0

0

0

PWD9 PWD8 PWD7 PWD6 PWD5 PWD4 PWD3 PWD2 PWD1 PWD0

Config 12

0

0

0

0

0

0

LW9

LW8

7

LW7

6

LW6

5

LW5

4

LW4

3

LW3

2

LW2

1

LW1

0

LW0

Config 11: EEPROM Security Password

Config 12: Motor Coil Inductance Multiplier

PWD[9:0]

LW[9:0]

The PWD[9:0] bits are for setting a password forcontrolling access to the EEPROM. The setting range isfrom 0 to 1023. For more details, see Section 11.17.2.

The LW[9:0] bits are for setting an inductance of the
motor winding, LWM. The equation below defines LWM,
which should range from 0 LU to 1023 LU:
LWM = n × LU .

(39)

Where n is a positive integer determined by theLW[9:0] bits, and LU is a factor of the inductance.
For example, when LW[9:0] = [00 1100 1000],
LWM = 200 LU.

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SX68200M Series
15

14

13

12

11

10

9

8

7

Config 13

0

0

0

0

0

0

XWM1 XWM0 LHT1 LHT0

Config 14

0

0

0

0

0

0

DTC

―

DG3

6

DG2

5

4

3

2

1

0

FW5

FW4

FW3

FW2

FW1

FW0

DG1

DG0

DM3

DM2

DM1

DM0

Config 13: Magnetic Field Control

Config 14: Dead Time Compensation

XWM[1:0]

DTC

Select a minimum threshold of the windmill braking
current by setting the XWM[1:0] bits as defined below.
IMX represents a maximum operating current. When thebraking current falls below this minimum threshold, theIC considers motor operations to be stopped (see Section
11.5).

The DTC bit enables or disables the dead timecompensation.

XWM1 XWM0

Minimum Braking Current
Threshold

Ref.
✓

0

0

6.25% IMX

0
1
1

1
0
1

12.50% IMX
18.75% IMX
25.00% IMX

DTCDead Time Compensation

Ref.

0

Disabled✓

1

EnabledVMC

The VMC bit enables or disables the compensation of
the VM pin voltage.
Ref.

0

VM Pin Voltage Compensation
Disabled

1

Enabled✓

VMC

LHT[1:0]

The LHT[1:0] bits are for setting a hold time after an
LOS (loss of synchronization) fault occurs.
LHT1

LHT0

LOS Fault Hold Time

Ref.

0

0

800 ms

✓

0
1
1

1
0
1

400 ms200 ms
100 msDG[3:0]The DG[3:0] bits are for setting a dead timecompensation gain, KDTC. The equation below defines
KDTC, which should range from 0 to 15:
K DTC = n .

(41)

Where n is a positive integer determined by theDG[3:0] bits.

FW[5:0]The FW[5:0] bits are for setting a field weakening
current, IFW. When IFW < 0, the motor operates in fieldenhancement mode; when IFW > 0, the motor operates infield weakening mode.
The equation below defines IFW with the maximum
current detection range, IFS. IFW should range from −26%
IFS to 100% IFS.
IFW = (n − 13) × 2(%) × IFS .

(40)

DM[3:0]The DM[3:0] bits are for setting a compensation ratioof the maximum dead time, tDCM (%).The equation
below defines tDCM with the dead time, tDEAD. tDCM
should range from 0% to 93.75%.
t DCM = n × 6.25 (%) t DEAD .

(42)

Where n is a positive integer determined by theDM[3:0] bits.

Where n is a positive integer determined by theFW[5:0] bits.
For example, when FW[5:0] = [00 1101],
IFW = 0% IFS.

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SX68200M Series
11.20.4. Speed Setting Registers
For the motor speed setting, see Section 11.7.
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Config 15

0

0

0

0

0

0

SCS

―

PN3

PN2

PN1

PN0

SU3

SU2

SU1

SU0

Config 16

0

0

0

0

0

0

SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
SRH9 SRH8 SRH7 SRH6 SRH5 SRH4 SRH3 SRH2 SRH1 SRH0

Config 15: Speed Limitation

Config 16: Speed Reference

SCS

SR[9:0]

Select the speed control mode to be enabled by setting
the SCS bit as defined below.

SRH[9:0]SCS
01

Speed Control ModeControlled by externally input
voltage on the VSP pin(external mode)
Controlled by internal registersettings

Ref.

✓

PN[3:0]

The PN[3:0] bits constitute a user-assigned variable
used as an identification number or a revision number.
The setting range is from 0 to 15.
SU[3:0]The SU[3:0] bits are for setting a multiplier, fU, of thereference speed, fREF. The equation below defines fU,
which should range from 0 Hz to 1.6 Hz.
fU = (1 + n) × 0.1 (Hz) .

(43)

Where n is a positive integer determined by theSU[3:0] bits. For example, when [3:0] = [1001],
fU = 1.0 Hz.

● SCS = 1
When SCS = 1, the motor reference speed, fREF, is set
by the parameters directly input via the serial
communications. In this option, the IC ignores the VSP
pin input voltage and only uses the value in the SR[9:0]bits.
Hence, the SR[9:0] bits are for setting fREF. The
equation below defines fREF, which should range from 0
fU to 1023 fU:
fREF = n × fU (Hz) .

(44)

Where n is a positive integer determined by theSR[9:0] bits, and fU is a multiplier of the speed range.
For example, when SR[9:0] = [00 0001 1110],
fREF = 30 fU.
The equation below calculates an actual motor speed,from the excitation frequency, fREF, and the number ofmagnetic pole pairs in the motor, NPP:S=

(fREF × 60)
.
NPP

(45)

When fREF = 30 fU, NPP = 4, and fU = 1.0 Hz, forinstance, we will find the actual motor speed as follows:S=(

30 × 1.0 × 60
) = 450 rpm .
4● SCS = 0
When SCS = 0, the IC uses the parameters in theSRH[9:0] bits to control the motor speed, not theSR[9:0] bits. In the external mode, the SRH[9:0] bits
determine the maximum reference speed, fRH,
corresponding to the VSP pin input.

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SX68200M Series

Config 17

15

14

13

12

11

10

0

0

0

0

0

0

9

8

7

6

5

4

3

2

1

0

SRL9 SRL8 SRL7 SRL6 SRL5 SRL4 SRL3 SRL2 SRL1 SRL0

Config 17: Minimum Reference Speed
SRL[9:0]
The SRL[9:0] bits are for setting the minimum
reference speed, fRL, which corresponds to the VSP pin
input voltage. The equation below defines fRL:
fRL = n × fU .

(46)

Where n is a positive integer determined by theSRL[9:0] bits, and fU is a multiplier of the speed range.
For example, when SRL[9:0] = [00 0000 0000],
fRL = 0 fU.
The equation below calculates an actual minimum
motor speed, from the minimum reference speed, fRL,
and the number of magnetic pole pairs in the motor, NPP:
SMIN =(fRL × 60)
.
NPP

(47)

When fRL = 0 fU, NPP = 4, fU = 1.0 Hz, for instance,
we will find the actual minimum motor speed asfollows:
SMIN = (0 × 1.0 × 60
) = 0 rpm .
4

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SX68200M Series
15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Config 18

0

0

0

0

0

0

VX9

VX8

VX7

VX6

VX5

VX4

VX3

VX2

VX1

VX0

Config 19

0

0

0

0

0

0

VS9

VS8

VS7

VS6

VS5

VS4

VS3

VS2

VS1

VS0

Config 20

0

0

0

0

0

0

VN9

VN8

VN7

VN6

VN5

VN4

VN3

VN2

VN1

VN0

Config 21

0

0

0

0

0

0

VC9

VC8

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

Config 18: Maximum Speed Voltage

Config 20: Minimum Speed Voltage

VX[9:0]VN[9:0]The VX[9:0] bits are for setting the VSP pin voltage
at which the motor reaches its maximum speed, VSMX.
The equation below defines VSMX, which should range
from 0 V to 5.88 V.

The VN[9:0] bits are for setting the VSP pin voltage
at which the motor reaches its minimum speed, VSMN.
The equation below defines VSMN, which should range
from 0 V to 5.88 V.

VSMX =

n
(V) .
174

(48)

VSMN =

n
(V) .
174

(50)

Where n is a positive integer determined by theVX[9:0] bits. For example, when VX[9:0] = [11 0110
0110] at power-on reset, VSMX = 5.000 V.

Where n is a positive integer determined by theVN[9:0] bits. For example, when VN[9:0] = [01 0101
1100] at power-on reset, VSMN = 2.000 V.

Config 19: Excitation Start Voltage

Config 21: Low
Transition Voltage

Power

ConsumptionModeVS[9:0]The VS[9:0] bits are for setting the VSP pin voltage at
which the motor starts excitation, VSST. The equation
below defines VSST, which should range from 0 V to
5.88 V.
VSST =

n
(V) .
174

VC[9:0]The VC[9:0] bits are for setting the VSP pin voltage
at which the IC enters the low power consumption mode,
VSSN. The equation below defines VSSN, which should
range from 0 V to 5.88 V.

(49)

Where n is a positive integer determined by theVS[9:0] bits. For example, when VS[9:0] = [01 1011
0011] at power-on reset, VSST = 2.500 V.

VSSN =

n
(V) .
174

(51)

Where n is a positive integer determined by theVC[9:0] bits. For example, when VC[9:0] = [00 1010
1110] at power-on reset, VSSN = 1.000 V.

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SX68200M Series
11.20.5. Internal Control Setting Registers
Register 28 Write
EEPROM Control
Register 28 Read
EEPROM Count
Register 29
Fault Mask

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

SAV

―

―

―

―

―

―

―

―

―

0

0

0

0

0

0

NVC9 NVC8 NVC7 NVC6 NVC5 NVC4 NVC3 NVC2 NVC1 NVC0

0

0

0

0

0

0

TW

Register 28: EEPROM Control
Section 11.17 provides further information.

OT

LOS

PMF

HOC OVM UVM

―

―

―

Register 29: Diagnostic Register Fault Mask
To disable each diagnostic
corresponding bit to “1”.

function,

set

the

● WriteSAV
When the SAV bit is changed from “1” to “0” in thecase where the motor stops and the IC is in the unlocked
mode, the following parameters are written to the
EEPROM:- Config 0 to Config 21- Register 29 (Diagnostic Register Fault Mask)- Register 31 (Run Register)
After the writing completes, the values of theNVC[9:0] bits are incremented by 1.

Bit Name

Fault Description

TW

Thermal warning

OT

Thermal shutdown

LOS

Loss of synchronization

PMF

Power module fault

HOC

Hard Overcurrent

OVM

VM pin overvoltage

UVM

VM pin undervoltage● ReadFault Mask Setting for Diagnostic
RegisterRef.

0

Diagnostic function enabled✓

1

Diagnostic function disabled

NVC[9:0]

The NVC[9:0] bits operate as EEPROM write counter
outputs. After the writing to the EEPROM completes,
the values of the NVC[9:0] bits are incremented by 1.
When the number of write count exceeds 1023 times, theEE bit in the diagnostic register is permanently set to “1”.

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SX68200M Series
15

14

13

12

11

10

9

8

7

6

5

4

3

Register 30 Write

0

0

0

0

0

0

―

―

―

―

―

Register 30 Read
Diagnostic

FF

POR

ME

WD

OC

EE

TW

OT

LOS

PMF

HOC OVM UVM

2

DIAG4 DIAG3 DIAG2

―

1

0

―

―

―

―

Register 30: Diagnostic Register● WriteSelect which fault signals the DIAG pin will output
by setting the DIAG[4:0] bits in Register 30 andRegister 31. When a fault status is detected, the DIAG
pin becomes logic low.
The table below lists the DIAG[4:0] bits settings.
DIAG[4:0] DIAG Pin Fault Signal to Be Output
0

General fault flag (FF)1
Loss of synchronization (LOS)
2
Temperature output of control MIC
3
Clock
4
PWMDIR*
5
SHTRIG*6ADDONE*
7
CLFLK_SYN*
8
CLFLK_ASYN*
9PWM output (HIN1)10PWM output (LIN1)
11PWM output (HIN2)
12PWM output (LIN2)
13
PWM output (HIN3)
14
PWM output (LIN3)
15
Watchdog timeout
16
Watchdog active
17
Power module fault (PMF)18
Power module fault (PMF) reset
19
Hard overcurrent (HOC)20
q-axis current
21
―
22
―
23
―
24 to 31 Reserved* Not used in motor designing.

Ref.
✓● ReadWhen a fault status is detected, the corresponding bit
is set to “1”. Section 11.14.2 explains the diagnostic
register in detail; Section 11.15 provides detailed
descriptions on the protections.
Bit Name
FF
POR
ME
WD
OC
EE
TW
OT
LOS
PMF
HOC
OVM
UVM

0
1

Fault Description
General fault flag
V3 pin undervoltage (power-on reset)
Memory error
Watchdog timeout
Soft overcurrent
EEPROM overwrite limit
Thermal warning for control MIC
Thermal shutdown for control MIC
Loss of synchronization
Power module fault (thermal shutdown forgate-drive MIC, low-side UVLO)
Hard overcurrent
VM pin overvoltage
VM pin undervoltage

Fault Detection
No fault detected
Fault detected

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SX68200M Series

Register 31
Run

15

14

13

12

11

10

0

0

0

0

0

0

9

RDG

The RDG bit determines whether to clear the DIAG
pin status that the GUI displays. When RDG = 0, thecontrols related to the restart operations are disabled.

0
1

6

5

4

3

2

1

0

PMR

STM

ESF

RSC

BRK

DIR

RUN

RSC

For the DIAG[1:0] bits, see the Register 30 definition
table.

GUI Display Setting
The fault status displayed on the
GUI is cleared.
The fault status displayed on the
GUI is not cleared (latched).

7

DIAG1 DIAG0 RDG

Register 31: Run Register

RDG

8

The RSC bit selects whether to restart motor
operations when a loss-of-synchronization (LOS)
condition is detected (see Section 11.15.10).
RSC
0

Ref.
1

Motor Restart Selection
No restart (The motor stops withcoasting upon LOS detection.)
Restart allowed (The motor restarts
upon LOS, SOCP, or HOCP
detection when RSC = 1, RUN = 1,
and BRK = 0.)

Ref.
✓

✓
BRK

PMR

The PMR bit selects whether to put the gate-drive
MIC into a standby state, in accordance with the reset
operation by the RESETn pin.
PMR
01Power Module Reset Selection
The gate-drive MIC enters a standby
state, according to the RESETn
input signal.
The gate-drive MIC does not enter astandby state.

Ref.
✓

The BRK bit controls braking operation. The braking
operation is enabled only when RUN = 1. When
RUN = 1 and BRK = 1, all the low-side power
MOSFETs turn on to produce electrodynamic braking.
Note that the BRK bit does not affect the braking
operation in the startup sequence.
BRK

Braking Control0

Normal operation (brake off)1

Braking operation (brake on)

Ref.
✓

DIR
STM

The DIR bit is for setting the direction of motor
rotation.

The STM bit selects the startup mode.
STM

Startup Mode0

Ramp-up start mode1

DC alignment start mode

Ref.

DIR Bit

DIR Pin

0
0

✓

ESF

DIR Bit
Ref.

L
H

Motor
Direction
Forward
Reverse1

L

Reverse✓1

H

Forward✓

The ESF bit selects the protective operation to be
performed at fault detection (see Section 11.14.3).
RUN
ESF
0

1

Protective Operation
The motor keeps driving; thecorresponding fault flag in the
diagnostic register is set.
All the power MOSFETs turn off;the corresponding fault flag in the
diagnostic register is set.

Ref.

The RUN bit controls the start/stop operations of the
motor.
RUN✓

Motor Start/Stop0

Excitation stops

1

Motor run starts

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Ref.
✓

53

SX68200M Series

Register Read

15

14

13

12

11

10

FF

POR

ME

WD

OC

EE

9

8

7

6

5

4

3

2

1

0

Register Read
The higher 6 bits contained in all the registers are
fault flags, which always indicate critical faults. The
remaining 10 bits read the individual settings of thecorresponding register. The table below provides thedefinitions of the higher 6 bits.
Bit Name
Fault Description
FF
General fault flag
V3 pin undervoltage
POR(power-on reset)
ME
Memory error
WD
Watchdog timeout
OC
Soft overcurrent
EE
EEPROM overwrite limit

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SX68200M Series
12. Design Notes

12.3.

12.1.

When measuring the leakage current of the output
transistors (power MOSFETs) incorporated in the IC,
note that all of the output (U, V1, W1), LSx, and COM
pins must be appropriately connected. Otherwise, theoutput transistors may result in permanent damage. Also
note that the gate and source of each output transistor
should have the same potential during the leakage
current measurement. Moreover, care should be taken
during the measurement because each output transistor
is connected as follows:

Notes on the Sequences for Turning
On/Off the IC

The following must be taken into account in thesequences for turning on and off the IC.
● Turning on
In startup operations (incl. a restart), the following
pins must be held at logic low until the V3 pin voltage isestablished: DIR, RESETn, SDA, and SCL. This lowlevel setting of the pins must also be applied to a restartfrom abnormalities in power supply, such as an
instantaneous power failure. In particular, when
applying external voltages on these pins, be sure to set
the pins to logic low until the V3 pin voltage isestablished.
● Turning off
To turn off the IC, decrease the VSP pin voltage first,
and then stop the motor operation.

12.2.

PCB Pattern Layout

Figure 12-1 shows a schematic diagram of a motor
drive circuit. The circuit consists of current paths having
high frequencies and high voltages, which also bringabout negative influences on IC operation, noiseinterference, and power dissipation. Therefore, PCB
trace layouts and component placements play animportant role in circuit designing.
Current loops, which have high frequencies and highvoltages, should be as small and wide as possible, inorder to maintain a low-impedance state. In addition,
ground traces should be as wide and short as possible sothat radiated EMI levels can be reduced.

Considerations in IC Characteristics
Measurement● All the high-side drains are internally connected to the
VBB pin.
● In the U-phase, the high-side source and the low-side
drain are internally connected to the U pin. (In the Vand W-phases, the high- and low-side transistors areunconnected inside the IC.)● The high-side gates are internally pulled down to the
output pins.
● The low-side gates are internally pulled down to the
COM pin.
The following are circuit diagrams representing
typical measurement circuits for leakage current: Figure12-2 shows the high-side transistor (Q1H) in the U-phase;
Figure 12-3 shows the low-side transistor (Q1L) in the Uphase. And all the pins that are not represented in thesefigures are open. When measuring the high-side
transistors, leave all the pins not be measured open.
When measuring the low-side transistors, connect theLSx pin to be measured to the COM pin, then leaveother unused pins open.

VBB
36

Q1H

Q2H

Q3H

VDC

VBB
36

34 W1
31 V1

CDC

MICs
27

RS
27
Gate
Driver

U

31 V1
23 V2
W1
34
W2
19

A

Ground traces
should be wideand short.

U

23 V2
Q1L

Q2L Q3L

19 W2

M
20 LS3COM

921 LS226 LS1

LS3
20
LS2
21
LS1
26

High-frequency, high-voltage
current loops should be as
small and wide as possible.

Figure 12-2. Typical Measurement Circuit for Highside Transistor (Q1H) in U-phase

Figure 12-1. High-frequency, High-voltage Current
Paths
SX68200M-DSE Rev.2.1
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SX68200M Series

36

Q1H

Q2H

13.1.

VBB

Steady-state loss in a power MOSFET can becomputed by using the RDS(ON) vs. ID curves, listed in
Section 14.3.1. As expressed by the curves in Figure
13-1, a linear approximation at a range the ID is actuallyused is obtained by: RDS(ON) = α × ID + β.

Q3H
34 W1
31 V1

MICs
27

U

A

23 V2
Q1L

Q2L Q3L

Power MOSFET Steady-state Loss,
PRON

VCC = 15 V

4.0

19 W2

3.5

20 LS3COM

921 LS226

LS1RDS(ON) (Ω)

3.0

y = 0.27x + 2.14

125 °C

2.5
75 °C

2.0
1.5

25 °C

1.0
0.5

Figure 12-3. Typical Measurement Circuit for Lowside Transistor (Q1L) in U-phase

0.0
0.0

0.5

1.0

1.5

2.0

ID (A)

13. Calculating Power Losses andEstimating Junction TemperatureThis section describes the procedures to calculate
power losses in output transistors (power MOSFETs),and to estimate a junction temperature. Note that thedescriptions listed here are applicable to the IC, which iscontrolled by a 3-phase sine-wave PWM driving
strategy. For quick and easy references, we offer
calculation support tools online. Please visit our website
to find out more.
● DT0050: SX68200M Series Calculation Tool
http://www.semicon.sanken-ele.co.jp/en/calctool/mosfet_caltool_en.html
Total power loss in a power MOSFET can beobtained by taking the sum of the following losses:
steady-state loss, PRON; switching loss, PSW; the steadystate loss of a body diode, PSD. In the calculation
procedure we offer, the recovery loss of a body diode,
PRR, is considered negligibly small compared with theratios of other losses.
The following subsections contain the mathematicalprocedures to calculate these losses (PRON, PSW, and PSD)
and the junction temperature of all power MOSFETs
operating.

Figure 13-1. Linear Approximate Equation of RDS(ON)vs. IDThe values gained by the above calculation are thenapplied as parameters in Equation (52), below. Hence,the equation to obtain the power MOSFET steady-state
loss, PRON, is:PRON =1 π∫ I (φ)2 × R DS(ON) (φ) × DT × dφ
2π 0 D= 2√2α (1
3+ M × cos θ) IM 3
3π 32
1 1
+ 2β ( +M × cos θ) IM 2 . (52)8 3πWhere:
ID is the drain current of the power MOSFET (A),RDS(ON) is the drain-to-source on-resistance of thepower MOSFET (Ω),
DT is the duty cycle, which is given byDT =1 + M × sin(φ + θ),
2

M is the modulation index (0 to 1),cosθ is the motor power factor (0 to 1),
IM is the effective motor current (A),α is the slope of the linear approximation in the RDS(ON)vs. ID curve, andβ is the intercept of the linear approximation in the
RDS(ON) vs. ID curve.

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SX68200M Series
13.2.

Power MOSFET Switching Loss, PSW

Switching loss in a power MOSFET can be calculated
by Equation (53) or (54), letting IM be the effective
current value of the motor:

PSD =● SX68201M
VDC√2× fC × αE × IM ×
.
π
150

PSW =

(53)

● SX68204M / SX68205M
VDC√2× fC × αE × IM ×
.
π
300

PSW =

The values gained by the above calculation are thenapplied as parameters in Equation (55), below. Hence,the equation to obtain the body diode steady-state loss,
PSD, is:1 π∫ V (φ) × ISD (φ) × (1 − DT) × dφ
2π 0 SD

1 1 4= α( −
M × cos θ) IM 2
2 2 3π√2 1 π+β ( − M × cos θ) IM .
π
2 8

(54)

Where:
fC is the PWM carrier frequency (Hz),VDC is the main power supply voltage (V), i.e., the
VBB pin input voltage, andαE is the slope on the switching loss curve (see Section
1.1.1.1).

Where:
VSD is the source-to-drain diode forward voltage of thepower MOSFET (V),ISD is the source-to-drain diode forward current of thepower MOSFET (A),DT is the duty cycle, which is given by
DT =

13.3.

Body Diode Steady-state Loss, PSD

Steady-state loss in the body diode of a power
MOSFET can be computed by using the VSD vs. ISD
curves, listed in Section 14.3.1. As expressed by the
curves in Figure 13-2, a linear approximation at a range
the ISD is actually used is obtained by: VSD = α × ISD + β.

VSD (V)

25 °C

0.8

1 + M × sin(φ + θ),
2

M is the modulation index (0 to 1),cosθ is the motor power factor (0 to 1),
IM is the effective motor current (A),α is the slope of the linear approximation in the VSD vs.
ISD curve, andβ is the intercept of the linear approximation in the VSD
vs. ISD curve.

13.4.

1.2
1.0

(55)

Estimating Junction Temperature ofPower MOSFETThe junction temperature of all power MOSFETs
operating, TJ, can be estimated with Equation (56):y = 0.25x + 0.54

0.6
125 °C

0.4

TJ = R J−C × {(PRON + PSW + PSD ) × 6} + TC .

75 °C

0.2
0.0
0.0

0.5

1.0

1.5

2.0

ISD (A)(56)

Where:
RJ-C is the junction-to-case thermal resistance (°C/W)
of all the power MOSFETs operating, andTC is the case temperature (°C), measured at the point
defined in Figure 3-3.

Figure 13-2. Linear Approximate Equation of VSD vs.
ISD

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SX68200M Series
14. Performance Curves
14.1.

Transient Thermal Resistance Curves

Ratio of Transient Thermal Resistance

The following graphs represent transient thermal resistance (the ratios of transient thermal resistance), with steadystate thermal resistance = 1.
1.00

0.10

0.01
0.001

0.01

0.1
Time (s)110Ratio of Transient Thermal Resistance

Figure 14-1. Transient Thermal Resistance: SX68201M

1.00

0.10

0.01
0.001

0.01

0.1

1

10

Time (s)Figure 14-2. Transient Thermal Resistance: SX68204M

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Ratio of Transient Thermal Resistance

SX68200M Series
1.00

0.10

0.01
0.001

0.01

0.1
Time (s)110Figure 14-3. Transient Thermal Resistance: SX68205M

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SX68200M Series
14.2.

Allowable Effective Current Curves

The following curves represent allowable effective currents in 3-phase sine-wave PWM driving with parameters suchas typical RDS(ON) and typical switching losses.

14.2.1. SX68201M
Operating conditions: VBB pin input voltage, VDC = 150 V; VCCx pin input voltage, VCC = 15 V; modulation index,
M = 0.9; motor power factor, cosθ = 0.8; junction temperature, TJ = 150 °C.
fC = 16 kHz

Allowable Effective Current (Arms)

2.0

1.5

1.0

0.5

0.0
25

50

75

100

125

150

TC (°C)
Figure 14-4. Allowable Effective Current (fC = 16 kHz)SX68200M-DSE Rev.2.1
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SX68200M Series
14.2.2. SX68204M
Operating conditions: VBB pin input voltage, VDC = 300 V; VCCx pin input voltage, VCC = 15 V; modulation index,
M = 0.9; motor power factor, cosθ = 0.8; junction temperature, TJ = 150 °C.
fC = 16 kHz

Allowable Effective Current (Arms)

1.0

0.5

0.0
25

50

75

100

125

150

TC (°C)
Figure 14-5. Allowable Effective Current (fC = 16 kHz)14.2.3. SX68205M
Operating conditions: VBB pin input voltage, VDC = 300 V; VCCx pin input voltage, VCC = 15 V; modulation index,
M = 0.9; motor power factor, cosθ = 0.8; junction temperature, TJ = 150 °C.
fC = 16 kHz

Allowable Effective Current (Arms)

1.5

1.0

0.5

0.0
25

50

75

100

125

150

TC (°C)
Figure 14-6. Allowable Effective Current (fC = 16 kHz)SX68200M-DSE Rev.2.1
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SX68200M Series
14.3.

Performance Curves of Output Parts

14.3.1. Output Transistor Performance Curves
14.3.1.1.

SX68201M
VCC = 15 V

4.0

1.2

3.5
3.0

125 °C

2.5
75 °C

2.0

VSD (V)RDS(ON) (Ω)

25 °C

1.0

1.5

0.6
75 °C

125 °C

0.4

25 °C

1.0

0.8

0.2

0.5
0.0

0.0
0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

ID (A)

1.5

2.0

ISD (A)

Figure 14-7. Power MOSFET RDS(ON) vs. ID

Figure 14-8. Power MOSFET VSD vs. ISD

14.3.1.2.
14.3.1.2.

SX68204M
VCC = 15 V

8.0

1.2

7.0
6.0

125°C

VSD (V)RDS(ON) (Ω)

25°C

1.0

5.0
4.0

75°C

3.0

0.8
75°C
0.6
0.4

25°C

125°C

2.0
0.2

1.0

0.0

0.0
0.0

0.5

1.0

1.5

0.0

Figure 14-9. Power MOSFET RDS(ON) vs. ID

0.5

1.0

1.5

ISD (A)

ID (A)

Figure 14-10.

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Power MOSFET VSD vs. ISD

62

SX68200M Series
14.3.1.3.

SX68205M
VCC = 15 V

6.0

25 °C

4.0

1.0

75 °C

3.0
2.0

25 °C

VSD (V)

5.0

RDS(ON) (Ω)

1.2

125 °C

0.8
0.6
75 °C

125 °C

0.4
0.2

1.0

0.0

0.0
0.0

0.5

1.0

1.5

2.0

0.0

0.5

Figure 14-11.

Power MOSFET RDS(ON) vs. ID

1.0

1.5

2.0

ISD (A)

ID (A)

Figure 14-12.

SX68200M-DSE Rev.2.1
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Power MOSFET VSD vs. ISD

63

SX68200M Series
14.3.2. Switching Loss Curves
14.3.2.1.

SX68201M

Conditions: VBB pin voltage = 150 V, half-bridge circuit with inductive load.
Switching Loss, E, is the sum of turn-on loss and turn-off loss.
VB = 15 V

60
50

50

40
30
20
10

TJ =125 °C

40

TJ = 125 °C

E (µJ)E (µJ)VCC = 15 V

60

30
20
10

TJ = 25 °C

0

TJ = 25 °C

0
0.0

0.5

1.0

1.5

2.0

0.0

0.5

ID (A)

Figure 14-13.

High-side Switching Loss

1.0

1.5

2.0

ID (A)

Figure 14-14.

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Low-side Switching Loss

64

SX68200M Series
14.3.2.2.

SX68204M

Conditions: VBB pin voltage = 300 V, half-bridge circuit with inductive load.
Switching Loss, E, is the sum of turn-on loss and turn-off loss.
VB = 15 V

200

VCC = 15 V

200

150

150

TJ =125 °C

E (µJ)E (µJ)

TJ = 125 °C
100
50

100
50

TJ = 25 °C

TJ = 25 °C
0

0
0.0

0.5

1.0

1.5

0.0

0.5

ID (A)

Figure 14-15.

14.3.2.3.

1.0

1.5

ID (A)

High-side Switching Loss

Figure 14-16.

Low-side Switching Loss

SX68205M

Conditions: VBB pin voltage = 300 V, half-bridge circuit with inductive load.
Switching Loss, E, is the sum of turn-on loss and turn-off loss.
VB = 15 V

200

VCC = 15 V

200

150

150

TJ =125 °C

E (µJ)E (µJ)

TJ = 125 °C
100
50

100
50

TJ = 25 °C

TJ = 25 °C

0

0
0.0

0.5

1.0

1.5

2.0

0.0

0.5

ID (A)

Figure 14-17.

High-side Switching Loss

1.0

1.5

2.0

ID (A)

Figure 14-18.

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Low-side Switching Loss

65

SX68200M Series
15. Pattern Layout Example
This section contains the schematic diagrams of a PCB pattern layout example using an SX68200M series device.
Note that the pattern layout example only uses the parts illustrated in the circuit diagram below. For details on the landpattern example of the IC, see Section 9.

(Top View)(Bottom View)
Figure 15-1. Pattern Layout Example

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SX68200M Series
D2

D1
IC1

CN1 F1
3
2 CX0

L1

RC1

TH0

2 AC1 DC 1
3 AC2 GND 4

RD0
CY2

CY1

R1

C6
L2

R4 D4

C4

R5 R6 R7 R8 R9 LED1

DC-Link
IPM1
1 VCC1 VBB 36
W1 34
2 RESETn
3 DIR
VB3 334 VSP
VB2 32

R101

R117

C106

C105

C104

C5

R3

D3

3
2
1

1
Frame ground

C3

R2

1 FB
SGND 82 VCC SGND 7
SGND 6
4 DST SGND 5

R105

R102
R103

V1 31

CN3

R106
R116
R104

9 COM

RESET

8
7
6

JP1

10 V3

V3

U 27
LS1 26
VB1 25

CN2
C101

3
2
1

V2 23

12 FG

R115

R110

R109

C111
C112

C110

C109

VBB 2911 VPP

TP9

R119

C108

5
4
3
2

3
4
5

C103

1
2
6

5 VM
6 TEST
7 SCL
8 SDA

C102

VSP_VR

13 DIAGLS2 21
14 CSCOM LS3 20
15 CSW
W2 19

Q1

1

CN4
1
2
3
4
5
6

16 CSV
17 CSUR203

18 VCC2

R202

C207 C206 C205

C204

C202 C201

R114
R121 R120

V3

C116

11 CTS
GND 1812 CBUS4 3V3OUT 17
13 CBUS2 USBDM 16
14 CBUS3 USBDP 15

RS3 RS2 RS1 C100

DIR SW

C107 R107

GND 21
VCC 20RESET 19

C113 C114 C115

C117 R108

9 DSR
10 DCD

JP2

R201

7 GND

R113

LED2

1
2
3
4
5
6

R112

R205

USB_Micro

5 RXD
6 RI

R111

OSCO 28OSCI 27
TEST 26
GND 25
CBUS0 23
CBUS1 22

LED3

1 TXD
2 DTR
3 RTS
4 VCCIO

R204

C203

IC2

LED4

Figure 15-2. Circuit Diagram of PCB Pattern Layout Example

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67

SX68200M Series
16. Typical Motor Driver Application
This section contains the information on the typical motor driver application listed in the previous section, including
a circuit diagram, specifications, and the bill of the materials used.
● Motor Driver Specifications
IC
Main Supply Voltage, VDC
Rated Output PowerSX68205M
280 VDC (typ.)30 W● Circuit Diagram
See Figure 15-2.

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68

SX68200M Series● Bill of Materials
SymbolPart Type
C3Electrolytic
C4Electrolytic
C5Electrolytic
C6
Ceramic
C100
Film
C101
Ceramic
C102
Ceramic
C103
Ceramic
C104
Electrolytic
C105
Ceramic
C106
Ceramic
C107
Ceramic
C108*
Ceramic
C109
Ceramic
C110
Ceramic
C111
Ceramic
C112
Ceramic
C113
Ceramic
C114
Ceramic
C115
Ceramic
C116
Ceramic
C117
Ceramic
C201*
Ceramic
C202*
Ceramic
C203
Ceramic
C204
Ceramic
C205
Ceramic
C206
Ceramic
C207
Ceramic
CX0
Film
CY1
Ceramic
CY2
Ceramic
R1
GeneralR2
GeneralR3
GeneralR4
GeneralRatings
120 μF, 400 V
100 μF, 25 V
10 μF, 50 V
0.22 μF, 50 V
0.047 μF, 400 V
1 μF, 50 V
1 μF, 50 V
1 μF, 50 V
100 μF, 25 V
1 μF, 50 V
1 μF, 50 V
100 pF, 50 VOpen
0.1 μF, 50 V
1 μF, 50 V
0.1 μF, 50 V
0.1 μF, 50 V
1000 pF, 50 V
1000 pF, 50 V
1000 pF, 50 V
100 pF, 50 V
100 pF, 50 V
Open
Open
0.1 μF, 50 VOpen
1 μF, 50 V
0.1 μF, 50 V
Open
22 nF, 275 VAC
4.7 nF, 250 VAC
4.7 nF, 250 VAC
10 kΩ, 0.25 W
47 kΩ, 0.25 W
4.7 kΩ, 0.25 W
4.7 kΩ, 0.25 W

Symbol
R109*
R110
R111
R112
R113
R114
R115
R116
R117
R119
R120
R121
R201
R202
R203
R204
R205
RS1*
RS2*
RS3*
RD0
TH0
VSP_VR
D1
D2
D3
D4
L1
L2
F1
LED1
LED2
LED3
LED4
RESET
DIR SW

R5

General

33 kΩ, 0.25 W

USB_Micro

R6
R7
R8
R9
R101
R102
R103
R104
R105
R106
R107
R108

GeneralGeneralGeneralGeneralMetal plate
Metal plate
Metal plate
Metal plate
GeneralGeneralGeneralGeneral

33 kΩ, 0.25 W
33 kΩ, 0.25 W
33 kΩ, 0.25 W
33 kΩ, 0.25 W
1 MΩ, 0.25 W
1 MΩ, 0.25 W
1 MΩ, 0.25 W
10 kΩ, 0.25 W
47 kΩ, 0.25 W
5.6 kΩ, 0.25 W
10 kΩ, 0.25 W
10 kΩ, 0.25 W

CN1
CN2
CN3
CN4
DC-Link
RC1
Q1
IPM1
IC1
IC2
JP1
JP2

Part Type
GeneralGeneralGeneralGeneralGeneralGeneralGeneralGeneralGeneralGeneralGeneralGeneralGeneralGeneralGeneralGeneralGeneralMetal plate
Metal plate
Metal plate
Metal plate
Thermistor
Trimmer
Fast recovery
Fast recovery
Fast recovery
Zener diode
FilterInductor
Fuse
LED
LED
LED
LED
SwitchSwitchMicro USB
Type-bconnector
Connector
Connector
Pin header
Pin header
Connector
Bridge diodeNPN transistor
IC
IC
IC
JumperJumperRatingsOpen
10 kΩ, 0.25 W
100 Ω, 0.25 W
100 Ω, 0.25 W
100 Ω, 0.25 W
10 kΩ, 0.25 W
10 kΩ, 0.25 W
2.2 kΩ, 0.25 W
Open
3.3 kΩ, 0.25 W
10 kΩ, 0.25 W
10 kΩ, 0.25 W
1 kΩ, 0.25 W
100 Ω, 0.25 W
Open100 Ω, 0.25 W
1 kΩ, 0.25 W
0.36 Ω, 1 W
0.36 Ω, 1 W
0.36 Ω, 1 W
1 MΩ, 1 W
10 Ω, 1800 mW
20 kΩ, 0.5 W
200 V, 1 A
500 V, 1 A
500 V, 1 A
1 W, Vz = 18.8 V (min.)74.5 mH
1 mH
250 VAC, 1 A
5 V, 30 mA
5 V, 30 mA
5 V, 30 mA
5 V, 30 mA
TS-AGGNH-G
1MS1-T2-B1-M1-Q-N-S
ZX62-B-5PA
Equiv. to B2P3-VH
Equiv. to B3P5-VH
2.54 mm pitch
2.54 mm pitch
Equiv. to B2P3-VH
D3SBA60
Open
SX68205M
STR5A464D
FT232RL
Short
Short

* Refers to a part that requires adjustment based on operation performance in an actual application.

SX68200M-DSE Rev.2.1
SANKEN ELECTRIC CO., LTD.
May 19, 2023
https://www.sanken-ele.co.jp/en© SANKEN ELECTRIC CO., LTD. 2019

69

SX68200M Series
Important Notes● All data, illustrations, graphs, tables and any other information included in this document (the “Information”) as to Sanken’s
products listed herein (the “Sanken Products”) are current as of the date this document is issued. The Information is subject to any
change without notice due to improvement of the Sanken Products, etc. Please make sure to confirm with a Sanken sales
representative that the contents set forth in this document reflect the latest revisions before use.
● The Sanken Products are intended for use as components of general purpose electronic equipment or apparatus (such as home
appliances, office equipment, telecommunication equipment, measuring equipment, etc.). Prior to use of the Sanken Products,
please put your signature, or affix your name and seal, on the specification documents of the Sanken Products and return them toSanken. When considering use of the Sanken Products for any applications that require higher reliability (such as transportationequipment and its control systems, traffic signal control systems or equipment, disaster/crime alarm systems, various safety
devices, etc.), you must contact a Sanken sales representative to discuss the suitability of such use and put your signature, or affix
your name and seal, on the specification documents of the Sanken Products and return them to Sanken, prior to the use of theSanken Products. The Sanken Products are not intended for use in any applications that require extremely high reliability such as:
aerospace equipment; nuclear power control systems; and medical equipment or systems, whose failure or malfunction may result
in death or serious injury to people, i.e., medical devices in Class III or a higher class as defined by relevant laws of Japan(collectively, the “Specific Applications”). Sanken assumes no liability or responsibility whatsoever for any and all damages andlosses that may be suffered by you, users or any third party, resulting from the use of the Sanken Products in the Specific
Applications or in manner not in compliance with the instructions set forth herein.
● In the event of using the Sanken Products by either (i) combining other products or materials or both therewith or (ii) physically,
chemically or otherwise processing or treating or both the same, you must duly consider all possible risks that may result from all
such uses in advance and proceed therewith at your own responsibility.
● Although Sanken is making efforts to enhance the quality and reliability of its products, it is impossible to completely avoid theoccurrence of any failure or defect or both in semiconductor products at a certain rate. You must take, at your own responsibility,
preventative measures including using a sufficient safety design and confirming safety of any equipment or systems in/for which
the Sanken Products are used, upon due consideration of a failure occurrence rate and derating, etc., in order not to cause any
human injury or death, fire accident or social harm which may result from any failure or malfunction of the Sanken Products.
Please refer to the relevant specification documents and Sanken’s official website in relation to derating.
● No anti-radioactive ray design has been adopted for the Sanken Products.
● The circuit constant, operation examples, circuit examples, pattern layout examples, design examples, recommended examples, allinformation and evaluation results based thereon, etc., described in this document are presented for the sole purpose of reference ofuse of the Sanken Products.
● Sanken assumes no responsibility whatsoever for any and all damages and losses that may be suffered by you, users or any third
party, or any possible infringement of any and all property rights including intellectual property rights and any other rights of you,users or any third party, resulting from the Information.
● No information in this document can be transcribed or copied or both without Sanken’s prior written consent.
● Regarding the Information, no license, express, implied or otherwise, is granted hereby under any intellectual property rights andany other rights of Sanken.
● Unless otherwise agreed in writing between Sanken and you, Sanken makes no warranty of any kind, whether express or implied,
including, without limitation, any warranty (i) as to the quality or performance of the Sanken Products (such as implied warrantyof merchantability, and implied warranty of fitness for a particular purpose or special environment), (ii) that any Sanken Product isdelivered free of claims of third parties by way of infringement or the like, (iii) that may arise from course of performance, courseof dealing or usage of trade, and (iv) as to the Information (including its accuracy, usefulness, and reliability).
● In the event of using the Sanken Products, you must use the same after carefully examining all applicable environmental laws andregulations that regulate the inclusion or use or both of any particular controlled substances, including, but not limited to, the EU
RoHS Directive, so as to be in strict compliance with such applicable laws and regulations.
● You must not use the Sanken Products or the Information for the purpose of any military applications or use, including but notlimited to the development of weapons of mass destruction. In the event of exporting the Sanken Products or the Information, or
providing them for non-residents, you must comply with all applicable export control laws and regulations in each country
including the U.S. Export Administration Regulations (EAR) and the Foreign Exchange and Foreign Trade Act of Japan, andfollow the procedures required by such applicable laws and regulations.
● Sanken assumes no responsibility for any troubles, which may occur during the transportation of the Sanken Products including
the falling thereof, out of Sanken’s distribution network.
● Although Sanken has prepared this document with its due care to pursue the accuracy thereof, Sanken does not warrant that it iserror free and Sanken assumes no liability whatsoever for any and all damages and losses which may be suffered by you resulting
from any possible errors or omissions in connection with the Information.
● Please refer to our official website in relation to general instructions and directions for using the Sanken Products, and refer to therelevant specification documents in relation to particular precautions when using the Sanken Products.
● All rights and title in and to any specific trademark or tradename belong to Sanken and such original right holder(s).

DSGN-CEZ-16003

SX68200M-DSE Rev.2.1
SANKEN ELECTRIC CO., LTD.
May 19, 2023
https://www.sanken-ele.co.jp/en© SANKEN ELECTRIC CO., LTD. 201970