650 V, 50 A
3-phase Motor Driver

SAM265M50BS3

Data Sheet

Description

Package

The SAM265M50BS3 is a 3-phase brushless motor
driver in which output transistors, a pre-drive circuit,bootstrap diodes with current-limiting resistors, and atemperature-sensing thermistor are highly integrated.
The IC is suitable for driving 3-phase motor of the units
such as industrial equipment.

DIP30 (Leadform: 2541)

Features● Pb-free (RoHS Compliant)● Isolation Voltage: 2500 V (for 1 min)
(UL-recognized Component)● Built-in Thermistor● Built-in Bootstrap Diodes● CMOS-compatible Input (3.3 V or 5 V)
● Fault Signal Output at Protection Activation● Shutdown Signal Input● Adjustable OCP Hold Time
● Protection Functions
Undervoltage Lockout for Power Supply
VBx Pin (UVLO_VBx): Auto-restart
VCCL Pin (UVLO_VCCL): Auto-restart
Overcurrent Protection (OCP): Auto-restart

Not to scale

Specifications● Breakdown Voltage: 650 V● Output Current: 50 A

Applications

Typical Application
VSU
1
VBU
2

VCC

VCCHU

3

High-side
MIC1

INHU

VCCHV

7
INHV
8
VSW
9
VBW
10

Controller

INVH

VCCHW

11

VTH
RTH

Temp.

INUL
INVL

VFO-PU
RFO

Fault

CFO

30

NC
VP

P

● Commercial Air Conditioner Compressor● General-purpose Inverter

CS

High-side
MIC2

28

High-side
MIC3

INHW

INWH

For driving 3-phase motors used in industrial
equipment such as:

U1

29

4
VSV
5
VBV
6

INUH

INWL

SAM265M50BS3

27
26

12
NC 13
TH
14

U
V

M

W

INLU
15
INLV
16
INLW
17
FO
18
CFO
19
OCP 20GND
21
VCCL 22

Low-side
MIC

NU
25
NV
24
23 NW

RS
GND

SAM265M50BS3-DSE Rev.1.1
SANKEN ELECTRIC CO., LTD.
Oct. 24, 2023
https://www.sanken-ele.co.jp/en© SANKEN ELECTRIC CO., LTD. 2021

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SAM265M50BS3
Contents
Description ------------------------------------------------------------------------------------------------------ 1
Contents --------------------------------------------------------------------------------------------------------- 2
1. Introduction ------------------------------------------------------------------------------------------------ 4
2. Absolute Maximum Ratings----------------------------------------------------------------------------- 4
3. Recommended Operating Conditions ----------------------------------------------------------------- 6
4. Electrical Characteristics -------------------------------------------------------------------------------- 7
4.1. Characteristics of Control Parts------------------------------------------------------------------ 7
4.2. Bootstrap Diode Characteristics ----------------------------------------------------------------- 9
4.3. Thermistor Characteristics ---------------------------------------------------------------------- 10
4.4. Thermal Resistance Characteristics ----------------------------------------------------------- 12
4.5. Transistor Characteristics ----------------------------------------------------------------------- 13
5. Mechanical Characteristics --------------------------------------------------------------------------- 14
6. Insulation Distance -------------------------------------------------------------------------------------- 14
7. Truth Table ----------------------------------------------------------------------------------------------- 15
8. Block Diagram ------------------------------------------------------------------------------------------- 16
9. Pin Configuration Definitions ------------------------------------------------------------------------- 18
10. Typical Application ------------------------------------------------------------------------------------- 19
11. Physical Dimensions ------------------------------------------------------------------------------------ 20
11.1. DIP30 (Leadform: 2541) ------------------------------------------------------------------------- 20
11.2. Reference PCB Hole Sizes ----------------------------------------------------------------------- 21
12. Marking Diagram --------------------------------------------------------------------------------------- 21
13. Functional Descriptions -------------------------------------------------------------------------------- 22
13.1. Turning On and Off the IC ---------------------------------------------------------------------- 22
13.2. Pin Descriptions ----------------------------------------------------------------------------------- 22
13.2.1. P ---------------------------------------------------------------------------------------------- 22
13.2.2. U, V, and W----------------------------------------------------------------------------------- 22
13.2.3. NU, NV, and NW ---------------------------------------------------------------------------- 22
13.2.4. VBU, VBV, and VBW ---------------------------------------------------------------------- 22
13.2.5. VSU, VSV, and VSW ----------------------------------------------------------------------- 23
13.2.6. VCCHU, VCCHV, VCCHW, and VCCL ---------------------------------------------- 23
13.2.7. GND -------------------------------------------------------------------------------------------- 24
13.2.8. INHU, INHV, and INHW; INLU, INLV, and INLW -------------------------------- 24
13.2.9. OCP -------------------------------------------------------------------------------------------- 24
13.2.10. CFO -------------------------------------------------------------------------------------------- 25
13.2.11. FO ---------------------------------------------------------------------------------------------- 25
13.2.12. TH ---------------------------------------------------------------------------------------------- 25
13.3. Protection Functions ------------------------------------------------------------------------------ 26
13.3.1. Fault Signal Output ------------------------------------------------------------------------- 26
13.3.2. Shutdown Signal Input --------------------------------------------------------------------- 26
13.3.3. Undervoltage Lockout for Power Supply (UVLO) ----------------------------------- 27
13.3.4. Overcurrent Protection (OCP) ----------------------------------------------------------- 28
14. Design Notes ---------------------------------------------------------------------------------------------- 30
14.1. PCB Pattern Layout ------------------------------------------------------------------------------ 30
14.2. Considerations in Heatsink Mounting -------------------------------------------------------- 30
14.3. Considerations in IC Characteristics Measurement --------------------------------------- 31
15. Calculating Power Losses and Estimating Junction Temperature ---------------------------- 32
15.1. IGBT Steady-state Loss, PON -------------------------------------------------------------------- 32
15.2. IGBT Switching Loss, PSW ----------------------------------------------------------------------- 32

SAM265M50BS3-DSE Rev.1.1
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SAM265M50BS3
15.3. Estimating Junction Temperature of IGBT -------------------------------------------------- 32
16. Performance Curves ------------------------------------------------------------------------------------ 33
16.1. Transient Thermal Resistance Curves -------------------------------------------------------- 33
16.2. Performance Curves of Output Parts --------------------------------------------------------- 34
16.2.1. Output Transistor Performance Curves ------------------------------------------------ 34
16.2.2. Switching Loss Curves --------------------------------------------------------------------- 34
16.3. Allowable Effective Current Curves ----------------------------------------------------------- 35
Important Notes ---------------------------------------------------------------------------------------------- 36

SAM265M50BS3-DSE Rev.1.1
SANKEN ELECTRIC CO., LTD.
Oct. 24, 2023
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SAM265M50BS3
1.

Introduction

For pin descriptions, this docment employs a notation system that denotes a pin name with the arbitrary letter “x”,
depending on context. The U-, V-, and W-phase (3-phases) output pins are represented as the pin numbers U, V, and W,
respectively. Thus, “the VBx pin” is used when referring to any or all of the VBU, VBV, and VBW pins. Whendifferent pin names are mentioned as a pair (e.g., “the VBx and VSx pins”), they are meant to be the pins in the same
phase. Also, “the OUTx pin” is used when referring to any or all of the output pins (U, V, and W).
Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).

2.

Absolute Maximum Ratings
Unless specifically noted, TA = 25 °C.
Parameter

SymbolConditions

Ratings

Unit

Inverter Stage
Main Supply Voltage (DC)

VP(DC)

P–Nx

500

V

Main Supply Voltage (Surge)
Collector-to-Emitter Voltage(Surge)Collector-to-Emitter Voltage

VP(SURGE)

P–Nx

550

V

VCE(SURGE)

P–OUTx, OUTx–Nx

550

V

VCES

Built-in IGBT chip

650

V

IC

TC = 25 °C

50

A

100

A

125

W

62.5

W

Nx–GND−5 to 5

V

Collector Current(1)Collector Current (Peak)Power Dissipation

Power Dissipation

ICP

PC

TC = 25 °C,
Pulse width < 1 ms,
Duty cycle < 1%
TC = 25 °C, 1 element
operating (IGBT)
TC = 25 °C, 1 element
operating (freewheeling
diode)

Control Parts
Nx Pin Voltage

VNx

VCCHx Pin Voltage

VVCCHx

VCCHx–GND−0.5 to 25

V

VCCL Pin Voltage

VVCCL

VCCL–GND−0.5 to 25

V

VBx-VSx Pin Voltage

VVBx-VSxVBx–VSx−0.5 to 25

V

INHx Pin Voltage

VINHx

INHx–GND−0.5 to VVCCHx + 0.3

VINLx Pin Voltage

VINLx

INLx–GND−0.5 to VVCCL + 0.3

V

FO Pin Voltage

VFO

FO–GND−0.5 to VVCCL + 0.3

V

FO Pin Sink Current

IFO

1

mA

OCP Pin Voltage
Change Rate of VCC Supply
Voltage Time

VOCP

−0.5 to VVCCL + 0.3

V−1 to 1

V/μs

(1)

OCP–GNDΔVVCC/Δt

Should be derated depending on an actual case temperature.

SAM265M50BS3-DSE Rev.1.1
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SAM265M50BS3
Parameter

SymbolConditions

Ratings

Unit

VR-BS

650

V

TTH

−40 to 150°C

Thermistor Allowable Current

ITH-MAX

1.8

mA

Thermistor Allowable Power

PTH-MAX

200mW

IGBTs and freewheeling
diodesControl MICs

−40 to 150°C−40 to 150°C

For measurement point, see−40 to 125°C−40 to 150

°C

2500

V

Bootstrap Circuit
Bootstrap Diode Reverse Voltage
Thermistor
Operating Thermistor Temperature

CommonJunction Temperature

TJ

Operating Case Temperature(2)TC

Storage Temperature

TSTG

Isolation Voltage(3)

(2)
(3)

VISO(RMS)

Figure 2-1.
Between surface of heatsinkside and each pin;AC, 60 Hz, 1 min

Refers to a case temperature measured during IC operation.
Refers to voltage conditions to be applied between all of the pins and the case. All the pins have to be shorted.
21.6 mm2330

15.5 mm22

1

Measurement point

Figure 2-1.

Case Temperature Measurement Point

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SAM265M50BS3
3.

Recommended Operating Conditions

Unless specifically noted, TC = −40 °C to 125 °C, VP(DC) = 300 V, VVCCHx = VVCCL = 15 V, RFO = 10 kΩ, CFO = 0 μF,
VFO-PU = 5 V.
Min.
Typ.
Max.
Unit
Parameter
SymbolConditions
Main Supply Voltage (DC)

VP(DC)

P–Nx

150

300

450

V

VCCHx Pin Voltage

VVCCHx

VCCHx–GND

13.5

15.0

16.5

V

VCCL Pin Voltage

VVCCL

VCCL–GND

13.5

15.0

16.5

V

VBx-VSx Pin Voltage

VVBx-VSxVBx–VSx

13.0

15.0

18.5

V

Dead Time of Input SignaltDEAD

INHx, INLx

2.0

—

—

μs

PWM Control Frequency

fPWM

5

10

20

kHz

INxH Pin Input Pulse Width (On)tINHX(ON)

1.5

—

—

μs

INxH Pin Input Pulse Width (Off)tINHX(OFF)

1.5

—

—

μs

INxL Pin Input Pulse Width (On)tINLX(ON)

1.5

—

—

μs

INxL Pin Input Pulse Width (Off)tINLX(OFF)

1.5

—

—

μs

0.1

47

—

μF

22

47

—

μF

0.47

1.0

2.2

μF

4.7

10

100

μF

Ceramic capacitor

0.47

1.0

2.2

μF

fPWM = 5 kHz

21

—

—

fPWM = 10 kHz

30

—

—

fPWM = 15 kHz

39

—

—

fPWM = 20 kHz

48

—

—

IZ = 1 mA

16.5

18.2

20.0

V

P Pin Capacitor

CS

VCCHx/VCCL Pin Capacitor 1

CVCC1

VCCHx/VCCL Pin Capacitor 2

CVCC2

Bootstrap Capacitor 1

CBS1

Bootstrap Capacitor 2

CBS2

External VCC Supply Output Current

VCCxH/VCCL Pin Zener Diode
Breakdown Voltage

Ceramic capacitor

Ceramic capacitor

IVCC

VZ-DVCCmA

FO Pin Pull-up Resistor

RFO

5.5

10.0

33.0

kΩ

FO Pin Pull-up Voltage

VFO_PU

3.0

5.0

5.5

V

FO Pin Capacitor

CFO

—

1000

3300

pF

CFO Pin Capacitor

CCFO

0.01

0.10

1.00

μF

Shunt Resistor*RS

OCP operating current:
50 A to 100 A

5.4

7.3

9.2

mΩ

OCP RC Filter Time ConstanttRFCF

tRFCF = RF × CF

0.5

1.0

1.5

μs

Thermistor Operating Current

ITH

—

—

0.2

mA

*

Should be a low-inductance resistor.

SAM265M50BS3-DSE Rev.1.1
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SAM265M50BS3
4.

Electrical Characteristics
Unless specifically noted, TA = 25 °C, VVCCHx = VVCCL = 15 V, RFO = 10 kΩ, CFO = 0 μF, VFO-PU = 5 V.

4.1.

Characteristics of Control Parts

Parameter
Power Supply Operation

SymbolVCCL Pin Operating Voltage

Conditions

Min.

Typ.

Max.

Unit

VVCCL_H

11.2

12.6

13.3

V

VCCL Pin Operating Stop
Voltage
VCCL Pin Hysteresis

VVCCL_L

10.7

12.1

12.8

V

VVCCL_HYS

—

0.5

—

V

VBx−VSx Operating Voltage

VVBx-VSx_H

11.0

12.1

12.8

V

VBx−VSx Operating Stop
VoltageVBx−VSx Hysteresis

VVBx-VSx_L

10.5

11.6

12.3

V

VVBx-VSx_HYS

0.5

—

V

VCCHx Pin Input Current

IVCCHX

1.4

2.0

1.4

2.0

VCCL Pin Input Current

IVCCL

—
—
—
—
—

1.9

3.2

1.9

3.2

—

0.09

0.30

VBx−VSx Pin Input Current

IVBx-VSx

—

0.11

0.30

—

2.0

2.5

V

1.0

1.5

—

V

—

0.5

—

V

—

2.0

2.5

V

1.0

1.5

—

V

—
—
—

0.5

—

V

0.25

0.50

mA

0.25

0.50

mA

—

2.0

2.5

V

1.0

1.5

—

V

—

0.5

—

V

4.8

5.0

—

V

—

0.05

0.50

V

VINHx = 0 V, each pin
VINHx = 5 V, each pin
VINLx = 0 V
VINLx = 5 V
VVBx-VSx = 15 V,
VINHx = 0 V;
1-phase operation
VVBx-VSx = 15 V,
VINHx = 5 V;
1-phase operation

Input Signal
INHx Pin High-level Input
VINHx_HThreshold Voltage
INHx Pin Low-level Input
VINHx_L
Threshold Voltage
VINHx_HYS
INHx Pin Hysteresis
INLx Pin High-level Input
VINLx_HThreshold Voltage
INLx Pin Low-level Input
VINLx_L
Threshold Voltage
VINLx_HYS
INLx Pin Hysteresis
IINHx
VINHx = 5 V, each pin
INHx Pin Input Current
IINLx
VINLx = 5 V, each pin
INLx Pin Input Current
Fault Signal Output, Shutdown Signal Input
FO Pin Shutdown Release
VFO_H
Voltage
FO Pin Shutdown Threshold
VFO_L
Voltage
VFO_HYSFO Pin Shutdown Hysteresis
FO Pin Output Voltage inNormal Operation

VFO(OUT)_H

FO Pin Error Signal Output
Voltage

VFO(OUT)_L

VFO_PU = 5 V,
RFO = 10 kΩ,
VOCP = 0 V
VFO_PU = 5 V,
RFO = 10 kΩ,
VOCP = 1 V

Remarks
Recovering voltage
from UVLO
UVLO detection
voltage
Recovering voltage
from UVLO
UVLO detection
voltage

mA
mA

mA

SAM265M50BS3-DSE Rev.1.1
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SAM265M50BS3
Parameter

FO Pin OCP Hold Time

SymbolConditions
CCFO = 0 μF
CCFO = 0.001 μF
CCFO = 0.01 μF
CCFO = 0.1 μF
CCFO = 1 μF

Min.

Typ.

Max.

Unit

0.012

0.030

0.060

ms

0.20

0.32

0.44

ms

2.0

3.2

4.4

ms

20

32

44

ms

200

320

440

ms

VOCP_H

0.46

0.50

0.54

V

VOCP_L

0.32

0.38

0.44

V

VOCP_HYS

—

0.12

—

V

—
—
—

0.7
0.3
0

1.5
0.5
—

μs
μs
mA

(1)

tFO

Protection
OCP Pin Overcurrent Detection
Voltage
OCP Pin Overcurrent Release
Voltage
OCP Pin Overcurrent
Hysteresis
OCP Pin Detection Delay TimeOCP Pin Filter Time(3)OCP Pin Input Current

tOCP_DELAY(2)tOCP_FILTERIOCP

VOCP = 0.5 V

Remarks

The shipping test is performed with the condition at CCFO = 0.01 μF only.
For the measurement circuit for the OCP Pin Detection Delay Time, see Figure 4-1 (all the pins that are notrepresented in the figure are open). Figure 4-2 provides the definition of the OCP Pin Detection Delay Time.
(3)
Guaranteed by design.
(1)
(2)

INLU
15
10 k

5V

FO
18
VCCL
22
OCP
20

15 V

0 1V

GND
21

U1
28

U 10

1V

OCP
50%

15 V

0

FO

25
24

NU
0

NV

23 NW

tOCP_DELAY
15 V

U

50%
0

Figure 4-1.

Measurement Circuit for OCP Pin
Detection Delay Time

Figure 4-2.

OCP Pin Detection Delay Time Definition

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SAM265M50BS3
4.2.

Bootstrap Diode Characteristics
Parameter

SymbolBootstrap Diode
Forward Voltage Drop

VF_BS

Bootstrap Diode
Series Resistor** Guaranteed by design.

Conditions

Min.

Typ.

Max.

Unit

Remarks

IF_BS = 0.01 A

0.4

0.9

1.4

V

IF_BS = 0.1 A

2.0

3.0

4.0

V

Including voltage
drop of series
resistor

12

20

28

Ω

RS_BS

1.4

Average Forward Current, IF (A)

1.2
1.0
0.8
0.6
0.4
0.2
0.0
0

5

10

15

20

25

Forward Voltage, VF (V)Figure 4-3.

Bootstrap Diode Typical Characteristics: IF vs. VF (TJ = 25 °C)

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SAM265M50BS3
4.3.

Thermistor Characteristics
Parameter

Thermistor Resistance

Symbol(1)(2)

Thermistor B Constant(1)R25

Conditions

Min.

Typ.

Max.

Unit

—

100.0

—

kΩ

—

4395

—

K

TA = 25 °C
TTH = 25 °C,
85 °C

B25-85

Remarks* Guaranteed by design.

Thermistor Resistance (kΩ)

10000

1000

100

10

1

0.1
-40 -30 -20 -10

0

10

20

30

40

50

60

70

80

90 100 110 120 130 140 150

Thermistor Temperature (℃)

Figure 4-4.

(1)
(2)

Reference Thermistor Resistance

Guaranteed by design.
For the reference thermistor resistance, see Figure 4-4 and Table 4-1.

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SAM265M50BS3

Table 4-1. Reference Thermistor Resistance
Thermistor Temperature
(°C)
−40
−35
−30
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100

Thermistor Resistance Typ.
(kΩ)
5427
3748
2619
1850
1321
954
696
513
382
287
218
166
128
100
78.4
62.0
49.4
39.6
32.0
26.0
21.3
17.5
14.5
12.0
10.1
8.46
7.15
6.07
5.17

Thermistor Temperature
(°C)
105
110
115
120
125
130
135
140
145
150

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Thermistor Resistance Typ.
(kΩ)
4.43
3.81
3.29
2.85
2.48
2.17
1.90
1.67
1.47
1.30

11

SAM265M50BS3
4.4.

Thermal Resistance Characteristics
Parameter

SymbolR(J-C)Q(3)Junction-to-Case Thermal Resistance(1)(2)

R(J-C)F(4)Conditions
1 element operating(IGBT)
1 element operating(freewheeling diode)

Min.

Typ.

Max.

Unit

—

—

1.0

°C/W

—

—

2.0

°C/W

(1)

Guaranteed by design.
Refers to a case temperature at the measurement point described in Figure 4-5.
(3)
Refers to steady-state thermal resistance between the junction of the built-in IGBTs and the case.
(4)
Refers to steady-state thermal resistance between the junction of the built-in freewheeling diodes and the case.
(2)

22.3 mm21.6 mm15.5 mm

23

30

22

1
IGBT measurement point

10.5 mm

Freewhelingdiode measurement point

Figure 4-5.

Case Temperature Measurement Point

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SAM265M50BS3
4.5.

Transistor Characteristics

Figure 4-6 provides the definitions of switching characteristics described in this and the following sections.
INHx/
INLx
0

trr
tON

tOFF

IC

90%

10%

0

tC(ON)tC(OFF)

VCE

10%

0

Figure 4-6.
Parameter
Collector-to-Emitter Leakage
Current
Collector-to-Emitter Saturation
Voltage
Diode Forward Voltage Drop
High-side Switching
Diode Reverse Recovery Time*
Turn-on Time*
Turn-on Switching Time*
Turn-off Time*
Turn-off Switching Time*
Low-side Switching
Diode Reverse Recovery Time*
Turn-on Time*
Turn-on Switching Time*
Turn-off Time*
Turn-off Switching Time*

SymbolICES
VCE(SAT)VF
trr
tON
tC(ON)tOFF
tC(OFF)
trr
tON
tC(ON)tOFF
tC(OFF)

Switching Characteristics Definitions
Conditions

Min.

Typ.

Max.

Unit

VCE = 650 V, TJ = 25 °C

—

—

0.1

mA

IC = 50 A, TJ = 25 °C
IC = 50 A, TJ = 125 °C
IF = 50 A, TJ = 25 °C

—
—
—

1.70
2.00
2.0

2.20
2.50
2.5

V
V
V

VDC = 300 V, IC = 50 A,
VIN = 0 ↔ 5 V, TJ = 25 °C;
inductive load

—
—
—
—
—

0.35
0.65
0.15
1.45
0.15

—
—
—
—
—

μs
μs
μs
μs
μs

VDC = 300 V, IC = 50 A,
VIN = 0 ↔ 5 V, TJ = 25 °C;
inductive load

—
—
—
—
—

0.35
0.50
0.20
0.95
0.10

—
—
—
—
—

μs
μs
μs
μs
μs

* Guaranteed by design.

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SAM265M50BS3
5.

Mechanical Characteristics
Parameter

Conditions

Heatsink Mounting Screw
Torque(1)(2)

Flatness of Heatsink Attachment
Area(1)
Package Weight(1)(1)(2)

See Figure 5-1

Min.

Typ.

Max.

Unit

0.64

0.80

0.96

N∙m

6.6

8.2

9.8

kgf∙cm

0

—

100

μm

—

23

—

g

Guaranteed by design.
Requires using a metric screw of M3 and a plain washer of 7 mm (φ). For more details about screw tightening, see
Section14.2.
Heatsink+-

Heatsink

Measurement position-+

Figure 5-1.

6.

Insulation DistanceParameter

Clearance(1)

Creepage(1)(2)(1)(2)

Flatness Measurement Position

Conditions

Min.

Typ.

Max.

Unit

Between heatsink andleads. See Figure 6-1.

3.0

3.1

—

mm

4.2

4.6

—

mm

Guaranteed by design.
Refers to when a heatsink to be mounted is flat. If your application requires a clearance exceeding the maximum
distance given above, use an alternative (e.g., a convex heatsink) that will meet the target requirement.

Creepage
Clearance

Heatsink

Figure 6-1.

Insulation Distance Definitions

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SAM265M50BS3
7.

Truth Table

Table 7-1 is a truth table that provides the logic level definitions of operation modes.
In the case where INHx and INLx signals in each phase are high at the same time, both the high- and low-side IGBTs
become on (simultaneous on-state). Therefore, the input signals for the INHx and INLx pins, require dead time setting
so that such a simultaneous on-state event can be avoided.
Table 7-1. Truth Table for Operation Modes
Mode

Normal Operation

External Shutdown Signal Input
FO = LVBx Pin Undervoltage Lockout
Operation (UVLO_VBx)

VCCL Pin Undervoltage Lockout
Operation (UVLO_VCCL)

Overcurrent Protection (OCP)

INHx
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

INLx
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

High-side IGBT
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON

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Low-side IGBT
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF

FO Pin Output

H

―

H

L

L

15

SAM265M50BS3
8.

Block Diagram

Figure 8-1 shows a block diagram, Figure 8-2 to Figure 8-4 show the internal circuit diagrams of the INHx or INLx
pin, the FO pin, and the OCP pin.
30 NC
29 P

VSU 1
VBU 2

VCCHU 3

UVLO

U-phaseHigh-side IC

INHU 4High-side
Input Logic

Level
Shift

VCCHV 7

UVLO

V-phaseHigh-side IC

INHV 8High-side
Input Logic

Level
Shift

VCCHW 11

UVLO

W-phaseHigh-side IC

INHW 12High-side
Input Logic

Level
Shift

UVLO
High-side
Driver

HOU

28 U

VSV 5
VBV 6
UVLO
High-side
Driver

27 V

HOV

VSW 9
VBW 10UVLO
High-side
Driver

26 W

HOW

NC 13
Thermistor
TH 14
UVLO
INLU 15INLV 16
INLW 17

LOU

Low-side
Input Logic

LOV
LOW

Low-side
DriverFO 18

CFO 19OCP 20
GND 21

25 NU
24 NV
23 NW
OCP
Low-side ICPower side

VCCL 22

Figure 8-1.

Block Diagram

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SAM265M50BS3
VCCHx
VCCL

VCCL 22

5V

1M
INHx
INLx

FO 18

30 k

50

40 k

+
-

+
-

10 k
GND 21

GND 21Figure 8-2. Internal Circuit Diagram of INHx, or INLx Pin

Figure 8-3.

Internal Circuit Diagram of FO Pin

VCCL 2240 k
OCP 20+-200 k

GND 21Figure 8-4.

Internal Circuit Diagram of OCP Pin

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SAM265M50BS3
9.

Pin Configuration Definitions
Top View (Heatsink Side)
130
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13*
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Pin Name
VSU
VBU
VCCHU
INHU
VSV
VBV
VCCHV
INHV
VSW
VBW
VCCHW
INHW
NC
TH
INLU
INLV
INLW
FO
CFO
OCP
GND
VCCL
NW
NV
NU
W
V
U
P
NC

Bottom View (Branding Side)
22

22

23

23

1

30

Description
U-phase high-side floating supply groundU-phase high-side floating supply voltage input
U-phase high-side logic supply voltage input
Logic input for U-phase high-side gate driver
V-phase high-side floating supply groundV-phase high-side floating supply voltage input
V-phase high-side logic supply voltage input
Logic input for V-phase high-side gate driver
W-phase high-side floating supply groundW-phase high-side floating supply voltage input
W-phase high-side logic supply voltage input
Logic input for W-phase high-side gate driver(No connection)
Thermistor output
Logic input for U-phase low-side gate driver
Logic input for V-phase low-side gate driver
Logic input for W-phase low-side gate driver
Fault signal output and shutdown signal input
Capacitor connection for OCP hold time setting
Input for overcurrent protection
Logic groundLow-side logic supply voltage input
W-phase low-side IGBT emitter
V-phase low-side IGBT emitter
U-phase low-side IGBT emitter
W-phase output
V-phase output
U-phase output
Positive DC bus supply voltage(No connection)* Pin trimmed.

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SAM265M50BS3
10. Typical Application
CR filters and Zener diodes should be added to your application as needed. This is to protect each pin against surge
voltages causing malfunctions, and to avoid the IC being used under the conditions exceeding the absolute maximum
ratings where critical damage is inevitable. Then, check all the pins thoroughly under actual operating conditions toensure that your application works flawlessly.

CBS1(U)

CBS2(U)

VSU
1
VBU
2
VCCHU

CVCC2(HU)

3

CBS2(V)7

INVH

CBS2(W)

Controller

INWH

VCC

VTH

RTH
Temp.

NC
VP

P
CS

High-side
MIC2

28
High-side
MIC3

12

27

26

NC 13
TH
14

U
V

M

W

INLU
15
INLV
16
INLW
17

INUL

INVL
INWL

VFO-PU
RFO
Fault

CFO

INHW

11

30
29

INHV
8
VSW
9
VBW
10

VCCHW
CVCC2(HW)High-side
MIC1

4
VSV
5
VBV
6

VCCHV
CVCC2(HV)

CBS1(W)

SAM265M50BS3

INHU

INUH

CBS1(V)U1

CCFO

CVCC2(L)

FO
18
CFO
19
OCP
20
GND
21
VCCL
22

Low-side
MIC

NU
25
NV
24
NW
23

CVCC1

DVCC

CF

RF

RS

GND

Figure 10-1.

Typical Application

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SAM265M50BS3
11. Physical Dimensions

(1)

4.25

(0.5)

(0.8)

3.6

H

12.7 ± 0.7

(7.3)

(6.3)

11.1. DIP30 (Leadform: 2541)

+0.15
-0.05

8-2.35

8-1.0
A

A

A

(1)

+0.15
-0.05
A

B

C

A = 7.62 ±0.5
B = 6.6 ± 0.5
C = 3.3 ± 0.5

CDetail of I (S = 4:1)

Detail of H (S = 4:1)

R0.2 min.

3.6

2.65

2D matrix
5.6 ± 0.2

46 ±0.15+0.15
0.52 -0.05

52.5 ± 0.3
3.25 ± 0.15

(1.55)

M(2)

3.95 ± 0.3

3.1 ± 0.1

Pin 302.04 ±0.3

Pin 13

F

J

D
D

D

D

D

E
E

D

17.7
35.4 ± 0.4

2 ±0.12.05 ± 0.1(Root of pin)

(Root of pin)

D
D

D

E
E

D
D

17.7

(13.5)M

Pin 22

Pin 1

D = 1.78 ±0.5
E = 4.32 ±0.5

DDD

(φ 3.5)(φ 3.3)E

D

Dambar cutting

D

+0.15
-0.05

0.3 max.

+0.15
21-1 -0.05

1.73

(7.3)

(6.3)

I

12.7 ±0.7

21-0.5(12.78)(17.7)

LK

15.5 ±0.2

0.3 max.

(4.66)

2D matrix(2.72)

G(17.7)

G

5)
0.
(R
2-

35.9 ± 0.7

2 -φ 3.3 ± 0.2

15.5 ±0.2

Pin 23(φ 3.7)
Cross section view G - G

0.3 max.

Enlarged view of K
(S = 4:1)

Enlarged view of L
(S = 4:1)

1.73
Heatsink side2 -φ3.731 ± 0.3(9.21)(2.01)(3.23)

Pin 13
Enlarged view of J (S = 4:1)
4.32

(0 to 5° ) (0 to 5° )1.6

A
(3.23)

1.4 max.

Pin 22

1.75

Pin 1

1

Enlarged view of F (S = 4:1)
Enlarged view of M (S = 4:1)

Pin 30Pin 23NOTES:● Dimensions in millimeters● Pb-free (RoHS compliant)

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SAM265M50BS3
11.2. Reference PCB Hole Sizes
1.25

1.95

0.85

1.35

1.7

2.9

Pins 1 to 22

2.2

3.4

Pins 23 to 30

12. Marking Diagram30
23

Branding Side
1
22
30

23

SAM265M50BS3
JAPAN

1

Part Number

YMDDX

22

Lot Number:
Y is the last digit of the year of manufacture (0 to 9)
M is the month of the year (1 to 9, O, N, or D)
DD is the day of the month (01 to 31)
X is the control number

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SAM265M50BS3
13. Functional Descriptions
Unless specifically noted, this section uses thefollowing definitions:● All the characteristic values given in this section are
typical values.
● In the following functional descriptions, “HOx”
denotes a gate input signal on the high-side IGBT,
whereas “LOx” denotes a gate input signal on the
low-side IGBT.
● For pin and peripheral component descriptions, thissection employs a notation system that denotes a pin
name with the arbitrary letter “x”, depending oncontext. Thus, “RSx” is used when referring to any or
all of the resistors RS1, RS2, and RS3.

13.1. Turning On and Off the IC
The procedures listed below provide recommended
startup and shutdown sequences. To turn on the IC
properly, do not apply any voltage on the INHx andINLx pins until the VCCL pin voltage has reached astable state (VVCCL_H ≥ 13.3 V).
It is required to fully charge bootstrap capacitors,
CBS1(x) and CBS2(x), at startup (see Section 13.2.4).
To turn off the IC, set the INHx and INLx pins tologic low (or “L”), and then decrease the VCCL pin
voltage.

13.2. Pin Descriptions
13.2.1. P
This is the input pin for the main supply voltage, i.e.,
the positive DC bus. All of the IGBT collectors of thehigh-side are connected to this pin. Voltages between
the P and Nx pins should be set within the recommended
range of the main supply voltage, VP(DC), given in
Section 3.
To suppress surge voltages, put a bypass capacitor of≥0.1 µF, CP, near the P pin with a minimal length of
PCB traces to the P pin.

13.2.2. U, V, and W
These pins are the outputs of the three phases, andserve as the connection terminals to the 3-phase motor.
The U, V, and W pins are internally connected to the
VSU, VSV, and VSW pins, respectively.

possible to the IC with a minimum length of traces to theNx and GND pins.

13.2.4. VBU, VBV, and VBW
These are the inputs of the high-side floating power
supplies for the individual phases.
Voltages across the VBx and VSx pins should bemaintained within the defined range (i.e., the VBx–VSx
Pin Voltage, VVBx-VSx) in Section 3.
In each phase, a bootstrap capacitor, CBS1(x), should beconnected between the VBx and VSx pins. For proper
startup, turn on the low-side transistor first, then fully
charge the bootstrap capacitor, CBS1(x). For thecapacitance of the bootstrap capacitors, CBS1(x), choose
the values that satisfy Equations (1) and (2). Note thatcapacitance tolerance and DC bias characteristics must
be taken into account when you choose appropriate
values for CBS1(x).
CBS1(x) (μF) > (63 × fPWM + 69) × t L(OFF) (s)(1)

4.7 μF ≤ CBS1(x) ≤ 100 μF(2)

In Equation (1), let tL(OFF) be the maximum off-time of
the low-side transistor (i.e., the non-charging time ofCBS1(x)), measured in seconds.
Even while the high-side transistor is not on, voltage
across the bootstrap capacitor keeps decreasing due topower dissipation in the IC. When the VBx pin voltage
decreases to VVBx-VSx_L or less, the VBx pin undervoltage
lockout (UVLO_VBx) starts operating (see Section
13.3.3.1). Therefore, actual board checking should bedone thoroughly to validate that voltage across the VBx
pin maintains over 12.3 V (VVBx > VVBx-VSx_L) during a
low-frequency operation such as a startup period.
As Figure 13-1 shows, bootstrap diodes, DB(x), andcurrent-limiting resistors, RB(x), are internally placed inseries between the VCCHx and VBx pins. Time constantfor the charging time of CBS1(x), τ, can be computed by
Equation (3):τ = CBS1(x) × R B(x) ,(3)

where CBS1(x) is the optimized capacitance of thebootstrap capacitor, and RB(x) is the resistance of thecurrent-limiting resistor (20 Ω ± 20%).

13.2.3. NU, NV, and NW
These are the emitter pins of the low-side IGBTs andare externally connected to shunt resistors, RSx.
When connecting a shunt resistor, place it as near as
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SAM265M50BS3

CBS1(U)

VCC

VSU
1
VBU
2

CBS2(U)

VCCHU

CBS1(V)

U1
RB(U)
DB(U)

3

High-side
MIC1

INHx
27

RB(V)
DB(V)

CBS2(V)

VCCHV
7

Reset

High-side
MIC2

0
26

VSW
9
VBW
10

25

CBS1(W) CBS2(W)

GND

VCCL

Set
0

VSV
5
VBV
6

VCCHW

0

P

RB(W)
DB(W)

11

High-side
MIC3

24

V

M

0

W

NU
23
NV
22
21 NW

22

13.2.5. VSU, VSV, and VSW

RS

Figure 13-1.

Bootstrap Circuit

Figure 13-2 shows an internal level-shifting circuit.
And Figure 13-3 shows operational waveforms of thelevel-shifting circuit. A high-side output signal, HOx, is
generated according to an input signal on the INHx pin.
When an input signal on the INHx pin transits from low
to high (rising edge), a “Set” signal is generated. Whenthe INHx input signal transits from high to low (fallingedge), a “Reset” signal is generated. These two signals
are then transmitted to the high-side by the level-shifting
circuit and are input to the SR flip-flop circuit. Finally,
the SR flip-flop circuit feeds an output signal, Q (i.e.,
HOx).
U1

VBx

S
Set
Input
logic

INHx

Q

HOx

R

Pulse
generator Reset

GND 21Figure 13-2.

HOx

Figure 13-3. Operational Waveforms ofLevel-shifting Circuit

Low-side MIC

21

UInternal Level-shifting Circuit

VSx

These pins are the grounds of the high-side floating
power supplies for each phase, and are connected to thenegative nodes of bootstrap capacitors, CBS1(X) andCBS2(X). The VSU, VSV, and VSW pins are internallyconnected to the U, V, and W pins, respectively.

13.2.6. VCCHU, VCCHV, VCCHW, andVCCLThe VCCHU, VCCHV, and VCCHW pins are thepower supply pins for the built-in high-side control
MICs. The VCCL pin is the power supply pin for thebuilt-in low-side control MIC. The VCCHx and VCCL
pins must be externally connected on a PCB because
they are not internally connected. To prevent
malfunction induced by supply ripples or other factors,
connect a capacitor of ≥22 μF (CVCC1) and a capacitor of
0.47 μF to 2.2 μF (CVCC2(L)) between the VCCL and
GND pins with a minimal length of traces. In addition,connect a capacitor of 0.47 μF to 2.2 μF (CVCC2(Hx))
between the VCCHx and GND pins with a minimal
length of traces.
To prevent damage caused by surge voltages, put a
16.5 V to 20 V Zener diode, DVCC, between the VCCLand GND pins.
Voltage to be applied between the VCCHx and GND
pins should be regulated within the recommended
operational range of VVCCHx, given in Section 3. Voltage
to be applied between the VCCL and GND pins should
be regulated within the recommended operational rangeof VVCCL, given in Section 3.

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SAM265M50BS3
13.2.7. GND
This is the logic ground pins for the IC. For proper
control, the control parts of the IC must be connected to
the GND pin. Varying electric potential of the logic
ground can be a cause of improper operations. Therefore,
connect the logic ground as close and short as possible
to a shunt resistor, RS, at a single-point ground (or star
ground) which is separated from the power ground (seeFigure 13-4). Moreover, extreme care should be taken indesigning a PCB so that currents from the power ground
do not affect the GND pin.
U1

VP(DC)

P 29

CS

NU 25
21 GND

NV 24

RS

Here are filter circuit constants for reference:– RINHx, RINLx: 47 Ω to 220 Ω– CINHx, CINLx: 100 pF to 1500 pF
Care should be taken in adding RINHx and RINLx to thetraces. When they are connected to each other, the input
voltage of the INHx and INLx pins becomes slightly
lower than the output voltage of the microcontroller.
Table 13-1. Input Signals for INHx and INLx Pins
Parameter
Input
Voltage
Input Pulse
Width
PWM
CarrierFrequency
Dead TimeHigh Level Signal

Low Level Signal

3 V < VIN < 5 V

0 V < VIN < 0.5 V≥1.5 μs≥1.5 μs

5 kHz ≤ fSW ≤20 kHz≥1.5 μs

NW 23

VCCHx
(VCCL)
OCP

Create a single-point ground(a star ground) near R S, but
keep it separated from thepower ground.

U1

INHx
(INLx)
30 kΩ

Figure 13-4.

Connections to Logic Ground40 kΩ

13.2.8. INHU, INHV, and INHW;
INLU, INLV, and INLW
These are the input pins of the internal motor drivers
for each phase. The INHx pin acts as a high-side
controller; the INLx pin acts as a low-side controller.
Figure 13-5 shows an internal circuit diagram of theINHx or INLx pin. This is a comparator circuit with abuilt-in pull-down resistor.
Input signals across the INHx–GND and the INLx–
GND pins in each phase should be set within the ranges
provided in Table 13-1, below. Note that dead time
setting must be done for INHx and INLx signals because
the IC does not have a dead time generator.
The higher PWM carrier frequency rises, the more
switching loss increases. Hence, the PWM carrier
frequency must be set so that operational casetemperatures and junction temperatures have sufficientmargins against the absolute maximum ranges, specified
in Section 2.
If the signals from the microcontroller become
unstable, the IC may result in malfunctions. To avoid
such malfunctions, set the microcontroller output line
not to have high-impedance outputs. Also, if the tracesfrom the microcontroller to the INHx or INLx pin (orboth) are too long, the traces may be interfered by noise.
Therefore, it is recommended to add an additional filter
near the INHx or INLx pin as needed (see Figure 13-6).

10 kΩ
GND 21Figure 13-5. Internal Circuit Diagram of
INHx or INLx Pin

Input
signal

RINHx(R INLx)

INHx(INLx)CINHx(C INLx)
Controller

Figure 13-6.

U1

Filter Circuit for INHx or INLx Pin

13.2.9. OCP
This pin serves as the input of the overcurrent
protection (OCP) which monitors the currents flowing
through the low-side output transistors. Section 13.3.4
provides further information about the OCP circuit
configuration and its mechanism.

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SAM265M50BS3
13.2.10. CFO

13.2.12. TH

The CFO pin determines the FO Pin OCP Hold Time,tFO, during the overcurrent protection (OCP) operation.
To set tFO, connect a capacitor, CCFO, between the CFO
and GND pins. Figure 13-7 shows how the OCP holdtime, tFO, and the capacitor, CCFO, are related. CCFO
should have a capacitance of 0.01 μF to 1.00 μF.

The SAM265M50BS3 incorporates a thermistor
which monitors the temperatures inside the IC.
Figure 13-9 illustrates an internal circuit diagram of
the TH pin and its peripheral circuit. The both ends ofthe internal thermistor are connected to the TH and
GND pins, respectively.
Connect a noise filter capacitor, CTH, between the TH
and GND pins. CTH should have a capacitance of ≥0.1
μF. Then, place CTH as close as possible to the IC, andconnect it between the pin connected to themicrocontroller and the TH pin with minimizing
respective trace lengths.
In addition, connect the external power supply, V TH_PU,
and the resistor, RTH, to the TH pin. The external power
supply, VTH_PU, should have voltages ranging from 3.0 V
to 5.5 V. Table 13-2 provides the recommended values
for RTH according to the external power supply.

tFO (ms)

1000

100

10

1
0.01

0.10

1.00

CCFO (μF)

Figure 13-7.

CFO Pin Capacitor, CCFO vs. FO Pin OCP
Hold Time, tFO

VTH_PU (3.3 V or 5 V)
U1
RTH

13.2.11. FO

CTH

This pin operates as the fault signal output and the
shutdown signal input. Sections 13.3.1 and 13.3.2
explain the two functions in detail, respectively.
Figure 13-8 illustrates an internal circuit diagram of
the FO pin and its peripheral circuit. Because of its
open-collector nature, the FO pin should be tied by apull-up resistor, RFO, to the external power supply. The
external power supply voltage (i.e., the FO Pin Pull-up
Voltage, VFO_PU) should range from 3.0 V to 5.5 V.
Therefore, it is recommended to use a 5.5 kΩ to 33 kΩ
pull-up resistor.
To suppress noise, add a filter capacitor, CFO, near the
IC with minimizing a trace length between the FO and
GND pins. The value of CFO must be set to ≤3300 pF.
For avoiding repeated OCP activations, the external
microcontroller must shut off any input signals to the IC
within a fixed hold time, tFO, after the internal MOSFET(QFO) turn-on. tFO is the value where minimum values ofthermal characteristics are taken into account (for moredetails, see Section 13.3.4).
VFO_PU

TH
14

VTH

VCC

U1

5V

GND
21

Figure 13-9.

Internal Circuit Diagram of TH Pin and
Its Peripheral Circuit

Table 13-2. Recommended RTH Values
VTH_PU (V)RTH (kΩ)
Min.

Typ.

Max.

3.3

6.8

15

33

5.0

10

22

47

The following figures show the relationships between
the VTH voltage and the thermistor temperature when
VTH_PU = 3.3 V (Figure 13-10) and when VTH_PU = 5.0 V(Figure 13-11). Be sure to set the external power supply,
VTH_PU, and the resistor, RTH, according to the thermistor
temperature to be detected.

1 MΩ

RFO
FO
18
50 Ω

Shutdown
signalCFO
GND
21

Figure 13-8.

QFO

Internal Circuit Diagram of FO Pin and
Its Peripheral Circuit

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SAM265M50BS3
inputting a fault signal to the FO pin.

3.0

RTH = 6.8 kΩ

VTH Voltage (V)2.5

RTH = 15 kΩ

2.0

13.3.1. Fault Signal Output
In case one or more of the following protections are
actuated, an internal transistor, QFO, turns on, then the
FO pin becomes logic low (0.09 V).

1.5
1.0
0.5

RTH = 33 kΩ

0.0
55

65

75

85

95

105

115

125

While the FO pin is in the low state, all the low-side
transistors turn off. In normal operation, the FO pin
outputs a high signal of about 5 V. The FO Pin OCP
Hold Time, tFO, is determined by a value of the capacitor,
CCFO, connected to the CFO pin (see Section 13.2.10).
For avoiding repeated OCP activations, the external
microcontroller must shut off any input signals to the IC
within a fixed hold time, tFO, after the internal MOSFET(QFO) turn-on. tFO is the value where minimum values ofthermal characteristics are taken into account (for moredetails, see Section 13.3.4).

Thermistor Temperature (℃)

Figure 13-10. VTH Voltage vs. Thermistor
Temperature (VTH_PU = 3.3 V)

4.0

VTH Voltage (V)3.5

RTH = 10 kΩ

3.0

RTH = 22 kΩ

2.51) VCCL pin undervoltage lockout for power supply(UVLO_VCCL)
2) Overcurrent protection (OCP)

2.0
1.5

13.3.2. Shutdown Signal Input

1.0
0.5

RTH = 47 kΩ

0.0
55

65

75

85

95

105

115

125

Thermistor Temperature (℃)

The FO pin also acts as the input pin of shutdown
signals. When the FO pin becomes logic low, all thelow-side transistors turn off. The voltages and pulse
widths of shutdown signals should be set as listed inTable 13-3.

Figure 13-11. VTH Voltage vs. Thermistor
Temperature (VTH_PU = 5.0 V)
The SAM265M50BS3 does not have any protection
against overtemperature; therefore, the motor must be
externally controlled when a temperature rise occurs, orbe controlled with such protective measures. Moreover,note that the TH pin output does not provide thetemperature followability, especially when a rapid
temperature rise in the output transistors occurs during
motor lock and short circuit conditions.

13.3. Protection Functions
This section describes the various protection circuits
provided in the SAM265M50BS3. The protection
circuits include the VBx pin undervoltage lockout for
power supply (UVLO_VBx), the VCCL pin
undervoltage lockout for power supply (UVLO_VCCL),
and the overcurrent protection (OCP).
In case the UVLO_VCCL or OCP circuit is activated,
the FO pin outputs a fault signal; as a result, the external
microcontroller can stop the operations of the threephases by receiving the fault signal. The external
microcontroller can also shut down IC operations by

Table 13-3. Shutdown Signals
Parameter
FO PinVoltage
Input Pulse
WidthHigh Level Signal

Low Level Signal

3 V < VFO < 5.5 V

0 V < VFO < 0.5 V≥3.0 μs≥3.0 μs

When the FO pin becomes logic high, all the low-side
transistors operate according to input signals to the INLx
pin. The FO pin has an internal filter circuit of 2.5 μs toprevent noise-induced malfunctions.
Figure 13-12 shows the operational waveforms atshutdown signal input. Figure 13-13 illustrates aninternal circuit diagram of the FO pin and its peripheral
circuit.

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SAM265M50BS3
Shutdown
Signal

FO
VFO_H
VFO_L

2 V (typ.)
1.5 V (typ.)
t

0

INHx
0

increases to VVBx-VSx_H = 12.1 V or more, the IC releases
the UVLO_VBx condition. Then, the HOx signal
becomes logic high at the rising edge of the first input
command after the UVLO_VBx release.
Any fault signals are not output from the FO pin
during the UVLO_VBx operation. The VBx pin has aninternal filter circuit of about 1.8 µs to prevent noiseinduced malfunctions.

t

INLx

INHx
0

t

0

HOx

INLx
t

0
2.5 µs2.5 µs2.5 µs02.5 µsUVLO_VBx
operation

LOx

VBx VSx
0t

VVBx-VSx_H

VVBx-VSx_L

Figure 13-12.

Operational Waveforms at Shutdown
Signal Input

About 1.8 µs

HOx

VFO_PUVCC

UVLO release0

About 1.8 µs

HOx restarts at
positive edge after
UVLO_VBx release.

U1

5V

0

1 MΩ

RFO
FO
18

0

50 Ω

Shutdown
signalLOx

FO

No FO output at UVLO_VBx

CFO
GND
21

Figure 13-13.

QFO

Internal Circuit Diagram of FO Pin and
Its Peripheral Circuit

13.3.3. Undervoltage Lockout for Power
Supply (UVLO)
In case the gate-driving voltages of the output
transistors decrease, their steady-state power dissipations
increase. This overheating condition may cause
permanent damage to the IC in the worst case. To
prevent this event, the IC has the undervoltage lockout(UVLO) circuits for each of the VBx and VCCL pins.

13.3.3.1. VBx Pin Undervoltage Lockout(UVLO_VBx)
Figure 13-14 shows operational waveforms of the
VBx pin undervoltage lockout for power supply (i.e.,
UVLO_VBx).
When the voltage between the VBx and VSx pins
(VBx–VSx) decreases to VVBx-VSx_L = 11.6 V or less, theUVLO_VBx circuit in the corresponding phase gets
activated and sets an HOx signal to logic low.
When the voltage between the VBx and VSx pins

0

Figure 13-14.

UVLO_VBx Operational Waveforms

13.3.3.2. VCCL Pin Undervoltage Lockout(UVLO_VCCL)
Figure 13-15 shows operational waveforms of the
VCCL pin undervoltage lockout for power supply (i.e.,
UVLO_VCCL).
When the VCCL pin voltage decreases to
VVCCL_L = 12.1 V or less, the UVLO_VCCL circuit gets
activated and sets an LOx signal to logic low.
When the VCCL pin voltage increases to
VVCCL_H = 12.6 V or more, the IC releases the
UVLO_VCCL condition. Then it resumes transmitting
the LOx signal according to an input command on the
INLx pin.
During the UVLO_VCCL operation, the FO pin
becomes logic low and sends fault signals. The VCCL
pin has an internal filter circuit of about 1.8 µs toprevent noise-induced malfunctions.

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SAM265M50BS3
IC puts an LOx signal and the FO pin to logic low. The
low-side transistors turn off as the LOx signal becomes
logic low; as a result, output current decreases. Even if
the OCP pin voltage falls below VOCP_L, the IC holds theFO pin in the low state for a fixed OCP hold time (t FO).
The low-side transistors also remain turned off during
this period. Then, the output transistors operateaccording to input signals.
The OCP pin has an internal filter circuit of about
0.29 µs to prevent noise-induced malfunctions.
The FO Pin OCP Hold Time, tFO, is determined by avalue of the capacitor, CCFO, connected to the CFO pin(see Section 13.2.10).

INHx
0

INLx
0
UVLO_VCCL operation

VCCL
VVCCL_H

VVCCL_L0

HOx0
LOx responds to input signal.

About 1.8 µs

LOx
INHx
0

About 2.5 µs

0

INLx

About 1.8 µs

FO

VVFO_H0

VVFO_L0

Figure 13-15.

IOCP

UVLO_VCCL Operational Waveforms
00.29 µs (typ.)OCP

13.3.4. Overcurrent Protection (OCP)

VOCP_HThe OCP pin has the overcurrent protection (OCP)
circuit. Figure 13-16 is an internal circuit diagram
describing the OCP pin and its peripheral circuit.
The OCP pin detects overcurrents with voltage acrossan external shunt resistor, RS. Because the OCP pin isinternally pulled down, the OCP pin voltage increases
proportionally to a rise in the current running throughthe shunt resistor, RS.

0.5 V (typ.)

0

HOx
0

LOx
0

FO

U1

P

27

VCC

OCP
20

CF
GND
21

tFO
Blanking
filter
0.29 µs(typ.)

Figure 13-17.

Output transistors
turn-off and QFOturn-onNW
NV NU
23 24 25
RS

Figure 13-16.

VFO_H
2 V (typ.)

VFO_L
1.5 V (typ.)40 kΩ
150 kΩ

RF

0Internal Circuit Diagram of OCP Pin
and Its Peripheral Circuit

Figure 13-17 shows operational waveforms when the
OCP pin detects an overcurrent condition. When the
OCP pin voltage increases to VOCP_H = 0.50 V or more,
and remains in this condition for 0.29 μs or longer, the
OCP circuit is activated. When the OCP is activated, the

OCP Operational Waveforms

The OCP is used for detecting abnormal conditions,such as an output transistor shorted. In case short-circuit
conditions occur repeatedly, the output transistors can be
destroyed. For this reason, motor operations must be
controlled by the external microcontroller so that it can
immediately stop the motor when fault signals aredetected.
The external microcontroller receives the fault signals
with its interrupt pin (INT), and must be programmed to
put the INHx and INLx pins to logic low within apredetermined OCP hold time, tFO. To resume the motor
operation thereafter, set the motor to be resumed after alapse of ≥2 seconds.
For proper shunt resistor setting, your applicationmust meet the following:

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SAM265M50BS3● Use the shunt resistor that has a recommended
resistance, RS (see Section 3).
● Set the OCP pin input voltage to vary within the rated
OCP pin voltages, VOCP (see Section 2).
● Keep the current through the output transistors below
the rated collector current (peak), ICP (see Section 2).
● Surface-mount current detection resistor● Allowable tolerance: ±2% or less
● Thermal coefficient: ±200 ppm/°C or less
It is required to use a resistor with low internal
inductance because high-frequency switching current
will flow through the shunt resistor, RS. In addition,choose a resistor with allowable power dissipationaccording to your application.
When you connect a CR filter (i.e., a pair of a filter
resistor, RF, and a filter capacitor, CF) to the OCP pin,care should be taken in setting the time constants of R F
and CF. The larger the time constant, the longer the timethat the OCP pin voltage rises to VOCP_H. And this may
cause permanent damage to the transistors. Be sure to set
the time constants of RF and CF to 1.5 µs or less so that
the OCP can start to operate within 2.0 µs when a shortcircuit condition occurs. And place CF as close as
possible to the IC with minimizing a trace length
between the OCP and GND pins.
Note that overcurrents are undetectable when one ormore of the U, V, and W pins or their traces are shorted
to ground (ground fault). In case any of these pins falls
into a state of ground fault, the output transistors may bedestroyed.

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SAM265M50BS3
14. Design Notes
Back side layout

U1

14.1. PCB Pattern Layout
Figure 14-1 shows a schematic diagram of a motor
driver circuit. The motor driver circuit consists ofcurrent paths having high frequencies and high voltages,
which also bring about negative influences on IC
operation, noise interference, and power dissipation.
Therefore, PCB trace layouts and component placements
play an important role in circuit designing. Current loops(especially, between the P pin, CP, and the Nx pin)should be as small and wide as possible, in order tomaintain a low-impedance state. In addition, groundtraces should be as wide and short as possible so thatradiated EMI levels can be reduced.
A shunt resistor, RS, should be placed as close as
possible to the IC with minimizing a trace length
between the Nx pin and a capacitor, CP.
Varying electric potential of the logic ground can be acause of improper operations. Therefore, connect thelogic ground as close and short as possible to the shunt
resistor, RS, at a single-point ground (or star ground)which is separated from the power ground (see Figure14-1). Moreover, extreme care should be taken whenwiring so that currents from the power ground do notaffect the logic ground (e.g., the control ground trace is
not placed parallel near the power ground, and thesetraces are not crossed as much as possible).
To reduce the noise effect to the OCP pin, connect theovercurrent detection trace as near as possible to theshunt resistor, RS (see Figure 14-1 and Figure 14-2).
Also, place the overcurrent detection trace parallel to thelogic ground trace and connect it to the OCP pin.
High-frequency, high-voltage current loops
should be as small and wide as possible.

U1

P 29
VP(DC)

21 GND

NU 25
NV 24
NW 23

CP
RS

20 OCP
Ground traces should
be wide and short.
Create a single-point ground (a star ground) nearRS, but keep it separated from the power ground.
Place the overcurrent detection trace parallel to the logic
ground trace.

GND 21RS

OCP 20 NW 23
NV 24
NU 25

CP
P 30

Front side layout

Figure 14-2.

Peripheral Layout Example of CP(Double-sided Board)

14.2. Considerations in Heatsink Mounting
The following are the key considerations and theguidelines for mounting a heatsink:● Be sure to use a metric screw of M3 and a plain
washer of 7 mm (φ). To tighten the screws, use atorque screwdriver. Tighten the two screws firstly up
to 20% to 30% of the maximum screw torque, thenfinally up to 100% of the prescribed maximum screw
torque. Perform appropriate tightening within therange of screw torque defined in Section 5. The orderof the screws does not matter to the temporary
tightening. Note that the sequence when the screws
are tightened finally must be the same order as these
are tightened firstly.
● When mounting a heatsink, it is recommended to use
silicone greases. If a thermally conductive sheet or anelectrically insulating sheet is used, package cracks
may be occurred due to creases at screw tightening.
Therefore, you should conduct thorough evaluations
before using these materials.
● When applying a silicone grease, make sure that there
are no foreign substances between the IC and aheatsink. Extreme care should be taken not to apply asilicone grease onto any device pins as much as
possible. The following requirements must be met for
proper grease application:− Grease thickness: 100 μm to 200 µm

Figure 14-1. High-frequency and High-voltage Current
Paths, and Connections to Logic Ground

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SAM265M50BS3
14.3. Considerations in IC Characteristics
Measurement
When checking the characteristics of the internal
switching elements (IGBTs and freewheeling diodes),the IGBTs may result in permanent damage unless theseare measured appropriately. Therefore, the following
should be taken into account. The absolute maximum
rating of the Collector-to-Emitter Voltage, VCES, is650 V.
● Do not measure the withstand voltage of the internal
IGBTs. Applying the voltage of VCES or more
between the collector and emitter may degrade the
IGBTs.
● Measurement condition of the leakage current of theinternal IGBTs must be below VCES.
● The leakage current value is the total leakage currentof such as IGBT, freewheeling diode, control IC, andbootstrap diode. These leakage currents can not bemeasured individually.
● When measuring leakage current of the IGBTs, notethat the gate and emitter of the IGBT must be thesame potential. To measure the leakage current of the
IGBTs, connect each pin as follows:
Measuring the High-side IGBTs:– Connect the VBx pin to the VSx pin of thecorresponding phase, respectively.
– Connect the INLx and VCCL pins to the GND pin.
– Connect the VCCHx pin of the to-be-measured
phase and the VCCL pin to the GND pin.
Measuring the Low-side IGBTs:– Connect the VBx pin to the VSx pin of thecorresponding phase, respectively.
– Connect the INLx and VCCL pins to the GND pin.
The following are circuit diagrams representing
typical measurement circuits for leakage current: Figure14-3 shows the high-side IGBT (QLH) in the U-phase;
Figure 14-4 shows the low-side IGBT (QLU) in the Uphase.

U1

VSW

29
9

High-side
MIC

VBW
10
VSV
VBV
VSU

VBU
VCCHU
INHU

5

1

QHV

High-side
MIC

2

A

QHW

High-side
MIC

6

P

QHU

3
28

4

U

27 V

INLU
15
INLV
16
INLW
17
VCCL
22
GND
21

Low-side
MIC

26 W

QLW

QLV
QLU

25
24

23

NU
NV

NW

Figure 14-3. Typical Leakage Current Measurement
Circuit for High-side IGBT (QHU) in U-phase

U1

VSW

29
9

VBW
10
VSV

VBV

5
6

High-side
MIC

P

QHW

QHV

High-side
MIC

QHU

VSU
VBU

1

High-side
MIC

2

INLU
15
INLV
16
INLW
17
VCCL
22
GND
21

28
Low-side
MIC

QLW

U

A

27 V
26 W
QLV

QLU
NU
25
NV
24
NW
23

Figure 14-4. Typical Leakage Current Measurement
Circuit for Low-side IGBT (QLU) in U-phase

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SAM265M50BS3
15. Calculating Power Losses andEstimating Junction Temperature

VCE(SAT) vs. IC curve.

This section describes the procedures to calculate
power losses in a switching transistor, and to estimate ajunction temperature. Note that the descriptions listed
here are applicable to the SAM265M50BS3, which iscontrolled by a 3-phase sine-wave PWM driving
strategy.
Total power loss in an IGBT can be obtained bytaking the sum of steady-state loss, PON, and switching
loss, PSW. The following subsections contain themathematical procedures to calculate the power losses in
an IGBT and its junction temperature.
For quick and easy references, we offer calculation
support tools online. Please visit our website to find out
more.

2.5

● DT0051: SAM265M50BS3 Calculation Tool
https://www.semicon.sanken-ele.co.jp/en/calctool/igbt1_caltool_en.html

Figure 15-1 shows the linear approximation(VCE(SAT) = α × IC + β) based on the VCE(SAT) vs. IC curve
at a range the IC is actually used.
The values gained by the above calculation are thenapplied as parameters in Equation (4), below. Hence, theequation to obtain the IGBT steady-state loss, PON, is:
1 π(φ) × IC (φ) × DT × dφ
∫ V
2π 0 CE(SAT)

1 1 4= α( +
M × cos θ) IM 2
2 2 3π√2 1 π+β ( + M × cos θ) IM .
π
2 8

(4)

Where:VCE(SAT) is the collector-to-emitter saturation voltage of
the IGBT (V),IC is the collector current of the IGBT (A),DT is the duty cycle, which is given byDT =VCE(SAT) (V)1.5
y = 0.026x + 1.203
1.0
0.5
TJ = 125 °C
0.0
0

10

20

30

40

50

IC (A)

Figure 15-1.

Linear Approximate Equation of
VCE(SAT) vs. IC

15.2. IGBT Switching Loss, PSW

15.1. IGBT Steady-state Loss, PON

PON =

2.0

1 + M × sin(φ + θ),
2

Switching loss in an IGBT, PSW, can be calculated by
Equation (5), letting IM be the effective current value ofthe motor:
PSW =VP(DC)√2× fC × αE × IM ×
.
π
300

(5)

Where:
fC is the PWM carrier frequency (Hz),VP(DC) is the main power supply voltage (V), i.e., the P
pin input voltage, andαE is the slope of the switching loss curve (see Section
16.2.2).

15.3. Estimating Junction Temperature of
IGBT
The junction temperature of an IGBT, T J, can be
estimated with Equation (6):
TJ = R (J−C)Q × (PON + PSW ) + TC .

(6)

Where:
R(J-C)Q is the junction-to-case thermal resistance per
IGBT (°C/W), andTC is the case temperature (°C), measured at the point
defined in Section 4.4.

M is the modulation index (0 to 1),cosθ is the motor power factor (0 to 1),
IM is the effective motor current (A),α is the slope of the linear approximation in the
VCE(SAT) vs. IC curve, andβ is the intercept of the linear approximation in the

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SAM265M50BS3
16. Performance Curves

Ratio of Transient Thermal Resistance

16.1. Transient Thermal Resistance Curves
1.00

0.10

0.01
0.001

0.01

0.1

1

10

Time (s)Figure 16-1.

Transient Thermal Resistance

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SAM265M50BS3
16.2. Performance Curves of Output Parts
16.2.1. Output Transistor Performance Curves
VVCCHx = 15 V, VVCCL = 15 V

2.5

2.5
2.0
TJ = 25 °C

TJ = 25 °C

1.5

VF (V)VCE(SAT) (V)

2.0

1.0
0.5

1.5
1.0
0.5

TJ = 125 °C
0.0

0.0
0

10

20

30

40

50

0

10

20

IC (A)

Figure 16-2.

30

40

50

IF (A)IGBT VCE(SAT) vs. IC

Figure 16-3.

Freewheeling Diode VF vs. IF

16.2.2. Switching Loss Curves
Conditions: P pin voltage = 300 V, half-bridge circuit with inductive load.
Switching Loss, E, is the sum of turn-on loss and turn-off loss.

4000

4000
TJ = 125 °C

TJ = 125 °C
3000

E (µJ)E (µJ)

3000
2000
1000

2000
1000

TJ = 25 °C

TJ = 25 °C
0

0
0.0

10.0

20.0

30.0

40.0

50.0

0.0

10.0

IC (A)

Figure 16-4.

High-side Switching Loss

20.0

30.0

40.0

50.0

IC (A)

Figure 16-5.

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Low-side Switching Loss

34

SAM265M50BS3
16.3. Allowable Effective Current Curves
The following curves represent allowable effective currents in 3-phase sine-wave PWM driving with parameters suchas maximum VCE(SAT) and maximum switching losses.
Operating conditions: P pin input voltage, VP(DC) = 300 V; VCCHx pin input voltage, VVCCHx = 15 V; VCCL pin
input voltage, VVCCL = 15 V; modulation index, M = 1.0; junction temperature, T J = 150 °C; output frequency = 60 Hz.
fC = 5 kHz

Allowable Effective Current (Arms)

50.0

40.0

30.0

20.0

10.0

0.0
25

50

75

100

125

150

TC (°C)
Figure 16-6.

Allowable Effective Current (fC = 5 kHz)fC = 20 kHz

Allowable Effective Current (Arms)

50.0

40.0

30.0

20.0

10.0

0.0
25

50

75

100

125

150

TC (°C)
Figure 16-7.

Allowable Effective Current (fC = 20 kHz)SAM265M50BS3-DSE Rev.1.1
SANKEN ELECTRIC CO., LTD.
Oct. 24, 2023
https://www.sanken-ele.co.jp/en© SANKEN ELECTRIC CO., LTD. 2021

35

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Important Notes● All data, illustrations, graphs, tables and any other information included in this document (the “Information”) as to Sanken’s
products listed herein (the “Sanken Products”) are current as of the date this document is issued. The Information is subject to any
change without notice due to improvement of the Sanken Products, etc. Please make sure to confirm with a Sanken sales
representative that the contents set forth in this document reflect the latest revisions before use.
● The Sanken Products are intended for use as components of general purpose electronic equipment or apparatus (such as home
appliances, office equipment, telecommunication equipment, measuring equipment, etc.). Prior to use of the Sanken Products,
please put your signature, or affix your name and seal, on the specification documents of the Sanken Products and return them toSanken. When considering use of the Sanken Products for any applications that require higher reliability (such as transportationequipment and its control systems, traffic signal control systems or equipment, disaster/crime alarm systems, various safety
devices, etc.), you must contact a Sanken sales representative to discuss the suitability of such use and put your signature, or affix
your name and seal, on the specification documents of the Sanken Products and return them to Sanken, prior to the use of theSanken Products. The Sanken Products are not intended for use in any applications that require extremely high reliability such as:
aerospace equipment; nuclear power control systems; and medical equipment or systems, whose failure or malfunction may result
in death or serious injury to people, i.e., medical devices in Class III or a higher class as defined by relevant laws of Japan(collectively, the “Specific Applications”). Sanken assumes no liability or responsibility whatsoever for any and all damages andlosses that may be suffered by you, users or any third party, resulting from the use of the Sanken Products in the Specific
Applications or in manner not in compliance with the instructions set forth herein.
● In the event of using the Sanken Products by either (i) combining other products or materials or both therewith or (ii) physically,
chemically or otherwise processing or treating or both the same, you must duly consider all possible risks that may result from all
such uses in advance and proceed therewith at your own responsibility.
● Although Sanken is making efforts to enhance the quality and reliability of its products, it is impossible to completely avoid theoccurrence of any failure or defect or both in semiconductor products at a certain rate. You must take, at your own responsibility,
preventative measures including using a sufficient safety design and confirming safety of any equipment or systems in/for which
the Sanken Products are used, upon due consideration of a failure occurrence rate and derating, etc., in order not to cause any
human injury or death, fire accident or social harm which may result from any failure or malfunction of the Sanken Products.
Please refer to the relevant specification documents and Sanken’s official website in relation to derating.
● No anti-radioactive ray design has been adopted for the Sanken Products.
● The circuit constant, operation examples, circuit examples, pattern layout examples, design examples, recommended examples, allinformation and evaluation results based thereon, etc., described in this document are presented for the sole purpose of reference ofuse of the Sanken Products.
● Sanken assumes no responsibility whatsoever for any and all damages and losses that may be suffered by you, users or any third
party, or any possible infringement of any and all property rights including intellectual property rights and any other rights of you,users or any third party, resulting from the Information.
● No information in this document can be transcribed or copied or both without Sanken’s prior written consent.
● Regarding the Information, no license, express, implied or otherwise, is granted hereby under any intellectual property rights andany other rights of Sanken.
● Unless otherwise agreed in writing between Sanken and you, Sanken makes no warranty of any kind, whether express or implied,
including, without limitation, any warranty (i) as to the quality or performance of the Sanken Products (such as implied warrantyof merchantability, and implied warranty of fitness for a particular purpose or special environment), (ii) that any Sanken Product isdelivered free of claims of third parties by way of infringement or the like, (iii) that may arise from course of performance, courseof dealing or usage of trade, and (iv) as to the Information (including its accuracy, usefulness, and reliability).
● In the event of using the Sanken Products, you must use the same after carefully examining all applicable environmental laws andregulations that regulate the inclusion or use or both of any particular controlled substances, including, but not limited to, the EU
RoHS Directive, so as to be in strict compliance with such applicable laws and regulations.
● You must not use the Sanken Products or the Information for the purpose of any military applications or use, including but notlimited to the development of weapons of mass destruction. In the event of exporting the Sanken Products or the Information, or
providing them for non-residents, you must comply with all applicable export control laws and regulations in each country
including the U.S. Export Administration Regulations (EAR) and the Foreign Exchange and Foreign Trade Act of Japan, andfollow the procedures required by such applicable laws and regulations.
● Sanken assumes no responsibility for any troubles, which may occur during the transportation of the Sanken Products including
the falling thereof, out of Sanken’s distribution network.
● Although Sanken has prepared this document with its due care to pursue the accuracy thereof, Sanken does not warrant that it iserror free and Sanken assumes no liability whatsoever for any and all damages and losses which may be suffered by you resulting
from any possible errors or omissions in connection with the Information.
● Please refer to our official website in relation to general instructions and directions for using the Sanken Products, and refer to therelevant specification documents in relation to particular precautions when using the Sanken Products.
● All rights and title in and to any specific trademark or tradename belong to Sanken and such original right holder(s).

DSGN-CEZ-16003

SAM265M50BS3-DSE Rev.1.1
SANKEN ELECTRIC CO., LTD.
Oct. 24, 2023
https://www.sanken-ele.co.jp/en© SANKEN ELECTRIC CO., LTD. 2021

36