500 V, 1 A to 3 A
High Voltage 3-phase Motor Drivers

SLA68xxMH Series

Data Sheet

Description

Packages

The SLA68xxMH series are high voltage 3-phasemotor drivers in which transistors, pre-drive circuits, andbootstrap circuits (diodes and resistors) are highly
integrated.
Selectable ZIP24 packages (heatsink type) withvarious leadforms enable excellent mountability to awide range of applications. These products can
optimally control the inverter systems of low- to
medium-capacity motors.

ZIP24 (Heatsink type)

Leadform 2175

Features● Built-in Bootstrap Diodes with Current Limiting
Resistors (210 Ω)● CMOS-compatible Input (5 V)● Shutdown Function● Bare Lead Frame: Pb-free (RoHS Compliant)● Protections Include:
Undervoltage Lockout for Power Supply
VBx Pin (UVLO_VB): Auto-restart
VCC1 Pin (UVLO_VCC1): Auto-restart
VCC2 Pin (UVLO_VCC2): Auto-restart
Overcurrent Limit (OCL)
Overcurrent Protection (OCP):
Auto-restart with Adjustable OCP Hold Time
Thermal Shutdown (TSD): Auto-restart

Leadform 2171
Not to scale

Selection Guide
VDSS
500 V

IO

Part Number

2.5 A

SLA6868MH

3.0 A

SLA6870MH

Typical Application
Applications
VCC

VCC1 4

1

VB1

For motor drives such as:

CBOOT1
2 VB2
COM1
HIN3
HIN2
HIN1

HIN3
HIN2
HIN1

6
7
8
9

5V

● Fan Motor and Pump Motor for Washer and Dryer● Fan Motor for Air Conditioner● Fan Motor for Air Purifier and Electric Fan

CBOOT23 VB3CBOOT3High-side
MIC

VDC

10VBB

Controller

RCL
SD1 5
CCL

24 U
OCL 17
LIN3 18
LIN2 19
LIN1 20
COM2 21

LIN3
LIN2

LIN1

5V

RSD2
Fault

5V

SD2

22
VCC2 23

11

12 V

Low-side
MIC

RRC
RC

W1

15

M

13 W2

14 LS216 LS1

CSD2 CRCCSB CDCRS

GND

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1

SLA68xxMH Series
Contents
Description ------------------------------------------------------------------------------------------------------ 1
Contents --------------------------------------------------------------------------------------------------------- 2
1. Absolute Maximum Ratings----------------------------------------------------------------------------- 4
2. Recommended Operating Conditions ----------------------------------------------------------------- 5
3. Electrical Characteristics -------------------------------------------------------------------------------- 6
3.1 Characteristics of Control Parts------------------------------------------------------------------ 6
3.2 Bootstrap Diode Characteristics ----------------------------------------------------------------- 7
3.3 Thermal Resistance Characteristics ------------------------------------------------------------- 7
3.4 Power MOSFET Characteristics ----------------------------------------------------------------- 8
3.4.1
SLA6868MH ----------------------------------------------------------------------------------- 8
3.4.2
SLA6870MH ----------------------------------------------------------------------------------- 9
4. Mechanical Characteristics ----------------------------------------------------------------------------- 9
5. Truth Table ----------------------------------------------------------------------------------------------- 10
6. Block Diagram ------------------------------------------------------------------------------------------- 11
7. Pin Configuration Definitions ------------------------------------------------------------------------- 12
8. Typical Application ------------------------------------------------------------------------------------- 13
9. Physical Dimensions ------------------------------------------------------------------------------------ 14
9.1 ZIP24 (Leadform 2175) -------------------------------------------------------------------------- 14
9.2 ZIP24 (Leadform 2171) -------------------------------------------------------------------------- 15
10. Marking Diagram --------------------------------------------------------------------------------------- 16
10.1 ZIP24 ------------------------------------------------------------------------------------------------ 16
11. Functional Descriptions -------------------------------------------------------------------------------- 17
11.1 Turning On and Off the IC ---------------------------------------------------------------------- 17
11.2 Pin Descriptions ----------------------------------------------------------------------------------- 17
11.2.1 U, V, W1, and W2 --------------------------------------------------------------------------- 17
11.2.2 VBB -------------------------------------------------------------------------------------------- 17
11.2.3 LS1 and LS2 ---------------------------------------------------------------------------------- 17
11.2.4 VB1, VB2, and VB3 ------------------------------------------------------------------------- 17
11.2.5 VCC1 and VCC2 ---------------------------------------------------------------------------- 18
11.2.6 COM1 and COM2--------------------------------------------------------------------------- 19
11.2.7 HIN1, HIN2, and HIN3; LIN1, LIN2, and LIN3 -------------------------------------- 19
11.2.8 OCL -------------------------------------------------------------------------------------------- 20
11.2.9 RC ---------------------------------------------------------------------------------------------- 20
11.2.10 SD1 and SD2 --------------------------------------------------------------------------------- 20
11.3 Protection Functions ------------------------------------------------------------------------------ 21
11.3.1 Fault Signal Output ------------------------------------------------------------------------- 21
11.3.2 Shutdown Signal Input --------------------------------------------------------------------- 21
11.3.3 Undervoltage Lockout for Power Supply (UVLO) ----------------------------------- 21
11.3.4 Overcurrent Limit (OCL) ----------------------------------------------------------------- 23
11.3.5 Overcurrent Protection (OCP) ----------------------------------------------------------- 23
11.3.6 Thermal Shutdown (TSD) ----------------------------------------------------------------- 24
12. Design Notes ---------------------------------------------------------------------------------------------- 24
12.1 PCB Pattern Layout ------------------------------------------------------------------------------ 24
12.2 Considerations in Heatsink Mounting -------------------------------------------------------- 25
12.3 Considerations in IC Characteristics Measurement --------------------------------------- 25
13. Calculating Power Losses and Estimating Junction Temperature ---------------------------- 26
13.1 Power MOSFET Steady-state Loss, PRON ---------------------------------------------------- 26
13.2 Power MOSFET Switching Loss, PSW --------------------------------------------------------- 26
13.3 Body Diode Steady-state Loss, PSD ------------------------------------------------------------- 27

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SLA68xxMH-DSE Rev.1.3

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SLA68xxMH Series
13.4 Estimating Junction Temperature of Power MOSFET ------------------------------------ 27
14. Performance Curves ------------------------------------------------------------------------------------ 28
14.1 Transient Thermal Resistance Curves -------------------------------------------------------- 28
14.2 Performance Curves of Control Parts--------------------------------------------------------- 29
14.3 Performance Curves of Output Parts --------------------------------------------------------- 35
14.3.1 Output Transistor Performance Curves ------------------------------------------------ 35
14.3.2 Switching Losses ----------------------------------------------------------------------------- 36
14.4 Allowable Effective Current Curves ----------------------------------------------------------- 37
14.4.1 SLA6868MH --------------------------------------------------------------------------------- 37
14.4.2 SLA6870MH --------------------------------------------------------------------------------- 38
15. Pattern Layout Example ------------------------------------------------------------------------------- 39
16. Typical Motor Driver Application ------------------------------------------------------------------- 41
Important Notes ---------------------------------------------------------------------------------------------- 42

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SLA68xxMH-DSE Rev.1.3

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SLA68xxMH Series
1.

Absolute Maximum Ratings

Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C, COM1 = COM2 = COM.
Parameter
SymbolConditions
Rating
Unit
Remarks
VBB–LSx,
Power MOSFET Breakdown
VDSS
VCC = 15 V,
500
V
Voltage
ID = 100 μA, VIN = 0 V
VCC1–COM,
VCC
20
VCC2–COM
Logic Supply VoltageV
VB1–U,VBS
VB2–V,
20
VB3–W1
SLA6868MH
2.5
TC = 25 °C,
Output Current (DC)(1)
IO
A
TJ < 150 °C
SLA6870MH
3.0
Output Current (Pulse)

IOP

Input Voltage

VIN

SD Pin Voltage

VSD

Allowable Power Dissipation
Operating Case Temperature (2)Junction Temperature (3)Storage Temperature

PD
TC(OP)TJ
TSTG

TC = 25 °C,
TJ < 150 °C,
PW ≤ 100 μs,
duty cycle = 1%
HIN1–COM,
HIN2–COM,
HIN3–COM;
LIN1–COM,
LIN2–COM,
LIN3–COM
SD1–COM,
SD2–COM
TC = 25 °C

3.75

A

4.5

SLA6868MH
SLA6870MH− 0.5 to 7

V

−0.5 to 7

V

32.8−30 to 100
150−40 to 150

W
°C
°C
°C

SLA6868MH/70MH(1)

Should be derated depending on an actual case temperature. See Section 14.4.
Refers to a case temperature measured during IC operation.
(3)
Refers to the junction temperature of each chip built in the IC, including the control MICs and power MOSFETs.
(2)

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SLA68xxMH-DSE Rev.1.3

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SLA68xxMH Series
2.

Recommended Operating Conditions

Unless specifically noted, COM1 = COM2 = COM.
Parameter
SymbolConditions
VBB–LS1,
Main Supply Voltage
VDC
VBB–LS2
Snubber Capacitor for Main
CSB
Power Supply
VCC1–COM,
VCC
VCC2–COM
Logic Supply Voltage
VB1–U,VBS
VB2–V,
VB3–W1VCC1–COM,
Protective Zener Voltage
VZ
VCC2–COM
Input Voltage
VIN(HINx, LINx, SDx)
SDx Pin Pull-up Voltage
VSD

Min.

Typ.

Max.

Unit

—

300

400

V

0.01

—

0.1

μF

13.5

15.0

16.5

V

13.5

—

16.5

V

18

—

20

V

0

—

5.5

V

3.0

—

5.5

V

OCL Pin Pull-up Voltage

VCL

3.0

—

5.5

V

SDx Pin Pull-up Resistor

RSD

3.3

—

10

kΩ

OCL Pin Pull-up Resistor

RCL

1

—

10

kΩ

SDx Pin Capacitor

CSDx

1

—

10

nF

OCL Pin Capacitor

CCL

1

—

10

nF

RC Pin Capacitor

CRC

1

—

4.7

nF

RC Pin Pull-up Resistor

RRC

33

—

680

kΩ

tIN(MIN)ON

TJ = −25 to 150 °C

0.5

—

—

μs

tIN(MIN)OFF

TJ = −25 to 150 °C

0.5

—

—

μs

tDEAD

1.5

—

—

μs

Switching Frequency

fc

—

—

20

kHz

Bootstrap Capacitor

CBOOT

1

—

220

μF

IP ≤ 3.75A

290

—

—

IP ≤ 4.5 A

240

—

—

Minimum Input Pulse Width
Dead Time of Input Signal

Shunt Resistor

RS

PWM Carrier Frequency

fC

—

—

20

kHz

TC(OP)

—

—

100

°C

Operating Case Temperature

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SLA68xxMH-DSE Rev.1.3mΩ

Remarks

SLA6868MH
SLA6870MH

5

SLA68xxMH Series
3.

Electrical Characteristics

Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C, VCC = 15 V, COM1 = COM2 = COM.

3.1

Characteristics of Control Parts
Parameter

SymbolConditions

Min.

Typ.

Max.

Unit

10.5

11.5

12.5

V

9.5

10.5

11.5

V

10.0

11.0

12.0

V

9.0

10.0

11.0

V

—

2.7

5.0

mA

—

135

380

μA

VIH

—

2.1

2.6

V

VIL

0.8

1.3

—

V

VHYS

—

0.8

—

VIN = 5 V

—

230

500

μA

VSD = VCL = 5 V,
RUP = 3.3 kΩ

—

—

0.6

V

0.50

0.53

0.56

V

0.9

1.0

1.1

V

—

1.0

—

ms

—

1.1

—

ms

Remarks

Power Supply Operation
VCC(ON)
Logic Operation Start Voltage
VBS(ON)VCC(OFF)
Logic Operation Stop Voltage
VBS(OFF)
ICC
Logic Supply Current
Input Signal
High Level Input Threshold
Voltage (HINx, LINx, SDx)
Low Level Input Threshold
Voltage (HINx, LINx, SDx)
Input Threshold Voltage
Hysteresis
Input Voltage
Protection
SDx Pin, OCL Pin
Low Level Output Voltage
Current Limit Reference
Voltage
OCP Threshold Voltage

OCP Hold Time

IBS

IIH

VSD(ON)

VCC1–COM,
VCC2–COM
VB1–U,
VB2–V,
VB3–W1VCC1–COM,
VCC2–COM
VB1–U,
VB2–V,
VB3–W1
IREG = 0 A
VBx = 15 V,
HINx = 5 V

VLIM
VTRIP

tP

VRC = 5 V,
RRC = 330 kΩ,
CRC = 0.0047 µF
VRC = 5 V,
RRC = 360 kΩ,
CRC = 0.0047 µF

OCP Blanking Time

tBK

—

2.0

—

μs

TSD Operating Temperature

TDH

120

135

150

°C

TSD Releasing Temperature
TSD Operating Temperature
Hysteresis

TDL

90

105

120

°C

TD_HYS

—

30

—

°C

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SLA68xxMH-DSE Rev.1.3

Outputtransistors ON
Outputtransistors OFF

6

SLA68xxMH Series
3.2

Bootstrap Diode Characteristics

Parameter
Bootstrap Diode Leakage
Current
Bootstrap Diode Forward
Voltage
Bootstrap Diode Series
Resistor

3.3

SymbolConditions

Min.

Typ.

Max.

Unit

ILBD

VR = 500 V, VIN = 0 V

—

—

10

μA

VFB

IFB = 0.05 A, VIN = 0 V

—

0.8

1.3

V

168

210

252

Ω

Min.

Typ.

Max.

Unit

—

—

3.8

°C/W 70MH

RBOOT

Thermal Resistance Characteristics
Parameter

SymbolJunction-to-Case Thermal
Resistance (1)R(J-C)(2)(1)(2)

Remarks

Conditions
All power MOSFETs
operatingRemarks
SLA6868MH/

Refers to a case temperature at the measurement point described in Figure 3-1, below.
Refers to steady-state thermal resistance between the junction of the built-in transistors and the case. For transient
thermal characteristics, see Section 14.1.

Measurement point

5 mm
24
Figure 3-1.

9Case Temperature Measurement Points

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SLA68xxMH Series
3.4

Power MOSFET Characteristics

エラー! 参照元が見つかりません。 provides the definitions of switching characteristics described in this and thefollowing sections.
HINx/
LINx
0

trr

ton

td(off) tf

td(on) tr

ID / IC

toff

90%
10%

0

VDS /
VCE

0

Figure 3-2.

3.4.1

Switching Characteristics Definitions

SLA6868MH
Parameter

SymbolConditions

Min.

Typ.

Max.

Unit

Drain-to-Source Leakage Current

IDSS

VDS = 500 V, VIN = 0 V

—

—

100

µA

Drain-to-Source On-resistanceSource-to-Drain Diode Forward
Voltage
High-side Switching
Source-to-Drain Diode Reverse
Recovery Time
Turn-on Delay Time

RDS(ON)

ID = 1.25 A, VIN = 5 V

—

2.0

2.4

Ω

VSD

ISD = 1.25 A, VIN = 0 V

—

1.1

1.5

V

—

120

—

ns

—

820

—

ns

—

100

—

ns

—

740

—

ns

—

30

—

ns

—

130

—

ns

—

790

—

ns

—

110

—

ns

—

700

—

ns

—

30

—

ns

Rise Time
Turn-off Delay Timetrrtd(ON)trtd(OFF)

Fall Timetf

Low-side Switching
Source-to-Drain Diode Reverse
Recovery Time
Turn-on Delay Time

trr

Rise Time
Turn-off Delay Time
Fall Timetd(ON)trtd(OFF)VDC = 300 V,
ID = 2.5 A,
VIN = 0 V to 5 V,
TJ = 25 °C,
inductive load

VDC = 300 V,
ID = 2.5 A,
VIN = 0 V to 5 V,
TJ = 25 °C,
inductive load

tf

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SLA68xxMH Series
3.4.2

SLA6870MH
Parameter

SymbolConditions

Min.

Typ.

Max.

Unit

Drain-to-Source Leakage Current

IDSS

VDS = 500 V, VIN = 0 V

—

—

100

µA

Drain-to-Source On-resistanceSource-to-Drain Diode Forward
Voltage
High-side Switching
Source-to-Drain Diode Reverse
Recovery Time
Turn-on Delay Time

RDS(ON)

ID = 1.5 A, VIN = 5 V

—

1.4

1.7

Ω

VSD

ISD = 1.5 A, VIN = 0 V

—

1.0

1.5

V

—

100

—

ns

—

755

—

ns

—

65

—

ns

—

680

—

ns

—

15

—

ns

—

105

—

ns

—

645

—

ns

—

70

—

ns

—

560

—

ns

—

20

—

ns

trr
td(on)

Rise Timetr

Turn-off Delay Timetd(off)Fall Timetf

Low-side Switching
Source-to-Drain Diode Reverse
Recovery Time
Turn-on Delay Timetrrtd(on)

Rise Timetr

Turn-off Delay Timetd(off)Fall Timetf

4.

VDC = 300 V,
ID = 3 A,
VIN = 0 V to 5 V,
TJ = 25 °C,
inductive load

VDC = 300 V,
ID = 3 A,
VIN = 0 V to 5 V,
TJ = 25 °C,
inductive load

Mechanical Characteristics
Parameter

Heatsink Mounting Screw Torque

Min.

Typ.

Max.

Unit

Remarks

58.8

—

78.4

N∙cm

SLA6868MH/
70MH

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SLA68xxMH Series
5.

Truth Table

Table 5-1 is a truth table that provides the logic level definitions of operation modes.
In the case where HINx and LINx signals in each phase are high at the same time, both the high- and low-side
transistors become on (simultaneous on-state). Therefore, HINx and LINx signals, the input signals for the HINx and
LINx pins, require dead time setting so that such a simultaneous on-state event can be avoided.
After the IC recovers from a UVLO_VCC2 condition, the low-side transistors resume switching in accordance with
the input logic levels of the LINx signals (level-triggered), whereas the high-side transistors resume switching at thenext rising edge of an HINx signal (edge-triggered).
After the IC recovers from a UVLO_VB or UVLO_VCC1 condition, the high-side transistors resume switching at
the next rising edge of an HINx signal (edge-triggered).
Table 5-1. Truth Table for Operation Modes
Mode

Normal Operation

Shutdown Signal Input(SD2 = “L”)

VBx Pin Undervoltage Lockout(UVLO_VB)
VCC1 Pin Undervoltage Lockout(UVLO_VCC1)

VCC2 Pin Undervoltage Lockout(UVLO_VCC2)

Overcurrent Protection (OCP)

Overcurrent Limit (OCL)(OCL = SD1)

Thermal Shutdown (TSD)

HINx
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

LINx
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

High-side Transistor
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
ON

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SLA68xxMH-DSE Rev.1.3

Low-side Transistor
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF

10

SLA68xxMH Series
6.

Block Diagram

Bootstrap
Diode RB
VCC1

VB1
1

VB2
2

VB3
3

UVLO

UVLO

UVLO

4

10 VBB
UVLO

HIN1
HIN2
HIN3

9
8
7

Input
Logic

High-side
Level Shift Driver
11 W1
13 W2
12 V

COM1 6
SD1

5

24 U

VCC2 23UVLO
LIN1 20
LIN2 19
LIN3 18

COM2 21

SD2 22

Low-side
DriverInput Logic(OCP reset)

ThermalShutdown

OCP
OCP, OCL

14 LS216 LS1

OCL 17
RC 15

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SLA68xxMH Series
7.

Pin Configuration Definitions

Leadform 2175

Leadform 2171

1
24

24

1

Pin Number
1
2
3
4

Pin Name
VB1
VB2
VB3
VCC1

5

SD1

6
7
8
9
10
11
12
13
14
15

COM1
HIN3
HIN2
HIN1
VBB
W1
V
W2
LS2
RC

16

LS1

17
18
19
20
21

OCL
LIN3
LIN2
LIN1
COM2

22

SD2

23
24

VCC2
U

Description
U-phase high-side floating supply voltage input
V-phase high-side floating supply voltage input
W-phase high-side floating supply voltage input
High-side logic supply voltage input
High-side shutdown signal input; fault signal output at UVLO_VCC1
activation
High-side logic ground
Logic input for W-phase high-side gate driver
Logic input for V-phase high-side gate driver
Logic input for U-phase high-side gate driver
Positive DC bus supply voltage
W-phase output (connected to W2 externally)
V-phase output
W-phase output (connected to W1 externally)
W-phase low-side power MOSFET source (connected to LS1 externally)
OCP hold time setting
U- and W-phase low-side power MOSFET source(connected to LS2 externally)
Overcurrent limit signal input
Logic input for W-phase low-side gate driver
Logic input for V-phase low-side gate driver
Logic input for U-phase low-side gate driverLow-side logic groundLow-side shutdown signal input; fault signal output at UVLO_VCC2, OCP, or
TSD activation
Low-side logic supply voltage input
U-phase output

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SLA68xxMH Series
8.

Typical Application

CR filters and Zener diodes should be added to your application as needed. This is to protect each pin against surge
voltages causing malfunctions, and to avoid the IC being used under the conditions exceeding the absolute maximum
ratings where critical damage is inevitable. Then, check all the pins thoroughly under actual operating conditions toensure that your application works flawlessly.
VCC

VCC1 4

1

VB1
CBOOT1

2 VB2
COM1
HIN3
HIN2
HIN1

HIN3
HIN2
HIN1

6
7
8
9

5V

CBOOT23 VB3CBOOT3High-side
MIC

VDC

10VBB

Controller

RCL
SD1 5
CCL

24 U
OCL 17
LIN3 18
LIN2 19
LIN1 20
COM2 21

LIN3
LIN2

LIN1

5V

RSD2
Fault

5V

SD2

22
VCC2 23

RRC
RC

15

11

W1

12 V

Low-side
MIC

M

13 W2

14 LS216 LS1

CSD2 CRCCSB CDCRS

GND

Figure8-1.

Typical Application (OCL = SD1)

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SLA68xxMH Series
9.

Physical Dimensions

9.1

ZIP24 (Leadform 2175)
31 ±0.2
24.4 ±0.2
Gate burr
16.4 ±0.2

4.8±0.2
φ3.2±0.15x3.8

1.7±0.1

φ3.2 ±0.15

9.9 ±0.2

0 to 0.55

D

2.45 ±0.2(Root of pin)
A

(4.4)

2.2 ±0.6(End of pin)

16 ±0.2

12.9 ±0.2

C(Roots of pins)D

0 to 0.55+0.15
0.5 -0.05

23×P1.27±0.1=(29.21)

2.2 ±0.6(End of pin)

+0.15
0.6 -0.05

B+0.5
3 -0.3(End of pin)

23×P1.27±0.6=(29.21)

0 to 0.55

31.3 ±0.2(Includes mold flash)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

D

0 to 0.55

D

Enlarged view of A

NOTES:- Dimensions in millimeters- Bare lead frame: Pb-free (RoHS compliant)- Maximum gate burr height is 0.3 mm.
- “B” depicts a pin whose plated surface may be cracked.
- “C” shows pins with a minimum inside radius (R) of 0.65 mm.
- “D” represents a pin illustrated for reference only, not the actual state of a bend.

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SLA68xxMH Series
9.2

ZIP24 (Leadform 2171)
31 ±0.2
24.4 ±0.2

4.8 ±0.2

16.4 ±0.2

1.7 ±0.1

Gate burr

φ3.2±0.15×3.8

16 ±0.2

2.45 ±0.2

5±0.512.9 ±0.2

9.9 ±0.2

φ3.2 ±0.15(Root of pin)

9.5 +0.7-0.5(4-R1)

0.6

+0.15
-0.05

(4.5)

R-end

0.5

23×P1.27±0.7=29.21±1

+0.15
-0.05

4.5±0.7(Ends of pins)(End of pin)

31.3 ±0.2(Includes mold flash)

2
1

4
3

6
5

8
7

10
9

12
11

14
13

16
15

18
17

20
19

22
21

24
23

NOTES:- Dimensions in millimeters- Bare lead frame: Pb-free (RoHS compliant)- Maximum gate burr height is 0.3 mm.

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SLA68xxMH Series
10. Marking Diagram
10.1 ZIP24

JAPANSLA68xxMHY MD DXPart Number
Lot Number:
Y is the last digit of the year of manufacture (0 to 9)
M is the month of the year (1 to 9, O, N, or D)
DD is the day of the month (01 to 31)
X is the control number

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SLA68xxMH Series
11. Functional Descriptions

11.2.3

Unless specifically noted, this section uses thefollowing definitions:

The LS1 pin is connected to the power MOSFET
sources of the U- and V-phases; the LS2 pin isconnected to the power MOSFET source of the W phase.
The LS1 and LS2 pins must be connected to eachother on a PCB. For current detection, these pins should
be connected to an external shunt resistor, RS. Whenconnecting the shunt resistor, place it as near as possible
to the IC with a minimum length of traces to the LSx
and COMx pins. Otherwise, malfunction may occur
because a longer circuit trace increases its inductanceand thus increases its susceptibility to improper
operations. In applications where long PCB traces are
required, add a fast recovery diode, DRS, between theLSx and COMx pins in order to prevent the IC from
malfunctioning.

● All the characteristic values given in this section are
typical values.
● For pin and peripheral component descriptions, thissection employs a notation system that denotes a pin
name with the arbitrary letter “x”, depending oncontext. Thus, “the VCCx pin” is used when referring
to either or both of the VCC1 and VCC2 pins.
● The COM1 pin is always connected to the COM2 pin.

11.1 Turning On and Off the IC
The procedures listed below provide recommended
startup and shutdown sequences. To turn on the IC
properly, do not apply any voltage on the VBB, HINx,
and LINx pins until the VCCx pin voltage has reached astable state (VCC(ON) ≥ 12.5 V).
It is required to fully charge bootstrap capacitors,
CBOOTx, at startup (see Section 11.2.2).
To turn off the IC, set the HINx and LINx pins tologic low (or “L”), and then decrease the VCCx pin
voltage.

LS1 and LS2

U1

VBB 10VDC
CS

6 COM1LS121 COM2

LS2

16
14

CDC
DRS
RS

Add a fast recovery
diode to a long trace.

11.2 Pin Descriptions
Figure 11-1.

11.2.1Connections to LSx Pin

U, V, W1, and W2

These pins are the outputs of the three phases, andserve as the connection terminals to the 3-phase motor.
The W1 and W2 pins must be connected to each otheron a PCB. The U, V, and W1 pins are the grounds for
the VB1, VB2, and VB3 pins. The U, V, and W1 pinsare connected to the negative nodes of bootstrap
capacitors, CBOOTx. Since high voltages are applied tothese output pins (U, V, W1, and W2), it is required totake measures for insulating as follows:● Keep enough distance between the output pins andlow-voltage traces.
● Coat the output pins with insulating resin.

11.2.2

Put a shunt resistor near
the IC with a minimum
length to the LSx pin.

VBB

This is the input pin for the main supply voltage, i.e.,
the positive DC bus. All of the power MOSFET drainsof the high-side are connected to this pin. Voltage
between the VBB and COMx pins should be set within
the recommended range of the main supply voltage, VDC,
given in Section 2.
To suppress surge voltages, put a 0.01 μF to 0.1 μF
bypass capacitor, CS, near the VBB pin and anelectrolytic capacitor, CDC, with a minimal length of
PCB traces to the VBB pin.

11.2.4

VB1, VB2, and VB3

These pins are connected to bootstrap capacitors forthe high-side floating supply.
Voltages across the VBx and these output pins should
be maintained within the recommended range (i.e., theLogic Supply Voltage, VBS) given in Section 2.
A bootstrap capacitor, CBOOTx, should be connected ineach of the traces between the VB1 and U pins, the VB2
and V pins, and the VB3 and W1 pins.
For proper startup, turn on the low-side transistors
first, then fully charge the bootstrap capacitor, CBOOTx.
For the capacitance of the bootstrap capacitors,
CBOOTx, choose the values that satisfy Equations (1) and(2). Note that capacitance tolerance and DC bias
characteristics must be taken into account when you
choose appropriate values for CBOOTx.
CBOOTx (μF) > 800 × t L(OFF)(1)

1 μF ≤ CBOOTx ≤ 220 μF(2)

In Equation (1), let tL(OFF) be the maximum off-timeof the low-side transistor (i.e., the non-charging time of
CBOOTx), measured in seconds.

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Even while the high-side transistor is not on, voltage
across the bootstrap capacitor keeps decreasing due topower dissipation in the IC. When the VBx pin voltage
decreases to VBS(OFF) or less, the high-side undervoltage
lockout (UVLO_VB) starts operating (see Section
11.3.3.1). Therefore, actual board checking should bedone thoroughly to validate that voltage across the VBx
pin maintains over 11.0 V (VBS > VBS(OFF)) during a
low-frequency operation such as a startup period.
As Figure 11-2 shows, a bootstrap diode, DBOOTx, anda current-limiting resistor, RBOOTx, are internally placed
in series between the VCC1 and VBx pins. Time
constant for the charging time of CBOOTx, τ, can becomputed by Equation (3):the high-side transistor is in an on-state), the next LINx
signal turns on the low-side transistor and causes asimultaneously-on condition, which may result incritical damage to the IC. To protect the VBx pin
against such a noise effect, add a bootstrap capacitor,
CBOOTx, in each phase. CBOOTx must be placed near the
IC and be connected between the VBx and HSx pinswith a minimal length of traces. To use an electrolytic
capacitor, add a 0.01 μF to 0.1 μF bypass capacitor, C Px,
in parallel near these pins used for the same phase.
U1

VBx

S

τ = CBOOTx × R BOOTx ,

(3)
Set

where CBOOTx is the optimized capacitance of thebootstrap capacitor, and RBOOTx is the resistance of thecurrent-limiting resistor (210 Ω ± 20%).

Input
logic

HINx

Q

HOx

R

Pulse
generator Reset

HSx

COM1
6

DBOOT1 RBOOT1
DBOOT2 RBOOT2

DBOOT3 RBOOT3

VB1

1
CBOOT1

VB2

HINx

3

VCC
4
VCC1

6

VBB
HO3
HO2
HO1
U
High-side
MIC

23
VCC2
21
Low-side
COM2 MIC

10

0
Set

CBOOT3
VDC

COM1

V

Internal Level-shifting Circuit

2
CBOOT2

VB3

Figure 11-3.

24
12

0
Reset

0
M

VBx–HSx
11
W1

VBS(ON)0

VBS(OFF)
Stays logic highQ

Figure 11-2.

Bootstrap Circuit

Figure 11-3 shows an internal level-shifting circuit. A
high-side output signal, HOx, is generated according toan input signal on the HINx pin. When an input signal
on the HINx pin transits from low to high (rising edge),a “Set” signal is generated. When the HINx input signaltransits from high to low (falling edge), a “Reset” signal
is generated. These two signals are then transmitted tothe high-side by the level-shifting circuit and are input
to the SR flip-flop circuit. Finally, the SR flip-flop
circuit feeds an output signal, Q (i.e., HOx).
Figure 11-4 is a timing diagram describing how noiseor other detrimental effects will improperly influence
the level-shifting process. When a noise-induced rapid
voltage drop between the VBx and output pins (U, V, or
W1; hereafter “VBx–HSx”) occurs after the Set signal
generation, the next Reset signal cannot be sent to theSR flip-flop circuit. And the state of an HOx signal
stays logic high (or “H”) because the SR flip-flop does
not respond. With the HOx state being held high (i.e.,0Figure 11-4.

11.2.5

VCC1 and VCC2

These are the logic supply pins for the built-in control
MIC. The VCC1 and VCC2 pins must be externallyconnected on a PCB because they are not internallyconnected. To prevent malfunction induced by supply
ripples or other factors, put a 0.01 μF to 0.1 μF ceramic
capacitor, CVCC, near these pins. To prevent damage
caused by surge voltages, put an 18 V to 20 V Zener
diode, DZ, between the VCCx and COMx pins.
Voltages to be applied between the VCCx and COMx
pins should be regulated within the recommended
operational range of VCC, given in Section 2.

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Waveforms at VBx–HSx Voltage Drop

18

SLA68xxMH Series
temperatures and junction temperatures have sufficientmargins against the absolute maximum ranges, specified
in Section 1.

4 VCC1CVCC1VCC

6 COM1

DZ

Table 11-1. Input Signals for HINx and LINx Pins

23 VCC2

Parameter
Input
Voltage
Input Pulse
Width
PWM
CarrierFrequency
Dead Time

CVCC2
21 COM2

Figure 11-5.

11.2.6

VCCx Pin Peripheral Circuit

COM1 and COM2

These are the logic ground pins for the built-in
control MICs. The COM1 and COM2 pins should beconnected externally on a PCB because they are notinternally connected. Varying electric potential of thelogic ground can be a cause of improper operations.
Therefore, connect the logic ground as close and short
as possible to a shunt resistor, RS, at a single-point
ground (or star ground) which is separated from thepower ground (see Figure 11-6).
U1

VBB 10VDC
CS

6 COM1LS1 1621 COM2

LS2 14

Connect the COM1 andCOM2 pins on a PCB.

Figure 11-6.

11.2.7

Low Level Signal

3 V < VIN < 5.5 V

0 V < VIN < 0.5 V≥0.5 μs≥0.5 μs≤20 kHz≥1.5 μs

U1
HINx(LINx)

5V
2 kΩ

2 kΩ

20 kΩ

COM1
(COM2)

Figure 11-7.

CDC

Internal Circuit Diagram of HINx or
LINx PinRS

U1Create a single-point
ground (a star ground)near R S, but keep it
separated from the power
ground.

Connections to Logic Ground

HIN1, HIN2, and HIN3;
LIN1, LIN2, and LIN3

These are the input pins of the internal motor drivers
for each phase. The HINx pin acts as a high-side
controller; the LINx pin acts as a low-side controller.
Figure 11-7 shows an internal circuit diagram of the
HINx or LINx pin. This is a CMOS Schmitt trigger
circuit with a built-in 20 kΩ pull-down resistor, and its
input logic is active high.
Input signals applied across the HINx–COMx and the
LINx–COMx pins in each phase should be set within
the ranges provided in Table 11-1, below. Note thatdead time setting must be done for HINx and LINx
signals because the IC does not have a dead time
generator.
The higher PWM carrier frequency rises, the more
switching loss increases. Hence, the PWM carrier
frequency must be set so that operational caseInput
signal

RIN1x
HINx/
LINx

RIN2x

CINx

Controller

Figure 11-8.

Filter Circuit for HINx or LINx Pin

If the signals from the microcontroller become
unstable, the IC may result in malfunctions. To avoid
this event, the outputs from the microcontroller output
line should not be high impedance. Also, if the tracesfrom the microcontroller to the HINx or LINx pin (orboth) are too long, the traces may be interfered by noise.
Therefore, it is recommended to add an additional filter
or a pull-down resistor near the HINx or LINx pin as
needed (see Figure 11-8).
Here are filter circuit constants for reference:–

RIN1x: 33 Ω to 100 Ω–

RIN2x: 1 kΩ to 10 kΩ

–CINx: 100 pF to 1000 pF

Care should be taken in adding RIN1x and RIN2x to thetraces. When they are connected to each other, the input
voltage of the HINx and LINx pins becomes slightly
lower than the output voltage of the microcontroller.

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High Level Signal

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11.2.8OCL

During OCL operation, the OCL pin logic level islow. To turn off the high- or low-side transistors during
the OCL operation, connect the OCL pin to the SD1 or
SD2 pin according to which side of transistors are to beturned off.
Figure 11-9 illustrates an internal circuit diagram of
the OCL pin and its peripheral circuit. Because of its
open-collector nature, the OCL pin should be tied by apull-up resistor, RCL, to the external power supply,
which should range from 3.0 V to 5.5 V. Whenconnecting the OCL and SDx pins, it is recommended touse a 1 kΩ to 10 kΩ pull-up resistor. To suppress noise,
add a filter capacitor, CCL, near the IC with minimizing
a trace length between the OCL and COM2 pins. CCL
should have a capacitance of 0.001 μF to 0.01 µF.
Leave the OCL pin open if not used.
For more details on the OCL, see Section 11.3.4.
VCL
RCL

U1

SDx
OCL 50 Ω
17

tBK

0.53 V
2 kΩ

Filter16

LS1

to 5.5 V.
RRC should have a resistance of 33 kΩ to 680 kΩ; CRC
should have a capacitance of 1000 pF to 0.0047 μF.
If RRC is left open, the IC cannot release the OCP
operation. Conversely, if RRC is shorted, the IC cannot
activate the OCP circuit. If CRC is left open, tP becomesshorter and the IC releases the OCP operation in ashorter time correspondingly. Therefore, care should betaken when you set these components.
Figure 11-11 is a timing chart showing the RC pin
waveform during the OCP operation. The enabled OCP
circuit turns off the low-side transistors and puts theSD2 pin into a low state. (Section 11.3.5 provides moredetails on the OCP.) At the same time, the internal
power MOSFET of the RC pin, QRC, turns on, then the
RC pin becomes logic low. QRC turns off about 5 μs
after the QRC turn-on. Subsequently, the RC pin voltage
increases with the time constant which is determined by
RRC and CRC. When the RC pin voltage reaches 2.46 V,
the IC releases the OCP operation.
The OCP Hold Time, tP, depends on the external
power supply voltage, VRC. The approximate value of tP
is calculated by the following equations:● When External Power Supply Voltage, VRC = 3.3 V:

CCL
200 kΩ

t P = 1.35 × R RC × CRC .

(4)

21
COM2

● When External Power Supply Voltage, VRC = 5 V:
Figure 11-9. Internal Circuit Diagram of OCL Pin and Its
Peripheral Circuit

11.2.9Figure 11-10 is an internal circuit diagram describing
the RC pin and its peripheral circuit.

RRC

(5)

Here is an example: when VRC = 5 V, RRC = 330 kΩ,and CRC = 0.0047 μF, we find that tRC = 1 ms.

RC

VRC

t RC = 0.65 × R RC × CRC .

LS1

tBK

VTRIP
0

U1
2.46 V

RC

RC

t

5 µs

15
CRC

0

tP

SD1
COM2

21

Figure 11-10.

2.46 V
50 Ω

QRCInternal Circuit Diagram of RC Pin and
Its Peripheral Circuit

The RC pin should be connected to a pull-up resistor,
RRC, and a capacitor, CRC, which determine a time from
OCP activation until OCP release (i.e., the OCP Hold
Time, tP). Because of its open-drain nature, the RC pinshould be tied by the pull-up resistor, RRC, to theexternal power supply, which should range from 3.0 V

0Figure 11-11.

t

RC Pin Waveform during OCP
Operation

11.2.10 SD1 and SD2
These pins operate as the fault signal outputs and the
shutdown signal inputs. Section 11.3.1 provides detailed
functional descriptions on the fault signal output;
Section 11.3.2 describes the shutdown function.

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Figure 11-12 illustrates an internal circuit diagram of
the SDx pin and its peripheral circuit. Note that the SDx
pin does not respond to a pulse shorter than an internalfilter of 3.3 μs (typ.). Because of its open-collector
nature, the SDx pin should be tied by a pull-up resistor,
RSDx, to the external power supply, which should range
from 3.0 V to 5.5 V. It is recommended to use a 3.3 kΩ
to 10 kΩ pull-up resistor. To suppress noise, add a filter
capacitor, CSDx, near the IC with minimizing a trace
length between the SDx and COMx pins. CSDx shouldhave a capacitance of 0.001 μF to 0.01 µF.
VSDx

U1

RSDx

SD1
(SD2)

11.3.23.3 µs (typ.)Blanking
filter

INT
50 Ω

CSDx

undervoltage lockout for power supply (UVLO_VCC2),
the overcurrent protection (OCP), and the thermal
shutdown (TSD). While the SD2 pin is in a low state, all
the low-side transistors turn off. The external
microcontroller receives the fault signals with its
interrupt pin (INT), and must be programmed to put the
HINx and LINx pins to logic low within thepredetermined OCP hold time, tP. tP is determined by
the value of the pull-up resistor and capacitor which areexternally connected to the RC pin (see Section 11.3.5).

QSDx

Output SW turn-off
and QSDx turn-on

COM1(COM2)

Shutdown Signal Input

The SDx pin also acts as the input pin of shutdown
signals. When the SD1 pin becomes logic low, all thehigh-side transistors turn off. When the SD2 pin
becomes logic low, all the low-side transistors turn off.
The voltages and pulse widths of the shutdown
signals to be applied are listed in Table 11-2.
Table 11-2. Shutdown Signals

Figure 11-12.

Internal Circuit Diagram of SDx Pin
and Its Peripheral Circuit

11.3 Protection Functions
This section describes the various protection circuits
provided in the IC. The protection circuits are as
follows: the undervoltage lockout for power supplies(UVLO) of the VBx, VCC1, and VCC2 pins; theovercurrent protection (OCP); the thermal shutdown(TSD). In case one or more of the following protections
are actuated, the SD1 or SD2 pin becomes logic low. By
receiving a fault signal from the SDx pin, the external
microcontroller can take a protective step such as
turning off all the transistors. The external
microcontroller can also shut down IC operations by
inputting a fault signal to the SDx pin.
In the following functional descriptions, “HOx”
denotes a gate input signal on the high-side transistor,
whereas “LOx” denotes a gate input signal on the lowside transistor. “VBx–HSx” refers to the voltages
between the VBx pin and output pins (U, V, and W1).

Parameter
Input
Voltage
Input Pulse
WidthHigh Level Signal

Low Level Signal

3 V < VIN < 5.5 V

0 V < VIN < 0.5 V

—

≥6 μs

Connecting the SD1 or SD2 pin to the OCL pinallows the IC to turn off the high- or low-side transistors
at OCL activation (see Section 11.3.4).

11.3.3

Undervoltage Lockout for Power
Supply (UVLO)

In case the gate-driving voltages of the output
transistors decrease, their steady-state power
dissipations increase. This overheating condition may
cause permanent damage to the IC in the worst case. To
prevent this event, the IC has the undervoltage lockout(UVLO) circuits for each of the VBx, VCC1, and VCC2
pins.

11.3.3.1. VBx Pin (UVLO_VB)
11.3.1

Fault Signal Output

The SDx pin is logic high in normal operation and islogic low in fault signal output operation.
● SD1
The SD1 pin becomes logic low while the VCC1 pin
undervoltage lockout for power supply (UVLO_VCC1)
is operating.
● SD2
The SD2 pin becomes logic low while one or more of
the following protections are operating: the VCC2 pin

Figure 11-13 shows operational waveforms of the
VBx pin undervoltage lockout for power supply (i.e.,
UVLO_VB).
When the voltage between the VBx and output pins
(VBx–HSx) decreases to the Logic Operation Stop
Voltage (VBS(OFF) = 10.0 V) or less, the UVLO_VB
circuit in the corresponding phase gets activated andsets an HOx signal to logic low. When the voltage
between the VBx and HSx pins increases to the Logic
Operation Start Voltage (VBS(ON) = 10.5 V) or more, theIC releases the UVLO_VB operation. Then, the HOx
signal becomes logic high at the rising edge of the first

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SLA68xxMH Series
input command after the UVLO_VB release.
Any fault signals are not output from the SDx pin
during the UVLO_VB operation. The VBx pin has aninternal filter circuit to prevent noise-induced
malfunctions.
HINx
0increases to the Logic Operation Start Voltage(VCC(ON) = 11.5 V) or more, the IC releases the
UVLO_VCC2 operation. The IC then resumes
transmitting an LOx signal according to an input
command on the LINx pin. During the UVLO_VCC2
operation, the SD2 pin becomes logic low and sends
fault signals.
The VCC2 pin has an internal filter circuit to prevent
noise-induced malfunctions.

t

LINx
HINx

0
UVLO_VB
operation

VBx−HSxt0t

VBS(OFF)LINx

VBS(ON)UVLO release0t
HOx restarts at positive edge
after UVLO_VB release.

HOxt

UVLO_VCC1
operation0

VCC1

VCC(ON)VCC(OFF)UVLO release
0

0

t

t
HOx restarts at positive edge
after UVLO_VCC1 release.

LOx
HOx
0
t
No SDx output at UVLO_VB

SDx

0

t

LOx
0

t

0

UVLO_VB Operational Waveforms

SD1t

Figure 11-13.

0t11.3.3.2. VCC1 Pin (UVLO_VCC1)
Figure 11-14 shows operational waveforms of the
VCC1 pin undervoltage lockout for power supply (i.e.,
UVLO_VCC1).
When the VCC1 pin voltage decreases to the Logic
Operation Stop Voltage (VCC(OFF) = 11.0 V) or less, theUVLO_VCC1 circuit gets activated and sets an HOx
signal to logic low. When the VCC1 pin voltage
increases to the Logic Operation Start Voltage(VCC(ON) = 11.5 V) or more, the IC releases the
UVLO_VCC1 operation. Then, the HOx signal
becomes logic high at the rising edge of the first input
command after the UVLO_VCC1 release. During the
UVLO_VCC1 operation, the SD1 pin becomes logic
low and sends fault signals.
The VCC1 pin has an internal filter circuit to prevent
noise-induced malfunctions.

Figure 11-14.

UVLO_VCC1 Operational Waveforms

HINx
0
t

LINx
0

t

UVLO_VCC2
operation

VCC2

VCC(OFF)VCC(ON)

0

t

HOx
0

11.3.3.3. VCC2 Pin (UVLO_VCC2)
Figure 11-15 shows operational waveforms of the
VCC2 pin undervoltage lockout for power supply (i.e.,
UVLO_VCC2).
When the VCC2 pin voltage decreases to the Logic
Operation Stop Voltage (VCC(OFF) = 11.0 V) or less, theUVLO_VCC2 circuit gets activated and sets an LOx
signal to logic low. When the VCC2 pin voltaget
LOx responds to input signal.

LOx
0
t

SD2
0

t

Figure 11-15.

UVLO_VCC2 Operational Waveforms

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SLA68xxMH-DSE Rev.1.3

SLA68xxMH Series
11.3.4

Overcurrent Limit (OCL)The overcurrent limit (OCL) is a protection against
relatively low overcurrent conditions. When the LS1 pin
voltage increases to the Current Limit Reference
Voltage (VLIM = 0.53 V) or more, and remains in thiscondition for a period of the Current Limit Blanking
Time (tBK = 2.0 μs) or longer, the OCL circuit isactivated. Then, the OCL pin goes logic low. When theLS1 pin voltage falls below VLIM (0.53 V), the OCL pin
logic level becomes high.
Figure 11-16 is a timing chart that represents
operational waveforms during the OCL operation where
the OCL and SD1 pins are externally connected on a
PCB. The SD1-OCL pin connection allows the IC toturn off the high-side transistors at OCL activation.
During the OCL operation, the gate logic levels of the
low-side transistors respond to an input command on the
LINx pin. The SD1 pin has an internal filter of 3.3 μs(typ.). After the SD1 and OCL pins have become logic
high, the high-side transistors remain turned off until thefirst low-to-high transition on an HINx input signal
occurs (i.e., edge-triggered).

a PCB. The LS1 pin voltage increases proportionally toa rise in the current flowing through the external shunt
resistor, RS. The built-in dedicated circuit monitors
changes in the LS1 pin voltage to detect overcurrents.
Figure 11-18 is a timing chart that represents
operational waveforms during OCP operation. When theLS1 pin voltage increases to the OCP Threshold
Voltage (VTRIP = 1.0 V) or more, and remains in thiscondition for a period of the OCP Blanking Time(tBK = 2.0 μs) or longer, the OCP circuit is activated.
When the OCP is activated, the IC puts both the LOx
and SD2 outputs to a low state.
The current flowing through RS decreases while theLOx signal is in the low state. Even if the LS1 pin
voltage falls below VTRIP, the IC holds the SD2 pin in
the low state for a fixed OCP hold time (tP). Then, theoutput transistors operate according to input signals. tP
is determined by the RC pin. For details on the RC pin
setting, see Section 11.2.9.
VBB
10

U1
HOU

W1
11
U
24
V
12
W2
13

HOV
HOW

HINx
LOU

0

LOV

t

LINx

LOW

tBK

0

t

LS2
14

1V

LS1
16

2 kΩ

FilterLS1
200 kΩ

VLIM

M

COM2
21

RS

0

t

Figure 11-17.

tBK

OCL
SD1
0

3.3 µs (typ.)HOx restarts at positive tedge after OCL release.

HOx

Internal Circuit Diagram of LS1 Pin and
Its Peripheral Circuit

HINx
0
t

LINx

0

t

0

LOx

tBK

tBK

tBK

t

LS1

0
t

Figure 11-16.

OCL Operational Waveforms(OCL = SD)

VTRIP
VLIM
0
t

HOx
0
t

11.3.5

Overcurrent Protection (OCP)The overcurrent protection (OCP) is a protection
against large inrush currents (i.e., high di/dt).
Figure 11-17 is an internal circuit diagram describing
the LS1 pin and its peripheral circuit. The LS1 pinshould be connected to an external shunt resistor, RS, on

0t
SD1 restarts
automatically after tP.

SD1
tP
0

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LOx responds to input signal.

LOx

0

23

SLA68xxMH Series
Figure 11-18.

OCP Operational Waveforms

The OCP is used for detecting abnormal conditions,such as an output transistor shorted. In case short-circuit
conditions occur repeatedly, the output transistors canbe destroyed. To prevent such event, the external
microcontroller, where a fault signal from the SD2 pin
is input via its interrupt pin (INT), must be programmed
to put the HINx and LINx pins to logic low within apredetermined OCP hold time, tP.
For proper shunt resistor setting, your applicationmust meet the following:● Use the shunt resistor that has a recommended
resistance, RS (see Section 2).
● Keep the current through the output transistors below
the rated output current (pulse), IOP (see Section 1).
It is required to use a resistor with low internal
inductance because high-frequency switching current
will flow through the shunt resistor, RS. In addition,choose a resistor with allowable power dissipationaccording to your application.
Note that overcurrents are undetectable when one ormore of the U, V, and W1/W2 pins or their traces areshorted to ground (ground fault). In case any of thesepins falls into a state of ground fault, the output
transistors may be destroyed.

11.3.6

Thermal Shutdown (TSD)

The IC incorporates the thermal shutdown (TSD)
circuit. Figure 11-19 shows TSD operational waveforms.
In case of overheating (e.g., increased power dissipation
due to overload, or elevated ambient temperature at thedevice), the IC puts both the LOx and SD2 outputs to alow state.

Figure 11-19.

TSD Operational Waveforms

The TSD circuit in the MIC monitors temperatures(see Section 6). When the temperature of the MIC
exceeds
the
TSD
OperatingTemperature(TDH = 135 °C), the corresponding TSD circuit isactivated. When the temperature of the MIC decreases
to the TSD Releasing Temperature (TDL = 105 °C) or
less, the shutdown condition is released. The transistors
then resume operating according to input signals.
Note that junction temperatures of the output
transistors themselves are not monitored; therefore, do
not use the TSD function as an overtemperature
prevention for the output transistors.

12. Design Notes
12.1 PCB Pattern Layout
Figure 12-1 shows a schematic diagram of a motor
drive circuit. The circuit consists of current paths having
high frequencies and high voltages, which also bringabout negative influences on IC operation, noiseinterference, and power dissipation. Therefore, PCB
trace layouts and component placements play animportant role in circuit designing.
Current loops, which have high frequencies and highvoltages, should be as small and wide as possible, inorder to maintain a low-impedance state. In addition,
ground traces should be as wide and short as possible sothat radiated EMI levels can be reduced.

VDC

VBB
10

CDC

High-side
MIC
RS

HINx
24

0

LINx

12 V
W1
11
W2
13

0
TSD operation

Tj(MIC)

Ground traces
should be wideand short.

M

Low-side
MIC

TDH

LS2
14
LS1
16

TDL
0

HOx
0

U

LOx responds to input signal.

High-frequency, highvoltage current loops
should be as small andwide as possible.

Figure 12-1.

High-frequency, High-voltage Current
Paths

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SD2
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SLA68xxMH-DSE Rev.1.3

SLA68xxMH Series
12.2 Considerations in Heatsink Mounting

to the COM2 pin, then leave other unused pins open.

The following are the key considerations and theguidelines for mounting a heatsink:● It is recommended to use a metric screw of M2.5. To
tighten the screws, use a torque screwdriver. Tighten
the two screws firstly up to about 30% of the
maximum screw torque, then finally up to 100% of
the prescribed maximum screw torque. Perform
appropriate tightening within the range of screw
torque defined in Section 4.
● When mounting a heatsink, it is recommended to use
silicone greases. If a thermally conductive sheet or anelectrically insulating sheet is used, package cracks
may be occurred due to creases at screw tightening.
Therefore, you should conduct thorough evaluations
before using these materials.
● When applying a silicone grease, make sure that there
are no foreign substances between the IC and aheatsink. Extreme care should be taken not to apply asilicone grease onto any device pins as much as
possible.

VBB
10High-side
MIC
COM1

Q1H

Q2H

6
24

● All the high-side drains are internally connected to
the VBB pin.
● In the U-phase, the high-side source and the low-side
drain are internally connected to the U pin.
(In the W-phase, the high- and low-side transistors
are unconnected inside the IC.)The gates of the high-side transistors are pulled down
to the corresponding output (U, V, and W1) pins;
similarly, the gates of the low-side transistors are pulled
down to the COM2 pin.
When measuring the breakdown voltage or leakage
current of the transistors, note that all of the output (U,V, and W1), LSx, and COMx pins must be
appropriately connected. Otherwise, the switchingtransistors may result in permanent damage.

U

11 W1
12 V
Q1L

Q2L Q3L

13 W2

Low-side
MIC
14
COM2

21

16

LS2
LS1

Figure 12-2. Typical Measurement Circuit for Highside Transistor (Q1H) in U-phase12.3 Considerations in IC Characteristics
Measurement
When measuring the breakdown voltage or leakage
current of the transistors incorporated in the IC, notethat the gate and source of each transistor should havethe same potential. Moreover, care should be taken
during the measurement because each transistor isconnected as follows:

V

Q3H

VBB
10
High-side
MIC
COM1

Q1H

Q2H

Q3H

6
24

U

11 W1
12 V
Q1L
Low-sideMIC

Q2L Q3L

13 W2

14
COM2

21

16

LS2

V

LS1

Figure 12-3. Typical Measurement Circuit for Lowside Transistor (Q1L) in U-phase

The following are circuit diagrams representing
typical measurement circuits for breakdown voltage:
Figure 12-2 shows the high-side transistor (Q1H) in the
U-phase; Figure 12-3 shows the low-side transistor(Q1L) in the U-phase. And all the pins that are notrepresented in these figures are open.
When measuring the high-side transistors, leave all
the pins not be measured open. When measuring thelow-side transistors, connect the LSx pin to be measured
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SLA68xxMH Series
13. Calculating Power Losses andEstimating Junction TemperatureThis section describes the procedures to calculate
power losses in output transistors (power MOSFETs),and to estimate a junction temperature. Note that thedescriptions listed here are applicable to the IC, which iscontrolled by a 3-phase sine-wave PWM driving
strategy. For quick and easy references, we offer
calculation support tools online. Please visit our website
to find out more.
● DT0050: SLA687xMH and SLA686xMH Series
Calculation Tool
http://www.semicon.sanken-ele.co.jp/en/calctool/mosfet_caltool_en.html
Total power loss in a power MOSFET can beobtained by taking the sum of the following losses:
steady-state loss, PRON; switching loss, PSW; the steadystate loss of a body diode, PSD. In the calculation
procedure we offer, the recovery loss of a body diode,
PRR, is considered negligibly small compared with theratios of other losses.
The following subsections contain the mathematicalprocedures to calculate these losses (PRON, PSW, and PSD)
and the junction temperature of all power MOSFETs
operating.

13.1 Power MOSFET Steady-state Loss,
PRON
Steady-state loss in a power MOSFET can becomputed by using the RDS(ON) vs. ID curves, listed in
Section 14.3.1. As expressed by the curves in Figure
13-1, linear approximations at a range the ID is actuallyused are obtained by: RDS(ON) = α × ID + β.

PRON =

12.0

y = 2.2x + 9.1
75°C

10.0

DT =

1 + M × sin(φ + θ),
2

M is the modulation index (0 to 1),cosθ is the motor power factor (0 to 1),
IM is the effective motor current (A),α is the slope of the linear approximation in the
RDS(ON) vs. ID curve, andβ is the intercept of the linear approximation in the
RDS(ON) vs. ID curve.

13.2 Power MOSFET Switching Loss, PSW
Switching loss in a power MOSFET can be calculated
by Equation (7), letting IM be the effective current valueof the motor:
VDC√2
× fC × αE × IM ×
.
π
300

(7)

Where:
fC is the PWM carrier frequency (Hz),VDC is the main power supply voltage (V), i.e., the
VBB pin input voltage, andαE is the slope on the switching loss curve (see Section
14.3.2).

8.0
6.0
25°C

4.0

(6)

Where:
ID is the drain current of the power MOSFET (A),RDS(ON) is the drain-to-source on-resistance of thepower MOSFET (Ω),
DT is the duty cycle, which is given by

PSW =

125°C

1 π
∫ I (φ)2 × R DS(ON) (φ) × DT × dφ
2π 0 D1
3= 2√2α ( +M × cos θ) IM 3
3π 32
1 1
+ 2β ( +M × cos θ) IM 2 .
8 3π

VCC = 15 V

14.0

RDS(ON) (Ω)

The values gained by the above calculation are thenapplied as parameters in Equation (6), below. Hence,the equation to obtain the power MOSFET steady-state
loss, PRON, is:

2.0
0.0
0.0

0.5

1.0

1.5

ID (A)

Figure 13-1.

Linear Approximate Equation of RDS(ON)vs. ID Curve

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SLA68xxMH Series
13.3 Body Diode Steady-state Loss, PSD
Steady-state loss in the body diode of a power
MOSFET can be computed by using the VSD vs. ISD
curves, listed in Section 14.3.1. As expressed by the
curves in Figure 13-2, linear approximations at a range
the ISD is actually used are obtained by: VSD = α × ISD +β.
1.2

VSD (V)The junction temperature of all power MOSFETs
operating, TJ, can be estimated with Equation (9):TJ = R J−C × {(PON + PSW + PSD ) × 6} + TC .

(9)

Where:
RJ-C is the junction-to-case thermal resistance (°C/W)
of all the power MOSFETs operating, andTC is the case temperature (°C), measured at the point
defined in Figure 3-1.

VCC = 15 V
1.0

13.4 Estimating Junction Temperature ofPower MOSFET

25°C

0.8

y = 0.23 + 0.59

0.6
125°C

75°C

0.4
0.2
0.0
0.0

0.5

1.0

1.5

ISD (A)

Figure 13-2.

Linear Approximate Equation of VSD vs.
ISD Curve

The values gained by the above calculation are thenapplied as parameters in Equation (8), below. Hence,the equation to obtain the body diode steady-state loss,
PSD, is:PSD =1 π∫ V (φ) × ISD (φ) × (1 − DT) × dφ
2π 0 SD

1 1
4= α( −
M × cos θ) IM 2
2 2 3π√2 1 π+β ( − M × cos θ) IM .
π
2 8

(8)

Where:
VSD is the source-to-drain diode forward voltage of thepower MOSFET (V),ISD is the source-to-drain diode forward current of thepower MOSFET (A),DT is the duty cycle, which is given byDT =1 + M × sin(φ + θ),
2

M is the modulation index (0 to 1),cosθ is the motor power factor (0 to 1),
IM is the effective motor current (A),α is the slope of the linear approximation in the VSD vs.
ISD curve, andβis the intercept of the linear approximation in the
VSD vs. ISD curve.

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SLA68xxMH Series
14. Performance Curves
14.1 Transient Thermal Resistance Curves
The following graphs represent transient thermal resistance (the ratios of transient thermal resistance), with steadystate thermal resistance = 1.

Ratio of Transient Thermal
Resistance

1.00

0.10

0.01
0.001

0.01

Figure 14-1.

0.1Time (s)10Transient Thermal Resistance

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SLA68xxMH Series
14.2 Performance Curves of Control Parts
Figure 14-2 to Figure 14-27 provide performance curves of the control parts integrated in the SLA6870MH and the
SLA6860MH series, including variety-dependent characteristics and thermal characteristics. TJ represents the junction
temperature of the control parts.
Table 14-1. Typical Characteristics of Control Parts
Figure Number
Figure 14-2
Figure 14-3
Figure 14-4
Figure 14-5
Figure 14-6
Figure 14-7
Figure 14-8
Figure 14-9
Figure 14-10
Figure 14-11
Figure 14-12
Figure 14-13
Figure 14-14
Figure 14-15
Figure 14-16
Figure 14-17
Figure 14-18
Figure 14-19
Figure 14-20
Figure 14-21
Figure 14-22
Figure 14-23
Figure 14-24
Figure 14-25
Figure 14-26
Figure 14-27

Figure Caption
Logic Supply Current, ICC vs. TC (HINx = 0 V, LINx = 0 V)
Logic Supply Current, ICC vs. TC (HINx = 5 V, LINx = 5 V)
Logic Supply Current, ICC vs. VCCx Pin Voltage, VCC
Logic Supply Current in 1-phase Operation (HINx = 0 V), IBS vs. TC
Logic Supply Current in 1-phase Operation (HINx = 5 V), IBS vs. TC
VBx Pin Voltage, VB vs. Logic Supply Current, IBS (HINx = 0 V)
Logic Operation Start Voltage, VBS(ON) vs. TC
Logic Operation Stop Voltage, VBS(OFF) vs. TC
Logic Operation Start Voltage, VCC(ON) vs. TC
Logic Operation Stop Voltage, VCC(OFF) vs. TC
UVLO_VB Filtering Time vs. TC
UVLO_VCC1 Filtering Time vs. TC
UVLO_VCC2 Filtering Time vs. TC
High Level Input Signal Threshold Voltage, VIH vs. TC
Low Level Input Signal Threshold Voltage, VIL vs. TC
Input Current at High Level (HINx or LINx), I IN vs. TC
High-side Turn-on Propagation Delay vs. TC (from HINx to HOx)
Low-side Turn-on Propagation Delay vs. TC (from LINx to LOx)
Minimum Transmittable Pulse Width for High-side Switching, tHIN(MIN) vs. TC
Minimum Transmittable Pulse Width for Low-side Switching, tLIN(MIN) vs. TC
SD1 Pin Filtering Time vs. TC
SD2 Pin Filtering Time vs. TC
Current Limit Reference Voltage, VLIM vs. TC
OCP Threshold Voltage, VTRIP vs. TC
OCP Hold Time, tP vs. TC
OCP Blanking Time, tBK(OCP) vs. TC; Current Limit Blanking Time, tBK(OCL) vs. TC

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SLA68xxMH Series

VCCx = 15 V, HINx = 0 V, LINx = 0 V

3.5

Max.

2.5

Typ.

2.0

Min.

1.5

Max.

3.5
3.0

ICC (mA)

ICC (mA)

3.0

VCCx = 15 V, HINx = 5 V, LINx = 5 V

4.0

Min.

2.0
1.5

1.0

1.0

0.5

0.5

0.0

Typ.

2.5

0.0
-30

0

30

60

90

120

150

-30

0

30

60

90

120

150

TC (°C)TC (°C)

Figure 14-2. Logic Supply Current, ICC vs. TC(HINx = 0 V, LINx = 0 V)

Figure 14-3. Logic Supply Current, ICC vs. TC(HINx = 5 V, LINx = 5 V)

HINx = 0 V, LINx = 0 V

3.0

VBx = 15 V, HINx = 0 V

250

2.8

200
Max.

2.4
125°C

2.2

25°C
−30°C

2.0

IBS (µA)

ICC (mA)

2.6
150

Typ.
Min.

100
50

1.8
1.6
12

13

14

15

16

17

18

19

0

20

-30

0

30

60

VCC (V)

Figure 14-4.

Logic Supply Current, ICC vs. VCCx Pin
Voltage, VCC

Figure 14-5.

VBx = 15 V, HINx = 5 V

250

Max.

200
150

Min.

100
50
0
0

30

60

90

120

150

IBS (µA)

IBS (µA)

Typ.

-30

120

150

Logic Supply Current in 1-phase Operation(HINx = 0 V), IBS vs. TC

VBx = 15 V, HINx = 0 V

180
160
140
120
100
80
60
40
20
0

－30°C

12

13

TC (°C)

Figure 14-6. Logic Supply Current in 1-phase
Operation (HINx = 5 V), IBS vs. TC

14

15

16

17

18

125°C
25°C

19

20

VCC (V)

Figure 14-7.

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90TC (°C)VBx Pin Voltage, VB vs. Logic Supply
Current, IBS (HINx = 0 V)

30

SLA68xxMH Series
11.5

12.0

11.0

11.5
11.0

Typ.

10.5

Min.

10.0

VBS(OFF) (V)VBS(ON) (V)

Max.
10.5

Max.
Typ.

10.0

Min.

9.5
9.0

9.5

8.5

9.0
-30

0

30

60

90

120

-30

150

0

30

TC (°C)

Figure 14-8.

60

90

120

Logic Operation Start Voltage, VBS(ON)vs. TC

Figure 14-9.

13.0

Logic Operation Stop Voltage, VBS(OFF) vs.
TC

12.5

12.5

12.0
Max.
Typ.

11.5

Min.

11.0

Max.

11.5

VCC(OFF) (V)VCC(ON) (V)

12.0

10.5

Typ.
11.0
Min.
10.5
10.0

10.0

9.5
-30

0

30

60

90

120

150

-30

0

30

TC (°C)

Logic Operation Start Voltage, VCC(ON)vs. TC

5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0

Max.
Typ.
Min.

-30

0

30

60

90

120

150

Figure 14-11.

UVLO_VB Filtering Time vs. TC

120

5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0

150

Max.
Typ.
Min.

-30

0

30

60

90

120

150

TC (°C)

Figure 14-13.

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90

Logic Operation Stop Voltage, VCC(OFF)vs. TCTC (°C)

Figure 14-12.

60

TC (°C)UVLO_VCC1 Filtering Time (µs)

Figure 14-10.

UVLO_VB Filtering Time (µs)

150

TC (°C)UVLO_VCC1 Filtering Time vs. TC

31

SLA68xxMH Series

2.6
2.4
Max.
Typ.
Min.

VIH (V)UVLO_VCC2 Filtering Time (µs)

10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0

2.2

Max.

2.0

Typ.

1.8

Min.

1.6
1.4
1.2
1.0

-30

0

30

60

90

120

150

-30

0

30

TC (°C)

Figure 14-14.

60

90

120

150

TC (°C)UVLO_VCC2 Filtering Time vs. TC

Figure 14-15.

2.0

400

1.8

350

High Level Input Signal Threshold
Voltage, VIH vs. TC

INHx/INLx = 5 V
Max.

300
Max.
Typ.

1.4
1.2

IIN (µA)

VIL (V)

1.6

Min.

250

Typ.

200

Min.

150
100

1.0

50
0

0.8
-30

0

30

60

90

120

-30

150

0

30

Low Level Input Signal Threshold
Voltage, VIL vs. TC

Figure 14-17.

800

120

150

Input Current at High Level (HINx or
LINx), IIN vs. TC

800

700

Max.

700

Max.

600

Typ.

600

Typ.

500

Min.

500

Min.

400
300
200
100

tHIN(MIN) (ns)tHIN(MIN) (ns)90

TC (°C)TC (°C)

Figure 14-16.

60

400
300
200
100

0

0
-30

0

30

60

90

120

150

-30

TC (°C)

Figure 14-18.

High-side Turn-on Propagation Delay vs.
TC (from HINx to HOx)

30

60

90

120

150

TC (°C)

Figure 14-19. Low-side Turn-on Propagation Delay
vs. TC (from LINx to LOx)

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SLA68xxMH Series

400

450
Max.

400

Typ.

350

tHIN(MIN) (ns)

300
250

Min.

200
150
100

Max.
Typ.

300

tLIN(MIN) (ns)

350

250

Min.

200
150
100

50

50

0
-30

0

30

60

90

120

0

150

-30

0

30

TC (°C)

Figure 14-20. Minimum Transmittable Pulse Width for
High-side Switching, tHIN(MIN) vs. TC

7.0

5.0

6.0

120

150

5.0
Max.

3.0

Typ.

2.0

tSD2 (µs)

tDS1 (µs)

90Figure 14-21. Minimum Transmittable Pulse Widthfor Low-side Switching, tLIN(MIN) vs. TC

6.0

4.0

Max.

4.0

Min.

1.0

3.0

Typ.

2.0

Min.

1.0

0.0

0.0
-30

0

30

60

90

120

150

-30

0

30

TC (°C)

Figure 14-22.

60

90

120

150

TC (°C)SD1 Pin Filtering Time vs. TC

Figure 14-23.

1.15

1.15

1.10

1.10

1.05

Max.

1.00

Typ.
Min.

0.95
0.90

SD2 Pin Filtering Time vs. TC

Max.

1.05

VTRIP (V)VLIM (V)60

TC (°C)

Typ.

1.00

Min.

0.95
0.90

0.85

0.85
-30

0

30

60

90

120

150

-30

TC (°C)

Figure 14-24.

Current Limit Reference Voltage, VLIM vs.
TC

30

60

90

120

150

TC (°C)

Figure 14-25.

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OCP Threshold Voltage, VTRIP vs. TC

33

SLA68xxMH Series
VRC = 3.3 V, RRC = 360 kΩ, CRC = 0.0047 μF

3.5

2.8

Max.

3.0

2.6

Typ.

2.5

2.4

Min.

2.0

Typ.

1.5

Min.

2.2
2.0

tBK (µs)tP (µs)

3.0

Max.

1.0

1.8

0.5

1.6
-30

0

30

60

90

120

150

0.0
-30

TC (°C)

Figure 14-26.

OCP Hold Time, tP vs. TC

30

60

90

120

150

Tj (°C)

Figure 14-27. OCP Blanking Time, tBK(OCP) vs. TC;
Current Limit Blanking Time, tBK(OCL) vs. TC

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SLA68xxMH Series
14.3 Performance Curves of Output Parts
14.3.1

Output Transistor Performance Curves

14.3.1.1. SLA6868MH

3.0
2.0

1.2

25°C

1.0
0.8
0.6

75°C
125°C

0.4

25°C

1.0

SLA6868MH

75°C

1.4

VSD (V)

4.0

SLA6868MH

125°C

5.0

RDS(ON) (Ω)

VCC = 15 V

VCC = 15 V

6.0

0.2
0.0

0.0
0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

3.5

0.5

1.0

2.0

2.5

3.0

3.5

ISD (A)

ID (A)

Figure 14-28.

1.5

Power MOSFET RDS(ON) vs. ID

Figure 14-29.

Power MOSFET VSD vs. ISD

14.3.1.2. SLA6870MH

2.0
25°C
1.0

SLA6870MH

1.2
25°C

1.0

VSD (V)

75°C

3.0

SLA6870MH

125°C
4.0

RDS(ON) (Ω)

VCC = 15 V

VCC = 15 V

5.0

0.8
0.6

75°C
125°C

0.4
0.2
0.0

0.0
0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

0.0

0.5

1.0

Power MOSFET RDS(ON) vs. ID

Figure 14-31.

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2.0

2.5

3.0

3.5

4.0

4.5

ISD (A)

ID (A)

Figure 14-30.

1.5Power MOSFET VSD vs. ISD

35

SLA68xxMH Series
14.3.2

Switching Losses

Conditions: VBBx pin voltage = 300 V, half-bridge circuit with inductive load.
Switching Loss, E, is the sum of turn-on loss and turn-off loss.

14.3.2.1. SLA6868MH
VB = 15 V

300

TJ = 125 °C

350
300

200
150
100

200
150
100

TJ = 25 °C

50

TJ = 125 °C

250

E (µJ)E (µJ)250

SLA6868MH

350

VCC = 15 V

400

SLA6868MH

400

TJ = 25 °C

50

0

0
0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

ID (A)

Figure 14-32.

2.0

2.5

3.0

3.5

ID (A)

High-side Switching Loss

Figure 14-33.

Low-side Switching Loss

14.3.2.2. SLA6870MH
VB = 15 V

300

TJ = 125 °C

350
300

TJ = 125 °C

250

E (µJ)E (µJ)

250
200
150
100

SLA6870MH

350

VCC = 15 V

400

SLA6870MH

400

200
150
100

TJ = 25 °C

50

TJ = 25 °C

50

0

0
0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

0.0

0.5

1.0

ID (A)

Figure 14-34.

High-side Switching Loss

2.0

2.5

3.0

3.5

4.0

4.5

ID (A)

Figure 14-35.

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1.5

Low-side Switching Loss

36

SLA68xxMH Series
14.4 Allowable Effective Current Curves
The following curves represent allowable effective currents in 3-phase sine-wave PWM driving with parameters suchas typical RDS(ON) or VCE(SAT), and typical switching losses.
Operating conditions: VBB pin input voltage, VDC = 300 V; VCCx pin input voltage, VCC = 15 V; modulation index,
M = 0.9; motor power factor, cosθ = 0.8; junction temperature, T J = 150 °C.

14.4.1

SLA6868MH
fC = 2 kHz

Allowable Effective Current (Arms)

2.5

2.0

1.5

1.0

0.5

0.0
25

50

75

100

125

150

TC (°C)
Figure 14-36.

Allowable Effective Current (fC = 2 kHz): SLA6868MH
fC = 16 kHz

Allowable Effective Current (Arms)

2.5

2.0

1.5

1.0

0.5

0.0

25

50

75

100

125

150

TC (°C)
Figure 14-37.

Allowable Effective Current (fC = 16 kHz): SLA6868MH

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SLA68xxMH Series
14.4.2

SLA6870MH
fC = 2 kHz

Allowable Effective Current (Arms)

2.5

2.0

1.5

1.0

0.5

0.0
25

50

75

100

125

150

TC (°C)
Figure 14-38.

Allowable Effective Current (fC = 2 kHz): SLA6870MH
fC = 16 kHz

Allowable Effective Current (Arms)

2.5

2.0

1.5

1.0

0.5

0.0
25

50

75

100

125

150

TC (°C)
Figure 14-39.

Allowable Effective Current (fC = 16 kHz): SLA6870MH

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SLA68xxMH Series
15. Pattern Layout Example
This section contains the schematic diagrams of a PCB pattern layout example using an IC from the devices listed
in this document.

Figure 15-1.

Top View

Figure 15-2.

Bottom View

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SLA68xxMH Series

VB1 1
4 VCC1

C3

VB2 2
C8

C5
VB3 3
5 SD1
C7
6 COM1
7 HIN3
VBB 108 HIN2
9 HIN1

CN2
10

7
6
5

4
3
2

C4

C6

CN1
C1
1
2

9
8

C2

W1 11

R3
R7
R8
R9
R4
R5
R6

CN3
R1 R2
SJ1

SJ2

15 RC

LS2 14LS1 16

C11 C10 C9

1

1
2
3

V 12
W2 13

R10

D1

17 OCL18 LIN3
19 LIN2
20 LIN1

U 24

C14 C13 C12
21 COM2
22 SD2C16DZ1

23 VCC2

Figure15-3.

C17

C18

C19

C15

Circuit Diagram of PCB Pattern Layout Example

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SLA68xxMH Series
16. Typical Motor Driver Application
This section contains the information on the typical motor driver application listed in the previous section, including
a circuit diagram, specifications, and the bill of the materials used. The SD1-OCL pin connection allows the IC to turnoff the high-side transistors at OCL activation (see Section 11.3.4).
● Motor Driver SpecificationsIC

SLA6870MH

Main Supply Voltage, VDC

300 VDC (typ.)

Rated Output Power

300 W● Circuit Diagram
See Figure15-3.
● Bill of Materials
SymbolPart Type(1)(2)

Ratings

SymbolC1

Film

0.1 μF, 400 V

D1

C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19

Electrolytic

47 μF, 50 V

Ceramic

0.1 μF, 50 V

Electrolytic

47 μF, 50 V

Ceramic

0.1 μF, 50 V

Electrolytic

47 μF, 50 V

Ceramic

0.1 μF, 50 V

Ceramic

0.1 μF, 50 V

Ceramic

100 pF, 50 V

Ceramic

100 pF, 50 V

Ceramic

100 pF, 50 V

Ceramic

100 pF, 50 V

Ceramic

100 pF, 50 V

Ceramic

100 pF, 50 V

Ceramic

0.1 μF, 50 V

Electrolytic

47 μF, 50 V

Ceramic

4700 pF, 50 V

Ceramic

0.01 μF, 50 V

R1
R2
R3
R4
R5
R6
R7
R8
R9
R10(1)ZD1
IPM1
SJ1(2)
SJ2(3)
CN1
CN2
CN3

Ceramic

0.01 μF, 50 V

定格

Part Type

General7 V, 200 mA;
VF ≤ 1.2 V (IF = 5 mA,−20 to 125 °C)
330 kΩ, 1/8 W

General

3.3 kΩ, 1/8 W

General

3.3 kΩ, 1/8 W

General1 kΩ, 1/8 W

General1 kΩ, 1/8 W

General1 kΩ, 1/8 W

General1 kΩ, 1/8 W

General1 kΩ, 1/8 W

General1 kΩ, 1/8 W

Metal plate0.24Ω, 2 W

Zener diode

VZ = 21 V (max.)

IC

SLA6870MH

General-Purpose
RectifierJumperJumperPin header

Equiv. to B2P3-VH

Connector

Equiv. to MA10-1

Pin header

Equiv. to B2P5-VH

Refers to a part that requires adjustment based on operation performance in an actual application.
When connecting the OCL pin to the SD1 pin, set SJ1 = short, SJ2 = open, and insert D1.
When not connecting the OCL pin to the SD1 pin, set SJ1 = open, SJ2 = short, and D1 = open.

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SLA68xxMH Series
Important Notes● All data, illustrations, graphs, tables and any other information included in this document (the “Information”) as to Sanken’s
products listed herein (the “Sanken Products”) are current as of the date this document is issued. The Information is subject to any
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appliances, office equipment, telecommunication equipment, measuring equipment, etc.). Prior to use of the Sanken Products,
please put your signature, or affix your name and seal, on the specification documents of the Sanken Products and return them toSanken. When considering use of the Sanken Products for any applications that require higher reliability (such as transportationequipment and its control systems, traffic signal control systems or equipment, disaster/crime alarm systems, various safety
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your name and seal, on the specification documents of the Sanken Products and return them to Sanken, prior to the use of theSanken Products. The Sanken Products are not intended for use in any applications that require extremely high reliability such as:
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DSGN-CEZ-16003

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42