%RQDYHQWXUD'U6DQ-RVH&$7HO²)D[ZZZ[VFDQLPDJLQJFRP/LQHDU;5D\3KRWRGLRGH'HWHFWRU$UUD\ZLWK6LJQDO$PSOLILFDWLRQ;%56HULHVAn X-Scan Imaging XB8801R linear detector array is constructed of CMOS silicon photodiode array detector
chips mounted on a single printed-circuit board. The imaging circuit of each detector chip consists of acontiguous linear array of photodiodes, a timing generator, digital scanning shift register, an array of charge
integrating amplifiers, sample-and-hold circuits, and signal amplification chain. Each detector array generates an
End-Of-Scan (EOS) pulse that can be used to initiate the scanning of the next detector array. Thus, a longer,
continuous detector array can be formed from a daisy chain of smaller detector arrays.
For x-ray scanning applications, a scintillator material tailored to the user’s application is attached to the surfaceof the detector array to convert x-ray photons into visible light for detection by the photodiode array. The
XB8801R photodiode array is uniquely designed and processed to reduce radiation damage from the x-ray flux.
The signal processing circuits are positioned 2 mm away from the photodiode array. These circuits are shieldedfrom direct x-ray radiation using an external heavy-metal shield. The precision alignment of the metal shieldwith respect to the signal processing circuits is performed at the factory using a special molded housing and chipon-board (COB) technology.

Key Features• Large element pitch with two selectable resolution modes: 0.1 mm and 0.2 mm• Different array lengths available:
o 2.0 inches (512 pixels at 0.1 mm, 256 pixels at 0.2 mm)
o 4.0 inches (1024 pixels at 0.1 mm, 512 pixels at 0.2 mm)• 5-V power supply operation• Simultaneous integration by using an array of charge
integrating amplifiers• Sequential readout with a digital scanning shift register• Integrated CDS circuits allow low noise and wide dynamic range up to > 4000
• User-specified scintillator material GOS:Tb, CsI:Tl etc.
• Extended radiation hardness lifetimes

Applications• Linear x-ray imaging for industrial and food inspection• Linear x-ray imaging for homeland security and contraband screening;6FDQ,PDJLQJ&RUS

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Parameter

Symboli

XB8801R-2.0(high resolution0.1-mm mode)iv
0.1
0.085

XB8801R-4.0(low resolution0.2-mm mode)
0.20.170

XB8801R-4.0(high resolution0.1-mm mode)
0.1
0.085

Unit

PW

XB8801R--2.0ii(low resoluution0.2-mm moode)iii
0.20.170

Element pitch
Elementdiffusion width
Element heightNumber ofelements
Active area
lengthH–

0.300
2560.150
5120.300
5120.150
1024

mm
––

51.2

51.2

102.4

102.4mmmm
mmi

Refer to enlarged view of active area figure.
2-inch and 4-inch long detector are specified heere. Other lengths (at multiples of 0.5 inches) are availab
ble upon special request.
iii
When RS (pin 12) is tied to GND, the detectorr operates in the low 0.2-mm resolution mode. There are 256 pixels in a 2-inchdetector (XB8801R-2.0) in 0.2-mm mode. Theree are 512 pixels in a 4-inch detector (XB8801R-4.0) in 0.22-mm mode.
iv
When RS (pin 12) is tied to VDD, the detectorr operates in the high 0.1-mm resolution mode. There are 512 pixels in a 2-inchdetector (XB8801R-2.0) in 0.1-mm mode. Theree are 1024 pixels in a 4-inch detector (XB8801R-4.0) in 0.1-mm
0mode.
ii

Ŷ Enlarged view of active area 

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3KRWRGLRGH'HWHFWRUZLWK6LJQDO$PSOLILFDWLRQ;%56HULHVŶ Absolute maximum ratings
Electronic device sensitive to electrostatic discharge and x-ray radiation. Although this device features ESD
protection circuitry, permanent damage ranging from subtle performance degradation to complete device failure
may occur on devices subjected to high-energy electrostatic discharges. Furthermore, although this device
features radiation shielding for protection against anticipated x-ray radiation, permanent damage ranging from
subtle performance degradation to complete device failure may occur on devices subjected to unanticipated xray radiation (e.g. off-axis or extremely high energy radiation). Therefore, proper precautions against ESD and
x-ray radiation must be taken during handling and storage of this device.

Parameter
Supply voltage
Reference voltage
Digital input voltages
Operating temperaturev
Storage temperaturev

SymbolVDD
VREF

Min–0.3–0.3–0.3–5–10ToprTstg

Max+6VDD + 0.3
VDD + 0.3
+60+70

Unit
VV
VoCoC

Max.
5.25–Unit
VV

Humidity must be controlled to prevent the occurrence of condensation.

Ŷ Recommended terminal voltage
Parameter
Supply voltage
Reference voltage

Symbol
VDD
VREF

Min.
4.75– Typ.
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3KRWRGLRGH'HWHFWRUZLWK6LJQDO$PSOLILFDWLRQ;%56HULHVŶ Electrical characteristics [Ta = 21oC, VDD = 5 V]
Parameter
DigitalClock pulse frequencyvi
Digital input voltagevii

High level
Low level

Digital input capacitance
Digital input leakage current
High level
Digital output voltageviii
Low level
Digital output load capacitanceAnalogReference voltage input impedanceHighsensitivity
Charge amplifier
feedback capacitanceix
Lowsensitivity
Video output impedanceVideo output load capacitancePowerPower consumptionSymbol

Min.

Typ.

Max.

Unit

f(CLK)
Vih
VilCi
Ii
Voh
Vol
Co

40
VDD–1.2
0––10
VDD–0.75
0––
VDD
040+10
VDD
0–

4000
VDD
0.8––
VDD
0.450

KHz
V
V
pF
ȝAV
V
pF

Rref

5––K

Cfhs

–

0.5–pFCfls–

1.5–pF

Zv
Cv

––––

1100

K
pF

P–

200–mW

vi

Video rate is 1/4 of clock pulse frequency f(CLK).
Digital inputs include CLK, RESET, EXTSP, VMS, SNS, and RS (see pin connections).
viii
Digital outputs include Trig and EOS (see pin connections).
ix
The sensitivity selection pin (see SNS in pin connections) controls the sensitivity of the detector by selecting whether the pixel
charge amplifier feedback capacitance is Cfhs or Cfls. At Cfhs, the detector has high sensitivity. At Cfls, the detector has low
sensitivity.
vii 

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3KRWRGLRGH'HWHFWRUZLWK6LJQDO$PSOLILFDWLRQ;%56HULHVŶ Electro-optical characteristics [Ta = 21oC, VDD = 5 V, V(SNS) = 5 V (High sensitivity), 0 V (Lowsensitivity)]

Parameter

SymbolOutput offset voltagex

VosHigh sensitivity
Low sensitivity
High sensitivity
X-ray sensitivityxii
Low sensitivity
Photo response non-uniformityxiii
High sensitivity
Noisexiv
Low sensitivity
Saturation output voltage
Dark offset voltagexi

VdS
PRNU
N
Vsat

XB8801R(0.2 mm mode)
Min.
Typ.
Max.
–
VREF
––40–
40
–40
–
40–
900––
300
––10–
10–
2.0–
–
0.7–
3.0––

XB8801R(0.1 mm mode)
Min.
Typ.
Max.
–
VREF
––40–
40
–40–
40–450––150––10–
10–
1.0––
0.6–
3.0––UnitVmVV/R%mVrms
Vx

Video output is negative-going output with respect to the output offset voltage.
Difference between output signal under dark conditions and Vref with an integration time of 1 ms.
xii
Measured with tube energy of 70KVp. Other scintillations with different sensitivity are available.
xiii
Measured without scintillation. When the photodiode array is exposed to uniform light which is 50% of the saturation exposure,the Photo Response Non Uniformity (PRNU) is defined as follows:
PRNU = ǻX ÷ X × 100%
where X is the average output of all elements and ǻX is the difference between the maximum and minimum outputs.
xiv
Measured with a video data rate of 750 KHz and an integration time of 1 ms in dark state.
xi

Ŷ Output waveform of one element
Dark State

Saturation Output
Voltage (Vsat)

Output Offset
Voltage (Vos)

Saturation StateGND

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3KRWRGLRGH'HWHFWRUZLWK6LJQDO$PSOLILFDWLRQ;%56HULHVŶ Block diagram
EXTSP
4RESET 1VMS

VDD

GND

567Timing Generator

3 TRIG

CLK 2
Shift Register

8 EOS

VREF 10

Hold Circuit

9 VIDEO

SNS 11Charge Amplifier Array

1RS 122345N-1N

Photodiode ArrayŶ Timing chartxv
12345 14 15 16 17 18 19 201234567CLK

tplw (RESET)
RESET

tphw (RESET)~7.5 Clocks~6.5 Clocks
Integration Time

Video Output Period
VIDEO

12n-1nTRIG

EOS 

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3KRWRGLRGH'HWHFWRUZLWK6LJQDO$PSOLILFDWLRQ;%56HULHVtf (CLK)tr (CLK)

tplw (CLK)thtphw (CLK)
thts

ts

tplw (RESET)

tf (RESET)

Parameter
Clock pulse low/high width
Clock pulse rise/fall times
Reset pulse low widthxvi
Reset pulse high widthxvii
Reset pulse rise/fall times
Reset pulse setup timexviii
Reset pulse hold time

tphw (RESET)

tr (RESET)

Symboltplw (CLK), tphw (CLK)tr (CLK), tf (CLK)tplw (RESET)
tphw (RESET)
tr (RESET), tf (RESET)
tsth

Min.
100012 / f(CLK)2004040Typ.
–
20
16 / f(CLK)
–
20
––

Max.
–
30
––
30
––

Unit
nsnsmsμs
nsnsnsxv

The falling of Video just before the 19th falling edge of CLK after transition of RESET from High to Low corresponds to the firstpixel. The video output for the first pixel should be read around the 20th falling edge and before the subsequent rising CLK edge while
Trig is high. After the first pixel, a pixel output appears on Video at every 4th clock cycle.
Care should be taken to prevent the rising edge of the RESET during the video output. Improper positioning of the RESET edges
can lead to interference with the read-out.
The falling edge of the RESET should follow the last pixel of the previous line’s read-out. Thus, one cycle of RESET pulses cannot
be set shorter than the time equal to (17 + 4 × N) clock cycles, where N is the number of pixels.
EOS of each detector chip appears during the output of the last pixel.
xvi
RESET must stay Low [tplw(RESET)] for at least twelve clock cycles.
xvii
The falling edge of RESET pulse determines the end of the integration time and the start of signal read-out, while the rising edge ofthe RESET pulse determines the start of the integration time. As a result, the signal-charge integration time can be controlled
externally with the width of the RESET pulse [tphw(RESET)]. However, the charge integration does not start at the rise of a RESET
pulse but starts at the 8th falling edge of clock after the rise of the RESET pulse and ends at the 7th falling edge of clock after the fall ofthe RESET pulse.
xviii
The rising and falling edges of RESET must observe the setup and hold time requirements around the falling edges of CLK.

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3KRWRGLRGH'HWHFWRUZLWK6LJQDO$PSOLILFDWLRQ;%56HULHVŶ Mechanical drawingsxix

xix

Part: 2-inch detector (XB8801R-2.0)
Units: Dimensions are in millimeters (mm).
Board: FR4 epoxy resin bonded glass fabric.
Connector: BISON Advanced Technology Corp., Ltd. (www.bison-protech.com), P101-RGP-060/030-12 or similar.

Ŷ Pin connections

PinNo.
12345Symbol

Name

Description

RESET
CLKTRIG
EXTSP
VMSReset Pulse
Clock Pulse
Trigger Pulse
External Start Pulse
Master/Slave
Selection Voltage

67891011

VDD
GND
EOS
VIDEO
VREF
SNSSupply Voltage
GroundEnd of Scan
Video Output
Reference Voltage
Sensitivity Selection

12RS

Resolution Selection

Negative-going pulse input
Pulse input
Positive-going pulse output
Pulse/voltage input
Voltage input:
See Master/slave selection voltage VMS and external start pulse EXTSP
settings note
5-V supply voltage
Common ground voltage
Negative-going pulse output
Negative-going output with respect to VREF
Voltage input
Voltage input:
High (VDD) for high sensitivity (Cfhs)
Low (GND) for low sensitivity (Cfls)
Voltage input:
High (VDD) for 0.1-mm pitch
Low (GND) for 0.2-mm pitch 

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3KRWRGLRGH'HWHFWRUZLWK6LJQDO$PSOLILFDWLRQ;%56HULHVŶ Master/slave selection voltage VMS and external start pulse EXTSP settings
For most applications, multiple detectors are read out in parallel. To ensure parallel read out, set the VMS
input of all detectors to VDD (A in the table below).
In applications where two or more linearly connected detectors are read out sequentially (in series), set theVMS input of the first detector to VDD and the VMS input of each subsequent (second and later) detector toGND while connecting the EXTSP input of each subsequent detector to the EOS output of each respective
preceding detector (B in the table below). The CLK and RESET pulses should be shared among all detectors
and the Video output terminals of all detectors are connected together. The maximum number of detectorsthat can be daisy-chained together is limited by the maximum Video output capacitance requirement.

AB

Operation Mode
Master configuration:
Parallel readout: all detectors
Serial readout: 1st detector only
Slave configuration:
Serial readout: 2nd and later detectors

VMS

EXTSP

VDD

Don’t care

GND

Preceding detector’s EOS should be input

Ŷ Readout circuit
In order to minimize noise and to maximize performance, an operational amplifier should be placed as close
to the detector to amplify the Video signal.

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