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Instruction fetch eciency on ALUS architecture
Kenji Kise,y Tomohiro Nakamura,y Hidenori Tsuji,yYuichiro Ajimay and Hidehiko Tanakay

We discuss the ratio of ALU usage on the ALUS architecture which integrates many arithmetic logic units in one chip. The ALUS architecture speculatively fetches instructions fromboth paths of a branch before the condition of the branch has been evaluated (eager execution).
In order to avoid the explosion of utilized resources, we adopt pruning eager execution(PEE).
Our evaluations showed that 1%-PEE bypassing about 30 branches reaches 7.2 speedup overthe scalar machine.

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v|ZÑ _fy] Eager Execution(PruningEager Execution) ½ hp[Ð{p{C
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