600 V, 15 A
High Voltage 3-phase Motor Driver

SCM1242MA

Data Sheet

Description

Package

The SCM1242MA is a high voltage 3-phase motor
driver in which transistors, pre-drive circuits, andbootstrap diodes with current-limiting resistors are highly
integrated. The product can run on a 3-shunt current
detection system and optimally control the inverter
systems of medium-capacity motors that require universal
input standards.

DIP33
Pin Pitch: 1.27 mm
Mold Dimensions: 47 mm × 19 mm × 4.4 mm

Features● Pb-free (RoHS Compliant)● Isolation Voltage: 2000 V (for 1 min)
UL-recognized Component (File No.: E118037)● In Case of Abnormal Operaion, All Outputs Shut
Down
● Built-in Bootstrap Diodes with Current Limiting
Resistors (22 Ω)● CMOS-compatible Input (3.3 V or 5 V)
● Fault Signal Output at Protection Activation● Protections Include:
Undervoltage Lockout for Power Supply
High-side (UVLO_VB): Auto-restartLow-side (UVLO_VCC): Auto-restart
Overcurrent Protection (OCP): Auto-restart
Simultaneous On-state Prevention: Auto-restart
Thermal Shutdown (TSD): Auto-restart

Typical Application
VCC

VFO

U1

1

LIN1

HIN1

● Breakdown Voltage: 600 V● Output Current: 15 A

Applications
For motor drives such as:● Refrigerator Compressor Motor● Air Conditioner Compressor Motor● Washing Machine Main Motor● Fan Motor● Pump Motor

LS1 33FO1

2 OCP1
3 LIN1
4 COM1
5 HIN1

CFO

Specifications

SCM1242MA

RFO
INT

Not to scale

MIC1

U 32

6 VCC1

31
7

CBOOT1

VB1

8 HS1

LS2
9

FO2

30

10 OCP2
11 LIN2LIN212 COM2

V

MIC2

29

M

13 HIN2

HIN2

Controller

14 VCC2

28
15

CBOOT2VB2

16 HS2
17

LS3

FO3

27

18 OCP3
19 LIN3LIN320 COM3

MIC3

W

26

21 HIN3HIN3

22 VCC3

VDC

VBB
25

CBOOT3VB3
23
24 HS3

A/D3

RO3
RO3
RO1

A/D2
A/D1

COM

CO1 CO2

CO3
RS3 RS2 RS1

SCM1242MA -DSE Rev.1.0
SANKEN ELECTRIC CO., LTD.
Mar. 09, 2021
https://www.sanken-ele.co.jp/en© SANKEN ELECTRIC CO., LTD. 2021

1

SCM1242MA
Contents
Description ------------------------------------------------------------------------------------------------------ 1
Contents --------------------------------------------------------------------------------------------------------- 2
1. Absolute Maximum Ratings----------------------------------------------------------------------------- 4
2. Recommended Operating Conditions ----------------------------------------------------------------- 5
3. Electrical Characteristics -------------------------------------------------------------------------------- 6
3.1. Characteristics of Control Parts------------------------------------------------------------------ 6
3.2. Bootstrap Diode Characteristics ----------------------------------------------------------------- 7
3.3. Thermal Resistance Characteristics ------------------------------------------------------------- 7
3.4. Transistor Characteristics ------------------------------------------------------------------------- 8
4. Mechanical Characteristics ----------------------------------------------------------------------------- 9
5. Insulation Distance ---------------------------------------------------------------------------------------- 9
6. Truth Table ----------------------------------------------------------------------------------------------- 10
7. Block Diagram ------------------------------------------------------------------------------------------- 11
8. Pin Configuration Definitions ------------------------------------------------------------------------- 12
9. Typical Applications ------------------------------------------------------------------------------------ 13
10. Physical Dimensions ------------------------------------------------------------------------------------ 15
11. Marking Diagram --------------------------------------------------------------------------------------- 16
12. Functional Descriptions -------------------------------------------------------------------------------- 17
12.1. Turning On and Off the IC ---------------------------------------------------------------------- 17
12.2. Pin Descriptions ----------------------------------------------------------------------------------- 17
12.2.1. U, V, and W----------------------------------------------------------------------------------- 17
12.2.2. VB1, VB2, and VB3 ------------------------------------------------------------------------- 17
12.2.3. HS1, HS2, and HS3 ------------------------------------------------------------------------- 18
12.2.4. VCC1, VCC2, and VCC3 ------------------------------------------------------------------ 18
12.2.5. COM1, COM2, and COM3---------------------------------------------------------------- 18
12.2.6. HIN1, HIN2, and HIN3; LIN1, LIN2, and LIN3 -------------------------------------- 18
12.2.7. VBB -------------------------------------------------------------------------------------------- 19
12.2.8. LS1, LS2, and LS3 -------------------------------------------------------------------------- 19
12.2.9. OCP1, OCP2, and OCP3------------------------------------------------------------------- 20
12.2.10. FO1, FO2, and FO3 ------------------------------------------------------------------------- 20
12.3. Protection Functions ------------------------------------------------------------------------------ 21
12.3.1. Fault Signal Output ------------------------------------------------------------------------- 21
12.3.2. Shutdown Signal Input --------------------------------------------------------------------- 21
12.3.3. Undervoltage Lockout for Power Supply (UVLO) ----------------------------------- 21
12.3.4. Overcurrent Protection (OCP) ----------------------------------------------------------- 22
12.3.5. Simultaneous On-state Prevention ------------------------------------------------------- 23
12.3.6. Thermal Shutdown (TSD) ----------------------------------------------------------------- 24
13. Design Notes ---------------------------------------------------------------------------------------------- 24
13.1. PCB Pattern Layout ------------------------------------------------------------------------------ 24
13.2. Considerations in Heatsink Mounting -------------------------------------------------------- 24
13.3. Considerations in IC Characteristics Measurement --------------------------------------- 25
14. Calculating Power Losses and Estimating Junction Temperature ---------------------------- 26
14.1. IGBT Steady-state Loss, PON -------------------------------------------------------------------- 26
14.2. IGBT Switching Loss, PSW ----------------------------------------------------------------------- 26
14.3. Estimating Junction Temperature of IGBT -------------------------------------------------- 26
15. Performance Curves ------------------------------------------------------------------------------------ 27
15.1. Performance Curves of Control Parts--------------------------------------------------------- 27

SCM1242MA -DSE Rev.1.0
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Mar. 09, 2021
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SCM1242MA
15.2. Performance Curves of Output Parts --------------------------------------------------------- 32
15.2.1. Output Transistor Performance Curves ------------------------------------------------ 32
15.2.2. Switching Loss Curves --------------------------------------------------------------------- 32
15.3. Allowable Effective Current Curves ----------------------------------------------------------- 33
15.4. Transient Thermal Resistance Curves -------------------------------------------------------- 34
15.5. Short Circuit SOA (Safe Operating Area) --------------------------------------------------- 34
Important Notes ---------------------------------------------------------------------------------------------- 35

SCM1242MA -DSE Rev.1.0
SANKEN ELECTRIC CO., LTD.
Mar. 09, 2021
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SCM1242MA
1.

Absolute Maximum Ratings

Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming outof the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C.
Parameter
SymbolConditions
Rating
Unit
Main Supply Voltage (DC)VDC
VBB–LSx
450
V
Main Supply Voltage (Surge)
VDC(SURGE)VBB–LSx
500
V
VCC = 15 V, IC = 1 mA,
IGBT Breakdown Voltage
VCES
600
V
VIN = 0 V
VCC
VCCx–COMx
20
Logic Supply Voltage
V
VBS
VBx–HSx20
Output Current(1)IO
TC = 25 °C, TJ < 150 °C
15A
TC = 25 °C,
Output Current (Pulse)
IOP
pulse width ≤ 1 ms,
30
Asingle pulse
HINx–COMx,
Input Voltage
VIN−0.5 to 7
V
LINx–COMx
FO1–COM1,
FOx Pin Voltage
VFO
FO2–COM2,−0.5 to 7
V
FO3–COM3
OCP1–COM1,
OCPx Pin Voltage
VOCP
OCP2–COM2,−10 to 5V
OCP3–COM3
TC(OP)
Operating Case Temperature(2)−30 to 100
°C
(3)
TJ
Junction Temperature
150
°C
TSTG
Storage Temperature−40 to 150°C
Between surface of heatsink
Isolation Voltage(4)VISO(RMS)
side and each pin; AC,
2000
V
60 Hz, 1 min(1)Should be derated depending on an actual case temperature. See Section 15.3.
Refers to a case temperature measured during IC operation.
(3)
Refers to the junction temperature of each chip built in the IC, including the control MICs, transistors, andfreewheeling diodes.
(4)
Refers to voltage conditions to be applied between all of the pins and the case. All the pins have to be shorted.
(2)

SCM1242MA -DSE Rev.1.0
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SCM1242MA
2.

Recommended Operating Conditions
Parameter

Min.

Typ.

Max.

Unit

—

300

400

V

13.5

—

16.5

V

13.5

—

16.5

V

VIN

0

—

5.5

V

tIN(MIN)ON

0.5

—

—

μs

tIN(MIN)OFF

0.5

—

—

μs

Dead Time of Input Signal

tDEAD

1.5

—

—

μs

FOx Pin Pull-up Resistor

RFO

3.3

—

22

kΩ

FOx Pin Pull-up Voltage

VFO

3.0

—

5.5

V

FOx Pin Noise Filter Capacitor

CFO

0.001

—

0.01

μF

Bootstrap Capacitor

CBOOT

10

—

220

μF

18

—

—

mΩ

Main Supply Voltage
Logic Supply Voltage
Input Voltage(HINx, LINx, and FOx)
Minimum Input Pulse Width

Shunt Resistor(1)

SymbolVCC

Conditions
COM1 = COM2 = COM3,VBB–COM
VCCx–COMx

VBS

VBx–HSx

VDC

RS

IOP ≤ 30 A

(2)

RO

—

—

100

Ω

RC Filter Capacitor

CO

—

—

8200

pF

PWM Carrier Frequency

fC

—

—

20

kHz

RC Filter Resistor

(1)
(2)

Should be a low-inductance resistor.
Requires the time constants that satisfy the following equation (see also Section 12.3.4): R O × CO < 0.82 μs .

SCM1242MA -DSE Rev.1.0
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SCM1242MA
3.

Electrical Characteristics

Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming outof the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C, VCC = 15 V.

3.1.

Characteristics of Control Parts
Parameter

SymbolConditions

Min.

Typ.

Max.

Unit

Power Supply Operation
Logic Operation Start Voltage
Logic Operation Stop Voltage

VCC(ON)

VCCx–COMx

10.5

11.5

12.5

V

VBS(ON)VBx–HSx

10.5

11.5

12.5

V

VCC(OFF)

VCCx–COMx

10.0

11.0

12.0

V

VBS(OFF)VBx–HSxVCC1 = VCC2 = VCC3,
COM1 = COM2 = COM3;
VCC pin current in 3-phase
operation
VBx–HSx = 15 V,
HINx = 5 V; VBx pin
current in 1-phase
operation

10.0

11.0

12.0

V

—

3

—

mA

—

110

—

μA

VIH

—

2.0

2.5

V

VIL

1.0

1.5

—

V

ICC
Logic Supply Current
IBS
Input Signal
High Level Input Threshold Voltage(HINx, LINx, and FOx)
Low Level Input Threshold Voltage(HINx, LINx , and FOx)
High Level Input Current(HINx, LINx)
Low Level Input Current(HINx, LINx)
Fault Signal Output
FOx Pin Voltage at Fault Signal
OutputFOx Pin Voltage in Normal
Operation
Protection

IIH

VIN = 5 V

—

230

500

μA

IIL

VIN = 0 V

—

—

2

μA

VFOL

VFO = 5 V, RFO = 10 kΩ

—

—

0.5

V

VFOH

VFO = 5 V, RFO = 10 kΩ

4.8

—

—

V

OCP Threshold Voltage

VTRIP

OCPx–COMx

0.46

0.50

0.54

V

OCP Blanking TimetBK(OCP)

VOCP = 1.0 V

—

370

—

ns

OCP Hold Time

tP

5

10

—

ms

TSD Operating Temperature*

TDH

135

150

165

°C

TSD Releasing Temperature*

TDL

105

120

135

°C

* Guaranteed by design.

SCM1242MA -DSE Rev.1.0
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SCM1242MA
3.2.

Bootstrap Diode Characteristics
Parameter

SymbolConditions

Min.

Typ.

Max.

Unit

Bootstrap Diode Leakage Current

ILBD

VR = 600 V

—

—

10

μA

Bootstrap Diode Forward Voltage

VFB

IFB = 0.15 A

—

1.1

1.3

V

Bootstrap Diode Series Resistor

RBOOT

17.6

22.0

26.4

Ω

Min.

Typ.

Max.

Unit

—

—

3.8

°C/W

—

—

5.0

°C/W

3.3.

Thermal Resistance Characteristics
Parameter

SymbolR(J-C)Q(2)Junction-to-Case Thermal
Resistance(1)R(J-C)F(3)Conditions
1 element operating(IGBT)
1 element operating(freewheeling diode)

24

1

25

33
Measurement point

Figure 3-1.

Case Temperature Measurement Point(1)

Refers to a case temperature at the measurement point described in Figure 3-1, below.
Refers to steady-state thermal resistance between the junction of the built-in transistors and the case. For transient
thermal characteristics, see Section 15.4.
(3)
Refers to steady-state thermal resistance between the junction of the built-in freewheeling diodes and the case.
(2)

SCM1242MA -DSE Rev.1.0
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SCM1242MA
3.4.

Transistor Characteristics
HINx/
LINx
0

trr
ton
td(on) tr

ID/
IC

toff
td(off) tf
90%

10%

0

VDS/
VCE

0

Figure 3-2.
Parameter
Collector-to-Emitter Leakage
Current
Collector-to-Emitter Saturation
Voltage
Diode Forward Voltage

Switching Characteristics Definitions

SymbolConditions

Min.

Typ.

Max.

Unit

ICES

VCE = 600 V, VIN = 0 V

—

—

1

mA

VCE(SAT)IC = 15 A, VIN = 5 V

—

1.7

2.2

V

VF

IF = 15 A, VIN = 0 V

—

1.7

2.2

V

—

100

—

ns

—

570

—

ns

—

110

—

ns

—

1100

—

ns

—

100

—

ns

—

100

—

ns

—

630

—

ns

—

120

—

ns

—

1100

—

ns

—

100

—

ns

High-side Switching
Diode Reverse Recovery Timetrr

Turn-on Delay Timetd(on)

Rise Timetr

Turn-off Delay Timetd(off)Fall Timetf

VDC = 300 V,
IC = 15 A,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C,
inductive load

Low-side Switching
Diode Reverse Recovery Timetrr

Turn-on Delay Timetd(on)

Rise Timetr

Turn-off Delay Timetd(off)Fall Timetf

VDC = 300 V,
IC = 15 A,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C,
inductive load

SCM1242MA -DSE Rev.1.0
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Mar. 09, 2021
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SCM1242MA
4.

Mechanical Characteristics
Parameter

Conditions

Min.

Typ.

Max.

Unit

Heatsink Mounting Screw Torque
*
0.588
—
0.784
N∙m
Flatness of Heatsink Attachment
See Figure 4-1.
0
—
200
μm
Area
Package Weight
—
10.8
—
g
* Requires using a metric screw of M3 and a plain washer of 7 mm (φ). For more on screw tightening, see Section 13.2.

Heatsink

Measurement position

-+

-

+

Heatsink

Figure 4-1.

5.

Flatness Measurement Position

Insulation DistanceParameter

Clearance

Conditions

Min.

Typ.

Max.

Unit

Between heatsink* and leads.
See Figure 5-1.

2.0

—

2.5

mm

Creepage
3.86
—
4.26
mm
* Refers to when a heatsink to be mounted is flat. If your application requires a clearance exceeding the maximum distancegiven above, use an alternative (e.g., a convex heatsink) that will meet the target requirement.

Creepage
Clearance

Heatsink

Figure 5-1.

Insulation Distance Definitions

SCM1242MA -DSE Rev.1.0
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SCM1242MA
6.

Truth Table

Table 6-1 is a truth table that provides the logic level definitions of operation modes.
In the case where HINx and LINx pin signals in each phase are high at the same time, the simultaneous on-stateprevention sets both the high- and low-side transistors off.
After the IC recovers from a UVLO_VCC condition, the high- and low-side transistors resume switching, according to
the input logic levels of the HINx and LINx signals (level-triggered).
After the IC recovers from a UVLO_VB condition, the high-side transistors resume switching at the next rising edgeof an HINx signal (edge-triggered).
Table 6-1.
Mode

Normal Operation

Shutdown Signal Input
FO1/FO2/FO3 = L

Undervoltage Lockout for High-side
Power Supply (UVLO_VB)

Undervoltage Lockout for Low-side
Power Supply (UVLO_VCC)

Overcurrent Protection (OCP)

Thermal Shutdown (TSD)

HINx
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

Truth Table for Operation Modes
LINx
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

High-side Transistor
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF

SCM1242MA -DSE Rev.1.0
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Low-side Transistor
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF

10

SCM1242MA
7.

Block Diagram

MIC1
1

FO1

UVLO_VCC

Filter
3 µs

2 OCP1

3 LIN1
4 COM1
5 HIN1

6 VCC1LS1 33

UVLO_VB

Level shift

Drive
circuit

HO1

Input logic

OCP

U 32

TSD

Simultaneous
on-stateprevention

Drivecircuit

Filter
370 ns

LO1

31

VB1
8 HS1
7

MIC2
9 FO2

UVLO_VCC

Filter
3 µs

10 OCP2

Level shift

11 LIN2

Input logic

12 COM2
13 HIN2
14 VCC2

Simultaneous
on-stateprevention

OCP

LS2

30

UVLO_VB
Drive
circuit

HO2

V
29
TSD
Drive
circuit

Filter
370 ns

LO2

28

VB2
15
16 HS2

MIC3
17

FO3

UVLO_VCC

Filter
3 µs

18 OCP3

19 LIN3
20 COM3
21 HIN3

22 VCC3LS3UVLO_VB

Level shift

Drive
circuit

HO3

Input logic

W
TSD

Simultaneous
on-stateprevention

OCP

Filter
370 nsDrive
circuit

27

26

LO3

VBB
25

VB3
23
24 HS3

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SCM1242MA
8.

Pin Configuration Definitions
Top View

1

24

1

25

33

33
24
25
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

Pin Name
FO1
OCP1
LIN1
COM1
HIN1
VCC1
VB1
HS1
FO2
OCP2
LIN2
COM2
HIN2
VCC2
VB2
HS2
FO3
OCP3
LIN3
COM3
HIN3
VCC3
VB3
HS3
VBB
W
LS3
VBB
V
LS2
VBB
U
LS1

Description
U-phase fault signal output and shutdown signal input
Input for U-phase overcurrent protection
Logic input for U-phase low-side gate driver
U-phase logic ground
Logic input for U-phase high-side gate driver
U-phase logic supply voltage input
U-phase high-side floating supply voltage input
U-phase high-side floating supply groundV-phase fault signal output and shutdown signal input
Input for V-phase overcurrent protection
Logic input for V-phase low-side gate driver
V-phase logic ground
Logic input for V-phase high-side gate driver
V-phase logic supply voltage input
V-phase high-side floating supply voltage input
V-phase high-side floating supply groundW-phase fault signal output and shutdown signal input
Input for W-phase overcurrent protection
Logic input for W-phase low-side gate driver
W-phase logic ground
Logic input for W-phase high-side gate driver
W-phase logic supply voltage input
W-phase high-side floating supply voltage input
W-phase high-side floating supply ground
Positive DC bus supply voltage
W-phase output
W-phase IGBT emitter(Pin trimmed) positive DC bus supply voltage
V-phase output
V-phase IGBT emitter(Pin trimmed) positive DC bus supply voltage
U-phase output
U-phase IGBT emitter

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SCM1242MA
9.

Typical Applications

CR filters and Zener diodes should be added to your application as needed. This is to protect each pin against surge
voltages causing malfunctions, and to avoid the IC being used under the conditions exceeding the absolute maximum
ratings where critical damage is inevitable. Then, check all the pins thoroughly under actual operating conditions to ensurethat your application works flawlessly.
VCC

VFO

SCM1242MA

U1

RFO
INT

LS1
1

CFO

33

FO1

2 OCP1
3 LIN1LIN14 COM1

CLIN1

MIC1

U 32

5 HIN1HIN1

6 VCC1

CHIN1

DZ
CVCC1

VB1
8 HS1
7

CBOOT131

DBOOT1 RBOOT1

CP1

LS2
9

30

FO2

10 OCP2
11 LIN2LIN212 COM2

CLIN2

V

MIC2

29

M

13 HIN2

HIN2

Controller

14 VCC2

CHIN2
CVCC2

VB2
16 HS2
15

CBOOT2

LS3

CP2
17

28

DBOOT2 RBOOT2

27

FO3

18 OCP3
19 LIN3LIN320 COM3

CLIN3

MIC3

W

26

21 HIN3HIN3

22 VCC3

CHIN3
CVCC3

25

VB3
24 HS323

CBOOT3VDC

VBB
DBOOT3 RBOOT3

CP3
CS

RO

A/D

CDC

CO
COM

DRS

Figure 9-1.

RS

Typical Application Using a Single Shunt Resistor

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SCM1242MA
VCC

VFO

SCM1242MA

U1

RFO
INT

LS1
1

CFO

33

FO1

2 OCP1
3 LIN1LIN14 COM1

CLIN1

MIC1

U 32

5 HIN1HIN1

6 VCC1

CHIN1

DZ
CVCC1

VB1
8 HS1
7

CBOOT131

DBOOT1 RBOOT1

CP1

LS2
9

30

FO2

10 OCP2
11 LIN2LIN212 COM2

CLIN2

V

MIC2

29

M

13 HIN2

HIN2

Controller

14 VCC2

CHIN2
CVCC2

VB2
16 HS2
15

CBOOT228

DBOOT2 RBOOT2

LS3

CP2
17

27

FO3

18 OCP3
19 LIN3LIN320 COM3

CLIN3

MIC3

W

26

21 HIN3HIN3

22 VCC3

CHIN3
CVCC3

25

VB3
24 HS323

CBOOT3VDC

VBB
DBOOT3 RBOOT3

CP3
RO3

A/D3

A/D2
A/D1

CS

RO2

CDC

RO1
CO1

CO2

CO3

COM

DRS3 DRS2

Figure 9-2.

DRS1

RS3 RS2 RS1

Typical Application Using Three Shunt Resistors

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SCM1242MA
10. Physical Dimensions● DIP33 (LF2551)
0.5

C

0.5

C

(2.6)

8xP5.1=40.8

4.4±0.3
1.2±0.2+0.5

47±0.3

2 0（Root of pin）

MAX1.2A(5ﾟ)

φ 3.2± 0.15

15.95± 0.5

11.45± 0.5

19± 0.3

12.25± 0.5

17.25± 0.5

A

(5ﾟ)

B
43.3 ±0.3

B

2.08±0.2

11.2±0.5
5xP1.27=6.35

3.7

1.27
3.7
+0.2

+0.2

3.7

3.24

0.5 -0.1

(2.6)

1.27

1.27

D
D

+0.2

2.57

5xP1.27=6.35

0.5 -0.1

5xP1.27=6.35

2

+0.2
-0.1

0.6 -0.1

B-B

+0.2

0.5 -0.1+0.2

0.5 -0.1

C-C

+0.2

0.7 -0.1

A-A

1.2

+0.2
-0.1

D-D

NOTES:● Dimensions in millimeters● Maximum gate burr height is 0.3 mm.
● Pb-free (RoHS compliant)● Ejector pin marks left on the branding side include “○” and “◎”.

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SCM1242MA● Reference PCB Hole Sizes

φ1.1

φ1.4

Pins 1 to 24

Pins 25 to 33

11. Marking Diagram25

33

Branding Side
24
1

25

33

JAPAN

SCM1242MA

Control Symbol

YMDD

Lot Number:
Y is the last digit of the year of manufacture (0 to 9)
24

1

M is the month of the year (1 to 9, O, N, or D)
DD is the day of the month (01 to 31)
Part Number

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SCM1242MA
12. Functional Descriptions
All the characteristic values given in this section are
typical values, unless they are specified as minimum or
maximum.
For pin descriptions, this section employs a notation
system that denotes a pin name with the arbitrary letter“x”, depending on context. The U-, V-, and W-phases are
represented as the pin numbers 1, 2, and 3, respectively.
Thus, “the VBx pin” is used when referring to any or allof the VB1, VB2, and VB3 pins. Also, when different pin
names are mentioned as a pair (e.g., “the VBx and HSxpins”), they are meant to be the pins in the same phase.

12.1. Turning On and Off the IC
The procedures listed below provide recommended
startup and shutdown sequences. To turn on the IC
properly, do not apply any voltage on the VBB, HINx,
and LINx pins until the VCCx pin voltage has reached astable state (VCC(ON) ≥ 12.5 V). It is required to fully
charge bootstrap capacitors, CBOOTx, at startup (seeSection 12.2.2).
To turn off the IC, set the HINx and LINx pins to logic
low (or “L”), and then decrease the VCCx pin voltage.

12.2. Pin Descriptions

CBOOT (μF) > 800 × t L(OFF) (s)(1)

10 μF ≤ CBOOTx ≤ 220 μF(2)

In Equation (1), let tL(OFF) be the maximum off-time of
the low-side transistor (i.e., the non-charging time of
CBOOTx), measured in seconds.
Even while the high-side transistor is off, voltage
across the bootstrap capacitor keeps decreasing due topower dissipation in the IC. When the VBx pin voltage
decreases to VBS(OFF) or less, the high-side undervoltage
lockout (UVLO_VB) starts operating (see Section
12.3.3.1). Therefore, actual board checking should bedone thoroughly to validate that voltage across the VBx
pin maintains over 12.0 V (VBS > VBS(OFF)) during a lowfrequency operation such as a startup period.
As Figure 12-1 shows, a bootstrap diode, DBOOTx, anda current-limiting resistor, RBOOTx, are internally placed inseries between the VCCx and VBx pins. Time constantfor the charging time of CBOOTx, τ, can be computed by
Equation (3):τ = CBOOTx × R BOOTx ,where CBOOTx is the optimized capacitance of thebootstrap capacitor, and RBOOTx is the resistance of thecurrent-limiting resistor (22 Ω ± 20%).

12.2.1. U, V, and W
These pins are the outputs of the three phases, and serveas the connection terminals to the 3-phase motor. The U,
V, and W pins are internally connected to the HS1, HS2,and HS3 pins, respectively.

U1

VB1

7

CP1

These are the inputs of the high-side floating power
supplies for the individual phases.
Voltages across the VBx and HSx pins should bemaintained within the recommended range (i.e., the Logic
Supply Voltage, VBS) given in Section 2.
In each phase, a bootstrap capacitor, CBOOTx, should beconnected between the VBx and HSx pins. For proper
startup, turn on the low-side transistor first, then fully
charge the bootstrap capacitor, CBOOTx. For thecapacitance of the bootstrap capacitors, CBOOTx, choose
the values that satisfy Equations (1) and (2). Note thatcapacitance tolerance and DC bias characteristics must be
taken into account when you choose appropriate values
for CBOOTx.

HS1

DBOOT1 RBOOT1

CBOOT1

8

31

VCC

VBB
HO

6

VCC1

12.2.2. VB1, VB2, and VB3

(3)

4

MIC1

U
COM1

32

Motor

LO

CDC VDC
LS1

Figure 12-1.

33

RS1

Bootstrap Circuit

Figure 12-2 shows an internal level-shifting circuit. A
high-side output signal, HOx, is generated according toan input signal on the HINx pin. When an input signal on
the HINx pin transits from low to high (rising edge), a“Set” signal is generated. When the HINx input signaltransits from high to low (falling edge), a “Reset” signal
is generated. These two signals are then transmitted to thehigh-side by the level-shifting circuit and are input to theSR flip-flop circuit. Finally, the SR flip-flop circuit feeds
an output signal, Q (i.e., HOx).
Figure 12-3 is a timing diagram describing how noiseor other detrimental effects will improperly influence theSCM1242MA -DSE Rev.1.0
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SCM1242MA
level-shifting process. When a noise-induced rapid
voltage drop between the VBx and HSx pins (“VBx–HSx”) occurs after the Set signal generation, the next
Reset signal cannot be sent to the SR flip-flop circuit. And
the state of an HOx signal stays logic high (or “H”)
because the SR flip-flop does not respond. With the HOx
state being held high (i.e., the high-side transistor is in an
on-state), the next LINx signal turns on the low-side
transistor and causes a simultaneously-on condition,
which may result in critical damage to the IC.
To protect the VBx pin against such a noise effect, add
a bootstrap capacitor, CBOOTx, in each phase. CBOOTx must
be placed near the IC and be connected between the VBx
and HSx pins with a minimal length of traces.
To use an electrolytic capacitor, add a 0.01 μF to 0.1
μF bypass capacitor, CPx, in parallel near these pins used
for the same phase.
U1

VBx

S
Set
Input
logic

HINx

Q

HOx

R

Pulse
generator Reset

HSx

COMx

Figure 12-2.

Internal Level-shifting Circuit

12.2.4. VCC1, VCC2, and VCC3
These are the logic supply pins for the built-in control
MICs. The VCC1, VCC2, and VCC3 pins must be
externally connected on a PCB because they are notinternally connected. To prevent malfunction induced bysupply ripples or other factors, put a 0.01 μF to 0.1 μF
ceramic capacitor, CVCCx, near these pins. To prevent
damage caused by surge voltages, put an 18 V to 20 V
Zener diode, DZ, between the VCCx and COMx pins.
Voltages to be applied between the VCCx and COMx
pins should be regulated within the recommended
operational range of VCC, given in Section 2.

12.2.5. COM1, COM2, and COM3
These are the logic ground pins for the built-in control
MICs. For proper control, the control parts in each phasemust be connected to the corresponding ground pin. The
COM1, COM2, and COM3 pins should be connected
externally on a PCB because they are not internallyconnected. Varying electric potential of the logic groundcan be a cause of improper operations. Therefore, connect
the logic ground as close and short as possible to a shunt
resistor, RS, at a single-point ground (or star ground)which is separated from the power ground (see Figure12-4). Moreover, extreme care should be taken indesigning a PCB so that currents from the power ground
do not affect the COMx pin.
U1

VDC

VBB 25HINx

CS
4 COM10

Set

12 COM2

0
20 COM3Reset

CDC
LS1 33LS2 30RSLS3 270

VBx-HSx

VBS(ON)VBS(OFF)
OCP1, OCP30

Stays logic highQ

Connect the COM1, COM2, andCOM3 pins on a PCB.

Create a single-point
ground (a star ground)near R S, but keep it
separated from thepower ground.

0

Figure 12-3.

Waveforms at VBx–HSx Voltage Drop

12.2.3. HS1, HS2, and HS3
These pins are the grounds of the high-side floating
power supplies for each phase, and are connected to thenegative nodes of bootstrap capacitors, CBOOTx. The HS1,
HS2, and HS3 pins are internally connected to the U, V,
and W pins, respectively.

Figure 12-4.

Connections to Logic Ground12.2.6. HIN1, HIN2, and HIN3;
LIN1, LIN2, and LIN3
These are the logic supply pins for the built-in control
MICs. The HINx pin acts as a high-side controller; theLINx pin acts as a low-side controller. Figure 12-5 shows
an internal circuit diagram of the HINx or LINx pin. Thisis a CMOS Schmitt trigger circuit with a built-in 22 kΩ

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SCM1242MA
pull-down resistor, and its input logic is active high.
Input signals across the HINx-COMx and the LINxCOMx pins in each phase should be set within the ranges
provided in Table 12-1, below. Note that dead time
setting must be done for HINx and LINx signals because
the IC does not have a dead time generator.
The higher PWM carrier frequency rises, the more
switching loss increases. Hence, the PWM carrier
frequency must be set so that operational casetemperatures and junction temperatures have sufficientmargins against the absolute maximum ranges, specified
in Section 1.
If the signals from the microcontroller become unstable,
the IC may result in malfunctions. To avoid this event, theoutputs from the microcontroller output line should not behigh impedance. Also, if the traces from themicrocontroller to the HINx or LINx pin (or both) are too
long, the traces may be interfered by noise. Therefore, it
is recommended to add an additional filter or a pull-downresistor near the HINx or LINx pin as needed (see Figure12-6).
Here are filter circuit constants for reference:
RIN1x: 33 Ω to 100 Ω
RIN2x 1 kΩ to 10 kΩ
CINx: 100 pF to 1000 pF
Care should be taken in adding RIN1x and RIN2x to thetraces. When they are connected to each other, the input
voltage of the HINx and LINx pins becomes slightly
lower than the output voltage of the microcontroller.
Table 12-1. Input Signals for HINx and LINx Pins
Parameter
Input
Voltage
Input Pulse
Width
PWM Carrier
Frequency
Dead TimeHigh Level
Signal3 V < VIN < 5.5
V

Low LevelSignal0 V < VIN < 0.5
V≥0.5 μs≥0.5 μs

U1

RIN1

Input
signal

HINx(LINx)

RIN2

SCM1272MA

Controller

Figure 12-6.

Filter Circuit for HINx or LINx Pin

12.2.7. VBB
This is the input pin for the main supply voltage, i.e.,
the positive DC bus. All of the IGBT collectors of thehigh-side are connected to this pin. Voltages between the
VBB and COMx pins should be set within therecommended range of the main supply voltage, V DC,
given in Section 2.
To suppress surge voltages, put a 0.01 μF to 0.1 μF
bypass capacitor, CS, near the VBB pin and an electrolytic
capacitor, CDC, with a minimal length of PCB traces to the
VBB pin.

12.2.8. LS1, LS2, and LS3
These are the emitter pins of the low-side IGBTs andare externally connected to a shunt resistor, RS. Whenconnecting a shunt resistor, use a resistor with low
inductance, and place it as near as possible to the IC witha minimum length of traces to the LSx and COMx pins.
Otherwise, malfunction may occur because a longer
circuit trace increases its inductance and thus increases its
susceptibility to improper operations. In applications
where long PCB traces are required, add a fast recovery
diode, DRS, between the LSx and COMx pins in order toprevent the IC from malfunctioning.
U1≤20 kHzCIN

VBB 25VDC
CS

4 COM1CDC

LS1 33≥1.5 μs

12 COM2RS

LS2 30U1

HINx(LINx)

5V

2 kΩ

20 COM3

OCP1,
OCP3
Add a fast recovery
diode to a long trace.

22 kΩ

COMx

Figure 12-5.

DRS

LS3 27

Figure 12-7.

Put a shunt resistor near
the IC with a minimum
length to the LSx pin.

Connections to LSx Pin

Internal Circuit Diagram of HINx or
LINx Pin

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SCM1242MA
VFO

12.2.9. OCP1, OCP2, and OCP3This pin serves as the input of the overcurrent
protection (OCP) which monitors the currents flowing
through the output transistors. Section 12.3.4 provides
further information about the OCP circuit configurationand its mechanism.

U1

5V

RFO

1 MΩ

2 kΩ

FOx

3.0 µs (typ.)Blanking
filterINT
50 Ω

Output transistors
turn-off

CFO
QFOx

COMx

12.2.10. FO1, FO2, and FO3
Figure 12-8.

Internal Circuit Diagram of FOx Pin and
Its Peripheral Circuit
QFOx

ON

FOx Pin
VoltagetD(FO)

VIL

0

Fault Signal Voltage (V)Figure 12-9.

FOx Pin Delay Time, tD(FO)
TJ = 25°C

0.5

Max.
0.4 Typ.
Min.
0.3
0.2
0.1
0
0

2

4

6

8

10

RFO (kΩ)

Figure 12-10.

Fault Signal Voltage vs. Pull-up
Resistor, RFO
TJ = 25°C

Delay TIme, tD(FO) (µs)

These pins operate as the fault signal outputs andshutdown signal inputs for each phase. Sections 12.3.1
and 12.3.2 explain the two functions in detail,respectively.
Figure 12-8 illustrates an internal circuit diagram of theFOx pin and its peripheral circuit. Because of its opendrain nature, each of the FOx pins should be tied by a pullup resistor, RFO, to the external power supply. The
external power supply voltage (i.e., the FOx Pin Pull-up
Voltage, VFO) should range from 3.0 V to 5.5 V. The filter
capacitor of the FOx pin, CFO, should have a capacitanceof ≤0.01 μF.
Figure 12-10 shows a relation between the FOx pin
voltage and the pull-up resistor, RFO. When the pull-up
resistor, RFO, has a too small resistance, the FOx pin
voltage at fault signal output becomes high due to the onresistance of a built-in MOSFET, QFOx (Figure 12-8).
Therefore, it is recommended to use a 3.3 kΩ to 22 kΩ
pull-up resistor when the Low Level Input Threshold
Voltage of the microcontroller, VIL, is set to 1.0 V.
To suppress noise, add a filter capacitor, CFO, near the
IC with minimizing a trace length between the FOx andCOMx pins. Note that, however, this additional filtering
allows a delay time to occur, as seen in Figure 12-9. The
delay time is a period of time which starts when the IC
receives a fault flag turning on the internal MOSFET,
QFOx, and continues until when the FOx pin reaches its
threshold voltage (VIL) of 1.0 V or below (put simply,
until the time when the IC detects a low state, “L”).Figure12-11 shows the relations between CFO and the FOx pin
delay time. For avoiding repeated OCP activations, theexternal microcontroller must shut off any input signals
to the IC within a fixed hold time, tP, after the internal
MOSFET (QFOx) turn-on. tP is 5 ms where minimum
values of thermal characteristics are taken into account(for more details, see Section 12.3.4). When VIL = 1.0 V,
the reference value of CFO is 0.001 μF to 0.01 μF.
Motor operation must be controlled by the external
microcontroller so that it can immediately stop the motor
when fault signals are detected. To resume the motor
operation thereafter, set the motor to be resumed after alapse of ≥2 seconds.

0.20

Max.

0.15
Typ.
0.10

Min.

0.05
0.00
0

200

400

600

800

1000

CFO (pF)

Figure 12-11.

Filter Capacitor, CFO vs. FOx Pin Delay
Time, tD(FO)SCM1242MA -DSE Rev.1.0
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SCM1242MA
Table 12-2. Shutdown Signals

12.3. Protection Functions
This section describes the various protection circuits
provided in the SCM1242MA. The protection circuits
include the undervoltage lockout for power supplies(UVLO), the simultaneous on-state prevention, theovercurrent protection (OCP), and the thermal shutdown(TSD). In case one or more of these protection circuits areactivated, the FOx pin outputs a fault signal; as a result,the external microcontroller can stop the operations of thethree phases by receiving the fault signal. The external
microcontroller can also shut down IC operations by
inputting a fault signal to the FOx pin. In the following
functional descriptions, “HOx” denotes a gate input
signal on the high-side transistor, whereas “LOx” denotes
a gate input signal on the low-side transistor (see also thediagram in Section 7). “VBx–HSx” refers to the voltages
between the VBx and HSx pins.

High Level
SignalLow Level Signal

3 V < VIN < 5.5 V

0 V < VIN < 0.5 V≥3.0 μs≥3.0 μs

Parameter
Input
Voltage
Input Pulse
Width

1 FO1
9 FO2
17 FO3

INT

RFO
CFO
VFO

Figure 12-12.

U1

4 COM112 COM2
20 COM3

All-phase Shutdown Circuit

12.3.1. Fault Signal Output
In case one or more of the following protections are
actuated, an internal transistor, QFOx, turns on, then the
FOx pin becomes logic low (≤0.5 V).

12.3.3. Undervoltage Lockout for Power
Supply (UVLO)

1) Low-side undervoltage lockout (UVLO_VCC)
2) Overcurrent protection (OCP)
3) Simultaneous on-state prevention
4) Thermal shutdown (TSD)

In case the gate-driving voltages of the output
transistors decrease, their steady-state power dissipations
increase. This overheating condition may cause
permanent damage to the IC in the worst case. To prevent
this event, the SCM1242MA has the undervoltage
lockout (UVLO) circuits for both of the high- and lowside power supplies.

While the FOx pin is in the low state, the high- and lowside transistors of each phase turn off. In normal operation,
the FOx pin outputs a high signal of about 5 V. The fault
signal output time of the FOx pin at OCP activation is thehold time, tP = 10 ms (typ.), fixed by a built-in feature of
the IC itself (see Section 12.3.4). The external
microcontroller receives the fault signals with its interrupt
pin (INT), and must be programmed to put the HINx and
LINx pins to logic low within the predetermined holdtime, tP. To resume motor operations thereafter, set the
motor to be resumed after a lapse of ≥2 seconds.

12.3.2. Shutdown Signal Input
The FOx pin also acts as the input pin of shutdown
signals. When the FOx pin becomes logic low, the highand low-side transistors of each phase turn off. The
voltages and pulse widths of shutdown signals should be
set as listed in Table 12-2.
In Figure 12-12, FO1, FO2 and FO3 are all connected.
If an abnormal condition is detected by any one of theMICs, the high- and low-side transistors of all phases turnoff at once.

12.3.3.1. Undervoltage Lockout for
High-side Power Supply(UVLO_VB)
Figure 12-13 shows operational waveforms of theundervoltage lockout for high-side power supply (i.e.,
UVLO_VB). When the voltage between the VBx andHSx pins (VBx–HSx) decreases to the Logic Operation
Stop Voltage (VBS(OFF) = 11.0 V) or less, the UVLO_VB
circuit in the corresponding phase gets activated and sets
an HOx signal to logic low. When the voltage between
the VBx and HSx pins increases to the Logic Operation
Start Voltage (VBS(ON) = 11.5 V) or more, the IC releases
the UVLO_VB condition. Then, the HOx signal becomes
logic high at the rising edge of the first input command
after the UVLO_VB release. Any fault signals are not
output from the FOx pin during the UVLO_VB operation.
In addition, the VBx pin has an internal UVLO_VB filterof about 3 μs, in order to prevent noise-induced
malfunctions.

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SCM1242MA
HINx
0

LINx
0
UVLO_VB
operation

VBx-HSx

VBS(ON)VBS(OFF)UVLO release0

No FOx output at
UVLO_VBFOx

As Figure 12-14 shows, when the VCCx pin voltage
decreases to the Logic Operation Stop Voltage(VCC(OFF) = 11.0 V) or less, the UVLO_VCC circuit in thecorresponding phase gets activated and sets both of HOx
and LOx signals to logic low. When the VCCx pin voltage
increases to the Logic Operation Start Voltage(VCC(ON) = 11.5 V) or more, the IC releases the
UVLO_VCC operation. Then it resumes transmitting the
HOx and LOx signals according to input commands on
the HINx and LINx pins. During the UVLO_VCC
operation, the FOx pin becomes logic low and sends fault
signals. In addition, the VCCx pin has an internal
UVLO_VCC filter of about 3 μs, in order to prevent
noise-induced malfunctions.

0
HOx restarts at
positive edge after
UVLO_VB release.

About 3 µs

HOx
0

LOx
0

Figure 12-13.

UVLO_VB Operational Waveforms

12.3.3.2. Undervoltage Lockout for
Low-side Power Supply(UVLO_VCC)
The VCCx pin has the VCC pin undervoltage lockout(UVLO_VCC) circuits for low-side power supply.
HINx
0

LINx
0

About 3 µs

VCCx
VCC(OFF)UVLO_VCC
operation

12.3.4. Overcurrent Protection (OCP)The OCPx pin has the overcurrent protection (OCP)
circuits. Figure 12-15 is an internal circuit diagram
describing the OCPx pin and its peripheral circuit. The
OCPx pin detects overcurrents with voltage across anexternal shunt resistor, RS. Because the OCPx pin isinternally pulled down, the OCPx pin voltage increases
proportionally to a rise in the current running through theshunt resistor, RS.
Figure 12-16 shows operational waveforms when the
OCPx pin detects an overcurrent condition. When the
OCPx pin voltage increases to the OCP Threshold
Voltage (VTRIP = 0.50 V) or more, and remains in thiscondition for a period of the OCP Blanking Time(tBK(OCP) = 370 ns) or longer, the corresponding OCP
circuit is activated. When an internal delay time(tD(OCP) = 0.3 µs) has elapsed after the OCP activation, theenabled OCP circuit shuts off the corresponding output
transistors and puts the FOx pin into a low state. Then,output current decreases as a result of the output transistor
turn-offs. Even if the OCPx pin voltage falls below VTRIP,
the IC holds the FOx pin in the low state for a fixed holdtime, tP = 10 ms. Then, the output transistors operateaccording to input signals.

VCC(ON)

U1

VTRIP

OCPx

0

FOx

2 kΩ

2 kΩ

+

100 kΩ0

VBB-

Blanking
filter
370 ns (typ.)

CO

HOx
COMx

Output transistors
turn-off and QFOturn-on0

LOx responds to input signal.

LSx
A/D

LOx

RO

0

Figure 12-14.

DRS

RS

COM

UVLO_VCC Operational Waveforms

Figure 12-15.

Internal Circuit Diagram of OCPx Pin
and Its Peripheral Circuit

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SCM1242MA
HINx
0

LINx
0

tBK(OCP)tD(OCP) 0.3 µs (typ.)tBK(OCP)tBK(OCP)

OCPx
VTRIP

0

FOx restarts
automatically after tP.

FOx
tP

and CO. The larger the time constant, the longer the timethat the OCPx pin voltage rises to VTRIP. And this may
cause permanent damage to the transistors. Consequently,
a propagation delay of the IC must be taken into accountwhen you determine the time constants. For RO and CO,their time constants must be set to ≤0.82 µs. The filter
capacitor, CO, should also be placed near the IC, between
the OCPx and COMx pins with a minimal length of traces.
Note that overcurrents are undetectable when one ormore of the U, V, and W pins or their traces are shorted
to ground (ground fault). In case any of these pins falls
into a state of ground fault, the output transistors may bedestroyed.

0HOx

HOx responds to input signal.

12.3.5. Simultaneous On-state Prevention

0

LOx
0

Figure 12-16.

OCP Operational Waveforms

A turn-off delay time of the output transistors depends
on the capacitance of the FOx pin capacitor, CFO. If thedelay time is too long, the output transistors may bedestroyed due to overcurrent. Thus, the value of CFO must
be set to ≤0.01 μF.
The OCP is used for detecting abnormal conditions,such as an output transistor shorted. In case short-circuit
conditions occur repeatedly, the output transistors can be
destroyed. To prevent such event, motor operation must
be controlled by the external microcontroller so that it can
immediately stop the motor when fault signals aredetected.
The external microcontroller receives the fault signals
with its interrupt pin (INT), and must be programmed to
put the HINx and LINx pins to logic low within thepredetermined hold time, tP. To resume motor operations
thereafter, set the motor to be resumed after a lapse of ≥2
seconds.
For proper shunt resistor setting, your application mustmeet the following:● Use the shunt resistor that has a recommended
resistance, RS (see Section 2).
● Set the OCPx pin input voltage to vary within the rated
OCPx pin voltages, VOCP (see Section 1).
● Keep the current through the output transistors below
the rated output current (pulse), IOP (see Section 1).
It is required to use a resistor with low internal
inductance because high-frequency switching current willflow through the shunt resistor, RS. In addition, choose aresistor with allowable power dissipation according to
your application.
When you connect a CR filter (i.e., a pair of a filter
resistor, RO, and a filter capacitor, CO) to the OCPx pin,care should be taken in setting the time constants of R O

In case both of the HINx and LINx pins receive logic
high signals at once, the high- and low-side transistors
turn on at the same time, causing overcurrents to passthrough. As a result, the switching transistors will be
destroyed. To prevent this event, the simultaneous onstate prevention circuit is built into each of the MICs.
Note that incorrect command input and noise interference
are also largely responsible for such a simultaneous-on
condition. Figure 12-17 shows operational waveforms of
the simultaneous on-state prevention.
Simultaneous on-stateprevention enabled

HINx
0

LINx
0

HOx

About 0.8 µs

0LOx

About 0.8 µs

0

FOx
0

Figure 12-17. Operational Waveforms of
Simultaneous On-state Prevention
When logic high signals are asserted on the HINx and
LINx pins at once, as in Figure 12-17, this function gets
activated and turns the high- and low-side transistors off.
Then, while the function is being enabled, the FOx pin
becomes logic low and sends fault signals. After the IC
comes out of the simultaneous on-state condition, “HOx”
and “LOx” start responding in accordance with HINx and
LINx input commands again.
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SCM1242MA
simultaneous on-state prevention circuit has a filter ofabout 0.8 μs. Note that this function does not have any ofdead-time programming circuits. Therefore, input signals
to the HINx and LINx pins must have proper dead times
as defined in Section 12.2.6.

13. Design Notes
This section also employs the notation systemdescribed in the beginning of the previous section.

13.1. PCB Pattern Layout
12.3.6. Thermal Shutdown (TSD)The SCM1242MA incorporates the thermal shutdown(TSD) circuits (see Section 7).
The TSD circuit protects the IC from overheating, suchas increased power dissipation due to overload, or
elevated ambient temperature at the device. When thetemperature of any one of the MICs exceeds the TSD
Operating Temperature (TDH = 150 °C) due to suchoverheating, the corresponding TSD circuit is activated.
During the TSD operation, the IC turns off the high- andlow-side output transistors in the corresponding phaseand outputs a fault signal (see Figure 12-18).
When the temperature of the corresponding MIC
decreases to the TSD Releasing Temperature(TDL = 120 °C) or less thereafter, the shutdown condition
is released. The output transistors then resume operating
according to input signals. Note that junction
temperatures of the output transistors themselves are notmonitored; therefore, do not use the TSD function as an
overtemperature prevention for the output transistors.

Figure 13-1 shows a schematic diagram of a motor
drive circuit. The circuit consists of current paths having
high frequencies and high voltages, which also bringabout negative influences on IC operation, noiseinterference, and power dissipation. Therefore, PCB tracelayouts and component placements play an important rolein circuit designing. Current loops, which have highfrequencies and high voltages, should be as small andwide as possible, in order to maintain a low-impedancestate. In addition, ground traces should be as wide andshort as possible so that radiated EMI levels can be
reduced.
U1
VBB

MIC3

W

LS3

VDC
25

26

27

Ground traces
should be wideand short.

HINx
0

MIC2

LINx

29

V

0

LS2

TSD operation

TJ(MIC)

M

30

TDH
TDL

MIC1

0

U

32

HOx responds to input signal.

HOx
0

LS1

LOx

33
High-frequency, high-voltage
current loops should be as small
and wide as possible.

0

Figure 13-1.

FOx

High-frequency, High-voltage Current
Paths

0

Figure 12-18.

TSD Operational Waveforms

13.2. Considerations in Heatsink Mounting
The following are the key considerations and theguidelines for mounting a heatsink:● Be sure to use a metric screw of M3 and a plain washerof 7 mm (φ). To tighten the screws, use a torquescrewdriver. Tighten the two screws firstly up to about
30% of the maximum screw torque, then finally up to
100% of the prescribed maximum screw torque.
Perform appropriate tightening within the range of

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SCM1242MA
screw torque defined in Section 4● When mounting a heatsink, it is recommended to use
silicone greases. If a thermally conductive sheet or anelectrically insulating sheet is used, package cracks
may be occurred due to creases at screw tightening.
Therefore, you should conduct thorough evaluations
before using these materials.
● When applying a silicone grease, make sure that there
are no foreign substances between the IC and aheatsink. Extreme care should be taken not to apply asilicone grease onto any device pins as much as
possible. The following requirements must be met for
proper grease application:− Grease thickness: 100 µm− Heatsink flatness: ±100 µm− Apply a silicone grease within the area indicated in
Figure 13-2, below.

phase. And all the pins that are not represented in thesefigures are open.
Before conducting a measurement, be sure to isolate
the ground of the to-be-measured phase from those ofother two phases not to be measured. Then, in each of thetwo phases, which are separated not to be measured,connect the LSx and COMx pins each other at the samepotential, and leave them unused and floated.
U1
VBB

25

Q1H
4 COM1

MIC1

U 32

V

Q1L
LS1
33
31

Screw hole

Screw hole

Q2H
V
12 COM2

5.8

5.8

M3

Thermal silicone
grease application area

29

MIC2

Q2L

LS2

30

M3
Q3H

Heatsink
3.1

37.1

20 COM3

3.1

MIC3

Unit: mm

W

26

Q3L
LS3

27

Figure 13-2.

Reference Application Area for Thermal
Silicone Grease
Figure 13-3. Typical Measurement Circuit for Highside Transistor (Q1H) in U-phase

13.3. Considerations in IC Characteristics
Measurement
When measuring the breakdown voltage or leakage
current of the transistors incorporated in the IC, note thatthe gate and emitter of each transistor should have thesame potential. Moreover, care should be taken during themeasurement because the collectors of the high-side
transistors are all internally connected to the VBB pin.
The output (U, V, and W) pins are connected to theemitters of the corresponding high-side transistors,
whereas the LSx pins are connected to the emitters of the
low-side transistors. The gates of the high-side transistors
are pulled down to the corresponding output (U, V, andW) pins; similarly, the gates of the low-side transistors
are pulled down to the COMx pins.
When measuring the breakdown voltage or leakage
current of the transistors incorporated in the IC, note that
all of the output (U, V, and W), LSx, and COMx pins
must be appropriately connected. Otherwise, theswitching transistors may result in permanent damage.
The following are circuit diagrams representing typicalmeasurement circuits for breakdown voltage: Figure 13-3
shows the high-side transistor (Q1H) in the U-phase;
Figure 13-4 shows the low-side transistor (Q1L) in the U-

U1
VBB

25

Q1H
4 COM1

U 32

MIC1

V

Q1L

LS1
33
31

Q2H
12 COM2

V
29

MIC2

Q2L
LS2

30

Q3H
20 COM3

MIC3

W

26

Q3L
LS3

27

Figure 13-4. Typical Measurement Circuit for Lowside Transistor (Q1L) in U-phase

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SCM1242MA
14. Calculating Power Losses andEstimating Junction Temperature● DT0051: SCM1242MA Calculation Tool
https://www.semicon.sanken-ele.co.jp/en/calctool/igbt1_caltool_en.html

14.1. IGBT Steady-state Loss, PON
Steady-state loss in an IGBT can be computed by using
the VCE(SAT) vs. IC curves, listed in Section 15.2.1. As
expressed by the curves in Figure 14-1, a linear
approximation at a range the IC is actually used is
obtained by: VCE(SAT) = α × IC + β.
The values gained by the above calculation are thenapplied as parameters in Equation (4), below. Hence, theequation to obtain the IGBT steady-state loss, PON, is:
PON =

1 π
(φ) × IC (φ) × DT
∫ V
2π 0 CE(SAT)
× dφ

1 1
4
= α( +
M × cos θ) IM 2
2 2 3π(4)√2 1 π+β ( + M × cos θ) IM .
π
2 8Where:VCE(SAT) is the collector-to-emitter saturation voltage of
the IGBT (V),IC is the collector current of the IGBT (A),DT is the duty cycle, which is given byDT =y = 0.075x + 0.86
2.0

VCE(SAT) (V)This section describes the procedures to calculate
power losses in a switching transistor, and to estimate ajunction temperature. Note that the descriptions listed
here are applicable to the SCM1242MA, which iscontrolled by a 3-phase sine-wave PWM driving strategy.
Total power loss in an IGBT can be obtained by taking
the sum of steady-state loss, PON, and switching loss, PSW.
The following subsections contain the mathematicalprocedures to calculate the power losses in an IGBT and
its junction temperature.
For quick and easy references, we offer calculation
support tools online. Please visit our website to find out
more.

VCCx = 15 V

2.5

25 °C

1.5
1.0

125 °C

0.5

75 °C

0.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

IC (A)

Figure 14-1.

Linear Approximate Equation of VCE(SAT)vs. IC

14.2. IGBT Switching Loss, PSW
Switching loss in an IGBT, PSW, can be calculated by
Equation (5), letting IM be the effective current value ofthe motor:
PSW =

VDC
√2
× fC × αE × IM ×
.
π
300

(5)

Where:
fC is the PWM carrier frequency (Hz),VDC is the main power supply voltage (V), i.e., the VBB
pin input voltage, andαE is the slope of the switching loss curve (see Section
15.2.2).

14.3. Estimating Junction Temperature of
IGBT
The junction temperature of an IGBT, T J, can be
estimated with Equation (6):
TJ = R (j−C)Q × (PON + PSW ) + TC .

(6)

Where:
R(J-C)Q is the junction-to-case thermal resistance per
IGBT (°C/W), andTC is the case temperature (°C), measured at the point
defined in Figure 3-1.

1 + M × sin(φ + θ),
2

M is the modulation index (0 to 1),cosθ is the motor power factor (0 to 1),
IM is the effective motor current (A),α is the slope of the linear approximation in the VCE(SAT)vs. IC curve, andβ is the intercept of the linear approximation in the
VCE(SAT) vs. IC curve.

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SCM1242MA
15. Performance Curves
15.1. Performance Curves of Control Parts
Figure 15-1 to Figure 15-21provide performance curves of the control parts integrated in the SCM1242MA, including
variety-dependent characteristics and thermal characteristics. TJ represents the junction temperature of the control parts.
Table 15-1. Typical Characteristics of Control Parts
Figure Number
Figure 15-1
Figure 15-2
Figure 15-3
Figure 15-4
Figure 15-5
Figure 15-6
Figure 15-7
Figure 15-8
Figure 15-9
Figure 15-10
Figure 15-11
Figure 15-12
Figure 15-13
Figure 15-14
Figure 15-15
Figure 15-16
Figure 15-17
Figure 15-18
Figure 15-19
Figure 15-20
Figure 15-21

Figure Caption
Logic Supply Current in 3-phase Operation, ICC vs. TC
Logic Supply Current in 3-phase Operation, ICC vs. VCCx Pin Voltage, VCC
Logic Supply Current in 1-phase Operation (HINx = 0 V), IBS vs. TC
Logic Supply Current in 1-phase Operation (HINx = 5 V), IBS vs. TC
Logic Supply Current in 1-phase Operation (HINx = 0 V), IBS vs. VBx Pin Voltage, VB
Logic Operation Start Voltage, VBS(ON) vs. TC
Logic Operation Stop Voltage, VBS(OFF) vs. TC
Logic Operation Start Voltage, VCC(ON) vs. TC
Logic Operation Stop Voltage, VCC(OFF) vs. TC
UVLO_VB Filtering Time vs. TC
UVLO_VCC Filtering Time vs. TC
Input Current at High Level (HINx or LINx), IIN vs. TC
High Level Input Signal Threshold Voltage, VIH vs. TC
Low Level Input Signal Threshold Voltage, VIL vs. TC
Minimum Transmittable Pulse Width for High-side Switching, tHIN(MIN) vs. TC
Minimum Transmittable Pulse Width for Low-side Switching, tLIN(MIN) vs. TC
FOx Pin Voltage in Normal Operation, VFOL vs. TC
OCP Threshold Voltage, VTRIP vs. TC
OCP Blanking Time, tBK(OCP) + Propagation Delay, tD(OCP) vs. TC
OCP Hold Time, tP vs. TC
Filtering Time of Simultaneous On-state Prevention vs. TC

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VCC x= 15 V, HINx = 0 V, LINx = 0 V

4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0

HIN x= 0 V, LINx = 0 V

3.3
Max.

3.2

Typ.
Min.

125 °C

3.2

ICC(mA)

ICC(mA)SCM1242MA

3.1
3.1
25 °C

3.0
−30 °C

3.0
2.9
-30

0

30

60

90

120

12

150

13

14

15

Figure 15-1.

Logic Supply Current in 3-phase
Operation, ICC vs. TC

18

19

20

VBx = 15 V, HINx = 5 V

250

250

200

200

Max.

150

Typ.

150

Max.

100

Typ.
Min.

IBS (µA)

IBS (µA)

17

Figure 15-2. Logic Supply Current in 3-phase
Operation, ICC vs. VCCx Pin Voltage, VCC

VBx = 15 V, HINx = 0 V

50

Min.
100
50

0
-30

0

30

60

90

120

0

150

-30

0

30

TC (°C)

60

90

120

150

TC (°C)

Figure 15-3. Logic Supply Current in 1-phase
Operation (HINx = 0 V), IBS vs. TC

Figure 15-4. Logic Supply Current in 1-phase
Operation (HINx = 5 V), IBS vs. TC

VBx = 15 V

160

12.5
Max.

12.0

140

Typ.

120

11.5

100

125 °C80−30 °C

60

25 °C

40

VBS(ON) (V)IBS (µA)

16

VCC (V)TC (°C)

Min.
11.0
10.5
10.0

20
0

9.5
12

13

14

15

16

17

18

19

20

-30

0

VB (V)

Figure 15-5. Logic Supply Current in 1-phase
Operation (HINx = 0 V), IBS vs. VBx Pin Voltage, VB

30

60

90

120

150

TC (°C)

Figure 15-6.

Logic Operation Start Voltage, VBS(ON) vs.
TC

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SCM1242MA
12.5

12.0
Max.
Typ.

11.0

Min.
10.5
10.0

VCC(ON) (V)VBS(OFF) (V)

11.5

12.0

Max.

11.5

Typ.

11.0

Min.

10.5
10.0

9.5

9.5

9.0
-30

0

30

60

90

120

-30

150

0

30

Logic Operation Stop Voltage, VBS(OFF)vs. TCVCC(OFF) (V)

12.0
11.5

Max.

11.0

Typ.

10.5

Min.

10.0
9.5
9.0
-30

0

30

60

90

120

Figure 15-8.

UVLO_VB Filtering Time (µs)

Figure 15-7.

4.0

Max.

3.0

Typ.

2.0

Min.

1.0
0.0
0

30

Max.

4.0
3.0

Typ.

2.0

Min.

1.0
0.0
90

120

150

IIN (µA)UVLO_VCC Filtering Time (µs)

Figure 15-10.

5.0

60

90

120

150

UVLO_VCC Filtering Time vs. TC

UVLO_VB Filtering Time vs. TC

INHx/INLx = 5 V

450
400
350
300
250
200
150
100
50
0

Max.
Typ.
Min.

-30

TC (°C)

Figure 15-11.

60

TC (°C)

6.0

30

150

5.0

-30

7.0

0

120

6.0

150

Logic Operation Stop Voltage, VCC(OFF)vs. TC-30

90

Logic Operation Start Voltage, VCC(ON) vs.
TC

TC (°C)

Figure 15-9.

60TC (°C)TC (°C)

0

30

60

90

120

150

TC (°C)

Figure 15-12.

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Input Current at High Level (HINx or
LINx), IIN vs. TC

29

SCM1242MA

2.6

2.0

2.4

1.8

2.0

Max.

1.8

Typ.

1.6

Min.

1.6

VIL (V)VIH (V)

2.2

1.4

Max.
Typ.

1.2

Min.

1.4
1.0

1.2
1.0

0.8
-30

0

30

60

90

120

150

-30

0

30

TC (°C)

Figure 15-13.

High Level Input Signal Threshold
Voltage, VIH vs. TC

Figure 15-14.

350

Min.

200
150
100

tLIN(MIN) (ns)tHIN(MIN) (ns)

120

150

Low Level Input Signal Threshold
Voltage, VIL vs. TC

Max.

300

Typ.

250

250
Typ.

200
150

Min.

100
50

50

0

0
-30

0

30

60

90

120

-30

150

0

30

TC (°C)

60

90

120

150

TC (°C)

Figure 15-15. Minimum Transmittable Pulse Width for
High-side Switching, tHIN(MIN) vs. TC

Figure 15-16. Minimum Transmittable Pulse Width for
Low-side Switching, tLIN(MIN) vs. TC

FOx pull-up voltage = 5 V, RFO = 3.3 kΩ, FOx in logic low

0.54
0.53

700

Max.

0.52

600

Max.

500
400
300

Typ.
Min.

200
100

VTRIP (V)VFOL (mV)

90

350
Max.

300

800

60

TC (°C)

0.51
Typ.

0.50
0.49
0.48

Min.

0.47

0
-30

0

30

60

90

120

150

TC (°C)

Figure 15-17.

FOx Pin Voltage in Normal Operation,
VFOL vs. TC

0.46
-30

0

30

60

90

120

150

TC (°C)

Figure 15-18.

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OCP Threshold Voltage, VTRIP vs. TC

30

SCM1242MA

1.2
1.0
Max.

0.8

Typ.
Min.

0.6
0.4
0.2
0.0
-30

0

30

60

90

120

150

tP (ms)tBK(OCP) + tD (OCP) (ns)

1.4

18
16
14
12
10
8
6
4
2
0

Max.

Typ.
Min.

-30

0

60

90

120

150

TC (°C)TC (°C)

Figure 15-19. OCP Blanking Time, tBK(OCP) +Propagation Delay, tD(OCP) vs. TC

Filtering Time of Simultaneous
On-state Prevention (µs)

30Figure 15-20.

OCP Hold Time, tP vs. TC

1.6
1.4
1.2
Max.

1.0
0.8
0.6

Typ.

0.4

Min.

0.2
0.0
-30

0

30

60

90

120

150

TC (°C)

Figure 15-21.

Filtering Time of Simultaneous On-state
Prevention vs. TC

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SCM1242MA
15.2. Performance Curves of Output Parts
15.2.1. Output Transistor Performance Curves
VCCx = 15 V

2.5

25 °C

1.5

VF (V)VCE(SAT) (V)

2.0

1.0
75 °C

0.5

125 °C

0.0
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0

25 °C

75 °C 125 °C

0

1

2

3

4

5

IC (A)

Figure 15-22.

6

7

8

9 10 11 12 13 14 15

IF (A)IGBT VCE(SAT) vs. IC

Figure 15-23.

Freewheeling Diode VF vs. IF

15.2.2. Switching Loss Curves
Conditions: VBB pin voltage = 300 V, half-bridge circuit with inductive load.
Switching Loss, E, is the sum of turn-on loss and turn-off loss.
VBx = 15 V

1400
1200

TJ = 125 °C

800

E (µJ)E (µJ)

1000

600
400

TJ = 25 °C

200
0
0.0

5.0

10.0

15.0

VCCx = 15 V

1800
1600
1400
1200
1000
800
600
400
200
0

TJ = 125 °C

TJ = 25 °C

0.0

IC (A)

Figure 15-24.

High-side Switching Loss

5.0

10.0

15.0

IC (A)

Figure 15-25.

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Low-side Switching Loss

32

SCM1242MA
15.3. Allowable Effective Current Curves
The following curves represent allowable effective currents in 3-phase sine-wave PWM driving with parameters suchas typical VCE(SAT) and typical switching losses.
Operating conditions: VBB pin input voltage, VDC = 300 V; VCCx pin input voltage, VCC = 15 V; modulation index,
M = 0.9; motor power factor, cosθ = 0.8; junction temperature, T J = 150 °C.
fC = 2 kHz

Allowable Effective Current (Arms)

12.0
10.0
8.0
6.0
4.0
2.0
0.0
25

50

75

100

125

150

TC (°C)
Figure 15-26.

Allowable Effective Current (fC = 2 kHz)fC = 16 kHz

Allowable Effective Current (Arms)

12.0
10.0
8.0
6.0
4.0
2.0
0.0
25

50

75

100

125

150

TC (°C)
Figure 15-27.

Allowable Effective Current (fC = 16 kHz)SCM1242MA -DSE Rev.1.0
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SCM1242MA
15.4. Transient Thermal Resistance Curves
The following graphs represent transient thermal resistance (the ratios of transient thermal resistance), with steadystate junction-to-case thermal resistance = 1. Note that the graph shows only IGBT characteristics; no freewheeling diodecharacteristics are included.

Ratio of Transient Thermal
Resistance

1.00

0.10

0.01
0.001

0.01

0.1

1

10

Time (s)Figure 15-28.

Transient Thermal Resistance

15.5. Short Circuit SOA (Safe Operating Area)
Conditions: VDC ≤ 400 V, 13.5 V ≤ VCC ≤ 16.5 V, TJ = 125 °C, 1 pulse.

Collector Current, IC(Peak) (A)

250
200
150
100
Short Circuit SOA

50
0
0

1

2

3

4

5

Pulse Width (µs)
Figure 15-29.

Short Circuit SOA

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SCM1242MA
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DSGN-CEZ-16003

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