Optimization design of an Isolated DC/DC Converter
Using Series Compensation on the Secondary Side

Satoshi Miyawaki

Jun-ichi Itoh

Kazuki Iwaya

Student Member, IEEE
Nagaoka University of Technology
1603-1 Kamitomioka-cho Nagaoka
City
Niigata, Japan
miyawaki@stn.nagaokaut.ac.jp

Member, IEEE
Nagaoka University of Technology
1603-1 Kamitomioka-cho Nagaoka
City
Niigata, Japan
itoh@vos.nagaokaut.ac.jp

Member, IEEE
TDK-LAMBDA, Ltd
2701 Tokawa Settaya Nagaoka City
Niigata, Japank.iwaya@jp.tdk-lambda.com

Abstract -- This paper proposes a new circuit topology for ahigh efficiency isolated buck-boost DC/DC converter. The
proposed converter consists of a high efficiency resonance halfbridge converter and a series converter. This proposed circuit
regulates the output voltage by the series converter, which
provides only the differential voltage between the input voltage
and the output voltage. Therefore, the circuit achieves highefficiency when the input voltage is closed to the nominal voltage,
since only the resonance converter will operate. The equivalentcircuit of the proposed circuit is mentioned to clarify the circuit
operation and circuit design. The experimental results
confirmed that the proposed circuit, which converts 48-V input
to 12-V output, achieves the maximum efficiency of 94.0% at thenominal input voltage region. Besides, the loss analysis isperformed to optimize the circuit parameters.
Index Terms-- DC/DC converter, Isolated converter, Series
voltage compensation, Current resonanceI.

INTRODUCTION

Recently, high efficiency and high power density of power
supplies are increasingly desired for telecom applications andmicroprocessor boards. In addition, these power converters
have to supply larger output current with very low output
voltage for the loads. In order to achieve high efficiency andhigh power density, the power system is divided into several
converters, such as point-of-load converter, bus converters
and front end converter. In this system, the power isdistributed to each of the device by a DC voltage line [1-5].
The DC bus converter, which regulates the constant DC
voltage for the output side, is required at the input point ofeach device because the DC bus voltage will fluctuate due tothe bus impedance when the load condition had changed. The
DC bus converter is also used to obtain different levels of DC
voltage from the DC bus voltage. Therefore, high efficiency
DC/DC converters are required for these bus converters.
Resonant type half-bridge converters, which use
resonance between the leakage inductance of transformers
and the DC capacitor, are one of the most effective circuit
topologies to obtain high efficiency. However, it is difficult
to regulate the output voltage in a wide range while there is afluctuation in the input voltage because the switching timing
is constrained by the resonance period. Therefore, a resonanttype half-bridge converter is generally connected to a voltage
control converter, such as a buck chopper [6-7]. As a result,the converter loss increases because all the power passes
through two converters; the voltage control converter and theresonant converter.
This paper proposes a new topology for an isolated
DC/DC converter using a series voltage compensation. The
input voltage fluctuation is compensated by the auxiliary
circuit that outputs only the fluctuation of the output voltage[8-11]. One of the advantages of the proposed circuit is thathigh efficiency can be achieved when the input voltage isclosed to the nominal input voltage because the power of theauxiliary circuit becomes very small in comparison to the
input power. Generally, the large fluctuations of the DC bus
voltage are not generated for long periods, and as a result, theconverter loss can be reduced.
Firstly, the approach used to obtain high efficiency withthe proposed series compensation method is introduced inthis paper. The circuit configuration and the control strategy
are described accordingly. Secondary, the operation mode isanalyzed using a simple equivalent circuit of the proposed
circuit. The stability of the operation in the proposed circuit
is clarified. In addition, the design strategy for optimization isclarified. Finally, some experimental results and loss analysis
are given in order to demonstrate the advantages of the
proposed converter.
II.
A.

CIRCUIT CONFIGURATIONSConventional Circuit
Fig. 1 shows a configuration of a conventional DC/DC
converter. The conventional circuit consists of a resonant
half-bridge converter and the voltage control converter, suchas a buck boost chopper. The fluctuation of the input voltage
is constantly controlled by the buck chopper. The output side
is isolated by the resonant half-bridge converter to the input
side. This system has two stages of the power flow from

input to output. The total efficiency of the conventional
circuit ηc is obtained from (1); using both the resonant
converter efficiency η1 and the buck chopper efficiency η2.
η c = η1η 2(1)
All the power passes through both converters despite therelation with the input voltages; therefore, the converter
efficiency is decreased.
Proposed Circuit
Fig. 2 shows the configuration of the proposed converter
using series connection on secondary side. In the proposed
circuit, this system consists of two power converters; main
circuit and auxiliary circuit, which are connected in series tothe output side using a transformer.
The main circuit is the resonant type half-bridge converterwith isolation transformer. Zero current switching (ZCS) is
implemented by the resonance circuit between the leakage
inductance of the transformer and the resonance capacitor in
the DC part, in order to achieve high efficiency. The
switching frequency of the main circuit is constrained by theresonance frequency f0.
The switching frequency of the main circuit is constrainedby the resonance frequency f0. From the equivalent circuit of
the transformer shown in Fig. 2(a), the resonant inductanceof the proposed circuit L is obtained from (2), using theleakage inductance lxx, mutual inductance Mxx and the numberof wire turns Nxx.

Buck chopper

Resonant converter

Vout

Vin

(a)

Circuit diagram.

B.

L = l11 +M 1 (l12 + LT 2 )M 1 + (l12 + LT 2 )(b) Power flow diagram.
Fig. 1. Conventional circuit using a buck chopper and a resonant
converter.

(2)
(a)

Circuit diagram.

2⎛ N11 ⎞ ⎛ N 22 ⎞⎛l22 M 2 ⎞⎟ ⎜⎟⎜⎟⎟ ⎜ N ⎟⎜ l21 + l + M ⎟N22
2 ⎠⎝ 12 ⎠ ⎝ 21 ⎠⎝where, LT 2 = ⎜⎜The resonance frequency of the proposed circuit f0 is
obtained by (3).
f0 =

1
2π LC

(3)

On the other hand, the auxiliary circuit is the full-bridge
converter uses for regulating the output voltage. The output
voltage of the auxiliary circuit is added to the output of themain circuit by the transformer. That is, the auxiliary circuit
compensates only the fluctuation voltage, against the output
voltage commands.
The proposed system consists of two power converters,
which are connected in series to the output side. The reason
for high efficiency in the proposed circuit is as follows. The
power Pout is obtained by adding the auxiliary converter
power P3 to the directly power P0, as shown by Fig. 2(b). The
total converter efficiency of the proposed circuit ηp is
obtained by (4), using the auxiliary circuit efficiency η3 andthe power ratio k=P3/P0.
η p = η1

1 + kη 3
1+ k(4)(b) Power flow diagram.
Fig. 2. Proposed circuit using series connection on secondary side.

It should be noted that the voltage rating of the switching
device in the auxiliary converter is lower than the main
circuit since the output voltage is lower than the input voltage.
That is, the conduction loss of the auxiliary circuit can be
decreased.
III. CONTROL STRATEGY
In the proposed circuit, the main circuit is controlled underan optimum condition as the resonant converter. In order toobtain the maximum efficiency, the resonant converter
operates at 50% duty cycle based on the resonance frequency
f0. Therefore, the main circuit can achieve zero current

switching (ZCS) at any time.
Fig. 3 shows the operation mode and the waveforms in the
primary side of the transformer in the boost mode. The
switching timing of the auxiliary circuit is synchronous withthe main circuit. The auxiliary circuit can output threedifferent voltage levels; +Vout, -Vout, and zero voltage. In the
boost mode; i.e. when the input voltage is decreased, theauxiliary circuit outputs positive phase voltage to the output
voltage of the main circuit without preventing the resonance
operation in the main circuit. Similarly, in the buck mode; i.e.
when the input voltage is increased; the auxiliary circuit
outputs negative phase voltage to the output voltage of themain circuit.
The output voltage is controlled by changing the pulse
width D of the auxiliary circuit. If the voltage drop from theleakage inductance and winding resistance are negligible, thepulse width of the auxiliary circuit D is obtained by (6), using
the switching (resonance) cycle T and the output voltage
command Vout*.
D=

*
V ⎞
N
T N 21 ⎛⎜ Vout⋅⋅
− 12 ⋅ in ⎟⎜2 N 22 ⎝ Vout 2 N11 Vout ⎟⎠(6)

Fig. 4 shows the control block diagram of the proposed
circuit. The duty cycle of the main circuit is set to 50%. In
the auxiliary circuit, the output pulse width D is calculated byan automatic voltage regulator (AVR) according to output
voltage command. The phase shift gain is then calculated by
D. The phase shift is used to decrease the switching loss inthe auxiliary circuit, because the phase of the output voltage
in the auxiliary circuit can be adjustable to the phase of theoutput voltage in the main circuit. According to the relation
between the output and input voltages, the mode selector
determines the operation mode. It should be note that the
proposed converter has the reference voltage mode, whichmeans that the auxiliary circuit stops when the input voltage
is almost the same as the nominal input voltage, in addition to
the buck and boost mode operation.

Fig. 3. Corresponding of the switching pattern and operation mode.

IV. OPERATIONAL MODE ANALYSIS
A.

Simple Equivalent Circuit
The proposed circuit is clarified in order to understand thestability of operation and the operational mode is analyzed
using a simple equivalent circuit. Fig. 5 shows the equivalentcircuit of the proposed circuit under the boost operation. In
the AC signal analysis, the switching operation of the main
circuit and the rectifier part at the output side is expressed asa square wave power source, which has the amplitude of the
input and output voltage at the frequency of the switchingfrequency respectively. The capacitors of the half-bridge
converter can be represented as one resonance capacitor with
ideal transformers. Moreover, the full-bridge converter in theauxiliary circuit is represented as three different voltage
levels; +Vout, -Vout, and zero voltage. Note that the excitationinductance of the transformer is disregarded in the analysis

Fig. 4. Control block diagram of the proposed circuit.

because it is much larger than the leakage inductance. The
resonance frequency is dominated by the leakage inductance.
B.

Derivation of the circuit equation
Fig. 6(a) and (b) show the simplified equivalent circuit
which is separated into the main circuit side and auxiliary
circuit side, according to the superposition principle. The

separation of the equivalent circuit is achieved by focusing
on the transformer input current iTm of the main circuit. The
equivalent circuit is obtained from the perspective of themain circuit, when the input of the auxiliary circuit is shortcircuited. Similarly, the equivalent circuit is obtained fromthe perspective of the auxiliary circuit, when the input of themain circuit is short-circuited; iTm is obtained by (7).
iTm = iTm _ m + iTm _ a(7)Fig. 5. Simple equivalent circuit

where iTm_m is the input current on the main circuit side asshown in Fig. 6(a) and iTm_a is the input current on theauxiliary circuit side as shown in Fig. 6(b). Consequently, theequation of the entire circuit can be obtained by deriving
each equation from each of the circuit equation in Fig. 6. The
input current iTm_m and iTm_a are obtained from (8) and (9).

(a)

αV
⎤
⎡ 1 Vinsin (ωt ) − out sin (ωt )⋅⎥1 ⎢− t 2 ωL
ωL⎥
iTm _ m = e τ ⎢
⎛
⎥
⎢
⎫
⎧
1
1 ⎞
⎜
⎟
i
cos
(
ω
t
)
sin
(
ω
t
)
q
ω
1
sin
(
ω
t
)
−
+
+
−
⎬ m (k ) ⎜⎥⎢ m (k ) ⎨
2 ⎟
2
Q
4
Q
⎭
⎝
⎩
⎠
⎦
⎣

Only main circuit.

(b) Only auxiliary circuit.
Fig. 6. Separation of circuit by superposition principle.

(8)
α∆Vout⎡ α Vout⎤⎢ β ⋅ ωL sin (ωt ) − ωL sin (ωt )⎥⎥iTm _ a = e τ ⎢
⎢
⎥
⎧
⎫
⎛
1
1 ⎞
⎟ sin (ωt )⎥sin (ωt )⎬ − qa (k )ω ⎜⎜1 +⎢+ ia (k ) ⎨cos(ωt ) −
2 ⎟
2
Q
4
Q
⎩
⎭
⎝
⎠
⎣⎢
⎦⎥
1
− t

(9)
where, τ =ωL1 ⎛ 1 ⎞−⎜ 2 ⎟ , Q =LC ⎝ τ ⎠
R

2L
, ω=
R
2

2

⎛α ⎞
⎛α ⎞
R = R1 + ⎜⎜ ⎟⎟ R2 , L = L1 + ⎜⎜ ⎟⎟ L2
⎝β ⎠
⎝β ⎠

im(k) and ia(k) are the initial currents of the leakage
inductions, and qm(k) and qa(k) are the initial charges ofresonance capacitor for the main and auxiliary sides,
respectively. The optimization design of the proposed circuit
can be obtained from this equation.
V.
A.

DESIGN OPTIMIZATION METHOD

Outline of the circuit design
Fig. 7 shows the design flowchart for the proposed circuit.
Optimization of the design is achieved by following thedesign flow. Firstly, the five circuit design specifications are
determined by applications, which consist of the volume of
the circuit, the minimum power of the stable operation area
Pmin, the fluctuation range of the input voltage Vfluc, the input
and output voltage Vin, Vout, and the rated power Pmax. The
resonance frequency is determined by the switchingfrequency. The resonance impedance is then designed basedon the specifications. Specifically, the minimum value of theresonance inductance L is limited by the minimum power ofthe stable operation area Pmin. After L is determined, resonantFig. 7. Optimization design procedure flowchart.

capacitor C can be obtained by (3) according to the resonancefrequency. Note that the resonance impedance needs to be
adjusted accordingly so that the maximum voltage of C is notlarger than the minimum input voltage.
B.

Determination of the resonant impedance
In order to control the output voltage, a stable operation isrequired. The discontinuance mode of the resonance current
causes instability in the light load area. The boundary
condition indicates the edge state between the continuous anddiscontinuous current. The boundary condition for the stable
operation depends only on the operation of the auxiliary
circuit in Fig. 6(b). In this state, the peak value of thetransformer current increases significantly compared to thecontinuous mode because the same output power is obtained

as the boundary condition using a narrow current pass period.
The instability problem also encountered for discontinuous
current mode of a boost reactor in a chopper circuit.
Therefore, the continuous mode has to be maintained until
the minimum power Pmin is outputted. The lower limit in thelight load in where the continuous mode is maintained
depends on the resonance impedance.
Fig. 8 shows the resonant current waveforms for the
separate auxiliary circuit shown in Fig. 6(b). At the boundary
condition in section (i), the current value iTm_a until t1 is zero
because the boundary condition indicates the edge state
between the continuous and discontinuous current. Next, iTm_ain section (ii) can be obtained from (10) using a linear
approximation according to the inductance L and output
voltage. Note that the capacitor voltage is equaled to theaverage value of the output voltage for one switching period
in the auxiliary circuit ∆Vout.
iTm _ a (ii ) =α Vout
⋅
D
β L

(10)

Input current on the auxiliary circuit side iTm_a becomes the
maximum at t2, and decreases in section (iii). The output
voltage period (output pulse width D in the auxiliary circuit)is limited according to (11).
2 D0 >

T−D
2

Fig. 8. Resonant current waveforms only on separating auxiliary circuitin Fig. 6(b).
TABLE ICIRCUIT SPECIFICATIONS(11)

where D0 is the zero voltage period of the auxiliary circuit fora half cycle.
When, the linear approximation is used, the current
waveform is approximated to be a triangular shape. Therefore,
the mean current value I0 for the half cycle is obtained by
(12).
I0 =

⎫
2 ⎧ 1 α Vout
D(D + D0 )⎬⎨ ⋅T ⎩2 β L⎭-6(×10 )(12)

4

On the other hand, the mean current value I0 is obtained
from the output power with (13), using the load resistance RL
and the average value of the output voltage in the auxiliary
circuit ∆Vout.
I0 =

∆Vout
αR L

3
2

(13)

1

Thus, the range of L for stable operation is obtained by(14), using (11) to (13).
L≥

α 2Vout 3 D

⎛
D ⎞
⎜1 +
⎟
4β ⋅ ∆Vout ⋅ Pmin ⎜⎝ T 2 ⎟⎠where, Pmin =

Vout
RL

(14)

2

Consequently, the minimum value of L is limited by theoutput pulse width D and the load condition. That is, theminimum reactor is increased according to the minimum
power Pmin in the specification.

5

36

40

44

48

52

56

60

Fig. 9. Calculation results of the Lower limit of resonant inductance.

C.

Design Example
Table 1 shows the specifications for the circuit. When thereference voltage mode, the proposed circuit converts 48 V
input to 12 V output. The input voltage 48 V is fluctuating ±25%. The optimization value at 220-kHz resonant frequency
is used. From the relations between the input and output
voltage, transformer turns ratio of the main circuit is
N11:N12=2:1. From the Vfluc, transformer turns ratio of theauxiliary circuit is N21:N22=2:1.
Fig. 9 shows the value of the minimum resonanceinductance is obtained by (14) using the specifications given
in Table 1. When Pout = 75 W, approximately 2.8 µH is
necessary for the resonance inductance. The inductance isinserted in series to the primary side of the transformer in themain circuit, because the leakage inductance of the maintransformer is insufficient. Moreover, C is determined by (3)to be 0.20 µF.
The maximum value of the resonance current Imax is thenobtained from (15), using the maximum power Pmax.
I max = 2

Pmax π⋅ = 13 A
Vin 2

14

96

Efficiency

94

12

92
90
88

(15)

86

I max
= 47V
ωC

11

Output voltage

10Output voltage : 12 V
Switching frequency : 205 kHz
0Therefore, the maximum value of the resonant capacitor
voltage Vc_max can be obtained from (16).
VC _ max =

13

50

100
150
Load [W]200

9Fig. 10. Load characteristics of the main circuit.

(16)

TABLE II
EXPERIMENTAL PARAMETERS

Vc_max is lower than the input voltage. Consequently, eachelement in the proposed circuit is selected according to thespecifications given in Table 1.
VI. EXPERIMENTAL RESULTAt first, experimental results of the main circuit arepresented in order to confirm the high efficiency can beachieved in the main circuit. Then, experimental results ofthe proposed circuit are presented at the second.

B.

Experimental results of the proposed circuit
Fig. 11 presents the efficiency of the proposed converter at
a constant load (cf., Table 1) when the input voltage has
fluctuation of ±25%. In order to confirm the validity of theconcept, the proposed converter was tested. The maximum
efficiency of 94.0% is obtained, as shown in Fig. 11, when
the input voltage is much closed to the nominal input voltage.
The reason for low efficiency in the boost mode compared tothe buck mode is that the current in the boost mode isincreased by the circulation current between the auxiliary
circuit and the rectifier. Consequently, the conduction loss isincreased by the circulating current.
Fig. 12 and Fig. 13 show the input current of the94

Pout = 60W

93

Efficiency [%]Experimental results of the main circuit
Fig. 10 shows the load characteristics of the main circuit(input voltage: 48V). The turn ratio of the transformer in themain circuit was 2:1. Therefore, the output voltage becomes
12V when the input voltage of the main circuit is 48V.
However, the control method is an open-loop control, that is,the duty cycle is set to 50%. As a result, the maximum
efficiency of 94.0% is obtained at load of 60 W, as shown in
Fig. 10. It is confirmed that the high efficiency is achieved in
the main circuit. It should be noted that the synchronousrectification using MOSFET is applied to the secondary sidein order to reduce the conduction losses of the rectifier.

95

A.

92
91

Pout = 100W
90
89
88
32

36

40

44
48
52
56
60
64
Input voltage [V]Fig. 11. Calculation results of the Lower limit of resonant inductance.

transformer and the terminal voltage of Sm2. In these modes,
reference mode, boost and buck mode accordingly, the halfbridge converter maintain at zero current switching. A
switching frequency of approximately 220 kHz was
confirmed.
Fig. 14 shows the loss analysis of the proposed converter
based on the simulated and experimental results. In order toclarify the power loss of the proposed circuit, the loss
measurement and analysis for each of the part have been
examined. When the input voltage is very close to thenominal input voltage, the maximum efficiency of the
proposed circuit is obtained. The auxiliary FET loss increases
in both boost and buck modes, and the loss in the maintransformer and main FET are predominant. Therefore, inorder to obtain higher efficiency, the selection of FETs in theauxiliary circuit is important. The low on-state resistancedevice should be chosen because the voltage rating of the
FET can be reduced in comparison with the main circuit.
Besides, the parameters design of the transformer based on
the equivalent circuit analysis are required.
VII.

REFERENCES

[2]
[3]

[4]
[5]

[6]

Trans.1
Input current

50[V/div]

0

5[A/div]

01[ s/div](a)

Reference mode (Vin = 49V).

CONCLUSIONSA series type isolated DC/DC converter consisting of aresonant-type half-bridge converter and an auxiliary
converter has been proposed. The concept for the series
compensation, which obtains the output voltage by adding or
subtracting the auxiliary converter voltage to the half-bridge
converter voltage, is proposed. The operation mode isanalyzed using a simple equivalent circuit of the proposed
circuit. Then, the stability of the operation for the proposed
circuit is clarified. In addition, design optimization in theresonant impedance was clarified by using a design
procedure flowchart.
The experimental results confirmed the maximum
efficiency of 94.0% is obtained when the input voltage wasclosed to the nominal input voltage. It was confirmed that thevoltage control can be regulated while maintaining highefficiency. From the loss analysis, the auxiliary FET loss
increases in both the boost and buck modes, and the loss inthe main transformer and main FET are predominant.
In future work, the circuit topology will be optimized toreduce the switch count in the auxiliary circuit.

[1]

Sm2
Voltage

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(b)

Boost mode (Vin = 40V).

(c) Buck mode (Vin = 56 V).
Fig. 12. Input current of the transformers and the terminal voltage of
Sm2 (Load: 60 W)
Sm2
VoltageTrans.1
Input current

50[V/div]

0

10[A/div]0

1[ s/div](a)
Sm2
Voltage

Reference mode (Vin = 50V).

50[V/div]

0

10[A/div]

Trans.1
0Input current

1[ s/div](b)
Sm2
VoltageTrans.1
Input current

Boost mode (Vin = 40V).

50[V/div]0010[A/div]
1[ s/div](c) Buck mode (Vin = 56 V).
Fig. 13. Input current of the transformers and the terminal voltage of
Sm2 (Load: 100 W)

P.Alou, J.Oliver, J.A.Cobos, O.Garcia, J.Uceda, "Buck+half bridge(d=50%) topology applied to very low voltage power converters",
APEC 2001, Sixteenth Annual IEEE Volume 2, pp 715-721, 2001.
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Reduced VA Ratings for Battery-Supercapacitor Mixed Systems",
IEEE PCC 2007, pp 936-941, 2007.
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Loss [W][7]

Fig. 14. Loss analysis at 60 W load.