Investigation of the Circuit Parameters Design ina Power Converter by using High-Frequency
Power Devices
Kenta Watanabe

Jun-ichi Itoh

Nagaoka University of Technology
Niigata, Japankwata@stn.nagaokaut.ac.jp

Nagaoka University of Technology
Niigata, Japan
itoh@vos.nagaokaut.ac.jp

Abstract-This paper discusses the problems which are thepower consumption of gate drive circuit and voltage oscillationof source-to-gate voltage in the power converters using highfrequency power devices. The circuit parameters design were
executed in terms of (i) power consumption of the gate drive
circuit at FET and (ii) voltage oscillation of source-to-gate
voltage at FET. As for (i), it is confirmed that the gate drive
circuit can reduce the power consumption of it from 250 mW to
10 mW. As for (ii), it formulated the relationship between thecircuit parameters and the voltage oscillation by circuit analysis.
However, a gap of voltage oscillation occurs for the calculation
results. The simulation was performed in order to presume thisgap of voltage oscillation factor. Then, it confirmed that gap of
the experimental results and the calculation results could be
reduced to about 2V.

I.

INTRODUCTION

Recently, packaging technology for power converters
features small size and high-density are highly demanding
and researching actively [1]-[2]. The size reduction in theheat sink, capacitors, reactors and also the improvement of
power density are essential elements to minimize the size ofthe power converter. However, power converters that use thesilicon MOSFET and silicon IGBT as the switching devices
are difficult to achieve miniaturization due to physicallimitation of the silicon device.
On the other hand, the performance of widegap
semiconductor such as silicon carbide (SiC) and gallium
nitride (GaN), are confirmed largely exceed the normal
silicon devices [3]-[4]. For example, SiC and GaN canperform fast-switching and low conduction loss under a hightemperature operation. However, when the SiC and the GaN
devices are applied to the normal gate drive circuit, the SiC
and GaN devices have two known problems;(i) Large power consumption at the gate driver.
When the GaN device uses the conventional drive circuit, alarge gate current flows into GaN devices, which haveJunction-FET (JFET) structure. This is because the gate of
JFET has no isolation layer. As a result, the gate drive power
will increase.
(ii) Source-to-gate voltage oscillation with the high-speed
switching.
Since the SiC and GaN has low gate threshold voltage incomparison with Si-IGBT and Si-MOSFET. The voltage

oscillation in gate signal is generating fault turn-on or turn-off
signal to the gate [5]. Although there are many papers discuss
about implementing SiC and GaN into a power converter, thepractical packaging method in terms of gate drive circuit has
not been reported.
This paper describes the design procedures for the GaNJFET in the basis of circuit parameters for a high frequency
converter. The circuit parameters were designed based on the
power consumption of the gate drive circuit and the switchingloss of GaN-JFET according to (i). For the problem of (ii),the significance of the voltage oscillation affecting the circuit
parameters were analyzed. Based on the analysis, thecalculation formula is derived. The validity of the derived
calculation formula was confirmed by the experimental
results. At the end, examination about the gap which occurs
for a calculation formula was performed.
II.

PARAMETER DESIGN THAT FOCUS ON POWERCONSUMPTION OF THE GATE DRIVE CIRCUIT

A. Gate Drive Circuit Configuration
Fig. 1 shows a configuration of the gate drive circuit for the
GaN-JFET. The buffer circuit of the gate drive circuit isclassified into two (a) the gate resistance RG1, (b) the gate
resistance RG2 connected with a series circuit of RS and CS(RC speed-up circuit). Table 1 shows the comparisons
between configurations (a) and (b) in term of gate drive
power consumption and switching time. In this section, thedrain-to-source voltage is 100 V, the drain current is 2 A. The
power consumption of the gate driver is classified into steadygate drive power PST and turn on or off gate drive power PTU.
Each of the power consumption is given by (1), (2)fsw :40kHz
D:0.5

VCC:+3.3V(a)(b)

RG1:3.3
CS:10nF

RS:3.3

Photo
coupler

IG G

RG2:1k330-VCC:-3.3V

100k

VGS
S

Fig. 1. Configurations (a) and (b) of the gate drive circuit.

respectively.
PST  VGS ( ST ) I G ( ST ) D .................................................. (1)2
PTU  f sw  QG  VGS (TU )  Ciss  VGS (TU )  .............. (2)where VGS(ST) is the source-to-gate voltage in the steadysection, IG(ST) is the gate current in the steady section. D is theduty ratio, fsw is the switching frequency, +VGS(TU) is thesource-to-gate voltage of the positive side in the switching
section, -VGS(TU) is the source-to-gate voltage of the negativeside in the switching section, QG is the quantity of the gatecharge electric from 0 V to +VGS(TU), and Ciss is the input
capacitance of GaN-JFET.
Moreover, total gate drive power is given by (3).
PTOTAL  PST  PTU ...................................................... (3)Table I. shows the measurement results of the power
consumption based on the experimental results of the gate
drive circuit with GaN-JFET. A step-down chopper is used toevaluate the gate power consumption. In Table 1, the gate
drive circuit configuration (b) obtains total gate drive power
lower than that of the circuit configuration (a), it is confirmed
PTOTAL of (b) is reduced by 97.9 % of that in (a). Therefore, as
for the circuit configuration (b), the value of RG2 isdetermined as 1 k. Furthermore, the switching speed isequal to that of the circuit configuration (a). As a result, thecircuit configuration (b) is more suitable to connect as thegate drive circuit for GaN-JFET.

TABLE I
POWER COMPARISON AND SWITCHING TIME BETWEENCONFIGURATIONS (A) AND (B) BY EXPERIMENTAL RESULTS

B. Parameter design of gate drive circuit
Fig. 2 - 4 shows the relationships between the drive circuit
Fig. 2. Relationship between the gate resistance and the power
parameters which is gate resistance RG2, time constant PST,
consumption. RG2 is a variable parameter.
(RS=3.0, CS=10nF: constant)
PTU and PLOSS(FET). The power consumption is demonstrated
by experimental results. Fig. 2 shows the relations between: Area of the PLOSS(FET) ≤ 440mW
the gate resistance and the power consumption. Fig. 3 and Fig.
1900
6.0
RG2=1k , CS=10nF: constant
4 show the relations between the time constant  of the speedup circuit and the power consumption. The switching loss of
Switching loss
4.5
1500
the GaN-JFET PLOSS(FET) and time constant of the speed-up
of GaN-FET PLOSS(FET)
circuit  are given by (4), (5) respectively.
Steady1
3.0
1100gate drive power PST
PLOSS ( FET )  VDS I D f sw tON  tOFF  ................... (4)6Turn ON/OFF  RS CS .................................................................... (5)gate drive power PTU
1.5
700
where tON is the turn-on time of GaN-JFET, tOFF is the440
turn-off time of GaN-JFET, VDS is the source-to-drain voltage
300
of GaN-JFET, and ID is the drain current of GaN-JFET.
450
900
1350
1800
0
50 100Time constant [ns]From these results, the gate drive circuit parameter is given
Fig. 3. Relationship between the time constant and the power
according to the specification of the gate drive circuit. For
consumption. RS is a variable parameter.
example, when the power consumption specifications of the(RG2=1k, CS=10nF: constant)gate drive circuit are given by following; (a) The total gate
III.
PARAMETER DESIGN THAT FOCUS ON VOLTAGE
drive power PTOTAL is less than 10 mW, (b) The switching
OSCILLATION OF SOURCE-TO-GATE VOLTAGE
loss of GaN-JFET PLOSS(FET) is about 400 mW. Table II.
shows the circuit parameters obtained from Fig. 2. It is noted
A. Behavior of the source-to-gate voltagethat the power supply voltage of the drive circuit is 3 V/ -3 V
Fig. 5 shows the configuration of the evaluated circuit. The
which is determined from the gate threshold voltage of a source-to-gate voltage of FET VGS is measured in this circuit.
GaN-JFET with safety margin.
In this paper, voltage oscillation of source-to-gate voltage
VGS is analyzed by using Si-MOSFET. Because it has the
fast-switching characteristics equal with GaN-FET. Table III.
shows a specifications of the Si-MOSFET.

Fig. 6 shows the voltage oscillation of VGS1 and VGS2. So forthe authors confirmed such a phenomenon is generated at ahigh-speed switching [6]. In this paper, the focus is applied toVGS2 of the lower arm when the upper arm is turned-on. Thisphenomenon depends on the parasitic parameters of thecircuit. Therefore, the false operation is caused by the GaNFET that has a low VGS(th).
B. Circuit analysis
Fig. 7 shows the equivalent circuit of a step-down circuit.
The calculation formula considers VGS2_peak is obtained fromthe equivalent circuit as shown in Fig.7(a). VGS2_peak is the
maximum value of VGS2. Firstly, the circuit equation issolved by Laplace transformation. The calculation result isgiven by (6).
VDC
1VGS 2 s  .................... (6)CGS As 3  Bs 2  Cs  D
where constant A - D is given by (7) - (10).
'
L C ' C  C C  CGS CGD
A  W GD DS ' DS GS.................. (7)CGD CGS

B: Area of the PLOSS(FET) ≤ 400mW
RG2=1k ，RS=8.0 : constant 1900

6.0

4.5

3.0

1.5

0

1500

Turn ON/OFF gate drive power PTU

1100

Steady gate drive power PST

700

Switching loss of GaN-FET PLOSS(FET)

1000

500
376

1500

2000

2500

400
300

80
Time constant [ns]Fig. 4. Relationship between the time constant and the power
consumption. CS is a variable parameter.
(RG2=1k，RS=8.0: constant)

TABLE IITHE CIRCUIT PARAMETERS DESIGN PROCEDURE'
LW CGD
 C DS'RG 2CGD CGS







'
'
RDS ON  RG 2 CGD
C DS  C DS CGS  CGS CGD



'
GD

RG 2 C CGS...................................................................................... (8)

C







'
'
RDS ON  CGD
 CDS  RG 2 CGD
 CGS
'
GD

RG 2C CGS

 ........... (9)1D...................................................... (10)'RG 2CGD
CGS
However, (6) is the third-order lag system. Therefore, theanalysis becomes complicated. Therefore, VGS2_peak is
obtained by an approximation, which is explained below.
Fig. 7(b) shows the simplification equivalent circuit of Fig.
7(a). In this circuit, it is supposed that RG2 is  . Therefore,
it becomes a simple RLC series circuit. The voltage of CGS isgiven by (11).

VGS' 2  VDC 1  e t cost   sint  ..... (11)where   

RDS ON 
2LW
'
GD

, 

Fig. 5. Experimental and simulation circuit composition.
TABLE III
SPECIFICATIONS OF SWITCHING DEVICES(2SK3928-01,FUJI ELECTRIC)

4LW CO   RDS2 ON 
2LW
'
GD

C
C CGS
 C DS, CO  '
'
 CGS
CGD
CGD  CGS

Fig. 8 shows the V’GS waveform derived from (11). It isnoted that VDC is a steady value. Therefore, it is necessary tosubtract VDC from V’GS2. The calculation formula which
subtracted VDC given by (12).

VGS' 2  VDC 1  e t cost   sint   VDC.................................................................................... (12)The maximum value V’GS2_peak is given by (13).

VGS' 2 _ peak  VDC
Tf  T    T 
 1  e 2 cos  f   sin  f   VDC
  2    2 
................................................................................... (13)where Tf is the resonance period of equivalent circuit. A
resonance period Tf is given by (14).

2.0

standard values
C'GD (100pF→50pF)
CDS (80pF→40pF)
CGS (1700pF→1200pF)
LW (400nH→200nH)
RDS(ON) (0.06 →0.6 )
VDC (140V→280V)

1.6
1.2
0.8
0.4
0
Fig. 6. The voltage oscillation of source-to-gate voltage.

(a) Before Simplification circuit.
(b) After Simplification circuit.
Fig. 7. Equivalent circuit composition.

Fig. 8 The V’GS waveform derived from a calculation formula.

T f  2 LW CO ......................................................... (14)Thus, V’GS2_peak is obtained from multiplying t of the (12)by 1/2 at the resonance period. In order to disclaim theinfluence of the approximation, in this paper, thecompensation coefficient k is applied. That is, therelationships between VGS2_peak of Fig. 7(a) and V’GS2_peak ofFig. 7(b) are given by (15).
VGS 2 _ peak  kVGS' 2 _ peak ........................................ (15)Fig. 9 shows the relationships between the compensation
coefficient k and the normalized coefficient of gate resistance
1/fCGSRG2. A resonance angular frequency f is a reciprocalof a Tf. Fig. 9 shows the compensation coefficient k
characteristics when the circuit parameters of the equivalentcircuit are varied from the standard values. From Fig. 9, it isconfirmed that correspond to the standard values (solid line)
even if the circuit parameters changes (graphical mark).
As a result, f is obtained from the circuit parameters from
Fig. 7(b). Then, k can be determined by select RG2. Therefore,
the design of VGS2_peak is possible to achieve by calculating
V’GS2_peak.

0

1.0

2.0
1/ f CGSRG2 [p.u.]

3.0

4.0

Fig. 9. Compensation coefficient calculation curve.

C. Experimental verification
The validity of (15) is confirmed experimentally. In theexperiment, the circuit parameters RG2, C’GD, LW werechanged. The experimental circuit is shown in Fig. 5. In thissection, VGS2_peak is calculated from (15) and VGS2_peak is
obtained from the experiment result, then these two results
are compared.
Fig. 10 shows the comparison of the experimental results
and the calculation results. The solid line is the calculated
results, the circle mark is the experimental results. In Fig.
10(a), (b) and (c), the experimental results and the calculation
results are not completely identical. However, all tendencies
to the voltage oscillation are approximately closed to eachpoint. The following section describes gap of theexperimental results and the calculation results for details.
D. Estimation of a gap
Fig.11 shows the experimental results when LW was changed.
The switching device which (1) used for the preceding
section (2sk3928-01, Fuji electric). The switching device inwhich the device model of a simulator exists in (2)(STW11NM80, STMicroelectronics). As a result, The LW VGS2_peak characteristics differ by each device. Therefore, thecalculation formula shown for the (13) cannot calculate exact
VGS2_peak. For this reason, it is necessary to clarify thecharacteristic which is not included in the simulation circuitof Fig. 5.
Fig.12 shows the simulation circuit to examine. This
simulation circuit has added the following characteristics tothe circuit of Fig.5.
1) Wiring inductance of a gate drive circuit LG1, LG2.
2) Lead inductance of switching devices Ll.
3) The recovery characteristics of switching devices.
Especially the recovery characteristics were not able to be
simulated in the conventional circuit of Fig. 5. Therefore, it isnecessary to add the recovery characteristics to an
improvement simulation circuit. Fig. 12 shows the circuit
which connected the current source Irec assumed recovery
current between freewheel diode of a lower arm. The current
wave form which extracted the recovery part of drain current
ID measured by the experiment is used for the current source
Irec. Then the experimental results and the simulation results
are compared.
Fig. 13 shows the comparison of the experimental results

10

12

10

C’GD=54pF，LW=400nH: constant

8

8

6

6

4

4

2

2

0

0

10

(b)STW11NM80(a)2sk3928-01

8
6

Experimental results4

Calculation results of Eq.(15)

2
0

0

0

4
4

16
12
8
Gate resistance RG2 [ ](a) RG2 is a variable parameter.
8

12

20

16

20

24
24

0

100

200
300
400
Wiring Inductance LW [nH]

500

600
F

ig. 11. The difference in the characteristics by switching devices.

8

6

4

2

0
0

20

40

60

80

Fig. 12. The simulation circuit in consideration of 1) to 3).

(b) C’GD is a variable parameter.
88

6

RG2=3 ，C’GD=54pF: constantExperimental results

6

4

4

2

2

Calculation results of Eq.(15)001000 1200
600
400
800
Wiring Inductance LW [nH](c) LW is a variable parameter.
Fig. 10. Experimental results and calculation results using a 2sk3928-01.
0
0

200
200

400

600

800

1000

1200

and the simulation results. The circle mark is theexperimental results, the square mark is the previous
simulation results using Fig. 5, and the triangle mark is the
improvement simulation results using Fig. 13. From Fig. 13,
it can confirm that gap of the improvement simulation results
and the experimental results are a maximum 2 V. Moreover,accuracy of simulation results using Fig. 13 is improvingfrom the simulation results using Fig. 5. The following can beconsidered as other gap factors.
(a) Disagreement of the device model characteristics of asimulator and the device characteristics used with theexperiment(b) Wiring inductance is not simulated in detail.
E. Control of a voltage oscillation
Fig.14 shows the drain current ID waveform at the time ofthe voltage oscillation generating. From Fig. 14, the voltage
oscillation has occurred to two timing. (i) is considered that

oscillation by the di/dt characteristics of recovery current and(ii) is oscillation by the dv/dt characteristics of the source-todrain voltage. This section focuses on (i) in voltage
oscillation.
The recovery characteristics of a switching device are variedby parasitic capacitance of FET CGS1 and gate resistance RG1.
In order to show the relation of the parasitic capacitance of
FET CGS1 and gate resistance RG1, the calculation formula of atime constant is given by (16).
  CGS1 RG1 ................................................................ (16)This time constant  is decided by the ratio of RG1 to CGS1. In
this paper, this RG1 and CGS1 investigate the influence which
exerts to the voltage oscillation. At this time, a time constant assumes that it is a steady value. Table IV shows theparameters ratio and time constant .
Fig. 15 shows the experimental results. In this paper, it
experimented in time constant  as about 20 ns. As a result, it
was confirmed that the VGS2_peak becomes small value whengate resistance RG1 is small value. Moreover, di/dt ismaintaining the steady value mostly and the recovery
characteristics were confirmed not changing. From the above
result, VGS2_peak can be controlled when RG1 is a low value.
IV.

CONCLUSION

This paper discussed the design of the circuit parameters
for a power converter circuit that employs high frequency
power devices. The results are shown as follows; (i) the gate
drive circuit can achieve a power consumption less than 10
mW, FET switching loss is approximately 400 mW by theapplying the designed parameter. (ii) The calculation formula
concerning the voltage oscillation in the gate waveform wasDrain current ID [A]Source-to-gate Voltage VGS2 [V]Fig. 14. A drain current ID waveform and a source-to-gate voltage VGS2
waveform.

(a) RG2 is a variable parameter.

TABLE IV
EXPERIMENTAL PARAMETERS AND A TIME CONSTANT

Additionnal
Time constantcapacitance[ns]
CGSadd[pF]
1.1
16900
20.4
2.7
6000
20.5
19.3
3.0
4820
5.6
1720
18.6
6.9
1180
19.2
495
19.1
9.1
12.0
0
19.2
CGS1:1600pF (VDS=140V,STW11NM80)
Gate resistance
RG1(b) C’GD is a variable parameter.
12

RG2=3 ,LW=250nH,LG2=50nH: constant

10
8

Experimental
Improvement simulation
6of Fig.12

900

5

5

750

4

4

600

3

450

450
300

300

dID/dt

VGS2_peak1(approximately-constant)

1

0

0

0

100

200

300

400

500

600

established by the circuit analysis. As a result, thecorrespondence of the predisposition to VGS2_peak by thecircuit parameters was confirmed. Moreover, the gap factor
was presumed.
In future work, the calculation formula that will consider
the gap of the results will be designed. Moreover, the voltage
oscillation control circuit will propose.

[3]

[4]

[5]

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14

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2

Wiring Inductance LW [nH]

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[6]

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