Power Decoupling Method for Isolated DC toSingle-phase AC Converter using Matrix Converter
Hiroki Takahashi, Nagisa Takaoka, Raul Roberto Rodriguez Gutierrez and Jun-ichi Itoh
Dept. of Electrical Engineering
Nagaoka University of Technology
Nagaoka, Niigata, Japan
thiroki@stn.nagaokaut.ac.jp, ntakaoka@stn.nagaokaut.ac.jp, s139063@stn.nagaokaut.ac.jp, itoh@vos.nagaokaut.ac.jp
Abstract—This paper presents an isolated DC to single-phase
AC converter using a matrix converter for HVDC (higher voltage
direct current) power feeding system. The proposed converter
comprises a full bridge inverter, a high frequency transformer
and a matrix converter and does not use a bulky electrolytic
capacitor. Then, in order to reduce a ripple component in a DC
bus current caused by the single-phase load, this paper also
proposes a power decoupling method. The power decoupling
method employs a center-tapped transformer and a small LC
buffer instead of additional switches, which aims to achieve highefficiency. Moreover, modulation methods of the full bridge
inverter and the matrix converter, and a control strategy of thepower decoupling are described. As an experimental result, thepower decoupling method reduces the DC bus current ripple to
2/3. In addition, a validity of a parameter design method of the
proposed control is confirmed in simulations.
Keywords—matrix converter; power decoupling; power ripple;

I.

INTRODUCTION

Recently, power consumption of ICT (information andcommunication technology) equipment in a building and afactory has been increasing drastically. As a solution for powersaving of a building, a HVDC (higher voltage direct current)
power feeding system has been developed [1]. The HVDC
power feeding system has a DC bus of 380 V in order to aim at
high efficiency and low cost because of reducing converters
and cables, compared to a conventional AC or a DC 48 V
power feeding. Then, if an existing power feeding system isreplaced with the HVDC one, a DC-AC converter to connect
the DC bus and existing single-phase AC equipment is required.
In addition, the DC-AC converter needs isolation between the
DC bus and the AC equipment for safety. Therefore, anisolated DC to single-phase AC converter is required.
The isolated DC-AC converter requires downsizing andhigh efficiency. Then, a conventional converter consists of afull bridge inverter as a primary converter, a high frequency
transformer and a secondary converter composed of a dioderectifier and an inverter. [2]. However, the secondary converter
uses a balky electrolytic capacitor to smooth DC-link voltage
and restricts downsizing and high efficiency.
On the other hand, a matrix converter has attracted a lot of
attentions because a matrix converter has no DC energy buffer[3-4]. A matrix converter promises to achieve higher efficiency,

smaller size and longer life-time compared to a conventional
rectifier-inverter system. Therefore, a matrix converter issuitable for a secondary converter of the isolated DC to singlephase AC converter.
However, a matrix converter cannot absorb power ripple
which is generated by a single-phase load because of no energy
buffer in its topology. As a result, DC bus current includes aripple component at twice of the AC load frequency which
affects a battery connected in DC bus for back-up andelectrolytic capacitors in other converters adversely. Thus, apower decoupling capability using small passive components isrequired to the isolated DC to single-phase AC converter toremove the ripple component.
In past works, some circuit topologies with a power
decoupling capability have been proposed [5-6]. However,these papers employ not only small passive components but
also more switching devices for the power decoupling. In orderto overcome this problem, a power decoupling method using acenter-tapped transformer and a small LC buffer has beenpresented [7]. This method does not use additional switches
and suppresses the ripple component in the input current
significantly. However, [7] deals with an isolated DC to singlephase AC converter using a diode rectifier and a PWM inverter,
not a matrix converter. In addition, a parameter design methodof its control block diagram has not been revealed.
This paper proposes an isolated DC to single-phase AC
converter using a matrix converter in order to improve theefficiency and size reduction. The proposed system consists ofa full bridge inverter, a center-tapped transformer, a small LC
buffer and a matrix converter. The proposed converter does not
require extra switching devices for the power decoupling,
owing to the center-tapped transformer. In contrast, the matrix
converter is applied a PDM (pulse density modulation) which
is appropriate to convert a high frequency voltage to asinusoidal voltage at 50 Hz. Moreover, in order to yield an
intended control performance, this paper clarifies a parameter
design method of the power decoupling control and an output
current control.
This paper is organized as follows; firstly, a circuit
configuration of the proposed DC-AC converter and a principleof the power decoupling are described; secondly, modulation
methods and a control block diagram with the design method
are reported; finally, fundamental operation waveforms andtransient responses of the proposed system are evaluated insimulations and experiments.

Ibus
Ldc

II.

CIRCUIT TOPOLOGY

Fig. 1 shows a conventional isolated DC to single-phase
AC converter. The conventional circuit comprises a full bridge
inverter, a high frequency transformer and a rectifier-inverter
system. The full bridge inverter outputs a square voltage at ahigh frequency in order to reduce volume of the transformer.
The secondary rectifier converts the high frequency voltage toa DC voltage and the PWM inverter controls an output filter
capacitor voltage with a feedback control. When the load
current is sinusoidal waveform and achieves the unity power
factor, an instantaneous output power pout is expressed by (1).

pout  2Vload sino t   2 I load sino t  Vload I load 1  cos2o t   Pave 1  cos2o t Fig. 2 shows the isolated DC to single-phase AC converter
using a matrix converter and a small LC buffer which is
proposed in this paper. The matrix converter is employed as asecondary converter in order to eliminate the DC-link capacitor
which is used in Fig. 1. In addition, a center-tapped transformer
links the full bridge inverter to the matrix converter for
isolation and the power decoupling which results in reducing
the DC bus current ripple. A buffer circuit including a buffer
capacitor Cbuf and a buffer inductor Lbuf is used to absorb thepower ripple. It should be noted that a charge and a discharge
to compensate the power ripple is implemented at Cbuf.
Fig. 3 shows a principle of the power decoupling with Cbuf.
In order to yield a DC bus current without the ripple, a
relationship among the output power pout, a DC bus power pbus
and a charged power pbuf is defined as (2) to (4).
pout  pbus  pbuf 

Lout

Vbus

Cdc

Full bridge Inverter

PWM inverter

Fig. 1. A conventional isolated DC to single-phase AC converter. The
conventional converter uses a balky electrolytic capacitor Cdc to absorb thepower ripple caused by a single-phase load.

Fig. 2. The proposed isolated DC to single-phase AC converter. The
secondary converter is replaced with a matrix converter in order to eliminatea DC-link smoothing capacitor. In addition, a center-tapped transformer anda small LC buffer are employed to achieve a power decoupling without
additional switching devices.
Vbus

vCbuf
VCmax
VCmin
t

0



pbuf  Pave cos2 o t  



o

t

t

0

iload
iload

t

0

2Vload sin

2 I load sin

o

t

0

t

discharge
pbuf

pbus

pout

chargedischarget

Input powerpbus [W]where, a polarity of pbuf is defined as positive when Cbuf ischarged. It should be noted that the used capacitor is smaller
than one in the conventional converter because the power
ripple is compensated by varying a buffer capacitor voltage
vCbuf not a large capacitance. On the other hand, an inductor in
the buffer circuit is used for a current control for the power
decoupling, which is equivalent to control of pbuf. The buffer

t

0



pbus  Pout 

vloadcharge
t

0

vload

ibuf

Ibus

0



Diode rectifier

vload

Cout Rload

vout



where, Vload is the load voltage (RMS), Iload is the load current(RMS), Pave is an output average power and o is the output
angular frequency. A ripple component shown in the second
term of (1) should be bypassed in order to obtain a constant DC
current of the DC bus. Hence, this system has to adopt a balky
electrolytic capacitor Cdc to absorb the power ripple.

iout iload

N1 N2

t

0

Buffer powerpbuf [W]0tOutput power
pout [W]Fig. 3. A principle of the power decoupling with the buffer capacitor. A
buffer power to compensate the power ripple is charged or discharged at
Cbuf. As a result, a DC bus current without the ripple component is obtained.

current control is carried out by the full bridge inverter. The
full bridge inverter outputs a differential mode voltage to excite
the transformer and a common mode voltage to compensate thepower ripple with the LC buffer independently, owing to thecenter-tapped transformer. Therefore, the proposed converter
does not require additional switching devices for the powerdecoupling and number of devices of the proposed converter isthe same as one of the conventional circuit.
III.

MODULATION METHOD

A. Full Bridge Inverter
Fig. 4 shows a modulation method of the full bridge
inverter. As mentioned above, the full bridge inverter outputs a
differential mode voltage vdif to excite the transformer and acommon mode voltage vcom to compensate the power ripple atthe same time. Therefore, a differential mode voltage reference
vdif* and a common mode voltage reference vcom* are set as
input parameters in Fig. 4. It should be noted that a gain of 0.5
is inserted to a path of vdif* only because a reference potential of
vdif* is different from one of vcom*. In order to obtain the
maximum secondary voltage of the transformer, vdif* is set to 1
p.u.. On the other hand, vcom* is calculated by a PI controller inthe buffer current control to compensate the power ripple asmentioned in chapter IV.
Fig. 5 shows operation modes of the full bridge inverter. A
hatched gray line indicates a turned off switch and a black solidline shows a current pathway. Fig. 5 (a) and (b) illustrate thedifferential mode to transfer the DC bus power. In this mode,
the transformer is excited. In addition, a buffer circuit voltage,
which is equivalent to vcom, is constant of Vbus/2. On the other
hand, Fig. 5 (c) and (d) show the common mode to control thebuffer current ibuf in order to compensate the power ripple. In
the common mode, the transformer is not excited because vdif
becomes zero. As a result, the full bridge inverter controls vdif
and vcom independently because the differential mode changes
vdif only and the common mode changes vcom only. This
independence achieves that the proposed converter does notneed additional switches for the power decoupling.
B. Matrix Converter
Fig. 6 shows a concept of a PDM method of the matrix
converter used as a secondary converter in the proposed system.
The PDM is appropriate for a direct AC-AC converter which
provides a sinusoidal voltage at a commercial frequency from ahigh frequency voltage, such as the proposed system. The
PDM treats an input voltage waveform at high frequency as apulse and synthesize an output voltage with a density of the
input voltage pulses. In Fig. 6, a half cycle of the input voltage
pulses are used as the minimum unit of the output voltage
waveform. Then, the matrix converter switches turn in zerovoltage period of the input voltage waveform inevitably. In
consequence, the matrix converter achieves a ZVS (zerovoltage switching) which results in decreasing a switching loss.
Thus, the PDM is applied to the matrix converter in this paper.
Fig. 7 shows a block diagram of the PDM. The block
diagram is composed of a  modulator, a switching phaseselector and a synchronization with a clock (CLK). Owing to
the switching phase selector, a full wave rectified signal of an
output voltage reference vout* is used for the PDM. The 
modulator generates a gate pulse such as an analog-digitalconversion. In addition, CLK to synchronize the gate pulse
with the zero voltage period is obtained by the common modeof the full bridge inverter and a phase shifter easily.

(a) Block diagram(b) Definition of vdif and vcom
Fig. 4. A modulation method of the full bridge inverter. A differential
mode voltage reference vdif* is for exciting the transformer and a common
mode voltage reference vcom* is used to compensate the power ripple with the
LC buffer.

(a) Differential mode 1.

(b) Differential mode 2.

(c) Common mode 1.

(d) Common mode 2.

Fig. 5. Operation modes of the full bridge inverter.

IV.

CONTROL STRATEGY AND PARAMETER DESIGN

Fig. 8 shows a control block diagram of the proposed
converter. The block diagram is composed of a buffer current
control, a voltage control of an output filter capacitor, a current
control of an output filter inductor and a compensation of asecondary voltage fluctuation of the transformer. These current
and voltage controls are implemented by PI controllers. The
buffer current control is for the power decoupling. The filter
current and voltage control are to provide a stable load voltage.
In addition, the compensation of the secondary voltage
fluctuation of the transformer is needed in order to eliminate a
disturbance of the filter current control caused by an input
voltage fluctuation of the matrix converter depending on thecommon mode voltage reference vcom*. A design method ofthese controls is described from the next section. It should be
noted that the filter voltage control is not described because thevoltage control is not a technical issue in this paper and can beselected in the previous studies.
A. Calculation of Buffer Current Reference ibuf*
In order to absorb the power ripple caused by the singlephase load, a buffer current reference ibuf* should be calculated
from pout* and a chargeable energy of Cbuf. First of all, thebuffer capacitor energy WCbuf is presented by (5).



dvCbuf tt d 
WCbuf   vCbuf ibuf d   vCbuf  Cbuf
t0
t0
d 






*

ibuf  C buf

dv Cbufdt

Pave cos 2 0 t 

*

*



2

*





Vbus
P
 ave sin 2 o t 4 o C buf

It should be noted that Pave* is calculated by a load resistance.
Therefore, the power ripple is compensated by using the buffer
current control with the current reference ibuf* as shown (9).
B. Buffer Current Control
Fig. 9 shows a block diagram to design the PI controller forthe buffer current control and a filter Fbuf (s) for a pole-zerocancelation. A plant model is the LC buffer circuit. In addition,
Kp_buf is a proportional gain and Ti_buf is an integral time of thebuffer PI controller. Then, a closed loop transfer function ofwhere, ibuf is a buffer current and t0 is a start time of operation.
In contrast, WCbuf is also expressed by using pbuf.
WCbuf   pbuf d   Pave cos2o d 
t

t

t0

t0



By using (5) and (6), vCbuf is calculated as following.

P
vCbuf  VC 0  ave sin 2 o t   sin 2 o t 0   o Cbuf2

Fig. 6. A concept of a PDM method of the matrix converter. The PDM
treats a half cycle of an input voltage waveform as a pulse and synthesize an
output voltage with a density of the input voltage pulses.

where, VC0 is an initial voltage of Cbuf and VC0 is Vbus/2. If t0 iszero, (7) is rewritten as (8).



2



vCbuf VbusP
 ave sin 2o t  4o CbufFinally, ibuf* is derived by using an output power reference Pave*.
Fig. 7. A block diagram of the PDM. The PDM is based on  modulator.

1
Vbus

Fig. 8. A control block diagram of the proposed converter. A buffer current control is for the power decoupling. A voltage control of an output filter capacitor
and a current control of an output filter inductor is to provide stable load voltage. A compensation of the secondary voltage fluctuation of the transformer isrequired for an intended control performance.

Fig. 9 except Fbuf (s) is expressed by (10).

ibuf_LPF*
ibuf

K p _ buf
1

Lbuf Cbuf Lbuf Ti _ buf
1  sTi _ buf
*Ti _ buf

ibuf _ LPF
K
K
1
p
_
buf
p
_
buf
1


s2 
s
 Lbuf Cbuf Lbuf Ti _ buf K p _ buf Cbuf
Lbuf



*

Fbuf (s)Kp_buf
Ti _ buf 
1
1 

Fbuf ( s ) 
1  sTi _ buf  K p _ buf Cbuf 





ibuf
ibuf

*

K p _ buf
1

Lbuf Cbuf Lbuf Ti _ buf


s 
2

K p _ buf
Lbuf

K p _ buf 
1

s

 Lbuf Cbuf Lbuf Ti _ buf 





1
s
Lbuf
1
s2 
Lbuf Cbuf

ibuf

LC buffer circuit
Fig. 9. A block diagram to design the PI controller for the buffer current
control and a filter Fbuf (s) for a pole-zero cancelation. By using this model,
an intended control response of the power decoupling is obtained.
iout_LPF*
iout*





sTi_buf

PI controller

ibuf

In order to transform (10) into a standard form of a second
order transfer function, Fbuf (s) is defined as (11) and a closed
loop transfer function including Fbuf (s) is presented by (12).

*1+sTi_buf vbuf

Fout (s)Kp_out*1+sTi_out vLout

sTi_out

PI controller

1
sLout

iout

Filterinductor

Fig. 10. A block diagram to design the PI contoller for the current control ofan output filter inductor and a filter Fout(s) for a pole-zero cancelation.

Then, Kp_buf and Ti_buf are calculated by using an intended
natural angular frequency n_buf and a damping factor buf of astandard form of a second order transfer function.
K p _ buf  2 buf  n _ buf Lbuf 





2 buf  n _ bufTi _ buf 1
 n _ buf 2 
Lbuf Cbuf

Hence, the power decoupling with an intended control
performance is achieved by (13) and (14).
C. Current Control of Output Filter Inductor
Fig. 10 shows a block diagram to design the PI controller
for the current control of the output filter inductor and a filter
Fout (s) for a pole-zero cancelation. A plant model is a filter
inductor. In addition, Kp_out is a proportional gain and Ti_ out isan integral time of the filter current PI controller. Then, if Fout(s) is defined as (15), a closed loop transfer function of Fig. 10
is presented by (16).
Fout (s) 11  sTi _ outK p _ out



iout

*
iout

LoutTi _ out
K
K p _ out
p
_
out
2
s 
s
Lout
LoutTi _ outFig. 11. A relationship between the common mode voltage reference vcom*
and the full wave rectified waveform of the secondary voltage. In order tocompensate the secondary voltage fluctuation, vout* is divided by vs_rec.

Therefore, Kp_out and Ti_out are designed by using an intended
natural angular frequency n_out and a damping factor out in thesame way with the buffer current control as (17) and (18).


K p _ out  2 out  n _ out Lout 

Ti _ out 2 out  n _ out





D. Compensation of Secondary Voltage Fluctuation
In order to obtain an intended response of the filter current
control regardless of a secondary voltage of the transformer, acompensation of a secondary voltage fluctuation of thetransformer is needed. Then, the secondary voltage depends onVbus, vcom* and a turn ratio of the transformer N2/N1. By the way,
the PDM deals with a half cycle of the secondary voltage
pulses as the minimum unit, regardless of a polarity of thesecondary voltage. Thus, the compensation is considered with afull wave rectified waveform of the secondary voltage vs_rec.
Fig. 11 shows a relationship between the common mode
voltage reference vcom* and vs_rec in a simulation. This
simulation is carried out with Fig. 4 (a) only. Therefore, thebuffer current control is not applied and the matrix converter is
not connected. These waveforms are normalized with the DCbus voltage Vbus. The turn ratio of the transformer is 1:1. From
Fig. 11, vs_rec is synchronized with vcom* and is presented as (19).


vs _ rec 





N2
*
Vbus 1  2  vcom N1

TABLE I.

SIMULATION CONDITION.

Therefore, in order to compensate the secondary voltage
fluctuation, vout* is divided by vs_rec as shown in (19).
V.

SIMULATION AND EXPERIMENTAL RESULTS

A. Simulation Results in Steady State
Table 1 shows a simulation condition to verify afundamental operation of the proposed converter. It should be
noted that the filter capacitor and the load resistance is replacedwith a voltage source of 100 Vrms, 50 Hz for simplicity. Thus,
the voltage control of the output filter capacitor is not used.
Fig. 12 shows the input and the output waveforms in a
steady state. Fig. 12 (a) shows a result without the power
decoupling method and (b) shows a result with the method. A
DC bus current is filtered with a LPF with a cut-off frequencyof 1 kHz in order to remove a switching ripple. From Fig. 12(a), the DC bus current has a ripple component at 100 Hz
caused by the single-phase load. Then, the ripple component at
100 Hz is 103% with reference to an average current in (a). In
contrast, the ripple component is reduced in (b), owing to thepower decoupling method. As a result, the ripple of the DC bus
current is suppressed by 92.5%. In addition, a filter inductor
current THD (total harmonic distortion) is less than 1%.

(a) Without the power decoupling method.

B. Evaluation of Control Performance
In order to verify the proposed design method of the control
parameters described in chapter IV, transient responses of thebuffer current control and the filter current control areevaluated in this section. It should be noted that thesesimulations are implemented with a DC model in order toevaluate the controls with an overshoot and an overshoot time.
Fig. 13 shows an indicial response of the buffer current
control. From Fig. 13, the actual buffer current ibuf follows thereference ibuf* right after a step input. In addition, the actual
current conforms to an ideal response of ibuf based on Fig. 9.
Then, a percentage overshoot of the ideal response is 4.60%
and an overshoot time of the ideal response is 0.737 ms. These
results correspond to their designed values based on the naturalangular frequency and the damping factor in Table I. It should
be noted that the designed percentage overshoot PO and theovershoot time To are calculated by following equations.








 buf 
PO  100[%]  exp 
1   buf 2 



To 


n _ buf 1   buf 2(b) With the power decoupling method.
Fig. 12. Input and output waveforms in a steady state. The proposed power
decoupling method reduces the DC bus current ripple by 92.5%.

Fig. 13. An indicial response of the buffer current control. The overhoot andthe overshoot time correspond to the designed values.





Fig. 14. An indicial response of the filter current control. The overhoot andthe overshoot time correspond to the designed values.

Fig. 14 shows an indicial response of the filter current
control. From Fig. 14, the actual filter current iout follows thereference iout* right after a step input. In addition, the actual
current conforms to an ideal response of iout based on Fig. 10.
Then, a percentage overshoot of the ideal response is 4.60%
and an overshoot time of the ideal response is 1.46 ms. These
results correspond to their designed results calculated in thesame manner with (20) and (21). Therefore, the proposed
design method achieves an intended control performance.
C. Experimental Results in Steady StateAn experimental setup is demonstrated to validate theproposed system,. It should be noted that a buffer capacitor of
250 F, a buffer inductor of 2 mH, a load inductor of 2 mH anda transformer of the turn ratio of 1/2 are used, and a LC filter isinserted in the DC bus side. Moreover, the PDM method basedon the  modulation in Fig. 7 is replaced with a PDM
discussed in [8] because of an experimental limitation. In
addition, the control parameters are adjusted for the experiment.
Fig. 15 shows experimental waveforms of the proposed
converter with Vbus of 350 V, vout of 80.8 Vrms and an R-L loadof 594 W. Fig. 16 (a) shows a result without the power
decoupling method and (b) shows a result with the method.
From (a), the buffer capacitor voltage does not vary because
the full bridge inverter does not output the common mode AC
voltage. As a result, the DC bus current has a power ripple
component at 100 Hz. In contrast, the proposed power
decoupling method provides the common mode AC voltage tofluctuate the buffer capacitor voltage. In consequence, thepower ripple component in the DC bus current is decreased.
Then, the output voltage THD in (b) is 5.9% because of aresolution problem of the used PDM method.
Fig. 16 shows a harmonic analysis of the DC bus current. It
should be noted that the harmonic number is based on the
output frequency at 50 Hz. From the result without the power
decoupling method, the power ripple component at 100 Hz is
65.5% with reference to an average current. In contrast, theproposed method reduces the 100-Hz component to 43.3%
because the buffer capacitor voltage fluctuation absorbs thepower ripple at 100 Hz. As a result, the proposed method
reduces the power ripple to 2/3. The DC bus current distortion
will be reduced more by improving the output voltage quality
with the PDM method based on the  modulation and thebuffer current control performance.

(a) Without the power decoupling method.

(b) With the power decoupling method.
Fig. 15. Experimental waveforms in a steady state.

Fig. 16. Harmonic analysis of the DC bus current. The proposed power
decoupling method reduces a 100-Hz ripple in the DC bus current to 2/3.

REFERENCES
[1]

[2]

[3]

VI.

CONCLUSION

This paper presents an isolated DC to single-phase AC
converter using a matrix converter. The proposed converter
eliminates a bulky electrolytic capacitor because a matrix
converter is employed as a secondary converter. This paper
also describes the power decoupling method to reduce a ripple
component in a DC bus current caused by a single-phase load.
In addition, design equations of the power decoupling control
and an output current control are proposed. As a simulation
result, the proposed power decoupling reduces the DC bus
current ripple by 92.5%. In addition, an experimental result
verifies the proposed power decoupling method reduces the
100-Hz component caused by the power ripple to 2/3.

[4]

[5]
[6]
[7]

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