Reduction of DC-link Current Harmonics over
Wide Power-Factor Range for Three-Phase VSI
using Single-Carrier-Comparison Continuous PWM
Koroku Nishizawa
Nagaoka University of Technology
Nagaoka, Niigata, Japan
koroku_nishizawa@stn.nagaokaut.ac.jp

Jun-ichi Itoh
Nagaoka University of Technology
Nagaoka, Niigata, Japan
itoh@vos.nagaokaut.ac.jp

Satoru Fujita
Fuji Electric Co., Ltd.
Tokyo, Japanfujita-satoru@fujielectric.com

Akihiro Odaka
Fuji Electric Co., Ltd.
Tokyo, Japanodaka-akihiro@fujielectric.com

Akio Toba
Fuji Electric Co., Ltd.
Tokyo, Japan
toba-akio@fujielectric.com

Hidetoshi Umida
Fuji Electric Co., Ltd.
Tokyo, Japanumida-hidetoshi@fujielectric.com

Abstract—This paper proposes a novel continuous PWM(CPWM) method to reduce DC-link current harmonics involtage source inverters (VSIs) over wide range of load power
factor. This modulation method contributes to a lifetime
extension of smoothing capacitors in motor drive systems.
Furthermore, a high cost digital hardware such as a fieldprogrammable gate array (FPGA) is not necessary because thismodulation is implemented with only one carrier. The DC-linkcurrent harmonics are reduced by shifting voltage references inevery half control period to reduce a fluctuation of the DC-linkcurrent around its average value. Experimental results confirm
that the application of the proposed CPWM reduces the DC-linkcurrent harmonics by 24.2% at most.

used for comparison. Thus, this DPWM can be implemented
only with the general-purpose micro-computer. However, theDPWM strategy faces many challenging disadvantages
compared to continuous PWM (CPWM); in particular, certain
switch is clamped to on-state at all times. Therefore, load
current continuously flows through the clamped switch and it
leads to overheat in the switch depending on the conditions ofmodulation index and fundamental frequency. Furthermore,
the number of switching per control period in the DPWM isless than that in the CPWM. This leads to an increase of the
AC motor noises due to a high inverter output voltage
harmonics. For the above reasons, the applications of the
DPWM are limited.

Keywords—Motor drive system, DC-link capacitor, Inverter
DC-link current harmonics, Continuous PWM

This paper proposes a novel carrier-comparison CPWM
which uses only one carrier to reduce the DC-link current
harmonics. This modulation method contributes the lifetime
extension of the smoothing capacitor in the motor drive
system and can be implemented only with the general-purpose
micro-computer. Three phase continuous voltage references
are shifted in every half control period to reduce thefluctuation of the DC-link current around its average value.
By optimizing the shifting manner of the voltage references,
it is possible to reduce the DC-link current harmonics overentire region of the load power factor. One more contributionof this CPWM is to overcome the problems of the DPWM,
such as heat concentration to specific switch and high inverter
output voltage harmonics.

I. INTRODUCTION
Three-phase AC motors are widely used in both industrial
and household applications [1-5]. A lifetime extension of the
AC motor drive systems has been actively researched for a
decade [6-11]. In general, electrolytic capacitors are employed
as smoothing capacitors in a DC-link part of a PWM inverter
due to their superior capacitance per volume ratio comparedto film capacitors or ceramic capacitors. However, the AC
motor drive system becomes less reliable due to the short
lifetime expectancy of electrolytic capacitors. It is possible toextend the lifetime of the smoothing capacitors by reducing
the dc-link current harmonics of voltage source inverters(VSIs).
So far, several modulation methods of VSI which reduce
the DC-link current harmonics have been proposed [7-11].
With a space vector PWM (SVPWM) in [10], voltage space
vectors are selected in order that the zero vector period isshortened to minimize the DC-link current harmonics.
Furthermore, this SVPWM adapts to the variation of the load
power factor by changing the voltage space vectors according
to polarities of inverter output phase currents. However, theemployment of the SVPWM leads to a constraint of digital
hardware, i.e. the requirement of high cost hardware such as
field-programmable gate array (FPGA).
As another approach to reduce the DC-link current
harmonics, a new single-carrier-comparison discontinuous
PWM (DPWM) has been proposed in [11]. In this DPWM,
voltage references of the classic DPWM are shifted at both thepositive-peak and negative-peak of a triangular carrier toreduce the DC-link current harmonics, and only one carrier is

II. INVERTER DC-LINK CURRENT HARMONICS WITHCONVENTIONAL CONTINUOUS PWM
Fig. 1 shows the voltage references of CPWM and output
phase currents at a modulation index of 0.7 and a load power
factor of 0.707. Three phase voltage references v*x.CPWM of theconventional CPWM are sine waves and expressed as [12]: vu*.CPWM  m  cos  2 ft  *
 vv.CPWM  m  cos  2 ft  2 3 v *
 w.CPWM  m  cos  2 ft  2 3

where m is the modulation index, f is the fundamental
frequency.
Fig. 2 shows zoomed-in waveforms of v*x.CPWM, switching
functions and an ideal DC-link current at the modulation index
of 0.7, a phase angle of 25 degrees and the load power factor

I*
vu.CPWMx u ,v ,w

Voltage references[p.u.]

1
1.0

0.5
0.5

The shaded area of the DC-link current waveform in
Fig. 2 indicates the instantaneous root-mean-square (rms)value of the current flowing into the smoothing capacitor,
which is calculated as:

Output phasecurrents [p.u.]of 0.707. The DC-link current is the superposition summationof the switched current pulses from each leg and calculated as:

iDC .in    sx  ix . 





III

IV

V

*
vv.CPWM

VI*
vw.CPWM

m

0
0.0

-0.5
-0.5
-1
-1.0
-0.002F0 0.002
0.004
0.006
0.0080.01C
0.012
0.014
0.016
0.018
A
B
D
E0.020.022
F
1.2
1.2
0.8
0.8
iu
iv
iw
0.4
0.4
0
0.0
-0.4
-0.4
-0.8
-0.8
-1.2
-1.2
-30 0
0 0.002
30 0.004
60 0.006
90 0.008
120 0.01
150 0.012
180 0.014
210 0.016
240 0.018
270 0.02
300 0.022
330-0.0022πft [deg.]2
2
iC .rms Ts   iDC.in .rms  Ts   iDC .in _ ave
1 Ts 2iDC .in dt iDC .in.rms Ts  

Ts 0
and 
3

iDC .in _ ave  4 m  I m cos 

II



Fig. 1.
Continuous voltage references and output phase currents at
m = 0.7, cos φ = 0.707. The sectors I-VI and A-F are determined by thepolarities of three-phase voltage references and output phase currents,
respectively.
1

Triangular carrierv *u.CPWMv *v.CPWM

where Ts is the control period, Im is the maximum value of theoutput phase current and φ is the load power factor angle. Notethat a smaller fluctuation of the DC-link current around its
average value results in a smaller rms value of the smoothing
capacitor current [13]. In the case of conventional CPWM, thecenter of the gate pulses are the same as the center of thecontrol period, which results in the longest overlap period of
the gate pulses. This leads to the large fluctuation of theDC-link current around its average value, i.e. the high DC-linkcurrent harmonics.

v*
w.CPWM

-1

su
sv
sw

V0

V1

V2

V7 V7

iu

V2

V1

V0

iDC.in_ave

iDC.iniu+iv(ideal)III. PROPOSED PWM METHOD TO REDUCE DC-LINK
CURRENT HARMONICS OF VSITs

It is obvious from (2) and (3) that the DC-link current
harmonics are highly influenced by the switching functions
and output phase currents, i.e. the load power factor. Therefore,
the proposed CPWM reduces the DC-link current harmonics
by shifting output voltage references in every half control
period and adjusting the location of the gate pulses in thecontrol period. Furthermore, the proposed shifting rule of thevoltage references changes depending on whether thepolarities of the voltage references and the output phasecurrents are equal or not. In other words, the proposed
modulation method can adapt the variation of the load power
factor.

Fig. 2.
Zoomed-in waveforms of voltage references of conventional
CPWM v*x.CPWM, switching functions, and ideal iDC.in at m = 0.7,
2πft = 25 deg., and cos φ = 0.707.

A. When Polarities of Voltage References and Output
Phase Currents are Equal
In this section, the proposed shifting rule of the voltage
references to reduce the DC-link current harmonics is
introduced in case when the polarities of the voltage
references and output phase currents are equal. In particular,
the overlap period between the sector I (v*u.CPWM > 0,v*v.CPWM < 0, and v*w.CPWM < 0) and sector A (iu > 0, iv < 0, andiw < 0), i.e. the phase angle period between 15~30 degrees inFig. 1, is demonstrated as an example.
Fig. 3 shows the zoomed-in waveforms of the voltage
references of the proposed CPWM, the switching functions,and the ideal DC-link current at the modulation index of 0.7,
the phase angle of 25 degrees, and the load power factor of
0.707. Note that the proposed voltage references are realizedbased on the premise that the references can be updated at bothv*
u.CPWM

v*
v.CPWM

v*
w.CPWM

vup*

1

*
un

v

vvp*
*
wp

v
vvn*

-1

*
vwn

su
sv
sw

V0

V1

V6

V2

iu
iDC.in(ideal)iu+iw

V0
iDC.in_ave

iu+iv
Ts

Fig. 3.
Zoomed-in waveforms of voltage references of proposed CPWM
v*x.PCPWM, switching functions, and ideal iDC.in at m = 0.7, 2πft = 25 deg., andcos φ = 0.707. The divergence degree coefficients between the original
voltage references and shifted references are set as Au = 1.68, Av = 2.00, and
Aw = 2.00.

the positive-peak and negative-peak of the triangular carrier
with the general-purposed micro-computer. The proposed
voltage references are generated by shifting the originalcontinuous voltage references alternately to positive-side andnegative-side in every half control period as:v*xp   2  Ax   v*x.CPWM  Ax  1
 **vxn  Ax  vx.CPWM  1  1v  A   v
*
xp

x

*
x .CPWM 1  1 **vxn   2  Ax   vx.CPWM  Ax  1

 if v*x .CPWM

0

1



v

 

 if v*x .CPWM

0

Triangular carrierv *u.CPWM

where v*xp is the positively-shifted voltage reference, v*xn is thenegatively-shifted voltage reference, and Ax is the divergencedegree coefficient between the original voltage references andshifted references. To reduce the DC-link current harmonics,
first, the phase of which polarity is different from the othertwo phases’ polarity, i.e. the u-phase in Fig. 3 for example, isfocused. When only the u-phase current is positive as inFig. 3, the u-phase voltage reference must be the maximum at
all times during the control period in order to avoid theswitching patterns which lead the large fluctuation of theDC-link current around its average value. Therefore, theu-phase voltage reference is shifted simultaneously with thelarger phase voltage reference between the other two phases,
i.e. the v-phase in Fig. 3. Besides, the overlap of the other twophase gate pulses must be shortened in order to reduce thefluctuation of the DC-link current around its average value.
Thus, the other two phase voltage references are shiftedalternately and maximally as long as they do not exceed theu-phase voltage reference.
Note that the divergence degree coefficient Ax between theoriginal voltage references in the proposed CPWM can becalculated based on (4) and the shifting rule of the voltage
references. This calculation might be a heavy computationload for the general-purposed micro-computer and thus should
not be processed online. It is recommended to calculate thesecoefficients offline in advance.
B. When Polarities of Voltage References and Output
Phase Currents are UnequalFig. 4 shows the zoomed-in waveforms of the voltage
references, the switching functions, and the ideal DC-linkcurrent at the modulation index of 0.7, the phase angle of -20
degrees, and the load power factor of 0.707 in the case of theconventional CPWM and the proposed CPWM, respectively.
The overlap period between the sector I (v*u.CPWM > 0,v*v.CPWM < 0, and v*w.CPWM < 0) and sector F (iu > 0, iv < 0, and
iw > 0), i.e. the phase angle period between -30~15 degrees inFig. 1, is demonstrated as an example of the case when thepolarities of the voltage references and output phase currents
are not equal. Similar to the above section, the phase of whichpolarity is different from the other two phases’ polarities,
i.e. the v-phase in Fig. 4, is focused to reduce the DC-linkcurrent harmonics. When only the v-phase current is negative
as in Fig. 4, the v-phase voltage reference must be theminimum at all times during the control period in order toavoid the switching patterns which lead the large fluctuationof the DC-link current around its average value. Therefore, thev-phase voltage reference is shifted simultaneously with thesmaller phase voltage reference between the other two phases,
i.e. the w-phase in Fig. 4. Besides, the overlap of the other twophase gate pulses must be also shortened in order to reduce thefluctuation of the DC-link current around its average value.
Thus, the other two phase voltage references are shiftedalternately and maximally as long as they do not become
smaller than the v-phase voltage reference.

*
w.CPWMv *v.CPWM
-1

su
sv
sw

V0

V1

V6

iu+iw

V7

V7

V6

V1

V0
iu

iDC.in(ideal)iDC.in_ave
Ts(a)v *u.CPWM

1*vw.CPWMv *v.CPWM

-1

*
vwp
vun*

vup*

vvn*

vvp*

*
vwn

su
sv
sw

V1

V7

iu+iw

V6 V5 V0iw

iu

iDC.in(ideal)iDC.in_ave
Ts(b)Fig. 4.
Zoomed-in waveforms of voltage references, switching
functions, and ideal iDC.in at m = 0.7, 2πft = -20 deg., and cos φ = 0.707(a) conventional CPWM (b) proposed CPWM with Au = 2.00, Av = 2.00, and
Aw = 2.00.

On the other hand, at the phase angle period between 0~15
degrees in Fig. 1, the v-phase voltage reference could not be
the minimum and the shifted voltage references generate theswitching patterns which worsen the DC-link current
harmonics. Therefore, the conventional CPWM is applied atthese periods.
C. Dead-time Consideration
Fig. 5 shows the zoomed-in waveforms of the voltage
references of the proposed CPWM, the switching functions,and the DC-link current with the consideration of the deadtime under the same conditions as in Fig. 3. During the deadtime period, especially from the falling edge of su and sv, thelarge fluctuation of the DC-link current occurs.
Fig. 6 shows the zoomed-in waveforms of the modified
voltage references of the proposed CPWM, the switching
functions, and the DC-link current with the consideration of
the dead-time under the same conditions as in Fig. 3. The
v-phase divergence degree coefficient Av is modified to insert
the dead-time width margin between the falling edges of thesu and sv. In this manner, dead-time width margin at theposition where gate pulse edges match is necessary for an
avoidance of the large fluctuation of the DC-link current.

v *u.CPWM

vup*

1

vun*

*
w.CPWM

-1

1
2 7 0
7
0
2
1

V2h

vvn*

*
vwn

-V0h = V

su

V2

λh

*
vwp

v *v.CPWM
v

V2

vvp*

*

-V0h = V

V1h

λh 0

V2h

0
1

*

V1h
6

sv

V0, V7

V1

V0

2

V1

sw

V6h
Dead-time

iu

iu+iw

iDC.in(w/ deadtime)

iDC.in_ave

V6

iu+iv

(a)

Ts
iv

Fig. 5.
Zoomed-in waveforms of voltage references of proposed CPWM
v*x.PCPWM, switching functions, and iDC.in with consideration of dead-time at
m = 0.7, 2πft = 25 deg., and cos φ = 0.707 (under same conditions as inFig. 3). The divergence degree coefficients are set as Au = 1.68, Av = 2.00,
and Aw = 2.00.

(b)Fig. 7.
Harmonic flux trajectories at m = 0.7, and 2πft = 25 deg.
(a) conventional CPWM (b) proposed CPWM.

DPWM based DC-link current harmonics
reduction modulation proposed in [11]

0.350

0.300

vun*
*
vwp

v *v.CPWM*
vw.CPWM

vvn*

-1

0.250

vvp*

λRMS [-]

v *u.CPWM

vup*

1

*
vwn

0.150

0.100

su

0.050

sv

0.000
0.2

0.4

0.6

0.8

1.0

1.2

Modulation index m [-]iu
iDC.inConventional DPWM
Conventional CPWM
0.0sw

(w/ deadtime)

Proposed CPWM

0.200

Dead-time
width margin
iDC.in_ave

iu+iw

Fig. 8.
Comparison of harmonic flux rms values.
In the proposed CPWM calculations, the load power factor is set to 1.

iu+iv
Ts

Fig. 6.
Zoomed-in waveforms of modified voltage references of
proposed CPWM v*x.PCPWM, switching functions, and iDC.in with considerationof dead-time at m = 0.7, 2πft = 25 deg., and cos φ = 0.707 (under same
conditions as in Fig. 3). The v-phase divergence degree coefficient Av ischanged from 2.00 to 1.96 in order to insert the dead-time width (1% of Ts)
margin between the falling edges of the su and sv.

D. Load Current Quality
In order to evaluate the load current quality, the concept ofharmonic flux presented in [14] is used. When the switchingfrequency model of the load motor is assumed as an
inductance L, the harmonic load current vector Ih has a
proportional relationship between the harmonic flux vector λh(time integral of the instantaneous error voltage vector), as:

λ h  LI h   N 1TsNTs

 V  V   dt 
*

k





RMS 

3



 
3
0

 N 1TsNTs

2

λ h dt.d . Fig. 8 shows the harmonic flux rms values of several
modulator. With the proposed CPWM, the VSI output voltage
has large instantaneous voltage error between the voltage
references, as shown in Fig. 7, as a result of the switchingpatterns to reduce the DC-link current harmonics. Therefore,
the application of the proposed CPWM worsens the harmonic
flux rms value compared to those with the conventional
CPWM. On the other hand, the proposed CPWM is superior
to the DPWM based DC-link current harmonics reduction
modulation method proposed in [11].
IV. SIMULATION AND EXPERIMENTAL RESULTS

where Vk (k = 0~7) is the output voltage space vector of the
VSI, and V* is the voltage reference vector, respectively.
Fig. 7 shows the harmonic flux trajectories at themodulation index of 0.7, and the phase angle of 25 degrees.
With the rms value of the harmonic flux, calculated as follows,
the load current quality characterized by the modulator can beevaluated without any load information.

The performances of the conventional and proposed
CPWM are verified in simulation and experiment. In theexperiment, the three-phase VSI (7MBP50RA120, Fuji
Electric Co., Ltd.) is operated at the switching frequency of
10 kHz. A three-phase induction motor (MVK8115A-R, Fuji
Electric Co., Ltd.), the rated power of which is 3.7 kW, is used
as a test motor.

v*u.PCPWM [2.0 -/div.]*
vu.CPWM[2.0 -/div.]00

vuv [500 V/div.]

vuv [500 V/div.]00iDC.in [20 A/div.]

iDC.in [20 A/div.]00iu [20 A/div.]

iu [20 A/div.]00[10 ms/div.][10 ms/div.]

(a)

(b)

Fig. 9.
u-phase voltage reference, line-to-line voltage, DC-link current, and output u-phase current at m = 0.550 and cos φ = 0.866(a) conventional CPWM (b) proposed CPWM.
100
100

10

100
100

34.2 %

IDC.in(p.u.) = 0.322 [p.u.]

5.59 %

Input current [%]Input current [%]IDC.in(p.u.) = 0.425 [p.u.]

11

0.1
0.01
0.01
0.001
0.001
10

15.3 % 11.7 %

10
10

1
0.1
0.1
0.01
0.01

100
100

1000
10000
1000
10000
Frequency [Hz]

0.001
0.001
10

100000100000

(a)

100
100

1000
10000
1000
10000
Frequency [Hz]100000100000(b)

Fig. 10. Harmonic components of DC-link current at m = 0.550 and cos φ = 0.866 (under same conditions as in Fig. 9)(a) conventional CPWM (b) proposed CPWM.

A. DC-link Current Harmonics
Fig. 9 shows the u-phase voltage reference, the line-to-line
voltage, the DC-link current, and the output u-phase current
with each modulation method at the modulation index of
0.550 and the load power factor of 0.866. When the load
power factor is 0.866, both periods, where the polarities of thevoltage references and output phase currents are equal or not
equal, occurred. Note that the voltage references of the
proposed CPWM are shifted in every half control period asshown in Fig. 9(b).
Fig. 10 shows the harmonic components of the DC-linkcurrent under the same conditions as in Fig. 9. The maximum
value of the vertical axis (100%) indicates the maximum valueof the output phase currents. Even though the employment of
the proposed CPWM worsens the 1st switching-frequency
harmonic component of the DC-link current, the integer
multiple components of the switching frequency are reduced
compared to those with the conventional CPWM.
Consequently, the proposed CPWM reduces the DC-linkcurrent harmonics by 24.2%. Note that the DC-link current
harmonics is evaluated as IDC.in(p.u.), which is the rms value of
the DC-link current (iDC.in.rms) normalized by the maximum
value of the output phase current.

i
1
I DC .in (p.u.)  DC .in.rms 
Im
Im

2

 1

iDC .in.n  2
n 1 
where n is the harmonic order and iDC.in.n is the n-ordercomponent of the DC-link current harmonics. The harmoniccomponents of the DC-link current up to 20th-order of theswitching frequency are considered in this evaluation.
Fig. 11 shows the VSI operating waveforms at themodulation index of 0.550 and the load power factor of 0.643,
i.e. low load power factor condition. When the load power
factor is 0.643, the period where the polarities of the voltage
references and output phase current are not equal is longer
compared to that at the load power factor of 0.866.
Furthermore, the periods where the proposed shifted voltage
references are not adequate for reduction of the DC-linkcurrent harmonics arise. Therefore, the conventional
sinusoidal voltage references are partially applied in these
periods.
Fig. 12 shows the harmonic components of the DC-linkcurrent under the same conditions as in Fig. 11. The proposed
CPWM reduces the DC-link current harmonics by 10.2%.
These results demonstrate that the proposed CPWM iseffective in terms of reducing the DC-link current harmonics,
even when the load power factor is low.

v*u.PCPWM [2.0 -/div.]*
vu.CPWM[2.0 -/div.]00

vuv [500 V/div.]

vuv [500 V/div.]00iDC.in [10 A/div.]

iDC.in [10 A/div.]00iu [10 A/div.]

iu [10 A/div.]00[10 ms/div.][10 ms/div.]

(a)

(b)

Fig. 11. u-phase voltage reference, line-to-line voltage, DC-link current, and output u-phase current at m = 0.550 and cos φ = 0.643, i.e. low load power
factor condition (a) conventional CPWM (b) proposed CPWM.

100
100

100
100

24.3 %

10
10

15.6 %

IDC.in(p.u.) = 0.320 [p.u.]

6.03 %

Input current [%]Input current [%]IDC.in(p.u.) = 0.356 [p.u.]

1
0.1
0.1
0.01
0.01

10
10

5.89 %

1
0.1
0.1
0.01
0.01

0.001
0.001
10

100
100

1000
10000
1000
10000
Frequency [Hz]

0.001
0.001
10

100000100000

100
100

1000
10000
1000
10000
Frequency [Hz](a)100000100000(b)

Fig. 12. Harmonic components of DC-link current at m = 0.550 and cos φ = 0.643 (under same conditions as in Fig. 11)(a) conventional CPWM (b) proposed CPWM.

0.500

0.500

cos φ = 0.866(φ = 30 deg.)Lines : Sim. results
Plots : Exp. results

Lines : Sim. results
Plots : Exp. resultscos φ = 0.866(φ = 30 deg.)

0.400

IIDC.in(p.u.)[p.u.]
DC.in(p.u.) [p.u.]

IIDC.in(p.u.)[p.u.]
DC.in(p.u.) [p.u.]

0.400

0.300

cos φ = 0.259(φ = 75 deg.)

0.200

cos φ = 0.643(φ = 50 deg.)

0.100

0.300

cos φ = 0.259(φ = 75 deg.)

0.200

cos φ = 0.643(φ = 50 deg.)

0.100

0.000

0.000
0.0

0.2

0.4

0.6

0.8

1.0

Modulation index
Modulationindex m [-]
(a)

0.0

0.2

0.4

0.6

0.8

1.0

Modulation index m [-]Modulation(b)

Fig. 13. Simulation and experimental results of DC-link current harmonics(a) conventional CPWM (b) proposed CPWM.

Fig. 13 shows the simulation and experimental results of
the DC-link current harmonics at the load power factor from0.259 to 0.866. The proposed CPWM reduces the DC-linkcurrent harmonics under any conditions of the modulationindex and the load power factor. A higher load power factor
enables a greater reduction effect on the DC-link current
harmonics to be obtained.

B. Output Phase Current Harmonics
Fig. 14 shows the total harmonic distortion (THD) of theoutput u-phase current at the load power factor of 0.866. The
harmonic components up to 40th-order of the fundamental
frequency are considered in this evaluation. These
characteristics are similar to the analytic results of theharmonic flux rms value shown in Fig. 8. The application of10.0

Proposed CPWM
6.0

4.0

V. ELECTROLYTIC CAPACITOR LIFETIME COMPARISON

2.0

I DC .in. freq (p.u.) 

1
Im

 1

2

iDC .in.n  . f  2  K
n 1





Fig. 15 shows the harmonic components of the DC-linkcurrent considering the frequency dependency of the ESR in
the aluminum electrolytic capacitor at the modulation index of
0.550, and the load power factor of 0.866 (under the same
conditions as in Figs. 9-10). The application of the proposed
CPWM reduces the DC-link current harmonics IDC.in.freq(p.u.) by
24.2% even when the frequency dependency of the ESR in theelectrolytic capacitor is considered. Assuming that the load
motor is mostly operated at the modulation index of 0.550 andthe load power factor of 0.866, and the embedded electrolytic
capacitors in the VSI modulated by the conventional CPWM
is designed at the worst case of the rated ripple current,
i.e. FI as 1, the lifetime expectancy Ln of the electrolytic
capacitors can be given by

Ln _ conv.CPWM  Lo  FI  Lo  1  5000 h
Ln _ prop.CPWM  Lo  FI  Lo  1.34  6 700 h





where Lo is 5000 hours in case of the aluminum electrolytic
capacitor (RWF series, Nippon Chemi-Con Corp. [16]).
Note that the above lifetime calculation is just an example.
However, it can be concluded that the application of the
proposed CPWM might extend the lifetime of the electrolytic
capacitor about 1.34 times longer at most than that with theconventional CPWM.
VI. CONCLUSION
This paper proposed the novel CPWM to reduce theDC-link current harmonics of VSI over entire load power
factor range. The proposed CPWM contributed to the lifetime

0.0

Conventional DPWM

0.2

0.4

0.6

0.8

1.0

1.2

Modulation index m [-]Fig. 14.

THD of output u-phase current iu at cos φ = 0.866.

TABLE I.

FREQUENCY COEFFICIENT OF RATED RIPPLE CURRENTFLOWING THROUGH ALUMINUM ELECTROLYTIC CAPACITORS(RWF SERIES, NIPPON CHEMI-CON CORP. [16])Frequency [Hz]

50

120

300

1k

3 k or more

Coefficient Kf

0.80

1.0

1.1

1.3

1.4

100
100

IDC.in.freq(p.u.) = 0.303 [p.u.]

Input current / Kf [%]Table I shows the frequency coefficient (Kf) of the rated
ripple current flowing through the aluminum electrolytic
capacitor (RWF series, Nippon Chemi-Con Corp. [16]),
which is used in the laboratory setup. With the considerationof the frequency dependency of the equivalent series
resistance (ESR) in the aluminum electrolytic capacitors, theDC-link current harmonics can be recalculated for the lifetime
estimation as:

Conventional CPWM
0.0

24.4 %

10
4.13 %

1
0.1
0.1
0.01
0.01
0.001
0.001
10

100
100

1000
10000
1000
10000
Frequency [Hz]100000100000

(a)
100
100

Input current / Kf [%]The expected lifetime of the electrolytic capacitor can becalculated as the multiplication of the specified lifetime (Lo)on the manufacturer catalog by three acceleration rates which
are dependent on the ambient temperature (FT), the ripple
current (FI), and the applied voltage (FV) [15]. In thisevaluation, only the acceleration according to the ripple
current FI is considered, and the other two factors are assumed
as 1.



DPWM based DC-link current harmonics
reduction modulation proposed in [11]8.0THD of iu [%]the proposed CPWM leads to higher distortion of the output
phase current compared to those with the conventional
CPWM. Nevertheless, those THD with the proposed CPWM
is superior to those with the DPWM based DC-link current
harmonics reduction modulation method proposed in [11], andthe almost same level of those with the conventional DPWM
method.

1010IDC.in.freq(p.u.) = 0.230 [p.u.] 10.9 %8.36 %

1
0.1
0.1
0.01
0.01
0.001
0.001
10

100
100

1000
10000
1000
10000
Frequency [Hz]100000100000(b)

Fig. 15. Harmonic components of DC-link current considering frequency
dependency of ESR in aluminum electrolytic capacitor at m = 0.550, andcos φ = 0.866 (under same conditions as in Figs. 9-10)(a) conventional CPWM (b) proposed CPWM.

extension of the smoothing capacitors in the motor drive
systems. Furthermore, high cost hardware such as FPGA was
not necessary because this modulation method could be
implemented with only one triangular carrier. The DC-linkcurrent harmonics were reduced by shifting the voltage
references in every half control period to reduce thefluctuation of the DC-link current around its average value.

The analytical results of the harmonic flux rms values
confirmed that the proposed CPWM achieved the same levelof the load current quality as the conventional DPWM. In
addition, the experimental results confirmed that theapplication of the proposed CPWM reduced the DC-linkcurrent harmonics by 24.2% at most even when the frequency
dependency of the ESR in the electrolytic capacitor wasconsidered. As a result of the capacitor lifetime estimation, the
24.2% reduction of the DC-link current harmonics might
extend the lifetime of the electrolytic capacitor about 1.34
times longer at most than that with the conventional CPWM.
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