Comparison of Circuit Topologies for Active Power
Decoupling toward High Power Density
Jun-ichi Itoh, Tomokazu Sakuraba, Keisuke Kusaka, Hiroki Watanabe and Keita Furukawa
Department of Electrical Engineering
Nagaoka University of Technology, NUT
Niigata, Japan
itoh@vos.nagaokaut.ac.jp, t_sakuraba@stn.nagaokaut.ac.jp
Abstract— This paper discusses how to achieve high power
density with high efficiency for single-phase AC connected
inverter with active or passive power decoupling circuit. An
inverter connected to a single-phase grid requires a power
decoupling device to compensate power pulsation with twice thegrid frequency. As the alternative to an electrolytic capacitor
connected to DC-link, active buffer circuits with bi-directional
chopper and a flying capacitor converter (FCC) with power
decoupling capability have been evaluated in terms of long
lifetime. In this paper, Pareto optimization is used to compare thecharacter of the power decoupling circuits in terms of an
efficiency and a power density. The volume of capacitors in the
FCC with ceramic capacitors can be reduced by 54.6% compared
to bulky electrolytic capacitors. As a result, when the 400-V SiCMOSFETs are used for the FCC at 25 kHz, a maximum power
density of 5.3 kW/dm3, which is 1.3 times higher than the power
density of the passive topology, can be obtained. Furthermore,
the total power loss is reduced by 10.5% in comparison with thatof the conventional converter.
Keywords— single-phase inverter, power ripple compensation,
power density design

I. INTRODUCTION
In recent years, single-phase grid connected converters
have been studied actively as the power conversion systems(PCSs) for photovoltaics systems or battery energy storage
systems and so on. Instantaneous power of the single-phasegrid oscillates at twice the grid frequency whereas the output
power is constant. As a result, a power ripple with twice thegrid frequency occurs at the connection point between the
chopper and the inverter. In order to absorb this power ripple,
bulky electrolytic capacitors are used in conventional circuits.
However, the electrolytic capacitor limits the lifetime and size
reduction of the PCS.
As an alternative power decoupling method, an active
power decoupling which consists of small capacitors, inductors
and switching devices has been proposed [1-3]. As a result, the
PCS with long lifetime is expected by using film capacitors or
ceramic capacitors as the buffer capacitor. However, an
additional inductor and switching devices for the buffer circuit
are required to control the buffer capacitor voltage. By
increasing the switching frequency of the active buffer circuit,the inductance can be reduced, however the size of the heatsink

becomes larger due to increase of the switching loss. As aresult, a relationship between the inductor volume and theheatsink volume indicates the trade-off characteristics. Thus,
the buffer circuit should be designed and operated at an
adequate switching frequency to maximize the power density.
In [1] and [3], the ceramic capacitors are applied for the power
decoupling circuit in order to achieve a high power density. In[2], the power loss mechanism is analyzed in order to improve
the system efficiency of the active buffer circuit. However, past
literatures have not clearly mentioned the conditions to achievea higher efficiency and a power density than the electrolytic
capacitor.
This paper clarify the conditions to achieve the higher
power density and the higher efficiency by comparing among
the electrolytic capacitor and the active power decoupling
topologies. First, the design flow for the passive topology using
the electrolytic capacitor and the active buffer topology [4-5]using the ceramic capacitor is introduced. Second, from thedesign flowchart and the specifications of the commerciallyavailable products, the power density and the efficiency of theactive power decoupling circuit are evaluated by Pareto
optimization. Finally, the comparisons of a total loss and a total
volume at the maximum power density point are discussed inorder to achieve a high efficiency and a high power density.
II. CIRCUIT CONFIGURATION AND DESIGN METHOD
A. Passive Power Decoupling Circuit
Fig. 1 shows the circuit configuration of the passive power
decoupling method using an electrolytic capacitor. Table 1
shows the circuit specifications. This paper evaluates thevolume of the buffer circuit based on the ripple current in theDC-link. In order to evaluate the ripple current, a power supply
with an internal impedance Rin is considered to emulate theoutput of the boost chopper connected to PV.
In the passive topology, the bulky electrolytic capacitor isconnected to absorb twice grid frequency. The ripple current
restricts the lifetime of the electrolytic capacitor. Therefore, theelectrolytic capacitor, which has the allowable ripple current
higher than the calculated ripple current, is selected in thispaper. The current which flows into the electrolytic capacitor
includes not only the power ripple component but also theswitching frequency component from the inverter. The

capacitor ripple current is the function of the output power
factor and the modulation index, which is a nonlinear value [6].
Then, the effective value of the capacitor ripple current isexpressed by
I rms _ cap = K cap (φ , m )I m

(1),

where, Im is the maximum value of the output current, φ is theoutput power factor, m is the modulation index and Kcap(φ, m)is the coefficient regarding ripple current in the DC-link which
is obtained by simulation.
Fig. 2 shows the value of Kcap(φ, m) which is obtained by
the ration between the output current and the ripple current
with circuit simulation as follows. In general, the output power
factor of the grid-connected inverter is approximately unity.
The modulation index, which expresses the ratio of the dc-link
voltage Vdc and the maximum output voltage Vm, is 0.74 in thiscase. Therefore, from Fig.2, Kcap(1, 0.74) is 0.56. With thefrequency multipliers, the allowable ripple current is calculated
by
2

2

 I
  1  ∞ 2
  I nsw
′ _ cap =  100 Hz  + I rms
 K 100 Hz   K sw  n =1(2),

where, I100Hz is the effective current whose frequencies aretwice the grid frequency, Insw is the effective current at theswitching frequency, K100Hz and Ksw are the frequency
multipliers at 100 Hz and the switching frequency,
respectively.
An electrolytic capacitor, which has the allowable ripple
current higher than the result of (2), should be required.
B. Boost Type Active Buffer Circuit
Fig. 3 shows the circuit configuration of the boost typeactive buffer circuit. The active circuit consists of a boost
chopper and a small capacitor Cbuf to absorb the power ripple in
DC-link. The active buffer circuit achieves long lifetime
because the film capacitors or the ceramic capacitors are usedas the buffer capacitor. The principle for the power decoupling
between the DC and the AC sides is explained as follows.
Fig. 4 shows the relationship among the input power pin, theoutput power pout and the compensation power pbuf in the active
buffer. The output instantaneous power is shown in (3) when
the output current is the sinusoidal wave with unity power
factor.
pout =

Fig. 1. Passive power decoupling circuit.
Table 1. System specification.

Vm I m(1 − cos 2ωout t )2(3),

where, Vm is the peak voltage of the single-phase grid and ωoutis the angular frequency of a grid. From (3), the twice gridfrequency power ripple occurs in the DC-link. In order toabsorb the power ripple, the instantaneous power pbuf in theactive buffer is controlled according toParameter

SymbolValue

Rated power

Pout

6 kW

Output voltage

Vout

200 V

Output frequency

fout

50 Hz

Power factor

cos

1.0

Input voltage

Vin

150 V

DC link voltage

Vdc

380 V

Input impedance

Rin

3.3

Modulation index

m

0.74

Ambient temperature

Ta

40 °C

Junction temperatureTj

140 °C
3 °C/dm3

CSPI
0.7
0.7

Power factor cos =1.0

0.6
0.6

cos =0.8
0.5
0.5

cos =0.6

0.4
0.4

cos =0.4

0.3
0.3

cos =0.2

0.2
0.2
0.1
0.1
0.1
0.1

0.2
0.2

0.3
0.3

0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.4
0.5
0.6
0.7
0.8
0.9
1
Modulation index m
Fig. 2. Current ripple coefficient for the calculation of the ripple current
flowing into the electrolytic capacitor. The ripple current is function of theoutput power factor cosφ and the modulation index m.

1
pbuf = Vm I m cos 2ωout t
2(4),

Fig. 5 shows the design flowchart in order to optimized
design the boost type active buffer. First, the capacitance of thebuffer capacitor is calculated based on an average voltage and a
voltage oscillation range of the buffer capacitor. Then, thecapacitor volume VolCbuf is determined from the commerciallyavailable products. The switching device is decided based on
the maximum voltage of the buffer capacitor. In this paper, theswitching device, which has a rating voltage of 1200 V, isused. Second, the boost inductor is designed based on theswitching frequency fsw and the inductor ripple current. The

volume of the boost inductor is estimated according to Area
Product concept [7]. Third, the heatsink volume is calculated
from the thermal resistance which depends on the conduction
loss Ploss_cond and the switching loss Ploss_sw of the switching
devices. Finally, the Pareto optimization is obtained throughvarying the switching frequency in order to reveal the
maximum power density point.

Rin idc
SW1
Cf

Vdc

iout

iL
Lbuf

Cbuf

2-levelinverterLC
filterSW2

The capacitance is decided from the relationship between
the storage energy and the capacitor voltage. From the storage
power in (4), the instantaneous power pbuf in the active buffer isrepresented by

Boost type active buffer
Fig. 3. Boost type active buffer circuit.
pout =

2
2

1
V  
V  
Pc = ωout Cbuf Vave + Δ c  − Vave − Δ c  22 
2  


vout

Pin =

(5),

Vm I m2

Vm I m(1 − cos 2ωoutt )2

where Vave is the average voltage and ΔVc is the voltage
oscillation range of the buffer capacitor.
In the passive topology circuit with the bulky electrolytic
capacitor, the power storage is achieved by the large
capacitance. On the other hand, in the active buffer, the storage
power is achieved through the large ΔVc [8]. This is theprinciple to reduce the capacitance with active power
decoupling method. Then, the capacitance to compensate thepower ripple is calculated by
Cbuf =Pc
ωoutVave ΔVc(6),

The buffer capacitor requires the large Vave and ΔVc for
reducing the capacitance. However, when the buffer capacitor
voltage is increased, the switching device with the high rating
voltage is required. In this paper, the switching device, which
has the rating voltage of 1200 V, is selected as the peakcapacitor voltage of 800 V.
The boost inductor is designed based on an allowable ripple
current ΔiL. The inductance becomes the maximum value when
the difference between the dc-link voltage and the buffer
capacitor voltage reaches the maximum. Thus, the inductanceof the boost inductor is provided by
ΔV c V + − V dc
V dc  ave
2 
Lbuf =ΔV c
Δi L f sw
V ave +
2

(7),

The inductor volume depends on many parameters of thecomponents. There are several ways to select the core for the
inductor. In this paper, the boost inductor is designed by Area
Product concept using the window area and the cross-sectional
area [7]. Therefore, the volume of the boost inductor VolLbuf iscalculated by Lbuf I
Vol Lbuf = K v  K u Bmax J 


2
max

Fig. 4. Single-phase power ripple compensation.
Start
input
Pout
Vdc
vout
fout
a
iL
Vin
iin
iin

Decision Vave, Vc, Vave_fc, vfc
Calculation
Cbuf and Cfc, VolCbuf from Fig. 8
Selection Switching device
Switching frequency fsw=1 kHz~100 kHz
Calculation
Lbuf and Lfc, VolLbuf by Eq. (8)Calculation
Conduction loss and Switching loss, Volheatsink by Eq. (9)Calculation total volumeVoltotal by Eq. (33)
Calculation
Power density(8),by Eq. (32), (34)fsw
End
Fig. 5. Designing flow for active buffer circuit.

where, Kv is the volume coefficient depending on the shape ofcores, Imax is the maximum current flowing to the inductor, Ku
is the fill factor of the window, Bmax is the maximum flux
density of the core, and J is the current density of the wire.
The switching devices require a cooling system such asheatsinks and fans. In general, the cooling system is designed
based on the thermal resistance. CSPI (cooling system
performance index) is introduced to estimate the volume ofcooling system [9]. CSPI means the cooling performance perunit volume of the cooling system. The cooling system isminiaturized when CSPI become higher. The volume of thecooling system Volheatsink is provided by
Vol heatsink =3
4

power, Efficiency

1
Rth ( f − a )CSPI(9),

where, Rth(f-a) is the thermal resistance of the cooling system

Rin idc

which is given by
Rth ( f − a ) =T j − TaPloss(

− Rth ( j − c ) + Rth (c − f )

)

SW1

(10),

iout

Vdc

Cf

where, Tj is the junction temperature of the switching device,
Ta is the ambient temperature, Rth(j-c) is the junction-to-casethermal resistance and Rth(c-f) is the case-to-fin thermal
resistance. The total loss Ploss, which is composed of the
conduction loss Ploss_cond and the switching loss Ploss_sw from theswitching devices, is calculated by
Ploss = Ploss _ cond _ buffer + Ploss _ sw _ buffer(11),

where, Ploss_cond and Ploss_sw are given by

1 Tout 2iL ron _ buffer dt
Tout 0(12),

1
1 Tout(eon + eoff ) f sw
vc iL dt
Edcd I md
Tout 0(13),

Ploss _ cond _ buffer =Ploss _ sw _ buffer =respectively, where, Tout is the period of the grid, ron is the onresistance of the switching device, fsw is the switchingfrequency of the active buffer, eon and eoff are the turn-on andturn-off energy per switching referred from a datasheet,respectively, Edcd and Imd are the voltage and the current underthe measurement condition of the switching loss described in
the datasheet. The buffer capacitor voltage vc and the boost
inductor current iL are expressed by

vc = Vave −
iL =

ΔVc
sin (2ωout t )
2

Vave
dv
Cbuf c
Vdc
dt

(14),
(15),

respectively. From (13), the increase in the switchingfrequency leads to the increase in the switching loss. The
cooling performance can be improved by fans to minimize theheatsinks. However, the system lifetime is limited by thesefans. Thus, in this paper, the cooling system is designed on theassumption that the natural cooling is applied.
The small filter capacitor Cf is necessary in order to absorb
the ripple current at the switching frequency. The impedance ofthe filter capacitor should be sufficiently small against theinternal impedance Rin. Thus, Cf is designed by
1
10
Cf =
2 × 2πf sw _ inv Rin

C. Buck Type Active Buffer Circuit
Fig. 6 shows the circuit configuration of the buck typeactive buffer circuit. In this circuit, the capacitor voltage is

iL

SW2

2-levelinverterLC
filtervout

Cbuf

Buck type active buffer
Fig. 6. Buck type active buffer circuit.

lower than the DC-link voltage. The buck type active buffer
can still be designed through the flowchart in Fig. 5.
The buffer capacitor is designed by (6). However, the DC
link voltage limits the peak voltage of the buffer capacitor. As
a result, the buffer capacitance has to be larger than the one of
the boost type active buffer.
The inductance of the smoothing inductor reaches the
maximum value when the capacitor voltage is a half of the
input voltage. Thus, the inductance is designed by

Lbuf =Vdc
4 ΔiL f sw

(17),

where, iL is the current which flows to the smoothing inductor
which is provided by

i L = Cbuf

dvc
P
= − out cos(2ω out t )
dt
Vave

(18),

The volume of the smoothing inductor is estimated by Area
Product of (8). The loss generated by the switching devices iscalculated by substituting (18) to (11), (12) and (13).
D. Flying Capacitor Converter
Fig. 7 shows the circuit configuration of a flying capacitor
converter (FCC) with a capability of the power decoupling [11].
This circuit consists of a flying capacitor Cfc, a boost inductor
Lfc and four switches. The power ripple is absorbed by theflying capacitor whose voltage oscillates at twice the gridfrequency. This circuit has no additional inductor for a buffer
voltage control. The duty ratio is decided from the sum of theduties of a current control for the FCC, a power decoupling
control and a noninterference control. Therefore, the duties forS1 and S2 are obtained byVin{1 + cos(2ωout t )}
Vdc

(19),


Vin  
Vdc 
cos(2ωout t )
1 + 1 −
Vdc   V fc _ ave 


(20),

d1 =

(16),

where fsw_inv is the switching frequency of the inverter.

Lbuf

d2 =

respectively. Note that the S3 and S4 are complementary to S2and S1, respectively. When the boost ratio is larger than 2, aninductance of the boost inductor in the worst case is calculatedby
L fc =[max (Vin − Vdc − v fc )d1 , (Vin − v fc )d 2
f sw Δiin

]

(21),

where Δiin is the allowable current ripple and fsw is theswitching frequency of the FCC. The volume of the boost
inductor is estimated by Area Product of (8). The voltage of theflying capacitor vfc is given by

Δv fc

v fc = V fc _ ave −2

sin (2ωout t )The conduction loss and the switching loss caused byswitching devices are calculated by

Ploss _ sw _ FCC =(1 Tout 2
iin ron _ FCC dt
Tout 0)

1
1 Touteon + eoff f sw
v Sn iin dt
E dcd I md
Tout 0

(23),
(24),

respectively, where ron_FCC is the on-resistance of switching
devices. The maximum voltage applied for each switch vSn isexpressed by

vS1 = vS 4 = Vdc − v fc

(25),

v S 2 = vS 3 = v fc

(26),

respectively. Based on the designing flowchart of Fig. 5, thePareto front of the FCC is obtained.

Fig. 8 shows the circuit configuration of an overall PCSs
which is consisted of a boost chopper, a buffer circuit, a gridinterconnected inverter and a LC filter. The FCC comes in the
boost chopper and the buffer circuit. In order to compare
between the volumes of the FCC and the conventional
topology, the volume design of the boost chopper is necessary.
The inductance of a boost inductor is determined by

Vin Vdc − Vin
Δiin f sw Vdc

iin

Lfc

Vin

Cfc

(27),

where, Δiin is the input current ripple, which is 30% of the rated
input current in this paper. The total loss of the switching
devices is expressed by

vfc

Cf

Vdc

iout
2-levelinverterLC
filter

vout

S3

S4

Capacitor for power decoupling
Fig. 7. Flying capacitor converter applied for the power decoupling.

Sp

Vdc

Lcho
Vin

iout
Buffercircuit

2-levelinverterLC
filtervout

Sn

Boost chopper
Fig. 8. Circuit configuration of an overall PCSs.

Ploss _ chopper = Ploss _ cond _ chopper + Ploss _ swi _ chopper(28),

where, the conduction loss Ploss_cond_chopper is calculated byΔi 2 
Ploss _ cond _ chopper = ron _ chopper  I in2 + in 
3 


(29),

and Ploss_swi_chopper is the total switching loss by Sp and Sn
whose the switching losses are obtained by[] (30),[] (31),

1f swVdc eon (iin + Δiin ) + eoff (iin − Δiin )Edcd I md
1
Ploss _ sw _ sn =f swVdc eon (iin − Δiin ) + eoff (iin + Δiin )Edcd I md

Ploss _ sw _ sp =III. BOOST CHOPPER DESIGN

Lcho =

S2(22),

where, Vave_fc is the average voltage and Δvfc is the voltage
oscillation range of the flying capacitor. Therefore, thecapacitance of the flying capacitor is calculated from (6).

Ploss _ cond _ FCC =S1

respectively.
IV. EFFICIENCY AND POWER DENSITY EVALUATION

A. Comparison Pareto front of buffer circuit
In the passive topology circuit, the electrolytic capacitor
connected to the DC-link is selected based on (2). The
allowable ripple current becomes 18.7 A on the assumptionthat K100Hz=1.0 and Ksw=1.4. Thus, the electrolytic capacitor,
which has the allowable ripple current larger than 18.7 A, isselected. When the rating voltage of the electrolytic capacitor isfixed, the volume of the electrolytic capacitor becomes smaller
by connecting the capacitors with small allowable ripplecurrent in parallel [10]. In this paper, 28 electrolytic capacitors,
which have the allowable ripple current of 1 A per one
capacitor, are connected in parallel with a ripple current marginof 50%. As a result, the total capacitance is 5040 μF.
Fig. 9 shows a relationship between the capacitance and thetotal volume when the ceramic capacitors are connected inparallel. In the active buffer, the ceramic capacitor is used as
the buffer capacitor in term of the high energy density. The DC
bias characteristic, which is the decrease in the capacitance ofthe ceramic capacitor by DC bias, has been considered in Fig.
9. Comparing to the electrolytic capacitor, the ceramic
capacitor has the higher ratio between the allowable ripple
current and the capacitance. Therefore, when the requirementof the capacitance for the power decoupling is satisfied, theallowable ripple current is sufficient for the ceramic capacitor.
Specifically, when the average voltage Vave and the voltage
amplitude ΔVc are 600 V and 400 V respectively, thecapacitance Cbuf is 79.6 μF. The volumes of capacitors of GRM
series and KC series (Murata Manufacturing Co., Ltd.) are 0.23
dm3 and 0.44 dm3 respectively in the total capacitance of 79.6
μF. However, the required numbers of the ceramic capacitor
are 1136 and 13440 respectively, which are not realistic. On
the other hand, when a ceramic capacitor of the EVS series(Murata Manufacturing Co., Ltd.) is applied, the total volume
and the required number are 0.11 dm3 and 45 in 79.6 μF.
Therefore, the EVS series capacitor (Murata ManufacturingCo., Ltd.) is used in this paper.
Table 2 shows the selected components. Fig. 10 shows thePareto front of the power density ρpower and the efficiency ηwith the switching frequency fsw as a variable. The power
density is calculated by (19) from the total volume of (20). The
efficiency η is provided by (21).

ρ power =PoutVoltotal(32),

Vol total = Vol Lbuf + Vol Cbuf + Vol sw + Vol heatsink

η=

Pout
Pout + Ploss + Ploss _ Cbuf + Ploss _ Cf

(

)

(33),

(34),

where, VolCbuf and Volsw are the volumes of the buffer capacitor
and the package of the switching device. The power density
reaches the maximum value, when SiC-MOSFET is used in the
boost type active buffer at 30 kHz. Specifically, the maximum
power density of 17.0 kW/dm3 are achieved with the efficiencyof 99.5%. On the other hand, the power density of 18.8
kW/dm3 and the efficiency of 99.8% are achieved in thepassive topology. The power density of the passive topology is
1.4 times higher than the maximum power density of the active
buffer.

B. Volume Comparison between Boost Type and Buck Type
Active Buffer
Fig. 11 shows the relationship between the rated power andthe total volume of the boost and the buck type active buffer. In

0.800

0.600

0.400

0.200

0.000
0.00

20.00

40.00

60.00

80.00

100.00120.00Fig. 9. Relationship between capacitor volume and capacitance.
Table 2. Selected components.
Circuit
Passive
bufferPart

Marking

Maximum ration

Cin

Nippon Chemi-Con
EKMZ451VSN181MP30S

450 V, 1.0 Arms
180 F

Cbuf

Murata Manufacturing
EVS20329S2G306MS09

400 V
30 F

ROHM
SiC-MOSFET, SCH2080KE

1200 V
40 A

Fuji Electric
IGBT, FGW30N120HD

1200 V
30 A

Fuji Electric
Si-MOSFET, FMH30N60S1

600 V(2 seriesconnection)
30 A

Murata Manufacturing
EVS20329S2G306MS09

400 V
30 F

ROHM
SCT2120AF

650 V
29 A

Sp
Sn

ROHM
SiC-MOSFET, SCT120AF

650 V
29 A

S1
S2
S3
S4

ROHM
SiC-MOSFET, SCT120AF

650 V
29 A

ROHM
SiC-MOSFET, SCTMU001F

400 V
20 A

Cfc

Murata Manufacturing
EVS20329S2G306MS09

400 V
30 F

Cf

Murata Manufacturing
KC355WD72E225MH01

450 V
1 F

Boost typeactive buffer SW1
SW2

Cbuf
Step down
type
active buffer SW1
SW2
Boost
chopper

Flyingcapacitor
converter

Fig. 11, the frequency value expresses the maximum power
density point in each rated power. In the region of less than 3
kW, the volume of the buck type active buffer is smaller thanthat of the boost type active buffer, especially 24% smaller at 2
kW.
Fig. 12(a) shows the volume ratio of components at the
maximum power density point when the output power is 2 kW.
In the boost type active buffer, the capacitance of the buffer
capacitor can be reduced by higher capacitor voltage, however,the series connection numbers increases to satisfy the rating
voltage. As a result, the volume of the buffer capacitor is 167%of that of the buck type active buffer.
Fig. 12(b) shows the volume ratio of components at the
maximum power density point in 6 kW. In the buck type active
buffer, the cooling system volume accounts for 64% of the total
and it is 244% against that of the boost type active buffer.
Because the buffer capacitor voltage is lower than DC-link
voltage, the high effective current of the boost inductor leads tothe large conduction loss. The increases of the heatsink volume

C. Comparison Pareto front of FCC
Fig. 13(a) presents the operation waveforms which isoperated by a 1-kW prototype of the FCC without the power
decoupling control. According to Fig. 13(a), the DC-link
voltage fluctuates at twice the grid frequency. On the other
hand, from Fig. 13(b), a flying capacitor voltage whose
amplitude and average are 100 Vpeak-peak and 200 V respectively,
oscillates at twice the grid frequency. As a results, the DC-link
voltage becomes the constant. This experimental waveforms
show that the single-phase power ripple can be compensated by
the flying capacitor.
Fig. 14 shows the Pareto front of the FCC and the boost
chopper with the buffer circuits. The switching devices with a
rated voltage of 650 V and 400 V are selected for the FCC in
Table 2 and the derating current which is 5 times of the rated
input current is considered. The maximum voltages of theflying capacitor are set to 340 V and 250 V for each switching
device. According to the Fig. 14, the power density approaches
the maximum value, when SiC-MOSFET with a rated voltage
of 400 V is used in the FCC at 25 kHz. A maximum power
density of 5.3 kW/dm3 is achieved with efficiency of 98.9%.
On the other hand, the power density of 4.2 kW/dm3 and theefficiency of 98.8% are achieves in the passive topology.
Therefore, the maximum power density of the FCC is 1.3 times
higher than the power density of the passive topology.

D. Volume Comparison
Fig. 15 shows the volume ratio of components at the
maximum power density point. The component volumes arenormalized with the total volume of the passive topology as
100%. In the FCC with 400-V SiC-MOSFET, the volume of
the flying capacitor is reduced by 54.6% of that of theelectrolytic capacitor. As a result, the overall volume is 78.8%
in comparison with the one of the passive topology. When the
flying capacitor voltage is set to 250 V and the switching
device with the rated voltage of 400 V is applied to the FCC,
the flying capacitor is twice the volume of the one with the
rated voltage of 650 V. However, the volumes of the boost
inductor and the cooling system are reduced to 58.3% and46.2%, respectively. As a result, the total volume of FCC withthe switching devices of the 400-V rated voltage is 57.5% ofthat of FCC with a rated voltage of 650 V.
E. Loss Comparison
Fig. 16 shows the power loss ratio at the maximum power
density point. The loss caused by the boost inductor is ignored.
The loss is normalized with the total loss of the passive
topology. When the switching device with a rated voltage of
650 V is used for the FCC, the total power loss is 120%. On theother hand, the conduction loss of the switching devices of
400-V rated voltage is reduced to 56.3% in comparison withthat of the 650-V rated voltage device. As a result, the total
power loss of the FCC using the switching device with the

100
100

SiC-MOSFET
30 kHzfsw increases.

1 kHz

Passive99.5
99.5

Si-MOSFET
20 kHz

99
99

IGBT 15 kHz
SiC-MOSFET 20 kHz

98.5
98.5

98
98

Boost type active buffer
Step down type active buffer
0

10
15
20
10000
15000
20000
Power density [kW/dm3]
Fig. 10. Pareto front of the passive and the active buffer circuits.

5
5000

0.6
0.6

CSPI=3 ̊ C/dm3(Natural cooling)
0.5
0.5

20 kHzBuck type active buffer(solid line)

0.4
0.4

Boost type active buffer(dashed line)

0.3
0.3

30 kHz

25 kHz40 kHz0.2
0.2

30 kHz

50 kHz35 kHz

0.1
0.1
00
1
1000

35 kHz40 kHz40 kHz

50 kHz

3
4
5
6
3000
4000
5000
6000
Rated power [kW]Fig. 11. Relationship between the rated power and the volume of the boost andbuck type active buffer at the maximum power density points.

2
2000

0.12
0.1

Volume [dm3]is more critical than that of the boost type active buffer.
Therefore, in the region of more than 3 kW, the total volume of
the buck type active buffer is larger than that of the boost typeactive buffer.

0.08
0.06
0.04
0.02
0
1

2

(a) 2 kW
0.6
0.6
0.5
0.5

Rated power=6kW
Switching device

0.4
0.4
0.3
0.3

Cf
Heatsink

0.2
0.2
0.1
0.1
00

Cbuf
Lbuf
Boost type active
bufferBuck type active
buffer1
2(30 kHz)(20 kHz)(b) 6 kW
Fig. 12. Volume comparison of the active buffer circuits.

rated voltage of 400 V is 89.5% compared to that of theconventional topology.

REFERENCES[1]

S. Qin, Y. Lei, C. Barth, W. Liu, R. C. N. Pilawa-Podgurski : “A HighEfficiency High Energy Density Buffer Architecture for Power Pulsation
Decoupling in Grid-Interfaced Converters”, IEEE ECCE 2015, pp.149157 (2015)[2] Chia-Tse Lee, Yen-Ming Chen, Li-Chung Chen, Po-Tai Cheng :“Efficiency Improvement of a DC/AC Converter with the Power
Decoupling Capability”, IEEE APEC 2012, pp. 1462-1468 (2012)[3] C. B. Barth, I. Moon, Y. Lei, S. Qin, R. C. N. Pilawa-Podgurski:“Experimental Evaluation of Capacitors for Power Buffering in SinglePhase Power Converters”, ECCE 2015, pp. 6269-6276 (2015)[4] H. Hu, S. Harb, N. Kutkut, I. Batarseh, Z. J. Shen : “Power Decoupling
Techniques for Micro-inverters in PV Systems — a Review,” Energy
Conversion Congress and Exposition 2010, pp.3235-3240, pp. 12-16(2010)[5] Y. Xue, L. Chang, S. B. Kjaer, Bau, J. Bordonau, T. Shimizu :“Topologies of Single-phase Inverters for Small Distributed Power
Generators: An Overview,” IEEE Transactions on Power Electronics,
Vol.19, No.5, pp. 1305-1314 (2004)[6] Y. Kashihara, J. Itoh : “Parameter design of a Five-Level Inverter for PV
systems”, ICPE 2011 - ECCE Asia, No. ThB3-2, pp. 1886-1893 (2011)[7] Wm. T. Mclyman : “Transformer and inductor design handbook”,
Marcel Dekker Inc., (2004)[8] S. Fan, Y. Xue, K. Zhang : "A Novel Active Power Decoupling Method
for Single-Phase Photovoltaic or Energy Storage Applications", IEEE
ECCE2012, pp. 2439-2446 (2012)[9] Uwe DROFENIK, Gerold LAIMER and Johann W. KOLAR :”Theoretical Converter Power Density Limits for Forced Convection
Cooling”, Proceedings of the International PCIM Europe Conference,
pp. 608-619 (2005)[10] T. Nakanishi and J. Itoh, “Capacitor volume evaluation based on ripple
current in Modular Multilevel Converter”, International Conference onPower Electronics, No. 09, pp. 815-822(2015)[11] H.Watanabe, K. Kusaka, K. Furukawa, J. Itoh: "DC to Single-phase AC
Voltage Source Inverter with Power Decoupling Circuit based on Flying
Capacitor Topologu for PV System", APEC2016, pp.1336-1343. (2016)

0

Input current [10A/div]0

Inverter DC voltage [100/div]

Inverter DC voltage [100/div]

Flying capacitor voltage [100V/div]

Output current [10A/div]0

Flying capacitor voltage [100V/div]
Output current [10A/div]

0

0

0

(a) without power decoupling(b) with power decoupling
Fig. 13. Operation waveforms of the flying capacitor converter.

99.5
99.5

fsw increases.

1 kHz

25 kHz (400V SiC-MOSFET)

9999

30 kHz98.5
98.5

Flying capacitor converter
Chopper and active buffer

97.5
97.5

9797

Boost type 20 kHz
20 kHz (650V SiC-MOSFET)

Buck type 10 kHz

9898

Chopper and electrolytic capacitor(passive topology)

5
6
3
4
3000
4000
5000
6000
Power density [kW/dm3]
Fig. 14. Pareto front of the FCC and the boost chopper with the buffer circuits.

00

1
1000

2
2000

250

200

Volume [%]This paper discussed a comparison of circuit topologies foran active power decoupling of single-phase inverter in terms ofefficiency and power density. In particular, the volume ofcapacitors is reduced by 54.6% in a FCC with ceramic
capacitors compared to bulky electrolytic capacitors. As aresult, when a SiC-MOSFET of the 400-V rated voltage isapplied for the FCC at 25 kHz, the maximum power density is
5.3 kW/dm3 which is 1.3 times higher than the power densityof the electrolytic capacitor. Furthermore, the total power loss
is reduced to 89.5% in comparison with that of theconventional converter. Therefore, the flying capacitor
converter can achieve the highest power density and the highest
efficiency in the discussed topologies in this paper.

Input current [10A/div]

150

100

50

0
1

2

3

4

5

Fig. 15. Volume comparison in the maximum power density points.
140
120

Loss [%] 100%=74.5 W

V. CONCLUSION

4 ms/div

4 ms/div

100
80
60
40
20
0
1

2

3

4

5

Fig. 16. Loss comparison in the maximum power density points.