Hybrid Multiple Chopper Cells of PWM and Square-wave Operation for
Solid-state Transformer
Naoto Kikuchi, Jun-ichi Itoh, Keisuke Kusaka, *Hoai Nam Le
Nagaoka University of Technology/ * Norwegian University of Science and Technology
1603-1, Kamitomioka-machi, Nagaoka, Niigata, JAPAN
Tel., Fax: +81 / (258) – 47.9533.
E-Mail: n_kikuchi@stn.nagaokaut.ac.jp
URL: http:// itohserver01.nagaokaut.ac.jp/itohlab/index.html

Keywords«Smart grids», «Modulation strategy», «Wide bandgap devices», «ZVS converters», «Solid-statetransformer»。

Abstract
This paper proposes a modulation method combining PWM and square-wave drive for solid-statetransformers (SSTs). Modular multilevel configurations based on input series and output parallel (ISOP)
have been widely used. The advantage of ISOP configuration is that low on-resister and low-switchingloss devices are available because the applied voltage on each cell is divided by the number of cells. For
this reason, SST based on the ISOP configuration is widely used in a medium-voltage system. However,this configuration has a problem that a high number of medium frequency devices, such as SiCMOSFET, increases the cost of SST. In order to solve above problem, a reduction method of medium
frequency devices are proposed. In the proposed method, one cell is driven with the PWM operation inorder to compensate for the harmonic component. The other cells are driven by square-wave operation.
Thus, the power factor correction (PFC) is held by different switching frequencies in each cell converter
operated.
Owing to the proposed operation, the medium frequency driving devices can be replaced with lowfrequency devices, such as Si-IGBT, for cost-saving. As the drawback of the proposed control, theconduction time is unbalanced in the square wave cells. Thus, this paper also proposes the sorting
operation to balance the output power of cells operated with square-wave drive. From the experimental
results, THD of the input current is 2.91%, the input power factor is 0.99, the maximum efficiency is
94.2% at 0.3p.u.(1.p.u.=1.0 k W).

Introduction
In recent years, the smart grid has attracted much attention due to the increasing demand for renewable
resources. The solid-state transformer (SST) is known as a critical component in the smart grid system.
SST consists of power converters and a medium frequency transformer for galvanic isolation. The power
converter provides power flow control and compensation of the reactive power. The medium frequency
transformer enables to increase the power density of the converter.
Focusing on the circuit topology of SST, various circuit topologies have been proposed in this decadefrom the view of efficiency, cost, and protection functions [1-20]. In [8-9], the ISOP configuration basedon the PWM rectifier and dual active bridge has been proposed. The advantage of this topology isachieving soft-switching in a wide load range. However, a lot of switching devices are required for themultistage cell. Also, the DC link capacitor with a large capacity is needed in order to keep the DC-link
voltage in the primly side. In [10-11], AC/AC-based ISOP configuration to reduce conversion stage andpassive component has been proposed. This topology increases the number of components because theconverter needs bidirectional switches. For these topologies, SiC-MOSFETs have been widely usedbecause of them high-switching speed and low on-resistance. The use of SiC-MOSFETs has a problem
with the cost of the SiC devices. The SiC devices are still more expensive than Si-IGBT, even if thedemand for SiC devices is increased.

In this paper, the hybrid modulation method for ISOP is proposed in order to reduce the cost of SST.
The new modulation method is that one of the cells is driven with PWM in order to compensate for the
harmonic components of the input current. The other cells are driven by square-wave operation in order
to correct the input power factor. It is possible to use the devices with the slower switching speed because
these switches are operated at the double of the grid frequency. It will contribute to the cost-saving
because Si-IGBT will be an option for these cells.
Besides, the proposed method causes the unbalance of the power loss among the cells operated withthe square-wave operation due to the different conduction time of switching devices. Therefore, thispaper also proposes the soring operation, which improves the unbalance of power loss among squarewave cells. The new contribution of this paper is reducing the cost of SST by replacing the highfrequency wide-bandgap devices to low-cost Si devices, in which only low-frequency operation isavailable.

Circuit configuration
System configuration
Figure 1 shows the circuit configuration of the single-phase SST with multiple cells. Each cell has
PFC stages and isolated resonant DC/DC converter. The input of the PFC stage in the cells is connected
in series. The outputs of the isolated resonant DC/DC converters, which ensure the galvanic isolation[16], are connected in parallel. The input diode rectifier is common for all cells to reduce the number ofcomponents. The high-frequency operation contributes to minimizing the isolation transformer. The
transformer of the isolated resonant DC/DC converter is smaller than the conventional commercial
frequency transformer because the switching frequency fsw_re is higher than the grid frequency. Besides,
the resonant capacitor Cr is connected to the primary side of the isolated transformer in series for thezero-voltage switching (ZVS) of the DC-DC converter with open-loop control. For the ZVS operation,
the leakage inductance is designed to be negligibly smaller than the excitation inductance.
Cell No.1(PWM Drive)
Resonant DC/DC Converter

PFC

Sdcdc11
Lb

Sdcdc21 Sdcdc31
Lr

sw1

N1:N2

C1

vin1

C2

Vout

Sdcdc12sw2

Cr

Sdcdc22 Sdcdc32

Cell No.2(Square wave drive)
vconv

Lr

sw3

N1:N2

C1

sw4

Cr

Cell No.m
Square wave drive

Fig. 1. Circuit configuration of the single-phase SST.
The new modulation method is applied into the PFC stage.

Conventional control of PFC stage
Figure 2 shows the block diagram of the conventional control method of the PFC stages. The
conventional method controls output voltage with PWM for all cells. The overall PFC circuit controls
output voltage and phase and amplitude of the input current to correct the input power factor. The phaseof the inductor current is detected from the grid voltage. The output voltage of the overall cell converter
is equally divided into each cell. Note that the phase-shifted carrier is used to reduce the current ripple.

The reference of the input current is a full wave rectified sine wave because the current reference is fed
to the inductor on the PFC stage. The current reference is multiplied by the phase, which is generated
by PLL of the grid voltage. The operation value of PI control is the total voltage of all cells. Thus, thevoltage divided by the number of cells is the reference voltage for each cell. The switching timing of the
PFC stage is shifted in each cell using the phase shift-carriers. Hence, the equivalent switching frequency
is increasing in proportional to the number of cells. Equivalent switching frequency feq is given byf eq  mf sw _ pfc(1),
where fsw_pfc is the switching frequency of the PFC stage in each cell.
Figure 3 shows the switching pulse generation of the secondary-side rectifier. The full-bridge
converter on the secondary side operates as a synchronous rectifier. The switching pulse is the same as
the pulse of the primary side. In the primary side, resonant current ire is positive when Sdcdc11 , Sdcdc21,
Sdcdc32 are turn-on. Note that phase of primly side resonant current is a little different in order to designresonant DC/DC converter. Similarly, Sdcdc12, Sdcdc22, Sdcdc31 are turn-on when the resonant current isnegative.
Boost inductor
current control

DC-link voltage control
Vdc*

+
vdc

PI

+
+

Vout
Vin

+

✕

-

ABS

Ioutu

iLuv

PI

-

1
m

+
vduv

÷
Vdc
1
0

Sin

qgrid
PLL
vin

+
-

Spfc11
Spfc12

fsw_pfc÷Phase-shifted Vdc
1carrier0+-

Spfcn1
Spfcn2

fsw_pfc

Duty of isolated resonant
DC-DC converter
0.5

+
-

Sdcdc11
Sdcdc12+
1
0

Sdcdcn1
Sdcdcn2fsw_llc

Fig. 2. Control diagram of conventional method in single-phase SST.

ire

Sdcdc11
Sdcdc21,Sdcdc32
Sdcdc12
Sdcdc22,Sdcdc31
Fig. 3. Pulse generation for secondly side rectifier

Proposed modulation method of PFC stage
Control with square-wave opearion
Figure 4 shows the relationship between the input voltage and output voltage of cell #1-3. The one ofcells #1 is driven by the PWM operation in order to compensate for the harmonic component of othercells. The other cells #2 and 3 are driven by the square-wave operation. The output voltage of the cell
operated with square wave is determined by the comparison with the reference voltage of the PFC stage
and the DC-link voltage of each cell. The switching device on the upper arm of cell #2 sw3 turns onwhen the output voltage reference vinv is higher than DC-link voltage of cell #2. Similarly, the switchingdevice on the upper arm of cell #3 sw5 turns on when the output voltage reference is higher than the sumof DC-link voltages of cell #2 and #3. Thus, the output voltage of the cell #2 and #3 is double the gridfrequency.
Figure 5 shows the block diagram with the proposed modulation. The PFC stage of one cell converter
is driven by PWM to compensate the harmonics component of the input current. The output value of the
PI controller is the total output voltage of all the cell converters. Thus input voltage of cell #1 vin1 isgiven by(2),
vin1  vin  vdc 2 Ssqr11  vdc3 Ssqr 21
where vdc2 and vdc3 are the DC-link voltage of cell #2 and cell #3, respectively. Moreover, Ssqr11 and Ssqr21
are the switching states of the PFC stage of square-wave cells. The current controller compensates forthe output voltage of the square-wave cells with feed-forward control.
V
Output vol.(Cell.3)

Threshold vol. |Vconv|

Output vol.(Cell.2)

vdc2 + vdc3

Output area(Cell.1)

vdc2
0
sw3
1

Time

s

0
sw5
1

Time

s

Time

s

0

Fig. 4. Operation principle of proposed method.
Boost inductor
current control

DC-link voltage control
Vdc*

+
vdc

PI

+
+
Ioutu

Vout
Vin

+

✕

-

ABS

PI

iLuv

Sin

qgrid

-

Duty of isolated resonant
DC-DC converter

vinv
+
vduv

+
vdc2
+

vdc2+vdc3

÷

-

+
-

vdc
1
0

vdc2,vdc3

PLL

Spwm1

0.5

Sdcdc11
Sdcdc12+-

fsw_pfc

Selection condition ofMultiplexer

vin

+
-

Spwm2

+
-

vdc2

1
0

Sdcdcn1
Sdcdcn2fsw_llc

Ssq11
Ssq12

+
-

vdc2+···+vdcn
vconvn

Ssqn1
Ssqn2

Fig. 5. Control block diagram with proposed method.
Only one cell is operated by PWM. Others output square wave.
Table I shows the comparison of the numberof switches between the proposed strategy andconventional strategy. As shown in Table I, thenumber of SiC devices is reduced by 25%
compared to the conventional strategy.
Therefore, the proposed strategy is effective in
improving the cost.

Thermal balancing control

Table I. Comparison of SiC-MOSFET and
Si-IGBT device between conventional
strategy and proposed strategy.
Rated voltage

Number of cell

3.3 kV
1.7 kV
1.2 kV611
16

Number of switching devices
Conventional
Proposed
SiC:52

SiC:40, Si:12

SiC:92

SiC:70, Si:22

SiC:132

SiC:100, Si:32

In the proposed method, the output power of
each cell is unbalanced because the conduction time between the upper arm and the lower arm of the

PFC stage is different in each cell. It may accelerate the aging of capacitors or switching devices andshorten the running time of a specific cell by concentering power loss.
Figure 6 shows the sorting operation with a PWM cell and five cells operated by square-wave drive.
When the sorting operation is not worked, the output power of cell #2 is the largest in the all cell, andthe output power of cell #6 is the smallest in all cell. It causes the problem that the advantage of the
ISOP configuration is disappeared from the view of equally sharing load in each cell.
The proposed modulation has the freedom on the option which cell output in the long term. Therefore,
the cell is selected to average the conduction time by the sorting operation. The sorting operation has
five modes in five square-wave cells. First, the cell #2 output the maximum power, and #6 output theminimum power in the mode I. Second, the operation mode is shifted to mode II. The cell #6 outputs
the maximum power and the cell #5 outputs the minimum power. Similarly, the mode is shifted insequence from I to V. The average output power of each cell is balanced in 2.5 times of the output grid
period.
V
Threshold vol.

|Vin|

vdc2 + vdc3 + vdc4 + vdc5 + vdc6
vdc2 + vdc3 + vdc4 + vdc5
vdc2 + vdc3 + vdc4
vdc2 + vdc3
vdc2

mode II

mode I Cell.6

mode IIImode Vmode IV

Cell.5Cell.4Cell.3Cell.2

0

phase

rad

Fig. 6. Sharing input voltage in sorting operation with proposed method (m = 6).

Table II. Sorting operation of square wave cell with proposed method.
3

3

4

4

5

5

6

i=2

i=2

i=2

i=2

i=2

i=2

i=2

vdc2< |vin| < S vdci Svdci < |vin| < Svdci Svdci < |vin| < Svdci Svdci < |vin| < Svdci
mode I
mode II
mode IIImode IV
mode V

Cell.2Cell.6
Cell.5Cell.4Cell.3Cell.3Cell.2Cell.6
Cell.5Cell.4Cell.4Cell.3Cell.2Cell.6
Cell.5Cell.5Cell.4Cell.3Cell.2Cell.6

6

Svdci < |vin|

i=2

Cell.6
Cell.5Cell.4Cell.3Cell.2

Simulation and Experimental Results
Simulation result of balancing control in conduction loss
In this section, the simulation result of the sorting operation is shown. Table III presents thesimulation conditions. In this simulation, a constant voltage source of 200 V is used as the primary side
DC link voltage of each cell because of evaluating the effects by eliminating the power ripple of DClink voltage. The switching devices for cell driven by PWM is SiC-MOSFET (Rohm, SCT3040KR)[21].
The switching devices for the cells driven by square-wave is Si-IGBT (Fairchild, FGA20N120FTD)[22].
Figure 7 shows the simulation result with or without sorting operation. In this simulation, cell #1 isdriven by PWM, and cell #2-6 are driven by square-wave. The conduction loss of each cell is given byt(3),
Pcon _ PFC  f sw  d  iout vce dt
t
off

on

where fsw is the switching frequency of PFC in each cell. d is the duty ratio of PFC. The current iout is
RMS value of input current. vce is the corrector-emitter voltage of IGBT. The relationship between
collector-emitter voltage is approximated asvce  v0  roniout(4),
whereas v0 is the corrector-emitter voltage at zero current of corrector-emitter, ron is approximated onresistance, and iout is the instantaneous value of the conduction current.
Fig. 7(a) shows the conduction loss and switching loss without sorting operation. In the cell #2, theconduction loss of FWD is dominant because the conduction time of the upper arm is the longest in allcells. In contrast, in cell 6, conduction loss of lower IGBT is dominant because the conduction time of
the lower arm is the second-longest in all cells.
Fig. 7(b) shows the simulation result of loss analysis with sorting algorism. Meanwhile, the power
loss of cells #2-6 is 16.7 W. It means that conduction loss of the upper and lower arm is balanced. Notethat total loss is 83.3 W, which is equivalent to a total loss of the result without sorting operation of 83.3
W. Therefore, the loss balancing is achieved by the proposed method.

Table III. Simulation condition in sorting operation of square-wave cell.
Input voltage
Vin
800 Vrms
Rated output power
Pout
16 kVA
Rated output voltage
Vout
100 V
Switching frequency of PFC fsw_pfc
30 kHzResonant frequency
fo
50 kHzNumber of cells
m
6
Lb
4 mH
Boost inductor
Primary side capacitor
C1
48 µF
Resonant capacitor
Cr
204 nF
Leakage inductor
Lr
50 µH
Secondary side capacitor
Cout3000 µF
Trans turns ration
1:1
N1:N2
Switching device(SiC-MOSFET)
SCT3040KR
Switching device(Si-IGBT)FGA20N120FTD
25

25

83.3

83.3

Power loss[W]

20
0.18

15

2.56

9.56
Sw.loss(lower)Cond.loss(lower)

4.01

5

2.22
4.78

11.0
10

17.6

16.8

16.4

16.3

16.3

16.1

16.1

14.1

3.18

16.7
15

10

16.7

16.7

3.52

3.52

3.52

3.52

13.1

13.1

13.1

13.1

13.1

2.56

4.01
8.01

16.7

16.7
3.52

11.0

11.9

Sw.loss(upper)Cond.loss(upper)1.23

Power loss[W]

20

5
1.23
3.18

0

0
Cell 1

Cell 2Cell 3Cell 4Cell 5Cell 6

Cell 1

Cell 2Cell 3Cell 4Cell 5Cell 6(a) Simulation result of power loss without sorting operation. (b) Simulation result of power loss withsorting operation.
Fig. 7. Simulation result of power loss in each cell.

Experimental result with conventional method
Table IV shows the parameters for the experiment. The input voltage is 200 V, the rated power is 1.0
kW, and the number of cells is three. Moreover, the prototype is operated with the conventional control
block diagram, as shown in Fig. 3, and the proposed control, as shown in Fig. 5. The switching frequencyof the PWM cell in the proposed control is three-times higher than the switching frequency of theconventional control for a fair comparison.
Figure 9 shows the operation waveforms of the conventional method. Fig. 9(a) shows that the input
current THD is 2.91%, and the input power factor is 0.99. Fig. 9(b) shows that each cell is driven by
PWM against grid voltage.

Experimental result with proposed method
Figure 10 shows the operation of the proposed method. In the proposed modulation, the switchingfrequency of the PFC circuits is 30 kHz. It means that the equivalent switching frequency fsw_eq is 30
kHz. Whereas the switching frequency of the PWM cell in the proposed control method is 30 kHz forthe fair comparison. Fig. 10(a) shows the result of the proposed modulation method. The input power
factor is also 0.99. The input current THD is 2.91%. In addition, Fig. 10(b) shows the output squarewave driving in each cell with double of the grid frequency. The PWM cell compensates for the
harmonic components by the square-wave cell.
Figure 11 shows that input current THD against the rotted power with the conventional and proposed
method. PFC shows to compensate the harmonic component of input current. However, in light load,
THD of the input current exceeded 5% with both controls. Improving the THD is future work.
Figure 12 shows the efficiency characteristic. The maximum efficiency is 94.2% at a load of 0.3 kW..
The efficiency at rated load is 84.4%.

Experimental result of the sorting operation
In this experiment, the output power is measured with or without the sorting operation. Experimental
parameters are common shown in Table IV. The square-wave cell outputs in double of the gridfrequency.

Figure 13 shows the operation waveform with sorting operation. The power factor of the input current
is 0.99.
Figure 14 shows the experimental result of output power with or without the operation. The output
power of cell #1 is 242 W, the output power of cell #2 is 485 W, and the output power of cell #3 is233W without the sorting operation. It means that concentering power loss occurs at a specific cell. In
contrast, the output power of each cell is 304 W, 329 W, and 332W, respectively with the sorting
operation. It clearly shows that unbalancing output power improves.

Table IV. Experiment parameter.
Input voltage
Vin
200 Vrms
Rated output power
Pout
1.0 kW
Rated output voltage
Vout
50 V
Switching Device
SCT2080KE
fs
50 Hz
Grid Freqency
1500 µF
Primary side capacitor
C1
Resonant capacitor
204 nFCr
Leakage inductor
Lr
50 µH
Secondary side capacitor
C23600 µF
Trans turns ration
N1:N2
1:1
Number of cellsm3
30 kHzSwitching frequency of PFC fsw_pfc
Switching frequency of LLC fsw_llc
50 kHzGate-source Volatge(20V/div)

Drain-source Volatge(500V/div)time(400ns/div)

Fig. 8. Waveforms of ZVS operation in resonant DC/DC converter.
The converter achieves ZVS of upper switches on resonant DC/DC.
0A

Input Voltage(500V/div)

Input Voltage(500V/div)

0V

0V

Cell.1 Output Voltage(100V/div)
Input Current(10A/div)

0V

0A
Cell.1 –3 Output Voltage(200V/div)

0V
0V

0V

Cell.2 Output Voltage(100V/div)

4[ms/div]

Cell.3 Output Voltage(100V/div)

4[ms/div](a) Operation waveform of SST with conventional method. (b) Operation waveform of SST withconventional method.
Fig. 9. Waveforms of SST, using conventional method.
Input Voltage(500V/div)

Input Voltage(500V/div)

0V

0V
Cell.1 Output Voltage(100V/div)

Input Current(10A/div)

0A

0V
Output Cell Voltage(200V/div)

0V

Cell.2 Output Voltage(100V/div)

0V
0V
4[ms/div]

Cell.3 Output Voltage(100V/div)

4[ms/div](a) Operation waveform of SST with proposed method. (b) Output voltage of each cell with proposed
method.
Fig. 10. Waveforms of SST, using proposed method.

Conclusion
This paper has proposed the hybrid modulation method, which combines PWM and square-wave
operation for ISOP based SST. In the proposed method, one of the cells is driven by PWM in order tocompensate for the harmonic component. The other cells are driven by square-wave operation in orderto share the load. Moreover, this paper proposed the sorting operation in order to improve unbalancing
power in each cell when the proposed modulation is used. As the experimental result, the input current
THD is 2.91% at an output power of 1.0 kW whereas the input current THD of conventional modulationis 3.18%. The efficiency of the total system is 82.0% at 1.0 kW. Besides, the output power of the cellwith the square-wave operation is balanced with the sorting operation.
1p.u. = 1.0 kW

Input current THD[%]

30
24
18
Prop. method

12

Conv. method

6
0
0

0.2

0.4

0.6

0.8

1

Power[p.u.]

Fig. 11. Relationship between input current THD and input powerwith conventional and proposed modulation
100

Efficiency[%]

95

90

85

80

75
0

0.2

0.4

0.6

0.8

1

Output power[p.u.]

Fig. 12. Efficiency characteristic with proposed method.
Input voltage(500V/div)

0V
Input current(10A/div)

0A
Cell 2 Output voltage(200V/div)

0V
Cell 3 Output voltage(200V/div)0V
4[ms/div]

Fig. 13. Operation waveform with sorting operation.

1200
1000

Cell 3

Power[W]

800
600

233W

332W

485W

329W

242W

304W

Cell 2400

200

Cell 10
without sorting operation

with sorting operation

Fig. 14. Measured output power with no using sorting operation and using sorting operation.

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