Open-loop-based Island-mode Voltage Control
Method for Single-phase Grid-tied Inverterwith Minimized LC Filter
Satoshi Nagai and Jun-ichi Itoh
Department of Energy and Environment Science Engineering,
Nagaoka University of technology, Niigata, Japan*E-mail: satoshi_nagai@stn.nagaokaut.ac.jp, itoh@vos.nagaokaut.ac.jp
Abstract— This paper proposes an island-mode voltage
control method by using an open-loop control applying ahigh-gain disturbance observer (DOB) for a single-phase
inverter with a low capacitance output filter. The output
voltage is distorted with the low capacitance by theconventional method which consists of a PID regulator foran automatic voltage regulator (AVR) and a PI regulator
for an automatic current regulator (ACR). In order tocompensate the output voltage distortion, the high-gain
DOB for the output voltage is applied in the open-loopbased voltage control. DOB is implemented into a fieldprogrammable gate array (FPGA) with high-speed
sampling. In the LC filter of a 1-kW prototype, theimpedance of the inductor is minimized to 1.0% of thenormalized inverter impedance, whereas the admittance ofthe capacitor is reduced to 0.25% of the normalized inverter
admittance. By the proposed method, the inverter output
voltage total harmonic distortion (THD) is reduced by
82.4% even with the diode rectifier load compared to theconventional voltage control, whereas the constant output
voltage is achieved regardless of any conditions of load.
Keywords— Grid-tied inverter, Island-mode, Minimized
LC filter, Open-loop-based voltage control

I.

INTRODUCTION

In recent years, grid-tied inverters, e.g. photovoltaic
systems, fuel cell systems, and wind turbine systems,
have been actively studied for energy saving [1]-[3]. The
inverter is required to have a small volume in order toincrease the power density of the system [4]-[5]. Generally, interconnected inductors occupy a majority of theinverter size. Therefore, the interconnected inductor ishighly required to reduce the size. By reducing the inductance, it is possible to reduce the volume of the inductor.
A high switching frequency with SiC or GaN devices isapplied in term of a same current ripple in order to reducethe inductance of the interconnected inductor. Moreover,the capacitance of the filter capacitor is possible to reduce
due to a filter design of high cutoff frequency. Therefore,
it is possible to apply the high resonance frequency
output filter for the inverter by increasing the switchingfrequency. On the other hand, the inverter output current

overshoot rate becomes high during the voltage sag when
the inductance of the interconnected inductor is reduced.
Thus, the authors propose the high-speed gate-block
method and the design method of LC or LCL filter inorder to meet the fault-ride-through (FRT) requirements[6]-[7]. In particular, in order to meet the FRT
requirements, a filter capacitor with low capacitance isdesirably designed to reduce the resonance.
Meanwhile, when a black out in a long period that isexceeding the FRT requirements occurs, the grid-tied
inverter is required to perform the island mode operationin order to supply the power to the load [8]-[10]. In orderto output the voltage, it is necessary to implement thevoltage controller for the inverter. However, the disturbance suppression performance of the voltage controller
worsens due to the low capacitance of the filter capacitor
in the minimized LC filter. The inverter output voltage isdistorted when the island mode operation with the low
disturbance suppression performance is connected tononlinear-load such as a rectifier load. As one of thesolution for this problem, the control response of thevoltage controller and the current controller are increased
in order to enhance the disturbance suppression performance. However, the increase in the control response islimited to the detection delay time and the sampling frequency. Moreover, in order to improve the output voltage
distortion, the voltage control methods applied in such as
Uninterruptible Power Supply (UPS) systems are proposed in [11]-[12]. The operation of UPS is not necessary toconsider the FRT operation. Thus, the filter capacitor of
the output filter is possible to increase the capacitance.
The voltage control methods of [11]-[12] are not considered with the output filter of the low capacitance. Therefore, in the grid-tied inverter, the voltage control with the
low capacitance has to be considered. Moreover, it isnecessary to implement a complex control or sampling
method for the control methods of [11]-[12].
This paper proposes new open-loop-based islandmode voltage control method equipped with a high-gain
disturbance suppression in order to achieve a low total

harmonic distortion (THD) of the output voltage. The
originality in this paper is that the island-mode voltage
control with the minimized LC filter is possible tocompensate an output error voltage for the load current
without a current feedback loop. Moreover, it is notnecessary to consider the interference between the voltage controller and the current controller. This control isdefined as the VOLTAGE DISTURBANCE COMPENSATION OPEN-LOOP CONTROL (VDCOLC) in thispaper. The proposed VDCOLC compensates the load
current disturbance by using the output voltage detection
value to calculate the disturbance through a high-gain
disturbance observer (DOB) [13]-[15]. In order to compensate the disturbance with the high-speed sampling, thehigh-gain DOB is implemented in field-programmablegate array (FPGA). By using this proposed VDCOLC, a
reduction of THD for the inverter output voltage isconfirmed with a 1-kW prototype.
II.

PROBLEM OF ISLAND-MODE VOLTAGE CONTROLWITH MINIMIZED LC FILTER

Figure 1 shows a circuit configuration of a singlephase grid-tied inverter with an LC filter. In this paper,an H-bridge single-phase two-level inverter is employed
due to its simplicity. In order to reduce the volume, theLC filter is minimized. In the island mode operation, theoutput voltage is controlled by configuring the voltage
controller with the filter capacitor of the output LC filter
as the control object. The disturbance gain of the output
current iout GD(s) when the voltage controller isconstructed by PI controller is expressed ass
GD ( s ) 
(1),
Kp
2
s C f  sK p 
Tiwhere Cf is the capacitance of the filter capacitor, Kp isthe proportional gain, Ti is the integral time, s is the
Laplace operator, and the current control gain is one. The
disturbance suppression performance worsens due to theincrease of the disturbance gain, when the capacitance ofthe filter capacitor Cf is decreased in (1). Thus, it is necessary to improve the disturbance suppression performance, in order to achieve the island mode operation
with the minimized LC filter.
III.

OPEN-LOOP-BASED VOLTAGE CONTROL FOR
ISLAND MODE OPERATION

A. Current Detection Problem of Filter Capacitor
Figure 2 shows a conventional closed-loop-based
island-mode voltage control with current controller composed by PI regulator. In general, an island-mode voltage
control is carried out by a voltage controller that has
inner loop of the current controller. Note that, the disturbance suppression performance is improved by using thefilter capacitor current control [16]. The disturbance forthe voltage controller such as the load current is includedin the filter capacitor current. Thus, the disturbancecompensation for the output voltage controller is not

S1

S3
iL

iout

L
Vdc

vC
S2

iC

Cf

Load

S4

Fig. 1. Circuit diagram for island mode. In this paper, the output LC
filter is minimized.
Control System
DSP
iC*
1
PIDv
PIc
vC*
+ + Vdc
iCdet
vCdet

CircuitvC
Vdce sTd _ ce

 sTd _ v+

iout
1 iL -iC 1
sC f
sL +

vC

Fig. 2. Control block diagram of conventional closed-loop-based
voltage control for island mode operation. In order to improve thedisturbance suppression performance, the control response has to be
increased.

necessary by the filter capacitor current feedback control.
Moreover, it is necessary to increase the control response,
which is limited due to the controller hardware, in orderto achieve the island mode with the minimized LC filter.
Figure 3 shows the filter capacitor current detection
value under the same output voltage with different detection delay time of the filter capacitor current, where theimpedance of the interconnected inductor is 1.0% of thenormalized inverter impedance, the admittance of thefilter capacitor is 0.25% of the normalized inverter admittance in the 1-kW system. The detection of the filter
capacitor average current for one switching period isrequired as shown in Fig. 2. However, the filter capacitor
current has a large current ripple when the low capacitance of the filter capacitor is applied. Because theswitching frequency becomes higher than the fundamental frequency component of the output current. Thus,
it is impossible to detect the filter capacitor average
current per the switching period due to the current
detection delay time. In Fig. 3 (a) and (b), it is possible todetect the average filter capacitor current as a sinusoidal
wave, when the detection delay time is 0 s or half periodof carrier (6.25 s). However, the detection point of theoutput current is different from the average value, i.e. thefilter capacitor current detection value becomes nonsinusoidal wave, when the detection delay time of thefilter capacitor current becomes longer as shown in Fig. 3(c) as 10 s. Thus, it is impossible to detect the filter
capacitor average current due to the above problem. As aresult, the inverter output voltage THD becomes worse. It
is necessary to apply the multi-rate sampling for the
average capacitor current detection [11]-[12], in order tosolve above problem.
B. Proposed Open-loop-based Island-mode Voltage
Control
The resonance frequency of the filter is shifted to thehigh frequency range when the LC filter is minimized.

Filter capacitor current [A]Output voltage [V]400Control System
DSP

200

Filter capacitor current [A]

+

-400

Control System

0.4

FPGA *
vconv 1
+ +
Vdc
v̂dis
c

Detection delay time: 0 s

Measurement value

0.2

vc*

0.0

s  c

-0.2

+
-

0.4

10 ms/div

Detection value

Detection delay time: 6.25 s

Measurement value

0.2
0.0
-0.2
-0.4

10 ms/div

Detection value(b) Current detection delay time is half of carrier period.
0.4

Detection delay time: 10 s

Measurement value

0.2
0.0
-0.2
-0.4

Vdc

+

iout
-

1 iL - ic
sL +

vc

1
sC f

Fig. 4. Control block diagram of conventional open-loop-based
island-mode voltage control for island mode operation.

-200

-0.4

1
Vdc

fswTdeadVdcsign(vc*)0(a) Without current detection delay time.

Filter capacitor current [A]+vc*

Circuitvc

10 ms/div

Detection value(c) Current detection delay time is not half of carrier period.
Fig. 3. Comparison of filter capacitor current detection with different
current detection delay time.

The transfer function for the output voltage commandwith the open-loop operation Gcom_OL(s) is expressed as
1(2).
Gcom _ OL ( s)  2
s LC f  1
The transfer function becomes wide bandwidth for the
output voltage command vc* with the minimized LC filterby (2). Therefore, an open-loop-based voltage control canbe employed without the occurrence of the output voltage
resonance. Nevertheless, the output voltage with the
open-loop-based voltage control varies highly dependently on the load, because the output voltage is not feedback and is not regulated by the voltage controller. Furthermore, odd number harmonic components occur in the
output voltage due to the nonlinear output current, whena diode rectifier load is connected to the inverter. Therefore, it is necessary to compensate the disturbance of theoutput current in order to obtain the stable and constant
output voltage regardless of the load.
Figure 4 shows the conventional open-loop-based
island-mode voltage control with the typical dead-timecompensation. The output voltage error due to the deadtime error voltage is compensated by using this method.
However, the harmonic components due to the nonlinearload such as the diode rectifier cannot be compensated.
Figure 5 shows the proposed VDCOLC. In order toachieve the high-gain compensation, the compensator iscCircuit
vc
-

Vdc

vcdet

s  ciout+e

1 iL - ic 1
sC f
sL +

vc

 sTd _ v

Fig. 5. Control block diagram of proposed VDCOLC for islandmode operation. In order to compensate output voltage in the highgain, the DOB is implemented in FPGA.

implemented by FPGA. Moreover, the compensator isoperated as a DOB that compensates the disturbance dueto the output current iout. The disturbance estimation
value vˆdis is expressed byvˆdis cs  c*vconv cs  c

vcdet

(3),

where c is the cutoff angular frequency of the DOB,
vconv* is the voltage command after the disturbancecompensation, and vcdet is the detection value of the filter
capacitor voltage.
C. Appling Area of Open-loop-based Voltage Control for
Island ModeIn the disturbance compensator of (3), the Low-passfilter (LPF) is implemented into DOB in order tosuppress the resonance components of the LC filter forthe voltage command in the voltage controller. The
resonance frequency of the LC filter fres_LC is expressed as
f res _ LC 

1
2 LC f(4).

In order to reduce the resonance component of the LC
filter by using LPF, the cutoff frequency of LPF isdesigned to less than 1/10 to 1/2 for the resonance frequency of the LC filter fres_LC. Thus, it is possible to reduce
the effect of the LC filter resonance. However, in order toincrease the performance of the disturbance compensator,
it is necessary to increase the cutoff frequency of LPF.
Due to the output current disturbance caused by the dioderectifier load, the odd-order harmonic components areincluded in the inverter output voltage. For instance, 11thorder harmonic wave is 550 Hz; where fundamental wave
is 50 Hz, when considering the reduction of the harmonics to 11th order for the fundamental wave of the output
voltage. Thus, it is necessary to increase the LPF cutoff
frequency of DOB higher than 550 Hz. Therefore, in order to consider the suppression of the harmonics to k order,
the proposed method is applied as follows conditionf res _ LC  
kf out  f c ,  n : 2  10, f c  c 
(5),
n
2



IV.

SIMULATION RESULT FOR PROPOSED VDCOLC

Table I shows the simulation conditions for the
proposed method. The LC filter parameter and the DOB
cutoff frequency are changed in the simulation results.
Figure 7 shows the simulation results of the proposed
method with the diode rectifier load. In Fig. 7 (a), it ispossible to suppress the inverter output voltage THD lessthan 5.0%, when the resonance frequency of the LC filter
is 10 kHz (L = 1.29 mH; %Z = 1.0%, Cf = 0.2 F; %Y =
0.25%), and the DOB cutoff frequency is 2 kHz. The LC
filter parameter is designed in order to suppress theoutput current overshoot with the low inductance during
the voltage sag [7]. In order to reduce the resonance ofthe output current at the voltage fluctuation, thecapacitance of the filter capacitor is designed to small.
The inverter output voltage THD is 1.56%. Moreover, thedesign of the DOB cutoff frequency lower than theresonance frequency of the LC filter is possible to reduce
the resonance component in the inverter output voltage.
Thus, the resonance component of the inverter output
voltage in Fig. 7 (a) does not occur, i.e. the condition ofFig. 7 (a) meets (5). In Fig. 7 (b), the resonancefrequency of the LC filter and the DOB cutoff frequency
are 2 kHz. The inverter output voltage is higher than 5%;
in addition, the resonance occurs in the inverter output
voltage. This is because the condition of Fig. 7 (b) does
not meet (5), i.e. the LC filter resonance component is

100

Disturbance gain vc/iout [dB]

where fout is the frequency of the output voltage, n is theratio for the resonance frequency of the LC filter fres_LC,
which implies the DOB cutoff frequency from 1/10 to 1/2of the resonance frequency of the LC filter. In this paper,
the resonance frequency of the LC filter is approximately
10 kHz, where L is 1.29 mH (%Z = 1.0%), and Cf is 0.2
F (%Y = 0.25%); therefore, if k is eleven, it is possible
to meet (5). Furthermore, in order to compensate 11thorder harmonic without interfering with the resonancefrequency of the LC filter, the DOB cutoff frequency is
set to 2 kHz.
Figure 6 shows the comparison of the disturbance gain
characteristics of the conventional closed-loop-based
voltage control and the proposed VDCOLC. The
controller of the conventional method is similarly
constructed as Fig. 2, where the angular frequency of thevoltage controller is 3000 rad/s, and the angularfrequency of the current controller is 30000 rad/s.
Moreover, the disturbance suppression gain is calculated
from the transfer function, where the output current iout isthe input, and the output voltage vc is the output.
Furthermore, the disturbance suppression performance isanalyzed by sweeping the frequency of the disturbance
suppression gain from 1 Hz to 100 kHz as Fig. 6. In Fig.
6, the disturbance gain is reduced with the proposed
control from 30 Hz to 1 kHz of the disturbance frequency,
which includes the harmonic components from first to
20th for the fundamental frequency of the output voltage.
Thus, it is possible to reduce the output voltage distortionby using the proposed method.

Conventional island mode

50
0
-50

Proposed method

-100
-150

1

10

100
1000
10000
Disturbance frequency [Hz]100000Fig. 6. Characteristics of disturbance gain from output current iout tooutput voltage vc. The resonance due to the controller is effected tothe output voltage distortion with the conventional method.
TABLE I. SIMULATION CONDITIONS.
Output power Pout 1 kW

Carrier fre. fcry 80 kHz
Samp. fre.
DC link vol. Vdc 380 V
fso 80 kHz
of DOB
Output volt.
vc* 200 Vrms Crest factor
3.0
commandof loadincluded in the voltage command. In Fig. 7 (c), theresonance frequency of the LC filter is 10 kHz, and the
DOB cutoff frequency is 200 Hz. The inverter output
voltage THD is higher than 5.0% in this condition. Thisis because that the disturbance suppression performanceof the DOB decreases due to the low DOB cutoff
frequency. Thus, the inverter output voltage THD isworse due to the disturbance for the diode rectifier load.
In addition, the dead-time error voltage compensation by
DOB becomes not effective enough due to the low DOB
cutoff frequency. In Fig. 7 (d), the resonance frequencyof the LC filter is 2 kHz, and the DOB cutoff frequency is
200 Hz. The inverter output voltage THD is also higher
than 5.0% in this condition. The inverter output voltage
includes the distortion due to the low resonancefrequency of the LC filter. Furthermore, the disturbancecompensation value becomes not effective enough for thediode rectifier load due to the low DOB cutoff frequency.
Thus, the inverter output voltage THD in Fig. 7 (d) ishigher than the condition of Fig. 7 (c). In conclusion, theproposed method can only be applied in the area of (5).
V.

EXPERIMENTAL RESULTS

In the experimental verification of the island mode
operation, three cases of load test are considered. The
load conditions are as follows: (A) No-load, (B) Linear
load such as resistance load, (C) Nonlinear-load such as
diode rectifier load.
Table II shows the experimental conditions. By
considering the frequency of the voltage command as 50
Hz, the angular frequency of the voltage controller for theconventional closed-loop-based island-mode voltage
control is designed to ten times of the voltage command
frequency. Thus, the angular frequency is set to 3000
rad/s. Moreover, in order to prevent the interference, theangular frequency of the current controller is designed to
ten times for the angular frequency of the voltage
controller. Thus, the angular frequency of the current

600

THD: 1.56%200

Output voltage [V]Output voltage [V]

300

100
0
-100
-200

Output current [A]

10
5
0
-5
-10
-15

10 ms/div(a) With high-resonance frequency LC filter.

Output voltage [V]

300
200

200
0
-200
-400

THD: 5.07%

100
0
-100
-200

0
-5

0
-10

100
0
-100
-200
-300
10

Output current [A]510

10 ms/div-20(b) DOB cutoff frequency and LC filter resonance frequency is same.
300
THD: 8.51%
200

-300
10

Output current [A]

THD: 26.8%

-600
20

Output voltage [V]Output current [A]

-300
15

400

5
0
-5

10 ms/div
10 ms/div-10-10(c) With high-resonance frequency LC filter and low-DOB cutoff frequency. (d) DOB cutoff frequency and LC filter resonance frequency is low.
Fig. 7. Simulation results for any condition of resonance frequency of LC filter and DOB cutoff frequency with the proposed VDCOLC. The
inverter output voltage THD is suppressed to less than 5% when (5) is met.

controller is set to 30000 rad/s. Note that the minimized
LC filter parameter is designed in order that the FRT
requirements are met during the voltage sag [7]. The
island mode operations are compared with theconventional closed-loop-based voltage control, theconventional open-loop-based island mode with the deadtime error compensation, and the proposed VDCOLC.
A. No-load Operation
Figure 8 shows the experimental result for the no-load
operation. In Fig. 8 (a), (b) and (c), the output voltage
THD of three methods are suppressed to less than 5.0%.
However, the inverter output voltage THD in Fig. 7 (a) is
high in the conventional closed-loop-based voltage
control. This is because the filter capacitor current
detection has the delay time that is different from the half
period of the carrier as shown in Fig. 3 (c). Thus, it is
impossible to detect the average value for the filter capacitor current. Therefore, the inverter output voltage is distorted in Fig. 8 (a). In particular, the distortion of theinverter output voltage with the proposed method is reduced by 70.2% compared with the conventional closedloop-based voltage control. In addition, the output voltage in Fig. 8 (a) is higher than the voltage command dueto the high gain of the current controller. In order to regulate the output voltage in Fig. 8 (a), it is necessary to
reduce the gain of the current controller. Moreover, theoutput voltage in Fig. 8 (b) is also higher than the voltage
command due to the typical dead-time compensation.
The dead-time error voltage does not occur in the no-load
operation. Thus, the output voltage increases by the deadtime compensation value. On the other hand, the output
voltage in Fig. 8 (c) is almost same compared with thevoltage command.
B. Linear-load Operation
Figure 9 shows the experimental result for the linear
load operation. In Fig. 9 (a), (b) and (c), the output
voltage THD at the rated power with three methods arealso suppressed to less than 5.0%. The inverter output

TABLE II. EXPERIMENTAL CONDITIONS.
Output power Pout 1 kW
fcry 80 kHz
Carrier fre.
DC link vol. Vdc 380 V
Samp. fre. of DSP fs 20 kHz
Output volt. vc* 200 Vrms
Angl. fre. of AVR avr 3000 rad/s
command
Inter. Induc. L 1.29 mH Angl. fre. of ACR acr 30000 rad/s(1.0%)(%Z)
Samp. fre. of DOB fso 80 kHz
Filter cap.
Cf 0.2 F(0.25%) Cutoff fre. of DOB fc 2 kHz(%Y)
Output voltage 250 V/div

Output voltage 250 V/div

THD: 3.08%0Output voltage: 209 Vrms

0

THD: 3.69%

Output current 5 A/div0

4 ms/div(a) Conventional closed-loop-based voltage control.
Output voltage 250 V/div

Output voltage: 208 Vrms

THD: 1.57%00Output current 5 A/div

Output voltage: 184 Vrms
4 ms/div(a) Conventional closed-loop-based voltage control.
Output voltage 250 V/div

0

THD: 1.83%

Output current 5 A/div0

4 ms/div(b) Conventional open-loop-based voltage control.
Output voltage 250 V/div

Output voltage: 208 Vrms

THD: 1.19%

00Output current 5 A/div

Output voltage: 203 Vrms
4 ms/div(b) Conventional open-loop-based voltage control.
Output voltage 250 V/div

0

THD: 1.10%

Output current 5 A/div0

4 ms/div(b) Proposed VDCOLC.
Fig. 9. Experimental result for linear load operation at rated load.
The output voltage THD is suppressed to less than 5.0% in both theconventional method and the proposed method.

Output voltage: 203 Vrms

0

Output current 5 A/div

4 ms/div(c) Proposed VDCOLC.
Fig. 8. Experimental result for no-load operation. The output voltage
THD is suppressed less than 5.0% in both the conventional method
and the proposed method.

voltage THD in Fig. 9 (a) is high compared with bothmethod of Fig. 9 (b) and (c), due to the same reason in
Fig. 8 (a). In particular, the inverter output voltage THDwith the proposed method is improved by 61.4%
compared with the conventional closed-loop-based voltage control at the rated load. In addition, the output voltage in Fig. 9 (a) is higher than the voltage command dueto the same reason in Fig. 8 (a). Moreover, the output
voltage in Fig. 9 (b) decreases due to the load current
compared with Fig. 8 (b). On the other hand, the output
voltage in Fig. 9 (c) is almost same compared with thevoltage command.

Figure 10 shows the output voltage THD characteristic
and the output voltage variation against the linear load. In
Fig. 10 (a), the output voltage THD with the proposed
method is reduced more effectively than with the conventional closed-loop-based voltage control. The maximum
improvement of the output voltage THD is 80.8% at loadof 0.9p.u.. Moreover, the inverter output voltage THD
characteristics with the conventional open-loop-based
island mode or the proposed method are approximately
constant compared with the conventional closed-loopbased voltage control in the load range from 0p.u. to
1.0p.u.. The cause of difference for the inverter output
voltage THD with the conventional closed-loop-based
voltage control is that the variation of the load current
causes the error of the filter capacitor average current
detection value. Due to the detection error of the filter
capacitor average current, the inverter output voltage becomes non-sinusoidal wave. Thus, the operation of theconventional closed-loop-based voltage control becomes
unstable. On the other hand, in Fig. 10 (b), the inverterOutput voltage THD [%]5.0

THD: 6.76%

Output voltage 250 V/div

Conventional closed-loop
method

4.0

0

3.0

Open-loop withdead time compensation

Output voltage: 208 Vrms

2.0
0

1.0
Proposed method
0

0

0.4
0.2
Output power [p.u.]

0.8
0.6(1.0 p.u. = 1 kW)

Output current 10 A/div

1.0(a) Output voltage THD characteristic with linear load.
215

4 ms/div(a) Conventional closed-loop-based voltage control.
THD: 6.75%

Output voltage 250 V/div

Conventional closed-loop method

Output voltage [Vrms]

210
205

0

Proposed method200

Output voltage: 205 Vrms

195
Open-loop withdead time compensation

190
185
180

0

0.2
0.4
Output power [p.u.]

0

0.6
0.8
(1.0 p.u. = 1 kW)

Output current 10 A/div

1.0(b) Output voltage variation with linear load.
Fig. 10. Relationship between output voltage and resistive load in 1kW system. By the proposed method, the output voltage THD is better than other two method. In addition, the output voltage is constant.

output voltage with the conventional closed-loop-based
voltage control is almost constant in the load range from
0p.u. to 1.0p.u.. This is because the voltage controller
regulates the inverter output voltage. However, the output
voltage with the conventional open-loop-based voltage
control varies significantly depending on the load. This isbecause that the inverter output voltage decreases due tothe decrease of the filter capacitor current by the load
current. On the other hand, the output voltage with theproposed method is constant. In the proposed control,
DOB uses the detection value of the output voltage inorder to estimate the output current and then compensate
for the disturbance of the output current. On otherperspective, the output voltage is indirectly regulated by a
feedback loop in DOB. Therefore, it is possible toachieve that the inverter outputs the constant voltage
during the island mode with the linear load in the
proposed method.
C. Nonlinear-load Operation
Figure 11 shows the experimental result for the
nonlinear-load operation. The diode rectifier is applied as
nonlinear load. The crest factor of the diode rectifier load
is approximately 3.0. The output voltage THD is higher
than 5.0%, when using the conventional closed-loopbased voltage control and the conventional open-loopbased island mode as in Fig. 11 (a) and (b). The inverter
output voltage with the conventional closed-loop-based
voltage control distorts due to the reduction of the
disturbance suppression performance by the low capacitance of the filter capacitor and the error of the filter

4 ms/div(b) Conventional open-loop-based voltage control.
Output voltage 250 V/div

THD: 1.19%0Output voltage: 203 Vrms

0

Output current 10 A/div

4 ms/div(c) Proposed VDCOLC.
Fig. 11. Experimental result for diode rectifier-load operation. By
using the proposed method, the output voltage THD is reduced to
1.19% with the nonlinear-load.

capacitor average current detection. In particular, thedisturbance compensation is not effective enough for the
output current control with the nonlinear load. Moreover,the inverter output voltage with the conventional openloop-based island mode also distorts due to the nonsinusoidal output current which flows during the output
voltage peak. On the other hand, by using the proposed
method as in Fig. 11 (c), the output voltage THD is lessthan 5.0%. It is possible to compensate the drop voltage
due to the open-loop-based operation with the high-gain
DOB in the proposed method. Thus, the inverter output
voltage becomes sinusoidal wave even with the dioderectifier load. Therefore, it is possible to suppress theoutput voltage THD by using the proposed method.
Figure 12 shows the THD characteristic and the output
voltage variation against the nonlinear-load. In Fig. 12 (a),the output voltage THD with the proposed method is
reduced more effectively than with the conventional
closed-loop-based voltage control or the conventional
open-loop-based voltage control. The maximum

VI.

CONCLUTION

This paper proposed the open-loop-based island-mode
voltage control with the high-gain disturbancecompensation when the LC filter is minimized. Moreover,
the applying area of the proposed method is clarified by
the DOB cutoff frequency and the resonance frequencyof the LC filter. By using the proposed method, theoutput voltage is constant in the island mode during
regardless of any conditions of load. Furthermore, theoutput voltage THD with the proposed method is
suppressed to less than 5.0%. In particular, the output
voltage THD was improved by 82.4% compared with theconventional closed-loop-based voltage control when the
nonlinear-load was connected. Therefore, the proposed
method was confirmed to the utility for the island modewith the minimized LC filter.
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Output voltage THD [%]8.0

Output capacitance of rectifier
7.0 : 1300 F
6.0
Conventional closed-loop
method

5.0
4.0
3.0
2.0

Open-loop withdead time compensation
Proposed method

1.0
0
0.1

0.2
0.3
0.4
0.5
0.6
Output power [p.u.] (1.0 p.u. = 1 kW)

0.7(a) Output voltage THD characteristic with nonlinear-load.

Output voltage [Vrms]

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load, or light/heavy load.

212
Output capacitance of rectifier: 1300 F
211
210
Conventional closed-loop
method
209
208
207
206
205
204
203
202
0.1

Open-loop withdead time compensation
Proposed method

0.2
0.3
0.4
0.5
0.6
Output power [p.u.] (1.0 p.u. = 1 kW)

0.7(b) Output voltage variation with nonlinear-load.
Fig. 12. Relationship between output voltage and rectifier load in 1kW system. By using the proposed method, the output voltage THD
is suppressed to less than 50%. Moreover, the output voltage isconstant.
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