電気学会論文誌●（●●●●●●●部門誌）
IEEJ Transactions on ●●●●●●●●●●●●●●●
Vol.●● No.● pp.●-●●
DOI: ●.●●/ieejeiss.●●.●

Paper

Development of Solid-State Transformer for 6.6-kV single-phase gridwith Automatically Balanced Capacitor Voltage
Jun-ichi Itoh＊a), Senior member, Kazuki Aoyagi＊, Non-member,
Keisuke Kusaka＊, Member, Masakazu Adachi＊, Student member(Manuscript received Jan. 00, 20XX, revised May 00, 20XX)
This paper proposes a solid-state transformer (SST) for a 6.6-kV single-phase grid using multiple cells, which have a power
factor correction stage and an isolated DC-DC converter. In the SST, the capacitor voltage of each cell is automatically balanced
on a primary side owing to the use of a resonant DC-DC converter. The main topic of this paper is calculating the fundamental lossof the proposed topology assuming a 6.6-kV single-phase grid. From the calculation, the maximum efficiency of the full model
SST reaches 99%. The scaled model with an input voltage of 1320 V, which is 1/5 of the full model, is tested to confirm thecalculation of the power loss and fundamental operation. As a result, it is confirmed that the input current is sinusoidal and a total
harmonic distortion is 4.3%. Moreover, the automatic capacitor voltage balancing capability is tested. The capacitor voltage oneach cell is automatically balanced without any control for voltage balance. Besides, the bidirectional operation is verified. Finally,
the power loss of the proposed topology is separated into each conversion part. The power loss shows a good agreement with thecalculation with an error of less than 5%.
Keywords : Solid-State Transformer, Power factor correction converter, Resonant DC-DC converter, High-frequency transformer

1.

attention(7–9). SSTs achieve significant volume reduction of theconverter in comparison with the low-frequency transformer byhigh-frequency switching using the characteristics of wide-bandgap
semiconductors, e.g., silicon carbide (SiC) and gallium nitride(GaN) devices (10). Moreover, the use of high-frequency transformer
for isolation and the step-down function provides the advantage to
the SST in terms of the downsizing. SST has the following
advantages in consequence(11):•AC voltage adjustment•
DC voltage output•
Reduction in size and weight of the system•
Active and reactive power control•
Low harmonics components in AC side
Furthermore, the converters with cells based on multilevel
topologies have advantages because it enables to reduce therequired voltage rating of the switching devices. Thus, theswitching devices with low on-state resistance and high-speed
switching can be used. In addition, the switching frequency isequivalently increased by the multilevel topology. Thus, the size ofthe inductors in the converter can also be reduced(12).
One of the problems of the multilevel topology is the number ofswitches. The number of switches greatly increases owing to themultiple cells. In addition, the control system driving the main
circuit will be complicated since the number of the gate signal will
be increased with an increased number of the switch(13). Moreover,a balance control for each capacitor on the cells must be employedin the multilevel converters such as a modular multilevel converter(MMC)(14). The balance control may cause an unstable if a feedback
control has a delay due to isolation or signal transmission (15).
Furthermore, the DC link capacitor with a large capacitance isrequired to maintain the capacitor voltage on each cell(16).
This paper proposes a simple circuit configuration of the single-

Introduction

In recent years, DC distribution systems have been actively
studied to save the power consumption of data-centers or large
buildings(1-2). The DC distribution systems have a capability ofdownsizing and efficient conversion in comparison with an AC
distribution system because the number of power conversion will
be decreased(3). In such a DC distribution system, a 6.6-kV AC gridis employed as one of the power sources.
A transformer is employed for the DC distribution system with
the AC power grid for achieving the step-down from 6.6 kV to the
distribution voltage of several hundred volts. The transformer plays
a role as galvanic isolation between the DC distribution system andthe AC power grid (4–5). Generally, the conventional transformer
which is used at the grid frequency, e.g., 60 Hz or 50 Hz is bulky
and heavy.
As one of the solutions to downsizing the isolation stage, atransformer-less PWM converter is proposed (6). The high voltage
IGBTs with the voltage rating more than 4.5 kV are required in afive-level diode-clamped converter. The five-level diode-clamped
converter requires the balancing circuit as the auxiliary circuit inorder to balance the capacitor voltage in the DC link. Besides, thefive-level diode-clamped converter is operated with a low switchingfrequency because the loss of high voltage rating devices is large
compared to low voltage rating devices. The operation in lowswitching frequency results in large passive components because
harmonic distortion of input current and voltage ripple of output DC
voltage should be suppressed.
As another solution, solid-state transformers (SST) have mucha) Correspondence to: Jun-ichi Itoh. E-mail: itoh@vos.nagaokaut.ac.jp＊
Nagaoka University of Technology.
1603-1, Kamitomioka-machi, Nagaoka, Niigata, Japan 940-2188© 200● The Institute of Electrical Engineers of Japan.

1

SST with Automatic Capacitor Voltage Balance Capability (Jun-ichi Itoh et al.)Primary side rec.

Cell No. 1

Snubber
circuit

PFC converter
Lb

S1

Cout

Resonant DC-DC converter Secondary side rec.

Spfc11
Sllc11
C1

S3
Spfc12vin

S7

S5
N1 : N2

Ls
Vdc1

Vout

Sllc12

S6

S8

Cs
Veq
S2

S4

Csnb
Rsnb

Cell No. 2
Cell No. 3

Fig. 1.

Circuit configuration of proposed bidirectional single-phase SST.

phase SST. The proposed SST has the automatic voltage balancing
capability without a complex voltage balance control with a small
primary side capacitor. In the proposed SST, the number of devices
is smaller than the conventional SST because a single-phaserectifier is employed for all of the cells. Moreover, the effect of
reducing the number of devices increases according to the numberof cells. The originality of this paper is proposing the new topologyof the SST, which has an automatic voltage balancing capability
using an open-loop controlled resonant DC-DC converter. By
connecting the resonant DC-DC converter with an open-loop
control in parallel on the secondary side, the DC-link voltage oneach cell is automatically balanced. Thus, a small capacitor on the
primary side in comparison with the conventional SST is usedbecause the proposed circuit decouples a power pulsation at twice
the grid frequency in the secondary side. The proposed SST in thispaper makes the control simple. The proposed SST has been tested
with a unidirectional miniature model with the input voltage of 200
V. The fundamental operation had been demonstrated in (17) byauthors. In this paper, the proposed SST is experimentally tested
under a derated voltage of 1320 V, which is 1/5 of the full model.
Moreover, the bidirectional operation is demonstrated in this paper.
Additionally, the equations for a calculation of the power loss isderived for separating the power loss of the proposed SST. The
validity of the equations is confirmed with the experimental resultwith the prototype. Then, the proposed SST is designed for a 6.6kV grid as the input voltage.

2.

Table 1. Comparison of switching device between
conventional SST and proposed SST.
Number of Switching devices
Conventional SST
Proposed SST(PWM rec. + DAB)

Rated Voltage

Number of cell

3.3 kV672

1.7 kV

11

132

92

1.2 kV

16

192

132

52

each cell, the resonant DC/DC converter is employed. The resonant
DC-DC converter is operated in high-frequency for the downsizing
the transformer. Moreover, the duty ratio of the resonant DC-DC
converter is operated in fixed duty. Thus, the switching loss is small
by the zero-current switching.
In general SST topology, a large capacitor should be used in the
primary side as the DC-ling capacitor to smooth the DC-link
voltage. By contrast, small capacitors are used because theproposed circuit decouples a power pulsation at twice the gridfrequency in the secondary side in this system.
Table 1 shows the comparison of the number of switches between
the conventional SST, which includes a PWM rectifier and a dual
active bridge converter(18) and the proposed SST and. Note that the
number of cells is calculated from each rated voltage of the switcheswith considering the voltage margin. As shown in Table 1, thenumber of devices is reduced by 30% in comparison with theconventional SST because the proposed SST save the number ofswitched using one rectifier on the primary side. Consequently, theproposed circuit increases the utilization rate of the circuitcompared to the MMC.
2.2
Control system
Figure 2 shows the control block
diagram of the proposed SST. The control block diagram has an
automatic current regulator (ACR) for the current control of theboost inductor. The ACR controls the inductor current into full wave
rectified waveform synchronized with the rectified input voltage toachieve a PFC operation. The inductor current command IL* is givenbyThe system configuration of Proposed SST

2.1 Circuit configuration
Figure 1 shows the circuit
configuration of the proposed SST. At the primary side, the fullbridge rectifier with switches with the high-voltage rating isconnected. These switches are switched at the grid frequency, so thehigh-voltage switched can be used even if the switching speed of
the high-voltage switches is slow. The characteristic of the proposed
topology is the SST has the full-bridge rectifier in the input stage.
The power factor correction (PFC) is ensured by the full-bridge
rectifier and each chopper cell connected in series. The PFC circuit
controls the input current to the sinusoidal waveform with the unity
power factor. For this reason, the voltage per cell is reduced.
Consequently, it is possible to apply the switching device with a low
voltage rating and low on-state resistance on the primary side. In

I L*  I amp sin(t ) 
where Iamp is the amplitude command value of the boost inductor
current. The inductor current command IL* is generated by the

2

IEEJ Trans. ●●, Vol.●●, No.●, ●●●SST with Automatic Capacitor Voltage Balance Capability (Jun-ichi Itoh et al.)

I L*
vin

PLL

Sin

×

ABS

Boost inductor
current control
(ACR)
+
P
-

+

1
m

÷

+
-

Vc1
IL

Vd

NOT

Spfc11
Spfc12

NOT

Spfcm1
Spfcm2

1
0

÷

+
-

Vcm
Phase-shifted 10carrierFig. 2.

Control block of PFC converter in proposed circuit.

multiplication of Iamp and the full-wave rectified waveform in phaseto the input voltage.
The gate signal for PFC is generated by phase shifted carriers ofa triangular wave. Thus, the input voltage is equally divided
because the switching timing is different. In addition, low voltage
switches can be used. Note that the ripple current is reduced because
the inductor voltage is reduced by the series connection in the PFC
converter. Then, the phase shift angle θ is given by

2k (k  0, 1,
m

vin

Vthp
Vthn

S1, S4, m  1) 
S2, S3

Meanwhile, the proposed topology does not need the balance
control of the capacitor on the primary side Vdc1. The voltage of the
primary side capacitor may be imbalanced owing to a difference oftransient response or variation of capacitances in general multilevel
topology. However, DC-link voltage of each cell is automaticallybalanced because the resonant DC-DC converters, which isoperated with the constant duties are connected in parallel on thesecondary side. Consequently, the capacitor voltage on the primaryside is naturally clamped by the voltage, which is determined by theturn ratio and the secondary voltage because the cell with high DClink voltage will supply much power than the cell with low voltage.
Thus, capacitor voltage management on the high-voltage side is not
required.
Figure 3 shows the switching pulse generation of the primary side
rectifier. The switching pulse is generated by comparing the input
voltage vin and the thresholds voltage of positive/negative (Vthp/Vthn).
The switching states are the following:•vin > Vthp
Switches S1 and S4 are a turn-on
Switches S2 and S3 are a turn-off•
vin < Vthn
Switches S2 and S3 are a turn-on
Switches S1 and S4 are a turn-off•
Vthn < vin < Vthp
All of switches S1, S2, S3, and S4 are a turn-off
During the period, all of switches S1-4 are a turn-off, the input
current commutates into the body diode of MOSFETs in the power
running operation. In contrast, the current flows to the snubber
circuit during the regeneration mode.
Table 2 shows the switching state of the rectifier on the primaryside, the resonant DC-DC converter, and the rectifier on thesecondary side. In the rectifier on the primary side, the switchingfrequency is the same as the grid frequency in order to achieve thepolarity inversion. In the resonant DC-DC converter, the switchingfrequency is set to the resonant frequency for the ZCS operation,

Fig. 3. Pulse generation for primary side rectifier.

Table 2. Switching mode ofresonant DC-DC converter and rectifier.
S 1 ~ S4
Switching frequency

50 Hz

Duty ratio

Sllc11 ~ Sllc12

S 5 ~ S8

50 kHz (= fo)50%

and the switches are modulated with a duty ratio of 50%. Hence,
the resonant DC-DC converter is operated with the open-loop
control with constant duty. Thus, the control is simple in this systembecause the current control is achieved by only the switches of PFC(Spfc). In the rectifier on the secondary side uses the synchronizedswitching pulse with the resonant DC-DC converter.

3. Design of Proposed SST
3.1
Snubber circuit
A snubber circuit is used for boththe powering operation and the regeneration operation in the
proposed SST. During the regeneration operation, the continuous
current flow is ensured by the snubber circuit. In other words, theboost inductor current commutates into the snubber circuit during
the dead time. The snubber circuit has to absorb all energy stored in
the boost inductor when all of the switches are a turn-off with anover-current detection. Thus, the capacitor of the snubber circuit
should be larger as expressed by

Csnb 

2
Lb I max
V 2

where V is the voltage rise of the capacitor, and Imax is current at
an over-current detection. The resistor of the snubber circuit isgiven by

3

IEEJ Trans. ●●, Vol.●●, No.●, ●●●SST with Automatic Capacitor Voltage Balance Capability (Jun-ichi Itoh et al.)Rsnb 

2Vclamp 2
2
b max

LI

f sw _ rec

Table 3. Circuit parameter of proposed SST forthe miniature model

where Vclamp is the clamp voltage, fse_rec is the switching frequencyof the rectifier on the primary side. The clamp voltage is designed
to have a margin concerning the rated voltage of the device. In theminiature model SST, the margin is 20%.
3.2
Power-factor-correction (PFC) converterTheboost converter on each cell is used for the PFC operation. The
boost inductor current is controlled into full-wave rectified
waveform as same as general PFC circuit(19–20). The boost inductor
Lb in the PFC circuit is given by

2Vin
Lb 
4 f eq I Lb
where feq is the equivalent switching frequency of the output voltage
Veq, and ΔILb is the ripple current of the inductor current, and. Then,the equivalent switching frequency feq is given byfeq  m  f sw 
where fsw is the switching frequency of the PFC circuit, m is thenumber of cells. Each cell is modulated with the phase-shifted
carrier each other. Consequently, the switching frequency
component in Veq is increased in proportional to the number of cells.
Thus, the size of the boost inductor is reduced because theinductance is inversely proportional to frequency.
3.3
Resonant DC-DC converter
The galvanic
isolation is ensured by the resonant DC-DC converter (21). The highfrequency operation contributes to the minimization of the isolationtransformer. In addition, the zero-current switching (ZCS) is
achieved by the series resonance between the inductor Ls and thecapacitor Cs. ZCS greatly reduce the switching loss of the proposed
SST system.
Furthermore, the leakage inductance is designed to be negligibly
smaller than the excitation inductance. Then, the switchingfrequency fo of the resonant DC-DC converter is given by (7). From
resonance frequency, the duty ratio of the switch is 50%.

fo 

1
2 Ls Cs

Parameter
Input voltage
Rated output power
Rated output voltage
Snubber capacitor
Sunbber resistance

Symbol
vin
Pout
Vout
Csnb
Rsnb

Value
1320 Vrms
2 kW
320 V
0.2 µF
2.5 MW

Boost inductor

Lb

24 mH
(%Z = 0.87%)

Primary side capacitor
Resonant capacitor
Leakage inductor
Secondary side capacitor
Switching frequency of rec.
Switching frequency of PFC
Resonant frequency
Number of cells
Trans turns ratio

C1
Cs
Ls
Cout

Input voltage vin [2 kV/div]

Input current iin [3 A/div]

Output voltage Vout [200 V/div]
10 ms

Fig. 4.

Operation waveform at power running.


Primary side capacitor voltage Vdc1, Vdc2, Vdc3 [100 V/div]
50 ms

In the proposed SST, the operation mode is always the boost
operation with respect to the primary side voltage. Thus, the turnratio of the transformer is designed by (8).

N

fsw_rec
fsw_pfc
fo
m
N1/N2

48 µF
204 nF
50 µH
8200 µF
50 Hz
10 kHz
50 kHz
3
1.0

2Vin
N1


N 2 2mVout
0.8p.uwhere Vin is the input voltage, Vout is the output voltage, N1 and N2
are the numbers of turns for the primary/secondary side of the highfrequency transformer, and λ is the modulation index of the boost
converter.

4. Experimental Results

1.0p.u (rated power)

Fig. 5. Primary side capacitor voltage in each cell.

4.1
Power running operation
Table 3 shows the
specifications and the circuit parameters. In this experiment, thefundamental operation is tested with the prototype, which has threecells. The input voltage of the prototype is derated to 1320 V whichis 1/5 of the full model.
Figure 4 shows the waveforms of the input voltage, the input
current, and the output voltage. The operation of the miniaturemodel is confirmed. The input power factor of the proposed SST is
unity. The input current THD is 4.3% at the rated load. At the output
side, the step-down operation is achieved because the output
voltage is regulated to 320 V.
Figure 5 shows voltage changes of the primary DC-link
capacitors in each cell when the output power is changed from
4

IEEJ Trans. ●●, Vol.●●, No.●, ●●●SST with Automatic Capacitor Voltage Balance Capability (Jun-ichi Itoh et al.)Output sum voltage of each cell Veq [500 V/div]

Output sum voltage of each cell Veq [500 V/div]

20 µs

5 ms

Fig. 6(b)(a) Whole figure(b) Enlarged figure

Fig. 6.

30

95

0.95

25

90

0.90

85

0.85

Efficiency
80

0.80

75

0.75

Input current THD [%]

1.00

cosf

Input power factor cosf

Efficiency [%]100

Output voltage of all cells at power running.

1p.u. = 2 kW
20
15
10
5

1p.u. = 2 kW
70
0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0
0.0

0.70
1.0

0.1

0.2

Fig. 7.

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Output power [p.u.]

Output power [p.u.]Characteristic of efficiency and power factor.

0.8p.u. to 1.0p.u. Note that the rated power is 1.0p.u. = 2 kW. The
primary capacitor voltage is balanced in both the steady state andtransient state. Moreover, the maximum DC-link capacitor voltage
on the primary side is almost matched. Thus, it is confirmed that theDC-link capacitor voltage on the primary side is automaticallybalanced among all cells without the balancing control despite theoutput power changes.
Figure 6 shows the input voltage of all cells. From Fig. 6(a), theinput voltage is equally divided into each cell because the output
voltage of all cells forms a balanced multilevel waveform. In Fig.
6(b), it is also confirmed that the equivalent switching frequency feq
is 30 kHz. The equivalent switching frequency is determined by theswitching frequency in PFC and the number of the cells.
Figure 7 shows the efficiency and input power factor
characteristic. The maximum efficiency is 89.5% at the rated power.
The input power factor is over 0.95 with the output power from
0.5p.u. to 1.0p.u.
Figure 8 shows the input current THD characteristic withchanging the output power of the SST. Input current THD isrelatively high in the low-power region. This is because the rate of
the low-order harmonics component appears remarkably withrespect to the fundamental component because the input current is
low when the output power is low.

Fig. 8.

Characteristic of input current THD

of 200 V because of the limitation of the experimental facilities inthis experiment. The regenerative power supply is used for the
output side for the test of the regeneration.
Figure 9 shows the bidirectional operation of the proposed SST
when the operation mode is switched from the power running toregeneration at the center of the horizontal axis. It is confirmed thatthe unity power factor on the input side is achieved in both thepower running and regeneration operation. The input current THD
is 4.2% during the operation. From the waveforms of the sum of theoutput voltage of each cell, it is confirmed that the waveform isfour-level staircase voltage. Note that an equivalent switchingfrequency feq is 30 kHz. Thereby, the stable operation of theminiature model without any large distortion is achieved even when
the operation abruptly changes.
Figure 10 shows the DC-link capacitor voltage on the primaryside of three cells in the bidirectional operation. Despite the changeof the power flow, the DC-link capacitor voltage on the primaryside is balanced among all cells without the balance control evenwhen the operation rapidly changes.

5. Loss Analysis and Estimation for Full Model
The loss of SST is separated based on the components shown as
follows:(i)
Diode bridge rectifier on the primary side(ii)
Switches of PFC converter(iii)
Switches of the resonant DC-DC converter(iv)
Rectifier on the secondary side

4.2
Bidirectional operation
The miniature model istested to confirm the fundamental operation with the input voltage

5

IEEJ Trans. ●●, Vol.●●, No.●, ●●●SST with Automatic Capacitor Voltage Balance Capability (Jun-ichi Itoh et al.)I rms _ cap  Kcap ( ,  ) Iout 

Table 4 shows the switching devices for each part. In the
proposed SST, the rated voltage of 3.3 kV is used in the primaryside rectifier.
First, the primary DC-link capacitors are selected for the fullmodel. The current which flows into the electrolytic capacitor
includes not only the power ripple component but also the switchingfrequency component from the inverter. Thus, it is very impossible
to analytically derive the ripple current on the DC-link capacitor.
Thus, the capacitor ripple current is evaluated by the simulation(22).
The capacitor ripple current is the function of the output power
factor angle φ and the modulation index , which is a nonlinear
value. Then, the effective value of the capacitor ripple current isgiven by (9).

where Iout is the average value of the output current, and Kcap is thecoefficient which is obtained by the simulation.
Figure 11 shows the simulation result of Kcap. The modulationindex, which expresses the ratio of the voltage per cell and the dclink voltage, is 0.94 in the miniature model SST. Therefore, from
Fig. 11, Kcap (1.0, 0.94) is 0.83.
5.1
Primary side diode bridge
The loss of switches,
which is calculated by the on-voltage of the switch and the current
through the switch, is given by (10).

Pcon 

1 
von isw dt 
2 0where von is the on-voltage of the switch, isw is the current throughthe switch. In this case, von and isw are given by (11), (12).

Input voltage vin [300 V/div]von  ron 2
Input current iin [3 A/div]

isw  2

100 msPower running mode

Regeneration mode

Input voltage vin [300 V/div]

Input voltage vin [300 V/div]

Input current iin [3 A/div]

Input current iin [3 A/div]

Output sum voltage ofeach cell Veq [200 V/div]

Output sum voltage ofeach cell Veq [200 V/div]

Output voltage Vout [50 V/div]

Output voltage Vout [50 V/div]

10 ms

10 ms

P
sin(t ) 
Vinwhere ron is the on-resistance of the switch, P is the rated power ofSST. In (11), v0 is defined as zero because the MOSFETs are usedin the prototype. Moreover, the phase difference between the input
voltage and the input current is not considered because the power
factor is always unity. The loss of the switches in the primary side
rectifier is given by (13).

Output sum voltage of each cell Veq [200 V/div]

Output voltage Vout [50 V/div]

2

Pcon _ pri _ rec 
5.2

Bidirectional operation of proposed circuit.

100 msSwitching devices for bidirectional operation.
Part

Type

Maximum
rationSingle-phase rectifier

S1 ~ S4-

3300 VPFC converter

Spfc11~Spfc12

Resonant DC-DC
converter

Sllc11 ~ Sllc12

SCT2080KE

1200 V
40 A

Secondary side
rectifierS5 ~ S8

Current coefficient Kcap

Regeneration mode

The conduction loss of the

Circuit topology

Primary side capacitor voltage Vdc1, Vdc2, Vdc3 [20 V/div]

Power running mode1  P ron   
2  Vin 

PFC converter
Table 4.

Fig. 9.

P
sin(t )  v0 
Vin

1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0

Power factor cosf

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

modulation index 

Fig. 11. Current coefficient of output capacitor.

Fig. 10. Primary side capacitor voltage of each cell atbidirectional operation.
6

IEEJ Trans. ●●, Vol.●●, No.●, ●●●SST with Automatic Capacitor Voltage Balance Capability (Jun-ichi Itoh et al.)switches in PFC is given by

Psw _ PFC  Enom I nom Vcell m

Loss [%]

60
40
20

f sw 

0where P is the rated power, m is the number of cells, Vdc is thevoltage of the primary side capacitor, fsw is the carrier frequency, eon
and eoff are the turn-on and the turn-off energy per switching, which
are provided by the datasheet, Enom and Inom are the voltage and thecurrent under the measurement condition of the switching loss fromthe datasheet, and Vcell is the input voltage of each cell.
5.3
Resonant DC-DC converter
Only the conduction
loss is considered in this power loss calculation of switches because
the ZCS is assumed overall operation regions.
Therefore, the conduction loss is given by
2

Experiment Calculation
Power running

Experiment Calculation
Regeneration

Total loss of 3-cell
Boost inductor
Primary side rec. conduction loss
Output capacitor loss
Secondary rec. conduction loss
HF trans._iron loss
HF trans._copper loss

Inductor_iron loss
Inductor_copper loss
LLC_conduction loss
PFC_switching loss
PFC_conduction loss
Snubber loss

Fig. 12. Loss distribution result by experiment andcalculation at bidirectional operation.
(Explanatory note corresponds to each color of graph.) N  I out  I rms _ cap
1
Pcon _ LLC  Ron  2 
2
m2
 N1 
2

100% = 16.5 W

80

where IL is the RMS value of the boost inductor current on the PFC
stage.
On the other hand, the switching loss, which is assumed that it isdirectly proportional to the voltage and the current of the switch, iscalculated using

1 eon  eoff Vdc P

100% = 21.9 W

100

1Pcon _ PFC  ron I L2 
2

2

120

h = 99.0%
100

Outout capacitor

At the secondary side, the conduction loss is given by (17).

I out  I rms _ cap
1
Ron
2
m2
2

80

Loss [W]2

Pcon _ sec_ rec 

5.4
High-frequency transformer
In this subsection,
the high-frequency transformer is evaluated. As one of the power
loss on the transformer, an iron loss is calculated from the magnetic
flux density on the core. The AC magnetic flux density Bac is given
by

60

40

20

0

Vout

Bac 
4 f o Ae N

Secondary side diode rec.
High-frequency trans.
Conduction loss (LLC)
Switching loss (PFC)
Conduction loss (PFC)
Boost inductor
Primary side diode rec.

Fig. 13. Loss distribution of 6.6 kV/ 10 kW full model SST
by calculation.

where N is the turns ratio of the transformer, Ae is the effective
cross-section of the core. The core loss, which is provided in thedatasheet of the core is used for this analysis considering themagnetic flux density of the core (19). Therefore, the iron loss isgiven bythe power loss between the calculation and the experiment is lessthan 5%.
Figure 13 shows the calculation result on the power loss of thefull model SST. The power loss is calculated with assuming an
input voltage of 6.6 kV and an input power of 10 kVA. Then, thenumber of cells is 15 because the use of 1.2-kV switching devices
is assumed. From this calculation, the efficiency of the 10-kVA fullmode will reach to a 99% conversion efficiency at the rated power.
The dominant power loss is the conduction loss of the diode on thesecondary side. The proposed SST will achieve higher efficiency
by applying the synchronous rectification on the secondary side.

Piron _ loss  PcvVe 
where Ve is the effective volume of the core.
The high-frequency transformer of full model SST is designed
using Gecko MAGNETICS which uses improved-improved
Generalized Steinmetz Equation (i2GSE) for the calculation of theiron loss of the high-frequency transformer (23). The optimum coreshape, core material, and winding shape can be selected using
Gecko MAGNETICS. From the analysis of Gecko MAGNETICS,EPCOS N95 is the optimum core to minimized the transformer.
5.5
Loss distribution
Figure 12 shows the shakedownof the power loss, which is measured by the experiments andcalculation. The power loss in the powering and regeneration
operation are presented. It should be noted that the power loss isnormalized with the experimental results as 100%. The calculationshows a good agreement with the experimental results. The error of

6. Conclusion
This paper has proposed a new topology of SST. In the proposed
SST, the DC-link capacitor on the primary side is automaticallybalanced without any voltage balancing control. The power running
operation of SST is confirmed with the input voltage of 1320 V
which is 1/5 of the full model from the experimental results.
Moreover, the bidirectional operation and switch between the
powering and regenerating operation is tested. As a result, thesinusoidal waveform of the input current is obtained at the primary
7

IEEJ Trans. ●●, Vol.●●, No.●, ●●●SST with Automatic Capacitor Voltage Balance Capability (Jun-ichi Itoh et al.)(20) Y. Hayashi, Y. Matsugaki, and T. Ninomiya, ”Capacitively Isolated Multicell
Dc-Dc Transformer for Future Dc Distribution System,” IEEJ J. Industry
Applications, vol. 6, no. 4, pp. 268–277, (2017)(21) M. Sato, R. Takiguchi, J. Imaoka, and M. Shoyama: “A Novel Secondary
PWM Controlled interleaved LLC Resonant Converter for Load Current
Sharing,” IPEMC 2016, pp.2276-2280, (2016)(22) J. Itoh, T. Sakuraba, H. N. Le, K. Kusaka: “Requirements for Circuit
Components of Single-Phase Inverter Applied with Power Decoupling
Capability toward High Power Density,” 18th European Conference onPower Electronics and Applications (EPE'16), DS2a 0291, (2016)(23) J. Muhlethaler, J. Biela, J. W. Kolar, and A. Ecklebe: “Improved Core-Loss
Calculation for Magnetic Components Employed in Power Electronic
Systems,” IEEE Trans. On Power Electronics, Vol. 27, No. 2, pp.964-973,(2012)

side. Furthermore, the average DC-link capacitor voltage on the
primary side is stable and balanced among all cells despite thechange of power flow.
Finally, the power loss of each part of the system is calculated
and compared with the experimental result. As a result, the error of
the loss between the experimental result and the calculation is lessthan 5%. Using the calculation, the efficiency of the full model ofthe proposed SST is estimated that it will reach a 99% conversion
efficiency.

References
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(7)

(8)

(9)

(10)

(11)
(12)

(13)

(14)

(15)

(16)

(17)

(18)

(19)

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Jun-ichi Itoh

(Senior member) received his M.S. and Ph.D. degree
in electrical and electronic systems engineering from
Nagaoka University of Technology, Niigata, Japan in
1996, 2000, respectively. From 1996 to 2004, he waswith Fuji Electric Corporate Research andDevelopment Ltd., Tokyo, Japan. He was with
Nagaoka University of Technology, Niigata, Japan as
an associate professor. Since 2017, he has been aprofessor. His research interests are matrix converters, dc/dc converters,
power factor correction techniques, energy storage system and adjustablespeed drive systems. He received IEEJ Academic Promotion Award (IEEJ
Technical Development Award) in 2007. In addition, he also received Isao
Takahashi Power Electronics Award in IPEC-Sapporo 2010 from IEEJ, 58th
OHM Technology Award from The Foundation for Electrical Science andEngineering, November, 2011, Intelligent Cosmos Award from Intelligent
Cosmos Foundation for the Promotion of Science, May, 2012, and Third
prize award from Energy Conversion Congress and Exposition-Asia, June,
2013. Prizes for Science and Technology (Development Category) from theCommendation for Science and Technology by the Minister of Education,
Culture, Sports, Science and Technology, April 2017. He is a senior memberof the Institute of Electrical Engineers of Japan, the Society of Automotive
Engineers of Japan and the IEEE.
Kazuki Aoyagi(Non-Member) received his B.S. and M.S. degrees
in electrical, electronics and information engineeringfrom Nagaoka University of Technology, Niigata,Japan in 2016 and 2018, respectively. Since 2018, hehas been with Toshiba Mitsubishi-Electric Industrial
systems Corporation, Japan. His research interests
include Solid State Transformer.

Keisuke Kusaka(Member) received his B.S. and M.S. degrees from
Nagaoka University of Technology, Niigata, Japan in
2011, 2013, respectively. From 2015 to 2016, he waswith Swiss Federal Institute of Technology in
Lausanne (EPFL), Switzerland as a trainee. In 2016,
he received his Ph.D. degree in energy andenvironment science from Nagaoka University ofTechnology. From 2016 to 2018, he has been with
Nagaoka University of Technology as a researcher. He is currently an
assistant professor at Nagaoka University of Technology. His current
research interests include an inductive power transfer system and highfrequency converters. He received the second prize paper award in IPECNiigata 2018.
8

IEEJ Trans. ●●, Vol.●●, No.●, ●●●SST with Automatic Capacitor Voltage Balance Capability (Jun-ichi Itoh et al.)Masakazu Adachi (Student member) received his B.S. degree inmechanical and electronics engineering from Salesian Polytechnic, Tokyo,
Japan in 2016. And he has been with Nagaoka
University of Technology as a M.S. course student inelectrical, electronics and information engineering.
He is the student member of IEEJ. His researchinterests include Modular converter.

9

IEEJ Trans. ●●, Vol.●●, No.●, ●●●