Discontinuous Current Mode Control for
Minimization of Three-phase Grid-Tied Inverterin Photovoltaic System
Hoai Nam Le1* and Jun-ichi Itoh2
1 Department of Electrical, Electronics and Information Engineering, Nagaoka University of Technology, Nagaoka, Japan
2 Department of Science of Technology Innovation, Nagaoka University of Technology, Nagaoka, Japan*E-mail: lehoainam@stn.nagaokaut.ac.jp
Abstract— In this paper, a current control method of
discontinuous current mode (DCM) is proposed for a threephase grid-tied inverter in order to minimize inductors
without worsening current total harmonic distortion (THD).
In a conventional continuous current mode (CCM) control,current THD increases as an inductor value is reduced,
because a zero-clamping phenomenon occurs due to deadtime. In the proposed DCM current control, a zero-current
interval is intentionally controlled and a dead-time-induced
error voltage is simply compensated with a conventional
dead-time compensation. The validation of the control
method is confirmed by simulation and a 700W-prototype.
As simulation results, compared to the conventional CCM
current control, the current THD is reduced by 97.6% withthe proposed DCM current control, whereas the inductor
volume is reduced by 70%. In the experiments, the current
THD is maintained below 5% over load range from 0.3 p.u.
to 1.0 p.u. even when the inductance impedance is reduced
to 0.5% of the inverter total impedance.
Keywords— three-phase grid-tied inverter, continuous
current mode, discontinuous current modeI.

INTRODUCTION

In the last decade, researches on photovoltaic system(PV) have accelerated due to an increasing demand of
renewable and sustainable energy sources [1]-[3]. In the
PV system, H-bridge three-phase grid-tied inverters are
generally employed as an interface between solar panels
and three-phase grid. In such grid-tied inverters, a grid
filter is required to connect between an output of theinverter and the grid in order to filter out the current
harmonics and to meet grid current harmonic constraints
as defined by standards such as IEEE-1547 [4]. Due tothe observation that inductors in the grid filter occupy amajor volume of the inverter, an inductor value of thegrid filter is necessarily reduced in order to minimize thegrid filter as well as the inverter. However, this reductionof the inductor value implies a design of a high switchingcurrent ripple due to a high dc-link voltage to inductanceratio. This high current ripple results in a current
distortion phenomenon called zero-current clamping,where a current distortion increases notably as theswitching current ripple increases [5]-[9].
Due to the zero-current clamping effect, the deadtime-induced error voltage exhibits a strong nonlinear
behavior around zero-current crossing points. Hence,
conventional dead-time compensation methods such as,e.g. two-level approximation compensation method(ACM) [10]-[11], linear ACM [12] and three-level ACM[13]-[15], cannot compensate for this nonlinear behaviorof the dead-time-induced error voltage. Several
compensation methods for the nonlinearity of the deadtime-induced error voltage such as adaptive dead-timecompensation method
and turn-off transitioncompensation method have been proposed to deal withthis nonlinearity behavior and to reduce the zero-crossing
current distortion [16]-[17]. Nevertheless, both methods
exhibit the requirements which restrict the employment
over a wide range of application. Adjustment mechanism
parameters for the adaptive dead-time compensation must
be properly tuned for each individual system [16].
Meanwhile, accurate device parameters, e.g. parasitic
capacitances, are required for the turn-off transitioncompensation method [17].
In this paper, a current control for the three-phase gridtied inverter operated in discontinuous current mode
(DCM) is proposed in order to minimize the grid filter
without worsening the current distortion. In order to deal
with the zero-current clamping effect, the inverter isintentionally operated in DCM instead of a conventional
continuous current mode (CCM). In other words, thezero-current interval with the DCM operation iscontrolled, enabling a proper compensation for the
nonlinear behavior. Consequently, the conventional
dead-time compensation method, i.e. two-level ACM,
can be employed simply in order to compensate the deadtime-induced error voltage and reduce the current

distortion. The contribution of this paper is that the
proposed DCM current control is implemented with theconventional dead-time compensation method to simply
compensate the dead-time-induced error voltage. The
effectiveness of the proposed current control is confirmedby simulations and experiments.
II.

during a switching period Tsw is given by (1),diavg _ uL
 D1 Vdc  vuo  vvo   D2  vuo  vvo  ... (1)dt

DISCONTINUOUS-CURRENT-MODE
CURRENT CONTROL

Discontinuous-current-mode operation
Figure 3 indicates the phase clamping selection in six
cycles of traditional discontinuous pulse widthmodulation (DPWM), and the inverter output current
waveform in one switching period during 0 o-60o region.
In order to simplify the control of DCM, only two phasecurrents should be controlled, whereas the current of thethird phase is the summation of the currents of the firsttwo phases. Hence, DPWM is employed in order tosatisfy this control condition. During each 60-degree time
region in DPWM, one phase is clamped to P or N
polarity of dc-link voltage as shown in Fig. 3(a), whereas
the other two phases are modulated to control separately
two inverter output currents as shown in Fig. 3(b). Notethat D1 and D2 indicate the duty ratios of the first and thesecond intervals of the first controlled current, D3 and D4
indicate the duty ratios of the first and the second
intervals of the second controlled current, whereas D5
depicts the duty ratio of the zero-current intervals. The
duty ratios in Figure 3 are calculated as follows.
The inductor voltage of the inverter-side inductor L

0A
Current (3 A/div)
Zero-crossing distortion
Time (5 ms/div)(a) Zero-crossing distortions in inverter output currents
Current (0.5 A/div)
Time (15 ms/div)

P
wp

Vdc

N

un

vn

wn

Lf ig_u

vuo

iv

ig_v

vvo

iw

ig_w

vwo

O

Cf

Fig. 1. H-bridge grid-tied three-phase inverter. This topology is
employed due to its simple control and construction.

Zero-current clamping
due to dead time1

Dead timeunSwitching signals up0(b) Zero-current clamping effect due to dead-time
Fig. 2. Zero-current distortion phenomenon. The current distortion
increases with the high current ripple due to the dead-time.

v to Nu to P

w to Nu phasev to Pu to Nv phasew to Pw phase

0

0o
60o
120o
180o
240o
(a) Phase clamping selection in six cycles of DPWM

iu

300o

360o

w-phase current
peak ipeak_w

u-phase current
peak ipeak_uiwu-phase average
current iavg_u

w-phase average
current iavg_w

0A

iv

L iu

iu

0A

B.

vp

iw
Magnified into Fig. 2(b)A.
Zero-crossing distortion
Figure 1 depicts the H-bridge three-phase grid-tied
inverter with a LCL-based grid filter. The minimizationof the LCL filter generates a current with a high ripple in
the inductors L. The filter stage with Lf and Cf can
suppress the high-order current harmonics in order tomeet grid current harmonic constraints as defined bystandards such as IEEE-1547 [4].
Figure 2 describes the zero-crossing current distortion
phenomenon. As the current ripple increases with theminimized LCL filter, the current distortion increases
notably around the zero-crossing points due to the zerocurrent clamping effect, making the dead-time-induced
error voltage become nonlinear. Therefore, theemployment of the conventional two-level ACM justfurther increases the current distortion [17].

up

iv

iu

D1Tsw

Zero-current
interval

v-phase average
current iavg_v

D2Tsw

D3Tsw

D4Tsw

D5Tsw

Tsw

(b) Inverter output current waveform in one switching period during 0o60o region
Fig. 3. Six 60-degree time regions of DPWM and inverter output current
in DCM. In order to simplifying the DCM control, DPWM is employed,
controlling only two phase currents at the same time.

where Vdc is the dc-link voltage, vuo and vvo are the gridphase voltages. The average current iavg_u and the current
peak ipeak_u shown in Figure 3 is expressed as,i peak _ uiavg _ u ( D1  D2 ) ....................................... (2)2V  (vuo  vvo )i peak _ u  dc
D1Tsw .............................. (3)2L
Substituting (3) into (2), and solving the equation for the
duty ratios D2, then the duty ratio D2 is expressed by (4),4 Liavg _ u
D2  D1 ............................ (4)D1Tsw (Vdc  vuo  vvo )Substituting (4) into (1) in order to remove the duty ratio
D2 and representing (1) as a function of only the duty
ratio D1, (5) is obtained [18].
diavg _ u
4 Liavg _ u  vuo  vvo L D1Vdc .............. (5)dt
D1Tsw (Vdc  vuo  vvo )Substituting the differential of the inductor current
diavg_u/dt in (5) as zero and the duty ratio D1 is expressed
as in (6),D1  2

iavg _ u Lf sw (vuo  vvo )Similarly, the duty ratios D3 and D4 shown in Figure 3
can be expressed as in (8)-(9),iavg _ w Lf sw (vwo  vvo )Vdc (Vdc  vwo  vvo )................................ (8)D (V  v  v )D4  3 dc wo vo ....................................... (9)vwo  vvo
Figure 4 shows the control system of the three-phasegrid-tied inverter operating completely in DCM, whereas
Table I depicts the values for the duty calculation and theswitching signal output in each 60-degree time region.
When the grid operates normally, the inverter only has toregulate the grid current following the sinusoidal
waveform. First, the 60-degree time region is detected bydetected values of the grid phase voltage vuo, vvo, and vwo.
Then, the phase current references and the phase voltages
are distributed to input values of a duty calculation basedon the detected 60-degree time region as shown in Table
I. In the duty calculation step, the duty ratios D1-D5 areexpressed as follows. Note that the calculation of the duty
ratios D1-D5 is similar to that of the duty ratios D1-D4
shown in Figure 3.

D1  2D2 

i1_ ref Lf sw (v1  v2 )Vdc (Vdc  v1  v2 )Dead Time Compensation

Dead Time Generation Value Output
pwm1

D1
Ddeadtime

up

pwm2

D1+D2

un

Look-up
Table I
pwm3 for eachregionD1+D2+D3
Ddeadtime

vp
vn
wp
wn

pwm4

................................. (6)

Vdc (Vdc  vuo  vvo )D1 (Vdc  vuo  vvo )........................................ (7)vuo  vvo

D3  2vw
PWM Generation

D1+D2+D3+D4

where fsw is the switching frequency. Then, substituting
the differential of the inductor current diavg_u/dt in (1) aszero and the duty ratio D2 is expressed as in (7),D2 

Voltage Region Detection
vuo
Value Input
Detection of 60- Region1-6
Duty Calculation
vvo
degree time
i1_refiu_refvwo region in DPWM
D1
i2_refiv_ref Look-up
v1 Equations D2Table I
iw_reffor eachv2 (10)-(13) D3
vuregionD4
v3vv................................. (10)

D1 (Vdc  v1  v2 )........................................ (11)v1  v2

1
0

Fig. 4. Control system of the three-phase grid-tied inverter operatingcompletely in DCM. The dead-time-induced error voltage iscompensated simply when the inverter is intentionally operated in DCM
because the zero-current interval is controlled.
TABLE I
LOOK-UP VALUES FOR DUTY CALCULATION AND PWN OUTPUT.
RegionVariable

0o-60o60o-120o 120o-180o 180o-240o 240o-300o 300o-360oi1_refiu_refiw_refiv_refiu_refiw_refiv_refi2_refiw_refiv_refiu_refiw_refiv_refiu_ref

v1

-vu

vw

-vv

vu

-vw

vv

v2

vv

-vu

vw

-vv

vu

-vw

v3

vw

-vv

vu

-vw

vv

-vu

up

pwm1

1

pwm3

pwm2

0

pwm4

un

pwm2

0

pwm4

pwm1

1

pwm3

vp

0

pwm4

pwm1

1

pwm3

pwm2

vn

1

pwm3

pwm2

0

pwm4

pwm1

wp

pwm3

pwm2

0

pwm4

pwm1

1

wn

pwm4

pwm1

1

pwm3

pwm2

0

D3  2D4 

i2 _ ref Lf sw (v3  v2 )Vdc (Vdc  v3  v2 )................................ (12)

D4 (Vdc  v3  v2 )....................................... (13)v3  v2

D5  1  D1  D2  D3  D4 ................................. (14)where i1_ref and i2_ref are the first and second controlledcurrents in each 60-degree time region, and v1, v2 and v3
are the voltages corresponding to the controlled currents.

III.

SIMULATION RESULTS

Table II shows the circuit parameters to evaluate theoperation of the inverters, whereas Figure 5 depicts theinductor volume against the inductor impedance. The
inverter-side inductors L in Fig. 1 occupy a majority of
the inverter volume. Therefore, the minimization of L ismainly focused in this paper. Generally, the inductor
value is expressed as a grid filter impedance scaled to theinverter total impedance %ZL [21]. In particular, threedesigns of the grid filter impedance are evaluated. As
shown in Fig. 5, the inverter-side inductor L volume is
minimized by 70% when the inductor impedance %ZL is
reduced from 2.5% to 0.075%.
Figure 6 shows the inverter output currents and theaverage currents of the conventional CCM current control
and the proposed DCM current control at rated load withthree inductor designs from Fig. 5. As the current rippleincreases, i.e. the decrease in the inductor impedance, thecurrent with the conventional CCM current control
distorts notably around the zero-crossing points.
Consequently, the current THD increases from 1.5% to9.8% when the inductor impedance %ZL is reduced from
2.5% to 0.075%. On the other hand, when the inverter isoperated in DCM, the zero-current interval can becontrolled and the dead-time-induced error voltage can becompensated simply as shown in Fig. 4. Therefore, evenwith the minimized inductor impedance of 0.075%, thelow current THD of 0.3% is achieved with the proposed
DCM current control.
Figure 7 depicts the load step response of the proposed
DCM current control. As shown in Fig. 7(a), even under
the sudden load step between the load of 0.1 p.u. and theload of 1.0 p.u., the stable inverter operation and the

TABLE IISIMULATION PARAMETERS.
Circuit Parameter
VDC

DC link VoltagevgLine-to-line Voltage

Pn

500 V
200 Vrms

Nominal Power

3 kW

fg

Grid Frequency

50 Hz

Zb

Total Impedance

13.3 W

fsw

Switching Frequency

40 kHzTdeadtime

Dead-time

500 nsL1

1st Inductor Value

1061 mH (2.5%)

L2

2nd Inductor Value

254.6 mH (0.6%)

L3rd

3 Inductor Value

31.8 mH (0.075%)

Current Controller Parameterz

Damping Factor

0.7

fc

Cutoff Frequency

1 kHz

350
VolL

300
Inverter-side Inductor Volume [cm3]

For instance, during the 0o-60o time region, the controlledcurrents are iu and iw as shown in Fig. 3. Therefore, theinput values to i1, i2, v1, v2, and v3 are iu_ref, iw_ref, vuo, vvo
and vwo, respectively, as shown in Table I.
Next, the dead-time compensation is introduced at thefirst step of PWM generation. The duty ratio which
compensates for the dead-time-induced error voltage, isexpressed as follow,
Ddeadtime  f swTdeadtime ............................................ (15)where Tdeadtime is the dead-time. The dead-time-induced
error voltage is simply compensated as shown in Fig. 4
because when the inverter is intentionally operated in
DCM, the zero-current interval is under control. The
compensated duty ratios are then compared with thesawtooth waveform to generate the PWM signals. In
order to avoid the simultaneous turn-on of both switching
devices in one leg, the typical dead-time generation isused to delay the turn on. Finally, the PWM signals are
distributed to the switching devices corresponding toeach 60-degree time region of DPWM based on Table I.
Note that if the outputs pwm2 and pwm4 are utilized asshown in Table I, the inverter is operated undersynchronous switching; otherwise, if the outputs pwm2
and pwm4 are set to zero, the inverter is operated underasynchronous switching.

250%ZL=2.5%(P1)

Inverter-side inductor L
volume reduced by 70%200
150%ZL=0.6%
(P2)

100
50
0

%ZL=0.075%
(P3)

10

1.0
0.1
Impedance of Inverter-side Inductor %ZL [%]0.01

Fig. 5. Relationship between filter volume and inductor impedance at
switching frequency of 40 kHz. The inductor volume can be minimized
greatly when reducing the inductor impedance.

balanced three-phase currents are still achieved with theproposed control.
Figure 8 shows the current THD characteristics of theconventional CCM current control and the proposed
DCM current control with three inductor designs from
Fig. 5. At rated load with the inductor impedance of
0.075%, the current distortion of the proposed DCM
current control is reduced by 97.6% compared to theconventional CCM current control. Note that the current
THD of the conventional CCM current control with theinductor impedance of 0.075% or 0.6% has a tendency todecrease at light load. The reason is when the average
current is significantly smaller than the current ripple, thecurrent mode is no longer CCM but triangular current
mode (TCM) [22]-[23]. In TCM, all the turn on of theswitching devices is zero voltage switching. On otherwords, the dead-time-induced error voltage does notoccur in TCM. Hence, the current distortion due to thezero-clamping phenomenon disappears at light load.

iv

iu

iw

Inverter output current (20 A/div)

0A

iu

iv

iw

Inverter output current (20 A/div)

iavg_uiavg_v

iavg_w

Average current (7.5 A/div)
Time (10 ms/div)0A

iavg_v

iavg_uiavg_w

Average current (7.5 A/div)
Time (10 ms/div)

THD=3.9%

THD=1.5%
0A

0A(a) Conventional CCM current control with %ZL = 2.5% at rated load(b) Conventional CCM current control with %ZL = 0.6% at rated load

Inverter output current (20 A/div)
iu

iv

iu

iw

0A

iv

Inverter output current (20 A/div)iw

0A

Average current (7.5 A/div)
Time (10 ms/div)

Average current (7.5 A/div)
Time (10 ms/div)0A

0A

iavg_uiavg_v

iavg_w

iavg_v

iavg_uiavg_w

THD=9.8%

THD=0.3%(c) Conventional CCM current control with %ZL = 0.075% at rated load (d) Proposed DCM current control with %ZL = 0.075% at rated load
Fig. 6. Inverter output currents and average currents of conventional CCM current control and proposed DCM current control at rated load. The
current THD of the conventional CCM current control increases with the reduction of the grid filter impedance, whereas the current THD of the
proposed current control is still low.
iu

LABORATORY SETUP

A. Discontinuous-current mode operation
Figure 10 depicts the three-phase grid-tied inverter
DCM operation waveform at rated load. In Figure 10(a),the phase difference between the grid current of u phaseand the grid u-phase voltage is almost zero, i.e. the unitypower-factor operation. Furthermore, even with the small
inverter-side inductor impedance of 0.5%, the low current
THD of 2.4% is still achieved. As shown in Figure 10(b)(c), the three-phase inverter output currents are similar to
those shown in Figure 6(c), i.e. the operation of the
proposed DCM control is confirmed.
Figure 11 shows the grid phase voltages and the gridcurrents of u phase and w phase at the normal operation
and at step-up load change. At the normal operation, thethree-phase grid current is well balance and the low
current THD of 2.4% is achieved for all three-phase gridcurrent. At the step-up load change from 0.1 p.u. to 1.0
p.u., the stable current response is confirmed. Note that

0A

0A

iavg_uiavg_v

iavg_w

Average current (7.5 A/div)
Time (10 ms/div)

Fig. 7. Load step response between load of 0.1 p.u. and load of 1.0 p.u..
The stable inverter operation is confirmed even at load step change.
Conventional CCM control with
%ZL=0.075%%ZL=0.6%%ZL=2.5%
Proposed DCM control with
%ZL=0.075%
Current distortion reduced by 97.6%
1 p.u. equals to 3 kW.

18.0
Average Current Distortion THDiavg [%]IV.

Table III shows the experimental parameters, whereas
figure 9 depicts the prototype of the miniature threephase grid-tied inverter. In order to operate the inverter
under DCM over entire load range with the switchingfrequency of 20 kHz, the inverter-side inductor value isdesigned at 80 mH, whose impedance is 0.5% of the total
inverter impedance.

Inverter output current (20 A/div)
iv
iw

16.0
14.0
12.0
10.0
8.0
6.0
4.0
2.0
0.0

0

0.1

0.2

0.3 0.4 0.5 0.6 0.7 0.8
Output Power Pout [p.u.]

0.9

1.0 1.1

Fig. 8. Current THD characteristics of conventional CCM current
control and proposed DCM current control with three different inductor
designs. With the proposed DCM current control, the current THD ismaintained below 5% over entire load range from 0.1 p.u. to 1.0 p.u..

TABLE III
EXPERIMENTAL PARAMETERS.

Grid phase voltage (100 V/div)vuo

Circuit Parameter
VDC

DC link VoltagevgLine-to-line Voltage

100 Vrms

Pn

Nominal Power

700 W

fg

Grid Frequency

50 Hz

Zb

Total Impedance

4.8 W

fsw

Switching Frequency

20 kHzTdeadtime

Dead-time

L

Inductor Value

0V

300 V

Grid current (5 A/div)

THD = 2.4%

ig_u
0A

iu

500 ns0A

80 mH (0.5%)

h = 60 mm

Inverter
outputcurrent(10 A/div)(a) Grid phase voltage, grid current, and inverter output current of uphase

w = 80 mm

vuo

0V
Grid phasevoltage (100 V/div)

Fig. 10(c)

iu

iv

iw

l = 260 mm

0A

Fig. 9. Prototype of miniature three-phase grid-tied inverter.

the three-phase grid currents are still balance both before
and after the step-up load change.
Figure 12 depicts the current THD characteristics ofthe proposed DCM current control. The current THD ismaintained below 5% over load range from 0.3 p.u. to 1.0
p.u., which satisfies the current THD constraint in IEEE1547, even when the inductance impedance is reduced to
0.5% of the inverter impedance. The increase of thecurrent THD at light load can be explained due to thehigh occupation of the reactive current flowing throughthe filter capacitor. Therefore, in order to reduce thecurrent THD at light load, the DCM control should also
consider the effect of the reactive current in the filter
capacitor.
B. Efficiency comparison between asynchronous
switching and synchronous switching in DCM
Figure 13 shows the asynchronous switching andsynchronous switching in DCM. In the asynchronous
switching, the corresponding switches are turned after theperiod D1Tsw and D3Tsw finish. Therefore, the current has
to flow through the diode. In the next generation
switching devices such as SiC or GaN, the forward
voltage of the inverse diode in such devices is generally
higher than that of the conventional MOS-FET devices.
Consequently, the conduction loss with the asynchronous
switching is higher that of the synchronous switching,where the current flows through the FET part. As shownin Figure 13, the synchronous switching can also be
applied into DCM in the same manner as theconventional CCM. Consequently, the conduction loss of

Inverter output current (5 A/div)

Time (4 ms/div)(b) Grid phase voltage of u phase, and three-phase inverter output
currents

iu

iw

0A
iv
Inverter output current (5 A/div)

Time (10 ms/div)(c) Zoom-in three-phase grid current from Fig. 10(b)Fig. 10. Three-phase grid-tied inverter DCM operation waveform at
rated load. The three-phase inverter output currents shown in Fig. 10(b)are similar to those shown in Fig. 6(c). This confirms the operation of
the proposed DCM control.

the switching device is reduced.
Figure 14 depicts the efficiency comparison between
asynchronous switching and synchronous switching in
DCM. The application of the DCM synchronous
switching reduces the conversion loss by 33% comparedto the DCM asynchronous switching at rated load.
Furthermore, the maximum efficiency of 97.8% isachieved at rated load.
V.

CONCLUSION

In this paper, the DCM current control was proposedto the grid-tied three-phase inverter in order to minimize
the grid filter volume without worsening the current THD.
When the inverter is operated under DCM, the zero-14.0
Proposed DCM control with %ZL=0.5%
Grid phase voltage (50 V/div)

vwo

12.0

vuo

Gird Current THDig [%]

10.0

0V

Grid current (5 A/div)

ig_w

ig_u

8.0

4.0
2.0

THD = 2.4%

0.0
0ATime (10 ms/div)(a) Grid phase voltages and grid currents of u phase and w phase atnormal operation
vuo
0V

Current THD constraint in IEEE-1547(Requirement: THD<5%)

6.0

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Power Pout [p.u.]

1

1.1

Fig. 12. Current THD characteristics of proposed DCM current control.
The current THD is maintained below 5% over load range from 0.3 p.u.
to 1.0 p.u., which satisfies the current THD constraint in IEEE-1547,
even when the inductance impedance is reduced to 0.5% of the inverter
impedance.

current THD was maintained below 5% over load range
from 0.3 p.u. to 1.0 p.u. even when the inductance
impedance is reduced to 0.5% of the inverter impedance.
In the future work, the DCM current feedback control
will be considered in order to eliminate the circuitparameter dependency.
REFERENCES

Grid phase voltage (100 V/div)

[1]
ig_u

ig_w
Grid current (5 A/div)

[2]

0A

[3]
Inverter output current (10 A/div)

iu

[4]
[5]

0A

[6]
Time (10 ms/div)(b) Current response of step-up load change
Fig. 11. Grid phase voltages and grid currents of u phase and w phase atnormal operation and at step-up load change. Three-phase currents arebalanced at normal operation as well as at step-up load change.

current interval can be controlled, compensating simply
the dead-time-induced error voltage. Consequently, when
the inductor impedance is reduced to 0.075%, the current
THD of the proposed DCM current control is reduced by
97.6% compared to the conventional CCM current
control as simulation results. In the experiments, the

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Inverter
outputcurrent(5 A/div)

iw

0A
iv

Switching signal
up

Synchronous switching in DCM

97.5
97
96.5
96
1.0 p.u. equals to 700 W.
Maximum efficiency of 97.8% is achieved at rated load.

95.5
95
94.5

Asynchronous switching in DCM

94

0V

93.5

un

93
0

0V
vp

Switches are turned off
in asynchronous switching.

vn
wp

0V
wn

Time (20 ms/div)

0V(a) Asynchronous switching in DCM

iuiw

Inverter
outputcurrent(5 A/div)

0A
iv

Switching signal
upTime (20 ms/div)

0V
un
0V
vp

0.1

0.2

0.3

0.4
0.5
0.6
0.7
Output Power Pout [p.u.]

0.8

0.9

1

Fig. 14. Efficiency comparison between asynchronous switching andsynchronous switching in DCM. The application of the DCM
synchronous switching reduces the conversion loss by 33% compared to
the DCM asynchronous switching at rated load.

0V

0V

Loss reduced by 33.3%

98

Conversion Efficiency h [%]iu

Switches are turned onin synchronous switching.

0V
vn
0V
wp
0V
wn
0V

(b) Synchronous switching in DCM
Fig. 13. Asynchronous switching and synchronous switching in DCM.
Similar to the conventional CCM, the synchronous switching can also
be applied into DCM. This makes the current flow through the FET partinstead of the diode. Consequently, the conduction loss of the switching
device can be reduced.
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