A New AC Bidirectional Switch
with Regenerative Snubber
to Realize a Simple Series Connectionfor High Power AC/AC Direct Converters
Jun-ichi Itoh,Ken-ichi Nagayoshi

Nagaoka University of Technology,1603-1 Kamitomioka-cho Nagaoka city Niigata, Japan
itoh@vos.nagaokaut.ac.jp
AbstractThis paper proposes a new bidirectional switch andsnubber circuit for high power AC to AC converter. The
proposed switch can be constructed with a 2-in-1 IGBT moduleand 2-in-1 diode module and can reduce the voltage stress of theswitching device by series connection. The proposed snubber
configuration is very easy and it can regenerate absorbed energy.
On the other hand, a timing error of switching between the seriesconnected switches causes the voltage unbalance in the snubber
circuit. This paper also proposes a simple voltage unbalance
reduction method with one voltage sensor for each switch circuit.
The proposed method controls snubber voltages by adjusting
switching timings. Furthermore, this paper mentions that the
proposed switch circuit can be applied to the matrix converter.
These new proposals are confirmed by experimental results.

I.

INTRODUCTION

Recently, AC/AC direct converters have been studied in an
attempt to realize high efficiency, long-life time, downsizing
and unity input power factor [1-7]. These advantages increasein high power converters more and more because the AC/AC
direct converter does not needs electrolytic capacitors which
are dominant to the volume and cost of high power converters.
However, there are two problems to realize the high power
AC/AC direct converters.
Firstly, it is difficult to apply bi-directional switches, such asa reverse blocking IGBT, to a high voltage rating. Therefore, itis generally necessary to use transformers for the constructionof high power AC/AC direct converters. Secondly, a snubber
circuit, such as a diode clamp circuit, is not effective because
the lead wire length becomes longer with respect to theincrease in the converter size [8]. Hence, the snubber circuits
are necessary in order to connect to each switch easily.
This paper proposes a new AC switch construction methodthat uses general switching modules with a regenerative
voltage clamp snubber circuit and a series connection
technique. Although a bidirectional switch has been proposed
for general purpose modules, as reported in [9-13], twice thenumber of switching devices is required for the conventional
direct converter. However, the same number of the switches issufficient for the proposed switch construction. Voltage

balance control for a series connection is also proposed. The
snubber circuit with a voltage clamp is possible to easily keep
the voltage balance of the terminal voltage of the switch
modules by the balance control because the switch voltage isslowly changed by a clamp capacitor. In case of the proposed
method, the terminal voltage of the switch modules can becontrolled by control of the switch timing. These new
proposals are confirmed by experimental results with ac
chopper. Furthermore, we also confirmed that the loss of the
proposed snubber is less than a conventional RC clamp
snubber under series connection.
II. CONFIGURATION OF THE PROPOSED SWITCH
Fig. 1 shows the circuit configuration of the proposedbidirectional switch and the principle operation. The proposedbidirectional switch is constructed with a 2-in-1 IGBT moduleand 2-in-1 diode module. Thus, a more inexpensive switch canbe realized compared with the H-bridge type bidirectionalswitch reported in [10]. Two capacitors (C1, C2) and a resistor(R) are configured for the snubber circuit. The snubber circuit
operation is described as follows.
Firstly, we consider that S2 is turned on, such as shown in
Fig. 1(a), and the current is flowing from left to right. Theenergy of C2 is then regenerated through R. Next, when S2 isturned off, such as shown in Fig. 1(b), the current commutates
to S1, and the energy of wire inductance, l, is absorbed by C1
and C2. Lastly, when S1 is turned on again, such as shown in
Fig. 1(c), the energy of C1 is regenerated though the arrow pass,
as shown in Fig. 1(c). Next, we describe a design method ofsnubber parameters.
A. Parameter design of C1, C2
The proposed snubber circuit absorbs storage energy of line
inductance l when S1 or S2 is turned off. In this case, theabsorbed energy Wa by the snubber circuit is obtained by Eq.
(1):
Wa =

(

)

1
2
2
2
C1 ⋅ ∆v1 + C2 ⋅ ∆v2 + R ⋅ iR ⋅ t2(1)

where, ∆v1, ∆v2 are increased voltage by absorbed energy, iR isthe average current to the resistance R.

S1

+

ON
C1

D1
R

C2

D2

l
S2

vC10
C2

C1
R

-

ON
E
vC10 :VC10
t=0 v :V
C30 C30

{

C4

vC30

R

C3

Load

I

(a)Turn on mode flowing forward current .

Fig. 2. A current path of the energy recovery mode.
S1

+

C1

D1
R

C2

D2

l
S2

SW

-

E

+

R

VC10

VC30

R

+

Fig. 3. Equivalent circuit in case of the surge recovery mode.
(b)Surge energy absorption mode.
S1

+

C1

l
S2

C2

D1
R

-

D2

(c)Energy recovery mode.

Fig. 1. Operation mode of the proposed switch.
C1 and C2 are constrained by the voltage rating of theswitching device since ∆v1 and ∆v2 are determined by thevoltage rating. Therefore, C1 and C2 have to be designed thatthe capacitor voltages is not over the voltage rating of theswitching device when the snubber circuit absorb the
maximum surge energy Wa. As a result, If C1=C2=C and R isneglected because the second term in Eq. (1) is not dominant,relation between Wa and energy of l (1) is leaded by Eq. (2):
1
1
2
(2)
Wa = C ⋅ ∆v 2 ≥ ⋅ l ⋅ I max
22
where Imax means maximum current of the power converter.
Therefore, the capacity of C1 and C2 can be decided by Eq. (3):
l ⋅i2
(3)
C1 = C 2 = C ≥ 2∆v
Fig. 2 shows a current path of the surge recovery mode. The
proposed snubber circuit regenerates the storage energy ofsnubber capacitor C1 and C3 toward the power source when S1and S3 are turned on.
The equivalent circuit of this mode is shown in Fig. 3. In thismode, the recovery energy is a summation of the energy
consumed by resisters and recovered to the power source. The
relation is expressed by Eq. (4):2
(4)
C (Vmax − Vmax 0 ) = E ⋅ I∆T + 2 R ⋅ I 2 ∆T
where Vmax is the maximal voltage of C1 and C3, Vmax0 is thecapacitor voltage after discharge, and ∆T is discharge time.
The meaning of the left terms is the discharge energy ofcapacitors. The value of R should be decided to recovery theenergy during ∆T. The discharge time ∆T should be set as
short as possible, because ∆T constrains the minimum andmaximum duty ratio. However, too short discharge time ∆T
causes large recovery current due to a very small value of R.
Therefore, the value of R is constrained by the recovery current.
The recovery current has to be suppressed below the current
rating of switching devices. The worst case of VC10 and VC30
shown in Fig.3 becomes Vmax when the opposite side capacitor
C2 and C4 all discharge. Therefore the recovery current I islead by Eq.(5) from Fig. 3.
2V − E(5)
I > max
2R
Finally, the value of R is decided using Eq. (6):2V − E(6)
R > max
2I n
where In is the maximum current of the switching device.

III. VOLTAGE BALANCE CONTROL FOR THE PROPOSEDSWITCH UNDER SERIES CONNECTION
Voltage balance control is required, because the switch
timing and the characteristics of the devices are not exactly thesame. Basically, in the case of a series connection, each of theswitches works with the same timing as the corresponding
switch. However, the response speed of the drive circuits orthe characteristics of the power device cause a gap in theswitch timings. These timing gaps cause an imbalance ofvoltage among each of the series-connected switches.
Fig. 4 shows the operation of the proposed voltage balancemethod by adjustment of the switch timings. To explain thecause of the unbalanced voltage, we assume that the switch
timing of SU1(S1, S2) are faster than SU2(S3, S4), as shown in
Fig. 4(b). When the forward direction switches (S2, S4) areturned off, the voltage of SU1(VSU1) immediately increases,
because the energy of l is stored in C1 and C2. In this case, thecapacitor voltage vC1 during time rag is obtained by Eq. (7) if

S1

SU1

S3

SU2

l

S3
S4

SU1,2
Lower

OFF
ON

Curr. Polarity
Det.

Switchingtimingcontrol
FPGA
SU1,2
Upper

Control
TriggerON

S3,S4

Volt. Polarity
Det.

(a)Series-connected switch.

S2

S1,S2

SU2
V

S1

SU4

SU1,2
Lower

SU1

SU3

comparator

S4

VSU2

SU1,2
Upper

S2

VSU1

AC chopper Sw.
signal gene.
(FPGA)

OFF
ON
OFF
ON

Duty commandOFF

8Controller

Fig. 5. Block diagram of the experimental system.

VSU1
VSU2

(b) Behavior of the switch voltages without control.

S 4 _OFF_delay

S 2 _OFF_delay

S 3 _OFF_delayOFF

S 1 _OFF_delay

OFFON

S 4 _ON_delay

S4

OFF
ON

S 3 _ON_delay

S3

S 2 _ON_delay

S2

ON
OFF
ON

S 1 _ON_delay

S1

VSU1
VSU2

(c) Behavior of the switch voltages with the proposed
control.
Fig. 4. Basic concept of the proposed method.
switch current is constant during time rag, and the R can beneglect.
i⋅(7)v =V + t
C1

C 10

C1

Table 1. Delay time calculation of “Time adjust cal.”.
Section I

SECTIONIt should be noted that the snubber voltage increases slowly
because the snubber capacitor is charged by the power supply
through the load.
On the other hand, when the switches in the opposite
direction (S1, S3) are turned on to regenerate the snubber, thevoltage of SU2(VSU2) also increases, because the power supply
voltage (V) is applied only to SU2. When S1 are turned on
faster than S3 as shown in Fig. 4(b), then the input voltage isonly biased to C4. In this case, only C4 is charged through the R
and the power supply. Therefore, the voltage of C4 during time
rag is given as Eq. (8).
vc 4 = E + Vc 40 e

Fig. 6. Block diagram of the switching timing control FPGA.

t−( R + Load )⋅C(8)where Vc40 is initial voltage of VC4.
It is noted that VSU1 and VSU2 can only be detected at thepeak timing of the triangular carrier. As a result, it is notpossible to distinguish the course of the voltage variation.

Section II

COMPARATOR VSU1 > VSU2 VSU1 < VSU2 VSU1 > VSU2 VSU1 < VSU2
S1ON_delay_time-Tajst+Tajst--S1OFF_delay_time--+Tajst-Tajst+TajstS2ON_delay_time---TajstS2OFF_delay_time-Tajst+Tajst--

S3ON_delay_time+Tajst-Tajst--S3OFF_delay_time---Tajst+Tajst

S4ON_delay_time--+Tajst-Tajst

S4OFF_delay_time+Tajst-Tajst--Fig. 4(c) shows the switching timings and the corresponding
voltages for the proposed voltage balance method. The
strategy of the proposed adjustment method is to add a delay
time to the switch timing according to the voltage difference
between the switch circuits at every control period
synchronized by a PWM generated carrier wave. That is, theswitch timing of S2 and S3 is delayed to reduce the switch
voltage VSU1 despite the increasing VSU2. If VSU2 becomes

SU2A 2
2

2

2

2

SU4

SU5

SU6

(9)

(10)
If SUP becomes active, then section I is selected. Similarly, if
SLW becomes active, then section II is selected.
Table 1 shows adjustment time of each switch depending on
the section and relation between magnitudes of the input
voltage. According to situation, the pulse of width Tadj is
added to the command pulses, or is subtracted from thecommand pulses.
It is noted that the proposed balance control does not
influence the other phase switch module in the matrix
converter because the proposed balance control does not use
information of other phase switch.

SU1
2
SU2
2
SU3

S UP = UPPERPWM
S LW = LOWERPWM(b) ILOAD < 0 .
(a) ILOAD > 0 .
Fig. 7. The proposed commutation method (V1>V2).

SU1A 2larger than VSU1, then the switch timing of S1 and S4 is delayedin the opposite way. This balance point of operation achieves
the same voltage for each of the switching modules. The
strategy of the proposed voltage balance method is very simple,
thus practical. Although the proposed method can not exactly
agree with each of the switch timings, the proposed method
realizes an easy and effective suppression of the voltage
imbalance.
Fig. 5 shows a block diagram of the proposed balance control
which is applied to an AC-chopper. The “AC chopper SW
signal gene” generates PWM patterns for each switch by using
duty commands generated by the “Controller”, the input
voltage polarity detected by the “Voltage Polarity Detection
Circuit”, and output current polarity detected by the “Current
Polarity Detection Circuit”. “Switching timing control FPGA”
adjusts pulse width of PWM patterns generated by “ACchopper SW signal gene”“Switching timing control FPGA” block is a main part of the
proposed method. The proposed balance control only adjusts
switch timing of SU1 and SU2. The trigger pulse, which issynchronous with the carrier peak, is obtained by the “Control
Trigger”
The proposed voltage balance method is achieved using aswitch timing control FPGA, as shown by the internal block
diagram of Fig. 6. The “UPPER LOWER Switching arm det.”
detects next pulse whether upper or lower arm is switching
because the behavior of the snubber voltage is deference
between upper arm switching (section I) and lower arm
switching (section II). The switching state signal SUP and
SLW can be obtained simply by Eq. (9) and (10) from upperand lower PWM commands at every timing of a carrier peak.

Fig. 8. Block diagram of 3-phase chopper
experimental system.

IV. COMMUTATION METHOD FOR THE PROPOSED SWITCH
The commutation avoids a short circuit of a power supply oran open circuit of an output terminal. In addition, the upperand lower arm in the proposed switch cannot be
simultaneously turned on because the capacitors of the snubber
circuit are shorted. Therefore, the proposed switch needs a
special commutation which uses both information of thevoltage and current direction.
Fig. 7 shows the switching patterns of the proposed
commutation method using a principle circuit when the voltage
condition is V1 > V2. The commutation patterns are selected by

Fig. 9. Switching patterns of the matrix converter.
relations between magnitude of the input voltages and theoutput current direction. The prohibited patterns do not haveto be selected. For example, when S1 and S3 are turned on at
the same time, a short circuit occurs in the power supply. On
the other hand, when S2 and S4 are turned off at the same time,
an open circuit occurs of the output terminal. At the section A
shown in Fig. 7(a) in which the current direction is positive,

the output voltage of V1 is obtained due to V1>V2 when S2 andS4 are turned on. At the section B, the output voltage appears
V2 because S2 is turned off. All the while, the energy of C1 isregenerated to the power supply through S1. As shown in Fig.
7(b), the current direction is negative in contrast to Fig. 7(a).
At the section C, the output voltage becomes V1 because S1 isturned on, and the energy of C4 is supplied to load through S4.
At the section D, the output voltage becomes V2 because S3 isturned on. It should be noted that the gate signals of S1 and S3,interchanged, respectively in case of the V1<V2. Similarly, thegate signals S2 and S4 are also interchanged.
Fig. 8 shows the block diagram of a principle model of thematrix converter in order to consider the applicability of the
proposed commutation method. This circuit is similar to single
phase of the matrix converter. In case of the pulse pattern ofthe matrix converter, there are three types command dependingon the relations of magnitude of power supply voltage asshown in Fig. 9[14]. The symbols, Vmax, Vmid, and Vmin shownin Fig. 9, indicate the maximum, the medium, and theminimum voltage of the power supply, respectively.
When the proposed commutation method is applied to thematrix converter, the commutation pattern has to change by the
relation between magnitudes of the power supply voltage.
Because a mode of the middle voltage switch often changes toa lower mode or an upper arm mode. In case of the switching
between Vmax and Vmid, the middle voltage switch changes
works as lower arm, in case of the switching between Vmid andVmin the middle voltage switch changes works as lower arm.
Therefore commutation pattern has to select immediately
according to the switch mode.

Input Voltage
100V/ div
Output Current 0
10A/ div

Max:139[V]S 11 Voltage
40V/div

Max:66.8[V]S 12 Voltage 0
40V/div(a)Without control.
Input Voltage
100V/div
Output Current 0
10A/ div

Max:94.8[V]S 11 Voltage
40V/div

Max:91.3[V]S 12 Voltage 0
40V/div(b)With Control.

Fig. 10. Experimental results for the proposed
Fig. 8 control
Experimentalof proposedbalancemethodresultswith theproposed balancesnubber.
control method with proposed snubber.

V. EXPERIMENTAL RESULTS
The experimental systems based on Fig. 5 is constricted inorder to confirm the validly of the proposed balance control.
The experimental conditions are described in Table 2. Itshould be noted that the SU1 switch timings are deliberately
faster than the SU2 switch timings by 0.5µs, in order to confirm
the proposed voltage balance method.
Fig. 10(a) shows the waveforms of the switch voltages
without any control, which results in an imbalance in thevoltage. Fig. 10(b) shows the waveforms of switch voltages
with the proposed method, where a voltage balance is achieved.
The maximal voltages of each switch decreased from 139V to
94.8V, when using the proposed balance control. More over
the almost same maximum voltage of the each switch is
obtained. This result means that we can use a low voltage
rating switching device when a high voltage power converter isconstructed because the voltage snubber shares the power
supply voltage.
Fig. 11 shows the validity of the proposed voltage balancemethod with a conventional RC snubber, which R is connectedin parallel with C. The proposed voltage balance method canalso be applied to a conventional snubber. As a result, themaximal voltages of each switch also decreased from 122V to
101V using the proposed balance control. That is, theproposed method is also useful for a conventional snubber.

Max:122V

0

Max:68.8V0

OutputInput
SU1
Voltage Current Voltage
100V/div 10A/div 40V/div

SU2
Voltage
40V/div(a) Without control.

0

Max:101V

Max:99.2V
Input
OutputSU2SU10 Voltage Current
Voltage Voltage
100V/div 10A/div 40V/div 40V/div(b) With control.
Fig. 11. Experimental results for the proposed balance
control method with an RC snubber.

SU1+SU2 snubber loss[W]Fig. 12 shows the comparison of snubber loss between theconventional and the proposed method. It is noted that the
proposed snubber loss is less than the conventional RC snubber,
as shown in, because the proposed snubber can regenerate thesnubber loss to the power supply or load.
Next, the experimental systems of the matrix converter basedon Fig. 8 is constricted in order to confirm to the validly of the
proposed commutation method and balance control.
Fig. 13(a) shows input voltage and output current waveformsof the experimental system. As shown in Fig. 13(a), the output
current of a good sinusoidal waveform is obtained. Fig. 13(b)shows expansion of the input and output current waveforms.
The power supply current flow continuously to output sideshown in Fig. 13(b). As a result, it is confirmed that the
proposed commutation method can apply to matrix converters.

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Output current[A]Fig. 12. Comparison of an RC snubber loss andthe proposed snubber loss(SU1+SU2)

VI. CONCLUSIONSThis paper proposes a method for construction of a highpower AC/AC converter with series connected switch modules.
The proposed switch and voltage balance method have thefollowing features and advantages:i.
The proposed switch is constructed with a 2-in-1
IGBT module and a 2-in-1 diode module. Therefore
the switch can be inexpensively constructed comparedwith an H-bridge type bi-directional switch.
ii.
The voltage imbalance caused by the time lags ofswitch timings can be easily suppressed by adjustmentof the switch timing.
iii.
The proposed timing control can also apply to theconventional RC snubber.
iv.
These proposals can apply to matrix converters.
The validity of the proposed snubber and balance method fora series connection switch were confirmed by simulation andexperimental results with an AC chopper system.
This study was supported by Industrial Technology Grant
Program in 2005 from New Energy and Industrial Technology
Development Organization (NEDO) of Japan.

4.5
4
3.5
3
2.5
2
1.5
1
0.5
0

Output Voltage (10V/div)00
Output Current (2A/div)(a) The Output voltage and the output current waveforms.
iU
0
0
0

iR
iS
iT

0

(b) Current waveforms of proposed
commutation method (1A/div).
Fig. 13. Experimental results of the test matrix converter.
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