Voltage Unbalance Compensation Method with
Zero Voltage Switching for Series Connected Switching Devices
Jun-ichi Itoh1, Ryosuke Iso1, and Hiroki Watanabe1
1

Nagaoka University of Technology, Japan

Abstract— This paper proposes a voltage unbalancecompensation method of series-connected switching devices
for high voltage application such as DC distribution systems.
In the series connection, a turn-off voltage unbalance occurs
in switching devices due to a parasitic parameter mismatchand a switching timing mismatch among switching devices.
In this paper, a capacitor snubber and Zero Voltage
Switching (ZVS) operation are utilized to reduce voltage
unbalance. In particular, the proposed method reduces theparasitic capacitor (collector-emitter capacitance) mismatchamong series-connected devices by a capacitor snubber
circuit, whereas the switching losses are effectively reduced
by ZVS. As the simulation results, it is confirmed that thecollector-emitter voltage unbalance is reduced by 88% by the
proposed method in comparison with a snubber-lessconfiguration. Finally, in order to confirm the effectiveness ofthe proposed method, experiments with a test circuit appliedwith the proposed method are conducted. According to theexperimental results, the voltage unbalance is reduced by
86.0% due to the application of the proposed method.
Index Terms—series connection, high voltage power
converter, voltage unbalance, zero voltage switching (ZVS)I.

INTRODUCTION

Recently, high voltage DC/DC converters have been
actively researched for DC distribution systems [1]-[6].
The DC distribution systems have many advantages incomparison with an AC distribution, e.g. low powertransmission losses and high compatibility to DC power
generation systems such as photovoltaics systems.
In the DC distribution system, isolated bidirectional
DC/DC converters are employed in order to connect the
DC power generation sources to the DC grid. Hence, thesepower converters require high voltage rating devices
because the DC-bus has a high voltage level more thanseveral kilovolts. Therefore, the switching devices whichhave high voltage rating are chosen.
On the other hand, wide band gap semiconductors suchas silicon carbide (SiC) and gallium nitride (GaN) havebeen developed in order to enhance the performance of thepower switching devices [7]. In particular, a high voltage
rating switch concept using series-connected SiCMOSFET has been actively researched for Medium
Voltage (MV) or High Voltage (HV) applications [8]-[10].
In this study, a 10 kV-15 kV SiC module which consists ofseries-connected 1.7 kV SiC-MOSFETs is employed inorder to improve the conversion efficiency [11].
Note that a drain-source voltage unbalance has to beconsidered in the series connection techniques due to themismatch of parasitic capacitors on each LV-devices [12][13]. A RC snubber method is commonly adopted in orderto solve this problem. However, the snubber resistor losses
worsen conversion efficiency.
In order to avoid the decrease in the conversion
efficiency, a voltage unbalance compensation method witha gate timing control method has been proposed [14]-[16].
In this method, the gate signals for series-connected
devices are adjusted by digital gate control with a Field
Programmable Gate Array (FPGA) and a Digital Signal
Processor (DSP). However, it is difficult to identify theparameter mismatch in actual systems because thecollector-emitter capacitance and the switching speed
depend on the junction temperature condition.
This paper proposes a voltage balance method for theseries-connected devices using C snubber and the zerovoltage-switching (ZVS) operation with the Triangular
Current Mode (TCM). The snubber capacitance is selected
at least five times higher than the parasitic capacitance toreduce the mismatch effect of the parasitic capacitances.
Meanwhile, turn-on losses are drastically reduced by the
ZVS operation. In addition, the design criteria of the C
snubber is introduced in order to compensate the risetiming mismatch of the corrector-emitter voltage on eachseries connected switching devices. The proposed method
has advantages such as simple configuration and low
snubber losses in comparison with the conventional
voltage balance methods such as the RCD snubber. The
originality of this paper is that the voltage unbalance of theseries-connected switching devices is compensated by thesimple capacitor snubber. In addition, the switching losses
are drastically reduced due to the ZVS operation. In thispaper, the validity of the proposed method is confirmed by
the simulation and fundamental experiments.
This paper is organized as follows; high power and highvoltage converter topologies are introduced in section II.
Next, the causes of the voltage unbalance of the seriesconnected devices is explained in section III. In section IV,
the proposed voltage balance method for series-connected
devices applied C snubber and ZVS operation is presented.
Finally, the effectiveness of the voltage balance method

in the prototype DC/DC converter is confirmed by thesimulations and experiments.
Vdc1

II.

Vdc2

HIGH POWER AND HIGH VOLTAGE CONVERTERTOPOLOGIESIII.

VOLTAGE UNBALANCE OF SERIES-CONNECTED
DEVICESFirstly, the drain-source voltage at the turn-off period isexpressed as1
vds =ic ( t ) dt
(1)
Cds 
where vds is the drain-source voltage, Cds is the parasitic

7 kV(±3.5 kV)

7 kV(±3.5 kV)Fig. 1. Circuit configuration of Series Resonant Converter (SRC) for
solid state transformer during two HVDC buses [17].

Vdc2

Vdc1

DC

Vdc3

DC

11 kV

Multi-port isolated
DC/DC
DC/DC converter
converter
Fig. 2. Circuit configuration of multiport isolated DC/DC converter
for medium voltage and low voltage DC grids [18].

20 kV

Fig. 1 shows the circuit configuration of Series
Resonance Converter (SRC) for aircraft application [17].
In this system, two HVDC buses are used for power systemarchitecture, and a Solid State Transformer (SST) is
utilized for the power link between two HVDC buses.
SRC achieves ZVS and the Zero Current Switching(ZCS) operation utilizing resonance between seriescapacitor and a leakage inductance to reduce the switchingloss. Each DC port is connected to 3.5 kV bus. Therefore,
medium-voltage SiC MOSFETs are applied for eachswitching devices.
Fig. 2 shows the circuit configuration of the multiportisolated DC/DC converter for medium voltage and low
voltage DC grids [18]. This converter is utilized forbidirectional interfacing of MVDC and LVDC grid. In thissystem, SRC is also applied to achieve the galvanic
isolation between each DC grid. Note that the SRC is
operated by the open loop control, and the switchingfrequency is set to the resonance frequency for theachievement of the ZVS operation. The power flow during
each port is controlled by two DC/DC converter. In thiscase, the switching devices which have high voltage rating
are necessary for port of MVDC grid.
Fig. 3 shows the circuit configuration of the DC/DC
converter which consists of the series-connected SiCMOSFET for high power medium voltage converter suchas data center DC distribution [19]. In this circuit as an
example, the switching devices with the high voltage
rating are required due to high voltage DC input of 20 kV.
Generally, IGBT is employed for the switching devices
due to its high voltage rating properties. Meanwhile, theDC/DC converter has the requirements such as the
reduction of the size and the improvement of theconversion efficiency. In particular, the high-speed
switching operation is important to reduce the size of thepassive components such as the transformer.
In this system, the series-connected configuration using
SiC-MOSFET is utilized in order to satisfy theserequirements, and it is the one solution to install the low
voltage devices to the high voltage power conversion
system such as Fig.1 and Fig.2. However, the voltage
unbalance between each series devices is the problem due
to mismatch of the parasitic capacitance.

Fig. 3. Circuit configuration of high power converter with seriesconnected technique for high power application [19]. The drainsource voltages of each MOSFET are divided due to the seriesconnection.

capacitance, ic is the parasitic capacitor current. According
to (1), the drain-source voltage depends on the parasitic
capacitance. The voltage unbalance occurs due tomismatch of Cds on each series-connected device. In
particular, Cds fluctuates dependently on the drain-source
voltage condition. Therefore, it is difficult to match thedrain-source voltage for each individual device.
The RC snubber is a simple solution to suppress thevoltage unbalance. In this method, the snubber capacitor isconnected to reduce the mismatch effect of the parasitic
capacitances. Note that the snubber capacitance isdesigned much higher than the parasitic capacitance. In
addition, the snubber resistor is applied to suppress thevoltage ringing caused by the resonance between thesnubber capacitor and the parasitic line inductance.
However, the snubber losses are increased due to thissnubber resistor.

On the other hand, in the gate timing control method
utilizing the digital gate control, the influence of theparameter mismatch which includes the gate-source
capacitor and the gate-drain capacitor is analyzed based onmathematical equations. In addition, the gate timing
control with the delay gate signal has been considered.
Fig. 4 shows the circuit configuration of the digital gate
control [14]. In this method, a gate timing control whichuses the FPGA has been proposed. The turn-off voltage
unbalance between two series-connected devices iscompensated by adjusting the switching timing, and thismethod has been proven to improve the conversion
efficiency in comparison with the RC snubber technique
due to the snubber less configuration. However, it isdifficult to match the nominal value of the parasitic
parameter with the actual value because the parasitic
parameter depends on the temperature condition.
Especially, the delay gate signal for the voltage balance isgiven by the parasitic capacitance. As the result, thevoltage unbalance remains due to these reasons.
In this paper, the voltage unbalance compensation
method with simple solution is introduced in order to solvethese problems.
IV.

L

S1
Rs1 vds1

GDU
FPG
A

S2

Delay
line

where Cce is the parasitic capacitance, Csnubber is thesnubber capacitance, and ic is the capacitor current. In thiscase, each snubber capacitance is designed much higher
than the parasitic capacitance.
However, the turn-on switching losses increases when
the snubber capacitor is inserted because this capacitor
discharges at the turn-on period of the switches. The
capacitor current is expressed asdv(3)
ic = ce ( Cce + Csnubber )dt
According to (3), ic increases due to the C snubber.
Moreover, the capacitance of the C snubber is much larger
than the parasitic capacitance. In this case, the capacitor
current flows into the switching device when the switching
device is turned on. As a result, the turn-on switchinglosses increase. Moreover, the current has potential tobreak the switching device because this discharge current
might become higher than the current rating of theswitching device. Thus, the connection of the C snubber
alone worsens the efficiency and might even break theswitching devices.

GDU

Fig. 4. Circuit configuration of digital gate control [14]. One of the gate
driver in switching device has a delay adjustment. The delay adjustmentchanges the gate timing based on the parasitic parameters.

Csnubber

Sp1

Cce
Sp2

.
.
.

SpN
Vout

Sn1

VOLTAGE UNBALANCE COMPENSATIONMETHOD

A. Principle of the proposed method
Fig. 5 shows the DC/DC converter with seriesconnected switching devices. The proposed method
compensates the voltage unbalance by the C snubber and
ZVS. Firstly, the parasitic capacitor mismatch issuppressed by introducing the snubber capacitors. The
collector-emitter voltage at the turn-off period with the C
snubber is expressed as
1
(2)
vce =
ic ( t ) dt
Cce + Csnubber 

Rs2 vds2

Sn2

.
.
.

Vin

SnN
Fig. 5. DC/DC converter with series-connected switching devices. The
upper and lower arms are consisted of multiple switching devices whichhave low voltage rating.

Gate Signal
SnON

Deadtime

0

Tsw
SpON

Deadtime

SnON

t

ZVS
iL

t

0
Mode: 1

2

3

4

ZVS
1

Fig. 6. Switching waveforms of TCM operation. The parasitic capacitor of
low side arm is discharged during dead time before turn-on. As a result,
ZVS is achieved. In the TCM operation, the current ripple is designed morethan the Continuous Current Mode (CCM) to obtain negative current for
ZVS.

In order to solve this problem, ZVS is applied to reduce
the turn-on switching losses. The charge of the snubber
capacitor and the parasitic capacitor is expressed as(4)
q = vce ( Cce + Csnubber )where q is the electrical charge. The charge of the snubber
capacitor and the parasitic capacitor are delivered back to
the DC-link capacitor by the negative current before theturn-on of the switches. As the result, the turn-on losses are
drastically reduced because the collector-emitter voltage
becomes almost zero thank to ZVS.
Fig.6 shows the switching waveforms of the TCM
operation [20]. The TCM operation utilizes the large

Sp1

Sp1

Sp1

Sp1

L Sp2

L Sp2

L Sp2

L Sp2

Sn1
ZVS
Sn2

Sn1

Sn1

Sn1

Sn2

Sn2

Mode1

Sn2

Capacitor ischarging

Mode2 (delay time)Mode3 (dead time)

Sp1
ZVS
L Sp2

Sp1

Sp1

L Sp2

L Sp2

Sn1

Sn1

Sn1

Sn2

Sn2

Sn2

Mode4

Mode5 (dead time)
Fig. 7. Operation modes of TCM applies with series connected-switching devices.

current ripple for ZVS; consequently, the parasitic
capacitor and the snubber capacitor are discharged during
the dead time.
Fig.7 shows the operation mode of the DC/DC converterwith the TCM operation. Firstly, the switch Sn1 and Sn2 isturned on, and the boost inductor L is charged. In mode 1,
Sn1 and Sn2 achieves ZVS in turn-on because the dischargeof the parasitic capacitor and the snubber capacitor is fullycompleted during the dead time.
When Sn2 is turned-off before Sn1 is turned-off, mode 2
is started. In this mode, the parasitic capacitor and thesnubber capacitor of switch Sp1 and Sp2 are discharged.
Together with Sp1 and Sp2 discharging, the Sn2 capacitor ischarged while delay time. It makes voltage unbalanceamong Sn1 and Sn2.
When Sn1 is turned-off, mode 3 is started. In this mode,the parasitic capacitor and the snubber capacitor of switch
Sp1 and Sp2 are continue discharged. After that, the inductor
current commutates from the each capacitors to the freewheeling diode. In mode 4, the Sp1 and Sp2 is turned-on at
the forward voltage of the free-wheeling diode, which isconsidered as ZVS. During the mode 4, the inductor
current reaches to negative current as shown in Fig.6.
Mode 5 is started when Sp1 and Sp2 is turned-off, and theparasitic capacitor and the snubber capacitor are
discharged due to the negative current which is obtained
from mode 3. As the result, the Sn1 and Sn2 achieves turnon ZVS. According to these operations, the proposed
method avoids the occurrence of large turn-on switchinglosses due to the snubber capacitor employed in eachswitching devices.
B. Design of snubber capacitor of series-connectedswitching devices
Fig.8 shows the waveforms of the gate-emitter voltage
and the collector-emitter voltage when gate timing
mismatch occurs. Note that the black line indicates large
parasitic capacitor condition, and vsignal is the gate signals
from the controller. In actual system, it is difficult tosynchronize each gate-emitter voltage although vsignal is thesame due to the difference of the parasitic capacitance. As
the result, the rise timing of the corrector-emitter voltage
has delay, leading to the occurrence of the voltage
unbalance between each series-connected switching
devices.
vsignalInput gate signal does not have delaytLarge parasitic
capacitor conditions

vge

Nominal parasitic
capacitor conditionstvce

Delay timeoccurs due toparasitic
capacitancemismatch

Voltage unbalanceoccurs due to tdelayttdelayFig. 8. Waveforms of gate-emitter voltage and corrector-emitter
voltage when switching timing mismatch occurs.

In order to avoid this problem, the minimum snubber
capacitor has to satisfy
ic * tdelay(5)
Csnubber 
− Cce
vunb
where tdelay is the period of the delay time among seriesconnected devices, vunb is the voltage unbalance which
occurs among series-connected devices. It can be observed
from (5) is that C snubber should be infinity to make thevoltage unbalance becomes zero. Thus, the design of thesnubber capacitance is according to the required minimum
voltage unbalance. Moreover, the C snubber also reduces
the influence of the delay time among series-connected
devices. Note that, the delay time among series-connected
devices should be evaluated to design the C snubber
reducing the influence of delay time.
V.

Table 1 Simulation parameters.

SIMULATION AND EXPERIMENTAL RESULTS

A. Simulation results of DC/DC converter applied withproposed method
Table.1 shows the parameters for simulations. In order
to confirm the validity of the TCM operation in the DC/DC
converter, two series-connected devices is used in eacharms.
Fig. 9 shows the simulation results of the upper arm in
the DC/DC converter with series-connected switching
devices. Note that Fig.9 (a) is depicts the waveform when
the C snubber is not applied. According to Fig.9 (a), thevoltage unbalance of 20.0% occurs due to the parasitic
parameter mismatch between CCE1 and CCE2. On the other
hand, as shown in Fig.9 (b), the voltage unbalance between
Vce1 and Vce2 is suppressed significantly by the C snubber.
The upper arm switching devices is confirmed to achieve
ZVS without the TCM operation.
Fig. 10 shows the simulation results of the lower arm in
the DC/DC converter with the series-connected switching
devices. Note that Fig. 10 (a) is depicts the waveforms
when the C snubber is not applied, whereas Fig.10 (b)shows the waveforms when the C snubber is applied. The
voltage unbalance reduction thanks to the C snubber sameas Fig. 9 is confirmed. According to Fig. 10 (a) and (b), thelower arm switching devices also achieves ZVS operation
due to the TCM operation.
Fig. 11 shows the simulation results of the lower arm in
the DC/DC converter with the delay time. Note that Fig.
11 (a)’s snubber capacitance is 4 nF. It is lower than thedesigned value of the C snubber. According to Fig. 11 (a),the delay time between S3 and S4 is 5 ns. The turned-off
period is different between S3 and S4 caused by the delay
time. Consequently, the voltage unbalance occurs between
series-connected devices caused by the delay time. On theother hand, in Fig. 11 (b) the snubber capacitance of 8.65
nF is employed. According to the Fig. 11 (b), the slope ofcollector-emitter voltage is less steep compared with thatin Fig. 11 (a). The high snubber capacitance connected tothe switching devices between collector and emitter
reduces the influence of the delay time among the seriesconnected devices.
B. Experimental results for effectiveness confirmation of
proposed method
Fig. 12 shows the test circuit which employs the proposed
voltage balance method. Note that this experiment isconducted for the fundamental evaluation of the proposed
method. In addition, IGBTs are installed in this experimentbecause the voltage unbalance compensation principle issimilar between IGBT and SiC-MOSFET.
Fig. 13 shows the experimental results of the test circuit.
Note that Fig. 13 (a) is not applied the proposed voltage
balance method. According to Fig. 13 (a), the voltage
unbalance of 29.2% occurs due to the parasitic parametermismatch. On the other hand, as shown in Fig. 13 (b), theQuantity

SymbolValue

Input voltage
Output voltage
Switching frequency
boost inductanceCollector-emitter
parasitic capacitance(Vce = 30 V)
Mismatch of theParasitic capacitance

Vin
Vout
fsw
L

200 V
300 V
20 kHz290 µHCce

1.2 nF-20%

Snubber capacitanceCsnubber

8.65 nF

1.0

Upper arm gate signal
Cce1=0.96 nF
Cce2=1.44 nF

0.5

Delay time
does not exist

0.0[V] 20% voltage unbalance occurs

S1

100

177 V

Upper arm
Collectoremitter voltage

S2

118 V

0

ZVS achieved(a) Without C snubber circuit.
1.0

Upper arm gate signal
Delay time
does not exist

Cce1=9.52 nF
Cce2=10 nF

0.5
0.0

S1

[V]
150
100

149 V 142 V

50

Upper arm
Collector-emitter
voltage

S2

0

ZVS achieved(b) With C snubber circuit
Fig. 9. Simulation results of upper arm in the DC/DC converter
applied series connected switching devices when the parasitic
capacitance is mismatched.
1.0
0.5

Lower arm gate signal
Cce1=1.44 nF
Delay time
Cce2=0.96 nF
does not exist

0.0
[V]
200

S3

179 V
100

S4

116 V

Lower arm
Collector-emitter
voltage

0

ZVS achieved(a) Without C snubber circuit
1.0
0.5

Lower arm gate signal
Cce1=10 nF
Delay time
Cce2=9.52 nF
does not exist

0.0
[V]
150

Lower arm
Collectoremitter voltage

100
50

153 V 145 V

0

ZVS achieved(b) With C snubber circuit
Fig. 10. Simulation results of lower arm in the DC/DC converter
applied series connected switching devices when the parasitic
capacitance is mismatched.

voltage unbalance between Vce1 and Vce2 is 4.2%. Thus, theproposed method is confirmed validity by test circuit.
VI.

Lower arm gate signal

CONCLUSION

In this paper, the voltage balancing method with the C
snubber and the ZVS achievement was proposed. The
voltage unbalance of the series-connected switching
devices was compensated by the simple snubber capacitor
circuit. In particular, the switching losses were drasticallyreduced due to the ZVS operation. The validity of the
proposed method was tested by a simulation model. The
simulation model was the DC/DC converter with theseries-connected switching devices. The circuit is appliedwith the TCM operation to achieve the ZVS operation in
the lower arm switching devices in the DC/DC converter.
According to the simulation results, the DC/DC converter
simulation model achieved the ZVS operation at the botharms. The application of the C snubber circuit reduced thevoltage unbalance caused by the parasitic capacitance ofthe switching devices. Moreover, the C snubber also
reduced the influence of the delay time among the seriesconnected switching devices. Finally, in order to confirm
the effectiveness of the proposed method, the boost
converter applied with the proposed method is
experimented. According to the experimental result, thevoltage unbalance is reduced due to the application of the
proposed method.
In the future work, the DC/DC converter and the TCM
operation will be conducted in the experiment.
REFERENCES[1]

Tdelay = 5 ns
1.0

N. Flourentzou, Agelidis. V, and Demetriades. G, “VSCBased HVDC Power Transmission Systems: An Overview”
IEEE Transactions on Power Electronics, Vol.24, (3),pp.592-602 (2009)[2] R. T. Naayagi, and S. K. Panda “Fault-tolerant converter for
future offshore wind farm HVDC networks” 2017 IEEE
Innovative Smart Grid Technologies - Asia (ISGT-Asia)[3] Y. Wang, K. Wang, C. Li, Z. Zheng, and Y. Li, “SystemLevel Efficiency Evaluation of Isolated DC/DC Converters
in Power Electronics Transformers for Medium-Voltage DC
Systems” IEEE Access (2019)[4] Yusuke Hayashi, and Tamotsu Ninomiya, “Highly Scalable
Sensorless Multicellular AC-DC Transformer (ADX) for
the DC Distribution System in Data Centers” IEEJ J.
Industry Applications, vol. 7, no. 6, pp. 479-487, 2018.
[5] Yusuke Hayashi, Yoshikatsu Matsugaki, and Tamotsu
Ninomiya, “Capacitively Isolated Multicell Dc-Dc
Transformer for Future Dc Distribution System” IEEJ J.
Industry Applications, vol. 6, no. 4, pp. 268-277, 2017.
[6] Yue Yu, Keisuke Masumoto, Keiji Wada, and Yuichi Kado,“A DC Power Distribution System in a Data Center using a
Triple Active Bridge DC-DC Converter” IEEJ J.Industry
Applications, vol. 7,no .3, pp. 202-209, 2018.
[7] S. Dimitrijev, and P. Jamet, “Advances in SiC PowerMOSFET technology”, Microelectronics Reliability, Vol.43,
pp.225-233 (2013)[8] K. Vechalapu, A. Negi, and S. Bhattacharya “Performance
evaluation of series connected 15 kV SiC IGBT devices for
MV power conversion systems” 2016 IEEE Energy
Conversion Congress and Exposition (ECCE)[9] S. Ji, T. Lu, Z. Zhao, H. Yu, and F. Wang “Active voltage
balancing control for 10kV three-level converter using
series-connected HV-IGBTs” 2016 IEEE Applied PowerElectronics Conference and Exposition (APEC)[10] K. Vechalapu, S. Hazra, U. Raheja, A Negi, and S.
Bhattacharya “High-speed medium voltage (MV) drive
applications enabled by series connection of 1.7 kV SiC

0.5
0.0
[V]
150

S3

100

Lower arm
Collectoremitter voltage

S4

50
0

Slope of the collector-emitter voltage is sudden.
(a) C snubber capacitance of 4 nF

Tdelay = 5 ns
1.0

Lower arm gate signal

0.5
0.0
[V]
150

S3

Lower arm
Collectoremitter voltage

S4

100
50
0

Slope of the collector-emitter voltage is less steep.
(b) C snubber capacitance of 8.65 nF
Fig. 11. Simulation results of DC / DC converter with and C snubber
capacitor when the gate signal has delay time.
Rated power:500 W
Input voltage:100 V
Output voltage:192 V Sw1
Input current:5 A
Inductor:2 mH
Switching frequency:10 kHz
Dead time:2 µs
IGBT:FGW50N60VD(Fuji Electric) Sw
2
CCE_nom.:215 pF
Lchop
Vin

+

CCE1
VCE1

CCE2
VCE2

Csnubber1
1.44nF
Rout Vout
Csnubber2+
1.45nF
Cout

Swlow

Cin

Fig. 12. Test circuit employed with the proposed voltage balancemethod.

MOSFET devices” 2017 IEEE Energy Conversion
Congress and Exposition (ECCE)[11] K. Vechalapu, and S. Bhattacharya “Performancecomparison of 10 kV-15 kV high voltage SiC modules andhigh voltage switch using series connected 1.7 kV LV SiC
MOSFET devices” IEEE ECCE 2016 (2016)[12] Y. Han, W. Chen, X. Chen, X. Ma, Y. Sha, X. Yang, and X.
Li “A 4000 V input auxiliary power supply with seriesconnected SiC MOSFETs for MMC-based HVDC system”,
Power Electronics and Motion Control Conference(IPEMC-ECCE Asia), 2016 IEEE 8th International, pp.279284 (2016)[13] L. Wang, D. zhang, and Y. Wang “High performance solidstate switches using series-connected SiC-MOSFETs forhigh voltage applications”, IPEMC-ECCE Asia, 2016 IEEE
8th International, pp.1674-1679 (2016)[14] K. Shingu, and K. Wada, “Digital control based voltage
balancing for series connected SiC MOSFETs underswitching operations”, in Proc. IEEE Energy Conversion
Congress and Exposition, 2017, pp. 5495-5500 (2017)[15] K.Shingu, and K. Wada, ”Voltage Balancing Control for
Series Connected MOSFETs Based on Time DelayAdjustment Under Start-Up and Steady-State Operations“ 2018 IEEE Energy Conversion Congress and Exposition(ECCE)[16] P. Wang, F. Gao, Y. jing, Q. Hao, K. Li, and H. Zhao, “AnIntegrated Gate Driver with Active Delay Control Method
for Series Connected SiC MOSFETs” 2018 IEEE 19th
Workshop on Control and Modeling for PowerElectronics(COMPEL)[17] Piotr Czyz, Thomas Guillod, Florian Krismer, and Johann
W. Kolar “Exploration of the Design and PerformanceSpace of a High Frequency 166 kW / 10 kV SiC Solid-State
Air-Core Transformer” The 2018 International PowerElectronics Conference[18] Yan-Kim Tran, and Drazen Dujic, “A multiport medium
voltage isolated DC-DC converter” IECON 2016 - 42nd
Annual Conference of the IEEE Industrial Electronics
Society[19] S. charya, R Chattopadhyay, A. Anurag, S. Rengarajan, Y.
Prabowo, and S. Bhattachary, “High Power Medium
Voltage 10 kV SiC MOSFET Based Bidirectional Isolated
Modular DC-DC Converter”, IPEC-ECCE Asia (2018)[20] Hoai Nam Le, Koji Orikawa, Jun-ichi Itoh “Zero-Voltage
Switching for Bidirectional Buck/Boost Converter using
Hybrid Discontinuous Current Mode” 2016 IEEE 17th
Workshop on Control and Modeling for Power Electronics(COMPEL), Trondheim, 2016, pp. 1-8.

8[µs/div]
029.2% voltage unbalance occurs
due to parasitic capacitancemismatch
vGE1[20V/div]0

vGE2[20V/div]vCE1[100V/div]

68V

0

124V

0

vCE2[100V/div](a) Without proposed method8[µs/div] The voltage unbalance

reduced by 86.0%.
0vGE1[20V/div]0

vGE2[20V/div]0

92V

vCE1[100V/div]

0

100V

vCE2[100V/div]

ZVS(b) With proposed method
Fig. 13. Experimental results of test circuit for effectivenessconfirmation of proposed method.