APPLICATION NOTE
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Impact of Stray Inductanceon EliteSiC Power and
VE-Tract IGBT Module's
Switching Characteristics
AND90238/D
Introduction

The IGBT and SiC module’s switching characteristics are affectedby many external parameters such as voltage, current, temperature,gate configurations and stray elements. This document centers aroundthe influence of the DC−link loop inductance and gate loop inductanceon the switching characteristics for the VE−Trac IGBT and EliteSiC
Power modules.

VE−Trac Direct Module − NVH950S75L4SPB

Test Setup

The Double Pulse Test (DPT) setup is used to extract the switching
characteristics of the SiC and IGBT modules. For the DC−link loop
inductance impact analysis, added the busbars between the DC−link
capacitor and module, as shown in Table 1 And for the gate loop
inductance impact analysis, the external sockets or wires were added
between the gate driver board and module, as shown in Table 10.
In order to investigate the module switching characteristics, the 900 V,
1.7 mW class EliteSiC Power Module (NVXR17S90M2SPC)
a n d 7 5 0 V c l a s s F i e l d S t o p 4 V E −Tr a c D i r e c t M o d u l e(NVH950S75L4SPB) are used as DUTs.

EliteSiC Power Module − NVXR17S90M2SPB

D

D
G

G

2
S
D

G

2
S

1

D

3

Double Pulse

Double Pulse
S

1
3

G
S

Current Sense

Current Sense

Figure 1. Double Pulse Test Setup© Semiconductor Components Industries, LLC, 2023

August, 2023 − Rev. 0

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Publication Order Number:AND90238/D

AND90238/D
Table 1. DC−LINK LOOP INDUCTANCE TEST SETUP
Test Case(Loop Inductance)

23 nH

30 nH

37 nH

No additional bus bar+ short bus bar (7 nH)+ long bus bar (14 nH)

Test Configuration

IGBT Switching Characteristics vs. DC−Link Loop
Inductance (LS)

Table 1 shows test setups for three different DC−link loop
inductance configurations to analyze the impact of DC−linkloop inductance.
Figure 2 illustrates waveform comparison by different
DC−link loop inductance setups during the IGBT turn−on,
and summarized characteristics are described in Table 1
below. A higher loop inductance setup shows a higher
inductive VCE voltage drop with a slower turn−on di/dt. As
a result, a higher loop inductance leads to lower turn−on loss
because the loss is an integral of VCE and IC with time.
In terms of the diode, after the reverse recovery peakcurrent (Irrm), higher loop inductance impacts the diode peakvoltage overshoot. Therefore, a higher loop inductanceconfiguration setup impacts higher reverse recovery loss
from snappy recovery. Consequently, RG(on) increase isnecessary for EMI compatibility.

This section analyzes the impact of different DC−linkinductances on the IGBT switching characteristics. A
double pulse test was performed on the NVH950S75L4SPB
module with the following conditions.

• DUT: FS4 750V 950A IGBT Module(NVH950S75L4SPB) Low side
• VDC = 400 V• IC = 600 A• VGE = +15/−8 V• RG(on) = 4.0 W• RG(off) = 12.0 W• Tvj = 25°C

• VCE & VF: 100 V/div• VGE: 10 V/div• IC: 200 A/div• Time: 200 ns/div
Figure 2. IGBT Turn−on Waveforms vs. DC−Link Loop Inductance (LS)

Table 2. SUMMARY OF IGBT TURN−ON CHARACTERISTICS VS. DC−LINK LOOP INDUCTANCE
Test Case

23 nH

30 nH

37 nH

Eon

24.0 mJ

21.4 mJ

18.6 mJdi/dt (20−80%)

4.5 A/ns

4.4 A/ns

4.3 A/ns

VF.peak

475 V

535 V

609 V

Err

3.0 mJ

3.4 mJ

3.7 mJ

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AND90238/D

Figure 3 illustrates a waveform comparison between
different DC−link loop inductance setups during the IGBT
turn−off event. Summarized characteristics are described inTable 3 below. A higher loop inductance setup shows aslower di/dt during the turn−off but a higher VCE peakvoltage due to the stray inductance. As a result, higher loop
inductance leads to higher turn−off loss because the losses
are integral of VCE and IC with time. However, a higher VCE

peak voltage can exceed the VCE voltage breakdown limit
during high current driving. Hence increasing the RG(off) is
highly recommended to suppress the peak voltage andoscillations. Additionally, the adherence to reverse bias safe
operating area (RBSOA) is an essential system design factor
that shall be considered according to the stray inductanceand turn−off speed.

• VCE & VF: 100 V/div• VGE: 10 V/div• IC: 200 A/div• Time: 200 ns/div
Figure 3. IGBT Turn−off Waveforms vs. DC−Link Loop Inductance (LS)

Table 3. SUMMARY OF IGBT TURN−OFF CHARACTERISTICS VS. DC−LINK LOOP INDUCTANCE
Test Case

23 nH

30 nH

37 nH

Eoff

33.8 mJ

37.6 mJ

40.0 mJdV/dt (20−80%)

5.0 V/ns

5.4 V/ns

5.7 V/ns−di/dt (85−55%)

9.1 A/ns

8.1 A/ns

7.2 A/ns

VCE.peak

608 V

643 V

666 V

IGBT Switching Characteristics vs. DC−Link Loop
Inductance (LG) with Optimized RG

overvoltage causes a worse RBSOA performance, so
adjusting the RG(off) is required based on the DC−link loop
inductance. Figure 4 illustrates a waveform comparison
between the DC−link loop inductance setups with optimized
RG(on) during the IGBT turn−on. Tuned the RG(on) till it has
a similar VF level with the original 23 nH test setup because
the VF peak and oscillation is one of the significant EMI
noise sources at the MHz range. As a result, a higher
DC−link loop inductance setup with an optimized RG(on)shows a higher Eon with a slower di/dt.

A higher DC−Link loop inductance setup has a lower Eon
by higher VCE voltage drop during the turn−on. By the way,from the system level consideration, it is mandatory toincrease RG(on) to have a similar EMI level with the lower
DC−Link inductance.
In the case of the IGBT, the DC−link inductance plays animportant role in the level of the VCE overshoot voltage
during the turn−off because the turn−off di/dt is not thatsignificantly affected by the external RG(off). A higher VCE

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AND90238/D• VCE & VF: 100 V/div• VGE: 10 V/div• IC: 200 A/div• Time: 200 ns/div
Figure 4. IGBT Turn−on Waveforms vs. DC−Link Loop Inductance with Optimized RG(on)Table 4. SUMMARY OF IGBT TURN−ON CHARACTERISTICS VS. DC−LINK LOOP INDUCTANCE WITH OPTIMIZEDRG(on)
Test Case

23 nH

30 nH

37 nH

RG(on)

4.0 W

6.8 W

9.2 W

Eon

24.0 mJ

27.7 mJ

31.3 mJdi/dt (20−80%)

4.5 A/ns

3.3 A/ns

2.7 A/ns

VE.peak

475 V

472 V

470 V

Err

3.0 mJ

2.4 V

2.3 mJ

for the higher loop inductance setups. As a result, a higher
DC−link loop inductance setup shows a higher Eoff with aslower dV/dt.

Figure 5 illustrates a waveform comparison between the
DC−link loop inductance setups with optimized RG(off)during the IGBT Turn−off. To keep the VCE overshoot level
similar to the original 23 nH setup, a higher RG(off) was used

• VCE & VF: 100 V/div• VGE: 10 V/div• IC: 200 A/div• Time: 200 ns/div
Figure 5. IGBT Turn−off Waveforms vs. DC−Link Loop Inductance with Optimized RG(off)www.onsemi.com
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AND90238/D
Table 5. SUMMARY OF IGBT TURN−OFF CHARACTERISTICS VS. DC−LINK LOOP INDUCTANCE WITH
OPTIMIZED RG(off)Test Case

23 nH

30 nH

37 nH

RG(off)12.0 W

16.0 W

20.0 W

Eoff

33.8 mJ

35.0 mJ

39.4 mJdV/dt (20−80%)

5.0 V/ns

4.8 V/ns

4.6 V/ns−di/dt (85−55%)

9.1 A/ns

7.1 A/ns

5.2 A/ns

VCE.peak

608 V

606 V

607 V

SiC MOSFET Switching Characteristics vs. DC−Link
Loop Inductance (LS)

Figure 6 illustrates waveform comparison by different
DC−link loop inductance setups during the SiC MOSFET
turn−on and summarized characteristics are described inTable 6 below. The higher loop inductance setup shows ahigher inductive VDS voltage drop with a slower turn−on
di/dt. As a result, this leads to lower turn−on loss because theloss is integral of VDS and ID with time.
In terms of the body diode, after the reverse recovery peakcurrent, higher loop inductance impacts the diode peakvoltage. Therefore, a higher loop inductance configuration
setup impacts higher reverse recovery loss with snappyrecovery. As a consequence of snappy recovery, increasing
the RG(on) may require compatibility with the EMI.
Additionally, in the SiC MOSFET case, the EMI
compatibility is more critical than the IGBT because it has
a larger oscillation amplitude and frequency that can work
as a noise source.

In this section, the impact of different DC−linkinductances on the SiC MOSFET switching characteristics
is analyzed. A double pulse test was performed on the
NVXR17S90M2SPC module in the same test setup as
Table 1 with the following conditions.

• DUT: NVXR17S90M2SPC Low side
• VDC = 400 V• ID = 600 A• VGS = +18/−5 V• RG(on) = 3.9 W• RG(off) = 1.8 W• Tvj = 25°C

• VDS & VSD: 100 V/div• VGS: 10 V/div• ID: 200 A/div• Time: 200 ns/div
Figure 6. SiC MOSFET Turn−on Waveforms vs. DC−Link Loop Inductance

Table 6. SUMMARY OF SiC TURN−ON CHARACTERISTICS VS. DC−LINK LOOP INDUCTANCE
Test Case

23 nH

30 nH

37 nH

Eon

14.3 mJ

12.7 mJ

10.4 mJdi/dt (20−80%)

6.0 A/ns

5.7 A/ns

5.4 A/ns

VSD.peak

567 V

639 V

679 V

Err

0.7 mJ

1.0 mJ

1.6 mJ

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5AND90238/D

Figure 7 illustrates waveform comparison by different
DC−link loop inductance setups during the SiC MOSFET
turn−off and summarized characteristics are described inTable 7 below. A higher loop inductance setup shows aslower di/dt during the turn−off but a higher VDS peakvoltage due to the inductance. As a result, a higher loop
inductance leads to higher turn−off loss because the loss isan integral of VDS and ID with time. However, a higher VDS

peak voltage can exceed the VDS voltage limit during highcurrent driving. Hence increasing the RG(off) is highly
recommended to suppress the peak voltage and oscillations.
Additionally, the adherence to reverse bias safe operatingarea (RBSOA) and compatibility with the EMI regulation isan essential system design factor that shall be consideredaccording to the stray inductance and turn−off speed.

• VDS & VSD: 100 V/div• VGS: 10 V/div• ID: 200 A/div• Time: 200 ns/div
Figure 7. SiC MOSFET Turn−off Waveforms vs. DC−Link Loop Inductance

Table 7. SUMMARY OF SiC TURN−OFF CHARACTERISTICS VS. DC−LINK LOOP INDUCTANCE
Test Case

23 nH

30 nH

37 nH

RG(off)

1.8 W

3.3 W

4.5 W

Eoff

15.3 mJ

24.8 mJ

32.9 mJdV/dt (20−80%)

8.5 V/ns

5.8 V/ns

4.4 V/ns−di/dt (80−20%)

10.4 A/ns

7.3 A/ns

5.9 A/ns

VDS.peak

647 V

645 V

645 V

SiC MOSFET Switching Characteristics vs. DC−Link
Loop Inductance (LG) – Optimized RG

inductance setup. Figure 8 illustrates a waveformcomparison between the DC−link loop inductance setups
with optimized RG(on) during the SiC MOSFET Turn−on.
Tuned the RG(on) till it has a similar VSD level with theoriginal 23 nH test setup because the VSD peak andoscillation is one of the significant EMI noise sources at the
MHz range. As a result, a higher DC−link loop inductancesetup shows a higher Eon with a slower di/dt.

A higher DC−Link loop inductance setup has a lower Eon
by higher VDS voltage drop during the turn−on. By the way,from the system level consideration, it is mandatory toincrease RG(on) to compensate for the VSD voltage
peak/amplitude and EMI level. Furthermore, higher VDS
overvoltage causes a worse RBSOA performance, so
adjusting the RG(off) is required based on the DC−link loop

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AND90238/D• VDS & VSD: 100 V/div• VGS: 10 V/div• ID: 200 A/div• Time: 200 ns/div
Figure 8. SiC MOSFET Turn−on Waveforms vs. DC−Link Loop Inductance with Optimized RG(on)Table 8. SUMMARY OF SiC TURN−ON CHARACTERISTICS VS. DC−LINK LOOP INDUCTANCE WITH OPTIMIZEDRG(on)
Test Case

23 nH

30 nH

37 nH

RG(on)

4.0 W

6.0 W

8.2 W

Eon

18.2 mJ

24.5 mJ

31.4 mJdi/dt (20−80%)

5.3 A/ns

3.8 A/ns

2.9 A/ns

VSD.peak

552 V

552 V

555 V

Err

0.4 mJ

0.7 mJ

0.7 mJ

RG(off) was used for the higher loop inductance setups. As
a result, a higher DC−link loop inductance setup shows ahigher Eoff with a slower dV/dt.

Figure 9 illustrates a waveform comparison between the
DC−link loop inductance setups with optimized RG(off)during the SiC MOSFET Turn−off. To keep the VDS
overshoot level similar to the original 23 nH setup, a higher• VDS & VSD: 100 V/div• VGS: 10 V/div• ID: 200 A/div• Time: 200 ns/div
Figure 9. SiC MOSFET Turn−off Waveforms vs. DC−Link Loop Inductance with Optimized RG(off)www.onsemi.com
7AND90238/D
Table 9. SUMMARY OF SiC TURN−OFF CHARACTERISTICS VS. DC−LINK LOOP INDUCTANCE
Test Case

23 nH

30 nH

37 nH

Eoff

17.0 mJ

19.4 mJ

21.8 mJdV/dt (20−80%)

8.9 V/ns

9.0 V/ns

9.1 V/ns−di/dt (80−20%)

10.4 A/ns

8.9 A/ns

8.5 A/ns

VDS.peak

647 V

717 V

774 V

Case 1Case 2

Case 3

No additional element+ additional socket (5 cm)+ external wire (20 cm)

Table 10. GATE LOOP INDUCTANCE TEST SETUP
Test Case(Loop Inductance)
Test Configuration

IGBT Switching Characteristics vs. Gate Loop
Inductance (LG)Figure 10 illustrates waveform comparison by different
gate loop test setups during the IGBT turn−on, andsummarized characteristics are described in Table 11 below.
A longer gate loop test setup shows a lower Eon with fasterdi/dt. A gate loop inductance is mainly caused by gate loop
length. The gate loop inductance can slow down the rising
current at the beginning of the turn−on. When the gate
voltage reaches the miller plateau, the loop inductanceworks as a current source. This current source can speed up
the di/dt by sourcing more current to the gate. The impact on
the turn−on characteristics by gate loop length is lesssignificant than the DC−link loop. Meanwhile, a higher gateloop inductance can increase the overshoot of the gate
voltage, which can lose controllability by RG.

Furthermore, the gate loop inductance influences theswitching characteristics. A double pulse test was
performed on the NVH950S75L4SPB module with thefollowing conditions.

• DUT: FS4 750V 950A IGBT Module(NVH950S75L4SPB) Low side

• VDC = 400 V• IC = 600 A• VGE = +15/−8 V• RG(on) = 4.0 W• RG(off) = 12.0 W• Tvj = 25°C

Table 10 shows three different test setups for the gate loop
inductance vs. switching characteristics. The external
socket or extended wires are added between the gate driverand module to simulate a higher loop inductance on the gate
loop.

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AND90238/D• VCE & VF: 100 V/div• VGE: 10 V/div• IC: 200 A/div• Time: 200 ns/div
Figure 10. IGBT Turn−on Waveforms vs. Gate Loop Inductance (LG)

Table 11. SUMMARY OF IGBT TURN−ON CHARACTERISTICS VS. GATE LOOP INDUCTANCE
Test Case

Case 1Case 2

Case 3Eon

22.6 mJ

22.2 mJ

21.6 mJdi/dt (20−80%)

4.5 A/ns

4.6 A/ns

4.8 A/ns

VF.peak

475 V

475 V

474 V

Err

3.0 mJ

3.4 mJ

3.7 mJ

Figure 11 illustrates a waveform comparison between
different gate loop inductance setups during the IGBT
turn−off event. Summarized characteristics are described inTable 12 below. The turn−off characteristics are less impact
than the turn−on characteristics. At the beginning of theturn−off, the undershoot voltage is slightly different by gateloop inductance, but it cannot impact the turn−offcharacteristics. When gate voltage reaches the miller
plateau, dV/dt and di/dt are slightly changed by undershootbut are quickly covered by gate sink current within a shorttransient.

• VCE & VF: 100 V/div• VGE: 10 V/div• IC: 200 A/div• Time: 200 ns/div
Figure 11. IGBT Turn−off Waveforms vs. Gate Loop Inductance (LG)www.onsemi.com
9AND90238/D
Table 12. SUMMARY OF IGBT TURN−OFF CHARACTERISTICS VS. GATE LOOP INDUCTANCE (LG)Test Case

Case 1Case 2

Case 3Eoff

31.5 mJ

31.2 mJ

31.2 mJdV/dt (20−80%)

5.0 V/ns

5.0 V/ns

5.1 V/ns−di/dt (85−55%)

9.1 A/ns

9.1 A/ns

9.3 A/ns

VCE.peak

602 V

604 V

608 V

• VGS = +18/−5 V• RG(on) = 3.9 W• RG(off) = 1.8 W• Tvj = 25°C

SiC MOSFET Switching Characteristics vs. Gate Loop
Inductance (LG)In this section, the impact of different gate loon
inductances on the SiC MOSFET switching characteristics
is analyzed. A double pulse test was performed on the
NVXR17S90M2SPC module in the same test setup as
Table 10 with the following conditions.

Figure 12 shows waveform comparison by different gateloop test setups during the SiC MOSFET turn−on, andsummarized characteristics are described in Table 13 below.
As in the IGBT case, a longer gate loop test setup shows alower Eon and higher VSD.peak voltage by faster di/dt.

• DUT: NVXR17S90M2SPC Low side
• VDC = 400 V• ID = 600 A• VDS & VSD: 100 V/div• VGS: 10 V/div• ID: 200 A/div• Time: 200 ns/div
Figure 12. SiC MOSFET Turn−on Waveforms vs. Gate Loop Inductance (LG)

Table 13. SUMMARY OF SiC MOSFET TURN−ON CHARACTERISTICS VS. GATE LOOP INDUCTANCE
Test Case

Case 1Case 2

Case 3Eon

16.3 mJ

16.2 mJ

15.3 mJdi/dt (20−80%)

5.1 A/ns

5.1 A/ns

5.4 A/ns

VSD.peak

558 V

563 V

581 V

Err

0.5 mJ

0.6 mJ

0.7 mJ

Figure 13. illustrates a waveform comparison between
different gate loop inductance setups during the SiC
MOSFET turn−off event. Summarized characteristics aredescribed in Table 14 below. A higher gate loop inductancetest setup shows a lower Eoff with a faster di/dt even thougha higher VDS overshoot voltage. After tun−off, the ID
oscillation amplitude that could be an EMI noise source
depends on the length of the gate loop.

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10AND90238/D• VDS & VSD: 100 V/div• VGS: 10 V/div• ID: 200 A/div• Time: 200 ns/div
Figure 13. SiC MOSFET Turn−off Waveforms vs. Gate Loop Inductance (LG)

Table 14. SUMMARY OF SiC MOSFET TURN−OFF CHARACTERISTICS VS. GATE LOOP INDUCTANCE
Test Case

Case 1Case 2

Case 3Eoff

14.8 mJ

14.8 mJ

14.2 mJdV/dt (20−80%)

9.1 V/ns

9.2 V/ns

9.5 V/ns−di/dt (80−20%)

10.3 A/ns

10.5 A/ns

11.8 A/ns

VDS.peak

672 V

679 V

702 V

Summary

the other parameters for the system performance ismandatory, although it loses di/dt controllability andswitching losses. Figure 14 and Figure 15 illustrate an IGBTand SiC switching loss comparison result by DC−link loop
inductance with/without the external RG optimization.
Before optimizing the external RG, a higher DC−link loop
inductance setup shows similar total switching losses, but
after external RG optimization for the system performance,
the total loss is a 20% and 92% increase in each IGBT and
SiC case when DC−link loop inductance changes from
23 nH to 37 nH.

In this application note analyzes the impact of theinductance on the IGBT and SiC MOSFET module’s
switching characteristics.
A higher DC−link loop inductance setup brings lower Eon
while higher Eoff and Err. Furthermore, the overall result
seems to be that a total switching loss gap between the 23 nH
and 37 nH test setup is less than 2 mJ. Thus, it can easily
misunderstand that the stray inductance does not have a big
impact on the switching losses. However, to adhere to the
RBSOA and EMC, adjusting the external gate resistance or

Figure 14. IGBT Total Losses Comparison

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AND90238/D

Figure 15. SiC MOSFET Total Switching Losses Comparison

to the gate. In terms of the short circuit event, this inductancecan pull up the gate voltage, thus, it will have a shortened
short circuit withstand time by the increased gate voltage. In
addition, a longer gate loop has less electromagnetic noise
immunity or interferes with the other circuitry because it canwork as an antenna.

A higher gate loop inductance setup brings a slightly
faster turn−on transient by inductive effect after the miller
plateau. And it is a less significant impact than the DC−linkloop inductance from the switching loss point of view.
However, because of the unwanted gate overshoot, a higher
gate loop inductance setup will bring lower controllability

Figure 16. IGBT/SiC Switching Losses vs. Gate Loop InductanceIn conclusion, minimizing DC−link and gate loop
inductance is essential for the IGBT/SiC switching

application to get lower switching losses with controllability
and EMC.

VE−Trac is a trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or othercountries.
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