APPLICATION NOTE
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MOSFET Selection for Reverse Polarity Protection
AND90146/D
OVERVIEW
When the vehicle’s battery is damaged and needs
replacement the probability of connecting the new battery
in reverse is high. Since many electronic control units(ECU) in the vehicle are connected to the vehicle’s battery,such an event could lead to numerous ECU failures.
Additionally, automotive standards like ISO (International
Organization for Standardization) defines the testing
methods, voltage levels, limits for electromagnetic emission
for electrical and electronic devices to ensure the safe andrugged operation of the system. One such standard related
to reverse polarity protection (RPP) is ISO 7637−2:2011
which replicates the various voltage scenarios like in the realapplication and the system needs to withstand such voltages
to showcase the robustness against failures. This madereverse polarity protection a crucial building block that isrequired by all automotive vehicle manufacturers for any
battery connected ECU/system.
This application note will first address the ISO pulses thatare commonly used to replicate the voltage transients that
could appear in real applications. It will then give details
about several protection techniques that could be used,
before helping to guide the reader to select an external
N−Channel MOSFET, that will provide RPP and help
reduce the power losses of the system. Finally, a listof recommended N−Channel MOSFETs to be used alongwith an ideal diode controller, based on the battery current
will be provided.

These test pulses come with different negativeand positive voltage levels to stress the DUT to see if it canwithstand. For example, Pulse 3b is shown in Figure 1
to give an idea about the type of pulses that are defined in
the standard, each pulse will have its own parameters as
in Table 1. Pulse 3b simulates the switching noise in the realapplication, such as relay and switch contact bouncing
which can produce a short burst of high frequency pulses.
AND8228/D talks in more details about voltage transientsand testing methods.
0.9 USUS
0.1 US
tr
td
V
t1

US
UA
0

July, 2023 − Rev. 1tt5

Figure 1. Test Pulse 3b

ISO PULSESISO 7637−2:2011 is an international standard which
specifies test methods and procedures to ensure
the compatibility to conducted electrical transientsof equipment installed on passenger cars and commercial
vehicles fitted with 12 V or 24 V electrical systems. Refer
to ISO 7637−2:2011 for detailed information.
Under this standard there are several types of test pulsesthat are defined to test the device. Below are few of the test
pulses.
− Pulse 1: Transients due to supply disconnectionof inductive loads.
− Pulse 2a: Transients due to sudden interruptionof currents in a device connected in parallel with the DUT(Device Under Test), due to the inductance of the wiring
harness.
− Pulse 3a & 3b: Transients which occur as a resultof switching processes. The characteristics of thesetransients are influenced by distributed capacitanceand inductance of the wiring harness.

© Semiconductor Components Industries, LLC, 2022

t4

Table 1. PARAMETERS OF TEST PULSE 3b

1

Parameters

Nominal 12 V System

Nominal 24 V System

US+75 V to +150 V+150 V to +300 V

Ri

50 W

td

150 ns ±45 ns

tr

5 ns ±1.5 ns

t1

100 ms

t4

10 ms

t5

90 ms

Publication Order Number:AND90146/D

AND90146/D
REVERSE POLARITY PROTECTIONTECHNIQUESIn the following section the three most common
techniques used for reverse polarity protection are
discussed.

only conduct current when the correct polarity is applied to
its terminals (i.e., forward biased). The forward voltage
drop, VF for a standard diode is around 0.7 V, while for a
Schottky diode it can be as low as 0.3 V. As a result, mostapplications use a Schottky diode, to reduce system losses.

Diode

The simplest way to protect a system from a reverse
battery is by using a diode. As shown in Figure 2, a diode will
Current Flow
Diode Conductive

+
−

VBAT

Reverse Current
Diode Nonconductive

+
Load
−

VBAT

GND

−
+

+
Load
−

GND

Figure 2. Reverse Polarity Protection using a Diode

Figure 3 shows the typical voltage drop of the
NRVBSS24NT3G Schottky diode. If the diode current(IDIODE) increases from 0.5 A to 1.0 A (100% increase), VF

increases from 0.35 V to 0.40 V (15% increase) at a junction
temperature TJ of 25°C.

Figure 3. Typical Forward Voltage of NRVBSS24NT3G Schottky Diode
MOSFETbattery is properly connected, the intrinsic body diode isconductive till the MOSFET’s channel is turned ON. To turn
ON a P−Channel MOSFET, the gate voltage needs to belower than the source voltage by at least the thresholdvoltage VT. When the battery is reversely connected, thebody diode is reversed biased, gate and source have the same
voltage thus turning OFF the P−Channel MOSFET. An
additional Zener diode is used to clamp the gate of the
P−Channel MOSFET and protect it in the case of a too highvoltage.

An alternative to a diode is a MOSFET. When a MOSFET
is conductive, the voltage drop between the drain−source
VDS is dependent on the drain−source resistance RDS,ON andthe drain−source current ID: VDS = RDS,ON * ID. Compared
to a Schottky diode the voltage drop is generally much
lower.
P−Channel MOSFETAs all MOSFETs, a P−Channel MOSFET has an intrinsic
body diode between the source and the drain. When the

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AND90146/D
S

D
P−Channel MOSFET

VBAT

D

S

P−Channel MOSFET

G
+

+
−

VBAT

Load
−

G
+

−
+

Load
−

GND

GND

Figure 4. Reverse Polarity Protection using a P−Channel MOSFETVBAT by at least VT. Hence a dedicated driver is used to drive
the gate voltage of the N−Channel MOSFET higher than thesource voltage, thus turning ON the N−Channel MOSFET.
When the battery is reverse connected, the body diode isreversed biased (anode voltage is lower than cathodevoltage) and the driver is disabled (source and gate areshorted), turning the N−Channel MOSFET OFF.

N−Channel MOSFET
It is also possible to use an N−Channel MOSFET forreverse polarity protection. When the battery is properly
connected (source is connected to VBAT), to turn ON the
MOSFET, the gate−source voltage has to be higher than thethreshold voltage (VGS > VTH). Given that the source isconnected to VBAT, the gate voltage needs to be higher than
S

D

D

S

N−Channel MOSFET

N−Channel MOSFET

G

G
VBAT

+
−

Driver

+
VBAT

Load
−

−
+

Driver

+
Load
−

GND

GND

Figure 5. Reverse Polarity Protection using a N−Channel MOSFET

Comparison of Reverse Polarity Protection Techniques
Table 2 summarizes the advantages and disadvantages ofthe different reverse polarity protection techniques. It is
worth mentioning that P−Channel MOSFET operation
depends upon the mobility of holes, while an N−Channel
MOSFET depends upon the mobility of electrons. Knowingthat the mobility of holes is almost 2.5 times lower than themobility of electrons, for the same drain current, a
P−Channel MOSFET will have a bigger die size and, by
implication, a higher cost compared to that of an N−Channel
MOSFET to achieve the same on−resistance. This makes
N−Channel MOSFETs preferable compared to P−Channel
MOSFETs in such applications.

Table 2. COMPARISON BETWEEN DIFFERENTPROTECTION TECHNIQUESAdvantages− Low cost
− Simple− Higher power
dissipation− Higher voltage drop

MOSFET− Flexibility (various
MOSFETs withvarious RDS,ON)− Higher power
dissipation− Lower operating
voltage drop

− High cost for low RDS,ON− Higher total solution cost(need of additionalcharge pump / controller)− Higher complexity(i.e., gate drive andprotection)www.onsemi.com
3

Disadvantages

Schottky
DiodeAND90146/D
MOSFET SELECTION
There are various parameters to consider when selecting
an N−Channel MOSFET for reverse polarity protection.
• Maximum Breakdown Voltage of the MOSFET
VDS, MAX♦ For 12 V board net (vehicle) VDS, MAX = 40 V ispreferred♦ For 24 V board net (truck) VDS, MAX = 60 V ispreferred• Maximum Operating Junction Temperature TJ, MAX♦ For vehicle and truck applications, 175°C is
recommended given the harsh environment• Gate Level♦ Logic Level is preferred over standard level since
they have a lower RDS,ON for the same gate−source
voltage VGS• Package♦ 3.30 × 3.30 mm (i.e. LFPAK33/WDFN8/m8FL) and5.00 × 6.00 mm (i.e., SO8−FL/LFPAK56) packages
with exposed pad for optimized power dissipation
are commonly used
• Total Gate Charge QG, TOT♦ Turning ON a MOSFET happens in 3 phases− When the gate voltage VGS rises to the plateau
voltage VGP, charges are mainly used to charge
the input capacitance CISS.
− When VGS is at the plateau voltage VGP, charges
are mainly used to charge the reverse transfer
capacitance (gate−to−drain capacitance) CRSS.
− When VGS rises from VGP to driver supply
voltage VGDR, the charges are used to further
enhance the channel.
♦ Lower the QG, TOT, lesser the gate voltage andcurrent needed to turn ON the MOSFET (i.e., fasterturn ON) and vice versa♦ More information about MOSFET Gate−Charge
could be found in the following onsemi applicationnote.
− https://www.onsemi.com/pub/Collateral/
AND9083−D.PDF• Drain−Source Resistance RDS, ON♦ RDS, ON plays a role to limit the power dissipation in
the device. The higher the RDS, ON for a given load
current, the higher is the power dissipation. Higher
losses lead to the increase in TJ of the MOSFET.
Hence it is important to choose the right device withrequired RDS, ON to have optimal performance.
♦ In the following sections, MOSFETs for thermal
evaluation are chosen in such a way that their
RDS, ON will keep power dissipation around 500 mWof losses.

NCV68061 IDEAL DIODE CONTROLLER
The combination of NCV68061 and an external
N−Channel MOSFET replicates an ideal diode which acts
like a perfect conductor when forward biased voltage (anodevoltage is higher than cathode) is applied and like a perfectinsulator when the reverse biased voltage (anode voltage islower than cathode) is applied. The NCV68061 is a reverse
polarity protection and ideal diode N−Channel MOSFET
controller intended as a lower loss and lower forward
voltage replacement for diodes.
The main function of the NCV68061 is to control the
ON/OFF state of an external N−Channel MOSFET
according to the source to drain differential voltage polarity.
Depending on the drain pin connection the device can be
configured in two different application modes. With thedrain pin is connected to the load the application is in ideal
diode mode, whereas with the drain pin connected to groundthe NCV68061 is merely in reverse polarity protection
mode. In both modes, the controller provides a typical gate
voltage of 11.4 V to external N−Channel MOSFET. Hencein all the calculations of following sections, RDS,ON @ 10 V
VGS has been used.
NCV68061 has undergone ISO 7637−2:2011 tests todemonstrate the robustness of the device to withstandvoltage stress. The results are shown in the NCV68061
datasheet.
Ideal Diode Application

Figure 6 shows how the NCV68061 is used in the ideal
diode configuration. In this configuration, the input voltage
is not allowed to discharge the bulk capacitance Cbulk. Thisconfiguration has two modes:− Conduction Mode: Prior to entering the conduction mode,the source voltage is lower than the drain voltage, andboth the charge pump and the N−Channel MOSFET are
disabled. As the source voltage becomes greater than thedrain voltage, the forward current flows through the body
diode of the N−Channel MOSFET. Once this forward
voltage drop exceeds the source to drain gate charge
voltage threshold level (typ. 140 mV), the charge pump isturned ON and the N−Channel MOSFET becomes fully
conductive.
− Reverse Current Blocking Mode: When the source
voltage becomes less than the drain voltage, reverse
current initially flows through the conductive channel ofthe N−Channel MOSFET. This current creates a voltage
drop across the conductive channel of the N−Channel
MOSFET which is proportional to its RDS,ON. When thisvoltage drops below the source to drain gate discharge
voltage threshold (typ. −10 mV), the charge pump is
disabled, and the external N−Channel MOSFET is turned
OFF by an internal P−Channel MOSFET of the controller.

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AND90146/D
BatteryS
GSCS

BatteryS

N−Channel
MOSFET

G
NCV68061

EN

Protected Battery

D

D

G
+

S
CS

Cbulk

G
NCV68061

EN

GND

D
N−Channel
MOSFET
D

Protected Battery

+

Cbulk

GND

Figure 7. NCV68061 Reverse Polarity Protection
Application

Figure 6. NCV68061 Ideal Diode Application
Reverse Polarity Protection

TEST SETUP
A dedicated test board for NCV68061 is used to determine
the power dissipation and thermal performance of thevarious MOSFETs in 3 × 3 and 5 × 6 packages with different
RDS,ON to help to understand the MOSFET selection for theideal diode controller considering various load currents.

By connecting the drain pin to the GND potential, as
shown in Figure 7, the NCV68061 does not allow a falling
input voltage to discharge the output below GND potential
but does allow the output to follow any positive input
voltage above the under−voltage lockout (UVLO)
threshold. This means that the bulk capacitance Cbulk will bedischarged by a falling input voltage.
When the source voltage is above the UVLO threshold(typ. 3.3 V), the source/drain and UVLO comparators
enable the charge pump to provide gate−source voltage tothe external N−Channel MOSFET, which is fully
conductive. When the source voltage is below the UVLO
threshold (typ. 3.2 V), the charge pump and the N−Channel
MOSFET are disabled, and any load current flows throughthe body diode of the N−Channel MOSFET.

Schematic

Figure 8 shows the schematic of the test board. It is
designed in such a way that MOSFETs in SO−8FL/LFPAK4
and m8FL/LFPAK33 can be tested. Each MOSFET circuit
has a jumper to enable/disable the NCV68061 to make surethat only one controller is active at a time. A 3.3 V LDO
NCV4294 is used to supply the enable pin EN of thecontroller. The controller will control the N−Channel
MOSFET to act like an ideal diode and also to block reverse
current.

Figure 8. Schematic of NCV68061 Test Board

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5AND90146/D
Layoutseveral layers helps to reduce the losses and to have better
thermal performance of the board. Inner2 layer has traces forgate signals and for enable signal. Bottom layer is fully
dedicated for the GND plane.

The board is a 4−layer printed circuit board (PCB). The
input and output currents have been distributed across top,
inner1 and inner2 layers. Distributing the current acrossFigure 9. Top Layer

Figure 10. Inner1 Layer

Figure 11. Inner2 Layer

Figure 12. Bottom Layer

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AND90146/D
THERMAL MEASUREMENTS
Table 3. MOSFETS UNDER EVALUATION
Battery
Current

Part Number

Package

Maximum RDS,ON @ 10 V
VGS (mW)

Maximum Losses
PD (mW)

RqJA (5C/W)

TCASE (5C)

6A

NVTFS5C478NLWFTAG

m8FL

14.0

504.0

51.0

47.3

NVMFS5C468NLAFT1G

SO−8FL

10.3

370.8

43.0

40.1

8A

NVTFS5C466NLWFTAG

m8FL

7.3

467.2

48.0

47.4

NVMFS5C466NLWFT1G

SO−8FL

7.3

467.2

43.0

45.3

NVTYS005N04CLTWG

LFPAK8

4.8

480.0

47.7

52.8

NVMYS4D6N04CLTWG

LFPAK4

4.5

450.0

40.0

47.5

10 A

Table 3 shows the N−Channel MOSFETs used for thermal
evaluation. MOSFETs with various RDS, ON are chosen to
limit the power dissipation to be around 500 mW.
Measurements of the MOSFETs top case temperature are
made at 24°C ambient temperature to evaluate the thermal

performance of the MOSFETs with different output currents(6 A, 8 A and 10 A). MOSFETs in SO−8FL/LFPAK4 (5 × 6)
and m8FL/LFPAK8 (3 × 3) are used for evaluation. Twomeasurements are made for each load current, one with 5 × 6
and another with 3 × 3 package.

Figure 13. 6 A with m8FL

Figure 14. 6 A with SO−8FL

Part Number

NVTFS5C478NLWFTAGPart Number

NVMFS5C468NLAFT1GMax. RDS(ON) @ 10 V VGS

14.0 mW

Max. RDS(ON) @ 10 V VGS

10.3 mW

Max. Temperature

47.3°C

Max. Temperature

40.1°C

Figure 16. 8 A with SO−8FL

Figure 15. 8 A with m8FL
Part Number

NVTFS5C466NLWFTAGPart Number

NVMFS5C466NLWFT1G

Max. RDS(ON) @ 10 V VGS

7.3 mW

Max. RDS(ON) @ 10 V VGS

7.3 mW

Max. Temperature

47.4°C

Max. Temperature

45.3°C

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7AND90146/D

Figure 17. 10 A with LFPAK8

Figure 18. 10 A with LFPAK4

Part Number

NVTYS005N04CLTWG

Part Number

NVMYS4D6N04CLTWG

Max. RDS(ON) @ 10 V VGS

4.8 mW

Max. RDS(ON) @ 10 V VGS

4.5 mW

Max. Temperature

52.8°C

Max. Temperature

45.3°CWith the measured top case temperature from thermal
measurements and calculated power dissipation, thejunction temperature TJ can be calculated using equation 1.
T J + T CASE ) P D

R qJT

TJ
= Junction temperature of the MOSFETTCASE = Temperature of the package on top measured by
the thermal cameraPD= Power dissipation of the MOSFET(eq. 1)RqJT= Thermal resistance between top case andjunction of the MOSFET

Figure 19. Equivalent Thermal Resistance of the MOSFET

junction to the top of the MOSFET and one can assume thatthe temperature difference between TJ and TCASE is not
significant. For the sake of the application note, theassumption is that RqJT is 1°C/W to determine TJ.
NOTE: 1°C/W is a very conservative assumption for3 × 3 and 5 × 6 packages. Other packages will
have a different thermal resistance.

The value of RqJT is not fixed, it depends on thermalboundary conditions such as PCB layout, cooling system of
the MOSFET (like exposed pad) and other parameters,
therefore it is not provided in the datasheet. RqJT is a small
number with < 1°C/W, as most of the heat will flow fromjunction to the PCB via the exposed pad on the bottom sideof the package. Therefore, not much heat flows from thewww.onsemi.com
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AND90146/D
Estimation of the Junction Temperature TJ

Theoretical Calculation for TJ
Theoretical calculations based on specification of thedatasheet are used to determine TJ. Assuming losses of
500 mW, the equation 3 is used to determine TJ of the device.

In the following section, the measured TCASE and actual
power dissipation in the MOSFET are used to calculate TJ.
In the next step a theoretical calculation based on
specifications of the datasheets is done and the result iscompared to the calculations made using measured data to
see if both theoretical and practical calculations of TJ arematching.
All
calculations
considerMOSFET
NVTFS5C478NLWFTAG in m8FL (3 × 3) package.

PD +2
P D + ǒ6.0 AǓ

operated TA = 24.0°C

MOSFET RqJA = 51.0°C/W (value from the datasheet)
TJ + PD+ 500.0 mW

R qJA ) T A

51.0°CńW ) 24.0°C + 49.5°C(eq. 4)This gives 125.5°C headroom for TJ,MAX of 175.0°C for
NVTFS5C478NLWFTAG.
The difference between estimated and theoreticallycalculated TJ’s is minor at 1.7°C (49.5°C vs. 47.8°C). In
Table 4, as shown in the above calculations, theoreticallycalculated TJ and measured TCASE, RqJT and PD are used toestimate TJ for various loads and packages.

(eq. 2)Using Equation 1,
T J + 47.3°C ) (504.0 mW(eq. 3)• Power dissipation of the MOSFET PD = 500.0 mW• Thermal resistance between junction and ambient of theR DS, ON

14.0 mW + 504.0 mW

R qJA• Junction temperature of the MOSFET TJ• Ambient temperature at which the MOSFET will be

Estimation for TJ Using Measured TCASE
The below calculations are done to estimate TJ using
values obtained from measurements.
• Load current ILOAD = ID = 6.0 A• Input voltage Vin = 12.0 V• Temperature of top case TCASE = 47.3°C (obtained
from the thermal measurement)• Max. on−resistance RDS, ON @ 10.0 V VGS = 14.0 mW• RqJT = 1.0°C/W (assumption for 3 × 3 and 5 × 6
packages)
P D + I 2D

TJ * TA

1.0°CńW) + 47.8°C

Table 4. CALCULATED TJ OF THE PROPOSED MOSFETS VS. LOAD CURRENT
TJ (5C)

Estimated TJ
Headroomfrom Maximum
175 5C
Based onMeasurement(5C)

Measured
TCASE (5C)

Estimated @245C Ambient
Based onMeasurement

Calculated
Theoretical
Value

DTJ
Between
Theoreticaland Scaled
Up Value
−1.7

127.2

Battery
Current

Part Number

Package

Maximum
RDS, ON @10 V VGS(mW)

6A

NVTFS5C478NLWFTAG

m8FL

14.0

504.0

51.0

47.3

47.8

49.5

NVMFS5C468NLAFT1G

SO−8FL

10.3

370.8

43.0

40.1

40.4

45.5

−5.1

134.6

NVTFS5C466NLWFTAG

m8FL

7.3

467.2

48.0

47.4

47.8

48.0

+0.2

127.2

NVMFS5C466NLWFT1G

SO−8FL

7.3

467.2

43.0

45.3

45.7

45.5

+0.2

129.3

NVTYS005N04CLTWG

LFPAK8

4.8

480.0

47.7

52.8

53.2

47.8

+5.4

121.8

NVMYS4D6N04CLTWG

LFPAK4

4.5

450.0

40.0

47.5

47.9

44.0

+3.9

127.1

8A

10 A

Maximum
Losses PD
(mW)

RqJA
(5C/W)• At 6 A load current there is approximately 5.8 % higher• Measurement of RqJA in the datasheet using 2 oz. copper

head room for TJ with 5 × 6 than 3 × 3 package.

pad with larger area board seems unrealistic from realapplication point of view but looking at the minor
difference in TJ as estimated above shows that RqJA
matched quite well with 4−layer test board optimized forthermal dissipation.
• The results show that due to the larger package (5 × 6) theheat is getting dissipated efficiently and being distributed
across the whole device hence there is better head room.
Larger packaged devices are suitable for higher load
current application from thermal point of view as well as
for applications with higher ambient temperature.

• At 8 A load, approximately 1.6 % higher head room with

5 × 6 than 3 × 3. Both the devices are having the same die
in different packages, therefore there is not muchdifference between TJ’s is seen.
• At 10 A, approximately 4.3 % higher head room with
5 x 6 than with 3 × 3.
• Likewise, the difference in theoretical and estimated TJ is
not significant except around 5.4°C difference for one of
the 10 A MOSFETs. This shows that the RqJA in thedatasheet is reliable for this specific test setup.

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9AND90146/D
The power dissipation at 175°C junction temperature and6 A load current is as follows:

Estimation of the Maximum Ambient Temperature TA
The previous calculations show that RqJA of the datasheet
matches quite well with the NCV68061 test board.
Therefore, the maximum ambient temperature above which
the MOSFET cannot not be operated can be calculated.
Figure 20 shows the variation of RDS, ON in relation to TJ
for NVTFS5C478NLWFTAG. At 175°C junction
temperature, the maximum RDS, ON is around 1.85 times
higher compared to 25°C junction temperature. This results
in a maximum RDS, ON of 1.85 × 14 mW = ~25.9 mW..

P D + ǒ6.0 AǓ

2

25.9 mW + 932.4 mW

With RqJA = 51.0°C/W, the temperature difference
between junction and ambient can be calculated:
Temperature difference DT + 51.0°CńW

932.4 mW + 47.5°C

Maximum T A + T J * DT
Maximum T A + 175.0°C * 47.5°C + 127.5°C(eq. 5)

From the above example, the MOSFET can be operated
at maximum ambient temperature of 127.5°C. If the ambient
temperature goes above the calculated value, then it would
mean that the TJ has reached over 175°C.
The silicon of the MOSFET itself can be operated at above
175°C, but due to the limitation of package mold compoundand to ensure reliability over long−term operation, the
MOSFET datasheet states that maximum TJ to be 175°C.
Temperature above maximum TJ would lead to
unguaranteed behavior of the device, and it also means thatdevice is operating out of specification.
Table 5 shows the estimated maximum ambient
temperature for various MOSFETS, considering different
load currents and a junction temperature of 175°C.

Figure 20. NVTFS5C478NLWFTAG On−Resistance
Variation with Temperature
Table 5. ESTIMATED MAXIMUM TAMB

Package

Maximum RDS, ON @ 10 V
VGS @ 1755C TJ (mW)Maximum Losses
PD (mW)

RqJA (5C/W)

Estimated
Maximum
TAMB (5C)

NVTFS5C478NLWFTAG

m8FL

25.9

932.4

51.0

127.5

NVMFS5C468NLAFT1G

SO−8FL

19.6

705.6

43.0

144.6

NVTFS5C466NLWFTAG

m8FL

14.4

921.6

48.0

130.7

NVMFS5C466NLWFT1G

SO−8FL

13.2

844.8

43.0

138.6

NVTYS005N04CLTWG

LFPAK8

8.8

880.0

47.7

133.0

NVMYS4D6N04CLTWG

LFPAK4

8.3

830.0

40.0

141.8

Battery
Current

Part Number

6A

8A

10 A

CONCLUSION
Reverse polarity protection circuits are one of the corebuilding blocks of any ECU in a vehicle. In this applicationnote several reverse polarity protection techniques are
discussed including diodes, P−Channel MOSFET and
N−Channel MOFET. A comparison between all thetechniques is presented highlighting advantages anddisadvantages of each technique. Moreover, a MOSFET
selection guide is given to support the MOSFET selection
process, including a list of recommended devices. Thermal
measurements with load currents from 6 A to 10 A show that5 × 6 packages perform well from thermal point of view, due
to the larger package and bigger die, RDS,ON will be reduced
and power losses are lesser than 3 × 3 package. Additionally,a larger die helps to dissipate the heat better than with asmaller die. With that said, table 3 shows that the differencein margin for maximum TJ between 5 × 6 and 3 × 3 is not
significant. Depending upon the application needs andcooling system used either 5 × 6 or 3 × 3 packaged
MOSFETs can be used.
Without significant difference between the theoreticallycalculated and practically estimated junction temperature
TJ, RqJA given in the datasheet is a realistic value to performthermal analysis in the real applications. RqJA helps tocalculate the maximum ambient temperature at which the
MOSFET can be operated using the calculations shown inthe document earlier.

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