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Addressing Thermal
Challenges in High‐Density
Power Applications
Demand for more features and higher performance fromever-smaller form factors presents significant challenges forengineers developing applications such as DC-DC
conversion, computing, industrial motor drives, andtelecommunications. In many cases, for example, enhancing
capabilities and functionality can lead to the need for larger
components and, consequently, demand for more cooling.
Forced-air cooling can be cumbersome, unreliable andinefficient. Passive cooling using heatsinks adds bulk andcost to the design and, ultimately, the end product. Thermal
issues can, effectively, stop innovation in its tracks.
Experienced power designers know that the best way todeal with heat is to not generate it in the first place, meaningthat each design generation has to be more efficient than theprevious. Correct selection of the topology and, more
importantly, the power switching components, is critical toa successful design. However, all power circuits generatesome heat, no matter how efficient they are. As designs get
smaller, the opportunities for passive convection cooling are
reduced and designers have to find intelligent andinnovative ways to thermally connect semiconductor
junctions to the ambient environment where the heat candissipate.
Not only does the package affect thermal performance, theleads themselves can also have an impact. For instance,
packages with longer leads introduce parasitic elements into
the circuit that can affect both speed of operation andefficiency.

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TECHNICAL NOTE

Dual Cool package construction is an evolutionary
extension of the popular PQFN form factor, incorporating
new features to meet future performance expectations. By
retaining the very popular Power33 and Power56 leadgeometries and pinouts, the package allows designers toimprove heatsink performance in existing PCB pad designs.
Customers currently using a heatsink on the surface ofa PowerQFN package will find this a very useful feature,
allowing an easy transition.

DUAL COOL) Advances PQFN Packaging

Figure 1. Solid Model Illustrating Dual Cool
Package Construction

Pursuing a strategy of power density leadership,
ON Semiconductor has developed a power-specificpackaging technology to meet the escalating demand for
improved thermal management in modern electronic
designs. Based on industry-standard Power Quad Flat
No-Lead (PQFN) packaging, ‘Dual Cool’ technology
creates a direct heat path from the drain and source sides ofthe vertical MOSFET die structure through the addition ofa heat slug to the top of the package. This structure allows
for supplemental cooling on top of the package witha heatsink system while also providing a direct thermal
conduction path into the printed circuit board (PCB).

© Semiconductor Components Industries, LLC, 2017

October, 2017 − Rev. 1

Copper clips, similar to leadframes, replace wire bonding
inside the Dual Cool concept. Not only does this approach
improve thermal conductivity but it also increases current
handling capability within the compact PQFN form factor,
thereby enabling higher power densities with excellent
thermal properties. In fact, the standard PQFN package
using the clip technology offers a 13.9% improvement over
the wire bond-based PQFN package. Dual Cool technology
further improves the performance differential to 57.5% in
a 5 × 6 mm package.

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Figure 2. The Cu Clip Offers Significant Improvement in Performance

top of the package for use with a heatsink, a heat slug issoldered to the source clip. This is exposed on the top of thepackage to provide the heatsink interface.
Solder attachment of the silicon to the lead frames, with
optimized copper clips additionally reduces electrical andthermal parasitics. The qJC (thermal resistance from thejunction to the case) has two important values with thispackage type: the junction to case thermal resistance to thedrain tab as well as the top heat slug. The datasheet offers
these values for each specific product type. These numbers
are a measure of the two efficient heat paths out of thecomponent, giving the designer options for managing theheat loads created by high power density designs.

Dual Cool uses 4 mils thin silicon as the core package
design constraint. This represents half the thickness of thetypical MOSFET that traditionally used 8 mils thick silicon
dice. By reducing the die thickness to 4 mils, thermal andelectrical performance are improved. This is thanks to thelower parasitic resistance created by the bulk resistancefrom the doped silicon area through which electrons flow toget from the trench structure at the top of the wafer to thedrain lead frame connection at the bottom.

DUAL COOL Enhances POWERTRENCH) MOSFETs

ON Semiconductor’s PowerTrench MOSFETs offer
excellent electrical properties including very low levels ofRDS(on). The fully RoHS-compliant products include an
integrated monolithic SyncFETt Schottky body diodemaking this technology a leading choice for power
designers. PowerTrench SyncFETs became a natural choice
to benefit from the new Dual Cool packaging concept.
The combination of Dual Cool and PowerTrench occupies
the same land pattern as 5 × 6 mm and 3.3 × 3.3 mm
PQFN−JEDEC standard parts, yet allows for > 60% better
thermal performance.

Figure 3. Cross Section of Dual Cooland Heatsink Assembly

The top and bottom surfaces of the die are plated withsolderable metal to permit solder attachment of the drain
lead frame on the bottom, and the source and gate clips on
the top. To improve the heat transfer path from the die to theFigure 4. Dual Cool has > 60% Better Thermal Performance than PQFN

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2

TND6224/DThe Dual Cool PowerTrench MOSFETs with top-side
cooling have a far better thermal coupling to the top of thedevice. In many cases, they can be used without anadditional heatsink thereby reducing size, cost and weight.
With enhanced dual-path thermal performance andimproved parasitics over its wire-bonded predecessors, theuse of a heatsink provides even more impressive results.
Laboratory testing proves that when a heatsink is usedwith Dual Cool package technology, synchronous buckconverters deliver higher output current and increased
power density. With ON Semiconductor’s trench silicon
technology, Dual Cool packaging proves to be a clear leader
in both power density and thermal performance.

Figure 5. PQFN Based Dual Cool Packaging

The Dual Cool portfolio offers in excess of 20 productswith BVDSS covering the range 25 V to 150 V and a numberof choices for RDS(on) and package size.

Figure 6. The Broad PowerTrench/Dual Cool Portfolio Offers Designers Choices

Dual Cool solutions are lead-free, RoHS-compliant, andavailable in 3.3 × 3.3 mm, 5 × 6 mm, and8 × 8 mm PQFNpackages.

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3TND6224/DUse with Heatsinks

Depending on the size of any heatsink used on the top-sideof the package and any air flow that may be present, thethermal resistance from the semiconductor to ambient canbe further improved.

Figure 7. Comparison of Various Cooling Modes

filler sheets. It was found for the wire bonded units that
performance improved 10% over gap pad, for the clip
bonded 12%, and for Dual Cool performance improved 21%
over the Gap Pad.
This represents a theoretical improvement in allowabledissipated power from 5.8 W with the gap pad to 7.0 W withthe grease. Grease is the best performance-wise, but is moredifficult to dispense, rework and does not have the electricalisolation properties of the pad. The application will dictate
if these trade-offs are worth making.
In applications where tightening a screw, a push pin, ora solder anchor is used to secure the heatsink, a compression
load is placed on the component. The PQFN 8 × 8 Dual Coolpackage has been tested and simulated to withstand highcompression loads. Results show that the package canwithstand up to 1500 N of load without causing any
electrical or mechanical failure.

In Figure 7 above, the large heatsink is aluminummeasuring 45.2 × 41.4 × 12.7 mm, and the smaller one is20.9 × 10.4 × 12.7 mm.
Various types of heatsinks are available and the design,form factor, and mechanism for thermal dissipation will
depend on the application, available space and heat to bedissipated. Methods of attachment also vary and include
solder anchoring, push pin, thermal tape, screwing, orglue/adhesive.
Thermal interface materials can be used to improve thecontact between the Dual Cool package and the heatsink andeliminate the possibility of air gaps in the interface that will
limit heat dissipation.
Thermal interface materials (TIM) are available in manyforms and include the following:• Thermal Grease• Insulating Pad• Phase-change Materials• Thermal Tape
• Gap Filler Sheet or Gel• Thermally Conductive Glue or Adhesives

PCB and Manufacturing Considerations

PQFN packages are widely used for low-voltage
applications. Due to the small configuration and low profile,these packages provide a good space-saving alternative tothe typical leaded options. The Dual Cool package offersa size advantage over the industrial standard D2PAK SMD
package.

Testing by ON Semiconductor has shown that thermal
grease provides an across-the-board improvement over gap

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In power applications where a large amount of heat is
generated during operation, the Cu land pattern provides
a larger area for heat to be dissipated into the PCB itself.
On the thermal characterization of PQFN 8 × 8 Dual Coolpackages, there is significant improvement in the thermal
resistance from junction to ambient if the Cu registration onthe printed circuit board is increased from a minimum padto a larger (say 1 in2) Cu pad connected to thesolder-mask-defined land pad.
Therefore, it is recommended that the drain pad on theboard be routed and connected to a large Cu area on theboard for heat dissipation.
Summary

Clearly the combination of PowerTrench technology with
the Dual Cool packaging concept addresses the two
fundamental challenges of modern power design; operating
as efficiently as possible to minimize heat generation andthen transmitting what heat is generated as efficiently aspossible from the semiconductor junction to the ambientenvironment.
In some applications, the package can be used without
additional cooling and, where additional cooling is required,a heatsink can be mounted easily to provide substantial
thermal performance gains.

Figure 8. Recommended Land Pattern for 8 y 8
PQFN (Dimensions in mm)

The source and gate pads are larger than the package leadto allow toe filleting of the solder. The pads are also wider
than the leads, providing allowance for variation in board
fabrication and component placement during assembly.
Combined, these tolerances can stack up to 0.10 mm.
The land pad for the exposed thermal pads is identical to
the size of the exposed pad. This large connection between
the board and the component allows the strong surface
tension of the molten solder to pull the component so that it
perfectly aligns with the land pad. Correct PCB layout will
ensure that the Dual Cool packages are consistently aligned
during production.

DUAL COOL and POWERTRENCH are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries
in the United States and/or other countries, SyncFET is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its
subsidiaries in the United States and/or other countries.
ON Semiconductor andare trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage
may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer
is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless ofany support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can anddo vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorizedfor use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices
intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify andhold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor wasnegligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyrightlaws and is not for resale in any manner.

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