TND6396/D
Rev. 2, March − 2024

Silicon Carbide (SiC) − From
Challenging Material to Robust
Reliability© Semiconductor Components Industries, LLC, 2022

March, 2024 − Rev. 2

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Publication Order Number:
TND6396/D

Silicon Carbide (SiC) − From Challenging Material to
Robust Reliability
Prepared by: Catherine De Keukeleire
onsemi Oudenaarde, Belgium

Abstract
Silicon Carbide (SiC) is one of the most promising semiconductor materials for manufacturinghigh−power electronic devices. Thanks to its excellent physical properties (high saturationelectron drift velocity, high thermal conductivity, high breakdown electric field), SiC−based
systems can achieve very low losses and faster−switching speed with smaller geometries than
Silicon (Si) MOSFET transistors. While onsemi made great use of knowledge andmethodologies acquired for many years on Si technologies, the specific challenges introducedby SiC materials have been and still are extensively assessed to tailor an appropriatequalification methodology to demonstrate robust reliability.
This white paper will introduce the reader to the onsemi Quality and Reliability methodology
deployed from first design to mass production. This comprehensive approach is founded on theinteraction between different fields, such as a rigorous design methodology, strict production
monitoring, manufacturing control, adequate screening, and robust qualification plans.
This methodology, applied to the Automotive market for many decades, has shown its
efficiency on Silicon products and has been tailored to address the specific needs of Silicon
Carbide products. You will be guided through this evolution to SiC and, more specifically, its
successful deployment addressing the integrity of the Gate Oxide of SiC MOSFET transistors.
Finally, the paper will briefly present recent publications on cryogenic bias temperature
instability, body diode degradation, and dynamic stress requirements.

Introduction
The quality and reliability of a given product are governed by all activities, from ideation todelivery to the end users’ product line. The onsemi Quality Statement/Policy fully embeds thisapproach (Figure 1).
It remains subject to several potential process−related reliability hazards even within thehighest possible degree of reliability designed into the product.
To eliminate these, one must understand the limiting failure modes and mechanisms and trace
them back through failure analysis and feedback loops to process weaknesses and implement
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2permanent corrective actions. This is achieved through elaborate wafer & product qualification,
rigorous design methodology, production monitoring, manufacturing control & adequate
screening. The use of these programs is described in the general reliability specifications ofonsemi and illustrated by the onsemi Quality − Road to Zero Defects (Figure 2).

Figure 1. onsemi Quality Statement/Policy
Consequently, onsemi has implemented three different qualification programs: the wafer fab
qualification, the product qualification, and the assembly route qualification. Each of thesequalification programs focuses explicitly on other areas of the product manufacturing cycle andaims to ensure maximum reliability of the targeted area.

Figure 2. onsemi Quality − Road to Zero Defects
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The wafer fab route qualification (also called intrinsic qualification) primarily focuses on thewafer fab processing—designed to ensure a constant inherently high−reliability level for all
wafers processed according to the qualified flow. At that stage, physics−based degradation
models are extracted.
The product and assembly route qualifications (also called extrinsic qualifications) validate
the reliability of the packaged dies based on the Mission Profile of the final products, the ultimate
goal being to assure high−reliability performance of the end product.

Silicon Carbide Challenges
Silicon Carbide (SiC) material combines excellent physical properties and attractive design
features, resulting in a very appealing solution for manufacturing high−power electronic
devices.
Multiple crucial elements must be combined when safely releasing a product to the market,
as illustrated in Figure 3.

Figure 3. Definition of Robust Intrinsic and Extrinsic Reliability
The first challenge is linked to the readiness of international standards. While these guidelines
are well established for Silicon−based technologies, multiple sub−teams within JEDEC, AEC,
and AQG committees are actively working to develop the proper foundation for future SiC
standards. This will ensure that suppliers are guided through a well−documented global
methodology and will avoid long debate on the validity of collected data.
The next challenge resides in the physics−based understanding of the failure mechanisms
to properly quantify the product robustness versus the required Mission Profile of the customer.
Electric Vehicles typically have extended mission profiles when compared to combustion
vehicles. This, combined with the enhanced performance of SiC technology compared towww.onsemi.com
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conventional Si technology or IGBTs, requires the reliability stressing to match the final
customer Application more closely.
At this stage, the involvement of a cross−functional team (Manufacturing front−end, Research& Development, Manufacturing back−end, Applications Testing, and Failure Analysis
engineering) is key to success. A clear relation between Intrinsic Reliability (lifetime models) andApplications is established.
Close collaboration with Universities and Research Centers is crucial to go deeper into thetheoretical aspects or to offer dedicated techniques & complementary skill sets not always
available in the semiconductor industry. Figure 4 illustrates the characterization and Reliability
assessment of the SiC/SiO2 interface.

Figure 4. Collaboration with Universities and Research Centers − SiC/SiO2 Interface
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The following SiC−specific challenges typically need to be addressed:• Substrate and Epitaxy defectivity level• Gate Oxide: intrinsic lifetime modeling (SiC/SiO2 interface characterization) and extrinsic
population (screening)• Body Diode degradation• Reliability during high−voltage blocking (HTRB)• Application−related performance (Avalanche robustness, Edge termination, Short Circuit,
Ruggedness against Cosmic Rays, Design for High dv/dt ruggedness, Surge currents).

The onsemi Methodology
For each degradation mechanism, the onsemi approach is rigorous and cross−functional.
Steps are Control – Improve – Test & Screen – Characterize – Qualify & extract models.
When applied to Gate Oxide Integrity (GOI), these steps articulate as follows:
Control
Methodology and tools are in place for manufacturing SiC technologies (Control Plan,
Statistical Process Control, Process FMEA). Data is being collected and used as a foundation
for potential process improvements.
Improve
Since substrate or epitaxial defects, metallic contaminants, and particles can heavily impact
the gate oxide quality, continuous improvements and their controlled introduction to production
are crucial to reduce defects’ occurrence further.
Test & Screen
onsemi has developed a full suite of visual and electrical screening tools to eliminate
defective dies.
The wafer fab process flow starts with a substrate scan, identifying all defects with coordinatestracking and auto−classification. Multiple inspections identify additional potential process
defects at critical process steps. All flagged defects found in the inspections above are excluded
from the population (Figure 5).

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Figure 5. Scanning and Inspections During the Front−End Process
Electrical screening is implemented at multiple levels:• Wafer level performance and acceptance (parametric testing and gate oxide integrity
acceptance criteria)• Wafer level Burn−in• Wafer level die Sort
• Dynamic Part Average Testing is in place to remove electrical outliers.
Finally, all wafers are screened with 100% automated outgoing inspection, including for visual
defects.
Characterize
onsemi is using the Charge to Failure (QBD) as a simple method to compare gate oxide quality
independent of the gate oxide thickness. This technique is more refined than GOI/Vramp andwill detect finer details in the intrinsic distribution.
As illustrated in Figure 6, planar SiC and Si gate oxides have comparable intrinsic capabilities
in breakdown and lifetime. A side−by−side comparison of intrinsic QBD performance(independent of gate oxide thickness) shows onsemi planar SiC being 50 times better
intrinsically than Si for the same nominal thickness.

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Figure 6. QBD Measured for SiC NMOS Capacitors, 1200 V 40 mW SiC MOSFETs,
and a Si MOSFET Product when forcing 5 mA/cm2 with a Forward Biased Gate at
Room Temperature
In production, the gate oxide quality of each lot is evaluated by sampling charge to failure(QBD) for SiC MOSFET product dies and compared with large area (2.7 mm x 2.7 mm) NMOS
capacitors.
An acceptance criterion is in place to accept or reject at the wafer level.
Qualify & Extract Models
Determining the true current conduction mechanism(s) of the gate oxide is crucial whendefining the stressing conditions [1]. Thermally Assisted Tunneling competes with Fowler
Nordheim as a function of stressing electric fields and stressing temperature (Figure 7).
Therefore, understanding the conduction mechanisms prevents stress in another conduction
mode than the one representative of actual use conditions in the field.

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8Figure 7. Competing Current Conduction Mechanisms as Function of
Temperature and Electric Fields
The intrinsic performance of the gate oxide is assessed via Time Dependent Dielectric
Breakdown (TDDB) stressing. Gate bias and temperature are combined to stress the SiC
MOSFETs, and times−to−failures are recorded. Weibull statistical distributions are then used
to extract the lifetimes.
A very conventional approach has been used so far: Arrhenius temperature acceleration and
E model for the gate voltage. Additional studies are ongoing to refine the model; the E model
is considered too conservative. Stresses at lower oxide fields and long duration (with t63% of
several months to more than a year) are being conducted, and they should experimentallyconfirm which model best suits the data.
Figure 8 shows TDDB data of SiC production MOSFETs stressed at a temperature of 175°C
and at oxide fields where electron trapping occurs (hence below 9 MV/cm, see also Figure 7),
for which the same failure mode occurs as expected under real−life conditions. For the lowest
stress voltage, times−to−fail over half a year are recorded. Experiments at even lower fields,with an estimated t63% of 1 to 2 years, are being conducted at a university partner. A 20−year
lifetime is reached for Vgs = 21 V, well above the specified operating voltage, using theconservative E−model, at 5 ppm.
Figure 9 shows the IG(t) curves (gate current as a function of stress time) of the individual
MOSFET transistors during TDDB stress. The gate current IG remains constant until reachinga specific envelope curve, after which IG drops due to the trapped electrons. This envelope
curve reflects the trapped charge that the dielectric can sustain before the transistor parameters
are affected. This charge is about one decade lower than the charge−to−breakdown (QBD) of
the dielectric (i.e., the charge for which the dielectric breaks) and is at par with the QBD obtainedon Si/SiO2 transistors.

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9Figure 8. TDDB Data of SiC Production MOSFETs (Stress at 1755C andBelow 9 MV/cm So Under Electron Trapping, See Also Figure 7)

Figure 9. IG(t) Curves of the TDDB Data Depicted in Figure 8(SiC Production MOSFETs Stressed at T=1755C)

Published Material
The purpose of this section is to describe recent studies performed at onsemi briefly. The
related publications are listed in the References section and will provide all details a reader
would love to obtain to get deeper into these technical topics.

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10Bias Temperature Instability (BTI)
BTI is a well−known degradation mode in the Si world, with threshold voltage drift of the
MOSFET due to generation or charging of traps at or near the semiconductor/oxide interface,ultimately leading to a detrimental increase of the on resistance. SiC MOSFETs are also
affected, and the fact that one is dealing with a wide bandgap material makes the study more
complex. The behavior of the material has to be well understood not only in DC but also in
switching mode.
The characterization of the SiC/SiO2 interface and the assessment of its intrinsic reliability has
been a focal point at onsemi for many years, with the creation of a Research Network to study
and improve interface states and mobility, using selected research partners and experimental
techniques (see Figure 4).
Static BTI evaluation for ON and OFF states occurs at package level via High Temperature(positive and negative) Gate Bias stressing, including a drift analysis of electrical parameters
after stress. Dynamic BTI requires a more comprehensive approach. onsemi allocatedresources to deeply investigate Ultra−Fast Bias Temperature Instability (UF−BTI), with themeasurement and modeling of threshold voltage (Vth) shifts when applying positive (PBTI) andnegative (NBTI) gate stress (or both) as illustrated in Figure 10.

Figure 10. Schematic Representation of the Stress / Measure / Emission
Sequence Used to Investigate Ultra Fast BTI on SiC MOSFETs
During PBTI, the “apparent” Vth will shift to higher voltages (due to capture of electrons), whileduring NBTI, the “apparent” Vth will shift to lower voltages (due to emission of electrons or
capture of holes). PBTI has a permanent and recoverable component, and NBTI seems only
to have a recoverable part.
A conventional IdVg characterization is not able to capture the fast components. But during
a typical switching application (100 kHz, so ~ 5 to 10 ms), the fast BTI component will dominate
and can become a potential application problem.
onsemi collected data down to the ms range and over an extensive range of temperatures,
including cryogenic.
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Figure 11. Vth Shift as a Function of Time and Temperature during PBTIat Vg = +10 V and Subsequent Recovery

Figure 12. Vth Shift as a Function of Time and Temperature during NBTI
at Vg = −10 V and Subsequent Recovery
The followings steps were:• The extraction of the Capture & Emission Time (CET) maps (Vth shifts result from trappedcharges, distributed in energy and space). Figure 11 displays Vth shifts during stress and in
the subsequent recovery as a 10 V PBTI stress, and in Figure 12 as a −10 V NBTI stress• The AC and DC modeling of the Vth drifts (fast BTI component for the applications and slow
BTI component for the long−term intrinsic reliability)• Extract a physical model (defect type, energy, depth) as shown in Figure 13• Predict lifetime under real−life application requirements.

Figure 13. Fitting of the Absolute Vth Shifts after NBTI and PBTI (with theComphy Model) allows Extracting a Trap Distributionwww.onsemi.com
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The cryogenic UF−BTI study has been presented at ISPSD2022 [4].
Body Diode Degradation
Bipolar degradation by Body Diode stress in SiC MOSFET can result in an on−state resistanceincrease triggered by the current flowing through the body diode when it is forward biased. Thisdegradation is sometimes also reported as a drift in forward voltage or increased off−state
leakage. The test procedure is described in Figure 14, while Figure 15 shows the forward
voltage drop VF and current ID during pulsed measurements.

Figure 14. Test Procedure for Bipolar Degradation

Figure 15. Transient Measured Body Diode Forward Voltage Drop VF and Current
ID during Pulsed Current Measurements with 250, 300 & 350 A, and VGS = −5 V

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onsemi has extensively assessed this degradation mechanism—most recently publishing a
study at ECSCRM2021 [2], performing individual mapping of BPDs in SiC MOSFET dies toestablish a correlation between RDSon drift after body diode stress and the number of BPDs in
the devices. RDSon and VF drifts were clearly increasing with the number of BPDs in a device.
However, extremely high current densities (J > 1600 A/cm2) had to be used to observe asignificant degradation in MOSFETs with no BPD (Figure 16).

Figure 16. Drift in RDSon and VF versus BPD Count on 1700 V 25 mW SiC
MOSFETs and versus Current. Body Diode Stress of 1 million 50 ms Long Pulses
onsemi implements the following elements for all SiC technology nodes:• Visual screening is in place, with each production wafer thoroughly scanned for Basal Plane
Dislocations (BPDs)• The epitaxial buffer layer is highly doped, and the development of stacking faults from BPD
is limited

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14• Finally, design rules for maximum current densities have been defined to remain within a safe
operating area for each MOSFET.
Thanks to the combination of these three elements, onsemi SiC MOSFET technologies up
to 1200 V can be considered as not impacted by Body Diode degradation.
Dynamic Stressing
Degradation under dynamic conditions is one of the concerns related to wide bandgap
material. Dynamic stressing studies have been performed at onsemi on benches internallydeveloped (limited sample size). We present an example of Room Temperature Dynamic Gate
Stress below.
Regarding dynamic stressing events on larger sample sizes (such as three lots of 80 unitseach), test solutions are presently in development (both internally and with an equipment
supplier).
Room Temperature Dynamic Gate Stress: a transient and overshoot−free VGS stress was
performed at T = 25°C with VDS = 0 V using a gate driver switching between −8 V and 20 V witha 50% duty cycle [3].

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Figure 17. Shifts of Vth and Normalized RDSon for onsemi’s Commercially
Available 1200 V 80 mW SiC MOSFET and 1200 V SiC MOSFET Products fromthree other Manufacturers
The stress measurements were interrupted after different time intervals to run a test program
consisting of Vth and RDSon. The shifts of Vth and normalized RDSon shifts are shown in Figure 17
for onsemi’s commercially available 1200 V 80 mW SiC MOSFET together with 1200 V SiC
MOSFET products from three other manufacturers (VGS = −8 V being outside the datasheet
rating for two of them).

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Conclusion
As illustrated in this white paper, onsemi has developed a comprehensive andcross−functional methodology to assess and safely release SiC products to the market.
The combination of a rigorous design methodology, strict production monitoring,
manufacturing control, adequate screening, and robust qualification plans is the foundation ofrobust and reliable SiC products.
The paper briefly addressed some specific SiC challenges as an introduction to how they havebeen characterized and modeled at onsemi.
Our published material provides more details about the physics−based studies performed atonsemi (see References for the most recent ones).

References[1] A Charge−to−Breakdown (QBD) Approach to SiC Gate Oxide Lifetime Extraction andModeling – P. Moens 1 , J. Franchi 1 , J. Lettens 1 , L. De Schepper 1 , M. Domeij 1 ,F. Allerstam1 – 1onsemi − ISPSD 2020
[2] Pulsed forward bias body diode stress of 1700 V SiC MOSFETs with individual mappingof basal plane dislocations − S. Kochoska1, M. Domeij1, S. Sunkari1, J. Justice1, H. Das1,
H. Lee1, X.Q. Hu1, T. Neyer1 − 1onsemi − ECSCRM 2021
[3] Gate oxide reliability and Vth stability of planar SiC MOS technology − M. Domeij1,
J.Franchi1, S. Maslougkas1, P. Moens1, J. Lettens1, J. Choi1, F. Allerstam1 −1onsemi − ECSCRM 2021
[4] Cryogenic Ultra−Fast Bias Temperature Instability Trap Profiling of SiC MOSFETs –F. Geenen 1 , F. Masin 2 , A. Stockman 1 , C. De Santi 2 , J. Lettens 1 , D. Waldhoer 3 ,M. Meneghini2, T. Grasser3, P. Moens1 − 1onsemi, Belgium; 2Università degli Studi di
Padova, Italy; 3Technischen Universität Wien, Austria − ISPSD 2022

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