APPLICATION NOTE
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On Board Charger (OBC)
Three-phase PFC Converter

AND9957/D
Summary

With the coming electrification of the automotive market, the needof battery chargers is more and more demanded. With the simple
equation more power, shorter the recharge time is, a 3−phase supply ishere considered which can provide up to ‘3x’ the power ofa single−phase supply.
The 3−phase PFC board here proposed is an example of the firststage of an On Board Charger system based on silicon carbide
MOSFET which will lead to a higher system efficiency and a reduced
BOM content.
The board is developed with the primarily goal of providing easy
access to the different devices for easing the testing phase and formeasuring; a form factor optimization has never been a target for the
EVB.
Output Voltage

The output voltage provided by the 3−phase PFC is here fixed to700 V (Accuracy 5%) and thanks to the SiC technology, the thermal
capability can be extended to higher ranges. The max deliverable
power is 11 kW considering an input voltage of 230 Vac at 50 Hz.
System• High fs Range (60−140 kHz)• High Efficiency (98.3% @ fs 100 kHz)• Wide Input Range (167 to 265 VPH rms)
• Bi−Directional• 3 Phase Full Bridge Rectifier

Figure 1. Board Photo
VDC

SAH

SBH

SCH

SAL

SBL

SCL

VOLTAGE SOURCE INVERTER

Figure 2. Topology − High Level© Semiconductor Components Industries, LLC, 2019

August, 2021 − Rev. 3

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Publication Order Number:
AND9957/D

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DC B US

3.3 V
24 V

3.3 V

MC U AN
OpAm psEMI
FilterPower
Grid

MC UAN
OpAm psCurrent
SensorEarth
24 V
MC UDIGIT AL

3.3 V
VOLTAGE SOURCE INVERTERMC U AN

15 V

OpAm ps

Isolated Gate
Isolated
Gate
DriverIsolated
Gate
DriverIsolated
Gate
DriverIsolated
Gate
DriverIsolated
PWM, EN, FAUL T
Driver Gate(from & to MCU)

3.3 V
DC BUS

DCDC

24

DCDC

15

Gate Dr iverGate Dr iverFault Mngm
(Logic)Dr iving HS

3.3 V

3.3 V

5V

Relay, FAN

DCDC
OpAmp

DCDC

5

DCDC
Analog Oﬀ

1.65

Microcontroller/ DSP

CAN Interface
To BMS

3.3

Dig, OpAmp

Figure 3. 3−Phase PFC Block Diagram

APPLICATION/CONTROL OVERVIEW
Overall concept can be seen in Figure 3. Since testability
was set as the highest priority during concept definition, theboard presented does not aim for highest power densities
and/or compactness.
The board behavior is simple, when a 3−phase voltage at
50 Hz is provided to the input connector; the output bus
capacitor voltage will rise because of nature of the PFC
topology. A bridge−less PFC with MOSFET guarantees
a current path from input to output because of the parasitic
freewheeling diode present on each MOSFET. When the
MOSFET are all off, the board simplifies in a 3−phase diodebridge. The rectified input AC voltage will set to a definedlevel depending on the supply voltage amplitude and on theforward voltage of the MOSFET body diodes, however it isexpected that at least 167 Vrms are given at the input. For
this reason, a resistor on two different lines serves as inrush
current limiter. Once the bus voltage reaches 400 V, the2−switch flyback converter starts to operate. It provides
24 V from which a series of DC/DC regulators generate theother needed voltage levels for powering up the digital andanalog circuitry.

When the micro awakes, besides verifying the offset
voltages for the ADC channels, it starts also monitoring thebus voltage and sensing the input voltages from which
determines the frequency and the angle of the phasevoltages. Such angle will be the reference angle of thesystem to achieve the power factor correction.
When the DC bus voltage becomes flat, the MCU issues
a command to the relay to bypass the resistor and allow
a further boost in the output bus voltage. However, thevoltage increment is going to be something lower therectified input voltage amplitude, √6∙VPH, RMS.
MCU will wait until the bus voltage becomes flat again inorder to start controlling the bus voltage to the targeted valueof 700 V. Target value does not change in a single step but
a smooth ramp generator will bring the bus value according
a parametrized slope to the final 700 V.
The PFC implements only one hardware protection,
against overcurrent events leveraging the DESAT
functionality of the NCV51705 gate driver. A thresholdvalue of 50 A is set on the board given the characteristic of
the NVHL080N120SC1 Silicon Carbide MOSFET(N−Channel, 1200 V, 80 mW, TO247−3L).

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AND9957/D
All the fault lines are collected together to generate
a single input to the MCU which provides a hardware stopto the PWM generation. A reset of the failure conditions is
possible only by a reset command sent through a GUI or by

a power down/power up sequence, basically it representsa HW/SW reset. The Figure 4 summarizes the high level
SW behavior.

FAULT HANDLER(DESAT FAILURE FEEDBACK MANAGEMENT)ERROR

NO_FAULT

IDLE(Ini�aliza�on)

STOP
Wait 5 sec.

TMR_EXPIRED &&fault_cnt < NUMBER
OF THR. FAULTDC BUSVOLTAGE_CONTROL(normal behavior)

FAULT
PERMANENTADC OFFSETVERIFICATION

Adc oﬀset
validatedvBus1 notstableINRUSH RELAY

FAULTTEMPORARYRESET FAULT

vBus2 stable

vBus2 notstableINRUSH OVERCONTROL HANDLER(FLOW DIAGRAM BEFORE STARTING THE OUT VOLTAGE CONTROL ALGORITHM)

Figure 4. Flow Diagram of Preliminary Steps before Activating DC Bus Voltage Regulation

guarantee 0° of phase delay between each phase voltage andphase current, the voltage regulation acts on the D−axescurrent. Q−axes current is set to be 0. D−axes represents the“ACTIVE” power branch, while Q−axes represents the“REACTIVE” power branch. Figure 5 shows the block
diagram of the control algorithm.

Once the application is sitting in the DC BUS voltage
control state and in case of no failure events, the MCU will
run the field oriented (FOC) voltage control algorithm.
The control algorithm is similar to a motor control one
where the inner loops control the current components. Outerloop controls the bus voltage. Since the goal of the PFC is towww.onsemi.com
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AND9957/D
ϑVOLT
I D,REF

V BUS,REF
V BUS,MEAS

VBUS,MEASVOLTAGEREGULATIONVA,REFI D,MEAS
CURRENTREGULATIONI Q,REF = 0

VB,REFd A,REF

MODULATIONFOR DUTY CYCLE
GENERATION

VC,REF

I Q,MEAS

d B,REFd C,REF

I D,MEAS
I Q,MEAS
VBUS,MEAS

ANALOGSENSING

V BUS , VPHASES , IPHASESϑ VOLT

Figure 5. Control Block Diagram

In the Figure 7, a more detailed picture of theimplemented control loop is provided. Such control loop is
running at 20 kHz no matter what is going to be the selected
PWM modulation frequency. PWM frequency is almost
independent from the control frequency although there isa synchronization procedure in place in order to have ADC
peripheral triggered by a specific PWM counter value.
This procedure allows to keep a good relationship amongphase currents, in a star connected three−phase system withisolated neutral it is expected to have the instantaneous valueof the sum of the current equal to zero.
The MCU selected is a general−purpose one, based on anArm® M3, clock frequency 84 MHz, single S/H and ADC
with multiplexed input channels, 1 MSPS, and 12 bits.
Delay time for one ADC conversion is around 1 ms.
Because of the reading delay, of the fast PWM frequency,of the instantaneous switches’ status and of the boost
inductance, the current flowing in each phase can changequite significantly in very short time. Therefore, in order toovercome such problematic situation, the currents are
sampled across three continuous PWM periods. This meansthat the minimum PWM frequency selectable for a proper
functionality is three times the control strategy, thus 60 kHz.
Limitations of course are also present on the max PWM
frequency allowed, and it is 140 kHz. This limitation is
introduced by the wait time needed to perform themeasurement in each PWM period before triggering again
the ADC peripheral for a new measurement. Figure 6
displays the reason behind this limitation.

The analog quantities sampled to perform the control
algorithm are:• Phase currents (x3);• Line voltages, since the neutral point is not provided at the
input connector (x3);• DC bus voltage.
The line to line voltages are used to determine the actual
position of the AC voltage phasor. The angle, theta, is thenused for regulated the current phase delay to 0° that is themain target of the PFC. The voltage position is used forswitching from stationary ABC system reference into therotating DQ frame by means of Clark and Parketransformation (for the PFC, D axes means the amplitude of
the phase voltage phasor).
By knowing theta, all the electrical quantities can be thenexpressed in the DQ system, such simplification will ensure
the usage of simple PI/PID regulators. Just as a side note,
PID stands for Proportional Integral and Derivative
regulation that may be applied singularly or a combinationof them to the system. In any case, the proper selection
depends on the transfer function of the plant to be regulated.
PI regulators indeed can effectively regulates an error tozero when a constant is provided as reference quantity, while
are not capable of regulating AC reference quantities. In any
case, a calibration of PI regulators are needed in order toensure proper system stability with a good trade−off
between PI loop bandwidth and time response. It is typicalto expect fast response for the current loop (internal) andlower response on the external loop (voltage).

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CNTRL
INTERRUPTfCONTROLALG ORITHM

SAVE
ADC

ALG ORITHM

ADC TRAPT

PWM
counter for
duty cycle
generation

SAVE
ADC

ALG ORITHM

ADC TRAPT

SAVE
ADC

Value sampledprevious period are
now used in thecontrol algorithm

ALGORITHM

time

ADC TRAPT

fPWM
ADC
Trigger

ADC
Triggertime

ADC
Trigger

Phase current sample:
IA or IB or IC

ADC
PERIPHERALACTIVITYLine to Line voltage sample:
VAB or VBC or VCA
DCLINK voltage sample:
VDCBUS

Figure 6. Main Peripheral Interaction and Control Algorithm Execution

a deterministic delay between the moment when the analog
quantities is sampled from the ADC and the moment when
it is effectively used in the control strategy. Such delay,
however, is not compensated; the reason is because the main
working frequency is well below the selected control
frequency period and therefore the delay is treated as
negligible.
Once available the ADC quantities, the control
implementation is straightforward, Figure 7.

As can be seen from Figure 6, a new ADC trigger can beissued only once the three analog quantities (1 current and
2 voltages) have been sampled and the end of conversion
interrupt from the ADC has been issued to the CPU to store
the result data registers into memory and prepare the ADC
for a new measurement. Each procedure requires around
3.5 ms. After three PWM periods, ADC is no longer
triggered until a new control interrupt is happening thatre−initialize the reading strategy.
The quantities collected during a control period will be
used at the next available control period. There is

VD
PIREG
VBUS,TARGET

Voltage
Ramp

VREF

+
-

+

ID,REF +

+

-

+

PIREG

VD,REF+

VBUS,LP F

Adapta�ve
DREG

ID,EST

VA,REFCROSS
COUPLING

DQ → ABC

VB,REF
VC,REF-

IQ,REF = 0

+
-

PIREG

MODULATIONSTRATEGY
1. Sinusoi dal
2. Sin + 3 rd Harmonic
3. SVM
4. FBM
5. FTM
6. Discon�neous 1

VQ,REF+

IQ,EST

VQ

VBUS,LP F

LPF

vBus

ABC → DQ

iPhas es

IQ,EST
ID,EST

ADC MEASUREMENT&
POST-PROCESSING

ϑEST
VD
fEST , ϑEST

vLine

VQ

Figure 7. Control Algorithm, Detailed Description

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vBus

DutyCycle_A
DutyCycle_B
DutyCycle_C

AND9957/D
RELAYS
The relays layout foresees that at power on, the 13.6 W
power resistors mounted on the board are limiting the inrush
current. Resistor is disconnected by toggling the
INRUSH_OFF pin setting the digital value to high. At
power up, such pin is initialized low.

As said earlier, the modulation frequency can beselectable in a range between 60 kHz to 140 kHz and this iswhat it is the benefit of using silicon carbide MOSFET. Of
course, from system behavior point of view, increasing theswitching frequency will imply higher switching losses,
which will heat up substantially the die and will increase, inturn, the conduction losses since RDS,ON increases with thetemperature. For this reason it has been foreseen on theboard a fan with the intent of keeping the heatsink on which
the SiC MOSFETs are mounted, cooled down. The fan isdriven by the MCU but, at the moment, its speed is kept
fixed. A fan speed regulation could be implemented
according the active power delivery which is direct
proportional to ID,REF.
In order to mitigate losses and improve system efficiency,
different driving strategies can be implemented. Some moredetails are provided in the results section.

Gate Driver System

The board is provided with six symmetric structures ofgate drivers. Each of them consists of an isolated DCDC
converter, a digital isolator and the NCP51705 gate driver.
NVP51705 is a dedicated device for driving SiC MOSFET.
Each section presents 3 digital pins: 2 inputs and 1 output(from gate driver prospective; 2 outputs and 1 input if
considering from MCU side). MCU has to provide for eachdriver a disable signal; it actually represents the negatedinput of the PWM signal, and the PWM signal itself. MCU
has to sense the fault pin. It represents a failure condition atgate driver level.
In order to understand better the gate driver operation,refer to the gate driver datasheet available at onsemi.com
website.
When a gate driver failure is established, the gate driverwill automatically disable the PWM output. The fault pin isused for signaling to the MCU a failure condition. Such
failure is normally introduced because of an over current
event, although it could be also triggered by additional
abnormal conditions.
Once a failure event is happening, the PWM signals are nolonger provided to the gate drivers and the disable pin isagain engaged.
The fault pin of each gate driver is collected in an “or” portwith six inputs. The resulting PWM_FAULT is thenconnected to the hardware PWM failure pin available on the
MCU.
DISABLE pin should be initialized as HIGH in order todisable the gate driver functionality. When the control
strategy is capable of sending valid duty cycle information,
DISABLE has to be set low.

HW OVERVIEW
The system consists of two boards: a 4−layer power board
and a 4−layer control board.
The power board embeds:• All the circuit from the input to the bus voltage (relays,
boost inductors, SiC MOSFETs, dc bus cap),• First level circuitry for analog signal conditioning(treated into 5 V range),• A fan and its driving circuitry,• Gate driver sub−systems (replicated for each MOSFET),• High to 24 V DCDC converter,• Distributed connectors to minimize the loops length at theswitching nodes.
The control board embeds:• The microcontroller and the circuit for his isolated
programming (through serial communication),• 24 to various DC voltage level as depicted in Figure 3.
• Second level analog signal conditioning, taking the powerboards inputs and adjusting to 3.3 V range.

• Logic gates to handle the fault signals coming from the

TESTING
The following test results are generated supplying theboard with 230 Vrms at 50 Hz.
The control algorithm is configured to provide a switchingfrequency of 100 kHz with 100 ns of dead−time. The boost
inductor used has an average inductance value of 330 mH.
The gate resistor values for driving the MOSFET are 22 W
for sourcing and 4.7 W for sinking ensuring the following
switching characteristic at maximum current:

gate drivers.
• LEDs and distributed connectors as per power board.
FAN

The fan requires two pins:• FAN_ON_OFF: setting the pin high will provide the 24 V

to the fan.
• FAN_PWM: this is a pulse width modulated pin. Higher
duty will result in an increasing fan speed, thus anincreased forced air.

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AND9957/D

Figure 8. Switching Speed Low Side SiC MOSFET

Different PWM strategies implemented and tested. Eachof them affects the inductor high frequency current ripple
while the low frequency envelope follows the output target
power. Although the current ripple is linked to the PWM

frequency and bus voltage, it is also heavily affected by thezero sequence voltage. Zero sequence voltage affects thevoltage generation across the inductor in a PWM period.

VAM = VA0 − VM0

Figure 9. Tested Modulation Strategy

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Figure 10. Efficiency Results @ fPWM = 100 kHz

And finally system efficiency results of running the PFC board at 100 kHz selecting the discontinuous type 1 modulation
strategy.
99

EFFICIENCY [%]

98.5

98

97.5

97
2E+3

3E+3

4E+3

5E+3

6E+3

7E+3

8E+3

9E+3

1E+4

OUTPUT POWER [Watt]

Figure 11. Efficiency Results @ fPWM = 100 kHz

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