Interleaved High Boost Ratio Marx Topology DC-DC
Converter
Asmarashid bin Ponniran, Koji Orikawa and Jun-ichi Itoh
Nagaoka University of Technology
Nagaoka, Japan
asmarashid.ponniran@gmail.com
Abstract—This paper proposes an interleaved high boost ratio
three-stage Marx topology DC-DC boost converter (MTBC). In
the proposed circuit, the parallel connection is applied at the
input side in order to reduce the conduction loss and the copper
loss. Meanwhile the multi-stage connection is applied at theoutput side in order to reduce the voltage rating of switching
devices. In addition, with the interleaved switching scheme, themaximum current stress at a bottom switching device of thestage-I is reduced and the equivalent frequency at the output
side becomes twice of the switching frequency. As a result, theinductance of the output inductor is reduced compared to that ofa synchronized switching scheme. In addition, with theinterleaved switching scheme, the output inductor volume is also
reduced. Two prototypes of the three-stage MTBC areexperimentally verified in order to confirm the converter design
and the operation. Besides, the achieved maximum efficiency of
the three-stage MTBC prototype with the synchronizedswitching scheme is 94.5% at the output power of 500 W.

I.

INTRODUCTION

DC-DC converters with high boost ratio is required for
low DC voltage energy sources such as for electric vehicle(EV) systems, fuel-cell systems and photovoltaic (PV)systems. These systems usually need low-voltage and highcurrent power converters in order to supply DC power to a DC
bus or loads.
In a conventional DC-DC boost converter, a high boost
ratio is achieved by connecting those converters in cascade
connection [1]. However, with this topology, a high efficiency
is not possible to be achieved due to a number of cascade
connection of DC-DC converters. Besides, generally DC-DC
converters using high frequency transformers are also used inorder to obtain a high boost ratio [1-5]. However, thoseconverters usually suffer from the bulkiness of a transformer
and large losses. On the other hand, a high boost ratio isachieved with switched capacitor DC-DC converters [6-8].
However, the output voltage stress on the output capacitor isvery high and it requires many capacitors connected in series.

Besides, a Marx generator is one of the attractive
topologies which achieves a high boost ratio in DC-DC
converter. Basically, the purpose of the Marx generator is togenerate a high-voltage pulse from a low-voltage DC source[9,10]. However, the conventional Marx generator has highconduction losses and copper losses due to large input current.
As a result, a main application of the Marx generator is limited
for low power applications. On the other hand, the Marx
topology DC-DC converters with a resonant condition areproposed in order to achieve a ZCS condition for highefficiency [11,12]. However, due to the resonant condition, theinput inductor current should be in discontinuous current
mode (DCM) and consequently the input inductor current ishigh. Therefore, the conduction loss and copper loss of the
input inductor is increased due to high inductor current.
This paper proposes an interleaved Marx topology DC-DC
converter with high boost ratio for the inductance and volume
reductions of the output inductor. In the proposed circuit, theparallel connection of conventional two-level boost DC-DC
converters are applied at the input side in order to reduce theconduction loss and the copper loss. In addition, the multistage connections are applied at the output side in order toreduce the voltage ratings of stage capacitors and switches. In
the three-stage MTBC, the interleaved switching scheme isdefined as the stage-III operates alternately with stage-I andstage-II, meanwhile the synchronized switching scheme isdefined as all stages are operated synchronously. Thus, byintroducing the interleaved switching scheme in the threestage MTBC, the current stress at the bottom switching deviceof the stage-I is reduced half compared to that of thesynchronized switching scheme. Furthermore the equivalentfrequency at the output side becomes twice. As a result, theinductance and core volume of the output inductor are
reduced.
This paper is organized as follows. First, the principle
operation of the three-stage MTBC with the synchronizedswitching scheme and the interleaved switching scheme isdescribed. Then, the experimental results of the three-stage
MTBC with the synchronized switching scheme are discussed.
After that, the experimental results comparison between thesynchronized switching scheme and the interleaved switching
scheme are compared and discussed.
II. CONVERTER PRINCIPLE WITH THE SYNCHRONIZEDSWITCHING SCHEME AND INTERLEAVED SWITCHING SCHEME
Fig. 1 shows a circuit configuration of the three-stage
Marx topology boost converter (MTBC). Basically, eachstage of the MTBC consists of a conventional two-level boost
DC-DC converter, a capacitor and two additional switches.
The converter is designed based on a principle of the Marxpulse generator whereby a high-output voltage is generated
from a low-voltage DC source. This principle is realized bycharging a number of capacitors in parallel and then suddenly
connecting those capacitors in series. Therefore by arranging
these combinations of capacitors in the proposed converter, ahigh-output voltage is generated from a low-voltage DC
power source.
In this paper, the synchronized and the interleaved
switching schemes are applied into the three-stage MTBC.
The synchronized switching scheme in the three-stage MTBC
is defined as stage-I, stage-II and stage-III are operated
synchronously. Meanwhile, the interleaved switching scheme
in the three-stage MTBC is defined as stage-III is operated
alternately with stage-I and stage-II. By using the interleaved
switching scheme, the inductance and the core volume of theoutput inductor are reduced due to the increasing of theequivalent frequency at the output side.
In order to analyze the MTBC characteristic, the threestage MTBC with the synchronized switching scheme and theinterleaved switching scheme are analyzed. In principle, therelationship between the input voltage Vin and the output
voltage Vout is expressed as follows:

Vout = βVin(1)where β is the boost ratio. Meanwhile the boost ratios β interms of duty ratio D for synchronized and interleaved are
expressed as follow, respectively:

β synchronized =β interleaved =Dsynchronized
1 − Dsynchronizedn

2 Dinterleaved − 1n
1 − Dinterleaved

(2)

(3)

where D is the duty ratio for the switches S1a, S1b, S2a, S2b, S3aand S3b and n is the number of stage. Thus the output voltage
Vout in terms of the duty ratio D, the number of stage n andthe input voltage Vin can be rewrite as follows:

Fig. 1. three-stage MTBC circuit configuration.

⎛ D synchronized ⎞⎟nVVout (synchronized ) = ⎜⎜ 1 − D synchronized ⎟ in
⎝
⎠

(4)

⎛ 2D
−1 ⎞
⎟⎟nVinVout (interleaved ) = ⎜⎜ interleaved
1−Dinterleaved ⎠⎝(5)

The inductor current of each stage in the MTBC is
designed to be operated in continuous current mode (CCM) inorder to minimize the peak input current. Thus the minimum
inductor current of each stage should be greater than zero inorder to ensure a CCM condition is achieved. Then theminimum inductance of the input inductor of each stage Lin(m)for CCM operation is expressed as follows:n (Vin ) D
2 Pout f sw
2

Lin (m ) >(6)

where D is the duty ratio for the synchronized switching
scheme and the interleaved switching scheme, m is the n-th ofstage, n is the number stage, Pout is the output power and fsw isthe switching frequency.
Meanwhile the inductor current ripple on each stage
ΔILin(m) can be expressed as follows:

ΔI Lin(m ) =Vin D
f sw Lin(m )

(7)

L3

D3
C3

S3a

S3b

Lout

L3

D3

S3a

C3

L2

D2

D2

S2a

C2

S2a

C2

S2b
S2c

L1

∗

D1 =

Ton −a
Tsw

∗

D2 =

C1

S1b

Vin

L3

D3

S3a

C3

L2

D2

S2a

C2

The capacitance of the stage capacitor is expressed asfollows:

C (m ) =ΔVC (m ) f sw=

Pin (1 − D )nVin ΔVC (m ) f sw

(8)

where C(m) is the capacitance of the stage capacitor and ΔVC(m)is the stage capacitor voltage ripple.
III.

OPERATION MODES AND SWITCHING SCHEMES

The discussion of this section is based on the three-stage
MTBC. The groups of switches have been divided into two,
whereby S1a, S2a and S3a are considered in the input sideswitches group; meanwhile S1b, S1c, S2b, S2c, S3b, S3c switches
are considered in the output side switches group.
Fig. 2 shows the switching schemes of the synchronized
and the interleaved. Both switching schemes are considered
the dead-time Td and the additional time-delayed Ta in orderto prevent from a short circuit and a surge voltage. In theinterleaved switching scheme, the output side switches group

S1b

S3b

Lout

S3a
L2

S2b
Cout

Vout

L1

D1
C1

S2a

S1b

Vin

S1a

D3
C3

S3b

Lout

S3c
D2
C2

S2b
S2c

Cout

C1

S1b
S1c

Additional time-delay Ta
Synchronized – Mode 3
Interleaved – Mode 3,5,9,11

C1, C2, C3 – charging
Synchronized – Mode 4Interleaved – N/A

S2a
L1
Vin S
1a

L3

D3
C3

S3b

Lout

S3a

S3c

L2

D2
C2

S2b
S2c

Cout

D1
C1

S1b

Vout

S2a
L1

Vin S
1a

Vout

D1

S1c

L2

Fig. 2. Switching schemes.

I L (m )− ave (1 − D )

S1a

S3a

(b) Synchronized switching scheme.

C1

Dead-time Td
Synchronized – Mode 2
Interleaved – Mode 2,6,8,12

L3

Ton−a
Tsw

D1

S1a

Vout

C1, C2, C3 – discharging
Synchronized – Mode 1
Interleaved – Mode 1,7

L1

D=

Vin

L1

Cout

S1c

S2c

∗

S2c

S3c

(a) Interleaved switching scheme.

S2b

S1c

L3

2Ton−b
Tsw

Cout

Vout

D1

Vin S
1a

Lout

S3c

S3c
L2

S3b

D3
C3

S3b

Lout

S3c
D2
C2

S2b
S2c

Cout

Vout

D1
C1

S1b

S1c

S1c

C3 – charging
Synchronized – N/AInterleaved – Mode 4

S1c, S2c and S3c – ON
Synchronized – N/AInterleaved – Mode 10

Fig. 3. Three-stage MTBC operation modes ofsynchronized and interleaved switching schemes.

has a twice of the equivalent frequency of the input sideswitches group.
Fig. 3 shows the operation modes of the synchronizedswitching scheme and the interleaved switching scheme. The
synchronized switching scheme has 4 operation modes;
meanwhile the interleaved switching scheme has 12 operation
modes. In the synchronized switching scheme, the stages
capacitors C1, C2 and C3 are charging at the same time andthen those stage capacitors are discharging at the same time.

TABLE I.

Thus from these conditions, the output voltage can be boostup by advantage of a series connection of the stage
capacitors. Therefore, a high boost ratio is achieved.

EXPERIMENT SPECIFICATION.

On the other hand, in the interleaved switching scheme,
the stage capacitors C1 and C2 are charging together at thesame time; meanwhile C3 is charging alternately. During
discharging condition, the stage capacitors C1, C2 and C3 aredischarging at the same time. Thus in one cycle, withinterleaved switching scheme, the stage capacitors arecharged and discharged twice. Consequently, the equivalentfrequency at the output side is a twice of the switchingfrequency. A high boost ratio is achieved in the synchronized
and interleaved switching schemes.
In the synchronized switching scheme and interleaved
switching scheme, the maximum voltage stresses on theswitching devices S1a, S1b, S1c, S2a, S2b, S2c, S3a, S3b, S3c are
determined by each of the maximum stage capacitor voltages
VC1, VC2 and VC3. Meanwhile the voltage stresses on the D1,
D2 and D3 are equal to the VC1, 2VC2, and 3VC3, respectively.
Thus the top diode voltage stress VD3 is equal to total stage
capacitor voltages stress.
IV.

EXPERIMENTAL RESULTS OF THE SYNCHRONIZEDSWITCHING SCHEME

Fig. 4. Experimental waveforms of the stage-I, stage-II and stage-III
inductor currents with the synchronized switching scheme.

Table 1 shows the experiment specifications of the
prototype circuit. A range of output power is from 230 W to 1
kW. The inductance of the input inductor on each stage isdesigned by using (6).
Fig. 4 shows the experimental results of the input inductor
current ripples on stage-I (IL1), stage-II (IL2) and stage-III(IL3), which are 1.9 A, 1.8 A and 1.8 A respectively at theoutput power of 1 kW. However the designed input inductor
current ripple on each stage which is designed according to(7) is 1.5 A. The different between the experimental result
and the designed value is due to the voltage drop on thewinding resistance of the inductors. The average stage
inductor current is divided by three due to three parallelconnections at the input side. Therefore, if many stages are
considered, the average input current will be divided by thefactor of the stage number and consequently the input current
stress, the conduction loss and the copper loss are reduced.
Fig. 5 shows the experimental results of each stage
capacitor voltage is 190 V (VC1 = VC2 = VC3) on the threestage Marx topology DC-DC converter. Besides it isexperimentally confirmed that the output voltage of 400 V isachieved with the input voltage of 48 V. If the number ofstage is increased the voltage stress on stage capacitors andthe maximum voltage stress on switching devices is reduced.
The voltage stress on stage capacitor voltages and the
maximum voltage stress on switching devices are inversely
proportional to the number of stage.
Fig. 6 shows the efficiency characteristic of the prototype
circuit with the synchronized switching scheme. The
measured maximum efficiency is 94.5% at the output power

Fig. 5. Experimental waveforms of the stage-I, stage-II and stage-III
capacitor voltages, and the output voltage with the synchronizedswitching scheme.

96
94
92
90
88
86
200

400

600

800

1000

Fig. 6. Efficiency of the three-stage MTBC with the synchronizedswitching scheme.

of 500 W, meanwhile the efficiency at the output power of 1
kW is 93.0%.
In addition, the efficiency is decreased when the output
power is increased at 1 kW due to the increasing of the
conduction loss and the copper loss. On the other hand,during low output power, the power loss is dominated by theiron loss. As a result, the efficiency is low during low output
power.
V.

COMPARISON BETWEEN SYNCHRONIZED AND
INTERLEAVED SWITCHING SCHEMESIn this section the experimental results comparison interms of the input inductor current, the output inductor
current, the current between stage-III and stage-II (IS3C-S2C),
and the current between stage-II and stage-I (IS2C-S1C) between
the synchronized and interleaved switching schemes isdiscussed. These experimental results are based on the output
power of 1 kW. Table I shows the experiment specifications.

(a) With synchronized switching scheme when Lout = 800 μH.

Fig. 7 shows the experimental results of the current IS3C-

S2C, the current IS2C-S1C, the stage-III inductor current IL3 andthe output inductor current ILout of the synchronized andinterleaved switching schemes.

Fig. 7(a) shows the current IS2C-S1C has higher amplitude
compared to the current IS3C-S2C when the synchronizedswitching scheme is applied with Lout = 800 μH. Furthermore,
the frequency of the inductor current ripple at the input sideand the output side is same.
Fig. 7(b) shows that the current IS2C-S1C has same
amplitude value compared to the current IS3C-S2C when theinterleaved switching scheme is applied with Lout = 800 μH
which is same to that of the synchronized switching scheme.
Thus, by applying the interleaved switching scheme, thecurrent IS2C-S1C is reduced half. Therefore, by applying
interleaved switching scheme, the maximum current stress ofthe switching device S1C which is the bottom switch in thestage-I is reduced due to the reduction of the current IS2C-S1C.
Besides the equivalent frequency at the output side becomes
twice of the switching frequency in the interleaved operation.
As a result, the inductance of the output inductor is reduced
compared to that of the synchronized switching scheme.
Therefore, the core volume of the output inductor is reduced
due to the equivalent frequency at the output side which has
twice of the switching frequency.
Fig. 7(c) shows the experimental results of the currents
IS3C-S2C, IS2C-S1C, the stage-III input inductor current IL3, and theoutput inductor current ILout when the interleaved switching
scheme is applied with Lout = 640 μH which is designed forsame output inductor current ripple of the synchronizedswitching scheme. It is confirmed that the output inductor
current ripple ΔILout is 3.0 A which is agreed with that of thesynchronized switching scheme as shown in Fig. 7(a).
Therefore, it is experimentally confirmed that the inductanceof the output inductor is reduced on the three-stage MTBC
when the interleaved switching scheme is applied. In(b) With interleaved switching scheme when Lout = 800 μH.

(c) With interleaved switching scheme when Lout = 640 μH.
Fig. 7. Experimental waveforms of the current IS3C-S2C,
the current IS2C-S1C, the stage-III inductor current andthe output inductor current.

addition, the effective value of the current IS2C-S1C is same
between the synchronized switching scheme and theinterleaved switching scheme. Only the maximum current
stress is different. Hence, the overall conduction andswitching losses between the two switching schemes are
same. Consequently, the heatsink volume is also same at thetwo switching schemes. On the other hand, the capacitors
volumes are considered same.
In a high power application such as 10 kW, theinterleaved operation has an advantage of the current stressreduction of the switching devices S1C. Thus lower current
stress switching devices can be selected.
VI.

1

Fig. 8 shows the comparison of the inductance and core
volume of the output inductor. The relationship between the
inductance of the output inductors Lout(interleaved) andLout(synchronized) is expressed as follows:(9)

Lout (interleaved ) = 80% × Lout ( synchronized )Meanwhile based on the Area Product principle, the core
volume of the output inductors between synchronized andinterleaved Vol(Lout(interleaved)) and Vol(Lout(synchronized)) isexpressed as follows:

(

)

(

Vol Lout (interleaved ) = 84% × Vol Lout ( synchronized )

)

(10)

VII. CONCLUSION
This paper proposed the high boost ratio Marx topology
DC-DC boost converter which consists of the parallel
connection of several two-level conventional boost converters
at the input side and the multistage connection of capacitors at
the output side with the interleaved switching scheme. First,
the operation principles of the interleaved and synchronizedswitching schemes on the three-stage MTBC were analyzed
and compared. Then, the prototype circuits with theinterleaved and synchronized switching schemes wereexperimentally confirmed by the three-stage MTBC. As aresult, the maximum current stress at the bottom switch of thefirst stage at the output side was reduced half by theinterleaved switching scheme. Furthermore, in the interleaved
switching scheme, the equivalent frequency at the output side
becomes twice of the switching frequency. As a result, it isexperimentally confirmed that the inductance and core volumeof the output inductor are reduced. Moreover, the efficiency ofthe prototype converter with the synchronized switching

Vout = 400 V
fsw = 50 kHz

0.6

WITH INTERLEAVED SWITCHING SCHEME

Figs. 7(a) and 7(b) show the output inductor current
ripples during the synchronized and interleaved switching
schemes, 3.0 A and 2.4 A, respectively. The ratio between
both output inductor current ripples is 0.8 (80%), thus theinductance of the output inductor is reduced in interleaved
switching scheme by 20%. Consequently the volume of theoutput inductor is also reduced.

Lout = 640 uH

0.8

THE INDUCTANCE AND CORE VOLUME REDUCTION

In this section, the inductance and core volume of theoutput inductor are analyzed and compared between thesynchronized switching scheme and the interleaved switching
scheme. It is experimentally confirmed that the equivalentfrequency at the output side becomes twice of the switchingfrequency when the interleaved switching scheme is applied.
In this prototype, the switching frequency fsw is 50 kHz.
Therefore, the equivalent frequency at the output side
becomes 100 kHz in the interleaved switching scheme.

Lout = 800 uH

0.4
0.2
0
SynchronizedInterleaved
Switching scheme

Fig. 8. Output inductor volume estimation with thesynchronized and interleaved switching schemes.

scheme was 93.0% at the output power of 1 kW.
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