ICM-45605 Datasheet
High Performance 6-Axis MEMS MotionTracking Device
ICM-45605 HIGHLIGHTSFEATURES

The ICM-45605 is a high performance 6-axis MEMS
MotionTracking device. It has a configurable hostinterface that supports I3CSM, I2C and SPI serial
communication, and an I2C master mode interface forconnection to external sensors. The device features up
to 8Kbytes FIFO and 2 programmable interrupts.

•

The ICM-45605 supports the lowest gyro and accel
sensor noise in this IMU class, and has the highest
stability against temperature, shock (up to 20,000g) or
SMT/bend induced offset as well as immunity against
out-of-band vibration induced noise. Other industryleading features include InvenSense on-chip APEX
Motion Processing engine for gesture recognition,
activity classification, and pedometer, along with
programmable digital filters, and an embedded
temperature sensor.

•

•

•

•
•
•

•

Gyroscope Noise: 3.8 mdps/Hz &Accelerometer Noise: 70 µg/Hzo Low-Noise mode 6-axis current
consumption of 0.42 mA at 1600Hz
User selectable Gyro Full-scale range (dps):±15.625/±31.25/±62.5/±125/±250/±500/±1000/±2000
User selectable Accelerometer Full-scale
range (g): ±2/±4/±8/±16
User configurable internal pull-up/pull-downs
included on I/O interfaces to reduce systemcosts associated with external pull-ups/pulldowns
User configurable Output Data Rate (ODR)
and FIFO Data Rate (FDR)
User-programmable digital filters for gyro,
accel, and temp sensor
APEX Motion Functions:o Pedometer, Tilt Detection,
Single/Double Tap Detection, Raise
to Wake, Wake on Motion
o Free-Fall Detection, Significant
Motion Detection, Low-G Detection,
High-G Detection
Host interface: 12.9 MHz I3CSM, 1 MHz I2C,
24 MHz SPIAPPLICATIONS•BLOCK DIAGRAM

Game Controllers, Cameras, IoT, Drones,
Non-OIS SmartPhones, Wearables, Hearables

ORDERING INFORMATIONPARTTEMP RANGE

ICM-45605†−40°C to +85°C

PACKAGE
2.5x3mm
14-Pin LGA†Denotes RoHS and Green-Compliant Package

InvenSense Inc. reserves the right to change specifications andinformation herein without notice unless the product is in mass
production and the datasheet has been designated by InvenSense inwriting as subject to a specified Product / Process Change Notification
Method regulation.

InvenSense, a TDK Group Company
1745 Technology Drive, San Jose, CA 95110 U.S.A+1(408) 988–7339
invensense.tdk.com

Document Number: DS-000576
Revision: 1.0
Rev. Date: 07/25/2024

ICM-45605
TABLE OF CONTENTS
ICM-45605 Highlights ......................................................................................................................................... 1
Features .............................................................................................................................................................. 1
Applications ........................................................................................................................................................ 1
Block Diagram ..................................................................................................................................................... 1
Ordering Information ......................................................................................................................................... 1
1

2

3

4

Introduction ...................................................................................................................................................... 14
1.1

Purpose and Scope ................................................................................................................................ 14

1.2

Product Overview .................................................................................................................................. 14

1.3

Applications ........................................................................................................................................... 14

Features ............................................................................................................................................................ 15
2.1

Gyroscope Features ............................................................................................................................... 15

2.2

Accelerometer Features ........................................................................................................................ 15

2.3

Motion Features .................................................................................................................................... 15

2.4

Additional Features ................................................................................................................................ 16

Electrical Characteristics ................................................................................................................................... 17
3.1

Gyroscope Specifications ....................................................................................................................... 17

3.2

Accelerometer Specifications ................................................................................................................ 18

3.3

Electrical Specifications ......................................................................................................................... 19

3.4

I2C Timing Characterization ................................................................................................................... 21

3.5

SPI Timing Characterization – 4-Wire SPI Mode .................................................................................... 23

3.6

SPI Timing Characterization – 3-Wire SPI Mode .................................................................................... 24

3.7

Absolute Maximum Ratings ................................................................................................................... 25

Applications Information .................................................................................................................................. 26
4.1

Pin Out Diagram and Signal Description ................................................................................................ 26

4.2

Typical Operating Circuit (Dual Interface I2C Master Mode) ................................................................. 29

4.3

Typical Operating Circuit (Single Interface Mode) ................................................................................. 30

4.4Bill of Materials for External Components ............................................................................................. 31

4.5

System Block Diagram ........................................................................................................................... 32

4.6

Overview ................................................................................................................................................ 32

4.7

Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning .............................................. 33

4.8

Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning ....................................... 33

4.9

I3CSM, I2C and SPI Host Interface ............................................................................................................ 33

4.10

I2C Master Interface for Connection To External Sensors ................................................................. 33

4.11

Self-Test ............................................................................................................................................. 33

4.12

Clocking ............................................................................................................................................. 34

4.13

Sensor Data Registers ........................................................................................................................ 34

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ICM-45605
4.14Interrupts........................................................................................................................................... 34

4.15

Digital-Output Temperature Sensor .................................................................................................. 34

4.16

Bias and LDOs .................................................................................................................................... 34

4.17

Charge Pump ..................................................................................................................................... 34

4.18Standard Power Modes ..................................................................................................................... 35

5

Signal Path ........................................................................................................................................................ 36

6

FIFO................................................................................................................................................................... 37
6.1

Packet Structure .................................................................................................................................... 37

6.2

FIFO Header ........................................................................................................................................... 38

7

Programmable Interrupts ................................................................................................................................. 40

8

EDMP ................................................................................................................................................................ 41

9APEX Motion Functions .................................................................................................................................... 42

10

Digital Interface ................................................................................................................................................ 43

11

10.1

I3CSM, I2C and SPI Serial Interfaces .................................................................................................... 43

10.2

I3CSM Interface ................................................................................................................................... 43

10.3

I2C Interface ....................................................................................................................................... 46

10.4

I2C Master Interface .......................................................................................................................... 46

10.5

SPI Interface ...................................................................................................................................... 47

Assembly........................................................................................................................................................... 48
11.1

Orientation of Axes ........................................................................................................................... 48

11.2

Package Dimensions .......................................................................................................................... 49

12

Device Package In Tape And Reel ..................................................................................................................... 51

13

Part Number Package Marking ......................................................................................................................... 52

14

Indirect Register Access .................................................................................................................................... 53
14.1

Host Indirect Access Register (IREG) ................................................................................................. 53

14.2

General Rules for Accessing IREG ...................................................................................................... 53

14.3

Minimum Wait Time-Gap .................................................................................................................. 53

14.4

IREG Write ......................................................................................................................................... 53

14.5

IREG READ ......................................................................................................................................... 54

15

Device Configuration for Data Endianness ....................................................................................................... 55

16

Register Map .................................................................................................................................................... 56
16.1

User Bank 0 Register Map ................................................................................................................. 56

16.2

User Bank IMEM_SRAM Register Map .............................................................................................. 58

16.3

User Bank IPREG_BAR Register Map ................................................................................................. 61

16.4

User Bank IPREG_TOP1 Register Map ............................................................................................... 61

16.5

User Bank IPREG_SYS1 Register Map ................................................................................................ 63

16.6

User Bank IPREG_SYS2 Register Map ................................................................................................ 63

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17

User Bank 0 Register Map – Descriptions......................................................................................................... 64
17.1

ACCEL_DATA_X1_UI .......................................................................................................................... 64

17.2

ACCEL_DATA_X0_UI .......................................................................................................................... 64

17.3

ACCEL_DATA_Y1_UI .......................................................................................................................... 64

17.4

ACCEL_DATA_Y0_UI .......................................................................................................................... 64

17.5

ACCEL_DATA_Z1_UI .......................................................................................................................... 64

17.6

ACCEL_DATA_Z0_UI .......................................................................................................................... 65

17.7

GYRO_DATA_X1_UI ........................................................................................................................... 65

17.8

GYRO_DATA_X0_UI ........................................................................................................................... 65

17.9

GYRO_DATA_Y1_UI ........................................................................................................................... 65

17.10

GYRO_DATA_Y0_UI ........................................................................................................................... 65

17.11

GYRO_DATA_Z1_UI ........................................................................................................................... 66

17.12

GYRO_DATA_Z0_UI ........................................................................................................................... 66

17.13

TEMP_DATA1_UI ............................................................................................................................... 66

17.14

TEMP_DATA0_UI ............................................................................................................................... 66

17.15

TMST_FSYNCH ................................................................................................................................... 67

17.16

TMST_FSYNCL .................................................................................................................................... 67

17.17

PWR_MGMT0 .................................................................................................................................... 67

17.18

FIFO_COUNT_0 .................................................................................................................................. 68

17.19

FIFO_COUNT_1 .................................................................................................................................. 68

17.20

FIFO_DATA......................................................................................................................................... 68

17.21

INT1_CONFIG0 ................................................................................................................................... 69

17.22

INT1_CONFIG1 ................................................................................................................................... 71

17.23

INT1_CONFIG2 ................................................................................................................................... 72

17.24

INT1_STATUS0 ................................................................................................................................... 73

17.25

INT1_STATUS1 ................................................................................................................................... 74

17.26

ACCEL_CONFIG0 ................................................................................................................................ 75

17.27

GYRO_CONFIG0 ................................................................................................................................. 76

17.28

FIFO_CONFIG0 ................................................................................................................................... 77

17.29

FIFO_CONFIG1_0 ............................................................................................................................... 77

17.30

FIFO_CONFIG1_1 ............................................................................................................................... 78

17.31

FIFO_CONFIG2 ................................................................................................................................... 78

17.32

FIFO_CONFIG3 ................................................................................................................................... 79

17.33

FIFO_CONFIG4 ................................................................................................................................... 80

17.34

TMST_WOM_CONFIG........................................................................................................................ 81

17.35

FSYNC_CONFIG0 ................................................................................................................................ 82

17.36

DMP_EXT_SEN_ODR_CFG ................................................................................................................. 83

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18

17.37

ODR_DECIMATE_CONFIG .................................................................................................................. 84

17.38

EDMP_APEX_EN0 .............................................................................................................................. 85

17.39

EDMP_APEX_EN1 .............................................................................................................................. 85

17.40

APEX_BUFFER_MGMT ....................................................................................................................... 86

17.41

INTF_CONFIG0 ................................................................................................................................... 87

17.42

INTF_CONFIG1_OVRD ....................................................................................................................... 87

17.43

IOC_PAD_SCENARIO .......................................................................................................................... 88

17.44

IOC_PAD_SCENARIO_AUX_OVRD ..................................................................................................... 88

17.45

DRIVE_CONFIG0 ................................................................................................................................ 89

17.46

DRIVE_CONFIG1 ................................................................................................................................ 90

17.47

DRIVE_CONFIG2 ................................................................................................................................ 90

17.48

REG_MISC1 ........................................................................................................................................ 91

17.49

INT_APEX_CONFIG0 .......................................................................................................................... 92

17.50

INT_APEX_CONFIG1 .......................................................................................................................... 93

17.51

INT_APEX_STATUS0 ........................................................................................................................... 93

17.52

INT_APEX_STATUS1 ........................................................................................................................... 94

17.53

INT2_CONFIG0 ................................................................................................................................... 95

17.54

INT2_CONFIG1 ................................................................................................................................... 97

17.55

INT2_CONFIG2 ................................................................................................................................... 98

17.56

INT2_STATUS0 ................................................................................................................................... 99

17.57

INT2_STATUS1 ................................................................................................................................. 100

17.58

WHO_AM_I ..................................................................................................................................... 100

17.59

REG_HOST_MSG .............................................................................................................................. 101

17.60

IREG_ADDR_15_8 ............................................................................................................................ 101

17.61

IREG_ADDR_7_0 .............................................................................................................................. 101

17.62

IREG_DATA ...................................................................................................................................... 101

17.63

REG_MISC2 ...................................................................................................................................... 102

User Bank IMEM_SRAM Register Map – Descriptions ................................................................................... 103
18.1

IMEM_SRAM_REG_0 ....................................................................................................................... 103

18.2

IMEM_SRAM_REG_1 ....................................................................................................................... 103

18.3

IMEM_SRAM_REG_2 ....................................................................................................................... 103

18.4

IMEM_SRAM_REG_3 ....................................................................................................................... 103

18.5

IMEM_SRAM_REG_4 ....................................................................................................................... 104

18.6

IMEM_SRAM_REG_5 ....................................................................................................................... 104

18.7

IMEM_SRAM_REG_6 ....................................................................................................................... 104

18.8

IMEM_SRAM_REG_7 ....................................................................................................................... 104

18.9

IMEM_SRAM_REG_8 ....................................................................................................................... 105

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18.10

IMEM_SRAM_REG_9 ....................................................................................................................... 105

18.11

IMEM_SRAM_REG_10 ..................................................................................................................... 105

18.12

IMEM_SRAM_REG_11 ..................................................................................................................... 105

18.13

IMEM_SRAM_REG_56 ..................................................................................................................... 106

18.14

IMEM_SRAM_REG_57 ..................................................................................................................... 106

18.15

IMEM_SRAM_REG_64 ..................................................................................................................... 107

18.16

IMEM_SRAM_REG_68 ..................................................................................................................... 107

18.17

IMEM_SRAM_REG_92 ..................................................................................................................... 108

18.18

IMEM_SRAM_REG_96 ..................................................................................................................... 108

18.19

IMEM_SRAM_REG_97 ..................................................................................................................... 108

18.20

IMEM_SRAM_REG_98 ..................................................................................................................... 108

18.21

IMEM_SRAM_REG_99 ..................................................................................................................... 109

18.22

IMEM_SRAM_REG_100 ................................................................................................................... 109

18.23

IMEM_SRAM_REG_101 ................................................................................................................... 109

18.24

IMEM_SRAM_REG_102 ................................................................................................................... 109

18.25

IMEM_SRAM_REG_103 ................................................................................................................... 109

18.26

IMEM_SRAM_REG_104 ................................................................................................................... 110

18.27

IMEM_SRAM_REG_105 ................................................................................................................... 110

18.28

IMEM_SRAM_REG_106 ................................................................................................................... 110

18.29

IMEM_SRAM_REG_107 ................................................................................................................... 110

18.30

IMEM_SRAM_REG_136 ................................................................................................................... 111

18.31

IMEM_SRAM_REG_137 ................................................................................................................... 111

18.32

IMEM_SRAM_REG_138 ................................................................................................................... 111

18.33

IMEM_SRAM_REG_139 ................................................................................................................... 111

18.34

IMEM_SRAM_REG_141 ................................................................................................................... 112

18.35

IMEM_SRAM_REG_142 ................................................................................................................... 112

18.36

IMEM_SRAM_REG_143 ................................................................................................................... 112

18.37

IMEM_SRAM_REG_144 ................................................................................................................... 112

18.38

IMEM_SRAM_REG_146 ................................................................................................................... 113

18.39

IMEM_SRAM_REG_154 ................................................................................................................... 113

18.40

IMEM_SRAM_REG_155 ................................................................................................................... 113

18.41

IMEM_SRAM_REG_156 ................................................................................................................... 113

18.42

IMEM_SRAM_REG_157 ................................................................................................................... 114

18.43

IMEM_SRAM_REG_159 ................................................................................................................... 114

18.44

IMEM_SRAM_REG_160 ................................................................................................................... 114

18.45

IMEM_SRAM_REG_182 ................................................................................................................... 114

18.46

IMEM_SRAM_REG_185 ................................................................................................................... 115

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18.47

IMEM_SRAM_REG_186 ................................................................................................................... 115

18.48

IMEM_SRAM_REG_196 ................................................................................................................... 115

18.49

IMEM_SRAM_REG_197 ................................................................................................................... 115

18.50

IMEM_SRAM_REG_198 ................................................................................................................... 116

18.51

IMEM_SRAM_REG_199 ................................................................................................................... 116

18.52

IMEM_SRAM_REG_288 ................................................................................................................... 116

18.53

IMEM_SRAM_REG_289 ................................................................................................................... 117

18.54

IMEM_SRAM_REG_290 ................................................................................................................... 117

18.55

IMEM_SRAM_REG_291 ................................................................................................................... 117

18.56

IMEM_SRAM_REG_292 ................................................................................................................... 117

18.57

IMEM_SRAM_REG_293 ................................................................................................................... 118

18.58

IMEM_SRAM_REG_294 ................................................................................................................... 118

18.59

IMEM_SRAM_REG_295 ................................................................................................................... 118

18.60

IMEM_SRAM_REG_296 ................................................................................................................... 118

18.61

IMEM_SRAM_REG_297 ................................................................................................................... 119

18.62

IMEM_SRAM_REG_298 ................................................................................................................... 119

18.63

IMEM_SRAM_REG_299 ................................................................................................................... 119

18.64

IMEM_SRAM_REG_304 ................................................................................................................... 120

18.65

IMEM_SRAM_REG_305 ................................................................................................................... 120

18.66

IMEM_SRAM_REG_306 ................................................................................................................... 120

18.67

IMEM_SRAM_REG_307 ................................................................................................................... 120

18.68

IMEM_SRAM_REG_308 ................................................................................................................... 121

18.69

IMEM_SRAM_REG_309 ................................................................................................................... 121

18.70

IMEM_SRAM_REG_316 ................................................................................................................... 121

18.71

IMEM_SRAM_REG_317 ................................................................................................................... 121

18.72

IMEM_SRAM_REG_318 ................................................................................................................... 122

18.73

IMEM_SRAM_REG_319 ................................................................................................................... 122

18.74

IMEM_SRAM_REG_320 ................................................................................................................... 122

18.75

IMEM_SRAM_REG_321 ................................................................................................................... 122

18.76

IMEM_SRAM_REG_392 ................................................................................................................... 123

18.77

IMEM_SRAM_REG_393 ................................................................................................................... 123

18.78

IMEM_SRAM_REG_400 ................................................................................................................... 123

18.79

IMEM_SRAM_REG_401 ................................................................................................................... 124

18.80

IMEM_SRAM_REG_402 ................................................................................................................... 124

18.81

IMEM_SRAM_REG_403 ................................................................................................................... 124

18.82

IMEM_SRAM_REG_404 ................................................................................................................... 125

18.83

IMEM_SRAM_REG_405 ................................................................................................................... 125

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18.84

IMEM_SRAM_REG_406 ................................................................................................................... 125

18.85

IMEM_SRAM_REG_540 ................................................................................................................... 126

18.86

IMEM_SRAM_REG_541 ................................................................................................................... 126

18.87

IMEM_SRAM_REG_542 ................................................................................................................... 126

18.88

IMEM_SRAM_REG_543 ................................................................................................................... 127

18.89

IMEM_SRAM_REG_544 ................................................................................................................... 127

18.90

IMEM_SRAM_REG_545 ................................................................................................................... 127

18.91

IMEM_SRAM_REG_546 ................................................................................................................... 128

18.92

IMEM_SRAM_REG_547 ................................................................................................................... 128

18.93

IMEM_SRAM_REG_548 ................................................................................................................... 128

18.94

IMEM_SRAM_REG_549 ................................................................................................................... 129

18.95

IMEM_SRAM_REG_550 ................................................................................................................... 129

18.96

IMEM_SRAM_REG_551 ................................................................................................................... 129

18.97

IMEM_SRAM_REG_556 ................................................................................................................... 130

18.98

IMEM_SRAM_REG_557 ................................................................................................................... 130

18.99

IMEM_SRAM_REG_558 ................................................................................................................... 130

18.100

IMEM_SRAM_REG_559 .............................................................................................................. 131

18.101

IMEM_SRAM_REG_560 .............................................................................................................. 131

18.102

IMEM_SRAM_REG_561 .............................................................................................................. 131

18.103

IMEM_SRAM_REG_562 .............................................................................................................. 132

18.104

IMEM_SRAM_REG_563 .............................................................................................................. 132

18.105

IMEM_SRAM_REG_564 .............................................................................................................. 132

18.106

IMEM_SRAM_REG_565 .............................................................................................................. 133

18.107

IMEM_SRAM_REG_566 .............................................................................................................. 133

18.108

IMEM_SRAM_REG_567 .............................................................................................................. 133

18.109

IMEM_SRAM_REG_568 .............................................................................................................. 134

18.110

IMEM_SRAM_REG_569 .............................................................................................................. 134

18.111

IMEM_SRAM_REG_570 .............................................................................................................. 134

18.112

IMEM_SRAM_REG_571 .............................................................................................................. 135

18.113

IMEM_SRAM_REG_572 .............................................................................................................. 135

18.114

IMEM_SRAM_REG_573 .............................................................................................................. 135

18.115

IMEM_SRAM_REG_574 .............................................................................................................. 136

18.116

IMEM_SRAM_REG_575 .............................................................................................................. 136

18.117

IMEM_SRAM_REG_576 .............................................................................................................. 136

18.118

IMEM_SRAM_REG_577 .............................................................................................................. 137

18.119

IMEM_SRAM_REG_578 .............................................................................................................. 137

18.120

IMEM_SRAM_REG_579 .............................................................................................................. 137

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1920

18.121

IMEM_SRAM_REG_580 .............................................................................................................. 138

18.122

IMEM_SRAM_REG_581 .............................................................................................................. 138

18.123

IMEM_SRAM_REG_582 .............................................................................................................. 138

18.124

IMEM_SRAM_REG_583 .............................................................................................................. 139

18.125

IMEM_SRAM_REG_584 .............................................................................................................. 139

18.126

IMEM_SRAM_REG_585 .............................................................................................................. 139

18.127

IMEM_SRAM_REG_586 .............................................................................................................. 140

18.128

IMEM_SRAM_REG_587 .............................................................................................................. 140

18.129

IMEM_SRAM_REG_988 .............................................................................................................. 140

18.130

IMEM_SRAM_REG_989 .............................................................................................................. 141

18.131

IMEM_SRAM_REG_990 .............................................................................................................. 141

18.132

IMEM_SRAM_REG_991 .............................................................................................................. 141

18.133

IMEM_SRAM_REG_994 .............................................................................................................. 142

18.134

IMEM_SRAM_REG_995 .............................................................................................................. 142

18.135

IMEM_SRAM_REG_1000 ............................................................................................................ 142

18.136

IMEM_SRAM_REG_1001 ............................................................................................................ 143

18.137

IMEM_SRAM_REG_1002 ............................................................................................................ 143

18.138

IMEM_SRAM_REG_1003 ............................................................................................................ 143

18.139

IMEM_SRAM_REG_1004 ............................................................................................................ 144

18.140

IMEM_SRAM_REG_1008 ............................................................................................................ 144

18.141

IMEM_SRAM_REG_1009 ............................................................................................................ 144

18.142

IMEM_SRAM_REG_1010 ............................................................................................................ 145

18.143

IMEM_SRAM_REG_1011 ............................................................................................................ 145

18.144

IMEM_SRAM_REG_1016 ............................................................................................................ 145

18.145

IMEM_SRAM_REG_1017 ............................................................................................................ 146

18.146

IMEM_SRAM_REG_1018 ............................................................................................................ 146

18.147

IMEM_SRAM_REG_1019 ............................................................................................................ 146

18.148

IMEM_SRAM_REG_1042 ............................................................................................................ 147

18.149

IMEM_SRAM_REG_1168 to IMEM_SRAM_REG_1203 ............................................................... 147

User Bank IPREG_BAR Register Map – Descriptions ...................................................................................... 148
19.1

IPREG_BAR_REG_57 ........................................................................................................................ 148

19.2

IPREG_BAR_REG_58 ........................................................................................................................ 149

19.3

IPREG_BAR_REG_59 ........................................................................................................................ 150

19.4

IPREG_BAR_REG_60 ........................................................................................................................ 151

19.5

IPREG_BAR_REG_61 ........................................................................................................................ 152

19.6

IPREG_BAR_REG_62 ........................................................................................................................ 153

User Bank IPREG_TOP1 Register Map – Descriptions .................................................................................... 154

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20.1

I2CM_COMMAND_0 ....................................................................................................................... 154

20.2

I2CM_COMMAND_1 ....................................................................................................................... 155

20.3

I2CM_COMMAND_2 ....................................................................................................................... 156

20.4

I2CM_COMMAND_3 ....................................................................................................................... 157

20.5

I2CM_DEV_PROFILE0 ...................................................................................................................... 158

20.6

I2CM_DEV_PROFILE1 ...................................................................................................................... 158

20.7

I2CM_DEV_PROFILE2 ...................................................................................................................... 158

20.8

I2CM_DEV_PROFILE3 ...................................................................................................................... 158

20.9

I2CM_CONTROL ............................................................................................................................... 159

20.10

I2CM_STATUS .................................................................................................................................. 159

20.11

I2CM_EXT_DEV_STATUS ................................................................................................................. 160

20.12

I2CM_RD_DATA0 ............................................................................................................................. 160

20.13

I2CM_RD_DATA1 ............................................................................................................................. 161

20.14

I2CM_RD_DATA2 ............................................................................................................................. 161

20.15

I2CM_RD_DATA3 ............................................................................................................................. 161

20.16

I2CM_RD_DATA4 ............................................................................................................................. 162

20.17

I2CM_RD_DATA5 ............................................................................................................................. 162

20.18

I2CM_RD_DATA6 ............................................................................................................................. 162

20.19

I2CM_RD_DATA7 ............................................................................................................................. 163

20.20

I2CM_RD_DATA8 ............................................................................................................................. 163

20.21

I2CM_RD_DATA9 ............................................................................................................................. 163

20.22

I2CM_RD_DATA10 ........................................................................................................................... 164

20.23

I2CM_RD_DATA11 ........................................................................................................................... 164

20.24

I2CM_RD_DATA12 ........................................................................................................................... 164

20.25

I2CM_RD_DATA13 ........................................................................................................................... 165

20.26

I2CM_RD_DATA14 ........................................................................................................................... 165

20.27

I2CM_RD_DATA15 ........................................................................................................................... 165

20.28

I2CM_RD_DATA16 ........................................................................................................................... 166

20.29

I2CM_RD_DATA17 ........................................................................................................................... 166

20.30

I2CM_RD_DATA18 ........................................................................................................................... 166

20.31

I2CM_RD_DATA19 ........................................................................................................................... 167

20.32

I2CM_RD_STATUS20 ....................................................................................................................... 167

20.33

I2CM_WR_DATA0 ............................................................................................................................ 167

20.34

I2CM_WR_DATA1 ............................................................................................................................ 167

20.35

I2CM_WR_DATA2 ............................................................................................................................ 168

20.36

I2CM_WR_DATA3 ............................................................................................................................ 168

20.37

I2CM_WR_DATA4 ............................................................................................................................ 168

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ICM-45605

21

20.38

I2CM_WR_DATA5 ............................................................................................................................ 168

20.39

SIFS_IXC_ERROR_STATUS ................................................................................................................ 169

20.40

EDMP_PRGRM_IRQ0_0 ................................................................................................................... 169

20.41

EDMP_PRGRM_IRQ0_1 ................................................................................................................... 169

20.42

EDMP_PRGRM_IRQ1_0 ................................................................................................................... 170

20.43

EDMP_PRGRM_IRQ1_1 ................................................................................................................... 170

20.44

EDMP_PRGRM_IRQ2_0 ................................................................................................................... 170

20.45

EDMP_PRGRM_IRQ2_1 ................................................................................................................... 170

20.46

EDMP_SP_START_ADDR .................................................................................................................. 171

20.47

SMC_CONTROL_0 ............................................................................................................................ 171

20.48

SMC_CONTROL_1 ............................................................................................................................ 172

20.49

STC_CONFIG .................................................................................................................................... 172

20.50

SREG_CTRL ...................................................................................................................................... 173

20.51

SIFS_I3C_STC_CFG ........................................................................................................................... 173

20.52

INT_PULSE_MIN_ON_INTF0 ............................................................................................................ 174

20.53

INT_PULSE_MIN_ON_INTF1 ............................................................................................................ 174

20.54

INT_PULSE_MIN_OFF_INTF0 ........................................................................................................... 174

20.55

INT_PULSE_MIN_OFF_INTF1 ........................................................................................................... 175

20.56

ISR_0_7 ............................................................................................................................................ 175

20.57

ISR_8_15 .......................................................................................................................................... 176

20.58

ISR_16_23 ........................................................................................................................................ 176

20.59

STATUS_MASK_PIN_0_7 ................................................................................................................. 177

20.60

STATUS_MASK_PIN_8_15 ............................................................................................................... 178

20.61

STATUS_MASK_PIN_16_23 ............................................................................................................. 179

20.62

INT_I2CM_SOURCE .......................................................................................................................... 179

20.63

ACCEL_WOM_X_THR....................................................................................................................... 179

20.64

ACCEL_WOM_Y_THR ....................................................................................................................... 180

20.65

ACCEL_WOM_Z_THR ....................................................................................................................... 180

20.66

SELFTEST .......................................................................................................................................... 181

20.67

IPREG_MISC ..................................................................................................................................... 181

20.68

SW_PLL1_TRIM ................................................................................................................................ 182

20.69

FIFO_SRAM_SLEEP .......................................................................................................................... 182

User Bank IPREG_SYS1 Register Map – Descriptions ..................................................................................... 183
21.1

IPREG_SYS1_REG_42 ....................................................................................................................... 183

21.2

IPREG_SYS1_REG_43 ....................................................................................................................... 183

21.3

IPREG_SYS1_REG_56 ....................................................................................................................... 183

21.4

IPREG_SYS1_REG_57 ....................................................................................................................... 183

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ICM-45605

22

21.5

IPREG_SYS1_REG_70 ....................................................................................................................... 184

21.6

IPREG_SYS1_REG_71 ....................................................................................................................... 184

21.7

IPREG_SYS1_REG_166 ..................................................................................................................... 184

21.8

IPREG_SYS1_REG_170 ..................................................................................................................... 185

21.9

IPREG_SYS1_REG_172 ..................................................................................................................... 185

User Bank IPREG_SYS2 Register Map – Descriptions ..................................................................................... 186
22.1

IPREG_SYS2_REG_24 ....................................................................................................................... 186

22.2

IPREG_SYS2_REG_25 ....................................................................................................................... 186

22.3

IPREG_SYS2_REG_32 ....................................................................................................................... 186

22.4

IPREG_SYS2_REG_33 ....................................................................................................................... 186

22.5

IPREG_SYS2_REG_40 ....................................................................................................................... 187

22.6

IPREG_SYS2_REG_41 ....................................................................................................................... 187

22.7

IPREG_SYS2_REG_123 ..................................................................................................................... 187

22.8

IPREG_SYS2_REG_129 ..................................................................................................................... 188

22.9

IPREG_SYS2_REG_131 ..................................................................................................................... 188

23

Reference ....................................................................................................................................................... 189

24

Revision History .............................................................................................................................................. 190

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ICM-45605
TABLE OF FIGURES
Figure 1. I2C Bus Timing Diagram .................................................................................................................................22
Figure 2. 4-Wire SPI Bus Timing Diagram ....................................................................................................................23
Figure 3. 3-Wire SPI Bus Timing Diagram ....................................................................................................................24
Figure 4. Pin Out Diagram for ICM-45605 2.5x3.0x0.81 mm LGA ...............................................................................29
Figure 5. ICM-45605 Application Schematic Dual Interface I2C Master Mode (I3CSM / I2C Interface to Host) ............29
Figure 6. ICM-45605 Application Schematic Dual Interface I2C Master Mode (SPI Interface to Host) ........................30
Figure 7. ICM-45605 Application Schematic Single Interface Mode (I3CSM / I2C Interface to Host) ............................30
Figure 8. ICM-45605 Application Schematic Single Interface Mode (SPI Interface to Host) .......................................31
Figure 9. ICM-45605 System Block Diagram ................................................................................................................32
Figure 10. ICM-45605 Signal Path ................................................................................................................................36
Figure 11. Typical SPI Master/Slave Configuration ......................................................................................................47
Figure 12. Orientation of Axes of Sensitivity and Polarity of Rotation ........................................................................48
Figure 13. ICM-45605 Device Package in Tape and Reel .............................................................................................51
Figure 14. Tape Dimensions with ICM-45605 Device Package ....................................................................................51

TABLE OF TABLES
Table 1. Gyroscope Specifications ...............................................................................................................................17
Table 2. Accelerometer Specifications ........................................................................................................................18
Table 3. D.C. Electrical Characteristics .........................................................................................................................19
Table 4. A.C. Electrical Characteristics .........................................................................................................................20
Table 5. I2C Host Interface Timing Characteristics .......................................................................................................21
Table 6. I2C Master Interface Timing Characteristics ...................................................................................................21
Table 7. 4-Wire SPI Timing Characteristics ..................................................................................................................23
Table 8. 3-Wire SPI Timing Characteristics ..................................................................................................................24
Table 9. Absolute Maximum Ratings ...........................................................................................................................25
Table 10. Signal Descriptions .......................................................................................................................................28
Table 11. Bill of Materials ............................................................................................................................................31
Table 12. Standard Power Modes for ICM-45605 .......................................................................................................35
Table 13. I3CSM CCC Commands...................................................................................................................................46

Page 13 of 191
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ICM-45605
1
1.1

INTRODUCTIONPURPOSE AND SCOPE

This document is a product specification, providing a description, specifications, and design related information on
the ICM-45605 Dual-Interface MotionTracking device. The device is housed in a small 2.5x3x0.81 mm 14-pin LGA
package.

1.2

PRODUCT OVERVIEWThe ICM-45605 is a 6-axis MotionTracking device with a configurable host interface that supports I3C SM, I2C and SPI
serial communication, and an I2C master mode interface for connection to external sensors. It combines a 3-axis
gyroscope, and a 3-axis accelerometer in a small 2.5x3x0.81 mm (14-pin LGA) package.
ICM-45605 also features up to 8Kbytes FIFO that can lower the traffic on the serial bus interface, and reduce
power consumption by allowing the system processor to burst read sensor data and then go into a low-power
mode. ICM-45605, with its 6-axis integration, enables manufacturers to eliminate the costly and complex selection,
qualification, and system level integration of discrete devices, guaranteeing optimal motion performance for
consumers.
The gyroscope supports independently programmable full-scale range settings from ±15.625dps to ±2000dps for
the UI path, and the accelerometer supports independently programmable full-scale range settings from ±2g to±16g for the UI path.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded
temperature sensor, and programmable interrupts. The device features I3CSM, I2C and SPI serial interfaces, a VDD
operating range of 1.71V to 3.6V, and a separate VDDIO operating range of 1.08V to 3.6V.
The host interface can be configured to support I3CSM slave, I2C slave, or SPI slave modes. The I3CSM interface
supports speeds up to 12.9MHz (data rates up to 12.9Mbps in SDR mode, 25.8Mbps in DDR mode), the I2C
interface supports speeds up to 1MHz, and the SPI interface supports speeds up to 24MHz.
User configurable internal pull-up/pull-downs are included on I/O interfaces to reduce system costs associatedwith external pull-ups/pull-downs.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers
with companion CMOS electronics through wafer-level bonding, TDK InvenSense has driven the package size down
to a footprint and thickness of 2.5x3x0.81 mm (14-pin LGA), to provide a very small yet high performance low costpackage. The device provides high robustness by supporting 20,000g shock reliability.

1.3

APPLICATIONS
•
•
•
•
•
•
•

Game Controllers
CamerasIoT
Drones
Non-OIS SmartPhones
Wearables
Hearables

Page 14 of 191
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ICM-45605
2

FEATURES

2.1

GYROSCOPE FEATURES

The triple-axis MEMS gyroscope in the ICM-45605 includes a wide range of features:•

Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with independently programmable fullscale range of ±15.625, ±31.25, ±62.5, ±125, ±250, ±500, ±1000, and ±2000 degrees/sec for UI and
auxiliary paths•

Low Noise (LN) and Low Power (LP) power modes support•

Digitally-programmable low-pass filters•

Self-test

2.2

ACCELEROMETER FEATURES

The triple-axis MEMS accelerometer in ICM-45605 includes a wide range of features:•

Digital-output X-, Y-, and Z-axis accelerometer with independently programmable full-scale range of ±2g,
±4g, ±8g and ±16g for UI and auxiliary paths•

Low Noise (LN) and Low Power (LP) power modes support•

User-programmable interrupts•

Wake-on-motion interrupt for low power operation of applications processor•

Self-test

2.3

MOTION FEATURES

ICM-45605 includes the following motion features, also known as APEX (Advanced Pedometer and Event Detection– neXt gen)•Pedometer: Tracks Step Count, also issues Step Detect interrupt.

•

Tilt Detection: Issues an interrupt when the Tilt angle exceeds 35 for more than a programmable time.

•

Raise to Wake/Sleep: Gesture detection for wake and sleep events. Interrupt is issued when either ofthese two events are detected.

•

Single Tap / Double Tap Detection: Issues an interrupt when a tap is detected, along with the tap type.

•

Wake on Motion: Detects motion when accelerometer data exceeds a programmable threshold.

•Freefall Detection: Triggers an interrupt when device freefall is detected and outputs freefall duration.

•

Significant Motion Detection: Detects significant motion based on accelerometer data.

•

Low-G Detection: Triggers an interrupt when absolute value of accelerometer combined axis falls below a
programmable threshold and stays below the threshold for a programmable time.

•High-G Detection: Triggers an interrupt when absolute value of accelerometer goes above a
programmable threshold and stays above the threshold for a programmable time.

Page 15 of 191
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ICM-45605
2.4

ADDITIONAL FEATURES

ICM-45605 includes the following additional features:•

Up to 8Kbytes FIFO buffer enables the applications processor to read the data in bursts, default FIFO size
is 2Kbytes, user can extend it up to 8kByte by disabling APEX functions•

EDMP Enhanced Digital Motion Processor for implementing motion algorithms•

20-bits data format support in FIFO for high-data resolution•

User-programmable digital filters for gyroscope, accelerometer, and temperature sensor•

Main interface: 12.5MHz I3CSM (data rates up to 12.5Mbps in SDR mode, 25Mbps in DDR mode) / 1 MHz
I2C / 24 MHz SPI slave host interface•

Auxiliary interface: 400 kHz I2C master•

User configurable internal pull-up/pull-downs included on I/O interfaces to reduce system costs
associated with external pull-ups/pull-downs•

User configurable Output Data Rate (ODR) and FIFO Data Rate (FDR)•

Digital-output temperature sensor•

Smallest and thinnest LGA package for portable devices: 2.5x3x0.81 mm (14-pin LGA)•

20,000 g shock tolerant•

MEMS structure hermetically sealed and bonded at wafer level•

RoHS and Green compliant

Page 16 of 191
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ICM-45605
3

ELECTRICAL CHARACTERISTICS

3.1

GYROSCOPE SPECIFICATIONS

Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

NOTES

GYROSCOPE SENSITIVITY
GYRO_UI_FS_SEL =1

±2000

º/s

3

GYRO_UI_FS_SEL =2

±1000

º/s

3

GYRO_UI_FS_SEL =3

±500

º/s

3

GYRO_UI_FS_SEL =4

±250

º/s

3

GYRO_UI_FS_SEL =5

±125

º/s

3

GYRO_UI_FS_SEL =6

±62.5

º/s

3

GYRO_UI_FS_SEL =7±31.25º/s

3

GYRO_UI_FS_SEL =8±15.625º/s

3Output in two’s complement format

16

bits

3, 6

GYRO_UI_FS_SEL =1

16.4

LSB/(º/s)

3

GYRO_UI_FS_SEL =2

32.8

LSB/(º/s)

3

GYRO_UI_FS_SEL =365.5

LSB/(º/s)

3

GYRO_UI_FS_SEL =4131

LSB/(º/s)

3

GYRO_UI_FS_SEL =5262

LSB/(º/s)

3

GYRO_UI_FS_SEL =6524.3

LSB/(º/s)

3

GYRO_UI_FS_SEL =71048.6

LSB/(º/s)

3

GYRO_UI_FS_SEL =82097.2

LSB/(º/s)

3

Sensitivity Scale Factor Initial Tolerance

Component-level, 25°C

±0.5

%

2

Sensitivity Change vs. Temperature-40°C to +85°C, board-level

±0.01

%/ºC

1, 8

Nonlinearity

Best fit straight line; board-level, 25°C

±0.1

%

1, 8

Cross-Axis Sensitivity

Board-level

±1

%

1, 8

Full-Scale Range

Gyroscope ADC Word Length

Sensitivity Scale Factor

ZERO-RATE OUTPUT (ZRO)
Initial ZRO Tolerance

Component-level, 25°C

±0.5

º/s

2

ZRO Change vs. Temperature-40°C to +85°C, board-level±0.015º/s/ºC1, 8

Rate Noise Spectral Density@ 10 Hz, 25°C

0.0038º/s /√Hz2, 4

Total RMS Noise

Bandwidth = 100 Hz

0.038º/s-rms

4, 5

29.7
35

kHz
ms
Hz
Hz

2
1, 7
3
3

OTHER PARAMETERS

Gyroscope Mechanical Frequencies
Gyroscope Start-Up Time
Output Data Rate

Time from gyro enable to gyro drive ready
Low Noise Mode (LNM)
Low Power Mode (LPM)

12.5
1.5625

45
6400
400

Table 1. Gyroscope Specifications
Notes:
1.
2.
3.
4.
5.
6.
7.
8.

Derived from validation or characterization of parts, not tested in production.
Tested in production.
Guaranteed by design.
Noise specifications shown are for low-noise mode.
Calculated from Rate Noise Spectral Density.
20-bits data format supported in FIFO, see section 6.
Measurement conditions: Gyroscope ODR = 6400Hz; Register field GYRO_UI_LPFBW_SEL set to 000 (low pass filter bypassed.
Board-level specs performance depends on specific board design of TDK-InvenSense test boards and may not be directly reproducible with other board designs.

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ICM-45605
3.2

ACCELEROMETER SPECIFICATIONS

Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

NOTES

ACCELEROMETER SENSITIVITY

Full-Scale Range

ADC Word Length

Sensitivity Scale Factor

Sensitivity Scale Factor
Initial Tolerance
Sensitivity Change vs.
Temperature

ACCEL_UI_FS_SEL = 1

±16

g

3

ACCEL_UI_FS_SEL = 2

±8

g

3

ACCEL_UI_FS_SEL = 3

±4

g

3

ACCEL_UI_FS_SEL = 4

±2

g

3

Output in two’s complement format

16

bits

3, 6

ACCEL_UI_FS_SEL = 1

2,048

LSB/g

3

ACCEL_UI_FS_SEL = 2

4,096

LSB/g

3

ACCEL_UI_FS_SEL = 3

8,192

LSB/g

3

ACCEL_UI_FS_SEL = 4

16,384

LSB/g

3

%

2

±0.5

Component-level, 25°C
-40°C to +85°C, board-level

±0.01

%/ºC

1, 8

Nonlinearity

Best fit straight line, ±2g; board-level, 25°C

±0.1

%

1, 8

Cross-Axis Sensitivity

Board-level

±1

%

1, 8

ZERO-G OUTPUT
Initial Tolerance

Component-level, 25°C

±15

mg

2

Zero-G Level Change
vs. Temperature-40°C to +85°C, board-level

±0.15

mg/ºC

1, 8

@ 10 Hz; Up to ±8g FSR

70µg/√Hz2, 4@ 10 Hz; ±16g FSR

80µg/√Hz2, 4Bandwidth = 100 Hz; Up to ±8g FSR

0.7

mg-rms4, 5Bandwidth = 100 Hz; ±16g FSR

0.8

mg-rms4, 5Accelerometer Startup
Time

From sleep mode to valid data

10

ms

1, 7

Output Data Rate

Low Noise Mode (LNM)
Low Power Mode (LPM)

12.5
1.5625

3
3

OTHER PARAMETERS
Noise Spectral Density
RMS Noise

12.5
1.56256400
400

Table 2. Accelerometer Specifications
Notes:
1.
2.
3.
4.
5.
6.
7.
8.

Derived from validation or characterization of parts, not tested in production.
Tested in production.
Guaranteed by design.
Noise specifications shown are for low-noise mode.
Calculated from Rate Noise Spectral Density.
20-bits data format supported in FIFO, see section 6.
Measurement conditions: Gyroscope ODR = 6400Hz; Register field GYRO_UI_LPFBW_SEL set to 000 (low pass filter bypassed.
Board-level specs performance depends on specific board design of TDK-InvenSense test boards and may not be directly reproducible with other board designs.

Page 18 of 191
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ICM-45605
3.3

ELECTRICAL SPECIFICATIONS

3.3.1 D.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

NOTES

VDD

1.71

1.8

3.6

V

1

VDDIO

1.08*

1.8

3.6

V

1

SUPPLY VOLTAGESSUPPLY CURRENTS
6-Axis Gyroscope + Accelerometer (1600Hz ODR)

420

µA

2

6-Axis Gyroscope + Accelerometer (6400Hz ODR)

440

µA

2

3-Axis Accelerometer (1600Hz ODR)

120

µA

2

3-Axis Accelerometer (6400Hz ODR)

130

µA

2

3-Axis Gyroscope (1600Hz ODR)

360

µA

2

3-Axis Gyroscope (6400Hz ODR)

370

µA

2

220

µA

2

325

µA

2

3-Axis Accelerometer (50Hz ODR; 4x AVG)

67

µA

2

3-Axis Gyroscope (50Hz ODR; 10x AVG)

210

µA

2

Ultra Low-Power Mode

3-Axis Accelerometer (50Hz ODR; 1x AVG)

15

µA

2

Full-Chip Sleep ModeAt 25ºC

2.2

µA

2

°C

1

Low-Noise Mode

6-Axis Gyroscope + Accelerometer(50Hz ODR; Gyro 10x AVG; Accel 4x AVG)
6-Axis Gyroscope + Accelerometer
Low-Power Mode

Specified Temperature Range(200Hz ODR; Gyro 10x AVG; Accel 4x AVG)TEMPERATURE RANGE
Performance parameters are not applicable beyond
Specified Temperature Range-40

Table 3. D.C. Electrical Characteristics
Notes:
1.
2.

Guaranteed by design.
Derived from validation or characterization of parts, not tested in production.

* Important Note: When using I3CSM interface the minimum VDDIO value is 1.1V.

Page 19 of 191
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ICM-45605
3.3.2 A.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERCONDITIONSMIN

SUPPLIES
Valid power-on RESET Monotonic ramp. Ramp
rate is 10% to 90% of the final value

Supply Ramp TimePower Supply Noise

VDD=1.8V or 3.6V, up to 1MHz

Operating Range
25°C Output
ADC Resolution
ODR
Room Temperature Offset
Stabilization Time (fixed number of clock
cycles)Sensitivity
Sensitivity for FIFO data

Ambient

Start-up time for register read/write

From power-up

TYP

0.01
10

MAX

UNITS

NOTES

1

ms

50

mV
peak-peak

1

°C
LSB
bits
Hz
°C

1
3
2
2, 4
3

1

TEMPERATURE SENSOR-4085

Output in two’s complement format

016With Filter
25°C

1.5625
-5

3200
5
0.014

TrimmedTrimmedsec

2LSB/°C
LSB/°C

1
1

1

ms

1

128
2

POWER-ON RESETI2C ADDRESSAP_AD0 = 0
AP_AD0 = 1

I2C ADDRESS

1101000
1101001

DIGITAL INPUTS (FSYNC, SCLK, SDI, CS)
VIH, High Level Input Voltage

0.7*VDDIOVDDIO +
0.5V

V

VIL, Low Level Input Voltage-0.5V

0.3*VDDIOV

CI, Input Capacitance<10

VOH, High Level Output Voltage

RLOAD=1 MΩ;

VOL1, LOW-Level Output Voltage

RLOAD=1 MΩ;

VOL.INT, INT Low-Level Output Voltage
Output Leakage Current

V

VIL, LOW-Level Input Voltage
VIH, HIGH-Level Input Voltage

100 or 8

V

0.1

V

µs

-0.5V

0.3*VDDIO

V

0.7*VDDIOVDDIO +
0.5V

V

0.1*VDDIO

VOL, LOW-Level Output Voltage
IOL, LOW-Level Output Current

3 mA sink current

03
6

Output Leakage Current
tof, Output Fall Time from VIHmax to VILmax

Clock Frequency Initial Tolerance
Frequency Variation over Temperature

1

nA
300

ns

INTERNAL CLOCK SOURCE
-1.25

+1.25

%

1

-1.25

+1.25

%

1

Gyro inactive; -40°C to +85°C

±3

%

1

Gyro active; -40oC to +85oC

±1

%

1

Gyro inactive; 25°C

20+0.1Cb

V
mA
mA

100
Cb bus capacitance in pf

Gyro active; 25°C

Table 4. A.C. Electrical Characteristics
Based on design. Not tested in production.
Guaranteed by design.
Production tested.
Temperature sensor ODR is the higher value between gyroscope and accelerometer ODR.

Page 20 of 191
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V0.4

VOL=0.4 V
VOL=0.6 V

1

nA
100

Vhys, Hysteresis

Notes:
1.
2.
3.
4.

0.1*VDDIO

100

int0_tpulse_duration= 0 , 1 (100µs, 8µs)
int1_tpulse_duration= 0 , 1 (100µs, 8µs)
I2C I/O (SCL, SDA)tINT, INT Pulse Width

pF

DIGITAL OUTPUT (SDO, INT1, INT2)
0.9*VDDIO

OPEN=1, 0.3 mA sink
Current
OPEN=11

ICM-45605
3.4

I2C TIMING CHARACTERIZATION

Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
Parameters

Conditions

I2C TIMING (Host Interface)

I2C FAST-MODE PLUSMin

TypicalfSCL, SCL Clock Frequency

Max

Units

Notes

1

MHz

1

tHD.STA, (Repeated) START Condition Hold Time

0.26

µs

1

tLOW, SCL Low Period

0.50

µs

1

tHIGH, SCL High Period

0.26

µs

1

tSU.STA, Repeated START Condition Setup Time

0.26

µs

1

tHD.DAT, SDA Data Hold Time

0

µs

1

tSU.DAT, SDA Data Setup Time

50

ns

1

120

ns

1, 2

120

ns

1, 2

µs

1

µs

1

130

pF

1

0.45
0.45

µs

1

µs

1

Max

Units

Notes

400

tr, SDA and SCL Rise TimeCb bus cap. from 30 to 130 pF

tf, SDA and SCL Fall TimeCb bus cap. from 30 to 130 pF

tSU.STO, STOP Condition Setup Time

20 x
(VDD / 5.5 V)
0.26

tBUF, Bus Free Time Between STOP and START
Condition

0.50

Cb, Capacitive Load for each Bus Line

30

tVD.DAT, Data Valid Time
tVD.ACK, Data Valid Acknowledge Time

Table 5. I2C Host Interface Timing Characteristics
Notes:
1.
2.

Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
Transition times are defined between thresholds: 0.3*VDDIO, 0.7*VDDIO.

Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
Parameters

Conditions

I2C TIMING (Master Interface)

I2C FAST-MODE

Min

fSCL, SCL Clock Frequency

TypicalkHz

1tHD.STA, (Repeated) START Condition Hold Time

0.60

µs

1

tLOW, SCL Low Period

1.30

µs

1

tHIGH, SCL High Period

0.60

µs

1

tSU.STA, Repeated START Condition Setup Time

0.60

µs

1

tHD.DAT, SDA Data Hold Time

0

µs

1

tSU.DAT, SDA Data Setup Time

100

ns

1

tr, SDA and SCL Rise TimeCb bus cap. from 30 to 200 pF

20

300

ns

1, 2

tf, SDA and SCL Fall TimeCb bus cap. from 30 to 200 pF

20 x(VDD / 5.5 V)

300

ns

1, 2

0.60

µs

1

µs

1

200

pF

1

0.90
0.90

µs

1

µs

1

tSU.STO, STOP Condition Setup TimetBUF, Bus Free Time Between STOP and START
Condition

1.30

Cb, Capacitive Load for each Bus Line

30

tVD.DAT, Data Valid Time
tVD.ACK, Data Valid Acknowledge Time

Table 6. I2C Master Interface Timing Characteristics
Notes:
1.
2.

Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
Transition times are defined between thresholds: 0.3*VDDIO, 0.7*VDDIO.

Page 21 of 191
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Revision: 1.0

ICM-45605
tf
SDA

tSU.DAT

tr

70%
30%

70%
30%
continued below at

tf
SCL

tr
70%
30%

S

tHD.STA

tVD.DAT
70%
30%

tHD.DAT
1/fSCLtLOW

1st clock cycle

9th clock cycle

tHIGH

tBUF
SDA

70%
30%

A

tSU.STA

tHD.STA

SCL

70%
30%

Sr

tSU.STO

tVD.ACK
9th clock cycle

Figure 1. I2C Bus Timing Diagram

Page 22 of 191
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Revision: 1.0

P

S

A

ICM-45605
3.5

SPI TIMING CHARACTERIZATION – 4-WIRE SPI MODE

Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERSVDDIO < 1.71V
MIN
MAX

CONDITIONSVDDIO ≥ 1.71V
MIN
MAX

UNITS

NOTES

24

SPI TIMING
fSPC, SCLK Clock Frequency

MHz

1

tLOW, SCLK Low Period

Default
23.5

17

ns

1

tHIGH, SCLK High Period

22.5

17

ns

1

tSU.CS, CS Setup Time

17

17

ns

1

tHD.CS, CS Hold Time

5

5

ns

1

tSU.SDI, SDI Setup Time

13

13

ns

1

tHD.SDI, SDI Hold Time

8

8

ns

1

ns

1

ns

1

ns

1

tVD.SDO, SDO Valid Time

Cload = 20 pF

tHD.SDO, SDO Hold Time

Cload = 20 pF

20

18.5

18.5

3.5

tDIS.SDO, SDO Output Disable Time

3.5
28

28

Table 7. 4-Wire SPI Timing Characteristics
Notes:
1.

CS

Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets

70%
30%

tFall

tSU;CS
SCLK

tHIGH

tRise

1/fCLK

tHD;CS

70%
30%

tSU;SDI

SDI

70%
30%

tLOW

tHD;SDILSB INMSB INtVD;SDOSDOMSB OUT

70%
30%

Figure 2. 4-Wire SPI Bus Timing Diagram

Page 23 of 191
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Revision: 1.0

tDIS;SDO

tHD;SDOLSB OUTICM-45605
3.6

SPI TIMING CHARACTERIZATION – 3-WIRE SPI MODE

Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERSVDDIO < 1.71V
MIN
MAX

CONDITIONSVDDIO ≥ 1.71V
MIN
MAX

UNITS

NOTES

24

SPI TIMING
fSPC, SCLK Clock Frequency

MHz

1

tLOW, SCLK Low Period

Default
23.5

17

ns

1

tHIGH, SCLK High Period

22.5

17

ns

1

tSU.CS, CS Setup Time

17

17

ns

1

tHD.CS, CS Hold Time

5

5

ns

1

tSU.SDIO, SDIO Input Setup Time

13

13

ns

1

tHD.SDIO, SDIO Input Hold Time

8

8

ns

1

ns

1

ns

1

ns

1

tVD.SDIO, SDIO Output Valid Time

Cload = 20 pF

tHD.SDIO, SDIO Output Hold Time

Cload = 20 pF

20

18.5

18.5

3.5

tDIS.SDIO, SDIO Output Disable Time

3.5
28

28

Table 8. 3-Wire SPI Timing Characteristics
Notes:
1.

CS

Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets

70%
30%

tFall

tSU;CS
SCLK

tHIGH

tRise

1/fCLK

tHD;CS

70%
30%

tSU;SDIO

SDIO

I

O

70%
30%

tLOW

tHD;SDIOLSB INMSB INtVD;SDIOMSB OUT

70%
30%

Figure 3. 3-Wire SPI Bus Timing Diagram

Page 24 of 191
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Revision: 1.0

tDIS;SDIOtHD;SDIOLSB OUTICM-45605
3.7

ABSOLUTE MAXIMUM RATINGS

Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These arestress ratings only and functional operation of the device at these conditions is not implied. Exposure to theabsolute maximum ratings conditions for extended periods may affect device reliability.
Parameter

RatingSupply Voltage, VDD-0.5 V to +4 V

Supply Voltage, VDDIO-0.5 V to +4 V

Input Voltage Level (FSYNC, SCL, SDA)

-0.5 V to VDDIO + 0.5 V

Acceleration (Any Axis, unpowered)

20,000g for 0.2 ms

Operating Temperature Range-40°C to +85°C

Storage Temperature Range-40°C to +125°C
2 kV (HBM);

Electrostatic Discharge (ESD) Protection

500 V (CDM)
JEDEC Class II (2) for VDDIO≤ 1.98V, JEDEC Class I (1) for
VDDIO > 1.98V, ±100 mA

Latch-up
Table 9. Absolute Maximum Ratings

Page 25 of 191
Document Number: DS-000576
Revision: 1.0

ICM-45605
44.1
Pin Number

1

2

APPLICATIONS INFORMATIONPIN OUT DIAGRAM AND SIGNAL DESCRIPTION
Pin Name

AP_SDO /AP_AD0RESV /
MAS_DA

Single Interface Mode

AP_SDO: AP SPI serial data
output (4-wire mode);
AP_AD0: AP I3CSM / I2C
slave address LSBRESV: No Connect orConnect to VDDIO or
Connect to GND

Dual Interface I2C Master
Mode

AP_SDO: AP SPI serial data
output (4-wire mode);
AP_AD0: AP I3CSM / I2C slave
address LSB

MAS_DA: I2C serial master
data

Notes
By default, internal pull-up is enabled. The internal weak pullup is not strong enough to replace a pull-up resistor usuallyused on an open-drain bus. This pin supports both internal
pull up and pull-down functionality. Internal pull up/down iscontrolled by two registers pads_ap_sdo_pe_trim_d2a[0] andpads_ap_sdo_pud_trim_d2a[0]. Internal pull-up can bedisabled (enabled) by configuringpads_ap_sdo_pe_trim_d2a[0] = 0 (1) and internal pull
direction down (up) can be set bypads_ap_sdo_pud_trim_d2a[0] = 0 (1).
If the AP interface is active, the internal pull-up should bedisabled by setting pads_ap_sdo_pe_trim_d2a[0] = 0.
By default, internal pull-up is enabled. The internal weak pullup is not strong enough to replace a pull-up resistor usuallyused on an open-drain bus. This pin supports both internal
pull up and pull-down functionality. Internal pull up/down iscontrolled by two registers
pads_aux1_sdi_pe_trim_d2a[0]andpads_aux1_sdi_pud_trim_d2a[0].
Internal pull-up can be disabled (enabled) by configuringpads_aux1_sdi_pe_trim_d2a[0] = 0 (1) and internal pull
direction down (up) can be set bypads_aux1_sdi_pud_trim_d2a[0] = 0 (1).

If the AUX1 interface is active, the internal pull-up should bedisabled by setting pads_aux1_sdi_pe_trim_d2a[0] = 0.

3

RESV /
MAS_CLKRESV: No Connect orConnect to VDDIO or
Connect to GND

MAS_CLK: I2C serial masterclock

If pin2 is no connect, leave pads_aux1_sdi_pe_trim_d2a[0] =1. If pin2 is connected to VDDIO or GND, disable internal pullup by setting pads_aux1_sdi_pe_trim_d2a[0] = 0.
By default, internal pull-up is enabled. The internal weak pullup is not strong enough to replace a pull-up resistor usuallyused on an open-drain bus. This pin supports both internal
pull up and pull-down functionality. Internal pull up/down iscontrolled by two registers
pads_aux1_sclk_pe_trim_d2a[0]andpads_aux1_sclk_pud_trim_d2a[0]Internal pull-up can be disabled (enabled) by configuringpads_aux1_sclk_pe_trim_d2a[0] = 0 (1) and internal pull
direction down (up) can be set bypads_aux1_sclk_pud_trim_d2a[0] = 0 (1).

If the AUX1 interface is active, the internal pull-up should bedisabled by setting pads_aux1_sclk_pe_trim_d2a[0] = 0.

4

INT1 / INT

INT1: Interrupt 1 (Note:
INT1 can be push-pull oropen drain); INT: All

INT1: Interrupt 1 (Note: INT1
can be push-pull or open
drain); INT: All interrupts
mapped to pin 4

Page 26 of 191
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Revision: 1.0

If pin3 is no connect, leave pads_aux1_sclk_pe_trim_d2a[0] =1. If pin3 is connected to VDDIO or GND, disable internal pullup by setting pads_aux1_sclk_pe_trim_d2a[0] = 0.
By default, internal pull-up is disabled. The internal weak pullup is not strong enough to replace a pull-up resistor usuallyused on an open-drain bus. This pin supports both internalICM-45605
interrupts mapped to pin
4

5

VDDIO

6

GND

7

RESV

VDDIO: IO power supply
voltage
GND: Power supply
groundRESV: No Connect orConnect to VDDIO or
Connect to GND

pull up and pull-down functionality. Internal pull up/down iscontrolled by two registers
pads_int1_pe_trim_d2a[0] andpads_int1_pud_trim_d2a[0]. Internal pull can be disabled(enabled) by configuring pads_int1_pe_trim_d2a[0] = 0 (1)and internal pull direction down (up) can be set bypads_int1_pud_trim_d2a[0] = 0 (1).
VDDIO: IO power supply
voltage
GND: Power supply ground

RESV: No Connect or Connect
to VDDIO or Connect to GND

By default, internal pull-up is enabled. The internal weak pullup is not strong enough to replace a pull-up resistor usuallyused on an open-drain bus. This pin supports both internal
pull up and pull-down functionality. Internal pull up/down iscontrolled by two registers
pads_pin7_pe_trim_d2a[0]and pads_pin7_cs_pud_trim_d2a[0]. Internal pull can bedisabled (enabled) by configuring pads_pin7_pe_trim_d2a[0]= 0 (1) and internal pull direction down (up) can be set bypads_pin7_cs_pud_trim_d2a[0] = 0 (1).
If pin7 is no connect, leave pads_pin7_pe_trim_d2a[0] = 1. If
pin7 is connected to VDDIO or GND, disable internal pull-up
by setting pads_pin7_pe_trim_d2a[0] = 0.

8

VDD

INT2 /
FSYNC

9

10

11

RESV

RESV

VDD: Power supply
voltage

INT2: Interrupt 2 (Note:
INT2 can be push-pull oropen drain); FSYNC: Frame
sync input; If pin not used,
can be No Connect orConnect to VDDIORESV: No Connect orConnect to VDDIO or
Connect to GND

RESV: No Connect orConnect to VDDIO or
Connect to GND

VDD: Power supply voltage

INT2: Interrupt 2 (Note: INT2
can be push-pull or open
drain); FSYNC: Frame sync
input; If pin not used, can be
No Connect or Connect to
VDDIORESV: No Connect or Connect
to VDDIO or Connect to GND

RESV: No Connect or Connect
to VDDIO or Connect to GND

Page 27 of 191
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Revision: 1.0

By default, internal pull-up is enabled. The internal weak pullup is not strong enough to replace a pull-up resistor usuallyused on an open-drain bus. This pin supports both internal
pull up and pull-down functionality. Internal pull up/down iscontrolled by two registers pads_int2_pe_trim_d2a[0] andpads_int2_pud_trim_d2a[0]. Internal pull-up can be disabled(enabled) by configuring pads_int2_pe_trim_d2a[0] = 0 (1)and internal pull direction down (up) can be set bypads_int2_pud_trim_d2a[0] = 0 (1).

If pin9 is no connect, leave pads_int2_pe_trim_d2a[0] = 1. If
pin9 is connected as an I/O, disable internal pull-up by setting
pads_int2_pe_trim_d2a[0] = 0.
By default, internal pull-up is enabled. The internal weak pullup is not strong enough to replace a pull-up resistor usuallyused on an open-drain bus. This pin supports both internal
pull up and pull-down functionality. Internal pull up/down iscontrolled by two registers
pads_aux1_cs_pe_trim_d2a[0]and pads_aux1_cs_pud_trim_d2a[0]. Internal pull-up can bedisabled (enabled) by configuringpads_aux1_cs_pe_trim_d2a[0] = 0 (1) and internal pull
direction down (up) can be set bypads_aux1_cs_pud_trim_d2a[0] = 0 (1).
If the AUX1 interface is active, the internal pull-up should bedisabled by setting pads_aux1_cs_pe_trim_d2a[0] = 0. If
pin10 is no connect, leave pads_aux1_cs_pe_trim_d2a[0] = 1.
If pin10 is connected to VDDIO or GND, disable internal pullup by setting pads_aux1_cs_pe_trim_d2a[0] = 0.
By default, internal pull-up is enabled. The internal weak pullup is not strong enough to replace a pull-up resistor usuallyused on an open-drain bus. This pin supports both internal
pull up and pull-down functionality. Internal pull up/down iscontrolled by two registersICM-45605
pads_aux1_sdo_pe_trim_d2a[0]andpads_aux1_sdo_pud_trim_d2a[0]. Internal pull-up can bedisabled (enabled) by configuringpads_aux1_sdo_pe_trim_d2a[0] = 0 (1) and internal pull
direction down (up) can be set bypads_aux1_sdo_pud_trim_d2a[0] = 0 (1).

12

13

AP_CS

AP_SCL /AP_SCLK

AP_CS: AP SPI Chip select(AP SPI interface); Connect
to VDDIO if using AP I3CSM/ I2C interface

AP_SCL: AP I3CSM / I2C
serial clock; AP_SCLK: AP
SPI serial clock

AP_CS: AP SPI Chip select (APSPI interface); Connect to
VDDIO if using AP I3CSM / I2C
interface

AP_SCL: AP I3CSM / I2C serial
clock; AP_SCLK: AP SPI serialclock

If AUX1 interface is active, the internal pull-up should bedisabled by setting pads_aux1_sdo_pe_trim_d2a[0] = 0. If
pin11 is no connect, leave pads_aux1_sdo_pe_trim_d2a[0] =1. If pin11 is connected to VDDIO or GND, disable internal
pull-up by setting pads_aux1_sdo_pe_trim_d2a[0] = 0.
By default, internal pull-up is enabled. The internal weak pullup is not strong enough to replace a pull-up resistor usuallyused on an open-drain bus. This pin supports both internal
pull up and pull-down functionality. Internal pull up/down iscontrolled by two registers pads_ap_cs_pe_trim_d2a[0] andpads_ap_cs_pud_trim_d2a[0]. Internal pull can be disabled(enabled) by configuring pads_ap_cs_pe_trim_d2a[0] = 0 (1)and internal pull direction down (up) can be set bypads_ap_cs_pud_trim_d2a[0] = 0 (1).
If the AP interface is active, the internal pull-up should bedisabled by setting pads_ap_cs_pe_trim_d2a[0] = 0.
By default, internal pull-up is enabled. The internal weak pullup is not strong enough to replace a pull-up resistor usuallyused on an open-drain bus. This pin supports both internal
pull up and pull-down functionality. Internal pull up/down iscontrolled by two registers pads_ap_sclk_pe_trim_d2a[0]and pads_ap_sclk_pud_trim_d2a[0]. Internal pull can bedisabled (enabled) by configuringpads_ap_sclk_pe_trim_d2a[0] = 0 (1) and internal pull
direction down (up) can be set bypads_ap_sclk_pud_trim_d2a[0] = 0 (1).
If the AP interface is active, the internal pull-up should bedisabled by setting pads_ap_sclk_pe_trim_d2a[0] = 0.

14

AP_SDA /AP_SDIO /AP_SDI

AP_SDA: AP I3CSM / I2C
serial data; AP_SDIO: AP
SPI serial data I/O (3-wiremode); AP_SDI: AP SPI
serial data input (4-wiremode)

AP_SDA: AP I3CSM / I2C serial
data; AP_SDIO: AP SPI serial
data I/O (3-wire mode);
AP_SDI: AP SPI serial data
input (4-wire mode)

By default, internal pull-up is enabled. The internal weak pullup is not strong enough to replace a pull-up resistor usuallyused on an open-drain bus. This pin supports both internal
pull up and pull-down functionality. Internal pull up/down iscontrolled by two registers pads_ap_sdi_pe_trim_d2a[0] andpads_ap_sdi_pud_trim_d2a[0]. Internal pull can be disabled(enabled) by configuring pads_ap_sdi_pe_trim_d2a[0] = 0 (1)and internal pull direction down (up) can be set bypads_ap_sdi_pud_trim_d2a[0] = 0 (1).
If the AP interface is active, the internal pull-up should bedisabled by setting pads_ap_sdi_pe_trim_d2a[0] = 0.

Table 10. Signal Descriptions

Page 28 of 191
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AP_SDA / AP_SDIO / AP_SDI

AP_SCL / AP_SCLK

AP_CS

14

13

12

ICM-45605+Z

AP_SDO / AP_AD0

1

11

RESV

RESV / MAS_DA

2

10

RESV

RESV / MAS_CLK3

9

INT2 / FSYNC

INT1 / INT

4

8

VDD

7

6
GND

+Y

+X

RESV

5
VDDIO

ICM-45605+Y+Z

Figure 4. Pin Out Diagram for ICM-45605 2.5x3.0x0.81 mm LGA

4.2

TYPICAL OPERATING CIRCUIT (DUAL INTERFACE I2C MASTER MODE)

MAS_DA
MAS_CLK
INT1 / INT

14

AP_SCL

AP_SDA

AP_AD0

13

VDDIO

12

1

2

11

RESV

10

RESV

ICM-45605
3

9

4

8

INT2 / FSYNC– 3.6VDC

5

6

VDD

7

RESV

GND

VDDIO

C1, 0.1 mF– 3.6VDC
C2, 0.1 µ F* Important Note: When using I3CSM interface the minimum VDDIO value is 1.1V.

Figure 5. ICM-45605 Application Schematic Dual Interface I2C Master Mode (I3CSM / I2C Interface to Host)

Note: I2C lines are open drain and pull-up resistors (e.g. 10 kΩ) are required.

Page 29 of 191
Document Number: DS-000576
Revision: 1.0+XICM-45605
AP_SDIO /AP_SDI

AP_SCLK

AP_SDO

AP_CS

14

13

12

1

MAS_DA

2

11

RESV

10

RESV

ICM-45605

MAS_CLK

3

9

4

8

INT2 / FSYNC– 3.6VDC

INT1 / INT

5

6

VDD

7

RESV

GND

VDDIO

C1, 0.1 mF– 3.6VDC
C2, 0.1 µ F* Important Note: When using I3CSM interface the minimum VDDIO value is 1.1V.

Figure 6. ICM-45605 Application Schematic Dual Interface I2C Master Mode (SPI Interface to Host)

4.3

TYPICAL OPERATING CIRCUIT (SINGLE INTERFACE MODE)

AP_SCLRESV

AP_SDA

AP_AD0

14

13

VDDIO

12

1

2

11

RESV

10

RESV

ICM-45605
RESV
INT1 / INT

3

9

4

8

INT2 / FSYNC– 3.6VDC

5

6

VDD

7

RESV

GND

VDDIO

C1, 0.1 mF– 3.6VDC
C2, 0.1 µ F* Important Note: When using I3CSM interface the minimum VDDIO value is 1.1V.

Figure 7. ICM-45605 Application Schematic Single Interface Mode (I3CSM / I2C Interface to Host)

Note: I2C lines are open drain and pull-up resistors (e.g. 10 kΩ) are required.

Page 30 of 191
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Revision: 1.0

ICM-45605
AP_SCLKRESV

AP_SDIO /AP_SDI

AP_SDO

AP_CS

14

13

12

1

2

11

RESV

10

RESV

ICM-45605
RESV
INT1 / INT

3

9

4

8

INT2 / FSYNC– 3.6VDC

5

6

VDD

7

RESV

GND

VDDIO

C1, 0.1 mF– 3.6VDC
C2, 0.1 µ F* Important Note: When using I3CSM interface the minimum VDDIO value is 1.1V.

Figure 8. ICM-45605 Application Schematic Single Interface Mode (SPI Interface to Host)

4.4

BILL OF MATERIALS FOR EXTERNAL COMPONENTS
Component

LabelSpecification

VDD Bypass Capacitor

C1

X7R, 0.1µF ±10%

1

VDDIO Bypass Capacitor

C2

X7R, 0.1µF ±10%

1Table 11. Bill of Materials

Note: Use larger bypass capacitor than 0.1µF if power supply ripple exceeds 50mV peak-to-peak.

Page 31 of 191
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Revision: 1.0

QuantityICM-45605
4.5

SYSTEM BLOCK DIAGRAM

Figure 9. ICM-45605 System Block Diagram

Note: The above block diagram is an example. Please refer to the pin-out (section 4.1) for other configuration
options.

4.6

OVERVIEWThe ICM-45605 is comprised of the following key blocks and functions:
•
•
•
•
•
•
•
•
•
•
•
•
•

Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioningo 20-bits data format support in FIFO for high-data resolution (see section 5 for details)
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioningo 20-bits data format support in FIFO for high-data resolution (see section 5 for details)
I3CSM, I2C and SPI Host Interface
I2C Master Interface for connection to external sensors
Self-Test
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Standard Power Modes

Page 32 of 191
Document Number: DS-000576
Revision: 1.0

ICM-45605
4.7

THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONINGThe ICM-45605 includes a vibratory MEMS rate gyroscope, which detects rotation about the X-, Y-, and Z- Axes.
When the gyroscope is rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detectedby a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that is
proportional to the angular rate. This voltage is digitized using on-chip Analog-to-Digital Converters (ADCs) to
sample each axis. The full-scale range of the gyro sensors may be digitally programmed to ±15.625, ±31.25, ±62.5,±125, ±250, ±500, ±1000, and ±2000degrees per second (dps).

4.8

THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONINGThe ICM-45605 includes a 3-Axis MEMS accelerometer. Acceleration along a particular axis induces displacementof a proof mass in the MEMS structure, and capacitive sensors detect the displacement. The ICM-45605
architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. Whenthe device is placed on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The
accelerometers’ scale factor is calibrated at the factory and is nominally independent of supply voltage. The fullscale range of the digital output can be adjusted to ±2g, ±4g, ±8g, and ±16g.

I3CSM, I2C AND SPI HOST INTERFACE

4.9

The ICM-45605 communicates to the application processor using an I3CSM, I2C, or SPI serial interface. The ICM45605 always acts as a slave when communicating to the application processor.

4.10

I2C MASTER INTERFACE FOR CONNECTION TO EXTERNAL SENSORSThe ICM-45605 has an I2C master interface for connection to external sensors.
Up to 2 external sensors can be connected on this interface and their data read into the ICM-45605. I2C speed up
to 400kHz is supported on the master interface. After I2C master finishes reading sensor data from the externalsensor(s), the received sensor data is then reformatted by the internal processor (eDMP). The reformatted
external sensor data is then moved into FIFO along with other internal sensor data. The external host reads the
FIFO to retrieve both the external sensor data and the internal sensor data.
•
•
•
•
•
•
•

4.11

Independent of the number of external devices on the I 2C bus, the I2C master automatically executes up
to 4 I2C transactions per trigger.
The 4 I2C transactions are fully independent to each other.
Each I2C transaction can be targeting any external I2C device (capped at 2 external I2C devices).
Each I2C transaction can be a read or a write access transaction.
Each I2C transaction can be a burst or a non-burst access transaction.
A read transaction can be from an auto-incremented address location, or from a new address location.
A read operation with a new address location consumes one of the 4 I 2C transactions per trigger.

SELF-TEST

Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for eachmeasurement axis can be activated by means of the gyroscope and accelerometer self-test registers.
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The
output signal is used to observe the self-test response.
The self-test response is defined as follows:
Self-test response = Sensor output with self-test enabled – Sensor output with self-test disabled
When the value of the self-test response is within the specified min/max limits of the product specification, thepart has passed self-test. When the self-test response exceeds the min/max values, the part is deemed to havefailed self-test.

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ICM-45605
4.12

CLOCKING

The ICM-45605 has a flexible clocking scheme, allowing internal clock sources to be used for the internal
synchronous circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and various control
circuits and registers.
Allowable internal sources for generating the internal clock are:a) An internal relaxation oscillatorb) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best available
sourceFor internal sources, the only setting supporting specified performance in all modes is option b). It is
recommended that option b) be used when using internal clock source.

4.13

SENSOR DATA REGISTERS

The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They
are read-only registers and are accessed via the serial interface. Data from these registers may be read anytime.

4.14

INTERRUPTS

Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include theinterrupt pins configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that
can trigger an interrupt are (1) Clock generator locked to new reference oscillator (used when switching clock
sources); (2) new data is available to be read (from the FIFO and Data registers); (3) accelerometer event
interrupts; (4) FIFO watermark; (5) FIFO overflow. The interrupt status can be read from the Interrupt Status
register.

4.15

DIGITAL-OUTPUT TEMPERATURE SENSOR

An on-chip temperature sensor and ADC are used to measure the ICM-45605 die temperature. The readings fromthe ADC can be read from the FIFO or the Sensor Data registers.
Temperature sensor register data TEMP_DATA is updated with new data at max (Accelerometer ODR, Gyroscope
ODR).

4.16

BIAS AND LDOS

The bias and LDO section generates the internal supply and the reference voltages and currents required by the
ICM-45605.

4.17

CHARGE PUMP

An on-chip charge pump generates the high voltage required for the MEMS oscillator.

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ICM-45605
4.18

STANDARD POWER MODES

The following table lists the user-accessible power modes for ICM-45605.
Name
Sleep Mode
Standby Mode
Accelerometer Low-Power Mode
Accelerometer Ultra Low-Power Mode
Gyroscope Low-Power Mode
6-Axis Low-Power Mode
Accelerometer Low-Noise Mode
Gyroscope Low-Noise Mode
6-Axis Low-Noise Mode

Gyro
Off
Drive On
Off
Off
Duty-Cycled
Duty-Cycled
Off
On
On

Table 12. Standard Power Modes for ICM-45605

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Accel
Off
Off
Duty-Cycled
Duty-Cycled
Off
Duty-Cycled
On
Off
On

ICM-45605
5

SIGNAL PATH

The following figure shows a block diagram of the signal path for ICM-45605.

Low-Noise Mode
ADC

Anti-Alias
Filter (AAF)

FSR Selection

Interpolator

LPF & ODR
Selection

Low-Power Mode

SensorRegisters

UI Interface

Average
ACCEL_MODE

Figure 10. ICM-45605 Signal Path

The signal path starts with ADCs for the gyroscope and accelerometer. Low-Noise Mode and Low-Power Mode
options are available for the gyroscope and accelerometer and are selectable using register fields GYRO_MODE
and ACCEL_MODE respectively.
In Low-Noise Mode, the ADC output is sent through an Anti-Alias Filter (AAF). The AAF is an FIR filter with fixedcoefficients (not user configurable). The AAF can be enabled or disabled by the user using GYRO_SRC_CTRL and
ACCEL_SRC_CTRL.
The AAF is followed by an Interpolator. Sensor data can be re-timed using an interpolator when the user applies anexternal clock for higher ODR accuracy or operates the ICM-45605 in I3CSM synchronous mode. The Interpolator
can be enabled or disabled by the user using GYRO_SRC_CTRL and ACCEL_SRC_CTRL.
In Low-Power Mode, the gyroscope and accelerometer ADC outputs are sent through Average filters, with user
configurable average filter setting using register fields GYRO_LP_AVG_SEL and ACCEL_LP_AVG_SEL.
The output of Interpolator in Low-Noise Mode, or Average filter in Low-Power Mode is subject to UI LPF and ODR
selection. The UI LPF BW is set by register bit field GYRO_UI_LPFBW_SEL and ACCEL_UI_LPFBW_SEL for gyroscope
and accelerometer respectively. User selectable ODR is set using register fields GYRO_ODR and ACCEL_ODR. This isfollowed by Full Scale Range (FSR) selection based on user configurable settings for register fields GYRO_UI_FS_SEL
and ACCEL_UI_FS_SEL.

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6

FIFO

The ICM-45605 contains up to 8Kbytes FIFO (default FIFO size is 2Kbytes, user can extend it up to 8Kbytes by
disabling APEX functions) that is accessible via the serial interface. The FIFO configuration register determines
which data is written into the FIFO. Possible choices include gyroscope data, accelerometer data, temperature
readings, and FSYNC input. A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO.
ICM-45605 includes FIFO Compression algorithm that allows storing compressed sensor data in FIFO frames, thus
virtually providing more FIFO space. It allows to store up to 4 times the number of frames with respect to noncompressed data. Frame decompression must be performed on the Host which reads the FIFO. Compression
algorithm uses a hardware lossless algorithm, based on data variation analysis of each axis. Compression ratios x2,
x3, x4 are supported, providing up to 32kByte data storage capability.
A 20-bit data format support is included in one of the FIFO packets structures. When the 20-bit data format isused, the gyroscope data consists of 20-bit of actual data, the accelerometer data consists of 19-bit of actual data
and the LSB is always set to 0. Irrespective of the user-full scale selection, this high-resolution 20-bit data format isalways scaled to ±4000dps (131.1 LSB/dps) for gyroscope and ±32g (16384 LSB/g) for accelerometer.
FIFO packet decimation capability is provided for additional storage optimization. User can configure the FIFO Data
Rate (FDR) to control the decimation rate for writing packets to the FIFO. User must disable sensors when
initializing FDR control value or making changes to it.

6.1

PACKET STRUCTURE

FIFO packets are assembled in different packet sizes based on the enabled sensors. When internal sensors Accel
and Gyro are enabled, the following packets are available:•••

8 bytes packet: Contains Accel-only or Gyro-only data and Temperature data (1 byte)
16 bytes packet: Contains Accel data, Gyro data, Temperature data (1 byte), Timestamp
20 bytes packet: Contains high-resolution Accel data, Gyro data, Temperature data (2 bytes),
Timestamp

The following figure shows packets organization for each format (big endian mode).

Accel-only(8 bytes)
7
0
1
2
3

4
5
6
7

Gyro-only(8 bytes)0

Header
Ax H
Ax L
Ay H
Ay L
Az H
Az L
Temp (1 byte)

7
0
1
2
3

4
5
6
7

Accel+Gyro(16 bytes)
0

Header
Gx H
Gx L
Gy H
Gy L
Gz H
Gz L
Temp (1 byte)

7
0
1
2
3

4
5
6
7
8

9
10
11
12
13

14
15

0

Header
Ax H
Ax L
Ay H
Ay L
Az H
Az L
Gx H
Gx L
Gy H
Gy L
Gz H
Gz L
Temp (1 byte)
Timestamp H
Timestamp L

7
0
1
2
3

4
5
6
7
8

9
10
11
12
13

14
15
16
17
18
19

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Accel+Gyro
High Resolution(20 bytes)
Header
Ax H
Ax L
Ay H
Ay L
Az H
Az L
Gx H
Gx L
Gy H
Gy L
Gz H
Gz L
Temp H
Temp LTimestamp H
Timestamp L
Ax LSBGx LSB
Ay LSB
Gy LSB
Az LSB
Gz LSB0ICM-45605
When external sensors ES0 and ES1 are enabled, the following packets are available:•••

16 bytes packet: Contains 6/9 bytes ES0-only or ES1-only data
20 bytes frame: Contains 6/9 bytes ES0 data and ES1 data
32 bytes frame: Contains Accel data, Gyro data, 6/9 bytes ES0 data, ES1 data, Temperature data
(1 byte), Timestamp. The 32 bytes format is always selected when at least one internal sensor and
one external sensor are enabled

The following figure shows packets organization for each format (big endian mode).
6b Ext Sensor 0(16 bytes)
7
0
1
2

3
4

5
6

7
8

9
10
11
12
13

14
15

9b Ext Sensor 0(16 bytes)
0

7

HeaderHeader 2
ES0_B0ES0_B1
ES0_B2
ES0_B3
ES0_B4
ES0_B5Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

0
1
2

3
4

5
6

7
8

9
10
11
12
13

14
15

6b Ext Sensor 0 +Ext Sensor 1(20 bytes)

Ext Sensor 1(16 bytes)
0

HeaderHeader 2
ES0_B0ES0_B1
ES0_B2
ES0_B3
ES0_B4
ES0_B5
ES0_B6
ES0_B7
ES0_B8Reserved
Reserved
Reserved
Reserved
Reserved

7
0
1
2

3
4

5
6

7
8

9
10
11
12
13

14
15

0

HeaderHeader 2
ES1_B0ES1_B1ES1_B2
ES1_B3
ES1_B4
ES1_B5Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

7
0
1
2

3
4

5
6

7
8

9
10
11
12
13

14
15

16
17

18
19

0

HeaderHeader 2
ES0_B0ES0_B1
ES0_B2
ES0_B3
ES0_B4
ES0_B5Reserved
Reserved
Reserved
ES1_B0ES1_B1ES1_B2
ES1_B3
ES1_B4
ES1_B5Reserved
Reserved
Reserved

Accel + Gyro +6b Ext Sensor 0 +Ext Sensor 1(32 bytes)

9b Ext Sensor 0 +Ext Sensor 1(20 bytes)

7
0
1
2

3
4

5
6

7
8

9
10
11
12
13

14
15

16
17

18
19

0

HeaderHeader 2
ES0_B0ES0_B1
ES0_B2
ES0_B3
ES0_B4
ES0_B5
ES0_B6
ES0_B7
ES0_B8
ES1_B0ES1_B1ES1_B2
ES1_B3
ES1_B4
ES1_B5Reserved
Reserved
Reserved

7
0
1
2

3
4

5
6

7
8

9
10
11
12
13

14
15

16
17

18
19

20
21
22
23
24

25
26

27
28

29
30

31

6.2

Accel + Gyro +9b Ext Sensor 0 +Ext Sensor 1(32 bytes)

0

HeaderHeader 2
Ax H
Ax L
Ay H
Ay L
Az H
Az L
Gx H
Gx L
Gy H
Gy L
Gz H
Gz L
ES0_B0ES0_B1
ES0_B2
ES0_B3
ES0_B4
ES0_B5Reserved
Reserved
Reserved
ES1_B0ES1_B1ES1_B2
ES1_B3
ES1_B4
ES1_B5
Temp (1 byte)
Timestamp H
Timestamp L

7
0
1
2

3
4

5
6

7
8

9
10
11
12
13

14
15

16
17

18
19

20
21
22
23
24

25
26

27
28

29
30

31

0

HeaderHeader 2
Ax H
Ax L
Ay H
Ay L
Az H
Az L
Gx H
Gx L
Gy H
Gy L
Gz H
Gz L
ES0_B0ES0_B1
ES0_B2
ES0_B3
ES0_B4
ES0_B5
ES0_B6
ES0_B7
ES0_B8
ES1_B0ES1_B1ES1_B2
ES1_B3
ES1_B4
ES1_B5
Temp (1 byte)
Timestamp H
Timestamp L

FIFO HEADER

The following table shows the structure of the first byte of the FIFO header.
Bit Field

Item

7

EXT_HEADER

6ACCEL_EN

5

GYRO_EN

4

HIRES_EN3

TMST_FIELD_EN

2

FSYNC_TAG_EN

Description
1: FIFO header length is extended to 2 bytes. The second byte is used forcompressed frame decoding fields or external sensors information
0: FIFO header length is 1 byte
1: Accel is enabled or high resolution is enabled
0: Accel is not enabled and high resolution is not enabled
1: Gyro is enabled or high resolution is enabled
0: Gyro is not enabled and high resolution is not enabled
1: High-resolution is enabled (20-bytes format)
0: High-resolution is not enabled
1: Timestamp field is included in the packet. This requires that: a) high-resolution isenabled, or b) both Accel and Gyro are enabled, or c) either Accel or Gyro areenabled, and either ES0 or ES1 are enabled
The timestamp field contains the timestamp value or FSYNC-ODR delay depending
on configuration
0: Timestamp field is not included in the packet
1: FSYNC is triggered and the Timestamp field contains the FSYNC-ODR delay
0: FSYNC is not triggered and the Timestamp field does not contain the FSYNC-ODR
delay

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ICM-45605
1

ACCEL_ODR

0

GYRO_ODR

1: The ODR for accel is different for this accel data packet compared to the previous
accel packet
0: The ODR for accel is the same as the previous packet with accel
1: The ODR for gyro is different for this gyro data packet compared to the previous
gyro packet
0: The ODR for gyro is the same as the previous packet with gyro

When External Sensors are enabled, an additional header byte is used. The second byte of the header is described
below.
Bit Field
7:5

Item
-

4

ES0_6b_9b3

ES1_VLD

2

ES0_VLD1

ES1_EN0

ES0_EN

Description
Reserved
Indicates how many bytes sensor ES0 provides
1: Sensor ES0 provides 9 bytes data
0: Sensor ES0 provides 6 bytes data
1: ES1 data is valid
0: ES1 data is not valid
1: ES0 data is valid
0: ES0 data is not valid
1: Sensor ES1 is enabled
0: Sensor ES1 is not enabled
1: Sensor ES0 is enabled
0: Sensor ES0 is not enabled

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ICM-45605
7

PROGRAMMABLE INTERRUPTS

The ICM-45605 has a programmable interrupt system that can generate an interrupt signal on the INT pins. Status
flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually. There are twointerrupt outputs. Any interrupt may be mapped to either interrupt pin as explained in the register section. The
following configuration options are available for the interrupts:•••

INT1 and INT2 can be push-pull or open drain
Level or pulse mode
Active high or active low

Additionally, ICM-45605 includes In-band Interrupt (IBI) support for the I3CSM interface.

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ICM-45605
8

EDMP

The on-chip Enhanced Digital Motion Processor (EDMP) is designed for motion processing of next-gen sensor
products. It enables ultra-low power run-time and offloads computation of motion processing and sensor fusion
algorithms from the host processor. It enables the host system to execute custom algorithms and issue softwareinterrupts to the external environment. The EDMP can be deployed in the system to minimize system level power,
simplify the software architecture, and save valuable MIPS on the host processor. The EDMP implements a motion
sensor optimized custom ISA with special motion processing instructions.

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ICM-45605
9

APEX MOTION FUNCTIONSThe APEX (Advanced Pedometer and Event Detection – neXt gen) features of ICM-45605 consist of:
•
•
•
•
•
•
•
•
•

Pedometer: Tracks Step Count, also issues Step Detect interrupt.
Tilt Detection: Issues an interrupt when the Tilt angle exceeds 35 for more than a programmable time.
Raise to Wake/Sleep: Gesture detection for wake and sleep events. Interrupt is issued when either of these
two events are detected.
Single Tap / Double Tap Detection: Issues an interrupt when a tap is detected, along with the tap type.
Wake on Motion: Detects motion when accelerometer data exceeds a programmable threshold. This
motion event can be used to enable chip operation from sleep mode.
Freefall Detection: Triggers an interrupt when device freefall is detected and outputs freefall duration.
Significant Motion Detection: Detects significant motion based on accelerometer data.
Low-G Detection: Triggers an interrupt when absolute value of accelerometer combined axis falls below a
programmable threshold and stays below the threshold for a programmable time.
High-G Detection: Triggers an interrupt when absolute value of accelerometer goes above a
programmable threshold and stays above the threshold for a programmable time.

These functions are run as software on EDMP.

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ICM-45605
10 DIGITAL INTERFACEI3CSM, I2C AND SPI SERIAL INTERFACES

10.1

The internal registers and memory of the ICM-45605 can be accessed using I3CSM at 12.5 MHz (data rates up to
12.5 Mbps in SDR mode, 25 Mbps in DDR mode), I2C at 1 MHz or SPI at 24 MHz. SPI operates in 3-wire or 4-wire
mode. Pin assignments for serial interfaces are described in section 4.

I3CSM INTERFACE

10.2

I3CSM is a new 2-wire digital interface comprised of the signals serial data (SDA) and serial clock (SCLK). I3C SM isintended to improve upon the I2C interface, while preserving backward compatibility. The I3CSM capability of thisdevice is compliant with Version 1.1.1 of the MIPI Alliance Specification for I3CSM. Please refer to the corresponding
MIPI I3CSM specification for I3CSM timing information for this device.
I3CSM carries the advantages of I²C in simplicity, low pin count, easy board design, and multi-drop (vs. point topoint), but provides the higher data rates, simpler pads, and lower power of SPI. I3C SM adds higher throughput fora given frequency, in-band interrupts (from slave to master), dynamic addressing.
ICM-45605 supports the following features of I3CSM:
•
•
•
•
•
•
•

SDR data rate up to 12.5 Mbps
DDR data rate up to 25 Mbps
Dynamic address allocation
In-band Interrupt (IBI) support
Support for asynchronous timing control mode 0
Error detection (CRC and/or Parity)
Common Command Code (CCC)

The ICM-45605 always operates as an I3CSM slave device when communicating to the system processor, which thus
acts as the I3CSM master. I3CSM master controls an active pullup resistance on SDA, which it can enable and disable.
The pullup resistance may be a board level resistor controlled by a pin, or it may be internal to the I3C SM master.
The following table shows I3CSM Common Command Code (CCC) commands supported by the device.

CCC Description

Required or Optional
per I3C v1.0

Supported by
ICM-45605 HostInterface

1

ENEC, broadcast mode. (Enable Events).

RequiredYes

2

DISEC, broadcast mode. (Disable Events)

Required

Yes

3

ENTAS0, broadcast mode. (Enter Activity State 0)

Required

Yes

4

ENTAS1, broadcast mode. (Enter Activity State 1)

Optional

No

5

ENTAS2, broadcast mode. (Enter Activity State 0)

Optional

No

6

ENTAS3, broadcast mode. (Enter Activity State 0)

Optional

No

7

RSTDAA, broadcast mode. (Reset dynamic address
assignment).

RequiredYes

8

ENTDAA, broadcast mode. (Enter dynamic address
assignment).

RequiredYes

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ICM-45605
9

DEFSLVS, broadcast mode. (Define list of slaves).

Optional

No

10

SETMWL, broadcast mode. (Set Max Write Length).

Required

Yes

11

SETMRL, broadcast mode. (Set Max Read Length).

RequiredYes

12

ENTTM, broadcast mode. (Enter Test Mode).

Optional

No

13

ENTHDR0, broadcast mode. (Enter HDR DDR mode)

Optional

Yes

14

ENTHDR1, broadcast mode. (Enter HDR TSP mode)

Optional

No

15

ENTHDR2, broadcast mode. (Enter HDR TSL mode)

Optional

No

16

SETXTIME, broadcast mode. (Exchange Timing Information).
16.1

Defining byte = 0x7F (ST)

Optional

Yes

16.2

Defining byte = 0xBF (DT)

Optional

Yes

16.3

Defining byte = 0xDF (Enter Async Mode 0)

Optional

Yes

16.4

Defining byte = 0xEF (Enter Async Mode 1)

Optional

No

16.5

Defining byte = 0xF7 (Enter Async Mode 2)

Optional

No

16.6

Defining byte = 0xFB (Enter Async Mode 3)

Optional

No

16.7

Defining byte = 0xFD (Async Trigger for Async
Mode 3).

Optional

No

16.8

Defining byte = 0x3F (TPH)

Optional

Yes

16.9

Defining byte = 0x9f (TU)

Optional

Yes

16.10

Defining byte = 0x8F (ODR)

Optional

Yes

17

ENEC, direct mode. (Enable Events).

Required

Yes

18

DISEC, direct mode. (Disable Events).

Required

Yes

19

ENTAS0, direct mode. (Enter Activity State 0).

Required

Yes

20

ENTAS1, direct mode. (Enter Activity State 1).

Optional

No

21

ENTAS2, direct mode. (Enter Activity State 2).

Optional

No

22

ENTAS3, direct mode. (Enter Activity State 3).
RSTDAA, direct mode. (Reset dynamic address
assignment).

Optional

No

RequiredYes

Optional

Yes

23

24

SETDASA, direct mode. (Set Dynamic address from static
address).

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ICM-45605
25

SETNEWDA, direct mode. (Set new dynamic address)

Required

Yes

26

SETMWL, direct mode. (Set Max Write Length).

Required / Conditional

Yes

27

SETMRL, direct mode. (Set Max Read length).

Required / Conditional

Yes

28

GETMWL, direct mode. (Get Max write length).

Required / Conditional

Yes

29

GETMRL, direct mode. (Get Max Read length).

Required / Conditional

Yes

30

GETPID, direct mode. (Get provisional ID).

RequiredYes

31

GETBCR, direct mode. (Get Bus Characteristics Register).

Required

Yes

32

GETDCR, direct mode. (Get Device Characteristics
Register).

RequiredYes

33

GETSTATUS, direct mode. (Get Device Status).

Required

Yes

34

GETACCMST, direct mode. (Get Accept Mastership).

Optional

No

35

SETBRGTGT, direct mode. (Set Bridge Targets).

Optional

No

36

GETMXDS, direct mod. (Get Max Data Speed).

Optional

Yes

37

GETHDRCAP, direct mode. (Get HDR capability).

Optional

Yes

38

SETXTIME, direct mode. (Set Exchange Timing information).
38.1

Defining byte = 0x7F (ST)

Optional

Yes

38.2

Defining byte = 0xBF (DT)

Optional

Yes

38.3

Defining byte = 0xDF (Enter Async Mode 0)

Optional

Yes

38.4

Defining byte = 0xEF (Enter Async Mode 1)

OptionalNo

38.5

Defining byte = 0xF7 (Enter Async Mode 2)

OptionalNo

38.6

Defining byte = 0xFB (Enter Async Mode 3)

Optional

No

38.7

Defining byte = 0xFD (Async Trigger for Async
Mode 3).

Optional

No

38.8

Defining byte = 0x3F (TPH)

Optional

Yes

38.9

Defining byte = 0x9f (TU)

Optional

Yes

38.10

Defining byte = 0x8F (ODR)

Optional

Yes

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ICM-45605
39

GETXTIME, direct mode. (Get Exchange Timing
Information).

Optional

Yes

Table 13. I3CSM CCC Commands

10.3

I2C INTERFACEI2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are
open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can be a master or aslave. The master device puts the slave address on the bus, and the slave device with the matching address
acknowledges the master.
The ICM-45605 always operates as a slave device when communicating to the system processor, which thus acts as
the master. SDA and SCL lines typically need pull-up resistors to VDDIO. The maximum bus speed is 1 MHz.
The slave address of the ICM-45605 is b110100X, which is 7 bits long. The LSB bit of the 7-bit address is determinedby the logic level on pin AP_AD0. This allows two ICM-45605s to be connected to the same I2C bus. When used inthis configuration, the address of one of the devices should be b1101000 (pin AP_AD0 is logic low) and the addressof the other should be b1101001 (pin AP_AD0 is logic high).

10.4

I2C MASTER INTERFACEI2C master is compliant with the I2C standard-Mode (max 100kbps), and I2C Fast-Mode (max 400kbps). It supports
8-bit I2C static address. It does not support multi-master on the I2C bus. Clock-stretching by external I2C devices is
not supported.

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ICM-45605
10.5

SPI INTERFACEThe ICM-45605 supports 3-wire or 4-wire SPI for the host interface. The ICM-45605 always operates as a Slave
device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO), the Serial Data Input(SDI), and the Serial Data IO (SDIO) are shared among the Slave devices. Each SPI slave device requires its own Chip
Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is activeat a time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected slave devices
are held high, causing their SDO lines to remain in a high-impedance (high-z) state so that they do not interferewith any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. The maximum frequency of SCLK is 24 MHz (it is 20MHz at VDDIO 1.2V)
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first
byte contains the Register Address, and the following byte(s) contain(s) the SPI data. The first bit of thefirst byte contains the Read/Write bit and indicates the Read (1) operation. The following 7 bits containthe Register Address. In cases of multiple-byte Reads, data is two or more bytes:
Register Address format
MSB
R/W

A6

A5

A4

A3

A2

A1

LSB
A0

D4

D3

D2

D1

LSB
D0

SPI Data format
MSB
D7
6.

D6

D5

Supports Single or Burst Read/Writes.
SCLK
SDIO

SPI Master

CS1

nCS

SPI Slave 1

CS2

SCLK
SDIO

SPI Slave 2

nCS

Figure 11. Typical SPI Master/Slave Configuration

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ICM-45605
11 ASSEMBLY
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS)
devices packaged in LGA package.

11.1

ORIENTATION OF AXES

The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1
identifier (•) in the figure.
+Z

+Y

+Z

+Y

+X

+X

Figure 12. Orientation of Axes of Sensitivity and Polarity of Rotation

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ICM-45605
11.2

PACKAGE DIMENSIONS

14 Lead LGA (2.5x3x0.81) mm NiAu pad finish

Page 49 of 191
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ICM-45605
DIMENSIONS IN MILLIMETERS
Total Thickness
Substrate Thickness
Mold Thickness
Body Size

SYMBOLS
A
A1
A2

MIN
0.76

D
E

NOM
0.81
0.105
0.7

MAX
0.86
REF
REF

2.5

BSC

3

BSC

Lead Width

W

0.2

0.25

0.3

Lead Length

L
e
n

0.425

0.475
0.5
14

0.525
BSC

Lead Pitch
Lead Count
Edge Ball Center to Center
Body Center to Contact Ball
Package Edge Tolerance
Mold Flatness
Coplanarity

D1

1.5

BSC

E1
SD

1
0.25

BSC
BSC

SE

---

BSC

aaa
bbb
ddd

0.1
0.2
0.08

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ICM-45605
12 DEVICE PACKAGE IN TAPE AND REEL
ICM-45605 devices are packaged in the tape and reel as shown in the figures below.

Figure 13. ICM-45605 Device Package in Tape and Reel

Figure 14. Tape Dimensions with ICM-45605 Device Package

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ICM-45605
13 PART NUMBER PACKAGE MARKINGThe part number package marking for ICM-45605 devices is summarized below:
Part Number
ICM-45605

Part Number Package Marking
I4565

TOP VIEWPart Number
Lot Traceability CodeI4565
XXXXXX
YYWW

Y Y = Year CodeW W = Work Week

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ICM-45605
14 INDIRECT REGISTER ACCESS
14.1

HOST INDIRECT ACCESS REGISTER (IREG)

An IREG is a register or a memory storage element that is not addressed directly by a 7-bit address. IREGs can only
be addressed using an internal 16-bit address. Indirect register access procedures described in this section must be
used to access all IREGs.
The host configures the internal 16-bit address by programming following registers:{ireg_addr_15_8[7:0], ireg_addr_7_0[7:0]}.

14.2
1.
2.
3.

14.3

GENERAL RULES FOR ACCESSING IREG
Burst-write and burst-read operations are not supported when accessing IREGs from the host.
Reading of an IREG is done on a read-pre-fetch basis (details in IREG READ section below).
A minimum wait time (refer to section MINIMUM WAIT TIME GAP below for details) is required between
two consecutive read/write access to an IREG.

MINIMUM WAIT TIME-GAP

The minimum time gap between two consecutive IREG accesses for various IREG components is 4µs.

14.4IREG WRITE

Procedure for writing to an IREG.
1.

2.
3.
4.
5.
6.
7.

The host specifies the destination address of an IREG by programming IREG_ADDR_7_0,
IREG_ADDR_15_8.
a. If host wants to access a register in IMEM_SRAM, it should add base address 0x0000 to theaddress of that register shown in the IMEM_SRAM registers section, and then use that resulting
value in registers IREG_ADDR_7_0, IREG_ADDR_15_8.
b. If host wants to access a register in IPREG_BAR, it should add base address 0xA000 to the addressof that register shown in the IPREG_BAR registers section, and then use that resulting value inregisters IREG_ADDR_7_0, IREG_ADDR_15_8.
c. If host wants to access a register in IPREG_SYS1, it should add base address 0xA400 to theaddress of that register shown in the IPREG_SYS1 registers section, and then use that resulting
value in registers IREG_ADDR_7_0, IREG_ADDR_15_8.
d. If host wants to access a register in IPREG_SYS2, it should add base address 0xA500 to theaddress of that register shown in the IPREG_SYS2 registers section, and then use that resulting
value in registers IREG_ADDR_7_0, IREG_ADDR_15_8.
e. If host wants to access a register in IPREG_TOP1, it should add base address 0xA200 to theaddress of that register shown in the IPREG_TOP1 registers section, and then use that resulting
value in registers IREG_ADDR_7_0, IREG_ADDR_15_8.
The host programs the write data to the IREG_DATA register.
The above programming steps must be performed in a single burst-write transaction to prevent an unintended read-pre-fetch operation.
After the IREG_DATA register is written, an internal operation is triggered to pass the contents from the
IREG_DATA register to a register pointed by {IREG_ADDR_7_0, IREG_ADDR_15_8}.
After the contents from the IREG_DATA register is written to the selected register, the internal 16-bit
address is auto-incremented.
After a minimum wait time-gap, the host can write to the IREG_DATA register again, which is effectively
writing to the register pointed by the post-auto-incremented address.
Or, after a minimum wait time-gap, the host can program a new destination address for the next write
operation.

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ICM-45605
14.5

IREG READ

Procedure for reading from an IREG.
1.

2.
3.
4.
5.

6.

The host specifies the destination address of an IREG by programming IREG_ADDR_7_0,
IREG_ADDR_15_8.
a. If host wants to access a register in IMEM_SRAM, it should add base address 0x0000 to theaddress of that register shown in the IMEM_SRAM registers section, and then use that resulting
value in registers IREG_ADDR_7_0, IREG_ADDR_15_8.
b. If host wants to access a register in IPREG_BAR, it should add base address 0xA000 to the addressof that register shown in the IPREG_BAR registers section, and then use that resulting value inregisters IREG_ADDR_7_0, IREG_ADDR_15_8.
c. If host wants to access a register in IPREG_SYS1, it should add base address 0xA400 to theaddress of that register shown in the IPREG_SYS1 registers section, and then use that resulting
value in registers IREG_ADDR_7_0, IREG_ADDR_15_8.
d. If host wants to access a register in IPREG_SYS2, it should add base address 0xA500 to theaddress of that register shown in the IPREG_SYS2 registers section, and then use that resulting
value in registers IREG_ADDR_7_0, IREG_ADDR_15_8.
e. If host wants to access a register in IPREG_TOP1, it should add base address 0xA200 to theaddress of that register shown in the IPREG_TOP1 registers section, and then use that resulting
value in registers IREG_ADDR_7_0, IREG_ADDR_15_8.
Upon the CSB=1 (SPI) or STOP (I2C) after the above programming, an internal read-pre-fetch operation istriggered.
The internal read-pre-fetch operation returns the desired data, which is saved to the IREG_DATA register.
After a minimum wait time-gap, the host reads the IREG_DATA register to retrieve the read-data.
After the host reads the IREG_DATA register, the internal 16-bit address is auto-incremented, and anotherinternal read-pre-fetch is automatically triggered, to fetch data from the IREG register pointed to by the
post-auto-incremented address.
After a minimum wait time-gap, the host can either read the IREG_DATA register to get the read-datafrom the next address location, or it can program a new read address.

Page 54 of 191
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ICM-45605
15 DEVICE CONFIGURATION FOR DATA ENDIANNESS
By default the device data endianness is Little Endian, for data in Sensor Data Registers and FIFO, and for FIFOCount. User must set register field SREG_DATA_ENDIAN_SEL in register SREG_CTRL to 1, to enable Big Endian data
format for data in Sensor Data Registers and FIFO, and for FIFO Count.
Data descriptions in the register map for Sensor Data Registers, FIFO data, and FIFO Count are for the commonlyused Big Endian format.

Page 55 of 191
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ICM-45605
16 REGISTER MAP
This section lists the register map for the ICM-45605, for user bank 0, IMEM_SRAM, IPREG_BAR, IPREG_TOP1,
IPREG_SYS1, IPREG_SYS2.
Please refer to the procedure in Section 14 for configuring device data endianness before using the register map.

16.1

USER BANK 0 REGISTER MAP

Addr
(Hex)

Addr
(Dec.)

Register Name

SerialI/F

00

00

ACCEL_DATA_X1_UI

SYNCR

01

01

ACCEL_DATA_X0_UISYNCRACCEL_DATA_X_UI[7:0]02

02

ACCEL_DATA_Y1_UISYNCRACCEL_DATA_Y_UI[15:8]

03

03

ACCEL_DATA_Y0_UISYNCRACCEL_DATA_Y_UI[7:0]0404

ACCEL_DATA_Z1_UISYNCRACCEL_DATA_Z_UI[15:8]

05

05

ACCEL_DATA_Z0_UISYNCRACCEL_DATA_Z_UI[7:0]0606

GYRO_DATA_X1_UI

SYNCR

GYRO _DATA_X_UI[15:8]

07

07

GYRO _DATA_X0_UI

SYNCR

GYRO _DATA_X_UI[7:0]0808

GYRO _DATA_Y1_UI

SYNCR

GYRO _DATA_Y_UI[15:8]

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

ACCEL_DATA_X_UI[15:8]

09

09

GYRO _DATA_Y0_UI

SYNCR

GYRO _DATA_Y_UI[7:0]0A

10

GYRO _DATA_Z1_UI

SYNCR

GYRO_DATA_Z_UI[15:8]

0B

11

GYRO _DATA_Z0_UI

SYNCR

GYRO_DATA_Z_UI[7:0]0C

12TEMP_DATA1_UI

SYNCR

TEMP_DATA_UI[15:8]

0D

13

TEMP_DATA0_UI

SYNCR

TEMP_DATA_UI[7:0]0E

14TMST_FSYNCH

SYNCR

TMST_FSYNC_DATA_UI[15:8]

0F

15TMST_FSYNCL

SYNCR

10

16

PWR_MGMT0

R/W

TMST_FSYNC_DATA_UI[7:0]12

18

FIFO_COUNT_0

R

FIFO_DATA_CNT[15:8]

13

19

FIFO_COUNT_1

R

FIFO_DATA_CNT[7:0]

14

20

FIFO_DATAR-GYRO_MODE

ACCEL_MODE

FIFO_DATA

16

22

INT1_CONFIG0

R/W

INT1_STATUS_EN_RESET_DONE

INT1_STATUS_EN_AUX1_A
GC_RDY

INT1_STATUS_EN_AP_AGC_RDY

INT1_STATUS_EN_AP_FSY
NC

INT1_STATUS_EN_AUX1_D
RDY

INT1_STATUS_EN_DRDY

INT1_STATUS_EN_FIFO_TH
S

INT1_STATUS_EN_FIFO_FU
LL

17

23

INT1_CONFIG1

R/W-

INT1_STATUS_EN_APEX_E
VENT

INT1_STATUS_EN_I2CM_D
ONE

INT1_STATUS_EN_I3C_PR
OTOCOL_ERR

INT1_STATUS_EN_WOM_Z

INT1_STATUS_EN_WOM_Y

INT1_STATUS_EN_WOM_X

INT1_STATUS_EN_PLL_RD
Y

18

24

INT1_CONFIG2

R/W

INT1_DRIVE

INT1_MODE

INT1_POLARI
TY

19

25

INT1_STATUS0

R/C

INT1_STATUS_RESET_DON
E

INT1_STATUS_AUX1_AGC_
RDY

INT1_STATUS_AP_AGC_RD
Y

INT1_STATUS_AP_FSYNC

INT1_STATUS_AUX1_DRDY

INT1_STATUS_DRDY

INT1_STATUS_FIFO_THS

INT1_STATUS_FIFO_FULL

1A

26

INT1_STATUS1

R/C-

INT1_STATUS_APEX_EVEN
T

INT1_STATUS_I2CM_DONE

INT1_STATUS_I3C_PROTO
COL_ERR

INT1_STATUS_WOM_Z

INT1_STATUS_WOM_Y

INT1_STATUS_WOM_X

1B

27

ACCEL_CONFIG0

R/W

-

1C

28

GYRO_CONFIG0

R/W

1D

29

FIFO_CONFIG0

R/W

1E

30

FIFO_CONFIG1_0

R/W

FIFO_WM_TH[7:0]

1F

31

FIFO_CONFIG1_1

R/W

FIFO_WM_TH[15:8]

20

32

FIFO_CONFIG2R/W-

ACCEL_UI_FS_SEL

GYRO_ODRFIFO_MODEFIFO_DEPTH-

FIFO_WR_W
M_GT_THFIFO_ES1_EN

FIFO_HIRES_EN

FIFO_FLUSH

33

FIFO_CONFIG3

R/W

-

22

34

FIFO_CONFIG4

R/W

-

23

35

TMST_WOM_CONFIG

R/W-

FIFO_ES0_EN

FIFO_COMP_NC_FLOW_CFG
TMST_DELTA_EN

TMST_RESOLPage 56 of 191
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ACCEL_ODR

GYRO_UI_FS_SEL

21

INT1_STATUS_PLL_RDY

WOM_EN

WOM_MODEFIFO_GYRO_EN

FIFO_ACCEL_EN

FIFO_IF_EN

FIFO_COMP_EN

FIFO_TMST_F
SYNC_ENFIFO_ES0_6B_9B

WOM_INT_MODE

WOM_INT_DUR

ICM-45605
Addr
(Hex)

Addr
(Dec.)

Register Name

SerialI/F

24

36

FSYNC_CONFIG0

R/W

27

39

DMP_EXT_SEN_ODR_CFG

R/W

28

40

ODR_DECIMATE_CONFIG

R/W

29

41

EDMP_APEX_EN0

R/W

2A

42

EDMP_APEX_EN1

R/W

2B

43

APEX_BUFFER_MGMT

R/W

Bit7

Bit6

Bit5

Bit4

Bit3

-

-

EXT_SENSOR_EN

SMD_ENR2W_ENPEDO_ENFEATURE3_E
N

FF_DURATION_HOST_RPTR

R/W

2D

45

INTF_CONFIG1_OVRD

R/W

2F

47

IOC_PAD_SCENARIO

R

30

48

IOC_PAD_SCENARIO_AUX_O
VRD

R/W

32

50

DRIVE_CONFIG0

R/W

33

51

DRIVE_CONFIG1

R/W

34

52

DRIVE_CONFIG2

R/W

35

53

REG_MISC1

R/W

39

57

INT_APEX_CONFIG0

R/W

3A

58

INT_APEX_CONFIG1

R/W

3B

59

INT_APEX_STATUS0

R/C

3C

60

INT_APEX_STATUS1

R/C

56

86

INT2_CONFIG0

R/W

INT2_STATUS_EN_RESET_DONE

INT2_STATUS_EN_AUX1_A
GC_RDY57

87

INT2_CONFIG1

R/W-

INT2_STATUS_EN_APEX_E
VENT

58

88

INT2_CONFIG2

R/W

59

89

INT2_STATUS0

R/C

INT2_STATUS_RESET_DON
E

INT2_STATUS_AUX1_AGC_
RDY

INT2_STATUS_AP_AGC_RD
Y

INT2_STATUS_AP_FSYNC

5A

90

INT2_STATUS1

R/C-

INT1_STATUS_APEX_EVEN
T

INT1_STATUS_I2CM_DONE

INT1_STATUS_I3C_PROTO
COL_ERR

72

114

WHO_AM_I

R
R/W

AP_SPI_34_
MODE_OVRD_VALAP_SPI_34_
MODE_OVRD
AUX1_MODE_OVRD-

INT_STATUS_
FF_DET

AUX1_ENABL
E
AUX1_ENABL
E_OVRD_VAL-

PADS_SLEW
OSC_ID_OVRD
INT_STATUS_
MASK_PIN_STEP_CNT_OVFL

INT_STATUS_
MASK_PIN_TI
LT_DET

INT_STATUS_
MASK_PIN_L
OW_G_DET

INT_STATUS_
MASK_PIN_H
IGH_G_DET

INT_STATUS_
MASK_PIN_T
AP_DET

INT_STATUS_
MASK_PIN_S
A_DONE-INT_STATUS_
MASK_PIN_S
ELFTEST_DO
NE

INT_STATUS_
MASK_PIN_S
MD_DET

INT_STATUS_
MASK_PIN_R
2W_SLEEP_D
ET

INT_STATUS_
STEP_CNT_O
VFL

INT_STATUS_
TILT_DET

INT_STATUS_
LOW_G_DET

INT_STATUS_HIGH_G_DET

INT_STATUS_TAP_DET

INT_STATUS_
SA_DONE-INT_STATUS_SELFTEST_DO
NE

INT_STATUS_
SMD_DET

INT_STATUS_
R2W_SLEEP_
DET

INT2_STATUS_EN_AP_AGC_RDY

INT2_STATUS_EN_AP_FSY
NC

INT2_STATUS_EN_AUX1_D
RDY

INT2_STATUS_EN_DRDY

INT2_STATUS_EN_FIFO_TH
S

INT2_STATUS_EN_FIFO_FU
LL

INT2_STATUS_EN_I2CM_D
ONE

INT2_STATUS_EN_I3C_PR
OTOCOL_ERR

INT2_STATUS_EN_WOM_Z

INT2_STATUS_EN_WOM_Y

INT2_STATUS_EN_WOM_X

INT2_STATUS_EN_PLL_RD
Y

INT2_DRIVE

INT2_MODE

INT2_POLARI
TY

INT2_STATUS_AUX1_DRDY

INT2_STATUS_DRDY

INT2_STATUS_FIFO_THS

INT2_STATUS_FIFO_FULL

INT1_STATUS_WOM_Z

INT1_STATUS_WOM_Y

INT1_STATUS_WOM_XINT_STATUS_
MASK_PIN_S
TEP_DET-

INT_STATUS_
R2W_WAKE_
DET

AP_SPI_MOD
E_OVRD_VAL

PADS_I3C_SDR_SLEW-

INT_STATUS_
MASK_PIN_F
F_DET

AP_SPI_MOD
E_OVRD

PADS_SPI_SLEW

PADS_I3C_DDR_SLEW

INT_STATUS_
MASK_PIN_R
2W_WAKE_D
ET

AP_SPI_MOD
E

AUX1_ENABL
E_OVRD

AUX1_ENABLE_OVRD_VAL

PADS_I2C_SLEW-

AP_SPI_34_
MODE

AUX1_MODE-

SOFT_HARD_
IRON_CORR_
EN

STEP_COUNT_EDMP_WPTR--

TAP_EN
INIT_EN

STEP_COUNT_HOST_RPTR

INT_STATUS_
STEP_DET--

INT1_STATUS_PLL_RDY

WHOAMI-

EDMP_ON_D
EMAND_ENTESTOPENAB
LE

-

7C

124

IREG_ADDR_15_8

R/W

IREG_ADDR_15_8

7D

125

IREG_ADDR_7_0

R/W

IREG_ADDR_7_0

7E

126

IREG_DATA

R/W

7F

127

REG_MISC2R/W

IREG_DATA-

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POWER_SAV
E_EN

FF_DURATION_EDMP_WPTR

INTF_CONFIG0

REG_HOST_MSG

TILT_EN-

44

115

APEX_ODRACCEL_FIFO_ODR_DEC

FF_EN

EDMP_ENAB
LE

Bit0

AP_FSYNC_SEL

GYRO_FIFO_ODR_DEC

-

Bit1

EXT_ODR

2C

73

Bit2

AP_FSYNC_FL
AG_CLEAR_S
EL

SOFT_RST

IREG_DONEICM-45605
16.2

USER BANK IMEM_SRAM REGISTER MAP

Addr
(Hex)

Addr
(Dec.)

Register Name

SerialI/F

00

00

IMEM_SRAM_REG_0

R/W

GYRO_X_STR_FT[7:0]0101IMEM_SRAM_REG_1

R/W

GYRO_X_STR_FT[15:8]

02

02

IMEM_SRAM_REG_2

R/W

GYRO_Y_STR_FT[7:0]0303

IMEM_SRAM_REG_3

R/W

GYRO_Y_STR_FT[15:8]

04

04

IMEM_SRAM_REG_4

R/W

GYRO_Z_STR_FT[7:0]0505

IMEM_SRAM_REG_5

R/W

GYRO_Z_STR_FT[15:8]

06

06

IMEM_SRAM_REG_6

R/W

07

07

IMEM_SRAM_REG_7

R/W

08

08

IMEM_SRAM_REG_8

R/W

09

09

IMEM_SRAM_REG_9

R/W

0A

10

IMEM_SRAM_REG_10

R/W

0B

11

IMEM_SRAM_REG_11

R/W

38

56

IMEM_SRAM_REG_56

R/W

39

57

IMEM_SRAM_REG_57

R/W

40

64

IMEM_SRAM_REG_64

R/W

Bit7

Bit6

Bit5

Bit4

Bit3

Bit1

Bit0

GYRO_X_CMOS_GAIN_FT[7:0]-

GYRO_X_CMOS_GAIN_FT[11:8]
GYRO_Y_CMOS_GAIN_FT[7:0]-

GYRO_Y_CMOS_GAIN_FT[11:8]
GYRO_Z_CMOS_GAIN_FT[7:0]-

GYRO_Z_CMOS_GAIN_FT[11:8]

ST_AVG_TIM
E[0]-ST_GYRO_EN

ST_GYRO_LIMIT

ST_ACCEL_LIMIT

ST_ACCEL_E
N

STC_INIT_EN

ST_AVG_TIME[2:1]

ST_DEBUG_EN

44

68

IMEM_SRAM_REG_68

R

5C

92

IMEM_SRAM_REG_92

R/W

60

96

IMEM_SRAM_REG_96

R/W

STC_GAIN_GX[7:0]6197IMEM_SRAM_REG_97

R/W

STC_GAIN_GX[15:8]

62

98

IMEM_SRAM_REG_98

R/W

STC_GAIN_GX[23:16]

63

99

IMEM_SRAM_REG_99

R/W

STC_GAIN_GX[31:24]

64

100

IMEM_SRAM_REG_100

R/W

STC_GAIN_GY[7:0]

65

101

IMEM_SRAM_REG_101

R/W

STC_GAIN_GY[15:8]

66

102

IMEM_SRAM_REG_102

R/W

STC_GAIN_GY[23:16]

67

103

IMEM_SRAM_REG_103

R/W

STC_GAIN_GY[31:24]

68

104

IMEM_SRAM_REG_104

R/W

STC_GAIN_GZ[7:0]

69

105

IMEM_SRAM_REG_105

R/W

STC_GAIN_GZ[15:8]

6A

106

IMEM_SRAM_REG_106

R/W

STC_GAIN_GZ[23:16]

6B

107

IMEM_SRAM_REG_107

R/W

STC_GAIN_GZ[31:24]

88

136

IMEM_SRAM_REG_136

R/W

FF_DURATION_BUF1[7:0]

ST_STATUSGZ_ST_PASS

GY_ST_PASS

GX_ST_PASS

FF_DURATION_BUF1[15:8]

QUAT_RESET_EN

89

137

IMEM_SRAM_REG_137

R/W

8A

138

IMEM_SRAM_REG_138

R/W

FF_DURATION_BUF2[7:0]

8B

139

IMEM_SRAM_REG_139

R/W

FF_DURATION_BUF2[15:8]

8D

141

IMEM_SRAM_REG_141

R/W

TAP_NUM

8E

142

IMEM_SRAM_REG_142

R/W

TAP_AXIS

8F

143

IMEM_SRAM_REG_143

R/W

TAP_DIR

90

144

IMEM_SRAM_REG_144

R/W

DOUBLE_TAP_TIMING

92

146

IMEM_SRAM_REG_146

R/W

TILT_RESET_EN

9A

154

IMEM_SRAM_REG_154

R/W

PED_STEP_CNT_BUF1[7:0]

9B

155

IMEM_SRAM_REG_155

R/W

PED_STEP_CNT_BUF1[15:8]

9C

156

IMEM_SRAM_REG_156

R/W

PED_STEP_CNT_BUF2[7:0]

9D

157

IMEM_SRAM_REG_157

R/W

PED_STEP_CNT_BUF2[15:8]

9F

159

IMEM_SRAM_REG_159

R/W

PED_STEP_CADENCE

A0

160

IMEM_SRAM_REG_160

R/W

POWER_ACTIVITY_CLASS

B6

182

IMEM_SRAM_REG_182

R/W

ES_RAM_IMAGE_EN

B9

185

IMEM_SRAM_REG_185

R/W

ES0_COMPASS_EN

BA

186

IMEM_SRAM_REG_186

R/W

ES_POWER_MODE

C4

196

IMEM_SRAM_REG_196

R/W

POWER_SAVE_TIME[7:0]

C5

197

IMEM_SRAM_REG_197

R/W

POWER_SAVE_TIME[15:8]

Page 58 of 191
Document Number: DS-000576
Revision: 1.0

Bit2

AZ_ST_PASS

AY_ST_PASS

AX_ST_PASSICM-45605
Addr
(Hex)

Addr
(Dec.)

Register Name

Serial
I/F

C6

198

IMEM_SRAM_REG_198

R/W

POWER_SAVE_TIME[23:16]

C7

199

IMEM_SRAM_REG_199

R/W

POWER_SAVE_TIME[31:24]

120

288

IMEM_SRAM_REG_288

R/W

FF_MIN_DURATION[7:0]

121

289

IMEM_SRAM_REG_289

R/W

FF_MIN_DURATION[15:8]

122

290

IMEM_SRAM_REG_290

R/W

FF_MIN_DURATION[23:16]

123

291

IMEM_SRAM_REG_291

R/W

FF_MIN_DURATION[31:24]

124

292

IMEM_SRAM_REG_292

R/W

FF_MAX_DURATION[7:0]

125

293

IMEM_SRAM_REG_293

R/W

FF_MAX_DURATION[15:8]

126

294

IMEM_SRAM_REG_294

R/W

FF_MAX_DURATION[23:16]

127

295

IMEM_SRAM_REG_295

R/W

FF_MAX_DURATION[31:24]

128

296

IMEM_SRAM_REG_296

R/W

FF_DEBOUNCE_DURATION[7:0]

Bit7

Bit6

Bit5

Bit4

Bit3

129

297

IMEM_SRAM_REG_297

R/W

FF_DEBOUNCE_DURATION[15:8]

12A

298

IMEM_SRAM_REG_298

R/W

FF_DEBOUNCE_DURATION[23:16]

12B

299

IMEM_SRAM_REG_299

R/W

FF_DEBOUNCE_DURATION[31:24]

130

304

IMEM_SRAM_REG_304

R/W

HIGHG_PEAK_TH[7:0]

131

305

IMEM_SRAM_REG_305

R/W

HIGHG_PEAK_TH[15:8]

132

306

IMEM_SRAM_REG_306

R/W

HIGHG_PEAK_TH_HYST[7:0]

133

307

IMEM_SRAM_REG_307

R/W

HIGHG_PEAK_TH_HYST[15:8]

134

308

IMEM_SRAM_REG_308

R/W

HIGHG_TIME_TH[7:0]

135

309

IMEM_SRAM_REG_309

R/W

HIGHG_TIME_TH[15:8]

13C

316

IMEM_SRAM_REG_316

R/W

LOWG_PEAK_TH[7:0]

13D

317

IMEM_SRAM_REG_317

R/W

LOWG_PEAK_TH[15:8]

13E

318

IMEM_SRAM_REG_318

R/W

LOWG_PEAK_TH_HYST[7:0]

13F

319

IMEM_SRAM_REG_319

R/W

LOWG_PEAK_TH_HYST[15:8]

140

320

IMEM_SRAM_REG_320

R/W

LOWG_TIME_TH[7:0]

141

321

IMEM_SRAM_REG_321

R/W

LOWG_TIME_TH[15:8]

188

392

IMEM_SRAM_REG_392

R/W

TILT_WAIT_TIME[7:0]

189

393

IMEM_SRAM_REG_393

R/W

TILT_WAIT_TIME[15:8]

190

400

IMEM_SRAM_REG_400

R/W

TAP_TMAX[7:0]

191

401

IMEM_SRAM_REG_401

R/W

TAP_TMAX[15:8]

192

402

IMEM_SRAM_REG_402

R/W

TAP_TMIN

193

403

IMEM_SRAM_REG_403

R/W

TAP_MIN_JERK

194

404

IMEM_SRAM_REG_404

R/W

TAP_SMUDGE_REJECT_THR

195

405

IMEM_SRAM_REG_405

R/W

TAP_MAX_PEAK_TOL

196

406

IMEM_SRAM_REG_406

R/W

TAP_TAVG

21C

543

IMEM_SRAM_REG_540

R/W

R2W_SLEEP_TIME_OUT[7:0]

21D

543

IMEM_SRAM_REG_541

R/W

R2W_SLEEP_TIME_OUT[15:8]

21E

543

IMEM_SRAM_REG_542

R/W

R2W_SLEEP_TIME_OUT[23:16]

21F

543

IMEM_SRAM_REG_543

R/W

R2W_SLEEP_TIME_OUT[31:24]

220

544

IMEM_SRAM_REG_544

R/W

R2W_SLEEP_GESTURE_DELAY[7:0]

221

545

IMEM_SRAM_REG_545

R/W

R2W_SLEEP_GESTURE_DELAY[15:8]

222

546

IMEM_SRAM_REG_546

R/W

R2W_SLEEP_GESTURE_DELAY[23:16]

223

547

IMEM_SRAM_REG_547

R/W

R2W_SLEEP_GESTURE_DELAY[31:24]

224

548

IMEM_SRAM_REG_548

R/W

R2W_MOUNTING_MATRIX[7:0]

225

549

IMEM_SRAM_REG_549

R/W

R2W_MOUNTING_MATRIX[15:8]

226

550

IMEM_SRAM_REG_550

R/W

R2W_MOUNTING_MATRIX[23:16]

227

551

IMEM_SRAM_REG_551

R/W

R2W_MOUNTING_MATRIX[31:24]

22C

556

IMEM_SRAM_REG_556

R/W

R2W_GRAVITY_FILTER_GAIN[7:0]

22D

557

IMEM_SRAM_REG_557

R/W

R2W_GRAVITY_FILTER_GAIN[15:8]

22E

558

IMEM_SRAM_REG_558

R/W

R2W_GRAVITY_FILTER_GAIN[23:16]

22F

559

IMEM_SRAM_REG_559

R/W

R2W_GRAVITY_FILTER_GAIN[31:24]

Page 59 of 191
Document Number: DS-000576
Revision: 1.0

Bit2

Bit1

Bit0

ICM-45605
Addr
(Hex)

Addr
(Dec.)

Register Name

Serial
I/F

230

560

IMEM_SRAM_REG_560

R/W

R2W_MOTION_THR_ANGLE_COSINE[7:0]

231

561

IMEM_SRAM_REG_561

R/W

R2W_MOTION_THR_ANGLE_COSINE[15:8]

232

562

IMEM_SRAM_REG_562

R/W

R2W_MOTION_THR_ANGLE_COSINE[23:16]

233

563

IMEM_SRAM_REG_563

R/W

R2W_MOTION_THR_ANGLE_COSINE[31:24]

234

564

IMEM_SRAM_REG_564

R/W

R2W_MOTION_THR_TIMER_FAST[7:0]

235

565

IMEM_SRAM_REG_565

R/W

R2W_MOTION_THR_TIMER_FAST[15:8]

236

566

IMEM_SRAM_REG_566

R/W

R2W_MOTION_THR_TIMER_FAST[23:16]

237

567

IMEM_SRAM_REG_567

R/W

R2W_MOTION_THR_TIMER_FAST[31:24]

238

568

IMEM_SRAM_REG_568

R/W

R2W_MOTION_THR_TIMER_SLOW[7:0]

239

569

IMEM_SRAM_REG_569

R/W

R2W_MOTION_THR_TIMER_SLOW[15:8]

23A

570

IMEM_SRAM_REG_570

R/W

R2W_MOTION_THR_TIMER_SLOW[23:16]

23B

571

IMEM_SRAM_REG_571

R/W

R2W_MOTION_THR_TIMER_SLOW[31:24]

23C

572

IMEM_SRAM_REG_572

R/W

R2W_MOTION_PREV_GRAVITY_TIMEOUT[7:0]

23D

573

IMEM_SRAM_REG_573

R/W

R2W_MOTION_PREV_GRAVITY_TIMEOUT[15:8]

23E

574

IMEM_SRAM_REG_574

R/W

R2W_MOTION_PREV_GRAVITY_TIMEOUT[23:16]
R2W_MOTION_PREV_GRAVITY_TIMEOUT[31:24]

Bit7

Bit6

Bit5

Bit4

Bit3

23F

575

IMEM_SRAM_REG_575

R/W

240

576

IMEM_SRAM_REG_576

R/W

R2W_LAST_GRAVITY_MOTION_TIMER[7:0]

241

577

IMEM_SRAM_REG_577

R/W

R2W_LAST_GRAVITY_MOTION_TIMER[15:8]

242

578

IMEM_SRAM_REG_578

R/W

R2W_LAST_GRAVITY_MOTION_TIMER[23:16]

243

579

IMEM_SRAM_REG_579

R/W

R2W_LAST_GRAVITY_MOTION_TIMER[31:24]

244

580

IMEM_SRAM_REG_580

R/W

R2W_LAST_GRAVITY_TIMEOUT[7:0]

245

581

IMEM_SRAM_REG_581

R/W

R2W_LAST_GRAVITY_TIMEOUT[15:8]

246

582

IMEM_SRAM_REG_582

R/W

R2W_LAST_GRAVITY_TIMEOUT[23:16]

247

583

IMEM_SRAM_REG_583

R/W

R2W_LAST_GRAVITY_TIMEOUT[31:24]

248

584

IMEM_SRAM_REG_584

R/W

R2W_GESTURE_VALIDITY_TIMEOUT[7:0]

249

585

IMEM_SRAM_REG_585

R/W

R2W_GESTURE_VALIDITY_TIMEOUT[15:8]

24A

586

IMEM_SRAM_REG_586

R/W

R2W_GESTURE_VALIDITY_TIMEOUT[23:16]
R2W_GESTURE_VALIDITY_TIMEOUT[31:24]

24B

587

IMEM_SRAM_REG_587

R/W

3DC

988

IMEM_SRAM_REG_988

R/W

PED_STEP_CNT_TH[7:0]

3DD

989

IMEM_SRAM_REG_989

R/W

PED_STEP_CNT_TH[15:8]

3DE

990

IMEM_SRAM_REG_990

R/W

PED_STEP_DET_TH[7:0]

3DF

991

IMEM_SRAM_REG_991

R/W

PED_STEP_DET_TH[15:8]

3E2

994

IMEM_SRAM_REG_994

R/W

PED_SB_TIMER_TH[7:0]

3E3

995

IMEM_SRAM_REG_995

R/W

PED_SB_TIMER_TH[15:8]

3E8

1000

IMEM_SRAM_REG_1000

R/W

PED_LOW_EN_AMP_TH[7:0]

3E9

1001

IMEM_SRAM_REG_1001

R/W

PED_LOW_EN_AMP_TH[15:8]

3EA

1002

IMEM_SRAM_REG_1002

R/W

PED_LOW_EN_AMP_TH[23:16]

3EB

1003

IMEM_SRAM_REG_1003

R/W

PED_LOW_EN_AMP_TH[31:24]

3EC

1004

IMEM_SRAM_REG_1004

R/W

PED_SENSITIVITY_MODE

3F0

1008

IMEM_SRAM_REG_1008

R/W

PED_AMP_TH[7:0]

3F1

1009

IMEM_SRAM_REG_1009

R/W

PED_AMP_TH[15:8]

3F2

1010

IMEM_SRAM_REG_1010

R/W

PED_AMP_TH[23:16]

3F3

1011

IMEM_SRAM_REG_1011

R/W

PED_AMP_TH[31:24]

3F8

1016

IMEM_SRAM_REG_1016

R/W

PED_HI_EN_TH[7:0]

3F9

1017

IMEM_SRAM_REG_1017

R/W

PED_HI_EN_TH[15:8]

3FA

1018

IMEM_SRAM_REG_1018

R/W

PED_HI_EN_TH[23:16]

3FB

1019

IMEM_SRAM_REG_1019

R/W

PED_HI_EN_TH[31:24]

412

1042

IMEM_SRAM_REG_1042

R/W

SMD_SENSITIVITY

490
to
4B3

1168 to1203

IMEM_SRAM_REG_1168 to
IMEM_SRAM_REG_1203

R/W

SOFT_IRON_SENSITIVITY_MATRIX[287:0]

Page 60 of 191
Document Number: DS-000576
Revision: 1.0

Bit2

Bit1

Bit0

ICM-45605
16.3

USER BANK IPREG_BAR REGISTER MAP

Addr
(Hex)

Addr
(Dec.)

Register Name

SerialI/F

39

57

IPREG_BAR_REG_57

R/W

Bit7

Bit6

Bit5

Bit4

Bit3

-

IO_OPT0

IO_OPT1

PADS_AP_SC
LK_PE_TRIM_
D2A-

PADS_AP_CS_PUD_TRIM_
D2A

PADS_AP_CS_PE_TRIM_D
2A

Bit2

Bit1

Bit0

-

3A

58

IPREG_BAR_REG_58

R/W

PADS_AP_SC
LK_PUD_TRI
M_D2A

3B

59

IPREG_BAR_REG_59

R/W

PADS_PIN7_
PE_TRIM_D2
A-

PADS_AP_SD
O_PUD_TRIM_D2A

PADS_AP_SD
O_PE_TRIM_
D2A-

PADS_AP_SD
I_PUD_TRIM_D2A

PADS_AP_SD
I_PE_TRIM_D
2A-

PADS_AUX1_
SCLK_PE_TRI
M_D2A

PADS_AUX_S
CLK_TP2_FR
OM_PAD_DIS
ABLE_TRIM_
D2A

PADS_AUX1_
CS_PUD_TRI
M_D2A

PADS_AUX1_
CS_PE_TRIM_D2A-

PADS_PIN7_
CS_PUD_TRI
M_D2A

-

PADS_AUX1_
SDO_PUD_TR
IM_D2A

PADS_AUX1_
SDO_PE_TRI
M_D2A

-

PADS_AUX1_
SDI_PUD_TRI
M_D2A

PADS_AUX1_
SDI_PE_TRIM_D2A

PADS_INT2_P
UD_TRIM_D2
A

PADS_INT2_P
E_TRIM_D2A

-

Bit2

Bit1

Bit0

3C

60

IPREG_BAR_REG_60

R/W-

PADS_AUX1_
SCLK_PUD_T
RIM_D2A

3D

61

IPREG_BAR_REG_61

R/W

PADS_INT1_P
UD_TRIM_D2
A

PADS_INT1_P
E_TRIM_D2A

3E

62

IPREG_BAR_REG_62

R/W

16.4

-

-

IO_OPT2

USER BANK IPREG_TOP1 REGISTER MAP

Addr
(Hex)

Addr
(Dec.)

Register Name

Serial
I/F

Bit7

Bit6

06

06

I2CM_COMMAND_0

R/W

ENDFLAG_0

CH_SEL_0

R_W_0

BURSTLEN_0

0707

I2CM_COMMAND_1

R/W

ENDFLAG_1

CH_SEL_1

R_W_1

BURSTLEN_1

0808

I2CM_COMMAND_2

R/W

ENDFLAG_2

CH_SEL_2

R_W_2

BURSTLEN_2

09

09

I2CM_COMMAND_3

R/W

ENDFLAG_3

CH_SEL_3

R_W_3

0E

14

I2CM_DEV_PROFILE0

R/W

0F

15

I2CM_DEV_PROFILE1

R/W

10

16

I2CM_DEV_PROFILE2

R/W

11

17

I2CM_DEV_PROFILE3

R/W

Bit5

Bit4

Bit3

BURSTLEN_3
RD_ADDRESS_0-

DEV_ID_0
RD_ADDRESS_1-

DEV_ID_1
I2CM_RESTA
RT_EN

16

22

I2CM_CONTROL

RWS

-

-

18

24

I2CM_STATUS

R

1A

26

I2CM_EXT_DEV_STATUS

1B

27

I2CM_RD_DATA0RWS

I2CM_RD_DATA0I2CM_SDA_E
RR-

I2CM_SPEED
I2CM_SCL_E
RR

I2CM_SRST_E
RR

-

1C

28

I2CM_RD_DATA1RWS

I2CM_RD_DATA129

I2CM_RD_DATA2RWS

I2CM_RD_DATA2

1E

30

I2CM_RD_DATA3RWS

I2CM_RD_DATA3

1F

31

I2CM_RD_DATA4RWS

I2CM_RD_DATA42032

I2CM_RD_DATA5RWS

I2CM_RD_DATA52133

I2CM_RD_DATA6RWS

I2CM_RD_DATA62234

I2CM_RD_DATA7RWS

I2CM_RD_DATA72335

I2CM_RD_DATA8RWS

I2CM_RD_DATA82436

I2CM_RD_DATA9RWS

I2CM_RD_DATA92537I2CM_RD_DATA10

RWS

I2CM_RD_DATA1026

38

I2CM_RD_DATA11

RWS

I2CM_RD_DATA1127

39

I2CM_RD_DATA12RWS

I2CM_RD_DATA1228

40

I2CM_RD_DATA13

RWS

I2CM_RD_DATA1329

41

I2CM_RD_DATA14

RWS

I2CM_RD_DATA14

2A

42

I2CM_RD_DATA15

RWS

I2CM_RD_DATA15

2B

43

I2CM_RD_DATA16

RWS

I2CM_RD_DATA16

2C

44

I2CM_RD_DATA17

RWS

I2CM_RD_DATA17

2D

45

I2CM_RD_DATA18

RWS

I2CM_RD_DATA18

Page 61 of 191

I2CM_TIMEOUT_ERR

I2CM_GO
I2CM_DONE

I2CM_EXT_DEV_STATUS

1D

Document Number: DS-000576
Revision: 1.0-

I2CM_BUSYICM-45605
Addr
(Hex)

Addr
(Dec.)

Register Name

SerialI/F

2E

46

I2CM_RD_DATA19

RWS

I2CM_RD_DATA19

2F

47

I2CM_RD_DATA20

RWS

I2CM_RD_DATA20

33

51

I2CM_WR_DATA0R/W

I2CM_WR_DATA03452

I2CM_WR_DATA1

R/W

I2CM_WR_DATA13553

I2CM_WR_DATA2R/W

I2CM_WR_DATA23654

I2CM_WR_DATA3R/W

I2CM_WR_DATA33755

I2CM_WR_DATA4R/W

I2CM_WR_DATA43856

I2CM_WR_DATA5R/W

I2CM_WR_DATA5

4B

75

SIFS_IXC_ERROR_STATUS

R/C

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

-

4F

79

EDMP_PRGRM_IRQ0_0

R/W

PRGRM_STRT_ADDR_IRQ_0[7:0]5080EDMP_PRGRM_IRQ0_1

R/W

PRGRM_STRT_ADDR_IRQ_0[15:8]

51

81

EDMP_PRGRM_IRQ1_0

R/W

PRGRM_STRT_ADDR_IRQ_1[7:0]5282

EDMP_PRGRM_IRQ1_1

R/W

PRGRM_STRT_ADDR_IRQ_1[15:8]

53

83

EDMP_PRGRM_IRQ2_0

R/W

PRGRM_STRT_ADDR_IRQ_2[7:0]5484

EDMP_PRGRM_IRQ2_1

R/W

PRGRM_STRT_ADDR_IRQ_2[15:8]

55

85

EDMP_SP_START_ADDR

R/W

EDMP_SP_START_ADDR

58

88

SMC_CONTROL_0

R/W

59

89

SMC_CONTROL_1

R/W

-

63

99

STC_CONFIG

R/W-

ACCEL_LP_CL
K_SEL

-

TEMP_DISTMST_FORCE_AUX_FINE_E
N

SREG_AUX_A
CCEL_ONLY_
EN

Bit1

Bit0

AUX1_SIFS_I
XC_TIMEOUT_ERR

SIFS_IXC_TIM
EOUT_ERRTMST_FSYNC_EN

TMST_EN-

STC_SENSOR_SEL

67

103

SREG_CTRL

R/W

68

104

SIFS_I3C_STC_CFG

R/W-

SREG_DATA_ENDIAN_SEL

I3C_STC_MO
DE

-

69

105

INT_PULSE_MIN_ON_INTF0

R/W

-

6A

106

INT_PULSE_MIN_ON_INTF1

R/W-

INT0_TPULSE_DURATION
INT1_TPULSE_DURATION

6B

107

INT_PULSE_MIN_OFF_INTF0

R/W-

INT0_TDEASSERT_DISABLE

6C

108

INT_PULSE_MIN_OFF_INTF1

R/W-

INT1_TDEASSERT_DISABLE

6E

110

ISR_0_7

R/C-

INT_STATUS_
ON_DEMAN
D_PIN_0

6F

111

ISR_8_15

R/C-

INT_STATUS_
ON_DEMAN
D_PIN_1-

INT_STATUS_
EXT_ODR_DR
DY_PIN_1-

INT_STATUS_ACCEL_DRDY_PIN_1

70

112

ISR_16_23

R/C-

INT_STATUS_
ON_DEMAN
D_PIN_2-

INT_STATUS_
EXT_ODR_DR
DY_PIN_2-

INT_STATUS_ACCEL_DRDY_PIN_2

71

113

STATUS_MASK_PIN_0_7

R/W-

INT_ON_DE
MAND_PIN_
0_DIS-

INT_EXT_OD
R_DRDY_PIN_0_DIS-

INT_ACCEL_D
RDY_PIN_0_
DIS

72

114

STATUS_MASK_PIN_8_15

R/W-

INT_ON_DE
MAND_PIN_
1_DIS-

INT_EXT_OD
R_DRDY_PIN_1_DIS-

INT_ACCEL_D
RDY_PIN_1_
DIS

73

115

STATUS_MASK_PIN_16_23

R/W-

INT_ON_DE
MAND_PIN_
2_DIS-

INT_EXT_OD
R_DRDY_PIN_2_DIS-

INT_ACCEL_D
RDY_PIN_2_
DIS

74

116

INT_I2CM_SOURCE

R/W

7E

126

ACCEL_WOM_X_THR

R/W

WOM_X_TH

7F

127

ACCEL_WOM_Y_THR

R/W

WOM_Y_TH

80

128

ACCEL_WOM_Z_THR

R/W

90

144

SELFTEST97

151

IPREG_MISC

R

A2

162

SW_PLL1_TRIM

R-

INT_STATUS_ACCEL_DRDY_PIN_0-

INT_STATUS_
I2CM_SMC_E
XT_ODR_EN-

EN_AY_ST

EN_AX_ST

EDMP_IDLE-

WOM_Z_TH-

EN_GZ_ST

EN_GY_ST

EN_GX_ST

SW_PLL1_TRIM

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INT_STATUS_
EXT_ODR_DR
DY_PIN_0

EN_AZ_STICM-45605
Addr
(Hex)

Addr
(Dec.)

Register Name

Serial
I/F

A7

167

FIFO_SRAM_SLEEP

R/W

16.5

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

-

Bit1

Bit0

FIFO_GSLEEP_SHARED_SRAM

USER BANK IPREG_SYS1 REGISTER MAP

Addr
(Hex)

Addr
(Dec.)

Register Name

SerialI/F

2A

42

IPREG_SYS1_REG_42

R/W

2B

43

IPREG_SYS1_REG_43

R/W

38

56

IPREG_SYS1_REG_56

R/W

39

57

IPREG_SYS1_REG_57

R/W

46

70

IPREG_SYS1_REG_56

R/W

47

71

IPREG_SYS1_REG_57

R/W

A6

166

IPREG_SYS1_REG_166

R/W

AA

170

IPREG_SYS1_REG_170

R/W

AC

172

IPREG_SYS1_REG_172

R/W

16.6

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

GYRO_X_OFFUSER[7:0]-

GYRO_X_OFFUSER[13:8]
GYRO_Y_OFFUSER[7:0]-

GYRO_Y_OFFUSER[13:8]
GYRO_Z_OFFUSER[7:0]-

GYRO_Z_OFFUSER[13:8]-

GYRO_SRC_CTRL--

GYRO_LP_AVG_SEL-

GYRO_UI_LPFBW_SEL

USER BANK IPREG_SYS2 REGISTER MAP

Addr
(Hex)

Addr
(Dec.)

Register Name

SerialI/F

18

24

IPREG_SYS2_REG_24

R/W

19

25

IPREG_SYS2_REG_25

R/W

20

32

IPREG_SYS2_REG_32

R/W

21

33

IPREG_SYS2_REG_33

R/W

28

40

IPREG_SYS2_REG_40

R/W

29

41

IPREG_SYS2_REG_41

R/W

7B

123

IPREG_SYS2_REG_123

R/W

81

129

IPREG_SYS2_REG_129

R/W

83

131

IPREG_SYS2_REG_131

R/W

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

ACCEL_X_OFFUSER[7:0]-

ACCEL_X_OFFUSER[13:8]
ACCEL_Y_OFFUSER[7:0]-

ACCEL_Y_OFFUSER[13:8]
ACCEL_Z_OFFUSER[7:0]-

ACCEL_Z_OFFUSER[13:8]-

ACCEL_SRC_CTRL
ACCEL_LP_AVG_SEL-

ACCEL_UI_LPFBW_SEL

Detailed register descriptions are provided in the sections that follow.
Register fields marked as Reserved must not be modified by the user. The Reset Value of the register can be used
to determine the default value of reserved register fields, and unless otherwise noted this default value must be
maintained even if the values of other register fields are modified by the user.
In the sections that follow, some register fields are described as “can be changed on-the-fly.” These are the only
register fields that can be changed on-the-fly even if sensor is on. Register fields not described as such must not bechanged on-the-fly if sensor is on.

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Bit0

ICM-45605
17 USER BANK 0 REGISTER MAP – DESCRIPTIONS
Please refer to the procedure in Section 14 for configuring device data endianness before using the register map.

17.1

ACCEL_DATA_X1_UI

Name: ACCEL_DATA_X1_UI
Address: 00 (00h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 ACCEL_DATA_X_UI[15:8]

17.2

ACCEL_DATA_X0_UI

Name: ACCEL_DATA_X0_UI
Address: 01 (01h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 ACCEL_DATA_X_UI[7:0]

17.3

FUNCTION
Upper byte of Accel Y-axis data for UI path

ACCEL_DATA_Y0_UI

Name: ACCEL_DATA_Y0_UI
Address: 03 (03h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 ACCEL_DATA_Y_UI[7:0]

17.5

FUNCTION
Lower byte of Accel X-axis data for UI path

ACCEL_DATA_Y1_UI

Name: ACCEL_DATA_Y1_UI
Address: 02 (02h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 ACCEL_DATA_Y_UI[15:8]

17.4

FUNCTION
Upper byte of Accel X-axis data for UI path

FUNCTION
Lower byte of Accel Y-axis data for UI path

ACCEL_DATA_Z1_UI

Name: ACCEL_DATA_Z1_UI
Address: 04 (04h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 ACCEL_DATA_Z_UI[15:8]

FUNCTION
Upper byte of Accel Z-axis data for UI path

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ICM-45605
17.6

ACCEL_DATA_Z0_UI

Name: ACCEL_DATA_Z0_UI
Address: 05 (05h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 ACCEL_DATA_Z_UI[7:0]17.7

GYRO_DATA_X1_UI

Name: GYRO_DATA_X1_UI
Address: 06 (06h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 GYRO_DATA_X_UI[15:8]

17.8

FUNCTION
Upper byte of Gyro X-axis data for UI path

GYRO_DATA_X0_UI

Name: GYRO_DATA_X0_UI
Address: 07 (07h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 GYRO_DATA_X_UI[7:0]

17.9

FUNCTION
Lower byte of Accel Z-axis data for UI path

FUNCTION
Lower byte of Gyro X-axis data for UI path

GYRO_DATA_Y1_UI

Name: GYRO_DATA_Y1_UI
Address: 08 (08h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 GYRO_DATA_Y_UI[15:8]

FUNCTION
Upper byte of Gyro Y-axis data for UI path

17.10 GYRO_DATA_Y0_UI
Name: GYRO_DATA_Y0_UI
Address: 09 (09h)Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 GYRO_DATA_Y_UI[7:0]

FUNCTION
Lower byte of Gyro Y-axis data for UI path

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ICM-45605
17.11 GYRO_DATA_Z1_UI
Name: GYRO_DATA_Z1_UI
Address: 10 (0Ah)
Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 GYRO_DATA_Z_UI[15:8]

FUNCTION
Upper byte of Gyro Z-axis data for UI path

17.12 GYRO_DATA_Z0_UI
Name: GYRO_DATA_Z0_UI
Address: 11 (0Bh)
Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 GYRO_DATA_Z_UI[7:0]

FUNCTION
Lower byte of Gyro Z-axis data for UI path

17.13 TEMP_DATA1_UI
Name: TEMP_DATA1_UI
Address: 12 (0Ch)
Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 TEMP_DATA_UI[15:8]

FUNCTION
Upper byte of temperature data for UI path

17.14 TEMP_DATA0_UI
Name: TEMP_DATA0_UI
Address: 13 (0Dh)
Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 TEMP_DATA_UI[7:0]

FUNCTION
Lower byte of temperature data for UI path

Temperature data value from the sensor data registers can be converted to degrees centigrade by using thefollowing formula:
Temperature in Degrees Centigrade = (TEMP_DATA / 128) + 25
Temperature data stored in FIFO is an 8-bit quantity, FIFO_TEMP_DATA. It can be converted to degrees centigradeby using the following formula:
Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2) + 25

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ICM-45605
17.15 TMST_FSYNCH
Name: TMST_FSYNCH
Address: 14 (0Eh)
Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0

TMST_FSYNC_DATA_UI[15:8]

FUNCTIONStores the upper byte of the time delta from the rising edge of FSYNC tothe latest ODR until the UI Interface reads the FSYNC tag in the status
register

17.16 TMST_FSYNCLName: TMST_FSYNCL
Address: 15 (0Fh)
Serial IF: SYNCRReset value: 0x00
Clock Domain: SCLKBIT NAME
7:0

TMST_FSYNC_DATA_UI[7:0]

FUNCTIONStores the lower byte of the time delta from the rising edge of FSYNC tothe latest ODR until the UI Interface reads the FSYNC tag in the status
register

17.17 PWR_MGMT0
Name: PWR_MGMT0
Address: 16 (10h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:4 -

3:2

1:0

GYRO_MODE

ACCEL_MODE

FUNCTION
Reserved
00: Turns gyroscope off
01: Places gyroscope in Standby Mode
10: Places gyroscope in Low Power (LP) Mode
11: Places gyroscope in Low Noise (LN) ModeCan be changed on-the-fly.
00: Turns accelerometer off
01: Turns accelerometer off
10: Places accelerometer in Low Power (LP) Mode
11: Places accelerometer in Low Noise (LN) ModeCan be changed on-the-fly.

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ICM-45605
17.18 FIFO_COUNT_0
Name: FIFO_COUNT_0
Address: 18 (12h)Serial IF: R
Reset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 FIFO_DATA_CNT[15:8]

FUNCTION
High Bits, count indicates the number of packets available in FIFO.

17.19 FIFO_COUNT_1
Name: FIFO_COUNT_1
Address: 19 (13h)Serial IF: R
Reset value: 0x00
Clock Domain: SCLKBIT NAME
7:0 FIFO_DATA_CNT[7:0]

FUNCTION
Low Bits, count indicates the number of packets available in FIFO.

17.20 FIFO_DATA
Name: FIFO_DATA
Address: 20 (14h)Serial IF: R
Reset value: 0x7F
Clock Domain: SCLKBIT NAME
7:0 FIFO_DATAFUNCTIONFIFO data port

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ICM-45605
17.21 INT1_CONFIG0
Name: INT1_CONFIG0
Address: 22 (16h)Serial IF: R/W
Reset value: 0x80
Clock Domain: MCLKBIT NAME

7

INT1_STATUS_EN_RESET_DONE

FUNCTION
Enable interrupt status bit to flag the occurrence of Reset Done event on
INT1
0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of AUX1 AGC Ready event
on INT1

6

INT1_STATUS_EN_AUX1_A
GC_RDY

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of UI AGC Ready event on
INT1

5

INT1_STATUS_EN_AP_AGC_RDY

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of UI FSYNC event on INT1

4

INT1_STATUS_EN_AP_FSY
NC

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of AUX1 Data Ready event
on INT1

3

INT1_STATUS_EN_AUX1_D
RDY

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of UI Data Ready event on
INT1

2

1

INT1_STATUS_EN_DRDY

INT1_STATUS_EN_FIFO_TH
S

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of FIFO count ≥ FIFO
threshold event on INT1

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ICM-45605
0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of FIFO full event on INT10

INT1_STATUS_EN_FIFO_FU
LL

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.

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ICM-45605
17.22 INT1_CONFIG1
Name: INT1_CONFIG1
Address: 23 (17h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7-

6

INT1_STATUS_EN_APEX_E
VENT

FUNCTION
Reserved
Enable interrupt status bit to flag the occurrence of APEX event on INT1
0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the completion of I2C master event on INT1

5

INT1_STATUS_EN_I2CM_D
ONE

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of I3C Protocol Error event
on INT1

4

INT1_STATUS_EN_I3C_PRO
TOCOL_ERR

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of WOM on Z-axis event on
INT1

3

INT1_STATUS_EN_WOM_Z

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of WOM on Y-axis event on
INT1

2

INT1_STATUS_EN_WOM_Y

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of WOM on X-axis event on
INT1

1

INT1_STATUS_EN_WOM_X

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of PLL Ready event on INT10

INT1_STATUS_EN_PLL_RDY
0: Disable interrupt.

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ICM-45605
1: Enable interrupt.
Setting can be changed by UI interface.

17.23 INT1_CONFIG2
Name: INT1_CONFIG2
Address: 24 (18h)Serial IF: R/W
Reset value: 0x04
Clock Domain: MCLKBIT NAME
7:3 2

INT1_DRIVE

1

INT1_MODE

FUNCTION
Reserved
Sets INT1 to open-drain or push-pull
0: Push-pull
1: Open-drain
INT1 interrupt mode
0: Pulse mode
1: Latch mode
Setting can be changed only when all interrupts of the corresponding serialinterface are disabled
INT1 interrupt polarity

0

INT1_POLARITY

0: Active low
1: Active highSetting can be changed only when all interrupts of the corresponding serialinterface are disabled

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ICM-45605
17.24 INT1_STATUS0
Name: INT1_STATUS0
Address: 25 (19h)Serial IF: R/C
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7

INT1_STATUS_RESET_DON
E

6

INT1_STATUS_AUX1_AGC_
RDY

5

INT1_STATUS_AP_AGC_RD
Y

4

INT1_STATUS_AP_FSYNC

3

INT1_STATUS_AUX1_DRDY

2

INT1_STATUS_DRDY

1

INT1_STATUS_FIFO_THS0

INT1_STATUS_FIFO_FULL

FUNCTION
Flags the occurrence of Reset Done event on INT1
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of AUX1 AGC Ready event on INT1
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of UI AGC Ready event on INT1
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of UI FSYNC event on INT1
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of AUX1 Data Ready event on INT1
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of UI Data Ready event on INT1
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of FIFO count ≥ FIFO threshold event on INT1
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of FIFO full event on INT1
0: Interrupt did not occur
1: Interrupt occurred

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ICM-45605
17.25 INT1_STATUS1
Name: INT1_STATUS1
Address: 26 (1Ah)
Serial IF: R/C
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7
6

INT1_STATUS_APEX_EVEN
T

5

INT1_STATUS_I2CM_DONE

4

INT1_STATUS_I3C_PROTO
COL_ERR

3

INT1_STATUS_WOM_Z

2

INT1_STATUS_WOM_Y

1

INT1_STATUS_WOM_X

0

INT1_STATUS_PLL_RDY

FUNCTION
Reserved
Flags the occurrence of APEX event on INT1
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of I2C Master Done event on INT1
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of I3CSM Protocol Error event on INT1
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of Z-axis WOM event on INT1
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of Y-axis WOM event on INT1
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of X-axis WOM event on INT1
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of PLL Ready event on INT1
0: Interrupt did not occur
1: Interrupt occurred

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ICM-45605
17.26 ACCEL_CONFIG0
Name: ACCEL_CONFIG0
Address: 27 (1Bh)
Serial IF: R/W
Reset value: 0x06
Clock Domain: MCLKBIT NAME
7
-

6:4

3:0

ACCEL_UI_FS_SEL

ACCEL_ODR

FUNCTION
Reserved
Full scale select for accelerometer UI interface output
000: Reserved001: ±16g
010: ±8g
011: ±4g
100: ±2g
101: Reserved
110: Reserved
111: Reserved
Can be changed on-the-fly.
Accelerometer ODR selection for UI interface output
0000: Reserved
0001: Reserved
0010: Reserved0011: 6.4kHz (LN mode)
0100: 3.2kHz (LN mode)
0101: 1.6kHz (LN mode)
0110: 800Hz (LN mode)
0111: 400Hz (LP or LN mode)
1000: 200Hz (LP or LN mode)
1001: 100Hz (LP or LN mode)
1010: 50Hz (LP or LN mode)
1011: 25Hz (LP or LN mode)
1100: 12.5Hz (LP or LN mode)
1101: 6.25Hz (LP mode)
1110: 3.125Hz (LP mode)
1111: 1.5625Hz (LP mode)
Can be changed on-the-fly.

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ICM-45605
17.27 GYRO_CONFIG0
Name: GYRO_CONFIG0
Address: 28 (1Ch)
Serial IF: R/W
Reset value: 0x06
Clock Domain: MCLKBIT NAME

7:4

3:0

GYRO_UI_FS_SEL

GYRO_ODRFUNCTION
Full scale select for gyroscope UI interface output
0000: Reserved
0001: ±2000dps
0010: ±1000dps
0011: ±500dps
0100: ±250dps
0101: ±125dps
0110: ±62.5dps
0111: ±31.25dps
1000: ±15.625dps
Rest of the settings are reserved
Can be changed on-the-fly.
Gyroscope ODR selection for UI interface output
0000: Reserved
0001: Reserved
0010: Reserved0011: 6.4kHz (LN mode)
0100: 3.2kHz (LN mode)
0101: 1.6kHz (LN mode)
0110: 800Hz (LN mode)
0111: 400Hz (LP or LN mode)
1000: 200Hz (LP or LN mode)
1001: 100Hz (LP or LN mode)
1010: 50Hz (LP or LN mode)
1011: 25Hz (LP or LN mode)
1100: 12.5Hz (LP or LN mode)
1101: 6.25Hz (LP mode)
1110: 3.125Hz (LP mode)
1111: 1.5625Hz (LP mode)
Can be changed on-the-fly.

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ICM-45605
17.28 FIFO_CONFIG0
Name: FIFO_CONFIG0
Address: 29 (1Dh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME

7:6

FIFO_MODE

FUNCTION
Set the FIFO operation mode.
00: Bypass (disabled)
01: Stream mode - Frames are overwritten when the FIFO full condition isreached. Supported only for 8, 16, 20 bytes frame size. When this mode isselected for 32 or 64 bytes frame sizes, FIFO remains in Bypass mode.
10: Stop-on-full mode - Frames are not stored in FIFO once the FIFO fullcondition is reached.
11: Reserved
Can be changed on-the-fly.
Set the FIFO depth in bytes.

5:0

FIFO_DEPTH

000111: Sets FIFO depth to 2K bytes (recommended setting)
011111: Sets FIFO depth to 8K bytes (valid when all APEX features are
disabled)
Others: Reserved
Can be changed when FIFO is disabled (Bypass mode).

17.29 FIFO_CONFIG1_0
Name: FIFO_CONFIG1_0
Address: 30 (1Eh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME

7:0

FIFO_WM_TH[7:0]

FUNCTION
Lower bits of FIFO watermark threshold. When set to 0, the watermark is
disabled. When writing new threshold value, user must first write
threshold LSByte (bits [7:0]), then MSByte (bits [15:8]). New thresholdregister value will take effect only when MSByte is written.
Can be changed on-the-fly.

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ICM-45605
17.30 FIFO_CONFIG1_1
Name: FIFO_CONFIG1_1
Address: 31 (1Fh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME

7:0

FIFO_WM_TH[15:8]

FUNCTION
Upper bits of FIFO watermark threshold. When set to 0, the watermark is
disabled. When writing new threshold value, user must first write
threshold LSByte (bits [7:0]), then MSByte (bits [15:8]). New thresholdregister value will take effect only when MSByte is written.
Can be changed on-the-fly.

17.31 FIFO_CONFIG2
Name: FIFO_CONFIG2
Address: 32 (20h)Serial IF: R/W
Reset value: 0x20
Clock Domain: MCLKBIT NAME

FUNCTIONFIFO flush command. When set high the FIFO is flushed, meaning thepointers and control logic is reset. Configuration registers are not reset.

7

FIFO_FLUSH

6:4-

Can be changed on-the-fly.
Reserved
Set write watermark interrupt generating condition:

3

FIFO_WR_WM_GT_TH

0: Write watermark interrupt generated when FIFO data count is equal to
the FIFO watermark threshold
1: Write watermark interrupt generated when FIFO data count is greaterthan or equal to FIFO watermark threshold

2:0-

Can be changed when FIFO is disabled (Bypass mode).
Reserved

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ICM-45605
17.32 FIFO_CONFIG3
Name: FIFO_CONFIG3
Address: 33 (21h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:6 5
FIFO_ES1_EN
4
FIFO_ES0_EN
3
FIFO_HIRES_EN
2
FIFO_GYRO_EN
1
FIFO_ACCEL_EN

0

FIFO_IF_EN

FUNCTION
Reserved
Enable External Sensor 1 data insertion into FIFO frame
Enable External Sensor 0 data insertion into FIFO frame
Enable high resolution accel and gyro data insertion into FIFO frame
Enable gyro data insertion into FIFO frame
Enable accel data insertion into FIFO frame
Enable Sensor Registers write interface to FIFO. This interface should beenabled when the FIFO is also enabled (i.e., not in bypass mode). A
standard enable sequence is:1) Enable FIFO.
2) Enable Sensor Registers to FIFO interface.
The opposite sequence should be used for the disable.
To prevent power drain, FIFO_IF_EN should be set to 0 if FIFO is in bypassmode.
Can be changed on-the-fly.

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ICM-45605
17.33 FIFO_CONFIG4
Name: FIFO_CONFIG4
Address: 34 (22h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:6 -

5:3

FIFO_COMP_NC_FLOW_CFG

2

FIFO_COMP_EN

1

FIFO_TMST_FSYNC_EN

0

FIFO_ES0_6B_9B

FUNCTION
Reserved
Configures the compression algorithm to write non-compressed packets
to FIFO at a certain rate
000: Non-compressed packet flow is disabled
001: Non-compressed packet every 8 frames
010: Non-compressed packet every 16 frames
011: Non-compressed packet every 32 frames
100: Non-compressed packet every 64 frames
101: Non-compressed packet every 128 frames
Others: Reserved
0: FIFO compression disabled
1: FIFO compression enabled
Enable the insertion of the Timestamp or FSYNC data into FIFO frame
0: No Timestamp/FSYNC data inserted into FIFO frame (timestamp fields
are 0x0000). FSYNC_TAG_EN bit in FIFO header is 0.
1: Timestamp/FSYNC data inserted into FIFO frame. FSYNC_TAG_EN bit in
FIFO header is set on an FSYNC trigger event.
Select number of valid bytes provided by External Sensor 0
0: 6 bytes
1: 9 bytes

Page 80 of 191
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ICM-45605
17.34 TMST_WOM_CONFIG
Name: TMST_WOM_CONFIG
Address: 35 (23h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7-

6

TMST_DELTA_EN

5

TMST_RESOL

4

WOM_EN3

WOM_MODE2

WOM_INT_MODE

1:0

WOM_INT_DUR

FUNCTION
Reserved
Time Stamp Delta Enable
0: Time stamp field does not contain the measurement of time since thelast occurrence of trigger event
1: Time stamp field contains the measurement of time since the last
occurrence of trigger event
Time Stamp Resolution
0: 1µs1: 16µs
Wake on Motion Enable
0: Wake on Motion not enabled
1: Wake on Motion enabled
Wake on Motion Mode
0: Initial sample is stored. Future samples are compared to initial sample
1: Compare current sample to previous sample
Wake on Motion Interrupt
0: Off
1: On
Wake on Motion Interrupt Duration
00: Wake on Motion interrupt asserted at first over-threshold event
01: Wake on Motion interrupt asserted at second over-threshold event
10: Wake on Motion interrupt asserted at third over-threshold event
11: Wake on Motion interrupt asserted at fourth over-threshold event

Page 81 of 191
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ICM-45605
17.35 FSYNC_CONFIG0
Name: FSYNC_CONFIG0
Address: 36 (24h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:4 -

3

2:0

AP_FSYNC_FLAG_CLEAR_SEL

AP_FSYNC_SEL

FUNCTION
Reserved
Select the AP/UI FSYNC flag clear policy.
0: The FSYNC flag is cleared when UI/AP sensor register is updated.
1: The FSYNC flag is cleared when UI/AP serial interface reads the sensor
register LSB of FSYNC tagged axis.
Select the AP/UI sensor that will carry the FSYNC tagging.
0: FSYNC tagging is disabled
1: Tag FSYNC flag to TEMP_DATA_UI LSB
2: Tag FSYNC flag to GYRO_DATA_X_UI LSB
3: Tag FSYNC flag to GYRO_DATA_Y_UI LSB
4: Tag FSYNC flag to GYRO_DATA_Z_UI LSB
5: Tag FSYNC flag to ACCEL_DATA_X_UI LSB
6: Tag FSYNC flag to ACCEL_DATA_Y_UI LSB
7: Tag FSYNC flag to ACCEL_DATA_Z_UI LSBPage 82 of 191
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ICM-45605
17.36 DMP_EXT_SEN_ODR_CFG
Name: DMP_EXT_SEN_ODR_CFG
Address: 39 (27h)Serial IF: R/W
Reset value: 0x01
Clock Domain: MCLKBIT NAME
76

EXT_SENSOR_EN

5:3

EXT_ODR

2:0

APEX_ODRFUNCTION
Reserved
0: Disables generation of ODR event for external sensor operation per thesetting of EXT_ODR.
1: Enables generation of ODR event for external sensor operation per thesetting of EXT_ODR.
I2C master external sensor ODR
000: 3.125Hz
001: 6.25Hz
010: 12.5Hz
011: 25Hz
100: 50Hz
101: 100Hz
110: 200Hz
111: 400HzDMP Output Data Rate. APEX_ODR should be smaller than or equal toboth ACCEL_ODR and GYRO_ODR. All rates shown below except 800Hz
can be set if Accel UI/AP in in LP mode. Accel UI/AP must be in LN mode to
set 800Hz.
000: 25Hz
001: 50Hz
010: 100Hz
011: 200Hz
100: 400Hz
101: 800Hz
110: Reserved
111: Reserved

Page 83 of 191
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ICM-45605
17.37 ODR_DECIMATE_CONFIG
Name: ODR_DECIMATE_CONFIG
Address: 40 (28h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME

7:4

3:0

GYRO_FIFO_ODR_DEC

ACCEL_FIFO_ODR_DEC

FUNCTION
Decimation factor for Gyroscope FIFO data:
0000: 1 (same are input ODR)
0001: 20010: 40011: 80100: 160101: 320110: 640111: 128
1000: 256
1001: 512
1010: 1024
1011: 2048
1100: 4096
1101: Reserved
1110: Reserved
1111: Reserved
Decimation factor for Accelerometer FIFO data:
0000: 1 (same are input ODR)
0001: 20010: 40011: 80100: 160101: 320110: 640111: 128
1000: 256
1001: 512
1010: 1024
1011: 2048
1100: 4096
1101: Reserved
1110: Reserved
1111: Reserved

Page 84 of 191
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ICM-45605
17.38 EDMP_APEX_EN0
Name: EDMP_APEX_EN0
Address: 41 (29h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7
SMD_EN
6
R2W_EN
5
FF_EN
4
PEDO_EN
3
TILT_EN
2:1 0
TAP_ENFUNCTION
Set 1 to enable SMD algorithm
Set 1 to enable Raise to Wake algorithm
Set 1 to enable Freefall algorithm
Set 1 to enable Pedometer algorithm
Set 1 to enable Tilt algorithm
Reserved
Set 1 to enable Tap algorithm

17.39 EDMP_APEX_EN1
Name: EDMP_APEX_EN1
Address: 42 (2Ah)
Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7
6
EDMP_ENABLE
5FEATURE3_EN
4:3 2
POWER_SAVE_EN
1

INIT_EN0

SOFT_HARD_IRON_CORR_EN

FUNCTION
Reserved
Set 1 to enable eDMP
Set 1 to enable eDMP to run algorithms from RAM image
Reserved
Set 1 to enable power save modeThis bit is set by the host to indicate: eDMP executes only the segment ofcode that initialize constants used by algorithms.
Set 1 to enable soft iron hard iron correction

Page 85 of 191
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ICM-45605
17.40 APEX_BUFFER_MGMT
Name: APEX_BUFFER_MGMT
Address: 43 (2Bh)
Serial IF: R/W (bits 5:4 are R only)
Reset value: 0x00
Clock Domain: MCLKBIT NAME

FUNCTION
LSB indicates SRAM address for host to read; MSB indicates size 2 buffer
wrap around

7:6

FF_DURATION_HOST_RPTR

00: Host reads buffer 0
01: Host reads buffer 1
10: Host reads buffer 0
11: Host reads buffer 1
Read only register field: LSB indicates SRAM address for eDMP to write;
MSB indicates size 2 buffer wrap around

5:4

FF_DURATION_EDMP_WPTR

00: eDMP writes to buffer 0
01: eDMP writes to buffer 1
10: eDMP writes to buffer 0
11: eDMP writes to buffer 1
LSB indicates SRAM address for host to read; MSB indicates size 2 buffer
wrap around

3:2

STEP_COUNT_HOST_RPTR

00: Host reads buffer 0
01: Host reads buffer 1
10: Host reads buffer 0
11: Host reads buffer 1
Read only register field: LSB indicates SRAM address for eDMP to write;
MSB indicates size 2 buffer wrap around

1:0

STEP_COUNT_EDMP_WPTR

00: eDMP writes to buffer 0
01: eDMP writes to buffer 1
10: eDMP writes to buffer 0
11: eDMP writes to buffer 1

Page 86 of 191
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ICM-45605
17.41 INTF_CONFIG0
Name: INTF_CONFIG0
Address: 44 (2Ch)
Serial IF: R/W (bits 1 and 0 are Read only)
Reset value: 0x9A
Clock Domain: MCLKBIT NAME
FUNCTION
7:2 Reserved
Read only register field, shows OTP trim for UI interface SPI in 3-wire or 4wire mode
1
AP_SPI_34_MODE
0: 3-wire mode
1: 4-wire mode
Read only register field, shows OTP trim for UI interface SPI mode
selection0
AP_SPI_MODE
0: SPI mode 0 or 3
1: SPI mode 1 or 2

17.42 INTF_CONFIG1_OVRD
Name: INTF_CONFIG1_OVRD
Address: 45 (2Dh)
Serial IF: R/W
Reset value: 0x0C
Clock Domain: SCLKBIT NAME
7:4 3

AP_SPI_34_MODE_OVRD

2

AP_SPI_34_MODE_OVRD_VA
L

1

AP_SPI_MODE_OVRD

0

AP_SPI_MODE_OVRD_VAL

FUNCTION
Reserved
0: Override disable for AP interface SPI 4-wire/3-wire modes
1: Override enable for AP interface SPI 4-wire/3-wire modes
Override value for AP interface SPI 4-wire/3-wire modes
0: SPI 3-wire mode
1: SPI 4-wire mode
0: Override disable for AP interface SPI_MODE value
1: Override enable for AP interface SPI_MODE value
Override value for AP interface SPI Mode
0: SPI mode 0 or 3
1: SPI mode 1 or 2

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ICM-45605
17.43 IOC_PAD_SCENARIO
Name: IOC_PAD_SCENARIO
Address: 47 (2Fh)
Serial IF: R
Reset value: 0x09
Clock Domain: MCLKBIT NAME
7:3 -

2:1

AUX1_MODE0

AUX1_ENABLE

FUNCTION
Reserved
Read only register field, effective only when AUX1_ENABLE is 1. Selects
AUX1 mode:
00: Reserved
01: AUX1 in I2C Master mode
10: AUX1 in I2C Master Bypass mode (Enable only when AP is not in SPI
mode)
11: Reserved
Read only register field, enable or disable AUX1
0: AUX1 disabled
1: AUX1 enabled

17.44 IOC_PAD_SCENARIO_AUX_OVRD
Name: IOC_PAD_SCENARIO_AUX_OVRD
Address: 48 (30h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
FUNCTION
7:5 Reserved
Override enable for AUX1_MODE
4
AUX1_MODE_OVRD
0: Disable
1: Enable
Override value for AUX1_ENABLE. Effective only when AUX1_ENABLE is 1.
Selects modes of AUX1 use:

3:2

AUX1_ENABLE_OVRD_VAL

1

AUX1_ENABLE_OVRD

0

AUX1_ENABLE_OVRD_VAL

0: Reserved
1: AUX1 in I2C Master mode
2: AUX1 in I2C Master Bypass mode (enable only when AP is not in SPI
mode)
Note: When enabling the I2C Master Bypass mode, this register should be
programmed individually, not as part of a burst transaction.
Override enable for AUX1_ENABLE
0: Disable
1: Enable
Override value for AUX1_ENABLE
0: AUX1 disabled
1: AUX1 enabled

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ICM-45605
17.45 DRIVE_CONFIG0
Name: DRIVE_CONFIG0
Address: 50 (32h)Serial IF: R/W
Reset value: 0x6C
Clock Domain: MCLKBIT NAME
7-

6:4

PADS_I2C_SLEW

FUNCTION
Reserved
Slew rate control for any pin in the I2C mode of operation, including pinson the AP serial interface when device is a client device of an I 2C bus,
including pins on the AUX1 serial interface when device is a master deviceof an I2C bus. Setting of the slew rate takes effect 1.5µs after the register
is programmed.
000: MIN: 3 ns; TYP: 20 ns; MAX: 136 ns
010: MIN: 2 ns; TYP: 7 ns; MAX: 84 ns
Others: Reserved
Slew rate control for any pin in the SPI mode of operation.
Setting of the slew rate takes effect 1.5µs after the register is
programmed.

3:1

PADS_SPI_SLEW

0-000: MIN: 12 ns; TYP: 38 ns; MAX: 106 ns
001: MIN: 4 ns; TYP: 14 ns; MAX: 45 ns
010: MIN: 3 ns; TYP: 10 ns; MAX: 37 ns
011: MIN: 2 ns; TYP: 7 ns; MAX: 25 ns
100: MIN: 1 ns; TYP: 5 ns; MAX: 17 ns
101: MIN: 1 ns; TYP: 4 ns; MAX: 14 ns
11x: MIN: 0.1 ns; TYP: 0.5 ns; MAX: 6 ns
Reserved

Page 89 of 191
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ICM-45605
17.46 DRIVE_CONFIG1
Name: DRIVE_CONFIG1
Address: 51 (33h)Serial IF: R/W
Reset value: 0x36
Clock Domain: MCLKBIT NAME
7:6 -

5:3

2:0

PADS_I3C_DDR_SLEW

PADS_I3C_SDR_SLEW

FUNCTION
Reserved
Slew rate control when device is in I3CSM DDR protocol. Setting of the slew
rate takes effect 1.5µs after the register is programmed.
000: MIN: 12 ns; TYP: 38 ns; MAX: 106 ns
001: MIN: 4 ns; TYP: 14 ns; MAX: 45 ns
010: MIN: 3 ns; TYP: 10 ns; MAX: 37 ns
011: MIN: 2 ns; TYP: 7 ns; MAX: 25 ns
100: MIN: 1 ns; TYP: 5 ns; MAX: 17 ns
101: MIN: 1 ns; TYP: 4 ns; MAX: 14 ns
11x: MIN: 0.1 ns; TYP: 0.5 ns; MAX: 6 ns
Slew rate control when device is in I3CSM SDR protocol. Setting of the slew
rate takes effect 1.5µs after the register is programmed.
000: MIN: 12 ns; TYP: 38 ns; MAX: 106 ns
001: MIN: 4 ns; TYP: 14 ns; MAX: 45 ns
010: MIN: 3 ns; TYP: 10 ns; MAX: 37 ns
011: MIN: 2 ns; TYP: 7 ns; MAX: 25 ns
100: MIN: 1 ns; TYP: 5 ns; MAX: 17 ns
101: MIN: 1 ns; TYP: 4 ns; MAX: 14 ns
11x: MIN: 0.1 ns; TYP: 0.5 ns; MAX: 6 ns

17.47 DRIVE_CONFIG2
Name: DRIVE_CONFIG2
Address: 52 (34h)Serial IF: R/W
Reset value: 0x06
Clock Domain: MCLKBIT NAME
7:3 -

2:0

PADS_SLEWFUNCTION
Reserved
Slew rate control for INT1 pin at all times. Slew rate control for all pins
before OTP copy operation is completed. Setting of the slew rate takes
effect 1.5µs after the register is programmed.
000: MIN: 12 ns; TYP: 38 ns; MAX: 106 ns
001: MIN: 4 ns; TYP: 14 ns; MAX: 45 ns
010: MIN: 3 ns; TYP: 10 ns; MAX: 37 ns
011: MIN: 2 ns; TYP: 7 ns; MAX: 25 ns
100: MIN: 1 ns; TYP: 5 ns; MAX: 17 ns
101: MIN: 1 ns; TYP: 4 ns; MAX: 14 ns
11x: MIN: 0.1 ns; TYP: 0.5 ns; MAX: 6 ns

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ICM-45605
17.48 REG_MISC1
Name: REG_MISC1
Address: 53 (35h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:4 -

3:0

OSC_ID_OVRD

FUNCTION
Reserved
Selects MCLK source.
0000: MCLK source requested by internal logic (default)
0010: Requests internal relaxation oscillator
1000: Requests external clock
Rest: Reserved
The selected clock source is the highest index that's requested and that isready.

Page 91 of 191
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ICM-45605
17.49 INT_APEX_CONFIG0
Name: INT_APEX_CONFIG0
Address: 57 (39h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME

7

6

5

4

3

2

1

0

INT_STATUS_MASK_PIN_R2
W_WAKE_DET

INT_STATUS_MASK_PIN_FF_
DET

INT_STATUS_MASK_PIN_STE
P_DET

INT_STATUS_MASK_PIN_STE
P_CNT_OVFL

INT_STATUS_MASK_PIN_TILT_DET

INT_STATUS_MASK_PIN_LO
W_G_DET

INT_STATUS_MASK_PIN_HIG
H_G_DET

INT_STATUS_MASK_PIN_TAP_DET

FUNCTION
Enable interrupt pin assertion when the INT_STATUS_R2W_WAKE_DET
status bit is 1.
0: Enable Interrupt pin assertion
1: No Interrupt pin assertion
Enable interrupt pin assertion when the INT_STATUS_FF_DET status bit is1.
0: Enable Interrupt pin assertion
1: No Interrupt pin assertion
Enable interrupt pin assertion when the INT_STATUS_STEP_DET status bit
is 1.
0: Enable Interrupt pin assertion
1: No Interrupt pin assertion
Enable interrupt pin assertion when the INT_STATUS_STEP_CNT_OVFL
status bit is 1.
0: Enable Interrupt pin assertion
1: No Interrupt pin assertion
Enable interrupt pin assertion when the INT_STATUS_TILT_DET status bit
is 1.
0: Enable Interrupt pin assertion
1: No Interrupt pin assertion
Enable interrupt pin assertion when the INT_STATUS_LOW_G_DET status
bit is 1.
0: Enable Interrupt pin assertion
1: No Interrupt pin assertion
Enable interrupt pin assertion when the INT_STATUS_HIGH_G_DET status
bit is 1.
0: Enable Interrupt pin assertion
1: No Interrupt pin assertion
Enable interrupt pin assertion when the INT_STATUS_TAP_DET status bit
is 1.
0: Enable Interrupt pin assertion
1: No Interrupt pin assertion

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ICM-45605
17.50 INT_APEX_CONFIG1
Name: INT_APEX_CONFIG1
Address: 58 (3Ah)
Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:5 INT_STATUS_MASK_PIN_SA_
4
DONE
3INT_STATUS_MASK_PIN_SELF
2
TEST_DONE
INT_STATUS_MASK_PIN_SM
1
D_DET
INT_STATUS_MASK_PIN_R2
0
W_SLEEP_DET

FUNCTION
Reserved
0: Enable interrupt generation when Secure Authentication is done
1: Disable interrupt generation for Secure Authentication
Reserved
0: Enable interrupt generation when self-test is done
1: Disable interrupt generation for self-test
0: Enable interrupt generation for Significant Motion Detection (SMD)
1: Disable interrupt generation for Significant Motion Detection (SMD)
0: Enable interrupt generation for Wake Sleep Detection
1: Disable interrupt generation for Wake Sleep Detection

17.51 INT_APEX_STATUS0
Name: INT_APEX_STATUS0
Address: 59 (3Bh)
Serial IF: R/C
Reset value: 0x00
Clock Domain: MCLKBIT NAME
INT_STATUS_R2W_WAKE_DE
7
T
6

INT_STATUS_FF_DET

5

INT_STATUS_STEP_DET

4

INT_STATUS_STEP_CNT_OVF
L

3

INT_STATUS_TILT_DET

2

INT_STATUS_LOW_G_DET

1

INT_STATUS_HIGH_G_DET

0

INT_STATUS_TAP_DET

FUNCTION
0: Wake interrupt did not occur.
1: Wake interrupt occurred.
0: Freefall interrupt did not occur.
1: Freefall interrupt occurred.
0: Step Detection interrupt did not occur.
1: Step Detection interrupt occurred.
0: Step-Count Overflow interrupt did not occur.
1: Step-Count Overflow interrupt occurred.
0: Tilt Detection interrupt did not occur.
1: Tilt Detection interrupt occurred.
0: LowG Detection interrupt did not occur.
1: LowG Detection interrupt occurred.
0: HighG Detection interrupt did not occur.
1: HighG Detection interrupt occurred.
0: Tap Detection interrupt did not occur.
1: Tap Detection interrupt occurred.

Page 93 of 191
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ICM-45605
17.52 INT_APEX_STATUS1
Name: INT_APEX_STATUS1
Address: 60 (3Ch)
Serial IF: R/C
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:5 4

INT_STATUS_SA_DONE

3

-

2

INT_STATUS_SELFTEST_DONE

1

INT_STATUS_SMD_DET

0

INT_STATUS_R2W_SLEEP_DET

FUNCTION
Reserved
For EDMP_OUT interface.
0: Secure Authentication interrupt did not occur.
1: Secure Authentication interrupt occurred.
Reserved
0: Self-Test interrupt did not occur.
1: Self-Test interrupt occurred.
This bit is set to 1 when Significant Motion Detection (SMD) interrupt isgenerated
0: Significant Motion Detection (SMD) interrupt did not occur.
1: Significant Motion Detection (SMD) interrupt occurred.
0: Sleep interrupt did not occur.
1: Sleep interrupt occurred.

Page 94 of 191
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ICM-45605
17.53 INT2_CONFIG0
Name: INT2_CONFIG0
Address: 86 (56h)Serial IF: R/W
Reset value: 0x80
Clock Domain: MCLKBIT NAME

7

INT2_STATUS_EN_RESET_DONE

FUNCTION
Enable interrupt status bit to flag the occurrence of Reset Done event on
INT2
0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI or AUX1 interface.
Enable interrupt status bit to flag the occurrence of AUX1 AGC Ready event
on INT2

6

INT2_STATUS_EN_AUX1_A
GC_RDY

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI or AUX1 interface.
Enable interrupt status bit to flag the occurrence of UI AGC Ready event on
INT2

5

INT2_STATUS_EN_AP_AGC_RDY

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI or AUX1 interface.
Enable interrupt status bit to flag the occurrence of UI FSYNC event on INT2

4

INT2_STATUS_EN_AP_FSY
NC

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI or AUX1 interface.
Enable interrupt status bit to flag the occurrence of AUX1 Data Ready event
on INT2

3

INT2_STATUS_EN_AUX1_D
RDY

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI or AUX1 interface.
Enable interrupt status bit to flag the occurrence of UI Data Ready event on
INT2

2

1

INT2_STATUS_EN_DRDY

INT2_STATUS_EN_FIFO_TH
S

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI or AUX1 interface.
Enable interrupt status bit to flag the occurrence of FIFO count ≥ FIFO
threshold event on INT2

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ICM-45605
0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI or AUX1 interface.
Enable interrupt status bit to flag the occurrence of FIFO full event on INT20

INT2_STATUS_EN_FIFO_FU
LL

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI or AUX1 interface.

Page 96 of 191
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ICM-45605
17.54 INT2_CONFIG1
Name: INT2_CONFIG1
Address: 87 (57h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7-

6

INT2_STATUS_EN_APEX_E
VENT

FUNCTION
Reserved
Enable interrupt status bit to flag the occurrence of APEX event on INT2
0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the completion of I2C master event on INT2

5

INT2_STATUS_EN_I2CM_D
ONE

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of I3C Protocol Error event
on INT2

4

INT2_STATUS_EN_I3C_PRO
TOCOL_ERR

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of WOM on Z-axis event on
INT2

3

INT2_STATUS_EN_WOM_Z

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of WOM on Y-axis event on
INT2

2

INT2_STATUS_EN_WOM_Y

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of WOM on X-axis event on
INT2

1

INT2_STATUS_EN_WOM_X

0: Disable interrupt.
1: Enable interrupt.
Setting can be changed by UI interface.
Enable interrupt status bit to flag the occurrence of PLL Ready event on INT20

INT2_STATUS_EN_PLL_RDY
0: Disable interrupt.

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ICM-45605
1: Enable interrupt.
Setting can be changed by UI interface.

17.55 INT2_CONFIG2
Name: INT2_CONFIG2
Address: 88 (58h)Serial IF: R/W
Reset value: 0x04
Clock Domain: MCLKBIT NAME
7:3 2

INT2_DRIVE

1

INT2_MODE

FUNCTION
Reserved
Sets INT2 to open-drain or push-pull
0: Push-pull
1: Open-drain
INT2 interrupt mode
0: Pulse mode
1: Latch mode
Setting can be changed only when all interrupts of the corresponding serialinterface are disabled
INT2 interrupt polarity

0

INT2_POLARITY

0: Active low
1: Active highSetting can be changed only when all interrupts of the corresponding serialinterface are disabled

Page 98 of 191
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ICM-45605
17.56 INT2_STATUS0
Name: INT2_STATUS0
Address: 89 (59h)Serial IF: R/C
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7

INT2_STATUS_RESET_DON
E

6

INT2_STATUS_AUX1_AGC_
RDY

5

INT2_STATUS_AP_AGC_RD
Y

4

INT2_STATUS_AP_FSYNC

3

INT2_STATUS_AUX1_DRDY

2

INT2_STATUS_DRDY

1

INT2_STATUS_FIFO_THS0

INT2_STATUS_FIFO_FULL

FUNCTION
Flags the occurrence of Reset Done event on INT2
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of AUX1 AGC Ready event on INT2
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of UI AGC Ready event on INT2
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of UI FSYNC event on INT2
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of AUX1 Data Ready event on INT2
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of UI Data Ready event on INT2
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of FIFO count ≥ FIFO threshold event on INT2
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of FIFO full event on INT2
0: Interrupt did not occur
1: Interrupt occurred

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17.57 INT2_STATUS1
Name: INT2_STATUS1
Address: 90 (5Ah)
Serial IF: R/C
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7
6

INT2_STATUS_APEX_EVEN
T

5

INT2_STATUS_I2CM_DONE

4

INT2_STATUS_I3C_PROTO
COL_ERR

3

INT2_STATUS_WOM_Z

2

INT2_STATUS_WOM_Y

1

INT2_STATUS_WOM_X

0

INT2_STATUS_PLL_RDY

FUNCTION
Reserved
Flags the occurrence of APEX event on INT2
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of I2C Master Done event on INT2
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of I3CSM Protocol Error event on INT2
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of Z-axis WOM event on INT2
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of Y-axis WOM event on INT2
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of X-axis WOM event on INT2
0: Interrupt did not occur
1: Interrupt occurred
Flags the occurrence of PLL Ready event on INT2
0: Interrupt did not occur
1: Interrupt occurred

17.58 WHO_AM_I
Name: WHO_AM_I
Address: 114 (72h)Serial IF: R
Reset value: 0xE5
Clock Domain: ALL
BIT NAME
7:0 WHOAMI

FUNCTION
Register to indicate to user which device is being accessed

Description:
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default
value of the register is 0xE5. This is different from the I2C address of the device as seen on the slave I2C controller
by the applications processor.

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17.59 REG_HOST_MSG
Name: REG_HOST_MSG
Address: 115 (73h)Serial IF: R/W
Reset value: 0x00
Clock Domain: SCLKBIT NAME
7:6 5

EDMP_ON_DEMAND_EN

4:1
0

TESTOPENABLE

FUNCTION
Reserved
When set, a trigger will be sent which will cause the eDMP to run once. It is
automatically reset to 0.
Reserved
1: Enable test operation

17.60 IREG_ADDR_15_8
Name: IREG_ADDR_15_8
Address: 124 (7Ch)
Serial IF: R/W
Reset value: 0xAF
Clock Domain: SCLKBIT NAME
7:0

IREG_ADDR_15_8

FUNCTION
Address bit[15:8] of the 16-bit indirect address for assessing indirect accessregisters (IREG)
Can be changed on-the-fly.

17.61 IREG_ADDR_7_0
Name: IREG_ADDR_7_0
Address: 125 (7Dh)
Serial IF: R/W
Reset value: 0x06
Clock Domain: SCLKBIT NAME
7:0

IREG_ADDR_7_0

FUNCTION
Address bit[7:0] of the 16-bit indirect address for assessing indirect accessregisters (IREG)
Can be changed on-the-fly.

17.62 IREG_DATA
Name: IREG_DATA
Address: 126 (7Eh)
Serial IF: R/W
Reset value: 0x02
Clock Domain: SCLKBIT NAME
7:0

FUNCTION
Register for indirect access registers (IREG) data read/write operations.

IREG_DATACan be changed on-the-fly.

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17.63 REG_MISC2
Name: REG_MISC2
Address: 127 (7Fh)
Serial IF: R/W
Reset value: 0x01
Clock Domain: SCLKBIT NAME
7:2 -

1

0

SOFT_RST

IREG_DONE

FUNCTION
Reserved
0: Soft reset not enabled.
1: Triggers soft reset operation. The programmed value of 1 is self-cleared to
0 upon completion of soft reset operation.
Can be changed on-the-fly.
0: Indicates that an indirect register access operation is in progress. No new
indirect register access should be triggered.
1: Indirect register access has completed. New indirect register access can betriggered.

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ICM-45605
18 USER BANK IMEM_SRAM REGISTER MAP – DESCRIPTIONSThis section describes the function and contents of each register within user bank IMEM_SRAM. The registers
described in this section are indirect access registers. Section 13 describes the procedure for accessing indirectaccess registers.

18.1

IMEM_SRAM_REG_0

Name: IMEM_SRAM_REG_0
Address: 00 (00h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Self-test response for gyro X-axis. Units are in kdps. Full scale is 0.5kdps, LSB
7:0 GYRO_X_STR_FT[7:0]is 30mdps.

18.2

IMEM_SRAM_REG_1

Name: IMEM_SRAM_REG_1
Address: 01 (01h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Self-test response for gyro X-axis. Units are in kdps. Full scale is 0.5kdps, LSB
7:0 GYRO_X_STR_FT[15:8]
is 30mdps.

18.3

IMEM_SRAM_REG_2

Name: IMEM_SRAM_REG_2
Address: 02 (02h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Self-test response for gyro Y-axis. Units are in kdps. Full scale is 0.5kdps, LSB
7:0 GYRO_Y_STR_FT[7:0]is 30mdps.

18.4

IMEM_SRAM_REG_3

Name: IMEM_SRAM_REG_3
Address: 03 (03h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Self-test response for gyro Y-axis. Units are in kdps. Full scale is 0.5kdps, LSB
7:0 GYRO_Y_STR_FT[15:8]
is 30mdps.

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18.5

IMEM_SRAM_REG_4

Name: IMEM_SRAM_REG_4
Address: 04 (04h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Self-test response for gyro Z-axis. Units are in kdps. Full scale is 0.5kdps, LSB
7:0 GYRO_Z_STR_FT[7:0]is 30mdps.

18.6

IMEM_SRAM_REG_5

Name: IMEM_SRAM_REG_5
Address: 05 (05h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Self-test response for gyro Z-axis. Units are in kdps. Full scale is 0.5kdps, LSB
7:0 GYRO_Z_STR_FT[15:8]
is 30mdps.

18.7

IMEM_SRAM_REG_6

Name: IMEM_SRAM_REG_6
Address: 06 (06h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTIONGYRO_X_CMOS_GAIN_FT[
Gyro X-axis gain measurement result. Units are in kdps. FSR is 500 dps,
7:0
7:0]
resolution is 122 mdps.

18.8

IMEM_SRAM_REG_7

Name: IMEM_SRAM_REG_7
Address: 07 (07h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:4 Reserved
GYRO_X_CMOS_GAIN_FT[
Gyro X-axis gain measurement result. Units are in kdps. FSR is 500 dps,
3:0
11:8]
resolution is 122 mdps.

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18.9

IMEM_SRAM_REG_8

Name: IMEM_SRAM_REG_8
Address: 08 (08h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTIONGYRO_Y_CMOS_GAIN_FT[
Gyro Y-axis gain measurement result. Units are in kdps. FSR is 500 dps,
7:0
7:0]
resolution is 122 mdps.

18.10 IMEM_SRAM_REG_9
Name: IMEM_SRAM_REG_9
Address: 09 (09h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:4 Reserved
GYRO_Y_CMOS_GAIN_FT
Gyro Y-axis gain measurement result. Units are in kdps. FSR is 500 dps,
3:0
[11:8]
resolution is 122 mdps.

18.11 IMEM_SRAM_REG_10
Name: IMEM_SRAM_REG_10
Address: 10 (0Ah)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTIONGYRO_Z_CMOS_GAIN_FT[
Gyro Z-axis gain measurement result. Units are in kdps. FSR is 500 dps,
7:0
7:0]
resolution is 122 mdps.

18.12 IMEM_SRAM_REG_11
Name: IMEM_SRAM_REG_11
Address: 11 (0Bh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:4 Reserved
GYRO_Z_CMOS_GAIN_FT
Gyro Z-axis gain measurement result. Units are in kdps. FSR is 500 dps,
3:0
[11:8]
resolution is 122 mdps.

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18.13 IMEM_SRAM_REG_56
Name: IMEM_SRAM_REG_56
Address: 56 (38h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Averaging time used to perform self-test (ST_AVG_TIME[2:1] in
IMEM_SRAM_REG_57)

7

ST_AVG_TIME[0]

6:3
2
1
0

ST_GYRO_EN
ST_ACCEL_EN
STC_INIT_EN

000: 10ms
001: 20ms
010: 40ms
011: 80ms
100: 160ms
101: 320ms
Rest: Reserved
Reserved
1: Enable gyro self-test operation
1: Enable accel self-test operation
1: Initializes self-test parameters18.14 IMEM_SRAM_REG_57
Name: IMEM_SRAM_REG_57
Address: 57 (39h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Tolerance between factory trim and gyro self-test response

7:5

4:2

ST_GYRO_LIMIT

ST_ACCEL_LIMIT

000: 5%001: 10%010: 15%011: 20%
100: 25%
101: 30%
110: 40%
111: 50%Tolerance between factory trim and accel self-test response000: 5%001: 10%010: 15%011: 20%
100: 25%
101: 30%
110: 40%
111: 50%

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ICM-45605
Averaging time used to perform self-test (ST_AVG_TIME[0] in
IMEM_SRAM_REG_56)

1:0

ST_AVG_TIME[2:1]000: 10ms
001: 20ms
010: 40ms
011: 80ms
100: 160ms
101: 320ms
Rest: Reserved

18.15 IMEM_SRAM_REG_64
Name: IMEM_SRAM_REG_64
Address: 64 (40h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Debug capability of self-test feature. Must be set to 0 whenever self-test is
7:0 ST_DEBUG_EN
requested.

18.16 IMEM_SRAM_REG_68
Name: IMEM_SRAM_REG_68
Address: 68 (44h)Serial IF: R
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Self-test status (gyro or accel)
7:6

ST_STATUS

5
4
3
2
1
0

GZ_ST_PASS
GY_ST_PASS
GX_ST_PASS
AZ_ST_PASS
AY_ST_PASS
AX_ST_PASS

00: Done
01: In Progress
10: Error
11: Reserved
1: Gyro Z-axis self-test passed
1: Gyro Y-axis self-test passed
1: Gyro X-axis self-test passed
1: Accel Z-axis self-test passed
1: Accel Y-axis self-test passed
1: Accel X-axis self-test passed

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18.17 IMEM_SRAM_REG_92
Name: IMEM_SRAM_REG_92
Address: 92 (5Ch)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Set 1 to force reset 3-axis quaternion when next tilt reset is done. This isapplicable only if TILT_RESET_EN is also set to 1.
7:0 QUAT_RESET_EN
Range: [0 – 1]
Default: 0

18.18 IMEM_SRAM_REG_96
Name: IMEM_SRAM_REG_96
Address: 96 (60h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:0 STC_GAIN_GX[7:0]
Gyro measurements for X-axis in s32.16 for gyro self-test

18.19 IMEM_SRAM_REG_97
Name: IMEM_SRAM_REG_97
Address: 97 (61h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:0 STC_GAIN_GX[15:8]
Gyro measurements for X-axis in s32.16 for gyro self-test

18.20 IMEM_SRAM_REG_98
Name: IMEM_SRAM_REG_98
Address: 98 (62h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:0 STC_GAIN_GX[23:16]
Gyro measurements for X-axis in s32.16 for gyro self-test

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18.21 IMEM_SRAM_REG_99
Name: IMEM_SRAM_REG_99
Address: 99 (63h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:0 STC_GAIN_GX[31:24]
Gyro measurements for X-axis in s32.16 for gyro self-test

18.22 IMEM_SRAM_REG_100
Name: IMEM_SRAM_REG_100
Address: 100 (64h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:0 STC_GAIN_GY[7:0]
Gyro measurements for Y-axis in s32.16 for gyro self-test

18.23 IMEM_SRAM_REG_101
Name: IMEM_SRAM_REG_101
Address: 101 (65h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:0 STC_GAIN_GY[15:8]
Gyro measurements for Y-axis in s32.16 for gyro self-test

18.24 IMEM_SRAM_REG_102
Name: IMEM_SRAM_REG_102
Address: 102 (66h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:0 STC_GAIN_GY[23:16]
Gyro measurements for Y-axis in s32.16 for gyro self-test

18.25 IMEM_SRAM_REG_103
Name: IMEM_SRAM_REG_103
Address: 103 (67h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:0 STC_GAIN_GY[31:24]
Gyro measurements for Y-axis in s32.16 for gyro self-test

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18.26 IMEM_SRAM_REG_104
Name: IMEM_SRAM_REG_104
Address: 104 (68h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:0 STC_GAIN_GZ[7:0]
Gyro measurements for Z-axis in s32.16 for gyro self-test

18.27 IMEM_SRAM_REG_105
Name: IMEM_SRAM_REG_105
Address: 105 (69h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:0 STC_GAIN_GZ[15:8]
Gyro measurements for Z-axis in s32.16 for gyro self-test

18.28 IMEM_SRAM_REG_106
Name: IMEM_SRAM_REG_106
Address: 106 (6Ah)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:0 STC_GAIN_GZ[23:16]
Gyro measurements for Z-axis in s32.16 for gyro self-test

18.29 IMEM_SRAM_REG_107
Name: IMEM_SRAM_REG_107
Address: 107 (6Bh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
7:0 STC_GAIN_GZ[31:24]
Gyro measurements for Z-axis in s32.16 for gyro self-test

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18.30 IMEM_SRAM_REG_136
Name: IMEM_SRAM_REG_136
Address: 136 (88h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Duration of the freefall in number of samples. Filled in alternatively with
FF_DURATION_BUF2.
7:0 FF_DURATION_BUF1[7:0]
Unit: Number of samples. Freefall duration in seconds is
FF_DURATION_BUF1 / ACCEL_ODR (in Hz)

18.31 IMEM_SRAM_REG_137
Name: IMEM_SRAM_REG_137
Address: 137 (89h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Duration of the freefall in number of samples. Filled in alternatively with
FF_DURATION_BUF2.
7:0 FF_DURATION_BUF1[15:8]
Unit: Number of samples. Freefall duration in seconds is
FF_DURATION_BUF1 / ACCEL_ODR (in Hz)

18.32 IMEM_SRAM_REG_138
Name: IMEM_SRAM_REG_138
Address: 138 (8Ah)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Duration of the freefall in number of samples. Filled in alternatively with
FF_DURATION_BUF1.
7:0 FF_DURATION_BUF2[7:0]
Unit: Number of samples. Freefall duration in seconds is
FF_DURATION_BUF2 / ACCEL_ODR (in Hz)

18.33 IMEM_SRAM_REG_139
Name: IMEM_SRAM_REG_139
Address: 139 (8Bh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Duration of the freefall in number of samples. Filled in alternatively with
FF_DURATION_BUF1.
7:0 FF_DURATION_BUF2[15:8]
Unit: Number of samples. Freefall duration in seconds is
FF_DURATION_BUF2 / ACCEL_ODR (in Hz)

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18.34 IMEM_SRAM_REG_141
Name: IMEM_SRAM_REG_141
Address: 141 (8Dh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Type of the last reported TAP event:
7:0 TAP_NUM
0: no tap, 1: single tap, 2: double tap

18.35 IMEM_SRAM_REG_142
Name: IMEM_SRAM_REG_142
Address: 142 (8Eh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Indicates the axis of the tap in the device frame
7:0 TAP_AXIS
0: AX, 1: AY, 2: AZ

18.36 IMEM_SRAM_REG_143
Name: IMEM_SRAM_REG_143
Address: 143 (8Fh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Indicates the direction of the tap in the device frame
7:0 TAP_DIR
0: Positive, 1: Negative

18.37 IMEM_SRAM_REG_144
Name: IMEM_SRAM_REG_144
Address: 144 (90h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Indicate in case of double tap, the sample count between the 2 detected
pulses
7:0 DOUBLE_TAP_TIMING
In case of double tap, indicates the sample count between the two detected
pulses. Double tap timing in seconds is DOUBLE_TAP_TIMING / ACCEL_ODR(in Hz).

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18.38 IMEM_SRAM_REG_146
Name: IMEM_SRAM_REG_146
Address: 146 (92h)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Set 1 to reset tilt prior to any further tilt processing on next sensor data.
7:0 TILT_RESET_EN
Range: [0 - 1]
Default: 0

18.39 IMEM_SRAM_REG_154
Name: IMEM_SRAM_REG_154
Address: 154 (9Ah)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Number of steps done since the last init of the pedometer feature. Filled in
7:0 PED_STEP_CNT_BUF1[7:0]
alternatively with PED_STEP_CNT_BUF2. Unit: number of steps

18.40 IMEM_SRAM_REG_155
Name: IMEM_SRAM_REG_155
Address: 155 (9Bh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTIONPED_STEP_CNT_BUF1[15:8 Number of steps done since the last init of the pedometer feature. Filled in
7:0]
alternatively with PED_STEP_CNT_BUF2. Unit: number of steps

18.41 IMEM_SRAM_REG_156
Name: IMEM_SRAM_REG_156
Address: 156 (9Ch)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Number of steps done since the last init of the pedometer feature. Filled in
7:0 PED_STEP_CNT_BUF2[7:0]
alternatively with PED_STEP_CNT_BUF1. Unit: number of steps

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18.42 IMEM_SRAM_REG_157
Name: IMEM_SRAM_REG_157
Address: 157 (9Dh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTIONPED_STEP_CNT_BUF2[15:8 Number of steps done since the last init of the pedometer feature. Filled in
7:0]
alternatively with PED_STEP_CNT_BUF1. Unit: number of steps

18.43 IMEM_SRAM_REG_159
Name: IMEM_SRAM_REG_159
Address: 159 (9Fh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Instant step cadence measured by the algorithm Unit: 4*number of samples
7:0 PED_STEP_CADENCE
between two consecutive steps. Cadency (step/s) = (ped_step_cadence / 4) /(pedometer_ ODR).

18.44 IMEM_SRAM_REG_160
Name: IMEM_SRAM_REG_160
Address: 160 (A0h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Activity classification of step detected
7:0

POWER_ACTIVITY_CLASS

00000000: Unknown
00000001: Walk
00000010: Run
Others: Reserved

18.45 IMEM_SRAM_REG_182
Name: IMEM_SRAM_REG_182
Address: 182 (B6h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Set 1 to load device specific RAM image for external sensor support,
7:0 ES_RAM_IMAGE_EN
otherwise set 0

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18.46 IMEM_SRAM_REG_185
Name: IMEM_SRAM_REG_185
Address: 185 (B9h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Set 1 for compass support with es0, for other external sensors with es0, set
7:0 ES0_COMPASS_EN
018.47 IMEM_SRAM_REG_186
Name: IMEM_SRAM_REG_186
Address: 186 (BAh)Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Set 1 for possibility of power savings when APEX features utilization is
7:0 ES_POWER_MODE
minimal. Set 0 when APEX features utilization is at maximum.

18.48 IMEM_SRAM_REG_196
Name: IMEM_SRAM_REG_196
Address: 196 (C4h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time of inactivity after which eDMP goes into power save mode.
7:0

POWER_SAVE_TIME[7:0]

Units: Time in sample number
Range: [0 - 4294967295]
Default: 6400 corresponding to 8s for ODR = 800Hz

18.49 IMEM_SRAM_REG_197
Name: IMEM_SRAM_REG_197
Address: 197 (C5h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time of inactivity after which eDMP goes into power save mode.
7:0

POWER_SAVE_TIME[15:8]

Units: Time in sample number
Range: [0 - 4294967295]
Default: 6400 corresponding to 8s for ODR = 800Hz

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18.50 IMEM_SRAM_REG_198
Name: IMEM_SRAM_REG_198
Address: 198 (C6h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time of inactivity after which eDMP goes into power save mode.
7:0

POWER_SAVE_TIME[23:16]

Units: Time in sample number
Range: [0 - 4294967295]
Default: 6400 corresponding to 8s for ODR = 800Hz

18.51 IMEM_SRAM_REG_199
Name: IMEM_SRAM_REG_199
Address: 199 (C7h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time of inactivity after which eDMP goes into power save mode.
7:0

POWER_SAVE_TIME[31:24]

Units: Time in sample number
Range: [0 - 4294967295]
Default: 6400 corresponding to 8s for ODR = 800Hz

18.52 IMEM_SRAM_REG_288
Name: IMEM_SRAM_REG_288
Address: 288 (120h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Minimum freefall duration. Shorter freefalls are ignored.
Unit: time in samples number
7:0 FF_MIN_DURATION[7:0]
Range: [4 - 420]
Default: 57 (set for default ODR = 400 Hz, equivalent to 142 ms)

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18.53 IMEM_SRAM_REG_289
Name: IMEM_SRAM_REG_289
Address: 289 (121h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Minimum freefall duration. Shorter freefalls are ignored.
Unit: time in samples number
7:0 FF_MIN_DURATION[15:8]
Range: [4 - 420]
Default: 57 (set for default ODR = 400 Hz, equivalent to 142 ms)

18.54 IMEM_SRAM_REG_290
Name: IMEM_SRAM_REG_290
Address: 290 (122h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Minimum freefall duration. Shorter freefalls are ignored.
Unit: time in samples number
7:0 FF_MIN_DURATION[23:16]
Range: [4 - 420]
Default: 57 (set for default ODR = 400 Hz, equivalent to 142 ms)

18.55 IMEM_SRAM_REG_291
Name: IMEM_SRAM_REG_291
Address: 291 (123h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Minimum freefall duration. Shorter freefalls are ignored.
Unit: time in samples number
7:0 FF_MIN_DURATION[31:24]
Range: [4 - 420]
Default: 57 (set for default ODR = 400 Hz, equivalent to 142 ms)

18.56 IMEM_SRAM_REG_292
Name: IMEM_SRAM_REG_292
Address: 292 (124h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Maximum freefall duration. Longer freefalls are ignored.
Unit: time in samples number
7:0 FF_MAX_DURATION[7:0]
Range: [12 - 1040]
Default: 285 (set for default ODR = 400 Hz, equivalent to 712 ms)

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18.57 IMEM_SRAM_REG_293
Name: IMEM_SRAM_REG_293
Address: 293 (125h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Maximum freefall duration. Longer freefalls are ignored.
Unit: time in samples number
7:0 FF_MAX_DURATION[15:8]
Range: [12 - 1040]
Default: 285 (set for default ODR = 400 Hz, equivalent to 712 ms)

18.58 IMEM_SRAM_REG_294
Name: IMEM_SRAM_REG_294
Address: 294 (126h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Maximum freefall duration. Longer freefalls are ignored.
FF_MAX_DURATION[23:16 Unit: time in samples number
7:0]
Range: [12 - 1040]
Default: 285 (set for default ODR = 400 Hz, equivalent to 712 ms)

18.59 IMEM_SRAM_REG_295
Name: IMEM_SRAM_REG_295
Address: 295 (127h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Maximum freefall duration. Longer freefalls are ignored.
FF_MAX_DURATION[31:24 Unit: time in samples number
7:0]
Range: [12 - 1040]
Default: 285 (set for default ODR = 400 Hz, equivalent to 712 ms)

18.60 IMEM_SRAM_REG_296
Name: IMEM_SRAM_REG_296
Address: 296 (128h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Period after a freefall is signaled during which a new freefall will not be
detected. Prevents false detection due to bounces.
FF_DEBOUNCE_DURATION
7:0
Unit: time in samples number[7:0]
Range: [75 - 3000]
Default: 800 (set for default ODR = 800 Hz, equivalent to 1 s)

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18.61 IMEM_SRAM_REG_297
Name: IMEM_SRAM_REG_297
Address: 297 (129h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Period after a freefall is signaled during which a new freefall will not be
detected. Prevents false detection due to bounces.
FF_DEBOUNCE_DURATION
7:0
Unit: time in samples number[15:8]
Range: [75 - 3000]
Default: 800 (set for default ODR = 800 Hz, equivalent to 1 s)

18.62 IMEM_SRAM_REG_298
Name: IMEM_SRAM_REG_298
Address: 298 (12Ah)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Period after a freefall is signaled during which a new freefall will not be
detected. Prevents false detection due to bounces.
FF_DEBOUNCE_DURATION
7:0
Unit: time in samples number[23:16]
Range: [75 - 3000]
Default: 800 (set for default ODR = 800 Hz, equivalent to 1 s)

18.63 IMEM_SRAM_REG_299
Name: IMEM_SRAM_REG_299
Address: 299 (12Bh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Period after a freefall is signaled during which a new freefall will not be
detected. Prevents false detection due to bounces.
FF_DEBOUNCE_DURATION
7:0
Unit: time in samples number[31:24]
Range: [75 - 3000]
Default: 800 (set for default ODR = 800 Hz, equivalent to 1 s)

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18.64 IMEM_SRAM_REG_304
Name: IMEM_SRAM_REG_304
Address: 304 (130h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold for accel values above which high-g state is detected.
Unit: g in q12
7:0 HIGHG_PEAK_TH[7:0]
Range: [1024 - 32768]
Default: 29696

18.65 IMEM_SRAM_REG_305
Name: IMEM_SRAM_REG_305
Address: 305 (131h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold for accel values above which high-g state is detected.
Unit: g in q12
7:0 HIGHG_PEAK_TH[15:8]
Range: [1024 - 32768]
Default: 29696

18.66 IMEM_SRAM_REG_306
Name: IMEM_SRAM_REG_306
Address: 306 (132h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Hysteresis value subtracted from the high-g threshold after exceeding it.
HIGHG_PEAK_TH_HYST[7:0 Unit: g in q12
7:0]
Range: [128 - 1024]
Default: 640

18.67 IMEM_SRAM_REG_307
Name: IMEM_SRAM_REG_307
Address: 307 (133h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Hysteresis value subtracted from the high-g threshold after exceeding it.
HIGHG_PEAK_TH_HYST[15: Unit: g in q12
7:0
8]
Range: [128 - 1024]
Default: 640

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18.68 IMEM_SRAM_REG_308
Name: IMEM_SRAM_REG_308
Address: 308 (134h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold for accel values above which high-g state is detected.
Unit: time in samples number
7:0 HIGHG_TIME_TH[7:0]
Range: [1-300]
Default: 1 (set for default ODR = 800 Hz, equivalent to 1.25 ms)

18.69 IMEM_SRAM_REG_309
Name: IMEM_SRAM_REG_309
Address: 309 (135h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold for accel values above which high-g state is detected.
Unit: time in samples number
7:0 HIGHG_TIME_TH[15:8]
Range: [1-300]
Default: 1 (set for default ODR = 800 Hz, equivalent to 1.25 ms)

18.70 IMEM_SRAM_REG_316
Name: IMEM_SRAM_REG_316
Address: 316 (13Ch)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold for accel values below which low-g state is detected.
Unit: g in q12
7:0 LOWG_PEAK_TH[7:0]
Range: [128 - 4096]
Default: 2048

18.71 IMEM_SRAM_REG_317
Name: IMEM_SRAM_REG_317
Address: 317 (13Dh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold for accel values below which low-g state is detected.
Unit: g in q12
7:0 LOWG_PEAK_TH[15:8]
Range: [128 - 4096]
Default: 2048

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18.72 IMEM_SRAM_REG_318
Name: IMEM_SRAM_REG_318
Address: 318 (13Eh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Hysteresis value added to the low-g threshold after exceeding it.
LOWG_PEAK_TH_HYST[7:0 Unit: g in q12
7:0]
Range: [128 - 1024]
Default: 128

18.73 IMEM_SRAM_REG_319
Name: IMEM_SRAM_REG_319
Address: 319 (13Fh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Hysteresis value added to the low-g threshold after exceeding it.
LOWG_PEAK_TH_HYST[15: Unit: g in q12
7:0
8]
Range: [128 - 1024]
Default: 128

18.74 IMEM_SRAM_REG_320
Name: IMEM_SRAM_REG_320
Address: 320 (140h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Number of samples required to enter low-g state.
Unit: time in samples number
7:0 LOWG_TIME_TH[7:0]
Range: [1 - 300]
Default: 13 (set for default ODR = 800 Hz, equivalent to 16 ms)

18.75 IMEM_SRAM_REG_321
Name: IMEM_SRAM_REG_321
Address: 321 (141h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Number of samples required to enter low-g state.
Unit: time in samples number
7:0 LOWG_TIME_TH[15:8]
Range: [1 - 300]
Default: 13 (set for default ODR = 800 Hz, equivalent to 16 ms)

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18.76 IMEM_SRAM_REG_392
Name: IMEM_SRAM_REG_392
Address: 392 (188h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Minimum duration for which the device should be tilted before signaling
event.
7:0 TILT_WAIT_TIME[7:0]
Unit: time in sample number
Range: [0 - 65536]
Default: 200 for ODR = 50Hz, 100 for ODR = 25Hz

18.77 IMEM_SRAM_REG_393
Name: IMEM_SRAM_REG_393
Address: 393 (189h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Minimum duration for which the device should be tilted before signaling
event.
7:0 TILT_WAIT_TIME[15:8]
Unit: time in sample number
Range: [0 - 65536]
Default: 200 for ODR = 50Hz, 100 for ODR = 25Hz

18.78 IMEM_SRAM_REG_400
Name: IMEM_SRAM_REG_400
Address: 400 (190h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Size of the analysis window to detect tap events (single-tap or double-tap)
unit: time in sample number
7:0 TAP_TMAX[7:0]
range: [49 – 496]
default: 99 (set for default ODR = 200Hz, equivalent to. 0.5s)

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18.79 IMEM_SRAM_REG_401
Name: IMEM_SRAM_REG_401
Address: 401 (191h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Size of the analysis window to detect tap events (single-tap or double-tap)
unit: time in sample number
7:0 TAP_TMAX[15:8]
range: [49 – 496]
default: 99 (set for default ODR = 200Hz, equivalent to. 0.5s)

18.80 IMEM_SRAM_REG_402
Name: IMEM_SRAM_REG_402
Address: 402 (192h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Single tap window, sub-windows within Tmax to detect single-tap event.
Unit: time in sample number
7:0 TAP_TMIN
Range: [24 – 184]
Default: 33 (set for default ODR = 200Hz, equivalent to. 0.165s)

18.81 IMEM_SRAM_REG_403
Name: IMEM_SRAM_REG_403
Address: 403 (193h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
The minimal value of jerk to be considered as a tap candidate.
Unit: g in q6
7:0 TAP_MIN_JERKRange: [0 - 64]
Default: 17

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18.82 IMEM_SRAM_REG_404
Name: IMEM_SRAM_REG_404
Address: 404 (194h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Max acceptable number of samples (jerk value) over TAP_MAX_PEAK_TOL
during the Tmin window. Over this value, Tap event is rejected
TAP_SMUDGE_REJECT_TH
7:0
unit: time in number of samples
R
range: [13 – 92]
Default: 17 (set for default ODR = 200Hz, equivalent to 0.085s)

18.83 IMEM_SRAM_REG_405
Name: IMEM_SRAM_REG_405
Address: 405 (195h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Maximum peak tolerance is the percentage of pulse amplitude to get thesmudge threshold for rejection.
7:0 TAP_MAX_PEAK_TOL
Range: [1 (12.5%) 2 (25.0%) 3 (37.5%) 4 (50.0 %)]Default: 2
Default: 17

18.84 IMEM_SRAM_REG_406
Name: IMEM_SRAM_REG_406
Address: 406 (196h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Energy measurement window size to determine the tap axis associated withthe 1st tap.
7:0 TAP_TAVG
Unit: time in sample number
Range: [1 ; 2 ; 4 ; 8]
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18.85 IMEM_SRAM_REG_540
Name: IMEM_SRAM_REG_540
Address: 540 (21Ch)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Defines the duration after wake event to report sleep event no matter if
position changes or not.
R2W_SLEEP_TIME_OUT[7:7:0
Unit: time in ms (millisecond)0]
Range: [100 - 10000]
Default: 640 (equivalent to 0.64s)

18.86 IMEM_SRAM_REG_541
Name: IMEM_SRAM_REG_541
Address: 541 (21Dh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Defines the duration after wake event to report sleep event no matter if
position changes or not.
R2W_SLEEP_TIME_OUT[157:0
Unit: time in ms (millisecond):8]
Range: [100 - 10000]
Default: 640 (equivalent to 0.64s)

18.87 IMEM_SRAM_REG_542
Name: IMEM_SRAM_REG_542
Address: 542 (21Eh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Defines the duration after wake event to report sleep event no matter if
position changes or not.
R2W_SLEEP_TIME_OUT[237:0
Unit: time in ms (millisecond):16]
Range: [100 - 10000]
Default: 640 (equivalent to 0.64s)

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18.88 IMEM_SRAM_REG_543
Name: IMEM_SRAM_REG_543
Address: 543 (21Fh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Defines the duration after wake event to report sleep event no matter if
position changes or not.
R2W_SLEEP_TIME_OUT[317:0
Unit: time in ms (millisecond):24]
Range: [100 - 10000]
Default: 640 (equivalent to 0.64s)

18.89 IMEM_SRAM_REG_544
Name: IMEM_SRAM_REG_544
Address: 544 (220h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Defines the minimal duration of sleep position before trigger the sleep
event.
R2W_SLEEP_GESTURE_DEL
7:0
Unit: time in ms (millisecond)
AY[7:0]Range: [0 - 256]
Default: 96 (equivalent to 0.096s)

18.90 IMEM_SRAM_REG_545
Name: IMEM_SRAM_REG_545
Address: 545 (221h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Defines the minimal duration of sleep position before trigger the sleep
event.
R2W_SLEEP_GESTURE_DEL
7:0
Unit: time in ms (millisecond)
AY[15:8]
Range: [0 - 256]
Default: 96 (equivalent to 0.096s)

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18.91 IMEM_SRAM_REG_546
Name: IMEM_SRAM_REG_546
Address: 546 (222h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Defines the minimal duration of sleep position before trigger the sleep
event.
R2W_SLEEP_GESTURE_DEL
7:0
Unit: time in ms (millisecond)
AY[23:16]
Range: [0 - 256]
Default: 96 (equivalent to 0.096s)

18.92 IMEM_SRAM_REG_547
Name: IMEM_SRAM_REG_547
Address: 547 (223h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Defines the minimal duration of sleep position before trigger the sleep
event.
R2W_SLEEP_GESTURE_DEL
7:0
Unit: time in ms (millisecond)
AY[31:24]
Range: [0 - 256]
Default: 96 (equivalent to 0.096s)

18.93 IMEM_SRAM_REG_548
Name: IMEM_SRAM_REG_548
Address: 548 (224h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Mounting matrix to rotate data from chip frame to device frame.
Range: 3 lower bits only are used [b2 b1 b0]:
R2W_MOUNTING_MATRIX - b2 = 1 swap X and Y
7:0
[7:0]
- b1 = 1 flip X sign
- b0 = 1 flip Y sign
Default: 0 (device frame aligned with android frame)

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18.94 IMEM_SRAM_REG_549
Name: IMEM_SRAM_REG_549
Address: 549 (225h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Mounting matrix to rotate data from chip frame to device frame.
Range: 3 lower bits only are used [b2 b1 b0]:
R2W_MOUNTING_MATRIX - b2 = 1 swap X and Y
7:0[15:8]- b1 = 1 flip X sign
- b0 = 1 flip Y sign
Default: 0 (device frame aligned with android frame)

18.95 IMEM_SRAM_REG_550
Name: IMEM_SRAM_REG_550
Address: 550 (226h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Mounting matrix to rotate data from chip frame to device frame.
Range: 3 lower bits only are used [b2 b1 b0]:
R2W_MOUNTING_MATRIX - b2 = 1 swap X and Y
7:0[23:16]- b1 = 1 flip X sign
- b0 = 1 flip Y sign
Default: 0 (device frame aligned with android frame)

18.96 IMEM_SRAM_REG_551
Name: IMEM_SRAM_REG_551
Address: 551 (227h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Mounting matrix to rotate data from chip frame to device frame.
Range: 3 lower bits only are used [b2 b1 b0]:
R2W_MOUNTING_MATRIX - b2 = 1 swap X and Y
7:0[31:24]- b1 = 1 flip X sign
- b0 = 1 flip Y sign
Default: 0 (device frame aligned with android frame)

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18.97 IMEM_SRAM_REG_556
Name: IMEM_SRAM_REG_556
Address: 556 (22Ch)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Gain used to filter the accelerometer to obtain an estimation of the gravity(low-pass filter), defined as: forgetting factor = Gain * SAMPLING_PERIOD /R2W_GRAVITY_FILTER_GAI
7:0(40 * 32), and 100Hz.
N[7:0]
Range: [2-16]
Default: 6 for ODR = 50Hz, 8 for ODR = 25Hz

18.98 IMEM_SRAM_REG_557
Name: IMEM_SRAM_REG_557
Address: 557 (22Dh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Gain used to filter the accelerometer to obtain an estimation of the gravity(low-pass filter), defined as: forgetting factor = Gain * SAMPLING_PERIOD /R2W_GRAVITY_FILTER_GAI
7:0(40 * 32), and 100Hz.
N[15:8]Range: [2-16]
Default: 6 for ODR = 50Hz, 8 for ODR = 25Hz

18.99 IMEM_SRAM_REG_558
Name: IMEM_SRAM_REG_558
Address: 558 (22Eh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Gain used to filter the accelerometer to obtain an estimation of the gravity(low-pass filter), defined as: forgetting factor = Gain * SAMPLING_PERIOD /R2W_GRAVITY_FILTER_GAI
7:0(40 * 32), and 100Hz.
N[23:16]
Range: [2-16]
Default: 6 for ODR = 50Hz, 8 for ODR = 25Hz

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ICM-45605
18.100 IMEM_SRAM_REG_559
Name: IMEM_SRAM_REG_559
Address: 559 (22Fh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Gain used to filter the accelerometer to obtain an estimation of the gravity(low-pass filter), defined as: forgetting factor = Gain * SAMPLING_PERIOD /R2W_GRAVITY_FILTER_GAI
7:0(40 * 32), and 100Hz.
N[31:24]
Range: [2-16]
Default: 6 for ODR = 50Hz, 8 for ODR = 25Hz

18.101 IMEM_SRAM_REG_560
Name: IMEM_SRAM_REG_560
Address: 560 (230h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Set the minimal angle that needed to be applied to device to detect R2W
Unit: fixed point value q30 of cosine of the angle
R2W_MOTION_THR_ANGL
7:0
Range: [130856211 - 1069655912], corresponding to angle between 5 and
E_COSINE[7:0]
85 degrees
Default: 1046221864, corresponding to an angle of 13 degrees

18.102 IMEM_SRAM_REG_561
Name: IMEM_SRAM_REG_561
Address: 561 (231h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Set the minimal angle that needed to be applied to device to detect R2W
Unit: fixed point value q30 of cosine of the angle
R2W_MOTION_THR_ANGL
7:0
Range: [130856211 - 1069655912], corresponding to angle between 5 and
E_COSINE[15:8]
85 degrees
Default: 1046221864, corresponding to an angle of 13 degrees

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ICM-45605
18.103 IMEM_SRAM_REG_562
Name: IMEM_SRAM_REG_562
Address: 562 (232h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Set the minimal angle that needed to be applied to device to detect R2W
Unit: fixed point value q30 of cosine of the angle
R2W_MOTION_THR_ANGL
7:0
Range: [130856211 - 1069655912], corresponding to angle between 5 and
E_COSINE[23:16]
85 degrees
Default: 1046221864, corresponding to an angle of 13 degrees

18.104 IMEM_SRAM_REG_563
Name: IMEM_SRAM_REG_563
Address: 563 (233h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Set the minimal angle that needed to be applied to device to detect R2W
Unit: fixed point value q30 of cosine of the angle
R2W_MOTION_THR_ANGL
7:0
Range: [130856211 - 1069655912], corresponding to angle between 5 and
E_COSINE[31:24]
85 degrees
Default: 1046221864, corresponding to an angle of 13 degrees

18.105 IMEM_SRAM_REG_564
Name: IMEM_SRAM_REG_564
Address: 564 (234h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Timer relative to the rapidity of the algorithm to trigger wake up when theorientation before motion is Y axis up (with less than 30 degrees of
R2W_MOTION_THR_TIME
inclination).
7:0
R_FAST[7:0]
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
Range: [100 - 500]
Default: 240

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18.106 IMEM_SRAM_REG_565
Name: IMEM_SRAM_REG_565
Address: 565 (235h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Timer relative to the rapidity of the algorithm to trigger wake up when theorientation before motion is Y axis up (with less than 30 degrees of
R2W_MOTION_THR_TIME
inclination).
7:0
R_FAST[15:8]
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
Range: [100 - 500]
Default: 240

18.107 IMEM_SRAM_REG_566
Name: IMEM_SRAM_REG_566
Address: 566 (236h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Timer relative to the rapidity of the algorithm to trigger wake up when theorientation before motion is Y axis up (with less than 30 degrees of
R2W_MOTION_THR_TIME
inclination).
7:0
R_FAST[23:16]
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
Range: [100 - 500]
Default: 240

18.108 IMEM_SRAM_REG_567
Name: IMEM_SRAM_REG_567
Address: 567 (237h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Timer relative to the rapidity of the algorithm to trigger wake up when theorientation before motion is Y axis up (with less than 30 degrees of
R2W_MOTION_THR_TIME
inclination).
7:0
R_FAST[31:24]
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
Range: [100 - 500]
Default: 240

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18.109 IMEM_SRAM_REG_568
Name: IMEM_SRAM_REG_568
Address: 568 (238h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Timer relative to the rapidity of the algorithm to trigger wake up when theorientation before motion is Y axis up (with less than 30 degrees of
R2W_MOTION_THR_TIME
inclination).
7:0
R_SLOW[7:0]
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
Range: [100 - 500]
Default: 240

18.110 IMEM_SRAM_REG_569
Name: IMEM_SRAM_REG_569
Address: 569 (239h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Timer relative to the rapidity of the algorithm to trigger wake up when theorientation before motion is Y axis up (with less than 30 degrees of
R2W_MOTION_THR_TIME
inclination).
7:0
R_SLOW[15:8]
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
Range: [100 - 500]
Default: 240

18.111 IMEM_SRAM_REG_570
Name: IMEM_SRAM_REG_570
Address: 570 (23Ah)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Timer relative to the rapidity of the algorithm to trigger wake up when theorientation before motion is Y axis up (with less than 30 degrees of
R2W_MOTION_THR_TIME
inclination).
7:0
R_SLOW[23:16]
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
Range: [100 - 500]
Default: 240

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18.112 IMEM_SRAM_REG_571
Name: IMEM_SRAM_REG_571
Address: 571 (23Bh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Timer relative to the rapidity of the algorithm to trigger wake up when theorientation before motion is Y axis up (with less than 30 degrees of
R2W_MOTION_THR_TIME
inclination).
7:0
R_SLOW[31:24]
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
Range: [100 - 500]
Default: 240

18.113 IMEM_SRAM_REG_572
Name: IMEM_SRAM_REG_572
Address: 572 (23Ch)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time delay to update internal value of previous gravity when no motion isdetected.
R2W_MOTION_PREV_GRA Longer time enables detection motion during slower gesture.
7:0
VITY_TIMEOUT[7:0]
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
Range: [100 - 1000]
Default: 300

18.114 IMEM_SRAM_REG_573
Name: IMEM_SRAM_REG_573
Address: 573 (23Dh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time delay to update internal value of previous gravity when no motion isdetected.
R2W_MOTION_PREV_GRA Longer time enables detection motion during slower gesture.
7:0
VITY_TIMEOUT[15:8]
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
Range: [100 - 1000]
Default: 300

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18.115 IMEM_SRAM_REG_574
Name: IMEM_SRAM_REG_574
Address: 574 (23Eh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time delay to update internal value of previous gravity when no motion isdetected.
R2W_MOTION_PREV_GRA Longer time enables detection motion during slower gesture.
7:0
VITY_TIMEOUT[23:16]
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
Range: [100 - 1000]
Default: 300

18.116 IMEM_SRAM_REG_575
Name: IMEM_SRAM_REG_575
Address: 575 (23Fh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time delay to update internal value of previous gravity when no motion isdetected.
R2W_MOTION_PREV_GRA Longer time enables detection motion during slower gesture.
7:0
VITY_TIMEOUT[31:24]
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
Range: [100 - 1000]
Default: 300

18.117 IMEM_SRAM_REG_576
Name: IMEM_SRAM_REG_576
Address: 576 (240h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time delay to update the current gravity estimator when no motion isdetected.
R2W_LAST_GRAVITY_MOT
7:0
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
ION_TIMER[7:0]
Range: [100 - 1000]
Default: 480

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18.118 IMEM_SRAM_REG_577
Name: IMEM_SRAM_REG_577
Address: 577 (241h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time delay to update the current gravity estimator when no motion isdetected.
R2W_LAST_GRAVITY_MOT
7:0
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
ION_TIMER[15:8]
Range: [100 - 1000]
Default: 480

18.119 IMEM_SRAM_REG_578
Name: IMEM_SRAM_REG_578
Address: 578 (242h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time delay to update the current gravity estimator when no motion isdetected.
R2W_LAST_GRAVITY_MOT
7:0
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
ION_TIMER[23:16]
Range: [100 - 1000]
Default: 480

18.120 IMEM_SRAM_REG_579
Name: IMEM_SRAM_REG_579
Address: 579 (243h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time delay to update the current gravity estimator when no motion isdetected.
R2W_LAST_GRAVITY_MOT
7:0
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
ION_TIMER[31:24]
Range: [100 - 1000]
Default: 480

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18.121 IMEM_SRAM_REG_580
Name: IMEM_SRAM_REG_580
Address: 580 (244h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time delay to update gravity in case motion is detected all the time, force toupdate gravity estimator even if the device is not stable.
R2W_LAST_GRAVITY_TIME
7:0
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
OUT[7:0]Range: [1000 - 10000]
Default: 2600

18.122 IMEM_SRAM_REG_581
Name: IMEM_SRAM_REG_581
Address: 581 (245h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time delay to update gravity in case motion is detected all the time, force toupdate gravity estimator even if the device is not stable.
R2W_LAST_GRAVITY_TIME
7:0
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
OUT[15:8]
Range: [1000 - 10000]
Default: 2600

18.123 IMEM_SRAM_REG_582
Name: IMEM_SRAM_REG_582
Address: 582 (246h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time delay to update gravity in case motion is detected all the time, force toupdate gravity estimator even if the device is not stable.
R2W_LAST_GRAVITY_TIME
7:0
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
OUT[23:16]
Range: [1000 - 10000]
Default: 2600

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18.124 IMEM_SRAM_REG_583
Name: IMEM_SRAM_REG_583
Address: 583 (247h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Time delay to update gravity in case motion is detected all the time, force toupdate gravity estimator even if the device is not stable.
R2W_LAST_GRAVITY_TIME
7:0
Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
OUT[31:24]
Range: [1000 - 10000]
Default: 2600

18.125 IMEM_SRAM_REG_584
Name: IMEM_SRAM_REG_584
Address: 584 (248h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
If gesture is not completed in this timeout limit, gesture is invalid.
R2W_GESTURE_VALIDITY_ Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
7:0
TIMEOUT[7:0]
Range: [100 - 1000]
Default: 240

18.126 IMEM_SRAM_REG_585
Name: IMEM_SRAM_REG_585
Address: 585 (249h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
If gesture is not completed in this timeout limit, gesture is invalid.
R2W_GESTURE_VALIDITY_ Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
7:0
TIMEOUT[15:8]
Range: [100 - 1000]
Default: 240

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18.127 IMEM_SRAM_REG_586
Name: IMEM_SRAM_REG_586
Address: 586 (24Ah)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
If gesture is not completed in this timeout limit, gesture is invalid.
R2W_GESTURE_VALIDITY_ Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
7:0
TIMEOUT[23:16]
Range: [100 - 1000]
Default: 240

18.128 IMEM_SRAM_REG_587
Name: IMEM_SRAM_REG_587
Address: 587 (24Bh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
If gesture is not completed in this timeout limit, gesture is invalid.
R2W_GESTURE_VALIDITY_ Unit: ms (no dependency on ODR, it is managed internally by the algorithm)
7:0
TIMEOUT[31:24]
Range: [100 - 1000]
Default: 240

18.129 IMEM_SRAM_REG_988
Name: IMEM_SRAM_REG_988
Address: 988 (3DCh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Minimum number of steps that must be detected before step count isincremented.
Low values reduce latency but increase false positives.
7:0 PED_STEP_CNT_TH[7:0]High values increase step count accuracy but increase latency
Unit: Number of steps
Range: [0-15]
Default: 5Page 140 of 191
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18.130 IMEM_SRAM_REG_989
Name: IMEM_SRAM_REG_989
Address: 989 (3DDh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Minimum number of steps that must be detected before step count isincremented.
Low values reduce latency but increase false positives.
7:0 PED_STEP_CNT_TH[15:8]
High values increase step count accuracy but increase latency
Unit: Number of steps
Range: [0-15]
Default: 518.131 IMEM_SRAM_REG_990
Name: IMEM_SRAM_REG_990
Address: 990 (3DEh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Minimum number of steps that must be detected before step event issignaled.
Low values reduce latency but increase false positives.
7:0 PED_STEP_DET_TH[7:0]High values increase step event validity but increase latency.
Unit: number of steps
Range: [0-7]Default: 2

18.132 IMEM_SRAM_REG_991
Name: IMEM_SRAM_REG_991
Address: 991 (3DFh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Minimum number of steps that must be detected before step event issignaled.
Low values reduce latency but increase false positives.
7:0 PED_STEP_DET_TH[15:8]
High values increase step event validity but increase latency.
Unit: number of steps
Range: [0-7]Default: 2

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18.133 IMEM_SRAM_REG_994
Name: IMEM_SRAM_REG_994
Address: 994 (3E2h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
While in the step buffer state, the step buffer count resets to 0 if a new step
isn't detected for this amount of time (user is considered to have "stopped
walking").
7:0 PED_SB_TIMER_TH[7:0]
Unit: time in samples number
Range: [0 - 225]
Default: 150 for ODR = 50Hz

18.134 IMEM_SRAM_REG_995
Name: IMEM_SRAM_REG_995
Address: 995 (3E3h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
While in the step buffer state, the step buffer count resets to 0 if a new step
isn't detected for this amount of time (user is considered to have "stopped
walking").
7:0 PED_SB_TIMER_TH[15:8]
Unit: time in samples number
Range: [0 - 225]
Default: 150 for ODR = 50Hz

18.135 IMEM_SRAM_REG_1000
Name: IMEM_SRAM_REG_1000
Address: 1000 (3E8h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold to select a valid step. Used to increase step detection for slow
walk use case only.
PED_LOW_EN_AMP_TH[7:7:0
Unit: g in q25.
0]
Range: [1006632 - 3523215]
Default: 2684354

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18.136 IMEM_SRAM_REG_1001
Name: IMEM_SRAM_REG_1001
Address: 1001 (3E9h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold to select a valid step. Used to increase step detection for slow
walk use case only.
PED_LOW_EN_AMP_TH[157:0
Unit: g in q25.
:8]
Range: [1006632 - 3523215]
Default: 2684354

18.137 IMEM_SRAM_REG_1002
Name: IMEM_SRAM_REG_1002
Address: 1002 (3EAh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold to select a valid step. Used to increase step detection for slow
walk use case only.
PED_LOW_EN_AMP_TH[237:0
Unit: g in q25.
:16]
Range: [1006632 - 3523215]
Default: 2684354

18.138 IMEM_SRAM_REG_1003
Name: IMEM_SRAM_REG_1003
Address: 1003 (3EBh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold to select a valid step. Used to increase step detection for slow
walk use case only.
PED_LOW_EN_AMP_TH[317:0
Unit: g in q25.
:24]
Range: [1006632 - 3523215]
Default: 2684354

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18.139 IMEM_SRAM_REG_1004
Name: IMEM_SRAM_REG_1004
Address: 1004 (3ECh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Pedometer sensitivity mode.
Slow walk mode improves slow walk detection (<1 Hz) but the number of
7:0 PED_SENSITIVITY_MODE
false positives may increase
Range: 0: Normal 1: Slow walkDefault: 0

18.140 IMEM_SRAM_REG_1008
Name: IMEM_SRAM_REG_1008
Address: 1008 (3F0h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold of step detection sensitivity.
Low values increase detection sensitivity: reduce miss-detection.
High values reduce detection sensitivity: reduce false-positive.
7:0 PED_AMP_TH[7:0]
Unit: g in q25.
Range: [1006632 - 3019898]
Default: 2080374

18.141 IMEM_SRAM_REG_1009
Name: IMEM_SRAM_REG_1009
Address: 1009 (3F1h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold of step detection sensitivity.
Low values increase detection sensitivity: reduce miss-detection.
High values reduce detection sensitivity: reduce false-positive.
7:0 PED_AMP_TH[15:8]
Unit: g in q25.
Range: [1006632 - 3019898]
Default: 2080374

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18.142 IMEM_SRAM_REG_1010
Name: IMEM_SRAM_REG_1010
Address: 1010 (3F2h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold of step detection sensitivity.
Low values increase detection sensitivity: reduce miss-detection.
High values reduce detection sensitivity: reduce false-positive.
7:0 PED_AMP_TH[23:16]
Unit: g in q25.
Range: [1006632 - 3019898]
Default: 2080374

18.143 IMEM_SRAM_REG_1011
Name: IMEM_SRAM_REG_1011
Address: 1011 (3F3h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold of step detection sensitivity.
Low values increase detection sensitivity: reduce miss-detection.
High values reduce detection sensitivity: reduce false-positive.
7:0 PED_AMP_TH[31:24]
Unit: g in q25.
Range: [1006632 - 3019898]
Default: 2080374

18.144 IMEM_SRAM_REG_1016
Name: IMEM_SRAM_REG_1016
Address: 1016 (3F8h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold to classify acceleration signal as motion not due to steps
High values improve vibration rejection.
Low values improve detection.
7:0 PED_HI_EN_TH[7:0]
Unit: g in q25.
Range: [2949120 - 5210112]
Default: 3506176

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18.145 IMEM_SRAM_REG_1017
Name: IMEM_SRAM_REG_1017
Address: 1017 (3F9h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold to classify acceleration signal as motion not due to steps
High values improve vibration rejection.
Low values improve detection.
7:0 PED_HI_EN_TH[15:8]
Unit: g in q25.
Range: [2949120 - 5210112]
Default: 3506176

18.146 IMEM_SRAM_REG_1018
Name: IMEM_SRAM_REG_1018
Address: 1018 (3FAh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold to classify acceleration signal as motion not due to steps
High values improve vibration rejection.
Low values improve detection.
7:0 PED_HI_EN_TH[23:16]
Unit: g in q25.
Range: [2949120 - 5210112]
Default: 3506176

18.147 IMEM_SRAM_REG_1019
Name: IMEM_SRAM_REG_1019
Address: 1019 (3FBh)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Threshold to classify acceleration signal as motion not due to steps
High values improve vibration rejection.
Low values improve detection.
7:0 PED_HI_EN_TH[31:24]
Unit: g in q25.
Range: [2949120 - 5210112]
Default: 3506176

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ICM-45605
18.148 IMEM_SRAM_REG_1042
Name: IMEM_SRAM_REG_1042
Address: 1042 (412h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
Parameter to tune SMD algorithm robustness to rejection, ranging from 0 to
4 (values higher than 4 are reserved).
Low values increase detection rate but increase false positives.
7:0 SMD_SENSITIVITYHigh values reduce false positives but reduce detection rate (especially fortransport use cases).
Range: [0 - 4]
Default: 0

18.149 IMEM_SRAM_REG_1168 TO IMEM_SRAM_REG_1203
Name: IMEM_SRAM_REG_1168 to IMEM_SRAM_REG_1203
Address: 1168 to 1203 (490h to 4B3h)
Serial IF: R/W
Reset value: Random value after reset until host runs EDMP_INIT procedure
Clock Domain: MCLKBIT NAME
FUNCTION
SOFT_IRON_SENSITIVITY_
7:0
Input 3x3 calibration matrix in q14 format applied to uncalibrated data.
MATRIX[287:0]

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ICM-45605
19 USER BANK IPREG_BAR REGISTER MAP – DESCRIPTIONSThis section describes the function and contents of each register within user bank IPREG_BAR. The registers
described in this section are indirect access registers. Section 13 describes the procedure for accessing indirectaccess registers.

19.1

IPREG_BAR_REG_57

Name: IPREG_BAR_REG_57
Address: 57 (39h)Serial IF: R/W
Reset value: 0x33
Clock Domain: MCLKBIT NAME
76

IO_OPT0

FUNCTION
Reserved
Set this register field to 1 for optimal speed of IOs.
IO_OPT1 must be also set to 1 if IO_OPT0 is set to 1.
Can be changed on-the-fly.
Set this register field to 1 for optimal speed of IOs.

5

IO_OPT1

4:0-

Can be changed on-the-fly.
Reserved

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ICM-45605
19.2

IPREG_BAR_REG_58

Name: IPREG_BAR_REG_58
Address: 58 (3Ah)
Serial IF: R/W
Reset value: 0xD9
Clock Domain: MCLKBIT NAME

7

PADS_AP_SCLK_PUD_TRIM_D2A

FUNCTION
Selects internal resistor pull direction for AP_SCLK pin (pin 13)
0: Down
1: Up
Can be changed on-the-fly.
Enables internal pull resistor to pull up or down for AP_SCLK pin (pin 13),depending on direction selected by bit 7.

6

PADS_AP_SCLK_PE_TRIM_
D2A

5

-

Can be changed on-the-fly.
Reserved
Selects internal resistor pull direction for AP_CS pin (pin 12)

4

PADS_AP_CS_PUD_TRIM_
D2A

0: Down
1: Up

0: Not enabled
1: Enabled

Can be changed on-the-fly.
Enables internal pull resistor to pull up or down for AP_CS pin (pin 12),depending on direction selected by bit 4.
3

PADS_AP_CS_PE_TRIM_D2
A

2:1

-

0

IO_OPT2

0: Not enabled
1: Enabled
Can be changed on-the-fly.
Reserved
Set this register field to 1 for optimal speed of IOs.
IO_OPT1 must be also set to 1 if IO_OPT2 is set to 1
Can be changed on-the-fly.

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ICM-45605
19.3

IPREG_BAR_REG_59

Name: IPREG_BAR_REG_59
Address: 59 (3Bh)
Serial IF: R/W
Reset value: 0xB6
Clock Domain: MCLKBIT NAME

FUNCTION
Enables internal pull resistor to pull up or down for pin 7, depending on
direction selected by bit 0 of register IPREG_BAR_REG_60

7

PADS_PIN7_PE_TRIM_D2A

0: Not enabled
1: Enabled

6-

Can be changed on-the-fly.
Reserved
Selects internal resistor pull direction for AP_SDO pin (pin 1)

5

PADS_AP_SDO_PUD_TRIM_D2A

0: Down
1: Up
Can be changed on-the-fly.
Enables internal pull resistor to pull up or down for AP_SDO pin (pin 1),
depending on direction selected by bit 5.

4

PADS_AP_SDO_PE_TRIM_
D2A

3

-

Can be changed on-the-fly.
Reserved
Selects internal resistor pull direction for AP_SDI pin (pin 14)2

PADS_AP_SDI_PUD_TRIM_
D2A

0: Down
1: Up

0: Not enabled
1: Enabled

Can be changed on-the-fly.
Enables internal pull resistor to pull up or down for AP_SDI pin (pin 14),depending on direction selected by bit 2.
1

PADS_AP_SDI_PE_TRIM_D
2A

0

-

0: Not enabled
1: Enabled
Can be changed on-the-fly.
Reserved

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ICM-45605
19.4

IPREG_BAR_REG_60

Name: IPREG_BAR_REG_60
Address: 60 (3Ch)
Serial IF: R/W
Reset value: 0x6D
Clock Domain: MCLKBIT NAME
7-

6

PADS_AUX1_SCLK_PUD_TR
IM_D2AFUNCTION
Reserved
Enables internal pull resistor to pull up or down for AUX1_SCLK pin (pin 3),
depending on direction selected by bit 5.
0: Not enabled
1: Enabled
Can be changed on-the-fly.
Selects internal resistor pull direction for AUX1_SCLK pin (pin 3)

5

PADS_AUX1_SCLK_PE_TRI
M_D2A

4

PADS_AUX_SCLK_TP2_FRO
M_PAD_DISABLE_TRIM_D
2A

0: Down
1: Up
Can be changed on-the-fly.
Set this bit to 1 if using I2C master mode. Set it to 0 otherwise.
Enables internal pull resistor to pull up or down for AUX1_CS pin (pin 10),depending on direction selected by bit 2.

3

PADS_AUX1_CS_PUD_TRI
M_D2A

0: Not enabled
1: Enabled
Can be changed on-the-fly.
Selects internal resistor pull direction for AUX1_CS pin (pin 10)

PADS_AUX1_CS_PE_TRIM_
D2A

0: Down
1: Up

1

-

Can be changed on-the-fly.
Reserved
Selects internal resistor pull direction for pin 70

PADS_PIN7_CS_PUD_TRIM_D2A

0: Down
1: Up

2Can be changed on-the-fly.

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ICM-45605
19.5

IPREG_BAR_REG_61

Name: IPREG_BAR_REG_61
Address: 61 (3Dh)
Serial IF: R/W
Reset value: 0xBB
Clock Domain: MCLKBIT NAME

7

PADS_INT1_PUD_TRIM_D2
A

FUNCTION
Enables internal pull resistor to pull up or down for INT1 pin (pin 4),
depending on direction selected by bit 6.
0: Not enabled
1: Enabled
Can be changed on-the-fly.
Selects internal resistor pull direction for INT1 pin (pin 4)

6

PADS_INT1_PE_TRIM_D2A

0: Down
1: Up

5

-

Can be changed on-the-fly.
Reserved
Selects internal resistor pull direction for AUX1_SDO pin (pin 11)

4

PADS_AUX1_SDO_PUD_TR
IM_D2A

0: Down
1: Up
Can be changed on-the-fly.
Enables internal pull resistor to pull up or down for AUX1_SDO pin (pin 11),depending on direction selected by bit 4.

3

PADS_AUX1_SDO_PE_TRI
M_D2A

2

-

1

PADS_AUX1_SDI_PUD_TRI
M_D2A

0: Not enabled
1: Enabled
Can be changed on-the-fly.
Reserved
Enables internal pull resistor to pull up or down for AUX1_SDI pin (pin 2),
depending on direction selected by bit 0.
0: Not enabled
1: Enabled
Can be changed on-the-fly.
Selects internal resistor pull direction for AUX1_SDI pin (pin 2)

0

PADS_AUX1_SDI_PE_TRIM_D2A

0: Down
1: Up
Can be changed on-the-fly.

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ICM-45605
19.6

IPREG_BAR_REG_62

Name: IPREG_BAR_REG_62
Address: 62 (3Eh)
Serial IF: R/W
Reset value: 0x06
Clock Domain: MCLKBIT NAME
7:3 -2

PADS_INT2_PUD_TRIM_D2
A

FUNCTION
Reserved
Selects internal resistor pull direction for INT2 pin (pin 9)
0: Down
1: Up
Can be changed on-the-fly.
Enables internal pull resistor to pull up or down for INT2 pin (pin 9),
depending on direction selected by bit 2.

1

PADS_INT2_PE_TRIM_D2A

0-

0: Not enabled
1: Enabled
Can be changed on-the-fly.
Reserved

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ICM-45605
20 USER BANK IPREG_TOP1 REGISTER MAP – DESCRIPTIONSThis section describes the function and contents of each register within user bank IPREG_TOP1. The registers
described in this section are indirect access registers. Section 13 describes the procedure for accessing indirectaccess registers.

20.1

I2CM_COMMAND_0

Name: I2CM_COMMAND_0 (I2C master command buffer 0)
Address: 06 (06h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
FUNCTION
Indicates if the current entry is the last I2C master communication with the
7
ENDFLAG_0
external slave device.
Specifies the channel number for I2C master transaction.

6

CH_SEL_0

Two external sensors are supported.
0: Specify one external sensor with device ID “ID1”
1: Specify the other external sensor with device ID “ID2”“ID1” and “ID2” should be replaced by the actual device ID of the chosen
external devices.
I2C master read/write command.

5:4

3:0

R_W_0

BURSTLEN_0

00: Write operation
01: Read operation with register address specified
10: Read operation without register address specified
11: Reserved
Specifies the burst length of I2C master communication with the externalslave device.
0000: Reserved
0001: 1 byte
0010: 2 bytes
0011: 3 bytes
0100: 4 bytes
0101: 5 bytes
0110: 6 bytes
0111: 7 bytes
1000: 8 bytes
1001: 9 bytes
1010: 10 bytes
1011: 11 bytes
1100: 12 bytes
1101: 13 bytes
1110: 14 bytes
1111: 15 bytes
Note: For write operation the valid values are 0001 to 0110; For read
operation the valid values are 0001 to 1111.

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ICM-45605
20.2

I2CM_COMMAND_1

Name: I2CM_COMMAND_1 (I2C master command buffer 1)
Address: 07 (07h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
FUNCTION
Indicates if the current entry is the last I2C master communication with the
7
ENDFLAG_1
external slave device.
Specifies the channel number for I2C master transaction.

6

CH_SEL_1

Two external sensors are supported.
0: Specify one external sensor with device ID “ID1”
1: Specify the other external sensor with device ID “ID2”“ID1” and “ID2” should be replaced by the actual device ID of the chosen
external devices.
I2C master read/write command.

5:4

3:0

R_W_1

BURSTLEN_1

00: Write operation
01: Read operation with register address specified
10: Read operation without register address specified
11: Reserved
Specifies the burst length of I2C master communication with the externalslave device.
0000: Reserved
0001: 1 byte
0010: 2 bytes
0011: 3 bytes
0100: 4 bytes
0101: 5 bytes
0110: 6 bytes
0111: 7 bytes
1000: 8 bytes
1001: 9 bytes
1010: 10 bytes
1011: 11 bytes
1100: 12 bytes
1101: 13 bytes
1110: 14 bytes
1111: 15 bytes
Note: For write operation the valid values are 0001 to 0110; For read
operation the valid values are 0001 to 1111.

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20.3

I2CM_COMMAND_2

Name: I2CM_COMMAND_2 (I2C master command buffer 2)
Address: 08 (08h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
FUNCTION
Indicates if the current entry is the last I2C master communication with the
7
ENDFLAG_2
external slave device.
Specifies the channel number for I2C master transaction.

6

CH_SEL_2

Two external sensors are supported.
0: Specify one external sensor with device ID “ID1”
1: Specify the other external sensor with device ID “ID2”“ID1” and “ID2” should be replaced by the actual device ID of the chosen
external devices.
I2C master read/write command.

5:4

3:0

R_W_2

BURSTLEN_2

00: Write operation
01: Read operation with register address specified
10: Read operation without register address specified
11: Reserved
Specifies the burst length of I2C master communication with the externalslave device.
0000: Reserved
0001: 1 byte
0010: 2 bytes
0011: 3 bytes
0100: 4 bytes
0101: 5 bytes
0110: 6 bytes
0111: 7 bytes
1000: 8 bytes
1001: 9 bytes
1010: 10 bytes
1011: 11 bytes
1100: 12 bytes
1101: 13 bytes
1110: 14 bytes
1111: 15 bytes
Note: For write operation the valid values are 0001 to 0110; For read
operation the valid values are 0001 to 1111.

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ICM-45605
20.4

I2CM_COMMAND_3

Name: I2CM_COMMAND_3 (I2C master command buffer 3)
Address: 09 (09h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
FUNCTION
Indicates if the current entry is the last I2C master communication with the
7
ENDFLAG_3
external slave device.
Specifies the channel number for I2C master transaction.

6

CH_SEL_3

Two external sensors are supported.
0: Specify one external sensor with device ID “ID1”
1: Specify the other external sensor with device ID “ID2”“ID1” and “ID2” should be replaced by the actual device ID of the chosen
external devices.
I2C master read/write command.

5:4

3:0

R_W_3

BURSTLEN_3

00: Write operation
01: Read operation with register address specified
10: Read operation without register address specified
11: Reserved
Specifies the burst length of I2C master communication with the externalslave device.
0000: Reserved
0001: 1 byte
0010: 2 bytes
0011: 3 bytes
0100: 4 bytes
0101: 5 bytes
0110: 6 bytes
0111: 7 bytes
1000: 8 bytes
1001: 9 bytes
1010: 10 bytes
1011: 11 bytes
1100: 12 bytes
1101: 13 bytes
1110: 14 bytes
1111: 15 bytes
Note: For write operation the valid values are 0001 to 0110; For read
operation the valid values are 0001 to 1111.

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ICM-45605
20.5

I2CM_DEV_PROFILE0

Name: I2CM_DEV_PROFILE0
Address: 14 (0Eh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0 RD_ADDRESS_0

20.6

I2CM_DEV_PROFILE1

Name: I2CM_DEV_PROFILE1
Address: 15 (0Fh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7
6:0 DEV_ID_0

20.7

FUNCTION
Reserved
Specifies the slave ID for channel 0 I2C master transaction

I2CM_DEV_PROFILE2

Name: I2CM_DEV_PROFILE2
Address: 16 (10h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0 RD_ADDRESS_1

20.8

FUNCTION
Specifies the read address for channel 0 I2C master transaction

FUNCTION
Specifies the read address for channel 1 I2C master transaction

I2CM_DEV_PROFILE3

Name: I2CM_DEV_PROFILE3
Address: 17 (11h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7
6:0 DEV_ID_1

FUNCTION
Reserved
Specifies the slave ID for channel 1 I2C master transaction

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ICM-45605
20.9

I2CM_CONTROL

Name: I2CM_CONTROL
Address: 22 (16h)Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7
6

I2CM_RESTART_EN

5:4

-

3

I2CM_SPEED

2:1

-

0

I2CM_GOFUNCTION
Reserved
0: No Restart is used
1: In an I2C register read transaction, the Restart is used to bridge theregister-address write transaction and register-data read transaction. This bit
is not programmable by MCU when I2CM_BUSY = 1.
Reserved
0: I2C Fast Mode
1: I2C Standard Mode
Reserved
1: Kicks off I2C master operation. Clears to 0 after I2C master operation iscompleted. This bit is not programmable when I2CM_BUSY = 1

20.10 I2CM_STATUS
Name: I2CM_STATUS
Address: 24 (18h)Serial IF: R
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:6 5
I2CM_SDA_ERR
4
I2CM_SCL_ERR
3
I2CM_SRST_ERR
2
I2CM_TIMEOUT_ERR
1

I2CM_DONE

0

I2CM_BUSYFUNCTION
Reserved
I2C master SDA error indication
I2C master SCL error indication
I2C master SRST error indication
I2C master timeout error indication
1: Status bit, indicates I2C master operation has completed, with or without
errors. This bit is cleared due to (a) MCU read or (b) when I2CM_GO is
programmed to 1 or (c) ODR event for fetching sensor data from theexternal sensor.
0: Indicates no I2C master operation is running
1: Indicates I2C master operation is running

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ICM-45605
20.11 I2CM_EXT_DEV_STATUS
Name: I2CM_EXT_DEV_STATUS
Address: 26 (1Ah)
Serial IF: R/C
Reset value: 0x0F
Clock Domain: MCLKBIT NAME
7:4 -FUNCTION
Reserved
Indicates ACK/NACK feedback from the external device per each entry of thecommand buffer. I2CM_EXT_DEV_STATUS is set to 0xF whenever I2C master
operation is kicked off.
Bit 0 of I2CM_EXT_DEV_STATUS: ACK/NACK feedback from the external
device to I2CM_COMMAND_0.
0: ACK
1: NACK

3:0

I2CM_EXT_DEV_STATUS

Bit 1 of I2CM_EXT_DEV_STATUS: ACK/NACK feedback from the external
device to I2CM_COMMAND_1.
0: ACK
1: NACK
Bit 2 of I2CM_EXT_DEV_STATUS: ACK/NACK feedback from the external
device to I2CM_COMMAND_2.
0: ACK
1: NACK
Bit 3 of I2CM_EXT_DEV_STATUS: ACK/NACK feedback from the external
device to I2CM_COMMAND_3.
0: ACK
1: NACK

20.12 I2CM_RD_DATA0
Name: I2CM_RD_DATA0
Address: 27 (1Bh)
Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA0FUNCTION
The 1st byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

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ICM-45605
20.13 I2CM_RD_DATA1
Name: I2CM_RD_DATA1
Address: 28 (1Ch)
Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA1FUNCTION
The 2nd byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

20.14 I2CM_RD_DATA2
Name: I2CM_RD_DATA2
Address: 29 (1Dh)
Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA2FUNCTION
The 3rd byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

20.15 I2CM_RD_DATA3
Name: I2CM_RD_DATA3
Address: 30 (1Eh)
Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA3FUNCTION
The 4th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

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ICM-45605
20.16 I2CM_RD_DATA4
Name: I2CM_RD_DATA4
Address: 31 (1Fh)
Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA4FUNCTION
The 5th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

20.17 I2CM_RD_DATA5
Name: I2CM_RD_DATA5
Address: 32 (20h)Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA5FUNCTION
The 6th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

20.18 I2CM_RD_DATA6
Name: I2CM_RD_DATA6
Address: 33 (21h)Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA6FUNCTION
The 7th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

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ICM-45605
20.19 I2CM_RD_DATA7
Name: I2CM_RD_DATA7
Address: 34 (22h)Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA7FUNCTION
The 8th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

20.20 I2CM_RD_DATA8
Name: I2CM_RD_DATA8
Address: 35 (23h)Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA8FUNCTION
The 9th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

20.21 I2CM_RD_DATA9
Name: I2CM_RD_DATA9Address: 36 (24h)Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA9FUNCTION
The 10th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

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ICM-45605
20.22 I2CM_RD_DATA10
Name: I2CM_RD_DATA10
Address: 37 (25h)Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA10FUNCTION
The 11th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

20.23 I2CM_RD_DATA11
Name: I2CM_RD_DATA11
Address: 38 (26h)Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA11FUNCTION
The 12th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

20.24 I2CM_RD_DATA12
Name: I2CM_RD_DATA12
Address: 39 (27h)Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA12FUNCTION
The 13th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

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ICM-45605
20.25 I2CM_RD_DATA13
Name: I2CM_RD_DATA13
Address: 40 (28h)Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA13FUNCTION
The 14th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

20.26 I2CM_RD_DATA14
Name: I2CM_RD_DATA14
Address: 41 (29h)Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA14FUNCTION
The 15th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

20.27 I2CM_RD_DATA15
Name: I2CM_RD_DATA15
Address: 42 (2Ah)
Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA15FUNCTION
The 16th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

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ICM-45605
20.28 I2CM_RD_DATA16
Name: I2CM_RD_DATA16
Address: 43 (2Bh)
Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA16FUNCTION
The 17th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

20.29 I2CM_RD_DATA17
Name: I2CM_RD_DATA17
Address: 44 (2Ch)
Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA17FUNCTION
The 18th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

20.30 I2CM_RD_DATA18
Name: I2CM_RD_DATA18
Address: 45 (2Dh)
Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA18FUNCTION
The 19th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

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20.31 I2CM_RD_DATA19
Name: I2CM_RD_DATA19
Address: 46 (2Eh)
Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA19FUNCTION
The 20th byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

20.32 I2CM_RD_STATUS20
Name: I2CM_RD_DATA20
Address: 47 (2Fh)
Serial IF: RWS
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

I2CM_RD_DATA20FUNCTION
The 21st byte received from I2C slave.
Content of this register is automatically cleared to 0 when I2CM_GO = 1 orupon ODR event for fetching sensor data from the external sensor.

20.33 I2CM_WR_DATA0
Name: I2CM_WR_DATA0
Address: 51 (33h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0 I2CM_WR_DATA0FUNCTION
The data/address byte for a Write transaction.

20.34 I2CM_WR_DATA1
Name: I2CM_WR_DATA1
Address: 52 (34h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0 I2CM_WR_DATA1FUNCTION
The data/address byte for a Write transaction.

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20.35 I2CM_WR_DATA2
Name: I2CM_WR_DATA2
Address: 53 (35h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0 I2CM_WR_DATA2FUNCTION
The data/address byte for a Write transaction.

20.36 I2CM_WR_DATA3
Name: I2CM_WR_DATA3
Address: 54 (36h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0 I2CM_WR_DATA3FUNCTION
The data/address byte for a Write transaction.

20.37 I2CM_WR_DATA4
Name: I2CM_WR_DATA4
Address: 55 (37h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0 I2CM_WR_DATA4FUNCTION
The data/address byte for a Write transaction.

20.38 I2CM_WR_DATA5
Name: I2CM_WR_DATA5
Address: 56 (38h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0 I2CM_WR_DATA5FUNCTION
The data/address byte for a Write transaction.

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20.39 SIFS_IXC_ERROR_STATUS
Name: SIFS_IXC_ERROR_STATUS
Address: 75 (4Bh)
Serial IF: R/C
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:2 1

AUX1_SIFS_IXC_TIMEOUT_
ERR

0

SIFS_IXC_TIMEOUT_ERR

FUNCTION
Reserved
0: No timeout error.
1: Indicates than an IxC timeout error occurred in AUX1 SIFS. No clock toggle
condition from host for 32ms while an IxC transaction was ongoing (after
START and before STOP).
0: No timeout error or when SPI slave is selected for serial transfers.
1: Indicates than an IxC timeout error occurred in SIFS. No clock toggle
condition from host for 32ms while an IxC transaction was ongoing (after
START and before STOP).

20.40 EDMP_PRGRM_IRQ0_0
Name: EDMP_PRGRM_IRQ0_0
Address: 79 (4Fh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

PRGRM_STRT_ADDR_IRQ_0[7:0]

FUNCTION
Start address of IRQ_0 vector.
Can be changed on-the-fly.

20.41 EDMP_PRGRM_IRQ0_1
Name: EDMP_PRGRM_IRQ0_1
Address: 80 (50h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

PRGRM_STRT_ADDR_IRQ_
0[15:8]FUNCTION
Start address of IRQ_0 vector.
Can be changed on-the-fly.

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20.42 EDMP_PRGRM_IRQ1_0
Name: EDMP_PRGRM_IRQ1_0
Address: 81 (51h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

PRGRM_STRT_ADDR_IRQ_
1[7:0]

FUNCTION
Start address of IRQ_1 vector.
Can be changed on-the-fly.

20.43 EDMP_PRGRM_IRQ1_1
Name: EDMP_PRGRM_IRQ1_1
Address: 82 (52h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

PRGRM_STRT_ADDR_IRQ_
1[15:8]FUNCTION
Start address of IRQ_1 vector.
Can be changed on-the-fly.

20.44 EDMP_PRGRM_IRQ2_0
Name: EDMP_PRGRM_IRQ2_0
Address: 83 (53h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

PRGRM_STRT_ADDR_IRQ_
2[7:0]

FUNCTION
Start address of IRQ_2 vector.
Can be changed on-the-fly.

20.45 EDMP_PRGRM_IRQ2_1
Name: EDMP_PRGRM_IRQ2_1
Address: 84 (54h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

PRGRM_STRT_ADDR_IRQ_
2[15:8]FUNCTION
Start address of IRQ_2 vector.
Can be changed on-the-fly.

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20.46 EDMP_SP_START_ADDR
Name: EDMP_SP_START_ADDR
Address: 85 (55h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

FUNCTION
Sets eDMP stack address.

EDMP_SP_START_ADDR
Can be changed on-the-fly.

20.47 SMC_CONTROL_0
Name: SMC_CONTROL_0
Address: 88 (58h)Serial IF: R/W
Reset value: 0x60
Clock Domain: MCLKBIT NAME
7:5 -FUNCTION
Reserved
This bit is applicable to host interface operation.
A. When RTC mode is not enabled (or RTC_MODE = 0 ):This bit is effective when the host interface is in accel only operation with
ACCEL_MODE set to LP mode.
0: Host interface is in AULP mode.
1: Host interface is in ALP mode.

4

ACCEL_LP_CLK_SEL

When I3CSM Synchronous Timing Control function is enabled on hostinterface, if the host interface is in accel only operation with ACCEL_MODE
set to LP mode, ACCEL_LP_CLK_SEL must be set to 1. I3CSM Synchronous
Timing Control may not generate correct timing if ACCEL_LP_CLK_SEL is set
to 0.
B. When RTC mode is enabled (or RTC_MODE = 1):
Independent of enabling/disabling of I3CSM Synchronous timing control
function, ACCEL_LP_CLK_SEL must be set to 1.

3

TEMP_DIS2

TMST_FORCE_AUX_FINE_E
N

1

TMST_FSYNC_EN

Dynamic Change Supported.
0: Temperature Sensor not disabled.
1: Temperature Sensor disabled.
0: Time Stamp fine counting enabled only on UI interface.
1: Time Stamp fine counting enabled on AUX interfaces in addition to UIinterface.
Time Stamp register FSYNC Enable.
0: Timestamp feature of FSYNC not enabled.

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0

TMST_EN

1: Timestamp feature of FSYNC enabled.
0: Timestamp not enabled.
1: Timestamp enabled.

20.48 SMC_CONTROL_1
Name: SMC_CONTROL_1
Address: 89 (59h)Serial IF: R/W
Reset value: 0x04
Clock Domain: MCLKBIT NAME
7:4 3

SREG_AUX_ACCEL_ONLY_E
N

2:0

-

FUNCTION
Reserved
0: Sensor data register read from AUX1 interface is supported only if gyro
sensor is enabled.
1: Sensor data register read from AUX1 interface is supported even if gyro
sensor is not enabled.
Reserved

20.49 STC_CONFIG
Name: STC_CONFIG
Address: 99 (63h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:4 3:2

STC_SENSOR_SEL

1:0-

FUNCTION
Reserved
Sensor that controls STC:
0 or 1: Slowest ODR sensor
2: Accel
3: GyroReserved

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20.50 SREG_CTRL
Name: SREG_CTRL
Address: 103 (67h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:2 -

1

0

SREG_DATA_ENDIAN_SEL-

FUNCTION
Reserved
Selects Endianness of Sensor Data Registers and FIFO data
0: Sensor data, FIFO data, and FIFO count is in Little Endian format
1: Sensor data, FIFO data, and FIFO count is in Big Endian format
Note: User must set register field SREG_DATA_ENDIAN_SEL to 1, to enable
Big Endian data format for data in Sensor Data Registers and FIFO, and for
FIFO Count.
Reserved

20.51 SIFS_I3C_STC_CFG
Name: SIFS_I3C_STC_CFG
Address: 104 (68h)Serial IF: R/W
Reset value: 0x23
Clock Domain: MCLKBIT NAME
7:3 -

2

1:0

I3C_STC_MODE-

FUNCTION
Reserved
Enable the STC controller
0: Disable I3C STC.
1: Enable I3C STC.
Toggling this bit restarts the ODR frequency and phase correction operation
as if the chip is out of reset.
The STC functionality can be enabled only if ACCEL_LP_CLK_SEL is set to 1;otherwise device may not behave as expected.
Reserved

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20.52 INT_PULSE_MIN_ON_INTF0
Name: INT_PULSE_MIN_ON_INTF0
Address: 105 (69h)Serial IF: R/W
Reset value: 0x01
Clock Domain: MCLKBIT NAME
FUNCTION
7:3 Reserved
INT0 interrupt pulse minimum “on” duration for host interface, when inpulse mode.
2:0

INT0_TPULSE_DURATION

0: 100µs (use only if ODR < 4kHz)
1: 8µs (required if ODR ≥ 4kHz, optional for ODR < 4kHz)
Other Settings: Reserved

20.53 INT_PULSE_MIN_ON_INTF1
Name: INT_PULSE_MIN_ON_INTF1
Address: 106 (6Ah)
Serial IF: R/W
Reset value: 0x01
Clock Domain: MCLKBIT NAME
FUNCTION
7:3 Reserved
INT1 interrupt pulse minimum “on” duration for host interface, when inpulse mode.
2:0

INT1_TPULSE_DURATION

0: 100µs (use only if ODR < 4kHz)
1: 8µs (required if ODR ≥ 4kHz, optional for ODR < 4kHz)
Other Settings: Reserved

20.54 INT_PULSE_MIN_OFF_INTF0
Name: INT_PULSE_MIN_OFF_INTF0
Address: 107 (6Bh)
Serial IF: R/W
Reset value: 0x01
Clock Domain: MCLKBIT NAME
FUNCTION
7:3 Reserved
INT0 interrupt pulse minimum “off” duration for host interface, indicatesminimum interrupt de-assertion duration.
2:0

INT0_TDEASSERT_DISABLE

0: 100µs
1: 8µsOther Settings: Reserved

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20.55 INT_PULSE_MIN_OFF_INTF1
Name: INT_PULSE_MIN_OFF_INTF1
Address: 108 (6Ch)
Serial IF: R/W
Reset value: 0x01
Clock Domain: MCLKBIT NAME
FUNCTION
7:3 Reserved
INT1 interrupt pulse minimum “off” duration for host interface, indicatesminimum interrupt de-assertion duration.
2:0

INT1_TDEASSERT_DISABLE

0: 100µs
1: 8µsOther Settings: Reserved

20.56 ISR_0_7
Name: ISR_0_7
Address: 110 (6Eh)
Serial IF: R/C
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:6 -5

INT_STATUS_ON_DEMAND_PIN_0

4-

3

INT_STATUS_EXT_ODR_DR
DY_PIN_0

2:1

-

0

INT_STATUS_ACCEL_DRDY_PIN_0FUNCTION
Reserved
For IRQ0 interface, if this interrupt status bit is enabled, this bit is to flag theoccurrence of on demand event.
0: Interrupt did not occur.
1: Interrupt occurred.
Reserved
For IRQ0 interface, if this interrupt status bit is enabled, this bit is to flag theoccurrence of EXT ODR DRDY event.
0: Interrupt did not occur.
1: Interrupt occurred.
Reserved
For IRQ0 interface, if this interrupt status bit is enabled, this bit is to flag theoccurrence of Accel DRDY event.
0: Interrupt did not occur.
1: Interrupt occurred.

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20.57 ISR_8_15
Name: ISR_8_15
Address: 111 (6Fh)
Serial IF: R/C
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:6 -5

INT_STATUS_ON_DEMAND_PIN_1

4-

3

INT_STATUS_EXT_ODR_DR
DY_PIN_1

2:1

-

0

INT_STATUS_ACCEL_DRDY_PIN_1

FUNCTION
Reserved
For IRQ1 interface, if this interrupt status bit is enabled, this bit is to flag theoccurrence of on demand event.
0: Interrupt did not occur.
1: Interrupt occurred.
Reserved
For IRQ1 interface, if this interrupt status bit is enabled, this bit is to flag theoccurrence of EXT ODR DRDY event.
0: Interrupt did not occur.
1: Interrupt occurred.
Reserved
For IRQ1 interface, if this interrupt status bit is enabled, this bit is to flag theoccurrence of Accel DRDY event.
0: Interrupt did not occur.
1: Interrupt occurred.

20.58 ISR_16_23
Name: ISR_16_23
Address: 112 (70h)Serial IF: R/C
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:6 -5

INT_STATUS_ON_DEMAND_PIN_2

4-

3

INT_STATUS_EXT_ODR_DR
DY_PIN_2

2:1

-

0

INT_STATUS_ACCEL_DRDY_PIN_2

FUNCTION
Reserved
For IRQ2 interface, if this interrupt status bit is enabled, this bit is to flag theoccurrence of on demand event.
0: Interrupt did not occur.
1: Interrupt occurred.
Reserved
For IRQ2 interface, if this interrupt status bit is enabled, this bit is to flag theoccurrence of EXT ODR DRDY event.
0: Interrupt did not occur.
1: Interrupt occurred.
Reserved
For IRQ2 interface, if this interrupt status bit is enabled, this bit is to flag theoccurrence of Accel DRDY event.
0: Interrupt did not occur.

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ICM-45605
1: Interrupt occurred.

20.59 STATUS_MASK_PIN_0_7
Name: STATUS_MASK_PIN_0_7
Address: 113 (71h)Serial IF: R/W
Reset value: 0x3F
Clock Domain: MCLKBIT NAME
7:6 -5

INT_ON_DEMAND_PIN_0_
DIS

4

-

3

INT_EXT_ODR_DRDY_PIN_
0_DIS

2:1

-

0

INT_ACCEL_DRDY_PIN_0_
DIS

FUNCTION
Reserved
For IRQ0, on-demand DRDY event, this is to enable the interrupt pin
assertion when the INT_STATUS_ON_DEMAND_PIN_0 status bit is 1.
0: Enable the Interrupt pin assertion.
1: No Interrupt pin assertion.
Reserved
For IRQ0, ODR DRDY event, this is to enable the interrupt pin assertion whenthe INT_STATUS_EXT_ODR_DRDY_PIN_0 status bit is 1.
0: Enable the Interrupt pin assertion.
1: No Interrupt pin assertion.
Reserved
For IRQ0, accel DRDY event, this is to enable the interrupt pin assertion
when the INT_STATUS_ACCEL_DRDY_PIN_0 status bit is 1.
0: Enable the Interrupt pin assertion.
1: No Interrupt pin assertion.

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20.60 STATUS_MASK_PIN_8_15
Name: STATUS_MASK_PIN_8_15
Address: 114 (72h)Serial IF: R/W
Reset value: 0x3F
Clock Domain: MCLKBIT NAME
7:6 -5

INT_ON_DEMAND_PIN_1_
DIS

4

-

3

INT_EXT_ODR_DRDY_PIN_
1_DIS

2:1

-

0

INT_ACCEL_DRDY_PIN_1_
DIS

FUNCTION
Reserved
For IRQ1, on-demand DRDY event, this is to enable the interrupt pin
assertion when the INT_STATUS_ON_DEMAND_PIN_1 status bit is 1.
0: Enable the Interrupt pin assertion.
1: No Interrupt pin assertion.
Reserved
For IRQ1, ODR DRDY event, this is to enable the interrupt pin assertion whenthe INT_STATUS_EXT_ODR_DRDY_PIN_1 status bit is 1.
0: Enable the Interrupt pin assertion.
1: No Interrupt pin assertion.
Reserved
For IRQ1, accel DRDY event, this is to enable the interrupt pin assertion
when the INT_STATUS_ACCEL_DRDY_PIN_1 status bit is 1.
0: Enable the Interrupt pin assertion.
1: No Interrupt pin assertion.

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20.61 STATUS_MASK_PIN_16_23
Name: STATUS_MASK_PIN_16_23
Address: 115 (73h)Serial IF: R/W
Reset value: 0x3F
Clock Domain: MCLKBIT NAME
7:6 INT_ON_DEMAND_PIN_2_
5
DIS
4
-

3

INT_EXT_ODR_DRDY_PIN_
2_DIS

2:1

-

0

INT_ACCEL_DRDY_PIN_2_
DIS

FUNCTION
Reserved
Enables the eDMP to be run once when IRQ2 is triggered by setting the
EDMP_ON_DEMAND_EN bit.
Reserved
For IRQ2, ODR DRDY event, this is to enable the interrupt pin assertion whenthe INT_STATUS_EXT_ODR_DRDY_PIN_2 status bit is 1.
0: Enable the Interrupt pin assertion.
1: No Interrupt pin assertion.
Reserved
For IRQ2, accel DRDY event, this is to enable the interrupt pin assertion
when the INT_STATUS_ACCEL_DRDY_PIN_2 status bit is 1.
0: Enable the Interrupt pin assertion.
1: No Interrupt pin assertion.

20.62 INT_I2CM_SOURCE
Name: INT_I2CM_SOURCE
Address: 116 (74h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:2 INT_STATUS_I2CM_SMC_E
1
XT_ODR_EN
0-

FUNCTION
Reserved
0: Does not automatically trigger eDMP operation on target ODR
1: Automatically triggers eDMP operation on target ODRReserved

20.63 ACCEL_WOM_X_THR
Name: ACCEL_WOM_X_THR
Address: 126 (7Eh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME

7:0

WOM_X_TH

FUNCTION
Set X-axis Wake on Motion threshold
Wake on Motion thresholds are expressed in fixed “mg” independently of
the selected full-scale (format <U,8,0>, range [0g : 1g], resolution
1g/256=~4mg)

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20.64 ACCEL_WOM_Y_THR
Name: ACCEL_WOM_Y_THR
Address: 127 (7Fh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME

7:0

WOM_Y_TH

FUNCTION
Set Y-axis Wake on Motion threshold
Wake on Motion thresholds are expressed in fixed “mg” independently of
the selected full-scale (format <U,8,0>, range [0g : 1g], resolution
1g/256=~4mg)

20.65 ACCEL_WOM_Z_THR
Name: ACCEL_WOM_Z_THR
Address: 128 (80h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME

7:0

WOM_Z_TH

FUNCTION
Set Z-axis Wake on Motion threshold
Wake on Motion thresholds are expressed in fixed “mg” independently of
the selected full-scale (format <U,8,0>, range [0g : 1g], resolution
1g/256=~4mg)

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ICM-45605
20.66 SELFTESTName: SELFTEST
Address: 144 (90h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:6 5

4

3

2

1

0

EN_GZ_ST

EN_GY_ST

EN_GX_ST

EN_AZ_ST

EN_AY_ST

EN_AX_ST

FUNCTION
Reserved
0: Z-axis gyroscope self-test is not enabled
1: Z-axis gyroscope self-test is enabled
Can be changed on-the-fly.
0: Y-axis gyroscope self-test is not enabled
1: Y-axis gyroscope self-test is enabled
Can be changed on-the-fly.
0: X-axis gyroscope self-test is not enabled
1: X-axis gyroscope self-test is enabled
Can be changed on-the-fly.
0: Z-axis accelerometer self-test is not enabled
1: Z-axis accelerometer self-test is enabled
Can be changed on-the-fly.
0: Y-axis accelerometer self-test is not enabled
1: Y-axis accelerometer self-test is enabled
Can be changed on-the-fly.
0: X-axis accelerometer self-test is not enabled
1: X-axis accelerometer self-test is enabled
Can be changed on-the-fly.

20.67 IPREG_MISC
Name: IPREG_MISC
Address: 151 (97h)Serial IF: R
Reset value: 0x02
Clock Domain: MCLKBIT NAME
7:2 1

EDMP_IDLE0-FUNCTION
Reserved
0: Indicates eDMP is busy.
1: Indicates eDMP is idle.
Reserved

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ICM-45605
20.68 SW_PLL1_TRIM
Name: SW_PLL1_TRIM
Address: 162 (A2h)
Serial IF: R
Reset value: 0x00
Clock Domain: MCLKBIT NAME

7:0

SW_PLL1_TRIM

FUNCTIONStores variation of PLL frequency test measurement vs. target value, used for
SW applications. Value to trim =(PLL_measurement – 6144000Hz) /6144000Hz * 2540. 6144000Hz is the target PLL freq. 2540 is the resolution
coefficient: max register range / max oscillator frequency error = (2^7 - 1) /5%, with a sign bit.

20.69 FIFO_SRAM_SLEEP
Name: FIFO_SRAM_SLEEP
Address: 167 (A7h)
Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:2 -FUNCTION
Reserved
Set selected SRAM bank global sleep mode
Bit 0:
1.
2.

1:0

FIFO_GSLEEP_SHARED_SR
AM
Bit 1:
1.
2.

When set to 1: SRAM bank-0 will remain enabled
When 0: permits SRAM bank-0 to go to sleep modea. SRAM bank goes to sleep, if not allocated as FIFO memory
spaceb. If allocated as FIFO memory space, remains active unless
FIFO is empty and sensors are off

When set to 1: SRAM bank-1 will remain enabled
When 0: Permits SRAM bank-1 to go to sleep modea. SRAM bank goes to sleep, if not allocated as FIFO memory
spaceb. If allocated as FIFO memory space, remains active unless
FIFO is empty and sensors are off

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ICM-45605
21 USER BANK IPREG_SYS1 REGISTER MAP – DESCRIPTIONSThis section describes the function and contents of each register within user bank IPREG_SYS1. The registers
described in this section are indirect access registers. Section 13 describes the procedure for accessing indirectaccess registers.

21.1

IPREG_SYS1_REG_42

Name: IPREG_SYS1_REG_42
Address: 42 (2Ah)
Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

GYRO_X_OFFUSER[7:0]

21.2

IPREG_SYS1_REG_43

Name: IPREG_SYS1_REG_43
Address: 43 (2Bh)
Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:6 5:0

GYRO_X_OFFUSER[13:8]

21.3

IPREG_SYS1_REG_56

Name: IPREG_SYS1_REG_56
Address: 56 (38h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

GYRO_Y_OFFUSER[7:0]

21.4

IPREG_SYS1_REG_57

Name: IPREG_SYS1_REG_57
Address: 57 (39h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:6 5:0

GYRO_Y_OFFUSER[13:8]

FUNCTION
Low bits for X-gyro offset programmed by user. Range is ±62.5dps,
resolution is 7.5mdps.

FUNCTION
Reserved
Upper bits for X-gyro offset programmed by user. Range is ±62.5dps,
resolution is 7.5mdps.

FUNCTION
Low bits for Y-gyro offset programmed by user. Range is ±62.5dps, resolution
is 7.5mdps.

FUNCTION
Reserved
Upper bits for Y-gyro offset programmed by user. Range is ±62.5dps,
resolution is 7.5mdps.

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ICM-45605
21.5

IPREG_SYS1_REG_70

Name: IPREG_SYS1_REG_70
Address: 70 (46h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

GYRO_Z_OFFUSER[7:0]

21.6

IPREG_SYS1_REG_71

Name: IPREG_SYS1_REG_71
Address: 71 (47h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:6 5:0

GYRO_Z_OFFUSER[13:8]

21.7

IPREG_SYS1_REG_166

Name: IPREG_SYS1_REG_166
Address: 166 (A6h)
Serial IF: R/W
Reset value: 0x1B
Clock Domain: MCLKBIT NAME
7-

6:5

GYRO_SRC_CTRL

4:0-

FUNCTION
Low bits for Z-gyro offset programmed by user. Range is ±62.5dps, resolution
is 7.5mdps.

FUNCTION
Reserved
Upper bits for Z-gyro offset programmed by user. Range is ±62.5dps,
resolution is 7.5mdps.

FUNCTION
Reserved
Gyro SRC CTRL:
0: Interpolator and AAF FIR filter off
1: Interpolator off and AAF FIR filter on
2: Interpolator on and AAF FIR filter on
3: Reserved (debug mode)
Reserved

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ICM-45605
21.8

IPREG_SYS1_REG_170

Name: IPREG_SYS1_REG_170
Address: 170 (AAh)Serial IF: R/W
Reset value: 0x0A
Clock Domain: MCLKBIT NAME
7:5 -

4:1

GYRO_LP_AVG_SEL

0

-

21.9

IPREG_SYS1_REG_172

Name: IPREG_SYS1_REG_172
Address: 172 (ACh)Serial IF: R/W
Reset value: 0x80
Clock Domain: MCLKBIT NAME
7:3 -

2:0

FUNCTION
Reserved
Gyro Low Power Mode Averaging Filter Selection
0000: 1x0001: 2x0010: 4x0011: 5x
0100: 7x
0101: 8x
0110: 10x
0111: 11x
1000: 16x
1001: 18x
1010: 20x
1011: 32x
1100: 64x
Others: Reserved
Reserved

GYRO_UI_LPFBW_SEL

FUNCTION
Reserved
Selects cut-off bandwidth for Gyro UI path LPF
000: Bypass
001: ODR/4
010: ODR/8
011: ODR/16
100: ODR/32
101: ODR/64
110: ODR/128
111: ODR/128

Note: When the FIR AAF is enabled, the signal path BW is decided by the FIR AAF and UI LPF combination. Pleaserefer to AN-000365 ICM-456xx User Guide for details.

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ICM-45605
22 USER BANK IPREG_SYS2 REGISTER MAP – DESCRIPTIONSThis section describes the function and contents of each register within user bank IPREG_SYS2. The registers
described in this section are indirect access registers. Section 13 describes the procedure for accessing indirectaccess registers.

22.1

IPREG_SYS2_REG_24

Name: IPREG_SYS2_REG_24
Address: 24 (18h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

ACCEL_X_OFFUSER[7:0]22.2

IPREG_SYS2_REG_25

Name: IPREG_SYS2_REG_25
Address: 25 (19h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:6 5:0

ACCEL_X_OFFUSER[13:8]

22.3

IPREG_SYS2_REG_32

Name: IPREG_SYS2_REG_32
Address: 32 (20h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

ACCEL_Y_OFFUSER[7:0]

22.4

IPREG_SYS2_REG_33

Name: IPREG_SYS2_REG_33
Address: 33 (21h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:6 5:0

ACCEL_Y_OFFUSER[13:8]

FUNCTION
Low bits for X-accel offset programmed by user. Range is ±1g, resolution is0.125mg.

FUNCTION
Reserved
Upper bits for X-accel offset programmed by user. Range is ±1g, resolution is0.125mg.

FUNCTION
Low bits for Y-accel offset programmed by user. Range is ±1g, resolution is0.125mg.

FUNCTION
Reserved
Upper bits for Y-accel offset programmed by user. Range is ±1g, resolution is0.125mg.

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ICM-45605
22.5

IPREG_SYS2_REG_40

Name: IPREG_SYS2_REG_40
Address: 40 (28h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:0

ACCEL_Z_OFFUSER[7:0]

22.6

IPREG_SYS2_REG_41

Name: IPREG_SYS2_REG_41
Address: 41 (29h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:6 5:0

ACCEL_Z_OFFUSER[13:8]

22.7

IPREG_SYS2_REG_123

Name: IPREG_SYS2_REG_123
Address: 123 (7Bh)
Serial IF: R/W
Reset value: 0x14
Clock Domain: MCLKBIT NAME
7:2 -

1:0

ACCEL_SRC_CTRL

FUNCTION
Low bits for Z-accel offset programmed by user. Range is ±1g, resolution is0.125mg.

FUNCTION
Reserved
Upper bits for Z-accel offset programmed by user. Range is ±1g, resolution is0.125mg.

FUNCTION
Reserved
Accel SRC CTRL:
0: Interpolator and AAF FIR filter off
1: Interpolator off and AAF FIR filter on
2: Interpolator on and AAF FIR filter on
3: Reserved (debug mode)

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ICM-45605
22.8

IPREG_SYS2_REG_129

Name: IPREG_SYS2_REG_129
Address: 129 (81h)Serial IF: R/W
Reset value: 0x02
Clock Domain: MCLKBIT NAME
7:4 -

3:0

22.9

ACCEL_LP_AVG_SEL

IPREG_SYS2_REG_131

Name: IPREG_SYS2_REG_131
Address: 131 (83h)Serial IF: R/W
Reset value: 0x00
Clock Domain: MCLKBIT NAME
7:3 -

2:0

FUNCTION
Reserved
Accel Low Power Mode Averaging Filter Selection
0000: 1x0001: 2x0010: 4x0011: 5x
0100: 7x
0101: 8x
0110: 10x
0111: 11x
1000: 16x
1001: 18x
1010: 20x
1011: 32x
1100: 64x
Others: Reserved

ACCEL_UI_LPFBW_SEL

FUNCTION
Reserved
Selects cut-off bandwidth for Accel UI path LPF
000: Bypass
001: ODR/4
010: ODR/8
011: ODR/16
100: ODR/32
101: ODR/64
110: ODR/128
111: ODR/128

Note: When the FIR AAF is enabled, the signal path BW is decided by the FIR AAF and UI LPF combination. Pleaserefer to AN-000365 ICM-456xx User Guide for details.

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ICM-45605
23 REFERENCE
Please refer to the following application notes for additional information.
•

IxM-4xxxx, IxM-2xxxx and MPU-6xxx Products PCB Design, Mounting, and Handling Guidelines (AN000393)•

Understanding IMU Sensor Offset (AN-000257)•

TDK InvenSense IMU Calibration Application Note (AN-000265)•

ICM-456xx Errata Update (AN-000364)•

ICM-45605 & ICM-45686 User Guide (AN-000478)

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ICM-45605
24 REVISION HISTORY
Revision Date

Revision

Description

07/25/2024

1.0

Initial Release

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ICM-45605

This information furnished by InvenSense or its affiliates (“TDK InvenSense”) is believed to be accurate and reliable. However, no responsibility
is assumed by TDK InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use.
Specifications are subject to change without notice. TDK InvenSense reserves the right to make changes to this product, including its circuits
and software, in order to improve its design and/or performance, without prior notice. TDK InvenSense makes no warranties, neither expressed
nor implied, regarding the information and specifications contained in this document. TDK InvenSense assumes no responsibility for any claims
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Trademarks that are registered trademarks are the property of their respective companies. TDK InvenSense sensors should not be used or soldin the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life
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instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2024 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, DMP,
AAR, and the InvenSense logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and productnames may be trademarks of the respective companies with which they are associated.

©2024 InvenSense. All rights reserved.

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