Heat Resistant Bump Protection Tape with Easy
Debonding
Jimmy Wang, Jian Kuan Wu, Benson Chen, Robin Gorrell *3M Taiwan, 7, No.66, Lane 800, Jhongshan S. Rd., Yangmei, Taoyuan, Taiwan*3M Corporation, 6801 River Place Blvd., Austin, TX 78726-9000, United States.
Abstract
This paper presents a novel high temperature tape developed
to support the wafer level package process. The hightemperature resistant backing film with cross linkableadhesive was designed to fit the die to wafer or package-onpackage process. With high initial adhesion for robust

I. Introduction2.5D/3D heterogeneous packaging has enabled highperformance package technologies to achieve
increased circuit densities, enhanced band width, andbumped wafer support, excellent thermal stability to carry thelower power consumption. Many process variants have

fan out or interposer wafer through the die stacking steps andbeen developed by Fabs and OSATs, for example,

resist reflow with easy final debonding of the tape. The

integrated fan out (InFO from TSMC); fanout chip onadhesive was designed for clean removal on metal pads or

substrate package (FOCoS from ASE); chip on wafer onsolder bump surfaces, meeting the requirements for HVM

substrate (CoWoS from TSMC) and Foveros / EMIB

(high volume mass production).
In this article, we demonstrate the tape can be easily
attached on a metal frame as a supporting tape carrier, thenlaminated with the device wafer to provide uniform bumpcoverage, with proper adhesion strength and adhesivefrom Intel. Those designs unveil the concept of systemon chip (SOC) though chip to wafer or package onpackage 2.5D / 3D package technology. To support
the wafer level package process, temporary bonding /modulus and thickness design, no delamination or rebounddebonding (TBDB) of carriers has been developed overoccurs after wafer lamination. To address the challenges,

a number of years to improve handling of thin andincluding high temp resistance; bump protection; tape releasefragile substrates. Within fan out packaging, UHD FO

and residue concerns, key process conditions were simulated(Ultra High Density Fan Out) is experiencing the highestto evaluate the tape’s performance.

growth rate at CAGR 20.7% for high end applicationsThe demonstration of tape performance in these criticalprocess conditions, designed to simulate advanced packaging
process steps and key quality attributes, shows that the newly
developed advanced package process tape can fully support
the wide range of processes needed for better performance inthe semiconductor advanced packaging industry.

like networking and HPC. The technology trend for fan
out has been towards a higher integration level, as
FOWLP enables many integration possibilities including
PoP, SiP or MCM.
Various multi-stack fan out packaging formats are
expected to achieve higher memory capacity andKey Words: Die to Wafer; Package on Package; High Temp

bandwidth. However, total cost reduction and process

Process Tape; Wafer Level Package; Fan out Package.

yield improvement has been one of the roadblocks toHeat Resistant Bump Protection Tape with Easy Debonding | 3M

grow fan out into a bigger platform. The overall cost
can be relatively high compared with a carrier-lessprocess, for example, using tape to support thebackend package process.

II. Application and Performance Challenge

Fig. 2, D2W, W2W with pre-tack and reflow processes can be donewith bumps covered by the tapei.

Process for Die to Wafer Package
A demonstration of the high temperature performanceThis tape was designed for high temperature resistanceof this tape starts from target wafer attach onto the tape.

and can withstand 200°C / 2 hr exposure to fulfill various

The tape can be handled in frame format using a

packaging material and process requirements.

standard roll type laminator, in a similar manner as adicing tape process. The laminator can easily laminateii.

Product Design and Feature

the tape to the metal frame. See Fig.1(a). After frame

The primary application for this process tape is toattach, the wafer form package is bonded to the tape by

support the wafer format package through several

vacuum compression to achieve good uniformity andnecessary high temperature process steps. The

TTV level. The wafer form package could comprise aadhesive was designed to have a thermal debond

variety of wafer types, for example, an interposer wafer;function along with robust resistance to high process

TSV wafer; fan out OS (on substrate) package withtemperatures and durations. See Fig. 3. The tapebumps or pads on the wafer top side. See Fig. 1(b).

structure is shown in Fig. 4. The adhesive thickness
was targeted to 20-60 μm to meet the requirements ofvarious types of I/O connections. The hightemperature resistant backing film is normallypolyimide, but other temperature resistant films whichmeet specific process temperature requirements may

Fig. 1(a), the tape can easily be laminated to the metal frame by alaminator

also be an option.

Fig. 1(b), the wafer form package bonds to the tape after frame attach

The tape adhesive may be fully covered withbumps/pads or partially covered, depending on wafer
format and the adhesive thickness design. The assembly
could follow a die to wafer or wafer to wafer bonding

Fig. 3, the adhesive is designed with a thermal debond function

process, with pre-tack and reflow processes. See Fig. 2.

Fig. 4, the structure of the tape2

Heat Resistant Bump Protection Tape with Easy Debonding | 3M

The adhesive crosslink density must be carefully
designed to meet the process requirements for peelstrength and residue. The adhesive peel strength isinversely proportional to adhesive crosslink density.
When the adhesive has higher crosslink density, theadhesion is decreased. On the other hand, the adhesiveFig.6 (a), Metal frame was set for suspension at 10 mm height

modulus and cohesion increases with crosslink density.
These properties must be balanced to achieve therequired adhesion through processing, release without
damage to pads or solder bumps, and clean, residue
free removal. See Fig. 5.
Fig.6 (b), thermal detach in adhesiveFig.6 (c), Residue check
Fig. 5, the adhesive modulus and cohesion are designed to achieve therequired adhesion through multiple processesiii.

Package Process Condition Simulation
Simulation of processes requiring higher temperatures in
the advanced packaging process was carried out tounderstand the tape performance and critical challengesof the application. A high temperature 180°C /1 hr +260°C / 10 min bake step was performed to simulate
various processes such as sputtering, molding, plasma
clean and die attach and the final solder reflow step. Fig.
6(a) depicts the test set-up, with tape performancechecked in the key process challenges of adhesion,residue and bump damage as shown in Figures 6(b)-(d).

Fig.6 (d), Bump damage check

Table 1 shows pre- and post- thermal exposure adhesion
strength testing, which was performed to demonstrate
the tape’s thermal stability and peel force reduction after
high temperature processing. This property of the taperesults in sufficient adhesive strength during processing
to maintain adhesion to the wafer and frame but allows
for easy debonding performance.

The tape is also

compatible with two solder reflow cycles at 260°C for
10 minutes without adhesive degradation or risk of tapebreakage. This performance provides for the possibilityof applications requiring a 2nd layer die stack, with morechip functionality to align with recent heterogenous
package technology trends.
3

Heat Resistant Bump Protection Tape with Easy Debonding | 3M

Table 1, Tape adhesion with temperature simulation

After the high temperature process treatments, the tapewas easily removed without bump damage, as evident
through high magnification microscopic inspection. The
tape’s debonding performance can significantly reduce
the yield loss and achieve cost reduction for very
backend SOC package chip sets. See Fig. 7.

Fig. 8, Bump damage evaluation

III. Conclusion
A newly designed high temperature process tape has
been presented. The product shows excellent wafer
supportperformance

asdemonstrated

throughsimulation of several high temperature and high loading
process conditions. Various tape thickness designs canFig. 7, Residue inspection after tape removal

To understand the performance of the tape in protectionof solder bumps during processing, several adhesive
formulation DOEs were conducted, making use of thesame high temperature process conditions citedpreviously. In evaluating formulations at targeted levelsof adhesive crosslinking, it was demonstrated that thecrosslink density correlates strongly with the relative

meet different wafer surface structure requirements,
which include solder bumps, C4 bumps, micro bumps
and pads, and other I/O connection needs. With proper
adhesive formulation design and crosslink density
control, the tape adhesive can achieve high initialadhesion, but allow lower detaping strength afterthermal processing, thus minimizing or eliminating bumpdamage and residue.

amount of bump damage or distortion. See Fig. 8. The
adhesive becomes stronger as the crosslink density isincreased, providing better support to bumps whensolder balls soften and melt when at or near the reflow
temperature.

Acknowledgments
The authors wish to thank Joann Wang, and all ourcoworkers who have assisted in the development andtesting of the high temperature process tape.

4Heat Resistant Bump Protection Tape with Easy Debonding | 3M

References[1]

S. Kumar, S. Chitoraga, F. Shoo, “Status of the advanced packaging
industry 2021”, Yole Développement Market and Technology Report,2021, pp. 117-149.

[2]

W. Shen, Y. Lin, S. Chen, H. Chang, T. Change, W. Lo, C. Lin, “3-D
Stacked Technology of DRAM-Logic Controller Using Through-SiliconVia (TSV)”, Journal of the Electronic Devices Society, pp. 396-402,
Volume 6, 2018.

[3]

M.J. Zajaczkowski, “Pressure sensitive adhesives in high performanceapplications”, The Adhesives and Sealants Council, Inc., 2010.

[4]

D. J. McClure, “Polyimide Film As a Vacuum Coating Substrate”, 53 rd
SVC Technical Conference, 2010.

[5]

Y. Arimitsu, T. Oshima, A. Murata, K. Kiuchi, “Thermal release sheet‘Revalpha’”, Nitto Technical Report, Volume 36, 1998, pp. 52-53.

[6]

D. Wilson, H.D. Stenzenberger, P.M Hergenrother, B. Glasgow,“Polyimides”, ISBN 0-412-02181-1, 1990.

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Heat Resistant Bump Protection Tape with Easy Debonding | 3M

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