PIXEL2012

Progress of SOI
Pixel Process
Sep. 3
Sep3, 2012
PIXEL2012@Inawashiro
YYasuoAArai,i KEK
yasuo.arai@kek.jp
http://rd.kek.jp/project/soi/
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OUTLINE•Introduction of SOI Technology•Recent Progress•SummaryS

2

KEK-Lapis SOI Pixel Related Presentations
Sep. 3. Session 3:• "Development and Deployment Status of X-ray 2D Detector for SACLA", T.
HATSUI.
Sep. 4, Session 4:• "High-Resolution Monolithic Pixel Detectors in SOI Technology", T. MIYOSHI.
• "A thinhi ffully-depletedll d l d monolithic
li hi pixel
i l sensor iin Sili
Silicon O
On IInsulator
ltechnology",h l"
S. MATTIAZZO.
• "Development and characterization of the latest X-ray SOI pixel sensor for afuture astronomical mission", S. NAKASHIMA• "3D Integration for SOI Pixel Detector", M. MOTOYOSHI.
Sep. 6,S
6 SSessioni 6• "Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC, using anested well structure to decouple the detector from the electronics", F. KHALID.
• "Test of TRAPPISTe Monolithic Detector System", L. SOUNG YEE.
Poster :• "HighHigh Resolution XX-rayray Imaging Sensor with SOI Technology"
Technology , A.
A TAKEDATAKEDA.
• "Development of the Pixel OR SOI Detector for High Energy Physics
Experiments" , Y. ONO.
• "Characterization
Coff SO
SOI Monolithic Detector System",
SR. ALVAREZ.
• "A study on the dynamic range of integrating SOI chips", Lu YUNPENG

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SOI Wafer Production (Smart Cut by SOITEC)

CMOS(Low R)

Sensor(High R)
4

SOI Pixel Detector ((SOIPIX))
Monolithic Detector having fine resolution of silicon
and data processing power of CMOS LSI by using
Silicon-On-Insulator (SOI) Technology.

5

SOI Performance : Smaller Junction CapacitanceCj iis 1/10 off Bulk
B lk technology.
t h lGate Capacitance is 30-40%Lower.

High Speed / Low Power
6

Radiation Tolerance
SOI is Immune to Single Event EffectGate Oxide
Gate
Si＋ －－ ＋＋ －－ ＋＋ －－ ＋＋ －－ ＋＋ －－ ＋＋ －Gate＋ －Si

BuriedOxide
Depletion
Layer

Bulk Device

SOI Device＋ －－ ＋＋ －－ ＋＋ －－ ＋

But not necessary strong to Total Ionization Dose due to thick BOX layer
GateSiThis must be remedy forthe application under highradiation environment.

BuriedOxide＋＋＋＋＋Trapped
Holes
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Operation at Cryogenic Temperature

Bulk MOS

4.2K

SOI MOS8

Feature of SOI Pixel Detector• No mechanical bonding. Fabricated with semiconductor
process only, so high reliability, low cost are expected.
• Fully depleted thick sensing region with Low sense
node capacitance.
• On Pixel processing with CMOS transistors.
• Can be operated in wide temperature (4K-570K) range,and has low single
g event cross section.
• Based on Industry StandardTechnology.

9Lapis (*) Semiconductor 0.2 m FD-SOI Pixel Process
Process

0.2m Low-Leakage Fully-Depleted SOI CMOS
1 Poly, 5 Metal layers.
MIM Capacitor (1.5 fF/um2), DMOS
Core (I/O) Voltage = 1.8 (3.3) V

SOIwafer

Diameter: 200 mm
mm, 720 mm thick
Top Si : Cz, ~18 -cm, p-type, ~40 nm thickB i dO
BuriedOxide:
id 200 nm thithickkHandle wafer: Cz (n) ~700 -cm,FZ(n) ~7k -cm, FZ(p) ~25 k -cm

Backside Mechanical Grind
Grind, Chemical Etching
Etching, Back sideprocess Implant, Laser Annealing and Al plating(*) Former OKI Semiconductor Co. Ltd.

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SOIPIX Collaboration:
Regular Multi-Project Wafer(MPW) run. (~twice/year)

0.2 m Fully-Depleted SOI Pixel
Process of Lapis Semiconductor
Co. Inc.

JAXA

RIKEN

AIST

U. of Hawaii
Osaka U.
Fermi Nat'l Accl. Lab.

Tohoku U.

KEKL
Lawrence
B
Berkeleyk l NNat'lt'l LLab.
b
Kyoto U.

Tsukuba U.

INP Krakow
U Heidelberg
U.

IHEP/IMECAS China

Louvain-la-Neuve Univ.

SOIPIX MPW Mask
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Examples of SOIPIX Measurements
X-ray Imaging

5mmCompton Electrons

Takeda's Poster
X-ray Spectrum@-50℃

 Nakashima's Talknoise 18e18e rms

12Recent Progress13

Larger Mask

New Mask

Previous Mask

Easyy to make Larger
gSensors, and reduce
cost per area.
Unit size : 5mm  6mm

31 mmm20.8 mmx20.8 mm

24.8 mm14

Stitching Exposure Hatsui's Talk

Mask Layout
Exposed Layout
Pixel
BlindBlind15

High Resistive wafers

INTPIX3e
INTPIX316

Vertical (3D) Integration

 Motoyoshi's Talk

3D vertical Integration technique is expected to play an important rolein future high performance pixel detector
detector.
We have made 3D test chips. These chips were bonded with -bumptechnology (~5 um pitch) of T-micro Co. Ltd.

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SOI 3D Bonded Chip

10 um

1st SOI 3D Sensor
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Isuues in SOI PixelSensor and Electronics are located very near. This cause ..

We need additional backback-plane
plane to suppress these effects.
effects
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Buried p-Well (BPW)BPW Implantation

Substrate Implantation
BuriedOxide(BOX)SOI Si
Pixel

P+PeripheralBPW• Cut Top Si and BOX• Keep Top Si not affected• High Dose• Low Dose• Suppress
Stheth BackB k Gate
G t Effect.
Eff t• Shrink pixel size without loosing sensitive area.
• Increase break down voltage with low dose region.
• Less electric field in the BOX which improve radiation
hardness.

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Id-Vg and BPW
w/o BPW

with BPW=0V

NMOS

back channel openshift

Back ggate effect is suppressedppby
y the BPW.
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Nested Well Structure Fahim Kahlid's Talk

• Signal is collectedwith the deep
Buried P-well
P-well.
• Back gate andCross Talk areshielded with theBuried NN-well.
well22Impurity
Concentration

Peaks of BNW andBPW are separated~0.7 m to reduce
capacitance23

Double SOI Wafer
circuitsensor

additional
conduction layer• Shield transistors from bottom electric field• Compensate electric field generated by the trappedh l iin thhole
the BOXBOX.
• Reduce crosstalk between sensors and circuits.

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Double SOI Process

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SEM View of Double
Double-SOI
SOI(post Field-Anneal)
Si：46.7nm
SiO2：158 7nm
SiO2：158.7nm
Si：84nm
SiO2：156.0nm

Poly-SiPl Si
Top-Si
BOX1(SiO2)
Middle Si
Middle-Si
BOX2(SiO2)
Handle-Wafer(Thickness of Si & SiO2 layers are not yet optimized)
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Suppression
ppof Back-Gate Effect with Middle-Si layeryb) Middle-Si = GND

1 0E 03
1.0E-03

1 0E-03
1.0E-03

1.0E-04

1.0E-04

1.0E-05

1.0E-05

1.0E-06

1.0E-06

1.0E-07

1.0E-07

Vback=0V
Vback=5V
Vback=10V
Vback=15V
Vback=20V
Vback=25V

1.0E-08
1.0E-09
1.0E-10
1 0E-11
1.0E-11
1.0E-12-0.5

Ids [A]Ids [A]a) Middls-Si Floating

00.5
1Vg [V]

1.5

Vback=0V
Vback=100V
Vback=200V
Vback=300V
Vback=400V
Vback=500V

1.0E-08
1.0E-09
1.0E-10
1 0E-11
1.0E-112

1.0E-12-0.5

Back Gate Effect is fully suppressed withBack-Gate
the Middle Si Layer of fixed voltage.

00.5
1Vg [V]

1.5

2

Nch Core Normal-Vt
L / W = 0.2
02/5
5.0um
0um
Vd=0.1V

Trapped Charge Compensation (ThresholdControl)with Middle-Si Layer
1 0E-03
1.0E03Threshold voltage of a transistor
is controlled with the bias voltege
off theth Middle-SiMiddl Si llayer.
This indicate effects of thet
trappedd charge
hiin ththe BOX canbe compensated with the bias
voltagevoltage.

1.0E-04
1.0E-05

Ids [A]

1.0E-06
1.0E-07
1.0E-08

Vm-si=4V

1.0E-09

Vm-si=2V
Vm-si=0V
Vm
si=0V

1.0E-10

Vm-si=-2V

1.0E-11
1.0E-12-0.5

Vm-si=-4V
00.5
1Vg [V]

1.5Nch Core Normal-Vt
L / W = 0.2 / 5.0 um
Vd=0.1V, Vback：floating

2Summary• SOI technology has many good features; low power, lowvariability, large operating temperature range, no latch
up..., and Industries are moving to extremely thin SOI.
• SOIPIX is monolithic detector, and many of the technicalpy existed are solved.
problems initially• We have ~twice/year regular MPW runs with increasing no.
of users.
users• The process technology is still progressing; Higher
resistivity
i ti it wafer,f NestedN t d wellll structure,t tL
Largermask
k size,iStitching, etc. …
• Double SOI wafer is successfully processed.
• We welcome new users to the SOI pixel processprocess.
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