Development and Prospectof Advanced Pixel Sensors
in SOI Technology
Dec. 20, 2011
US-Japan WS@KEK
Yasuo Arai, KEK
yasuo.arai@kek.jp
http://rd.kek.jp/project/soi/Silicon-On-Insulator (SOI) Pixel Detector

Monolithic Si Pixel Sensor with Micro Electronics
Features of the SOI Pixel Detector!!

Bonded wafer : Thick High Resistivity Sensor + CMOS!!

Monolithic Detector (-> High Density, Low material).

Standard CMOS (-> Complex functions in a pixel).
!! No mechanical bump bonding (-> High yield, Low cost).
!!

Full depleted sensor with small capacitance of the sense
node (~10fF, High conversion gain, Low noise)!! Based on Industrial standard technology (-> Cost benefitand Scalability)!! No Latch Up, Low SEE !."!!

Low Power!! Operate in wide temperature(4K-570K(300#C)) range.
!!

!!

Si



...


SOI Pixel Project & US-JP Collaboration
Brief History'05. 4 : Proposed to KEK Detector Technology Project.
'05.10 : 1st Submission to U. of Tokyo VDEC MPW run.
'06.12 : 1st 0.15 um KEK SOI-MPW run.
'07.11 : SOI Users Meeting @ U. of Hawaii during IEEE NSS.
'08. 1 : 1st 0.2 um KEK SOI-MPW run at Miyagi OKI Fab.
2008.4 – 2012.3 : 1st Phase of SOI R&D is approved.
'10. 3 : Collaboration Meeting @ Fermilab.
'11. 3 : International Review @ KEK.
'11.10 : 6th 0.2um KEK SOI-MPW run.
'12. 3 : Collaboration Meeting @ LBNL.
US-JP Collaboration
[JAPAN]
KEK, Tsukuba Univ., Osaka Univ., Tohoku Univ.,
Kyoto Univ., JAXA/ISAS[US]
LBNL, FNAL, U. of Hawaii
Other Collaborators
Japan : Riken/SPring-8, U. of Tokyo, Kyoto U. of Education, NAOJ,AIST
Foreign : IHEP China, INP Krakow, AGH Krakow, INFN Padova, MPI,
U. of Heidelberg, Louvain U., Academia Sinica, SMU, ...

[Industry]
Lapis (OKI) Semiconductor, …
3 Joint Research Programs> 150 members in SOI
mailing listMarch 2010,
Meeting@Fermilab
MPW (Multi Project Wafer) run~Twice / year.
Louvain-la-Neuve Univ.

U. of Hawaii

INP Krakow

IHEP China

U. Heidelberg

U. Tohoku
Kyoto Univ.

JAXA/ISAS
AIST

Tsukuba Univ.
2006

2008~9

0.64 mm

2.56 mmHistory of SOI Pixel
Detectors

32x32
Vbias~10V2010

128x128

13.8 mmVbias~100V

832x512
Vbias~250V


MAMBO V (submitted in Oct. 2011, 9.1 x 6 mm2)

Fermilab
105 µmMAMBO III pixel•! Counting (fMAX= ~ 1MHz)•! Each pixel: CSA, CRRC2 SHA, window
discri. + 12 bit counterJapan-US Cooperative Research Program Workshop, Dec. 20, 2011     #Size : 14 µm x 14 µm
with CDS circuitCounting Type Pixel (CNTPIX)

CNTPIX5Pixel Size : 64x64 µm2

Energy selection andCounting in each pixel.
4 pixels can becombined.
Spatial Resolution (Contrast Transfer Function)
•! Comparison of contrasts with commercial X-ray devices.
–! SOI Pixel : INTPIX4, Flat Panel Sensor (FPS), CCD, and Imaging Plate (IP)FPS

INTPIX4

CTF [%] = B / A

CCD

A

B

High Contrast

Upper Line
Under Line

IPBase Line13Fine resolution & High Contrast

(A. Takeda)
XRPIX1

Energy Resolution

FWHM=260eV

Cu K$ and K# isseparated
Noise ~ 23e@-50#C

(Kyoto Univ.)
Beamtest with INTPIX3e telescope@CERN SPS H6 beam line (Oct. 2011)
INTPIX3e

4layers of INTPIX3e

beam 

CERN SPS
200 GeV/c %- beam
by LBNL/Padova(2010/2011)

 

New Techniques

1st AlHandle Wafer Major Issues in SOI Pixel
Sensor and Electronics are located very near. This cause ..

We need additional back-plane to overcome these effects. 

Buried p-Well (BPW)
BPW Implantation

Substrate Implantation!*+),-(&.)-,(/!&01

%&'(%)
").,2

"$",+)34,+52!"#•! Cut Top Si and BOX•! High Dose•! Keep Top Si not affected•! Low Dose•!Suppress the Back Gate Effect.
•!Shrink pixel size without loosing sensitive area.
•!Increase break down voltage with low dose region.
•!Less electric field in the BOX which improve radiation
hardness.

Id-Vg and BPW
NMOS

w/o BPW

with BPW=0V

back channel open
shift

Back gate effect is suppressed by the BPW.
Nested Well Structure
•!Signal is collectedwith the deep
Buried P-well.
•!Back gate andCross Talk areshielded with theBuried N-well.

Proposed by G. Deptuch (Fermilab)
Double SOI Layer wafer
circuit
sensor•!Shield between sensors andelectronics•!Oxide trapped hole created byradiation can be compensatedwith back-biasing•!Dynamically boost performance(forward back-bias) at the expenseof leakage, or to cut leakage(reverse back-bias at the expenseof performance

additional
conduction layer
Wafer is ready.
First Process is inprogress. FZ(p and n) SOI Wafer
It was difficult to process 8’’ FZ-SOI wafer in CMOS process.
" ! 
!
Slips
We optimized the process parameters, and succeeded toperform the process without creating many slips.
Wafer type and Leakage Current

INTPIX3eMask Layout

Stitching Exposure
Exposed Layout

BlindPixelBlind26

Compton Electrons from High-Energy X-rays 

On-Going SOI Projects
•!INTPIX : Genera Purpose Integration Type•!CNTPIX : General Purpose Counting Type•!MVIA : Multi Via Sensor for XFEL•!PIXOR : Belle II SVD Innermost layer•!XRPIX : X-ray Astronomy in Satellite•!MAMBO : High Performance 3D Detector for ILC•!HiRPIX : High Efficiency X-ray Detector•!MALPIX : TOF Imaging Mass Spectrometer•!FPIX : Contamination Inspection•!µSR, Syncrotron Light, Plasma, Radiation
Monitor, . . . 

4. Summary•! SOI Pixel Technology has many features; High Spatial Resolution,Low Material budget, Low Cost etc.
•! It can include variety of functionality in each pixel ; Energy Selection,
Hit Counting, Memory, ADC and TDC and so on.
•! US-JP Collaboration on SOI Pixel detector was started in FY2008, andthe first phase R&D will end next March. The collaboration has beenvery successful. We share the cost of the MPW runs, and are working
for common issues such as thinning and backside processing.
•! The regular MPW run (~twice/year) is attracting many users from not
only HEP but also other fields such as astrophysics, X-ray analysis,
medical, contamination inspection, ...
•! Although the first phase SOI project will end soon, we would like topropose second phase proposal to the US-JP program.
