SOI (Silicon-On-Insulator) 技術を⽤いたピクセル検出器の開発
原 和彦（数理物質系）•

素粒⼦実験でのPixel 検出器•

読出し⼀体型SOI Pixel 検出器•

筑波⼤のSOI Pixel開発経緯
最初の放射線耐性薄型化(INTPIX)とテストビーム試験
2重 SOI の導⼊
TrTEG6, INTPIXh2
FPIX2
放射線耐性の向上化

K. Hara, CiRfSE Nov.30, 2015•

SOFIST
KEK MPWと新学術
新学術

•

まとめ

2

素粒⼦実験でのピクセル検出器

衝突点の近傍で⾶跡検出

LHC-ATLAS: 3層⇒4層⇒5層(HL-LHC)
ILC-ILD: 5層(double layer)
ILC

ATLAS (LHC⇒HL-LHC)
微細ピクセル50x450um(⇒ 50x250um)⇒ 50x50um?
（ハイブリッド）

5umの位置分解能(読出し回路⼀体型)

⾼速信号

25nsを分離(全空乏化)

1msを分割(~全空乏化)

低物質量3.5%X0⊥/layer⇒keep or less

0.16%X0⊥/layer(⼀体型)

放射線耐性2⇒ x10
0 5MG 1015neq/cm
0.5MGy,/10 @HL@HL-LHCLHC

2 /y~ 1 kGy/y,kG / ~101011neq/cm//

ATLAS 内部⾶跡検出器

ILD pixel

ATLAS での粒⼦発⽣(データ)

HL-LHCでは最⼤200 verticesへ
K. Hara, CiRfSE Nov.30, 2015

3HybridからMonolithicピクセル検出器へ

ATLAS Hybrid型pixel
Sensor部とR/O部をBUMP BOND

Monolithic型pixel
CMOS

HR CMOSHR-CMOSR/O circuit

R/O circuit

全空乏化しにくい（低抵抗）（~⾼抵抗）
R/O circuit

Deep W
DWellll
epitaxial（~⾼抵抗）

K. Hara, CiRfSE Nov.30, 2015

SOI-CMOSCMOS process最適化
ＢＯＸ

R/O circuit（~⾼抵抗）~25um

SOI-CMOSは回路プロセス、全空乏化両⽅に最適化されている？埋込酸化膜の放射線による帯電の影響

4

読出し⼀体型SOIピクセル検出器

CMOS(Low Resistivity)

SiO

2
SOI Pixelの技術的特徴:(BOX) Soitec（⇒信越化学）による張合ウェハー
従来抵抗値：CMOS回路の製作
⾼抵抗ウェハー：粒⼦検出部
⽤途に応じた（全空乏型⾼速センサ）
 Lapis
L i Semiconductor
Sid t (0.2um(0 2CMOS)によるMPWreliable fabrication

Handle wafer:
CZn ~ 700 -cm (Default)
FZn > 3 k -cm (2009~)
FZp ~ 25 k-cm (2010~)
Double SOI (CZn) (2012~)
Double SOI (CZp) (2014(2014~))
K. Hara, CiRfSE Nov.30, 2015

Sensor(High Resistivity)

5

筑波⼤SOIピクセル検出器開発の経緯

2005年

KEK検出器開発室（幅教授）内にSOIグループ(新井教授)
⼤学グループとして筑波⼤（原）が参加

発⾜

K. Hara et al., Radiation Resistance of SOI Pixel Devices fabricated with OKI 0.15um
FD-SOI Technology, IEEE TNS 56-5 (2009) 2896.

2009 12年 科研費「SOIピクセルによる⾼レート実験⽤薄型ピクセル」(新井-原）
2009-12年
科研費「SOIピクセルによる⾼レ ト実験⽤薄型ピクセル」(新井 原）
M. Kochiyama et al., Radiation effects in silicon-on-insulator transistors with back-gate
control method fabricated with OKI Semiconductor 0.20 um FD-SOI technology, NIM2011
K Shinsho et al.,K.
al Evaluation of Monolithic Silicon
Silicon-On-Insulator
On Insulator Pixel Devices Thinned to 100um, IEEE NS (2010)2013-17年 科研費「⾼輝度加速器実験のための素粒⼦イメージング」(坪⼭-原）S. Honda et al., Total Ionization Damage Compensations in Double Silicon-on-Insulator
Pixel Sensors, PoS(TIPP2014)
K. Hara et al., Initial Characteristics and Radiation Damage Compensation of Double
Silicon-on-Insulator Pixel Device, PoS(Vertex2014)
K. Hara et al., Development of Fine Pixel Detector for HEP Experiments Based on
Innovative Double SOI Technology, IEEE2015 NS, San Diego

放射線耐性の評価(TrTEG,INTPIX) Double SOIに焦点
放射線耐性の評価(TrTEG,INTPIX)⇒Double
微細DSOI-FPIXの製作
ILC⽤SOFISTの開発
K. Hara, CiRfSE Nov.30, 2015

6

放射線損傷 FETの ID-VGS 曲線

M. Kochiyama et al., NIM A636(2011)S62
NMOS

PMOS

●preirrad●3kGy●10kGy●20kGy●50kGy●100kGy●200kGy●preirrad●3kGy●10kGy●20kGy●50kGy●100kGyk●200kGy

VSOI2=0V

VSOI2=0V

With accumulating dose, the curves shift negatively for both PMOS andNMOS, influenced by the holes accumulated in the oxide layer.
⇒limited to a few kGy
K. Hara, CiRfSE Nov.30, 2015

7

最初のSOI全空乏化ピクセル
100 um thick INTPIX3 Cz (n)K Shinsho et al.,K.
al IEEE2010 CR N23_2
N23 2

１PixelInjectedfrom back

5μm

window
20μm

薄型化前後での暗電流の増加

K. Hara, CiRfSE Nov.30, 2015

8

CERN Test Beam (2011)

K. Shinsho 修論(2012)INTPIX3:
16x16um pixel size
Thinned to 100/50um

K. Hara, CiRfSE Nov.30, 2015

2重SOI による TID Recovery

9(SOITEC DSOI)2012~

Courtesy of Lapis SemiConductor(SHINETSU DSOI)
apply negative voltage (VSOI2) to compensate
positive chargespg in oxide layers
y++ + + + + +Middle SOI (SOI2)+ + + + + + +0V-HV

K. Hara, CiRfSE Nov.30, 2015

P-bulkSOITEC nCZSHINETSU pCZ

10Co-γ Irradiations (Double SOI): TrTEGs
Irradiation performed at RT at rate of 0.3~5kGy/h; No annealing

3kGy~2MGy (200Mrad)
18 species each for PMOS/NMOStrL[um][] W[um][]00.20510.50521.00530.20540.50551.00560.35570.35580.20590.505101.00
5110.40
10120.60
6131.00
5140.205150.50516
1.00
5CiRfSE Nov.30, 2015
17 K. Hara,1.00
5mComment
4
NVT
10
NVT
20
NVT
4
HVT
10
LVT
20
LVT
7
iohvt
7
iohvt
4
lvt_s-tie
10
lvt_s-tie
20
lvt_s-tie
4
nvt_s-tie2
10
nvt_s-tie2
20
nvt_s-tie2
4 nvt_multib-tie
10 nvt_multib-tie
20 nvt_multib-tie
20
Io_s-tie

0.5kGy~100kGy (10Mrad)
11 species each for PMOS/NMOS
TR012345678910ST1L0 20
0.20
0.20
0.40
0.35
0.20
0.35
0.35
0 40
0.40
0.35
0.35
0.40

W
55555555552.5M

11111111112

ST2COMMENT

LVT
NVT
NVT_S-TIE2
NVT_S-TEI2
NVT_S-TIE

IOHVT
IONVT

IOHVT_S-TIE2

IONVT_S-TIE2
IONVT_S-TIE
NVT_S-TIE2

11Tr characteristics recovery by VSOI2-Id-Vg curves: typical examples
Transconductance (gm): Id~ gm Vg
Threshold (Vth): Vgate@Id=(100nA)x(W/L)
Sub-threshold Swingg (S)( )(Id multiplied by 10 for
Vgate increase by S[V/dec])Th
hreshold voltageeS Honda
S.
NMOS- - - pre-irrad
pre irrad
NMOS
2MGy

PMOS

preirrad- - - prepre-irrad
irrad
PMOS
2MGy

●VSOI2= 0V ●VSOI2=-3V ●VSOI2=-10V ●VSOI2=-25V●VSOI2=-1V ●VSOI2=-4V ●VSOI2=-15V●VSOI2=-2V ●VSOI2=-5V ●VSOI2=-20V

preirradVth recoverable, but gm degraded=>limited to 100kGy (OK to ILC)

K. Hara, CiRfSE Nov.30, 2015

12 S. Honda, TIPP2014

Optimump
VSOI2 for Vth compensationp
VSOI2 to compensate for Vth to back to pre-irradiation
BFSTBTNMOS

PMOS

Noticeable differences are observed among various transistor types.
Different VSOI2 settings are preferred to compensate fully the TID forNMOS, PMOS and each body connections.

K. Hara, CiRfSE Nov.30, 2015

13S. Honda, TIPP2014

Example Vth Compensation Schema

Scheme: Average of optimum VSOI2 separately for BF and S-TIE2 for NMOS
Average of optimum VSOI2 for all types for PMOS
Residual of Vth shifts

Vth are compensable within ±0.05 V for NMOS
and with ±0.1 V for PMOS in this scheme.
Need further consideration for PMOS~2MGyK. Hara, CiRfSE Nov.30, 2015

14

Response of Irradiated Pixel Circuit

M. Asano

INTPIXh2： Integration-type pixel sensor (single VSOI2 control)
Functionality of electronics examined utilizing RESET voltage (V_RST).
STORExLOAD+V
V_RST

RSTx

STORE

VSS(GND)

COL_O
OUT

RST(sensor)

Storage
capacitor

Bias voltage = 100V
Integration Time = 120nsCharge(ADC(ADDCcount)
V COL_CCOUTC count)

READ

VDD

4500
4000

VSOI2=-2.0V

3500

100kGyRecover

3000
2500

VSOI2=-11.0V

2000
1500
1000
500
00

beforeirradiation
200 400 600 800 1000 1200 1400
V_RST (mV)

INTPIXh2 response recovered
d withith VSOI2
VSOI2.
Dynamic range is degraded since optimum VSOI2 setting depends on
the transistor types (NMOS, PMOS effectively).
Expect the dynamic range is recovered further if VSOI2 is set dependingon the transistor types.
K. Hara, CiRfSE Nov.30, 2015

15Pixel Evaluation
IR pulse laser (~10ns)
RED picosecondpulse laser

SEABAS2
12b ADCx16ch
8 parallel outputs

K. Hara, CiRfSE Nov.30, 2015

PIXEL on carrier16Response of irradiated DSOI Pixel

M. Asano

Response to infrared laser of 1064 nm wavelength
Pre-irradand 20 ns pulse duration.
VSOI2=-10V

Images after 100 kGy disappeared but
recoveredd withith VSOI2=-10V.
VSOI2 10V

Average ADC count vs. the bias voltage.
 Linearity and sensitivity after 100kGy(with VSOI2=-10V)
VSOI2= 10V) are similar to prepreirradiation
K. Hara, CiRfSE Nov.30, 2015

Charge (ADCCC count)

VSOI2=0V

6000
preirrad5000

100kGy VSOI2=-10V
VSOI2 10V

4000
3000
2000
V_RST(preirrad)=550mV
V_RST(100kGy)=950mVINT_TIME=120ns

1000
00246810 12 14 16 18 20
Sensor Bias ( V)17Rolling-shutter R/O

FPIX2: Pixel design

S. Honda

8mchip size

2 9mm x 2
2.9mm
2.9mm
9mm

Pixel size

8m x 8m

Number of pixels

128x128(Rows x columns) x blocks(128x16) x 8

Active region

1024 m x 1024 mO t tOutputs

8 parallel/1
ll l/1 globall b l

3 VSOI2 controls for pixel/decoder/IO regions

K. Hara, CiRfSE Nov.30, 2015

row address

pixel

decoder

AOUT

columncEN
N(AOUTA) address
aSpecifications

EN(AOUT)
EItem

Rolling-Shutter Parallel Readout M. Asano

Norm. R/OO sequeence

ScanTime=440ns
Bias=40VNFZ (single( i l as reference)f)
100 frames averaged
Int. Time= 440ns x[ (128/8) x127+N ]~900usRED asynchronous
laser pulse (100kHz, <1ns)Rev. R
R/O
sequuence
読み出し
読し⽅向18Int. Time= 440ns x N (N=0~15)~0-7usImages as expected from different Integration times
Eight parallel readout lines active!
K. Hara, CiRfSE Nov.30, 2015

19

Scan Time

DSOI
RO with 8 parallel ADCs240ns

Scan Time (digitization time for eachpixel) requires >200ns to keep the laser
p un-distorted.
spot
digitization by SEABAS2 12b ADCs
FPIX2 is a working DSOI device toexamine the functionality against
radiation⇒ another pixel device with pixel andcolumn amps optimized for shorter scantime is in process for fast HEP application

Scan T.
T =Scan T.
T =Scan T. =440ns

Scan T.. =Sca

440ns

Scan T.
T =200ns

M. Asano

Scan T. =120ns

80ns

Non irrad sensor
Non-irrad
Vdet = -50V
VSOI2 (IO/DEC/pix)/ /)= ((0v/0v/-0.25v)

RESETV = 1500mV19

K. Hara, CiRfSE Nov.30, 2015

20

Response to collimated IR laser M. Asano

ScanTime=440ns
Pedestal subtracted
500 frames averaged
NFZ(single)
VDET=50VSingle

IR laser (~10ns) collimated on one pixel(pixel window 2 m□)
100 DSOIfframesaveragedd
VDET=-40V

DSOI

Similar profiles for single and double
K. Hara, CiRfSEspread
Nov.30, 2015 caused by carrier diffusion, laser angle and focusing,,,

21
DSOI

Performance after 100kGy

M. Asano

VSOI2(IO/Dec/pix)= 12V/ 12V /-9.5V
VSOI2(IO/Dec/pix)=-12V/-12V/ 9 5VRSTV response: dependence on VSOI2(Dec)
Fullyy recoverable to p
pre-irrad

RSTV [mV]K. Hara, CiRfSE Nov.30, 2015

Previous DSOIINTPIXh2 w/ a single
VSOI2 control

V COL_C
COUTCharge(ADDCcount)(ADCcount)

Response to RED

4500
4000

VSOI2=-2.0V3500

Recover

3000
2500

VSOI2=-11.0V

2000
1500
1000
500
00

beforei di iirradiation
200 400 600 800 1000 1200 1400
V_RST (mV)22Improvement of PMOS gm reduction
0112kGyLDD dose: ⇒x6 nominal density
gm reduction 80%⇒20% at 112 kGyg

Effective gate length modulation by radiation
I. Kurachi,,, K. Hara, et al., IEEE Trans of Elec.Dev. 62 (2015)2371.

Sidewall spacer

gate

P+P+

LDD (lightly doped drain)
K. Hara, CiRfSE Nov.30, 2015

BOX

Vt of gate edges is notcontrolledt ll d bby VVg ddue tto holeh laccumulation in spacer

SOFIST (SOI sensor for fine measurement of Space and Time)Ono(阪⼤）demonstrator chip for ILC

K. Hara, CiRfSE Nov.30, 2015

on-pixel circuit

24

KEK MPW~ 年2回

K. Hara, CiRfSE Nov.30, 2015

25

新学術 計画研究

B01班：宇宙最初期ブラックホールの探査研究を実現す
る衛星搭載X線精密イメージングの開拓
る衛星搭載
線精密イメ ジングの開拓
B02班:「ダストに隠された宇宙の物質進化を暴く 極低温
SOI⾚外線イメージングの開拓」
C01班：⾼輝度加速器実験のための素粒⼦イメ ジング
C01班：⾼輝度加速器実験のための素粒⼦イメージング
C02班: X線⾃由電⼦レーザー(XFEL)による超⾼速ナノ構
造解析⽤検出器

A02班：SOI技術を⽤いた極低ノイズ・⾼速イメージングデバイスの研究
D02班:投影型イメージング質量分析による迅速で⾼02班 投影型イメ ジング質量分析による迅速で⾼解像度な⽣体内分⼦イメージング
K. Hara, CiRfSE Nov.30, 2015

26

まとめ
SOI Pixelの開発を初めて10年が経過
新学術科研費 進⾏中2013-17

放射線耐性評価を主導的にTID効果による限界：

数kGy

DSOIの導⼊>100kGy

LDD調整〜MGｙ（評価中）

FPIXの設計 製作（最⼩ピクセルサイズFPIXの設計・製作（最⼩ピクセルサイズ88um⾓）
⾓）

ILC⽤のSOFIST開発中
卒業論⽂
2014
2013
2012
2011
2009
2007
K. Hara, CiRfSE Nov.30, 2015

Master本多
⽯橋
橋
新庄
河内⼭、瀬賀望⽉

Senior⻘柳、関川、Subedi
浅野、前⽥、⾶⽥
本多
堀内、⼭⽥
⼩池、新庄
河内⼭ 瀬賀河内⼭、瀬賀