SOI Monolithic Pixel
Detector Technology
Sep. 29, 2016, Vertex2016@Isola d'Elba, Italy

Yasuo AraiHigh Energy Accelerator Research Organization (KEK)& The Okinawa Institute of Science and Technology (OIST)
yasuo.arai@kek.jp, http://rd.kek.jp/project/soi/1Outline
I.
II.

III.
IV.

Introduction
Recent Progress*Double SOI Wafer & Process*Higher Dose LDD*Layout Shrinking with NMOS-PMOS merge
Examples of SOI Detectors
Summary

Poster Presentations• ‘A monolithic pixel sensor with fine space-time resolution basedon silicon-on-insulator (SOI) technology for the ILC vertex
detector’, S. Ono, et al.

2

I. Introduction
Hybrid Detector
Silicon-On-Insulator (SOI)

Full Deplete(Hi-R)

Full Deplete(Hi-R)

To use SOI technology for pixel detector is alreadydiscussed in 1990(*).
(*) Jean-Pierre Colinge, 'An overview of CMOS-SOI technology and its
potential use in particle detection systems', NIM A305 (1991) 615-619.

3

Issues in SOI Pixel+++HV• Transistors does not workwith Detector High Voltage.
(Back-Gate Effect)• Circuit signal and sense nodecouples.
(Signal Cross Talk)• Oxide trapped hole inducedby radiation will shift transistor
threshold voltage.
(Radiation Tolerance)

Unfortunately, in 1990s, due to immature process
technology, no good high-resistivity SOI wafer etc. , many
SOI sensor R&D projects were stopped.
4

SmartCut (1991)

Michel. Bruel(Leti)

Become popular after 2000 (SOITEC Co.).

Layer Transfer(from SOITEC Web)

CMOS(Low R)

Sensor(High R)
5

SOIPIX Detector(Single)Single SOI Detector• Buried-Well shield back-gate potential• Good for Integration-type sensor• Relatively Low radiation applications
6

SOIPIX Detectors(Double)Double SOI Detector• Middle Si layer shields coupling between sensor and circuit.
• It also compensate E-field generated by radiation trapped hole.
• Good for Complex function and Counting-type sensor.
• Can be used in High radiation environment.
7

Features of SOI Pixel Detector• Monolithic device. No mechanical bonding.
• Fabricated with semiconductor process only.
 High reliability and Low Cost.
• High Resistive fully depleted sensor (50um~700um thick) with Low
sense node capacitance.  Large S/N.
• On Pixel processing with CMOS circuits.
• No Latch up and very low Single Event cross section.
• Can be operated in wide temperature (1K-570K) range.
• Based on Industry Standard
Technology.

8

15.3 mm

KEK SOI Multi-Project Wafer
run. (1~2 runs/year)

2015.6 Submit

2016.6 Submit

24.6 mm9

II. Recent Progress*Double SOI Wafer & Process*Higher Dose LDD*Layout Shrinking with NMOS‐PMOS merge

10Metal 5

Cross section of the Double SOI Pixel
Middle Si

Transistor

Metal 1

Middle Si
Contact

SensorContact
11

Specification of Double SOI wafer
Layer

Present Lot

Next Lot

SOI1

p‐type 88 nm,< 10  •cm
145 nmp‐type 88 nm,< 10  •cm
145 nmn‐type 150 nm,< 10  •cm
145 nmn‐type 150 nm,
3‐5  •cm
145 nm

BOX1
SOI2
BOX2

p‐typeSubstrate Low Oxygen Cz, 725um,> 1.0 k  •cm

p‐typeFZ, 725um,> 5.0 k  •cm
12

Effect of Double SOI
Cross Talk from Clock line
Single SOI

Double SOI

Shield:Cross Talk
between Circuitand Sensor is
reduced to 1/20.

(by Lu Yunpeng (IHEP))

13

Effect of Double SOI
Coupling:
Gain of Charge
Amp increases ~3times by cutting
parasitic C.

5fF

5fFSingle SOI

Double SOI

Am241
Gain
15.3uV/e-Gain
49.2uV/e-14

Gamma-ray Irradiation Test
(Id-Vg Characteristics v.s. SOI2 Potential)

I/O normal VthSource‐Tie Tr.
L/W =0.35um/5um

NMOS

100 kGy

0 kGy

Vg[V]

VSOI2=-5V
Id[A]

VSOI2=-2V
Id[A]

Id[A]

VSOI2=0V

100 kGy

0 kGy

0 kGy

Vg[V]

Vg[V]

By setting Middle Si potential (Vsoi2） to -5V, IdVg curve returned nearly to pre-irradiation value
at 100 kGy(Si) (10 Mrad).
(by U. of Tsukuba)

15

*Double SOI Wafer & Process*Higher Dose LDD*Layout Shrinking with NMOS‐PMOS merge

16Variation of Id-Vg Characteristics
and Effect of SOI2 Potential

0 kGy

0 kGy

0 kGy

100kGy100kGyVg[V]Vds=‐0.1V

Linear Id

VSOI2=-5V
Id[A]

VSOI2=-2V
Id[A]

Id[A]

VSOI2=0V

PMOS

I/O Normal Vt
Source‐Tie
L/W =0.35um/5um‐80%

Threshold voltage shift is not solarge in PMOS, but Drain Current
decreases much .

112kGy17

Radiation Effect toNMOS & PMOS

In PMOS, effective Gate Length become longer and Channel
Resistance is increased with radiation.
 Radiation Induced Gate LEngth Modulation (RIGLEM).

18

Dose Increase in Lightly Doped Drain (LDD) Region• Major cause of the drain current degradation by radiation is Vth
increase at gate edge due to positive charge generation in spacer.
• Charge in spacer control the Vth of the parasitic transistor.
• To reduce this effect, lightly doped drain (LDD) dose should beincreased.
• Present process has rather low dose in LDD region to aiming lowerpower.

Parasitic transistor
P++GateP‐+P‐

Parasitic transistor
P+BOX
LDD（Lightly Doped Drain)(by I. Kurachi)

19

Id‐Vg Characteristics in Triode Region
Present Process

LDD Dose x 6

Linear Id

Vds=‐0.1V

Vds=‐0.1V

0kGy

0kGy

112kGy112kGyWith increasing Implantation dose of PLDD region 6 times higher thanpresent value, the degradation is reduced from 80% to 20% at 112 kGy(Si).

Ref.) I. Kurachi, et al. "Analysis of Effective Gate Length Modulation by X‐Ray Irradiation for Fully
Depleted SOI p‐MOSFETs, IEEE Trans. on Elec. Dev. Vol. 62, Aug. 2015, pp. 2371‐2376.

20

*Double SOI Wafer & Process*Higher Dose LDD*Layout Shrinking with NMOS‐PMOS merge21Lapis Semi.(*) 0.2 m FD-SOI Pixel Process
Process

0.2m Low-Leakage Fully-Depleted SOI CMOS
1 Poly, 5 Metal layers.
MIM Capacitor (1.5 fF/um2), DMOS
Core (I/O) Voltage = 1.8 (3.3) V

SOIwafer

Diameter: 200 mm, 720 m thick
Top Si : Cz, ~18 -cm, p-type, ~40 nm thickBuried Oxide: 200 nm thickHandle wafer: Cz (n) ~700 -cm,FZ(n) > 2k -cm, FZ(p) ~25 k -cm etc.

Backside Mechanical Grind, Chemical Etching, Back sideprocess Implant, Laser Annealing and Al plating(*) Former OKI Semiconductor Co. Ltd.

22

SOI

Layout Shrink （Active Merge)
Bulk CMOS
PMOS

PMOS

NMOS

NMOS

ShareContacts

N-Well

P-WellIn the SOI process, it ispossible to merge NMOS
& PMOS Active regionand share contacts.

SalicideConnection
23

Single Port SRAM Bit CellBLBLB

WL
VSS

Only 1 Active region

VDDNchPch

NchCell Size : 3.94m X 3.06m = 12.06m224

New D Flip‐Flop
25% of Previous Cell

25

52um

Hexagonal Counting-type Pixel (submitted in June)

45um

Charge Amp+
Shaper+
Discriminator+
Q Share Handling+
19bit Counter+7bit register(in 2,340 um2)

Smallest Counting-type Pixel of this kind.
(much smaller than designed in 0.13um process)26

III. Examples of SOI Detectors

8.704mm

NeedleAcrylic Resin

Stent Wire(INTPIX4)
14.144mm
27

Integration type detector & 3D CTINTPIX4

Pixel Size : 17 um x 17 um
No. of Pixel : 512 x 832 (= 425,984)
Chip Size : 10.3 mm x 15.5 mm••••DriedSardineSensor：INTPIX4 FZn, Backside Illumination
HV：200V、Integration Time：1ms、ScanTime：320ns/pix, 1000frame/event
KEK PF, X‐ray Energy：9.5keV
Took images for 0~180°at every 1 degree.

(by R. Nishimura, K. Hirano (KEK)28

INTPIX4: Computed Tomography with Syncrotron X‐ray3mm(by R. Nishimura, K. Hirano (KEK)29

SOI Photon-Imaging Array Sensor (SOPHIAS)
for X-ray Free Electron Laser (XFEL) SACLA
Utilization of SOPHIAS has been started for various
experiments in SACLA@RIKEN.
• Dynamics of Atomic Structure• Direct Observation of Chemical Reactions• etc.

X-ray Tube Cu 22kV 400uA
5000 frames accumulated(total exposure: 500 s)
Sensor-detector:2m60 mm

Dual Sensor Camera
30

Stitching Exposure for Large Sensor
Mask Layout
Exposed Layout
Pixel
Blind

Blind31

SOPHIAS detector: Fluctuation of speckle pattern
Wave length: 0.155 nm
Camera length: 7.7 m
Beam E=8keV φ 30um
Detector:
SOPHIAS (30μm2 / pixel)
Frame rate:
30 Hz (readout 8ms)
Sample:200 nm Si particle in PPG

３ｍｍ0.008 nm‐1Courtesy of Prof. Masunaga and Dr. Kudo.

32

analog part

digital part

XRPIX5: Event Driven X-ray Astronomy Detector

Triggereach column line
8 setsSignal

33

XRPIX5: Event Driven X-ray Astronomy Detector
15.3 mm- Chip size : 24.6 mm x 15.3 mm- Pixel size : 36 µm sq.
- # of pixel : 608 x 384 (= ~233k)- Thickness of sensor layer : 310 µm (CZ wafer)
500 µm (FZ wafer)

13.8 mmCounts13.9 keVXRPIX5

241Am Spectrum

17.7 keV
4.1%
580 eV(FWHM)

608 x 384 pixel array1 Pixel : 36 µm sq.

24.6 mm21.9 mmPGA

Readout Noise : 48 e- (rms)Temp : -60 ºC
VBB : 100 V
35 e- (rms) of XRPIX3b.

20.8 keV

59.5 keV

26.3 keV
DECODER & TRIGGER
PROCESSOR

Pulse Height (ADU) 34

R&D for ILC Vertex Detector
SOFIST: SOI sensor for Fine measurement of Space and Time

Analog Memories &Time Stamp Memories

35

SOFIST Test Chip (Ver.2)

Submitted last June

25um x 25um

36

IV. Summary• SOI pixel technology becomes mature. Back-gate andsensor-circuit coupling issues are solved by introducing
double SOI wafer.
• Radiation tolerance is improved to more than 10 Mrad bybiasing middle Si of the DSOI and increasing the dose ofLDD region.
• NMOS-PMOS active merge reduces layout size very much.
This is almost equivalent to go to finer process while
keeping analog voltage of 0.2um process (1.8V/3.3V).
• Many kinds of SOI X-ray detectors are developed (orunder development) so far.
• New R&D for ILC pixel detector (SOFIST) is started fromlast year.

37