10th International Symposium on the Development andApplication of Semiconductor
Tracking detectors (HSTD10)

Looking with a SOI
monolithic pixel sensor
Sep. 27, 2015, HSTD10@Xi'an
Yasuo Arai (KEK)yasuo.arai@kek.jp
http://rd.kek.jp/project/soi/

from the movie 'The Mummy: Tomb of the Dragon Emperor'

1Outline
I.

Introduction

II.

Recent Progress

III.

Looking with SOI pixel

IV. Summary
X‐ray Transmission Image

Compton Electron Track2

I. Introduction

Silicon-On-Insulator Pixel Detector (SOIPIX)

Monolithic Detector having fine resolution ofsilicon process and high functionality of CMOS
LSI by using a SOI Pixel Technology.

3

Features of SOI Pixel Detector• Monolithic device. No mechanical bonding.
• Fabricated with semiconductor process only, so high reliability and low cost areexpected.
• High Resistivity fully depleted thick sensing region with Low sense nodecapacitance.
• On Pixel processing with CMOS transistors.
• 100% Fill‐Factor with Back Illumination.
• No Latch up and Low single event cross section.
• Can be operated in wide temperature (1K‐570K) range.
• Based on Industry Standard Technology.

4Lapis Semi.(*) 0.2 m FD-SOI Pixel Process
Process

0.2m Low-Leakage Fully-Depleted SOI CMOS
1 Poly, 5 Metal layers.
MIM Capacitor (1.5 fF/um2), DMOS
Core (I/O) Voltage = 1.8 (3.3) VSOIwafer

Diameter: 200 mm, 720 m thick
Top Si : Cz, ~18 -cm, p-type, ~40 nm thickBuried Oxide: 200 nm thickHandle wafer: Cz (n) ~700 -cm,FZ(n) > 2k -cm, FZ(p) ~25 k -cm etc.

Backside Mechanical Grind, Chemical Etching, Back sideprocess Implant, Laser Annealing and Al plating(*) Former OKI Semiconductor Co. Ltd.

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1st International Worksop on SOI Detector(SOIPIX2015) ＠Sendai, June 3-6, 2015

No. of Participants ~ 85

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II. Recent Progress

Double SOISingle SOI•

Shield Crosstalk•Compensate
radiation inducedoxide charge

Metal 5

Cross section of the Double SOI Pixel
Middle SiTransistor

Metal 1Sensor
Contact

Middle Si
Contact

Structure of 2 kinds of Double SOI wafer
Layer

D‐1

D‐2SOI1

p‐type 88 nm,<10 •cm
145 nmp‐type 88 nm,<10  •cm
145 nmp‐type 88 nm,<10  •cm
145 nmn‐type 150 nm,<10  •cm
145 nmn‐type CZ 725um,>700  •cm

p‐type CZ, 725um,>1.0 k  •cm

BOX1
SOI2
BOX2
Substrate

9Sheet Resistance of the Middle Si (SOI2)
VSOI2+0.2V

SOI20V
VSOI20V

Sheet resistance of themiddle Si changes dependon its potential.
D-2 wafer has lower
resistance in operation
region.

Operation Region

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Single SOI

By using Double SOI
wafer, Cross Talk
between Circuit andSensor reduced to1/20.

Double SOI

 Next Talk by Lu Yunpeng

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Gamma-ray Irradiation Test
(Id-Vg Characteristics v.s. SOI2 Potential)

I/O normal Vth
Source‐Tie Tr.
L/W =0.35um/5um

NMOS

VSOI2=-5V

100 kGy

0 kGy

Vg[V]

Id[A]

VSOI2=-2V
Id[A]

Id[A]

VSOI2=0V

100 kGy

0 kGy

0 kGy

Vg[V]

Vg[V]

By setting Vsoi2 ~ -5V, Id-Vg curve returned
nearly to pre-irradiation value at 100 kGy(Si) Poster by Mari Asano
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Variation of Id-Vg Characteristics
and Effect of SOI2 Potential

0 kGy

0 kGy

0 kGy

10Mrad10MradVg[V]Vds=‐0.1V

Linear Id

VSOI2=-5V
Id[A]

VSOI2=-2V
Id[A]

Id[A]

VSOI2=0V

PMOS

I/O Normal Vt
Source‐Tie
L/W =0.35um/5um‐80%

Threshold voltage shift is not solarge in PMOS, but Drain Current
decreases much .

112kGy13

TID Improvement for PMOSFETs• Major cause of drain current degradation by X-ray irradiation for
PMOSFETs must be Vt increase at gate edge due to positive charge
generation in spacer.
• To reduce this effect, lightly doped drain (LDD) concentration may be a keyfactor.
• When the concentration is high, impurity diffused underneath the gate andconsequently Vt of gate edge is not controlled by charge in the spacer.
• Higher LDD dose for PMOSFETs should be one of TID improvement
methods.
When LDD dope is low or P‐ is offset, possibility to form
parasitic transistor at gate edge.
Parasitic transistor

Parasitic transistor

Gate
P+P‐P‐P+

BOX
LDD（Lightly Doped Drain)(by I. Kurachi)

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Id‐Vg Characteristics in Triode Region

Linear Id

LDD Dose : 1E13cm‐2

LDD Dose : 6E13cm‐20kGy

112kGy112kGyVds=‐0.1V

With increasing Implantation dose of PLDD region 6 times higher thanpresent value, the degradation reduces 80% to 20% at 112 krad(Si).
Ref.) I. Kurachi, et al. "Analysis of Effective Gate Length Modulation by X‐Ray Irradiation for Fully Depleted SOI p‐MOSFETs, IEEE Trans. on
Elec. Dev. Vol. 62, Aug. 2015, pp. 2371‐2376.
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Removing Radiation
Induced Oxide Charge withFN Tunneling+140V (~3 s)-140V (~3 s)

VpulseGSBOXn-+D+

BPW+++PS

Radiation damage is recovered byapplying HV pulses to under‐layerof transistor.
 Poster by Miho Yamada16

Back Gate Pinning SOI Pixel(BPSPIX)• New sensor structure to deplete frombackside.
• Suppress Back Gate effect and achievesmall collection electrode.
• Low capacitance, High Gain.
• Lower surface leak current.
17III. Looking with SOI Pixel detector

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Looking Cosmic X-ray
XRPIX (SOI Pixel sensor for X-ray Astronomy)
Timing resolution of CCD is too poor to make anti‐coincidence.

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 Poster by Ito & Ohmura

XRPIX• Generate Trigger signal when a hit is occurred.
• Then X- and Y- addresses of the hit are sent out.

TriggerSignal
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Pixel Layout
MIM Cap. RST COMP2

MIM Cap. RST COMP1

1 pixel area

trigger circuit(other tr.)

BPW

30 μm

PSUB (電極)

trigger circuit(comp. 2)

trigger circuit
XRPIX3(comp. 1)

analog signal circuit

XRPIX2b

MIM Cap.

analog signal

MIM Cap. (CDS)21

History of XRPIX Noise & Gain

VeryPreliminary!
New SOI Pixel
Detector (BSPPIX)(7e‐, 30uV/e‐)
Shizuoka Univ.

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Looking XFELSOI Photon-Imaging Array Sensor (SOPHIAS)
Dual Sensor Camera for SACLA X-ray Free
Electron Laser

60 mm23XFEL Test: CoOAve.  = 22nm
t=1mm
Si Attenuation Film
Transmittance=5%

Sensor Temp.：-24℃
Exposure 1ms
HV 200V

Beamstopper

Courtesy of T. Kudo (RIKEN)
Hatsui, T., et al. (2013), Proc.
of Intl. Image Sensor
Workshop (IISW) 3.05.
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Looking 3D Fish with Synchrotron X‐rayCollimator
SampleMirrorINTPIX4•
•
•
•

Dried
SardineSensor：INTPIX4 FZn, Backside Illumination
HV：200V、Integration Time：1ms、Scan Time：320ns/pix, 1000frame/event
KEK PF, X‐ray Energy：9.5keV
Took images for 0~180°at every 1 degree.

(by R. Nishimura, K. Hirano (KEK)  [59] Development of X-ray Imaging system with SOI Pixel Detectors)

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III. Summary• SOI pixel detector is a monolithic detector which has bothradiation sensor and CMOS circuit in a single die.
• The thickness of the sensor and pixel circuit can be easily
tailored.
• Double SOI reduces cross talk between sensor and circuit.
• Radiation tolerance is improved by introducing the Double
SOI and increasing the dose of LDD region.
• Radiation induced oxide charge can be extracted with HV
pulsing in under-layer of transistors.
• Higher gain and lower noise are expected in new sensor
structure (BPSPIX).
• Many applications are being pursued within SOIPIXcollaboration.

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