SC8721 DATASHEET DRAFT
SOUTHCHIP SEMICONDUCTOR

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SC8721 High Efficiency, Synchronous, Buck-Boost Converterwith Four Integrated MOSFET
1

Descriptions

2

FeaturesSC8721 is a synchronous 4-switch buck-boost converter•

High Efficiency Buck-Boost Conversion

with four integrated switches. It is able to effectively output•

Integrated Switches, 10 mΩ for Q1/4, 20 mΩ for Q2/3

voltage no matter it is higher, lower or equal to the input•

Wide VIN Range: 2.7 V to 22 V, 25V sustainable

voltage.

•

Wide VOUT Range: 2.7 V to 22 V, 25V sustainable

SC8721 supports very wide input and output voltage range.

•

Dynamic Output Voltage Control

It can support applications from 2.7V to 22V input range and•Adjustable Switching Frequency

2.7V to 22V output range. Through its I2C interface, user•

Output Voltage Cable Drop Compensation

can program the output voltage and output current limit and•I2C Programmable Output Voltage

switching frequency. VINREG voltage can be adjusted by•

I2C Programmable Output Current Limit

external resistor.

•

Output Current Monitor•

Under Voltage Protection, Over Voltage Protection,

SC8721 employs current-mode control and supports output
current limit, dynamic output voltage adjustment, internalOver Current Protection

current limit, output short protection and over temperature•

Short Protection

protections to ensure safety under different abnormal•

Thermal Shutdown Protection

conditions.

•

QFN-21 4 x 4 Package

The IC is in a 21 pin 4x4 QFN package.

3

Applications

4

Device Information•

USB Power Delivery

Part Number

Package

Dimension•

Wall Adapter

SC8721QFER

21 pin QFN

4.0mm x 4.0mm x 0.75mm•

Type C Hub•

Industry Power Supplies

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5SOUTHCHIP CONFIDENTIAL, SUBJECT TO CHANGE

Typical Application Circuit
Rs

BT2

VOUT

SW2

SW1

BT1

VIN

VIN

VOUT

VCC

PGND
VSET
CSP
CSN

Optional
CE
VDD

AGND

COMP

CSO

SDA

SCL

FB

Host
Control

Typical application circuit 1. current sense at VOUT

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VIN

SOUTHCHIP CONFIDENTIAL, SUBJECT TO CHANGE

Rs

VOUT

VOUT

BT2

SW2

SW1

VIN

BT1

CSN

CSP

VCC
PGND

VSET
CSP
CSN

CSP
CSN

Optional
CE
VDD

AGND

COMP

CSO

SDA

SCL

FB

Host
Control

Typical application circuit 2. current sense at VIN

Note: User can place current sense resistor at VIN or VOUT according to application requirement. SC8721 constantly regulates the sense
resistor current at setting value, which is decided by internal register and CSO resistor. Please refer to Output Current Limit for current
setting specification.

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Terminal Configuration and Functions
Top View
BT2 14

NC 15

AGND 16COMP 17

FB 18

CSO 19CSN 20

CSP 21VOUT 1VOUT

PGND 2SW2

13 SW2SW1

12 SW1

PGND

VIN 3

VIN

11 BT1

10 NC

9 VCC

8 VSET

7 NC

6 SCL

5 SDA

4 CE

TERMINAL
I/O

DESCRIPTIONNUMBER

NAME

1

VOUT

I/O

The power output node of the converter.

2

PGND

I/O

Power ground. User shall connect PGND and AGND together on PCB.

3

VIN

I/O

the power input node of the converter.

4

CE

I

Chip enable pin, active high: pull this pin to logic low to disable the chip. This pin is internallypulled high.

5

SDA

I/O

I2C interface data. Connect SDA to the logic rail through a pull up resistor (typical 10 kΩ).

6

SCL

I

I2C interface clock. Connect SCL to the logic rail through a pull up resistor (typical 10 kΩ).

7

NC

8

VSET

IO

VINREG internal 1.2V voltage reference. Set the VINREG voltage by resistor divider from to this
pin

9

VCC

O

Output of an internal regulator. Connect a 2.2 µF ceramic capacitor from VCC to PGND pin close
to the IC. The regulator provides supply for internal gate drivers.

Must be floating

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10

NC

Must be floating

11

BT1

I

Connect a 100nF ceramic capacitor between BT1 pin and SW1 pin to provide the boosted bias
voltage for high side gate driver.

12

SW1

I/O

Switching Node 1. Connect to inductor.

13

SW2

I/O

Switching Node 2. Connect to inductor.

14

BT2

I

Connect a 100nF ceramic capacitor between BT2 pin and SW2 pin to provide the boosted bias
voltage for high side gate driver.

15

NC

16

AGND

I/O

Analog ground. User shall connect PGND and AGND together on PCB.

17

COMP

I

Connect a RC network to compensate the control loop.

18

FB

I

Feedback node of VOUT output voltage. Set the VOUT output voltage by the resistor divider
connected at this pin.

19

CSO

O

Use this pin to monitor the current sensed by CSP and CSN pin. The voltage of CSO is
proportional to the sense current.

20

CSN

I

Negative input of an internal current sense amplifier. Connect a current sense resistor (typical 10mΩ) between CSP and CSN to sense the current.

21

CSP

I

Positive input of an internal current sense amplifier. Connect a current sense resistor (typical 10mΩ) between CSP and CSN to sense the current.

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7Specifications

7.1

Absolute Maximum Ratings

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over operating free-air temperature range (unless otherwise noted) (1)
MIN

MAX

Unit

CE, SDA, SCL, CSEL, VSET, COMP, CSO, FB

-0.3

5.5

V

VCC

-0.3

6.5

V

VIN, VOUT, CSP, CSN

-0.3

25

V

SW1, SW2

-0.3

25

V

BT1, BT2

-0.3

32

V

CSP to CSN

-10

10

V

BT1 to SW1, BT2 to SW2

-0.3

6.5

V

TJ

Operating junction temperature range

-40

150

°C

Tstg

Storage temperature range

-65

150

°C

Voltage range atterminals(2)(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to network ground terminal.

7.2

Thermal Information(TBD)

THERMAL RESISTANCE(1)QFN-21 (4mmX4mm)

UNIT

θJA

Junction to ambient thermal resistance

TBD

°C/W

θJC

Junction to case resistance

TBD

°C/W

(1)

Measured on JESD51-7, 4-layer PCB.

7.3

Handling Ratings

PARAMETER

DEFINITIONMIN

Human body model (HBM) ESD stress voltage(2)

MAX

UNIT

-2

2

kV

-750

750

V

ESD(1)(3)

Charged device model (CDM) ESD stress voltage(1)

Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic
discharges into the device.

(2)

Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM
allows safe manufacturing with a standard ESD control process.

(3)

Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows
safe manufacturing with a standard ESD control process.

7.4

Recommended Operating Conditions
MIN

MAX

UNIT

VIN

VIN voltage range

2.7

22

V

VOUT

VOUT voltage range

2.7

22

V

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CIN, COUT

VIN Capacitance, VOUT capacitance

30

L

Inductance

2.2

10

µH

RS

Current Sense Resistor

5

10

mΩ

RCSO

Current Limit setting resistor

64

KΩ

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µF

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7.5

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Electrical Characteristics(TBD)

TJ= 25°C and VIN = 12V, Rs=10mΩ, Rcso=64kΩ unless otherwise noted.
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE
VUVLO

VIN
under-voltage
threshold

IQ

Quiescent current into VIN

ISHUTDOWN

Shutdown current VINISTANDBY

Standby current from VIN

lockout

Rising edge

2.5

V

Hysteresis

160

mV

1.5

mA

VIN = 8V, CE = L

5.5

μA

Standby mode (Reg0x05<2>=1),
VIN=8V, CE=H

30

μA

VIN = 8V, VOUT = 5V
CE = H, non-switching

VCC, DIRVER AND POWER SWITCH

VCC

VCC regulation voltage

IVCC_LIM

VCC current limit

RDSon_HS
RDSon_LS

VIN = 9V

4.4

VIN= 5V, ICC = 30mA

4V

VIN= 6V, ICC = 1mA,
(Reg0x05<2>=1)

4.2

V

VIN = 9V, VCC = 4V

5

5.5

V

80

mA

High side MOS on resistance10mΩ

Low side MOS on resistance

20mΩ

REFERENCE VOLTAGE FOR VOUTVFB

FB reference voltage

0.99

1

VFB_OVPFB OVP threshold, over FB target

VINOVP

Absolute OVP threshold for VIN

23

V

VSHORT

Short circuit detection threshold

2.4

V

VINREG_REF

VSET reference voltage

1.2

V

Rising edge

110%

Hysteresis

2%

1.01

V

CURRENT LIMIT
ILIM

Output current limit accuracy

IOCP

Internal current limit

IOUT RS ≥ 20mV

5%

-5%
10

A

ERROR AMPLIFIER
GmEA

Error amplifier gm

0.16

mS

ROUT

Error amplifier output resistance20

MΩ

ISINK_COMP

COMP sink current

27

μA

ISRC_COMP

COMP source current

16

μA

IBIAS_FBFB pin input bias current

FB in regulation

50

nA

LOGIC CONTROL
RPH

CE pin internal pull high resistor

VIL

CE pin input low voltage

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2

MΩ
0.4

V

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VIH

SOUTHCHIP CONFIDENTIAL, SUBJECT TO CHANGE

CE pin input high voltage

1.2

V

Frequency

Fsw

Switching frequency

REG08 = 0x00

260

kHz

REG08 = 0x01(default)

500

kHz

REG08 = 0x02

720

kHz

REG08 = 0x03

920

kHz

From 10% to 90% VOUT

15

ms

SOFTSTARTtSS

Internal soft-start timeI2C INTERFACE (SDA, SCL)
VILSDA/SCL logic low input voltage
level

VPULL_UP = 3V

VIH

SDA/SCL logic high input voltage
level

VPULL_UP = 3V

2

V

ISINK_SDA

SDA sink current

VSDA = 0.4 V

20

mA

fSCL

I2C clock frequency

0.4

400

V

kHz

THERMAL SHUTDOWN
TSD

Thermal shutdown temperature (1)Thermal shutdown hysteresis(1)

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160

°C

30

°C

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8

Feature Description

8.1

Chip Enable

8.3.3

The IC is enabled or disabled by CE signal. When CE input
is logic high, the IC is enabled; when CE input is logic low,
the IC is disabled. The CE pin is pulled high by 2 MΩ resistor
internally.

8.2

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Soft Start

The IC implements soft start feature to prevent inrush
current during startup in discharging mode. After thedischarging mode is enabled, the IC ramps up the internalreference voltage in around 15ms. The output voltage
follows the reference, so it starts up slowly. Meantime, the IC
ramps up the current limits during the startup. If a heavy load
is applied before the output voltage is established, the IC
may fail to start up due to the current limit.

Dynamic Output Control

In discharging mode, output voltage can be set via IIC. In IIC,
there’s a load function, after Load is set to 1, VOUT starts toramp at the speed of 1mV/us.
8.3.4
Cable drop compensation
VOUT has a cable drop compensation. The slope can be
programmed via I2C registers. If external feedback resistor
is applied, Rup must be 100K to have the designed slope.

8.4

Output Current Limit

The output current limit can be set by internal register andexternal resistor.
IOUT_LIM=(CSO_SET + 1) ∗ 4mV ∗ 2kΩ
RS*RCSO

where
CSO_SET is reference voltage, set by Reg 0x01<7:0>;

8.3

Output Voltage Setting

8.3.1

External Setting method

RS = Current sense resistor value to sense output current;

When FB_SEL signal is 0, the output voltage is set by theresistor divider connected at FB pin and can be calculated
as below.
VOUT = VFB_REF x (1+

RUP
)
RDOWN

Where:
VFB_REF is the internal reference voltage 1V, RUP and RDOWN
are the resistors connected from VOUT to FB and to AGND.
8.3.2

Rcso = Resistors at CSO pin;Internal Setting method

When FB_SEL signal is 1, the out voltage can be
programmed internally via IIC. VOUT offset voltage isdecided by 10-bit register (Reg03<7:0> and Reg04<1:0>), a
20mV/step resolution is given.

When output is overload, the IC regulates the output current
at setting current limit value and output voltage decreases
automatically.

8.5

Output Current Monitor

In discharging mode, the output current can be monitored inreal time through CSO pin.
IOUT=

VCSO ∗ 2kΩ
RS*RCSO

where
VCSO is voltage of CSO pin;
RCSO = Resistors at CSO pin;
RS = Current sense resistor value to sense IOUT current;

OFFSET= [Reg03<7:0> x 4 + Reg04<1:0>] x 20mV

FB_ON is the mask control bit of VOUT_REF register. Only
when FB_ON=1, the VOUT_REF register value is valid, the
VOUT voltage is 5V default. FB_DIR is the direction controlbit.
If FB_DIR=0, the VOUT voltage is:
VOUT = 5V + OFFSET

If FB_DIR=1, the VOUT voltage is:
VOUT = 5V - OFFSET

8.6

Self-adaptive Input Voltage Regulation

The IC features dynamic VIN power management. The
allowed minimum VIN operation voltage is VINREG
threshold, which can be set by resistor divider at the VSET
pin. During charging, if the output current is higher than
VIN’s current capability, the input source will be overloaded,
and the VIN voltage is pulled low. Once the VIN voltage
drops at VINREG threshold, the IC reduces the output
voltage automatically and regulates the VIN voltage at
VINREG threshold. the VINREG voltage is set by the resistor
divider connected at VSET pin and can be calculated as
below.

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VINREG = VSET_REF x (1+

RUP
)
RDOWN

SOUTHCHIP CONFIDENTIAL, SUBJECT TO CHANGE
and is clamped to 5V. Connect a 2.2µF ceramic capacitor
from VCC to PGND pin close to the IC.

Where:
VSET_REF is the internal reference voltage 1.2V, RUP and
RDOWN are the resistors connected from VIN to VSET and to
AGND.
Connect VSET pin with 10kΩ pull-up resistor to VCC, or set
Reg06<4> to 0, VINREG function is disabled.

8.7

Register Load function

When output current limit and output voltage register value isset via I2C, Load bit (Reg0x05<1>) must be set to 1, thenvalue can be loaded to corresponding registers.

8.8

PWM/PFM Operation

The IC supports two operation modes: PWM mode and PFM
mode.
In PWM mode, the IC always works with constant switchingfrequency for the whole load range. This helps achieve thebest output voltage performance, but the efficiency is low atlight load condition because of the high switching loss.
In PFM mode, the IC still works with constant switchingfrequency under heavy load condition, but under light loadcondition, it changes to pulse frequency modulation
operation to reduce the switching loss. The efficiency can be
improved under light load condition while output voltage
ripple will be a little larger compared with PWM operation.
Below figure shows the output voltage behavior of PFM
mode.

8.11 Loop Compensation
The internal control loop should be compensated by theresistor and capacitor connected at COMP pin. 10 kΩ
resistor and 22 nF capacitor are suggested for mostapplications. If faster response is required, the user canincrease the resistor value but should keep R*C value
unchanged. After changing the compensation, check andmake sure the loop is stable under target conditions.

8.9 Standby Mode
When CE signal is high and DIS_DCDC bit is 1, the IC
enters into Standby mode. In this mode, the IC stops
switching to save the quiescent current. The other functions
are still valid, and the MCU can still control the IC throughI2C.

8.10 Shutdown Mode
When CE signal is low, the IC enters into Shutdown mode.
In this mode, the IC stops working and disables the I2C
interface to save the power.

8.12 Protections
8.12.1

Over Voltage Protection

The IC supports three mechanisms for over voltage
protection.
The first is once the IC detects the VIN voltage is higher thantypical 23V, the IC stops switching until the voltage drops
below the threshold.

PFM operation at light load

PFM VOUT

Vout
Normal VOUT

The second is once the IC detects the VOUT voltage ishigher than the setting target by typical 10%(FB_SEL=0), theIC stops switching until the voltage drops below thethreshold.

Change to PWM operation at heavy load

Figure 1 PFM operation

8.9

Switching Frequency

The SC8721 provides four switching frequency selection
from 230kHz/500kHz/690kHz/920kHz.

8.10 VCC Driver Voltage

The third is once the IC detects the VOUT voltage is 500mV
higher than the setting target (FB_SEL=1), the IC stops
switching until the voltage drops below the threshold.
8.12.2

Over Current Protection

The IC implements internal current limit at 10A. Once the IC
detects the inductor current is higher than 10A, it reduces
the switching duty cycle, and keeps the inductor current fromincreasing.

The IC integrates a VCC regulator so to generate the drivervoltage for internal driver circuit. The VCC is supplied by VIN
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8.12.3

Output Short Circuit Protection

The IC supports FB pin short circuit protection when external
divider resistor is applied to adjust voltage in discharging
mode. During power on, the IC monitors the FB pin status.
Once it detects the FB pin is short to ground, it still starts up
and limits the VOUT voltage at 5V fixed voltage. This helps
protect the circuits connected at VOUT pin from over voltage
stress.
Besides FB short circuit protection, the IC also monitors the
VOUT voltage all the time. Once it detects the VOUT voltage
drops below short circuit protection threshold, typical 2.4V,
the IC begins to hiccup.
8.12.48.13.1.2 START and STOP Conditions
All transactions begin with a START (S) and are terminatedby a STOP (P). A HIGH to LOW transition on the SDA line
while SCL is HIGH defines a START condition. A LOW to
HIGH transition on the SDA line while SCL is HIGH defines a
STOP condition.
START and STOP conditions are always generated by themaster. The bus is considered to be busy after the START
condition. The bus is considered to be free again a certain
time after the STOP condition.

Over Temperature Protection

Once the IC detects the chip junction temperature exceeds
the threshold (160°C typical), the IC goes into thermal
shutdown and stops switching. When the junction
temperature falls below typical 130°C, the IC resumes
operation.

8.13 I2C and Registers
8.13.1

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I2C Interface

The IC features I2C interface, so the MCU or controller cancontrol the IC flexibly. The 7-bit I2C address of the chip is
0x62 (8-bit address is 0xC4 for write command, 0xC5 forread command). The SDA and SCL pins are open drain andmust be connected to the positive supply voltage via acurrent source or pull-up resistor. When the bus is free, bothlines are HIGH. The I2C interface supports both standard
mode (up to 100kbits) and fast mode (up to 400k bits with 5kΩ pull up resistor at SCL pin and SDA pin respectively).

Figure 3 START and STOP conditions
8.13.1.3 Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer isunrestricted. Each byte must be followed by an Acknowledgebit. Data is transferred with the Most Significant Bit (MSB)
first. If a slave cannot receive or transmit another complete
byte of data until it has performed some other function, forexample servicing an internal interrupt, it can hold the clock
line SCL LOW to force the master into a wait state. Datatransfer then continues when the slave is ready for anotherbyte of data and releases clock line SCL.

8.13.1.1 Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW. One clock pulse is generated for each data bittransferred.

Figure 4 Data transfer on the I2C bus
8.13.1.4 Acknowledge (ACK) and Not Acknowledge(NACK)
The acknowledge takes place after every byte. The
acknowledge bit allows the receiver to signal the transmitterthat the byte was successfully received and another byte
may be sent. During data is transferred, the master caneither be the transmitter or the receiver. No matter what it is,
the master generates all clock pulses, including theacknowledge ninth clock pulse.

Figure 2 Bit transfer on the I2C bus

The transmitter releases the SDA line during theacknowledge clock pulse so the receiver can pull the SDA
line LOW and it remains stable LOW during the HIGH periodof this clock pulse.

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When SDA remains HIGH during this ninth clock pulse, thisis defined as the Not Acknowledge signal. The master canthen generate either a STOP condition to abort the transfer,or a repeated START condition to start a new transfer.

SOUTHCHIP CONFIDENTIAL, SUBJECT TO CHANGE
8.13.1.6 Single Read and Write

8.13.1.5 The slave address and R/W bit
Data transfers follow the format shown in below. After the
START condition (S), a slave address is sent. This address
is seven bits long followed by an eighth bit which is a data
direction bit (R/W) — a ‘zero’ indicates a transmission(WRITE), a ‘one’ indicates a request for data (READ). A datatransfer is always terminated by a STOP condition (P)generated by the master. However, if a master still wishes tocommunicate on the bus, it can generate a repeated START
condition (Sr) and address another slave without first
generating a STOP condition.

Figure 7 Single Wite

Figure 8 Single Read
If the register address is not defined, the charger IC sendback NACK and go back to the idle state.
8.13.1.7 Multi-Read and Multi-Write
The IC supports multi-read and multi-write for continuous
registers.

Figure 5 A complete data transfer

Figure 9 Multi-Write

Figure 6 The first byte after the START procedure

Figure 10 Multi-Read

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9Application Information (TBD)

9.1

Input and Output Capacitor Selection

Since MLCC ceramic capacitor has good high frequency
filtering and low ESR, X5R or X7R capacitors arerecommended for input and output capacitors. Typically,
three 22 μF ceramic input capacitors and three 22 μF
ceramic output capacitors work for most applications. The
input / output capacitors should be places as close to VIN /CSN pins as possible, and they should be also near the
PGND pins or thermal pad.
Capacitors’ derating effect under DC bias should be taken
into account when selecting the capacitors. Ceramic
capacitor normally loses its most capacitance at the rated
voltage, so leave margin on voltage rating to ensure
adequate effective capacitance. For example, if the highest
operating voltage is 12V, select 16V or 25V capacitor.

SOUTHCHIP CONFIDENTIAL, SUBJECT TO CHANGE
inductor like 4.7 μH to 10 μH is recommended for
applications where the difference between input voltage andoutput voltage is big, such as 5V to 20V; while for those
applications where input voltage is close to output voltage
but large current is on power path, low value inductor like
2.2 μH is suggested.
For applications where efficiency or thermal dissipation isvery important, it is highly suggested that the user chooses
the inductor in larger package size for lower DCR, and also
tests the efficiency with different inductor values, so to findthe best combination to achieve the highest efficiency.
The saturation current is another important parameter whenselecting the inductor. The inductance can decrease 20% to
35% when the current approaches saturation level, so theuser should make sure the saturation current is higher than
the inductor peak current during the operation.
The inductor peak current can be calculated by below
formula.

Besides this, high value electrolytic capacitor or tantalum
capacitor is recommended to place in parallel with theceramic capacitors at output to improve the load transient
response.

9.2

IL_peak = IIN +IL_peak = IOUT +The IC can work with inductors between 2.2 μH to 10 μH
range for most applications. A higher value is suggested tokeep the inductor current ripple ≤ 30% of the DC current.
Compared with high value inductor in the same package
size, a lower value inductor normally has smaller DC
resistance (DCR), so can reduce the conduction power loss,
which can be calculated roughly as
PL_DC = IL2 ∙DCR

IL is the average value of inductor current, and it equals to
IIN or IOUT.
However, besides DCR, the core loss or AC loss of an
inductor also affects the power efficiency a lot. The low
value inductor causes large inductor current ripple, thus highcore loss or AC loss, so it is not always the low value
inductor supports the higher efficiency.
Since the core loss is related to the inductor material type,and normally the inductor vendors don’t provide the coreloss data, it is very difficult to suggest what inductor value
can result in higher efficiency. As a rule of thumb, high value

2∙fsw∙L∙VOUT(VOUT≥VIN)

VOUT∙(VIN - VOUT)(VOUT<VIN)

2∙fsw∙L∙VIN∙η

Inductor Selection

Because the selection of inductor affects the loop stability
and the power efficiency, inductor is one of the mostimportant components for the DCDC design.

VIN∙(VOUT-VIN∙η)𝜂 is the power conversion efficiency. User can use 90% forcalculation.
fsw is the switching frequency
L is the inductor value
When selecting inductor, the inductor saturation current
must be higher than the peak inductor current with enoughmargin (20% margin is recommended). The rating current of
the inductor must be higher than the output current.

9.3

Current Sense Resistor

The RS in the typical application circuit are current sense
resistors for current limit functions.
A high resistor value can result in high current limit / monitor
accuracy but causes high conductor loss. Typically, 10 mΩ
is recommended. But for applications where efficiency ismore important than accuracy, lower value is suggested.
When selecting the current sense resistor, its power rating
and temperature coefficient should also be considered.
The power dissipation can be roughly calculated as P=I2R,
where I is the highest current flowing through it. The power
rating should be higher than the calculated value.

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The resistor value varies with temperature and the variation
is decided by its temperature coefficient. If high accuracy oflimit or monitor is required, select as lower temperature
coefficient as possible.

9.4

Snubber Circuit

The RC snubber circuits at SWx nodes as shown below canbe used to suppress the switching spike so to improve the
EMC performance. A typical snubber circuit is composed by
a 2.2Ω resistor and 1nF capacitor. The user can reduce theresistance and increase the capacitance further to improve
the EMC. However, because it often causes higher
switching loss and results in lower efficiency, it is suggested
not to add snubber circuits unless necessary.

SW1

SW2

Figure 15 Snubber circuit at SWx nodes
The IC also allows user adding a driver resistor for the low
side MOSFET at VOUT side to slow down the switching,thus to reduce the switching spike improve the EMC
performance. However, because the driver resistor also
causes higher switching loss and thus lower efficiency, it issuggested not to add the driver resistor unless necessary.
If the driver resistor is needed, a 0603 resistor should be
used, and it should be placed near the IC.

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10 Register Map
Addr

RegisterType

Default value
@POR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01H

CSO

R/W

1111 0000

02H

SLOPE_COMP

R/W

xxxx xx00

CSO_SET

03H

VOUT_SET_MSB

R/W

0000 0000

04H

VOUT_SET_LSB

R/W

xxx0 0000

05H

GLOBAL_CTRL

R/W

xxxx x000

06H

SYS_SET

R/W

00x1 xxxx

07H

RESERVED

R/W

xxxx xxxx

08H

FREQ_SET

R/W

0000 0001

09H

STATUS_1

R

0000 0000

VOUT_SHORTVOUT_VIN_H

RESERVEDRESERVEDTHD

RESERVEDRESERVEDOCP

0AH

STATUS_2

R

0000 0000

VINOVPRESERVEDRESERVEDRESERVEDRESERVED

VINREG_FLAG

IBUS_FLAGRESERVEDRESERVED

SLOP_COMP
VOUT_SET_MSB

RESERVEDFB_SELFB_ON

RESERVED
EN_PWM

EXT_DT

RESERVEDFB_DIR
DIS_DCDC

EN_VINREG

VOUT_SET_LSB
REG_LOAD

RESERVEDRESERVEDRESERVEDRESERVED

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Table 1 0x01H CSO_SET Register
Bit

Mode

Bit Name

7-0

R/W

CSO voltage
setting

Default value@POR
1111 0000

Description

Notes

CSO_SET used to set VOUT current reference limit
The output current limit is calculated as:
IOUT_ILIM =(CSO_SET+1)*4mV*2kΩ
Rs*RCSO

CSO_SET isclamped tobe higher
than 0x08
internally.

CSO_SET range:0~255
0000 0000: 00000 0001: 10000 0010: 2….
1111 0000: 240 (default)….
1111 1111: 255

Table 2 0x02H SLOPE_COMP Register
Bit

Mode

Bit Name

Default value
@POR

7-2

R/W

Reserved

0000001-0

R/W

SLOPE_COMP

00

Description

Notes

Internal use. Don’t overwrite this bit.
SLOPE_COMP is used to set VOUT cable dropcompensation
00: no slope compensation (default)
01: 50mV/A
10: 100mV/A
11:150mV/A

Table 3 0x03H VOUT _SET_MSB Register
Bit

Mode

Bit Name

7-0

R/W

VOUT_SET_MSB

Default value@POR
000000Description

Notes

The highest 8-bit of the VOUT_ SET.
VOUT_SET_MSB and VOUT_SET_LSB are used to set
VOUT_SETThe VOUT_SET is calculated as:
VOUT_SET = VOUT_SET_MSB x4+VOUT_SET_LSB) x 20mV

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Table 4 0x04H VOUT_SET Register
Bit

Mode

Bit Name

Default value@POR

Description

7-5

R/W

Reserved

000

Internal use. Don’t overwrite this bit

4

R/W

FB_SEL0

VOUT voltage setting control, only for discharging mode:

Notes

0: External VOUT setting, VOUT output voltage is set byresistor divider at FB pin
1: Internal VOUT setting, VOUT output voltage is set by
VOUT _SET_MSB, VOUT _SET_LSB and FB_DIR
3

R/W

FB_ON

0

VOUT_SET mask bit
0: VOUT voltage is not allowed to be revised
1: VOUT voltage is allowed to be revised

2

R/W

FB_DIR0

VOUT_SET_direction:
0: Increment(default)
1: Decrement

1-0

R/W

VOUT_SET_LSB

00

The lowest 2-bit of the VOUT_SET

Table 5 0x05H GLOBAL_CTRL Register
Bit

Mode

Bit Name

Default value
@POR

7-3

R/W

Reserved

0000

2

R/W

DIS_DCDC

0

Description

Notes

Internal use. Don’t overwrite this bit
DCDC switching control:
0: enable(default)
1: disable

1

R/W

Load

0

Write 1 to load register (CSO_SET/VOUT_SET /FB_DIR)
and clear to 0 automatically after read0

R/W

Reserved bit

0Internal use. Don’t overwrite this bit

Table 6 0x06H SYS_SET Register
Bit

Mode

Bit Name

Default value@POR

Description

7

R/W

EN_PWM

1

EN_ PWM:

Notes

0: disable, auto pwm mode
1: enable, force pwm mode(default)
6

R/W

EXT_DT0

Switching dead time setting:
0: 20ns(default)
1: 40ns

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5

R/W

Reserved bit

0Internal use. Don’t overwrite this bit

4

R/W

EN_VINREG

1

VINREG enable control:
0: disable
1: enable（default）

3-0

R/W

Reserved bit

0000

Internal use. Don’t overwrite this bit

Table 7 0x07H TERM_SET Register
Bit

Mode

Bit Name

Default value
@POR

7-0

R/W

Reserved bit

00000000

Description

Notes

Internal use. Don’t overwrite this bit

Table 8 0x08H FREQ_SET Register
Bit

Mode

Bit Name

Default value
@POR

7-2

R/W

Reserved bit

0000001-0

R/W

Frequency set

01

Description

Notes

Internal use. Don’t overwrite this bit
Switching frequency setting:
00: 260kHz
01: 500kHz(default)
10: 720kHz
11: 920kHz

Table 9 0x09H STATUS_1 Register
Bit

Mode

Bit Name

Default value@POR

Description

7

R

VOUT SHORT0

1: VOUT<0.7V happens

6

R

VOUT_VOUT_H

0

0: VOUT < VIN

Notes

1: VOUT > VIN
5

RReserved bit

0Internal use. Don’t overwrite this bit

4

R

Reserved bit

0Internal use. Don’t overwrite this bit

3

R

THD

0

1: Thermal shutdown

2

R

Reserved bit

0Internal use. Don’t overwrite this bit

1

R

Reserved bit

0Internal use. Don’t overwrite this bit

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0

R

OCP

0

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1: Internal over current protection happens

Table 10 0x0AH STATUS_2 Register
Bit

Mode

Bit Name

Default value@POR

Description

7

R

VINOVP

0

1: VIN higher than absolute voltage threshold (22V) happens

6

R

Reserved bit

0Internal use. Don’t overwrite this bit

5

R

Reserved bit

0Internal use. Don’t overwrite this bit

4

R

Reserved bit

0Internal use. Don’t overwrite this bit

3

R

Reserved bit

0Internal use. Don’t overwrite this bit

2

R

VINREG_FLAG0

1: IC working in VINREG loop

1

R

IBUS_FLAG0

1: IC working in current limit loop

0

R

Reserved bit

0Internal use. Don’t overwrite this bit

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Notes

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QFN-21 (4x4x0.75)

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RECOMMENDED FOOTPRINT
QFN-21 (4x4x0.75)(Unit: mm)

0.85

0.7

2.2

1.175

1
0.4

0.9

0.9

0.3

3.1 4.8

0.725

0.3

0.4

0.25

4.8

Copyright © 2019, Southchip Semiconductor Technology (Shanghai) Co., Ltd.

22