S-19114xxxA Series
www.ablic.com

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR
WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION,
DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00© ABLIC Inc., 2023

This IC, developed using CMOS technology, is a high-accuracy voltage detector. The detection voltage and release voltage
are fixed internally with an accuracy of ±1.5%.
Since the detection response time is as fast as 10 μs max., voltage abnormalities can be detected and notified quickly.
Apart from the power supply pin, the detection voltage input pin (SENSE pin) is also prepared, so the output is stable even if
the SENSE pin voltage (VSENSE) falls to 0 V. The SENSE pin also has a built-in reverse connection protection circuit that
reduces current in the SENSE pin during a reverse connection.
The release signal can be delayed by setting a capacitor externally, and the release delay time accuracy is ±20% (CD =3.3 nF). The output form is Nch open-drain output.
ABLIC Inc. offers FIT rate calculated based on actual customer usage conditions in order to support customer functionalsafety design.
For more information regarding our FIT rate calculation, contact our sales representatives.
CautionThis product can be used in vehicle equipment and in-vehicle equipment. Before using the product forthese purposes, it is imperative to contact our sales representatives.

 Features• Detection voltage:
4.0 V to 12.0 V (0.05 V step)• Detection voltage accuracy:±1.5%• Hysteresis width selectable from "Available" / "Unavailable":"Available": 2.0%, 5.0%, 10.0%"Unavailable": 0%• Detection response time:
10 μs max. (S-19114 Series L / M / N / R type)25 μs max. (S-19114 Series P / Q / S / T type)• Release delay time:
10 ms typ. (CD = 3.3 nF)• Release delay time accuracy:±20% (CD = 3.3 nF)• Current consumption:
2.0 μA typ.
• Operation voltage range:
3.0 V to 36.0 V• Output form:
Nch open-drain output• Built-in reverse connection protection circuit: Reduces current in the SENSE pin during a reverse connection.
• Operation temperature range:
Ta = −40°C to +125°C• Lead-free (Sn 100%), halogen-free• Withstand 45 V load dump
• AEC-Q100 qualified*1*1.

Contact our sales representatives for details.

 Applications

 Detection response time Packages• SOT-23-5• HSNT-6(2025)

VSENSE, VOUT [V]• Automotive battery voltage detection• For automotive use (engine, transmission, suspension,
ABS, related-devices for EV / HEV / PHEV, etc.)

VDET(S) = 8.0 V, VHYS = 5.0 %, VDD = 13.5 V,
VSENSE = VDET(S) + 1.0 V→VDET(S) − 1.0 V,
pull-up to VDD, pull-up resistance : 100 kΩ
16
14
12
10
VSENSE
8
6
4
VOUT
2
0
-2
0
4
6
8
10 12
2
t [µs]

1

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19114xxxA Series
Rev.1.2_00
 Block Diagrams
1.

S-19114 Series L / P type
SENSE

VDD
OUT

+
*1

−

Delay
circuit

VREF

*1

*1

VSS

CD

*1.

Parasitic diodeFigure 1

Product TypeL typeP type2

Detection Response Time
10 μs max.
25 μs max.

Hysteresis Width0%0%

Output FormNch open-drain output
Nch open-drain output

Output Logic
Active "L"
Active "L"AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00
S-19114xxxA Series
2.

S-19114 Series M / N / R / Q / S / T type
SENSE

VDD
OUT
*1

Delay
circuit

+
−
VREF

*1

*1

VSS

CD

*1.

Parasitic diodeFigure 2

Product TypeM typeN typeR typeQ typeS typeT typeDetection Response Time
10 μs max.
10 μs max.
10 μs max.
25 μs max.
25 μs max.
25 μs max.

Hysteresis Width
2.0%
5.0%
10.0%
2.0%
5.0%
10.0%

Output FormNch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output

Output Logic
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"3

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19114xxxA Series
Rev.1.2_00
 AEC-Q100 Qualified
This IC supports AEC-Q100 for operation temperature grade 1.
Contact our sales representatives for details of AEC-Q100 reliability specification.

 Product Name Structure
1.

Product name
S-19114 x

xx A - xxxx U 7

Environmental codeU:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
M5T1: SOT-23-5, Tape
A6T8: HSNT-6(2025), Tape
Operation temperatureA:
Ta = −40°C to +125°C
Detection voltage
40 to C0(e.g., when the detection voltage is 4.0 V,
it is expressed as 40.
when the detection voltage is 12.0 V,
it is expressed as C0.)
Product type*2

*1.
*2.

2.

Refer to the tape drawing.
Refer to "2. Function list of product types".

Function list of product types
Table 1
Product TypeL typeM typeN typeR typeP typeQ typeS typeT type3.

Detection Response Time
10 μs max.
10 μs max.
10 μs max.
10 μs max.
25 μs max.
25 μs max.
25 μs max.
25 μs max.

Hysteresis Width
0%
2.0%
5.0%
10.0%
0%
2.0%
5.0%
10.0%

Pin Output FormNch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output

Output Logic
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"

Packages
Table 2 Package Drawing Codes

Package Name
SOT-23-5
HSNT-6(2025)

4

Dimension
MP005-A-P-SD
PJ006-B-P-SD

Tape
MP005-A-C-SD
PJ006-B-C-SD

Reel
MP005-A-R-SD
PJ006-B-R-SD

Land−
PJ006-B-LM-SD

Stencil Opening−
PJ006-B-LM-SD

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00
S-19114xxxA Series
 Pin Configurations
1.

SOT-23-5
Table 3Top view

Pin No.
12
3
45Symbol
OUT
VSS
CD*1
SENSE
VDD

Description
Voltage detection output pin
GND pinConnection pin for release delay time adjustment capacitor
Detection voltage input pin
Voltage input pin

Figure 3*1.

2.

Connect a capacitor between the CD pin and the VSS pin. The release delay time can be adjusted according to
the capacitance.
Moreover, the CD pin is available even when it is open.

HSNT-6(2025)
Top view
1
2
3

Table 4
6
5
4

Bottom view
6
5
4

1
2
3

Pin No.
1
2
3
4
5
6

Symbol
VDD
NC*2
SENSE
CD*3
VSS
OUT

Description
Voltage input pin
No connection
Detection voltage input pin
Connection pin for release delay time adjustment capacitor
GND pin
Voltage detection output pin*1

Figure 4
*1.
*2.
*3.

Connect the heat sink of backside at shadowed area to the board, and set electric potential GND.
However, do not use it as the function of electrode.
The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.
Connect a capacitor between the CD pin and the VSS pin. The release delay time can be adjusted according to
the capacitance.
Moreover, the CD pin is available even when it is open.

5

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19114xxxA Series
Rev.1.2_00
 Absolute Maximum Ratings
Table 5
(Ta = −40°C to +125°C unless otherwise specified)
Item
SymbolAbsolute Maximum Rating
Unit
VSS − 0.3 to VSS + 45.0
Power supply voltage
VDD
V
VSS − 30.0 to VSS + 45.0
SENSE pin voltage
VSENSEV
VSS − 0.3 to VDD + 0.3 ≤ VSS + 7.0
CD pin input voltage
VCD
V
VSS − 0.3 to VSS + 45.0
Output voltage
VOUT
V
Output current
IOUT
25
mA
−40 to +150
Junction temperature
Tj°C−40 to +125
Operation ambient temperature
Topr°C−40 to +150
Storage temperature
Tstg°C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physicaldamage. These values must therefore not be exceeded under any conditions.

 Thermal Resistance Value
Table 6
Item

SymbolCondition

Board A
Board B
Board C
SOT-23-5
Board D
Board E
θJA
Junction-to-ambient thermal resistance*1
Board A
Board B
HSNT-6(2025) Board C
Board D
Board E
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Remark6

Refer to " Power Dissipation" and "Test Board" for details.

Min.
−
−
−
−
−
−
−
−
−
−

Typ.
192
160
−
−
−
180
128
43
44
36

Max.
−
−
−
−
−
−
−
−
−
−

Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00
S-19114xxxA Series Electrical Characteristics
Table 7
(Ta = −40°C to +125°C unless otherwise specified)
Item

SymbolCondition

Min.

Typ.

Max.

Unit

Test
CircuitVDD = 13.5 V,
VDET(S)
VDET(S)
VDET(S)V
1
4.0 V ≤ VDET(S) ≤ 12.0 V
× 0.985
× 1.015
L / P type
VDET
−
−
V
1
× 0.00(VHYS = 0%)
M / Q type
VDET
VDET
VDET
V
1
×
0.01
×
0.02
×
0.03
(V
=
2.0%)
HYS
Hysteresis width*2
VHYS
N / S type
VDET
VDET
VDET
V
1
× 0.04
× 0.05× 0.06(VHYS = 5.0%)
R / T type
VDET
VDET
VDET
V
1
× 0.09× 0.10× 0.11(VHYS = 10.0%)
VDD = 13.5 V,−
μA
Current consumption
ISS1
2.0
3.5
2
VSENSE = VREL(S)*3 + 1 V−−−
Operation voltage
VDD
3.0
36.0
V
OUT pin Nch driver,
−
−
0.60
mA
3
Output current
IOUT
VDD = 3.0 V, VDS*4 = 0.1 V,
VSENSE = VDET(S) − 1 V
OUT pin Nch driver,−−μA
Leakage current
ILEAK
VDD = 36 V, VOUT = 36 V,
2.0
3
VSENSE = VREL(S)*3 + 1 V−−
μs
L / M / N / R type10.0
4
Detection response time*5
tRESET−−μs
P / Q / S / T type25.0
4
Release delay time*6tDELAYCD = 3.3 nF
8.0
10.0
12.0
ms
4
−
MΩ
SENSE pin resistance
RSENSE
12.3
32.2
75.0
2
−
kΩ
−
CD pin discharge ON resistance RCDD
VDD = 3.0 V, VCD = 0.5 V
0.15
1.00
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value*2. The Release voltage (VREL) is as follows.
L / P type (hysteresis width "Unavailable"):VREL = VDET
M / N / R / Q / S / T type (hysteresis width "Available"):VREL = VDET + VHYS
*3. VREL(S) ): Set release voltage value*4. VDS: Drain-to-source voltage of the output transistor*5. The time period from when the pulse voltage of VDET(S) + 1.0 V → VDET(S) − 1.0 V is applied to the SENSE pin after
VSENSE reaches the release voltage once, until VOUT reaches 50% of VDD.
*6. The time period from when the pulse voltage of VREL(S) − 1.0 V → VREL(S) + 1.0 V is applied to the SENSE pin to when
VOUT reaches 50% of VDD.
Detection voltage*1

VDET

7

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19114xxxA Series
Rev.1.2_00
 Test Circuits
ROUT
100 kΩ

VDD
VDD
SENSE
VSENSE+OUT+VSENSE

CD

SENSE
CD

A

OUT
VSS
V

OUT
VSS

ROUT
100 kΩVDD

Figure 7 Test Circuit 3

8

A

Figure 6 Test Circuit 2

VDD

SENSE

+

VSENSEV

Figure 5 Test Circuit 1

VDD

VDD

A

VDD

VSS

CD

V

+

+

+ VOUTVDD
VSENSE

SENSE
CD

OUT
VSS

Figure 8 Test Circuit 4

OscilloscopeAUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00
S-19114xxxA Series
 Standard Circuit
VDD
VDD

ROUT*2SENSE
CDVSENSE

OUT
VSS

CD*1

CD is a release delay time adjustment capacitor. The CD should be connected directly to the CD pin and the VSS
pin.
ROUT is the external pull-up resistors for the output pin.

*1.
*2.

Figure 9
Caution

The above connection diagram and constants will not guarantee successful operation. Perform thoroughevaluation including the temperature characteristics with an actual application to set the constants.

 Selection of Release Delay Time Adjustment Capacitor (CD)In this IC, the release delay time adjustment capacitor (CD) is necessary between the CD pin and the VSS pin to adjust
the release delay time (tDELAY) of the detector. Refer to "3. Delay circuit" in " Operation" for details.
Caution

Perform thorough evaluation including the temperature characteristics with an actual application to
select CD.

9

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19114xxxA Series
Rev.1.2_00
 Explanation of Terms
1. Detection voltage (VDET)The detection voltage is a SENSE pin voltage at which the output voltage in Figure 12 turns to "L". The detection
voltage varies slightly among products of the same specification. The variation of detection voltage between thespecified minimum and the maximum is called the detection voltage range (Refer to "Figure 10 Detection Voltage").
Example: In VDET = 10.0 V product, the detection voltage is at any point in the range of 9.85 V ≤ VDET ≤ 10.15 V.
This means that some VDET = 10.0 V product has VDET = 9.85 V and some has VDET = 10.15 V.

2. Release voltage (VREL)
The release voltage is a SENSE pin voltage at which the output voltage in Figure 12 turns to "H". The release voltage
varies slightly among products of the same specification. The variation of release voltage between the specified
minimum and the maximum is called the release voltage range (Refer to "Figure 11 Release Voltage").
The release voltage becomes the value differs from the detection voltage within the range shown below.
• M / Q type: 1% to 3% (2% typ.)• N / S type: 4% to 6% (5% typ.)• R / T type: 9% to 11% (10% typ.)Example: For R type, VDET = 10.0 V product, the release voltage is at any point in the range of 10.736 V ≤ VREL ≤11.267 V despite VREL = 11.0 V typ.
This means that some R type, VDET = 10.0 V product has VREL = 10.736 V and some has VREL = 11.267 V.
Detection voltage

VSENSEVDET max.

Release voltage
VREL max.

Detection voltage
range

VDET min.

Release voltage
range

VREL min.
VSENSEtRESET
VOUT

tDELAY

VOUT

Figure 10 Detection Voltage

Figure 11 Release Voltage

ROUT
100 kΩ

VDD
SENSE
+

VDD
V
VSENSE

CD

OUT
VSS

+
V

Figure 12 Test Circuit of Detection Voltage and Release Voltage

10

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00
S-19114xxxA Series
3. Hysteresis width (VHYS)
The hysteresis width is the voltage difference between the detection voltage (VDET) and the release voltage (VREL).
Voltage difference between VREL and VDET is the hysteresis width (VHYS*1) of the OUT pin. Setting the hysteresis width
between VDET and VREL, prevents malfunction caused by noise on the input voltage.
*1.

Refer to "1. 2

S-19114 Series M / N / R / Q / S / T type" in "■ Operation" for details.

4. Feed-through current
The feed-through current is a current that flows instantaneously to the VDD pin at the time of detection and release of
a voltage detector.

11

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19114xxxA Series
Rev.1.2_00
 Operation
1.

Basic operation
Figure 13 and Figure 15 show that the OUT pin being pulled up by resistors (ROUT) is an example of basic operation.
1. 1 S-19114 Series L / P type(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage(VSENSE) is the release voltage (VREL) or higher, the Nch transistor is turned off to output VDD ("H") when the output
is pulled up.
(RB + RC ) • VSENSEAt this time, the input voltage to the comparator is.
RA + RB + RC
(2) When VSENSE decreases to the detection voltage (VDET) or lower (point A in Figure 14), the Nch transistor isturned on. And then VSS ("L") is output from the OUT pin after the elapse of the detection response time (tRESET).
(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin isstable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE increases, VSS is output when VSENSE is lower than VREL.
(5) When VSENSE increases to VREL or higher (point B in Figure 14), the Nch transistor is turned off. And then VDD is
output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.

SENSE

ROUT

VDD

VSENSE

RA

+
−

VDD
VREF

OUT

Delay
circuit

*1

RB
+

*1

VSS

*1

RC

CD
CD

*1. Parasitic diodeFigure 13 Operation of S-19114 Series L / P type12

V

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00
S-19114xxxA Series(1)

Detection voltage (VDET)(2)
A(3) (4)(5)

B

Release voltage (VREL)VSENSE
Minimum operation voltage
VSS
VDD
Output from OUT pin

VSStRESETtDELAY

Remark The release voltage is set to the same value as the detection voltage, since there is no hysteresis width.
Figure 14 Timing Chart of S-19114 Series L / P Type

13

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19114xxxA Series
Rev.1.2_00
1. 2

S-19114 Series M / N / R / Q / S / T type(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage(VSENSE) is the release voltage (VREL) or higher, the Nch transistor is turned off to output VDD ("H") when the output
is pulled up.
(RB + RC ) • VSENSE
Since the Nch transistor (N1) is turned off, the input voltage to the comparator is.
RA + RB + RC
(2) Even if VSENSE decreases to VREL or lower, VDD is output when VSENSE is higher than the detection voltage (VDET).
When VSENSE decreases to VDET or lower (point A in Figure 16), the Nch transistor is turned on. And then VSS ("L")
is output from the OUT pin after the elapse of the detection response time (tRESET).
RB • VSENSE.
At this time, N1 is turned on, and the input voltage to the comparator is
RA + RB(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin isstable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE exceeds VDET, VSS is output when VSENSE is lower than VREL.
(5) When VSENSE increases to VREL or higher (point B in Figure 16), the Nch transistor is turned off. And then VDD is
output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.

SENSE

ROUT

VDD

VSENSE

RA

+
−

VDD
VREF

OUT

Delay
circuit

*1

RB
N1

+

*1

VSS

*1

RC

CD
CD

*1. Parasitic diodeFigure 15 Operation of S-19114 Series M / N / R / Q / S / T type14

V

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00
S-19114xxxA Series

(1)

(2)

(3)

(4)

(5)

B

Hysteresis width
A(VHYS)

Release voltage (VREL)
Detection voltage (VDET)VSENSE

Minimum operation voltage
VSS
VDD
Output from OUT pin

VSStRESETtDELAY

Figure 16 Timing Chart of S-19114 Series M / N / R / Q / S / T Type

2.

SENSE pin
The SENSE pin is the input pin for the detection voltage. The power supply VDD pin and SENSE pin, for voltage
detection, are divided. Therefore, as long as a voltage is supplied to the VDD pin, the reset signal will be held even if
the input voltage to the SENSE pin drops below the minimum operation voltage. Also, the SENSE pin of this IC has abuilt-in reverse connection protection circuit. Even when the SENSE pin voltage is less than the VSS pin voltage, thecurrent flowing from the VSS pin to the SENSE pin is reduced to 0.05 mA typ.
2. 1

Error when detection voltage is set externally

The detection voltage can be set externally by connecting a node that was resistance-divided by the resistor (RA)and the resistor (RB) to the SENSE pin as shown in Figure 17.
For conventional products without the SENSE pin, external resistor cannot be too large since the resistance-divided
node must be connected to the VDD pin. This is because a feed-through current will flow through the VDD pin whenit goes from detection to release, and if external resistor is large, problems such as oscillation or larger error in thehysteresis width may occur.
In this IC, RA and RB in Figure 17 are easily made larger since the resistance-divided node can be connected to the
SENSE pin through which no feed-through current flows. However, be careful of error in the current flowing throughthe internal resistance (RSENSE) that will occur.
Although RSENSE*1 in this IC is large to make the error small, RA and RB should be selected such that the error iswithin the allowable limits.
*1.

12.3 MΩ min.

15

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19114xxxA Series
Rev.1.2_00
2. 2

Selection of RA and RB

In Figure 17, the relation between the external setting detection voltage (VDX) and the actual detection voltage(VDET) is ideally calculated by the equation below.
RA
VDX = VDET × (1 + R ) ·········································(1)B

However, in reality there is an error in the current flowing through RSENSE.
When considering this error, the relation between VDX and VDET is calculated as follows.
RA
VDX = VDET × (1 + R || R
)
B
SENSE
RA

= VDET × 1 +
 RB × RSENSE  RB + RSENSE RARA× VDET ················(2)= VDET × (1 + R ) + R
B
SENSE
By using equations (1) and (2), the error is calculated as VDET × R

RA

SENSE

.

The error rate is calculated as follows by dividing the error by the right-hand side of equation (1).
RA × RB
RA || RB
× 100 [%] = R
× 100 [%] ····(3)SENSE
RSENSE × (RA + RB)
As seen in equation (3), the smaller the resistance values of RA and RB compared to RSENSE, the smaller the error
rate becomes.
Also, the relation between the external setting hysteresis width (VHX) and the hysteresis width (VHYS) is calculated
by equation below. Error due to RSENSE also occurs to the relation in a similar way to the detection voltage.
RA
VHX = VHYS × (1 + R ) ··········································(4)
B

A

VDX

RA
VDET

VDD
SENSE

OUT

RSENSERB

VSS

Figure 17 Detection Voltage External Setting Circuit
Caution16

If RA and RB are large, the SENSE pin input impedance becomes higher and may cause a
malfunction due to noise. In this case, connect a capacitor between the SENSE pin and the
VSS pin.

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00
S-19114xxxA Series
3.

Delay circuit
The delay circuit has a function that adjusts the release delay time (tDELAY) from when the SENSE pin voltage (VSENSE)
reaches the release voltage (VREL = VDET + VHYS) or higher to when the output from OUT pin inverts.
tDELAY is determined by the delay coefficient, the release delay time adjustment capacitor (CD) and the release delay
time when the CD pin is open (tDELAY0). They are calculated by the equations below.
tDELAY [ms] = Delay coefficient × CD [nF] + tDELAY0 [ms]Table 8Operation Temperature
Ta = −40°C to +125°C

Min.
2.76

Delay Coefficient
Typ.
3.00

Max.
3.28

Table 9Operation Temperature
Ta = −40°C to +125°C
Caution 1.

2.

3.

Release Delay Time when CD Pin is Open(tDELAY0)
Min.
Typ.
Max.
0.01
0.04
0.20

Mounted board layout should be made in such a way that no current flows into or flows fromthe CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot beprovided.
There is no limit for the capacitance of CD as long as the leakage current of the capacitor canbe ignored against the built-in constant current value (approximately 350 nA). The leakage
current may cause error in delay time. When the leakage current is larger than the built-in
constant current, no detect or release takes place.
The above equations will not guarantee successful operation. Determine the capacitance of CD
through thorough evaluation including temperature characteristics in the actual usage
conditions.

17

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19114xxxA Series
Rev.1.2_00
 Usage Precautions
1.

Feed-through current at the time of detection and release
In this IC, a feed-through current flows instantaneously at the time of detection and release. Therefore, if the input
impedance is increased, oscillation may occur due to the voltage drop caused by the feed-through current.
When this IC is used in the configuration shown in Figure 18, the input impedance is recommended to be 1.0 kΩ or
less.
Perform a sufficient evaluation including the temperature characteristics under the actual operating conditions.

VDD
OUT

SENSE
CD

VBAT

VSS

Figure 18

2.

Power down (Reference)
As shown in Figure 19, when the VDD pin voltage (VDD) falls sharply in the state of VSENSE < VREL, the OUT pin may
be released. So be careful.
Figure 20 shows the relationship between the dVREL*1 that can hold the detected state and the falling slew rate (SR) of
VDD.
Please perform a sufficient evaluation with the actual machine when using it.
*1.

dVREL: Difference between VREL(S) and VSENSE
VDD = 3.0 V ↔ 36.0 V, VSENSE = VREL(S) − dVREL
0.24

tSR

VP−P
SR = VP−P / tSR

0.16
0.12
0.08
0.04

VREL(S)

0.00
dVREL

VSENSE

Figure 19

18

dVREL [V]

VDD

VOUT = “L”

0.20

0.01

0.1
SR [V / µs]
Figure 20

1

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00
S-19114xxxA Series
 Precautions• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• Because the SENSE pin has a high impedance, malfunctions may occur due to noise.
Be careful of wiring adjoining SENSE pin wiring in actual applications.
• When designing for mass production using an application circuit described herein, the product deviation andtemperature characteristics should be taken into consideration. ABLIC Inc. shall not bear any responsibility for patent
infringements related to products using the circuits described herein.
• ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.

19

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19114xxxA Series
Rev.1.2_00
 Characteristics (Typical Data)1.

Detection voltage (VDET), Release voltage (VREL) vs. Temperature (Ta)VDET(S) = 4.0 V, VHYS = 2.0%, VDD = 13.5 V

VDET(S) = 8.0 V, VHYS = 5.0%, VDD = 13.5 V

8.8
VDET, VREL [V]

VDET, VREL [V]

4.4
VREL

4.2
4.0

VDET

3.8
3.6
-40 -2502550Ta [°C]

75

100

VREL

8.6
8.4
8.2
8.0
7.8

VDET

7.6
-40 -25

125

0

25
50
Ta [°C]

75

100

125

VDET, VREL [V]

VDET(S) = 12.0 V, VHYS = 10.0%, VDD = 13.5 V
13.6

13.2
12.8

VREL

12.4

VDET

12.0
11.6
-40 -25

75

100

125

Detection voltage (VDET), Release voltage (VREL) vs. Power supply voltage (VDD)
VDET(S) = 4.0 V, VHYS = 2.0%

VDET, VREL [V]

4.06
4.04

VREL Ta = +25°C
Ta = +125°C
Ta = -40°C
Ta = +25°C
Ta = -40°C Ta = +125°C

4.02
4.00
3.98
3.96
3.94

VDET
0

6

VDET, VREL [V]

13.0

VREL

12.6
12.2
11.8

12

18
24
VDD [V]

30

36

VDET(S) = 12.0 V, VHYS = 10.0%

13.4

20

25
50
Ta [°C]

VDET
0Ta = -40°C
Ta = +25°C
Ta = +125°C
Ta = +25°C
Ta = +125°C
Ta = -40°C

6

12

18
24
VDD [V]

30

36

VDET(S) = 8.0 V, VHYS = 5.0%

8.45

VDET, VREL [V]

2.

0

8.35
8.25

VREL
Ta = -40°C
Ta = +25°C
Ta = +125°C

8.15

Ta = +125°C
Ta = +25°C
Ta = -40°C

VDET

8.05
7.95

0

6

12

18
24
VDD [V]

30

36

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00
S-19114xxxA Series
3.

Hysteresis width (VHYS) vs. Temperature (Ta)VDET(S) = 8.0 V, VHYS = 5.0%, VDD = 13.5 V

7.0

3.0

6.0

VHYS [%]

VHYS [%]VDET(S) = 4.0 V, VHYS = 2.0%, VDD = 13.5 V

4.0

2.0
1.0

5.0
4.0

0
-40 -2502550Ta [°C]

75

100

3.0
-40 -25

125

0

25
50
Ta [°C]

75

100

125

VHYS [%]VDET(S) = 12.0 V, VHYS = 10.0%, VDD = 13.5 V
12.0

11.0
10.0
9.0
8.0
-40 -252550
Ta [°C]

75

100

125

Hysteresis width (VHYS) vs. Power supply voltage (VDD)
VDET(S) = 4.0 V, VHYS = 2.0%

VDET(S) = 8.0 V, VHYS = 5.0%,

7.0

3.0

Ta = -40°C

Ta = +25°C

VHYS [%]

VHYS [%]

4.0

2.0
Ta = +125°C

1.0
0

0

6

12

6.0

Ta = -40°C

5.0
4.0

18
24
VDD [V]30

36

Ta = +25°C

3.0

Ta = +125°C
0

6

12

18
24
VDD [V]

30

36

VDET(S) =12.0 V, VHYS = 10.0%

12.0
VHYS [%]

4.

0

11.0

Ta = -40°C

Ta = +25°C

10.0
9.0
8.0

Ta = +125°C
0

6

12

18
24
VDD [V]

30

36

21

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19114xxxA Series
Rev.1.2_00
Current consumption (ISS1) vs. Temperature (Ta)VDET(S) = 4.0 V, VHYS = 2.0%, VDD = 13.5 V,
VSENSE = VREL(S) + 1.0 V (during release)
3.0

VDET(S) = 8.0 V, VHYS = 5.0%, VDD = 13.5 V,
VSENSE = VREL(S) + 1.0 V (during release)
3.0

2.5

2.5

2.0

2.0

ISS1 [µA]

ISS1 [µA]

5.

1.5
1.0

1.5
1.0

0.5

0.5

0.0

0.0

-40 -2502550Ta [°C]

75

100

125

-40 -2502550Ta [°C]

75

100

125

VDET(S) = 12.0 V, VHYS = 10.0%, VDD = 13.5 V,
VSENSE = VREL(S) + 1.0 V (during release)
3.0

ISS1 [µA]

2.5
2.0
1.5
1.0
0.5
0.0
-40 -25

6.

0

25
50
Ta [°C]

75

100

125

Current consumption (ISS1) vs. Power supply voltage (VDD)
VDET(S) = 4.0 V, VHYS = 2.0%, VDD = 0 V → 36.0 V,
VSENSE = VREL(S) + 1.0 V (during release)
3.0

Ta = +25°C

2.5

Ta = +125°C

2.0

ISS1 [µA]

ISS1 [µA]

2.5
1.5
1.0

Ta = -40°C

0.5
0.0

0

ISS1 [µA]

2.5

6

12

18
24
VDD [V]30

36

Ta = +25°C

Ta = +125°C

2.0
1.5
1.0

Ta = -40°C

0.5

22

Ta = +25°C

Ta = +125°C

2.0
1.5
1.0

Ta = -40°C

0.5

VDET(S) = 12.0 V, VHYS = 10.0%, VDD = 0 V → 36.0 V,
VSENSE = VREL(S) + 1.0 V (during release)
3.0

0.0

VDET(S) = 8.0 V, VHYS = 5.0%, VDD = 0 V → 36.0 V,
VSENSE = VREL(S) + 1.0 V (during release)
3.0

0

6

12

18
24
VDD [V]

30

36

0.0

0

6

12

18
24
VDD [V]

30

36

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00
S-19114xxxA Series
Current consumption (ISS2) vs. Temperature (Ta)VDET(S) = 4.0 V, VHYS = 2.0%, VDD = 13.5 V,
VSENSE = VDET(S) − 1.0 V (during detection)
3.0

VDET(S) = 8.0 V, VHYS = 5.0%, VDD = 13.5 V,
VSENSE = VDET(S) − 1.0 V (during detection)
3.0

2.5

2.5

2.0

2.0

ISS2 [µA]

ISS2 [µA]

7.

1.5
1.0

1.5
1.0

0.5

0.5

0.0

0.0

-40 -2502550Ta [°C]

75

100

125

-40 -2502550Ta [°C]

75

100

125

VDET(S) = 12.0 V, VHYS = 10.0%, VDD = 13.5 V,
VSENSE = VDET(S) − 1.0 V (during detection)
3.0

ISS2 [µA]

2.5
2.0
1.5
1.0
0.5
0.0
-40 -252550
Ta [°C]

75

100

125

Current consumption (ISS2) vs. Power supply voltage (VDD)
VDET(S) = 4.0 V, VHYS = 2.0%, VDD = 0 V → 36.0 V,
VSENSE = VDET(S) − 1.0 V (during detection)
3.0

Ta = +25°C

2.5

Ta = +125°C

2.0
1.5
1.0

Ta = -40°C

0.5
0.0

VDET(S) = 8.0 V, VHYS = 5.0%, VDD = 0 V → 36.0 V,
VSENSE = VDET(S) − 1.0 V (during detection)
3.0

ISS2 [µA]

ISS2 [µA]

2.5

0

6

12

18
24
VDD [V]Ta = +25°C

2.0
1.5
1.0

Ta = -40°C

0.5
30

36

Ta = +125°C

0.0

0

6

12

18
24
VDD [V]

30

36

VDET(S) = 12.0 V, VHYS = 10.0%, VDD = 0 V → 36.0 V,
VSENSE = VDET(S) − 1.0 V (during detection)
3.0

2.5

ISS2 [µA]8.

0Ta = +25°C

Ta = +125°C

2.0
1.5
1.0

Ta = -40°C

0.5
0.0

0

6

12

18
24
VDD [V]

30

36

23

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19114xxxA Series
Rev.1.2_00
Nch transistor output current (IOUT) vs. VDS
VSENSE = 0 V, Ta = −40°C

10

VDD = 36.0 V

IOUT [mA]88

VDD = 13.5 V

642

VDD = 36.0 V

6VDD = 13.5 V

42

VDD = 3.0 V

0

VDD = 3.0 V

0
0.0

0.1

0.2

0.3
0.4
VDS [V]

0.5

0.6

0.0

0.1

0.2

0.3
0.4
VDS [V]

0.5

0.6

VSENSE = 0 V, Ta = +125°C

10
8

IOUT [mA]

VSENSE = 0 V, Ta = +25°C

10

IOUT [mA]9.

VDD = 36.0 V

6VDD = 13.5 V

4

VDD = 3.0 V

2
0
0.0

0.1

0.2

0.3
0.4
VDS [V]

0.5

0.6

Remark VDS: Drain-to-source voltage of the output transistor

10. Nch transistor output current (IOUT) vs. Power supply voltage (VDD)
VDS = 0.1 V, VSENSE = VDET(S) − 1.0 V

IOUT [mA]1.6
1.2

Ta = -40°C

Ta = +25°C

0.8
0.4

Ta = +125°C

0.0
0

6

12

18
24
VDD [V]

30

36

Remark VDS: Drain-to-source voltage of the output transistor

11. Output voltage (VOUT) vs. SENSE pin voltage (VSENSE)
VDET(S) = 4.0 V, VHYS = 2.0%, VDD = 3.0 V,
VSENSE = 6.0 V → 0.0 V,
pull-up to VDD, pull-up resistance: 100 kΩ

VDET(S) = 4.0 V, VHYS = 2.0%, VDD = 3.0 V,
VSENSE = 6.0 V → 0.0 V,
pull-up to 16.0 V, pull-up resistance: 100 kΩ
20

Ta = -40°C

3

VOUT [V]

VOUT [V]4

Ta = +25°C

2

Ta = +125°C
10

Ta = +25°C

10

Ta = +125°C
5

0

1

2

3
VSENSE [V]24

Ta = -40°C

15

4

5

6

0

0

1

2

3
4
VSENSE [V]56

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00
S-19114xxxA Series
12. Dynamic response vs. Output pin capacitance (COUT) (CD pin; open)

tPLH

1000
100

tPHL
10
1
0.01

0.1

1

10

VDET(S) = 8.0 V, VHYS = 5.0%,
VDD = 13.5 V, Ta = +25°C

10000

Response time [µs]Response time [µs]10000

VDET(S) = 8.0 V, VHYS = 5.0%,
VDD = 13.5 V, Ta = −40°C

tPLH

1000
100

tPHL
10
1
0.01

100

0.1

COUT [nF]

Response time [µs]

10000

1
COUT [nF]10100

VDET(S) = 8.0 V, VHYS = 5.0%,
VDD = 13.5 V, Ta = +125°C

tPLH

1000
100

tPHL
10
1
0.01

0.1

1
COUT [nF]

10

100

1 µs

1 µs

VIH*1
VSENSE
VIL*2

tPLH

tPHL

VDD1
VOUT

VDD1 × 50%

VDD1 × 50%

VSS
*1.
*2.

tPHL : VIH = VDET(S) + 1.0 V, tPLH : VIH = VREL(S) + 1.0 V
tPHL : VIL = VDET(S) − 1.0 V, tPLH : VIL = VREL(S) − 1.0 V
Figure 21 Test Condition of Response TimeVSENSE
VDD

ROUT
100 kΩ

VDD
SENSE
CD

OUT
VDD1

VSS
COUT

V

Figure 22 Test Circuit of Response Time
Caution

The above connection diagram and constants will not guarantee successful operation. Perform
thorough evaluation including the temperature characteristics with an actual application to set theconstants.

25

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19114xxxA Series
Rev.1.2_00
 Reference Data1.

Detection response time (tRESET) vs.
Temperature (Ta)2.

Detection response time (tRESET) vs.
Power supply voltage (VDD)
VDET(S) = 8.0 V, VHYS = 5.0%

8

6

6

tRESET [µs]tRESET [µs]VDET(S) = 8.0 V, VHYS = 5.0%, VDD = 13.5 V

8

4
2
0
-40 -2502550Ta [°C]

75

100

4
2
0

125

Ta = +125°C
Ta = +25°C

Ta = -40°C
0

6

12

18
24
VDD [V]

30

36

1 µs
VIH*1
VSENSE
VIL*2

ROUT
100 kΩVDD

tRESET

SENSE

VDD

VDD

CD

VOUT

VDD × 50%

OUT
VSS
V

VSENSEVSS
VIH = VDET(S) + 1.0 V
VIL = VDET(S) − 1.0 V

*1.
*2.

Figure 23 Test Condition of Detection Response Time
Caution3.

Figure 24 Test Circuit of Detection Response TimeThe above connection diagram and constants will not guarantee successful operation. Perform
thorough evaluation including the temperature characteristics with an actual application to set theconstants.

Detection response time (tRESET) vs. Overdrive voltage (VOverdrive)
VDET(S) = 8.0 V, VHYS = 5.0%, VDD = 13.5 V,
VSENSE = VDET(S) + 1.0 V → VDET(S) − VOverdrive60
Ta = -40°C
50
Ta = +25°C
40

30

Ta = +125°C

20

VSENSE
VDET(S)

100

VOvredrive

0.1

1

10

VOverdrive [V]Figure 25

26

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00
S-19114xxxA Series
4.

Release delay time (tDELAY) vs.
Temperature (Ta)5.

Release delay time (tDELAY) vs.
Power supply voltage (VDD)

VDET(S) = 8.0 V, VHYS = 5.0%,
VDD = 13.5 V, CD = 3.3 nF

VDET(S) = 8.0 V, VHYS = 5.0%,
CD = 3.3 nF

12

12

11

11

tDELAY [ms]tDELAY [ms]Ta = +125°C

1098-40 -25

6.

0

25
50
Ta [°C]

75

100

10
9
8

125

Ta = +25°C

Ta = -40°C
0

6

12

18
24
VDD [V]30

36

Release delay time (tDELAY) vs. CD pin capacitance (CD) (Without output pin capacitance)
10000

VDET(S) = 8.0 V, VHYS = 5.0%, VDD = 13.5 V

Ta = +25°C

1000

tDELAY [ms]100Ta = -40°C

10
1
0.1

Ta = +125°C

0.01
0.01

0.1

1
10
CD [nF]

100

1 µs
VIH*1
VSENSE
VIL*2

ROUT
100 kΩVDD

tDELAY
VDD

VDD
VOUT

VDD × 50%

OUT

SENSE
CD

VSS
V

VSENSE

CD

VSS
*1.
*2.

VIH = VREL(S) + 1.0 V
VIL = VREL(S) − 1.0 V

Figure 26 Test Condition of Release Delay Time
CautionFigure 27 Test Circuit of Release Delay TimeThe above connection diagram and constants will not guarantee successful operation. Perform thoroughevaluation including the temperature characteristics with an actual application to set the constants.

27

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19114xxxA Series
Rev.1.2_00
Load dump characteristics (Ta = +25°C)
7. 1

VDET(S) = 7.3 V, VHYS = 5.0%

VDD = VSENSE = 13.5 V ↔ 45.0 V,
CD = 3.3 nF

100

VOUT [V]

80
60
40
20

60
40

VDD

20
0

VOUT

0
−0.2

−20
−40
0.0

0.2

0.4

0.6

VDD [V]

7.

R
100 kΩ

VDD
SENSE

VDD
V

OUT

CD VSS

+

V

CD

+

0.8

t [s]
Figure 28
Caution28

The above connection diagram and constants will not guarantee successful operation. Perform thoroughevaluation including the temperature characteristics with an actual application to set the constants.

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR WITH FAST DETECTION RESPONSE, SENSE PIN REVERSE CONNECTION PROTECTION, DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.2_00
S-19114xxxA Series Power Dissipation
SOT-23-5

HSNT-6(2025)
Tj = +150°C max.

4
3
2
1 B

Tj = +150°C max.

5
Power dissipation (PD) [W]Power dissipation (PD) [W]

5

4

E
C

3

D
2
B

1

A

A
0

0

25

50

75

100

125

150

175

0

0

25

Ambient temperature (Ta) [°C]
Board
A
B
C
D
E

Power Dissipation (PD)
0.65 W
0.78 W
−
−
−

50

75

100

125

150

175

Ambient temperature (Ta) [°C]
Board
A
B
C
D
E

Power Dissipation (PD)0.69 W
0.98 W
2.91 W
2.84 W
3.47 W

29

SOT-23-3/3S/5/6 Test Board
IC Mount Area

(1) Board A
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]

1
2
3
4

Thermal via

Specification
114.3 x 76.2 x t1.6
FR-4
2Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070-(2) Board B
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]Thermal via

1
2
3
4

Specification
114.3 x 76.2 x t1.6
FR-4
4Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070-

No. SOT23x-A-Board-SD-2.0

ABLIC Inc.

HSNT-6(2025) Test Board
IC Mount Area

(1) Board A
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]

1
2
3
4

Thermal via

Specification
114.3 x 76.2 x t1.6
FR-4
2Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070-(2) Board B
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]

1
2
3
4

Thermal via

Specification
114.3 x 76.2 x t1.6
FR-4
4Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070-(3) Board C
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]Thermal via

1
2
3
4

Specification
114.3 x 76.2 x t1.6
FR-4
4Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
Number: 4
Diameter: 0.3 mm

No. HSNT6-B-Board-SD-1.0
enlarged view

ABLIC Inc.

HSNT-6(2025) Test Board
IC Mount Area

(4) Board D
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]

1
2
3
4

Thermal via

Specification
114.3 x 76.2 x t1.6
FR-4
42
Pattern for heat radiation: 2000mm t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070-

enlarged view

(5) Board E
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]Thermal via

1
2
3
4

Specification
114.3 x 76.2 x t1.6
FR-4
42
Pattern for heat radiation: 2000mm t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070

Number: 4
Diameter: 0.3 mm

enlarged viewNo. HSNT6-B-Board-SD-1.0

ABLIC Inc.

2.9±0.2
1.9±0.2
4

5

1

2

+0.1

0.16 -0.06

30.95±0.1
0.4±0.1

No. MP005-A-P-SD-1.3

TITLE

SOT235-A-PKG Dimensions

No.

MP005-A-P-SD-1.3

ANGLE
UNIT

mm

ABLIC Inc.

4.0±0.1(10 pitches:40.0±0.2)+0.1

ø1.5 -0+0.2

ø1.0 -0

2.0±0.05

0.25±0.1

4.0±0.1

1.4±0.2

3.2±0.2

3 2 1

4

5

Feed direction

No. MP005-A-C-SD-2.1

TITLE

SOT235-A-Carrier Tape

No.

MP005-A-C-SD-2.1

ANGLE
UNIT

mm

ABLIC Inc.

+1.0

9.0 - 0.0
11.4±1.0

Enlarged drawing in the central part

ø13±0.2

(60°)

(60°)

No. MP005-A-R-SD-2.0

TITLE

SOT235-A-Reel

No.

MP005-A-R-SD-2.0

ANGLE

QTY.

UNIT

mm

ABLIC Inc.

3,000

1.96±0.05
1.78±0.1
6

5

4

2

3

0.5

0.5

0.5
1

0.12±0.04

0.48±0.02

0.22±0.05
The heat sink of back side has different electric
potential depending on the product.
Confirm specifications of each product.
Do not use it as the function of electrode.

No. PJ006-B-P-SD-1.0

TITLE

HSNT-6-C-PKG Dimensions

No.

PJ006-B-P-SD-1.0

ANGLE
UNIT

mm

ABLIC Inc.

+0.1

2.0±0.05

ø1.5 -0

4.0±0.1

ø0.5±0.1

0.25±0.05

0.65±0.05

4.0±0.1

2.25±0.05

3 21

0.5
0.5

0.5

0.5

0.5

0.5

4 5 6

Feed direction

No. PJ006-B-C-SD-1.0

TITLE

HSNT-6-C-Carrier Tape

No.

PJ006-B-C-SD-1.0

ANGLE
UNIT

mm

ABLIC Inc.

+1.0

9.0 - 0.0
11.4±1.0

Enlarged drawing in the central part

ø13±0.2

(60°)

(60°)

No. PJ006-B-R-SD-1.0

TITLE

HSNT-6-C-Reel

No.

PJ006-B-R-SD-1.0
QTY.

ANGLE
UNIT

mm

ABLIC Inc.

5,000

Land Recommendation
0.50

0.35

0.50

1.44
1.78
2.10

Caution It is recommended to solder the heat sink to a board in order to ensure the heat radiation.
PKG

Stencil Opening

1.40
0.50

0.50

No. PJ006-B-LM-SD-1.0

0.35

CautionMask aperture ratio of the lead mounting part is 100~120%.
Mask aperture ratio of the heat sink mounting part is 30%.
Mask thickness: t0.12 mm
Reflow atmosphere: Nitrogen atmosphere is recommended.
(Oxygen concentration: 1000ppm or less)100~120%30%
t0.12 mm

TITLE

HSNT-6-C-Land &Stencil Opening

No.

PJ006-B-LM-SD-1.0

ANGLE
UNIT

mm

1000ppm

ABLIC Inc.

Disclaimers (Handling Precautions)1.

All the information described herein (product data, specifications, figures, tables, programs, algorithms andapplication circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.

2.

The circuit examples and the usages described herein are for reference only, and do not guarantee the success ofany specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any otherright due to the use of the information described herein.

3.

ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information describedherein.

4.

Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due tothe use of the products outside their specified ranges.

5.

Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.

6.

When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-relatedlaws, and follow the required procedures.

7.

The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,biological or chemical weapons or missiles, or use any other military purposes.

8.

The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.

9.

In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products areallowed to apply for the system on customer's own responsibility.

10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of thisdocument described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07

www.ablic.com