TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

Data Manual

Literature Number: SPRS230J
October 2003 – Revised September 2007

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does notnecessarily include testing of all parameters.

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Contents
Revision History ........................................................................................................................... 91
F280x, F2801x, C280x DSPs ................................................................................................. 11
1.1
1.2

2

Introduction ....................................................................................................................... 13
2.1
2.2

3

3.3
3.4
3.5
3.6

3.7

Memory Maps ............................................................................................................... 28
Brief Descriptions........................................................................................................... 36
3.2.1
C28x CPU ....................................................................................................... 36
3.2.2
Memory Bus (Harvard Bus Architecture) .................................................................... 36
3.2.3
Peripheral Bus .................................................................................................. 36
3.2.4
Real-Time JTAG and Analysis ................................................................................ 36
3.2.5
Flash .............................................................................................................. 37
3.2.6
ROM ............................................................................................................... 37
3.2.7
M0, M1 SARAMs ............................................................................................... 37
3.2.8
L0, L1, H0 SARAMs ............................................................................................ 37
3.2.9
Boot ROM ........................................................................................................ 37
3.2.10 Security .......................................................................................................... 39
3.2.11 Peripheral Interrupt Expansion (PIE) Block .................................................................. 40
3.2.12 External Interrupts (XINT1, XINT2, XNMI) ................................................................... 40
3.2.13 Oscillator and PLL .............................................................................................. 40
3.2.14 Watchdog ........................................................................................................ 40
3.2.15 Peripheral Clocking ............................................................................................. 40
3.2.16 Low-Power Modes .............................................................................................. 40
3.2.17 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 41
3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 41
3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 41
3.2.20 Control Peripherals ............................................................................................. 41
3.2.21 Serial Port Peripherals ......................................................................................... 42
Register Map ................................................................................................................ 42
Device Emulation Registers............................................................................................... 44
Interrupts .................................................................................................................... 44
3.5.1
External Interrupts .............................................................................................. 47
System Control ............................................................................................................. 48
3.6.1
OSC and PLL Block ............................................................................................ 49
3.6.2
Watchdog Block ................................................................................................. 52
Low-Power Modes Block .................................................................................................. 53

Peripherals ........................................................................................................................ 54
4.1
4.2
4.3
4.4
4.5
4.6

4.7
4.8
2

Pin Assignments............................................................................................................ 15
Signal Descriptions ......................................................................................................... 21

Functional Overview ........................................................................................................... 27
3.1
3.2

4

Features ..................................................................................................................... 11
Getting Started.............................................................................................................. 12

32-Bit CPU-Timers 0/1/2 .................................................................................................. 54
Enhanced PWM Modules (ePWM1/2/3/4/5/6) .......................................................................... 56
Hi-Resolution PWM (HRPWM) ........................................................................................... 58
Enhanced CAP Modules (eCAP1/2/3/4) ................................................................................ 58
Enhanced QEP Modules (eQEP1/2)..................................................................................... 61
Enhanced Analog-to-Digital Converter (ADC) Module ................................................................ 63
4.6.1
ADC Connections if the ADC Is Not Used ................................................................... 66
4.6.2
ADC Registers ................................................................................................... 67
Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)..................................... 68
Serial Communications Interface (SCI) Modules (SCI-A, SCI-B) .................................................... 73

Contents

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

4.9
4.10
4.11

5

Device Support .................................................................................................................. 86
5.1
5.2

6

6.5
6.6

6.7
6.8
6.9

6.10

6.11
6.12
6.13

Absolute Maximum Ratings ............................................................................................... 91
Recommended Operating Conditions ................................................................................... 92
Electrical Characteristics ................................................................................................. 92
Current Consumption ..................................................................................................... 93
6.4.1
Reducing Current Consumption .............................................................................. 97
6.4.2
Current Consumption Graphs .................................................................................. 98
Emulator Connection Without Signal Buffering for the DSP .......................................................... 99
Timing Parameter Symbology........................................................................................... 100
6.6.1
General Notes on Timing Parameters....................................................................... 100
6.6.2
Test Load Circuit .............................................................................................. 101
6.6.3
Device Clock Table ........................................................................................... 101
Clock Requirements and Characteristics ............................................................................. 103
Power Sequencing........................................................................................................ 104
6.8.1
Power Management and Supervisory Circuit Solutions................................................... 104
General-Purpose Input/Output (GPIO) ................................................................................. 107
6.9.1
GPIO - Output Timing ......................................................................................... 107
6.9.2
GPIO - Input Timing ........................................................................................... 108
6.9.3
Sampling Window Width for Input Signals .................................................................. 109
6.9.4
Low-Power Mode Wakeup Timing ........................................................................... 110
Enhanced Control Peripherals .......................................................................................... 113
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ........................................................ 113
6.10.2 Trip-Zone Input Timing ........................................................................................ 113
6.10.3 External Interrupt Timing ...................................................................................... 115
6.10.4 I2C Electrical Specification and Timing ..................................................................... 116
6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing .................................................... 116
6.10.6 SPI Slave Mode Timing ....................................................................................... 120
6.10.7 On-Chip Analog-to-Digital Converter ........................................................................ 123
Detailed Descriptions .................................................................................................... 128
Flash Timing ............................................................................................................... 129
ROM Timing (C280x only) ............................................................................................... 130

Migrating From F280x Devices to C280x Devices.................................................................. 131
7.1

8

Device and Development Support Tool Nomenclature................................................................ 86
Documentation Support ................................................................................................... 88

Electrical Specifications ...................................................................................................... 91
6.1
6.2
6.3
6.4

7

Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D) ........................................... 76
Inter-Integrated Circuit (I2C) .............................................................................................. 80
GPIO MUX .................................................................................................................. 82

Migration Issues........................................................................................................... 131

Mechanical Data ............................................................................................................... 132

Contents3

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

List of Figures
2-1

TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View) ............................................................. 16

2-2

TMS320F2806 100-Pin PZ LQFP (Top View) ................................................................................. 17

2-3

TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP
(Top View) ......................................................................................................................... 18

2-4

TMS320F2801x 100-Pin PZ LQFP
(Top View) ......................................................................................................................... 19

2-5

TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801,
TMS320F28016, TMS320F28015, TMS320C2802, TMS320C2801
100-Ball GGM and ZGM MicroStar BGA™ (Bottom View) .................................................................. 20

3-1

Functional Block Diagram ........................................................................................................ 27

3-2

F2809 Memory Map .............................................................................................................. 28

3-3

F2808 Memory Map .............................................................................................................. 29

3-4

F2806 Memory Map .............................................................................................................. 30

3-5F2802, C2802 Memory Map ..................................................................................................... 31

3-6

F2801, F28015, F28016, C2801 Memory Map ............................................................................... 32

3-7

External and PIE Interrupt Sources ............................................................................................. 45

3-8

Multiplexing of Interrupts Using the PIE Block ................................................................................ 46

3-9

Clock and Reset Domains ....................................................................................................... 48

3-10

OSC and PLL Block Diagram ................................................................................................... 49

3-11

Using a 3.3-V External Oscillator ............................................................................................... 50

3-12

Using a 1.8-V External Oscillator ............................................................................................... 50

3-13

Using the Internal Oscillator ..................................................................................................... 50

3-14

Watchdog Module ................................................................................................................. 52

4-1

CPU-Timers ........................................................................................................................ 54

4-2

CPU-Timer Interrupt Signals and Output Signal .............................................................................. 55

4-3

Multiple PWM Modules in a 280x System ..................................................................................... 56

4-4

ePWM Sub-Modules Showing Critical Internal Signal Interconnections ................................................... 58

4-5

eCAP Functional Block Diagram ................................................................................................ 59

4-6

eQEP Functional Block Diagram ................................................................................................ 61

4-7

Block Diagram of the ADC Module ............................................................................................. 64

4-8

ADC Pin Connections With Internal Reference ............................................................................... 65

4-9

ADC Pin Connections With External Reference .............................................................................. 66

4-10

eCAN Block Diagram and Interface Circuit .................................................................................... 69

4-11

eCAN-A Memory Map ............................................................................................................ 70

4-12

eCAN-B Memory Map ............................................................................................................ 71

4-13

Serial Communications Interface (SCI) Module Block Diagram ............................................................ 75

4-14

SPI Module Block Diagram (Slave Mode) ..................................................................................... 79

4-15

I2C Peripheral Module Interfaces ............................................................................................... 81

4-16

GPIO MUX Block Diagram ....................................................................................................... 82

4-17

Qualification Using Sampling Window.......................................................................................... 85

5-1

Example of TMS320x280x Device Nomenclature ............................................................................ 87

4

List of Figures

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

6-1

Typical Operational Current Versus Frequency (F2808) .................................................................... 98

6-2

Typical Operational Power Versus Frequency (F2808) ...................................................................... 98

6-3

Emulator Connection Without Signal Buffering for the DSP................................................................. 99

6-4

3.3-V Test Load Circuit ......................................................................................................... 101

6-5

Clock Timing ..................................................................................................................... 104

6-6

Power-on Reset .................................................................................................................. 105

6-7

Warm Reset ...................................................................................................................... 106

6-8

Example of Effect of Writing Into PLLCR Register .......................................................................... 107

6-9

General-Purpose Output Timing ............................................................................................... 107

6-10

Sampling Mode .................................................................................................................. 108

6-11

General-Purpose Input Timing ................................................................................................. 109

6-12

IDLE Entry and Exit Timing .................................................................................................... 110

6-13

STANDBY Entry and Exit Timing Diagram ................................................................................... 111

6-14

HALT Wake-Up Using GPIOn ................................................................................................. 112

6-15

PWM Hi-Z Characteristics ...................................................................................................... 113

6-16

ADCSOCAO or ADCSOCBO Timing ......................................................................................... 115

6-17

External Interrupt Timing ....................................................................................................... 115

6-18

SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 118

6-19

SPI Master Mode External Timing (Clock Phase = 1) ...................................................................... 120

6-20

SPI Slave Mode External Timing (Clock Phase = 0)........................................................................ 121

6-21

SPI Slave Mode External Timing (Clock Phase = 1)........................................................................ 122

6-22

ADC Power-Up Control Bit Timing ............................................................................................ 124

6-23

ADC Analog Input Impedance Model ......................................................................................... 125

6-24

Sequential Sampling Mode (Single-Channel) Timing ....................................................................... 126

6-25

Simultaneous Sampling Mode Timing ........................................................................................ 127

List of Figures

5

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

List of Tables
2-1

Hardware Features (100-MHz Devices)........................................................................................ 14

2-2

Hardware Features (60-MHz Devices) ......................................................................................... 15

2-3

Signal Descriptions ............................................................................................................... 21

3-1

Addresses of Flash Sectors in F2809 .......................................................................................... 33

3-2

Addresses of Flash Sectors in F2808 .......................................................................................... 33

3-3

Addresses of Flash Sectors in F2806, F2802 ................................................................................. 33

3-4

Addresses of Flash Sectors in F2801, F28015, F28016 ..................................................................... 34

3-5

Impact of Using the Code Security Module .................................................................................... 34

3-6

Wait-states ......................................................................................................................... 35

3-7

Boot Mode Selection.............................................................................................................. 38

3-8

Peripheral Frame 0 Registers .................................................................................................. 43

3-9

Peripheral Frame 1 Registers .................................................................................................. 43

3-10

Peripheral Frame 2 Registers .................................................................................................. 44

3-11

Device Emulation Registers ..................................................................................................... 44

3-12

PIE Peripheral Interrupts ........................................................................................................ 46

3-13

PIE Configuration and Control Registers ...................................................................................... 47

3-14

External Interrupt Registers ...................................................................................................... 47

3-15

PLL, Clocking, Watchdog, and Low-Power Mode Registers ................................................................ 49

3-16

PLLCR Register Bit Definitions .................................................................................................. 51

3-17

Possible PLL Configuration Modes ............................................................................................. 51

3-18

Low-Power Modes ................................................................................................................ 53

4-1

CPU-Timers 0, 1, 2 Configuration and Control Registers ................................................................... 55

4-2

ePWM Control and Status Registers ........................................................................................... 57

4-3

eCAP Control and Status Registers ............................................................................................ 59

4-4

eQEP Control and Status Registers ............................................................................................ 62

4-5

ADC Registers ..................................................................................................................... 67

4-6

3.3-V eCAN Transceivers ....................................................................................................... 69

4-7

CAN Register Map ............................................................................................................... 72

4-8

SCI-A Registers .................................................................................................................. 74

4-9

SCI-B Registers .................................................................................................................. 74

4-10

SPI-A Registers ................................................................................................................... 77

4-11

SPI-B Registers ................................................................................................................... 77

4-12

SPI-C Registers ................................................................................................................... 78

4-13

SPI-D Registers ................................................................................................................... 78

4-14

I2C-A Registers.................................................................................................................... 81

4-15

GPIO Registers ................................................................................................................... 83

4-16

F2808 GPIO MUX Table ......................................................................................................... 84

6-1

TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT............ 93

6-2

TMS320F2806 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT .............................. 94

6

List of Tables

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

6-3

TMS320F2802, TMS320F2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT............ 95

6-4

TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT ........... 96

6-5

Typical Current Consumption by Various Peripherals (at 100 MHz) ...................................................... 97

6-6

TMS320x280x Clock Table and Nomenclature (100-MHz Devices) ...................................................... 101

6-7

TMS320x280x Clock Table and Nomenclature (60-MHz Devices) ....................................................... 102

6-8

Input Clock Frequency .......................................................................................................... 103

6-9

XCLKIN Timing Requirements - PLL Enabled ............................................................................... 103

6-10

XCLKIN Timing Requirements - PLL Disabled .............................................................................. 103

6-11

XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ....................................................... 103

6-12

Power Management and Supervisory Circuit Solutions .................................................................... 104

6-13

Reset (XRS) Timing Requirements ........................................................................................... 106

6-14

General-Purpose Output Switching Characteristics ......................................................................... 107

6-15

General-Purpose Input Timing Requirements ............................................................................... 108

6-16

IDLE Mode Timing Requirements ............................................................................................. 110

6-17

IDLE Mode Switching Characteristics......................................................................................... 110

6-18

STANDBY Mode Timing Requirements ...................................................................................... 110

6-19

STANDBY Mode Switching Characteristics ................................................................................. 111

6-20

HALT Mode Timing Requirements ............................................................................................ 111

6-21

HALT Mode Switching Characteristics ....................................................................................... 112

6-22

ePWM Timing Requirements................................................................................................... 113

6-23

ePWM Switching Characteristics .............................................................................................. 113

6-24

Trip-Zone input Timing Requirements ........................................................................................ 113

6-25

High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz) .............................................. 114

6-26

Enhanced Capture (eCAP) Timing Requirement ............................................................................ 114

6-27

eCAP Switching Characteristics ............................................................................................... 114

6-28

Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................... 114

6-29

eQEP Switching Characteristics ............................................................................................... 114

6-30

External ADC Start-of-Conversion Switching Characteristics.............................................................. 114

6-31

External Interrupt Timing Requirements ...................................................................................... 115

6-32

External Interrupt Switching Characteristics ................................................................................. 115

6-33

I2C Timing ....................................................................................................................... 116

6-34

SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 117

6-35

SPI Master Mode External Timing (Clock Phase = 1) ...................................................................... 119

6-36

SPI Slave Mode External Timing (Clock Phase = 0)........................................................................ 120

6-37

SPI Slave Mode External Timing (Clock Phase = 1)........................................................................ 121

6-38

ADC Electrical Characteristics (over recommended operating conditions) .............................................. 123

6-39

ADC Power-Up Delays.......................................................................................................... 124

6-40

Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK) ....................................... 124

6-41

Sequential Sampling Mode Timing ............................................................................................ 126

6-42

Simultaneous Sampling Mode Timing ........................................................................................ 127

6-43

Flash Endurance ................................................................................................................. 129
List of Tables

7

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

6-44

Flash Parameters at 100-MHz SYSCLKOUT ................................................................................ 129

6-45Flash/OTP Access Timing ...................................................................................................... 129

6-46

Minimum Required Flash/OTP Wait-States at Different Frequencies .................................................... 130

6-47

ROM/OTP Access Timing ...................................................................................................... 130

6-48

ROM/ROM (OTP area) Minimum Required Wait-States at Different Frequencies ..................................... 130

8-1

F280x Thermal Model 100-pin GGM Results ................................................................................ 132

8-2

F280x Thermal Model 100-pin PZ Results ................................................................................... 132

8-3

C280x Thermal Model 100-pin GGM Results................................................................................ 132

8-4

C280x Thermal Model 100-pin PZ Results................................................................................... 132

8-5

F2809 Thermal Model 100-pin GGM Results ............................................................................... 132

8-6

F2809 Thermal Model 100-pin PZ Results .................................................................................. 133

8

List of Tables

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual was revised from SPRS230I to SPRS230J.
This document has been reviewed for technical accuracy; the technical content is up to date as of thespecified release date with the following changes:
Technical Changes Made for Revision J
Location

Additions, Deletions, Changes

Section 2.1

Modified first paragraph in section on pin assignments

Figure 2-3

Modified the TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP
pinmapFigure 2-5

Added 2801x devices to title of pinmap for GGM and ZGM packages

Table 2-3

Changed description of EPWM5A and EPWM6A

Figure 3-5

Added a note to the 2802 memory map

Figure 3-6

Added a note to the 2801, 2801x memory map

Table 3-6

Modified Wait-states table

Table 3-6

Modified section on ROM

Section 3.2.10

Deleted part of note in section on security

Section 3.2.19

Modified section on 32-bit CPU timers

Figure 3-7

Modified External and PIE Interrupt Sources figure and added two paragraphs following figure

Figure 4-2

Modified figure

Section 4.3

Deleted note in HRPWM section

Revision History

9

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

10

Revision History

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www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

1

F280x, F2801x, C280x DSPs

1.1

Features

•

•
•

•

•

•

•
•
•

•

(1)

High-Performance Static CMOS Technology– 100 MHz (10-ns Cycle Time)– 60 MHz (16.67-ns Cycle Time)– Low-Power (1.8-V Core, 3.3-V I/O) Design
JTAG Boundary Scan Support (1)High-Performance 32-Bit CPU (TMS320C28x)– 16 x 16 and 32 x 32 MAC Operations– 16 x 16 Dual MAC– Harvard Bus Architecture– Atomic Operations– Fast Interrupt Response and Processing– Unified Memory Programming Model– Code-Efficient (in C/C++ and Assembly)
On-Chip Memory– F2809: 128K X 16 Flash, 18K X 16 SARAM
F2808: 64K X 16 Flash, 18K X 16 SARAM
F2806: 32K X 16 Flash, 10K X 16 SARAM
F2802: 32K X 16 Flash, 6K X 16 SARAM
F2801: 16K X 16 Flash, 6K X 16 SARAM
F2801x: 16K X 16 Flash, 6K X 16 SARAM– 1K x 16 OTP ROM (Flash Devices Only)– C2802: 32K X 16 ROM, 6K X 16 SARAM
C2801: 16K X 16 ROM, 6K X 16 SARAM
Boot ROM (4K x 16)– With Software Boot Modes (via SCI, SPI,
CAN, I2C, and Parallel I/O)
– Standard Math Tables
Clock and System Control– Dynamic PLL Ratio Changes Supported– On-Chip Oscillator– Watchdog Timer Module
Any GPIO A Pin Can Be Connected to One of
the Three External Core Interrupts
Peripheral Interrupt Expansion (PIE) BlockThat Supports All 43 Peripheral Interrupts
128-Bit Security Key/Lock– Protects Flash/OTP/L0/L1 Blocks– Prevents Firmware Reverse Engineering
Three 32-Bit CPU Timers

•

•

•

•
•

•

•

•

•

Enhanced Control Peripherals– Up to 16 PWM Outputs– Up to 6 HRPWM Outputs With 150 ps MEPResolution– Up to Four Capture Inputs– Up to Two Quadrature Encoder Interfaces– Up to Six 32-bit/Six 16-bit Timers
Serial Port Peripherals– Up to 4 SPI Modules– Up to 2 SCI (UART) Modules– Up to 2 CAN Modules– One Inter-Integrated-Circuit (I2C) Bus
12-Bit ADC, 16 Channels– 2 x 8 Channel Input Multiplexer– Two Sample-and-Hold– Single/Simultaneous Conversions– Fast Conversion Rate:
80 ns - 12.5 MSPS (F2809 only)
160 ns - 6.25 MSPS (280x)
267 ns - 3.75 MSPS (F2801x)– Internal or External Reference
Up to 35 Individually Programmable,
Multiplexed GPIO Pins With Input Filtering
Advanced Emulation Features– Analysis and Breakpoint Functions– Real-Time Debug via Hardware
Development Support Includes– ANSI C/C++ Compiler/Assembler/Linker– Code Composer Studio™ IDE– DSP/BIOS™
– Digital Motor Control and Digital Power
Software Libraries
Low-Power Modes and Power Savings– IDLE, STANDBY, HALT Modes Supported– Disable Individual Peripheral Clocks
Package Options– Thin Quad Flatpack (PZ)
– MicroStar BGA™ (GGM, ZGM)
Temperature Options:– A: -40C to 85C (PZ, GGM, ZGM)
– S: -40C to 125C (PZ, GGM, ZGM)
– Q: -40C to 125C (PZ)

IEEE Standard 1149.1-1990 Standard Test Access Port andBoundary Scan Architecture

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
Code Composer Studio, DSP/BIOS, MicroStar BGA, TMS320C28x, C28x, TMS320C2000 are trademarks of Texas Instruments.
eZdsp is a trademark of Spectrum Digital.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does notnecessarily include testing of all parameters.

Copyright © 2003–2007, Texas Instruments Incorporated

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

www.ti.com

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

1.2

Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x device. For moredetail on each of these steps, see the following:• Getting Started With TMS320C28x™ Digital Signal Controllers (literature number SPRAAM0).
• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)
Step 1. Acquire the appropriate development tools
The quickest way to begin working with a C28x device is to acquire an eZdsp™ kit for initialdevelopment, which, in one package, includes:• On-board JTAG emulation via USB or parallel port
• Appropriate emulation driver• Code Composer Studio™ IDE for eZdsp
Once you have become familiar with the device and begin developing on your own
hardware, purchase Code Composer Studio™ IDE separately for software development anda JTAG emulation tool to get started on your project.
Step 2. Download starter software
To simplify programming for C28x devices, it is recommended that users download and use
the C/C++ Header Files and Example(s) to begin developing software for the C28x devices
and their various peripherals.
After downloading the appropriate header file package for your device, refer to the following
resources for step-by-step instructions on how to run the peripheral examples and use theheader file structure for your own software• The Quick Start Readme in the /doc directory to run your first application.
• Programming TMS320x28xx and 28xxx Peripherals in C/C++ Application Report(literature number SPRAA85)
Step 3. Download flash programming software
Many C28x devices include on-chip flash memory and tools that allow you to program theflash with your software IP.
• Flash Tools: C28x Flash Tools• TMS320F281x Flash Programming Solutions (literature number SPRB169)• Running an Application from Internal Flash Memory on the TMS320F28xx DSP (literature
number SPRA958)
Step 4. Move on to more advanced topics
For more application software and other advanced topics, visit the TI website at
http://www.ti.com or http://www.ti.com/c2000getstarted.

12

F280x, F2801x, C280x DSPs

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

2

Introduction
The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320F28015,
TMS320F28016, TMS320C2802, and TMS320C2801, devices, members of the TMS320C28x™ DSP
generation, are highly integrated, high-performance solutions for demanding control applications.
Throughout this document, TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802,
TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28015, and TMS32028016 are abbreviated as
F2809, F2808, F2806, F2802, F2801, F28015, F28016, C2802, and C2801, respectively. TMS320F28015
and TMS320F28016 are abbreviated as F2801x. Table 2-1 provides a summary of features for eachdevice.

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TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 2-1. Hardware Features (100-MHz Devices)
FEATURE
Instruction cycle (at 100 MHz)
Single-access RAM (SARAM) (16-bit word)
3.3-V on-chip flash (16-bit word)

F2809

F2808

F2806

F2802

F2801

C2802

C2801

10 ns

10 ns

10 ns

10 ns

10 ns

10 ns

10 ns

18K
(L0, L1, M0, M1,
H0)

18K(L0, L1, M0, M1,
H0)

10K(L0, L1, M0, M1)

6K(L0, M0, M1)

6K(L0, M0, M1)

6K(L0, M0, M1)

6K(L0, M0, M1)

128K

64K

32K

32K

16K

–

–

On-chip ROM (16-bit word)

–

–

–

–

–

32K

16K

Code security for on-chip flash/SARAM/OTP blocks

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Boot ROM (4K X16)

Yes

Yes

Yes

Yes

Yes

Yes

Yes

One-time programmable (OTP) ROM(16-bit word)

1K

1K

1K

1K

1K

–

–

PWM outputs

ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6

ePWM1/2/3

ePWM1/2/3

ePWM1/2/3

ePWM1/2/3

HRPWM channels

ePWM1A/2A/3A/
4A/5A/6A

ePWM1A/2A/
3A/4A

ePWM1A/2A/
3A/4A

ePWM1A/2A/3A

ePWM1A/2A/3A

ePWM1A/2A/3A

ePWM1A/2A/3A

eCAP1/2/3/4

eCAP1/2/3/4

eCAP1/2/3/4

eCAP1/2

eCAP1/2

eCAP1/2

eCAP1/2eQEP132-bit CAPTURE inputs or auxiliary PWM outputs
32-bit QEP channels (four inputs/channel)

eQEP1/2

eQEP1/2

eQEP1/2

eQEP1

eQEP1

eQEP1

Watchdog timer

Yes

Yes

Yes

Yes

Yes

Yes

Yes

12-Bit, 16-channel ADC conversion time

80 ns

160 ns160 ns160 ns160 ns160 ns160 ns32-Bit CPU timers

3

3

3

3

3

3

3

SPI-A/B/C/D

SPI-A/B/C/D

SPI-A/B/C/D

SPI-A/B

SPI-A/B

SPI-A/B

SPI-A/B

Serial Communications Interface (SCI)SCI-A/B

SCI-A/B

SCI-A/B

SCI-A

SCI-A

SCI-A

SCI-A

Enhanced Controller Area Network (eCAN)

eCAN-A/B

eCAN-A/B

eCAN-AeCAN-AeCAN-AeCAN-AeCAN-A

I2C-A

I2C-A

I2C-A

I2C-A

I2C-A

I2C-A

I2C-A

Digital I/O pins (shared)

35

35

35

35

35

35

35

External interrupts

3

3

3

3

3

3

3

1.8-V Core, 3.3-V I/O

Yes

Yes

Yes

Yes

Yes

Yes

Yes

100-Pin PZ

Yes

Yes

Yes

Yes

Yes

Yes

Yes

100-Ball GGM, ZGM

Yes

Yes

Yes

Yes

Yes

Yes

Yes

A: -40°C to 85°C

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

S: -40°C to 125°C(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

Q: -40°C to 125°C

(PZ)

(PZ)

(PZ)

(PZ)

(PZ)

(PZ)

(PZ)

TMS

TMS

TMS

TMS

TMS

TMS

TMS

Serial Peripheral Interface (SPI)Inter-Integrated Circuit (I2C)

Supply voltage
PackagingTemperature options
Product status
(1)

14

(1)

See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages.

Introduction

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TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 2-2. Hardware Features (60-MHz Devices)
FEATURE

F2802-60

F2801-60

F28016

F28015

Instruction cycle (at 60 MHz)

16.67 ns

16.67 ns

16.67 ns

16.67 ns

6K
(L0, M0, M1)

6K(L0, M0, M1)

6K(L0, M0, M1)

6K(L0, M0, M1)

3.3-V on-chip flash (16-bit word)

32K

16K

16K

16K

On-chip ROM (16-bit word)

–

–

–

–

Code security for on-chip flash/SARAM/OTP
blocks

Yes

Yes

Yes

Yes

Boot ROM (4K X16)

Yes

Yes

Yes

Yes

One-time programmable (OTP) ROM(16-bit word)

1K

1K

1K

1K

Single-access RAM (SARAM) (16-bit word)

PWM outputs

ePWM1/2/3

ePWM1/2/3

ePWM1/2/3/4

ePWM1/2/3/4

ePWM1A/2A/3A

ePWM1A/2A/3A

ePWM1A/2A/3A/4A

ePWM1A/2A/3A/4A

32-bit CAPTURE inputs or auxiliary PWM
outputs

eCAP1/2

eCAP1/2

eCAP1/2

eCAP1/2

32-bit QEP channels (four inputs/channel)

eQEP1

eQEP1

-

Yes

HRPWM channels

Watchdog timer

Yes

Yes

Yes

No. of channels

16

16

16

16

MSPS

3.75

3.75

3.75

3.75

Conversion time

267 ns267 ns267 ns267 ns3

3

3

3

Serial Peripheral Interface (SPI)SPI-A/B

SPI-A/B

SPI-A

SPI-A

Serial Communications Interface (SCI)

SCI-A

SCI-A

SCI-A

SCI-A

Enhanced Controller Area Network (eCAN)

eCAN-AeCAN-AeCAN-A-

Inter-Integrated Circuit (I2C)

I2C-A

I2C-A

I2C-A

I2C-A

35

35

35

35

12-Bit ADC
32-Bit CPU timers

Digital I/O pins (shared)
External interrupts
Supply voltage
PackagingTemperature options

100-Pin PZ
100-Ball GGM, ZGM

3

3

1.8-V Core,
3.3-V I/O

1.8-V Core,
3.3-V I/O

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

S: -40°C to 125°C(PZ GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

(PZ, GGM, ZGM)

Q: -40°C to 125°C

2.1

3
1.8-V Core,
3.3-V I/O

A: -40°C to 85°C

Product status (1)(1)

3
1.8-V Core,
3.3-V I/O

(PZ)

(PZ)

(PZ)

(PZ)

TMS

TMS

TMS

TMS

See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages.

Pin Assignments
The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28015, and TMS320F28016 100-pin PZ low-profile quad flatpack (LQFP) pin
assignments are shown in Figure 2-1, Figure 2-2, Figure 2-3, and Figure 2-4. The 100-ball GGM and ZGM
ball grid array (BGA) terminal assignments are shown in Figure 2-5. Table 2-3 describes the function(s) ofeach pin.

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TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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52

GPIO18/SPICLKA/SCITXDBGPIO5/EPWM3B/SPICLKD/ECAP1
GPIO17/SPISOMIA/CANRXB/TZ6
GPIO4/EPWM3A

54

53

51

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
VSS
56

55

GPIO7/EPWM4B/SPISTED/ECAP2

GPIO19/SPISTEA/SCIRXDB
57

59

58

GPIO9/EPWM5B/SCITXDB/ECAP3
GPIO8/EPWM5A/CANTXB/ADCSOCAO
VDD
61

60

GPIO20/EQEP1A/SPISIMOC/CANTXB
VSS
63

62

GPIO10/EPWM6A/CANRXB/ADCSOCBO
64

65

GPIO21/EQEP1B/SPISOMIC/CANRXBXCLKOUT
VDDIO
66

68

67

GPIO11/EPWM6B/SCIRXDB/ECAP4
VSS
VDD
69

70

71

TDI

GPIO23/EQEP1I/SPISTEC/SCIRXDBGPIO22/EQEP1S/SPICLKC/SCITXDB

73

72

TCK

TMS

75

74

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

46

EMU1
VDDIO

81

45

82

44

GPIO24/ECAP1/EQEP2A/SPISIMOB

83

43

TRST

84

42

GPIO34
VDD

VDD
X2

85

41

VSS

86

40

VSS
X1

87

39

VDD2A18
VSS2AGND

88

38

ADCRESEXT

VSS

89

37

XCLKIN90

36

ADCREFPADCREFMGPIO25/ECAP2/EQEP2B/SPISOMIB

91

35

GPIO28/SCIRXDA/TZ5
VDD

92

34

93

33

VSS

94

32

GPIO13/TZ2/CANRXB/SPISOMIB
VDD3VFL

95

31

96

30

TEST1
TEST2

97

29

ADCINB3
ADCINB2

98

28

ADCINB1

GPIO26/ECAP3/EQEP2I/SPICLKB

99

27

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

100

26

ADCINB0
VDDAIO

22

24

25

ADCLO

VSSAIO

2023

19

ADCINA4ADCINA01718

ADCINA6ADCINA5ADCINA3ADCINA2
ADCINA1

1516

ADCINA7

14

VSSA2
VDDA2

13

VSS1AGND

11

12

9

GPIO15/TZ4/SCIRXDB/SPISTEB
VDD
VSS
VDD1A18

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO30/CANRXAGPIO31/CANTXAGPIO14/TZ3/SCITXDB/SPICLKB3

GPIO29/SCITXDA/TZ6

21

80

GPIO3/EPWM2B/SPISOMID
GPIO0/EPWM1A
VDDIO

10

47

8

79

7

GPIO27/ECAP4/EQEP2S/SPISTEB
EMU0

5

48

6

78

4

VSS

XRS

1

GPIO16/SPISIMOA/CANTXB/TZ5

49

2

50

77

VSS
VDDIO

76

GPIO12/TZ1/CANTXB/SPISIMOB

TDO
VSS

GPIO2/EPWM2A
GPIO1/EPWM1B/SPISIMOD

ADCREFIN
ADCINB7ADCINB6ADCINB5ADCINB4

Figure 2-1. TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View)

16

Introduction

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TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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GPIO4/EPWM3A
51

52

GPIO18/SPICLKA/SCITXDBGPIO5/EPWM3B/SPICLKD/ECAP1
GPIO17/SPISOMIA/TZ6

54

53

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
VSS
56

55

GPIO7/EPWM4B/SPISTED/ECAP2

GPIO19/SPISTEA/SCIRXDBGPIO8/EPWM5A/ADCSOCAO
VDD

58

GPIO9/EPWM5B/SCITXDB/ECAP3
61

60

57

GPIO20/EQEP1A/SPISIMOC
VSS

59

GPIO10/EPWM6A/ADCSOCBO
64

63

62

XCLKOUT
VDDIO
66

65

GPIO21/EQEP1B/SPISOMIC
67

68

GPIO11/EPWM6B/SCIRXDB/ECAP4
VSS
VDD
69

70

71

TDI

GPIO23/EQEP1I/SPISTEC/SCIRXDBGPIO22/EQEP1S/SPICLKC/SCITXDB

73

72

TCK

TMS

75

74

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

50

GPIO16/SPISIMOA/TZ5

77

49

VSS

78

48

GPIO3/EPWM2B/SPISOMID

79

47

EMU0
EMU1
VDDIO

80

46

GPIO0/EPWM1A
VDDIO

81

45

GPIO2/EPWM2A

82

44

GPIO24/ECAP1/EQEP2A/SPISIMOB
TRST

83

43

84

42

GPIO1/EPWM1B/SPISIMOD
GPIO34
VDD

VDD

85

41

VSS

X2
VSS

86

40

87

39

VDD2A18
VSS2AGND

X1
VSS

88

38

ADCRESEXT

89

37

ADCREFPXCLKIN90

36

ADCREFMGPIO25/ECAP2/EQEP2B/SPISOMIB

91

35

GPIO28/SCIRXDA/TZ5
VDD

92

34

ADCREFIN
ADCINB79333

ADCINB6VSS
GPIO13/TZ2/SPISOMIB
VDD3VFL

94

32

ADCINB595

31ADCINB4

96

30

TEST1
TEST2

97

29

ADCINB3
ADCINB2

98

TDO
VSS
XRS

76

GPIO27/ECAP4/EQEP2S/SPISTEB

24

22

23

ADCINA1

ADCINA0ADCLOVSSAIO25

20

21

ADCINA3ADCINA21819

ADCINA517ADCINA6ADCINA4

15

14

VSSA2

16

12

13

VDD1A18
VSS1AGND

VDDA2

11

VSS

ADCINA7

10

8

GPIO31/CANTXAGPIO14/TZ3/SCITXDB/SPICLKB

97GPIO30/CANRXAGPIO15/TZ4/SCIRXDB/SPISTEB
VDD

5

6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

23ADCINB0
VDDAIO

4

26

VDDIO

100

GPIO29/SCITXDA/TZ6

ADCINB1

27
1

28

99

GPIO12/TZ1/SPISIMOBVSSGPIO26/ECAP3/EQEP2I/SPICLKBGPIO32/SDAA/EPWMSYNCI/ADCSOCAO

Figure 2-2. TMS320F2806 100-Pin PZ LQFP (Top View)

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TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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GPIO17/SPISOMIA/TZ6

GPIO4/EPWM3A

52

51

54

53

56

55

GPIO7/ECAP2

GPIO19/SPISTEAGPIO6/EPWMSYNCI/EPWMSYNCO
VSSGPIO18/SPICLKA
GPIO5/EPWM3B/ECAP158

GPIO8/ADCSOCAO
VDD
60

57

GPIO20/EQEP1A
VSS
GPIO9

59

GPIO10/ADCSOCBO
64

63

61

XCLKOUT
VDDIO
66

62

GPIO21/EQEP1B
67

65

GPIO11
VSS
VDD
68GPIO22/EQEP1S
71

70

69

TDI
GPIO23/EQEP1I
73

GPIO16/SPISIMOA/TZ5
VSS

TDO
VSS

76

50

77

49

XRS
SPISTEB/GPIO27

78

48

79

47

EMU0

80

46

EMU1
VDDIO
SPISIMOB/GPIO24/ECAP1
TRST

81

45

82

44

83

43

84

42

VDD

85

41

VSS

X2
VSS

86

40

87

39

VDD2A18
VSS2AGND

GPIO3/EPWM2B
GPIO0/EPWM1A
VDDIO
GPIO2/EPWM2A
GPIO1/EPWM1B
GPIO34VDD

ADCINA624

17

ADCINA7

25

15

16

VDD1A18
VSS1AGND
VSSA2
VDDA2

9

3

4

1

VDDIO

VSS

SPISIMOB/GPIO12/TZ1ADCLO
VSSAIOADCINB0
VDDAIO

2226

23

ADCINB127

100

ADCINA1

28

99

ADCINA098

20

ADCINB3
ADCINB22129

ADCINA3

97

ADCINA2

TEST1
TEST2
SPICLKB/GPIO26
GPIO32/SDAA/EPWMSYNCI/ADSOCAO

18

ADCINB4

30

19

31

96

ADCINA595(A)

ADCINA4ADCINB5SPISOMIB/GPIO13/TZ2

14ADCINB6

32

12

33

94

13

93

11

ADCREFIN
ADCINB7

VSS

34

10

35

92

8

91

SPICLKB/GPIO14/TZ3SPISTEB/GPIO15/TZ4VDD

ADCREFMGPIO25/ECAP2/SPISOMIBGPIO28/SCIRXDA/TZ5
VDD
VSS

7

36

GPIO31/CANTXA

90

5ADCREFPXCLKIN

6ADCRESEXT

37

GPIO30/CANRXA

38

89

GPIO29/SCITXDA/TZ6
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

88

2

X1
VSS

VDD3VFL

A.

72

TCK

TMS

75

74

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

On the C280x devices, the VDD3VFL pin is VDDIO.

Figure 2-3. TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP
(Top View)

18

Introduction

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TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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A.

GPIO17/SPISOMIA/TZ6

GPIO4/EPWM3A

52

51

54

53

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
VSSGPIO18/SPICLKA
GPIO5/EPWM3B/ECAP156

55

GPIO7/EPWM4B/ECAP2

GPIO19/SPISTEA

58

57

GPIO8/ADCSOCAO
VDD
60

59

62

61

GPIO10/ADCSOCBO

GPIO20
VSS
GPIO9

64

63

XCLKOUTVDDIO
65GPIO21
67

66

69

68

GPIO22
GPIO11
VSS
VDD
71

70

TDI
GPIO23
73

72

TCK

TMS

75

74

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

GPIO16/SPISIMOA/TZ5
VSS

TDO
VSS

76

50

77

49

XRS
GPIO27

78

48

79

47

EMU0

80

46

EMU1
VDDIO
GPIO24/ECAP1

81

45

82

44

83

43

TRST

84

42

VDD

85

41

VSS

X2
VSS

86

40

87

39

VDD2A18
VSS2AGND

GPIO3/EPWM2B
GPIO0/EPWM1A
VDDIO
GPIO2/EPWM2A
GPIO1/EPWM1B
GPIO34
VDD

24

ADCLO
VSSAIO25

22

23

ADCINA1

ADCINA0

14

13

7

8

6

20

ADCINB0
VDDAIO

21

26

ADCINA3100

ADCINA2

ADCINB1

27

18

28

99

19

98

GPIO26
GPIO32/SDAA/EPWMSYNCI/ADSOCAO

ADCINA5ADCINB3
ADCINB2

ADCINA4

29

16

TEST1
TEST2

17

30

97

ADCINA796

ADCINA6ADCINB4VDD3VFL(A)

15

31

12

95

VDD1A18
VSS1AGND
VSSA2
VDDA2

ADCINB5

GPIO13/TZ2

11

ADCINB6

32

VSS

33

94

9

93

10

ADCREFIN
ADCINB7

VDD

34

GPIO31/CANTXAGPIO14/TZ3
GPIO15/TZ4

92

5

35

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO30/CANRXA

91

3ADCREFMGPIO25/ECAP2
GPIO28/SCIRXDA/TZ5
VDD
VSS

4

36

VDDIO

90

GPIO29/SCITXDA/TZ6

ADCREFPXCLKIN

1

ADCRESEXT

37

2

38

89

VSS

88

GPIO12/TZ1X1VSSCANTXA (pin 7) and CANRXA (pin 6) pins are not applicable for the TMS320F28015.

Figure 2-4. TMS320F2801x 100-Pin PZ LQFP
(Top View)

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TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

K

J

H

G

F

E

D

C

B

A

ADCINB0

ADCINB3

ADCINB5ADCINB7

VSS2AGND

GPIO1

GPIO0

VSS

GPIO16ADCLO

VDDAIOADCINB1

ADCINB4

ADCREFIN

VDD2A18

GPIO2

GPIO3

GPIO4

GPIO17ADCINA1

ADCINA0

ADCINB2

ADCINB6

ADCREFM

VSS

VDDIO

GPIO18GPIO5VSSADCINA4ADCINA3ADCINA2

ADCINA5

ADCREFPVDD

GPIO34

GPIO7

GPIO6

GPIO19

VSSA2

VDDA2

ADCINA7ADCINA6

ADCRESEXTGPIO20

VSS

GPIO9

GPIO8

VDD

GPIO15VDD

VSS

VDD1A18

VSS1AGND

X1

GPIO21XCLKOUTVDDIOGPIO10

GPIO31

GPIO30

GPIO14VDD

GPIO28VSS

VDD

GPIO22

GPIO11VSS

GPIO33

VDDIO

GPIO29VDD3VFLGPIO25X2

GPIO24

GPIO27TDI

GPIO23VSS

GPIO12TEST2GPIO13XCLKIN

VDD

EMU1

XRS

TDO

TMS

GPIO32

GPIO26

TEST1

VSS

VSS

TRST

VDDIO

EMU0

VSS

TCK

1

2

3

4

5

6

7

8

9

10

VSSAIO

Bottom View

Figure 2-5. TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801,
TMS320F28016, TMS320F28015, TMS320C2802, TMS320C2801
100-Ball GGM and ZGM MicroStar BGA™ (Bottom View)

20

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TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

2.2

Signal Descriptions
Table 2-3 describes the signals on the 280x devices. All digital inputs are TTL-compatible. All outputs are
3.3 V with CMOS levels. Inputs are not 5-V tolerant.
Table 2-3. Signal Descriptions
PIN NO.
NAME

PZ
PIN #

GGM/
ZGM
BALL #DESCRIPTION (1)

JTAG

TRST

84

A6

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active
high test pin and must be maintained low at all times during normal device operation. In a low-noise
environment, TRST may be left floating. In other instances, an external pulldown resistor is highly
recommended. The value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this isapplication-specific, it is recommended that each target board be validated for proper operation of
the debugger and the application. (I, ↓)

TCK

75

A10

JTAG test clock with internal pullup (I, ↑)

TMS

74

B10

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I, ↑)

TDI

73

C9

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK. (I, ↑)

TDO

76

B9

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)

A8

Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put thedevice into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at alogic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
(I/O/Z, 8 mA drive ↑)NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should bebased on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.

B7

Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put thedevice into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at alogic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
(I/O/Z, 8 mA drive ↑)NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should bebased on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.

EMU0

EMU1

80

81

FLASH
VDD3VFL

96

C4

3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. On the ROM
parts (C280x), this pin should be connected to VDDIO.

TEST1

97

A3

Test Pin. Reserved for TI. Must be left unconnected. (I/O)

TEST2

98

B3

Test Pin. Reserved for TI. Must be left unconnected. (I/O)
CLOCK

XCLKOUT

66

E8

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half thefrequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0
(XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal
can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is notplaced in high-impedance state during a reset. (O/Z, 8 mA drive).

XCLKIN90

B5

External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.8-V oscillator isused to feed clock to X1 pin), this pin must be tied to GND. (I)(1)

I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown

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TMS320F2802, TMS320F2801
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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 2-3. Signal Descriptions (continued)
PIN NO.
NAME

PZ
PIN #

GGM/
ZGM
BALL #DESCRIPTION (1)

X1

88

E6

Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic
resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital
power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN
pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 mustbe tied to GND. (I)

X2

86

C6

Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 andX2. If X2 is not used it must be left unconnected. (O)
RESET

XRS

78

B8

Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the addresscontained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at thelocation pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑)The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin
be driven by an open-drain device.

ADCINA716F3

ADC Group A, Channel 7 input (I)

ADCINA617F4ADC Group A, Channel 6 input (I)

ADCINA518

G4ADC Group A, Channel 5 input (I)

ADCINA419G1

ADC Group A, Channel 4 input (I)

ADCINA320G2

ADC Group A, Channel 3 input (I)

ADCINA221

G3

ADC Group A, Channel 2 input (I)

ADCINA1

22

H1

ADC Group A, Channel 1 input (I)

ADCINA023

H2

ADC Group A, Channel 0 input (I)

ADCINB734K5ADC Group B, Channel 7 input (I)

ADCINB633

H4ADC Group B, Channel 6 input (I)

ADCINB532

K4ADC Group B, Channel 5 input (I)

ADCINB431

J4ADC Group B, Channel 4 input (I)

ADCINB330

K3ADC Group B, Channel 3 input (I)

ADCINB229

H3

ADC Group B, Channel 2 input (I)

ADCINB128J3ADC Group B, Channel 1 input (I)

ADCINB027

K2

ADC Group B, Channel 0 input (I)

ADCLO

24

J1

Low Reference (connect to analog ground) (I)

ADCRESEXT38

F5ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.

ADCREFIN

35

J5External reference input (I)

ADCREFP37

G5Internal Reference Positive Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass capacitorof 2.2 μF to analog ground. (O)

ADCREFM36

H5Internal Reference Medium Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass capacitorof 2.2 μF to analog ground. (O)

VDDA2

15

F2

ADC Analog Power Pin (3.3 V)

VSSA2

14

F1

ADC Analog Ground Pin

VDDAIO26

J2

ADC Analog I/O Power Pin (3.3 V)

VSSAIO

25

K1

ADC Analog I/O Ground Pin

VDD1A1812E4ADC Analog Power Pin (1.8 V)

VSS1AGND

13

E5

ADC Analog Ground Pin

VDD2A1840J6ADC Analog Power Pin (1.8 V)

VSS2AGND

39

K6

ADC Analog Ground Pin

ADC SIGNALSCPU AND I/O POWER PINS

22

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TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 2-3. Signal Descriptions (continued)
PIN NO.
NAME

PZ
PIN #

GGM/
ZGM
BALL #

VDD

10

E2

VDD

42

G6

VDD

59

F10

VDD

68

D7

VDD

85

B6

VDD

93

D4

VDDIO

3

C2

VDDIO

46

H7

VDDIO

65

E9

VDDIO

82

A7

VSS

2

B1

VSS

11

E3

VSS

41

H6

VSS

49

K9

VSS

55

H10

VSS

62

F7

VSS

69

D10

VSS

77

A9

VSS

87

D6

VSS

89

A5

VSS

94

A4

DESCRIPTION (1)CPU and Logic Digital Power Pins (1.8 V)

Digital I/O Power Pin (3.3 V)

Digital Ground Pins

GPIOA AND PERIPHERAL SIGNALS (2) (3)GPIO0
EPWM1AGPIO1
EPWM1BSPISIMODGPIO2
EPWM2AGPIO3
EPWM2BSPISOMID
GPIO4
EPWM3AGPIO5
EPWM3BSPICLKD
ECAP1

(2)
(3)
(4)

47

44

K8

General purpose input/output 0 (I/O/Z) (4)Enhanced PWM1 Output A and HRPWM channel (O)-K7

General purpose input/output 1 (I/O/Z) (4)Enhanced PWM1 Output B (O)SPI-D slave in, master out (I/O) (not available on 2801, 2802)-

J7

General purpose input/output 2 (I/O/Z) (4)Enhanced PWM2 Output A and HRPWM channel (O)-J8General purpose input/output 3 (I/O/Z) (4)Enhanced PWM2 Output B (O)SPI-D slave out, master in (I/O) (not available on 2801, 2802)-

J9

General purpose input/output 4 (I/O/Z) (4)Enhanced PWM3 output A and HRPWM channel (O)-H9General purpose input/output 5 (I/O/Z) (4)Enhanced PWM3 output B (O)SPI-D clock (I/O) (not available on 2801, 2802)
Enhanced capture input/output 1 (I/O)

45

48

51

53

Some peripheral functions may not be available in TMS320F2801x devices. See Table 2-2 for details.
All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively
enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at
reset. The peripheral signals that are listed under them are alternate functions.
The pullups on GPIO0-GPIO11 pins are not enabled at reset.

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TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 2-3. Signal Descriptions (continued)
PIN NO.
NAME

GPIO6
EPWM4AEPWMSYNCIEPWMSYNCO
GPIO7
EPWM4BSPISTEDECAP2
GPIO8
EPWM5ACANTXB
ADCSOCAOGPIO9
EPWM5BSCITXDBECAP3
GPIO10EPWM6ACANRXB
ADCSOCBO
GPIO11EPWM6BSCIRXDBECAP4
GPIO12TZ1CANTXBSPISIMOB
GPIO13TZ2CANRXBSPISOMIBGPIO14TZ3SCITXDBSPICLKB
GPIO15TZ4SCIRXDBSPISTEB
GPIO16SPISIMOACANTXB
TZ5
GPIO17SPISOMIACANRXB
TZ6
GPIO18SPICLKASCITXDB
GPIO19SPISTEASCIRXDB
(5)
24

PZ
PIN #

56

58

60

61

64

70

1

95

8

9

50

52

54

57

GGM/
ZGM
BALL #DESCRIPTION (1)G9General purpose input/output 6 (I/O/Z) (4)Enhanced PWM4 output A and HRPWM channel (not available on 2801, 2802) (O)External ePWM sync pulse input (I)External ePWM sync pulse output (O)G8General purpose input/output 7 (I/O/Z) (4)Enhanced PWM4 output B (not available on 2801, 2802) (O)SPI-D slave transmit enable (not available on 2801, 2802) (I/O)
Enhanced capture input/output 2 (I/O)

F9General purpose input/output 8 (I/O/Z) (4)Enhanced PWM5 output A and HRPWM channel (not available on 2801, 2802) (O)Enhanced CAN-B transmit (not available on 2801, 2802, F2806) (O)ADC start-of-conversion A (O)F8General purpose input/output 9 (I/O/Z) (4)Enhanced PWM5 output B (not available on 2801, 2802) (O)SCI-B transmit data (not available on 2801, 2802) (O)Enhanced capture input/output 3 (not available on 2801, 2802) (I/O)

E10

General purpose input/output 10 (I/O/Z) (4)Enhanced PWM6 output A and HRPWM channel (not available on 2801, 2802) (O)Enhanced CAN-B receive (not available on 2801, 2802, F2806) (I)
ADC start-of-conversion B (O)D9General purpose input/output 11 (I/O/Z) (4)Enhanced PWM6 output B (not available on 2801, 2802) (O)SCI-B receive data (not available on 2801, 2802) (I)
Enhanced CAP Input/Output 4 (not available on 2801, 2802) (I/O)

B2

General purpose input/output 12 (I/O/Z) (5)Trip Zone input 1 (I)Enhanced CAN-B transmit (not available on 2801, 2802, F2806) (O)SPI-B Slave in, Master out (I/O)

B4

General purpose input/output 13 (I/O/Z) (5)Trip zone input 2 (I)Enhanced CAN-B receive (not available on 2801, 2802, F2806) (I)
SPI-B slave out, master in (I/O)

D3

General purpose input/output 14 (I/O/Z) (5)Trip zone input 3 (I)SCI-B transmit (not available on 2801, 2802) (O)SPI-B clock input/output (I/O)

E1

General purpose input/output 15 (I/O/Z) (5)Trip zone input (I)SCI-B receive (not available on 2801, 2802) (I)
SPI-B slave transmit enable (I/O)

K10

General purpose input/output 16 (I/O/Z) (5)SPI-A slave in, master out (I/O)
Enhanced CAN-B transmit (not available on 2801, 2802, F2806) (O)
Trip zone input 5 (I)J10General purpose input/output 17 (I/O/Z) (5)SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (not available on 2801, 2802, F2806) (I)
Trip zone input 6(I)H8General purpose input/output 18 (I/O/Z) (5)SPI-A clock input/output (I/O)
SCI-B transmit (not available on 2801, 2802) (O)-G10General purpose input/output 19 (I/O/Z) (5)SPI-A slave transmit enable input/output (I/O)
SCI-B receive (not available on 2801, 2802) (I)-The pullups on GPIO12-GPIO34 are enabled upon reset.
Introduction

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TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 2-3. Signal Descriptions (continued)
PIN NO.
NAME

GPIO20
EQEP1ASPISIMOCCANTXBGPIO21
EQEP1BSPISOMICCANRXBGPIO22
EQEP1SSPICLKCSCITXDBGPIO23
EQEP1ISPISTECSCIRXDBGPIO24
ECAP1
EQEP2ASPISIMOBGPIO25
ECAP2
EQEP2BSPISOMIBGPIO26
ECAP3
EQEP2ISPICLKB
GPIO27
ECAP4
EQEP2SSPISTEB
GPIO28SCIRXDA
TZ5
GPIO29SCITXDA
TZ6
GPIO30CANRXA
GPIO31CANTXA
GPIO32SDAA
EPWMSYNCIADCSOCAO

PZ
PIN #

GGM/
ZGM
BALL #
F6

General purpose input/output 20 (I/O/Z) (5)Enhanced QEP1 input A (I)SPI-C slave in, master out (not available on 2801, 2802) (I/O)
Enhanced CAN-B transmit (not available on 2801, 2802, F2806) (O)E7

General purpose input/output 21 (I/O/Z) (5)Enhanced QEP1 input A (I)SPI-C master in, slave out (not available on 2801, 2802) (I/O)
Enhanced CAN-B receive (not available on 2801, 2802, F2806) (I)

D8General purpose input/output 22 (I/O/Z) (5)Enhanced QEP1 strobe (I/O)
SPI-C clock (not available on 2801, 2802) (I/O)
SCI-B transmit (not available on 2801, 2802) (O)C10General purpose input/output 23 (I/O/Z) (5)Enhanced QEP1 index (I/O)
SPI-C slave transmit enable (not available on 2801, 2802) (I/O)
SCI-B receive (I) (not available on 2801, 2802)

C7

General purpose input/output 24 (I/O/Z) (5)Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I) (not available on 2801, 2802)
SPI-B slave in, master out (I/O)

C5General purpose input/output 25 (I/O/Z) (5)Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I) (not available on 2801, 2802)
SPI-B master in, slave out (I/O)

A2

General purpose input/output 26 (I/O/Z) (5)Enhanced capture 3 (I/O) (not available on 2801, 2802)
Enhanced QEP2 index (I/O) (not available on 2801, 2802)
SPI-B clock (I/O)

C8General purpose input/output 27 (I/O/Z) (5)Enhanced capture 4 (I/O) (not available on 2801, 2802)
Enhanced QEP2 strobe (I/O) (not available on 2801, 2802)
SPI-B slave transmit enable (I/O)

D5

General purpose input/output 28. This pin has an 8-mA (typical) output buffer. (I/O/Z) (5)SCI receive data (I)Trip zone input 5 (I)C3General purpose input/output 29. This pin has an 8-mA (typical) output buffer. (I/O/Z) (5)SCI transmit data (O)Trip zone 6 input (I)D2General purpose input/output 30. This pin has an 8-mA (typical) output buffer. (I/O/Z) (5)Enhanced CAN-A receive data (I)-D1General purpose input/output 31. This pin has an 8-mA (typical) output buffer. (I/O/Z) (5)Enhanced CAN-A transmit data (O)-A1General purpose input/output 32 (I/O/Z) (5)I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)ADC start-of-conversion (O)

63

67

71

72

83

91

99

79

92

4

6

7

100

DESCRIPTION (1)Submit Documentation Feedback

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 2-3. Signal Descriptions (continued)
PIN NO.
NAME

GPIO33SCLAEPWMSYNCO
ADCSOCBO
GPIO34
(1)

PZ
PIN #

5

43

GGM/
ZGM
BALL #DESCRIPTION (1)C1General-Purpose Input/Output 33 (I/O/Z) (1)I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)ADC start-of-conversion (O)G7General-Purpose Input/Output 34 (I/O/Z) (1)-The pullups on GPIO12-GPIO34 are enabled upon reset.

NOTE
Some peripheral functions may not be available in TMS320F2801x devices. See
Table 2-2 for details.

26

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TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

3

Functional Overview
Memory Bus
TINT032-bit CPU TIMER 0

TINT1

7

32-bit CPU TIMER 1
TINT2

Real-Time JTAG
(TDI, TDO, TRST, TCK,
TMS, EMU0, EMU1)

32-bit CPU TIMER 2
INT14
PIE
(96 Interrupts)(A)INT[12:1]
M0 SARAM1 K 16
NMI, INT13
External Interrupt
Control

32
4

SCI-A/B

FIFO

SPI-A/B/C/D

FIFO

I2C-A

FIFO

16
2

GPIOs
(35)

GPIO MUX

4

L0 SARAM4 K 16(0-wait)
L1 SARAM(B)4 K 16(0-wait)eCAN-A/B (32 mbox)

8

H0 SARAM(C)8 K 16(0-wait)eQEP1/2

4

M1 SARAM1 K 16eCAP1/2/3/4(4 timers 32-bit)

12
ePWM1/2/3/4/5/6(12 PWM outputs,
6 trip zones,
6 timers 16-bit)

6

32

C28x CPU(100 MHz)SYSCLKOUT

System Control
RS

XCLKOUTXRSXCLKIN
X1
X2(Oscillator, PLL,
Peripheral Clocking,
Low Power Modes,
WatchDog)ROM
32K x 16 (C2802)
16K x 16 (C2801)

FLASH
128K x 16 (F2809)
64K x 16 (F2808)
32K x 16 (F2806)
32K x 16 (F2802)
16K x 16 (F2801)
16K x 16 (F2801x)

CLKIN

OTP(D)
1K 16
ADCSOCA/B
SOCA/B
Boot ROM
4 K 16(1-wait state)

12-Bit ADC
16 Channels

Protected by the code-security module.

Peripheral BusA.

43 of the possible 96 interrupts are used on the devices.

B.

Not available in F2802, F2801, C2802, and C2801.

C.

Not available in F2806, F2802, F2801, C2802, and C2801.

D.

The 1K x 16 OTP has been replaced with 1K x 16 ROM for C280x devices.

Figure 3-1. Functional Block Diagram
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3.1

Memory Maps
Block Start
Address

Data Space

Prog Space

0x00 0000

ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
M0 SARAM (1 K y 16)

0x00 0400

M1 SARAM (1 K y 16)

0x00 0800
Low 64K [0000 − FFFF](24x/240x equivalent data space)

Peripheral Frame 00x00 0D00

PIE Vector − RAM(256 x 16)(Enabled if ENPIE = 1)0x00 0E00
0x00 6000

0x00 7000

Peripheral Frame 1(protected)

Peripheral Frame 2(protected)

0x00 8000

L0 SARAM (0-wait)(4 k y 16, Secure Zone, Dual Mapped)

0x00 9000

0x00 A000

L1 SARAM (0-wait)(4 k y 16, Secure Zone, Dual Mapped)
H0 SARAM (0-wait)(8 k y 16, Dual Mapped)

0x00 C000

0x3D 7800

OTP(1 k y 16, Secure Zone)

0x3D 7C00

0x3D 8000

High 64K [3F0000 − 3FFFFF](24x/240x equivalent program space)

FLASH(128 k y 16, Secure Zone)

ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ

0x3F 7FF8128-bit Password

0x3F 8000
L0 SARAM (0-wait)(4 k y 16, Secure Zone, Dual Mapped)ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ

0x3F 9000

0x3F A000

L1 SARAM (0-wait)(4 k y 16, Secure Zone, Dual Mapped)
H0 SARAM (0-wait)(8 k y 16, Dual Mapped)

0x3F C000
0x3F F000

Boot ROM (4 k y 16)

0x3F FFC0

Vectors (32 y 32)(enabled if VMAP = 1, ENPIE = 0)

Reserved

A.

Memory blocks are not to scale.

B.

Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.

C.

Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.

D.

Certain memory ranges are EALLOW protected against spurious writes after configuration.

Figure 3-2. F2809 Memory Map

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Block Start
Address

Data Space

Prog Space

0x00 0000

ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
M0 SARAM (1 K y 16)

0x00 0400

M1 SARAM (1 K y 16)

0x00 0800
Low 64K [0000 − FFFF](24x/240x equivalent data space)

Peripheral Frame 00x00 0D00

PIE Vector − RAM(256 x 16)(Enabled if ENPIE = 1)0x00 0E00
0x00 6000

0x00 7000

Peripheral Frame 1(protected)

Peripheral Frame 2(protected)

0x00 8000

L0 SARAM (0-wait)(4 k y 16, Secure Zone, Dual Mapped)

0x00 9000

0x00 A000

L1 SARAM (0-wait)(4 k y 16, Secure Zone, Dual Mapped)
H0 SARAM (0-wait)(8 k y 16, Dual Mapped)

0x00 C000

0x3D 7800

OTP(1 k y 16, Secure Zone)

0x3D 7C00

0x3E 8000

High 64K [3F0000 − 3FFFFF](24x/240x equivalent program space)

FLASH(64 k y 16, Secure Zone)

ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ

0x3F 7FF8128-bit Password

0x3F 8000
L0 SARAM (0-wait)(4 k y 16, Secure Zone, Dual Mapped)ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ

0x3F 9000

0x3F A000

L1 SARAM (0-wait)(4 k y 16, Secure Zone, Dual Mapped)
H0 SARAM (0-wait)(8 k y 16, Dual Mapped)

0x3F C000
0x3F F000

Boot ROM (4 k y 16)

0x3F FFC0

Vectors (32 y 32)(enabled if VMAP = 1, ENPIE = 0)

Reserved

A.

Memory blocks are not to scale.

B.

Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.

C.

Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.

D.

Certain memory ranges are EALLOW protected against spurious writes after configuration.

Figure 3-3. F2808 Memory Map

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Block Start
Address

Data Space

Prog Space

0x00 0000

ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
M0 SARAM (1K y 16)

0x00 0400

M1 SARAM (1K y 16)

Low 64K [0000−FFFF](24x/240x equivalent data space)

0x00 0800

Peripheral Frame 00x00 0D00

PIE Vector − RAM(256 x 16)(Enabled if ENPIE = 1)0x00 0E00
0x00 6000

Peripheral Frame 1(protected)

0x00 7000

Peripheral Frame 2(protected)

0x00 8000

0x00 9000
0x00 A000

0x3D 7800

L0 SARAM (0-wait)(4k y 16, Secure Zone, Dual Mapped)

L1 SARAM (0-wait)(4k y 16, Secure Zone, Dual Mapped)

OTP(1 K y 16, Secure Zone)

0x3D 7C00

High 64K [3F0000 −3FFFF](24x/240x equivalent program space)

0x3F 0000

0x3F 7FF8FLASH(32 K y 16, Secure Zone)
128-bit Password

0x3F 8000

L0 SARAM (0-wait) (4k y 16,
Secure Zone, Dual Mapped)

0x3F 9000

L1 SARAM (0-wait) (4k y 16,
Secure Zone, Dual Mapped)

0x3F A000

0x3F F000

ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ

0x3F FFC0

Boot ROM (4 K y 16)

Vectors (32 y 32)(enabled if VMAP = 1, ENPIE = 0)

Reserved

A.

Memory blocks are not to scale.

B.

Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.

C.

Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.

D.

Certain memory ranges are EALLOW protected against spurious writes after configuration.

Figure 3-4. F2806 Memory Map

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007
Block Start
Address
0x00 0000

Data Space

Prog SpaceÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
M0 SARAM (1K y 16)

0x00 0400

Low 64K [0000−FFFF](24x/240x equivalent data space)

M1 SARAM (1K y 16)

0x00 0800

Peripheral Frame 00x00 0D00

0x00 0E00
0x00 6000

0x00 7000

0x00 8000
0x00 9000

0x3D 7800
0x3D 7C00

High 64K [3F0000 −3FFFF](24x/240x equivalent program space)

0x3F 0000
0x3F 7FF8PIE Vector − RAM(256 x 16)(Enabled if ENPIE = 1)

Peripheral Frame 1(protected)

Peripheral Frame 2(protected)

L0 SARAM (0-wait)(4K y 16, Secure Zone, Dual Mapped)

OTP (F2802 Only)(A)(1K y 16, Secure Zone)

FLASH (F2802) or ROM (C2802)(32K y 16, Secure Zone)
128-bit Password

0x3F 8000

L0 (0-wait)(4K y 16, Secure Zone, Dual Mapped)

0x3F 9000

0x3F F000

ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ

0x3F FFC0

Boot ROM (4 K y 16)

Vectors (32 y 32)(enabled if VMAP = 1, ENPIE = 0)

ReservedA.

The 1K x 16 OTP has been replaced with 1K x 16 ROM in C2802.

B.

Memory blocks are not to scale.

C.

Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.

D.

Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.

E.

Certain memory ranges are EALLOW protected against spurious writes after configuration.

F.

Some locations in ROM are reserved for TI. See Table 3-5 for more information.

Figure 3-5. F2802, C2802 Memory Map

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Block Start
Address
0x00 0000

Data Space

Prog SpaceÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
M0 SARAM (1K y 16)

0x00 0400

Low 64K [0000−FFFF](24x/240x equivalent data space)

M1 SARAM (1K y 16)

0x00 0800

Peripheral Frame 00x00 0D00

0x00 0E00
0x00 6000

0x00 7000
0x00 8000

0x00 9000

0x3D 7800
0x3D 7C00

High 64K [3F0000 −3FFFF](24x/240x equivalent program space)

0x3F 4000
0x3F 7FF8PIE Vector − RAM(256 x 16)(Enabled if ENPIE = 1)

Peripheral Frame 1(protected)

Peripheral Frame 2(protected)

L0 SARAM (0-wait)(4K y 16, Secure Zone, Dual Mapped)

OTP (F2801/F2801x Only)(A)(1K y 16, Secure Zone)

FLASH (F2801) or ROM (C2801)(16K y 16, Secure Zone)
128-bit Password

0x3F 8000

L0 (0-wait)(4K y 16, Secure Zone, Dual Mapped)

0x3F 9000

0x3F F000

ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ

0x3F FFC0

Boot ROM (4K y 16)

Vectors (32 y 32)(enabled if VMAP = 1, ENPIE = 0)

ReservedA.

The 1K x 16 OTP has been replaced with 1K x 16 ROM in C2801.

B.

Memory blocks are not to scale.

C.

Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.

D.

Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.

E.

Certain memory ranges are EALLOW protected against spurious writes after configuration.

F.

Some locations in ROM are reserved for TI. See Table 3-5 for more information.

Figure 3-6. F2801, F28015, F28016, C2801 Memory Map

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Table 3-1. Addresses of Flash Sectors in F2809
ADDRESS RANGEPROGRAM AND DATA SPACE

0x3D 8000 - 0x3D BFFF

Sector H (16K x 16)

0x3D C000 - 0x3D FFFF

Sector G (16K x 16)

0x3E 0000 - 0x3E 3FFF

Sector F (16K x 16)

0x3E 4000 - 0x3E 7FFF

Sector E (16K x 16)

0x3E 8000 - 0x3E BFFF

Sector D (16K x 16)

0x3E C000 - 0x3E FFFF

Sector C (16K x 16)

0x3F 0000 - 0x3F 3FFF

Sector B (16K x 16)

0x3F 4000 - 0x3F 7F7F

Sector A (16K x 16)

0x3F 7F80 - 0x3F 7FF5

Program to 0x0000 when using theCode Security Module

0x3F 7FF6 - 0x3F 7FF7

Boot-to-Flash Entry Point(program branch instruction here)

0x3F 7FF8 - 0x3F 7FFF

Security Password (128-Bit)(Do not program to all zeros)

Table 3-2. Addresses of Flash Sectors in F2808
ADDRESS RANGEPROGRAM AND DATA SPACE

0x3E 8000 - 0x3E BFFF

Sector D (16K x 16)

0x3E C000 - 0x3E FFFF

Sector C (16K x 16)

0x3F 0000 - 0x3F 3FFF

Sector B (16K x 16)

0x3F 4000 - 0x3F 7F7F

Sector A (16K x 16)

0x3F 7F80 - 0x3F 7FF5

Program to 0x0000 when using theCode Security Module

0x3F 7FF6 - 0x3F 7FF7

Boot-to-Flash Entry Point(program branch instruction here)

0x3F 7FF8 - 0x3F 7FFF

Security Password (128-Bit)(Do not program to all zeros)

Table 3-3. Addresses of Flash Sectors in F2806, F2802

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ADDRESS RANGEPROGRAM AND DATA SPACE

0x3F 0000 - 0x3F 1FFF

Sector D (8K x 16)

0x3F 2000 - 0x3F 3FFF

Sector C (8K x 16)

0x3F 4000 - 0x3F 5FFF

Sector B (8K x 16)

0x3F 6000 - 0x3F 7F7F

Sector A (8K x 16)

0x3F 7F80 - 0x3F 7FF5

Program to 0x0000 when using theCode Security Module

0x3F 7FF6 - 0x3F 7FF7

Boot-to-Flash Entry Point(program branch instruction here)

0x3F 7FF8 - 0x3F 7FFF

Security Password (128-Bit)(Do not program to all zeros)

Functional Overview

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TMS320F2809, TMS320F2808, TMS320F2806
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Table 3-4. Addresses of Flash Sectors in F2801, F28015, F28016
ADDRESS RANGEPROGRAM AND DATA SPACE

0x3F 4000 - 0x3F 4FFF

Sector D (4K x 16)

0x3F 5000 - 0x3F 5FFF

Sector C (4K x 16)

0x3F 6000 - 0x3F 6FFF

Sector B (4K x 16)

0x3F 7000 - 0x3F 7F7F

Sector A (4K x 16)

0x3F 7F80 - 0x3F 7FF5

Program to 0x0000 when using theCode Security Module

0x3F 7FF6 - 0x3F 7FF7

Boot-to-Flash Entry Point(program branch instruction here)

0x3F 7FF8 - 0x3F 7FFF

Security Password (128-Bit)(Do not program to all zeros)

NOTE• When the code-security passwords are programmed, all addresses between
0x3F7F80 and 0x3F7FF5 cannot be used as program code or data. These locations
must be programmed to 0x0000.
• If the code security feature is not used, addresses 0x3F7F80 through 0x3F7FEF may
be used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data andshould not contain program code. .
• On ROM devices, addresses 0x3F7FF0 – 0x3F7FF5 and 0x3D7BFC – 0x3D7BFF arereserved for TI, irrespective of whether code security has been used or not. User
application should not use these locations in any way.
Table 3-5 shows how to handle these memory locations.

Table 3-5. Impact of Using the Code Security Module
ADDRESS

FLASH
Code security enabled

0x3F7F80 - 0x3F7FEF
0x3F7FF0 - 0x3F7FF5
0x3D7BFC – 0x3D7BFF

Fill with 0x0000

ROM

Code security disabled

Code security enabled

Code security disabled

Application code and data

Fill with 0x0000

Application code and data

Reserved for data only

Application code and data

Reserved for TI. Do not use.

Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to bewrite/read peripheral block protected. The protected mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different
memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems
in certain peripheral applications where the user expected the write to occur first (as written). The C28x
CPU supports a block protection mode where a region of memory can be protected so as to make surethat operations occur as written (the penalty is extra cycles are added to align the operations). This modeis programmable and by default, it will protect the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 3-6.

34

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Table 3-6. Wait-states
AREA

WAIT-STATES

M0 and M1 SARAMs

0-waitCOMMENTS
Fixed

Peripheral Frame 00-waitFixed

Peripheral Frame 1

0-wait (writes)
2-wait (reads)

Fixed. The eCAN peripheral can extend a cycle as needed.
Back-to-back writes will introduce a 1-cycle delay.

Peripheral Frame 20-wait (writes)
2-wait (reads)

Fixed

L0 & L1 SARAMs

0-wait

OTP

Programmed via the Flash registers. 1-wait-state operation
Programmable,
is possible at a reduced CPU frequency. See Section 3.2.5
1-wait minimum
for more information.

Flash

Programmed via the Flash registers. 0-wait-state operation
Programmable, is possible at reduced CPU frequency. The CSM password
0-wait minimum locations are hardwired for 16 wait-states. See
Section 3.2.5 for more information.

H0 SARAM

0-waitFixed

Boot-ROM

1-waitFixed

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3.2

Brief Descriptions

3.2.1

C28x CPU
The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is avery efficient C/C++ engine, hence enabling users to develop not only their system control software in ahigh-level language, but also enables math algorithms to be developed using C/C++. The C28x is as
efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller
devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC
capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher
numerical resolution problems that would otherwise demand a more expensive floating-point processor
solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting ina device that is capable of servicing many asynchronous events with minimal latency. The C28x has an
8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x toexecute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead
hardware minimizes the latency for conditional discontinuities. Special store conditional operations further
improve performance.

3.2.2

Memory Bus (Harvard Bus Architecture)
As with many DSP type devices, multiple busses are used to move data between the memories andperipherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables theC28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals andmemories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:

Highest:Data Writes(Simultaneous data and program writes cannot occur on the memory bus.)

Program Writes(Simultaneous data and program writes cannot occur on the memory bus.)

Data Reads
Lowest:3.2.3

Program Reads(Simultaneous program reads and fetches cannot occur on the memory bus.)

Fetches(Simultaneous program reads and fetches cannot occur on the memory bus.)

Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the280x devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge
multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16
address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus
are supported on the 280x. One version only supports 16-bit accesses (called peripheral frame 2). The
other version supports both 16- and 32-bit accesses (called peripheral frame 1).

3.2.4

Real-Time JTAG and Analysis
The 280x implements the standard IEEE 1149.1 JTAG interface. Additionally, the 280x supports real-timemode of operation whereby the contents of memory, peripheral and register locations can be modified
while the processor is running and executing code and servicing interrupts. The user can also single step
through non-time critical code while enabling time-critical interrupts to be serviced without interference.
The 280x implements the real-time mode in hardware within the CPU. This is a unique feature to the
280x, no software monitor is required. Additionally, special analysis hardware is provided which allows theuser to set hardware breakpoint or data/address watch-points and generate various user-selectable break
events when a match occurs.

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3.2.5

Flash
The F2809 contains 128K x 16 of embedded flash memory, segregated into eight 16K X 16 sectors. The
F2808 contains 64K x 16 of embedded flash memory, segregated into four 16K X 16 sectors. The F2806
and F2802 have 32K X 16 of embedded flash, segregated into four 8K X 16 sectors. The F2801 device
contains 16K X 16 of embedded flash, segregated into four 4K X 16 sectors. All five devices also containa single 1K x 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BFF. The user can individuallyerase, program, and validate a flash sector while leaving other sectors untouched. However, it is notpossible to use one sector of the flash or the OTP to execute flash algorithms that erase/program othersectors. Special memory pipelining is provided to enable the flash module to achieve higher performance.
The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code orstore data information. Note that addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data variables andshould not contain program code.
NOTE
The F2809/F2808/F2806/F2802/F2801 Flash and OTP wait-states can be configured by
the application. This allows applications running at slower frequencies to configure theflash to use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in theFlash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode isapplication-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the TMS320x280x System Control and Interrupts Reference Guide (literature number
SPRU712).

3.2.6

ROM
The C2802 contains 32K x 16 of ROM, while the C2801 contains 16K x 16 of ROM.

3.2.7

M0, M1 SARAMs
All 280x devices contain these two blocks of single access memory, each 1K x 16 in size. The stack
pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks
on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 toexecute code or for data variables. The partitioning is performed within the linker. The C28x device
presents a unified memory map to the programmer. This makes for easier programming in high-level
languages.

3.2.8

L0, L1, H0 SARAMs
The F2809 and F2808 each contain an additional 16K x 16 of single-access RAM, divided into 3 blocks(L0-4K, L1-4K, H0-8K). The F2806 contains an additional 8K x 16 of single-access RAM, divided into
2 blocks (L0-4K, L1-4K). The F2802, F2801, C2802, and C2801 each contain an additional 4K x 16 of
single-access RAM (L0-4K). Each block can be independently accessed to minimize CPU pipeline stalls.
Each block is mapped to both program and data space.

3.2.9

Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in theinternal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use
in math related algorithms.

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Table 3-7. Boot Mode Selection
MODE

DESCRIPTIONGPIO18SPICLKASCITXDBGPIO29SCITXDAGPIO34

Boot to Flash/ROM

Jump to Flash/ROM address 0x3F 7FF6
You must have programmed a branch instruction here prior
to reset to redirect code execution as desired.

1

1

1

SCI-A Boot

Load a data stream from SCI-A

1

1

0

SPI-A Boot

Load from an external serial SPI EEPROM on SPI-A

1

0

1

I2C Boot

Load data from an external EEPROM at address 0x50 on
the I2C bus

1

0

0

eCAN-A Boot

Call CAN_Boot to load from eCAN-A mailbox 1.

0

1

1

Boot to M0 SARAM

Jump to M0 SARAM address 0x00 0000.

0

1

0

Boot to OTP

Jump to OTP address 0x3D 7800

0

0

1

Parallel I/O Boot

Load data from GPIO0 - GPIO15

0

0

0

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3.2.10 Security
The 280x devices support high levels of security to protect the user firmware from being reverse
engineered. The security features a 128-bit password (hardcoded for 16 wait-states), which the user
programs into the flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1
SARAM blocks. The security feature prevents unauthorized users from examining the memory contents
via the JTAG port, executing code from external memory or trying to boot-load some undesirable softwarethat would export the secure memory contents. To enable access to the secure blocks, the user must
write the correct 128-bit KEY value, which matches the value stored in the password locations within theFlash.
NOTE
The 128-bit password (at 0x3F 7FF8 – 0x3F 7FFF) must not be programmed to zeros.
Doing so would permanently lock the device.

disclaimer
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WASDESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATEDMEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXASINSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND
CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE
WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BECOMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATEDMEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER,
EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR
REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR
A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN
ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOTTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDEDDAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER
ECONOMIC LOSS.

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3.2.11 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the 280x, 43 of the possible 96 interrupts areused by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12
CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.

3.2.12 External Interrupts (XINT1, XINT2, XNMI)The 280x supports three masked external interrupts (XINT1, XINT2, XNMI). XNMI can be connected to
the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, orboth negative and positive edge triggering and can also be enabled/disabled (including the XNMI). The
masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a validinterrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the281x devices, there are no dedicated pins for the external interrupts. Rather, any Port A GPIO pin can be
configured to trigger any external interrupt.

3.2.13 Oscillator and PLL
The 280x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit.
A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly
in software, enabling the user to scale back on operating frequency if lower power operation is desired.
Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.

3.2.14 Watchdog
The 280x devices contain a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog
can be disabled if necessary.

3.2.15 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption
when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN)
and the ADC blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be
decoupled from increasing CPU clock speeds.

3.2.16 Low-Power Modes
The 280x devices are full static CMOS devices. Three low-power modes are provided:

40

IDLE:

Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that need to function during IDLE are left operating. An enabled interrupt
from an active peripheral or the watchdog timer will wake the processor from IDLE mode.

STANDBY:

Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
An external interrupt event will wake the processor and the peripherals. Execution begins
on the next valid cycle after detection of the interrupt event

HALT:

Turns off the internal oscillator. This mode basically shuts down the device and places it in
the lowest possible power consumption mode. A reset or external signal can wake thedevice from this mode.

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3.2.17 Peripheral Frames 0, 1, 2 (PFn)
The 280x segregate peripherals into three sections. The mapping of peripherals is as follows:
PF0:

PF1:

PF2:

PIE:

PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash:

Flash Control, Programming, Erase, Verify Registers

Timers:CPU-Timers 0, 1, 2 Registers

CSM:

Code Security Module KEY Registers

ADC:

ADC Result Registers (dual-mapped)

eCAN:

eCAN Mailbox and Control Registers

GPIO:

GPIO MUX Configuration and Control Registers

ePWM:

Enhanced Pulse Width Modulator Module and Registers

eCAP:

Enhanced Capture Module and Registers

eQEP:

Enhanced Quadrature Encoder Pulse Module and Registers

SYS:

System Control Registers

SCI:

Serial Communications Interface (SCI) Control and RX/TX Registers

SPI:

Serial Port Interface (SPI) Control and RX/TX Registers

ADC:

ADC Status, Control, and Result Register

I2C:

Inter-Integrated Circuit Module and Registers

3.2.18 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pinsare configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.

3.2.19 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clockprescaling. The timers have a 32-bit count down register, which generates an interrupt when the counterreaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 isreserved for the DSP/BIOS Real-Time OS, and is connected to INT14 of the CPU. If DSP/BIOS is not
being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can beconnected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.

3.2.20 Control Peripherals
The 280x devices support the following peripherals which are used for embedded control andcommunication:ePWM:

The enhanced PWM peripheral supports independent/complementary PWM generation,
adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip
mechanism. Some of the PWM pins support HRPWM features.

eCAP:

The enhanced capture peripheral uses a 32-bit time base and registers up to four
programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.

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eQEP:

The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed
measurement using capture unit and high-speed measurement using a 32-bit unit timer.
This peripheral has a watchdog timer to detect motor stall and input error detection logic
to identify simultaneous edge transition in QEP signals.

ADC:

The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling.

3.2.21 Serial Port Peripherals
The 280x devices support the following serial communication peripherals:

3.3

eCAN:

This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, timestamping of messages, and is CAN 2.0B-compliant.

SPI:

The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream ofprogrammed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multi-device communications are supported by the master/slave
operation of the SPI. On the 280x, the SPI contains a 16-level receive and transmit FIFO
for reducing interrupt servicing overhead.

SCI:

The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the 280x, the SCI contains a 16-level receive and transmit FIFO for
reducing interrupt servicing overhead.

I2C:

The inter-integrated circuit (I2C) module provides an interface between a DSP and otherdevices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version
2.1 and connected by way of an I2C-bus. External components attached to this 2-wireserial bus can transmit/receive up to 8-bit data to/from the DSP through the I2C module.
On the 280x, the I2C contains a 16-level receive and transmit FIFO for reducing interrupt
servicing overhead.

Register Map
The 280x devices contain three peripheral register spaces. The spaces are categorized as follows:

42

Peripheral
Frame 0:

These are peripherals that are mapped directly to the CPU memory bus.
See Table 3-8

Peripheral
Frame 1

These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 3-9

Peripheral
Frame 2:

These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 3-10

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Table 3-8. Peripheral Frame 0 Registers (1) (2)NAME

ACCESS TYPE (3)ADDRESS RANGESIZE (x16)

Device Emulation Registers

0x0880 - 0x09FF

384

EALLOW protected

FLASH Registers (4)0x0A80 - 0x0ADF

96

EALLOW protected
CSM Protected

Code Security Module Registers

0x0AE0 - 0x0AEF

16

EALLOW protected

ADC Result Registers (dual-mapped)

0x0B00 - 0x0B0F

16

Not EALLOW protected

CPU-TIMER0/1/2 Registers

0x0C00 - 0x0C3F

64

Not EALLOW protected

PIE Registers

0x0CE0 - 0x0CFF

32

Not EALLOW protected

PIE Vector Table

0x0D00 - 0x0DFF

256

EALLOW protected

(1)
(2)
(3)
(4)

Registers in Frame 0 support 16-bit and 32-bit accesses.
Missing segments of memory space are reserved and should not be used in applications.
If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
The Flash Registers are also protected by the Code Security Module (CSM).

Table 3-9. Peripheral Frame 1 Registers (1) (2)NAME

ADDRESS RANGESIZE (x16)

ACCESS TYPE

eCANA Registers

0x6000 - 0x60FF

256

Some eCAN control registers (and selected
bits in other eCAN control registers) are
EALLOW-protected.

eCANA Mailbox RAM

0x6100 - 0x61FF

256

Not EALLOW-protected

eCANB Registers

0x6200 - 0x62FF

256

Some eCAN control registers (and selected
bits in other eCAN control registers) are
EALLOW-protected.

eCANB Mailbox RAM

0x6300 - 0x63FF

256

Not EALLOW-protected

ePWM1 Registers

0x6800 - 0x683F

64

ePWM2 Registers

0x6840 - 0x687F

64

ePWM3 Registers

0x6880 - 0x68BF

64

ePWM4 Registers

0x68C0 - 0x68FF

64

ePWM5 Registers

0x6900 - 0x693F

64

ePWM6 Registers

0x6940 - 0x697F

64

eCAP1 Registers

0x6A00 - 0x6A1F

32

eCAP2 Registers

0x6A20 - 0x6A3F

32

eCAP3 Registers

0x6A40 - 0x6A5F

32

eCAP4 Registers

0x6A60 - 0x6A7F

32

eQEP1 Registers

0x6B00 - 0x6B3F

64

eQEP2 Registers

0x6B40 - 0x6B7F

64

GPIO Control Registers

0x6F80 - 0x6FBF

128

EALLOW protected

GPIO Data Registers

0x6FC0 - 0x6FDF

32

Not EALLOW protected

GPIO Interrupt and LPM Select Registers

0x6FE0 - 0x6FFF

32

EALLOW protected

(1)
(2)

Some ePWM registers are EALLOW
protected.
See Table 4-2

Not EALLOW protected

The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
Missing segments of memory space are reserved and should not be used in applications.

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Table 3-10. Peripheral Frame 2 Registers (1) (2)
ADDRESS RANGESIZE (x16)System Control Registers

NAME

0x7010 - 0x702F

32

SPI-A Registers

0x7040 - 0x704F

16

SCI-A Registers

0x7050 - 0x705F

16

External Interrupt Registers

0x7070 - 0x707F

16

ADC Registers

0x7100 - 0x711F

32

SPI-B Registers

0x7740 - 0x774F

16

SCI-B Registers

0x7750 - 0x775F

16

SPI-C Registers

0x7760 - 0x776F

16

SPI-D Registers

0x7780 - 0x778F

16

I2C Registers

0x7900 - 0x792F

48

(1)
(2)

ACCESS TYPE
EALLOW Protected

Not EALLOW Protected

Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
Missing segments of memory space are reserved and should not be used in applications.

3.4

Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some criticaldevice signals. The registers are defined in Table 3-11.
Table 3-11. Device Emulation Registers
ADDRESSRANGE

SIZE (x16)

DEVICECNF

0x08800x0881

2

Device Configuration Register

PARTID

0x0882

1

Part ID Register

0x002C (1) - F2801
0x0024 - F2802
0x0034 - F2806
0x003C - F2808
0x00FE - F2809
0x0014 - F28016
0x001C - F28015
0xFF2C - C2801
0xFF24 - C2802

REVID

0x0883

1

Revision ID Register

0x0000 - Silicon Rev. 0 - TMX
0x0001 - Silicon Rev. A - TMX
0x0002 - Silicon Rev. B - TMS
0x0003 - Silicon Rev. C - TMS

Revision ID Register

0x0000 - Silicon rev. 0 - TMS (F2809 only)

PROTSTART

0x0884

1

Block Protection Start Address Register

PROTRANGE

0x0885

1

Block Protection Range Address Register

NAME

(1)

3.5

DESCRIPTION

The first byte (00) denotes flash devices. FF denotes ROM devices. Other values are reserved for future devices.

Interrupts
Figure 3-7 shows how the various interrupt sources are multiplexed within the 280x devices.
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8interrupts per group equals 96 possible interrupts. On the 280x, 43 of these are used by peripherals asshown in Table 3-12.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address
pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,
TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.

44

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When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector
from INT1.1, TRAP #2 fetches the vector from INT2.1 and so forth.
Peripherals(SPI, SCI, I2C, eCAN, ePWM, eCAP, eQEP, ADC)WDINT

WAKEINT

XINT1

XINT1

Interrupt Control

Low Power ModesMUX

LPMINT

Watchdog

96 Interrupts

XINT1CTR(15:0)
GPIOXINT1SEL(4:0)
ADC
XINT2

C28

XINT2SOCMUX

INT1 to
INT12

PIE

XINT1CR(15:0)

XINT2

Interrupt Control
XINT2CR(15:0)

CPU

XINT2CTR(15:0)
GPIOXINT2SEL(4:0)

TINT0
TINT2
INT14

CPU TIMER 0
CPU TIMER 2(Reserved for DSP/BIOS)

TINT1
INT13

MUX

CPU TIMER 1

int13_select
nmi_select

GPIO0.int

MUX

NMI

GPIO

MUX

XNMI_XINT13
Interrupt Control
XNMICR(15:0)

MUX
GPIO31.int

1
XNMICTR(15:0)
GPIOXNMISEL(4:0)

Figure 3-7. External and PIE Interrupt Sources

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IFR(12:1)

IER(12:1)

INTM

INT1
INT2
1
CPU

MUX

0

INT11
INT12
(Flag)

INTx

GlobalEnable(Enable)INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8MUXPIEACKx(Enable/Flag)(Enable)(Flag)

PIEIERx(8:1)

PIEIFRx(8:1)

From
Peripherals orExternal
Interrupts

Figure 3-8. Multiplexing of Interrupts Using the PIE Block
Table 3-12. PIE Peripheral Interrupts (1)CPU
INTERRUPTS

(1)

46

PIE INTERRUPTS
INTx.8

INTx.7

INTx.6

INTx.5

INTx.4

INTx.3

INTx.2

INTx.1

INT1

WAKEINT(LPM/WD)

TINT0(TIMER 0)

ADCINT
(ADC)

XINT2

XINT1

reserved

SEQ2INT(ADC)

SEQ1INT
(ADC)

INT2

reserved

reserved

EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT(ePWM6)(ePWM5)(ePWM4)(ePWM3)(ePWM2)(ePWM1)

INT3

reserved

reserved

EPWM6_INT(ePWM6)EPWM5_INT(ePWM5)EPWM4_INT(ePWM4)EPWM3_INT(ePWM3)EPWM2_INT(ePWM2)EPWM1_INT(ePWM1)

INT4

reserved

reserved

reserved

reserved

ECAP4_INT(eCAP4)

ECAP3_INT(eCAP3)

ECAP2_INT(eCAP2)

ECAP1_INT(eCAP1)

INT5

reserved

reserved

reserved

reserved

reserved

reserved

EQEP2_INT(eQEP2)

EQEP1_INT(eQEP1)INT6SPITXINTD(SPI-D)SPIRXINTD(SPI-D)SPITXINTC(SPI-C)SPIRXINTC(SPI-C)SPITXINTB(SPI-B)SPIRXINTB(SPI-B)SPITXINTA(SPI-A)SPIRXINTA(SPI-A)

INT7

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved
I2CINT1A(I2C-A)

INT8

reserved

reserved

reserved

reserved

reserved

reserved

I2CINT2A(I2C-A)

INT9

ECAN1_INTB(CAN-B)

ECAN0_INTB(CAN-B)ECAN1_INTA(CAN-A)

ECAN0_INTA(CAN-A)SCITXINTB(SCI-B)SCIRXINTB(SCI-B)SCITXINTA(SCI-A)SCIRXINTA(SCI-A)

INT10

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

INT11

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

INT12

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 12).

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Table 3-13. PIE Configuration and Control Registers
NAME

SIZE (X16)

PIECTRL

0x0CE01

PIE, Control Register

PIEACK

0x0CE1

1

PIE, Acknowledge Register

PIEIER1

0x0CE2

1

PIE, INT1 Group Enable Register

PIEIFR1

0x0CE3

1

PIE, INT1 Group Flag Register

PIEIER2

0x0CE4

1

PIE, INT2 Group Enable Register

PIEIFR2

0x0CE5

1

PIE, INT2 Group Flag Register

PIEIER3

0x0CE6

1

PIE, INT3 Group Enable Register

PIEIFR3

0x0CE7

1

PIE, INT3 Group Flag Register

PIEIER4

0x0CE8

1

PIE, INT4 Group Enable Register

PIEIFR4

0x0CE91

PIE, INT4 Group Flag Register

PIEIER5

0x0CEA

1

PIE, INT5 Group Enable Register

PIEIFR5

0x0CEB

1

PIE, INT5 Group Flag Register

PIEIER6

0x0CEC

1

PIE, INT6 Group Enable Register

PIEIFR6

0x0CED

1

PIE, INT6 Group Flag Register

PIEIER7

0x0CEE

1

PIE, INT7 Group Enable Register

PIEIFR7

0x0CEF

1

PIE, INT7 Group Flag Register

PIEIER8

0x0CF01

PIE, INT8 Group Enable Register

PIEIFR8

0x0CF1

1

PIE, INT8 Group Flag Register

PIEIER90x0CF2

1

PIE, INT9 Group Enable Register

PIEIFR90x0CF3

1

PIE, INT9 Group Flag Register

PIEIER10

0x0CF4

1

PIE, INT10 Group Enable Register

PIEIFR10

0x0CF5

1

PIE, INT10 Group Flag Register

PIEIER11

0x0CF6

1

PIE, INT11 Group Enable Register

PIEIFR11

0x0CF7

1

PIE, INT11 Group Flag Register

PIEIER12

0x0CF8

1

PIE, INT12 Group Enable Register

PIEIFR12

0x0CF91

PIE, INT12 Group Flag Register

Reserved

0x0CFA
0x0CFF

6

Reserved

(1)

3.5.1

DESCRIPTION (1)ADDRESSThe PIE configuration and control registers are not protected by EALLOW mode. The PIE vector tableis protected.

External Interrupts
Table 3-14. External Interrupt Registers
NAME

ADDRESSSIZE (x16)0x70701

XINT1 control register

XINT2CR

0x7071

1

XINT2 control register

reserved

0x7072 - 0x7076

5

XNMICR

0x7077

1

XNMI control register

XINT1CTR

0x7078

1

XINT1 counter register

XINT2CTR

0x70791

XINT2 counter register

reserved

0x707A - 0x707E

5XNMICTR0x707F1

XINT1CRDESCRIPTIONXNMI counter register

Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive andnegative edge. For more information, see the TMS320x280x System Control and Interrupts Reference
Guide (literature number SPRU712).

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3.6

System Control
This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and thelow power modes. Figure 3-9 shows the various clock and reset domains in the 280x devices that will be
discussed.
Reset
XRS

Watchdog
Block

SYSCLKOUT(A)Peripheral Reset

X1

CLKIN(A)
28x
CPU

PLL

Peripheral
Registers

Peripheral Bus

SystemControl
Registers

X2

Power
Modes
ControlCPU
TimersXCLKIN

Clock Enables

Peripheral
Registers

ePWM 1/2/3/4/5/6
eCAP 1/2/3/4 eQEP 1/2

I/O

Peripheral
Registers

eCAN-A/B
I2C-A

I/O

Low-Speed Prescaler
Peripheral
Registers

OSC

GPIO
MUX

GPIOs

LSPCLK

Low-Speed Peripherals
SCI-A/B, SPI-A/B/C/D

I/O

High-Speed Prescaler
HSPCLK
ADC
RegistersA.

12-Bit ADC

16 ADC inputs

CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT).

Figure 3-9. Clock and Reset Domains

48

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The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-15.
Table 3-15. PLL, Clocking, Watchdog, and Low-Power Mode Registers (1)NAME

ADDRESSSIZE (x16)0x7010

1

XCLKOUT Pin Control, X1 and XCLKIN Status Register

PLLSTS

0x7011

1

PLL Status Register

reserved

0x7012 - 0x7019

8

HISPCP

0x701A

1

High-Speed Peripheral Clock Prescaler Register (for HSPCLK)LOSPCP

0x701B

1

Low-Speed Peripheral Clock Prescaler Register (for LSPCLK)PCLKCR00x701C

1

Peripheral Clock Control Register 0

PCLKCR10x701D

1

Peripheral Clock Control Register 1

LPMCR00x701E1

Low Power Mode Control Register 0

reserved

0x701F - 0x7020

1

PLLCR

0x7021

1

PLL Control Register

SCSR

0x7022

1

System Control and Status Register

WDCNTR

0x7023

1

Watchdog Counter Register

reserved

0x70241

WDKEY

0x70251reserved

0x7026 - 0x7028

3

WDCR

0x70291

reserved

0x702A - 0x702F

6

XCLK

(1)

DESCRIPTION

Watchdog Reset Key Register
Watchdog Control RegisterAll of the registers in this table are EALLOW protected.

3.6.1

OSC and PLL Block
Figure 3-10 shows the OSC and PLL block on the 280x.
XCLKIN
(3.3-V clock input)

OSCCLKOSCCLK

0xor
PLLSTS[OSCOFF]
PLL

OSCCLK or
VCOCLK

CLKIN

VCOCLKnn≠0/2

PLLSTS[PLLOFF]
PLLSTS[CLKINDIV]

X1
On chip
oscillator

4-bit PLL Select (PLLCR)

X2

Figure 3-10. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the 280x devices using the X1
and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of thefollowing configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed VDDIO.
2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left
unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed VDD.
The three possible input-clock configurations are shown in Figure 3-11 through Figure 3-13

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XCLKIN

X1

X2

NC

External Clock Signal(Toggling 0 −VDDIO)

Figure 3-11. Using a 3.3-V External Oscillator

X1

X2

External Clock Signal(Toggling 0 −VDD)

NC

XCLKIN

Figure 3-12. Using a 1.8-V External Oscillator

XCLKIN

X1

X2

CL2

CL1
CrystalFigure 3-13. Using the Internal Oscillator
3.6.1.1 External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below:• Fundamental mode, parallel resonant• CL (load capacitance) = 12 pF• CL1 = CL2 = 24 pF• Cshunt = 6 pF
• ESR range = 30 to 60 Ω
TI recommends that customers have the resonator/crystal vendor characterize the operation of theirdevice with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tankcircuit. The vendor can also advise the customer regarding the proper tank component values that willproduce proper start up and stability over the entire operating range.
3.6.1.2 PLL-Based Clock Module
The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessary
clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio
control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before
writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, whichtakes 131072 OSCCLK cycles.

50

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Table 3-16. PLLCR Register Bit Definitions
PLLCR[DIV] (1)

(1)
(2)

SYSCLKOUT(CLKIN) (2)0000 (PLL bypass)

OSCCLK/n

0001(OSCCLK*1)/n0010(OSCCLK*2)/n0011(OSCCLK*3)/n0100(OSCCLK*4)/n

0101(OSCCLK*5)/n0110(OSCCLK*6)/n0111(OSCCLK*7)/n

1000(OSCCLK*8)/n

1001(OSCCLK*9)/n1010(OSCCLK*10)/n1011-1111

reserved

This register is EALLOW protected.
CLKIN is the input clock to the CPU. SYSCLKOUT is the output
clock from the CPU. The frequency of SYSCLKOUT is the same as
CLKIN. If CLKINDIV = 0, n = 2; if CLKINDIV = 1, n = 1.

NOTE
PLLSTS[CLKINDIV] enables or bypasses the divide-by-two block before the clock is fed
to the core. This bit must be 0 before writing to the PLLCR and must only be set after
PLLSTS[PLLLOCKS] = 1.

The PLL-based clock module provides two modes of operation:• Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time baseto the device.
• External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 3-17. Possible PLL Configuration Modes
REMARKSPLLSTS[CLKINDIV]SYSCLKOUT(CLKIN)0OSCCLK/2

PLL Off

Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL blockis disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.

1

OSCCLK

PLL Bypass is the default PLL configuration upon power-up or after an external
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.

0

OSCCLK/2

PLL Bypass

1

OSCCLKPLL Enable

Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.

0

OSCCLK*n/2

PLL MODE

3.6.1.3 Loss of Input ClockIn PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still
issue a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typicalfrequency of 1-5 MHz. Limp mode is not specified to work from power-up, only after input clocks havebeen present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to
the CPU if the input clock is removed or absent.
Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog

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reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops
decrementing (i.e., the watchdog counter does not change with the limp-mode clock). In addition to this,the device will be reset and the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions could
be used by the application firmware to detect the input clock failure and initiate necessary shut-down
procedure for the system.
NOTE
Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the DSP will be held in reset, should the input clocks
ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSP,
should the capacitor ever get fully charged. An I/O pin may be used to discharge thecapacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would
also help in detecting failure of the flash memory and the VDD3VFL rail.

3.6.2

Watchdog Block
The watchdog block on the 280x is similar to the one used on the 240x and 281x devices. The watchdog
module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up
counter has reached its maximum value. To prevent this, the user disables the counter or the softwaremust periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset thewatchdog counter. Figure 3-14 shows the various functional blocks within the watchdog module.
WDCR (WDPS(2:0))

WDCR (WDDIS)
WDCNTR(7:0)

OSCCLK

Watchdog
Prescaler

/512

WDCLK

8-Bit
Watchdog
Counter
CLR
Clear Counter

Internal
Pullup
WDKEY(7:0)
Watchdog
55 + AAKey Detector

WDRST
Generate
Output Pulse
WDINT(512 OSCCLKs)

Good Key

XRS
Core-reset
WDCR (WDCHK(2:0))

WDRST(A)

A.

1

0

Bad
WDCHK
Key

SCSR (WDENINT)

1The WDRST signal is driven low for 512 OSCCLK cycles.

Figure 3-14. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.

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In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the
LPM block so that it can wake the device from STANDBY (if enabled). See Section Section 3.7,
Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence sois the WATCHDOG.

3.7

Low-Power Modes Block
The low-power modes on the 280x are similar to the 240x devices. Table 3-18 summarizes the various
modes.
Table 3-18. Low-Power Modes

MODE

LPMCR0(1:0)

OSCCLK

CLKIN

SYSCLKOUT

EXIT (1)

IDLE

00

On

On

On (2)XRS, Watchdog interrupt, any enabledinterrupt, XNMISTANDBY

01

On(watchdog still running)

Off

Off

XRS, Watchdog interrupt, GPIO Port A
signal, debugger (3), XNMI

HALT

1X

Off
(oscillator and PLL turned off,
watchdog not functional)

Off

Off

XRS, GPIO Port A signal, XNMI,
debugger (3)

(1)
(2)
(3)

The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, willexit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the
IDLE mode will not be exited and the device will go back into the indicated low power mode.
The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.
On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.

The various low-power modes operate as follows:
IDLE Mode:

This mode is exited by any enabled interrupt or an XNMI that is recognized by
the processor. The LPM block performs no tasks during this mode as long as the
LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode:

Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY
mode. The user must select which signal(s) will wake the device in the
GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK
before waking the device. The number of OSCCLKs is specified in the LPMCR0register.

HALT Mode:

Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the device
from HALT mode. The user selects the signal in the GPIOLPMSEL register.

NOTE
The low-power modes do not affect the state of the output pins (PWM pins included).
They will be in whatever state the code left them in when the IDLE instruction was
executed. See the TMS320x280x System Control and Interrupts Reference Guide(literature number SPRU712) for more details.

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4

Peripherals
The integrated peripherals of the 280x are described in the following subsections:• Three 32-bit CPU-Timers• Up to six enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6)• Up to four enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4)• Up to two enhanced QEP modules (eQEP1, eQEP2)• Enhanced analog-to-digital converter (ADC) module• Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)• Up to two serial communications interface modules (SCI-A, SCI-B)• Up to four serial peripheral interface (SPI) modules (SPI-A, SPI-B, SPI-C, SPI-D)• Inter-integrated circuit module (I2C)• Digital I/O and shared pin functions

4.1

32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on the 280x devices (CPU-TIMER0/1/2).
CPU-Timer 0 and CPU-Timer 1 can be used in user applications. Timer 2 is reserved for DSP/BIOS™.
These timers are different from the timers that are present in the ePWM modules.
NOTE
NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in theapplication.

Reset
Timer Reload

16-Bit Timer Divide-Down
TDDRH:TDDRSYSCLKOUT
TCR.4(Timer Start Status)

32-Bit Timer Period
PRDH:PRD

16-Bit Prescale Counter
PSCH:PSC
Borrow

32-Bit Counter
TIMH:TIM
Borrow

TINT

Figure 4-1. CPU-Timers
In the 280x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in
Figure 4-2.

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INT1
to
INT12

PIE

TINT0

CPU-TIMER 0

C28x
TINT1
CPU-TIMER 1

INT13
XINT13

CPU-TIMER 2(Reserved for
DSP/BIOS)

TINT2

INT14

A.

The timer registers are connected to the memory bus of the C28x processor.

B.

The timing of the timers is synchronized to SYSCLKOUT of the processor clock.

Figure 4-2. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with thevalue in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of theC28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The
registers listed in Table 4-1 are used to configure the timers. For more information, see the TMS320x280x
System Control and Interrupts Reference Guide (literature number SPRU712).
Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers
ADDRESSSIZE (x16)

TIMER0TIM

NAME

0x0C001

CPU-Timer 0, Counter Register

TIMER0TIMH

0x0C01

1

CPU-Timer 0, Counter Register HighTIMER0PRD

0x0C02

1

CPU-Timer 0, Period Register

TIMER0PRDH

0x0C03

1

CPU-Timer 0, Period Register HighTIMER0TCR

0x0C04

1

CPU-Timer 0, Control Register

reserved

0x0C05

1

TIMER0TPR

0x0C06

1

CPU-Timer 0, Prescale Register

TIMER0TPRH

0x0C07

1

CPU-Timer 0, Prescale Register HighTIMER1TIM

0x0C081

CPU-Timer 1, Counter Register

TIMER1TIMH

0x0C091

CPU-Timer 1, Counter Register HighTIMER1PRD

0x0C0A

1

CPU-Timer 1, Period Register

TIMER1PRDH

0x0C0B

1

CPU-Timer 1, Period Register HighTIMER1TCR

0x0C0C

1

CPU-Timer 1, Control Register

reserved

0x0C0D

1

TIMER1TPR

0x0C0E

1

CPU-Timer 1, Prescale Register

TIMER1TPRH

0x0C0F

1

CPU-Timer 1, Prescale Register HighTIMER2TIM

0x0C101

CPU-Timer 2, Counter Register

TIMER2TIMH

0x0C11

1

CPU-Timer 2, Counter Register HighTIMER2PRD

0x0C12

1

CPU-Timer 2, Period Register

TIMER2PRDH

0x0C13

1

CPU-Timer 2, Period Register HighTIMER2TCR

0x0C14

1

CPU-Timer 2, Control Register

reserved

0x0C15

1

TIMER2TPR

0x0C16

1

CPU-Timer 2, Prescale Register

TIMER2TPRH

0x0C17

1

CPU-Timer 2, Prescale Register High

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Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers (continued)
NAME
reserved

4.2

ADDRESSSIZE (x16)0x0C18
0x0C3F40

DESCRIPTION

Enhanced PWM Modules (ePWM1/2/3/4/5/6)
The 280x device contains up to six enhanced PWM Modules (ePWM). Figure 4-3 shows a block diagramof multiple ePWM modules. Figure 4-4 shows the signal interconnections with the ePWM. See the
TMS320x280x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (literature number
SPRU791) for more details.
EPWM1SYNCIEPWM1INT

EPWM1SYNCIEPWM1A

EPWM1SOCePWM1 module

EPWM1BTZ1 to TZ6

to eCAP1
module(sync in)

EPWM1SYNCO

EPWM1SYNCO.

EPWM2SYNCIEPWM2INT
EPWM2SOCPIE

EPWM2AePWM2 module

EPWM2BGPIO
MUX

TZ1 to TZ6

EPWM2SYNCO

EPWMxSYNCIEPWMxINT
EPWMxSOC

EPWMxAePWMx module

EPWMxB

EPWMxSYNCO

TZ1 to TZ6ADCSOCx0

ADC

Peripheral Bus

Figure 4-3. Multiple PWM Modules in a 280x System
Table 4-2 shows the complete ePWM register set per module.

56

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Table 4-2. ePWM Control and Status Registers
EPWM1

EPWM2

EPWM3

EPWM4

EPWM5

EPWM6

SIZE (x16) /#SHADOW

TBCTL

0x68000x68400x68800x68C00x69000x69401/0Time Base Control Register

TBSTS

0x68010x68410x6881

0x68C10x69010x6941

1/0Time Base Status Register

TBPHSHR

0x68020x68420x68820x68C2

N/A

N/A

1/0

Time Base Phase HRPWM Register

TBPHS

0x68030x68430x68830x68C30x69030x6943

1/0Time Base Phase Register

TBCTR

0x68040x68440x68840x68C40x69040x6944

1/0Time Base Counter Register

TBPRD

0x68050x68450x68850x68C50x69050x6945

1/1Time Base Period Register Set

CMPCTL0x68070x68470x68870x68C70x69070x6947

1/0Counter Compare Control Register

CMPAHR

0x68080x68480x68880x68C8

N/A

N/A

1/1

Time Base Compare A HRPWM Register

CMPA

0x68090x68490x68890x68C90x69090x6949

1/1Counter Compare A Register Set

CMPB

0x680A0x684A

0x688A

0x68CA

0x690A

0x694A

1/1

Counter Compare B Register Set

AQCTLA

0x680B

0x684B

0x688B

0x68CB

0x690B

0x694B

1/0

Action Qualifier Control Register For Output A

AQCTLB

0x680C0x684C0x688C

0x68CC0x690C0x694C

1/0

Action Qualifier Control Register For Output B

AQSFRC0x680D

0x684D

0x688D

0x68CD

0x690D

0x694D

1/0

Action Qualifier Software Force Register

AQCSFRC

0x680E0x684E0x688E

0x68CE

0x690E0x694E

1/1

Action Qualifier Continuous S/W Force Register Set

DBCTL

0x680F0x684F0x688F

0x68CF0x690F0x694F

1/1

Dead-Band Generator Control Register

DBRED

0x68100x68500x68900x68D00x69100x69501/0

Dead-Band Generator Rising Edge Delay Count Register

DBFED

0x68110x68510x6891

0x68D10x69110x6951

1/0

Dead-Band Generator Falling Edge Delay Count Register

TZSEL

0x68120x68520x68920x68D20x69120x6952

1/0

Trip Zone Select Register (1)TZCTL

0x68140x68540x68940x68D40x69140x6954

1/0

Trip Zone Control Register (1)TZEINT

0x68150x68550x68950x68D50x69150x6955

1/0

Trip Zone Enable Interrupt Register (1)TZFLG

0x68160x68560x6896

0x68D60x69160x6956

1/0

Trip Zone Flag Register

TZCLR

0x68170x68570x6897

0x68D70x69170x6957

1/0

Trip Zone Clear Register (1)TZFRC

0x68180x68580x68980x68D80x69180x6958

1/0

Trip Zone Force Register (1)NAME

DESCRIPTION

ETSEL

0x68190x68590x68990x68D90x69190x69591/0

Event Trigger Selection Register

ETPS

0x681A0x685A

0x689A

0x68DA

0x691A

0x695A

1/0

Event Trigger Prescale Register

ETFLG

0x681B

0x685B

0x689B

0x68DB

0x691B

0x695B

1/0

Event Trigger Flag Register

ETCLR

0x681C0x685C0x689C

0x68DC0x691C0x695C

1/0

Event Trigger Clear Register

ETFRC

0x681D

0x685D

0x689D

0x68DD

0x691D

0x695D

1/0

Event Trigger Force Register

PCCTL

0x681E0x685E0x689E

0x68DE

0x691E

0x695E

1/0

PWM Chopper Control Register

0x68E0

(2)

(2)

1/0

HRPWM Configuration Register (1)

HRCNFG(1)(2)

0x68200x68600x68A00x69200x6960Registers that are EALLOW protected.
Applicable to F2809 only

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Time−base (TB)
Sync
in/outselectMux

CTR=ZERO
CTR=CMPB
Disabled

TBPRD shadow (16)TBPRD active (16)
CTR=PRD

EPWMxSYNCOTBCTL[SYNCOSEL]TBCTL[CNTLDE]
EPWMxSYNCICounterup/down(16 bit)

CTR=ZERO
CTR_Dir

TBCNT
active (16)TBPHSHR (8)168TBPHS active (24)Phase
controlCounter compare (CC)CTR=CMPA
CMPAHR (8)16

TBCTL[SWFSYNC](software forced sync)

Actionqualifier(AQ)

CTR = PRD
CTR = ZERO
CTR = CMPA
CTR = CMPBCTR_Dir8

Event
triggerandinterrupt(ET)

EPWMxINT
EPWMxSOCA
EPWMxSOCB

HiRes PWM (HRPWM)

CMPA active (24)EPWMA

EPWMxAOCMPA shadow (24)
CTR=CMPB

Dead
band
(DB)

16

PWM
chopper
(PC)

EPWMB

EPWMxBOCMPB active (16)
CMPB shadow (16)

Trip
zone
(TZ)
EPWMxTZINTCTR = ZEROTZ1 to TZ6

Figure 4-4. ePWM Sub-Modules Showing Critical Internal Signal Interconnections

4.3

Hi-Resolution PWM (HRPWM)
The HRPWM module offers PWM resolution (time granularity) which is significantly better than what canbe achieved using conventionally derived digital PWM methods. The key points for the HRPWM moduleare:• Significantly extends the time resolution capabilities of conventionally derived digital PWM• Typically used when effective PWM resolution falls below ~ 9-10 bits. This occurs at PWM frequencies
greater than ~200 KHz when using a CPU/System clock of 100 MHz.
• This capability can be utilized in both duty cycle and phase-shift control methods.
• Finer time granularity control or edge positioning is controlled via extensions to the Compare A andPhase registers of the ePWM module.
• HRPWM capabilities are offered only on the A signal path of an ePWM module (i.e., on the EPWMxA
output). EPWMxB output has conventional PWM capabilities.

4.4

Enhanced CAP Modules (eCAP1/2/3/4)
The 280x device contains up to four enhanced capture (eCAP) modules. Figure 4-5 shows a functional
block diagram of a module. See the TMS320x280x Enhanced Capture (eCAP) Module Reference Guide(literature number SPRU807) for more details.
The eCAP modules are clocked at the SYSCLKOUT rate.

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SYNC

The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAP
modules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK,ECAP3ENCLK, and ECAP4ENCLK are set to low, indicating that the peripheral clock is off.

SYNCInSYNCOut

CTRPHS(phase register−32 bit)
TSCTR
(counter−32 bit)

APWM modeOVF
RST

CTR_OVF
Delta−mode

CTR [0−31]
PWM
comparelogic

PRD [0−31]
CMP [0−31]

32
CTR=PRD

CTR [0−31]

CTR=CMP
32

32

LD1

CAP1
(APRD active)
APRD
shadow
32

32

MODE SELECT

PRD [0−31]

Polarity
selectLD

32
CMP [0−31]

CAP2(ACMP active)
32

LD

LD2

Polarity
selectEventqualifierACMP
shadow

32

CAP3(APRD shadow)

LD

32

CAP4
(ACMP shadow)

LD

eCAPx

Event
Pre-scale
Polarity
selectLD3LD4Polarity
select4

Capture events

4

CEVT[1:4]

to PIEInterrupt
TriggerandFlagcontrolContinuous /Oneshot
Capture Control

CTR_OVF
CTR=PRD
CTR=CMP

Figure 4-5. eCAP Functional Block Diagram
Table 4-3. eCAP Control and Status Registers
NAME

ECAP1

ECAP2

ECAP3

ECAP4

SIZE
(x16)

TSCTR

0x6A00

0x6A20

0x6A400x6A602

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DESCRIPTION
Time-Stamp Counter
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Table 4-3. eCAP Control and Status Registers (continued)

60

NAME

ECAP1

ECAP2

ECAP3

ECAP4

SIZE
(x16)

DESCRIPTIONCTRPHS

0x6A02

0x6A22

0x6A42

0x6A62

2

Counter Phase Offset Value Register

CAP1

0x6A04

0x6A24

0x6A44

0x6A642

Capture 1 Register

CAP2

0x6A06

0x6A26

0x6A46

0x6A662

Capture 2 Register

CAP3

0x6A08

0x6A28

0x6A48

0x6A682

Capture 3 Register
Capture 4 Register

CAP4

0x6A0A

0x6A2A

0x6A4A

0x6A6A

2

Reserved

0x6A0C0x6A12

0x6A2C0x6A32

0x6A4C0x6A52

0x6A6C0x6A72

8

ECCTL1

0x6A14

0x6A34

0x6A54

0x6A741

Capture Control Register 1

ECCTL2

0x6A15

0x6A35

0x6A55

0x6A751

Capture Control Register 2

ECEINT

0x6A16

0x6A36

0x6A56

0x6A761

Capture Interrupt Enable Register

ECFLG

0x6A17

0x6A37

0x6A57

0x6A771

Capture Interrupt Flag Register

ECCLR

0x6A18

0x6A38

0x6A58

0x6A781

Capture Interrupt Clear Register

ECFRC

0x6A19

0x6A39

0x6A59

0x6A791

Capture Interrupt Force Register

Reserved

0x6A1A0x6A1F

0x6A3A0x6A3F

0x6A5A0x6A5F

0x6A7A0x6A7F

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4.5

Enhanced QEP Modules (eQEP1/2)
The 280x device contains up to two enhanced quadrature encoder (eQEP) modules. See the
TMS320x280x Enhanced Quadrature Encoder (eQEP) Module Reference Guide (literature number
SPRU790) for more details.
Systemcontrol registers

To CPU

EQEPxENCLK
Data bus

SYSCLKOUT

QCAPCTL

QCPRD
QCTMR

16

16

16
Quadrature
capture unit
(QCAP)QCTMRLATQCPRDLAT

Registers
used bymultiple units

QUTMR

QWDTMRQUPRD

QWDPRD32

16

QEPCTLQEPSTS

UTIME

QFLG

UTOUT

QWDOG

QDECCTL
16

WDTOUTPIE

EQEPxAINQCLK

EQEPxINT
16

QI

Position counter/
control unit
(PCCU)QPOSLATQSPHEQPOSSLAT

EQEPxIIN
Quadrature
decoder(QDU)

PCSOUTQPOSILAT

EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE

32

32

QPOSCNTQPOSINITQPOSMAXQPOSCMP

EQEPxA/XCLK

EQEPxBIN

QDIR

EQEPxB/XDIR
GPIO
MUX

EQEPxI
EQEPxS

16
QEINT
QFRC
QCLR
QPOSCTL

Enhanced QEP (eQEP) peripheral

Figure 4-6. eQEP Functional Block Diagram

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Table 4-4. eQEP Control and Status Registers
EQEP1
ADDRESS

EQEP2ADDRESS

EQEP1
SIZE(x16)/#SHADOWQPOSCNT

0x6B000x6B402/0eQEP Position CounterQPOSINIT

0x6B02

0x6B422/0

eQEP Initialization Position CountQPOSMAX

0x6B04

0x6B442/0

eQEP Maximum Position CountQPOSCMP0x6B060x6B462/1

eQEP Position-compare

QPOSILAT

0x6B08

0x6B482/0

eQEP Index Position Latch

QPOSSLAT

0x6B0A

0x6B4A

2/0

eQEP Strobe Position LatchQPOSLAT

0x6B0C

0x6B4C

2/0

eQEP Position Latch

QUTMR

0x6B0E

0x6B4E

2/0

eQEP Unit Timer

QUPRD

0x6B100x6B502/0eQEP Unit Period Register

QWDTMR

0x6B12

0x6B52

1/0

eQEP Watchdog Timer

QWDPRD

0x6B13

0x6B53

1/0

eQEP Watchdog Period Register

QDECCTL

0x6B14

0x6B541/0

eQEP Decoder Control Register

QEPCTL

0x6B15

0x6B551/0

eQEP Control Register

QCAPCTL

0x6B160x6B561/0

eQEP Capture Control Register

QPOSCTL

0x6B17

0x6B571/0

eQEP Position-compare Control Register

QEINT

0x6B18

0x6B581/0

eQEP Interrupt Enable Register

NAME

REGISTER DESCRIPTION

QFLG

0x6B190x6B591/0

eQEP Interrupt Flag Register

QCLR

0x6B1A

0x6B5A

1/0

eQEP Interrupt Clear Register

QFRC

0x6B1B

0x6B5B

1/0

eQEP Interrupt Force Register

QEPSTS

0x6B1C

0x6B5C

1/0

eQEP Status Register

QCTMR

0x6B1D

0x6B5D

1/0

eQEP Capture Timer

QCPRD

0x6B1E

0x6B5E

1/0

eQEP Capture Period Register

QCTMRLAT

0x6B1F

0x6B5F

1/0

eQEP Capture Timer Latch
eQEP Capture Period Latch

QCPRDLAT

0x6B200x6B60

1/0

Reserved

0x6B210x6B3F

0x6B610x6B7F

31/0

62

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4.6

Enhanced Analog-to-Digital Converter (ADC) Module
A simplified functional block diagram of the ADC module is shown in Figure 4-7. The ADC module
consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module
include:• 12-bit ADC core with built-in S/H• Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)• Fast conversion rate: Up to 80 ns at 25-MHz ADC clock, 12.5 MSPS
• 16-channel, MUXed inputs• Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion
can be programmed to select any 1 of 16 input channels• Sequencer can be operated as two independent 8-state sequencers or as one large 16-state
sequencer (i.e., two cascaded 8-state sequencers)• Sixteen result registers (individually addressable) to store conversion values– The digital value of the input analog voltage is derived by:when input ≤ 0 V

Digital Value + 0,
Digital Value + 4096
Digital Value + 4095,
A.

•

•
•
•
•

Input Analog Voltage * ADCLO
3

when 0 V < input < 3 V
when input ≥ 3 V

All fractional values are truncated.

Multiple triggers as sources for the start-of-conversion (SOC) sequence– S/W - software immediate start– ePWM start of conversion– XINT2 ADC start of conversion
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS.
Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" tosynchronize conversions.
SOCA and SOCB triggers can operate independently in dual-sequencer mode.
Sample-and-hold (S/H) acquisition time window has separate prescale control.

The ADC module in the 280x has been enhanced to provide flexible interface to ePWM peripherals. The
ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of up to 80 ns at
25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel
modules. The two independent 8-channel modules can be cascaded to form a 16-channel module.
Although there are multiple input channels and two sequencers, there is only one converter in the ADC
module. Figure 4-7 shows the block diagram of the ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module
has the choice of selecting any one of the respective eight channels available through an analog MUX. In
the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer,
once the conversion is complete, the selected channel value is stored in its respective RESULT register.
Autosequencing allows the system to convert the same channel multiple times, allowing the user toperform oversampling algorithms. This gives increased resolution over traditional single-sampledconversion results.

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SystemControl BlockADCENCLKSYSCLKOUT

High-Speed
Prescaler

HALT

DSP

HSPCLK

AnalogMUXResult Registers
Result Reg 0

ADCINA070A8h

Result Reg 1
S/H
ADCINA7
12-BitADC
ModuleResult Reg 7

70AFh

Result Reg 8

70B0h

Result Reg 15

70B7h

ADCINB0
S/H
ADCINB7ADC Control Registers
S/W
EPWMSOCAGPIO/XINT2_ADCSOC

SOC

Sequencer 2

Sequencer 1

SOC

S/W
EPWMSOCB

Figure 4-7. Block Diagram of the ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent
possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths.
This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs.
Furthermore, proper isolation techniques must be used to isolate the ADC module power pins ( VDD1A18,
VDD2A18 , VDDA2, VDDAIO ) from the digital supply.Figure 4-8 shows the ADC pin connections for the 280x
devices.
NOTE
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the
ADC module is controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT
signals is as follows:
–

–

64

Peripherals

ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) theclock to the register will still function. This is necessary to make sure all registers
and modes go into their default reset state. The analog module, however, will bein a low-power inactive state. As soon as reset goes high, then the clock to theregisters will be disabled. When the user sets the ADCENCLK signal high, thenthe clocks to the registers will be enabled and the analog module will be enabled.
There will be a certain time delay (ms range) before the ADC is stable and can beused.
HALT: This mode only affects the analog module. It does not affect the registers.
In this mode, the ADC module goes into low-power mode. This mode also will stop
the clock to the CPU, which will stop the HSPCLK; therefore, the ADC register
logic will be turned off indirectly.

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Figure 4-8 shows the ADC pin-biasing for internal reference and Figure 4-9 shows the ADC pin-biasing forexternal reference.
ADC 16-Channel Analog Inputs

ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCREFIN

Analog input 0−3 V with respect to ADCLO
Connect to analog ground
Float or ground if internal reference is used
22 kW

ADC External Current Bias Resistor

ADCRESEXTADC Reference Positive Output

ADCREFPADC Reference Medium Output

ADCREFMADC Power

2.2 mF (A)
2.2 mF (A)VDD1A18
VDD2A18

ADCREFP and ADCREFM should not
be loaded by external circuitry

VSS1AGNDVSS2AGNDADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
ADC Analog Ground Pin

VDDA2
VSSA2

ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin

VDDAIOVSSAIOADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin

ADC Analog and Reference I/O PowerA.

TAIYO YUDEN LMK212BJ225MG-T or equivalent

B.

External decoupling capacitors are recommended on all power pins.

C.

Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.

Figure 4-8. ADC Pin Connections With Internal Reference

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ADC 16-Channel Analog Inputs

ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCREFIN

Analog input 0−3 V with respect to ADCLO
Connect to Analog Ground
Connect to 1.500, 1.024, or 2.048-V precision source (D)22 kW

ADC External Current Bias Resistor

ADCRESEXTADC Reference Positive Output

ADCREFPADC Reference Medium Output

ADCREFMADC Analog PowerVDD1A18
VDD2A18
VSS1AGNDVSS2AGNDADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
ADC Analog Ground Pin

VDDA2
VSSA2

ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin

VDDAIOVSSAIOADC Analog Power Pin (3.3 V)

ADC Analog and Reference I/O Power

2.2 mF (A)
2.2 mF (A)ADCREFP and ADCREFM should not
be loaded by external circuitry

ADC Analog I/O Ground Pin

A.

TAIYO YUDEN LMK212BJ225MG-T or equivalent

B.

External decoupling capacitors are recommended on all power pins.

C.

Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.

D.

External voltage on ADCREFIN is enabled by changing bits 15:14 in the ADC Reference Select register depending on
the voltage used on this pin. TI recommends TI part REF3020 or equivalent for 2.048-V generation. Overall gain
accuracy will be determined by accuracy of this voltage source.

Figure 4-9. ADC Pin Connections With External Reference
NOTE
The temperature rating of any recommended component must match the rating of the end
product.

4.6.1

ADC Connections if the ADC Is Not Used
It is recommended to keep the connections for the analog power pins, even if the ADC is not used.
Following is a summary of how the ADC pins should be connected, if the ADC is not used in an
application:• VDD1A18/VDD2A18 – Connect to VDD• VDDA2, VDDAIO – Connect to VDDIO• VSS1AGND/VSS2AGND, VSSA2, VSSAIO – Connect to VSS• ADCLO – Connect to VSS• ADCREFIN – Connect to VSS• ADCREFP/ADCREFM – Connect a 100-nF cap to VSS• ADCRESEXT – Connect a 20-kΩ resistor (very loose tolerance) to VSS.
• ADCINAn, ADCINBn - Connect to VSS
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize powersavings.
When the ADC module is used in an application, unused ADC input pins should be connected to analog
ground (VSS1AGND/VSS2AGND)

66

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4.6.2

ADC Registers
The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-5.
Table 4-5. ADC Registers (1)NAME

ADDRESS (1)ADCTRL1

0x71001

ADC Control Register 1

ADCTRL20x7101

1

ADC Control Register 2

ADCMAXCONV

0x7102

1

ADC Maximum Conversion Channels Register

ADCCHSELSEQ1

0x7103

1

ADC Channel Select Sequencing Control Register 1

ADCCHSELSEQ20x71041

ADC Channel Select Sequencing Control Register 2

ADCCHSELSEQ30x71051

ADC Channel Select Sequencing Control Register 3

ADCCHSELSEQ40x71061

ADC Channel Select Sequencing Control Register 4

(1)
(2)

ADDRESS (2)SIZE (x16)

DESCRIPTIONADCASEQSR

0x7107

1

ADC Auto-Sequence Status Register

ADCRESULT00x71080x0B001

ADC Conversion Result Buffer Register 0

ADCRESULT1

0x71090x0B01

1

ADC Conversion Result Buffer Register 1

ADCRESULT2

0x710A

0x0B02

1

ADC Conversion Result Buffer Register 2

ADCRESULT3

0x710B

0x0B03

1

ADC Conversion Result Buffer Register 3

ADCRESULT40x710C

0x0B041

ADC Conversion Result Buffer Register 4

ADCRESULT50x710D

0x0B051

ADC Conversion Result Buffer Register 5

ADCRESULT6

0x710E

0x0B061

ADC Conversion Result Buffer Register 6

ADCRESULT7

0x710F

0x0B071

ADC Conversion Result Buffer Register 7

ADCRESULT8

0x7110

0x0B081

ADC Conversion Result Buffer Register 8

ADCRESULT90x7111

0x0B091

ADC Conversion Result Buffer Register 9

ADCRESULT10

0x71120x0B0A1

ADC Conversion Result Buffer Register 10

ADCRESULT11

0x71130x0B0B1

ADC Conversion Result Buffer Register 11

ADCRESULT12

0x71140x0B0C1ADC Conversion Result Buffer Register 12

ADCRESULT13

0x7115

0x0B0D1

ADC Conversion Result Buffer Register 13

ADCRESULT14

0x7116

0x0B0E1

ADC Conversion Result Buffer Register 14

ADCRESULT15

0x71170x0B0F1

ADC Conversion Result Buffer Register 15

ADCTRL30x71181

ADC Control Register 3

ADCST

0x71191

ADC Status Register

Reserved

0x711A
0x711B

2

ADCREFSEL

0x711C1

ADC Reference Select Register

ADCOFFTRIM

0x711D1

ADC Offset Trim Register

Reserved

0x711E0x711F2

ADC Status Register

The registers in this column are Peripheral Frame 2 Registers.
The ADC result registers are dual mapped in the 280x DSP. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait-states and left
justified. Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 0 wait sates and right justified. During high speed/continuous
conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to user memory.

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4.7

Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
The CAN module has the following features:• Fully compliant with CAN protocol, version 2.0B
• Supports data rates up to 1 Mbps
• Thirty-two mailboxes, each with the following properties:– Configurable as receive or transmit– Configurable with standard or extended identifier– Has a programmable receive mask
– Supports data and remote frame– Composed of 0 to 8 bytes of data
– Uses a 32-bit time stamp on receive and transmit message– Protects against reception of new message– Holds the dynamically programmable priority of transmit message– Employs a programmable interrupt scheme with two interrupt levels– Employs a programmable alarm on transmission or reception time-out• Low-power mode
• Programmable wake-up on bus activity• Automatic reply to a remote request message• Automatic retransmission of a frame in case of loss of arbitration or error• 32-bit local network time counter synchronized by a specific message (communication in conjunction
with mailbox 16)• Self-test mode
– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE
For a SYSCLKOUT of 100 MHz, the smallest bit rate possible is 15.625 kbps.
For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 9.375 kbps.

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eCAN0INT

Controls AddresseCAN1INT

Data

Enhanced CAN Controller

32

Message Controller
Mailbox RAM(512 Bytes)
32-Message Mailboxof 4 × 32-Bit Words

Memory Management
Unit
32

CPU Interface,
Receive Control Unit,
Timer Management Unit

eCAN Memory(512 Bytes)
Registers and Message
Objects Control

32

32

Receive Buffer

eCAN Protocol Kernel

Transmit Buffer
Control Buffer
Status Buffer

SN65HVD23x
3.3-V CAN Transceiver

CAN BusFigure 4-10. eCAN Block Diagram and Interface Circuit
Table 4-6. 3.3-V eCAN Transceivers
PART NUMBER

SUPPLYVOLTAGE

LOW-POWER
MODE

SLOPE
CONTROL

VREF

OTHER

TA

SN65HVD230

3.3 V

StandbyAdjustable

Yes–-40°C to 85°C

SN65HVD230Q

3.3 V

StandbyAdjustable

Yes–-40°C to 125°C

SN65HVD231

3.3 V

Sleep

Adjustable

Yes–-40°C to 85°C

SN65HVD231Q

3.3 V

Sleep

Adjustable

Yes–-40°C to 125°C

SN65HVD232

3.3 V

None

None

None

–

-40°C to 85°C

SN65HVD232Q

3.3 V

None

None

None

–

-40°C to 125°C

SN65HVD233

3.3 V

StandbyAdjustable

None

Diagnostic
Loopback-40°C to 125°C

SN65HVD234

3.3 V

Standby & Sleep

Adjustable

None

–

-40°C to 125°C

SN65HVD235

3.3 V

StandbyAdjustable

None

Autobaud
Loopback-40°C to 125°C

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eCAN-A Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
eCAN-A Memory (512 Bytes)
6000h

Abort Acknowledge − CANAA
Received Message Pending − CANRMP

Control and Status Registers

Received Message Lost − CANRML

603Fh
6040h
607Fh
6080h
60BFh
60C0h
60FFh

Remote Frame Pending − CANRFP

Local Acceptance Masks (LAM)(32 × 32-Bit RAM)

Global Acceptance Mask − CANGAM

Message Object Time Stamps (MOTS)(32 × 32-Bit RAM)

Bit-Timing Configuration − CANBTC

Message Object Time-Out (MOTO)(32 × 32-Bit RAM)

Transmit Error Counter − CANTEC

Master Control − CANMC
Error and Status − CANES
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1

eCAN-A Memory RAM (512 Bytes)
6100h−6107h

Mailbox 06108h−610Fh

Mailbox 1

6110h−6117h

Mailbox 26118h−611Fh

Mailbox 36120h−6127h

Mailbox 4

Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMILOverwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS

61E0h−61E7h

Mailbox 28

61E8h−61EFh

Mailbox 29

61F0h−61F7h

Mailbox 30

61F8h−61FFh

Mailbox 31

Reserved

Message Mailbox (16 Bytes)
61E8h−61E9h

Message Identifier − MSGID

61EAh−61EBh

Message Control − MSGCTRL

61ECh−61EDh

Message Data Low − MDL

61EEh−61EFh

Message Data High − MDH

Figure 4-11. eCAN-A Memory Map
NOTE
If the eCAN module is not used in an application, the RAM available (LAM, MOTS,
MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock
should be enabled for this.

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eCAN-B Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
eCAN-B Memory (512 Bytes)
6200h

Abort Acknowledge − CANAA
Received Message Pending − CANRMP

Control and Status Registers

Received Message Lost − CANRML

623Fh
6240h
627Fh
6280h
62BFh
62C0h
62FFh

Remote Frame Pending − CANRFP

Local Acceptance Masks (LAM)(32 × 32-Bit RAM)

Global Acceptance Mask − CANGAM

Message Object Time Stamps (MOTS)(32 × 32-Bit RAM)

Bit-Timing Configuration − CANBTC

Message Object Time-Out (MOTO)(32 × 32-Bit RAM)

Transmit Error Counter − CANTEC

Master Control − CANMC
Error and Status − CANES
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1

eCAN-B Memory RAM (512 Bytes)
6300h−6307h

Mailbox 06308h−630Fh

Mailbox 1

6310h−6317h

Mailbox 26318h−631Fh

Mailbox 36320h−6327h

Mailbox 4

Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMILOverwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS

63E0h−63E7h

Mailbox 28

63E8h−63EFh

Mailbox 29

63F0h−63F7h

Mailbox 30

63F8h−63FFh

Mailbox 31

Reserved

Message Mailbox (16 Bytes)
63E8h−63E9h

Message Identifier − MSGID

63EAh−63EBh

Message Control − MSGCTRL

63ECh−63EDh

Message Data Low − MDL

63EEh−63EFh

Message Data High − MDH

Figure 4-12. eCAN-B Memory Map
The CAN registers listed in Table 4-7 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.

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Table 4-7. CAN Register Map (1)REGISTER NAME

ECAN-A
ADDRESS

ECAN-BADDRESS

SIZE
(x32)

(1)

72

DESCRIPTION

CANME

0x60000x62001

Mailbox enable

CANMD

0x60020x6202

1

Mailbox direction

CANTRS

0x60040x6204

1

Transmit request set

CANTRR

0x60060x6206

1

Transmit request reset

CANTA

0x60080x62081

Transmission acknowledge

CANAA

0x600A

0x620A

1

Abort acknowledge

CANRMP

0x600C0x620C

1

Receive message pending

CANRML

0x600E0x620E

1

Receive message lost

CANRFP

0x60100x62101

Remote frame pending

CANGAM

0x60120x6212

1

Global acceptance mask

CANMC

0x60140x6214

1

Master control

CANBTC

0x60160x6216

1

Bit-timing configuration

CANES

0x60180x62181

Error and status

CANTEC

0x601A

0x621A

1

Transmit error counter

CANREC

0x601C

0x621C

1

Receive error counter

CANGIF00x601E0x621E

1

Global interrupt flag 0

CANGIM

0x60200x62201

Global interrupt mask

CANGIF10x60220x6222

1

Global interrupt flag 1

CANMIM

0x60240x62241

Mailbox interrupt mask

CANMIL

0x60260x62261

Mailbox interrupt level

CANOPC

0x60280x62281

Overwrite protection control

CANTIOC

0x602A

0x622A1

TX I/O control

CANRIOC

0x602C

0x622C1

RX I/O control

CANTSC

0x602E0x622E

1Time stamp counter (Reserved in SCC mode)

CANTOC

0x60300x62301Time-out control (Reserved in SCC mode)

CANTOS

0x60320x6232

1

Time-out status (Reserved in SCC mode)

These registers are mapped to Peripheral Frame 1.

Peripherals

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4.8

Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)
The 280x devices include two serial communications interface (SCI) modules. The SCI modules support
digital communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its
own separate enable and interrupt bits. Both can be operated independently or simultaneously in the
full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity,
overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit
baud-select register.
Features of each SCI module include:• Two external pins:– SCITXD: SCI transmit-output pin– SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:

•

•
•
•
•
•

•
•

•
•

Baud rate =LSPCLK(BRR ) 1) * 8

when BRR ≠ 0

Baud rate =LSPCLK
16

when BRR = 0

Data-word format– One start bit– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit– One or two stop bits
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)Max bit rate + 100 MHz + 6.25 106 bńs
16(for 100 MHz devices)60
MHz
6
Max bit rate ++ 3.75 10 bńs
16(for 60 MHz devices)
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upperbyte (15-8) is read as zeros. Writing to the upper byte has no effect.

Enhanced features:• Auto baud-detect hardware logic
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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007•16-level transmit/receive FIFOThe SCI port operation is configured and controlled by the registers listed in Table 4-8 and Table 4-9.
Table 4-8. SCI-A Registers (1)NAME

ADDRESSSIZE (x16)

SCICCRA0x70501

SCI-A Communications Control Register

SCICTL1A

0x7051

1

SCI-A Control Register 1

SCIHBAUDA

0x7052

1

SCI-A Baud Register, High Bits

SCILBAUDA

0x7053

1

SCI-A Baud Register, Low Bits

SCICTL2A

0x7054

1

SCI-A Control Register 2

SCIRXSTA

0x7055

1

SCI-A Receive Status Register

SCIRXEMUA

0x7056

1

SCI-A Receive Emulation Data Buffer Register

SCIRXBUFA

0x7057

1

SCI-A Receive Data Buffer Register

SCITXBUFA

0x70591

SCI-A Transmit Data Buffer Register(2)0x705A

1

SCI-A FIFO Transmit Register

SCIFFRXA (2)0x705B

1

SCI-A FIFO Receive Register

SCIFFCTA (2)0x705C1

SCI-A FIFO Control Register

SCIPRIA0x705F

1

SCI-A Priority Control Register

SCIFFTXA(1)(2)

DESCRIPTION

Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.

Table 4-9. SCI-B Registers (1) (2)NAME

ADDRESSSIZE (x16)

SCICCRB

0x77501

SCI-B Communications Control Register

SCICTL1B

0x7751

1

SCI-B Control Register 1

SCIHBAUDB

0x7752

1

SCI-B Baud Register, High Bits

SCILBAUDB

0x7753

1

SCI-B Baud Register, Low Bits

SCICTL2B

0x7754

1

SCI-B Control Register 2

SCIRXSTB

0x7755

1

SCI-B Receive Status Register

SCIRXEMUB

0x7756

1

SCI-B Receive Emulation Data Buffer Register

SCIRXBUFB

0x7757

1

SCI-B Receive Data Buffer Register

SCITXBUFB

0x77591

SCI-B Transmit Data Buffer Register

SCIFFTXB (2)0x775A

1

SCI-B FIFO Transmit Register(2)0x775B

1

SCI-B FIFO Receive Register

SCIFFCTB (2)0x775C

1

SCI-B FIFO Control Register

SCIPRIB

0x775F

1

SCI-B Priority Control Register

SCIFFRXB

(1)
(2)

74

DESCRIPTION

Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.

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Figure 4-13 shows the SCI module block diagram.
SCICTL1.1
SCITXD

Frame Format and Mode
ParityEven/Odd Enable

TXSHF
Register

TXENA

8SCICCR.6 SCICCR.5

TX EMPTYSCICTL2.6
TXRDY

TXWAKESCICTL1.3
1

Transmitter-Data
Buffer Register

8

TX INT ENA

SCICTL2.7
SCICTL2.0
TX FIFOInterrupts

TX FIFO _0
TX FIFO _1

SCITXDTXINT
TX Interrupt
Logic

-----

To CPU

TX FIFO _15

WUT

SCI TX Interrupt select logic

SCITXBUF.7-0
TX FIFO registers
SCIFFENA

AutoBaud Detect logic

SCIFFTX.14

SCIHBAUD. 15 - 8
Baud Rate
MSbyteRegister

SCIRXD

RXSHFRegister

SCIRXDRXWAKELSPCLKSCIRXST.1
SCILBAUD. 7 - 0
Baud Rate
LSbyteRegister

RXENA
8SCICTL1.0
SCICTL2.1

Receive Data
Buffer register
SCIRXBUF.7-0

RXRDY

8

BRKDT

RX FIFO _15----RX FIFO_1
RX FIFO _0
SCIRXBUF.7-0

RX/BK INT ENASCIRXST.6

SCIRXST.5
RX FIFOInterrupts
RX Interrupt
Logic

To CPURX FIFO registers

SCIRXST.7

SCIRXST.4 - 2

RX Error

FE OE PERXINT

RXFFOVFSCIFFRX.15

RX Error
RX ERR INT ENA
SCICTL1.6

SCI RX Interrupt select logic

Figure 4-13. Serial Communications Interface (SCI) Module Block Diagram

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4.9

Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)The 280x devices include the four-pin serial peripheral interface (SPI) module. Up to four SPI modules(SPI-A, SPI-B, SPI-C, and SPI-D) are available. The SPI is a high-speed, synchronous serial I/O port thatallows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of thedevice at a programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include external I/O orperipheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice
communications are supported by the master/slave operation of the SPI.
The SPI module features include:• Four external pins:– SPISOMI: SPI slave-output/master-input pin– SPISIMO: SPI slave-input/master-output pin– SPISTE: SPI slave transmit-enable pin– SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
• Two operational modes: master and slave
Baud rate: 125 different programmable rates.

•
•

•
•
•

Baud rate =LSPCLK(SPIBRR ) 1)

when SPIBRR = 3 to 127

Baud rate =LSPCLK
4

when SPIBRR = 0,1, 2

Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of thefalling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of thefalling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upperbyte (15-8) is read as zeros. Writing to the upper byte has no effect.

Enhanced feature:• 16-level transmit/receive FIFO
• Delayed transmit control
The SPI port operation is configured and controlled by the registers listed in Table 4-10.

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Table 4-10. SPI-A Registers(1)

DESCRIPTION (1)NAME

ADDRESSSIZE (X16)

SPICCR

0x70401

SPI-A Configuration Control Register

SPICTL0x70411

SPI-A Operation Control Register

SPISTS0x7042

1

SPI-A Status Register

SPIBRR

0x7044

1

SPI-A Baud Rate Register

SPIRXEMU

0x7046

1

SPI-A Receive Emulation Buffer Register

SPIRXBUF

0x7047

1

SPI-A Serial Input Buffer Register

SPITXBUF

0x7048

1

SPI-A Serial Output Buffer Register

SPIDAT

0x70491

SPI-A Serial Data Register

SPIFFTX

0x704A

1

SPI-A FIFO Transmit Register

SPIFFRX0x704B

1

SPI-A FIFO Receive Register

SPIFFCT

0x704C1

SPI-A FIFO Control Register

SPIPRI

0x704F

1

SPI-A Priority Control Register

Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.

Table 4-11. SPI-B Registers(1)

DESCRIPTION (1)NAME

ADDRESSSIZE (X16)

SPICCR

0x77401

SPI-B Configuration Control Register

SPICTL

0x7741

1

SPI-B Operation Control Register

SPISTS0x7742

1

SPI-B Status Register

SPIBRR

0x7744

1

SPI-B Baud Rate Register

SPIRXEMU

0x7746

1

SPI-B Receive Emulation Buffer Register

SPIRXBUF

0x7747

1

SPI-B Serial Input Buffer Register

SPITXBUF

0x7748

1

SPI-B Serial Output Buffer Register

SPIDAT0x77491

SPI-B Serial Data Register

SPIFFTX

0x774A

1

SPI-B FIFO Transmit Register

SPIFFRX0x774B

1

SPI-B FIFO Receive Register

SPIFFCT

0x774C

1

SPI-B FIFO Control Register

SPIPRI

0x774F

1

SPI-B Priority Control Register

Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.

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TMS320F2809, TMS320F2808, TMS320F2806
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Table 4-12. SPI-C Registers(1)

DESCRIPTION (1)NAME

ADDRESSSIZE (X16)

SPICCR

0x77601

SPI-C Configuration Control Register

SPICTL

0x7761

1

SPI-C Operation Control Register

SPISTS

0x7762

1

SPI-C Status Register

SPIBRR

0x7764

1

SPI-C Baud Rate Register

SPIRXEMU

0x7766

1

SPI-C Receive Emulation Buffer Register

SPIRXBUF

0x7767

1

SPI-C Serial Input Buffer Register

SPITXBUF

0x7768

1

SPI-C Serial Output Buffer Register

SPIDAT

0x77691

SPI-C Serial Data Register

SPIFFTX

0x776A

1

SPI-C FIFO Transmit Register

SPIFFRX0x776B

1

SPI-C FIFO Receive Register

SPIFFCT

0x776C1

SPI-C FIFO Control Register

SPIPRI

0x776F

1

SPI-C Priority Control Register

Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.

Table 4-13. SPI-D Registers

(1)

78

DESCRIPTION (1)NAME

ADDRESSSIZE (X16)

SPICCR

0x7780

1

SPI-D Configuration Control Register

SPICTL

0x7781

1

SPI-D Operation Control Register

SPISTS

0x7782

1

SPI-D Status Register

SPIBRR

0x7784

1

SPI-D Baud Rate Register

SPIRXEMU

0x7786

1

SPI-D Receive Emulation Buffer Register

SPIRXBUF

0x7787

1

SPI-D Serial Input Buffer Register

SPITXBUF

0x7788

1

SPI-D Serial Output Buffer Register

SPIDAT

0x7789

1

SPI-D Serial Data Register

SPIFFTX

0x778A

1

SPI-D FIFO Transmit Register

SPIFFRX0x778B

1

SPI-D FIFO Receive Register

SPIFFCT

0x778C1

SPI-D FIFO Control Register

SPIPRI

0x778F

1

SPI-D Priority Control Register

Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.

Peripherals

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Figure 4-14 is a block diagram of the SPI in slave mode.

SPIFFENASPIFFTX.14

ReceiverOverrun Flag

RX FIFO registers

SPISTS.7

OverrunINT ENASPICTL.4

SPIRXBUF
RX FIFO _0
RX FIFO _1−−−−−

SPIINT/SPIRXINT

RX FIFO Interrupt

RX Interrupt
Logic

RX FIFO _15

16
SPIRXBUF
Buffer Register

SPIFFOVF FLAG
SPIFFRX.15

To CPU

TX FIFO registers

SPITXBUF
TX FIFO _15−−−−−

TX Interrupt
Logic

TX FIFO Interrupt

TX FIFO _1
TX FIFO _0

SPITXINT16

SPI INT FLAGSPITXBUF
Buffer Register

16

SPI INTENA

SPISTS.6
SPICTL.0

16
M

M
SPIDAT
Data Register

S
S

SW1

SPISIMO
M

M

SPIDAT.15 − 0

S
S

SW2

SPISOMITalk
SPICTL.1
SPISTE(A)State Control
Master/Slave
SPI Char

SPICCR.3 − 0
3

2

1

SW3
M

SPI Bit Rate
LSPCLKS

SPIBRR.6 − 0
6A.

SPICTL.2

S

0

5

4

3

2

1

0

Clock
Polarity

Clock
Phase

SPICCR.6

SPICTL.3

SPICLKM

SPISTE is driven low by the master for a slave device.

Figure 4-14. SPI Module Block Diagram (Slave Mode)

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

4.10 Inter-Integrated Circuit (I2C)
The 280x device contains one I2C Serial Port. Figure 4-15 shows how the I2C peripheral moduleinterfaces within the 280x device.
The I2C module has the following features:• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):– Support for 1-bit to 8-bit format transfers– 7-bit and 10-bit addressing modes– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers– Support for multiple slave-transmitters and master-receivers– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (Philips Fast-mode rate)• One 16-bit receive FIFO and one 16-bit transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of thefollowing conditions:– Transmit-data ready– Receive-data ready– Register-access ready– No-acknowledgment received– Arbitration lost
– Stop condition detected– Addressed as slave• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability• Free data format mode

80

Peripherals

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System Control
Block

C28X CPUI2CAENCLKSYSRSControl
Data[16]
SDAA

Peripheral Bus

SYSCLKOUT

Data[16]

GPIO
MUX

I2C−A

Addr[16]SCLA
I2CINT1A
PIE
Block
I2CINT2AA.

The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port arealso at the SYSCLKOUT rate.

B.

The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.

Figure 4-15. I2C Peripheral Module Interfaces
The registers in Table 4-14 configure and control the I2C port operation.
Table 4-14. I2C-A Registers
NAME

ADDRESSI2COAR

0x7900I2C own address register

DESCRIPTION

I2CIER

0x7901I2C interrupt enable register

I2CSTR

0x7902I2C status register

I2CCLKL

0x7903

I2C clock low-time divider register

I2CCLKH

0x7904I2C clock high-time divider register

I2CCNT

0x7905I2C data count register

I2CDRR

0x7906

I2C data receive register

I2CSAR

0x7907

I2C slave address register

I2CDXR

0x7908I2C data transmit register

I2CMDR

0x7909I2C mode register

I2CISRC

0x790AI2C interrupt source register

I2CPSC

0x790CI2C prescaler register

I2CFFTX

0x7920I2C FIFO transmit register

I2CFFRX0x7921I2C FIFO receive register

I2CRSR-I2C receive shift register (not accessible to the CPU)I2CXSR-I2C transmit shift register (not accessible to the CPU)

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TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

4.11 GPIO MUXOn the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO
pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin
is shown in Figure 4-16. Because of the open drain capabilities of the I2C pins, the GPIO MUX block
diagram for these pins differ. See the TMS320x280x System Control and Interrupts Reference Guide(literature number SPRU712) for details.
GPIOXINT1SELGPIOLMPSELGPIOXINT2SELLPMCR0GPIOXNMISEL

Low Power
Modes Block

External Interrupt
MUX

Asynchronouspath

GPxDAT (read)
GPxQSEL1/2
GPxCTRLGPxPUD

00
Input
Qualification

Internal
Pullup

PIE

N/C

01

Peripheral 1 Input

10

Peripheral 2 Input

11

Peripheral 3 Input
GPxTOGGLE

Asynchronous path
GPIOx pin

GPxCLEARGPxSET00

GPxDAT (latch)

01

Peripheral 1 Output

10

Peripheral 2 Output

11

Peripheral 3 Output

00

GPxDIR (latch)

High Impedance
Output Control

01

Peripheral 1 Output Enable

10

Peripheral 2 Output Enable

11

Peripheral 3 Output Enable

0 = Input, 1 = Output
XRS= Default at Reset

GPxMUX1/2

A.

x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.

B.

GPxDAT latch/read are accessed at the same memory location.

Figure 4-16. GPIO MUX Block Diagram

82

Peripherals

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The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1
to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-15 shows the GPIO
register mapping.
Table 4-15. GPIO Registers
NAME

ADDRESSSIZE (x16)

DESCRIPTIONGPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL

0x6F802

GPIO A Control Register (GPIO0 to 31)

GPAQSEL1

0x6F82

2

GPIO A Qualifier Select 1 Register (GPIO0 to 15)

GPAQSEL2

0x6F84

2

GPIO A Qualifier Select 2 Register (GPIO16 to 31)

GPAMUX1

0x6F862

GPIO A MUX 1 Register (GPIO0 to 15)

GPAMUX2

0x6F882

GPIO A MUX 2 Register (GPIO16 to 31)

GPADIR

0x6F8A

2

GPIO A Direction Register (GPIO0 to 31)

GPAPUD

0x6F8C

2

GPIO A Pull Up Disable Register (GPIO0 to 31)

reserved

0x6F8E
0x6F8F

2

GPBCTRL

0x6F902

GPIO B Control Register (GPIO32 to 35)

GPBQSEL1

0x6F92

2

GPIO B Qualifier Select 1 Register (GPIO32 to 35)

GPBQSEL2

0x6F942

reserved

GPBMUX1

0x6F962

GPIO B MUX 1 Register (GPIO32 to 35)

GPBMUX2

0x6F982

reserved

GPBDIR

0x6F9A

2

GPIO B Direction Register (GPIO32 to 35)

GPBPUD

0x6F9C

2

GPIO B Pull Up Disable Register (GPIO32 to 35)

reserved

0x6F9E
0x6F9F2

reserved

reserved

0x6FA00x6FBF

32

GPIO DATA REGISTERS (NOT EALLOW PROTECTED)GPADAT

0x6FC02

GPIO Data Register (GPIO0 to 31)

GPASET

0x6FC2

2

GPIO Data Set Register (GPIO0 to 31)

GPACLEAR

0x6FC4

2

GPIO Data Clear Register (GPIO0 to 31)

GPATOGGLE

0x6FC62

GPIO Data Toggle Register (GPIO0 to 31)

GPBDAT

0x6FC82

GPIO Data Register (GPIO32 to 35)

GPBSET

0x6FCA

2

GPIO Data Set Register (GPIO32 to 35)

GPBCLEAR

0x6FCC

2

GPIO Data Clear Register (GPIO32 to 35)

GPBTOGGLE

0x6FCE

2

GPIO Data Toggle Register (GPIO32 to 35)

reserved

0x6FD00x6FDF

16

GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)GPIOXINT1SEL

0x6FE01

XINT1 GPIO Input Select Register (GPIO0 to 31)

GPIOXINT2SEL

0x6FE1

1

XINT2 GPIO Input Select Register (GPIO0 to 31)

GPIOXNMISEL

0x6FE2

1

XNMI GPIO Input Select Register (GPIO0 to 31)

reserved

0x6FE30x6FE7

5

GPIOLPMSEL

0x6FE82

reserved

0x6FEA
0x6FFF

22

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LPM GPIO Select Register (GPIO0 to 31)

Peripherals

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 4-16. F2808 GPIO MUX Table
DEFAULT AT RESETPRIMARY I/O
FUNCTION(GPxMUX1/2
BITS = 0,0)

GPAMUX1/2 (1)REGISTER
BITS

PERIPHERALSELECTION 1 (2)(GPxMUX1/2 BITS = 0,1)

PERIPHERALSELECTION 2(GPxMUX1/2 BITS = 1,0)

PERIPHERALSELECTION 3(GPxMUX1/2 BITS = 1,1)

GPAMUX1
1-0

GPIO0

EPWM1A (O)Reserved (3)Reserved (3)

3-2

GPIO1

EPWM1B (O)SPISIMOD (I/O)

Reserved (3)

(3)

5-4

GPIO2

EPWM2A (O)Reserved

7-6

GPIO3

EPWM2B (O)SPISOMID (I/O)(3)

Reserved (3)Reserved (3)Reserved (3)

9-8

GPIO4

EPWM3A (O)Reserved

11-10

GPIO5

EPWM3B (O)SPICLKD (I/O)

ECAP1 (I/O)

13-12

GPIO6

EPWM4A (O)EPWMSYNCI (I)EPWMSYNCO (O)

15-14

GPIO7

EPWM4B (O)SPISTED (I/O)

ECAP2 (I/O)

17-16

GPIO8

EPWM5A (O)CANTXB (O)ADCSOCAO (O)

19-18

GPIO9

EPWM5B (O)SCITXDB (O)ECAP3 (I/O)

21-20

GPIO10EPWM6A (O)CANRXB (I)

ADCSOCBO (O)

23-22

GPIO11EPWM6B (O)SCIRXDB (I)ECAP4 (I/O)

25-24

GPIO12TZ1 (I)CANTXB (O)SPISIMOB (I/O)

27-26

GPIO13TZ2 (I)CANRXB (I)

SPISOMIB (I/O)

29-28

GPIO14TZ3 (I)SCITXDB (O)SPICLKB (I/O)

31-30

GPIO15TZ4 (I)SCIRXDB (I)SPISTEB (I/O)

GPAMUX2
1-0

GPIO16SPISIMOA (I/O)

CANTXB (O)TZ5 (I)

3-2

GPIO17SPISOMIA (I/O)

CANRXB (I)TZ6 (I)

5-4

GPIO18SPICLKA (I/O)

SCITXDB (O)Reserved (3)7-6GPIO19SPISTEA (I/O)

SCIRXDB (I)

Reserved (3)9-8GPIO20

EQEP1A (I)SPISIMOC (I/O)

CANTXB (O)

11-10

GPIO21

EQEP1B (I)

SPISOMIC (I/O)

CANRXB (I)

13-12

GPIO22

EQEP1S (I/O)

SPICLKC (I/O)

SCITXDB (O)

15-14

GPIO23

EQEP1I (I/O)

SPISTEC (I/O)

SCIRXDB (I)

17-16

GPIO24

ECAP1 (I/O)

EQEP2A (I)SPISIMOB (I/O)

19-18

GPIO25

ECAP2 (I/O)

EQEP2B (I)

SPISOMIB (I/O)

21-20

GPIO26

ECAP3 (I/O)

EQEP2I (I/O)

SPICLKB (I/O)

23-22

GPIO27

ECAP4 (I/O)

EQEP2S (I/O)

SPISTEB (I/O)

25-24

GPIO28SCIRXDA (I)

Reserved (3)TZ5 (I)(3)

TZ6 (I)

27-26

GPIO29SCITXDA (O)Reserved

29-28

GPIO30CANRXA (I)

Reserved (3)Reserved (3)(3)

Reserved (3)31-30

GPIO31CANTXA (O)Reserved

1-0

GPIO32SDAA (I/OC)

EPWMSYNCI (I)ADCSOCAO (O)

3-2

GPIO33SCLA (I/OC)

EPWMSYNCO (O)ADCSOCBO (O)5-4

GPIO34

Reserved (3)Reserved (3)Reserved (3)GPBMUX1

(1)
(2)
(3)

84

GPxMUX1/2 refers to the appropriate MUX register for the pin; GPAMUX1, GPAMUX2 or GPBMUX1.
This table pertains to the 2808 device. Some peripherals may not be available in the 2809, 2806, 2802, or 2801 devices. See the pin
descriptions for more detail.
The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.

Peripherals

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers fromfour choices:• Synchronization To SYSCLKOUT Only (GPxQSEL1/2=0,0): This is the default mode of all GPIO pinsat reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
• Qualification Using Sampling Window (GPxQSEL1/2=0,1 and 1,0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before
the input is allowed to change.
Time between samples
GPyCTRL Reg

GPIOx

SYNC

Qualification

Input Signal
Qualified By 3
or 6 Samples

GPxQSELSYSCLKOUT
Number of Samples

Figure 4-17. Qualification Using Sampling Window••

The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable ingroups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The
sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL
samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).
No Synchronization (GPxQSEL1/2=1,1): This mode is used for peripherals where synchronization is
not required (synchronization is performed within the peripheral).

Due to the multi-level multiplexing that is required on the 280x device, there may be cases where aperipheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is notselected, the input signal will default to either a 0 or 1 state, depending on the peripheral.

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

5

Device Support
Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSPs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of 280x-based applications:
Software Development Tools• Code Composer Studio™ Integrated Development Environment (IDE)– C/C++ Compiler– Code generation tools– Assembler/Linker– Cycle Accurate Simulator• Application algorithms• Sample applications code
Hardware Development Tools• 2808 eZdsp™
• Evaluation modules• JTAG-based emulators - SPI515, XDS510PP, XDS510PP Plus, XDS510USB• Universal 5-V dc power supply• Documentation and cables

5.1

Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ DSP devices and support tools. Each TMS320™ DSP commercial family member has one ofthree prefixes: TMX, TMP, or TMS (e.g., TMS320F2808). Texas Instruments recommends two of threepossible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX/TMDX) through fully qualified
production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX

Experimental device that is not necessarily representative of the final device's electrical
specifications

TMP

Final silicon die that conforms to the device's electrical specifications but has not completedquality and reliability verification

TMS

Fully qualified production device

Support tool development evolutionary flow:
TMDX

Development-support product that has not yet completed Texas Instruments internal qualification
testing

TMDS

Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality andreliability of the device have been demonstrated fully. TI's standard warranty applies.

86

Device Support

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TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices areto be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PBK) and temperature range (for example, A). Figure 5-1 provides a legend
for reading the complete device name for any family member.
TMS

320

F

28015

PZ

A

PREFIX
TMX = Experimental Device
TMP = Prototype Device
TMS = Qualified Device

Indicates 60-MHz device
Absence of “−60” indicates
100-MHz device.
TEMPERATURE RANGE
A= –405C to 855C
S
= –405C to 1255C
Q = –405C to 1255C — Q100 Fault Grading

DEVICE FAMILY
320 = TMS320E DSP Family

TECHNOLOGYF = Flash EEPROM(1.8-V Core/3.3-V I/O)

−60

PACKAGE TYPE
PZ
= 100-Pin Low-Profile Quad
Flatpack (LQFP)
GGM = 100-Ball Ball Grid Array (BGA)
ZGM = 100-Ball Lead-Free BGA
DEVICE
2809
2808
2806
2802
2801
28015
28016

Figure 5-1. Example of TMS320x280x Device Nomenclature

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SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

5.2

Documentation Support
Extensive documentation supports all of the TMS320™ DSP family generations of devices from productannouncement through applications development. The types of documentation available include: data
sheets and data manuals, with design specifications; and hardware and software applications. Usefulreference documentation includes:
CPU User's Guides
SPRU430
TMS320C28x DSP CPU and Instruction Set Reference Guide describes the central
processing unit (CPU) and the assembly language instructions of the TMS320C28x
fixed-point digital signal processors (DSPs). It also describes emulation features available onthese DSPs.
SPRU712

TMS320x280x, 2801x, 2804x System Control and Interrupts Reference Guide describes thevarious interrupts and system control features of the 280x digital signal processors (DSPs).

Peripheral Guides
SPRU566
TMS320x28xx, 28xxx Peripheral Reference Guide describes the peripheral reference guidesof the 28x digital signal processors (DSPs).

88

SPRU716

TMS320x280x, 2801x, 2804x Analog-to-Digital Converter (ADC) Reference Guide describes
how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC.

SPRU791

TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide
describes the main areas of the enhanced pulse width modulator that include digital motor
control, switch mode power supply control, UPS (uninterruptible power supplies), and otherforms of power conversion

SPRU924

TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) describes theoperation of the high-resolution extension to the pulse width modulator (HRPWM)

SPRU807

TMS320x28xx, 28xxx Enhanced Capture (eCAP) Module Reference Guide describes theenhanced capture module. It includes the module description and registers.

SPRU790

TMS320x28xx, 28xxx Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide
describes the eQEP module, which is used for interfacing with a linear or rotary incremental
encoder to get position, direction, and speed information from a rotating machine in highperformance motion and position control systems. It includes the module description andregisters

SPRU074

TMS320x28xx, 28xxx Enhanced Controller Area Network (eCAN) Reference Guide
describes the eCAN that uses established protocol to communicate serially with othercontrollers in electrically noisy environments.

SPRU051

TMS320x28xx, 28xxx Serial Communication Interface (SCI) Reference Guide describes the
SCI, which is a two-wire asynchronous serial port, commonly known as a UART. The SCI
modules support digital communications between the CPU and other asynchronous
peripherals that use the standard non-return-to-zero (NRZ) format.

SPRU059

TMS320x28xx, 28xxx Serial Peripheral Interface (SPI) Reference Guide describes the SPI a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream ofprogrammed length (one to sixteen bits) to be shifted into and out of the device at a
programmed bit-transfer rate.

SPRU721

TMS320x28xx, 28xxx Inter-Integrated Circuit (I2C) Reference Guide describes the featuresand operation of the inter-integrated circuit (I2C) module that is available on the
TMS320x280x digital signal processor (DSP).

SPRU722

TMS320x280x, 2801x, 2804x Boot ROM Reference Guide describes the purpose andfeatures of the bootloader (factory-programmed boot-loading software). It also describes
other contents of the device on-chip boot ROM and identifies where all of the information is

Device Support

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located within that memory.
Tools Guides
SPRU513
TMS320C28x Assembly Language Tools User's Guide describes the assembly language
tools (assembler and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the
TMS320C28x device.
SPRU514

TMS320C28x Optimizing C Compiler User's Guide describes the TMS320C28x™ C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320
DSP assembly language source code for the TMS320C28x device.

SPRU608

The TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,
available within the Code Composer Studio for TMS320C2000 IDE, that simulates the
instruction set of the C28x™ core.

SPRU625

TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide
describes development using DSP/BIOS.

Application Reports and Software
Key Links Include:
1. C2000 Get Started - www.ti.com/c2000getstarted
2. C2000 Digital Motor Control Software Library - www.ti.com/c2000appsw
3. C2000 Digital Power Supply Software Library - www.ti.com/dpslib
4. DSP Power Management Reference Designs - www.ti.com/dsppower
SPRAAM0

Getting Started With TMS320C28x™ Digital Signal Controllers is organized by development
flow and functional areas to make your design effort as seamless as possible. Tips on
getting started with C28x™ DSP software and hardware development are provided to aid inyour initial design and debug efforts. Each section includes pointers to valuable information
including technical documentation, software, and tools for use in each phase of design.

SPRA958

Running an Application from Internal Flash Memory on the TMS320F28xx DSP covers therequirements needed to properly configure application software for execution from on-chip
flash memory. Requirements for both DSP/BIOS™ and non-DSP/BIOS projects arepresented. Example code projects are included.

SPRAA85

Programming TMS320x28xx and 28xxx Peripherals in C/C++ explores a hardware
abstraction layer implementation to make C/C++ coding easier on 28x DSPs. This method iscompared to traditional #define macros and topics of code efficiency and special caseregisters are also addressed.

SPRAA88

Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x presents a method
for utilizing the on-chip pulse width modulated (PWM) signal generators on the
TMS320F280x family of digital signal controllers as a digital-to-analog converter (DAC).

SPRAA91

TMS320F280x DSC USB Connectivity Using TUSB3410 USB-to-UART Bridge Chip presents
hardware connections as well as software preparation and operation of the development
system using a simple communication echo program.

SPRAAH1

Using the Enhanced Quadrature Encoder Pulse (eQEP) Module provides a guide for the useof the eQEP module as a dedicated capture unit and is applicable to the TMS320x280x,
28xxx family of processors.

SPRAA58

TMS320x281x to TMS320x280x Migration Overview describes differences between the
Texas Instruments TMS320x281x and TMS320x280x DSPs to assist in application migrationfrom the 281x to the 280x. While the main focus of this document is migration from 281x to
280x, users considering migrating in the reverse direction (280x to 281x) will also find thisdocument useful.

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SPRAAI1

Using Enhanced Pulse Width Modulator (ePWM) Module for 0-100% Duty Cycle Control
provides a guide for the use of the ePWM module to provide 0% to 100% duty cycle control
and is applicable to the TMS320x280x family of processors.

SPRAAD5Power Line Communication for Lighting Apps using BPSK w/ a Single DSP Controller
presents a complete implementation of a power line modem following CEA-709 protocol
using a single DSP.

SPRAAD8

TMS320280x and TMS320F2801x ADC Calibration describes a method for improving theabsolute accuracy of the 12-bit ADC found on the TMS320280x and TMS3202801x devices.
Inherent gain and offset errors affect the absolute accuracy of the ADC. The methods
described in this report can improve the absolute accuracy of the ADC to levels better than
0.5%. This application report has an option to download an example program that executes
from RAM on the F2808 EzDSP.

SPRA820

Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology for
online stack overflow detection on the TMS320C28x™ DSP. C-source code is provided that
contains functions for implementing the overflow detection on both DSP/BIOS™ and
non-DSP/BIOS applications.

SPRA806

An Easy Way of Creating a C-callable Assembly Function for the TMS320C28x DSP
provides instructions and suggestions to configure the C compiler to assist with
understanding of parameter-passing conventions and environments expected by the Ccompiler.

Software
SPRC191

C280x, C2801x C/C++ Header Files and Peripheral Examples

SPRM194

F2801 100-Pin GGM/ZGM BSDL Model

SPRM195

F2801 100-Pin PZ BSDL Model

SPRM196F2806 100-Pin PZ BSDL Model

SPRM197

F2808 100-Pin PZ BSDL Model

SPRM198

F2808 100-Pin GGM/ZGM BSDL Model

SPRM200

F2806 100-Pin GGM/ZGM BSDL Model

SPRM244F2809 GGM/ZGM BSDL Model

SPRM245

F2809 PZ BSDL Model

A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, ispublished quarterly and distributed to update TMS320 DSP customers on product information.
Updated information on the TMS320 DSP controllers can be found on the worldwide web at:
http://www.ti.com.
To send comments regarding this data manual (literature number SPRS230), use thecomments@books.sc.ti.com email address, which is a repository for feedback. For questions and support,
contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.

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6

Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320F280x DSPs.

6.1

Absolute Maximum Ratings (1) (2)Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges.
Supply voltage range, VDDIO, VDD3VFL

with respect to VSS- 0.3 V to 4.6 V

Supply voltage range, VDDA2, VDDAIO

with respect to VSSA

- 0.3 V to 4.6 V

Supply voltage range, VDD

with respect to VSS- 0.3 V to 2.5 V

Supply voltage range, VDD1A18, VDD2A18

with respect to VSSA

- 0.3 V to 2.5 V

Supply voltage range, VSSA2, VSSAIO, VSS1AGND, VSS2AGND

with respect to VSS- 0.3 V to 0.3 V

Input voltage range, VIN- 0.3 V to 4.6 V

Output voltage range, VO- 0.3 V to 4.6 V

Input clamp current, IIK (VIN < 0 or VIN > VDDIO)± 20 mA(3)± 20 mA

Output clamp current, IOK (VO < 0 or VO > VDDIO)
Operating ambient temperature ranges,

Junction temperature range, Tj (4)Storage temperature range, Tstg
(1)
(2)
(3)
(4)

(4)

TA: A version (GGM, PZ) (4)- 40°C to 85°C

TA: S version (GGM, PZ) (4)- 40°C to 125°C

TA: Q version ( PZ) (4)- 40°C to 125°C- 40°C to 150°C- 65°C to 150°C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
Continuous clamp current per pin is ± 2 mA. This includes the analog inputs which have an internal clamping circuit that clamps thevoltage to a diode drop above VDDA2 or below VSSA2.
Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for
TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963)

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6.2

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN

NOM

MAX

UNIT

Device supply voltage, I/O, VDDIO

3.14

3.3

3.47

V

Device supply voltage CPU, VDD

1.71

1.8

1.89

V

Supply ground, VSS, VSSIO

0V

ADC supply voltage (3.3 V), VDDA2, VDDAIO

3.14

3.3

3.47

V

ADC supply voltage (1.8 V), VDD1A18, VDD2A18

1.71

1.8

1.89

V

Flash supply voltage, VDD3VFL

3.14

3.3

3.47

V

Device clock frequency (system clock), fSYSCLKOUT

100-MHz devices

2

100

MHz

60-MHz devices

2

60

MHz

2

VDDIO

High-level input voltage, VIH
Low-level input voltage, VIL
High-level output source current, VOH = 2.4 V, IOH
Low-level output sink current, VOL = VOL MAX, IOL

Ambient temperature, TA
(1)

6.3

V

0.8
All I/Os except Group 2-4Group 2 (1)-8All I/Os except Group 2

4Group 2

(1)

mA
mA

8

A version-40

85

S version

-40

125

Q version

-40

125

°C

Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, and EMU1Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER
VOH

High-level output voltage

VOL

Low-level output voltage

IIL

Input current(low level)

IIH

Input current(high level)

TEST CONDITIONSMINIOH = IOHMAX

TYP

MAX

2.4

IOH = 50 μA

V

VDDIO - 0.2

IOL = IOLMAX

0.4

Pin with pullup
enabledVDDIO = 3.3 V, VIN = 0 V

Pin with pulldown
enabledVDDIO = 3.3 V, VIN = 0 V±2

Pin with pullup
enabledVDDIO = 3.3 V, VIN = VDDIO±2

Pin with pulldown
enabledVDDIO = 3.3 V, VIN = VDDIO (F280x)

28

50

80

Pin with pulldown
enabledVDDIO = 3.3 V, VIN = VDDIO (C280x)

80

140

190

IOZ

Output current, pullup or
pulldown disabled

CI

Input capacitance

92

Electrical Specifications

All I/Os (including XRS)

-80

UNIT

-140

V

-190
μA

±2

VO = VDDIO or 0 V
2

μA

μA
pF

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6.4

Current Consumption
Table 6-1. TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz
SYSCLKOUT

MODE

TEST CONDITIONSIDDIO (1)IDD

IDDA18 (2)IDD3VFL

IDDA33 (3)TYP (4)MAX

TYP (4)

MAX

TYP

MAX

TYP (4)MAX

TYP (4)MAX

Operational(Flash)The following peripheral
clocks are enabled:•ePWM1/2/3/4/5/6•
eCAP1/2/3/4•
eQEP1/2•
eCAN-A•
SCI-A/B
•
SPI-A
•
ADC
•
I2C
All PWM pins are toggled
at 100 kHz.
All I/O pins are left
unconnected.
Data is continuouslytransmitted out of the
SCI-A, SCI-B, andeCAN-A ports. The
hardware multiplier is
exercised.
Code is running out offlash with 3 wait-states.
XCLKOUT is turned off.

195 mA

230 mA

15 mA

27 mA

35 mA

40 mA

30 mA

38 mA

1.5 mA

2 mA

IDLE

Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:•eCAN-A
•
SCI-A
•
SPI-A
•
I2C

75 mA

90 mA

500 μA

2 mA

2 μA

10 μA

5 μA

50 μA

15 μA

30 μA

STANDBY

Flash is powered down.
Peripheral clocks are off.

6 mA

12 mA

100 μA

500 μA

2 μA

10 μA

5 μA

50 μA

15 μA

30 μA

HALT

Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.

70 μA

60 μA

120 μA

2 μA

10 μA

5 μA

50 μA

15 μA

30 μA

(1)
(2)
(3)
(4)

IDDIO current is dependent on the electrical loading on the I/O pins.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
The TYP numbers are applicable over room temperature and nominal voltage.

NOTE
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done,
the current drawn by the device will be more than the numbers specified in the current
consumption tables.

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Table 6-2. TMS320F2806 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
MODE

TEST CONDITIONS

Operational(Flash)The following peripheral
clocks are enabled:•ePWM1/2/3/4/5/6•
eCAP1/2/3/4•
eQEP1/2•
eCAN-A•
SCI-A/B
•
SPI-A
•
ADC
•
I2C
All PWM pins are toggled at
100 kHz.
All I/O pins are left
unconnected.
Data is continuouslytransmitted out of the
SCI-A, SCI-B, and eCAN-A
ports. The hardware
multiplier is exercised.
Code is running out of flash
with 3 wait-states.
XCLKOUT is turned off

IDDIO (1)IDD3VFL

IDDA18 (2)IDDA33 (3)

MAX

TYP

(4)

MAX

TYP

(4)

MAX

TYP

(4)

MAX

15 mA

27 mA

35 mA

40 mA

30 mA

38 mA

1.5 mA

2 mA

90 mA

500 μA

2 mA

2 μA

10 μA

5 μA

50 μA

15 μA

30 μA

12 mA

100 μA

500 μA

2 μA

10 μA

5 μA

50 μA

15 μA

30 μA

60 μA

120 μA

2 μA

10 μA

5 μA

50 μA

15 μA

30 μA

IDD
MAX

TYP

(4)

195 mA

230 mA

IDLE

Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:•eCAN-A
•
SCI-A
•
SPI-A
•
I2C

75 mA

STANDBY

Flash is powered down.
Peripheral clocks are off.

6 mA

HALT

Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.

70 μA

(1)
(2)
(3)
(4)

TYP

(4)

IDDIO current is dependent on the electrical loading on the I/O pins.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
The TYP numbers are applicable over room temperature and nominal voltage.

NOTE
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done,
the current drawn by the device will be more than the numbers specified in the current
consumption tables.

94

Electrical Specifications

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Table 6-3. TMS320F2802, TMS320F2801 Current Consumption by Power-Supply Pins at 100-MHz
SYSCLKOUT
IDDIO (1)IDD3VFL

MAX

TYP

(4)

MAX

TYP

(4)

180 mA

210 mA

15 mA

27 mA

IDLE

Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:•eCAN-A
•
SCI-A
•
SPI-A
•
I2C

75 mA

90 mA

500 μA

STANDBY

Flash is powered down.
Peripheral clocks are off.

6 mA

12 mA

HALT

Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.

70 μA

MODE

TEST CONDITIONS

Operational(Flash)The following peripheral
clocks are enabled:•ePWM1/2/3•
eCAP1/2•
eQEP1•
eCAN-A
•
SCI-A
•
SPI-A
•
ADC
•
I2C
All PWM pins are toggled at
100 kHz.
All I/O pins are left
unconnected.
Data is continuouslytransmitted out of the SCI-A,
SCI-B, and eCAN-A ports.
The hardware multiplier is
exercised.
Code is running out of flash
with 3 wait-states.
XCLKOUT is turned off.

(1)
(2)
(3)
(4)

IDD
TYP

(4)

IDDA18 (2)

MAX

TYP

(4)

35 mA

40 mA

2 mA

2 μA

100 μA

500 μA

60 μA

120 μA

IDDA33 (3)

MAX

TYP

(4)

MAX

30 mA

38 mA

1.5 mA

2 mA

10 μA

5 μA

50 μA

15 μA

30 μA

2 μA

10 μA

5 μA

50 μA

15 μA

30 μA

2 μA

10 μA

5 μA

50 μA

15 μA

30 μA

IDDIO current is dependent on the electrical loading on the I/O pins.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
The TYP numbers are applicable over room temperature and nominal voltage.

NOTE
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done,
the current drawn by the device will be more than the numbers specified in the current
consumption tables.

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Table 6-4. TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at
100-MHz SYSCLKOUT
MODE

TEST CONDITIONSIDDIO (1)

IDD
TYP

(4)

MAX

TYP

(4)

IDDA18 (2)
MAX

TYP

(4)

IDDA33 (3)
MAX

TYP

(4)

MAX

Operational(ROM)

The following peripheral clocks
are enabled:•ePWM1/2/3•
eCAP1/2•
eQEP1•
eCAN-A
•
SCI-A
•
SPI-A
•
ADC
•
I2C
All PWM pins are toggled at
100 kHz.
All I/O pins are left unconnected.
Data is continuously transmitted
out of the SCI-A, SCI-B, andeCAN-A ports. The hardware
multiplier is exercised.
Code is running out of ROM with
3 wait-states.
XCLKOUT is turned off.

150 mA

165 mA

5 mA

10 mA

30 mA

38 mA

1.5 mA

2 mA

IDLE

XCLKOUT is turned off.
The following peripheral clocks
are enabled:•eCAN-A
•
SCI-A
•
SPI-A
•
I2C

75 mA

90 mA

500 μA

2 mA

5 μA

50 μA

15 μA

30 μA

STANDBY

Peripheral clocks are off.

6 mA

12 mA

100 μA

500 μA

5 μA

50 μA

15 μA

30 μA

HALT

Peripheral clocks are off.
Input clock is disabled.

70 μA

80 μA

120 μA

5 μA

50 μA

15 μA

30 μA

(1)
(2)
(3)
(4)

IDDIO current is dependent on the electrical loading on the I/O pins.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
The TYP numbers are applicable over room temperature and nominal voltage.

NOTE
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done,
the current drawn by the device will be more than the numbers specified in the current
consumption tables.

96

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6.4.1

Reducing Current Consumption
280x devices have a richer peripheral mix compared to the 281x family. While the McBSP has been
removed, the following new peripherals have been added on the 280x:• 3 SPI modules• 1 CAN module• 1 I2C module
The two event manager modules of the 281x have been enhanced and replaced with separate ePWM (6),eCAP (4) and eQEP (2) modules, providing tremendous flexibility in applications. Like 281x, 280x DSPs
incorporate a unique method to reduce the device current consumption. Since each peripheral unit has anindividual clock-enable bit, significant reduction in current consumption can be achieved by turning off theclock to any peripheral module that is not used in a given application. Furthermore, any one of the three
low-power modes could be taken advantage of to reduce the current consumption even further. Table 6-5
indicates the typical reduction in current consumption achieved by turning off the clocks.
Table 6-5. Typical Current Consumption by Various
Peripherals (at 100 MHz) (1)

(1)
(2)

PERIPHERALMODULEIDD CURRENT
REDUCTION (mA)

ADC

8 (2)

I2C

5

eQEP

5

ePWM

5

eCAP

2

SCI

4

SPI

5

eCAN

11

All peripheral clocks are disabled upon reset. Writing to/readingfrom peripheral registers is possible only after the peripheral clocks
are turned on.
This number represents the current drawn by the digital portion of
the ADC module. Turning off the clock to the ADC module results inthe elimination of the current drawn by the analog portion of the
ADC (IDDA18) as well.

NOTE
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
NOTE
The baseline IDD current (current when the core is executing a dummy loop with noperipherals enabled) is 110 mA, typical. To arrive at the IDD current for a given application,
the current-drawn by the peripherals (enabled by that application) must be added to thebaseline IDD current.

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6.4.2

Current Consumption Graphs
250.0

Current (mA)

200.0
150.0
100.0
50.0
0.0
10

20

30

40

50

60

70

80

90

100

SYSCLKOUT (MHz)IDD

IDDA18

1.8-V current

IDDIO

IDD3VFL

3.3-V current

Figure 6-1. Typical Operational Current Versus Frequency (F2808)
600.0
500.0

Device Power (mW)

400.0
300.0
200.0
100.0
0.0
10

20

30

40

50

60

70

80

90

100

SYSCLKOUT (MHz)TOTAL POWER

Figure 6-2. Typical Operational Power Versus Frequency (F2808)
NOTE
Typical operational current for 60-MHz devices can be estimated from Figure 6-1. For Idd
current alone, subtract the current contribution of non-existent peripherals after scaling theperipheral currents for 60 MHz. For example, to compute the current of F2801-60 device,
the contribution by the following peripherals must be subtracted from Idd : ePWM4/5/6,
eCAP3/4, eQEP2, SCI-B.

98

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6.5

Emulator Connection Without Signal Buffering for the DSP
Figure 6-3 shows the connection between the DSP and JTAG header for a single-processor configuration.
If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals
must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-3 shows
the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section.
6 inches or less

VDDIO

VDDIO

5

13
EMU0

EMU0

PD

14
EMU1

EMU1
4

2
TRST

TRST

GND

TMS

GND

TDI

GND

TDO

GND

TCK

GND

6

1
TMS

8

3
TDI

10

7
TDO

12

11
TCK
9
TCK_RETDSPJTAG Header

Figure 6-3. Emulator Connection Without Signal Buffering for the DSP

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6.6

Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten thesymbols, some of the pin names and other related terminology have been abbreviated as follows:

6.6.1

Lowercase subscripts and their
meanings:

Letters and symbols and their
meanings:

aaccess time

H

High

c

cycle time (period)

L

Low

d

delay time

V

Valid

f

fall timeX

Unknown, changing, or don't care levelhhold time

Z

High impedancerrise timesu

setup timettransition timevvalid timew

pulse duration (width)

General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.

100

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6.6.2

Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.

Tester Pin Electronics

42 Ω

Data Sheet Timing Reference Point

3.5 nH
Transmission LineZ0 = 50 Ω(Α)

Output
Under
Test
Device Pin(B)

4.0 pF1.85 pF

A.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at thedevice pin.

B.

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.

Figure 6-4. 3.3-V Test Load Circuit

6.6.3

Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 280x DSPs. Table 6-6 and Table 6-7 list the cycle times of various clocks.
Table 6-6. TMS320x280x Clock Table and Nomenclature (100-MHz Devices)
MIN

On-chip oscillator
clock
XCLKIN (1)SYSCLKOUTXCLKOUTHSPCLK (2)LSPCLK (2)ADC clock
(1)
(2)
(3)

tc(OSC), Cycle time

NOM

MAX

UNIT

28.6

50

ns

Frequency

20

35

MHz

tc(CI), Cycle time

10

250

ns

Frequency

4

100

MHz

tc(SCO), Cycle time

10

500

ns

Frequency

2

100

MHz

tc(XCO), Cycle time

10

2000

ns

Frequency

0.5

100

MHz

tc(HCO), Cycle time

10

100

MHz

100

MHz

50 (3)

Frequencytc(LCO), Cycle time10

Frequencyns

40 (3)
25 (3)

Frequencytc(ADCCLK), Cycle time

20 (3)

ns

80

ns
12.5

MHz

This also applies to the X1 pin if a 1.8-V oscillator is used.
Lower LSPCLK and HSPCLK will reduce device power consumption.
This is the default reset value if SYSCLKOUT = 100 MHz.

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Table 6-7. TMS320x280x Clock Table and Nomenclature (60-MHz Devices)
MIN
On-chip oscillator
clock
XCLKIN (1)SYSCLKOUTXCLKOUTHSPCLK (2)LSPCLK (2)ADC clock
(1)
(2)
(3)

102

tc(OSC), Cycle time
Frequencytc(CI), Cycle time
Frequencytc(SCO), Cycle time
Frequencytc(XCO), Cycle time
Frequencytc(HCO), Cycle time

Frequency

UNIT

50

ns
MHz

20

35
250

ns

4

60

MHz

16.67

500

ns

2

60

MHz

16.67

2000

ns

0.5

60

MHz

60

MHz

16.67

33.3 (3)30 (3)

16.67

Frequencytc(ADCCLK), Cycle time

MAX

16.67

Frequencytc(LCO), Cycle time

NOM

28.6

ns

66.7 (3)
15

(3)

ns
60

MHz

12.5

MHz

80

ns

This also applies to the X1 pin if a 1.8-V oscillator is used.
Lower LSPCLK and HSPCLK will reduce device power consumption.
This is the default reset value if SYSCLKOUT = 60 MHz.

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6.7

Clock Requirements and Characteristics
Table 6-8. Input Clock Frequency
PARAMETER

fx

Input clock frequency

MIN

MAX

UNIT

20

35

Crystal (X1/X2)

20

35

100-MHz device

4100

60-MHz device

4

External oscillator/clock
source (XCLKIN or X1 pin)fl

TYP

Resonator (X1/X2)

Limp mode SYSCLKOUT frequency range (with /2 enabled)

MHz

60
1-5

MHz

Table 6-9. XCLKIN (1) Timing Requirements - PLL EnabledNO.
C8tc(CI)

Cycle time, XCLKIN

MIN

MAX

UNIT

33.3

200

ns

C9

tf(CI)

Fall time, XCLKIN

6

ns

C10

tr(CI)

Rise time, XCLKIN

6

ns

C11

tw(CIL)

Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)

45

55

%

C12

tw(CIH)

Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)

45

55

%

(1)

This applies to the X1 pin also.

Table 6-10. XCLKIN (1) Timing Requirements - PLL DisabledNO.
C8tc(CI)

Cycle time, XCLKIN

C9tf(CI)

Fall time, XCLKIN

C10tr(CI)

Rise time, XCLKIN

MIN

MAX

UNIT

100-MHz device

10

250

ns

60-MHz device

16.67

250

Up to 20 MHz

6ns

20 MHz to 100 MHz

2ns

Up to 20 MHz

6ns

20 MHz to 100 MHz

2

ns

C11

tw(CIL)

Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)

45

55

%

C12

tw(CIH)

Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)

45

55

%

(1)

This applies to the X1 pin also.

The possible configuration modes are shown in Table 3-17.
Table 6-11. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2)NO.

PARAMETER
100-MHz device

1060-MHz device

16.67

TYP

MAX

UNIT

C1

tc(XCO)

Cycle time, XCLKOUT

C3

tf(XCO)

Fall time, XCLKOUT

C4

tr(XCO)

Rise time, XCLKOUT

C5

tw(XCOL)

Pulse duration, XCLKOUT low

H-2

H+2

ns

C6

tw(XCOH)

Pulse duration, XCLKOUT high

H-2

H+2

ns

(3)

cycles

tp
(1)
(2)
(3)

MIN

ns
2

ns

2

PLL lock timens131072tc(OSCCLK)

A load of 40 pF is assumed for these parameters.
H = 0.5tc(XCO)
OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.

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C10
C9

C8
XCLKIN(A)

C6

C3

C1

C4

C5

XCLKOUT(B)A.

The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown isintended to illustrate the timing parameters only and may differ based on actual configuration.

B.

XCLKOUT configured to reflect SYSCLKOUT.

Figure 6-5. Clock Timing

6.8

Power Sequencing
No requirements are placed on the power up/down sequence of the various power pins to ensure thecorrect reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffersof the I/O pins are powered prior to the 1.8-V transistors, it is possible for the output buffers to turn on,
causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD (core voltage)pins prior to or simultaneously with the VDDIO (input/output voltage) pins, ensuring that the VDD pins havereached 0.7 V before the VDDIO pins reach 0.7 V.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for tw(RSL1) after the input clock is stable (seeTable 6-13). This is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8 μs prior to VDD reaching 1.5 V. This is toenhance flash reliability.
Additionally it is recommended that no voltage larger than a diode drop (0.7 V) should be applied to any
pin prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal p-njunctions in unintended ways and produce unpredictable results.

6.8.1

Power Management and Supervisory Circuit Solutions
Table 6-12 lists the power management and supervisory circuit solutions for 280x DSPs. LDO selection
depends on the total power consumed in the end application. Go to www.power.ti.com for a complete listof TI power ICs or select TI DSP Power Solutions for links to the DSP Power Selection Guide(slub006a.pdf) and links to specific power reference designs.
Table 6-12. Power Management and Supervisory Circuit Solutions

SUPPLIER

TYPE

PART

DESCRIPTION

Texas Instruments

LDO

TPS767D301

Dual 1-A low-dropout regulator (LDO) with supply voltage supervisor (SVS)

Texas Instruments

LDO

TPS70202

Dual 500/250-mA LDO with SVS

Texas Instruments

LDO

TPS766xx

250-mA LDO with PG

Texas Instruments

SVS

TPS3808

Open Drain SVS with programmable delay

Texas Instruments

SVS

TPS3803

Low-cost Open-drain SVS with 5 μS delay

Texas Instruments

LDO

TPS799xx

200-mA LDO in WCSP package

Texas Instruments

LDO

TPS736xx

400-mA LDO with 40 mV of VDO

Texas Instruments

DC/DC

TPS62110High Vin 1.2-A dc/dc converter in 4x4 QFN package

Texas Instruments

DC/DC

TPS6230x

500-mA converter in WCSP package

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VDDIO, VDD3VFL
VDDA2, VDDAIO(3.3 V)
VDD, VDD1A18,
VDD2A18(1.8 V)XCLKIN

X1/X2

OSCCLK/8(A)XCLKOUTtOSCST

User-Code Dependenttw(RSL1)

XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control(Internal)td(EX)th(boot-mode)(B)

Boot-Mode
Pins

User-Code Execution Phase
User-Code Dependent

GPIO Pins as Input
Peripheral/GPIO Function
Based on Boot CodeBoot-ROM Execution Starts
I/O Pins(C)GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code DependentA.

Upon power up, SYSCLKOUT is OSCCLK/2. Since the XCLKOUTDIV bits in the XCLK register come up with a reset
state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT =OSCCLK/8 during this phase.

B.

After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (indebugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.

C.

See Section 6.8 for requirements to ensure a high-impedance state for GPIO pins during power-up.

Figure 6-6. Power-on Reset

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Table 6-13. Reset (XRS) Timing Requirements
MIN

NOM

MAX

UNIT

tw(RSL1) (1)Pulse duration, stable XCLKIN to XRS hightw(RSL2)

Pulse duration, XRS lowtw(WDRS)

Pulse duration, reset pulse generated bywatchdog

512tc(OSCCLK)

cyclestd(EX)

Delay time, address/data valid after XRS high32tc(OSCCLK)

cyclestOSCST(2)th(boot-mode)(1)(2)

Warm reset

8tc(OSCCLK)

cycles8tc(OSCCLK)

cyclesOscillator start-up time1

Hold time for boot-mode pins

10200tc(OSCCLK)

ms
cyclesIn addition to the tw(RSL1) requirement, XRS has to be low at least for 1 ms after VDD reaches 1.5 V.
Dependent on crystal/resonator and board design.
XCLKIN

X1/X2

OSCCLK/8

XCLKOUT

User-Code Dependent

OSCCLK * 5
tw(RSL2)
XRS
Address/Data/
Control(Internal)td(EX)
User-Code Execution(Don’t Care)

Boot-ROM Execution Starts
Boot-Mode
Pins

Peripheral/GPIO Function

User-Code Execution Phase

GPIO Pins as Inputth(boot-mode)(A)Peripheral/GPIO Function
User-Code Execution Starts

I/O Pins

User-Code Dependent

GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code DependentA.

After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (indebugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.

Figure 6-7. Warm Reset
Figure 6-8 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating
frequency, OSCCLK x 4.

106

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OSCCLK
Write to PLLCRSYSCLKOUTOSCCLK * 2

OSCCLK/2

OSCCLK * 4(Current CPU
Frequency)(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period(PLL Lock-up Time, tp) is131072 OSCCLK Cycles Long.)(Changed CPU Frequency)

Figure 6-8. Example of Effect of Writing Into PLLCR Register

6.9

General-Purpose Input/Output (GPIO)

6.9.1

GPIO - Output Timing
Table 6-14. General-Purpose Output Switching Characteristics
PARAMETERMIN

tr(GPO)

Rise time, GPIO switching low to highAll GPIOs

tf(GPO)

Fall time, GPIO switching high to low

All GPIOs

tfGPO

Toggling frequency, GPO pins

MAX

UNIT

8

ns

8

ns

25

MHz

GPIO

tf(GPO)tr(GPO)

Figure 6-9. General-Purpose Output Timing

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6.9.2

GPIO - Input Timing(A)

GPIO Signal

GPxQSELn = 1,0 (6 samples)

1

1

0

0

0

0

0

0

0

1

0

tw(SP)

0

0

1

1

1

1

1

1

1

1

1

Sampling Period determinedby GPxCTRL[QUALPRD](B)tw(IQSW)(SYSCLKOUT cycle * 2 * QUALPRD) * 5(C))

Sampling Window
SYSCLKOUTQUALPRD = 1(SYSCLKOUT/2)(D)

Output From
QualifierA.

This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value"n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin
will be sampled).

B.

The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.

C.

The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.

D.

In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles orgreater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.

Figure 6-10. Sampling Mode
Table 6-15. General-Purpose Input Timing Requirements
MIN
tw(SP)

Sampling periodtw(IQSW)

Input qualifier sampling window

tw(GPI) (2)Pulse duration, GPIO low/high

(1)
(2)

108

MAX

UNIT

QUALPRD = 0

1tc(SCO)cyclesQUALPRD ≠ 0

2tc(SCO) * QUALPRD

cyclestw(SP) * (n (1) - 1)

cyclesSynchronous mode

2tc(SCO)cyclesWith input qualifiertw(IQSW) + tw(SP) + 1tc(SCO)

cycles"n" represents the number of qualification samples as defined by GPxQSELn register.
For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.

Electrical Specifications

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6.9.3

Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity ofthe signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0
XCLKOUTGPIOxntw(GPI)

Figure 6-11. General-Purpose Input Timing

The pulse-width requirement
XINT2_ADCSOC signal as well.

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for

NOTE
general-purpose

input

is

applicable

for

the

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6.9.4

Low-Power Mode Wakeup Timing
Table 6-16 shows the timing requirements, Table 6-17 shows the switching characteristics, andFigure 6-12 shows the timing diagram for IDLE mode.
Table 6-16. IDLE Mode Timing Requirements (1)MIN

tw(WAKE-INT)(1)

Pulse duration, external wake-up signal

Without input qualifier

NOM

MAX

2tc(SCO)With input qualifier

UNIT
cycles5tc(SCO) + tw(IQSW)

For an explanation of the input qualifier parameters, see Table 6-15.

Table 6-17. IDLE Mode Switching Characteristics (1)PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

20tc(SCO)

cyclesDelay time, external wake signal toprogram execution resume (2)td(WAKE-IDLE)•

Wake-up from Flash– Flash module in active state

Without input qualifier•

Wake-up from Flash– Flash module in sleep state

Without input qualifier

Wake-up from SARAM

Without input qualifier•

With input qualifier

20tc(SCO) + tw(IQSW)
1050tc(SCO)

With input qualifier

20tc(SCO)

With input qualifier(1)(2)

cycles1050tc(SCO) + tw(IQSW)
cycles20tc(SCO) + tw(IQSW)

For an explanation of the input qualifier parameters, see Table 6-15.
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggeredby the wake up) signal involves additional latency.
td(WAKE−IDLE)

Address/Data(internal)
XCLKOUT
tw(WAKE−INT)WAKE INT(A)A.

WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.

Figure 6-12. IDLE Entry and Exit Timing
Table 6-18. STANDBY Mode Timing Requirementstw(WAKE-INT)
(1)

110

Pulse duration, external
wake-up signal

TEST CONDITIONSMINWithout input qualification

3tc(OSCCLK)With input qualification (1)(2 + QUALSTDBY) * tc(OSCCLK)

NOM

MAX

UNIT
cyclesQUALSTDBY is a 6-bit field in the LPMCR0 register.

Electrical Specifications

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Table 6-19. STANDBY Mode Switching Characteristics
PARAMETERTEST CONDITIONSDelay time, IDLE instruction
executed to XCLKOUT lowtd(IDLE-XCOL)

MIN

TYP

32tc(SCO)

MAX

UNIT

45tc(SCO)

cyclesDelay time, external wake signal
to program execution resume (1)•td(WAKE-STBY)•

Wake up from flash– Flash module in activestateWithout input qualifier

Wake up from flash– Flash module in sleep
state

Without input qualifier

100tc(SCO)

With input qualifier

100tc(SCO) + tw(WAKE-INT)

With input qualifier

Wake up from SARAM

cycles1125tc(SCO)
1125tc(SCO) + tw(WAKE-INT)

Without input qualifier•(1)

cycles100tc(SCO)

With input qualifier

100tc(SCO) + tw(WAKE-INT)

cyclescyclesThis is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggeredby the wake up signal) involves additional latency.
(A)

(C)
(B)

DeviceStatusSTANDBY

(E)
(D)

(F)

STANDBY

Normal Execution

Flushing Pipeline
Wake−up
Signaltw(WAKE-INT)
td(WAKE-STBY)X1/X2 or
X1 or
XCLKINXCLKOUT
td(IDLE−XCOL)A.

IDLE instruction is executed to put the device into STANDBY mode.

B.

The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being
turned off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.

C.

Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.

D.

The external wake-up signal is driven active.

E.

After a latency period, the STANDBY mode is exited.

F.

Normal execution resumes. The device will respond to the interrupt (if enabled).

Figure 6-13. STANDBY Entry and Exit Timing Diagram
Table 6-20. HALT Mode Timing Requirements
MIN

NOM

MAX

UNIT

tw(WAKE-GPIO)

Pulse duration, GPIO wake-up signal

toscst + 2tc(OSCCLK) (1)cyclestw(WAKE-XRS)

Pulse duration, XRS wakeup signal

toscst + 8tc(OSCCLK)

cycles

(1)

See Table 6-13 for an explanation of toscst.

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Table 6-21. HALT Mode Switching Characteristics
PARAMETER

MIN

td(IDLE-XCOL)Delay time, IDLE instruction executed to XCLKOUT low

tp

PLL lock-up timetd(WAKE-HALT)

Delay time, PLL lock to program execution resume• Wake up from flash– Flash module in sleep state
•

TYP

MAX

UNIT

45tc(SCO)

cycles131072tc(OSCCLK)

cycles1125tc(SCO)

cycles35tc(SCO)

cycles32tc(SCO)

Wake up from SARAM

(A)

(C)

DeviceStatus(D)
HALT

Flushing Pipeline

(G)

(E)

(B)

(F)

HALT
PLL Lock-up Time
Wake-up Latency

NormalExecution

GPIOn
td(WAKE−HALT)
tw(WAKE-GPIO)

tp

X1/X2
or XCLKIN
Oscillator Start-up TimeXCLKOUT
td(IDLE−XCOL)A.

IDLE instruction is executed to put the device into HALT mode.

B.

The PLL block responds to the HALT signal. SYSCLKOUT is held for approximately 32 cycles before the oscillator isturned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending
operations to flush properly.

C.

Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power.

D.

When the GPIOn pin is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The
GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock
signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup
procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode.

E.

When GPIOn is deactivated, it initiates the PLL lock sequence, which takes 131,072 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles.

F.

When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.

G.

Normal operation resumes.

Figure 6-14. HALT Wake-Up Using GPIOn

112

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6.10 Enhanced Control Peripherals
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1-6. Table 6-22 shows the PWM timing requirements andTable 6-23, switching characteristics.
Table 6-22. ePWM Timing Requirements (1)TEST CONDITIONStw(SYCIN)

Sync input pulse width

MIN

Asynchronous

(1)

UNIT
cycles2tc(SCO)cycles1tc(SCO) + tw(IQSW)

cyclesSynchronous
With input qualifierMAX

2tc(SCO)For an explanation of the input qualifier parameters, see Table 6-15.

Table 6-23. ePWM Switching Characteristics
PARAMETER
tw(PWM)

Pulse duration, PWMx output high/lowtw(SYNCOUT)

Sync output pulse widthtd(PWM)tza

Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced lowtd(TZ-PWM)HZ

Delay time, trip input active to PWM Hi-Z

TEST CONDITIONS

MIN

MAX

UNIT

20

ns

8tc(SCO)cyclesno pin load

25

ns

20

ns

6.10.2 Trip-Zone Input Timing
XCLKOUT(A)

tw(TZ)TZ
td(TZ-PWM)HZPWM(B)A.

TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6

B.

PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.

Figure 6-15. PWM Hi-Z Characteristics
Table 6-24. Trip-Zone input Timing Requirements (1)MIN
tw(TZ)

Pulse duration, TZx input low

UNIT

1tc(SCO)cyclesSynchronous

2tc(SCO)cycles1tc(SCO) + tw(IQSW)

cyclesWith input qualifier
(1)

MAX

Asynchronous

For an explanation of the input qualifier parameters, see Table 6-15.

Table 6-25 shows the high-resolution PWM switching characteristics.

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Table 6-25. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
MIN

TYP

MAX

UNIT

150

310

ps

Micro Edge Positioning (MEP) step size (1)(1)

Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.

Table 6-26 shows the eCAP timing requirement and Table 6-27 shows the eCAP switching characteristics.
Table 6-26. Enhanced Capture (eCAP) Timing Requirement (1)TEST CONDITIONS
tw(CAP)

Capture input pulse width

MIN

UNIT

Asynchronous

2tc(SCO)cyclesSynchronous

2tc(SCO)cycles1tc(SCO) + tw(IQSW)

cyclesWith input qualifier
(1)

MAX

For an explanation of the input qualifier parameters, see Table 6-15.

Table 6-27. eCAP Switching Characteristics
PARAMETER
tw(APWM)TEST CONDITIONS

MIN

Pulse duration, APWMx output high/low

MAX

20

UNIT
ns

Table 6-28 shows the eQEP timing requirement and Table 6-29 shows the eQEP switching
characteristics.
Table 6-28. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1)TEST CONDITIONS
tw(QEPP)QEP input period

Asynchronous/synchronous
With input qualifiertw(INDEXH)QEP Index Input High timetw(INDEXL)QEP Index Input Low time
QEP Strobe High timetw(STROBL)QEP Strobe Input Low timecycles2tc(SCO)cycles2tc(SCO) +tw(IQSW)

cycles2tc(SCO)cycles2tc(SCO) + tw(IQSW)

cycles2tc(SCO)cycles2tc(SCO) + tw(IQSW)

cycles2tc(SCO)cycles2tc(SCO) +tw(IQSW)

cyclesAsynchronous/synchronous
With input qualifier(1)

cyclesAsynchronous/synchronous
With input qualifier

UNIT

2tc(SCO)Asynchronous/synchronous
With input qualifierMAX

2(1tc(SCO) + tw(IQSW))Asynchronous/synchronous
With input qualifier

tw(STROBH)

MIN

For an explanation of the input qualifier parameters, see Table 6-15.

Table 6-29. eQEP Switching Characteristics
MAX

UNIT

td(CNTR)xin

Delay time, external clock to counter increment

PARAMETERTEST CONDITIONS

MIN

4tc(SCO)cyclestd(PCS-OUT)QEP

Delay time, QEP input edge to position compare sync output

6tc(SCO)cyclesMAX

UNIT

Table 6-30. External ADC Start-of-Conversion Switching Characteristics
PARAMETER
tw(ADCSOCAL)

114

Pulse duration, ADCSOCAO low

Electrical Specifications

MIN
32tc(HCO)

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tw(ADCSOCAL)ADCSOCAOorADCSOCBO

Figure 6-16. ADCSOCAO or ADCSOCBO Timing

6.10.3 External Interrupt Timingtw(INT)
XNMI, XINT1, XINT2
td(INT)
Address bus(internal)

Interrupt Vector

Figure 6-17. External Interrupt Timing
Table 6-31. External Interrupt Timing Requirements (1)TEST CONDITIONS
tw(INT) (2)(1)(2)

Pulse duration, INT input low/high

MIN

MAX

UNIT

Synchronous

1tc(SCO)cyclesWith qualifier

1tc(SCO) + tw(IQSW)

cyclesFor an explanation of the input qualifier parameters, see Table 6-15.
This timing is applicable to any GPIO pin configured for ADCSOC functionality.

Table 6-32. External Interrupt Switching Characteristics (1)PARAMETER
td(INT)(1)

Delay time, INT low/high to interrupt-vector fetch

MIN

MAX

UNIT

tw(IQSW) + 12tc(SCO)

cyclesFor an explanation of the input qualifier parameters, see Table 6-15.

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6.10.4 I2C Electrical Specification and Timing
Table 6-33. I2C Timing
TEST CONDITIONSMIN

I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler andclock divider registers are configured
appropriately

MAX

UNIT

400

kHz

0.3 VDDIOVfSCL

SCL clock frequency

vil

Low level input voltage

VihHigh level input voltage

Vhys

Input hysteresisVol

Low level output voltage

3 mA sink current

tLOW

Low period of SCL clock

I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler andclock divider registers are configured
appropriately

1.3

μs

tHIGH

High period of SCL clock

I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler andclock divider registers are configured
appropriately

0.6

μs

lI

Input current with an input voltage
between 0.1 VDDIO and 0.9 VDDIO MAX

0.7 VDDIO

V

0.05 VDDIO
0

-10

V
0.4

10

V

μA

6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing
Table 6-34 lists the master mode timing (clock phase = 0) and Table 6-35 lists the timing (clockphase = 1). Figure 6-18 and Figure 6-19 show the timing waveforms.

116

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Table 6-34. SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
NO.

MIN

MAX

5tc(LCO)

127tc(LCO)

ns

Pulse duration, SPICLK high(clock polarity = 0)

0.5tc(SPC)M -10

0.5tc(SPC)M

0.5tc(SPC)M - 0.5tc(LCO) - 10

0.5tc(SPC)M - 0.5tc(LCO)

ns

tw(SPCL)M

Pulse duration, SPICLK low(clock polarity = 1)

0.5tc(SPC)M - 10

0.5tc(SPC)M

0.5tc(SPC)M - 0.5tc(LCO) - 10

0.5tc(SPC)M - 0.5tc(LCO)

tw(SPCL)M

Pulse duration, SPICLK low(clock polarity = 0)

0.5tc(SPC)M - 10

0.5tc(SPC)M

0.5tc(SPC)M + 0.5tc(LCO)-10

0.5tc(SPC)M + 0.5tc(LCO)

tw(SPCH)M

Pulse duration, SPICLK high(clock polarity = 1)

0.5tc(SPC)M - 10

0.5tc(SPC)M

0.5tc(SPC)M + 0.5tc(LCO)- 10

0.5tc(SPC)M + 0.5tc(LCO)

td(SPCH-SIMO)M

Delay time, SPICLK high to SPISIMO
valid (clock polarity = 0)1010td(SPCL-SIMO)M

Delay time, SPICLK low to SPISIMO
valid (clock polarity = 1)

10

10

tv(SPCL-SIMO)M

Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)

0.5tc(SPC)M -10

0.5tc(SPC)M + 0.5tc(LCO) -10

tv(SPCH-SIMO)M

Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)

0.5tc(SPC)M -10

0.5tc(SPC)M + 0.5tc(LCO) -10

tsu(SOMI-SPCL)M

Setup time, SPISOMI before SPICLK
low (clock polarity = 0)

35

35

ns

tsu(SOMI-SPCH)M

Setup time, SPISOMI before SPICLK
high (clock polarity = 1)

35

35

ns

tv(SPCL-SOMI)M

Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)0.25tc(SPC)M -10

0.5tc(SPC)M- 0.5tc(LCO)- 10tv(SPCH-SOMI)M

Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)

0.25tc(SPC)M - 10

0.5tc(SPC)M- 0.5tc(LCO)- 10

2

tw(SPCH)M

8

9

(5)

MAX
128tc(LCO)

Cycle time, SPICLK

5

UNIT

MIN
tc(SPC)M

4

SPI WHEN (SPIBRR + 1) IS ODDAND SPIBRR > 3

4tc(LCO)

1

3

(1)
(2)
(3)
(4)

SPI WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2

ns

ns

ns

The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
tc(LCO) = LSPCLK cycle time
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).

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1
SPICLK(clock polarity = 0)2
3
SPICLK(clock polarity = 1)
4
5
SPISIMO

Master Out Data Is Valid
8
9

SPISOMI

Master In Data
Must Be Valid

SPISTE(A)A.

In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of theword, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE
stays active between back-to-back transmit words in both FIFO and nonFIFO modes.

Figure 6-18. SPI Master Mode External Timing (Clock Phase = 0)

118

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Table 6-35. SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5)NO.

5tc(LCO)

127tc(LCO)

ns

Pulse duration, SPICLK high (clock
polarity = 0)

0.5tc(SPC)M -10

0.5tc(SPC)M

0.5tc(SPC)M - 0.5tc (LCO)-10

0.5tc(SPC)M - 0.5tc(LCO)

ns

tw(SPCL))M

Pulse duration, SPICLK low (clock
polarity = 1)

0.5tc(SPC)M -10

0.5tc(SPC)M

0.5tc(SPC)M - 0.5tc (LCO)-10

0.5tc(SPC)M - 0.5tc(LCO

ns

tw(SPCL)M

Pulse duration, SPICLK low (clock
polarity = 0)

0.5tc(SPC)M -10

0.5tc(SPC)M

0.5tc(SPC)M + 0.5tc(LCO) - 10

0.5tc(SPC)M + 0.5tc(LCO)

ns

tw(SPCH)M

Pulse duration, SPICLK high (clock
polarity = 1)

0.5tc(SPC)M -10

0.5tc(SPC)M

0.5tc(SPC)M + 0.5tc(LCO) -10

0.5tc(SPC)M + 0.5tc(LCO)

nstsu(SIMO-SPCH)M

Setup time, SPISIMO data valid
before SPICLK high (clock polarity= 0)

0.5tc(SPC)M -10

0.5tc(SPC)M - 10

nstsu(SIMO-SPCL)M

Setup time, SPISIMO data valid
before SPICLK low (clock polarity =1)

0.5tc(SPC)M -10

0.5tc(SPC)M - 10

nstv(SPCH-SIMO)M

Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)

0.5tc(SPC)M -10

0.5tc(SPC)M - 10

nstv(SPCL-SIMO)M

Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)

0.5tc(SPC)M -10

0.5tc(SPC)M -10

nstsu(SOMI-SPCH)M

Setup time, SPISOMI before
SPICLK high (clock polarity = 0)

35

35

ns

tsu(SOMI-SPCL)M

Setup time, SPISOMI before
SPICLK low (clock polarity = 1)

35

35

ns

tv(SPCH-SOMI)M

Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)0.25tc(SPC)M -10

0.5tc(SPC)M -10

nstv(SPCL-SOMI)M

Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)

0.25tc(SPC)M -10

0.5tc(SPC)M -10ns

2

tw(SPCH)M

7

10

11

(4)
(5)

MAX
128tc(LCO)

Cycle time, SPICLK

MIN

UNIT

MIN
tc(SPC)M

6

SPI WHEN (SPIBRR + 1) IS ODDAND SPIBRR > 3

4tc(LCO)

1

3

(1)
(2)
(3)

SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2

MAX

The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

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1
SPICLK(clock polarity = 0)2
3
SPICLK(clock polarity = 1)
6
7
SPISIMO

Master Out Data Is Valid

Data Valid

10
11
Master In Data Must
Be Valid

SPISOMISPISTE(A)A.

In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of theword, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE
stays active between back-to-back transmit words in both FIFO and nonFIFO modes.

Figure 6-19. SPI Master Mode External Timing (Clock Phase = 1)

6.10.6 SPI Slave Mode Timing
Table 6-36 lists the slave mode external timing (clock phase = 0) and Table 6-37 (clock phase = 1).
Figure 6-20 and Figure 6-21 show the timing waveforms.
Table 6-36. SPI Slave Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
NO.

MIN

MAX

12

tc(SPC)SCycle time, SPICLK

13

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 0)

0.5tc(SPC)S - 10

0.5tc(SPC)S

ns

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 1)

0.5tc(SPC)S - 10

0.5tc(SPC)S

ns

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 0)

0.5tc(SPC)S - 10

0.5tc(SPC)S

ns

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 1)

0.5tc(SPC)S - 10

0.5tc(SPC)S

ns

td(SPCH-SOMI)S

Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)35

nstd(SPCL-SOMI)S

Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)35

nstv(SPCL-SOMI)S

Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0)0.75tc(SPC)S

ns

tv(SPCH-SOMI)S

Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1)

0.75tc(SPC)Sns

tsu(SIMO-SPCL)S

Setup time, SPISIMO before SPICLK low (clock polarity = 0)35

nstsu(SIMO-SPCH)S

Setup time, SPISIMO before SPICLK high (clock polarity = 1)35

nstv(SPCL-SIMO)S

Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0)

0.5tc(SPC)S-10

ns

tv(SPCH-SIMO)S

Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1)

0.5tc(SPC)S-10

ns

14
15
16
19
20

(1)
(2)
(3)
(4)
(5)

120

4tc(LCO)UNIT
ns

The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

Electrical Specifications

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12
SPICLK(clock polarity = 0)13
14
SPICLK(clock polarity = 1)
15
16
SPISOMISPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be ValidSPISIMOSPISTE(A)A.

In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clockedge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.

Figure 6-20. SPI Slave Mode External Timing (Clock Phase = 0)
Table 6-37. SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4)
NO.

MIN

MAX

tc(SPC)SCycle time, SPICLK

13

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 0)

0.5tc(SPC)S - 10

0.5tc(SPC)S

ns

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 1)

0.5tc(SPC)S - 10

0.5tc(SPC)S

ns

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 0)

0.5tc(SPC)S - 10

0.5tc(SPC)S

ns

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 1)

0.5tc(SPC)S - 10

0.5tc(SPC)Sns

tsu(SOMI-SPCH)S

Setup time, SPISOMI before SPICLK high (clock polarity = 0)0.125tc(SPC)Sns

tsu(SOMI-SPCL)S

Setup time, SPISOMI before SPICLK low (clock polarity = 1

0.125tc(SPC)S

ns

tv(SPCH-SOMI)S

Valid time, SPISOMI data valid after SPICLK low (clock polarity =0)0.75tc(SPC)S

ns

tv(SPCL-SOMI)S

Valid time, SPISOMI data valid after SPICLK high(clock polarity = 1)

0.75tc(SPC)Sns

tsu(SIMO-SPCH)S

Setup time, SPISIMO before SPICLK high (clock polarity = 0)35

nstsu(SIMO-SPCL)S

Setup time, SPISIMO before SPICLK low (clock polarity = 1)35

nstv(SPCH-SIMO)S

Valid time, SPISIMO data valid after SPICLK high(clock polarity = 0)

0.5tc(SPC)S-10

ns

tv(SPCL-SIMO)S

Valid time, SPISIMO data valid after SPICLK low (clock polarity =1)

0.5tc(SPC)S-10

ns

14
17
18

21
22

(1)
(2)
(3)
(4)

8tc(LCO)

UNIT

12

ns

The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

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12
SPICLK(clock polarity = 0)13
14
SPICLK(clock polarity = 1)
17
18
SPISOMISPISOMI Data Is Valid

Data Valid

21
22
SPISIMOSPISIMO Data
Must Be Valid

SPISTE(A)A.

In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge andremain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.

Figure 6-21. SPI Slave Mode External Timing (Clock Phase = 1)

122

Electrical Specifications

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6.10.7 On-Chip Analog-to-Digital Converter
Table 6-38. ADC Electrical Characteristics (over recommended operating conditions) (1) (2)PARAMETER

MIN

TYP

MAX

UNIT

DC SPECIFICATIONSResolution

12

ADC clockBits

60-MHz device

0.001

7.5

MHz

100-MHz device

0.001

12.5

MHz

100-MHz device (F2809 only)

0.001

25

ACCURACY
INL (Integral nonlinearity)

1-12.5 MHz ADC clock (6.25 MSPS)
12.5-25 MHz ADC clock (12.5
MSPS)

DNL (Differential nonlinearity) (3)Offset error (4)

-60

LSB

±2

LSB

±1

LSB

+60

LSB

±4

Offset error with hardware trimming
Overall gain error with internal reference

±1.5

(5)

Overall gain error with external reference

LSB

-60

+60

LSB

-60

+60

LSB

Channel-to-channel offset variation

±4

LSB

Channel-to-channel gain variation

±4

LSB

ANALOG INPUT
Analog input voltage (ADCINx to ADCLO) (6)

0

ADCLO

-5

Input capacitance

0

3

V

5

mV

±5

μA

10

Input leakage current

pF

INTERNAL VOLTAGE REFERENCE (5)VADCREFP - ADCREFP output voltage at the pin based oninternal reference

1.275

V

VADCREFM - ADCREFM output voltage at the pin based oninternal reference

0.525

V

Voltage difference, ADCREFP - ADCREFM

0.75

V

50

PPM/°CADCREFSEL[15:14] = 11b

1.024

V

ADCREFSEL[15:14] = 10b

1.500

V

ADCREFSEL[15:14] = 01b

2.048

V

Temperature coefficient
EXTERNAL VOLTAGE REFERENCE (5) (7)VADCREFIN - External reference voltage input on ADCREFIN
pin 0.2% or better accurate reference recommended
AC SPECIFICATIONSSINAD (100 kHz) Signal-to-noise ratio + distortion

67.5

dB

SNR (100 kHz) Signal-to-noise ratio

68dB

THD (100 kHz) Total harmonic distortion

-79

dB

ENOB (100 kHz) Effective number of bits

10.9

Bits

83

dB

SFDR (100 kHz) Spurious free dynamic range
(1)
(2)
(3)
(4)
(5)

(6)
(7)

Tested at 12.5 MHz ADCCLK.
All voltages listed in this table are with respect to VSSA2.
TI specifies that the ADC will have no missing codes.
1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
A single internal/external band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error listed for the internal reference
is inclusive of the movement of the internal bandgap over temperature. Gain error over temperature for the external reference option will
depend on the temperature profile of the source used.
Voltages above VDDA + 0.3 V or below VSS - 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.
To avoid this, the analog inputs should be kept within these limits.
TI recommends using high precision external reference TI part REF3020/3120 or equivalent for 2.048-V reference.

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6.10.7.1 ADC Power-Up Control Bit Timing
ADC Power Up Delay

ADC Ready for ConversionsPWDNBGPWDNREFtd(BGR)PWDNADC
td(PWD)

Request for
ADC
Conversion

Figure 6-22. ADC Power-Up Control Bit Timing
Table 6-39. ADC Power-Up Delays
PARAMETER (1)td(BGR)

Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.

td(PWD)

Delay time for power-down control to be stable. Bit delay time for band-gap
reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0)
must be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3
register (PWDNADC)must be set to 1 before any ADC conversions are initiated.

(1)

MIN

20

TYP

MAX

UNIT

5

ms

1

ms

μs

50

Timings maintain compatibility to the 281x ADC module. The 280x ADC also supports driving all 3 bits at the same time and waitingtd(BGR) ms before first conversion.

Table 6-40. Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK) (1) (2)
VDDA18VDDA3.3

UNIT

Mode A (Operational Mode):

ADC OPERATING MODE••BG and REF enabled
PWD disabled

30

2

mA

Mode B:•••ADC clock enabled
BG and REF enabled
PWD enabled

9

0.5

mA

Mode C:•••ADC clock enabled
BG and REF disabled
PWD enabled

5

20

μA

Mode D:•••ADC clock disabled
BG and REF disabled
PWD enabled

5

15

μA

(1)

(2)

124

CONDITIONSTest Conditions:
SYSCLKOUT = 100 MHz
ADC module clock = 12.5 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
VDDA18 includes current into VDD1A18 and VDD2A18. VDDA3.3 includes current into VDDA2 and VDDAIO.

Electrical Specifications

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Rs

SourceSignalADCIN0Ron
1 kΩ

Switch

Cp
10 pF

ac

Ch
1.64 pF

28x DSP

Typical Values of the Input Circuit Components:
Switch Resistance (Ron):
Sampling Capacitor (Ch):
Parasitic Capacitance (Cp):
Source Resistance (Rs):

1 kΩ
1.64 pF
10 pF
50 Ω

Figure 6-23. ADC Analog Input Impedance Model
6.10.7.2 Definitions
Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC.
Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at
a time. These inputs are software-selectable.
Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate withlow power consumption.
Conversion Modes
The conversion can be performed in two different conversion modes:• Sequential sampling mode (SMODE = 0)
• Simultaneous sampling mode (SMODE = 1)

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6.10.7.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Axto Bx). The ADC can start conversions on event triggers from the ePWM, software trigger, or from anexternal ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on
every Sample/Hold pulse. The conversion time and latency of the Result register update are explained
below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The
selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse
width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Sample n+2
Sample n+1
Analog Input on
Channel Ax or Bx

Sample n

ADC ClockSample and HoldSH Pulse
SMODE Bittd(SH)

tdschx_n+1
tdschx_n

ADC Event Trigger fromePWM or Other SourcestSH

Figure 6-24. Sequential Sampling Mode (Single-Channel) Timing
Table 6-41. Sequential Sampling Mode Timing
SAMPLE n

SAMPLE n + 1

AT 12.5 MHz
ADC CLOCK,tc(ADCCLK) = 80 ns

td(SH)

Delay time from event trigger tosampling

2.5tc(ADCCLK)tSH

Sample/Hold width/Acquisition
Width(1 + Acqps) *tc(ADCCLK)

80 ns with Acqps = 0

td(schx_n)

Delay time for first result to appear
in Result register

4tc(ADCCLK)

320 nstd(schx_n+1)

Delay time for successive results toappear in Result register

126

Electrical Specifications(2 + Acqps) *tc(ADCCLK)REMARKS

Acqps value = 0-15
ADCTRL1[8:11]

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6.10.7.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, orfrom an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selectedchannels on every Sample/Hold pulse. The conversion time and latency of the result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register
update. The selected channels will be sampled simultaneously at the falling edge of the Sample/Holdpulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC
clocks wide (maximum).
NOTE
In simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,
and not in other combinations (such as A1/B3, etc.).
Sample n

Sample n+2

Sample n+1

Analog Input on
Channel Ax
Analog Input on
Channel Bx
ADC ClockSample and HoldSH Pulse
SMODE Bittd(SH)

tdschA0_n+1

tSH

ADC Event Trigger fromePWM or Other SourcestdschA0_ntdschB0_n+1

tdschB0_n

Figure 6-25. Simultaneous Sampling Mode Timing
Table 6-42. Simultaneous Sampling Mode Timing
SAMPLE n

SAMPLE n + 1

AT 12.5 MHz
ADC CLOCK,tc(ADCCLK) = 80 ns

td(SH)

Delay time from event trigger tosampling

2.5tc(ADCCLK)tSH

Sample/Hold width/Acquisition
Width(1 + Acqps) *tc(ADCCLK)

80 ns with Acqps = 0

td(schA0_n)

Delay time for first result toappear in Result register

4tc(ADCCLK)

320 nstd(schB0_n)

Delay time for first result toappear in Result register

5tc(ADCCLK)

400 nstd(schA0_n+1)

Delay time for successive results
to appear in Result register(3 + Acqps) * tc(ADCCLK)

240 nstd(schB0_n+1)

Delay time for successive results
to appear in Result register(3 + Acqps) * tc(ADCCLK)

240 nsSubmit Documentation Feedback

REMARKS

Acqps value = 0-15
ADCTRL1[8:11]

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6.11 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through fullscale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point isdefined as level one-half LSB beyond the last code transition. The deviation is measured from the centerof each particular code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal
value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as thedeviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The lasttransition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error isthe deviation of the actual difference between first and last code transitions and the ideal difference
between first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral
components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD isexpressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following(SINAD * 1.76)
N+
6.02
formula,it is possible to get a measure of performance expressed as N, the effective
number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency
can be calculated directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured
input signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.

128

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6.12 Flash Timing
Table 6-43. Flash Endurance
Nf

Flash endurance for the array (write/erase cycles)

NOTP OTP endurance for the array (write cycles)

0°C to 85°C (ambient)

MIN

TYP

100

1000

0°C to 85°C (ambient)

MAX

UNIT
cycles

1

write

MAX

UNIT

Table 6-44. Flash Parameters at 100-MHz SYSCLKOUT
PARAMETER (1)Program
Time

Erase TimeTEST CONDITIONS

MIN

TYP

16-Bit Word50

μs

16K Sector

500

ms

8K Sector

250

ms

4K Sector

125

ms

16K Sector

10S

8K Sector

10S

4K Sector

10

S

75

mA

IDD3VFLP

VDD3VFL current consumption during theErase/Program cycle

35

mA

IDDP

VDD current consumption during Erase/Program
cycle

140

mA

IDDIOP

VDDIO current consumption during Erase/Program
cycle

20

mA

(1)

Erase
Program

Typical parameters as seen at room temperature using flash API version 3.00 including function call overhead.

Table 6-45. Flash/OTP Access Timing
PARAMETER

MIN

TYP

MAX

UNIT

ta(fp)

Paged flash access time36

nsta(fr)

Random flash access time36

nsta(OTP)OTP access time

60

ns

Equations to compute the Flash page wait-state and random wait-state in Table 6-46 are as follows:
Flash Page Wait-State +ƪǒ Ǔ ƫƪǒ Ǔ ƫ
ta(fp)t c(SCO)Flash Random Wait-State +*1ta(fr)t c(SCO)(round up to the next highest integer) or 0, whichever is larger* 1 (round up to the next highest integer) or 1, whichever is larger

Equation to compute the OTP wait-state in Table 6-46 is as follows:
OTP Wait-State +ƪǒta(OTP)t c(SCO)Submit Documentation FeedbackǓ ƫ* 1 (round up to the next highest integer) or 1, whichever is larger

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Table 6-46. Minimum Required Flash/OTP Wait-States at Different Frequencies
SYSCLKOUT
(MHz)

(1)

SYSCLKOUT (ns)FLASH PAGE
WAIT-STATEFLASH RANDOM
WAIT-STATE (1)OTP WAIT-STATE

100

10

3

3

5

75

13.33

2

2

4

60

16.67

2

2

3

50

20

1

1

2

30

33.33

1

1

1

25

40

0

1

1

15

66.67

0

1

1

4

250

0

1

1

Random wait-state must be greater than or equal to 1.

6.13 ROM Timing (C280x only)
Table 6-47. ROM/OTP Access Timing
PARAMETER

MIN

TYP

MAX

UNIT

ta(rp)

Paged ROM access time19

nsta(rr)

Random ROM access time

19

nsta(ROM)

ROM (OTP area) access time (1)

60

ns

(1)

In C280x devices, a 1K X 16 ROM block replaces the OTP block found in Flash devices.

Equations to compute the page wait-state and random wait-state in Table 6-48 are as follows:
ROM Page Wait-State +ƪǒROM Random Wait-State +t a(rp)t c(SCO)

ƪǒ

Ǔ ƫ
*1

t a(rr)t c(SCO)(round up to the next highest integer) or 0, whichever is largerǓ ƫ* 1 (round up to the next highest integer) or 1, whichever is larger

Table 6-48. ROM/ROM (OTP area) Minimum Required
Wait-States at Different Frequencies
SYSCLKOUT(MHz)SYSCLKOUT
(ns)

PAGE
WAIT-STATERANDOM
WAIT-STATE (1)

100

10

1

1

75

13.33

1

1

50

20

0

1

30

33.33

0

1

25

40

0

1

15

66.67

0

1

4

250

0

1

(1)

130

Electrical Specifications

Random wait-state must be greater than or equal to 1.

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Migrating From F280x Devices to C280x Devices

7.1

Migration Issues
The migration issues to be considered while migrating from the F280x devices to C280x devices are as
follows:• The 1K OTP memory available in F280x devices has been replaced by 1K ROM C280x devices.
• Current consumption differs for F280x and C280x devices for all four possible modes. See theappropriate electrical section for exact numbers.
• The VDD3VFL pin is the 3.3-V Flash core power pin in F280x devices but is a VDDIO pin in C280x
devices.
• F280x and C280x devices are pin-compatible and code-compatible; however, they are electricallydifferent with different EMI/ESD profiles. Before ramping production with C280x devices, evaluate
performance of the hardware design with both devices.
• Addresses 0x3D 7BFC through 0x3D 7BFF in the OTP and addresses 0x3F 7FF0 through 0x3F 7FF5in the main ROM array are reserved for ROM part-specific information and are not available for user
applications.
• The paged and random wait-state specifications for the Flash and ROM parts are different. Whilemigrating from Flash to ROM parts, the same wait-state values must be used for best-performancecompatibility (for example, in applications that use software delay loops or where precise interrupt
latencies are critical).
•

The analog input switch resistance is smaller in C280x devices compared to F280x devices. Whilemigrating from a Flash to a ROM device care should be taken to design the analog input circuits tomeet the application performance required by the sampling network.
• The PART-ID register value is different for Flash and ROM parts.
• From a silicon functionality/errata standpoint, rev A ROM devices are equivalent to rev C flash devices.
See the errata applicable to 280x devices for details.
• As part of the ROM code generation process, all unused memory locations in the customer application
are automatically filled with 0xFFFF. Unused locations should not be manually filled with any otherdata.
For errata applicable to 280x devices, see the TMS320F280x, TMS320C280x, and TMS320F2801x DSP
Silicon Errata (literature number SPRZ171).

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Migrating From F280x Devices to C280x Devices

131

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

www.ti.com

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 20078

Mechanical Data
Table 8-1, Table 8-2, Table 8-3, and Table 8-4 show the thermal data.
The mechanical package diagram(s) that follow the tables reflect the most current released mechanicaldata available for the designated device(s).
Table 8-1. F280x Thermal Model 100-pin GGM Results
AIR FLOW
PARAMETER

0 lfm

150 lfm

250 lfm

θJA[°C/W] High k PCB

30.58

29.31

28.09

500 lfm
26.62

ΨJT[°C/W]

0.41840.32

0.37250.4887

θJC

12.08

θJB

16.46

Table 8-2. F280x Thermal Model 100-pin PZ Results
AIR FLOW
PARAMETER

0 lfm

150 lfm

250 lfm

500 lfm

θJA[°C/W] High k PCB

48.16

40.06

37.96

35.17

ΨJT[°C/W]

0.34250.85

1.0575

1.410

θJC

12.89

θJB

29.58

Table 8-3. C280x Thermal Model 100-pin GGM Results
AIR FLOW
PARAMETER

0 lfm

150 lfm

250 lfm

500 lfm

θJA[°C/W] High k PCB

36.33

35.01

33.81

32.31

ΨJT[°C/W]

0.57

0.43

0.52

0.67

θJC

14.18

θJB

21.36

Table 8-4. C280x Thermal Model 100-pin PZ Results
AIR FLOW
PARAMETER

0 lfm

150 lfm

250 lfm

500 lfm

θJA[°C/W] High k PCB

69.81

60.34

57.46

53.63

ΨJT[°C/W]

0.42

1.23

1.54

2.11

θJC

13.52

θJB

54.78

Table 8-5. F2809 Thermal Model 100-pin GGM Results
AIR FLOW

132

PARAMETER

0 lfm

150 lfm

250 lfm

500 lfm

θJA[°C/W] High k PCB

28.15

26.89

25.68

24.22

ΨJT[°C/W]

0.38

0.35

0.33

0.44

θJC

10.36

θJB

13.3

Mechanical Data

Submit Documentation Feedback

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

www.ti.com

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 8-6. F2809 Thermal Model 100-pin PZ Results
AIR FLOW
PARAMETER

0 lfm

150 lfm

250 lfm

500 lfm

θJA[°C/W] High k PCB

44.02

28.34

36.28

33.68

ΨJT[°C/W]

0.2

0.56

0.7

0.95

θJC

7.06

θJB

28.76

Submit Documentation Feedback

Mechanical Data

133

PACKAGE OPTION ADDENDUM
www.ti.com

18-Sep-2008

PACKAGING INFORMATION
Orderable Device

Status (1)Package
Type

Package
Drawing

Pins Package Eco Plan (2)Qty

Lead/Ball Finish

MSL Peak Temp (3)DMF2802PZA-60

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARDMPF2806PZA

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320C2801GGMA

ACTIVE

BGA

GGM

100

TBD

Call TI

Call TI

TMS320C2801GGMSACTIVEBGA

TMS320C2801PZA

ACTIVE

LQFP

GGM

100

TBD

Call TI

Call TI

PZ

100

TBD

Call TI

TMS320C2801PZQ

ACTIVE

LQFP

Call TI

PZ

100

TBD

Call TI

Call TI

TMS320C2801PZSACTIVE

LQFP

PZ

100

TBD

Call TI

Call TI

TMS320C2801ZGMAACTIVE

BGA MICROSTA
R

ZGM

100

TBD

Call TI

Call TI

TMS320C2801ZGMSACTIVE

BGA MICROSTA
R

ZGM

100

TBD

Call TI

Call TI

TMS320C2802GGMA

ACTIVE

BGA

GGM

100

TBD

Call TI

Call TI

TMS320C2802GGMSACTIVE

BGA

GGM

100

TBD

Call TI

Call TI

TMS320C2802PZA

ACTIVE

LQFP

PZ

100

TBD

Call TI

Call TI

TMS320C2802PZQ

ACTIVE

LQFP

PZ

100

TBD

Call TI

Call TI

TMS320C2802PZSACTIVE

LQFP

PZ

100

TBD

Call TI

Call TI

TMS320C2802ZGMAACTIVE

BGA MICROSTA
R

ZGM

100

TBD

Call TI

Call TI

TMS320C2802ZGMSACTIVE

BGA MICROSTA
R

ZGM

100

TBD

Call TI

Call TI

TMS320F28015PZA

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F28015PZQACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F28015PZSACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F28015ZGMAACTIVE

BGA MICROSTA
R

ZGM

100

184

Green (RoHS &no Sb/Br)

SNAGCU

Level-3-260C-168 HR

TMS320F28016PZA

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F28016PZQACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F28016PZSACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2801GGMA

ACTIVE

BGA

GGM

100

184

TBD

SNPB

Level-3-220C-168 HR

TMS320F2801GGMSACTIVE

BGA

GGM

100

184

TBD

SNPB

Level-3-220C-168 HR

TMS320F2801PZA

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2801PZA-60

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2801PZQ

ACTIVE

LQFP

PZ

100

90

Green (RoHS &CU NIPDAU

Level-2-260C-1 YEAR

Addendum-Page 1

PACKAGE OPTION ADDENDUM
www.ti.com

18-Sep-2008

Orderable Device

Status (1)Package
Type

Package
Drawing

Pins Package Eco Plan (2)Qty

Lead/Ball Finish

MSL Peak Temp (3)TMS320F2801PZSACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2801PZS-60

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2801ZGMAACTIVE

BGA MICROSTA
R

ZGM

100

184

Green (RoHS &no Sb/Br)

SNAGCU

Level-3-260C-168 HR

TMS320F2801ZGMSACTIVE

BGA MICROSTA
R

ZGM

100

184

Green (RoHS &no Sb/Br)

SNAGCU

Level-3-260C-168 HR

TMS320F2802GGMA

ACTIVE

BGA

GGM

100

184

TBD

SNPB

Level-3-220C-168 HR

TMS320F2802GGMSTMS320F2802PZA

ACTIVE

BGA

GGM

100

184

TBD

SNPB

Level-3-220C-168 HR

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2802PZA-60

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2802PZQ

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2802PZSACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2802PZS-60

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2802ZGMAACTIVE

BGA MICROSTA
R

ZGM

100

184

Green (RoHS &no Sb/Br)

SNAGCU

Level-3-260C-168 HR

TMS320F2802ZGMSACTIVE

BGA MICROSTA
R

ZGM

100

184

Green (RoHS &no Sb/Br)

SNAGCU

Level-3-260C-168 HR

TMS320F2806GGMA

ACTIVE

BGA

GGM

100

184

TBD

SNPB

Level-3-220C-168 HR

TMS320F2806GGMSACTIVE

BGA

GGM

100

184

TBD

SNPB

Level-3-220C-168 HR

TMS320F2806PZA

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2806PZQ

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2806PZSACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2806ZGMAACTIVE

BGA MICROSTA
R

ZGM

100

184

Green (RoHS &no Sb/Br)

SNAGCU

Level-3-260C-168 HR

TMS320F2806ZGMSACTIVE

BGA MICROSTA
R

ZGM

100

184

Green (RoHS &no Sb/Br)

SNAGCU

Level-3-260C-168 HR

TMS320F2808GGMA

ACTIVE

BGA

GGM

100

184

TBD

SNPB

Level-3-220C-168 HR

TMS320F2808GGMSACTIVE

BGA

GGM

100

184

TBD

SNPB

Level-3-220C-168 HR

TMS320F2808PZA

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2808PZQ

ACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2808PZSACTIVE

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEAR

no Sb/Br)

Addendum-Page 2

PACKAGE OPTION ADDENDUM
www.ti.com

18-Sep-2008

Orderable Device

Status (1)Package
Type

Package
Drawing

Pins Package Eco Plan (2)Qty

Lead/Ball Finish

MSL Peak Temp (3)TMS320F2808ZGMAACTIVE

BGA MICROSTA
R

ZGM

100

184

Green (RoHS &no Sb/Br)

SNAGCU

Level-3-260C-168 HR

TMS320F2808ZGMSACTIVE

BGA MICROSTA
R

ZGM

100

184

Green (RoHS &no Sb/Br)

SNAGCU

Level-3-260C-168 HR

TMS320F2809GGMA

ACTIVEBGA

GGM

TMS320F2809GGMSACTIVE

BGA

GGM

100

184

TBD

SNPB

Level-3-220C-168 HR

100

184

TBD

SNPB

TMS320F2809PZA

ACTIVE

LQFP

Level-3-220C-168 HR

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2809PZQ

ACTIVETMS320F2809PZSACTIVE

LQFP

PZ

100

90

TBD

Call TI

LQFP

PZ

100

90

Green (RoHS &no Sb/Br)CU NIPDAU

Level-2-260C-1 YEARTMS320F2809ZGMAACTIVE

BGA MICROSTA
R

ZGM

100

184

Green (RoHS &no Sb/Br)

SNAGCU

Level-3-260C-168 HR

TMS320F2809ZGMSACTIVE

BGA MICROSTA
R

ZGM

100

184

Green (RoHS &no Sb/Br)

SNAGCU

Level-3-260C-168 HR

Call TI(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHScompatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 3

MECHANICAL DATAMTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27
0,17

0,50
75

0,08 M

51

76

50

100

26

1

0,13 NOM

25
12,00 TYP

Gage Plane

14,20
SQ
13,80
16,20
SQ
15,80

0,05 MIN

1,45
1,35

0,25
0°– 7°

0,75
0,45
Seating Plane
0,08

1,60 MAX

4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

POST OFFICE BOX 655303• DALLAS, TEXAS 75265

1

MECHANICAL DATAMPBG028B FEBRUARY 1997 – REVISED MAY 2002

GGM (S–PBGA–N100)

PLASTIC BALL GRID ARRAY

10,10
SQ
9,90

7,20 TYP
0,80
0,40

K
0,80

J
H
G
F
E
0,40

D
C
B
A

A1 Corner

1

2

3

4

5

6

7

8

9

10

Bottom View

0,95
0,85

1,40 MAX

Seating Plane
0,55
0,45

0,08

0,45
0,35

0,10

4145257–3/C 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGA configuration.

POST OFFICE BOX 655303• DALLAS, TEXAS 75265

1

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