PTN5100
USB Type-C power delivery PHY and protocol IC
Rev. 1.1 — 25 July 2017

Product data sheet

1. General description
PTN5100 is a single port USB Type-C Power Delivery (PD) PHY and Protocol IC thatprovides Type-C Configuration channel interface and USB PD Physical and Protocol layer
functions to a System PD Port Policy Controller (Policy Engine and Device Policy
Manager, Alternate mode controller). It complies with USB PD[1] and Type-C[2]specifications and delta updates of PD spec. This IC is targeted for a wide range ofplatforms (Standard Notebook PCs, Desktop PCs, Chromebooks, Tablets, Convertibles,
Smart phones) and PC Accessories (e.g. Docks, Monitors, Cable adapters etc.)
applications. PTN5100 is architected to deliver robust performance, compliant behavior,configurability and system implementation flexibility that are essential to tide overinteroperability and compliance hurdles in the platform applications.
PTN5100 can support system realization of the following PD roles: (i) Provider (P) only, (ii)
Provider/Consumer (P/C) (iii) Consumer only (C) (iv) Consumer/Provider (C/P). Further, it
can be register programmed to operate in Type-C specific Upstream Facing Port (UFP),
Downstream Facing Port (DFP) or Dual Role Port (DRP) role.
PTN5100 implements VCONN low RON switch with register programmable Forward
Current protection feature. The VCON switch also provides Reverse current protection
feature to detect reverse current flow into the system whenever (inductive or) charged
cable is unplugged from the connector.
PTN5100 operates from platform power supply VDD, or it can also be powered from USB
power VBUS directly, which is especially required for operation under Dead Battery (DB)condition and certain platform use cases. The host interface operates on VIO supply tofacilitate interfacing to systems that use IO supply rail different from VDD supply rail.
It provides SPI/I2C interface for system host control/status update. The interface choice ispre- configured in NXP factory.
PTN5100 is available in a small footprint package option: HVQFN20 4 mm x 4 mm,
0.5 mm pitch.
Remark:1. The term 'EC' is used interchangeably with 'Embedded Controller', 'AP', 'Application
Processor' or 'System Management Controller, SMC' or System Host Controller
throughout this document.
2. The terms 'PMIC', 'Power Management Interface Controller', 'Charger IC' are usedinterchangeably throughout this document.

PTN5100

NXP Semiconductors

USB Type-C power delivery PHY and protocol IC

2. Features and benefits
2.1 USB PD and Type-C Features
Complies with USB PD[1] and USB Type-C[2] specifications.
 Supports implementation of various system PD roles: P, P/C, C, C/P Supports Type-C role configurability
 Type-C role (DFP, UFP, DRP) is Non-Volatile Memory (NVM) and register
programmable based on OEM platform requirements
 Implements UFP role pull down behavior to handle dead battery condition on
battery powered platforms
 Supports register programmable and variable ‘Rp’ indication (for DRP/DFP usage
and accessory detection)
 Implements 'Rd' indication on CC pin (for Device side implementation)
 CC detection/indication scheme based on Type-C role
 Indication of orientation detection via CC_ORIENT pin and status register(s) Debug and Audio Accessory detection and indication in status register(s) Cooperatively works under the control of Policy controller MCU for power delivery
negotiation and contract(s), Alternate mode and VDM exchanges
 Implements BMC (de)coding, 4B5B symbol (de)coding, CRC generation/checking,PD packet assembling/disassembling including Preamble, SOP, EOP, Good CRC
response, Retries, Hard and Cable resets
 PD PHY and Protocol layer interface control and status update handled via SPI/I2C
interface SOP* Configurability
 Register programmable to generate and receive SOP, SOP', SOP'-debug, SOP",
SOP"-debug'' in DFP/DRP (host use case) Register programmable to receive and respond on SOP, SOP'-debug and
SOP"-debug commands
 Supports low RON VCONN switch with enable/disable (Hi-Z) support
 Capable of maximum current delivery of 1 A over 2.7 V to 5.5 V
 Supports register programmable Forward current protection control
 Supports register programmable Reverse current protection

2.2 System protection features
 Back current protection on all pins when PTN5100 is unpowered CC1 and CC2 pins are 5.5 V tolerant
 VBUS pin and VBUS power path MOSFET enable pins are 28 V tolerant

2.3 General Delivers (active LOW enable) gate control signals for PMOS Power MOSFETs on
VBUS source and sink power paths
 Provides dedicated IO pin (CC_ORIENT) for indicating Cable/plug orientation and IO
pin (DBGACC_FOUND) for indicating Debug accessory detection
 Delivers up to 30 mA (max) for powering Policy controller MCU
 Supports SPI slave interface (SPI modes 1 and 2 supported) up to 30 MHz
PTN5100

Product data sheet

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USB Type-C power delivery PHY and protocol IC

 Supports I2C slave interface standard mode (100 kHz), Fast mode (400 kHz) and Fastmode plus (1 MHz) I2C Device slave address programmable up to 3 values
 Supports 3.3 V or 1.8 V capable I2C-bus or SPI interface
 Supports register access - device configuration, control and status/interrupt
interfacing through Slave I2C-bus interface
 Power supplies - VDD (3.3 V 10 %) or VBUS
 Tolerant up to 28 V on VBUS and operational up to maximum of 25 V on VBUS
 Operating temperature 20 C to 85 C
 ESD 8 kV HBM, 1 kV CDM
 Package: HVQFN20 4 mm  4 mm, 0.5 mm pitch

3. Applications
 PC platforms: Notebook PCs, Desktop PCs, Ultrabooks, Chromebooks
 Tablets, 2:1 Convertibles, Smartphones and Portable devices
 PC accessories/peripherals: Docking, Mobile Monitors, Multi-Function Monitors,
Portable/External hard drives, Cable adaptors, Dongles and accessories, etc.

4. Ordering information
Table 1.

Ordering information

Type number

Topsidemarking

Package
Name

Description

Version

PTN5100BS

5100

HVQFN20

plastic thermal enhanced very thin quad flat package;no leads; 20 terminals; body 4  4  0.85 mm[2]SOT917-4

PTN5100ABS

510A

HVQFN20

plastic thermal enhanced very thin quad flat package;no leads; 20 terminals; body 4  4  0.85 mm[3]SOT917-4[1]

Total height after printed-circuit board mounting <=1 mm (maximum)[2]

Supported system interface - SPI[3]Supported system interface - I2C

PTN5100

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USB Type-C power delivery PHY and protocol IC

4.1 Ordering options
Table 2.

Ordering options

Type number

Orderable
part number

Package

Packing method

Minimumorder quantity

Temperature

PTN5100BS

PTN5100BSMP

HVQFN20

Reel 13" Q2/T3
6000*standard mark SMD
dry pack

Tamb = 20 C to +85 C

PTN5100ABS

PTN5100ABSMP

HVQFN20

Reel 13" Q2/T3
6000*standard mark SMD
dry pack

Tamb = 20 C to +85 C

VBUS
VOLTAGESENSE
USB PDPHY

USB PD
PROTOCOL

EN_USBFET2

EN_USBFET1

EN_USBSRC

VDD
VIO
V_MCUPWR

BYPASS

VBUS

GND

5. Block diagram

FET
CONTROLANDSTATUSVBUS
LDO

SLV_ADDR
INT_N

CC1
CC2
CC_ORIENT
CC_CTRL1

CC
BLOCK

NVM

INTERNAL LDO AND
POWER DISTRIBUTION

DBGACC_FOUNDVCONN_IN

VCONN
SWITCHCURRENTPROTECTIONCONTROLREGISTERINTERFACEI2C SLAVEINTERFACESPI_CSSPI SLAVEINTERFACESPI_MISOSPI_CLK_I2C_SCL

SPI_MOSI_I2C_SDA

aaa-016429

Fig 1.

PTN5100 block diagram

PTN5100

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USB Type-C power delivery PHY and protocol IC

6. Pinning information

17 V_MCUPWR

16 SPI_MISO

18 VIO

terminal 1
index area

19 BYPASS

20 EN_USBFET2

6.1 Pinning

EN_USBFET1

1

15 VDDVBUS

214 SLV_ADDR

EN_USBSRC

3

CC2

4

12 SPI_MOSI_I2C_SDA

CC1

511 SPI_CLK_I2C_SCL
9

13 INT_N

CC_CTRL1 10

8
VCONN_IN

7
SPI_CS

CC_ORIENT

6DBGACC_FOUND

PTN5100

aaa-016428

Transparent top view

Note: HVQFN20 package ground is connected to exposed center pad. The exposed center pad
must be connected to platform supply ground for proper device operation. For enhanced thermal,
electrical, and board level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board and for proper heat conduction through the board,thermal vias need to be incorporated in the PCB in the thermal pad region.

Fig 2.

PTN5100

Product data sheet

Pin configuration for HVQFN20

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USB Type-C power delivery PHY and protocol IC

6.2 Pin description
Table 3.

Pin description

SymbolPin

Pin
Pin Type
direction

Description

EN_USBSRC

3

OutputUSB PD VBUS Source Power path PMOS FET gate
Active Low enable.

Open drain

At default/POR, this pin is Hi-Z; PTN5100 drives thispin LOW based on Type-C connection state and/or
policy controller MCU command.
The pin status can be read in the internal register(s).
EN_USBFET1

1

OutputOpen drain

USB PD VBUS Source or Sink Power path PMOS
FET gate Active Low enable.
At default/POR, this pin is Hi-Z; PTN5100 drives thispin LOW based on Type-C connection state and/or
policy controller MCU command.
The pin status can be read in the internal register(s).

EN_USBFET2

20

OutputOpen drain

USB PD VBUS Source or Sink Power path PMOS
FET gate Active Low enable.
At default/POR, this pin is Hi-Z; PTN5100 drives thispin LOW based on policy controller MCU command.
The pin status can be read in the internal register(s).

CC1

5

IO

Custom IO

Type-C Configuration channel #1
TVS or similar protection diode (e.g.
PESD5V0S1USF, PESD5V0S1UL, etc.) shall be
used to protect the CC1/2 pins fromovershoot/undershoot during cable plug/unplug andcable discharge events.

CC2

4

IO

Custom IO

Type-C Configuration channel #2
TVS protection diode (e.g. PESD5V0S1USF,
PESD5V0S1UL, etc) shall be used to protect theCC1/2 pins from overshoot/undershoot during cableplug/unplug and cable discharge events.

CC_ORIENT

9OutputCMOS IO on VIO power
railThis pin indicates Type-C cable plug orientation.
The pin's polarity is inverted at power-on reset and
the PD policy controller MCU has to initialize
PTN5100D before the pin level is valid. After the
initialization, the pin indicates orientation as follows:
LOW = Normal plug orientation (CCcommunication on CC1)
HIGH = Reverse plug orientation (CCcommunication on CC2)
Default pin value is LOW even if there is noconnection or normal plug connection

CC_CTRL1

10

DBGACC_ FOUND 6
VCONN_IN

PTN5100

Product data sheet

8

Input

Analog Input

Input to indicate whether to present ‘Rd’ or Open on
CC pin under Unpowered condition

OutputCMOS IO on VIO power
rail

Indicates the presence of Type-C Debug accessory

Power

VCONN power input from system side

Input

Default/POR value is LOW

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USB Type-C power delivery PHY and protocol IC

Table 3.

Pin description …continued

SymbolPin

Pin
Pin Type
direction

Description

SPI_MOSI_I2C_SDA

12

IO

Dual purpose pin. In I2C slave mode, this serves as
I2C data input/output (open drain)

Open drain IO (I2Cmode) referenced to VIO
voltage
V_MCUPWR power rail

In SPI slave mode, this pin serves Master Output
Slave Input function (push pull CMOS IO)(SPI mode)
SPI_MISO16

SPI_CLK_I2C_SCL 11

Output

V_MCUPWR railThis serves Master Input Slave Output function of
SPI interface

Input

Open drain IO (I2Cmode) referenced to VIO
voltage

Dual purpose pin. In I2C slave mode, this serves as
I2C clock input (open drain).
In SPI slave mode, it serves as SPI clock input pin

V_MCUPWR power rail
(SPI mode)
SPI_CS

7Input

V_MCUPWR railThis pin provides SPI chip select Input

INT_N

13

OutputOpen drain

Level triggered interrupt. Open drain output; This pin
needs to be externally pulled up VIO.
This pin is usable only when VDD is valid

SLV_ADDR

14

Ternary
input

V_MCUPWR rail

Ternary slave address (I2C) pin

V_MCUPWR

17

OutputPowerThis pin delivers current up to 30 mA (max) to policy
controller MCU. External supply de-coupling
capacitor(s) (2.2 F 10 % ceramic capacitor) are
required

VIO

18

Input

Power

IO domain power supply. External supply
de-coupling capacitor(s) are required

VBUS

2

Input

Power

VBUS power supply. External supply de-coupling
capacitor(s) are required

VDD

15

Input

Power

Core domain power supply. External supply
de-coupling capacitor(s) are required

BYPASS

19

Internal

Internal power rail

Internal power rail. A ceramic capacitor (2.2 F
10 %) is to be connected to this pin

GND

Centerpad

GND

Ground Center pad

7. Functional description
PTN5100 is a 1-port USB Type-C PD Physical and Protocol Layer IC that can be used torealize single or multi-port USB Type-C PD and/or Alternate mode implementations. It
complies with USB PD [1] and Type-C specifications [2]. PTN5100 supports the following
use configurations:
1. On a System Host (single or multi-port configuration)a. Controlled by a PD Policy controller and/or Alternate mode control MCU
b. Controlled by Embedded controller or Application processor
2. On a Device platform
PTN5100

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USB Type-C power delivery PHY and protocol IC

a. Controlled by a PD policy controller or Alternate mode control MCU or existingprocessor
On the host and device use cases, different PD roles are possible: (P), (P/C), (C), (C/P).
PTN5100 supports two levels of configurability and programmability:• NVM configuration options - configurability in the factory through NVM configuration
utility• I2C/SPI register programmable - read/write accesses at application/Firmware (FW)level
PTN5100 can be partitioned into the following major functional blocks along with theirrespective interfaces:• Type-C Configuration Channel functional block• USB Power Delivery function• VCONN Low RON Switch• Power FET Enable Control• MCU interface and Control
The following subsections describe the PTN5100 with its major functional blocks.

7.1 Type-C Configuration Channel functional block
Type-C Configuration Channel (CC) function operates as a front end to cable/pluginterface.
PTN5100 can operate autonomously or under MCU control. To support use cases
especially with autonomous mode, PTN5100 implements HW circuitry to perform thefollowing operations:• Applying 'Rp' or 'Rd' depending on the (NVM) configured role
• Detecting cable/plug connect and disconnect events• Indicating Type-C current limit level in a system under DFP role
• Detecting the current level supported by remote end under UFP role
• Identifying plug orientation and indicating through CC_ORIENT pin• Identifying Type-C Debug accessory detection and indicating through
DBGACC_FOUND pin• Updating event, interrupt and status registers and raising interrupt signal using INT_N
pin
In order to provide reliable connect/disconnect event triggers, debouncing is also
implemented as per [2].
PTN5100 allows for NVM configurability and/or register programmability to enable usage
under different platform configurations.

PTN5100

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USB Type-C power delivery PHY and protocol IC

7.2 USB Power Delivery Function
In general, the Embedded Controller (EC) or System Management Controller (SMC)
handles the overall Application/Platform power management given the system states,
battery status, etc. It reviews capabilities and status of various power providers (USB PD,
AC-DC adapter, battery, docking, etc.) dynamically and determines a specific source forpowering/charging the platform - the power source selection is an important and platform
dependent aspect of Application power delivery scheme.

• For example, in some computing applications, EC plays a central role in controllingthe various power sources including USB PD. To support this, PTN5100 and Policy
controller MCU can be configured to negotiate and agree on power contract based oncommand/response exchanges with EC• In several applications, EC may not even exist or EC wants to play a hands-off role.
To support these applications, PTN5100 and Policy controller MCU can be configured
to operate autonomously
In a Type-C PD implementation, the system partitioning involves the following parts:• Port PHY and Protocol layer functions  PTN5100• Port policy engine and device policy management, Alternate mode support Discrete policy controller MCU• System management  EC or SMC
PTN5100 implements USB PD PHY layer and HW intensive Protocol functions and it
works along with a discrete MCU to implement Full PD functionality. The combined 2-chipsystem solution (PTN5100 and MCU) can be configured to support one or more of thefollowing PD roles:
1. PD Consumer (C)
2. PD Consumer/Provider (C/P)
3. PD Provider (P)4. PD Provider/Consumer (P/C)
The interface between PTN5100 and Policy controller MCU can be either SPI or I2C.
PTN5100 provides a transparent set of commands and register interface for the MCU tocontrol the operation and ensure safe/suitable system behavior/response. PTN5100
Application Programming guide [3] describes the register set supported for the PD control,
status updates and operational control/sequences.
The policy controller MCU implements PD port policy layer as per [1]. The default PD
power profiles are configured in the MCU and the EC could request for specific profile and
PD contract based on platform application. The 2-chip solution can operate autonomouslyor under EC control.

PTN5100

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USB Type-C power delivery PHY and protocol IC

PTN5100(PORT PHY AND
PROTOCOL IC)DISCRETE MCU(PORT POLICYCONTROLLER)

EC OR SMC(SYSTEM POWER
MANAGEMENT)

aaa-016430

Fig 3.

PTN5100 to MCU

PTN5100(PORT PHY AND
PROTOCOL IC)

APPLICATION PROCESSOROR EC OR SMC (PD POLICYCONTROLLER AND SYSTEM
POWER MANAGEMENT
aaa-016431

Fig 4.

PTN5100 to EC

PTN5100 implements USB PD PHY layer function as follows:• Slew rate controlled IO• Bit transmission and data recovery• Bi-phase Mark Coding• 4B5B Line coding• CRC computation and checking
It handles the following Protocol layer functions:• Data Packetization and Extraction• Good CRC Response• Automated Retries• Hard reset, Cable reset• Tx and Rx buffer management
It handles both Transmit and Receive operation and it maintains dedicated TX and RX
data buffers. To minimize chances of collision, PTN5100 checks the CC line before start oftransmission. Once the data is transmitted or received, the I2C interface status is updated
and MCU is interrupted.
BIST mode (Tx, Rx) is also supported.
Note: NXP is open to engage on Firmware licensing to give a head start to customers on
USB PD Policy and Alternate mode Firmware front. Please contact NXP for further details.

7.3 VCONN Switch
Type-C specification defines a dedicated power pin VCONN_IN to deliver power to fullfeatured cables, dongles and cable adapters.

PTN5100

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USB Type-C power delivery PHY and protocol IC

PTN5100 implements very low RON switch that can deliver up to 1 A current. Dependingon the pin over which CC communication is established, VCONN power is delivered into
the other CC pin. With patented architecture, the switch implements Soft Start behavior to
avoid heavy inrush current flow.
The VCONN switch is to be used only when VCONN_IN lies within the valid range (2.7 V
to 5.5 V).
The VCONN switch can be enabled or disabled by Firmware. When in disabled condition,
it presents Hi-Z condition. The switch implements two important features related torobustness:• Forward Current Protection (FCP) that monitors over current condition (over current
limit is register programmable) and trips the connection by disabling the switch• Reverse Current Protection (RCP) that avoids reverse current flow back into thesystem due to inductive effects of cable unplug events
Further, both FCP and RCP circuitry shall be activated only when VCONN_IN is within
valid range.

7.3.1 Forward Current Protection (FCP)PTN5100 implements Forward current protection in VCONN switch that keeps monitoring
for a current flow above the preconfigured level from the system side and whenever thethreshold is exceeded, the switch is opened and an interrupt event is raised. The switch
remains open until the port controller MCU reads the status and re-enables the switch.

7.3.2 Reverse Current Protection (RCP)PTN5100 implements Reverse Current Protection in VCONN switch that watches for any
instantaneous reverse current flow back into the system via VCONN and whenever thepreconfigured threshold is exceeded, the switch is opened and an interrupt event israised. The switch remains open until the port controller MCU reads the status andre-enables the switch.

7.4 Power FET control
PTN5100 implements three dedicated open drain IOs that can be used to control theexternal power MOSFETs and enable/ disable VBUS source and sink power paths of thesystem. These are enabled or disabled based on PD power role (provider or consumer) of
the Type-C interface. Based on PD negotiation and contract, the policy controller MCU
enables/disables the specific power path (source FET or sink FETs).

• EN_USBSRC: This pin is used to enable/disable the power MOSFETs that
corresponds to VBUS source (e.g. 5V regulated output). The FET enable can be
configured and controlled through the register interface by the MCU. The pin status ismonitored and updated in a status register.

• EN_USBFET1: This pin is used to enable/disable the power MOSFETs that
corresponds to USB PD power from external power sources or delivering VBUS
power to external peripherals. Its specific use as a VBUS source or sink path control
is programmable. The FET enable can be configured and controlled through theregister interface by the MCU. The pin status is monitored and updated in a status
register.
PTN5100

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USB Type-C power delivery PHY and protocol IC• EN_USBFET2: This pin is used to enable/disable the power MOSFETs that
corresponds to USB PD power from external power sources or delivering VBUS
power to external peripherals. It specific use as a VBUS source or sink path control isprogrammable. The FET enable can be configured and controlled through the registerinterface by the MCU. The pin status is monitored and updated in a status register.

7.5 MCU interface and control
PTN5100 works along with policy controller MCU to realize USB PD functionality and/or
Alternate mode support. The MCU can control and interface with PTN5100 through a
dedicated I2C/SPI interface. In a given system implementation, only one of the twointerfaces (I2C, SPI) can be used. This selection can be static configured via NVM.
PTN5100 provides up to three I2C slave address combinations based on ternary pin(SLV_ADDR) setting as per the table below.
Table 4.

I2C slave address combinations

SLV_ADDR pin

Device address (Write/read)

GND

0xE0/0xE1

VDDIO

0xE4/0xE5

Unconnected

0xE8/0xE9

7.5.1 I2C-bus interface
PTN5100 has a slave I2C interface through which it provides a mechanism for control andstatus interaction/communication with the MCU. It supports Standard mode, Fast modeand Fast mode plus.
7.5.1.1

I2C writes
The following figure shows the basic protocol for I2C writes. A 16-bit offset is used toaddress each register.

S SLAVE ADDRESS[7:1] R/W ACK0

REG OFFSET[15:8]

ACK

REG OFFSET[7:0]

ACKDATA 0

ACK P
aaa-016432

Fig 5.

I2C writes

7.5.1.2

I2C reads
The following figure shows the basic protocol for I2C reads. They start off like I2C writes
by specifying a 16-bit register offset. This is followed by a repeat start condition, the Slave
Address (Read), and the read data.

S

SLAVE
ADDRESS[7:1]

R/W
ACK
0

REG
OFFSET[15:8]

ACK

REG
SLAVE
R/W
ACK
ACK SrOFFSET[7:0]
ADDRESS[7:1] 1

DATA 0

ACK P
aaa-016433

Fig 6.

I2C reads

PTN5100

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7.5.1.3

I2C address auto-incrementing
Bursts are allowed during writes and reads. Bit 15 of the register offset is theauto-increment indication. If ‘0’ then the internally generated MMIO address will notincrement with each data byte. If ‘1’, then the address will increment with each data byte.
A detailed description of the I2C-bus specification, with applications, is given in user
manual UM10204, "I2C-bus specification and user manual" [4]. Referring to I2C protocol,
PTN5100 positively acknowledges all 256 register offset addresses, though there arecertain undefined address offsets.

7.5.2 SPI interface
PTN5100 provides an SPI slave interface as well. It supports SPI modes 1 and 2. This
interface exposes same register interface as that of I2C. Its main advantage is fastercommand and data transport and relaxes MCU response time/latency requirements.

7.5.3 Register interface
PTN5100 Application programming guide [3] describes the various registers with their bit
definitions, POR values and the various functions. Also, sample 'C' programs
corresponding to various functions and operations are given. This guide can be used by
the platform system architects to implement the EC firmware to control the operations with
PTN5100. Refer to programming guide for more information. The register definitions arealso described in the guide.

7.5.4 Relevant Interface pins - SLV_ADDR, SPI_CLK_I2C_SCL,
SPI_MOSI_I2C_SDA, SPI_CS, SPI_MISO, INT_N• SLV_ADDR is a ternary input pin that is used to support up to 3 slave PTN5100
devices on a given platform. This pin can be pulled to V_MCUPWR rail, left open or
pulled to GND.

• While in SPI mode, SPI_CLK_I2C_SCL, SPI_MISO, SPI_MOSI_I2C_SDA andSPI_CS provide the necessary interface for connecting to SPI master controller on
the MCU.

• While in I2C mode, SPI_CLK_I2C_SCL and SPI_MOSI_I2C_SDA are used for I2C
clock and data interfacing to MCU• INT_N pin is used to raise Active LOW level triggered interrupt signal to EC. PTN5100
processes various events and raises interrupt that require SMC intervention. Once all
relevant events are processed by the MCU, the INT_N pin goes HIGH. At POR, thispin remains HIGH (when VIO is valid). The specific events that can generate theinterrupt can be selected.

7.6 Power supplies
PTN5100 is designed to operate under various power supplies. It can operate under bothnormal battery and dead battery environments (while drawing power from VBUS).
PTN5100 handles power supply transitions (VBUS, VDD) transparently and there is no
specific power supply ramp requirement imposed on the system (between VDD and VIO
rails) also.
The following table highlights the power supplies and operating conditions for PTN5100.

PTN5100

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USB Type-C power delivery PHY and protocol IC

Table 5.

Power supplies vs. operating conditions

Valid power supply
input combination

Operational condition

Remarks

VDD, VIO

Normal powered condition (both battery
based or non-battery based platforms)

All interfaces operational

VDD, VIO, VBUS

Normal powered condition; Host Platform
may be powered/charged through VBUS
simultaneously

All interfaces operational

VBUS,
VIO(=V_MCUPWR)

Dead battery in battery based platforms or
Normal powered condition under otherplatforms; Host Platform powered/charged
through USB PD

All interfaces operational

VBUS

Dead battery operation; PTN5100 draws
power from VBUS for its operation; Host
Platform may be powered/charged throughUSB PD later

PTN5100 pins
(dependent on VIO rail)
are not operational

Remark: The Policy controller MCU is powered by PTN5100.
The relevant pins associated with this functional block are:

• VDD
• VIO
• VBUS• V_MCUPWR• BYPASS

8. PTN5100 - Use case view
Given that USB Power Delivery could address the requirements of a wide set of markets
and product segments, PTN5100 is designed to work over a range of product categories,
platform applications, use cases and usage roles. With its configurability, it can be serve
the needs of both general and custom applications. Not limited to these but the following
subsections illustrate a set the use cases of PTN5100.

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USB Type-C power delivery PHY and protocol IC

8.1 System use cases
8.1.1 USB PD Provider/Consumer - Notebook/Ultrabook/Chromebook/Tablet PC
high-voltage
power FET

QUSB4

VIN

VBUS

5 V power FET

QUSB2

IADP+

QUSB1

RADP

5 V REG

IADP-

QUSB3

EN_USBFET2

EN_USBFET1

VCONN_IN

EN_USBSRC

POWER
NETWORKCHARGERICV_MCUPWR

I2C

EC/SMCI2C

BATTERY

CC_CTRL1

VBUS
BYPASSSPITYPE-CCONNECTOR

INT_N

PTN5100(PD PHY)

LPC1115MCU(PD POLICYAND ALT
MODECONTROLLER

V_MCUPWR

CC1
CC2

VIO
VDD

D+/-

USB2+/PCH

TX1+/USB3 TX+/RX1+/-

USB3 RX+/-CBTL08GP053
TX2+/RX2+/-(TYPE-C HIGH SPEED
SWITCH FOR USB 3.1,
4-LANE DP1.3 AND AUXSIDEBAND)DP[3:0]+/AUX+/-

RFU1/2CPU

HPD
aaa-016439

Fig 7.

Illustrative diagrams of Notebook/Ultrabook/Tablet application (Separate source and sink power paths):
PD Provider/Consumer role (DFP role under Normal power/battery; UFP role under dead battery
condition) 1 of 2

PTN5100

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USB Type-C power delivery PHY and protocol IC

NX20P5090(20 V/5 A power switch)
VIN

VBUS

RADP

NX5P3090

5 V REG

IADP-

IADP+

(5 V/3 A power switch)

EN_USBFET2

EN_USBSRC

EN_USBFET1

VCONN_IN

POWER
NETWORKCHARGERICV_MCUPWR

BATTERY

CC_CTRL1

VBUS
BYPASSSPITYPE-CCONNECTOR

INT_N

PTN5100(PD PHY)

I2C

EC/SMCSPI

LPC1115MCU(PD POLICYAND ALT
MODECONTROLLER

V_MCUPWR

CC1
CC2

VIO
VDD

USB2+/-

D+/I2C

PCH

TX1+/USB3 TX+/RX1+/-

USB3 RX+/-CBTL08GP053
TX2+/RX2+/-(TYPE-C HIGH SPEED
SWITCH FOR USB 3.1,
4-LANE DP1.3 AND AUXSIDEBAND)DP[3:0]+/AUX+/-

RFU1/2CPU

HPD
aaa-020081

Fig 8.

Illustrative diagram of Notebook/Ultrabook/Tablet application (Separate source and sink power paths):
PD Provider/Consumer role (DFP role under Normal power/battery; UFP role under dead battery
condition) 2 of 2

8.1.1.1

Brief description
In this illustration, the 2-chip solution (PTN5100 + Policy controller & Alternate mode
MCU) is behind the Type-C receptacle and it is configured as a PD Provider/ Consumer.
The EC interfaces with the Charger IC to configure at specific voltage/ current levels toperform battery charging and/or powering of the platform.
This application is expected to:

PTN5100

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PTN5100

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USB Type-C power delivery PHY and protocol IC• Source VBUS 5 V (if not under dead battery)• Charge from VBUS PD and AC barrel power, if applicable• Source VCONN power
The EC communicates with controller MCU via an I2C bus and control the operations.
The PTN5100 and MCU can operate autonomously or under the control of EC.
Figure 7 and Figure 8 illustrate the configurations with discrete MOSFETs and Powerswitches respectively. PTN5100 controls the power FETs/switch to determine charging(Green colored FETs/switch on VBUS power inputs) and 5 V VBUS power delivery(Orange colored FETs/switch on VBUS). If NXP5P3090 is used, then the Active HIGH
switch enable control is required to be generated based on the EN_USBSRC control
output.
An important aspect to consider here is that PTN5100 would indicate a 'Rd' pulldown(UFP) under dead battery condition and this enables the port partner to provide VBUS at
5 V (provided the port partner is capable of acting as DFP). However, after system starts
up, role swap has to be performed to become DFP. This is handled by PTN5100 and MCU
together.
CC_ORIENT and DBGACC_FOUND outputs can be used by the platform, if necessary.

PTN5100

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USB Type-C power delivery PHY and protocol IC

8.1.2 USB PD Provider with Type-C receptacle - Desktop PC

QUSB3

high-voltage
power FET

QUSB4

VBUS

QUSB1

PLATFORM
POWER
NETWORK5 V power FET

QUSB2

EN_USBFET1

EN_USBFET2

EN_USBSRC

5 V REGV_MCUPWR
V_MCUPWR

CTLxx
VCONN_IN

VBUS
BYPASS

I2C

TYPE-CCONNECTOR

INT_N
V_MCUPWR

PTN5100

MCU(PD POLICYAND ALT
MODECONTROLLER(PD PHY)
CC1
CC2

VDD
VIO
I2C

D+/-

USB2+/PCH

TX1+/I2C
RX1+/-

USB3 TX+/USB3 RX+/-CBTL08GP053
TX2+/RX2+/-(TYPE-C HIGH SPEED
SWITCH FOR USB 3.1,
4-LANE DP1.3 AND AUXSIDEBAND)DP[3:0]+/AUX+/-

RFU1/2CPU

HPD
aaa-016440

Fig 9.

Illustrative diagram of Desktop PC application (Source power paths and FETs/power switches): PD
Provider only (DFP role under powered condition and open under unpowered condition) 1 of 2

PTN5100

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USB Type-C power delivery PHY and protocol IC

NX20P5090(20 V/5 A power switch)
VBUS

NX5P3090

PLATFORM
POWER
NETWORK(5 V/3 A power switch)

EN_USBFET1

EN_USBSRC

EN_USBFET2

5 V REGV_MCUPWR
V_MCUPWR

Control
GPIO
VCONN_IN

VBUS
BYPASS

I2C

TYPE-CCONNECTOR

INT_N
V_MCUPWR

PTN5100

MCU(PD POLICYAND ALT
MODECONTROLLER(PD PHY)
CC1
CC2

VDD
VIO

D+/-

USB2+/PCH

TX1+/I2C
RX1+/-

USB3 TX+/USB3 RX+/-CBTL08GP053
TX2+/RX2+/-(TYPE-C HIGH SPEED
SWITCH FOR USB 3.1,
4-LANE DP1.3 AND AUXSIDEBAND)DP[3:0]+/AUX+/-

RFU1/2CPU

HPD
aaa-020143

Fig 10. Illustrative diagram of Desktop PC application (Source power paths and FETs/power switches): PD
Provider only (DFP role under powered condition and open under unpowered condition) 2 of 2

8.1.2.1

Brief description
In this illustration also, the 2-chip solution (PTN5100+ Policy controller & Alternate mode
control MCU) is behind Type-C receptacle and it is configured to act as a PD Provider(Autonomous mode) based on pre-configured Power profiles. The PC system uses the
ATX or similar power supply and it can deliver power to all USB ports. In this diagram,
there is no EC to interface with and so, the 2-chip solution (MCU and PTN5100) is
configured for autonomous operation.

PTN5100

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USB Type-C power delivery PHY and protocol IC

For USB ports, this application:• Sources VBUS 5 V• Sources USB PD power (specific wattage depends on the system application)• Sources VCONN power
Figure 9 and Figure 10 illustrate the configurations with discrete MOSFETs and Powerswitches respectively. PTN5100 controls the power FETs/switches to VBUS 5V and PD
power (Orange colored FETs/Switch). The handshake with power supply unit isdependent on OEM/ODM design.
An important aspect to consider here is that a Desktop PC does not have dead battery
condition though it can be unpowered. If not powered, it presents 'Open' on CC pins. After
power up initialization, PTN5100 would indicate 'Rp'. After PD negotiation, the Desktop
platform could deliver higher voltage/current.
CC_ORIENT and DBGACC_FOUND connections can be used based on platform need.

PTN5100

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USB Type-C power delivery PHY and protocol IC

8.1.3 USB PD Consumer/Provider (Smartphone use case) - Standalone PTN5100
NXP load
switch

CCHR_IN

QCHR_SW

VDC

POWER
SYSTEM

CCHR_OUTSYSTEMPMIC WITH
CHARGERCONTROLLERQCHR_SYN

IBAT+

IBAT-

EN_USBFET2

EN_USBSRC

EN_USBFET1

RBATT

QBATT

QBATT
VBATT

VBUS

BATTERYVCONN_IN
BYPASS
TYPE-CCONNECTOR

VIO
VDD

PTN5100(PD PHY)V_MCUPWR

CC1
INT_N

CC2

I2C
SLV_ADDR

CC_CTRL1

USB2
TX1

I2C

RX1
TX2
RX2

USB3 TX
USB3 RXAPPLICATIONPROCESSOR

CBTL08GP053(TYPE-C HIGH SPEED
SWITCH)

4-lane DP
AUX+/-

RFU1/2aaa-016442

Fig 11. Illustrative diagram of Low power devices (e.g. Smartphones) that need 5 V, 3 A only: PD
Consumer/Provider (DRP role with UFP in dead battery condition and DFP/UFP role depending on Type-C
Partner capability

PTN5100

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USB Type-C power delivery PHY and protocol IC

8.1.3.1

Application description
In this illustration, PTN5100 is behind Type-C receptacle and it is configured to act as a
PD consumer/ Provider. It is important to note that there is no dedicated policy controller
MCU associated with the PD functionality as this application can operate with 5V, 3A only.
Under normal battery/powered condition, PTN5100 is configured as DFP, DRP or UFP
based on register configuration setting and it performs cable/plug connect and disconnect
detection, orientation detection. However, on dead battery condition, it defaults to UFP
role. The power path FET control may or may not be used in the application depending on
the capabilities of System PMIC.
This application is expected to• Receive VBUS 5 V @ 3 A• Provides VBUS 5 V @ 3 A• Sourcing VCONN power is dependent on the Type-C role taken
PTN5100 operates autonomously but it is possible for the system processor to control it
via I2C interface. Though there may not be a need to negotiate higher voltage/current, theplatform may still need to support Alternate modes and VDMs. The Application Processor
is used to handle those capabilities.

PTN5100

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USB Type-C power delivery PHY and protocol IC

8.1.4 Type-C cable adapters with PTN5100

VBUS

VCONN

DCDC
VDD

depletionmode FET

VDD

VBUS

Ra
I2C

CC1

PTN5100

INT_N(PD PHY)

TYPE-CPLUG

LPC11U35
ADAPTOR MCU(IMPLEMENTS
PD POLICY AND
ALTERNATE MODE
SUPPORT)

USB BBREMOTESIDE
CONNECTION

USB2+/-

D+/TX1+/RX1+/TX2+/RX2+/-

ADAPTER/DONGLE HIGHSPEED CIRCUITRY- SWITCHING AND/OR
PROTOCOL CONVERTER

RFU1/2aaa-016443

Fig 12. Illustrative diagram of Cable adapter use case (e.g. UFP in a Type-C to legacy adapter)

8.1.4.1

Application description
In this illustration, PTN5100 is inside Type-C cable adapter operating in UFP role. Some
example use cases are Type-C to DP adapter, Type-C to VGA adapter, Type-C toThunderbolt adapter etc. PTN5100 serves as PD PHY layer device for a Cable adapter
management MCU or dedicated PD MCU wherein PD policy management, Alternate
mode and VDM support are handled. The USB Billboard device is assumed to be
implemented as part of adapter management MCU.
The cable adapter implementation operates on VCONN supply. Discrete depletion mode
FET has to be used in the application for 'Ra' indication on CC pin.

PTN5100

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USB Type-C power delivery PHY and protocol IC

8.1.5 USB PD Consumer/Provider with Type-C receptacle

QUSB3

QUSB4

high-voltage/current
PMOS FETs (SRC)

USB PD negotiatedhigher voltage
DOCKINGSTATIONPOWER
SUPPLYUNIT

EN_USBFET2

TYPE-C
RECEPTACLE

EN_USBFET1

5 V PMOS
FETs (SRC)QUSB2EN_USBSRC

QUSB1

5 V supply for deadbattery condition

VIO

VCONN_IN

VBUS

CTLx
BYPASS

INT_N
I2C

MCU
(PD POLICYCONTROLLER)

PTN5100(PD PHY)USB BB

CC1

VIO

CC2

VDD

applicable only fordocking and monitors
USB2/3 data bus

USB HUB

downstream
USB ports
aaa-016444

Fig 13. Illustrative diagrams of Docking/Multi-Function Monitor/Printer application (2 source power paths and
FETs/power switches): PD Consumer/Provider (Charging UFP) 1 of 2

PTN5100

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USB Type-C power delivery PHY and protocol IC

NX20P5090(20 V/5 A power switch)
USB PD negotiatedhigher voltage
DOCKINGSTATIONPOWER
SUPPLYUNIT

NX5P2090(5 V/2 A power switch)

EN_USBFET1

TYPE-C
RECEPTACLE

EN_USBFET2

EN_USBSRC

5 V supply for deadbattery condition

VIO

VCONN_IN

VBUS
BYPASS

INT_N
I2C

control
GPIO
MCU(PD POLICYCONTROLLER)

PTN5100(PD PHY)USB BB

CC1

VIO

CC2

VDD

applicable only fordocking and monitors
USB2/3 data bus

USB HUB

downstream
USB ports
aaa-020080

Fig 14. Illustrative diagrams of Docking/Multi-Function Monitor/Printer application (2 source power paths and
FETs/power switches): PD Consumer/Provider (Charging UFP) 2 of 2

8.1.5.1

Application description
The example applications are Multi-function monitor, Dock or Printer. PTN5100 is
configured for Charging UFP role. The policy controller MCU would probe PTN5100 to
make sure there is no dead battery device connected at the other end. If a pulldown 'Rd' isdetected at the remote cable end, this platform supplies VBUS 5V. Once the remote end
system is capable of performing power role swap, the roles would be reversed.
This application is expected to:• Receive VBUS 5 V (or provide power during Dead battery operation - VBUS 5 V)
• Provides VBUS PD power
The PD software running on the MCU controls the power FETs/switches to determine
VBUS 5 V and USB PD power delivery (Orange colored power FETs/switch on VBUS).
PTN5100

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

NXP Semiconductors

PTN5100

Product data sheet

8.1.6 USB PD Consumer with Type-C receptacle example
NX20P5090 (20V/5A
power switch)

USB 5 V or PD negotiatedhigher voltage

EN_USBFET2

EN_USBFET1

VIN
VIO

12 V
EN1_12 V
PD LEDs

CTL0

enable_DCDC

CTL1

enable_HDD

BYPASS
INT_N

PTN5100(PD PHY)

I2C/SPI
V_MCUPWR

CC1
CC2

DC DC
CONVERTER(e.g. 5 V
TO 12 V

5 V, 3/6 A

12 V
EN2_12 V

LPC1114
TYPE-C
RECEPTACLE

EN1_5 VCTL2

MCU
(PD POLICY CTL3
CONTROLLERHARDDISK A

EN2_5 V

5V

HARD
DISK B

PowerGood

VIO

USB2 D+/-

TX1
RX1
TX2

XBAR switch

USB3 TX/RX

RX2
aaa-016445

Fig 15. Illustrative diagram of Portable Hard Drive application (sink power path); PD Consumer only

PTN5100

26 of 53

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(TYPE-C HIGH SPEED SWITCH)(REQUIRED FOR DETACHABLE
USB TYPE-C CABLE USE)

USB Type-C power delivery PHY and protocol IC

Rev. 1.1 — 25 July 2017

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VBUS

5V

PTN5100

NXP Semiconductors

USB Type-C power delivery PHY and protocol IC

8.1.6.1

Application description
In a USB PD based hard drive application, PTN5100 + Policy controller MCU operates
autonomously. At POR, PTN5100 presents UFP role and starts to receive VBUS 5 V.
Then based on configured power profile, PD negotiation and contracting is performed.
The MCU interfaces with Hard drive electronics and delivers power after handshake. The
MCU's GPIO pins can be reused to handshake with DCDC converter and the handshakemechanism is OEM platform dependent.
This application is expected to:• Receive VBUS 5 V, USB PD power

PTN5100

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USB Type-C power delivery PHY and protocol IC

9. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
SymbolPTN5100

Product data sheet

Parameter

Conditions

Min

Max

Unit

VDD

supply voltage

0.5

+4.6

V

VIO

IO voltage

0.5

+4.6

V

VBUS

USB VBUS voltage

0.5

+28

V

VI

Input voltage

CC_CTRL1, CC_ORIENT,DBGACC_FOUND

0.5

+4.6

V

CC1, CC2

0.5

+6.0

V

EN_USBSRC, EN_USBFET1,
EN_USBFET2

0.5

+28

V

BYPASS

0.5

+2.5

V

VCONN_IN

0.5

+6.0

V

INT_N

0.5

+4.6

V

SLV_ADDR

0.5

+4.6

V

SPI_CLK_I2C_SCL,
SPI_MOSI_SDA, SPI_MISO,SPI_CS

0.5

+4.6

V

Tstg

Storage temperature

VESD

electrostatic
discharge voltage

voltage at the pin

65

+150

C

HBM: VBUS, CC1, CC2[1][2]

8000-

V

HBM for internal pins:
CC_CTRL1, CC_ORIENT,DBGACC_FOUND, BYPASS,VCONN_IN, VDD, VIO,
INT_N, SLV_ADDR, SPI,
EN_USBFET1, EN_USBFET2
and EN_USBSRC signals

[2]

2000

-

V

CDM

[3]

1000

-

V

[1]

All voltage values, except differential voltages, are with respect to network ground terminal.

[2]

Human Body Model: ANSI/ESDA/JEDEC JDS-001-2012 (Revision of ANSI/ESDA/JEDEC JS-001-2011),
ESDA/JEDEC Joint standard for ESD sensitivity testing, Human Body Model - Component level;
Electrostatic Discharge Association, Rome, NY, USA; JEDEC Solid State Technology Association,
Arlington, VA, USA.

[3]

Charged Device Model: JESD22-C101E December 2009 (Revision of JESD22-C101D, October 2008),
standard for ESD sensitivity testing, Charged Device Model - Component level; JEDEC Solid State
Technology Association, Arlington, VA, USA.

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USB Type-C power delivery PHY and protocol IC

10. Recommended operating conditions
Table 7.

Operating conditions

Symbol Parameter
VDD

System supply voltage

VIO

System IO supply
voltage

Conditions

Specification
guaranteed by

Min

Typ

Max

Unit

ATE

3.0

-

3.6

V

when 3.3 V supply is
used

ATE

3.0

-

3.6

V

when 1.8 V supply is
used

ATE

1.7

-

1.9

V

3.7

-

25

V

VBUS

USB VBUS voltage

ATE or benchVI

input voltage on the pin

ATE

Tamb

CC_CTRL1,
CC_ORIENT,DBGACC_FOUND

ATE

0.3

-

+3.6

V

CC1, CC2

ATE

0.3

-

+5.5

V

EN_USBSRC,
EN_USBFET1,
EN_USBFET2

ATE

0.3

-

+25

V

VCONN_IN

ATE

0.3

-

+5.5

V

INT_N

ATE

0.3

-

+3.6

V

SLV_ADDR

ATE

0.3

-

+3.6

V

20

-

+85

C

Ambient Operating
temperature

PTN5100

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USB Type-C power delivery PHY and protocol IC

11. Characteristics
11.1 Device characteristics
Table 8.
Device characteristics
Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values
are specified at 27 C (unless otherwise noted).
SymbolParameter

Conditions

Min

Typ

Max

Unit

TFET_EN

Time duration between I2C
write/ACK and FET enableasserted

Applicable to all FET enable
pins

-

-

10

s

TFET_DISTime duration between I2C
write/ACK and FET enablede-asserted

Applicable to all FET enable
pins

-

-

10

s

IDD,Active

Active mode operating current

UFP role; attached condition; VDD = 3.3 V

200

-

A

DFP role; attached condition; VDD = 3.3 V

300

-

A

SPI interface is active

-

3

-

A

PD mode is functional; does
not include power delivered
on V_MCUPWR pin; VDD =
3.3 V

-

3

-

mA

VCONN switch is enabled
without FCP and RCP; VDD =
3.3 V

175

250

A

VCONN switch is enabledwith FCP and RCP; VDD =
3.3 V

-

250

340

A

UFP role; Unattachedcondition

-

50

-

A

DFP role; Unattachedcondition (Rp at standard
current level)

-

70

-

A

DRP mode; Unattachedcondition

-

100

-

A

-

-

10

A

CC1, CC2 = 5V

10

-

10

A

Additional current consumed on
VDD

IDD(idle)

Idle mode current on VDD

IVIO(idle)

Idle mode supply current (VIO)

Ibckdrv

Backdrive current

Backdrive current on VDD
pin when that pin is at 0 V

ILIH,EN

HIGH-level input leakage current

VI=3.3V, applies to CC1,
CC2

-

-

20

A

ILIL,EN

LOW-level input leakage current

VI=GND,

20

-

0

A

Applies to CC1, CC2

PTN5100

Product data sheet

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USB Type-C power delivery PHY and protocol IC

11.2 USB PD and Type-C characteristics
Table 9.
USB PD and Type-C AC/DC characteristics
Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values
are specified at 27 C (unless otherwise noted).
SymbolParameter

Conditions

Min

Typ

Max

Unit

USB PD normative specification
fBitrate

Bit rate

270

300

330

Kbps

tUnitInterval

unit interval

3.03

-

3.7

s

pBitRate

Maximum difference between At the transmitterthe bit-rate during the payload
and the reference bit-rate (Thereference bit rate is theaverage bit rate of the last 32
bits of the preamble)

-

-

0.25

%

tInterFrameGap

Time from the end of last bit ofa Frame until the start of thefirst bit of the next Preamble.

25

-

-

s

tStartDrive

Time before the start of thefirst bit of the Preamble when
the transmitter shall startdriving the line.

1

-

1

s

USB PD transmitter normative specificationtEndDriveBMC

Time to cease driving the line
after the end of the last bit of
the Frame.

Min value is limited bytHoldLowBMC

-

-

23

s

tFall

Fall time

10 % and 90 % amplitude
points, minimum is underunloaded condition

300

-

-

ns

tHoldLowBMC

Time to cease driving the line
after the final high-to-lowtransition

Max value is limited by
tEndDriveBMC

1

-

-

us

tRise

Rise time

10 % and 90 % amplitude
points, minimum is underunloaded condition

300

-

-

ns

vSwingVoltage swing

1.05

1.125

1.2

V

zDriver

Transmitter output impedance Source output impedance 33
at the Nyquist frequency of[USB2.0] low speed (750kHz) while the source isdriving the CC line.

-

75



200

-

600

pF

USB PD receiver normative specification
cReceiver

CC Receiver capacitancenTransitionCount

Transitions for signal detect

3

-

-

tRxFilter

Time constant of Rx
bandwidth limiting filter

100

-

-

ns

tTransitionWindow

Time window for detecting
non-idle

12

-

20

s

zBmcRx

Receiver Input Impedance

10

-

-

M

PTN5100

Product data sheet

The CC pin (DFP or UFP)
capacitance when nottransmitting on the line

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NXP Semiconductors

USB Type-C power delivery PHY and protocol IC

Table 9.
USB PD and Type-C AC/DC characteristics …continued
Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values
are specified at 27 C (unless otherwise noted).
SymbolParameter

Conditions

Min

Typ

Max

Unit

64

80

96

A

166

180

194

A

314

330

346

A

Type-C specification
Current source for DFP pullup Default current
indication
1.5 A

Ipullup

3A
Rpulldn

Pulldown termination on UFP

After on-board calibration is 4.6
completed

5.1

5.6

k

zOPEN

UFP CC termination

Applies to self-powered
UFP to remain
undetectable by DFP

126

-

-

k

VCLAMPH

High current mode clamp
voltage

UFP mode; VDD = 0,
VBUS = 0

0.85

-

2.18

V

VCLAMPM

Medium current mode clamp
voltage

UFP mode; VDD = 0,
VBUS = 0

0.45

-

1.25

V

VCLAMPD

Default current mode clamp
voltage

UFP mode; VDD = 0,
VBUS = 0

0.25

-

1.25

V

VTUM

Medium current mode
detection threshold

UFP mode

1.16

1.23

1.31

V

VTUS

Standard current mode
detection threshold

UFP mode

0.61

0.66

0.70

V

VTURa

Powered Accessory (Ra)mode detection threshold

UFP mode

0.15

0.2

0.25

V

VTDH,RaHigh current mode Ra
detection threshold

DFP mode

0.75

0.8

0.85

V

VTD,RdRd detection threshold

DFP mode

2.45

2.6

2.75

V

VTDM,Ra

Medium current mode Ra
detection threshold

DFP mode

0.35

0.4

0.45

V

VTDS,RaStandard current mode Ra
detection threshold

DFP mode

0.15

0.2

0.25

V

11.3 VCONN switch characteristics
Table 10. VCONN switch characteristics
Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values
are specified at 27 C (unless otherwise noted).
SymbolParameter

VVCONN_IN

Conditions

Min

Typ

Max

Unit

VCONN_IN voltage

2.7

-

5.5

V

IVCONN_IN

DC Current

-

-

1

A

RON

ON resistance

-

150

240

m

CON

ON capacitance

-

450

-

pF

COFF

OFF Capacitance

-

250

-

pF

IinrushInrush current

-

150

mA

PTN5100

Product data sheet

When VCONN switch isenabled; corresponding
CCx pin voltage is zero; CCcapacitance = 10 F

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USB Type-C power delivery PHY and protocol IC

Table 10. VCONN switch characteristics …continued
Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values
are specified at 27 C (unless otherwise noted).
SymbolParameter

Conditions

Min

Typ

Max

Unit

IFCP

Forward Current Protection
Limit@ threshold of 250 mA

125

250

350

mA

@ threshold of 500 mA

350

500

700

mA

@ threshold of 1 A

700

1000

1300

mA

IRCP

Reverse Current Protection
limit

-

60

110

mA

Tdis

VCONN Switch disable time
due to FCP or RCP fault

-

-

300

s

11.4 Power AC/DC characteristics
Table 11. Power AC/DC characteristics
Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values
are specified at 27 C (unless otherwise noted).[1]SymbolParameter

Conditions

Min

Typ

Max

Unit

VMCUPWRDC Voltage on V_MCUPWR
pin

Applies to both VBUS and
VDD

2.5

-

3.6

V

IMCUPWR

DC Current delivered out of
V_MCUPWR pin

Applies to both VBUS and
VDD;

-

-

30

mA

-

150

-

mA

2.2 F 10 %De-coupling capacitor on
V_MCUPWR pin
IinrushInrush current

2.2 F capacitors on
BYPASS and V_MCUPWR
pins, these pins are at 0 V

VOUT_load

V_MCUPWR voltage

VBUS @ 3.7 V, load current 2.5
30 mA

-

3.6

V

VLine_reg

Line voltage regulation

VBUS sweep 3.7 V to 25 V; load current 30 mA

-

200

mV

VLoad_reg

Load voltage regulation

VBUS @ 3.7 V; load
current sweep 0 mA to
30 mA

-

-

50

mV

VLoad_step

Load voltage variation underload step

VBUS @ 3.7 V; load
current step from 0 to
30 mA over 30 S interval

-

-

150

mV

PSRR

Power supply rejection ratio

VBUS @ 3.7 V to 25 V

[1]

DC

70

dB

F = 100 kHz

50dB

F = 1 MHz30

dB

For all the specification measurements, supply decoupling capacitor 2.2 A 10 % is considered to be present on V_MCUPWR pin.
Also, the capacitor is charged up to V_MCUPWR voltage unless otherwise specified.

PTN5100

Product data sheet

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USB Type-C power delivery PHY and protocol IC

11.5 I2C characteristics
Table 12. I2C characteristics
Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values
are specified at 27 C (unless otherwise noted).[1]SymbolParameter

Min

Typ

Max

Unit

FI2C

I2C clock frequency

0

-

1000

kHz

VIH

HIGH-level Input voltage

0.7 
VDDIO

-

-

V

VIL

LOW-level Input voltage

-

-

0.3 
VDDIO

V

Vhys

Hysteresis of Schmitt trigger VDDIO > 2 V
inputs

0.05
VDDIO

-

-

V

VDDIO < 2 V

0.1 
VDDIO

-

-

V

LOW-level output voltage at VDDIO > 2 V
3mA sink current
VDDIO < 2 V

0

-

0.4

V

0

-

0.2
VDDIO

V

LOW-level output current

3

-

-

mA

20

-

-

mA

6

-

-

mA

10

-

10

A

VOL

IOL

Conditions

VOL = 0.4 V;
Standard and Fast modes
VOL = 0.4 V;
Fast mode plus
VOL = 0.6 V;
Fast mode

IIL

LOW-level input current

Pin voltage - 0.1VDDIO to 0.9VIO,
max

CI

Capacitance of IO pin

-

-

10

pF

tHD,STA

Hold time (repeated) START Fast mode plus; After this period, thecondition
first clock pulse is generated

0.26

-

-

s

tLOW

LOW period of I2C clock

0.5

-

-

s

tHIGH

HIGH period of I2C clock

Fast mode plus

0.26

-

-

s

tSU;STA

Setup time (repeated)
START condition

Fast mode plus

0.26

-

-

s

tHD;DAT

Data Hold time

Fast mode plus

0

-

-

s

Fast mode plus

tSU;DAT

Data Setup time

Fast mode plus

50

-

-

ns

tr

Rise time of I2C_SCL and
I2C_SDA signals

Fast mode plus

-

-

120

ns

tf

Fall time of I2C_SCL and
I2C_SDA signals

Fast mode plus

-

-

120

ns

tSU;STO

Setup time for STOP
condition

Fast mode plus

0.26

-

-

s

tBUF

Bus free time between
Fast mode plus
STOP and START condition

0.5

-

-

s

PTN5100

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USB Type-C power delivery PHY and protocol IC

Table 12. I2C characteristics …continued
Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values
are specified at 27 C (unless otherwise noted).[1]SymbolParameter

Conditions

tVD;DAT

Data valid time

Fast mode plus

0.45

-

-

s

tVD;ACK

Data valid acknowledge
time

Fast mode plus

0.45

-

-

s

tSP

Pulse width of spikes thatmust be suppressed by
input filter

-

-

50

ns

[1]

Min

Typ

Max

Unit

VDDIO is I2C bus pull up voltage.

tf
SDA

tr

tSU;DAT

70 %
30 %

70 %
30 %

cont.

tHD;DAT

tf

tVD;DAT
tHIGH

tr
70 %
30 %

SCL

70 %
30 %

70 %
30 %

tHD;STA

70 %
30 %

cont.

tLOW

9th clock

1 / fI2CS

1st clock cycle
tBUF

tf
SDA

tSU;STAtHD;STAtVD;ACKtSPtSU;STO

70 %
30 %

SCL
Sr

P
9th clockS
aaa-020541

Fig 16. I2C timing diagram

PTN5100

Product data sheet

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USB Type-C power delivery PHY and protocol IC

11.6 SPI characteristics
Table 13. SPI interface: AC/DC characteristics
Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values
are specified at 27 C (unless otherwise noted).
SymbolParameter

Conditions

Min

Typ

Max

Unit

fSPI

SPI clock frequency(SPI_CLK)

Applies to both TX and RX

-

-

20

MHz

tSPI;HISPI clock HIGH time

20

-

-

ns

tSPI;LO

SPI clock LOW time

20

-

-

ns

tSPI;rise

SPI clock (LOW to HIGH) rise
time

0.1

-

-

V/ns

tSPI;fall

SPI clock (HIGH to LOW) fall
time

0.1

-

-

V/ns

tSPI;CSNSSPI_CS Not Setup time

Relative to SPI clock pin

0

-

-

ns

tSPI;CSNHSPI_CS Not Hold time

Relative to SPI clock pin

0

-

-

ns

tSPI;DINS

Data In Setup time

Applies to5
SPI_MOSI_I2C_SDA; relative
to SPI clock

-

-

ns

tSPI;DINH

Data In Hold time

Applies to5
SPI_MOSI_I2C_SDA; relative
to SPI clock

-

-

ns

tSPI;DONS

SPI clock edge to Valid Data
Out

Applies to SPI_MISO

-

-

7

ns

tSPI;DONHSPI clock edge to Data Out
Hold time

Applies to SPI_MISO

0-

CL;SPI

Maximum IO capacitance
supported

SPI_CLK_I2C_SCL,
SPI_MOSI_I2C_SDA

-

-

10

pF

CIN;SPI

Maximum IO capacitance

SPI_MISO, SPI_CS

-

-

10

pF

VIH;SPI

HIGH-level input voltage

SPI_MISO

0.7 
V_MCUPWR--

V

VIL;SPI

LOW-level input voltage

SPI_MISO

-

-

0.3 
V
V_MCUPWR

VOL;SPI

LOW-level output voltage

SPI_CLK_I2C_SCL, SPI_CS,
SPI_MOSI_I2C_SDA

-

-

0.5

V

V_MCUPWR
 0.5

-

-

V

ns

IOL = 4 mA
VOH;SPI

HIGH-level output voltage

SPI_CLK_I2C_SCL, SPI_CS,
SPI_MOSI_I2C_SDA
IOH = 4 mA

ILIH;EN

HIGH-level input leakage
current

VI = 3.3 V

1

-

1

A

ILIL;EN

LOW-level input leakage
current

VI = GND

1

-

1

A

PTN5100

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USB Type-C power delivery PHY and protocol IC

SPI_CStSPI;FALLtSPI;CSNHtSPI;CSNSSPI_CLKtSPI;DINHtSPI;DINSMOSItSPI;RISE

MSB

LSB

HIGH-Z

HIGH-Z

MISO
aaa-020542

Fig 17. SPI write timing

SPI_CStSPI;HItSPI;LOSPI_CLKtSPI;DONH
MISO

MSB

LSB

tSPI;DONS
MOSI
aaa-020543

Fig 18. SPI read timing

11.7 CONTROL IO characteristics
Table 14. Control I/O characteristics
Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values
are specified at 27 C (unless otherwise noted).
SymbolParameter

Conditions

Min

Typ

Max

Unit

System side CMOS output pins (CC_ORIENT, DBGACC_FOUND)
VOH

HIGH-level Output voltage

IOH = 4 mA

VIO 0.5-

VOL

LOW-level Output voltage

IOL = 4 mA

-

-

0.5

V

CI

Capacitance of IO pin

-

-

20

pF

ILIH,EN

HIGH-level input leakage
current

VI = 3.3 V

1

-

1

A

ILIL,EN

LOW-level input leakage
current

VI = GND

1

-

1

A

applies to CC_CTRL1

-

-

0.4

V

applies to SLV_ADDR

-

-

0.3 
VDD

V

V

System side input pins (CC_CTRL1)
VIL

LOW-level Input voltage

PTN5100

Product data sheet

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NXP Semiconductors

USB Type-C power delivery PHY and protocol IC

Table 14. Control I/O characteristics …continued
Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values
are specified at 27 C (unless otherwise noted).
SymbolParameter

Conditions

Min

Typ

Max

Unit

VIH

HIGH-level input voltage

applies to SLV_ADDR

0.7  VDD

-

-

V

CI

Capacitance of IO pin

applies to CC_CTRL1,
SLV_ADDR

-

-

20

pF

ILIH,EN

HIGH-level input leakage
current

VI = 3.3 V

1

-

1

A

ILIL,EN

LOW-level input leakage
current

VI = GND

1

-

1

A

-

-

0.5

V

-

-

20

pF

System side open drain interface pins (INT_N); pulled up to VDDIO
VOL

LOW-level Output voltage

CI

Capacitance of IO pin

PTN5100

Product data sheet

IOL = 4 mA

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NXP Semiconductors

USB Type-C power delivery PHY and protocol IC

Table 14. Control I/O characteristics …continued
Applicable across operating temperature and power supply ranges as per Section 10 (unless otherwise noted). Typical values
are specified at 27 C (unless otherwise noted).
SymbolParameter

Conditions

Min

Typ

Max

Unit

FET enable pins (EN_USBSRC, EN_USBFET1, EN_USBFET2)
VOL,EN

LOW-level output voltage

IOL = 4 mA

-

-

0.5

V

VIH,ENHIGH-level input voltage

FET enable pins are in Hi-Z

0.7 
V_MCUPWR

25

V

ILIH,EN

HIGH-level input leakage
current

VI = 25 V

1

-

1

A

ILIL,EN

LOW-level input leakage
current

VI = GND

1

-

1

A

[1]

VFET_Bias is the bias voltage on the FET enable pins

PTN5100

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USB Type-C power delivery PHY and protocol IC

12. Package outline
HVQFN20: plastic thermal enhanced very thin quad flat package; no leads;
20 terminals; body 4 x 4 x 0.85 mm

A

B

D

SOT917-4

terminal 1
index area
A

E

A1
c

detail X

e1
e
6

10

C

C A B
C

v
w

b

y1 C

y

L

11

5

e
Eh

e2

1

15

terminal 1
index area

20

X

16
Dh

0

5 mm
scale

Dimensions
b

c

D(1)

Dh

E(1)

Eh

e

e1

e2

L

v

w

max 1.00 0.05 0.30
nom 0.85
0.25
min 0.80
0.20

0.2

4.1
4.0
3.9

3.0
2.9
2.8

4.1
4.0
3.9

3.0
2.9
2.8

0.5

2

2

0.35
0.30
0.25

0.1

0.05 0.08

Unit
mm

A

A1

y

y1
0.1

Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outlineversion
SOT917-4

References
IEC

JEDEC

JEITA

MO-220---sot917-4_po

Europeanprojection

Issue date
14-10-27
14-11-07

Fig 19. Package outline SOT917-4 (HVQFN20)
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USB Type-C power delivery PHY and protocol IC

13. Packing information
13.1 SOT917-4: HVQFN20; Reel pack, SMD, 13" Q2/T3 standard productorientation; Orderable part number ending ,128 or HP; Ordering code
(12NC) ending 128
13.1.1 Packing method%DJ%DUFRGHODEHO
7DSH
5HHODVVHPEO\%DUFRGHODEHO(6'HPERVVHG*XDUGEDQG(6'ODEHO%DJZLWKUHHO&LUFXODUVSURFNHWKROHVRSSRVLWHWKHODEHOVLGHRIUHHO

3ULQWHGSODQRER[&RYHUWDSH

4$VHDO&DUULHUWDSH

6SDFHIRUDGGLWLRQDOODEHO3UHSULQWHG(6'ZDUQLQJ%DUFRGHODEHO'U\SDFN,'VWLFNHU
3ULQWHGSODQRER[
DDD

Fig 20. Reel pack for SMD

PTN5100

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USB Type-C power delivery PHY and protocol IC

Table 15.

Dimensions and quantities

Reel dimensionsd  w (mm) [1]

SPQ/PQ (pcs)[2]Reels per box

Outer box dimensionsl  w  h (mm)330  126000

1342  338  27

[1]

d = reel diameter; w = tape width.

[2]

Packing quantity dependent on specific product type.
View ordering and availability details at NXP order portal, or contact your local NXP representative.

13.1.2 Product orientation

47 47
EDOO

47 47

DDD

DDD

Tape pocket quadrants

Ball 1 is in quadrant Q2/T3

Fig 21. Product orientation in carrier tape

13.1.3 Carrier tape dimensions
PP

:

.

$

%

3

7

GLUHFWLRQRIIHHG

DDRFig 22. Carrier tape dimensions
Table 16. Carrier tape dimensions
In accordance with IEC 60286-3.

PTN5100

Product data sheet

A0 (mm)

B0 (mm)

K0 (mm)T (mm)

P1 (mm)W (mm)

4.30  0.10

4.30  0.10

1.10  0.10

0.30  0.05

8.0  0.10

12  0.30

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USB Type-C power delivery PHY and protocol IC

13.1.4 Reel dimensions

$

=

:

%

&

'

GHWDLO=DDRFig 23. Schematic view of reel
Table 17. Reel dimensions
In accordance with IEC 60286-3.

PTN5100

Product data sheet

A [nom](mm)

W2 [max](mm)

B [min](mm)

C [min](mm)

D [min]
(mm)

330

18.4

1.5

12.8

20.2

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13.1.5 Barcode label)L[HGWH[W&RXQWU\RIRULJLQ
LH0DGHLQRU
'LIIXVHGLQ(8>@$VVHPEOHGLQ
3DFNLQJXQLW 34 LGHQWLILFDWLRQQGWUDFHDELOLW\ORWQXPEHU
QG \RXQJHVW GDWHFRGH
QG4XDQWLW\
7UDFHDELOLW\ORWQXPEHU'DWHFRGH:LWKOLQHDUEDUFRGH
4XDQWLW\:LWKOLQHDUEDUFRGH
7\SHQXPEHU
1;31&:LWKOLQHDUEDUFRGH

1;36(0,&21'8&7256
0$'(,1!&28175<>352'8&7,1)2@
7 38,'%
7 /27
' 5('$7(' '$7(7 25,*
4 47<7 30&
3 06/3%7
7 /2706/3%7
' '$7(
4 47<+$/2*(1)5((3 7<3(
5R+6FRPSOLDQW
3 &2'(122SWLRQDOSURGXFWLQIRUPDWLRQ
5HDSSURYDOGDWHFRGH
2ULJLQFRGH
3URGXFW0DQXIDFWXULQJ&RGH
06/DWWKH3HDN%RG\VROGHU
WHPSHUDWXUHZLWKWLQOHDG 
06/DWWKHKLJKHUOHDGIUHH
3HDN%RG\7HPSHUDWXUH'PDWUL[ZLWKDOOGDWDLQFOXGLQJWKHGDWDLGHQWLILHUV$GGLWLRQDOLQIRLIKDORJHQ
IUHHSURGXFW$GGLWLRQDOLQIRRQ5R+6/HDGIUHHV\PERODDNFig 24. Example of typical box and reel information barcode label
Table 18.

PTN5100

Product data sheet

Barcode dimensions

Box barcode labell  w (mm)Reel barcode labell  w (mm)100  75

100  75

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NXP Semiconductors

USB Type-C power delivery PHY and protocol IC

14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth accountof soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.

14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached toPrinted Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides boththe mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole andSurface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is notsuitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and highdensities that come with increased miniaturization.

14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming froma standing wave of liquid solder. The wave soldering process is suitable for the following:• Through-hole components• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadlesspackages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed bycomponent placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation• The moisture sensitivity level of the packages• Package placement• Inspection and repair• Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave

• Solder bath specifications, including temperature and impurities
PTN5100

Product data sheet

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USB Type-C power delivery PHY and protocol IC

14.4 Reflow soldering
Key characteristics in reflow soldering are:• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads tohigher minimum peak temperatures (see Figure 25) than a SnPb process, thus
reducing the process window• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board• Reflow temperature profile; this profile includes preheat, reflow (in which the board isheated to the peak temperature) and cooling down. It is imperative that the peaktemperature is high enough for the solder to make reliable solder joints (a solder pastecharacteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 19 and 20
Table 19.

SnPb eutectic process (from J-STD-020D)

Package thickness (mm)Package reflow temperature (C)
Volume (mm3)
< 350

 350

< 2.5

235

220

 2.5

220

220

Table 20.

Lead-free process (from J-STD-020D)

Package thickness (mm)Package reflow temperature (C)
Volume (mm3)< 350

350 to 2000

> 2000

< 1.6

260

260

260

1.6 to 2.5

260

250

245

> 2.5

250

245

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 25.

PTN5100

Product data sheet

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temperature

maximum peak temperature= MSL limit, damage level

minimum peak temperature= minimum soldering temperaturepeak
temperaturetime
001aac844

MSL: Moisture Sensitivity Level

Fig 25. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365“Surface mount reflow soldering description”.

PTN5100

Product data sheet

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USB Type-C power delivery PHY and protocol IC

15. Soldering: PCB footprints)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI+94)1SDFNDJH

627

+[
*[
3

'





&

Q63[

63[

+\

63\WRW

63\
*\

Q63\
6/\

%\

$\

63[WRW

;
6/[



%[



$[
5HFRPPHQGHGVWHQFLOWKLFNQHVVPP
 

VROGHUODQG

VROGHUODQGSOXVVROGHUSDVWH

VROGHUSDVWHGHSRVLW

VROGHUUHVLVWRFFXSLHGDUHD'LPHQVLRQVLQPP

GHWDLO;'LPHQVLRQV PPDUHWKHRULJLQDOGLPHQVLRQV
3

$[





,VVXHGDWH

$\

%[

%\

&

'

6/[

6/\ 63[WRW 63\WRW 63[

63\

*[

*\

+[

+\

Q63[

Q63\






































VRWBIU

Fig 26. PCB footprint for SOT917-4 (HVQFN20); reflow soldering
PTN5100

Product data sheet

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NXP Semiconductors

USB Type-C power delivery PHY and protocol IC

16. Abbreviations
Table 21.

Abbreviations

AcronymDescription

AP

Application Processor

ASIC

Application Specific Integrated Circuit

CDM

Charged Device Model, an ESD standard

CPU

Central Processing Unit

DBP

Dead Battery Provisioning

DFP

Downstream Facing Port

DRP

Dual Role PortEC

Embedded Controller

FCP

Forward Current ProtectionFS

USB Full Speed signaling

HBM

Human Body Model, an ESD standardHS

USB High Speed signaling

LDO

Low Drop-Out regulator

LS

USB Low Speed signaling

MM

Machine Model, an ESD standardOCOver-Current condition

OCD

Over-Current Detection

PCH

Platform Controller Hub

PD

Power Delivery specification

PMIC

Power Management IC

POR

Power ON Reset

RCP

Reverse Current Protection

SS

USB3.0 Super Speed Signaling

UFP

Upstream Facing PortUSB

Universal Serial Bus

17. References

PTN5100

Product data sheet[1]

USB Power Delivery Specification Revision 2.0, version 1.1, May 2015

[2]

USB Type-C Cable and Connector Specification Revision 1, April 2015

[3]

PTN5100 Application Programming guide[4]

UM10204, "I2C-bus specification and user manual"; NXP Semiconductors, Revision
03 June 19, 2007

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USB Type-C power delivery PHY and protocol IC

18. Revision history
Table 22.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

PTN5100 v.1.1

20170725

Product data sheet-

PTN5100 v.1

Modifications:• Figure 15: Replaced “CBTL04GP043” with “XBAR switch” in Type-C high speed switch
block

PTN5100 v.1

PTN5100

Product data sheet

20160801

Product data sheet-

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19. Legal information
19.1 Data sheet status
Document status[1][2]Product status[3]Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product development.

Preliminary [short] data sheet

Qualification

This document contains data from the preliminary specification.

Product [short] data sheet

Production

This document contains the product specification.

[1]

Please consult the most recently issued document before initiating or completing a design.

[2]

The term ‘short data sheet’ is explained in section “Definitions”.

[3]

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.

19.2 Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences ofuse of such information.
Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed andfull information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, thefull data sheet shall prevail.
Product specification — The information and data provided in a Productdata sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors andcustomer have explicitly agreed otherwise in writing. In no event however,shall an agreement be valid in which the NXP Semiconductors product isdeemed to offer functions and qualities beyond those described in the
Product data sheet.

19.3 Disclaimers
Limited warranty and liability — Information in this document is believed tobe accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy orcompleteness of such information and shall have no liability for theconsequences of use of such information. NXP Semiconductors takes noresponsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordancewith the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to makechanges to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

PTN5100

Product data sheet

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical orsafety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability forinclusion and/or use of NXP Semiconductors products in such equipment orapplications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer productdesign. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications andproducts planned, as well as for the planned application and use ofcustomer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with theirapplications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in thecustomer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications andthe products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects toapplying the customer’s general terms and conditions with regard to thepurchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted orconstrued as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents orother industrial or intellectual property rights.

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USB Type-C power delivery PHY and protocol IC

Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of thisdocument, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use inautomotive applications to automotive specifications and standards, customer(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design anduse of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.

20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

PTN5100

Product data sheet

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USB Type-C power delivery PHY and protocol IC

21. Contents
1
2
2.1
2.2
2.3
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.3
7.3.1
7.3.2
7.4
7.5
7.5.1
7.5.1.1
7.5.1.2
7.5.1.3
7.5.2
7.5.3
7.5.4

7.6
8
8.1
8.1.1
8.1.1.1
8.1.2
8.1.2.1
8.1.3
8.1.3.1
8.1.4
8.1.4.1
8.1.5
8.1.5.1

General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
USB PD and Type-C Features . . . . . . . . . . . . . 2
System protection features . . . . . . . . . . . . . . . . 2
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 7
Type-C Configuration Channel functional block 8
USB Power Delivery Function . . . . . . . . . . . . . 9
VCONN Switch . . . . . . . . . . . . . . . . . . . . . . . 10
Forward Current Protection (FCP) . . . . . . . . . 11
Reverse Current Protection (RCP) . . . . . . . . . 11
Power FET control . . . . . . . . . . . . . . . . . . . . . 11
MCU interface and control . . . . . . . . . . . . . . . 12
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 12
I2C writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I2C reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I2C address auto-incrementing . . . . . . . . . . . 13
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Register interface . . . . . . . . . . . . . . . . . . . . . . 13
Relevant Interface pins - SLV_ADDR,SPI_CLK_I2C_SCL, SPI_MOSI_I2C_SDA,
SPI_CS, SPI_MISO, INT_N . . . . . . . . . . . . . . 13
Power supplies . . . . . . . . . . . . . . . . . . . . . . . 13
PTN5100 - Use case view . . . . . . . . . . . . . . . . 14
System use cases . . . . . . . . . . . . . . . . . . . . . 15
USB PD Provider/Consumer Notebook/Ultrabook/Chromebook/Tablet PC . 15
Brief description . . . . . . . . . . . . . . . . . . . . . . . 16
USB PD Provider with Type-C receptacle Desktop PC . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Brief description . . . . . . . . . . . . . . . . . . . . . . . 19
USB PD Consumer/Provider (Smartphone usecase) - Standalone PTN5100 . . . . . . . . . . . . . 21
Application description . . . . . . . . . . . . . . . . . . 22
Type-C cable adapters with PTN5100 . . . . . . 23
Application description . . . . . . . . . . . . . . . . . . 23
USB PD Consumer/Provider with Type-C
receptacle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Application description . . . . . . . . . . . . . . . . . . 25

8.1.6
8.1.6.1
9
10
11
11.1
11.2
11.3
11.4
11.5
11.6
11.7
12
13
13.1

13.1.113.1.213.1.313.1.413.1.5
14
14.1
14.2
14.3
14.4
15
16
17
18
19
19.1
19.2
19.3
19.4
20
21

USB PD Consumer with Type-C receptacle
example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Application description . . . . . . . . . . . . . . . . . . 27
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 28
Recommended operating conditions . . . . . . 29
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30
Device characteristics . . . . . . . . . . . . . . . . . . 30
USB PD and Type-C characteristics . . . . . . . 31
VCONN switch characteristics . . . . . . . . . . . . 32
Power AC/DC characteristics . . . . . . . . . . . . 33
I2C characteristics . . . . . . . . . . . . . . . . . . . . . 34
SPI characteristics . . . . . . . . . . . . . . . . . . . . . 36
CONTROL IO characteristics. . . . . . . . . . . . . 37
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 40
Packing information . . . . . . . . . . . . . . . . . . . . 41
SOT917-4: HVQFN20; Reel pack, SMD, 13"
Q2/T3 standard product orientation; Orderable
part number ending ,128 or HP; Ordering code
(12NC) ending 128. . . . . . . . . . . . . . . . . . . . . 41
Packing method . . . . . . . . . . . . . . . . . . . . . . . 41
Product orientation . . . . . . . . . . . . . . . . . . . . . 42
Carrier tape dimensions . . . . . . . . . . . . . . . . . 42
Reel dimensions . . . . . . . . . . . . . . . . . . . . . . 43
Barcode label . . . . . . . . . . . . . . . . . . . . . . . . . 44
Soldering of SMD packages . . . . . . . . . . . . . . 45
Introduction to soldering. . . . . . . . . . . . . . . . . 45
Wave and reflow soldering. . . . . . . . . . . . . . . 45
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 45
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 46
Soldering: PCB footprints . . . . . . . . . . . . . . . 48
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 49
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Revision history . . . . . . . . . . . . . . . . . . . . . . . 50
Legal information . . . . . . . . . . . . . . . . . . . . . . 51
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 51
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Contact information . . . . . . . . . . . . . . . . . . . . 52
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

© NXP Semiconductors N.V. 2017.

All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 July 2017
Document identifier: PTN5100