S-19115xxxA Series
www.ablic.com

AUTOMOTIVE, 125°C OPERATION, 36 V,
VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION
WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)© ABLIC Inc., 2021-2023

Rev.1.3_00

This IC, developed using CMOS technology, is a high-accuracy voltage detector. The detection voltage and release voltage
are fixed internally with an accuracy of ±1.5% (16.0 V ≤ VDET(S))
Apart from the power supply pin, the detection voltage input pin (SENSE pin) is also prepared, so the output is stable even if
the SENSE pin voltage (VSENSE) falls to 0 V. The SENSE pin also has a built-in reverse connection protection circuit that
reduces current in the SENSE pin during a reverse connection.
The release signal can be delayed by setting a capacitor externally, and the release delay time accuracy is ±15% (CD =3.3 nF). The output form is Nch open-drain output.
ABLIC Inc. offers FIT rate calculated based on actual customer usage conditions in order to support customer functionalsafety design.
For more information regarding our FIT rate calculation, contact our sales representatives.
CautionThis product can be used in vehicle equipment and in-vehicle equipment. Before using the product forthese purposes, it is imperative to contact our sales representatives.

 Features• Detection voltage:• Detection voltage accuracy:

12.2 V to 18.0 V (0.1 V step)±1.5% (16.0 V ≤ VDET(S) ≤ 18.0 V, Ta = −40°C to +125°C)±1.6% (12.2 V ≤ VDET(S) < 16.0 V, Ta = −40°C to +125°C)• Hysteresis width selectable from "Available" / "Unavailable":"Available": 5.0%, 10.0%"Unavailable": 0%• Release delay time accuracy:±15% (CD = 3.3 nF)• Current consumption:
0.6 μA typ.
• Output form:
Nch open-drain output• Built-in reverse connection protection circuit: Reduces current in the SENSE pin during a reverse connection.
• Operation voltage range:
3.0 V to 36.0 V• Operation temperature range:
Ta = −40°C to +125°C• Lead-free (Sn 100%), halogen-free• Withstand 45 V load dump
• AEC-Q100 qualified*1*1.

Contact our sales representatives for details.

 Applications• Automotive battery voltage detection• For automotive use (engine, transmission, suspension, ABS, related-devices for EV / HEV / PHEV, etc.)

 Packages• HTMSOP-8• HSNT-8(2030)• SOT-23-5

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AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
 Block Diagrams
1.

S-19115 Series L type
VDD

SENSE
OUT
−
+

*1

Delay
circuit

VREF
*1

*1

VSS

CD

*1.

Parasitic diodeFigure 1

Product TypeL type2Hysteresis Width0%

Output FormNch open-drain output

Output Logic
Active "L"AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series
2.

S-19115 Series M / N type
VDD

SENSE
OUT
−
+

*1

Delay
circuit

VREF
*1

*1

VSS

CD

*1.

Parasitic diodeFigure 2

Product TypeM typeN typeHysteresis Width
5.0%
10.0%

Output FormNch open-drain output
Nch open-drain output

Output Logic
Active "L"
Active "L"3

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
 AEC-Q100 Qualified
This IC supports AEC-Q100 for operation temperature grade 1.
Contact our sales representatives for details of AEC-Q100 reliability specification.

 Product Name Structure
1.

Product name
S-19115 x

xx

A - xxxx

U 7

Environmental codeU:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
S8T1: HTMSOP-8, Tape
A8T1: HSNT-8(2030), Tape
M5T1: SOT-23-5, Tape
Operation temperatureA:
Ta = −40°C to +125°C
Overvoltage detection voltage*2
C2 to J0
(e.g., when the detection voltage is 12.2 V, it is expressed as C2.
when the detection voltage is 18.0 V, it is expressed as J0.)
Product type*3

*1.
*2.
*3.

4

Refer to the tape drawing.
Regarding detection voltage, contact our sales representatives.
Refer to "2. Function list of product types".

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series
2.

Function list of product types
Table 1
Product TypeL typeM typeN type3.

Hysteresis Width
0%
5.0%
10.0%

Output FormNch open-drain output
Nch open-drain output
Nch open-drain output

Output Logic
Active "L"
Active "L"
Active "L"

Packages
Table 2 Package Drawing Codes
Package NameHTMSOP-8
HSNT-8(2030)
SOT-23-5

Dimension

Tape

Reel

Land

FP008-A-P-SD
PP008-A-P-SD
MP005-A-P-SD

FP008-A-C-SD
PP008-A-C-SD
MP005-A-C-SD

FP008-A-R-SD
PP008-A-R-SD
MP005-A-R-SD

FP008-A-L-SD
PP008-A-L-SD−

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AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
 Pin Configurations
1.

HTMSOP-8
Top view

Table 3

1
2
3
4

8
7
6
5
Bottom view
1
2
3
4

8
7
6
5

Pin No.
1
2
3
4
5
6
7
8

Symbol
NC*2
VDD
NC*2
SENSE
CD*3
VSS
OUT
NC*2

Description
No connection
Voltage input pin
No connection
Detection voltage input pin
Connection pin for release delay time adjustment capacitor
GND pin
Voltage detection output pin
No connection*1

Figure 3
*1.
*2.
*3.

2.

Connect the heat sink of backside at shadowed area to the board, and set electric potential GND.
However, do not use it as the function of electrode.
The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.
Connect a capacitor between the CD pin and the VSS pin. The release delay time can be adjusted according to
the capacitance.

HSNT-8(2030)
Top view
1

Table 4
8

4

5

Bottom view
8

1

5

4
*1

Pin No.
1
2
3
4
5
6
7
8

Symbol
NC*2
VDD
NC*2
SENSE
CD*3
VSS
OUT
NC*2

Description
No connection
Voltage input pin
No connection
Detection voltage input pin
Connection pin for release delay time adjustment capacitor
GND pin
Voltage detection output pin
No connection

Figure 4
*1.
*2.
*3.

6

Connect the heat sink of backside at shadowed area to the board, and set electric potential GND.
However, do not use it as the function of electrode.
The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.
Connect a capacitor between the CD pin and the VSS pin. The release delay time can be adjusted according to
the capacitance.

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series
3.

SOT-23-5
Table 5Top view

Pin No.

Symbol

1
2

OUT
VSS

3

CD*1

4
5

SENSE
VDD

Description
Overvoltage detection output pin
GND pinConnection pin for release delay time adjustment
capacitor
Detection voltage input pin
Voltage input pin

Figure 5*1.

Connect a capacitor between the CD pin and the VSS pin. The release delay time can be adjusted according to
the capacitance.

7

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
 Absolute Maximum Ratings
Table 6
(Ta = −40°C to +125°C unless otherwise specified)
Item
SymbolAbsolute Maximum Rating
Unit
VSS − 0.3 to VSS + 45.0
Power supply voltage
VDD
V
VSS − 30.0 to VSS + 45.0
SENSE pin voltage
VSENSEV
VSS − 0.3 to VDD + 0.3 ≤ VSS + 7.0
CD pin input voltage
VCD
V
VSS − 0.3 to VSS + 45.0
Output voltage
VOUT
V
Output current
IOUT
25
mA
−40 to +150
Junction temperature
Tj°C−40 to +125
Operation ambient temperature
Topr°C−40 to +150
Storage temperature
Tstg°C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physicaldamage. These values must therefore not be exceeded under any conditions.

 Thermal Resistance Value
Table 7
Item

SymbolCondition

Board A
Board B
Board CHTMSOP-8
Board D
Board E
Board A
Board B
θJA
Junction-to-ambient thermal resistance*1
HSNT-8(2030) Board C
Board D
Board E
Board A
Board B
SOT-23-5
Board C
Board D
Board E
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Remark8

Refer to " Power Dissipation" and "Test Board" for details.

Min.
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−

Typ.
159
113
39
40
30
181
135
40
42
32
192
160
−
−
−

Max.
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−

Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series Electrical Characteristics
Table 8(Ta = −40°C to +125°C unless otherwise specified)
Item

SymbolCondition

Min.

Typ.

Max.

Unit

Test
CircuitVDD = 13.5 V,
VDET(S)
VDET(S)
VDET(S)
V
1
≤
18.0
V
16.0
V
≤
V
×
0.985
×
1.015
DET(S)
Detection voltage*1
VDET
VDET(S)
VDET(S)VDD = 13.5 V,
VDET(S)V1
12.2 V ≤ VDET(S) < 16.0 V
× 0.984
× 1.016
L typeVDET−−
V
1
× 0.00(VHYS = 0%)
M type
VDET
VDET
VDET
Hysteresis width*2
VHYS
V1
× 0.04
× 0.05× 0.06(VHYS = 5.0%)
N type
VDET
VDET
VDET
V
1
× 0.09× 0.10× 0.11(VHYS = 10.0%)
VDD = 13.5 V, VSENSE = 13.5 V,
−
μA
0.6
2.4
4
16.0 V ≤ VDET(S) ≤ 18.0 V
Current consumption
ISS1
VDD = 13.5 V, VSENSE = 10.0 V,
−
μA
0.6
2.4
4
12.2 V ≤ VDET(S) < 16.0 V−−
Operation voltage
VDD
3.0
36.0
V
1
OUT pin Nch driver,
−
−
0.60
mA
2
Output current
IOUT
VDD = 3.0 V, VDS*3 = 0.1 V,
VSENSE = VDET(S) + 1 V
OUT pin Nch driver,VDD = 36 V, VOUT = 36 V,
−
−
μA
2.0
2
VSENSE = 13.5 V,
16.0 V ≤ VDET(S) ≤ 18.0 V
Leakage current
ILEAK
OUT pin Nch driver,VDD = 36 V, VOUT = 36 V,
−
−
μA
2.0
2
VSENSE = 10.0 V,
12.2 V ≤ VDET(S) < 16.0 V
*4
−
−
μs
Detection response time
tRESET
80
200
3
Release delay time*5
tDELAYCD = 3.3 nF
8.5
10.0
11.5
ms
3
−
−
MΩ
SENSE pin resistance
RSENSE
6.8
200
4
−
kΩ
−
CD pin discharge ON resistance RCDD
VDD = 3.0 V, VCD = 0.7 V
0.15
0.90
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value*2. The release voltage (VREL) are as follows.
L type (hysteresis width "Unavailable"):VREL = VDET
M / N type (hysteresis width "Available"):VREL = VDET − VHYS
*3. VDS: Drain-to-source voltage of the output transistor*4. The time period from when the pulse voltage of VDET(S) − 1.0 V → VDET(S) + 1.0 V is applied to the SENSE pin after
VSENSE reaches the release voltage once, until VOUT reaches 50% of VDD.
*5. VREL(S): Set release voltage value
The time period from when the pulse voltage of VREL(S) + 1.0 V → VREL(S) − 1.0 V is applied to the SENSE pin to when
VOUT reaches 50% of VDD.

9

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
 Test Circuits
R
100 kΩ

VDD

SENSE
+
V

VSS

VDD

SENSE

OUT
CD

VSS

+

CD
V

V

Figure 6 Test Circuit 1

SENSE
VSS

Figure 7 Test Circuit 2R
100 kΩ

VDD

CD

VDD
+

OUT
Oscilloscope

Figure 8 Test Circuit 3

10

A

OUT

A
+

A

SENSE
+
V

VSS

OUT
CD

Figure 9 Test Circuit 4++

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series
 Standard Circuit
VDD

R1*2

SENSE
VSS

OUT
CD
CD*1

*1.

CD is a release delay time adjustment capacitor. The CD should be connected directly to the CD pin and the VSS
pin.
R1 are the external pull-up resistors for the reset output pin.

*2.

Figure 10
Caution

The above connection diagram and constants will not guarantee successful operation. Perform thoroughevaluation including the temperature characteristics with an actual application to set the constants.

 Condition of Application
Release delay time adjustment capacitor (CD): A ceramic capacitor with capacitance of 1.0 nF or more is recommended.

 Selection of Release Delay Time Adjustment Capacitor (CD)In this IC, the release delay time adjustment capacitor (CD) is necessary between the CD pin and the VSS pin to adjust
the release delay time (tDELAY) of the detector. Refer to "1. 4 Delay circuit" in " Operation" for details.
Caution

Perform thorough evaluation including the temperature characteristics with an actual application to
select CD.

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AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
 Explanation of Terms
1.

Detection voltage (VDET)The detection voltage is a SENSE pin voltage at which the output voltage in Figure 13 turns to "L". The detection
voltage varies slightly among products of the same specification. The variation of detection voltage between thespecified minimum and the maximum is called the detection voltage range (Refer to "Figure 11 Detection Voltage").
Example: In VDET = 16.0 V product, the detection voltage is at any point in the range of 15.760 V ≤ VDET ≤ 16.240 V.
This means that some VDET = 16.0 V product has VDET = 15.760 V and some has VDET = 16.240 V.

2.

Release voltage (VREL)
The release voltage is a SENSE pin voltage at which the output voltage in Figure 13 turns to "H". The release voltage
varies slightly among products of the same specification. The variation of release voltage between the specified
minimum and the maximum is called the release voltage range (Refer to "Figure 12 Release Voltage").
The release voltage becomes the value differs from the detection voltage within the range shown below.
• M type: 4% to 6% (5% typ.)• N type: 9% to 11% (10% typ.)Example: For N type, VDET = 16.0 V product, the release voltage is at any point in the range of 14.026 V ≤ VREL ≤14.779 V despite VREL = 14.400 V typ.
This means that some N type, VDET = 16.0 V product has VREL = 14.026 V and some has VREL =14.779 V.

12AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series
VSENSE

Detection voltage
VDET max.

VREL max.

Detection voltage
range

VDET min.
VSENSE

Release voltage
Release voltage
range

VREL min.

tRESETtDELAYVOUT

VOUT

Figure 11 Detection Voltage

Figure 12 Release Voltage

VDD

R1
100 kΩ

VDD
SENSE

+
V
VSENSE

VSS

OUT
CD

+
V
CD

Figure 13 Test Circuit of Detection Voltage and Release Voltage

3.

Hysteresis width (VHYS)
The hysteresis width is the voltage difference between the detection voltage (VDET) and the release voltage (VREL).
Voltage difference between VREL and VDET is the hysteresis width (VHYS*1) of the OUT pin. Setting the hysteresis width
between VDET and VREL, prevents malfunction caused by noise on the input voltage.
*1.

4.

Refer to "1. 2

S-19115 Series M / N type" in "■ Operation" for details.

Feed-through current
The feed-through current is a current that flows instantaneously to the VDD pin at the time of detection and release of
a voltage detector.

13

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
 Operation
1.

Basic operation
Figure 14 and Figure 16 show that the OUT pin being pulled up by resistors (R1) is an example of basic detector block
operation.
1. 1

S-19115 Series L type(1) Release status to detection status
The SENSE pin voltage (VSENSE) rises, and when it exceeds the detection voltage (VDET), the OUT pin output
becomes "L" after detection response time (tRESET).
(2) Detection status to release status
VSENSE drops, and when it goes below the release voltage (VREL = VDET), the OUT pin output changes to "H"after release delay time (tDELAY).

R1
100 kΩ

VDD

SENSE
OUT
VOUT
−
VDD

+

VSENSE*1

Delay
circuit

VREF
VSS

+

*1

*1

CD
CD

*1. Parasitic diodeFigure 14 Operation of S-19115 Series L type14

V

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series

(1)
VDET

(2)
VREL

VSENSEt RESETt DELAY

VOUT

Figure 15 Timing Chart of S-19115 Series L Type

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AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
1. 2

S-19115 Series M / N type(1) Release status to detection status
The SENSE pin voltage (VSENSE) rises, and when it exceeds the detection voltage (VDET), the OUT pin output
becomes "L" after detection response time (tRESET).
(2) Detection status to release status
VSENSE drops, and when it goes below the release voltage (VREL = VDET − VHYS), the OUT pin output changes to"H" after release delay time (tDELAY).

R1
100 kΩ

VDD

SENSE
OUT
VOUT
−
VDD

+

VSENSE*1

Delay
circuit

VREF
VSS

*1

*1

CD
CD

*1. Parasitic diodeFigure 16 Operation of S-19115 Series M / N type

16

+
V

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series

(1)

(2)

VDET

VREL
VHYS

VSENSEt RESETt DELAY

VOUT

Figure 17 Timing Chart of S-19115 Series M / N Type17

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
1. 3

SENSE pin

The SENSE pin is the input pin for the detection voltage. The power supply VDD pin and SENSE pin, for voltage
detection, are divided. Therefore, as long as a voltage is supplied to the VDD pin, the release signal will be heldeven if the input voltage to the SENSE pin drops below the minimum operation voltage. Also, the SENSE pin of thisIC has a built-in reverse connection protection circuit. Even when the SENSE pin voltage is less than the VSS pin
voltage, the current flowing from the VSS pin to the SENSE pin is reduced to 0.05 mA typ.
1. 3. 1

Error when detection voltage is set externally

The detection voltage can be set externally by connecting a node that was resistance-divided by the resistor (RA)and the resistor (RB) to the SENSE pin as shown in Figure 18.
For conventional products without the SENSE pin, external resistor cannot be too large since theresistance-divided node must be connected to the VDD pin. This is because a feed-through current will flow
through the VDD pin when it goes from detection to release, and if external resistor is large, problems such as
oscillation or larger error in the hysteresis width may occur.
In this IC, RA and RB in Figure 18 are easily made larger since the resistance-divided node can be connected to
the SENSE pin through which no feed-through current flows. However, be careful of error in the current flowing
through the internal resistance (RSENSE) that will occur.
Although RSENSE*1 in this IC is large to make the error small, RA and RB should be selected such that the error iswithin the allowable limits.
*1. 6.8 MΩ min.

18

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series
1. 3. 2

Selection of RA and RB

In Figure 18, the relation between the external setting detection voltage (VDX) and the actual detection voltage(VDET) is ideally calculated by the equation below.
RA
VDX = VDET × (1 + R ) ·········································(1)B

However, in reality there is an error in the current flowing through RSENSE.
When considering this error, the relation between VDX and VDET is calculated as follows.
RA
VDX = VDET × (1 + R || R
)
B
SENSE
RA

= VDET × 1 +
 RB × RSENSE  RB + RSENSE RARA× VDET ················(2)= VDET × (1 + R ) + R
B
SENSE
By using equations (1) and (2), the error is calculated as VDET × R

RA

SENSE

.

The error rate is calculated as follows by dividing the error by the right-hand side of equation (1).
RA || RB
RA × RB
× 100 [%] = R
× 100 [%] ····(3)SENSE
RSENSE × (RA + RB)
As seen in equation (3), the smaller the resistance values of RA and RB compared to RSENSE, the smaller the error
rate becomes.
Also, the relation between the external setting hysteresis width (VHX) and the hysteresis width (VHYS) is calculated
by equation below. Error due to RSENSE also occurs to the relation in a similar way to the detection voltage.
RA
VHX = VHYS × (1 + R ) ··········································(4)
B

A

VDX

RA
VDET

VDD
SENSE

OUT

RSENSERB

VSS

Figure 18 Detection Voltage External Setting Circuit
CautionIf RA and RB are large, the SENSE pin input impedance becomes higher and may cause a
malfunction due to noise. In this case, connect a capacitor between the SENSE pin and the
VSS pin.

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AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
1. 4

Delay circuit

The delay circuit comes with a function for adjusting the release delay time (tDELAY) from when the SENSE pin
voltage (VSENSE) reaches the detection voltage (VREL = VDET − VHYS) or lower to when the output from OUT pin
inverts.
tDELAY is determined by the delay coefficient, the release delay time adjustment capacitor (CD) and the release delay
time when the CD pin is open (tDELAY0). They are calculated by the equations below.
tDELAY [ms] = Delay coefficient × CD [nF] + tDELAY0 [ms]Table 9Operation
Temperature
Ta = +125°C
Ta = +105°C
Ta = +25°C
Ta = −40°C

Min.

Delay Coefficient
Typ.

Max.

2.65
2.71
2.92
2.65

3.03
3.05
3.06
3.09

3.41
3.35
3.14
3.41

Table 10
Operation
Temperature
Ta = +125°C
Ta = +105°C
Ta = +25°C
Ta = −40°C
Caution 1.

2.

3.

20

Release Delay Time when CD Pin is Open (tDELAY0)
Min.
Typ.
Max.
0.05
0.05
0.06
0.06

0.09
0.10
0.11
0.13

0.17
0.17
0.19
0.25

Mounted board layout should be made in such a way that no current flows into or flows fromthe CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot beprovided.
There is no limit for the capacitance of CD as long as the leakage current of the capacitor canbe ignored against the built-in constant current value (approximately 160 nA). The leakage
current may cause error in delay time. When the leakage current is larger than the built-in
constant current, no detect or release takes place.
The above equations will not guarantee successful operation. Determine the capacitance of CD
through thorough evaluation including temperature characteristics in the actual usage
conditions.

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series
 Usage Precautions
1.

Power on sequence
Turn on the power in one of the following two procedures.
(1) Order of VDD pin and SENSE pin (Refer to Figure 19)(2) VDD pin and SENSE pin at the same time

VDD

VDD min.

VSENSEtDELAY
VOUT

Figure 19
CautionWhen the SENSE pin is turned on before the VDD pin, a detection may mistakenly occur even if
VSENSE is less than VDET.

21

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
2.

SENSE pin voltage glitch (Typical data)
2. 1

Detection operation

Figure 20 shows the relation between pulse width and pulse voltage difference (VOD) where the release status canbe maintained when a pulse equal to or higher than the detection voltage (VDET) is input to the SENSE pin during
release status.
Tj = −40°C to +150°C

Pulse width [µs]1000

Pulse width

100

VIH*1

10

VOD

VOUT = “H”

VSENSE VDET

1
0.1
10

100
VOD [mV]

VIL*2

1000

tr = 1 µs*1.
*2.

Figure 20
Caution

2. 2

tf = 1 µs

VIH = VDET + VOD
VIL = 13.5 V (16.0 V ≤ VDET(S) ≤ 18.0 V)

Figure 21 SENSE Pin Input Voltage Waveform

Figure 20 shows the pulse condition which can maintain the release status. If the pulse whose
pulse width and VOD are larger than this condition is input to the SENSE pin, the OUT pin may
change to a detection status.

Release operation

Figure 22 shows the relation between pulse width and pulse voltage difference (VOD) where the detection status
can be maintained when a pulse equal to or lower than the release voltage (VREL) is input to the SENSE pin during
detection status.
Tj = −40°C to +150°C

Pulse width [µs]1000

Pulse width

100
VIH*1

10
VOUT = “L”
1

VSENSE VREL

0.1

VIL*2

VOD
10

100
VOD [mV]

1000

tf = 1 µs*1.
*2.

Figure 22
Caution22

tr = 1 µs

VIH = VDET + 1.0 V
VIL = VREL − VOD

Figure 23 SENSE Pin Input Voltage Waveform

Figure 22 shows the pulse condition which can maintain the detection status. If the pulse whose
pulse width and VOD are larger than this condition is input to the SENSE pin, the OUT pin may
change to a release status.

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series
 Precautions• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• Because the SENSE pin has a high impedance, malfunctions may occur due to noise.
Be careful of wiring adjoining SENSE pin wiring in actual applications.
• When designing for mass production using an application circuit described herein, the product deviation andtemperature characteristics should be taken into consideration. ABLIC Inc. shall not bear any responsibility for patent
infringements related to products using the circuits described herein.
• ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.

23

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
 Characteristics (Typical Data)
Detection voltage (VDET), Release voltage (VREL) vs. Temperature (Ta)VDET(S) = 12.2 V, VREL(S) = 10.98 V, VDD = 13.5 V
12.6

VDET(S) = 16.0 V, VREL(S) = 14.4 V, VDD = 13.5 V
16.5

12.2

16.0

VDET, VREL [V]

VDET, VREL [V]

1.

VDET

11.8
11.4

VREL

11.0
10.6
10.2
-40 -2502550Ta [°C]

75

100

VDET

15.5

VREL

15.0
14.5
14.0
13.5
-40 -25

125

0

25
50
Ta [°C]

75

100

125

VDET, VREL [V]

VDET(S) = 18.0 V, VREL(S) = 16.2 V, VDD = 13.5 V
18.5

18.0
17.5

VDET

17.0

VREL

16.5
16.0
15.5
-40 -25

75

100

125

Detection voltage (VDET), Release voltage (VREL) vs. Power supply voltage (VDD)
VDET(S) = 12.2 V, VREL(S) = 10.98 V

VDET, VREL [V]

12.6
12.2

VDET

11.8

Ta = -40°C
Ta = +25°C
Ta = +125°C
Ta = +25°C
Ta = +125°C

11.4
11.0

VREL

10.6
10.2

0

6

VDET, VREL [V]

18.0

12

18
24
VDD [V]

30

36

V DET

17.5

Ta = -40°C
Ta = +25°C
Ta = +125°C
Ta = +25°C
Ta = +125°C

17.0
16.5
16.0
15.5

Ta = -40°C

VDET(S) = 18.0 V, VREL(S) = 16.2 V

18.5

24

25
50
Ta [°C]

VREL
0

6

Ta = -40°C
12

18
24
VDD [V]

30

36

VDET(S) = 16.0 V, VREL(S) = 14.4 V

16.5

VDET, VREL [V]

2.

0

16.0

V DET

15.5

Ta = -40°C
Ta = +25°C
Ta = +125°C
Ta = +25°C
Ta = +125°C

15.0
14.5

VREL

14.0
13.5

0

6

Ta = -40°C
12

18
24
VDD [V]

30

36

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series

3.

Hysteresis width (VHYS) vs. Temperature (Ta)11

VDET(S) = 16.0 V, VREL(S) = 14.4 V, VDD = 13.5 V
12

VHYS [%]

VHYS [%]VDET(S) = 12.2 V, VREL(S) = 10.98 V, VDD = 13.5 V
12

10
9

11
10
9

8
-40 -2502550Ta [°C]75

100

8-40 -25

125

0

25
50
Ta [°C]

75

100

125

VHYS [%]VDET(S) = 18.0 V, VREL(S) = 16.2 V, VDD = 13.5 V
12

11
10
9
8
-40 -252550
Ta [°C]

75

100

125

Hysteresis width (VHYS) vs. Power supply voltage (VDD)
VDET(S) = 12.2 V, VREL(S) = 10.98 V

VDET(S) = 16.0 V, VREL(S) = 14.4 V

12

Ta = -40°C

11

Ta = +25°C

VHYS [%]

VHYS [%]

12

10
Ta = +125°C

9
8

0

6

12

Ta = -40°C

11
10

Ta = +125°C

9

18
24
VDD [V]30

36

Ta = +25°C

8

0

6

12

18
24
VDD [V]

30

36

VDET(S) = 18.0 V, VREL(S) = 16.2 V

12

VHYS [%]

4.

0

Ta = -40°C

11

Ta = +25°C

10
Ta = +125°C

9
8

0

6

12

18
24
VDD [V]

30

36

25

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
Current consumption (ISS1) vs. Temperature (Ta)VDET(S) = 12.2 V, VDD = 13.5 V, VSENSE = 10.0 V(during release)
1.5

VDET(S) = 16.0 V, VDD = 13.5 V, VSENSE = 13.5 V(during release)
1.5

1.2

1.2

ISS1 [µA]

ISS1 [µA]

5.

0.9
0.6
0.3
0.0
-40 -25

0.9
0.6
0.3

0

25
50
Ta [°C]

75

100

0.0
-40 -25

125

0

25
50
Ta [°C]

75

100

125

VDET(S) = 18.0 V, VDD = 13.5 V, VSENSE = 13.5 V(during release)
1.5

ISS1 [µA]

1.2
0.9
0.6
0.3
0

25
50
Ta [°C]

75

100

125

VDET(S) = 12.2 V, VDD = 13.5 V, VSENSE = 13.2 V(during detection)
1.5

VDET(S) = 16.0 V, VDD = 13.5 V, VSENSE = 17.0 V(during detection)
1.5

1.2

1.2

ISS1 [µA]

ISS1 [µA]0.0-40 -25

0.9
0.6
0.3
0.0
-40 -2502550Ta [°C]

75

100

125

ISS1 [µA]

1.2
0.9
0.6
0.3

26

0.6
0.3

VDET(S) = 18.0 V, VDD = 13.5 V, VSENSE = 19.0 V(during detection)
1.5

0.0-40 -25

0.9

0

25
50
Ta [°C]

75

100

125

0.0
-40 -2502550Ta [°C]

75

100

125

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series
6. Current consumption (ISS1) vs. Power supply voltage (VDD) (No load)
VDET(S) = 12.2 V,
VDD = 0 V → 36.0 V, VSENSE = 10.0 V(during release)

VDET(S) = 16.0 V,
VDD = 0 V → 36.0 V, VSENSE = 13.5 V(during release)

1.5

Ta = +125°C

1.0

ISS1 [µA]

ISS1 [µA]1.5

Ta = -40°C

Ta = +25°C
0.5
0.0

0

6

12

18
24
VDD [V]30

Ta = -40°C

Ta = +25°C
0.5
0.0

36

Ta = +125°C

1.0

0

6

12

18
24
VDD [V]

30

36

VDET(S) = 18.0 V,
VDD = 0 V → 36.0 V, VSENSE = 13.5 V(during release)

1.5

ISS1 [µA]

Ta = +125°C
1.0
Ta = +25°C

Ta = -40°C

0.5
0.0

0

6

12

18
24
VDD [V]

30

36

VDET(S) = 12.2 V,
VDD = 0 V → 36.0 V, VSENSE = 13.2 V(during detection)

VDET(S) = 16.0 V,
VDD = 0 V → 36.0 V, VSENSE = 17.0 V(during detection)

1.5

1.5

1.0

Ta = +125°C

ISS1 [µA]

ISS1 [µA]

Ta = +125°C
Ta = -40°C

Ta = +25°C

0.5
0.0

0

6

12

18
24
VDD [V]

30

36

1.0

Ta = +25°C

Ta = -40°C

0.5
0.0

0

6

12

18
24
VDD [V]

30

36

VDET(S) = 18.0 V,
VDD = 0 V → 36.0 V, VSENSE = 19.0 V(during detection)

1.5

ISS1 [µA]

Ta = +125°C
1.0
Ta = +25°C

Ta = -40°C

0.5
0.0

0

6

12

18
24
VDD [V]

30

36

27

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
7.

Nch transistor output current (IOUT) vs. VDS
VDET(S) = 18.0 V, VSENSE = 19.0 V, Ta = −40°C
10

VDD = 36.0 V

68
IOUT [mA]

8
IOUT [mA]

VDET(S) = 18.0 V, VSENSE = 19.0 V, Ta = +25°C
10

VDD = 13.5 V

42

VDD = 36.0 V

6VDD = 13.5 V

42

VDD = 3.0 V

0

VDD = 3.0 V

0
0.0

0.1

0.2

0.3
0.4
VDS [V]

0.5

0.6

0.0

0.1

0.2

0.3
0.4
VDS [V]

0.5

0.6

VDET(S) = 18.0 V, VSENSE = 19.0 V, Ta = +125°C
10

IOUT [mA]8

VDD = 36.0 V

6VDD = 13.5 V

4

VDD = 3.0 V

2
0
0.0

0.1

0.2

0.3
0.4
VDS [V]

0.5

0.6

Remark VDS: Drain-to-source voltage of the output transistor

8.

Nch transistor output current (IOUT) vs. Power supply voltage (VDD)

IOUT [mA]

VDET(S) = 18.0 V, VDS = 0.1 V, VSENSE = 36.0 V
1.5

1.0

Ta = -40°C

Ta = +25°C

0.5
Ta = +125°C
0.0
0

6

12

18
24
VDD [V]

30

36

Remark VDS: Drain-to-source voltage of the output transistor

9.

Output voltage (VOUT) vs. SENSE pin voltage (VSENSE)

32

Ta = +25°C

1

Ta = +125°C

028

Ta = -40°C

0

3

6

9
12
VSENSE [V]VDET(S) = 18.0 V, VREL(S) = 16.2 V, VDD = 3.0 V,
pull-up to 16.0 V, pull-up resistance: 100 kΩ
20

VOUT [V]

VOUT [V]VDET(S) = 18.0 V, VREL(S) = 16.2 V, VDD = 3.0 V,
pull-up to VDD, pull-up resistance: 100 kΩ
4

15

18

21

15

Ta = -40°C

10

Ta = +25°C

5

Ta = +125°C

0

0

3

6

9
12
VSENSE [V]

15

18

21

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series

Response time [ms]10

VDET(S) = 18.0 V, VREL(S) = 16.2 V,
VDD = 13.5 V, Ta = −40°C

Response time [ms]Response time [ms]10. Dynamic response vs. Output pin capacitance (COUT) (CD pin; open)

tPLH

1
0.1
0.01
0.001
0.00001

10tPHL
0.00010.001
COUT [µF]

0.01

0.1

VDET(S) = 18.0 V, VREL(S) = 16.2 V,
VDD = 13.5 V, Ta = +25°C

10

tPLH

1
0.1

tPHL

0.01
0.001
0.00001

0.00010.001
COUT [µF]

0.01

0.1

VDET(S) = 18.0 V, VREL(S) = 16.2 V,
VDD = 13.5 V, Ta = +125°C

tPLH

1
0.1

tPHL

0.01
0.001
0.00001

0.00010.001
COUT [µF]

0.01

0.1

VIH1*1
VIH2*2VSENSE
VIL1*3VIL2*4
tPLH
VOUT

tPHL

VDD1 × 50%

*1.
*2.
*3.
*4.

VDD1 × 50%

VIH1 = VDET(S) + 1.0 V
VIH2 = VREL(S) + 1.0 V
VIL1 = VDET(S) − 1.0 V
VIL2 = VREL(S) − 1.0 V

Figure 24 Test Condition of Response TimeR
100 kΩVDD

VSENSE

OUT

SENSE

VDD
V

+

VSS

CD
V

+

VDD1

Figure 25 Test Circuit of Response Time
Caution 1.

2.

The above connection diagram and constants will not guarantee successful operation. Perform
thorough evaluation including the temperature characteristics with an actual application to set theconstants.
When the CD pin is open, a double pulse may appear at release.
To avoid the double pulse, attach 1 nF or more capacitor to the CD pin.

29

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
 Reference Data1.

Detection response time (tRESET) vs.
Temperature (Ta)2.

Detection response time (tRESET) vs.
Power supply voltage (VDD)
VDET(S) = 18.0 V, VREL(S) = 16.2 V,
CD = 3.3 nF

200

200

150

150

tRESET [µs]tRESET [µs]VDET(S) = 18.0 V, VREL(S) = 16.2 V,
VDD = 13.5 V, CD = 3.3 nF

100
50
0
-40 -2502550Ta [°C]

75

100

Ta = +25°C

100
50
0

125

Ta = -40°C

Ta = +125°C
0

6

12

18
24
VDD [V]

30

36

1 µs
VIH*1
VSENSE
VIL*2

R
100 kΩVDD

tRESET
VDD

VDD
VOUT

VDD × 50%

V

+

SENSE
VSS

OUT
CD
V

VSENSE

+

CD

VSS
*1.
*2.

VIH = VDET(S) + 1.0 V
VIL = VDET(S) − 1.0 V

Figure 26 Test Condition of Detection Response Time
Caution30

Figure 27 Test Circuit of Detection Response TimeThe above connection diagram and constants will not guarantee successful operation. Perform thoroughevaluation including the temperature characteristics with an actual application to set the constants.

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series
3.

Release delay time (tDELAY) vs. Temperature (Ta)12

4. Release delay time (tDELAY) vs. Power supply voltage (VDD)

VDET(S) = 18.0 V, VREL(S) = 16.2 V,
VDD = 13.5 V, CD = 3.3 nF

VDET(S) = 18.0 V, VREL(S) = 16.2 V,
CD = 3.3 nF

12

10
9
8
-40 -25

5.

tDELAY [ms]tDELAY [ms]Ta = -40°C
11

0

25
50
Ta [°C]

75

100

10
9
8

125

Ta = +25°C

11

Ta = +125°C
0

6

12

18
24
VDD [V]30

36

Release delay time (tDELAY) vs. CD pin capacitance (CD) (Without output pin capacitance)
1000

VDET(S) = 18.0 V, VREL(S) = 16.2 V

Ta = +25°C

tDELAY [ms]10010Ta = -40°C

1
0.1
0.01
0.01

Ta = +125°C
0.1

1
CD [nF]

10

100

1 µs
VIH*1
VSENSE
VIL*2

R
100 kΩVDD
tDELAY

VDD

VDD
VOUT

VDD × 50%

V

+

SENSE
VSS

OUT
CD
V

VSENSE

+

CD

VSS
*1.
*2.

VIH = VREL(S) + 1.0 V
VIL = VREL(S) − 1.0 V

Figure 28 Test Condition of Release Delay Time
CautionFigure 29 Test Circuit of Release Delay TimeThe above connection diagram and constants will not guarantee successful operation. Perform thoroughevaluation including the temperature characteristics with an actual application to set the constants.

31

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
S-19115xxxA Series
Rev.1.3_00
Load dump characteristics (Ta = +25°C)
6. 1

VDET(S) = 18.0 V

VDD = VSENSE = 13.5 V ↔ 45.0 V,
VDD1 = 5.0 V, CD = 3.3 nF

VOUT [V]

25.0

50

20.0

40

15.0

30

10.0
5.0
0.0

20

VDD

10

VOUT

−5.0
−0.2

0
0.0

0.2

0.4

0.6

0.8

−10

VDD [V]

6.

R
100 kΩ

VDD
SENSE

VDD
V

+

VSS

VDD1
CD

OUT
CD

t [s]
Figure 30

32

V

+

AUTOMOTIVE, 125°C OPERATION, 36 V, VOLTAGE DETECTOR FOR OVERVOLTAGE DETECTION WITH DELAY FUNCTION (EXTERNAL DELAY TIME SETTING)
Rev.1.3_00
S-19115xxxA Series Power Dissipation
HTMSOP-8

HSNT-8(2030)
Tj = +150°C max.

5

Tj = +150°C max.

5
Power dissipation (PD) [W]Power dissipation (PD) [W]

E
4
C
3 D
2
B
1

E

4

C
3

D

2
B

1

A
0

0

A
25

50

75

100

125

150

175

0

0

25

Ambient temperature (Ta) [°C]
Board
A
B
C
D
E

50

75

100

125

150

175

Ambient temperature (Ta) [°C]Power Dissipation (PD)
0.79 W
1.11 W
3.21 W
3.13 W
4.17 W

Board
A
B
C
D
E

Power Dissipation (PD)0.69 W
0.93 W
3.13 W
2.98 W
3.91 W

SOT-23-5
Tj = +150°C max.

Power dissipation (PD) [W]

5
4
3
2
1 B
A
0

0

25

50

75

100

125

150

175

Ambient temperature (Ta) [°C]
Board
A
B
C
D
E

Power Dissipation (PD)
0.65 W
0.78 W−−−

33

HTMSOP-8 Test Board
IC Mount Area

(1) Board A
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]

1
2
3
4

Thermal via

Specification
114.3 x 76.2 x t1.6
FR-4
2Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070-(2) Board B
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]

1
2
3
4

Thermal via

Specification
114.3 x 76.2 x t1.6
FR-4
4Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070-(3) Board C
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]Thermal via

1
2
3
4

Specification
114.3 x 76.2 x t1.6
FR-4
4Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
Number: 4
Diameter: 0.3 mm

No. HTMSOP8-A-Board-SD-1.0

enlarged view

ABLIC Inc.

HTMSOP-8 Test Board
IC Mount Area
(4) Board D
Item
Size [mm]Material
Number of copper foil layer

Specification
114.3 x 76.2 x t1.6
FR-4
4

Thermal via

2
Pattern for heat radiation: 2000mm t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070-

Item
Size [mm]Material
Number of copper foil layer

Specification
114.3 x 76.2 x t1.6
FR-4
4

Copper foil layer [mm]

1
2
3
4

enlarged view

(5) Board E

Copper foil layer [mm]Thermal via

1
2
3
4

2
Pattern for heat radiation: 2000mm t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070

Number: 4
Diameter: 0.3 mm

enlarged viewNo. HTMSOP8-A-Board-SD-1.0

ABLIC Inc.

HSNT-8(2030) Test Board
IC Mount Area
(1) Board A
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]

1
2
3
4

Thermal via

Specification
114.3 x 76.2 x t1.6
FR-4
2Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070-(2) Board B
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]

1
2
3
4

Thermal via

Specification
114.3 x 76.2 x t1.6
FR-4
4Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070-(3) Board C
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]Thermal via

1
2
3
4

Specification
114.3 x 76.2 x t1.6
FR-4
4Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
Number: 4
Diameter: 0.3 mm

enlarged viewNo. HSNT8-A-Board-SD-2.0

ABLIC Inc.

HSNT-8(2030) Test Board
IC Mount Area
(4) Board D
Item
Size [mm]Material
Number of copper foil layer

Specification
114.3 x 76.2 x t1.6
FR-4
4

Thermal via

2
Pattern for heat radiation: 2000mm t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070-

Item
Size [mm]Material
Number of copper foil layer

Specification
114.3 x 76.2 x t1.6
FR-4
4

Copper foil layer [mm]

1
2
3
4

enlarged view

(5) Board E

Copper foil layer [mm]Thermal via

1
2
3
4

2
Pattern for heat radiation: 2000mm t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070

Number: 4
Diameter: 0.3 mm

enlarged viewNo. HSNT8-A-Board-SD-2.0

ABLIC Inc.

SOT-23-3/3S/5/6 Test Board
IC Mount Area

(1) Board A
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]

1
2
3
4

Thermal via

Specification
114.3 x 76.2 x t1.6
FR-4
2Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070-(2) Board B
Item
Size [mm]Material
Number of copper foil layer

Copper foil layer [mm]Thermal via

1
2
3
4

Specification
114.3 x 76.2 x t1.6
FR-4
4Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070-

No. SOT23x-A-Board-SD-2.0

ABLIC Inc.

2.90±0.2
1.85
8

5

1

4

0.13±0.1

0.2±0.1
0.65±0.1

No. FP008-A-P-SD-2.0

TITLE

HTMSOP8-A-PKG Dimensions

No.

FP008-A-P-SD-2.0

ANGLE
UNIT

mm

ABLIC Inc.

2.00±0.05
4.00±0.1

4.00±0.1

1.00±0.1+0.1

1.5 -01.05±0.05

0.30±0.05

3.25±0.05

4

1

5

8

Feed direction

No. FP008-A-C-SD-1.0

TITLE

HTMSOP8-A-Carrier Tape

No.

FP008-A-C-SD-1.0

ANGLE
UNIT

mm

ABLIC Inc.

+1.0

13.0 - 0.0
15.4±1.0

Enlarged drawing in the central part

ø13±0.2

(60°)

(60°)

No. FP008-A-R-SD-2.0

TITLE

HTMSOP8-A-ReelNo.

FP008-A-R-SD-2.0

ANGLE

QTY.

UNIT

mm

ABLIC Inc.

4,000

0.35

1.90

0.65

0.65

0.65

No. FP008-A-L-SD-2.0

TITLE

HTMSOP8-A-Land Recommendation

No.

FP008-A-L-SD-2.0

ANGLE
UNIT

mm

ABLIC Inc.

2.0±0.185(1.70)

+0.05

1

4

0.08 -0.02

0.5

0.23±0.1

The heat sink of back side has different electric
potential depending on the product.
Confirm specifications of each product.
Do not use it as the function of electrode.

No. PP008-A-P-SD-2.0

TITLE

HSNT-8-A-PKG Dimensions

No.

PP008-A-P-SD-2.0

ANGLE
UNIT

mm

ABLIC Inc.

+0.1

ø1.5 -0

2.0±0.05

4.0±0.1

0.25±0.05+0.1

0.60±0.05

ø1.0 -0

4.0±0.1

2.3±0.05

4 321

5 6 78Feed direction

No. PP008-A-C-SD-1.0

TITLE

HSNT-8-A-Carrier TapeNo.

PP008-A-C-SD-1.0

ANGLE
UNIT

mm

ABLIC Inc.

+1.0

9.0 - 0.0
11.4±1.0

Enlarged drawing in the central part

ø13±0.2

(60°)

(60°)

No. PP008-A-R-SD-2.0

TITLE

HSNT-8-A-ReelNo.

PP008-A-R-SD-2.0

ANGLE

QTY.

UNIT

mm

ABLIC Inc.

5,000

1.6

0.30

0.50

No. PP008-A-L-SD-1.0

TITLE
No.

HSNT-8-A-Land Recommendation
PP008-A-L-SD-1.0

ANGLE
UNIT

mm

ABLIC Inc.

2.9±0.2
1.9±0.2
4

5

1

2

+0.1

0.16 -0.06

30.95±0.1
0.4±0.1

No. MP005-A-P-SD-1.3

TITLE

SOT235-A-PKG Dimensions

No.

MP005-A-P-SD-1.3

ANGLE
UNIT

mm

ABLIC Inc.

4.0±0.1(10 pitches:40.0±0.2)+0.1

ø1.5 -0+0.2

ø1.0 -0

2.0±0.05

0.25±0.1

4.0±0.1

1.4±0.2

3.2±0.2

3 2 1

4

5

Feed direction

No. MP005-A-C-SD-2.1

TITLE

SOT235-A-Carrier Tape

No.

MP005-A-C-SD-2.1

ANGLE
UNIT

mm

ABLIC Inc.

+1.0

9.0 - 0.0
11.4±1.0

Enlarged drawing in the central part

ø13±0.2

(60°)

(60°)

No. MP005-A-R-SD-2.0

TITLE

SOT235-A-Reel

No.

MP005-A-R-SD-2.0

ANGLE

QTY.

UNIT

mm

ABLIC Inc.

3,000

Disclaimers (Handling Precautions)1.

All the information described herein (product data, specifications, figures, tables, programs, algorithms andapplication circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.

2.

The circuit examples and the usages described herein are for reference only, and do not guarantee the success ofany specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any otherright due to the use of the information described herein.

3.

ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information describedherein.

4.

Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due tothe use of the products outside their specified ranges.

5.

Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.

6.

When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-relatedlaws, and follow the required procedures.

7.

The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,biological or chemical weapons or missiles, or use any other military purposes.

8.

The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.

9.

In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products areallowed to apply for the system on customer's own responsibility.

10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of thisdocument described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07

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