S-US55D2
www.ablic.com

OCTAL DAC WITH DIFFERENTIAL OUTPUTS
AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER© ABLIC Inc., 2021-2023

Rev.1.2_00

The ABLIC S-US55D2 is an octal, 12-bit, 200MSPS, Digital-to-Analog Converter (DAC) with analog differential outputs and 2-bit
per channel CMOS output pattern generators. It is designed for an ultrasound linear amplifier with 3-level pulser (3LP). Eachchannel has a 12bit x 4096 DAC pattern memory and a 128Byte 3LP pattern memory. The S-US55D2 is suitable as the input
signal pattern generator to the S-UM55L2 ultrasound transmitter.
■ Function• Octal DAC with differential outputs and 2-bit per channel CMOS output pattern generators for an ultrasound transmitter■ Features<DAC>• On-chip 12bit x4096 pattern Memory for each DAC• 0.16μs to 40.96μs programmable delay time with 5ns resolution from TRIG signal• 200MSPS sampling rate
• Both current output mode and voltage output mode are available.
• 14Ω/2Ω output impedance are selectable at voltage output mode.
• 1.28mA ~ 10.24mA selectable full-scale current @Current output mode
• 0.074V~0.592V (0.083V~0.664V) selectable full-scale voltage @voltage output mode
<3LP pattern generator>• On-chip 128Byte pattern Memory for each 3LP pattern generator• 0.16μs to 40.96μs programmable delay time with 5ns resolution from TRIG signal<Others>• Serial Peripheral Interface (SPI) for access to Memory and Register.
• 1.8V to 3.3V CMOS control logic interface• Latch-up free, low crosstalk by SOI CMOS technology• 68-lead 10x10mm QFN package (RoHS compliant)

1

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2■ Contents
Block Diagram
Absolute Maximum Ratings
Operating Supply Voltage and Temperature
LVDS Differential Logic Inputs
CMOS Logic Inputs & Outputs
Open Drain Outputs
Typical Application Circuit (current output)
Typical Application Circuit (voltage output)
Operating Supply Currents (1)Operating Supply Currents (2)Operating Supply Currents (3)Static Characteristics
Dynamic Characteristics
Tx Pattern Width and Delay Digital Control Table
SPI Header Configuration
Access to DAC Memory with SPI
Access to 3LP Data Memory with SPI
Access to Control Register with SPI
Access to CRC & ERROR Register with SPI
Definition of SDOUT Propagation Delay
Operation Mode
Operation Sequence Example
Tx Pattern Generation Timing Chart
Tx Pattern Generation Timing Chart when use 200MHz CLKTx Timing chart on "TXONFLAG"DAC Block Diagram (Current Output mode)
DAC Equations & Parameter Definitions (Current mode)
DAC Block Diagram (Voltage Output mode)
DAC Equations & Parameter Definitions (Voltage mode)
3LP DATA & DRVSEL Generator Block Diagram
DAC Memory MAP
3LP Data Memory MAP
Register Function (1)Register Function (2)Register Function (3)Control Register Map (1)Control Register Map (2)Control Register Map (3)Control Register Map (4)Control Register Map (5)CRC & Error Register function (1)CRC & Error Register function (2)CRC & Error Register MAP
Truth TablePIN Descriptions
Pin Configuration
Package
Storage, Mounting
Important Notice
Cautions
Package outline, tray, marking, land recommendation and packing
Disclaimers (Handling Precautions)

2

p.3
p.4
p.5
p.6
p.7
p.8
p.9
p.10
p.11
p.12
p.13
p.14
p.15
p.16
p.17
p.18
p.19
p.20
p.21
p.22
p.23
p.24-25
p.26-27
p.28-29
p.30
p.31
p.32
p.33
p.34
p.35
p.36
p.37
p.38
p.39
p.40
p.41
p.42
p.43
p.44
p.45
p.46
p.47
p.48
p.49-50
p.51
p.52
p.53
p.53
p.54
p.55
p.56–60
p.61

VLLIO(1.8 to 3.3V)
TXONFLAG

TXONFLAG

EXT_SIGB

CMOS
Logic I/F

FAULT

Fault

DVDD(+3.3V)

VLL(1.8V)

RBGR

EN
CLK
TRIG

DRVSEL
Generator<CH#7><CH#6><CH#5><CH#4>

SEL

Register

DRVSELyTRIG
CLKEN
SPI I/O+-SPI_OFF
CSP
CSN
SCLKP
SCLKN
SDATAP
SDATAN

CLKN
TRIG

120
120
120
120

RegisterParameter<CH#3><CH#2><CH#1><CH#0>

EN

USE_EXTSIG
Ch3 Parameters
Ch2 Parameters
Ch1 Parameters
Ch0 Parameters
DRVSELA Parameter s

DAC+3LP Pattern Generator (1ch)3LP
ch(x) 3LP Data CHxWDATAn[7:0]Pattern
Memory8
Generator(128Byte)

PINx

CMOS
DRIVER N xIN

2ch(x) DAC CHxDATAn[11:0]
Memory12(12bit x 4096)

DACOUTPx

CHxDACn[11:0]

DAC

12

DACOUTNx10

DRVSELB
PIN7
NIN7
PIN6
NIN6
PIN5
NIN5
PIN4
NIN4
DACOUTP7DACOUTN7DACOUTP6DACOUTN6DACOUTP5DACOUTN5DACOUTP4DACOUTN4

INVx, GAINx[9:0]120

DACOUTNx

PIN3
NIN3
PIN2
NIN2
PIN1
NIN1
PIN0
NIN0
DACOUTP3DACOUTN3DACOUTP2DACOUTN2DACOUTP1DACOUTN1DACOUTP0DACOUTN0CMOS DRIVER

DRVSELA

DAC+3LP Pattern Generator (1ch)

120
120
120

RegisterParameter24

SPI I/O

CLK

3LP
ch(x) 3LP Data CHxWDATAn[7:0]Pattern
Memory8
Generator(128Byte)

PINx

2

CMOS
DRIVER N x
INch(x) DAC full scale current control

EN
CLK

TRIG

TRIG
Register

EXT_SIGACMOS DRIVER

24

Control Register(132Byte)

EN

LVDS/CMOS
Logic I/F

CLKP

VCOMREF

SPI I/O

SDOUT
EN

AVSS(0~-2V)

AGND

ch(x) DAC full scale current control
DRVSELB Parameters
Ch7 Parameters
Ch6 Parameters
Ch5 Parameters
Ch4 Parameters

SPI Logic I/F and controller

SPI_IFAVDD(+3.3V)

DRVSELB

Current Ref.
BGR

DGND

CMOS
Logic I/F

TRIG
CLK
EN

DRVSELDRVSEL
Generator
Generator

DRVSELySEL

DRVSELAch(x) DAC CHxDATAn[11:0]
Memory12(12bit x 4096)

CHxDACn[11:0]
12
10

DACOUTPx

DAC

INVx, GAINx[9:0]3

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ Block Diagram

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2■ Absolute Maximum Ratings

Ta=25°C unless otherwise noted.

No.
1
2
3
4
5
6
7
8
9

Items
Logic I/F voltage
Logic supply voltage
Positive supply voltage for DAC
Negative supply voltage for DAC
Positive to Negative voltage rail
LVDS Positive supply voltage
DAC outputs (x=0~7)
RBGR output voltage
VCOMREF input voltage

10 Logic output voltage (x=0~7)
11 Logic input voltages
12 Operating junction temperature
13 Storage temperature
14 Maximum power dissipation

Symbol
VLLIO
VLL
AVDD
AVSS
AVDD - AVSSDVDDIDACPx, IDACNx
RBGR
VCOMREF
PINx, NINx, DRVSELA,DRVSELB, SDOUT, FAULT
CLKP, CLKN, TRIG, SPI_OFF,
EN, EXT_SIGA, EXT_SIGB,
CSP, CSN, SCLKP, SCLKN,
SDATAP, SDATAN
TJop
TSTG
PDmax

Value
-0.4 to +4-0.4 to +2.3
-0.4 to +7-7 to +0.4
-0.4 to +7-0.4 to +7-0.4 to +7-0.4 to +7
AVSS to AVDD

Units
V
V
V
V
V
V
V
V
V

-0.4 to +7

V-0.4 to +7

V-20 to +125
-55 to +150
4oC

NOTE: Stresses beyond the absolute maximum ratings may cause permanent damage to the product.

4

oC

W

Condition

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2■ Operating Supply Voltage and Temperature
No

Items

Symbol

Min

Typ

Max

Units

Condition

1

Logic I/F voltage

VLLIO

1.71

1.8 to 3.3

3.6

V

2

Logic supply voltage ※1

VLL

1.71

1.8

1.89

V

3

LVDS Positive supply voltage

DVDD

3.0

3.3

3.6

V

4

DAC Positive supply voltage

AVDD

3.0

3.3

3.6

V

5

DAC Negative supply voltage

AVSS

-2

0

V

6

GND for LOGIC

DGND

-

0

-

V

7

GND for DAC

AGND

-

0

-

V

8

IC substrate voltage *

VSUB

-

0

-

V

AVSS +1.1

AVDD -2

V

Register parameter
OUTIFSEL[1:0]=10

AVSS +1.2

AVDD -2

V

Register parameter
OUTIFSEL[1:0]=11

0

75

oC

9

DAC common voltage reference
VCOMREF(Voltage output mode only)

10 Operating free-air TemperatureTa

NOTE: * The package exposed pad internally connected to the chip substrate must be soldered to the ground.
※1. Be sure to power on VLL last5

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2■ LVDS Differential Logic Inputs
CLKP/CLKN, CSP/CSN, SCLKP/SCLKN, SDATAP/SDATAN
No
1
2
3
4
5
6
7
8
9

Items
High-level input voltage
Low-level input voltage
Differential input voltage range
Differential input voltage
peak to peak swing
Input common mode voltage
High-level input current
Low-level input current
Input rise/fall time
Input clock frequency (Tx)
Input clock frequency (SPI)

10
11
12
13
14

Clock duty cycle
SDATA setup time
SDATA hold time
CS setup time
CS hold time15

CS width

Symbol
VIH
VIL
VDIFF(range)

Min
1.265
0.13

Typ
0.35

Max
1.135
0.49

VDIFF(p-p)

0.26

0.7

0.98

VIHCMR
IIH
IIL
tr , tf
fCLK

0.84
45
2.5
2.5
2.5
2.5
1042TSCLK
49170TSCLK
1074TSCLK
114TSCLK
138TSCLK
1042TSCLK
49170TSCLK
1074TSCLK
34TSCLK
66TSCLK

1.2
50

1.56
5.8
5.8
600
200
100
50
55

fSCLK
DCLK, DSCLKtSU_SDATAtHLD_SDATA
tSU_CStHLD_CS

tW_CS

Units
ConditionV
VIHCMR(Typ)+VDIFF(Min)/2
V
VIHCMR(Typ)-VDIFF(Min)/2±V Same as voltage swing
Differential peak-to-peak absoluteVppvoltage swing
V
mA
mA
ps 20% to 80% of VDIFF
MHz CLKP/CLKN TCLK=1/fCLK
MHz SCLKP/SCLKN (Write mode), TSCLK=1/fSCLKMHz SCLKP/SCLKN (Read mode)%ns SDATA to SCLK risens SDATA to SCLK risens CS to SCLK risens CS to SCLK risens Write to 3LP Memory (128byte)
ns Write to DAC Memory (6144Byte)
ns Write to All Control Register (132Byte)
ns Write to common Register (12Byte)
ns Write to ch(x) Register (15Byte), x=0~7
ns Read from 3LP Memory (128byte)
ns Read from DAC Memory (6144Byte)
ns Read from All control Register (132Byte)
ns Read CRC & Calculated CRC data (2Byte)
ns Read from Error Register (6Byte)

NOTE: External termination resister (100Ω) is necessary for LVDS I/F differential inputs.

6

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2■ CMOS Logic Inputs & Outputs
EN, TRIG, SPI_OFF, EXT_SIGA, EXT_SIGB, SDOUT, DRVSELA, DRVSELB, PINx/NINx (x=0~7),
CSP/CSN *2, SCLKP/SCLKN *2, SDATAP/SDATAN *2
No

Items

Symbol

Min

Typ

Max

Units

VIH

0.8VLLIO

-

VLLIO

V

Low-level logic input voltage

VIL

0

-

0.2VLLIO

V

Logic input capacitance

CIN

-

3

-

pF

4

Logic input high current

IIH

-10

-

10

μA

5

Logic input low current *1

IIL

-10

-

10

μA

6

Input rise/fall time

tr , tf

-

-

2.0

ns

7

TRIG fall to clock rise setup time

tSU_TRFtoCKR

1.4

-

-

ns

8

TRIG fall to clock rise hold time

tHLD_TRFtoCKR

1.4

-

-

ns

1

High-level logic input voltage

2
3

Condition

10~90% of signal

9

TRIG widthtW_TRIG

6TCLK

-

-

ns

10

High-level logic output voltage

VOH

0.8VLLIO

-

VLLIO

V

11

Low-level logic output voltage

VOL

0

-

0.2VLLIOV

SDOUT, PINx/NINx(x=0~7),
DRVSELA, DRVSELB

12

Logic output off leak current

IOFFLEAK

-10

-

10

μA

SDOUT HiZ output

10

13

17

ns

VLLIO=3.3V

12

15

19

ns

VLLIO=2.5V

14

18

23

ns

VLLIO=1.8V

13

SDOUT propagation delaytD_SDOUT

Remark:*1) EN has 50μA leakage at VLLIO=2.5V due to 50kΩ internal pull-up resistor.
*2) Single-ended CMOS interface is also available for SPI pins of CSP/N, SCLKP/N and SDATAP/N by setting SPI-IF to “Hi”.
When SPI-IF is set to “Hi”, SPI CMOS inputs must be connected to P-terminals of SPI pins (CSP, SCLKP and SDATAP)
and N-terminals of SPI pins (CSN, SCLKN and SDATAN) are need to be open.
(As for the N-terminals of SPI pins (CSN, SCLKN and SDATAN), half of VLLIO (VLLIO /2) is biased internally .)7

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2■ Open Drain Outputs
FAULT, TXONFLAG
No

Items

Symbol

Min

Typ

Max

Units

Condition

1

Pull-up voltage

VPUFAULT

-

-

VLLIO

V

Connected to VLLIO with external pullup resistor (R1, shown in page 9)2

Output low voltage

VOLFAULT

-

-

0.5

V

3

Output current

IFAULT

-

1.0

-

mA

Open drain MOS is Active.
VLLIO=2.5V
External pull-up resistor (R1) =2.5kΩ

4Off leakage current

IOFFLEAK

-10

-

10

μA

Open drain MOS is disabled. (HiZ)8

+1.8~3.3V

+1.8V

C1

C3

C2
R23

TXONFLAG
EXT_SIGB
R1

FAULT

VLLIO

+3.3V
C5

C6

C4
VLL

C1~C7=0.1uF(≧10V)
C8~C23=0.1uF(≧6V)
R1,R23=2.5kΩ
R2=24kΩ (1%)
R3~R6=100Ω (for LVDS termination)
R7~R22=62Ω

C7
DVDD

DGND

AVDD

AGND

AVSS

VCOMREF2
2
2
2

R2 RBGRSPI_OFFSPI_IF
R3

CSP
CSN

FPGA

SCLKP
R4

SDATAN
SDOUT
EN
CLKP

R6

PIN7,NIN7
PIN6,NIN6
PIN5,NIN5
PIN4,NIN4DACOUTP7DACOUTN7DRVSEL
PIN7,NIN7
PIN6,NIN6
PIN5,NIN5
PIN4,NIN4R7DACOUTP6DACOUTN6DACOUTP5DACOUTN5R11DACOUTP4DACOUTN4

R13

R8
R9
R10

R12

C8
C9
C10
C11
C12
C13
C14
C15

R14

SCLKN
SDATAP

R5

S-UM55L2DRVSELB

S-US55D2(ES2)
S-US55D2

CLKN
TRIG

2
2
2
2

PIN3,NIN3
PIN2,NIN2
PIN1,NIN1
PIN0,NIN0DACOUTP3DACOUTN3

INN5
INP4
INN4

S-UM55L2

R15

C16
C17

INP3

R16

INN3
INP2

R18

INN2
INP1

DACOUTP2DACOUTN2DACOUTP1DACOUTN1

C20
R19 C21DACOUTP0DACOUTN0R21

DRVSELA

INN6
INP5

PIN3,NIN3
PIN2,NIN2
PIN1,NIN1
PIN0,NIN0C18
R17 C19

R20

R22

EXT_SIGA

INP7
INN7
INP6

C22
C23

INN1
INP0
INN0

DRVSEL

9

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ Typical Application Circuit (current output)

+1.8~3.3V

+1.8V

C1

C3

C2
R23

TXONFLAG
EXT_SIGB
R1

FAULT

VLLIO

-2V

+3.3V
C5

C8

C6

C4
VLL

C1~C8=0.1uF(≧10V)
C9~C24=0.1uF(≧6V)
R1,R23=2.5kΩ
R2=24kΩ (1%)
R3~R6=100Ω (for LVDS termination)

C7
DVDD

DGND

AVDD

AGND

AVSS

VCOMREF2
2
2
2

R2 RBGRCSPCSNDACOUTP4DACOUTN4

FPGA

SCLKP
R4

SDATAN
SDOUT
EN
CLKP

R6

DRVSEL
PIN7,NIN7
PIN6,NIN6
PIN5,NIN5
PIN4,NIN4
C9
C10
C11

CLKN
TRIG

EXT_SIGA22
2
2

PIN3,NIN3
PIN2,NIN2
PIN1,NIN1
PIN0,NIN0DACOUTP3DACOUTN3DACOUTP2DACOUTN2DACOUTP1DACOUTN1DACOUTP0DACOUTN0DRVSELA

INP7
INN7
INP6

C12
C13

INN6
INP5

C14
C15
C16

INN5
INP4

SCLKN
SDATAP

R5

PIN7,NIN7
PIN6,NIN6
PIN5,NIN5
PIN4,NIN4DACOUTP7DACOUTN7DACOUTP6DACOUTN6DACOUTP5DACOUTN5SPI_OFFSPI_IF
R3

S-UM55L2DRVSELB

S-US55D2(ES2)
S-US55D2

INN4

S-UM55L2

C17
C18
C19
C20
C21
C22
C23
C24

PIN3,NIN3
PIN2,NIN2
PIN1,NIN1
PIN0,NIN0
INP3
INN3
INP2
INN2
INP1
INN1
INP0
INN0

DRVSELOCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

10■ Typical Application Circuit (voltage output)

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2■ Operating Supply Currents (1)VLLIO=2.5V, VLL=1.8V, DVDD=AVDD=3.3V, AVSS=-2V, TA=25°
C, CLKP/CLKN=200MHz,
PINx/NINx(x=0~7) load = 10pF, unless otherwise specified.

No

Symbol

Min

Typ

Max

Units

1

VLLIO current

Items

ILLIOQD

-

0.06

-

mA

2

VLL current

ILLQD

-

0.11

-

mA

-

0.7

-

mA

Quiescent current-1

-

1.3

-

mA

Quiescent current at chip is disabled.
EN=“1”(Disable)
CLKP/CLKN is stopped.

SPI_OFF=“1”,SPI_IF=“0/1”3DVDD current

4

AVDD current

SPI_OFF=“0”,SPI_IF=“1”IDDDQD

-

6.3

-

mA

IADDQD

-

2.8

-

mA

SPI_OFF=“0”,SPI_IF=“0”5AVSS current

IASSQD

-

0.65

-

mA

6

VLLIO current

ILLIOQE1

-

0.1

-

mA

7

VLL current

ILLQE1

-

22.3

-

mA

-

3.2

-

mA

-

3.8

-

mA

-

mA

SPI_OFF=“1”,SPI_IF=“0/1”8DVDD current

SPI_OFF=“0”,SPI_IF=“1”IDDDQE1

8.6-

AVDD current

IADDQE1

-

2.9

-

mA

10 AVSS current

IASSQE1

-

0.65

-

mA

11 VLLIO current

ILLIOQE2

-

0.1

-

mA

12 VLL current

ILLQE2

-

22.3

-

mA

-

3.2

-

mA

-

3.8

-

mA

-

8.6

-

mA

-

88

-

mA

-

14

-

mA

-

0.65

-

mA

SPI_OFF=“0”,SPI_IF=“0”9SPI_OFF=“1”,SPI_IF=“0/1”

13 DVDD current

SPI_OFF=“0”,SPI_IF=“1”IDDDQE2SPI_OFF=“0”,SPI_IF=“0”14 AVDD current
15 AVSS current

ICSELx[2:0] =“111”ICSELx[2:0] =“000”IADDQE2IASSQE2

Condition

Quiescent current-2
Quiescent current at chip is enable andall DAC is bias-off,
Both DAC and 3LP-PG are not operated.
EN=“0”(Enable)
CLKP/CLKN is activated (200MHz)DACTXCHx=“0” (x=0~7)
TLPTXCHx=“0” (x=0~7)
PWRSAVE=“1”Quiescent current-3
Quiescent current at chip is enable andall DAC is bias-on,
Both DAC and 3LP-PG are not operated.
EN=“0”(Enable)
CLKP/CLKN is activated (200MHz)DACTXCHx=“0” (x=0~7)
TLPTXCHx=“0” (x=0~7)
PWRSAVE=“0”11

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2■ Operating Supply Currents (2)VLLIO=2.5V, VLL=1.8V, DVDD=AVDD=3.3V, AVSS=-2V, TA=25°
C, CLKP/CLKN=200MHz, unless otherwise specified.

No

Items

16

VLLIO current

17

VLL current

Symbol

Min

Typ

Max

Units

ILLIODAC1ILLDAC1

-

0.1

-

mA

-

229

-

mA

-

3.2

-

mA

-

3.8

-

mA

SPI_OFF=“0”,SPI_IF=“0”

-

8.6

-

mA

ICSELx[2:0] =“111”

-

229

-

mA

-

156

-

mA

-

0.65

-

mA

-

0.1

-

mA

-

229

-

mA

-

3.2

-

mA

-

3.8

-

mA

SPI_OFF=“0”,SPI_IF=“0”

-

8.6

-

mA

ICSELx[2:0] =“111”

-

206

-

mA

-

183

-

mA

-

62

-

mA

-

40

-

mA

-

0.1

-

mA

-

229

-

mA

-

3.2

-

mA

-

3.8

-

mA

SPI_OFF=“0”,SPI_IF=“0”

-

8.6

-

mA

ICSELx[2:0] =“111”

-

310

-

mA

-

287

-

mA

-

163

-

mA

-

140

-

mA

SPI_OFF=“1”,SPI_IF=“0/1”

18 DVDD current

19 AVDD current

SPI_OFF=“0”,SPI_IF=“1”ICSELx[2:0] =“000”

IADDDAC1
IASSDAC1ILLIODAC2ILLDAC2

20 AVSS current
21 VLLIO current
22

IDDDDAC1

VLL current
SPI_OFF=“1”,SPI_IF=“0/1”

23 DVDD current

24 AVDD current
25 AVSS current
26

VLLIO current

27

VLL current

SPI_OFF=“0”,SPI_IF=“1”ICSELx[2:0] =“000”ICSELx[2:0] =“111”ICSELx[2:0] =“000”IDDDDAC2
IADDDAC2
IASSDAC2ILLIODAC3ILLDAC3SPI_OFF=“1”,SPI_IF=“0/1”

28 DVDD current

29 AVDD current
30 AVSS current

12

SPI_OFF=“0”,SPI_IF=“1”ICSELx[2:0] =“000”ICSELx[2:0] =“111”ICSELx[2:0] =“000”IDDDDAC3
IADDDAC3
IASSDAC3

Condition
DAC operating current -1
Operating current with current DAC.
EN=“0”(Enable)
DRVSELA/B =“1” (DAC is selected)
DAC output load = 50Ω//2pF
All channel active
CW 5MHz sin wave outputs
OUTIFSEL[1:0]=“00” (Current output mode)
DACTXCHx=“1” (x=0~7)

DAC operating current -2
Operating current with voltage DAC (Ro=14Ω）.
EN=“0”(Enable)
DRVSELA/B =“1” (DAC is selected)
DAC output load = 500Ω//2pF
All channel active
CW 5MHz sin wave outputs
OUTIFSEL[1:0]=“10” (Voltage mode Ro=14Ω)
DACTXCHx=“1” (x=0~7)

DAC operating current -3
Operating current with voltage DAC (Ro=2Ω).
EN=“0”(Enable)
DRVSELA/B =“1” (DAC is selected)
DAC output load= 500Ω//2pF
All channel active
CW 5MHz sin wave outputs
OUTIFSEL[1:0]=“11” (Voltage mode Ro=2Ω)
DACTXCHx=“1” (x=0~7)

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2■ Operating Supply Currents (3)C, CLKP/CLKN=200MHz, PINx/NINx(x=0~7) load = 10pF, unless otherwise specified.
VLLIO=2.5V, VLL=1.8V, DVDD=AVDD=3.3V, AVSS=-2V, TA=25°

No

Items

Symbol

Min

Typ

Max

Units

Condition

ILLIO3LP1
ILL3LP1

-

4.0

-

mA

3LP Pattern Generator operating current-1

-

24

-

mA

-

3.2

-

mA

Operating current with 3LP Pattern Generator at
DAC is bias-off,

IDDD3LP1

-

3.8

-

mA

1

VLLIO current

2

VLL current

3

DVDD current

-

8.6

-

mA

4

AVDD current

IADD3LP1

-

3.0

-

mA

5

AVSS current

IASS3LP1

-

0.65

-

mA

EN=“0”(Enable)
DRVSELA/B =“0” (3LP DATA is selected)
All channel active, CW 5MHz BIP wave outputs
DACTXCHx=“0” (x=0~7)
TLPTXCHx=“1” (x=0~7)
PWRSAVE=“1”6

VLLIO current

-

4.0

-

mA

3LP Pattern Generator operating current-2

7

VLL current

ILLIO3LP2
ILL3LP2

-

24

-

mA

-

3.2

-

mA

Operating current with 3LP Pattern Generator atcurrent DAC is bias-on,

-

3.8

-

mA

SPI_OFF=“0”,SPI_IF=“0”

-

8.6

-

mA

ICSELx[2:0] =“111”

-

88

-

mA

-

14

-

mA

-

0.65

-

mA

-

4.0

-

mA

-

24

-

mA

-

3.2

-

mA

-

3.8

-

mA

-

8.6

-

mA

-

64

-

mA

-

41

-

mA

-

62

-

mA

-

40

-

mA

SPI_OFF=“1”,SPI_IF=“0/1”
SPI_OFF=“0”,SPI_IF=“1”SPI_OFF=“0”,SPI_IF=“0”SPI_OFF=“1”,SPI_IF=“0/1”89DVDD current

AVDD current

SPI_OFF=“0”,SPI_IF=“1”ICSELx[2:0] =“000”IDDD3LP2
IADD3LP2
IASS3LP2ILLIO3LP3
ILL3LP3

10 AVSS current
11 VLLIO current
12 VLL current
SPI_OFF=“1”,SPI_IF=“0/1”

13 DVDD current

SPI_OFF=“0”,SPI_IF=“1”IDDD3LP3SPI_OFF=“0”,SPI_IF=“0”14 AVDD current
15 AVSS current

ICSELx[2:0] =“111”ICSELx[2:0] =“000”ICSELx[2:0] =“111”ICSELx[2:0] =“000”

IADD3LP3
IASS3LP3

EN=“0”(Enable)
DRVSELA/B =“0” (3LP DATA is selected)
All channel active, CW 5MHz BIP wave outputs
OUTIFSEL[1:0]=“00” (Current output mode)
DACTXCHx=“0/1” (x=0~7)
TLPTXCHx=“1” (x=0~7)
PWRSAVE=“0”3LP Pattern Generator operating current-3

Operating current with 3LP Pattern Generator atvoltage DAC is bias-on,
EN=“0”(Enable)
DRVSELA/B =“0” (3LP DATA is selected)
All channel active, CW 5MHz BIP wave outputs
OUTIFSEL[1:0]=“10” (Voltage output mode Ro=14Ω)
DACTXCHx=“0/1” (x=0~7)
TLPTXCHx=“1” (x=0~7)
PWRSAVE=“0”13

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2■ Static Characteristics
C, CLKP/CLKN=200MHz, unless otherwise specified.
VLLIO=2.5V, VLL=2.5V, DVDD=AVDD=3.3V, TA=25°

No

Items

Symbol

Min

Typ

Max

Note

DAC Resolution

2

DAC Differential Nonlinearity

DNLx

-2

+/-1

2

LSB Differential Non-linearity of DAC differential outputs

3

DAC Integral Nonlinearity

INLx

-3.5

+/-1

3.5

LSB Integral Non-linearity of DAC differential outputs

4

DAC Full-scale output current(Current output mode)

IFSx

1.28

10.24

mA

5

DAC Full-scale output voltage(Voltage output mode )

VFSx

0.077

0.592

0.083

0.664

6

DAC digital gain

GDx

-1

1

7

DAC differential current offset error(Current output mode)

IOFSx

-0.8

+0.8

LSB Without adjustment+5

LSB Without adjustment, ICSEL[2:0]=“111” (VFSx is max)

89

DAC differential voltage offset error(Voltage output mode)
DAC Gain error

10 DAC ch to ch Gain matching

12

Unit

1

VOFSx
GERRORx
ΔGCH-CHRo

12 DAC output common voltage error

VOFS_COM

13 Internal BGR reference voltage

14+/-0.375-5+/-1+/-0.1-0.6%%

No load, Register OUTIFSEL[1:0]=“11” (Ro=2Ω)programable with register GAINx[9:0] and INVx,
except for 0, step=1/1024

Without adjustment
Adjusted with Register GAINADJx[6:0]Without adjustment
DAC is disabled

18

Ω

3.5
VBGR

No load, Register OUTIFSEL[1:0]=“10” (Ro=14Ω)

LSB Adjusted with Register OFSADJx[6:0], ICSEL[2:0]=“111”+4+/-0.06+0.6

V/V

Register OUTIFSEL[1:0]=“00”LSB Adjusted with Register OFSADJx[6:0]+/-0.375
-4

V

100M

DAC output impedance(Voltage output mode only)

11

bits

-10

DAC is active, OUTIFSEL[1:0]=“11”
10

1.207

DAC is active, OUTIFSEL[1:0]=“10”mVV

Voltage output only (OUTIFSEL[1:0]=“10” or ”11”)

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2■ Dynamic Characteristics

C, CLKP/CLKN=200MHz, ICSELx[2:0]=111, VCOMREF=0V, unless otherwise specified.
VLLIO=2.5V, VLL=1.8V, DVDD=AVDD=3.3V, VSS=-2V, TA=25°

No.

Items

Symbol

Min

Typ

1

DAC Spurious Free Dynamic Range

SFDR

49

55

2

DAC output noise(load noise is included, @5MHz )

3

4

5

6
7

DAC differential output voltage

DAC output propagation delay(From programmed delay clock rise)

DAC output rise/fall time
(full-scale swing, 10%-90%)

No

DRVOUTtPD_DACtRF_DAC

3LP Data output propagation delaytPD_3LP

3LP Data output rise/fall time
DRVSEL output propagation delay

10 DRVSEL output rise/fall time

dBc

Note
fCLK= 200MHz, ICSELx[2:0]=111, Current output, 5MHz

2

Current output (OUTIFSEL[1:0]=“00”), load=50Ω//2pF

4.5

nv/rtHz Voltage output (OUTIFSEL[1:0]=“10”), load=500Ω//2pF

6

Voltage output (OUTIFSEL[1:0]=“11”), load=500Ω//2pF

1.03

Current output (OUTIFSEL[1:0]=“00”) load=50Ω//2pF

1.15

Vpp

Voltage output (OUTIFSEL[1:0]=“10”) load=500Ω//2pF

1.33

Voltage output (OUTIFSEL[1:0]=“11”) load=500Ω//2pF

14

Current output (OUTIFSEL[1:0]=“00”) load=50Ω//2pF

16

ns

Voltage output (OUTIFSEL[1:0]=“10”) load=500Ω//2pF

17.5

Voltage output (OUTIFSEL[1:0]=“11”) load=500Ω//2pF

3

Current output (OUTIFSEL[1:0]=“00”) load=50Ω//2pF

8ns

Current output (OUTIFSEL[1:0]=“00”) load=50Ω//2pF

22

ns

26
tRF_3LP1
12

tRF_DRVSEL

1Voltage output (OUTIFSEL[1:0]=“10”) load=500Ω//2pF
Voltage output (OUTIFSEL[1:0]=“11”) load=500Ω//2pF

11

tPD_DRVSEL

Voltage output (OUTIFSEL[1:0]=“10”) load=500Ω//2pF
Voltage output (OUTIFSEL[1:0]=“11”) load=500Ω//2pF

9tSET_DAC

8

Unit

5.5

DAC output current settling time
(full-scale step, settling to <+/-0.1% )

9

Max

2
2

ns

From programmed delay clock rise edge

nsload = 10pF

ns

From programmed wait clock rise edge

nsload = 10pF

15

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2■ Tx Pattern Width and Delay Digital Control Table

Clock frequency = 200MHz (TCLK=5ns)
No

Items

Symbol

Min
0.16

1

DRVSELy(y=A,B) wait time from
TRIG fall edge

TWAIT_DRVSELy

2

DRVSELy(y=A,B) wait time step

ΔTWAIT_DRVSEL

3DRVSELy(y=A,B) “high” period

TWIDTH_DRVSELy

Typ

Max

Unit

40.955µs

TWAIT_DRVSELy = TCLK*(32*WAITy + 31)
WAITy(=0~255) is decimal number of WAITy[7:0]µsΔTWAIT_DRVSEL = 32*TCLK

ms

If WIDTHy[15:0]= all high, Hi state is kept until next Trig riseedge or it is reset by “EN”.
Else, TWIDTH_DRVSELy(=0~10.48544ms) = 32*TCLK*WIDTHy
WIDTHy(=0~65534) is decimal number of WIDTHy[15:0]

0.16

0

Note

4

DRVSELy(y=A,B) “high” period step ΔTWIDTH_DRVSELµs

ΔTWIDTH_DRVSEL = 32*TCLK5DRVSELy(y=A,B) L to H settling

TPON_DRV

3.2

µs

6

DRVSELy(y=A,B) H to L settling

TPOFF_DRV

3.205

µs

During 640 clock cycle (3.2us) from DRVSEL rise/fall edge.
DAC/3LP output for Tx is not allowed.

7

DAC clock rate

fDAC-CLK

200

Mbps

8

Initial wait time for DAC/3LP data
output from TRIG fall edge

TINIT

9

CHx(x=0~7) delay range of DAC
output from TRIG fall edge

TDL_CHxDAC

10

CHx delay delta resolution of
DAC output (x=0~7)

ΔTDL_CHxDAC

11 Ch#x(x=0~7) Tx pulse width of 3LP

TCHxWIDTHn

12 Tx pulse width resolution of 3LP

ΔTCHxWIDTHn

0.16

0.16

µs

ΔTINIT = 32*TCLKTDL_CHxDAC=(32+DAC_DLx)*TCLK

13

CHx(x=0~7) delay range of 3LPTx output from TRIG fall edge

TDL_CHx3LP

14

CHx(x=0~7) delay delta resolution
of TLP output

ΔTDL_CHx3LP

0.16

41.115
5

10

325
5

0.16

41.1155µs

DAC_DLx(=0~8191※1) is a decimal number of DAC_DLx[12:0]ns

ΔTDL_CHxDAC=TCLK

ns

TCHxWIDTHn [ns] = TCLK * (CHxWIDTHn + 2)
CHxWIDTHn(=0~63) is decimal number of
CHxWIDTHn[5:0] in memory #n, n=0~127

ns

ΔTCHxWIDTHn =TCLKµs

TDL_CHx3LP=(32+TLP_DLx)*TCLKTLP_DLx(=0~8191) is a decimal number of TLP_DLx [12:0]

ns

ΔTDL_CHx3LP=TCLK※1 . In case of USE_EXTSIG=0 , DAC_DLx=0~639(decimal number) cannot be used due to restrictions with DRVSEL.

16

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2■ SPI Header Configuration

D7(MSB)
01

1

SDATA Control Header (First 1Byte of SDATA)
D5
D4
D3
D2
D1
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
1
1
1
1
0
1
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
0
0
1
0
1
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
1
*
*
*
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
1
1
1
1
0
1
0
*
*
0
0
1
0
0
0
1
0
1
0
1
1
1
0
1
0
1
1
1
1
1
0
0
*
*
1
0
1
*
*
1
1
0
*
*
1
1
1
*
*

D6
*

SPI operation
D0(LSB)*
Hold
0
Write to all-channel 3LP Memory at the same time (128Byte)0
Write to CH0 3LP Memory (128Byte)
1
Write to CH1 3LP Memory (128Byte)0
Write to CH2 3LP Memory (128Byte)
1
Write to CH3 3LP Memory (128Byte)0
Write to CH4 3LP Memory (128Byte)
1
Write to CH5 3LP Memory (128Byte)0
Write to CH6 3LP Memory (128Byte)
1
Write to CH7 3LP Memory (128Byte)0
Write to all-channel DAC Memory at the same time (6144Byte)0
Write to CH0 DAC Memory (6144Byte)
1
Write to CH1 DAC Memory (6144Byte)0
Write to CH2 DAC Memory (6144Byte)
1
Write to CH3 DAC Memory (6144Byte)0
Write to CH4 DAC Memory (6144Byte)
1
Write to CH5 DAC Memory (6144Byte)0
Write to CH6 DAC Memory (6144Byte)
1
Write to CH7 DAC Memory (6144Byte)0
Write to Register 132Byte(#0~#131)
0
Write to Register 12Byte(#0~#11)0
Write to Register 15Byte(#12~#26)
1
Write to Register 15Byte(#27~#41)
0
Write to Register 15Byte(#42~#56)
1
Write to Register 15Byte(#57~#71)
0
Write to Register 15Byte(#72~#86)
1
Write to Register 15Byte(#87~#101)
0
Write to Register 15Byte(#102~#116)
1
Write to Register 15Byte(#117~#131)*
Don’t use
0
Don’t use0
Read from CH0 3LP Memory (128Byte)
1
Read from CH1 3LP Memory (128Byte)0
Read from CH2 3LP Memory (128Byte)
1
Read from CH3 3LP Memory (128Byte)0
Read from CH4 3LP Memory (128Byte)
1
Read from CH5 3LP Memory (128Byte)0
Read from CH6 3LP Memory (128Byte)
1
Read from CH7 3LP Memory (128Byte)*
Don’t use0
Read from CH0 DAC Memory (6144Byte)
1
Read from CH1 DAC Memory (6144Byte)0
Read from CH2 DAC Memory (6144Byte)
1
Read from CH3 DAC Memory (6144Byte)0
Read from CH4 DAC Memory (6144Byte)
1
Read from CH5 DAC Memory (6144Byte)0
Read from CH6 DAC Memory (6144Byte)
1
Read from CH7 DAC Memory (6144Byte)*
Read from Register 132Byte(#0~#131)*
Don’t use*
Read from CRC[7:0] & CAL_CRC[7:0] (2Byte)*
Read from ERROR[47:0] (6byte)

Note: Control Headers which don’t listed in the above table are prohibited.

17 Write to ch#x DAC Memory
CS
Transfer data to ch#x DAC Memory 12bit x 4096 (=6144Bytes)

Header (1Byte)(operation command)

CHx Memory#0

D0 D11D7CRC (1Byte)

CHx Memory #4095
D0 D11SDATA

D0 D11+2cycleCRC[7:0]
D0 D7

D0

SCLK
(HiZ)

SDOUT

Note:
In “WRITE” operation with SPI, internal logic circuit also calculates the CRC ,and writes it to internal Register CAL_CRC[7:0].
If CAL_CRC[7:0] unmatched transferred CRC data (CRC[7:0]), corresponding ERROR bit is set to “1” and FAULT is reported
until ERROR bit is cleared.
 Read from ch#x DAC Memory
CS
Readout data from ch#x DAC Memory 12bit x 4096 (=6144Bytes)

Wait (8.5cycle)

Header (1Byte)+1.5cycle(operation command)
D7

D0

SDATA
SCLK
CHx Memory#0

SDOUT

(HiZ)

D11

D0 D11

D0 D11

CHx Memory #4095

Note:
In case of “READ” operation, SDATA inputs except for Header are ignored. (CRC error detection is disabled)

D0

(HiZ)

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

18■ Access to DAC Memory with SPI Write to ch#x 3LP Data Memory
CS
Transfer data to ch#x 3LP Data Memory 128Bytes

Header (1Byte)(operation command) CHx Memory#0
D0 D7

D7

CRC (1Byte)

CHx Memory#126 CHx Memory#127
D0 D7
D0 D7

CHx Memory#1
D0 D7

SDATA

+2cycleCRC[7:0]
D0

SCLK
(HiZ)

SDOUT

Note:
In “WRITE” operation with SPI, internal logic circuit also calculates the CRC ,and writes it to internal Register CAL_CRC[7:0].
If CAL_CRC[7:0] unmatched transferred CRC data (CRC[7:0]), corresponding ERROR bit is set to “1” and FAULT is reported
until ERROR bit is cleared.
 Read from ch#x 3LP Data Memory
CS
Readout data from ch#x 3LP Data Memory 128Bytes

Wait (8.5cycle)

Header (1Byte)+1.5cycle(operation command)
D7

D0

SDATA
SCLK
SDOUT

CHx Memory#0

(HiZ)

D7

CHx Memory#1
D0 D7

CHx Memory#126
CHx Memory#127
D0 D7
D0

Note:
In case of “READ” operation, SDATA inputs except for Header are ignored. (CRC error detection is disabled)

(HiZ)

19

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ Access to 3LP Data Memory with SPI Write to Control Register
CS
Transfer data to Control Register (132Byte/12Byte/15Byte)

Header (1Byte)(operation command)

R#0(R#0/R#12/R#27/
R#42/R#57/R#72/
R#87/R#102/R#117)
D0 D7
D0 D7

D7

CRC (1Byte)
R#131(R#11/R#26/R#41/
R#56/R#71/R#86/
R#101/R#116/R#131)

D0 D7

SDATA

+2cycleCRC[7:0]

D0 D7

D0

SCLK
(HiZ)

SDOUT

Note:
In “WRITE” operation with SPI, internal logic circuit also calculates the CRC ,and writes it to internal Register CAL_CRC[7:0].
If CAL_CRC[7:0] unmatched transferred CRC data (CRC[7:0]), corresponding ERROR bit is set to “1” and FAULT is reported
until ERROR bit is cleared.
 Read from control RegisterCS
Readout data from Control Register (132Bytes)

Wait (8.5cycle)

Header (1Byte)+1.5cycle(operation command)
D7

D0

SDATA
SCLK
R#0

SDOUT

(HiZ)

D7

D0 D7

D0 D7

Note:
In case of “READ” operation, SDATA inputs except for Header are ignored. (CRC error detection is disabled)

R#131

D0

(HiZ)

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

20■ Access to Control Register with SPI Read from CRC RegisterCS
Readout datafrom CRC Register (2Bytes)

Wait (8.5cycle)

Header (1Byte)(operation command)
D7+1.5cycle

D0

SDATA
SCLK
CRC[7:0] (*1)
D7

(HiZ)

SDOUT

CAL_CRC[7:0] (*1)
D0
D0 D7

(HiZ)

Note:
*1: CRC[7:0] and CALCRC[7:0] is the received CRC data and its calculated CRC data in previous “WRITE” operation.
 Read from control RegisterCS
Readout data from Error Register (6Bytes)

Wait (8.5cycle)

Header (1Byte)+1.5cycle(operation command)
D7

D0

SDATA
SCLK
ERROR[47:40]

SDOUT

(HiZ)

D7

ERROR[39:32]
D0 D7

ERROR[15:8]
D0 D7

ERROR[7:0]
D0

(HiZ)

21

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ Access to CRC & ERROR Register with SPIThe SDOUT propagation delay is defined as the time from the 17th rising edge of SCLK until the data comes out of SDOUT.
(Independent of SCLK rate.) Read from Register and Memory
CS
Header (1Byte)
D7(operation command)

Wait (8.5cycle)
D0

SDATA

SCLK
1st rising edge

9th rising edge

17th rising edge
R#0

SDOUT

(HiZ)

D7

SDOUT Propagation delay

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

22■ Definition of SDOUT Propagation Delay Operation mode

sectionEN

Access toAccess to
DRV Access to
Ch(x)
Ch(x)
DAC
Ch(x)
3LP
RegisterCS_
Tx- _SEL
DAC
TRIG
MemoryMemory(control)FLAG
pattern (y)Write Read Write Read Write Read Tx

A
B

0

0

0

C
D

0

0

1

E
F

0

1

0

G

Ch(x)
3LP Data
Tx

Operation mode

Rx

none

＊

×

×

×

×

×

×

×

×

Gen.

0

×

×

×

×

×

×

×

○（*1)

×

3LP Tx

Gen.

1

×

×

×

×

×

×

○（*1)

×

×

DAC Tx

none

＊

×

×

×

×

×

×

none

＊

○

○

○

○

○

○

Gen.

0

○

○

×（*2)

○

○

○

Gen.

1

○

○

○

○

Reset by TRIG
Access to Memory or Register×× ○（*1)during Rx
Access to Memory or Register× ○（*1) ×
during 3LP Tx
Access to Memory or Register○（*1) ××
during DAC Tx
××× Error[6] condition, N/A (*3)

×（*2) ×（*2)○（*1) Rx(TRSW control with 3LP data)

×

×

×

-

0

1

1

none

＊

○

○

○

○

○

○

H

1

0

＊

none

0

×

×

×

×

×

×

×

×

×

J

1

1

0

none

0

○

○

○

○

×（*4)

○

×

×

×

-

1

1

1

none

0

○

○

○

○

○

○

×

×

×

○ : available, ×: not available,

Chip disabled
Access to Memory or Registerduring chip disabled
Error[6] condition, N/A (*3)

CS _ FLAG = CS • SPI _ OFFSPI_OFF is the bias control of LVDS Receiver in SPI for power saving. (0:bias on, 1:bias-off)Suffix x (=0~7) corresponds to channel number, and Suffix y (=A/B) corresponds to the number of DRV_SEL.
DRV_SELA(or DRV_SELB) controls the ch0~3 (or ch4~7) operation.
*1： Register parameter DACTXCHx, TLPTXCHx or RXCHx is necessary to be set “1”.
*2： If CH(x) DAC Memory is accessed during CH(x) DAC Tx operation or CH(x) 3LP Memory is accessed during CH(x)3LP Tx operation, ERROR[4] or ERROR[5] is set to “1” and Tx operation is stopped.
*3： “1” state of TRIG signal during CS_FLAG=‘1’ is the error operation, so Tx operation is reset and its TRIG “1” is ignored.
*4： Register parameters are reset by fall edge of “EN”.
23

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ Operation Mode

<section> HJ

A E AD

A

F

C

F A

B

G E ADA

B

A

C

DA

B

A

C

Clear Register at EN fall edge

EN
Write#0
to DAC
MemoryWrite#0
to Register

Write#0
to 3LP
MemoryWrite#1
to DAC
MemoryWrite#1
to Register

CS_FLAG
TRIG
Load Register data at TRIG rise edge

Load Register data at TRIG rise edge

DRVSEL(y)(y=A for ch#0~3,
y=B for ch#4~7)

Preset width#0
Preset wait#0

Preset wait#1

IC disabled

DACTXCHx=1
TLPTXCHx=1
RXCHx=1
DACTXCHx=1
TLPTXCHx=1
RXCHx=0DACTXCHx=1
TLPTXCHx=0
RXCHx=1
DACTXCHx=1
TLPTXCHx=0
RXCHx=0ch(x) DAC
Tx pattern#1

with DAC MEM.
by write#0 &REG. by write #0

with 3LP MEM.
by write#0 &REG. by write#0

with 3LP MEM.
by Write#0 &REG. by write#1

with DAC MEM.
by write#1 &REG. by write#1

00
(GND)

11
(Rx)

00
(HiZ *1)

00

DAC Tx

00
(GND)

00
(GND)

00
(HiZ *1)

00

DAC TxPINx/NINx

00
(GND)

11
(Rx)

00
(HiZ *1)

DACOUTPx-DACOUTNx

00

DAC Tx

00
(GND)

00
(GND)

00
(HiZ *1)

DACOUTPx-DACOUTNx
PINx/NINxDACOUTPx-DACOUTNx

PINx/NINx

Preset DAC delay#1

ch(x) 3LP
Tx pattern#1

DAC TxPINx/NINx

Preset DAC delay#1

ch(x) 3LP
Tx pattern#0

0

0
11
(Rx)

10/01/00(3LP Tx)

11(Rx)

DAC Tx10/01/00(3LP Tx)

11
(Rx)

0
00
GND

10/01/00(3LP Tx)

00
(GND)

00
GND

0
11
(Rx)

11
(Rx)

11
(Rx)

00

00
(GND)

00
(GND)

2bit output code of PINx/NINx corresponds to 3LP input code of “S-UM55L2”.
*1: In 3LP Tx driver of “S-UM55L2”, “HiZ” operation is assigned to “00” inputs during DRVSEL =1.

11
(Rx)

00
(HiZ *1)

11
(Rx)

11
(Rx)

00
(HiZ *1)

00
GND

00
GND

00
(HiZ *1)

ch(x) DAC
Tx pattern#1

0

DAC Tx10/01/00(3LP Tx)

11(Rx)

10/01/00(3LP Tx)

11
(Rx)

11
(Rx)

00
GND

00

00
(GND)

00
(HiZ *1)

DAC Tx
11
(Rx)

0
GND

00
(HiZ *1)

DAC Tx0

DAC Tx00(GND)

ch(x) 3LP
Tx pattern#1

0

DAC Tx0
GND

00(HiZ *1)

DAC Tx10/01/00(3LP Tx)

Preset width#1

Preset 3LP delay#1

ch(x) DAC
Tx pattern#0

0

DACOUTPx-DACOUTNx

Preset wait#1

Preset width#1

Preset 3LP delay#1

Preset 3LP delay#0
Preset DAC delay#0

TX-PT(x)（x=0~7）

Load Register data at TRIG rise edge

00
(HiZ *1)

DAC Tx00
GND

00(HiZ *1)

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

24■ Operation Sequence Example

<section> HJ

A E AD

A

F

C

F A

B

G E ADA

B

A

C

DA

B

A

C

Clear Register at EN fall edge

EN
Write#0
to DAC
MemoryWrite#0
to Register

Write#0
to 3LP
MemoryWrite#1
to DAC
MemoryWrite#1
to Register

CS_FLAG
TRIG
Load Register data at TRIG rise edge

Load Register data at TRIG rise edge

DRVSEL(y)(y=A for ch#0~3,
y=B for ch#4~7)

Preset width#0
Preset wait#0

Preset wait#1

IC disabled

DACTXCHx=0
TLPTXCHx=1
RXCHx=1
DACTXCHx=0
TLPTXCHx=1
RXCHx=0DACTXCHx=0
TLPTXCHx=0
RXCHx=1
DACTXCHx=0
TLPTXCHx=0
RXCHx=0ch(x) DAC
Tx pattern#1

with DAC MEM.
by write#0 &REG. by write #0

with 3LP MEM.
by write#0 &REG. by write#0

with 3LP MEM.
by Write#0 &REG. by write#1

with DAC MEM.
by write#1 &REG. by write#1

00
(GND)

11
(Rx)

11
(Rx)

0

0

0

00
(GND)

00
(GND)

00
(GND)

0

0

0

PINx/NINx

00
(GND)

11
(Rx)

11
(Rx)

DACOUTPx-DACOUTNx000

DACOUTPx-DACOUTNx
PINx/NINxDACOUTPx-DACOUTNx

PINx/NINx

00
(GND)

00
(GND)

Preset DAC delay#1

ch(x) 3LP
Tx pattern#1

0

PINx/NINx

Preset DAC delay#1

ch(x) 3LP
Tx pattern#0

0

00
(GND)

0
11
(Rx)

10/01/00(3LP Tx)

11
(Rx)

0
10/01/00(3LP Tx)

11
(Rx)

00
GND

10/01/00(3LP Tx)00(GND)

10/01/00(3LP Tx)

00
GND

0
11
(Rx)

11
(Rx)

11
(Rx)

00

00
(GND)

00
(GND)

2bit output code of PINx/NINx corresponds to 3LP input code of “S-UM55L2”.
*1: In 3LP Tx driver of “S-UM55L2”, “HiZ” operation is assigned to “00” inputs during DRVSEL =1.

11
(Rx)

00
(GND)

11
(Rx)

11
(Rx)

00
(GND)

00

11
(Rx)

00
GND

00
(GND)

ch(x) DAC
Tx pattern#1

00

10/01/00(3LP Tx)

11(Rx)

10/01/00(3LP Tx)

11
(Rx)

11
(Rx)

00
GND

GND

00
(GND)

00
(GND)

0
11
(Rx)

0
00

11
(Rx)

0

0

0
GND

ch(x) 3LP
Tx pattern#1

0

0

0
GND

11
(Rx)

0

0

Preset width#1

Preset 3LP delay#1

ch(x) DAC
Tx pattern#0

0

DACOUTPx-DACOUTNx

Preset wait#1

Preset width#1

Preset 3LP delay#1

Preset 3LP delay#0
Preset DAC delay#0

TX-PT(x)（x=0~7）

Load Register data at TRIG rise edge

11
(Rx)

0
00
GND

00
(GND)

25

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ Operation Sequence Example (continuation)

TRIG
CLK
TCLK
6TCLK(min)DRVSEL(y)(y=A for ch#0~3,
y=B for ch#4~7)

Ch(x)DAC output:
DACOUTPx-DACOUTNx（x=0~7）TWAIT_DRVSELy
31TCLK~8191TCLK(Δ32TCLK)
TINIT(32TCLK)DACTXCHx=1
PWRSAVE=＊

0 (DAC bias on)

DACTXCHx=0PWRSAVE=0

0 (DAC bias on)

DACTXCHx=0PWRSAVE=1

0 (DAC bias off)
TINIT
(32TCLK)

PINx/NINx(for 3LP)（x=0~7）TWIDTH_DRVSELy
0~65534*32TCLK or until next TRIG rise
(Δ32TCLK)
TPON_DRV : 640TCLK (no Tx)

TDL_DACx : 0~8191TCLK (Δ1TCLK) per ch tWAIT_TRSWTPOFF_DRV : 640TCLK (no Tx)*2

DAC Tx pattern

0 (DAC bias on)

20*TCLK (for TRSW turn off time 100ns)

20*TCLK (for TRSW turn off time 100ns)
tWAIT_TRSW *2
3LP Tx Pattern

TDL_3LPx 0~8191TCLK (Δ1TCLK) per ch

DACTXCHx=1
TLPTXCHx=1
RXCHx=1

11(GND+TRSW)

00(HiZ *1)

1100(GND+TRSW) (GND)

10/01/00(+HV/-HV/GND)DACTXCHx=1
TLPTXCHx=1
RXCHx=0

00
(GND)

00
(HiZ *1)00(GND)00(GND)

10/01/00(+HV/-HV/GND)DACTXCHx=1
TLPTXCHx=0
RXCHx=1

11(GND+TRSW)

00(HiZ *1)DACTXCHx=1
TLPTXCHx=0
RXCHx=0

00
(GND)

11
(GND+TRSW)
00(GND)

00(HiZ *1)*1: In S-UM55L2, 3LP driver outputs “HiZ” state during DRVSELy is “Hi” except both PINX and NINx is “Hi”.

*2: tWAIT_TRSW (0/80/120/160/200/240/280/320TCLK) is adjustable clamp time after transmission (per channel).

00
(GND)

00
(GND)

11

00
(GND)

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

26■ Tx Pattern Generation Timing Chart

TRIG
CLK
TWAIT_DRVSELy
31TCLK~8191TCLK
6TCLK(min)(Δ32TCLK)TCLKDRVSEL(y)(y=A for ch#0~3,
y=B for ch#4~7)

Ch(x)DAC output:
DACOUTPx-DACOUTNx（x=0~7）TINIT(32TCLK)DACTXCHx=1
PWRSAVE=＊

0 (DAC bias on)

DACTXCHx=0PWRSAVE=0

0 (DAC bias on)

DACTXCHx=0PWRSAVE=1

0 (DAC bias off)
TINIT
(32TCLK)DACTXCHx=0
TLPTXCHx=1
RXCHx=1

PINx/NINx(for 3LP)（x=0~7）DACTXCHx=0
TLPTXCHx=1
RXCHx=0

TPON_DRV : 640TCLK (no Tx)

TPOFF_DRV : 640TCLK (no Tx)

TDL_DACx : 0~8191TCLK (Δ1TCLK) per ch

DAC Tx pattern

0 (DAC bias on)

20*TCLK (for TRSW turn off time 100ns)

TDL_3LPx 0~8191TCLK (Δ1TCLK) per ch
11(GND+TRSW)

00
(GND)

DACTXCHx=0
TLPTXCHx=0
RXCHx=1
DACTXCHx=0
TLPTXCHx=0
RXCHx=0

TWIDTH_DRVSELy
0~65534*32TCLK or until next TRIG rise
(Δ32TCLK)

20*TCLK (for TRSW turn off time 100ns)
tWAIT_TRSW *2
3LP Tx Pattern
00
(GND)

00
(HiZ *1)00(GND)

10/01/00(+HV/-HV/GND)
10/01/00(+HV/-HV/GND)

11(GND+TRSW)

00
(GND)

00
(HiZ *1)*1: In S-UM55L2, 3LP driver outputs “HiZ” state during DRVSELy is “Hi” except both PINX and NINx is “Hi”.

*2: tWAIT_TRSW (0/80/120/160/200/240/280/320TCLK) is adjustable clamp time after transmission (per channel).

00
(GND)

00
(GND)

11

00
(GND)

27

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ Tx Pattern Generation Timing Chart (continuation)

TRIG
CLK
(200MHz)

5ns
30ns(min)DRVSEL(y)(y=A for ch#0~3,
y=B for ch#4~7)

Ch(x)DAC output:
DACOUTPx-DACOUTNx（x=0~7）TWIDTH_DRVSELy
TWAIT_DRVSELy
0~10.486ms or until next TRIG rise
0.155~40.955us (Δ0.16us)(Δ0.16us)
TINIT(0.16us)DACTXCHx=1
PWRSAVE=＊

0 (DAC bias on)

DACTXCHx=0PWRSAVE=0

0 (DAC bias on)

DACTXCHx=0PWRSAVE=1

0 (DAC bias off)
TINIT
(0.16us)

PINx/NINx(for 3LP)（x=0~7）

TPON_DRV : 3.2us (no Tx)
TDL_DACx : 0~40955ns (Δ5ns) per ch

TPOFF_DRV : 3.2us (no Tx)
tWAIT_TRSW*2

DAC Tx pattern

0 (DAC bias on)

20*TCLK (for TRSW turn off time 100ns)

20*TCLK (for TRSW turn off time 100ns)
tWAIT_TRSW *2
3LP Tx Pattern

TDL_3LPx 0~40955ns (Δ5ns) per ch

DACTXCHx=1
TLPTXCHx=1
RXCHx=1

11(GND+TRSW)

00(HiZ *1)

1100(GND+TRSW) (GND)

10/01/00(+HV/-HV/GND)DACTXCHx=1
TLPTXCHx=1
RXCHx=0

00
(GND)

00
(HiZ *1)00(GND)00(GND)

10/01/00(+HV/-HV/GND)DACTXCHx=1
TLPTXCHx=0
RXCHx=1

11(GND+TRSW)

00(HiZ *1)DACTXCHx=1
TLPTXCHx=0
RXCHx=0

00
(GND)

11
(GND+TRSW)
00(GND)

00(HiZ *1)*1: In S-UM55L2, 3LP driver outputs “HiZ” state during DRVSELy is “Hi” except both PINX and NINx is “Hi”.

*2: tWAIT_TRSW (0ns/400ns/600ns/800ns/1μs/1.2μs/1.4μs/1.6μs) is adjustable clamp time after transmission (per channel).

00
(GND)

00
(GND)

11

00
(GND)

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D228■ Tx Pattern Generation Timing Chart when use 200MHz CLK (1/2)

TRIG
CLK
(200MHz)

5ns
30ns(min)DRVSEL(y)(y=A for ch#0~3,
y=B for ch#4~7)

Ch(x)DAC output:
DACOUTPx-DACOUTNx（x=0~7）TWIDTH_DRVSELy
TWAIT_DRVSELy
0~10.486ms or until next TRIG rise
0.155~40.955us (Δ0.16us)(Δ0.16us)
TINIT(0.16us)DACTXCHx=1
PWRSAVE=＊

0 (DAC bias on)

DACTXCHx=0PWRSAVE=0

0 (DAC bias on)

DACTXCHx=0PWRSAVE=1

0 (DAC bias off)
TINIT
(0.16us)DACTXCHx=0
TLPTXCHx=1
RXCHx=1

PINx/NINx(for 3LP)（x=0~7）DACTXCHx=0
TLPTXCHx=1
RXCHx=000(GND)

TPOFF_DRV : 3.2us (no Tx)

TDL_DACx : 0~40955ns (Δ5ns) per ch

DAC Tx pattern

20*TCLK (for TRSW turn off time 100ns)

TDL_3LPx 0~40955ns (Δ5ns) per ch
11(GND+TRSW)DACTXCHx=0
TLPTXCHx=0
RXCHx=1
DACTXCHx=0
TLPTXCHx=0
RXCHx=0

TPON_DRV : 3.2us (no Tx)

0 (DAC bias on)

20*TCLK (for TRSW turn off time 100ns)
tWAIT_TRSW *2
3LP Tx Pattern
00
(GND)

00
(HiZ *1)00(GND)

10/01/00(+HV/-HV/GND)
10/01/00(+HV/-HV/GND)

11(GND+TRSW)

00
(GND)

00
(HiZ *1)*1: In S-UM55L2, 3LP driver outputs “HiZ” state during DRVSELy is “Hi” except both PINX and NINx is “Hi”.

*2: tWAIT_TRSW (0ns/400ns/600ns/800ns/1μs/1.2μs/1.4μs/1.6μs) is adjustable clamp time after transmission (per channel).

00
(GND)

00
(GND)

11

00
(GND)

29

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ Tx Pattern Generation Timing Chart when use 200MHz CLK (2/2)

TRIG

TWAIT_DRVSELADRVSELA Ch0~3 3LP selected

TWIDTH_DRVSELBTINIT + TDL_DAC0

Ch0 DAC

0 (DAC bias on)

Ch0 PIN/NIN

11(GND+TRSW)

Ch0~3 3LP selected

Ch0~3 Linear-AMP selected
20*TCLK

20*TCLK

tWAIT_TRSW0DAC Tx pattern

tWAIT_TRSW00 (DAC bias on)

TINIT + TDL_3LP000 (HiZ )00(GND) 11(GND+TRSW)TINIT + TDL_DAC1

Ch1 DAC
Ch1 PIN/NIN

0 (DAC bias on)

DAC Tx pattern

TINIT + TDL_3LP1
11(GND+TRSW)

Ch2 PIN/NIN

00 (HiZ)

00(GND) 11(GND+TRSW)

0 (DAC bias on)

DAC Tx pattern

TINIT + TDL_3LP2
11(GND+TRSW)

00 (HiZ)

0 (DAC bias on)

00(GND)

00(GND)

3LP Tx pattern

tWAIT_TRSW100(GND)

00(GND)

11(GND+TRSW)

00(GND)

tWAIT_TRSW200(GND)

3LP Tx pattern

DRVSELB

0 (DAC bias on)

00 (HiZ)

TWAIT_DRVSELB
Ch4~7 3LP selected00(GND) 11(GND+TRSW)

0 (DAC bias on)

Ch4 PIN/NIN

11(GND+TRSW)

00(GND)

tWAIT_TRSW300(GND)

3LP Tx pattern

11(GND+TRSW)TWIDTH_DRVSELB
Ch4~7 3LP selected

Ch4~7 Linear-AMP selected

TINIT + TDL_DAC4

Ch4 DAC

11(GND+TRSW)tWAIT_TRSW3DAC Tx pattern

11(GND+TRSW)

11(GND+TRSW)

0 (DAC bias on)

TINIT + TDL_3LP3

Ch3 PIN/NIN

11(GND+TRSW)tWAIT_TRSW2TINIT + TDL_DAC3

Ch3 DAC

3LP Tx pattern

0 (DAC bias on)

TINIT + TDL_DAC2

Ch2 DAC

00(GND)

tWAIT_TRSW1tWAIT_TRSW4tWAIT_TRSW4DAC Tx pattern

0 (DAC bias on)

TINIT + TDL_3LP400 (HiZ)
TINIT + TDL_DAC5

Ch5 DAC

0 (DAC bias on)

00(GND) 11(GND+TRSW)

00(GND)

3LP Tx pattern

DAC Tx pattern

11(GND+TRSW)

00 (HiZ )TINIT + TDL_DAC6

Ch6 DAC

00(GND) 11(GND+TRSW)

00(GND)

3LP Tx pattern

tWAIT_TRSW500(GND)

0 (DAC bias on)

DAC Tx pattern

11(GND+TRSW)

00 (HiZ )TINIT + TDL_DAC7

Ch7 DAC

0 (DAC bias on)
00(GND)

11(GND+TRSW)

00(GND)

3LP Tx pattern

TXONFLAG(open-drain)tWAIT_TRSW600(GND)

11

tWAIT_TRSW70 (DAC bias on)

DAC Tx pattern

0 (DAC bias on)

TINIT + TDL_3LP7

Ch7 PIN/NIN

11

tWAIT_TRSW6TINIT + TDL_3LP6

Ch6 PIN/NIN

11

0 (DAC bias on)

TINIT + TDL_3LP5

Ch5 PIN/NIN

00(GND)

tWAIT_TRSW511(GND+TRSW)

00 (HiZ)Tx bursting

00(GND)11(GND+TRSW)

00(GND)Tx bursting

Note: TXONFLAG is newly added open-drain indicator which is “OR” of each channel Tx bursting time.

3LP Tx patternTx burstingtWAIT_TRSW700(GND)

11

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D230■ Tx Timing chart on “TXONFLAG”

GAINADJx[7:0](x=0~7)ICSELx[2:0](x=0~7)3

8IFSx

Ch (x) DAC full scalecurrent controlEN
PWRSAVEDACTXCHx (x=0~7)

TRIG
CLK

VCOMREF

Memory for ch(x) DAC
12bit x 4096

DAC_STARTx[11:0] (x=0~7)
DAC_STOPx[11:0] (x=0~7)
DAC_DLx[12:0] (x=0~7)
DAC_REPEATx[7:0] (x=0~7)
DAC_RPTSELCHxDAC(n)[11:0](x=0~7,n=0~4095)

CHxDATA(n)[11:0](x=0~7, n=0~4095)
12

12

IOPx

DAC

10
46

DRVSELy(y=A for x=0~3
y=B for x=4~7)

INVx, GAINx[9:0](x=0~7)OFSADJx[6:0] (x=0~7)

OUTIFSEL[1:0]=“00” (Current output mode)

7

2

IONx

DACOUTPx (x=0~7)
DACOUTNx (x=0~7)

31

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ DAC Block Diagram (Current Output mode) DAC Equations
IOPx [mA]=IFSx*(2048 + CHxDAC(n))/4096 + IFSx*(1-OFSADJx[6])*3*OFSADJx/16384
IONx [mA]=IFSx*(2048 – CHxDAC(n))/4096 + IFSx*OFSADJx[6]*3*OFSADJx/16384
IOPx - IONx [mA] = 2*IFSx*CHxDAC(n)/4096 + IFSx*(1-2*OFSADJx[6])*3*OFSADJx/16384
IFSx [mA]=1.28*GADJ*(ICSELx+1)
GADJ =1+(6.25e-4)*(1-2*GAINADJx[7])*GAINADJx
CHxDAC(n)=GDx*CHxDATA(n)GDx [V/V]=(1-2*INVX)*(GAINx+1)/1024

 Parameter Definitions
IOPx [mA]: ch(x) DAC positive side output current from AVDD
IONx [mA]: ch(x) DAC negative side output current from AVDD
IOPx - IONx [mA]: ch(x) DAC differential output current
IFSx [mA]: Selectable DAC full scale current (=1.2875mA~10.3mA, step=1.2875mA=25600*VBGR/RBGR at GADJ=1 ）ICSELx(=0~7) : decimal number of 3bit full-scale current selector ICSELx[2:0]
GADJ [V/V]: Gain adjustment coefficient for DAC unit current compensation (=0.9603 ~1.0397, step=3.125e-4)
GAINADJx[7] (=0/1) : polarity bit of gain compensation data for ch(x) differential DAC output (0=positive, 1=negative)
GAINADJx(=0~127) : decimal number of gain compensation data for ch (x) differential DAC except for MSB (GAINADJ[6:0]).
CHxDAC(n) (=-2047~2047) : decimal number of 12bit DAC inputs CHxDAC(n) [11:0] , MSB is polarity bit
CHxDATA(n) (=-2047~2047) : decimal number of 12bit data CHxDATA(n) [11:0] form ch(x) DAC Memory(#n), MSB is polarity bit.
GDx [V/V]: Selectable digital gain for DAC (=-1~1 except for 0, step=1/1024)
INVx (=0/1) : Inversion control of DAC/3LP output polarity. (0=Normal, 1=Inversion)
GAINx (=0~1023) is decimal number of GAINx[9:0]
OFSADJx[6] (=0/1) : polarity bit of offset compensation data for differential DAC output (0=positive, 1=negative),
OFSADJx (=0~63) : decimal number of offset compensation data for ch (x) differential DAC except for MSB (OFSADJx[5:0]).

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

32■ DAC Equations & Parameter Definitions (Current mode)GAINADJx[7:0](x=0~7)ICSELx[2:0](x=0~7)3

8IFSx

Ch (x) DAC full scalecurrent controlEN
PWRSAVEDACTXCHx (x=0~7)

TRIG
CLK

VCOMREF

Memory for ch(x) DAC
12bit x 4096

DAC_STARTx[11:0] (x=0~7)
DAC_STOPx[11:0] (x=0~7)
DAC_DLx[12:0] (x=0~7)
DAC_REPEATx[7:0] (x=0~7)
DAC_RPTSELCHxDAC(n)[11:0](x=0~7,n=0~4095)

CHxDATA(n)[11:0](x=0~7, n=0~4095)
12

VFSx
VOPx

DAC

12

VONx

10
46

DRVSELy(y=A for x=0~3
y=B for x=4~7)

INVx, GAINx[9:0](x=0~7)

7

OFSADJx[6:0] (x=0~7)

OUTIFSEL[1:0]=“10” or “11”(Voltage output mode)

2

DACOUTPx (x=0~7)
DACOUTNx (x=0~7)

33

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ DAC Block Diagram (Voltage Output mode) DAC Equations
VOPx [V]=VFSx*{ +CHxDAC(n)/4096 + (1-OFSADJx[6])* 3* OFSADJx/16384} + VCOMREF
VONx [V]=VFSx*{ –CHxDAC(n)/4096 + OFSADJx[6]* 3* OFSADJx/16384} + VCOMREF
VOPx - VONx [V] = VFSx*{2*CHxDAC(n)/4096 + (1-2*OFSADJx[6])* 3* OFSADJx/16384}
VFSx [V] =0.074*GADJ*(ICSELx+1)@OUTIFSEL[1:0]=“10”=0.083*GADJ*(ICSELx+1) @OUTIFSEL[1:0]=“11”GADJ =1+(6.25e-4)*(1-2*GAINADJx[7])*GAINADJx
CHxDAC(n)=GDx*CHxDATA(n)GDx [V/V]=(1-2*INVX)*(GAINx+1)/1024

 Parameter Definitions
VOPx [V]: ch(x) DAC positive side output voltage
VONx [V]: ch(x) DAC negative side output voltage
VOPx - VONx [V]: ch(x) DAC differential output voltage
VFSx [mA]: Selectable DAC full scale voltage= 0.077V~0.616V, step=0.077V @ GADJ=1 , OUTIFSEL=‘10’= 0.083V~0.664V, step=0.083V @ GADJ=1 , OUTIFSEL=‘11’
ICSELx(=0~7) : decimal number of 3bit full-scale current selector ICSELx[2:0]
GADJ [V/V]: Gain adjustment coefficient for DAC unit current compensation (=0.9603 ~1.0397, step=3.125e-4)
GAINADJx[7] (=0/1) : polarity bit of gain compensation data for ch(x) differential DAC output (0=positive, 1=negative)
GAINADJx(=0~127) : decimal number of gain compensation data for ch (x) differential DAC except for MSB (GAINADJ[6:0]).
CHxDAC(n) (=-2047~2047) : decimal number of 12bit DAC inputs CHxDAC(n) [11:0] , MSB is polarity bit
CHxDATA(n) (=-2047~2047) : decimal number of 12bit data CHxDATA(n) [11:0] form ch(x) DAC Memory(#n), MSB is polarity bit.
GDx [V/V]: Selectable digital gain for DAC (=-1~1 except for 0, step=1/1024)
INVx (=0/1) : Inversion control of DAC/3LP output polarity. (0=Normal, 1=Inversion)
GAINx (=0~1023) is decimal number of GAINx[9:0]
OFSADJx[6] (=0/1) : polarity bit of offset compensation data for differential DAC output (0=positive, 1=negative),
OFSADJx (=0~63) : decimal number of offset compensation data for ch (x) differential DAC except for MSB (OFSADJx[5:0]).

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

34■ DAC Equations & Parameter Definitions (Voltage mode) 3LP DATA Generator
DRVSELy(y=A for x=0~3
y=B for x=4~7)

EN
DACTXCHx (x=0~7)
TLPTXCHx (x=0~7)
RXCHx (x=0~7

4

Ch(x)
Memory for 3LP
128 Byte

TRIG
CLK

CHxWDATAn[7:0](x=0~7, n=0~127)
8

PINx (x=0~7)
3LP
CMOS
NINx
(x=0~7)2bit wave Pattern
DRIVER
Generator

TLP_STARTx[11:0] (x=0~7)
TLP_STOPx[11:0] (x=0~7)
TLP_DLx[12:0] (x=0~7)
TLP_REPEATx[7:0] (x=0~7)
TLP_RPTSELINVx (x=0~7)

PINx (x=0~7)
NINx (x=0~7)

47

 DRVSEL Signal Generator
USE_EXTSIG

EXT_SIGy (y=A,B)
TRIG
CLK
WAITy[7:0](y=A,B)
WIDTHy[15:0](y=A,B)

DRVSEL(y)Wave Generator
24

EN

SEL

DRVSELy(y=A,B)

CMOS
DRIVERDRVSELy (y=A,B)

35

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ 3LP DATA & DRVSEL Generator Block DiagramCh#x(x=0~7)
DAC_MEM.#
0

D11
(MSB)

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0
(LSB)

Default

W/R

CHxDATA0[11:0]

-

W/R

1

CHxDATA1[11:0]

-

W/R

2

CHxDATA2[11:0]

-

W/R

3

CHxDATA3[11:0]

-

W/R

:

:

:

:

n

CHxDATAn[11:0]

-

W/R

:

:

:

:

4092

CHxDATA4092[11:0]

-

W/R

4093

CHxDATA4093[11:0]

-

W/R

4094

CHxDATA4094[11:0]

-

W/R

4095

CHxDATA4095[11:0]-

W/R

In CH#x DAC Memory Map, each 12bit code CHxDATAn[11:0] corresponds to read-out data (CHxDATAn) in 1 clock cyclefrom CH#x DAC Memory#n.
Suffix “x” corresponds to channel number (x=0~7)Suffix “n” corresponds to Memory number of 12bit code (n=0~4095)
CHxDATAn(=-2047~2047) is a decimal value of CHxDATAn[11:0].
Where, CHxDATAn[11] is polarity bit (0:+, 1: -) and decimal number of CHxDATAn[10:0](=0~2047) expresses the absolutevalue.
Note: Memory for DAC has no reset sequence.

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

36■ DAC Memory MAP

CH#x(x=0~7)
3LP_MEM.#0

D7 (MSB)

D6

D5

D4

D3

D2

D1

D0 (LSB)

Default

W/R

CHxCODE0[1:0]

CHxWIDTH0[5:0]00000000

W/R

1

CHxCODE1[1:0]

CHxWIDTH1[5:0]00000000

W/R

2

CHxCODE2[1:0]

CHxWIDTH2[5:0]00000000

W/R

3

CHxCODE3[1:0]

CHxWIDTH3[5:0]00000000

W/R

:

:

:

:

:

n

CHxCODEn[1:0]

CHxWIDTHn[5:0]00000000

W/R

:

:

:

:

:

124

CHxCODE124[1:0]

CHxWIDTH124[5:0]00000000

W/R

125

CHxCODE125[1:0]

CHxWIDTH125[5:0]00000000

W/R

126

CHxCODE126[1:0]

CHxWIDTH126[5:0]00000000

W/R

127

CHxCODE127[1:0]

CHxWIDTH127[5:0]00000000

W/R

In CH#x 3LP DATA Memory Map, each 1-byte code consists of upper 2-bit CHxCODEn[1:0] and lower 6-bit CHxWIDTHn[5:0].
Suffix “x” corresponds to channel number (x=0~7)Suffix “n” corresponds to 1-byte Memory number (n=0~127)
CHxCODEn[1:0] stands for an output state for 3LP Tx burst as shown in Truth Table.
CHxWIDTHn[5:0] expresses the pulse width (TWIDTH) which is calculated as follows.
TCHxWIDTHn [ns] = TCLK * (CHxWIDTHn + 2)
Where, TCLK is the CLKP/CLKN clock period and CHxWIDTHn(=0~63) is decimal number of CHxWIDTHn[5:0].
In case of 200MHz clock
TCLK = 5ns and TCHxWIDTHn [ns] is 10ns ~ 325ns (5ns step)
Memory for 3LP data is reset by power-on transition of VLL.

37

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ 3LP Data Memory MAP

Register Parameter

Function

PDSEL[1:0]CommonDAC OUTPUT pull-down control during DAC bias-off
00: Open, 01: Not used, 10: pull-down to GND with 100Ω, 11: pull-down to VCOMREF with 40kΩ

OUTIFSEL[1:0]CommonDAC OUTPUT mode Selection
00: current output, 01: Not available, 10: voltage output (Ro=14Ω), 11: voltage output (Ro=2Ω)USE_EXTSIG

Common 0: use internal signal for DRVSELA/B, 1: use external signal as DRVSELA/BPWRSAVE

Common 0: DAC bias is on at disable state, 1: DAC bias is off at disable state

DAC_RPTSEL

Common Multiplying factor selection for DAC_REPEATx[7:0] / TLP_REPEATx[7:0] (0=1, 1=16)

TLP_RPTSEL

Common Multiplying factor selection for DAC_REPEATx[7:0] / TLP_REPEATx[7:0] (0=1, 1=16)

DACTXCHx (x=0~7)/channel

Enable/Disable control of DAC Outputs (DACOUTPx/DACOUTNx at CHx) (0:disabled, 1:enable)
In case of PWRSAVE=“1”, ch(x) DAC is also bias-off at DACTXCHx=“0”TLPTXCHx (x=0~7)/channel

Enable/Disable control for 3LP Tx operation at CHx(0: PINx,NINx ="0,0" , 1: PINx,NINx ="0,0" or "1,0" or "0,1" during Tx operation)

RXCHx (x=0~7)/channel

Enable/Disable control for Rx operation(TRSW of TLP ON/Off) at CHx (0: PINx,NINx ="0,0" , 1: PINx,NINx ="1,1" during Rx operation)

WAITy[7:0] (y=A/B)/4channel DRVSELy wait time from TRIG fall : 32*TCLK*WAITy+31*TCLK, WAITy(=0~255) is decimal number of WAITy[7:0]

WIDTHy[15:0] (y=A/B)

DRVSELy Hi duration time (TWIDTH_DRVSELy)/4channel WIDTHy[15:0]= 1111111111111111 : keep Hi until next Trig rise edge or reset with “EN”
else TWIDTH_DRVSELy = 32*TCLK*WIDTHy, WIDTHy(=0~65535) is decimal number of WIDTHy[15:0]

Note: Register parameter hatched by brown color

is latched to F/F with TRIG rise edge.

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

38■ Register Function (1)Function

DAC_STARTx[11:0] (x=0~7) /channel

Start address (0~4095) of the DAC Memory

DAC_STOPx[11:0] (x=0~7)/channelStop address (0~4095) of the DAC Memory

DAC_REPEATx[7:0]/channel

Repeat counts control of DAC Tx waveform pattern generation for ch(x) (x=0~7)
DACx_REPEAT(=0~255) is decimal number of DAC_REPEATx[7:0]
DACx_REPEAT=0, Repeat counts=1
DACx_REPEAT=1~254, Repeat counts=1*DAC_REPEATx or 16*DAC_REPEATx(Multiplying factor (1 or 16) is selectable with DAC_RPTSEL)
DACx_REPEAT=255, Repeat counts = continuous wave (CW)CW is stopped by next TRIG rise edge or SPI access

DAC_DLx[12:0] (x=0~7)/channel

Chx Tx delay from TRIG fall edge : 32*TCLK + TCLK*DAC_DLx, (DAC_DLx = 0~8191) ※1

ICSELx[2:0] (x=0~7)/channel

DAC unit current (IC) , IC(=0.3125~2.5) [uA] = 0.3125*(1+ICSELx)ICSELx(=0~7) is decimal number of ICSELx[2:0]

GAINx[9:0] (x=0~7)/channel

DAC Digital Gain Control at CHx (GDIGx), GDIGx(=1/1024~1) = (1+GAINx)/1024
GAINx(=0~1023) is decimal number of GAINx[9:0]

ACT_GAINADJx (x=0~7)/channel

Option for GAINADJx[7:0] (0: Register GAINADJx[7:0] is not available, 1: Register GAINADJx[7:0] is available )GAINADJx[7:0] (x=0~7)/channel

DAC gain adjustment coefficient (GADJ): 0.9206 ~1.0794 (step=6.25e-4)
GADJ = 1+(1-2*GAINADJx[7])*(6.25e-4)*GAINADJx
GAINADJx[7](=0/1) is polarity bit, GAINADJx(=0~127) is decimal number of GAINADJx[6:0]

ACT_OFSADJx (x=0~7)/channel

Option for OFSADJx[6:0] (0: Register OFSADJx[6:0] is not available, 1: Register OFSADJx[6:0] is available )OFSADJx[6:0] (x=0~7)/channel

DAC differential current offset (ΔIDACPx-IDACNx) adjustment : -63*IC/4 ~ +63*IC/4, step=IC/4
OFSADJx[6] =0: OFSADJx*IC/4 is added to IDACPx. , OFSADJx[6] =1: OFSADJx*IC/4 is added to IDACNx.
OFSADJx(=0~63) is decimal number of OFSADJx[5:0]Note: Register parameter hatched by brown color

is latched to F/F with TRIG rise edge.

※1 . In case of USE_EXTSIG=0 , DAC_DLx=0~639(decimal number) cannot be used due to restrictions with DRVSEL.

39

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Register Parameter

Rev.1.2_00■ Register Function (2)Register Parameter

Function

TLP_STARTx[6:0] (x=0~7)/channelStart address (0~127) of the 3LP Memory

TLP_STOPx[6:0] (x=0~7)/channelStop address (0~127) of the 3LP Memory

TLP_REPEATx[7:0]/channel

Repeat counts control of Tx waveform pattern generation for ch(x) (x=0~7)
TLP_REPEATx(=0~255) is decimal number of TLP_REPEATx[7:0]
TLP_REPEATx=0 : Repeat counts=1
TLP_REPEATx=1~254 : Repeat counts=1*TLP_REPEATx or 16*TLP_REPEATx(Multiplying factor (1 or 16) is selectable with TLP_RPTSEL.)TLP_REPEATx=255 : Repeat counts = continuous wave (CW)CW is stopped by next TRIG rise edge or SPI access

TLP_DLx[12:0] (x=0~7)/channel

Chx Tx delay from TRIG fall edge : 32*TCLK + TCLK*TLP_DLx, (TLP_DLx = 0~8191)

INVx/channel

Polarity inversion of generating DAC/3LP Tx waveform pattern (0:Normal, 1: Inversion)

TRSW_WAITx[2:0]/channelclamp (TRSW-On wait ) time after transmission"000"=0,"001"=80*TCLK, "010"=120*TCLK, "011"=160*TCLK, "100"=200*TCLK, "101"=240*Tclk, "110"=280*TCLK,"111"=320*TCLK

Note: Register parameter hatched by brown color

is latched to F/F with TRIG rise edge.

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

40■ Register Function (3)Function
Commonsetting
Active chselection

ReservedDRVSEL#A
Setting

DRVSEL#B
Setting

REG.#
0

D7 (MSB)

D6

PDSEL[1:0]

D5

D4

OUTIFSEL[1:0]

D3

D2

USE_EXTSIG

D1

D0 (LSB)

Default

W/R

PWRSAVE

DAC_RPTSEL TLP_RPTSEL 00000000

W/R

1

DACTXCH0DACTXCH1DACTXCH2DACTXCH3DACTXCH4DACTXCH5DACTXCH6DACTXCH700000000

W/R

2TLPTXCH0TLPTXCH1TLPTXCH2TLPTXCH3TLPTXCH4TLPTXCH5TLPTXCH6TLPTXCH700000000

W/R

3

RXCH0

RXCH1

RXCH2

RXCH3

RXCH4

RXCH5

RXCH6

RXCH7

00000000

W/R

4RESERVEDC[15:8]

00000000

W/R

5RESERVEDC[7:0]00000000

W/R

6WAITA[7:0]00000000

W/R

7WIDTHA[15:8]

00000000

W/R

8WIDTHA[7:0]00000000

W/R

9WAITB[7:0]00000000

W/R

10WIDTHB[15:8]

00000000

W/R

11

WIDTHB[7:0]00000000

W/R

Note: Register parameter hatched by brownis re-latched into F/F with TRIG rise edge.

41

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ Control Register Map (1)Function

REG.#

D7 (MSB)

D6

D5

12
13

Ch#0
DAC
Setting

DAC_START0[3:0]D1

D0 (LSB)

DAC_STOP0[11:8]

Default

W/R

00000000

W/R

00000000

W/R

00000000

W/R

15

DAC_REPEAT0[7:0]00000000

W/R

16DAC_DL0[12:5]

00000000

W/R

00000000

W/R

00000000

W/R

GAIN0[7:0]00000000

W/R

GAIN_ADJ0[7:0]00000000

W/R

00000000

W/R

17DAC_DL0[4:0]

ICSEL0[2:0]

TRSW_WAIT0[2:0]

ACT_GAINADJ0

20

GAIN0[9:8]

RESERVED0[5:4]21

ACT_OFSADJ0

OFS_ADJ0[6:0]

22

RESERVED0[3]

TLP_START0[6:0]00000000

W/R

23

RESERVED0[2]

TLP_STOP0[6:0]00000000

W/R

24

TLP_REPEAT0[7:0]00000000

W/R

25

TLP_DL0[12:5]

00000000

W/R

26

TLP_DL0[4:0]

27

RESERVED0[1:0]

INV0

DAC_START1[11:4]

28

DAC_START1[3:0]

DAC_STOP1[11:8]

00000000

W/R

00000000

W/R

00000000

W/R

00000000

W/R

29

DAC_STOP1[7:0]30

DAC_REPEAT1[7:0]00000000

W/R

31

DAC_DL1[12:5]

00000000

W/R

00000000

W/R

32
33

DAC_DL1[4:0]
ACT_GAINADJ1ICSEL1[2:0]00000000

W/R

GAIN1[7:0]00000000

W/R

GAIN_ADJ1[7:0]00000000

W/R

00000000

W/R

TRSW_WAIT1[2:0]

34
35

Ch#1
3LP Data
Setting

D2

DAC_STOP0[7:0]

19

Ch#1
DAC
Setting

D3

14

18

Ch#0
3LP Data
Setting

D4

DAC_START0[11:4]

RESERVED1[5:4]

GAIN1[9:8]36

ACT_OFSADJ1

OFS_ADJ1[6:0]

37

RESERVED1[3]TLP_START1[6:0]00000000

W/R

38

RESERVED1[2]TLP_STOP1[6:0]00000000

W/R

39

TLP_REPEAT1[7:0]00000000

W/R

40

TLP_DL1[12:5]

00000000

W/R

00000000

W/R

41

Note: Register parameter hatched by brown

TLP_DL1[4:0]is re-latched into F/F with TRIG rise edge.

RESERVED1[1:0]INV1OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

42■ Control Register Map (2)

Ch#2
DAC
Setting

Ch#2
3LP Data
Setting

Ch#3
DAC
Setting

REG.#

42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58

D7 (MSB)

D6

D5

D3

DAC_START2[3:0]

D2

D1

D0 (LSB)

DAC_STOP2[11:8]
DAC_STOP2[7:0]

Default

W/R

00000000

W/R

00000000

W/R

00000000

W/R

DAC_REPEAT2[7:0]00000000

W/R

DAC_DL2[12:5]

00000000

W/R

00000000

W/R

00000000

W/R

GAIN2[7:0]00000000

W/R

GAIN_ADJ2[7:0]00000000

W/R

00000000

W/R

DAC_DL2[4:0]

ICSEL2[2:0]

TRSW_WAIT2[2:0]

ACT_GAINADJ2

GAIN2[9:8]

RESERVED2[5:4]

ACT_OFSADJ2

OFS_ADJ2[6:0]

RESERVED2[3]TLP_START2[6:0]00000000

W/R

RESERVED2[2]TLP_STOP2[6:0]00000000

W/R

TLP_REPEAT2[7:0]00000000

W/R

TLP_DL2[12:5]

00000000

W/R

TLP_DL2[4:0]

RESERVED2[1:0]

INV2

DAC_START3[11:4]
DAC_START3[3:0]

DAC_STOP3[11:8]

00000000

W/R

00000000

W/R

00000000

W/R

00000000

W/R

59

DAC_STOP3[7:0]60

DAC_REPEAT3[7:0]00000000

W/R

61

DAC_DL3[12:5]

00000000

W/R

00000000

W/R

62
63

DAC_DL3[4:0]
ACT_GAINADJ3ICSEL3[2:0]00000000

W/R

GAIN3[7:0]00000000

W/R

GAIN_ADJ3[7:0]00000000

W/R

00000000

W/R

TRSW_WAIT3[2:0]

64
65

Ch#3
3LP Data
Setting

D4

DAC_START2[11:4]

RESERVED3[5:4]

GAIN3[9:8]66

ACT_OFSADJ3

OFS_ADJ3[6:0]

67

RESERVED3[3]TLP_START3[6:0]00000000

W/R

68

RESERVED3[2]TLP_STOP3[6:0]00000000

W/R

69

TLP_REPEAT3[7:0]00000000

W/R

70

TLP_DL3[12:5]

00000000

W/R

00000000

W/R

71

Note: Register parameter hatched by brown

TLP_DL3[4:0]is re-latched into F/F with TRIG rise edge.

RESERVED3[1:0]

INV3

43

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Function

Rev.1.2_00■ Control Register Map (3)Function

Ch#4
DAC
Setting

Ch#4
3LP Data
Setting

Ch#5
DAC
Setting

Ch#5
3LP Data
Setting

REG.#

72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101

D7 (MSB)

D6

D5

D4

D3

D2

D1

D0 (LSB)

DAC_START4[11:4]
DAC_START4[3:0]

DAC_STOP4[11:8]
DAC_STOP4[7:0]

W/R
W/R

00000000

W/R

00000000

W/R

DAC_REPEAT4[7:0]00000000

W/R

DAC_DL4[12:5]

00000000

W/R

00000000

W/R

00000000

W/R

GAIN4[7:0]00000000

W/R

GAIN_ADJ4[7:0]00000000

W/R

00000000

W/R

DAC_DL4[4:0]

ICSEL4[2:0]

TRSW_WAIT4[2:0]

ACT_GAINADJ4

Default
00000000

GAIN4[9:8]

RESERVED4[5:4]

ACT_OFSADJ4

OFS_ADJ4[6:0]

RESERVED4[3]TLP_START4[6:0]00000000

W/R

RESERVED4[2]TLP_STOP4[6:0]00000000

W/R

TLP_REPEAT4[7:0]00000000

W/R

TLP_DL4[12:5]

00000000

W/R

TLP_DL4[4:0]

RESERVED4[1:0]

INV4

DAC_START5[11:4]
DAC_START5[3:0]

DAC_STOP5[11:8]
DAC_STOP5[7:0]

W/R

00000000

W/R

00000000

W/R

00000000

W/R

DAC_REPEAT5[7:0]00000000

W/R

DAC_DL5[12:5]

00000000

W/R

00000000

W/R

DAC_DL5[4:0]
ACT_GAINADJ500000000ICSEL5[2:0]00000000

W/R

GAIN5[7:0]00000000

W/R

GAIN_ADJ5[7:0]00000000

W/R

00000000

W/R

TRSW_WAIT5[2:0]

RESERVED5[5:4]

GAIN5[9:8]

ACT_OFSADJ5

OFS_ADJ5[6:0]

RESERVED5[3]TLP_START5[6:0]00000000

W/R

RESERVED5[2]TLP_STOP5[6:0]00000000

W/R

Note: Register parameter hatched by brown

TLP_REPEAT5[7:0]00000000

W/R

TLP_DL5[12:5]

00000000

W/R

00000000

W/R

TLP_DL5[4:0]is re-latched into F/F with TRIG rise edge.

RESERVED5[1:0]INV5

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

44■ Control Register Map (4)

Ch#6
DAC
Setting

Ch#6
3LP Data
Setting

Ch#7
DAC
Setting

Ch#7
3LP Data
Setting

REG.#

102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131

D7 (MSB)

D6

D5

D4

D3

D2

D1

D0 (LSB)

DAC_START6[11:4]
DAC_START6[3:0]

DAC_STOP6[11:8]
DAC_STOP6[7:0]

W/R
W/R

00000000

W/R

00000000

W/R

DAC_REPEAT6[7:0]00000000

W/R

DAC_DL6[12:5]

00000000

W/R

00000000

W/R

00000000

W/R

GAIN6[7:0]00000000

W/R

GAIN_ADJ6[7:0]00000000

W/R

00000000

W/R

DAC_DL6[4:0]

ICSEL6[2:0]

TRSW_WAIT6[2:0]

ACT_GAINADJ6

Default
00000000

GAIN6[9:8]

RESERVED6[5:4]

ACT_OFSADJ6

OFS_ADJ6[6:0]

RESERVED6[3]TLP_START6[6:0]00000000

W/R

RESERVED6[2]TLP_STOP6[6:0]00000000

W/R

TLP_REPEAT6[7:0]00000000

W/R

TLP_DL6[12:5]

00000000

W/R

TLP_DL6[4:0]

RESERVED6[1:0]

INV6

DAC_START7[11:4]
DAC_START7[3:0]

DAC_STOP7[11:8]
DAC_STOP7[7:0]

W/R

00000000

W/R

00000000

W/R

00000000

W/R

DAC_REPEAT7[7:0]00000000

W/R

DAC_DL7[12:5]

00000000

W/R

00000000

W/R

DAC_DL7[4:0]
ACT_GAINADJ700000000ICSEL7[2:0]00000000

W/R

GAIN7[7:0]00000000

W/R

GAIN_ADJ7[7:0]00000000

W/R

00000000

W/R

TRSW_WAIT7[2:0]

RESERVED7[5:4]

GAIN7[9:8]

ACT_OFSADJ7

OFS_ADJ7[6:0]

RESERVED7[3]

TLP_START7[6:0]00000000

W/R

RESERVED7[2]

TLP_STOP7[6:0]00000000

W/R

Note: Register parameter hatched by brown

TLP_REPEAT7[7:0]00000000

W/R

TLP_DL7[12:5]

00000000

W/R

00000000

W/R

TLP_DL7[4:0]is re-latched into F/F with TRIG rise edge.

RESERVED7[1:0]

INV7

45

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Function

Rev.1.2_00■ Control Register Map (5)Registerparameter
CRC[7:0]
CAL_CRC[7:0]FunctionTransferred 8bit CRC Data in last SPI Write operation
CRC initial value = 00000000
CRC polynomial equation is X8+X5+X4+1
Calculated CRC values with transferred SDATA in last SPI Write operation

Memory address error for ch#x (x=0~7) 3LP data. (Start and Stop address is same when “TRIG” becomes high.)
ERROR[47:40] If Error has occurred in ch(x), Register bit ERROR[8x+40] is set to “1” and “FAULT” pin becomes to “0” until ERROR[8x+40] is cleared.
Error[8x+40] is cleared with “EN” fall edge or setting Memory address for ch#x 3LP data properly.
Memory address error for ch#x (x=0~7) DAC. (Start and Stop address is same when “TRIG” becomes high.)
ERROR[39:32] If Error has occurred in ch(x), Register bit ERROR[8x+32] is set to “1” and “FAULT” pin becomes to “0” until ERROR[8x+32] is cleared.
Error[8x+32] is cleared with “EN” fall edge or setting Memory address for ch#x DAC properly.
SPI transfer error (CRC un-match) has occurred during Write to memory for ch#x (x=0~7) 3LP data.
ERROR[31:24] If Error has occurred in ch(x), Register bit ERROR[8x+24] is set to “1” and “FAULT” pin becomes to “0” until ERROR[8x+24] is cleared.
Error[8x+24] is cleared when the DATA for ch#x 3LP is transferred to memory normally.
SPI transfer error (CRC un-match) has occurred during Write to memory for ch#x (x=0~7) DAC data.
ERROR[23:16] If Error has occurred in ch(x), Register bit ERROR[8x+16] is set to “1” and “FAULT” pin becomes to “0” until ERROR[8x+16] is cleared.
Error[8x+16] is cleared when the DATA for ch#x DAC is transferred to memory normally.

ERROR[15:8]

SPI transfer error (CRC un-match) has occurred during Write to Register on ch#x (x=0~7).
If Error has occurred in ch(x), Register bit ERROR[8x+8] is set to “1” and “FAULT” pin becomes to “0” until ERROR[8x+8] is cleared.
Error[8x+8] is cleared with “EN” fall edge or re-transferring the data to ch#x Register normally.

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

46■ CRC & Error Register function (1)Registerparameter

Function

ERROR[7]SPI transfer error (CRC un-match) has occurred during Write to Register#0~#11.
If Error has occurred, Register bit ERROR[7] is set to “1” and “FAULT” pin becomes to “0” until ERROR[7] is cleared.
Error[7] is cleared with “EN” fall edge or re-transferring the data to Register#0~#6 normally.

ERROR[6]TRIG “hi” has occurred during SPI operation.
If Error has occurred, Register bit ERROR[6] is set to “1” until it is cleared.
Error[6] is cleared with “EN” fall edge.

ERROR[5]Access to ch#x (x=0~7) 3LP memory has occurred during ch#x (x=0~7) 3LP Tx data is output.
If Error has occurred, Register bit ERROR[5] is set to “1” until cleared.
Error[5] is cleared with “EN” fall edge.

ERROR[4]Access to ch#x (x=0~7) DAC memory has occurred during ch#x (x=0~7) DAC Tx operation.
If Error has occurred, Register bit ERROR[4] is set to “1” until cleared.
Error[4] is cleared with “EN” fall edge.

ERROR[3]Ch#x (x=4~7) 3LP Tx data is output during “1” state of DRVSELB or transition period (640 clock cycle) from rise/fall edge.
If Error has occurred, Register bit ERROR[3] is set to “1” and “FAULT” pin becomes to “0” until ERROR[3] is cleared.
Error[3] is cleared with “EN” fall edge.

ERROR[2]Ch#x (x=0~3) 3LP Tx data is output during “1” state of DRVSELA or transition period (640 clock cycle) from rise/fall edge.
If Error has occurred, Register bit ERROR[2] is set to “1” and “FAULT” pin becomes to “0” until ERROR[2] is cleared.
Error[2] is cleared with “EN” fall edge.

ERROR[1]Ch#x (x=4~7) DAC Tx data is output during “0” state of DRVSELB or transition period (640 clock cycle) from rise/fall edge.
If Error has occurred, Register bit ERROR[1] is set to “1” and “FAULT” pin becomes to “0” until ERROR[1] is cleared.
Error[1] is cleared with “EN” fall edge.

ERROR[0]Ch#x (x=0~3) DAC Tx data is output during “0” state of DRVSELA or transition period (640 clock cycle) from rise/fall edge.
If Error has occurred, Register bit ERROR[0] is set to “1” and “FAULT” pin becomes to “0” until ERROR[0] is cleared.
Error[0] is cleared with “EN” fall edge.

47

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ CRC & Error Register function (2)Function

REG.#

CRC
Code

C0
C1

Error
Code

D7 (MSB)

D6

D5

D4

D3

D2

D1

D0 (LSB)

Default

W/R

CRC[7:0]00000000

W/R

CAL_CRC[7:0]00000000R

E0ERROR[47]ERROR[46]ERROR[45]ERROR[44]ERROR[43]ERROR[42]ERROR[41]ERROR[40]00000000RE1ERROR[39]ERROR[38]ERROR[37]

ERROR[36]ERROR[35]ERROR[34]

ERROR[33]ERROR[32]00000000RE2ERROR[31]ERROR[30]

ERROR[29]ERROR[28]ERROR[27]

ERROR[26]ERROR[25]ERROR[24]00000000RE3ERROR[23]

ERROR[22]ERROR[21]ERROR[20]

ERROR[19]ERROR[18]ERROR[17]ERROR[16]00000000RE4ERROR[15]ERROR[14]ERROR[13]ERROR[12]ERROR[11]ERROR[10]ERROR[9]ERROR[8]00000000ROCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D248■ CRC & Error Register MAP

CS
IC statusEN

TLP TxDAC Tx

TRIG_
Reset

REG Accessduring Rx

REG AccessduringTLP TxREG Accessduring DAC TX(*2)

tocontrol
REG.

TRIG

Internal
Tx-PT(x)Driver
SelectCh(x) DAC
Ch(x) TLP
MEM.
MEM. Readout
Readoutcode
code
CHxDATACHxCODE[1:0]
RXCHｘ
(dec)
0
none
none
none
1
none
none
none
0
none
none
none
1
none
none
none
0
none
none
none
1
none
none
none
none
0
0
＊
none
0
1
＊
none
0
1
＊
none
1
0
＊
none
1
0
＊
none
1
1
＊
CHxDATA none
none＊
CHxDATA none
none
＊
0
none
none
none
1
none
none
none
0
none
none
none
1
none
none
none
0
none
none
none
1
none
none
none
0
none
none
none
1
none
none
none
0
none
none
none
1
none
none
none
0
none
none
none
1
none
none
none
none
0
0
＊
none
0
1
＊
none
0
1
＊
none
1
0
＊
none
1
0
＊
none
1
1
＊

Control Register
INVｘ

GAINx[5:0]Ch(x) DAC digital input
CHxDAC[11:0]

DAC IcBias
On/OffDRVSELy (y=A for ch0~3, y=B for ch4~7),
Ch(x) (x=0~7) TLP DATA & DAC current

＊
＊
＊
＊
＊
＊
＊
0
1
0
1
＊
0
1
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
0
1
0
1
＊

GAINx
(dec)
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
GAINx
GAINx
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊

CHxDAC (*1)
BIASONx DRVSELy
(dec)
0
none
1
0
none
1
0
none
0
0
none
0
1
none
1
1
none
1
0
none
1
0
none
1
0
none
1
0
none
1
0
none
1
0
none
1
1
(GAINx+1)/64*CHxDATA
1
1-1*(GAINx+1)/64*CHxDATA
1
0
none
1
0
none
1
0
none
0
0
none
0
1
none
1
1
none
1
0
none
1
0
none
1
0
none
0
0
none
0
1
none
1
1
none
1
0
none
1
0
none
1
0
none
1
0
none
1
0
none
1
0
none
1

PINx

NINx

CHx DACIOP-ION000(bias-on)1

10(bias-on)000(bias-off)1

10(bias-off)0

00(bias-on)1

10(bias-on)000(bias-on)100(bias-on)0

10(bias-on)0

10(bias-on)100(bias-on)

0(N/A)

0(N/A)

0(bias-on)

0

0

0

0

2*Ic*CHxDAC
2*Ic*CHxDAC000(bias-on)1

10(bias-on)000(bias-off)1

10(bias-off)0

00(bias-on)1

10(bias-on)000(bias-on)1

10(bias-on)000(bias-off)1

10(bias-off)0

00(bias-on)1

10(bias-on)000(bias-on)100(bias-on)0

10(bias-on)0

10(bias-on)100(bias-on)

0(N/A)

0(N/A)

0(bias-on)

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

-

-

1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0

Gen.
Gen.
Gen.
Gen.
Gen.
Gen.

DACTX TLPTX
CHｘ
CHｘ
0
0
＊
0
0
＊
0
0
＊
0
0
＊
1
＊
＊
1
＊
＊
0（TLP)
1＊
0（TLP)
1＊
0（TLP)
1＊
0（TLP)
1＊
0（TLP)
1＊
0（TLP)
1＊
1(DAC)
1＊
1(DAC)
1
＊
0
0
＊
0
0
＊
0
0
＊
0
0
＊
1
＊
＊
1
＊
＊
0
0
＊
0
0
＊
0
0
＊
0
0
＊
1
＊
＊
1
＊
＊
0（TLP)
1＊
0（TLP)
1＊
0（TLP)
1＊
0（TLP)
1＊
0（TLP)
1＊
0（TLP)
1
＊

0

-

-

1

0

Gen.

1(DAC)

1＊＊＊

CHxDATA

none

none

0

GAINx

(GAINx+1)/64*CHxDATA

1

1

0

0

2*Ic*CHxDAC

0

-

-

1

0

Gen.

1(DAC)

1＊＊＊

CHxDATA

none

none

1

GAINx

-1*(GAINx+1)/64*CHxDATA

1

1

0

0

2*Ic*CHxDAC

mode

Rx

to Ch(x) to Ch(x)
TLP
DAC
MEM.
MEM.

Control Register

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1

none
none
none
none
none
none

Gen.
Gen.
Gen.
Gen.
Gen.
Gen.
Gen.
Gen.
none
none
none
none
none
none
none
none
none
none
none
none

PWR
SAVE

0
0
1
1
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
0
0
1
1
＊
＊
0
0
1
1
＊
＊
＊
＊
＊
＊
＊
＊

*1: The decimal point is suppressed.
*2: If ICSELx[2:0] and GAINADJx[7:0] are changed during ch(x) DAC opearting, ch(x) DAC output current will be varied.

INVｘ

49

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Rev.1.2_00■ Truth TableCS
IC status
ENmode

Ch(x) TLP MEM
Accessduring Rx
Ch(x) TLP MEM.
Access during
TLP TxCh(x) TLP MEM.
Access during
DAC TxCh(x) DAC
MEM. Accessduring Rx

Ch(x) DAC
MEM. Accessduring TLP Tx
Ch(x) DAC
MEM. Accessduring DAC Tx
TRIG rise during
CS=Hi
IC disabled
SPI accessduring IC
disabled

to Ch(x) to Ch(x)
DAC
TLP
MEM.
MEM.

to
control
REG.

TRIG

Internal
Tx-PT(x)Control Register
Driver
SelectDACTX TLPTX
CHｘ
CHｘ
0
0
0
0
0
0
0
0
1
＊
1
＊

PWR
SAVE

Ch(x) DAC
Ch(x) TLP
MEM.
MEM. Readout
Readoutcode
code
CHxDATACHxCODE[1:0]
RXCHｘ
(dec)
0
none
none
none
1
none
none
none
0
none
none
none
1
none
none
none
0
none
none
none
1
none
none
none

Control Register
GAINx[5:0]Ch(x) DAC digital input
CHxDAC[11:0]

＊
＊
＊
＊
＊
＊

GAINx
(dec)
＊
＊
＊
＊
＊
＊

CHxDAC (*1)
(dec)
none
none
none
none
none
none

INVｘ
INVｘ

0
0
0
0
0
0

-

1
1
1
1
1
1

-

0
0
0
0
0
0

none
none
none
none
none
none

＊
＊

0

-

1

-

0

Gen.

0（TLP)

＊

1

＊

＊

none

＊

＊

＊

＊

0

-

1

-

0

Gen.

1(DAC)

1＊＊＊

CHxDATA

none

none

0

0

-

1

-

0

Gen.

1(DAC)

1＊＊＊

CHxDATA

none

none

0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1

-

-

0
0
0
0
0
0
0
0
0
0
0
0

none
none
none
none
none
none

＊
＊
＊
＊

Gen.
Gen.
Gen.
Gen.
Gen.
Gen.

＊
＊
0（TLP)
0（TLP)
0（TLP)
0（TLP)
0（TLP)
0（TLP)

0
0
0
0
1
1
＊
＊
＊
＊
＊
＊

0
0
0
0
＊
＊
1
1
1
1
1
1

0
0
1
1
＊
＊
＊
＊
＊
＊
＊
＊

0
1
0
1
0
1
＊
＊
＊
＊
＊
＊

none
none
none
none
none
none
none
none
none
none
none
none

none
none
none
none
none
none
0
0
0
1
1
1

none
none
none
none
none
none
0
1
1
0
0
1

0

1

-

-

0

Gen.

1(DAC)

1

＊

＊

＊

none

＊

＊

1

＊

＊

＊

＊

＊

＊

none

＊

＊
＊
＊
＊

none
none
none
none

＊
＊
＊
＊

＊
＊
＊
＊

＊
＊
＊
＊

＊
＊
＊
＊

＊
＊
＊
＊

none
none
none
none

＊
＊
＊
＊

1

0
1
1
1
1

0
1

1
-

1
-

＊
＊
＊
＊

0
0
1
1
＊
＊

*1: The decimal point is suppressed.
*2: If ICSELx[2:0] and GAINADJx[7:0] are changed during ch(x) DAC opearting, ch(x) DAC output current will be varied.

DAC IcBias
On/OffDRVSELy (y=A for ch0~3, y=B for ch4~7),
Ch(x) (x=0~7) TLP DATA & DAC current

BIASONx DRVSELy

PINx

NINx

CHx DACIOP-ION0(bias-on)

1
1
0
0
1
1

0

0

0

0

1

1

0(bias-on)

0

0

0

0(bias-off)

0

1

1

0(bias-off)

1

0

0

0(bias-on)

1

1

1

0(bias-on)

none

1

Error condition (ERROR[5]=1) N/A

GAINx(GAINx+1)/64*CHxDATA

1

1

0

0

2*Ic*CHxDAC

1

GAINx

-1*(GAINx+1)/64*CHxDATA

1

1

0

0

2*Ic*CHxDAC

＊
＊
＊
＊
＊
＊
＊
0
1
0
1
＊

＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊

none
none
none
none
none
none
none
none
none
none
none
none

1
1
0
0
1
1
1
1
1
1
1
1

0

0

0

0(bias-on)

0

1

1

0(bias-on)

0

0

0

0(bias-off)

0

1

1

0(bias-off)

1

0

0

0(bias-on)

1

1

1

0(bias-on)

0

0

0

0(bias-on)

0

1

0

0(bias-on)

0

0

1

0(bias-on)

0

0

1

0(bias-on)

0

1

0

0(bias-on)00(N/A)

0(N/A)

0(bias-on)

＊

＊

none

1

Error condition (ERROR[4]=1) N/A

＊

＊

＊

none

＊

Error condition (ERROR[6]=1) N/A

＊
＊
＊
＊

＊
＊
＊
＊

＊
＊
＊
＊

none
none
none
none

0
0
0
0

0

0

0

0(bias-off)

0

0

0

0(bias-off)

0

0

0

0(bias-off)

0

0

0

0(bias-off)

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2

50■ Truth Table (continuation)

Pin Name
Function
Pin# Pin Name
FunctionSPI_OFF Control of SPI On/Off (H:Power-off,L:Power-on(50kΩ pull-down)) 35 DACOUTP6CH6 DAC differential outputs
SDOUT
SPI serial output data (tri-state output )36 DACOUTN6
VLL
Positive low voltage power supply for Logic (+1.8V)
37 DACOUTP5CH5 DAC differential outputs
CSP
Positive LVDS chip select (CS) input
38 DACOUTN5
CSN
Negative LVDS chip select (CS) input
39 DACOUTP4CH4 DAC differential outputs
SDATAP Positive LVDS Serial Data input
40 DACOUTN4SDATAN Negative LVDS Serial Data input
41
AGND
Reserved for Testing (Connected to GND)
SCLKP
Positive LVDS serial clock input (up to 100MHz)
42
RBGR
Output for Constant Reference Current (Connect 24kΩ to GND)
SCLKN
Negative LVDS serial clock input (up to 100MHz)
43
FAULT
Fault output flag, Open N-MOS Drain (H:Normal, L:Fault)
DGND
GND for Digital Power Supplies
44
AVSS
Negative Analog Power Supply for DAC (-2~0V)
CLKP
Positive LVDS clock input (up to 200MHz)
45 VCOMREF Output common voltage reference
CLKN
Negative LVDS clock Input (up to 200MHz)
46 DACOUTN3CH3 DAC differential outputs
DVDD
Positive Digital Power Supply for LVDS Receiver (+3.3V)
47 DACOUTP3
TRIG
Trigger signal for operation (CMOS)
48 DACOUTN2CH2 DAC differential outputs
VLL
Positive low voltage power supply for Logic (+1.8V)
49 DACOUTP2ENIC Disable/Enable control (H: Disable (50kΩ pull-up), L:Enable)
50 DACOUTN1CH1 DAC differential outputs
SPI_IFI/F selection for SPI (H:Single CMOS, L:LVDS(default) )51 DACOUTP1
Positive low voltage power supply for Logic I/F (+1.8 ~ 3.3V)
VLLIO
52 DACOUTN0
CH0 DAC differential outputs
53 DACOUTP0
PIN7
2bit Tx data for ch7 3LP
NIN7
54
AGND
GND for Analog Power Supplies
PIN6
55
AVDD
Positive Analog Power Supply for DAC (+3.3V)
2bit Tx data for ch6 3LP
NIN6
56
DGND
GND for Digital Power Supplies
PIN5
57 TXONFLAG Tx DATA output flag, Open N-MOS Drain (L:Outputting Tx DATA)
2bit Tx data for ch5 3LP
NIN558 DRVSELA Driver select signal for ch0~3
PIN4
59 EXT_SIGA External driver select input for ch0~3
2bit Tx data for ch4 3LP
NIN4
60
NIN3
2bit Tx data for ch3 TLP
EXT_SIGB External driver select input for ch4~7
61
PIN3
DRVSELB Driver select signal for ch4~762
NIN22bit Tx data for ch2 TLP
DGNDReserved for Testing (Connected to GND)
63
PIN2
DGND
GND for Digital Power Supplies
64
NIN1
2bit Tx data for ch1 TLP
AVDD
Positive Analog Power Supply for DAC (+3.3V)
65
PIN1
AGND
GND for Analog Power Supplies
66
NIN0
2bit Tx data for ch0 TLP67
PIN0DACOUTP7CH7 DAC differential outputs
DACOUTN7
68
VLLIO
Positive low voltage power supply for Logic I/F (+1.8 ~ 3.3V)

51

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2

Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

Rev.1.2_00■ PIN Descriptions

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2■ PIN Configuration

52

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2
 Package
Package Name
QFN-68(1010)B

Dimension
QN068-B-P-SD

Tray
QN068-B-T-SD

Marking
QN068-B-M-SD

Land
QN068-B-L-SD

Packing
QN068-B-K-SD

 Storage, Mounting
1. Storage conditions
1. 1

The storage location should be kept at 5 to 35°C and 40 to 70% relative humidity. Keeping in a dry box isrecommended. Moisture-proof property is assured for 12 months from delivery date for sealed moisture-proof
packing, while it is guaranteed for 7 days from unpacked date under the condition above.

1. 2When the storage conditions do not conform to those above or other conditions occur indicating moisture
exposure, the ICs should be dried to avoid package cracks. A baking process at 125°C lasting for 24 hours
results in sufficient dehumidification. The baking is not allowed more than twice, and the ICs should be
mounted within 7 days after initial baking or within 10 days of total exposure after the second dehumidification.

2. Reflow soldering
The temperature rise may be different in the resin and a terminal part due to the reflow soldering.
It is necessary to check the package surface temperature (resin) before setting the temperature profile.
Figure 1 shows the resistance to soldering heat condition for package (Reflow method).
Confirm the heat resistance of the package shown below. (Based on JEDEC J-STD-020).
10 s max.
Peak temperature: 260°C
More than 255°C 30 s max.

Temp.
Ramp up rate: 3°C/s max.

Ramp down rate: 6°C/s max.

More than 217°C
60 to 150 s
200°C

150°C
Preheat area: 60 to 120 s

Temperature measurement point:
resin surface temperature

25°C
Time: 8 min max. to peakFigure 1

Time

Resistance to Soldering Heat Condition for Package (Reflow Method)

53

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
S-US55D2
Rev.1.2_00
 Important Notice

54

1.

ABLIC Inc. warrants performance of its hardware products (hereinafter called “products”) to the specifications
applicable at the time of sale in accordance with the Product Specification. Testing and other quality control
techniques are utilized to the extent ABLIC Inc. needs to meet specifications described in the Product Specification.
Specific testing of all parameters of each device is not necessarily performed, except those mandated by related
laws and/or regulations.

2.

Should any claim be made within one month of product delivery about products’ failure to meet performancedescribed in the Product Specification, all the products in relevant lot(s) shall be re-tested and re-delivered.
Products delivered more than one month before such claim shall not be counted for such response.

3.

ABLIC Inc. assumes no obligation or any way of compensation should any fault about customer products andapplications using ABLIC Inc. products be found in marketplace. Only in such a case fault of ABLIC Inc. is evident
and products concerned do not meet the Product Specification, compensation shall be conducted if claimed within
one year of product delivery up to in the way of product replacement or payment of equivalent amount.

4.

ABLIC Inc. reserves the right to make changes to the Product Specification at any time and to discontinue mass
production of the relevant products without notice. Customers are advised before placing orders to confirm that theProduct Specification of inquiry is the latest version and that the relevant product is currently on mass production
status.

5.

In no event shall ABLIC Inc. be liable for any damage that may result from an accident or any other cause during
operation of the user’s units according to the Product Specification. ABLIC Inc. assumes no responsibility for any
intellectual property claims or any other problems that may result from applications of information, products orcircuits described in the Product Specification.

6.

No license is granted by the Product Specification under any patents or other rights of any third party or ABLIC Inc.

7.

The Product Specification may not be reproduced or duplicated, in any form, in whole or in part, without theexpressed written permission of ABLIC Inc.

8.

Resale of ABLIC Inc. products with statements different from or beyond the parameters described in the ProductSpecification voids all express and any implied warranties for the products, and is an unfair and deceptive businesspractice. ABLIC Inc. is not responsible or liable for any such statements.

9.

Products (technologies) described in the Product Specification are not to be provided to any party whose purpose in
their application will hinder maintenance of international peace and safety nor are they to be applied to that purposeby their direct purchasers or any third party. When exporting those products (technologies), the necessary
procedures are to be taken in accordance with related laws and regulations.

OCTAL DAC WITH DIFFERENTIAL OUTPUTS AND 2-BIT PER CHANNEL CMOS OUTPUTPATTERN GENERATORS FOR ULTRASOUND TRANSMITTER
Rev.1.2_00
S-US55D2
 Cautions
1.

Customers are advised to follow the cautions below to protect products from damage caused by electrical static
discharge (ESD).
1. 1

Material of container or any device to carry products should be free from ESD, which may be caused byvibration while transportation. It is recommended that electric-conductive container or aluminum sheet be used
as an effective countermeasure.

1. 2

Those that touch products, such as work platform, machine, or measurement/test equipment, should begrounded.

1. 3

Those who deal with products should be grounded through a large series impedance around 100kΩ to 1MΩ.

1. 4

Prevent friction with other materials made with high polymer.

1. 5

Prevent vibration or friction when carrying the printed circuit board (PCB) where products are mounted. To
short circuit terminals is a recommended countermeasure to keep the same electric potential on the PCB.

1. 6

Avoid dealing with or storing products in an extremely arid environment.

2.

“Absolute maximum ratings” should never be exceeded during use regardless of any change in external conditions.
Otherwise, products may be damaged or destroyed. In no event shall ABLIC Inc. be liable for any failure in products
or any secondary damage resulting from use at a value exceeding the absolute maximum ratings.

3.

Products may experience failures due to accident or unexpected surge voltages. Accordingly, adopt safe design
features, such as redundancy or prevention of erroneous action, to avoid extensive damage in the event of a failure.
(If a semiconductor device fails, there may be cases in which the semiconductor device, wiring or wiring pattern will
emit smoke or cause a fire or in which the semiconductor device will burst.)

4.

Products may experience failures or malfunction in poor surroundings, such as electrical leakage in products due tolong-term use in high humidity, malfunctioning or permanent damage due to chemical reaction of products incorrosive environment or due to discharge by strongly charged object near products or due to excessive mechanicalshock. To use products in radiation environment is not assumed. To use products near material easy to ignite may
cause a fire due to its flammable package. Avoid using products in such environment or take appropriate
countermeasures depending on the environment.

5.

Products are not designed, manufactured, or warranted to be suitable for use where extremely high reliability isrequired (such as use in nuclear power control, aerospace and aviation, traffic equipment, life-support-related
medical equipment, fuel control equipment and various kinds of safety equipment). Inclusion of products in suchapplication shall be fully at the risk of customers. ABLIC Inc. assumes no liability for applications assistance,
customer product design, or performance.

55

(8.5)

10.0±0.1
51

35
34

68

18

(8.5)

10.0±0.1

52

1

17

Index

0.4±0.1

0.5±0.1

0.25±0.05(0.2)

0.9 max.

(0.35)

No. QN068-B-P-SD-2.0

TITLE

QFN68-B-PKG Dimensions

No.

QN068-B-P-SD-2.0

ANGLE
UNIT

mm

ABLIC Inc.

R
1.
60

322.60±0.25

10.30
11.95

12.70

92.10

135.90±0.25

16

R
2.
50

315.00

C3.5

11

14.65

10.30

25.40

255.30

5.62

34.30

2.54

50
2.
R

7.62

5.62
7.62

( Direction of IC in tray )(1) (2) (3) (4) (5) (6)(7) (8) (9) (10) (11) (12)(13) (14) (15) (16) (1
7)

(18)

(21) (22) (2
3)

(24)

(19) (20)

No. QN068-B-T-SD-1.0

Tray index
1#Pin

TITLE

QFN68-B-Tray

No.

QN068-B-T-SD-1.0

ANGLE
UNIT

QTY.
mm

ABLIC Inc.

168

(1) (2) (3) (4) (5) (6) (7) (8)(9) (10) (11) (12) (13) (14) (15)(16) (17) (18) (19) (20)(21) (22) (23) (24) (25)(A)(1) to (10): Product code(11) , (12): Quality control code(13)

: Year of assembly(14): Month of assembly(15): Week of assembly(16) to (25) : Quality control code(A)

: 1-pin markNo. QN068-B-M-SD-2.0

TITLE

QFN68-B-M a r k i n g s

No.

QN068-B-M-SD-2.0

ANGLE
UNIT

TYPE

ABLIC Inc.

LASER

8.50
35

51

34

68

18

0.50
0.75

0.32

8.50

10.60

5.30

52

0.75
1

17

5.30
10.60

No. QN068-B-L-SD-2.0

TITLE

QFN68-B-Land Recommendation

No.

QN068-B-L-SD-2.0

ANGLE
UNIT

mm

ABLIC Inc.

Max. 168 ICs/Tray
IC Index
Empty tray on the top
1 Tray = Max. 168 ICs/Box

Tray Index

P-P Bands
Humidity Indicator Card

Label

Solid Desiccant

Dry Pack

Air cushion

Box(Cardboard Paper)

Label

No. QN068-B-K-SD-2.0

TITLE

QFN68-B-Packing ProcedureNo.

QN068-B-K-SD-2.0

ANGLE
UNIT

ABLIC Inc.

Disclaimers (Handling Precautions)1.

All the information described herein (product data, specifications, figures, tables, programs, algorithms andapplication circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.

2.

The circuit examples and the usages described herein are for reference only, and do not guarantee the success ofany specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any otherright due to the use of the information described herein.

3.

ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information describedherein.

4.

Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due tothe use of the products outside their specified ranges.

5.

Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.

6.

When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-relatedlaws, and follow the required procedures.

7.

The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,biological or chemical weapons or missiles, or use any other military purposes.

8.

The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.

9.

In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products areallowed to apply for the system on customer's own responsibility.

10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of thisdocument described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07

www.ablic.com