Shanghai Chipanalog Microelectronics Co., Ltd.

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

CA-IS36xx High-performance, 5kVRMS Reinforced Digital Isolators with
Integrated high-efficiency, Low-emissions DC-DC Converter
1

Features3•

Integrated High-efficiency DC-DC Converter withonchip Transformer
 Regulated output options: 3.3 V or 5.0 V
 Up to 650mW output power Soft-start to limit inrush current and overshoot Overload and short-circuit protection
 Thermal shutdown Low emissions
Robust Galvanic Isolation of Digital Signals
 High lifetime: > 40 years
 Withstands 5kVRMS for 60s
 ±150 kV/μs typical CMTI Schmitt trigger inputs
Interfaces Directly with Most Micros and FPGAs
 Data rate: DC to 150Mbps
 3V to 5.5V single supply operation, also provide
individual logic supply input (CA-IS36xxLVW and
CA-IS36xxHVW devices only) Default output High (CA-IS362xH, CA-IS364xH)
and Low (CA-IS362xL, CA-IS364xL) Options
Best in class propagation delay and skew
 10ns typical propagation delay 2ns propagation delay skew (chip -to-chip) 1ns pulse width distortion
No Start-Up Initialization Required
Wide-body SOIC16-WB(W) package
Wide operating temperature range: -40°C to 125°C
Safety Regulatory Approvals
 VDE 0884-11 Reinforced Isolation
 UL According to UL1577
 IEC 62368-1, IEC 61010-1, IEC 60950-1, GB
4943.1-2011 certifications (Pending)

The CA-IS36xx family integrated signal and power isolation
devices simplify system design and reduce board area.
These devices are high-performance, dual-channel andfour-channel, unidirectional reinforced digital isolatorswith up to 5kVRMS isolation rating and ultra-fast data rate.
The integrated isolated DC-DC converter provides up to650mW of isolated power and different output voltage
configurations. These devices offer high electromagnetic
immunity and low emissions while isolating different
ground domains and block high-voltage/high-current
transients from sensitive or human interface circuitry. Eachisolation channel has a logic input and output buffer
separated by capacitive silicon dioxide (SiO2) insulation
barrier, the integrated Schmitt trigger on each input
provide excellent noise immunity.

•

•

•

•
•
•
•

2

Applications

•
•
•
•

Industrial automation systems
Motor control
Medical equipment
Test and Measurement

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

General Description

The CA-IS3620/CA-IS3621/CA-IS3622 devices are dualchannel digital isolators and the CA-IS3640/CA-IS3641/CAIS3642/CA-IS3643/CA-IS3644 devices are quad-channel
digital isolators. They offer all possible unidirectional
channel configurations to accommodate any 2-channel or
4-channel digital I/Os design, including SPI, RS-485, anddigital I/O applications, see Name Convention for moredetail, also Table 5-1 shows the detail configurations ofdigital signal transmission direction for each part. The CAIS36xx family also features different default outputs. Whenthe input is either not powered or is open-circuit, thedefault output is low for devices with suffix L and high fordevices with suffix H, see the Ordering Information forsuffixes associated with each option. The individual logic
supply input of CA-IS36xxLVW and CA-IS36xxHVW devices
allows fully compatible +3.3V and +5.0V logic on side-Adigital lines.
The CA-IS36xx family devices are specified over the -40°C
to +125°C operating temperature range and are available
in 16-pin SOIC wide body package.

1

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644
Version 1.05 2022/12/19

Shanghai Chipanalog Microelectronics Co., Ltd.

Device Information
PART NUMBER
CA-IS3620
CA-IS3621
CA-IS3622
CA-IS3640
CA-IS3641
CA-IS3642
CA-IS3643
CA-IS3644

PACKAGEBODY SIZE(NOM)

SOIC16-WB(W)

10.30 mm × 7.50 mm

Simplified Functional Diagram

VDD

DCDC Secondary Side

DCDC Primary Side

Isolation
Barrrier

VIN

4CA-IS36 M N H W
Number of Revered Channels

2

GNDB

Name Convention

Number of Channels

2

VOUT

Driver
RX

GNDA

VISO

Default Output
H: High Level
L: Low Level

Package
W: SOIC16-WB

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

Shanghai Chipanalog Microelectronics Co., Ltd.

5

Ordering Information
Table 5-1. Ordering Information

Ordering Part
NumberCA-IS3620LW
CA-IS3620HW
CA-IS3621LW
CA-IS3621HW
CA-IS3622LW
CA-IS3622HW
CA-IS3640LW
CA-IS3640HW
CA-IS3641LW
CA-IS3641HW
CA-IS3642LW
CA-IS3642HW
CA-IS3643LW
CA-IS3643HW
CA-IS3644LW
CA-IS3644HW
CA-IS3620LVW
CA-IS3620HVW
CA-IS3621LVW
CA-IS3621HVW
CA-IS3622LVW
CA-IS3622HVW
CA-IS3640LVW
CA-IS3640HVW
CA-IS3641LVW
CA-IS3641HVW
CA-IS3642LVW
CA-IS3642HVW
CA-IS3643LVW
CA-IS3643HVW
CA-IS3644LVW
CA-IS3644HVW

Number of Inputs
A Side
2
2
1
1
0
0
4
4
3
3
2
2
1
1
0
0
2
2
1
1
0
0
4
4
3
3
2
2
1
1
0
0

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

Number of Inputs
B Side
0
0
1
1
2
2
0
0
1
1
2
2
3
3
4
4
0
0
1
1
2
2
0
0
1
1
2
2
3
3
4
4

Default Output

Pin 7

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL
VDDL

Isolation
Rating (kV)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0

Package
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB
SOIC16-WB

3

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644
Version 1.05 2022/12/19

1
2
3
4
5
6
7
8

6

Features .............................................................1
Applications........................................................1
General Description ............................................1
Name Convention ...............................................2
Ordering Information ..........................................3
Revision History ..................................................4
Pin Configuration and Functions ..........................5
Specifications .....................................................7

8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9

Absolute Maximum Ratings1, 2 ............................7
ESD Ratings..........................................................7
Recommended Operating Conditions .................7
Thermal Information ...........................................7
Power Rating .......................................................7
Insulation Specifications .....................................8
Safety-Related Certifications ...............................9
Electrical Characteristics ...................................10
Supply Current Characteristics ..........................13

8.10
8.11

Timing Characteristics ....................................... 19
Typical Characteristics ....................................... 20

10.1
10.2
10.3
10.4
10.5

Overview ........................................................... 26
Functional Block Diagram ................................. 26
Undervoltage Protection................................... 27
Isolated Supply Output ..................................... 27
Operation Modes .............................................. 28

11.1
11.2

Typical Application ............................................ 29
PCB Layout Guidelines ...................................... 30

9 Parameter Measurement Information ............... 25
10 Detailed Description .........................................26

11 Application and Implementation ....................... 29
12
13
14
15

Package Information .........................................32
Soldering Temperature (reflow) Profile .............. 33
Tape and Reel Information ................................34
IMPORTANT NOTICE..........................................36

Revision History

Revision Number
Version 1.00
Version 1.00
Version 1.02
Version 1.03
Version 1.04
Version 1.05

4

Table of Contents

Shanghai Chipanalog Microelectronics Co., Ltd.

Description
N/A
Updated pin descriptions, removed package information table.
Added Bypass Capacitors Selections.
Added PCB Layout Guidelines section.
Added new parts of CA-IS364_VW,
Updated PCB layout Guidelines.
Add supply configuration
Updated VDE and UL certification by adding certification number.
Update POD

Date

2022.12.19

Page Changed
N/A
5, 30
29
29
3
26
29
9
31

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

Shanghai Chipanalog Microelectronics Co., Ltd.
7

Pin Configuration and Functions
CA-IS3620 16-Pin SOIC WB Top View

2

VI1

3

TX

VI2

4

TX

NC

5

NC

6

NC/VDDL

7

GNDA

8

VISO

VDD

1

15

GNDB

GNDA

2

RX

14

VO1

VI1

3

TX

RX

13

VO2

VO2

4

RX

12

NC

NC

5

11

SEL

NC

6

10

NC

NC/VDDL

7

9

GNDB

GNDA

8

16

VISO

VDD

1

15

GNDB

GNDA

2

RX

14

VO1

VO1

3

RX

TX

13

VI2

VO2

4

RX

12

NC

NC

5

11

SEL

NC

6

10

NC

NC/VDDL

7

9

GNDB

GNDA

8

ISOLATION BARRIER

GNDA

16

ISOLATION BARRIER

1ISOLATION BARRIERVDDCA-IS3622 16-Pin SOIC WB Top View

CA-IS3621 16-Pin SOIC WB Top View

16

VISO

15

GNDB

TX

14

VI1

TX

13

VI2

12

NC

11

SEL

10

NC

9

GNDB

Figure 7-1. CA-IS362x pin configuration
Table 7-1. CA-IS362x Pin Description and Functions
CA-IS3620
1
2, 8
3
4
5, 6

16-SOIC(W) Pin#
CA-IS3621
CA-IS3622
1
1
2, 8
2, 8
3
14
13
13
5, 6

5, 6

Name

Type

Description

VDD
GNDA
VI1
VI2

SupplyGroundDigital I/O
Digital I/O

NC

---

NC

---

VDDL1

SupplyPower supply for side A. Bypass to GNDA with 10μF||0.1μF capacitors.
Ground reference for side A.
Digital input 1 on side A/B, corresponds to logic output 1 on side B/A.
Digital input 2 on side A/B, corresponds to logic output 2 on side B/A.
Not internally connected. These pins can be left open or tied to VDD or
GNDA.
For the CA-IS362xLW and CA-IS362xHW devices, this pin is NC, means notinternally connected. It can be left open or tied to VDD or GNDA.
For the CA-IS362xLVW and CA-IS362xHVW devices, this pin is logic-supply
input. VDDL is the logic supply voltage for side-A input/output. Bypass to
GNDA with a 0.1µF capacitor.
Not internally connected. These pins can be left open or tied to VISO or
GNDB.
Ground reference for side B.
VISO output selection pin, see Table 10-3.
VISO = 5 V, when SEL is connected to VISO.
VISO = 3.3 V, when SEL is connected to GNDB or left floating.
Digital output 2 on side B/A, VO2 is the logic output for the VI2 input onside A/B.
Digital output 1 on side B/A, VO1 is the logic output for the VI1 input onside A/B.
Output of the isolated DC-DC converter. Bypass to GNDB with
10μF||0.1μF capacitors. The 0.1μF capacitor should be placed as close as
possible to the pin.

7

7

7

10, 12

10, 12

10, 12

NC

9, 15

9, 15

9, 15

GNDB

No
Connect
Ground

11

11

11

SEL

Digital I/O

13

4

4

VO2

Digital I/O

14

14

3

VO1

Digital I/O

16

16

16

VISO

SupplyNote:
1. Logic-Supply Input. VDDL can be different voltage from VDD supply, which allows fully compatible +3.3V and +5.0V logic on side-A digital lines.

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

5

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644
Version 1.05 2022/12/19

CA-IS3641 16-Pin SOIC WB Top View

CA-IS3640 16-Pin SOIC WB Top View

2

VI1

3

TX

VI2

4

TX

VI3

5

TX

VI4

6

TX

NC/
VDDL

7

GNDA

8

VISO

VDD

1

15

GNDB

GNDA

2

RX

14

VO1

VI1

3

TX

RX

13

VO2

VI2

4

TX

RX

12

VO3

VI3

5

TX

RX

11

VO4

VO4

6

RX

10

SEL

NC/
VDDL

7

9

GNDB

GNDA

8

VISO

VDD

1

15

GNDB

GNDA

2

RX

14

VO1

VI1

3

TX

RX

13

VO2

VI2

4

TX

RX

12

VO3

VO3

5

RX

TX

11

VI4

VO4

6

RX

10

SEL

NC/
VDDL

7

9

GNDB

GNDA

8

CA-IS3643 16-Pin SOIC WB Top View

GNDA

2

VI1

3

TX

VO2

4

RX

VO3

5

RX

VO4

6

RX

NC/
VDDL

7

GNDA

8

16

VISO

15

GNDB

RX

14

VO1

RX

13

VO2

TX

12

VI3

TX

11

VI4

10

SEL

9

GNDB

CA-IS3644 16-Pin SOIC WB Top View
16

VISO

VDD

1

15

GNDB

GNDA

2

RX

14

VO1

VO1

3

RX

TX

13

VI2

VO2

4

RX

TX

12

VI3

VO3

5

RX

TX

11

VI4

VO4

6

RX

10

SEL

NC/
VDDL

7

9

GNDB

GNDA

8

ISOLATION BARRIER

1ISOLATION BARRIERVDDCA-IS3642 16-Pin SOIC WB Top View
16

ISOLATION BARRIER

GNDA

16

ISOLATION BARRIER

1ISOLATION BARRIER

VDDShanghai Chipanalog Microelectronics Co., Ltd.

16

VISO

15

GNDB

TX

14

VI1

TX

13

VI2

TX

12

VI3

TX

11

VI4

10

SEL

9

GNDB

Figure 7-2. CA-IS364x pin configuration

CAIS3640

16-SOIC(W) Pin#
CACACAIS3641
IS3642
IS3643

Table 7-2. CA-IS364x Pin Description and Functions
CAIS3644

Name

Type

1

1

1

1

1

VDD

Supply

2, 8
3
4
5
6

2, 8
3
4
5
11

2, 8
3
4
12
11

2, 8
3
13
12
11

2, 8
14
13
12
11

GNDA
VI1
VI2
VI3
VI4

GroundDigital I/O
Digital I/O
Digital I/O
Digital I/O

NC

---

VDDL1

Supply

7

7

7

7

7

9, 15

9, 15

9, 15

9, 15

9, 15

GNDB

Ground

10

10

10

10

10

SEL

Digital I/O

11

6

6

6

6

VO4

Digital I/O

12

12

5

5

5

VO3

Digital I/O

13

13

13

4

4

VO2

Digital I/O

14

14

14

14

3

VO1

Digital I/O

16

16

16

16

16

VISO

Supply6

Description
Power supply for side A. Bypass to GNDA with 10μF||0.1μF
capacitors.
Ground reference for side A.
Digital input 1 on side A/B, corresponds to logic output 1 on side B/A.
Digital input 2 on side A/B, corresponds to logic output 2 on side B/A.
Digital input 3 on side A/B, corresponds to logic output 3 on side B/A.
Digital input 4 on side A/B, corresponds to logic output 4 on side B/A.
Not internally connected for the CA-IS364xLW and CA-IS364xHW
devices.
For the CA-IS364xLVW and CA-IS364xHVW devices, this pin is logicsupply input. VDDL is the logic supply voltage for side-A input/output.
Bypass to GNDA with a 0.1µF capacitor.
Ground reference for side B.
VISO selection pin, see Table 10-3. VISO = 5 V, when SEL is connected to
VISO; VISO = 3.3 V, when SEL is connected to GNDB or left floating.
Digital output 4 on side B/A, VO4 is the logic output for the VI4 input
on side A/B.
Digital output 3 on side B/A, VO3 is the logic output for the VI3 input
on side A/B.
Digital output 2 on side B/A, VO2 is the logic output for the VI2 input
on side A/B.
Digital output 1 on side B/A, VO1 is the logic output for the VI1 input
on side A/B.
Output of the isolated DC-DC converter. Bypass to GNDB with
10μF||0.1μF capacitors.

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

Shanghai Chipanalog Microelectronics Co., Ltd.

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

Note:
1. Logic-Supply Input. VDDL can be different voltage from VDD supply, which allows fully compatible +3.3V and +5.0V logic on side-A digital lines.

8

Specifications
8.1

Absolute Maximum Ratings1, 2

VDD, VDDL
VISOSupply voltage
Isolated supply voltage

MIN
-0.5
-0.5

MAX
6.0
6.0

VIO

Voltage at VIx, VOx, SEL pins

-0.5

VDD+0.53

UNIT
V
V
V

IO
Output current
-20
20
mA
TJ
Junction temperature
150
°C
TSTG
Storage temperature
-65
150
°C
Notes:
1.
The stresses listed under “Absolute Maximum Ratings” are stress ratings only, not for functional operation condition. Exposure to absolute
maximum rating conditions for extended periods may cause permanent damage to the device.
2.
All voltage values are with respect to the local ground terminal (GNDA or GNDB) and are peak voltage values.
3.
Maximum voltage must not be exceed 6 V.

8.2

ESD Ratings

VESD Electrostatic discharge

VALUE
±6000
±2000

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins1
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins2

UNIT
V

Notes:
1. Per JEDEC document JEP155, 500V HBM allows safe manufacturing of standard ESD control process.
2. Per JEDEC document JEP157, 250V CDM allows safe manufacturing of standard ESD control process.

8.3

Recommended Operating Conditions

VDD
VDDL

Supply Voltage
Logic Supply Voltage

IOH

High-level Output Current

VDDO1 = 5V
VDDO = 3.3V

IOL

Low-level Output Current

VDDO = 5V
VDDO = 3.3V

VIH
High-level Input Voltage
VIL
Low-level Input Voltage
DR
Data RateTA
Ambient TemperatureNote:
1. VDDO = Output-side supply, VISO.

8.4

MIN
3.15
2.375
-4
-2

TYP

8.5
PD

UNIT
V
V
mA

4
2

mA

2.0
0
-40

0.8
150
125

25

V
V
Mbps
°C

Thermal Information
CA-IS36xx

THERMAL METRIC
RθJA

MAX
5.5
5.5

UNIT

SOIC16-WB

Junction-to-ambient thermal resistance

68.5

°C/W

Power Rating
PARAMETER
Maximum Power Dissipation

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

TEST CONDITIONSVDD = 5.5V, VISO = 5V, IISO = 130mA, all the input
signal is 50% duty circle square and CL = 15pF.

MIN

TYP

MAX

UNIT

1

W
7

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644
Version 1.05 2022/12/19
8.6 Insulation Specifications
CLR
CPG
DTI
CTI

PARAMETRTEST CONDITIONS

External clearance
External creepage
Distance through the insulation
Comparative tracking index
Material group

Shortest terminal-to-terminal distance through air
Shortest terminal-to-terminal distance across the package surface
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 400 VRMS
Rated mains voltage ≤ 600 VRMS

Overvoltage category per IEC 60664-1
DIN V VDE V 0884-11:2017-011
VIORM
Maximum repetitive peak isolation voltage
VIOWM

Maximum working isolation voltage

VIOTM

Maximum transient isolation voltage

VIOSM

Maximum surge isolation voltage2

qpd

Shanghai Chipanalog Microelectronics Co., Ltd.

Apparent charge3

CIO

Barrier capacitance, input to output4

RIO

Isolation resistanceAC voltage (bipolar)
AC voltage; Time dependent dielectric breakdown (TDDB) Test
DC voltage
VTEST = VIOTM,
t = 60 s (qualification);
VTEST = 1.2 × VIOTM,
t= 1 s (100% production)
Test method per IEC 60065, 1.2/50 μs waveform,
VTEST = 1.6 × VIOSM (qualification)
Method a, after input/output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s
Method b1, at routine test (100% production) and preconditioning(type test)
Vini = 1.2 × VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
VIO = 0.4 × sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C

Pollution degree
UL2
VISO(max)

Maximum withstanding isolation voltage

VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 × VISO , t = 1 s (100% production)

VALUE
W
8
8
19
>400
II
I-IV
I-IV
I-III

UNIT
mm
mm
μm
V

1414
1000
1414

VPK
VRMS
VDC

7070

VPK

6250

VPK

≤5

≤5

pC

≤5
~0.5
>1012
>1011
>109
2

pF

5000

VRMS

Ω

Notes:
1.
This coupler is suitable for “safe electrical insulation” only within the safety ratings. Compliance with the safety ratings shall be ensured bymeans of suitable protective circuits.
2.
Devices are immersed in oil during surge characterization test.
3.
The characterization charge is discharging charge (pd) caused by partial discharge.
4.
Capacitance and resistance are measured with all pins on field-side and logic-side tied together.

8

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

Shanghai Chipanalog Microelectronics Co., Ltd.
8.7 Safety-Related Certifications
VDE
Certified according to DIN
VDE V 0884-11:2017-01

CSA(Pending)
Certified according to IEC
60950-1 and IEC 60601-1

Basic isolation:
Maximum transientisolation voltage: 7070Vpk
Maximum repetitive-peakisolation voltage: 849 Vpk
Maximum surge isolation
voltage: 6250Vpk.
Reinforced isolation:
Maximum transientisolation voltage: 7070Vpk
Maximum repetitive-peakisolation voltage: 1414 Vpk
Maximum surge isolation
voltage: 6250Vpk.(Pending)
Certificate number:
40054252

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

UL
Recognized under UL
1577 Component
Recognition Program

CQC(Pending)
Certified according toGB4943.1-2011

TUV(Pending)
Certified according to EN
61010-1:2010 (3rd Ed)
and EN 609501:2006/A2:2013

Protection voltage:
5kVRMS

Certificate number:
UL-US-2125790-0

9

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644
Version 1.05 2022/12/19
8.8 Electrical Characteristics
5 V Input, 5 V output

Shanghai Chipanalog Microelectronics Co., Ltd.

VDD = VDDL = 5 V ± 10%, TA = -40 to 125°C, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)
VISO

IISO

Parameters
Isolated supply voltage

Maximum load current1

VISO（LINE） DC line regulation
VISO（LOAD） DC load regulation
EFF

Efficiency@maximum load current

Test Conditions
IISO = 0 to 130mA
Data-rate of each channel: DR<1Mbps
CA-IS3622LW/CA-IS3622LVW/
CA-IS3622HW/CA-IS3622HVW/
CA-IS3644LW/CA-IS3644LVW/
CA-IS3644HW/CA-IS3644HVW
Data-rate of each channel: DR = 100Mbps
CA-IS3621LW/CA-IS3621LVW/
CA-IS3621HW/CA-IS3621HVW/
CA-IS3643LW/CA-IS3643LVW/
CA-IS3643HW/CA-IS3643HVW
Data-rate of each channel: DR = 100Mbps
CA-IS3620LW/CA-IS3620LVW/
CA-IS3620HW/CA-IS3620HVW/
CA-IS3642LW/CA-IS3642LVW/
CA-IS3642HW/CA-IS3642HVW
Data-rate of each channel: DR = 100Mbps
CA-IS3641LW/CA-IS3641LVW/
CA-IS3641HW/CA-IS3641HVW
Data-rate of each channel: DR = 100Mbps
CA-IS3640LW/CA-IS3640LVW/
CA-IS3640HW/CA-IS3640HVW
Data-rate of each channel: DR = 100Mbps
IISO=50mA, VDD=4.5V to 5.5V
IISO=0 to 130mA
IISO = 130mA，CLOAD = 0.1μF || 10μF；
VI = VDDI2 (CA-IS36xxL)；VI = 0V (CA-IS36xxH)

Min.
4.75

Typ.
5
130

Max.
5.25

Unit
V

120

110
mA
100

90

80
2
1%

mV/V

53%

VDD(UVLO+)

VDD undervoltage threshold when
2.75
3.05
V
supply voltage is rising
VDD(UVLO-) VDD undervoltage threshold when
2.0
2.35
V
supply voltage is falling
VHYS(UVLO) VDD undervoltage threshold
0.40
V
hysteresis
IIH
High-level input leakage current
VIH=VDDI1 at VIx or Bx or ENx or SEL
20
µA
IIL
Low-level input leakage current
VIL=0V atVIx or Bx or ENx or SEL
–20
µA
VOH
High-level output voltage
IOL=-4mA, see Figure 9-1
VDDO2 – 0.4
VDDO2 – 0.2
VVOL
Low-level output voltage
IOL=4mA, see Figure 9-1
0.2
0.4
V
CMTI
Common-mode transient
VI = VDDI1 or 0V, VCM=1500V, see Figure 9-2
100
150
kV/µs
immunity
VISO(RIP) Output ripple on isolated supply
VISO shorted to GNDB
50
mA
(pk-pk)IISO VISO output current for external load2
60mV
Notes:
1. The maximum VISO output current will be decreased with the data rate increased ta each isolation channel. Also, the available output
current will be reduced when TA > 85˚C, see Figure 8-11. to Figure 8-16. the maximum output current of VISO vs. temperature.
2. VDDI = input side supply; VDDO = output side supply.

5 V Input, 3.3V Output

VDD= VDDL = 5 V ± 10%, TA = -40 to 125°C, SEL shorted to GNDB (over recommended operating conditions, unless otherwise specified)10

Copyright © 2020, Chipanalog
Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

Shanghai Chipanalog Microelectronics Co., Ltd.
VISO

IISO

Parameters
Isolated supply voltage

Test Conditions
IISO = 0 to 130mA
Data-rate of each channel: DR<1Mbps
CA-IS3622LW/CA-IS3622LVW/
CA-IS3622HW/CA-IS3622HVW/
CA-IS3644LW/CA-IS3644LVW/
CA-IS3644HW/CA-IS3644HVW
Data-rate of each channel: DR = 100Mbps
CA-IS3621LW/CA-IS3621LVW/
CA-IS3621HW/CA-IS3621HVW/
CA-IS3643LW/CA-IS3643LVW/
CA-IS3643HW/CA-IS3643HVW
Data-rate of each channel: DR = 100Mbps
CA-IS3620LW/CA-IS3620LVW/
CA-IS3620HW/CA-IS3620HVW/
CA-IS3642LW/CA-IS3642LVW/
CA-IS3642HW/CA-IS3642HVW
Data-rate of each channel: DR = 100Mbps
CA-IS3641LW/CA-IS3641LVW/
CA-IS3641HW/CA-IS3641HVW
Data-rate of each channel: DR = 100Mbps
CA-IS3640LW/CA-IS3640LVW/
CA-IS3640HW/CA-IS3640HVW
Data-rate of each channel: DR = 100Mbps
IISO=50mA, VDD=4.5V to 5.5V
IISO=0 to 130mA

Maximum load current1

VISO（LINE） DC line regulation
VISO（LOAD） DC load regulation
EFF
current
VDD(UVLO+)
when
VDD(UVLO-)
when

Efficiency@maximum

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

load

IISO = 130mA，CLOAD = 0.1μF || 10μF；
VI = VDDI2 (CA-IS36xxL)；VI = 0V (CA-IS36xxH)

Version 1.05 2022/12/19

Min

3.13

Typ
3.3

Max
3.47

130

120

110
mA
100

90

80
2
1%

mV/V

42%

VDD undervoltage threshold
2.75

supply voltage is rising
VDD undervoltage threshold

Unit
V

3.05

V

2.0
2.35
V
supply voltage is falling
0.4
VHYS(UVLO) VDD undervoltage thresholdVhysteresis
IIH
High-level input leakage current VIH=VDDI1 at VIx or Bx or ENx or SEL
20
µA
IIL
Low-level input leakage current VIL=0V atVIx or Bx or ENx or SEL
–20
µA
VOH
High-level output voltage
IOL=-4mA, see Figure 9-1
VDDO2 – 0.4
VDDO2 – 0.2
VVOL
Low-level output voltage
IOL=4mA, see Figure 9-1
0.2
0.4
V
CMTI
Common-mode transient
VI = VDDI1 or 0V, VCM=1500V, see Figure 9-2
100
150
kV/µs
immunity
VISO(RIP) Output ripple on isolated supply
50
VISO shorted to GNDB
mA
(pk-pk)50
IISO VISO output current for external load2mV
Notes:
1.
The maximum VISO output current will be decreased with the data rate increased ta each isolation channel. Also, the available output
current will be reduced when TA > 85˚C, see Figure 8-11. to Figure 8-16. the maximum output current of VISO vs. temperature.
2.
VDDI = input side supply; VDDO = output side supply.

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

11

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644
Version 1.05 2022/12/19
3.3V Input, 3.3 V Output

Shanghai Chipanalog Microelectronics Co., Ltd.

VDD= VDDL = 3.3 V ± 10%, TA = -40 to 125°C, SEL shorted to GNDB (over recommended operating conditions, unless otherwise specified)
VISO

IISO

Parameters
Isolated supply voltage

Maximum load current 1

VISO（LINE） DC line regulation
VISO（LOAD） DC load regulation
EFF

Efficiency@maximum load current

Test Conditions
IISO = 0 to 75mA
Data-rate of each channel: DR<1Mbps
CA-IS3622LW/CA-IS3622LVW/
CA-IS3622HW/CA-IS3622HVW/
CA-IS3644LW/CA-IS3644LVW/
CA-IS3644HW/CA-IS3644HVW
Data-rate of each channel: DR = 100Mbps
CA-IS3621LW/CA-IS3621LVW/
CA-IS3621HW/CA-IS3621HVW/
CA-IS3643LW/CA-IS3643LVW/
CA-IS3643HW/CA-IS3643HVW
Data-rate of each channel: DR = 100Mbps
CA-IS3620LW/CA-IS3620LVW/
CA-IS3620HW/CA-IS3620HVW/
CA-IS3642LW/CA-IS3642LVW/
CA-IS3642HW/CA-IS3642HVW
Data-rate of each channel: DR = 100Mbps
CA-IS3641LW/CA-IS3641LVW/
CA-IS3641HW/CA-IS3641HVW
Data-rate of each channel: DR = 100Mbps
CA-IS3640LW/CA-IS3640LVW/
CA-IS3640HW/CA-IS3640HVW
Data-rate of each channel: DR = 100Mbps
IISO = 50mA, VDD = 3V to 3.6V
IISO = 0 to 75mA
IISO = 75mA, CLOAD = 0.1μF || 10μF；
VI = VDDI2 (CA-IS36xxL);VI = 0V (CA-IS36xxH)

Min
3.13

Typ
3.3
75

Max
3.47

Unit
V

65

60
mA
55

50

45
2
1%

mV/V

47%

VDD(UVLO+)

VDD undervoltage threshold when
2.75
3.05
V
supply voltage is rising
VDD(UVLO-) VDD undervoltage threshold when
2.1
2.35
V
supply voltage is falling
VHYS(UVLO) VDD undervoltage threshold
0.4
V
hysteresis
IIH
High-level input leakage current
VIH = VDDI2@ VIx or SEL
20
µA
IIL
Low-level input leakage current
VIL = 0V @ VIx or SEL
–20
µA
VOH
High-level output voltage
IOL=-4mA, see Figure 9-1
VDDO2 – 0.4 VDDO2 – 0.2
VVOL
Low-level output voltage
IOL=4mA, see Figure 9-1
0.2
0.4
V
CMTI
Common-mode transient
VI = VDDI1 or 0V, VCM=1500V, see Figure 9-2
100
150
kV/µs
immunity
VISO(RIP) Output ripple on isolated supply
VISO shorted to GNDB
36
mA
(pk-pk)IISO VISO output current for external load245mV
Notes:
1.
The maximum VISO output current will be decreased with the data rate increased ta each isolation channel. Also, the available output
current will be reduced when TA > 85˚C, see Figure 8-11. to Figure 8-16. the maximum output current of VISO vs. temperature.
2.
VDDI = input side supply; VDDO = output side supply.

12

Copyright © 2020, Chipanalog
Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

Shanghai Chipanalog Microelectronics Co., Ltd.
8.9
Supply Current Characteristics
5 V Input, 5 V Output

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

VDD = VDDL = 5 V ± 10%, TA = -40 to 125°C, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)Parameters
Test Conditions
Min
Typ
Max
CA-IS3620
No external ILOAD; VI=0V (CA-IS3620H); VI=VDDI1 (CA-IS3620L)
1218
1
No external ILOAD; VI=0V (CA-IS3620L); VI=VDDI (CA-IS3620H)
1015
All channels input 1Mbps, 50% duty cycle square wave clock signal,
1218
CL=15pF each channel, no external ILOAD.
IDD2Supply current
All channels input 10Mbps, 50% duty cycle square wave clock signal,
24
36
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
56
84
CL=15pF each channel, no external ILOAD.
CA-IS3621
No external ILOAD; VI =0V (CA-IS3621H); VI=VDDI1 (CA-IS3621L)
13
19
No external ILOAD; VI =0V (CA-IS3621L); VI=VDDI1 (CA-IS3621H)
9
14
All channels input 1Mbps, 50% duty cycle square wave clock signal,
11
17
CL=15pF each channel, no external ILOAD.
IDD2Supply current
All channels input 10Mbps, 50% duty cycle square wave clock signal,
23
35
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
42
63
CL=15pF each channel, no external ILOAD.
CA-IS3622
No external ILOAD; VI=0V (CA-IS3622H); VI=VDDI1 (CA-IS3622L)
14
20
No external ILOAD; VI=0V (CA-IS3622L); VI=VDDI1 (CA-IS3622H)
9
14
All channels input 1Mbps, 50% duty cycle square wave clock signal,
914
CL=15pF each channel, no external ILOAD.
IDD2Supply current
All channels input 10Mbps, 50% duty cycle square wave clock signal,
20
30
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
30
45
CL=15pF each channel, no external ILOAD.
CA-IS3640
No external ILOAD; VI=0V (CA-IS3640H); VI=VDDI1 (CA-IS3640L)
1726
No external ILOAD; VI=0V (CA-IS3640L); VI=VDDI1 (CA-IS3640H)
13
20
All channels input 1Mbps, 50% duty cycle square wave clock signal,
16
24
CL=15pF each channel, no external ILOAD.
IDD2Supply current
All channels input 10Mbps, 50% duty cycle square wave clock signal,
22
33
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
76
115
CL=15pF each channel, no external ILOAD.
Notes:
1. VDDI = input side supply; VDDO = output side supply.
2. For the CA-IS36xxVW, the IDD is the total supply current from VDD and VDDL.

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

Unit

mA

mA

mA

mA

13

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19
Supply Current Characteristics Continued (5 V Input, 5 V Output)
CA-IS3641

IDD2

Parameters

Test Conditions

Supply current

No external ILOAD; VI=0V (CA-IS3641H); VI=VDDI1 (CA-IS3641L)
No external ILOAD; VI=0V (CA-IS3641L); VI=VDDI1 (CA-IS3641H)
All channels input 1Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 10Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.

CA-IS3642

IDD2

Supply current

CA-IS3643

IDD2

Supply current

CA-IS3644

IDD2

Shanghai Chipanalog Microelectronics Co., Ltd.

Supply current

Min

No external ILOAD; VI =0V (CA-IS3642H); VI=VDDI1 (CA-IS3642L)
No external ILOAD; VI =0V (CA-IS3642L); VI=VDDI1 (CA-IS3642H)
All channels input 1Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 10Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
No external ILOAD; VI=0V (CA-IS3643H); VI=VDDI1 (CA-IS3643L)
No external ILOAD; VI=0V (CA-IS3643L); VI=VDDI1 (CA-IS3643H)
All channels input 1Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 10Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
No external ILOAD; VI=0V (CA-IS3644H); VI=VDDI1 (CA-IS3644L)
No external ILOAD; VI=0V (CA-IS3644L); VI=VDDI1 (CA-IS3644H)
All channels input 1Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 10Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.

Typ

Max

19
13

29
20

16

24

22

33

66

99

18
13

27
20

15

23

20

30

62

93

18
13

27
20

16

24

20

30

62

93

18
13

27
20

14

21

17

26

45

68

Unit

mA

mA

mA

mA

Notes:
1. VDDI = input side supply; VDDO = output side supply.
2. For the CA-IS36xxVW, the IDD is the total supply current from VDD and VDDL.

14

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Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

Shanghai Chipanalog Microelectronics Co., Ltd.
5 V Input, 3.3 V Output

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

VDD= VDDL= 5 V ± 10%, TA = -40 to 125°C, SEL shorted to GNDB (over recommended operating conditions, unless otherwise specified)Parameters
Test Conditions
Min
Typ
Max
CA-IS3620
No external ILOAD; VI=0V (CA-IS3620H); VI=VDDI1 (CA-IS3620L)
11
17
No external ILOAD; VI=0V (CA-IS3620L); VI=VDDI1 (CA-IS3620H)
914
All channels input 1Mbps, 50% duty cycle square wave clock signal,
1015
CL=15pF each channel, no external ILOAD.
IDD2Supply current
All channels input 10Mbps, 50% duty cycle square wave clock signal,
18
27
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
34
51
CL=15pF each channel, no external ILOAD.
CA-IS3621
No external ILOAD; VI =0V (CA-IS3621H); VI=VDDI1 (CA-IS3621L)
12
18
No external ILOAD; VI =0V (CA-IS3621L); VI=VDDI1 (CA-IS3621H)
9
14
All channels input 1Mbps, 50% duty cycle square wave clock signal,
914
CL=15pF each channel, no external ILOAD.
IDD2Supply current
All channels input 10Mbps, 50% duty cycle square wave clock signal,
16
24
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
32
48
CL=15pF each channel, no external ILOAD.
CA-IS3622
No external ILOAD; VI=0V (CA-IS3622H); VI=VDDI1 (CA-IS3622L)
14
21
No external ILOAD; VI=0V (CA-IS3622L); VI=VDDI1 (CA-IS3622H)
9
14
All channels input 1Mbps, 50% duty cycle square wave clock signal,
7
11
CL=15pF each channel, no external ILOAD.
IDD2Supply current
All channels input 10Mbps, 50% duty cycle square wave clock signal,
14
21
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
30
45
CL=15pF each channel, no external ILOAD.
CA-IS3640
No external ILOAD; VI=0V (CA-IS3640H); VI=VDDI1 (CA-IS3640L)
15
23
No external ILOAD; VI=0V (CA-IS3640L); VI=VDDI1 (CA-IS3640H)
11
18
All channels input 1Mbps, 50% duty cycle square wave clock signal,
13
19
CL=15pF each channel, no external ILOAD.
IDD2Supply current
All channels input 10Mbps, 50% duty cycle square wave clock signal,
17
26
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
50
75
CL=15pF each channel, no external ILOAD.
Notes:
1. VDDI = input side supply; VDDO = output side supply, VISO.
2. For the CA-IS36xxVW, the IDD is the total supply current from VDD and VDDL.

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

Unit

mA

mA

mA

mA

15

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19
Supply Current Characteristics Continued (5 V Input, 3.3 V Output)
CA-IS3641

IDD2

Parameters

Test Conditions

Supply current

No external ILOAD; VI=0V (CA-IS3641H); VI=VDDI1 (CA-IS3641L)
No external ILOAD; VI=0V (CA-IS3641L); VI=VDDI1 (CA-IS3641H)
All channels input 1Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 10Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.

CA-IS3642

IDD2

Supply current

CA-IS3643

IDD2

Supply current

CA-IS3644

IDD2

Shanghai Chipanalog Microelectronics Co., Ltd.

Supply current

Min

No external ILOAD; VI =0V (CA-IS3642H); VI=VDDI1 (CA-IS3642L)
No external ILOAD; VI =0V (CA-IS3642L); VI=VDDI1 (CA-IS3642H)
All channels input 1Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 10Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
No external ILOAD; VI=0V (CA-IS3643H); VI=VDDI1 (CA-IS3643L)
No external ILOAD; VI=0V (CA-IS3643L); VI=VDDI1 (CA-IS3643H)
All channels input 1Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 10Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
No external ILOAD; VI=0V (CA-IS3644H); VI=VDDI1 (CA-IS3644L)
No external ILOAD; VI=0V (CA-IS3644L); VI=VDDI1 (CA-IS3644H)
All channels input 1Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 10Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.

Typ

Max

16
11

24
18

13

20

16

24

47

71

16
11

24
18

13

20

16

24

46

69

16
11

24
18

13

20

15

23

44

66

16
11

24
18

13

20

15

23

43

66

Unit

mA

mA

mA

mA

Notes:
1. VDDI = input side supply; VDDO = output side supply, VISO.
2. For the CA-IS36xxVW, the IDD is the total supply current from VDD and VDDL.

16

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Shanghai Chipanalog Microelectronics Co., Ltd.

Shanghai Chipanalog Microelectronics Co., Ltd.
3.3 V Input, 3.3 V Output

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

VDD= VDDL = 3.3 V ± 10%, TA = -40 to 125°C, SEL shorted to GNDB (over recommended operating conditions, unless otherwise specified)Parameters
Test Conditions
Min
Typ
Max
CA-IS3620
No external ILOAD; VI=0V (CA-IS3620H); VI=VDDI1 (CA-IS3620L)
10
15
No external ILOAD; VI=0V (CA-IS3620L); VI=VDDI1 (CA-IS3620H)
8
12All channels input 1Mbps, 50% duty cycle square wave clock signal,
11
17
CL=15pF each channel, no external ILOAD.
IDD2Supply current
All channels input 10Mbps, 50% duty cycle square wave clock signal,
19
29
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
40
60
CL=15pF each channel, no external ILOAD.
CA-IS3621
No external ILOAD; VI =0V (CA-IS3621H); VI=VDDI1 (CA-IS3621L)
12
18
No external ILOAD; VI =0V (CA-IS3621L); VI=VDDI1 (CA-IS3621H)
8
12
All channels input 1Mbps, 50% duty cycle square wave clock signal,
1015
CL=15pF each channel, no external ILOAD.
IDD2Supply current
All channels input 10Mbps, 50% duty cycle square wave clock signal,
18
27
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
31
46
CL=15pF each channel, no external ILOAD.
CA-IS3622
No external ILOAD; VI=0V (CA-IS3622H); VI=VDDI1 (CA-IS3622L)
14
21
No external ILOAD; VI=0V (CA-IS3622L); VI=VDDI1 (CA-IS3622H)
8
12
All channels input 1Mbps, 50% duty cycle square wave clock signal,
914
CL=15pF each channel, no external ILOAD.
IDD2Supply current
All channels input 10Mbps, 50% duty cycle square wave clock signal,
16
24
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
21
32
CL=15pF each channel, no external ILOAD.
CA-IS3640
No external ILOAD; VI=0V (CA-IS3640H); VI=VDDI1 (CA-IS3640L)
16
24
No external ILOAD; VI=0V (CA-IS3640L); VI=VDDI1 (CA-IS3640H)
12
18
All channels input 1Mbps, 50% duty cycle square wave clock signal,
15
23
CL=15pF each channel, no external ILOAD.
IDD2Supply current
All channels input 10Mbps, 50% duty cycle square wave clock signal,
18
27
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
57
86
CL=15pF each channel, no external ILOAD.
Note:
1. VDDI = input side supply; VDDO = output side supply, VISO.
2. For the CA-IS36xxVW, the IDD is the total supply current from VDD and VDDL.

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

Unit

mA

mA

mA

mA

17

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19
Supply Current Characteristics Continued (3.3 V Input, 3.3 V Output)
CA-IS3641

IDD2

Parameters

Test Conditions

Supply current

No external ILOAD; VI=0V (CA-IS3641H); VI=VDDI1 (CA-IS3641L)
No external ILOAD; VI=0V (CA-IS3641L); VI=VDDI1 (CA-IS3641H)
All channels input 1Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 10Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.

CA-IS3642

IDD2

Supply current

CA-IS3643

IDD2

Supply current

CA-IS3644

IDD2

Shanghai Chipanalog Microelectronics Co., Ltd.

Supply current

Min

No external ILOAD; VI =0V (CA-IS3642H); VI=VDDI1 (CA-IS3642L)
No external ILOAD; VI =0V (CA-IS3642L); VI=VDDI1 (CA-IS3642H)
All channels input 1Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 10Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
No external ILOAD; VI=0V (CA-IS3643H); VI=VDDI1 (CA-IS3643L)
No external ILOAD; VI=0V (CA-IS3643L); VI=VDDI1 (CA-IS3643H)
All channels input 1Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 10Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
No external ILOAD; VI=0V (CA-IS3644H); VI=VDDI1 (CA-IS3644L)
No external ILOAD; VI=0V (CA-IS3644L); VI=VDDI1 (CA-IS3644H)
All channels input 1Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 10Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.
All channels input 100Mbps, 50% duty cycle square wave clock signal,
CL=15pF each channel, no external ILOAD.

Typ

Max

16
12

24
18

15

23

18

27

50

75

17
12

25
18

14

21

17

26

46

69

18
12

27
18

14

21

16

24

40

60

18
12

27
18

14

21

16

24

36

54

Unit

mA

mA

mA

mA

Notes:
1. VDDI = input side supply; VDDO = output side supply, VISO.
2. For the CA-IS36xxVW, the IDD is the total supply current from VDD and VDDL.

18

Copyright © 2020, Chipanalog
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Shanghai Chipanalog Microelectronics Co., Ltd.

Shanghai Chipanalog Microelectronics Co., Ltd.
8.10 Timing Characteristics
5 Input, 5V Output

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

VDD = VDDL= 5 V ± 10%, TA = -40 to 125°C, SEL shorted to VISO (over recommended operating conditions, unless otherwise specified)Parameters
Test Conditions
Min
Typ
Max
Unit
DR
Data rate
0
150
Mbps
PWminL
Minimum Pulse Width
5.0
nstPLH, tPHL
Propagation Delay Time
10.0
20.0
ns
See Figure 9-1
PWD
Pulse Width Distortion |tPLH - tPHL|
0.2
4.5
ns
trk(o)
Channel-to-channel Output Skew Time1
See Figure 9-1
0.4
2.5
ns
trk(pp)Chip-to-chip skew time2
2.0
4.5
ns
tr
Output Signal Rise Time
See Figure 9-1
2.5
4.0
ns
tf
Output Signal Fall Time
See Figure 9-1
2.5
4.0
ns
Notes:
1. tsk is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction
while driving identical loads.
2. trk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.

5 V Input, 3.3 V Output

VDD= VDDL=5 V ± 10%, TA = -40 to 125°C, SEL shorted to GNDB (over recommended operating conditions, unless otherwise specified)Parameters
Test Conditions
Min
Typ
Max
Unit
DR
Data rate
0
150
Mbps
PWminL
Minimum Pulse Width
5.0
nstPLH, tPHL
Propagation Delay Time
10.0
20.0
ns
See Figure 9-1
PWD
Pulse Width Distortion |tPLH - tPHL|
0.2
4.5
ns
trk(o)
Channel-to-channel Output Skew Time1
See Figure 9-1
0.4
2.5
ns
trk(pp)Chip-to-chip skew time2
2.0
4.5
ns
tr
Output Signal Rise Time
See Figure 9-1
2.5
4.0
ns
tf
Output Signal Fall Time
See Figure 9-1
2.5
4.0
ns
Notes:
3.
tsk is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
4.
trk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.

3.3 V Input, 3.3 V Output

VDD= VDDL= 3.3 V ± 10%, TA = -40 to 125°C, SEL shorted to GNDB (over recommended operating conditions, unless otherwise specified)Parameters
Test Conditions
Min
Typ
Max
Unit
DR
Data rate
0
150
Mbps
PWminL
Minimum Pulse Width
5.0
nstPLH, tPHL
Propagation Delay Time
10.0
20.0
ns
See Figure 9-1
PWD
Pulse Width Distortion |tPLH - tPHL|
0.2
4.5
ns
trk(o)
Channel-to-channel Output Skew Time1
See Figure 9-1
0.4
2.5
ns
trk(pp)Chip-to-chip skew time2
2.0
4.5
ns
tr
Output Signal Rise Time
See Figure 9-1
2.5
4.0
ns
tf
Output Signal Fall Time
See Figure 9-1
2.5
4.0
ns
Notes:
1.
tsk is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
2.
trk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

19

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644
Version 1.05 2022/12/19
8.11 Typical Characteristics

Shanghai Chipanalog Microelectronics Co., Ltd.

Quiescent Current (mA)

VDD=5V,VISO=5V

16
12
8

IDD_VI=L

IDD_VI=H4
0-40 -20

0

20

40

60

80

Operating Current (mA)

60
20

VDD=5V,VISO=5V

50
40

1Mbps

10
0

-40 -2012
8

0

IDD_VI=H-40 -20

0

20

IDD_VI=L
40

60

80

100 12550

30
20

IDD_VI=L4
0-60 -40 -20

0

20

40

60

80 100 125

Temperature (℃)
Figure 8-5. VDD quiescent current, all inputs connected to logic HIGH
or logic LOW, VDD = 3.3V，VISO = 3.3V

20

VDD=5V,VISO=3.3V

10Mbps100Mbps

1Mbps

10
0

60

动态电流（mA）

Quiescent Current (mA)IDD_VI=H

100 125-40 -20

0

20

40

60

80

100 125

Figure 8-4. VDD supply current for the CA-IS3641HW at different data
rate ; VDD = 5V，VISO = 3.3V

VDD=3.3V,VISO=3.3V

12
8

80

Temperature (℃)

Figure 8-3. VDD quiescent current, all inputs connected to logic HIGH or
logic LOW, VDD = 5V，VISO = 3.3V

16

60

40

Temperature (℃)

20

40

60

VDD=5V,VISO=3.3V

4

20

Figure 8-2. VDD supply current for the CA-IS3641HW at different data
rate ; VDD = 5V, VISO = 5V

Operating Current (mA)

Quiescent Current (mA)

160

Temperature (℃)

Temperature (℃)

20

100Mbps20

100 125

Figure 8-1. VDD quiescent current, all inputs connected to logic HIGH or
logic LOW, VDD = 5V，VISO = 5V

10Mbps30

50

VDD=3.3V,VISO=3.3V

40
30
20

10Mbps100Mbps

1Mbps

10
0

-60 -40 -20

0

20

40

60

80 100 125

Temperature (℃)
Figure 8-6. VDD supply current for the CA-IS3641HW at different data
rate ; VDD = 3.3V，VISO = 3.3V

Copyright © 2020, Chipanalog
Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

Shanghai Chipanalog Microelectronics Co., Ltd.

0.5

5Vo output voltage（V）

Vo outpu voltage（V）

6

4
3
2
VDD=5V,VISO=5V

1

VDD=5V,VISO=3.3V

0-40 -20

0

20

40

60

80

VDD=5V,VISO=5V
0.4
VDD=5V,VISO=3.3V
0.3
0.2
0.1
0.0

-40 -20100 125

Figure 8-7. VO = High, pull-down current = 4mA

tPHL

6
3
0

-40 -20

0

20

40

60

80

100 125

Propagation delay（ns）

Propagation delay （ns）

12
tPLH

80

100 125

12
tPLH

9

tPHL

6
3
0

-40 -20

0

20

40

60

80

100 125

Temperature (℃)

Figure 8-9. Propagation delay time vs. temperature,
VDD = 5V，VISO = 5V

Figure 8-10. Propagation delay time vs. temperature,
VDD = 3.3V，VISO = 3.3V

140

120

DR<1Mbps

100
80
60
40

VDD=5V,VISO=5V和VDD=5V,VISO=3.3V

20

VDD=3.3,VISO=3.3V
-40

-20

0

20

40

60

85

105 125 145

Temperature (℃)
Figure 8-11.
All of CA-IS36xx devices
Maximum output current from VISO vs. temperature
DR < 1Mbps

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

VISO load current IISO（mA）

140
VISO load current IISO（mA）

60

VDD=3.3V,VISO=3.3V

Temperature (℃)

040

Figure 8-8. VO = Low, pull-up current = 4mA
15

VDD=5V,VISO=5V

920

Temperature (℃)

Temperature (℃)

15

0

120

DR=100Mbps

100
80
60
40

VDD=5V,VISO=5V和VDD=5V,VISO=3.3V

200

VDD=3.3,VISO=3.3V
-40

-20

0

20

40

60

85

105 125 145

Temperature (℃)
Figure 8-12.
CA-IS3621LW/CA-IS3621LVW/CA-IS3621HW/CA-IS3621HVW/
CA-IS3643LW/CA-IS3643LVW/CA-IS3643HW/CA-IS3643HVW
Maximum output current from VISO vs. temperature
DR = 100Mbps

21

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644
140
120
100
80
60
40
20
0

VDD=5V,VISO=5V和VDD=5V,VISO=3.3V
VDD=3.3,VISO=3.3V

DR=100Mbps
-40

-20

0

20

40

60

85

105 125 145

Shanghai Chipanalog Microelectronics Co., Ltd.
VISO load current IISO（mA）

VISO load current IISO（mA）

Version 1.05 2022/12/19

140
120
100
80
60
40
20
0

Temperature(℃)

VDD=3.3,VISO=3.3V

100
80
60
40

DR=50Mbps

20
0

-40

-20

0

20

40

60

85

DR=100Mbps
-40

-20

0

20

40

60

105 125 145

Temperture(℃)
Figure 8-15.
CA-IS3641LW/CA-IS3641LVW/CA-IS3641HW/CA-IS3641HVW
Maximum output current from VISO vs. temperature
DR = 100Mbps

105 125 145

140
VDD=5V,VISO=5V和VDD=5V,VISO=3.3V

120
100
80
60
40
20
0

DR=100Mbps-40 -200

20 40 60 85 105 125 145
Temperture (℃)

Figure 8-16.
CA-IS3640LW/CA-IS3640LVW/CA-IS3640HW/CA-IS3640HVW
Maximum output current from VISO vs. temperature
DR = 100Mbps

VISO

20mV/div

20mV/div

VISO

85

Figure 8-14.
CA-IS3620LW/CA-IS3620LVW/ CA-IS3620HW/CA-IS3620HVW/
CA-IS3642LW/CA-IS3642LVW/CA-IS3642HW/CA-IS3642HVW
Maximum output current from VISO vs. temperature
DR = 100Mbps

VISO load current IISO(mA)

VISO load current IISO（mA）

VDD=5V,VISO=5V和VDD=5V,VISO=3.3V

120

VDD=3.3,VISO=3.3V

Temperature (℃)

Figure 8-13.
CA-IS3621LW/CA-IS3621LVW/CA-IS3621HW/CA-IS3621HVW/
CA-IS3643LW/CA-IS3643LVW/CA-IS3643HW/CA-IS3643HVW
Maximum output current from VISO vs. temperature
DR = 100Mbps

140

VDD=5V,VISO=5V和VDD=5V,VISO=3.3V

130mA

100mA/div

IISO
5μs/div
Figure 8-17. VDD = 5V, VISO = 5.0V, IISO = 130mA;
VISO ripple voltage @ 130mA load current: 58mV

22

IISO

13mA

100mA/div

120μs/div
Figure 8-18. VDD = 5V, VISO = 5V, 13mA to 130mA load transient
response; VISO ripple voltage (pick to pick): 68mV

Copyright © 2020, Chipanalog
Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

Shanghai Chipanalog Microelectronics Co., Ltd.

VISO

VISO

20mV/div

20mV/div

130mA

IISO

100mA/div

IISO

13mA

5μs/div

100mA/div

120μs/div

Figure 8-19. VDD = 5V, VISO = 3.3V, IISO = 130mA; VISO ripple voltage @130mA load current: 51mV

Figure 8-20. VDD = 5V, VISO = 3.3V, 13mA to 130mA load transient
response; VISO ripple voltage (pick to pick): 58mV

VISO
VISO

20mV/div

20mV/div

75mA
IVISO

100mA/div

IVISO

7.5mA
120μs/div

5μs/div
Figure 8-21. VDD = 3.3V, VISO = 3.3V, IISO = 130mA
VISO ripple voltage @ 75mA load current: 40mV

Figure 8-22. VDD = 3.3V, VISO = 3.3V, 7.5mA to 75mA load transient
response; VISO ripple voltage (pick to pick): 42mV
60%

VDD=5V，VISO=5V

60%

VDD=5V，VISO=3.3V

50%

50%

40%

40%

30%

30%

20%

20%
-40℃

10%
0%

100mA/div

0

25℃

85℃

10 20 30 40 50 60 70 80 90 100 110 120 130

VISO load current (mA)
Figure 8-23. Efficiency vs. load current (IISO) at different ambient
temperature, VDD = 5V，VISO = 5V

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

10%
0%
-10%

-40℃
0

25℃

85℃

10 20 30 40 50 60 70 80 90 100 110 120 130

VISO load current (mA)
Figure 8-24. Efficiency vs. load current (IISO) at different ambient
temperature, VDD = 5V，VISO = 3.3V

23

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644
Version 1.05 2022/12/19
60%

Shanghai Chipanalog Microelectronics Co., Ltd.

VDD=3.3V，VISO=3.3V

50%
40%
30%
20%
-40℃

10%
0%

0

10

20

30

25℃

40

50

85℃

60

70

75

VISO load current (mA)
Figure 8-25. Efficiency vs. load current (IISO) at different ambient
temperature, VDD = 3.3V，VISO = 3.3V

24

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Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

Isolation Barrier

Shanghai Chipanalog Microelectronics Co., Ltd.
9 Parameter Measurement Information

IN

VIN1

OUT

VIN

VOUT

50%

50%

tPLH

tPHL

CL2

50Ω

90%

VOUT

50%

50%
10%
tf

tr

Notes:

1. A square wave generator provide VIN input signal with characteristics of frequency ≤100kHz, 50% duty cycle, tr≤3ns, tf≤3ns, Zout = 50Ω. At the
input, 50 Ω resistor is required to terminate input generator signal. It is not needed in actual application.
2. CL = 15pF, includes external circuit (instrumentation and fixture etc.) capacitance. Since the load capacitance influence the output rising time, it’sa key factor in the timing characteristic measurement.

Figure 9-1. Timing Characteristics Test Circuit and Voltage Waveforms

IN

CBP4

VDDO

Isolation Barrier

VDDI

OUT

VOUT3
CBP4
CL2

GNDA

High
Voltage
Surge
Generator1

GNDB

Notes:
1.

2.
3.
4.

The High Voltage Surge Generator generates repetitive high voltage surges with > 1.5kV amplitude, rise time <10ns and fall time <10ns, toreach common-mode transient noise with > 150kV/μs slew rate.
CL = 15pF and includes external circuit (instrumentation and fixture etc.) capacitance.
Pass-fail criteria: the output must remain stable.
CBP (0.1 ~ 1uF) is bypass capacitance.

Figure 9-2. Common-Mode Transient Immunity Test Circuit

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

25

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644
Version 1.05 2022/12/19
10 Detailed Description

Shanghai Chipanalog Microelectronics Co., Ltd.

10.1 Overview
The CA-IS36xx family of devices integrates most of the components needed for digital isolation application, a highefficiency, low-emissions isolated DC-DC converter with internal transformer and high-speed isolated data channels, into asingle, compact SOIC package. This results an efficient and compact fully integrated solution that complies with EMI
requirements and makes system level design as easy as possible.
The CA-IS36xx family of devices offers dual-channel and four-channel digital galvanic isolators using Chipanalog’s fulldifferential capacitive isolation technology. These devices have an ON-OFF keying (OOK) modulation scheme to transfer digital
signals across the SiO2 based isolation barrier between circuits with different power domains. The transmitter sends a highfrequency carrier across the barrier to represent one digital state and sends no signal to represent the another digital state.
The receiver demodulates the signal and recovery input signal at output through a buffer stage. With this OOK architecture,
CA-IS36xx family of devices build a robust data transmission path between different power domains, without any special startup initialization requirements. These devices also incorporate advanced full differential techniques to maximize the CMTI
performance and minimize the radiated emissions due to the high frequency carrier and I/O buffer switching.
The internal DC-DC converter uses switched mode operation and proprietary PWM feedback circuit techniques to provide
high efficiency and low radiated emissions. Undervoltage lockout (UVLO) with hysteresis is integrated on the VDD supply which
ensures robust system performance under noisy conditions. An integrated soft-start mechanism ensures controlled inrush
current and avoids any overshoot on the output during power up.

10.2 Functional Block Diagram
The functional block diagram of CA-IS36xx devices is shown in Figure 10-1. The simplified functional block diagram of atypical signal isolation channel and a conceptual OOK operation waveform are shown in Figure 10-2 and Figure 10-3. Eachchannel of the CA-IS36xx is unidirectional, only passes data in one direction as indicated in the functional diagram andoperates independently with guaranteed data rates from DC up to 150Mbps.
VDD

TRANSFORMER
VISOTransformer
DriverPower
Controller

Frequency
Controller

I/O_A1

Data Channel

I/O_A2

Data Channel

I/O_A3
I/O_A4GNDA

ISOLATION BARRIERUVLO, Soft-start,
Thermal Shut down

Rectifier

VFB

UVLO, Soft-start

Feedback
Controller

VREF

Data Channel

I/O_B1

Data Channel

I/O_B2

Data Channel

Data Channel

I/O_B3

Data Channel

Data Channel

I/O_B4

GNDB

Figure 10-1. Functional Block Diagram of CA-IS36xx Devices

26

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Shanghai Chipanalog Microelectronics Co., Ltd.

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

Shanghai Chipanalog Microelectronics Co., Ltd.

Schmitt
Trigger
VIN

Receiver (RX)ISOLATION BARRIER

Transmitter (TX)

Modulator

RF Carrier
Generator

DriverVOUT

Demodulator

EN

Figure 10-2. Functional Block Diagram of a Single Channel

VIN
Signal throughisolation barrier

VOUT
Figure 10-3. Operation Waveforms of a Single Channel

10.3 Undervoltage Protection
Below two tables show CA-IS36xxW and CA-IS36xxVW channel output in different supply configuration.
Table 10-1. CA-IS36xxW Channel Output in Different Supply Configuration
VDD (V)A side OUTPUT

B side OUTPUT

PD

High-Z

High-Z

PU

NormalNormalTable 10-2. CA-IS36xxVW Channel Output in Different Supply Configuration
VDD (V)VDDL (V)A side OUTPUT

B side OUTPUT

PD

PD

High-Z

High-Z

PD

PU

High-Z

PU
PU

PD
PU

High-Z
NormalHigh-Z
NormalNormalNote: PU = Power up (VDD/L ≥ VDD(UVLO+)); PD = Power down(VDD/L ≤VDD(UVLO-))
10.4 Isolated Supply Output
The integrated isolated DC-DC converter based on PWM control structure provides up to 650mW of isolated power anddifferent output voltage configurations. The VDD supply is provided to the primary of power controller that switches the powerstage connected to the integrated high-Q transformer. The output voltage VISO is monitored and a PWM signal based on
feedback information is conveyed to the supply primary side through a dedicated isolation channel, the PWM duty cycle of the
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CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19
Shanghai Chipanalog Microelectronics Co., Ltd.
primary switching stage is adjusted accordingly. Power is transferred to the secondary side of transformer, internal rectified
and regulated to either 3.3 V or 5 V, depending on the SEL pin status, see Table 10-3 for the supply configurations of CA-IS36xx
devices. The maximum output current from VISO is shown as Table 10-4. Note that the IISO value in Table 10-4 is the maximum
output current at +25°C. With the increase of temperature, especially when the temperature exceeds +85°C, the maximum
load current will be decreased, see more details from Figure 8-11. to Figure 8-16.
Table 10-3. Supply Configuration
SEL INPUT
Shorted to VISO
Shorted to GNDB or floating
Shorted to GNDB or floating

VDD
5V
5V
3.3 V 1

VISO
5V
3.3V
3.3V 2

Notes:1.
VDD = 3.3 V, SEL shorted to VISO (essentially VISO = 5 V) is not recommended.
2.
The SEL pin has a weak pull-down internally. However, for VISO = 3.3 V, the SEL pin should be connected to the GNDB externally, especiallyin the noisy system.

Table 10-4. Maximum Output Current of VISO @ TA = 25°C
Supply Voltage
VDD (V)
4.5~5.5

5V or 3.3V

3.15~3.6
4.5~5.5

3.3V
5V or 3.3V

3.15~3.6
4.5~5.5
3.15~3.6
4.5~5.5
3.15~3.6
4.5~5.5
3.15~3.6
4.5~5.5
3.15~3.6

3.3V
5V or 3.3V
3.3V
5V or 3.3V
3.3V
5V or 3.3V
3.3V
5V or 3.3V
3.3V

VISO (V)Part Number

Data Rate (bps)

CA-IS36xx<1M

CA-IS3622LW/CA-IS3622LVW/ CA-IS3622HW/CA-IS3622HVW/
CA-IS3644LW/CA-IS3644LVW/CA-IS3644HW/CA-IS3644HVW

100M

CA-IS3621LW/CA-IS3621LVW/ CA-IS3621HW/CA-IS3621HVW/
CA-IS3643LW/CA-IS3643LVW/CA-IS3643HW/CA-IS3643HVW
CA-IS3620LW/CA-IS3620LVW/ CA-IS3620HW/CA-IS3620HVW/
CA-IS3642LW/CA-IS3642LVW/CA-IS3642HW/CA-IS3642HVW
CA-IS3641LW/CA-IS3641LVW/ CA-IS3641HW/CA-IS3641HVW
CA-IS3640LW/CA-IS3640LVW/CA-IS3640HW/CA-IS3640HVW

100M
100M
100M
100M

IISO (mA)
130
75
120
65
110
60
100
55
90
50
80
45

10.5 Operation Modes
Table 10-5 lists the operation modes for the CA-IS36xx devices.
Table 10-5. Operation Mode1
VDD1

PU

INPUT(VIx)
H
L
Open

OUTPUT (VOx)H
L
Default

OPERATION
Normal operation mode:
A channel output follows the logic state of its input.
Default output mode:
When input VIx is open, the corresponding channel output goes to its default logic state.
Default is High for CA-IS36xxH and Low for CA-IS36xxL.
If the VDD is unpowered, a channel output is undetermined.

PD
X
Undetermined 2
Notes:1.
VDD = Input-side power supply; PU = Powered up (VDD ≥ 3.15 V); PD = Powered down (VDD ≤ 2.0 V); X = Don't care; H = High level; L = Low
level.
2.
The outputs are in undetermined state when VDD < 2.0V.

28

Copyright © 2020, Chipanalog
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Shanghai Chipanalog Microelectronics Co., Ltd.

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

Shanghai Chipanalog Microelectronics Co., Ltd.
11 Application and Implementation

11.1 Typical Application
The CA-IS36xx isolation ICs provide complete galvanic isolation between two power domains, protecting circuits fromhigh common-mode transients and faults, eliminating ground loops. In many applications, digital isolators are replacing
optocouplers because they can reduce the power requirements and take up less board space while offering the same isolation
capability. Unlike optocouplers, which require external components to improve performance, provide bias, or limit current, the
CA-IS36xx devices integrated both signal and power isolation, only require few external bypass capacitors to operate, and savean external isolated power supply on side-B, help designers to simplify system-level design and reduces board area. These
devices are ideal for applications that have limited board space and desire more integration. Figure 11-1 shows typicaloperating circuit of the CA-IS3642; Figure 11-2 is the typical schematic of CA-IS3641 in SPI isolation application.
10uF

10uF

CA-IS3642
0.1 uF

0.1 uF2mm maximum from VDDA

2mm maximum from VDDB

VDD

VISO

IN1

VI1

TX

IN2

VI2

TX

OUT3

VO3

RX

OUT4

VO4

RX

NC

ISOLATION BARRIER

GNDA

GNDB

RX

VO1

OUT1

RX

VO2

OUT2

TX

VI3

IN3

TX

VI4

IN4

SEL

GNDA

GNDB

Figure 11-1. Typical Application Circuit of CA-IS3642

CA-IS3641
3.3V VIN
VISO

VDD
22uF

0.1uF

CS

INA

SCLK

INB

MCU

SDO
SDI

INC
OUTD

DGND
GNDA

ISOLATION BARRIER

DVDD

0.1uF

REF

47uF

AVDD

OUTA

CS

OUTB

SCLK

DVDD

ADC
OUTC

SDO

IND

SDI
AGND

Analog
Input

DGND

SEL
GNDB

Figure 11-2. CA-IS3641 provides SPI isolation and isolated power for ADC

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CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19
Shanghai Chipanalog Microelectronics Co., Ltd.
The CA-IS36xx family devices do not require special power supply sequencing. The logic levels are set independently oneither side by VDD/VDDL (side-A) and VISO (side-B). When designing with digital isolators, keep in mind that because of the singleended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating
single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, MCU or
FPGA), and a data converter or a line transceivers etc., regardless of the interface type or standard. The PCB designer should
follow some critical recommendations in order to get the best performance from the design, especially for the high-speed
operating digital circuit boards, see PCB Layout Guidelines section.

11.2 PCB Layout Guidelines
High switching frequencies and large peak currents make PCB layout very important for the digital isolators with internal
DC-DC converter. Good PCB design minimizes excessive electromagnetic interference (EMI) and voltage gradients in the groundplane to avoid instability and regulation errors. Even with the high level of integration design, users may fail to achieve
specified operation with a poor layout. So careful PCB layout is critical to achieve clean and stable operation.
In the typical application circuit, the input capacitors (0.1μF and a bulk capacitor with at least 10μF capacitance) between
VDD and GNDA are required to reduce the peak current drawn from input power source and reduce the switching noise,increase internal DC-DC efficiency. For the supply input capacitors, choose the ceramic capacitor because they have the lowest
equivalent series resistance (ESR), smallest size, and lowest cost. For most applications, we recommend to use at least 0.1μF
and a 10μF ceramic capacitors with X5R or X7R temperature characteristic. When operating at a VDD voltage close to the UVLO
threshold, more input capacitance may be required to keep the input voltage ripple from tripping the UVLO protection. Also,these low-ESR ceramic bypass capacitors must be placed as close to the chip pads as possible. For the logic supply input, werecommend to use a 1μF ceramic capacitors with X5R or X7R between VDDL pin and GNDA. On side-B, the supply output
capacitors between VISO and GNDB are required as well to keep the output voltage ripple small and to ensure loop stability.
These bypass capacitors must have low impedance at the switching frequency. Ceramic capacitors are recommended due totheir small size and low ESR. Make sure the capacitor does not degrade its capacitance significantly over temperature and DC
bias. Although a 10μF capacitor is adequate, higher decoupling capacitors (such as 47μF) on both VDD and VISO pins to therespective grounds are strongly recommended to provide better noise and ripple performance, because of very-high current
flowing through the VDD and VISO supplies.
Place the supply input capacitors, supply output capacitors, and the CA-IS36xx IC on the same PCB layer. The paths must
be wide and short to minimize inductance, also any via holes must be avoided on these paths. See Figure 11-3 recommended
components placement for the PCB layout.

30

Copyright © 2020, Chipanalog
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Shanghai Chipanalog Microelectronics Co., Ltd.

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19<2mm

10μF 0.1μF<2mm

Shanghai Chipanalog Microelectronics Co., Ltd.

VDD

VISO

GNDA

GNDB

0.1μF 10μF

1μF

VDDL
GNDA

:PCB TOP Layer:PCB Bottom Layer:PCB Vias

Figure 11-3. Recommended PCB layout for CA-IS36xxVW with VDDL = VDD

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

31

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644
Version 1.05 2022/12/19
12 Package Information

Shanghai Chipanalog Microelectronics Co., Ltd.

16-Pin Wide Body SOIC Package Outline

Note:
1. All dimensions are in millimeters, angles are in degrees.

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Copyright © 2020, Chipanalog
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Shanghai Chipanalog Microelectronics Co., Ltd.

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

Shanghai Chipanalog Microelectronics Co., Ltd.

13 Soldering Temperature (reflow) Profile

TP

Temperature

TL

Max. Ramp Up Rate=3℃/s

TC-5℃

tL

Preheat Area

Tsmax

tP

Tsmin
ts

25℃
Time 25℃ to PeakTime

Figure 13-1. Soldering Temperature (reflow) Profile

Table 13-1. Soldering Temperature Parameter
Profile Feature
Average ramp-up rate(217 ℃ to Peak)Time of Preheat temp(from 150 ℃ to 200 ℃
Time to be maintained above 217 ℃
Peak temperature
Time within 5 ℃of actual peak temp
Ramp-down rate
Time from 25℃ to peak temp

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

Pb-Free Assembly
3℃/second max
60-120 second
60-150 second
260 +5/-0 ℃
30 second
6 ℃/second max.
8 minutes max

33

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644
Version 1.05 2022/12/19
14 Tape and Reel Information

Shanghai Chipanalog Microelectronics Co., Ltd.

REEL DIMENSIONSTAPE DIMENSIONS

A0
B0
K0
W
P1

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

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Shanghai Chipanalog Microelectronics Co., Ltd.
evice

Package
Type

Package
Drawing

Pins

SPQ

CA-IS3620LW
CA-IS3620HW
CA-IS3621LW
CA-IS3621HW
CA-IS3622LW
CA-IS3622HW
CA-IS3640LW
CA-IS3640HW
CA-IS3641LW
CA-IS3640HW
CA-IS3642LW
CA-IS3642HW
CA-IS3643LW
CA-IS3643HW
CA-IS3644LW
CA-IS3644HW
CA-IS3620LVW
CA-IS3620HVW
CA-IS3621LVW
CA-IS3621HVW
CA-IS3622LVW
CA-IS3622HVW
CA-IS3640LVW
CA-IS3640HVW
CA-IS3641LVW
CA-IS3640HVW
CA-IS3642LVW
CA-IS3642HVW
CA-IS3643LVW
CA-IS3643HVW
CA-IS3644LVW
CA-IS3644HVW

SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC

W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W

16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16

1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000

Copyright © 2020, Chipanalog Incorporated
Shanghai Chipanalog Microelectronics Co., Ltd.

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644

Version 1.05 2022/12/19

Reel
Diameter
(mm)
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330

Reel Width
W1 (mm)

A0
(mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
(mm)

Pin1
Quadrant

16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4

10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9
10.9

10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7
10.7

3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2

12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0

16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0

Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1

35

CA-IS3620, CA-IS3621, CA-IS3622,
CA-IS3640, CA-IS3641, CA-IS3642, CA-IS3643, CA-IS3644
Version 1.05 2022/12/19
15 IMPORTANT NOTICE

Shanghai Chipanalog Microelectronics Co., Ltd.

The above information is for reference only and is used to assist Chipanalog customers in design and development. Chipanalog
reserves the right to change the above information due to technological innovation without prior notice.
Chipanalog products are all factory tested. The customers shall be responsible for self-assessment and determine whether it isapplicable for their specific application. Chipanalog's authorization to use the resources is limited to the development ofrelated applications that the Chipanalog products involved in. In addition, the resources shall not be copied or displayed. And
Chipanalog shall not be liable for any claim, cost, and loss arising from the use of the resources.
Trademark Information

Chipanalog Inc. ®, Chipanalog® are trademarks or registered trademarks of Chipanalog.

http://www.chipanalog.com
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