UM10211
LPC2364/66/68/78 User manual
Rev. 01 — 6 July 2007

User manual

Document information
Info

Content

Keywords

LPC2300, LPC2364, LPC2366, LPC2368, LPC2378, ARM, ARM7, 32-bit,
USB, Ethernet, CAN, I2S, Microcontroller

Abstract

An initial LPC2364/6/8/78 User manual revisionUM10211NXP Semiconductors

LPC2364/66/68/78 User manual

Revision history
Rev

Date

Description

01.05

20070706

Changes made to the 20070327 edition:• RESET, RESETOUT, and VBAT description updated in Section 8–2 “Pin description for
LPC2364/6/8”.

• BLS0 function added to pin P4[25] for LPC2378 only, see and Section 8–4 “Pindescription for LPC2378” and Section 5–1 “Introduction”.

• Clock generation block diagram updated Figure 4–9 “Clock generation for the
LPC2300”.
01.04

20070618

Changes made to the 20070327 edition:• Battery RAM usage updated (see Section 4–7.10 “Power domains”).
• CCLKCFG register bits updated: Only odd values are supported and can be used forprogramming the CCLKSEL bits, see Table 4–34 “CPU Clock Configuration register(CCLKCFG - address 0xE01F C104) bit description”.

• Supported N and M values updated in PLL configuration register, see Table 4–26 “PLL
Configuration register (PLLCFG - address 0xE01F C084) bit description”:
01.03

20070327

Changes made to the 20061013 edition:• VDD(1V8) pins are left unconnected• Deep power-down mode removed
01.02

20061013

Changes made to 20061006 edition:• Flash memory programming firmware chapter updated
01.01

20061006

Changes made to 20061002 edition:• Pad structure details added in Table 8–80 “LPC2364/66/68 pin description” and Table
8–81 “LPC2378 pin description”• order of the “On-Chip RAM“ elements adjusted in Table 2–3 “LPC2300 memory usage”
01

20061002

Preliminary LPC234/6/8/78 User manual

Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Chapter 1: Introductory informationRev. 01 — 6 July 2007

User manual

1. Introduction
LPC2364/6/8/78 is an ARM-based microcontroller for applications requiring serial
communications for a variety of purposes. These microcontrollers incorporate a 10/100
Ethernet MAC, USB 2.0 Full Speed interface, four UARTs, two CAN channels, an SPI
interface, two Synchronous Serial Ports (SSP), three I2C interfaces, an I2S interface, anda MiniBus (LPC2378 only: 8-bit data/16-bit address parallel bus).
Important: Term “LPC2300“ in the following text will be used as a generic name for all
four parts covered with this user manual: LPC2364, LPC2366, LPC2368, and LPC2378.
Only when needed, a specific device name will be used to single out one of them.

2. Features• ARM7TDMI-S processor, running at up to 72 MHz.
• Up to 512 kB on-chip Flash Program Memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Single Flash sector or full chip erase in
400 ms and 256 bytes programming in 1 ms. Flash program memory is on the ARM
local bus for high performance CPU access.

• Up to 32 kB of SRAM on the ARM local bus for high performance CPU access.
• 16 kB Static RAM for Ethernet interface. Can also be used as general purpose SRAM.
• 8 kB Static RAM for USB interface. Can also be used as general purpose SRAM.
• Dual AHB system that provides for simultaneous Ethernet DMA, USB DMA, andprogram execution from on-chip Flash with no contention between those functions. A
bus bridge allows the Ethernet DMA to access the other AHB subsystem.

• External memory controller that supports static devices such as Flash and SRAM. An
8-bit data/16-bit address parallel bus is available in LPC2378 only.

• Advanced Vectored Interrupt Controller, supporting up to 32 vectored interrupts.
• General Purpose AHB DMA controller (GPDMA) that can be used with the SSP serialinterfaces, the I2S port, and the SD/MMC card port, as well as for memory-to-memorytransfers.

• Serial Interfaces:– Ethernet MAC with associated DMA controller. These functions reside on an
independent AHB bus.
– USB 2.0 Device with on-chip PHY and associated DMA controller.
– Four UARTs with fractional baud rate generation, one with modem control I/O, onewith IrDA support, all with FIFO. These reside on the APB bus.
– Two CAN channels with Acceptance Filter/FullCAN mode reside on the APB bus.
– SPI controller, residing on the APB bus.
– Two SSP controllers with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt and pins. The SSP controllers can be usedwith the GPDMA controller and reside on the APB bus.
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Chapter 1: Introductory information– Three I2C Interfaces reside on the APB bus. The second and third I2C interfaces
are expansion I2Cs with standard port pins rather than special open drain I2C pins.
– I2S (Inter-IC Sound) interface for digital audio input or output, residing on the APB
bus. The I2S interface can be used with the GPDMA.

• Other APB Peripherals:– Secure Digital (SD) / MultiMediaCard (MMC) memory card interface.
– Up to 70 (LPC2364/6/8) or 104 (LPC2378) general purpose I/O pins.
– 10 bit A/D converter with input multiplexing among 6 pins (LPC2364/66/68) or 8
pins LPC2378).
– 10 bit D/A converter.
– Four general purpose Timers with two capture inputs each and up to four compare
output pins each. Each Timer block has an external count input.
– One PWM/Timer block with support for 3 phase motor control. The PWM has two
external count inputs.
– Real Time Clock with separate power pin, clock source can be the RTC oscillator
or the APB clock.
– 2 kB Static RAM powered from the RTC power pin, allowing data to be stored
when the rest of the chip is powered off.
– Watchdog Timer. The watchdog timer can be clocked from the internal RC
oscillator, the RTC oscillator, or the APB clock.

• Standard ARM Test/Debug interface for compatibility with existing tools.
• Emulation Trace Module.
• Support for real-time trace.
• Single 3.3 V power supply (3.0 V to 3.6 V).
• Four reduced power modes: Idle, Sleep, Power Down, and Deep Power down.
• Four external interrupt inputs. In addition every PORT0/2 pin can be configured as anedge sensing interrupt.

• Processor wakeup from Power Down mode via any interrupt able to operate during
Power Down mode (includes external interrupts, RTC interrupt, and Ethernet wakeup
interrupt).

• Two independent power domains allow fine tuning of power consumption based onneeded features.

• Brownout detect with separate thresholds for interrupt and forced reset.
• On-chip Power On Reset.
• On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
• 4 MHz internal RC oscillator that can optionally be used as the system clock. For USB
and CAN application, an external clock source is suggested to be used.

• On-chip PLL allows CPU operation up to the maximum CPU rate without the need fora high frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.

• Boundary scan for simplified board testing. (LPC2378 only).
• Versatile pin function selections allow more possibilities for using on-chip peripheral
functions.
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Chapter 1: Introductory information

3. Applications• Industrial control• Medical systems

4. Ordering options
Table 1.

LPC2364/6/8/78 ordering options

Type number

Flash
SRAM(kB)
Ethernet USB CAN SD/ GP
ADC DAC Temp(kB) Local Ether. GP/ RTC Total
dev +MMC DMA
range
4kB
bus
buff
USB
FIFO

LPC2364FB100 128

8

16

8

2

34

RMII

yes

2 ch noyes

6 ch 1 ch−40 °C to+85 °C

LPC2366FB100 256

32

16

8

2

58

RMII

yes

2 ch noyes

6 ch 1 ch−40 °C to+85 °C

LPC2368FB100 512

32

16

8

2

58

RMII

yes

2 ch yesyes

6 ch 1 ch−40 °C to+85 °C

LPC2378 ordering options

RTC

Total

LPC2378FBD144 512

SRAM(kB)
GP/USB

Flash(kB)

Ether. buff

Type number

Local bus

Table 2.

32

16

8

2

58

Ext Bus Ether USB CAN SD/ GP
ADC DAC Temp
net
dev +
MMC DMA
range
4kB
FIFO

MiniBus: RMII
8 data,16 addr& 2 cs

yes

2 ch

yes

yes

8 ch

1 ch

−40 °C to+85 °C

5. Architectural overview
The LPC2300 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local
Bus for closely coupled, high speed access to the majority of on-chip memory, the AMBA
Advanced High-performance Bus (AHB) interfacing to high speed on-chip peripherals andexternal memory, and the AMBA Advanced Peripheral Bus (APB) for connection to otheron-chip peripheral functions. The microcontroller permanently configures the
ARM7TDMI-S processor for little-endian byte order.
The microcontroller implements two AHB buses in order to allow the Ethernet block tooperate without interference caused by other system activity. The primary AHB, referred
to as AHB1, includes the Vectored Interrupt Controller, General Purpose DMA Controller,
External Memory Controller, USB interface, and a 8 kB SRAM primarily intended for use
by the USB.
The second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
off-chip memory or unused space in memory residing on AHB1.
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Chapter 1: Introductory information

In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, theGeneral Purpose DMA function, and the Ethernet block (via the bus bridge from AHB2).
Bus masters with access to AHB2 are the ARM7 and the Ethernet block.
AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB
ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the
AHB address space. Lower speed peripheral functions are connected to the APB bus.
The AHB to APB bridge interfaces the APB bus to the AHB bus. APB peripherals are also
allocated a 2 MB range of addresses, beginning at the 3.5 GB address point. Each APB
peripheral is allocated a 16 kB address space within the APB address space.

6. ARM7TDMI-S processor
The ARM7TDMI-S is a general purpose 32 bit microprocessor, which offers highperformance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput andimpressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:• The standard 32 bit ARM instruction set.
• A 16 bit THUMB instruction set.
The THUMB set’s 16 bit instruction length allows it to approach twice the density ofstandard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16 bit processor using 16 bit registers. This is possible because THUMB code
operates on the same 32 bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of theperformance of an equivalent ARM processor connected to a 16 bit memory system.
The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet thatcan be found on official ARM website.

7. On-Chip flash memory system
The LPC2300 includes a Flash memory system with up to 512 kB. This memory may be
used for both code and data storage. Programming of the Flash memory may be
accomplished in several ways. It may be programmed In System via the serial port. The
application program may also erase and/or program the Flash while the application isrunning, allowing a great degree of flexibility for data storage field firmware upgrades, etc.
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Chapter 1: Introductory information

The Flash is 128 bits wide and includes pre-fetching and buffering techniques to allow it tooperate at SRAM speeds.

8. On-Chip Static RAM
The LPC2300 includes a static RAM memory up to 32 kB in size, that may be used forcode and/or data storage.
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls
during back-to-back writes. The write-back buffer always holds the last data sent bysoftware to the SRAM. The data is only written to the SRAM when software does anotherwrite. After a "warm" chip reset, the SRAM does not reflect the last write operation. Two
identical writes to a location guarantee that the data will be present after a Reset.
Alternatively, a dummy write operation before entering idle or power-down mode will
similarly guarantee that the last data written will be present after a subsequent Reset.

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Chapter 1: Introductory information

9. Block diagram

TMS TDI

XTAL1
XTAL2
VDDA

trace signals

LPC2364/66/68
P0, P1, P2,
P3, P4

8/32 kBSRAM
HIGH-SPEED
GPI/O
70 PINS
TOTAL

128/256/
512 kBFLASHINTERNAL
CONTROLLERSETHERNET
MAC WITHDMA

EINT3 to EINT0

ARM7TDMI-S

SRAM FLASHAHB2RMII(8)

TEST/DEBUG
INTERFACEEMULATION
TRACE MODULE

TRST TCK TDO
EXTIN0VDD(3V3)PLL

SYSTEM
FUNCTIONS

systemclock

INTERNAL RC
OSCILLATORVREFVSSA, VSSVDD(DCDC)(3V3)VECTORED
INTERRUPTCONTROLLER

AHB
BRIDGE

AHB1

AHB
BRIDGEMASTER AHB TO SLAVEPORT APB BRIDGE PORT

16 kB
SRAM

RESET

AHB TOAPB BRIDGE

8 kB
SRAM

USB WITH
4 kB RAMAND DMA

VBUS
USB_D+, USB_D−
USB_CONNECT
USB_UP_LED

GP DMA
CONTROLLERI2S INTERFACEI2SRX_CLKI2STX_CLKI2SRX_WS
I2STX_WS
I2SRX_SDA
I2STX_SDA

PWM1

SPI, SSP0 INTERFACE

SCK, SCK0MOSI, MOSI0MISO, MISO0
SSEL, SSEL1

P0, P1LEGACY GPI/O
52 PINS TOTAL

SSP1 INTERFACE

6 × AD0

A/D CONVERTER

P0, P22 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1

EXTERNAL INTERRUPTS
CAPTURE/COMPARETIMER0/TIMER1/
TIMER2/TIMER3

2 × PCAP1AOUTMCICLK, MCIPWR

SD/MMC CARD
INTERFACE(1)MCICMD,MCIDAT[3:0]

D/A CONVERTERUART0, UART2, UART3

VBAT

TXD0, TXD2, TXD3
RXD0, RXD2, RXD3

2 kB BATTERY RAM
TXD1
RXD1
DTR1, RTS1

power domain
domain 22
power
RTCX1
RTCX2

SCK1
MOSI1
MIS01
SSEL1

RTC
OSCILLATORREALTIME
CLOCK

UART1

DSR1, CTS1, DCD1,
RI1

WATCHDOG TIMER

CAN1, CAN2

RD1, RD2
TD1, TD2

SYSTEM CONTROL

I2C0, I2C1, I2C2

SCL0, SCL1, SCL2
SDA0, SDA1, SDA2002aac566(1) LPC2368 only.

Fig 1. LPC2364/6/8 block diagram
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Chapter 1: Introductory information

TMS TDIXTAL1
VDD(3V3)
XTAL2

trace signals

P0, P1, P2,
P3, P4

LPC2378

32 kB
SRAM

HIGH-SPEED
GPI/O
104 PINSTOTAL

512 kBFLASHINTERNAL
CONTROLLERS

EINT3 to EINT0
P0, P2

ARM7TDMI-S

SRAM FLASHAHB2RMII(8)

TEST/DEBUG
INTERFACE

VDDA

RESET

PLL

SYSTEM
FUNCTIONS

systemclock

INTERNAL RC
OSCILLATORVECTORED
INTERRUPTCONTROLLER

AHB
BRIDGE

16 kB
SRAM

ETHERNET
MAC WITHDMAEMULATION
TRACE MODULE

TRST TCK TDO
EXTIN0 DBGEN

AHB
BRIDGEMASTER AHB TO SLAVEPORT APB BRIDGE PORTAHB TOAPB BRIDGE

EXTERNAL
MEMORYCONTROLLERVREFVSSA, VSSVDD(DCDC)(3V3)

D[7:0]
A[15:0]WE, OE, CS0, CS1,
BLS0

AHB1

8 kB
SRAM

USB WITH
4 kB RAMAND DMA

VBUS
2 × USB_D+/USB_D−
2 × USB_CONNECT
2 × USB_UP_LED

GP DMA
CONTROLLERI2S INTERFACEI2SRX_CLKI2STX_CLKI2SRX_WS
I2STX_WS
I2SRX_SDA
I2STX_SDA

PWM1

SPI, SSP0 INTERFACE

SCK, SCK0MOSI, MOSI0MISO, MISO0
SSEL, SSEL1

P0, P1LEGACY GPI/O
56 PINS TOTAL

SSP1 INTERFACE

8 × AD0

A/D CONVERTER

2 × CAP0/CAP1/
CAP2/CAP3
4 × MAT2,
2 × MAT0/MAT1/
MAT3
6 × PWM1

EXTERNAL INTERRUPTS
CAPTURE/COMPARETIMER0/TIMER1/
TIMER2/TIMER3

2 × PCAP1AOUTMCICLK, MCIPWR

SD/MMC CARD
INTERFACEMCICMD,MCIDAT[3:0]

D/A CONVERTERUART0, UART2, UART3

VBAT

TXD0, TXD2, TXD3
RXD0, RXD2, RXD3

2 kB BATTERY RAM
TXD1
RXD1
DTR1, RTS1

power domain 2
RTCX1
RTCX2

SCK1
MOSI1
MIS01
SSEL1

RTC
OSCILLATORREALTIME
CLOCK

UART1

DSR1, CTS1, DCD1,
RI1

ALARM
CAN1, CAN2

RD1, RD2
TD1, TD2

I2C0, I2C1, I2C2

SCL0, SCL1, SCL2
SDA0, SDA1, SDA2

WATCHDOG TIMERSYSTEM CONTROL

002aac574

Fig 2. LPC2378 block diagram

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Chapter 2: LPC2300 memory addressing
Rev. 01 — 6 July 2007

User manual

1. Memory map and peripheral addressing
ARM processors have a single 4 GB address space. The following table shows how thisspace is used on NXP embedded ARM devices.
Table 3.

LPC2300 memory usage

Address range General use

Address range details and description

0x0000 0000 to
0x3FFF FFFF

On-Chip
NV Memoryand fast I/O

0x0000 0000 - 0x0007 FFFF

Flash Memory (up to 512 kB)

0x3FFF C000 - 0x3FFF FFFF

Fast GPIO registers

0x4000 0000 to
0x7FFF FFFF

On-Chip RAM

0x8000 0000 to
0xDFFF FFFF

0x4000 0000 - 0x4000 7FFF

RAM (up to 32 kB)

0x7FD0 0000 - 0x7FD0 1FFF

USB RAM (8 kB)

0x7FE0 0000 - 0x7FE0 3FFF

Ethernet RAM (16 kB)

Off-Chip Memory Two static memory banks, 64 KB each:0x8000 0000 - 0x8000 FFFF

Static memory bank 0, 64 KB

0x8100 0000 - 0x8100 FFFF

Static memory bank 1, 64 KB

0xE000 0000 to APB Peripherals 0xE000 0000 - 0xE008 FFFF
0xEFFF FFFF
0xE01F C000 - 0xE01F FFFF

36 peripheral blocks, 16 kB each (some unused).

0xF000 0000 to AHB Peripherals 0xFFE0 0000 - 0xFFE0 3FFF
0xFFFF FFFF
0xFFE0 4000 - 0xFFE0 7FFF

Ethernet Controller

System Control Block
General Purpose DMA Controller

0xFFE0 8000 - 0xFFE0 BFFF

External Memory Controller (EMC)

0xFFE0 C000 - 0xFFE0 FFFF

USB Controller

0xFFFF F000 - 0xFFFF FFFF

Vectored Interrupt Controller (VIC)

2. Memory maps
The LPC2300 incorporates several distinct memory regions, shown in the following
figures. Figure 2–3 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping,which is described later in this section.

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Chapter 2: LPC2300 Memory map

4.0 GB

0xFFFF FFFFAHB PERIPHERALS
0xF000 0000

3.75 GBAPB PERIPHERALS
3.5 GB

0xE000 0000

3.0 GB

0xC000 0000
RESERVED ADDRESS SPACE

2.0 GB

0x8000 0000
BOOT ROM AND BOOT FLASH(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)RESERVED ADDRESS SPACE
0x7FE0 3FFF
0x7FE0 0000

ETHERNET RAM (16 kB)

0x7FD0 1FFF

USB RAM (8 KB)

0x7FD0 0000

RESERVED ADDRESS SPACE
0x4000 8000
0x4000 7FFF
32 kB LOCAL ON-CHIP STATIC RAM (LPC2366/LPC2368)
0x4000 2000
0x4000 1FFF
8 kB LOCAL ON-CHIP STATIC RAM (LPC2364)
1.0 GB

0x4000 0000

RESERVED FOR ON-CHIP MEMORY
0x0008 0000
0x0007 FFFF
0x0004 0000
0x0003 FFFF
0x0002 0000
0x0001 FFFF
0x0000 0000

TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY (LPC2368)
TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY (LPC2366)
0.0 GBTOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY (LPC2364)

002aac577

Fig 3. LPC2364/66/68 system memory map

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Chapter 2: LPC2300 Memory map

4.0 GB

0xFFFF FFFFAHB PERIPHERALS
0xF000 0000

3.75 GBAPB PERIPHERALS
3.5 GB

0xE000 0000

RESERVED ADDRESS SPACE
3.0 GB

0xC000 0000

0x8100 FFFF

EXTERNAL MEMORY BANK 1 (64 kB)

2.0 GB

0x8100 0000
0x8000 FFFF

EXTERNAL MEMORY BANK 0 (64 kB)

0x8000 0000

BOOT ROM AND BOOT FLASH(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)RESERVED ADDRESS SPACE
0x7FE0 3FFF
0x7FE0 0000

ETHERNET RAM (16 kB)

0x7FD0 1FFF

USB RAM (8 kB)

0x7FD0 0000

RESERVED ADDRESS SPACE

0x4000 8000
0x4000 7FFF
1.0 GB

32 kB LOCAL ON-CHIP STATIC RAM

0x4000 0000

RESERVED ADDRESS SPACE
0x0008 0000
0x0007 FFFFTOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY
0.0 GB

0x0000 0000

002aac585

Fig 4. LPC2378 system memory map

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Chapter 2: LPC2300 Memory map

4.0 GB

0xFFFF FFFFAHB PERIPHERALS
0xFFE0 0000
0xFFDF FFFF

4.0 GB - 2 MB

RESERVED

0xF000 0000
0xEFFF FFFF

3.75 GBRESERVED

0xE020 0000
0xE01F FFFF

3.5 GB + 2 MB
APB PERIPHERALS
3.5 GB

0xE000 0000

Fig 5. Peripheral memory map

Figure 6 and Table 2–4 show different views of the peripheral address space. Both the
AHB and APB peripheral areas are 2 megabyte spaces which are divided up into 128
peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying theaddress decoding for each peripheral.

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Chapter 2: LPC2300 Memory map

All peripheral register addresses are word aligned (to 32 bit boundaries) regardless of
their size. This eliminates the need for byte lane mapping hardware that would be required
to allow byte (8 bit) or half-word (16 bit) accesses to occur at smaller boundaries. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.

VECTORED INTERRUPT CONTROLLER

0xFFFF F000 (4G - 4K)

0xFFFF C000

(AHB PERIPHERAL #126)
0xFFFF 8000

0xFFE1 8000
NOT USED(AHB PERIPHERAL #5)
0xFFE1 4000
NOT USED(AHB PERIPHERAL #4)
0xFFE1 0000
USB CONTROLLER(AHB PERIPHERAL #3)
0xFFE0 C000
EXTERNAL MEMORY CONTROLLER(AHB PERIPHERAL #2)
0xFFE0 8000
GENERAL PURPOSE DMA CONTROLLER(AHB PERIPHERAL #1)
0xFFE0 4000
ETHERNET CONTROLLER(AHB PERIPHERAL #0)
0xFFE0 0000

Fig 6. AHB peripheral map

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Chapter 2: LPC2300 Memory map

3. APB peripheral addresses
The following table shows the APB address map. No APB peripheral uses all of the 16 kB
space allocated to it. Typically each device’s registers are "aliased" or repeated at multiple
locations within each 16 kB range.
Table 4.

APB peripherals and base addresses

APB Peripheral

Base Address

Peripheral Name

00xE000 0000

Watchdog Timer

1

0xE000 4000

Timer 02

0xE000 8000

Timer 1

30xE000 C000

UART0

4

0xE001 0000

UART1

5

0xE001 4000

Not used

60xE001 8000

PWM1

7

0xE001 C000

I2C0

8

0xE002 0000

SPI

90xE002 4000

RTC

10

0xE002 8000

GPIO

11

0xE002 C000

Pin Connect Block120xE003 0000

SSP1

13

0xE003 4000

ADC

14

0xE003 8000

CAN Acceptance Filter RAM

15

0xE003 C000CAN Acceptance Filter Registers

16

0xE004 0000

CAN Common Registers

17

0xE004 4000

CAN Controller 1180xE004 8000

CAN Controller 2

19 to 220xE004 C000 to 0xE005 8000

Not used

23

0xE005 C000

I2C1

24

0xE006 0000

Not used25

0xE006 4000

Not used26

0xE006 8000

SSP0

27

0xE006 C000

DAC

28

0xE007 0000

Timer 229

0xE007 4000

Timer 330

0xE007 8000

UART2

31

0xE007 C000

UART3

32

0xE008 0000

I2C2

33

0xE008 4000

Battery RAM

34

0xE008 8000

I2S

35

0xE008 C000

SD/MMC Card Interface

36 to 126

0xE009 0000 to 0xE01F BFFF

Not used

127

0xE01F C000

System Control Block

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4. LPC2300 memory re-mapping and boot ROM
4.1 Memory map concepts and operating modes
The basic concept on the LPC2300 is that each memory area has a "natural" location in
the memory map. This is the address range for which code residing in that area is written.
The bulk of each memory space remains permanently fixed in the same location,
eliminating the need to have portions of the code designed to run in different address
ranges.
Because of the location of the interrupt vectors on the ARM7 processor (at addresses
0x0000 0000 through 0x0000 001C, as shown in Table 2–5 below), a small portion of the
Boot ROM and SRAM spaces need to be re-mapped in order to allow alternative uses ofinterrupts in the different operating modes described in Table 2–6. Re-mapping of theinterrupts is accomplished via the Memory Mapping Control feature (Section 2–5 “Memory
mapping control” on page 17).
Table 5.

ARM exception vector locations

Address

Exception

0x0000 0000

Reset

0x0000 0004

Undefined Instruction

0x0000 0008

Software Interrupt

0x0000 000C

Prefetch Abort (instruction fetch memory fault)

0x0000 0010

Data Abort (data access memory fault)

0x0000 0014

Reserved
Note: Identified as reserved in ARM documentation, this location is usedby the Boot Loader as the Valid User Program key. This is described indetail in "Flash Memory System and Programming" chapter on page 517.

0x0000 0018

IRQ

0x0000 001C

FIQ

Table 6.

LPC2300 Memory mapping modes

Mode

Activation

Usage

Boot
Loadermode

Hardwareactivation by
any Reset

The Boot Loader always executes after any reset. The Boot ROM
interrupt vectors are mapped to the bottom of memory to allow
handling exceptions and using interrupts during the Boot Loading
process. A sector of the Flash memory (the Boot Flash) is available tohold part of the Boot Code.

User
Flash
mode

Softwareactivation by
Boot code

Activated by the Boot Loader when a valid User Program Signature isrecognized in memory and Boot Loader operation is not forced.
Interrupt vectors are not re-mapped and are found in the bottom of theFlash memory.

User RAM Software
Activated by a User Program as desired. Interrupt vectors aremode
activation by re-mapped to the bottom of the Static RAM.
User program

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4.2 Memory re-mapping
In order to allow for compatibility with future derivatives, the entire Boot ROM is mapped
to the top of the on-chip memory space. In this manner, the use of larger or smaller flash
modules will not require changing the location of the Boot ROM (which would requirechanging the Boot Loader code itself) or changing the mapping of the Boot ROM interrupt
vectors. Memory spaces other than the interrupt vectors remain in fixed locations.
Figure 2–7 shows the on-chip memory mapping in the modes defined above.
The portion of memory that is re-mapped to allow interrupt processing in different modes
includes the interrupt vector area (32 bytes) and an additional 32 bytes for a total of
64 bytes, that facilitates branching to interrupt handlers at distant physical addresses. The
remapped code locations overlay addresses 0x0000 0000 through 0x0000 003F. A typicaluser program in the Flash memory can place the entire FIQ handler at address
0x0000 001C without any need to consider memory boundaries. The vector contained in
the SRAM, external memory, and Boot ROM must contain branches to the actual interrupt
handlers, or to other instructions that accomplish the branch to the interrupt handlers.
There are three reasons this configuration was chosen:
1. To give the FIQ handler in the Flash memory the advantage of not having to take amemory boundary caused by the remapping into account.
2. Minimize the need to for the SRAM and Boot ROM vectors to deal with arbitrary
boundaries in the middle of code space.
3. To provide space to store constants for jumping beyond the range of single word
branch instructions.
Re-mapped memory areas, including the Boot ROM and interrupt vectors, continue toappear in their original location in addition to the re-mapped address.
Details on re-mapping and examples can be found in Section 2–5 “Memory mapping
control” on page 17.

5. Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. This allows code running in different memory spaces
to have control of the interrupts.

5.1 Memory Mapping Control Register (MEMMAP - 0xE01F C040)
Whenever an exception handling is necessary, microcontroller will fetch an instruction
residing on exception corresponding address as described in Table 2–5 “ARM exception
vector locations” on page 16. The MEMMAP register determines the source of data thatwill fill this table.
Table 7.

Memory mapping control registers

Name

Description

MEMMAP Memory mapping control. Selects whether the
ARM interrupt vectors are read from the Boot
ROM, User Flash, or RAM.
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AccessReset Address
value

R/W

0x00

0xE01F C040

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Table 8.

Memory Mapping control register (MEMMAP - address 0xE01F C040) bit
description

Bit

Symbol Value Description

1:0

MAP

Reset
value

00

Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 00

01

User Flash Mode. Interrupt vectors are not re-mapped and residein Flash.

10

User RAM Mode. Interrupt vectors are re-mapped to Static RAM.

11

User External Memory Mode (available on LPC2378 only).

Warning: Improper setting of this value may result in incorrect operation of
the device.
7:2

-

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

5.2 Memory mapping control usage notes
Memory Mapping Control simply selects one out of three available sources of data (sets of
64 bytes each) necessary for handling ARM exceptions (interrupts).
For example, whenever a Software Interrupt request is generated, ARM core will always
fetch 32 bit data "residing" on 0x0000 0008 see Table 2–5 “ARM exception vector
locations” on page 16. This means that when MEMMAP[1:0] = 10 (User RAM Mode),
read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of
MEMMAP[1:0] = 00 (Boot Loader Mode), read/fetch from 0x0000 0008 will provide data
available also at 0x7FFF E008 (Boot ROM remapped from on-chip Bootloader).

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EXTERNAL MEMORY INTERRUPT VECTORS

0x8000 0000

8 kB BOOT ROM

0x7FFF FFFF

2.0 GB - 8 kB

(BOOT ROM INTERRUPT VECTORS)

2.0 GB - 64 kB

8 kB BOOT FLASH(RE-MAPPED FROM TOP OF FLASH MEMORY)

0x7FFF E000
0x7FFE FFFF

2.0 GB

2.0 GB - 72 kB

0x7FFE E000
RESERVED FOR ON-CHIP MEMORY

upper limit depends on
specific part number
STATIC RAM

1.0 GB(SRAM INTERRUPT VECTORS)FAST GPIO REGISTERS

0x4000 0000
0x3FFF FFFF
0x3FFF C000
0x3FFF BFFF

PARTCFG REGISTERS
0x3FFF 8000

RESERVED FOR ON-CHIP MEMORY

BOOT FLASH

upper limit depends on
specific part number

FLASH MEMORY

0.0 GB

ACTIVE INTERRUPT VECTORS(FROM FLASH, SRAM, BOOT ROM, OR EXT MEMORY)

0x0000 0000

Fig 7. Map of lower memory is showing re-mapped and re-mappable areas

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6. Prefetch abort and data abort exceptions
The LPC2300 generates the appropriate bus cycle abort exception if an access is
attempted for an address that is in a reserved or unassigned address region. The regionsare:• Areas of the memory map that are not implemented for a specific ARM derivative. For
the LPC2300, this is:– Address space between On-Chip Non-Volatile Memory and the Special Register
space. Labelled "Reserved for On-Chip Memory" in Figure 2–3.
– Address space between On-Chip Static RAM and the Boot ROM. Labelled"Reserved Address Space" in Figure 2–3.
– External Memory– Reserved regions of the AHB and APB spaces. See Figure 2–5.

• Unassigned AHB peripheral spaces. See Figure 2–6.
• Unassigned APB peripheral spaces. See Table 2–4.
For these areas, both attempted data access and instruction fetch generate an exception.
In addition, a Prefetch Abort exception is generated for any instruction fetch that maps toan AHB or APB peripheral address, or to the Special Register space located just below
the SRAM at addresses 0x3FFF8000 through 0x3FFFFFFF.
Within the address space of an existing APB peripheral, a data abort exception is not
generated in response to an access to an undefined address. Address decoding withineach peripheral is limited to that needed to distinguish defined registers within the
peripheral itself. For example, an access to address 0xE000 D000 (an undefined address
within the UART0 space) may result in an access to the register defined at address
0xE000 C000. Details of such address aliasing within a peripheral space are not definedin the LPC2300 documentation and are not a supported feature.
If software executes a write directly to the Flash memory, the MAM generates a data abort
exception. Flash programming must be accomplished using the specified Flashprogramming interface provided by the Boot Code.
Note that the ARM core stores the Prefetch Abort flag along with the associatedinstruction (which will be meaningless) in the pipeline and processes the abort only if an
attempt is made to execute the instruction fetched from the illegal address. This preventsaccidental aborts that could be caused by prefetches that occur when code is executed
very near a memory boundary.

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User manual

1. Summary of system control block functions
The System Control Block includes several system features and control registers for anumber of functions that are not related to specific peripheral devices. These include:• Reset• Brown-Out Detection• External Interrupt Inputs• Miscellaneous System Controls and Status• Code Security vs. Debugging• AHB Configuration
Each type of function has its own register(s) if any are required and unneeded bits aredefined as reserved in order to allow future expansion. Unrelated functions never sharethe same register addresses

2. Pin description
Table 3–9 shows pins that are associated with System Control block functions.
Table 9.

Pin summary

Pin namePindirection

Pin description

EINT0

Input

External Interrupt Input 0 - An active low/high level orfalling/rising edge general purpose interrupt input. This pin may be
used to wake up the processor from Idle or Power down modes.

EINT1

Input

External Interrupt Input 1 - See the EINT0 description above.

EINT2

Input

External Interrupt Input 2 - See the EINT0 description above.

EINT3

Input

External Interrupt Input 3 - See the EINT0 description above.

RESET

Input

External Reset input - A LOW on this pin resets the chip, causing
I/O ports and peripherals to take on their default states, and theprocessor to begin execution at address 0x0000 0000.

3. Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
Table 10.
Name

Summary of system control registers
Description

Access

Reset
value

Address

External Interrupts
EXTINT

External Interrupt Flag Register

R/W

0x00

0xE01F C140

EXTMODE

External Interrupt Mode register

R/W

0x00

0xE01F C148

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Table 10.

Summary of system control registers

Name

Description

Access

Reset
value

Address

EXTPOLAR

External Interrupt Polarity Register

R/W

0x00

0xE01F C14C

Reset Source Identification Register

R/W

see text

0xE01F C180

Code Security Protection Register

WO

0x00

0xE01F C184

AHBCFG1

AHB1 Arbiter Configuration Register1 R/W

0x00

0xE01F C188

AHBCFG2

AHB2 Arbiter Configuration Register2 R/W

0x00

0xE01F C18C

0x00

0xE01F C1A0

Reset
RSID
Chip Security
CSPR

AHB Configuration

Syscon Miscellaneous Registers
SCS

System Control and Status

R/W

4. Reset
Reset has four sources on the LPC2300: the RESET pin, the Watchdog Reset, Power On
Reset (POR) and the Brown Out Detection circuit (BOD). The RESET pin is a Schmitt
trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains
a usable level, starts the Wakeup Timer (see description in Section 4–8 “Wakeup timer” inthis chapter), causing reset to remain asserted until the external Reset is de-asserted, theoscillator is running, a fixed number of clocks have passed, and the Flash controller has
completed its initialization. The relationship between Reset, the oscillator, and the
Wakeup Timer are shown in Figure 3–8.
On the assertion of any of reset sources (POR, BOD reset, External reset and Watchdog
reset), the following two sequences start simultaneously:
1. After IRC-start-up time (maximum of 60 μs on power-up), IRC provides stable clock
output, the reset signal is latched and synchronized on the IRC clock. The 2-bit IRC
wakeup timer starts counting when the synchronized reset is de-asserted. The bootcode in the ROM starts when the 2-bit IRC wakeup timer times out. The boot code
performs the boot tasks and may jump to the Flash. If the Flash is not ready toaccess, the MAM will insert wait cycles until the Flash is ready.
2. After IRC-start-up time (maximum of 60 μs on power-up), IRC provides stable clock
output, the reset signal is synchronized on the IRC clock. The Flash wakeup-timer(9-bit) starts counting when the synchronized reset is de-asserted. The Flashwakeup-timer generates the 100 μs Flash start-up time. Once it times out, the Flashinitialization sequence is started, which takes about 250 cycles. When it’s done, theMAM will be granted access to the Flash.
When the internal Reset is removed, the processor begins executing at address 0, whichis initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
The various Resets have some small differences. For example, a Power On Reset causes
the value of certain pins to be latched to configure the part.
For more details on Reset, PLL and startup/boot code interaction see Section 4–5.2 “PLLand startup/boot code interaction”.
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external
reset

Reset to the
on-chip circuitry

C
Q

watchdogreset

Reset to
PCON.PD

S

POR
BOD

WAKEUP TIMER
START

power
down

COUNT 2 nCQinternal RC
oscillator

EINT0 wakeup
EINT1 wakeup

Swrite “1”from APB

EINT2 wakeup
EINT3 wakeup
RTC wakeup
BOD wakeup
Ethernet MAC wakeup

reset
APB read of
PDBITin PCON

USB need_clk wakeup
CAN wakeup
GPIO0 port wakeup
GPIO2 port wakeup

FOSC
to otherblocksFig 8. Reset block diagram including the wakeup timer

4.1 Reset Source Identification Register (RSIR - 0xE01F C180)
This register contains one bit for each source of Reset. Writing a 1 to any of these bits
clears the corresponding read-side bit to 0. The interactions among the four sources aredescribed below.
Table 11.

Reset Source Identification register (RSID - address 0xE01F C180) bit description

Bit

Symbol Description

0

POR

Assertion of the POR signal sets this bit, and clears all of the other bits in See text
this register. But if another Reset signal (e.g., External Reset) remains
asserted after the POR signal is negated, then its bit is set. This bit is notaffected by any of the other sources of Reset.

1

EXTR

Assertion of the RESET signal sets this bit. This bit is cleared by POR,
but is not affected by WDT or BOD reset.

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value

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Table 11.

Reset Source Identification register (RSID - address 0xE01F C180) bit description

Bit

Symbol Description

Reset
value

2

WDTR

This bit is set when the Watchdog Timer times out and the WDTRESET See text
bit in the Watchdog Mode Register is 1. It is cleared by any of the othersources of Reset.

3

BODR

This bit is set when the 3.3 V power reaches a level below 2.6 V.

See text

If the VDD voltage dips from 3.3 V to 2.5 V and backs up, the BODR bit
will be set to 1.
If the VDD(3V3) voltage dips from 3.3 V to 2.5 V and continues to decline
to the level at which POR is asserted (nominally 1 V), the BODR bit iscleared.
if the VDD(3V3) voltage rises continuously from below 1 V to a level above
2.6 V, the BODR will be set to 1.
This bit is not affected by External Reset nor Watchdog Reset.
Note: Only in case when a reset occurs and the POR = 0, the BODR bit
indicates if the VDD(3V3) voltage was below 2.6 V or not.
7:4-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

5. Brown-out detection
The LPC2300 includes 2-stage monitoring of the voltage on the VDD(3V3) pins. If thisvoltage falls below 2.95 V, the Brown-Out Detector (BOD) asserts an interrupt signal to
the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt
Enable Register in the VIC (see Section 6–4.4 “Interrupt Enable Register (VICIntEnable 0xFFFF F010)”) in order to cause a CPU interrupt; if not, software can monitor the signal
by reading the Raw Interrupt Status Register (see Section 6–4.3 “Raw Interrupt Status
Register (VICRawIntr - 0xFFFF F008)”).
The second stage of low-voltage detection asserts Reset to inactivate the LPC2300 whenthe voltage on the VDD(3V3) pins falls below 2.65 V. This Reset prevents alteration of theFlash as operation of the various elements of the chip would otherwise become unreliable
due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point
the Power-On Reset circuitry maintains the overall Reset.
Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
But when Brown-Out Detection is enabled to bring the LPC2300 out of Power-Down mode
(which is itself not a guaranteed operation -- see Section 4–7.6 “Power Mode Control
register (PCON - 0xE01F C0C0)”), the supply voltage may recover from a transient before
the Wakeup Timer has completed its delay. In this case, the net result of the transient
BOD is that the part wakes up and continues operation after the instructions that set
Power-Down Mode, without any interrupt occurring and with the BOD bit in the RSID
being 0. Since all other wakeup conditions have latching flags (see Section 3–6.2“External Interrupt flag register (EXTINT - 0xE01F C140)” and Section 26–4.2), a wakeupof this type, without any apparent cause, can be assumed to be a Brown-Out that hasgone away.

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6. External interrupt inputs
The LPC2300 includes four External Interrupt Inputs as selectable pin functions. In
addition, external interrupts have the ability to wake up the CPU from Power down mode.
This is controlled by the register INTWAKE, which is described in the Clocking and Power
Control chapter under the Power Control heading

6.1 Register description
The external interrupt function has four registers associated with it. The EXTINT registercontains the interrupt flags. The EXTMODE and EXTPOLAR registers specify the leveland edge sensitivity parameters.
Table 12.

External Interrupt registers

Name

Description

Access Reset
Addressvalue[1]EXTINT

The External Interrupt Flag Register contains
interrupt flags for EINT0, EINT1, EINT2 andEINT3. See Table 3–13.

R/W

0x00

0xE01F C140

EXTMODEThe External Interrupt Mode Register controls
whether each pin is edge- or level-sensitive.
See Table 3–14.

R/W

0x00

0xE01F C148

EXTPOLAR

The External Interrupt Polarity Register controls R/Wwhich level or edge on each pin will cause aninterrupt. See Table 3–15.

0x00

0xE01F C14C

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

6.2 External Interrupt flag register (EXTINT - 0xE01F C140)
When a pin is selected for its external interrupt function, the level or edge on that pin(selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag inthis register. This asserts the corresponding interrupt request to the VIC, which will cause
an interrupt if interrupts from the pin are enabled.
Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding
bits. In level-sensitive mode the interrupt is cleared only when the pin is in its inactive
state.
Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling
wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise
event that was just triggered by activity on the EINT pin will not be recognized in future.
Important: whenever a change of external interrupt operating mode (i.e. active
level/edge) is performed (including the initialization of an external interrupt),
corresponding bit in the EXTINT register must be cleared! For details see Section
3–6.3 “External Interrupt Mode register (EXTMODE - 0xE01F C148)” and Section 3–6.4“External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)”.
For example, if a system wakes up from power-down using low level on external interrupt
0 pin, its post-wakeup code must reset EINT0 bit in order to allow future entry into thepower-down mode. If EINT0 bit is left set to 1, subsequent attempt(s) to invoke
power-down mode will fail. The same goes for external interrupt handling.
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More details on power-down mode will be discussed in the following chapters.
Table 13.

External Interrupt Flag register (EXTINT - address 0xE01F C140) bit description

Bit

Symbol Description

0

EINT0

Reset
value

In level-sensitive mode, this bit is set if the EINT0 function is selected for its 0pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT0 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.[1]

1

EINT1

In level-sensitive mode, this bit is set if the EINT1 function is selected for its 0pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT1 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.[1]

2

EINT2

In level-sensitive mode, this bit is set if the EINT2 function is selected for its 0pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT2 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.[1]

3

EINT3

In level-sensitive mode, this bit is set if the EINT3 function is selected for its 0pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT3 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.[1]

7:4 [1]

Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.

NA

Example: e.g. if the EINTx is selected to be low level sensitive and low level is present on

corresponding pin, this bit can not be cleared; this bit can be cleared only when signal on thepin becomes high.

6.3 External Interrupt Mode register (EXTMODE - 0xE01F C148)
The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pinsthat are selected for the EINT function (see chapter Pin Connect Block on page 109) andenabled in the VICIntEnable register (Section 6–4.4 “Interrupt Enable Register(VICIntEnable - 0xFFFF F010)”) can cause interrupts from the External Interrupt function(though of course pins selected for other functions may cause interrupts from thosefunctions).
Note: Software should only change a bit in this register when its interrupt isdisabled in VICIntEnable, and should write the corresponding 1 to EXTINT before
enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could
be set by changing the mode and not having the EXTINT cleared.

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Table 14.

External Interrupt Mode register (EXTMODE - address 0xE01F C148) bit
description

Bit

SymbolValue

0

EXTMODE0 0
1

1

EXTMODE1 0
12

EXTMODE2 0
1

3
7:4

EXTMODE3 0-

Description

Reset
value

Level-sensitivity is selected for EINT0.

0

EINT0 is edge sensitive.
0

Level-sensitivity is selected for EINT1.
EINT1 is edge sensitive.

0

Level-sensitivity is selected for EINT2.
EINT2 is edge sensitive.

0

Level-sensitivity is selected for EINT3.

1

EINT3 is edge sensitive.

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

6.4 External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)
In level-sensitive mode, the bits in this register select whether the corresponding pin is
high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or
falling-edge sensitive. Only pins that are selected for the EINT function (see "Pin Connect
Block" chapter on page 109) and enabled in the VICIntEnable register (Section 6–4.4“Interrupt Enable Register (VICIntEnable - 0xFFFF F010)”) can cause interrupts from theExternal Interrupt function (though of course pins selected for other functions may causeinterrupts from those functions).
Note: Software should only change a bit in this register when its interrupt isdisabled in VICIntEnable, and should write the corresponding 1 to EXTINT before
enabling (initializing) or re-enabling the interrupt. An extraneous interrupt(s) could
be set by changing the polarity and not having the EXTINT cleared.
Table 15.

External Interrupt Polarity register (EXTPOLAR - address 0xE01F C14C) bit
description

Bit Symbol0

12

Value Description

EXTPOLAR0 0

EINT0 is low-active or falling-edge sensitive (depending on
EXTMODE0).

1

EINT0 is high-active or rising-edge sensitive (depending on
EXTMODE0).

EXTPOLAR1 0

EINT1 is low-active or falling-edge sensitive (depending on
EXTMODE1).

1

EINT1 is high-active or rising-edge sensitive (depending on
EXTMODE1).

EXTPOLAR2 0

EINT2 is low-active or falling-edge sensitive (depending on
EXTMODE2).

1

EINT2 is high-active or rising-edge sensitive (depending on
EXTMODE2).

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0

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Table 15.

External Interrupt Polarity register (EXTPOLAR - address 0xE01F C14C) bit
description

Bit Symbol
3

Value Description

Reset
value

EXTPOLAR3 0

EINT3 is low-active or falling-edge sensitive (depending on
EXTMODE3).

1

EINT3 is high-active or rising-edge sensitive (depending on
EXTMODE3).

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

7:4 -

0

NA

7. Other system controls and status flags
Some aspects of controlling LPC2300 operation that do not fit into peripheral or otherregisters are grouped here.

7.1 System Controls and Status register (SCS - 0xE01F C1A0)
Table 16.

System Controls and Status register (SCS - address 0xE01F C1A0) bit description

Bit

Symbol

0

GPIOM

1

EMC Reset
Disable[1]

2

-

3

MCIPWR
ActiveLevel[1]4

Value Description
GPIO access mode selection.
0

GPIO ports 0 and 1 are accessed via APB addresses in a fashioncompatible with previous LPC2000 devices.

1

High speed GPIO is enabled on ports 0 and 1, accessed via addresses in
the on-chip memory range. This mode includes the port masking featuredescribed in the GPIO chapter.
External Memory Controller Reset Disable.

0

R/W

0

Both EMC resets are asserted when any type of reset event occurs. In thismode, all registers and functions of the EMC are initialized upon any reset
condition.

1

Many portions of the EMC are only reset by a power-on or brown-out event,in order to allow the EMC to retain its state through a warm reset (external
reset or watchdog reset). If the EMC is configured correctly, auto-refresh canbe maintained through a warm reset.

-

Reserved. User software should not write ones to reserved bits. The value
read from a reserved bit is not defined.

NA

NA

MCIPWR pin control.

R/W

0

R/W

0

R/W

0

0

The MCIPWR pin is low.

1

The MCIPWR pin is high.

OSCRANGE

Main oscillator range select.
1

OSCEN

The frequency range of the main oscillator is 1 MHz to 20 MHz.
The frequency range of the main oscillator is 15 MHz to 24 MHz.
Main oscillator enable.

0

The main oscillator is disabled.

1

The main oscillator is enabled, and will start up if the correct external
circuitry is connected to the XTAL1 and XTAL2 pins.

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0
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Table 16.

System Controls and Status register (SCS - address 0xE01F C1A0) bit description

Bit

Symbol6

OSCSTAT

31:7 -[1]

Value Description

Access Reset
value

Main oscillator status.
0

The main oscillator is not ready to be used as a clock source.

1

The main oscillator is ready to be used as a clock source. The main
oscillator must be enabled via the OSCEN bit.

-Reserved. User software should not write ones to reserved bits. The value
read from a reserved bit is not defined.

RO

0

-

NA

The state of this bit is preserved through a software reset, and only a POR or a BOD event will reset it to its default value.

8. Code security vs. debugging
Applications in development typically need the debugging and tracing facilities in the
LPC2300. Later in the life cycle of an application, it may be more important to protect theapplication code from observation by hostile or competitive eyes. The following feature of
the LPC2300 allows an application to control whether it can be debugged or protectedfrom observation.
Details on the way Code Read Protection works can be found in "Flash Memory
Programming Hardware" chapter on page 517.
Table 17.

Code security register map

Name

Description

Access

Reset
value

Address

CPSR

Controls whether debugging features areenabled.

R/W

00xE01F C184

8.1 Code Security Protection Register (CSPR - 0xE01F C184)
Table 18.
Bit

Code Security Protection Register (CSPR - address 0xE01F C184) bit description

Symbol Description

31:0 CPSR

Reset
value

If the value 0x8765 4321 is written to this register within the first 256 clocks 0of execution of the Boot Code, the debugging features of the LPC2300 will
be disabled, making the application code in Flash memory secure fromobservation. If that value is not written to this register within that time
period, debugging features will be enabled.
If the Boot Code detects a valid checksum in Flash (see the Boot Codedescription in the Flash Memory Programming Firmware chapter), it willaccess the contents of the word at Flash address 0x0000 01FC and writethat value to this register. Thus, if the application contains the value
0x8765 4321 at address 0x0000 01FC, debugging will be disabled andthus the code in Flash will be protected from observation.

9. AHB configuration
The AHB Configuration Registers allows changing AHB scheduling and arbitration
strategies.

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Table 19.

AHB configuration register map

Name

Description

AccessReset Address
value

AHBCFG1 Configures the AHB1 arbiter.

R/W

00xE01F C188

AHBCFG2 Configures the AHB2 arbiter.

R/W

00xE01F C18C

9.1 AHB Arbiter Configuration register 1 (AHBCFG1 - 0xE01F C188)
Table 20.

AHB Arbiter Configuration register 1 (AHBCFG1 - address 0xE01F C188) bit
description

Bit

SymbolValue Description

Reset
value

0

scheduler00

1

Uniform (round-robin) scheduling.

2:1

break_burst

00

Break all defined length bursts (the CPU does not create
defined bursts).

01

Break all defined length bursts greater than four-beat.

10

Break all defined length bursts greater than eight-beat.

11

Never break defined length bursts.

0

A quantum is an AHB clock.

1

A quantum is an AHB bus cycle.

3
7:4

quantum_type
quantum_size

Priority scheduling.

1

Controls the type of arbitration and the number of quanta
before re-arbitration occurs.
0000

Preemptive, re-arbitrate after 1 AHB quantum.

0001

Preemptive, re-arbitrate after 2 AHB quanta.

0010

Preemptive, re-arbitrate after 4 AHB quanta.

0011

Preemptive, re-arbitrate after 8 AHB quanta.

0100

Preemptive, re-arbitrate after 16 AHB quanta.

0101

Preemptive, re-arbitrate after 32 AHB quanta.

0110

Preemptive, re-arbitrate after 64 AHB quanta.

0111

Preemptive, re-arbitrate after 128 AHB quanta.

1000

Preemptive, re-arbitrate after 256 AHB quanta.

1001

Preemptive, re-arbitrate after 512 AHB quanta.

1010

Preemptive, re-arbitrate after 1024 AHB quanta.

1011

Preemptive, re-arbitrate after 2048 AHB quanta.

1100

Preemptive, re-arbitrate after 4096 AHB quanta.

1101

Preemptive, re-arbitrate after 8192 AHB quanta.

1110

Preemptive, re-arbitrate after 16384 AHB quanta.

1111

Non- preemptive, infinite AHB quanta.

0001

Master 1 (CPU) is the default master.

0001

15:12 EP1

0010

External priority for master 1 (CPU) is tbd.

tbd

19:16 EP2

0001

External priority for master 2 (AHB1) is tbd.

tbd

11:8

default_master

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Table 20.
Bit

AHB Arbiter Configuration register 1 (AHBCFG1 - address 0xE01F C188) bit
description

SymbolValue Description

Reset
value

23:20 EP3

nnnn

External priority for master 3 (USB) is tbd.

tbd

27:24 EP4

nnnn

External priority for master 4 (GPDMA) is tbd.

tbd

31:28 --

Reserved. User software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

9.2 AHB Arbiter Configuration register 2 (AHBCFG2 - 0xE01F C18C)
Table 21.

AHB Arbiter Configuration register 2 (AHBCFG2 - address 0xE01F C18C) bit
description

Bit

SymbolValue Description

Reset
value

0

scheduler

0

Priority scheduling.

0

1

Uniform (round-robin) scheduling.

00

Break all defined length bursts (the CPU does not create
defined bursts).

01

Break all defined length bursts greater than four-beat.

10

Break all defined length bursts greater than eight-beat.

11

Never break defined length bursts.

2:1

3
7:4

11:8

break_burst

quantum_type

0

A quantum is an AHB clock.

1

A quantum is an AHB bus cycle.

quantum_size

default_master1

Controls the type of arbitration and the number of quanta tbd
before re-arbitration occurs.
0000

Preemptive, re-arbitrate after 1 AHB quantum.

0001

Preemptive, re-arbitrate after 2 AHB quanta.

0010

Preemptive, re-arbitrate after 4 AHB quanta.

0011

Preemptive, re-arbitrate after 8 AHB quanta.

0100

Preemptive, re-arbitrate after 16 AHB quanta.

0101

Preemptive, re-arbitrate after 32 AHB quanta.

0110

Preemptive, re-arbitrate after 64 AHB quanta.

0111

Preemptive, re-arbitrate after 128 AHB quanta.

1000

Preemptive, re-arbitrate after 256 AHB quanta.

1001

Preemptive, re-arbitrate after 512 AHB quanta.

1010

Preemptive, re-arbitrate after 1024 AHB quanta.

1011

Preemptive, re-arbitrate after 2048 AHB quanta.

1100

Preemptive, re-arbitrate after 4096 AHB quanta.

1101

Preemptive, re-arbitrate after 8192 AHB quanta.

1110

Preemptive, re-arbitrate after 16384 AHB quanta.

1111

Non- preemptive, infinite AHB quanta.

0010

Master 2 (Ethernet) is the default master.

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Table 21.
Bit

AHB Arbiter Configuration register 2 (AHBCFG2 - address 0xE01F C18C) bit
description

SymbolValue Description

Reset
value

15:12 EP1

0010

External priority for master 1 (CPU) is tbd.

tbd

19:16 EP2

0001

External priority for master 2 (Ethernet) is tbd.

tbd

31:20 --

Reserved. User software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

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Chapter 4: Clocking and power control
Rev. 01 — 6 July 2007

User manual

1. Summary of clocking and power control functions
This section describes the generation of the various clocks needed by the LPC2300 andoptions of clock source selection, as well as power control and wakeup from reduced
power modes. Functions described in the following subsections include:• Oscillators• Clock Source Selection• PLL• Clock Dividers• APB Divider• Power Control• Wakeup Timer

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EXTERNALETHERNET
PHY
usbclk
(48 MHz)USB
CLOCK
DIVIDERMAIN
OSCILLATORPLLINTERNAL
RC
OSCILLATOR

cclk

CPU
CLOCK
DIVIDER

BYPASSSYNCHRONIZER

25 or
50 MHzUSB clock config(USBCLKCFG)

pllclksystemclock
select(CLKSRCSEL)

USB BLOCKCPU clock config(CCLKCFG)

ARM7
TDMI-SETHERNET
BLOCK
EMC, DMA,FAST I/O
VIC

WATCHDOG
TIMER
WDT
clock
select(WDTCLKSEL)

CCLK/8PERIPHERAL
CLOCK
GENERATOR

CCLK/6
CCLK/4
CCLK/2other peripherals
see PCLKSEL0/1

CCLK

pclkWDT

CAN1
pclkCAN1PCLK
SEL0[1:0]

RTC
PRESCALER
rtclk

RTC
OSCILLATOR
RTC
clock
select(CCR)

REAL-TIME
CLOCK

2 kB BATTERYRAM

PCLK PCONP[13]
SEL0[27:26]

pclkRTC

PCONP[9] PCLKSEL0[19:18]
MCI(1)

pclkBAT_RAM

pclkMCI
PCLK
SEL1[1:0]
PCLK PCONP[28]
SEL1[25:24]
SYSTEM
CTRL
pclkSYSCON

PCLK
SEL1[29:28](1) LPC2368 and LPC2378 only

Fig 9. Clock generation for the LPC2300
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2. Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
Table 22.

Summary of system control registers

Name

Description

AccessReset value Address

R/W

00xE01F C10CClock source selection
CLKSRCSEL

Clock Source Select Register

Phase Locked Loop
PLLCONPLL Control Register

R/W

00xE01F C080

PLLCFGPLL Configuration Register

R/W

00xE01F C084

PLLSTATPLL Status RegisterRO

0

0xE01F C088

PLLFEED

PLL Feed Register

WO

NA

0xE01F C08CCPU Clock Configuration Register

R/W

00xE01F C104

Clock dividers
CCLKCFG
USBCLKCFG

USB Clock Configuration Register

R/W

00xE01F C108

IRCTRIMIRC Trim Register

R/W

0xA0

0xE01FC1A4

PCLKSEL0

Peripheral Clock Selection register 0.

R/W

00xE01F C1A8PCLKSEL1

Peripheral Clock Selection register 1.

R/W

00xE01F C1ACPCONPower Control Register

R/W

00xE01F C0C0

INTWAKEInterrupt Wakeup Register

R/W

00xE01F C144

PCONPPower Control for Peripherals Register

R/W

0x03BE0xE01F C0C4

Power control

3. Oscillators
The LPC2300 includes three independent oscillators. These are the Main Oscillator, theInternal RC Oscillator, and the RTC oscillator. Each oscillator can be used for more than
one purpose as required in a particular application.
Following Reset, the LPC2300 will operate from the Internal RC Oscillator until switchedby software. This allows systems to operate without any external crystal, and allows the
Boot Loader code to operate at a known frequency. When Boot Block will branch to a user
program, there could be an option to activate the main oscillator prior to entering usercode.

3.1 Internal RC oscillator
The Internal RC Oscillator (IRC) may be used as the clock source for the watchdog timer,
and/or as the clock that drives the PLL and subsequently the CPU. The precision of the
IRC does not allow for use of the USB interface, which requires a much more precise timebase. The nominal IRC frequency is 4 MHz.
Upon power up or any chip reset, the LPC2300 uses the IRC as the clock source.
Software may later switch to one of the other available clock sources.

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3.2 Main oscillator
The main oscillator can be used as the clock source for the CPU, with or without using the
PLL. The main oscillator operates at frequencies of 1 MHz to 24 MHz. This frequency canbe boosted to a higher frequency, up to the maximum CPU operating frequency, by the
PLL. The oscillator output is called OSCCLK. The clock selected as the PLL input is
PLLCLKIN and the ARM processor clock frequency is referred to as CCLK for purposes ofrate equations, etc. elsewhere in this document. The frequencies of PLLCLKIN and CCLK
are the same value unless the PLL is active and connected. Refer to the PLL description
in this chapter for details.
Since chip operation always begins using the Internal RC Oscillator, and the main
oscillator may never be used in some applications, it will only be started by software
request. This is accomplished by setting the OSCEN bit in the SCS register, as describedin the System Control Block chapter. The main oscillator provides a status flag (theOSCSTAT bit in the SCS register) so that software can determine when the oscillator is
running and stable. At that point, software can control switching to the main oscillator as aclock source. Prior to starting the main oscillator, a frequency range must be selected byconfiguring the OSCRANGE bit in the SCS register.

3.3 RTC oscillator
The RTC oscillator can be used as the clock source for the RTC, and/or the watchdog
timer. Also, the RTC oscillator can be used to drive the PLL and the CPU.

4. Clock source selection multiplexer
Several clock sources may be chosen to drive the PLL and ultimately the CPU andon-chip peripheral devices. The clock sources available are the main oscillator, the RTC
oscillator, and the Internal RC oscillator.
The clock source selection can only be changed safely when the PLL is not connected.
For a detailed description of how to change the clock source in a system using the PLL
see Section 4–5.14 “PLL setup sequence”.

4.1 Clock Source Select register (CLKSRCSEL - 0xE01F C10C)
The PCLKSRCSEL register contains the bits that select the clock source for the PLL.

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Table 23.

Clock Source Select register (CLKSRCSEL - address 0xE01F C10C) bit
description

Bit Symbol

Value Description

1:0 CLKSRC

Reset
value

Selects the clock source for the PLL as follows:

000

Selects the Internal RC oscillator as the PLL clock source(default).

01

Selects the main oscillator as the PLL clock source.

10

Selects the RTC oscillator as the PLL clock source.

11

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

Warning: Improper setting of this value, or an incorrect sequence ofchanging this value may result in incorrect operation of the device.
7:2 -

0

Unused, always 0.

0

5. PLL (Phase Locked Loop)
The PLL accepts an input clock frequency in the range of 32 kHz to 50 MHz . The input
frequency is multiplied up to a high frequency, then divided down to provide the actual
clock used by the CPU and the USB block.

5.1 PLL operation
The PLL input, in the range of 32 kHZ to 50 MHz, may initially be divided down by a value"N", which may be in the range of 1 to 256. This input division provides a greater numberof possibilities in providing a wide range of output frequencies from the same input
frequency.
Following the PLL input divider is the PLL multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value "M", in therange of 1 through 32768. The resulting frequency must be in the range of 275 MHz to550 MHz. The multiplier works by dividing the CCO output by the value of M, then using aphase-frequency detector to compare the divided CCO output to the multiplier input. The
error value is used to adjust the CCO frequency.
There are additional dividers at the PLL output to bring the frequency down to what isneeded for the CPU, USB, and other peripherals. The PLL output dividers are describedin the Clock Dividers section following the PLL description. A block diagram of the PLL isshown in Figure 4–10
PLL activation is controlled via the PLLCON register. The PLL multiplier and divider
values are controlled by the PLLCFG register. These two registers are protected in orderto prevent accidental alteration of PLL parameters or deactivation of the PLL. Since allchip operations, including the Watchdog Timer, could be dependent on the PLL if so
configured (for example when it is providing the chip clock), accidental changes to the PLL
setup could result in unexpected or fatal behavior of the microcontroller. The protection isaccomplished by a feed sequence similar to that of the Watchdog Timer. Details areprovided in the description of the PLLFEED register.
The PLL is turned off and bypassed following a chip Reset and by entering power Down
mode. PLL is enabled by software only.
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It is important that the setup procedure described in Section 4–5.14 “PLL setup sequence”
is followed as is or the PLL might not operate at all!.

5.2 PLL and startup/boot code interaction
The boot code for the LPC2300 is a little different from those for the previous NXP ARM7
LPC2000 chips. When there's no valid code (determined by the checksum word) in theuser flash or the ISP enable pin (P2.10) is pulled low on startup, the ISP mode will beentered and the boot code will setup the PLL with the IRC. Therefore it can not beassumed that the PLL is disabled when the user opens a debug session to debug theapplication code. The user startup code must follow the steps described in this chapter todisconnect the PLL.
The boot code may also change the values for some registers when the chip enters ISP
mode. For example, the GPIOM bit in the SCS register is set in the ISP mode. If the user
doesn't notice it and clears the GPIOM bit in the application code, the application code will
not be able to operate with the traditional GPIO function on PORT0 and PORT1.

5.3 Register description
The PLL is controlled by the registers shown in Table 4–24. More detailed descriptions
follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic
zero.
Warning: Improper setting of PLL values may result in incorrect operation of thedevice!
Table 24.

PLL registers

Name

Description

PLLCONPLL Control Register. Holding register for
R/W
updating PLL control bits. Values written to thisregister do not take effect until a valid PLL feed
sequence has taken place.

00xE01F C080

PLLCFGPLL Configuration Register. Holding register for R/W
updating PLL configuration values. Values
written to this register do not take effect until avalid PLL feed sequence has taken place.

00xE01F C084

PLLSTATPLL Status Register. Read-back register forRO
PLL control and configuration information. If
PLLCON or PLLCFG have been written to, but
a PLL feed sequence has not yet occurred, they
will not reflect the current PLL state. Reading
this register provides the actual values
controlling the PLL, as well as the PLL status.

00xE01F C088

PLLFEED

PLL Feed Register. This register enables
WO
loading of the PLL control and configuration
information from the PLLCON and PLLCFG
registers into the shadow registers that actuallyaffect PLL operation.

NA

0xE01F C08C

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

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USBSEL[3:0]

PLLC
PLLE
PLOCK
pd
refclkpllclkin

N-DIVIDER
NSEL
[7:0]

PHASEFREQUENCYDETECTORFILTER

M-DIVIDER/2

CCO

sysclkUSB
CLOCK
DIVIDER

usbclkCPU
CLOCK
DIVIDER

cclk

CCLKSEL[7:0]

MSEL[14:0]

Fig 10. PLL block diagram

5.4 PLL Control register (PLLCON - 0xE01F C080)
The PLLCON register contains the bits that enable and connect the PLL. Enabling the
PLL allows it to attempt to lock to the current settings of the multiplier and divider values.
Connecting the PLL causes the processor and all chip functions to run from the PLL
output clock. Changes to the PLLCON register do not take effect until a correct PLL feed
sequence has been given (see Section 4–5.9 “PLL Feed register (PLLFEED 0xE01F C08C)”).
Table 25.

PLL Control register (PLLCON - address 0xE01F C080) bit description

Bit

SymbolDescription

Reset
value

0

PLLE

0
PLL Enable. When one, and after a valid PLL feed, this bit will
activate the PLL and allow it to lock to the requested frequency. See
PLLSTAT register, Table 4–28.

1

PLLC

PLL Connect. Having both PLLC and PLLE set to one followed by avalid PLL feed sequence, the PLL becomes the clock source for theCPU, as well as the USB subsystem and. Otherwise, the clock
selected by the Clock Source Selection Multiplexer is used directlyby the LPC2300. See PLLSTAT register, Table 4–28.

0

7:2

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

The PLL must be set up, enabled, and Lock established before it may be used as a clock
source. When switching from the oscillator clock to the PLL output or vice versa, internal
circuitry synchronizes the operation in order to ensure that glitches are not generated.
Hardware does not insure that the PLL is locked before it is connected or automaticallydisconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it islikely that the oscillator clock has become unstable and disconnecting the PLL will not
remedy the situation.

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5.5 PLL Configuration register (PLLCFG - 0xE01F C084)
The PLLCFG register contains the PLL multiplier and divider values. Changes to the
PLLCFG register do not take effect until a correct PLL feed sequence has been given (seeSection 4–5.9 “PLL Feed register (PLLFEED - 0xE01F C08C)”). Calculations for the PLL
frequency, and multiplier and divider values are found in the Section 4–5.11 “PLL
frequency calculation”.
Table 26.

PLL Configuration register (PLLCFG - address 0xE01F C084) bit description

Bit

SymbolDescription

Reset
value

14:0

MSEL

PLL Multiplier value. Supplies the value "M" in the PLL frequency
calculations. The value stored here is M - 1. Supported values for M
are 6 through 512 and those listed in Table 4–27

0Note: Not all values of M are needed, and therefore some are notsupported by hardware. For details on selecting values for MSEL see
Section 4–5.11 “PLL frequency calculation”.
15-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

23:16 NSELPLL Pre-Divider value. Supplies the value "N" in the PLL frequency
calculations. Supported values for N are 1 through 32.

0Note: For details on selecting the right value for NSEL see Section
4–5.11 “PLL frequency calculation”.
31:24 -

Table 27.

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Multiplier values for 32 kHz oscillator

Multiplier (M)Pre-divide (N)

FCCO

4272

1

279.96984395

1

288.03074578

1

300.02384725

1

309.6576

4807

1

315.03165127

1

336.0031

5188

1

340.0008

5400

1

353.89445493

1359.9892

5859

1

383.97546042

1395.9685

6075

1

398.13126104

1

400.03176409

1420.0202

6592

1

432.01336750

1442.3680

6836

1448.0041

6866

1

449.97026958

1455.9995

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Table 27.

Multiplier values for 32 kHz oscillator

Multiplier (M)Pre-divide (N)

FCCO

7050

1

462.02887324

1

479.98577425

1

486.60487690

1503.9718

7813

1

512.03287935

1

520.02828057

1528.02368100

1530.84168545

2280.00268789

2

287.9980

9155

2

299.9910

9613

2314.9988

10254

2

336.0031

10376

2340.000810986

2

359.989211719

2

384.008212085

2396.0013

12207

2399.9990

12817

2419.9875

12817

3279.991613184

2432.013313184

3288.008913672

2448.004113733

2450.002913733

3300.002013916

2455.999514099

2461.9960

14420

3315.009714648

2

479.985715381

2504.004615381

3

336.0031

15564

3

340.000815625

2

512.000015869

2519.9954

16113

2527.9908

16479

3359.9892

17578

3

383.9973

18127

3

395.9904

18311

3400.0099

19226

3

419.9984

19775

3

431.9915

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Table 27.

Multiplier values for 32 kHz oscillator

Multiplier (M)Pre-divide (N)

FCCO

20508

3

448.004120599

3449.9920

20874

3455.999521149

3462.0070

21973

3480.007523071

3

503.993723438

3512.010923804

3

520.006324170

3528.0017

5.6 PLL Status register (PLLSTAT - 0xE01F C088)
The read-only PLLSTAT register provides the actual PLL parameters that are in effect at
the time it is read, as well as the PLL status. PLLSTAT may disagree with values found in
PLLCON and PLLCFG because changes to those registers do not take effect until aproper PLL feed has occurred (see Section 4–5.9 “PLL Feed register (PLLFEED 0xE01F C08C)”).
Table 28.

PLL Status register (PLLSTAT - address 0xE01F C088) bit description

Bit

SymbolDescription

Reset
value

14:0

MSEL

Read-back for the PLL Multiplier value. This is the value currently
used by the PLL, and is one less than the actual multiplier.

0

15

-

Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.

23:16 NSEL

Read-back for the PLL Pre-Divider value. This is the value currently 0
used by the PLL, and is one less than the actual divider.

24

PLLE

Read-back for the PLL Enable bit. When one, the PLL is currently 0
activated. When zero, the PLL is turned off. This bit is automatically
cleared when Power Down mode is activated.

25

PLLC

Read-back for the PLL Connect bit. When PLLC and PLLE are both 0
one, the PLL is connected as the clock source for the LPC2300.
When either PLLC or PLLE is zero, the PLL is bypassed. This bit isautomatically cleared when Power Down mode is activated.

26

PLOCK

Reflects the PLL Lock status. When zero, the PLL is not locked.
When one, the PLL is locked onto the requested frequency. See
text for details.

31:27 -

0Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.

5.7 PLL Interrupt: PLOCK
The PLOCK bit in the PLLSTAT register reflects the lock status of the PLL. When the PLL
is enabled, or parameters are changed, the PLL requires some time to establish lockunder the new conditions. PLOCK can be monitored to determine when the PLL may beconnected for use. The value of PLOCK may not be stable when the PLL reference
frequency (FREF, the frequency of REFCLK, which is equal to the PLL input frequency
divided by the pre-divider value) is less than 100 kHz or greater than 20 MHz. In these
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cases, the PLL may be assumed to be stable after a start-up time has passed. This time is
500 μs when FREF is greater than 400 kHz and 200 / FREF seconds when FREF is lessthan 400 kHz
PLOCK is connected to the interrupt controller. This allows for software to turn on the PLL
and continue with other functions without having to wait for the PLL to achieve lock. Whenthe interrupt occurs, the PLL may be connected, and the interrupt disabled.

5.8 PLL Modes
The combinations of PLLE and PLLC are shown in Table 4–29.
Table 29.

PLL control bit combinations

PLLC

PLLE

PLL Function00

PLL is turned off and disconnected. The PLL outputs the unmodified clock
input.

0

1

The PLL is active, but not yet connected. The PLL can be connected after
PLOCK is asserted.

10

Same as 00 combination. This prevents the possibility of the PLL being
connected without also being enabled.

1

1

The PLL is active and has been connected as the system clock source.

5.9 PLL Feed register (PLLFEED - 0xE01F C08C)
A correct feed sequence must be written to the PLLFEED register in order for changes to
the PLLCON and PLLCFG registers to take effect. The feed sequence is:
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
The two writes must be in the correct sequence, and must be consecutive APB bus
cycles. The latter requirement implies that interrupts must be disabled for the duration of
the PLL feed operation. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not
become effective.
Table 30.

PLL Feed register (PLLFEED - address 0xE01F C08C) bit description

Bit

SymbolDescription

Reset
value

7:0

PLLFEED

The PLL feed sequence must be written to this register in order for
PLL configuration and control register changes to take effect.

0x00

5.10 PLL and Power down mode
Power Down mode automatically turns off and disconnects the PLL. Wakeup from Power
Down mode does not automatically restore the PLL settings, this must be done insoftware. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL
can be called at the beginning of any interrupt service routine that might be called due tothe wakeup. It is important not to attempt to restart the PLL by simply feeding it when
execution resumes after a wakeup from Power Down mode. This would enable andconnect the PLL at the same time, before PLL lock is established.

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5.11 PLL frequency calculation
The PLL equations use the following parameters:
Table 31.

PLL frequency parameter

Parameter

Description

FIN

the frequency of PLLCLKIN from the Clock Source Selection Multiplexer.

FCCO

the frequency of the SYSCLK (output of the PLL Current Controlled Oscillator)N

PLL Pre-divider value from the NSEL bits in the PLLCFG register (PLLCFGNSEL field + 1). N is an integer from 1 through 32.

M

PLL Multiplier value from the MSEL bits in the PLLCFG register (PLLCFG
MSEL field + 1). Not all potential values are supported. See below.

FREF

PLL internal reference frequency, FIN divided by N.

The PLL output frequency (when the PLL is both active and connected) is given by:
FCCO = (2 × M × FIN) / N
The PLL inputs and settings must meet the following:• FIN is in the range of 32 kHz to 50 MHz.
• FCCO is in the range of 275 MHz to 550 MHz.
The PLL equation can be solved for other PLL parameters:
M = (FCCO × N) / (2 × FIN)
N = (2 × M × FIN) / FCCOFIN = (FCCO × N) / (2 × M)
Allowed values for M:
At higher oscillator frequencies, in the MHz range, values of M from 6 through 512 areallowed. This supports the entire useful range of both the main oscillator and the IRC.
For lower frequencies, specifically when the RTC is used to clock the PLL, a set of 65
additional M values have been selected for supporting baud rate generation, CAN/USB
operation, and attaining even MHz frequencies. These values are shown in Table 4–32
Table 32.

Additional Multiplier Values for use with a Low Frequency Clock Input
Low Frequency PLL Multipliers

4272

4395

4578

4725

4807

5127

5188

5400

5493

5859

6042

6075

6104

6409

6592

6750

6836

6866

6958

7050

7324

7425

7690

7813

7935

8057

8100

8545

8789

9155

9613

10254

10376

10986

11719

12085

12207

12817

13184

13672

13733

13916

14099

14420

14648

15381

15564

15625

15869

16113

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Table 32.

Additional Multiplier Values for use with a Low Frequency Clock Input
Low Frequency PLL Multipliers

16479

17578

18127

18311

19226

19775

20508

20599

20874

21149

21973

23071

23438

23804

24170

5.12 Procedure for determining PLL settings
PLL parameter determination can be simplified by using a spreadsheet available from
NXP. To determine PLL parameters by hand, the following general procedure may beused:
1. Determine if the application requires use of the USB interface. The USB requires a
50% duty cycle clock of 48 MHz within a very small tolerance, which means that FCCO
must be an even integer multiple of 48 MHz (i.e. an integer multiple of 96 MHz), withina very small tolerance.
2. Choose the desired processor operating frequency (CCLK). This may be based onprocessor throughput requirements, need to support a specific set of UART baudrates, etc. Bear in mind that peripheral devices may be running from a lower clock
frequency than that of the processor (see Section 4–6 “Clock dividers” on page 47
and Section 4–7 “Power control” on page 51). Find a value for FCCO that is close to a
multiple of the desired CCLK frequency, bearing in mind the requirement for USB
support in [1] above, and that lower values of FCCO result in lower power dissipation.
3. Choose a value for the PLL input frequency (FIN). This can be a clock obtained fromthe main oscillator, the RTC oscillator, or the on-chip RC oscillator. For USB support,
the main oscillator should be used.
4. Calculate values for M and N to produce a sufficiently accurate FCCO frequency. The
desired M value -1 will be written to the MSEL field in PLLCFG. The desired N value -1
will be written to the NSEL field in PLLCFG.
In general, it is better to use a smaller value for N, to reduce the level of multiplication thatmust be accomplished by the CCO. Due to the difficulty in finding the best values in somecases, it is recommended to use a spreadsheet or similar method to show many
possibilities at once, from which an overall best choice may be selected. A spreadsheet isavailable from NXP for this purpose.

5.13 Examples of PLL settings
The following examples illustrate selecting PLL values based on different system
requirements.
Example 1)
Assumptions:• The USB interface will be used in the application. The lowest integer multiple of
96 MHz that falls within the PLL operating range (288 MHz) will be targeted.

• The desired CPU rate = 60 MHz.
• An external 4 MHz crystal or clock source will be used as the system clock source.
Calculations:
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M = (FCCO × N) / (2 × FIN)
Start by assuming N = 1, since this produces the smallest multiplier needed for the PLL.
So, M = 288 × 106 / (2 × 4 × 106) = 36. Since the result is an integer, there is no need tolook further for a good set of PLL configuration values. The value written to PLLCFG
would be 0x23 (N - 1 = 0; M - 1 = 35 = 0x23).
The potential CPU clock rate can be determined by dividing FCCO by the desired CPU
frequency: 288 × 106 / 60 × 106 = 4.8. The nearest integer value for the CPU Clock
Divider is then 5, giving us 57.6 MHz as the nearest value to the desired CPU clock rate.
If it is important to obtain exactly 60 MHz, an FCCO rate must be found that can be divided
down to both 48 MHz and 60 MHz. The only possibility is 480 MHz. Divided by 10, thisgives the 48 MHz with a 50% duty cycle needed by the USB block. Divided by 8, it gives
60 MHz for the CPU clock. PLL settings for 480 MHz are N = 1 and M = 60.
Example 2)
Assumptions:• The USB interface will not be used in the application.
• The desired CPU rate = 72 MHz• The 32.768 kHz RTC clock source will be used as the system clock source
Calculations:
M = (FCCO × N) / (2 × FIN)
The smallest frequency for FCCO that can produce our desired CPU clock rate and iswithin the PLL operating range is 288 MHz (4 × 72 MHz). Start by assuming N = 1, since
this produces the smallest multiplier needed for the PLL.
So, M = 288 × 106 / (2 × 32,768) = 4,394.53125. This is not an integer, so the CPU
frequency will not be exactly 288 MHz with this setting. Since this case is less obvious, it
may be useful to make a table of possibilities for different values of N (see Table 4–33).
Table 33.

Potential values for PLL example

NM

M Rounded FREF (Hz)FCCO (Hz)Actual
CCLK (Hz)% Error1

4394.53125

4395

32768

288.030772.00770.010728789.0625

8789

16384

287.9980

71.9995-0.0007313183.59375 13184

10922.67

288.0089

72.00220.0031

4

17578.125

8192

287.9980

71.9995-0.00075

21972.65625 21973

6553.6288.0045

72.00110.001617578

Beyond N = 7, the value of M is out of range or not supported, so the table stops there. In
the table, the calculated M value is rounded to the nearest integer. If this results in CCLK
being above the maximum operating frequency (72 MHz), it is allowed if it is not more than½% above the maximum frequency.

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In general, larger vlaues of FREF result in a more stable PLL when the input clock is a low
frequency. Even the first table entry shows a very small error of just over 1 hundredth of apercent, or 107 parts per million (ppm). If that is not accurate enough in the application,
the second case gives a much smaller error of 7 ppm.
Remember that when a frequency below about 1 MHz is used as the PLL clock source,
not all multiplier values are available. As it turns out, all of the rounded M values found in
Table 4–33 of this exmaple are supported, as may be confirmed in Table 4–32.
If PLL calculations suggest use of unsupported multiplier values, those values must be
disregarded and other values examined to find the best fit. Multiplier values one count off
from calculated values may also be good possibilities..
The value written to PLLCFG for the second table entry would be 0x12254(N - 1 = 1 = 0x1; M - 1 = 8788 = 0x2254).

5.14 PLL setup sequence
The following sequence must be followed step by step in order to have the PLL initialized
an running:
1. Disconnect the PLL with one feed sequence if PLL is already connected.
2. Disable the PLL with one feed sequence.
3. Change the CPU Clock Divider setting to speed up operation without the PLL, if
desired.
4. Write to the Clock Source Selection Control register to change the clock source.
5. Write to the PLLCFG and make it effective with one feed sequence. The PLLCFG canonly be updated when the PLL is disabled.
6. Enable the PLL with one feed sequence.
7. Change the CPU Clock Divider setting for the operation with the PLL. It's critical to do
this before connecting the PLL.
8. Wait for the PLL to achieve lock by monitoring the PLOCK bit in the PLLSTAT register,or using the PLOCK interrupt, or wait for a fixed time when the input clock to PLL isslow (i.e. 32 kHz). The value of PLOCK may not be stable when the PLL reference
frequency (FREF, the frequency of REFCLK, which is equal to the PLL input
frequency divided by the pre-divider value) is less than 100 kHz or greater than
20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time
has passed. This time is 500 µs when FREF is greater than 400 kHz and 200 / FREF
seconds when FREF is less than 400 kHz.
9. Connect the PLL with one feed sequence.
It's very important not to merge any steps above. For example, don't update the PLLCFG
and enable the PLL simultaneously with the same feed sequence.

6. Clock dividers
The output of the PLL must be divided down for use by the CPU and the USB block.
Separate dividers are provided such that the CPU frequency can be determined
independently from the USB block, which always requires 48 MHz with a 50% duty cycle
for proper operation.
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USB clock
divider

PLLC
PLLE

USBSEL

usb
clk

PLOCK
pd
Fosc

PhaseFrequency
Detector

N-divider

Filter

CCO

hclk

CPU
clock
divider
CCLKSELNSEL[7:0]
M-dividercclk

individual
peripheral
clock
divider.
.
.

PCLKSEL/2

MSEL[15:0]

Fig 11. PLL and clock dividers

6.1 CPU Clock Configuration register (CCLKCFG - 0xE01F C104)
The CCLKCFG register controls the division of the PLL output before it is used by theCPU. When the PLL is bypassed, the division may be by 1. When the PLL is running, theoutput must be divided in order to bring the CPU clock frequency (CCLK) within operating
limits. An 8 bit divider allows a range of options, including slowing CPU operation to a low
rate for temporary power savings without turning off the PLL.
Note: when the USB interface is used in an application, CCLK must be at least 18 MHz inorder to support internal operations of the USB block.
Table 34.

CPU Clock Configuration register (CCLKCFG - address 0xE01F C104) bit
description

Bit Symbol

Description

Reset
value

7:0 CCLKSEL

Selects the divide value for creating the CPU clock (CCLK) from the 0x00
PLL output.
Only 0 and odd values (1, 3, 5, ..., 255) are supported and can beused when programming the CCLKSEL bits.
Warning: Using an even value (2, 4, 6, ..., 254) when setting the
CCLKSEL bits may result in incorrect operation of the device.

The CCLK is derived from the PLL output signal, divided by CCLKSEL + 1. Having
CCLKSEL = 1 results in CCLK being one half the PLL output, CCLKSEL = 3 results in
CCLK being one quarter of the PLL output, etc..

6.2 USB Clock Configuration register (USBCLKCFG - 0xE01F C108)
The USBCLKCFG register controls the division of the PLL output before it is used by theUSB block. If the PLL is bypassed, the division may be by 1. In that case, the PLL input
frequency must be 48 MHz, with a 500 ppm tolerance. When the PLL is running, theUM10211_1

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output must be divided in order to bring the USB clock frequency to 48 MHz with a 50%
duty cycle. A 4-bit divider allows obtaining the correct USB clock from any even multiple of48 MHz (i.e. any mutliple of 96 MHz) within the PLL operating range.
Table 35.

USB Clock Configuration register (USBCLKCFG - address 0xE01F C108) bit
description

Bit Symbol

Description

Reset
value

3:0 USBSEL

Selects the divide value for creating the USB clock from the PLL output. 0
Warning: Improper setting of this value will result in incorrect operationof the USB interface.

7:4 -Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

The USB clock is derived from the PLL output signal, divided by USBSEL + 1. Having
USBSEL = 1 results in USB’s clock being one half the PLL output.

6.3 IRC Trim Register (IRCTRIM - 0xE01F C1A4)
This register is used to trim the on - chip 4 MHz oscillator.
Table 36.

IRC Trim register (IRCTRIM - address 0xE01F C1A4) bit description

Bit

SymbolDescription

Reset
value

7:0

IRCtrim

IRC trim value. It controls the on-chip 4 MHz IRC frequency.

0xA0

15:8

-

Reserved. Software must write 0 into these bits.

NA

6.4 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 0xE01F C1A8 and PCLKSEL1 - 0xE01F C1AC)
A pair of bits in a Peripheral Clock Selection register controls the rate of the clock signalthat will be supplied to the corresponding peripheral as specified in Table 4–37,
Table 4–38 and Table 4–39. For details on the HCLK clock see Figure 4–11.
Table 37.

Peripheral Clock Selection register 0 (PCLKSEL0 - address 0xE01F C1A8) bit
description

Bit

SymbolDescription

Reset
value

1:0

PCLK_WDT

Peripheral clock selection for WDT.

00

3:2

PCLK_TIMER0

Peripheral clock selection for TIMER0.

00

5:4

PCLK_TIMER1

Peripheral clock selection for TIMER1.

00

7:6

PCLK_UART0

Peripheral clock selection for UART0.

00

9:8

PCLK_UART1

Peripheral clock selection for UART1.

00

11:10

-

Unused, always read as 0.

00

13:12

PCLK_PWM1

Peripheral clock selection for PWM1.

00

15:14

PCLK_I2C0

Peripheral clock selection for I2C0.

00

17:16

PCLK_SPI

Peripheral clock selection for SPI.

00

19:18

PCLK_RTC[1]Peripheral clock selection for RTC.

00

21:20

PCLK_SSP1

Peripheral clock selection for SSP1.

00

23:22

PCLK_DAC

Peripheral clock selection for DAC.

00

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Table 37.

Peripheral Clock Selection register 0 (PCLKSEL0 - address 0xE01F C1A8) bit
description

Bit

SymbolDescription

Reset
value

25:24

PCLK_ADC

Peripheral clock selection for ADC.

00

27:26

PCLK_CAN1

Peripheral clock selection for CAN1.

00

29:28

PCLK_CAN2

Peripheral clock selection for CAN2.

00

31:30

PCLK_ACF

Peripheral clock selection for CAN filtering.

00

[1]

For PCLK_RTC only, the value ’01’ is illegal. Do not write ’01’ to the PCLK_RTC. Attempting to write ’01’
results in the previous value being unchanged.

Table 38.

Peripheral Clock Selection register 1 (PCLKSEL1 - address 0xE01F C1AC) bit
description

Bit

SymbolDescription

Reset
value

1:0

PCLK_BAT_RAM

Peripheral clock selection for the battery supported RAM.

00

3:2

PCLK_GPIO

Peripheral clock selection for GPIOs.

00

5:4

PCLK_PCB

Peripheral clock selection for the Pin Connect block.

00

7:6

PCLK_I2C1

Peripheral clock selection for I2C1.

00

9:8

-

Unused, always read as 0.

00

11:10

PCLK_SSP0

Peripheral clock selection for SSP0.

00

13:12

PCLK_TIMER2

Peripheral clock selection for TIMER2.

00

15:14

PCLK_TIMER3

Peripheral clock selection for TIMER3.

00

17:16

PCLK_UART2

Peripheral clock selection for UART2.

00

19:18

PCLK_UART3

Peripheral clock selection for UART3.

00

21:20

PCLK_I2C2

Peripheral clock selection for I2C2.

00

23:22

PCLK_I2S

Peripheral clock selection for I2S.

00

25:24

PCLK_MCI

Peripheral clock selection for MCI.

00

27:26

-

Unused, always read as 0.

00

29:28

PCLK_SYSCON

Peripheral clock selection for the System Control block.

00

31:30

-

Unused, always read as 0.

00

Table 39.

Peripheral Clock Selection register bit values

PCLKSEL0 and PCLKSEL1 Function
individual peripheral’s clock
select options

Reset
value

00

PCLK_xyz = CCLK/40001

PCLK_xyz = CCLK[1]10

PCLK_xyz = CCLK/2

11

Peripheral’s clock is selected to PCLK_xyz = HCLK/8
except for CAN1, CAN2, and CAN filtering when ’11’
selects PCLK_xyz = HCLK/6.

[1]

For PCLK_RTC only, the value ’01’ is illegal. Do not write ’01’ to the PCLK_RTC. Attempting to write ’01’
results in the previous value being unchanged.

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7. Power control
The LPC2300 supports a variety of power control features. There are four special modesof processor power reduction: Idle mode, Sleep mode, and Power down. The CPU clock
rate may also be controlled as needed by changing clock sources, re-configuring PLL
values, and/or altering the CPU clock divider value. This allows a trade-off of power
versus processing speed based on application requirements. In addition, Peripheral
Power Control allows shutting down the clocks to individual on-chip peripherals, allowing
fine tuning of power consumption by eliminating all dynamic power use in any peripherals
that are not required for the application.
The LPC2300 also implements a separate power domain in order to allow turning off
power to the bulk of the device while maintaining operation of the Real Time Clock and asmall static RAM, referred to as the Battery RAM. This feature is described in more detaillater in this chapter under the heading Power Domains, and in the Real Time Clock andBattery RAM chapter.

7.1 Idle mode
When Idle mode is entered, the clock to the core is stopped. Resumption from the Idle
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generateinterrupts to cause the processor to resume execution. Idle mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internalbuses.

7.2 Sleep mode
When the chip enters the Sleep mode, the main oscillator is powered down and all clocks
are stopped. The output of the IRC is disabled but the IRC is not powered down for a fast
wakeup later. The 32 kHz RTC oscillator is not stopped because the RTC interrupts may
be used as the wakeup source. The Flash is left in the standby mode allowing a very quick
wakeup. The PLL is automatically turned off and disconnected. The CCLK and USBCLK
clock dividers automatically get reset to zero.
The processor state and registers, peripheral registers, and internal SRAM values arepreserved throughout Sleep mode and the logic levels of chip pins remain static. The
Sleep mode can be terminated and normal operation resumed by either a Reset or certain
specific interrupts that are able to function without clocks. Since all dynamic operation of
the chip is suspended, Sleep mode reduces chip power consumption to a very low value.
On the wakeup of sleep mode, if the IRC was used before entering sleep mode, the 2-bit
IRC timer starts counting and the code execution and peripherals activities will resume
after the timer expires (4 cycles). If the main external oscillator was used, the 12-bit main
oscillator timer starts counting and the code execution will resume when the timer expires(4096 cycles). Customer must not forget to re-configure the PLL and clock dividers after
the wakeup.

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7.3 Power Down mode
Power Down mode does everything that Sleep mode does, but also turns off the Flashmemory. This saves more power, but requires waiting for resumption of Flash operation
before execution of code or data access in the Flash memory can be accomplished.
When the chip enters power-down mode, the IRC, the main oscillator and all clocks are
stopped. The 32Khz RTC oscillator is not stopped because the RTC interrupts may be
used as the wakeup source. The flash is forced into power-down mode. The PLL is
automatically turned off and disconnected. The CCLK and USBCLK clock dividers
automatically get reset to zero.
On the wakeup of power-down mode, if the IRC was used before entering power-down
mode, after IRC-start-up time (60 μs), the 2-bit IRC timer starts counting and expires in 4
cycles. The code execution can then be resumed immediately upon the expiration of the
IRC timer if the code was running from SRAM. In the meantime, the Flash wakeup-timer
generates Flash start-up time 100 μs. When it times out, access to the Flash is enabled.
Customer must not forget to re-configure the PLL and clock dividers after the wakeup.

7.4 Peripheral power control
A Power Control for Peripherals feature allows individual peripherals to be turned off ifthey are not needed in the application, resulting in additional power savings. This isdetailed in the description of the PCONP register.

7.5 Register description
The Power Control function uses registers shown in Table 4–40. More detailed
descriptions follow.
Table 40.

Power Control registers

Name

Description

Access Reset
value[1]Address

PCON

Power Control Register. This registercontains control bits that enable the two
reduced power operating modes of the
LPC2300. See Table 4–41.

R/W

0x00

0xE01F C0C0

R/W

0x00

0xE01F C144

INTWAKE Interrupt Wakeup Register. Controls whichinterrupts will wake the LPC2300 frompower-down mode. See Table 4–43
PCONP

[1]

Power Control for Peripherals Register. This R/Wregister contains control bits that enable anddisable individual peripheral functions,allowing elimination of power consumption by
peripherals that are not needed.

0xE01F C0C4

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

7.6 Power Mode Control register (PCON - 0xE01F C0C0)
Reduced power modes are controlled via the PCON register, as described in Table 4–41.

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Table 41.

Power Mode Control register (PCON - address 0xE01F COCO) bit description

Bit

SymbolDescription

Reset
value

0

PM0 (IDL)

Power mode control bit 0. See text and table below for details.

01PM1 (PD)

Power mode control bit 1. See text and table below for details.

0

2

BODPDM

Brown-Out Power Down Mode. When BODPDM is 1, the Brown-Out0
Detect circuitry will turn off when chip Power Down mode is entered,resulting in a further reduction in power usage. However, the possibilityof using Brown-Out Detect as a wakeup source from Power Down mode
will be lost.
When 0, the Brown-Out Detect function remains active during Power
Down mode.
See the System Control Block chapter for details of Brown-Out
detection.

3

BOGD

Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detectcircuitry is fully disabled at all times, and does not consume power.

0

When 0, the Brown-Out Detect circuitry is enabled.
See the System Control Block chapter for details of Brown-Out
detection.
4

BORD

Brown-Out Reset Disable. When BORD is 1, the second stage of low
voltage detection (2.6 V) will not cause a chip reset.

0When BORD is 0, the reset is enabled. The first stage of low voltage
detection (2.9 V) Brown-Out interrupt is not affected.
See the System Control Block chapter for details of Brown-Out
detection.
6:3-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

7

PM2

Power mode control bit 2. See text and table below for details.

0

Encoding of Reduced Power Modes
The PM2, PM1, and PM0 bits in PCON allow entering reduced power modes as needed.
The encoding of these bits allows backward compatibility with devices that previously only
supported Idle and Power Down modes. Table 4–42 below shows the encoding for thefour reduced power modes supported by the LPC2300.
Table 42.

Encoding of reduced power modes

PM2, PM1, PM0 Description000

Normal operation

001

Idle mode. Causes the processor clock to be stopped, while on-chip peripherals
remain active. Any enabled interrupt from a peripheral or an external interrupt
source will cause the processor to resume execution. See text for details.

101

Sleep mode. This mode is similar to Power Down mode (the oscillator and all
on-chip clocks are stopped), but the Flash memory is left in Standby mode. This
allows a more rapid wakeup than Power Down mode because the Flashreference voltage regulator start-up time is not needed. See text for details.

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Table 42.

Encoding of reduced power modes

PM2, PM1, PM0 Description
010

Power Down mode. Causes the oscillator and all on-chip clocks to be stopped.
A wakeup condition from an external interrupt can cause the oscillator to
re-start, the PD bit to be cleared, and the processor to resume execution. See
text for details.

110

Reserved.

OthersReserved, not currently used.

7.7 Interrupt Wakeup Register (INTWAKE - 0xE01F C144)
Enable bits in the INTWAKE register allow the external interrupts to wake up theprocessor if it is in Power Down mode. The related EINTn function must be mapped to thepin in order for the wakeup process to take place. It is not necessary for the interrupt to beenabled in the Vectored Interrupt Controller for a wakeup to take place. This arrangement
allows additional capabilities, such as having an external interrupt input wake up theprocessor from Power Down mode without causing an interrupt (simply resuming
operation), or allowing an interrupt to be enabled during Power Down without waking theprocessor up if it is asserted (eliminating the need to disable the interrupt if the wakeupfeature is not desirable in the application). Details of the wakeup operations are shown in
Table 4–43.
For an external interrupt pin to be a source that would wake up the microcontroller fromPower-down mode, it is also necessary to clear the corresponding interrupt flag (seeSection 3–6.2 “External Interrupt flag register (EXTINT - 0xE01F C140)”).
Table 43.

Interrupt Wakeup register (INTWAKE - address 0xE01F C144) bit description

Bit

SymbolDescription

0

EXTWAKE0

When one, assertion of EINT0 will wake up the processor from 0
Power Down mode.

1

EXTWAKE1

When one, assertion of EINT1 will wake up the processor from 0
Power Down mode.

2

EXTWAKE2

When one, assertion of EINT2 will wake up the processor from 0
Power Down mode.

3

EXTWAKE3

When one, assertion of EINT3 will wake up the processor from 0
Power Down mode.

4

ETHWAKE

When one, assertion of the Wake-up on LAN interrupt(WakeupInt) of the Ethernet block will wake up the processor
from Power Down mode.

5

USBWAKE

When one, activity on the USB bus will wake up the processor 0
from Power Down mode. Any change of state on the USB data
pins will cause a wakeup when this bit is set. For details on therelationship of USB to Power Down Mode and wakeup, see therelevant USB chapter(s).

6

CANWAKE

When one, activity of the CAN bus will wake up the processor
from Power Down mode. Any change of state on the CAN
receive pins will cause a wakeup when this bit is set.

7

GPIOWAKE

When one, specified activity on GPIO pins enabled for wakeup 0
will wake up the processor from Power Down mode. See the
GPIO chapter for details.

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Reset
value

0

0

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Table 43.

Interrupt Wakeup register (INTWAKE - address 0xE01F C144) bit description

Bit

SymbolDescription

Reset
value

13:8

-

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

14

BODWAKE

When one, Brown-Out Detect interrupt will wake up theprocessor from Power Down mode.

0

Note: since there is a delay before execution begins, there is
no guarantee that execution will resume before VDD(3V3) has
fallen below the lower BOD threshold, which preventsexecution. If execution does resume, there is no guarantee of
how long the processor will continue execution before the lower
BOD threshold terminates execution. These issues depend on
the slope of the decline of VDD(3V3). High decoupling
capacitance (between VDD(3V3) and ground) in the vicinity of the
LPC2300 will improve the likelihood that software will be able todo what needs to be done when power is in the process of
being lost.
15

RTCWAKE

When one, assertion of an RTC interrupt will wake up theprocessor from Power Down mode.

0

7.8 Power Control for Peripherals register (PCONP - 0xE01F COC4)The PCONP register allows turning off selected peripheral functions for the purpose ofsaving power. This is accomplished by gating off the clock source to the specified
peripheral blocks. A few peripheral functions cannot be turned off (i.e. the Watchdog timer,
GPIO, the Pin Connect block, and the System Control block).
Some peripherals, particularly those that include analog functions, may consume powerthat is not clock dependent. These peripherals may contain a separate disable control thatturns off additional circuitry to reduce power. Information on peripheral specific powersaving features may be found in the chapter describing that peripheral.
Each bit in PCONP controls one peripheral as shown in Table 4–44. The bit numbers
correspond to the related peripheral number as shown in the APB peripheral map Table
2–4 “APB peripherals and base addresses” in the "LPC2300 Memory Addressing"chapter.
If a peripheral control bit is 1, that peripheral is enabled. If a peripheral bit is 0, thatperipheral’s clock is disabled (gated off) to conserve power. For example if bit 19 is 1, theI2C1 interface is enabled. If bit 19 is 0, the I2C1 interface is disabled.
Important: valid read from a peripheral register and valid write to a peripheral
register is possible only if that peripheral is enabled in the PCONP register!
Table 44.

Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit
description

Bit

SymbolDescription

Reset
value

0

-

Unused, always 0.

01

PCTIM0Timer/Counter 0 power/clock control bit.

1

2

PCTIM1

Timer/Counter 1 power/clock control bit.

1

3

PCUART0

UART0 power/clock control bit.

1

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Table 44.

Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit
description

Bit

SymbolDescription

Reset
value

4

PCUART1

UART1 power/clock control bit.

1

5

-

Unused, always 0.

1

6

PCPWM1PWM1power/clock control bit.

1

7

PCI2C0The I2C0 interface power/clock control bit.

1

8

PCSPI

The SPI interface power/clock control bit.

1

9

PCRTC

The RTC power/clock control bit.

1

10

PCSSP1The SSP 1 interface power/clock control bit.

1

11

PCEMC

External Memory Controller

1

12

PCAD

A/D converter (ADC) power/clock control bit.

0

Note: Clear the PDN bit in the AD0CR before clearing this bit, and set
this bit before setting PDN.
13

PCAN1

CAN Controller 1 power/clock control bit.

0

14

PCAN2

CAN Controller 2 power/clock control bit.

0

18:15 -

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

19

PCI2C1The I2C1 interface power/clock control bit.

1

20

-

Unused, always 0

0

21

PCSSP0The SSP0 interface power/clock control bit.

1

22

PCTIM2Timer 2 power/clock control bit.

023

PCTIM3Timer 3 power/clock control bit.

024

PCUART2

UART 2 power/clock control bit.

025

PCUART3

UART 3 power/clock control bit.

0

PCI2C2I2S interface 2 power/clock control bit.

1

27

PCI2S

I2S interface power/clock control bit.

0

28

PCSDC

SD card interface power/clock control bit.

029

PCGPDMA GP DMA function power/clock control bit.

030

PCENET

Ethernet block power/clock control bit.

0

31

PCUSB

USB interface power/clock control bit.

026

7.9 Power control usage notes
After every reset, the PCONP register contains the value that enables selected interfaces
and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper
configuring via peripheral dedicated registers, the user’s application might have to accessthe PCONP in order to start using some of the on-board peripherals.
Power saving oriented systems should have 1s in the PCONP register only in positions
that match peripherals really used in the application. All other bits, declared to be"Reserved" or dedicated to the peripherals not used in the current application, must be
cleared to 0.

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7.10 Power domains
The LPC2300 provides two independent power domains that allow the bulk of the device
to have power removed while maintaining operation of the Real Time Clock and theBattery RAM.
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation. Details may be found in the Real Time Clock and Battery RAM
chapter on page 503.
Note: The RTC and the battery RAM operate independently from each other. Therefore,
the battery RAM can be accessed at any time, regardless of whether the RTC is enabledor disabled via a dedicated bit in the PCONP register.

8. Wakeup timer
The LPC2300 begins operation at power-up and when awakened from Power-down modeby using the 4 MHz IRC oscillator as the clock source. This allows chip operation quickly
in these cases. If the main oscillator or the PLL is needed by the application, software willneed to enable these features and wait for them to stabilize before they are used as aclock source.
When the main oscillator is initially activated, the wakeup timer allows software to ensurethat the main oscillator is fully functional before the processor uses it as a clock sourceand starts to execute instructions. This is important at power on, all types of Reset, andwhenever any of the aforementioned functions are turned off for any reason. Since theoscillator and other functions are turned off during Power Down mode, any wakeup of theprocessor from Power Down mode makes use of the Wakeup Timer.
The Wakeup Timer monitors the crystal oscillator as the means of checking whether it issafe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD(3V3) ramp (in the case of power on), the type of
crystal and its electrical characteristics (if a quartz crystal is used), as well as any otherexternal circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the
existing ambient conditions.
Once a clock is detected, the Wakeup Timer counts a fixed number of clocks (4096), thensets the flag (OSCSTAT bit in the SCS register) that indicates that the main oscillator isready for use. Software can then switch to the main oscillator and, if needed, start the
PLL. Refer to the Main Oscillator description in this chapter for details.

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Chapter 5: External Memory Controller (EMC)
Rev. 01 — 6 July 2007

User manual

1. Introduction
The LPC2378 External Memory Controller (EMC) is an ARM PrimeCell™ MultiPort
Memory Controller peripheral offering support for asynchronous static memory devices
such as RAM, ROM and Flash. The EMC is an Advanced Microcontroller Bus Architecture(AMBA) compliant peripheral.

2. Features• Asynchronous static memory device support including RAM, ROM, and Flash, with orwithout asynchronous page mode.

• Low transaction latency.
• Read and write buffers to reduce latency and to improve performance.
• 8 bit bit wide static memory support.
• Can be used as an interface to some external I/O devices.
• Two chip selects for chip selects for static memory devices.

3. Functional overview
This chapter describes the major functional blocks of the EMC.

4. EMC functional description
Figure 5–12 shows a block diagram of the EMC.

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EMC

A[15:0]AHB BusAHB SLAVEMEMORYINTERFACEDATA
BUFFERSMEMORYCONTROLLERSTATE
MACHINE

PAD INTERFACE

D[7:0]AHB SLAVEREGISTERINTERFACE

sharedsignals

WE
BSL0
OE
staticmemorysignals
CS0, CS1

Fig 12. EMC block diagram

The functions of the EMC blocks are described in the following sections:• AHB slave register interface.
• AHB slave memory interfaces.
• Data buffers.
• Memory controller state machine.
• Pad interface.

5. AHB Slave register interface
The AHB slave register interface block enables the registers of the EMC to be
programmed. This module also contains most of the registers and performs the majority of
the register address decoding.
To eliminate the possibility of endianness problems, all data transfers to and from theregisters of the EMC must be 32 bits wide.
Note: If an access is attempted with a size other than a word (32 bits), it causes an
ERROR response to the AHB bus and the transfer is terminated.

5.1 AHB Slave memory interface
The AHB slave memory interface allows access to external memories.

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5.1.1 Memory transaction endianness
The endianness of the data transfers to and from the external memories is determined by
the Endian mode (N) bit in the EMCConfig Register.
Note: The memory controller must be idle (see the busy field of the EMCStatus Register)
before endianness is changed, so that the data is transferred correctly.

5.1.2 Memory transaction size
For the LPC23xx, memory transactions must be 8 bits wide. Any access attempted with asize greater than 8 bits causes an ERROR response to the AHB bus and the transfer isterminated.

5.1.3 Write protected memory areas
Write transactions to write-protected memory areas generate an ERROR response to the
AHB bus and the transfer is terminated.

5.2 Data buffers
The AHB interface reads and writes via buffers to improve memory bandwidth and reducetransaction latency. The EMC contains four 16-word buffers. The buffers can be used asread buffers, write buffers, or a combination of both. The buffers are allocatedautomatically.
They can be enabled or disabled for static memory using the EMCStaticConfig Registers.

5.2.1 Write buffers
Write buffers are used to:• Merge write transactions so that the number of external transactions are minimized.
Buffer data until the EMC can complete the write transaction, improving AHB write
latency.
Convert all dynamic memory write transactions into quadword bursts on the external
memory interface. This enhances transfer efficiency for dynamic memory.

• Reduce external memory traffic. This improves memory bandwidth and reduces
power consumption.
Write buffer operation:• If the buffers are enabled, an AHB write operation writes into the Least Recently Used
(LRU) buffer, if empty.
If the LRU buffer is not empty, the contents of the buffer are flushed to memory to
make space for the AHB write data.

• If a buffer contains write data it is marked as dirty, and its contents are written tomemory before the buffer can be reallocated.
The write buffers are flushed whenever:• The memory controller state machine is not busy performing accesses to external
memory.

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The memory controller state machine is not busy performing accesses to external
memory, and an AHB interface is writing to a different buffer.
Note: For dynamic memory, the smallest buffer flush is a quadword of data. For static
memory, the smallest buffer flush is a byte of data.

5.2.2 Read buffers
Read buffers are used to:• Buffer read requests from memory. Future read requests that hit the buffer read thedata from the buffer rather than memory, reducing transaction latency.
Convert all read transactions into quadword bursts on the external memory interface.
This enhances transfer efficiency for dynamic memory.

• Reduce external memory traffic. This improves memory bandwidth and reduces
power consumption.
Read buffer operation:• If the buffers are enabled and the read data is contained in one of the buffers, the readdata is provided directly from the buffer.

• If the read data is not contained in a buffer, the LRU buffer is selected. If the buffer isdirty (contains write data), the write data is flushed to memory. When an empty buffer
is available the read command is posted to the memory.
A buffer filled by performing a read from memory is marked as not-dirty (not containing
write data) and its contents are not flushed back to the memory controller unless a
subsequent AHB transfer performs a write that hits the buffer.

5.3 Memory controller state machine
The memory controller state machine comprises a static memory controller and a dynamic
memory controller.

5.4 Pad interface
The pad interface block provides the interface to the pads.

6. Memory bank selectTwo independently-configurable memory chip selects are supported. Pins CS1 and CS0
are used to select static memory devices.
Static memory chip select ranges are each 64 kilobytes in size. Table 5–45 shows theaddress ranges of the chip selects.
Table 45.

Memory bank selection

Chip Select Pin Address Range

Memory Type Size of Range

CS00x8000 000 - 0x8000 FFFF

Static64 kB

CS10x8100 000 - 0x8100 FFFF

Static64 kB

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7. Reset
The EMC receives two reset signals. One is Power-On Reset (POR), asserted when chip
power is applied, and when a brown-out condition is detected (see Section 3–5“Brown-out detection” for details). The other reset is from the external Reset pin and theWatchdog Timer.
A configuration bit in the SCS register, called EMC_Reset_Disable, allows control of how
the EMC is reset. The default configuration (EMC_Reset_Disable = 0) is that both EMC
resets are asserted when any type of reset event occurs. In this mode, all registers andfunctions of the EMC are initialized upon any reset condition.
If EMC_Reset_Disable is set to 1, many portions of the EMC are only reset by a power-onor brown-out event, in order to allow the EMC to retain its state through a warm reset(external reset or watchdog reset). If the EMC is configured correctly, auto-refresh can be
maintained through a warm reset.

8. Pin description
Table 5–46 shows the interface and control signal pins for the EMC.
Table 46.

Pad interface and control signal descriptions

Name

Type

Value on POR Description
reset

A[15:0]

Output 0x0000 0000

D[7:0]

Input/ Data outputs = External memory data lines. These are inputs when
Output 0x0000 0000
data is read from external memory and outputs whendata is written to external memory.

External memory address output.

OE

Output 1

Low active output enable for static memory devices.

WE

Output 1

Low active write enable.

CS[1:0]

Output 0x3

Static memory chip selects. Default active LOW.
Used for static memory devices.

9. Register description
This chapter describes the EMC registers and provides details required when
programming the microcontroller. The EMC registers are shown in Table 5–47.
Table 47.

EMC register summary

Address

Register Name

Description

Warm POR Type
Reset Reset
Value Value

0xFFE0 8000

EMCControl

Controls operation of the memory controller.

0x1

0x3

R/W

0xFFE0 8004

EMCStatus

Provides EMC status information.

-

0x5

RO

0xFFE0 8008

EMCConfig

Configures operation of the memory controller

-

0x0

R/W

0xFFE0 8200

EMCStaticConfig0

Selects the memory configuration for static chip select 0.

-

0x0

R/W

0xFFE0 8204

EMCStaticWaitWen0

Selects the delay from chip select 0 to write enable.

-

0x0

R/W

0xFFE0 8208

EMCStaticWaitOen0

Selects the delay from chip select 0 or address change,
whichever is later, to output enable.

-

0x0

R/W

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Table 47.

EMC register summary

Address

Register Name

Description

Warm POR Type
Reset Reset
Value Value

0xFFE0 820C EMCStaticWaitRd0

Selects the delay from chip select 0 to a read access.

-

0x1F

R/W

0xFFE0 8210

EMCStaticWaitPage0

Selects the delay for asynchronous page modesequential accesses for chip select 0.

-

0x1F

R/W

0xFFE0 8214

EMCStaticWaitWr0

Selects the delay from chip select 0 to a write access.

-

0x1F

R/W

0xFFE0 8218

EMCStaticWaitTurn0

Selects the number of bus turnaround cycles for chip
select 0.

-

0xF

R/W

0xFFE0 8220

EMCStaticConfig1

Selects the memory configuration for static chip select 1.

-

0x0

R/W

0xFFE0 8224

EMCStatic\WaitWen1

Selects the delay from chip select 1 to write enable.

-

0x0

R/W

0xFFE0 8228

EMCStaticWaitOen1

Selects the delay from chip select 1 or address change,
whichever is later, to output enable.

-

0x0

R/W

0xFFE0 822C EMCStaticWaitRd1

Selects the delay from chip select 1 to a read access.

-

0x1F

R/W

0xFFE0 8230

EMCStaticWaitPage1

Selects the delay for asynchronous page modesequential accesses for chip select 1.

-

0x1F

R/W

0xFFE0 8234

EMCStaticWaitWr1

Selects the delay from chip select 1 to a write access.

-

0x1F

R/W

0xFFE0 8238

EMCStaticWaitTurn1

Selects the number of bus turnaround cycles for chip
select 1.

-

0xF

R/W

0xFFE0 8880

EMCStaticExtendedWait

Time long static memory read and write transfers.

-

0x0

R/W

9.1 EMC Control Register (EMCControl - 0xFFE0 8000)
The EMCControl Register is a read/write register that controls operation of the memory
controller. The control bits can be altered during normal operation. Table 5–48 shows the
bit assignments for the EMCControl Register.
Table 48.

EMC Control register (EMCControl - address 0xFFE0 8000) bit description

Bit

Symbol0

E

Value Description

POR
Reset
Value

EMC Enable control. Indicates if the EMC is enabled or disabled:0

Disabled

1

Enabled (POR and warm reset value).

1

Note: Disabling the EMC reduces power consumption. When the memory controller isdisabled the memory is not refreshed. The memory controller is enabled by setting theenable bit or by reset.
This bit must only be modified when the EMC is in idle state.[1]1MAddress mirror control. Indicates normal or reset memory map:

10Normal memory map.

1

Reset memory map. Static memory chip select 1 is mirrored onto chip select 0 (POR
reset value).
Note: On POR, chip select 1 is mirrored to both chip select 0 and chip select 1 memoryareas. Clearing the M bit enables chip select 0 memory to be accessed.

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Table 48.

EMC Control register (EMCControl - address 0xFFE0 8000) bit description

Bit

Symbol2

L

Value Description

POR
Reset
Value

Low-power mode control. Indicates normal, or low-power mode:0

Normal mode (warm reset value).

1

Low-power mode.

0

Note: Entering low-power mode reduces memory controller power consumption.
Dynamic memory is refreshed as necessary. The memory controller returns to normal
functional mode by clearing the low-power mode bit (L), or by POR.
This bit must only be modified when the EMC is in idle state.[1]
31:3

[1]

-

-

Reserved, user software should not write ones to reserved bits. The value read from areserved bit is not defined.

NA

The external memory cannot be accessed in low-power or disabled state. If a memory access is performed an AHB error response isgenerated. The EMC registers can be programmed in low-power and/or disabled state.

9.2 EMC Status Register (EMCStatus - 0xFFE0 8004)
The read-only EMCStatus Register provides EMC status information. Table 5–49 shows
the bit assignments for the EMCStatus Register.
Table 49.

EMC Status register (EMCStatus - address 0xFFE0 8008) bit description

Bit

Symbol

0

B

1

2

Value

POR
Reset
Value

Busy. This bit is used to ensure that the memory controller enters the low-power or 1
disabled mode cleanly by determining if the memory controller is busy or not:0

EMC is idle (warm reset value).

1

EMC is busy performing memory transactions, commands, auto-refresh cycles, oris in self-refresh mode (POR reset value).

S

Write buffer status. This bit enables the EMC to enter low-power mode or disabled 0
mode cleanly:0

Write buffers empty (POR reset value)

1

Write buffers contain data.

SA

31:3 -

Description

Self-refresh acknowledge. This bit indicates the operating mode of the EMC:
0

Normal mode1

Self-refresh mode (POR reset value).

-Reserved, user software should not write ones to reserved bits. The value readfrom a reserved bit is not defined.

1NA

9.3 EMC Configuration Register (EMCConfig - 0xFFE0 8008)
The EMCConfig Register configures the operation of the memory controller. It is
recommended that this register is modified during system initialization, or when there areno current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power or disabled mode. This register is accessed with one
wait state. Table 5–50 shows the bit assignments for the EMCConfig Register.

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Table 50.

EMC Configuration register (EMCConfig - address 0xFFE0 8008) bit description

Bit

SymbolValue Description

0

Endian_mode

POR
Reset
Value

Endian mode:

00

Little-endian mode (POR reset value).

1

Big-endian mode.
On power-on reset, the value of the endian bit is 0. All data must be flushed in the
EMC before switching between little-endian and big-endian modes.

7:1

-

-

Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.

8

-

-

Reserved, user software should not write ones to reserved bits. The value read from 0
a reserved bit is not defined.

31:9 --

Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.

9.4 Static Memory Configuration Registers (EMCStaticConfig0-1 0xFFE0 8200, 220)
The EMCStaticConfig0-1 Registers configure the static memory configuration. It is
recommended that these registers are modified during system initialization, or when there
are no current or outstanding transactions. This can be ensured by waiting until the EMC
is idle, and then entering low-power, or disabled mode. These registers are accessed with
one wait state.
Table 5–51 shows the bit assignments for the EMCStaticConfig0-1 Registers. Note thatsynchronous burst mode memory devices are not supported.
Table 51.

Static Memory Configuration registers (EMCStaticConfig0-1 - addresses 0xFFE0 8200, 0xFFE0 8220) bit
description

Bit

Symbol

1:0

MW

2

-

3

PM

Value Description

Memory width.

-

00

00

8 bit (POR reset value).

01

Reserved.

10

Reserved.

11

Reserved.

-

Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.
Page mode. In page mode the EMC can burst up to four external accesses.
0
Therefore devices with asynchronous page mode burst four or higher devices aresupported. Asynchronous page mode burst two devices are not supported and mustbe accessed normally.

0
5:4

POR
Reset
Value

Disabled (POR reset value).

1

Async page mode enabled (page length four).

-

Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.

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Table 51.

Static Memory Configuration registers (EMCStaticConfig0-1 - addresses 0xFFE0 8200, 0xFFE0 8220) bit
description

Bit

Symbol

6

PC

7

-

8

EW

18:9

-

19

B

20

POR
Reset
Value

Chip select polarity. The value of the chip select polarity on power-on reset is 0.

00

Active LOW chip select.

1

Active HIGH chip select.

-

Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.
Extended wait. Extended wait (EW) uses the EMCStaticExtendedWait Register totime both the read and write transfers rather than the EMCStaticWaitRd and
EMCStaticWaitWr Registers. This enables much longer transactions.[1]00Extended wait disabled (POR reset value).

1

Extended wait enabled.

-

Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.
Buffer enable control.

0

Write buffer disabled (POR reset value).

1

Write buffer enabled.

P

31:21 -

[1]

Value Description

0

Write protect control.

00

Writes not protected (POR reset value).

1

Write protected.

-

Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.

Extended wait and page mode cannot be selected simultaneously.

9.5 Static Memory Write Enable Delay Registers (EMCStaticWaitWen0-1 0xFFE0 8204, 224)
The EMCStaticWaitWen0-1 Registers enable you to program the delay from the chip
select to the write enable. It is recommended that these registers are modified duringsystem initialization, or when there are no current or outstanding transactions. This can beensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
These registers are accessed with one wait state.
Table 5–52 shows the bit assignments for the EMCStaticWaitWen0-1 Registers.

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Table 52.

Static Memory Write Enable Delay registers (EMCStaticWaitWen0-1 - addresses
0xFFE0 8204,0xFFE0 8224) bit description

Bit

Symbol

3:0

WAITWEN

31:4

-

Value

Description

POR Reset
Value

Wait write enable. Delay from chip select assertion
to write enable in terms of the CCLK clock cycles.
The delay is: (WAITWEN + 1) x tCCLK.

00

One CCLK cycle delay between assertion of chip
select and write enable (POR reset value).

n(n + 1) CCLK clock cycles delay.

0xF

16 CCLK cycle delay.

-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is
not defined.

NA

9.6 Static Memory Output Enable Delay Registers (EMCStaticWaitOen0-1- 0xFFE0 8208, 228)
The EMCStaticWaitOen0-1 Registers enable you to program the delay from the chip
select or address change, whichever is later, to the output enable. It is recommended thatthese registers are modified during system initialization, or when there are no current or
outstanding transactions. This can be ensured by waiting until the EMC is idle, and thenentering low-power, or disabled mode. These registers are accessed with one wait state.
Table 5–53 shows the bit assignments for the EMCStaticWaitOen0-1 Registers.
Table 53.

Static Memory Output Enable delay registers (EMCStaticWaitOen0-1 - addresses
0xFFE0 8208, 0xFFE0 8228) bit description

Bit

Symbol

3:0

WAITOEN

31:4-

Value Description

POR Reset
Value

Wait output enable. Delay from chip select assertion 0x0
to output enable in terms of the CCLK cycles. The
delay is: (WAITOEN x tCCLK).
0x0

No delay (POR reset value).

nn CCLK clock cycles delay.

0xF

15 CCLK clock cycles delay.

-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is
not defined.

NA

9.7 Static Memory Read Delay Registers (EMCStaticWaitRd0-1 0xFFE0 820C, 22C)
The EMCStaticWaitRd0-1 Registers enable you to program the delay from the chip selectto the read access. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can beensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. It
is not used if the extended wait bit is enabled in the EMCStaticConfig0-1 Registers. These
registers are accessed with one wait state.
Table 5–54 shows the bit assignments for the EMCStaticWaitRd0-1 Registers.
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Table 54.

Static Memory Read Delay registers (EMCStaticWaitRd0-1 - addresses
0xFFE0 820C, 0xFFE0 822C) bit description

Bit

Symbol

4:0

WAITRD

Value Description

Non-page mode read wait states or asynchronous page 0x1F
mode readfirst access wait state expressed in terms of
the CCLK clock cycles. Non-page mode read or
asynchronous page mode read, first read only wait statetime is: (WAITRD + 1) x tCCLK
0x0

31:5

Reset
Value

-

1 CCLK clock cycle for read accesses.

n(n + 1) CCLK cycles for read accesses.

0x1F

32 CCLK cycles for read accesses (POR reset value).

-Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

9.8 Static Memory Page Mode Read Delay Registers(EMCStaticwaitPage0-1 - 0xFFE0 8210, 230)
The EMCStaticWaitPage0-1 Registers enable you to program the delay for asynchronous
page mode sequential accesses. It is recommended that these registers are modified
during system initialization, or when there are no current or outstanding transactions. Thiscan be ensured by waiting until the EMC is idle, and then entering low-power, or disabledmode. This register is accessed with one wait state.
Table 5–55 shows the bit assignments for the EMCStaticWaitPage0-1 Registers.
Table 55.

Static Memory Page Mode Read Delay registers0-1 (EMCStaticWaitPage0-1 addresses 0xFFE0 8210, 0xFFE0 8230) bit description

Bit

Symbol

4:0

WAITPAGE

31:5-

Value Description

POR Reset
Value

Asynchronous page mode read after the first read wait 0x1F
states. Number of wait states for asynchronous pagemode read accesses after the first read is:(WAITPAGE + 1) x tCCLK
0x0

1 CCLK cycle read access time.

n(n+ 1) CCLK cycle read access time.

0x1F

32 CCLK cycle read access time (POR reset value).

-Reserved, user software should not write ones toNAreserved bits. The value read from a reserved bit is notdefined.

9.9 Static Memory Write Delay Registers (EMCStaticWaitwr0-1 0xFFE0 8214, 234)
The EMCStaticWaitWr0-1 Registers enable you to program the delay from the chip selectto the write access. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can beensured by waiting until the EMC is idle, and then entering low-power, or disabledmode.These registers are not used if the extended wait (EW) bit is enabled in the
EMCStaticConfig Register. These registers are accessed with one wait state.
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Table 5–56 shows the bit assignments for the EMCStaticWaitWr0-1 Registers.
Table 56.

Static Memory Write Delay registers0-1 (EMCStaticWaitWr - addresses
0xFFE0 8214, 0xFFE0 8234) bit description

Bit

Symbol

4:0

WAITWR

31:5-

Value Description

Reset
Value

SRAM Write wait states. SRAM wait state time for write
accesses after the first read in terms of the CCLK clock
cycles. The wait state time for write accesses after the
first read is (WAITWR + 2) x tCCLK:
0x0

2 CCLK cycles write access time.

n(n + 2) CCLK cycle write access time.

0x1F

33 CCLK cycle write access time (POR reset value).

-Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

0x1F

NA

9.10 Static Memory Extended Wait Register (EMCStaticExtendedWait 0xFFE0 8880)
The EMCStaticExtendedWait register times long static memory read and write transfers(which are longer that can be supported by the EMCStaticWaitRd[n] or
EMCStaticWaitWr[n] registers) when the EW bit of one of the EMCStaticConfig registers is
enabled. There is only a single EMCStaticExtendedWait Register. This is used by therelevant static memory chip select if the appropriate ExtendedWait (EW) bit in the
EMCStaticConfig Register is set. It is recommended that this register is modified duringsystem initialization, or when there are no current or outstanding transactions. However, if
necessary, these control bits can be altered during normal operation. This register isaccessed with one wait state.
Table 5–57 shows the bit assignments for the EMCStaticExtendedWait register.
Table 57.

Static Memory Extended Wait register (EMCStaticExtendedWait - address
0xFFE0 8880) bit description

Bit

Symbol

9:0

EXTENDEDWAIT

31:10 -

Value Description

Reset
Value

External wait time out in terms of the CCLK clock
cycles. The delay is (EXTENDWAIT + 1) x 16 x tCCLK
0x0

16 CCLK clock cycles (POR reset value).

n(n+1) x 16 CCLK clock cycles.

0x3F(0x3F+1) x 16 CCLK clock cycles.

-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is
not defined.

0x000

NA

For example, for a static memory read/write transfer time of 16 µs, and a CCLK frequencyof 50 MHz, the following value must be programmed into this register:–6

6

16 × 10 × 50 × 10-------------------------------------------------- – 1 = 49
16
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9.11 Static Memory Turn Round Delay Registers (EMCStaticWaitTurn0-1 0xFFE0 8218, 238, 258, 278)
The EMCStaticWaitTurn0-1 Registers enable you to program the number of bus
turnaround cycles. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can beensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
These registers are accessed with one wait state.
Table 5–58 shows the bit assignments for the EMCStaticWaitTurn0-1 Registers.
Table 58.

Static Memory Turn Round Delay registers0-1 (EMCStaticWaitTurn0-1- addresses
0xFFE0 8218, 0xFFE0 8238) bit description

Bit

Symbol

3:0

WAITTURN

31:4-

Value Description

Reset
Value

Bus turnaround cycles in terms of the CCLK clock cycles.
Bus turnaround time is (WAITTURN + 1) x tCCLK.
0

1 CCLK clock cycle turnaround cyclesn(n + 1) CCLK clock cycles turnaround cycle.

0xF

16 CCLK turnaround cycles (POR reset value).

-Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

0xF
NATo prevent bus contention on the external memory data bus, the WAITTURN field controls
the number of bus turnaround cycles added between static memory read and write
accesses. The WAITTURN field also controls the number of turnaround cycles between
static memory and dynamic memory accesses.

10. External memory interface
Shown in Figure 5–13 is the external memory interfacing for an 8 bit bank width .
8 bit wide memory banks do require all address lines down to A0. Configuring A1 and/or
A0 line(s) to provide address or non-address function is accomplished using the Pin
Function Select Register (see Section 9–6.9).
Symbol "a_b" in the following figures refers to the highest order address line in the databus. Symbol "a_m" refers to the highest order address line of the memory chip used in theexternal memory interface.

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CS
OE

BLS[0]
D[7:0]

CE
OE
WE
IO[7:0]A[a_m:0]

A[a_b:0]

Fig 13. 8 bit bank external memory interface

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Chapter 6: Vectored Interrupt Controller (VIC)Rev. 01 — 6 July 2007

User manual

1. Features• ARM PrimeCell Vectored Interrupt Controller• Mapped to AHB address space for fast access• Supports 32 vectored IRQ interrupts• 16 programmable interrupt priority levels• Fixed hardware priority within each programmable priority level• Hardware priority level masking• Any input can be assigned as an FIQ interrupt• Software interrupt generation

2. Description
The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast
Interrupt reQuest (FIQ). The Vectored Interrupt Controller (VIC) takes 32 interrupt request
inputs and programmably assigns them as FIQ or vectored IRQ types. The programmableassignment scheme means that priorities of interrupts from the various peripherals can be
dynamically assigned and adjusted.
Fast Interrupt reQuest (FIQ) requests have the highest priority. If more than one request is
assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM
processor. The fastest possible FIQ latency is achieved when only one request isclassified as FIQ, because then the FIQ service routine can simply start dealing with thatdevice. But if more than one request is assigned to the FIQ class, the FIQ service routine
can read a word from the VIC that identifies which FIQ source(s) is (are) requesting aninterrupt.
Vectored IRQ’s, which include all interrupt requests that are not classified as FIQs, have aprogrammable interrupt priority. When more than one interrupt is assigned the samepriority and occur simultaneously, the one connected to the lowest numbered VIC channel(see Table 6–73 on page 79) will be serviced first.
The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the
ARM processor. The IRQ service routine can start by reading a register from the VIC andjumping to the address supplied by that register.

3. Register description
The VIC implements the registers shown in Table 6–59. More detailed descriptions follow.

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Table 59.

VIC register map

Name

Description

AccessReset Address
value[1]

VICIRQStatus

IRQ Status Register. This register reads out the state of thoseinterrupt requests that are enabled and classified as IRQ.

RO

0

0xFFFF F000

VICFIQStatus

FIQ Status Requests. This register reads out the state of thoseinterrupt requests that are enabled and classified as FIQ.

RO

0

0xFFFF F004

VICRawIntr

Raw Interrupt Status Register. This register reads out the state of RO
the 32 interrupt requests / software interrupts, regardless ofenabling or classification.

-

0xFFFF F008

VICIntSelectInterrupt Select Register. This register classifies each of the 32
interrupt requests as contributing to FIQ or IRQ.

R/W

00xFFFF F00C

VICIntEnable

Interrupt Enable Register. This register controls which of the 32
interrupt requests and software interrupts are enabled tocontribute to FIQ or IRQ.

R/W

00xFFFF F010

VICIntEnClr

Interrupt Enable Clear Register. This register allows software toclear one or more bits in the Interrupt Enable register.

WO-

0xFFFF F014

VICSoftInt

Software Interrupt Register. The contents of this register are
ORed with the 32 interrupt requests from various peripheral
functions.

R/W

00xFFFF F018

VICSoftIntClear

Software Interrupt Clear Register. This register allows software
to clear one or more bits in the Software Interrupt register.

WO-

0xFFFF F01C

VICProtection

Protection enable register. This register allows limiting access to R/Wthe VIC registers by software running in privileged mode.

0

0xFFFF F020

VICSWPriorityMask Software Priority Mask Register. Allows masking individualinterrupt priority levels in any combination.

R/W

0xFFFF 0xFFFF F024

VICVectAddr0

Vector address 0 register. Vector Address Registers 0-31 holdthe addresses of the Interrupt Service routines (ISRs) for the 32
vectored IRQ slots.

R/W

0

0xFFFF F100

VICVectAddr1

Vector address 1 register.

R/W

00xFFFF F104

VICVectAddr2

Vector address 2 register.

R/W

00xFFFF F108

VICVectAddr3

Vector address 3 register.

R/W

00xFFFF F10C

VICVectAddr4

Vector address 4 register.

R/W

00xFFFF F110

VICVectAddr5

Vector address 5 register.

R/W

00xFFFF F114

VICVectAddr6

Vector address 6 register.

R/W

00xFFFF F118

VICVectAddr7

Vector address 7 register.

R/W

00xFFFF F11C

VICVectAddr8

Vector address 8 register.

R/W

00xFFFF F120

VICVectAddr9

Vector address 9 register.

R/W

00xFFFF F124

VICVectAddr10

Vector address 10 register.

R/W

00xFFFF F128

VICVectAddr11

Vector address 11 register.

R/W

00xFFFF F12C

VICVectAddr12

Vector address 12 register.

R/W

00xFFFF F130

VICVectAddr13

Vector address 13 register.

R/W

00xFFFF F134

VICVectAddr14

Vector address 14 register.

R/W

00xFFFF F138

VICVectAddr15

Vector address 15 register.

R/W

00xFFFF F13C

VICVectAddr16

Vector address 16 register.

R/W

00xFFFF F140

VICVectAddr17

Vector address 17 register.

R/W

00xFFFF F144

VICVectAddr18

Vector address 18 register.

R/W

00xFFFF F148

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Table 59.

VIC register map

Name

Description

AccessReset Address
value[1]

VICVectAddr19

Vector address 19 register.

R/W

00xFFFF F14C

VICVectAddr20

Vector address 20 register.

R/W

00xFFFF F150

VICVectAddr21

Vector address 21 register.

R/W

00xFFFF F154

VICVectAddr22

Vector address 22 register.

R/W

00xFFFF F158

VICVectAddr23

Vector address 23 register.

R/W

00xFFFF F15C

VICVectAddr24

Vector address 24 register.

R/W

00xFFFF F160

VICVectAddr25

Vector address 25 register.

R/W

00xFFFF F164

VICVectAddr26

Vector address 26 register.

R/W

00xFFFF F168

VICVectAddr27

Vector address 27 register.

R/W

00xFFFF F16C

VICVectAddr28

Vector address 28 register.

R/W

00xFFFF F170

VICVectAddr29

Vector address 29 register.

R/W

00xFFFF F174

VICVectAddr30

Vector address 30 register.

R/W

00xFFFF F178

VICVectAddr31

Vector address 31 register.

R/W

00xFFFF F17C

VICVectPriority0

Vector priority 0 register. Vector Priority Registers 0-31. Each ofthese registers designates the priority of the corresponding
vectored IRQ slot.

R/W

0xF

0xFFFF F200

VICVectPriority1

Vector priority 1 register.

R/W

0xF

0xFFFF F204

VICVectPriority2

Vector priority 2 register.

R/W

0xF

0xFFFF F208

VICVectPriority3

Vector priority 3 register.

R/W

0xF

0xFFFF F20C

VICVectPriority4

Vector priority 4 register.

R/W

0xF

0xFFFF F210

VICVectPriority5

Vector priority 5 register.

R/W

0xF

0xFFFF F214

VICVectPriority6

Vector priority 6 register.

R/W

0xF

0xFFFF F218

VICVectPriority7

Vector priority 7 register.

R/W

0xF

0xFFFF F21C

VICVectPriority8

Vector priority 8 register.

R/W

0xF

0xFFFF F220

VICVectPriority9

Vector priority 9 register.

R/W

0xF

0xFFFF F224

VICVectPriority10

Vector priority 10 register.

R/W

0xF

0xFFFF F228

VICVectPriority11

Vector priority 11 register.

R/W

0xF

0xFFFF F22C

VICVectPriority12

Vector priority 12 register.

R/W

0xF

0xFFFF F230

VICVectPriority13

Vector priority 13 register.

R/W

0xF

0xFFFF F234

VICVectPriority14

Vector priority 14 register.

R/W

0xF

0xFFFF F238

VICVectPriority15

Vector priority 15 register.

R/W

0xF

0xFFFF F23C

VICVectPriority16

Vector priority 16 register.

R/W

0xF

0xFFFF F240

VICVectPriority17

Vector priority 17 register.

R/W

0xF

0xFFFF F244

VICVectPriority18

Vector priority 18 register.

R/W

0xF

0xFFFF F248

VICVectPriority19

Vector priority 19 register.

R/W

0xF

0xFFFF F24C

VICVectPriority20

Vector priority 20 register.

R/W

0xF

0xFFFF F250

VICVectPriority21

Vector priority 21 register.

R/W

0xF

0xFFFF F254

VICVectPriority22

Vector priority 22 register.

R/W

0xF

0xFFFF F258

VICVectPriority23

Vector priority 23 register.

R/W

0xF

0xFFFF F25C

VICVectPriority24

Vector priority 24 register.

R/W

0xF

0xFFFF F260

VICVectPriority25

Vector priority 25 register.

R/W

0xF

0xFFFF F264

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Chapter 6: LPC2300 VIC

Table 59.

VIC register map

Name

Description

AccessReset Address
value[1]

VICVectPriority26

Vector priority 26 register.

R/W

0xF

0xFFFF F268

VICVectPriority27

Vector priority 27 register.

R/W

0xF

0xFFFF F26C

VICVectPriority28

Vector priority 28 register.

R/W

0xF

0xFFFF F270

VICVectPriority29

Vector priority 29 register.

R/W

0xF

0xFFFF F274

VICVectPriority30

Vector priority 30 register.

R/W

0xF

0xFFFF F278

VICVectPriority31

Vector priority 31 register.

R/W

0xF

0xFFFF F27C

VICAddress

Vector address register. When an IRQ interrupt occurs, theVector Address Register holds the address of the currently
active interrupt.

R/W

00xFFFF FF00

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

4. VIC registers
The following section describes the VIC registers in the order in which they are used in the
VIC logic, from those closest to the interrupt request inputs to those most abstracted foruse by software. For most people, this is also the best order to read about the registers
when learning the VIC.

4.1 Software Interrupt Register (VICSoftInt - 0xFFFF F018)
The VICSoftInt register is used to generate software interrupts. The contents of thisregister are ORed with the 32 interrupt requests from the various peripherals, before anyother logic is applied.
Table 60.

Software Interrupt register (VICSoftInt - address 0xFFFF F018) bit description

Bit

SymbolValue

Description

Reset
value

31:0

See Table 6–74
“Interrupt sources
bit allocationtable”.

0

Do not force the interrupt request with this bit number. Writing zeroes to bits 0
in VICSoftInt has no effect, see VICSoftIntClear (Section 6–4.2).

1

Force the interrupt request with this bit number.

4.2 Software Interrupt Clear Register (VICSoftIntClear - 0xFFFF F01C)
The VICSoftIntClear register is a ’Write Only’ register. This register allows software toclear one or more bits in the Software Interrupt register, without having to first read it.
Table 61.

Software Interrupt Clear register (VICSoftIntClear - address 0xFFFF F01C) bit description

Bit

SymbolValue

Description

Reset
value

31:0

See Table 6–74
“Interrupt sources
bit allocation table”.

0

Writing a 0 leaves the corresponding bit in VICSoftInt unchanged.

0

1

Writing a 1 clears the corresponding bit in the Software Interrupt register,
removing any interrupt that may have been generated by that bit.

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4.3 Raw Interrupt Status Register (VICRawIntr - 0xFFFF F008)
This is a read only register. This register reads out the state of the 32 interrupt requests
and software interrupts, regardless of enabling or classification.
Table 62.
Bit

Raw Interrupt Status register (VICRawIntr - address 0xFFFF F008) bit description

Symbol31:0 See Table
6–74“Interrupt
sources bit
allocationtable”.

Value Description

Reset
value

0

Neither the hardware nor software interrupt request with this bit number are asserted.

1

The hardware or software interrupt request with this bit
number is asserted.

4.4 Interrupt Enable Register (VICIntEnable - 0xFFFF F010)
This is a read/write accessible register. This register controls which of the 32 combined
hardware and software interrupt requests are enabled to contribute to FIQ or IRQ.
Table 63.
Bit

Interrupt Enable register (VICIntEnable - address 0xFFFF F010) bit description

Symbol31:0 See Table
6–74“Interrupt
sources bit
allocationtable”.

Description

Reset
value

When this register is read, 1s indicate interrupt requests or softwareinterrupts that are enabled to contribute to FIQ or IRQ.

0

When this register is written, ones enable interrupt requests orsoftware interrupts to contribute to FIQ or IRQ, zeroes have noeffect. See Section 6–4.5 “Interrupt Enable Clear Register(VICIntEnClear - 0xFFFF F014)” on page 76 and Table 6–64 below
for how to disable interrupts.

4.5 Interrupt Enable Clear Register (VICIntEnClear - 0xFFFF F014)
This is a write only register. This register allows software to clear one or more bits in theInterrupt Enable register (see Section 6–4.4 “Interrupt Enable Register (VICIntEnable 0xFFFF F010)” on page 76), without having to first read it.
Table 64.
Bit

Interrupt Enable Clear register (VICIntEnClear - address 0xFFFF F014) bit
description

Symbol31:0 See Table
6–74“Interrupt
sources bit
allocationtable”.

Value Description

Reset
value

0

Writing a 0 leaves the corresponding bit in VICIntEnable
unchanged.

-

1

Writing a 1 clears the corresponding bit in the Interrupt
Enable register, thus disabling interrupts for this request.

4.6 Interrupt Select Register (VICIntSelect - 0xFFFF F00C)
This is a read/write accessible register. This register classifies each of the 32 interrupt
requests as contributing to FIQ or IRQ.

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Table 65.

Interrupt Select register (VICIntSelect - address 0xFFFF F00C) bit description

Bit

SymbolValue Description

Reset
value

31:0

See Table
6–74“Interrupt
sources bit
allocationtable”.

0

The interrupt request with this bit number is assigned to the 0
IRQ category.

1

The interrupt request with this bit number is assigned to the
FIQ category.

4.7 IRQ Status Register (VICIRQStatus - 0xFFFF F000)
This is a read only register. This register reads out the state of those interrupt requests
that are enabled and classified as IRQ.
Table 66.
Bit

IRQ Status register (VICIRQStatus - address 0xFFFF F000) bit description

Symbol31:0 See Table
6–74“Interrupt
sources bit
allocationtable”.

Description

Reset
value

A bit read as 1 indicates a corresponding interrupt request being
enabled, classified as IRQ, and asserted

0

4.8 FIQ Status Register (VICFIQStatus - 0xFFFF F004)
This is a read only register. This register reads out the state of those interrupt requests
that are enabled and classified as FIQ. If more than one request is classified as FIQ, theFIQ service routine can read this register to see which request(s) is (are) active.
Table 67.
Bit

FIQ Status register (VICFIQStatus - address 0xFFFF F004) bit description

Symbol31:0 See Table
6–74“Interrupt
sources bit
allocationtable”.

Description

Reset
value

A bit read as 1 indicates a corresponding interrupt request being
enabled, classified as IRQ, and asserted

0

4.9 Vector Address Registers 0-31 (VICVectAddr0-31 - 0xFFFF F100 to
17C)
These are read/write accessible registers. These registers hold the addresses of theInterrupt Service routines (ISRs) for the 32 vectored IRQ slots.

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Table 68.
Bit

Vector Address registers 0-31 (VICVectAddr0-31 - addresses 0xFFFF F100 to
0xFFFF F17C) bit description

SymbolDescription

Reset value

31:0 VICVectAddr The VIC provides the contents of one of these registers in
0x0000 0000
response to a read of the Vector Address register (VICAddress
see Section 6–4.9). The contents of the specific VICVectAddr
register (one of the 32 VICVectAddr registers) that
corresponds to the interrupt that is to be serviced is read from
VICAddress whenever an interrupt occurs.

4.10 Vector Priority Registers 0-31 (VICVectPriority0-31 - 0xFFFF F200 to
27C)
These registers select a priority level for the 32 vectored IRQs. There are 16 priority
levels, corresponding to the values 0 through 15 decimal, of which 15 is the lowest priority.
The reset value of these registers defaults all interrupt to the lowest priority, allowing asingle write to elevate the priority of an individual interrupt.
Table 69.

Vector Priority registers 0-31 (VICVectPriority0-31 - addresses 0xFFFF F200 to
0xFFFF F27C) bit description

Bit

Symbol

3:0

VICVectPriority Selects one of 16 priority levels for the corresponding vectoredinterrupt.

31:4 -

Description

Reset
value
0xF

Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.

4.11 Vector Address Register (VICAddress - 0xFFFF FF00)
When an IRQ interrupt occurs, the address of the Interrupt Service Routine (ISR) for theinterrupt that is to be serviced can be read from this register. The address supplied is fromone of the Vector Address Registers (VICVectAddr0-31).
Table 70.
Bit

Vector Address register (VICAddress - address 0xFFFF FF00) bit description

SymbolDescription

Reset
value

31:0 VICAddress Contains the address of the ISR for the currently active interrupt. This 0
register must be written (with any value) at the end of an ISR, to
update the VIC priority hardware. Writing to the register at any othertime can cause incorrect operation.

4.12 Software Priority Mask Register (VICSWPriorityMask - 0xFFFF F024)
The Software Priority Mask Register contains individual mask bits for the 16 interrupt
priority levels.

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Table 71.

Software Priority Mask register (VICSWPriorityMask - address 0xFFFF F024) bit
description

Bit

SymbolValue Description

15:0

VICSWPriorityMask 0

31:16 -

Reset
value

Interrupt priority level is masked.

0xFFFF

1

Interrupt priority level is not masked.

-

Reserved, user software should not write ones toNAreserved bits. The value read from a reserved bit is
not defined.

4.13 Protection Enable Register (VICProtection - 0xFFFF F020)
This is a read/write accessible register. This one bit register controls access to the VIC
registers by software running in User mode. The VICProtection register itself can only beaccessed in privileged mode.
Table 72.

Protection Enable register (VICProtection - address 0xFFFF F020) bit description

Bit

SymbolValue Description

Reset
value

0

VIC_access

0

VIC registers can be accessed in User or privileged mode.

0

1

The VIC registers can only be accessed in privileged mode.

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

31:1 -

NA

5. Interrupt sources
Table 6–73 lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. There is no significance or priority about whatline is connected where, except for certain standards from ARM.
Table 73.
Block

Connection of interrupt sources to the Vectored Interrupt Controller
Flag(s)

VIC Channel # andHex Mask

WDT

Watchdog Interrupt (WDINT)

00x0000 0001-

Reserved for Software Interrupts only

1

0x0000 0002

ARM Core

Embedded ICE, DbgCommRx

20x0000 0004

ARM Core

Embedded ICE, DbgCommTX

30x0000 0008

TIMER0Match 0 - 1 (MR0, MR1)

40x0000 0010

50x0000 0020

60x0000 0040

Capture 0 - 1 (CR0, CR1)TIMER1

Match 0 - 2 (MR0, MR1, MR2)
Capture 0 - 1 (CR0, CR1)

UART0

Rx Line Status (RLS)
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)

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Table 73.

Connection of interrupt sources to the Vectored Interrupt Controller

Block

Flag(s)

VIC Channel # andHex Mask

UART1

Rx Line Status (RLS)

70x0000 0080

Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Control Change
PWM1

Match 0 - 6 of PWM1
Capture 0-1 of PWM1

80x0000 0100

I2C0

SI (state change)

90x0000 0200

SPI, SSP0SPI Interrupt Flag of SPI (SPIF)

10

0x0000 0400

110x0000 0800

Mode Fault of SPI0 (MODF)
Tx FIFO half empty of SSP1
Rx FIFO half full of SSP1
Rx Timeout of SSP1
Rx Overrun of SSP1
SSP 1

Tx FIFO half empty
Rx FIFO half fullRx Timeout
Rx Overrun

PLL

PLL Lock (PLOCK)

120x0000 1000

RTC

Counter Increment (RTCCIF)

130x0000 2000

External Interrupt 0 (EINT0)140x0000 4000

External Interrupt 1 (EINT1)

150x0000 8000

External Interrupt 2 (EINT2)

160x0001 0000

External Interrupt 3 (EINT3).

170x0002 0000

Alarm (RTCALF)
Subsecond Int (RTCSSF)
SystemControl(External
Interrupts)

Note: EINT3 channel is shared with GPIO interrupts
ADC0

A/D Converter 0 end of conversion

18

0x0004 0000

I2C1

SI (state change)

190x0008 0000

BOD

Brown Out detect200x0010 0000

Ethernet

WakeupInt, SoftInt, TxDoneInt, TxFinishedInt,

210x0020 0000

TxErrorInt, TxUnderrunInt, RxDoneInt,
RxFinishedInt, RxErrorInt, RxOverrunInt.
USB

USB_INT_REQ_LP, USB_INT_REQ_HP,
USB_INT_REQ_DMA

220x0040 0000CANCAN Common, CAN 0 Tx, CAN 0 Rx, CAN 1 Tx,
CAN 1 Rx23

0x0080 0000

SD/ MMC
interface

RxDataAvlbl, TxDataAvlbl, RxFifoEmpty, TxFifoEmpty,
24
RxFifoFull, TxFifoFull, RxFifoHalfFull, TxFifoHalfEmpty,
RxActive, TxActive, CmdActive, DataBlockEnd, StartBitErr,
DataEnd, CmdSent, CmdRespEnd, RxOverrun,
TxUnderrun, DataTimeOut, CmdTimeOut, DataCrcFail,
CmdCrcFail

0x0100 0000

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Table 73.

Connection of interrupt sources to the Vectored Interrupt Controller

Block

Flag(s)

VIC Channel # andHex Mask

GP DMA

IntStatus of DMA channel 0, IntStatus of DMA channel 1

250x0200 0000

Match 0-3

26

0x0400 0000

27

0x0800 0000

28

0x1000 0000

29

0x2000 0000

Timer 2

Capture 0-1
Timer 3

Match 0-3
Capture 0-1

UART 2Rx Line Status (RLS)
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)

UART 3Rx Line Status (RLS)
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)

I2C2

SI (state change)30

0x4000 0000

I2S

irq_rx31

0x8000 0000

irq_tx
Table 74.

Interrupt sources bit allocation table

Bit

31

30

29

28

27

26

25

24

Symbol

I2S

I2C2

UART3

UART2

TIMER3

TIMER2GPDMA

SD/MMC

Bit

23

22

21

20

19

18

17

16

CAN1&2USB

Ethernet

BOD

I2C1

AD0

EINT3

EINT2

15

14

13

12

11

10

9

8

EINT1

EINT0

RTC

PLL

SSP1

SPI/SSP0

I2C0

PWM1

7

6

5

4

3

2

1

0

UART1

UART0

TIMER1TIMER0

ARMCore1

ARMCore0-

WDT

SymbolBit
SymbolBit
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interrupt request, masking, and selection
SoftIntClear[31:0]

IntEnableClear[31:0]SoftInt[31:0]

IntEnable[31:0]

status registers and FIQ generation
FIQStatus[31:0]

VICINT
SOURCE[31:0]

IRQStatus[31:0]RawIntr[31:0]FIQ

FIQStatus[31:0]
IRQStatus[31:0]

IntSelect[31:0]

prioritization and vector generation
vectored interrupt 0
IRQStatus[0]

SWPriorityMask [31:0]
D

Q

D

Q

SWPriorityMask [0]HWPriorityMask [0]VectPriority0[3:0]

HWPriorityMask [31:0]
PRIORITY
MASKINGLOGIC
VectAddr0[31:0]VectIRQ0

Vect Addr0[31:0]

vectored interrupt 1
VectIRQ1

IRQStatus[1]

SWPriorityMask[31:0]IRQ

PRIORITY
LOGIC

vector selectfor highest priority
interrupt

Vect Addr1[31:0]
VectAddr[31:0]Vect
AddrOut

vectored interrupt 31
IRQStatus[31]

VectIRQ31
Vect Addr31[31:0]

Fig 14. Block diagram of the Vectored Interrupt Controller

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UM10211
Chapter 7: Memory Acceleration Module (MAM)
Rev. 01 — 6 July 2007

User manual

1. Introduction
The MAM block in the LPC2300 maximizes the performance of the ARM processor when
it is running code in Flash memory using a single Flash bank.

2. Operation
Simply put, the Memory Accelerator Module (MAM) attempts to have the next ARM
instruction that will be needed in its latches in time to prevent CPU fetch stalls. The
LPC2300 uses one bank of Flash memory, compared to the two banks used on
predecessor devices. It includes three 128 bit buffers called the Prefetch buffer, theBranch Trail Buffer and the data buffer. When an Instruction Fetch is not satisfied by either
the Prefetch or Branch Trail buffer, nor has a prefetch been initiated for that line, the ARM
is stalled while a fetch is initiated for the 128 bit line. If a prefetch has been initiated but not
yet completed, the ARM is stalled for a shorter time. Unless aborted by a data access, aprefetch is initiated as soon as the Flash has completed the previous access. The
prefetched line is latched by the Flash module, but the MAM does not capture the line inits prefetch buffer until the ARM core presents the address from which the prefetch has
been made. If the core presents a different address from the one from which the prefetch
has been made, the prefetched line is discarded.
The prefetch and Branch Trail buffers each include four 32 bit ARM instructions or eight
16 bit Thumb instructions. During sequential code execution, typically the prefetch buffer
contains the current instruction and the entire Flash line that contains it.
The MAM uses the LPROT[0] line to differentiate between instruction and data accesses.
Code and data accesses use separate 128 bit buffers. 3 of every 4 sequential 32 bit codeor data accesses "hit" in the buffer without requiring a Flash access (7 of 8 sequential
16 bit accesses, 15 of every 16 sequential byte accesses). The fourth (eighth, 16th)
sequential data access must access Flash, aborting any prefetch in progress. When aFlash data access is concluded, any prefetch that had been in progress is re-initiated.
Timing of Flash read operations is programmable and is described later in this section.
In this manner, there is no code fetch penalty for sequential instruction execution when the
CPU clock period is greater than or equal to one fourth of the Flash access time. The
average amount of time spent doing program branches is relatively small (less than 25%)and may be minimized in ARM (rather than Thumb) code through the use of theconditional execution feature present in all ARM instructions. This conditional execution
may often be used to avoid small forward branches that would otherwise be necessary.
Branches and other program flow changes cause a break in the sequential flow of
instruction fetches described above. The Branch Trail buffer captures the line to whichsuch a non-sequential break occurs. If the same branch is taken again, the next
instruction is taken from the Branch Trail buffer. When a branch outside the contents of theprefetch and Branch Trail buffer is taken, a stall of several clocks is needed to load theBranch Trail buffer. Subsequently, there will typically be no further instruction fetch delays
until a new and different branch occurs.
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If an attempt is made to write directly to the Flash memory, without using the normal Flashprogramming interface, the MAM generates a data abort.

3. Memory Acceleration Module blocks
The Memory Accelerator Module is divided into several functional blocks:• A Flash Address Latch and an incrementor function to form prefetch addresses• A 128 bit prefetch buffer and an associated Address latch and comparator• A 128 bit Branch Trail buffer and an associated Address latch and comparator• A 128 bit Data buffer and an associated Address latch and comparator• Control logic• Wait logic
Figure 7–15 shows a simplified block diagram of the Memory Accelerator Module data
paths.
In the following descriptions, the term “fetch” applies to an explicit Flash read request fromthe ARM. “Pre-fetch” is used to denote a Flash read of instructions beyond the current
processor fetch address.

3.1 Flash memory bank
There is one bank of Flash memory with the LPC2300 MAM.
Flash programming operations are not controlled by the MAM, but are handled as aseparate function. A “boot block” sector contains Flash programming algorithms that may
be called as part of the application program, and a loader that may be run to allow serial
programming of the Flash memory.

MEMORY ADDRESSFLASH MEMORY BANKARM LOCAL BUS

BUS
INTERFACE

BUFFERSFig 15. Simplified block diagram of the Memory Accelerator Module

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3.2 Instruction latches and data latches
Code and Data accesses are treated separately by the Memory Accelerator Module.
There is a 128 bit Latch, a 15 bit Address Latch, and a 15 bit comparator associated witheach buffer (prefetch, branch trail, and data). Each 128 bit latch holds 4 words (4 ARM
instructions, or 8 Thumb instructions).
Also associated with each buffer are 32 4:1 Multiplexers that select the requested wordfrom the 128 bit line.

3.3 Flash programming Issues
Since the Flash memory does not allow accesses during programming and erase
operations, it is necessary for the MAM to force the CPU to wait if a memory access to a
Flash address is requested while the Flash module is busy. (This is accomplished byasserting the ARM7TDMI-S local bus signal CLKEN.) Under some conditions, this delay
could result in a Watchdog time-out. The user will need to be aware of this possibility andtake steps to insure that an unwanted Watchdog reset does not cause a system failure
while programming or erasing the Flash memory.
In order to preclude the possibility of stale data being read from the Flash memory, theLPC2300 MAM holding latches are automatically invalidated at the beginning of any Flashprogramming or erase operation. Any subsequent read from a Flash address will cause a
new fetch to be initiated after the Flash operation has completed.

4. Memory Accelerator Module Operating modes
Three modes of operation are defined for the MAM, trading off performance for ease ofpredictability:
Mode 0: MAM off. All memory requests result in a Flash read operation (see note 2
below). There are no instruction prefetches.
Mode 1: MAM partially enabled. Sequential instruction accesses are fulfilled from theholding latches if the data is present. Instruction prefetch is enabled. Non-sequential
instruction accesses initiate Flash read operations (see Table note 7–2). This meansthat all branches cause memory fetches. All data operations cause a Flash readbecause buffered data access timing is hard to predict and is very situation dependent.
Mode 2: MAM fully enabled. Any memory request (code or data) for a value that iscontained in one of the corresponding holding latches is fulfilled from the latch.
Instruction prefetch is enabled. Flash read operations are initiated for instruction
prefetch and code or data values not available in the corresponding holding latches.
Table 75.

MAM responses to program accesses of various types

Program Memory Request Type
Sequential access, data in latches

MAM Mode012Initiate Fetch[2]Use Latched
Data[1]

Use Latched
Data[1]

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Table 75.

MAM responses to program accesses of various types

Program Memory Request Type

MAM Mode0

12

Sequential access, data not in latches

Initiate Fetch

Initiate Fetch[1]Initiate Fetch[1]Non-sequential access, data in latches

Initiate Fetch[2]Initiate Fetch[1][2]Use Latched
Data[1]

Non-sequential access, data not inlatches

Initiate Fetch

Initiate Fetch[1]Initiate Fetch[1][1]Instruction prefetch is enabled in modes 1 and 2.

[2]

The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting thefetch timing value in MAMTIM to one clock.

Table 76.

MAM responses to data and DMA accesses of various types

Data Memory Request Type

MAM Mode0

12

Sequential access, data in latches

Initiate Fetch[1]Initiate Fetch[1]Use Latched
Data

Sequential access, data not in latches

Initiate Fetch

Initiate Fetch

Initiate Fetch

Non-sequential access, data in latches

Initiate Fetch[1]Initiate Fetch[1]Use Latched
Data

Initiate Fetch

Initiate Fetch

Non-sequential access, data not in latches Initiate Fetch[1]

The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting thefetch timing value in MAMTIM to one clock.

5. MAM configuration
After reset the MAM defaults to the disabled state. Software can turn memory accessacceleration on or off at any time. This allows most of an application to be run at thehighest possible performance, while certain functions can be run at a somewhat slower
but more predictable rate if more precise timing is required.

6. Register description
The MAM is controlled by the registers shown in Table 7–77. More detailed descriptions
follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic
zero.

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Table 77.

Summary of Memory Acceleration Module registers

Name

Description

Access Reset
Addressvalue[1]

MAMCR Memory Accelerator Module Control Register.
Determines the MAM functional mode, that is, towhat extent the MAM performance enhancements
are enabled. See Table 7–78.

R/W

0x0

0xE01F C000

MAMTIM Memory Accelerator Module Timing control.
Determines the number of clocks used for Flashmemory fetches (1 to 7 processor clocks).

R/W

0x07

0xE01F C004

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

7. MAM Control Register (MAMCR - 0xE01F C000)
Two configuration bits select the three MAM operating modes, as shown in Table 7–78.
Following any reset, MAM functions are disabled. Software can turn memory accessacceleration on or off at any time allowing most of an application to be run at the highest
possible performance, while certain functions can be run at a somewhat slower but morepredictable rate if more precise timing is required.
Changing the MAM operating mode causes the MAM to invalidate all of the holding
latches, resulting in new reads of Flash information as required. This guarantees
synchronization of the MAM to CPU operation.
Table 78.

MAM Control Register (MAMCR - address 0xE01F C000) bit description

Bit

Symbol1:0

MAM_mode_control
00

7:2

-

Value

Description

Reset
value

These bits determine the operating mode of the MAM.

0

MAM functions disabled

01

MAM functions partially enabled

10

MAM functions fully enabled

11

Reserved. Not to be used in the application.

-

Unused, always 0.

0

8. MAM Timing Register (MAMTIM - 0xE01F C004)
The MAM Timing register determines how many CCLK cycles are used to access theFlash memory. This allows tuning MAM timing to match the processor operating
frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock Flashaccesses would essentially remove the MAM from timing calculations. In this case theMAM mode may be selected to optimize power usage.

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Chapter 7: LPC2300 MAM

Table 79.

MAM Timing register (MAMTIM - address 0xE01F C004) bit description

Bit

Symbol2:0

MAM_fetch_
cycle_timing

Value Description

Reset
value

These bits set the duration of MAM fetch operations.
000

0 - Reserved001

1 - MAM fetch cycles are 1 processor clock (CCLK) in
duration

010

2 - MAM fetch cycles are 2 CCLKs in duration

011

3 - MAM fetch cycles are 3 CCLKs in duration

100

4 - MAM fetch cycles are 4 CCLKs in duration

101

5 - MAM fetch cycles are 5 CCLKs in duration

110

6 - MAM fetch cycles are 6 CCLKs in duration

111

7 - MAM fetch cycles are 7 CCLKs in duration

07

Warning: These bits set the duration of MAM Flash fetch operations
as listed here. Improper setting of this value may result in incorrect
operation of the device.
7:3

-

-

Unused, always 0

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Chapter 7: LPC2300 MAM

xFFE0

xFFE4

xFFE8

xFFEC

30000

30004

30008

3000C

20000

20004

20008

2000C

10000
0FFF0

10004
0FFF4

10008
0FFF8

1000C
0FFFC

00020
00010
00000

00024
00014
00004

00028
00018
00008

0002C
0001C
0000C

INCREMENTOR

MUX

D
ENAL0

ADDR

Q

EN

cclk

[18:4]
=

EQA0

128

ENP
ADDR

ENBT
PREFETCH LATCH

=

ADDR

END
BT LATCH=
128

EQPREF
PREFETCH MUXDATA LATCH

=
128

EQBT
LA[3:2]

ADDR

128
EQD

BT MUX

32

32

DATA MUX
32

FINAL MUXDI[31:0] (to ARM core)Fig 16. Block diagram of the Memory Accelerator Module

9. MAM usage notes
When changing MAM timing, the MAM must first be turned off by writing a zero to
MAMCR. A new value may then be written to MAMTIM. Finally, the MAM may be turnedon again by writing a value (1 or 2) corresponding to the desired operating mode to
MAMCR.
For system clock slower than 20 MHz, MAMTIM can be 001. For system clock between
20 MHz and 40 MHz, Flash access time is suggested to be 2 CCLKs, while in systems
with system clock faster than 40 MHz, 3 CCLKs are proposed.

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UM10211
Chapter 8: Pin configurationRev. 01 — 6 July 2007

User manual

76

100

1. LPC2364/6/8 100-pin package

175

LPC2364FBD100
LPC2366FBD100
LPC2368FBD100

50

51
26

25

002aac576

Fig 17. LPC2364/6/8 100 - pin packages

2. Pin description for LPC2364/6/8
Pin description for LPC2364/6/8 and a brief explanation of corresponding functions areshown in the following table.
Table 80.

LPC2364/66/68 pin description

SymbolPin

Type

Description

P0[0] to P0[31]

I/O

Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 0 pins depends upon the pin function selected via the Pin Connect
block. Pins 12, 13, 14, and 31 of this port are not available.

P0[0]/RD1/TXD3/ 46[1]
SDA1

I/O

P0[0] — General purpose digital input/output pin.

I

RD1 — CAN1 receiver input.

O

TXD3 — Transmitter output for UART3.

I/O

SDA1 — I2C1 data input/output (this is not an open-drain pin).

I/O

P0[1] — General purpose digital input/output pin.

O

TD1 — CAN1 transmitter output.

I

RXD3 — Receiver input for UART3.

I/O

SCL1 — I2C1 clock input/output (this is not an open-drain pin).

I/O

P0[2] — General purpose digital input/output pin.

O

TXD0 — Transmitter output for UART0.

I/O

P0[3] — General purpose digital input/output pin.

I

RXD0 — Receiver input for UART0.

I/O

P0[4] — General purpose digital input/output pin.

I/O

I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I2S-bus specification.

I

RD2 — CAN2 receiver input.

I

CAP2[0] — Capture input for Timer 2, channel 0.

P0[1]/TD1/RXD3/ 47[1]SCL1

P0[2]/TXD098[1]P0[3]/RXD099[1]P0[4]/I2SRX_CLK/
RD2/CAP2[0]81[1]UM10211_1

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Chapter 8: LPC2300 Pin configuration

Table 80.

LPC2364/66/68 pin description …continued

SymbolPin

Type

Description

P0[5]/I2SRX_WS/
TD2/CAP2[1]

80[1]

I/O

P0[5] — General purpose digital input/output pin.

I/O

I2SRX_WS — Receive Word Select. It is driven by the master and received by theslave. Corresponds to the signal WS in the I2S-bus specification.

O

TD2 — CAN2 transmitter output.

I

CAP2[1] — Capture input for Timer 2, channel 1.

I/O

P0[6] — General purpose digital input/output pin.

I/O

I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver.
Corresponds to the signal SD in the I2S-bus specification.

I/O

SSEL1 — Slave Select for SSP1.

O

MAT2[0] — Match output for Timer 2, channel 0.

I/O

P0[7] — General purpose digital input/output pin.

I/O

I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I2S-bus specification.

I/O

SCK1 — Serial Clock for SSP1.

O

MAT2[1] — Match output for Timer 2, channel 1.

I/O

P0[8] — General purpose digital input/output pin.

I/O

I2STX_WS — Transmit Word Select. It is driven by the master and received by theslave. Corresponds to the signal WS in the I2S-bus specification.

I/O

MISO1 — Master In Slave Out for SSP1.

O

MAT2[2] — Match output for Timer 2, channel 2.

I/O

P0[9] — General purpose digital input/output pin.

I/O

I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver.
Corresponds to the signal SD in the I2S-bus specification.

I/O

MOSI1 — Master Out Slave In for SSP1.

O

MAT2[3] — Match output for Timer 2, channel 3.

I/O

P0[10] — General purpose digital input/output pin.

O

TXD2 — Transmitter output for UART2.

I/O

SDA2 — I2C2 data input/output (this is not an open-drain pin).

O

MAT3[0] — Match output for Timer 3, channel 0.

I/O

P0[11] — General purpose digital input/output pin.

I

RXD2 — Receiver input for UART2.

I/O

SCL2 — I2C2 clock input/output (this is not an open-drain pin).

O

MAT3[1] — Match output for Timer 3, channel 1.

I/O

P0[15] — General purpose digital input/output pin.

O

TXD1 — Transmitter output for UART1.

I/O

SCK0 — Serial clock for SSP0.

I/O

SCK — Serial clock for SPI.

I/O

P0[16] — General purpose digital input/output pin.

I

RXD1 — Receiver input for UART1.

I/O

SSEL0 — Slave Select for SSP0.

I/O

SSEL — Slave Select for SPI.

P0[6]/I2SRX_SDA/
SSEL1/MAT2[0]P0[7]/I2STX_CLK/SCK1/MAT2[1]P0[8]/I2STX_WS/MISO1/MAT2[2]P0[9]/I2STX_SDA/
MOSI1/MAT2[3]P0[10]/TXD2/
SDA2/MAT3[0]P0[11]/RXD2/
SCL2/MAT3[1]P0[15]/TXD1/
SCK0/SCK

P0[16]/RXD1/
SSEL0/SSEL

79[1]

78[1]

77[1]

76[1]

48[1]

49[1]

62[1]

63[1]

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Chapter 8: LPC2300 Pin configuration

Table 80.

LPC2364/66/68 pin description …continued

SymbolPin

Type

Description

P0[17]/CTS1/
MISO0/MISO

61[1]

I/O

P0[17] — General purpose digital input/output pin.

I

CTS1 — Clear to Send input for UART1.

P0[18]/DCD1/
MOSI0/MOSI

P0[19]/DSR1/MCICLK/SDA1

P0[20]/DTR1/
MCICMD/SCL1

P0[21]/RI1/
MCIPWR/RD1

P0[22]/RTS1/
MCIDAT0/TD1

60[1]

59[1]

58[1]

57[1]

56[1]

P0[23]/AD0[0]/I2SRX_CLK/
CAP3[0]9[2]P0[24]/AD0[1]/I2SRX_WS/
CAP3[1]8[2]P0[25]/AD0[2]/I2SRX_SDA/
TXD3

7[2]

I/O

MISO0 — Master In Slave Out for SS1

I/O

MISO — Master In Slave Out for SPI.

I/O

P0[18] — General purpose digital input/output pin.

I

DCD1 — Data Carrier Detect input for UART1.

I/O

MOSI0 — Master Out Slave In for SSP0.

I/O

MOSI — Master Out Slave In for SPI.

I/O

P0[19] — General purpose digital input/output pin.

I

DSR1 — Data Set Ready input for UART1.

OMCICLK — Clock output line for SD/MMC interface. (LPC2368 only)

I/O

SDA1 — I2C1 data input/output (this is not an open-drain pin).

I/O

P0[20] — General purpose digital input/output pin.

O

DTR1 — Data Terminal Ready output for UART1.

I

MCICMD — Command line for SD/MMC interface. (LPC2368 only)

I/O

SCL1 — I2C1 clock input/output (this is not an open-drain pin).

I/O

P0[21] — General purpose digital input/output pin.

I

RI1 — Ring Indicator input for UART1.

OMCIPWR — Power Supply Enable for external SD/MMC power supply. (LPC2368
only)

I

RD1 — CAN1 receiver input.

I/O

P0[22] — General purpose digital input/output pin.

O

RTS1 — Request to Send output for UART1.

OMCIDAT0 — Data line for SD/MMC interface. (LPC2368 only)O

TD1 — CAN1 transmitter output.

I/O

P0[23] — General purpose digital input/output pin.

I

AD0[0] — A/D converter 0, input 0.

I/O

I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I2S-bus specification.

I

CAP3[0] — Capture input for Timer 3, channel 0.

I/O

P0[24] — General purpose digital input/output pin.

I

AD0[1] — A/D converter 0, input 1.

I/O

I2SRX_WS — Receive Word Select. It is driven by the master and received by theslave. Corresponds to the signal WS in the I2S-bus specification.

I

CAP3[1] — Capture input for Timer 3, channel 1.

I/O

P0[25] — General purpose digital input/output pin.

I

AD0[2] — A/D converter 0, input 2.

I/O

I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver.
Corresponds to the signal SD in the I2S-bus specification.

O

TXD3 — Transmitter output for UART3.

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Chapter 8: LPC2300 Pin configuration

Table 80.

LPC2364/66/68 pin description …continued

SymbolPin

Type

Description

P0[26]/AD0[3]/
AOUT/RXD3

6[3]

I/O

P0[26] — General purpose digital input/output pin.

I

AD0[3] — A/D converter 0, input 3.

O

AOUT — D/A converter output.

I

RXD3 — Receiver input for UART3.

I/O

P0[27] — General purpose digital input/output pin.

I/O

SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance).

I/O

P0[28] — General purpose digital input/output pin.

I/O

SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance).

I/O

P0[29] — General purpose digital input/output pin.

I/O

USB_D+ — USB bidirectional D+ line.

I/O

P0[30] — General purpose digital input/output pin.

I/O

USB_D− — USB bidirectional D− line.

I/O

Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 1 pins depends upon the pin function selected via the Pin Connect
block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available.

I/O

P1[0] — General purpose digital input/output pin.

O

ENET_TXD0 — Ethernet transmit data 0.

I/O

P1[1] — General purpose digital input/output pin.

O

ENET_TXD1 — Ethernet transmit data 1.

I/O

P1[4] — General purpose digital input/output pin.

O

ENET_TX_EN — Ethernet transmit data enable.

I/O

P1[8] — General purpose digital input/output pin.

I

ENET_CRS — Ethernet carrier sense.

I/O

P1[9] — General purpose digital input/output pin.

P0[27]/SDA0
P0[28]/SCL0

25[4]
24[4]

P0[29]/USB_D+

29[5]P0[30]/USB_D−

30[5]P1[0] to P1[31]P1[0]/
ENET_TXD0

95[1]P1[1]/
ENET_TXD1

94[1]P1[4]/
ENET_TX_EN

93[1]

P1[8]/
ENET_CRS

92[1]P1[9]/
ENET_RXD0

91[1]

I

ENET_RXD0 — Ethernet receive data.

P1[10]/
ENET_RXD1

90[1]

I/O

P1[10] — General purpose digital input/output pin.

I

ENET_RXD1 — Ethernet receive data.

P1[14]/
ENET_RX_ER

89[1]

I/O

P1[14] — General purpose digital input/output pin.

I

ENET_RX_ER — Ethernet receive error.

P1[15]/
ENET_REF_CLK

88[1]

I/O

P1[15] — General purpose digital input/output pin.

I

ENET_REF_CLK/ENET_RX_CLK — Ethernet receiver clock.

P1[16]/
ENET_MDC

87[1]

I/O

P1[16] — General purpose digital input/output pin.

I

ENET_MDC — Ethernet MIIM clock.

P1[17]/
ENET_MDIO

86[1]

I/O

P1[17] — General purpose digital input/output pin.

I/O

ENET_MDIO — Ethernet MI data input and output.

P1[18]/
USB_UP_LED/
PWM1[1]/
CAP1[0]

32[1]

I/O

P1[18] — General purpose digital input/output pin.

O

USB_UP_LED — USB GoodLink LED indicator. It is LOW when device is configured(non-control endpoints enabled). It is HIGH when the device is not configured or
during global suspend.

O

PWM1[1] — Pulse Width Modulator 1, channel 1 output.

I

CAP1[0] — Capture input for Timer 1, channel 0.

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Chapter 8: LPC2300 Pin configuration

Table 80.

LPC2364/66/68 pin description …continued

SymbolPin

Type

Description

P1[19]/CAP1[1]

33[1]

I/O

P1[19] — General purpose digital input/output pin.

I

CAP1[1] — Capture input for Timer 1, channel 1.

P1[20]/PWM1[2]/
SCK0

34[1]

I/O

P1[20] — General purpose digital input/output pin.

O

PWM1[2] — Pulse Width Modulator 1, channel 2 output.

I/O

SCK0 — Serial clock for SSP0.

P1[21]/PWM1[3]/
SSEL0

35[1]

I/O

P1[21] — General purpose digital input/output pin.

O

PWM1[3] — Pulse Width Modulator 1, channel 3 output.

I/O

SSEL0 — Slave Select for SSP0.

I/O

P1[22] — General purpose digital input/output pin.

O

MAT1[0] — Match output for Timer 1, channel 0.

I/O

P1[23] — General purpose digital input/output pin.

O

PWM1[4] — Pulse Width Modulator 1, channel 4 output.

I/O

MISO0 — Master In Slave Out for SSP0.

I/O

P1[24] — General purpose digital input/output pin.

O

PWM1[5] — Pulse Width Modulator 1, channel 5 output.

I/O

MOSI0 — Master Out Slave in for SSP0.

I/O

P1[25] — General purpose digital input/output pin.

O

MAT1[1] — Match output for Timer 1, channel 1.

I/O

P1[26] — General purpose digital input/output pin.

O

PWM1[6] — Pulse Width Modulator 1, channel 6 output.

P1[22]/MAT1[0]36[1]P1[23]/PWM1[4]/
MISO0

37[1]

P1[24]/PWM1[5]/
MOSI0

38[1]

P1[25]/MAT1[1]39[1]P1[26]/PWM1[6]/CAP0[0]40[1]I

CAP0[0] — Capture input for Timer 0, channel 0.

P1[27]/CAP0[1]

43[1]

I/O

P1[27] — General purpose digital input/output pin.

I

CAP0[1] — Capture input for Timer 0, channel 1.

P1[28]/
PCAP1[0]/MAT0[0]

44[1]

I/O

P1[28] — General purpose digital input/output pin.

I

PCAP1[0] — Capture input for PWM1, channel 0.

O

MAT0[0] — Match output for Timer 0, channel 0.

P1[29]/
PCAP1[1]/MAT0[1]

45[1]

I/O

P1[29] — General purpose digital input/output pin.

I

PCAP1[1] — Capture input for PWM1, channel 1.

O

MAT0[1] — Match output for Timer 0, channel 0.

P1[30]/VBUS/
AD0[4]

21[2]

I/O

P1[30] — General purpose digital input/output pin.

I

VBUS — Indicates the presence of USB bus power.
Note: This signal must be HIGH for USB reset to occur.

P1[31]/SCK1/
AD0[5]

P2[0] to P2[31]

20[2]

I

AD0[4] — A/D converter 0, input 4.

I/O

P1[31] — General purpose digital input/output pin.

I/O

SCK1 — Serial Clock for SSP1.

I

AD0[5] — A/D converter 0, input 5.

I/O

Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 2 pins depends upon the pin function selected via the Pin Connect
block. Pins 14 through 31 of this port are not available.

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UM10211NXP Semiconductors

Chapter 8: LPC2300 Pin configuration

Table 80.

LPC2364/66/68 pin description …continued

SymbolPin

Type

Description

P2[0]/PWM1[1]/TXD1/TRACECLK

75[1]

I/O

P2[0] — General purpose digital input/output pin.

O

PWM1[1] — Pulse Width Modulator 1, channel 1 output.

O

TXD1 — Transmitter output for UART1.

OTRACECLK — Trace Clock.

I/O

P2[1] — General purpose digital input/output pin.

O

PWM1[2] — Pulse Width Modulator 1, channel 2 output.

I

RXD1 — Receiver input for UART1.

OPIPESTAT0 — Pipeline Status, bit 0.

I/O

P2[2] — General purpose digital input/output pin.

O

PWM1[3] — Pulse Width Modulator 1, channel 3 output.

I

CTS1 — Clear to Send input for UART1.

OPIPESTAT1 — Pipeline Status, bit 1.

I/O

P2[3] — General purpose digital input/output pin.

O

PWM1[4] — Pulse Width Modulator 1, channel 4 output.

I

DCD1 — Data Carrier Detect input for UART1.

OPIPESTAT2 — Pipeline Status, bit 2.

I/O

P2[4] — General purpose digital input/output pin.

O

PWM1[5] — Pulse Width Modulator 1, channel 5 output.

I

DSR1 — Data Set Ready input for UART1.

OTRACESYNC — Trace Synchronization.

I/O

P2[5] — General purpose digital input/output pin.

O

PWM1[6] — Pulse Width Modulator 1, channel 6 output.

O

DTR1 — Data Terminal Ready output for UART1.

OTRACEPKT0 — Trace Packet, bit 0.

I/O

P2[6] — General purpose digital input/output pin.

I

PCAP1[0] — Capture input for PWM1, channel 0.

I

RI1 — Ring Indicator input for UART1.

OTRACEPKT1 — Trace Packet, bit 1.

I/O

P2[7] — General purpose digital input/output pin.

I

RD2 — CAN2 receiver input.

O

RTS1 — Request to Send output for UART1.

OTRACEPKT2 — Trace Packet, bit 2.

I/O

P2[8] — General purpose digital input/output pin.

O

TD2 — CAN2 transmitter output.

O

TXD2 — Transmitter output for UART2.

OTRACEPKT3 — Trace Packet, bit 3.

I/O

P2[9] — General purpose digital input/output pin.

O

USB_CONNECT — Signal used to switch an external 1.5 kΩ resistor under software
control. Used with the SoftConnect USB feature.

I

RXD2 — Receiver input for UART2.

I

EXTIN0 — External Trigger Input.

P2[1]/PWM1[2]/RXD1/PIPESTAT0

P2[2]/PWM1[3]/CTS1/PIPESTAT1

P2[3]/PWM1[4]/DCD1/PIPESTAT2

P2[4]/PWM1[5]/DSR1/TRACESYNC

P2[5]/PWM1[6]/DTR1/TRACEPKT0

P2[6]/PCAP1[0]/RI1/TRACEPKT1

P2[7]/RD2/
RTS1/
TRACEPKT2

P2[8]/TD2/
TXD2/TRACEPKT3

P2[9]/
USB_CONNECT/
RXD2/EXTIN0

74[1]

73[1]

70[1]

69[1]

68[1]

67[1]

66[1]

65[1]

64[1]

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UM10211NXP Semiconductors

Chapter 8: LPC2300 Pin configuration

Table 80.

LPC2364/66/68 pin description …continued

SymbolPin

Type

Description

P2[10]/EINT0

53[6]

I/O

P2[10] — General purpose digital input/output pin.
Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take overcontrol of the part after a reset.

P2[11]/EINT1/
MCIDAT1/
I2STX_CLKP2[12]/EINT2/MCIDAT2/
I2STX_WS

P2[13]/EINT3/MCIDAT3/
I2STX_SDA

52[6]

51[6]

50[6]

P3[0] to P3[31]P3[25]/MAT0[0]/PWM1[2]27[1]P3[26]/MAT0[1]/
PWM1[3]26[1]P4[0] to P4[31]P4[28]/MAT2[0]/
TXD3

82[1]

P4[29]/MAT2[1]/
RXD3

85[1]

TDO

1[1]

TDI

2[1]

I

EINT0 — External interrupt 0 input.

I/O

P2[11] — General purpose digital input/output pin.

I

EINT1 — External interrupt 1 input.

O

MCIDAT1 — Data line for SD/MMC interface. (LPC2368 only)

I/O

I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I2S-bus specification.

I/O

P2[12] — General purpose digital input/output pin.

I

EINT2 — External interrupt 2 input.

O

MCIDAT2 — Data line for SD/MMC interface. (LPC2368 only)

I/O

I2STX_WS — Transmit Word Select. It is driven by the master and received by theslave. Corresponds to the signal WS in the I2S-bus specification.

I/O

P2[13] — General purpose digital input/output pin.

I

EINT3 — External interrupt 3 input.

O

MCIDAT3 — Data line for SD/MMC interface. (LPC2368 only)

I/O

I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver.
Corresponds to the signal SD in the I2S-bus specification.

I/OPort 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 3 pins depends upon the pin function selected via the Pin Connect
block. Pins 0 through 24, and 27 through 31 of this port are not available.

I/O

P3[25] — General purpose digital input/output pin.

O

MAT0[0] — Match output for Timer 0, channel 0.

O

PWM1[2] — Pulse Width Modulator 1, output 2.

I/O

P3[26] — General purpose digital input/output pin.

O

MAT0[1] — Match output for Timer 0, channel 1.

O

PWM1[3] — Pulse Width Modulator 1, output 3.

I/O

Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 4 pins depends upon the pin function selected via the Pin Connect
block. Pins 0 through 27, 30, and 31 of this port are not available.

I/O

P4[28] — General purpose digital input/output pin.

O

MAT2[0] — Match output for Timer 2, channel 0.

O

TXD3 — Transmitter output for UART3.

I/O

P4[29] — General purpose digital input/output pin.

O

MAT2[1] — Match output for Timer 2, channel 1.

I

RXD3 — Receiver input for UART3.

O

TDO — Test Data out for JTAG interface.

I

TDI — Test Data in for JTAG interface.

TMS

3[1]

I

TMS — Test Mode Select for JTAG interface.

TRST

4[1]

I

TRST — Test Reset for JTAG interface.

TCK

5[1]

I

TCK — Test Clock for JTAG interface.

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Chapter 8: LPC2300 Pin configuration

Table 80.

LPC2364/66/68 pin description …continued

SymbolPin

Type

Description

RTCK

100[1]I/O

RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operateas Trace port after reset.

RSTOUT

14[1]O

RSTOUT — LOW on this pin indicates LPC2300 being in Reset state.

RESET

17[7]

I

external reset input: A LOW on this pin resets the device, causing I/O ports andperipherals to take on their default states, and processor execution to begin ataddress 0. TTL with hysteresis, 5 V tolerant.
The VBAT pin must be powered with 3.3 V for the RESET pin to detect external signal
existence and/or activity.

XTAL1

22[8]

I

Input to the oscillator circuit and internal clock generator circuits.

XTAL2

23[8]

O

Output from the oscillator amplifier.

RTCX1

16[8]

I

Input to the RTC oscillator circuit.

RTCX2

18[8]

O

Output from the RTC oscillator circuit.

VSS

15, 31,41, 55,72, 97,83[9]I

ground: 0 V reference.

VSSA

11[10]

I

analog ground: 0 V reference. This should nominally be the same voltage as VSS,
but should be isolated to minimize noise and error.

VDD(3V3)

28, 54,71,
96[11]

I

3.3 V supply voltage: This is the power supply voltage for the I/O ports.

VDD(DCDC)(3V3)13, 42,84[12]

I

3.3 V DC-to-DC converter supply voltage: This is the supply voltage for the on-chip
DC-to-DC converter only.

VDDA

10[13]

I

analog 3.3 V pad supply voltage: This should be nominally the same voltage as
VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to
power the ADC and DAC.

VREF

12[13]I

ADC reference: This should be nominally the same voltage as VDD(3V3) but should be
isolated to minimize noise and error. Level on this pin is used as a reference for ADC
and DAC.

VBAT

19[13]I

RTC and RESET pin power supply: 3.3 V on this pin supplies the power to the RTC
peripheral and the RESET pin logic.

[1]

5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[2]

5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input,
digital section of the pad is disabled.

[3]

5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.

[4]Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires an external pull-up to provide output
functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.

[5]

Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed andLow-speed mode only).

[6]

5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis[7]

5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis[8]

Pad provides special analog functionality.

[9]

Pad provides special analog functionality.

[10] Pad provides special analog functionality.
[11] Pad provides special analog functionality.
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Chapter 8: LPC2300 Pin configuration[12] Pad provides special analog functionality.
[13] Pad provides special analog functionality.

109

144

3. LPC2378 144-pin package

1108

LPC2378FBD144

72

73
37

36

002aac584

Fig 18. LPC2378 144 - pin package

4. Pin description for LPC2378
Pin description for LPC2378 and a brief explanation of corresponding functions are shownin the following table.
Table 81.

LPC2378 pin description

SymbolPinP0[0] to P0[31]P0[0]/RD1/TXD/
SDA1

P0[1]/TD1/RXD3/
SCL1

66[1]

67[1]

P0[2]/TXD0141[1]

P0[3]/RXD0142[1]

P0[4]/I2SRX_CLK/
RD2/CAP2[0]116[1]Type

Description

I/O

Port 0: Port 0 is a 32 bit I/O port with individual direction controls for each bit. The
operation of port 0 pins depends upon the pin function selected via the Pin Connect
block.

I/O

P0[0] — General purpose digital input/output pin.

I

RD1 — CAN1 receiver input.

O

TXD3 — Transmitter output for UART3.

I/O

SDA1 — I2C1 data input/output (this is not an open drain pin).

I/O

P0[1] — General purpose digital input/output pin.

O

TD1 — CAN1 transmitter output.

I

RXD3 — Receiver input for UART3.

I/O

SCL1 — I2C1 clock input/output (this is not an open drain pin).

I/O

P0[2] — General purpose digital input/output pin.

O

TXD0 — Transmitter output for UART0.

I/O

P0[3] — General purpose digital input/output pin.

I

RXD0 — Receiver input for UART0.

I/O

P0[4] — General purpose digital input/output pin.

I/O

I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I2S-bus specification.

I

RD2 — CAN2 receiver input.

I

CAP2[0] — Capture input for Timer 2, channel 0.

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Chapter 8: LPC2300 Pin configuration

Table 81.

LPC2378 pin description …continued

SymbolPin

Type

Description

P0[5]/I2SRX_WS/
TD2/CAP2[1]115[1]

I/O

P0[5] — General purpose digital input/output pin.

I/O

I2SRX_WS — Receive Word Select. It is driven by the master and received by theslave. Corresponds to the signal WS in the I2S-bus specification.

O

TD2 — CAN2 transmitter output.

I

CAP2[1] — Capture input for Timer 2, channel 1.

I/O

P0[6] — General purpose digital input/output pin.

I/O

I2SRX_SDA — Receive data. It is driven by the transmitter and read by thereceiver. Corresponds to the signal SD in the I2S-bus specification.

I/O

SSEL1 — Slave Select for SSP1.

O

MAT2[0] — Match output for Timer 2, channel 0.

I/O

P0[7] — General purpose digital input/output pin.

I/O

I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I2S-bus specification.

I/O

SCK1 — Serial Clock for SSP1.

O

MAT2[1] — Match output for Timer 2, channel 1.

I/O

P0[8] — General purpose digital input/output pin.

I/O

I2STX_WS — Transmit Word Select. It is driven by the master and received by theslave. Corresponds to the signal WS in the I2S-bus specification.

I/O

MISO1 — Master In Slave Out for SSP1.

O

MAT2[2] — Match output for Timer 2, channel 2.

I/O

P0[9] — General purpose digital input/output pin.

I/O

I2STX_SDA — Transmit data. It is driven by the transmitter and read by thereceiver. Corresponds to the signal SD in the I2S-bus specification.

I/O

MOSI1 — Master Out Slave In for SSP1.

O

MAT2[3] — Match output for Timer 2, channel 3.

I/O

P0[10] — General purpose digital input/output pin.

O

TXD2 — Transmitter output for UART2.

I/O

SDA2 — I2C2 data input/output (this is not an open drain pin).

O

MAT3[0] — Match output for Timer 3, channel 0.

I/O

P0[11] — General purpose digital input/output pin.

I

RXD2 — Receiver input for UART2.

I/O

SCL2 — I2C2 clock input/output (this is not an open drain pin).

O

MAT3[1] — Match output for Timer 3, channel 1.

I/O

P0[12] — General purpose digital input/output pin.

I/O

MISO1 — Master In Slave Out for SSP1.

I

AD0[6] — A/D converter 0, input 6.

I/O

P0[13] — General purpose digital input/output pin.

O

USB_UP_LED2 — USB2 Good Link LED indicator. It is LOW when device isconfigured (non-control endpoints enabled). It is HIGH when the device is notconfigured or during global suspend.

I/O

MOSI1 — Master Out Slave In for SSP1.

I

AD0[7] — A/D converter 0, input 7.

P0[6]/I2SRX_SDA/
SSEL1/MAT2[0]P0[7]/I2STX_CLK/SCK1/MAT2[1]P0[8]/I2STX_WS/MISO1/MAT2[2]P0[9]/I2STX_SDA/
MOSI1/MAT2[3]P0[10]/TXD2/
SDA2/MAT3 [0]P0[11]/RXD2/
SCL2/MAT3[1]P0[12]/MISO1/
AD0[6]

P0[13]/
USB_UP_LED2/
MOSI1/AD0[7]113[1]

112[1]

111[1]

109[1]

69[1]

70[1]

29[2]

32[2]

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Chapter 8: LPC2300 Pin configuration

Table 81.

LPC2378 pin description …continued

SymbolPin

Type

Description

P0[14]/
USB_CONNECT2/
SSEL1

48[1]

I/O

P0[14] — General purpose digital input/output pin.

O

USB_CONNECT2 — USB2 Soft Connect control. Signal used to switch an external
1.5 kΩ resistor under software control. Used with the SoftConnect USB feature.

I/O

SSEL1 — Slave Select for SSP1.

P0[15]/TXD1/
SCK0/SCK

89[1]

I/O

P0[15] — General purpose digital input/output pin.

O

TXD1 — Transmitter output for UART1.

I/O

SCK0 — Serial clock for SSP0.

I/O

SCK — Serial clock for SPI.

I/O

P0 [16] — General purpose digital input/output pin.

I

RXD1 — Receiver input for UART1.

I/O

SSEL0 — Slave Select for SSP0.

I/O

SSEL — Slave Select for SPI.

I/O

P0[17] — General purpose digital input/output pin.

I

CTS1 — Clear to Send input for UART1.

I/O

MISO0 — Master In Slave Out for SSP0.

I/O

MISO — Master In Slave Out for SPI.

I/O

P0[18] — General purpose digital input/output pin.

I

DCD1 — Data Carrier Detect input for UART1.

I/O

MOSI0 — Master Out Slave In for SSP0.

I/O

MOSI — Master Out Slave In for SPI.

I/O

P0[19] — General purpose digital input/output pin.

I

DSR1 — Data Set Ready input for UART1.

OMCICLK — Clock output line for SD/MMC interface.

I/O

SDA1 — I2C1 data input/output (this is not an open drain pin).

I/O

P0[20] — General purpose digital input/output pin.

O

DTR1 — Data Terminal Ready output for UART1.

I

MCICMD — Command line for SD/MMC interface.

I/O

SCL1 — I2C1 clock input/output (this is not an open drain pin).

I/O

P0[21] — General purpose digital input/output pin.

I

RI1 — Ring Indicator input for UART1.

OMCIPWR — Power Supply Enable for external SD/MMC power supply.

I

RD1 — CAN1 receiver input.

I/O

P0[22] — General purpose digital input/output pin.

O

RTS1 — Request to Send output for UART1.

OMCIDAT0 — Data line for SD/MMC interface.

O

TD1 — CAN1 transmitter output.

I/O

P0[23] — General purpose digital input/output pin.

I

AD0[0] — A/D converter 0, input 0.

I/O

I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I2S-bus specification.

I

CAP3[0] — Capture input for Timer 3, channel 0.

P0[16]/RXD1/
SSEL0/SSEL

P0[17]/CTS1/
MISO0/MISO

P0[18]/DCD1/
MOSI0/MOSI

P0[19]/DSR1/MCICLK/SDA1

P0[20]/DTR1/
MCICMD/SCL1

P0[21]/RI1/
MCIPWR/RD1

P0[22]/RTS1/
MCIDAT0/TD1

P0[23]/AD0[0]/I2SRX_CLK/
CAP3[0]

90[1]

87[1]

86[1]

85[1]

83[1]

82[1]

80[1]

13[2]

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Chapter 8: LPC2300 Pin configuration

Table 81.

LPC2378 pin description …continued

SymbolPin

Type

Description

P0[24]/AD0[1]/I2SRX_WS/
CAP3[1]

11[3]

I/O

P0[24] — General purpose digital input/output pin.

I

AD0[1] — A/D converter 0, input 1.

I/O

I2SRX_WS — Receive Word Select. It is driven by the master and received by theslave. Corresponds to the signal WS in the I2S-bus specification.

I

CAP3[1] — Capture input for Timer 3, channel 1.

P0[25]/AD0[2]/I2SRX_SDA/
TXD3

10[2]

I/O

P0[25] — General purpose digital input/output pin.

I

AD0[2] — A/D converter 0, input 2.

I/O

I2SRX_SDA — Receive data. It is driven by the transmitter and read by thereceiver. Corresponds to the signal SD in the I2S-bus specification.

O

TXD3 — Transmitter output for UART3.

P0[26]/AD0[3]/
AOUT/RXD3

8[2]

I/O

P0[26] — General purpose digital input/output pin.

I

AD0[3] — ]A/D converter 0, input 3.

O

AOUT — D/A converter output.

I

RXD3 — Receiver input for UART3.

I/O

P0[27] — General purpose digital input/output pin.

I/O

SDA0 — I2C0 data input/output. Open drain output (for I2C-bus compliance).

I/O

P0[28] — General purpose digital input/output pin.

I/O

SCL0 — I2C0 clock input/output. Open drain output (for I2C-bus compliance).

I/O

P0[29] — General purpose digital input/output pin.

I/O

USB_D+1 — USB1 port bidirectional D+ line.

I/O

P0[30] — General purpose digital input/output pin.

I/O

USB_D−1 — USB1 port bidirectional D− line.

I/O

P0[31] — General purpose digital input/output pin.

I/O

USB_D+2 — USB2 port bidirectional D+ line.

I/O

Port 1: Port 1 is a 32 bit I/O port with individual direction controls for each bit. The
operation of port 1 pins depends upon the pin function selected via the Pin Connect
block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available.

I/O

P1[0] — General purpose digital input/output pin.

O

ENET_TXD0 — Ethernet transmit data 0.

I/O

P1[1] — General purpose digital input/output pin.

O

ENET_TXD1 — Ethernet transmit data 1.

I/O

P1[4] — General purpose digital input/output pin.

O

ENET_TX_EN — Ethernet transmit data enable.

I/O

P1[8] — General purpose digital input/output pin.

I

ENET_CRS — Ethernet carrier sense.

I/O

P1[9] — General purpose digital input/output pin.

I

ENET_RXD0 — Ethernet receive data.

I/O

P1[10] — General purpose digital input/output pin.

I

ENET_RXD1 — Ethernet receive data.

I/O

P1[14] — General purpose digital input/output pin.

I

ENET_RX_ER — Ethernet receive error.

P0[27]/SDA0
P0[28]/SCL0
P0[29]/USB_D+1

35[4]
34[4]
42[5]

P0[30]/USB_D−1

43[5]P0[31]/USB_D+2

36[5]P1[0] to P1[31]P1[0]/
ENET_TXD0136[1]

P1[1]/
ENET_TXD1

135[1]

P1[4]/
ENET_TX_EN

133[1]

P1[8]/
ENET_CRS

132[1]

P1[9]/
ENET_RXD0131[1]

P1[10]/
ENET_RXD1

129[1]

P1[14]/
ENET_RX_ER

128[1]

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Chapter 8: LPC2300 Pin configuration

Table 81.

LPC2378 pin description …continued

SymbolPin

Type

Description

P1[15]/
ENET_REF_CLK

126[1]

I/O

P1[15] — General purpose digital input/output pin.

I

ENET_REF_CLK/ENET_RX_CLK — Ethernet receiver clock.

P1[16]/
ENET_MDC

125[1]

I/O

P1[16] — General purpose digital input/output pin.

I

ENET_MDC — Ethernet MIIM clock.

P1[17]/
ENET_MDIO

123[1]

I/O

P1[17] — General purpose digital input/output pin.

I/O

ENET_MDIO — Ethernet MI data input and output.

P1[18]/
USB_UP_LED1/
PWM1[1]/
CAP1[0]

46[1]

I/O

P1[18] — General purpose digital input/output pin.

O

USB_UP_LED1 — USB1 port Good Link LED indicator. It is LOW when device isconfigured (non-control endpoints enabled). It is HIGH when the device is notconfigured or during global suspend.

O

PWM1[1] — Pulse Width Modulator 1, channel 1 output.

I

CAP1[0] — Capture input for Timer 1, channel 0.

I/O

P1[19] — General purpose digital input/output pin.

I

CAP1[1] — Capture input for Timer 1, channel 1.

I/O

P1[20] — General purpose digital input/output pin.

O

PWM1[2] — Pulse Width Modulator 1, channel 2 output.

I/O

SCK0 — Serial clock for SSP0.

I/O

P1[21] — General purpose digital input/output pin.

O

PWM1[3] — Pulse Width Modulator 1, channel 3 output.

I/O

SSEL0 — Slave Select for SSP0.

I/O

P1[22] — General purpose digital input/output pin.

O

MAT1[0] — Match output for Timer 1, channel 0.

I/O

P1[23] — General purpose digital input/output pin.

O

PWM1[4] — Pulse Width Modulator 1, channel 4 output.

I/O

MISO0 — Master In Slave Out for SSP0.

I/O

P1[24] — General purpose digital input/output pin.

O

PWM1[5] — Pulse Width Modulator 1, channel 5 output.

I/O

MOSI0 — Master Out Slave in for SSP0.

I/O

P1[25] — General purpose digital input/output pin.

O

MAT1[1] — Match output for Timer 1, channel 1.

I/O

P1[26] — General purpose digital input/output pin.

O

PWM1[6] — Pulse Width Modulator 1, channel 6 output.

I

CAP0[0] — Capture input for Timer 0, channel 0.

I/O

P1[27] — General purpose digital input/output pin.

I

CAP0[1] — Capture input for Timer 0, channel 1.

I/O

P1[28] — General purpose digital input/output pin.

I

PCAP1[0] — Capture input for PWM1, channel 0.

O

MAT0[0] — Match output for Timer 0, channel 0.

I/O

P1[29] — General purpose digital input/output pin.

I

PCAP1[1] — Capture input for PWM1, channel 1.

O

MAT0[1] — Match output for Timer 0, channel 0.

P1[19]/CAP1[1]47[1]

P1[20]/PWM1[2]/
SCK0

49[1]

P1[21]/PWM1[3]/
SSEL0

50[1]

P1[22]/MAT1[0]51[1]P1[23]/PWM1[4]/
MISO0

53[1]

P1[24]/PWM1[5]/
MOSI0

54[1]

P1[25]/MAT1[1]56[1]P1[26]/PWM1[6]/CAP0[0]57[1]P1[27]/CAP0[1]61[1]P1[28]/
PCAP1[0]/MAT0[0]63[1]P1[29]/
PCAP1[1]/MAT0[1]64[1]UM10211_1

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Chapter 8: LPC2300 Pin configuration

Table 81.

LPC2378 pin description …continued

SymbolPin

Type

Description

P1[30]/
VBUS/AD0[4]

30[2]

I/O

P1[30] — General purpose digital input/output pin.

I

VBUS — Indicates the presence of USB bus power.
Note: This signal must be HIGH for USB reset to occur.

P1[31]/SCK1/
AD0[5]

28[2]P2[0] to P2[31]P2[0]/PWM1[1]/TXD1/TRACECLK

107[1]

P2[1]/PWM1[2]/RXD1/PIPESTAT0

106[1]

P2[2]/PWM1[3]/CTS1/PIPESTAT1

105[1]

P2[3]/PWM1[4]/DCD1/PIPESTAT2

100[1]

P2[4]/PWM1[5]/DSR1/TRACESYNC

99[1]P2[5]/PWM1[6]/DTR1/TRACEPKT097[1]P2[6]/PCAP1[0]/RI1/TRACEPKT1

96[1]

I

AD0[4] — A/D converter 0, input 4.

I/O

P1[31] — General purpose digital input/output pin.

I/O

SCK1 — Serial Clock for SSP1.

I

AD0[5] — A/D converter 0, input 5.

I/O

Port 2: Port 2 is a 32 bit I/O port with individual direction controls for each bit. The
operation of port 2 pins depends upon the pin function selected via the Pin Connect
block. Pins 14 through 31 of this port are not available.

I/O

P2[0] — General purpose digital input/output pin.

O

PWM1[1] — Pulse Width Modulator 1, channel 1 output.

O

TXD1 — Transmitter output for UART1.

OTRACECLK — Trace Clock.

I/O

P2[1] — General purpose digital input/output pin.

O

PWM1[2] — Pulse Width Modulator 1, channel 2 output.

I

RXD1 — Receiver input for UART1.

OPIPESTAT0 — Pipeline Status, bit 0.

I/O

P2[2] — General purpose digital input/output pin.

O

PWM1[3] — Pulse Width Modulator 1, channel 3 output.

I

CTS1 — Clear to Send input for UART1.

OPIPESTAT1 — Pipeline Status, bit 1.

I/O

P2[3] — General purpose digital input/output pin.

O

PWM1[4] — Pulse Width Modulator 1, channel 4 output.

I

DCD1 — Data Carrier Detect input for UART1.

OPIPESTAT2 — Pipeline Status, bit 2.

I/O

P2[4] — General purpose digital input/output pin.

O

PWM1[5] — Pulse Width Modulator 1, channel 5 output.

I

DSR1 — Data Set Ready input for UART1.

OTRACESYNC — Trace Synchronization.

I/O

P2[5] — General purpose digital input/output pin.

O

PWM1[6] — Pulse Width Modulator 1, channel 6 output.

O

DTR1 — Data Terminal Ready output for UART1.

OTRACEPKT0 — Trace Packet, bit 0.

I/O

P2[6] — General purpose digital input/output pin.

I

PCAP1[0] — Capture input for PWM1, channel 0.

I

RI1 — Ring Indicator input for UART1.

OTRACEPKT1 — Trace Packet, bit 1.

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Chapter 8: LPC2300 Pin configuration

Table 81.

LPC2378 pin description …continued

SymbolPin

Type

Description

P2[7]/RD2/
RTS1/
TRACEPKT2

95[1]

I/O

P2[7] — General purpose digital input/output pin.

I

RD2 — CAN2 receiver input.

O

RTS1 — Request to Send output for UART1.

OTRACEPKT2 — Trace Packet, bit 2.

I/O

P2[8] — General purpose digital input/output pin.

O

TD2 — CAN2 transmitter output.

O

TXD2 — Transmitter output for UART2.

OTRACEPKT3 — Trace Packet, bit 3.

I/O

P2[9] — General purpose digital input/output pin.

O

USB_CONNECT1 — USB1 Soft Connect control. Signal used to switch an external
1.5 kΩ resistor under the software control. Used with the SoftConnect USB feature.

I

RXD2 — Receiver input for UART2.

I

EXTIN0 — External Trigger Input.

I/O

P2[10] — General purpose digital input/output pin.

P2[8]/TD2/
TXD2/TRACEPKT3

93[1]P2[9]/
USB_CONNECT1/RXD2/EXTIN092[1]P2[10]/EINT076[6]Note: LOW on this pin while RESET is LOW forces on-chip boot-loader to take overcontrol of the part after a reset.
P2[11]/EINT1/
MCIDAT1/
I2STX_CLKP2[12]/EINT2/MCIDAT2/
I2STX_WS

P2[13]/EINT3/MCIDAT3/
I2STX_SDA

75[6]

73[6]

71[6]

P3[0] to P3[31]P3[0]/D0

137[1]

P3[1]/D1

140[1]

P3[2]/D2

144[1]

P3[3]/D3

2[1]I

EINT0 — External interrupt 0 input.

I/O

P2[11] — General purpose digital input/output pin.

I

EINT1 — External interrupt 1 input.

O

MCIDAT1 — Data line for SD/MMC interface.

I/O

I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I2S-bus specification.

I/O

P2[12] — General purpose digital input/output pin.

I

EINT2 — External interrupt 2 input.

O

MCIDAT2 — Data line for SD/MMC interface.

I/O

I2STX_WS — Transmit Word Select. It is driven by the master and received by theslave. Corresponds to the signal WS in the I2S-bus specification.

I/O

P2[13] — General purpose digital input/output pin.

I

EINT3 — External interrupt 3 input.

O

MCIDAT3 — Data line for SD/MMC interface.

I/O

I2STX_SDA — Transmit data. It is driven by the transmitter and read by thereceiver. Corresponds to the signal SD in the I2S-bus specification.

I/OPort 3: Port 3 is a 32 bit I/O port with individual direction controls for each bit. The
operation of port 3 pins depends upon the pin function selected via the Pin Connect
block. Pins 8 through 22, and 27 through 31 of this port are not available.

I/O

P3[0] — General purpose digital input/output pin.

I/O

D0 — External memory data line 0.

I/O

P3[1] — General purpose digital input/output pin.

I/O

D1 — External memory data line 1.

I/O

P3[2] — General purpose digital input/output pin.

I/O

D2 — External memory data line 2.

I/O

P3[3] — General purpose digital input/output pin.

I/O

D3 — External memory data line 3.

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Chapter 8: LPC2300 Pin configuration

Table 81.

LPC2378 pin description …continued

SymbolPin

Type

Description

P3[4]/D4

9[1]

I/O

P3[4] — General purpose digital input/output pin.

I/O

D4 — External memory data line 4.

P3[5]/D5

12[1]

I/O

P3[5] — General purpose digital input/output pin.

I/O

D5 — External memory data line 5.

I/O

P3[6] — General purpose digital input/output pin.

I/O

D6 — External memory data line 6.

I/O

P3[7] — General purpose digital input/output pin.

I/O

D7 — External memory data line 7.

I/O

P3[23] — General purpose digital input/output pin.

I

CAP0[0] — Capture input for Timer 0, channel 0.

P3[6]/D6

16[1]P3[7]/D7

19[1]P3[23]/CAP0[0]/PCAP1[0]45[1]P3[24]/CAP0[1]/
PWM1[1]40[1]P3[25]/MAT0[0]/PWM1[2]39[1]P3[26]/MAT0[1]/
PWM1[3]38[1]P4[0] to P4[31]P4[0]/A052[1]P4[1]/A1

55[1]P4[2]/A2

58[1]P4[3]/A3

68[1]P4[4]/A4

72[1]P4[5]/A5

74[1]P4[6]/A6

78[1]P4[7]/A7

84[1]P4[8]/A888[1]I

PCAP1[0] — Capture input for PWM1, channel 0.

I/O

P3[24] — General purpose digital input/output pin.

I

CAP0[1] — Capture input for Timer 0, channel 1.

O

PWM1[1] — Pulse Width Modulator 1, output 1.

I/O

P3[25] — General purpose digital input/output pin.

O

MAT0[0] — Match output for Timer 0, channel 0.

O

PWM1[2] — Pulse Width Modulator 1, output 2.

I/O

P3[26] — General purpose digital input/output pin.

O

MAT0[1] — Match output for Timer 0, channel 1.

O

PWM1[3] — Pulse Width Modulator 1, output 3.

I/O

Port 4: Port 4 is a 32 bit I/O port with individual direction controls for each bit. The
operation of port 4 pins depends upon the pin function selected via the Pin Connect
block. Pins 16 through 23, 26, and 27 of this port are not available.

I/O

P4[0] — ]General purpose digital input/output pin.

I/O

A0 — External memory address line 0.

I/O

P4[1] — General purpose digital input/output pin.

I/O

A1 — External memory address line 1.

I/O

P4[2] — General purpose digital input/output pin.

I/O

A2 — External memory address line 2.

I/O

P4[3] — General purpose digital input/output pin.

I/O

A3 — External memory address line 3.

I/O

P4[4] — General purpose digital input/output pin.

I/O

A4 — External memory address line 4.

I/O

P4[5] — General purpose digital input/output pin.

I/O

A5 — External memory address line 5.

I/O

P4[6] — General purpose digital input/output pin.

I/O

A6 — External memory address line 6.

I/O

P4[7] — General purpose digital input/output pin.

I/O

A7 — External memory address line 7.

I/O

P4[8] — General purpose digital input/output pin.

I/O

A8 — External memory address line 8.

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Chapter 8: LPC2300 Pin configuration

Table 81.

LPC2378 pin description …continued

SymbolPin

Type

Description

P4[9]/A9

91[1]

I/O

P4[9] — General purpose digital input/output pin.

I/O

A9 — External memory address line 9.

P4[10]/A10

94[1]

I/O

P4[10] — General purpose digital input/output pin.

I/O

A10 — External memory address line 10.

I/O

P4[11] — General purpose digital input/output pin.

I/O

A11 — External memory address line 11.

I/O

P4[12] — General purpose digital input/output pin.

I/O

A12 — External memory address line 12.

I/O

P4[13] — General purpose digital input/output pin.

I/O

A13 — External memory address line 13.

I/O

P4[14] — General purpose digital input/output pin.

I/O

A14 — External memory address line 14.

I/O

P4[15] — General purpose digital input/output pin.

I/O

A15 — External memory address line 15.

I/O

P4[24] — General purpose digital input/output pin.

O

OE — LOW active Output Enable signal.

I/O

P4[25] — General purpose digital input/output pin.

O

WE — LOW active Write Enable signal.

O

BLS0 — LOW active Byte Lane select signal 0.

I/O

P4 [28] — General purpose digital input/output pin.

O

MAT2[0] — Match output for Timer 2, channel 0.

O

TXD3 — Transmitter output for UART3.

I/O

P4[29] — General purpose digital input/output pin.

O

MAT2[1] — Match output for Timer 2, channel 1.

I

RXD3 — Receiver input for UART3.

I/O

P4[30] — General purpose digital input/output pin.

O

CS0 — LOW active Chip Select 0 signal.

I/O

P4[31] — General purpose digital input/output pin.

P4[11]/A11

101[1]

P4[12]/A12

104[1]

P4[13]/A13

108[1]

P4[14]/A14

110[1]

P4[15]/A15

120[1]

P4[24]/OE

127[1]

P4[25]/WE/BLS0

124[1]

P4[28]/MAT2[0]/TXD3

118[1]

P4[29]/MAT2[1]/RXD3

122[1]

P4[30]/CS0

130[1]

P4[31]/CS1

134[1]

O

CS1 — LOW active Chip Select 1 signal.

ALARM

26[8]

O

ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC
alarm is generated.

USB_D−2

37

I/O

USB_D−2 — USB2 port bidirectional D− line.

DBGEN

6[1]

I

DBGEN — JTAG interface control signal. Also used for boundary scanning.

TDO

1[1]

O

TDO — Test Data out for JTAG interface.

TDI

3[1]

I

TDI — Test Data in for JTAG interface.

TMS

4[1]

I

TMS — Test Mode Select for JTAG interface.

TRST

5[1]

I

TRST — Test Reset for JTAG interface.

TCK

7[1]

I

TCK — Test Clock for JTAG interface.

RTCK

143[1]I/O

RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operateas Trace port after reset.

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Chapter 8: LPC2300 Pin configuration

Table 81.

LPC2378 pin description …continued

SymbolPin

Type

Description

RSTOUT

20[1]O

RSTOUT — LOW on this pin indicates UM10211 being in Reset state.

RESET

24[7]

I

external reset input: A LOW on this pin resets the device, causing I/O ports andperipherals to take on their default states, and processor execution to begin ataddress 0. TTL with hysteresis, 5 V tolerant.
The VBAT pin must be powered with 3.3 V for the RESET pin to detect externalsignal existence and/or activity.

XTAL1

31[8]

I

Input to the oscillator circuit and internal clock generator circuits.

XTAL2

33[8]

O

Output from the oscillator amplifier.

RTCX1

23[8]

I

Input to the RTC oscillator circuit.

RTCX2

25[8]

O

VSS

22, 44,I59, 65,79, 103,
117,119,
139[9]

ground: 0 V reference.

VSSA

15[10]

analog ground: 0 V reference. This should nominally be the same voltage as VSS,
but should be isolated to minimize noise and error.

VDD(3V3)

41, 62,
I77, 102,114,
138[11]

3.3 V supply voltage: This is the power supply voltage for the I/O ports.

N.C.

21, 81,98[12]

I

These pins are left unconnected.

VDD(DCDC)(3V3)18, 60,121[13]I

3.3 V DC-to-DC converter supply voltage: This is the power supply for the on-chip
DC-to-DC converter only.

VDDA

14[14]

I

analog 3.3 V pad supply voltage: This should be nominally the same voltage as
VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to
power the ADC and DAC.

VREF

17[14]I

ADC reference: This should be nominally the same voltage as VDD(3V3) but should
be isolated to minimize noise and error. The level on this pin is used as a reference
for ADC and DAC.

VBAT

27[14]I

RTC and RESET pin power supply: 3.3 V on this pin supplies the power to the
RTC peripheral and the RESET pin logic.

I

Output from the RTC oscillator circuit.

[1]

5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[2]

5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input,
digital section of the pad is disabled.

[3]

5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.

[4]

Open drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires an external pull-up to provide output
functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.

[5]

Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed andLow-speed mode only).

[6]

5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

[7]

5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.

[8]

Pad provides special analog functionality.

[9]

Pad provides special analog functionality.

[10] Pad provides special analog functionality.

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Chapter 8: LPC2300 Pin configuration[11] Pad provides special analog functionality.
[12] Pad provides special analog functionality.
[13] Pad provides special analog functionality.
[14] Pad provides special analog functionality.

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UM10211
Chapter 9: Pin connect blockRev. 01 — 6 July 2007

User manual

1. Features
Allows individual pin configuration.

2. Applications
The purpose of the Pin Connect Block is to configure the microcontroller pins to thedesired functions.

3. Description
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between thepin and the on chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated, and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Selection of a single function on a port pin completely excludes all other functions
otherwise available on the same pin.

4. Pin function select register values
The PINSEL registers control the functions of device pins as shown below. Pairs of bits inthese registers correspond to specific device pins.
Table 82.

Pin function select register bits

PINSEL0 to
Function
PINSEL9 Values

Value after Reset00

Primary (default) function, typically GPIO port

00

01First alternate function

10

Second alternate function

11

Third alternate function

The direction control bit in the GPIO registers is effective only when the GPIO function is
selected for a pin. For other functions, direction is controlled automatically. Eachderivative typically has a different pinout and therefore a different set of functions possible
for each pin. Details for a specific derivative may be found in the appropriate data sheet.

5. Pin mode select register values
The PINMODE registers control the on-chip pull-up/pull-down resistor feature for all GPIO
ports. Two bits are used to control a port pin.

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Chapter 9: LPC2300 Pin connect block

Table 83.

Pin Mode Select register Bits

PINMODE0 to
PINMODE9
ValuesFunction

Value after Reset00

Pin has an on-chip pull-up resistor enabled.

00

01

Reserved. This value should not be used.

10

Pin has neither pull-up nor pull-down resistor enabled.

11

Pin has an on-chip pull-down resistor enabled.

6. Register description
The Pin Control Module contains 11 registers as shown in Table 9–84 below.
Table 84.

Pin Connect Block Register Map

Name

Description

Access Reset Value[1] Address

PINSEL0

Pin function select register 0.

R/W

0x0000 0000

0xE002 C000

PINSEL1

Pin function select register 1.

R/W

0x0000 0000

0xE002 C004

PINSEL2

Pin function select register 2.

R/W

0x0000 0000

0xE002 C008

PINSEL3

Pin function select register 3.

R/W

0x0000 0000

0xE002 C00CPINSEL4

Pin function select register 4.

R/W

0x0000 0000

0xE002 C010

PINSEL5

Pin function select register 5.

R/W

0x0000 0000

0xE002 C014

PINSEL6

Pin function select register 6.

R/W

0x0000 0000

0xE002 C018

PINSEL7

Pin function select register 7.

R/W

0x0000 0000

0xE002 C01CPINSEL8

Pin function select register 8.

R/W

0x0000 0000

0xE002 C020

PINSEL9

Pin function select register 9.

R/W

0x0000 0000

0xE002 C024

PINSEL10

Pin function select register 10.

R/W

0x0000 0000

0xE002 C028

PINMODE0

Pin mode select register 0.

R/W

0x0000 0000

0xE002 C040

PINMODE1

Pin mode select register 1.

R/W

0x0000 0000

0xE002 C044

PINMODE2

Pin mode select register 2.

R/W

0x0000 0000

0xE002 C048

PINMODE3

Pin mode select register 3.

R/W

0x0000 0000

0xE002 C04CPINMODE4

Pin mode select register 4.

R/W

0x0000 0000

0xE002 C050

PINMODE5

Pin mode select register 5.

R/W

0x0000 0000

0xE002 C054

PINMODE6

Pin mode select register 6.

R/W

0x0000 0000

0xE002 C058

PINMODE7

Pin mode select register 7.

R/W

0x0000 0000

0xE002 C05CPINMODE8

Pin mode select register 8.

R/W

0x0000 0000

0xE002 C060

PINMODE9

Pin mode select register 9.

R/W

0x0000 0000

0xE002 C064

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

Pin control module register reset values
On power-on-reset and BOD reset, all registers in this module are reset to '0'.
On external reset and watchdog reset:• The corresponding bits for P0.31:0, P1.31:0, P2.13:0 are always reset to '0'.
• For all the other bits:
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UM10211NXP Semiconductors

Chapter 9: LPC2300 Pin connect block– if the EMC_Reset_Disable = 1 ( see Section 3–7 “Other system controls and status
flags”), they retain their values for external memory interface– else if the EMC_Reset_Disable = 0, they are reset to '0'.

6.1 Pin Function Select register 0 (PINSEL0 - 0xE002 C000)
The PINSEL0 register controls the functions of the pins as per the settings listed inTable 9–85. The direction control bit in the IO0DIR register (or the FIO0DIR register if theenhanced GPIO function is selected for port 0) is effective only when the GPIO function is
selected for a pin. For other functions, direction is controlled automatically.
Table 85.

Pin function select register 0 (PINSEL0 - address 0xE002 C000) bit description

PINSEL0 Pin
name

Function when Function when 01
00

Functionwhen 10

Functionwhen 11

Reset
value

1:0

P0.0

GPIO Port 0.0

RD1

TXD3

SDA1

00

3:2

P0.1

GPIO Port 0.1

TD1

RXD3

SCL1

00

5:4

P0.2

GPIO Port 0.2

TXD0

Reserved

Reserved

00

7:6

P0.3

GPIO Port 0.3

RXD0Reserved

Reserved

00

9:8

P0.4

GPIO Port 0.4

I2SRX_CLK

RD2

CAP2.0

00

11:10

P0.5

GPIO Port 0.5

I2SRX_WS

TD2

CAP2.1

00

13:12

P0.6

GPIO Port 0.6

I2SRX_SDA

SSEL1

MAT2.0

00

15:14

P0.7

GPIO Port 0.7

I2STX_CLK

SCK1

MAT2.1

00

17:16

P0.8

GPIO Port 0.8

I2STX_WS

MISO1

MAT2.2

00

19:18

P0.9

GPIO Port 0.9

I2STX_SDA

MOSI1

MAT2.3

00

21:20

P0.10

GPIO Port 0.10

TXD2

SDA2

MAT3.0

00

23:22

P0.11

GPIO Port 0.11

RXD2

SCL2

MAT3.100

25:24[1]P0.12

GPIO Port 0.12

Reserved

MISO1

AD0.6

00

27:26[1]P0.13

GPIO Port 0.13

U2UP_LED

MOSI1

AD0.7

00

29:28[1]P0.14

GPIO Port 0.14

U2CONNECT

Reserved

SSEL1

00

31:30

P0.15

GPIO Port 0.15

TXD1

SCK0

SCK

00

[1]

LPC2378 only. These bits are reserved for LPC2364/66/68.

6.2 Pin Function Select Register 1 (PINSEL1 - 0xE002 C004)
The PINSEL1 register controls the functions of the pins as per the settings listed inTable 9–86. The direction control bit in the IO0DIR (or the FIO0DIR register if theenhanced GPIO function is selected for port 0) register is effective only when the GPIO
function is selected for a pin. For other functions direction is controlled automatically.
Table 86.

Pin function select register 1 (PINSEL1 - address 0xE002 C004) bit description

PINSEL1 Pin
name

Function when Function
00
when 01

Functionwhen 10

Functionwhen 11

1:0

P0.16

GPIO Port 0.16

RXD1

SSEL0

SSEL

00

3:2

P0.17

GPIO Port 0.17

CTS1

MISO0

MISO

00

5:4

P0.18

GPIO Port 0.18

DCD1

MOSI0

MOSI

00

7:6

P0.19

GPIO Port 0.19

DSR1

MCICLK

SDA1

00

9:8

P0.20

GPIO Port 0.20

DTR1

MCICMD

SCL1

00

UM10211_1

User manual

Reset
value

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UM10211NXP Semiconductors

Chapter 9: LPC2300 Pin connect block

Table 86.

Pin function select register 1 (PINSEL1 - address 0xE002 C004) bit description

PINSEL1 Pin
name

Function when Function
00
when 01

Functionwhen 10

Functionwhen 11

Reset
value

11:10

P0.21

GPIO Port 0.21

RI1

MCIPWR

RD1

00

13:12

P0.22

GPIO Port 0.22

RTS1

MCIDAT0

TD1

00

15:14

P0.23

GPIO Port 0.23

AD0.0

I2SRX_CLK

CAP3.0

00

17:16

P0.24

GPIO Port 0.24

AD0.1

I2SRX_WS

CAP3.1

00

19:18

P0.25

GPIO Port 0.25

AD0.2

I2SRX_SDA

TXD3

00

21:20

P0.26

GPIO Port 0.26

AD0.3

AOUT

RXD3

00

23:22

P0.27

GPIO Port 0.27

SDA0

Reserved

Reserved

00

25:24

P0.28

GPIO Port 0.28

SCL0

Reserved

Reserved

00

27:26

P0.29

GPIO Port 0.29

U1D+

Reserved

Reserved

00

29:28

P0.30

GPIO Port 0.30

U1D−

Reserved

Reserved00

31:30[1]P0.31

GPIO Port 0.31

U2D+

Reserved

Reserved00[1]

LPC2378 only. These bits are reserved for LPC2364/66/68.

6.3 Pin Function Select register 2 (PINSEL2 - 0xE002 C008)
The PINSEL2 register controls the functions of the pins as per the settings listed inTable 9–87. The direction control bit in the IO1DIR register (or the FIO1DIR register if theenhanced GPIO function is selected for port 1) is effective only when the GPIO function is
selected for a pin. For other functions, direction is controlled automatically.
Table 87.

Pin function select register 2 (PINSEL2 - address 0xE002 C008) bit description

PINSEL2 Pin
name

Function when Function when
00
01

1:0

P1.0

GPIO Port 1.0

ENET_TXD0

Reserved

Reserved

00

3:2

P1.1

GPIO Port 1.1

ENET_TXD1

Reserved

Reserved

00

5:4

P1.2

Reserved

Reserved

Reserved

Reserved

00

7:6

P1.3

Reserved

Reserved

Reserved

Reserved

00

9:8

P1.4

GPIO Port 1.4

ENET_TX_EN

Reserved

Reserved

00

11:10

P1.5

Reserved

Reserved

Reserved

Reserved

00

13:12

P1.6

Reserved

Reserved

Reserved

Reserved

00

15:14

P1.7

Reserved

Reserved

Reserved

Reserved

00

17:16

P1.8

GPIO Port 1.8

ENET_CRS

Reserved

Reserved

00

19:18

P1.9

GPIO Port 1.9

ENET_RXD0

Reserved

Reserved

00

21:20

P1.10

GPIO Port 1.10

ENET_RXD1

Reserved

Reserved

00

23:22

P1.11

Reserved

Reserved

Reserved

Reserved

00

25:24

P1.12

Reserved

Reserved

Reserved

Reserved

00

27:26

P1.13

Reserved

Reserved

Reserved

Reserved

00

29:28

P1.14

GPIO Port 1.14

ENET_RX_ER

Reserved

Reserved

00

31:30

P1.15

GPIO Port 1.15

ENET_REF_CLK Reserved

Reserved

00

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Functionwhen 11

Reset
value

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6.4 Pin Function Select Register 3 (PINSEL3 - 0xE002 C00C)The PINSEL3 register controls the functions of the pins as per the settings listed inTable 9–88. The direction control bit in the IO1DIR register (or the FIO1DIR register if theenhanced GPIO function is selected for port 1) is effective only when the GPIO function is
selected for a pin. For other functions, direction is controlled automatically.
Table 88.

Pin function select register 3 (PINSEL3 - address 0xE002 C00C) bit description

PINSEL3 Pin
name

Function when Function
00
when 01

Functionwhen 10

Functionwhen 11

Reset
value

1:0

P1.16

GPIO Port 1.16 ENET_MDC

Reserved

Reserved

00

3:2

P1.17

GPIO Port 1.17 ENET_MDIO

Reserved

Reserved

00

5:4

P1.18

GPIO Port 1.18 U1UP_LED

PWM1.1

CAP1.0

00

7:6

P1.19

GPIO Port 1.19 Reserved

Reserved

CAP1.1

00

9:8

P1.20

GPIO Port 1.20 Reserved

PWM1.2

SCK0

00

11:10

P1.21

GPIO Port 1.21 Reserved

PWM1.3

SSEL0

00

13:12

P1.22

GPIO Port 1.22 Reserved

Reserved

MAT1.0

00

15:14

P1.23

GPIO Port 1.23 Reserved

PWM1.4

MISO0

00

17:16

P1.24

GPIO Port 1.24 Reserved

PWM1.5

MOSI0

00

19:18

P1.25

GPIO Port 1.25 Reserved

Reserved

MAT1.1

00

21:20

P1.26

GPIO Port 1.26 Reserved

PWM1.6

CAP0.0

00

23:22

P1.27

GPIO Port 1.27 Reserved

Reserved

CAP0.1

00

25:24

P1.28

GPIO Port 1.28 Reserved

PCAP1.0

MAT0.0

00

27:26

P1.29

GPIO Port 1.29 Reserved

PCAP1.1

MAT0.1

00

29:28

P1.30

GPIO Port 1.30 Reserved

VBUS

AD0.4

00

31:30

P1.31

GPIO Port 1.31 Reserved

SCK1

AD0.5

00

6.5 Pin Function Select Register 4 (PINSEL4 - 0xE002 C010)
The PINSEL4 register controls the functions of the pins as per the settings listed inTable 9–89. The direction control bit in the FIO2DIR register is effective only when the
GPIO function is selected for a pin. For other functions, direction is controlled
automatically.
Table 89.

Pin function select register 4 (PINSEL4 - address 0xE002 C010) bit description

PINSEL4 Pin
name

Function when Function
00
when 01

Functionwhen 10

Function when
11

Reset
value

1:0

GPIO Port 2.0

TXD1

TRACECLK[1]

00

RXD1

PIPESTAT0[1]

00

CTS1

PIPESTAT1[1]

00
00

3:2
5:4

P2.0
P2.1
P2.2

GPIO Port 2.1
GPIO Port 2.2

PWM1.1PWM1.2
PWM1.3

7:6

P2.3

GPIO Port 2.3

PWM1.4

DCD1

PIPESTAT2[1]

9:8

P2.4

GPIO Port 2.4

PWM1.5DSR1TRACESYNC[1]

00

DTR1

TRACEPKT0[1]

00

RI1

TRACEPKT1[1]

00
00

11:10
13:12

P2.5
P2.6

GPIO Port 2.5
GPIO Port 2.6

PWM1.6
PCAP1.0

15:14

P2.7

GPIO Port 2.7

RD2

RTS1

TRACEPKT2[1]

17:16

P2.8

GPIO Port 2.8

TD2

TXD2

TRACEPKT3[1]00

EXTIN0[1]

00

19:18

P2.9

GPIO Port 2.9

U1CONNECT RXD2

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Table 89.

Pin function select register 4 (PINSEL4 - address 0xE002 C010) bit description

PINSEL4 Pin
name

Function when Function
00
when 01

Functionwhen 10

Function when
11

Reset
value

21:20

P2.10

GPIO Port 2.10

EINT0

Reserved

Reserved

00

23:22

P2.11

GPIO Port 2.11

EINT1

MCIDAT1

I2STX_CLK

00

25:24

P2.12

GPIO Port 2.12

EINT2MCIDAT2

I2STX_WS

00

27:26

P2.13

GPIO Port 2.13

EINT3MCIDAT3

I2STX_SDA

00

29:28

P2.14

Reserved

Reserved

Reserved

Reserved

00

31:30

P2.15

Reserved

Reserved

Reserved

Reserved00[1]

See Section 9–6.11 “Pin Function Select Register 10 (PINSEL10 - 0xE002 C028)”for details on using theETM functionality.

6.6 Pin Function Select Register 5 (PINSEL5 - 0xE002 C014)
The PINSEL5 register controls the functions of the pins as per the settings listed inTable 9–90. The direction control bit in the FIO2DIR register is effective only when the
GPIO function is selected for a pin. For other functions, direction is controlled
automatically.
Table 90.

Pin function select register 5 (PINSEL5 - address 0xE002 C014) bit description

PINSEL5 Pin
name

Function when Function
00
when 01

Functionwhen 10

Functionwhen 11

Reset
value

1:0

P2.16

Reserved

Reserved

Reserved

Reserved

00

3:2

P2.17

Reserved

Reserved

Reserved

Reserved

00

5:4

P2.18

Reserved

Reserved

Reserved

Reserved

00

7:6

P2.19

Reserved

Reserved

Reserved

Reserved

00

9:8

P2.20

Reserved

Reserved

Reserved

Reserved

00

11:10

P2.21

Reserved

Reserved

Reserved

Reserved

00

13:12

P2.22

Reserved

Reserved

Reserved

Reserved

00

15:14

P2.23

Reserved

Reserved

Reserved

Reserved

00

17:16

P2.24

Reserved

Reserved

Reserved

Reserved

00

19:18

P2.25

Reserved

Reserved

Reserved

Reserved

00

21:20

P2.26

Reserved

Reserved

Reserved

Reserved

00

23:22

P2.27

Reserved

Reserved

Reserved

Reserved

00

25:24

P2.28

Reserved

Reserved

Reserved

Reserved

00

27:26

P2.29

Reserved

Reserved

Reserved

Reserved

00

29:28

P2.30

Reserved

Reserved

Reserved

Reserved

00

31:30

P2.31

Reserved

Reserved

Reserved

Reserved

00

6.7 Pin Function Select Register 6 (PINSEL6 - 0xE002 C018)
The PINSEL6 register controls the functions of the pins as per the settings listed inTable 9–91. The direction control bit in the FIO3DIR register is effective only when the
GPIO function is selected for a pin. For other functions, direction is controlled
automatically.

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Table 91.

Pin function select register 6 (PINSEL6 - address 0xE002 C018) bit description

PINSEL6 Pin
name

Function when Function
00
when 01

Functionwhen 10

Functionwhen 11

Reset
value

1:0[1]

P3.0

GPIO Port 3.0

D0

Reserved

Reserved00

3:2[1]P3.1

GPIO Port 3.1

D1

Reserved

Reserved00

5:4[1]P3.2

GPIO Port 3.2

D2

Reserved

Reserved00

7:6[1]P3.3

GPIO Port 3.3

D3

Reserved

Reserved00

9:8[1]P3.4

GPIO Port 3.4

D4

Reserved

Reserved00

11:10[1]P3.5

GPIO Port 3.5

D5

Reserved

Reserved00

13:12[1]P3.6

GPIO Port 3.6

D6

Reserved

Reserved00

15:14[1]P3.7

GPIO Port 3.7

D7

Reserved

Reserved

00

17:16

P3.8

Reserved

Reserved

Reserved

Reserved

00

19:18

P3.9

Reserved

Reserved

Reserved

Reserved

00

21:20

P3.10

Reserved

Reserved

Reserved

Reserved

00

23:22

P3.11

Reserved

Reserved

Reserved

Reserved

00

25:24

P3.12

Reserved

Reserved

Reserved

Reserved

00

27:26

P3.13

Reserved

Reserved

Reserved

Reserved

00

29:28

P3.14

Reserved

Reserved

Reserved

Reserved

00

31:30

P3.15

Reserved

Reserved

Reserved

Reserved00[1]

LPC2378 only. These bits are reserved for LPC2364/66/68.

6.8 Pin Function Select Register 7 (PINSEL7 - 0xE002 C01C)
The PINSEL7 register controls the functions of the pins as per the settings listed inTable 9–92. The direction control bit in the FIO3DIR register is effective only when the
GPIO function is selected for a pin. For other functions, direction is controlled
automatically.
Table 92.

Pin function select register 7 (PINSEL7 - address 0xE002 C01C) bit description

PINSEL7 Pin
name

Function when Function
00
when 01

Functionwhen 10

Functionwhen 11

Reset
value

1:0

P3.16

Reserved

Reserved

Reserved

Reserved

00

3:2

P3.17

Reserved

Reserved

Reserved

Reserved

00

5:4

P3.18

Reserved

Reserved

Reserved

Reserved

00

7:6

P3.19

Reserved

Reserved

Reserved

Reserved

00

9:8

P3.20

Reserved

Reserved

Reserved

Reserved

00

11:10

P3.21

Reserved

Reserved

Reserved

Reserved

00

13:12

P3.22

Reserved

Reserved

Reserved

Reserved00

15:14[1]P3.23

GPIO Port 3.23

Reserved

CAP0.0

PCAP1.000

17:16[1]P3.24

GPIO Port 3.24

Reserved

CAP0.1PWM1.1

00

19:18

P3.25

GPIO Port 3.25

Reserved

MAT0.0PWM1.2

00

21:20

P3.26

GPIO Port 3.26

Reserved

MAT0.1PWM1.3

00

23:22

P3.27

Reserved

Reserved

Reserved

Reserved

00

25:24

P3.28

Reserved

Reserved

Reserved

Reserved

00

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Chapter 9: LPC2300 Pin connect block

Table 92.

Pin function select register 7 (PINSEL7 - address 0xE002 C01C) bit description

PINSEL7 Pin
name

Function when Function
00
when 01

Functionwhen 10

Functionwhen 11

Reset
value

27:26

P3.29

Reserved

Reserved

Reserved

Reserved

00

29:28

P3.30

Reserved

Reserved

Reserved

Reserved

00

31:30

P3.31

Reserved

Reserved

Reserved

Reserved00[1]

LPC2378 only. These bits are reserved for LPC2364/66/68.

6.9 Pin Function Select Register 8 (PINSEL8 - 0xE002 C020)
The PINSEL8 register controls the functions of the pins as per the settings listed inTable 9–93. The direction control bit in the FIO4DIR register is effective only when the
GPIO function is selected for a pin. For other functions, direction is controlled
automatically.
Table 93.

Pin function select register 8 (PINSEL8 - address 0xE002 C020) bit description

PINSEL8 Pin
name

Functionwhen 00

Functionwhen 01

Functionwhen 10

Functionwhen 11

Reset
value

1:0[1]

P4.0

GPIO Port 4.0

A0

Reserved

Reserved00

3:2[1]P4.1

GPIO Port 4.1

A1

Reserved

Reserved00

5:4[1]P4.2

GPIO Port 4.2

A2

Reserved

Reserved00

7:6[1]P4.3

GPIO Port 4.3

A3

Reserved

Reserved00

9:8[1]P4.4

GPIO Port 4.4

A4

Reserved

Reserved00

11:10[1]P4.5

GPIO Port 4.5

A5

Reserved

Reserved00

13:12[1]P4.6

GPIO Port 4.6

A6

Reserved

Reserved00

15:14[1]P4.7

GPIO Port 4.7

A7

Reserved

Reserved

00

17:16[1]P4.8

GPIO Port 4.8

A8

Reserved

Reserved

00

19:18[1]P4.9

GPIO Port 4.9A9

Reserved

Reserved

00

21:20[1]P4.10

GPIO Port 4.10 A10

Reserved

Reserved

00

23:22[1]P4.11

GPIO Port 4.11 A11Reserved

Reserved

00

25:24[1]P4.12

GPIO Port 4.12 A12Reserved

Reserved

00

27:26[1]P4.13

GPIO Port 4.13 A13

Reserved

Reserved

00

29:28[1]P4.14

GPIO Port 4.14 A14Reserved

Reserved00

31:30[1]P4.15

GPIO Port 4.15 A15Reserved

Reserved00[1]

LPC2378 only. These bits are reserved for LPC2364/66/68.

6.10 Pin Function Select Register 9 (PINSEL9 - 0xE002 C024)
The PINSEL9 register controls the functions of the pins as per the settings listed inTable 9–94. The direction control bit in the FIO4DIR register is effective only when the
GPIO function is selected for a pin. For other functions, direction is controlled
automatically.

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Chapter 9: LPC2300 Pin connect block

Table 94.

Pin function select register 9 (PINSEL9 - address 0xE002 C024) bit description

PINSEL9 Pin
name

Function when Function
00
when 01

Functionwhen 10

Functionwhen 11

Reset
value

1:0

P4.16

Reserved

Reserved

Reserved

Reserved

00

3:2

P4.17

Reserved

Reserved

Reserved

Reserved

00

5:4

P4.18

Reserved

Reserved

Reserved

Reserved

00

7:6

P4.19

Reserved

Reserved

Reserved

Reserved

00

9:8

P4.20

Reserved

Reserved

Reserved

Reserved

00

11:10

P4.21

Reserved

Reserved

Reserved

Reserved

00

13:12

P4.22

Reserved

Reserved

Reserved

Reserved

00

15:14

P4.23

Reserved

Reserved

Reserved

Reserved

00

17:16[1]P4.24

GPIO Port 4.24

OE

Reserved

Reserved

00

Reserved

00

19:18[1]P4.25

GPIO Port 4.25

WE

BLS0[2]

21:20

P4.26

Reserved

Reserved

Reserved

Reserved

00

23:22

P4.27

Reserved

Reserved

Reserved

Reserved

00

25:24

P4.28

GPIO Port 4.28

Reserved

MAT2.0

TXD3

00

27:26

P4.29

GPIO Port 4.29

Reserved

MAT2.1RXD300

29:28[1]P4.30

GPIO Port 4.30

CS0

Reserved

Reserved00

31:30[1]P4.31

GPIO Port 4.31

CS1

Reserved

Reserved00[1]

LPC2378 only. These bits are reserved for LPC2364/66/68.

[2]

Applies to LPC2378 only.

6.11 Pin Function Select Register 10 (PINSEL10 - 0xE002 C028)
Only bit 3 of this register is used to control the ETM interface pins.
The value of the RTCK I/O pin is sampled when the external reset is asserted. When
RTCK pin is low during external reset, bit 3 in PINSEL10 is set to enable the ETM
interface pins. When RTCK pin is high during external reset, bit 3 in PINSEL10 is cleared
to disable the ETM interface pins.
The ETM interface control pin can also be modified by the software.
Table 95.

Pin function select register 10 (PINSEL10 - address 0xE002 C028) bit description

Bit

SymbolValue Description

2:0

-

-

3

GPIO/TRACE

31:4

-

Reset
value

Reserved. Software should not write 1 to these bits. NA
ETM interface pins control.

RTCK, see
the text
above

0

ETM interface is disabled.

1

ETM interface is enabled. ETM signals are available
on the pins hosting them regardless of the PINSEL4
content.

-

Reserved. Software should not write 1 to these bits. NA

6.12 Pin Mode select register 0 (PINMODE0 - 0xE002 C040)
This register controls pull-up/pull-down resistor configuration for PORT0 pins 0 to 15.

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Chapter 9: LPC2300 Pin connect block

Table 96.

Pin Mode select register 0 (PINMODE0 - address 0xE002 C040) bit description

PINMODE0 Symbol
1:0

Value

P0.00MODE

Description

Reset
value

PORT0 pin 0 on-chip pull-up/down resistor control.

00

00

P0.00 pin has a pull-up resistor enabled.

01

Reserved. This value should not be used.

10

P0.00 pin has neither pull-up nor pull-down.

11

P0.00 has a pull-down resistor enabled.

...
31:30

P0.15MODE

PORT0 pin 15 on-chip pull-up/down resistor control. 00

6.13 Pin Mode select register 1 (PINMODE1 - 0xE002 C044)
This register controls pull-up/pull-down resistor configuration for PORT0 pins 16 to 26. For
details see Section 9–5 “Pin mode select register values”.
Table 97.

Pin Mode select register 1 (PINMODE1 - address 0xE002 C044) bit description

PINMODE1 Symbol

Description

Reset
value

1:0

P0.16MODE

PORT0 pin 16 on-chip pull-up/down resistor control.

00

21:20

P0.26MODE

PORT0 pin 26 on-chip pull-up/down resistor control.

00

31:21

-

Reserved...

Remark: Pins P0.27 and P0.28 are dedicated I2C open drain pins without pull-up/down.
Pins P0.29, P0.30, P0.31 are USB specific pins without configurable pull-up or pull-downresistors.

6.14 Pin Mode select register 2 (PINMODE2 - 0xE002 C048)
This register controls pull-up/pull-down resistor configuration for PORT1 pins 0 to 15. For
details see Section 9–5 “Pin mode select register values”.
Table 98.

Pin Mode select register 2 (PINMODE2 - address 0xE002 C048) bit description

PINMODE2 Symbol

Description

Reset
value

1:0

P1.00MODE

PORT1 pin 0 on-chip pull-up/down resistor control.

00

P1.15MODE

PORT1 pin 15 on-chip pull-up/down resistor control.

00

...
31:30

6.15 Pin Mode select register 3 (PINMODE3 - 0xE002 C04C)
This register controls pull-up/pull-down resistor configuration for PORT1 pins 16 to 31. For
details see Section 9–5 “Pin mode select register values”.

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Chapter 9: LPC2300 Pin connect block

Table 99.

Pin Mode select register 3 (PINMODE3 - address 0xE002 C04C) bit description

PINMODE3 Symbol

Description

Reset
value

1:0

P1.16MODE

PORT1 pin 16 on-chip pull-up/down resistor control.

00

P1.31MODE

PORT1 pin 31 on-chip pull-up/down resistor control.

00

...
31:30

6.16 Pin Mode select register 4 (PINMODE4 - 0xE002 C050)
This register controls pull-up/pull-down resistor configuration for PORT2 pins 0 to 15. For
details see Section 9–5 “Pin mode select register values”.
Table 100. Pin Mode select register 4 (PINMODE4 - address 0xE002 C050) bit description
PINMODE4

SymbolDescription

Reset
value

1:0

P2.00MODE

PORT2 pin 0 on-chip pull-up/down resistor control.

00

P2.15MODE

PORT2 pin 15 on-chip pull-up/down resistor control.

00

...
31:30

6.17 Pin Mode select register 5 (PINMODE5 - 0xE002 C054)
This register controls pull-up/pull-down resistor configuration for PORT2 pins 16 to 31. For
details see Section 9–5 “Pin mode select register values”.
Table 101. Pin Mode select register 5 (PINMODE5 - address 0xE002 C054) bit description
PINMODE5 Symbol

Description

Reset
value

1:0

P2.16MODE

PORT2 pin 16 on-chip pull-up/down resistor control.

00

P2.31MODE

PORT2 pin 31 on-chip pull-up/down resistor control.

00

...
31:30

6.18 Pin Mode select register 6 (PINMODE6 - 0xE002 C058)
This register controls pull-up/pull-down resistor configuration for PORT3 pins 0 to 15. For
details see Section 9–5 “Pin mode select register values”.
Table 102. Pin Mode select register 6 (PINMODE6 - address 0xE002 C058) bit description
PINMODE6 Symbol

Description

Reset
value

1:0

P3.00MODE

PORT3 pin 0 on-chip pull-up/down resistor control.

00

P3.15MODE

PORT3 pin 15 on-chip pull-up/down resistor control.

00

...
31:30

6.19 Pin Mode select register 7 (PINMODE7 - 0xE002 C05C)
This register controls pull-up/pull-down resistor configuration for PORT3 pins 16 to 31. For
details see Section 9–5 “Pin mode select register values”.

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Chapter 9: LPC2300 Pin connect block

Table 103. Pin Mode select register 7 (PINMODE7 - address 0xE002 C05C) bit description
PINMODE7 Symbol

Description

Reset
value

1:0

P3.16MODE

PORT3 pin 16 on-chip pull-up/down resistor control.

00

P3.31MODE

PORT3 pin 31 on-chip pull-up/down resistor control.

00

...
31:30

6.20 Pin Mode select register 8 (PINMODE8 - 0xE002 C060)
This register controls pull-up/pull-down resistor configuration for PORT4 pins 0 to 15. For
details see Section 9–5 “Pin mode select register values”.
Table 104. Pin Mode select register 8 (PINMODE8 - address 0xE002 C060) bit description
PINMODE8 Symbol

Description

Reset
value

1:0

P4.00MODE

PORT4 pin 0 on-chip pull-up/down resistor control.

00

P4.15MODE

PORT4 pin 15 on-chip pull-up/down resistor control.

00

...
31:30

6.21 Pin Mode select register 9 (PINMODE9 - 0xE002 C064)
This register controls pull-up/pull-down resistor configuration for PORT4 pins 16 to 31. For
details see Section 9–5 “Pin mode select register values”.
Table 105. Pin Mode select register 9 (PINMODE9 - address 0xE002 C064) bit description
PINMODE9 Symbol

Description

Reset
value

1:0

P4.16MODE

PORT4 pin 16 on-chip pull-up/down resistor control.

00

P4.31MODE

PORT4 pin 31 on-chip pull-up/down resistor control.

00

...
31:30

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Chapter 10: General Purpose Input/Output ports (GPIO)
Rev. 01 — 6 July 2007

User manual

1. Features
1.1 Digital I/O ports• GPIO PORT0 and PORT1 are ports accessible via either the group of registers
providing enhanced features and accelerated port access or the legacy group ofregisters. PORT2/3/4 are accessed as fast ports only.

• Accelerated GPIO functions:– GPIO registers are relocated to the ARM local bus so that the fastest possible I/Otiming can be achieved– Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged– All GPIO registers are byte and half-word addressable– Entire port value can be written in one instruction• Bit-level set and clear registers allow a single instruction set or clear of any number ofbits in one port

• Direction control of individual bits
• All I/O default to inputs after reset• Backward compatibility with other earlier devices is maintained with legacy registers
appearing at the original addresses on the APB bus

1.2 Interrupt generating digital ports• PORT0 and PORT2 provide an interrupt for each port pin• Each interrupt can be programmed to generate an interrupt on a rising edge, a fallingedge, or both

• Edge detection is asynchronous, so may operate when clocks are not present, suchas during Power Down mode. With this feature, level triggered interrupts are notneeded• Each enabled interrupt contributes to a Wakeup signal that can be used to bring thepart out of Power Down mode

• Registers provide software a view of pending rising edge interrupts, pending fallingedge interrupts, and overall pending GPIO interrupts• GPIO0 and GPIO2 interrupts share the same VIC slot with the External Interrupt 3
event

2. Applications• General purpose I/O• Driving LEDs, or other indicators• Controlling off-chip devices
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• Sensing digital inputs, detecting edges• Bringing the part out of Power Down mode

3. Pin description
Table 106. GPIO pin description
Pin Name

Type

Description

P0.[31:0]
P1.[31:0]
P2.[31:0]
P3.[31:0]
P4.[31:0]

Input/
OutputGeneral purpose input/output. These are typically shared with otherperipherals functions and will therefore not all be available in an
application. Packaging options may affect the number of GPIOs
available in a particular device.
Some pins may be limited by requirements of the alternate functions of
the pin. For example, I2C0 pins are open drain. Details may be found in
the LPC2300 pin description.

4. Register description
LPC2300 has up to five 32-bit General Purpose I/O ports. PORT0 and PORT1 arecontrolled via two groups of registers as shown in Table 10–107 and Table 10–108. Apartfrom them, LPC2300 can have three additional 32-bit ports, PORT2, PORT3 and PORT4.
Details on a specific GPIO port usage can be found in the "Pin Configuration" chapter on
page 90 and "Pin Connect Block" chapter on page 109.
Legacy registers shown in Table 10–107 allow backward compatibility with earlier family
devices, using existing code. The functions and relative timing of older GPIO
implementations is preserved. Only PORT0 and PORT1 can be controlled via the legacy
port registers.
The registers in Table 10–108 represent the enhanced GPIO features available on all of
the LPC2300’s GPIO ports. These registers are located directly on the local bus of the
CPU for the fastest possible read and write timing. They can be accessed as byte or
half-word long data, too. A mask register allows access to a group of bits in a single GPIO
port independently from other bits in the same port.
When PORT0 and PORT1 are used, user must select whether these ports will beaccessed via registers that provide enhanced features or a legacy set of registers (seeSection 3–7 “Other system controls and status flags” on page 28). While both of a port’s
fast and legacy GPIO registers are controlling the same physical pins, these two port
control branches are mutually exclusive and operate independently. For example,
changing a pin’s output via a fast register will not be observable via the corresponding
legacy register.
The following text will refer to the legacy GPIO as "the slow" GPIO, while GPIO equippedwith the enhanced features will be referred as "the fast" GPIO.

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Table 107. GPIO register map (legacy APB accessible registers)
Generic Description
Name

Access Reset
value[1]

PORTn Register
Address & NameIOPIN

GPIO Port Pin value register. The current state of the GPIO
R/W
configured port pins can always be read from this register,regardless of pin direction. By writing to this register port’s pins will
be set to the desired level instantaneously.

NA

IO0PIN - 0xE002 8000
IO1PIN - 0xE002 8010

IOSET

GPIO Port Output Set register. This register controls the state ofR/Woutput pins in conjunction with the IOCLR register. Writing ones
produces highs at the corresponding port pins. Writing zeroes has
no effect.

0x0

IO0SET - 0xE002 8004
IO1SET - 0xE002 8014

IODIR

GPIO Port Direction control register. This register individuallycontrols the direction of each port pin.

R/W

0x0

IO0DIR - 0xE002 8008
IO1DIR - 0xE002 8018

IOCLR

GPIO Port Output Clear register. This register controls the state of WO
output pins. Writing ones produces lows at the corresponding port
pins and clears the corresponding bits in the IOSET register.
Writing zeroes has no effect.

0x0

IO0CLR - 0xE002 800C
IO1CLR - 0xE002 801C

[1]

Reset value reflects the data stored in used bits only. It does not include reserved bits content.

Table 108. GPIO register map (local bus accessible registers - enhanced GPIO features)
Generic
Name

Description

Access Reset
PORTn Registervalue[1] Address & NameFIODIR

Fast GPIO Port Direction control register. This register
individually controls the direction of each port pin.

R/W

0x0

FIO0DIR - 0x3FFF C000
FIO1DIR - 0x3FFF C020
FIO2DIR - 0x3FFF C040
FIO2DIR - 0x3FFF C060
FIO2DIR - 0x3FFF C080

FIOMASK Fast Mask register for port. Writes, sets, clears, and reads to R/Wport (done via writes to FIOPIN, FIOSET, and FIOCLR, andreads of FIOPIN) alter or return only the bits enabled by zeros
in this register.

0x0

FIO0MASK - 0x3FFF C010
FIO1MASK - 0x3FFF C030
FIO2MASK - 0x3FFF C050
FIO3MASK - 0x3FFF C070
FIO4MASK - 0x3FFF C090

FIOPIN

0x0

FIO0PIN - 0x3FFF C014
FIO1PIN - 0x3FFF C034
FIO2PIN - 0x3FFF C054
FIO3PIN - 0x3FFF C074
FIO4PIN - 0x3FFF C094

Fast Port Pin value register using FIOMASK. The current state R/Wof digital port pins can be read from this register, regardless ofpin direction or alternate function selection (as long as pins are
not configured as an input to ADC). The value read is masked
by ANDing with inverted FIOMASK. Writing to this register
places corresponding values in all bits enabled by zeros in
FIOMASK.
Important: if a FIOPIN register is read, its bit(s) masked with 1
in the FIOMASK register will be set to 0 regardless of thephysical pin state.

FIOSET

Fast Port Output Set register using FIOMASK. This register
R/W
controls the state of output pins. Writing 1s produces highs at
the corresponding port pins. Writing 0s has no effect. Reading
this register returns the current contents of the port output
register. Only bits enabled by 0 in FIOMASK can be altered.

0x0

FIO0SET - 0x3FFF C018
FIO1SET - 0x3FFF C038
FIO2SET - 0x3FFF C058
FIO3SET - 0x3FFF C078
FIO4SET - 0x3FFF C098

FIOCLR

Fast Port Output Clear register using FIOMASK0. This register WO
controls the state of output pins. Writing 1s produces lows at
the corresponding port pins. Writing 0s has no effect. Only bits
enabled by 0 in FIOMASK0 can be altered.

0x0

FIO0CLR - 0x3FFF C01CFIO1CLR - 0x3FFF C03CFIO2CLR - 0x3FFF C05CFIO3CLR - 0x3FFF C07CFIO4CLR - 0x3FFF C09C

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[1]

Reset value reflects the data stored in used bits only. It does not include reserved bits content.

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Table 109. GPIO interrupt register map
Generic
Name

Description

Access Reset
value[1]

PORTn Register
Address & Name

IntEnR

GPIO Interrupt Enable for Rising edge.

R/W

0x0

IO0IntEnR - 0xE002 8090
IO2IntEnR - 0xE002 80B0

IntEnF

GPIO Interrupt Enable for Falling edge.

R/W

0x0

IO0IntEnR - 0xE002 8094
IO2IntEnR - 0xE002 80B4

IntStatR

GPIO Interrupt Status for Rising edge.

RO

0x0

IO0IntStatR - 0xE002 8084
IO2IntStatR - 0xE002 80A4

IntStatF

GPIO Interrupt Status for Falling edge.

RO

0x0

IO0IntStatF - 0xE002 8088
IO2IntStatF - 0xE002 80A8

IntClrGPIO Interrupt Clear.

WO

0x0

IO0IntClr - 0xE002 808C
IO2IntClr - 0xE002 80AC

IntStatus

GPIO overall Interrupt Status.

RO

0x00

IOIntStatus - 0xE002 8080

[1]

Reset value reflects the data stored in used bits only. It does not include reserved bits content.

4.1 GPIO port Direction register IODIR and FIODIR(IO[0/1]DIR 0xE002 80[0/1]8 and FIO[0/1/2/3/4]DIR - 0x3FFF C0[0/2/4/6/8]0)This word accessible register is used to control the direction of the pins when they are
configured as GPIO port pins. Direction bit for any pin must be set according to the pinfunctionality.
Legacy registers are the IO0DIR and IO1DIR while the enhanced GPIO functions aresupported via the FIO0DIR, FIO1DIR, FIO2DIR, FIO3DIR and FIO4DIR registers.
Table 110. GPIO port Direction register (IO0DIR - address 0xE002 8008 and IO1DIR - address
0xE002 8018) bit description
Bit

Symbol

31:0

P0xDIR
or
P1xDIR

Value Description

Reset
value

Slow GPIO Direction PORTx control bits. Bit 0 in IOxDIR
controls pin Px.0, bit 31 IOxDIR controls pin Px.31.
0Controlled pin is an input pin.

1

Controlled pin is an output pin.

0x0

Table 111. Fast GPIO port Direction register (FIO[0/1/2/3/4]DIR - address
0x3FFF C0[0/2/4/6/8]0) bit description
Bit

Symbol

31:0

FP0xDIR
FP1xDIR
FP2xDIR
FP3xDIR
FP4xDIR

Value Description

Reset
value

Fast GPIO Direction PORTx control bits. Bit 0 in FIOxDIR
controls pin Px.0, bit 31 in FIOxDIR controls pin Px.31.
0Controlled pin is input.

1

Controlled pin is output.

0x0

Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port
can also be controlled via several byte and half-word accessible registers listed inTable 10–112, too. Next to providing the same functions as the FIODIR register, these
additional registers allow easier and faster access to the physical port pins.

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Table 112. Fast GPIO port Direction control byte and half-word accessible register
description
Generic
Register
name

Description

FIOxDIR0

Registerlength (bits)& access

Reset
value

PORTn Register
Address & Name

Fast GPIO Port x Direction
8 (byte)control register 0. Bit 0 in
R/W
FIOxDIR0 register corresponds
to pin Px.0 ... bit 7 to pin Px.7.

0x00

FIO0DIR0 - 0x3FFF C000
FIO1DIR0 - 0x3FFF C020
FIO2DIR0 - 0x3FFF C040
FIO3DIR0 - 0x3FFF C060
FIO4DIR0 - 0x3FFF C080

FIOxDIR1

Fast GPIO Port x Direction
8 (byte)control register 1. Bit 0 in
R/W
FIOxDIR1 register corresponds
to pin Px.8 ... bit 7 to pin Px.15.

0x00

FIO0DIR1 - 0x3FFF C001
FIO1DIR1 - 0x3FFF C021
FIO2DIR1 - 0x3FFF C041
FIO3DIR1 - 0x3FFF C061
FIO4DIR1 - 0x3FFF C081

FIO0DIR2

Fast GPIO Port x Direction
8 (byte)R/W
control register 2. Bit 0 in
FIOxDIR2 register corresponds
to pin Px.16 ... bit 7 to pin
Px.23.

0x00

FIO0DIR2 - 0x3FFF C002
FIO1DIR2 - 0x3FFF C022
FIO2DIR2 - 0x3FFF C042
FIO3DIR2 - 0x3FFF C062
FIO4DIR2 - 0x3FFF C082

FIOxDIR3

Fast GPIO Port x Direction
8 (byte)control register 3. Bit 0 in
R/W
FIOxDIR3 register corresponds
to pin Px.24 ... bit 7 to pin
Px.31.

0x00

FIO0DIR3 - 0x3FFF C003
FIO1DIR3 - 0x3FFF C023
FIO2DIR3 - 0x3FFF C043
FIO3DIR3 - 0x3FFF C063
FIO4DIR3 - 0x3FFF C083

FIOxDIRL

Fast GPIO Port x Direction
control Lower half-wordregister. Bit 0 in FIOxDIRL
register corresponds to pin
Px.0 ... bit 15 to pin Px.15.

16 (half-word) 0x0000 FIO0DIRL - 0x3FFF C000
R/W
FIO1DIRL - 0x3FFF C020
FIO2DIRL - 0x3FFF C040
FIO3DIRL - 0x3FFF C060
FIO4DIRL - 0x3FFF C080

FIOxDIRU

Fast GPIO Port x Direction
control Upper half-wordregister. Bit 0 in FIOxDIRU
register corresponds to Px.16... bit 15 to Px.31.

16 (half-word) 0x0000 FIO0DIRU - 0x3FFF C002
R/W
FIO1DIRU - 0x3FFF C022
FIO2DIRU - 0x3FFF C042
FIO3DIRU - 0x3FFF C062
FIO4DIRU - 0x3FFF C082

4.2 GPIO port output Set register IOSET and FIOSET(IO[0/1]SET 0xE002 80[0/1]4 and FIO[0/1/2/3/4]SET - 0x3FFF C0[1/3/5/7/9]8)This register is used to produce a HIGH level output at the port pins configured as GPIO in
an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins.
Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing
1 to the corresponding bit in the IOSET has no effect.
Reading the IOSET register returns the value of this register, as determined by previous
writes to IOSET and IOCLR (or IOPIN as noted above). This value does not reflect theeffect of any outside world influence on the I/O pins.
Legacy registers are the IO0SET and IO1SET while the enhanced GPIOs are supported
via the FIO0SET, FIO1SET, FIO2SET, FIO3SET, and FIO4SET registers. Access to a port
pin via the FIOSET register is conditioned by the corresponding bit of the FIOMASK
register (see Section 10–4.5 “Fast GPIO port Mask register
FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF C0[1/3/5/7/9]0)”).
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Table 113. GPIO port output Set register (IO0SET - address 0xE002 8004 and IO1SET address 0xE002 8014) bit description
Bit

Symbol

31:0

P0xSETor
P1xSET

Value Description

Reset
value

Slow GPIO output value Set bits. Bit 0 in IOxSET controls pin
Px.0, bit 31 in IOxSET controls pin Px.31.
0Controlled pin output is unchanged.

1

Controlled pin output is set to HIGH.

0x0

Table 114. Fast GPIO port output Set register (FIO[0/1/2/3/4]SET - address
0x3FFF C0[1/3/5/7/9]8) bit description
Bit

SymbolValue Description

31:0

FP0xSET
FP1xSET
FP2xSET 0
FP3xSET
FP4xSET 1

Reset
value

Fast GPIO output value Set bits. Bit 0 in FIOxSET controls pin
Px.0, bit 31 in FIOxSET controls pin Px.31.

0x0

Controlled pin output is unchanged.
Controlled pin output is set to HIGH.

Aside from the 32-bit long and word only accessible FIOSET register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed inTable 10–115, too. Next to providing the same functions as the FIOSET register, these
additional registers allow easier and faster access to the physical port pins.
Table 115. Fast GPIO port output Set byte and half-word accessible register description
Generic
Register
name

Description

Registerlength (bits)& access

Reset
value

PORTn Register
Address & NameFIOxSET0

Fast GPIO Port x output Set
register 0. Bit 0 in FIOxSET0
register corresponds to pin
Px.0 ... bit 7 to pin Px.7.

8 (byte)
R/W

0x00

FIO0SET0 - 0x3FFF C018
FIO1SET0 - 0x3FFF C038
FIO2SET0 - 0x3FFF C058
FIO3SET0 - 0x3FFF C078
FIO4SET0 - 0x3FFF C098

FIOxSET1

Fast GPIO Port x output Set
register 1. Bit 0 in FIOxSET1
register corresponds to pin
Px.8 ... bit 7 to pin Px.15.

8 (byte)
R/W

0x00

FIO0SET1 - 0x3FFF C019
FIO1SET1 - 0x3FFF C039
FIO2SET1 - 0x3FFF C059
FIO3SET1 - 0x3FFF C079
FIO4SET1 - 0x3FFF C099

FIOxSET2

Fast GPIO Port x output Set
register 2. Bit 0 in FIOxSET2
register corresponds to pin
Px.16 ... bit 7 to pin Px.23.

8 (byte)
R/W

0x00

FIO0SET2 - 0x3FFF C01AFIO1SET2 - 0x3FFF C03AFIO2SET2 - 0x3FFF C05AFIO3SET2 - 0x3FFF C07AFIO4SET2 - 0x3FFF C09A

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Table 115. Fast GPIO port output Set byte and half-word accessible register description
Generic
Register
name

Description

Registerlength (bits)& access

Reset
value

PORTn Register
Address & NameFIOxSET3

Fast GPIO Port x output Set
register 3. Bit 0 in FIOxSET3
register corresponds to pin
Px.24 ... bit 7 to pin Px.31.

8 (byte)
R/W

0x00

FIO0SET3 - 0x3FFF C01B
FIO1SET3 - 0x3FFF C03B
FIO2SET3 - 0x3FFF C05B
FIO3SET3 - 0x3FFF C07B
FIO4SET3 - 0x3FFF C09B

FIOxSETL

Fast GPIO Port x output Set 16 (half-word) 0x0000 FIO0SETL - 0x3FFF C018
Lower half-word register. Bit 0 R/W
FIO1SETL - 0x3FFF C038
in FIOxSETL register
FIO2SETL - 0x3FFF C058
corresponds to pin Px.0 ... bit
FIO3SETL - 0x3FFF C078
15 to pin Px.15.
FIO4SETL - 0x3FFF C098

FIOxSETU

Fast GPIO Port x output Set 16 (half-word) 0x0000 FIO0SETU - 0x3FFF C01A
Upper half-word register. Bit 0 R/W
FIO1SETU - 0x3FFF C03A
in FIOxSETU register
FIO2SETU - 0x3FFF C05A
corresponds to Px.16 ... bit
FIO3SETU - 0x3FFF C07A
15 to Px.31.
FIO4SETU - 0x3FFF C09A

4.3 GPIO port output Clear register IOCLR and FIOCLR (IO[0/1]CLR 0xE002 80[0/1]C and FIO[0/1/2/3/4]CLR - 0x3FFF C0[1/3/5/7/9]C)This register is used to produce a LOW level output at port pins configured as GPIO in an
OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears
the corresponding bit in the IOSET register. Writing 0 has no effect. If any pin is configured
as an input or a secondary function, writing to IOCLR has no effect.
Legacy registers are the IO0CLR and IO1CLR while the enhanced GPIOs are supported
via the FIO0CLR, FIO1CLR, FIO2CLR, FIO3CLR, and FIO4CLR registers. Access to aport pin via the FIOCLR register is conditioned by the corresponding bit of the FIOMASK
register (see Section 10–4.5 “Fast GPIO port Mask register
FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF C0[1/3/5/7/9]0)”).
Table 116. GPIO port output Clear register (IO0CLR - address 0xE002 800C and IO1CLR address 0xE002 801C) bit description
Bit

Symbol

31:0

P0xCLR
or
P1xCLR

Value Description

Reset
value

Slow GPIO output value Clear bits. Bit 0 in IOxCLR controls pin
Px.0, bit 31 in IOxCLR controls pin Px.31.
0Controlled pin output is unchanged.

1

Controlled pin output is set to LOW.

0x0

Table 117. Fast GPIO port output Clear register (FIO[0/1/2/3/4]CLR - address
0x3FFF C0[1/3/5/7/9]C) bit description
Bit

SymbolValue Description

31:0

FP0xCLR
FP1xCLR
FP2xCLR 0
FP3xCLR
FP4xCLR 1

Fast GPIO output value Clear bits. Bit 0 in FIOxCLR controls pin 0x0
Px.0, bit 31 controls pin Px.31.
Controlled pin output is unchanged.
Controlled pin output is set to LOW.

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Aside from the 32-bit long and word only accessible FIOCLR register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed inTable 10–118, too. Next to providing the same functions as the FIOCLR register, these
additional registers allow easier and faster access to the physical port pins.
Table 118. Fast GPIO port output Clear byte and half-word accessible register description
Generic
Register
name

Description

FIOxCLR0Registerlength (bits)& access

Reset
value

PORTn Register
Address & Name

Fast GPIO Port x output
8 (byte)Clear register 0. Bit 0 in
WO
FIOxCLR0 registercorresponds to pin Px.0 ... bit
7 to pin Px.7.

0x00

FIO0CLR0 - 0x3FFF C01CFIO1CLR0 - 0x3FFF C03CFIO2CLR0 - 0x3FFF C05CFIO3CLR0 - 0x3FFF C07CFIO4CLR0 - 0x3FFF C09C

FIOxCLR1

Fast GPIO Port x output
8 (byte)Clear register 1. Bit 0 in
WO
FIOxCLR1 registercorresponds to pin Px.8 ... bit
7 to pin Px.15.

0x00

FIO0CLR1 - 0x3FFF C01DFIO1CLR1 - 0x3FFF C03DFIO2CLR1 - 0x3FFF C05DFIO3CLR1 - 0x3FFF C07DFIO4CLR1 - 0x3FFF C09D

FIOxCLR2

Fast GPIO Port x output
Clear register 2. Bit 0 in
FIOxCLR2 registercorresponds to pin Px.16 ...
bit 7 to pin Px.23.

8 (byte)WO

0x00

FIO0CLR2 - 0x3FFF C01E
FIO1CLR2 - 0x3FFF C03E
FIO2CLR2 - 0x3FFF C05E
FIO3CLR2 - 0x3FFF C07E
FIO4CLR2 - 0x3FFF C09E

FIOxCLR3

Fast GPIO Port x output
Clear register 3. Bit 0 in
FIOxCLR3 registercorresponds to pin Px.24 ...
bit 7 to pin Px.31.

8 (byte)WO

0x00

FIO0CLR3 - 0x3FFF C01F
FIO1CLR3 - 0x3FFF C03FFIO2CLR3 - 0x3FFF C05F
FIO3CLR3 - 0x3FFF C07F
FIO4CLR3 - 0x3FFF C09F

FIOxCLRL

Fast GPIO Port x output
Clear Lower half-wordregister. Bit 0 in FIOxCLRL
register corresponds to pin
Px.0 ... bit 15 to pin Px.15.

16 (half-word)
WO

0x0000 FIO0CLRL - 0x3FFF C01CFIO1CLRL - 0x3FFF C03CFIO2CLRL - 0x3FFF C05CFIO3CLRL - 0x3FFF C07CFIO4CLRL - 0x3FFF C09C

FIOxCLRU Fast GPIO Port x output
Clear Upper half-wordregister. Bit 0 in FIOxCLRU
register corresponds to pin
Px.16 ... bit 15 to Px.31.

16 (half-word)
WO

0x0000 FIO0CLRU - 0x3FFF C01E
FIO1CLRU - 0x3FFF C03E
FIO2CLRU - 0x3FFF C05E
FIO3CLRU - 0x3FFF C07E
FIO4CLRU - 0x3FFF C09E

4.4 GPIO port Pin value register IOPIN and FIOPIN (IO[0/1]PIN 0xE002 80[0/1]0 and FIO[0/1/2/3/4]PIN - 0x3FFF C0[1/3/5/7/9]4)
This register provides the value of port pins that are configured to perform only digital
functions. The register will give the logic value of the pin regardless of whether the pin is
configured for input or output, or as GPIO or an alternate digital function. As an example,
a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output
as selectable functions. Any configuration of that pin will allow its current logic state to beread from the corresponding IOPIN register.
If a pin has an analog function as one of its options, the pin state cannot be read if theanalog configuration is selected. Selecting the pin as an A/D input disconnects the digitalfeatures of the pin. In that case, the pin value read in the IOPIN register is not valid.
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Writing to the IOPIN register stores the value in the port output register, bypassing theneed to use both the IOSET and IOCLR registers to obtain the entire written value. Thisfeature should be used carefully in an application since it affects the entire port.
Legacy registers are the IO0PIN and IO1PIN while the enhanced GPIOs are supported
via the FIO0PIN, FIO1PIN, FIO2PIN, FIO3PIN and FIO4PIN registers. Access to a port
pin via the FIOPIN register is conditioned by the corresponding bit of the FIOMASK
register (see Section 10–4.5 “Fast GPIO port Mask register
FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF C0[1/3/5/7/9]0)”).
Only pins masked with zeros in the Mask register (see Section 10–4.5 “Fast GPIO port
Mask register FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF C0[1/3/5/7/9]0)”) will becorrelated to the current content of the Fast GPIO port pin value register.
Table 119. GPIO port Pin value register (IO0PIN - address 0xE002 8000 and IO1PIN - address
0xE002 8010) bit description
Bit

Symbol

31:0

P0xVALor
P1xVAL

Value Description

Reset
value

Slow GPIO pin value bits. Bit 0 in IOxPIN corresponds to pin
Px.0, bit 31 in IOxPIN corresponds to pin Px.31.
0Controlled pin output is set to LOW.

1

Controlled pin output is set to HIGH.

0x0

Table 120. Fast GPIO port Pin value register (FIO[0/1/2/3/4]PIN - address
0x3FFF C0[1/3/5/7/9]4) bit description
Bit

SymbolValue Description

31:0

FP0xVAL
FP1xVALFP2xVAL 0
FP3xVAL
FP4xVAL 1

Reset
value

Fast GPIO output value Set bits. Bit 0 in FIOxCLR corresponds
to pin Px.0, bit 31 in FIOxCLR corresponds to pin Px.31.

0x0

Controlled pin output is set to LOW.
Controlled pin output is set to HIGH.

Aside from the 32-bit long and word only accessible FIOPIN register, every fast GPIO port
can also be controlled via several byte and half-word accessible registers listed inTable 10–121, too. Next to providing the same functions as the FIOPIN register, these
additional registers allow easier and faster access to the physical port pins.

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Table 121. Fast GPIO port Pin value byte and half-word accessible register description
Generic
Register
name

Description

Registerlength (bits)& access

Reset
value

PORTn Register
Address & NameFIOxPIN0

Fast GPIO Port x Pin value
register 0. Bit 0 in FIOxPIN0
register corresponds to pin
Px.0 ... bit 7 to pin Px.7.

8 (byte)
R/W

0x00

FIO0PIN0 - 0x3FFF C014
FIO1PIN0 - 0x3FFF C034
FIO2PIN0 - 0x3FFF C054
FIO3PIN0 - 0x3FFF C074
FIO4PIN0 - 0x3FFF C094

FIOxPIN1

Fast GPIO Port x Pin value
register 1. Bit 0 in FIOxPIN1
register corresponds to pin
Px.8 ... bit 7 to pin Px.15.

8 (byte)
R/W

0x00

FIO0PIN1 - 0x3FFF C015
FIO1PIN1 - 0x3FFF C035
FIO2PIN1 - 0x3FFF C055
FIO3PIN1 - 0x3FFF C075
FIO4PIN1 - 0x3FFF C095

FIOxPIN2

Fast GPIO Port x Pin value
register 2. Bit 0 in FIOxPIN2
register corresponds to pin
Px.16 ... bit 7 to pin Px.23.

8 (byte)
R/W

0x00

FIO0PIN2 - 0x3FFF C016
FIO1PIN2 - 0x3FFF C036
FIO2PIN2 - 0x3FFF C056
FIO3PIN2 - 0x3FFF C076
FIO4PIN2 - 0x3FFF C096

FIOxPIN3

Fast GPIO Port x Pin value
register 3. Bit 0 in FIOxPIN3
register corresponds to pin
Px.24 ... bit 7 to pin Px.31.

8 (byte)
R/W

0x00

FIO0PIN3 - 0x3FFF C017
FIO1PIN3 - 0x3FFF C037
FIO2PIN3 - 0x3FFF C057
FIO3PIN3 - 0x3FFF C077
FIO4PIN3 - 0x3FFF C097

FIOxPINL

Fast GPIO Port x Pin value
Lower half-word register. Bit 0
in FIOxPINL registercorresponds to pin Px.0 ... bit
15 to pin Px.15.

16 (half-word) 0x0000 FIO0PINL - 0x3FFF C014
R/W
FIO1PINL - 0x3FFF C034
FIO2PINL - 0x3FFF C054
FIO3PINL - 0x3FFF C074
FIO4PINL - 0x3FFF C094

FIOxPINU

Fast GPIO Port x Pin value
Upper half-word register. Bit 0
in FIOxPINU registercorresponds to pin Px.16 ... bit
15 to Px.31.

16 (half-word) 0x0000 FIO0PINU - 0x3FFF C016
R/W
FIO1PINU - 0x3FFF C036
FIO2PINU - 0x3FFF C056
FIO3PINU - 0x3FFF C076
FIO4PINU - 0x3FFF C096

4.5 Fast GPIO port Mask register FIOMASK(FIO[0/1/2/3/4]MASK 0x3FFF C0[1/3/5/7/9]0)This register is available in the enhanced group of registers only. It is used to select port
pins that will and will not be affected by write accesses to the FIOPIN, FIOSET or FIOCLR
register. Mask register also filters out port’s content when the FIOPIN register is read.
A zero in this register’s bit enables an access to the corresponding physical pin via a reador write access. If a bit in this register is one, corresponding pin will not be changed withwrite access and if read, will not be reflected in the updated FIOPIN register. For software
examples, see Section 10–5 “GPIO usage notes” on page 135

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Table 122. Fast GPIO port Mask register (FIO[0/1/2/3/4]MASK - address
0x3FFF C0[1/3/5/7/9]0) bit description
Bit

SymbolValue Description

31:0 FP0xMASK,
FP1xMASK,
FP2xMASK,
FP3xMASK
FP4xMASK

Reset
value

Fast GPIO physical pin access control.

0x0

0Controlled pin is affected by writes to the port’s FIOSET,FIOCLR, and FIOPIN register(s). Current state of the pin canbe read from the FIOPIN register.

1

Controlled pin is not affected by writes into the port’s
FIOSET, FIOCLR and FIOPIN register(s). When the FIOPIN
register is read, this bit will not be updated with the state of
the physical pin.

Aside from the 32-bit long and word only accessible FIOMASK register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed inTable 10–123, too. Next to providing the same functions as the FIOMASK register, these
additional registers allow easier and faster access to the physical port pins.
Table 123. Fast GPIO port Mask byte and half-word accessible register description
Generic
Register
name

Description

Registerlength (bits)& access

Reset PORTn Registervalue Address & NameFIOxMASK0

Fast GPIO Port x Mask
register 0. Bit 0 in
FIOxMASK0 registercorresponds to pin Px.0 ...
bit 7 to pin Px.7.

8 (byte)
R/W

0x0

FIO0MASK0 - 0x3FFF C010
FIO1MASK0 - 0x3FFF C030
FIO2MASK0 - 0x3FFF C050
FIO3MASK0 - 0x3FFF C070
FIO4MASK0 - 0x3FFF C090

FIOxMASK1

Fast GPIO Port x Mask
register 1. Bit 0 in
FIOxMASK1 registercorresponds to pin Px.8 ...
bit 7 to pin Px.15.

8 (byte)
R/W

0x0

FIO0MASK1 - 0x3FFF C011
FIO1MASK1 - 0x3FFF C031
FIO2MASK1 - 0x3FFF C051
FIO3MASK1 - 0x3FFF C071
FIO4MASK1 - 0x3FFF C091

FIOxMASK2

8 (byte)Fast GPIO Port x Mask
register 2. Bit 0 in
R/W
FIOxMASK2 registercorresponds to pin Px.16 ...
bit 7 to pin Px.23.

0x0

FIO0MASK2 - 0x3FFF C012
FIO1MASK2 - 0x3FFF C032
FIO2MASK2 - 0x3FFF C052
FIO3MASK2 - 0x3FFF C072
FIO4MASK2 - 0x3FFF C092

FIOxMASK3

Fast GPIO Port x Mask
8 (byte)register 3. Bit 0 in
R/W
FIOxMASK3 registercorresponds to pin Px.24 ...
bit 7 to pin Px.31.

0x0

FIO0MASK3 - 0x3FFF C013
FIO1MASK3 - 0x3FFF C033
FIO2MASK3 - 0x3FFF C053
FIO3MASK3 - 0x3FFF C073
FIO4MASK3 - 0x3FFF C093

FIOxMASKL

Fast GPIO Port x Mask
Lower half-word register.
Bit 0 in FIOxMASKL
register corresponds to pin
Px.0 ... bit 15 to pin Px.15.

16(half-word)
R/W

0x0

FIO0MASKL - 0x3FFF C010
FIO1MASKL - 0x3FFF C030
FIO2MASKL - 0x3FFF C050
FIO3MASKL - 0x3FFF C070
FIO4MASKL - 0x3FFF C090

FIOxMASKU

Fast GPIO Port x Mask
Upper half-word register.
Bit 0 in FIOxMASKU
register corresponds to pin
Px.16 ... bit 15 to Px.31.

16(half-word)
R/W

0x0

FIO0MASKU - 0x3FFF C012
FIO1MASKU - 0x3FFF C032
FIO2MASKU - 0x3FFF C053
FIO3MASKU - 0x3FFF C072
FIO4MASKU - 0x3FFF C092

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4.6 GPIO overall Interrupt Status register (IOIntStatus - 0xE002 8080)
This read-only register indicates the presence of interrupt pending on all of the GPIO portsthat support GPIO interrupts. Only one bit per port is used.
Table 124. GPIO overall Interrupt Status register (IOIntStatus - address 0xE002 8080) bit
description
Bit

Symbol

0

P0Int

1

-

2

P2Int

31:2

-

Value Description

Reset
value

PORT0 GPIO interrupt pending.

00There are no pending interrupts on PORT0.

1

There is at least one pending interrupt on PORT0.

-

Reserved. The value read from a reserved bit is not defined.

NA

PORT2 GPIO interrupt pending.

00There are no pending interrupts on PORT2.

1

There is at least one pending interrupt on PORT2.

-

Reserved. The value read from a reserved bit is not defined.

NA

4.7 GPIO Interrupt Enable for Rising edge register (IO0IntEnR 0xE002 8090 and IO2IntEnR - 0xE002 80B0)
Each bit in these read-write registers enables the rising edge interrupt for thecorresponding GPIO port pin.
Table 125. GPIO Interrupt Enable for Rising edge register (IO0IntEnR - address 0xE002 8090
and IO2IntEnR - address 0xE002 80B0) bit description
Bit

Symbol

31:0

P0xER
and
P2xER

Value Description

Reset
value

Enable Rising edge. Bit 0 in IOxIntEnR corresponds to pin Px.0, 0
bit 31 in IOxIntEnR corresponds to pin Px.31.
0

Rising edge interrupt is disabled on the controlled pin.

1

Rising edge interrupt is enabled on the controlled pin.

4.8 GPIO Interrupt Enable for Falling edge register (IO0IntEnF 0xE002 8094 and IO2IntEnF - 0xE002 80B4)
Each bit in these read-write registers enables the falling edge interrupt for thecorresponding GPIO port pin.
Table 126. GPIO Interrupt Enable for Falling edge register (IO0IntEnF - address 0xE002 8094
and IO2IntEnF - address 0xE002 80B4) bit description
Bit

Symbol

31:0

P0xEF
and
P2xEF

Value Description

Enable Falling edge. Bit 0 in IOxIntEnF corresponds to pin Px.0, 0
bit 31 in IOxIntEnF corresponds to pin Px.31.
0

Falling edge interrupt is disabled on the controlled pin.

1

Falling edge interrupt is enabled on the controlled pin.

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4.9 GPIO Interrupt Status for Rising edge register (IO0IntStatR 0xE002 8084 and IO2IntStatR - 0xE002 80A4)
Each bit in these read-only registers indicates the rising edge interrupt status for thecorresponding port.
Table 127. GPIO Status for Rising edge register (IO0IntStatR - address 0xE002 8084 andIO2IntStatR - address 0xE002 80A4) bit description
Bit

Symbol

31:0

P0xREI
andP2xREI

Value Description

Reset
value

Rising Edge Interrupt status. Bit 0 in IOxIntStatR corresponds to 0
pin Px.0, bit 31 in IOxIntStatR corresponds to pin Px.31.
0

Rising edge has not been detected on the corresponding pin.

1

An interrupt is generated due to a rising edge on thecorresponding pin.

4.10 GPIO Interrupt Status for Falling edge register (IO0IntStatF 0xE002 8088 and IO2IntStatF - 0xE002 80A8)
Each bit in these read-only registers indicates the rising edge interrupt status for thecorresponding port.
Table 128. GPIO Status for Falling edge register (IO0IntStatF - address 0xE002 8088 and
IO2IntStatF - address 0xE002 80A8) bit description
Bit

Symbol

31:0

P0xFEI
and
P2xFEI

Value Description

Reset
value

Falling Edge Interrupt status. Bit 0 in IOxIntStatF corresponds to 0
pin Px.0, bit 31 in IOxIntStatF corresponds to pin Px.31.
0

Falling edge has not been detected on the corresponding pin.

1

An interrupt is generated due to a falling edge on thecorresponding pin.

4.11 GPIO Interrupt Clear register (IO0IntClr - 0xE002 808C and IO2IntClr 0xE002 80AC)
Writing a 1 into each bit in these write-only registers clears any interrupts for thecorresponding GPIO port pin.
Table 129. GPIO Status for Falling edge register (IO0IntClr - address 0xE002 808C andIO2IntClr - address 0xE002 80AC) bit description
Bit

Symbol

31:0

P0xCI
and
P2xCI

Value Description
Clear GPIO port Interrupt. Bit 0 in IOxIntClr corresponds to pin
Px.0, bit 31 in IOxIntClr corresponds to pin Px.31.
0

Corresponding bit in IOxIntStatR and/or IOxIntStatF is
unchanged.

1

Corresponding bit in IOxIntStatR and IOxStatF is cleared to 0.

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Chapter 10: LPC2300 GPIO

5. GPIO usage notes
5.1 Example 1: sequential accesses to IOSET and IOCLR affecting thesame GPIO pin/bit
State of the output configured GPIO pin is determined by writes into the pin’s port IOSET
and IOCLR registers. Last of these accesses to the IOSET/IOCLR register will determine
the final output of a pin.
In the example code:
IO0DIR = 0x0000 0080 ;pin P0.7 configured as output
IO0CLR = 0x0000 0080 ;P0.7 goes LOW
IO0SET = 0x0000 0080 ;P0.7 goes HIGH
IO0CLR = 0x0000 0080 ;P0.7 goes LOW
pin P0.7 is configured as an output (write to IO0DIR register). After this, P0.7 output is set
to low (first write to IO0CLR register). Short high pulse follows on P0.7 (write access to
IO0SET), and the final write to IO0CLR register sets pin P0.7 back to low level.

5.2 Example 2: an instantaneous output of 0s and 1s on a GPIO port
Write access to port’s IOSET followed by write to the IOCLR register results with pins
outputting 0s being slightly later then pins outputting 1s. There are systems that cantolerate this delay of a valid output, but for some applications simultaneous output of abinary content (mixed 0s and 1s) within a group of pins on a single GPIO port is required.
This can be accomplished by writing to the port’s IOPIN register.
Following code will preserve existing output on PORT0 pins P0.[31:16] and P0.[7:0] andat the same time set P0.[15:8] to 0xA5, regardless of the previous value of pins P0.[15:8]:
IO0PIN = (IO0PIN && 0xFFFF00FF) || 0x0000A500
The same outcome can be obtained using the fast port access.
Solution 1: using 32-bit (word) accessible fast GPIO registers
FIO0MASK = 0xFFFF00FF;
FIO0PIN = 0x0000A500;
Solution 2: using 16-bit (half-word) accessible fast GPIO registers
FIO0MASKL = 0x00FF;
FIO0PINL = 0xA500;
Solution 3: using 8-bit (byte) accessible fast GPIO registers
FIO0PIN1 = 0xA5;

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5.3 Writing to IOSET/IOCLR vs. IOPIN
Write to the IOSET/IOCLR register allows easy change of the port’s selected output pin(s)to high/low level at a time. Only pin/bit(s) in the IOSET/IOCLR written with 1 will be set tohigh/low level, while those written as 0 will remain unaffected. However, by just writing toeither IOSET or IOCLR register it is not possible to instantaneously output arbitrary binary
data containing a mixture of 0s and 1s on a GPIO port.
Write to the IOPIN register enables instantaneous output of a desired content on theparallel GPIO. Binary data written into the IOPIN register will affect all output configured
pins of that parallel port: 0s in the IOPIN will produce low level pin outputs and 1s in IOPIN
will produce high level pin outputs. In order to change output of only a group of port’s pins,
application must logically AND readout from the IOPIN with mask containing 0s in bits
corresponding to pins that will be changed, and 1s for all others. Finally, this result has tobe logically ORred with the desired content and stored back into the IOPIN register.
Example 2 from above illustrates output of 0xA5 on PORT0 pins 15 to 8 while preserving
all other PORT0 output pins as they were before.

5.4 Output signal frequency considerations when using the legacy andenhanced GPIO registers
The enhanced features of the fast GPIO ports available on this microcontroller make
GPIO pins more responsive to the code that has task of controlling them. In particular,software access to a GPIO pin is 3.5 times faster via the fast GPIO registers than it iswhen the legacy set of registers is used. As a result of the access speed increase, themaximum output frequency of the digital pin is increased 3.5 times, too. This tremendous
increase of the output frequency is not always that visible when a plain C code is used,
and a portion of an application handling the fast port output might have to be written inassembly code and executed in the ARM mode.

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Chapter 11: Ethernet controller
Rev. 01 — 6 July 2007

User manual

1. Introduction
Remark: LPC21364/6/8/78 devices are RMII interfaced only.
The Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media
Access Controller) designed to provide optimized performance through the use of DMA
hardware acceleration. Features include a generous suite of control registers, half or full
duplex operation, flow control, control frames, hardware acceleration for transmit retry,receive packet filtering and wake-up on LAN activity. Automatic frame transmission andreception with Scatter-Gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share a dedicated AHB subsystem (AHB2) that is used
to access the Ethernet SRAM for Ethernet data, control, and status information. All other
AHB traffic in the LPC2300 takes place on a different AHB subsystem, effectively
separating Ethernet activity from the rest of the system. The Ethernet DMA can also
access off-chip memory via the External Memory Controller, as well as the SRAM locatedon AHB1, if is not being used by the USB block. However, using memory other than the
Ethernet SRAM, especially off-chip memory (possible in LPC2378 only), will slow
Ethernet access to memory and increase the loading of AHB1.
The Ethernet block interfaces between an off-chip Ethernet PHY using the MII (Media
Independent Interface) or RMII (reduced MII) protocol. and the on-chip MIIM (Media
Independent Interface Management) serial bus.
Table 130. Ethernet acronyms, abbreviations, and definitions
Acronym or
Abbreviation

Definition

AHB

Advanced High-performance bus

CRC

Cyclic Redundancy Check

DMA

Direct Memory Access

Double-word

64 bit entity

FCS

Frame Check Sequence (CRC)

Fragment

A (part of an) Ethernet frame; one or multiple fragments can add up to a single
Ethernet frame.

Frame

An Ethernet frame consists of destination address, source address, length
type field, payload and frame check sequence.

Half-word

16 bit entity

LAN

Local Area Network

MAC

Media Access Control sublayer

MIIMedia Independent Interface

MIIM

MII management

Octet

An 8 bit data entity, used in lieu of "byte" by IEEE 802.3

PacketA frame that is transported across Ethernet; a packet consists of a preamble,
a start of frame delimiter and an Ethernet frame.

PHY

Ethernet Physical Layer

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Table 130. Ethernet acronyms, abbreviations, and definitions
Acronym or
Abbreviation

Definition

RMII

Reduced MII

Rx

Receive

TCP/IP

Transmission Control Protocol / Internet Protocol. The most common
high-level protocol used with Ethernet.

Tx

Transmit

VLAN

Virtual LAN

WoL

Wake-up on LAN

Word

32 bit entity

2. Features• Ethernet standards support:– Supports 10 or 100 Mbps PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex backpressure.
– Flexible transmit and receive frame options.
– VLAN frame support.

• Memory management:– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and pre-fetching.

• Enhanced Ethernet features:– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic FCS insertion (CRC) for transmit.
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision backoff and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using thereceive filters or a magic frame detection filter.

• Physical interface:– Attachment of external PHY chip through standard Media Independent Interface(MII) or standard Reduced MII (RMII) interface, software selectable.

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Chapter 11: LPC2300 Ethernet– PHY register access is available via the Media Independent Interface Management(MIIM) interface.

3. Architecture and operation

TRANSMITDMA

TRANSMITRETRY

RECEIVE
DMA

RECEIVE
BUFFERR MII A DAP TER

TRANSMITFLOW
CONTROLETH ER N ET MAC

HOST
REGISTERSRMIIMII orRMIIMIIET HE RN ET PHY

DMA interface(AHB master)BU SIN TER F ACE

registerinterface (AHB
slave)

BUS IN T ERF AC E

AH B BU S

Figure 11–19 shows the internal architecture of the Ethernet block.

MIIM
RECEIVEFILTERETHERNETBLOCK

Fig 19. Ethernet block diagram

The block diagram for the Ethernet block consists of:• The host registers module containing the registers in the software view and handling
AHB accesses to the Ethernet block. The host registers connect to the transmit andreceive datapath as well as the MAC.

• The DMA to AHB interface. This provides an AHB master connection that allows the
Ethernet block to access the Ethernet SRAM for reading of descriptors, writing ofstatus, and reading and writing data buffers.

• The Ethernet MAC and attached RMII adapter. The MAC interfaces to the off-chip
PHY.

• The transmit datapath, including:– The transmit DMA manager which reads descriptors and data from memory andwrites status to memory.
– The transmit retry module handling Ethernet retry and abort situations.
– The transmit flow control module which can insert Ethernet pause frames.

• The receive datapath, including:– The receive DMA manager which reads descriptors from memory and writes dataand status to memory.
– The Ethernet MAC which detects frame types by parsing part of the frame header.
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Chapter 11: LPC2300 Ethernet– The receive filter which can filter out certain Ethernet frames by applying different
filtering schemes.
– The receive buffer implementing a delay for receive frames to allow the filter tofilter out certain frames before storing them to memory.

4. DMA engine functions
The Ethernet block is designed to provide optimized performance via DMA hardware
acceleration. Independent scatter/gather DMA engines connected to the AHB bus off-loadmany data transfers from the ARM7 CPU.
Descriptors, which are stored in memory, contain information about fragments of incomingor outgoing Ethernet frames. A fragment may be an entire frame or a much smaller
amount of data. Each descriptor contains a pointer to a memory buffer that holds dataassociated with a fragment, the size of the fragment buffer, and details of how thefragment will be transmitted or received.
Descriptors are stored in arrays in memory, which are located by pointer registers in the
Ethernet block. Other registers determine the size of the arrays, point to the next
descriptor in each array that will be used by the DMA engine, and point to the next
descriptor in each array that will be used by the Ethernet device driver.

5. Overview of DMA operation
The DMA engine makes use of a Receive descriptor array and a Transmit descriptor arrayin memory. All or part of an Ethernet frame may be contained in a memory buffer
associated with a descriptor. When transmitting, the transmit DMA engine uses as many
descriptors as needed (one or more) to obtain (gather) all of the parts of a frame, andsends them out in sequence. When receiving, the receive DMA engine also uses as many
descriptors as needed (one or more) to find places to store (scatter) all of the data in thereceived frame.
The base address registers for the descriptor array, registers indicating the number ofdescriptor array entries, and descriptor array input/output pointers are contained in the
Ethernet block. The descriptor entries and all transmit and receive packet data are stored
in memory which is not a part of the Ethernet block. The descriptor entries tell whererelated frame data is stored in memory, certain aspects of how the data is handled, andthe result status of each Ethernet transaction.
Hardware in the DMA engine controls how data incoming from the Ethernet MAC is saved
to memory, causes fragment related status to be saved, and advances the hardware
receive pointer for incoming data. Driver software must handle the disposition of received
data, changing of descriptor data addresses (to avoid unnecessary data movement), andadvancing the software receive pointer. The two pointers create a circular queue in thedescriptor array and allow both the DMA hardware and the driver software to know which
descriptors (if any) are available for their use, including whether the descriptor array is
empty or full.

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Chapter 11: LPC2300 Ethernet

Similarly, driver software must set up pointers to data that will be transmitted by the
Ethernet MAC, giving instructions for each fragment of data, and advancing the softwaretransmit pointer for outgoing data. Hardware in the DMA engine reads this information andsends the data to the Ethernet MAC interface when possible, updating the status andadvancing the hardware transmit pointer.

6. Ethernet Packet
Figure 11–20 illustrates the different fields in an Ethernet packet.

ethernet packet
PREAMBLE
7 bytesETHERNET FRAME

start-of-framedelimiter
1 byteDESTINATIONADDRESSSOURCEADDRESSOPTIONAL
VLAN

LEN
TYPE

DesA
oct6

DesA
oct5

DesA
oct4

DesA
oct3

DesA
oct2

DesA
oct1

SrcA
oct6

SrcA
oct5

LSB
oct(0)

oct(1)

oct(2)

oct(3)

oct(4)

oct(5)

oct(6)MSB
oct(7)PAYLOAD

SrcA
oct4

SrcA
oct3

FCS

SrcA
oct2

SrcA
oct1

time

Fig 20. Ethernet packet fields

A packet consists of a preamble, a start-of-frame delimiter and an Ethernet frame.
The Ethernet frame consists of the destination address, the source address, an optional
VLAN field, the length/type field, the payload and the frame check sequence.
Each address consists of 6 bytes where each byte consists of 8 bits. Bits are transferredstarting with the least significant bit.

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Chapter 11: LPC2300 Ethernet

7. Overview
7.1 Partitioning
The Ethernet block and associated device driver software offer the functionality of theMedia Access Control (MAC) sublayer of the data link layer in the OSI reference model(see IEEE std 802.3). The MAC sublayer offers the service of transmitting and receiving
frames to the next higher protocol level, the MAC client layer, typically the Logical Link
Control sublayer. The device driver software implements the interface to the MAC client
layer. It sets up registers in the Ethernet block, maintains descriptor arrays pointing toframes in memory and receives results back from the Ethernet block through interrupts.
When a frame is transmitted, the software partially sets up the Ethernet frames by
providing pointers to the destination address field, source address field, the length/typefield, the MAC client data field and optionally the CRC in the frame check sequence field.
Preferably concatenation of frame fields should be done by using the scatter/gather
functionality of the Ethernet core to avoid unnecessary copying of data. The hardware
adds the preamble and start frame delimiter fields and can optionally add the CRC, if
requested by software. When a packet is received the hardware strips the preamble andstart frame delimiter and passes the rest of the packet - the Ethernet frame - to the device
driver, including destination address, source address, length/type field, MAC client data
and frame check sequence (FCS).
Apart from the MAC, the Ethernet block contains receive and transmit DMA managers that
control receive and transmit data streams between the MAC and the AHB interface.
Frames are passed via descriptor arrays located in host memory, so that the hardware
can process many frames without software/CPU support. Frames can consist of multiple
fragments that are accessed with scatter/gather DMA. The DMA managers optimize
memory bandwidth using prefetching and buffering.
A receive filter block is used to identify received frames that are not addressed to thisEthernet station, so that they can be discarded. The Rx filters include a perfect addressfilter and a hash filter.
Wake-on-LAN power management support makes it possible to wake the system up froma power-down state -a state in which some of the clocks are switched off -when wake-up
frames are received over the LAN. Wake-up frames are recognized by the receive filtering
modules or by a Magic Frame detection technology. System wake-up occurs by triggering
an interrupt.
An interrupt logic block raises and masks interrupts and keeps track of the cause ofinterrupts. The interrupt block sends an interrupt request signal to the host system.
Interrupts can be enabled, cleared and set by software.
Support for IEEE 802.3/clause 31 flow control is implemented in the flow control block.
Receive flow control frames are automatically handled by the MAC. Transmit flow control
frames can be initiated by software. In half duplex mode, the flow control module will
generate back pressure by sending out continuous preamble only, interrupted by pauses
to prevent the jabber limit from being exceeded.
The Ethernet block has both a standard IEEE 802.3/clause 22 Media Independent
Interface (MII) bus and a Reduced Media Independent Interface (RMII) to connect to an
external Ethernet PHY chip. MII or RMII mode can be selected by the RMII bit in theCommand register. The standard nibble-wide MII interface allows a low speed data
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connection to the PHY chip: 2.5 MHz at 10 Mbps or 25 MHz at 100 Mbps. The RMII
interface allows a low pin count double clock data connection to the PHY. Registers in the
PHY chip are accessed via the AHB interface through the serial management connectionof the MII bus (MIIM) operating at 2.5 MHz.

7.2 Example PHY Devices
Some examples of compatible PHY devices are shown in Table 11–131.
Table 131. Example PHY Devices
Manufacturer

Part Number(s)Broadcom

BCM5221

ICS

ICS1893

Intel

LXT971A

LSI Logic

L80223, L80225, L80227

Micrel

KS8721

National

DP83847, DP83846, DP83843

SMSC

LAN83C185

8. Pin description
Table 11–132 shows the signals used for the Reduced Media Independent Interface(RMII) to the external PHY.
Table 132. Ethernet RMII pin descriptions
Pin NameType

Pin Description

ENET_TX_EN

OutputTransmit data enable

ENET_TXD[1:0]OutputTransmit data, 2 bits

ENET_RXD[1:0]

Input

Receive data, 2 bits.

ENET_RX_ER

Input

Receive error.

ENET_CRS

Input

Carrier sense/data valid.

ENET_REF_CLK

Input

Reference clock

Table 11–133 shows the signals used for Media Independent Interface Management(MIIM) of the external PHY.
Table 133. Ethernet MIIM pin descriptions
Pin NameType

Pin Description

ENET_MDC

OutputMIIM clock.

ENET_MDIO

Input/Output

MI data input and output

9. Registers and software interface
The software interface of the Ethernet block consists of a register view and the format
definitions for the transmit and receive descriptors. These two aspects are addressed in
the next two subsections.

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9.1 Register map
Table 11–134 lists the registers, register addresses and other basic information. The total
AHB address space required is 4 kilobytes.
After a hard reset or a soft reset via the RegReset bit of the Command register all bits inall registers are reset to 0 unless stated otherwise in the following register descriptions.
Some registers will have unused bits which will return a 0 on a read via the AHB interface.
Writing to unused register bits of an otherwise writable register will not have side effects.
The register map consists of registers in the Ethernet MAC and registers around the corefor controlling DMA transfers, flow control and filtering.
Reading from reserved addresses or reserved bits leads to unpredictable data. Writing toreserved addresses or reserved bits has no effect.
Reading of write-only registers will return a read error on the AHB interface. Writing ofread-only registers will return a write error on the AHB interface.
Table 134. Register definitions
SymbolAddress

R/W Description

MAC1

0xFFE0 0000

R/W MAC configuration register 1.

MAC2

0xFFE0 0004

R/W MAC configuration register 2.

IPGT

0xFFE0 0008

R/W Back-to-Back Inter-Packet-Gap register.

IPGR

0xFFE0 000C

R/W Non Back-to-Back Inter-Packet-Gap register.

MAC registers

CLRT

0xFFE0 0010

R/W Collision window / Retry register.

MAXF

0xFFE0 0014

R/W Maximum Frame register.

SUPP

0xFFE0 0018

R/W PHY Support register.

TEST

0xFFE0 001C

R/W Test register.

MCFG

0xFFE0 0020

R/W MII Mgmt Configuration register.

MCMD

0xFFE0 0024

R/W MII Mgmt Command register.

MADR

0xFFE0 0028

R/W MII Mgmt Address register.

MWTD

0xFFE0 002C

WO

MII Mgmt Write Data register.

MRDD

0xFFE0 0030

RO

MII Mgmt Read Data register.

MIND

0xFFE0 0034

RO

MII Mgmt Indicators register.

-

0xFFE0 0038 to 0xFFE0 00FC

SA0

0xFFE0 0040

R/W Station Address 0 register.

SA1

0xFFE0 0044

R/W Station Address 1 register.

SA2

0xFFE0 0048

R/W Station Address 2 register.

-

0xFFE0 004C to 0xFFE0 00FC

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit
is not defined.

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit
is not defined.

Control registers
Command0xFFE0 0100

R/W Command register.

Status0xFFE0 0104

RO

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Table 134. Register definitions
SymbolAddress

R/W Description

RxDescriptor

0xFFE0 0108

R/W Receive descriptor base address register.

RxStatus

0xFFE0 010C

R/W Receive status base address register.

RxDescriptorNumber 0xFFE0 0110

R/W Receive number of descriptors register.

RxProduceIndex

0xFFE0 0114

RO

RxConsumeIndex

0xFFE0 0118

R/W Receive consume index register.

TxDescriptor

0xFFE0 011C

R/W Transmit descriptor base address register.

TxStatus

0xFFE0 0120

R/W Transmit status base address register.

TxDescriptorNumber

0xFFE0 0124

R/W Transmit number of descriptors register.

TxProduceIndex

0xFFE0 0128

R/W Transmit produce index register.

TxConsumeIndex

0xFFE0 012C

RO-

0xFFE0 0130 to 0xFFE0 0154

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit
is not defined.

TSV0

0xFFE0 0158

RO

Transmit status vector 0 register.

TSV1

0xFFE0 015C

RO

Transmit status vector 1 register.

RSV

0xFFE0 0160

RO

Receive status vector register.

-

0xFFE0 0164 to 0xFFE0 016C

FlowControlCounter0xFFE0 0170

R/W Flow control counter register.

FlowControlStatus

0xFFE0 0174

RO-

0xFFE0 0178 to 0xFFE0 01FC

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit
is not defined.

RxFliterCtrl

0xFFE0 0200

Receive filter control register.

RxFilterWoLStatus

0xFFE0 0204

Receive filter WoL status register.

RxFilterWoLClear

0xFFE0 0208

Receive filter WoL clear register.

-

0xFFE0 020C

HashFilterL

0xFFE0 0210

Hash filter table LSBs register.

HashFilterH

0xFFE0 0214

Hash filter table MSBs register.

-

0xFFE0 0218 to 0xFFE0 0FDC

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit
is not defined.

Receive produce index register.

Transmit consume index register.

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit
is not defined.
Flow control status register.

Rx filter registers-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit
is not defined.

Module control registers
IntStatus

0xFFE0 0FE0

RO

IntEnable

0xFFE0 0FE4

R/W Interrupt enable register.

IntClear

0xFFE0 0FE8

WO

Interrupt clear register.

IntSet0xFFE0 0FEC

WO

Interrupt set register.

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Table 134. Register definitions
SymbolAddress

R/W Description-

0xFFE0 0FF0-

PowerDown

0xFFE0 0FF4

R/W Power-down register.

-

0xFFE0 0FF8-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit
is not defined.
Reserved, user software should not write ones toreserved bits. The value read from a reserved bit
is not defined.

The third column in the table lists the accessibility of the register: read-only, write-only,
read/write.
All AHB register write transactions except for accesses to the interrupt registers areposted i.e. the AHB transaction will complete before write data is actually committed to theregister. Accesses to the interrupt registers will only be completed by accepting the write
data when the data has been committed to the register.

10. Ethernet MAC register definitions
This section defines the bits in the individual registers of the Ethernet block register map.

10.1 MAC Configuration Register 1 (MAC1 - 0xFFE0 0000)
The MAC configuration register 1 (MAC1) has an address of 0xFFE0 0000. Its bit
definition is shown in Table 11–135.
Table 135. MAC Configuration register 1 (MAC1 - address 0xFFE0 0000) bit description
Bit

SymbolFunction

Reset
value

0

RECEIVE ENABLE

Set this to allow receive frames to be received. Internally the MAC synchronizes
this control bit to the incoming receive stream.

0

1

PASS ALL RECEIVE
FRAMES

When enabled (set to ’1’), the MAC will pass all frames regardless of type (normal
vs. Control). When disabled, the MAC does not pass valid Control frames.

02

RX FLOW CONTROL When enabled (set to ’1’), the MAC acts upon received PAUSE Flow Control
frames. When disabled, received PAUSE Flow Control frames are ignored.

03

TX FLOW CONTROL

When enabled (set to ’1’), PAUSE Flow Control frames are allowed to betransmitted. When disabled, Flow Control frames are blocked.

0

4

LOOPBACK

Setting this bit will cause the MAC Transmit interface to be looped back to the MAC 0
Receive interface. Clearing this bit results in normal operation.

7:5-

Unused0x0

8

RESET TX

Setting this bit will put the Transmit Function logic in reset.

0

9

RESET MCS / TX

Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic
implements flow control.

0

10

RESET RX

Setting this bit will put the Ethernet receive logic in reset.

0

11

RESET MCS / RX

Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic
implements flow control.

0x0

Reserved. User software should not write ones to reserved bits. The value readfrom a reserved bit is not defined.

0x0

13:12 -

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Table 135. MAC Configuration register 1 (MAC1 - address 0xFFE0 0000) bit description
Bit

SymbolFunction

14

SIMULATION RESET Setting this bit will cause a reset to the random number generator within theTransmit Function.

0

15

SOFT RESET

Setting this bit will put all modules within the MAC in reset except the HostInterface.

1

Reserved. User software should not write ones to reserved bits. The value readfrom a reserved bit is not defined.

0x0

31:16 -

Reset
value

10.2 MAC Configuration Register 2 (MAC2 - 0xFFE0 0004)
The MAC configuration register 2 (MAC2) has an address of 0xFFE0 0004. Its bit
definition is shown in Table 11–136.
Table 136. MAC Configuration register 2 (MAC2 - address 0xFFE0 0004) bit description
Bit

SymbolFunction

Reset
value

0

FULL-DUPLEX

When enabled (set to ’1’), the MAC operates in Full-Duplex mode. When disabled,
the MAC operates in Half-Duplex mode.

0

1

FRAME LENGTHCHECKING

When enabled (set to ’1’), both transmit and receive frame lengths are compared to 0
the Length/Type field. If the Length/Type field represents a length then the check is
performed. Mismatches are reported in the StatusInfo word for each received frame.

2

HUGE FRAME
ENABLE

When enabled (set to ’1’), frames of any length are transmitted and received.

03

DELAYED CRC

This bit determines the number of bytes, if any, of proprietary header informationthat exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignoredby the CRC function) are added. When 0, there is no proprietary header.

0

4

CRC ENABLE

Set this bit to append a CRC to every frame whether padding was required or not.
Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the
MAC contain a CRC.

05

PAD / CRC ENABLE

Set this bit to have the MAC pad all short frames. Clear this bit if frames presented 0
to the MAC have a valid length. This bit is used in conjunction with AUTO PADENABLE and VLAN PAD ENABLE. See Table 11–138 - Pad Operation for details on
the pad function.

6

VLAN PAD ENABLE

Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid 0
CRC. Consult Table 11–138 - Pad Operation for more information on the various
padding features.
Note: This bit is ignored if PAD / CRC ENABLE is cleared.

7

AUTO DETECT PAD
ENABLESet this bit to cause the MAC to automatically detect the type of frame, either tagged 0
or un-tagged, by comparing the two octets following the source address with
0x8100 (VLAN Protocol ID) and pad accordingly. Table 11–138 - Pad Operation
provides a description of the pad function based on the configuration of this register.
Note: This bit is ignored if PAD / CRC ENABLE is cleared.

8

PURE PREAMBLE
ENFORCEMENT

When enabled (set to ’1’), the MAC will verify the content of the preamble to ensure 0
it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded.
When disabled, no preamble checking is performed.

9

LONG PREAMBLE
ENFORCEMENT

When enabled (set to ’1’), the MAC only allows receive packets which containpreamble fields less than 12 bytes in length. When disabled, the MAC allows any
length preamble as per the Standard.

0

11:10

-

Reserved. User software should not write ones to reserved bits. The value readfrom a reserved bit is not defined.

0x0

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Table 136. MAC Configuration register 2 (MAC2 - address 0xFFE0 0004) bit description
Bit

SymbolFunction

Reset
value

12

NO BACKOFFWhen enabled (set to ’1’), the MAC will immediately retransmit following a collision
rather than using the Binary Exponential Backoff algorithm as specified in theStandard.

013

BACK PRESSURE /NO BACKOFFWhen enabled (set to ’1’), after the MAC incidentally causes a collision during back 0
pressure, it will immediately retransmit without backoff, reducing the chance offurther collisions and ensuring transmit packets get sent.

14

EXCESS DEFER

When enabled (set to ’1’) the MAC will defer to carrier indefinitely as per theStandard. When disabled, the MAC will abort when the excessive deferral limit isreached.

0

31:15

-

Reserved. User software should not write ones to reserved bits. The value readfrom a reserved bit is not defined.

0x0

Table 137. Pad operation
Type

Auto detect VLAN pad
pad enable enable
MAC2 [7]MAC2 [6]Pad/CRC
enable
MAC2 [5]Action

Any

x

x

0

No pad or CRC check

Any

0

0

1

Pad to 60 bytes, append CRC

Any

x

1

1

Pad to 64 bytes, append CRC

Any

1

0

1

If untagged, pad to 60 bytes and append CRC. If VLAN tagged: pad to
64 bytes and append CRC.

10.3 Back-to-Back Inter-Packet-Gap Register (IPGT - 0xFFE0 0008)
The Back-to-Back Inter-Packet-Gap register (IPGT) has an address of 0xFFE0 0008. Its
bit definition is shown in Table 11–138.
Table 138. Back-to-back Inter-packet-gap register (IPGT - address 0xFFE0 0008) bit description
Bit

SymbolFunction

Reset
value

6:0

BACK-TO-BACK
INTER-PACKET-GAP

This is a programmable field representing the nibble time offset of the minimum 0x0
possible period between the end of any transmitted packet to the beginning of thenext. In Full-Duplex mode, the register value should be the desired period in
nibble times minus 3. In Half-Duplex mode, the register value should be thedesired period in nibble times minus 6. In Full-Duplex the recommended setting is
0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or
9.6 µs (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d),
which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs(in 10 Mbps mode).

31:7

-

Reserved. User software should not write ones to reserved bits. The value readfrom a reserved bit is not defined.

0x0

10.4 Non Back-to-Back Inter-Packet-Gap Register (IPGR - 0xFFE0 000C)
The Non Back-to-Back Inter-Packet-Gap register (IPGR) has an address of
0xFFE0 000C. Its bit definition is shown in Table 11–139.

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Table 139. Non Back-to-back Inter-packet-gap register (IPGR - address 0xFFE0 000C) bit description
Bit

SymbolFunction

Reset
value

6:0

NON-BACK-TO-BACK
INTER-PACKET-GAP PART2

This is a programmable field representing the Non-Back-to-Back
Inter-Packet-Gap. The recommended value is 0x12 (18d), which
represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in10 Mbps mode).

0x0

7

-

Reserved. User software should not write ones to reserved bits. The value 0x0
read from a reserved bit is not defined.

14:8

NON-BACK-TO-BACK
INTER-PACKET-GAP PART1

This is a programmable field representing the optional carrierSense
0x0
window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier isdetected during the timing of IPGR1, the MAC defers to carrier. If,
however, carrier becomes active after IPGR1, the MAC continues timing
IPGR2 and transmits, knowingly causing a collision, thus ensuring fair
access to medium. Its range of values is 0x0 to IPGR2. The recommended
value is 0xC (12d)

31:15 -

Reserved. User software should not write ones to reserved bits. The value 0x0
read from a reserved bit is not defined.

10.5 Collision Window / Retry Register (CLRT - 0xFFE0 0010)
The Collision window / Retry register (CLRT) has an address of 0xFFE0 0010. Its bit
definition is shown in Table 11–140.
Table 140. Collision Window / Retry register (CLRT - address 0xFFE0 0010) bit description
Bit

SymbolFunction

Reset
value

3:0

RETRANSMISSIONMAXIMUM

This is a programmable field specifying the number of retransmission attempts
following a collision before aborting the packet due to excessive collisions. The
Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5.

0xF

7:4

-

Reserved. User software should not write ones to reserved bits. The value read from 0x0
a reserved bit is not defined.

13:8

COLLISION
WINDOW

This is a programmable field representing the slot time or collision window during
which collisions occur in properly configured networks. The default value of 0x37(55d) represents a 56 byte window following the preamble and SFD.

31:14

-

Reserved, user software should not write ones to reserved bits. The value read from NA
a reserved bit is not defined.

0x37

10.6 Maximum Frame Register (MAXF - 0xFFE0 0014)
The Maximum Frame register (MAXF) has an address of 0xFFE0 0014. Its bit definition isshown in Table 11–141.
Table 141. Maximum Frame register (MAXF - address 0xFFE0 0014) bit description
Bit

SymbolFunction

Reset
value

15:0

MAXIMUM FRAME This field resets to the value 0x0600, which represents a maximum receive frame of 0x0600
LENGTH
1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged
frame adds four octets for a total of 1522 octets. If a shorter maximum length
restriction is desired, program this 16 bit field.

31:16

-

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10.7 PHY Support Register (SUPP - 0xFFE0 0018)
The PHY Support register (SUPP) has an address of 0xFFE0 0018. The SUPP register
provides additional control over the RMII interface. The bit definition of this register isshown in Table 11–142.
Table 142. PHY Support register (SUPP - address 0xFFE0 0018) bit description
Bit

SymbolFunction

Reset
value

7:0

-

Unused

0x0

8

SPEED

This bit configures the Reduced MII logic for the current operating speed. When set, 0
100 Mbps mode is selected. When cleared, 10 Mbps mode is selected.

31:9

-

Unused0x0

Unused bits in the PHY support register should be left as zeroes.

10.8 Test Register (TEST - 0xFFE0 001C)
The Test register (TEST) has an address of 0xFFE0 001C. The bit definition of thisregister is shown in Table 11–143. These bits are used for testing purposes only.
Table 143. Test register (TEST - address 0xFFE0 ) bit description
Bit

SymbolFunction

Reset
value

0

SHORTCUT PAUSEQUANTAThis bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time.

0

1

TEST PAUSE

This bit causes the MAC Control sublayer to inhibit transmissions, just as if a
0
PAUSE Receive Control frame with a nonzero pause time parameter was received.

2

TEST
BACKPRESSURE

Setting this bit will cause the MAC to assert backpressure on the link. Backpressure 0
causes preamble to be transmitted, raising carrier sense. A transmit packet from thesystem will be sent during backpressure.

31:3

-

Unused

0x0

10.9 MII Mgmt Configuration Register (MCFG - 0xFFE0 0020)
The MII Mgmt Configuration register (MCFG) has an address of 0xFFE0 0020. The bit
definition of this register is shown in Table 11–144.
Table 144. MII Mgmt Configuration register (MCFG - address 0xFFE0 0020) bit description
Bit

SymbolFunction

Reset
value

0

SCAN INCREMENT

Set this bit to cause the MII Management hardware to perform read cycles across a 0
range of PHYs. When set, the MII Management hardware will perform read cycles
from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow
continuous reads of the same PHY.

1

SUPPRESSPREAMBLE

Set this bit to cause the MII Management hardware to perform read/write cycles
without the 32 bit preamble field. Clear this bit to cause normal cycles to be
performed. Some PHYs support suppressed preamble.

0

4:2

CLOCK SELECTThis field is used by the clock divide logic in creating the MII Management Clock(MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs
support clock rates up to 12.5 MHz, however. Refer to Table 11–145 below for thedefinition of values for this field.

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Table 144. MII Mgmt Configuration register (MCFG - address 0xFFE0 0020) bit description
Bit

SymbolFunction

Reset
value

14:5

-

Unused0x0

15

RESET MII MGMTThis bit resets the MII Management hardware.

0

31:16

-

Unused0x0

Table 145. Clock select encoding
Clock Select

Bit 4

Bit 3

Bit 2

Host Clock divided by 4

0

0

x

Host Clock divided by 6

0

1

0

Host Clock divided by 8

0

1

1

Host Clock divided by 10

1

0

0

Host Clock divided by 14

1

0

1

Host Clock divided by 20

1

1

0

Host Clock divided by 28

1

1

1

10.10 MII Mgmt Command Register (MCMD - 0xFFE0 0024)
The MII Mgmt Command register (MCMD) has an address of 0xFFE0 0024. The bit
definition of this register is shown in Table 11–146.
Table 146. MII Mgmt Command register (MCMD - address 0xFFE0 0024) bit description
Bit

Symbol Function

Reset
value

0

READ

This bit causes the MII Management hardware to perform a single Read cycle. The Read data is 0
returned in Register MRDD (MII Mgmt Read Data).

1

SCAN

This bit causes the MII Management hardware to perform Read cycles continuously. This isuseful for monitoring Link Fail for example.

0

31:2

-

Unused

0x0

10.11 MII Mgmt Address Register (MADR - 0xFFE0 0028)
The MII Mgmt Address register (MADR) has an address of 0xFFE0 0028. The bit
definition of this register is shown in Table 11–147.
Table 147. MII Mgmt Address register (MADR - address 0xFFE0 0028) bit description
Bit

SymbolFunction

Reset
value

4:0

REGISTERADDRESS

This field represents the 5 bit Register Address field of Mgmt
cycles. Up to 32 registers can be accessed.

0x0

7:5

-

Unused0x0

12:8

PHY ADDRESSThis field represents the 5 bit PHY Address field of Mgmt
cycles. Up to 31 PHYs can be addressed (0 is reserved).

0x0

31:13

-

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10.12 MII Mgmt Write Data Register (MWTD - 0xFFE0 002C)
The MII Mgmt Write Data register (MWTD) is a Write Only register with an address of
0xFFE0 002C. The bit definition of this register is shown in Table 11–148.
Table 148. MII Mgmt Write Data register (MWTD - address 0xFFE0 002C) bit description
Bit

SymbolFunction

Reset
value

15:0

WRITE
DATA

When written, an MII Mgmt write cycle is performed using the 16 bit
data and the pre-configured PHY and Register addresses from the
MII Mgmt Address register (MADR).

0x0

31:16

-

Unused

0x0

10.13 MII Mgmt Read Data Register (MRDD - 0xFFE0 0030)
The MII Mgmt Read Data register (MRDD) is a Read Only register with an address of
0xFFE0 0030. The bit definition of this register is shown in Table 11–149.
Table 149. MII Mgmt Read Data register (MRDD - address 0xFFE0 0030) bit description
Bit

SymbolFunction

Reset
value

15:0

READ
DATA

Following an MII Mgmt Read Cycle, the 16 bit data can be read fromthis location.

0x0

31:16

-

Unused

0x0

10.14 MII Mgmt Indicators Register (MIND - 0xFFE0 0034)
The MII Mgmt Indicators register (MIND) is a Read Only register with an address of
0xFFE0 0034. The bit definition of this register is shown in Table 11–150.
Table 150. MII Mgmt Indicators register (MIND - address 0xFFE0 0034) bit description
Bit

SymbolFunction

Reset
value

0

BUSY

When ’1’ is returned - indicates MII Mgmt is currently performing an 0
MII Mgmt Read or Write cycle.

1

SCANNING When ’1’ is returned - indicates a scan operation (continuous MII
Mgmt Read cycles) is in progress.

02

NOT VALID

When ’1’ is returned - indicates MII Mgmt Read cycle has notcompleted and the Read Data is not yet valid.

03

MII Link Fail When ’1’ is returned - indicates that an MII Mgmt link fail has
occurred.

0

31:4

-

0x0

UnusedHere are two examples to access PHY via the MII Management Controller.
For PHY Write if scan is not used:
1. Write 0 to MCMD
2. Write PHY address and register address to MADR
3. Write data to MWTD
4. Wait for busy bit to be cleared in MIND

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For PHY Read if scan is not used:
1. Write 1 to MCMD
2. Write PHY address and register address to MADR
3. Wait for busy bit to be cleared in MIND
4. Write 0 to MCMD
5. Read data from MRDD

10.15 Station Address 0 Register (SA0 - 0xFFE0 0040)
The Station Address 0 register (SA0) has an address of 0xFFE0 0040. The bit definition ofthis register is shown in Table 11–151.
Table 151. Station Address register (SA0 - address 0xFFE0 0040) bit description
Bit

SymbolFunction

Reset
value

7:0

STATION ADDRESS, This field holds the second octet of the station address.
2nd octet

0x0

15:8

STATION ADDRESS, This field holds the first octet of the station address.
1st octet

0x0

31:16

-

0x0

UnusedThe station address is used for perfect address filtering and for sending pause control
frames. For the ordering of the octets in the packet please refer to Figure 11–20.

10.16 Station Address 1 Register (SA1 - 0xFFE0 0044)
The Station Address 1 register (SA1) has an address of 0xFFE0 0044. The bit definition ofthis register is shown in Table 11–152.
Table 152. Station Address register (SA1 - address 0xFFE0 0044) bit description
Bit

SymbolFunction

7:0

STATION ADDRESS, This field holds the fourth octet of the station address.
4th octet

0x0

15:8

STATION ADDRESS, This field holds the third octet of the station address.
3rd octet

0x0

31:16

-

0x0

Unused

Reset
value

The station address is used for perfect address filtering and for sending pause control
frames. For the ordering of the octets in the packet please refer to Figure 11–20.

10.17 Station Address 2 Register (SA2 - 0xFFE0 0048)
The Station Address 2 register (SA2) has an address of 0xFFE0 0048. The bit definition ofthis register is shown in Table 11–153.

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Table 153. Station Address register (SA2 - address 0xFFE0 0048) bit description
Bit

SymbolFunction

Reset
value

7:0

STATION ADDRESS, This field holds the sixth octet of the station address.
6th octet

0x0

15:8

STATION ADDRESS, This field holds the fifth octet of the station address.
5th octet

0x0

31:16

-

0x0

UnusedThe station address is used for perfect address filtering and for sending pause control
frames. For the ordering of the octets in the packet please refer to Figure 11–20.

11. Control register definitions
11.1 Command Register (Command - 0xFFE0 0100)
The Command register (Command) register has an address of 0xFFE0 0100. Its bit
definition is shown in Table 11–154.
Table 154. Command register (Command - address 0xFFE0 0100) bit description
Bit

SymbolFunction

Reset
value

0

RxEnable

Enable receive.

0

1

TxEnable

Enable transmit.

0

2

-

Unused0x0

3RegReset

When a ’1’ is written, all datapaths and the host registers arereset. The MAC needs to be reset separately.

04

TxResetWhen a ’1’ is written, the transmit datapath is reset.

05

RxResetWhen a ’1’ is written, the receive datapath is reset.

0

6

PassRuntFrame

When set to ’1’, passes runt frames smaller than 64 bytes tomemory unless they have a CRC error. If ’0’ runt frames arefiltered out.

0

7

PassRxFilter

When set to ’1’, disables receive filtering i.e. all frames
received are written to memory.

0

8

TxFlowControl

Enable IEEE 802.3 / clause 31 flow control sending pause
frames in full duplex and continuous preamble in half duplex.

0

9

RMII

When set to ’1’, RMII mode is selected; if ’0’, MII mode isselected.

010

FullDuplex

When set to ’1’, indicates full duplex operation.

0

31:11

-

Unused0x0

All bits can be written and read. The Tx/RxReset bits are write only, reading will return a 0.

11.2 Status Register (Status - 0xFFE0 0104)
The Status register (Status) is a Read Only register with an address of 0xFFE0 0104. Its
bit definition is shown in Table 11–155.

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Table 155. Status register (Status - address 0xFFE0 0104) bit description
Bit

SymbolFunction

Reset
value

0

RxStatus If 1, the receive channel is active. If 0, the receive channel is inactive.

1

TxStatus If 1, the transmit channel is active. If 0, the transmit channel is inactive. 0

31:2

-

0

Unused0x0

The values represent the status of the two channels/datapaths. When the status is 1, thechannel is active, meaning:• It is enabled and the Rx/TxEnable bit is set in the Command register or it just got
disabled while still transmitting or receiving a frame.

• Also, for the transmit channel, the transmit queue is not empty
i.e. ProduceIndex != ConsumeIndex.

• Also, for the receive channel, the receive queue is not fulli.e. ProduceIndex != ConsumeIndex - 1.
The status transitions from active to inactive if the channel is disabled by a software resetof the Rx/TxEnable bit in the Command register and the channel has committed the status
and data of the current frame to memory. The status also transitions to inactive if thetransmit queue is empty or if the receive queue is full and status and data have beencommitted to memory.

11.3 Receive Descriptor Base Address Register (RxDescriptor 0xFFE0 0108)
The Receive Descriptor base address register (RxDescriptor) has an address of
0xFFE0 0108. Its bit definition is shown in Table 11–156.
Table 156. Receive Descriptor Base Address register (RxDescriptor - address 0xFFE0 0108)
bit description
Bit

SymbolFunction

Reset
value

1:0

-

Fixed to ’00’

-

31:2

RxDescriptor

MSBs of receive descriptor base address.

0x0

The receive descriptor base address is a byte address aligned to a word boundary i.e.
LSB 1:0 are fixed to ’00’. The register contains the lowest address in the array ofdescriptors.

11.4 Receive Status Base Address Register (RxStatus - 0xFFE0 010C)
The receive descriptor base address is a byte address aligned to a word boundary i.e.
LSB 1:0 are fixed to ’00’. The register contains the lowest address in the array ofdescriptors.
Table 157. receive Status Base Address register (RxStatus - address 0xFFE0 010C) bit
description
Bit

SymbolFunction

Reset
value

2:0

-

Fixed to ’000’

-

31:3

RxStatus

MSBs of receive status base address.

0x0

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The receive status base address is a byte address aligned to a double word boundary i.e.
LSB 2:0 are fixed to ’000’.

11.5 Receive Number of Descriptors Register (RxDescriptor 0xFFE0 0110)
The Receive Number of Descriptors register (RxDescriptorNumber) has an address of
0xFFE0 0110. Its bit definition is shown in Table 11–158.
Table 158. Receive Number of Descriptors register (RxDescriptor - address 0xFFE0 0110) bit
description
Bit

SymbolFunction

Reset
value

15:0

RxDescriptorNumber

Number of descriptors in the descriptor array for which
RxDescriptor is the base address. The number ofdescriptors is minus one encoded.

0x0

31:16

-

Unused0x0

The receive number of descriptors register defines the number of descriptors in thedescriptor array for which RxDescriptor is the base address. The number of descriptors
should match the number of statuses. The register uses minus one encoding i.e. if thearray has 8 elements, the value in the register should be 7.

11.6 Receive Produce Index Register (RxProduceIndex - 0xFFE0 0114)
The Receive Produce Index register (RxProduceIndex) is a Read Only register with anaddress of 0xFFE0 0114. Its bit definition is shown in Table 11–159.
Table 159. Receive Produce Index register (RxProduceIndex - address 0xFFE0 0114) bit
description
Bit

SymbolFunction

Reset
value

15:0

RxProduceIndex Index of the descriptor that is going to be filled next by thereceive datapath.

0x0

31:16

-

0x0

UnusedThe receive produce index register defines the descriptor that is going to be filled next by
the hardware receive process. After a frame has been received, hardware increments theindex. The value is wrapped to 0 once the value of RxDescriptorNumber has beenreached. If the RxProduceIndex equals RxConsumeIndex - 1, the array is full and any
further frames being received will cause a buffer overrun error.

11.7 Receive Consume Index Register (RxConsumeIndex - 0xFFE0 0118)
The Receive consume index register (RxConsumeIndex) has an address of
0xFFE0 0118. Its bit definition is shown in Table 11–160.

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Table 160. Receive Consume Index register (RXConsumeIndex - address 0xFFE0 0118) bit
description
Bit

SymbolFunction

Reset
value

15:0

RxConsumeIndex Index of the descriptor that is going to be processed next by
the receive

31:16

-

Unused0x0

The receive consume register defines the descriptor that is going to be processed next by
the software receive driver. The receive array is empty as long as RxProduceIndex equals
RxConsumeIndex. As soon as the array is not empty, software can process the frame
pointed to by RxConsumeIndex. After a frame has been processed by software, software
should increment the RxConsumeIndex. The value must be wrapped to 0 once the valueof RxDescriptorNumber has been reached. If the RxProduceIndex equals
RxConsumeIndex - 1, the array is full and any further frames being received will cause abuffer overrun error.

11.8 Transmit Descriptor Base Address Register (TxDescriptor 0xFFE0 011C)
The Transmit Descriptor base address register (TxDescriptor) has an address of
0xFFE0 011C. Its bit definition is shown in Table 11–161.
Table 161. Transmit Descriptor Base Address register (TxDescriptor - address 0xFFE0 011C)
bit description
Bit

SymbolFunction

Reset
value

1:0

-

Fixed to ’00’

-

31:2

TxDescriptor

MSBs of transmit descriptor base address.

0x0

The transmit descriptor base address is a byte address aligned to a word boundary i.e.
LSB 1:0 are fixed to ’00’. The register contains the lowest address in the array ofdescriptors.

11.9 Transmit Status Base Address Register (TxStatus - 0xFFE0 0120)
The Transmit Status base address register (TxStatus) has an address of 0xFFE0 0120. Its
bit definition is shown in Table 11–162.
Table 162. Transmit Status Base Address register (TxStatus - address 0xFFE0 0120) bit
description
Bit

SymbolFunction

Reset
value

1:0

-

Fixed to ’00’

-

31:2

TxStatus

MSBs of transmit status base address.

0x0

The transmit status base address is a byte address aligned to a word boundary i.e. LSB
1:0 are fixed to ’00’. The register contains the lowest address in the array of statuses.

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11.10 Transmit Number of Descriptors Register (TxDescriptorNumber 0xFFE0 0124)
The Transmit Number of Descriptors register (TxDescriptorNumber) has an address of
0xFFE0 0124. Its bit definition is shown in Table 11–163.
Table 163. Transmit Number of Descriptors register (TxDescriptorNumber - address
0xFFE0 0124) bit description
Bit

SymbolFunction

Reset
value

15:0

TxDescriptorNumber

Number of descriptors in the descriptor array for which
TxDescriptor is the base address. The register is minus
one encoded.

31:16

-

Unused0x0

The transmit number of descriptors register defines the number of descriptors in thedescriptor array for which TxDescriptor is the base address. The number of descriptors
should match the number of statuses. The register uses minus one encoding i.e. if thearray has 8 elements, the value in the register should be 7.

11.11 Transmit Produce Index Register (TxProduceIndex - 0xFFE0 0128)
The Transmit Produce Index register (TxProduceIndex) has an address of 0xFFE0 0128.
Its bit definition is shown in Table 11–164.
Table 164. Transmit Produce Index register (TxProduceIndex - address 0xFFE0 0128) bit
description
Bit

SymbolFunction

15:0

TxProduceIndex Index of the descriptor that is going to be filled next by thetransmit software driver.

0x0

31:16

-

0x0

Unused

Reset
value

The transmit produce index register defines the descriptor that is going to be filled next by
the software transmit driver. The transmit descriptor array is empty as long as
TxProduceIndex equals TxConsumeIndex. If the transmit hardware is enabled, it will starttransmitting frames as soon as the descriptor array is not empty. After a frame has beenprocessed by software, it should increment the TxProduceIndex. The value must be
wrapped to 0 once the value of TxDescriptorNumber has been reached. If the
TxProduceIndex equals TxConsumeIndex - 1 the descriptor array is full and software
should stop producing new descriptors until hardware has transmitted some frames andupdated the TxConsumeIndex.

11.12 Transmit Consume Index Register (TxConsumeIndex - 0xFFE0 012C)
The Transmit Consume Index register (TxConsumeIndex) is a Read Only register with anaddress of 0xFFE0 012C. Its bit definition is shown in Table 11–165.

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Table 165. Transmit Consume Index register (TxConsumeIndex - address 0xFFE0 012C) bit
description
Bit

SymbolFunction

Reset
value

15:0

TxConsumeIndex Index of the descriptor that is going to be transmitted next by
the transmit datapath.

0x0

31:16

-

0x0

UnusedThe transmit consume index register defines the descriptor that is going to be transmitted
next by the hardware transmit process. After a frame has been transmitted hardware
increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has
been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is
empty and the transmit channel will stop transmitting until software produces new
descriptors.

11.13 Transmit Status Vector 0 Register (TSV0 - 0xFFE0 0158)
The Transmit Status Vector 0 register (TSV0) is a Read Only register with an address of
0xFFE0 0158. The transmit status vector registers store the most recent transmit status
returned by the MAC. Since the status vector consists of more than 4 bytes, status isdistributed over two registers TSV0 and TSV1. These registers are provided for debug
purposes, because the communication between driver software and the Ethernet block
takes place primarily through the frame descriptors. The status register contents are valid
as long as the internal status of the MAC is valid and should typically only be read when
the transmit and receive processes are halted.
Table 11–166 lists the bit definitions of the TSV0 register.
Table 166. Transmit Status Vector 0 register (TSV0 - address 0xFFE0 0158) bit description
Bit

SymbolFunction

Reset
value

0

CRC error

The attached CRC in the packet did not match theinternally generated CRC.

0

1

Length check error

Indicates the frame length field does not match the actual
number of data items and is not a type field.

02

Length out of range[1] Indicates that frame type/length field was larger than
1500 bytes.

0

3

Done

Transmission of packet was completed.

04Multicast

Packet’s destination was a multicast address.

05

Broadcast

Packet’s destination was a broadcast address.

06

Packet Defer

Packet was deferred for at least one attempt, but less than 0
an excessive defer.

7

Excessive Defer

Packet was deferred in excess of 6071 nibble times in
100 Mbps or 24287 bit times in 10 Mbps mode.

8

Excessive Collision

Packet was aborted due to exceeding of maximum allowed 0
number of collisions.

9

Late Collision

Collision occurred beyond collision window, 512 bit times.

0

10

Giant

Byte count in frame was greater than can be represented
in the transmit byte count field in TSV1.

0

11

Underrun

Host side caused buffer underrun.

0

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Table 166. Transmit Status Vector 0 register (TSV0 - address 0xFFE0 0158) bit description
Bit

SymbolFunction

Reset
value

27:12

Total bytes

The total number of bytes transferred including collided
attempts.

0x0

28

Control frame

The frame was a control frame.

0

29

Pause

The frame was a control frame with a valid PAUSE
opcode.

030

Backpressure

Carrier-sense method backpressure was previously
applied.

0

31

VLAN

Frame’s length/type field contained 0x8100 which is the
VLAN protocol identifier.

0[1]

The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or
ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length
out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding thestatus of the received frame.

11.14 Transmit Status Vector 1 Register (TSV1 - 0xFFE0 015C)
The Transmit Status Vector 1 register (TSV1) is a Read Only register with an address of
0xFFE0 015C. The transmit status vector registers store the most recent transmit status
returned by the MAC. Since the status vector consists of more than 4 bytes, status isdistributed over two registers TSV0 and TSV1. These registers are provided for debug
purposes, because the communication between driver software and the Ethernet block
takes place primarily through the frame descriptors. The status register contents are valid
as long as the internal status of the MAC is valid and should typically only be read when
the transmit and receive processes are halted.Table 11–167 lists the bit definitions of theTSV1 register.
Table 167. Transmit Status Vector 1 register (TSV1 - address 0xFFE0 015C) bit description
Bit

SymbolFunction

Reset
value

15:0

Transmit byte count

The total number of bytes in the frame, not counting thecollided bytes.

0x0

19:16

Transmit collision
count

Number of collisions the current packet incurred during0x0transmission attempts. The maximum number of collisions(16) cannot be represented.

31:20

-

Unused

0x0

11.15 Receive Status Vector Register (RSV - 0xFFE0 0160)
The Receive status vector register (RSV) is a Read Only register with an address of
0xFFE0 0160. The receive status vector register stores the most recent receive status
returned by the MAC. This register is provided for debug purposes, because thecommunication between driver software and the Ethernet block takes place primarily
through the frame descriptors. The status register contents are valid as long as theinternal status of the MAC is valid and should typically only be read when the transmit andreceive processes are halted.
Table 11–168 lists the bit definitions of the RSV register.

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Table 168. Receive Status Vector register (RSV - address 0xFFE0 0160) bit description
Bit

SymbolFunction

Reset
value

15:0

Received byte countIndicates length of received frame.

0x0

16

Packet previously
ignoredIndicates that a packet was dropped.

017

RXDV event
previously seen

Indicates that the last receive event seen was not longenough to be a valid packet.

018

Carrier event
previously seen

Indicates that at some time since the last receive statistics, 0
a carrier event was detected.

19

Receive code
violation

Indicates that MII data does not represent a valid receive
code.

0

20

CRC error

The attached CRC in the packet did not match theinternally generated CRC.

0

21

Length check error

Indicates the frame length field does not match the actual
number of data items and is not a type field.

0

22

Length out of range[1] Indicates that frame type/length field was larger than
1518 bytes.

023

Receive OK

The packet had valid CRC and no symbol errors.

024Multicast

The packet destination was a multicast address.

025

Broadcast

The packet destination was a broadcast address.

026

Dribble Nibble

Indicates that after the end of packet another 1-7 bits were 0
received. A single nibble, called dribble nibble, is formed
but not sent out.

27

Control frame

The frame was a control frame.

0

28

PAUSE

The frame was a control frame with a valid PAUSE
opcode.

029

Unsupported Opcode The current frame was recognized as a Control Frame but 0
contains an unknown opcode.

30

VLAN

Frame’s length/type field contained 0x8100 which is the
VLAN protocol identifier.

0

31

-

Unused0x0[1]

The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or
ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length
out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding thestatus of the received frame.

11.16 Flow Control Counter Register (FlowControlCounter - 0xFFE0 0170)
The Flow Control Counter register (FlowControlCounter) has an address of 0xFFE0 0170.
Table 11–169 lists the bit definitions of the register.

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Table 169. Flow Control Counter register (FlowControlCounter - address 0xFFE0 0170) bit
description
Bit

SymbolFunction

Reset
value

15:0

MirrorCounter

In full duplex mode the MirrorCounter specifies the number 0x0
of cycles before re-issuing the Pause control frame.

31:16

PauseTimer

In full-duplex mode the PauseTimer specifies the valuethat is inserted into the pause timer field of a pause flow
control frame. In half duplex mode the PauseTimer
specifies the number of backpressure cycles.

0x0

11.17 Flow Control Status Register (FlowControlStatus - 0xFFE0 0174)
The Flow Control Status register (FlowControlStatus) is a Read Only register with anaddress of 0xFFE0 8174. Table 11–170 lists the bit definitions of the register.
Table 170. Flow Control Status register (FlowControlStatus - address 0xFFE0 8174) bit
description
Bit

SymbolFunction

Reset
value

15:0

MirrorCounterCurrent In full duplex mode this register represents the current
0x0
value of the datapath’s mirror counter which counts up to
the value specified by the MirrorCounter field in the
FlowControlCounter register. In half duplex mode theregister counts until it reaches the value of the PauseTimerbits in the FlowControlCounter register.

31:16

-

Unused0x0

12. Receive filter register definitions
12.1 Receive Filter Control Register (RxFilterCtrl - 0xFFE0 0200)
The Receive Filter Control register (RxFilterCtrl) has an address of 0xFFE0 0200.
Table 11–171 lists the definition of the individual bits in the register.
Table 171. Receive Filter Control register (RxFilterCtrl - address 0xFFE0 0200) bit
description
Bit

SymbolFunction

Reset
value

0

AcceptUnicastEn

When set to ’1’, all unicast frames are accepted.

01

AcceptBroadcastEn

When set to ’1’, all broadcast frames are accepted.

02

AcceptMulticastEn

When set to ’1’, all multicast frames are accepted.

03

AcceptUnicastHashEn

When set to ’1’, unicast frames that pass the imperfect 0
hash filter are accepted.

4

AcceptMulticastHashEn

When set to ’1’, multicast frames that pass theimperfect hash filter are accepted.

05

AcceptPerfectEn

When set to ’1’, the frames with a destination address
identical to the0station address are accepted.

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Table 171. Receive Filter Control register (RxFilterCtrl - address 0xFFE0 0200) bit
description
Bit

SymbolFunction

11:6-

Reserved, user software should not write ones toNAreserved bits. The value read from a reserved bit is notdefined.

12

MagicPacketEnWoL

When set to ’1’, the result of the magic packet filter will 0
generate a WoL interrupt when there is a match.

13

RxFilterEnWoL

When set to ’1’, the result of the perfect address
matching filter and the imperfect hash filter will
generate a WoL interrupt when there is a match.

0

Unused0x0

31:14 -

Reset
value

12.2 Receive Filter WoL Status Register (RxFilterWoLStatus 0xFFE0 0204)
The Receive Filter Wake-up on LAN Status register (RxFilterWoLStatus) is a Read Only
register with an address of 0xFFE0 0204.
Table 11–172 lists the definition of the individual bits in the register.
Table 172. Receive Filter WoL Status register (RxFilterWoLStatus - address 0xFFE0 0204) bit
description
Bit

SymbolFunction

Reset
value

0

AcceptUnicastWoLWhen the value is ’1’, a unicast frames caused WoL.

0

1

AcceptBroadcastWoLWhen the value is ’1’, a broadcast frame caused WoL.

02

AcceptMulticastWoLWhen the value is ’1’, a multicast frame caused WoL.

03

AcceptUnicastHashWoL

When the value is ’1’, a unicast frame that passes theimperfect hash filter caused WoL.

0

4

AcceptMulticastHashWoL When the value is ’1’, a multicast frame that passes theimperfect hash filter caused WoL.

5

AcceptPerfectWoL

6-

Unused0x0

7

RxFilterWoL

When the value is ’1’, the receive filter caused WoL.

0

8

MagicPacketWoL

When the value is ’1’, the magic packet filter caused
WoL.

0

Unused0x0

31:9 -

0

When the value is ’1’, the perfect address matching filter 0caused WoL.

The bits in this register record the cause for a WoL. Bits in RxFilterWoLStatus can becleared by writing the RxFilterWoLClear register.

12.3 Receive Filter WoL Clear Register (RxFilterWoLClear - 0xFFE0 0208)
The Receive Filter Wake-up on LAN Clear register (RxFilterWoLClear) is a Write Only
register with an address of 0xFFE0 0208.
Table 11–173 lists the definition of the individual bits in the register.

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Table 173. Receive Filter WoL Clear register (RxFilterWoLClear - address 0xFFE0 0208) bit
description
Bit

SymbolFunction

Reset
value

0

AcceptUnicastWoLClr

01

AcceptBroadcastWoLClr

When a ’1’ is written to one of these bits (0 to 5), thecorresponding status bit in the RxFilterWoLStatus
register is cleared.

0

2

AcceptMulticastWoLClr

3

AcceptUnicastHashWoLClr

04

AcceptMulticastHashWoLClr

05

AcceptPerfectWoLClr

0

6

-

Unused7

RxFilterWoLClr

8

MagicPacketWoLClr

When a ’1’ is written to one of these bits (7 and/or 8), 0
the corresponding status bit in the RxFilterWoLStatus 0
register is cleared.

31:9 -

0

0x0

Unused0x0

The bits in this register are write-only; writing resets the corresponding bits in the
RxFilterWoLStatus register.

12.4 Hash Filter Table LSBs Register (HashFilterL - 0xFFE0 0210)
The Hash Filter table LSBs register (HashFilterL) has an address of 0xFFE0 0210.
Table 11–174 lists the bit definitions of the register. Details of Hash filter table use can befound in Section 11–16.10 “Receive filtering” on page 194.
Table 174. Hash Filter Table LSBs register (HashFilterL - address 0xFFE0 0210) bit
description
Bit

SymbolFunction

Reset
value

31:0

HashFilterL

Bit 31:0 of the imperfect filter hash table for receive
filtering.

0x0

12.5 Hash Filter Table MSBs Register (HashFilterH - 0xFFE0 0214)
The Hash Filter table MSBs register (HashFilterH) has an address of 0xFFE0 0214.
Table 11–175 lists the bit definitions of the register. Details of Hash filter table use can befound in Section 11–16.10 “Receive filtering” on page 194.
Table 175. Hash Filter MSBs register (HashFilterH - address 0xFFE0 0214) bit description
Bit

SymbolFunction

Reset
value

31:0

HashFilterH

Bit 63:32 of the imperfect filter hash table for receive
filtering.

0x0

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13. Module control register definitions
13.1 Interrupt Status Register (IntStatus - 0xFFE0 0FE0)
The Interrupt Status register (IntStatus) is a Read Only register with an address of
0xFFE0 0FE0. The interrupt status register bit definition is shown in Table 11–176. Notethat all bits are flip-flops with an asynchronous set in order to be able to generateinterrupts if there are wake-up events while clocks are disabled.
Table 176. Interrupt Status register (IntStatus - address 0xFFE0 0FE0) bit description
Bit

SymbolFunction

Reset
value

0

RxOverrunInt

Interrupt set on a fatal overrun error in the receive queue. The
0fatal interrupt should be resolved by a Rx soft-reset. The bit is not
set when there is a nonfatal overrun error.

1

RxErrorInt

Interrupt trigger on receive errors: AlignmentError, RangeError,
0
LengthError, SymbolError, CRCError or NoDescriptor or Overrun.

2

RxFinishedInt

Interrupt triggered when all receive descriptors have beenprocessed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.

3

RxDoneInt

Interrupt triggered when a receive descriptor has been processed 0
while the Interrupt bit in the Control field of the descriptor was set.

4

TxUnderrunInt Interrupt set on a fatal underrun error in the transmit queue. The 0
fatal interrupt should be resolved by a Tx soft-reset. The bit is not
set when there is a nonfatal underrun error.

5

TxErrorInt

Interrupt trigger on transmit errors: LateCollision,
ExcessiveCollision and ExcessiveDefer, NoDescriptor or
Underrun.

0

6

TxFinishedInt

Interrupt triggered when all transmit descriptors have beenprocessed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.

0

7

TxDoneInt

Interrupt triggered when a descriptor has been transmitted while
the Interrupt bit in the Control field of the descriptor was set.

0

11:8

-

Unused0x0

12SoftInt

Interrupt triggered by software writing a 1 to the SoftintSet bit in
the IntSet register.

0

13

WakeupInt

Interrupt triggered by a Wakeup event detected by the receive
filter.

0

31:14

-

Unused0x0

0

The interrupt status register is read-only. Setting can be done via the IntSet register. Resetcan be accomplished via the IntClear register.

13.2 Interrupt Enable Register (IntEnable - 0xFFE0 0FE4)
The Interrupt Enable register (IntEnable) has an address of 0xFFE0 0FE4. The interrupt
enable register bit definition is shown in Table 11–177.

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Table 177. Interrupt Enable register (intEnable - address 0xFFE0 0FE4) bit description
Bit

SymbolFunction

Reset
value

0

RxOverrunIntEn

Enable for interrupt trigger on receive buffer overrun or
descriptor underrun situations.

01

RxErrorIntEn

Enable for interrupt trigger on receive errors.

0

2

RxFinishedIntEn

Enable for interrupt triggered when all receive descriptors have 0
been processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.

3

RxDoneIntEn

Enable for interrupt triggered when a receive descriptor has
0been processed while the Interrupt bit in the Control field of thedescriptor was set.

4

TxUnderrunIntEn Enable for interrupt trigger on transmit buffer or descriptor
underrun situations.

05

TxErrorIntEn

Enable for interrupt trigger on transmit errors.

0

6

TxFinishedIntEn

Enable for interrupt triggered when all transmit descriptors
have been processed i.e. on the transition to the situation
where ProduceIndex == ConsumeIndex.

0

7

TxDoneIntEn

Enable for interrupt triggered when a descriptor has beentransmitted while the Interrupt bit in the Control field of thedescriptor was set.

0

11:8

-

Unused0x0

12SoftIntEn

Enable for interrupt triggered by the SoftInt bit in the IntStatus
register, caused by software writing a 1 to the SoftIntSet bit in
the IntSet register.

0

13

WakeupIntEn

Enable for interrupt triggered by a Wakeup event detected by
the receive filter.

0

31:14

-

Unused0x0

13.3 Interrupt Clear Register (IntClear - 0xFFE0 0FE8)
The Interrupt Clear register (IntClear) is a Write Only register with an address of
0xFFE0 0FE8. The interrupt clear register bit definition is shown in Table 11–178.
Table 178. Interrupt Clear register (IntClear - address 0xFFE0 0FE8) bit description
Bit

SymbolFunction

Reset
value

0

RxOverrunIntClr

Writing a ’1’ to one of these bits clears (0 to 7) the
corresponding status bit in interrupt status register
IntStatus.

01

RxErrorIntClr

2

RxFinishedIntClr

3

RxDoneIntClr

0

4

TxUnderrunIntClr

05

TxErrorIntClr

0

6

TxFinishedIntClr

0

7

TxDoneIntClr

0

11:8

-

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Table 178. Interrupt Clear register (IntClear - address 0xFFE0 0FE8) bit description
Bit

SymbolFunction

Reset
value

12

SoftIntClr

013

WakeupIntClr

Writing a ’1’ to one of these bits (12 and/or 13) clears thecorresponding status bit in interrupt status register
IntStatus.

0

31:14

-

Unused0x0

The interrupt clear register is write-only. Writing a 1 to a bit of the IntClear register clears
the corresponding bit in the status register. Writing a 0 will not affect the interrupt status.

13.4 Interrupt Set Register (IntSet - 0xFFE0 0FEC)
The Interrupt Set register (IntSet) is a Write Only register with an address of
0xFFE0 0FEC. The interrupt set register bit definition is shown in Table 11–179.
Table 179. Interrupt Set register (IntSet - address 0xFFE0 0FEC) bit description
Bit

SymbolFunction

Reset
value

0

RxOverrunIntSet

0

1

RxErrorIntSet

2

RxFinishedIntSet

Writing a ’1’ to one of these bits (0 to 7) sets thecorresponding status bit in interrupt status register
IntStatus.

3

RxDoneIntSet

0

4

TxUnderrunIntSet

0

5

TxErrorIntSet

0

6

TxFinishedIntSet

0

7

TxDoneIntSet

0

11:8

-

Unused0x0

12SoftIntSet

13

WakeupIntSet

Writing a ’1’ to one of these bits (12 and/or 13) sets thecorresponding status bit in interrupt status register
IntStatus.

0

31:14

-

Unused

0x0

0
0

0

The interrupt set register is write-only. Writing a 1 to a bit of the IntSet register sets thecorresponding bit in the status register. Writing a 0 will not affect the interrupt status.

13.5 Power Down Register (PowerDown - 0xFFE0 0FF4)
The Power-Down register (PowerDown) is used to block all AHB accesses except
accesses to the PowerDown register. The register has an address of 0xFFE0 0FF4. The
bit definition of the register is listed in Table 11–180.
Table 180. Power Down register (PowerDown - address 0xFFE0 0FF4) bit description
Bit

SymbolFunction

Reset
value

30:0

-

Unused0x0

31PowerDownMACAHB

If true, all AHB accesses will return a read/write error,
except accesses to the PowerDown register.

0

Setting the bit will return an error on all read and write accesses on the MACAHB interface
except for accesses to the PowerDown register.
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14. Descriptor and status formats
This section defines the descriptor format for the transmit and receive scatter/gather DMA
engines. Each Ethernet frame can consist of one or more fragments. Each fragment
corresponds to a single descriptor. The DMA managers in the Ethernet block scatter (forreceive) and gather (for transmit) multiple fragments for a single Ethernet frame.

14.1 Receive descriptors and statuses
Figure 11–21 depicts the layout of the receive descriptors in memory.

RxDescriptor

RxStatus

PACKET

1

DATA BUFFERCONTROL
PACKET

2

StatusHashCRC
DATA BUFFERCONTROL
PACKET

3

PACKETDATA BUFFER

PACKETDATA BUFFER

PACKET

StatusInfo
StatusHashCRC

DATA BUFFERCONTROL

RxDescriptorNumber

StatusInfo
StatusHashCRC

CONTROL
5

StatusInfo
StatusHashCRC

CONTROL
4

StatusInfo

StatusInfo
StatusHashCRC

DATA BUFFERCONTROL

StatusInfo
StatusHashCRC

Fig 21. Receive descriptor memory layout

Receive descriptors are stored in an array in memory. The base address of the array isstored in the RxDescriptor register, and should be aligned on a 4 byte address boundary.
The number of descriptors in the array is stored in the RxDescriptorNumber register using
a minus one encoding style e.g. if the array has 8 elements the register value should be 7.
Parallel to the descriptors there is an array of statuses. For each element of the descriptor
array there is an associated status field in the status array. The base address of the statusarray is stored in the RxStatus register, and must be aligned on an 8 byte address
boundary. During operation (when the receive datapath is enabled) the RxDescriptor,
RxStatus and RxDescriptorNumber registers should not be modified.
Two registers, RxConsumeIndex and RxProduceIndex, define the descriptor locations
that will be used next by hardware and software. Both registers act as counters starting at
0 and wrapping when they reach the value of RxDescriptorNumber. The RxProduceIndex
contains the index of the descriptor that is going to be filled with the next frame being
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received. The RxConsumeIndex is programmed by software and is the index of the next
descriptor that the software receive driver is going to process. When RxProduceIndex ==RxConsumeIndex, the receive buffer is empty. When RxProduceIndex ==RxConsumeIndex -1 (taking wraparound into account), the receive buffer is full and newly
received data would generate an overflow unless the software driver frees up one or more
descriptors.
Each receive descriptor takes two word locations (8 bytes) in memory. Likewise eachstatus field takes two words (8 bytes) in memory. Each receive descriptor consists of apointer to the data buffer for storing receive data (Packet) and a control word (Control).
The Packet field has a zero address offset, the control field has a 4 byte address offset
with respect to the descriptor address as defined in Table 11–181.
Table 181. Receive Descriptor Fields
SymbolAddress Bytes Description
offsetPacket0x0

4Base address of the data buffer for storing receive data.

Control

0x4

4Control information, see Table 11–182.

The data buffer pointer (Packet) is a 32 bits byte aligned address value containing thebase address of the data buffer. The definition of the control word bits is listed inTable 11–182.
Table 182. Receive Descriptor Control Word
Bit

SymbolDescription

10:0

Size

Size in bytes of the data buffer. This is the size of the buffer reserved by thedevice driver for a frame or frame fragment i.e. the byte size of the buffer
pointed to by the Packet field. The size is -1 encoded e.g. if the buffer is 8
bytes the size field should be equal to 7.

30:11 -

Unused31

If true generate an RxDone interrupt when the data in this frame or frame
fragment and the associated status information has been committed tomemory.

Interrupt

Table 11–183 lists the fields in the receive status elements from the status array.
Table 183. Receive Status Fields
SymbolAddress Bytes Description
offsetStatusInfo

0x0

4

Receive status return flags, see Table 11–185.

StatusHashCRC 0x4

4

The concatenation of the destination address hash CRC andthe source address hash CRC.

Each receive status consists of two words. The StatusHashCRC word contains aconcatenation of the two 9 bit hash CRCs calculated from the destination and source
addresses contained in the received frame. After detecting the destination and source
addresses, StatusHashCRC is calculated once, then held for every fragment of the same
frame.
The concatenation of the two CRCs is shown in Table 11–184:

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Table 184. Receive Status HashCRC Word
Bit

SymbolDescription

8:0

SAHashCRC Hash CRC calculated from the source address.

15:9

-

Unused

24:16 DAHashCRC Hash CRC calculated from the destination address.
31:25 -

UnusedThe StatusInfo word contains flags returned by the MAC and flags generated by thereceive datapath reflecting the status of the reception. Table 11–185 lists the bit definitionsin the StatusInfo word.
Table 185. Receive status information word
Bit

SymbolDescription

10:0

RxSizeThe size in bytes of the actual data transferred into one fragment buffer. In
other words, this is the size of the frame or fragment as actually written by
the DMA manager for one descriptor. This may be different from the Sizebits of the Control field in the descriptor that indicate the size of the buffer
allocated by the device driver. Size is -1 encoded e.g. if the buffer has
8 bytes the RxSize value will be 7.

17:11 -

Unused18

Indicates this is a control frame for flow control, either a pause frame or aframe with an unsupported opcode.

ControlFrame

19

VLAN

Indicates a VLAN frame.

20

FailFilter

Indicates this frame has failed the Rx filter. These frames will not normally
pass to memory. But due to the limitation of the size of the buffer, part ofthis frame may already be passed to memory. Once the frame is found tohave failed the Rx filter, the remainder of the frame will be discarded
without being passed to the memory. However, if the PassRxFilter bit in
the Command register is set, the whole frame will be passed to memory.

21

Multicast

Set when a multicast frame is received.

22

Broadcast

Set when a broadcast frame is received.

23

CRCError

The received frame had a CRC error.

24

SymbolError

The PHY reports a bit error over the MII during reception.

25

LengthError

The frame length field value in the frame specifies a valid length, but does
not match the actual data length.

26

RangeError[1]The received packet exceeds the maximum packet size.

27

AlignmentError An alignment error is flagged when dribble bits are detected and also a
CRC error is detected. This is in accordance with IEEE std. 802.3/clause
4.3.2.

28

OverrunReceive overrun. The adapter can not accept the data stream.

29

NoDescriptor

No new Rx descriptor is available and the frame is too long for the buffer
size in the current receive descriptor.

30

LastFlag

When set to 1, indicates this descriptor is for the last fragment of a frame.
If the frame consists of a single fragment, this bit is also set to 1.

31

Error

An error occurred during reception of this frame. This is a logical OR of
AlignmentError, RangeError, LengthError, SymbolError, CRCError, andOverrun.

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The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or
ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Range"error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of thereceived frame.

For multi-fragment frames, the value of the AlignmentError, RangeError, LengthError,
SymbolError and CRCError bits in all but the last fragment in the frame will be 0; likewise
the value of the FailFilter, Multicast, Broadcast, VLAN and ControlFrame bits is undefined.
The status of the last fragment in the frame will copy the value for these bits from the
MAC. All fragment statuses will have valid LastFrag, RxSize, Error, Overrun and
NoDescriptor bits.

14.2 Transmit descriptors and statuses
Figure 11–22 depicts the layout of the transmit descriptors in memory.

TxDescriptor

TxStatus

PACKET

1

DATA BUFFER
StatusInfo

CONTROL
PACKET

2

DATA BUFFER
StatusInfo

CONTROL
PACKET

3

DATA BUFFER
StatusInfo

CONTROL
PACKET

4

DATA BUFFER
StatusInfo

CONTROL
PACKET

5

DATA BUFFER
StatusInfo

CONTROL

TxDescriptorNumber

PACKETDATA BUFFER
StatusInfo

CONTROLFig 22. Transmit descriptor memory layout

Transmit descriptors are stored in an array in memory. The lowest address of the transmit
descriptor array is stored in the TxDescriptor register, and must be aligned on a 4 byte
address boundary. The number of descriptors in the array is stored in the
TxDescriptorNumber register using a minus one encoding style i.e. if the array has 8elements the register value should be 7. Parallel to the descriptors there is an array ofstatuses. For each element of the descriptor array there is an associated status field in thestatus array. The base address of the status array is stored in the TxStatus register, andmust be aligned on a 4 byte address boundary. During operation (when the transmit
datapath is enabled) the TxDescriptor, TxStatus, and TxDescriptorNumber registers
should not be modified.
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Two registers, TxConsumeIndex and TxProduceIndex, define the descriptor locations thatwill be used next by hardware and software. Both register act as counters starting at 0 andwrapping when they reach the value of TxDescriptorNumber. The TxProduceIndex
contains the index of the next descriptor that is going to be filled by the software driver.
The TxConsumeIndex contains the index of the next descriptor going to be transmitted by
the hardware. When TxProduceIndex == TxConsumeIndex, the transmit buffer is empty.
When TxProduceIndex == TxConsumeIndex -1 (taking wraparound into account), thetransmit buffer is full and the software driver cannot add new descriptors until the
hardware has transmitted one or more frames to free up descriptors.
Each transmit descriptor takes two word locations (8 bytes) in memory. Likewise eachstatus field takes one word (4 bytes) in memory. Each transmit descriptor consists of apointer to the data buffer containing transmit data (Packet) and a control word (Control).
The Packet field has a zero address offset, whereas the control field has a 4 byte addressoffset, see Table 11–186.
Table 186. Transmit descriptor fields
SymbolAddress offset

Bytes

Description

Packet0x0

4Base address of the data buffer containing transmit data.

Control

0x4

4Control information, see Table 11–187.

The data buffer pointer (Packet) is a 32 bit, byte aligned address value containing thebase address of the data buffer. The definition of the control word bits is listed inTable 11–187.
Table 187. Transmit descriptor control word
Bit

SymbolDescription

10:0

Size

Size in bytes of the data buffer. This is the size of the frame or fragment as itneeds to be fetched by the DMA manager. In most cases it will be equal to thebyte size of the data buffer pointed to by the Packet field of the descriptor. Sizeis -1 encoded e.g. a buffer of 8 bytes is encoded as the Size value 7.

25:11 -

Unused26

Override

Per frame override. If true, bits 30:27 will override the defaults from the MAC
internal registers. If false, bits 30:27 will be ignored and the default values
from the MAC will be used.

27

Huge

If true, enables huge frame, allowing unlimited frame sizes. When false,prevents transmission of more than the maximum frame length (MAXF[15:0]).

28

Pad

If true, pad short frames to 64 bytes.

29

CRC

If true, append a hardware CRC to the frame.

30

Last

If true, indicates that this is the descriptor for the last fragment in the transmit
frame. If false, the fragment from the next descriptor should be appended.

31

Interrupt

If true, a TxDone interrupt will be generated when the data in this frame orframe fragment has been sent and the associated status information has beencommitted to memory.

Table 11–188 shows the one field transmit status.
Table 188. Transmit status fields
SymbolAddress
offsetBytes

Description

StatusInfo

0x0

4

Transmit status return flags, see Table 11–189.

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The transmit status consists of one word which is the StatusInfo word. It contains flags
returned by the MAC and flags generated by the transmit datapath reflecting the status of
the transmission. Table 11–189 lists the bit definitions in the StatusInfo word.
Table 189. Transmit status information word
Bit

SymbolDescription

20:0

-

Unused

24:21 CollisionCountThe number of collisions this packet incurred, up to the
Retransmission Maximum.

25

Defer

This packet incurred deferral, because the medium was occupied.
This is not an error unless excessive deferral occurs.

26

ExcessiveDefer

This packet incurred deferral beyond the maximum deferral limit andwas aborted.

27

ExcessiveCollision Indicates this packet exceeded the maximum collision limit and wasaborted.

28

LateCollision

An Out of window Collision was seen, causing packet abort.

29

Underrun

A Tx underrun occurred due to the adapter not producing transmit
data.

30

NoDescriptor

The transmit stream was interrupted because a descriptor was notavailable.

31

Error

An error occurred during transmission. This is a logical OR ofUnderrun, LateCollision, ExcessiveCollision, and ExcessiveDefer.

For multi-fragment frames, the value of the LateCollision, ExcessiveCollision,
ExcessiveDefer, Defer and CollissionCount bits in all but the last fragment in the frame willbe 0. The status of the last fragment in the frame will copy the value for these bits from the
MAC. All fragment statuses will have valid Error, NoDescriptor and Underrun bits.

15. Ethernet block functional description
This section defines the functions of the DMA capable 10/100 Ethernet MAC. After
introducing the DMA concepts of the Ethernet block, and a description of the basic
transmit and receive functions, this section elaborates on advanced features such as flow
control, receive filtering, etc.

15.1 Overview
The Ethernet block can transmit and receive Ethernet packets from an off-chip Ethernet
PHY connected through the MII or RMII interface. MII or RMII mode can be selected fromsoftware.
Typically during system start-up, the Ethernet block will be initialized. Software
initialization of the Ethernet block should include initialization of the descriptor and statusarrays as well as the receiver fragment buffers.
To transmit a packet the software driver has to set up the appropriate Control registers
and a descriptor to point to the packet data buffer before transferring the packet tohardware by incrementing the TxProduceIndex register. After transmission, hardware will
increment TxConsumeIndex and optionally generate an interrupt.

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The hardware will receive packets from the PHY and apply filtering as configured by thesoftware driver. While receiving a packet the hardware will read a descriptor from memory
to find the location of the associated receiver data buffer. Receive data is written in thedata buffer and receive status is returned in the receive descriptor status word. Optionallyan interrupt can be generated to notify software that a packet has been received. Notethat the DMA manager will prefetch and buffer up to three descriptors.

15.2 AHB interface
The registers of the Ethernet block connect to an AHB slave interface to allow access to
the registers from the CPU.
The AHB interface has a 32 bit data path, which supports only word accesses and has anaddress aperture of 4 kB. Table 11–134 lists the registers of the Ethernet block.
All AHB write accesses to registers are posted except for accesses to the IntSet, IntClear
and IntEnable registers. AHB write operations are executed in order.
If the PowerDown bit of the PowerDown register is set, all AHB read and write accesses
will return a read or write error except for accesses to the PowerDown register.
Bus Errors
The Ethernet block generates errors for several conditions:• The AHB interface will return a read error when there is an AHB read access to awrite-only register; likewise a write error is returned when there is an AHB write
access to the read-only register. An AHB read or write error will be returned on AHB
read or write accesses to reserved registers. These errors are propagated back to theCPU. Registers defined as read-only and write-only are identified in Table 11–134.

• If the PowerDown bit is set all accesses to AHB registers will result in an error
response except for accesses to the PowerDown register.

16. Interrupts
The Ethernet block has a single interrupt request output to the CPU (via the Vectored
Interrupt Controller).
The interrupt service routine must read the IntStatus register to determine the origin of theinterrupt. All interrupt statuses can be set by software writing to the IntSet register;
statuses can be cleared by software writing to the IntClear register.
The transmit and receive datapaths can only set interrupt statuses, they cannot clear
statuses. The SoftInt interrupt cannot be set by hardware and can be used by software fortest purposes.

16.1 Direct Memory Access (DMA)
Descriptor arrays
The Ethernet block includes two DMA managers. The DMA managers make it possible totransfer frames directly to and from memory with little support from the processor andwithout the need to trigger an interrupt for each frame.
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The DMA managers work with arrays of frame descriptors and statuses that are stored inmemory. The descriptors and statuses act as an interface between the Ethernet hardware
and the device driver software. There is one descriptor array for receive frames and one
descriptor array for transmit frames. Using buffering for frame descriptors, the memory
traffic and memory bandwidth utilization of descriptors can be kept small.
Each frame descriptor contains two 32 bit fields: the first field is a pointer to a data buffer
containing a frame or a fragment, whereas the second field is a control word related tothat frame or fragment.
The software driver must write the base addresses of the descriptor and status arrays in
the TxDescriptor/RxDescriptor and TxStatus/RxStatus registers. The number ofdescriptors/statuses in each array must be written in the
TxDescriptorNumber/RxDescriptorNumber registers. The number of descriptors in anarray corresponds to the number of statuses in the associated status array.
Transmit descriptor arrays, receive descriptor arrays and transmit status arrays must bealigned on a 4 byte (32bit)address boundary, while the receive status array must bealigned on a 8 byte (64bit) address boundary.
Ownership of descriptors
Both device driver software and Ethernet hardware can read and write the descriptor
arrays at the same time in order to produce and consume descriptors. Arbitration on the
AHB bus gives priority to the DMA hardware in the case of simultaneous requests. A
descriptor is "owned" either by the device driver or by the Ethernet hardware. Only theowner of a descriptor reads or writes its value. Typically, the sequence of use andownership of descriptors and statuses is as follows: a descriptor is owned and set up by
the device driver; ownership of the descriptor/status is passed by the device driver to the
Ethernet block, which reads the descriptor and writes information to the status field; theEthernet block passes ownership of the descriptor back to the device driver, which uses
the status information and then recycles the descriptor to be used for another frame.
Software must pre-allocate the memory used to hold the descriptor arrays.
Software can hand over ownership of descriptors and statuses to the hardware byincrementing (and wrapping if on the array boundary) the
TxProduceIndex/RxConsumeIndex registers. Hardware hands over descriptors andstatus to software by updating the TxConsumeIndex/ RxProduceIndex registers.
After handing over a descriptor to the receive and transmit DMA hardware, device driver
software should not modify the descriptor or reclaim the descriptor by decrementing the
TxProduceIndex/ RxConsumeIndex registers because descriptors may have been
prefetched by the hardware. In this case the device driver software will have to wait until
the frame has been transmitted or the device driver has to soft-reset the transmit and/or
receive datapaths which will also reset the descriptor arrays.
Sequential order with wrap-around
When descriptors are read from and statuses are written to the arrays, this is done insequential order with wrap-around. Sequential order means that when the Ethernet block
has finished reading/writing a descriptor/status, the next descriptor/status it reads/writes isthe one at the next higher, adjacent memory address. Wrap around means that when the

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Ethernet block has finished reading/writing the last descriptor/status of the array (with thehighest memory address), the next descriptor/status it reads/writes is the firstdescriptor/status of the array at the base address of the array.
Full and Empty state of descriptor arrays
The descriptor arrays can be empty, partially full or full. A descriptor array is empty when
all descriptors are owned by the producer. A descriptor array is partially full if bothproducer and consumer own part of the descriptors and both are busy processing thosedescriptors. A descriptor array is full when all descriptors (except one) are owned by the
consumer, so that the producer has no more room to process frames. Ownership ofdescriptors is indicated with the use of a consume index and a produce index. The
produce index is the first element of the array owned by the producer. It is also the index
of the array element that is next going to be used by the producer of frames (it may
already be busy using it and subsequent elements). The consume index is the firstelement of the array that is owned by the consumer. It is also the number of the arrayelement next to be consumed by the consumer of frames (it and subsequent elements
may already be in the process of being consumed). If the consume index and the produce
index are equal, the descriptor array is empty and all array elements are owned by the
producer. If the consume index equals the produce index plus one, then the array is fulland all array elements (except the one at the produce index) are owned by the consumer.
With a full descriptor array, still one array element is kept empty, to be able to easily
distinguish the full or empty state by looking at the value of the produce index andconsume index. An array must have at least 2 elements to be able to indicate a fulldescriptor array with a produce index of value 0 and a consume index of value 1. The
wrap around of the arrays is taken into account when determining if a descriptor array isfull, so a produce index that indicates the last element in the array and a consume index
that indicates the first element in the array, also means the descriptor array is full. Whenthe produce index and the consume index are unequal and the consume index is not the
produce index plus one (with wrap around taken into account), then the descriptor array ispartially full and both the consumer and producer own enough descriptors to be able tooperate actively on the descriptor array.
Interrupt bit
The descriptors have an Interrupt bit, which is programmed by software. When the
Ethernet block is processing a descriptor and finds this bit set, it will allow triggering aninterrupt (after committing status to memory) by passing the RxDoneInt or TxDoneInt bitsin the IntStatus register to the interrupt output pin. If the Interrupt bit is not set in thedescriptor, then the RxDoneInt or TxDoneInt are not set and no interrupt is triggered (notethat the corresponding bits in IntEnable must also be set to trigger interrupts). This offers
flexible ways of managing the descriptor arrays. For instance, the device driver could add
10 frames to the Tx descriptor array, and set the Interrupt bit in descriptor number 5 in thedescriptor array. This would invoke the interrupt service routine before the transmit
descriptor array is completely exhausted. The device driver could add another batch offrames to the descriptor array, without interrupting continuous transmission of frames.
Frame fragments
For maximum flexibility in frame storage, frames can be split up into multiple frame
fragments with fragments located in different places in memory. In this case one
descriptor is used for each frame fragment. So, a descriptor can point to a single frame or

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to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit
frames are gathered from multiple fragments in memory and receive frames can be
scattered to multiple fragments in memory.
By stringing together fragments it is possible to create large frames from small memoryareas. Another use of fragments is to be able to locate a frame header and frame payload
in different places and to concatenate them without copy operations in the device driver.
For transmissions, the Last bit in the descriptor Control field indicates if the fragment is thelast in a frame; for receive frames, the LastFrag bit in the StatusInfo field of the statuswords indicates if the fragment is the last in the frame. If the Last(Frag) bit is 0 the next
descriptor belongs to the same Ethernet frame, If the Last(Frag) bit is 1 the next descriptor
is a new Ethernet frame.

16.2 Initialization
After reset, the Ethernet software driver needs to initialize the Ethernet block. Duringinitialization the software needs to:• Remove the soft reset condition from the MAC• Configure the PHY via the MIIM interface of the MAC• Select RMII or MII mode
• Configure the transmit and receive DMA engines, including the descriptor arrays• Configure the host registers (MAC1,MAC2 etc.) in the MAC• Enable the receive and transmit datapaths
Depending on the PHY, the software needs to initialize registers in the PHY via the MIIManagement interface. The software can read and write PHY registers by programming
the MCFG, MCMD, MADR registers of the MAC. Write data should be written to the
MWTD register; read data and status information can be read from the MRDD and MIND
registers.
The Ethernet block supports RMII and MII PHYs. During initialization software must selectMII or RMII mode by programming the Command register. After initialization, the RMII or
MII mode should not be modified.
Before switching to RMII mode the default soft reset (MAC1 register bit 15) has to bedeasserted when the Ethernet block is in MII mode . The phy_tx_clk and phy_rx_clk arenecessary during this operation. In case an RMII PHY is used (which does not provide
these clock signals), phy_tx_clk and phy_rx_clk can be connected to the phy_ref_clk.
Transmit and receive DMA engines should be initialized by the device driver by allocating
the descriptor and status arrays in memory. Transmit and receive functions have their own
dedicated descriptor and status arrays. The base addresses of these arrays need to be
programmed in the TxDescriptor/TxStatus and RxDescriptor/RxStatus registers. The
number of descriptors in an array matches the number of statuses in an array.
Please note that the transmit descriptors, receive descriptors and receive statuses are 8
bytes each while the transmit statuses are 4 bytes each. All descriptor arrays and transmit
statuses need to be aligned on 4 byte boundaries; receive status arrays need to bealigned on 8 byte boundaries. The number of descriptors in the descriptor arrays needs toUM10211_1

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be written to the TxDescriptorNumber/RxDescriptorNumber registers using a -1 encoding
i.e. the value in the registers is the number of descriptors minus one e.g. if the descriptor
array has 4 descriptors the value of the number of descriptors register should be 3.
After setting up the descriptor arrays, frame buffers need to be allocated for the receive
descriptors before enabling the receive datapath. The Packet field of the receive
descriptors needs to be filled with the base address of the frame buffer of that descriptor.
Amongst others the Control field in the receive descriptor needs to contain the size of thedata buffer using -1 encoding.
The receive datapath has a configurable filtering function for discarding/ignoring specific
Ethernet frames. The filtering function should also be configured during initialization.
After an assertion of the hardware reset, the soft reset bit in the MAC will be asserted. The
soft reset condition must be removed before the Ethernet block can be enabled.
Enabling of the receive function is located in two places. The receive DMA manager
needs to be enabled and the receive datapath of the MAC needs to be enabled. To
prevent overflow in the receive DMA engine the receive DMA engine should be enabled
by setting the RxEnable bit in the Command register before enabling the receive datapath
in the MAC by setting the RECEIVE ENABLE bit in the MAC1 register.
The transmit DMA engine can be enabled at any time by setting the TxEnable bit in theCommand register.
Before enabling the datapaths, several options can be programmed in the MAC, such as
automatic flow control, transmit to receive loop-back for verification, full/half duplex
modes, etc.
Base addresses of descriptor arrays and descriptor array sizes cannot be modified
without a (soft) reset of the receive and transmit datapaths.

16.3 Transmit process
Overview
This section outlines the transmission process.
Device driver sets up descriptors and data
If the descriptor array is full the device driver should wait for the descriptor arrays to
become not full before writing to a descriptor in the descriptor array. If the descriptor arrayis not full, the device driver should use the descriptor numbered TxProduceIndex of thearray pointed to by TxDescriptor.
The Packet pointer in the descriptor is set to point to a data frame or frame fragment to betransmitted. The Size field in the Command field of the descriptor should be set to thenumber of bytes in the fragment buffer, -1 encoded. Additional control information can beindicated in the Control field in the descriptor (bits Interrupt, Last, CRC, Pad).
After writing the descriptor the descriptor needs to be handed over to the hardware byincrementing (and possibly wrapping) the TxProduceIndex register.
If the transmit datapath is disabled, the device driver should not forget to enable thetransmit datapath by setting the TxEnable bit in the Command register.
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When there is a multi-fragment transmission for fragments other than the last, the Last bitin the descriptor must be set to 0; for the last fragment the Last bit must be set to 1. To
trigger an interrupt when the frame has been transmitted and transmission status has
been committed to memory, set the Interrupt bit in the descriptor Control field to 1. To havethe hardware add a CRC in the frame sequence control field of this Ethernet frame, set
the CRC bit in the descriptor. This should be done if the CRC has not already been added
by software. To enable automatic padding of small frames to the minimum required framesize, set the Pad bit in the Control field of the descriptor to 1. In typical applications bits
CRC and Pad are both set to 1.
The device driver can set up interrupts using the IntEnable register to wait for a signal ofcompletion from the hardware or can periodically inspect (poll) the progress oftransmission. It can also add new frames at the end of the descriptor array, while
hardware consumes descriptors at the start of the array.
The device driver can stop the transmit process by resetting the TxEnable bit in theCommand register to 0. The transmission will not stop immediately; frames already beingtransmitted will be transmitted completely and the status will be committed to memory
before deactivating the datapath. The status of the transmit datapath can be monitored by
the device driver reading the TxStatus bit in the Status register.
As soon as the transmit datapath is enabled and the corresponding TxConsumeIndex and
TxProduceIndex are not equal i.e. the hardware still needs to process frames from thedescriptor array, the TxStatus bit in the Status register will return to 1 (active).
Tx DMA manager reads the Tx descriptor array
When the TxEnable bit is set, the Tx DMA manager reads the descriptors from memory at
the address determined by TxDescriptor and TxConsumeIndex. The number ofdescriptors requested is determined by the total number of descriptors owned by the
hardware: TxProduceIndex - TxConsumeIndex. Block transferring descriptors minimizes
memory loading. Read data returned from memory is buffered and consumed as needed.
Tx DMA manager transmits data
After reading the descriptor the transmit DMA engine reads the associated frame datafrom memory and transmits the frame. After transfer completion, the Tx DMA manager
writes status information back to the StatusInfo and StatusHashCRC words of the status
field. The value of the TxConsumeIndex is only updated after status information has beencommitted to memory, which is checked by an internal tag protocol in the memory
interface. The Tx DMA manager continues to transmit frames until the descriptor array is
empty. If the transmit descriptor array is empty the TxStatus bit in the Status register will
return to 0 (inactive). If the descriptor array is empty the Ethernet hardware will set the
TxFinishedInt bit of the IntStatus register. The transmit datapath will still be enabled.
The Tx DMA manager inspects the Last bit of the descriptor Control field when loading thedescriptor. If the Last bit is 0, this indicates that the frame consists of multiple fragments.
The Tx DMA manager gathers all the fragments from the host memory, visiting a string offrame descriptors, and sends them out as one Ethernet frame on the Ethernet connection.
When the Tx DMA manager finds a descriptor with the Last bit in the Control field set to 1,
this indicates the last fragment of the frame and thus the end of the frame is found.
Update ConsumeIndex
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Each time the Tx DMA manager commits a status word to memory it completes thetransmission of a descriptor and it increments the TxConsumeIndex (taking wrap aroundinto account) to hand the descriptor back to the device driver software. Software canre-use the descriptor for new transmissions after hardware has handed it back.
The device driver software can keep track of the progress of the DMA manager by reading
the TxConsumeIndex register to see how far along the transmit process is. When the Tx
descriptor array is emptied completely, the TxConsumeIndex register retains its last value.
Write transmission status
After the frame has been transmitted over the (R)MII bus, the StatusInfo word of the frame
descriptor is updated by the DMA manager.
If the descriptor is for the last fragment of a frame (or for the whole frame if there are no
fragments), then depending on the success or failure of the frame transmission, error
flags (Error, LateCollision, ExcessiveCollision, Underrun, ExcessiveDefer, Defer) are set
in the status. The CollisionCount field is set to the number of collisions the frame incurred,
up to the Retransmission Maximum programmed in the Collision window/retry register ofthe MAC.
Statuses for all but the last fragment in the frame will be written as soon as the data in theframe has been accepted by the Tx DMA manager. Even if the descriptor is for a frame
fragment other than the last fragment, the error flags are returned via the AHB interface. If
the Ethernet block detects a transmission error during transmission of a (multi-fragment)
frame, all remaining fragments of the frame are still read via the AHB interface. After anerror, the remaining transmit data is discarded by the Ethernet block. If there are errors
during transmission of a multi-fragment frame the error statuses will be repeated until thelast fragment of the frame. Statuses for all but the last fragment in the frame will be written
as soon as the data in the frame has been accepted by the Tx DMA manager. These may
include error information if the error is detected early enough. The status for the lastfragment in the frame will only be written after the transmission has completed on the
Ethernet connection. Thus, the status for the last fragment will always reflect any errorthat occurred anywhere in the frame.
The status of the last frame transmission can also be inspected by reading the TSV0 and
TSV1 registers. These registers do not report statuses on a fragment basis and do notstore information of previously sent frames. They are provided primarily for debug
purposes, because the communication between driver software and the Ethernet block
takes place through the frame descriptors. The status registers are valid as long as theinternal status of the MAC is valid and should typically only be read when the transmit andreceive processes are halted.
Transmission error handlingIf an error occurs during the transmit process, the Tx DMA manager will report the error
via the transmission StatusInfo word written in the Status array and the IntStatus interrupt
status register.
The transmission can generate several types of errors: LateCollision, ExcessiveCollision,
ExcessiveDefer, Underrun, and NoDescriptor. All have corresponding bits in thetransmission StatusInfo word. In addition to the separate bits in the StatusInfo word,
LateCollision, ExcessiveCollision, and ExcessiveDefer are ORed together into the Error
bit of the Status. Errors are also propagated to the IntStatus register; the TxError bit in the
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IntStatus register is set in the case of a LateCollision, ExcessiveCollision, ExcessiveDefer,or NoDescriptor error; Underrun errors are reported in the TxUnderrun bit of the IntStatus
register.
Underrun errors can have three causes:• The next fragment in a multi-fragment transmission is not available. This is a nonfatal
error. A NoDescriptor status will be returned on the previous fragment and the TxError
bit in IntStatus will be set.

• The transmission fragment data is not available when the Ethernet block has alreadystarted sending the frame. This is a nonfatal error. An Underrun status will be returnedon transfer and the TxError bit in IntStatus will be set.

• The flow of transmission statuses stalls and a new status has to be written while aprevious status still waits to be transferred across the memory interface. This is a fatal
error which can only be resolved by a soft reset of the hardware.
The first and second situations are nonfatal and the device driver has to resend the frameor have upper software layers resend the frame. In the third case the hardware is in an
undefined state and needs to be soft reset by setting the TxReset bit in the Command
register.
After reporting a LateCollision, ExcessiveCollision, ExcessiveDefer or Underrun error, thetransmission of the erroneous frame will be aborted, remaining transmission data andframe fragments will be discarded and transmission will continue with the next frame inthe descriptor array.
Device drivers should catch the transmission errors and take action.
Transmit triggers interrupts
The transmit datapath can generate four different interrupt types:• If the Interrupt bit in the descriptor Control field is set, the Tx DMA will set the
TxDoneInt bit in the IntStatus register after sending the fragment and committing theassociated transmission status to memory. Even if a descriptor (fragment) is not thelast in a multi-fragment frame the Interrupt bit in the descriptor can be used togenerate an interrupt.

• If the descriptor array is empty while the Ethernet hardware is enabled the hardware
will set the TxFinishedInt bit of the IntStatus register.

• If the AHB interface does not consume the transmission statuses at a sufficiently highbandwidth the transmission may underrun in which case the TxUnderrun bit will be set
in the IntStatus register. This is a fatal error which requires a soft reset of thetransmission queue.

• In the case of a transmission error (LateCollision, ExcessiveCollision, orExcessiveDefer) or a multi-fragment frame where the device driver did provide theinitial fragments but did not provide the rest of the fragments (NoDescriptor) or in thecase of a nonfatal overrun, the hardware will set the TxErrorInt bit of the IntStatus
register.

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All of the above interrupts can be enabled and disabled by setting or resetting thecorresponding bits in the IntEnable register. Enabling or disabling does not affect the
IntStatus register contents, only the propagation of the interrupt status to the CPU (via the
Vectored Interrupt Controller).
The interrupts, either of individual frames or of the whole list, are a good means ofcommunication between the DMA manager and the device driver, triggering the device
driver to inspect the status words of descriptors that have been processed.
Transmit example

status 0

StatusInfo

status 1

StatusInfo

status 2

StatusInfo

StatusInfo

0x7FE011F8

0x7FE011FC

3
Control
0x7FE0100 1 1 CONTROL

0x7FE0132B

Packet0x7FE01419

0x7FE01324

0x7FE010FC

0 0 CONTROL
7
Control

descriptor 2

descriptor array

0x7FE010F8

Packet0x7FE01411

descriptor 1

PACKET 0 PAYLOAD (12 bytes)
0x7FE010F4

0x7FE0104

0x7FE01108

Packet0x7FE01324

7
0 0 CONTROL
Control
descriptor arraydescriptor 3

PACKET 1 HEADER (8 bytes)

0x7FE01200

status array

0x7FE0141C

0x7FE01419

0 0 CONTROL
Control
7

0x7FE01411

PACKET 0 HEADER (8 bytes)
Packet0x7FE01314

descriptor 0

0x7FE010F0

TxStatus
0x7FE011F8

status 3

0x7FE01314

TxDescriptor
0x7FE010EC

0x7FE010EC

0x7FE0131B

Figure 11–23 illustrates the transmit process in an example transmitting uses a frame
header of 8 bytes and a frame payload of 12 bytes.

0x7FE01204

TxProduceIndex
TxConsumeIndex
TxDescriptorNumber=3

fragment buffers

status arrayFig 23. Transmit example memory and registers

After reset the values of the DMA registers will be zero. During initialization the device
driver will allocate the descriptor and status array in memory. In this example, an array offour descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address
boundary. Since the number of descriptors matches the number of statuses the statusarray consists of four elements; the array is 4x1x4 bytes and aligned on a 4 byte address
boundary. The device driver writes the base address of the descriptor array(0x7FE0 10EC) to the TxDescriptor register and the base address of the status array

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Chapter 11: LPC2300 Ethernet(0x7FE0 11F8) to the TxStatus register. The device driver writes the number of descriptors
and statuses minus 1(3) to the TxDescriptorNumber register. The descriptors andstatuses in the arrays need not be initialized, yet.
At this point, the transmit datapath may be enabled by setting the TxEnable bit in theCommand register. If the transmit datapath is enabled while there are no further frames tosend the TxFinishedInt interrupt flag will be set. To reduce the processor interrupt load
only the desired interrupts can be enabled by setting the relevant bits in the IntEnableregister.
Now suppose application software wants to transmit a frame of 12 bytes using a TCP/IP
protocol (in real applications frames will be larger than 12 bytes). The TCP/IP stack will
add a header to the frame. The frame header need not be immediately in front of the
payload data in memory. The device driver can program the Tx DMA to collect header andpayload data. To do so, the device driver will program the first descriptor to point at theframe header; the Last flag in the descriptor will be set to false/0 to indicate amulti-fragment transmission. The device driver will program the next descriptor to point at
the actual payload data. The maximum size of a payload buffer is 2 kB so a single
descriptor suffices to describe the payload buffer. For the sake of the example though the
payload is distributed across two descriptors. After the first descriptor in the arraydescribing the header, the second descriptor in the array describes the initial 8 bytes ofthe payload; the third descriptor in the array describes the remaining 4 bytes of the frame.
In the third descriptor the Last bit in the Control word is set to true/1 to indicate it is the lastdescriptor in the frame. In this example the Interrupt bit in the descriptor Control field is set
in the last fragment of the frame in order to trigger an interrupt after the transmission
completed. The Size field in the descriptor’s Control word is set to the number of bytes in
the fragment buffer, -1 encoded.
Note that in real device drivers, the payload will typically only be split across multiple
descriptors if it is more than 2 kB. Also note that transmission payload data is forwarded tothe hardware without the device driver copying it (zero copy device driver).
After setting up the descriptors for the transaction the device driver increments the
TxProduceIndex register by 3 since three descriptors have been programmed. If thetransmit datapath was not enabled during initialization the device driver needs to enable
the datapath now.
If the transmit datapath is enabled the Ethernet block will start transmitting the frame assoon as it detects the TxProduceIndex is not equal to TxConsumeIndex - both were zeroafter reset. The Tx DMA will start reading the descriptors from memory. The memory
system will return the descriptors and the Ethernet block will accept them one by one
while reading the transmit data fragments.
As soon as transmission read data is returned from memory, the Ethernet block will try tostart transmission on the Ethernet connection via the (R)MII interface.
After transmitting each fragment of the frame the Tx DMA will write the status of thefragment’s transmission. Statuses for all but the last fragment in the frame will be written
as soon as the data in the frame has been accepted by the Tx DMA manager. The status
for the last fragment in the frame will only be written after the transmission has completed
on the Ethernet connection.

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Since the Interrupt bit in the descriptor of the last fragment is set, after committing thestatus of the last fragment to memory the Ethernet block will trigger a TxDoneInt interrupt,
which triggers the device driver to inspect the status information.
In this example the device driver cannot add new descriptors as long as the Ethernet
block has not incremented the TxConsumeIndex because the descriptor array is full (eventhough one descriptor is not programmed yet). Only after the hardware commits the status
for the first fragment to memory and the TxConsumeIndex is set to 1 by the DMA manager
can the device driver program the next (the fourth) descriptor. The fourth descriptor canalready be programmed before completely transmitting the first frame.
In this example the hardware adds the CRC to the frame. If the device driver softwareadds the CRC, the CRC trailer can be considered another frame fragment which can be
added by doing another gather DMA.
Each data byte is transmitted across the MII interface as two nibbles. On the MII interface
the Ethernet block adds the preamble, frame delimiter leader, and the CRC trailer if
hardware CRC is enabled. Once transmission on the MII interface commences thetransmission cannot be interrupted without generating an underrun error, which is why
descriptors and data read commands are issued as soon as possible and pipelined.
For an RMII PHY, the data communication between the Ethernet block and the PHY iscommunicated at half the data-width (2 bits) and twice the clock frequency (50 MHz). In
10 Mbps mode data will only be transmitted once every 10 clock cycles.

16.4 Receive processThis section outlines the receive process including the activities in the device driver
software.
Device driver sets up descriptors
After initializing the receive descriptor and status arrays to receive frames from the
Ethernet connection, the receive datapath should be enabled in the MAC1 register andthe Control register.
During initialization, each Packet pointer in the descriptors is set to point to a datafragment buffer. The size of the buffer is stored in the Size bits of the Control field of thedescriptor. Additionally, the Control field in the descriptor has an Interrupt bit. The Interrupt
bit allows generation of an interrupt after a fragment buffer has been filled and its status
has been committed to memory.
After the initialization and enabling of the receive datapath, all descriptors are owned by
the receive hardware and should not be modified by the software unless hardware hands
over the descriptor by incrementing the RxProduceIndex, indicating that a frame has been
received. The device driver is allowed to modify the descriptors after a (soft) reset of thereceive datapath.
Rx DMA manager reads Rx descriptor arrays
When the RxEnable bit in the Command register is set, the Rx DMA manager reads thedescriptors from memory at the address determined by RxDescriptor and
RxProduceIndex. The Ethernet block will start reading descriptors even before actual
receive data arrives on the (R)MII interface (descriptor prefetching). The block size of theUM10211_1

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descriptors to be read is determined by the total number of descriptors owned by the
hardware: RxConsumeIndex - RxProduceIndex - 1. Block transferring of descriptors
minimizes memory load. Read data returned from memory is buffered and consumed asneeded.
RX DMA manager receives data
After reading the descriptor, the receive DMA engine waits for the MAC to return receive
data from the (R)MII interface that passes the receive filter. Receive frames that do notmatch the filtering criteria are not passed to memory. Once a frame passes the receive
filter, the data is written in the fragment buffer associated with the descriptor. The Rx DMA
does not write beyond the size of the buffer. When a frame is received that is larger than adescriptor’s fragment buffer, the frame will be written to multiple fragment buffers ofconsecutive descriptors. In the case of a multi-fragment reception, all but the last fragmentin the frame will return a status where the LastFrag bit is set to 0. Only on the lastfragment of a frame the LastFrag bit in the status will be set to 1. If a fragment buffer is thelast of a frame, the buffer may not be filled completely. The first receive data of the next
frame will be written to the fragment buffer of the next descriptor.
After receiving a fragment, the Rx DMA manager writes status information back to the
StatusInfo and StatusHashCRC words of the status. The Ethernet block writes the size inbytes of a descriptor’s fragment buffer in the RxSize field of the Status word. The value of
the RxProduceIndex is only updated after the fragment data and the fragment status
information has been committed to memory, which is checked by an internal tag protocolin the memory interface. The Rx DMA manager continues to receive frames until thedescriptor array is full. If the descriptor array is full, the Ethernet hardware will set the
RxFinishedInt bit of the IntStatus register. The receive datapath will still be enabled. If thereceive descriptor array is full any new receive data will generate an overflow error andinterrupt.
Update ProduceIndex
Each time the Rx DMA manager commits a data fragment and the associated status word
to memory, it completes the reception of a descriptor and increments the RxProduceIndex(taking wrap around into account) in order to hand the descriptor back to the device driver
software. Software can re-use the descriptor for new receptions by handing it back to
hardware when the receive data has been processed.
The device driver software can keep track of the progress of the DMA manager by reading
the RxProduceIndex register to see how far along the receive process is. When the Rx
descriptor array is emptied completely, the RxProduceIndex retains its last value.
Write reception status
After the frame has been received from the (R)MII bus, the StatusInfo andStatusHashCRC words of the frame descriptor are
updated by the DMA manager.
If the descriptor is for the last fragment of a frame (or for the whole frame if there are no
fragments), then depending on the success or failure of the frame reception, error flags(Error, NoDescriptor, Overrun, AlignmentError, RangeError, LengthError, SymbolError, or
CRCError) are set in StatusInfo. The RxSize field is set to the number of bytes actually
written to the fragment buffer, -1 encoded. For fragments not being the last in the frame
the RxSize will match the size of the buffer. The hash CRCs of the destination and source
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addresses of a packet are calculated once for all the fragments belonging to the same
packet and then stored in every StatusHashCRC word of the statuses associated with thecorresponding fragments. If the reception reports an error, any remaining data in thereceive frame is discarded and the LastFrag bit will be set in the receive status field, so
the error flags in all but the last fragment of a frame will always be 0.
The status of the last received frame can also be inspected by reading the RSV register.
The register does not report statuses on a fragment basis and does not store informationof previously received frames. RSV is provided primarily for debug purposes, because thecommunication between driver software and the Ethernet block takes place through theframe descriptors.
Reception error handling
When an error occurs during the receive process, the Rx DMA manager will report theerror via the receive StatusInfo written in the Status array and the IntStatus interrupt status
register.
The receive process can generate several types of errors: AlignmentError, RangeError,
LengthError, SymbolError, CRCError, Overrun, and NoDescriptor. All have corresponding
bits in the receive StatusInfo. In addition to the separate bits in the StatusInfo,
AlignmentError, RangeError, LengthError, SymbolError, and CRCError are ORed together
into the Error bit of the StatusInfo. Errors are also propagated to the IntStatus register; theRxError bit in the IntStatus register is set if there is an AlignmentError, RangeError,
LengthError, SymbolError, CRCError, or NoDescriptor error; nonfatal overrun errors arereported in the RxError bit of the IntStatus register; fatal Overrun errors are report in the
RxOverrun bit of the IntStatus register. On fatal overrun errors, the Rx datapath needs tobe soft reset by setting the RxReset bit in the Command register.
Overrun errors can have three causes:• In the case of a multi-fragment reception, the next descriptor may be missing. In thiscase the NoDescriptor field is set in the status word of the previous descriptor and theRxError in the IntStatus register is set. This error is nonfatal.

• The data flow on the receiver data interface stalls, corrupting the packet. In this casethe overrun bit in the status word is set and the RxError bit in the IntStatus register isset. This error is nonfatal.

• The flow of reception statuses stalls and a new status has to be written while aprevious status still waits to be transferred across the memory interface. This error will
corrupt the hardware state and requires the hardware to be soft reset. The error is
detected and sets the Overrun bit in the IntStatus register.
The first overrun situation will result in an incomplete frame with a NoDescriptor status
and the RxError bit in IntStatus set. Software should discard the partially received frame.
In the second overrun situation the frame data will be corrupt which results in the Overrun
status bit being set in the Status word while the IntError interrupt bit is set. In the third casereceive errors cannot be reported in the receiver Status arrays which corrupts the
hardware state; the errors will still be reported in the IntStatus register’s Overrun bit. The
RxReset bit in the Command register should be used to soft reset the hardware.
Device drivers should catch the above receive errors and take action.
Receive triggers interrupts
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The receive datapath can generate four different interrupt types:• If the Interrupt bit in the descriptor Control field is set, the Rx DMA will set the
RxDoneInt bit in the IntStatus register after receiving a fragment and committing theassociated data and status to memory. Even if a descriptor (fragment) is not the last ina multi-fragment frame, the Interrupt bit in the descriptor can be used to generate aninterrupt.

• If the descriptor array is full while the Ethernet hardware is enabled, the hardware will
set the RxFinishedInt bit of the IntStatus register.

• If the AHB interface does not consume receive statuses at a sufficiently highbandwidth, the receive status process may overrun, in which case the RxOverrun bit
will be set in the IntStatus register.

• If there is a receive error (AlignmentError, RangeError, LengthError, SymbolError, or
CRCError), or a multi-fragment frame where the device driver did provide descriptors
for the initial fragments but did not provide the descriptors for the rest of thefragments, or if a nonfatal data Overrun occurred, the hardware will set the RxErrorInt
bit of the IntStatus register.
All of the above interrupts can be enabled and disabled by setting or resetting thecorresponding bits in the IntEnable register. Enabling or disabling does not affect the
IntStatus register contents, only the propagation of the interrupt status to the CPU (via the
Vectored Interrupt Controller).
The interrupts, either of individual frames or of the whole list, are a good means ofcommunication between the DMA manager and the device driver, triggering the device
driver to inspect the status words of descriptors that have been processed.
Device driver processes receive data
As a response to status (e.g. RxDoneInt) interrupts or polling of the RxProduceIndex, thedevice driver can read the descriptors that have been handed over to it by the hardware(RxProduceIndex - RxConsumeIndex). The device driver should inspect the status words
in the status array to check for multi-fragment receptions and receive errors.
The device driver can forward receive data and status to upper software layers. After
processing of data and status, the descriptors, statuses and data buffers may be recycled
and handed back to hardware by incrementing the RxConsumeIndex.
Receive example
Figure 11–24 illustrates the receive process in an example receiving a frame of 19 bytes.

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Status 0

StatusInfo

7

0x7FE011F8

StatusHashCRC
StatusInfo

7

0x7FE01200

StatusHashCRC

0x7FE01100 1 CONTROL 7

0x7FE01325

PACKET
0x7FE01419

Status 2

StatusInfo

2

0x7FE01208

StatusHashCRC
StatusInfo

7

0x7FE01210

StatusHashCRC

0x7FE0132C

FRAGMENT 2 BUFFER(3 bytes)
0x7FE010FC

Status 3

0x7FE0141B

0x7FE010F8 1 CONTROL 7

0x7FE01419

PACKET
0x7FE01411

Descriptor 2

descriptor array

0x7FE010F4

Descriptor 1

FRAGMENT 1 BUFFER(8 bytes)

status array

1 CONTROL 7

0x7FE01418

0x7FE010F0

0x7FE01411

FRAGMENT 0 BUFFER(8 bytes)
PACKET
0x7FE01409

Descriptor 0

0x7FE010EC

RxStatus
0x7FE011F8

Status 1

RxDescriptor
0x7FE010EC

0x7FE01410

0x7FE01409

Chapter 11: LPC2300 Ethernet

FRAGMENT 3 BUFFER(8 bytes)

0x7FE01108

1 CONTROL 7
descriptor array

RxProduceIndex

Descriptor 3

0x7FE01104

PACKET
0x7FE01325

RxConsumeIndex
RxDescriptorNumber= 3
fragment buffers

status arrayFig 24. Receive Example Memory and Registers

After reset, the values of the DMA registers will be zero. During initialization, the device
driver will allocate the descriptor and status array in memory. In this example, an array offour descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address
boundary. Since the number of descriptors matches the number of statuses, the statusarray consists of four elements; the array is 4x2x4 bytes and aligned on a 8 byte address
boundary. The device driver writes the base address of the descriptor array(0xFEED B0EC) in the RxDescriptor register, and the base address of the status array(0xFEED B1F8) in the RxStatus register. The device driver writes the number ofdescriptors and statuses minus 1 (3) in the RxDescriptorNumber register. The descriptors
and statuses in the arrays need not be initialized yet.
After allocating the descriptors, a fragment buffer needs to be allocated for each of thedescriptors. Each fragment buffer can be between 1 byte and 2 k bytes. The baseaddress of the fragment buffer is stored in the Packet field of the descriptors. The numberof bytes in the fragment buffer is stored in the Size field of the descriptor Control word.
The Interrupt field in the Control word of the descriptor can be set to generate an interrupt
as soon as the descriptor has been filled by the receive process. In this example thefragment buffers are 8 bytes, so the value of the Size field in the Control word of thedescriptor is set to 7. Note that in this example, the fragment buffers are actually aUM10211_1

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continuous memory space; even when a frame is distributed over multiple fragments it will
typically be in a linear, continuous memory space; when the descriptors wrap at the end of
the descriptor array the frame will not be in a continuous memory space.
The device driver should enable the receive process by writing a 1 to the RxEnable bit of
the Command register, after which the MAC needs to be enabled by writing a 1 to the‘RECEIVE ENABLE’ bit of the MAC1 configuration register. The Ethernet block will now
start receiving Ethernet frames. To reduce the processor interrupt load, some interrupts
can be disabled by setting the relevant bits in the IntEnable register.
After the Rx DMA manager is enabled, it will start issuing descriptor read commands. In
this example the number of descriptors is 4. Initially the RxProduceIndex and
RxConsumeIndex are 0. Since the descriptor array is considered full if RxProduceIndex== RxConsumeIndex - 1, the Rx DMA manager can only read (RxConsumeIndex RxProduceIndex - 1 =) 3 descriptors; note the wrapping.
After enabling the receive function in the MAC, data reception will begin starting at thenext frame i.e. if the receive function is enabled while the (R)MII interface is halfway
through receiving a frame, the frame will be discarded and reception will start at the next
frame. The Ethernet block will strip the preamble and start of frame delimiter from theframe. If the frame passes the receive filtering, the Rx DMA manager will start writing theframe to the first fragment buffer.
Suppose the frame is 19 bytes long. Due to the buffer sizes specified in this example, theframe will be distributed over three fragment buffers. After writing the initial 8 bytes in thefirst fragment buffer, the status for the first fragment buffer will be written and the Rx DMA
will continue filling the second fragment buffer. Since this is a multi-fragment receive, thestatus of the first fragment will have a 0 for the LastFrag bit in the StatusInfo word; theRxSize field will be set to 7 (8, -1 encoded). After writing the 8 bytes in the second
fragment the Rx DMA will continue writing the third fragment. The status of the second
fragment will be like the status of the first fragment: LastFrag = 0, RxSize = 7. After writing
the three bytes in the third fragment buffer, the end of the frame has been reached and thestatus of the third fragment is written. The third fragment’s status will have the LastFrag bit
set to 1 and the RxSize equal to 2 (3, -1 encoded).
The next frame received from the (R)MII interface will be written to the fourth fragment
buffer i.e. five bytes of the third buffer will be unused.
The Rx DMA manager uses an internal tag protocol in the memory interface to check thatthe receive data and status have been committed to memory. After the status of thefragments are committed to memory, an RxDoneInt interrupt will be triggered, which
activates the device driver to inspect the status information. In this example, alldescriptors have the Interrupt bit set in the Control word i.e. all descriptors will generate
an interrupt after committing data and status to memory.
In this example the receive function cannot read new descriptors as long as the device
driver does not increment the RxConsumeIndex, because the descriptor array is full (eventhough one descriptor is not programmed yet). Only after the device driver has forwarded
the receive data to application software, and after the device driver has updated the
RxConsumeIndex by incrementing it, will the Ethernet block can continue reading
descriptors and receive data. The device driver will probably increment the
RxConsumeIndex by 3, since the driver will forward the complete frame consisting of
three fragments to the application, and hence free up three descriptors at the same time.
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Each pair of nibbles transferred on the MII interface (or four pairs of bits for RMII) istransferred as a byte on the data write interface after being delayed by 128 or 136 cycles
for filtering by the receive filter and buffer modules. The Ethernet block removes
preamble, frame start delimiter, and CRC from the data and checks the CRC. To limit thebuffer NoDescriptor error probability, three descriptors are buffered. The value of the
RxProduceIndex is only updated after status information has been committed to memory,which is checked by an internal tag protocol in the memory interface. The software device
driver will process the receive data, after which the device driver will update the
RxConsumeIndex.
For an RMII PHY the data between the Ethernet block and the PHY is communicated at
half the data-width and twice the clock frequency (50 MHz).

16.5 Transmission retry
If a collision on the Ethernet occurs, it usually takes place during the collision window
spanning the first 64 bytes of a frame. If collision is detected, the Ethernet block will retry
the transmission. For this purpose, the first 64 bytes of a frame are buffered, so that thisdata can be used during the retry. A transmission retry within the first 64 bytes in a frame
is fully transparent to the application and device driver software.
When a collision occurs outside of the 64 byte collision window, a LateCollision error istriggered, and the transmission is aborted. After a LateCollision error, the remaining datain the transmit frame will be discarded. The Ethernet block will set the Error and
LateCollision bits in the frame’s status fields. The TxError bit in the IntStatus register will
be set. If the corresponding bit in the IntEnable register is set, the TxError bit in the
IntStatus register will be propagated to the CPU (via the Vectored Interrupt Controller).
The device driver software should catch the interrupt and take appropriate actions.
The ‘RETRANSMISSION MAXIMUM’ field of the CLRT register can be used to configure
the maximum number of retries before aborting the transmission.

16.6 Status hash CRC calculations
For each received frame, the Ethernet block is able to detect the destination address andsource address and from them calculate the corresponding hash CRCs. To perform thecomputation, the Ethernet block features two internal blocks: one is a controller
synchronized with the beginning and the end of each frame, the second block is the CRC
calculator.
When a new frame is detected, internal signaling notifies the controller.The controller
starts counting the incoming bytes of the frame, which correspond to the destination
address bytes. When the sixth (and last) byte is counted, the controller notifies thecalculator to store the corresponding 32 bit CRC into a first inner register. Then thecontroller repeats counting the next incoming bytes, in order to get synchronized with thesource address. When the last byte of the source address is encountered, the controller
again notifies the CRC calculator, which freezes until the next new frame. When thecalculator receives this second notification, it stores the present 32 bit CRC into a second
inner register. Then the CRCs remain frozen in their own registers until new notifications
arise.

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The destination address and source address hash CRCs being written in the
StatusHashCRC word are the nine most significant bits of the 32 bit CRCs as calculatedby the CRC calculator.

16.7 Duplex modes
The Ethernet block can operate in full duplex and half duplex mode. Half or full duplex
mode needs to be configured by the device driver software during initialization.
For a full duplex connection the FullDuplex bit of the Command register needs to be set to
1 and the FULL-DUPLEX bit of the MAC2 configuration register needs to be set to 1; forhalf duplex the same bits need to be set to 0.

16.8 IEE 802.3/Clause 31 flow control
Overview
For full duplex connections, the Ethernet block supports IEEE 802.3/clause 31 flow control
using pause frames. This type of flow control may be used in full-duplex point-to-pointconnections. Flow control allows a receiver to stall a transmitter e.g. when the receive
buffers are (almost) full. For this purpose, the receiving side sends a pause frame to thetransmitting side.
Pause frames use units of 512 bit times corresponding to 128 rx_clk/tx_clk cycles.
Receive flow control
In full-duplex mode, the Ethernet block will suspend its transmissions when the it receives
a pause frame. Rx flow control is initiated by the receiving side of the transmission. It isenabled by setting the ‘RX FLOW CONTROL’ bit in the MAC1 configuration register. If the
RX FLOW CONTROL’ bit is zero, then the Ethernet block ignores received pause control
frames. When a pause frame is received on the Rx side of the Ethernet block,transmission on the Tx side will be interrupted after the currently transmitting frame hascompleted, for an amount of time as indicated in the received pause frame. The transmit
datapath will stop transmitting data for the number of 512 bit slot times encoded in thepause-timer field of the received pause control frame.
By default the received pause control frames are not forwarded to the device driver. To
forward the receive flow control frames to the device driver, set the ‘PASS ALL RECEIVE
FRAMES’ bit in the MAC1 configuration register.
Transmit flow control
If case device drivers need to stall the receive data e.g. because software buffers are full,the Ethernet block can transmit pause control frames. Transmit flow control needs to be
initiated by the device driver software; there is no IEEE 802.3/31 flow control initiated byhardware, such as the DMA managers.
With software flow control, the device driver can detect a situation in which the process ofreceiving frames needs to be interrupted by sending out Tx pause frames. Note that due
to Ethernet delays, a few frames can still be received before the flow control takes effectand the receive stream stops.

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Transmit flow control is activated by writing 1 to the TxFlowControl bit of the Command
register. When the Ethernet block operates in full duplex mode, this will result intransmission of IEEE 802.3/31 pause frames. The flow control continues until a 0 is
written to TxFlowControl bit of the Command register.
If the MAC is operating in full-duplex mode, then setting the TxFlowControl bit of the
Command register will start a pause frame transmission. The value inserted into thepause-timer value field of transmitted pause frames is programmed via the
PauseTimer[15:0] bits in the FlowControlCounter register. When the TxFlowControl bit isdeasserted, another pause frame having a pause-timer value of 0x0000 is automaticallysent to abort flow control and resume transmission.
When flow control be in force for an extended time, a sequence of pause frames must betransmitted. This is supported with a mirror counter mechanism. To enable mirror
counting, a nonzero value is written to the MirrorCounter[15:0] bits in the
FlowControlCounter register. When the TxFlowControl bit is asserted, a pause frame istransmitted. After sending the pause frame, an internal mirror counter is initialized to zero.
The internal mirror counter starts incrementing one every 512 bit-slot times. When theinternal mirror counter reaches the MirrorCounter value, another pause frame istransmitted with pause-timer value equal to the PauseTimer field from the
FlowControlCounter register, the internal mirror counter is reset to zero and restarts
counting. The register MirrorCounter[15:0] is usually set to a smaller value than register
PauseTimer[15:0] to ensure an early expiration of the mirror counter, allowing time to senda new pause frame before the transmission on the other side can resume. By continuing
to send pause frames before the transmitting side finishes counting the pause timer, thepause can be extended as long as TxFlowControl is asserted. This continues until
TxFlowControl is deasserted when a final pause frame having a pause-timer value of
0x0000 is automatically sent to abort flow control and resume transmission. To disable themirror counter mechanism, write the value 0 to MirrorCounter field in the
FlowControlCounter register. When using the mirror counter mechanism, account for
time-of-flight delays, frame transmission time, queuing delays, crystal frequency
tolerances, and response time delays by programming the MirrorCounter conservatively,
typically about 80% of the PauseTimer value.
If the software device driver sets the MirrorCounter field of the FlowControlCounterregister to zero, the Ethernet block will only send one pause control frame. After sending
the pause frame an internal pause counter is initialized at zero; the internal pause counteris incremented by one every 512 bit-slot times. Once the internal pause counter reaches
the value of the PauseTimer register, the TxFlowControl bit in the Command register will
be reset. The software device driver can poll the TxFlowControl bit to detect when thepause completes.
The value of the internal counter in the flow control module can be read out via the
FlowControlStatus register. If the MirrorCounter is nonzero, the FlowControlStatus register
will return the value of the internal mirror counter; if the MirrorCounter is zero the
FlowControlStatus register will return the value of the internal pause counter value.
The device driver is allowed to dynamically modify the MirrorCounter register value andswitch between zero MirrorCounter and nonzero MirrorCounter modes.

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Transmit flow control is enabled via the ‘TX FLOW CONTROL’ bit in the MAC1
configuration register. If the ‘TX FLOW CONTROL’ bit is zero, then the MAC will nottransmit pause control frames, software must not initiate pause frame transmissions, andthe TxFlowControl bit in the Command register should be zero.
Transmit flow control example
Figure 11–25 illustrates the transmit flow control.

device driver PauseTimerregister MirrorCounter
TxFlowCtl
writes(R)MII
transmitclear
TxFlowCtl

normaltransmission

pause control
frame
transmission

pause control
frame
transmission

normal transimissonpause control
frame
transmission

MirrorCounter(1/515 bit
slots)(R)MII
receive0pause in effectnormal receive

50

100

150

200

250

300

normal receive

350

400

450

500

Fig 25. Transmit Flow Control

In this example, a frame is received while transmitting another frame (full duplex.) The
device driver detects that some buffer might overrun and enables the transmit flow control
by programming the PauseTimer and MirrorCounter fields of the FlowControlCounterregister, after which it enables the transmit flow control by setting the TxFlowControl bit in
the Command register.
As a response to the enabling of the flow control a pause control frame will be sent after
the currently transmitting frame has been transmitted. When the pause frametransmission completes the internal mirror counter will start counting bit slots; as soon as
the counter reaches the value in the MirrorCounter field another pause frame istransmitted. While counting the transmit datapath will continue normal transmissions.
As soon as software disables transmit flow control a zero pause control frame istransmitted to resume the receive process.

16.9 Half-Duplex mode backpressure
When in half-duplex mode, backpressure can be generated to stall receive packets bysending continuous preamble that basically jams any other transmissions on the Ethernet
medium. When the Ethernet block operates in half duplex mode, asserting
the TxFlowControl bit in the Command register will result in applying continuous preambleon the Ethernet wire, effectively blocking traffic from any other Ethernet station on thesame segment.

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In half duplex mode, when the TxFlowControl bit goes high, continuous preamble is sent
until TxFlowControl is deasserted. If the medium is idle, the Ethernet block begins
transmitting preamble, which raises carrier sense causing all other stations to defer. In theevent the transmitting of preamble causes a collision, the backpressure ‘rides through’ thecollision. The colliding station backs off and then defers to the backpressure. If during
backpressure, the user wishes to send a frame, the backpressure is interrupted, the frame
sent and then the backpressure resumed. If TxFlowControl is asserted for longer than
3.3 ms in 10 Mbps mode or 0.33 ms in 100 Mbps mode, backpressure will cease sending
preamble for several byte times to avoid the jabber limit.

16.10 Receive filtering
Features of receive filtering
The Ethernet MAC has several receive packet filtering functions that can be configured
from the software driver:• Perfect address filter: allows packets with a perfectly matching station address to be
identified and passed to the software driver.

• Hash table filter: allows imperfect filtering of packets based on the station address.
• Unicast/multicast/broadcast filtering: allows passing of all unicast, multicast, and/or
broadcast packets.

• Magic packet filter: detection of magic packets to generate a Wake-on-LAN interrupt.
The filtering functions can be logically combined to create complex filtering functions.
Furthermore, the Ethernet block can pass or reject runt packets smaller than 64 bytes; apromiscuous mode allows all packets to be passed to software.
Overview
The Ethernet block has the capability to filter out receive frames by analyzing the Ethernet
destination address in the frame. This capability greatly reduces the load on the hostsystem, because Ethernet frames that are addressed to other stations would otherwise
need to be inspected and rejected by the device driver software, using up bandwidth,
memory space, and host CPU time. Address filtering can be implemented using theperfect address filter or the (imperfect) hash filter. The latter produces a 6 bits hash code
which can be used as an index into a 64 entry programmable hash table. Figure 11–26
depicts a functional view of the receive filter.
At the top of the diagram the Ethernet receive frame enters the filters. Each filter iscontrolled by signals from control registers; each filter produces a ‘Ready’ output and a‘Match’ output. If ‘Ready’ is 0 then the Match value is ‘don’t care’; if a filter finishes filtering
then it will assert its Ready output; if the filter finds a matching frame it will assert the
Match output along with the Ready output. The results of the filters are combined by logic
functions into a single RxAbort output. If the RxAbort output is asserted, the frame does
not need to be received.
In order to reduce memory traffic, the receive datapath has a buffer of 68 bytes. The
Ethernet MAC will only start writing a frame to memory after 68 byte delays. If the RxAbort
signal is asserted during the initial 68 bytes of the frame, the frame can be discarded andremoved from the buffer and not stored to memory at all, not using up receive descriptors,
etc. If the RxAbort signal is asserted after the initial 68 bytes in a frame (probably due toreception of a Magic Packet), part of the frame is already written to memory and theUM10211_1

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Ethernet MAC will stop writing further data in the frame to memory; the FailFilter bit in thestatus word of the frame will be set to indicate that the software device driver can discard
the frame immediately.

packetAcceptUnicastEn
AcceptMulticastEn
IMPERFECTHASHFILTER
AcceptUnicastHashEn

StationAddress

AcceptMulticastHashEn

AcceptPerfectEn

PERFECTADDRESSFILTER

PAMatchPAReady

HFReady

H FMatc h

HashFilter

CRC
OK?

FMatchRxFilterWoL

RxFilterEnWoL
RxAbort

FReadyFig 26. Receive filter block diagram

Unicast, broadcast and multicast
Generic filtering based on the type of frame (unicast, multicast or broadcast) can be
programmed using the AcceptUnicastEn, AcceptMulticastEn, or AcceptBroadcastEn bitsof the RxFilterCtrl register. Setting the AcceptUnicast, AcceptMulticast, andAcceptBroadcast bits causes all frames of types unicast, multicast and broadcast,respectively, to be accepted, ignoring the Ethernet destination address in the frame. To
program promiscuous mode, i.e. to accept all frames, set all 3 bits to 1.
Perfect address match
When a frame with a unicast destination address is received, a perfect filter compares thedestination address with the 6 byte station address programmed in the station address
registers SA0, SA1, SA2. If the AcceptPerfectEn bit in the RxFilterCtrl register is set to 1,
and the address matches, the frame is accepted.
Imperfect hash filtering

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An imperfect filter is available, based on a hash mechanism. This filter applies a hashfunction to the destination address and uses the hash to access a table that indicates if
the frame should be accepted. The advantage of this type of filter is that a small table cancover any possible address. The disadvantage is that the filtering is imperfect, i.e.
sometimes frames are accepted that should have been discarded.

• Hash function:– The standard Ethernet cyclic redundancy check (CRC) function is calculated fromthe 6 byte destination address in the Ethernet frame (this CRC is calculated
anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of
the 32 bits CRC result are taken to form the hash. The 6 bit hash is used to accessthe hash table: it is used as an index in the 64 bit HashFilter register that has been
programmed with accept values. If the selected accept value is 1, the frame isaccepted.
– The device driver can initialize the hash filter table by writing to the registers
HashFilterL and HashfilterH. HashFilterL contains bits 0 through 31 of the tableand HashFilterH contains bit 32 through 63 of the table. So, hash value 0
corresponds to bit 0 of the HashfilterL register and hash value 63 corresponds to
bit 31 of the HashFilterH register.

• Multicast and unicast– The imperfect hash filter can be applied to multicast addresses, by setting the
AcceptMulticastHashEn bit in the RxFilter register to 1.
– The same imperfect hash filter that is available for multicast addresses can also be
used for unicast addresses. This is useful to be able to respond to a multitude ofunicast addresses without enabling all unicast addresses. The hash filter can beapplied to unicast addresses by setting the AcceptUnicastHashEn bit in the
RxFilter register to 1.
Enabling and disabling filtering
The filters as defined in the sections above can be bypassed by setting the PassRxFilter
bit in the Command register. When the PassRxFilter bit is set, all receive frames will bepassed to memory. In this case the device driver software has to implement all filteringfunctionality in software. Setting the PassRxFilter bit does not affect the runt frame filtering
as defined in the next section.
Runt frames
A frame with less than 64 bytes (or 68 bytes for VLAN frames) is shorter than theminimum Ethernet frame size and therefore considered erroneous; they might be collisionfragments. The receive datapath automatically filters and discards these runt frames
without writing them to memory and using a receive descriptor.
When a runt frame has a correct CRC there is a possibility that it is intended to be useful.
The device driver can receive the runt frames with correct CRC by setting the
PassRuntFrame bit of the Command register to 1.

16.11 Power management
The Ethernet block supports power management by means of clock switching. All clocks
in the Ethernet core can be switched off. If Wake-up on LAN is needed, the rx_clk should
not be switched off.
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16.12 Wake-up on LAN
Overview
The Ethernet block supports power management with remote wake-up over LAN. The
host system can be powered down, even including part of the Ethernet block itself, while
the Ethernet block continues to listen to packets on the LAN. Appropriately formed
packets can be received and recognized by the Ethernet block and used to trigger thehost system to wake up from its power-down state.
Wake-up of the system takes effect through an interrupt. When a wake-up event is
detected, the WakeupInt bit in the IntStatus register is set. The interrupt status will trigger
an interrupt if the corresponding WakeupIntEn bit in the IntEnable register is set. This
interrupt should be used by system power management logic to wake up the system.
While in a power-down state the packet that generates a Wake-up on LAN event is lost.
There are two ways in which Ethernet packets can trigger wake-up events: generic
Wake-up on LAN and Magic Packet. Magic Packet filtering uses an additional filter for
Magic Packet detection. In both cases a Wake-up on LAN event is only triggered if thetriggering packet has a valid CRC. Figure 11–26 shows the generation of the wake-up
signal.
The RxFilterWoLStatus register can be read by the software to inspect the reason for a
Wake-up event. Before going to power-down the power management software should
clear the register by writing the RxFilterWolClear register.
NOTE: when entering in power-down mode, a receive frame might be not entirely stored
into the Rx buffer. In this situation, after turning exiting power-down mode, the next
receive frame is corrupted due to the data of the previous frame being added in front of
the last received frame. Software drivers have to reset the receive datapath just after
exiting power-down mode.
The following subsections describe the two Wake-up on LAN mechanisms.
Filtering for WoL
The receive filter functionality can be used to generate Wake-up on LAN events. If the
RxFilterEnWoL bit of the RxFilterCtrl register is set, the receive filter will set the WakeupInt
bit of the IntStatus register if a frame is received that passes the filter. The interrupt will
only be generated if the CRC of the frame is correct.
Magic Packet WoL
The Ethernet block supports wake-up using Magic Packet technology (see ‘Magic Packet
technology’, Advanced Micro Devices). A Magic Packet is a specially formed packet solely
intended for wake-up purposes. This packet can be received, analyzed and recognized by
the Ethernet block and used to trigger a wake-up event.
A Magic Packet is a packet that contains in its data portion the station address repeated
16 times with no breaks or interruptions, preceded by 6 Magic Packet synchronization
bytes with the value 0xFF. Other data may be surrounding the Magic Packet pattern in thedata portion of the packet. The whole packet must be a well-formed Ethernet frame.

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The magic packet detection unit analyzes the Ethernet packets, extracts the packet
address and checks the payload for the Magic Packet pattern. The address from thepacket is used for matching the pattern (not the address in the SA0/1/2 registers.) A magic
packet only sets the wake-up interrupt status bit if the packet passes the receive filter as
illustrated in Figure 11–26: the result of the receive filter is ANDed with the magic packet
filter result to produce the result.
Magic Packet filtering is enabled by setting the MagicPacketEnWoL bit of the RxFilterCtrl
register. Note that when doing Magic Packet WoL, the RxFilterEnWoL bit in the
RxFilterCtrl register should be 0. Setting the RxFilterEnWoL bit to 1 would accept all
packets for a matching address, not just the Magic Packets i.e. WoL using Magic Packets
is more strict.
When a magic packet is detected, apart from the WakeupInt bit in the IntStatus register,
the MagicPacketWoL bit is set in the RxFilterWoLStatus register. Software can reset the
bit writing a 1 to the corresponding bit of the RxFilterWoLClear register.
Example: An example of a Magic Packet with station address 0x11 0x22 0x33 0x44 0x55
0x66 is the following (MISC indicates miscellaneous additional data bytes in the packet):<DESTINATION> <SOURCE> <MISC>
FF FF FF FF FF FF
11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66<MISC> <CRC>

16.13 Enabling and disabling receive and transmit
Enabling and disabling reception
After reset, the receive function of the Ethernet block is disabled. The receive function canbe enabled by the device driver setting the RxEnable bit in the Command register and the“RECEIVE ENABLE’ bit in the MAC1 configuration register (in that order).
The status of the receive datapath can be monitored by the device driver by reading the
RxStatus bit of the Status register. Figure 11–27 illustrates the state machine for thegeneration of the RxStatus bit.

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ACTIVE
RxStatus = 1
xxxxxxxxxxxxxxxxxx

RxEnable = 0 and not busy receiving
OR
RxProduceIndex = RxConsumeIndex - 1

RxEnable = 1

INACTIVE
RxStatus = 0

reset

Fig 27. Receive Active/Inactive state machine

After a reset, the state machine is in the INACTIVE state. As soon as the RxEnable bit isset in the Command register, the state machine transitions to the ACTIVE state. As soon
as the RxEnable bit is cleared, the state machine returns to the INACTIVE state. If thereceive datapath is busy receiving a packet while the receive datapath gets disabled, thepacket will be received completely, stored to memory along with its status before returning
to the INACTIVE state. Also if the Receive descriptor array is full, the state machine will
return to the INACTIVE state.
For the state machine in Figure 11–27, a soft reset is like a hardware reset assertion, i.e.
after a soft reset the receive datapath is inactive until the datapath is re-enabled.
Enabling and disabling transmission
After reset, the transmit function of the Ethernet block is disabled. The Tx transmit
datapath can be enabled by the device driver setting the TxEnable bit in the Command
register to 1.
The status of the transmit datapaths can be monitored by the device driver reading the
TxStatus bit of the Status register. Figure 11–28 illustrates the state machine for thegeneration of the TxStatus bit.

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ACTIVE
TxStatus = 1
xxxxxxxxxxxxxxxxxxxxxx

TxEnable = 1
AND
TxProduceIndex <> TxConsumeIndex

TxEnable = 0 and not busy transmitting
OR
TxProduceIndex = TxConsumeIndex

INACTIVE
TxStatus = 0

reset

Fig 28. Transmit Active/Inactive state machine

After reset, the state machine is in the INACTIVE state. As soon as the TxEnable bit is set
in the Command register and the Produce and Consume indices are not equal, the statemachine transitions to the ACTIVE state. As soon as the TxEnable bit is cleared and thetransmit datapath has completed all pending transmissions, including committing thetransmission status to memory, the state machine returns to the INACTIVE state. The
state machine will also return to the INACTIVE state if the Produce and Consume indicesare equal again i.e. all frames have been transmitted.
For the state machine in Figure 11–28, a soft reset is like a hardware reset assertion, i.e.
after a soft reset the transmit datapath is inactive until the datapath is re-enabled.

16.14 Transmission padding and CRC
In the case of a frame of less than 60 bytes (or 64 bytes for VLAN frames), the Ethernet
block can pad the frame to 64 or 68 bytes including a 4 bytes CRC Frame Check
Sequence (FCS). Padding is affected by the value of the ‘AUTO DETECT PAD ENABLE’(ADPEN), ‘VLAN PAD ENABLE’ (VLPEN) and ‘PAD/CRC ENABLE’ (PADEN) bits of the
MAC2 configuration register, as well as the Override and Pad bits from the transmit
descriptor Control word. CRC generation is affected by the ‘CRC ENABLE’ (CRCE) and‘DELAYED CRC’ (DCRC) bits of the MAC2 configuration register, and the Override and
CRC bits from the transmit descriptor Control word.
The effective pad enable (EPADEN) is equal to the ‘PAD/CRC ENABLE’ bit from the
MAC2 register if the Override bit in the descriptor is 0. If the Override bit is 1, then
EPADEN will be taken from the descriptor Pad bit. Likewise the effective CRC enable(ECRCE) equals CRCE if the Override bit is 0, otherwise it equal the CRC bit from thedescriptor.
If padding is required and enabled, a CRC will always be appended to the padded frames.
A CRC will only be appended to the non-padded frames if ECRCE is set.
If EPADEN is 0, the frame will not be padded and no CRC will be added unless ECRCE is
set.
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If EPADEN is 1, then small frames will be padded and a CRC will always be added to thepadded frames. In this case if ADPEN and VLPEN are both 0, then the frames will bepadded to 60 bytes and a CRC will be added creating 64 bytes frames; if VLPEN is 1, theframes will be padded to 64 bytes and a CRC will be added creating 68 bytes frames; if
ADPEN is 1, while VLPEN is 0 VLAN frames will be padded to 64 bytes, non VLAN
frames will be padded to 60 bytes, and a CRC will be added to padded frames, creating
64 or 68 bytes padded frames.
If CRC generation is enabled, CRC generation can be delayed by four bytes by setting the
DELAYED CRC bit in the MAC2 register, in order to skip proprietary header information.

16.15 Huge frames and frame length checking
The ‘HUGE FRAME ENABLE’ bit in the MAC2 configuration register can be set to 1 toenable transmission and reception of frames of any length. Huge frame transmission canbe enabled on a per frame basis by setting the Override and Huge bits in the transmit
descriptor Control word.
When enabling huge frames, the Ethernet block will not check frame lengths and reportframe length errors (RangeError and LengthError). If huge frames are enabled, thereceived byte count in the RSV register may be invalid because the frame may exceed the
maximum size; the RxSize fields from the receive status arrays will be valid.
Frame lengths are checked by comparing the length/type field of the frame to the actual
number of bytes in the frame. A LengthError is reported by setting the corresponding bit in
the receive StatusInfo word.
The MAXF register allows the device driver to specify the maximum number of bytes in aframe. The Ethernet block will compare the actual receive frame to the MAXF value andreport a RangeError in the receive StatusInfo word if the frame is larger.

16.16 Statistics counters
Generally, Ethernet applications maintain many counters that track Ethernet traffic
statistics. There are a number of standards specifying such counters, such as IEEE std
802.3 / clause 30. Other standards are RFC 2665 and RFC 2233.
The approach taken here is that by default all counters are implemented in software. With
the help of the StatusInfo field in frame statuses, many of the important statistics events
listed in the standards can be counted by software.

16.17 MAC status vectors
Transmit and receive status information as detected by the MAC are available in registers
TSV0, TSV1 and RSV so that software can poll them. These registers are normally of
limited use because the communication between driver software and the Ethernet block
takes place primarily through frame descriptors. Statistical events can be counted bysoftware in the device driver. However, for debug purposes the transmit and receive status
vectors are made visible. They are valid as long as the internal status of the MAC is validand should typically only be read when the transmit and receive processes are halted.

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16.18 Reset
The Ethernet block has a hard reset input which is connected to the chip reset, as well as
several soft resets which can be activated by setting the appropriate bit(s) in registers. Allregisters in the Ethernet block have a value of 0 after a hard reset, unless otherwise
specified.
Hard reset
After a hard reset, all registers will be set to their default value.
Soft reset
Parts of the Ethernet block can be soft reset by setting bits in the Command register andthe MAC1 configuration register.The MAC1 register has six different reset bits:• SOFT RESET: Setting this bit will put all modules in the MAC in reset, except for the
MAC registers (at addresses 0x000 to 0x0FC). The value of the soft reset after ahardware reset assertion is 1, i.e. the soft reset needs to be cleared after a hardware
reset.

• SIMULATION RESET: Resets the random number generator in the Transmit Function.
The value after a hardware reset assertion is 0.

• RESET MCS/Rx: Setting this bit will reset the MAC Control Sublayer (pause frame
logic) and the receive function in the MAC. The value after a hardware reset assertion
is 0.

• RESET Rx: Setting this bit will reset the receive function in the MAC. The value after ahardware reset assertion is 0.

• RESET MCS/Tx: Setting this bit will reset the MAC Control Sublayer (pause frame
logic) and the transmit function in the MAC. The value after a hardware reset
assertion is 0.

• RESET Tx: Setting this bit will reset the transmit function of the MAC. The value after
a hardware reset assertion is 0.
The above reset bits must be cleared by software.
The Command register has three different reset bits:• TxReset: Writing a ‘1’ to the TxReset bit will reset the transmit datapath, excluding the
MAC portions, including all (read-only) registers in the transmit datapath, as well as
the TxProduceIndex register in the host registers module. A soft reset of the transmit
datapath will abort all AHB transactions of the transmit datapath. The reset bit will becleared autonomously by the Ethernet block. A soft reset of the Tx datapath will clear
the TxStatus bit in the Status register.

• RxReset: Writing a ‘1’ to the RxReset bit will reset the receive datapath, excluding the
MAC portions, including all (read-only) registers in the receive datapath, as well as the
RxConsumeIndex register in the host registers module. A soft reset of the receive
datapath will abort all AHB transactions of the receive datapath. The reset bit will becleared autonomously by the Ethernet block. A soft reset of the Rx datapath will clear
the RxStatus bit in the Status register.

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Chapter 11: LPC2300 Ethernet• RegReset: Resets all of the datapaths and registers in the host registers module,
excluding the registers in the MAC. A soft reset of the registers will also abort all AHB
transactions of the transmit and receive datapath. The reset bit will be clearedautonomously by the Ethernet block.
To do a full soft reset of the Ethernet block, device driver software must:• Set the ‘SOFT RESET’ bit in the MAC1 register to 1.
• Set the RegReset bit in the Command register, this bit clears automatically.
• Reinitialize the MAC registers (0x000 to 0x0FC).
• Reset the ‘SOFT RESET’ bit in the MAC1 register to 0.
To reset just the transmit datapath, the device driver software has to:• Set the ‘RESET MCS/Tx’ bit in the MAC1 register to 1.
• Disable the Tx DMA managers by setting the TxEnable bits in the Command register
to 0.

• Set the TxReset bit in the Command register, this bit clears automatically.
• Reset the ‘RESET MCS/Tx’ bit in the MAC1 register to 0.
To reset just the receive datapath, the device driver software has to:• Disable the receive function by resetting the ‘RECEIVE ENABLE’ bit in the MAC1
configuration register and resetting of the RxEnable bit of the Command register.

• Set the ‘RESET MCS/Rx’ bit in the MAC1 register to 1.
• Set the RxReset bit in the Command register, this bit clears automatically.
• Reset the ‘RESET MCS/Rx’ bit in the MAC1 register to 0.
16.19 Ethernet errors
The Ethernet block generates errors for the following conditions:• A reception can cause an error: AlignmentError, RangeError, LengthError,
SymbolError, CRCError, NoDescriptor, or Overrun. These are reported back in thereceive StatusInfo and in the interrupt status register (IntStatus).

• A transmission can cause an error: LateCollision, ExcessiveCollision,
ExcessiveDefer, NoDescriptor, or Underrun. These are reported back in thetransmission StatusInfo and in the interrupt status register (IntStatus).

17. AHB bandwidth
The Ethernet block is connected to an AHB bus which must carry all of the data andcontrol information associated with all Ethernet traffic in addition to the CPU accesses
required to operate the Ethernet block and deal with message contents.

17.1 DMA access
Assumptions

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By making some assumptions, the bandwidth needed for each type of AHB transfer canbe calculated and added in order to find the overall bandwidth requirement.
The flexibility of the descriptors used in the Ethernet block allows the possibility of defining
memory buffers in a range of sizes. In order to analyze bus bandwidth requirements,
some assumptions must be made about these buffers. The "worst case" is not addressedsince that would involve all descriptors pointing to single byte buffers, with most of thememory occupied in holding descriptors and very little data. It can easily be shown that
the AHB cannot handle the huge amount of bus traffic that would be caused by such a
degenerate (and illogical) case.
For this analysis, an Ethernet packet is assumed to consist of a 64 byte frame.
Continuous traffic is assumed on both the transmit and receive channels.
This analysis does not reflect the flow of Ethernet traffic over time, which would include
inter-packet gaps in both the transmit and receive channels that reduce the bandwidth
requirements over a larger time frame.
Types of DMA access and their bandwidth requirements
The interface to an external Ethernet PHY is via either MII or RMII. An MII operates at
25 MHz, transferring a byte in 2 clock cycles. An RMII operates at 50 MHz , transferring abyte in 4 clock cycles. The data transfer rate is the same in both cases: 12.5 Mbps.
The Ethernet block initiates DMA accesses for the following cases:• Tx descriptor read:– Transmit descriptors occupy 2 words (8 bytes) of memory and are read once foreach use of a descriptor.
– Two word read happens once every 64 bytes (16 words) of transmitted data.
– This gives 1/8th of the data rate, which = 1.5625 Mbps.

• Rx descriptor read:– Receive descriptors occupy 2 words (8 bytes) of memory and are read once foreach use of a descriptor.
– Two word read happens once every 64 bytes (16 words) of received data.
– This gives 1/8th of the data rate, which = 1.5625 Mbps.

• Tx status write:– Transmit status occupies 1 word (4 bytes) of memory and is written once for eachuse of a descriptor.
– One word write happens once every 64 bytes (16 words) of transmitted data.
– This gives 1/16th of the data rate, which = 0.7813 Mbps.

• Rx status write:– Receive status occupies 2 words (8 bytes) of memory and is written once for eachuse of a descriptor.
– Two word write happens once every 64 bytes (16 words) of received data.
– This gives 1/8 of the data rate, which = 1.5625 Mbps.

• Tx data read:– Data transmitted in an Ethernet frame, the size is variable.
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Chapter 11: LPC2300 Ethernet– Basic Ethernet rate = 12.5 Mbps.

• Rx data write:– Data to be received in an Ethernet frame, the size is variable.
– Basic Ethernet rate = 12.5 Mbps.
This gives a total rate of 30.5 Mbps for the traffic generated by the Ethernet DMA function.

17.2 Types of CPU access• Accesses that mirror each of the DMA access types:– All or part of status values must be read, and all or part of descriptors need to be
written after each use, transmitted data must be stored in the memory by the CPU,and eventually received data must be retrieved from the memory by the CPU.
– This gives roughly the same or slightly lower rate as the combined DMA functions,which = 30.5 Mbps.

• Access to registers in the Ethernet block:– The CPU must read the RxProduceIndex, TxConsumeIndex, and IntStatus
registers, and both read and write the RxConsumeIndex and TxProduceIndex
registers.
– 7 word read/writes once every 64 bytes (16 words) of transmitted and received
data.
– This gives 7/16 of the data rate, which = 5.4688 Mbps.
This gives a total rate of 36 Mbps for the traffic generated by the Ethernet DMA function.

17.3 Overall bandwidth
Overall traffic on the AHB is the sum of DMA access rates and CPU access rates, whichcomes to approximately 66.5 MB/s.
The peak bandwidth requirement can be somewhat higher due to the use of small
memory buffers, in order to hold often used addresses (e.g. the station address) for
example. Driver software can determine how to build frames in an efficient manner that
does not overutilize the AHB.
The bandwidth available on the AHB bus depends on the system clock frequency. As an
example, assume that the system clock is set at 60 MHz. All or nearly all of bus accesses
related to the Ethernet will be word transfers. The raw AHB bandwidth can beapproximated as 4 bytes per two system clocks, which equals 2 times the system clock
rate. With a 60 MHz system clock, the bandwidth is 120 MB/s, giving about 55% utilization
for Ethernet traffic during simultaneous transmit and receive operations.

18. CRC calculation
The calculation is used for several purposes:• Generation the FCS at the end of the Ethernet frame.
• Generation of the hash table index for the hash table filtering.
• Generation of the destination and source address hash CRCs.
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The C pseudocode function below calculates the CRC on a frame taking the frame(without FCS) and the number of bytes in the frame as arguments. The function returns
the CRC as a 32 bit integer.
int crc_calc(char frame_no_fcs[], int frame_len) {int i;// iterator
int j;// another iterator
char byte; // current byte
int crc; // CRC result
int q0, q1, q2, q3; // temporary variables
crc = 0xFFFFFFFF;
for (i = 0; i < frame_len; i++) {byte = *frame_no_fcs++;for (j = 0; j < 2; j++) {if (((crc >> 28) ^ (byte >> 3)) & 0x00000001) {q3 = 0x04C11DB7;} else {q3 = 0x00000000;}
if (((crc >> 29) ^ (byte >> 2)) & 0x00000001) {q2 = 0x09823B6E;} else {q2 = 0x00000000;}
if (((crc >> 30) ^ (byte >> 1)) & 0x00000001) {q1 = 0x130476DC;} else {q1 = 0x00000000;}
if (((crc >> 31) ^ (byte >> 0)) & 0x00000001) {q0 = 0x2608EDB8;} else {q0 = 0x00000000;}
crc = (crc << 4) ^ q3 ^ q2 ^ q1 ^ q0;
byte >>= 4;}}
return crc;}
For FCS calculation, this function is passed a pointer to the first byte of the frame and thelength of the frame without the FCS.
For hash filtering, this function is passed a pointer to the destination address part of theframe and the CRC is only calculated on the 6 address bytes. The hash filter uses bits
[28:23] for indexing the 64 bits { HashFilterH, HashFilterL } vector. If the corresponding bit
is set the packet is passed, otherwise it is rejected by the hash filter.

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For obtaining the destination and source address hash CRCs, this function calculates firstboth the 32 bit CRCs, then the nine most significant bits from each 32 bit CRC are
extracted, concatenated, and written in every StatusHashCRC word of every fragment
status.

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UM10211
Chapter 12: CAN controllers CAN1/2
Rev. 01 — 6 July 2007

User manual

1. CAN controllers
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The CAN Controller is designed to provide a full
implementation of the CAN-Protocol according to the CAN Specification Version 2.0B.
Microcontrollers with this on-chip CAN controller are used to build powerful local networks
by supporting distributed real-time control with a very high level of security. The
applications are automotive, industrial environments, and high speed networks as well as
low cost multiplex wiring. The result is a strongly reduced wiring harness and enhanced
diagnostic and supervisory capabilities.
The CAN block is intended to support multiple CAN buses simultaneously, allowing thedevice to be used as a gateway, switch, or router among a number of CAN buses invarious applications.
The CAN module consists of two elements: the controller and the Acceptance Filter. Allregisters and the RAM are accessed as 32 bit words.

2. Features
2.1 General CAN features• Compatible with CAN specification 2.0B, ISO 11898-1.
• Multi-master architecture with non destructive bit-wise arbitration.
• Bus access priority determined by the message identifier (11-bit or 29-bit).
• Guaranteed latency time for high priority messages.
• Programmable transfer rate (up to 1 Mbit/s).
• Multicast and broadcast message facility.
• Data length from 0 up to 8 bytes.
• Powerful error handling capability.
• Non-return-to-zero (NRZ) coding/decoding with bit stuffing.
2.2 CAN controller features• 2 CAN controllers and buses.
• Supports 11-bit identifier as well as 29-bit identifier.
• Double Receive Buffer and Triple Transmit Buffer.
• Programmable Error Warning Limit and Error Counters with read/write access.
• Arbitration Lost Capture and Error Code Capture with detailed bit position.
• Single Shot Transmission (no re-transmission).
• Listen Only Mode (no acknowledge, no active error flags).
• Reception of "own" messages (Self Reception Request).
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2.3 Acceptance filter features• Fast hardware implemented search algorithm supporting a large number of CAN
identifiers.

• Global Acceptance Filter recognizes 11 and 29 bit Rx Identifiers for all CAN buses.
• Allows definition of explicit and groups for 11-bit and 29-bit CAN identifiers.
• Acceptance Filter can provide FullCAN-style automatic reception for selectedStandard Identifiers.

3. Pin description
Table 190. CAN Pin descriptions
Pin Name

Type

Description

RD2-1

InputsSerial Inputs. From CAN transceivers.

TD2-1

Outputs

Serial Outputs. To CAN transceivers.

4. CAN controller architecture
The CAN Controller is a complete serial interface with both Transmit and Receive Buffers
but without Acceptance Filter. CAN Identifier filtering is done for all CAN channels in a
separate block (Acceptance Filter). Except for message buffering and acceptance filtering
the functionality is similar to the PeliCAN concept.
The CAN Controller Block includes interfaces to the following blocks:• APB Interface• Acceptance Filter• Vectored Interrupt Controller (VIC)• CAN Transceiver• Common Status Registers

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Chapter 12: LPC2300 CAN1, 2

INTERFACEMANAGEMENTLOGICAPB BUSCAN CORE
BLOCK
TX
ERROR
MANAGEMENT
LOGIC

VIC
TRANSMITBUFFERS 1,2
AND 3

COMMONSTATUSREGISTERACCEPTANCEFILTERRX

CAN
TRANSCEIVER

BIT
TIMINGLOGIC

BIT
STREAM
PROCESSOR

RECEIVE
BUFFERS 1
AND 2

Fig 29. CAN controller block diagram

4.1 APB interface block (AIB)The APB Interface Block provides access to all CAN Controller registers.

4.2 Interface management logic (IML)The Interface Management Logic interprets commands from the CPU, controls internal
addressing of the CAN Registers and provides interrupts and status information to theCPU.

4.3 Transmit Buffers (TXB)
The TXB represents a Triple Transmit Buffer, which is the interface between the Interface
Management Logic (IML) and the Bit Stream Processor (BSP). Each Transmit Buffer isable to store a complete message which can be transmitted over the CAN network. Thisbuffer is written by the CPU and read out by the BSP.

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31

24 23

TX

Frame info

16 15

unusedTX DLC87

unused0 . . . 00

TX Priority

TFS

ID.28 ... ID.18

TID

TX Data 4

TX Data 3

TX Data 2

TX Data 1

TDA

TX Data 8

TX Data 7

TX Data 6

TX Data 5

TDB

Descriptor
Field

Data Field

Standard Frame Format (11-bit Identifier)

31

24 23

TX

Frame info

000

ID.28

16 15

unusedTX DLC87

unused0

TX Priority

TFS

ID.00

TID

...

TX Data 4

TX Data 3

TX Data 2

TX Data 1

TDA

TX Data 8

TX Data 7

TX Data 6

TX Data 5

TDB

Descriptor
Field

Data Field

Extended Frame Format (29-bit Identifier)Fig 30. Transmit buffer layout for standard and extended frame format configurations

4.4 Receive Buffer (RXB)The Receive Buffer (RXB) represents a CPU accessible Double Receive Buffer. It is
located between the CAN Controller Core Block and APB Interface Block and stores allreceived messages from the CAN Bus line. With the help of this Double Receive Bufferconcept the CPU is able to process one message while another message is being
received.
The global layout of the Receive Buffer is very similar to the Transmit Buffer describedearlier. Identifier, Frame Format, Remote Transmission Request bit and Data Length
Code have the same meaning as described for the Transmit Buffer. In addition, theReceive Buffer includes an ID Index field (see Section 12–6.9.1 “ID index field”).
The received Data Length Code represents the real transmitted Data Length Code, which
may be greater than 8 depending on transmitting CAN node. Nevertheless, the maximum
number of received data bytes is 8. This should be taken into account by reading amessage from the Receive Buffer. If there is not enough space for a new message within
the Receive Buffer, the CAN Controller generates a Data Overrun condition when thismessage becomes valid and the acceptance test was positive. A message that is partly
written into the Receive Buffer (when the Data Overrun situation occurs) is deleted. Thissituation is signalled to the CPU via the Status Register and the Data Overrun Interrupt, if
enabled.

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31

24 23

RX

Frame info

16 15

unusedRX DLC

10 9 8 7

unusedunused0

ID Index

RFS

ID.28 ... ID.18

RID

RX Data 4

RX Data 3

RX Data 2

RX Data 1

RDA

RX Data 8

RX Data 7

RX Data 6

RX Data 5

RDB

Descriptor
Field

Data Field

BPM=bypass
messageStandard Frame Format (11-bit Identifier)

31

24 23

RX

Frame info

unused

ID.28

16 15

unusedRX DLC

10 9 8 7

unused0

ID Index

...

RFS

ID.00

RID

RX Data 4

RX Data 3

RX Data 2

RX Data 1

RDA

RX Data 8

RX Data 7

RX Data 6

RX Data 5

RDB

Descriptor
Field

Data Field

Extended Frame Format (29-bit Identifier)Fig 31. Receive buffer layout for standard and extended frame format configurations

4.5 Error Management Logic (EML)The EML is responsible for the error confinement. It gets error announcements from the
BSP and then informs the BSP and IML about error statistics.

4.6 Bit Timing Logic (BTL)
The Bit Timing Logic monitors the serial CAN Bus line and handles the Bus line related bit
timing. It synchronizes to the bit stream on the CAN Bus on a "recessive" to "dominant"Bus line transition at the beginning of a message (hard synchronization) andre-synchronizes on further transitions during the reception of a message (softsynchronization). The BTL also provides programmable time segments to compensate forthe propagation delay times and phase shifts (e.g. due to oscillator drifts) and to define thesample point and the number of samples to be taken within a bit time.

4.7 Bit Stream Processor (BSP)The Bit Stream Processor is a sequencer, controlling the data stream between theTransmit Buffer, Receive Buffers and the CAN Bus. It also performs the error detection,
arbitration, stuffing and error handling on the CAN Bus.

4.8 CAN controller self-tests
The CAN controller of the LPC2000 family supports two different options for self-tests:• Global Self-Test (setting the self reception request bit in normal Operating Mode)• Local Self-Test (setting the self reception request bit in Self Test Mode)

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Both self-tests are using the ‘Self Reception’ feature of the CAN Controller. With the Self
Reception Request, the transmitted message is also received and stored in the receive
buffer. Therefore the acceptance filter has to be configured accordingly. As soon as the
CAN message is transmitted, a transmit and a receive interrupt are generated, if enabled.
Global self test
A Global Self-Test can for example be used to verify the chosen configuration of the CAN
Controller in a given CAN system. As shown in Figure 12–32, at least one other CAN
node, which is acknowledging each CAN message has to be connected to the CAN bus.

TX
TXBuffer
BufferTX Buffer
LPC24xxCAN BusTransceiverack
RX BufferFig 32. Global Self-Test (high-speed CAN Bus example)

Initiating a Global Self-Test is similar to a normal CAN transmission. In this case thetransmission of a CAN message(s) is initiated by setting Self Reception Request bit(SRR) in conjunction with the selected Message Buffer bits (STB3, STB2, STB1) in the
CAN Controller Command register (CANCMR).
Local self test
The Local Self-Test perfectly fits for single node tests. In this case an acknowledge fromother nodes is not needed. As shown in the Figure below, a CAN transceiver with anappropriate CAN bus termination has to be connected to the LPC. The CAN Controller
has to be put into the 'Self Test Mode' by setting the STM bit in the CAN Controller Moderegister (CANMOD). Hint: Setting the Self Test Mode bit (STM) is possible only when the
CAN Controller is in Reset Mode.

TX
BufferTX
TXBuffer
Buffer
LPC24xx

Transceiver

RX BufferFig 33. Local Self-Test (high-speed CAN Bus example)

A message transmission is initiated by setting Self Reception Request bit (SRR) in
conjunction with the selected Message Buffer(s) (STB3, STB2, STB1).

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5. Memory map of the CAN block
The CAN Controllers and Acceptance Filter occupy a number of APB slots, as follows:
Table 191. Memory Map of the CAN Block
Address Range

Used for0xE003 8000 - 0xE003 87FF

Acceptance Filter RAM.

0xE003 C000 - 0xE003 C017

Acceptance Filter Registers.

0xE004 0000 - 0xE004 000B

Central CAN Registers.

0xE004 4000 - 0xE004 405F

CAN Controller 1 Registers.

0xE004 8000 - 0xE004 805F

CAN Controller 2 Registers.

6. CAN controller registers
CAN block implements the registers shown in Table 12–192 and Table 12–193. Moredetailed descriptions follow.
Table 192. CAN acceptance filter and central CAN registers
Name

Description

Access Reset Value

Address

AFMR

Acceptance Filter Register

R/W

1

0xE003 C000

SFF_saStandard Frame Individual Start Address Register

R/W

0

0xE003 C004

SFF_GRP_sa Standard Frame Group Start Address Register

R/W

0

0xE003 C008

EFF_saR/W

0

0xE003 C00CEFF_GRP_sa Extended Frame Group Start Address Register

Extended Frame Start Address Register

R/W

0

0xE003 C010

ENDofTable

End of AF Tables register

R/W

0

0xE003 C014

LUTerrAd

LUT Error Address registerRO

0

0xE003 C018
0xE003 C01C

LUTerr

LUT Error RegisterRO

0

CANTxSRCAN Central Transmit Status RegisterRO

0x0003 0300 0xE004 0000

CANRxSRCAN Central Receive Status RegisterRO

0

0xE004 0004

CANMSRCAN Central Miscellaneous RegisterRO

0

0xE004 0008

Table 193. CAN1 and CAN2 controller register map
Generic Description
Name

Access CAN1 Register
Address & Name

CAN2 Register
Address & Name

MOD

Controls the operating mode of the CAN
Controller.

R/W

CAN1MOD - 0xE004 4000

CAN2MOD - 0xE004 8000

CMR

Command bits that affect the state of the
CAN Controller

WO

CAN1CMR - 0xE004 4004

CAN2CMR - 0xE004 8004

GSR

Global Controller Status and Error Counters RO[1]CAN1GSR - 0xE004 4008

CAN2GSR - 0xE004 8008

ICR

Interrupt status, Arbitration Lost Capture,
Error Code CaptureRO

CAN1ICR - 0xE004 400C

CAN2ICR - 0xE004 800C

IER

Interrupt Enable

R/W

CAN1IER - 0xE004 4010

CAN2IER - 0xE004 8010

Bus Timing

R/W[2]CAN1BTR - 0xE004 4014

CAN2BTR - 0xE004 8014

EWL

Error Warning Limit

R/W[2]CAN1EWL - 0xE004 4018

CAN2EWL - 0xE004 8018

SR

Status RegisterRO

CAN1SR - 0xE004 401C

CAN2SR - 0xE004 801C

Receive frame status

R/W[2]

CAN1RFS - 0xE004 4020

CAN2RFS - 0xE004 8020

BTR

RFS
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Table 193. CAN1 and CAN2 controller register map
Generic Description
Name

Access CAN1 Register
Address & Name

CAN2 Register
Address & Name

RID

Received Identifier

R/W[2]

CAN1RID - 0xE004 4024

CAN2RID - 0xE004 8024

RDA

Received data bytes 1-4

R/W[2]

CAN1RDA - 0xE004 4028

CAN2RDA - 0xE004 8028

RDB

Received data bytes 5-8

R/W[2]

CAN1RDB - 0xE004 402C

CAN2RDB - 0xE004 802C

TFI1

Transmit frame info (Tx Buffer 1)

R/W

CAN1TFI1 - 0xE004 4030

CAN2TFI1 - 0xE004 8030

TID1

Transmit Identifier (Tx Buffer 1)

R/W

CAN1TID1 - 0xE004 4034

CAN2TID1 - 0xE004 8034

TDA1

Transmit data bytes 1-4 (Tx Buffer 1)

R/W

CAN1TDA1 - 0xE004 4038 CAN2TDA1 - 0xE004 8038

TDB1

Transmit data bytes 5-8 (Tx Buffer 1)

R/W

CAN1TDB1- 0xE004 403C
CAN2TDB1- 0xE004 803C

CAN1TDB1 - 0xE004 403C
CAN2TDB1 - 0xE004 803C

TFI2

Transmit frame info (Tx Buffer 2)

R/W

CAN1TFI2 - 0xE004 4040
CAN2TFI2 - 0xE004 8040

CAN1TFI2 - 0xE004 4040
CAN2TFI2 - 0xE004 8040

TID2

Transmit Identifier (Tx Buffer 2)

R/W

CAN1TID2 - 0xE004 4044
CAN2TID2 - 0xE004 8044

CAN1TID2 - 0xE004 4044
CAN2TID2 - 0xE004 8044

TDA2

Transmit data bytes 1-4 (Tx Buffer 2)

R/W

CAN1TDA2 - 0xE004 4048 CAN1TDA2 - 0xE004 4048
CAN2TDA2 - 0xE004 8048 CAN2TDA2 - 0xE004 8048

TDB2

Transmit data bytes 5-8 (Tx Buffer 2)

R/W

CAN1TDB2 - 0xE004 404C CAN1TDB2 - 0xE004 404C
CAN2TDB2 - 0xE004 804C CAN2TDB2 - 0xE004 804C

TFI3

Transmit frame info (Tx Buffer 3)

R/W

CAN1TFI3 - 0xE004 4050
CAN2TFI3 - 0xE004 8050

CAN1TFI3 - 0xE004 4050
CAN2TFI3 - 0xE004 8050

TID3

Transmit Identifier (Tx Buffer 3)

R/W

CAN1TID3 - 0xE004 4054
CAN2TID3 - 0xE004 8054

CAN1TID3 - 0xE004 4054
CAN2TID3 - 0xE004 8054

TDA3

Transmit data bytes 1-4 (Tx Buffer 3)

R/W

CAN1TDA3 - 0xE004 4058 CAN1TDA3 - 0xE004 4058
CAN2TDA3 - 0xE004 8058 CAN2TDA3 - 0xE004 8058

TDB3

Transmit data bytes 5-8 (Tx Buffer 3)

R/W

CAN1TDB3 - 0xE004 405C CAN1TDB3 - 0xE004 405C
CAN2TDB3 - 0xE004 805C CAN2TDB3 - 0xE004 805C

[1]

The error counters can only be written when RM in CANMOD is 1.

[2]

These registers can only be written when RM in CANMOD is 1.

The internal registers of each CAN Controller appear to the CPU as on-chip memory
mapped peripheral registers. Because the CAN Controller can operate in different modes(Operating/Reset, see also Section 12–6.1 “Mode Register (CAN1MOD - 0xE004 4000,
CAN2MOD - 0xE004 8000)”), one has to distinguish between different internal address
definitions. Note that write access to some registers is only allowed in Reset Mode.
Table 194. CAN1 and CAN2 controller register map
Generic
Name

Operating Mode

Reset Mode

Read

Write

Read

Write

MOD

Mode

Mode

Mode

Mode

CMR

0x00

Command

0x00

Command

GSR

Global Status and Error
Counters-

Global Status and Error
Counters

Error Counters only

ICR

Interrupt and Capture-Interrupt and Capture-

IER

Interrupt Enable

Interrupt Enable

Interrupt Enable

Interrupt Enable

BTR

Bus Timing-

Bus Timing

Bus Timing

EWL

Error Warning Limit-

Error Warning Limit

Error Warning Limit

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Table 194. CAN1 and CAN2 controller register map
Generic
Name

Operating Mode

Reset Mode

Read

Write

Read

Write

SR

Status-Status-RFS

Rx Info and Index-

Rx Info and Index

Rx Info and Index

RID

Rx Identifier-

Rx Identifier

Rx Identifier

RDA

Rx Data-Rx DataRx Data

RDB

Rx Info and Index-

Rx Info and Index

Rx Info and Index

TFI1

Tx Info1

Tx Info

Tx Info

Tx Info

TID1

Tx Identifier

Tx Identifier

Tx Identifier

Tx Identifier

TDA1

Tx Data

Tx Data

Tx Data

Tx Data

TDB1

Tx Data

Tx Data

Tx Data

Tx DataIn the following register tables, the column “Reset Value” shows how a hardware reset
affects each bit or field, while the column “RM Set” indicates how each bit or field isaffected if software sets the RM bit, or RM is set because of a Bus-Off condition. Note thatwhile hardware reset sets RM, in this case the setting noted in the “Reset Value” column
prevails over that shown in the “RM Set” column, in the few bits where they differ. In bothcolumns, X indicates the bit or field is unchanged.

6.1 Mode Register (CAN1MOD - 0xE004 4000, CAN2MOD - 0xE004 8000)
The contents of the Mode Register are used to change the behavior of the CAN
Controller. Bits may be set or reset by the CPU that uses the Mode Register as aread/write memory. Reserved Bits are read as 0 and should be written as 0.
Table 195. Mode register (CAN1MOD - address 0xE004 4000, CAN2MOD - address 0xE004 8000) bit description
Bit Symbol Value01

RM[1][6]2Reset RM
Value Set

Reset Mode.

1

1

0

x

0

x

0(normal)

The CAN Controller is in the Operating Mode, and certain registers can not be
written.

1(reset)CAN operation is disabled, writable registers can be written and the current
transmission/reception of a message is aborted.

LOM[3][2][6]Function

Listen Only Mode.
0(normal)

The CAN controller acknowledges a successfully received message on the
CAN bus. The error counters are stopped at the current value.

1(listen only)

The controller gives no acknowledgment, even if a message is successfullyreceived. Messages cannot be sent, and the controller operates in “error
passive” mode. This mode is intended for software bit rate detection and “hotplugging”.

STM[3][6]Self Test Mode.
0(normal)A transmitted message must be acknowledged to be considered successful.

1(self test)

The controller will consider a Tx message successful even if there is noacknowledgment received.
In this mode a full node test is possible without any other active node on the bus
using the SRR bit in CANxCMR.

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Table 195. Mode register (CAN1MOD - address 0xE004 4000, CAN2MOD - address 0xE004 8000) bit description
Bit Symbol Value
3

4

5

TPM[4]

Function

Reset RM
Value Set

Transmit Priority Mode.

0

x

0

0

0

x

Reserved, user software should not write ones to reserved bits.

00

Test Mode.

0x0(CAN ID)

The transmit priority for 3 Transmit Buffers depends on the CAN Identifier.

1(local prio)

The transmit priority for 3 Transmit Buffers depends on the contents of the Tx
Priority register within the Transmit Buffer.

SM[5]Sleep Mode.
0(wake-up)

Normal operation.

1(sleep)

The CAN controller enters Sleep Mode if no CAN interrupt is pending and there
is no bus activity. See the Sleep Mode description Section 12–7.2 on page 235.

RPM

Receive Polarity Mode.
0(low active)

RD input is active Low (dominant bit = 0).

1(high active) RD input is active High (dominant bit = 1) -- reverse polarity.
6

-

7

TM

[1]

0(disabled)

Normal operation.

1(enabled)

The TD pin will reflect the bit, detected on RD pin, with the next positive edge ofthe system clock.

During a Hardware reset or when the Bus Status bit is set '1' (Bus-Off), the Reset Mode bit is set '1' (present). After the Reset Mode bit
is set '0' the CAN Controller will wait for:- one occurrence of Bus-Free signal (11 recessive bits), if the preceding reset has been caused by a Hardware reset or a CPU-initiatedreset.
- 128 occurrences of Bus-Free, if the preceding reset has been caused by a CAN Controller initiated Bus-Off, before re-entering the
Bus-On mode.

[2]

This mode of operation forces the CAN Controller to be error passive. Message Transmission is not possible. The Listen Only Mode canbe used e.g. for software driven bit rate detection and "hot plugging".

[3]

A write access to the bits MOD.1 and MOD.2 is possible only if the Reset Mode is entered previously.

[4]

Transmit Priority Mode is explained in more detail in Section 12–4.3 “Transmit Buffers (TXB)”.

[5]The CAN Controller will enter Sleep Mode, if the Sleep Mode bit is set '1' (sleep), there is no bus activity, and none of the CAN interrupts
is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. The CAN
Controller will wake up if SM is set LOW (wake-up) or there is bus activity. On wake-up, a Wake-up Interrupt is generated. A sleeping
CAN Controller which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits
(Bus-Free sequence). Note that setting of SM is not possible in Reset Mode. After clearing of Reset Mode, setting of SM is possible only
when Bus-Free is detected again.

[6]

The LOM and STM bits can only be written if the RM bit is 1 prior to the write operation.

6.2 Command Register (CAN1CMR - 0xE004 x004, CAN2CMR 0xE004 8004)
Writing to this write-only register initiates an action within the transfer layer of the CAN
Controller. Bits not listed should be written as 0. Reading this register yields zeroes.
At least one internal clock cycle is needed for processing between two commands.

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Table 196. Command Register (CAN1CMR - address 0xE004 4004, CAN2CMR - address 0xE004 8004) bit description
Bit

Symbol Value

0[1][2] TR

5

0

0

0

0

0

0

0

0

0

0

0

0

0

0 (no action)

Do not abort the transmission.

1 (present)

if not already in progress, a pending Transmission Request for theselected Transmit Buffer is cancelled.
Release Receive Buffer.

0 (no action)

Do not release the receive buffer.

1 (released)

The information in the Receive Buffer (consisting of CANxRFS,
CANxRID, and if applicable the CANxRDA and CANxRDB registers)
is released, and becomes eligible for replacement by the next
received frame. If the next received frame is not available, writing
this command clears the RBS bit in the Status Register(s).

0 (no action)

Do not clear the data overrun bit.

1 (clear)

The Data Overrun bit in Status Register(s) is cleared.

Clear Data Overrun.

SRR

Self Reception Request.
0 (absent)

No self reception request.

1 (present)

The message, previously written to the CANxTFS, CANxTID, andoptionally the CANxTDA and CANxTDB registers, is queued fortransmission from the selected Transmit Buffer and received
simultaneously. This differs from the TR bit above in that the receiver
is not disabled during the transmission, so that it receives themessage if its Identifier is recognized by the Acceptance Filter.
Select Tx Buffer 1.

0 (not selected)

Tx Buffer 1 is not selected for transmission.

1 (selected)

Tx Buffer 1 is selected for transmission.
Select Tx Buffer 2.

0 (not selected)
1 (selected)[1]0Abort Transmission.

STB2

7

0

The message, previously written to the CANxTFI, CANxTID, andoptionally the CANxTDA and CANxTDB registers, is queued fortransmission from the selected Transmit Buffer. If at two or all threeof STB1, STB2 and STB3 bits are selected when TR=1 is written,
Transmit Buffer will be selected based on the chosen priority
scheme (for details see Section 12–4.3 “Transmit Buffers (TXB)”)

STB1

6

0

1 (present)CDO

4[1][6]

Transmission Request.
No transmission request.

RRB

3[5]

Reset RM
Value Set

0 (absent)

1[1][3] AT

2[4]Function

STB3

Tx Buffer 2 is not selected for transmission.
Tx Buffer 2 is selected for transmission.
Select Tx Buffer 3.

0 (not selected)

Tx Buffer 3 is not selected for transmission.

1 (selected)

Tx Buffer 3 is selected for transmission.

- Setting the command bits TR and AT simultaneously results in transmitting a message once. No re-transmission will be performed incase of an error or arbitration lost (single shot transmission).
- Setting the command bits SRR and TR simultaneously results in sending the transmit message once using the self-reception feature.
No re-transmission will be performed in case of an error or arbitration lost.
- Setting the command bits TR, AT and SRR simultaneously results in transmitting a message once as described for TR and AT. The
moment the Transmit Status bit is set within the Status Register, the internal Transmission Request Bit is cleared automatically.
- Setting TR and SRR simultaneously will ignore the set SRR bit.

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If the Transmission Request or the Self-Reception Request bit was set '1' in a previous command, it cannot be cancelled by resetting thebits. The requested transmission may only be cancelled by setting the Abort Transmission bit.

[3]

The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission, e.g. to transmit amore urgent message before. A transmission already in progress is not stopped. In order to see if the original message has been eithertransmitted successfully or aborted, the Transmission Complete Status bit should be checked. This should be done after the Transmit
Buffer Status bit has been set to '1' or a Transmit Interrupt has been generated.

[4]

After reading the contents of the Receive Buffer, the CPU can release this memory space by setting the Release Receive Buffer bit '1'.
This may result in another message becoming immediately available. If there is no other message available, the Receive Interrupt bit isreset. If the RRB command is given, it will take at least 2 internal clock cycles before a new interrupt is generated.

[5]This command bit is used to clear the Data Overrun condition signalled by the Data Overrun Status bit. As long as the Data Overrun
Status bit is set no further Data Overrun Interrupt is generated.

[6]

Upon Self Reception Request, a message is transmitted and simultaneously received if the Acceptance Filter is set to the corresponding
identifier. A receive and a transmit interrupt will indicate correct self reception (see also Self Test Mode in Section 12–6.1 “ModeRegister (CAN1MOD - 0xE004 4000, CAN2MOD - 0xE004 8000)”).

6.3 Global Status Register (CAN1GSR - 0xE004 x008, CAN2GSR 0xE004 8008)
The content of the Global Status Register reflects the status of the CAN Controller. This
register is read-only, except that the Error Counters can be written when the RM bit in the
CANMOD register is 1. Bits not listed read as 0 and should be written as 0.
Table 197. Global Status Register (CAN1GSR - address 0xE004 4008, CAN2GSR - address 0xE004 8008) bit
description
Bit

Symbol Value

Function

Reset RM
Value Set0

RBS[1]

Receive Buffer Status.

0

0

0

0

1

1

1

x

1

2

3

0 (empty)

No message is available.

1 (full)

At least one complete message is received by the Double Receive Buffer
and available in the CANxRFS, CANxRID, and if applicable the CANxRDA
and CANxRDB registers. This bit is cleared by the Release Receive Buffer
command in CANxCMR, if no subsequent received message is available.

DOS[2]

Data Overrun Status.
0 (absent)

No data overrun has occurred since the last Clear Data Overrun command
was given/written to CANxCMR (or since Reset).

1 (overrun)

A message was lost because the preceding message to this CAN controller
was not read and released quickly enough (there was not enough space fora new message in the Double Receive Buffer).

TBS

Transmit Buffer Status.
0 (locked)

At least one of the Transmit Buffers is not available for the CPU, i.e. at least
one previously queued message for this CAN controller has not yet beensent, and therefore software should not write to the CANxTFI, CANxTID,
CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s).

1 (released)

All three Transmit Buffers are available for the CPU. No transmit message ispending for this CAN controller (in any of the 3 Tx buffers), and software may
write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.

TCS[3]

Transmit Complete Status.
0 (incomplete) At least one requested transmission has not been successfully completedyet.
1 (complete)

All requested transmission(s) has (have) been successfully completed.

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Table 197. Global Status Register (CAN1GSR - address 0xE004 4008, CAN2GSR - address 0xE004 8008) bit
description
Bit

Symbol Value

Function

Reset RM
Value Set

4

RS[4]

Receive Status.

1

0

1

0

0

0

0

0

0 (idle)The CAN controller is idle.

1 (receive)

The CAN controller is receiving a message.

TS[4]

5

Transmit Status.
0 (idle)The CAN controller is idle.

1 (transmit)

The CAN controller is sending a message.

ES[5]

6

Error Status.
0 (ok)

Both error counters are below the Error Warning Limit.

1 (error)

One or both of the Transmit and Receive Error Counters has reached thelimit set in the Error Warning Limit register.

BS[6]

7

Bus Status.
0 (Bus-On)

The CAN Controller is involved in bus activities

1 (Bus-Off)The CAN controller is currently not involved/prohibited from bus activity
because the Transmit Error Counter reached its limiting value of 255.

-

Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.

NA

23:16 RXERR -The current value of the Rx Error Counter (an 8 - bit value).

0X

31:24 TXERR -The current value of the Tx Error Counter (an 8 - bit value).

0

X

15:8

-

[1]

After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.

[2]

If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition issignalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of anerror), no overrun condition is signalled.

[3]

The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit
is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages aretransmitted successfully.

[4]

If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting tobecome idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off thiswill take 128 times of 11 consecutive recessive bits.

[5]

Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is
set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if
enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 12–6.7 “Error Warning Limit
Register (CAN1EWL - 0xE004 4018, CAN2EWL - 0xE004 8018)”.

[6]Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', andthe Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN
Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error
Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error
Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the
Bus-Off recovery.

RX error counter
The RX Error Counter Register, which is part of the Status Register, reflects the current
value of the Receive Error Counter. After hardware reset this register is initialized to 0. In
Operating Mode this register appears to the CPU as a read only memory. A write accessto this register is possible only in Reset Mode. If a Bus Off event occurs, the RX Error
Counter is initialized to 0. As long as Bus Off is valid, writing to this register has noeffect.The Rx Error Counter is determined as follows:
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RX Error Counter = (CANxGSR AND 0x00FF0000) / 0x00010000
Note that a CPU-forced content change of the RX Error Counter is possible only if theReset Mode was entered previously. An Error Status change (Status Register), an Error
Warning or an Error Passive Interrupt forced by the new register content will not occur
until the Reset Mode is cancelled again.
TX error counter
The TX Error Counter Register, which is part of the Status Register, reflects the current
value of the Transmit Error Counter. In Operating Mode this register appears to the CPU
as a read only memory. After hardware reset this register is initialized to ’0’. A write accessto this register is possible only in Reset Mode. If a bus-off event occurs, the TX Error
Counter is initialized to 127 to count the minimum protocol-defined time (128 occurrencesof the Bus-Free signal). Reading the TX Error Counter during this time gives information
about the status of the Bus-Off recovery. If Bus Off is active, a write access to TXERR in
the range of 0 to 254 clears the Bus Off Flag and the controller will wait for one occurrenceof 11 consecutive recessive bits (bus free) after clearing of Reset Mode. The Tx error
counter is determined as follows:
TX Error Counter = (CANxGSR AND 0xFF000000) / 0x01000000
Writing 255 to TXERR allows initiation of a CPU-driven Bus Off event. Note that a
CPU-forced content change of the TX Error Counter is possible only if the Reset Modewas entered previously. An Error or Bus Status change (Status Register), an Error
Warning, or an Error Passive Interrupt forced by the new register content will not occur
until the Reset Mode is cancelled again. After leaving the Reset Mode, the new TX
Counter content is interpreted and the Bus Off event is performed in the same way as if it
was forced by a bus error event. That means, that the Reset Mode is entered again, theTX Error Counter is initialized to 127, the RX Counter is cleared, and all concerned Status
and Interrupt Register Bits are set. Clearing of Reset Mode now will perform the protocol
defined Bus Off recovery sequence (waiting for 128 occurrences of the Bus-Free signal).
If the Reset Mode is entered again before the end of Bus Off recovery (TXERR>0), Bus
Off keeps active and TXERR is frozen.

6.4 Interrupt and Capture Register (CAN1ICR - 0xE004 400C, CAN2ICR 0xE004 800C)
Bits in this register indicate information about events on the CAN bus. This register isread-only. Bits not listed read as 0 and should be written as 0.
The Interrupt flags of the Interrupt and Capture Register allow the identification of aninterrupt source. When one or more bits are set, a CAN interrupt will be indicated to theCPU. After this register is read from the CPU all interrupt bits are reset except of theReceive Interrupt bit. The Interrupt Register appears to the CPU as a read only memory.
Bits 1 thru 10 clear when they are read.
Bits 16-23 are captured when a bus error occurs. At the same time, if the BEIE bit in
CANIER is 1, the BEI bit in this register is set, and a CAN interrupt can occur.

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Bits 24-31 are captured when CAN arbitration is lost. At the same time, if the ALIE bit in
CANIER is 1, the ALI bit in this register is set, and a CAN interrupt can occur. Once eitherof these bytes is captured, its value will remain the same until it is read, at which time it isreleased to capture a new value.
The clearing of bits 1 to 10 and the releasing of bits 16-23 and 24-31 all occur on any readfrom CANxICR, regardless of whether part or all of the register is read. This means thatsoftware should always read CANxICR as a word, and process and deal with all bits of theregister as appropriate for the application.
Table 198. Interrupt and Capture Register (CAN1ICR - address 0xE004 400C, CAN2ICR address 0xE004 800C) bit description
Bit

SymbolValue

Function

Reset RM
Value Set

0

RI[1]

0 (reset)
1 (set)Receive Interrupt. This bit is set whenever the RBS bit 0
in CANxSR and the RIE bit in CANxIER are both 1,
indicating that a new message was received andstored in the Receive Buffer.

0

1

TI1

0 (reset)
1 (set)Transmit Interrupt 1. This bit is set when the TBS1 bit 0
in CANxSR goes from 0 to 1 (whenever a messageout of TXB1 was successfully transmitted or aborted),
indicating that Transmit buffer 1 is available, and theTIE1 bit in CANxIER is 1.

0

2

EI

0 (reset)
1 (set)Error Warning Interrupt. This bit is set on everychange (set or clear) of either the Error Status or Bus
Status bit in CANxSR and the EIE bit bit is set within
the Interrupt Enable Register at the time of thechange.

0

X

3

DOI

0 (reset)
1 (set)Data Overrun Interrupt. This bit is set when the DOS
bit in CANxSR goes from 0 to 1 and the DOIE bit in
CANxIER is 1.

0

0

4

WUI[2]

0 (reset)
1 (set)Wake-Up Interrupt. This bit is set if the CAN controller 0
is sleeping and bus activity is detected and the WUIE
bit in CANxIER is 1.

0

5

EPI

0 (reset)
1 (set)Error Passive Interrupt. This bit is set if the EPIE bit in 0
CANxIER is 1, and the CAN controller switches
between Error Passive and Error Active mode ineither direction.

0This is the case when the CAN Controller has reachedthe Error Passive Status (at least one error counter
exceeds the CAN protocol defined level of 127) or if
the CAN Controller is in Error Passive Status andenters the Error Active Status again.
6

ALI

0 (reset)
1 (set)Arbitration Lost Interrupt. This bit is set if the ALIE bit
in CANxIER is 1, and the CAN controller loses
arbitration while attempting to transmit. In this case
the CAN node becomes a receiver.

0

0

7

BEI

0 (reset)
1 (set)Bus Error Interrupt -- this bit is set if the BEIE bit in0
CANxIER is 1, and the CAN controller detects an error
on the bus.

X

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Table 198. Interrupt and Capture Register (CAN1ICR - address 0xE004 400C, CAN2ICR address 0xE004 800C) bit description
Bit

SymbolValue

Function

8IDI

0 (reset)
1 (set)ID Ready Interrupt -- this bit is set if the IDIE bit in0
CANxIER is 1, and a CAN Identifier has been
received (a message was successfully transmitted oraborted). This bit is set whenever a message was
successfully transmitted or aborted and the IDIE bit isset in the IER reg.

0

9

TI2

0 (reset)
1 (set)Transmit Interrupt 2. This bit is set when the TBS2 bit 0
in CANxSR goes from 0 to 1 (whenever a messageout of TXB2 was successfully transmitted or aborted),
indicating that Transmit buffer 2 is available, and theTIE2 bit in CANxIER is 1.

0

10

TI3

0 (reset)
1 (set)Transmit Interrupt 3. This bit is set when the TBS3 bit 0
in CANxSR goes from 0 to 1 (whenever a messageout of TXB3 was successfully transmitted or aborted),
indicating that Transmit buffer 3 is available, and the
TIE3 bit in CANxIER is 1.

0-

Reserved, user software should not write ones toreserved bits.

0

15:11 -

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Reset RM
Value Set

0

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Chapter 12: LPC2300 CAN1, 2

Table 198. Interrupt and Capture Register (CAN1ICR - address 0xE004 400C, CAN2ICR address 0xE004 800C) bit description
Bit

SymbolValue

20:16 ERRBIT
4:0[3]

21

FunctionError Code Capture: when the CAN controller detects 0
a bus error, the location of the error within the frame iscaptured in this field. The value reflects an internal
state variable, and as a result is not very linear:
00011

Start of Frame

00010

ID28 ... ID21

00110

ID20 ... ID18

00100

SRTR Bit

00101

IDE bit

00111

ID17 ... 13

01111

ID12 ... ID501110

ID4 ... ID0

01100

RTR Bit

01101

Reserved Bit 1

01001

Reserved Bit 0

01011

Data Length Code

01010

Data Field

01000

CRC Sequence

11000

CRC Delimiter

11001

Acknowledge Slot11011

Acknowledge Delimiter

11010

End of Frame

10010

Intermission

10001

Active Error Flag

10110

Passive Error Flag

10011

Tolerate Dominant Bits

10111

Error Delimiter

11100

Overload flag

ERRDIR

When the CAN controller detects a bus error, thedirection of the current bit is captured in this bit.

X

0

X

When the CAN controller detects a bus error, the type 0of error is captured in this field:

X

0Error occurred during transmitting.

1

Error occurred during receiving.

23:22 ERRC1:000

Bit error

01

Form error

10

Stuff error

11

Other error

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Value Set

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Chapter 12: LPC2300 CAN1, 2

Table 198. Interrupt and Capture Register (CAN1ICR - address 0xE004 400C, CAN2ICR address 0xE004 800C) bit description
Bit

SymbolValue

31:24 ALCBIT[4] -Function

Reset RM
Value Set

Each time arbitration is lost while trying to send on the 0
CAN, the bit number within the frame is captured into
this field. After the content of ALCBIT is read, the ALI
bit is cleared and a new Arbitration Lost interrupt canoccur.

00

arbitration lost in the first bit (MS) of identifier

...

a

11

arbitration lost in SRTS bit (RTR bit for standard frame
messages)

12

arbitration lost in IDE bit

13

arbitration lost in 12th bit of identifier (extended frame
only)

X

...
30

arbitration lost in last bit of identifier (extended frame
only)

31

arbitration lost in RTR bit (extended frame only)[1]

The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command“Release Receive Buffer” will clear RI temporarily. If there is another message available within the Receive
Buffer after the release command, RI is set again. Otherwise RI remains cleared.

[2]

A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller isinvolved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when theaccording enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.

[3]

Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time,
the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The
content within this register is fixed until the user software has read out its content once. From now on, thecapture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt.

[4]

On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current
bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content
within this register is fixed until the user application has read out its contents once. From now on, thecapture mechanism is activated again.

6.5 Interrupt Enable Register (CAN1IER - 0xE004 4010, CAN2IER 0xE004 8010)
This read/write register controls whether various events on the CAN controller will result in
an interrupt or not. Bits 10:0 in this register correspond 1-to-1 with bits 10:0 in the
CANxICR register. If a bit in the CANxIER register is 0 the corresponding interrupt isdisabled; if a bit in the CANxIER register is 1 the corresponding source is enabled totrigger an interrupt.

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Chapter 12: LPC2300 CAN1, 2

Table 199. Interrupt Enable Register (CAN1IER - address 0xE004 4010, CAN2IER - address
0xE004 8010) bit description
Bit

Symbol Function

Reset RM
Value Set

0

RIE

Receiver Interrupt Enable. When the Receive Buffer Status is 'full', 0
the CAN Controller requests the respective interrupt.

X

1

TIE1

Transmit Interrupt Enable for Buffer1. When a message has been 0
successfully transmitted out of TXB1 or Transmit Buffer 1 isaccessible again (e.g. after an Abort Transmission command), the
CAN Controller requests the respective interrupt.

X

2

EIE

Error Warning Interrupt Enable. If the Error or Bus Status change 0(see Status Register), the CAN Controller requests the respective
interrupt.

X

3

DOIE

Data Overrun Interrupt Enable. If the Data Overrun Status bit isset (see Status Register), the CAN Controller requests therespective interrupt.

0

X

4

WUIE

Wake-Up Interrupt Enable. If the sleeping CAN controller wakes
up, the respective interrupt is requested.

0

X

5

EPIE

Error Passive Interrupt Enable. If the error status of the CAN
0Controller changes from error active to error passive or vice versa,
the respective interrupt is requested.

X

6

ALIE

Arbitration Lost Interrupt Enable. If the CAN Controller has lostarbitration, the respective interrupt is requested.

0

X

7

BEIE

Bus Error Interrupt Enable. If a bus error has been detected, the
CAN Controller requests the respective interrupt.

0

X

8

IDIE

ID Ready Interrupt Enable. When a CAN identifier has been
received, the CAN Controller requests the respective interrupt.

0

X

9

TIE2

Transmit Interrupt Enable for Buffer2. When a message has been 0
successfully transmitted out of TXB2 or Transmit Buffer 2 isaccessible again (e.g. after an Abort Transmission command), the
CAN Controller requests the respective interrupt.

X

10

TIE3

Transmit Interrupt Enable for Buffer3. When a message has been 0
successfully transmitted out of TXB3 or Transmit Buffer 3 isaccessible again (e.g. after an Abort Transmission command), the
CAN Controller requests the respective interrupt.

X

31:11

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

6.6 Bus Timing Register (CAN1BTR - 0xE004 4014, CAN2BTR 0xE004 8014)
This register controls how various CAN timings are derived from the APB clock. It defines
the values of the Baud Rate Prescaler (BRP) and the Synchronization Jump Width (SJW).
Furthermore, it defines the length of the bit period, the location of the sample point and thenumber of samples to be taken at each sample point. It can be read at any time but can
only be written if the RM bit in CANmod is 1.

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Table 200. Bus Timing Register (CAN1BTR - address 0xE004 4014, CAN2BTR - address
0xE004 8014) bit description
Bit

Symbol Value Function

Reset RM
Value Set

9:0

BRP

Baud Rate Prescaler. The APB clock is divided by (thisvalue plus one) to produce the CAN clock.

0

13:10 -

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

15:14 SJWThe Synchronization Jump Width is (this value plus one)
CAN clocks.

0X

19:16 TESG1

The delay from the nominal Sync point to the sample pointis (this value plus one) CAN clocks.

1100

X

22:20 TESG2001
The delay from the sample point to the next nominal sync
point is (this value plus one) CAN clocks. The nominal CAN
bit time is (this value plus the value in TSEG1 plus 3) CAN
clocks.

X

23

Sampling

SAM
0

The bus is sampled once (recommended for high speed
buses)

1

The bus is sampled 3 times (recommended for low to
medium speed buses to filter spikes on the bus-line)

31:24 -

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

X

0

X

NA

Baud rate prescaler
The period of the CAN system clock tSCL is programmable and determines the individual
bit timing. The CAN system clock tSCL is calculated using the following equation:(1)
t SCL = t CANsuppliedCLK × ( BRP + 1 )Synchronization jump width
To compensate for phase shifts between clock oscillators of different bus controllers, any
bus controller must re-synchronize on any relevant signal edge of the current
transmission. The synchronization jump width tSJW defines the maximum number of clock
cycles a certain bit period may be shortened or lengthened by one re-synchronization:(2)
t SJW = t SCL × ( SJW + 1 )Time segment 1 and time segment 2
Time segments TSEG1 and TSEG2 determine the number of clock cycles per bit period
and the location of the sample point:(3)
t SYNCSEG = t SCL
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t TSEG1 = t SCL × ( TSEG1 + 1 )(5)t TSEG2 = t SCL × ( TSEG2 + 1 )6.7 Error Warning Limit Register (CAN1EWL - 0xE004 4018, CAN2EWL 0xE004 8018)
This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be readat any time but can only be written if the RM bit in CANmod is 1. The default value (after
hardware reset) is 96.
Table 201. Error Warning Limit register (CAN1EWL - address 0xE004 4018, CAN2EWL address 0xE004 8018) bit description
Bit Symbol Function
7:0 EWL

Reset
Value

RM
Set

During CAN operation, this value is compared to both the Tx and 9610 = 0x60 X
Rx Error Counters. If either of these counter matches this value,the Error Status (ES) bit in CANSR is set.

Note that a content change of the Error Warning Limit Register is possible only if theReset Mode was entered previously. An Error Status change (Status Register) and an
Error Warning Interrupt forced by the new register content will not occur until the Reset
Mode is cancelled again.

6.8 Status Register (CAN1SR - 0xE004 401C, CAN2SR - 0xE004 801C)
This register contains three status bytes in which the bits not related to transmission are
identical to the corresponding bits in the Global Status Register, while those relating totransmission reflect the status of each of the 3 Tx Buffers.
Table 202. Status Register (CAN1SR - address 0xE004 401C, CAN2SR - address 0xE004 801C) bit description
Bit

Symbol Value

Function

Reset RM
Value Set

0

RBS

Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.

0

0

1

DOS

Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.

0

0

2

TBS1[1]

Transmit Buffer Status 1.

1

1

1

x

1

0

3

4

0(locked)

Software cannot access the Tx Buffer 1 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because amessage is either waiting for transmission or is in transmitting process.

1(released)

Software may write a message into the Transmit Buffer 1 and its CANxTFI,CANxTID, CANxTDA, and CANxTDB registers.

TCS1[2]

RS

Transmission Complete Status.
0(incomplete)

The previously requested transmission for Tx Buffer 1 is not complete.

1(complete)

The previously requested transmission for Tx Buffer 1 has been successfullycompleted.
Receive Status. This bit is identical to the RS bit in the GSR.

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Chapter 12: LPC2300 CAN1, 2

Table 202. Status Register (CAN1SR - address 0xE004 401C, CAN2SR - address 0xE004 801C) bit description
Bit

Symbol Value

Function

Reset RM
Value Set

5

TS1

Transmit Status 1.

100(idle)There is no transmission from Tx Buffer 1.

1(transmit)

The CAN Controller is transmitting a message from Tx Buffer 1.

6

ES

Error Status. This bit is identical to the ES bit in the CANxGSR.

0

0

7

BS

Bus Status. This bit is identical to the BS bit in the CANxGSR.

0

0

8

RBS

Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.

0

0

9

DOS

Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.

0

0

10

TBS2[1]

Transmit Buffer Status 2.

1

1

1

x

11

0(locked)

Software cannot access the Tx Buffer 2 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because amessage is either waiting for transmission or is in transmitting process.

1(released)

Software may write a message into the Transmit Buffer 2 and its CANxTFI,CANxTID, CANxTDA, and CANxTDB registers.

0(incomplete)

The previously requested transmission for Tx Buffer 2 is not complete.

1(complete)

The previously requested transmission for Tx Buffer 2 has been successfullycompleted.

TCS2[2]

Transmission Complete Status.

12

RS

Receive Status. This bit is identical to the RS bit in the GSR.

1

0

13

TS2

Transmit Status 2.

100(idle)There is no transmission from Tx Buffer 2.

1(transmit)

The CAN Controller is transmitting a message from Tx Buffer 2.

14

ES

Error Status. This bit is identical to the ES bit in the CANxGSR.

0

0

15

BS

Bus Status. This bit is identical to the BS bit in the CANxGSR.

0

0

16

RBS

Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.

0

0

17

DOS

Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.

0

0

18

TBS3[1]

Transmit Buffer Status 3.

1

1

1

x

19

0(locked)

Software cannot access the Tx Buffer 3 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because amessage is either waiting for transmission or is in transmitting process.

1(released)

Software may write a message into the Transmit Buffer 3 and its CANxTFI,CANxTID, CANxTDA, and CANxTDB registers.

TCS3[2]

Transmission Complete Status.
0(incomplete)

The previously requested transmission for Tx Buffer 3 is not complete.

1(complete)

The previously requested transmission for Tx Buffer 3 has been successfullycompleted.

20

RS

Receive Status. This bit is identical to the RS bit in the GSR.

1

0

21

TS3

Transmit Status 3.

100(idle)There is no transmission from Tx Buffer 3.

1(transmit)

The CAN Controller is transmitting a message from Tx Buffer 3.

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Chapter 12: LPC2300 CAN1, 2

Table 202. Status Register (CAN1SR - address 0xE004 401C, CAN2SR - address 0xE004 801C) bit description
Bit

Symbol Value

Function

Reset RM
Value Set

22

ES

Error Status. This bit is identical to the ES bit in the CANxGSR.

0

0

23

BS

Bus Status. This bit is identical to the BS bit in the CANxGSR.

00

Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.

NA

31:24 -

[1]

If the CPU tries to write to this Transmit Buffer when the Transmit Buffer Status bit is '0' (locked), the written byte is not accepted and islost without this being signalled.

[2]

The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit
is set '1' for this TX buffer. The Transmission Complete Status bit remains '0' until a message is transmitted successfully.

6.9 Receive Frame Status Register (CAN1RFS - 0xE004 4020, CAN2RFS 0xE004 8020)
This register defines the characteristics of the current received message. It is read-only innormal operation but can be written for testing purposes if the RM bit in CANxMOD is 1.
Table 203. Receive Frame Status register (CAN1RFS - address 0xE004 4020, CAN2RFS address 0xE004 8020) bit description
Bit

Symbol Function

Reset RM
Value Set

9:0

ID Index If the BP bit (below) is 0, this value is the zero-based number of the 0
Lookup Table RAM entry at which the Acceptance Filter matched
the received Identifier. Disabled entries in the Standard tables areincluded in this numbering, but will not be matched. See Section
12–16 “Examples of acceptance filter tables and ID index values”
on page 259 for examples of ID Index values.

X

10

BP

X

If this bit is 1, the current message was received in AF Bypass
mode, and the ID Index field (above) is meaningless.

0

15:11 -

Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.

19:16 DLC

The field contains the Data Length Code (DLC) field of the current
received message. When RTR = 0, this is related to the number ofdata bytes available in the CANRDA and CANRDB registers as
follows:

0X

0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes
With RTR = 1, this value indicates the number of data bytes
requested to be sent back, with the same encoding.
29:20 -

Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.

30

RTR

This bit contains the Remote Transmission Request bit of the0current received message. 0 indicates a Data Frame, in which (ifDLC is non-zero) data can be read from the CANRDA and possibly
the CANRDB registers. 1 indicates a Remote frame, in which case
the DLC value identifies the number of data bytes requested to besent using the same Identifier.

X

31

FF

A 0 in this bit indicates that the current received message included 0
an 11 bit Identifier, while a 1 indicates a 29 bit Identifier. This affects
the contents of the CANid register described below.

X

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6.9.1 ID index field
The ID Index is a 10-bit field in the Info Register that contains the table position of the ID
Look-up Table if the currently received message was accepted. The software can use thisindex to simplify message transfers from the Receive Buffer into the Shared Message
Memory. Whenever bit 10 (BP) of the ID Index in the CANRFS register is 1, the current
CAN message was received in acceptance filter bypass mode.

6.10 Receive Identifier Register (CAN1RID - 0xE004 4024, CAN2RID 0xE004 8024)
This register contains the Identifier field of the current received message. It is read-only innormal operation but can be written for testing purposes if the RM bit in CANmod is 1. It
has two different formats depending on the FF bit in CANRFS. See Table 12–192 fordetails on specific CAN channel register address.
Table 204. Receive Identifier Register (CAN1RID - address 0xE004 4024, CAN2RID - address
0xE004 8024) bit description
Bit

Symbol Function

Reset Value RM Set

10:0

ID

The 11 bit Identifier field of the current received
message. In CAN 2.0A, these bits are called ID10-0,
while in CAN 2.0B they’re called ID29-18.

0

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

31:11 -X

Table 205. RX Identifier register when FF = 1
Bit

Symbol Function

Reset Value RM Set

28:0

ID

The 29 bit Identifier field of the current received
message. In CAN 2.0B these bits are called ID29-0.

0

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

31:29 -

X

6.11 Receive Data Register A (CAN1RDA - 0xE004 4028, CAN2RDA 0xE004 8028)
This register contains the first 1-4 Data bytes of the current received message. It is
read-only in normal operation, but can be written for testing purposes if the RM bit in
CANMOD is 1. See Table 12–192 for details on specific CAN channel register address.
Table 206. Receive Data register A (CAN1RDA - address 0xE004 4028, CAN2RDA - address
0xE004 8028) bit description
Bit

Symbol Function

7:0

Data 1

If the DLC field in CANRFS ≥ 0001, this contains the first Data byte 0of the current received message.

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Table 206. Receive Data register A (CAN1RDA - address 0xE004 4028, CAN2RDA - address
0xE004 8028) bit description
Bit

Symbol Function

Reset RM
Value Set

15:8

Data 2

If the DLC field in CANRFS ≥ 0010, this contains the first Data byte 0of the current received message.

X

23:16 Data 3

If the DLC field in CANRFS ≥ 0011, this contains the first Data byte 0of the current received message.

X

31:24 Data 4

If the DLC field in CANRFS ≥ 0100, this contains the first Data byte 0of the current received message.

X

6.12 Receive Data Register B (CAN1RDB - 0xE004 402C, CAN2RDB 0xE004 802C)
This register contains the 5th through 8th Data bytes of the current received message. It is
read-only in normal operation, but can be written for testing purposes if the RM bit in
CANMOD is 1. See Table 12–192 for details on specific CAN channel register address.
Table 207. Receive Data register B (CAN1RDB - address 0xE004 402C, CAN2RDB - address
0xE004 802C) bit description
Bit

Symbol Function

Reset RM
Value Set

7:0

Data 5

If the DLC field in CANRFS ≥ 0101, this contains the first Data byte 0of the current received message.

X

15:8

Data 6

If the DLC field in CANRFS ≥ 0110, this contains the first Data byte 0of the current received message.

X

23:16 Data 7

If the DLC field in CANRFS ≥ 0111, this contains the first Data byte 0of the current received message.

X

31:24 Data 8

If the DLC field in CANRFS ≥ 1000, this contains the first Data byte 0of the current received message.

X

6.13 Transmit Frame Information Register (CAN1TFI[1/2/3] - 0xE004 40[30/40/50], CAN2TFI[1/2/3] - 0xE004 80[30/40/50])
When the corresponding TBS bit in CANSR is 1, software can write to one of theseregisters to define the format of the next transmit message for that Tx buffer. Bits not listed
read as 0 and should be written as 0.
The values for the reserved bits of the CANxTFI register in the Transmit Buffer should be
set to the values expected in the Receive Buffer for an easy comparison, when using the
Self Reception facility (self test), otherwise they are not defined.
The CAN Controller consist of three Transmit Buffers. Each of them has a length of 4
words and is able to store one complete CAN message as shown in Figure 12–30.
The buffer layout is subdivided into Descriptor and Data Field where the first word of the
Descriptor Field includes the TX Frame Info that describes the Frame Format, the Data
Length and whether it is a Remote or Data Frame. In addition, a TX Priority register allows
the definition of a certain priority for each transmit message. Depending on the chosen
Frame Format, an 11-bit identifier for Standard Frame Format (SFF) or an 29-bit identifier
for Extended Frame Format (EFF) follows. Note that unused bits in the TID field have tobe defined as 0. The Data Field in TDA and TDB contains up to eight data bytes.
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Table 208. Transmit Frame Information Register (CAN1TFI[1/2/3] - address
0xE004 40[30/40/50], CAN2TFI[1/2/3] - 0xE004 80[30/40/50]) bit description
Bit

Symbol Function

7:0

PRIO

If the TPM (Transmit Priority Mode) bit in the CANxMOD register is
set to 1, enabled Tx Buffers contend for the right to send theirmessages based on this field. The buffer with the lowest TX Priority
value wins the prioritization and is sent first.

15:8

-

Reserved.

0

Data Length Code. This value is sent in the DLC field of the nexttransmit message. In addition, if RTR = 0, this value controls thenumber of Data bytes sent in the next transmit message, from the
CANxTDA and CANxTDB registers:

0

19:16 DLC

Reset RM
Value Set
x

X

0000-0111 = 0-7 bytes
1xxx = 8 bytes
29:20 -

Reserved.

0

30

RTR

0
This value is sent in the RTR bit of the next transmit message. If
this bit is 0, the number of data bytes called out by the DLC field aresent from the CANxTDA and CANxTDB registers. If this bit is 1, aRemote Frame is sent, containing a request for that number ofbytes.

X

31

FF

If this bit is 0, the next transmit message will be sent with an 11 bit 0
Identifier (standard frame format), while if it’s 1, the message will besent with a 29 bit Identifier (extended frame format).

X

Automatic transmit priority detection
To allow uninterrupted streams of transmit messages, the CAN Controller provides
Automatic Transmit Priority Detection for all Transmit Buffers. Depending on the selectedTransmit Priority Mode, internal prioritization is based on the CAN Identifier or a user
defined "local priority". If more than one message is enabled for transmission (TR=1) theinternal transmit message queue is organized such as that the transmit buffer with thelowest CAN Identifier (TID) or the lowest "local priority" (TX Priority) wins the prioritizationand is sent first. The result of the internal scheduling process is taken into account short
before a new CAN message is sent on the bus. This is also true after the occurrence of atransmission error and right before a re-transmission.
Tx DLCThe number of bytes in the Data Field of a message is coded with the Data Length Code(DLC). At the start of a Remote Frame transmission the DLC is not considered due to the
RTR bit being '1 ' (remote). This forces the number of transmitted/received data bytes tobe 0. Nevertheless, the DLC must be specified correctly to avoid bus errors, if two CAN
Controllers start a Remote Frame transmission with the same identifier simultaneously.
For reasons of compatibility no DLC > 8 should be used. If a value greater than 8 isselected, 8 bytes are transmitted in the data frame with the Data Length Code specified in
DLC. The range of the Data Byte Count is 0 to 8 bytes and is coded as follows:(6)
DataByteCount = DLC

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6.14 Transmit Identifier Register (CAN1TID[1/2/3] - 0xE004 40[34/44/54],
CAN2TID[1/2/3] - 0xE004 80[34/44/54])
When the corresponding TBS bit in CANxSR is 1, software can write to one of theseregisters to define the Identifier field of the next transmit message. Bits not listed read as 0
and should be written as 0. The register assumes two different formats depending on the
FF bit in CANTFI.
In Standard Frame Format messages, the CAN Identifier consists of 11 bits (ID.28 toID.18), and in Extended Frame Format messages, the CAN identifier consists of 29 bits
(ID.28 to ID.0). ID.28 is the most significant bit, and it is transmitted first on the bus during
the arbitration process. The Identifier acts as the message's name, used in a receiver for
acceptance filtering, and also determines the bus access priority during the arbitration
process.
Table 209. Transfer Identifier Register (CAN1TID[1/2/3] - address 0xE004 40[34/44/54],
CAN2TID[1/2/3] - address 0xE004 80[34/44/54]) bit description
Bit

Symbol Function

Reset RM
Value Set

10:0

ID

The 11 bit Identifier to be sent in the next transmit message.

0

31:11

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

X

Table 210. Transfer Identifier register when FF = 1
Bit

Symbol Function

Reset RM
Value Set

28:0

ID

The 29 bit Identifier to be sent in the next transmit message.

0

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

31:29 -

X

6.15 Transmit Data Register A (CAN1TDA[1/2/3] - 0xE004 40[38/48/58],
CAN2TDA[1/2/3] - 0xE004 80[38/48/58])
When the corresponding TBS bit in CANSR is 1, software can write to one of theseregisters to define the first 1 - 4 data bytes of the next transmit message. The Data Length
Code defines the number of transferred data bytes. The first bit transmitted is the mostsignificant bit of TX Data Byte 1.
Table 211. Transmit Data Register A (CAN1TDA[1/2/3] - address 0xE004 40[38/48/58],
CAN2TDA[1/2/3] - address 0xE004 80[38/48/58]) bit description
Bit

Symbol Function

Reset
Value

RM
Set

7:0

Data 1

If RTR = 0 and DLC ≥ 0001 in the corresponding CANxTFI, thisbyte is sent as the first Data byte of the next transmit message.

0

X

15;8

Data 2

If RTR = 0 and DLC ≥ 0010 in the corresponding CANxTFI, thisbyte is sent as the 2nd Data byte of the next transmit message.

0X

23:16 Data 3

If RTR = 0 and DLC ≥ 0011 in the corresponding CANxTFI, thisbyte is sent as the 3rd Data byte of the next transmit message.

0X

31:24 Data 4

If RTR = 0 and DLC ≥ 0100 in the corresponding CANxTFI, thisbyte is sent as the 4th Data byte of the next transmit message.

0

X

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6.16 Transmit Data Register B (CAN1TDB[1/2/3] - 0xE004 40[3C/4C/5C],
CAN2TDB[1/2/3] - 0xE004 80[3C/4C/5C])
When the corresponding TBS bit in CANSR is 1, software can write to one of theseregisters to define the 5th through 8th data bytes of the next transmit message. The Data
Length Code defines the number of transferred data bytes. The first bit transmitted is themost significant bit of TX Data Byte 1.
Table 212. Transmit Data Register B (CAN1TDB[1/2/3] - address 0xE004 40[3C/4C/5C],
CAN2TDB[1/2/3] - address 0xE004 80[3C/4C/5C]) bit description
Bit

Symbol Function

Reset
Value

RM
Set

7:0

Data 5

If RTR = 0 and DLC ≥ 0101 in the corresponding CANTFI, thisbyte is sent as the 5th Data byte of the next transmit message.

0

X

15;8

Data 6

If RTR = 0 and DLC ≥ 0110 in the corresponding CANTFI, thisbyte is sent as the 6th Data byte of the next transmit message.

0X

23:16 Data 7

If RTR = 0 and DLC ≥ 0111 in the corresponding CANTFI, thisbyte is sent as the 7th Data byte of the next transmit message.

0X

31:24 Data 8

If RTR = 0 and DLC ≥ 1000 in the corresponding CANTFI, thisbyte is sent as the 8th Data byte of the next transmit message.

0X

7. CAN controller operation
7.1 Error handling
The CAN Controllers count and handle transmit and receive errors as specified in CAN
Spec 2.0B. The Transmit and Receive Error Counters are incriminated for each detected
error and are decremented when operation is error-free. If the Transmit Error countercontains 255 and another error occurs, the CAN Controller is forced into a state called
Bus-Off. In this state, the following register bits are set: BS in CANxSR, BEI and EI in
CANxIR if these are enabled, and RM in CANxMOD. RM resets and disables much of the
CAN Controller. Also at this time the Transmit Error Counter is set to 127 and the Receive
Error Counter is cleared. Software must next clear the RM bit. Thereafter the Transmit
Error Counter will count down 128 occurrences of the Bus Free condition (11 consecutive
recessive bits). Software can monitor this countdown by reading the Tx Error Counter.
When this countdown is complete, the CAN Controller clears BS and ES in CANxSR, andsets EI in CANxSR if EIE in IER is 1.
The Tx and Rx error counters can be written if RM in CANxMOD is 1. Writing 255 to theTx Error Counter forces the CAN Controller to Bus-Off state. If Bus-Off (BS in CANxSR) is
1, writing any value 0 through 254 to the Tx Error Counter clears Bus-Off. When software
clears RM in CANxMOD thereafter, only one Bus Free condition (11 consecutive
recessive bits) is needed before operation resumes.

7.2 Sleep mode
The CAN Controller will enter sleep mode if the SM bit in the CAN Mode register is 1, no
CAN interrupt is pending, and there is no activity on the CAN bus. Software can only set
SM when RM in the CAN Mode register is 0; it can also set the WUIE bit in the CAN
Interrupt Enable register to enable an interrupt on any wake-up condition.

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The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the
CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b)
software clearing SM in the CAN Mode register. A sleeping CAN Controller, that wakes up
in response to bus activity, is not able to receive an initial message, until after it detects
Bus_Free (11 consecutive recessive bits). If an interrupt is pending or the CAN bus isactive when software sets SM, the wake-up is immediate.

7.3 Interrupts
Each CAN Controller produces 3 interrupt requests, Receive, Transmit, and “other status”.
The Transmit interrupt is the OR of the Transmit interrupts from the three Tx Buffers. Each
Receive and Transmit interrupt request from each controller is assigned its own channel inthe Vectored Interrupt Controller (VIC), and can have its own interrupt service routine. The“other status” interrupts from all of the CAN controllers, and the Acceptance Filter LUTerrcondition, are ORed into one VIC channel.

7.4 Transmit priority
If the TPM bit in the CANxMOD register is 0, multiple enabled Tx Buffers contend for theright to send their messages based on the value of their CAN Identifier (TID). If TPM is 1,
they contend based on the PRIO fields in bits 7:0 of their CANxTFS registers. In bothcases the smallest binary value has priority. If two (or three) transmit-enabled buffers havethe same smallest value, the lowest-numbered buffer sends first.
The CAN controller selects among multiple enabled Tx Buffers dynamically, just before it
sends each message.

8. Centralized CAN registers
For easy and fast access, all CAN Controller Status bits from each CAN Controller Status
register are bundled together. Each defined byte of the following registers contains one
particular status bit from each of the CAN controllers, in its LS bits.
All Status registers are “read-only” and allow byte, half word and word access.

8.1 Central Transmit Status Register (CANTxSR - 0xE004 0000)
Table 213. Central Transit Status Register (CANTxSR - address 0xE004 0000) bit description
Bit

SymbolDescription0

TS1

When 1, the CAN controller 1 is sending a message (same as TS in the 0
CAN1GSR).

1

TS2

When 1, the CAN controller 2 is sending a message (same as TS in the 0
CAN2GSR)

7:2-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

8

TBS1

When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU 1(same as TBS in CAN1GSR).

9

TBS2

When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU 1(same as TBS in CAN2GSR).

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Table 213. Central Transit Status Register (CANTxSR - address 0xE004 0000) bit description
Bit

SymbolDescription

Reset
Value

15:10 -

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

16

TCS1

When 1, all requested transmissions have been completed successfully 1
by the CAN1 controller (same as TCS in CAN1GSR).

17:16 TCS2

When 1, all requested transmissions have been completed successfully 1
by the CAN2 controller (same as TCS in CAN2GSR).

31:18 -

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

8.2 Central Receive Status Register (CANRxSR - 0xE004 0004)
Table 214. Central Receive Status Register (CANRxSR - address 0xE004 0004) bit
description
Bit

Symbol Description

Reset
Value

0

RS1

0

When 1, CAN1 is receiving a message (same as RS in CAN1GSR).

1

RS2

When 1, CAN2 is receiving a message (same as RS in CAN2GSR).

0

7:2

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

8

RB1

When 1, a received message is available in the CAN1 controller (sameas RBS in CAN1GSR).

0

9

RB2

When 1, a received message is available in the CAN2 controller (sameas RBS in CAN2GSR).

0

15:10 -

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

16

DOS1

When 1, a message was lost because the preceding message to CAN1 0
controller was not read out quickly enough (same as DOS in CAN1GSR).

17:16 DOS2

When 1, a message was lost because the preceding message to CAN2 0
controller was not read out quickly enough (same as DOS in CAN2GSR).

31:18 -

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

8.3 Central Miscellaneous Status Register (CANMSR - 0xE004 0008)
Table 215. Central Miscellaneous Status Register (CANMSR - address 0xE004 0008) bit
description
Bit

Symbol Description

0

E1

When 1, one or both of the CAN1 Tx and Rx Error Counters has reached 0
the limit set in the CAN1EWL register (same as ES in CAN1GSR)

1

E2

When 1, one or both of the CAN2 Tx and Rx Error Counters has reached 0
the limit set in the CAN2EWL register (same as ES in CAN2GSR)

7:2-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

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Table 215. Central Miscellaneous Status Register (CANMSR - address 0xE004 0008) bit
description
Bit

Symbol Description

8

BS1

When 1, the CAN1 controller is currently involved in bus activities (same 0
as BS in CAN1GSR).

9

BS2

When 1, the CAN2 controller is currently involved in bus activities (same 0
as BS in CAN2GSR).

31:10 -

Reset
Value

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

9. Global acceptance filter
This block provides lookup for received Identifiers (called Acceptance Filtering in CAN
terminology) for all the CAN Controllers. It includes a 512 × 32 (2 kB) RAM in whichsoftware maintains one to five tables of Identifiers. This RAM can contain up to 1024
Standard Identifiers or 512 Extended Identifiers, or a mixture of both types.

10. Acceptance filter modes
The Acceptance Filter can be put into different modes by setting the according AccOff,
AccBP, and eFCAN bits in the Acceptance Filter Mode Register (Section 12–13.1“Acceptance Filter Mode Register (AFMR - 0xE003 C000)”). During each mode theaccess to the Configuration Register and the ID Look-up table is handled differently.
Table 216. Acceptance filter modes and access control
Acceptance Bit
Bit
Acceptancefilter mode AccOff AccBP filter state

ID Look-up
table
RAM[1]

Acceptance filterconfig.
registers

CAN controller
message receive
interrupt

Off Mode

10reset &
haltedr/w accessfrom CPUr/w accessfrom CPUno messages
accepted

BypassModeX

1reset &
haltedr/w accessfrom CPUr/w accessfrom CPU

all messages
accepted

OperatingMode and
FullCANMode

00runningread only
from CPU[2]access from hardware
Acceptance acceptance filteringfilter only

[1]

The whole ID Look-up Table RAM is only word accessible.

[2]

During the Operating Mode of the Acceptance Filter the Look-up Table can be accessed only to disable orenable Messages.

A write access to all section configuration registers is only possible during the Acceptance
Filter Off and Bypass Mode. Read access is allowed in all Acceptance Filter Modes.

10.1 Acceptance filter Off mode
The Acceptance Filter Off Mode is typically used during initialization. During this mode an
unconditional access to all registers and to the Look-up Table RAM is possible. With the
Acceptance Filter Off Mode, CAN messages are not accepted and therefore not stored in
the Receive Buffers of active CAN Controllers.
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10.2 Acceptance filter Bypass mode
The Acceptance Filter Bypass Mode can be used for example to change the acceptancefilter configuration during a running system, e.g. change of identifiers in the ID-Look-up
Table memory. During this re-configuration, software acceptance filtering has to be used.
It is recommended to use the ID ready Interrupt (ID Index) and the Receive Interrupt (RI).
In this mode all CAN message are accepted and stored in the Receive Buffers of active
CAN Controllers.

10.3 Acceptance filter Operating mode
The Acceptance Filter is in Operating Mode when neither the AccOff nor the AccBP in the
Configuration Register is set and the eFCAN = 0.

10.4 FullCAN mode
The Acceptance Filter is in Operating Mode when neither the AccOff nor the AccBP in the
Configuration Register is set and the eFCAN = 1. More details on FullCAN mode areavailable in Section 12–15 “FullCAN mode”.

11. Sections of the ID look-up table RAM
Four 12-bit section configuration registers (SFF_sa, SFF_GRP_sa, EFF_sa,
EFF_GRP_sa) are used to define the boundaries of the different identifier sections in the
ID-Look-up Table Memory. The fifth 12-bit section configuration register, the End of Table
address register (ENDofTable) is used to define the end of all identifier sections. The End
of Table address is also used to assign the start address of the section where FullCAN
Message Objects, if enabled are stored.
Table 217. Section configuration register settings
ID-Look up Table Section

Register

Value

SectionstatusFullCAN (Standard Frame Format) Identifier Section

SFF_sa= 0x000

disabled> 0x000

enabledExplicit Standard Frame Format Identifier Section
Group of Standard Frame Format Identifier Section

SFF_GRP_sa = SFF_sa

disabled> SFF_saenabled

EFF_sa= SFF_GRP_sa disabled> SFF_GRP_sa enabled

Explicit Extended Frame Format Identifier Section
Group of Extended Frame Format Identifier Section

EFF_GRP_sa = EFF_sa

disabled> EFF_saenabled

ENDofTable= EFF_GRP_sa disabled> EFF_GRP_sa enabled

12. ID look-up table RAM
The Whole ID Look-up Table RAM is only word accessible. A write access is only possible
during the Acceptance Filter Off or Bypass Mode. Read access is allowed in all
Acceptance Filter Modes.
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If Standard (11 bit) Identifiers are used in the application, at least one of 3 tables in
Acceptance Filter RAM must not be empty. If the optional “fullCAN mode” is enabled, thefirst table contains Standard identifiers for which reception is to be handled in this mode.
The next table contains individual Standard Identifiers and the third contains ranges ofStandard Identifiers, for which messages are to be received via the CAN Controllers. The
tables of fullCAN and individual Standard Identifiers must be arranged in ascending
numerical order, one per halfword, two per word. Since each CAN bus has its own
address map, each entry also contains the number of the CAN Controller (001-010) towhich it applies.

31
15

CONTROLLER #

16
0

26
10

29
13

DIS
NOT
ABLE USEDIDENTIFIER

Fig 34. Entry in FullCAN and individual standard identifier tables

The table of Standard Identifier Ranges contains paired upper and lower (inclusive)bounds, one pair per word. These must also be arranged in ascending numerical order.

16
LOWER IDENTIFIER
BOUND

10
CONTROLLER#DISABLENOT USEDCONTROLLER#

26
NOT USED

29
DISABLE

31

0
UPPER IDENTIFIER
BOUND

Fig 35. Entry in standard identifier range table

The disable bits in Standard entries provide a means to turn response, to particular CAN
Identifiers or ranges of Identifiers, on and off dynamically. When the Acceptance Filter
function is enabled, only the disable bits in Acceptance Filter RAM can be changed bysoftware. Response to a range of Standard addresses can be enabled by writing 32 zero
bits to its word in RAM, and turned off by writing 32 one bits (0xFFFF FFFF) to its word in
RAM. Only the disable bits are actually changed. Disabled entries must maintain theascending sequence of Identifiers.
If Extended (29 bit) Identifiers are used in the application, at least one of the other two
tables in Acceptance Filter RAM must not be empty, one for individual Extended Identifiers
and one for ranges of Extended Identifiers. The table of individual Extended Identifiersmust be arranged in ascending numerical order.

31

29 28

0

CONTROLLER #IDENTIFIER

Fig 36. Entry in either extended identifier table

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The table of ranges of Extended Identifiers must contain an even number of entries, of thesame form as in the individual Extended Identifier table. Like the Individual Extended
table, the Extended Range must be arranged in ascending numerical order. The first andsecond (3rd and 4th …) entries in the table are implicitly paired as an inclusive range ofExtended addresses, such that any received address that falls in the inclusive range is
received (accepted). Software must maintain the table to consist of such word pairs.
There is no facility to receive messages to Extended identifiers using the fullCAN method.
Five address registers point to the boundaries between the tables in Acceptance Filter
RAM: fullCAN Standard addresses, Standard Individual addresses, Standard address
ranges, Extended Individual addresses, and Extended address ranges. These tables
must be consecutive in memory. The start of each of the latter four tables is implicitly theend of the preceding table. The end of the Extended range table is given in an End of
Tables register. If the start address of a table equals the start of the next table or the End
Of Tables register, that table is empty.
When the Receive side of a CAN controller has received a complete Identifier, it signals
the Acceptance Filter of this fact. The Acceptance Filter responds to this signal, and reads
the Controller number, the size of the Identifier, and the Identifier itself from the Controller.
It then proceeds to search its RAM to determine whether the message should be received
or ignored.
If fullCAN mode is enabled and the CAN controller signals that the current message
contains a Standard identifier, the Acceptance Filter first searches the table of identifiers
for which reception is to be done in fullCAN mode. Otherwise, or if the AF doesn’t find amatch in the fullCAN table, it searches its individual Identifier table for the size of Identifier
signalled by the CAN controller. If it finds an equal match, the AF signals the CAN
controller to retain the message, and provides it with an ID Index value to store in its
Receive Frame Status register.
If the Acceptance Filter does not find a match in the appropriate individual Identifier table,
it then searches the Identifier Range table for the size of Identifier signalled by the CAN
controller. If the AF finds a match to a range in the table, it similarly signals the CAN
controller to retain the message, and provides it with an ID Index value to store in its
Receive Frame Status register. If the Acceptance Filter does not find a match in either theindividual or Range table for the size of Identifier received, it signals the CAN controller todiscard/ignore the received message.

13. Acceptance filter registers
13.1 Acceptance Filter Mode Register (AFMR - 0xE003 C000)
The AccBP and AccOff bits of the acceptance filter mode register are used for putting theacceptance filter into the Bypass and Off mode. The eFCAN bit of the mode register canbe used to activate a FullCAN mode enhancement for received 11-bit CAN ID messages.

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Table 218. Acceptance Filter Mode Register (AFMR - address 0xE003 C000) bit description
Bit

SymbolValue Description

Reset
Value

0

AccOff[2]1

if AccBP is 0, the Acceptance Filter is not operational. All Rx
messages on all CAN buses are ignored.

1

1

AccBP[1]1

All Rx messages are accepted on enabled CAN controllers.
0
Software must set this bit before modifying the contents of any of
the registers described below, and before modifying the contentsof Lookup Table RAM in any way other than setting or clearing
Disable bits in Standard Identifier entries. When both this bit andAccOff are 0, the Acceptance filter operates to screen received
CAN Identifiers.

2eFCAN[3] 01

31:3 -

Software must read all messages for all enabled IDs on all
enabled CAN buses, from the receiving CAN controllers.

0

The Acceptance Filter itself will take care of receiving and storingmessages for selected Standard ID values on selected CAN
buses. See Section 12–15 “FullCAN mode” on page 248.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

[1]

Acceptance Filter Bypass Mode (AccBP): By setting the AccBP bit in the Acceptance Filter Mode Register,
the Acceptance filter is put into the Acceptance Filter Bypass mode. During bypass mode, the internal statemachine of the Acceptance Filter is reset and halted. All received CAN messages are accepted, andacceptance filtering can be done by software.

[2]

Acceptance Filter Off mode (AccOff): After power-upon hardware reset, the Acceptance filter will be in Off
mode, the AccOff bit in the Acceptance filter Mode register 0 will be set to 1. The internal state machine of
the acceptance filter is reset and halted. If not in Off mode, setting the AccOff bit, either by hardware or bysoftware, will force the acceptance filter into Off mode.

[3]

FullCan Mode Enhancements: A FullCan mode for received CAN messages can be enabled by setting theeFCAN bit in the acceptance filter mode register.

13.2 Section configuration registers
The 10 bit section configuration registers are used for the ID look-up table RAM to indicate
the boundaries of the different sections for explicit and group of CAN identifiers for 11 bit
CAN and 29 bit CAN identifiers, respectively. The 10 bit wide section configuration
registers allow the use of a 512x32 (2 kB) look-up table RAM. The whole ID Look-up Table
RAM is only word accessible. All five section configuration registers contain APB
addresses for the acceptance filter RAM and do not include the APB base address. A
write access to all section configuration registers is only possible during the Acceptancefilter off and Bypass modes. Read access is allowed in all acceptance filter modes.

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13.3 Standard Frame Individual Start Address Register (SFF_sa 0xE003 C004)
Table 219. Standard Frame Individual Start Address Register (SFF_sa - address
0xE003 C004) bit description
Bit

SymbolDescription

Reset
Value

1:0

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

10:2

SFF_sa[1] The start address of the table of individual Standard Identifiers in AF
0
Lookup RAM. If the table is empty, write the same value in this registerand the SFF_GRP_sa register described below. For compatibility withpossible future devices, write zeroes in bits 31:11 and 1:0 of thisregister. If the eFCAN bit in the AFMR is 1, this value also indicates thesize of the table of Standard IDs which the Acceptance Filter will searchand (if found) automatically store received messages in Acceptance
Filter RAM.

31:11 [1]Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

Write access to the look-up table section configuration registers are possible only during the Acceptancefilter bypass mode or the Acceptance filter off mode.

13.4 Standard Frame Group Start Address Register (SFF_GRP_sa 0xE003 C008)
Table 220. Standard Frame Group Start Address Register (SFF_GRP_sa - address
0xE003 C008) bit description
Bit

SymbolDescription

Reset
Value

1:0

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

11:2

SFF_GRP_sa[1] The start address of the table of grouped Standard Identifiers in 0
AF Lookup RAM. If the table is empty, write the same value inthis register and the EFF_sa register described below. The
largest value that should be written to this register is 0x800, when
only the Standard Individual table is used, and the last word
(address 0x7FC) in AF Lookup Table RAM is used. For
compatibility with possible future devices, please write zeroes inbits 31:12 and 1:0 of this register.

31:12 [1]Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

Write access to the look-up table section configuration registers are possible only during the Acceptancefilter bypass mode or the Acceptance filter off mode.

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13.5 Extended Frame Start Address Register (EFF_sa - 0xE003 C00C)
Table 221. Extended Frame Start Address Register (EFF_sa - address 0xE003 C00C) bit
description
Bit

SymbolDescription

Reset
Value

1:0

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

10:2

EFF_sa[1] The start address of the table of individual Extended Identifiers in AF 0
Lookup RAM. If the table is empty, write the same value in this registerand the EFF_GRP_sa register described below. The largest value thatshould be written to this register is 0x800, when both Extended Tables
are empty and the last word (address 0x7FC) in AF Lookup Table RAM
is used. For compatibility with possible future devices, please write
zeroes in bits 31:11 and 1:0 of this register.

31:11 [1]Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

Write access to the look-up table section configuration registers are possible only during the Acceptancefilter bypass mode or the Acceptance filter off mode.

13.6 Extended Frame Group Start Address Register (EFF_GRP_sa 0xE003 C010)
Table 222. Extended Frame Group Start Address Register (EFF_GRP_sa - address
0xE003 C010) bit description
Bit

SymbolDescription

Reset
Value

1:0

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

11:2

Eff_GRP_sa[1] The start address of the table of grouped Extended Identifiers in
0
AF Lookup RAM. If the table is empty, write the same value in thisregister and the ENDofTable register described below. The largest
value that should be written to this register is 0x800, when thistable is empty and the last word (address 0x7FC) in AF Lookup
Table RAM is used. For compatibility with possible future devices,
please write zeroes in bits 31:12 and 1:0 of this register.

31:12 [1]Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

Write access to the look-up table section configuration registers are possible only during the Acceptancefilter bypass mode or the Acceptance filter off mode.

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13.7 End of AF Tables Register (ENDofTable - 0xE003 C014)
Table 223. End of AF Tables Register (ENDofTable - address 0xE003 C014) bit description
Bit

SymbolDescription

Reset
Value

1:0

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

11:2

EndofTable The address above the last active address in the last active AF table. 0
For compatibility with possible future devices, please write zeroes inbits 31:12 and 1:0 of this register.

[1]

If the eFCAN bit in the AFMR is 0, the largest value that should be
written to this register is 0x800, which allows the last word (address
0x7FC) in AF Lookup Table RAM to be used.
If the eFCAN bit in the AFMR is 1, this value marks the start of thearea of Acceptance Filter RAM, into which the Acceptance Filter willautomatically receive messages for selected IDs on selected CAN
buses. In this case, the maximum value that should be written to thisregister is 0x800 minus 6 times the value in SFF_sa. This allows 12
bytes of message storage between this address and the end of
Acceptance Filter RAM, for each Standard ID that is specified
between the start of Acceptance Filter RAM, and the next active AF
table.
31:12 [1]Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

Write access to the look-up table section configuration registers are possible only during the Acceptancefilter bypass mode or the Acceptance filter off mode.

13.8 Status registers
The look-up table error status registers, the error addresses, and the flag register provide
information if a programming error in the look-up table RAM during the ID screening was
encountered. The look-up table error address and flag register have only read access. If
an error is detected, the LUTerror flag is set, and the LUTerrorAddr register provides theinformation under which address during an ID screening an error in the look-up table was
encountered. Any read of the LUTerrorAddr Filter block can be used for a look-up tableinterrupt.

13.9 LUT Error Address Register (LUTerrAd - 0xE003 C018)
Table 224. LUT Error Address Register (LUTerrAd - address 0xE003 C018) bit description
Bit

SymbolDescription

Reset
Value

1:0

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

10:2

LUTerrAd It the LUT Error bit (below) is 1, this read-only field contains the address 0
in AF Lookup Table RAM, at which the Acceptance Filter encounteredan error in the content of the tables.

31:11 -

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

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13.10 LUT Error Register (LUTerr - 0xE003 C01C)
Table 225. LUT Error Register (LUTerr - address 0xE003 C01C) bit description
Bit

Symbol Description

Reset
Value

0

LUTerrThis read-only bit is set to 1 if the Acceptance Filter encounters an error 0
in the content of the tables in AF RAM. It is cleared when software reads
the LUTerrAd register. This condition is ORed with the “other CAN”
interrupts from the CAN controllers, to produce the request for a VIC
interrupt channel.

31:1

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

13.11 Global FullCANInterrupt Enable register (FCANIE - 0xE003 C020)
A write access to the Global FullCAN Interrupt Enable register is only possible when the
Acceptance Filter is in the off mode.
Table 226. Global FullCAN Enable register (FCANIE - address 0xE003 C020) bit description
Bit

Symbol Description

Reset
Value

0

FCANIE Global FullCAN Interrupt Enable. When 1, this interrupt is enabled.

0

31:1

-

NA

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

13.12 FullCAN Interrupt and Capture registers (FCANIC0 - 0xE003 C024 and
FCANIC1 - 0xE003 C028)
For detailed description on these two registers, see Section 12–15.2 “FullCAN interrupts”.
Table 227. FullCAN Interrupt and Capture register 0 (FCANIC0 - address 0xE003 C024) bit
description
Bit

SymbolDescription

Reset
Value

0

IntPnd0

FullCan Interrupt Pending bit 0.

0...

IntPndx (0<x<31)

FullCan Interrupt Pending bit x.

031

IntPnd31

FullCan Interrupt Pending bit 31.

0

Table 228. FullCAN Interrupt and Capture register 1 (FCANIC1 - address 0xE003 C028) bit
description
Bit

SymbolDescription

Reset
Value

0

IntPnd32

FullCan Interrupt Pending bit 32.

0...

IntPndx (32<x<63)

FullCan Interrupt Pending bit x.

031

IntPnd63

FullCan Interrupt Pending bit 63.

0

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14. Configuration and search algorithm
The CAN Identifier Look-up Table Memory can contain explicit identifiers and groups of
CAN identifiers for Standard and Extended CAN Frame Formats. They are organized as asorted list or table with an increasing order of the Source CAN Channel (SCC) together
with CAN Identifier in each section.
SCC value equals CAN_controller - 1, i.e., SCC = 0 matches CAN1 and SCC = 1
matches CAN2.
Every CAN identifier is linked to an ID Index number. In case of a CAN Identifier match,the matching ID Index is stored in the Identifier Index of the Frame Status Register(CANRFS) of the according CAN Controller.

14.1 Acceptance filter search algorithm
The identifier screening process of the acceptance filter starts in the following order:
1. FullCAN (Standard Frame Format) Identifier Section
2. Explicit Standard Frame Format Identifier Section
3. Group of Standard Frame Format Identifier Section
4. Explicit Extended Frame Format Identifier Section
5. Group of Extended Frame Format Identifier Section
Note: Only activated sections will take part in the screening process.
In cases where equal message identifiers of same frame format are defined in more than
one section, the first match will end the screening process for this identifier.
For example, if the same Source CAN Channel in conjunction with the identifier is definedin the FullCAN, the Explicit Standard Frame Format and the Group of Standard Frame
Format Identifier Sections, the screening will already be finished with the match in the
FullCAN section.
In the example of Figure 12–37, Identifiers with their Source CAN Channel have been
defined in the FullCAN, Explicit and Group of Standard Frame Format Identifier Sections.
This example corresponds to a LPC2290 compatible part that would have 6 CAN
controllers.

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Messagedisable bit

Messagedisable bit

Index 0, 1

SCC = 10

ID = 0x5A

SCC = 10...

Index 2, 3

SCC = 20...

SCC = 30...

Index 4, 5

SCC = 40...

SCC = 50...

Index 6, 7

SCC = 60...

SCC = 60...

Index 8, 9

SCC = 10

ID = 0x5A

SCC = 10...

Index 10, 11

SCC = 20...

SCC = 30...

Index 12, 13

SCC = 40...

SCC = 50...

Index 14

SCC = 10

ID = 0x5A

SCC = 10

ID = 0x5F
0x5A

Index 15

SCC = 20...

SCC = 20...

FullCAN
ExplicitStandard
Frame
FormatIdentifier
SectionExplicitStandard
Frame
FormatIdentifier
SectionGroup ofStandard
Frame
FormatIdentifier
SectionFig 37. ID Look-up table example explaining the search algorithm

The identifier 0x5A of the CAN Controller 1 with the Source CAN Channel SCC = 1, isdefined in all three sections. With this configuration incoming CAN messages on CAN
Controller 1 with a 0x5A identifier will find a match in the FullCAN section.
It is possible to disable the ‘0x5A identifier’ in the FullCAN section. With that, thescreening process would be finished with the match in the Explicit Identifier Section.
The first group in the Group Identifier Section has been defined in that way, that incoming
CAN messages with identifiers of 0x5A up to 0x5F are accepted on CAN Controller 1 with
the Source CAN Channel SCC = 1. As stated above, the identifier 0x5A would find amatch already in the FullCAN or in the Explicit Identifier section if enabled. The rest of thedefined identifiers of this group (0x5B to 0x5F) will find a match in this Group Identifier
Section.
This way the user can switch dynamically between different filter modes for same
identifiers.

15. FullCAN mode
The FullCAN mode is based on capabilities provided by the CAN Gateway module used in
the LPC2000 family of products. This block uses the Acceptance Filter to provide filteringfor both CAN channels.
The concept of the CAN Gateway block is mainly based on a BasicCAN functionality. This
concept fits perfectly in systems where a gateway is used to transfer messages ormessage data between different CAN channels. A BasicCAN device is generating a

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receive interrupt whenever a CAN message is accepted and received. Software has tomove the received message out of the receive buffer from the according CAN controller
into the user RAM.
To cover dashboard like applications where the controller typically receives data fromseveral CAN channels for further processing, the CAN Gateway block was extended by aso-called FullCAN receive function. This additional feature uses an internal message
handler to move received FullCAN messages from the receive buffer of the according
CAN controller into the FullCAN message object data space of Look-up Table RAM.
When fullCAN mode is enabled, the Acceptance Filter itself takes care of receiving andstoring messages for selected Standard ID values on selected CAN buses, in the style of“FullCAN” controllers.
In order to set this bit and use this mode, two other conditions must be met with respect tothe contents of Acceptance Filter RAM and the pointers into it:• The Standard Frame Individual Start Address Register (SFF_sa) must be greater thanor equal to the number of IDs for which automatic receive storage is to be done, times
two. SFF_sa must be rounded up to a multiple of 4 if necessary.

• The EndOfTable register must be less than or equal to 0x800 minus 6 times the
SFF_sa value, to allow 12 bytes of message storage for each ID for which automatic
receive storage will be done.
When these conditions are met and eFCAN is set:

• The area between the start of Acceptance Filter RAM and the SFF_sa address, isused for a table of individual Standard IDs and CAN Controller/bus identification,sorted in ascending order and in the same format as in the Individual Standard ID
table (see Figure 12–34 “Entry in FullCAN and individual standard identifier tables” onpage 240). Entries can be marked as “disabled” as in the other Standard tables. If
there are an odd number of “FullCAN” ID’s, at least one entry in this table must be somarked.

• The first (SFF_sa)/2 IDindex values are assigned to these automatically-stored ID’s.
That is, IDindex values stored in the Rx Frame Status Register, for IDs not handled inthis way, are increased by (SFF_sa)/2 compared to the values they would have wheneFCAN is 0.

• When a Standard ID is received, the Acceptance Filter searches this table before theStandard Individual and Group tables.

• When a message is received for a controller and ID in this table, the Acceptance filter
reads the received message out of the CAN controller and stores it in Acceptance
Filter RAM, starting at (EndOfTable) + its IDindex*12.

• The format of such messages is shown in Table 12–229.

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15.1 FullCAN message layout
Table 229. Format of automatically stored Rx messages
Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
SEM
[1:0]

0000

DLC

00000

8

7

6

5

0

F R 0000
F T
R+4Rx Data 4

Rx Data 3

Rx Data 2

Rx Data 1+8

Rx Data 8

Rx Data 7

Rx Data 6

Rx Data 5

4

3

2

1

0

ID.28 ... ID.18

The FF, RTR, and DLC fields are as described in Table 12–203.
Since the FullCAN message object section of the Look-up table RAM can be accessedboth by the Acceptance Filter and the CPU, there is a method for insuring that no CPU
reads from FullCAN message object occurs while the Acceptance Filter hardware is
writing to that object.
For this purpose the Acceptance Filter uses a 3-state semaphore, encoded with the two
semaphore bits SEM1 and SEM0 (see Table 12–229 “Format of automatically stored Rx
messages”) for each message object. This mechanism provides the CPU with information
about the current state of the Acceptance Filter activity in the FullCAN message object
section.
The semaphore operates in the following manner:
Table 230. FullCAN semaphore operation
SEM1

SEM0

activity0

1

Acceptance Filter is updating the content

1

1

Acceptance Filter has finished updating the content

00

CPU is in process of reading from the Acceptance Filter

Prior to writing the first data byte into a message object, the Acceptance Filter will write
the FrameInfo byte into the according buffer location with SEM[1:0] = 01.
After having written the last data byte into the message object, the Acceptance Filter will
update the semaphore bits by setting SEM[1:0] = 11.
Before reading a message object, the CPU should read SEM[1:0] to determine the current
state of the Acceptance Filter activity therein. If SEM[1:0] = 01, then the Acceptance Filter
is currently active in this message object. If SEM[1:0] = 11, then the message object isavailable to be read.
Before the CPU begins reading from the message object, it should clear SEM[1:0] = 00.
When the CPU is finished reading, it can check SEM[1:0] again. At the time of this final
check, if SEM[1:0] = 01 or 11, then the Acceptance Filter has updated the message object
during the time when the CPU reads were taking place, and the CPU should discard thedata. If, on the other hand, SEM[1:0] = 00 as expected, then valid data has beensuccessfully read by the CPU.
Figure 12–38 shows how software should use the SEM field to ensure that all three words
read from the message are all from the same received message.

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START

read 1st word

SEM == 01?

this message has not been
received since last check

SEM == 11?

clear SEM, write back 1st word

read 2nd and 3rd words

read 1st word

SEM == 00?

most recently read 1st, 2nd, and3rd words are from the samemessageFig 38. Semaphore procedure for reading an auto-stored message

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15.2 FullCAN interrupts
The CAN Gateway Block contains a 2 kB ID Look-up Table RAM. With this size amaximum number of 146 FullCAN objects can be defined if the whole Look-up Table RAM
is used for FullCAN objects only. Only the first 64 FullCAN objects can be configured toparticipate in the interrupt scheme. It is still possible to define more than 64 FullCAN
objects. The only difference is, that the remaining FullCAN objects will not provide a
FullCAN interrupt.
The FullCAN Interrupt Register-set contains interrupt flags (IntPndx) for (pending)
FullCAN receive interrupts. As soon as a FullCAN message is received, the according
interrupt bit (IntPndx) in the FCAN Interrupt Register gets asserted. In case that the Global
FullCAN Interrupt Enable bit is set, the FullCAN Receive Interrupt is passed to the
Vectored Interrupt Controller.
Application Software has to solve the following:
1. Index/Object number calculation based on the bit position in the FCANIC Interrupt
Register for more than one pending interrupt.
2. Interrupt priority handling if more than one FullCAN receive interrupt is pending.
The software that covers the interrupt priority handling has to assign a receive interrupt
priority to every FullCAN object. If more than one interrupt is pending, then the software
has to decide, which received FullCAN object has to be served next.
To each FullCAN object a new FullCAN Interrupt Enable bit (FCANIntxEn) is added, sothat it is possible to enable or disable FullCAN interrupts for each object individually. The
new Message Lost flag (MsgLstx) is introduced to indicate whether more than one
FullCAN message has been received since last time this message object was read by theCPU. The Interrupt Enable and the Message Lost bits reside in the existing Look-up TableRAM.

15.2.1 FullCAN message interrupt enable bit
In Figure 12–39 8 FullCAN Identifiers with their Source CAN Channel are defined in the
FullCAN, Section. The new introduced FullCAN Message Interrupt enable bit can be used
to enable for each FullCAN message an Interrupt.

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Messagedisable bit

Messagedisable bit

3
1

0

2
9

8

7

6

5 4

3

2

1

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

Index 0, 1SCC

011-bit CAN ID

SCC

011-bit CAN ID

Index 2, 3SCC

011-bit CAN ID

SCC

011-bit CAN ID

Index 4, 5SCC

011-bit CAN ID

SCC

011-bit CAN ID

Index 6, 7

SCC

011-bit CAN ID

SCC

011-bit CAN ID

New:
FullCAN
Message
Interrupt
enable bit

3

2

1

0

FullCAN
ExplicitStandard
Frame
FormatIdentifier
SectionNew:
FullCAN
Message
Interrupt
enable bit

Fig 39. FullCAN section example of the ID look-up table

15.2.2 Message lost bit and CAN channel number
Figure 12–40 is the detailed layout structure of one FullCAN message stored in the
FullCAN message object section of the Look-up Table.

APB

New:

New:

FullCANCAN

Message

Sourcelost bit

Channel

31

24

23

16

15

10

9

8

7

0

Base +

Msg_ObjAddr + 0

F
F

R
T
R

unused

S
E
M
1

S
E
M
0

unusedRX DLC

SCC

unusedID.2
8............................

Msg_ObjAddr + 4

RX Data 4

RX Data 3

RX Data 2

RX Data 1

Msg_ObjAddr + 8

RX Data 8

RX Data 7

RX Data 6

RX Data 5

ID.1
8

Fig 40. FullCAN message object layout

The new message lost bit (MsgLst) is introduced to indicate whether more than one
FullCAN message has been received since last time this message object was read. For
more information the CAN Source Channel (SCC) of the received FullCAN message isadded to Message Object.

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15.2.3 Setting the interrupt pending bits (IntPnd 63 to 0)
The interrupt pending bit (IntPndx) gets asserted in case of an accepted FullCAN
message and if the interrupt of the according FullCAN Object is enabled (enable bit
FCANIntxEn) is set).
During the last write access from the data storage of a FullCAN message object theinterrupt pending bit of a FullCAN object (IntPndx) gets asserted.

15.2.4 Clearing the interrupt pending bits (IntPnd 63 to 0)
Each of the FullCAN Interrupt Pending requests gets cleared when the semaphore bits ofa message object are cleared by Software (ARM CPU).

15.2.5 Setting the message lost bit of a FullCAN message object (MsgLost 63 to 0)
The Message Lost bit of a FullCAN message object gets asserted in case of an accepted
FullCAN message and when the FullCAN Interrupt of the same object is asserted already.
During the first write access from the data storage of a FullCAN message object the
Message Lost bit of a FullCAN object (MsgLostx) gets asserted if the interrupt pending bit
is set already.

15.2.6 Clearing the message lost bit of a FullCAN message object (MsgLost 63 to0)
The Message Lost bit of a FullCAN message object gets cleared when the FullCAN
Interrupt of the same object is not asserted.
During the first write access from the data storage of a FullCAN message object the
Message Lost bit of a FullCAN object (MsgLostx) gets cleared if the interrupt pending bit
is not set.

15.3 Set and clear mechanism of the FullCAN interrupt
Special precaution is needed for the built-in set and clear mechanism of the FullCAN
Interrupts. The following text illustrates how the already existing Semaphore Bits (seeSection 12–15.1 “FullCAN message layout” for more details) and how the new introduced
features (IntPndx, MsgLstx) will behave.

15.3.1 Scenario 1: Normal case, no message lost
Figure 12–41 below shows a typical “normal” scenario in which an accepted FullCAN
message is stored in the FullCAN Message Object Section. After storage the message isread out by Software (ARM CPU).

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Chapter 12: LPC2300 CAN1, 2

semaphore
bits

01

11

00

write
SEM

read clear
SEM SEM

IntPndx

look-uptable
accessWrite
ID, SEM

write
D1

write
D2

read
D1

read read
D2 SEM

MsgLostx

messagehandler
accessARM
processor
accessFig 41. Normal case, no messages lost

15.3.2 Scenario 2: Message lostIn this scenario a first FullCAN Message is stored and read out by Software (1st Object
write and read). In a second course a second message is stored (2nd Object write) but notread out before a third message gets stored (3rd Object write). Since the FullCAN Interruptof that Object (IntPndx) is already asserted, the Message Lost Signal gets asserted.

semaphore
bits

01

11

00

write
write write write
ID,
D1
D2 SEM
SEM

read clear
SEM SEM

01

11

11

write
read read read ID, write write write
D1
D2 SEM SEM D1
D2 SEMwrite
write write write
ID,
D1
D2 SEM
SEM

IntPndx
look-uptable
access

1st Object
write

2nd Object
write

3rd Object
write

1st Object
read

MsgLostx

messagehandler
accessARM
processor
accessFig 42. Message lost

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Chapter 12: LPC2300 CAN1, 2

15.3.3 Scenario 3: Message gets overwritten indicated by Semaphore bits
This scenario is a special case in which the lost message is indicated by the existing
semaphore bits. The scenario is entered, if during a Software read of a message object
another new message gets stored by the message handler. In this case, the FullCAN
Interrupt bit gets set for a second time with the 2nd Object write.

semaphore
bits

01

11

00

write
SEM

read clear
SEM SEM

01

11

00

IntPndx
look-uptable
accesswrite
write write
ID,
D1
D2
SEM
1st Object
write

write
ID, write write write
D2 SEMSEM D1

read read read
D1
D2 SEM

clear
SEM

read read read
D1
D2 SEM

2nd Object
write
2nd Object
read

1st Object readInterrupt Service
RoutineMsgLostx

messagehandler
accessARM
processor
accessFig 43. Message gets overwritten

15.3.4 Scenario 3.1: Message gets overwritten indicated by Semaphore bits andMessage Lost
This scenario is a sub-case to Scenario 3 in which the lost message is indicated by theexisting semaphore bits and by Message Lost.

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semaphore
bits

01

11

00

write
write write write
ID,
D1
D2 SEM
SEM

read clear
SEM SEM

01

11

00

IntPndx

look-uptable
access

1st Object
write

write
write write write
ID,
D1
D2 SEM
SEM

read read readD1 D2 SEM

clear
SEM

read read readD1 D2 SEM

2nd Object
write
2nd Object
read

1st Object readInterrupt Service
RoutineMsgLostx

messagehandler
accessARM
processor
accessFig 44. Message overwritten indicated by semaphore bits and message lost

15.3.5 Scenario 3.2: Message gets overwritten indicated by Message Lost
This scenario is a sub-case to Scenario 3 in which the lost message is indicated by
Message Lost.

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Chapter 12: LPC2300 CAN1, 2

semaphore
bits

01

11

01

11

00

write
write write write
ID,
D1
D2 SEM
SEM

clear
SEM

01

11

IntPndx

look-uptable
accesswrite
write write write readID,
D1
D2 SEM SEM
SEM
1st Object
write

2nd Object
write

read read readD1 D2 SEM

write
write write write
ID,
D1
D2 SEMSEM
3rd Object
write

1st Object
read
Interrupt Service
RoutineMsgLostx

messagehandler
accessARM
processor
accessFig 45. Message overwritten indicated by message lost

15.3.6 Scenario 4: Clearing Message Lost bit
This scenario is a special case in which the lost message bit of an object gets set during
an overwrite of a none read message object (2nd Object write). The subsequent read outof that object by Software (1st Object read) clears the pending Interrupt. The 3rd Object
write clears the Message Lost bit. Every “write ID, SEM” clears Message Lost bit if nopending Interrupt of that object is set.

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Chapter 12: LPC2300 CAN1, 2

semaphore
bits

01

11

01

11

00

write
write write write
ID,
D1
D2 SEMSEM

write
write write write
ID,
D1
D2 SEM
SEM

read clear
SEM SEM

1st Object
write

2nd Object
write

11

IntPndx

look-uptable
accessread read read
D1
D2 SEMwrite
write write write
ID,
D1
D2 SEMSEM
3rd Object
write

1st Object
read

MsgLostx

messagehandler
accessARM
processor
accessFig 46. Clearing message lost

16. Examples of acceptance filter tables and ID index values
16.1 Example 1: only one section is used
SFF_sa<
SFF_GRP_sa <EFF_sa<EFF_GRP_sa <ENDofTable
ENDofTable
ENDofTable
ENDofTable

OR
OR
OR

The start address of a section is lower than the end address of all programmed CAN
identifiers.

16.2 Example 2: all sections are used
SFF_sa<
SFF_GRP_sa <EFF_sa<EFF_GRP_sa <SFF_GRP_sa
EFF_saEFF_GRP_sa
ENDofTable

AND
AND
AND

In cases of a section not being used, the start address has to be set onto the value of thenext section start address.

16.3 Example 3: more than one but not all sections are used
If the SFF group is not used, the start address of the SFF Group Section (SFF_GRP_sa
register) has to be set to the same value of the next section start address, in this case thestart address of the Explicit SFF Section (SFF_sa register).

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Chapter 12: LPC2300 CAN1, 2

In cases where explicit identifiers as well as groups of the identifiers are programmed, a
CAN identifier search has to start in the explicit identifier section first. If no match is found,it continues the search in the group of identifier section. By this order it can be guaranteedthat in case where an explicit identifier match is found, the succeeding software candirectly proceed on this certain message whereas in case of a group of identifier matchthe succeeding software needs more steps to identify the message.

16.4 Configuration example 4
Suppose that the five Acceptance Filter address registers contain the values shown in thethird column below. In this case each table contains the decimal number of words andentries shown in the next two columns, and the ID Index field of the CANRFS register canreturn the decimal values shown in the column ID Indexes for CAN messages whose
Identifiers match the entries in that table.
Table 231. Example of Acceptance Filter Tables and ID index Values
Table

RegisterValue# Words# Entire

ID IndexesStandard Individual

SFF_sa

0x040

810

1610

0-1510Standard GroupSFF_GRP_sa

0x060

410

410

16-1910Extended Individual

EFF_sa

0x070

810

1610

20-5510Extended GroupEFF_GRP_sa

0x100

810

1610

56-5710

ENDofTable

0x110

16.5 Configuration example 5
Figure 12–47 below is a more detailed and graphic example of the address registers,
table layout, and ID Index values. It shows:• A Standard Individual table starting at the start of Acceptance Filter RAM andcontaining 26 Identifiers, followed by:• A Standard Group table containing 12 ranges of Identifiers, followed by:• An Extended Individual table containing 3 Identifiers, followed by:• An Extended Group table containing 2 ranges of Identifiers.

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Chapter 12: LPC2300 CAN1, 2000 d := 000 h := 0 0000 0000 b

look-up table RAM

APB base +addresscolumn_lower

column_upper

00d = 00h0104d = 04h23

44d = 2Ch222348d = 30h

24

25
2 6

52d = 34h

ID index #

0
1
2
3

22
23
24
25

explicit SFF table

SFF_sa26 d84d = 54h

lower_boundary 3 4 upper_boundary 34 d

88d = 58h

lower_boundary 3 5 upper_boundary 35 d

92d = 5Ch

lower_boundary 3 6 upper_boundary 36 d

100d = 64h

38

38 d

104d = 68h

39

39 d

EFF_GRP_sa 112 d := 070 h := 0 0111 0000 b

112d = 70h

lower_boundary

116d = 74h

upper_boundary

120d = 78h

lower_boundary

124d = 7Ch

upper_boundary

ENDofTable

41

41 d

42

42 d

explicit EFF table

100 d := 064 h := 0 0110 0100 bgroup EFF table

EFF_sagroup SFF table

SFF_GRP_sa 52 d := 034 h := 0 0011 0100 b

128 d := 080 h := 0 1000 0000 b

Fig 47. Detailed example of acceptance filter tables and ID index values

16.6 Configuration example 6
The Table below shows which sections and therefore which types of CAN identifiers areused and activated. The ID-Look-up Table configuration of this example is shown in
Figure 12–48.

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Table 232. Used ID-Look-up Table sections
ID-Look-up Table Section

StatusFullCANnot activated

Explicit Standard Frame Format

activated

Group of Standard Frame Format

activated

Explicit Extended Frame Format

activated

Group of Extended Frame Format

activated

Explicit standard frame format identifier section (11-bit CAN ID):
The start address of the Explicit Standard Frame Format section is defined in the SFF_sa
register with the value of 0x00. The end of this section is defined in the SFF_GRP_sa
register. In the Explicit Standard Frame Format section of the ID Look-up Table two CAN
Identifiers with their Source CAN Channels (SCC) share one 32-bit word. Not used or
disabled CAN Identifiers can be marked by setting the message disable bit.
Group of standard frame format identifier section (11-bit CAN ID):
The start address of the Group of Standard Frame Format section is defined with the
SFF_GRP_sa register with the value of 0x10. The end of this section is defined with the
EFF_sa register. In the Group of Standard Frame Format section two CAN Identifiers withthe same Source CAN Channel (SCC) share one 32-bit word and represent a range of
CAN Identifiers to be accepted. Bit 31 down to 16 represents the lower boundary and bit
15 down to 0 represents the upper boundary of the range of CAN Identifiers. All Identifierswithin this range (including the boundary identifiers) will be accepted. A whole group canbe disabled and not used by the acceptance filter by setting the message disable bit in theupper and lower boundary identifier. To provide memory space for four Groups ofStandard Frame Format identifiers, the EFF_sa register value is set to 0x20. The identifiergroup with the Index 9 of this section is not used and therefore disabled.
Explicit extended frame format identifier section (29-bit CAN ID, Figure 12–48)
The start address of the Explicit Extended Frame Format section is defined with the
EFF_sa register with the value of 0x20. The end of this section is defined with the
EFF_GRP_sa register. In the explicit Extended Frame Format section only one CAN
Identifier with its Source CAN Channel (SCC) is programmed per address line. To provide
memory space for four Explicit Extended Frame Format identifiers, the EFF_GRP_sa
register value is set to 0x30.
Group of extended frame format identifier section (29-bit CAN ID, Figure 12–48)
The start address of the Group of Extended Frame Format is defined with the
EFF_GRP_sa register with the value of 0x30. The end of this section is defined with the
End of Table address register (ENDofTable). In the Group of Extended Frame Format
section the boundaries are programmed with a pair of address lines; the first is the lower
boundary, the second the upper boundary. To provide memory space for two Groups ofExtended Frame Format Identifiers, the ENDofTable register value is set to 0x40.

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Chapter 12: LPC2300 CAN1, 2

Messagedisable bit

Messagedisable bit
Index

SFF_sa= 0x00

SFF_GRP_sa= 0x10

EFF_sa= 0x20

EFF_GRP_sa= 0x30

ExplicitStandard
Frame... Format
Identifier
SectionGroup ofStandard
Frame...Format
Identifier
Section

SCC 0

MSB
ID28

0

LSB
ID18

SCC

0

MSB
ID28

1

LSB
ID18

SCC 0

MSB
ID28

2

LSB
ID18

SCC

0

MSB
ID28

3

LSB
ID18

SCC 0

MSB
ID28

4

LSB
ID18

SCC

0

MSB
ID28

5

LSB
ID18

SCC 0

MSB
ID28

6

LSB
ID18

SCC

1

MSB
ID28

Disabled, 7

LSB
ID18

SCC 0

MSB
ID28

8

LSB
ID18

SCC

0

MSB
ID28

8

LSB
ID18

SCC 1

MSB
ID28

Disabled, 9

LSB
ID18

SCC

1

MSB
ID28

Disabled, 9

LSB
ID18

Disabled
Group 9

SCC 1

MSB
ID28

10

LSB
ID18

SCC

1

MSB
ID28

10

LSB
ID18

Group 10

SCC 0

MSB
ID28

11

LSB
ID18

SCC

0

MSB
ID28

11

LSB
ID18

Group 11SCC
Explicit
Extended
Frame
FormatIdentifier
Section

MSB
ID28
MSB

SCC ID28MSB

SCC ID28MSB

SCC ID28
MSBGroup of
Extended
Frame
FormatIdentifier
SectionSCC ID28MSB

SCC ID28MSB

SCC ID28MSB

SCC ID28

12

LSB
ID0

13

LSB
ID0

14

LSB
ID0

15

LSB
ID0

16

LSB
ID0

16

LSB
ID0

17

LSB
ID0

17

LSB
ID0

Group 8Group 16

Group 17

ENDofTable= 0x40

Fig 48. ID Look-up table configuration example (no FullCAN)

16.7 Configuration example 7
The Table below shows which sections and therefore which types of CAN identifiers areused and activated. The ID-Look-up Table configuration of this example is shown in
Figure 12–49.
This example uses a typical configuration in which FullCAN as well as Explicit Standard
Frame Format messages are defined. As described in Section 12–14.1 “Acceptance filter
search algorithm”, acceptance filtering takes place in a certain order. With the enabled
FullCAN section, the identifier screening process of the acceptance filter starts always in
the FullCAN section first, before it continues with the rest of enabled sections.e disabled.
Table 233. Used ID-Look-up Table sections
ID-Look-up Table Section

StatusFullCANactivated and enabled

Explicit Standard Frame Format

activated

Group of Standard Frame Format

not activated

Explicit Extended Frame Format

not activatedGroup of Extended Frame Format

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FullCAN explicit standard frame format identfier section (11-bit CAN ID)
The start address of the FullCAN Explicit Standard Frame Format Identifier section is(automatically) set to 0x00. The end of this section is defined in the SFF_sa register. In the
FullCAN ID section only identifiers of FullCAN Object are stored for acceptance filtering.
In this section two CAN Identifiers with their Source CAN Channels (SCC) share one
32-bit word. Not used or disabled CAN Identifiers can be marked by setting the message
disable bit. The FullCAN Object data for each defined identifier can be found in the
FullCAN Message Object section. In case of an identifier match during the acceptancefilter process, the received FullCAN message object data is moved from the Receive
Buffer of the appropriate CAN Controller into the FullCAN Message Object section. To
provide memory space for eight FullCAN, Explicit Standard Frame Format identifiers, theSFF_sa register value is set to 0x10. The identifier with the Index 1 of this section is not
used and therefore disabled.
Explicit standard frame format identifier section (11-bit CAN ID)
The start address of the Explicit Standard Frame Format section is defined in the SFF_sa
register with the value of 0x10. The end of this section is defined in the End of Table
address register (ENDofTable). In the explicit Standard Frame Format section of the ID
Look-up Table two CAN Identifiers with their Source CAN Channel (SCC) share one 32-bit
word. Not used or disabled CAN Identifiers can be marked by setting the message disablebit. To provide memory space for eight Explicit Standard Frame Format identifiers, theENDofTable register value is set to 0x20.
FullCAN message object data section
The start address of the FullCAN Message Object Data section is defined with the
ENDofTable register. The number of enabled FullCAN identifiers is limited to the available
memory space in the FullCAN Message Object Data section. Each defined FullCAN
Message needs three address lines for the Message Data in the FullCAN Message Object
Data section. The FullCAN Message Object section is organized in that way, that eachIndex number of the FullCAN Identifier section corresponds to a Message Object Numberin the FullCAN Message Object section.

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Chapter 12: LPC2300 CAN1, 2

Message
Disable bit

FullCAN
ExplicitStandard
Frame... Format
Identifier
SectionSFF_sa= 0x10

ENDofTable =SFF_GRP_sa =EFF_sa =EFF_GRP_sa =
0x20

SCC

MSB
ID28
MSB
0 1
ID28

SCC

0 1

SCC

SCC
SCC

ExplicitStandard
Frame...Format
Identifier
Section

SCC
SCC
SCC

0 0

MSB
ID28
MSB
0 1
ID28
MSB
0 0
ID28
MSB
0 0
ID28
MSB
0 0
ID28
MSB
0 0
ID28

FullCANInterrupt
Enable bit

FullCANInterrupt
Enable bit

Message
Disable bit
Index

2

LSB
ID18
LSB
ID18

4

LSB
ID18

SCC

0 0

6

LSB
ID18

SCC

0 0

SCC

0 0

SCC

0 0

SCC

0 0

SCC

0 0

0

12

LSB
ID18
LSB
ID18
LSB
ID18

14

LSB
ID18

8
10

SCC

1 1 MSB

SCC

0 0

ID28
MSB
ID28
MSB
ID28
MSB
ID28
MSB
ID28
MSB
ID28
MSB
ID28
MSB
ID28

3

LSB
ID18
LSB
ID18

5

LSB
ID18

7

LSB
ID18

Disabled, 1

13

LSB
ID18
LSB
ID18
LSB
ID18

15

LSB
ID18

9
11

FF RTR SEM DLC CAN-ID
FullCAN
Message
ObjectsectionSectionRXDATA 4, 3, 2, 1

Message Object
Data 0RXDATA 8, 7, 6, 5
No Message Data, disabled.
No Message Data, disabled.

Message Object
Data 1

No Message Data, disabled.
FF RTR SEM DLC CAN-ID
RXDATA 4, 3, 2, 1

Message Object
Data 2RXDATA 8, 7, 6, 5

Fig 49. ID Look-up table configuration example (FullCAN activated and enabled)

16.8 Look-up table programming guidelines
All identifier sections of the ID Look-up Table have to be programmed in such a way, thateach active section is organized as a sorted list or table with an increasing order of the
Source CAN Channel (SCC) together with CAN Identifier in each section.
SCC value equals CAN_controller - 1, i.e., SCC = 0 matches CAN1 and SCC = 1
matches CAN2.
In cases, where a syntax error in the ID Look-up Table is encountered, the Look-up Table
address of the incorrect line is made available in the Look-up Table Error Address
Register (LUTerrAd).
The reporting process in the Look-up Table Error Address Register (LUTerrAd) is a“run-time” process. Only those address lines with syntax error are reported, which werepassed through the acceptance filtering process.
The following general rules for programming the Look-up Table apply:
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Chapter 12: LPC2300 CAN1, 2• Each section has to be organized as a sorted list or table with an increasing order of
the Source CAN Channel (SCC) in conjunction with the CAN Identifier (there is no
exception for disabled identifiers).

• The upper and lower bound in a Group of Identifiers definition has to be from thesame Source CAN Channel.

• To disable a Group of Identifiers the message disable bit has to be set for both, theupper and lower bound.

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UM10211
Chapter 13: USB device controller
Rev. 01 — 6 July 2007

User manual

1. Introduction
The Universal Serial Bus (USB) is a four-wire bus that supports communication between ahost and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by thehost controller.
The host schedules transactions in 1 ms frames. Each frame contains a Start-Of-Frame(SOF) marker and transactions that transfer data to or from device endpoints. Each device
can have a maximum of 16 logical or 32 physical endpoints. There are four types oftransfers defined for the endpoints. Control transfers are used to configure the device.
Interrupt transfers are used for periodic data transfer. Bulk transfers are used when therate of transfer is not critical. Isochronous transfers have guaranteed delivery time but noerror correction.
For more information on the Universal Serial Bus, see the USB Implementers Forumwebsite.
The USB device controller on the LPC23xx enables full-speed (12 Mb/s) data exchangewith a USB host controller.
Table 234. USB related acronyms, abbreviations, and definitions used in this chapter
Acronym/abbreviation Description
AHB

Advanced High-performance bus

ATLE

Auto Transfer Length Extraction

ATX

Analog TransceiverDD

DMA Descriptor

DDP

DMA Description Pointer

DMA

Direct Memory Access

EOP

End-Of-Packet

EP

Endpoint

EP_RAM

Endpoint RAM

FS

Full Speed

LED

Light Emitting DiodeLS

Low Speed

MPS

Maximum Packet Size

NAK

Negative Acknowledge

PLL

Phase Locked LoopRAM

Random Access Memory

SOF

Start-Of-Frame

SIE

Serial Interface Engine

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Chapter 13: LPC2300 USB device

Table 234. USB related acronyms, abbreviations, and definitions used in this chapter
Acronym/abbreviation Description
SRAM

Synchronous RAM

UDCA

USB Device Communication Area

USB

Universal Serial Bus

2. Features• Fully compliant with the USB 2.0 specification (full speed).
• Supports 32 physical (16 logical) endpoints.
• Supports Control, Bulk, Interrupt and Isochronous endpoints.
• Scalable realization of endpoints at run time.
• Endpoint maximum packet size selection (up to USB maximum specification) bysoftware at run time.

• Supports SoftConnect and GoodLink features.
• Supports DMA transfers on all non-control endpoints.
• Allows dynamic switching between CPU controlled and DMA modes.
• Double buffer implementation for Bulk and Isochronous endpoints.

3. Fixed endpoint configuration
Table 13–235 shows the supported endpoint configurations. Endpoints are realized andconfigured at run time using the Endpoint realization registers, documented in Section
13–8.5 “Endpoint realization registers”.
Table 235. Fixed endpoint configuration
Logicalendpoint

Physical
endpoint

Endpoint type

Direction

Packet size (bytes)

Double buffer00ControlOut8, 16, 32, 64

No

0

1

ControlIn8, 16, 32, 64

No

1

2

Interrupt

Out

1 to 64No

1

3Interrupt

In

1 to 64

No

2

4

Bulk

Out

8, 16, 32, 64

Yes

2

5

Bulk

In

8, 16, 32, 64

Yes

3

6

IsochronousOut

1 to 1023

Yes

3

7

IsochronousIn

1 to 1023

Yes

4

8

Interrupt

Out

1 to 64No

49Interrupt

In

1 to 64

No

5

10

Bulk

Out

8, 16, 32, 64

Yes

5

11

Bulk

In

8, 16, 32, 64

Yes

6

12

IsochronousOut

1 to 1023

Yes

6

13

IsochronousIn

1 to 1023

Yes

7

14

Interrupt

Out

1 to 64No

715Interrupt

In

1 to 64

No

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Table 235. Fixed endpoint configuration
Logicalendpoint

Physical
endpoint

Endpoint type

Direction

Packet size (bytes)

Double buffer

8

16

Bulk

Out

8, 16, 32, 64

Yes

8

17

Bulk

In

8, 16, 32, 64

Yes

9

18

IsochronousOut

1 to 1023

Yes

9

19

IsochronousIn

1 to 1023

Yes

10

20

Interrupt

Out

1 to 64

No

10

21

Interrupt

In

1 to 64

No

11

22

Bulk

Out

8, 16, 32, 64

Yes

11

23

Bulk

In

8, 16, 32, 64

Yes

12

24

IsochronousOut

1 to 1023

Yes

12

25

IsochronousIn

1 to 1023

Yes

13

26

Interrupt

Out

1 to 64

No

13

27

Interrupt

In

1 to 64

No

14

28

Bulk

Out

8, 16, 32, 64

Yes

14

29

Bulk

In

8, 16, 32, 64

Yes

15

30

Bulk

Out

8, 16, 32, 64

Yes

15

31

Bulk

In

8, 16, 32, 64

Yes

4. Functional description
The architecture of the USB device controller is shown below in Figure 13–50.

BUS
MASTER
INTERFACE

VBUS
DMA
ENGINE

USB_CONNECT,
USB_CONNECT1(
USB_CONNECT2(REGISTERINTERFACE

registerinterface(AHB slave)

USB DEVICEBLOCK

EP_RAMACCESSCONTROL

EP_RAM(4K)

SERIAL
INTERFACE
ENGINEUSB ATX

AHB BUSDMA interface(AHB master)

USB_D+,
USB_D+1(1),USB_D-1(1)
USB_D-,
USB_D-1(1),USB_D-2(1)
USB_UP_LED,
USB_UP_LED1(1),USB_UP_LED2(1)(1) LPC2378 only

Fig 50. USB device controller block diagram

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4.1 Analog transceiver
The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX
sends/receives the bi-directional D+ and D- signals of the USB bus.

4.2 Serial Interface Engine (SIE)
The SIE implements the full USB protocol layer. It is completely hardwired for speed andneeds no firmware intervention. It handles transfer of data between the endpoint buffers in
EP_RAM and the USB bus. The functions of this block include: synchronization patternrecognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation,
PID verification/generation, address recognition, and handshake evaluation/generation.

4.3 Endpoint RAM (EP_RAM)
Each endpoint buffer is implemented as an SRAM based FIFO. The SRAM dedicated forthis purpose is called the EP_RAM. Each realized endpoint has a reserved space in the
EP_RAM. The total EP_RAM space required depends on the number of realized
endpoints, the maximum packet size of the endpoint, and whether the endpoint supports
double buffering.

4.4 EP_RAM access control
The EP_RAM Access Control logic handles transfer of data from/to the EP_RAM and thethree sources that can access it: the CPU (via the Register Interface), the SIE, and theDMA Engine.

4.5 DMA engine and bus master interface
When enabled for an endpoint, the DMA Engine transfers data between RAM on the AHB
bus and the endpoint’s buffer in EP_RAM. A single DMA channel is shared between all
endpoints. When transferring data, the DMA Engine functions as a master on the AHB
bus through the bus master interface.

4.6 Register interface
The Register Interface allows the CPU to control the operation of the USB Device
Controller. It also provides a way to write transmit data to the controller and read receive
data from the controller.

4.7 SoftConnect
The connection to the USB is accomplished by bringing D+ (for a full-speed device) HIGH
through a 1.5 kOhm pull-up resistor. The SoftConnect feature can be used to allow
software to finish its initialization sequence before deciding to establish connection to theUSB. Re-initialization of the USB bus connection can also be performed without having to
unplug the cable.
To use the SoftConnect feature, the CONNECT signal should control an external switchthat connects the 1.5 kOhm resistor between D+ and +3.3V. Software can then control the
CONNECT signal by writing to the CON bit using the SIE Set Device Status command.

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4.8 GoodLink
Good USB connection indication is provided through GoodLink technology. When thedevice is successfully enumerated and configured, the LED indicator will be permanently
ON. During suspend, the LED will be OFF.
This feature provides a user-friendly indicator on the status of the USB device. It is a
useful field diagnostics tool to isolate faulty equipment.
To use the GoodLink feature the UP_LED signal should control an LED. The UP_LED
signal is controlled using the SIE Configure Device command.

5. Operational overview
Transactions on the USB bus transfer data between device endpoints and the host. The
direction of a transaction is defined with respect to the host. OUT transactions transfer
data from the host to the device. IN transactions transfer data from the device to the host.
All transactions are initiated by the host controller.
For an OUT transaction, the USB ATX receives the bi-directional D+ and D- signals of theUSB bus. The Serial Interface Engine (SIE) receives the serial data from the ATX andconverts it into a parallel data stream. The parallel data is written to the corresponding
endpoint buffer in the EP_RAM.
For IN transactions, the SIE reads the parallel data from the endpoint buffer in EP_RAM,
converts it into serial data, and transmits it onto the USB bus using the USB ATX.
Once data has been received or sent, the endpoint buffer can be read or written. How thisis accomplished depends on the endpoint’s type and operating mode. The two operating
modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode.
In Slave mode, the CPU transfers data between RAM and the endpoint buffer using theRegister Interface. See Section 13–12 “Slave mode operation” for a detailed description ofthis mode.
In DMA mode, the DMA transfers data between RAM and the endpoint buffer. See
Section 13–13 “DMA operation” for a detailed description of this mode.

6. Pin description
Table 236. USB external interface
Name

Direction

Description

VBUS

I

VBUS status input. When this function is not enabled
via its corresponding PINSEL register, it is driven
HIGH internally.

USB_CONNECT,
USB_CONNECT1[1],USB_CONNECT2[1]O

SoftConnect control signal.

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Table 236. USB external interface
Name

Direction

Description

USB_UP_LED,
USB_UP_LED1[1],USB_UP_LED2[1]O

GoodLink LED control signal.

USB_D+, USB_D+1[1],USB_D+2[1]I/O

Positive differential data.

USB_D-, USB_D-1[1],USB_D-2[1]I/O

Negative differential data.

[1]

LPC2378 only.

For the LPC2378 only, the USB interface can be routed to either USB port1 (using
USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D−1) or USB port2 (using
USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D−2) to allow for more versatile pin
multiplexing (see Section 13–8.1.1 “USB Port Select register (USBPortSel - 0xFFE0 C110
– LPC2378 only)”).

7. Clocking and power management
This section describes the clocking and power management features of the USB Device
Controller.

7.1 Power requirements
The USB protocol insists on power management by the device. This becomes very critical
if the device draws power from the bus (bus-powered device). The following constraints
should be met by a bus-powered device:
1. A device in the non-configured state should draw a maximum of 100 mA from the bus.
2. A configured device can draw only up to what is specified in the Max Power field of
the configuration descriptor. The maximum value is 500 mA.
3. A suspended device can draw a maximum of 500 μA.

7.2 Clocks
The USB device controller clocks are shown in Table 13–237
Table 237. USB device controller clock sources
Clock source

Description

AHB master clock

Clock for the AHB master bus interface and DMA

AHB slave clock

Clock for the AHB slave interface

usbclk

48 MHz clock from the USB clock divider, used to recover the
12 MHz clock from the USB bus

7.3 Power management support
To help conserve power, the USB device controller automatically disables the AHB masterclock and usbclk when not in use.

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When the USB Device Controller goes into the suspend state (bus is idle for 3 ms), theusbclk input to the device controller is automatically disabled, helping to conserve power.
However, if software wishes to access the device controller registers, usbclk must be
active. To allow access to the device controller registers while in the suspend state, theUSBClkCtrl and USBClkSt registers are provided.
When software wishes to access the device controller registers, it should first ensure
usbclk is enabled by setting DEV_CLK_EN in the USBClkCtrl register, and then poll thecorresponding DEV_CLK_ON bit in USBClkSt until set. Once set, usbclk will remain
enabled until DEV_CLK_EN is cleared by software.
When a DMA transfer occurs, the device controller automatically turns on the AHB masterclock. Once asserted, it remains active for a minimum of 2 ms (2 frames), to help ensurethat DMA throughput is not affected by turning off the AHB master clock. 2 ms after thelast DMA access, the AHB master clock is automatically disabled to help conserve power.
If desired, software also has the capability of forcing this clock to remain enabled using the
USBClkCtrl register.
Note that the AHB slave clock is always enabled as long as the PCUSB bit of PCONP isset. When the device controller is not in use, all of the device controller clocks may bedisabled by clearing PCUSB.
The USB_NEED_CLK signal is used to facilitate going into and waking up from chip
Power Down mode. USB_NEED_CLK is asserted if any of the bits of the USBClkSt
register are asserted.
After entering the suspend state with DEV_CLK_EN and AHB_CLK_EN cleared, the
DEV_CLK_ON and AHB_CLK_ON will be cleared when the corresponding clock turns off.
When both bits are zero, USB_NEED_CLK will be low, indicating that the chip can be put
into Power Down mode by writing to the PCON register. The status of USB_NEED_CLK
can be read from the USBIntSt register.
Any bus activity in the suspend state will cause the USB_NEED_CLK signal to beasserted. When the USB is configured to be a wakeup source from Power Down
(USBWAKE bit set in the INTWAKE register), the assertion of USB_NEED_CLK causes
the chip to wake up from Power Down mode.

7.4 Remote wake-up
The USB device controller supports software initiated remote wake-up. Remote wake-up
involves resume signaling on the USB bus initiated from the device. This is done byclearing the SUS bit in the SIE Set Device Status register. Before writing into the register,
all the clocks to the device controller have to be enabled using the USBClkCtrl register.

8. Register description
Table 13–238 shows the USB Device Controller registers directly accessible by the CPU.
The Serial Interface Engine (SIE) has other registers that are indirectly accessible via the
SIE command registers. See Section 13–10 “Serial interface engine commanddescription” for more info.

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Table 238. USB device register map
AccessReset value[1]Address

USB Port Select

R/W

0x0000 0000

0xFFE0 C110

USBClkCtrl

USB Clock Control

R/W

0x0000 0000

0xFFE0 CFF4

USBClkSt

USB Clock Status

RO

0x0000 0000

0xFFE0 CFF8

Name

Description

Port select register (LPC2378 only)
USBPortSel
Clock control registers

Device interrupt registers
USBIntSt

USB Interrupt Status

R/W

0x8000 0000

0xE01F C1C0

USBDevIntSt

USB Device Interrupt Status

RO

0x0000 0010

0xFFE0 C200

USBDevIntEn

USB Device Interrupt Enable

R/W

0x0000 0000

0xFFE0 C204

USBDevIntClr

USB Device Interrupt Clear

WO

0x0000 0000

0xFFE0 C208

USBDevIntSet

USB Device Interrupt Set

WO

0x0000 0000

0xFFE0 C20C

USBDevIntPri

USB Device Interrupt Priority

WO

0x00

0xFFE0 C22C

Endpoint interrupt registers
USBEpIntSt

USB Endpoint Interrupt Status

RO

0x0000 0000

0xFFE0 C230

USBEpIntEn

USB Endpoint Interrupt Enable

R/W

0x0000 0000

0xFFE0 C234

USBEpIntClr

USB Endpoint Interrupt Clear

WO

0x0000 0000

0xFFE0 C238

USBEpIntSet

USB Endpoint Interrupt Set

WO

0x0000 0000

0xFFE0 C23C

USBEpIntPri

USB Endpoint Priority

WO[2]0x0000 0000

0xFFE0 C240

USB Realize Endpoint

R/W

0x0000 0003

0xFFE0 C244

USBEpIndUSB Endpoint Index

WO[2]0x0000 0000

0xFFE0 C248

USBMaxPSize

USB MaxPacketSize

R/W

0x0000 0008

0xFFE0 C24C

USB Receive Data

RO

0x0000 0000

0xFFE0 C218

USBRxPLen

USB Receive Packet LengthRO

0x0000 0000

0xFFE0 C220

USBTxData

USB Transmit Data

WO[2]0x0000 0000

0xFFE0 C21C

USBTxPLen

USB Transmit Packet Length

WO[2]0x0000 0000

0xFFE0 C224

USBCtrl

USB Control

R/W

0x0000 0000

0xFFE0 C228

Endpoint realization registers
USBReEpUSB transfer registers
USBRxData

SIE Command registers
USBCmdCode

USB Command CodeWO[2]0x0000 0000

0xFFE0 C210

USBCmdData

USB Command Data

RO

0x0000 0000

0xFFE0 C214

DMA registers
USBDMARSt

USB DMA Request Status

RO

0x0000 0000

0xFFE0 C250

USBDMARClr

USB DMA Request Clear

WO[2]0x0000 0000

0xFFE0 C254

USBDMARSet

USB DMA Request Set

WO[2]0x0000 0000

0xFFE0 C258

USBUDCAH

USB UDCA Head

R/W

0x0000 0000

0xFFE0 C280

USBEpDMASt

USB Endpoint DMA Status

RO

0x0000 0000

0xFFE0 C284

USBEpDMAEn

USB Endpoint DMA Enable

WO[2]0x0000 0000

0xFFE0 C288

USBEpDMADis

USB Endpoint DMA Disable

WO[2]0x0000 0000

0xFFE0 C28C

USBDMAIntSt

USB DMA Interrupt Status

RO

0x0000 0000

0xFFE0 C290

USBDMAIntEn

USB DMA Interrupt Enable

R/W

0x0000 0000

0xFFE0 C294

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Table 238. USB device register map
Name

Description

AccessReset value[1]Address

USBEoTIntSt

USB End of Transfer Interrupt Status

RO

0x0000 0000

0xFFE0 C2A0

USB End of Transfer Interrupt Clear

WO[2]0x0000 0000

0xFFE0 C2A4

USBEoTIntSet

USB End of Transfer Interrupt Set

WO[2]0x0000 0000

0xFFE0 C2A8

USBNDDRIntSt

USB New DD Request Interrupt Status

RO

0x0000 0000

0xFFE0 C2AC

USB New DD Request Interrupt Clear

WO[2]0x0000 0000

0xFFE0 C2B0

USBNDDRIntSet

USB New DD Request Interrupt Set

WO[2]0x0000 0000

0xFFE0 C2B4

USBSysErrIntSt

USB System Error Interrupt Status

RO

0x0000 0000

0xFFE0 C2B8

USBSysErrIntClr

USB System Error Interrupt Clear

WO[2]0x0000 0000

0xFFE0 C2BC

USB System Error Interrupt Set

WO[2]0x0000 0000

0xFFE0 C2C0

USBEoTIntClr

USBNDDRIntClr

USBSysErrIntSet[1]

Reset value reflects the data stored in used bits only. It does not include reserved bits content.

[2]

Reading WO register will return an invalid value.

8.1 Port select register
8.1.1 USB Port Select register (USBPortSel - 0xFFE0 C110 – LPC2378 only)This register selects the USB port pins the USB device signals are routed to. USBPortSelis a read/write register.
Table 239. USB Port Select register (USBPortSel - address 0xFFE0 C110) bit description
Bit

SymbolValue

Description

Reset value

1:0

PORTSEL0x0

The USB device controller signals are mapped to
the U1 port: USB_CONNECT1, USB_UP_LED1,
USB_D+1, USB_D-1.

00x3

The USB device controller signals are mapped to
the U2 port:USB_CONNECT2, USB_UP_LED2,
USB_D+2, USB_D-2.

-

Reserved, user software should not write ones toNAreserved bits. The value read from a reserved bit is
not defined.

31:2

-

8.2 Clock control registers
8.2.1 USB Clock Control register (USBClkCtrl - 0xFFE0 CFF4)
This register controls the clocking of the USB Device Controller. Whenever software
wants to access the device controller registers, both DEV_CLK_EN and AHB_CLK_EN
must be set. The PORTSEL_CLK_EN bit need only be set when accessing the
USBPortSel register.
The software does not have to repeat this exercise for every register access, provided thatthe corresponding USBClkCtrl bits are already set. Note that this register is functional only
when the PCUSB bit of PCONP is set; when PCUSB is cleared, all clocks to the device
controller are disabled irrespective of the contents of this register. USBClkCtrl is aread/write register.

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Table 240. USBClkCtrl register (USBClkCtrl - address 0xFFE0 CFF4) bit description
Bit

SymbolDescription

Reset
value

0

-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is
not defined.

NA1

DEV_CLK_EN

Device clock enable. Enables the usbclk input to the 0
device controller

2-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is
not defined.

NA

3

PORTSEL_CLK_EN

Port select register clock enable(LPC2378 only).

NA

4

AHB_CLK_EN

AHB clock enable

0

31:5

-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is
not defined.

NA

8.2.2 USB Clock Status register (USBClkSt - 0xFFE0 CFF8)
This register holds the clock availability status. The bits of this register are ORed together
to form the USB_NEED_CLK signal. When enabling a clock via USBClkCtrl, software
should poll the corresponding bit in USBClkSt. If it is set, then software can go ahead withthe register access. Software does not have to repeat this exercise for every access,provided that the USBClkCtrl bits are not disturbed. USBClkSt is a read only register.
Table 241. USB Clock Status register (USBClkSt - 0xFFE0 CFF8) bit description
Bit

SymbolDescription

Reset
value

0

-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is
not defined.

NA1

DEV_CLK_ON

Device clock on. The usbclk input to the device
controller is active.

0

2

-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is
not defined.

NA

3

PORTSEL_CLK_ON

Port select register clock on (LPC2378 only).

NA

4

AHB_CLK_ON

AHB clock on.

0

31:5

-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is
not defined.

NA

8.3 Device interrupt registers
8.3.1 USB Interrupt Status register (USBIntSt - 0xE01F C1C0)
The USB Device Controller has three interrupt lines. This register allows software to
determine their status with a single read operation. All three interrupt lines are ORed
together to a single channel of the vectored interrupt controller. This register also contains
the USB_NEED_CLK status and EN_USB_INTS control bits. USBIntSt is a read/write
register.
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Table 242. USB Interrupt Status register (USBIntSt - address 0xE01F C1C0) bit description
Bit

SymbolDescription

Reset
value

0

USB_INT_REQ_LP

Low priority interrupt line status. This bit is read only.

01

USB_INT_REQ_HP

High priority interrupt line status. This bit is read only.

02

USB_INT_REQ_DMA

DMA interrupt line status. This bit is read only.

0

7:3

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

8

USB_NEED_CLK

0
USB need clock indicator. This bit is set to 1 when USB activity or achange of state on the USB data pins is detected, and it indicates that a
PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK
becomes one, it it resets to zero 5 ms after the last packet has been
received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt
has occurred. A change of this bit from 0 to 1 can wake up the
microcontroller if activity on the USB bus is selected to wake up the partfrom the Power Down mode (see Section 4–7.7 “Interrupt Wakeup
Register (INTWAKE - 0xE01F C144)” for details). Also see Section
4–5.10 “PLL and Power down mode” and Section 4–7.8 “Power Control
for Peripherals register (PCONP - 0xE01F COC4)” for considerations
about the PLL and invoking the Power Down mode. This bit is read only.

30:9

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

31

EN_USB_INTS

Enable all USB interrupts. When this bit is cleared, the Vectored
Interrupt Controller does not see the ORed output of the USB interrupt
lines.

1

8.3.2 USB Device Interrupt Status register (USBDevIntSt - 0xFFE0 C200)
The USBDevIntSt register holds the status of each interrupt. A 0 indicates no interrupt and1 indicates the presence of the interrupt. USBDevIntSt is a read only register.
Table 243. USB Device Interrupt Status register (USBDevIntSt - address 0xFFE0 C200) bit allocation
Reset value: 0x0000 0000
Bit

31

30

29

28

27

26

25

24

Symbol

-

-

-

-

-

-

-

-

Bit

23

22

21

20

19

18

17

16

Symbol

-

-

-

-

-

-

-

-

Bit

15

14

13

12

11

10

9

8

Symbol

-

-

-

-

-

-

ERR_INTEP_RLZED

Bit
Symbol

7

6

5

4

3

2

1

0

TxENDPKTRx
ENDPKT

CDFULLCCEMPTY

DEV_STATEP_SLOW

EP_FAST

FRAME

Table 244. USB Device Interrupt Status register (USBDevIntSt - address 0xFFE0 C200) bit description
Bit

SymbolDescription

Reset value

0

FRAME

The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers.

01

EP_FAST

Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit isset, the corresponding endpoint interrupt will be routed to this bit.

02

EP_SLOW

Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is
not set, the corresponding endpoint interrupt will be routed to this bit.

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Table 244. USB Device Interrupt Status register (USBDevIntSt - address 0xFFE0 C200) bit description
Bit

SymbolDescription

3

DEV_STAT0
Set when USB Bus reset, USB suspend change or Connect change event occurs.
Refer to Section 13–10.6 “Set Device Status (Command: 0xFE, Data: write 1 byte)” on
page 303.

4

CCEMPTY

The command code register (USBCmdCode) is empty (New command can be written). 1

5

CDFULL

Command data register (USBCmdData) is full (Data can be read now).

6

RxENDPKT The current packet in the endpoint buffer is transferred to the CPU.

0

7

TxENDPKTThe number of data bytes transferred to the endpoint buffer equals the number ofbytes programmed in the TxPacket length register (USBTxPLen).

08

EP_RLZED

Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize 0
register (USBMaxPSize) is updated and the corresponding operation is completed.

9

ERR_INT

Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13–10.9 0“Read Error Status (Command: 0xFB, Data: read 1 byte)” on page 305

31:10 -

Reset value0

Reserved, user software should not write ones to reserved bits. The value read from a NA
reserved bit is not defined.

8.3.3 USB Device Interrupt Enable register (USBDevIntEn - 0xFFE0 C204)
Writing a one to a bit in this register enables the corresponding bit in USBDevIntSt togenerate an interrupt on one of the interrupt lines when set. By default, the interrupt isrouted to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME
interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of
USBDevIntPri. USBDevIntEn is a read/write register.
Table 245. USB Device Interrupt Enable register (USBDevIntEn - address 0xFFE0 C204) bit allocation
Reset value: 0x0000 0000
Bit

31

30

29

28

27

26

25

24

Symbol

-

-

-

-

-

-

-

-

Bit

23

22

21

20

19

18

17

16

Symbol

-

-

-

-

-

-

-

-

Bit

15

14

13

12

11

10

9

8

Symbol

-

-

-

-

-

-

ERR_INTEP_RLZED

Bit

7

6

5

4

3

2

1

0

TxENDPKTRx
ENDPKT

CDFULLCCEMPTY

DEV_STATEP_SLOW

EP_FAST

FRAME

SymbolTable 246. USB Device Interrupt Enable register (USBDevIntEn - address 0xFFE0 C204) bit description
Bit

Symbol

Value

31:0

See
0
USBDevIntEn 1
bit allocationtable above

Description

Reset value

No interrupt is generated.

0

An interrupt will be generated when the corresponding bit in the Device
Interrupt Status (USBDevIntSt) register (Table 13–243) is set. By default,
the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally,
either the EP_FAST or FRAME interrupt may be routed to the
USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.

8.3.4 USB Device Interrupt Clear register (USBDevIntClr - 0xFFE0 C208)
Writing one to a bit in this register clears the corresponding bit in USBDevIntSt. Writing azero has no effect.
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Remark: Before clearing the EP_SLOW or EP_FAST interrupt bits, the corresponding
endpoint interrupts in USBEpIntSt should be cleared.
USBDevIntClr is a write only register.
Table 247. USB Device Interrupt Clear register (USBDevIntClr - address 0xFFE0 C208) bit allocation
Reset value: 0x0000 0000
Bit

31

30

29

28

27

26

25

24

Symbol

-

-

-

-

-

-

-

-

Bit

23

22

21

20

19

18

17

16

Symbol

-

-

-

-

-

-

-

-

Bit

15

14

13

12

11

10

9

8

Symbol

-

-

-

-

-

-

ERR_INTEP_RLZED

Bit

7

6

5

4

3

2

1

0

TxENDPKTRx
ENDPKT

CDFULLCCEMPTY

DEV_STATEP_SLOW

EP_FAST

FRAME

SymbolTable 248. USB Device Interrupt Clear register (USBDevIntClr - address 0xFFE0 C208) bit description
Bit

Symbol31:0

See
0
USBDevIntClr 1
bit allocationtable above

Value

Description

Reset value

No effect.

0

The corresponding bit in USBDevIntSt (Section 13–8.3.2) is cleared.

8.3.5 USB Device Interrupt Set register (USBDevIntSet - 0xFFE0 C20C)
Writing one to a bit in this register sets the corresponding bit in the USBDevIntSt. Writing azero has no effect
USBDevIntSet is a write only register.
Table 249. USB Device Interrupt Set register (USBDevIntSet - address 0xFFE0 C20C) bit allocation
Reset value: 0x0000 0000
Bit

31

30

29

28

27

26

25

24

Symbol

-

-

-

-

-

-

-

-

Bit

23

22

21

20

19

18

17

16

Symbol

-

-

-

-

-

-

-

-

Bit

15

14

13

12

11

10

9

8

Symbol

-

-

-

-

-

-

ERR_INTEP_RLZED

Bit

7

6

5

4

3

2

1

0

TxENDPKTRx
ENDPKT

CDFULLCCEMPTY

DEV_STATEP_SLOW

EP_FAST

FRAME

SymbolTable 250. USB Device Interrupt Set register (USBDevIntSet - address 0xFFE0 C20C) bit description
Bit

Symbol

Value

31:0

See
0
USBDevIntSet 1
bit allocationtable above

Description

Reset value

No effect.

0

The corresponding bit in USBDevIntSt (Section 13–8.3.2) is set.

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8.3.6 USB Device Interrupt Priority register (USBDevIntPri - 0xFFE0 C22C)
Writing one to a bit in this register causes the corresponding interrupt to be routed to the
USB_INT_REQ_HP interrupt line. Writing zero causes the interrupt to be routed to the
USB_INT_REQ_LP interrupt line. Either the EP_FAST or FRAME interrupt can be routed
to USB_INT_REQ_HP, but not both. If the software attempts to set both bits to one, nointerrupt will be routed to USB_INT_REQ_HP. USBDevIntPri is a write only register.
Table 251. USB Device Interrupt Priority register (USBDevIntPri - address 0xFFE0 C22C) bit description
Bit

SymbolValue

Description

Reset value

0

FRAME

0

FRAME interrupt is routed to USB_INT_REQ_LP.

0

1

FRAME interrupt is routed to USB_INT_REQ_HP.

0

EP_FAST interrupt is routed to USB_INT_REQ_LP.

1

EP_FAST interrupt is routed to USB_INT_REQ_HP.

-

Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.

1
7:2

EP_FAST-

0NA

8.4 Endpoint interrupt registers
The registers in this group facilitate handling of endpoint interrupts. Endpoint interrupts areused in Slave mode operation.

8.4.1 USB Endpoint Interrupt Status register (USBEpIntSt - 0xFFE0 C230)
Each physical non-isochronous endpoint is represented by a bit in this register to indicatethat it has generated an interrupt. All non-isochronous OUT endpoints generate aninterrupt when they receive a packet without an error. All non-isochronous IN endpoints
generate an interrupt when a packet is successfully transmitted, or when a NAK
handshake is sent on the bus and the interrupt on NAK feature is enabled (see Section
13–10.3 “Set Mode (Command: 0xF3, Data: write 1 byte)” on page 302). A bit set to one inthis register causes either the EP_FAST or EP_SLOW bit of USBDevIntSt to be set
depending on the value of the coreesponding bit of USBEpDevIntPri. USBEpIntSt is aread only register.
Note that for Isochronous endpoints, handling of packet data is done when the FRAME
interrupt occurs.
Table 252. USB Endpoint Interrupt Status register (USBEpIntSt - address 0xFFE0 C230) bit allocation
Reset value: 0x0000 0000
Bit
SymbolBit
SymbolBit
SymbolBit
Symbol

31

30

29

28

27

26

25

24

EP15TX

EP15RX

EP14TX

EP14RX

EP13TX

EP13RX

EP12TX

EP12RX

23

22

21

20

19

18

17

16

EP11TX

EP11RX

EP10TX

EP10RX

EP9TX

EP9RX

EP8TX

EP8RX

15

14

13

12

11

10

9

8

EP7TX

EP7RX

EP6TX

EP6RX

EP5TX

EP5RX

EP4TX

EP4RX

7

6

5

4

3

2

1

0

EP3TX

EP3RX

EP2TX

EP2RX

EP1TX

EP1RX

EP0TX

EP0RX

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Table 253. USB Endpoint Interrupt Status register (USBEpIntSt - address 0xFFE0 C230) bit description
Bit

SymbolDescription

Reset value

0

EP0RX

Endpoint 0, Data Received Interrupt bit.

0

1

EP0TX

Endpoint 0, Data Transmitted Interrupt bit or sent a NAK.

0

2

EP1RX

Endpoint 1, Data Received Interrupt bit.

0

3

EP1TX

Endpoint 1, Data Transmitted Interrupt bit or sent a NAK.

0

4

EP2RX

Endpoint 2, Data Received Interrupt bit.

0

5

EP2TX

Endpoint 2, Data Transmitted Interrupt bit or sent a NAK.

0

6

EP3RX

Endpoint 3, Isochronous endpoint.

NA

7

EP3TX

Endpoint 3, Isochronous endpoint.

NA

8

EP4RX

Endpoint 4, Data Received Interrupt bit.

0

9

EP4TX

Endpoint 4, Data Transmitted Interrupt bit or sent a NAK.

0

10

EP5RX

Endpoint 5, Data Received Interrupt bit.

0

11

EP5TX

Endpoint 5, Data Transmitted Interrupt bit or sent a NAK.

0

12

EP6RX

Endpoint 6, Isochronous endpoint.

NA

13

EP6TX

Endpoint 6, Isochronous endpoint.

NA

14

EP7RX

Endpoint 7, Data Received Interrupt bit.

0

15

EP7TX

Endpoint 7, Data Transmitted Interrupt bit or sent a NAK.

0

16

EP8RX

Endpoint 8, Data Received Interrupt bit.

0

17

EP8TX

Endpoint 8, Data Transmitted Interrupt bit or sent a NAK.

0

18

EP9RX

Endpoint 9, Isochronous endpoint.

NA

19

EP9TX

Endpoint 9, Isochronous endpoint.

NA

20

EP10RX

Endpoint 10, Data Received Interrupt bit.

021

EP10TX

Endpoint 10, Data Transmitted Interrupt bit or sent a NAK.

022

EP11RX

Endpoint 11, Data Received Interrupt bit.

023

EP11TX

Endpoint 11, Data Transmitted Interrupt bit or sent a NAK.

024

EP12RX

Endpoint 12, Isochronous endpoint.

NA

25

EP12TX

Endpoint 12, Isochronous endpoint.

NA

26

EP13RX

Endpoint 13, Data Received Interrupt bit.

027

EP13TX

Endpoint 13, Data Transmitted Interrupt bit or sent a NAK.

028

EP14RX

Endpoint 14, Data Received Interrupt bit.

029

EP14TX

Endpoint 14, Data Transmitted Interrupt bit or sent a NAK.

030

EP15RX

Endpoint 15, Data Received Interrupt bit.

031

EP15TX

Endpoint 15, Data Transmitted Interrupt bit or sent a NAK.

08.4.2 USB Endpoint Interrupt Enable register (USBEpIntEn - 0xFFE0 C234)
Setting a bit to 1 in this register causes the corresponding bit in USBEpIntSt to be set
when an interrupt occurs for the associated endpoint. Setting a bit to 0 causes thecorresponding bit in USBDMARSt to be set when an interrupt occurs for the associatedendpoint. USBEpIntEn is a read/write register.

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Table 254. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0xFFE0 C234) bit allocation
Reset value: 0x0000 0000
Bit
SymbolBit
SymbolBit
SymbolBit
Symbol

31

30

29

28

27

26

25

24

EP15TX

EP15RX

EP14TX

EP14RX

EP13TX

EP13RX

EP12TX

EP12RX

23

22

21

20

19

18

17

16

EP11TX

EP11RX

EP10TX

EP10RX

EP9TX

EP9RX

EP8TX

EP8RX

15

14

13

12

11

10

9

8

EP7TX

EP7RX

EP6TX

EP6RX

EP5TX

EP5RX

EP4TX

EP4RX

7

6

5

4

3

2

1

0

EP3TX

EP3RX

EP2TX

EP2RX

EP1TX

EP1RX

EP0TX

EP0RX

Table 255. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0xFFE0 C234) bit description
Bit

SymbolValue

Description

Reset value

31:0

See
USBEpIntEn
bit allocationtable above

0

The corresponding bit in USBDMARSt is set when an interrupt occurs forthis endpoint.

01

The corresponding bit in USBEpIntSt is set when an interrupt
occurs for this endpoint. Implies Slave mode for this endpoint.

8.4.3 USB Endpoint Interrupt Clear register (USBEpIntClr - 0xFFE0 C238)
Writing a one to this a bit in this register causes the SIE Select Endpoint/Clear Interrupt
command to be executed (Table 13–299) for the corresponding physical endpoint. Writing
zero has no effect. Before executing the Select Endpoint/Clear Interrupt command, the
CDFULL bit in USBDevIntSt is cleared by hardware. On completion of the command, the
CDFULL bit is set, USBCmdData contains the status of the endpoint, and thecorresponding bit in USBEpIntSt is cleared.
Notes:• When clearing interrupts using USBEpIntClr, software should wait for CDFULL to be
set to ensure the corresponding interrupt has been cleared before proceeding.

• While setting multiple bits in USBEpIntClr simultaneously is possible, it is notrecommended; only the status of the endpoint corresponding to the least significant
interrupt bit cleared will be available at the end of the operation.

• Alternatively, the SIE Select Endpoint/Clear Interrupt command can be directly
invoked using the SIE command registers, but using USBEpIntClr is recommended
because of its ease of use.
Each physical endpoint has its own reserved bit in this register. The bit field definition is
the same as that of USBEpIntSt shown in Table 13–252 . USBEpIntClr is a write only
register.
Table 256. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0xFFE0 C238) bit allocation
Reset value: 0x0000 0000
Bit
SymbolBit
Symbol

31

30

29

28

27

26

25

24

EP15TX

EP15RX

EP14TX

EP14RX

EP13TX

EP13RX

EP12TX

EP12RX

23

22

21

20

19

18

17

16

EP11TX

EP11RX

EP10TX

EP10RX

EP9TX

EP9RX

EP8TX

EP8RX

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Bit
SymbolBit
Symbol

15

14

13

12

11

10

9

8

EP7TX

EP7RX

EP6TX

EP6RX

EP5TX

EP5RX

EP4TX

EP4RX

7

6

5

4

3

2

1

0

EP3TX

EP3RX

EP2TX

EP2RX

EP1TX

EP1RX

EP0TX

EP0RX

Table 257. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0xFFE0 C238) bit description
Bit

SymbolValue

Description

Reset value

31:0

See
USBEpIntClr
bit allocationtable above0

No effect.

01

Clears the corresponding bit in USBEpIntSt, by executing the SIE SelectEndpoint/Clear Interrupt command for this endpoint.

8.4.4 USB Endpoint Interrupt Set register (USBEpIntSet - 0xFFE0 C23C)
Writing a one to a bit in this register sets the corresponding bit in USBEpIntSt. Writing zero
has no effect. Each endpoint has its own bit in this register. USBEpIntSet is a write only
register.
Table 258. USB Endpoint Interrupt Set register (USBEpIntSet - address 0xFFE0 C23C) bit allocation
Reset value: 0x0000 0000
Bit
SymbolBit
SymbolBit
SymbolBit
Symbol

31

30

29

28

27

26

25

24

EP15TX

EP15RX

EP14TX

EP14RX

EP13TX

EP13RX

EP12TX

EP12RX

23

22

21

20

19

18

17

16

EP11TX

EP11RX

EP10TX

EP10RX

EP9TX

EP9RX

EP8TX

EP8RX

15

14

13

12

11

10

9

8

EP7TX

EP7RX

EP6TX

EP6RX

EP5TX

EP5RX

EP4TX

EP4RX

7

6

5

4

3

2

1

0

EP3TX

EP3RX

EP2TX

EP2RX

EP1TX

EP1RX

EP0TX

EP0RX

Table 259. USB Endpoint Interrupt Set register (USBEpIntSet - address 0xFFE0 C23C) bit description
Bit

SymbolValue

Description

Reset value

31:0

See
USBEpIntSet
bit allocationtable above0

No effect.

0

1

Sets the corresponding bit in USBEpIntSt.

8.4.5 USB Endpoint Interrupt Priority register (USBEpIntPri - 0xFFE0 C240)
This register determines whether an endpoint interrupt is routed to the EP_FAST or
EP_SLOW bits of USBDevIntSt. If a bit in this register is set to one, the interrupt is routed
to EP_FAST, if zero it is routed to EP_SLOW. Routing of multiple endpoints to EP_FAST
or EP_SLOW is possible.
Note that the USBDevIntPri register determines whether the EP_FAST interrupt is routed
to the USB_INT_REQ_HP or USB_INT_REQ_LP interrupt line.
USBEpIntPri is a write only register.

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Table 260. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0xFFE0 C240) bit allocation
Reset value: 0x0000 0000
Bit
SymbolBit
SymbolBit
SymbolBit
Symbol

31

30

29

28

27

26

25

24

EP15TX

EP15RX

EP14TX

E14RX

EP13TX

EP13RX

EP12TX

EP12RX

23

22

21

20

19

18

17

16

EP11TX

EP11RX

EP10TX

EP10RX

EP9TX

EP9RX

EP8TX

EP8RX

15

14

13

12

11

10

9

8

EP7TX

EP7RX

EP6TX

EP6RX

EP5TX

EP5RX

EP4TX

EP4RX

7

6

5

4

3

2

1

0

EP3TX

EP3RX

EP2TX

EP2RX

EP1TX

EP1RX

EP0TX

EP0RX

Table 261. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0xFFE0 C240) bit description
Bit

SymbolValue

Description

Reset value

31:0

See
USBEpIntPri
bit allocationtable above

0

The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt

01

The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt

8.5 Endpoint realization registers
The registers in this group allow realization and configuration of endpoints at run time.

8.5.1 EP RAM requirements
The USB device controller uses a RAM based FIFO for each endpoint buffer. The RAM
dedicated for this purpose is called the Endpoint RAM (EP_RAM). Each endpoint has
space reserved in the EP_RAM. The EP_RAM space required for an endpoint depends
on its MaxPacketSize and whether it is double buffered. 32 words of EP_RAM are used by
the device for storing the endpoint buffer pointers. The EP_RAM is word aligned but the
MaxPacketSize is defined in bytes hence the RAM depth has to be adjusted to the next
word boundary. Also, each buffer has one word header showing the size of the packet
length received.
The EP_ RAM space (in words) required for the physical endpoint can be expressed as+ 3 + 1⎞ × dbstatus
EPRAMspace = ⎛ MaxPacketSize⎝ ------------------------------------------------⎠
4

where dbstatus = 1 for a single buffered endpoint and 2 for double a buffered endpoint.

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Since all the realized endpoints occupy EP_RAM space, the total EP_RAM requirement isN

TotalEPRAMspace = 32 + ∑ EPRAMspace ( n )n=0where N is the number of realized endpoints. Total EP_RAM space should not exceed
4096 bytes (4 kB, 1 kwords).

8.5.2 USB Realize Endpoint register (USBReEp - 0xFFE0 C244)
Writing one to a bit in this register causes the corresponding endpoint to be realized.
Writing zeros causes it to be unrealized. This register returns to its reset state when a bus
reset occurs. USBReEp is a read/write register.
Table 262. USB Realize Endpoint register (USBReEp - address 0xFFE0 C244) bit allocation
Reset value: 0x0000 0003
Bit

31

30

29

28

27

26

25

24

Symbol

EP31

EP30

EP29

EP28

EP27

EP26

EP25

EP24

Bit

23

22

21

20

19

18

17

16

Symbol

EP23

EP22

EP21

EP20

EP19

EP18

EP17

EP16

Bit

15

14

13

12

11

10

9

8

Symbol

EP15

EP14

EP13

EP12

EP11

EP10

EP9

EP8

Bit

7

6

5

4

3

2

1

0

Symbol

EP7

EP6

EP5

EP4

EP3

EP2

EP1

EP0

Table 263. USB Realize Endpoint register (USBReEp - address 0xFFE0 C244) bit description
Bit

SymbolValue

Description

Reset value

0

EP0

0

Control endpoint EP0 is not realized.

1

1

Control endpoint EP0 is realized.

0Control endpoint EP1 is not realized.

1

Control endpoint EP1 is realized.

0Endpoint EPxx is not realized.

1

Endpoint EPxx is realized.

1
31:2

EP1
EPxx

1
0

On reset, only the control endpoints are realized. Other endpoints, if required, are realized
by programming the corresponding bits in USBReEp. To calculate the required EP_RAM
space for the realized endpoints, see Section 13–8.5.1.
Realization of endpoints is a multi-cycle operation. Pseudo code for endpoint realization isshown below.
Clear EP_RLZED bit in USBDevIntSt;for every endpoint to be realized,{/* OR with the existing value of the Realize Endpoint register */UM10211_1

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USBReEp |= (UInt32) ((0x1 << endpt));/* Load Endpoint index Reg with physical endpoint no.*/USBEpIn = (UInt32) endpointnumber;/* load the max packet size Register */USBEpMaxPSize = MPS;/* check whether the EP_RLZED bit in the Device Interrupt Status register is set*/
while (!(USBDevIntSt & EP_RLZED)){/* wait until endpoint realization is complete */}/* Clear the EP_RLZED bit */Clear EP_RLZED bit in USBDevIntSt;}
The device will not respond to any transactions to unrealized endpoints. The SIE
Configure Device command will only cause realized and enabled endpoints to respond totransactions. For details see Table 13–294.

8.5.3 USB Endpoint Index register (USBEpIn - 0xFFE0 C248)
Each endpoint has a register carrying the MaxPacketSize value for that endpoint. This is
in fact a register array. Hence before writing, this register is addressed through theUSBEpIn register.
The USBEpIn register will hold the physical endpoint number. Writing to USBMaxPSize
will set the array element pointed to by USBEpIn. USBEpIn is a write only register.
Table 264. USB Endpoint Index register (USBEpIn - address 0xFFE0 C248) bit description
Bit

SymbolDescription

Reset value

4:0

PHY_EP

Physical endpoint number (0-31)

0

31:5

-

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

8.5.4 USB MaxPacketSize register (USBMaxPSize - 0xFFE0 C24C)
On reset, the control endpoint is assigned the maximum packet size of 8 bytes. Other
endpoints are assigned 0. Modifying USBMaxPSize will cause the endpoint buffer
addresses within the EP_RAM to be recalculated. This is a multi-cycle process. At theend, the EP_RLZED bit will be set in USBDevIntSt (Table 13–243). USBMaxPSize arrayindexing is shown in Figure 13–51. USBMaxPSize is a read/write register.
Table 265. USB MaxPacketSize register (USBMaxPSize - address 0xFFE0 C24C) bit
description
Bit

SymbolDescription

Reset value

9:0

MPS

The maximum packet size value.

0x008[1]31:10 [1]Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

Reset value for EP0 and EP1. All other endpoints have a reset value of 0x0.

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MPS_EP0
ENDPOINT INDEXMPS_EP31

The Endpoint Index is set via the USBEpIn register. MPS_EP0 to MPS_EP31 are accessed via
the USBMaxPSize register.

Fig 51. USB MaxPacketSize register array indexing

8.6 USB transfer registers
The registers in this group are used for transferring data between endpoint buffers and
RAM in Slave mode operation. See Section 13–12 “Slave mode operation”.

8.6.1 USB Receive Data register (USBRxData - 0xFFE0 C218)
For an OUT transaction, the CPU reads the endpoint buffer data from this register. Before
reading this register, the RD_EN bit and LOG_ENDPOINT field of the USBCtrl registershould be set appropriately. On reading this register, data from the selected endpoint
buffer is fetched. The data is in little endian format: the first byte received from the USB
bus will be available in the least significant byte of USBRxData. USBRxData is a read only
register.
Table 266. USB Receive Data register (USBRxData - address 0xFFE0 C218) bit description
Bit

SymbolDescription

Reset value

31:0

RX_DATA

Data received.

0x0000 0000

8.6.2 USB Receive Packet Length register (USBRxPLen - 0xFFE0 C220)
This register contains the number of bytes remaining in the endpoint buffer for the current
packet being read via the USBRxData register, and a bit indicating whether the packet isvalid or not. Before reading this register, the RD_EN bit and LOG_ENDPOINT field of the
USBCtrl register should be set appropriately. This register is updated on each read of theUSBRxData register. USBRxPLen is a read only register.

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Table 267. USB Receive Packet Length register (USBRxPlen - address 0xFFE0 C220) bit
description
Bit

Symbol

9:0

10

11

Description

Reset
value

PKT_LNGTH -The remaining number of bytes to be read from thecurrently selected endpoint’s buffer. When this field
decrements to 0, the RxENDPKT bit will be set in
USBDevIntSt.

0

DV

Data valid. This bit is useful for isochronous endpoints.
0
Non-isochronous endpoints do not raise an interrupt whenan erroneous data packet is received. But invalid data
packet can be produced with a bus reset. For isochronous
endpoints, data transfer will happen even if an erroneous
packet is received. In this case DV bit will not be set for the
packet.

PKT_RDY

31:12 -

Value

0

Data is invalid.

1

Data is valid.

-

The PKT_LNGTH field is valid and the packet is ready forreading.

-

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

08.6.3 USB Transmit Data register (USBTxData - 0xFFE0 C21C)
For an IN transaction, the CPU writes the endpoint data into this register. Before writing tothis register, the WR_EN bit and LOG_ENDPOINT field of the USBCtrl register should be
set appropriately, and the packet length should be written to the USBTxPlen register. On
writing this register, the data is written to the selected endpoint buffer. The data is in little
endian format: the first byte sent on the USB bus will be the least significant byte of
USBTxData. USBTxData is a write only register.
Table 268. USB Transmit Data register (USBTxData - address 0xFFE0 C21C) bit description
Bit

SymbolDescription

Reset value

31:0

TX_DATA

Transmit Data.

0x0000 0000

8.6.4 USB Transmit Packet Length register (USBTxPLen - 0xFFE0 C224)
This register contains the number of bytes transferred from the CPU to the selected
endpoint buffer. Before writing data to USBTxData, software should first write the packet
length (≤ MaxPacketSize) to this register. After each write to USBTxData, hardware
decrements USBTxPLen by 4. The WR_EN bit and LOG_ENDPOINT field of the USBCtrl
register should be set to select the desired endpoint buffer before starting this process.
For data buffers larger than the endpoint’s MaxPacketSize, software should submit data inpackets of MaxPacketSize, and send the remaining extra bytes in the last packet. For
example, if the MaxPacketSize is 64 bytes and the data buffer to be transferred is oflength 130 bytes, then the software sends two 64-byte packets and the remaining 2 bytes
in the last packet. So, a total of 3 packets are sent on USB. USBTxPLen is a write only
register.

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Table 269. USB Transmit Packet Length register (USBTxPLen - address 0xFFE0 C224) bit
description
Bit

Symbol9:0

PKT_LNGTH -31:10 -

Value Description

Reset
value

The remaining number of bytes to be written to the
0x000
selected endpoint buffer. This field is decremented by 4 byhardware after each write to USBTxData. When this field
decrements to 0, the TxENDPKT bit will be set in
USBDevIntSt.

-

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

8.6.5 USB Control register (USBCtrl - 0xFFE0 C228)
This register controls the data transfer operation of the USB device. It selects the endpoint
buffer that is accessed by the USBRxData and USBTxData registers, and enables
reading and writing them. USBCtrl is a read/write register.
Table 270. USB Control register (USBCtrl - address 0xFFE0 C228) bit description
Bit

Symbol

0

RD_EN

1

5:2

Value

Reset
value

Read mode control. Enables reading data from the OUT 0
endpoint buffer for the endpoint specified in the
LOG_ENDPOINT field using the USBRxData register.
This bit is cleared by hardware when the last word of
the current packet is read from USBRxData.
0

Read mode is disabled.

1

Read mode is enabled.

WR_EN

Write mode control. Enables writing data to the IN
endpoint buffer for the endpoint specified in the
LOG_ENDPOINT field using the USBTxData register.
This bit is cleared by hardware when the number ofbytes in USBTxLen have been sent.
0

Write mode is disabled.

1

Write mode is enabled.

LOG_ENDPOINT -31:6 -

Description-0

Logical Endpoint number.

0x0

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

8.7 SIE command code registers
The SIE command code registers are used for communicating with the Serial Interface
Engine. See Section 13–10 “Serial interface engine command description” for more
information.

8.7.1 USB Command Code register (USBCmdCode - 0xFFE0 C210)
This register is used for sending the command and write data to the SIE. The commands
written here are propagated to the SIE and executed there. After executing the command,
the register is empty, and the CCEMPTY bit of USBDevIntSt register is set. See
Section 13–10 for details. USBCmdCode is a write only register.
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Table 271. USB Command Code register (USBCmdCode - address 0xFFE0 C210) bit description
Bit

SymbolValue

Description

7:0

-

-

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

15:8

CMD_PHASE

23:16

CMD_CODE/CMD_WDATA

31:24

-

Reset value

The command phase:
0x01

Read

0x02

Write

0x05

Command0x00

This is a multi-purpose field. When CMD_PHASE is
Command or Read, this field contains the code for thecommand (CMD_CODE). When CMD_PHASE is Write,
this field contains the command write data
(CMD_WDATA).
-

0x00

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

8.7.2 USB Command Data register (USBCmdData - 0xFFE0 C214)This register contains the data retrieved after executing a SIE command. When the data isready to be read, the CD_FULL bit of the USBDevIntSt register is set. See Table 13–243
for details. USBCmdData is a read only register.
Table 272. USB Command Data register (USBCmdData - address 0xFFE0 C214) bit
description
Bit

SymbolDescription

Reset value

7:0

CMD_RDATA

Command Read Data.

0x00

31:8

-

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

8.8 DMA registers
The registers in this group are used for the DMA mode of operation (see Section 13–13“DMA operation”)

8.8.1 USB DMA Request Status register (USBDMARSt - 0xFFE0 C250)
A bit in this register associated with a non-isochronous endpoint is set by hardware whenan endpoint interrupt occurs (see the description of USBEpIntSt) and the corresponding
bit in USBEpIntEn is 0. A bit associated with an isochronous endpoint is set when thecorresponding bit in USBEpIntEn is 0 and a FRAME interrupt occurs. A set bit serves asa flag for the DMA engine to start the data transfer if the DMA is enabled for thecorresponding endpoint in the USBEpDMASt register. The DMA cannot be enabled forcontrol endpoints (EP0 and EP1). USBDMARSt is a read only register.
Table 273. USB DMA Request Status register (USBDMARSt - address 0xFFE0 C250) bit allocation
Reset value: 0x0000 0000
Bit

31

30

29

28

27

26

25

24

Symbol

EP31

EP30

EP29

EP28

EP27

EP26

EP25

EP24

Bit

23

22

21

20

19

18

17

16

Symbol

EP23

EP22

EP21

EP20

EP19

EP18

EP17

EP16

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Bit

15

14

13

12

11

10

9

8

Symbol

EP15

EP14

EP13

EP12

EP11

EP10

EP9

EP8

Bit

7

6

5

4

3

2

1

0

Symbol

EP7

EP6

EP5

EP4

EP3

EP2

EP1

EP0

Table 274. USB DMA Request Status register (USBDMARSt - address 0xFFE0 C250) bit description
Bit

SymbolValue

Description

Reset value

0

EP0

0

Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0
bit must be 0).

0

1

EP1

0

Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit
must be 0).

0

31:2

EPxx

Endpoint xx (2 ≤ xx ≤ 31) DMA request.

0

[1]

0

DMA not requested by endpoint xx.

1

DMA requested by endpoint xx.

DMA can not be enabled for this endpoint and the corresponding bit in the USBDMARSt must be 0.

8.8.2 USB DMA Request Clear register (USBDMARClr - 0xFFE0 C254)
Writing one to a bit in this register will clear the corresponding bit in the USBDMARSt
register. Writing zero has no effect.
This register is intended for initialization prior to enabling the DMA for an endpoint. When
the DMA is enabled for an endpoint, hardware clears the corresponding bit in
USBDMARSt on completion of a packet transfer. Therefore, software should not clear thebit using this register while the endpoint is enabled for DMA operation.
USBDMARClr is a write only register.
The USBDMARClr bit allocation is identical to the USBDMARSt register (Table 13–273).
Table 275. USB DMA Request Clear register (USBDMARClr - address 0xFFE0 C254) bit description
Bit

SymbolValue

Description

Reset value

0

EP0

0

Control endpoint OUT (DMA cannot be enabled for this endpoint and theEP0 bit must be 0).

0

1

EP1

0

Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 0
bit must be 0).

31:2

EPxx

Clear the endpoint xx (2 ≤ xx ≤ 31) DMA request.
0

No effect.

1

Clear the corresponding bit in USBDMARSt.

08.8.3 USB DMA Request Set register (USBDMARSet - 0xFFE0 C258)
Writing one to a bit in this register sets the corresponding bit in the USBDMARSt register.
Writing zero has no effect.
This register allows software to raise a DMA request. This can be useful when switchingfrom Slave to DMA mode of operation for an endpoint: if a packet to be processed in DMA
mode arrives before the corresponding bit of USBEpIntEn is cleared, the DMA request is
not raised by hardware. Software can then use this register to manually start the DMA
transfer.
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Software can also use this register to initiate a DMA transfer to proactively fill an IN
endpoint buffer before an IN token packet is received from the host.
USBDMARSet is a write only register.
The USBDMARSet bit allocation is identical to the USBDMARSt register (Table 13–273).
Table 276. USB DMA Request Set register (USBDMARSet - address 0xFFE0 C258) bit
description
Bit

SymbolValue Description

Reset
value

0

EP0

0

Control endpoint OUT (DMA cannot be enabled for this endpoint
and the EP0 bit must be 0).

0

1

EP1

0

Control endpoint IN (DMA cannot be enabled for this endpoint
and the EP1 bit must be 0).

0

Set the endpoint xx (2 ≤ xx ≤ 31) DMA request.

0

31:2 EPxx
0

No effect.

1

Set the corresponding bit in USBDMARSt.

8.8.4 USB UDCA Head register (USBUDCAH - 0xFFE0 C280)
The UDCA (USB Device Communication Area) Head register maintains the address
where the UDCA is located in the USB RAM. Refer to Section 13–13.2 “USB device
communication area” and Section 13–13.4 “The DMA descriptor” for more details on the
UDCA and DMA descriptors. USBUDCAH is a read/write register.
Table 277. USB UDCA Head register (USBUDCAH - address 0xFFE0 C280) bit description
Bit

SymbolDescription

Reset value

6:0-

Reserved. Software should not write ones to reserved bits. The UDCA isaligned to 128-byte boundaries.

0x00

31:7

UDCA_ADDR

Start address of the UDCA.

08.8.5 USB EP DMA Status register (USBEpDMASt - 0xFFE0 C284)
Bits in this register indicate whether DMA operation is enabled for the corresponding
endpoint. A DMA transfer for an endpoint can start only if the corresponding bit is set inthis register. USBEpDMASt is a read only register.
Table 278. USB EP DMA Status register (USBEpDMASt - address 0xFFE0 C284) bit
description
Bit

SymbolValue Description

Reset
value

0

EP0_DMA_ENABLE

0Control endpoint OUT (DMA cannot be enabled forthis endpoint and the EP0_DMA_ENABLE bit mustbe 0).

0

1

EP1_DMA_ENABLE

0Control endpoint IN (DMA cannot be enabled for this 0
endpoint and the EP1_DMA_ENABLE bit must be0).
endpoint xx (2 ≤ xx ≤ 31) DMA enabled bit.

31:2 EPxx_DMA_ENABLE
0The DMA for endpoint EPxx is disabled.

1

The DMA for endpoint EPxx is enabled.

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8.8.6 USB EP DMA Enable register (USBEpDMAEn - 0xFFE0 C288)
Writing one to a bit to this register will enable the DMA operation for the corresponding
endpoint. Writing zero has no effect.The DMA cannot be enabled for control endpoints
EP0 and EP1. USBEpDMAEn is a write only register.
Table 279. USB EP DMA Enable register (USBEpDMAEn - address 0xFFE0 C288) bit
description
Bit

SymbolValue Description

Reset
value

0

EP0_DMA_ENABLE

0Control endpoint OUT (DMA cannot be enabled forthis endpoint and the EP0_DMA_ENABLE bit value
must be 0).

01EP1_DMA_ENABLE

0Control endpoint IN (DMA cannot be enabled for this 0
endpoint and the EP1_DMA_ENABLE bit must be 0).

0

No effect.

1

Enable the DMA operation for endpoint EPxx.

Endpoint xx(2 ≤ xx ≤ 31) DMA enable control bit.

31:2 EPxx_DMA_ENABLE

08.8.7 USB EP DMA Disable register (USBEpDMADis - 0xFFE0 C28C)
Writing a one to a bit in this register clears the corresponding bit in USBEpDMASt. Writing
zero has no effect on the corresponding bit of USBEpDMASt. Any write to this register
clears the internal DMA_PROCEED flag. Refer to Section 13–13.5.4 “Optimizing
descriptor fetch” for more information on the DMA_PROCEED flag. If a DMA transfer is inprogress for an endpoint when its corresponding bit is cleared, the transfer is completed
before the DMA is disabled. When an error condition is detected during a DMA transfer,the corresponding bit is cleared by hardware. USBEpDMADis is a write only register.
Table 280. USB EP DMA Disable register (USBEpDMADis - address 0xFFE0 C28C) bit
description
Bit

SymbolValue Description

Reset
value

0

EP0_DMA_DISABLE

0

Control endpoint OUT (DMA cannot be enabled for 0
this endpoint and the EP0_DMA_DISABLE bit value
must be 0).

1

EP1_DMA_DISABLE

0

Control endpoint IN (DMA cannot be enabled for0
this endpoint and the EP1_DMA_DISABLE bit value
must be 0).
Endpoint xx (2 ≤ xx ≤ 31) DMA disable control bit.

31:2 EPxx_DMA_DISABLE
0

No effect.

1

Disable the DMA operation for endpoint EPxx.

08.8.8 USB DMA Interrupt Status register (USBDMAIntSt - 0xFFE0 C290)
Each bit of this register reflects whether any of the 32 bits in the corresponding interrupt
status register are set. USBDMAIntSt is a read only register.

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Table 281. USB DMA Interrupt Status register (USBDMAIntSt - address 0xFFE0 C290) bit
description
Bit

Symbol0

EOT

Value Description
End of Transfer Interrupt bit.
02

At least one bit in the USBEoTIntSt is set.

NDDR

New DD Request Interrupt bit.

00

All bits in the USBNDDRIntSt register are 0.

1

At least one bit in the USBNDDRIntSt is set.

ERR

31:3 -

0

All bits in the USBEoTIntSt register are 0.

1
1

Reset
value

System Error Interrupt bit.

00

All bits in the USBSysErrIntSt register are 0.

1

At least one bit in the USBSysErrIntSt is set.

-

Reserved, user software should not write
ones to reserved bits. The value read from areserved bit is not defined.

NA

8.8.9 USB DMA Interrupt Enable register (USBDMAIntEn - 0xFFE0 C294)
Writing a one to a bit in this register enables the corresponding bit in USBDMAIntSt togenerate an interrupt on the USB_INT_REQ_DMA interrupt line when set. USBDMAIntEn
is a read/write register.
Table 282. USB DMA Interrupt Enable register (USBDMAIntEn - address 0xFFE0 C294) bit
description
Bit

Symbol

0

EOT

1

2

Valu
e

Reset
value

End of Transfer Interrupt enable bit.

00

The End of Transfer Interrupt is disabled.

1

The End of Transfer Interrupt is enabled.

0

The New DD Request Interrupt isdisabled.

1

The New DD Request Interrupt isenabled.

0

The System Error Interrupt is disabled.

1

The System Error Interrupt is enabled.

-

Reserved, user software should not write
ones to reserved bits. The value readfrom a reserved bit is not defined.

NDDR

New DD Request Interrupt enable bit.

ERR

31:3 -

Description

System Error Interrupt enable bit.

0

0

NA

8.8.10 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0xFFE0 C2A0)
When the DMA transfer completes for the current DMA descriptor, either normally(descriptor is retired) or because of an error, the bit corresponding to the endpoint is set inthis register. The cause of the interrupt is recorded in the DD_status field of the descriptor.
USBEoTIntSt is a read only register.

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Table 283. USB End of Transfer Interrupt Status register (USBEoTIntSt - address
0xFFE0 C2A0s) bit description
Bit

Symbol

31:0

EPxx

Value

Description

Reset
value

Endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request.

00There is no End of Transfer interrupt request for endpoint xx.

1

There is an End of Transfer Interrupt request for endpoint xx.

8.8.11 USB End of Transfer Interrupt Clear register (USBEoTIntClr - 0xFFE0 C2A4)
Writing one to a bit in this register clears the corresponding bit in the USBEoTIntSt
register. Writing zero has no effect. USBEoTIntClr is a write only register.
Table 284. USB End of Transfer Interrupt Clear register (USBEoTIntClr - address
0xFFE0 C2A4) bit description
Bit

SymbolValue Description

Reset
value

Clear endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0

31:0 EPxx
0

No effect.

1

Clear the EPxx End of Transfer Interrupt request in the
USBEoTIntSt register.

8.8.12 USB End of Transfer Interrupt Set register (USBEoTIntSet - 0xFFE0 C2A8)
Writing one to a bit in this register sets the corresponding bit in the USBEoTIntSt register.
Writing zero has no effect. USBEoTIntSet is a write only register.
Table 285. USB End of Transfer Interrupt Set register (USBEoTIntSet - address
0xFFE0 C2A8) bit description
Bit

Symbol

31:0

EPxx

Value

Description

Reset
value

Set endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 00

No effect.

1

Set the EPxx End of Transfer Interrupt request in the
USBEoTIntSt register.

8.8.13 USB New DD Request Interrupt Status register (USBNDDRIntSt - 0xFFE0
C2AC)
A bit in this register is set when a transfer is requested from the USB device and no valid
DD is detected for the corresponding endpoint. USBNDDRIntSt is a read only register.
Table 286. USB New DD Request Interrupt Status register (USBNDDRIntSt - address
0xFFE0 C2AC) bit description
Bit

Symbol

31:0

EPxx

Value

Description

Reset value

Endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request.

00There is no new DD interrupt request for endpoint xx.

1

There is a new DD interrupt request for endpoint xx.

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8.8.14 USB New DD Request Interrupt Clear register (USBNDDRIntClr - 0xFFE0
C2B0)
Writing one to a bit in this register clears the corresponding bit in the USBNDDRIntSt
register. Writing zero has no effect. USBNDDRIntClr is a write only register.
Table 287. USB New DD Request Interrupt Clear register (USBNDDRIntClr - address 0xFFE0
C2B0) bit description
Bit

SymbolValue

Description

Reset value

Clear endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request. 0

31:0 EPxx
0

No effect.

1

Clear the EPxx new DD interrupt request in the
USBNDDRIntSt register.

8.8.15 USB New DD Request Interrupt Set register (USBNDDRIntSet - 0xFFE0
C2B4)
Writing one to a bit in this register sets the corresponding bit in the USBNDDRIntSt
register. Writing zero has no effect. USBNDDRIntSet is a write only register
Table 288. USB New DD Request Interrupt Set register (USBNDDRIntSet - address 0xFFE0
C2B4) bit description
Bit

Symbol

31:0

EPxx

Value

Description

Reset value

Set endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request. 00

No effect.

1

Set the EPxx new DD interrupt request in the
USBNDDRIntSt register.

8.8.16 USB System Error Interrupt Status register (USBSysErrIntSt - 0xFFE0 C2B8)
If a system error (AHB bus error) occurs when transferring the data or when fetching or
updating the DD the corresponding bit is set in this register. USBSysErrIntSt is a read only
register.
Table 289. USB System Error Interrupt Status register (USBSysErrIntSt - address
0xFFE0 C2B8) bit description
Bit

Symbol

31:0

EPxx

Value

Description

Reset
value

Endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request.

00There is no System Error Interrupt request for endpoint xx.

1

There is a System Error Interrupt request for endpoint xx.

8.8.17 USB System Error Interrupt Clear register (USBSysErrIntClr - 0xFFE0 C2BC)
Writing one to a bit in this register clears the corresponding bit in the USBSysErrIntSt
register. Writing zero has no effect. USBSysErrIntClr is a write only register.

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Table 290. USB System Error Interrupt Clear register (USBSysErrIntClr - address
0xFFE0 C2BC) bit description
Bit

Symbol

31:0

EPxx

Value

Description

Reset
value

Clear endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request.

00

No effect.

1

Clear the EPxx System Error Interrupt request in the
USBSysErrIntSt register.

8.8.18 USB System Error Interrupt Set register (USBSysErrIntSet - 0xFFE0 C2C0)
Writing one to a bit in this register sets the corresponding bit in the USBSysErrIntSt
register. Writing zero has no effect. USBSysErrIntSet is a write only register.
Table 291. USB System Error Interrupt Set register (USBSysErrIntSet - address 0xFFE0
C2C0) bit description
Bit

Symbol

31:0

EPxx

Value

Description

Reset
value

Set endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request. 00

No effect.

1

Set the EPxx System Error Interrupt request in the
USBSysErrIntSt register.

9. Interrupt handlingThis section describes how an interrupt event on any of the endpoints is routed to the
Vectored Interrupt Controller (VIC). For a diagram showing interrupt event handling, see
Figure 13–52.
All non-isochronous OUT endpoints (control, bulk, and interrupt endpoints) generate aninterrupt when they receive a packet without an error. All non-isochronous IN endpoints
generate an interrupt when a packet has been succesfully transmitted or when a NAK
signal is sent and interrupts on NAK are enabled by the SIE Set Mode command, see
Section 13–10.3. For isochronous endpoints, a frame interrupt is generated every 1 ms.
The interrupt handling is different for Slave and DMA mode.
Slave mode
If an interrupt event occurs on an endpoint and the endpoint interrupt is enabled in theUSBEpIntEn register, the corresponding status bit in the USBEpIntSt is set. For
non-isochronous endpoints, all endpoint interrupt events are divided into two types by thecorresponding USBEpIntPri[n] registers: fast endpoint interrupt events and slow endpointinterrupt events. All fast endpoint interrupt events are ORed and routed to bit EP_FAST in
the USBDevIntSt register. All slow endpoint interrupt events are ORed and routed to the
EP_SLOW bit in USBDevIntSt.
For isochronous endpoints, the FRAME bit in USBDevIntSt is set every 1 ms.
The USBDevIntSt register holds the status of all endpoint interrupt events as well as thestatus of various other interrupts (see Section 13–8.3.2). By default, all interrupts (ifenabled in USBDevIntEn) are routed to the USB_INT_REQ_LP bit in the USBIntSt
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register to request low priority interrupt handling. However, the USBDevIntPri register canroute either the FRAME or the EP_FAST bit to the USB_INT_REQ_HP bit in the USBIntSt
register.
Only one of the EP_FAST and FRAME interrupt events can be routed to the
USB_INT_REQ_HP bit. If routing both bits to USB_INT_REQ_HP is attempted, bothinterrupt events are routed to USB_INT_REQ_LP.
Slow endpoint interrupt events are always routed directly to the USB_INT_REQ_LP bit for
low priority interrupt handling by software.
The final interrupt signal to the VIC is gated by the EN_USB_INTS bit in the USBIntSt
register. The USB interrupts are routed to VIC channel #22 only if EN_USB_INTS is set.
DMA mode
If an interrupt event occurs on a non-control endpoint and the endpoint interrupt is notenabled in the USBEpIntEn register, the corresponding status bit in the USBDMARSt is
set by hardware. This serves as a flag for the DMA engine to transfer data if DMA transfer
is enabled for the corresponding endpoint in the USBEpDMASt register.
Three types of interrupts can occur for each endpoint for data transfers in DMA mode: Endof transfer interrupt , new DD request interrupt, and system error interrupt. These interrupt
events set a bit for each endpoint in the respective registers USBEoTIntSt,
USBNDDRIntSt, and USBSysErrIntSt. The End of transfer interrupts from all endpoints
are then Ored and routed to the EOT bit in USBDMAIntSt. Likewise, all New DD request
interrupts and system error interrupt events are routed to the NDDR and ERR bits
respectively in the USBDMAStInt register.
The EOT, NDDR, and ERR bits (if enabled in USBDMAIntEn) are ORed to set the
USB_INT_REQ_DMA bit in the USBIntSt register. If the EN_USB_INTS bit is set in
USBIntSt, the interrupt is routed to VIC channel #22.

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interrupt
event onEPn

Slave mode

USBEpIntSt

from otherEndpoints
.
.
.
.

FRAME
EP_FAST
EP_SLOW

.
.
.
.

n

USBEpIntEn[n]USBDevIntSt

USBDevIntPri[0]

.
.
.
.

.
.
.
.
.
USBEpIntPri[n] ..
.

.
.
.
.

USBDevIntPri[1]ERR_INTUSBIntSt

USBDMARSt

USB_INT_REQ_HP
USB_INT_REQ_LP
USB_INT_REQ_DMA

to DMA enginento VIC
channel#22

EN_USB_INTS

USBEoTIntSTDMA Mode

0
.
.
.
.
31
USBNDDRIntSt
0

USBDMAIntSt
.
.
.
.

EOT
NDDR
ERR

31
USBSysErrIntSt
0
.
.
.
.
31

For simplicity, USBDevIntEn and USBDMAIntEn are not shown.

Fig 52. Interrupt event handling

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10. Serial interface engine command description
The functions and registers of the Serial Interface Engine (SIE) are accessed usingcommands, which consist of a command code followed by optional data bytes (read or
write action). The USBCmdCode (Table 13–271) and USBCmdData (Table 13–272)
registers are used for these accesses.
A complete access consists of two phases:
1. Command phase: the USBCmdCode register is written with the CMD_PHASE field
set to the value 0x05 (Command), and the CMD_CODE field set to the desiredcommand code. On completion of the command, the CCEMPTY bit of USBDevIntSt isset.
2. Data phase (optional): for writes, the USBCmdCode register is written with the
CMD_PHASE field set to the value 0x01 (Write), and the CMD_WDATA field set withthe desired write data. On completion of the write, the CCEMPTY bit of USBDevIntSt
is set. For reads, USBCmdCode register is written with the CMD_PHASE field set tothe value 0x02 (Read), and the CMD_CODE field set with command code the readcorresponds to. On completion of the read, the CDFULL bit of USBDevInSt will be set,
indicating the data is available for reading in the USBCmdData register. In the case ofmulti-byte registers, the least significant byte is accessed first.
An overview of the available commands is given in Table 13–292.
Here is an example of the Read Current Frame Number command (reading 2 bytes):
USBDevIntClr = 0x30;// Clear both CCEMPTY & CDFULL
USBCmdCode = 0x00F50500;// CMD_CODE=0xF5, CMD_PHASE=0x05(Command)
while (!(USBDevIntSt & 0x10)); // Wait for CCEMPTY.
USBDevIntClr = 0x10;// Clear CCEMPTY interrupt bit.
USBCmdCode = 0x00F50200;// CMD_CODE=0xF5, CMD_PHASE=0x02(Read)
while (!(USBDevIntSt & 0x20)); // Wait for CDFULL.
USBDevIntClr = 0x20;// Clear CDFULL.
CurFrameNum = USBCmdData;// Read Frame number LSB byte.
USBCmdCode = 0x00F50200;// CMD_CODE=0xF5, CMD_PHASE=0x02(Read)
while (!(USBDevIntSt & 0x20)); // Wait for CDFULL.
Temp = USBCmdData;// Read Frame number MSB byte
USBDevIntClr = 0x20;// Clear CDFULL interrupt bit.
CurFrameNum = CurFrameNum | (Temp << 8);Here is an example of the Set Address command (writing 1 byte):
USBDevIntClr = 0x10;// Clear CCEMPTY.
USBCmdCode = 0x00D00500;// CMD_CODE=0xD0, CMD_PHASE=0x05(Command)
while (!(USBDevIntSt & 0x10)); // Wait for CCEMPTY.
USBDevIntClr = 0x10;// Clear CCEMPTY.
USBCmdCode = 0x008A0100;// CMD_WDATA=0x8A(DEV_EN=1, DEV_ADDR=0xA),// CMD_PHASE=0x01(Write)
while (!(USBDevIntSt & 0x10)); // Wait for CCEMPTY.
USBDevIntClr = 0x10;// Clear CCEMPTY.

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Table 292. SIE command code table
Command nameRecipient

Code (Hex)

Data phase

Set Address

DeviceD0

Write 1 byte

Configure Device

Device

D8

Write 1 byte

Set Mode

DeviceF3

Write 1 byte

Device commands

Read Current Frame Number

DeviceF5

Read 1 or 2 bytes

Read Test Register

DeviceFD

Read 2 bytes

Set Device Status

DeviceFE

Write 1 byte

Get Device Status

DeviceFE

Read 1 byte

Get Error CodeDeviceFF

Read 1 byte

Read Error Status

DeviceFB

Read 1 byte

Endpoint 000

Read 1 byte (optional)

Endpoint 1

01

Read 1 byte (optional)

Endpoint xx

xx

Read 1 byte (optional)

Endpoint 0

40

Read 1 byte

Endpoint 1

41

Read 1 byte

Endpoint Commands
Select Endpoint

Select Endpoint/Clear Interrupt

Set Endpoint Status

Endpoint xx

xx + 40

Read 1 byte

Endpoint 0

40

Write 1 byte

Endpoint 1

41

Write 1 byte

Endpoint xx

xx + 40

Write 1 byte

Clear Buffer

Selected Endpoint

F2

Read 1 byte (optional)

Validate Buffer

Selected Endpoint

FA

None

10.1 Set Address (Command: 0xD0, Data: write 1 byte)
The Set Address command is used to set the USB assigned address and enable the(embedded) function. The address set in the device will take effect after the status stageof the control transaction. After a bus reset, DEV_ADDR is set to 0x00, and DEV_EN is
set to 1. The device will respond to packets for function address 0x00, endpoint 0 (default
endpoint).
Table 293. Device Set Address Register bit description
Bit

SymbolDescription

Reset value

6:0

DEV_ADDR

Device address set by the software. After a bus reset this field is set to
0x00.

0x00

7

DEV_EN

Device Enable. After a bus reset this bit is set to 1.

0

0: Device will not respond to any packets.
1: Device will respond to packets for function address DEV_ADDR.

10.2 Configure Device (Command: 0xD8, Data: write 1 byte)
A value of 1 written to the register indicates that the device is configured and all the
enabled non-control endpoints will respond. Control endpoints are always enabled andrespond even if the device is not configured, in the default state.

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Table 294. Configure Device Register bit description
Bit

SymbolDescription

Reset value

0

CONF_DEVICE

Device is configured. All enabled non-control endpoints will respond. Thisbit is cleared by hardware when a bus reset occurs. When set, the
UP_LED signal is driven LOW if the device is not in the suspended state(SUS=0).

7:1-

Reserved, user software should not write ones to reserved bits. The value NA
read from a reserved bit is not defined.

10.3 Set Mode (Command: 0xF3, Data: write 1 byte)
Table 295. Set Mode Register bit description
Bit

Symbol0

AP_CLK

1

2

3

4

5

6

Value Description
Always PLL Clock.

00

USB_NEED_CLK is functional; the 48 MHz clock can be
stopped when the device enters suspend state.

1

USB_NEED_CLK is fixed to 1; the 48 MHz clock cannot be
stopped when the device enters suspend state.

INAK_CI

Interrupt on NAK for Control IN endpoint.

00Only successful transactions generate an interrupt.

1

Both successful and NAKed IN transactions generate interrupts.

INAK_COInterrupt on NAK for Control OUT endpoint.

00Only successful transactions generate an interrupt.

1

Both successful and NAKed OUT transactions generateinterrupts.

INAK_IIInterrupt on NAK for Interrupt IN endpoint.

00Only successful transactions generate an interrupt.

1

Both successful and NAKed IN transactions generate interrupts.

INAK_IO[1]Interrupt on NAK for Interrupt OUT endpoints.

00Only successful transactions generate an interrupt.

1

Both successful and NAKed OUT transactions generateinterrupts.

INAK_BIInterrupt on NAK for Bulk IN endpoints.

00Only successful transactions generate an interrupt.

1

Both successful and NAKed IN transactions generate interrupts.

INAK_BO[2]Interrupt on NAK for Bulk OUT endpoints.

00Only successful transactions generate an interrupt.

1

Both successful and NAKed OUT transactions generateinterrupts.

-

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

7

-

[1]

This bit should be reset to 0 if the DMA is enabled for any of the Interrupt OUT endpoints.

[2]

This bit should be reset to 0 if the DMA is enabled for any of the Bulk OUT endpoints.

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10.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2
bytes)
Returns the frame number of the last successfully received SOF. The frame number iseleven bits wide. The frame number returns least significant byte first. In case the user isonly interested in the lower 8 bits of the frame number, only the first byte needs to be read.

• In case no SOF was received by the device at the beginning of a frame, the frame
number returned is that of the last successfully received SOF.

• In case the SOF frame number contained a CRC error, the frame number returned willbe the corrupted frame number as received by the device.

10.5 Read Test Register (Command: 0xFD, Data: read 2 bytes)
The test register is 16 bits wide. It returns the value of 0xA50F if the USB clocks (usbclk
and AHB slave clock) are running.

10.6 Set Device Status (Command: 0xFE, Data: write 1 byte)
The Set Device Status command sets bits in the Device Status Register.
Table 296. Set Device Status Register bit description
Bit

Symbol

0

CON

1

2

Value Description

0
The Connect bit indicates the current connect status of thedevice. It controls the CONNECT output pin, used for
SoftConnect. Reading the connect bit returns the current connect
status. This bit is cleared by hardware when the VBUS status input
is LOW for more than 3 ms. The 3 ms delay filters out temporary
dips in the VBUS voltage.
0

Writing a 0 will make the CONNECT pin go HIGH.

1

Writing a 1 will make the CONNECT pin go LOW..

CON_CH

Connect Change.

00This bit is cleared when read.

1

This bit is set when the device’s pull-up resistor is disconnected
because VBUS disappeared. The DEV_STAT interrupt isgenerated when this bit is 1.

SUS

Suspend: The Suspend bit represents the current suspend state. 0
When the device is suspended (SUS = 1) and the CPU writes a 0
into it, the device will generate a remote wakeup. This will only
happen when the device is connected (CON = 1). When thedevice is not connected or not suspended, writing a 0 has noeffect. Writing a 1 to this bit has no effect.
0This bit is reset to 0 on any activity.

1

This bit is set to 1 when the device hasn’t seen any activity on its
upstream port for more than 3 ms.

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Table 296. Set Device Status Register bit description
Bit

Symbol3

SUS_CH

Value Description

Reset
value
0

Suspend (SUS) bit change indicator. The SUS bit can toggle
because:• The device goes into the suspended state.
• The device is disconnected.
• The device receives resume signalling on its upstream port.
This bit is cleared when read.

4

0

SUS bit not changed.

1

SUS bit changed. At the same time a DEV_STAT interrupt isgenerated.

RST

Bus Reset bit. On a bus reset, the device will automatically go to
the default state. In the default state:0• Device is unconfigured.
• Will respond to address 0.
• Control endpoint will be in the Stalled state.
• All endpoints are unrealized except control endpoints EP0
and EP1.

• Data toggling is reset for all endpoints.
• All buffers are cleared.
• There is no change to the endpoint interrupt status.
• DEV_STAT interrupt is generated.
Note: Bus resets are ignored when the device is not connected(CON=0).

7:5 -0This bit is cleared when read.

1

This bit is set when the device receives a bus reset. A
DEV_STAT interrupt is generated.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

10.7 Get Device Status (Command: 0xFE, Data: read 1 byte)
The Get Device Status command returns the Device Status Register. Reading the device
status returns 1 byte of data. The bit field definition is same as the Set Device Status
Register as shown in Table 13–296.
Remark: To ensure correct operation, the DEV_STAT bit of USBDevIntSt must be cleared
before executing the Get Device Status command.

10.8 Get Error Code (Command: 0xFF, Data: read 1 byte)
Different error conditions can arise inside the SIE. The Get Error Code command returns
the last error code that occurred. The 4 least significant bits form the error code.

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Table 297. Get Error Code Register bit description
Bit

Symbol Value

Description

Reset
value

3:0

EC

Error Code.

0x0

4

EA

7:5

-

0000

No Error.

0001

PID Encoding Error.

0010

Unknown PID.

0011

Unexpected Packet - any packet sequence violation from thespecification.

0100

Error in Token CRC.

0101

Error in Data CRC.

0110

Time Out Error.

0111

Babble.

1000

Error in End of Packet.

1001

Sent/Received NAK.

1010

Sent Stall.

1011

Buffer Overrun Error.

1100

Sent Empty Packet (ISO Endpoints only).

1101

Bitstuff Error.

1110

Error in Sync.

1111

Wrong Toggle Bit in Data PID, ignored data.

-

The Error Active bit will be reset once this register is read.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

10.9 Read Error Status (Command: 0xFB, Data: read 1 byte)
This command reads the 8-bit Error register from the USB device. This register records
which error events have recently occurred in the SIE. If any of these bits are set, the
ERR_INT bit of USBDevIntSt is set. The error bits are cleared after reading this register.
Table 298. Read Error Status Register bit description
Bit

SymbolDescription

Reset value

0

PID_ERRPID encoding error or Unknown PID or Token CRC.

0

1

UEPKT

Unexpected Packet - any packet sequence violation from thespecification.

0

2

DCRC

Data CRC error.

0

3

TIMEOUTTime out error.

0

4

EOP

End of packet error.

05

B_OVRN

Buffer Overrun.

0

6

BTSTF

Bit stuff error.

0

7

TGL_ERR

Wrong toggle bit in data PID, ignored data.

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10.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional))
The Select Endpoint command initializes an internal pointer to the start of the selectedbuffer in EP_RAM. Optionally, this command can be followed by a data read, which
returns some additional information on the packet(s) in the endpoint buffer(s). The
command code of the Select Endpoint command is equal to the physical endpoint
number. In the case of a single buffered endpoint the B_2_FULL bit is not valid.
Table 299. Select Endpoint Register bit description
Bit Symbol
0

1

2

3

4

5

Value Description

FE

Full/Empty. This bit indicates the full or empty status of theendpoint buffer(s). For IN endpoints, the FE bit gives theANDed result of the B_1_FULL and B_2_FULL bits. For OUT
endpoints, the FE bit gives ORed result of the B_1_FULL and
B_2_FULL bits. For single buffered endpoints, this bit simply
reflects the status of B_1_FULL.
0

For an IN endpoint, at least one write endpoint buffer is empty.

1

For an OUT endpoint, at least one endpoint read buffer is full.

ST

0

Stalled endpoint indicator.
0

The selected endpoint is not stalled.

1

The selected endpoint is stalled.

STP

0

SETUP bit: the value of this bit is updated after eachsuccessfully received packet (i.e. an ACKed package on thatparticular physical endpoint).
0

The STP bit is cleared by doing a Select Endpoint/Clear
Interrupt on this endpoint.

1

The last received packet for the selected endpoint was a
SETUP packet.

PO0

Packet over-written bit.

00

The PO bit is cleared by the ‘Select Endpoint/Clear Interrupt’command.

1

The previously received packet was over-written by a SETUP
packet.

EPN

EP NAKed bit indicates sending of a NAK. If the host sends an 0
OUT packet to a filled OUT buffer, the device returns NAK. If
the host sends an IN token packet to an empty IN buffer, thedevice returns NAK.
0The EPN bit is reset after the device has sent an ACK after an
OUT packet or when the device has seen an ACK after sending
an IN packet.

1

The EPN bit is set when a NAK is sent and the interrupt on NAKfeature is enabled.

B_1_FULL

The buffer 1 status.
0

Buffer 1 is empty.

1

Buffer 1 is full.

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Table 299. Select Endpoint Register bit description
Bit Symbol
6

7

Value Description

B_2_FULL

Reset
value

The buffer 2 status.

-

0

0

Buffer 2 is empty.

1

Buffer 2 is full.

-Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

10.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1
byte)
Commands 0x40 to 0x5F are identical to their Select Endpoint equivalents, with thefollowing differences:• They clear the bit corresponding to the endpoint in the USBEpIntSt register.
• In case of a control OUT endpoint, they clear the STP and PO bits in thecorresponding Select Endpoint Register.

• Reading one byte is obligatory.
Remark: This command may be invoked by using the USBCmdCode and USBCmdDataregisters, or by setting the corresponding bit in USBEpIntClr. For ease of use, using theUSBEpIntClr register is recommended.

10.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte
(optional))
The Set Endpoint Status command sets status bits 7:5 and 0 of the endpoint. The
Command Code of Set Endpoint Status is equal to the sum of 0x40 and the physicalendpoint number in hex. Not all bits can be set for all types of endpoints.
Table 300. Set Endpoint Status Register bit description
Bit

Symbol

0

ST

4:1 -

Value

Description

Stalled endpoint bit. A Stalled control endpoint is automatically0unstalled when it receives a SETUP token, regardless of thecontent of the packet. If the endpoint should stay in its stalledstate, the CPU can stall it again by setting this bit. When a stalled
endpoint is unstalled - either by the Set Endpoint Statuscommand or by receiving a SETUP token - it is also re-initialized.
This flushes the buffer: in case of an OUT buffer it waits for a
DATA 0 PID; in case of an IN buffer it writes a DATA 0 PID.
There is no change of the interrupt status of the endpoint. Whenalready unstalled, writing a zero to this bit initializes the endpoint.
When an endpoint is stalled by the Set Endpoint Statuscommand, it is also re-initialized.
0

The endpoint is unstalled.

1

The endpoint is stalled.

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

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Table 300. Set Endpoint Status Register bit description
Bit

Symbol

5

DA

6

7

Value

Description

Reset
value

Disabled endpoint bit.

00

The endpoint is enabled.

1

The endpoint is disabled.

RF_MO

Rate Feedback Mode.

00Interrupt endpoint is in the Toggle mode.

1

Interrupt endpoint is in the Rate Feedback mode. This meansthat transfer takes place without data toggle bit.

CND_ST

Conditional Stall bit.

00

Unstalls both control endpoints.

1

Stall both control endpoints, unless the STP bit is set in the
Select Endpoint register. It is defined only for control OUT
endpoints.

10.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional))
When an OUT packet sent by the host has been received successfully, an internal
hardware FIFO status Buffer_Full flag is set. All subsequent packets will be refused byreturning a NAK. When the device software has read the data, it should free the buffer by
issuing the Clear Buffer command. This clears the internal Buffer_Full flag. When thebuffer is cleared, new packets will be accepted.
When bit 0 of the optional data byte is 1, the previously received packet was over-written
by a SETUP packet. The Packet over-written bit is used only in control transfers.
According to the USB specification, a SETUP packet should be accepted irrespective of
the buffer status. The software should always check the status of the PO bit after reading
the SETUP data. If it is set then it should discard the previously read data, clear the PO bit
by issuing a Select Endpoint/Clear Interrupt command, read the new SETUP data andagain check the status of the PO bit.
See Section 13–12 “Slave mode operation” for a description of when this command is
used.
Table 301. Clear Buffer Register bit description
Bit

Symbol Value

Description

Reset
value

0

PO

Packet over-written bit. This bit is only applicable to the control
endpoint EP0.

0

7:1

-

0

The previously received packet is intact.

1

The previously received packet was over-written by a later SETUP
packet.

-Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.

10.14 Validate Buffer (Command: 0xFA, Data: none)
When the CPU has written data into an IN buffer, software should issue a Validate Buffer
command. This tells hardware that the buffer is ready for sending on the USB bus.
Hardware will send the contents of the buffer when the next IN token packet is received.
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Internally, there is a hardware FIFO status flag called Buffer_Full. This flag is set by the
Validate Buffer command and cleared when the data has been sent on the USB bus andthe buffer is empty.
A control IN buffer cannot be validated when its corresponding OUT buffer has the Packet
Over-written (PO) bit (see the Clear Buffer Register) set or contains a pending SETUP
packet. For the control endpoint the validated buffer will be invalidated when a SETUP
packet is received.
See Section 13–12 “Slave mode operation” for a description of when this command isused.

11. USB device controller initialization
The LPC23xx USB device controller initialization includes the following steps:
1. Enable the device controller by setting the PCUSB bit of PCONP.
2. Configure and enable the PLL and Clock Dividers to provide 48 MHz for usbclk, andthe desired frequency for cclk. For correct operation of synchronization logic in thedevice controller, the minimum cclk frequency is 18 MHz. For the procedure fordetermining the PLL setting and configuration, see Section 4–5.12 “Procedure fordetermining PLL settings”.
3. Enable the device controller clocks by setting DEV_CLK_EN and AHB_CLK_EN bitsin the USBClkCtrl register. Poll the respective clock bits in the USBClkSt register until
they are set.
4. LPC2378 only: select the desired USB port pins using the USBPortSel register. The
PORTSEL_CLK_EN bit must be set in USBClkCtrl before accessing USBPortSel andshould be cleared after accessing USBPortSel.
5. Enable the USB pin functions by writing to the corresponding PINSEL register.
6. Disable the pull-up resistor on the VBUS pin using the corresponding PINMODE
register.
7. Set USBEpIn and USBMaxPSize registers for EP0 and EP1, and wait until the
EP_RLZED bit in USBDevIntSt is set so that EP0 and EP1 are realized.
8. Enable endpoint interrupts (Slave mode):– Clear all endpoint interrupts using USBEpIntClr.
– Clear any device interrupts using USBDevIntClr.
– Enable Slave mode for the desired endpoints by setting the corresponding bits in
USBEpIntEn.
– Set the priority of each enabled interrupt using USBEpIntPri.
– Configure the desired interrupt mode using the SIE Set Mode command.
– Enable device interrupts using USBDevIntEn (normally DEV_STAT, EP_SLOW,and possibly EP_FAST).
9. Configure the DMA (DMA mode):– Disable DMA operation for all endpoints using USBEpDMADis.
– Clear any pending DMA requests using USBDMARClr.

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Chapter 13: LPC2300 USB device– Clear all DMA interrupts using USBEoTIntClr, USBNDDRIntClr, andUSBSysErrIntClr.
– Prepare the UDCA in system memory.
– Write the desired address for the UDCA to USBUDCAH (for example 0x7FD00000).
– Enable the desired endpoints for DMA operation using USBEpDMAEn.
– Set EOT, DDR, and ERR bits in USBDMAIntEn.
10. Install USB interrupt handler in the VIC by writing its address to the corresponding
VICVectAddr register and enabling the USB interrupt in the VICIntEnable register.
11. Set default USB address to 0x0 and DEV_EN to 1 using the SIE Set Addresscommand. A bus reset will also cause this to happen.
12. Set CON bit to 1 to make CONNECT active using the SIE Set Device Statuscommand.
The configuration of the endpoints varies depending on the software application. Bydefault, all the endpoints are disabled except control endpoints EP0 and EP1. Additional
endpoints are enabled and configured by software after a SET_CONFIGURATION or
SET_INTERFACE device request is received from the host.

12. Slave mode operation
In Slave mode, the CPU transfers data between RAM and the endpoint buffer using theRegister Interface.

12.1 Interrupt generation
In slave mode, data packet transfer between RAM and an endpoint buffer can be initiatedin response to an endpoint interrupt. Endpoint interrupts are enabled using theUSBEpIntEn register, and are observable in the USBEpIntSt register.
All non-isochronous OUT endpoints generate an endpoint interrupt when they receive apacket without an error. All non-isochronous IN endpoints generate an interrupt when apacket is successfully transmitted, or when a NAK handshake is sent on the bus and theinterrupt on NAK feature is enabled.
For Isochronous endpoints, transfer of data is done when the FRAME interrupt (inUSBDevIntSt) occurs.

12.2 Data transfer for OUT endpoints
When the software wants to read the data from an endpoint buffer it should set the
RD_EN bit and program LOG_ENDPOINT with the desired endpoint number in the
USBCtrl register. The control logic will fetch the packet length to the USBRxPLen register,and set the PKT_RDY bit (Table 13–267 ).
Software can now start reading the data from the USBRxData register (Table 13–266).
When the end of packet is reached, the RD_EN bit is cleared, and the RxENDPKT bit isset in the USBDevSt register. Software now issues a Clear Buffer (refer to Table 13–301)
command. The endpoint is now ready to accept the next packet. For OUT isochronous

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endpoints, the next packet will be received irrespective of whether the buffer has beencleared. Any data not read from the buffer before the end of the frame is lost. See
Section 13–14 “Double buffered endpoint operation” for more details.
If the software clears RD_EN before the entire packet is read, reading is terminated, andthe data remains in the endpoint’s buffer. When RD_EN is set again for this endpoint, thedata will be read from the beginning.

12.3 Data transfer for IN endpoints
When writing data to an endpoint buffer, WR_EN (Section 13–8.6.5 “USB Control register(USBCtrl - 0xFFE0 C228)”) is set and software writes to the number of bytes it is going tosend in the packet to the USBTxPLen register (Section 13–8.6.4). It can then write data
continuously in the USBTxData register.
When the the number of bytes programmed in USBTxPLen have been written to
USBTxData, the WR_EN bit is cleared, and the TxENDPKT bit is set in the USBDevIntSt
register. Software issues a Validate Buffer (Section 13–10.14 “Validate Buffer (Command:
0xFA, Data: none)”) command. The endpoint is now ready to send the packet. For IN
isochronous endpoints, the data in the buffer will be sent only if the buffer is validated
before the next FRAME interrupt occurs; otherwise, an empty packet will be sent in thenext frame. If the software clears WR_EN before the entire packet is written, writing will
start again from the beginning the next time WR_EN is set for this endpoint.
Both RD_EN and WR_EN can be high at the same time for the same logical endpoint.
Interleaved read and write operation is possible.

13. DMA operation
In DMA mode, the DMA transfers data between RAM and the endpoint buffer.
The following sections discuss DMA mode operation. Background information is given in
sections Section 13–13.2 “USB device communication area” and Section 13–13.3“Triggering the DMA engine”. The fields of the DMA Descriptor are described in section
Section 13–13.4 “The DMA descriptor”. The last three sections describe DMA operation:
Section 13–13.5 “Non-isochronous endpoint operation”, Section 13–13.6 “Isochronous
endpoint operation”, and Section 13–13.7 “Auto Length Transfer Extraction (ATLE) mode
operation”.

13.1 Transfer terminology
Within this section three types of transfers are mentioned:
1. USB transfers – transfer of data over the USB bus. The USB 2.0 specification refers
to these simply as transfers. Within this section they are referred to as USB transfers
to distinguish them from DMA transfers. A USB transfer is composed of transactions.
Each transaction is composed of packets.
2. DMA transfers – the transfer of data between an endpoint buffer and system memory(RAM).
3. Packet transfers – in this section, a packet transfer refers to the transfer of a packet ofdata between an endpoint buffer and system memory (RAM). A DMA transfer iscomposed of one or more packet transfers.
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13.2 USB device communication area
The CPU and DMA controller communicate through a common area of memory, called the
USB Device Communication Area, or UDCA. The UDCA is a 32-word array of DMA
Descriptor Pointers (DDPs), each of which corresponds to a physical endpoint. Each DDP
points to the start address of a DMA Descriptor, if one is defined for the endpoint. DDPs
for unrealized endpoints and endpoints disabled for DMA operation are ignored and canbe set to a NULL (0x0) value.
The start address of the UDCA is stored in the USBUDCAH register. The UDCA canreside at any 128-byte boundary of RAM that is accessible to both the CPU and DMA
controller.
Figure 36 illustrates the UDCA and its relationship to the UDCA Head (USBUDCAH)
register and DMA Descriptors.

UDCA

0

NULL
NULL

1

NULL

Next_DD_pointerNext_DD_pointerNext_DD_pointer

DD-EP2-a

DD-EP2-b

DD-EP2-c

Next_DD_pointerNext_DD_pointer

DD-EP16-a

DD-EP16-b

2
DDP-EP2

NULL
UDCA HEADREGISTER

NULL
16
DDP-EP16

31
DDP-EP31

Fig 53. UDCA Head register and DMA Descriptors

13.3 Triggering the DMA engine
An endpoint raises a DMA request when Slave mode is disabled by setting thecorresponding bit in the USBEpIntEn register to 0 (Section 13–8.4.2) and an endpointinterrupt occurs (see Section 13–8.8.1 “USB DMA Request Status register (USBDMARSt- 0xFFE0 C250)”).
A DMA transfer for an endpoint starts when the endpoint is enabled for DMA operation in
USBEpDMASt, the corresponding bit in USBDMARSt is set, and a valid DD is found forthe endpoint.
All endpoints share a single DMA channel to minimize hardware overhead. If more than
one DMA request is active in USBDMARSt, the endpoint with the lowest physical endpoint
number is processed first.

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In DMA mode, the bits corresponding to Interrupt on NAK for Bulk OUT and Interrupt OUT
endpoints (INAK_BO and INAK_IO) should be set to 0 using the SIE Set Mode command(Section 13–10.3).

13.4 The DMA descriptor
DMA transfers are described by a data structure called the DMA Descriptor (DD).
DDs are placed in the USB RAM. These descriptors can be located anywhere in the USB
RAM at word-aligned addresses. USB RAM is part of the system memory that is used for
the USB purposes. It is located at address 0x7FD0 0000 and is 8 kB in size.
DDs for non-isochronous endpoints are four words long. DDs for isochronous endpoints
are five words long.
The parameters associated with a DMA transfer are:

• The start address of the DMA buffer• The length of the DMA buffer• The start address of the next DMA descriptor• Control information• Count information (number of bytes transferred)• Status information
Table 13–302 lists the DMA descriptor fields.
Table 302. DMA descriptor
Word
Access Access Bit
Description
position (H/W)(S/W)
position
0

R

R/W

31:0

Next_DD_pointer (USB RAM address)

1

R

R/W

1:0

DMA_mode (00 -Normal; 01 - ATLE)

R

R/W

2

Next_DD_valid (1 - valid; 0 - invalid)

-

-

3

Reserved

R

R/W

4

Isochronous_endpoint (1 - isochronous;
0 - non-isochronous)

R

R/W

15:5

Max_packet_size

R/W[1]

R/W

31:16

DMA_buffer_length
This value is specified in bytes for non-isochronous
endpoints and in number of packets for isochronous
endpoints.

2

R/W

R/W

31:0

DMA_buffer_start_addr

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Table 302. DMA descriptor
Word
Access Access Bit
Description
position (H/W)(S/W)
position
3

R/W

R/I

0

DD_retired (To be initialized to 0)

W

R/I

4:1

DD_status (To be initialized to 0000):
0000 - NotServiced
0001 - BeingServiced
0010 - NormalCompletion
0011 - DataUnderrun (short packet)
1000 - DataOverrun
1001 - SystemError

4
[1]

W

R/I

5

Packet_valid (To be initialized to 0)

W

R/I

6

LS_byte_extracted (ATLE mode) (To be initialized to 0)

W

R/I

7

MS_byte_extracted (ATLE mode) (To be initialized to 0)

R

W

13:8

Message_length_position (ATLE mode)

-

-

15:14

Reserved

R/W

R/I

31:16

Present_DMA_count (To be initialized to 0)

R/W

R/W

31:0

Isochronous_packetsize_memory_address

Write only in ATLE mode

Legend: R - Read; W - Write; I - Initialize

13.4.1 Next_DD_pointerPointer to the memory location from where the next DMA descriptor will be fetched.

13.4.2 DMA_mode
Specifies the DMA mode of operation. Two modes have been defined: Normal andAutomatic Transfer Length Extraction (ATLE) mode. In normal mode, software initializes
the DMA_buffer_length for OUT endpoints. In ATLE mode, the DMA_buffer_length isextracted from the incoming data. See Section 13–13.7 “Auto Length Transfer Extraction(ATLE) mode operation” on page 320 for more details.

13.4.3 Next_DD_valid
This bit indicates whether the software has prepared the next DMA descriptor. If set, theDMA engine fetches the new descriptor when it is finished with the current one.

13.4.4 Isochronous_endpoint
When set, this bit indicates that the descriptor belongs to an isochronous endpoint. Hence
5 words have to be read when fetching it.

13.4.5 Max_packet_size
The maximum packet size of the endpoint. This parameter is used while transferring thedata for IN endpoints from the memory. It is used for OUT endpoints to detect the shortpacket. This is applicable to non-isochronous endpoints only. This field should be set tothe same MPS value that is assigned for the endpoint using the USBMaxPSize register.

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13.4.6 DMA_buffer_length
This indicates the depth of the DMA buffer allocated for transferring the data. The DMA
engine will stop using this descriptor when this limit is reached and will look for the next
descriptor.
In Normal mode operation, software sets this value for both IN and OUT endpoints. In
ATLE mode operation, software sets this value for IN endpoints only. For OUT endpoints,
hardware sets this value using the extracted length of the data stream.
For isochronous endpoints, DMA_buffer_length is specified in number of packets, for
non-isochronous endpoints in bytes.

13.4.7 DMA_buffer_start_addr
The address where the data is read from or written to. This field is updated each time the
DMA engine finishes transferring a packet.

13.4.8 DD_retired
This bit is set by hardware when the DMA engine finishes the current descriptor. This
happens when the end of the buffer is reached, a short packet is transferred(non-isochronous endpoints), or an error condition is detected.

13.4.9 DD_status
The status of the DMA transfer is encoded in this field. The following codes are defined:• NotServiced - No packet has been transferred yet.
• BeingServiced - At least one packet is transferred.
• NormalCompletion - The DD is retired because the end of the buffer is reached andthere were no errors. The DD_retired bit is also set.

• DataUnderrun - Before reaching the end of the DMA buffer, the USB transfer isterminated because a short packet is received. The DD_retired bit is also set.

• DataOverrun - The end of the DMA buffer is reached in the middle of a packet
transfer. This is an error situation. The DD_retired bit is set. The present DMA countfield is equal to the value of DMA_buffer_length. The packet must be re-transmitted
from the endpoint buffer in another DMA transfer. The corresponding
EPxx_DMA_ENABLE bit in USBEpDMASt is cleared.

• SystemError - The DMA transfer being serviced is terminated because of an error on
the AHB bus. The DD_retired bit is not set in this case. The corresponding
EPxx_DMA_ENABLE in USBEpDMASt is cleared. Since a system error can happen
while updating the DD, the DD fields in RAM may be unreliable.

13.4.10 Packet_valid
This bit is used for isochronous endpoints. It indicates whether the last packet transferredto the memory is received with errors or not. This bit is set if the packet is valid, i.e., it wasreceived without errors. See Section 13–13.6 “Isochronous endpoint operation” on page318 for isochronous endpoint operation.
This bit is unnecessary for non-isochronous endpoints because a DMA request is
generated only for packets without errors, and thus Packet_valid will always be set when
the request is generated.
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13.4.11 LS_byte_extracted
Used in ATLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of
the transfer length has been extracted. The extracted size is reflected in the
DMA_buffer_length field, bits 23:16.

13.4.12 MS_byte_extracted
Used in ATLE mode. When set, this bit indicates that the Most Significant Byte (MSB) of
the transfer size has been extracted. The size extracted is reflected in the
DMA_buffer_length field, bits 31:24. Extraction stops when LS_Byte_extracted andMS_byte_extracted bits are set.

13.4.13 Present_DMA_countThe number of bytes transferred by the DMA engine. The DMA engine updates this field
after completing each packet transfer.
For isochronous endpoints, Present_DMA_count is the number of packets transferred; fornon-isochronous endpoints, Present_DMA_count is the number of bytes.

13.4.14 Message_length_position
Used in ATLE mode. This field gives the offset of the message length position embeddedin the incoming data packets. This is applicable only for OUT endpoints. Offset 0 indicatesthat the message length starts from the first byte of the first packet.

13.4.15 Isochronous_packetsize_memory_address
The memory buffer address where the packet size information along with the frame
number has to be transferred or fetched. See Figure 13–54. This is applicable toisochronous endpoints only.

13.5 Non-isochronous endpoint operation
13.5.1 Setting up DMA transfers
Software prepares the DMA Descriptors (DDs) for those physical endpoints to be enabledfor DMA transfer. These DDs are present in the USB RAM. The start address of the first
DD is programmed into the DMA Description pointer (DDP) location for the corresponding
endpoint in the UDCA. Software then sets the EPxx_DMA_ENABLE bit for this endpoint in
the USBEpDMAEn register (Section 13–8.8.6).The DMA_mode bit field in the descriptor
is set to ‘00’ for normal mode operation. All other DD fields are initialized as specified inTable 13–302.
DMA operation is not supported for physical endpoints 0 and 1 (default control endpoints).

13.5.2 Finding DMA Descriptor
When there is a trigger for a DMA transfer for an endpoint, the DMA engine will first
determine whether a new descriptor has to the fetched or not. A new descriptor does nothave to be fetched if the last packet transferred was for the same endpoint and the DD is
not yet in the retired state. An internal flag called DMA_PROCEED is used to identify thiscondition (see Section 13–13.5.4 “Optimizing descriptor fetch” on page 317).

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If a new descriptor has to be read, the DMA engine will calculate the location of the DDP
for this endpoint and will fetch the start address of the DD from this location. A DD start
address at location zero is considered invalid. In this case the NDDR interrupt is raised.
All other word-aligned addresses are considered valid.
When the DD is fetched, the DD status word (word 3) is read first and the status of the
DD_retired bit is checked. If not set, DDP points to a valid DD. If DD_retired is set, theDMA engine will read the control word (word 1) of the DD.
If Next_DD_valid bit is set, the DMA engine will fetch the Next_DD_pointer field (word 0)of the DD and load it to the DDP. The new DDP is written to the UDCA area.
The full DD (4 words) will then be fetched from the address in the DDP. The DD will givethe details of the DMA transfer to be done. The DMA engine will load its hardware
resources with the information fetched from the DD (start address, DMA count etc.).
If Next_DD_valid is not set and DD_retired bit is set, the DMA engine raises the NDDR
interrupt for this endpoint and clears the corresponding EPxx_DMA_ENABLE bit.

13.5.3 Transferring the data
For OUT endpoints, the current packet is read from the EP_RAM by the DMA Engine andtransferred to the USB RAM memory locations starting from DMA_buffer_start_addr. For
IN endpoints, the data is fetched from the USB RAM at DMA_buffer_start_addr andwritten to the EP_RAM. The DMA_buffer_start_addr and Present_DMA_count fields are
updated after each packet is transferred.

13.5.4 Optimizing descriptor fetch
A DMA transfer normally involves multiple packet transfers. Hardware will not re-fetch a
new DD from memory unless the endpoint changes. To indicate an ongoing multi-packet
transfer, hardware sets an an internal flag called DMA_PROCEED.
The DMA_PROCEED flag is cleared after the required number of bytes specified in the
DMA_buffer_length field is transferred. It is also cleared when the software writes into theUSBEpDMADis register. The ability to clear the DMA_PROCEED flag allows software toto force the DD to be re-fetched for the next packet transfer. Writing all zeros into theUSBEpDMADis register clears the DMA_PROCEED flag without disabling DMA operation
for any endpoint.

13.5.5 Ending the packet transfer
On completing a packet transfer, the DMA engine writes back the DD with updated status
information to the same memory location from where it was read. The
DMA_buffer_start_addr, Present_DMA_count, and the DD_status fields in the DD are
updated.
A DD can have the following types of completion:
Normal completion - If the current packet is fully transferred and the
Present_DMA_count field equals the DMA_buffer_length, the DD has completed
normally. The DD will be written back to memory with DD_retired set and DD_status set
to NormalCompletion. The EOT interrupt is raised for this endpoint.

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USB transfer end completion - If the current packet is fully transferred and its size isless than the Max_packet_size field, and the end of the DMA buffer is still not reached,
the USB transfer end completion occurs. The DD will be written back to the memory
with DD_retired set and DD_Status set to the DataUnderrun completion code. The EOT
interrupt is raised for this endpoint.
Error completion - If the current packet is partially transferred i.e. the end of the DMA
buffer is reached in the middle of the packet transfer, an error situation occurs. The DD
is written back with DD_retired set and DD_status set to the DataOverrun status code.
The EOT interrupt is raised for this endpoint and the corresponding bit in USBEpDMASt
register is cleared. The packet will be re-sent from the endpoint buffer to memory when
the corresponding EPxx_DMA_ENABLE bit is set again using the USBEpDMAEn
register.

13.5.6 No_Packet DD
For an IN transfer, if the system does not have any data to send for a while, it can respondto an NDDR interrupt by programming a No_Packet DD. This is done by setting both the
Max_packet_size and DMA_buffer_length fields in the DD to 0. On processing a
No_Packet DD, the DMA engine clears the DMA request bit in USBDMARSt
corresponding to the endpoint without transferring a packet. The DD is retired with astatus code of NormalCompletion. This can be repeated as often as necessary. The
device will respond to IN token packets on the USB bus with a NAK until a DD with a data
packet is programmed and the DMA transfers the packet into the endpoint buffer.

13.6 Isochronous endpoint operation
For isochronous endpoints, the packet size can vary for each packet. There is one packet
per isochronous endpoint for each frame.

13.6.1 Setting up DMA transfers
Software sets the isochronous endpoint bit to 1 in the DD, and programs the initial value ofthe Isochronous_packetsize_memory_address field. All other fields are initialized thesame as for non-isochronous endpoints.
For isochronous endpoints, the DMA_buffer_length and Present_DMA_count fields are inframes rather than bytes.

13.6.2 Finding the DMA Descriptor
Finding the descriptors is done in the same way as that for a non-isochronous endpoint.
A DMA request will be placed for DMA-enabled isochronous endpoints on every FRAME
interrupt. On processing the request, the DMA engine will fetch the descriptor and if
Isochronous_endpoint is set, will fetch the Isochronous_packetsize_memory_addressfrom the fifth word of the DD.

13.6.3 Transferring the Data
The data is transferred to or from the memory location DMA_buffer_start_addr. After theend of the packet transfer the Present_DMA_count value is incremented by 1.

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The isochronous packet size is stored in memory as shown in figure 32. Each word in thepacket size memory shown is divided into fields: Frame_number (bits 31 to 17),
Packet_valid (bit 16), and Packet_length (bits 15 to 0). The space allocated for the packet
size memory for a given DD should be DMA_buffer_length words in size – one word foreach packet to transfer.
OUT endpoints
At the completion of each frame, the packet size is written to the address location in
Isochronous_packet_size_memory_address, andIsochronous_packet_size_memory_address is incremented by 4.
IN endpoints
Only the Packet_length field of the isochronous packet size word is used. For each frame,
an isochronous data packet of size specified by this field is transferred from the USB
device to the host, and Isochronous_packet_size_memory_address is incremented by 4
at the end of the packet transfer. If Packet_length is zero, an empty packet will be sent by
the USB device.

13.6.4 DMA descriptor completion
DDs for isochronous endpoints can only end with a status code of NormalCompletion
since there is no short packet on Isochronous endpoints, and the USB transfer continues
indefinitely until a SystemError occurs. There is no DataOverrun detection for isochronous
endpoints.

13.6.5 Isochronous OUT Endpoint Operation Example
Assume that an isochronous endpoint is programmed for the transfer of 10 frames andthat the transfer begins when the frame number is 21. After transferring four frames withpacket sizes of 10,15, 8 and 20 bytes without errors, the descriptor and memory map
appear as shown in Figure 13–54.
The_total_number_of_bytes_transferred = 0x0A + 0x0F + 0x08 + 0x14 = 0x35.
The Packet_valid bit (bit 16) of all the words in the packet length memory is set to 1.

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Next_DD_PointerW0
NULL
DMA_buffer_length

Max_packet_size

0x000A

0x0

W1

Isochronous_endpoint

Next_DD_ValidDMA_mode

00

1
DMA_buffer_start_addr

W20x80000000
Present_DMA_Count

ATLE settings

Packet_Valid

DD_Status

DD_Retired

0x0

NA

NA

0x0

0

W3

Isocronous_packetsize_memory_address

W40x60000000

after 4 packets

W0

0x0

W1

0x000A0010
FULL

W2
W3

0x80000035
0x4

- -

0x1

0
frame_ number Packet_Valid Packet_Length

W40x60000010

31

15

16
21
22
23
24

1
1
1
1

0

EMPTY

10
15
8
20
data memory

packet size memory

Fig 54. Isochronous OUT endpoint operation example

13.7 Auto Length Transfer Extraction (ATLE) mode operation
Some host drivers such as NDIS (Network Driver Interface Specification) host drivers arecapable of concatenating small USB transfers (delta transfers) to form a single large USBtransfer. For OUT USB transfers, the device hardware has to break up this concatenatedtransfer back into the original delta transfers and transfer them to separate DMA buffers.
This is achieved by setting the DMA mode to Auto Transfer Length Extraction (ATLE)
mode in the DMA descriptor. ATLE mode is supported for Bulk endpoints only.
OUT transfers in ATLE mode

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data to be sent

data in packets

data to be stored in USB

by host driveras seen on USB

RAM by DMA engine

160 bytes
64 bytes

DMA_buffer_start_addr
of DD1160 bytes
64 bytes

32 bytes
32 bytes
100 bytes
100 bytes
64 bytes

DMA_buffer_start_addr
of DD2

4 bytesFig 55. Data transfer in ATLE mode

Figure 13–55 shows a typical OUT USB transfer in ATLE mode, where the hostconcatenates two USB transfers of 160 bytes and 100 bytes, respectively. Given a
MaxPacketSize of 64, the device hardware interprets this USB transfer as four packets of
64 bytes and a short packet of 4 bytes. The third and fourth packets are concatenated.
Note that in Normal mode, the USB transfer would be interpreted as packets of 64, 64, 32,
and 64 and 36 bytes.
It is now the responsibility of the DMA engine to separate these two USB transfers and put
them in the memory locations in the DMA_buffer_start_addr field of DMA Descriptor 1(DD1) and DMA Descriptor 2 (DD2).
Hardware reads the two-byte-wide DMA_buffer_length at the offset (from the start of the
USB transfer) specified by Message_length_position from the incoming data packets andwrites it in the DMA_buffer_length field of the DD. To ensure that both bytes of the
DMA_buffer_length are extracted in the event they are split between two packets, theflags LS_byte_extracted and MS_byte_extracted are set by hardware after the respective
byte is extracted. After the extraction of the MS byte, the DMA transfer continues as in thenormal mode.
The flags LS_byte_extracted and MS_byte_extracted are set to 0 by software when
preparing a new DD. Therefore, once a DD is retired, the transfer length is extracted again
for the next DD.
If DD1 is retired during the transfer of a concatenated packet (such as the third packet in
Figure 13–55), and DD2 is not programmed (Next_DD_valid field of DD1 is 0), then DD1
is retired with DD_status set to the DataOverrun status code. This is treated as an error
condition and the corresponding EPxx_DMA_ENABLE bit of USBEpDMASt is cleared byhardware.

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In ATLE mode, the last buffer length to be transferred always ends with a short or empty
packet indicating the end of the USB transfer. If the concatenated transfer lengths are
such that the USB transfer ends on a MaxPacketSize packet boundary, the (NDIS) hostwill send an empty packet to mark the end of the USB transfer.
IN transfers in ATLE mode
For IN USB transfers from the device to the host, DMA_buffer_length is set by the device
software as in normal mode.
In ATLE mode, the device concatenates data from multiple DDs to form a single USBtransfer. If a DD is retired in the middle of a packet (packet size is less than
MaxPacketSize), the next DD referenced by Next_DD_pointer is fetched, and theremaining bytes to form a packet of MaxPacketSize are transferred from the next DD’s
buffer.
If the next DD is not programmed (i.e. Next_DD_valid field in DD is 0), and the DMA buffer
length for the current DD has completed before the MaxPacketSize packet boundary, thenthe available bytes from current DD are sent as a short packet on USB, which marks theend of the USB transfer for the host.
If the last buffer length completes on a MaxPacketSize packet boundary, the device
software must program the next DD with DMA_buffer_length field 0, so that an empty
packet is sent by the device to mark the end of the USB transfer for the host.

13.7.1 Setting up the DMA transfer
For OUT endpoints, the host hardware needs to set the field Message_length_position in
the DD. This indicates the start location of the message length in the incoming data
packets. Also the device software has to set the DMA_buffer_length field to 0 for OUT
endpoints because this field is updated by the device hardware after the extraction of thebuffer length.
For IN endpoints, descriptors are set in the same way as in normal mode operation.
Since a single packet can be split between two DDs, software should always keep two
DDs ready, except for the last DMA transfer which ends with a short or empty packet.

13.7.2 Finding the DMA Descriptor
DMA descriptors are found in the same way as the normal mode operation.

13.7.3 Transferring the Data
OUT endpoints
If the LS_byte_extracted or MS_byte_extracted bit in the status field is not set, thehardware will extract the transfer length from the data stream and program
DMA_buffer_length. Once the extraction is complete both the LS_byte_extracted andMS_byte_extracted bits will be set.
IN endpoints
The DMA transfer proceeds as in normal mode and continues until the number of bytes
transferred equals the DMA_buffer_length.
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13.7.4 Ending the packet transfer
The DMA engine proceeds with the transfer until the number of bytes specified in the field
DMA_buffer_length is transferred to or from the USB RAM. Then the EOT interrupt will be
generated. If this happens in the middle of the packet, the linked DD will get loaded andthe remaining part of the packet gets transferred to or from the address pointed by the
new DD.
OUT endpoints
If the linked DD is not valid and the packet is partially transferred to memory, the DD ends
with DataOverrun status code set, and the DMA will be disabled for this endpoint.
Otherwise DD_status will be updated with the NormalCompletion status code.
IN endpoints
If the linked DD is not valid and the packet is partially transferred to USB, the DD ends
with a status code of NormalCompletion in the DD_status field. This situation corresponds
to the end of the USB transfer, and the packet will be sent as a short packet. Also, when
the linked DD is valid and buffer length is 0, an empty packet will be sent to indicate theend of the USB transfer.

14. Double buffered endpoint operation
The Bulk and Isochronous endpoints of the USB Device Controller are double buffered toincrease data throughput.
When a double-buffered endpoint is realized, enough space for both endpoint buffers is
automatically allocated in the EP_RAM. See Section 13–8.5.1.
For the following discussion, the endpoint buffer currently accessible to the CPU or DMA
engine for reading or writing is said to be the active buffer.

14.1 Bulk endpoints
For Bulk endpoints, the active endpoint buffer is switched by the SIE Clear Buffer orValidate Buffer commands.
The following example illustrates how double buffering works for a Bulk OUT endpoint in
Slave mode:
Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty, and that the active buffer is
B_1.
1. The host sends a data packet to the endpoint. The device hardware puts the packet
into B_1, and generates an endpoint interrupt.
2. Software clears the endpoint interrupt and begins reading the packet data from B_1.
While B_1 is still being read, the host sends a second packet, which device hardware
places in B_2, and generates an endpoint interrupt.
3. Software is still reading from B_1 when the host attempts to send a third packet.
Since both B_1 and B_2 are full, the device hardware responds with a NAK.
4. Software finishes reading the first packet from B_1 and sends a SIE Clear Buffer
command to free B_1 to receive another packet. B_2 becomes the active buffer.
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5. Software sends the SIE Select Endpoint command to read the Select Endpoint
Register and test the FE bit. Software finds that the active buffer (B_2) has data
(FE=1). Software clears the endpoint interrupt and begins reading the contents of
B_2.
6. The host resends the third packet which device hardware places in B_1. An endpointinterrupt is generated.
7. Software finishes reading the second packet from B_2 and sends a SIE Clear Buffer
command to free B_2 to receive another packet. B_1 becomes the active buffer.
Software waits for the next endpoint interrupt to occur (it already has been generated
back in step 6).
8. Software responds to the endpoint interrupt by clearing it and begins reading the third
packet from B_1.
9. Software finishes reading the third packet from B_1 and sends a SIE Clear Buffer
command to free B_1 to receive another packet. B_2 becomes the active buffer.
10. Software tests the FE bit and finds that the active buffer (B_2) is empty (FE=0).
11. Both B_1 and B_2 are empty. Software waits for the next endpoint interrupt to occur.
The active buffer is now B_2. The next data packet sent by the host will be placed in
B_2.
The following example illustrates how double buffering works for a Bulk IN endpoint in
Slave mode:
Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty and that the active buffer is
B_1. The interrupt on NAK feature is enabled.
1. The host requests a data packet by sending an IN token packet. The device respondswith a NAK and generates an endpoint interrupt.
2. Software clears the endpoint interrupt. The device has three packets to send.
Software fills B_1 with the first packet and sends a SIE Validate Buffer command. The
active buffer is switched to B_2.
3. Software sends the SIE Select Endpoint command to read the Select Endpoint
Register and test the FE bit. It finds that B_2 is empty (FE=0) and fills B_2 with thesecond packet. Software sends a SIE Validate Buffer command, and the active bufferis switched to B_1.
4. Software waits for the endpoint interrupt to occur.
5. The device successfully sends the packet in B_1 and clears the buffer. An endpointinterrupt occurs.
6. Software clears the endpoint interrupt. Software fills B_1 with the third packet andvalidates it using the SIE Validate Buffer command. The active buffer is switched to
B_2.
7. The device successfully sends the second packet from B_2 and generates an
endpoint interrupt.
8. Software has no more packets to send, so it simply clears the interrupt.
9. The device successfully sends the third packet from B_1 and generates an endpointinterrupt.
10. Software has no more packets to send, so it simply clears the interrupt.

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11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written bysoftware will go into B_2.
In DMA mode, switching of the active buffer is handled automatically in hardware. For
Bulk IN endpoints, proactively filling an endpoint buffer to take advantage of the double
buffering can be accomplished by manually starting a packet transfer using the
USBDMARSet register.

14.2 Isochronous endpoints
For isochronous endpoints, the active data buffer is switched by hardware when the
FRAME interrupt occurs. The SIE Clear Buffer and Validate Buffer commands do notcause the active buffer to be switched.
Double buffering allows the software to make full use of the frame interval writing or
reading a packet to or from the active buffer, while the packet in the other buffer is being
sent or received on the bus.
For an OUT isochronous endpoint, any data not read from the active buffer before the endof the frame is lost when it switches.
For an IN isochronous endpoint, if the active buffer is not validated before the end of theframe, an empty packet is sent on the bus when the active buffer is switched, and its
contents will be overwritten when it becomes active again.

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Chapter 14: Universal Asynchronous Receiver Transmitter(UART) 0, 2, 3
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User manual

1. Features• 16 byte Receive and Transmit FIFOs.
• Register locations conform to ‘550 industry standard.
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
• Built-in baud rate generator.
• Fractional divider for baud rate control, autobaud capabilities and mechanism thatenables software flow control implementation.

• In addition, UART3 includes an IrDA mode to support infrared communication.

2. Pin description
Table 303: UART0 Pin description
Pin

Type

Description

RXD0, RXD2, RXD3

Input

Serial Input. Serial receive data.

TXD0, TXD2, TXD3

OutputSerial Output. Serial transmit data.

3. Register description
Each UART contains registers as shown in Table 14–304. The Divisor Latch Access Bit(DLAB) is contained in UnLCR7 and enables access to the Divisor Latches.

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NXP Semiconductors

UM10211_1

User manual

Table 304: UART Register Map
Generic
Name

Description

Access Reset

Bit functions and addresses
MSB
BIT7

value[

LSB
BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

UARTn Register
Name & Address

1]

BIT0
NA

U0RBR - 0xE000 C000
U2RBR - 0xE007 8000
U3RBR - 0xE007 C000

THR
Transmit Holding(DLAB=0) Register

8 bit Write Data

WO

NA

U0THR - 0xE000 C000
U2THR - 0xE007 8000
U3THR - 0xE007 C000

DLL
Divisor Latch LSB(DLAB=1)

8 bit Data

R/W

0x01

U0DLL - 0xE000 C000
U2DLL - 0xE007 8000
U3DLL - 0xE007 C000

DLM
Divisor Latch(DLAB=1) MSB

8 bit Data

R/W

0x00

U0DLM - 0xE000 C004
U2DLM - 0xE007 8004
U3DLM - 0xE007 C004

R/W

0x00

U0IER - 0xE000 C004
U2IER - 0xE007 8004
U3IER - 0xE007 C004

RO

0x01

U0IIR - 0xE000 C008
U2IIR - 0xE007 8008
U3IIR - 0xE007 C008

WO

0x00

U0FCR - 0xE000 C008
U2FCR - 0xE007 8008
U3FCR - 0xE007 C008

Word Length Select

R/W

0x00

U0LCR - 0xE000 C00CU2LCR - 0xE007 800C
U3LCR - 0xE007 C00C

OE

RO

0x60

U0LSR - 0xE000 C014
U2LSR - 0xE007 8014
U3LSR - 0xE007 C014

R/W

0x00

U0SCR - 0xE000 C01CU2SCR - 0xE007 801CU3SCR - 0xE007 C01C

R/W

0x00

U0ACR - 0xE000 C020
U2ACR - 0xE007 8020
U3ACR - 0xE007 C020

Reserved0
IIRInterrupt ID
Register

Enable RX
Line Status
Interrupt
Reserved

FIFOs Enabled

0

IIR3

Enable THRE
Interrupt

Enable RX
Data Available
Interrupt

ABTOInt

ABEOint

IIR1

IIR0

TX FIFOReset

RX FIFOReset

FIFO Enable© NXP B.V. 2007. All rights reserved.

FIFO Control
Register

LCRLine Control
Register

DLAB

Set BreakStick
ParityEven
ParitySelectParityEnableNumber ofStop Bits

LSRLine Status
Register

RX FIFO
Error

TEMT

THRE

BI

FE

PE

SCR

Scratch Pad
Register

ACR

Auto-baud Control
RegisterReserved

Enable End of
Auto- BaudInterrupt

IIR2

FCR

RX Trigger

Enable AutoBaud TimeOut Interrupt

DR

8 bit Data

Reserved [31:10]
Reserved [7:3]

Auto Reset

ABTO IntClr

ABEO IntClr

Mode

Start

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Chapter 14: LPC2300 UART0, 2, 3

8 bit Read Data

IER
Interrupt Enable(DLAB=0) Register

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Generic
Name
ICR

Description

MSB
IrDA Control
Register

FDR

Fractional Divider
Register

TER

Transmit Enable
Register[1]

Access Reset

Bit functions and addresses

value[

LSB

Reserved

PulseDiv

FixPulse En

IrDAInv

IrDAEnNXP Semiconductors

UM10211_1

User manual

Table 304: UART Register Map
UARTn Register
Name & Address

1]

R/W

0

U3ICR - 0xE000 C024
(UART3 only)

MulValTXEN

DivAddVal

Reserved

R/W

0x10

U0FDR - 0xE000 C028
U2FDR - 0xE007 8028
U3FDR - 0xE007 C028

R/W

0x80

U0TER - 0xE000 C030
U2TER - 0xE007 8030
U3TER - 0xE007 C030

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

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Chapter 14: LPC2300 UART0, 2, 3

14.3.1 UARTn Receiver Buffer Register (U0RBR - 0xE000 C000, U2RBR 0xE007 8000, U3RBR - 0xE007 C000 when DLAB = 0, Read Only)
The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, theunused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the UnRBR.
The UnRBR is always Read Only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching thevalid pair of received byte and its status bits is first to read the content of the U0LSR
register, and then to read a byte from the UnRBR.
Table 305: UARTn Receiver Buffer Register (U0RBR - address 0xE000 C000,
U2RBR - 0xE007 8000, U3RBR - 0E007 C000 when DLAB = 0, Read Only) bit
description
Bit

SymbolDescription

Reset Value

7:0

RBR

The UARTn Receiver Buffer Register contains the oldest
received byte in the UARTn Rx FIFO.

Undefined

3.2 UARTn Transmit Holding Register (U0THR - 0xE000 C000, U2THR 0xE007 8000, U3THR - 0xE007 C000 when DLAB = 0, Write Only)
The UnTHR is the top byte of the UARTn TX FIFO. The top byte is the newest character in
the TX FIFO and can be written via the bus interface. The LSB represents the first bit totransmit.
The Divisor Latch Access Bit (DLAB) in UnLCR must be zero in order to access the
UnTHR. The UnTHR is always Write Only.
Table 306: UART0 Transmit Holding Register (U0THR - address 0xE000 C000,
U2THR - 0xE007 8000, U3THR - 0xE007 C000 when DLAB = 0, Write Only) bit
description
Bit

SymbolDescription

Reset Value

7:0

THR

Writing to the UARTn Transmit Holding Register causes the data NA
to be stored in the UARTn transmit FIFO. The byte will be sent
when it reaches the bottom of the FIFO and the transmitter isavailable.

3.3 UARTn Divisor Latch LSB Register (U0DLL - 0xE000 C000, U2DLL 0xE007 8000, U3DLL - 0xE007 C000 when DLAB = 1) and UARTn
Divisor Latch MSB Register (U0DLM - 0xE000 C004, U2DLL 0xE007 8004, U3DLL - 0xE007 C004 when DLAB = 1)
The UARTn Divisor Latch is part of the UARTn Baud Rate Generator and holds the value
used to divide the APB clock (PCLK) in order to produce the baud rate clock, which mustbe 16× the desired baud rate. The UnDLL and UnDLM registers together form a 16 bit
divisor where UnDLL contains the lower 8 bits of the divisor and UnDLM contains theUM10211_1

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higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by
zero is not allowed. The Divisor Latch Access Bit (DLAB) in UnLCR must be one in orderto access the UARTn Divisor Latches.
Table 307: UARTn Divisor Latch LSB Register (U0DLL - address 0xE000 C000,
U2DLL - 0xE007 8000, U3DLL - 0xE007 C000 when DLAB = 1) bit description
Bit

SymbolDescription

Reset Value

7:0

DLLSB

The UARTn Divisor Latch LSB Register, along with the UnDLM
register, determines the baud rate of the UARTn.

0x01

Table 308: UARTn Divisor Latch MSB Register (U0DLM - address 0xE000 C004,
U2DLM - 0xE007 8004, U3DLM - 0xE007 C004 when DLAB = 1) bit description
Bit

SymbolDescription

Reset Value

7:0

DLMSB

The UARTn Divisor Latch MSB Register, along with the U0DLL
register, determines the baud rate of the UARTn.

0x00

3.4 UARTn Interrupt Enable Register (U0IER - 0xE000 C004, U2IER 0xE007 8004, U3IER - 0xE007 C004 when DLAB = 0)
The UnIER is used to enable the three UARTn interrupt sources.
Table 309: UARTn Interrupt Enable Register (U0IER - address 0xE000 C004,
U2IER - 0xE007 8004, U3IER - 0xE007 C004 when DLAB = 0) bit description
Bit

Symbol0

RBRInterrupt
EnableValue Description
UnIER[0] enables the Receive Data Available interrupt for
UARTn. It also controls the Character Receive Time-out
interrupt.
0

1

2

THRE
Interrupt
EnableRX LineStatusInterrupt
Enable0Disable the RDA interrupts.

1

Enable the RDA interrupts.

0

UnIER[1] enables the THRE interrupt for UARTn. The
status of this can be read from UnLSR[5].

1

Enable the THRE interrupts.

0

UnIER[2] enables the UARTn RX line status interrupts.
The status of this interrupt can be read from UnLSR[4:1].

0

Disable the THRE interrupts.
0

Disable the RX line status interrupts.
1

Enable the RX line status interrupts.

7:3-

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

8

ABTOIntEn

U1IER8 enables the auto-baud time-out interrupt.

90Disable Auto-baud Time-out Interrupt.

1

Enable Auto-baud Time-out Interrupt.

ABEOIntEn

31:10 -

U1IER9 enables the end of auto-baud interrupt.
0

Disable End of Auto-baud Interrupt.

1

Enable End of Auto-baud Interrupt.

00Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

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Chapter 14: LPC2300 UART0, 2, 3

3.5 UARTn Interrupt Identification Register (U0IIR - 0xE000 C008, U2IIR 0xE007 8008, U3IIR - 0x7008 C008, Read Only)
The UnIIR provides a status code that denotes the priority and source of a pending
interrupt. The interrupts are frozen during an UnIIR access. If an interrupt occurs during
an UnIIR access, the interrupt is recorded for the next UnIIR access.
Table 310: UARTn Interrupt Identification Register (U0IIR - address 0xE000 C008,
U2IIR - 0x7008 8008, U3IIR - 0x7008 C008, Read Only) bit description
Bit

Symbol0

IntStatus

3:1

Value

Description

Reset
Value

Interrupt status. Note that U1IIR[0] is active low. The
pending interrupt can be determined by evaluating
UnIIR[3:1].

1

0

At least one interrupt is pending.

1

No interrupt is pending.

IntIdInterrupt identification. UnIER[3:1] identifies an interrupt
corresponding to the UARTn Rx FIFO. All othercombinations of UnIER[3:1] not listed above are reserved(000,100,101,111).
011

1 - Receive Line Status (RLS).

010

2a - Receive Data Available (RDA).

110

2b - Character Time-out Indicator (CTI).

001

3 - THRE Interrupt

0

5:4

-

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

7:6

FIFO Enable

These bits are equivalent to UnFCR[0].

08ABEOInt

End of auto-baud interrupt. True if auto-baud has finishedsuccessfully and interrupt is enabled.

0

9

ABTOInt

Auto-baud time-out interrupt. True if auto-baud has timedout and interrupt is enabled.

0

31:10 -

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

Bit UnIIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baudcondition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.
If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus
is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type ofinterrupt and handling as described in Table 14–311. Given the status of UnIIR[3:0], aninterrupt handler routine can determine the cause of the interrupt and how to clear theactive interrupt. The UnIIR must be read in order to clear the interrupt prior to exiting theInterrupt Service Routine.
The UARTn RLS interrupt (UnIIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UARTn Rx input: overrun error(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UARTn Rx error
condition that set the interrupt can be observed via U0LSR[4:1]. The interrupt is cleared
upon an UnLSR read.

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The UARTn RDA interrupt (UnIIR[3:1] = 010) shares the second level priority with the CTI
interrupt (UnIIR[3:1] = 110). The RDA is activated when the UARTn Rx FIFO reaches thetrigger level defined in UnFCR[7:6] and is reset when the UARTn Rx FIFO depth falls
below the trigger level. When the RDA interrupt goes active, the CPU can read a block ofdata defined by the trigger level.
The CTI interrupt (UnIIR[3:1] = 110) is a second level interrupt and is set when the UARTn
Rx FIFO contains at least one character and no UARTn Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UARTn Rx FIFO activity (read or write of UARTn RSR) willclear the interrupt. This interrupt is intended to flush the UARTn RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
wished to send a 105 character message and the trigger level was 10 characters, theCPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
Table 311: UARTn Interrupt Handling
U0IIR[3:0] Priority Interrupt Typevalue[1]Interrupt Source

Interrupt Reset

0001

None

UnLSR Read[2]

-

None

0110

Highest RX Line Status/ ErrorOE[2] or PE[2] or FE[2] or BI[2]0100

Second RX Data
Available

Rx data available or trigger level reached UnRBR Read[3]in FIFO (UnFCR0=1)
or UARTn FIFO
drops below
trigger level

1100

Second Character
Time-out
indication

Minimum of one character in the Rx
UnRBR Read[3]FIFO and no character input or removed
during a time period depending on how
many characters are in FIFO and what
the trigger level is set at (3.5 to 4.5
character times).
The exact time will be:[(word length) × 7 - 2] × 8 + [(trigger level- number of characters) × 8 + 1] RCLKs

0010

Third

THRE

THRE[2]

UnIIR Read (ifsource ofinterrupt) or
THR write[4][1]

Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.

[2]

For details see Section 14–3.8 “UARTn Line Status Register (U0LSR - 0xE000 C014, U2LSR 0xE007 8014, U3LSR - 0xE007 C014, Read Only)”[3]

For details see Section 14–14.3.1 “UARTn Receiver Buffer Register (U0RBR - 0xE000 C000, U2RBR 0xE007 8000, U3RBR - 0xE007 C000 when DLAB = 0, Read Only)”[4]

For details see Section 14–3.5 “UARTn Interrupt Identification Register (U0IIR - 0xE000 C008, U2IIR 0xE007 8008, U3IIR - 0x7008 C008, Read Only)” and Section 14–3.2 “UARTn Transmit Holding Register(U0THR - 0xE000 C000, U2THR - 0xE007 8000, U3THR - 0xE007 C000 when DLAB = 0, Write Only)”

The UARTn THRE interrupt (UnIIR[3:1] = 001) is a third level interrupt and is activatedwhen the UARTn THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UARTn THR FIFO a chance tofill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit wheneverUM10211_1

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THRE = 1 and there have not been at least two characters in the UnTHR at one timesince the last THRE = 1 event. This delay is provided to give the CPU time to write data to
UnTHR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UARTn THR FIFO has held two or more characters at one time andcurrently, the UnTHR is empty. The THRE interrupt is reset when a UnTHR write occurs ora read of the UnIIR occurs and the THRE is the highest interrupt (UnIIR[3:1] = 001).

3.6 UARTn FIFO Control Register (U0FCR - 0xE000 C008, U2FCR 0xE007 8008, U3FCR - 0xE007 C008, Write Only)
The UnFCR controls the operation of the UARTn Rx and TX FIFOs.
Table 312: UARTn FIFO Control Register (U0FCR - address 0xE000 C008,
U2FCR - 0xE007 8008, U3FCR - 0xE007 C008, Write Only) bit description
Bit

SymbolValue

0

FIFO Enable 0

Description

Reset ValueUARTn FIFOs are disabled. Must not be used in the 0
application.

1

Active high enable for both UARTn Rx and TX
FIFOs and UnFCR[7:1] access. This bit must be set
for proper UARTn operation. Any transition on thisbit will automatically clear the UARTn FIFOs.

RX FIFOReset

0

No impact on either of UARTn FIFOs.

1

Writing a logic 1 to UnFCR[1] will clear all bytes in
UARTn Rx FIFO and reset the pointer logic. This bit
is self-clearing.

TX FIFOReset

0

No impact on either of UARTn FIFOs.

1

Writing a logic 1 to UnFCR[2] will clear all bytes in
UARTn TX FIFO and reset the pointer logic. This bit
is self-clearing.

5:3

-

0

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is
not defined.

NA

7:6

RX Trigger
Level

These two bits determine how many receiver
UARTn FIFO characters must be written before aninterrupt is activated.

0

1

2

00

Trigger level 0 (1 character or 0x01)

01

Trigger level 1 (4 characters or 0x04)

10

Trigger level 2 (8 characters or 0x08)

11

Trigger level 3 (14 characters or 0x0E)

00

3.7 UARTn Line Control Register (U0LCR - 0xE000 C00C, U2LCR 0xE007 800C, U3LCR - 0xE007 C00C)The UnLCR determines the format of the data character that is to be transmitted or
received.

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Chapter 14: LPC2300 UART0, 2, 3

Table 313: UARTn Line Control Register (U0LCR - address 0xE000 C00C,U2LCR - 0xE007 800C, U3LCR - 0xE007 C00C) bit description
Bit

Symbol

1:0 Word Length
Select2
3

Stop Bit SelectParity Enable

5:4 Parity Select

6

7

Break Control

Divisor Latch
Access Bit(DLAB)

Value Description

Reset
Value

00

5 bit character length

001

6 bit character length

10

7 bit character length11

8 bit character length0

1 stop bit.

1

2 stop bits (1.5 if UnLCR[1:0]=00).

0

Disable parity generation and checking.

1

Enable parity generation and checking.

00

Odd parity. Number of 1s in the transmitted character andthe attached parity bit will be odd.

01

Even Parity. Number of 1s in the transmitted character andthe attached parity bit will be even.

10

Forced "1" stick parity.

11

Forced "0" stick parity.

0

Disable break transmission.

1

Enable break transmission. Output pin UART0 TXD isforced to logic 0 when UnLCR[6] is active high.

0

Disable access to Divisor Latches.

1

Enable access to Divisor Latches.

0
0
0

0

0

3.8 UARTn Line Status Register (U0LSR - 0xE000 C014, U2LSR 0xE007 8014, U3LSR - 0xE007 C014, Read Only)
The UnLSR is a read-only register that provides status information on the UARTn TX andRX blocks.
Table 314: UARTn Line Status Register (U0LSR - address 0xE000 C014,
U2LSR - 0xE007 8014, U3LSR - 0xE007 C014, Read Only) bit description
Bit Symbol
01Receiver
Data Ready(RDR)

Value Description
UnLSR0 is set when the UnRBR holds an unread characterand is cleared when the UARTn RBR FIFO is empty.
0

UnRBR is empty.

1

UnRBR contains valid data.

Overrun Error(OE)

The overrun error condition is set as soon as it occurs. An
UnLSR read clears UnLSR1. UnLSR1 is set when UARTn
RSR has a new character assembled and the UARTn RBRFIFO is full. In this case, the UARTn RBR FIFO will not be
overwritten and the character in the UARTn RSR will be lost.
0Overrun error status is inactive.

1

Overrun error status is active.

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0

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Table 314: UARTn Line Status Register (U0LSR - address 0xE000 C014,
U2LSR - 0xE007 8014, U3LSR - 0xE007 C014, Read Only) bit description
Bit Symbol
2

Value Description

Parity Error
(PE)

Reset
Value

When the parity bit of a received character is in the wrong
state, a parity error occurs. An UnLSR read clears UnLSR[2].
Time of parity error detection is dependent on UnFCR[0].

0Note: A parity error is associated with the character at the topof the UARTn RBR FIFO.

3

0

Parity error status is inactive.

1

Parity error status is active.

Framing Error(FE)

When the stop bit of a received character is a logic 0, a
framing error occurs. An UnLSR read clears UnLSR[3]. The
time of the framing error detection is dependent on UnFCR0.
Upon detection of a framing error, the Rx will attempt toresynchronize to the data and assume that the bad stop bit isactually an early start bit. However, it cannot be assumed thatthe next received byte will be correct even if there is no
Framing Error.

0

Note: A framing error is associated with the character at the
top of the UARTn RBR FIFO.

4

0

Framing error status is inactive.

1

Framing error status is active.

Break
Interrupt(BI)

When RXDn is held in the spacing state (all 0’s) for one full0
character transmission (start, data, parity, stop), a breakinterrupt occurs. Once the break condition has been detected,
the receiver goes idle until RXDn goes to marking state (all1’s). An UnLSR read clears this status bit. The time of break
detection is dependent on UnFCR[0].
Note: The break interrupt is associated with the character at
the top of the UARTn RBR FIFO.

5

6

7

Transmitter
Holding
Register
Empty(THRE))

0

Break interrupt status is inactive.

1

Break interrupt status is active.
THRE is set immediately upon detection of an empty UARTn
THR and is cleared on a UnTHR write.

0

UnTHR contains valid data.

1

UnTHR is empty.
TEMT is set when both UnTHR and UnTSR are empty; TEMT 1
is cleared when either the UnTSR or the UnTHR contain valid
data.

Transmitter
Empty(TEMT)0

UnTHR and/or the UnTSR contains valid data.

1

UnTHR and the UnTSR are empty.

Error in RX
FIFO(RXFE)UnLSR[7] is set when a character with a Rx error such as
framing error, parity error or break interrupt, is loaded into the
UnRBR. This bit is cleared when the UnLSR register is readand there are no subsequent errors in the UARTn FIFO.
0

UnRBR contains no UARTn RX errors or UnFCR[0]=0.

1

UARTn RBR contains at least one UARTn RX error.

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Chapter 14: LPC2300 UART0, 2, 3

3.9 UARTn Scratch Pad Register (U0SCR - 0xE000 C01C, U2SCR 0xE007 801C U3SCR - 0xE007 C01C)The UnSCR has no effect on the UARTn operation. This register can be written and/or
read at user’s discretion. There is no provision in the interrupt interface that would indicate
to the host that a read or write of the UnSCR has occurred.
Table 315: UARTn Scratch Pad Register (U0SCR - address 0xE000 C01C,U2SCR - 0xE007 801C, U3SCR - 0xE007 C01C) bit description
Bit Symbol Description

Reset
Value

7:0 Pad0x00

A readable, writable byte.

3.10 UARTn Auto-baud Control Register (U0ACR - 0xE000 C020, U2ACR 0xE007 8020, U3ACR - 0xE007 C020)
The UARTn Auto-baud Control Register (UnACR) controls the process of measuring theincoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
Table 316: UARTn Auto-baud Control Register (U0ACR - 0xE000 C020, U2ACR - 0xE007 8020,
U3ACR - 0xE007 C020) bit description
Bit

Symbol

0

Start

1

Value Description
This bit is automatically cleared after auto-baudcompletion.
Auto-baud stop (auto-baud is not running).

1

Auto-baud start (auto-baud is running).Auto-baud run
bit. This bit is automatically cleared after auto-baudcompletion.

Mode

Auto-baud mode select bit.
1

AutoRestart 00Mode 0.
Mode 1.
No restart.

0

1

Restart in case of time-out (counter restarts at next
UART0 Rx falling edge)

0

NA

Reserved, user software should not write ones to0reserved bits. The value read from a reserved bit is notdefined.

7:3

-

8

ABEOIntClr

End of auto-baud interrupt clear bit (write only
accessible). Writing a 1 will clear the corresponding
interrupt in the UnIIR. Writing a 0 has no impact.

09

ABTOIntClr

Auto-baud time-out interrupt clear bit (write only
accessible). Writing a 1 will clear the corresponding
interrupt in the UnIIR. Writing a 0 has no impact.

0

31:10 -

NA

Reserved, user software should not write ones to0reserved bits. The value read from a reserved bit is notdefined.

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Chapter 14: LPC2300 UART0, 2, 3

14.3.10.1

Auto-baud
The UARTn auto-baud function can be used to measure the incoming baud-rate based onthe ”AT" protocol (Hayes command). If enabled the auto-baud feature will measure the bittime of the receive data stream and set the divisor latch registers UnDLM and UnDLL
accordingly.
Auto-baud is started by setting the UnACR Start bit. Auto-baud can be stopped by clearing
the UnACR Start bit. The Start bit will clear once auto-baud has finished and reading the
bit will return the status of auto-baud (pending/finished).
Two auto-baud measuring modes are available which can be selected by the UnACR
Mode bit. In mode 0 the baud-rate is measured on two subsequent falling edges of the
UARTn Rx pin (the falling edge of the start bit and the falling edge of the least significantbit). In mode 1 the baud-rate is measured between the falling edge and the subsequentrising edge of the UARTn Rx pin (the length of the start bit).
The UnACR AutoRestart bit can be used to automatically restart baud-rate measurement
if a time-out occurs (the rate measurement counter overflows). If this bit is set the ratemeasurement will restart at the next falling edge of the UARTn Rx pin.
The auto-baud function can generate two interrupts.

• The UnIIR ABTOInt interrupt will get set if the interrupt is enabled (UnIER ABToIntEn
is set and the auto-baud rate measurement counter overflows).

• The UnIIR ABEOInt interrupt will get set if the interrupt is enabled (UnIER ABEOIntEn
is set and the auto-baud has completed successfully).
The auto-baud interrupts have to be cleared by setting the corresponding UnACRABTOIntClr and ABEOIntEn bits.
Typically the fractional baud-rate generator is disabled (DIVADDVAL = 0) during
auto-baud. However, if the fractional baud-rate generator is enabled (DIVADDVAL > 0), it
is going to impact the measuring of UARTn Rx pin baud-rate, but the value of the UnFDR
register is not going to be modified after rate measurement. Also, when auto-baud is used,
any write to UnDLM and UnDLL registers should be done before UnACR register write.
The minimum and the maximum baudrates supported by UARTn are function of pclk,
number of data bits, stop bits and parity bits.
(7)
2 × P CLK
16 × 2 15

PCLK
16 × ( 2 + databits + paritybits + stopbits )ratemin = ------------------------- ≤ UART n baudrate ≤ ------------------------------------------------------------------------------------------------------------ = ratemax

14.3.10.2

Auto-baud modes
When the software is expecting an ”AT" command, it configures the UARTn with the
expected character format and sets the UnACR Start bit. The initial values in the divisor
latches UnDLM and UnDLM don‘t care. Because of the ”A" or ”a" ASCII coding(”A" = 0x41, ”a" = 0x61), the UARTn Rx pin sensed start bit and the LSB of the expectedcharacter are delimited by two falling edges. When the UnACR Start bit is set, theauto-baud protocol will execute the following phases:

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Chapter 14: LPC2300 UART0, 2, 3

1. On UnACR Start bit setting, the baud-rate measurement counter is reset and the
UARTn UnRSR is reset. The UnRSR baud rate is switch to the highest rate.
2. A falling edge on UARTn Rx pin triggers the beginning of the start bit. The ratemeasuring counter will start counting pclk cycles optionally pre-scaled by thefractional baud-rate generator.
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input withthe frequency of the (fractional baud-rate pre-scaled) UARTn input clock,guaranteeing the start bit is stored in the UnRSR.
4. During the receipt of the start bit (and the character LSB for mode = 0) the rate
counter will continue incrementing with the pre-scaled UARTn input clock (pclk).
5. If Mode = 0 then the rate counter will stop on next falling edge of the UARTn Rx pin. If
Mode = 1 then the rate counter will stop on the next rising edge of the UARTn Rx pin.
6. The rate counter is loaded into UnDLM/UnDLL and the baud-rate will be switched tonormal operation. After setting the UnDLM/UnDLL the end of auto-baud interrupt
UnIIR ABEOInt will be set, if enabled. The UnRSR will now continue receiving theremaining bits of the ”A/a" character.

'A' (0x41) or 'a' (0x61)
start

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

parity stop

UARTn RXstart bit

LSB of 'A' or 'a'

U0ACR start
rate counter
16xbaud_rate

16 cycles

16 cyclesa. Mode 0 (start bit and LSB are used for auto-baud)

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Chapter 14: LPC2300 UART0, 2, 3

'A' (0x41) or 'a' (0x61)
start

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

parity stop

UARTn RXstart bit

LSB of 'A' or 'a'

U1ACR start
rate counter
16xbaud_rate

16 cyclesb. Mode 1 (only start bit is used for auto-baud)
Fig 56. Autobaud a) mode 0 and b) mode 1 waveform

3.11 IrDA Control Register for UART3 Only (U3ICR - 0xE007 C024)
The IrDA Control Register enables and configures the IrDA mode for UART3 only. The
value of U3ICR should not be changed while transmitting or receiving data, or data loss or
corruption may occur.
Table 317: IrDA Control Register for UART3 only (U3ICR - address 0xE007 C024) bit
description
Bit

SymbolValue Description

Reset value0

IrDAEn0

IrDA mode on UART3 is disabled, UART3 acts as astandard UART.

0

1

IrDA mode on UART3 is enabled.

1

IrDAInv

When 1, the serial input is inverted. This has no effect 0on the serial output. When 0, the serial input is notinverted.

2

FixPulseEn

When 1, enabled IrDA fixed pulse width mode.

0

5:3

PulseDiv

Configures the pulse when FixPulseEn = 1. See text
below for details.

0

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is
not defined.

0

31:6 -NA

The PulseDiv bits in U3ICR are used to select the pulse width when the fixed pulse widthmode is used in IrDA mode (IrDAEn = 1 and FixPulseEn = 1). The value of these bits
should be set so that the resulting pulse width is at least 1.63 µs. Table 14–318 shows thepossible pulse widths.
Table 318: IrDA Pulse Width
FixPulseEn

PulseDiv

IrDA Transmitter Pulse width (µs)

0x3 / (16 × baud rate)

10

2 × TPCLK

1

1

4 × TPCLK

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Chapter 14: LPC2300 UART0, 2, 3

Table 318: IrDA Pulse Width
FixPulseEn

PulseDiv

IrDA Transmitter Pulse width (µs)

12

8 × TPCLK

1

3

16 × TPCLK

1

432 × TPCLK

1

564 × TPCLK

1

6128 × TPCLK

1

7

256 × TPCLK

3.12 UARTn Fractional Divider Register (U0FDR - 0xE000 C028, U2FDR 0xE007 8028, U3FDR - 0xE007 C028)
The UARTn Fractional Divider Register (UnFDR) controls the clock pre-scaler for thebaud rate generation and can be read and written at user’s discretion.
Table 319: UARTn Fractional Divider Register (U0FDR - address 0xE000 C028,
U2FDR - 0xE007 8028, U3FDR - 0xE007 C028) bit description
Bit

Function

Value Description

Reset
value

3:0

DIVADDVAL

0

Baud-rate generation pre-scaler divisor value. If this field is 00, fractional baud-rate generator will not impact the UARTn
baudrate.

7:4

MULVAL

1

Baud-rate pre-scaler multiplier value. This field must be
1
greater or equal 1 for UARTn to operate properly,
regardless of whether the fractional baud-rate generator isused or not.

31:8

-

NA

Reserved, user software should not write ones to reserved 0
bits. The value read from a reserved bit is not defined.

This register controls the clock pre-scaler for the baud rate generation. The clock can bepre-scaled by a value of:(8)
MULVAL-----------------------------------------------------------------------( MULVAL + DIVADDVAL )UARTn baud-rate can be calculated as:
(9)

PCLK
UARTn baudrate = ------------------------------------------------------------------------------------DIVADDVAL
16 × UnDL × ⎛ 1 + -----------------------------------⎞⎝MULVAL ⎠Where PCLK is the peripheral clock, UnDL is value determined by the UnDLM and UnDLL
registers (UnDL = 256 × UnDLM + UnDLL), and DIVADDVAL and MULVAL are UARTn
fractional baud-rate generator specific parameters.
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The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 0 < MULVAL ≤ 15
2. 0 ≤ DIVADDVAL ≤ 15
If the UnFDR register value does not comply to these two requests then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled
and the clock will not be divided.
Remark: f DIVADDVAL>0, UnDL must be UnDL ≥ 0x0002 or the UART will not operate at
the desired baud-rate!
The value of the UnFDR should not be modified while transmitting/receiving data or data
may be lost or corrupted.
Usage Note: For practical purposes, UARTnbaudrate formula can be written in a way that
identifies the part of a UART baudrate generated without the fractional baud-rate
generator, and the correction factor that this module adds:
(10)
PCLK
MULVAL
UARTn baudrate = ---------------------------- × -----------------------------------------------------------------------16 × UnDL ( MULVAL + DIVADDVAL )Based on this representation, fractional baud-rate generator contribution can also be
described as a prescaling with a factor of MULVAL/(MULVAL+DIVADDVAL).

3.13 UARTn Baudrate Calculation
Example 1: Using UARTnbaudrate formula from above, it can be determined that systemwith pclk = 20 MHz, UnDL = 130 (UnDLM = 0x00 and UnDLL = 0x82), DIVADDVAL = 0
and MULVAL = 1 will enable UARTn with UARTnbaudrate = 9615 bauds.
Example 2: Using UARTnbaudrate formula from above, it can be determined that systemwith PCLK = 20 MHz, UnDL = 93 (UnDLM = 0x00 and UnDLL = 0x5D), DIVADDVAL = 2
and MULVAL = 5 will enable UARTn with UARTnbaudrate = 9600 bauds.
Additonal examples of Baud Rate Vales: Table 14–320 shows additional examples ofbaud rate for PCLK = 20 MHz
Table 320: Baud-rates available when using 20 MHz peripheral clock (PCLK = 20 MHz)
Desired
MULVAL = 0 DIVADDVAL = 0
baud-rate UnDLM:UnDLL% error[3]hex[2] dec[1]Optimal MULVAL & DIVADDVALUnDLM:UnDLL
dec[1]% error[3]

MULDIV
MULDIV + DIVADDVAL

50

61A8

25000

0.000025000

1/(1+0)0.0000

75

411B

16667

0.002012500

3/(3+1)0.0000

110

2C64

11364

0.00326250

11/(11+9)0.0000

134.5

244E

9294

0.00343983

3/(3+4)0.0001

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Chapter 14: LPC2300 UART0, 2, 3

Table 320: Baud-rates available when using 20 MHz peripheral clock (PCLK = 20 MHz)
Desired
MULVAL = 0 DIVADDVAL = 0
baud-rate UnDLM:UnDLL% error[3]hex[2] dec[1]Optimal MULVAL & DIVADDVALUnDLM:UnDLL
dec[1]

Fractional
pre-scaler value% error[3]

MULDIV
MULDIV + DIVADDVAL

150

208D

8333

0.00406250

3/(3+1)0.0000

300

1047

4167

0.00803125

3/(3+1)0.0000

600

0823

2083

0.01601250

3/(3+2)0.0000

1200

0412

1042

0.0320625

3/(3+2)0.0000

1800

02B6

694

0.0640625

9/(9+1)0.0000

2000

0271

625

0.0000625

1/(1+0)0.0000

2400

0209

521

0.0320250

12/(12+13)

0.0000

3600

015B

347

0.0640248

5/(5+2)0.0064

4800

0104

260

0.1600125

12/(12+13)

0.0000

7200

00AE

174

0.2240124

5/(5+2)0.0064

9600

0082

130

0.160093

5/(5+2)0.0064

19200

0041

65

0.160031

10/(10+11)

0.0064

38400

0021

33

1.376012

7/(7+12)0.0594

56000

0021

22

1.440013

7/(7+5)0.0160

57600

0016

22

1.376019

7/(7+1)0.0594112000000B

111.44006

7/(7+6)0.1600115200000B

111.37604

7/(7+12)0.05942240000006

67.52003

7/(7+6)0.16004480000003

37.52002

5/(5+2)0.3520[1]

Values in the row represent decimal equivalent of a 16 bit long content (DLM:DLL).

[2]

Values in the row represent hex equivalent of a 16 bit long content (DLM:DLL).

[3]

Refers to the percent error between desired and actual baud-rate.

3.14 UARTn Transmit Enable Register (U0TER - 0xE000 C030, U2TER 0xE007 8030, U3TER - 0xE007 C030)
LPC2300’s UnTER enables implementation of software flow control. When TXEn=1,
UARTn transmitter will keep sending data as long as they are available. As soon as TXEn
becomes 0, UARTn transmission will stop.
Table 14–321 describes how to use TXEn bit in order to achieve software flow control.

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Chapter 14: LPC2300 UART0, 2, 3

Table 321: UARTn Transmit Enable Register (U0TER - address 0xE000 C030,
U2TER - 0xE007 8030, U3TER - 0xE007 C030) bit description
Bit

SymbolDescription

Reset
Value

6:0

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

7

TXEN

When this bit is 1, as it is after a Reset, data written to the THR is output 1
on the TXD pin as soon as any preceding data has been sent. If this bit
is cleared to 0 while a character is being sent, the transmission of thatcharacter is completed, but no further characters are sent until this bit isset again. In other words, a 0 in this bit blocks the transfer of charactersfrom the THR or TX FIFO into the transmit shift register. Software
implementing software-handshaking can clear this bit when it receives
an XOFF character (DC3). Software can set this bit again when it
receives an XON (DC1) character.

4. Architecture
The architecture of the UARTs 0, 2 and 3 are shown below in the block diagram.
The APB interface provides a communications link between the CPU or host and the
UART.
The UARTn receiver block, UnRX, monitors the serial input line, RXDn, for valid input.
The UARTn RX Shift Register (UnRSR) accepts valid characters via RXDn. After a validcharacter is assembled in the UnRSR, it is passed to the UARTn RX Buffer Register FIFO
to await access by the CPU or host via the generic host interface.
The UARTn transmitter block, UnTX, accepts data written by the CPU or host and buffers
the data in the UARTn TX Holding Register FIFO (UnTHR). The UARTn TX Shift Register(UnTSR) reads the data stored in the UnTHR and assembles the data to transmit via theserial output pin, TXDn.
The UARTn Baud Rate Generator block, UnBRG, generates the timing enables used by
the UARTn TX block. The UnBRG clock input source is the APB clock (PCLK). The main
clock is divided down per the divisor specified in the UnDLL and UnDLM registers. This
divided down clock is a 16x oversample clock, NBAUDOUT.
The interrupt interface contains registers UnIER and UnIIR. The interrupt interface
receives several one clock wide enables from the UnTX and UnRX blocks.
Status information from the UnTX and UnRX is stored in the UnLSR. Control information
for the UnTX and UnRX is stored in the UnLCR.

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UnTX

UnTHR

NTXRDY
UnTSR

TXDn

UnBRG

UnDLL

NBAUDOUT

UnDLM

RCLK

UnRX

NRXRDYINTERRUPTUnRBRUnINTR

UnRSR

RXDn

UnIER

UnIIR

UnFCR

UnLSR
UnSCR
UnLCR

PA[2:0]PSEL
PSTB
PWRITE
PD[7:0]APBINTERFACE

DDIS

AR
MR
PCLK

Fig 57. LPC2300 UART0, 2 and 3 block diagram

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Chapter 15: Universal Asynchronous Receiver Transmitter(UART) 1
Rev. 01 — 6 July 2007

User manual

1. Features• UART1 is identical to UART0/2/3, with the addition of a modem interface.
• 16 byte Receive and Transmit FIFOs.
• Register locations conform to ‘550 industry standard.
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
• Built-in baud rate generator.
• Standard modem interface signals included (CTS, DCD, DTS, DTR, RI, RTS).
• LPC2300 UART1 provides mechanism that enables implementation of either softwareor hardware flow control.

2. Pin description
Table 322: UART1 Pin Description
Pin

Type

RXD1 Input

Description
Serial Input. Serial receive data.

TXD1 Output Serial Output. Serial transmit data.
CTS1 Input

Clear To Send. Active low signal indicates if the external modem is ready toaccept transmitted data via TXD1 from the UART1. In normal operation of themodem interface (U1MCR[4] = 0), the complement value of this signal is stored in
U1MSR[4]. State change information is stored in U1MSR[0] and is a source for apriority level 4 interrupt, if enabled (U1IER[3] = 1).
Only CTS1 is also used in auto-cts mode to control the UART1 transmitter.
Clear to send. CTS1 is an asynchronous, active low modem status signal. Its
condition can be checked by reading bit 4 (CTS) of the modem status register. Bit
0 (DCTS) of the Modem Status Register (MSR) indicates that CTS1 has changed
states since the last read from the MSR. If the modem status interrupt is enabled
when CTS1 changes levels and the auto-cts mode is not enabled, an interrupt isgenerated. CTS1 is also used in the auto-cts mode to control the transmitter.
(IP_3106)

DCD1 Input

Data Carrier Detect. Active low signal indicates if the external modem hasestablished a communication link with the UART1 and data may be exchanged. In
normal operation of the modem interface (U1MCR[4]=0), the complement value of
this signal is stored in U1MSR[7]. State change information is stored in U1MSR3
and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1).

DSR1 Input

Data Set Ready. Active low signal indicates if the external modem is ready toestablish a communications link with the UART1. In normal operation of themodem interface (U1MCR[4] = 0), the complement value of this signal is stored in
U1MSR[5]. State change information is stored in U1MSR[1] and is a source for apriority level 4 interrupt, if enabled (U1IER[3] = 1).

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Table 322: UART1 Pin Description
Pin

Type

Description

DTR1 Output Data Terminal Ready. Active low signal indicates that the UART1 is ready toestablish connection with external modem. The complement value of this signal isstored in U1MCR[0].
RI1

Input

Ring Indicator. Active low signal indicates that a telephone ringing signal has
been detected by the modem. In normal operation of the modem interface(U1MCR[4] = 0), the complement value of this signal is stored in U1MSR[6]. Statechange information is stored in U1MSR[2] and is a source for a priority level 4
interrupt, if enabled (U1IER[3] = 1).

RTS1 Output Request To Send. Active low signal indicates that the UART1 would like totransmit data to the external modem. The complement value of this signal isstored in U1MCR[1].
Only in the auto-rts mode uses RTS1 to control the transmitter FIFO thresholdlogic.
Request to send. RTS1 is an active low signal informing the modem or data set
that the UART is ready to receive data. RTS1 is set to the active (low) level by
setting the RTS modem control register bit and is set to the inactive (high) level
either as a result of a system reset or during loop-back mode operations or byclearing bit 1 (RTS) of the MCR. In the auto-rts mode, RTS1 is controlled by thetransmitter FIFO threshold logic. (IP_3106)

3. Register description
UART1 contains registers organized as shown in Table 15–323. The Divisor Latch AccessBit (DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches.

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NXP Semiconductors

UM10211_1

User manual

Table 323: UART1 register map
Name

Description Bit functions and addresses
MSB
BIT7

LSB
BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

Acces Resets
Value[

Address1]

BIT0

Receiver
BufferRegister

8 bit Read Data

RONA

0xE001 0000
(DLAB=0)U1THR

Transmit
Holding
Register

8 bit Write Data

WO

NA

0xE001 0000
(DLAB=0)U1DLL

Divisor Latch
LSB

8 bit Data

R/W

0x01

0xE001 0000
(DLAB=1)U1DLM

Divisor Latch
MSB

8 bit Data

R/W

0x00

0xE001 0004
(DLAB=1)U1IER

Interrupt
EnableRegister

EnableEnable R/W
Autobaud End ofTime-Out Autobaud
Interrupt Interrupt

0x00

0xE001 0004
(DLAB=0)0x01

0xE001 0008

Rev. 01 — 6 July 2007

U1RBR

Reserved

EnableCTS
Interrupt
U1IIR

Interrupt ID
Register0

EnableModem
Statusinterrupt

EnableRX LineStatusInterrupt

Reserved
FIFOs Enabled

0

RX Trigger

Enable
THRE
Interrupt

EnableRX Data
Available
Interrupt

ABTO Itn ABEO int RO
IIR3

Reserved

U1LCR

Line Control
Register

DLAB

Set
Break

Stick
ParityEven
ParitySelect

U1MCR

Modem
Control
Register

CTSen

RTSen

0

Loop
Back

U1LSR

Line Status
Register

RX
FIFO
Error

TEMT

THRE

BI

FE

U1MSR

Modem
StatusRegister

DCD

RI

DSR

CTS

Delta
DCD

ParityEnable

IIR0

TX FIFOReset

RX FIFOReset

FIFO
EnableWO

0x00

0xE001 0008

Numberof Stop
Bits

Word Length Select

R/W

0x00

0xE001 000C

0

RTS

DTR

R/W

0x00

0xE001 0010

PE

OE

DR

RO

0x60

0xE001 0014

Trailing
Edge RI

Delta
DSR

Delta
CTS

RO

0x00

0xE001 0018

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FIFO Control
Register

IIR1

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U1FCR

IIR2

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Name

Description Bit functions and addresses
MSB

U1SCR

Scratch Pad
Register

U1ACR

Autobaud
Control
Register

U1FDR

U1TER

Rev. 01 — 6 July 2007[1]

8 bit Data
Reserved [31:10]
Reserved [7:3]

Fractional
Divider
RegisterTransmit
EnableRegister

LSB

Auto
Reset

ABTO
IntClr

ABEO
IntClr

Mode

Start

Reserved [31:8]
MulvalTXEN

Acces Resets
Value[NXP Semiconductors

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Table 323: UART1 register map …continued
Address

1]

R/W

0x00

0xE001 001C

R/W

0x00

0xE001 0020

R/W

0x10

0xE001 0028

R/W

0x80

0xE001 0030

DivAddVal
Reserved

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

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Chapter 15: LPC2300 UART1

3.1 UART1 Receiver Buffer Register (U1RBR - 0xE001 0000, when
DLAB = 0 Read Only)
The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, theunused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the
U1RBR. The U1RBR is always Read Only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching thevalid pair of received byte and its status bits is first to read the content of the U1LSR
register, and then to read a byte from the U1RBR.
Table 324: UART1 Receiver Buffer Register (U1RBR - address 0xE001 0000 when DLAB = 0,
Read Only) bit description
Bit

SymbolDescription

Reset Value

7:0

RBR

The UART1 Receiver Buffer Register contains the oldest
received byte in the UART1 RX FIFO.

undefined

3.2 UART1 Transmitter Holding Register (U1THR - 0xE001 0000 when
DLAB = 0, Write Only)
The U1THR is the top byte of the UART1 TX FIFO. The top byte is the newest character in
the TX FIFO and can be written via the bus interface. The LSB represents the first bit totransmit.
The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the
U1THR. The U1THR is always Write Only.
Table 325: UART1 Transmitter Holding Register (U1THR - address 0xE001 0000 when
DLAB = 0, Write Only) bit description
Bit

SymbolDescription

Reset Value

7:0

THR

Writing to the UART1 Transmit Holding Register causes the data NA
to be stored in the UART1 transmit FIFO. The byte will be sent
when it reaches the bottom of the FIFO and the transmitter isavailable.

3.3 UART1 Divisor Latch LSB and MSB Registers (U1DLL - 0xE001 0000
and U1DLM - 0xE001 0004, when DLAB = 1)
The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value
used to divide the APB clock (PCLK) in order to produce the baud rate clock, which mustbe 16x the desired baud rate (Equation 15–11). The U1DLL and U1DLM registers
together form a 16 bit divisor where U1DLL contains the lower 8 bits of the divisor and
U1DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001
value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in U1LCR
must be one in order to access the UART1 Divisor Latches. Details on how to select theright value for U1DLL and U1DLM can be found later on in this chapter.

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(11)

pclk
UART1 baudrate = -------------------------------------------------------------------------------16 × ( 256 × U1DLM + U1DLL )Table 326: UART1 Divisor Latch LSB Register (U1DLL - address 0xE001 0000 when
DLAB = 1) bit description
Bit

SymbolDescription

Reset Value

7:0

DLLSB

The UART1 Divisor Latch LSB Register, along with the U1DLM
register, determines the baud rate of the UART1.

0x01

Table 327: UART1 Divisor Latch MSB Register (U1DLM - address 0xE001 0004 when
DLAB = 1) bit description
Bit

SymbolDescription

Reset Value

7:0

DLMSB

The UART1 Divisor Latch MSB Register, along with the U1DLL
register, determines the baud rate of the UART1.

0x00

3.4 UART1 Interrupt Enable Register (U1IER - 0xE001 0004, when
DLAB = 0)
The U1IER is used to enable the four UART1 interrupt sources.
Table 328: UART1 Interrupt Enable Register (U1IER - address 0xE001 0004 when DLAB = 0)
bit description
Bit

Symbol0

RBRInterrupt
Enable

1

2

3

6:4

THRE
Interrupt
EnableRX LineInterrupt
EnableModem
StatusInterrupt
Enable-Value

Description

Reset
Value

U1IER[0] enables the Receive Data Available interrupt for
UART1. It also controls the Character Receive Time-out
interrupt.

00Disable the RDA interrupts.

1

Enable the RDA interrupts.
U1IER[1] enables the THRE interrupt for UART1. The
status of this interrupt can be read from U1LSR[5].

0Disable the THRE interrupts.

1

Enable the THRE interrupts.
U1IER[2] enables the UART1 RX line status interrupts.
The status of this interrupt can be read from U1LSR[4:1].

0

Disable the RX line status interrupts.

1

Enable the RX line status interrupts.
U1IER[3] enables the modem interrupt. The status of thisinterrupt can be read from U1MSR[3:0].

0
1

0

0

Disable the modem interrupt.
Enable the modem interrupt.
Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

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Chapter 15: LPC2300 UART1

Table 328: UART1 Interrupt Enable Register (U1IER - address 0xE001 0004 when DLAB = 0)
bit description
Bit

Symbol7

CTS
Interrupt
EnableValue

Description

Reset
Value

If auto-cts mode is enabled this bit enables/disables the0modem status interrupt generation on a CTS1 signaltransition. If auto-cts mode is disabled a CTS1 transition
will generate an interrupt if Modem Status Interrupt Enable(U1IER[3]) is set.
In normal operation a CTS1 signal transition will generate
a Modem Status Interrupt unless the interrupt has been
disabled by clearing the U1IER[3] bit in the U1IER register.
In auto-cts mode a transition on the CTS1 bit will trigger aninterrupt only if both the U1IER[3] and U1IER[7] bits are
set.

8

9

0

Disable the CTS interrupt.

1

Enable the CTS interrupt.

ABTOIntEn

U1IER8 enables the auto-baud time-out interrupt.
0

Disable Auto-baud Time-out Interrupt.

1

Enable Auto-baud Time-out Interrupt.

ABEOIntEn

U1IER9 enables the end of auto-baud interrupt.
0

Disable End of Auto-baud Interrupt.

1

Enable End of Auto-baud Interrupt.

31:10 -

0

0

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

3.5 UART1 Interrupt Identification Register (U1IIR - 0xE001 0008, Read
Only)
The U1IIR provides a status code that denotes the priority and source of a pending
interrupt. The interrupts are frozen during an U1IIR access. If an interrupt occurs during
an U1IIR access, the interrupt is recorded for the next U1IIR access.
Table 329: UART1 Interrupt Identification Register (U1IIR - address 0xE001 0008, Read Only)
bit description
Bit

Symbol0

IntStatus

Value Description
Interrupt status. Note that U1IIR[0] is active low. The
pending interrupt can be determined by evaluating
U1IIR[3:1].
0

At least one interrupt is pending.

1

No interrupt is pending.

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Value
1

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Chapter 15: LPC2300 UART1

Table 329: UART1 Interrupt Identification Register (U1IIR - address 0xE001 0008, Read Only)
bit description
Bit

Symbol3:1

IntId

Value Description

Reset
Value

Interrupt identification. U1IER[3:1] identifies an interrupt
corresponding to the UART1 Rx FIFO. All othercombinations of U1IER[3:1] not listed above are reserved(100,101,111).
011

1 - Receive Line Status (RLS).

010

2a - Receive Data Available (RDA).

110

2b - Character Time-out Indicator (CTI).

001

3 - THRE Interrupt.

000

0

4 - Modem Interrupt.

5:4-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

7:6

FIFO Enable

These bits are equivalent to U1FCR[0].

08ABEOInt

End of auto-baud interrupt. True if auto-baud has finishedsuccessfully and interrupt is enabled.

0

9

ABTOInt

Auto-baud time-out interrupt. True if auto-baud has timedout and interrupt is enabled.

0

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

31:10 -

Bit U1IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baudcondition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.
If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus
is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type ofinterrupt and handling as described in Table 15–330. Given the status of U1IIR[3:0], aninterrupt handler routine can determine the cause of the interrupt and how to clear theactive interrupt. The U1IIR must be read in order to clear the interrupt prior to exiting theInterrupt Service Routine.
The UART1 RLS interrupt (U1IIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UART1RX input: overrun error(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART1 Rx error
condition that set the interrupt can be observed via U1LSR[4:1]. The interrupt is cleared
upon an U1LSR read.
The UART1 RDA interrupt (U1IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (U1IIR[3:1] = 110). The RDA is activated when the UART1 Rx FIFO reaches thetrigger level defined in U1FCR7:6 and is reset when the UART1 Rx FIFO depth falls below
the trigger level. When the RDA interrupt goes active, the CPU can read a block of data
defined by the trigger level.
The CTI interrupt (U1IIR[3:1] = 110) is a second level interrupt and is set when the UART1
Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UART1 Rx FIFO activity (read or write of UART1 RSR) willclear the interrupt. This interrupt is intended to flush the UART1 RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
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wished to send a 105 character message and the trigger level was 10 characters, theCPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
Table 330: UART1 Interrupt Handling
U1IIR[3:0] Priority Interrupt
value[1]TypeInterrupt Source

Interrupt
Reset

0001

-

None

-

0110

Highest RX Line
Status /Error

OE[2] or PE[2] or FE[2] or BI[2]U1LSR
Read[2]0100

Second RX Data
Available

Rx data available or trigger level reached in FIFO
(U1FCR0=1)

U1RBR
Read[3] or
UART1FIFO drops
below
trigger level

1100

Second Character Minimum of one character in the RX FIFO and noTime-out character input or removed during a time period
indication depending on how many characters are in FIFO
and what the trigger level is set at (3.5 to 4.5
character times).

None

U1RBR
Read[3]The exact time will be:[(word length) × 7 - 2] × 8 + [(trigger level - numberof characters) × 8 + 1] RCLKs
0010

Third

THRE

THRE[2]U1IIR
Read[4] (ifsource ofinterrupt) or
THR write

0000

FourthModem
StatusCTS or DSR or RI or DCD

MSR Read[1]

Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.

[2]

For details see Section 15–3.10 “UART1 Line Status Register (U1LSR - 0xE001 0014, Read Only)”[3]

For details see Section 15–3.1 “UART1 Receiver Buffer Register (U1RBR - 0xE001 0000, when DLAB = 0
Read Only)”[4]

For details see Section 15–3.5 “UART1 Interrupt Identification Register (U1IIR - 0xE001 0008, Read Only)”and Section 15–3.2 “UART1 Transmitter Holding Register (U1THR - 0xE001 0000 when DLAB = 0, Write
Only)”The UART1 THRE interrupt (U1IIR[3:1] = 001) is a third level interrupt and is activatedwhen the UART1 THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UART1 THR FIFO a chance tofill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the U1THR at one time since
the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U1THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART1 THR FIFO has held two or more characters at one time andcurrently, the U1THR is empty. The THRE interrupt is reset when a U1THR write occurs ora read of the U1IIR occurs and the THRE is the highest interrupt (U1IIR[3:1] = 001).
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It is the lowest priority interrupt and is activated whenever there is any state change on
modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem
input RI will generate a modem interrupt. The source of the modem interrupt can be
determined by examining U1MSR[3:0]. A U1MSR read will clear the modem interrupt.

3.6 UART1 FIFO Control Register (U1FCR - 0xE001 0008, Write Only)
The U1FCR controls the operation of the UART1 RX and TX FIFOs.
Table 331: UART1 FIFO Control Register (U1FCR - address 0xE001 0008, Write Only) bit
description
Bit

SymbolValue Description

Reset
Value

0

FIFO
Enable0

UART1 FIFOs are disabled. Must not be used in the application.

0

1

Active high enable for both UART1 Rx and TX FIFOs andU1FCR[7:1] access. This bit must be set for proper UART1
operation. Any transition on this bit will automatically clear the
UART1 FIFOs.

1

RX FIFO 0
Reset
1

No impact on either of UART1 FIFOs.

TX FIFO 0
Reset
1

No impact on either of UART1 FIFOs.

5:3-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

7:6

RX
Trigger
Level

These two bits determine how many receiver UART1 FIFO
characters must be written before an interrupt is activated.

0

2

0

Writing a logic 1 to U1FCR[1] will clear all bytes in UART1 Rx
FIFO and reset the pointer logic. This bit is self-clearing.
0

Writing a logic 1 to U1FCR[2] will clear all bytes in UART1 TX
FIFO and reset the pointer logic. This bit is self-clearing.

00

Trigger level 0 (1 character or 0x01).

01

Trigger level 1 (4 characters or 0x04).

10

Trigger level 2 (8 characters or 0x08).

11

Trigger level 3 (14 characters or 0x0E).

3.7 UART1 Line Control Register (U1LCR - 0xE001 000C)
The U1LCR determines the format of the data character that is to be transmitted or
received.
Table 332: UART1 Line Control Register (U1LCR - address 0xE001 000C) bit description
Bit

Symbol Value Description

Reset
Value

1:0

Word
LengthSelect02
300

5 bit character length.

01

6 bit character length.

10

7 bit character length.

11

8 bit character length.

Stop Bit
Select0

1 stop bit.

1

2 stop bits (1.5 if U1LCR[1:0]=00).

ParityEnable0Disable parity generation and checking.

1

Enable parity generation and checking.

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Table 332: UART1 Line Control Register (U1LCR - address 0xE001 000C) bit description
Bit

Symbol Value Description

Reset
Value

5:4

ParitySelect

0

6

7

00

Odd parity. Number of 1s in the transmitted character and theattached parity bit will be odd.

01

Even Parity. Number of 1s in the transmitted character and theattached parity bit will be even.

10

Forced "1" stick parity.

11

Forced "0" stick parity.

BreakControl0

Disable break transmission.

1

Enable break transmission. Output pin UART1 TXD is forced tologic 0 when U1LCR[6] is active high.

Divisor
Latch
AccessBit(DLAB)0

Disable access to Divisor Latches.

1

Enable access to Divisor Latches.

00

3.8 UART1 Modem Control Register (U1MCR - 0xE001 0010)
The U1MCR enables the modem loopback mode and controls the modem output signals.
Table 333: UART1 Modem Control Register (U1MCR - address 0xE001 0010) bit description
Bit

Symbol0

DTR
Control

Source for modem output pin, DTR. This bit reads as 0 whenmodem loopback mode is active.

0

1

RTS
Control

Source for modem output pin RTS. This bit reads as 0 whenmodem loopback mode is active.

0

3-2

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

04

Loopback
Mode
Select5-

Value Description

NA

The modem loopback mode provides a mechanism to perform0
diagnostic loopback testing. Serial data from the transmitter isconnected internally to serial input of the receiver. Input pin,
RXD1, has no effect on loopback and output pin, TXD1 is held inmarking state. The four modem inputs (CTS, DSR, RI and DCD)
are disconnected externally. Externally, the modem outputs (RTS,
DTR) are set inactive. Internally, the four modem outputs areconnected to the four modem inputs. As a result of theseconnections, the upper four bits of the U1MSR will be driven by
the lower four bits of the U1MCR rather than the four modem
inputs in normal mode. This permits modem status interrupts tobe generated in loopback mode by writing the lower four bits of
U1MCR.
0

Disable modem loopback mode.

1

Enable modem loopback mode.

NA

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

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value

0

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Chapter 15: LPC2300 UART1

Table 333: UART1 Modem Control Register (U1MCR - address 0xE001 0010) bit description
Bit

SymbolValue Description

Reset
value

6

RTSen

0

Disable auto-rts flow control.

01Enable auto-rts flow control.

7

CTSen

0

Disable auto-cts flow control.

1

Enable auto-cts flow control.

0

3.9 Auto-Flow control
If auto-RTS mode is enabled the UART1‘s receiver FIFO hardware controls the RTS1
output of the UART1. If the auto-cts mode is enabled the UART1‘s U1TSR hardware will
only start transmitting if the CTS1 input signal is asserted.
15.3.9.1

Auto-RTS
The Auto-RTS function is enabled by setting the CTSen bit. Auto-RTS data flow control
originates in the U1RBR module and is linked to the programmed receiver FIFO trigger
level. If auto-rts is enabled, when the receiver FIFO level reaches the programmed trigger
level RTS1 is deasserted (to a high value). The sending UART may send an additional
byte after the trigger level is reached (assuming the sending UART has another byte tosend) because it may not recognize the deassertion of RTS1 until after it has begun
sending the additional byte. RTS1 is automatically reasserted (to a low value) once thereceiver FIFO has reached the previous trigger level. The reassertion of RTS1 signals thesending UART to continue transmitting data.
If Auto-RTS mode is disabled the RTSen bit controls the RTS1 output of the UART1. If
Auto-RTS mode is enabled hardware controls the RTS1 output and the actual value of
RTS1 will be copied in the RTSen bit of the UART1. As long as Auto-RTS is enabled thevalue if the RTSen bit is read-only for software.
Example: Suppose the UART1 operating in type 550 has trigger level in U1FCR set to
0x2 then if Auto-RTS is enabled the UART1 will deassert the RTS1 output as soon as thereceive FIFO contains 8 bytes (Table 15–331 on page 354). The RTS1 output will bereasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes.

~~

UART1 Rx
byte N

stop

start

bits0..7

stop

N

N-1

N-2

start

bits0..7

M

M-1

stop

~
~

start

RTS1 pin

N-1

N-1

N-2

M+2

M+1

~
~

UART1 Rx
FIFO level~~~~

UART1 Rx
FIFO readFig 58. Auto-RTS Functional Timing

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Chapter 15: LPC2300 UART1

15.3.9.2

Auto-CTSThe Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled thetransmitter circuitry in the U1TSR module checks CTS1 input before sending the next databyte. When CTS1 is active (low), the transmitter sends the next byte. To stop thetransmitter from sending the following byte, CTS1 must be released before the middle ofthe last stop bit that is currently being sent. In Auto-CTS mode a change of the CTS1
signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set,
Delta CTS bit in the U1MSR will be set though. Table 15–334 lists the conditions forgenerating a Modem Status interrupt.
Table 334: Modem status interrupt generation
EnableCTSen
Modem(U1MCR[7])StatusInterrupt(U1ER[3])CTSInterrupt
Enable(U1IER[7])Delta CTS Delta DCD or Trailing Edge Modem(U1MSR[0]) RI or
StatusDelta DSR (U1MSR[3] orInterrupt
U1MSR[2] or U1MSR[1])

0

x

x

x

x

No

1

0

x

0

0

No

1

0

x

1

x

Yes

1

0

x

x

1

Yes

1

1

0

x

0

No

1

1

0

x

1

Yes

1

1

1

0

0

No

1

1

1

1

x

Yes

1

1

1

x

1

Yes

~
~

UART1 TX
bits0..7

stop

start

bits0..7

stop

start

bits0..7

stop

~
~

start

~
~

The auto-CTS function reduces interrupts to the host system. When flow control isenabled, a CTS1 state change does not trigger host interrupts because the device
automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any
data present in the transmit FIFO and a receiver overrun error can result. Figure 15–59
illustrates the Auto-CTS functional timing.

~~

CTS1 pin

Fig 59. Auto-CTS Functional Timing

While starting transmission of the initial character the CTS1 signal is asserted.
Transmission will stall as soon as the pending transmission has completed. The UART willcontinue transmitting a 1 bit as long as CTS1 is deasserted (high). As soon as CTS1 getsdeasserted transmission resumes and a start bit is sent followed by the data bits of thenext character.

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Chapter 15: LPC2300 UART1

3.10 UART1 Line Status Register (U1LSR - 0xE001 0014, Read Only)
The U1LSR is a read-only register that provides status information on the UART1 TX andRX blocks.
Table 335: UART1 Line Status Register (U1LSR - address 0xE001 0014, Read Only) bit
description
Bit Symbol0

12Receiver
Data
Ready
(RDR)

Value Description

Reset
Value

U1LSR[0] is set when the U1RBR holds an unread character and 0
is cleared when the UART1 RBR FIFO is empty.
0

U1RBR is empty.

1

U1RBR contains valid data.

OverrunError(OE)

The overrun error condition is set as soon as it occurs. An U1LSR 0
read clears U1LSR[1]. U1LSR[1] is set when UART1 RSR has a
new character assembled and the UART1 RBR FIFO is full. In
this case, the UART1 RBR FIFO will not be overwritten and thecharacter in the UART1 RSR will be lost.
0Overrun error status is inactive.

1

Overrun error status is active.
When the parity bit of a received character is in the wrong state, a 0
parity error occurs. An U1LSR read clears U1LSR[2]. Time ofparity error detection is dependent on U1FCR[0].

ParityError(PE)

Note: A parity error is associated with the character at the top of
the UART1 RBR FIFO.

3

0

Parity error status is inactive.

1

Parity error status is active.

Framing
Error(FE)

When the stop bit of a received character is a logic 0, a framing
0
error occurs. An U1LSR read clears U1LSR[3]. The time of theframing error detection is dependent on U1FCR0. Upon detectionof a framing error, the RX will attempt to resynchronize to the data
and assume that the bad stop bit is actually an early start bit.
However, it cannot be assumed that the next received byte will becorrect even if there is no Framing Error.
Note: A framing error is associated with the character at the topof the UART1 RBR FIFO.

4

0

Framing error status is inactive.

1

Framing error status is active.
0
When RXD1 is held in the spacing state (all 0’s) for one fullcharacter transmission (start, data, parity, stop), a break interrupt
occurs. Once the break condition has been detected, the receivergoes idle until RXD1 goes to marking state (all 1’s). An U1LSR
read clears this status bit. The time of break detection isdependent on U1FCR[0].

BreakInterrupt(BI)

Note: The break interrupt is associated with the character at the
top of the UART1 RBR FIFO.
0

Break interrupt status is inactive.

1

Break interrupt status is active.

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Chapter 15: LPC2300 UART1

Table 335: UART1 Line Status Register (U1LSR - address 0xE001 0014, Read Only) bit
description
Bit Symbol
5

6

7

Value Description

Transmitter Holding
Register
Empty(THRE)

Reset
Value

THRE is set immediately upon detection of an empty UART1
THR and is cleared on a U1THR write.

Transmitter Empty(TEMT)

0

U1THR contains valid data.

1

U1THR is empty.

1

TEMT is set when both U1THR and U1TSR are empty; TEMT is 1
cleared when either the U1TSR or the U1THR contain valid data.
0

U1THR and/or the U1TSR contains valid data.

1

U1THR and the U1TSR are empty.

Error in RX
FIFO(RXFE)U1LSR[7] is set when a character with a RX error such as framing 0
error, parity error or break interrupt, is loaded into the U1RBR.
This bit is cleared when the U1LSR register is read and there areno subsequent errors in the UART1 FIFO.
0

U1RBR contains no UART1 RX errors or U1FCR[0]=0.

1

UART1 RBR contains at least one UART1 RX error.

3.11 UART1 Modem Status Register (U1MSR - 0xE001 0018)
The U1MSR is a read-only register that provides status information on the modem input
signals. U1MSR[3:0] is cleared on U1MSR read. Note that modem signals have no direct
affect on UART1 operation, they facilitate software implementation of modem signal
operations.
Table 336: UART1 Modem Status Register (U1MSR - address 0xE001 0018) bit description
Bit Symbol Value Description

Reset
Value

0

0

1

2

3

4

Delta
CTS

Delta
DSR

Set upon state change of input CTS. Cleared on an U1MSR read.
0

No change detected on modem input, CTS.

1State change detected on modem input, CTS.
Set upon state change of input DSR. Cleared on an U1MSR read.

0

No change detected on modem input, DSR.

1

State change detected on modem input, DSR.

Trailing
Edge RI

Delta
DCD

CTS

Set upon low to high transition of input RI. Cleared on an U1MSR
read.
0

No change detected on modem input, RI.

1

Low-to-high transition detected on RI.
Set upon state change of input DCD. Cleared on an U1MSR read.

0

No change detected on modem input, DCD.

1

State change detected on modem input, DCD.
Clear To Send State. Complement of input signal CTS. This bit isconnected to U1MCR[1] in modem loopback mode.

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0

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Chapter 15: LPC2300 UART1

Table 336: UART1 Modem Status Register (U1MSR - address 0xE001 0018) bit description
Bit Symbol Value Description

Reset
Value

5

DSR

Data Set Ready State. Complement of input signal DSR. This bit isconnected to U1MCR[0] in modem loopback mode.

0

6

RI

Ring Indicator State. Complement of input RI. This bit is connected
to U1MCR[2] in modem loopback mode.

0

7

DCD

Data Carrier Detect State. Complement of input DCD. This bit isconnected to U1MCR[3] in modem loopback mode.

0

3.12 UART1 Scratch Pad Register (U1SCR - 0xE001 001C)
The U1SCR has no effect on the UART1 operation. This register can be written and/or
read at user’s discretion. There is no provision in the interrupt interface that would indicate
to the host that a read or write of the U1SCR has occurred.
Table 337: UART1 Scratch Pad Register (U1SCR - address 0xE001 0014) bit description
Bit Symbol Description

Reset Value

7:0 Pad0x00

A readable, writable byte.

3.13 UART1 Auto-baud Control Register (U1ACR - 0xE001 0020)
The UART1 Auto-baud Control Register (U1ACR) controls the process of measuring theincoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
Table 338: Auto-baud Control Register (U1ACR - address 0xE001 0020) bit description
Bit

Symbol

0

Start

1

2

Value Description

Auto-baud stop (auto-baud is not running).

1

Auto-baud start (auto-baud is running).Auto-baud run
bit. This bit is automatically cleared after auto-baudcompletion.
Auto-baud mode select bit.

0Mode 0.

1Mode 1.

AutoRestart 0-

8

ABEOIntClr

0

No restart0

1

Restart in case of time-out (counter restarts at next
UART1 Rx falling edge)

0

NA

Reserved, user software should not write ones to0reserved bits. The value read from a reserved bit is notdefined.
End of auto-baud interrupt clear bit (write only
accessible).

00

Writing a 0 has no impact.

1

Writing a 1 will clear the corresponding interrupt in the
U1IIR.

UM10211_1

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0

0

Mode

7:3

Reset value

This bit is automatically cleared after auto-baudcompletion.

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Chapter 15: LPC2300 UART1

Table 338: Auto-baud Control Register (U1ACR - address 0xE001 0020) bit description
Bit

Symbol9

ABTOIntClr

31:10 -

Value Description

Reset value

Auto-baud time-out interrupt clear bit (write only
accessible).

00

Writing a 0 has no impact.

1

Writing a 1 will clear the corresponding interrupt in the
U1IIR.

NA

Reserved, user software should not write ones to0reserved bits. The value read from a reserved bit is notdefined.

3.14 Auto-baud
The UART1 auto-baud function can be used to measure the incoming baud-rate based onthe ”AT" protocol (Hayes command). If enabled the auto-baud feature will measure the bittime of the receive data stream and set the divisor latch registers U1DLM and U1DLL
accordingly.
Auto-baud is started by setting the U1ACR Start bit. Auto-baud can be stopped by clearing
the U1ACR Start bit. The Start bit will clear once auto-baud has finished and reading the
bit will return the status of auto-baud (pending/finished).
Two auto-baud measuring modes are available which can be selected by the U1ACR
Mode bit. In mode 0 the baud-rate is measured on two subsequent falling edges of theUART1 Rx pin (the falling edge of the start bit and the falling edge of the least significantbit). In mode 1 the baud-rate is measured between the falling edge and the subsequentrising edge of the UART1 Rx pin (the length of the start bit).
The U1ACR AutoRestart bit can be used to automatically restart baud-rate measurement
if a time-out occurs (the rate measurement counter overflows). If this bit is set the ratemeasurement will restart at the next falling edge of the UART1 Rx pin.
The auto-baud function can generate two interrupts.

• The U1IIR ABTOInt interrupt will get set if the interrupt is enabled (U1IER ABToIntEn
is set and the auto-baud rate measurement counter overflows).

• The U1IIR ABEOInt interrupt will get set if the interrupt is enabled (U1IER ABEOIntEn
is set and the auto-baud has completed successfully).
The auto-baud interrupts have to be cleared by setting the corresponding U1ACRABTOIntClr and ABEOIntEn bits.
Typically the fractional baud-rate generator is disabled (DIVADDVAL = 0) during
auto-baud. However, if the fractional baud-rate generator is enabled (DIVADDVAL > 0), it
is going to impact the measuring of UART1 Rx pin baud-rate, but the value of the U1FDR
register is not going to be modified after rate measurement. Also, when auto-baud is used,
any write to U1DLM and U1DLL registers should be done before U1ACR register write.
The minimum and the maximum baudrates supported by UART1 are function of pclk,
number of data bits, stop bits and parity bits.
(12)

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Chapter 15: LPC2300 UART1

2 × P CLK
16 × 2 15

PCLK
16 × ( 2 + databits + paritybits + stopbits )ratemin = ------------------------- ≤ UART 1 baudrate ≤ ------------------------------------------------------------------------------------------------------------ = ratemax

3.15 Auto-baud modes
When the software is expecting an ”AT" command, it configures the UART1 with the
expected character format and sets the U1ACR Start bit. The initial values in the divisor
latches U1DLM and U1DLM don‘t care. Because of the ”A" or ”a" ASCII coding(”A" = 0x41, ”a" = 0x61), the UART1 Rx pin sensed start bit and the LSB of the expectedcharacter are delimited by two falling edges. When the U1ACR Start bit is set, theauto-baud protocol will execute the following phases:
1. On U1ACR Start bit setting, the baud-rate measurement counter is reset and theUART1 U1RSR is reset. The U1RSR baud rate is switch to the highest rate.
2. A falling edge on UART1 Rx pin triggers the beginning of the start bit. The ratemeasuring counter will start counting pclk cycles optionally pre-scaled by thefractional baud-rate generator.
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input withthe frequency of the (fractional baud-rate pre-scaled) UART1 input clock,guaranteeing the start bit is stored in the U1RSR.
4. During the receipt of the start bit (and the character LSB for mode = 0) the rate
counter will continue incrementing with the pre-scaled UART1 input clock (pclk).
5. If Mode = 0 then the rate counter will stop on next falling edge of the UART1 Rx pin. If
Mode = 1 then the rate counter will stop on the next rising edge of the UART1 Rx pin.
6. The rate counter is loaded into U1DLM/U1DLL and the baud-rate will be switched tonormal operation. After setting the U1DLM/U1DLL the end of auto-baud interrupt
U1IIR ABEOInt will be set, if enabled. The U1RSR will now continue receiving theremaining bits of the ”A/a" character.

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Chapter 15: LPC2300 UART1'A' (0x41) or 'a' (0x61)
start

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

parity stop

UARTn RXstart bit

LSB of 'A' or 'a'

U0ACR start
rate counter
16xbaud_rate

16 cycles

16 cyclesa. Mode 0 (start bit and LSB are used for auto-baud)'A' (0x41) or 'a' (0x61)
start

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

parity stop

UARTn RXstart bit

LSB of 'A' or 'a'

U1ACR start
rate counter
16xbaud_rate

16 cyclesb. Mode 1 (only start bit is used for auto-baud)
Fig 60. Auto-baud a) mode 0 and b) mode 1 waveform

3.16 UART1 Fractional Divider Register (U1FDR - 0xE001 0028)
The UART1 Fractional Divider Register (U1FDR) controls the clock pre-scaler for thebaud rate generation and can be read and written at user’s discretion.

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Chapter 15: LPC2300 UART1

Table 339: UART1 Fractional Divider Register (U1FDR - address 0xE001 C028) bit description
Bit

Function

Value Description

Reset
value

3:0

DIVADDVAL

0

Baud-rate generation pre-scaler divisor value. If this field
is 0, fractional baud-rate generator will not impact the
UART1 baudrate.

0

7:4

MULVAL

1

Baud-rate pre-scaler multiplier value. This field must be
1
greater or equal 1 for UART1 to operate properly,
regardless of whether the fractional baud-rate generator isused or not.

31:8

-

NA

Reserved, user software should not write ones to reserved 0
bits. The value read from a reserved bit is not defined.

This register controls the clock pre-scaler for the baud rate generation.
UART1 baud-rate can be calculated as:
(13)

PCLK
UART1 baudrate = ------------------------------------------------------------------------------------DIVADDVAL⎛
16 × U1DL × 1 + -----------------------------------⎞⎝MULVAL ⎠Where PCLK is the peripheral clock, U1DL is value determined by the U1DLM and U1DLL
registers, and DIVADDVAL and MULVAL are UART1 fractional baud-rate generator
specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 0 < MULVAL ≤ 15
2. 0 ≤ DIVADDVAL ≤ 15
If the U1FDR register value does not comply to these two requests then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled
and the clock will not be divided.
Remark: if DIVADDVAL>0, UnDL must be UnDL ≥ 0x0002, or the UART will not operate
at the desired baud-rate!
The value of the U1FDR should not be modified while transmitting/receiving data or data
may be lost or corrupted.
Usage Note: For practical purposes, the UART0 baudrate formula can be written in a waythat identifies the part of a UART baudrate generated without the fractional baud-rate
generator, and the correction factor that this module adds:
(14)
PCLK
MULVALUART1 baudrate = ---------------------------- × -----------------------------------------------------------------------16 × U1DL ( MULVAL + DIVADDVAL )UM10211_1

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Chapter 15: LPC2300 UART1

Based on this representation, fractional baud-rate generator contribution can also be
described as a prescaling with a factor of MULVAL/(MULVAL+DIVADDVAL).

3.17 UART1 Baudrate Calculation
Example 1: Using UART1baudrate formula from above, it can be determined that systemwith PCLK = 20 MHz, UnDL = 130 (U1DLM = 0x00 and U1DLL = 0x82), DIVADDVAL = 0
and MULVAL = 1 will enable UART1 with UART1baudrate = 9615 bauds.
Example 2: Using UART1baudrate formula from above, it can be determined that systemwith PCLK = 20 MHz, U1DL = 93 (U1DLM = 0x00 and U1DLL = 0x5D), DIVADDVAL = 2
and MULVAL = 5 will enable UART1 with UART1baudrate = 9600 bauds.
Table 340: Baud-rates available when using 20 MHz peripheral clock (PCLK = 20 MHz)
Desired
MULVAL = 0 DIVADDVAL = 0
baud-rate U1DLM:U1DLL% error[3]hex[2] dec[1]Optimal MULVAL & DIVADDVALU1DLM:U1DLL
dec[1]% error[3]

MULDIV
MULDIV + DIVADDVAL

50

61A8

25000

0.000025000

1/(1+0)0.0000

75

411B

16667

0.002012500

3/(3+1)0.0000

110

2C64

11364

0.00326250

11/(11+9)0.0000

134.5

244E

9294

0.00343983

3/(3+4)0.0001

150

208D

8333

0.00406250

3/(3+1)0.0000

300

1047

4167

0.00803125

3/(3+1)0.0000

600

0823

2083

0.01601250

3/(3+2)0.0000

1200

0412

1042

0.0320625

3/(3+2)0.0000

1800

02B6

694

0.0640625

9/(9+1)0.0000

2000

0271

625

0.0000625

1/(1+0)0.0000

2400

0209

521

0.0320250

12/(12+13)

0.0000

3600

015B

347

0.0640248

5/(5+2)0.0064

4800

0104

260

0.1600125

12/(12+13)

0.0000

7200

00AE

174

0.2240124

5/(5+2)0.0064

9600

0082

130

0.160093

5/(5+2)0.0064

19200

0041

65

0.160031

10/(10+11)

0.0064

38400

0021

33

1.376012

7/(7+12)0.0594

56000

0021

22

1.440013

7/(7+5)0.0160

57600

0016

22

1.376019

7/(7+1)0.0594112000000B

111.44006

7/(7+6)0.1600115200000B

111.37604

7/(7+12)0.05942240000006

67.52003

7/(7+6)0.16004480000003

37.52002

5/(5+2)0.3520[1]

Values in the row represent decimal equivalent of a 16 bit long content (DLM:DLL).

[2]

Values in the row represent hex equivalent of a 16 bit long content (DLM:DLL).

[3]

Refers to the percent error between desired and actual baud-rate.

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Chapter 15: LPC2300 UART1

3.18 UART1 Transmit Enable Register (U1TER - 0xE001 0030)
In addition to being equipped with full hardware flow control (auto-cts and auto-rts
mechanisms described above), U1TER enables implementation of software flow control,
too. When TxEn=1, UART1 transmitter will keep sending data as long as they areavailable. As soon as TxEn becomes 0, UART1 transmission will stop.
Although Table 15–341 describes how to use TxEn bit in order to achieve hardware flow
control, it is strongly suggested to let UART1 hardware implemented auto flow control
features take care of this, and limit the scope of TxEn to software flow control.
LPC2300’s U1TER enables implementation of software and hardware flow control. When
TXEn=1, UART1 transmitter will keep sending data as long as they are available. As soon
as TXEn becomes 0, UART1 transmission will stop.
Table 15–341 describes how to use TXEn bit in order to achieve software flow control.
Table 341: UART1 Transmit Enable Register (U1TER - address 0xE001 0030) bit description
Bit

SymbolDescription

Reset Value

6:0-

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

7

TXEN

When this bit is 1, as it is after a Reset, data written to the THR 1
is output on the TXD pin as soon as any preceding data has
been sent. If this bit cleared to 0 while a character is being sent,
the transmission of that character is completed, but no further
characters are sent until this bit is set again. In other words, a 0
in this bit blocks the transfer of characters from the THR or TX
FIFO into the transmit shift register. Software can clear this bit
when it detects that the a hardware-handshaking TX-permit
signal (CTS) has gone false, or with software handshaking,when it receives an XOFF character (DC3). Software can set
this bit again when it detects that the TX-permit signal has gonetrue, or when it receives an XON (DC1) character.

4. Architecture
The architecture of the UART1 is shown below in the block diagram.
The APB interface provides a communications link between the CPU or host and theUART1.
The UART1 receiver block, U1RX, monitors the serial input line, RXD1, for valid input.
The UART1 RX Shift Register (U1RSR) accepts valid characters via RXD1. After a validcharacter is assembled in the U1RSR, it is passed to the UART1 RX Buffer Register FIFO
to await access by the CPU or host via the generic host interface.
The UART1 transmitter block, U1TX, accepts data written by the CPU or host and buffers
the data in the UART1 TX Holding Register FIFO (U1THR). The UART1 TX Shift Register(U1TSR) reads the data stored in the U1THR and assembles the data to transmit via theserial output pin, TXD1.

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Chapter 15: LPC2300 UART1The UART1 Baud Rate Generator block, U1BRG, generates the timing enables used by
the UART1 TX block. The U1BRG clock input source is the APB clock (PCLK). The main
clock is divided down per the divisor specified in the U1DLL and U1DLM registers. This
divided down clock is a 16x oversample clock, NBAUDOUT.
The modem interface contains registers U1MCR and U1MSR. This interface is
responsible for handshaking between a modem peripheral and the UART1.
The interrupt interface contains registers U1IER and U1IIR. The interrupt interface
receives several one clock wide enables from the U1TX and U1RX blocks.
Status information from the U1TX and U1RX is stored in the U1LSR. Control information
for the U1TX and U1RX is stored in the U1LCR.

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Chapter 15: LPC2300 UART1

MODEM

U1TX

U1THR

CTS
DSR

NTXRDY
U1TSR

TXD1

U1MSR

RI

U1BRG

DCD
DTR
RTS

U1DLL

NBAUDOUT

U1DLM

RCLK

U1MCR

U1RX

NRXRDYINTERRUPTU1RBR
U1INTR

U1RSR

RXD1

U1IER

U1IIR

U1FCR

U1LSR
U1SCR
U1LCR

PA[2:0]PSEL
PSTB
PWRITE
PD[7:0]APBINTERFACE

DDIS

AR
MR
PCLK

Fig 61. LPC2300 UART1 block diagram

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Chapter 16: SPI interface SPI0
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User manual

1. Features• Compliant with Serial Peripheral Interface (SPI) specification.
• Synchronous, Serial, Full Duplex Communication.
• SPI master or slave.
• Maximum data bit rate of one eighth of the input clock rate.
• 8 to 16 bits per transfer

2. SPI overview
SPI is a full duplex serial interfaces. It can handle multiple masters and slaves being
connected to a given bus. Only a single master and a single slave can communicate on
the interface during a given data transfer. During a data transfer the master always sends
8 to 16 bits of data to the slave, and the slave always sends a byte of data to the master.

3. SPI data transfers
Figure 16–62 is a timing diagram that illustrates the four different data transfer formats
that are available with the SPI. This timing diagram illustrates a single 8 bit data transfer.
The first thing you should notice in this timing diagram is that it is divided into threehorizontal parts. The first part describes the SCK and SSEL signals. The second partdescribes the MOSI and MISO signals when the CPHA variable is 0. The third partdescribes the MOSI and MISO signals when the CPHA variable is 1.
In the first part of the timing diagram, note two points. First, the SPI is illustrated with
CPOL set to both 0 and 1. The second point to note is the activation and de-activation of
the SSEL signal. When CPHA = 0, the SSEL signal will always go inactive between datatransfers. This is not guaranteed when CPHA = 1 (the signal can remain active).

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Chapter 16: LPC2300 SPI0SCK (CPOL = 0)

SCK (CPOL = 1)

SSEL

CPHA = 0

Cycle # CPHA = 0

1

2

3

4

5

6

7

8

MOSI (CPHA = 0)

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

MISO (CPHA = 0)

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

CPHA = 1

Cycle # CPHA = 1

1

2

3

4

5

6

7

8

MOSI (CPHA = 1)

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

MISO (CPHA = 1)

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

Fig 62. SPI data transfer format (CPHA = 0 and CPHA = 1)

The data and clock phase relationships are summarized in Table 16–342. This tablesummarizes the following for each setting of CPOL and CPHA.

• When the first data bit is driven.
• When all other data bits are driven.
• When data is sampled.
Table 342. SPI Data To Clock Phase Relationship
CPOL and CPHA settings First data driven

Other data driven

Data sampled

CPOL = 0, CPHA = 0

Prior to first SCK rising edge SCK falling edge

SCK rising edge

CPOL = 0, CPHA = 1

First SCK rising edge

SCK rising edge

SCK falling edge

CPOL = 1, CPHA = 0

Prior to first SCK falling edge SCK rising edge

SCK falling edge

CPOL = 1, CPHA = 1

First SCK falling edge

SCK rising edge

SCK falling edge

The definition of when an 8 bit transfer starts and stops is dependent on whether a device
is a master or a slave, and the setting of the CPHA variable.
When a device is a master, the start of a transfer is indicated by the master having a byteof data that is ready to be transmitted. At this point, the master can activate the clock, andbegin the transfer. The transfer ends when the last clock cycle of the transfer is complete.

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Chapter 16: LPC2300 SPI0

When a device is a slave and CPHA is set to 0, the transfer starts when the SSEL signal
goes active, and ends when SSEL goes inactive. When a device is a slave, and CPHA is
set to 1, the transfer starts on the first clock edge when the slave is selected, and ends on
the last clock edge where data is sampled.

4. SPI peripheral details
4.1 General information
There are four registers that control the SPI peripheral. They are described in detail in
Section 16–6 “Register description” on page 374.
The SPI control register contains a number of programmable bits used to control thefunction of the SPI block. The settings for this register must be set up prior to a given datatransfer taking place.
The SPI status register contains read only bits that are used to monitor the status of the
SPI interface, including normal functions, and exception conditions. The primary purposeof this register is to detect completion of a data transfer. This is indicated by the SPIF bit.
The remaining bits in the register are exception condition indicators. These exceptions will
be described later in this section.
The SPI data register is used to provide the transmit and receive data bytes. An internal
shift register in the SPI block logic is used for the actual transmission and reception of theserial data. Data is written to the SPI data register for the transmit case. There is no buffer
between the data register and the internal shift register. A write to the data register goes
directly into the internal shift register. Therefore, data should only be written to this registerwhen a transmit is not currently in progress. Read data is buffered. When a transfer iscomplete, the receive data is transferred to a single byte data buffer, where it is later read.
A read of the SPI data register returns the value of the read data buffer.
The SPI clock counter register controls the clock rate when the SPI block is in mastermode. This needs to be set prior to a transfer taking place, when the SPI block is amaster. This register has no function when the SPI block is a slave.
The SPI controller has an enable bit (SPEN), which controls the following functions:• Activation of SPI I/Os.
• Enables the SPI internal state machine. If a transfer is in progress, and the enable
signal is deactivated, the transfer will complete first, then the SPI controller will bedisabled.

• Disables any other logic that can be disabled, to conserve power.
• The enable does not disable register accesses to the SPI controller.
The I/Os for this implementation of SPI are standard CMOS I/Os. The open drain SPI
option is not implemented in this design. When a device is set up to be a slave, its I/Os are
only active when it is selected by the SSEL signal being active.

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Chapter 16: LPC2300 SPI0

4.2 Master operation
The following sequence describes how one should process a data transfer with the SPI
block when it is set up to be the master. This process assumes that any prior data transfer
has already completed.
1. Set the SPI clock counter register to the desired clock rate.
2. Set the SPI control register to the desired settings.
3. Write the data to transmitted to the SPI data register. This write starts the SPI datatransfer.
4. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set
after the last cycle of the SPI data transfer.
5. Read the SPI status register.
6. Read the received data from the SPI data register (optional).
7. Go to step 3 if more data is required to transmit.
Note: A read or write of the SPI data register is required in order to clear the SPIF status
bit. Therefore, if the optional read of the SPI data register does not take place, a write tothis register is required in order to clear the SPIF status bit.

4.3 Slave operation
The following sequence describes how one should process a data transfer with the SPI
block when it is set up to be a slave. This process assumes that any prior data transfer
has already completed. It is required that the system clock driving the SPI logic be at least
8X faster than the SPI.
1. Set the SPI control register to the desired settings.
2. Write the data to transmitted to the SPI data register (optional). Note that this can only
be done when a slave SPI transfer is not in progress.
3. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set
after the last sampling clock edge of the SPI data transfer.
4. Read the SPI status register.
5. Read the received data from the SPI data register (optional).
6. Go to step 2 if more data is required to transmit.
Note: A read or write of the SPI data register is required in order to clear the SPIF status
bit. Therefore, at least one of the optional reads or writes of the SPI data register musttake place, in order to clear the SPIF status bit.

4.4 Exception conditions
Read Overrun
A read overrun occurs when the SPI block internal read buffer contains data that has notbeen read by the processor, and a new transfer has completed. The read buffer
containing valid data is indicated by the SPIF bit in the status register being active. Whena transfer completes, the SPI block needs to move the received data to the read buffer. If
the SPIF bit is active (the read buffer is full), the new receive data will be lost, and the read
overrun (ROVR) bit in the status register will be activated.
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Chapter 16: LPC2300 SPI0

Write Collision
As stated previously, there is no write buffer between the SPI block bus interface, and theinternal shift register. As a result, data must not be written to the SPI data register when a
SPI data transfer is currently in progress. The time frame where data cannot be written to
the SPI data register is from when the transfer starts, until after the status register has
been read when the SPIF status is active. If the SPI data register is written in this timeframe, the write data will be lost, and the write collision (WCOL) bit in the status register
will be activated.
Mode Fault
If the SSEL signal goes active, when the SPI block is a master, this indicates anothermaster has selected the device to be a slave. This condition is known as a mode fault.
When a mode fault is detected, the mode fault (MODF) bit in the status register will be
activated, the SPI signal drivers will be de-activated, and the SPI mode will be changed to
be a slave.
If the Px.y/SSEL/... pin is assigned the SSEL function in Pin Function Select Register 0,
the SSEL signal must always be inactive when the SPI controller is a master.
Slave Abort
A slave transfer is considered to be aborted, if the SSEL signal goes inactive before thetransfer is complete. In the event of a slave abort, the transmit and receive data for thetransfer that was in progress are lost, and the slave abort (ABRT) bit in the status register
will be activated.

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Chapter 16: LPC2300 SPI0

5. Pin description
Table 343. SPI Pin Description
Pin
Name

Type

Pin Description

SCK0

Input/
OutputSerial Clock. The SPI is a clock signal used to synchronize the transfer of data
across the SPI interface. The SPI is always driven by the master and received
by the slave. The clock is programmable to be active high or active low. The SPI
is only active during a data transfer. Any other time, it is either in its inactive
state, or tri-stated.

SSEL0 Input

Slave Select. The SPI slave select signal is an active low signal that indicates
which slave is currently selected to participate in a data transfer. Each slave has
its own unique slave select signal input. The SSEL must be low before datatransactions begin and normally stays low for the duration of the transaction. If
the SSEL signal goes high any time during a data transfer, the transfer isconsidered to be aborted. In this event, the slave returns to idle, and any datathat was received is thrown away. There are no other indications of thisexception. This signal is not directly driven by the master. It could be driven by asimple general purpose I/O under software control.
On the LPC2300 (unlike earlier NXP ARM devices) the SSEL0 pin can be used
for a different function when the SPI0 interface is only used in Master mode. For
example, pin hosting the SSEL0 function can be configured as an output digital
GPIO pin and used to select one of the SPI0 slaves.

MISO0 Input/
OutputMaster In Slave Out. The MISO signal is a unidirectional signal used to transfer
serial data from the slave to the master. When a device is a slave, serial data is
output on this signal. When a device is a master, serial data is input on thissignal. When a slave device is not selected, the slave drives the signal highimpedance.

MOSI0 Input/
OutputMaster Out Slave In. The MOSI signal is a unidirectional signal used to transfer
serial data from the master to the slave. When a device is a master, serial data
is output on this signal. When a device is a slave, serial data is input on thissignal.

6. Register description
The SPI contains 5 registers as shown in Table 16–344. All registers are byte, half word
and word accessible.
Table 344. SPI Register Map
Name

Description

AccessReset
Value[1]Address

S0SPCRSPI Control Register. This register controls theoperation of the SPI.

R/W

0x00

0xE002 0000

S0SPSRSPI Status Register. This register shows thestatus of the SPI.

RO

0x00

0xE002 0004

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Chapter 16: LPC2300 SPI0

Table 344. SPI Register Map
Name

Description

AccessS0SPDRSPI Data Register. This bi-directional register
R/W
provides the transmit and receive data for the
SPI. Transmit data is provided to the SPI0 by
writing to this register. Data received by the SPI0
can be read from this register.

Reset
Value[1]Address

0x00

0xE002 0008

S0SPCCR SPI Clock Counter Register. This register
controls the frequency of a master’s SCK0.

R/W

0x00

0xE002 000CS0SPINT

R/W

0x00

0xE002 001C

[1]

SPI Interrupt Flag. This register contains theinterrupt flag for the SPI interface.

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

6.1 SPI Control Register (S0SPCR - 0xE002 0000)
The S0SPCR register controls the operation of the SPI0 as per the configuration bits
setting.
Table 345: SPI Control Register (S0SPCR - address 0xE002 0000) bit description
Bit

Symbol

1:0-

2

BitEnable

3

Value Description
Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

0

The SPI controller sends and receives 8 bits of data pertransfer.

0

1

The SPI controller sends and receives the number of bits
selected by bits 11:8.

CPHA

Clock phase control determines the relationship between 0
the data and the clock on SPI transfers, and controls
when a slave transfer is defined as starting and ending.
0
1

4

5

6

CPOL

Data is sampled on the first clock edge of SCK. A transfer
starts and ends with activation and deactivation of the
SSEL signal.
Data is sampled on the second clock edge of the SCK. A
transfer starts with the first clock edge, and ends with thelast sampling edge when the SSEL signal is active.
Clock polarity control.

0

SCK is active high.

1

SCK is active low.

MSTR

0

Master mode select.
0

The SPI operates in Slave mode.

1

The SPI operates in Master mode.

LSBF

0

LSB First controls which direction each byte is shifted
when transferred.
0

SPI data is transferred MSB (bit 7) first.

1

SPI data is transferred LSB (bit 0) first.

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Chapter 16: LPC2300 SPI0

Table 345: SPI Control Register (S0SPCR - address 0xE002 0000) bit description
Bit

Symbol

7

SPIE

11:8

Value Description
Serial peripheral interrupt enable.

-

0

0

SPI interrupts are inhibited.

1

A hardware interrupt is generated each time the SPIF or
MODF bits are activated.

BITS

15:12

Reset
Value

When bit 2 of this register is 1, this field controls thenumber of bits per transfer:
1000

8 bits per transfer

1001

9 bits per transfer

1010

10 bits per transfer

1011

11 bits per transfer

1100

12 bits per transfer

1101

13 bits per transfer

1110

14 bits per transfer

1111

15 bits per transfer

0000

16 bits per transfer

0000

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

6.2 SPI Status Register (S0SPSR - 0xE002 0004)
The S0SPSR register controls the operation of the SPI0 as per the configuration bits
setting.
Table 346: SPI Status Register (S0SPSR - address 0xE002 0004) bit description
Bit

SymbolDescription

Reset Value

2:0-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

3

ABRT

Slave abort. When 1, this bit indicates that a slave abort has
occurred. This bit is cleared by reading this register.

0

4

MODF

Mode fault. when 1, this bit indicates that a Mode fault error has 0
occurred. This bit is cleared by reading this register, then writing
the SPI0 control register.

5

ROVR

Read overrun. When 1, this bit indicates that a read overrun has 0
occurred. This bit is cleared by reading this register.

6

WCOL

Write collision. When 1, this bit indicates that a write collision has 0
occurred. This bit is cleared by reading this register, thenaccessing the SPI data register.

7

SPIF

SPI transfer complete flag. When 1, this bit indicates when a SPI 0
data transfer is complete. When a master, this bit is set at theend of the last cycle of the transfer. When a slave, this bit is set
on the last data sampling edge of the SCK. This bit is cleared byfirst reading this register, then accessing the SPI data register.
Note: this is not the SPI interrupt flag. This flag is found in the
SPINT register.

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6.3 SPI Data Register (S0SPDR - 0xE002 0008)
This bi-directional data register provides the transmit and receive data for the SPI.
Transmit data is provided to the SPI by writing to this register. Data received by the SPI
can be read from this register. When a master, a write to this register will start a SPI datatransfer. Writes to this register will be blocked from when a data transfer starts to when the
SPIF status bit is set, and the status register has not been read.
Table 347: SPI Data Register (S0SPDR - address 0xE002 0008) bit description
Bit

SymbolDescription

Reset Value

7:0

DataLow

SPI Bi-directional data port.

0x00

15:8 DataHigh

If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some 0x00
or all of these bits contain the additional transmit and receive
bits. When less than 16 bits are selected, the more significant
among these bits read as zeroes.

6.4 SPI Clock Counter Register (S0SPCCR - 0xE002 000C)
This register controls the frequency of a master’s SCK. The register indicates the numberof PCLK cycles that make up an SPI clock. The value of this register must always be aneven number. As a result, bit 0 must always be 0. The value of the register must also
always be greater than or equal to 8. Violations of this can result in unpredictablebehavior.
Table 348: SPI Clock Counter Register (S0SPCCR - address 0xE002 000C) bit description
Bit

SymbolDescription

Reset Value

7:0

Counter

SPI0 Clock counter setting.

0x00

The SPI0 rate may be calculated as: PCLK / SPCCR0 value. The PCLK rate is
CCLK /APB divider rate as determined by the PCLKSEL0 register contents for
PCLK_SPI.

6.5 SPI Test Control Register (SPTCR - 0xE002 0010)
Note that the bits in this register are intended for functional verification only. This registershould not be used for normal operation.
Table 349: SPI Test Control Register (SPTCR - address 0xE002 0010) bit description
Bit

SymbolDescription

Reset Value0-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

7:1

Test

SPI test mode. When 0, the SPI operates normally. When 1,
0
SCK will always be on, independent of master mode select, anddata availability setting.

6.6 SPI Test Status Register (SPTSR - 0xE002 0014)
Note: The bits in this register are intended for functional verification only. This registershould not be used for normal operation.

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This register is a replication of the SPI status register. The difference between theregisters is that a read of this register will not start the sequence of events required toclear these status bits. A write to this register will set an interrupt if the write data for therespective bit is a 1.
Table 350: SPI Test Status Register (SPTSR - address 0xE002 0014) bit description
Bit

SymbolDescription

Reset Value

2:0-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

3

ABRT

Slave abort.

0

4

MODF

Mode fault.

0

5

ROVR

Read overrun.

0

6

WCOL

Write collision.

0

7

SPIF

SPI transfer complete flag.

0

6.7 SPI Interrupt Register (S0SPINT - 0xE002 001C)
This register contains the interrupt flag for the SPI0 interface.
Table 351: SPI Interrupt Register (S0SPINT - address 0xE002 001C) bit description
Bit Symbol Description
0

Reset
Value

SPI
SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared 0
Interrupt by writing a 1 to this bit.
Flag
Note: this bit will be set once when SPIE = 1 and at least one of SPIF and
WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0
Interrupt is enabled in the VIC, SPI based interrupt can be processed byinterrupt handling software.

7:1 -Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.

NA

7. Architecture
The block diagram of the SPI solution implemented in SPI0 interface is shown in the
Figure 16–63.

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Chapter 16: LPC2300 SPI0MOSI_INMOSI_OUTMISO_INMISO_OUTSPI SHIFT REGISTERSPI CLOCKSCK_INSCK_OUT
SS_IN

GENERATOR &DETECTORSPI Interrupt

APB Bus

SPI REGISTERINTERFACESPI STATE CONTROLOUTPUT
ENABLELOGIC

SCK_OUT_EN
MOSI_OUT_EN
MISO_OUT_EN

Fig 63. SPI block diagram

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Chapter 17: SSP interface
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User manual

1. Features• Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.

• Synchronous Serial Communication.
• Master or slave operation.
• 8 frame FIFOs for both transmit and receive.
• 4 to 16 bits frame.
• DMA transfers supported by GPDMA.

2. Description
The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given datatransfer. Data transfers are in principle full duplex, with frames of 4 to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
LPC2300 has two Synchronous Serial Port controllers -- SSP0 and SSP1.

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Chapter 17: LPC2300 SSP

3. Pin descriptions
Table 352. SSP pin descriptions
Pin
Name

Interface pin
Type name/function
Pin Description
SPI
SSI
Microwire

SCK

I/O

SCK

CLK

SK

Serial Clock. SCK/CLK/SK is a clock signal used tosynchronize the transfer of data. It is driven by themaster and received by the slave. When SPI
interface is used the clock is programmable to be
active high or active low, otherwise it is always active
high. SCK1 only switches during a data transfer. Anyother time, the SSPn either holds it in its inactive
state, or does not drive it (leaves it in high impedancestate).

SSEL

I/O

SSEL FSCS

Frame Sync/Slave Select. When the SSPn is a bus
master, it drives this signal from shortly before thestart of serial data, to shortly after the end of serial
data, to signify a data transfer as appropriate for theselected bus and mode. When the SSPn is a bus
slave, this signal qualifies the presence of data from
the Master, according to the protocol in use.
When there is just one bus master and one bus
slave, the Frame Sync or Slave Select signal from
the Master can be connected directly to the slave’s
corresponding input. When there is more than one
slave on the bus, further qualification of their Frame
Select/Slave Select inputs will typically be necessary
to prevent more than one slave from responding to atransfer.

MISO

I/O

MISO DR(M) SI(M)
DX(S) SO(S)

Master In Slave Out. The MISO signal transfers
serial data from the slave to the master. When the
SSPn is a slave, serial data is output on this signal.
When the SSPn is a master, it clocks in serial datafrom this signal. When the SSPn is a slave and is notselected by FS/SSEL, it does not drive this signal(leaves it in high impedance state).

MOSI

I/O

MOSI DX(M) SO(M)
DR(S) SI(S)

Master Out Slave In. The MOSI signal transfers
serial data from the master to the slave. When the
SSPn is a master, it outputs serial data on this signal.
When the SSPn is a slave, it clocks in serial datafrom this signal.

4. Bus description
4.1 Texas Instruments Synchronous Serial Frame Format
Figure 17–64 shows the 4-wire Texas Instruments synchronous serial frame format
supported by the SSP module.

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CLK
FS
DX/DR

MSB

LSB
4 to 16 bitsa. Single frame transfer

CLK
FS
DX/DR

MSB

LSB

MSB

4 to 16 bits

LSB
4 to 16 bitsb. Continuous/back-to-back frames transfer
Fig 64. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two
Frames Transfer

For device configured as a master in this mode, CLK and FS are forced LOW, and thetransmit data line DX is tristated whenever the SSP is idle. Once the bottom entry of thetransmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to betransmitted is also transferred from the transmit FIFO to the serial shift register of thetransmit logic. On the next rising edge of CLK, the MSB of the 4 to 16 bit data frame isshifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR
pin by the off-chip serial slave device.
Both the SSP and the off-chip serial slave device then clock each data bit into their serial
shifter on the falling edge of each CLK. The received data is transferred from the serial
shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.

4.2 SPI Frame Format
The SPI interface is a four-wire interface where the SSEL signal behaves as a slave
select. The main feature of the SPI format is that the inactive state and phase of the SCK
signal are programmable through the CPOL and CPHA bits within the SSPCR0 control
register.

4.2.1 Clock Polarity (CPOL) and Phase (CPHA) Control
When the CPOL clock polarity control bit is LOW, it produces a steady state low value on
the SCK pin. If the CPOL clock polarity control bit is HIGH, a steady state high value isplaced on the CLK pin when data is not being transferred.

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The CPHA control bit selects the clock edge that captures data and allows it to change
state. It has the most impact on the first bit transmitted by either allowing or not allowing aclock transition before the first data capture edge. When the CPHA phase control bit is
LOW, data is captured on the first clock edge transition. If the CPHA clock phase control
bit is HIGH, data is captured on the second clock edge transition.

4.2.2 SPI Format with CPOL=0,CPHA=0
Single and continuous transmission signal sequences for SPI format with CPOL = 0,
CPHA = 0 are shown in Figure 17–65.

SCK
SSEL

MOSI
MISO

MSB

LSB

MSB

LSB

Q

4 to 16 bitsa. Single transfer with CPOL=0 and CPHA=0

SCK
SSEL

MOSI
MISO

MSB

LSB

MSB

LSB

MSB
Q

LSB

MSB

4 to 16 bits

LSB

Q

4 to 16 bitsb. Continuous transfer with CPOL=0 and CPHA=0
Fig 65. SPI Frame Format with CPOL=0 and CPHA=0 (a) Single and b) Continuous Transfer)

In this configuration, during idle periods:• The CLK signal is forced LOW.
• SSEL is forced HIGH.
• The transmit MOSI/MISO pad is in high impedance.
If the SSP is enabled and there is valid data within the transmit FIFO, the start oftransmission is signified by the SSEL master signal being driven LOW. This causes slave
data to be enabled onto the MISO input line of the master. Master’s MOSI is enabled.
One half SCK period later, valid master data is transferred to the MOSI pin. Now that boththe master and slave data have been set, the SCK master clock pin goes HIGH after one
further half SCK period.
The data is now captured on the rising and propagated on the falling edges of the SCK
signal.
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In the case of a single word transmission, after all bits of the data word have beentransferred, the SSEL line is returned to its idle HIGH state one SCK period after the last
bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSEL signal must be
pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave
device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK
period after the last bit has been captured.

4.2.3 SPI Format with CPOL=0,CPHA=1
The transfer signal sequence for SPI format with CPOL = 0, CPHA = 1 is shown in
Figure 17–66, which covers both single and continuous transfers.

SCK
SSEL

MOSI
MISO

Q

MSB

LSB

MSB

LSB

Q

4 to 16 bits

Fig 66. SPI Frame Format with CPOL=0 and CPHA=1

In this configuration, during idle periods:• The CLK signal is forced LOW.
• SSEL is forced HIGH.
• The transmit MOSI/MISO pad is in high impedance.
If the SSP is enabled and there is valid data within the transmit FIFO, the start oftransmission is signified by the SSEL master signal being driven LOW. Master’s MOSI pin
is enabled. After a further one half SCK period, both master and slave valid data isenabled onto their respective transmission lines. At the same time, the SCK is enabledwith a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SCK
signal.
In the case of a single word transfer, after all bits have been transferred, the SSEL line isreturned to its idle HIGH state one SCK period after the last bit has been captured.
For continuous back-to-back transfers, the SSEL pin is held LOW between successive
data words and termination is the same as that of the single word transfer.

4.2.4 SPI Format with CPOL = 1,CPHA = 0
Single and continuous transmission signal sequences for SPI format with CPOL=1,
CPHA=0 are shown in Figure 17–67.
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SCK
SSEL

MOSI
MISO

MSB

LSB

MSB

LSB

Q

4 to 16 bitsa. Single transfer with CPOL=1 and CPHA=0
SCK
SSEL

MOSI
MISO

MSB

LSB

MSB

LSB

MSB
Q

LSB

MSB

4 to 16 bits

LSB

Q

4 to 16 bitsb. Continuous transfer with CPOL=1 and CPHA=0
Fig 67. SPI Frame Format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer)

In this configuration, during idle periods:• The CLK signal is forced HIGH.
• SSEL is forced HIGH.
• The transmit MOSI/MISO pad is in high impedance.
If the SSP is enabled and there is valid data within the transmit FIFO, the start oftransmission is signified by the SSEL master signal being driven LOW, which causesslave data to be immediately transferred onto the MISO line of the master. Master’s MOSI
pin is enabled.
One half period later, valid master data is transferred to the MOSI line. Now that both themaster and slave data have been set, the SCK master clock pin becomes LOW after one
further half SCK period. This means that data is captured on the falling edges and be
propagated on the rising edges of the SCK signal.
In the case of a single word transmission, after all bits of the data word are transferred, theSSEL line is returned to its idle HIGH state one SCK period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSEL signal must be
pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave
device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK
period after the last bit has been captured.
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4.2.5 SPI Format with CPOL = 1,CPHA = 1
The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in
Figure 17–68, which covers both single and continuous transfers.

SCK
SSEL

MOSI
MISO

Q

MSB

LSB

MSB

LSB

Q

4 to 16 bits

Fig 68. SPI Frame Format with CPOL = 1 and CPHA = 1

In this configuration, during idle periods:• The CLK signal is forced HIGH.
• SSEL is forced HIGH.
• The transmit MOSI/MISO pad is in high impedance.
If the SSP is enabled and there is valid data within the transmit FIFO, the start oftransmission is signified by the SSEL master signal being driven LOW. Master’s MOSI isenabled. After a further one half SCK period, both master and slave data are enabled onto
their respective transmission lines. At the same time, the SCK is enabled with a fallingedge transition. Data is then captured on the rising edges and propagated on the fallingedges of the SCK signal.
After all bits have been transferred, in the case of a single word transmission, the SSEL
line is returned to its idle HIGH state one SCK period after the last bit has been captured.
For continuous back-to-back transmissions, the SSEL pins remains in its active LOW
state, until the final bit of the last word has been captured, and then returns to its idle state
as described above. In general, for continuous back-to-back transfers the SSEL pin isheld LOW between successive data words and termination is the same as that of thesingle word transfer.

4.3 Semiconductor Microwire Frame Format
Figure 17–69 shows the Microwire frame format for a single frame. Figure 17–70 shows
the same format when back-to-back frames are transmitted.

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SK
CS

SO
SI

MSB

LSB

8 bit control
0 MSB

LSB

4 to 16 bits
output dataFig 69. Microwire Frame Format (Single Transfer)

Microwire format is very similar to SPI format, except that transmission is half-duplex
instead of full-duplex, using a master-slave message passing technique. Each serialtransmission begins with an 8 bit control word that is transmitted from the SSP to theoff-chip slave device. During this transmission, no incoming data is received by the SSP.
After the message has been sent, the off-chip slave decodes it and, after waiting one
serial clock after the last bit of the 8 bit control message has been sent, responds with therequired data. The returned data is 4 to 16 bits in length, making the total frame length
anywhere from 13 to 25 bits.
In this configuration, during idle periods:• The SK signal is forced LOW.
• CS is forced HIGH.
• The transmit data line SO is arbitrarily forced LOW.
A transmission is triggered by writing a control byte to the transmit FIFO.The falling edgeof CS causes the value contained in the bottom entry of the transmit FIFO to betransferred to the serial shift register of the transmit logic, and the MSB of the 8 bit control
frame to be shifted out onto the SO pin. CS remains LOW for the duration of the frametransmission. The SI pin remains tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the risingedge of each SK. After the last bit is latched by the slave device, the control byte is
decoded during a one clock wait-state, and the slave responds by transmitting data backto the SSP. Each bit is driven onto SI line on the falling edge of SK. The SSP in turnlatches each bit on the rising edge of SK. At the end of the frame, for single transfers, theCS signal is pulled HIGH one clock period after the last bit has been latched in the receive
serial shifter, that causes the data to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge ofSK after the LSB has been latched by the receive shiftier, or when the CS pin goes HIGH.
For continuous transfers, data transmission begins and ends in the same manner as asingle transfer. However, the CS line is continuously asserted (held LOW) andtransmission of data occurs back to back. The control byte of the next frame follows
directly after the LSB of the received data from the current frame. Each of the received
values is transferred from the receive shifter on the falling edge SK, after the LSB of theframe has been latched into the SSP.

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SK
CS
SO

LSB

MSB

LSB

8 bit control
SI

0 MSB

LSB

MSB

4 to 16 bits
output data

LSB

4 to 16 bits
output dataFig 70. Microwire Frame Format (Continuos Transfers)

4.3.1 Setup and Hold Time Requirements on CS With Respect to SK in Microwire
Mode
In the Microwire mode, the SSP slave samples the first bit of receive data on the risingedge of SK after CS has gone LOW. Masters that drive a free-running SK must ensurethat the CS signal has sufficient setup and hold margins with respect to the rising edge ofSK.
Figure 17–71 illustrates these setup and hold time requirements. With respect to the SK
rising edge on which the first bit of receive data is to be sampled by the SSP slave, CS
must have a setup of at least two times the period of SK on which the SSP operates. With
respect to the SK rising edge previous to this edge, CS must have a hold of at least one
SK period.

t HOLD= tSKtSETUP=2*tSK

SK
CS

SI

Fig 71. Microwire frame format setup and hold details

5. Register Description
The register offsets from the SSP controller base addresses are shown in the
Table 17–353.

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Table 353. SSP Register Map
Generic Name

Description

CR0

Control Register 0. Selects the serial clock rate, bus R/Wtype, and data size.

0

SSP0CR0 - 0xE006 8000
SSP1CR0 - 0xE003 0000

CR1

Control Register 1. Selects master/slave and othermodes.

R/W

0

SSP0CR1 - 0xE006 8004
SSP1CR1 - 0xE003 0004

DR

Data Register. Writes fill the transmit FIFO, andreads empty the receive FIFO.

R/W

0

SSP0DR - 0xE006 8008
SSP1DR - 0xE003 0008

SR

Status Register

RO

CPSR

Clock Prescale Register

R/W

0

SSP0CPSR - 0xE006 8010
SSP1CPSR - 0xE003 0010

IMSC

Interrupt Mask Set and Clear Register

R/W

0

SSP0IMSC - 0xE006 8014
SSP1IMSC - 0xE003 0014

RIS

Raw Interrupt Status Register

R/W

MIS

Masked Interrupt Status Register

R/W

0

SSP0MIS - 0xE006 801C
SSP1MIS - 0xE003 001CICR

SSPICR Interrupt Clear Register

R/W

NA

SSP0ICR - 0xE006 8020
SSP1ICR - 0xE003 0020DMACR

DMA Control Register

R/W

0

SSP0DMACR - 0xE006 8024
SSP1DMACR - 0xE003 0024

[1]

Access Reset
Value[1]SSPn Register
Name & Address

SSP0SR - 0xE006 800C
SSP1SR - 0xE003 000C

SSP0RIS - 0xE006 8018
SSP1RIS - 0xE003 0018

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

5.1 SSPn Control Register 0 (SSP0CR0 - 0xE006 8000, SSP1CR0 - 0xE003
0000)
This register controls the basic operation of the SSP controller.

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Table 354: SSPn Control Register 0 (SSP0CR0 - address 0xE006 8000, SSP1CR0 0xE003 0000) bit description
Bit

Symbol

3:0

DSS

5:4

6

7

15:8

Value

Reset
Value

Data Size Select. This field controls the number of bits
transferred in each frame. Values 0000-0010 are notsupported and should not be used.

0000

0011

4 bit transfer

0100

5 bit transfer

0101

6 bit transfer

0110

7 bit transfer

0111

8 bit transfer

1000

9 bit transfer

1001

10 bit transfer

1010

11 bit transfer

1011

12 bit transfer

1100

13 bit transfer

1101

14 bit transfer

1110

15 bit transfer

1111

16 bit transfer

FRF

Frame Format.

00

00

SPI

01

TI

10

Microwire

11

This combination is not supported and should not be used.

SPO

Clock Out Polarity. This bit is only used in SPI mode.
0

SSP controller captures serial data on the first clock transitionof the frame, that is, the transition away from the inter-frame
state of the clock line.

1

SSP controller captures serial data on the second clocktransition of the frame, that is, the transition back to theinter-frame state of the clock line.

SPH

SCR

Description

Clock Out Phase. This bit is only used in SPI mode.
0

SSP controller maintains the bus clock low between frames.

1

SSP controller maintains the bus clock high between frames.

00Serial Clock Rate. The number of prescaler-output clocks per 0x00
bit on the bus, minus one. Given that CPSDVR is the prescale
divider, and the APB clock PCLK clocks the prescaler, the bit
frequency is PCLK / (CPSDVSR × [SCR+1]).

5.2 SSPn Control Register 1 (SSP0CR1 - 0xE006 8004, SSP1CR1 0xE003 0004)
This register controls certain aspects of the operation of the SSP controller.

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Table 355: SSPn Control Register 1 (SSP0CR1 - address 0xE006 8004, SSP1CR1 0xE003 0004) bit description
Bit

Symbol

0

LBM

1

2

Value

Description

Reset
Value

Loop Back Mode.

00

During normal operation.

1

Serial input is taken from the serial output (MOSI or MISO)
rather than the serial input pin (MISO or MOSI
respectively).

SSE

SSP Enable.

00

The SSP controller is disabled.

1

The SSP controller will interact with other devices on theserial bus. Software should write the appropriate control
information to the other SSP registers and interrupt
controller registers, before setting this bit.

MS

Master/Slave Mode.This bit can only be written when theSSE bit is 0.
010

The SSP controller acts as a master on the bus, driving the
SCLK, MOSI, and SSEL lines and receiving the MISO line.
The SSP controller acts as a slave on the bus, driving
MISO line and receiving SCLK, MOSI, and SSEL lines.
0

3

SOD

Slave Output Disable. This bit is relevant only in slave
mode (MS = 1). If it is 1, this blocks this SSP controller
from driving the transmit data line (MISO).

7:4-

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

5.3 SSPn Data Register (SSP0DR - 0xE006 8008, SSP1DR - 0xE003 0008)
Software can write data to be transmitted to this register, and read data that has been
received.
Table 356: SSPn Data Register (SSP0DR - address 0xE006 8008, SSP1DR - 0xE003 0008) bit
description
Bit

SymbolDescription

Reset Value

15:0

DATA

Write: software can write data to be sent in a future frame to this 0x0000
register whenever the TNF bit in the Status register is 1,
indicating that the Tx FIFO is not full. If the Tx FIFO waspreviously empty and the SSP controller is not busy on the bus,transmission of the data will begin immediately. Otherwise thedata written to this register will be sent as soon as all previous
data has been sent (and received). If the data length is less than
16 bits, software must right-justify the data written to this register.
Read: software can read data from this register whenever the
RNE bit in the Status register is 1, indicating that the Rx FIFO is
not empty. When software reads this register, the SSP controller
returns data from the least recent frame in the Rx FIFO. If thedata length is less than 16 bits, the data is right-justified in thisfield with higher order bits filled with 0s.

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5.4 SSPn Status Register (SSP0SR - 0xE006 800C, SSP1SR 0xE003 000C)
This read-only register reflects the current status of the SSP controller.
Table 357: SSPn Status Register (SSP0SR - address 0xE006 800C, SSP1SR - 0xE003 000C)
bit description
Bit

SymbolDescription

Reset Value

0

TFE

Transmit FIFO Empty. This bit is 1 is the Transmit FIFO isempty, 0 if not.

1

1

TNF

Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1

2

RNEReceive FIFO Not Empty. This bit is 0 if the Receive FIFO isempty, 1 if not.

0

3

RFF

Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if
not.

0

4

BSY

Busy. This bit is 0 if the SSPn controller is idle, or 1 if it iscurrently sending/receiving a frame and/or the Tx FIFO is not
empty.

0

7:5-

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

5.5 SSPn Clock Prescale Register (SSP0CPSR - 0xE006 8010, SSP1CPSR- 0xE003 0010)
This register controls the factor by which the Prescaler divides the APB clock PCLK toyield the prescaler clock that is, in turn, divided by the SCR factor in SSPnCR0, to
determine the bit clock.
Table 358: SSPn Clock Prescale Register (SSP0CPSR - address 0xE006 8010, SSP1CPSR 0xE003 8010) bit description
Bit

SymbolDescription

Reset Value

7:0

CPSDVSR This even value between 2 and 254, by which PCLK is divided 0
to yield the prescaler output clock. Bit 0 always reads as 0.

Important: the SSPnCPSR value must be properly initialized or the SSP controller will not
be able to transmit data correctly. In case of an SSP operating in the master mode, the
CPSDVSRmin = 2, while in case of the slave mode CPSDVSRmin = 12.

5.6 SSPn Interrupt Mask Set/Clear Register (SSP0IMSC - 0xE006 8014,
SSP1IMSC - 0xE003 0014)
This register controls whether each of the four possible interrupt conditions in the SSP
controller are enabled. Note that ARM uses the word “masked” in the opposite sense fromclassic computer terminology, in which “masked” meant “disabled”. ARM uses the word
“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.

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Table 359: SSPn Interrupt Mask Set/Clear register (SSP0IMSC - address 0xE006 8014,
SSP1IMSC - 0xE003 0014) bit description
Bit

SymbolDescription

Reset
Value

0

RORIM

Software should set this bit to enable interrupt when a Receive0Overrun occurs, that is, when the Rx FIFO is full and another frame iscompletely received. The ARM spec implies that the preceding frame
data is overwritten by the new frame data when this occurs.

1

RTIM

Software should set this bit to enable interrupt when a Receive
Timeout condition occurs. A Receive Timeout occurs when the Rx
FIFO is not empty, and no has not been read for a "timeout period".

2

RXIM

Software should set this bit to enable interrupt when the Rx FIFO is at 0
least half full.

3

TXIM

Software should set this bit to enable interrupt when the Tx FIFO is at 0
least half empty.

7:4-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

0NA

5.7 SSPn Raw Interrupt Status Register (SSP0RIS - 0xE006 8018,
SSP1RIS - 0xE003 0018)
This read-only register contains a 1 for each interrupt condition that is asserted,
regardless of whether or not the interrupt is enabled in the SSPnIMSC.
Table 360: SSPn Raw Interrupt Status register (SSP0RIS - address 0xE006 8018, SSP1RIS 0xE003 0018) bit description
Bit

SymbolDescription

Reset Value0

RORRISThis bit is 1 if another frame was completely received while the 0
RxFIFO was full. The ARM spec implies that the preceding
frame data is overwritten by the new frame data when thisoccurs.

1

RTRIS

This bit is 1 if the Rx FIFO is not empty, and has not been read 0
for a "timeout period".

2

RXRIS

This bit is 1 if the Rx FIFO is at least half full.

0

3

TXRIS

This bit is 1 if the Tx FIFO is at least half empty.

1

7:4

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

5.8 SSPn Masked Interrupt Status Register (SSP0MIS - 0xE006 801C,
SSP1MIS - 0xE003 001C)
This read-only register contains a 1 for each interrupt condition that is asserted andenabled in the SSPnIMSC. When an SSP interrupt occurs, the interrupt service routine
should read this register to determine the cause(s) of the interrupt.

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Table 361: SSPn Masked Interrupt Status register (SSPnMIS -address 0xE006 801C,
SSP1MIS - 0xE003 001C) bit description
Bit

SymbolDescription

0

RORMISThis bit is 1 if another frame was completely received while the 0
RxFIFO was full, and this interrupt is enabled.

Reset Value

1

RTMIS

This bit is 1 if the Rx FIFO is not empty, has not been read fora "timeout period", and this interrupt is enabled.

2

RXMIS

This bit is 1 if the Rx FIFO is at least half full, and this interrupt 0
is enabled.

3

TXMIS

This bit is 1 if the Tx FIFO is at least half empty, and thisinterrupt is enabled.

0

7:4

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA0

5.9 SSPn Interrupt Clear Register (SSP0ICR - 0xE006 8020, SSP1ICR 0xE003 0020)
Software can write one or more one(s) to this write-only register, to clear thecorresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt
conditions can be cleared by writing or reading the appropriate FIFO, or disabled byclearing the corresponding bit in SSPnIMSC.
Table 362: SSPn interrupt Clear Register (SSP0ICR - address 0xE006 8020, SSP1ICR 0xE003 0020) bit description
Bit

SymbolDescription

Reset Value

0

RORIC

Writing a 1 to this bit clears the “frame was received when
RxFIFO was full” interrupt.

NA

1

RTIC

Writing a 1 to this bit clears the "Rx FIFO was not empty andhas not been read for a timeout period" interrupt.

NA

7:2

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

5.10 SSPn DMA Control Register (SSP0DMACR - 0xE006 8024,
SSP1DMACR - 0xE003 0024)
The SSPnDMACR register is the DMA control register.It is a read/write register.
Table 17–363 shows the bit assignments of the SSPnDMACR register.
Table 363: SSPn DMA Control Register (SSP0DMACR - address 0xE006 8024, SSP1DMACR 0xE003 0024) bit description
Bit

SymbolDescription

Reset
Value

0

Receive DMA
Enable(RXDMAE)

When this bit is set to one 1, DMA for the receive FIFO isenabled, otherwise receive DMA is disabled.

0

1

Transmit DMA
Enable(TXDMAE)

When this bit is set to one 1, DMA for the transmit FIFO isenabled, otherwise transmit DMA is disabled

0

15:2

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

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Chapter 18: SD_MMC card interface
Rev. 01 — 6 July 2007

User manual

1. Introduction
The Secure Digital and Multimedia Card Interface (MCI) is an interface between the
Advanced Peripheral Bus (APB) system bus and multimedia and/or secure digital memory
cards. It consists of two parts:• The MCI adapter block provides all functions specific to the Secure Digital/MultiMedia
memory card, such as the clock generation unit, power management control,
command and data transfer.

• The APB interface accesses the MCI adapter registers, and generates interrupt andDMA request signals.

2. Features of the MCI
The following features are provided by the MCI:

• Conformance to Multimedia Card Specification v2.11.
• Conformance to Secure Digital Memory Card Physical Layer Specification, v0.96.
• Use as a multimedia card bus or a secure digital memory card bus host. It can beconnected to several multimedia cards, or a single secure digital memory card.

• DMA supported through the General Purpose DMA Controller.

3. SD/MMC card interface pin description
Table 364. SD/MMC card interface pin description
Pin Name

Type

Description

MCICLK

OutputClock output

MCICMD

Input

Command input/output.

MCIDAT[3:0]OutputData lines. Only MCIDAT[0] is used for Multimedia cards.

MCIPWR

OutputPower Supply Enable for external SD/MMC power supply.

There is one additional signal needed in the interface, a power control line MCIPWR, but it
can be sourced from any GPIO signal.

4. Functional overview
The MCI may be used as a multimedia card bus host (see Section 18–4.1 “Mutimediacard”) or a secure digital memory card bus host (see Section 18–4.2 “Secure digitalmemory card”). Up to approximately 4 multimedia cards (limited by I/O pin specifications
and board loading) may be connected, or a single secure digital memory card.

4.1 Mutimedia card
Figure 18–72 shows the multimedia card system.
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MULTIMEDIA
CARD
INTERFACEPOWER
SUPPLY

MULTIMEDIA CARD BUS

CARD

CARD

CARD

MULTIMEDIA CARD STACK

Fig 72. Multimedia card system

Multimedia cards are grouped into three types according to their function:• Read Only Memory (ROM) cards, containing pre-programmed data
• Read/Write (R/W) cards, used for mass storage• Input/Output (I/O) cards, used for communication
The multimedia card system transfers commands and data using three signal lines:• CLK: One bit is transferred on both command and data lines with each clock cycle.
The clock frequency varies between 0 MHz and 20 MHz (for a multimedia card) or
0 MHz and 25 MHz (for a secure digital memory card).

• CMD: Bidirectional command channel that initializes a card and transfers commands.
CMD has two operational modes:– Open-drain for initialization– Push-pull for command transfer• DAT: Bidirectional data channel, operating in push-pull mode
4.2 Secure digital memory card
Figure 18–73 shows the secure digital memory card connection.

CLK
SECUREDIGITALMEMORY CARDCONTROLLER

CMD
D[3:0]

SECUREDIGITALMEMORY CARD

Fig 73. Secure digital memory card connection

4.2.1 Secure digital memory card bus signals
The following signals are used on the secure digital memory card bus:

• CLK Host to card clock signal
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4.3 MCI adapter
Figure 18–74 shows a simplified block diagram of the MCI adapter.

MULTIMEDIA CARD INTERFACEMCICLKCONTROLUNIT

APB BUSAPBINTERFACE

ADAPTERREGISTERSMCIPWRCOMMANDPATHDATA PATH

MCICMDMCIDATA [3:0]

FIFO

Fig 74. MCI adapter

The MCI adapter is a multimedia/secure digital memory card bus master that provides aninterface to a multimedia card stack or to a secure digital memory card. It consists of fivesubunits:• Adapter register block• Control unit
• Command path
• Data path
• Data FIFO
4.3.1 Adapter register block
The adapter register block contains all system registers. This block also generates thesignals that clear the static flags in the multimedia card. The clear signals are generated
when 1 is written into the corresponding bit location of the MCIClear register.

4.3.2 Control unit
The control unit contains the power management functions and the clock divider for the
memory card clock.
There are three power phases:• Power-off• Power-up• Power-on

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The power management logic controls an external power supply unit, and disables thecard bus output signals during the power-off or power-up phases. The power-up phase isa transition phase between the power-off and power-on phases, and allows an external
power supply to reach the card bus operating voltage. A device driver is used to ensurethat the PrimeCell MCI remains in the power-up phase until the external power supply
reaches the operating voltage.
The clock management logic generates and controls the MCICLK signal. The MCICLK
output can use either a clock divide or clock bypass mode. The clock output is inactive:• after reset• during the power-off or power-up phases• if the power saving mode is enabled and the card bus is in the IDLE state (eight clock
periods after both the command and data path subunits enter the IDLE phase)

4.3.3 Command path
The command path subunit sends commands to and receives responses from the cards.

4.3.4 Command path state machine
When the command register is written to and the enable bit is set, command transfer
starts. When the command has been sent, the Command Path State Machine (CPSM)
sets the status flags and enters the IDLE state if a response is not required. If a responseis required, it waits for the response (see Figure 18–75). When the response is received,
the received CRC code and the internally generated code are compared, and theappropriate status flags are set.

IDLE
Response received
or disabled orcommand CRC failed

Enabled andPending command

Disabled
PEND

RECEIVE

Disabled or
no response
Disabled
or timeout

Enabled andcommand start

Response
started

LastData

SEND

WAIT
Wait forresponse

Fig 75. Command path state machine

When the WAIT state is entered, the command timer starts running. If the timeout1 isreached before the CPSM moves to the RECEIVE state, the timeout flag is set and the
IDLE2 state is entered.
1.

The timeout period has a fixed value of 64 MCICLK clocks period.

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If the interrupt bit is set in the command register, the timer is disabled and the CPSM waits
for an interrupt request from one of the cards. If a pending bit is set in the command
register, the CPSM enters the PEND state, and waits for a CmdPend signal from the data
path subunit. When CmdPend is detected, the CPSM moves to the SEND state. This
enables the data counter to trigger the stop command transmission.
Figure 18–76 shows the MCI command transfer.

min 8
MCICLKMCICLKCOMMANDRESPONSE

COMMAND

State

IDLE

SEND

WAIT

RECEIVE

IDLE

SEND

MCICMD

HI-Z

controller drives

HI-Z

card drives

HI-Z

controller drives

Fig 76. MCI command transfer

4.3.5 Command format
The command path operates in a half-duplex mode, so that commands and responses
can either be sent or received. If the CPSM is not in the SEND state, the MCICMD output
is in HI-Z state, as shown in Figure 18–76. Data on MCICMD is synchronous to the rising
MCICLK edge. All commands have a fixed length of 48 bits. Table 18–365 shows thecommand format.
Table 365. Command format
Bit Position

Width

Value

Description

0

1

1

End bit.

7:1

7

-

CRC7

39:8

32

-

Argument.

45:40

6

-

Command index.

46

1

1

Transmission bit.

47

1

0

Stat bit.

The MCI adapter supports two response types. Both use CRC error checking:• 48 bit short response (see Table 18–366)• 136 bit long response (see Table 18–367)
Note: If the response does not contain CRC (CMD1 response), the device driver must
ignore the CRC failed status.

2.

The CPSM remains in the IDLE state for at least eight MCICLK periods to meet Ncc and Nrc timing constraints.

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Table 366. Simple response format
Bit Position

Width

Value

Description

0

1

1

End bit.

7:1

7

-

CRC7 (or 1111111).

39:8

32

-

Argument.

45:40

6

-

Command index.

46

1

0

Transmission bit.

47

1

0

Start bit.

Table 367. Long response format
Bit Position

Width

Value

Description

0

1

1

End bit.

127:1

127

-

CID or CSD (including internal CRC7).

133:128

6111111

Reserved.

134

1

1

Transmission bit.

135

1

0

Start bit.

The command register contains the command index (six bits sent to a card) and thecommand type. These determine whether the command requires a response, andwhether the response is 48 or 136 bits long (see Section 18–5.5 “Command Register(MCICommand - 0xE008 C00C)” for more information). The command path implements
the status flags shown in Table 18–368 (see Section 18–5.12 “Status Register (MCIStatus- 0xE008 C034)” for more information).
Table 368. Command path status flags
Flag

Description

CmdRespEnd

Set if response CRC is OK.

CmdCrcFail

Set if response CRC fails.

CmdSent

Set when command (that does not require response) is sent.

CmdTimeOut

Response timeout.

CmdActive

Command transfer in progress.

The CRC generator calculates the CRC checksum for all bits before the CRC code. This
includes the start bit, transmitter bit, command index, and command argument (or card
status). The CRC checksum is calculated for the first 120 bits of CID or CSD for the longresponse format. Note that the start bit, transmitter bit and the six reserved bits are notused in the CRC calculation.
The CRC checksum is a 7 bit value:
CRC[6:0] = Remainder [(M(x) × x7 ) / G(x)]G(x) = x7 + x3 + 1
M(x) = (start bit) × x39 + ... + (last bit before CRC) × x0 , orM(x) = (start bit) × x119 + ... + (last bit before CRC) × x0

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4.3.6 Data path
The card data bus width can be programmed using the clock control register. If the widebus mode is enabled, data is transferred at four bits per clock cycle over all four data
signals (MCIDAT[3:0]). If the wide bus mode is not enabled, only one bit per clock cycle istransferred over MCIDAT0.
Depending on the transfer direction (send or receive), the Data Path State Machine(DPSM) moves to the WAIT_S or WAIT_R state when it is enabled:• Send: The DPSM moves to the WAIT_S state. If there is data in the send FIFO, theDPSM moves to the SEND state, and the data path subunit starts sending data to acard.

• Receive: The DPSM moves to the WAIT_R state and waits for a start bit. When it
receives a start bit, the DPSM moves to the RECEIVE state, and the data path subunit
starts receiving data from a card.

4.3.7 Data path state machine
The DPSM operates at MCICLK frequency. Data on the card bus signals is synchronous
to the rising edge of MCICLK. The DPSM has six states, as shown in Figure 18–77.

Reset

Disabled or
FIFO underrun or
end of data or
CRC fail

IDLE

Disabled or
CRC fail ortimeout

Disabled or
Rx FIFO empty
or timeout or
start bit error

Disabled or
end of data
Enableand send

BUSY

Enable andnot send

Disabled or
CRC fail

WAIT_R

Not busy

WAIT_SEnd of packet

Start bit

End of packet
or end of data
or FIFO overrun

Data ready
SEND

RECEIVE

Fig 77. Data path state machine• IDLE: The data path is inactive, and the MCIDAT[3:0] outputs are in HI-Z. When thedata control register is written and the enable bit is set, the DPSM loads the data
counter with a new value and, depending on the data direction bit, moves to either the
WAIT_S or WAIT_R state.
WAIT_R: If the data counter equals zero, the DPSM moves to the IDLE state when
the receive FIFO is empty. If the data counter is not zero, the DPSM waits for a start
bit on MCIDAT.
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The DPSM moves to the RECEIVE state if it receives a start bit before a timeout, andloads the data block counter. If it reaches a timeout before it detects a start bit, or a start
bit error occurs, it moves to the IDLE state and sets the timeout status flag.

• RECEIVE: Serial data received from a card is packed in bytes and written to the data
FIFO. Depending on the transfer mode bit in the data control register, the data transfer
mode can be either block or stream:– In block mode, when the data block counter reaches zero, the DPSM waits until it
receives the CRC code. If the received code matches the internally generated
CRC code, the DPSM moves to the WAIT_R state. If not, the CRC fail status flag is
set and the DPSM moves to the IDLE state.
– In stream mode, the DPSM receives data while the data counter is not zero. Whenthe counter is zero, the remaining data in the shift register is written to the data
FIFO, and the DPSM moves to the WAIT_R state.
If a FIFO overrun error occurs, the DPSM sets the FIFO error flag and moves to the
WAIT_R state.

• WAIT_S: The DPSM moves to the IDLE state if the data counter is zero. If not, it waits
until the data FIFO empty flag is deasserted, and moves to the SEND state.
Note: The DPSM remains in the WAIT_S state for at least two clock periods to meet Nwr
timing constraints.

• SEND: The DPSM starts sending data to a card. Depending on the transfer mode bitin the data control register, the data transfer mode can be either block or stream:– In block mode, when the data block counter reaches zero, the DPSM sends aninternally generated CRC code and end bit, and moves to the BUSY state.
– In stream mode, the DPSM sends data to a card while the enable bit is HIGH andthe data counter is not zero. It then moves to the IDLE state.
If a FIFO underrun error occurs, the DPSM sets the FIFO error flag and moves to the
IDLE state.

• BUSY: The DPSM waits for the CRC status flag:– If it does not receive a positive CRC status, it moves to the IDLE state and sets the
CRC fail status flag.
– If it receives a positive CRC status, it moves to the WAIT_S state if MCIDAT0 is not
LOW (the card is not busy).
If a timeout occurs while the DPSM is in the BUSY state, it sets the data timeout flag andmoves to the IDLE state.
The data timer is enabled when the DPSM is in the WAIT_R or BUSY state, andgenerates the data timeout error:• When transmitting data, the timeout occurs if the DPSM stays in the BUSY state forlonger than the programmed timeout period• When receiving data, the timeout occurs if the end of the data is not true, and if the
DPSM stays in the WAIT_R state for longer than the programmed timeout period.

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4.3.8 Data counter
The data counter has two functions:• To stop a data transfer when it reaches zero. This is the end of the data condition.
• To start transferring a pending command (see Figure 18–78). This is used to send thestop command for a stream data transfer.

MCICLK

MCICMD

3

2

1

cmd state

MCIDAT0

0

7

6

5

4

PEND

Z

Z

data
counter

Z

3

2

1

CMD

CMD

CMD

SEND

Z

Z

S

7

CMD

CMD

6

CmdPendFig 78. Pending command start

The data block counter determines the end of a data block. If the counter is zero, theend-of-data condition is TRUE (see Section 18–5.10 “Data Control Register (MCIDataCtrl- 0xE008 C02C)” for more information).

4.3.9 Bus modeIn wide bus mode, all four data signals (MCIDAT[3:0]) are used to transfer data, and the
CRC code is calculated separately for each data signal. While transmitting data blocks toa card, only MCIDAT0 is used for the CRC token and busy signalling. The start bit must betransmitted on all four data signals at the same time (during the same clock period). If thestart bit is not detected on all data signals on the same clock edge while receiving data,
the DPSM sets the start bit error flag and moves to the IDLE state.
The data path also operates in half-duplex mode, where data is either sent to a card or
received from a card. While not being transferred, MCIDAT[3:0] are in the HI-Z state.
Data on these signals is synchronous to the rising edge of the clock period.
If standard bus mode is selected the MCIDAT[3:1] outputs are always in HI-Z state andonly the MCIDAT0 output is driven LOW when data is transmitted.
Design note: If wide mode is selected, both nMCIDAT0EN and nMCIDATEN outputs are
driven low at the same time. If not, the MCIDAT[3:1] outputs are always in HI-Z state(nMCIDATEN) is driven HIGH), and only the MCIDAT0 output is driven LOW when data istransmitted.

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4.3.10 CRC Token status
The CRC token status follows each write data block, and determines whether a card hasreceived the data block correctly. When the token has been received, the card asserts abusy signal by driving MCIDAT0 LOW. Table 18–369 shows the CRC token status values.
Table 369. CRC token status
Token

Description

010

Card has received error-free data block.

101

Card has detected a CRC error.

4.3.11 Status flags
Table 18–370 lists the data path status flags (see Section 18–5.12 “Status Register(MCIStatus - 0xE008 C034)” on page 412 for more information).
Table 370. Data path status flags
Flag

Description

TxFifoFull

Transmit FIFO is full.

TxFifoEmpty

Transmit FIFO is empty.

TxFifoHalfEmpty

Transmit FIFO is half full.

TxDataAvlbl

Transmit FIFO data available.

TxUnderrun

Transmit FIFO underrun error.

RxFifoFull

Receive FIFO is full.

RxFifoEmpty

Receive FIFO is empty.

RxFifoHalfFull

Receive FIFO is half full.

RxDataAvlbl

Receive FIFO data available.

RxOverrun

Receive FIFO overrun error.

DataBlockEnd

Data block sent/received.

StartBitErr

Start bit not detected on all data signals in wide bus mode.

DataCrcFail

Data packet CRC failed.

DataEnd

Data end (data counter is zero).

DataTimeOut

Data timeout.

TxActive

Data transmission in progress.

RxActive

Data reception in progress.

4.3.12 CRC generator
The CRC generator calculates the CRC checksum only for the data bits in a single block,and is bypassed in data stream mode. The checksum is a 16 bit value:
CRC[15:0] = Remainder [(M(x) × x15) / G(x)]G(x) = x16 + x12 + x5 + 1
M(x) - (first data bit) × xn + ... + (last data bit) ¥ X0

4.3.13 Data FIFO
The data FIFO (first-in-first-out) subunit is a data buffer with transmit and receive logic.

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The FIFO contains a 32 bit wide, 16-word deep data buffer, and transmit and receive
logic. Because the data FIFO operates in the APB clock domain (PCLK), all signals fromthe subunits in the MCI clock domain (MCLK) are resynchronized.
Depending on TxActive and RxActive, the FIFO can be disabled, transmit enabled, or
receive enabled. TxActive and RxActive are driven by the data path subunit and are
mutually exclusive:• The transmit FIFO refers to the transmit logic and data buffer when TxActive isasserted (see Section 18–4.3.14 “Transmit FIFO”)• The receive FIFO refers to the receive logic and data buffer when RxActive isasserted (see Section 18–4.3.15 “Receive FIFO”).

4.3.14 Transmit FIFO
Data can be written to the transmit FIFO through the APB interface once the MCI isenabled for transmission.
The transmit FIFO is accessible via 16 sequential addresses (see Section 18–5.16 “Data
FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008 C0BC)”). The transmit FIFO contains
a data output register that holds the data word pointed to by the read pointer. When thedata path subunit has loaded its shift register, it increments the read pointer and drives
new data out.
If the transmit FIFO is disabled, all status flags are deasserted. The data path subunit
asserts TxActive when it transmits data. Table 18–371 lists the transmit FIFO status flags.
Table 371. Transmit FIFO status flags
Flag

Description

TxFifoFull

Set to HIGH when all 16 transmit FIFO words contain valid data.

TxFifoEmpty

Set to HIGH when the transmit FIFO does not contain valid data.

TxHalfEmpty

Set to HIGH when 8 or more transmit FIFO words are empty. This flagcan be used as a DMA request.

TxDataAvlbl

Set to HIGH when the transmit FIFO contains valid data. This flag is theinverse of the TxFifoEmpty flag.

TxUnderrun

Set to HIGH when an underrun error occurs. This flag is cleared bywriting to the MCIClear register.

4.3.15 Receive FIFO
When the data path subunit receives a word of data, it drives data on the write data bus
and asserts the write enable signal. This signal is synchronized to the PCLK domain. The
write pointer is incremented after the write is completed, and the receive FIFO control
logic asserts RxWrDone, that then deasserts the write enable signal.
On the read side, the content of the FIFO word pointed to by the current value of the readpointer is driven on the read data bus. The read pointer is incremented when the APB bus
interface asserts RxRdPrtInc.
If the receive FIFO is disabled, all status flags are deasserted, and the read and write
pointers are reset. The data path subunit asserts RxActive when it receives data. Table
353 lists the receive FIFO status flags.

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The receive FIFO is accessible via 16 sequential addresses (see Section 18–5.16 “Data
FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008 C0BC)”).
If the receive FIFO is disabled, all status flags are deasserted, and the read and write
pointers are reset. The data path subunit asserts RxActive when it receives data.
Table 18–372 lists the receive FIFO status flags.
Table 372. Receive FIFO status flags
SymbolDescription

RxFifoFull

Set to HIGH when all 16 receive FIFO words contain valid data.

RxFifoEmpty

Set to HIGH when the receive FIFO does not contain valid data.

RxHalfFull

Set to HIGH when 8 or more receive FIFO words contain valid data. This
flag can be used as a DMA request.

RxDataAvlbl

Set to HIGH when the receive FIFO is not empty. This flag is the inverseof the RxFifoEmpty flag.

RxOverrun

Set to HIGH when an overrun error occurs. This flag is cleared by writing
to the MCIClear register.

4.3.16 APB interfaces
The APB interface generates the interrupt and DMA requests, and accesses the MCI
adapter registers and the data FIFO. It consists of a data path, register decoder, andinterrupt/DMA logic. DMA is controlled by the General Purpose DMA controller, see thatchapter for details.

4.3.17 Interrupt logic
The interrupt logic generates an interrupt request signal that is asserted when at least oneof the selected status flags is HIGH. A mask register is provided to allow selection of theconditions that will generate an interrupt. A status flag generates the interrupt request if acorresponding mask flag is set.

5. Register description
This section describes the MCI registers and provides programming details.

5.1 Summary of MCI Registers
The MCI registers are shown in Table 18–373.
Table 373. SPI register map
Name

Description

Address

MCIPower

Power control register.

R/W

8

0x00

0xE008 C000

MCIClock

Clock control register.

R/W

12

0x000

0xE008 C004

MCIArgument

Argument register.

R/W

32

0x00000000 0xE008 C008

MMCCommand Command register.

R/W

11

0x000

0xE008 C00C
0xE008 C010

MCIRespCmd

RO

6

0x00

MCIResponse0 Response register.

Response command register.

RO

32

0x00000000 0xE008 C014

MCIResponse1 Response register.

RO

32

0x00000000 0xE008 C018

MCIResponse2 Response register.

RO

32

0x00000000 0xE008 C01C

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Table 373. SPI register map
Name

Description

MCIResponse3 Response register.
MCIDataTimer

Data Timer.

Access Width Reset
Value[1]RO31

Address

0x00000000 0xE008 C020

R/W

32

0x00000000 0xE008 C024

MCIDataLength Data control register.

R/W

16

0x00000xE008 C028

MCIDataCtrl

Data control register.

R/W

8

0x00

0xE008 C02C

MCIDataCnt

Data counter.

RO

16

0x00000xE008 C030

MCIStatus

Status register.

RO

220x000000

0xE008 C034

MCIClear

Clear register.

WO

11

-

0xE008 C038

MCIMask0

Interrupt 0 mask register.

R/W

22

0x000000

0xE008 C03C

MCIMask1

Interrupt 1 mask register.

R/W

22

0x000000

0xE008 C040
0xE008 C048

MCIFifoCnt

FIFO Counter.

RO

150x0000MCIFIFO

Data FIFO Register.

R/W

32

0x00000000 0xE008 C080
to0xE008 C0BC

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

5.2 Power Control Register (MCI Power - 0xE008 C000)
The MCIPower register controls an external power supply. Power can be switched on andoff, and adjust the output voltage. Table 18–374 shows the bit assignment of theMCIPower register.
The active level of the MCIPWR (Power Supply Enable) pin can be selected by bit 3 of the
SCS register (see Section 3–7.1 “System Controls and Status register (SCS - 0xE01F
C1A0)” on page 28 for details).
Table 374: Power Control register (MCIPower - address 0xE008 C000) bit description
Bit

SymbolValue Description

Reset
Value

1:0

Ctrl

00

Power-off00

01

Reserved

10Power-up

11

Power-on

5:2-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

6OpenDrain

MCICMD output control.

0

7

Rod

Rod control.

0

31:8

-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

When the external power supply is switched on, the software first enters the power-up
phase, and waits until the supply output is stable before moving to the power-on phase.
During the power-up phase, MCIPWR is set HIGH. The card bus outlets are disabledduring both phases.

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Note: After a data write, data cannot be written to this register for three MCLK clock
periods plus two PCLK clock periods.

5.3 Clock Control Register (MCIClock - 0xE008 C004)
The MCIClock register controls the MCICLK output. Table 18–375 shows the bit
assignment of the clock control register.
Table 375: Clock Control register (MCIClock - address 0xE008 C004) bit description
Bit

SymbolValue Description

7:0

ClkDiv

MCI bus clock period:

8

EnableEnable MCI bus clock:

Reset
Value
0x00

MCLCLK frequency = MCLK / [2×(ClkDiv+1)].

9

10

11

31:12

0

Clock disabled.

1

Clock enabled.

0

Always enabled.

1

Clock enabled when bus is active.

PwrSave

Disable MCI clock output when bus is idle:

Bypass0

Enable bypass of clock divide logic:00Disable bypass.

1

Enable bypass. MCLK driven to card bus output (MCICLK).

WideBus-0

Enable wide bus mode:0Standard bus mode (only MCIDAT0 used).

1

Wide bus mode (MCIDAT3:0 used)0

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

While the MCI is in identification mode, the MCICLK frequency must be less than
400 kHz. The clock frequency can be changed to the maximum card bus frequency whenrelative card addresses are assigned to all cards.
Note: After a data write, data cannot be written to this register for three MCLK clock
periods plus two PCLK clock periods.

5.4 Argument Register (MCIArgument - 0xE008 C008)
The MCIArgument register contains a 32 bit command argument, which is sent to a cardas part of a command message. Table 18–376 shows the bit assignment of the
MCIArgument register.
Table 376: Argument register (MCIArgument - address 0xE008 C008) bit description
Bit

SymbolDescription

Reset Value

31:0

CmdArgCommand argument

0x0000 0000

If a command contains an argument, it must be loaded into the argument register before
writing a command to the command register.

5.5 Command Register (MCICommand - 0xE008 C00C)
The MCICommand register contains the command index and command type bits:
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Chapter 18: LPC2300 SD_MMC• The command index is sent to a card as part of a command message.
• The command type bits control the Command Path State Machine (CPSM). Writing 1
to the enable bit starts the command send operation, while clearing the bit disables
the CPSM.
Table 18–377 shows the bit assignment of the MCICommand register.
Table 377: Command register (MCICommand - address 0xE008 C00C) bit description
Bit

SymbolDescription

Reset
Value

5:0

CmdIndex Command index.

0

6

Response If set, CPSM waits for a response.

0

7

LongRspIf set, CPSM receives a 136 bit long response.

08Interrupt

If set, CPSM disables command timer and waits for interrupt request. 0

9Pending

If set, CPSM waits for CmdPend before it starts sending a command. 0

10

EnableIf set, CPSM is enabled.

0

31:11

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

Note: After a data write, data cannot be written to this register for three MCLK clock
periods plus two PCLK clock periods.
Table 18–378 shows the response types.
Table 378: Command Response Types
Response

Long Response

Description

00

No response, expect CmdSent flag.

01

No response, expect CmdSent flag.

1

0

Short response, expect CmdRespEnd or CmdCrcFail flag.

1

1

Long response, expect CmdRespEnd or CmdCrcFail flag.

5.6 Command Response Register (MCIRespCommand - 0xE008 C010)
The MCIRespCommand register contains the command index field of the last command
response received. Table 18–377 shows the bit assignment of the MCIRespCommand
register.
Table 379: Command Response register (MCIRespCommand - address 0xE008 C010) bit
description
Bit

SymbolDescription

Reset
Value

5:0

RespCmd Response command index

0x00

31:6

-

NA

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

If the command response transmission does not contain the command index field (longresponse), the RespCmd field is unknown, although it must contain 111111 (the value ofthe reserved field from the response).

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5.7 Response Registers (MCIResponse0-3 - 0xE008 C014, E008 C018,
E008 C01C and E008 C020)
The MCIResponse0-3 registers contain the status of a card, which is part of the received
response. Table 18–380 shows the bit assignment of the MCIResponse0-3 registers.
Table 380: Response registers (MCIResponse0-3 - addresses 0xE008 0014, 0xE008 C018,
0xE008 001C and 0xE008 C020) bit description
Bit

Symbol31:0 Status

Description

Reset Value

Card status

0x0000 0000

The card status size can be 32 or 127 bits, depending on the response type (seeTable 18–381).
Table 381: Response Register Type
Description

Short ResponseLong Response

MCIResponse0

Card status [31:0]

Card status [127:96]

MCIResponse1

UnusedCard status [95:64]

MCIResponse2

UnusedCard status [63:32]

MCIResponse3

UnusedCard status [31:1]

The most significant bit of the card status is received first. The MCIResponse3 register
LSBit is always 0.

5.8 Data Timer Register (MCIDataTimer - 0xE008 C024)
The MCIDataTimer register contains the data timeout period, in card bus clock periods.
Table 18–382 shows the bit assignment of the MCIDataTimer register.
Table 382: Data Timer register (MCIDataTimer - address 0xE008 C024) bit description
Bit

SymbolDescription

Reset Value

31:0

DataTime

Data timeout period.

0x0000 0000

A counter loads the value from the data timer register, and starts decrementing when the
Data Path State Machine (DPSM) enters the WAIT_R or BUSY state. If the timer reaches
0 while the DPSM is in either of these states, the timeout status flag is set.
A data transfer must be written to the data timer register and the data length register
before being written to the data control register.

5.9 Data Length Register (MCIDataLength - 0xE008 C028)
The MCIDataLength register contains the number of data bytes to be transferred. The
value is loaded into the data counter when data transfer starts. Table 18–383 shows the
bit assignment of the MCIDataLength register.
Table 383: Data Length register (MCIDataLength - address 0xE008 C028) bit description
Bit

SymbolDescription

Reset
Value

15:0

DataLength

Data length value

0x0000

31:16-

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

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For a block data transfer, the value in the data length register must be a multiple of theblock size (see Section 18–5.10 “Data Control Register (MCIDataCtrl - 0xE008 C02C)”).
To initiate a data transfer, write to the data timer register and the data length register
before writing to the data control register.

5.10 Data Control Register (MCIDataCtrl - 0xE008 C02C)
The MCIDataCtrl register controls the DPSM. Table 18–384 shows the bit assignment of
the MCIDataCtrl register.
Table 384: Data Control register (MCIDataCtrl - address 0xE008 C02C) bit description
Bit

Symbol0

EnableData transfer enable.

01

Direction

Data transfer direction:

0

2

3

7:4

Value Description

0

From controller to card.

1

From card to controller.

0

Block data transfer.

1

Stream data transfer.

Mode

Reset
Value

Data transfer mode:

DMAEnable

0

Enable DMA:0DMA disabled.

1

DMA enabled.

BlockSize

31:8 -

0

Data block length0

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

Note: After a data write, data cannot be written to this register for three MCLK clock
periods plus two PCLK clock periods.
Data transfer starts if 1 is written to the enable bit. Depending on the direction bit, theDPSM moves to the WAIT_S or WAIT_R state. It is not necessary to clear the enable bit
after the data transfer. BlockSize controls the data block length if Mode is 0, as shown in
Table 18–385.
Table 385: Data Block Length
Block Size

Block Length0

20= 1 byte.

1

21 = 2 bytes.

...

-

11

211 = 2048 bytes.

12:15

Reserved.

5.11 Data Counter Register (MCIDataCnt - 0xE008 C030)
The MCIDataCnt register loads the value from the data length register (see Section
18–5.9 “Data Length Register (MCIDataLength - 0xE008 C028)”) when the DPSM moves
from the IDLE state to the WAIT_R or WAIT_S state. As data is transferred, the counter

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decrements the value until it reaches 0. The DPSM then moves to the IDLE state and thedata status end flag is set. Table 18–386 shows the bit assignment of the MCIDataCnt
register.
Table 386: Data Counter register (MCIDataCnt - address 0xE008 C030) bit description
Bit

SymbolDescription

Reset
Value

15:0

DataCount Remaining data

0x0000

31:16

-

NA

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

Note: This register should be read only when the data transfer is complete.

5.12 Status Register (MCIStatus - 0xE008 C034)
The MCIStatus register is a read-only register. It contains two types of flag:• Static [10:0]: These remain asserted until they are cleared by writing to the Clear
register (see Section 18–5.13 “Clear Register (MCIClear - 0xE008 C038)”).

• Dynamic [21:11]: These change state depending on the state of the underlying logic(for example, FIFO full and empty flags are asserted and deasserted as data while
written to the FIFO).
Table 18–387 shows the bit assignment of the MCIStatus register.
Table 387: Status register (MCIStatus - address 0xE008 C034) bit description
Bit

SymbolDescription

Reset
Value

0

CmdCrcFail

Command response received (CRC check failed).

0

1

DataCrcFail

Data block sent/received (CRC check failed).

02

CmdTimeOut

Command response timeout.

03

DataTimeOut

Data timeout.

0

4

TxUnderrun

Transmit FIFO underrun error.

0

5

RxOverrun

Receive FIFO overrun error.

06

CmdRespEnd

Command response received (CRC check passed).

0

7

CmdSent

Command sent (no response required).

08

DataEnd

Data end (data counter is zero).

09StartBitErr

Start bit not detected on all data signals in wide bus mode. 0

10

DataBlockEnd

Data block sent/received (CRC check passed).

11

CmdActive

Command transfer in progress.

012

TxActive

Data transmit in progress.

013

RxActive

Data receive in progress.

0

14

TxFifoHalfEmpty Transmit FIFO half empty.

0

15

RxFifoHalfFull

Receive FIFO half full.

0

16

TxFifoFull

Transmit FIFO full.

0

17

RxFifoFull

Receive FIFO full.

0

18

TxFifoEmpty

Transmit FIFO empty.

0

19

RxFifoEmpty

Receive FIFO empty.

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Table 387: Status register (MCIStatus - address 0xE008 C034) bit description
Bit

SymbolDescription

Reset
Value

20

TxDataAvlbl

Data available in transmit FIFO.

0

21

RxDataAvlbl

Data available in receive FIFO.

0

31:22

-

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

5.13 Clear Register (MCIClear - 0xE008 C038)
The MCIClear register is a write-only register. The corresponding static status flags can becleared by writing a 1 to the corresponding bit in the register. Table 18–388 shows the bit
assignment of the MCIClear register.
Table 388: Clear register (MCIClear - address 0xE008 C038) bit description
Bit

SymbolDescription

Reset
Value

0
1

CmdCrcFailClr

Clears CmdCrcFail flag.

-

DataCrcFailClr

Clears DataCrcFail flag.

-

2

CmdTimeOutClr

Clears CmdTimeOut flag.

-

3

DataTimeOutClr

Clears DataTimeOut flag.

-

4

TxUnderrunClr

Clears TxUnderrun flag.

-

5

RxOverrunClr

Clears RxOverrun flag.

-

6

CmdRespEndClr

Clears CmdRespEnd flag.

-

7

CmdSentClr

Clears CmdSent flag.

-

8

DataEndClr

Clears DataEnd flag.

-

9

StartBitErrClr

Clears StartBitErr flag.

-

10

DataBlockEndClr

Clears DataBlockEnd flag.

-

31:11

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

5.14 Interrupt Mask Registers (MCIMask0 - 0xE008 C03C and MCIMask1 0xE008 C0040)
The interrupt mask registers determine which status flags generate an interrupt request by
setting the corresponding bit to 1. Table 18–389 shows the bit assignment of the
MCIMaskx registers.
Table 389: Interrupt Mask registers (MCIMask0 - address 0xE008 C03C and MCIMask1 address 0xE008 C040) bit description
Bit

SymbolDescription

Reset
Value

0

Mask0

Mask CmdCrcFail flag.

0

1

Mask1

Mask DataCrcFail flag.

0

2

Mask2

Mask CmdTimeOut flag.

0

3

Mask3

Mask DataTimeOut flag.

0

4

Mask4

Mask TxUnderrun flag.

0

5

Mask5

Mask RxOverrun flag.

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Table 389: Interrupt Mask registers (MCIMask0 - address 0xE008 C03C and MCIMask1 address 0xE008 C040) bit description
Bit

SymbolDescription

Reset
Value

6

Mask6

Mask CmdRespEnd flag.

0

7

Mask7

Mask CmdSent flag.

0

8

Mask8

Mask DataEnd flag.

0

9

Mask9

Mask StartBitErr flag.

010

Mask10

Mask DataBlockEnd flag.

011

Mask11

Mask CmdActive flag.

012

Mask12

Mask TxActive flag.

013

Mask13

Mask RxActive flag.

014

Mask14

Mask TxFifoHalfEmpty flag.

015

Mask15

Mask RxFifoHalfFull flag.

016

Mask16

Mask TxFifoFull flag.

017

Mask17

Mask RxFifoFull flag.

018

Mask18Mask TxFifoEmpty flag.

019

Mask19Mask RxFifoEmpty flag.

020

Mask20

Mask TxDataAvlbl flag.

021

Mask21

Mask RxDataAvlbl flag.

0

31:22

-

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

5.15 FIFO Counter Register (MCIFifoCnt - 0xE008 C048)
The MCIFifoCnt register contains the remaining number of words to be written to or readfrom the FIFO. The FIFO counter loads the value from the data length register (seeSection 18–5.9 “Data Length Register (MCIDataLength - 0xE008 C028)”) when the
Enable bit is set in the data control register. If the data length is not word aligned (multipleof 4), the remaining 1 to 3 bytes are regarded as a word. Table 18–390 shows the bit
assignment of the MCIFifoCnt register.
Table 390: FIFO Counter register (MCIFifoCnt - address 0xE008 C048) bit description
Bit

SymbolDescription

Reset
Value

14:0

DataCount

Remaining data

0x0000

31:15-

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

5.16 Data FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008 C0BC)
The receive and transmit FIFOs can be read or written as 32 bit wide registers. The FIFOs
contain 16 entries on 16 sequential addresses. This allows the microprocessor to use its
load and store multiple operands to read/write to the FIFO. Table 18–391 shows the bit
assignment of the MCIFIFO register.

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Table 391: Data FIFO register (MCIFIFO - address 0xE008 C080 to 0xE008 C0BC) bit
description
Bit

SymbolDescription

Reset Value

31:0

Data

FIFO data.

0x0000 0000

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Chapter 19: I2C interfaces I2C0, I2C1, I2C2
Rev. 01 — 6 July 2007

User manual

1. Features• Standard I2C compliant bus interfaces that may be configured as Master, Slave, orMaster/Slave.

• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.

• Programmable clock to allow adjustment of I2C transfer rates.
• Bidirectional data transfer between masters and slaves.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend andresume serial transfer.

• The I2C bus may be used for test and diagnostic purposes.

2. Applications
Interfaces to external I2C standard parts, such as serial RAMs, LCDs, tone generators,
etc.

3. Description
A typical I2C bus configuration is shown in Figure 19–79. Depending on the state of thedirection bit (R/W), two types of data transfers are possible on the I2C bus:

• Data transfer from a master transmitter to a slave receiver. The first byte transmitted
by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte.

• Data transfer from a slave transmitter to a master receiver. The first byte (the slave
address) is transmitted by the master. The slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last byte. At the end of thelast received byte, a “not acknowledge” is returned. The master device generates allof the serial clock pulses and the START and STOP conditions. A transfer is ended
with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the I2C bus will not bereleased.
Each of the three I2C interfaces on the LPC2300 is byte oriented, and has four operating
modes: master transmitter mode, master receiver mode, slave transmitter mode andslave receiver mode.
The three I2C interfaces are identical except for the pin I/O characteristics. I2C0 complies
with entire I2C specification, supporting the ability to turn power off to the LPC2300
without causing a problem with other devices on the same I2C bus (see "The I2C-bus
specification" description under the heading "Fast-Mode", and notes for the table titled
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Chapter 19: LPC2300 I2C0, I2C1, I2C2"Characteristics of the SDA and SCL I/O stages for F/S-mode I2C-bus devices"). This issometimes a useful capability, but intrinsically limits alternate uses for the same pins if the
I2C interface is not used. Seldom is this capability needed on multiple I2C interfaces
within the same microcontroller. Therefore, I2C1 and I2C2 are implemented using
standard port pins, and do not support the ability to turn power off to the LPC2300 whileleaving the I2C bus functioning between other devices. This difference should beconsidered during system design while assigning uses for the I2C interfaces.

pull-upresistorpull-upresistor

SDA
I 2C bus
SCL

SDA

SCL

LPC2300

OTHER DEVICE WITH
I 2C INTERFACEOTHER DEVICE WITH
I 2C INTERFACE

Fig 79. I2C bus configuration

4. Pin description
Table 392. I2C Pin Description
Pin

Type

Description

SDA0,1, 2

Input/Output

I2C Serial Data.

SCL0,1, 2

Input/Output

I2C Serial Clock.

5. I2C operating modes
In a given application, the I2C block may operate as a master, a slave, or both. In the slavemode, the I2C hardware looks for its own slave address and the general call address. If
one of these addresses is detected, an interrupt is requested. If the processor wishes tobecome the bus master, the hardware waits until the bus is free before the master mode isentered so that a possible slave operation is not interrupted. If bus arbitration is lost in themaster mode, the I2C block switches to the slave mode immediately and can detect its
own slave address in the same serial transfer.

5.1 Master Transmitter mode
In this mode data is transmitted from master to slave. Before the master transmitter modecan be entered, the I2CONSET register must be initialized as shown in Table 19–393.
I2EN must be set to 1 to enable the I2C function. If the AA bit is 0, the I2C interface will not
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Chapter 19: LPC2300 I2C0, I2C1, I2C2

acknowledge any address when another device is master of the bus, so it can not enter
slave mode. The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the
SIC bit in the I2CONCLR register.
Table 393. I2CnCONSET used to configure Master mode
Bit

7

6

5

4

3

2

1

0

Symbol

-

I2EN

STA

STO

SI

AA

-

-

Value

-

1

0

0

0

0

-

-

The first byte transmitted contains the slave address of the receiving device (7 bits) andthe data direction bit. In this mode the data direction bit (R/W) should be 0 which means
Write. The first byte transmitted contains the slave address and Write bit. Data istransmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.
START and STOP conditions are output to indicate the beginning and the end of a serialtransfer.
The I2C interface will enter master transmitter mode when software sets the STA bit. The
I2C logic will send the START condition as soon as the bus is free. After the START
condition is transmitted, the SI bit is set, and the status code in the I2STAT register is
0x08. This status code is used to vector to a state service routine which will load the slave
address and Write bit to the I2DAT register, and then clear the SI bit. SI is cleared bywriting a 1 to the SIC bit in the I2CONCLR register.
When the slave address and R/W bit have been transmitted and an acknowledgment bit
has been received, the SI bit is set again, and the possible status codes now are 0x18,
0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xB0 if the slave mode was enabled(by setting AA to 1). The appropriate actions to be taken for each of these status codes
are shown in Table 19–408 to Table 19–411.

S

SLAVE ADDRESS

RW

A

DATA

“0” - write“1” - read

A

A/A

DATA

P

data transferred(n Bytes + Acknowledge)
A = Acknowledge (SDA low)from Master to Slave

A = Not acknowledge (SDA high)from Slave to MasterS = START condition
P = STOP condition

Fig 80. Format in the Master Transmitter mode

5.2 Master Receiver mode
In the master receiver mode, data is received from a slave transmitter. The transfer is
initiated in the same way as in the master transmitter mode. When the START condition
has been transmitted, the interrupt service routine must load the slave address and thedata direction bit to the I2C Data Register (I2DAT), and then clear the SI bit. In this case,the data direction bit (R/W) should be 1 to indicate a read.

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When the slave address and data direction bit have been transmitted and an
acknowledge bit has been received, the SI bit is set, and the Status Register will show thestatus code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. For
slave mode, the possible status codes are 0x68, 0x78, or 0xB0. For details, refer toTable 19–409.

S

SLAVE ADDRESS

R

A

DATA

A

“0” - write“1” - read

A

DATA

P

data transferred(n Bytes + Acknowledge)
A = Acknowledge (SDA low)from Master to Slave

A = Not acknowledge (SDA high)from Slave to MasterS = START condition
P = STOP condition

Fig 81. Format of Master Receive mode

After a repeated START condition, I2C may switch to the master transmitter mode.

S

SLA

R

A

DATA

A

DATA

A

RS

SLA

W

A

DATA

A

P

data transferred(n Bytes + Acknowledge)
A = Acknowledge (SDA low)
From master to slave

A = Not acknowledge (SDA high)From slave to masterS = START condition
P = STOP condition
SLA = Slave Address

Fig 82. A master receiver switch to master Transmitter after sending repeated START

5.3 Slave Receiver mode
In the slave receiver mode, data bytes are received from a master transmitter. To initialize
the slave receiver mode, user write the Slave Address Register (I2ADR) and write the I2C
Control Set Register (I2CONSET) as shown in Table 19–394.
Table 394. I2CnCONSET used to configure Slave mode
Bit

7

6

5

4

3

2

1

0

Symbol

-

I2EN

STA

STO

SI

AA

-

-

Value

-

1

0

0

0

1

-

-

I2EN must be set to 1 to enable the I2C function. AA bit must be set to 1 to acknowledge
its own slave address or the general call address. The STA, STO and SI bits are set to 0.
After I2ADR and I2CONSET are initialized, the I2C interface waits until it is addressed byits own address or general address followed by the data direction bit. If the direction bit is
0 (W), it enters slave receiver mode. If the direction bit is 1 (R), it enters slave transmitter
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mode. After the address and direction bit have been received, the SI bit is set and a valid
status code can be read from the Status Register (I2STAT). Refer to Table 19–410 for the
status codes and actions.

S

SLAVE ADDRESS

W

A

DATA

“0” - write“1” - read

A

A/A

DATA

P/RS

data transferred(n Bytes + Acknowledge)
A = Acknowledge (SDA low)from Master to Slavefrom Slave to Master

A = Not acknowledge (SDA high)S = START condition
P = STOP condition
RS = Repeated START condition

Fig 83. Format of Slave Receiver mode

5.4 Slave Transmitter mode
The first byte is received and handled as in the slave receiver mode. However, in thismode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via
SDA while the serial clock is input through SCL. START and STOP conditions arerecognized as the beginning and end of a serial transfer. In a given application, I2C may
operate as a master and as a slave. In the slave mode, the I2C hardware looks for its own
slave address and the general call address. If one of these addresses is detected, aninterrupt is requested. When the microcontrollers wishes to become the bus master, thehardware waits until the bus is free before the master mode is entered so that a possible
slave action is not interrupted. If bus arbitration is lost in the master mode, the I2C
interface switches to the slave mode immediately and can detect its own slave address inthe same serial transfer.

S

SLAVE ADDRESSR

A“0” - write“1” - read

DATA

A

A

DATA

P

data transferred(n Bytes + Acknowledge)
A = Acknowledge (SDA low)from Master to Slave

A = Not acknowledge (SDA high)from Slave to MasterS = START condition
P = STOP condition

Fig 84. Format of Slave Transmitter mode

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6. I2C implementation and operation
6.1 Input filters and output stages
Input signals are synchronized with the internal clock , and spikes shorter than threeclocks are filtered out.
The output for I2C is a special pad designed to conform to the I2C specification. The
outputs for I2C1 and I2C2 are standard port I/Os that support a subset of the full I2C
specification.
Figure 19–85 shows how the on-chip I2C bus interface is implemented, and the following
text describes the individual blocks.

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8

I2ADR

ADDRESS REGISTERCOMPARATORINPUTFILTERSDA
OUTPUTSTAGE

SHIFT REGISTER

ACK
I2DAT

BIT COUNTER/
ARBITRATION &SYNC LOGICINPUTFILTERPCLK

APB BUS8

TIMING &CONTROL
LOGIC

SCLinterrupt

SERIAL CLOCK
GENERATOROUTPUT
STAGE

I2CONSETI2CONCLR
I2SCLHI2SCLLCONTROL REGISTER & SCL DUTYCYCLE REGISTERS

16

statusbus

STATUSDECODERSTATUS REGISTERI2STAT8

Fig 85. I2C Bus serial interface block diagram

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6.2 Address Register I2ADDRThis register may be loaded with the 7 bit slave address (7 most significant bits) to which
the I2C block will respond when programmed as a slave transmitter or receiver. The LSB(GC) is used to enable general call address (0x00) recognition.

6.3 Comparator
The comparator compares the received 7 bit slave address with its own slave address (7most significant bits in I2ADR). It also compares the first received 8 bit byte with thegeneral call address (0x00). If an equality is found, the appropriate status bits are set andan interrupt is requested.

6.4 Shift register I2DATThis 8 bit register contains a byte of serial data to be transmitted or a byte which has justbeen received. Data in I2DAT is always shifted from right to left; the first bit to betransmitted is the MSB (bit 7) and, after a byte has been received, the first bit of received
data is located at the MSB of I2DAT. While data is being shifted out, data on the bus issimultaneously being shifted in; I2DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from master transmitter to slave
receiver is made with the correct data in I2DAT.

6.5 Arbitration and synchronization logic
In the master transmitter mode, the arbitration logic checks that every transmitted logic 1
actually appears as a logic 1 on the I2C bus. If another device on the bus overrules a logic
1 and pulls the SDA line low, arbitration is lost, and the I2C block immediately changes
from master transmitter to slave receiver. The I2C block will continue to output clock
pulses (on SCL) until transmission of the current serial byte is complete.
Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode
can only occur while the I2C block is returning a “not acknowledge: (logic 1) to the bus.
Arbitration is lost when another device on the bus pulls this signal LOW. Since this canoccur only at the end of a serial byte, the I2C block generates no further clock pulses.
Figure 19–86 shows the arbitration procedure.

(1)

(1)

(2)

1

2

3

(3)

SDA line

SCL line

4

8

9
ACK

(1) A device transmits serial data.
(2) Another device overrules a logic 1 (dotted line), transmitted by this I2C master, by pulling the
SDA line low. Arbitration is lost, and this I2C enters Slave Receiver mode.
(3) This I2C is in Slave Receiver mode but still generates clock pulses until the current byte has
been transmitted. This I2C will not generate clock pulses for the next byte. Data on SDA
originates from the new master once it has won arbitration.

Fig 86. Arbitration procedure

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The synchronization logic will synchronize the serial clock generator with the clock pulses
on the SCL line from another device. If two or more master devices generate clock pulses,
the “mark” duration is determined by the device that generates the shortest “marks,” andthe “space” duration is determined by the device that generates the longest “spaces”.
Figure 19–87 shows the synchronization procedure.

SDA line
(1)

(3)

(1)

SCL line(2)
highperiodlow
period(1) Another device pulls the SCL line low before this I2C has timed a complete high time. The otherdevice effectively determines the (shorter) HIGH period.
(2) Another device continues to pull the SCL line low after this I2C has timed a complete low timeand released SCL. The I2C clock generator is forced to wait until SCL goes HIGH. The otherdevice effectively determines the (longer) LOW period.
(3) The SCL line is released , and the clock generator begins timing the HIGH time.

Fig 87. Serial clock synchronization

A slave may stretch the space duration to slow down the bus master. The space duration
may also be stretched for handshaking purposes. This can be done after each bit or after
a complete byte transfer. the I2C block will stretch the SCL space duration after a byte has
been transmitted or received and the acknowledge bit has been transferred. The serialinterrupt flag (SI) is set, and the stretching continues until the serial interrupt flag iscleared.

6.6 Serial clock generator
This programmable clock pulse generator provides the SCL clock pulses when the I2C
block is in the master transmitter or master receiver mode. It is switched off when the I2C
block is in a slave mode. The I2C output clock frequency and duty cycle is programmable
via the I2C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH
registers for details. The output clock pulses have a duty cycle as programmed unless thebus is synchronizing with other SCL clock sources as described above.

6.7 Timing and control
The timing and control logic generates the timing and control signals for serial byte
handling. This logic block provides the shift pulses for I2DAT, enables the comparator,
generates and detects start and stop conditions, receives and transmits acknowledge bits,
controls the master and slave modes, contains interrupt request logic, and monitors theI2C bus status.

6.8 Control register I2CONSET and I2CONCLR
The I2C control register contains bits used to control the following I2C block functions: startand restart of a serial transfer, termination of a serial transfer, bit rate, address recognition,
and acknowledgment.
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The contents of the I2C control register may be read as I2CONSET. Writing to I2CONSET
will set bits in the I2C control register that correspond to ones in the value written.
Conversely, writing to I2CONCLR will clear bits in the I2C control register that correspondto ones in the value written.

6.9 Status decoder and status register
The status decoder takes all of the internal status bits and compresses them into a 5 bitcode. This code is unique for each I2C bus status. The 5 bit code may be used to generate
vector addresses for fast processing of the various service routines. Each service routine
processes a particular bus status. There are 26 possible bus states if all four modes of the
I2C block are used. The 5 bit status code is latched into the five most significant bits of thestatus register when the serial interrupt flag is set (by hardware) and remains stable until
the interrupt flag is cleared by software. The three least significant bits of the status
register are always zero. If the status code is used as a vector to service routines, then theroutines are displaced by eight address locations. Eight bytes of code is sufficient for mostof the service routines (see the software example in this section).

7. Register description
Each I2C interface contains 7 registers as shown in Table 19–395 below.
Table 395. I2C register map
Generic
Name

Description

AccessReset I2Cn Registervalue[1] Name & Address

I2CONSET I2C Control Set Register. When a one is written to a R/W
bit of this register, the corresponding bit in the I2C
control register is set. Writing a zero has no effect on
the corresponding bit in the I2C control register.

0x00

I2C0CONSET - 0xE001 C000
I2C1CONSET - 0xE005 C000
I2C2CONSET - 0xE008 0000

I2STATI2C Status Register. During I2C operation, thisregister provides detailed status codes that allow
software to determine the next action needed.

RO

0xF8

I2C0STAT - 0xE001 C004
I2C1STAT - 0xE005 C004
I2C2STAT - 0xE008 0004

I2DAT

I2C Data Register. During master or slave transmit
R/Wmode, data to be transmitted is written to this register.
During master or slave receive mode, data that has
been received may be read from this register.

0x00

I2C0DAT - 0xE001 C008
I2C1DAT - 0xE005 C008
I2C2DAT - 0xE008 0008

I2ADR

I2C Slave Address Register. Contains the 7 bit slave R/Waddress for operation of the I2C interface in slavemode, and is not used in master mode. The leastsignificant bit determines whether a slave responds to
the general call address.

0x00

I2C0ADR - 0xE001 C00CI2C1ADR - 0xE005 C00CI2C2ADR - 0xE008 000C

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Table 395. I2C register map
Generic
Name

Description

AccessReset I2Cn Registervalue[1] Name & Address

I2SCLHSCH Duty Cycle Register High Half Word.
Determines the high time of the I2C clock.

R/W

0x04

I2C0SCLH - 0xE001 C010
I2C1SCLH - 0xE005 C010
I2C2SCLH - 0xE008 0010

I2SCLLR/W
SCL Duty Cycle Register Low Half Word.
Determines the low time of the I2C clock. I2nSCLL
and I2nSCLH together determine the clock frequency
generated by an I2C master and certain times used inslave mode.

0x04

I2C0SCLL - 0xE001 C014
I2C1SCLL - 0xE005 C014
I2C2SCLL - 0xE008 0014

NA

I2C0CONCLR - 0xE001 C018
I2C1CONCLR - 0xE005 C018
I2C2CONCLR - 0xE008 0018

I2CONCLR I2C Control Clear Register. When a one is written to WO
a bit of this register, the corresponding bit in the I2C
control register is cleared. Writing a zero has no effecton the corresponding bit in the I2C control register.
[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

7.1 I2C Control Set Register (I2C[0/1/2]CONSET: 0xE001 C000,
0xE005 C000, 0xE008 0000)
The I2CONSET registers control setting of bits in the I2CON register that controls
operation of the I2C interface. Writing a one to a bit of this register causes thecorresponding bit in the I2C control register to be set. Writing a zero has no effect.
Table 396. I2C Control Set Register (I2C[0/1/2]CONSET - addresses: 0xE001 C000,
0xE005 C000, 0xE008 0000) bit description
Bit Symbol

Description

Reset
Value

1:0 -

Reserved. User software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.

2

AA

Assert acknowledge flag. See the text below.

3SI

I2C interrupt flag.

4

STO

STOP flag. See the text below.

0

5

STA

START flag. See the text below.

0

6

I2EN

I2C interface enable. See the text below.

0

7

-

Reserved. User software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.

0

I2EN I2C Interface Enable. When I2EN is 1, the I2C interface is enabled. I2EN can becleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I2C
interface is disabled.
When I2EN is “0”, the SDA and SCL input signals are ignored, the I2C block is in the “notaddressed” slave state, and the STO bit is forced to “0”.
I2EN should not be used to temporarily release the I2C bus since, when I2EN is reset, theI2C bus status is lost. The AA flag should be used instead.
STA is the START flag. Setting this bit causes the I2C interface to enter master mode andtransmit a START condition or transmit a repeated START condition if it is already inmaster mode.

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When STA is 1 and the I2C interface is not already in master mode, it enters master mode,
checks the bus and generates a START condition if the bus is free. If the bus is not free, it
waits for a STOP condition (which will free the bus) and generates a START condition
after a delay of a half clock period of the internal clock generator. If the I2C interface isalready in master mode and data has been transmitted or received, it transmits a repeated
START condition. STA may be set at any time, including when the I2C interface is in an
addressed slave mode.
STA can be cleared by writing 1 to the STAC bit in the I2CONCLR register. When STA is0, no START condition or repeated START condition will be generated.
If STA and STO are both set, then a STOP condition is transmitted on the I2C bus if it theinterface is in master mode, and transmits a START condition thereafter. If the I2C
interface is in slave mode, an internal STOP condition is generated, but is not transmitted
on the bus.
STO is the STOP flag. Setting this bit causes the I2C interface to transmit a STOP
condition in master mode, or recover from an error condition in slave mode. When STO is
1 in master mode, a STOP condition is transmitted on the I2C bus. When the bus detects
the STOP condition, STO is cleared automatically.
In slave mode, setting this bit can recover from an error condition. In this case, no STOP
condition is transmitted to the bus. The hardware behaves as if a STOP condition has
been received and it switches to “not addressed” slave receiver mode. The STO flag iscleared by hardware automatically.
SI is the I2C Interrupt Flag. This bit is set when the I2C state changes. However, entering
state F8 does not set SI since there is nothing for an interrupt service routine to do in thatcase.
While SI is set, the low period of the serial clock on the SCL line is stretched, and theserial transfer is suspended. When SCL is high, it is unaffected by the state of the SI flag.
SI must be reset by software, by writing a 1 to the SIC bit in I2CONCLR register.
AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA)
will be returned during the acknowledge clock pulse on the SCL line on the following
situations:
1. The address in the Slave Address Register has been received.
2. The general call address has been received while the general call bit (GC) in I2ADR is
set.
3. A data byte has been received while the I2C is in the master receiver mode.
4. A data byte has been received while the I2C is in the addressed slave receiver mode.
The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA
is 0, a not acknowledge (high level to SDA) will be returned during the acknowledge clock
pulse on the SCL line on the following situations:
1. A data byte has been received while the I2C is in the master receiver mode.
2. A data byte has been received while the I2C is in the addressed slave receiver mode.

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7.2 I2C Control Clear Register (I2C[0/1/2]CONCLR: 0xE001 C018,
0xE005 C018, 0xE008 0018)
The I2CONCLR registers control clearing of bits in the I2CON register that controls
operation of the I2C interface. Writing a one to a bit of this register causes thecorresponding bit in the I2C control register to be cleared. Writing a zero has no effect.
Table 397. I2C Control Set Register (I2C[0/1/2]CONCLR - addresses 0xE001 C018,
0xE005 C018, 0xE008 0018) bit description
Bit Symbol

Description

Reset
Value

1:0 -

Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

2

AAC

Assert acknowledge Clear bit.

3

SIC

I2C interrupt Clear bit.

0

4

-

Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

5

STAC

START flag Clear bit.

0

6

I2ENC

I2C interface Disable bit.

0

7

-

Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

AAC is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the
I2CONSET register. Writing 0 has no effect.
SIC is the I2C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the I2CONSET
register. Writing 0 has no effect.
STAC is the Start flag Clear bit. Writing a 1 to this bit clears the STA bit in the I2CONSET
register. Writing 0 has no effect.
I2ENC is the I2C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the
I2CONSET register. Writing 0 has no effect.

7.3 I2C Status Register (I2C[0/1/2]STAT - 0xE001 C004, 0xE005 C004,
0xE008 0004)
Each I2C Status register reflects the condition of the corresponding I2C interface. The I2C
Status register is Read-Only.
Table 398. I2C Status Register (I2C[0/1/2]STAT - addresses 0xE001 C004, 0xE005 C004,
0xE008 0004) bit description
Bit Symbol

Description

Reset Value

2:0 -These bits are unused and are always 0.

0

7:3 Status

These bits give the actual status information about the I2C interface. 0x1F

The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I2C states. When any of these states entered, the SI bit will
be set. For a complete list of status codes, refer to tables from Table 19–408 to
Table 19–411.
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7.4 I2C Data Register (I2C[0/1/2]DAT - 0xE001 C008, 0xE005 C008,
0xE008 0008)
This register contains the data to be transmitted or the data just received. The CPU canread and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT isalways shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after abyte has been received, the first bit of received data is located at the MSB of I2DAT.
Table 399. I2C Data Register ( I2C[0/1/2]DAT - addresses 0xE001 C008, 0xE005 C008,
0xE008 0008) bit description
Bit Symbol

Description

Reset Value

7:0 Data

This register holds data values that have been received, or are to 0
be transmitted.

7.5 I2C Slave Address Register (I2C[0/1/2]ADR - 0xE001 C00C,
0xE005 C00C, 0xE008 000C)
These registers are readable and writable, and is only used when an I2C interface is set toslave mode. In master mode, this register has no effect. The LSB of I2ADR is the generalcall bit. When this bit is set, the general call address (0x00) is recognized.
Table 400. I2C Slave Address register (I2C[0/1/2]ADR - addresses 0xE001 C00C,
0xE005 C00C, 0xE008 000C) bit description
Bit Symbol

Description

Reset Value0

General Call enable bit.

0

The I2C device address for slave mode.

0x00

GC

7:1 Address

7.6 I2C SCL High Duty Cycle Register (I2C[0/1/2]SCLH - 0xE001 C010,
0xE0015 C010, 0xE008 0010)
Table 401. I2C SCL High Duty Cycle register (I2C[0/1/2]SCLH - addresses 0xE001 C010,
0xE005 C010, 0xE008 0010) bit description
Bit

SymbolDescription

Reset Value

15:0

SCLH

Count for SCL HIGH time period selection.

0x0004

7.7 I2C SCL Low Duty Cycle Register (I2C[0/1/2]SCLL - 0xE001 C014,
0xE0015 C014, 0xE008 0014)
Table 402. I2C SCL Low Duty Cycle register (I2C[0/1/2]SCLL - addresses 0xE001 C014,
0xE005 C014, 0xE008 0014) bit description
Bit

SymbolDescription

Reset Value

15:0

SCLL

Count for SCL LOW time period selection.

0x0004

7.8 Selecting the appropriate I2C data rate and duty cycle
Software must set values for the registers I2SCLH and I2SCLL to select the appropriate
data rate and duty cycle. I2SCLH defines the number of PCLK cycles for the SCL hightime, I2SCLL defines the number of PCLK cycles for the SCL low time. The frequency isdetermined by the following formula (fPCLK being the frequency of PCLK):

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(15)
f PCLKI 2 C bitfrequency = -------------------------------------------------------I2CSCLH + I2CSCLL

The values for I2SCLL and I2SCLH should not necessarily be the same. Software can set
different duty cycles on SCL by setting these two registers. For example, the I2C bus
specification defines the SCL low time and high time at different values for a 400 kHz I2C
rate. The value of the register must ensure that the data rate is in the I2C data rate rangeof 0 through 400 kHz. Each register value must be greater than or equal to 4.
Table 19–403 gives some examples of I2C bus rates based on PCLK frequency and
I2SCLL and I2SCLH values.
Table 403. Example I2C Clock Rates
I2C Bit Frequency (kHz) at PCLK (MHz)I2SCLL +I2SCLH

1

8

125

10

100

25

40

5

10

200

400

16

20

40

60

50

20

100

200

320

400

100

10

50

100

160

200

400

160

6.25

31.25

62.5

100

125

250

375

200

5

25

50

80

100

200

300

400

2.5

12.5

25

40

50

100

150

800

1.25

6.25

12.5

20

25

50

75

8. Details of I2C operating modes
The four operating modes are:• Master Transmitter• Master Receiver• Slave Receiver• Slave Transmitter
Data transfers in each mode of operation are shown in Figures 88 to 92. Table 19–404
lists abbreviations used in these figures when describing the I2C operating modes.
Table 404. Abbreviations used to describe an I2C operation
Abbreviation

Explanation

S

Start Condition

SLA

7 bit slave address

R

Read bit (high level at SDA)W

Write bit (low level at SDA)A

Acknowledge bit (low level at SDA)

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Table 404. Abbreviations used to describe an I2C operation
Abbreviation

ExplanationA

Not acknowledge bit (high level at SDA)

Data

8 bit data byte

P

Stop condition

In Figures 88 to 92, circles are used to indicate when the serial interrupt flag is set. The
numbers in the circles show the status code held in the I2STAT register. At these points, aservice routine must be executed to continue or complete the serial transfer. These
service routines are not critical since the serial transfer is suspended until the serialinterrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in I2STAT is used to branch tothe appropriate service routine. For each status code, the required software action anddetails of the following serial transfer are given in tables from Table 19–408 to
Table 19–412.

8.1 Master Transmitter mode
In the master transmitter mode, a number of data bytes are transmitted to a slave receiver(see Figure 19–88). Before the master transmitter mode can be entered, I2CON must be
initialized as follows:
Table 405. I2CONSET used to initialize Master Transmitter mode
Bit

7

6

5

4

3

2

1

0

Symbol

-

I2EN

STA

STO

SI

AA

-

-

Value

-

1

0

0

0

x

-

-

The I2C rate must also be configured in the I2SCLL and I2SCLH registers. I2EN must be
set to logic 1 to enable the I2C block. If the AA bit is reset, the I2C block will not
acknowledge its own slave address or the general call address in the event of anotherdevice becoming master of the bus. In other words, if AA is reset, the I2C interface cannot
enter a slave mode. STA, STO, and SI must be reset.
The master transmitter mode may now be entered by setting the STA bit. The I2C logic will
now test the I2C bus and generate a start condition as soon as the bus becomes free.
When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status
code in the status register (I2STAT) will be 0x08. This status code is used by the interrupt
service routine to enter the appropriate state service routine that loads I2DAT with theslave address and the data direction bit (SLA+W). The SI bit in I2CON must then be reset
before the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and anumber of status codes in I2STAT are possible. There are 0x18, 0x20, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = logic 1).
The appropriate action to be taken for each of these status codes is detailed inTable 19–408. After a repeated start condition (state 0x10). The I2C block may switch tothe master receiver mode by loading I2DAT with SLA+R).

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8.2 Master Receiver mode
In the master receiver mode, a number of data bytes are received from a slave transmitter(see Figure 19–89). The transfer is initialized as in the master transmitter mode. When thestart condition has been transmitted, the interrupt service routine must load I2DAT with the
7 bit slave address and the data direction bit (SLA+R). The SI bit in I2CON must then becleared before the serial transfer can continue.
When the slave address and the data direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and anumber of status codes in I2STAT are possible. These are 0x40, 0x48, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = 1). The
appropriate action to be taken for each of these status codes is detailed in Table 19–409.
After a repeated start condition (state 0x10), the I2C block may switch to the mastertransmitter mode by loading I2DAT with SLA+W.

8.3 Slave Receiver mode
In the slave receiver mode, a number of data bytes are received from a master transmitter(see Figure 19–90). To initiate the slave receiver mode, I2ADR and I2CON must be
loaded as follows:
Table 406. I2C0ADR and I2C1ADR usage in Slave Receiver mode
Bit

7

6

5

Symbol4

32

1

own slave 7 bit address

0GC

The upper 7 bits are the address to which the I2C block will respond when addressed by amaster. If the LSB (GC) is set, the I2C block will respond to the general call address(0x00); otherwise it ignores the general call address.
Table 407. I2C0CONSET and I2C1CONSET used to initialize Slave Receiver mode
Bit

7

6

5

4

3

2

1

0

Symbol

-

I2EN

STA

STO

SI

AA

-

-

Value

-

1

0

0

0

1

-

-

The I2C bus rate settings do not affect the I2C block in the slave mode. I2EN must be set
to logic 1 to enable the I2C block. The AA bit must be set to enable the I2C block to
acknowledge its own slave address or the general call address. STA, STO, and SI must
be reset.
When I2ADR and I2CON have been initialized, the I2C block waits until it is addressed byits own slave address followed by the data direction bit which must be “0” (W) for the I2C
block to operate in the slave receiver mode. After its own slave address and the W bit
have been received, the serial interrupt flag (SI) is set and a valid status code can be readfrom I2STAT. This status code is used to vector to a state service routine. The appropriate
action to be taken for each of these status codes is detailed in Table 104. The slave
receiver mode may also be entered if arbitration is lost while the I2C block is in the mastermode (see status 0x68 and 0x78).

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If the AA bit is reset during a transfer, the I2C block will return a not acknowledge (logic 1)
to SDA after the next received data byte. While AA is reset, the I2C block does not
respond to its own slave address or a general call address. However, the I2C bus is stillmonitored and address recognition may be resumed at any time by setting AA. Thismeans that the AA bit may be used to temporarily isolate the I2C block from the I2C bus.

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Chapter 19: LPC2300 I2C0, I2C1, I2C2

MT
successfultransmission
to a Slave
Receiver

S

SLA

W

A

DATA

A

18H

08H

P

28H

next transfer
started with a
Repeated Start
condition

S

SLA

W

10H

Not
Acknowledge
received after
the Slaveaddress

A

P

R

20H

Not
Acknowledge
received after a
Data byteAP

to Master
receive
mode,
entry
= MR

30H

arbitration lostin Slaveaddress orData byte

A OR Aother Master
continues

A OR A

38H

arbitration lostandaddressed as
Slave

A

other Master
continues

38H

other Master
continues

68H 78H B0H

to corresponding
states in Slave mode

from Master to Slavefrom Slave to Master

DATA

n

any number of data bytes and their associated Acknowledge bits

this number (contained in I2STA) corresponds to a defined state of the
I2C busFig 88. Format and States in the Master Transmitter mode

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MR

successfultransmission toa Slavetransmitter

S

08H

SLA

R

A

DATA

40H

A

DATA

50H

A

P

58H

next transfer
started with a
Repeated Start
condition

S

SLA

R

10H
Not Acknowledge
received after the
Slave address

A

P

W

48H
to Mastertransmit
mode, entry= MT

arbitration lost in
Slave address or
Acknowledge bitother Master
continues

A OR AA

38H

arbitration lostand addressedas SlaveAother Master
continues

38H

other Master
continues

68H 78H B0H

to corresponding
states in Slavemode

from Master to Slavefrom Slave to Master

DATA

n

A

any number of data bytes and their associatedAcknowledge bits
this number (contained in I2STA) corresponds to a defined state of
the I2C bus

Fig 89. Format and States in the Master Receiver mode

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reception of the own
Slave address and one
or more Data bytes all
are acknowledged

S

SLA

R

A

DATA

60H

A

DATA

80H

last data byte
received is Not
acknowledged

A

P OR S

80H

A0H

A

P OR S

88H
arbitration lost as
Master and addressedas SlaveA

68H

reception of theGeneral Call address
and one or more Data
bytes

GENERAL CALL

A

DATA

70h

A

DATA

90h

last data byte is Not
acknowledged

A

P OR S

90h

A0H

A

P OR S98h
arbitration lost as
Master and addressedas Slave by General
Call

A

78h

from Master to Slavefrom Slave to Master

DATA

n

A

any number of data bytes and their associated Acknowledge bits

this number (contained in I2STA) corresponds to a defined state of the 2IC
bus

Fig 90. Format and States in the Slave Receiver mode

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reception of the own
Slave address andone or more Data
bytes all areacknowledged

S

SLA

R

A

A8H

arbitration lost as
Master andaddressed as Slave

DATA

A

B8H

DATA

A

P OR S

C0H

A

B0H

last data byte
transmitted. Switchedto Not Addressed
Slave (AA bit in
I2CON = “0”)A

ALL ONES

P OR S

C8H

from Master to Slavefrom Slave to Master

DATA

n

A

any number of data bytes and their associatedAcknowledge bits

this number (contained in I2STA) corresponds to a defined state of
the I2C bus

Fig 91. Format and States in the Slave Transmitter mode

8.4 Slave Transmitter mode
In the slave transmitter mode, a number of data bytes are transmitted to a master receiver(see Figure 19–91). Data transfer is initialized as in the slave receiver mode. When I2ADR
and I2CON have been initialized, the I2C block waits until it is addressed by its own slave
address followed by the data direction bit which must be “1” (R) for the I2C block tooperate in the slave transmitter mode. After its own slave address and the R bit have been
received, the serial interrupt flag (SI) is set and a valid status code can be read fromI2STAT. This status code is used to vector to a state service routine, and the appropriate
action to be taken for each of these status codes is detailed in Table 19–411. The slavetransmitter mode may also be entered if arbitration is lost while the I2C block is in themaster mode (see state 0xB0).
If the AA bit is reset during a transfer, the I2C block will transmit the last byte of the transfer
and enter state 0xC0 or 0xC8. The I2C block is switched to the not addressed slave mode
and will ignore the master receiver if it continues the transfer. Thus the master receiverreceives all 1s as serial data. While AA is reset, the I2C block does not respond to its own
slave address or a general call address. However, the I2C bus is still monitored, andaddress recognition may be resumed at any time by setting AA. This means that the AA
bit may be used to temporarily isolate the I2C block from the I2C bus.
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Table 408. Master Transmitter mode
StatusStatus of the I2C bus Application software responseCodeand hardware
To/From I2DATTo I2CON(I2CSTAT)STA STO SI

AA

0x08

A START condition
Load SLA+W
has been transmitted.

X

0x10

A repeated START
condition has beentransmitted.

Load SLA+W or

X

0

0

X

As above.

Load SLA+R

X

0

0

X

SLA+W will be transmitted; the I2C block
will be switched to MST/REC mode.

SLA+W has beentransmitted; ACK has
been received.

Load data byte or

0

0

0

X

Data byte will be transmitted; ACK bit will
be received.

No I2DAT action
or

1

0

0

X

Repeated START will be transmitted.

No I2DAT action
or

0

1

0

X

STOP condition will be transmitted; STO
flag will be reset.

No I2DAT action

1

1

0

X

STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.

SLA+W has been
Load data byte ortransmitted; NOT ACK
has been received.
No I2DAT action
or

0

0

0

X

Data byte will be transmitted; ACK bit will
be received.

1

0

0

X

Repeated START will be transmitted.

No I2DAT action
or

0

1

0

X

STOP condition will be transmitted; STO
flag will be reset.

No I2DAT action

1

1

0

X

STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.

Data byte in I2DATLoad data byte or
has been transmitted;
ACK has been
No I2DAT action
received.
or

0

0

0

X

Data byte will be transmitted; ACK bit will
be received.

1

0

0

X

Repeated START will be transmitted.

No I2DAT action
or

0

1

0

X

STOP condition will be transmitted; STO
flag will be reset.

No I2DAT action

1

1

0

X

STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.

Data byte in I2DATLoad data byte or
has been transmitted;
NOT ACK has been
No I2DAT action
received.
or

0

0

0

X

Data byte will be transmitted; ACK bit will
be received.

1

0

0

X

Repeated START will be transmitted.

No I2DAT action
or

0

1

0

X

STOP condition will be transmitted; STO
flag will be reset.

No I2DAT action

1

1

0

X

STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.

No I2DAT action
or

0

0

0

X

I2C bus will be released; not addressedslave will be entered.

No I2DAT action

1

0

0

X

A START condition will be transmitted
when the bus becomes free.

0x18

0x20

0x28

0x30

0x38

Arbitration lost in
SLA+R/W or Data
bytes.

X

0

0

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Chapter 19: LPC2300 I2C0, I2C1, I2C2

Table 409. Master Receiver mode
StatusStatus of the I2C bus Application software responseCodeand hardware
To/From I2DATTo I2CON(I2CSTAT)STA STO SI

AA

0x08

A START condition
Load SLA+R
has been transmitted.

X

0x10

A repeated START
condition has beentransmitted.

0x38

0x40

0x48

0x50

0x58

X

0

0

SLA+R will be transmitted; ACK bit will bereceived.

Load SLA+R or

X

0

0

X

As above.

Load SLA+W

X

0

0

X

SLA+W will be transmitted; the I2C block
will be switched to MST/TRX mode.

Arbitration lost in NOT No I2DAT action
ACK bit.
or

0

0

0

X

I2C bus will be released; the I2C block willenter a slave mode.

No I2DAT action

1

0

0

X

A START condition will be transmitted
when the bus becomes free.

No I2DAT action
or

0

0

0

0

Data byte will be received; NOT ACK bit
will be returned.

No I2DAT action

0

0

0

1

Data byte will be received; ACK bit will be
returned.

SLA+R has been
No I2DAT action
transmitted; NOT ACK or
has been received.
No I2DAT action
or

1

0

0

X

Repeated START condition will betransmitted.

0

1

0

X

STOP condition will be transmitted; STO
flag will be reset.

No I2DAT action

1

1

0

X

STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.

Data byte has been
received; ACK has
been returned.

Read data byte or 0

0

0

0

Data byte will be received; NOT ACK bit
will be returned.

Read data byte

0

0

0

1

Data byte will be received; ACK bit will be
returned.

Data byte has been
received; NOT ACK
has been returned.

Read data byte or 1

0

0

X

Repeated START condition will betransmitted.

Read data byte or 0

1

0

X

STOP condition will be transmitted; STO
flag will be reset.

Read data byte

1

0

X

STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.

SLA+R has beentransmitted; ACK has
been received.

1

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Table 410. Slave Receiver Mode
StatusStatus of the I2C bus Application software responseCodeand hardware
To/From I2DATTo I2CON(I2CSTAT)STA STO SI

AA

0x60

0x68

0x70

0x78

0x80

0x88

0x90

Own SLA+W has
been received; ACK
has been returned.

No I2DAT action
or

X

0

0

0

Data byte will be received and NOT ACK
will be returned.

No I2DAT action

X

0

0

1

Data byte will be received and ACK will
be returned.

Arbitration lost in
SLA+R/W as master;Own SLA+W has
been received, ACK
returned.

No I2DAT action
or

X

0

0

0

Data byte will be received and NOT ACK
will be returned.

No I2DAT action

X

0

0

1

Data byte will be received and ACK will
be returned.

General call address(0x00) has been
received; ACK has
been returned.

No I2DAT action
or

X

0

0

0

Data byte will be received and NOT ACK
will be returned.

No I2DAT action

X

0

0

1

Data byte will be received and ACK will
be returned.

Arbitration lost in
SLA+R/W as master;
General call address
has been received,
ACK has beenreturned.

No I2DAT action
or

X

0

0

0

Data byte will be received and NOT ACK
will be returned.

No I2DAT action

X

0

0

1

Data byte will be received and ACK will
be returned.

Previously addressedwith own SLV
address; DATA has
been received; ACK
has been returned.

Read data byte or X

0

0

0

Data byte will be received and NOT ACK
will be returned.

Read data byte

X

0

0

1

Data byte will be received and ACK will
be returned.

Previously addressedwith own SLA; DATA
byte has been
received; NOT ACK
has been returned.

Read data byte or 0

0

0

0

Switched to not addressed SLV mode; norecognition of own SLA or General calladdress.

Read data byte or 0

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General calladdress will be recognized if
I2ADR[0] = logic 1.

Read data byte or 1

0

0

0

Switched to not addressed SLV mode; norecognition of own SLA or General calladdress. A START condition will betransmitted when the bus becomes free.

Read data byte

1

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General calladdress will be recognized if
I2ADR[0] = logic 1. A START condition
will be transmitted when the bus becomes
free.

Read data byte or X

0

0

0

Data byte will be received and NOT ACK
will be returned.

Read data byte

0

0

1

Data byte will be received and ACK will
be returned.

Previously addressedwith General Call;
DATA byte has been
received; ACK has
been returned.

X

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Table 410. Slave Receiver Mode
StatusStatus of the I2C bus Application software responseCodeand hardware
To/From I2DATTo I2CON(I2CSTAT)STA STO SI

AA

0x98

0xA0

Previously addressedwith General Call;
DATA byte has been
received; NOT ACK
has been returned.

A STOP condition or
repeated START
condition has been
received while still
addressed as
SLV/REC or
SLV/TRX.

Read data byte or 0

0

0

0

Switched to not addressed SLV mode; norecognition of own SLA or General calladdress.

Read data byte or 0

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General calladdress will be recognized if
I2ADR[0] = logic 1.

Read data byte or 1

0

0

0

Switched to not addressed SLV mode; norecognition of own SLA or General calladdress. A START condition will betransmitted when the bus becomes free.

Read data byte

1

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General calladdress will be recognized if
I2ADR[0] = logic 1. A START condition
will be transmitted when the bus becomesfree.

No STDAT action
or

0

0

0

0

Switched to not addressed SLV mode; norecognition of own SLA or General calladdress.

No STDAT action
or

0

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General calladdress will be recognized if
I2ADR[0] = logic 1.

No STDAT action
or

1

0

0

0

Switched to not addressed SLV mode; norecognition of own SLA or General calladdress. A START condition will betransmitted when the bus becomes free.

No STDAT action

1

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General calladdress will be recognized if
I2ADR[0] = logic 1. A START condition
will be transmitted when the bus becomes
free.

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Table 411. Tad_105: Slave Transmitter mode
StatusStatus of the I2C bus Application software responseCodeand hardware
To/From I2DATTo I2CON(I2CSTAT)STA STO SI

AA

0xA8

0xB0

0xB8

0xC0

0xC8

Own SLA+R has been Load data byte orreceived; ACK has
been returned.
Load data byte

X

0

0

0

Last data byte will be transmitted and
ACK bit will be received.

X

0

0

1

Data byte will be transmitted; ACK will bereceived.

X

0

0

0

Last data byte will be transmitted and
ACK bit will be received.

X

0

0

1

Data byte will be transmitted; ACK bit will
be received.

X

0

0

0

Last data byte will be transmitted and
ACK bit will be received.

X

0

0

1

Data byte will be transmitted; ACK bit will
be received.

Data byte in I2DATNo I2DAT action
has been transmitted; or
NOT ACK has been
received.
No I2DAT action
or

0

0

0

0

Switched to not addressed SLV mode; norecognition of own SLA or General calladdress.

0

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General calladdress will be recognized if
I2ADR[0] = logic 1.

No I2DAT action
or

1

0

0

0

Switched to not addressed SLV mode; norecognition of own SLA or General calladdress. A START condition will betransmitted when the bus becomes free.

No I2DAT action

1

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General calladdress will be recognized if
I2ADR[0] = logic 1. A START condition
will be transmitted when the bus becomesfree.

No I2DAT action
or

0

0

0

0

Switched to not addressed SLV mode; norecognition of own SLA or General calladdress.

No I2DAT action
or

0

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General calladdress will be recognized if
I2ADR[0] = logic 1.

No I2DAT action
or

1

0

0

0

Switched to not addressed SLV mode; norecognition of own SLA or General calladdress. A START condition will betransmitted when the bus becomes free.

No I2DAT action

1

0

0

1

Switched to not addressed SLV mode;
Own SLA will be recognized; General calladdress will be recognized if
I2ADR.0 = logic 1. A START condition willbe transmitted when the bus becomes
free.

Arbitration lost in
Load data byte or
SLA+R/W as master;Own SLA+R has been Load data byte
received, ACK has
been returned.
Data byte in I2DATLoad data byte or
has been transmitted;
ACK has been
Load data byte
received.

Last data byte in
I2DAT has beentransmitted (AA = 0);
ACK has been
received.

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8.5 Miscellaneous states
There are two I2STAT codes that do not correspond to a defined I2C hardware state (seeTable 19–412). These are discussed below.
19.8.5.1

I2STAT = 0xF8
This status code indicates that no relevant information is available because the serialinterrupt flag, SI, is not yet set. This occurs between other states and when the I2C blockis not involved in a serial transfer.

19.8.5.2

I2STAT = 0x00
This status code indicates that a bus error has occurred during an I2C serial transfer. A
bus error is caused when a START or STOP condition occurs at an illegal position in theformat frame. Examples of such illegal positions are during the serial transfer of an
address byte, a data byte, or an acknowledge bit. A bus error may also be caused when
external interference disturbs the internal I2C block signals. When a bus error occurs, SI isset. To recover from a bus error, the STO flag must be set and SI must be cleared. This
causes the I2C block to enter the “not addressed” slave mode (a defined state) and toclear the STO flag (no other bits in I2CON are affected). The SDA and SCL lines are
released (a STOP condition is not transmitted).

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Table 412. Miscellaneous states
StatusStatus of the I2C bus Application software responseCodeand hardware
To/From I2DATTo I2CON(I2CSTAT)STA STO SI
0xF8

No relevant state
information available;
SI = 0.

No I2DAT action

0x00

Bus error during MST No I2DAT action
or selected slavemodes, due to an
illegal START or
STOP condition. State
0x00 can also occur
when interference
causes the I2C blockto enter an undefinedstate.

Next action taken by I2C hardware
AA

No I2CON action

0

1

0

X

Wait or proceed current transfer.

Only the internal hardware is affected in
the MST or addressed SLV modes. In allcases, the bus is released and the I2C
block is switched to the not addressed
SLV mode. STO is reset.

8.6 Some special cases
The I2C hardware has facilities to handle the following special cases that may occur
during a serial transfer:

8.7 Simultaneous repeated START conditions from two masters
A repeated START condition may be generated in the master transmitter or masterreceiver modes. A special case occurs if another master simultaneously generates arepeated START condition (see Figure 19–92). Until this occurs, arbitration is not lost byeither master since they were both transmitting the same data.
If the I2C hardware detects a repeated START condition on the I2C bus before generatinga repeated START condition itself, it will release the bus, and no interrupt request is
generated. If another master frees the bus by generating a STOP condition, the I2C block
will transmit a normal START condition (state 0x08), and a retry of the total serial datatransfer can commence.

8.8 Data transfer after loss of arbitration
Arbitration may be lost in the master transmitter and master receiver modes (seeFigure 19–86). Loss of arbitration is indicated by the following states in I2STAT; 0x38,
0x68, 0x78, and 0xB0 (see Figure 19–88 and Figure 19–89).
If the STA flag in I2CON is set by the routines which service these states, then, if the bus
is free again, a START condition (state 0x08) is transmitted without intervention by theCPU, and a retry of the total serial transfer can commence.

8.9 Forced access to the I2C bus
In some applications, it may be possible for an uncontrolled source to cause a bus
hang-up. In such situations, the problem may be caused by interference, temporaryinterruption of the bus or a temporary short-circuit between SDA and SCL.

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If an uncontrolled source generates a superfluous START or masks a STOP condition,then the I2C bus stays busy indefinitely. If the STA flag is set and bus access is not
obtained within a reasonable amount of time, then a forced access to the I2C bus ispossible. This is achieved by setting the STO flag while the STA flag is still set. No STOP
condition is transmitted. The I2C hardware behaves as if a STOP condition was received
and is able to transmit a START condition. The STO flag is cleared by hardware (seeFigure 34).

8.10 I2C Bus obstructed by a Low level on SCL or SDA
An I2C bus hang-up occurs if SDA or SCL is pulled LOW by an uncontrolled source. If the
SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer ispossible, and the I2C hardware cannot resolve this type of problem. When this occurs, theproblem must be resolved by the device that is pulling the SCL bus line LOW.
If the SDA line is obstructed by another device on the bus (e.g., a slave device out of bit
synchronization), the problem can be solved by transmitting additional clock pulses on the
SCL line (see Figure 19–94). The I2C hardware transmits additional clock pulses when
the STA flag is set, but no START condition can be generated because the SDA line ispulled LOW while the I2C bus is considered free. The I2C hardware attempts to generate a
START condition after every two additional clock pulses on the SCL line. When the SDA
line is eventually released, a normal START condition is transmitted, state 0x08 isentered, and the serial transfer continues.
If a forced bus access occurs or a repeated START condition is transmitted while SDA isobstructed (pulled LOW), the I2C hardware performs the same action as described above.
In each case, state 0x08 is entered after a successful START condition is transmitted andnormal serial transfer continues. Note that the CPU is not involved in solving these bus
hang-up problems.

8.11 Bus error
A bus error occurs when a START or STOP condition is present at an illegal position in theformat frame. Examples of illegal positions are during the serial transfer of an addressbyte, a data bit, or an acknowledge bit.
The I2C hardware only reacts to a bus error when it is involved in a serial transfer either as
a master or an addressed slave. When a bus error is detected, the I2C block immediately
switches to the not addressed slave mode, releases the SDA and SCL lines, sets theinterrupt flag, and loads the status register with 0x00. This status code may be used tovector to a state service routine which either attempts the aborted serial transfer again or
simply recovers from the error condition as shown in Table 19–412.

S
08H

SLA

W

A
18H

DATA

A

S

OTHER MASTERCONTINUES

28H

other Master sends
repeated START earlier

P

S

SLA

08H

retry

Fig 92. Simultaneous repeated START conditions from 2 masters
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Chapter 19: LPC2300 I2C0, I2C1, I2C2time limit
STA flag

STO flag
SDA line

SCL line
start
condition

Fig 93. Forced access to a busy I2C bus

STA flag(2)(1)

SDA line(3)(1)

SCL line
start
condition(1) Unsuccessful attempt to send a start condition.
(2) SDA line is released.
(3) Successful attempt to send a start condition. State 08H is entered.

Fig 94. Recovering from a bus obstruction caused by a low level on SDA

8.12 I2C State service routines
This section provides examples of operations that must be performed by various I2C stateservice routines. This includes:• Initialization of the I2C block after a Reset.
• I2C Interrupt Service.
• The 26 state service routines providing support for all four I2C operating modes.
8.12.1 Initialization
In the initialization example, the I2C block is enabled for both master and slave modes.
For each mode, a buffer is used for transmission and reception. The initialization routine
performs the following functions:• I2ADR is loaded with the part’s own slave address and the general call bit (GC).
• The I2C interrupt enable and interrupt priority bits are set.
• The slave mode is enabled by simultaneously setting the I2EN and AA bits in I2CON
and the serial clock frequency (for master modes) is defined by loading CR0 and CR1
in I2CON. The master routines must be started in the main program.
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Chapter 19: LPC2300 I2C0, I2C1, I2C2The I2C hardware now begins checking the I2C bus for its own slave address and generalcall. If the general call or the own slave address is detected, an interrupt is requested and
I2STAT is loaded with the appropriate state information.

8.12.2 I2C interrupt service
When the I2C interrupt is entered, I2STAT contains a status code which identifies one of
the 26 state services to be executed.

8.12.3 The state service routines
Each state routine is part of the I2C interrupt routine and handles one of the 26 states.

8.12.4 Adapting state services to an application
The state service examples show the typical actions that must be performed in responseto the 26 I2C state codes. If one or more of the four I2C operating modes are not used, theassociated state services can be omitted, as long as care is taken that the those states
can never occur.
In an application, it may be desirable to implement some kind of timeout during I2C
operations, in order to trap an inoperative bus or a lost service routine.

9. Software example
9.1 Initialization routine
Example to initialize I2C Interface as a Slave and/or Master.
1. Load I2ADR with own Slave Address, enable general call recognition if needed.
2. Enable I2C interrupt.
3. Write 0x44 to I2CONSET to set the I2EN and AA bits, enabling Slave functions. For
Master only functions, write 0x40 to I2CONSET.

9.2 Start master transmit function
Begin a Master Transmit operation by setting up the buffer, pointer, and data count, theninitiating a Start.
1. Initialize Master data counter.
2. Set up the Slave Address to which data will be transmitted, and add the Write bit.
3. Write 0x20 to I2CONSET to set the STA bit.
4. Set up data to be transmitted in Master Transmit buffer.
5. Initialize the Master data counter to match the length of the message being sent.
6. Exit

9.3 Start master receive function
Begin a Master Receive operation by setting up the buffer, pointer, and data count, theninitiating a Start.
1. Initialize Master data counter.
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2. Set up the Slave Address to which data will be transmitted, and add the Read bit.
3. Write 0x20 to I2CONSET to set the STA bit.
4. Set up the Master Receive buffer.
5. Initialize the Master data counter to match the length of the message to be received.
6. Exit

9.4 I2C interrupt routine
Determine the I2C state and which state routine will be used to handle it.
1. Read the I2C status from I2STA.
2. Use the status value to branch to one of 26 possible state routines.

9.5 Non mode specific states
9.5.1 State : 0x00
Bus Error. Enter not addressed Slave mode and release bus.
1. Write 0x14 to I2CONSET to set the STO and AA bits.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Exit

9.6 Master states
State 08 and State 10 are for both Master Transmit and Master Receive modes. The R/W
bit decides whether the next state is within Master Transmit mode or Master Receivemode.

9.6.1 State : 0x08
A Start condition has been transmitted. The Slave Address + R/W bit will be transmitted,
an ACK bit will be received.
1. Write Slave Address with R/W bit to I2DAT.
2. Write 0x04 to I2CONSET to set the AA bit.
3. Write 0x08 to I2CONCLR to clear the SI flag.
4. Set up Master Transmit mode data buffer.
5. Set up Master Receive mode data buffer.
6. Initialize Master data counter.
7. Exit9.6.2 State : 0x10
A repeated Start condition has been transmitted. The Slave Address + R/W bit will betransmitted, an ACK bit will be received.
1. Write Slave Address with R/W bit to I2DAT.
2. Write 0x04 to I2CONSET to set the AA bit.
3. Write 0x08 to I2CONCLR to clear the SI flag.
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4. Set up Master Transmit mode data buffer.
5. Set up Master Receive mode data buffer.
6. Initialize Master data counter.
7. Exit

9.7 Master Transmitter states
9.7.1 State : 0x18
Previous state was State 8 or State 10, Slave Address + Write has been transmitted, ACK
has been received. The first data byte will be transmitted, an ACK bit will be received.
1. Load I2DAT with first data byte from Master Transmit buffer.
2. Write 0x04 to I2CONSET to set the AA bit.
3. Write 0x08 to I2CONCLR to clear the SI flag.
4. Increment Master Transmit buffer pointer.
5. Exit9.7.2 State : 0x20
Slave Address + Write has been transmitted, NOT ACK has been received. A Stopcondition will be transmitted.
1. Write 0x14 to I2CONSET to set the STO and AA bits.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Exit9.7.3 State : 0x28
Data has been transmitted, ACK has been received. If the transmitted data was the last
data byte then transmit a Stop condition, otherwise transmit the next data byte.
1. Decrement the Master data counter, skip to step 5 if not the last data byte.
2. Write 0x14 to I2CONSET to set the STO and AA bits.
3. Write 0x08 to I2CONCLR to clear the SI flag.
4. Exit
5. Load I2DAT with next data byte from Master Transmit buffer.
6. Write 0x04 to I2CONSET to set the AA bit.
7. Write 0x08 to I2CONCLR to clear the SI flag.
8. Increment Master Transmit buffer pointer9. Exit9.7.4 State : 0x30
Data has been transmitted, NOT ACK received. A Stop condition will be transmitted.
1. Write 0x14 to I2CONSET to set the STO and AA bits.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Exit
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9.7.5 State : 0x38
Arbitration has been lost during Slave Address + Write or data. The bus has beenreleased and not addressed Slave mode is entered. A new Start condition will betransmitted when the bus is free again.
1. Write 0x24 to I2CONSET to set the STA and AA bits.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Exit

9.8 Master Receive states
9.8.1 State : 0x40
Previous state was State 08 or State 10. Slave Address + Read has been transmitted,
ACK has been received. Data will bereceived and ACK returned.
1. Write 0x04 to I2CONSET to set the AA bit.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Exit9.8.2 State : 0x48
Slave Address + Read has been transmitted, NOT ACK has been received. A Stopcondition will be transmitted.
1. Write 0x14 to I2CONSET to set the STO and AA bits.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Exit9.8.3 State : 0x50
Data has been received, ACK has been returned. Data will be read from I2DAT. Additional
data will be received. If this is the last data byte then NOT ACK will be returned, otherwise
ACK will be returned.
1. Read data byte from I2DAT into Master Receive buffer.
2. Decrement the Master data counter, skip to step 5 if not the last data byte.
3. Write 0x0C to I2CONCLR to clear the SI flag and the AA bit.
4. Exit
5. Write 0x04 to I2CONSET to set the AA bit.
6. Write 0x08 to I2CONCLR to clear the SI flag.
7. Increment Master Receive buffer pointer8. Exit9.8.4 State : 0x58
Data has been received, NOT ACK has been returned. Data will be read from I2DAT. A
Stop condition will be transmitted.
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1. Read data byte from I2DAT into Master Receive buffer.
2. Write 0x14 to I2CONSET to set the STO and AA bits.
3. Write 0x08 to I2CONCLR to clear the SI flag.
4. Exit

9.9 Slave Receiver states
9.9.1 State : 0x60
Own Slave Address + Write has been received, ACK has been returned. Data will bereceived and ACK returned.
1. Write 0x04 to I2CONSET to set the AA bit.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Set up Slave Receive mode data buffer.
4. Initialize Slave data counter.
5. Exit9.9.2 State : 0x68
Arbitration has been lost in Slave Address and R/W bit as bus Master. Own Slave Address+ Write has been received, ACK has been returned. Data will be received and ACK will be
returned. STA is set to restart Master mode after the bus is free again.
1. Write 0x24 to I2CONSET to set the STA and AA bits.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Set up Slave Receive mode data buffer.
4. Initialize Slave data counter.
5. Exit.

9.9.3 State : 0x70
General call has been received, ACK has been returned. Data will be received and ACK
returned.
1. Write 0x04 to I2CONSET to set the AA bit.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Set up Slave Receive mode data buffer.
4. Initialize Slave data counter.
5. Exit9.9.4 State : 0x78
Arbitration has been lost in Slave Address + R/W bit as bus Master. General call has been
received and ACK has been returned. Data will be received and ACK returned. STA is set
to restart Master mode after the bus is free again.
1. Write 0x24 to I2CONSET to set the STA and AA bits.
2. Write 0x08 to I2CONCLR to clear the SI flag.
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Chapter 19: LPC2300 I2C0, I2C1, I2C2

3. Set up Slave Receive mode data buffer.
4. Initialize Slave data counter.
5. Exit9.9.5 State : 0x80
Previously addressed with own Slave Address. Data has been received and ACK has
been returned. Additional data will be read.
1. Read data byte from I2DAT into the Slave Receive buffer.
2. Decrement the Slave data counter, skip to step 5 if not the last data byte.
3. Write 0x0C to I2CONCLR to clear the SI flag and the AA bit.
4. Exit.
5. Write 0x04 to I2CONSET to set the AA bit.
6. Write 0x08 to I2CONCLR to clear the SI flag.
7. Increment Slave Receive buffer pointer.
8. Exit9.9.6 State : 0x88
Previously addressed with own Slave Address . Data has been received and NOT ACK
has been returned. Received data will not be saved. Not addressed Slave mode isentered.
1. Write 0x04 to I2CONSET to set the AA bit.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Exit9.9.7 State : 0x90
Previously addressed with general call. Data has been received, ACK has been returned.
Received data will be saved. Only the first data byte will be received with ACK. Additional
data will be received with NOT ACK.
1. Read data byte from I2DAT into the Slave Receive buffer.
2. Write 0x0C to I2CONCLR to clear the SI flag and the AA bit.
3. Exit9.9.8 State : 0x98
Previously addressed with general call. Data has been received, NOT ACK has beenreturned. Received data will not be saved. Not addressed Slave mode is entered.
1. Write 0x04 to I2CONSET to set the AA bit.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Exit9.9.9 State : 0xA0
A Stop condition or repeated Start has been received, while still addressed as a Slave.
Data will not be saved. Not addressed Slave mode is entered.
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Chapter 19: LPC2300 I2C0, I2C1, I2C2

1. Write 0x04 to I2CONSET to set the AA bit.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Exit9.10 Slave Transmitter States
9.10.1 State : 0xA8
Own Slave Address + Read has been received, ACK has been returned. Data will betransmitted, ACK bit will be received.
1. Load I2DAT from Slave Transmit buffer with first data byte.
2. Write 0x04 to I2CONSET to set the AA bit.
3. Write 0x08 to I2CONCLR to clear the SI flag.
4. Set up Slave Transmit mode data buffer.
5. Increment Slave Transmit buffer pointer.
6. Exit9.10.2 State : 0xB0
Arbitration lost in Slave Address and R/W bit as bus Master. Own Slave Address + Readhas been received, ACK has been returned. Data will be transmitted, ACK bit will bereceived. STA is set to restart Master mode after the bus is free again.
1. Load I2DAT from Slave Transmit buffer with first data byte.
2. Write 0x24 to I2CONSET to set the STA and AA bits.
3. Write 0x08 to I2CONCLR to clear the SI flag.
4. Set up Slave Transmit mode data buffer.
5. Increment Slave Transmit buffer pointer.
6. Exit9.10.3 State : 0xB8
Data has been transmitted, ACK has been received. Data will be transmitted, ACK bit will
be received.
1. Load I2DAT from Slave Transmit buffer with data byte.
2. Write 0x04 to I2CONSET to set the AA bit.
3. Write 0x08 to I2CONCLR to clear the SI flag.
4. Increment Slave Transmit buffer pointer.
5. Exit9.10.4 State : 0xC0
Data has been transmitted, NOT ACK has been received. Not addressed Slave mode isentered.
1. Write 0x04 to I2CONSET to set the AA bit.
2. Write 0x08 to I2CONCLR to clear the SI flag.
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Chapter 19: LPC2300 I2C0, I2C1, I2C2

3. Exit9.10.5 State : 0xC8
The last data byte has been transmitted, ACK has been received. Not addressed Slave
mode is entered.
1. Write 0x04 to I2CONSET to set the AA bit.
2. Write 0x08 to I2CONCLR to clear the SI flag.
3. Exit

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UM10211
Chapter 20: I2S
Rev. 01 — 6 July 2007

User manual

1. Features
The I2S bus provides a standard communication interface for digital audio applications.
The I2S bus specification defines a 3-wire serial bus, having 1 data, 1 clock, and one word
select signal. The basic I2S connection has one master, which is always the master, andone slave. The I2S interface on the LPC2300 provides a separate transmit and receive
channel, each of which can operate as either a master or a slave.

• The I2S input can operate in both master and slave mode.
• The I2S output can operate in both master and slave mode, independent of the I2S
input.

• Capable of handling 8, 16, and 32 bit word sizes.
• Mono and stereo audio data supported.
• The sampling frequency can range (in practice) from 16 - 48 kHz. (16, 22.05, 32, 44.1,
48 kHz).

• Word Select period in master mode is configurable (separately for I2S input and I2S
output).

• Two 8 byte FIFO data buffers are provided, one for transmit and one for receive.
• Generates interrupt requests when buffer levels cross a programmable boundary.
• Two DMA requests, controlled by programmable buffer levels. These are connectedto the General Purpose DMA block.

• Controls include reset, stop and mute options separately for I2S input and I2S output.

2. Description
The I2S performs serial data out via the transmit channel and serial data in via the receive
channel. These support the NXP Inter IC Audio format for 8, 16 and 32 bits audio data
both for stereo and mono modes. Configuration, data access and control is performed bya APB register set. Data streams are buffered by FIFOs with a depth of 8 bytes.
The I2S receive and transmit stage can operate independently in either slave or mastermode. Within the I2S module the difference between these modes lies in the word select(WS) signal which determines the timing of data transmissions. Data words start on thenext falling edge of the transmitting clock after a WS change. In stereo mode when WS is
low left data is transmitted and right data when WS is high. In mono mode the same datais transmitted twice, once when WS is low and again when WS is high.

• In master mode (ws_sel = 0), word select is generated internally with a 9 bit counter.
The half period count value of this counter can be set in the control register.

• In slave mode (ws_sel = 1) word select is input from the relevant bus pin.
• When an I2S bus is active, the word select, receive clock and transmit clock signals
are sent continuously by the bus master, while data is sent continuously by thetransmitter.
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Chapter 20: LPC2300 I2S• Disabling the I2S can be done with the stop or mute control bits separately for thetransmit and receive.

• The stop bit will disable accesses by the transmit channel or the receive channel to
the FIFOs and will place the transmit channel in mute mode.

• The mute control bit will place the transmit channel in mute mode. In mute mode, thetransmit channel FIFO operates normally, but the output is discarded and replaced byzeroes. This bit does not affect the receive channel, data reception can occur
normally.

3. Pin descriptions
Table 413. Pin descriptions
Pin Name

Type

Description

I2SRX_CLK Input/Output Receive Clock. A clock signal used to synchronize the transfer of dataon the receive channel. It is driven by the master and received by theslave. Corresponds to the signal SCK in the I2S bus specification.
I2SRX_WS

Input/Output Receive Word Select. Selects the channel from which data is to bereceived. It is driven by the master and received by the slave.
Corresponds to the signal WS in the I2S bus specification.
WS = 0 indicates that data is being received by channel 1 (leftchannel).
WS = 1 indicates that data is being received by channel 2 (rightchannel).

I2SRX_SD
A

Input/Output Receive Data. Serial data, received MSB first. It is driven by thetransmitter and read by the receiver. Corresponds to the signal SD in
the I2S bus specification.

I2STX_CLK Input/Output Transmit Clock. A clock signal used to synchronize the transfer ofdata on the transmit channel. It is driven by the master and received
by the slave. Corresponds to the signal SCK in the I2S bus
specification.
I2STX_WS

Input/Output Transmit Word Select. Selects the channel to which data is being
sent. It is driven by the master and received by the slave.
Corresponds to the signal WS in the I2S bus specification.
WS = 0 indicates that data is being sent to channel 1 (left channel).
WS = 1 indicates that data is being sent to channel 2 (right channel).

I2STX_SDA Input/Output Transmit Data. Serial data, sent MSB first. It is driven by thetransmitter and read by the receiver. Corresponds to the signal SD in
the I2S bus specification.

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Chapter 20: LPC2300 I2S

SCK: serial clock
TRANSMITTER(MASTER)

SCK: serial clock
RECEIVER(SLAVE)

WS: word select
SD: serial data

TRANSMITTER(SLAVE)

WS: word select
SD: serial data

RECEIVER(MASTER)CONTROLLER(MASTER)SCK
TRANSMITTER(SLAVE)WS
SD

RECEIVER(SLAVE)

SCK

WS

MSB

SD
word n-1
right channel

LSBword nleft channel

MSB
word n+1
right channel

Fig 95. Simple I2S configurations and bus timing

4. Register description
Table 20–414 shows the registers associated with the I2S interface and a summary of
their functions. Following the table are details for each register.
Table 414. I2S register map
Name

Description

Access Reset
Address
Value[1]I2SDAO

Digital Audio Output Register. Contains control
bits for the I2S transmit channel.

R/W

0xE008 8000

I2SDAI

Digital Audio Input Register. Contains control
bits for the I2S receive channel.

R/W

0xE008 8004

I2STXFIFO

Transmit FIFO. Access register for the 8 × 32 bit WO
transmitter FIFO.

0xE008 8008

I2SRXFIFO

Receive FIFO. Access register for the 8 × 32 bit RO
receiver FIFO.

0xE008 800C

I2SSTATE

Status Feedback Register. Contains status
information about the I2S interface.

RO

0xE008 8010

I2SDMA1DMA Configuration Register 1. Contains control R/W
information for DMA request 1.

0xE008 8014

I2SDMA2DMA Configuration Register 2. Contains control R/W
information for DMA request 2.

0xE008 8018

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Chapter 20: LPC2300 I2STable 414. I2S register map
Name

Description

I2SIRQInterrupt Request Control Register. Contains bits R/Wthat control how the I2S interrupt request is
generated.

0xE008 801CI2STXRATE

Transmit bit rate divider. This register
R/W
determines the I2S transmit bit rate by specifying
the value to divide pclk by in order to produce
the transmit bit clock.

0xE008 8020

I2SRXRATE Receive bit rate divider. This register determines R/Wthe I2S receive bit rate by specifying the value todivide pclk by in order to produce the receive bit
clock.

0xE008 8024

[1]

Access Reset
Address
Value[1]Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

4.1 Digital Audio Output Register (I2SDAO - 0xE008 8000)
The I2SDAO register controls the operation of the I2S transmit channel. The function ofbits in DAO are shown in Table 20–415.
Table 415: Digital Audio Output register (I2SDAO - address 0xE008 8000) bit description
Bit

Symbol

1:0

wordwidth

Value Description

Reset
Value

Selects the number of bytes in data as follows:00

8 bit data01

16 bit data

10

Reserved, do not use this setting

11

32 bit data

01

2

mono

When one, data is of monaural format. When zero, thedata is in stereo format.

0

3

stop

Disables accesses on FIFOs, places the transmit
channel in mute mode.

0

4

reset

Asynchronously reset the transmit channel and FIFO.

0

5

ws_selWhen 0 master mode, when 1 slave mode.

1

14:6

ws_halfperiod

Word select half period minus one, i.e. WS 64clk period-> ws_halfperiod = 31.

0x1F

15

mute

When true, the transmit channel sends only zeroes.

1

4.2 Digital Audio Input Register (I2SDAI - 0xE008 8004)
The I2SDAI register controls the operation of the I2S receive channel. The function of bits
in DAI are shown in Table 20–416.

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Chapter 20: LPC2300 I2STable 416: Digital Audio Input register (I2SDAI - address 0xE008 8004) bit description
Bit

Symbol

1:0

wordwidth

Value Description

Reset
Value

Selects the number of bytes in data as follows:00

8 bit data01

16 bit data

10

Reserved, do not use this setting

11

32 bit data

01

2

mono

When one, data is of monaural format. When zero, thedata is in stereo format.

0

3

stop

Disables accesses on FIFOs, places the transmit
channel in mute mode.

0

4

reset

Asynchronously reset the transmit channel and FIFO.

0

5

ws_selWhen 0 master mode, when 1 slave mode.

1

14:6

ws_halfperiod

Word select half period minus one, i.e. WS 64clk period-> ws_halfperiod = 31.

0x1F

15

UnusedUnused.

1

4.3 Transmit FIFO Register (I2STXFIFO - 0xE008 8008)
The I2STXFIFO register provides access to the transmit FIFO. The function of bits in
I2STXFIFO are shown in Table 20–417.
Table 417: Transmit FIFO register (I2STXFIFO - address 0xE008 8008) bit description
Bit

SymbolDescription

Reset Value

31:0

I2STXFIFO

8 × 32 bits transmit FIFO.

Level = 0

4.4 Receive FIFO Register (I2SRXFIFO - 0xE008 800C)
The I2SRXFIFO register provides access to the receive FIFO. The function of bits in
I2SRXFIFO are shown in Table 20–418.
Table 418: Receive FIFO register (I2RXFIFO - address 0xE008 800C) bit description
Bit

Symbol31:0 I2SRXFIFO

Description

Reset Value

8 × 32 bits transmit FIFO.

level = 0

4.5 Status Feedback Register (I2SSTATE - 0xE008 8010)
The I2SSTATE register provides status information about the I2S interface. The meaningof bits in I2SSTATE are shown in Table 20–419.
Table 419: Status Feedback register (I2SSTATE - address 0xE008 8010) bit description
Bit

SymbolDescription0

irq

This bit reflects the presence of Receive Interrupt or Transmit Interrupt. 0

1

dmareq1

This bit reflects the presence of Receive or Transmit DMA Request 1.

0

2

dmareq2

This bit reflects the presence of Receive or Transmit DMA Request 2.

0

7:3

UnusedUnused.

0UM10211_1

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Chapter 20: LPC2300 I2STable 419: Status Feedback register (I2SSTATE - address 0xE008 8010) bit description
Bit

SymbolDescription

Reset
Value

15:8

rx_level

Reflects the current level of the Receive FIFO.

0

23:16 tx_level

Reflects the current level of the Transmit FIFO.

0

31:24 -

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

4.6 DMA Configuration Register 1 (I2SDMA1 - 0xE008 8014)
The I2SDMA1 register controls the operation of DMA request 1. The function of bits in
I2SDMA1 are shown in Table 20–420. Refer to the General Purpose DMA Controller
chapter for details of DMA operation.
Table 420: DMA Configuration register 1 (I2SDMA1 - address 0xE008 8014) bit description
Bit

SymbolDescription

Reset
Value

0

rx_dma1_enable

When 1, enables DMA1 for I2S receive.

01

tx_dma1_enable

When 1, enables DMA1 for I2S transmit.

0

7:2

UnusedUnused.

0

15:8

rx_depth_dma1

Set the FIFO level that triggers a receive DMA request on
DMA1.

0

23:16

tx_depth_dma1

Set the FIFO level that triggers a transmit DMA request on
DMA1.

0

31:24

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

4.7 DMA Configuration Register 2 (I2SDMA2 - 0xE008 8018)
The I2SDMA2 register controls the operation of DMA request 2. The function of bits in
I2SDMA2 are shown in Table 20–415.
Table 421: DMA Configuration register 2 (I2SDMA2 - address 0xE008 8018) bit description
Bit

SymbolDescription

Reset
Value

0

rx_dma2_enable

When 1, enables DMA1 for I2S receive.

01

tx_dma2_enable

When 1, enables DMA1 for I2S transmit.

0

7:2

UnusedUnused.

0

15:8

rx_depth_dma2

Set the FIFO level that triggers a receive DMA request
on DMA2.

0

23:16

tx_depth_dma2

Set the FIFO level that triggers a transmit DMA request
on DMA2.

0

31:24

-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

4.8 Interrupt Request Control Register (I2SIRQ - 0xE008 801C)
The I2SIRQ register controls the operation of the I2S interrupt request. The function of bits
in I2SIRQ are shown in Table 20–415.
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Chapter 20: LPC2300 I2STable 422: Interrupt Request Control register (I2SIRQ - address 0xE008 801C) bit description
Bit

SymbolDescription

Reset
Value

0

rx_Irq_enable

When 1, enables I2S receive interrupt.

01

tx_Irq_enable

When 1, enables I2S transmit interrupt.

0

7:2

UnusedUnused.

0

15:8

rx_depth_Irq

Set the FIFO level on which to create an irq request.

0

23:16

tx_depth_Irq

Set the FIFO level on which to create an irq request.

0

31:24

-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

4.9 Transmit Clock Rate Register (I2STXRATE - 0xE008 8020)
The bit rate for the I2S transmitter is determined by the value of the I2STXRATE register.
The value depends on the audio sample rate desired, and the data size and format(stereo/mono) used. For example, a 48 kHz sample rate for 16 bit stereo data requires a
bit rate of 48,000×16×2 = 1.536 MHz.
Table 423: Transmit Clock Rate register (I2TXRATE - address 0xE008 8020) bit description
Bit

SymbolDescription

Reset
Value

9:0

tx_rateI2S transmit bit rate. This value plus one is used to divide PCLK by 0
to produce the transmit bit clock. Ten bits of divide supports a wide
range of I2S rates over a wide range of pclk rates.

15:10

UnusedUnused.

04.10 Receive Clock Rate Register (I2SRXRATE - 0xE008 8024)
The bit rate for the I2S receiver is determined by the value of the I2SRXRATE register.
The value depends on the audio sample rate, as well as the data size and format used.
The calculation is the same as for I2STXRATE.
Table 424: Receive Clock Rate register (I2SRXRATE - address 0xE008 8024) bit description
Bit

SymbolDescription

Reset
Value

9:0

rx_rateI2S receive bit rate. This value plus one is used to divide PCLK by
to produce the receive bit clock. Ten bits of divide supports a wide
range of I2S rates over a wide range of pclk rates.

0

15:10

UnusedUnused.

0

5. I2S transmit and receive interfaces
The I2S interface can transmit and receive 8, 16 or 32 bits stereo or mono audio
information. Some details of I2S implementation are:• When the FIFO is empty, the transmit channel will repeat transmitting the same data
until new data is written to the FIFO.

• When mute is true, the data value 0 is transmitted.
• When mono is false, two successive data words are respectively left and right data.
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Chapter 20: LPC2300 I2S• Data word length is determined by the wordwidth value in the configuration register.
There is a separate wordwidth value for the receive channel and the transmit channel.
– 0: word is considered to contain four 8 bits data words.
– 1: word is considered to contain two 16 bits data words.
– 3: word is considered to contain one 32 bits data word.

• When the transmit FIFO contains insufficient data the transmit channel will repeat
transmitting the last data until new data is available. This can occur when the
microprocessor or the DMA at some time is unable to provide new data fast enough.
Because of this delay in new data there is a need to fill the gap, which isaccomplished by continuing to transmit the last sample. The data is not muted as thiswould produce an noticeable and undesirable effect in the sound.

• The transmit channel and the receive channel only handle 32 bit aligned words, data
chunks must be clipped or extended to a multiple of 32 bits.
When switching between data width or modes the I2S must be reset via the reset bit in thecontrol register in order to ensure correct synchronization. It is advisable to set the stop bit
also until sufficient data has been written in the transmit FIFO. Note that when stopped
data output is muted.
All data accesses to FIFO's are 32 bits. Figure 20–96 shows the possible data sequences.
A data sample in the FIFO consists of:• 1×32 bits in 8 or 16 bit stereo modes.
• 1×32 bits in mono modes.
• 2×32 bits, first left data, second right data, in 32 bit stereo modes.
Data is read from the transmit FIFO after the falling edge of WS, it will be transferred tothe transmit clock domain after the rising edge of WS. On the next falling edge of WS theleft data will be loaded in the shift register and transmitted and on the following rising edgeof WS the right data is loaded and transmitted.
The receive channel will start receiving data after a change of WS. When word selectbecomes low it expects this data to be left data, when WS is high received data is
expected to be right data. Reception will stop when the bit counter has reached the limit
set by wordwidth. On the next change of WS the received data will be stored in theappropriate hold register. When complete data is available it will be written into the receive
FIFO.

6. FIFO controller
Handling of data for transmission and reception is performed via the FIFO controller which
can generate two DMA requests and an interrupt request. The controller consists of a setof comparators which compare FIFO levels with depth settings contained in registers. The
current status of the level comparators can be seen in the APB status register.

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Chapter 20: LPC2300 I2STable 425. Conditions for FIFO level comparison
Level Comparison

Condition

dmareq_tx_1

tx_depth_dma1 >= tx_level

dmareq_rx_1

rx_depth_dma1 <= rx_level

dmareq_tx_2

tx_depth_dma2 >= tx_level

dmareq_rx_2

rx_depth_dma2 <= rx_level

irq_txtx_depth_irq >= tx_level

irq_rxrx_depth_irq <= rx_level

System signaling occurs when a level detection is true and enabled.
Table 426. DMA and interrupt request generation
System Signaling

Conditionirq(irq_rx & rx_irq_enable) | (irq_tx & tx_irq_enable

dmareq[0](dmareq_tx_1 & tx_dma1_enable ) | (dmareq_rx_1 &rx_dma1_enable )dmareq[1]( dmareq_tx_2 & tx_dma2_enable ) | (dmareq_rx_2 &rx_dma2_enable )Table 427. Status feedback in the I2SSTATE register
Status Feedback

Statusirq

irq_rx | irq_tx

dmareq1(dmareq_tx_1 | dmareq_rx_1)

dmareq2(dmareq_rx_2 | dmareq_tx_2)

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Chapter 20: LPC2300 I2SMono 8-bit data mode
7

N+3

0

7

0

7

N+2

0

7

0

7

0

15

0

15

N+1

0

7

0

7

N

0

Stereo 8-bit data mode
7

LEFT + 1

RIGHT + 1

LEFT

RIGHT

0

Mono 16-bit data mode
15

N+1

N

0

Stereo 16-bit data mode
15

LEFT

RIGHT

0

Mono 32-bit data mode
31

N

0

Stereo 32-bit data mode
31

31

LEFT

RIGHT

0

0

N

N+1

Fig 96. FIFO contents for various I2S modes

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UM10211
Chapter 21: Timer 0, 1, 2, 3
Rev. 01 — 6 July 2007

User manual

1. Features
Remark: The four Timer/Counters are identical except for the peripheral base address. A
minimum of two Capture inputs and two Match outputs are pinned out for all four timers,
with a choice of several pins for each. Timer 1 brings out a third Match output, while
Timers 2 and 3 bring out all four Match outputs.

• A 32 bit Timer/Counter with a programmable 32 bit Prescaler.
• Counter or Timer operation• Up to four 32 bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.

• Four 32 bit match registers that allow:– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following
capabilities:– Set low on match.
– Set high on match.
– Toggle on match.
– Do nothing on match.

2. Applications• Interval Timer for counting internal events.
• Pulse Width Demodulator via Capture inputs.
• Free running timer.

3. Description
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally-supplied clock, and can optionally generate interrupts or perform other actionsat specified timer values, based on four match registers. It also includes four capture
inputs to trap the timer value when an input signal transitions, optionally generating aninterrupt.

4. Pin description
Table 21–428 gives a brief summary of each of the Timer/Counter related pins.

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Chapter 21: LPC2300 Timer

Table 428. Timer/Counter pin description
Pin

Type

CAP0[1:0] Input
CAP1[1:0]
CAP2[1:0]
CAP3[1:0]

Description
Capture Signals- A transition on a capture pin can be configured to load oneof the Capture Registers with the value in the Timer Counter and optionallygenerate an interrupt. Capture functionality can be selected from a numberof pins. When more than one pin is selected for a Capture input on a single
TIMER0/1 channel, the pin with the lowest Port number is used
Timer/Counter block can select a capture signal as a clock source instead of
the PCLK derived clock. For more details see Section 21–5.3.

MAT0[1:0] Output
MAT1[1:0]
MAT2[3:0]
MAT3[1:0]

External Match Output - When a match register (MR3:0) equals the timer
counter (TC) this output can either toggle, go low, go high, or do nothing. The
External Match Register (EMR) controls the functionality of this output.
Match Output functionality can be selected on a number of pins in parallel.

4.1 Multiple CAP and MAT pins
Software can select multiple pins for most of the CAP or MAT functions in the Pin Selectregisters, which are described in Section 9–4. When more than one pin is selected for a
MAT output, all such pins are driven identically. When more than one pin is selected for a
CAP input, the pin with the lowest Port number is used.

5. Register description
Each Timer/Counter contains the registers shown in Table 21–429 ("Reset Value" refers to
the data stored in used bits only; it does not include reserved bits content). More detailed
descriptions follow.
Table 429. TIMER/COUNTER0-3 register map
Generic Description
Name

Access Reset
TIMERn Register/
Value[1] Name & Address

IRInterrupt Register. The IR can be written to R/Wclear interrupts. The IR can be read to
identify which of eight possible interrupt
sources are pending.

0

T0IR - 0xE000 4000
T1IR - 0xE000 8000
T2IR - 0xE007 0000
T3IR - 0xE007 4000

TCR

Timer Control Register. The TCR is used
to control the Timer Counter functions.
The Timer Counter can be disabled or
reset through the TCR.

R/W

0

T0TCR - 0xE000 4004
T1TCR - 0xE000 8004
T2TCR - 0xE007 0004
T3TCR - 0xE007 4004

TC

Timer Counter. The 32 bit TC is
incremented every PR+1 cycles of PCLK.
The TC is controlled through the TCR.

R/W

0

T0TC - 0xE000 4008
T1TC - 0xE000 8008
T2TC - 0xE007 0008
T3TC - 0xE007 4008

PR

Prescale Register. The Prescale Counter(below) is equal to this value, the next
clock increments the TC and clears the
PC.

R/W

0

T0PR - 0xE000 400C
T1PR - 0xE000 800C
T2PR - 0xE007 000C
T3PR - 0xE007 400C

PC

Prescale Counter. The 32 bit PC is acounter which is incremented to the value
stored in PR. When the value in PR isreached, the TC is incremented and the
PC is cleared. The PC is observable andcontrollable through the bus interface.

R/W

0

T0PC - 0xE000 4010
T1PC - 0xE000 8010
T2PC - 0xE007 0010
T3PC - 0xE007 4010

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Chapter 21: LPC2300 Timer

Table 429. TIMER/COUNTER0-3 register map
Generic Description
Name

Access Reset
TIMERn Register/
Value[1] Name & Address

MCR

Match Control Register. The MCR is used R/W
to control if an interrupt is generated and if
the TC is reset when a Match occurs.

0

T0MCR - 0xE000 4014
T1MCR - 0xE000 8014
T2MCR - 0xE007 0014
T3MCR - 0xE007 4014

MR0

Match Register 0. MR0 can be enabled
R/W
through the MCR to reset the TC, stop
both the TC and PC, and/or generate aninterrupt every time MR0 matches the TC.

0

T0MR0 - 0xE000 4018
T1MR0 - 0xE000 8018
T2MR0 - 0xE007 0018
T3MR0 - 0xE007 4018

MR1

Match Register 1. See MR0 description.

R/W

0

T0MR1 - 0xE000 401C
T1MR1 - 0xE000 801C
T2MR1 - 0xE007 001C
T3MR1 - 0xE007 401C

MR2

Match Register 2. See MR0 description.

R/W

0

T0MR2 - 0xE000 4020
T1MR2 - 0xE000 8020
T2MR2 - 0xE007 0020
T3MR2 - 0xE007 4020

MR3

Match Register 3. See MR0 description.

R/W

0

T0MR3 - 0xE000 4024
T1MR3 - 0xE000 8024
T2MR3 - 0xE007 0024
T3MR3 - 0xE007 4024

CCR

Capture Control Register. The CCR
R/Wcontrols which edges of the capture inputs
are used to load the Capture Registers
and whether or not an interrupt isgenerated when a capture takes place.

0

T0CCR - 0xE000 4028
T1CCR - 0xE000 8028
T2CCR - 0xE007 0028
T3CCR - 0xE007 4028

CR0

Capture Register 0. CR0 is loaded with the RO
value of TC when there is an event on the
CAPn.0(CAP0.0 or CAP1.0 respectively)
input.

0

T0CR0 - 0xE000 402C
T1CR0 - 0xE000 802C
T2CR0 - 0xE007 002C
T3CR0 - 0xE007 402C

CR1

Capture Register 1. See CR0 description.

RO0

T0CR1 - 0xE000 4030
T1CR1 - 0xE000 8030
T2CR1 - 0xE007 0030
T3CR1 - 0xE007 4030

CR2

Capture Register 2. See CR0 description.

RO

0

T0CR2 - 0xE000 4034
T1CR2 - 0xE000 8034
T2CR2 - 0xE007 0034
T3CR2 - 0xE007 4034

CR3

Capture Register 3. See CR0 description.

RO

0

T0CR3 - 0xE000 4038
T1CR3 - 0xE000 8038
T2CR3 - 0xE007 0038
T3CR3 - 0xE007 4038

EMR

External Match Register. The EMR
R/W
controls the external match pins MATn.0-3(MAT0.0-3 and MAT1.0-3 respectively).

0

T0EMR - 0xE000 403C
T1EMR - 0xE000 803C
T2EMR - 0xE007 003C
T3EMR - 0xE007 403C

CTCR

Count Control Register. The CTCR selects R/W
between Timer and Counter mode, and inCounter mode selects the signal andedge(s) for counting.

0

T0CTCR - 0xE000 4070
T1CTCR - 0xE000 8070
T2CTCR - 0xE007 0070
T3CTCR - 0xE007 4070

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

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Chapter 21: LPC2300 Timer

5.1 Interrupt Register (T[0/1/2/3]IR - 0xE000 4000, 0xE000 8000,
0xE007 0000, 0xE007 4000)
The Interrupt Register consists of four bits for the match interrupts and four bits for thecapture interrupts. If an interrupt is generated then the corresponding bit in the IR will behigh. Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset
the interrupt. Writing a zero has no effect.
Table 430: Interrupt Register (T[0/1/2/3]IR - addresses 0xE000 4000, 0xE000 8000,
0xE007 0000, 0xE007 4000) bit description
Bit Symbol

Description

Reset
Value

0

MR0 Interrupt Interrupt flag for match channel 0.

0

1

MR1 Interrupt Interrupt flag for match channel 1.

02

MR2 Interrupt Interrupt flag for match channel 2.

03

MR3 Interrupt Interrupt flag for match channel 3.

0

4

CR0 Interrupt

Interrupt flag for capture channel 0 event.

05

CR1 Interrupt

Interrupt flag for capture channel 1 event.

0

6

CR2 Interrupt

Interrupt flag for capture channel 2 event.

0

7

CR3 Interrupt

Interrupt flag for capture channel 3 event.

0

5.2 Timer Control Register (T[0/1/2/3]CR - 0xE000 4004, 0xE000 8004,
0xE007 0004, 0xE007 4004)
The Timer Control Register (TCR) is used to control the operation of the Timer/Counter.
Table 431: Timer Control Register (TCR, TIMERn: TnTCR - addresses 0xE000 4004,
0xE000 8004, 0xE007 0004, 0xE007 4004) bit description
Bit

SymbolDescription

Reset Value

0

Counter Enable When one, the Timer Counter and Prescale Counter are 0
enabled for counting. When zero, the counters are
disabled.

1

Counter Reset

When one, the Timer Counter and the Prescale Counter 0
are synchronously reset on the next positive edge of
PCLK. The counters remain reset until TCR[1] isreturned to zero.

7:2-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

5.3 Count Control Register (T[0/1/2/3]CTCR - 0xE000 4070, 0xE000 8070,
0xE007 0070, 0xE007 4070)
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:

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Chapter 21: LPC2300 Timerrising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event corresponds to the one selected by bits 1:0 in the CTCR
register, the Timer Counter register will be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one quarter of
the PCLK clock. Consequently, duration of the high/low levels on the same CAP input inthis case can not be shorter than 1/(2 PCLK).
Table 432: Count Control Register (T[0/1/2/3]CTCR - addresses 0xE000 4070, 0xE000 8070,
0xE007 0070, 0xE007 4070) bit description
Bit

Symbol1:0Counter/
Timer
Mode

Value

Description

Reset
Value

This field selects which rising PCLK edges can increment
Timer’s Prescale Counter (PC), or clear PC and increment
Timer Counter (TC).

00

Timer Mode: the TC is incremented when the Prescale
Counter matches the Prescale Register.

3:2

Count
Input
Select00

Timer Mode: every rising PCLK edge

01

Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.

10

Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.

11

Counter Mode: TC is incremented on both edges on the CAP
input selected by bits 3:2.
When bits 1:0 in this register are not 00, these bits selectwhich CAP pin is sampled for clocking:

00

CAPn.0 for TIMERn

01

CAPn.1 for TIMERn

10

CAPn.2 for TIMERn

11

CAPn.3 for TIMERn

00

Note: If Counter mode is selected for a particular CAPn input
in the TnCTCR, the 3 bits for that input in the Capture
Control Register (TnCCR) must be programmed as 000.
However, capture and/or interrupt can be selected for theother 3 CAPn inputs in the same timer.
7:4

-

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

5.4 Timer Counter registers (T0TC - T3TC, 0xE000 4008, 0xE000 8008,
0xE007 0008, 0xE007 4008)
The 32-bit Timer Counter register is incremented when the prescale counter reaches its
terminal count. Unless it is reset before reaching its upper limit, the Timer Counter willcount up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000.
This event does not cause an interrupt, but a match register can be used to detect anoverflow if needed.

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Chapter 21: LPC2300 Timer

5.5 Prescale register (T0PR - T3PR, 0xE000 400C, 0xE000 800C,
0xE007 000C, 0xE007 400C)
The 32-bit Prescale register specifies the maximum value for the Prescale Counter.

5.6 Prescale Counter register (T0PC - T3PC, 0xE000 4010, 0xE000 8010,
0xE007 0010, 0xE007 4010)
The 32-bit Prescale Counter controls division of PCLK by some constant value before it isapplied to the Timer Counter. This allows control of the relationship of the resolution of thetimer versus the maximum time before the timer overflows. The Prescale Counter isincremented on every PCLK. When it reaches the value stored in the Prescale register,
the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK.
This causes the Timer Counter to increment on every PCLK when PR = 0, every 2 PCLKs
when PR = 1, etc.

5.7 Match Registers (MR0 - MR3)
The Match register values are continuously compared to the Timer Counter value. Whenthe two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions arecontrolled by the settings in the MCR register.

5.8 Match Control Register (T[0/1/2/3]MCR - 0xE000 4014, 0xE000 8014,
0xE007 0014, 0xE007 4014)
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shownin Table 21–433.
Table 433: Match Control Register (T[0/1/2/3]MCR - addresses 0xE000 4014, 0xE000 8014,
0xE007 0014, 0xE007 4014) bit description
Bit

Symbol Value Description

Reset
Value

0

MR0I

0

1

Interrupt on MR0: an interrupt is generated when MR0 matches
the value in the TC.

0This interrupt is disabled
Reset on MR0: the TC will be reset if MR0 matches it.

1

MR0R

1
0

Feature disabled.

2

MR0S

1

Stop on MR0: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR0 matches the TC.

0

Feature disabled.

1

Interrupt on MR1: an interrupt is generated when MR1 matches
the value in the TC.

0This interrupt is disabled
Reset on MR1: the TC will be reset if MR1 matches it.

3

MR1I

4

MR1R

1
0

Feature disabled.

5

MR1S

1

Stop on MR1: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR1 matches the TC.

0

Feature disabled.

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0

0

0
0

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Chapter 21: LPC2300 Timer

Table 433: Match Control Register (T[0/1/2/3]MCR - addresses 0xE000 4014, 0xE000 8014,
0xE007 0014, 0xE007 4014) bit description
Bit

Symbol Value Description

Reset
Value

6

MR2I

0

1

Interrupt on MR2: an interrupt is generated when MR2 matches
the value in the TC.

0This interrupt is disabled
Reset on MR2: the TC will be reset if MR2 matches it.

7

MR2R

1
0

Feature disabled.

8

MR2S

1

Stop on MR2: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR2 matches the TC.

0

Feature disabled.

1

Interrupt on MR3: an interrupt is generated when MR3 matches
the value in the TC.

0This interrupt is disabled
Reset on MR3: the TC will be reset if MR3 matches it.

9

MR3I

10

MR3R

1
0

Feature disabled.

11

MR3S

1

Stop on MR3: the TC and PC will be stopped and TCR[0] will be
set to 0 if MR3 matches the TC.

0

Feature disabled.

15:12 -

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

0
0

0

0
0

NA

5.9 Capture Registers (CR0 - CR3)
Each Capture register is associated with a device pin and may be loaded with the TimerCounter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.

5.10 Capture Control Register (T[0/1/2/3]CCR - 0xE000 4028, 0xE000 8028,
0xE007 0028, 0xE007 4028)
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when the capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at thesame time is a valid configuration, resulting in a capture event for both edges. In thedescription below, "n" represents the Timer number, 0 or 1.
Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits forthat input in this register should be programmed as 000, but capture and/or interrupt canbe selected for the other 3 CAP inputs.

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Chapter 21: LPC2300 Timer

Table 434: Capture Control Register (T[0/1/2/3]CCR - addresses 0xE000 4028, 0xE000 8020,
0xE007 0028, 0xE007 4028) bit description
Bit

SymbolValue Description

0

CAP0RE 1

1

CAP0FE 1

0

2

3

1

Interrupt on CAPn.0 event: a CR0 load due to a CAPn.0 event
will generate an interrupt.

0This feature is disabled.

CAP0I

CAP1RE 1

CAP1FE 15

CAP1IInterrupt on CAPn.1 event: a CR1 load due to a CAPn.1 event
will generate an interrupt.

0This feature is disabled.

Interrupt on CAPn.2 event: a CR2 load due to a CAPn.2 event
will generate an interrupt.

CAP3RE 1

0

0
CAP3FE 1

15:12 -

Capture on CAPn.2 falling edge: a sequence of 1 then 0 on
CAPn.2 will cause CR2 to be loaded with the contents of TC.

1

9

0

0

0

0

0

0

This feature is disabled.
Capture on CAPn.3 rising edge: a sequence of 0 then 1 on
CAPn.3 will cause CR3 to be loaded with the contents of TC.

0

This feature is disabled.
Capture on CAPn.3 falling edge: a sequence of 1 then 0 on
CAPn.3 will cause CR3 to be loaded with the contents of TC

0This feature is disabled.

1

Interrupt on CAPn.3 event: a CR3 load due to a CAPn.3 event
will generate an interrupt.

0This feature is disabled.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

UM10211_1

User manual0This feature is disabled.

This feature is disabled.

CAP2I

CAP3I

Capture on CAPn.2 rising edge: A sequence of 0 then 1 on
CAPn.2 will cause CR2 to be loaded with the contents of TC.

0
8

11

Capture on CAPn.1 falling edge: a sequence of 1 then 0 on
CAPn.1 will cause CR1 to be loaded with the contents of TC.

1

CAP2FE 1

0This feature is disabled.

This feature is disabled.

010

Capture on CAPn.1 rising edge: a sequence of 0 then 1 on
CAPn.1 will cause CR1 to be loaded with the contents of TC.

0

CAP2RE 1

0This feature is disabled.
Capture on CAPn.0 falling edge: a sequence of 1 then 0 on
CAPn.0 will cause CR0 to be loaded with the contents of TC.
This feature is disabled.

4

7

Capture on CAPn.0 rising edge: a sequence of 0 then 1 on
CAPn.0 will cause CR0 to be loaded with the contents of TC.

0

0

6

Reset
Value

0

0

NA

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Chapter 21: LPC2300 Timer

5.11 External Match Register (T[0/1/2/3]EMR - 0xE000 403C, 0xE000 803C,
0xE007 003C, 0xE007 403C)
The External Match Register provides both control and status of the external match pins.
In the descriptions below, “n” represents the Timer number, 0 or 1, and “m” represent a
Match number, 0 through 3.
Table 435: External Match Register (T[0/1/2/3]EMR - addresses 0xE000 403C, 0xE000 803C,
0xE007 003C, 0xE007 403C) bit description
Bit

Symbol Description

Reset
Value

0

EM0

External Match 0. When a match occurs between the TC and MR0, this 0
bit can either toggle, go low, go high, or do nothing, depending on bits 5:4of this register. This bit can be driven onto a MATn.0 pin, in apositive-logic manner (0 = low, 1 = high).

1

EM1

External Match 1. When a match occurs between the TC and MR1, this 0
bit can either toggle, go low, go high, or do nothing, depending on bits 7:6of this register. This bit can be driven onto a MATn.1 pin, in apositive-logic manner (0 = low, 1 = high).

2

EM2

External Match 2. When a match occurs between the TC and MR2, this 0
bit can either toggle, go low, go high, or do nothing, depending on bits 9:8of this register. This bit can be driven onto a MATn.0 pin, in apositive-logic manner (0 = low, 1 = high).

3

EM3

External Match 3. When a match occurs between the TC and MR3, thisbit can either toggle, go low, go high, or do nothing, depending on bits
11:10 of this register. This bit can be driven onto a MATn.0 pin, in apositive-logic manner (0 = low, 1 = high).

5:4

EMC0

External Match Control 0. Determines the functionality of External Match 00
0. Table 21–436 shows the encoding of these bits.

7:6

EMC1

External Match Control 1. Determines the functionality of External Match 00
1. Table 21–436 shows the encoding of these bits.

9:8

EMC2

External Match Control 2. Determines the functionality of External Match 00
2. Table 21–436 shows the encoding of these bits.

11:10 EMC3External Match Control 3. Determines the functionality of External Match 00
3. Table 21–436 shows the encoding of these bits.

15:12 -

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

0

NA

Table 436. External Match Control
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]

Function00

Do Nothing.

01

Clear the corresponding External Match bit/output to 0 (MATn.m pin is
LOW if pinned out).

10

Set the corresponding External Match bit/output to 1 (MATn.m pin is
HIGH if pinned out).

11

Toggle the corresponding External Match bit/output.

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Chapter 21: LPC2300 Timer

6. Example timer operation
Figure 21–97 shows a timer configured to reset the count and generate an interrupt onmatch. The prescaler is set to 2 and the match register set to 6. At the end of the timer
cycle where the match occurs, the timer count is reset. This gives a full length cycle to thematch value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 21–98 shows a timer configured to stop and generate an interrupt on match. The
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.

PCLK
prescalecounter2

timer
counter

4

0

1

2

0

1

5

2

6

0

1
0

2

0

1
1

timer counter
reset
interrupt

Fig 97. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.

PCLK
prescale counter
timer counter
TCR[0](counter enable)

2
4

0

1
5
1

2

0
6
0

interrupt

Fig 98. A Timer Cycle in Which PR=2, MRx=6, and Both Interrupt and Stop on Match are Enabled

7. Architecture
The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in
Figure 21–99.

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Chapter 21: LPC2300 Timer

MATCH REGISTER 0
MATCH REGISTER 1
MATCH REGISTER 2
MATCH REGISTER 3
MATCH CONTROL REGISTER
EXTERNAL MATCH REGISTERINTERRUPT REGISTERCONTROL=

MAT[3:0]
INTERRUPT=CAP[3:0]=

STOP ON MATCH
RESET ON MATCH
LOAD[3:0]=

CAPTURE CONTROL REGISTERCSNCAPTURE REGISTER 0

TIMER COUNTERCAPTURE REGISTER 1CE

CAPTURE REGISTER 2CAPTURE REGISTER 3

TCI
PCLK
PRESCALE COUNTER
reset

enableTIMER CONTROL REGISTERMAXVALPRESCALE REGISTER

Fig 99. Timer block diagram

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UM10211
Chapter 22: Watchdog Timer (WDT)
Rev. 01 — 6 July 2007

User manual

1. Features• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to bedisabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate Watchdog reset.
• Programmable 32 bit timer with internal pre-scaler.
• Selectable time period from (TWDCLK × 256 × 4) to (TWDCLK × 232 × 4) in multiples of
TWDCLK × 4.

• The Watchdog clock (WDCLK) source can be selected from the RTC clock, theInternal RC oscillator (IRC), or the APB peripheral clock (PCLK). This gives a wide
range of potential timing choices for Watchdog operation under different power
reduction conditions. It also provides the ability to run the Watchdog timer from anentirely internal source that is not dependent on an external crystal and its associatedcomponents and wiring, for increased reliability.

2. Applications
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount oftime if it enters an erroneous state. When enabled, the Watchdog will generate a system
reset if the user program fails to "feed" (or reload) the Watchdog within a predeterminedamount of time.
For interaction of the on-chip watchdog and other peripherals, especially the reset andboot-up procedures, please read Section 3–4 “Reset” on page 22 of this document.

3. Description
The Watchdog consists of a divide by 4 fixed pre-scaler and a 32 bit counter. The clock is
fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value
from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF
to be loaded in the counter. Hence the minimum Watchdog interval is (TWDCLK × 256 × 4)
and the maximum Watchdog interval is (TWDCLK × 232 × 4) in multiples of (TWDCLK × 4).
The Watchdog should be used in the following manner:• Set the Watchdog timer constant reload value in WDTC register.
• Setup mode in WDMOD register.
• Enable the Watchdog by writing 0xAA followed by 0x55 to the WDFEED register.
• Watchdog should be fed again before the Watchdog counter underflows to prevent
reset/interrupt.

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Chapter 22: LPC2300 WDTWhen the Watchdog counter underflows, the program counter will start from 0x0000 0000
as in the case of external reset. The Watchdog time-out flag (WDTOF) can be examined
to determine if the Watchdog has caused the reset condition. The WDTOF flag must be
cleared by software.
The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB
accesses to the watchdog registers. The WDCLK is used for the watchdog timer counting.
There is some synchronization logic between these two clock domains. When the
WDMOD and WDTC registers are updated by APB operations, the new value will takeeffect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog
timer is counting on WDCLK, the synchronization logic will first lock the value of thecounter on WDCLK and then synchronize it with the PCLK for reading as the WDTV
register by the CPU.

4. Register description
The Watchdog contains 4 registers as shown in Table 22–437 below.
Table 437. Watchdog register map
Name

Description

Access Reset
Address
Value[1]WDMOD

Watchdog mode register. This register contains
the basic mode and status of the Watchdog
Timer.

R/W

0

0xE000 0000

WDTC

Watchdog timer constant register. This register
determines the time-out value.

R/W

0xFF

0xE000 0004

WDFEED

Watchdog feed sequence register. Writing 0xAA
followed by 0x55 to this register reloads the
Watchdog timer with the value contained in
WDTC.

WO

NA

0xE000 0008

WDTV

Watchdog timer value register. This register
reads out the current value of the Watchdog
timer.

RO

0xFF

0xE000 000C

R/W

0

0xE000 0010

WDCLKSEL Watchdog clock source selection register.
[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

4.1 Watchdog Mode Register (WDMOD - 0xE000 0000)
The WDMOD register controls the operation of the Watchdog as per the combination of
WDEN and RESET bits.

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Chapter 22: LPC2300 WDT

Table 438. Watchdog operating modes selection
WDEN

WDRESET

Mode of Operation0

X (0 or 1)

Debug/Operate without the Watchdog running.

1

0

Watchdog interrupt mode: debug with the Watchdog interrupt but no
WDRESET enabled.
When this mode is selected, a watchdog counter underflow will set the
WDINT flag and the Watchdog interrupt request will be generated.

1

1

Watchdog reset mode: operate with the Watchdog interrupt and
WDRESET enabled.
When this mode is selected, a watchdog counter underflow will reset
the microcontroller. Although the Watchdog interrupt is also enabled inthis case (WDEN = 1) it will not be recognized since the watchdog
reset will clear the WDINT flag.

Once the WDEN and/or WDRESET bits are set they can not be cleared by software. Bothflags are cleared by an external reset or a Watchdog timer underflow.
WDTOF The Watchdog time-out flag is set when the Watchdog times out. This flag iscleared by software.
WDINT The Watchdog interrupt flag is set when the Watchdog times out. This flag iscleared when any reset occurs. Once the watchdog interrupt is serviced, it can bedisabled in the VIC or the watchdog interrupt request will be generated indefinitely.
Table 439: Watchdog Mode register (WDMOD - address 0xE000 0000) bit description
Bit

SymbolDescription

Reset Value

0

WDEN

WDEN Watchdog interrupt enable bit (Set Only).

0

1

WDRESET WDRESET Watchdog reset enable bit (Set Only).

0

2

WDTOF

WDTOF Watchdog time-out flag.

0 (Only after
external reset)

3

WDINT

WDINT Watchdog interrupt flag (Read Only).

0

7:4

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

4.2 Watchdog Timer Constant Register (WDTC - 0xE000 0004)
The WDTC register determines the time-out value. Every time a feed sequence occurs
the WDTC content is reloaded in to the Watchdog timer. It’s a 32 bit register with 8 LSB
set to 1 on reset. Writing values below 0xFF will cause 0x0000 00FF to be loaded to the
WDTC. Thus the minimum time-out interval is TWDCLK × 256 × 4.
Table 440: Watchdog Constant register (WDTC - address 0xE000 0004) bit description
Bit

SymbolDescription

Reset Value

31:0

Count

Watchdog time-out interval.

0x0000 00FF

4.3 Watchdog Feed Register (WDFEED - 0xE000 0008)
Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the
WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD
register. Setting the WDEN bit in the WDMOD register is not sufficient to enable theWatchdog. A valid feed sequence must be completed after setting WDEN before theWatchdog is capable of generating a reset. Until then, the Watchdog will ignore feed
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Chapter 22: LPC2300 WDT

errors. After writing 0xAA to WDFEED, any APB register access other than writing 0x55 to
WDFEED causes an immediate reset/interrupt when the Watchdog is enabled. The reset
will be generated during the second PCLK following an incorrect access to a Watchdog
register during a feed sequence.
This implies that interrupts should be disabled during the feed sequence.
Table 441: Watchdog Feed Register (WDFEED - address 0xE000 0008) bit description
Bit

SymbolDescription

Reset Value

7:0

Feed

Feed value should be 0xAA followed by 0x55.

NA

4.4 Watchdog Timer Value Register (WDTV - 0xE000 000C)
The WDTV register is used to read the current value of Watchdog timer.
When reading the value of the 32 bit timer, the lock and synchronization procedure takes
up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual
value of the timer when it's being read by the CPU.
Table 442: Watchdog Timer Value register (WDTV - address 0xE000 000C) bit description
Bit

SymbolDescription

Reset Value

31:0

Count

Counter timer value.

0x0000 00FF

4.5 Watchdog Timer Clock Source Selection Register (WDCLKSEL 0xE000 0010)
This register allows selecting the clock source for the Watchdog timer. The possibilities are: theInternal RC oscillator (IRC), the RTC oscillator, and the APB peripheral clock (pclk). The function ofbits in WDCLKSEL are shown in Table 22–443.
Table 443: Watchdog Timer Clock Source Selection register (WDCLKSEL - address
0xE000 0010) bit description
Bit

Symbol Value Description

Reset
Value

1:0

WDSEL

0

These bits select the clock source for the Watchdog timer as
described below.
Warning: Improper setting of this value may result in incorrect
operation of the Watchdog timer, which could adversely affectsystem operation.

31:2 -

00

Selects the Internal RC oscillator as the Watchdog clock source(default).

01

Selects the APB peripheral clock (PCLK) as the Watchdog clock
source.

10

Selects the RTC oscillator as the Watchdog clock source.

11

Reserved-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

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Chapter 22: LPC2300 WDT

5. Block diagram
The block diagram of the Watchdog is shown below in the Figure 22–100. The
synchronization logic (PCLK - WDCLK) is not shown in the block diagram.

feed sequence

WDTC
feed ok

WDFEED
feed error
RTC oscillator
pclkinternal RC oscillator

wdclk

÷4

32 BIT DOWN COUNTER
underflow

enablecount

WDCLKSELSHADOW BITWMOD register
WDINT

WDTOF WDRESET

WDEN

reset
interrupt

Fig 100.Watchdog block diagram

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UM10211
Chapter 23: Pulse Width Modulator (PWM)
Rev. 01 — 6 July 2007

User manual

1. Features• Counter or Timer operation (may use the peripheral clock or one of the capture inputs
as the clock source).

• Seven match registers allow up to 6 single edge controlled or 3 double edge
controlled PWM outputs, or a mix of both types. The match registers also allow:– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.

• An external output for each match register with the following capabilities:– Set low on match.
– Set high on match.
– Toggle on match.
– Do nothing on match.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go high at the beginning of each cycle unless theoutput is a constant low. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.

• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive goingor negative going pulses.

• Match register updates are synchronized with pulse outputs to prevent generation oferroneous pulses. Software must "release" new match values before they can
become effective.

• May be used as a standard timer if the PWM mode is not enabled.
• A 32 bit Timer/Counter with a programmable 32 bit Prescaler.
• Two 32 bit capture channels take a snapshot of the timer value when an input signaltransitions. A capture event may also optionally generate an interrupt.

2. Description
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2300. The Timer is designed to countcycles of the peripheral clock (PCLK) and optionally generate interrupts or perform otheractions when specified timer values occur, based on seven match registers. The PWM
function is in addition to these features, and is based on match register events.

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Chapter 23: LPC2300 PWM

The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires
three non-overlapping PWM outputs with individual control of all three pulse widths andpositions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (PWMMR0) controls the PWM cycle rate, by resetting the count uponmatch. The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have arising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the PWMMR0 match register controls the PWM cycle rate. The other matchregisters control the two PWM edge positions. Additional double edge controlled PWM
outputs require only two match registers each, since the repetition rate is the same for all
PWM outputs.
With double edge controlled PWM outputs, specific match registers control the rising andfalling edge of the output. This allows both positive going PWM pulses (when the risingedge occurs prior to the falling edge), and negative going PWM pulses (when the fallingedge occurs prior to the rising edge).
Figure 23–101 shows the block diagram of the PWM. The portions that have been added
to the standard timer block are on the right hand side and at the top of the diagram.

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Chapter 23: LPC2300 PWM

MATCH REGISTER 0SHADOW REGISTER 0
LOAD ENABLE

MATCH REGISTER 1SHADOW REGISTER 1
LOAD ENABLE

MATCH REGISTER 2SHADOW REGISTER 2
LOAD ENABLE

MATCH REGISTER 3SHADOW REGISTER 3
LOAD ENABLE

MATCH REGISTER 4SHADOW REGISTER 4
LOAD ENABLE

MATCH REGISTER 5SHADOW REGISTER 5
LOAD ENABLE

MATCH REGISTER 6

Match 0SHADOW REGISTER 6
LOAD ENABLE

PWM1
S

Q

R

EN

Match 1PWMENA1PWMSEL2PWM2MUXMatch0

S

Q

R

EN

PWMENA2

Match 2LOAD ENABLE REGISTER

CLEAR

PWMSEL3
MATCH CONTROL REGISTER

PWM3
MUX

EXTERNAL MATCH REGISTER

Match 3

S

Q

R

EN

PWMENA3

INTERRUPT REGISTERPWMSEL4PWM4MUXCONTROL
=

Q

R

EN

PWMENA4

Match 4=

M[6:0]
INTERRUPTCAPTURE[1:0]S=

PWMSEL5

=
PWM5
MUX

=

STOP ON MATCH
RESET ON MATCH
LOAD[1:0]

=

S

Q

R

EN

Match 5=PWMENA5PWMSEL6CAPTURE CONTROL REGISTER

PWM6
MUX

S

Q

R

EN

CSN

CAPTURE REGISTER 0

TIMER COUNTER

Match 6

CAPTURE REGISTER 1PWMENA6RESERVEDCE

RESERVEDTCI
PRESCALE COUNTER

reset
TIMER CONTROL REGISTER

enablePWMENA1..6

PWMSEL2..6

MAXVALPRESCALE REGISTERPWM CONTROL REGISTER

Fig 101.PWM block diagram

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3. Sample waveform with rules for single and double edge control
A sample of how PWM values relate to waveform outputs is shown in Figure 23–102.
PWM output logic is shown in Figure 23–101 that allows selection of either single or
double edge controlled PWM outputs via the muxes controlled by the PWMSELn bits. The
match register selections for various PWM outputs is shown in Table 23–444. This
implementation supports up to N-1 single edge PWM outputs or (N-1)/2 double edge
PWM outputs, where N is the number of match registers that are implemented. PWM
types can be mixed if desired.

PWM2
PWM4

PWM5

0

27

41

53

65

78

100
(counter is reset)

The waveforms below show a single PWM cycle and demonstrate PWM outputs under thefollowing conditions:
The timer is configured for PWM mode.
Match 0 is configured to reset the timer/counter when a match event occurs.
All PWM related Match registers are configured for toggle on match.
Control bits PWMSEL2 and PWMSEL4 are set.
The Match register values are as follows:
MR0 = 100 (PWM rate)
MR1 = 41, MR2 = 78 (PWM2 output)
MR3 = 53, MR$ = 27 (PWM4 output)
MR5 = 65 (PWM5 output)

Fig 102.Sample PWM waveforms
Table 444. Set and reset inputs for PWM Flip-Flops
PWM Channel

Single Edge PWM (PWMSELn = 0)

Double Edge PWM (PWMSELn = 1)

Set byReset by

Set byReset by
Match 1[1]1Match 0Match 1

Match 0[1]2Match 0Match 2

Match 1

Match 2

3

Match 0Match 3

Match 2[2]Match 3[2]4Match 0Match 4

Match 3

Match 4
Match 5[2]Match 6

5

Match 0Match 5

Match 4[2]6Match 0Match 6

Match 5[1]

Identical to single edge mode in this case since Match 0 is the neighboring match register. Essentially,
PWM1 cannot be a double edged output.

[2]

It is generally not advantageous to use PWM channels 3 and 5 for double edge PWM outputs because it
would reduce the number of double edge PWM outputs that are possible. Using PWM 2, PWM4, andPWM6 for double edge PWM outputs provides the most pairings.

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3.1 Rules for Single Edge Controlled PWM Outputs
1. All single edge controlled PWM outputs go high at the beginning of a PWM cycle
unless their match value is equal to 0.
2. Each PWM output will go low when its match value is reached. If no match occurs (i.e.
the match value is greater than the PWM rate), the PWM output remains continuously
high.

3.2 Rules for Double Edge Controlled PWM Outputs
Five rules are used to determine the next value of a PWM output when a new cycle isabout to begin:
1. The match values for the next PWM cycle are used at the end of a PWM cycle (a time
point which is coincident with the beginning of the next PWM cycle), except as notedin rule 3.
2. A match value equal to 0 or the current PWM rate (the same as the Match channel 0
value) have the same effect, except as noted in rule 3. For example, a request for a
falling edge at the beginning of the PWM cycle has the same effect as a request for a
falling edge at the end of a PWM cycle.
3. When match values are changing, if one of the "old" match values is equal to the
PWM rate, it is used again once if the neither of the new match values are equal to 0
or the PWM rate, and there was no old match value equal to 0.
4. If both a set and a clear of a PWM output are requested at the same time, clear takes
precedence. This can occur when the set and clear match values are the same as in,or when the set or clear value equals 0 and the other value equals the PWM rate.
5. If a match value is out of range (i.e. greater than the PWM rate value), no match event
occurs and that match channel has no effect on the output. This means that the PWM
output will remain always in one state, allowing always low, always high, or"no change" outputs.

4. Pin description
Table 23–445 gives a brief summary of each of PWM related pins.
Table 445. Pin summary
Pin

Type

Description

PWM1.1

OutputOutput from PWM channel 1.

PWM1.2

OutputOutput from PWM channel 2.

PWM1.3

OutputOutput from PWM channel 3.

PWM1.4

OutputOutput from PWM channel 4.

PWM1.5

OutputOutput from PWM channel 5.

PWM1.6

OutputOutput from PWM channel 6.

PCAP1.1:0

Input

Capture Inputs. A transition on a capture pin can be configured to load
the corresponding Capture Register with the value of the TimerCounter and optionally generate an interrupt. PWM1 brings out 2
capture inputs.

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5. PWM base addresses
Table 446: Addresses for PWM1
PWM

Base Addresses

1

0xE001 8000

6. Register description
PWM1 function adds new registers and registers bits as shown in Table 23–447 below.
Table 447. PWM1 register map
Generic Description
Name

Access Reset
PWMn Register
Value[1] Name & Address

IRInterrupt Register. The IR can be written to clear interrupts. The R/W
IR can be read to identify which of eight possible interrupt
sources are pending.

0

PWM1IR - 0xE001 8000

TCR

Timer Control Register. The TCR is used to control the Timer
R/W
Counter functions. The Timer Counter can be disabled or reset
through the TCR.

0

PWM1TCR - 0xE001 8004

TC

Timer Counter. The 32 bit TC is incremented every PR+1
cycles of PCLK. The TC is controlled through the TCR.

R/W

0

PWM1TC -0xE001 8008

PR

Prescale Register. The TC is incremented every PR+1 cyclesof PCLK.

R/W

0

PWM1PR - 0xE001 800C

PC

Prescale Counter. The 32 bit PC is a counter which is
R/Wincremented to the value stored in PR. When the value in PR isreached, the TC is incremented. The PC is observable andcontrollable through the bus interface.

0

PWM1PC - 0xE001 8010

MCR

Match Control Register. The MCR is used to control if aninterrupt is generated and if the TC is reset when a Matchoccurs.

R/W

0

PWM1MCR - 0xE001 8014

MR0

Match Register 0. MR0 can be enabled in the MCR to reset the R/WTC, stop both the TC and PC, and/or generate an interrupt
when it matches the TC. In addition, a match between thisvalue and the TC sets any PWM output that is in single-edge
mode, and sets PWM1 if it’s in double-edge mode.

0

PWM1MR0 - 0xE001 8018

MR1

Match Register 1. MR1 can be enabled in the MCR to reset the R/WTC, stop both the TC and PC, and/or generate an interrupt
when it matches the TC. In addition, a match between thisvalue and the TC clears PWM1 in either edge mode, and sets
PWM2 if it’s in double-edge mode.

0

PWM1MR1 - 0xE001 801C

MR2

Match Register 2. MR2 can be enabled in the MCR to reset the R/WTC, stop both the TC and PC, and/or generate an interrupt
when it matches the TC. In addition, a match between thisvalue and the TC clears PWM2 in either edge mode, and sets
PWM3 if it’s in double-edge mode.

0

PWM1MR2 - 0xE001 8020

MR3Match Register 3. MR3 can be enabled in the MCR to reset the R/WTC, stop both the TC and PC, and/or generate an interrupt
when it matches the TC. In addition, a match between thisvalue and the TC clears PWM3 in either edge mode, and sets
PWM4 if it’s in double-edge mode.

0

PWM1MR3 - 0xE001 8024

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Table 447. PWM1 register map
Generic Description
Name

Access Reset
PWMn Register
Value[1] Name & Address

CCR

Capture Control Register. The CCR controls which edges of
the capture inputs are used to load the Capture Registers andwhether or not an interrupt is generated when a capture takes
place.

R/W

0

PWM1CCR - 0xE001 8028

CR0

Capture Register 0. CR0 is loaded with the value of the TC
when there is an event on the CAPn.0 input.

RO

0

PWM1CR0 - 0xE001 802C

CR1

Capture Register 1. See CR0 description.

RO

0

PWM1CR1 - 0xE001 8030

CR2

Capture Register 2. See CR0 description.

RO

0

PWM1CR2 - 0xE001 8034

CR3

Capture Register 3. See CR0 description.

RO

0

PWM1CR3 - 0xE001 8038

EMR

The External Match Register controls the external match pins
MAT0 through MAT6.

R/W

0

PWM1EMR - 0xE001 803C

MR4

Match Register 4. MR4 can be enabled in the MCR to reset the R/WTC, stop both the TC and PC, and/or generate an interrupt
when it matches the TC. In addition, a match between thisvalue and the TC clears PWM4 in either edge mode, and sets
PWM5 if it’s in double-edge mode.

0

PWM1MR - 0xE001 8040

MR5

Match Register 5. MR5 can be enabled in the MCR to reset the R/WTC, stop both the TC and PC, and/or generate an interrupt
when it matches the TC. In addition, a match between thisvalue and the TC clears PWM5 in either edge mode, and sets
PWM6 if it’s in double-edge mode.

0

PWM1MR - 0xE001 8044

MR6

Match Register 6. MR6 can be enabled in the MCR to reset the R/WTC, stop both the TC and PC, and/or generate an interrupt
when it matches the TC. In addition, a match between thisvalue and the TC clears PWM6 in either edge mode.

0

PWM1MR - 0xE001 8048

PCR

PWM Control Register. Enables PWM outputs and selects
PWM channel types as either single edge or double edge
controlled.

R/W

0

PWM1PCR - 0xE001 804C

LER

Load Enable Register. Enables use of new PWM match values. R/W

0

PWM1LER - 0xE001 8050

CTCR

Count Control Register. The CTCR selects between Timer and R/WCounter mode, and in Counter mode selects the signal andedge(s) for counting.

0

PWM1CTCR - 0xE001 8070

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

6.1 PWM Interrupt Register (PWM1IR - 0xE001 8000)
The PWM Interrupt Register consists of eleven bits (Table 23–448), seven for the matchinterrupts and four reserved for the future use. If an interrupt is generated then thecorresponding bit in the PWMIR will be high. Otherwise, the bit will be low. Writing a logic
one to the corresponding IR bit will reset the interrupt. Writing a zero has no effect.
Table 448: PWM Interrupt Register (PWM1IR - address 0xE001 8000) bit description
Bit

SymbolDescription

0

PWMMR0 Interrupt Interrupt flag for PWM match channel 0.

0

1

PWMMR1 Interrupt Interrupt flag for PWM match channel 1.

0

2

PWMMR2 Interrupt Interrupt flag for PWM match channel 2.

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Chapter 23: LPC2300 PWM

Table 448: PWM Interrupt Register (PWM1IR - address 0xE001 8000) bit description
Bit

SymbolDescription

Reset
Value

3

PWMMR3 Interrupt Interrupt flag for PWM match channel 3.

0

7:4

-

NA

8

PWMMR4 Interrupt Interrupt flag for PWM match channel 4.

0

9

PWMMR5 Interrupt Interrupt flag for PWM match channel 5.

0

10

PWMMR6 Interrupt Interrupt flag for PWM match channel 6.

0

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

15:11 -

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

6.2 PWM Timer Control Register (PWM1TCR - 0xE001 8004)
The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM
Timer Counter. The function of each of the bits is shown in Table 23–449.
Table 449: PWM Timer Control Register (PWM1TCR - address 0xE001 8004) bit description
Bit

SymbolDescription

Reset Value

0

Counter Enable When one, the PWM Timer Counter and PWM Prescale 0
Counter are enabled for counting. When zero, thecounters are disabled.

1

Counter Reset

When one, the PWM Timer Counter and the PWM
Prescale Counter are synchronously reset on the next
positive edge of PCLK. The counters remain reset until
TCR[1] is returned to zero.

0

2

-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

3

PWM Enable

When one, PWM mode is enabled. PWM mode causes 0
shadow registers to operate in connection with the
Match registers. A program write to a Match register will
not have an effect on the Match result until thecorresponding bit in PWMLER has been set, followed by
the occurrence of a PWM Match 0 event. Note that the
PWM Match register that determines the PWM rate
(PWM Match 0) must be set up prior to the PWM being
enabled. Otherwise a Match event will not occur tocause shadow register contents to become effective.

7:4-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

6.3 PWM Count Control Register (PWM1CTCR - 0xE001 8070)
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting. The function of each of
the bits is shown in Table 23–450.

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Table 450: PWM Count control Register (PWM1CTCR - address 0xE001 8004) bit description
Bit

Symbol

1:0

3:2

7:4

Value

Description

Reset
Value

Counter/
00
Timer Mode

Timer Mode: the TC is incremented when the Prescale
Counter matches the Prescale Register.

00

01

Counter Mode: the TC is incremented on rising edges of
the PCAP input selected by bits 3:2.

10

Counter Mode: the TC is incremented on falling edges of
the PCAP input selected by bits 3:2.

11

Counter Mode: the TC is incremented on both edges of
the PCAP input selected by bits 3:2.

Count Input
SelectWhen bits 1:0 of this register are not 00, these bits select 00
which PCAP pin which carries the signal used toincrement the TC.
00

PCAP1.0

01

CAP1.1 (Other combinations are reserved)-

Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.

NA

6.4 PWM Match Control Register (PWM1MCR - 0xE001 8014)
The PWM Match Control Registers are used to control what operations are performed
when one of the PWM Match Registers matches the PWM Timer Counter. The function ofeach of the bits is shown in Table 23–451.
Table 451: Match Control Register (PWM1MCR - address 0xE000 8014) bit description
Bit

SymbolValue Description

Reset
Value

0

PWMMR0I

1

01

PWMMR0R 1

0

0
2

3

PWMMR0S 1

PWMMR1IInterrupt on PWMMR0: an interrupt is generated when
PWMMR0 matches the value in the PWMTC.
This interrupt is disabled.
Reset on PWMMR0: the PWMTC will be reset if PWMMR0
matches it.
This feature is disabled.

Stop on PWMMR0: the PWMTC and PWMPC will be stopped 0
and PWMTCR[0] will be set to 0 if PWMMR0 matches the
PWMTC.

0This feature is disabled

1

Interrupt on PWMMR1: an interrupt is generated when
PWMMR1 matches the value in the PWMTC.

0This interrupt is disabled.

4

PWMMR1R 1

5PWMMR1S 1

0

0

Reset on PWMMR1: the PWMTC will be reset if PWMMR1
matches it.

00This feature is disabled.
Stop on PWMMR1: the PWMTC and PWMPC will be stopped 0
and PWMTCR[0] will be set to 0 if PWMMR1 matches the
PWMTC.
This feature is disabled.

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Table 451: Match Control Register (PWM1MCR - address 0xE000 8014) bit description
Bit

SymbolValue Description

Reset
Value

6

PWMMR2I

1Interrupt on PWMMR2: an interrupt is generated when
PWMMR2 matches the value in the PWMTC.

00This interrupt is disabled.

7

PWMMR2R 1

8PWMMR2S 1

9PWMMR3I

01012This feature is disabledInterrupt on PWMMR3: an interrupt is generated when
PWMMR3 matches the value in the PWMTC.

0This interrupt is disabled.

PWMMR3S 1

PWMMR4I

Interrupt on PWMMR4: An interrupt is generated when
PWMMR4 matches the value in the PWMTC.

0This interrupt is disabled.

PWMMR4S 1

15

PWMMR5I

0Interrupt on PWMMR5: An interrupt is generated when
PWMMR5 matches the value in the PWMTC.

0This interrupt is disabled.
Reset on PWMMR5: the PWMTC will be reset if PWMMR5
matches it.

0

0

0

0

This feature is disabled.
Stop on PWMMR5: the PWMTC and PWMPC will be stopped 0
and PWMTCR[0] will be set to 0 if PWMMR5 matches the
PWMTC.

0This feature is disabled

1

Interrupt on PWMMR6: an interrupt is generated when
PWMMR6 matches the value in the PWMTC.

0This interrupt is disabled.

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Stop on PWMMR4: the PWMTC and PWMPC will be stopped 0
and PWMTCR[0] will be set to 0 if PWMMR4 matches the
PWMTC.
This feature is disabled

PWMMR5S 1

0This feature is disabled.

1

PWMMR5R 1

PWMMR6I

Reset on PWMMR4: the PWMTC will be reset if PWMMR4
matches it.

0

0

18

Stop on PWMMR3: The PWMTC and PWMPC will be
stopped and PWMTCR[0] will be set to 0 if PWMMR3
matches the PWMTC.

1

14

0

This feature is disabledThis feature is disabled

PWMMR4R 1

17

Reset on PWMMR3: the PWMTC will be reset if PWMMR3
matches it.

0

13

16

This feature is disabled.

0

PWMMR3R 1

0

Stop on PWMMR2: the PWMTC and PWMPC will be stopped 0
and PWMTCR[0] will be set to 0 if PWMMR2 matches the
PWMTC.

1

0
11

Reset on PWMMR2: the PWMTC will be reset if PWMMR2
matches it.

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Table 451: Match Control Register (PWM1MCR - address 0xE000 8014) bit description
Bit

SymbolValue Description

19

PWMMR6R 1

Reset on PWMMR6: the PWMTC will be reset if PWMMR6
matches it.

0
20

Reset
Value
0

This feature is disabled.

PWMMR6S 1

Stop on PWMMR6: the PWMTC and PWMPC will be stopped 0
and PWMTCR[0] will be set to 0 if PWMMR6 matches the
PWMTC.

31:21 -

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

6.5 PWM Capture Control Register (PWM1CCR - 0xE001 8028)
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when a capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at thesame time is a valid configuration, resulting in a capture event for both edges. In thedescriptions below, “n” represents the Timer number, 0 or 1.
Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits forthat input in this register should be programmed as 000, but capture and/or interrupt canbe selected for the other 3 CAP inputs.
Table 452: PWM Capture Control Register (PWM1CCR - address 0xE001 8028) bit description
Bit

SymbolValue Description

Reset
Value

0

Capture on
CAPn.0 risingedge0This feature is disabled.

0

1

A synchronously sampled rising edge on the CAPn.0 input
will cause CR0 to be loaded with the contents of the TC.

1

2

3

4

5

6

Capture on
0
CAPn.0 falling 1
edgeThis feature is disabled.

Interrupt on
CAPn.0 event

0This feature is disabled.

1

A CR0 load due to a CAPn.0 event will generate aninterrupt.

Capture on
CAPn.1risingedge0This feature is disabled.

1

A synchronously sampled rising edge on the CAPn.1 input
will cause CR1 to be loaded with the contents of the TC.

Capture on
CAPn.1fallingedge0This feature is disabled.

1

A synchronously sampled falling edge on CAPn.1 willcause CR1 to be loaded with the contents of TC.

Interrupt on
CAPn.1 event

0This feature is disabled.

1

A CR1 load due to a CAPn.1 event will generate aninterrupt.

Capture on
CAPn.2risingedge0This feature is disabled.

1

A synchronously sampled rising edge on the CAPn.2 input
will cause CR2 to be loaded with the contents of the TC.

A synchronously sampled falling edge on CAPn.0 willcause CR0 to be loaded with the contents of TC.

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0

0

0

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Chapter 23: LPC2300 PWM

Table 452: PWM Capture Control Register (PWM1CCR - address 0xE001 8028) bit description
Bit

SymbolValue Description

Reset
Value

7

Capture on
CAPn.2fallingedge0This feature is disabled.

0

1

A synchronously sampled falling edge on CAPn.2 willcause CR2 to be loaded with the contents of TC.

Interrupt on
CAPn.2 event

0This feature is disabled.

1

A CR2 load due to a CAPn.2 event will generate aninterrupt.

Capture on
CAPn.3risingedge0This feature is disabled.

1

A synchronously sampled rising edge on the CAPn.3 input
will cause CR3 to be loaded with the contents of TC.

Capture on
CAPn.3fallingedge0This feature is disabled.

1

A synchronously sampled falling edge on CAPn.3 willcause CR3 to be loaded with the contents of TC.

Interrupt on
CAPn.3 event

0This feature is disabled.

1

A CR3 load due to a CAPn.3 event will generate aninterrupt.

8

9

10

11

31:12 -

0

0

0

0

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

6.6 PWM Control Registers (PWM1PCR - 0xE001 804C)
The PWM Control Registers are used to enable and select the type of each PWM
channel. The function of each of the bits are shown in Table 23–453.
Table 453: PWM Control Registers (PWM1PCR - address 0xE001 804C) bit description
Bit

Symbol

1:0
2

Valu
e

Description

Reset
Value

UnusedUnused, always zero.

NA

PWMSEL2 1

Selects double edge controlled mode for the PWM2 output.

00
3

PWMSEL3 1
0

4

PWMSEL4 1
0

5

PWMSEL5 1
0

6

PWMSEL6 1
0

Selects single edge controlled mode for PWM2.
Selects double edge controlled mode for the PWM3 output.
Selects double edge controlled mode for the PWM4 output.

0

Selects single edge controlled mode for PWM4.
Selects double edge controlled mode for the PWM5 output.

0

Selects single edge controlled mode for PWM5.
Selects double edge controlled mode for the PWM6 output.

0

Selects single edge controlled mode for PWM6.

8:7-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

9

PWMENA1 1

The PWM1 output enabled.

00

The PWM1 output disabled.

PWMENA2 1

The PWM2 output enabled.

0

The PWM2 output disabled.

10

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Selects single edge controlled mode for PWM3.

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Table 453: PWM Control Registers (PWM1PCR - address 0xE001 804C) bit description
Bit

Symbol11

PWMENA3 1
0

The PWM3 output disabled.

12

PWMENA4 1

The PWM4 output enabled.

0

The PWM4 output disabled.

13

PWMENA5 1

The PWM5 output enabled.

0

The PWM5 output disabled.

14

PWMENA6 1

The PWM6 output enabled.

0

The PWM6 output disabled.

31:15 Unused

Value

Description

Reset
Value

The PWM3 output enabled.

0

Unused, always zero.

0
0
0
NA

6.7 PWM Latch Enable Register (PWM1LER - 0xE001 8050)
The PWM Latch Enable Registers are used to control the update of the PWM Matchregisters when they are used for PWM generation. When software writes to the location ofa PWM Match register while the Timer is in PWM mode, the value is captured, but not
used immediately.
When a PWM Match 0 event occurs (normally also resetting the timer in PWM mode), thecontents of shadow registers will be transferred to the shadow registers if thecorresponding bit in the Latch Enable Register has been set. At that point, the new values
will take effect and determine the course of the next PWM cycle. Once the transfer of newvalues has taken place, all bits of the LER are automatically cleared. Until thecorresponding bit in the PWMLER is set and a PWM Match 0 event occurs, any value
written to the PWM Match registers has no effect on PWM operation.
For example, if PWM2 is configured for double edge operation and is currently running, atypical sequence of events for changing the timing would be:• Write a new value to the PWM Match1 register.
• Write a new value to the PWM Match2 register.
• Write to the PWMLER, setting bits 1 and 2 at the same time.
• The altered values will become effective at the next reset of the timer (when a PWM
Match 0 event occurs).
The order of writing the two PWM Match registers is not important, since neither value will
be used until after the write to LER. This insures that both values go into effect at thesame time, if that is required. A single value may be altered in the same way if needed.
The function of each of the bits in the LER is shown in Table 23–454.

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Chapter 23: LPC2300 PWM

Table 454: PWM Latch Enable Register (PWM1LER - address 0xE001 8050) bit description
Bit Symbol

Description

0

Enable PWM
Match 0 Latch

0
Writing a one to this bit allows the last value written to the PWM
Match 0 register to be become effective when the timer is next resetby a PWM Match event. See Section 23–6.4 “PWM Match Control
Register (PWM1MCR - 0xE001 8014)”.

1

Enable PWM
Match 1 Latch

0
Writing a one to this bit allows the last value written to the PWM
Match 1 register to be become effective when the timer is next resetby a PWM Match event. See Section 23–6.4 “PWM Match Control
Register (PWM1MCR - 0xE001 8014)”.

2

Enable PWM
Match 2 Latch

Writing a one to this bit allows the last value written to the PWM
0Match 2 register to be become effective when the timer is next resetby a PWM Match event. See Section 23–6.4 “PWM Match Control
Register (PWM1MCR - 0xE001 8014)”.

3

Enable PWM
Match 3 Latch

Writing a one to this bit allows the last value written to the PWM
0Match 3 register to be become effective when the timer is next resetby a PWM Match event. See Section 23–6.4 “PWM Match Control
Register (PWM1MCR - 0xE001 8014)”.

4

Enable PWM
Match 4 Latch

Writing a one to this bit allows the last value written to the PWM
0Match 4 register to be become effective when the timer is next resetby a PWM Match event. See Section 23–6.4 “PWM Match Control
Register (PWM1MCR - 0xE001 8014)”.

5

Enable PWM
Match 5 Latch

Writing a one to this bit allows the last value written to the PWM
0Match 5 register to be become effective when the timer is next resetby a PWM Match event. See Section 23–6.4 “PWM Match Control
Register (PWM1MCR - 0xE001 8014)”.

6

Enable PWM
Match 6 Latch

Writing a one to this bit allows the last value written to the PWM
0Match 6 register to be become effective when the timer is next resetby a PWM Match event. See Section 23–6.4 “PWM Match Control
Register (PWM1MCR - 0xE001 8014)”.

7-

Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.

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Chapter 24: Analog-to-Digital Converter (ADC)
Rev. 01 — 6 July 2007

User manual

1. Features• 10 bit successive approximation analog to digital converter.
• Input multiplexing among 6 pins (LPC2364/66/68) or 8 pins (LPC2378).
• Power down mode.
• Measurement range 0 to 3 V.
• 10 bit conversion time ≥ 2.44 μs.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or Timer Match signal.
• Individual result registers for each A/D channel to reduce interrupt overhead.

2. Description
Basic clocking for the A/D converters is provided by the APB clock (PCLK). A
programmable divider is included in each converter, to scale this clock to the 4.5 MHz(max) clock needed by the successive approximation process. A fully accurate conversion
requires 11 of these clocks.

3. Pin description
Table 24–455 gives a brief summary of each of ADC related pins.
Table 455. A/D pin description
Pin

Type

DescriptionAD0[5:0],AD0[7:0](LPC2378)

Input

Analog Inputs. The A/D converter cell can measure the voltage on any of these input signals.
Note that these analog inputs are always connected to their pins, even if the Pin Multiplexing
Register assigns them to port pins. A simple self-test of the A/D Converter can be done by driving
these pins as port outputs.
Note: while the ADC pins are specified as 5 V tolerant (see Section 8–2 “Pin description for
LPC2364/6/8” on page 90 and Section 8–4 “Pin description for LPC2378” on page 98), the analog
multiplexing in the ADC block is not. More than VDD(3V3)/VREF/3.3 V (VDDA) +10 % should not beapplied to any pin that is selected as an ADC input, or the ADC reading will be incorrect. If forexample AD0.0 and AD0.1 are used as the ADC0 inputs and voltage on AD0.0 = 4.5 V while
AD0.1 = 2.5 V, an excessive voltage on the AD0.0 can cause an incorrect reading of the AD0.1,
although the AD0.1 input voltage is within the right range.
If the A/D converter is not used in an application then the pins associated with A/D inputs can beused as 5V tolerant digital IO pins

VREF

Reference Voltage Reference. This pin provides a voltage reference level for the A/D converter.

VDDA ,VSSA

Power

Analog Power and Ground. These should be nominally the same voltages as VDD(3V3) and VSS
respectively but should be isolated to minimize noise and error.

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Chapter 24: LPC2300 ADC

4. Register description
The base address of the ADC is 0xE003 4000. The A/D Converter includes registers asshown in Table 24–456.
Table 456. A/D registers
Name

Description

Access Reset
Value[1]Address

AD0CR

A/D Control Register. The AD0CR registermust be written to select the operating mode
before A/D conversion can occur.

R/W

AD0GDRA/D Global Data Register. Contains the result R/Wof the most recent A/D conversion.

NA

0xE003 4004

AD0STATA/D Status Register. This register contains
RO
DONE and OVERRUN flags for all of the A/Dchannels, as well as the A/D interrupt flag.

00xE003 4030

0x0000 0001 0xE003 4000

AD0INTEN A/D Interrupt Enable Register. This register
R/W
contains enable bits that allow the DONE flagof each A/D channel to be included or
excluded from contributing to the generationof an A/D interrupt.

0x0000 0100 0xE003 400C

AD0DR0A/D Channel 0 Data Register. This registercontains the result of the most recent
conversion completed on channel 0

R/W

NA

0xE003 4010

AD0DR1

A/D Channel 1 Data Register. This registercontains the result of the most recent
conversion completed on channel 1.

R/W

NA

0xE003 4014

AD0DR2

A/D Channel 2 Data Register. This registercontains the result of the most recent
conversion completed on channel 2.

R/W

NA

0xE003 4018

AD0DR3

A/D Channel 3 Data Register. This registercontains the result of the most recent
conversion completed on channel 3.

R/W

NA

0xE003 401C

AD0DR4

A/D Channel 4 Data Register. This registercontains the result of the most recent
conversion completed on channel 4.

R/W

NA

0xE003 4020

AD0DR5

A/D Channel 5 Data Register. This registercontains the result of the most recent
conversion completed on channel 5.

R/W

NA

0xE003 4024

AD0DR6

A/D Channel 6 Data Register. This registercontains the result of the most recent
conversion completed on channel 6.

R/W

NA

0xE003 4028

AD0DR7

A/D Channel 7 Data Register. This registercontains the result of the most recent
conversion completed on channel 7.

R/W

NA

0xE003 402C

[1]

Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

4.1 A/D Control Register (AD0CR - 0xE003 4000)
The A/D Control Register provides bits to select A/D channels to be converted, A/D timing,
A/D modes, and the A/D start trigger.
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Chapter 24: LPC2300 ADC

Table 457: A/D Control Register (AD0CR - address 0xE003 4000) bit description
Bit

SymbolValue Description

Reset
Value

7:0

SEL

Selects which of the AD0.7:0 pins is (are) to be sampled and converted. For AD0, bit 0
selects Pin AD0.0, and bit 7 selects pin AD0.7. In software-controlled mode, only one ofthese bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All
zeroes is equivalent to 0x01.

15:8

CLKDIVThe APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D 0
converter, which should be less than or equal to 4.5 MHz. Typically, software should
program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but incertain cases (such as a high-impedance analog source) a slower clock may bedesirable.

16

BURST

0

Conversions are software controlled and require 11 clocks.

1

The AD converter does repeated conversions at the rate selected by the CLKS field,
scanning (if necessary) through the pins selected by 1s in the SEL field. The first
conversion after the start corresponds to the least-significant 1 in the SEL field, thenhigher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated byclearing this bit, but the conversion that’s in progress when this bit is cleared will becompleted.

0x01

0

Important: START bits must be 000 when BURST = 1 or conversions will not start.
19:17 CLKS

This field selects the number of clocks used for each conversion in Burst mode, and thenumber of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks(10 bits) and 4 clocks (3 bits).
000

11 clocks / 10 bits001

10 clocks / 9 bits

010

9 clocks / 8 bits

011

8 clocks / 7 bits

100

7 clocks / 6 bits

101

6 clocks / 5 bits

110

5 clocks / 4 bits

111

4 clocks / 3 bits

20
21

PDN

000

Reserved, user software should not write ones to reserved bits. The value read from areserved bit is not defined.

NA

1

The A/D converter is operational.

00

The A/D converter is in power-down mode.

23:22 -

Reserved, user software should not write ones to reserved bits. The value read from areserved bit is not defined.

NA

26:24 START

When the BURST bit is 0, these bits control whether and when an A/D conversion isstarted:

0000

No start (this value should be used when clearing PDN to 0).

001

Start conversion now.

010

Start conversion when the edge selected by bit 27 occurs on P2.10/EINT0.

011

Start conversion when the edge selected by bit 27 occurs on P1.27/CAP0.1.

100

Start conversion when the edge selected by bit 27 occurs on MAT0.1[1].

101Start conversion when the edge selected by bit 27 occurs on MAT0.3[1].

110Start conversion when the edge selected by bit 27 occurs on MAT1.0[1].

111Start conversion when the edge selected by bit 27 occurs on MAT1.1[1].

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Chapter 24: LPC2300 ADC

Table 457: A/D Control Register (AD0CR - address 0xE003 4000) bit description
Bit

Symbol27

EDGE

31:28 -

[1]

Value Description

Reset
Value

This bit is significant only when the START field contains 010-111. In these cases:
1

Start conversion on a falling edge on the selected CAP/MAT signal.

0

Start conversion on a rising edge on the selected CAP/MAT signal.

0

Reserved, user software should not write ones to reserved bits. The value read from areserved bit is not defined.

NA

Function not pinned out on LPC2300.

4.2 A/D Global Data Register (AD0GDR - 0xE003 4004)
The A/D Global Data Register contains the result of the most recent A/D conversion. This
includes the data, DONE, and Overrun flags, and the number of the A/D channel to which
the data relates.
Table 458: A/D Global Data Register (AD0GDR - address 0xE003 4004) bit description
Bit

SymbolDescription

Reset
Value

5:0

UnusedThese bits always read as zeroes. They provide compatible expansion
room for future, higher-resolution A/D converters.

0

15:6

V/VREF

When DONE is 1, this field contains a binary fraction representing thevoltage on the Ain pin selected by the SEL field, divided by the voltage
on the VDDA pin. Zero in the field indicates that the voltage on the Ain
pin was less than, equal to, or close to that on VSSA, while 0x3FF
indicates that the voltage on Ain was close to, equal to, or greater thanthat on VREF.

X

23:16 Unused

These bits always read as zeroes. They allow accumulation of
successive A/D values without AND-masking, for at least 256 values
without overflow into the CHN field.

0

26:24 CHN

These bits contain the channel from which the LS bits were converted.

X

29:27 Unused

These bits always read as zeroes. They could be used for expansion of 0
the CHN field in future compatible A/D converters that can convert morechannels.

30

OVERU
N

This bit is 1 in burst mode if the results of one or more conversions was 0(were) lost and overwritten before the conversion that produced theresult in the LS bits. In non-FIFO operation, this bit is cleared by reading
this register.

31

DONE

This bit is set to 1 when an A/D conversion completes. It is cleared0when this register is read and when the ADCR is written. If the ADCR is
written while a conversion is still in progress, this bit is set and a newconversion is started.

4.3 A/D Status Register (AD0STAT - 0xE003 4030)
The A/D Status register allows checking the status of all A/D channels simultaneously.
The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel
are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also foundin ADSTAT.

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Chapter 24: LPC2300 ADC

Table 459: A/D Status Register (AD0STAT - address 0xE003 4030) bit description
Bit

SymbolDescription

Reset
Value

7:0

Done7:0

These bits mirror the DONE status flags that appear in the result
register for each A/D channel.

0

15:8

Overrun7:0 These bits mirror the OVERRRUN status flags that appear in the
result register for each A/D channel. Reading ADSTAT allows
checking the status of all A/D channels simultaneously.

0

16

ADINT

This bit is the A/D interrupt flag. It is one when any of the individual
A/D channel Done flags is asserted and enabled to contribute to the
A/D interrupt via the ADINTEN register.

0

Unused, always 0.

0

31:17 Unused

4.4 A/D Interrupt Enable Register (AD0INTEN - 0xE003 400C)
This register allows control over which A/D channels generate an interrupt when aconversion is complete. For example, it may be desirable to use some A/D channels tomonitor sensors by continuously performing conversions on them. The most recent
results are read by the application program whenever they are needed. In this case, aninterrupt is not desirable at the end of each conversion for some A/D channels.
Table 460: A/D Interrupt Enable Register (AD0INTEN - address 0xE003 400C) bit description
Bit

SymbolDescription

7:0

ADINTEN 7:0

These bits allow control over which A/D channels generate
0x00
interrupts for conversion completion. When bit 0 is one, completionof a conversion on A/D channel 0 will generate an interrupt, when bit
1 is one, completion of a conversion on A/D channel 1 will generate
an interrupt, etc.

8

ADGINTEN

When 1, enables the global DONE flag in ADDR to generate aninterrupt. When 0, only the individual A/D channels enabled byADINTEN 7:0 will generate interrupts.

1

Unused, always 0.

0

31:9 Unused

Reset
Value

4.5 A/D Data Registers (AD0DR0 to AD0DR7 - 0xE003 4010 to
0xE003 402C)
The A/D Data Register hold the result when an A/D conversion is complete, and also
include the flags that indicate when a conversion has been completed and when aconversion overrun has occurred.

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Chapter 24: LPC2300 ADC

Table 461: A/D Data Registers (AD0DR0 to AD0DR7 - addresses 0xE003 4010 to
0xE003 402C) bit description
Bit

SymbolDescription

Reset
Value

5:0

UnusedUnused, always 0.

0These bits always read as zeroes. They provide compatible expansion
room for future, higher-resolution ADCs.
15:6

V/VREF

29:16 Unused

When DONE is 1, this field contains a binary fraction representing the NA
voltage on the Ain pin, divided by the voltage on the Vref pin. Zero in
the field indicates that the voltage on the Ain pin was less than, equal
to, or close to that on VREF, while 0x3FF indicates that the voltage on
Ain was close to, equal to, or greater than that on Vref.
These bits always read as zeroes. They allow accumulation of
successive A/D values without AND-masking, for at least 256 values
without overflow into the CHN field.

030

OVERRUN This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced
the result in the LS bits.This bit is cleared by reading this register.

0

31

DONE

0

This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read.

5. Operation
5.1 Hardware-triggered conversion
If the BURST bit in the ADCR is 0 and the START field contains 010-111, the A/D
converter will start a conversion when a transition occurs on a selected pin or Timer Matchsignal. The choices include conversion on a specified edge of any of 4 Match signals, orconversion on a specified edge of either of 2 Capture/Match pins. The pin state from theselected pad or the selected Match signal, XORed with ADCR bit 27, is used in the edge
detection logic.

5.2 Interrupts
An interrupt is requested to the Vectored Interrupt Controller (VIC) when the ADINT bit in
the ADSTAT register is 1. The ADINT bit is one when any of the DONE bits of A/Dchannels that are enabled for interrupts (via the ADINTEN register) are one. Software
can use the Interrupt Enable bit in the VIC that corresponds to the ADC to control whether
this results in an interrupt. The result register for an A/D channel that is generating aninterrupt must be read in order to clear the corresponding DONE flag.

5.3 Accuracy vs. Digital Receiver
While the A/D converter can be used to measure the voltage on any AIN pin, regardless ofthe pin’s setting in the Pin Select register (Table 9–84 “Pin Connect Block Register Map”
on page 110), selecting the AIN function improves the conversion accuracy by disabling
the pin’s digital receiver.

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UM10211
Chapter 25: Digital-to-Analog Converter (DAC)
Rev. 01 — 6 July 2007

User manual

1. Features• 10 bit digital to analog converter• Resistor string architecture• Buffered output• Power down mode
• Selectable speed vs. power

2. Pin description
Table 25–462 gives a brief summary of each of DAC related pins.
Table 462. D/A Pin Description
Pin

Type

Description

AOUT

OutputAnalog Output. After the selected settling time after the DACR is
written with a new value, the voltage on this pin (with respect to
VSSA) is VALUE/1024 × VREF.

VREF

Reference

Voltage Reference. This pin provides a voltage reference level for
the D/A converter.

VDDA, VSSA

Power

Analog Power and Ground. These should be nominally the same
voltages as VDD(3V3) and VSS, but should be isolated to minimize
noise and error.

3. Register description (DACR - 0xE006 C000)
This read/write register includes the digital value to be converted to analog, and a bit that
trades off performance vs. power. Bits 5:0 are reserved for future, higher-resolution D/Aconverters.
Table 463: D/A Converter Register (DACR - address 0xE006 C000) bit description
Bit

Symbol Value

Description

Reset
Value

5:0

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

15:6

VALUE

0
After the selected settling time after this field is written with a
new VALUE, the voltage on the AOUT pin (with respect to VSSA)
is VALUE/1024 × VREF.

16

BIAS

31:17 -

0

The settling time of the DAC is 1 μs max, and the maximum
current is 700 υA.

1The settling time of the DAC is 2.5 μs and the maximum
current is 350 μA.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

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Chapter 25: LPC2300 DAC

4. Operation
Bits 21:20 of the PINSEL1 register (Section 9–6.2 “Pin Function Select Register 1(PINSEL1 - 0xE002 C004)” on page 111) control whether the DAC is enabled andcontrolling the state of pin P0.26/AD0.3/AOUT/RXD3. When these bits are 10, the DAC ispowered on and active.
The settling times noted in the description of the BIAS bit are valid for a capacitance loadon the AOUT pin not exceeding 100 pF. A load impedance value greater than that value
will cause settling time longer than the specified time. One or more graph(s) of load
impedance vs. settling time will be included in the final data sheet.

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UM10211
Chapter 26: Real Time Clock (RTC) and battery RAM
Rev. 01 — 6 July 2007

User manual

1. Features• Measures the passage of time to maintain a calendar and clock.
• Ultra Low Power design to support battery powered systems.
• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, andDay of Year.

• Dedicated 32 kHz oscillator or programmable prescaler from APB clock.
• Dedicated power supply pin can be connected to a battery or to the main 3.3 V.
• An alarm output pin is included to assist in waking up from Power-down mode, or
when the chip has had power removed to all functions except the RTC and Battery
RAM (LPC2378 only).

• Periodic interrupts can be generated from increments of any field of the time registers,
and selected fractional second values.

• 2 kilobyte static RAM powered by VBAT.
• RTC and Battery RAM power supply is isolated from the rest of the chip.

2. Description
The Real Time Clock (RTC) is a set of counters for measuring time when system power ison, and optionally when it is off. It uses little power in power down mode. On the
LPC2300, the RTC can be clocked by a separate 32.768 KHz oscillator or by aprogrammable prescale divider based on the APB clock. Also, the RTC is powered by its
own power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V
supply used by the rest of the device.
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that can be used by external hardware to restore chip power
and resume operation. The alarm output has a nominal voltage swing of 1.8 V.

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Chapter 26: LPC2300 RTC

3. Architecture

RTC OSCILLATOR
CLK32kMUXCLOCK GENERATORREFERENCE CLOCK DIVIDER(PRESCALER)
strobe

CLK1

CCLK

TIME COUNTERS

counterenables

ALARM
REGISTERSCOMPARATORSCOUNTER INCREMENTALARM MASKINTERRUPT ENABLE

REGISTERINTERRUPT GENERATOR

Fig 103.RTC block diagram

4. Register description
The RTC includes a number of registers. The address space is split into four sections byfunctionality. The first eight addresses are the Miscellaneous Register Group(Section 26–4.2). The second set of eight locations are the Time Counter Group(Section 26–4.4). The third set of eight locations contain the Alarm Register Group(Section 26–5). The remaining registers control the Reference Clock Divider.
The Real Time Clock includes the register shown in Table 26–464. Detailed descriptionsof the registers follow. In these descriptions, for most of the registers the Reset Valuecolumn shows "NC", meaning that these registers are not changed by a Reset. Softwaremust initialize these registers between power-on and setting the RTC into operation.
Table 464. Real Time Clock register map
Name

Size Description

Access Reset
Value[1]Address

ILR

2

Interrupt Location Register

R/W*

0xE002 4000

CTC

15

Clock Tick CounterRO*

0xE002 4004

CCR

4Clock Control Register

R/W*

0xE002 4008

CIIR

8

Counter Increment Interrupt Register

R/W*

0xE002 400C

AMR

8Alarm Mask Register

R/W*

0xE002 4010

CTIME032

Consolidated Time Register 0RO*

0xE002 4014

CTIME132

Consolidated Time Register 1

RO*

0xE002 4018

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Chapter 26: LPC2300 RTC

Table 464. Real Time Clock register map
Name

Size Description

Access Reset
Value[1]Address

CTIME232

RO

0xE002 401C

Consolidated Time Register 2

*

SEC

6

Seconds Counter

R/W*

0xE002 4020

MIN

6

Minutes Register

R/W*

0xE002 4024

HOUR

5

Hours Register

R/W*

0xE002 4028

DOM

5

Day of Month Register

R/W*

0xE002 402C

DOW

3

Day of Week Register

R/W*

0xE002 4030

DOY

9

Day of Year Register

R/W*

0xE002 4034

MONTH

4

Months Register

R/W*

0xE002 4038

YEAR

12

Years Register

R/W*

0xE002 403C

CISS

8

Counter Increment select mask for
Sub-Second interrupt

R/W*

0xE002 4040

ALSEC

6

Alarm value for Seconds

R/W*

0xE002 4060

ALMIN

6

Alarm value for Minutes

R/W*

0xE002 4064

ALHOUR

5

Alarm value for Seconds

R/W*

0xE002 4068

ALDOM

5

Alarm value for Day of Month

R/W*

0xE002 406C

ALDOW

3

Alarm value for Day of Week

R/W*

0xE002 4070

ALDOY

9

Alarm value for Day of Year

R/W*

0xE002 4074

ALMON

4

Alarm value for Months

R/W*

0xE002 4078

ALYEAR

12

Alarm value for Year

R/W*

0xE002 407C

PREINT

13

Prescaler value, integer portion

R/W

0

0xE002 4080

PREFRAC 15

Prescaler value, integer portion

R/W

0

0xE002 4084

[1]

Registers in the RTC other than those that are part of the Prescaler are not affected by chip Reset. These
registers must be initialized by software if the RTC is enabled. Reset Value reflects the data stored in used
bits only. It does not include reserved bits content.

4.1 RTC interrupts
Interrupt generation is controlled through the Interrupt Location Register (ILR), Counter
Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register(AMR). Interrupts are generated only by the transition into the interrupt state. The ILR
separately enables CIIR and AMR interrupts. Each bit in CIIR corresponds to one of thetime counters. If CIIR is enabled for a particular counter, then every time the counter isincremented an interrupt is generated. The alarm registers allow the user to specify a date
and time for an interrupt to be generated. The AMR provides a mechanism to mask alarmcompares. If all nonmasked alarm registers match the value in their corresponding time
counter, then an interrupt is generated.
The RTC interrupt can bring the microcontroller out of power-down mode if the RTC is
operating from its own oscillator on the RTCX1-2 pins. When the RTC interrupt is enabled
for wakeup and its selected event occurs, the oscillator wakeup cycle associated with the
XTAL1/2 pins is started. For details on the RTC based wakeup process see Section 4–7.7“Interrupt Wakeup Register (INTWAKE - 0xE01F C144)” on page 54 and Section 4–8“Wakeup timer” on page 57.

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4.2 Miscellaneous register group
Table 26–465 summarizes the registers located from 0 to 7 of A[6:2]. More detailed
descriptions follow.
Table 465. Miscellaneous registers
Name

Size

Description

AccessAddress

ILR

3Interrupt Location. Reading this location indicatesthe source of an interrupt. Writing a one to theappropriate bit at this location clears the associatedinterrupt.

R/W

0xE002 4000

CTC

15

Clock Tick Counter. Value from the clock divider.

RO

0xE002 4004

CCR

4Clock Control Register. Controls the function of theclock divider.

R/W

0xE002 4008

CIIR

8

Counter Increment Interrupt. Selects which counters R/Wwill generate an interrupt when they are
incremented.

0xE002 400C

AMR

8Alarm Mask Register. Controls which of the alarm
registers are masked.

R/W

0xE002 4010

CTIME032

Consolidated Time Register 0RO

0xE002 4014

CTIME132

Consolidated Time Register 1

RO

0xE002 4018

CTIME232

Consolidated Time Register 2RO

0xE002 401C

4.2.1 Interrupt Location Register (ILR - 0xE002 4000)
The Interrupt Location Register is a 2 bit register that specifies which blocks are
generating an interrupt (see Table 26–466). Writing a one to the appropriate bit clears thecorresponding interrupt. Writing a zero has no effect. This allows the programmer to readthis register and write back the same value to clear only the interrupt that is detected by
the read.
Table 466. Interrupt Location Register (ILR - address 0xE002 4000) bit description
Bit

SymbolDescription

Reset
value

0

RTCCIF

When one, the Counter Increment Interrupt block generated an interrupt. NC
Writing a one to this bit location clears the counter increment interrupt.

1

RTCALF

When one, the alarm registers generated an interrupt. Writing a one tothis bit location clears the alarm interrupt.

NC

2

RTSSF

When one, the Counter Increment Sub-Seconds interrupt is generated.
The interrupt rate is determined by the CISS register.

NC

7:2

-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

4.2.2 Clock Tick Counter Register (CTCR - 0xE002 4004)
The Clock Tick Counter is read only. It can be reset to zero through the Clock Control
Register (CCR). The CTC consists of the bits of the clock divider counter.

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Table 467. Clock Tick Counter Register (CTCR - address 0xE002 4004) bit description
Bit

SymbolDescription

Reset
value

14:0

NA
Clock Tick Prior to the Seconds counter, the CTC counts 32,768 clocks per
Counter
second. Due to the RTC Prescaler, these 32,768 time increments may
not all be of the same duration. Refer to the Section 26–8.1 “Reference
Clock Divider (Prescaler)” on page 512 for details.

15-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

4.2.3 Clock Control Register (CCR - 0xE002 4008)
The clock register is a 4 bit register that controls the operation of the clock divide circuit.
Each bit of the clock register is described in Table 26–468.
Table 468. Clock Control Register (CCR - address 0xE002 4008) bit description
Bit

SymbolDescription

Reset
value

0

CLKEN

Clock Enable. When this bit is a one the time counters are enabled.
When it is a zero, they are disabled so that they may be initialized.

NA

1

CTCRST

CTC Reset. When one, the elements in the Clock Tick Counter are
reset. The elements remain reset until CCR[1] is changed to zero.

NA

3:2

CTTEST

Test Enable. These bits should always be zero during normal
operation.

NA

4

CLKSRCIf this bit is 0, the Clock Tick Counter takes its clock from the Prescaler, NA
as on earlier devices in the NXP Embedded ARM family. If this bit is 1,
the CTC takes its clock from the 32 kHz oscillator that’s connected to
the RTCX1 and RTCX2 pins (see Section 26–10 “RTC external 32 kHz
oscillator component selection” for hardware details).

7:5-

Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

NA

4.2.4 Counter Increment Interrupt Register (CIIR - 0xE002 400C)
The Counter Increment Interrupt Register (CIIR) gives the ability to generate an interrupt
every time a counter is incremented. This interrupt remains valid until cleared by writing a
one to bit zero of the Interrupt Location Register (ILR[0]).
Table 469. Counter Increment Interrupt Register (CIIR - address 0xE002 400C) bit description
Bit

SymbolDescription

Reset
value

0

IMSEC

When 1, an increment of the Second value generates an interrupt.

NA

1

IMMIN

When 1, an increment of the Minute value generates an interrupt.

NA

2

IMHOUR

When 1, an increment of the Hour value generates an interrupt.

NA

3

IMDOM

When 1, an increment of the Day of Month value generates aninterrupt.

NA

4

IMDOW

When 1, an increment of the Day of Week value generates an interrupt. NA

5

IMDOY

When 1, an increment of the Day of Year value generates an interrupt.

NA

6

IMMON

When 1, an increment of the Month value generates an interrupt.

NA

7

IMYEAR

When 1, an increment of the Year value generates an interrupt.

NA

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4.2.5 Counter Increment Select Mask Register (CISS - 0xE002 4040)
The CISS register provides a way to obtain millisecond-range periodic CPU interrupts
from the Real Time Clock. This can allow freeing up one of the general purpose timers, or
support power saving by putting the CPU into a reduced power mode between periodic
interrupts.
Carry out signals from different stages of the Clock Tick Counter are used to generate thesub-second interrupts. The possibilities range from 16 counts of the CTC (about
488 microseconds), up to 2,048 counts of the CTC (about 62.5 milliseconds). The
available counts and corresponding times are given in Table 26–470.
Table 470. Counter Increment Select Mask register (CISS - address 0xE002 4040) bit description
Bit Symbol

Value Description

2:0 SubSecSel

Reset
value

SubSecSelSub-Second Select. This field selects a count for the sub-second interrupt as NC
follows:000

An interrupt is generated on every 16 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 488 microseconds.

001

An interrupt is generated on every 32 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 977 microseconds.

010

An interrupt is generated on every 64 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 1.95 milliseconds.

011

An interrupt is generated on every 128 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 3.9 milliseconds.

100

An interrupt is generated on every 256 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 7.8 milliseconds.

101

An interrupt is generated on every 512 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 15.6 milliseconds.

110

An interrupt is generated on every 1024 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 31.25 milliseconds.

111

An interrupt is generated on every 2048 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 62.5 milliseconds.

6:3 Unused

Reserved, user software should not write ones to reserved bits. The value read from areserved bit is not defined.

NA

7

Subsecond interrupt enable.

NC

SubSecEna
0

The sub-second interrupt is disabled.

1

The sub-second interrupt is enabled.

4.2.6 Alarm Mask Register (AMR - 0xE002 4010)
The Alarm Mask Register (AMR) allows the user to mask any of the alarm registers.
Table 26–471 shows the relationship between the bits in the AMR and the alarms. For thealarm function, every non-masked alarm register must match the corresponding time
counter for an interrupt to be generated. The interrupt is generated only when the countercomparison first changes from no match to match. The interrupt is removed when a one iswritten to the appropriate bit of the Interrupt Location Register (ILR). If all mask bits areset, then the alarm is disabled.

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Table 471. Alarm Mask Register (AMR - address 0xE002 4010) bit description
Bit

SymbolDescription

Reset
value

0

AMRSECWhen 1, the Second value is not compared for the alarm.

NA

1

AMRMIN

When 1, the Minutes value is not compared for the alarm.

NA

2

AMRHOUR When 1, the Hour value is not compared for the alarm.

NA

3

AMRDOM

When 1, the Day of Month value is not compared for the alarm.

NA

4

AMRDOW

When 1, the Day of Week value is not compared for the alarm.

NA

5

AMRDOY

When 1, the Day of Year value is not compared for the alarm.

NA

6

AMRMON

When 1, the Month value is not compared for the alarm.

NA

7

AMRYEAR

When 1, the Year value is not compared for the alarm.

NA

4.3 Consolidated time registers
The values of the Time Counters can optionally be read in a consolidated format whichallows the programmer to read all time counters with only three read operations. The
various registers are packed into 32 bit values as shown in Table 26–472, Table 26–473,
and Table 26–474. The least significant bit of each register is read back at bit 0, 8, 16, or
24.
The Consolidated Time Registers are read only. To write new values to the TimeCounters, the Time Counter addresses should be used.

4.3.1 Consolidated Time Register 0 (CTIME0 - 0xE002 4014)
The Consolidated Time Register 0 contains the low order time values: Seconds, Minutes,
Hours, and Day of Week.
Table 472. Consolidated Time register 0 (CTIME0 - address 0xE002 4014) bit description
Bit

SymbolDescription

Reset
value

5:0
7:6

Seconds

Seconds value in the range of 0 to 59

NA-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

13:8

Minutes

Minutes value in the range of 0 to 59

NA

15:14

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

20:16

Hours

Hours value in the range of 0 to 23

NA

23:21

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

26:24

Day Of Week Day of week value in the range of 0 to 6

NA

31:27

-

NA

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

4.3.2 Consolidated Time Register 1 (CTIME1 - 0xE002 4018)
The Consolidate Time Register 1 contains the Day of Month, Month, and Year values.

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Table 473. Consolidated Time register 1 (CTIME1 - address 0xE002 4018) bit description
Bit

SymbolDescription

Reset
value

4:0

Day of Month Day of month value in the range of 1 to 28, 29, 30, or 31(depending on the month and whether it is a leap year).

NA

7:5

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

11:8

Month

Month value in the range of 1 to 12.

NA

15:12

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

27:16

Year

Year value in the range of 0 to 4095.

NA

31:28

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

4.3.3 Consolidated Time Register 2 (CTIME2 - 0xE002 401C)
The Consolidate Time Register 2 contains just the Day of Year value.
Table 474. Consolidated Time register 2 (CTIME2 - address 0xE002 401C) bit description
Bit

SymbolDescription

Reset
value

11:0

Day of YearDay of year value in the range of 1 to 365 (366 for leap years).

NA

31:12

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

4.4 Time Counter Group
The time value consists of the eight counters shown in Table 26–475 and Table 26–476.
These counters can be read or written at the locations shown in Table 26–476.
Table 475. Time Counter relationships and values)
Counter

Size

Enabled by

Minimum value

Maximum value
59

Second6

Clk1 (seeFigure 26–103)0Minute6Second

0

59

Hour

5

Minute023

Day of Month

5

Hour

1

28, 29, 30 or 31

Day of Week

3

Hour

0

6

Day of Year

9

Hour

1

365 or 366 (for leap year)

Month

4

Day of Month

1

12

Year

12

Month or day of Year

0

4095

Table 476. Time Counter registers
Name

Size Description

AccessAddress

SEC

6

Seconds value in the range of 0 to 59

R/W

0xE002 4020

MIN

6

Minutes value in the range of 0 to 59

R/W

0xE002 4024

HOUR

5

Hours value in the range of 0 to 23

R/W

0xE002 4028

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Table 476. Time Counter registers
Name

Size Description

DOM

5

Day of month value in the range of 1 to 28, 29, 30, R/W
or 31 (depending on the month and whether it is aleap year).[1]0xE002 402C

DOW

3

Day of week value in the range of 0 to 6[1]R/W

0xE002 4030

DOY

9

Day of year value in the range of 1 to 365 (366 for R/Wleap years)[1]0xE002 4034

MONTH

4

Month value in the range of 1 to 12

R/W

0xE002 4038

YEAR

12

Year value in the range of 0 to 4095

R/W

0xE002 403C

[1]

AccessAddress

These values are simply incremented at the appropriate intervals and reset at the defined overflow point.
They are not calculated and must be correctly initialized in order to be meaningful.

4.4.1 Leap year calculation
The RTC does a simple bit comparison to see if the two lowest order bits of the year
counter are zero. If true, then the RTC considers that year a leap year. The RTC considers
all years evenly divisible by 4 as leap years. This algorithm is accurate from the year 1901
through the year 2099, but fails for the year 2100, which is not a leap year. The only effectof leap year on the RTC is to alter the length of the month of February for the month, dayof month, and year counters.

5. Alarm register group
The alarm registers are shown in Table 26–477. The values in these registers arecompared with the time counters. If all the unmasked (See Section 26–4.2.6 “Alarm Mask
Register (AMR - 0xE002 4010)” on page 508) alarm registers match their correspondingtime counters then an interrupt is generated. The interrupt is cleared when a one is written
to bit one of the Interrupt Location Register (ILR[1]).
Table 477. Alarm registers
Name

Size

Description

AccessAddress

ALSEC

6

Alarm value for Seconds

R/W

0xE002 4060

ALMIN

6

Alarm value for Minutes

R/W

0xE002 4064

ALHOUR

5

Alarm value for Hours

R/W

0xE002 4068

ALDOM

5

Alarm value for Day of Month

R/W

0xE002 406C

ALDOW

3

Alarm value for Day of Week

R/W

0xE002 4070

ALDOY

9

Alarm value for Day of Year

R/W

0xE002 4074

ALMON

4

Alarm value for Months

R/W

0xE002 4078

ALYEAR

12

Alarm value for Years

R/W

0xE002 407C

6. Alarm output
The RTC includes an alarm output pin that reflects both the alarm comparisons andinterrupts from the RTC. This pin is in the RTC power domain, and therefore it is available
during all power saving modes as long as power is supplied to VBAT. Since the Alarm pin
combines the alarm and interrupt functions of the RTC, either a specific time/date/etc. or a

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periodic interval can be provided to the outside world. For example, a time of day alarm
could be used to tell external circuitry to turn on power to the LPC2300 in order to wake up
from Power-down mode.

7. RTC usage notes
The RTC may be clocked by either the 32.786 kHz RTC oscillator, or by the APB
peripheral clock (PCLK) after adjustment by the reference clock divider.
If the RTC is used, VBAT must be connected to either pin VDD(3V3) or an independent
power supply (external battery). Otherwise, VBAT should be tied to the ground (VSS). No
provision is made in the LPC2300 to retain RTC status upon the VBAT power loss, or tomaintain time incrementation if the clock source is lost, interrupted, or altered.
Since the RTC operates using one of two available clocks (the APB clock (PCLK) or the
32 kHz signal coming from the RTCX1-2pins), any interruption of the selected clock willcause the time to drift away from the time value it would have provided otherwise. The
variance could be to actual clock time if the RTC was initialized to that, or simply an error
in elapsed time since the RTC was activated.
While the signal from RTCX1-2 pins can be used to supply the RTC clock at anytime,
selecting the PCLK as the RTC clock and entering the Power Down mode will cause alapse in the time update. Also, feeding the RTC with the PCLK and altering this timebase
during system operation (by reconfiguring the PLL, the APB divider, or the RTC prescaler)
will result in some form of accumulated time error. Accumulated time errors may occur incase RTC clock source is switched between the PCLK to the RTCX pins, too.
Once the 32 kHz signal from RTCX1-2 pins is selected as a clock source, the RTC can
operate completely without the presence of the APB clock (PCLK). Therefore, power
sensitive applications (i.e. battery powered application) utilizing the RTC will reduce thepower consumption by using the signal from RTCX1-2 pins, and writing a 0 into the
PCRTC bit in the PCONP power control register (see Section 4–7 “Power control” onpage 51).

8. RTC clock generation
The RTC may be clocked by either the 32.786 kHz RTC oscillator, or by the APB
peripheral clock (PCLK) after adjustment by the reference clock divider.

8.1 Reference Clock Divider (Prescaler)
The reference clock divider (hereafter referred to as the Prescaler) may be used when the
RTC clock source is not supplied by the RTC oscillator, but comes from the APB
peripheral clock (PCLK).
The Prescaler allows generation of a 32.768 kHz reference clock from any PCLK
frequency greater than or equal to 65.536 kHz (2 × 32.768 kHz). This permits the RTC toalways run at the proper rate regardless of the peripheral clock rate. Basically, thePrescaler divides PCLK by a value which contains both an integer portion and a fractional
portion. The result is not a continuous output at a constant frequency, some clock periods
will be one PCLK longer than others. However, the overall result can always be 32,768
counts per second.
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The reference clock divider consists of a 13 bit integer counter and a 15 bit fractionalcounter. The reasons for these counter sizes are as follows:
1. For frequencies that are expected to be supported by the LPC2300, a 13 bit integer
counter is required. This can be calculated as 160 MHz divided by 32,768 minus 1
equals 4881 with a remainder of 26,624. Thirteen bits are needed to hold the value4881, but actually supports frequencies up to 268.4 MHz (32,768 × 8192).
2. The remainder value could be as large as 32,767, which requires 15 bits.
Table 478. Reference Clock Divider registers
Name

Size

Description

PREINT

13

Prescale Value, integer portion

R/W

0xE002 4080

Prescale Value, fractional portion

R/W

0xE002 4084

PREFRAC 15

AccessAddress

8.2 Prescaler Integer Register (PREINT - 0xE002 4080)
This is the integer portion of the prescale value, calculated as:
PREINT = int (PCLK/32768) - 1. The value of PREINT must be greater than or equal to 1.
Table 479: Prescaler Integer register (PREINT - address 0xE002 4080) bit description
Bit

SymbolDescription

Reset
Value

12:0

Prescaler Integer

Contains the integer portion of the RTC prescaler value.

0

15:13

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

8.3 Prescaler Fraction Register (PREFRAC - 0xE002 4084)
This is the fractional portion of the prescale value, and may be calculated as:
PREFRAC = PCLK - ((PREINT + 1) x 32768).
Table 480: Prescaler Integer register (PREFRAC - address 0xE002 4084) bit description
Bit

SymbolDescription

Reset
Value

14:0

Prescaler
FractionContains the integer portion of the RTC prescaler value.

0

15

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

8.4 Example of Prescaler Usage
In a simplistic case, the PCLK frequency is 65.537 kHz. So:
PREINT = int (PCLK / 32768) - 1 = 1 and
PREFRAC = PCLK - ([PREINT + 1] x 32768) = 1
With this prescaler setting, exactly 32,768 clocks per second will be provided to the RTC
by counting 2 PCLKs 32,767 times, and 3 PCLKs once.
In a more realistic case, the PCLK frequency is 10 MHz. Then,

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PREINT = int (PCLK / 32768) - 1 = 304 and
PREFRAC = PCLK - ([PREINT + 1] x 32768) = 5,760.
In this case, 5,760 of the prescaler output clocks will be 306 (305+1) PCLKs long, the rest
will be 305 PCLKs long.
In a similar manner, any PCLK rate greater than 65.536 kHz (as long as it is an evennumber of cycles per second) may be turned into a 32 kHz reference clock for the RTC.
The only caveat is that if PREFRAC does not contain a zero, then not all of the 32,768 persecond clocks are of the same length. Some of the clocks are one PCLK longer thanothers. While the longer pulses are distributed as evenly as possible among the remaining
pulses, this "jitter" could possibly be of concern in an application that wishes to observe
the contents of the Clock Tick Counter (CTC) directly(Section 26–4.2.2 “Clock Tick
Counter Register (CTCR - 0xE002 4004)” on page 506).

PCLK(APB clock)to clock tick counter

CLK
CLK

UNDERFLOW

15 BIT FRACTION COUNTER

13 BIT INTEGER COUNTER(DOWN COUNTER)RELOAD
15

COMBINATORIAL LOGIC

13

extendreload1513 BIT RELOAD INTEGERREGISTER(PREINT)

15 BIT FRACTION REGISTER(PREFRAC)

13

15
APB busFig 104.RTC prescaler block diagram

8.5 Prescaler operation
The Prescaler block labelled "Combination Logic" in Figure 26–104 determines when thedecrement of the 13 bit PREINT counter is extended by one PCLK. In order to both insert
the correct number of longer cycles, and to distribute them evenly, the combinatorial Logic
associates each bit in PREFRAC with a combination in the 15 bit Fraction Counter. These
associations are shown in the following Table 26–481.
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For example, if PREFRAC bit 14 is a one (representing the fraction 1/2), then half of thecycles counted by the 13 bit counter need to be longer. When there is a 1 in the LSB of the
Fraction Counter, the logic causes every alternate count (whenever the LSB of the
Fraction Counter=1) to be extended by one PCLK, evenly distributing the pulse widths.
Similarly, a one in PREFRAC bit 13 (representing the fraction 1/4) will cause every fourth
cycle (whenever the two LSBs of the Fraction Counter = 10) counted by the 13 bit counterto be longer.
Table 481. Prescaler cases where the Integer Counter reload value is incremented
Fraction Counter

PREFRAC Bit
14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

--- ---- ---- ---1

1

-

-

-

-

-

-

-

-

-

-

-

-

-

-

--- ---- ---- --10

-

1

-

-

-

-

-

-

-

-

-

-

-

-

-

--- ---- ---- -100

-

-

1

-

-

-

-

-

-

-

-

-

-

-

-

--- ---- ---- 1000

-

-

-

1

-

-

-

-

-

-

-

-

-

-

-

--- ---- ---1 0000

-

-

-

-

1

-

-

-

-

-

-

-

-

-

-

--- ---- --10 0000

-

-

-

-

-

1

-

-

-

-

-

-

-

-

-

--- ---- -100 0000

-

-

-

-

-

-

1

-

-

-

-

-

-

-

-

--- ---- 1000 0000

-

-

-

-

-

-

-

1

-

-

-

-

-

-

-

--- ---1 0000 0000

-

-

-

-

-

-

-

-

1

-

-

-

-

-

-

--- --10 0000 0000

-

-

-

-

-

-

-

-

-

1

-

-

-

-

-

--- -100 0000 0000

-

-

-

-

-

-

-

-

-

-

1

-

-

-

-

--- 1000 0000 0000

-

-

-

-

-

-

-

-

-

-

-

1

-

-

-

--1 0000 0000 0000

-

-

-

-

-

-

-

-

-

-

-

-

1

-

-

-10 0000 0000 0000

-

-

-

-

-

-

-

-

-

-

-

-

-

1

-

100 0000 0000 0000

-

-

-

-

-

-

-

-

-

-

-

-

-

-

1

9. Battery RAM
The Battery RAM is a 2 kbyte static RAM residing on the APB bus. The address range is
0xE008 4000 to 0xE008 47FF. The Battery RAM is powered from the VBAT pin along with
the RTC, both of which exist in a power domain that is isolated from the rest of the chip.
This allows them to operate while the main chip power has been removed.

10. RTC external 32 kHz oscillator component selection
The RTC external oscillator circuit is shown in Figure 26–105. Since the feedback
resistance is integrated on chip, only a crystal, the capacitances CX1 and CX2 need to beconnected externally to the microcontroller.

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LPC23xx

RTCX1

CX1

RTCX2

32 kHzXtal

CX2

Fig 105.RTC 32 kHz crystal oscillator circuit

Table 26–482 gives the crystal parameters that should be used. CL is the typical load
capacitance of the crystal and is usually specified by the crystal manufacturer. The actual
CL influences oscillation frequency. When using a crystal that is manufactured for adifferent load capacitance, the circuit will oscillate at a slightly different frequency(depending on the quality of the crystal) compared to the specified one. Therefore for an
accurate time reference it is advised to use the load capacitors as specified inTable 26–482 that belong to a specific CL. The value of external capacitances CX1 and
CX2 specified in this table are calculated from the internal parasitic capacitances and the
CL. Parasitics from PCB and package are not taken into account.
Table 482. Recommended values for the RTC external 32 kHz oscillator CX1/X2 components
Crystal load capacitance Maximum crystal seriesCLresistance RS

External load capacitors CX1, CX2

11 pF< 100 kΩ18 pF, 18 pF

13 pF< 100 kΩ22 pF, 22 pF

15 pF< 100 kΩ27 pF, 27 pF

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Chapter 27: Flash memory programming firmware
Rev. 01 — 6 July 2007

User manual

1. Flash boot loader
The boot loader controls initial operation after reset, and also provides the means toaccomplish programming of the flash memory. This could be initial programming of a
blank device, erasure and re-programming of a previously programmed device, or
programming of the flash memory by the application program in a running system.

2. Features• In-System Programming: In-System programming (ISP) is programming or
reprogramming the on-chip flash memory, using the boot loader software and UART0
serial port. This can be done when the part resides in the end-user board.

• In Application Programming: In-Application (IAP) programming is performing erase
and write operation on the on-chip flash memory, as directed by the end-user
application code.

3. Applications
The flash boot loader provides both In-System and In-Application programming interfaces
for programming the on-chip flash memory.

4. Description
The flash boot loader code is executed every time the part is powered on or reset. The
loader can execute the ISP command handler or the user application code. A LOW level
after reset at the P2.10 pin is considered as an external hardware request to start the ISP
command handler. Assuming that power supply pins are on their nominal levels when therising edge on RESET pin is generated, it may take up to 3 ms before P2.10 is sampled
and the decision on whether to continue with user code or ISP handler is made. If P2.10 issampled low and the watchdog overflow flag is set, the external hardware request to start
the ISP command handler is ignored. If there is no request for the ISP command handler
execution (P2.10 is sampled HIGH after reset), a search is made for a valid user program.
If a valid user program is found then the execution control is transferred to it. If a valid user
program is not found, the auto-baud routine is invoked.
Pin P2.10 that is used as hardware request for ISP requires special attention. Since P2.10
is in high impedance mode after reset, it is important that the user provides external
hardware (a pull-up resistor or other device) to put the pin in a defined state. Otherwise
unintended entry into ISP mode may occur.
When ISP mode is entered after a power on reset, the IRC and PLL are used to generate
CCLK of 14.748 MHz. This may not be the case when ISP is invoked by the user
application (see Section 27–9.8 “Reinvoke ISP” on page 536).

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4.1 Memory map after any reset
The flash portion of the boot block is 8 kB in size and resides in the top portion (startingfrom 0x0007 E000) of the on-chip flash memory. After any reset the entire boot block isalso mapped to the top of the on-chip memory space i.e. the boot block is also visible inthe memory region starting from the address 0x7FFF E000. The flash boot loader isdesigned to run from this memory area, but both the ISP and IAP software use parts of the
on-chip RAM. The RAM usage is described later in this chapter. The interrupt vectors
residing in the boot block of the on-chip flash memory also become active after reset, i.e.,the bottom 64 bytes of the boot block are also visible in the memory region starting fromthe address 0x0000 0000. The reset vector contains a jump instruction to the entry pointof the flash boot loader software.

2.0 GB

8 kB BOOT BLOCK

0x7FFF FFFF

(RE-MAPPED FROM TOP OF FLASH MEMORY)
2.0 GB - 8 kB

(BOOT BLOCK INTERRUPT VECTORS)

0x7FFF E000

0x0007 FFFF
8 kB BOOT BLOCK RE-MAPPED TOHIGHER ADDRESS RANGE
0x0007 E000

ON-CHIP FLASH MEMORYACTIVE INTERRUPT VECTORSFROM THE BOOT BLOCK
0x0000 0000

0.0 GBFig 106.Map of lower memory after reset

4.1.1 Criterion for Valid User CodeCriterion for valid user code: The reserved ARM interrupt vector location (0x0000 0014)
should contain the 2’s complement of the check-sum of the remaining interrupt vectors.
This causes the checksum of all of the vectors together to be 0. The boot loader code
disables the overlaying of the interrupt vectors from the boot block, then checksums theinterrupt vectors in sector 0 of the flash. If the signatures match then the execution control
is transferred to the user code by loading the program counter with 0x0000 0000. Hencethe user flash reset vector should contain a jump instruction to the entry point of the user
application code.
If the signature is not valid, the auto-baud routine synchronizes with the host via serial port
0. The host should send a ’?’ (0x3F) as a synchronization character and wait for a
response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity.
The auto-baud routine measures the bit time of the received synchronization character interms of its own frequency and programs the baud rate generator of the serial port. It also
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Chapter 27: LPC2300 Flash memory

sends an ASCII string ("Synchronized<CR><LF>") to the Host. In response to this hostshould send the same string ("Synchronized<CR><LF>"). The auto-baud routine looks at
the received characters to verify synchronization. If synchronization is verified then
"OK<CR><LF>" string is sent to the host. Host should respond by sending the crystal
frequency (in kHz) at which the part is running. For example, if the part is running at 10
MHz , the response from the host should be "10000<CR><LF>". "OK<CR><LF>" string issent to the host after receiving the crystal frequency. If synchronization is not verified thenthe auto-baud routine waits again for a synchronization character. For auto-baud to work
correctly in case of user invoked ISP, the CCLK frequency should be greater than or equal
to 10 MHz.
For more details on Reset, PLL and startup/boot code interaction see Section 4–5.2 “PLLand startup/boot code interaction”.
Once the crystal frequency is received the part is initialized and the ISP command handler
is invoked. For safety reasons an "Unlock" command is required before executing thecommands resulting in flash erase/write operations and the "Go" command. The rest of
the commands can be executed without the unlock command. The Unlock command isrequired to be executed once per ISP session. The Unlock command is explained in
Section 27–8 “ISP commands” on page 524.

4.2 Communication protocol
All ISP commands should be sent as single ASCII strings. Strings should be terminatedwith Carriage Return (CR) and/or Line Feed (LF) control characters. Extra <CR> and<LF> characters are ignored. All ISP responses are sent as <CR><LF> terminated ASCII
strings. Data is sent and received in UU-encoded format.

4.2.1 ISP command format"Command Parameter_0 Parameter_1 ... Parameter_n<CR><LF>" "Data" (Data only for
Write commands).

4.2.2 ISP response format"Return_Code<CR><LF>Response_0<CR><LF>Response_1<CR><LF> ...
Response_n<CR><LF>" "Data" (Data only for Read commands).

4.2.3 ISP data format
The data stream is in UU-encode format. The UU-encode algorithm converts 3 bytes ofbinary data in to 4 bytes of printable ASCII character set. It is more efficient than Hex
format which converts 1 byte of binary data in to 2 bytes of ASCII hex. The sender should
send the check-sum after transmitting 20 UU-encoded lines. The length of any
UU-encoded line should not exceed 61 characters(bytes) i.e. it can hold 45 data bytes.
The receiver should compare it with the check-sum of the received bytes. If thecheck-sum matches then the receiver should respond with "OK<CR><LF>" to continue
further transmission. If the check-sum does not match the receiver should respond with
"RESEND<CR><LF>". In response the sender should retransmit the bytes.
A description of UU-encode is available at the wotsit webpage.

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4.2.4 ISP flow control
A software XON/XOFF flow control scheme is used to prevent data loss due to buffer
overrun. When the data arrives rapidly, the ASCII control character DC3 (stop) is sent tostop the flow of data. Data flow is resumed by sending the ASCII control character DC1(start). The host should also support the same flow control scheme.

4.2.5 ISP command abort
Commands can be aborted by sending the ASCII control character "ESC". This feature is
not documented as a command under "ISP Commands" section. Once the escape code isreceived the ISP command handler waits for a new command.

4.2.6 Interrupts during ISP
The boot block interrupt vectors located in the boot block of the flash are active after any
reset.

4.2.7 Interrupts during IAP
The on-chip flash memory is not accessible during erase/write operations. When the user
application code starts executing the interrupt vectors from the user flash area are active.
The user should either disable interrupts, or ensure that user interrupt vectors are active in
RAM and that the interrupt handlers reside in RAM, before making a flash erase/write IAP
call. The IAP code does not use or disable interrupts.

4.2.8 RAM used by ISP command handler
ISP commands use on-chip RAM from 0x4000 0120 to 0x4000 01FF. The user could use
this area, but the contents may be lost upon reset. Flash programming commands use the
top 32 bytes of on-chip RAM. The stack is located at RAM top - 32. The maximum stackusage is 256 bytes and it grows downwards.

4.2.9 RAM used by IAP command handler
Flash programming commands use the top 32 bytes of on-chip RAM. The maximum stackusage in the user allocated stack space is 128 bytes and it grows downwards.

4.2.10 RAM used by RealMonitor
The RealMonitor uses on-chip RAM from 0x4000 0040 to 0x4000 011F. The user could
use this area if RealMonitor based debug is not required. The flash boot loader does notinitialize the stack for RealMonitor.

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5. Boot process flowchartRESETINITIALIZE

CRP1/2/3 ENABLED?

noENABLE DEBUG

yes

WATCHDOG
FLAG SET?

yes
A

no
USER CODE
VALID?

noyes

CRP3 ENABLED?

yes

EXECUTE INTERNALUSER CODEEnter ISP
MODE?
(P2.10=LOW)USER CODE VALID?
no
yes

no

yes

A

RUN AUTO-BAUDno

AUTO-BAUD
SUCCESSFUL?

yes
RECEIVE CRYSTALFREQUENCY 1

RUN ISP COMMAND
HANDLER 2(1) For details on handling the crystal frequency, see Section 27–9.8 “Reinvoke ISP” on page 536(2) For details on available ISP commands based on the CRP settings see Section 27–7 “Code Read Protection (CRP)”

Fig 107.Boot process flowchart

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6. Sector numbers
Some IAP and ISP commands operate on "sectors" and specify sector numbers. The
following table indicate the correspondence between sector numbers and memory
addresses for LPC2300 devices containing 64, 128, 256 and 512 kbytes of flash
respectively. IAP, ISP, and RealMonitor routines are located in the boot block. The bootblock is present at addresses 0x0007 E000 to 0x0007 FFFF in all devices. ISP and IAP
commands do not allow write/erase/go operation on the boot block. Because of the bootblock, the amount of flash available for user code and data is 504 K bytes in "512K"
devices.
Table 483. Sectors in a LPC2300 device
SectorNumber

SectorSize [kB]

Address Range

128 kBPart

256 kBPart

512 kBPart

0

4

0X0000 0000 - 0X0000 0FFF

x

x

x

1

4

0X0000 1000 - 0X0000 1FFF

x

x

x

2

4

0X0000 2000 - 0X0000 2FFF

x

x

x

3

4

0X0000 3000 - 0X0000 3FFF

x

x

x

4

4

0X0000 4000 - 0X0000 4FFF

x

x

x

5

4

0X0000 5000 - 0X0000 5FFF

x

x

x

6

4

0X0000 6000 - 0X0000 6FFF

x

x

x

7

4

0X0000 7000 - 0X0000 7FFF

x

x

x

8

32

0x0000 8000 - 0X0000 FFFF

x

x

x

9

32

0x0001 0000 - 0X0001 7FFF

x

x

x

10 (0x0A)

32

0x0001 8000 - 0X0001 FFFF

x

x

x

11 (0x0B)

32

0x0002 0000 - 0X0002 7FFFxx

12 (0x0C)

32

0x0002 8000 - 0X0002 FFFFxx

13 (0x0D)

32

0x0003 0000 - 0X0003 7FFFxx

14 (0X0E)

32

0x0003 8000 - 0X0003 FFFFxx

15 (0x0F)

32

0x0004 0000 - 0X0004 7FFFx

16 (0x10)

32

0x0004 8000 - 0X0004 FFFFx

17 (0x11)

32

0x0005 0000 - 0X0005 7FFFx

18 (0x12)

32

0x0005 8000 - 0X0005 FFFFx

19 (0x13)

32

0x0006 0000 - 0X0006 7FFFx

20 (0x14)

32

0x0006 8000 - 0X0006 FFFFx

21 (0x15)

32

0x0007 0000 - 0X0007 7FFFx

22 (0x16)

40x0007 8000 - 0X0007 8FFFx

23 (0x17)

40x0007 9000 - 0X0007 9FFFx

24 (0x18)

40x0007 A000 - 0X0007 AFFFx

25 (0x19)

40x0007 B000 - 0X0007 BFFFx

26 (0x1A)

40x0007 C000 - 0X0007 CFFFx

27 (0x1B)

4

0x0007 D000 - 0X0007 DFFFx

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7. Code Read Protection (CRP)
Code Read Protection is a mechanism that allows user to enable different levels of
security in the system so that access to the on-chip flash and use of the ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern in flash
location at 0x000001FC. IAP commands are not affected by the code read protection.
Starting with bootloader version 3.2 three levels of CRP are implemented. Earlier
bootloader versions had only CRP2 option implemented.
Important: any CRP change becomes effective only after the device has gone
through a power cycle.
Table 484. Code Rad Protection options
Name Pattern
Description
programmed
in 0x000001FC
CRP1 0x12345678

Access to chip via the JTAG pins is disabled. This mode allows partial
flash update using the following ISP commands and restrictions:• Write to RAM command can not access RAM below 0x40000200• Copy RAM to flash command can not write to Sector 0• Erase command can erase Sector 0 only when all sectors are
selected for erase• Compare command is disabledThis mode is useful when CRP is required and flash field updates areneeded but all sectors can not be erased. Since compare command isdisabled in case of partial updates the secondary loader should
implement checksum mechanism to verify the integrity of the flash.
CRP2 0x87654321

Access to chip via the JTAG pins is disabled. The following ISP
commands are disabled:• Read Memory• Write to RAM• Go• Copy RAM to flash• Compare
When CRP2 is enabled the ISP erase command only allows erasure of
all user sectors.
CRP3 0x43218765

Access to chip via the JTAG pins is disabled. ISP entry by pulling P2.10
LOW is disabled if a valid user code is present in flash sector 0.
This mode effectively disables ISP overide using P2.10 pin. It is up to theuser’s application to provide need flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.
Caution: when this mode is invoked, no future factory testing canbe performed on the device.

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Table 485. Code Read Protection hardware/software interaction
CRP option

User Code
Valid

P2.10 pin at
reset

JTAG enabled LPC2300
enters ISP
mode

partial flash
update in ISP
mode

No

No

X

Yes

Yes

Yes

No

Yes

High

Yes

No

NA

No

Yes

Low

Yes

Yes

Yes

CRP1

Yes

High

No

No

NA

CRP1

Yes

Low

No

Yes

Yes

CRP2

Yes

High

No

Yes

NA

CRP2

Yes

Low

No

Yes

No

CRP3

Yes

High

No

No

NA

CRP3

Yes

Low

No

No

NA

CRP1

No

x

No

Yes

Yes

CRP2

No

x

No

Yes

No

CRP3

No

x

No

Yes

No

In case a CRP mode is enabled and access to the chip is allowed via the ISP, an
unsupoorted or restricted ISP command will be terminated with return code
CODE_READ_PROTECTION_ENABLED.

8. ISP commands
The following commands are accepted by the ISP command handler. Detailed status
codes are supported for each command. The command handler sends the return code
INVALID_COMMAND when an undefined command is received. Commands and return
codes are in ASCII format.
CMD_SUCCESS is sent by ISP command handler only when received ISP command has
been completely executed and the new ISP command can be given by the host.
Exceptions from this rule are "Set Baud Rate", "Write to RAM", "Read Memory", and "Go"commands.
Table 486. ISP command summary
ISP Command

Usage

UnlockU <Unlock Code>

Table 27–487

Set Baud Rate

B <Baud Rate> <stop bit>

Table 27–488

Echo

A <setting>

Table 27–490

Write to RAM

W <start address> <number of bytes>

Table 27–491

Read Memory

R <address> <number of bytes>

Table 27–492

Prepare sector(s) for
write operation

P <start sector number> <end sector number>Table 27–493

Copy RAM to flash

C <flash address> <RAM address> <number of bytes>

Table 27–494

Go

G <address> <Mode>

Table 27–495

Erase sector(s)E <start sector number> <end sector number>Table 27–496

Blank check sector(s)I <start sector number> <end sector number>Table 27–497

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Table 486. ISP command summary
ISP Command

Usage

Described in

Read Part ID

J

Table 27–498

Read Boot code version

K

Table 27–500

CompareM <address1> <address2> <number of bytes>

Table 27–501

8.1 Unlock <Unlock code>
Table 487. ISP Unlock command
CommandU

Input

Unlock code: 2313010

Return CodeCMD_SUCCESS |INVALID_CODE |PARAM_ERROR

Description

This command is used to unlock flash Write, Erase, and Go commands.

Example"U 23130<CR><LF>" unlocks the flash Write/Erase & Go commands.

8.2 Set Baud Rate <Baud Rate> <stop bit>
Table 488. ISP Set Baud Rate command
CommandB

Input

Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200 | 230400
Stop bit: 1 | 2

Return CodeCMD_SUCCESS |INVALID_BAUD_RATE |INVALID_STOP_BIT |PARAM_ERROR

Description

This command is used to change the baud rate. The new baud rate is effective
after the command handler sends the CMD_SUCCESS return code.

Example"B 57600 1<CR><LF>" sets the serial port to baud rate 57600 bps and 1 stop bit.

Table 489. Correlation between possible ISP baudrates and CCLK frequency (in MHz)ISP Baudrate .vs.
CCLK Frequency

9600

19200

38400

10.0000+++

11.0592++

12.2880

+

+

+

+

+

+

15.3600+

18.4320++

19.6608+++

24.5760+++

25.0000+++

230400++++

ISP entry after reset uses the on chip IRC and PLL to run the device at CCLK = 14.748 MHz

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8.3 Echo <setting>
Table 490. ISP Echo command
CommandA

Input

Setting: ON = 1 | OFF = 0

Return CodeCMD_SUCCESS |PARAM_ERROR

Description

The default setting for echo command is ON. When ON the ISP command handler
sends the received serial data back to the host.

Example"A 0<CR><LF>" turns echo off.

8.4 Write to RAM <start address> <number of bytes>
The host should send the data only after receiving the CMD_SUCCESS return code. The
host should send the check-sum after transmitting 20 UU-encoded lines. The checksum isgenerated by adding raw data (before UU-encoding) bytes and is reset after transmitting
20 UU-encoded lines. The length of any UU-encoded line should not exceed
61 characters(bytes) i.e. it can hold 45 data bytes. When the data fits in less then
20 UU-encoded lines then the check-sum should be of the actual number of bytes sent.
The ISP command handler compares it with the check-sum of the received bytes. If thecheck-sum matches, the ISP command handler responds with "OK<CR><LF>" tocontinue further transmission. If the check-sum does not match, the ISP command
handler responds with "RESEND<CR><LF>". In response the host should retransmit thebytes.
Table 491. ISP Write to RAM command
Command

W

Input

Start Address: RAM address where data bytes are to be written. This address
should be a word boundary.

Return CodeCMD_SUCCESS |Number of Bytes: Number of bytes to be written. Count should be a multiple of 4
ADDR_ERROR (Address not on word boundary) |ADDR_NOT_MAPPED |COUNT_ERROR (Byte count is not multiple of 4) |PARAM_ERROR |CODE_READ_PROTECTION_ENABLED
Description

This command is used to download data to RAM. Data should be in UU-encoded
format. This command is blocked when code read protection is enabled.

Example"W 1073742336 4<CR><LF>" writes 4 bytes of data to address 0x4000 0200.

8.5 Read Memory <address> <no. of bytes>
The data stream is followed by the command success return code. The check-sum is sent
after transmitting 20 UU-encoded lines. The checksum is generated by adding raw data
(before UU-encoding) bytes and is reset after transmitting 20 UU-encoded lines. The
length of any UU-encoded line should not exceed 61 characters(bytes) i.e. it can hold45 data bytes. When the data fits in less then 20 UU-encoded lines then the check-sum isof actual number of bytes sent. The host should compare it with the checksum of thereceived bytes. If the check-sum matches then the host should respond with
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Chapter 27: LPC2300 Flash memory"OK<CR><LF>" to continue further transmission. If the check-sum does not match thenthe host should respond with "RESEND<CR><LF>". In response the ISP command
handler sends the data again.
Table 492. ISP Read Memory command
Command

R

Input

Start Address: Address from where data bytes are to be read. This address
should be a word boundary.
Number of Bytes: Number of bytes to be read. Count should be a multiple of 4.

Return CodeCMD_SUCCESS followed by <actual data (UU-encoded)> |ADDR_ERROR (Address not on word boundary) |ADDR_NOT_MAPPED |COUNT_ERROR (Byte count is not a multiple of 4) |PARAM_ERROR |CODE_READ_PROTECTION_ENABLED

Description

This command is used to read data from RAM or flash memory. This command isblocked when code read protection is enabled.

Example"R 1073741824 4<CR><LF>" reads 4 bytes of data from address 0x4000 0000.

8.6 Prepare sector(s) for write operation <start sector number> <end
sector number>This command makes flash write/erase operation a two step process.
Table 493. ISP Prepare sector(s) for write operation command
CommandP

Input

Start Sector Number
End Sector Number: Should be greater than or equal to start sector number.

Return CodeCMD_SUCCESS |BUSY |INVALID_SECTOR |PARAM_ERROR

Description

This command must be executed before executing "Copy RAM to flash" or "Erase
Sector(s)" command. Successful execution of the "Copy RAM to flash" or "Erase
Sector(s)" command causes relevant sectors to be protected again. The bootblock can not be prepared by this command. To prepare a single sector use thesame "Start" and "End" sector numbers.

Example"P 0 0<CR><LF>" prepares the flash sector 0.

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8.7 Copy RAM to flash <flash address> <RAM address> <no of bytes>
Table 494. ISP Copy command
CommandC

Input

Flash Address(DST): Destination flash address where data bytes are to be
written. The destination address should be a 256 byte boundary.
RAM Address(SRC): Source RAM address from where data bytes are to be read.
Number of Bytes: Number of bytes to be written. Should be 256 | 512 | 1024 |4096.

Return Code CMD_SUCCESS |SRC_ADDR_ERROR (Address not on word boundary) |DST_ADDR_ERROR (Address not on correct boundary) |SRC_ADDR_NOT_MAPPED |DST_ADDR_NOT_MAPPED |COUNT_ERROR (Byte count is not 256 | 512 | 1024 | 4096) |SECTOR_NOT_PREPARED_FOR WRITE_OPERATION |BUSY |
CMD_LOCKED |PARAM_ERROR |CODE_READ_PROTECTION_ENABLED
Description

This command is used to program the flash memory. The "Prepare Sector(s) for
Write Operation" command should precede this command. The affected sectors areautomatically protected again once the copy command is successfully executed.
The boot block cannot be written by this command. This command is blocked whencode read protection is enabled.

Example"C 0 1073774592 512<CR><LF>" copies 512 bytes from the RAM address
0x4000 8000 to the flash address 0.

8.8 Go <address> <mode>
Table 495. ISP Go command
CommandG

Input

Address: Flash or RAM address from which the code execution is to be started.
This address should be on a word boundary.
Mode: T (Execute program in Thumb Mode) | A (Execute program in ARM mode).

Return Code CMD_SUCCESS |ADDR_ERROR |ADDR_NOT_MAPPED |CMD_LOCKED |PARAM_ERROR |CODE_READ_PROTECTION_ENABLED
Description

This command is used to execute a program residing in RAM or flash memory. It
may not be possible to return to the ISP command handler once this command is
successfully executed. This command is blocked when code read protection isenabled.

Example"G 0 A<CR><LF>" branches to address 0x0000 0000 in ARM mode.

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8.9 Erase sector(s) <start sector number> <end sector number>Table 496. ISP Erase sector command
Command

E

Input

Start Sector Number
End Sector Number: Should be greater than or equal to start sector number.

Return Code CMD_SUCCESS |BUSY |INVALID_SECTOR |SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |CMD_LOCKED |PARAM_ERROR |CODE_READ_PROTECTION_ENABLED
Description

This command is used to erase one or more sector(s) of on-chip flash memory. Theboot block can not be erased using this command. This command only allows
erasure of all user sectors when the code read protection is enabled.

Example"E 2 3<CR><LF>" erases the flash sectors 2 and 3.

8.10 Blank check sector(s) <sector number> <end sector number>Table 497. ISP Blank check sector command
Command

I

Input

Start Sector Number:
End Sector Number: Should be greater than or equal to start sector number.

Return Code CMD_SUCCESS |SECTOR_NOT_BLANK (followed by <Offset of the first non blank word location><Contents of non blank word location>) |INVALID_SECTOR |PARAM_ERROR |Description

This command is used to blank check one or more sectors of on-chip flash memory.
Blank check on sector 0 always fails as first 64 bytes are re-mapped to flash
boot block.

Example"I 2 3<CR><LF>" blank checks the flash sectors 2 and 3.

8.11 Read Part Identification number
Table 498. ISP Read Part Identification command
Command

J

Input

None.

Return Code CMD_SUCCESS followed by part identification number in ASCII (see Table 27–499“LPC2300 part Identification numbers”).
Description

This command is used to read the part identification number.

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Table 499. LPC2300 part Identification numbers
DeviceASCII/dec coding

Hex coding

LPC2364

100924162

0x0603 FB02

LPC2366

100924195

0x0603 FB23

LPC2368

100924197

0x0603 FB25

LPC2378117702437

0x0703 FF25

8.12 Read Boot code version number
Table 500. ISP Read Boot Code version number command
Command

K

Input

None

Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format.
It is to be interpreted as <byte1(Major)>.<byte0(Minor)>.
Description

This command is used to read the boot code version number.

8.13 Compare <address1> <address2> <no of bytes>
Table 501. ISP Compare command
CommandM

Input

Address1 (DST): Starting flash or RAM address of data bytes to be compared.
This address should be a word boundary.
Address2 (SRC): Starting flash or RAM address of data bytes to be compared.
This address should be a word boundary.
Number of Bytes: Number of bytes to be compared; should be a multiple of 4.

Return Code CMD_SUCCESS | (Source and destination data are equal)
COMPARE_ERROR | (Followed by the offset of first mismatch)
COUNT_ERROR (Byte count is not a multiple of 4) |ADDR_ERROR |ADDR_NOT_MAPPED |PARAM_ERROR |Description

This command is used to compare the memory contents at two locations.
Compare result may not be correct when source or destination addresscontains any of the first 64 bytes starting from address zero. First 64 bytes
are re-mapped to flash boot sector

Example"M 8192 1073741824 4<CR><LF>" compares 4 bytes from the RAM address
0x4000 0000 to the 4 bytes from the flash address 0x2000.

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8.14 ISP Return Codes
Table 502. ISP Return Codes Summary
Return Mnemonic
Code

Description0

CMD_SUCCESS

Command is executed successfully. Sent by ISP
handler only when command given by the host has
been completely and successfully executed.

1

INVALID_COMMAND

Invalid command.

2

SRC_ADDR_ERROR

Source address is not on word boundary.

3

DST_ADDR_ERROR

Destination address is not on a correct boundary.

4

SRC_ADDR_NOT_MAPPED

Source address is not mapped in the memory map.
Count value is taken in to consideration whereapplicable.

5

DST_ADDR_NOT_MAPPED

Destination address is not mapped in the memory
map. Count value is taken in to consideration
where applicable.

6

COUNT_ERROR

Byte count is not multiple of 4 or is not a permitted
value.

7

INVALID_SECTOR

Sector number is invalid or end sector number isgreater than start sector number.

8

SECTOR_NOT_BLANK

Sector is not blank.

9

SECTOR_NOT_PREPARED_FOR_ Command to prepare sector for write operation
WRITE_OPERATION
was not executed.

10

COMPARE_ERROR

Source and destination data not equal.

11

BUSY

Flash programming hardware interface is busy.

12

PARAM_ERROR

Insufficient number of parameters or invalid
parameter.

13

ADDR_ERROR

Address is not on word boundary.

14

ADDR_NOT_MAPPED

Address is not mapped in the memory map. Countvalue is taken in to consideration where applicable.

15

CMD_LOCKED

Command is locked.

16

INVALID_CODE

Unlock code is invalid.

17

INVALID_BAUD_RATE

Invalid baud rate setting.

18

INVALID_STOP_BIT

Invalid stop bit setting.

19

CODE_READ_PROTECTION_ENABLED

Code read protection enabled.

9. IAP commands
For in application programming the IAP routine should be called with a word pointer inregister r0 pointing to memory (RAM) containing command code and parameters. Resultof the IAP command is returned in the result table pointed to by register r1. The user canreuse the command table for result by passing the same pointer in registers r0 and r1. The
parameter table should be big enough to hold all the results in case if number of results
are more than number of parameters. Parameter passing is illustrated in the
Figure 27–108. The number of parameters and results vary according to the IAP
command. The maximum number of parameters is 5, passed to the "Copy RAM to
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FLASH" command. The maximum number of results is 2, returned by the "Blankchecksector(s)" command. The command handler sends the status code INVALID_COMMAND
when an undefined command is received. The IAP routine resides at 0x7FFF FFF0
location and it is thumb code.
The IAP function could be called in the following way using C.
Define the IAP location entry point. Since the 0th bit of the IAP location is set there will bea change to Thumb instruction set when the program counter branches to this address.
#define IAP_LOCATION 0x7ffffff1
Define data structure or pointers to pass IAP command table and result table to the IAP
function:unsigned long command[5];unsigned long result[2];orunsigned long * command;
unsigned long * result;command=(unsigned long *) 0x……
result= (unsigned long *) 0x……
Define pointer to function type, which takes two parameters and returns void. Note the IAP
returns the result with the base address of the table residing in R1.
typedef void (*IAP)(unsigned int [],unsigned int[]);
IAP iap_entry;
Setting function pointer:
iap_entry=(IAP) IAP_LOCATION;
Whenever you wish to call IAP you could use the following statement.
iap_entry (command, result);
The IAP call could be simplified further by using the symbol definition file feature
supported by ARM Linker in ADS (ARM Developer Suite). You could also call the IAP
routine using assembly code.
The following symbol definitions can be used to link IAP routine and user application:#<SYMDEFS># ARM Linker, ADS1.2 [Build 826]: Last Updated: Wed May 08 16:12:23 2002
0x7fffff90 T rm_init_entry
0x7fffffa0 A rm_undef_handler
0x7fffffb0 A rm_prefetchabort_handler
0x7fffffc0 A rm_dataabort_handler
0x7fffffd0 A rm_irqhandler
0x7fffffe0 A rm_irqhandler2
0x7ffffff0 T iap_entry

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As per the ARM specification (The ARM Thumb Procedure Call Standard SWS ESPC
0002 A-05) up to 4 parameters can be passed in the r0, r1, r2 and r3 registers
respectively. Additional parameters are passed on the stack. Up to 4 parameters can be
returned in the r0, r1, r2 and r3 registers respectively. Additional parameters are returned
indirectly via memory. Some of the IAP calls require more than 4 parameters. If the ARM
suggested scheme is used for the parameter passing/returning then it might create
problems due to difference in the C compiler implementation from different vendors. The
suggested parameter passing scheme reduces such risk.
The flash memory is not accessible during a write or erase operation. IAP commands,
which results in a flash write/erase operation, use 32 bytes of space in the top portion of
the on-chip RAM for execution. The user program should not be use this space if IAP flash
programming is permitted in the application.
Table 503. IAP Command Summary
IAP Command

Command CodeDescribed in

Prepare sector(s) for write operation

5010

Table 27–504

Copy RAM to flash

5110

Table 27–505

Erase sector(s)5210

Table 27–506

Blank check sector(s)5310

Table 27–507

Read Part ID

5410

Table 27–508

Read Boot code version

5510

Table 27–509

Compare5610

Table 27–510

Reinvoke ISP

5710

Table 27–511

COMMAND CODE
PARAMETER 1

commandparameter table

PARAMETER 2
ARM REGISTER r0

PARAMETER n
ARM REGISTER r1

STATUS CODERESULT 1

commandresult table

RESULT 2

RESULT n

Fig 108.IAP parameter passing

9.1 Prepare sector(s) for write operation
This command makes flash write/erase operation a two step process.
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Table 504. IAP Prepare sector(s) for write operation command
Command

Prepare sector(s) for write operation

Input

Command code: 5010
Param0: Start Sector Number
Param1: End Sector Number (should be greater than or equal to start sector
number).

Return CodeCMD_SUCCESS |BUSY |INVALID_SECTOR

ResultNone

Description

This command must be executed before executing "Copy RAM to flash" or "Erase
Sector(s)" command. Successful execution of the "Copy RAM to flash" or "Erase
Sector(s)" command causes relevant sectors to be protected again. The bootsector can not be prepared by this command. To prepare a single sector use thesame "Start" and "End" sector numbers.

9.2 Copy RAM to flash
Table 505. IAP Copy RAM to flash command
Command

Copy RAM to flash

Input

Command code: 5110
Param0(DST): Destination flash address where data bytes are to be written. Thisaddress should be a 256 byte boundary.
Param1(SRC): Source RAM address from which data bytes are to be read. Thisaddress should be a word boundary.
Param2: Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.
Param3: System Clock Frequency (CCLK) in kHz.

Return CodeCMD_SUCCESS |SRC_ADDR_ERROR (Address not a word boundary) |DST_ADDR_ERROR (Address not on correct boundary) |SRC_ADDR_NOT_MAPPED |DST_ADDR_NOT_MAPPED |COUNT_ERROR (Byte count is not 256 | 512 | 1024 | 4096) |SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |BUSY |

ResultNone

Description

This command is used to program the flash memory. The affected sectors should
be prepared first by calling "Prepare Sector for Write Operation" command. The
affected sectors are automatically protected again once the copy command is
successfully executed. The boot sector can not be written by this command.

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9.3 Erase Sector(s)Table 506. IAP Erase Sector(s) command
CommandErase Sector(s)InputCommand code: 5210
Param0: Start Sector Number
Param1: End Sector Number (should be greater than or equal to start sector
number).
Param2: System Clock Frequency (CCLK) in kHz.

Return CodeCMD_SUCCESS |BUSY |SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |INVALID_SECTOR

ResultNone

Description

This command is used to erase a sector or multiple sectors of on-chip flash
memory. The boot sector can not be erased by this command. To erase a single
sector use the same "Start" and "End" sector numbers.

9.4 Blank check sector(s)Table 507. IAP Blank check sector(s) command
Command

Blank check sector(s)InputCommand code: 5310
Param0: Start Sector Number
Param1: End Sector Number (should be greater than or equal to start sector
number).

Return CodeCMD_SUCCESS |BUSY |SECTOR_NOT_BLANK |INVALID_SECTOR

ResultResult0: Offset of the first non blank word location if the Status Code is
SECTOR_NOT_BLANK.
Result1: Contents of non blank word location.

Description

This command is used to blank check a sector or multiple sectors of on-chip flash
memory. To blank check a single sector use the same "Start" and "End" sector
numbers.

9.5 Read Part Identification number
Table 508. IAP Read Part Identification command
Command

Read part identification number

Input

Command code: 5410

Return CodeCMD_SUCCESS |ResultResult0: Part Identification Number.

Description

This command is used to read the part identification number.

Parameters: None

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9.6 Read Boot code version number
Table 509. IAP Read Boot Code version number command
Command

Read boot code version number

Input

Command code: 5510
Parameters: None

Return CodeCMD_SUCCESS |ResultResult0: 2 bytes of boot code version number in ASCII format. It is to beinterpreted as <byte1(Major)>.<byte0(Minor)>

Description

This command is used to read the boot code version number.

9.7 Compare <address1> <address2> <no of bytes>
Table 510. IAP Compare command
CommandCompareInput

Command code: 5610
Param0(DST): Starting flash or RAM address of data bytes to be compared. Thisaddress should be a word boundary.
Param1(SRC): Starting flash or RAM address of data bytes to be compared. Thisaddress should be a word boundary.
Param2: Number of bytes to be compared; should be a multiple of 4.

Return CodeCMD_SUCCESS |COMPARE_ERROR |COUNT_ERROR (Byte count is not a multiple of 4) |ADDR_ERROR |ADDR_NOT_MAPPEDResultDescription

Result0: Offset of the first mismatch if the Status Code is COMPARE_ERROR.
This command is used to compare the memory contents at two locations.
The result may not be correct when the source or destination includes anyof the first 64 bytes starting from address zero. The first 64 bytes can be
re-mapped to RAM.

9.8 Reinvoke ISP
Table 511. Reinvoke ISP
CommandCompareInput

Command code: 5710

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Table 511. Reinvoke ISP
CommandCompareReturn Code

None

ResultNone.

Description

This command is used to invoke the bootloader in ISP mode. It maps bootvectors, sets PCLK = CCLK / 4, configures UART0 pins Rx and Tx, restets
TIMER1 and resets the U0FDR (see Section 14–3.12). This command may be
used when a valid user program is present in the internal flash memory and theP2.10 pin is not accessible to force the ISP mode. The command does not disable
the PLL hence it is possible to invoke the bootloader when the part is running off
the PLL. In such case the ISP utility should pass the CCLK (crystal or PLL output
depending on the clock source selection Section 4–4.1) frequency after autobaud
handshake.
Another option is to disable the PLL and select the IRC as the clock source before
making this IAP call. In this case frequency sent by ISP is ignored and IRC and
PLL are used to generate CCLK = 14.748 MHz.

9.9 IAP Status Codes
Table 512. IAP Status Codes Summary
Status Mnemonic
Code

Description0

CMD_SUCCESS

Command is executed successfully.

1

INVALID_COMMAND

Invalid command.

2

SRC_ADDR_ERROR

Source address is not on a word boundary.

3

DST_ADDR_ERROR

Destination address is not on a correct boundary.

4

SRC_ADDR_NOT_MAPPED

Source address is not mapped in the memory map.
Count value is taken in to consideration whereapplicable.

5

DST_ADDR_NOT_MAPPED

Destination address is not mapped in the memory
map. Count value is taken in to consideration whereapplicable.

6

COUNT_ERROR

Byte count is not multiple of 4 or is not a permitted
value.

7

INVALID_SECTOR

Sector number is invalid.

8

SECTOR_NOT_BLANK

Sector is not blank.

9

SECTOR_NOT_PREPARED_
FOR_WRITE_OPERATION

Command to prepare sector for write operation was
not executed.

10

COMPARE_ERROR

Source and destination data is not same.

11

BUSY

Flash programming hardware interface is busy.

10. JTAG flash programming interface
Debug tools can write parts of the flash image to the RAM and then execute the IAP call
"Copy RAM to flash" repeatedly with proper offset.

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Chapter 28: General Purpose DMA controller (GPDMA)
Rev. 01 — 6 July 2007

User manual

1. Introduction
The General Purpose DMA Controller (GPDMA) is an AMBA AHB compliant peripheral
allowing selected LPC2300 peripherals to have DMA support.

2. Features of the GPDMA• Two DMA channels. Each channel can support a unidirectional transfer.
• The GPDMA provides 16 peripheral DMA request lines. Some of these are connected
to peripheral functions that support DMA: the SD/MMC, two SSP, and I2S interfaces.

• Single DMA and burst DMA request signals. Each peripheral connected to the
GPDMA can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the GPDMA.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, andperipheral-to-peripheral transfers.

• Scatter or gather DMA is supported through the use of linked lists. This means thatthe source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority. Each DMA channel has a specific hardware priority.
DMA channel 0 has the highest priority and channel 1 has the lowest priority. If
requests from two channels become active at the same time the channel with thehighest priority is serviced first.

• AHB slave DMA programming interface. The GPDMA is programmed by writing to the
DMA control registers over the AHB slave interface.

• One AHB bus master for transferring data. This interface transfers data when a DMA
request goes active.

• 32 bit AHB master bus width.
• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the
peripheral.

• Internal four-word FIFO per channel.
• Supports 8, 16, and 32 bit wide transactions.
• Big-endian and little-endian support. The GPDMA defaults to little-endian mode on
reset.

• An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.

• Interrupt masking. The DMA error and DMA terminal count interrupt requests can bemasked.

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be readprior to masking.

• Test registers for use in block and integration system level testing.
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Chapter 28: LPC2300 GPDMA• Identification registers that uniquely identify the GPDMA. These can be used by anoperating system to automatically configure itself.

3. Functional overview
This chapter describes the major functional blocks of the GPDMA. It contains the following
sections:• GPDMA functional description• System considerations• System connectivity• Use with memory management unit based systems
3.1 GPDMA functional description
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, andcan be accessed through the AHB master.
Figure 28–109 shows a block diagram of the GPDMA.

GPDMA

AHB BUSDMA
requests
DMA
responses

DMA
Interrupts

AHB SLAVEINTERFACE

CONTROL
LOGIC ANDREGISTERSDMAREQUESTANDRESPONSE
INTERFACECHANNELLOGIC ANDREGISTERS

AHB
MASTER
INTERFACEAHB BUSINTERRUPTREQUESTFig 109.GPDMA Block Diagram

The functions of the GPDMA are described in the following sections:• AHB slave interface• Control logic and register bank
• DMA request and response interface• Channel logic and channel register bank
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Chapter 28: LPC2300 GPDMA• Interrupt request• AHB master interface• Channel hardware• DMA request priority
3.1.1 AHB Slave Interface
All transactions on the AHB slave programming bus of the GPDMA are 32 bit wide.

3.1.2 Control Logic and Register Bank
The register block stores data written, or to be read across the AHB interface.

3.1.3 DMA Request and Response Interface
See DMA Interface description for information on the DMA request and responseinterface.

3.1.4 Channel Logic and Channel Register Bank
The channel logic and channel register bank contains registers and logic required for each
DMA channel.

3.1.5 Interrupt Request
The interrupt request generates interrupts to the ARM processor.

3.1.6 AHB Master Interface
The GPDMA contains a full AHB master. See Figure 28–110 for an example showing the
GPDMA connected into a system.

ARM

AHB
BRIDGE

GPDMA
AHB
SLAVE

AHB
MASTERUART

EXTERNAL
MEMORY

EXTERNAL
MEMORYCONTROLLER

APB
BRIDGE

TIMER

GPIO
AHB
PERIPHERALINTERNAL
SRAM

Fig 110.Example of GPDMA in a System

The AHB master is capable of dealing with all types of AHB transactions, including:• Split, retry, and error responses from slaves. If a peripheral performs a split or retry,
the GPDMA stalls and waits until the transaction can complete.

• Locked transfers for source and destination of each stream.
• Setting of protection bits for transfers on each stream.
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Chapter 28: LPC2300 GPDMA

3.1.7 Bus and Transfer Widths
The physical width of the AHB bus is 32 bits. Source and destination transfers can be ofdiffering widths, and can be the same width or narrower than the physical bus width. The
GPDMA packs or unpacks data as appropriate.

3.1.8 Endian Behavior
The GPDMA can cope with both little-endian and big-endian addressing. You can set theendianness of each AHB master individually.
Internally the GPDMA treats all data as a stream of bytes instead of 16 bit or 32 bit
quantities. This means that when performing mixed-endian activity, where the endiannessof the source and destination are different, byte swapping of the data within the 32 bit databus is observed.
Note: If you do not require byte swapping then avoid using different endianness between
the source and destination addresses.
Table 28–513 shows endian behavior for different source and destination combinations.
Table 513. Endian behavior
Sourc DestinatioenEndian Endian

Sourc
e
Width

Destination Source
WidthTransfer no/
byte Lane

Sourc Destinatione Data Transfer no/
byte Lane

Destination
Data

Little88LittleLittleLittleLittleLittleLittleLittleLittleLittleLittleLittle

8

8

16

16

16

16

32

8

16

32

1/[7:0]21

1/[7:0]21212121

2/[15:8]43

2/[15:8]43434343

3/[23:16]65

3/[23:16]

65656565

4/[31:24]

87

4/[31:24]

87878787

1/[7:0]21

1/[15:0]43214321

2/[15:8]43

2/[31:16]

87658765

3/[23:16]65
1/[31:0]87654321

4/[31:24]

87

1/[7:0]21

2/[15:8]43

3/[23:16]65

4/[31:24]

87

1/[7:0]21

1/[7:0]21212121

1/[15:8]43

2/[15:8]43434343

2/[23:16]65

3/[23:16]

65656565

2/[31:24]

87

4/[31:24]

87878787

1/[7:0]21

1/[15:0]43214321

1/[15:8]43

2/[31:16]

87658765

2/[23:16]65

2/[31:24]

87

1/[7:0]21

1/[31:0]87654321

2/[15:8]43

3/[23:16]65

4/[31:24]

87

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Table 513. Endian behavior
Sourc DestinatioenEndian Endian

Sourc
e
Width

Destination Source
WidthTransfer no/
byte Lane

Sourc Destinatione Data Transfer no/
byte Lane

Destination
Data

Little32

81/[7:0]21

1/[7:0]21212121

1/[15:8]43

2/[15:8]43434343

2/[23:16]65

3/[23:16]

65656565

2/[31:24]

87

4/[31:24]

87878787

1/[7:0]21

1/[15:0]43214321

1/[15:8]43

2/[31:16]

87658765

2/[23:16]65

2/[31:24]

87

1/[7:0]21

1/[31:0]87654321

2/[15:8]43

3/[23:16]65

4/[31:24]

87

1/[31:24]

12

1/[31:24]

12121212

2/[23:16]

34

2/[23:16]

34343434

3/[15:8]56

3/[15:8]56565656

4/[7:0]78

4/[7:0]78787878

1/[31:24]

12

1/[15:0]12341234

2/[23:16]34

2/[31:16]

56785678

3/[15:8]56

4/[7:0]78

1/[31:24]

12

1/[31:0]12345678

2/[23:16]

34

3/[15:8]56

4/[7:0]78

1/[31:24]

12

1/[31:24]

12121212

2/[23:16]

34

2/[23:16]

34343434

3/[15:8]56

3/[15:8]56565656

4/[7:0]78

4/[7:0]78787878

1/[31:24]

12

1/[15:0]12341234

2/[23:16]34

2/[31:16]

56785678

3/[15:8]56

4/[7:0]78
1/[31:0]12345678

LittleLittle

Big

Big

Big

Big

Big

Big

LittleLittleLittle

Big

Big

Big

Big

Big

Big

32

32

8

8

8

16

16

16

16

32

8

16

32

8

16

32

1/[31:24]

12

2/[23:16]

34

3/[15:8]56

4/[7:0]78

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Chapter 28: LPC2300 GPDMA

Table 513. Endian behavior
Sourc DestinatioenEndian Endian

Sourc
e
Width

Destination Source
WidthTransfer no/
byte Lane

Sourc Destinatione Data Transfer no/
byte Lane

Big

32

8

Big

Big

Big

Big

Big

32

16

32

32

DestinationData

1/[31:24]

12

1/[31:24]

12121212

2/[23:16]

34

2/[23:16]

34343434

3/[15:8]56

3/[15:8]56565656

4/[7:0]78

4/[7:0]78787878

1/[31:24]

12

1/[15:0]12341234

2/[23:16]34

2/[31:16]

56785678

3/[15:8]56

4/[7:0]78

1/[31:24]

12

1/[31:0]12345678

2/[23:16]

34

3/[15:8]56

4/[7:0]78

3.1.9 Error Conditions
An error during a DMA transfer is flagged directly by the peripheral by asserting an Error
response on the AHB bus during the transfer. The GPDMA automatically disables the
DMA stream after the current transfer has completed, and can optionally generate anerror interrupt to the CPU. This error interrupt can be masked.

3.1.10 Channel Hardware
Each stream is supported by a dedicated hardware channel, including source anddestination controllers, and a FIFO. This enables better latency than a DMA controller with
only a single hardware channel shared between several DMA streams and simplifies thecontrol logic.

3.1.11 DMA Request Priority
DMA channel priority is fixed. DMA channel 0 has the highest priority and DMA channel 1
has the lowest priority.
If the GPDMA is transferring data for the lower priority channel and then the higher priority
channel goes active, it completes the number of transfers delegated to the masterinterface by the lower priority channel before switching over to transfer data for the higher
priority channel. In the worst case this is as large as a one quadword. Channel 1 in the
GPDMA is designed so that it cannot saturate the AHB bus. If it goes active, the GPDMA
relinquishes control of the bus (for a bus cycle), after four transfers of the programmed
size (irrespective of the size of transfer). This enables other AHB masters to access thebus.
It is recommended that memory-to-memory transactions use the low priority channel.
Otherwise other (lower priority) AHB bus masters are prevented from accessing the bus
during GPDMA memory-to-memory transfer.

3.1.12 Interrupt Generation
A combined interrupt output is generated as an OR function of the individual interrupt
requests of the GPDMA, and is connected to the LPC2300 interrupt controller.
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3.1.13 The completion of the DMA transfer indication
The completion of the DMA transfer is indicated by:
1. The transfer count reaching 0 if the GPDMA is performing flow control, OR
2. The peripheral setting the DMA Last Word Request Input (DMACLSREQ) or the DMA
Last Burst Request Input (DMALBREQ) if the peripheral is performing flow control.
According to Table 28–514 “DMA Connections”, SSP0, SSP1 and I2S do not use DMA
Last Word Request Input nor DMA Last Burst Request Input. Therefore there will be no
indication of completion if SSP0, SSP1 and I2S are performing the flow control.

3.2 DMA System Connections
The connection of the GPDMA to the supported peripheral devices depends on the DMA
functions implemented in those peripherals. Table 28–514 shows the DMA Request
numbers used by the supported peripherals.
Table 514. DMA Connections
Peripheral Function DMA Single
Request Input

DMA Burst
Request Input

DMA Last Word DMA Last Burst
Request Input
Request Input

SSP0 Tx

0

-

0

-

SSP0 Rx

1

1

-

-

SSP1 Tx

2

2

-

-

SSP1 Rx

3

3

-

-

SD/MMC44

4

4

I2S channel 0

-

5

-

-

I2S channel 1

-

6

-

-

4. Programmer’s modelThis chapter describes the GPDMA registers and provides details required when
programming the microcontroller. It contains the following sections:• About the programmer’s model.
• Programming the GPDMA.
• Summary of GPDMA registers.
• Register descriptions.
• Address generation.
• Scatter/gather.
• Interrupt requests.
• GPDMA data flow.

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5. About the programmer’s model
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream isconfigured to provide unidirectional DMA transfers for a single source and destination.
The source and destination areas can each be either a memory region or a peripheral
which supports the GPDMA, and must be accessible through AHB1.

6. Programming the GPDMA
The following applies to the registers used in the GPDMA:• Reserved or unused address locations must not be accessed because this can resultin unpredictable behavior of the device.

• Reserved or unused bits of registers must be written as zero, and ignored on read
unless otherwise stated in the relevant text.

• All register bits are reset to a logic 0 by a system or power-on reset unless otherwise
stated in the relevant text.

• Unless otherwise stated in the relevant text, all registers support read and write
accesses. A write updates the contents of a register and a read returns the contentsof the register.

• All registers defined in this document can only be accessed using word reads andword writes (i.e. 32 bit accesses), unless otherwise stated in the relevant text.

6.1 Enabling the GPDMATo enable the GPDMA set the DMA Enable bit in the DMACConfiguration Register(Section 28–8.13 “Configuration Register (DMACConfiguration - 0xFFE0 4030)”.

6.2 Disabling the GPDMA
To disable the GPDMA:
1. Read the DMACEnbldChns Register and ensure that all the DMA channels havebeen disabled. If any channels are active, see Section 28–6.4 “Disabling a DMA
Channel”.
2. Disable the GPDMA by writing 0 to the DMA Enable bit in the DMACConfiguration
Register (Section 28–9.6 “Channel Configuration Registers (DMACC0Configuration 0xFFE0 4110 and DMACC1Configuration - 0xFFE0 4130)”).

6.3 Enabling a DMA Channel
To enable the DMA channel set the Channel Enable bit in the relevant DMA channel
Configuration Register ( Section 28–9.6 “Channel Configuration Registers(DMACC0Configuration - 0xFFE0 4110 and DMACC1Configuration - 0xFFE0 4130)”).
Note: The channel must be fully initialized before it is enabled. Additionally, you must set
the Enable bit of the GPDMA before any channels are enabled.

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6.4 Disabling a DMA Channel
You can disable a DMA channel in the following ways:• Write directly to the Channel Enable bit. Any outstanding data in the FIFOs is lost if
this method is used.

• Use the Active and Halt bits in conjunction with the Channel Enable bit.
• Wait until the transfer completes. The channel is then automatically disabled.
6.5 Disabling a DMA Channel Without Losing Data in the FIFO
To disable a DMA channel without losing data in the FIFO:
1. Set the Halt bit in the relevant channel Configuration Register (Section 28–9.6“Channel Configuration Registers (DMACC0Configuration - 0xFFE0 4110 and
DMACC1Configuration - 0xFFE0 4130)”). This causes any further DMA requests tobe ignored.
2. Poll the Active bit in the relevant channel Configuration Register until it reaches 0.
This bit indicates whether there is any data in the channel which has to be transferred.
3. Clear the Channel Enable bit in the relevant channel Configuration Register.

6.6 Setup a New DMA Transfer
To set up a new DMA transfer:
1. If the channel is not set aside for the DMA transaction:– Read the DMACEnbldChns Register and find out which channels are inactive (seeSection 28–8.8 “Enabled Channel Register (DMACEnbldChns - 0xFFE0 401C)”).
– Choose an inactive channel that has the required priority.
2. Program the GPDMA.

6.7 Disabling a DMA Channel and Losing Data in the FIFO
Clear the relevant Channel Enable bit in the relevant channel Configuration Register(Section 28–9.6 “Channel Configuration Registers (DMACC0Configuration - 0xFFE0 4110
and DMACC1Configuration - 0xFFE0 4130)”). The current AHB transfer, if one is inprogress, completes and the channel is disabled. Any data in the FIFO is lost.

6.8 Halting a DMA Transfer
Set the Halt bit in the relevant DMA channel Configuration Register. The current source
request is serviced. Any further source DMA requests are ignored until the Halt bit iscleared.

6.9 Programming a DMA Channel
To program a DMA channel:
1. Choose a free DMA channel with the priority required. DMA channel 0 has the highest
priority and DMA channel 1 the lowest priority.

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2. Clear any pending interrupts on the channel to be used by writing to the
DMACIntTCClr Register (Section 28–8.3 “Interrupt Terminal Count Clear Register(DMACIntClear - 0xFFE0 4008)”) and DMACIntErrClr Register (Section 28–8.5“Interrupt Error Clear Register (DMACIntErrClr - 0xFFE0 4010)”). The previous
channel operation might have left interrupts active.
3. Write the source address into the DMACCxSrcAddr Register (Section 28–9.1“Channel Source Address Registers (DMACC0SrcAddr - 0xFFE0 4100 and
DMACC1SrcAddr - 0xFFE0 4120)”).
4. Write the destination address into the DMACCxDestAddr Register (Section 28–9.2“Channel Destination Address Registers (DMACC0DestAddr - 0xFFE0 4104 andDMACC1DestAddr - 0xFFE0 4124)”).
5. Write the address of the next Linked List Item (LLI) into the DMACCxLLI Register(Section 28–9.3 “Channel Linked List Item Registers (DMACC0LLI - 0xFFE0 4108
and DMACC1LLI - 0xFFE0 4128)”). If the transfer consists of a single packet of datathen 0 must be written into this register.
6. Write the control information into the DMACCxControl Register (Section 28–9.4“Channel Control Registers (DMACC0Control - 0xFFE0 410C and DMACC0Control 0xFFE0 412C)”).
7. Write the channel configuration information into the DMACCxConfiguration Register(Section 28–9.6 “Channel Configuration Registers (DMACC0Configuration 0xFFE0 4110 and DMACC1Configuration - 0xFFE0 4130)”). If the Enable bit is set
then the DMA channel is automatically enabled.

7. Summary of GPDMA registers
The GPDMA registers are shown in Table 28–515.
Table 515. GPDMA register map
Name

Description

Access Reset Value

AddressDMACIntStatus

Interrupt Status Register

RO

0x0

0xFFE0 4000

DMACIntTCStatus

Interrupt Terminal Count
Status Register

RO

0x0

0xFFE0 4004

DMACIntTCClear

Interrupt Terminal Count Clear WO
Register-

0xFFE0 4008

DMACIntErrorStatus

Interrupt Error Status Register RO

0x0

0xFFE0 400CDMACIntErrClr

Interrupt Error Clear Register

WO-

0xFFE0 4010

DMACRawIntTCStatus

Raw Interrupt Terminal Count
Status Register

RO-

0xFFE0 4014

DMACRawIntErrorStatus Raw Error Interrupt Status
RegisterRO-

0xFFE0 4018

DMACEnbldChns

Enabled Channel Register

RO

0x0

0xFFE0 401CDMACSoftBReq

Software Burst Request
Register

R/W

0x00000xFFE0 4020

DMACSoftSReq

Software Single Request
Register

R/W

0x00000xFFE0 4024

DMACSoftLBReq

Software Last Burst Request
Register

R/W

0x00000xFFE0 4028

General Registers

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Table 515. GPDMA register map
Name

Description

Access Reset Value

AddressDMACSoftLSReq

Software Last Single Request
Register

R/W

0x00000xFFE0 402CDMACConfiguration

Configuration Register

R/W

0x0000 0000 0xFFE0 4030

DMACSync

Synchronization Register

R/W

0x0000DMACC0SrcAddr

Channel 0 Source Address
Register

R/W

0x0000 0000 0xFFE0 4100

DMACC0DestAddr

Channel 0 Destination
Address Register

R/W

0x0000 0000 0xFFE0 4104

DMACC0LLI

Channel 0 Linked List Item
Register

R/W

0x0000 0000 0xFFE0 4108

DMACC0Control

Channel 0 Control Register

R/W

0x0000 0000 0xFFE0 410CDMACC0Configuration

Channel 0 Configuration
Register

R/W

0x00000 [1]DMACC1SrcAddr

Channel 1 Source Address
Register

R/W

0x0000 0000 0xFFE0 4120

DMACC1DestAddr

Channel 1 Destination
Address Register

R/W

0x0000 0000 0xFFE0 4124

DMACC1LLI

Channel 1 Linked List Item
Register

R/W

0x0000 0000 0xFFE0 4128

DMACC1Control

Channel 1 Control Register

R/W

0x0000 0000 0xFFE0 412C

DMACC1Configuration

Channel 1 Configuration
Register

R/W

0x00000 [1]0xFFE0 4034

Channel 0 Registers

0xFFE0 4110

Channel 1 Registers[1]

0xFFE0 4130

Bit [17] is read-only.

8. Register descriptions
This section describes the registers of the GPDMA.

8.1 Interrupt Status Register (DMACIntStatus - 0xFFE0 4000)
The DMACIntStatus Register is read-only and shows the status of the interrupts after
masking. A HIGH bit indicates that a specific DMA channel interrupt request is active. The
request can be generated from either the error or terminal count interrupt requests.
Table 28–516 shows the bit assignments of the DMACIntStatus Register.
Table 516. Interrupt Status register (DMACIntStatus - address 0xFFE0 4000) bit description
Bit

SymbolDescription

Reset
Value

0

IntStatus0

Status of channel 0 interrupts after masking.

0

1

IntStatus1

Status of channel 1 interrupts after masking.

0

31:2

-

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

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8.2 Interrupt Terminal Count Status Register (DMACIntTCStatus 0xFFE0 4004)
The DMACIntTCStatus Register is read-only and indicates the status of the terminal countafter masking. Table 28–517 shows the bit assignments of the DMACIntTCStatus
Register.
Table 517. Interrupt Terminal Count Status register (DMACIntTCStatus - address
0xFFE0 4004) bit description
Bit

SymbolDescription

Reset
Value

0

IntTCStatus0

Terminal count interrupt request status for channel 0.

01IntTCStatus1

Terminal count interrupt request status for channel 1.

0

31:2

-

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

8.3 Interrupt Terminal Count Clear Register (DMACIntClear 0xFFE0 4008)
The DMACIntTCClear Register is write-only and clears a terminal count interrupt request.
When writing to this register, each data bit that is set HIGH causes the corresponding bit
in the status register to be cleared. Data bits that are LOW have no effect on thecorresponding bit in the register. Table 28–518 shows the bit assignments of the
DMACIntTCClear Register.
Table 518. Interrupt Terminal Count Clear register (DMACIntClear - address 0xFFE0 4008) bit
description
Bit

SymbolDescription

Reset
Value

0

IntTCClear0

Writing a 1 clears the terminal count interrupt request forchannel 0 (IntTCStatus0).

-

1

IntTCClear1

Writing a 1 clears the terminal count interrupt request forchannel 1 (IntTCStatus1).

-

31:2

-

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

8.4 Interrupt Error Status Register (DMACIntErrorStatus - 0xFFE0 400C)
The DMACIntErrorStatus Register is read-only and indicates the status of the error
request after masking. Table 28–519 shows the bit assignments of the
DMACIntErrorStatus Register.
Table 519. Interrupt Error Status register (DMACIntErrorStatus - address 0xFFE0 400C) bit
description
Bit

SymbolDescription

Reset
Value

0

IntErrorStatus0

Interrupt error status for channel 0.

0x0

1IntErrorStatus1

Interrupt error status for channel 1.

0x0

31:2

-

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

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8.5 Interrupt Error Clear Register (DMACIntErrClr - 0xFFE0 4010)
The DMACIntErrClr Register is write-only and clears the error interrupt requests. When
writing to this register, each data bit that is HIGH causes the corresponding bit in thestatus register to be cleared. Data bits that are LOW have no effect on the corresponding
bit in the register. Table 28–520 shows the bit assignments of the DMACIntErrClr Register.
Table 520. Interrupt Error Clear register (DMACIntErrClr - address 0xFFE0 4010) bit
description
Bit

SymbolDescription

Reset
Value

0

IntErrClr0

Writing a 1 clears the error interrupt request for channel 0(IntErrorStatus0).

-1

IntErrClr1

Writing a 1 clears the error interrupt request for channel 1(IntErrorStatus1).

-

31:2

-

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

8.6 Raw Interrupt Terminal Count Status Register (DMACRawIntTCStatus- 0xFFE0 4014)
The DMACRawIntTCStatus Register is read-only and indicates which DMA channel isrequesting a transfer complete (terminal count interrupt) prior to masking. A HIGH bit
indicates that the terminal count interrupt request is active prior to masking. Table 28–521
shows the bit assignments of the DMACRawIntTCStatus Register.
Table 521. Raw Interrupt Terminal Count Status register (DMACRawIntTCStatus - address
0xFFE0 4014) bit description
Bit

SymbolDescription

Reset
Value

0

RawIntTCStatus0 Status of the terminal count interrupt for channel 0 prior tomasking.

-

1

RawIntTCStatus1 Status of the terminal count interrupt for channel 1 prior tomasking.

-

31:2

-

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

8.7 Raw Error Interrupt Status Register (DMACRawIntErrorStatus 0xFFE0 4018)
The DMACRawIntErrorStatus Register is read-only and indicates which DMA channel isrequesting an error interrupt prior to masking. A HIGH bit indicates that the error interrupt
request is active prior to masking. Table 28–522 shows the bit assignments of register ofthe DMACRawIntErrorStatus Register.

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Table 522. Raw Error Interrupt Status register (DMACRawIntErrorStatus - address
0xFFE0 4018) bit description
Bit

SymbolDescription

Reset
Value

0

RawIntErrorStatus0 Status of the error interrupt for channel 0 prior to masking.

-

1

RawIntErrorStatus1 Status of the error interrupt for channel 1 prior to masking.

-

31:2

-

NA

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

8.8 Enabled Channel Register (DMACEnbldChns - 0xFFE0 401C)
The DMACEnbldChns Register is read-only and indicates which DMA channels areenabled, as indicated by the Enable bit in the DMACCxConfiguration Register. A HIGH bit
indicates that a DMA channel is enabled. A bit is cleared on completion of the DMA
transfer. Table 28–523 shows the bit assignments of the DMACEnbldChns Register.
Table 523. Enabled Channel register (DMACEnbldChns - address 0xFFE0 401C) bit
description
Bit

SymbolDescription

Reset
Value

0

EnabledChannels0 Enable status for Channel 0.

1

EnabledChannels1 Enable status for Channel 1.

0

31:2

-

NA

0

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

8.9 Software Burst Request Register (DMACSoftBReq - 0xFFE0 4020)
The DMACSoftBReq Register is read/write and enables DMA burst requests to begenerated by software. A DMA request can be generated for each source by writing a 1 tothe corresponding register bit. A register bit is cleared when the transaction has
completed. Writing 0 to this register has no effect. Reading the register indicates whichsources are requesting DMA burst transfers. A request can be generated from either aperipheral or the software request register. Table 28–524 shows the bit assignments of the
DMACSoftBReq Register.
Table 524. Software Burst Request register (DMACSoftBReq - address 0xFFE0 4020) bit
description
Bit

SymbolDescription

Reset
Value

0

SoftBReqSSP0Tx

Software burst request flag for SSP0 Tx.

01

SoftBReqSSP0Rx

Software burst request flag for SSP0 Rx.

02

SoftBReqSSP1Tx

Software burst request flag for SSP1 Tx.

0

3

SoftBReqSSP1Rx

Software burst request flag for SSP1 Rx.

0

4

SoftBReqSDMMC

Software burst request flag for SD/MMC.

0

31:5

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

Note: It is recommended that software and hardware peripheral requests are not used at
the same time.

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8.10 Software Single Request Register (DMACSoftSReq - 0xFFE0 4024)
The DMACSoftSReq Register is read/write and enables DMA single requests to begenerated by software. A DMA request can be generated for each source by writing a 1 tothe corresponding register bit. A register bit is cleared when the transaction has
completed. Writing 0 to this register has no effect. Reading the register indicates whichsources are requesting single DMA transfers. A request can be generated from either aperipheral or the software request register. Table 28–525 shows the bit assignments of the
DMACSoftSReq Register.
Table 525. Software Single Request register (DMACSoftSReq - address 0xFFE0 4024) bit
description
Bit

SymbolDescription

Reset
Value

0

SoftReqSSP0Tx

Single software request flag for SSP0 Tx.

01

SoftReqSSP0Rx

Single software request flag for SSP0 Rx.

02

SoftReqSSP1Tx

Single software request flag for SSP1 Tx.

0

3

SoftReqSSP1Rx

Single software request flag for SSP1 Rx.

0

4

SoftReqSDMMC

Single software request flag for SD/MMC.

05SoftSReqI2S0

Single software request flag for i2S0.

0

6

SoftSReqI2S1Single software request flag for i2S1.

0

31:7

-

Reserved, user software should not write ones to reserved NA
bits. The value read from a reserved bit is not defined.

8.11 Software Last Burst Request Register (DMACSoftLBreq 0xFFE0 4028)
The DMACSoftLBReq Register is read/write and enables DMA last burst requests to begenerated by software. A DMA request can be generated for each source by writing a 1 tothe corresponding register bit. A register bit is cleared when the transaction has
completed. Writing 0 to this register has no effect. Reading the register indicates whichsources are requesting last burst DMA transfers. A request can be generated from either
a peripheral or the software request register. Table 28–526 shows the bit assignments of
the DMACSoftLBReq Register.
Table 526. Software Last Burst Request register (DMACSoftLBReq - address 0xFFE0 4028)
bit description
Bit

SymbolDescription

Reset
Value

3:0

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

4

SoftLBReqSDMMC Software last burst request flags for SD/MMC.

0

31:5

-

NA

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

8.12 Software Last Single Request Register (DMACSoftLSReq 0xFFE0 402C)
The DMACSoftLSReq Register is read/write and enables DMA last single requests to begenerated by software. A DMA request can be generated for each source by writing a 1 tothe corresponding register bit. A register bit is cleared when the transaction has
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completed. Writing 0 to this register has no effect. Reading the register indicates whichsources are requesting last single DMA transfers. A request can be generated from either
a peripheral or the software request register. Table 28–527 shows the bit assignments of
the DMACSoftLSReq Register.
Table 527. Software Last Single Request register (DMACSoftLSReq - address 0xFFE0 402C)
bit description
Bit

SymbolDescription

Reset
Value

3:0

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

4

SoftLSReqSDMMC

Software last single request flags for SD/MMC.

0

31:5

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

8.13 Configuration Register (DMACConfiguration - 0xFFE0 4030)
The DMACConfiguration Register is read/write and configures the operation of the
GPDMA. The endianness of the AHB master interface can be altered by writing to the M
bit of this register. The AHB master interface is set to little-endian mode on reset.
Table 28–528 shows the bit assignments of the DMACConfiguration Register.
Table 528. Configuration register (DMACConfiguration - address 0xFFE0 4030) bit
description
Bit

Symbol Value

Description

Reset
Value

0

E

GPDMA enable:

0

1

31:2

0

Disabled. Disabling the GPDMA reduces power consumption.

1

Enabled.

M-

AHB Master endianness configuration:00Little-endian mode.

1

Big-endian mode.

-

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

8.14 Synchronization Register (DMACSync - 0xFFE0 4034)
The DMACSync Register is read/write and enables or disables synchronization logic for
the DMA request signals. The DMA request signals consist of the DMACBREQ[15:0],
DMACSREQ[15:0], DMACLBREQ[15:0], and DMACLSREQ[15:0]. A bit set to 0 enables
the synchronization logic for a particular group of DMA requests. A bit set to 1 disables thesynchronization logic for a particular group of DMA requests. This register is reset to 0,
synchronization logic enabled.
Table 28–529 shows the bit assignments of the DMACSync Register.

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Table 529. Synchronization register (DMACSync - address 0xFFE0 4034) bit description
Bit

SymbolDescription

15:0

DMACSync

DMA synchronization logic for DMA request signals enabled or 0x0000
disabled. A LOW bit indicates that the synchronization logic for
the DMACBREQ[15:0], DMACSREQ[15:0],
DMACLBREQ[15:0], and DMACLSREQ[15:0] request signals
is enabled. A HIGH bit indicates that the synchronization logic
is disabled.

31:16 -

Reset
Value

Reserved, user software should not write ones to reserved bits. NA
The value read from a reserved bit is not defined.

9. Channel registers
The channel registers are used to program the two DMA channels. These registers
consist of:• Two DMACCxSrcAddr Registers• Two DMACCxDestAddr Registers• Two DMACCxLLI Registers• Two DMACCxControl Registers• Two DMACCxConfiguration Registers
When performing scatter/gather DMA the first four registers are automatically updated.

9.1 Channel Source Address Registers (DMACC0SrcAddr - 0xFFE0 4100
and DMACC1SrcAddr - 0xFFE0 4120)
The two read/write DMACCxSrcAddr Registers contain the current source address(byte-aligned) of the data to be transferred. Each register is programmed directly bysoftware before the appropriate channel is enabled. When the DMA channel is enabled
this register is updated:• As the source address is incremented.
• By following the linked list when a complete packet of data has been transferred.
Reading the register when the channel is active does not provide useful information. Thisis because by the time software has processed the value read, the channel might haveprogressed. It is intended to be read only when the channel has stopped, in which case itshows the source address of the last item read.
Note: The source and destination addresses must be aligned to the source anddestination widths.
Table 28–530 shows the bit assignments of the DMACCxSrcAddr Registers.
Table 530. Channel Source Address registers (DMACC0SrcAddr - address 0xFFE0 4100 and
DMACC1SrcAddr - address 0xFFE0 4120) bit description
Bit

SymbolDescription

Reset Value

31:0

SrcAddrDMA source address.

0x0000 0000

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9.2 Channel Destination Address Registers (DMACC0DestAddr 0xFFE0 4104 and DMACC1DestAddr - 0xFFE0 4124)
The two read/write DMACCxDestAddr Registers contain the current destination address(byte-aligned) of the data to be transferred. Each register is programmed directly bysoftware before the channel is enabled. When the DMA channel is enabled the register is
updated as the destination address is incremented and by following the linked list when acomplete packet of data has been transferred. Reading the register when the channel isactive does not provide useful information. This is because by the time that software has
processed the value read, the channel might have progressed. It is intended to be read
only when a channel has stopped, in which case it shows the destination address of thelast item read. Table 28–531 shows the bit assignments of the DMACCxDestAddr
Register.
Table 531. Channel Destination Address registers (DMACC0DestAddr - address
0xFFE0 4104 and DMACC1DestAddr - address 0xFFE0 4124) bit description
Bit

SymbolDescription

Reset Value

31:0

DestAddr

DMA destination address

0x0000 0000

9.3 Channel Linked List Item Registers (DMACC0LLI - 0xFFE0 4108 and
DMACC1LLI - 0xFFE0 4128)
The two read/write DMACCxLLI Registers contain a word-aligned address of the next
Linked List Item (LLI). If the LLI is 0, then the current LLI is the last in the chain, and the
DMA channel is disabled when all DMA transfers associated with it are completed.
Note: Programming this register when the DMA channel is enabled has unpredictableside effects.
Table 28–532 shows the bit assignments of the DMACCxLLI Register.
Table 532. Channel Linked List Item registers (DMACC0LLI - address 0xFFE0 4108 and
DMACC1LLI - address 0xFFE0 4128) bit description
Bit

SymbolDescription

Reset Value0

Reserved Reserved, read as zero, do not modify.

NA

1

R

Reserved, and must be written as 0, masked on read.

0

31:2

LLI

Linked list item. Bits [31:2] of the address for the next LLI.
Address bits [1:0] are 0.

0Note: To make loading the LLIs more efficient for some systems, the LLI data structures
can be made four-word aligned.

9.4 Channel Control Registers (DMACC0Control - 0xFFE0 410C andDMACC0Control - 0xFFE0 412C)
The two read/write DMACCxControl Registers contain DMA channel control informationsuch as the transfer size, burst size, and transfer width. Each register is programmed
directly by software before the DMA channel is enabled. When the channel is enabled theregister is updated by following the linked list when a complete packet of data has beentransferred. Reading the register while the channel is active does not give useful
information. This is because by the time software has processed the value read, thechannel might have progressed. It is intended to be read only when a channel has
stopped. Table 28–533 shows the bit assignments of the DMACCxControl Register.
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Table 533. Channel Control registers (DMACC0Control - address 0xFFE0 410C andDMACC1Control - address 0xFFE0 412C) bit description
Bit

Symbol11:0

TransferSize Transfer size. A write to this field sets the size of the transfer 0
when the GPDMA is the flow controller.A read from this fieldindicates the number of transfers completed on thedestination bus. Reading the register when the channel isactive does not give useful information because by the timethat the software has processed the value read, the channel
might have progressed. It is intended to be used only when achannel is enabled and then disabled.The transfer size value
is not used if the GPDMA is not the flow controller.

Description

Reset Value

14:12 SBSize

Source burst size. Indicates the number of transfers thatmake up a source burst. This value must be set to the burst
size of the source peripheral, or if the source is memory, tothe memory boundary size. The burst size is the amount ofdata that is transferred when the DMACBREQ signal goesactive in the source peripheral.

17:15 DBsize

Destination burst size. Indicates the number of transfers that 0
make up a destination burst transfer request. This value must
be set to the burst size of the destination peripheral, or if thedestination is memory, to the memory boundary size. The
burst size is the amount of data that is transferred when the
DMACBREQ signal goes active in the destination peripheral.

20:18 SWidth

Source transfer width. Transfers wider than the AHB masterbus width are illegal.The source and destination widths canbe different from each other. The hardware automatically
packs and unpacks the data as required.

0

23:21 DWidth

Destination transfer width. Transfers wider than the AHB
master bus width are not supported.The source anddestination widths can be different from each other. The
hardware automatically packs and unpacks the data as
required.

0

25:24 -

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

NA

26

SI

Source increment. When set the source address isincremented after each transfer.

0

27

DI

Destination increment. When set the destination address isincremented after each transfer.

030:28 Prot

Protection.

031

Terminal count interrupt enable bit. It controls whether the0current LLI is expected to trigger the terminal count interrupt.

I

0

Table 28–534 shows the value of the 3 bit DBSize or SBSize fields and the corresponding
burst sizes.
Table 534. Source or destination burst size
Bit value of DBSize or SBSize

Source or distention burst transfer request size

000

1

001

4

010

8

011

16

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Table 534. Source or destination burst size
Bit value of DBSize or SBSize

Source or distention burst transfer request size

100

32

101

64

110

128

111

256

Table 28–535 shows the value of the 3 bit SWidth or DWidth fields and the correspondingtransfer width.
Table 535. Source or destination transfer width
Bit value of DBWidth or SBWidth

Source or distention burst transfer request size

000

Byte (8 bit)

001

Halfword (16 bit)010

Word (32 bit)

011 and 1xxx

Reserved

9.5 Protection and Access Information
AHB access information is provided to the source and destination peripherals when atransfer occurs. The transfer information is provided by programming the DMA channel(the Prot bit of the DMACCxControl Register, and the Lock bit of the
DMACCxConfiguration Register). These bits are programmed by software andperipherals can use this information if necessary. Three bits of information are provided,and Table 28–536 shows the purpose of the three protection bits.
Table 536. Protection bits
DMACC1Control Value
Bit
28

Description

Reset
Value

Privileged or User. This bit controls the AHB HPROT[1] signal. 0
Indicates that the access is in User, or privileged mode:0

User mode.

1

Privileged mode.

29

Bufferable or not bufferable. This bit indicates that the access 0
is bufferable. This bit can, for example, be used to indicate toan AMBA bridge that the read can complete in zero wait stateson the source bus without waiting for it to arbitrate for thedestination bus and for the slave to accept the data. This bit
controls the AHB HPROT[2] signal.
Indicates that the access is bufferable, or not bufferable:0

Not bufferable.

1

Bufferable.

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Table 536. Protection bits
DMACC1Control Value
Bit

Description

Reset
Value

30

Cacheable or not cacheable. This indicates that the access is 0
cacheable. This bit can, for example, be used to indicate to an
AMBA bridge that when it saw the first read of a burst of eight it
can transfer the whole burst of eight reads on the destinationbus, rather than pass the transactions through one at a time.
This bit controls the AHB HPROT[3] signal.
Indicates that the access is cacheable or not cacheable:0

Not cacheable.

1

Cacheable.

9.6 Channel Configuration Registers (DMACC0Configuration 0xFFE0 4110 and DMACC1Configuration - 0xFFE0 4130)
The two DMACCxConfiguration Registers are read/write with the exception of bit[17]which is read-only. Used these to configure the DMA channel. The registers are not
updated when a new LLI is requested. Table 28–537 shows the bit assignments of the
DMACCxConfiguration Register.
Table 537. Channel Configuration registers (DMACC0Configuration - address 0xFFE0 4110 and
DMACC1Configuration - address 0xFFE0 4130) bit description
Bit

Symbol0

E

Value Description

Reset
Value

The Channel Enable bit status can also be found by reading the DMACEnbldChns
Register.

0

A channel is enabled by setting this bit.
A channel can be disabled by clearing the Enable bit. This causes the current AHB
transfer (if one is in progress) to complete and the channel is then disabled. Anydata in the FIFO of the relevant channel is lost. Restarting the channel by setting the
Channel Enable bit has unpredictable effects and the channel must be fully
re-initialized.
The channel is also disabled, and Channel Enable bit cleared, when the last LLI isreached or if a channel error is encountered.
If a channel has to be disabled without losing data in the FIFO the Halt bit must be
set so that further DMA requests are ignored. The Active bit must then be polled
until it reaches 0, indicating that there is no data left in the FIFO. Finally the Channel
Enable bit can be cleared.
Channel enable -- reading this bit indicates whether a channel is currently enabledor disabled:0

Channel disabled.

1

Channel enabled.

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Table 537. Channel Configuration registers (DMACC0Configuration - address 0xFFE0 4110 and
DMACC1Configuration - address 0xFFE0 4130) bit description
Bit

SymbolValue Description

4:1

SrcPeripheral

5

-

9:6

DestPeriphera
l

10

-

Reset
Value

Source peripheral. This value selects the DMA source request peripheral.This fieldis ignored if the source of the transfer is from memory.

0

0000

SSP0 Tx

0001

SSP0 Rx

0010

SSP1 Tx

0011

SSP1 Rx

0100

SD/MMC

0101

I2S channel 00110

I2S channel 1

0111
or
1xxx

These values are reserved and should not be used.

-

Reserved, do not modify, masked on read.

NA

Destination peripheral. This value selects the DMA destination request peripheral.
This field is ignored if the destination of the transfer is to memory. See the
SrcPeripheral symbol description for values.

0

Reserved, do not modify, masked on read.

NA

13:11 FlowCntrl

Flow control and transfer type. This value indicates the flow controller and transfer
type. The flow controller can be the GPDMA, the source peripheral, or thedestination peripheral.The transfer type can be memory-to-memory,
memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral.

0

14

IE

Interrupt error mask. When cleared this bit masks out the error interrupt of therelevant channel.

0

15

ITC

Terminal count interrupt mask. When cleared this bit masks out the terminal countinterrupt of the relevant channel.

0

16

L

Lock. When set, this bit enables locked transfers.

0

17

A

Active. This value can be used with the Halt and Channel Enable bits to cleanly
disable a DMA channel. Writing to this bit has no effect.

18

-

0

There is no data in the FIFO of the channel.

1

The channel FIFO has data.

H

31:19 -

Halt. The contents of the channel FIFO are drained. This value can be used with the 0
Active and Channel Enable bits to cleanly disable a DMA channel.
0

Enable DMA requests.

1

Ignore further source DMA requests.
Reserved, do not modify, masked on read.

NA

9.7 Lock control
Set the lock bit by programming bit 16 in the DMACCxConfiguration Register.
When a burst occurs, the AHB arbiter must not de-grant the master during the burst until
the lock is deasserted. The GPDMA can be locked for a a single burst such as a longsource fetch burst or a long destination drain burst. The GPDMA does not usually assert
the lock continuously for a source fetch burst followed by a destination drain burst.

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There are situations when the GPDMA asserts the lock for source transfers followed bydestination transfers. This is possible when internal conditions in the GPDMA permit it toperform a source fetch followed by a destination drain back-to-back.

9.8 Flow control and transfer type
Table 28–538 lists the bit values of the three flow control and transfer type bits.
Table 538. Flow control and transfer type bits
Bit Value Transfer Type

Controller

000

Memory to memory.

DMA

001

Memory to peripheral.

DMA

010

Peripheral to memory.

DMA

011

Source peripheral to destination peripheral.

DMA

100

Source peripheral to destination peripheral.

Destination peripheral.

101

Memory to peripheral.

Peripheral.

110

Peripheral to memory.

Peripheral.

111

Source peripheral to destination peripheral.

Source peripheral.

10. Address generation
Address generation can be either incrementing or non-incrementing (address wrapping is
not supported). Bursts do not cross the 1 kB address boundary.

11. Scatter/Gather
Scatter/gather is supported through the use of linked lists. This means that the source anddestination areas do not have to occupy contiguous areas in memory. Where
scatter/gather is not required the DMACCxLLI Register must be set to 0.
The source and destination data areas are defined by a series of linked lists. Each Linked
List Item (LLI) controls the transfer of one block of data, and then optionally loads another
LLI to continue the DMA operation, or stops the DMA stream. The first LLI is programmed
into the GPDMA.
The data to be transferred described by a LLI (referred to as the packet of data) usuallyrequires one or more DMA bursts (to each of the source and destination).

11.1 Linked List Items
A Linked List Item (LLI) consists of four words. These words are organized in the following
order:
1. DMACCxSrcAddr.
2. DMACCxDestAddr.
3. DMACCxLLI.
4. DMACCxControl.

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Note: The DMACCxConfiguration DMA channel Configuration Register is not part of thelinked list item.

11.2 Programming the GPDMA for scatter/gather DMA
To program the GPDMA for scatter/gather DMA:
1. Write the LLIs for the complete DMA transfer to memory. Each linked list item contains
four words:– Source address.
– Destination address.
– Pointer to next LLI.
– Control word.
The last LLI has its linked list word pointer set to 0. The LLIs must be stored in thememory where the GPDMA has access to (i.e. AHB1 SRAM and external memory).
2. Choose a free DMA channel with the priority required. DMA channel 0 has the highest
priority and DMA channel 1 the lowest priority.
3. Write the first linked list item, previously written to memory, to the relevant channel in
the GPDMA.
4. Write the channel configuration information to the channel Configuration Register andset the Channel Enable bit. The GPDMA then transfers the first and then subsequent
packets of data as each linked list item is loaded.
5. An interrupt can be generated at the end of each LLI depending on the Terminal
Count bit in the DMACCxControl Register. If this bit is set an interrupt is generated at
the end of the relevant LLI. The interrupt request must then be serviced and therelevant bit in the DMACIntTCClear Register must be set to clear the interrupt.

11.3 Example of scatter/gather DMA
See Figure 28–111 for an example of an LLI. A rectangle of memory has to be transferred
to a peripheral. The addresses of each line of data are given, in hexadecimal, at theleft-hand side of the figure. The LLIs describing the transfer are to be stored contiguously
from address 0x20000.

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0x--200

0x–E000x0A--0x0B--0x0C--0x0D--0x0E--0x0F--0x10--0x11---

Fig 111.LLI example

The first LLI, stored at 0x20000, defines the first block of data to be transferred, which isthe data stored between addresses 0x0A200 and 0x0AE00:• Source start address 0x0A200.
• Destination address set to the destination peripheral address.
• Transfer width, word (32 bit).
• Transfer size, 3 072 bytes (0XC00).
• Source and destination burst sizes, 16 transfers.
• Next LLI address, 0x20010.
The second LLI, stored at 0x20010 , describes the next block of data to be transferred:• Source start address 0x0B200.
• Destination address set to the destination peripheral address.
• Transfer width, word (32 bit).
• Transfer size, 3 072 bytes (0xC00).
• Source and destination burst sizes, 16 transfers.
• Next LLI address, 0x20020.
A chain of descriptors is built up, each one pointing to the next in the series. To initialize
the DMA stream, the first LLI, 0x20000, is programmed into the GPDMA. When the first
packet of data has been transferred the next LLI is automatically loaded.
The final LLI is stored at 0x20070 and contains:• Source start address 0x11200.
• Destination address set to the destination peripheral address.
• Transfer width, word (32 bit).
• Transfer size, 3 072 bytes (0xC00).
• Source and destination burst sizes, 16 transfers.
• Next LLI address, 0x0.
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Because the next LLI address is set to zero, this is the last descriptor, and the DMA
channel is disabled after transferring the last item of data. The channel is probably set togenerate an interrupt at this point to indicate to the ARM processor that the channel canbe reprogrammed.

12. Interrupt requests
Interrupt requests can be generated when an AHB error is encountered, or at the end of atransfer (terminal count) after all the data corresponding to the current LLI has beentransferred to the destination. The interrupts can be masked by programming bits in therelevant DMACCxControl and DMACCxConfiguration Channel Registers. Interrupt status
registers are provided which group the interrupt requests from all the DMA channels prior
to interrupt masking (DMACRawIntTCStatus and DMACRawIntErrorStatus), and after
interrupt masking (DMACIntTCStatus and DMACIntErrorStatus). The DMACIntStatus
Register combines both the DMACIntTCStatus and DMACIntErrorStatus requests into asingle register to enable the source of an interrupt to be quickly found. Writing to the
DMACIntTCClear or the DMACIntErrClr Registers with a bit set HIGH enables selective
clearing of interrupts.

12.1 Hardware interrupt sequence flow
When a DMA interrupt request occurs, the Interrupt Service Routine needs to:
1. Read the DMACIntStatus Register to determine which channel generated theinterrupt. If more than one request is active it is recommended that the highest priority
channels be checked first.
2. Read the DMACIntTCStatus Register to determine whether the interrupt was
generated due to the end of the transfer (terminal count). A HIGH bit indicates that thetransfer completed.
3. Read the DMACIntErrorStatus Register to determine whether the interrupt was
generated due to an error occurring. A HIGH bit indicates that an error occurred.
4. Service the interrupt request.
5. For a terminal count interrupt write a 1 to the relevant bit of the DMACIntTCClr
Register. For an error interrupt write a 1 to the relevant bit of the DMACIntErrClr
Register to clear the interrupt request.

12.2 Interrupt polling sequence flow
Used when the GPDMA interrupt request signal is either masked out, disabled in theinterrupt controller or disabled in the processor. When polling the GPDMA, you must:
1. Read the DMACIntStatus Register. If none of the bits are HIGH repeat this step,otherwise go to step 2. If more than one request is active it is recommended that thehighest priority channels be checked first.
2. Read the DMACIntTCStatus Register to determine whether the interrupt was
generated due to the end of the transfer (terminal count). A HIGH bit indicates that thetransfer completed.
3. Service the interrupt request.

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4. For a terminal count interrupt write a 1 to the relevant bit of the DMACIntTCClr
Register. For an error interrupt write a 1 to the relevant bit of the DMACIntErrClr
Register to clear the interrupt request.

13. GPDMA data flow
This section describes the GPDMA data flow sequences for the four allowed transfer
types:• Memory-to-peripheral.
• Peripheral-to-memory.
• Memory-to-memory.
• Peripheral-to-peripheral.
Each transfer type can have either the peripheral or the GPDMA as the flow controller sothere are eight possible control scenarios.
Table 28–539 indicates the request signals used for each type of transfer.
Table 539. DMA request signal usage
Transfer Direction

Request Generator

Flow Controller

Memory-to-peripheral

Peripheral

GPDMA

Memory-to-peripheral

Peripheral

Peripheral

Peripheral-to-memory

Peripheral

GPDMA

Peripheral-to-memory

Peripheral

Peripheral

Memory-to-memory

GPDMA

GPDMA

Source peripheral to destination
peripheral

Source peripheral anddestination peripheral

Source peripheral

Source peripheral to destination
peripheral

Source peripheral anddestination peripheral

Destination peripheral

Source peripheral to destination
peripheral

Source peripheral anddestination peripheral

GPDMA

13.1 Peripheral-to-memory, or Memory-to-peripheral DMA Flow
For a peripheral-to-memory or memory-to-peripheral DMA flow the following sequenceoccurs:1. Program and enable the DMA channel.
2. Wait for a DMA request.
3. The GPDMA starts transferring data when:– The DMA request goes active.
– The DMA stream has the highest pending priority.
– The GPDMA is the bus master of the AHB bus.
4. If an error occurs while transferring the data, an error interrupt is generated anddisables the DMA stream, and the flow sequence ends.
5. Decrement the transfer count if the GPDMA is performing the flow control.
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6. If the transfer has completed (indicated by the transfer count reaching 0 if the GPDMA
is performing flow control, or by the peripheral sending a DMA request if theperipheral is performing flow control):– The GPDMA responds with a DMA acknowledge.
– The terminal count interrupt is generated (this interrupt can be masked).
– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr,
DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go back tostep 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow
sequence ends.

13.2 Peripheral-to-peripheral DMA Flow
For a peripheral-to-peripheral DMA flow the following sequence occurs:
1. Program and enable the DMA channel.
2. Wait for a source DMA request.
3. The GPDMA starts transferring data when:– The DMA request goes active.
– The DMA stream has the highest pending priority.
– The GPDMA is the bus master of the AHB bus.
4. If an error occurs while transferring the data an error interrupt is generated, thenfinishes.
5. Decrement the transfer count if the GPDMA is performing the flow control.
6. If the transfer has completed (indicated by the transfer count reaching 0 if the GPDMA
is performing flow control, or by the peripheral sending a DMA request if theperipheral is performing flow control):– The GPDMA responds with a DMA acknowledge to the source peripheral.
– Further source DMA requests are ignored.
7. When the destination DMA request goes active and there is data in the GPDMA FIFO,
transfer data into the destination peripheral.
8. If an error occurs while transferring the data, an error interrupt is generated anddisables the DMA stream, and the flow sequence ends.
9. If the transfer has completed it is indicated by the transfer count reaching 0 if the
GPDMA is performing flow control, or by the sending a DMA request if the peripheral
is performing flow control. The following happens:– The GPDMA responds with a DMA acknowledge to the destination peripheral.
– The terminal count interrupt is generated (this interrupt can be masked).
– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr,
DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go to backto step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow
sequence ends.

13.3 Memory-to-memory DMA Flow
For a memory-to-memory DMA flow the following sequence occurs:

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1. Program and enable the DMA channel.
2. Transfer data whenever the DMA channel has the highest pending priority and the
GPDMA gains mastership of the AHB bus.
3. If an error occurs while transferring the data generate an error interrupt and disable
the DMA stream.
4. Decrement the transfer count.
5. If the count has reached zero:– Generate a terminal count interrupt (the interrupt can be masked).
– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr,
DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go to backto step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow
sequence ends.
Note: Memory-to-memory transfers should be programmed with a low channel priority,
otherwise other DMA channels cannot access the bus until the memory-to-memorytransfer has finished, or other AHB masters cannot perform any transaction.

14. Flow control
The peripheral that controls the length of the packet is known as the flow controller. The
flow controller is usually the GPDMA where the packet length is programmed by software
before the DMA channel is enabled. If the packet length is unknown when the DMA
channel is enabled, either the source or destination peripherals can be used as the flow
controller.
For simple or low-performance peripherals that know the packet length (that is, when the
peripheral is the flow controller), a simple way to indicate that a transaction has completed
is for the peripheral to generate an interrupt and enable the processor to reprogram the
DMA channel.
The transfer size value (in the DMACCxControl register) is ignored if a peripheral isconfigured as the flow controller.
When the DMA is transferred:
1. The GPDMA issues an acknowledge to the peripheral in order to indicate that thetransfer has finished.
2. A TC interrupt is generated, if enabled.
3. The GPDMA moves on to the next LLI.

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User manual

1. Features• No target resources are required by the software debugger in order to start the
debugging session.

• Allows the software debugger to talk via a JTAG (Joint Test Action Group) port directly
to the core.

• Inserts instructions directly in to the ARM7TDMI-S core.
• The ARM7TDMI-S core or the System state can be examined, saved or changed
depending on the type of instruction inserted.

• Allows instructions to execute at a slow debug speed or at a fast system speed.

2. Applications
The EmbeddedICE logic provides on-chip debug support. The debugging of the target
system requires a host computer running the debugger software and an EmbeddedICE
protocol convertor. EmbeddedICE protocol convertor converts the Remote Debug
Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present
on the target system.

3. Description
The ARM7TDMI-S Debug Architecture uses the existing JTAG3 port as a method ofaccessing the core. The scan chains that are around the core for production test arereused in the debug state to capture information from the databus and to insert new
information into the core or the memory. There are two JTAG-style scan chains within the
ARM7TDMI-S. A JTAG-style Test Access Port Controller controls the scan chains. In
addition to the scan chains, the debug architecture uses EmbeddedICE logic which
resides on chip with the ARM7TDMI-S core. The EmbeddedICE has its own scan chainthat is used to insert watchpoints and breakpoints for the ARM7TDMI-S core. The
EmbeddedICE logic consists of two real time watchpoint registers, together with a control
and status register. One or both of the watchpoint registers can be programmed to halt the
ARM7TDMI-S core. Execution is halted when a match occurs between the values
programmed into the EmbeddedICE logic and the values currently appearing on theaddress bus, databus and some control signals. Any bit can be masked so that its value
does not affect the comparison. Either watchpoint register can be configured as awatchpoint (i.e. on a data access) or a break point (i.e. on an instruction fetch). The
watchpoints and breakpoints can be combined such that:• The conditions on both watchpoints must be satisfied before the ARM7TDMI core is
stopped. The CHAIN functionality requires two consecutive conditions to be satisfied
before the core is halted. An example of this would be to set the first breakpoint to

3.For more details refer to IEEE Standard 1149.1 - 1990 Standard Test Access Port and Boundary Scan Architecture.
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Chapter 29: LPC2300 Embedded ICE

trigger on an access to a peripheral and the second to trigger on the code segmentthat performs the task switching. Therefore when the breakpoints trigger the
information regarding which task has switched out will be ready for examination.

• The watchpoints can be configured such that a range of addresses are enabled forthe watchpoints to be active. The RANGE function allows the breakpoints to be
combined such that a breakpoint is to occur if an access occurs in the bottom
256 bytes of memory but not in the bottom 32 bytes.
The ARM7TDMI-S core has a Debug Communication Channel function in-built. The
debug communication channel allows a program running on the target to communicate
with the host debugger or another separate host without stopping the program flow oreven entering the debug state. The debug communication channel is accessed as aco-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data andcontrol registers are mapped in to addresses in the EmbeddedICE logic.

• For more details refer to IEEE Standard 1149.1 - 1990 Standard Test Access Port andBoundary Scan Architecture.

4. Pin description
Table 540. EmbeddedICE pin description
Pin Name

Type

Description

TMS

Input

Test Mode Select. The TMS pin selects the next state in the TAP statemachine.

TCK

Input

Test Clock. This allows shifting of the data in, on the TMS and TDI pins. It
is a positive edgetriggered clock with the TMS and TCK signals thatdefine the internal state of the device.

TDI

Input

Test Data In. This is the serial data input for the shift register.

TDO

Output

Test Data Output. This is the serial data output from the shift register.
Data is shifted out of the device on the negative edge of the TCK signal.

nTRST

Input

Test Reset. The nTRST pin can be used to reset the test logic within theEmbeddedICE logic.

RTCK

OutputReturned Test Clock. Extra signal added to the JTAG port. Required fordesigns based on ARM7TDMI-S processor core. Multi-ICE (Development
system from ARM) uses this signal to maintain synchronization withtargets having slow or widely varying clock frequency. For details refer to"Multi-ICE System Design considerations Application Note 72 (ARM DAI
0072A)".
Board designers may need to connect a weak bias resistor to this pin as
described below.

5. JTAG function select
The JTAG port may be used either for debug or for boundary scan. The state of the
DBGEN pin determines which function is available. When DBGEN = 0, the JTAG port may
be used for boundary scan. When DBGEN = 1, the JTAG port may be used for debug.

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Chapter 29: LPC2300 Embedded ICE

6. Register description
The EmbeddedICE logic contains 16 registers as shown in Table 29–541 below. The
ARM7TDMI-S debug architecture is described in detail in "ARM7TDMI-S (rev 4) Technical
Reference Manual" (ARM DDI 0234A) published by ARM Limited.
Table 541. EmbeddedICE logic registers
Name

Width

Description

Address

Debug Control

6Force debug state, disable interrupts

00000

Debug Status

5

Status of debug

00001

Debug Comms Control Register32

Debug communication control register

00100

Debug Comms Data Register32

Debug communication data register

00101

Watchpoint 0 Address Value

32

Holds watchpoint 0 address value

01000

Watchpoint 0 Address Mask

32

Holds watchpoint 0 address mask

01001

Watchpoint 0 Data Value

32

Holds watchpoint 0 data value

01010

Watchpoint 0 Data Mask

32

Holds watchpoint 0 data mask

01011

Watchpoint 0 Control Value

9

Holds watchpoint 0 control value

01100

Watchpoint 0 Control Mask

8

Holds watchpoint 0 control mask

01101

Watchpoint 1 Address Value

32

Holds watchpoint 1 address value

10000

Watchpoint 1 Address Mask

32

Holds watchpoint 1 address mask

10001

Watchpoint 1 Data Value

32

Holds watchpoint 1 data value

10010

Watchpoint 1 Data Mask

32

Holds watchpoint 1 data mask

10011

Watchpoint 1 Control Value

9

Holds watchpoint 1 control value

10100

Watchpoint 1 Control Mask

8

Holds watchpoint 1 control mask

10101

7. Block diagram
The block diagram of the debug environment is shown below in Figure 29–112.

JTAG PORT
serialparallelinterface

EMBEDDED ICEINTERFACE
PROTOCOL
CONVERTER

5

EMBEDDED ICE

host running debugger
ARM7TDMI-STARGET BOARD

Fig 112.EmbeddedICE debug environment block diagram

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UM10211
Chapter 30: EmbeddedTrace Module (ETM)
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User manual

1. Features• Closely track the instructions that the ARM core is executing.
• One external trigger input.
• 10 pin interface.
• All registers are programmed through JTAG interface.
• Does not consume power when trace is not being used.
• THUMB instruction set support.

2. Applications
As the microcontroller has significant amounts of on-chip memories, it is not possible todetermine how the processor core is operating simply by observing the external pins. The
ETM provides real-time trace capability for deeply embedded processor cores. It outputs
information about processor execution to a trace port. A software debugger allows
configuration of the ETM using a JTAG interface and displays the trace information thathas been captured, in a format that a user can easily understand.

3. Description
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
Trace Port Analyzer captures the trace information under software debugger control.
Trace port can broadcast the Instruction trace information. Instruction trace (or PC trace)shows the flow of execution of the processor and provides a list of all the instructions thatwere executed. Instruction trace is significantly compressed by only broadcasting branchaddresses as well as a set of status signals that indicate the pipeline status on a cycle bycycle basis. Trace information generation can be controlled by selecting the trigger
resource. Trigger resources include address comparators, counters and sequencers.
Since trace information is compressed the software debugger requires a static image ofthe code being executed. Self-modifying code can not be traced because of thisrestriction.

3.1 ETM configuration
The following standard configuration is selected for the ETM macrocell.
Table 542. ETM configuration
Resource number/type

Small[1]Pairs of address comparators

1

Data Comparators

0 (Data tracing is not supported)

Memory Map Decoders

4

Counters

1

Sequencer Present

No

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Table 542. ETM configuration
Resource number/type

Small[1]External Inputs

2

External Outputs

0

FIFOFULL Present

Yes (Not wired)

FIFO depth

10 bytes

Trace Packet Width

4/8

[1]

For details refer to ARM documentation "Embedded Trace Macrocell Specification (ARM IHI 0014E)".

4. Pin description
Table 543. ETM pin description
Pin Name

Type

Description

TRACECLK

Output Trace Clock. The trace clock signal provides the clock for the trace
port. PIPESTAT[2:0], TRACESYNC, and TRACEPKT[3:0] signals arereferenced to the rising edge of the trace clock. This clock is not
generated by the ETM block. It is to be derived from the system clock.
The clock should be balanced to provide sufficient hold time for the
trace data signals. Half rate clocking mode is supported. Trace data
signals should be shifted by a clock phase from TRACECLK. Refer toFigure 3.14 page 3.26 and figure 3.15 page 3.27 in "ETM7 Technical
Reference Manual" (ARM DDI 0158B), for example circuits that
implements both half-rateclocking and shifting of the trace data withrespect to the clock. For TRACECLK timings refer to section 5.2 on
page 5-13 in "Embedded Trace Macrocell Specification" (ARM IHI
0014E).

PIPESTAT[2:0]Output Pipe Line status. The pipeline status signals provide a cycle-by-cycle
indication of what is happening in the execution stage of the processor
pipeline.

TRACESYNC

Output Trace synchronization. The trace sync signal is used to indicate thefirst packet of a group of trace packets and is asserted HIGH only forthe first packet of any branch address.

TRACEPKT[3:0] Output Trace Packet. The trace packet signals are used to output packaged
address and data information related to the pipeline status. All packets
are eight bits in length. A packet is output over two cycles. In the firstcycle, Packet[3:0] is output and in the second cycle, Packet[7:4] is
output.
EXTIN[0]Input

External Trigger Input

5. Register description
The ETM contains 29 registers as shown in Table 30–544 below. They are described indetail in the ARM IHI 0014E document published by ARM Limited, which is available via
the Internet at http://www.arm.com.

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Chapter 30: LPC2300 ETM

Table 544. ETM Registers
Name

Description

Access Register
Encoding

ETM Control

Controls the general operation of the ETM.

R/W

000 0000ETM Configuration CodeAllows a debugger to read the number of
each type of resource.

RO

000 0001

Trigger Event

Holds the controlling event.

WO

000 0010

Memory Map Decode Control Eight bit register, used to statically configure WO
the memory map decoder.

000 0011

ETM Status

Holds the pending overflow status bit.

RO

000 0100

System Configuration

Holds the configuration information using the RO
SYSOPT bus.

000 0101

Trace Enable Control 3

Holds the trace on/off addresses.

WO

000 0110Trace Enable Control 2

Holds the address of the comparison.

WO

000 0111

Trace Enable Event

Holds the enabling event.

WO

000 1000

Trace Enable Control 1

Holds the include and exclude regions.

WO

000 1001

FIFOFULL Region

Holds the include and exclude regions.

WO

000 1010

FIFOFULL Level

Holds the level below which the FIFO isconsidered full.

WO

000 1011

ViewData event

Holds the enabling event.

WO

000 1100

ViewData Control 1

Holds the include/exclude regions.

WO

000 1101

ViewData Control 2

Holds the include/exclude regions.

WO

000 1110

ViewData Control 3

Holds the include/exclude regions.

WO

000 1111

Address Comparator 1 to 16

Holds the address of the comparison.

WO

001 xxxx

Address Access Type 1 to 16

Holds the type of access and the size.

WO

010 xxxx

Reserved--

000 xxxx

Reserved--

100 xxxx

Initial Counter Value 1 to 4

Holds the initial value of the counter.

WO

101 00xx

Counter Enable 1 to 4

Holds the counter clock enable control andevent.

WO

101 01xx

Counter reload 1 to 4

Holds the counter reload event.

WO

101 10xx

Counter Value 1 to 4

Holds the current counter value.

RO

101 11xx

Sequencer State and Control

Holds the next state triggering events.

-

110 00xx

External Output 1 to 4

Holds the controlling events for each output. WO

110 10xx

Reserved--

110 11xx

Reserved--

111 0xxx

Reserved--

111 1xxx

6. Reset state of multiplexed pins
On the LPC2300, the ETM pin functions are multiplexed with GPIO, PWM, UART, and
CAN functions. In order to use the trace feature, the pins must be configured to select thefunction. Details may be found in "Pin Connect" chapter on page 109.

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Chapter 30: LPC2300 ETM

7. Block diagram
The block diagram of the ETM debug environment is shown below in Figure 30–113.

APPLICATION PCBCONNECTOR

TRACE
PORT
ANALYZER

TRACE

10
ETM

TRIGGERPERIPHERALPERIPHERALCONNECTOR
Hostrunningdebugger

RAM
JTAG
INTERFACE
UNIT

5

ARM

ROM
EMBEDDED ICE

LAN

Fig 113.ETM debug environment block diagram

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UM10211
Chapter 31: RealMonitor
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1. Features
Remark: RealMonitor is a configurable software module which enables real time debug.
RealMonitor is developed by ARM Inc. Information presented in this chapter is taken fromthe ARM document RealMonitor Target Integration Guide (ARM DUI 0142A). It applies toa specific configuration of RealMonitor software programmed in the on-chip ROM bootmemory of this device.

• Allows user to establish a debug session to a currently running system without halting
or resetting the system.

• Allows user time-critical interrupt code to continue executing while other user
application code is being debugged.

2. Applications
Real time debugging.

3. Description
RealMonitor is a lightweight debug monitor that allows interrupts to be serviced while user
debug their foreground application. It communicates with the host using the DCC (Debug
Communications Channel), which is present in the EmbeddedICE logic. RealMonitor
provides advantages over the traditional methods for debugging applications in ARM
systems. The traditional methods include:• Angel (a target-based debug monitor).
• Multi-ICE or other JTAG unit and EmbeddedICE logic (a hardware-based debug
solution).
Although both of these methods provide robust debugging environments, neither issuitable as a lightweight real-time monitor.
Angel is designed to load and debug independent applications that can run in a variety ofmodes, and communicate with the debug host using a variety of connections (such as aserial port or ethernet). Angel is required to save and restore full processor context, andthe occurrence of interrupts can be delayed as a result. Angel, as a fully functionaltarget-based debugger, is therefore too heavyweight to perform as a real-time monitor.
Multi-ICE is a hardware debug solution that operates using the EmbeddedICE unit that isbuilt into most ARM processors. To perform debug tasks such as accessing memory or
the processor registers, Multi-ICE must place the core into a debug state. While theprocessor is in this state, which can be millions of cycles, normal program execution issuspended, and interrupts cannot be serviced.
RealMonitor combines features and mechanisms from both Angel and Multi-ICE toprovide the services and functions that are required. In particular, it contains both theMulti-ICE communication mechanisms (the DCC using JTAG), and Angel-like support for
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Chapter 31: LPC2300 RealMonitor

processor context saving and restoring. RealMonitor is pre-programmed in the on-chip
ROM memory (boot sector). When enabled It allows user to observe and debug whileparts of application continue to run. Refer to Section 31–4 “How to Enable RealMonitor”
on page 577 for details.

3.1 RealMonitor Components
As shown in Figure 31–114, RealMonitor is split in to two functional components:

DEBUGGER
RDI 1.5.1

host
REALMONITOR.DLLRMHOST
RDI 1.5.1 RT

JTAG UNIT

RealMonitor
protocolDCC transmissions
over the JTAG linktargetTARGET BOARD AND
PROCESSORRMTARGETAPPLICATION

Fig 114. RealMonitor Components

3.1.1 RMHost
This is located between a debugger and a JTAG unit. The RMHost controller,
RealMonitor.dll, converts generic Remote Debug Interface (RDI) requests from thedebugger into DCC-only RDI messages for the JTAG unit. For complete details on
debugging a RealMonitor-integrated application from the host, see the ARM RMHost User
Guide (ARM DUI 0137A).

3.1.2 RMTarget
This is pre-programmed in the on-chip ROM memory (boot sector), and runs on the target
hardware. It uses the EmbeddedICE logic, and communicates with the host using the
DCC. For more details on RMTarget functionality, see the RealMonitor Target Integration
Guide (ARM DUI 0142A).

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Chapter 31: LPC2300 RealMonitor

3.2 How RealMonitor Works
In general terms, the RealMonitor operates as a state machine, as shown in
Figure 31–115. RealMonitor switches between running and stopped states, in response topackets received by the host, or due to asynchronous events on the target. RMTarget
supports the triggering of only one breakpoint, watchpoint, stop, or semihosting SWI at atime. There is no provision to allow nested events to be saved and restored. So, forexample, if user application has stopped at one breakpoint, and another breakpoint
occurs in an IRQ handler, RealMonitor enters a panic state. No debugging can be
performed after RealMonitor enters this state.

SWI abort
undef
stop
SWI abort
undef
RUNNINGSTOPPED

PANIC

goFig 115.RealMonitor as a State Machine

A debugger such as the ARM eXtended Debugger (AXD) or other RealMonitor aware
debugger, that runs on a host computer, can connect to the target to send commands andreceive data. This communication between host and target is illustrated in Figure 31–114.
The target component of RealMonitor, RMTarget, communicates with the host component,
RMHost, using the Debug Communications Channel (DCC), which is a reliable link whose
data is carried over the JTAG connection.
While user application is running, RMTarget typically uses IRQs generated by the DCC.
This means that if user application also wants to use IRQs, it must pass any
DCC-generated interrupts to RealMonitor.
To allow nonstop debugging, the EmbeddedICE-RT logic in the processor generates a
Prefetch Abort exception when a breakpoint is reached, or a Data Abort exception when awatchpoint is hit. These exceptions are handled by the RealMonitor exception handlersthat inform the user, by way of the debugger, of the event. This allows user application tocontinue running without stopping the processor. RealMonitor considers user application
to consist of two parts:• A foreground application running continuously, typically in User, System, or SVC
mode• A background application containing interrupt and exception handlers that are
triggered by certain events in user system, including:– IRQs or FIQs
– Data and Prefetch aborts caused by user foreground application. This indicates anerror in the application being debugged. In both cases the host is notified and theuser application is stopped.

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Chapter 31: LPC2300 RealMonitor– Undef exception caused by the undefined instructions in user foregroundapplication. This indicates an error in the application being debugged. RealMonitor
stops the user application until a "Go" packet is received from the host.
When one of these exceptions occur that is not handled by user application, the following
happens:• RealMonitor enters a loop, polling the DCC. If the DCC read buffer is full, control ispassed to rm_ReceiveData() (RealMonitor internal function). If the DCC write buffer isfree, control is passed to rm_TransmitData() (RealMonitor internal function). If there isnothing else to do, the function returns to the caller. The ordering of the above
comparisons gives reads from the DCC a higher priority than writes to thecommunications link.

• RealMonitor stops the foreground application. Both IRQs and FIQs continue to beserviced if they were enabled by the application at the time the foreground application
was stopped.

4. How to Enable RealMonitor
The following steps must be performed to enable RealMonitor. A code example which
implements all the steps can be found at the end of this section.

4.1 Adding Stacks
User must ensure that stacks are set up within application for each of the processor
modes used by RealMonitor. For each mode, RealMonitor requires a fixed number ofwords of stack space. User must therefore allow sufficient stack space for both
RealMonitor and application.
RealMonitor has the following stack requirements:
Table 545. RealMonitor stack requirement
Processor Mode

RealMonitor Stack Usage (Bytes)

Undef

48

Prefetch Abort

16

Data Abort

16

IRQ

8

4.2 IRQ ModeA stack for this mode is always required. RealMonitor uses two words on entry to its
interrupt handler. These are freed before nested interrupts are enabled.

4.3 Undef ModeA stack for this mode is always required. RealMonitor uses 12 words while processing an
undefined instruction exception.

4.4 SVC Mode
RealMonitor makes no use of this stack.
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4.5 Prefetch Abort Mode
RealMonitor uses four words on entry to its Prefetch abort interrupt handler.

4.6 Data Abort Mode
RealMonitor uses four words on entry to its data abort interrupt handler.

4.7 User/System Mode
RealMonitor makes no use of this stack.

4.8 FIQ Mode
RealMonitor makes no use of this stack.

4.9 Handling Exceptions
This section describes the importance of sharing exception handlers between
RealMonitor and user application.

4.9.1 RealMonitor Exception HandlingTo function properly, RealMonitor must be able to intercept certain interrupts andexceptions. Figure 31–116 illustrates how exceptions can be claimed by RealMonitor
itself, or shared between RealMonitor and application. If user application requires the
exception sharing, they must provide function (such as app_IRQDispatch ()). Dependingon the nature of the exception, this handler can either:• Pass control to the RealMonitor processing routine, such as rm_irqhandler2().
• Claim the exception for the application itself, such as app_IRQHandler ().
In a simple case where an application has no exception handlers of its own, theapplication can install the RealMonitor low-level exception handlers directly into the vector
table of the processor. Although the irq handler must get the address of the Vectored
Interrupt Controller. The easiest way to do this is to write a branch instruction (<address>)
into the vector table, where the target of the branch is the start address of the relevant
RealMonitor exception handler.

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RealMonitor supplied exception vector handlers
RM_UNDEF_HANDLER()
RM_PREFETCHABORT_HANDLER()
RM_DATAABORT_HANDLER()
RM_IRQHANDLER()

RESET

UNDEF

SWI
sharing IRQs between RealMonitor and user IRQ handler
PREFETCH
ABORT

RM_IRQHANDLER2()DATA ABORTAPP_IRQDISPATCH

RESERVED

APP_IRQHANDLER2()
OR

IRQ

FIQ

Fig 116. Exception Handlers

4.10 RMTarget Initialization
While the processor is in a privileged mode, and IRQs are disabled, user must include aline of code within the start-up sequence of application to call rm_init_entry().

4.11 Code Example
The following example shows how to setup stack, VIC, initialize RealMonitor and sharenon vectored interrupts:
IMPORT rm_init_entry
IMPORT rm_prefetchabort_handler
IMPORT rm_dataabort_handler
IMPORT rm_irqhandler2
IMPORT rm_undef_handler
IMPORT User_Entry ;Entry point of user application.
CODE32ENTRY;Define exception table. Instruct linker to place code at address 0x0000 0000
AREA exception_table, CODELDR pc, Reset_Address
LDR pc, Undefined_Address
LDR pc, SWI_Address
LDR pc, Prefetch_Address
LDR pc, Abort_Address
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NOP ; Insert User code valid signature here.
LDR pc, [pc, #-0x120] ;Load IRQ vector from VIC
LDR PC, FIQ_Address
Reset_Address
Undefined_Address
SWI_Address
Prefetch_Address
Abort_Address
FIQ_Address

DCD __init;Reset Entry point
DCD rm_undef_handler ;Provided by RealMonitor
DCD 0;User can put address of SWI handler here
DCD rm_prefetchabort_handler;Provided by RealMonitor
DCD rm_dataabort_handler;Provided by RealMonitor
DCD 0;User can put address of FIQ handler here

AREA init_code, CODE
ram_end EQU 0x4000xxxx ; Top of on-chip RAM.
__init; /*********************************************************************; * Set up the stack pointers for various processor modes. Stack grows; * downwards.
; *********************************************************************/LDR r2, =ram_end ;Get top of RAM
MRS r0, CPSR ;Save current processor mode
; Initialize the Undef mode stack for RealMonitor use
BIC r1, r0, #0x1f
ORR r1, r1, #0x1b
MSR CPSR_c, r1;Keep top 32 bytes for flash programming routines.
;Refer to Flash Memory System and Programming chapter
SUB sp,r2,#0x1F; Initialize the Abort mode stack for RealMonitor
BIC r1, r0, #0x1f
ORR r1, r1, #0x17
MSR CPSR_c, r1;Keep 64 bytes for Undef mode stack
SUB sp,r2,#0x5F; Initialize the IRQ mode stack for RealMonitor and User
BIC r1, r0, #0x1f
ORR r1, r1, #0x12
MSR CPSR_c, r1;Keep 32 bytes for Abort mode stack
SUB sp,r2,#0x7F; Return to the original mode.
MSR CPSR_c, r0; Initialize the stack for user application; Keep 256 bytes for IRQ mode stack
SUB sp,r2,#0x17F

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Chapter 31: LPC2300 RealMonitor; /*********************************************************************; * Setup Vectored Interrupt controller. DCC Rx and Tx interrupts; * generate Non Vectored IRQ request. rm_init_entry is aware; * of the VIC and it enables the DBGCommRX and DBGCommTx interrupts.
; * Default vector address register is programmed with the address of; * Non vectored app_irqDispatch mentioned in this example. User can setup; * Vectored IRQs or FIQs here.
; *********************************************************************/
VICBaseAddr
EQU 0xFFFFF000 ; VIC Base address
VICDefVectAddrOffset EQU 0x34
LDR
LDR
STR

r0, =VICBaseAddr
r1, =app_irqDispatch
r1, [r0,#VICDefVectAddrOffset]BL
rm_init_entry;Initialize RealMonitor;enable FIQ and IRQ in ARM Processor
MRS r1, CPSR
; get the CPSR
BIC r1, r1, #0xC0; enable IRQs and FIQs
MSR CPSR_c, r1; update the CPSR
; /*********************************************************************; * Get the address of the User entry point.
; *********************************************************************/LDR lr, =User_Entry
MOV pc, lr; /*********************************************************************; * Non vectored irq handler (app_irqDispatch); *********************************************************************/
AREA app_irqDispatch, CODE
VICVectAddrOffset EQU 0x30
app_irqDispatch;enable interrupt nesting
STMFD sp!, {r12,r14}
MRS r12, spsr
MSR cpsr_c,0x1F;Save SPSR in to r12;Re-enable IRQ, go to system mode

;User should insert code here if non vectored Interrupt sharing is;required. Each non vectored shared irq handler must return to;the interrupted instruction by using the following code.
;
MSR cpsr_c, #0x52;Disable irq, move to IRQ mode;
MSR spsr, r12;Restore SPSR from r12;
STMFD sp!, {r0};
LDR r0, =VICBaseAddr;
STR r1, [r0,#VICVectAddrOffset];Acknowledge Non Vectored irq has finished;LDMFD sp!, {r12,r14,r0};Restore registers;
SUBS pc, r14, #4;Return to the interrupted instruction;user interrupt did not happen so call rm_irqhandler2. This handler
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Chapter 31: LPC2300 RealMonitor;is not aware of the VIC interrupt priority hardware so trick;rm_irqhandler2 to return here
STMFD sp!, {ip,pc}
LDR pc, rm_irqhandler2;rm_irqhandler2 returns here
MSR cpsr_c, #0x52
MSR spsr, r12
STMFD sp!, {r0}
LDR r0, =VICBaseAddr
STR r1, [r0,#VICVectAddrOffset]
LDMFD sp!, {r12,r14,r0}
SUBS pc, r14, #4;Disable irq, move to IRQ mode
;Restore SPSR from r12;Acknowledge Non Vectored irq has finished;Restore registers;Return to the interrupted instruction

END

5. RealMonitor Build Options
RealMonitor was built with the following options:
RM_OPT_DATALOGGING=FALSEThis option enables or disables support for any target-to-host packets sent on a non
RealMonitor (third-party) channel.
RM_OPT_STOPSTART=TRUE
This option enables or disables support for all stop and start debugging features.
RM_OPT_SOFTBREAKPOINT=TRUE
This option enables or disables support for software breakpoints.
RM_OPT_HARDBREAKPOINT=TRUE
Enabled for cores with EmbeddedICE-RT. This device uses ARM-7TDMI-S Rev 4 with
EmbeddedICE-RT.
RM_OPT_HARDWATCHPOINT=TRUE
Enabled for cores with EmbeddedICE-RT. This device uses ARM-7TDMI-S Rev 4 with
EmbeddedICE-RT.
RM_OPT_SEMIHOSTING=FALSEThis option enables or disables support for SWI semi-hosting. Semi-hosting provides
code running on an ARM target use of facilities on a host computer that is running an
ARM debugger. Examples of such facilities include the keyboard input, screen output,
and disk I/O.
RM_OPT_SAVE_FIQ_REGISTERS=TRUE
This option determines whether the FIQ-mode registers are saved into the registers
block when RealMonitor stops.
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RM_OPT_READBYTES=TRUE
RM_OPT_WRITEBYTES=TRUE
RM_OPT_READHALFWORDS=TRUE
RM_OPT_WRITEHALFWORDS=TRUE
RM_OPT_READWORDS=TRUE
RM_OPT_WRITEWORDS=TRUE
Enables/Disables support for 8/16/32 bit read/write.
RM_OPT_EXECUTECODE=FALSE
Enables/Disables support for executing code from "execute code" buffer. The code
must be downloaded first.
RM_OPT_GETPC=TRUE
This option enables or disables support for the RealMonitor GetPC packet. Useful incode profiling when real monitor is used in interrupt mode.
RM_EXECUTECODE_SIZE=NA"execute code" buffer size. Also refer to RM_OPT_EXECUTECODE option.
RM_OPT_GATHER_STATISTICS=FALSEThis option enables or disables the code for gathering statistics about the internal
operation of RealMonitor.
RM_DEBUG=FALSEThis option enables or disables additional debugging and error-checking code in
RealMonitor.
RM_OPT_BUILDIDENTIFIER=FALSEThis option determines whether a build identifier is built into the capabilities table of
RMTarget. Capabilities table is stored in ROM.
RM_OPT_SDM_INFO=FALSE
SDM gives additional information about application board and processor to debug tools.
RM_OPT_MEMORYMAP=FALSEThis option determines whether a memory map of the board is built into the target andmade available through the capabilities table
RM_OPT_USE_INTERRUPTS=TRUE
This option specifies whether RMTarget is built for interrupt-driven mode or polled
mode.
RM_FIFOSIZE=NA
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This option specifies the size, in words, of the data logging FIFO buffer.
CHAIN_VECTORS=FALSEThis option allows RMTarget to support vector chaining through µHAL (ARM HWabstraction API).

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Chapter 32: Supplementary informationRev. 01 — 6 July 2007

User manual

1. Abbreviations
Table 546. Abbreviations
AcronymDescription

ADC

Analog-to-Digital Converter

APB

ARM Peripheral Bus

BOD

Brown-Out Detection

CPU

Central Processing Unit

DAC

Digital-to-Analog Converter

DCC

Debug Communications Channel

FIFO

First In, First Out

GPIO

General Purpose Input/Output

NA

Not Applicable

PLL

Phase-Locked Loop

POR

Power-On Reset

PWM

Pulse Width Modulator

RAM

Random Access Memory

SRAM

Static Random Access Memory

UART

Universal Asynchronous Receiver/Transmitter

USB

Universal Serial Bus

VIC

Vector Interrupt Controller

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Chapter 32: Supplementary information

2. Legal information
2.1

Definitions

Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences ofuse of such information.

2.2

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected toresult in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Disclaimers

General — Information in this document is believed to be accurate andreliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of suchinformation and shall have no liability for the consequences of use of suchinformation.
Right to make changes — NXP Semiconductors reserves the right to makechanges to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

2.3

Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
SoftConnect — is a trademark of NXP B.V.
I2C-bus — logo is a trademark of NXP B.V.
GoodLink — is a trademark of NXP B.V.

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Chapter 32: Supplementary information

Notes

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Chapter 32: Supplementary information

3. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.

LPC2364/6/8/78 ordering options . . . . . . . . . . .5
LPC2378 ordering options . . . . . . . . . . . . . . . . .5
LPC2300 memory usage . . . . . . . . . . . . . . . . .10
APB peripherals and base addresses . . . . . . .15
ARM exception vector locations . . . . . . . . . . . .16
LPC2300 Memory mapping modes . . . . . . . . .16
Memory mapping control registers . . . . . . . . . .17
Memory Mapping control register (MEMMAP address 0xE01F C040) bit description . . . . . . .18
Table 9. Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 10. Summary of system control registers . . . . . . . .21
Table 11. Reset Source Identification register (RSID address 0xE01F C180) bit description . . . . . . .23
Table 12. External Interrupt registers . . . . . . . . . . . . . . . .25
Table 13. External Interrupt Flag register (EXTINT - address
0xE01F C140) bit description . . . . . . . . . . . . . .26
Table 14. External Interrupt Mode register (EXTMODE address 0xE01F C148) bit description . . . . . . .27
Table 15. External Interrupt Polarity register (EXTPOLAR address 0xE01F C14C) bit description . . . . . . .27
Table 16. System Controls and Status register (SCS address 0xE01F C1A0) bit description . . . . . . .28
Table 17. Code security register map. . . . . . . . . . . . . . . .29
Table 18. Code Security Protection Register (CSPR address 0xE01F C184) bit description . . . . . . .29
Table 19. AHB configuration register map . . . . . . . . . . . .30
Table 20. AHB Arbiter Configuration register 1 (AHBCFG1 address 0xE01F C188) bit description . . . . . . .30
Table 21. AHB Arbiter Configuration register 2 (AHBCFG2 address 0xE01F C18C) bit description . . . . . . .31
Table 22. Summary of system control registers . . . . . . . .35
Table 23. Clock Source Select register (CLKSRCSEL address 0xE01F C10C) bit description . . . . . . .37
Table 24. PLL registers . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 25. PLL Control register (PLLCON - address
0xE01F C080) bit description . . . . . . . . . . . . . .39
Table 26. PLL Configuration register (PLLCFG - address
0xE01F C084) bit description . . . . . . . . . . . . . .40
Table 27. Multiplier values for 32 kHz oscillator . . . . . . . .40
Table 28. PLL Status register (PLLSTAT - address
0xE01F C088) bit description . . . . . . . . . . . . . .42
Table 29. PLL control bit combinations . . . . . . . . . . . . . .43
Table 30. PLL Feed register (PLLFEED - address
0xE01F C08C) bit description. . . . . . . . . . . . . .43
Table 31. PLL frequency parameter . . . . . . . . . . . . . . . . .44
Table 32. Additional Multiplier Values for use with a Low
Frequency Clock Input . . . . . . . . . . . . . . . . . . .44
Table 33. Potential values for PLL example . . . . . . . . . . .46

Table 34. CPU Clock Configuration register (CCLKCFG address 0xE01F C104) bit description. . . . . . . 48
Table 35. USB Clock Configuration register (USBCLKCFG address 0xE01F C108) bit description. . . . . . . 49
Table 36. IRC Trim register (IRCTRIM - address
0xE01F C1A4) bit description . . . . . . . . . . . . . 49
Table 37. Peripheral Clock Selection register 0 (PCLKSEL0- address 0xE01F C1A8) bit description . . . . . 49
Table 38. Peripheral Clock Selection register 1 (PCLKSEL1- address 0xE01F C1AC) bit description . . . . . 50
Table 39. Peripheral Clock Selection register bit values . 50
Table 40. Power Control registers . . . . . . . . . . . . . . . . . . 52
Table 41. Power Mode Control register (PCON - address
0xE01F COCO) bit description . . . . . . . . . . . . 53
Table 42. Encoding of reduced power modes . . . . . . . . . 53
Table 43. Interrupt Wakeup register (INTWAKE - address
0xE01F C144) bit description. . . . . . . . . . . . . . 54
Table 44. Power Control for Peripherals register (PCONP address 0xE01F C0C4) bit description . . . . . . 55
Table 45. Memory bank selection . . . . . . . . . . . . . . . . . . 61
Table 46. Pad interface and control signal descriptions . 62
Table 47. EMC register summary . . . . . . . . . . . . . . . . . . 62
Table 48. EMC Control register (EMCControl - address
0xFFE0 8000) bit description . . . . . . . . . . . . . . 63
Table 49. EMC Status register (EMCStatus - address
0xFFE0 8008) bit description . . . . . . . . . . . . . . 64
Table 50. EMC Configuration register (EMCConfig address 0xFFE0 8008) bit description . . . . . . . 65
Table 51. Static Memory Configuration registers(EMCStaticConfig0-1 - addresses 0xFFE0 8200,
0xFFE0 8220) bit description . . . . . . . . . . . . . . 65
Table 52. Static Memory Write Enable Delay registers(EMCStaticWaitWen0-1 - addresses
0xFFE0 8204,0xFFE0 8224) bit description . . 67
Table 53. Static Memory Output Enable delay registers(EMCStaticWaitOen0-1 - addresses
0xFFE0 8208, 0xFFE0 8228) bit description . . 67
Table 54. Static Memory Read Delay registers(EMCStaticWaitRd0-1 - addresses 0xFFE0 820C,
0xFFE0 822C) bit description . . . . . . . . . . . . . 68
Table 55. Static Memory Page Mode Read Delayregisters0-1 (EMCStaticWaitPage0-1 - addresses
0xFFE0 8210, 0xFFE0 8230) bit description . . 68
Table 56. Static Memory Write Delay registers0-1(EMCStaticWaitWr - addresses 0xFFE0 8214,
0xFFE0 8234) bit description . . . . . . . . . . . . . . 69
Table 57. Static Memory Extended Wait register(EMCStaticExtendedWait - addresscontinued >>UM10211_1

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Chapter 32: Supplementary information

0xFFE0 8880) bit description . . . . . . . . . . . . . .69
Table 58. Static Memory Turn Round Delay registers0-1(EMCStaticWaitTurn0-1- addresses
0xFFE0 8218, 0xFFE0 8238) bit description . .70
Table 59. VIC register map. . . . . . . . . . . . . . . . . . . . . . . .73
Table 60. Software Interrupt register (VICSoftInt - address
0xFFFF F018) bit description . . . . . . . . . . . . . .75
Table 61. Software Interrupt Clear register (VICSoftIntClear- address 0xFFFF F01C) bit description . . . . . .75
Table 62. Raw Interrupt Status register (VICRawIntr address 0xFFFF F008) bit description . . . . . . .76
Table 63. Interrupt Enable register (VICIntEnable - address
0xFFFF F010) bit description . . . . . . . . . . . . . .76
Table 64. Interrupt Enable Clear register (VICIntEnClear address 0xFFFF F014) bit description . . . . . . .76
Table 65. Interrupt Select register (VICIntSelect - address
0xFFFF F00C) bit description . . . . . . . . . . . . . .77
Table 66. IRQ Status register (VICIRQStatus - address
0xFFFF F000) bit description . . . . . . . . . . . . . .77
Table 67. FIQ Status register (VICFIQStatus - address
0xFFFF F004) bit description . . . . . . . . . . . . . .77
Table 68. Vector Address registers 0-31 (VICVectAddr0-31 addresses 0xFFFF F100 to 0xFFFF F17C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Table 69. Vector Priority registers 0-31 (VICVectPriority0-31- addresses 0xFFFF F200 to 0xFFFF F27C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Table 70. Vector Address register (VICAddress - address
0xFFFF FF00) bit description . . . . . . . . . . . . . .78
Table 71. Software Priority Mask register(VICSWPriorityMask - address 0xFFFF F024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 72. Protection Enable register (VICProtection address 0xFFFF F020) bit description . . . . . . .79
Table 73. Connection of interrupt sources to the Vectored
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . .79
Table 74. Interrupt sources bit allocation table . . . . . . . . .81
Table 75. MAM responses to program accesses of various
types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 76. MAM responses to data and DMA accesses ofvarious types . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 77. Summary of Memory Acceleration Module
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 78. MAM Control Register (MAMCR - address
0xE01F C000) bit description . . . . . . . . . . . . . .87
Table 79. MAM Timing register (MAMTIM - address
0xE01F C004) bit description . . . . . . . . . . . . . .88
Table 80. LPC2364/66/68 pin description . . . . . . . . . . . .90
Table 81. LPC2378 pin description . . . . . . . . . . . . . . . . .98
Table 82. Pin function select register bits . . . . . . . . . . . .109
Table 83. Pin Mode Select register Bits . . . . . . . . . . . . . 110

Table 84. Pin Connect Block Register Map . . . . . . . . . . 110
Table 85. Pin function select register 0 (PINSEL0 - address
0xE002 C000) bit description. . . . . . . . . . . . . 111
Table 86. Pin function select register 1 (PINSEL1 - address
0xE002 C004) bit description. . . . . . . . . . . . . 111
Table 87. Pin function select register 2 (PINSEL2 - address
0xE002 C008) bit description. . . . . . . . . . . . . 112
Table 88. Pin function select register 3 (PINSEL3 - address
0xE002 C00C) bit description . . . . . . . . . . . . 113
Table 89. Pin function select register 4 (PINSEL4 - address
0xE002 C010) bit description. . . . . . . . . . . . . 113
Table 90. Pin function select register 5 (PINSEL5 - address
0xE002 C014) bit description. . . . . . . . . . . . . 114
Table 91. Pin function select register 6 (PINSEL6 - address
0xE002 C018) bit description. . . . . . . . . . . . . 115
Table 92. Pin function select register 7 (PINSEL7 - address
0xE002 C01C) bit description . . . . . . . . . . . . 115
Table 93. Pin function select register 8 (PINSEL8 - address
0xE002 C020) bit description. . . . . . . . . . . . . 116
Table 94. Pin function select register 9 (PINSEL9 - address
0xE002 C024) bit description. . . . . . . . . . . . . 117
Table 95. Pin function select register 10 (PINSEL10 address 0xE002 C028) bit description . . . . . . 117
Table 96. Pin Mode select register 0 (PINMODE0 - address
0xE002 C040) bit description. . . . . . . . . . . . . 118
Table 97. Pin Mode select register 1 (PINMODE1 - address
0xE002 C044) bit description. . . . . . . . . . . . . 118
Table 98. Pin Mode select register 2 (PINMODE2 - address
0xE002 C048) bit description. . . . . . . . . . . . . 118
Table 99. Pin Mode select register 3 (PINMODE3 - address
0xE002 C04C) bit description . . . . . . . . . . . . 119
Table 100.Pin Mode select register 4 (PINMODE4 - address
0xE002 C050) bit description. . . . . . . . . . . . . 119
Table 101.Pin Mode select register 5 (PINMODE5 - address
0xE002 C054) bit description. . . . . . . . . . . . . 119
Table 102.Pin Mode select register 6 (PINMODE6 - address
0xE002 C058) bit description. . . . . . . . . . . . . 119
Table 103.Pin Mode select register 7 (PINMODE7 - address
0xE002 C05C) bit description . . . . . . . . . . . . 120
Table 104.Pin Mode select register 8 (PINMODE8 - address
0xE002 C060) bit description. . . . . . . . . . . . . 120
Table 105.Pin Mode select register 9 (PINMODE9 - address
0xE002 C064) bit description. . . . . . . . . . . . . 120
Table 106.GPIO pin description . . . . . . . . . . . . . . . . . . . 122
Table 107.GPIO register map (legacy APB accessible
registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 108.GPIO register map (local bus accessible registers- enhanced GPIO features) . . . . . . . . . . . . . . 123
Table 109.GPIO interrupt register map. . . . . . . . . . . . . . 125
Table 110. GPIO port Direction register (IO0DIR - address
0xE002 8008 and IO1DIR - addresscontinued >>UM10211_1

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Chapter 32: Supplementary information

0xE002 8018) bit description . . . . . . . . . . . . .125
Table 111. Fast GPIO port Direction register(FIO[0/1/2/3/4]DIR - address
0x3FFF C0[0/2/4/6/8]0) bit description . . . . . .125
Table 112. Fast GPIO port Direction control byte andhalf-word accessible register description . . . .126
Table 113. GPIO port output Set register (IO0SET - address
0xE002 8004 and IO1SET - address
0xE002 8014) bit description . . . . . . . . . . . . .127
Table 114. Fast GPIO port output Set register(FIO[0/1/2/3/4]SET - address
0x3FFF C0[1/3/5/7/9]8) bit description . . . . . .127
Table 115. Fast GPIO port output Set byte and half-wordaccessible register description . . . . . . . . . . . .127
Table 116. GPIO port output Clear register (IO0CLR address 0xE002 800C and IO1CLR - address
0xE002 801C) bit description . . . . . . . . . . . . .128
Table 117. Fast GPIO port output Clear register(FIO[0/1/2/3/4]CLR - address
0x3FFF C0[1/3/5/7/9]C) bit description. . . . . .128
Table 118. Fast GPIO port output Clear byte and half-wordaccessible register description . . . . . . . . . . . .129
Table 119. GPIO port Pin value register (IO0PIN - address
0xE002 8000 and IO1PIN - address
0xE002 8010) bit description . . . . . . . . . . . . .130
Table 120.Fast GPIO port Pin value register(FIO[0/1/2/3/4]PIN - address
0x3FFF C0[1/3/5/7/9]4) bit description . . . . . .130
Table 121.Fast GPIO port Pin value byte and half-wordaccessible register description . . . . . . . . . . . .131
Table 122.Fast GPIO port Mask register(FIO[0/1/2/3/4]MASK - address
0x3FFF C0[1/3/5/7/9]0) bit description . . . . . .132
Table 123.Fast GPIO port Mask byte and half-wordaccessible register description . . . . . . . . . . . .132
Table 124.GPIO overall Interrupt Status register (IOIntStatus- address 0xE002 8080) bit description . . . . .133
Table 125.GPIO Interrupt Enable for Rising edge register(IO0IntEnR - address 0xE002 8090 and
IO2IntEnR - address 0xE002 80B0) bit description
133
Table 126.GPIO Interrupt Enable for Falling edge register(IO0IntEnF - address 0xE002 8094 andIO2IntEnF - address 0xE002 80B4) bit description
133
Table 127.GPIO Status for Rising edge register (IO0IntStatR- address 0xE002 8084 and IO2IntStatR - address
0xE002 80A4) bit description . . . . . . . . . . . . .134
Table 128.GPIO Status for Falling edge register (IO0IntStatF- address 0xE002 8088 and IO2IntStatF - address
0xE002 80A8) bit description . . . . . . . . . . . . .134

Table 129.GPIO Status for Falling edge register (IO0IntClr address 0xE002 808C and IO2IntClr - address
0xE002 80AC) bit description . . . . . . . . . . . . 134
Table 130.Ethernet acronyms, abbreviations, and definitions
137
Table 131.Example PHY Devices. . . . . . . . . . . . . . . . . . 143
Table 132.Ethernet RMII pin descriptions. . . . . . . . . . . . 143
Table 133.Ethernet MIIM pin descriptions . . . . . . . . . . . 143
Table 134.Register definitions . . . . . . . . . . . . . . . . . . . . 144
Table 135.MAC Configuration register 1 (MAC1 - address
0xFFE0 0000) bit description . . . . . . . . . . . . . 146
Table 136.MAC Configuration register 2 (MAC2 - address
0xFFE0 0004) bit description . . . . . . . . . . . . . 147
Table 137. Pad operation . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 138.Back-to-back Inter-packet-gap register (IPGT address 0xFFE0 0008) bit description . . . . . . 148
Table 139. Non Back-to-back Inter-packet-gap register(IPGR - address 0xFFE0 000C) bit description . .
149
Table 140.Collision Window / Retry register (CLRT - address
0xFFE0 0010) bit description . . . . . . . . . . . . . 149
Table 141.Maximum Frame register (MAXF - address
0xFFE0 0014) bit description . . . . . . . . . . . . . 149
Table 142.PHY Support register (SUPP - address
0xFFE0 0018) bit description . . . . . . . . . . . . . 150
Table 143. Test register (TEST - address 0xFFE0 ) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 144.MII Mgmt Configuration register (MCFG - address
0xFFE0 0020) bit description . . . . . . . . . . . . . 150
Table 145. Clock select encoding . . . . . . . . . . . . . . . . . . 151
Table 146.MII Mgmt Command register (MCMD - address
0xFFE0 0024) bit description . . . . . . . . . . . . . 151
Table 147.MII Mgmt Address register (MADR - address
0xFFE0 0028) bit description . . . . . . . . . . . . . 151
Table 148.MII Mgmt Write Data register (MWTD - address
0xFFE0 002C) bit description . . . . . . . . . . . . 152
Table 149.MII Mgmt Read Data register (MRDD - address
0xFFE0 0030) bit description . . . . . . . . . . . . . 152
Table 150.MII Mgmt Indicators register (MIND - address
0xFFE0 0034) bit description . . . . . . . . . . . . . 152
Table 151.Station Address register (SA0 - address
0xFFE0 0040) bit description . . . . . . . . . . . . . 153
Table 152.Station Address register (SA1 - address
0xFFE0 0044) bit description . . . . . . . . . . . . . 153
Table 153.Station Address register (SA2 - address
0xFFE0 0048) bit description . . . . . . . . . . . . . 154
Table 154.Command register (Command - address
0xFFE0 0100) bit description . . . . . . . . . . . . . 154
Table 155.Status register (Status - address 0xFFE0 0104) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 156.Receive Descriptor Base Address register

continued >>UM10211_1

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Chapter 32: Supplementary information(RxDescriptor - address 0xFFE0 0108) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Table 157.receive Status Base Address register (RxStatus address 0xFFE0 010C) bit description . . . . . .155
Table 158.Receive Number of Descriptors register(RxDescriptor - address 0xFFE0 0110) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Table 159.Receive Produce Index register (RxProduceIndex- address 0xFFE0 0114) bit description . . . . .156
Table 160.Receive Consume Index register(RXConsumeIndex - address 0xFFE0 0118) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Table 161.Transmit Descriptor Base Address register(TxDescriptor - address 0xFFE0 011C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Table 162.Transmit Status Base Address register (TxStatus address 0xFFE0 0120) bit description . . . . . .157
Table 163.Transmit Number of Descriptors register(TxDescriptorNumber - address 0xFFE0 0124) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Table 164.Transmit Produce Index register (TxProduceIndex- address 0xFFE0 0128) bit description . . . . .158
Table 165.Transmit Consume Index register(TxConsumeIndex - address 0xFFE0 012C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .159
Table 166. Transmit Status Vector 0 register (TSV0 - address
0xFFE0 0158) bit description . . . . . . . . . . . . .159
Table 167.Transmit Status Vector 1 register (TSV1 - address
0xFFE0 015C) bit description . . . . . . . . . . . . .160
Table 168.Receive Status Vector register (RSV - address
0xFFE0 0160) bit description . . . . . . . . . . . . .161
Table 169.Flow Control Counter register(FlowControlCounter - address 0xFFE0 0170) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .162
Table 170.Flow Control Status register (FlowControlStatus address 0xFFE0 8174) bit description . . . . . .162
Table 171.Receive Filter Control register (RxFilterCtrl address 0xFFE0 0200) bit description . . . . . .162
Table 172.Receive Filter WoL Status register(RxFilterWoLStatus - address 0xFFE0 0204) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Table 173.Receive Filter WoL Clear register(RxFilterWoLClear - address 0xFFE0 0208) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .164
Table 174.Hash Filter Table LSBs register (HashFilterL address 0xFFE0 0210) bit description . . . . . .164
Table 175.Hash Filter MSBs register (HashFilterH - address
0xFFE0 0214) bit description . . . . . . . . . . . . .164
Table 176.Interrupt Status register (IntStatus - address
0xFFE0 0FE0) bit description . . . . . . . . . . . . .165
Table 177.Interrupt Enable register (intEnable - address

0xFFE0 0FE4) bit description . . . . . . . . . . . . 166
Table 178.Interrupt Clear register (IntClear - address
0xFFE0 0FE8) bit description . . . . . . . . . . . . 166
Table 179.Interrupt Set register (IntSet - address
0xFFE0 0FEC) bit description . . . . . . . . . . . . 167
Table 180.Power Down register (PowerDown - address
0xFFE0 0FF4) bit description. . . . . . . . . . . . . 167
Table 181.Receive Descriptor Fields . . . . . . . . . . . . . . . 169
Table 182.Receive Descriptor Control Word. . . . . . . . . . 169
Table 183.Receive Status Fields . . . . . . . . . . . . . . . . . . 169
Table 184.Receive Status HashCRC Word . . . . . . . . . . 170
Table 185.Receive status information word . . . . . . . . . . 170
Table 186.Transmit descriptor fields . . . . . . . . . . . . . . . . 172
Table 187.Transmit descriptor control word . . . . . . . . . . 172
Table 188.Transmit status fields . . . . . . . . . . . . . . . . . . . 172
Table 189.Transmit status information word . . . . . . . . . . 173
Table 190.CAN Pin descriptions . . . . . . . . . . . . . . . . . . . 209
Table 191.Memory Map of the CAN Block . . . . . . . . . . . 214
Table 192.CAN acceptance filter and central CAN registers
214
Table 193.CAN1 and CAN2 controller register map . . . . 214
Table 194.CAN1 and CAN2 controller register map . . . . 215
Table 195. Mode register (CAN1MOD - address
0xE004 4000, CAN2MOD - address
0xE004 8000) bit description . . . . . . . . . . . . . 216
Table 196.Command Register (CAN1CMR - address
0xE004 4004, CAN2CMR - address
0xE004 8004) bit description . . . . . . . . . . . . . 218
Table 197. Global Status Register (CAN1GSR - address
0xE004 4008, CAN2GSR - address
0xE004 8008) bit description . . . . . . . . . . . . . 219
Table 198.Interrupt and Capture Register (CAN1ICR address 0xE004 400C, CAN2ICR - address
0xE004 800C) bit description. . . . . . . . . . . . . 222
Table 199.Interrupt Enable Register (CAN1IER - address
0xE004 4010, CAN2IER - address 0xE004 8010)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 200. Bus Timing Register (CAN1BTR - address
0xE004 4014, CAN2BTR - address 0xE004 8014)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 201.Error Warning Limit register (CAN1EWL - address
0xE004 4018, CAN2EWL - address
0xE004 8018) bit description . . . . . . . . . . . . . 228
Table 202. Status Register (CAN1SR - address
0xE004 401C, CAN2SR - address 0xE004 801C)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 203.Receive Frame Status register (CAN1RFS address 0xE004 4020, CAN2RFS - address
0xE004 8020) bit description . . . . . . . . . . . . . 230
Table 204.Receive Identifier Register (CAN1RID - address
0xE004 4024, CAN2RID - address 0xE004 8024)

continued >>UM10211_1

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Chapter 32: Supplementary information

bit description . . . . . . . . . . . . . . . . . . . . . . . . .231
Table 205.RX Identifier register when FF = 1 . . . . . . . . .231
Table 206.Receive Data register A (CAN1RDA - address
0xE004 4028, CAN2RDA - address
0xE004 8028) bit description . . . . . . . . . . . . .231
Table 207.Receive Data register B (CAN1RDB - address
0xE004 402C, CAN2RDB - address
0xE004 802C) bit description . . . . . . . . . . . . .232
Table 208.Transmit Frame Information Register(CAN1TFI[1/2/3] - address 0xE004 40[30/40/50],
CAN2TFI[1/2/3] - 0xE004 80[30/40/50]) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .233
Table 209.Transfer Identifier Register (CAN1TID[1/2/3] address 0xE004 40[34/44/54], CAN2TID[1/2/3] address 0xE004 80[34/44/54]) bit description 234
Table 210.Transfer Identifier register when FF = 1 . . . . .234
Table 211. Transmit Data Register A (CAN1TDA[1/2/3] address 0xE004 40[38/48/58], CAN2TDA[1/2/3] address 0xE004 80[38/48/58]) bit description 234
Table 212.Transmit Data Register B (CAN1TDB[1/2/3] address 0xE004 40[3C/4C/5C], CAN2TDB[1/2/3]- address 0xE004 80[3C/4C/5C]) bit description .
235
Table 213.Central Transit Status Register (CANTxSR address 0xE004 0000) bit description . . . . . .236
Table 214.Central Receive Status Register (CANRxSR address 0xE004 0004) bit description . . . . . .237
Table 215.Central Miscellaneous Status Register (CANMSR- address 0xE004 0008) bit description . . . . .237
Table 216.Acceptance filter modes and access control .238
Table 217.Section configuration register settings . . . . . .239
Table 218.Acceptance Filter Mode Register (AFMR address 0xE003 C000) bit description . . . . . .242
Table 219.Standard Frame Individual Start Address Register(SFF_sa - address 0xE003 C004) bit description.
243
Table 220.Standard Frame Group Start Address Register(SFF_GRP_sa - address 0xE003 C008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .243
Table 221.Extended Frame Start Address Register (EFF_sa- address 0xE003 C00C) bit description . . . . .244
Table 222.Extended Frame Group Start Address Register(EFF_GRP_sa - address 0xE003 C010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .244
Table 223.End of AF Tables Register (ENDofTable - address
0xE003 C014) bit description . . . . . . . . . . . . .245
Table 224.LUT Error Address Register (LUTerrAd - address
0xE003 C018) bit description . . . . . . . . . . . . .245
Table 225.LUT Error Register (LUTerr - address
0xE003 C01C) bit description . . . . . . . . . . . . .246
Table 226.Global FullCAN Enable register (FCANIE -address 0xE003 C020) bit description . . . . . . 246
Table 227.FullCAN Interrupt and Capture register 0(FCANIC0 - address 0xE003 C024) bit description
246
Table 228.FullCAN Interrupt and Capture register 1(FCANIC1 - address 0xE003 C028) bit description
246
Table 229.Format of automatically stored Rx messages 250
Table 230.FullCAN semaphore operation. . . . . . . . . . . . 250
Table 231.Example of Acceptance Filter Tables and ID index
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 232.Used ID-Look-up Table sections . . . . . . . . . . 262
Table 233.Used ID-Look-up Table sections . . . . . . . . . . 263
Table 234.USB related acronyms, abbreviations, anddefinitions used in this chapter. . . . . . . . . . . . 267
Table 235.Fixed endpoint configuration . . . . . . . . . . . . . 268
Table 236.USB external interface . . . . . . . . . . . . . . . . . . 271
Table 237.USB device controller clock sources . . . . . . . 272
Table 238.USB device register map . . . . . . . . . . . . . . . . 274
Table 239.USB Port Select register (USBPortSel - address
0xFFE0 C110) bit description. . . . . . . . . . . . . 275
Table 240.USBClkCtrl register (USBClkCtrl - address
0xFFE0 CFF4) bit description . . . . . . . . . . . . 276
Table 241.USB Clock Status register (USBClkSt - 0xFFE0
CFF8) bit description . . . . . . . . . . . . . . . . . . . 276
Table 242.USB Interrupt Status register (USBIntSt - address
0xE01F C1C0) bit description . . . . . . . . . . . . 277
Table 243.USB Device Interrupt Status register(USBDevIntSt - address 0xFFE0 C200) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 244.USB Device Interrupt Status register(USBDevIntSt - address 0xFFE0 C200) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 245.USB Device Interrupt Enable register(USBDevIntEn - address 0xFFE0 C204) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 246.USB Device Interrupt Enable register(USBDevIntEn - address 0xFFE0 C204) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 247.USB Device Interrupt Clear register(USBDevIntClr - address 0xFFE0 C208) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 248.USB Device Interrupt Clear register(USBDevIntClr - address 0xFFE0 C208) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 249.USB Device Interrupt Set register (USBDevIntSet- address 0xFFE0 C20C) bit allocation . . . . 279
Table 250.USB Device Interrupt Set register (USBDevIntSet- address 0xFFE0 C20C) bit description. . . . 279
Table 251.USB Device Interrupt Priority register(USBDevIntPri - address 0xFFE0 C22C) bit

continued >>UM10211_1

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description . . . . . . . . . . . . . . . . . . . . . . . . . . .280
Table 252.USB Endpoint Interrupt Status register(USBEpIntSt - address 0xFFE0 C230) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .280
Table 253.USB Endpoint Interrupt Status register(USBEpIntSt - address 0xFFE0 C230) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .281
Table 254.USB Endpoint Interrupt Enable register(USBEpIntEn - address 0xFFE0 C234) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
Table 255.USB Endpoint Interrupt Enable register(USBEpIntEn - address 0xFFE0 C234) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .282
Table 256.USB Endpoint Interrupt Clear register(USBEpIntClr - address 0xFFE0 C238) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
Table 257.USB Endpoint Interrupt Clear register(USBEpIntClr - address 0xFFE0 C238) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .283
Table 258.USB Endpoint Interrupt Set register (USBEpIntSet- address 0xFFE0 C23C) bit allocation . . . . .283
Table 259.USB Endpoint Interrupt Set register (USBEpIntSet- address 0xFFE0 C23C) bit description . . . .283
Table 260.USB Endpoint Interrupt Priority register(USBEpIntPri - address 0xFFE0 C240) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
Table 261.USB Endpoint Interrupt Priority register(USBEpIntPri - address 0xFFE0 C240) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .284
Table 262.USB Realize Endpoint register (USBReEp address 0xFFE0 C244) bit allocation . . . . . .285
Table 263.USB Realize Endpoint register (USBReEp address 0xFFE0 C244) bit description . . . . .285
Table 264.USB Endpoint Index register (USBEpIn - address
0xFFE0 C248) bit description . . . . . . . . . . . .286
Table 265.USB MaxPacketSize register (USBMaxPSize address 0xFFE0 C24C) bit description . . . . .286
Table 266.USB Receive Data register (USBRxData address 0xFFE0 C218) bit description . . . . .287
Table 267.USB Receive Packet Length register (USBRxPlen- address 0xFFE0 C220) bit description . . . .288
Table 268.USB Transmit Data register (USBTxData address 0xFFE0 C21C) bit description . . . . .288
Table 269.USB Transmit Packet Length register(USBTxPLen - address 0xFFE0 C224) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .289
Table 270.USB Control register (USBCtrl - address 0xFFE0
C228) bit description . . . . . . . . . . . . . . . . . . .289
Table 271.USB Command Code register (USBCmdCode address 0xFFE0 C210) bit description . . . . .290
Table 272.USB Command Data register (USBCmdData -address 0xFFE0 C214) bit description . . . . . 290
Table 273.USB DMA Request Status register (USBDMARSt- address 0xFFE0 C250) bit allocation . . . . . 290
Table 274.USB DMA Request Status register (USBDMARSt- address 0xFFE0 C250) bit description . . . . 291
Table 275.USB DMA Request Clear register (USBDMARClr- address 0xFFE0 C254) bit description . . . . 291
Table 276.USB DMA Request Set register (USBDMARSet address 0xFFE0 C258) bit description . . . . . 292
Table 277.USB UDCA Head register (USBUDCAH - address
0xFFE0 C280) bit description . . . . . . . . . . . . 292
Table 278.USB EP DMA Status register (USBEpDMASt address 0xFFE0 C284) bit description . . . . . 292
Table 279.USB EP DMA Enable register (USBEpDMAEn address 0xFFE0 C288) bit description . . . . . 293
Table 280.USB EP DMA Disable register (USBEpDMADis address 0xFFE0 C28C) bit description . . . . . 293
Table 281.USB DMA Interrupt Status register (USBDMAIntSt- address 0xFFE0 C290) bit description . . . . 294
Table 282.USB DMA Interrupt Enable register(USBDMAIntEn - address 0xFFE0 C294) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 283.USB End of Transfer Interrupt Status register(USBEoTIntSt - address 0xFFE0 C2A0s) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 284.USB End of Transfer Interrupt Clear register(USBEoTIntClr - address 0xFFE0 C2A4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 285.USB End of Transfer Interrupt Set register(USBEoTIntSet - address 0xFFE0 C2A8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 286.USB New DD Request Interrupt Status register(USBNDDRIntSt - address 0xFFE0 C2AC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 287.USB New DD Request Interrupt Clear register(USBNDDRIntClr - address 0xFFE0 C2B0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Table 288.USB New DD Request Interrupt Set register(USBNDDRIntSet - address 0xFFE0 C2B4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Table 289.USB System Error Interrupt Status register(USBSysErrIntSt - address 0xFFE0 C2B8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Table 290.USB System Error Interrupt Clear register(USBSysErrIntClr - address 0xFFE0 C2BC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 291.USB System Error Interrupt Set register(USBSysErrIntSet - address 0xFFE0 C2C0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 292.SIE command code table . . . . . . . . . . . . . . . . 301
Table 293.Device Set Address Register bit description . 301

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

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Chapter 32: Supplementary information

Table 294.Configure Device Register bit description. . . .302
Table 295.Set Mode Register bit description. . . . . . . . . .302
Table 296.Set Device Status Register bit description . . .303
Table 297.Get Error Code Register bit description . . . . .305
Table 298.Read Error Status Register bit description . . .305
Table 299.Select Endpoint Register bit description . . . . .306
Table 300.Set Endpoint Status Register bit description. .307
Table 301.Clear Buffer Register bit description . . . . . . . .308
Table 302.DMA descriptor . . . . . . . . . . . . . . . . . . . . . . . .313
Table 303:UART0 Pin description . . . . . . . . . . . . . . . . . .326
Table 304:UART Register Map . . . . . . . . . . . . . . . . . . . .327
Table 305:UARTn Receiver Buffer Register (U0RBR address 0xE000 C000, U2RBR - 0xE007 8000,
U3RBR - 0E007 C000 when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . .329
Table 306:UART0 Transmit Holding Register (U0THR address 0xE000 C000, U2THR - 0xE007 8000,
U3THR - 0xE007 C000 when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . .329
Table 307:UARTn Divisor Latch LSB Register (U0DLL address 0xE000 C000, U2DLL - 0xE007 8000,
U3DLL - 0xE007 C000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .330
Table 308:UARTn Divisor Latch MSB Register (U0DLM address 0xE000 C004, U2DLM - 0xE007 8004,
U3DLM - 0xE007 C004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .330
Table 309:UARTn Interrupt Enable Register (U0IER address 0xE000 C004, U2IER - 0xE007 8004,
U3IER - 0xE007 C004 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .330
Table 310:UARTn Interrupt Identification Register (U0IIR address 0xE000 C008, U2IIR - 0x7008 8008,
U3IIR - 0x7008 C008, Read Only) bit description.
331
Table 311: UARTn Interrupt Handling . . . . . . . . . . . . . . .332
Table 312:UARTn FIFO Control Register (U0FCR - address
0xE000 C008, U2FCR - 0xE007 8008, U3FCR 0xE007 C008, Write Only) bit description. . . .333
Table 313:UARTn Line Control Register (U0LCR - address
0xE000 C00C, U2LCR - 0xE007 800C, U3LCR 0xE007 C00C) bit description . . . . . . . . . . . . .334
Table 314:UARTn Line Status Register (U0LSR - address
0xE000 C014, U2LSR - 0xE007 8014, U3LSR 0xE007 C014, Read Only) bit description. . . .334
Table 315:UARTn Scratch Pad Register (U0SCR - address
0xE000 C01C, U2SCR - 0xE007 801C, U3SCR 0xE007 C01C) bit description . . . . . . . . . . . . .336
Table 316:UARTn Auto-baud Control Register (U0ACR 0xE000 C020, U2ACR - 0xE007 8020, U3ACR 0xE007 C020) bit description . . . . . . . . . . . . .336

Table 317:IrDA Control Register for UART3 only (U3ICR address 0xE007 C024) bit description . . . . . . 339
Table 318:IrDA Pulse Width . . . . . . . . . . . . . . . . . . . . . . 339
Table 319:UARTn Fractional Divider Register (U0FDR address 0xE000 C028, U2FDR - 0xE007 8028,
U3FDR - 0xE007 C028) bit description . . . . . 340
Table 320:Baud-rates available when using 20 MHz
peripheral clock (PCLK = 20 MHz). . . . . . . . . 341
Table 321:UARTn Transmit Enable Register (U0TER address 0xE000 C030, U2TER - 0xE007 8030,
U3TER - 0xE007 C030) bit description . . . . . 343
Table 322:UART1 Pin Description . . . . . . . . . . . . . . . . . 345
Table 323:UART1 register map . . . . . . . . . . . . . . . . . . . 347
Table 324:UART1 Receiver Buffer Register (U1RBR address 0xE001 0000 when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . 349
Table 325:UART1 Transmitter Holding Register (U1THR address 0xE001 0000 when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . . 349
Table 326:UART1 Divisor Latch LSB Register (U1DLL address 0xE001 0000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Table 327:UART1 Divisor Latch MSB Register (U1DLM address 0xE001 0004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Table 328:UART1 Interrupt Enable Register (U1IER address 0xE001 0004 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Table 329:UART1 Interrupt Identification Register (U1IIR address 0xE001 0008, Read Only) bit description
351
Table 330:UART1 Interrupt Handling . . . . . . . . . . . . . . . 353
Table 331:UART1 FIFO Control Register (U1FCR - address
0xE001 0008, Write Only) bit description. . . . 354
Table 332:UART1 Line Control Register (U1LCR - address
0xE001 000C) bit description. . . . . . . . . . . . . 354
Table 333:UART1 Modem Control Register (U1MCR address 0xE001 0010) bit description . . . . . . 355
Table 334:Modem status interrupt generation . . . . . . . . 357
Table 335:UART1 Line Status Register (U1LSR - address
0xE001 0014, Read Only) bit description . . . 358
Table 336:UART1 Modem Status Register (U1MSR address 0xE001 0018) bit description . . . . . . 359
Table 337:UART1 Scratch Pad Register (U1SCR - address
0xE001 0014) bit description . . . . . . . . . . . . . 360
Table 338:Auto-baud Control Register (U1ACR - address
0xE001 0020) bit description . . . . . . . . . . . . . 360
Table 339:UART1 Fractional Divider Register (U1FDR address 0xE001 C028) bit description . . . . . . 364
Table 340:Baud-rates available when using 20 MHz
peripheral clock (PCLK = 20 MHz). . . . . . . . . 365

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

594 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

Table 341:UART1 Transmit Enable Register (U1TER address 0xE001 0030) bit description . . . . . .366
Table 342.SPI Data To Clock Phase Relationship. . . . . .370
Table 343.SPI Pin Description. . . . . . . . . . . . . . . . . . . . .374
Table 344.SPI Register Map . . . . . . . . . . . . . . . . . . . . . .374
Table 345:SPI Control Register (S0SPCR - address
0xE002 0000) bit description . . . . . . . . . . . . .375
Table 346:SPI Status Register (S0SPSR - address
0xE002 0004) bit description . . . . . . . . . . . . .376
Table 347:SPI Data Register (S0SPDR - address
0xE002 0008) bit description . . . . . . . . . . . . .377
Table 348:SPI Clock Counter Register (S0SPCCR - address
0xE002 000C) bit description . . . . . . . . . . . . .377
Table 349:SPI Test Control Register (SPTCR - address
0xE002 0010) bit description . . . . . . . . . . . . .377
Table 350:SPI Test Status Register (SPTSR - address
0xE002 0014) bit description . . . . . . . . . . . . .378
Table 351:SPI Interrupt Register (S0SPINT - address
0xE002 001C) bit description . . . . . . . . . . . . .378
Table 352.SSP pin descriptions . . . . . . . . . . . . . . . . . . .381
Table 353.SSP Register Map . . . . . . . . . . . . . . . . . . . . .389
Table 354:SSPn Control Register 0 (SSP0CR0 - address
0xE006 8000, SSP1CR0 - 0xE003 0000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .390
Table 355:SSPn Control Register 1 (SSP0CR1 - address
0xE006 8004, SSP1CR1 - 0xE003 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .391
Table 356:SSPn Data Register (SSP0DR - address
0xE006 8008, SSP1DR - 0xE003 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .391
Table 357:SSPn Status Register (SSP0SR - address
0xE006 800C, SSP1SR - 0xE003 000C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .392
Table 358:SSPn Clock Prescale Register (SSP0CPSR address 0xE006 8010, SSP1CPSR 0xE003 8010) bit description . . . . . . . . . . . . .392
Table 359:SSPn Interrupt Mask Set/Clear register(SSP0IMSC - address 0xE006 8014, SSP1IMSC- 0xE003 0014) bit description . . . . . . . . . . . .393
Table 360:SSPn Raw Interrupt Status register (SSP0RIS address 0xE006 8018, SSP1RIS - 0xE003 0018)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .393
Table 361:SSPn Masked Interrupt Status register (SSPnMIS-address 0xE006 801C, SSP1MIS 0xE003 001C) bit description . . . . . . . . . . . . .394
Table 362:SSPn interrupt Clear Register (SSP0ICR address 0xE006 8020, SSP1ICR - 0xE003 0020)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .394
Table 363:SSPn DMA Control Register (SSP0DMACR address 0xE006 8024, SSP1DMACR 0xE003 0024) bit description . . . . . . . . . . . . .394

Table 364.SD/MMC card interface pin description . . . . . 395
Table 365.Command format . . . . . . . . . . . . . . . . . . . . . . 399
Table 366.Simple response format . . . . . . . . . . . . . . . . . 400
Table 367.Long response format . . . . . . . . . . . . . . . . . . 400
Table 368.Command path status flags . . . . . . . . . . . . . . 400
Table 369.CRC token status . . . . . . . . . . . . . . . . . . . . . . 404
Table 370.Data path status flags . . . . . . . . . . . . . . . . . . 404
Table 371.Transmit FIFO status flags. . . . . . . . . . . . . . . 405
Table 372.Receive FIFO status flags . . . . . . . . . . . . . . . 406
Table 373.SPI register map . . . . . . . . . . . . . . . . . . . . . . 406
Table 374:Power Control register (MCIPower - address
0xE008 C000) bit description. . . . . . . . . . . . . 407
Table 375:Clock Control register (MCIClock - address
0xE008 C004) bit description. . . . . . . . . . . . . 408
Table 376:Argument register (MCIArgument - address
0xE008 C008) bit description. . . . . . . . . . . . . 408
Table 377:Command register (MCICommand - address
0xE008 C00C) bit description . . . . . . . . . . . . 409
Table 378:Command Response Types. . . . . . . . . . . . . . 409
Table 379:Command Response register(MCIRespCommand - address 0xE008 C010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Table 380:Response registers (MCIResponse0-3 addresses 0xE008 0014, 0xE008 C018,
0xE008 001C and 0xE008 C020) bit description .
410
Table 381:Response Register Type . . . . . . . . . . . . . . . . 410
Table 382:Data Timer register (MCIDataTimer - address
0xE008 C024) bit description. . . . . . . . . . . . . 410
Table 383:Data Length register (MCIDataLength - address
0xE008 C028) bit description. . . . . . . . . . . . . 410
Table 384:Data Control register (MCIDataCtrl - address
0xE008 C02C) bit description . . . . . . . . . . . . 411
Table 385:Data Block Length . . . . . . . . . . . . . . . . . . . . . 411
Table 386:Data Counter register (MCIDataCnt - address
0xE008 C030) bit description. . . . . . . . . . . . . 412
Table 387:Status register (MCIStatus - address
0xE008 C034) bit description. . . . . . . . . . . . . 412
Table 388:Clear register (MCIClear - address 0xE008 C038)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 413
Table 389:Interrupt Mask registers (MCIMask0 - address
0xE008 C03C and MCIMask1 - address
0xE008 C040) bit description. . . . . . . . . . . . . 413
Table 390:FIFO Counter register (MCIFifoCnt - address
0xE008 C048) bit description. . . . . . . . . . . . . 414
Table 391:Data FIFO register (MCIFIFO - address
0xE008 C080 to 0xE008 C0BC) bit description . .
415
Table 392.I2C Pin Description. . . . . . . . . . . . . . . . . . . . . 417
Table 393.I2CnCONSET used to configure Master mode . .
418

continued >>UM10211_1

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Rev. 01 — 6 July 2007

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Chapter 32: Supplementary information

Table 394.I2CnCONSET used to configure Slave mode.419
Table 395.I2C register map . . . . . . . . . . . . . . . . . . . . . . .425
Table 396.I2C Control Set Register (I2C[0/1/2]CONSET addresses: 0xE001 C000, 0xE005 C000,
0xE008 0000) bit description . . . . . . . . . . . . .426
Table 397.I2C Control Set Register (I2C[0/1/2]CONCLR addresses 0xE001 C018, 0xE005 C018,
0xE008 0018) bit description . . . . . . . . . . . . .428
Table 398.I2C Status Register (I2C[0/1/2]STAT - addresses
0xE001 C004, 0xE005 C004, 0xE008 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .428
Table 399.I2C Data Register ( I2C[0/1/2]DAT - addresses
0xE001 C008, 0xE005 C008, 0xE008 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .429
Table 400.I2C Slave Address register (I2C[0/1/2]ADR addresses 0xE001 C00C, 0xE005 C00C,
0xE008 000C) bit description . . . . . . . . . . . . .429
Table 401.I2C SCL High Duty Cycle register(I2C[0/1/2]SCLH - addresses 0xE001 C010,
0xE005 C010, 0xE008 0010) bit description .429
Table 402.I2C SCL Low Duty Cycle register (I2C[0/1/2]SCLL- addresses 0xE001 C014, 0xE005 C014,
0xE008 0014) bit description . . . . . . . . . . . . .429
Table 403.Example I2C Clock Rates . . . . . . . . . . . . . . . .430
Table 404.Abbreviations used to describe an I2C operation .
430
Table 405.I2CONSET used to initialize Master Transmittermode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431
Table 406.I2C0ADR and I2C1ADR usage in Slave Receivermode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .432
Table 407.I2C0CONSET and I2C1CONSET used to initialize
Slave Receiver mode . . . . . . . . . . . . . . . . . . .432
Table 408.Master Transmitter mode . . . . . . . . . . . . . . . .438
Table 409.Master Receiver mode . . . . . . . . . . . . . . . . . .439
Table 410.Slave Receiver Mode . . . . . . . . . . . . . . . . . . .440
Table 411. Tad_105: Slave Transmitter mode . . . . . . . . .442
Table 412.Miscellaneous states . . . . . . . . . . . . . . . . . . .444
Table 413.Pin descriptions . . . . . . . . . . . . . . . . . . . . . . .456
Table 414.I2S register map . . . . . . . . . . . . . . . . . . . . . . .457
Table 415:Digital Audio Output register (I2SDAO - address
0xE008 8000) bit description . . . . . . . . . . . . .458
Table 416:Digital Audio Input register (I2SDAI - address
0xE008 8004) bit description . . . . . . . . . . . . .459
Table 417:Transmit FIFO register (I2STXFIFO - address
0xE008 8008) bit description . . . . . . . . . . . . .459
Table 418:Receive FIFO register (I2RXFIFO - address
0xE008 800C) bit description . . . . . . . . . . . . .459
Table 419:Status Feedback register (I2SSTATE - address
0xE008 8010) bit description . . . . . . . . . . . . .459
Table 420:DMA Configuration register 1 (I2SDMA1 - address
0xE008 8014) bit description . . . . . . . . . . . . .460

Table 421:DMA Configuration register 2 (I2SDMA2 - address
0xE008 8018) bit description . . . . . . . . . . . . . 460
Table 422:Interrupt Request Control register (I2SIRQ address 0xE008 801C) bit description . . . . . . 461
Table 423:Transmit Clock Rate register (I2TXRATE address 0xE008 8020) bit description . . . . . . 461
Table 424:Receive Clock Rate register (I2SRXRATE address 0xE008 8024) bit description . . . . . . 461
Table 425.Conditions for FIFO level comparison . . . . . . 463
Table 426.DMA and interrupt request generation. . . . . . 463
Table 427.Status feedback in the I2SSTATE register . . . 463
Table 428.Timer/Counter pin description . . . . . . . . . . . . 466
Table 429.TIMER/COUNTER0-3 register map. . . . . . . . 466
Table 430:Interrupt Register (T[0/1/2/3]IR - addresses
0xE000 4000, 0xE000 8000, 0xE007 0000,
0xE007 4000) bit description . . . . . . . . . . . . . 468
Table 431:Timer Control Register (TCR, TIMERn: TnTCR addresses 0xE000 4004, 0xE000 8004,
0xE007 0004, 0xE007 4004) bit description . 468
Table 432:Count Control Register (T[0/1/2/3]CTCR addresses 0xE000 4070, 0xE000 8070,
0xE007 0070, 0xE007 4070) bit description . 469
Table 433:Match Control Register (T[0/1/2/3]MCR addresses 0xE000 4014, 0xE000 8014,
0xE007 0014, 0xE007 4014) bit description . 470
Table 434:Capture Control Register (T[0/1/2/3]CCR addresses 0xE000 4028, 0xE000 8020,
0xE007 0028, 0xE007 4028) bit description . 472
Table 435:External Match Register (T[0/1/2/3]EMR addresses 0xE000 403C, 0xE000 803C,
0xE007 003C, 0xE007 403C) bit description . 473
Table 436.External Match Control . . . . . . . . . . . . . . . . . 473
Table 437.Watchdog register map . . . . . . . . . . . . . . . . . 477
Table 438.Watchdog operating modes selection . . . . . . 478
Table 439:Watchdog Mode register (WDMOD - address
0xE000 0000) bit description . . . . . . . . . . . . . 478
Table 440:Watchdog Constant register (WDTC - address
0xE000 0004) bit description . . . . . . . . . . . . . 478
Table 441:Watchdog Feed Register (WDFEED - address
0xE000 0008) bit description . . . . . . . . . . . . . 479
Table 442:Watchdog Timer Value register (WDTV - address
0xE000 000C) bit description. . . . . . . . . . . . . 479
Table 443:Watchdog Timer Clock Source Selection register(WDCLKSEL - address 0xE000 0010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Table 444.Set and reset inputs for PWM Flip-Flops . . . . 484
Table 445.Pin summary . . . . . . . . . . . . . . . . . . . . . . . . . 485
Table 446:Addresses for PWM1 . . . . . . . . . . . . . . . . . . . 486
Table 447.PWM1 register map . . . . . . . . . . . . . . . . . . . . 486
Table 448:PWM Interrupt Register (PWM1IR - address
0xE001 8000) bit description . . . . . . . . . . . . . 487

continued >>UM10211_1

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Rev. 01 — 6 July 2007

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Chapter 32: Supplementary information

Table 449:PWM Timer Control Register (PWM1TCR address 0xE001 8004) bit description . . . . . .488
Table 450:PWM Count control Register (PWM1CTCR address 0xE001 8004) bit description . . . . . .489
Table 451:Match Control Register (PWM1MCR - address
0xE000 8014) bit description . . . . . . . . . . . . .489
Table 452:PWM Capture Control Register (PWM1CCR address 0xE001 8028) bit description . . . . . .491
Table 453:PWM Control Registers (PWM1PCR - address
0xE001 804C) bit description . . . . . . . . . . . . .492
Table 454:PWM Latch Enable Register (PWM1LER address 0xE001 8050) bit description . . . . . .494
Table 455.A/D pin description . . . . . . . . . . . . . . . . . . . . .495
Table 456.A/D registers . . . . . . . . . . . . . . . . . . . . . . . . . .496
Table 457:A/D Control Register (AD0CR - address
0xE003 4000) bit description . . . . . . . . . . . . .497
Table 458:A/D Global Data Register (AD0GDR - address
0xE003 4004) bit description . . . . . . . . . . . . .498
Table 459:A/D Status Register (AD0STAT - address
0xE003 4030) bit description . . . . . . . . . . . . .499
Table 460:A/D Interrupt Enable Register (AD0INTEN address 0xE003 400C) bit description . . . . . .499
Table 461:A/D Data Registers (AD0DR0 to AD0DR7 addresses 0xE003 4010 to 0xE003 402C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .500
Table 462.D/A Pin Description . . . . . . . . . . . . . . . . . . . .501
Table 463:D/A Converter Register (DACR - address
0xE006 C000) bit description . . . . . . . . . . . . .501
Table 464.Real Time Clock register map . . . . . . . . . . . .504
Table 465.Miscellaneous registers . . . . . . . . . . . . . . . . .506
Table 466.Interrupt Location Register (ILR - address
0xE002 4000) bit description . . . . . . . . . . . . .506
Table 467.Clock Tick Counter Register (CTCR - address
0xE002 4004) bit description . . . . . . . . . . . . .507
Table 468.Clock Control Register (CCR - address
0xE002 4008) bit description . . . . . . . . . . . . .507
Table 469.Counter Increment Interrupt Register (CIIR address 0xE002 400C) bit description . . . . . .507
Table 470.Counter Increment Select Mask register (CISS address 0xE002 4040) bit description . . . . . .508
Table 471.Alarm Mask Register (AMR - address
0xE002 4010) bit description . . . . . . . . . . . . .509
Table 472.Consolidated Time register 0 (CTIME0 - address
0xE002 4014) bit description . . . . . . . . . . . . .509
Table 473.Consolidated Time register 1 (CTIME1 - address
0xE002 4018) bit description . . . . . . . . . . . . .510
Table 474.Consolidated Time register 2 (CTIME2 - address
0xE002 401C) bit description . . . . . . . . . . . . .510
Table 475.Time Counter relationships and values) . . . . .510
Table 476.Time Counter registers . . . . . . . . . . . . . . . . . .510
Table 477.Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 511

Table 478.Reference Clock Divider registers . . . . . . . . . 513
Table 479:Prescaler Integer register (PREINT - address
0xE002 4080) bit description . . . . . . . . . . . . . 513
Table 480:Prescaler Integer register (PREFRAC - address
0xE002 4084) bit description . . . . . . . . . . . . . 513
Table 481.Prescaler cases where the Integer Counter reload
value is incremented . . . . . . . . . . . . . . . . . . . 515
Table 482.Recommended values for the RTC external
32 kHz oscillator CX1/X2 components . . . . . . . 516
Table 483.Sectors in a LPC2300 device. . . . . . . . . . . . . 522
Table 484.Code Rad Protection options . . . . . . . . . . . . . 523
Table 485.Code Read Protection hardware/softwareinteraction . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
Table 486.ISP command summary. . . . . . . . . . . . . . . . . 524
Table 487.ISP Unlock command . . . . . . . . . . . . . . . . . . 525
Table 488.ISP Set Baud Rate command . . . . . . . . . . . . 525
Table 489.Correlation between possible ISP baudrates and
CCLK frequency (in MHz) . . . . . . . . . . . . . . . 525
Table 490.ISP Echo command . . . . . . . . . . . . . . . . . . . . 526
Table 491.ISP Write to RAM command . . . . . . . . . . . . . 526
Table 492.ISP Read Memory command. . . . . . . . . . . . . 527
Table 493.ISP Prepare sector(s) for write operationcommand . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Table 494.ISP Copy command . . . . . . . . . . . . . . . . . . . . 528
Table 495.ISP Go command. . . . . . . . . . . . . . . . . . . . . . 528
Table 496.ISP Erase sector command . . . . . . . . . . . . . . 529
Table 497.ISP Blank check sector command . . . . . . . . . 529
Table 498.ISP Read Part Identification command . . . . . 529
Table 499.LPC2300 part Identification numbers. . . . . . . 530
Table 500.ISP Read Boot Code version number command .
530
Table 501.ISP Compare command. . . . . . . . . . . . . . . . . 530
Table 502.ISP Return Codes Summary . . . . . . . . . . . . . 531
Table 503.IAP Command Summary . . . . . . . . . . . . . . . . 533
Table 504.IAP Prepare sector(s) for write operationcommand . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Table 505.IAP Copy RAM to flash command . . . . . . . . . 534
Table 506.IAP Erase Sector(s) command . . . . . . . . . . . 535
Table 507.IAP Blank check sector(s) command . . . . . . . 535
Table 508.IAP Read Part Identification command . . . . . 535
Table 509.IAP Read Boot Code version number command .
536
Table 510.IAP Compare command. . . . . . . . . . . . . . . . . 536
Table 511. Reinvoke ISP . . . . . . . . . . . . . . . . . . . . . . . . . 536
Table 512.IAP Status Codes Summary . . . . . . . . . . . . . 537
Table 513.Endian behavior . . . . . . . . . . . . . . . . . . . . . . . 541
Table 514.DMA Connections . . . . . . . . . . . . . . . . . . . . . 544
Table 515.GPDMA register map. . . . . . . . . . . . . . . . . . . 547
Table 516.Interrupt Status register (DMACIntStatus address 0xFFE0 4000) bit description . . . . . . 548
Table 517.Interrupt Terminal Count Status register

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

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UM10211NXP Semiconductors

Chapter 32: Supplementary information(DMACIntTCStatus - address 0xFFE0 4004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .549
Table 518.Interrupt Terminal Count Clear register(DMACIntClear - address 0xFFE0 4008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .549
Table 519.Interrupt Error Status register(DMACIntErrorStatus - address 0xFFE0 400C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .549
Table 520.Interrupt Error Clear register (DMACIntErrClr address 0xFFE0 4010) bit description . . . . . .550
Table 521.Raw Interrupt Terminal Count Status register(DMACRawIntTCStatus - address 0xFFE0 4014)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .550
Table 522.Raw Error Interrupt Status register(DMACRawIntErrorStatus - address
0xFFE0 4018) bit description . . . . . . . . . . . . .551
Table 523.Enabled Channel register (DMACEnbldChns address 0xFFE0 401C) bit description . . . . . .551
Table 524.Software Burst Request register (DMACSoftBReq- address 0xFFE0 4020) bit description . . . . .551
Table 525.Software Single Request register(DMACSoftSReq - address 0xFFE0 4024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .552
Table 526.Software Last Burst Request register(DMACSoftLBReq - address 0xFFE0 4028) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .552
Table 527.Software Last Single Request register(DMACSoftLSReq - address 0xFFE0 402C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .553
Table 528.Configuration register (DMACConfiguration address 0xFFE0 4030) bit description . . . . . .553
Table 529.Synchronization register (DMACSync - address
0xFFE0 4034) bit description . . . . . . . . . . . . .554
Table 530.Channel Source Address registers(DMACC0SrcAddr - address 0xFFE0 4100 and
DMACC1SrcAddr - address 0xFFE0 4120) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .554
Table 531.Channel Destination Address registers(DMACC0DestAddr - address 0xFFE0 4104 andDMACC1DestAddr - address 0xFFE0 4124) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .555
Table 532.Channel Linked List Item registers (DMACC0LLI address 0xFFE0 4108 and DMACC1LLI - address
0xFFE0 4128) bit description . . . . . . . . . . . . .555
Table 533.Channel Control registers (DMACC0Control address 0xFFE0 410C and DMACC1Control address 0xFFE0 412C) bit description . . . . . .556
Table 534.Source or destination burst size . . . . . . . . . . .556
Table 535.Source or destination transfer width . . . . . . . .557
Table 536.Protection bits . . . . . . . . . . . . . . . . . . . . . . . . .557
Table 537.Channel Configuration registers(DMACC0Configuration - address 0xFFE0 4110
and DMACC1Configuration - address
0xFFE0 4130) bit description . . . . . . . . . . . . . 558
Table 538.Flow control and transfer type bits . . . . . . . . . 560
Table 539.DMA request signal usage. . . . . . . . . . . . . . . 564
Table 540.EmbeddedICE pin description . . . . . . . . . . . . 568
Table 541.EmbeddedICE logic registers . . . . . . . . . . . . 569
Table 542.ETM configuration . . . . . . . . . . . . . . . . . . . . . 570
Table 543.ETM pin description . . . . . . . . . . . . . . . . . . . . 571
Table 544.ETM Registers . . . . . . . . . . . . . . . . . . . . . . . . 572
Table 545.RealMonitor stack requirement . . . . . . . . . . . 577
Table 546.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 585

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

598 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

4. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Fig 29.
Fig 30.
Fig 31.
Fig 32.
Fig 33.
Fig 34.
Fig 35.
Fig 36.
Fig 37.
Fig 38.

LPC2364/6/8 block diagram . . . . . . . . . . . . . . . . .8
LPC2378 block diagram . . . . . . . . . . . . . . . . . . . .9
LPC2364/66/68 system memory map . . . . . . . . . 11
LPC2378 system memory map . . . . . . . . . . . . . .12
Peripheral memory map. . . . . . . . . . . . . . . . . . . .13
AHB peripheral map . . . . . . . . . . . . . . . . . . . . . .14
Map of lower memory is showing re-mapped andre-mappable areas. . . . . . . . . . . . . . . . . . . . . . . .19
Reset block diagram including the wakeup timer.23
Clock generation for the LPC2300. . . . . . . . . . . .34
PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . .39
PLL and clock dividers . . . . . . . . . . . . . . . . . . . . .48
EMC block diagram . . . . . . . . . . . . . . . . . . . . . . .59
8 bit bank external memory interface. . . . . . . . . .71
Block diagram of the Vectored Interrupt Controller .
82
Simplified block diagram of the Memory Accelerator
Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Block diagram of the Memory Accelerator Module .
89
LPC2364/6/8 100 - pin packages. . . . . . . . . . . . .90
LPC2378 144 - pin package . . . . . . . . . . . . . . . .98
Ethernet block diagram . . . . . . . . . . . . . . . . . . .139
Ethernet packet fields . . . . . . . . . . . . . . . . . . . .141
Receive descriptor memory layout. . . . . . . . . . .168
Transmit descriptor memory layout . . . . . . . . . .171
Transmit example memory and registers. . . . . .182
Receive Example Memory and Registers . . . . .188
Transmit Flow Control . . . . . . . . . . . . . . . . . . . .193
Receive filter block diagram. . . . . . . . . . . . . . . .195
Receive Active/Inactive state machine . . . . . . .199
Transmit Active/Inactive state machine . . . . . . .200
CAN controller block diagram . . . . . . . . . . . . . .210
Transmit buffer layout for standard and extended
frame format configurations . . . . . . . . . . . . . . . . 211
Receive buffer layout for standard and extended
frame format configurations . . . . . . . . . . . . . . . .212
Global Self-Test (high-speed CAN Bus example) . .
213
Local Self-Test (high-speed CAN Bus example) 213
Entry in FullCAN and individual standard identifier
tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
Entry in standard identifier range table . . . . . . .240
Entry in either extended identifier table . . . . . . .240
ID Look-up table example explaining the searchalgorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
Semaphore procedure for reading an auto-stored
message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

Fig 39. FullCAN section example of the ID look-up table . .
253
Fig 40. FullCAN message object layout . . . . . . . . . . . . 253
Fig 41. Normal case, no messages lost . . . . . . . . . . . . 255
Fig 42. Message lost . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Fig 43. Message gets overwritten . . . . . . . . . . . . . . . . . 256
Fig 44. Message overwritten indicated by semaphore bits
and message lost . . . . . . . . . . . . . . . . . . . . . . . 257
Fig 45. Message overwritten indicated by message lost258
Fig 46. Clearing message lost. . . . . . . . . . . . . . . . . . . . 259
Fig 47. Detailed example of acceptance filter tables and ID
index values . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Fig 48. ID Look-up table configuration example (noFullCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Fig 49. ID Look-up table configuration example (FullCAN
activated and enabled) . . . . . . . . . . . . . . . . . . . 265
Fig 50. USB device controller block diagram . . . . . . . . 269
Fig 51. USB MaxPacketSize register array indexing . . 287
Fig 52. Interrupt event handling . . . . . . . . . . . . . . . . . . 299
Fig 53. UDCA Head register and DMA Descriptors . . . 312
Fig 54. Isochronous OUT endpoint operation example. 320
Fig 55. Data transfer in ATLE mode . . . . . . . . . . . . . . . 321
Fig 56. Autobaud a) mode 0 and b) mode 1 waveform 339
Fig 57. LPC2300 UART0, 2 and 3 block diagram . . . . . 344
Fig 58. Auto-RTS Functional Timing . . . . . . . . . . . . . . . 356
Fig 59. Auto-CTS Functional Timing . . . . . . . . . . . . . . . 357
Fig 60. Auto-baud a) mode 0 and b) mode 1 waveform 363
Fig 61. LPC2300 UART1 block diagram . . . . . . . . . . . . 368
Fig 62. SPI data transfer format (CPHA = 0 and CPHA = 1)
370
Fig 63. SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . 379
Fig 64. Texas Instruments Synchronous Serial Frame
Format: a) Single and b) Continuous/back-to-back
Two Frames Transfer . . . . . . . . . . . . . . . . . . . . 382
Fig 65. SPI Frame Format with CPOL=0 and CPHA=0 (a)Single and b) Continuous Transfer) . . . . . . . . . 383
Fig 66. SPI Frame Format with CPOL=0 and CPHA=1 384
Fig 67. SPI Frame Format with CPOL = 1 and CPHA = 0 (a)Single and b) Continuous Transfer) . . . . . . . . . 385
Fig 68. SPI Frame Format with CPOL = 1 and CPHA = 1 .
386
Fig 69. Microwire Frame Format (Single Transfer) . . . . 387
Fig 70. Microwire Frame Format (Continuos Transfers) 388
Fig 71. Microwire frame format setup and hold details . 388
Fig 72. Multimedia card system . . . . . . . . . . . . . . . . . . 396
Fig 73. Secure digital memory card connection . . . . . . 396
Fig 74. MCI adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Fig 75. Command path state machine . . . . . . . . . . . . . 398

continued >>UM10211_1

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Fig 76.
Fig 77.
Fig 78.
Fig 79.
Fig 80.
Fig 81.
Fig 82.

MCI command transfer . . . . . . . . . . . . . . . . . . .399
Data path state machine . . . . . . . . . . . . . . . . . .401
Pending command start . . . . . . . . . . . . . . . . . . .403
I2C bus configuration . . . . . . . . . . . . . . . . . . . . .417
Format in the Master Transmitter mode. . . . . . .418
Format of Master Receive mode . . . . . . . . . . . .419
A master receiver switch to master Transmitter after
sending repeated START. . . . . . . . . . . . . . . . . .419
Fig 83. Format of Slave Receiver mode . . . . . . . . . . . .420
Fig 84. Format of Slave Transmitter mode . . . . . . . . . .420
Fig 85. I2C Bus serial interface block diagram. . . . . . . .422
Fig 86. Arbitration procedure . . . . . . . . . . . . . . . . . . . . .423
Fig 87. Serial clock synchronization. . . . . . . . . . . . . . . .424
Fig 88. Format and States in the Master Transmitter mode.
434
Fig 89. Format and States in the Master Receiver mode. . .
435
Fig 90. Format and States in the Slave Receiver mode.436
Fig 91. Format and States in the Slave Transmitter mode. .
437
Fig 92. Simultaneous repeated START conditions from 2
masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .445
Fig 93. Forced access to a busy I2C bus . . . . . . . . . . . .446
Fig 94. Recovering from a bus obstruction caused by a low
level on SDA . . . . . . . . . . . . . . . . . . . . . . . . . . .446
Fig 95. Simple I2S configurations and bus timing . . . . .457
Fig 96. FIFO contents for various I2S modes. . . . . . . . .464
Fig 97. A timer cycle in which PR=2, MRx=6, and bothinterrupt and reset on match are enabled. . . . . .474
Fig 98. A Timer Cycle in Which PR=2, MRx=6, and BothInterrupt and Stop on Match are Enabled . . . . .474
Fig 99. Timer block diagram . . . . . . . . . . . . . . . . . . . . .475
Fig 100. Watchdog block diagram . . . . . . . . . . . . . . . . . .480
Fig 101. PWM block diagram. . . . . . . . . . . . . . . . . . . . . .483
Fig 102. Sample PWM waveforms. . . . . . . . . . . . . . . . . .484
Fig 103. RTC block diagram . . . . . . . . . . . . . . . . . . . . . .504
Fig 104. RTC prescaler block diagram . . . . . . . . . . . . . .514
Fig 105. RTC 32 kHz crystal oscillator circuit . . . . . . . . .516
Fig 106. Map of lower memory after reset . . . . . . . . . . . .518
Fig 107. Boot process flowchart . . . . . . . . . . . . . . . . . . .521
Fig 108. IAP parameter passing . . . . . . . . . . . . . . . . . . .533
Fig 109. GPDMA Block Diagram . . . . . . . . . . . . . . . . . . .539
Fig 110. Example of GPDMA in a System . . . . . . . . . . . .540
Fig 111. LLI example . . . . . . . . . . . . . . . . . . . . . . . . . . . .562
Fig 112. EmbeddedICE debug environment block diagram .
569
Fig 113. ETM debug environment block diagram . . . . . .573
Fig 114. RealMonitor Components . . . . . . . . . . . . . . . . .575
Fig 115. RealMonitor as a State Machine . . . . . . . . . . . .576
Fig 116. Exception Handlers. . . . . . . . . . . . . . . . . . . . . .579

continued >>UM10211_1

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Rev. 01 — 6 July 2007

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5. Contents
Chapter 1: Introductory information
1
2
3
4
5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5
Architectural overview . . . . . . . . . . . . . . . . . . . 5

6
7
8
9

ARM7TDMI-S processor . . . . . . . . . . . . . . . . . .
On-Chip flash memory system . . . . . . . . . . . .
On-Chip Static RAM . . . . . . . . . . . . . . . . . . . . .
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .

6
6
7
8

5
5.1

Memory mapping control . . . . . . . . . . . . . . . . 17
Memory Mapping Control Register (MEMMAP 0xE01F C040) . . . . . . . . . . . . . . . . . . . . . . . . 17
Memory mapping control usage notes. . . . . . 18
Prefetch abort and data abort exceptions . . 20

Chapter 2: LPC2300 memory addressing
1
2
3
4
4.1
4.2

Memory map and peripheral addressing. . . . 10
Memory maps. . . . . . . . . . . . . . . . . . . . . . . . . . 10
APB peripheral addresses . . . . . . . . . . . . . . . 15
LPC2300 memory re-mapping and boot ROM 16
Memory map concepts and operating modes. 16
Memory re-mapping . . . . . . . . . . . . . . . . . . . . 17

5.2
6

Chapter 3: System control block
1
2
3
4
4.1
5
6
6.1
6.2
6.3

Summary of system control block functions 21
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 21
Register description . . . . . . . . . . . . . . . . . . . . 21
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset Source Identification Register (RSIR 0xE01F C180) . . . . . . . . . . . . . . . . . . . . . . . . 23
Brown-out detection . . . . . . . . . . . . . . . . . . . . 24
External interrupt inputs . . . . . . . . . . . . . . . . . 25
Register description . . . . . . . . . . . . . . . . . . . . 25
External Interrupt flag register (EXTINT 0xE01F C140) . . . . . . . . . . . . . . . . . . . . . . . . 25
External Interrupt Mode register (EXTMODE 0xE01F C148) . . . . . . . . . . . . . . . . . . . . . . . . 26

6.4
7
7.1
8
8.1
9
9.1
9.2

External Interrupt Polarity register (EXTPOLAR 0xE01F C14C) . . . . . . . . . . . . . . . . . . . . . . . . 27
Other system controls and status flags . . . . 28
System Controls and Status register (SCS 0xE01F C1A0) . . . . . . . . . . . . . . . . . . . . . . . . 28
Code security vs. debugging . . . . . . . . . . . . . 29
Code Security Protection Register (CSPR 0xE01F C184) . . . . . . . . . . . . . . . . . . . . . . . . 29
AHB configuration . . . . . . . . . . . . . . . . . . . . . 29
AHB Arbiter Configuration register 1 (AHBCFG1 0xE01F C188) . . . . . . . . . . . . . . . . . . . . . . . . 30
AHB Arbiter Configuration register 2 (AHBCFG2 0xE01F C18C) . . . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 4: Clocking and power control
1
2
3
3.1
3.2
3.3
4
4.1
5

Summary of clocking and power control
functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Register description . . . . . . . . . . . . . . . . . . . . 35
Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Internal RC oscillator . . . . . . . . . . . . . . . . . . . 35
Main oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 36
RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 36
Clock source selection multiplexer . . . . . . . . 36
Clock Source Select register (CLKSRCSEL 0xE01F C10C) . . . . . . . . . . . . . . . . . . . . . . . . 36
PLL (Phase Locked Loop). . . . . . . . . . . . . . . . 37

5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9

PLL operation. . . . . . . . . . . . . . . . . . . . . . . . . 37
PLL and startup/boot code interaction . . . . . . 38
Register description . . . . . . . . . . . . . . . . . . . . 38
PLL Control register (PLLCON - 0xE01F C080) .
39
PLL Configuration register (PLLCFG 0xE01F C084) . . . . . . . . . . . . . . . . . . . . . . . . 40
PLL Status register (PLLSTAT - 0xE01F C088) . .
42
PLL Interrupt: PLOCK . . . . . . . . . . . . . . . . . . 42
PLL Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 43
PLL Feed register (PLLFEED - 0xE01F C08C) 43

continued >>UM10211_1

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Rev. 01 — 6 July 2007

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5.10
5.11
5.12
5.13
5.14
6
6.1
6.2
6.3
6.4

PLL and Power down mode . . . . . . . . . . . . . . 43
PLL frequency calculation . . . . . . . . . . . . . . . 44
Procedure for determining PLL settings . . . . . 45
Examples of PLL settings . . . . . . . . . . . . . . . . 45
PLL setup sequence . . . . . . . . . . . . . . . . . . . . 47
Clock dividers . . . . . . . . . . . . . . . . . . . . . . . . . 47
CPU Clock Configuration register (CCLKCFG 0xE01F C104) . . . . . . . . . . . . . . . . . . . . . . . . 48
USB Clock Configuration register (USBCLKCFG 0xE01F C108) . . . . . . . . . . . . . . . . . . . . . . . . 48
IRC Trim Register (IRCTRIM - 0xE01F C1A4) 49
Peripheral Clock Selection registers 0 and 1(PCLKSEL0 - 0xE01F C1A8 and PCLKSEL1 0xE01F C1AC) . . . . . . . . . . . . . . . . . . . . . . . . 49

7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8

Power control . . . . . . . . . . . . . . . . . . . . . . . . . 51
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Power Down mode. . . . . . . . . . . . . . . . . . . . . 52
Peripheral power control . . . . . . . . . . . . . . . . 52
Register description . . . . . . . . . . . . . . . . . . . . 52
Power Mode Control register (PCON 0xE01F C0C0) . . . . . . . . . . . . . . . . . . . . . . . . 52
Interrupt Wakeup Register (INTWAKE 0xE01F C144) . . . . . . . . . . . . . . . . . . . . . . . . 54
Power Control for Peripherals register (PCONP 0xE01F COC4) . . . . . . . . . . . . . . . . . . . . . . . 55
Power control usage notes . . . . . . . . . . . . . . 56
Power domains . . . . . . . . . . . . . . . . . . . . . . . 57
Wakeup timer. . . . . . . . . . . . . . . . . . . . . . . . . . 57

Chapter 5: External Memory Controller (EMC)
1
2
3
4
5
5.1
5.1.1
5.1.2
5.1.3
5.2
5.2.1
5.2.2
5.3
5.4
6
7
8
9
9.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Functional overview . . . . . . . . . . . . . . . . . . . . 58
EMC functional description . . . . . . . . . . . . . . 58
AHB Slave register interface. . . . . . . . . . . . . . 59
AHB Slave memory interface . . . . . . . . . . . . . 59
Memory transaction endianness. . . . . . . . . . . 60
Memory transaction size. . . . . . . . . . . . . . . . . 60
Write protected memory areas . . . . . . . . . . . . 60
Data buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Write buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Read buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Memory controller state machine . . . . . . . . . . 61
Pad interface . . . . . . . . . . . . . . . . . . . . . . . . . 61
Memory bank select . . . . . . . . . . . . . . . . . . . . 61
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 62
Register description . . . . . . . . . . . . . . . . . . . . 62
EMC Control Register (EMCControl 0xFFE0 8000) . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11

10

EMC Status Register (EMCStatus - 0xFFE0 8004)
64
EMC Configuration Register (EMCConfig 0xFFE0 8008) . . . . . . . . . . . . . . . . . . . . . . . . 64
Static Memory Configuration Registers(EMCStaticConfig0-1 - 0xFFE0 8200, 220) . . 65
Static Memory Write Enable Delay Registers(EMCStaticWaitWen0-1 - 0xFFE0 8204, 224) 66
Static Memory Output Enable Delay Registers(EMCStaticWaitOen0-1 - 0xFFE0 8208, 228) 67
Static Memory Read Delay Registers(EMCStaticWaitRd0-1 - 0xFFE0 820C, 22C) . 67
Static Memory Page Mode Read Delay Registers(EMCStaticwaitPage0-1 - 0xFFE0 8210, 230) 68
Static Memory Write Delay Registers(EMCStaticWaitwr0-1 - 0xFFE0 8214, 234) . . 68
Static Memory Extended Wait Register(EMCStaticExtendedWait - 0xFFE0 8880). . . 69
Static Memory Turn Round Delay Registers(EMCStaticWaitTurn0-1 - 0xFFE0 8218, 238, 258,278) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
External memory interface . . . . . . . . . . . . . . . 70

Chapter 6: Vectored Interrupt Controller (VIC)
1
2
3
4
4.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Register description . . . . . . . . . . . . . . . . . . . . 72
VIC registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Software Interrupt Register (VICSoftInt 0xFFFF F018). . . . . . . . . . . . . . . . . . . . . . . . . 75

4.2
4.3
4.4
4.5

Software Interrupt Clear Register(VICSoftIntClear - 0xFFFF F01C) . . . . . . . . . 75
Raw Interrupt Status Register (VICRawIntr 0xFFFF F008) . . . . . . . . . . . . . . . . . . . . . . . . 76
Interrupt Enable Register (VICIntEnable 0xFFFF F010) . . . . . . . . . . . . . . . . . . . . . . . . 76
Interrupt Enable Clear Register (VICIntEnClear 0xFFFF F014) . . . . . . . . . . . . . . . . . . . . . . . . 76

continued >>UM10211_1

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Rev. 01 — 6 July 2007

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Chapter 32: Supplementary information

4.6
4.7
4.8
4.9

Interrupt Select Register (VICIntSelect 0xFFFF F00C) . . . . . . . . . . . . . . . . . . . . . . . . 76
IRQ Status Register (VICIRQStatus 0xFFFF F000). . . . . . . . . . . . . . . . . . . . . . . . . 77
FIQ Status Register (VICFIQStatus 0xFFFF F004). . . . . . . . . . . . . . . . . . . . . . . . . 77
Vector Address Registers 0-31 (VICVectAddr0-31- 0xFFFF F100 to 17C) . . . . . . . . . . . . . . . . . . 77

4.10
4.11
4.12
4.13
5

Vector Priority Registers 0-31
(VICVectPriority0-31 - 0xFFFF F200 to 27C).
Vector Address Register (VICAddress 0xFFFF FF00) . . . . . . . . . . . . . . . . . . . . . . . .
Software Priority Mask Register(VICSWPriorityMask - 0xFFFF F024) . . . . . .
Protection Enable Register (VICProtection 0xFFFF F020) . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . .

78
78
78
79
79

Chapter 7: Memory Acceleration Module (MAM)
1
2
3
3.1
3.2
3.3
4

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Memory Acceleration Module blocks. . . . . . . 84
Flash memory bank . . . . . . . . . . . . . . . . . . . . 84
Instruction latches and data latches . . . . . . . . 85
Flash programming Issues . . . . . . . . . . . . . . . 85
Memory Accelerator Module Operating modes .
85

5
6
7

9

MAM configuration . . . . . . . . . . . . . . . . . . . . . 86
Register description . . . . . . . . . . . . . . . . . . . . 86
MAM Control Register (MAMCR - 0xE01F C000)
87
MAM Timing Register (MAMTIM - 0xE01F C004)
87
MAM usage notes . . . . . . . . . . . . . . . . . . . . . . 89

34

LPC2378 144-pin package . . . . . . . . . . . . . . . 98
Pin description for LPC2378 . . . . . . . . . . . . . 98

6.8

Pin Function Select Register 7 (PINSEL7 0xE002 C01C) . . . . . . . . . . . . . . . . . . . . . . . . 115
Pin Function Select Register 8 (PINSEL8 0xE002 C020) . . . . . . . . . . . . . . . . . . . . . . . . 116
Pin Function Select Register 9 (PINSEL9 0xE002 C024) . . . . . . . . . . . . . . . . . . . . . . . . 116
Pin Function Select Register 10 (PINSEL10 0xE002 C028) . . . . . . . . . . . . . . . . . . . . . . . . 117
Pin Mode select register 0 (PINMODE0 0xE002 C040) . . . . . . . . . . . . . . . . . . . . . . . . 117
Pin Mode select register 1 (PINMODE1 0xE002 C044) . . . . . . . . . . . . . . . . . . . . . . . . 118
Pin Mode select register 2 (PINMODE2 0xE002 C048) . . . . . . . . . . . . . . . . . . . . . . . . 118
Pin Mode select register 3 (PINMODE3 0xE002 C04C) . . . . . . . . . . . . . . . . . . . . . . . . 118
Pin Mode select register 4 (PINMODE4 0xE002 C050) . . . . . . . . . . . . . . . . . . . . . . . . 119
Pin Mode select register 5 (PINMODE5 0xE002 C054) . . . . . . . . . . . . . . . . . . . . . . . . 119
Pin Mode select register 6 (PINMODE6 0xE002 C058) . . . . . . . . . . . . . . . . . . . . . . . . 119

8

Chapter 8: Pin configuration
1
2

LPC2364/6/8 100-pin package. . . . . . . . . . . . . 90
Pin description for LPC2364/6/8 . . . . . . . . . . . 90

Chapter 9: Pin connect block
1
2
3
4
5
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Pin function select register values. . . . . . . . 109
Pin mode select register values . . . . . . . . . . 109
Register description . . . . . . . . . . . . . . . . . . . 110
Pin control module register reset values. . . . .110
Pin Function Select register 0 (PINSEL0 0xE002 C000). . . . . . . . . . . . . . . . . . . . . . . . 111
Pin Function Select Register 1 (PINSEL1 0xE002 C004). . . . . . . . . . . . . . . . . . . . . . . . 111
Pin Function Select register 2 (PINSEL2 0xE002 C008). . . . . . . . . . . . . . . . . . . . . . . . 112
Pin Function Select Register 3 (PINSEL3 0xE002 C00C) . . . . . . . . . . . . . . . . . . . . . . . 113
Pin Function Select Register 4 (PINSEL4 0xE002 C010). . . . . . . . . . . . . . . . . . . . . . . . 113
Pin Function Select Register 5 (PINSEL5 0xE002 C014). . . . . . . . . . . . . . . . . . . . . . . . 114
Pin Function Select Register 6 (PINSEL6 0xE002 C018). . . . . . . . . . . . . . . . . . . . . . . . 114

6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

603 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

6.19
6.20

Pin Mode select register 7 (PINMODE7 0xE002 C05C) . . . . . . . . . . . . . . . . . . . . . . . 119
Pin Mode select register 8 (PINMODE8 0xE002 C060). . . . . . . . . . . . . . . . . . . . . . . . 120

6.21

Pin Mode select register 9 (PINMODE9 0xE002 C064) . . . . . . . . . . . . . . . . . . . . . . . 120

Chapter 10: General Purpose Input/Output ports (GPIO)
1
1.1
1.2
2
3
4
4.1

4.2

4.3

4.4

4.5

4.6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Digital I/O ports . . . . . . . . . . . . . . . . . . . . . . . 121
Interrupt generating digital ports . . . . . . . . . . 121
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 122
Register description . . . . . . . . . . . . . . . . . . . 122
GPIO port Direction register IODIR and
FIODIR(IO[0/1]DIR - 0xE002 80[0/1]8 andFIO[0/1/2/3/4]DIR - 0x3FFF C0[0/2/4/6/8]0) . 125
GPIO port output Set register IOSET and
FIOSET(IO[0/1]SET - 0xE002 80[0/1]4 andFIO[0/1/2/3/4]SET - 0x3FFF C0[1/3/5/7/9]8) 126
GPIO port output Clear register IOCLR andFIOCLR (IO[0/1]CLR - 0xE002 80[0/1]C andFIO[0/1/2/3/4]CLR - 0x3FFF C0[1/3/5/7/9]C) 128
GPIO port Pin value register IOPIN and FIOPIN(IO[0/1]PIN - 0xE002 80[0/1]0 andFIO[0/1/2/3/4]PIN - 0x3FFF C0[1/3/5/7/9]4) . 129
Fast GPIO port Mask register
FIOMASK(FIO[0/1/2/3/4]MASK 0x3FFF C0[1/3/5/7/9]0) . . . . . . . . . . . . . . . . 131
GPIO overall Interrupt Status register (IOIntStatus- 0xE002 8080) . . . . . . . . . . . . . . . . . . . . . . . 133

4.7

4.8

4.9

4.10

4.11
5
5.1
5.2
5.3
5.4

GPIO Interrupt Enable for Rising edge register(IO0IntEnR - 0xE002 8090 and IO2IntEnR 0xE002 80B0) . . . . . . . . . . . . . . . . . . . . . . . 133
GPIO Interrupt Enable for Falling edge register(IO0IntEnF - 0xE002 8094 and IO2IntEnF 0xE002 80B4) . . . . . . . . . . . . . . . . . . . . . . . 133
GPIO Interrupt Status for Rising edge register(IO0IntStatR - 0xE002 8084 and IO2IntStatR 0xE002 80A4) . . . . . . . . . . . . . . . . . . . . . . . 134
GPIO Interrupt Status for Falling edge register(IO0IntStatF - 0xE002 8088 and IO2IntStatF 0xE002 80A8) . . . . . . . . . . . . . . . . . . . . . . . 134
GPIO Interrupt Clear register (IO0IntClr 0xE002 808C and IO2IntClr - 0xE002 80AC) 134
GPIO usage notes . . . . . . . . . . . . . . . . . . . . . 135
Example 1: sequential accesses to IOSET and
IOCLR affecting the same GPIO pin/bit . . . . 135
Example 2: an instantaneous output of 0s and 1s
on a GPIO port. . . . . . . . . . . . . . . . . . . . . . . 135
Writing to IOSET/IOCLR vs. IOPIN . . . . . . . 136
Output signal frequency considerations whenusing the legacy and enhanced GPIO registers .
136

Chapter 11: Ethernet controller
1
2
3
4
5
6
7
7.1
7.2
8
9
9.1
10
10.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Architecture and operation . . . . . . . . . . . . . . 139
DMA engine functions . . . . . . . . . . . . . . . . . . 140
Overview of DMA operation . . . . . . . . . . . . . 140
Ethernet Packet . . . . . . . . . . . . . . . . . . . . . . . 141
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Example PHY Devices . . . . . . . . . . . . . . . . . 143
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 143
Registers and software interface . . . . . . . . . 143
Register map . . . . . . . . . . . . . . . . . . . . . . . . 144
Ethernet MAC register definitions . . . . . . . . 146
MAC Configuration Register 1 (MAC1 0xFFE0 0000) . . . . . . . . . . . . . . . . . . . . . . . . 146

10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10

MAC Configuration Register 2 (MAC2 0xFFE0 0004) . . . . . . . . . . . . . . . . . . . . . . . 147
Back-to-Back Inter-Packet-Gap Register (IPGT 0xFFE0 0008) . . . . . . . . . . . . . . . . . . . . . . . 148
Non Back-to-Back Inter-Packet-Gap Register(IPGR - 0xFFE0 000C) . . . . . . . . . . . . . . . . 148
Collision Window / Retry Register (CLRT 0xFFE0 0010) . . . . . . . . . . . . . . . . . . . . . . . 149
Maximum Frame Register (MAXF - 0xFFE0 0014)
149
PHY Support Register (SUPP - 0xFFE0 0018) . .
150
Test Register (TEST - 0xFFE0 001C) . . . . . 150
MII Mgmt Configuration Register (MCFG 0xFFE0 0020) . . . . . . . . . . . . . . . . . . . . . . . 150
MII Mgmt Command Register (MCMD 0xFFE0 0024) . . . . . . . . . . . . . . . . . . . . . . . 151

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

604 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

10.11
10.12
10.13
10.14
10.15
10.16
10.17
11
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
11.14
11.15
11.16
11.17
12

MII Mgmt Address Register (MADR 0xFFE0 0028) . . . . . . . . . . . . . . . . . . . . . . . . 151
MII Mgmt Write Data Register (MWTD 0xFFE0 002C) . . . . . . . . . . . . . . . . . . . . . . . 152
MII Mgmt Read Data Register (MRDD 0xFFE0 0030) . . . . . . . . . . . . . . . . . . . . . . . . 152
MII Mgmt Indicators Register (MIND 0xFFE0 0034) . . . . . . . . . . . . . . . . . . . . . . . . 152
Station Address 0 Register (SA0 - 0xFFE0 0040)
153
Station Address 1 Register (SA1 - 0xFFE0 0044)
153
Station Address 2 Register (SA2 - 0xFFE0 0048)
153
Control register definitions . . . . . . . . . . . . . 154
Command Register (Command - 0xFFE0 0100) .
154
Status Register (Status - 0xFFE0 0104) . . . . 154
Receive Descriptor Base Address Register(RxDescriptor - 0xFFE0 0108) . . . . . . . . . . . 155
Receive Status Base Address Register (RxStatus- 0xFFE0 010C) . . . . . . . . . . . . . . . . . . . . . . 155
Receive Number of Descriptors Register(RxDescriptor - 0xFFE0 0110) . . . . . . . . . . . 156
Receive Produce Index Register(RxProduceIndex - 0xFFE0 0114) . . . . . . . . 156
Receive Consume Index Register(RxConsumeIndex - 0xFFE0 0118) . . . . . . . 156
Transmit Descriptor Base Address Register(TxDescriptor - 0xFFE0 011C) . . . . . . . . . . . 157
Transmit Status Base Address Register (TxStatus- 0xFFE0 0120). . . . . . . . . . . . . . . . . . . . . . . 157
Transmit Number of Descriptors Register(TxDescriptorNumber - 0xFFE0 0124) . . . . . 158
Transmit Produce Index Register(TxProduceIndex - 0xFFE0 0128) . . . . . . . . 158
Transmit Consume Index Register(TxConsumeIndex - 0xFFE0 012C) . . . . . . . 158
Transmit Status Vector 0 Register (TSV0 0xFFE0 0158) . . . . . . . . . . . . . . . . . . . . . . . . 159
Transmit Status Vector 1 Register (TSV1 0xFFE0 015C) . . . . . . . . . . . . . . . . . . . . . . . 160
Receive Status Vector Register (RSV 0xFFE0 0160) . . . . . . . . . . . . . . . . . . . . . . . . 160
Flow Control Counter Register(FlowControlCounter - 0xFFE0 0170). . . . . . 161
Flow Control Status Register (FlowControlStatus 0xFFE0 0174) . . . . . . . . . . . . . . . . . . . . . . . . 162
Receive filter register definitions . . . . . . . . . 162

12.1
12.2
12.3
12.4
12.5
13
13.1
13.2
13.3
13.4
13.5
14
14.1
14.2
15
15.1
15.2
16
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
16.10
16.11
16.12
16.13
16.14
16.15
16.16
16.17
16.18
16.19
17
17.1

Receive Filter Control Register (RxFilterCtrl 0xFFE0 0200) . . . . . . . . . . . . . . . . . . . . . . . 162
Receive Filter WoL Status Register(RxFilterWoLStatus - 0xFFE0 0204) . . . . . . 163
Receive Filter WoL Clear Register(RxFilterWoLClear - 0xFFE0 0208) . . . . . . . 163
Hash Filter Table LSBs Register (HashFilterL 0xFFE0 0210) . . . . . . . . . . . . . . . . . . . . . . . 164
Hash Filter Table MSBs Register (HashFilterH 0xFFE0 0214) . . . . . . . . . . . . . . . . . . . . . . . 164
Module control register definitions . . . . . . . 165
Interrupt Status Register (IntStatus 0xFFE0 0FE0) . . . . . . . . . . . . . . . . . . . . . . . 165
Interrupt Enable Register (IntEnable 0xFFE0 0FE4) . . . . . . . . . . . . . . . . . . . . . . . 165
Interrupt Clear Register (IntClear - 0xFFE0 0FE8)
166
Interrupt Set Register (IntSet - 0xFFE0 0FEC) . .
167
Power Down Register (PowerDown 0xFFE0 0FF4) . . . . . . . . . . . . . . . . . . . . . . . 167
Descriptor and status formats . . . . . . . . . . . 168
Receive descriptors and statuses . . . . . . . . 168
Transmit descriptors and statuses . . . . . . . . 171
Ethernet block functional description. . . . . 173
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
AHB interface. . . . . . . . . . . . . . . . . . . . . . . . 174
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Direct Memory Access (DMA) . . . . . . . . . . . 174
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 177
Transmit process . . . . . . . . . . . . . . . . . . . . . 178
Receive process . . . . . . . . . . . . . . . . . . . . . 184
Transmission retry . . . . . . . . . . . . . . . . . . . . 190
Status hash CRC calculations . . . . . . . . . . . 190
Duplex modes . . . . . . . . . . . . . . . . . . . . . . . 191
IEE 802.3/Clause 31 flow control. . . . . . . . . 191
Half-Duplex mode backpressure . . . . . . . . . 193
Receive filtering . . . . . . . . . . . . . . . . . . . . . . 194
Power management. . . . . . . . . . . . . . . . . . . 196
Wake-up on LAN . . . . . . . . . . . . . . . . . . . . . 197
Enabling and disabling receive and transmit 198
Transmission padding and CRC . . . . . . . . . 200
Huge frames and frame length checking . . . 201
Statistics counters . . . . . . . . . . . . . . . . . . . . 201
MAC status vectors . . . . . . . . . . . . . . . . . . . 201
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Ethernet errors . . . . . . . . . . . . . . . . . . . . . . . 203
AHB bandwidth . . . . . . . . . . . . . . . . . . . . . . . 203
DMA access. . . . . . . . . . . . . . . . . . . . . . . . . 203

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

605 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

17.2
17.3

Types of CPU access . . . . . . . . . . . . . . . . . . 205
Overall bandwidth . . . . . . . . . . . . . . . . . . . . . 205

18

CRC calculation. . . . . . . . . . . . . . . . . . . . . . . 205

6.11

Receive Data Register A (CAN1RDA 0xE004 4028, CAN2RDA - 0xE004 8028) . . 231
Receive Data Register B (CAN1RDB 0xE004 402C, CAN2RDB - 0xE004 802C) . 232
Transmit Frame Information Register(CAN1TFI[1/2/3] - 0xE004 40[30/ 40/50],
CAN2TFI[1/2/3] - 0xE004 80[30/40/50]) . . . 232
Automatic transmit priority detection . . . . . . . 233
Tx DLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Transmit Identifier Register (CAN1TID[1/2/3] 0xE004 40[34/44/54], CAN2TID[1/2/3] 0xE004 80[34/44/54]). . . . . . . . . . . . . . . . . . 234
Transmit Data Register A (CAN1TDA[1/2/3] 0xE004 40[38/48/58], CAN2TDA[1/2/3] 0xE004 80[38/48/58]). . . . . . . . . . . . . . . . . . 234
Transmit Data Register B (CAN1TDB[1/2/3] 0xE004 40[3C/4C/5C], CAN2TDB[1/2/3] 0xE004 80[3C/4C/5C]). . . . . . . . . . . . . . . . . 235
CAN controller operation . . . . . . . . . . . . . . . 235
Error handling . . . . . . . . . . . . . . . . . . . . . . . 235
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . 235
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Transmit priority . . . . . . . . . . . . . . . . . . . . . . 236
Centralized CAN registers . . . . . . . . . . . . . . 236
Central Transmit Status Register (CANTxSR 0xE004 0000). . . . . . . . . . . . . . . . . . . . . . . . 236
Central Receive Status Register (CANRxSR 0xE004 0004). . . . . . . . . . . . . . . . . . . . . . . . 237
Central Miscellaneous Status Register (CANMSR- 0xE004 0008) . . . . . . . . . . . . . . . . . . . . . . 237
Global acceptance filter . . . . . . . . . . . . . . . . 238
Acceptance filter modes. . . . . . . . . . . . . . . . 238
Acceptance filter Off mode. . . . . . . . . . . . . . 238
Acceptance filter Bypass mode . . . . . . . . . . 239
Acceptance filter Operating mode . . . . . . . . 239
FullCAN mode . . . . . . . . . . . . . . . . . . . . . . . 239
Sections of the ID look-up table RAM . . . . . 239
ID look-up table RAM . . . . . . . . . . . . . . . . . . 239
Acceptance filter registers . . . . . . . . . . . . . . 241
Acceptance Filter Mode Register (AFMR 0xE003 C000) . . . . . . . . . . . . . . . . . . . . . . . 241
Section configuration registers. . . . . . . . . . . 242
Standard Frame Individual Start Address Register(SFF_sa - 0xE003 C004) . . . . . . . . . . . . . . . 243

Chapter 12: CAN controllers CAN1/2
1
2
2.1
2.2
2.3
3
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8

5
6
6.1
6.2
6.3

6.4
6.5
6.6

6.7
6.8
6.9
6.9.1
6.10

CAN controllers . . . . . . . . . . . . . . . . . . . . . . . 208
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
General CAN features . . . . . . . . . . . . . . . . . 208
CAN controller features . . . . . . . . . . . . . . . . 208
Acceptance filter features . . . . . . . . . . . . . . . 209
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 209
CAN controller architecture . . . . . . . . . . . . . 209
APB interface block (AIB) . . . . . . . . . . . . . . . 210
Interface management logic (IML) . . . . . . . . 210
Transmit Buffers (TXB) . . . . . . . . . . . . . . . . . 210
Receive Buffer (RXB) . . . . . . . . . . . . . . . . . 211
Error Management Logic (EML) . . . . . . . . . 212
Bit Timing Logic (BTL) . . . . . . . . . . . . . . . . . 212
Bit Stream Processor (BSP) . . . . . . . . . . . . . 212
CAN controller self-tests . . . . . . . . . . . . . . . . 212
Global self test . . . . . . . . . . . . . . . . . . . . . . . .213
Local self test . . . . . . . . . . . . . . . . . . . . . . . . .213
Memory map of the CAN block. . . . . . . . . . . 214
CAN controller registers . . . . . . . . . . . . . . . . 214
Mode Register (CAN1MOD - 0xE004 4000,
CAN2MOD - 0xE004 8000) . . . . . . . . . . . . . 216
Command Register (CAN1CMR - 0xE004 x004,
CAN2CMR - 0xE004 8004) . . . . . . . . . . . . . 217
Global Status Register (CAN1GSR 0xE004 x008, CAN2GSR - 0xE004 8008) . . 219
RX error counter . . . . . . . . . . . . . . . . . . . . . . .220
TX error counter . . . . . . . . . . . . . . . . . . . . . . .221
Interrupt and Capture Register (CAN1ICR 0xE004 400C, CAN2ICR - 0xE004 800C) . . 221
Interrupt Enable Register (CAN1IER 0xE004 4010, CAN2IER - 0xE004 8010) . . . 225
Bus Timing Register (CAN1BTR - 0xE004 4014,
CAN2BTR - 0xE004 8014) . . . . . . . . . . . . . . 226
Baud rate prescaler . . . . . . . . . . . . . . . . . . . .227
Synchronization jump width . . . . . . . . . . . . . .227
Time segment 1 and time segment 2 . . . . . . .227
Error Warning Limit Register (CAN1EWL 0xE004 4018, CAN2EWL - 0xE004 8018) . . 228
Status Register (CAN1SR - 0xE004 401C,
CAN2SR - 0xE004 801C) . . . . . . . . . . . . . . . 228
Receive Frame Status Register (CAN1RFS 0xE004 4020, CAN2RFS - 0xE004 8020) . . 230
ID index field . . . . . . . . . . . . . . . . . . . . . . . . . 231
Receive Identifier Register (CAN1RID 0xE004 4024, CAN2RID - 0xE004 8024) . . . 231

6.12
6.13

6.14

6.15

6.16

7
7.1
7.2
7.3
7.4
8
8.1
8.2
8.3
9
10
10.1
10.2
10.3
10.4
11
12
13
13.1
13.2
13.3

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

606 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

13.4
13.5
13.6
13.7
13.8
13.9
13.10
13.11
13.12

14
14.1
15
15.1
15.2
15.2.115.2.215.2.315.2.415.2.515.2.6
15.3

Standard Frame Group Start Address Register(SFF_GRP_sa - 0xE003 C008) . . . . . . . . . . 243
Extended Frame Start Address Register (EFF_sa- 0xE003 C00C) . . . . . . . . . . . . . . . . . . . . . . 244
Extended Frame Group Start Address Register(EFF_GRP_sa - 0xE003 C010) . . . . . . . . . . 244
End of AF Tables Register (ENDofTable 0xE003 C014). . . . . . . . . . . . . . . . . . . . . . . . 245
Status registers . . . . . . . . . . . . . . . . . . . . . . . 245
LUT Error Address Register (LUTerrAd 0xE003 C018). . . . . . . . . . . . . . . . . . . . . . . . 245
LUT Error Register (LUTerr - 0xE003 C01C) 246
Global FullCANInterrupt Enable register (FCANIE- 0xE003 C020) . . . . . . . . . . . . . . . . . . . . . . 246
FullCAN Interrupt and Capture registers(FCANIC0 - 0xE003 C024 and FCANIC1 0xE003 C028). . . . . . . . . . . . . . . . . . . . . . . . 246
Configuration and search algorithm . . . . . . 247
Acceptance filter search algorithm . . . . . . . . 247
FullCAN mode . . . . . . . . . . . . . . . . . . . . . . . . 248
FullCAN message layout . . . . . . . . . . . . . . . 250
FullCAN interrupts . . . . . . . . . . . . . . . . . . . . 252
FullCAN message interrupt enable bit . . . . . 252
Message lost bit and CAN channel number . 253
Setting the interrupt pending bits (IntPnd 63 to 0)
254
Clearing the interrupt pending bits (IntPnd 63 to 0)
254
Setting the message lost bit of a FullCAN
message object (MsgLost 63 to 0) . . . . . . . . 254
Clearing the message lost bit of a FullCAN
message object (MsgLost 63 to 0) . . . . . . . . 254
Set and clear mechanism of the FullCAN interrupt
254

15.3.1
15.3.215.3.315.3.415.3.515.3.6
16
16.1
16.2
16.3
16.4
16.5
16.6

16.7

16.8

Scenario 1: Normal case, no message lost . 254
Scenario 2: Message lost. . . . . . . . . . . . . . . 255
Scenario 3: Message gets overwritten indicatedby Semaphore bits . . . . . . . . . . . . . . . . . . . . 256
Scenario 3.1: Message gets overwritten indicatedby Semaphore bits and Message Lost. . . . . 256
Scenario 3.2: Message gets overwritten indicatedby Message Lost . . . . . . . . . . . . . . . . . . . . . 257
Scenario 4: Clearing Message Lost bit . . . . 258
Examples of acceptance filter tables and ID
index values. . . . . . . . . . . . . . . . . . . . . . . . . . 259
Example 1: only one section is used . . . . . . 259
Example 2: all sections are used . . . . . . . . . 259
Example 3: more than one but not all sections areused . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Configuration example 4 . . . . . . . . . . . . . . . 260
Configuration example 5 . . . . . . . . . . . . . . . 260
Configuration example 6 . . . . . . . . . . . . . . . 261
Explicit standard frame format identifier section(11-bit CAN ID): . . . . . . . . . . . . . . . . . . . . . . . 262
Group of standard frame format identifier section(11-bit CAN ID): . . . . . . . . . . . . . . . . . . . . . . . 262
Explicit extended frame format identifier section(29-bit CAN ID, Figure 12–48) . . . . . . . . . . . . 262
Group of extended frame format identifier section(29-bit CAN ID, Figure 12–48) . . . . . . . . . . . . 262
Configuration example 7 . . . . . . . . . . . . . . . 263
FullCAN explicit standard frame format identfiersection (11-bit CAN ID) . . . . . . . . . . . . . . . . . 264
Explicit standard frame format identifier section(11-bit CAN ID) . . . . . . . . . . . . . . . . . . . . . . . 264
FullCAN message object data section . . . . . . 264
Look-up table programming guidelines . . . . 265

Chapter 13: USB device controller
1
2
3
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Fixed endpoint configuration . . . . . . . . . . . . 268
Functional description . . . . . . . . . . . . . . . . . 269
Analog transceiver . . . . . . . . . . . . . . . . . . . . 270
Serial Interface Engine (SIE) . . . . . . . . . . . . 270
Endpoint RAM (EP_RAM) . . . . . . . . . . . . . . 270
EP_RAM access control . . . . . . . . . . . . . . . . 270
DMA engine and bus master interface . . . . . 270
Register interface . . . . . . . . . . . . . . . . . . . . . 270
SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . 270
GoodLink . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Operational overview . . . . . . . . . . . . . . . . . . 271

6
7
7.1
7.2
7.3
7.4
8
8.1
8.1.1
8.2
8.2.1

Pin description . . . . . . . . . . . . . . . . . . . . . . . 271
Clocking and power management. . . . . . . . 272
Power requirements . . . . . . . . . . . . . . . . . . . 272
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Power management support . . . . . . . . . . . . 272
Remote wake-up . . . . . . . . . . . . . . . . . . . . . 273
Register description . . . . . . . . . . . . . . . . . . . 273
Port select register . . . . . . . . . . . . . . . . . . . . 275
USB Port Select register (USBPortSel - 0xFFE0
C110 – LPC2378 only) . . . . . . . . . . . . . . . . . 275
Clock control registers . . . . . . . . . . . . . . . . . 275
USB Clock Control register (USBClkCtrl 0xFFE0 CFF4) . . . . . . . . . . . . . . . . . . . . . . . 275

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

607 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

8.2.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.7
8.7.1
8.7.2
8.8

USB Clock Status register (USBClkSt - 0xFFE0
CFF8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Device interrupt registers . . . . . . . . . . . . . . . 276
USB Interrupt Status register (USBIntSt 0xE01F C1C0) . . . . . . . . . . . . . . . . . . . . . . . 276
USB Device Interrupt Status register(USBDevIntSt - 0xFFE0 C200) . . . . . . . . . . 277
USB Device Interrupt Enable register(USBDevIntEn - 0xFFE0 C204). . . . . . . . . . 278
USB Device Interrupt Clear register(USBDevIntClr - 0xFFE0 C208). . . . . . . . . . 278
USB Device Interrupt Set register (USBDevIntSet- 0xFFE0 C20C) . . . . . . . . . . . . . . . . . . . . . 279
USB Device Interrupt Priority register(USBDevIntPri - 0xFFE0 C22C) . . . . . . . . . 280
Endpoint interrupt registers. . . . . . . . . . . . . . 280
USB Endpoint Interrupt Status register(USBEpIntSt - 0xFFE0 C230) . . . . . . . . . . . 280
USB Endpoint Interrupt Enable register(USBEpIntEn - 0xFFE0 C234). . . . . . . . . . . 281
USB Endpoint Interrupt Clear register(USBEpIntClr - 0xFFE0 C238). . . . . . . . . . . 282
USB Endpoint Interrupt Set register (USBEpIntSet- 0xFFE0 C23C) . . . . . . . . . . . . . . . . . . . . . 283
USB Endpoint Interrupt Priority register(USBEpIntPri - 0xFFE0 C240). . . . . . . . . . . 283
Endpoint realization registers . . . . . . . . . . . . 284
EP RAM requirements . . . . . . . . . . . . . . . . . 284
USB Realize Endpoint register (USBReEp 0xFFE0 C244) . . . . . . . . . . . . . . . . . . . . . . . 285
USB Endpoint Index register (USBEpIn - 0xFFE0
C248) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
USB MaxPacketSize register (USBMaxPSize 0xFFE0 C24C). . . . . . . . . . . . . . . . . . . . . . . 286
USB transfer registers . . . . . . . . . . . . . . . . . 287
USB Receive Data register (USBRxData 0xFFE0 C218) . . . . . . . . . . . . . . . . . . . . . . . 287
USB Receive Packet Length register(USBRxPLen - 0xFFE0 C220). . . . . . . . . . . 287
USB Transmit Data register (USBTxData 0xFFE0 C21C). . . . . . . . . . . . . . . . . . . . . . . 288
USB Transmit Packet Length register(USBTxPLen - 0xFFE0 C224) . . . . . . . . . . . 288
USB Control register (USBCtrl - 0xFFE0 C228) .
289
SIE command code registers . . . . . . . . . . . . 289
USB Command Code register (USBCmdCode 0xFFE0 C210) . . . . . . . . . . . . . . . . . . . . . . . 289
USB Command Data register (USBCmdData 0xFFE0 C214) . . . . . . . . . . . . . . . . . . . . . . . 290
DMA registers . . . . . . . . . . . . . . . . . . . . . . . . 290

8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.8.7
8.8.8
8.8.9
8.8.108.8.11
8.8.128.8.138.8.148.8.158.8.168.8.178.8.18
9

10
10.1
10.2
10.3
10.4

USB DMA Request Status register (USBDMARSt- 0xFFE0 C250) . . . . . . . . . . . . . . . . . . . . . 290
USB DMA Request Clear register (USBDMARClr- 0xFFE0 C254) . . . . . . . . . . . . . . . . . . . . . 291
USB DMA Request Set register (USBDMARSet 0xFFE0 C258). . . . . . . . . . . . . . . . . . . . . . . 291
USB UDCA Head register (USBUDCAH - 0xFFE0
C280) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
USB EP DMA Status register (USBEpDMASt 0xFFE0 C284). . . . . . . . . . . . . . . . . . . . . . . 292
USB EP DMA Enable register (USBEpDMAEn 0xFFE0 C288). . . . . . . . . . . . . . . . . . . . . . . 293
USB EP DMA Disable register (USBEpDMADis 0xFFE0 C28C) . . . . . . . . . . . . . . . . . . . . . . 293
USB DMA Interrupt Status register (USBDMAIntSt- 0xFFE0 C290) . . . . . . . . . . . . . . . . . . . . . 293
USB DMA Interrupt Enable register(USBDMAIntEn - 0xFFE0 C294) . . . . . . . . 294
USB End of Transfer Interrupt Status register(USBEoTIntSt - 0xFFE0 C2A0). . . . . . . . . . 294
USB End of Transfer Interrupt Clear register(USBEoTIntClr - 0xFFE0 C2A4) . . . . . . . . . 295
USB End of Transfer Interrupt Set register(USBEoTIntSet - 0xFFE0 C2A8) . . . . . . . . 295
USB New DD Request Interrupt Status register(USBNDDRIntSt - 0xFFE0 C2AC) . . . . . . . 295
USB New DD Request Interrupt Clear register(USBNDDRIntClr - 0xFFE0 C2B0) . . . . . . . 296
USB New DD Request Interrupt Set register(USBNDDRIntSet - 0xFFE0 C2B4). . . . . . . 296
USB System Error Interrupt Status register(USBSysErrIntSt - 0xFFE0 C2B8) . . . . . . . . 296
USB System Error Interrupt Clear register(USBSysErrIntClr - 0xFFE0 C2BC) . . . . . . . 296
USB System Error Interrupt Set register(USBSysErrIntSet - 0xFFE0 C2C0) . . . . . . 297
Interrupt handling . . . . . . . . . . . . . . . . . . . . 297
Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . 297
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Serial interface engine command description . .
300
Set Address (Command: 0xD0, Data: write 1 byte)
301
Configure Device (Command: 0xD8, Data: write 1byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Set Mode (Command: 0xF3, Data: write 1 byte) .
302
Read Current Frame Number (Command: 0xF5,
Data: read 1 or 2 bytes) . . . . . . . . . . . . . . . . 303

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

608 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
11
12
12.1
12.2
12.3
13
13.1
13.2
13.3
13.4
13.4.113.4.213.4.313.4.413.4.513.4.613.4.713.4.8Read Test Register (Command: 0xFD, Data: read
2 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Set Device Status (Command: 0xFE, Data: write 1byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Get Device Status (Command: 0xFE, Data: read 1byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Get Error Code (Command: 0xFF, Data: read 1byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Read Error Status (Command: 0xFB, Data: read 1byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Select Endpoint (Command: 0x00 - 0x1F, Data:read 1 byte (optional)) . . . . . . . . . . . . . . . . . 306
Select Endpoint/Clear Interrupt (Command:
0x40 - 0x5F, Data: read 1 byte) . . . . . . . . . . 307
Set Endpoint Status (Command: 0x40 - 0x55,
Data: write 1 byte (optional)). . . . . . . . . . . . . 307
Clear Buffer (Command: 0xF2, Data: read 1 byte
(optional)) . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Validate Buffer (Command: 0xFA, Data: none). . .
308
USB device controller initialization . . . . . . . 309
Slave mode operation . . . . . . . . . . . . . . . . . . 310
Interrupt generation . . . . . . . . . . . . . . . . . . . 310
Data transfer for OUT endpoints. . . . . . . . . . 310
Data transfer for IN endpoints. . . . . . . . . . . . 311
DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 311
Transfer terminology. . . . . . . . . . . . . . . . . . . 311
USB device communication area . . . . . . . . . 312
Triggering the DMA engine. . . . . . . . . . . . . . 312
The DMA descriptor . . . . . . . . . . . . . . . . . . . 313
Next_DD_pointer . . . . . . . . . . . . . . . . . . . . . 314
DMA_mode. . . . . . . . . . . . . . . . . . . . . . . . . . 314
Next_DD_valid . . . . . . . . . . . . . . . . . . . . . . . 314
Isochronous_endpoint . . . . . . . . . . . . . . . . . 314
Max_packet_size . . . . . . . . . . . . . . . . . . . . . 314
DMA_buffer_length. . . . . . . . . . . . . . . . . . . . 315
DMA_buffer_start_addr . . . . . . . . . . . . . . . . 315
DD_retired . . . . . . . . . . . . . . . . . . . . . . . . . . 315

13.4.913.4.1013.4.1113.4.1213.4.1313.4.1413.4.15
13.5
13.5.1
13.5.213.5.313.5.413.5.513.5.613.6
13.6.1
13.6.213.6.313.6.413.6.513.7

13.7.1
13.7.213.7.313.7.4

14
14.1
14.2

DD_status . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Packet_valid. . . . . . . . . . . . . . . . . . . . . . . . . 315
LS_byte_extracted . . . . . . . . . . . . . . . . . . . . 316
MS_byte_extracted . . . . . . . . . . . . . . . . . . . 316
Present_DMA_count . . . . . . . . . . . . . . . . . . 316
Message_length_position . . . . . . . . . . . . . . 316
Isochronous_packetsize_memory_address. 316
Non-isochronous endpoint operation . . . . . . 316
Setting up DMA transfers. . . . . . . . . . . . . . . 316
Finding DMA Descriptor. . . . . . . . . . . . . . . . 316
Transferring the data . . . . . . . . . . . . . . . . . . 317
Optimizing descriptor fetch . . . . . . . . . . . . . 317
Ending the packet transfer . . . . . . . . . . . . . . 317
No_Packet DD . . . . . . . . . . . . . . . . . . . . . . . 318
Isochronous endpoint operation. . . . . . . . . . 318
Setting up DMA transfers. . . . . . . . . . . . . . . 318
Finding the DMA Descriptor. . . . . . . . . . . . . 318
Transferring the Data . . . . . . . . . . . . . . . . . . 318
OUT endpoints. . . . . . . . . . . . . . . . . . . . . . . . 319
IN endpoints. . . . . . . . . . . . . . . . . . . . . . . . . . 319
DMA descriptor completion . . . . . . . . . . . . . 319
Isochronous OUT Endpoint Operation Example .
319
Auto Length Transfer Extraction (ATLE) mode
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
OUT transfers in ATLE mode. . . . . . . . . . . . . 320
IN transfers in ATLE mode. . . . . . . . . . . . . . . 322
Setting up the DMA transfer. . . . . . . . . . . . . 322
Finding the DMA Descriptor. . . . . . . . . . . . . 322
Transferring the Data . . . . . . . . . . . . . . . . . . 322
OUT endpoints. . . . . . . . . . . . . . . . . . . . . . . . 322
IN endpoints. . . . . . . . . . . . . . . . . . . . . . . . . . 322
Ending the packet transfer . . . . . . . . . . . . . . 323
OUT endpoints. . . . . . . . . . . . . . . . . . . . . . . . 323
IN endpoints. . . . . . . . . . . . . . . . . . . . . . . . . . 323
Double buffered endpoint operation . . . . . . 323
Bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . 323
Isochronous endpoints . . . . . . . . . . . . . . . . . 325

Chapter 14: Universal Asynchronous Receiver Transmitter (UART) 0, 2, 3
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 326
3
Register description . . . . . . . . . . . . . . . . . . . 326
14.3.1
UARTn Receiver Buffer Register (U0RBR 0xE000 C000, U2RBR - 0xE007 8000, U3RBR 0xE007 C000 when DLAB = 0, Read Only) . 329
3.2
UARTn Transmit Holding Register (U0THR 0xE000 C000, U2THR - 0xE007 8000, U3THR 0xE007 C000 when DLAB = 0, Write Only) . 329

3.3

3.4

UARTn Divisor Latch LSB Register (U0DLL 0xE000 C000, U2DLL - 0xE007 8000, U3DLL 0xE007 C000 when DLAB = 1) and UARTn
Divisor Latch MSB Register (U0DLM 0xE000 C004, U2DLL - 0xE007 8004, U3DLL 0xE007 C004 when DLAB = 1) . . . . . . . . . . 329
UARTn Interrupt Enable Register (U0IER 0xE000 C004, U2IER - 0xE007 8004, U3IER 0xE007 C004 when DLAB = 0) . . . . . . . . . . 330

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

609 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

3.5

3.6

3.7

3.8

3.9

UARTn Interrupt Identification Register (U0IIR 0xE000 C008, U2IIR - 0xE007 8008, U3IIR 0x7008 C008, Read Only) . . . . . . . . . . . . . . 331
UARTn FIFO Control Register (U0FCR 0xE000 C008, U2FCR - 0xE007 8008, U3FCR 0xE007 C008, Write Only) . . . . . . . . . . . . . . 333
UARTn Line Control Register (U0LCR 0xE000 C00C, U2LCR - 0xE007 800C, U3LCR 0xE007 C00C) . . . . . . . . . . . . . . . . . . . . . . . 333
UARTn Line Status Register (U0LSR 0xE000 C014, U2LSR - 0xE007 8014, U3LSR 0xE007 C014, Read Only) . . . . . . . . . . . . . . 334
UARTn Scratch Pad Register (U0SCR 0xE000 C01C, U2SCR - 0xE007 801C U3SCR 0xE007 C01C) . . . . . . . . . . . . . . . . . . . . . . . 336

3.10

UARTn Auto-baud Control Register (U0ACR 0xE000 C020, U2ACR - 0xE007 8020, U3ACR 0xE007 C020) . . . . . . . . . . . . . . . . . . . . . . . 336
14.3.10.1 Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 337
14.3.10.2 Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 337
3.11
IrDA Control Register for UART3 Only (U3ICR 0xE007 C024) . . . . . . . . . . . . . . . . . . . . . . . 339
3.12
UARTn Fractional Divider Register (U0FDR 0xE000 C028, U2FDR - 0xE007 8028, U3FDR 0xE007 C028) . . . . . . . . . . . . . . . . . . . . . . . 340
3.13
UARTn Baudrate Calculation . . . . . . . . . . . . 341
3.14
UARTn Transmit Enable Register (U0TER 0xE000 C030, U2TER - 0xE007 8030, U3TER 0xE007 C030) . . . . . . . . . . . . . . . . . . . . . . . 342
4Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 343

Chapter 15: Universal Asynchronous Receiver Transmitter (UART) 1
1
2
3
3.1
3.2
3.3

3.4
3.5
3.6
3.7
3.8

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 345
Register description . . . . . . . . . . . . . . . . . . . 346
UART1 Receiver Buffer Register (U1RBR 0xE001 0000, when DLAB = 0 Read Only) . 349
UART1 Transmitter Holding Register (U1THR 0xE001 0000 when DLAB = 0, Write Only) . 349
UART1 Divisor Latch LSB and MSB Registers(U1DLL - 0xE001 0000 and U1DLM 0xE001 0004, when DLAB = 1) . . . . . . . . . . 349
UART1 Interrupt Enable Register (U1IER 0xE001 0004, when DLAB = 0) . . . . . . . . . . 350
UART1 Interrupt Identification Register (U1IIR 0xE001 0008, Read Only) . . . . . . . . . . . . . . 351
UART1 FIFO Control Register (U1FCR 0xE001 0008, Write Only). . . . . . . . . . . . . . . 354
UART1 Line Control Register (U1LCR 0xE001 000C). . . . . . . . . . . . . . . . . . . . . . . . 354
UART1 Modem Control Register (U1MCR 0xE001 0010) . . . . . . . . . . . . . . . . . . . . . . . . 355

3.9
15.3.9.1
15.3.9.2
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
4

Auto-Flow control . . . . . . . . . . . . . . . . . . . . . 356
Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
UART1 Line Status Register (U1LSR 0xE001 0014, Read Only) . . . . . . . . . . . . . . 358
UART1 Modem Status Register (U1MSR 0xE001 0018). . . . . . . . . . . . . . . . . . . . . . . . 359
UART1 Scratch Pad Register (U1SCR 0xE001 001C) . . . . . . . . . . . . . . . . . . . . . . . 360
UART1 Auto-baud Control Register (U1ACR 0xE001 0020). . . . . . . . . . . . . . . . . . . . . . . . 360
Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 362
UART1 Fractional Divider Register (U1FDR 0xE001 0028). . . . . . . . . . . . . . . . . . . . . . . . 363
UART1 Baudrate Calculation . . . . . . . . . . . . 365
UART1 Transmit Enable Register (U1TER 0xE001 0030). . . . . . . . . . . . . . . . . . . . . . . . 366
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 366

Chapter 16: SPI interface SPI0
1
2
3
4
4.1
4.2
4.3
4.4
5

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
SPI overview. . . . . . . . . . . . . . . . . . . . . . . . . . 369
SPI data transfers . . . . . . . . . . . . . . . . . . . . . 369
SPI peripheral details . . . . . . . . . . . . . . . . . . 371
General information . . . . . . . . . . . . . . . . . . . 371
Master operation. . . . . . . . . . . . . . . . . . . . . . 372
Slave operation. . . . . . . . . . . . . . . . . . . . . . . 372
Exception conditions. . . . . . . . . . . . . . . . . . . 372
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 374

6
6.1
6.2
6.3
6.4
6.5

Register description . . . . . . . . . . . . . . . . . . . 374
SPI Control Register (S0SPCR - 0xE002 0000) .
375
SPI Status Register (S0SPSR - 0xE002 0004) . .
376
SPI Data Register (S0SPDR - 0xE002 0008) 377
SPI Clock Counter Register (S0SPCCR 0xE002 000C) . . . . . . . . . . . . . . . . . . . . . . . 377
SPI Test Control Register (SPTCR 0xE002 0010). . . . . . . . . . . . . . . . . . . . . . . . 377

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

610 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

6.6

SPI Test Status Register (SPTSR - 0xE002 0014)
377

6.7
7

SPI Interrupt Register (S0SPINT - 0xE002 001C)
378
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 378

Chapter 17: SSP interface
1
2
3
4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.3
4.3.1
5
5.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . 381
Bus description . . . . . . . . . . . . . . . . . . . . . . . 381
Texas Instruments Synchronous Serial Frame
Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
SPI Frame Format . . . . . . . . . . . . . . . . . . . . 382
Clock Polarity (CPOL) and Phase (CPHA) Control
382
SPI Format with CPOL=0,CPHA=0 . . . . . . . 383
SPI Format with CPOL=0,CPHA=1 . . . . . . . 384
SPI Format with CPOL = 1,CPHA = 0 . . . . . 384
SPI Format with CPOL = 1,CPHA = 1 . . . . . 386
Semiconductor Microwire Frame Format . . . 386
Setup and Hold Time Requirements on CS With
Respect to SK in Microwire Mode. . . . . . . . . 388
Register Description . . . . . . . . . . . . . . . . . . . 388
SSPn Control Register 0 (SSP0CR0 0xE006 8000, SSP1CR0 - 0xE003 0000) . . 389

5.2
5.3
5.4
5.5
5.6

5.7
5.8

5.9
5.10

SSPn Control Register 1 (SSP0CR1 0xE006 8004, SSP1CR1 - 0xE003 0004) . . 390
SSPn Data Register (SSP0DR - 0xE006 8008,
SSP1DR - 0xE003 0008) . . . . . . . . . . . . . . . 391
SSPn Status Register (SSP0SR - 0xE006 800C,
SSP1SR - 0xE003 000C). . . . . . . . . . . . . . . 392
SSPn Clock Prescale Register (SSP0CPSR 0xE006 8010, SSP1CPSR - 0xE003 0010) . 392
SSPn Interrupt Mask Set/Clear Register(SSP0IMSC - 0xE006 8014, SSP1IMSC 0xE003 0014). . . . . . . . . . . . . . . . . . . . . . . . 392
SSPn Raw Interrupt Status Register (SSP0RIS 0xE006 8018, SSP1RIS - 0xE003 0018) . . . 393
SSPn Masked Interrupt Status Register(SSP0MIS - 0xE006 801C, SSP1MIS 0xE003 001C) . . . . . . . . . . . . . . . . . . . . . . . 393
SSPn Interrupt Clear Register (SSP0ICR 0xE006 8020, SSP1ICR - 0xE003 0020). . . 394
SSPn DMA Control Register (SSP0DMACR 0xE006 8024, SSP1DMACR - 0xE003 0024). . .
394

Chapter 18: SD_MMC card interface
1
2
3
4
4.1
4.2
4.2.1
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.104.3.11
4.3.124.3.13Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Features of the MCI . . . . . . . . . . . . . . . . . . . . 395
SD/MMC card interface pin description . . . . 395
Functional overview . . . . . . . . . . . . . . . . . . . 395
Mutimedia card . . . . . . . . . . . . . . . . . . . . . . . 395
Secure digital memory card . . . . . . . . . . . . . 396
Secure digital memory card bus signals . . . . 396
MCI adapter . . . . . . . . . . . . . . . . . . . . . . . . . 397
Adapter register block. . . . . . . . . . . . . . . . . . 397
Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Command path . . . . . . . . . . . . . . . . . . . . . . . 398
Command path state machine . . . . . . . . . . . 398
Command format . . . . . . . . . . . . . . . . . . . . . 399
Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Data path state machine. . . . . . . . . . . . . . . . 401
Data counter . . . . . . . . . . . . . . . . . . . . . . . . . 403
Bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
CRC Token status. . . . . . . . . . . . . . . . . . . . . 404
Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . 404
CRC generator . . . . . . . . . . . . . . . . . . . . . . . 404
Data FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

4.3.144.3.154.3.164.3.17
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7

5.8

Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . .
Receive FIFO. . . . . . . . . . . . . . . . . . . . . . . .
APB interfaces . . . . . . . . . . . . . . . . . . . . . . .
Interrupt logic . . . . . . . . . . . . . . . . . . . . . . . .
Register description . . . . . . . . . . . . . . . . . . .
Summary of MCI Registers . . . . . . . . . . . . .
Power Control Register (MCI Power 0xE008 C000) . . . . . . . . . . . . . . . . . . . . . . .
Clock Control Register (MCIClock 0xE008 C004) . . . . . . . . . . . . . . . . . . . . . . .
Argument Register (MCIArgument 0xE008 C008) . . . . . . . . . . . . . . . . . . . . . . .
Command Register (MCICommand 0xE008 C00C) . . . . . . . . . . . . . . . . . . . . . . .
Command Response Register(MCIRespCommand - 0xE008 C010) . . . . .
Response Registers (MCIResponse0-3 0xE008 C014, E008 C018, E008 C01C andE008 C020) . . . . . . . . . . . . . . . . . . . . . . . . .
Data Timer Register (MCIDataTimer 0xE008 C024) . . . . . . . . . . . . . . . . . . . . . . .

405
405
406
406
406
406
407
408
408
408
409

410
410

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

611 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

5.9
5.10
5.11
5.12
5.13

Data Length Register (MCIDataLength 0xE008 C028). . . . . . . . . . . . . . . . . . . . . . . . 410
Data Control Register (MCIDataCtrl 0xE008 C02C) . . . . . . . . . . . . . . . . . . . . . . . 411
Data Counter Register (MCIDataCnt 0xE008 C030). . . . . . . . . . . . . . . . . . . . . . . . 411
Status Register (MCIStatus - 0xE008 C034) 412
Clear Register (MCIClear - 0xE008 C038) . . 413

5.14

5.15
5.16

Interrupt Mask Registers (MCIMask0 0xE008 C03C and MCIMask1 - 0xE008 C0040) .
413
FIFO Counter Register (MCIFifoCnt 0xE008 C048) . . . . . . . . . . . . . . . . . . . . . . . 414
Data FIFO Register (MCIFIFO - 0xE008 C080 to
0xE008 C0BC) . . . . . . . . . . . . . . . . . . . . . . . 414

Chapter 19: I2C interfaces I2C0, I2C1, I2C2
1
2
3
4
5
5.1
5.2
5.3
5.4
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
7.1
7.2
7.3
7.4
7.5
7.6

7.7

7.8

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 417
I2C operating modes . . . . . . . . . . . . . . . . . . . 417
Master Transmitter mode . . . . . . . . . . . . . . . 417
Master Receiver mode . . . . . . . . . . . . . . . . . 418
Slave Receiver mode . . . . . . . . . . . . . . . . . . 419
Slave Transmitter mode . . . . . . . . . . . . . . . . 420
I2C implementation and operation . . . . . . . . 421
Input filters and output stages. . . . . . . . . . . . 421
Address Register I2ADDR . . . . . . . . . . . . . . 423
Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . 423
Shift register I2DAT. . . . . . . . . . . . . . . . . . . . 423
Arbitration and synchronization logic . . . . . . 423
Serial clock generator . . . . . . . . . . . . . . . . . . 424
Timing and control . . . . . . . . . . . . . . . . . . . . 424
Control register I2CONSET and I2CONCLR 424
Status decoder and status register . . . . . . . . 425
Register description . . . . . . . . . . . . . . . . . . . 425
I2C Control Set Register (I2C[0/1/2]CONSET:
0xE001 C000, 0xE005 C000, 0xE008 0000) 426
I2C Control Clear Register (I2C[0/1/2]CONCLR:
0xE001 C018, 0xE005 C018, 0xE008 0018) 428
I2C Status Register (I2C[0/1/2]STAT 0xE001 C004, 0xE005 C004, 0xE008 0004) 428
I2C Data Register (I2C[0/1/2]DAT - 0xE001 C008,
0xE005 C008, 0xE008 0008) . . . . . . . . . . . . 429
I2C Slave Address Register (I2C[0/1/2]ADR 0xE001 C00C, 0xE005 C00C, 0xE008 000C) 429
I2C SCL High Duty Cycle Register(I2C[0/1/2]SCLH - 0xE001 C010, 0xE0015 C010,
0xE008 0010) . . . . . . . . . . . . . . . . . . . . . . . . 429
I2C SCL Low Duty Cycle Register(I2C[0/1/2]SCLL - 0xE001 C014, 0xE0015 C014,
0xE008 0014) . . . . . . . . . . . . . . . . . . . . . . . . 429
Selecting the appropriate I2C data rate and duty
cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

8
Details of I2C operating modes . . . . . . . . . . 430
8.1
Master Transmitter mode . . . . . . . . . . . . . . . 431
8.2
Master Receiver mode. . . . . . . . . . . . . . . . . 432
8.3
Slave Receiver mode. . . . . . . . . . . . . . . . . . 432
8.4
Slave Transmitter mode . . . . . . . . . . . . . . . . 437
8.5
Miscellaneous states . . . . . . . . . . . . . . . . . . 443
19.8.5.1 I2STAT = 0xF8 . . . . . . . . . . . . . . . . . . . . . . . 443
19.8.5.2 I2STAT = 0x00 . . . . . . . . . . . . . . . . . . . . . . . 443
8.6
Some special cases . . . . . . . . . . . . . . . . . . . 444
8.7
Simultaneous repeated START conditions fromtwo masters . . . . . . . . . . . . . . . . . . . . . . . . . 444
8.8
Data transfer after loss of arbitration . . . . . . 444
8.9
Forced access to the I2C bus. . . . . . . . . . . . 444
8.10
I2C Bus obstructed by a Low level on SCL or SDA
445
8.11
Bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
8.12
I2C State service routines. . . . . . . . . . . . . . . 446
8.12.1
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 446
8.12.2I2C interrupt service . . . . . . . . . . . . . . . . . . . 447
8.12.3The state service routines . . . . . . . . . . . . . . 447
8.12.4Adapting state services to an application. . . 447
9Software example . . . . . . . . . . . . . . . . . . . . . 447
9.1
Initialization routine . . . . . . . . . . . . . . . . . . . 447
9.2
Start master transmit function . . . . . . . . . . . 447
9.3
Start master receive function . . . . . . . . . . . . 447
9.4
I2C interrupt routine . . . . . . . . . . . . . . . . . . . 448
9.5
Non mode specific states . . . . . . . . . . . . . . . 448
9.5.1
State : 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . 448
9.6
Master states . . . . . . . . . . . . . . . . . . . . . . . . 448
9.6.1
State : 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . 448
9.6.2
State : 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . 448
9.7
Master Transmitter states . . . . . . . . . . . . . . 449
9.7.1
State : 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . 449
9.7.2
State : 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . 449
9.7.3
State : 0x28 . . . . . . . . . . . . . . . . . . . . . . . . . 449
9.7.4
State : 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . 449
9.7.5
State : 0x38 . . . . . . . . . . . . . . . . . . . . . . . . . 450
9.8
Master Receive states . . . . . . . . . . . . . . . . . 450
9.8.1
State : 0x40 . . . . . . . . . . . . . . . . . . . . . . . . . 450
9.8.2
State : 0x48 . . . . . . . . . . . . . . . . . . . . . . . . . 450

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

612 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

9.8.3
9.8.4
9.9
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.9.6

State : 0x50. . . . . . . . . . . . . . . . . . . . . . . . . . 450
State : 0x58. . . . . . . . . . . . . . . . . . . . . . . . . . 450
Slave Receiver states . . . . . . . . . . . . . . . . . . 451
State : 0x60. . . . . . . . . . . . . . . . . . . . . . . . . . 451
State : 0x68. . . . . . . . . . . . . . . . . . . . . . . . . . 451
State : 0x70. . . . . . . . . . . . . . . . . . . . . . . . . . 451
State : 0x78. . . . . . . . . . . . . . . . . . . . . . . . . . 451
State : 0x80. . . . . . . . . . . . . . . . . . . . . . . . . . 452
State : 0x88. . . . . . . . . . . . . . . . . . . . . . . . . . 452

9.9.7
9.9.8
9.9.9
9.10
9.10.19.10.29.10.39.10.49.10.5

State : 0x90 . . . . . . . . . . . . . . . . . . . . . . . . .
State : 0x98 . . . . . . . . . . . . . . . . . . . . . . . . .
State : 0xA0 . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Transmitter States . . . . . . . . . . . . . . .
State : 0xA8 . . . . . . . . . . . . . . . . . . . . . . . . .
State : 0xB0 . . . . . . . . . . . . . . . . . . . . . . . . .
State : 0xB8 . . . . . . . . . . . . . . . . . . . . . . . . .
State : 0xC0 . . . . . . . . . . . . . . . . . . . . . . . . .
State : 0xC8 . . . . . . . . . . . . . . . . . . . . . . . . .

452
452
452
453
453
453
453
453
454

Chapter 20: I2S
1
2
3
4
4.1
4.2
4.3
4.4

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . 456
Register description . . . . . . . . . . . . . . . . . . . 457
Digital Audio Output Register (I2SDAO 0xE008 8000) . . . . . . . . . . . . . . . . . . . . . . . . 458
Digital Audio Input Register (I2SDAI 0xE008 8004) . . . . . . . . . . . . . . . . . . . . . . . . 458
Transmit FIFO Register (I2STXFIFO 0xE008 8008) . . . . . . . . . . . . . . . . . . . . . . . . 459
Receive FIFO Register (I2SRXFIFO 0xE008 800C). . . . . . . . . . . . . . . . . . . . . . . . 459

4.5
4.6
4.7
4.8
4.9
4.10
5
6

Status Feedback Register (I2SSTATE 0xE008 8010). . . . . . . . . . . . . . . . . . . . . . . . 459
DMA Configuration Register 1 (I2SDMA1 0xE008 8014). . . . . . . . . . . . . . . . . . . . . . . . 460
DMA Configuration Register 2 (I2SDMA2 0xE008 8018). . . . . . . . . . . . . . . . . . . . . . . . 460
Interrupt Request Control Register (I2SIRQ 0xE008 801C) . . . . . . . . . . . . . . . . . . . . . . . 460
Transmit Clock Rate Register (I2STXRATE 0xE008 8020). . . . . . . . . . . . . . . . . . . . . . . . 461
Receive Clock Rate Register (I2SRXRATE 0xE008 8024). . . . . . . . . . . . . . . . . . . . . . . . 461
I2S transmit and receive interfaces . . . . . . . 461
FIFO controller . . . . . . . . . . . . . . . . . . . . . . . 462

Chapter 21: Timer 0, 1, 2, 3
1
2
3
4
4.1
5
5.1
5.2

5.3

5.4

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 465
Multiple CAP and MAT pins . . . . . . . . . . . . . 466
Register description . . . . . . . . . . . . . . . . . . . 466
Interrupt Register (T[0/1/2/3]IR - 0xE000 4000,
0xE000 8000, 0xE007 0000, 0xE007 4000) . 468
Timer Control Register (T[0/1/2/3]CR 0xE000 4004, 0xE000 8004, 0xE007 0004,
0xE007 4004) . . . . . . . . . . . . . . . . . . . . . . . . 468
Count Control Register (T[0/1/2/3]CTCR 0xE000 4070, 0xE000 8070, 0xE007 0070,
0xE007 4070) . . . . . . . . . . . . . . . . . . . . . . . . 468
Timer Counter . . . . . . . .registers (T0TC - T3TC,
0xE000 4008, 0xE000 8008, 0xE007 0008,
0xE007 4008) . . . . . . . . . . . . . . . . . . . . . . . . 469

5.5

6
7

Prescale register (T0PR - T3PR, 0xE000 400C,
0xE000 800C, 0xE007 000C, 0xE007 400C) 470
Prescale Counter register (T0PC - T3PC,
0xE000 4010, 0xE000 8010, 0xE007 0010,
0xE007 4010). . . . . . . . . . . . . . . . . . . . . . . . 470
Match Registers (MR0 - MR3) . . . . . . . . . . . 470
Match Control Register (T[0/1/2/3]MCR 0xE000 4014, 0xE000 8014, 0xE007 0014,
0xE007 4014). . . . . . . . . . . . . . . . . . . . . . . . 470
Capture Registers (CR0 - CR3) . . . . . . . . . . 471
Capture Control Register (T[0/1/2/3]CCR 0xE000 4028, 0xE000 8028, 0xE007 0028,
0xE007 4028). . . . . . . . . . . . . . . . . . . . . . . . 471
External Match Register (T[0/1/2/3]EMR 0xE000 403C, 0xE000 803C, 0xE007 003C,
0xE007 403C) . . . . . . . . . . . . . . . . . . . . . . . 473
Example timer operation . . . . . . . . . . . . . . . 474
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 474

2

Applications. . . . . . . . . . . . . . . . . . . . . . . . . . 476

5.6

5.7
5.8

5.9
5.10

5.11

Chapter 22: Watchdog Timer (WDT)
1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

613 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

3
4
4.1
4.2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
Register description . . . . . . . . . . . . . . . . . . . 477
Watchdog Mode Register (WDMOD 0xE000 0000) . . . . . . . . . . . . . . . . . . . . . . . . 477
Watchdog Timer Constant Register (WDTC 0xE000 0004) . . . . . . . . . . . . . . . . . . . . . . . . 478

4.3
4.4
4.5
5

Watchdog Feed Register (WDFEED 0xE000 0008). . . . . . . . . . . . . . . . . . . . . . . . 478
Watchdog Timer Value Register (WDTV 0xE000 000C) . . . . . . . . . . . . . . . . . . . . . . . 479
Watchdog Timer Clock Source Selection Register(WDCLKSEL - 0xE000 0010) . . . . . . . . . . . 479
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 480

Chapter 23: Pulse Width Modulator (PWM)
1
2
3
3.1
3.2
4
5
6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Sample waveform with rules for single anddouble edge control. . . . . . . . . . . . . . . . . . . . 484
Rules for Single Edge Controlled PWM Outputs .
485
Rules for Double Edge Controlled PWM Outputs.
485
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 485
PWM base addresses . . . . . . . . . . . . . . . . . . 486
Register description . . . . . . . . . . . . . . . . . . . 486

6.1
6.2
6.3
6.4
6.5
6.6
6.7

PWM Interrupt Register (PWM1IR - 0xE001 8000)
487
PWM Timer Control Register (PWM1TCR 0xE001 8004). . . . . . . . . . . . . . . . . . . . . . . . 488
PWM Count Control Register (PWM1CTCR 0xE001 8070). . . . . . . . . . . . . . . . . . . . . . . . 488
PWM Match Control Register (PWM1MCR 0xE001 8014). . . . . . . . . . . . . . . . . . . . . . . . 489
PWM Capture Control Register (PWM1CCR 0xE001 8028). . . . . . . . . . . . . . . . . . . . . . . . 491
PWM Control Registers (PWM1PCR 0xE001 804C) . . . . . . . . . . . . . . . . . . . . . . . 492
PWM Latch Enable Register (PWM1LER 0xE001 8050). . . . . . . . . . . . . . . . . . . . . . . . 493

Chapter 24: Analog-to-Digital Converter (ADC)
1
2
3
4
4.1
4.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 495
Register description . . . . . . . . . . . . . . . . . . . 496
A/D Control Register (AD0CR - 0xE003 4000). . .
496
A/D Global Data Register (AD0GDR 0xE003 4004) . . . . . . . . . . . . . . . . . . . . . . . . 498

4.3

5
5.1
5.2
5.3

A/D Status Register (AD0STAT - 0xE003 4030) .
498
A/D Interrupt Enable Register (AD0INTEN 0xE003 400C) . . . . . . . . . . . . . . . . . . . . . . . 499
A/D Data Registers (AD0DR0 to AD0DR7 0xE003 4010 to 0xE003 402C) . . . . . . . . . . 499
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Hardware-triggered conversion . . . . . . . . . . 500
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Accuracy vs. Digital Receiver . . . . . . . . . . . 500

34Register description (DACR - 0xE006 C000) 501
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

4.4
4.5

Chapter 25: Digital-to-Analog Converter (DAC)1
2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 501

Chapter 26: Real Time Clock (RTC) and battery RAM
1
2
3
4
4.1
4.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Register description . . . . . . . . . . . . . . . . . . . 504
RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . 505
Miscellaneous register group . . . . . . . . . . . . 506

4.2.1
4.2.2
4.2.3

Interrupt Location Register (ILR - 0xE002 4000) .
506
Clock Tick Counter Register (CTCR 0xE002 4004). . . . . . . . . . . . . . . . . . . . . . . . 506
Clock Control Register (CCR - 0xE002 4008) 507

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

614 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

4.2.4
4.2.5
4.2.6
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1

Counter Increment Interrupt Register (CIIR 0xE002 400C). . . . . . . . . . . . . . . . . . . . . . . . 507
Counter Increment Select Mask Register (CISS 0xE002 4040) . . . . . . . . . . . . . . . . . . . . . . . . 508
Alarm Mask Register (AMR - 0xE002 4010). 508
Consolidated time registers . . . . . . . . . . . . . 509
Consolidated Time Register 0 (CTIME0 0xE002 4014) . . . . . . . . . . . . . . . . . . . . . . . . 509
Consolidated Time Register 1 (CTIME1 0xE002 4018) . . . . . . . . . . . . . . . . . . . . . . . . 509
Consolidated Time Register 2 (CTIME2 0xE002 401C). . . . . . . . . . . . . . . . . . . . . . . . 510
Time Counter Group . . . . . . . . . . . . . . . . . . . 510
Leap year calculation . . . . . . . . . . . . . . . . . . 511

5
6
7
8
8.1
8.2
8.3
8.4
8.5
9
10

Alarm register group. . . . . . . . . . . . . . . . . . . . 511
Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . 511
RTC usage notes. . . . . . . . . . . . . . . . . . . . . . 512
RTC clock generation . . . . . . . . . . . . . . . . . . 512
Reference Clock Divider (Prescaler) . . . . . . 512
Prescaler Integer Register (PREINT 0xE002 4080). . . . . . . . . . . . . . . . . . . . . . . . 513
Prescaler Fraction Register (PREFRAC 0xE002 4084). . . . . . . . . . . . . . . . . . . . . . . . 513
Example of Prescaler Usage . . . . . . . . . . . . 513
Prescaler operation . . . . . . . . . . . . . . . . . . . 514
Battery RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 515
RTC external 32 kHz oscillator component
selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

Chapter 27: Flash memory programming firmware
1
2
3
4
4.1
4.1.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10
5
6
7
8
8.1
8.2
8.3
8.4

Flash boot loader . . . . . . . . . . . . . . . . . . . . . . 517
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Memory map after any reset. . . . . . . . . . . . . 518
Criterion for Valid User Code . . . . . . . . . . . . 518
Communication protocol . . . . . . . . . . . . . . . . 519
ISP command format . . . . . . . . . . . . . . . . . . 519
ISP response format . . . . . . . . . . . . . . . . . . . 519
ISP data format. . . . . . . . . . . . . . . . . . . . . . . 519
ISP flow control. . . . . . . . . . . . . . . . . . . . . . . 520
ISP command abort . . . . . . . . . . . . . . . . . . . 520
Interrupts during ISP. . . . . . . . . . . . . . . . . . . 520
Interrupts during IAP. . . . . . . . . . . . . . . . . . . 520
RAM used by ISP command handler . . . . . . 520
RAM used by IAP command handler . . . . . . 520
RAM used by RealMonitor . . . . . . . . . . . . . . 520
Boot process flowchart . . . . . . . . . . . . . . . . . 521
Sector numbers . . . . . . . . . . . . . . . . . . . . . . . 522
Code Read Protection (CRP) . . . . . . . . . . . . 523
ISP commands . . . . . . . . . . . . . . . . . . . . . . . . 524
Unlock <Unlock code> . . . . . . . . . . . . . . . . . 525
Set Baud Rate <Baud Rate> <stop bit> . . . . 525
Echo <setting> . . . . . . . . . . . . . . . . . . . . . . . 526
Write to RAM <start address> <number of bytes>
526

8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
10

Read Memory <address> <no. of bytes>. . . 526
Prepare sector(s) for write operation <start sector
number> <end sector number> . . . . . . . . . . 527
Copy RAM to flash <flash address> <RAM
address> <no of bytes> . . . . . . . . . . . . . . . . 528
Go <address> <mode> . . . . . . . . . . . . . . . . 528
Erase sector(s) <start sector number> <end
sector number> . . . . . . . . . . . . . . . . . . . . . . 529
Blank check sector(s) <sector number> <end
sector number> . . . . . . . . . . . . . . . . . . . . . . 529
Read Part Identification number . . . . . . . . . 529
Read Boot code version number . . . . . . . . . 530
Compare <address1> <address2> <no of bytes>
530
ISP Return Codes . . . . . . . . . . . . . . . . . . . . 531
IAP commands . . . . . . . . . . . . . . . . . . . . . . . 531
Prepare sector(s) for write operation . . . . . . 533
Copy RAM to flash . . . . . . . . . . . . . . . . . . . . 534
Erase Sector(s) . . . . . . . . . . . . . . . . . . . . . . 535
Blank check sector(s). . . . . . . . . . . . . . . . . . 535
Read Part Identification number . . . . . . . . . 535
Read Boot code version number . . . . . . . . . 536
Compare <address1> <address2> <no of bytes>
536
Reinvoke ISP . . . . . . . . . . . . . . . . . . . . . . . . 536
IAP Status Codes. . . . . . . . . . . . . . . . . . . . . 537
JTAG flash programming interface . . . . . . . 537

Chapter 28: General Purpose DMA controller (GPDMA)
1
2
3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Features of the GPDMA. . . . . . . . . . . . . . . . . 538
Functional overview . . . . . . . . . . . . . . . . . . . 539

3.1
3.1.1
3.1.2

GPDMA functional description . . . . . . . . . . . 539
AHB Slave Interface. . . . . . . . . . . . . . . . . . . 540
Control Logic and Register Bank . . . . . . . . . 540

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

615 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
3.1.103.1.11
3.1.12
3.1.13
3.2
4
5
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8

DMA Request and Response Interface . . . . 540
Channel Logic and Channel Register Bank . 540
Interrupt Request . . . . . . . . . . . . . . . . . . . . . 540
AHB Master Interface . . . . . . . . . . . . . . . . . . 540
Bus and Transfer Widths . . . . . . . . . . . . . . . 541
Endian Behavior . . . . . . . . . . . . . . . . . . . . . . 541
Error Conditions . . . . . . . . . . . . . . . . . . . . . . 543
Channel Hardware . . . . . . . . . . . . . . . . . . . . 543
DMA Request Priority . . . . . . . . . . . . . . . . . . 543
Interrupt Generation . . . . . . . . . . . . . . . . . . . 543
The completion of the DMA transfer indication. . .
544
DMA System Connections . . . . . . . . . . . . . . 544
Programmer’s model . . . . . . . . . . . . . . . . . . . 544
About the programmer’s model . . . . . . . . . . 545
Programming the GPDMA. . . . . . . . . . . . . . . 545
Enabling the GPDMA . . . . . . . . . . . . . . . . . . 545
Disabling the GPDMA. . . . . . . . . . . . . . . . . . 545
Enabling a DMA Channel . . . . . . . . . . . . . . . 545
Disabling a DMA Channel . . . . . . . . . . . . . . 546
Disabling a DMA Channel Without Losing Data in
the FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Setup a New DMA Transfer . . . . . . . . . . . . . 546
Disabling a DMA Channel and Losing Data in the
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Halting a DMA Transfer . . . . . . . . . . . . . . . . 546
Programming a DMA Channel . . . . . . . . . . . 546
Summary of GPDMA registers . . . . . . . . . . . 547
Register descriptions . . . . . . . . . . . . . . . . . . 548
Interrupt Status Register (DMACIntStatus 0xFFE0 4000) . . . . . . . . . . . . . . . . . . . . . . . . 548
Interrupt Terminal Count Status Register(DMACIntTCStatus - 0xFFE0 4004) . . . . . . . 549
Interrupt Terminal Count Clear Register(DMACIntClear - 0xFFE0 4008) . . . . . . . . . . 549
Interrupt Error Status Register(DMACIntErrorStatus - 0xFFE0 400C) . . . . . 549
Interrupt Error Clear Register (DMACIntErrClr 0xFFE0 4010) . . . . . . . . . . . . . . . . . . . . . . . . 550
Raw Interrupt Terminal Count Status Register(DMACRawIntTCStatus - 0xFFE0 4014) . . . 550
Raw Error Interrupt Status Register(DMACRawIntErrorStatus - 0xFFE0 4018). . 550
Enabled Channel Register (DMACEnbldChns 0xFFE0 401C) . . . . . . . . . . . . . . . . . . . . . . . 551

8.9

13.2
13.3
14

Software Burst Request Register(DMACSoftBReq - 0xFFE0 4020) . . . . . . . . 551
Software Single Request Register(DMACSoftSReq - 0xFFE0 4024) . . . . . . . . 552
Software Last Burst Request Register(DMACSoftLBreq - 0xFFE0 4028) . . . . . . . . 552
Software Last Single Request Register(DMACSoftLSReq - 0xFFE0 402C) . . . . . . . 552
Configuration Register (DMACConfiguration 0xFFE0 4030) . . . . . . . . . . . . . . . . . . . . . . . 553
Synchronization Register (DMACSync 0xFFE0 4034) . . . . . . . . . . . . . . . . . . . . . . . 553
Channel registers . . . . . . . . . . . . . . . . . . . . . 554
Channel Source Address Registers(DMACC0SrcAddr - 0xFFE0 4100 and
DMACC1SrcAddr - 0xFFE0 4120). . . . . . . . 554
Channel Destination Address Registers(DMACC0DestAddr - 0xFFE0 4104 andDMACC1DestAddr - 0xFFE0 4124). . . . . . . 555
Channel Linked List Item Registers (DMACC0LLI- 0xFFE0 4108 and DMACC1LLI - 0xFFE0 4128)
555
Channel Control Registers (DMACC0Control 0xFFE0 410C and DMACC0Control 0xFFE0 412C) . . . . . . . . . . . . . . . . . . . . . . . 555
Protection and Access Information . . . . . . . 557
Channel Configuration Registers(DMACC0Configuration - 0xFFE0 4110 and
DMACC1Configuration - 0xFFE0 4130) . . . 558
Lock control . . . . . . . . . . . . . . . . . . . . . . . . . 559
Flow control and transfer type . . . . . . . . . . . 560
Address generation . . . . . . . . . . . . . . . . . . . 560
Scatter/Gather . . . . . . . . . . . . . . . . . . . . . . . . 560
Linked List Items . . . . . . . . . . . . . . . . . . . . . 560
Programming the GPDMA for scatter/gather DMA
561
Example of scatter/gather DMA . . . . . . . . . . 561
Interrupt requests . . . . . . . . . . . . . . . . . . . . . 563
Hardware interrupt sequence flow . . . . . . . . 563
Interrupt polling sequence flow . . . . . . . . . . 563
GPDMA data flow . . . . . . . . . . . . . . . . . . . . . 564
Peripheral-to-memory, or Memory-to-peripheral
DMA Flow . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Peripheral-to-peripheral DMA Flow . . . . . . . 565
Memory-to-memory DMA Flow . . . . . . . . . . 565
Flow control. . . . . . . . . . . . . . . . . . . . . . . . . . 566

2

Applications. . . . . . . . . . . . . . . . . . . . . . . . . . 567

8.10
8.11
8.12
8.13
8.14
9
9.1

9.2

9.3

9.4

9.5
9.6

9.7
9.8
10
11
11.1
11.2
11.3
12
12.1
12.2
13
13.1

Chapter 29: EmbeddedICE logic
1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567

continued >>UM10211_1

User manual© NXP B.V. 2007. All rights reserved.

Rev. 01 — 6 July 2007

616 of 617

UM10211NXP Semiconductors

Chapter 32: Supplementary information

3
4
5

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 568
JTAG function select . . . . . . . . . . . . . . . . . . . 568

6
7

Register description . . . . . . . . . . . . . . . . . . . 569
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 569

4
5
6
7

Pin description . . . . . . . . . . . . . . . . . . . . . . .
Register description . . . . . . . . . . . . . . . . . . .
Reset state of multiplexed pins . . . . . . . . . .
Block diagram . . . . . . . . . . . . . . . . . . . . . . . .

571
571
572
573

4.4
4.5
4.6
4.7
4.8
4.9
4.9.1
4.10
4.11
5

SVC Mode . . . . . . . . . . . . . . . . . . . . . . . . . .
Prefetch Abort Mode . . . . . . . . . . . . . . . . . .
Data Abort Mode . . . . . . . . . . . . . . . . . . . . .
User/System Mode . . . . . . . . . . . . . . . . . . .
FIQ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
Handling Exceptions . . . . . . . . . . . . . . . . . .
RealMonitor Exception Handling . . . . . . . . .
RMTarget Initialization . . . . . . . . . . . . . . . . .
Code Example . . . . . . . . . . . . . . . . . . . . . . .
RealMonitor Build Options. . . . . . . . . . . . . .

577
578
578
578
578
578
578
579
579
582

3
4
5

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

Chapter 30: EmbeddedTrace Module (ETM)
1
2
3
3.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
ETM configuration . . . . . . . . . . . . . . . . . . . . 570

Chapter 31: RealMonitor
1
2
3
3.1
3.1.1
3.1.2
3.2
4
4.1
4.2
4.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
RealMonitor Components . . . . . . . . . . . . . . . 575
RMHost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
RMTarget . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
How RealMonitor Works . . . . . . . . . . . . . . . . 576
How to Enable RealMonitor . . . . . . . . . . . . . 577
Adding Stacks . . . . . . . . . . . . . . . . . . . . . . . . 577
IRQ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
Undef Mode . . . . . . . . . . . . . . . . . . . . . . . . . 577

Chapter 32: Supplementary information
1
2
2.1
2.2
2.3

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 585
Legal information. . . . . . . . . . . . . . . . . . . . . . 586
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 586
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 586

617

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

© NXP B.V. 2007.

All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 July 2007
Document identifier: UM10211_1