88W8987_SDS

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2
Solution
Rev. 6 — 2 December 2022

1

Product short data sheet

Product overview
The 88W8987 is a highly integrated Wi-Fi (2.4/5 GHz) and Bluetooth single-chip solution,
specifically designed to support the speed, reliability, and quality requirements of next
generation Very High Throughput (VHT) products.
The System-on-Chip (SoC) provides both simultaneous and independent operation of thefollowing:• IEEE 802.11ac (Wave 2), 1x1 with data rates up to MCS9 (433 Mbit/s)• Bluetooth 5.2 (includes Bluetooth Low Energy (LE))
The SoC also provides:• Bluetooth Classic and Bluetooth LE dual (Smart Ready) operation• Wi-Fi indoor location positioning (802.11mc)
For security, the device supports high performance 802.11i security standards throughimplementation of the Advanced Encryption Standard (AES)/Counter Mode CBCMAC Protocol (CCMP), AES/Galois/Counter Mode Protocol (GCMP), AES/CipherBased Message Authentication Code (CMAC), and WLAN Authentication and Privacy
Infrastructure (WAPI) security mechanisms.
For video, voice, and multimedia applications, 802.11e Quality of Service (QoS) is
supported. The device also supports 802.11h Dynamic Frequency Selection (DFS) for
detecting radar pulses when operating in the 5 GHz range.
Host interfaces include SDIO 3.0 and high-speed UART interfaces for connecting Wi-Fi
and Bluetooth technologies to the host processor.
The device is designed with two front-end configurations to accommodate Wi-Fi andBluetooth on either separate or shared paths:• 2-antenna configuration—1x1 Wi-Fi and Bluetooth on separate paths (QFN)• 1-antenna configuration—1x1 Wi-Fi and Bluetooth on shared paths (eWLP)
The following figures show the application diagrams for each package option.

88W8987_SDS

NXP Semiconductors

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

Wi-Fi
Antenna

88W8987
SDIO 3.0

Wi-Fi 5 GHz
Diplexer

Bluetooth UART
Wi-Fi 2.4 GHz
PCM

GPIO

Bluetooth
Antenna

Supply voltages
Power-downBluetooth Tx/Rx

XTAL_IN
XTAL_OUT

Figure 1. Application diagram—QFN package option

88W8987
Antenna

SDIO 3.0

Wi-Fi 5 GHz Rx
T/R
switchBluetooth UART
Wi-Fi 5 GHz Tx

Diplexer

PCM
Wi-Fi 2.4 GHz Tx/Rx andBluetooth Tx/Rx

GPIO

Supply voltages
Power-down
XTAL_IN
XTAL_OUT

Figure 2. Application diagram—eWLP package option

88W8987_SDS

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88W8987_SDS

NXP Semiconductors

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

1.1 Applications• Wi-Fi and Bluetooth enabled smart phones and tablets• Personal computing systems including notebooks and ultrabooks• Wireless home audio and video entertainment systems• Mobile routers and Internet of Things (IoT) gateways

1.2 Wi-Fi key features• Support 802.11ac/n/a/g/b• Dual band: 2.4 GHz and 5 GHz• Up to MCS9 data rates• 20/40/80 MHz channel bandwidth• Security: AES, WAPI

1.3 Bluetooth key features• Bluetooth 5.2 support• PCM audio interface• Security: AES

1.4 Host interfaces
Wi-Fi and Bluetooth host interface options
Wi-Fi

Bluetooth

SDIO 3.0

UART

SDIO 3.0

SDIO 3.0

1.5 Operating characteristics• Supply voltage: 2.2V, 1.8V, and 1.1V
• Operating temperature– Extended: -30 to 85°C
– Industrial: -40 to 85°C

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

1.6 General features• Package options– 68-pin 8x8 mm QFN with wettable flanks– 83-bump 4.6x4.2 mm eWLP
• Power management– Low power dissipation– Optional lower power operation with external sleep clock– Sleep and standby modes for low-power operation• Independent ARM-based Wi-Fi and Bluetooth CPUs
• Supports reference clock signal from external crystal or external crystal oscillator• Memory– Internal SRAM
– Boot ROM– One Time Programmable (OTP) memory to store the MAC address and calibration
data• Peripheral interfaces– GPIO interface (up to 21)

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NXP Semiconductors

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

1.7 Internal block diagram

Wi-Fi 5G Tx/Rx
SDIO 3.0

Wi-Fi CPU

1x1
Wi-Fi 5 MAC/Baseband(802.11ac)

1x1
Wi-Fi 5 RF(802.11ac)

Bluetooth/ Bluetooth LE
BasebandBluetooth RF

Host interface

Wi-Fi 2.4G Tx/Rx

UART
BluetoothCPU

Bluetooth Tx/Rx

PCM

Supply voltages

Power regulator

OTP

Coexistence

Figure 3. Internal block diagram—QFN package option

Wi-Fi 5G Tx/Rx
Wi-Fi
CPU

SDIO 3.0

1x1
Wi-Fi 5 MAC/
Baseband (802.11ac)

1x1
Wi-Fi 5 RF(802.11ac)

Wi-Fi 2.4G Tx/Rx
Bluetooth Tx/Rx

Wi-Fi 2.4 GHz Tx

Host interface

Wi-Fi 2.4 GHz Rx
and Bluetooth Rx

S
P
3
T

UART
BluetoothCPU

Bluetooth/ Bluetooth
LE Baseband

BluetoothRF

Bluetooth Tx

PCM

Supplyvoltages

Power regulator

OTP

Coexistence

Figure 4. Internal block diagram—eWLP package option

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NXP Semiconductors

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

2

Ordering information

88W8987-xx-xxxx/xx
Packing code
Temperature code
E = Extended
I = Industrial

Part number

Revision number

Package code

Figure 5. Part numbering scheme

Table 1. Part order codes
Part order code

Package type

Packing

88W8987-A2-NYEE/AK

68-pin HVQFN - 8 x 8 x 0.85 mm, with 0.4 mm pitch

Tray

88W8987-A2-NYEE/AZ

68-pin HVQFN - 8 x 8 x 0.85 mm, with 0.4 mm pitch

Tape and reel

88W8987-A2-NYEI/AK

68-pin HVQFN - 8 x 8 x 0.85 mm, with 0.4 mm pitch

Tray

88W8987-A2-NYEI/AZ

68-pin HVQFN - 8 x 8 x 0.85 mm, with 0.4 mm pitch

Tape and reel

88W8987-A2-EAHE/AZ

83-terminal eWLP - 4.6 x 4.2 x 0.75 mm, with 0.4 mm pitch

Tape and reel

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

3

Wi-Fi subsystem
3.1 IEEE 802.11 standards• 802.11 data rates of 1 and 2 Mbit/s• 802.11b data rates of 5.5 and 11 Mbit/s• 802.11a/g data rates 6, 9, 12, 18, 24, 36, 48, and 54 Mbit/s for multimedia content
transmission• 802.11g/b performance enhancements• 802.11ac / 802.11n with maximum data rates up to 86.7 Mbit/s (20 MHz channel), 200
Mbit/s (40 MHz channel), 433 Mbit/s (80 MHz channel)• 802.11d international roaming• 802.11e quality of service• 802.11h transmit power control• 802.11h DFS radar pulse detection• 802.11i enhanced security• 802.11k radio resource measurement• 802.11mc precise indoor location positioning• 802.11n block acknowledgment extension• 802.11r fast hand-off for AP roaming• 802.11u Hotspot 2.0 (STA mode only)• 802.11v TIM frame transmission/reception• 802.11w protected management frames• Fully supports clients (stations) implementing IEEE Power Save mode

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NXP Semiconductors

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

3.2 Wi-Fi MAC• Simultaneous peer-to-peer and Infrastructure Modes• RTS/CTS for operation under DCF• Hardware filtering of 32 multicast addresses and duplicate frame detection for up to 32
unicast addresses• On-chip Tx and Rx FIFO for maximum throughput• Open System and Shared Key Authentication services• A-MPDU Rx (de-aggregation) and Tx (aggregation) (supports 802.11ac single-MPDU
A-MPDU)• 20/40/80 MHz coexistence• Reduced Inter-Frame Spacing (RIFS) receive• Management information base counters• Radio resource measurement counters• Quality of service queues• Block acknowledgment extension• Dynamic frequency selection• Beamforming– 802.11ac Explicit Beamformee, supports immediate feedback generation using
802.11ac compressed steering matrix feedback– 802.11ac Multi-User Beamformee– 802.11n Explicit Beamformee, supports immediate feedback generation using
uncompress and compress steering matrix or delayed feedback of all feedback types• TIM frame transmission/reception• Multiple-BSS/Station• Transmit rate adaptation• Transmit power control• Long and short preamble generation on a frame-by-frame basis for 802.11b frames• Mobile hotspot

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NXP Semiconductors

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

3.3 Wi-Fi baseband• 802.11ac (on-chip RF radio)• Backward compatibility with legacy 802.11n/a/g/b technology• Simultaneous Wi-Fi and Bluetooth receive in single-antenna mode (eWLP only)• PHY data rates up to 433 Mbit/s• 20 MHz bandwidth/channel, 40 MHz bandwidth/channel, upper/lower 20 MHz packets
in 40 MHz channel, 20 MHz duplicate legacy packets in 40 MHz channel mode
operation• 80 MHz bandwidth/channel, 4 positions of 20 MHz packets in 80 MHz channel, upper/
lower 40 MHz packets in 80 MHz channel, 20 MHz quadruplicate legacy packets in
80 MHz channel mode operation• Modulation and Coding Scheme (MCS)– 802.11ac—MCS 0~9 Nsts = 1– 802.11n—MCS 0~7 and MCS 32 (duplicate 6 Mbit/s)• Dynamic frequency selection (radar detection)– Enhanced radar detection for long and short pulse radar– Enhanced AGC scheme for DFS channel– Japan DFS requirements for W53 and W56 frequency bands• Radio resource measurement• Optional 802.11ac and 802.11n features:– 20/40/80 MHz coexistence with middle-packet detection (GI detection) for enhanced
CCA– 1 spatial stream STBC reception– LDPC transmission and reception for both 802.11n and 802.11ac– 256 QAM (MCS 8, 9) modulation, optional support for 802.11ac MCS 9 in 20 MHz
using LDPC
– Short guard interval– RIFS on receive path for 802.11n packets– 802.11n greenfield Tx/Rx– Explicit beamformee support– 802.11ac multi-user beamformee– MU-PPDUs (receive)• Wi-Fi indoor locationing (802.11mc)• Power save features

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NXP Semiconductors

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

3.4 Wi-Fi radio• Integrated direct-conversion radio• 20, 40, and 80 MHz channel bandwidths• Shared Wi-Fi/Bluetooth receive input scheme for 2.4 GHz band (eWLP only)

Wi-Fi Rx path
• Direct conversion architecture eliminates need for external SAW filter• On-chip gain selectable LNA with optimized noise figure and power consumption• High dynamic range AGC function in receive mode

Wi-Fi Tx path
• Internal PA with power control• Optimized Tx gain distribution for linearity and noise performance

Wi-Fi local oscillator• Fractional-N for multiple reference clock support• Fine channel step

3.5 Wi-Fi encryption• Advanced Encryption Standard (AES) / Counter-Mode/CBC-MAC Protocol (CCMP)• Advanced Encryption Standard (AES) /Cipher-Based Message Authentication Code(CMAC)• Advanced Encryption Standard (AES) / Galois/Counter Mode Protocol (GCMP)• WLAN Authentication and Privacy Infrastructure (WAPI)

3.6 Wi-Fi host interfaces• SDIO 3.0 device interface (4-bit SDIO and 1-bit SDIO) transfer modes at full clock
range up to 208 MHz

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

4

Bluetooth subsystem
4.1 2.4 GHz Bluetooth Tx/Rx• Bluetooth 5.2• Bluetooth Class 2• Bluetooth Class 1• Single-ended, shared Tx/Rx path for Bluetooth (QFN package option)• Simultaneous Wi-Fi and Bluetooth receive in single-antenna mode (eWLP package
option)• PCM interface for voice applications• Baseband and radio BDR and EDR packet types—1 Mbit/s (GFSK), 2 Mbit/s ( /4DQPSK), and 3 Mbit/s (8DPSK)• Fully functional Bluetooth baseband—AFH, forward error correction, header error
control, access code correlation, CRC, encryption bit stream generation, and whitening• Adaptive Frequency Hopping (AFH) using Packet Error Rate (PER)• Interlaced scan for faster connection setup• Simultaneous active ACL connection support• Automatic ACL packet type selection• Full central and peripheral piconet support• Scatternet support• Standard SDIO and UART HCI transport layer• HCI layer to integrate with profile stack• SCO/eSCO links with hardware accelerated audio signal processing and hardware
supported PPEC algorithm for speech quality improvement• All standard SCO/eSCO voice coding• All standard pairing, authentication, link key, and encryption operations• Standard Bluetooth power-saving mechanisms(sniff modes, and sniff subrating)• Enhanced Power Control (EPC)• Channel Quality Driven Data Rate (CQDDR)• Wideband Speech (WBS) support (1 WBS link)1• Encryption (AES) support

1 Refer to 88W8987 errata sheet (ES_88W8987)
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NXP Semiconductors

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

4.2 Bluetooth Low Energy (LE)• Broadcaster, Observer, Central, and Peripheral roles• Supports link layer topology to be central and peripheral (connects up to 16 links)• Wi-Fi/Bluetooth coexistence protocol support• Shared RF with BDR/EDR
2• Encryption (AES) support• Intelligent Adaptive Frequency Hopping (AFH)• Bluetooth LE Privacy 1.2• Bluetooth LE Secure Connection2• Bluetooth LE Data Length Extension• Bluetooth LE Advertising Extension• 2 Mbit/s Bluetooth LE

2 Refer to 88W8987 errata sheet (ES_88W8987)
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NXP Semiconductors

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

4.3 Bluetooth host interfaces• SDIO 3.0• High-speed UART

4.4 Coexistence• Internal coexistence arbitration for Wi-Fi/Bluetooth

4.5 PCM interface• Central or peripheral mode
• PCM bit width size of 8 bits or 16 bits
• Up to 4 slots with configurable bit width and start positions
3• PCM short frame and long frame synchronization• 3-state PCM interface capability

3 In PCM Central mode, PCM long frame synchronization is 1 clock wide. In PCM peripheral mode, PCM

central long frame synchronization pattern is supported.

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

5

Pin information
5.1 Signal diagrams
5.1.1 Signal diagram for QFN package option
Figure 6 shows the signals for the QFN package of the device.
Note: Signals may be muxed. See Section 5.5 "Pin description".

88W8987
SD_CLK
SD_CMD
SD_DAT[3:0]SDIO interface

Wi-Fi radio
interface
Bluetooth radio
interface

UART_SIN
UART_SOUT
UART_RTSn

BRF_ANT

RF front-end control
interface

RF_CNTL1_P
RF_CNTL2_N
RF_CNTL3_P

CONFIG_HOST[0]PCM_SYNC
PCM_DIN

RF_TR_5

RF_CNTL0_N
UART interface

UART_CTSn

PCM_CLK

RF_TR_2

Host configuration
PCM interface

CONFIG_HOST[1]CONFIG_AUTO_REF_DET

PCM_DOUTGPIO[20:0]
LED_OUT_BT

Power management
interface

DVSC[1]

GPIO/LED interface

LED_OUT_WLAN
Clock interface

JTAG_TCKJTAG_TDIJTAG_TDO
JTAG_TMS

DVSC[0]XTAL_IN
XTAL_OUTSLP_CLK_IN
XOSC_EN

JTAG interface

Power-down

PDn

Figure 6. Signal diagram—QFN

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

5.1.2 Signal diagram for eWLP package option
Figure 7 shows the signals for eWLP package option.
Note: Signals may be muxed. See Section 5.5 "Pin description".

88W8987
SD_CLK
SD_CMD
SD_DAT[3:0]

RF_TR_2 / BRF_ANTSDIO interface

Wi-Fi radio interface

RF_TX_5
RF_RX_5

RF_CNTL0_N

UART_SIN
UART_SOUT
UART_RTSn

RF front-end control
interface

UART interface

UART_CTSn

PCM_DIN

RF_CNTL2_N
RF_CNTL3_P

CONFIG_HOST[0]PCM_SYNC
PCM_CLK

RF_CNTL1_P

Host configuration

CONFIG_HOST[1]CONFIG_AUTO_REF_DET

PCM interface

PCM_DOUT
Power management
interface
GPIO[20:0]
LED_OUT_BT

GPIO/LED interface

LED_OUT_WLAN
JTAG_TCKJTAG_TDIJTAG_TDO
JTAG_TMS

Clock interface

DVSC[0]DVSC[1]

XTAL_IN
XTAL_OUTSLP_CLK_IN
XOSC_EN

JTAG interface
Power-down

PDn

Figure 7. Signal diagram—eWLP

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

5.2 Pin types
Table 2. Pin types
Pin type

Description

I/O

Digital input/output

I

Digital input

O

Digital output

A, I

Analog input

A, O

Analog output

A, I/O

Analog input/output

NC

No connect

DNC

Do not connect

Power

Power

GroundGround88W8987_SDS

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

GPIO[7]GPIO[6]GPIO[5]GPIO[4]GPIO[0]CONFIG_AUTO_REF_DET

CONFIG_HOST[1]CONFIG_HOST[0]DNC

AVDD18

AVDD18

XTAL_OUTXTAL_IN

AVDD18

AVDD18

AVDD18

AVSS

AVSS

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

5.3 Pin assignment—68-pin QFN

52

34

AVDD18

VIO

53

33

AVSS

SLP_CLK_IN

54

32

RF_TR_5

GPIO[1]

55

31

VPA

GPIO[16]

56

30

VPA

GPIO[17]

57

29

AVDD18GPIO[18]58

28

RF_TR_2

GPIO[19]

59

27

AVSS

GPIO[20]

60

26

AVSS

VCORE

61

25

VCORE

VIO_SD62

24

BRF_ANT

SD_CLK

63

23

AVDD18

88W8987

9

10

11

12

13

14

15

16

17

GPIO[15]

GPIO[2]

GPIO[3]PDn

AVDD18

VIO_RF

RF_CNTL0_N

RF_CNTL1_P

8
GPIO[13]GPIO[14]7

RF_CNTL3_P

GPIO[12]18
6RF_CNTL2_N

VCORE

19

68

5

67

SD_DAT[3]GPIO[11]

SD_DAT[2]4

AVDD18VIO

20

3

AVDD1866

GPIO[10]21

SD_DAT[1]2

AVSS

GPIO[9]

22

1

64
65

GPIO[8]SD_CMD
SD_DAT[0][1]

Figure 8. Pin assignment—68-pin QFN package option[1]

EPAD on pin 69.

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NXP Semiconductors

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

5.3.1 Pin list by number
The following table shows the pin list sorted by pin number.
Table 3. Pin list by number

88W8987_SDS

Product short data sheet

Pin number

Pin name

Power

Type

1

GPIO[8]

VIO

I/O

2

GPIO[9]

VIO

I/O

3

GPIO[10]

VIO

I/O

4

VIO

--

Power

5

GPIO[11]

VIO

I/O

6

VCORE

--

Power

7

GPIO[12]

VIO

I/O

8

GPIO[13]

VIO

I/O

9

GPIO[14]

VIO

I/O

10

GPIO[15]

VIO

I/O

11

GPIO[2]

VIO

I/O

12

GPIO[3]

VIO

I/O

13

PDn

AVDD18I

14

AVDD18

--

Power

15

VIO_RF

--

Power

16

RF_CNTL0_N

VIO_RFO

17

RF_CNTL1_P

VIO_RFO

18

RF_CTLN3_P

VIO_RFO

19

RF_CTLN2_N

VIO_RFO

20

AVDD18

--

Power

21

AVDD18

--

Power

22

AVSS

--

Ground23

AVDD18

--

Power

24

BRF_ANT

AVDD18A, I/O

25

VCORE

--

Power

26

AVSS

--

Ground

27

AVSS

--

Ground28

RF_TR_2

AVDD18A, I/O

29

AVDD18

--

Power

30

VPA

--

Power

31

VPA

--

Power

32

RF_TR_5

AVDD18A, I/O

33

AVSS

--

Ground34

AVDD18--Power

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 3. Pin list by number...continued

88W8987_SDS

Product short data sheet

Pin number

Pin name

Power

Type

35

AVSS

--

Ground

36

AVSS

--

Ground37

AVDD18

--

Power

38

AVDD18

--

Power

39

AVDD18

--

Power

40

XTAL_IN

AVDD18I

41

XTAL_OUT

AVDD18

O

42

AVDD18

--

Power

43

AVDD18

--

Power

44

DNC

--

--

45

CONFIG_HOST[0]AVDD18I

46

CONFIG_HOST[1]AVDD18I

47

CONFIG_AUTO_REF_DET

AVDD18I

48

GPIO[0]

VIO

I/O

49

GPIO[4]

VIO

I/O

50

GPIO[5]

VIO

I/O

51

GPIO[6]

VIO

I/O

52

GPIO[7]

VIO

I/O

53

VIO

--

Power

54

SLP_CLK_IN

VIO

I

55

GPIO[1]

VIO

I/O

56

GPIO[16]

VIO

I/O

57

GPIO[17]

VIO

I/O

58

GPIO[18]

VIO

I/O

59

GPIO[19]

VIO

I/O

60

GPIO[20]

VIO

I/O

61

VCORE

--

Power

62

VIO_SD

--

Power

63

SD_CLK

VIO_SDI

64

SD_CMD

VIO_SD

I/O

65

SD_DAT[0]VIO_SD

I/O

66

SD_DAT[1]

VIO_SD

I/O

67

SD_DAT[2]

VIO_SD

I/O

68

SD_DAT[3]VIO_SDI/O

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

5.4 Pad locations—83-bump eWLP
1

2

3

4

5

6

A

A1

A2

A3

A4

A5

A6

B

B1

B3

B4

B5

B6

C

C1

C2

C3

C4

C5

D

D1

D2

D3

D4

D5

E

E1

E2

E3

E4

F

F3

G

H

H1

9

10

A8

A9

A10

B7

B8

B9

B10

C6

C7

C8

C9

C10

D6

D7

D8

D9

D10

E5

E7

E8

E9

E10

F5

F7

F8

F9

F10

G7

G8

G9

G10

G3

G4

G5

H2

H3

H4

H5

J

K

8

G2

G6

7

H7

J3

K1

K2

K3

K4

K5

K6

K7

H10

J8

J9

J10

K8

K9

K10

Non-Bump-Side View

Alphanumeric designations are approximations to the grid.
Figure 9. Pad locations—83-bump eWLP (non-bump-side view, bumps down)

Table 4 indicates the pad locations in 83-bump eWLP package.
Note: Alphanumeric designations are approximations to the grid shown in Figure 9

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 4. Pad locations—83-bump eWLP
Signal name

Alpha-numericdesignation

Pad location relative to die
center (non-bump-side view)
X

Y

NC

A1

-1800.0

1800.0GPIO[18]A2-1400.0

1800.0VSS

A3-1000.0

1800.0GPIO[19]A4-600.01800.0VCORE

A5-200.01800.0

VIO_SD

A6

200.0

1800.0VSS

A81000.01800.0

SD_DAT[3]A91400.01800.0VSS

A101800.01800.0VIO

B1-1800.0

1400.0SLP_CLK_IN

B3-1000.0

1400.0GPIO[16]B4-600.01400.0GPIO[17]B5-200.01400.0GPIO[20]

B6

200.0

1400.0SD_CLK

B7

600.0

1400.0

SD_DAT[0]B81000.01400.0

SD_DAT[1]B91400.01400.0

SD_DAT[2]B101800.01400.0

AVDD18C1-1800.0

1000.0AVSS

C2-1400.0

1000.0GPIO[0] / XOSC_EN

C3-1000.0

1000.0GPIO[6]C4-600.01000.0GPIO[7]C5-200.01000.0GPIO[1]C6

200.0

1000.0SD_CMD

C7

600.0

1000.0GPIO[10]C8

1000.01000.0GPIO[8]C91400.01000.0VIO

C101800.01000.0XTAL_IN

D1-1800.0

600.0

XTAL_OUT

D2-1400.0

600.0

DNC

D3

-1000.0

600.0

CONFIG_HOST[0]D4-600.0600.0

GPIO[4]D5-200.0600.0

GPIO[5]

D6

200.0

600.0

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 4. Pad locations—83-bump eWLP...continued
Signal name

Alpha-numericdesignation

Pad location relative to die
center (non-bump-side view)
X

Y

GPIO[12]

D7

600.0

600.0

GPIO[9]D81000.0600.0

GPIO[11]D91400.0

600.0

VCORE

D10

1800.0600.0

AVDD18E1-1800.0

200.0

AVSS

E2

-1400.0

200.0

AVDD18E3-1000.0

200.0

AVSS

E4

-600.0200.0

CONFIG_AUTO_REF_DET

E5-200.0200.0

GPIO[13]

E7

600.0

200.0

GPIO[3]E81000.0200.0

GPIO[15]E91400.0200.0

GPIO[14]E101800.0

200.0

AVSS

F3

-1000.0-200.0CONFIG_HOST[1]F5-200.0-200.0GPIO[2]F7

600.0-200.0PDn

F81000.0-200.0

AVDD18F91400.0-200.0VSS

F101800.0-200.0

AVDD18G2-1400.0-600.0AVSS

G3-1000.0-600.0VCORE

G4-600.0-600.0AVSS

G5-200.0-600.0

RF_CNTL0_N

G6

200.0

-600.0

RF_CNTL1_P

G7

600.0

-600.0

RF_CNTL3_P

G81000.0-600.0

RF_CNTL2_N

G91400.0-600.0

VIO_RF

G10

1800.0-600.0AVSS

H1-1800.0-1000.0

AVSS

H2-1400.0-1000.0

AVSS

H3-1000.0-1000.0

AVSS

H4-600.0-1000.0

AVSS

H5-200.0-1000.0

AVSS

H7

600.0

-1000.0

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 4. Pad locations—83-bump eWLP...continued
Signal name

Alpha-numericdesignation

Pad location relative to die
center (non-bump-side view)
X

Y

AVSS

H10

1800.0-1000.0

VPA

J3-1000.0-1400.0

AVSS

J8

1000.0-1400.0

AVSS

J9

1400.0-1400.0

AVSS

J10

1800.0-1400.0NCK1-1800.0-1800.0

RF_RX_5

K2-1400.0-1800.0

RF_TX_5

K3-1000.0-1800.0

RF_TR_2 / BRF_ANT

K4-600.0-1800.0

AVDD18K5-200.0-1800.0

AVSS

K6

200.0

-1800.0

AVDD18K7600.0-1800.0

AVDD18K81000.0-1800.0

AVDD18K91400.0-1800.0NCK101800.0-1800.0

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5.5 Pin description
5.5.1 Pin states
The pin states information provided in the tables includes:• No Pad Power State indicates the state when there is no power• PwrDwn State denotes the power-down state in the default configuration. Many pads
have programmable power-down values which can be set by firmware.
• Reset State is the state after the power-on-reset state and before the hardware state(HW State)• HW State (hardware state) is the state after the boot code finishes and before thefirmware download begins (firmware may change the pin state). HW State may
differ based on the pin muxing/configuration setting. For example, for UART_RTSn
and UART_SOUT, the boot code enables the UART interface when the device is in
PCIe-UARTSDIO-UART mode, making the HW states output high and output low,respectively.
• PwrDwn Prog indicates if the power-down state can be programmed• Internal PU/PD columns indicates the following:– Type of PU/PD (weak vs nominal)– The polarity (PU vs. PD)
The internal pull-up or pull-down applies when the pin is in input mode
• PU denotes whether the pull-up can be programmed or not• PD denotes whether the pull-down can be programmed or not• Pull-up and pull-down are only effective when the pad is in input mode
• At the end of the firmware download, the pads (for example GPIO and RF control) areprogrammed in the functional mode corresponding to the functionality of the pins

5.5.2 General purpose I/O (GPIO)[1]

Table 5. General purpose I/O (GPIO) (MFP)
Pins may be Multi-Functional Pins (MFP).
Pin Name Supply

No Pad
Power
[2]
State

Reset
State

HW State

GPIO[20] VIO

tristate

outputoutput high[3]

PwrDwnState

PwrDwnProg

Internal PU/
PD

PU

PD

tristateyes

weak PUyes

yes

weak PUyes

yes

weak PUyes

yes

weak PU

yes

yes

GPIO Mode: GPIO[20] (input/output).
This pin can be used for Bluetooth to host wake-up (out-of-band wake-up signal)
GPIO[19] VIO

tristate

outputoutput hightristate

yes

GPIO Mode: GPIO[19] (input/output)
Power Management Mode: DVSC[1] digital voltage scaling control (output)
GPIO[18] VIO

tristate

outputoutput hightristate

yes

GPIO Mode: GPIO[18] (input/output)
Power Management Mode: DVSC[0] digital voltage scaling control (output)
GPIO[17] VIO

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tristate

input

input

tristateyes

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution[1]

Table 5. General purpose I/O (GPIO) (MFP)...continued
Pins may be Multi-Functional Pins (MFP).
Pin Name Supply

No Pad
Power
[2]
State

Reset
State

HW State

PwrDwnState

PwrDwnProg

Internal PU/
PD

PU

PD

GPIO Mode: GPIO[17] (input/output)
JTAG Mode: JTAG_TDO, JTAG test data (output)
This pin is used as a configuration pin: CON[9] (input). See Section 5.6 "Configuration pins".
GPIO[16] VIO

tristate

input

input

tristateyesnominal PU

yes

yes

outputhighyesnominal PU

yes

yes

tristateyesnominal PU

yes

yes

outputhighyesnominal PU

yes

yes

yes

yes

yes

yes

GPIO Mode: GPIO[16] (input/output)
JTAG Mode: JTAG_TDI, JTAG test data (input)
GPIO[15] VIO

tristate

input

input

GPIO Mode: GPIO[15] (input/output).
This pin can also be used as Bluetooth independent reset.
JTAG Mode: JTAG_TMS, JTAG controller select (input)
GPIO[14] VIO

tristate

input

input

GPIO Mode: GPIO[14] (input/output)
This pin can also be used as Wi-Fi independent reset.
JTAG Mode: JTAG_TCK, JTAG test clock (input)
GPIO[13] VIO

tristate

[4]

input

input
[5]
outputGPIO Mode: GPIO[13] (input/output)
This pin can also be used for host to 88W8987 Wi-Fi wake-up (out-of-band wake-up signal).
GPIO[12] VIO

tristate

input

input

tristateyesnominal PU

GPIO Mode: GPIO[12] (input/output)
This pin can also be used for host to 88W8987 Bluetooth wake-up (out-of-band wake-up signal)
GPIO[11]

VIO

tristate

[4]

input

input
[5]
outputoutputhighyesweak PU

GPIO Mode: GPIO[11] (input/output)
UART Mode: UART_RTSn (output) (active low)This pin is used as a configuration pin: CON[8] (input). See Section 5.6 "Configuration pins".
GPIO[10] VIO

tristate

input

input

tristateyesnominal PU

yes

yes

input

tristateyesnominal PU

yes

yes

weak PU

yes

yes

GPIO Mode: GPIO[10] (input/output)
UART Mode: UART_CTSn (input) (active low)
GPIO[9]VIO

tristate

input

GPIO Mode: GPIO[9] (input/output)
UART Mode: UART_SIN (input)
GPIO[8]

VIO

tristate

input

[4]

input
[5]
outputoutput low yes

GPIO Mode: GPIO[8] (input/output)
UART Mode: UART_SOUT (output)
This pin is used as a configuration pin: CONFIG_XOSC_SEL (input). See Section 5.6 "Configuration pins".

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution[1]

Table 5. General purpose I/O (GPIO) (MFP)...continued
Pins may be Multi-Functional Pins (MFP).
Pin Name Supply

No Pad
Power
[2]
State

Reset
State

HW State

PwrDwnState

PwrDwnProg

Internal PU/
PD

PU

PD

GPIO[7]

tristate

input

input

tristateyesnominal PU

yes

yes

input

tristateyesnominal PU

yes

yes

input

tristateyes

weak PU

yes

yes

VIO

GPIO Mode: GPIO[7] (input/output)
PCM Mode: PCM_SYNC (input/output)• Output if central• Input if peripheral
GPIO[6]

VIO

tristate

input

GPIO Mode: GPIO[6] (input/output)
PCM Mode: PCM_CLK (input/output)• Output if central• Input if peripheral
GPIO[5]

VIO

tristate

input

GPIO Mode: GPIO[5] (input/output)
PCM Mode: PCM_DOUT (output)
This pin is used as a configuration pin: CON[7] (input). See Section 5.6 "Configuration pins".
GPIO[4]

VIO

tristate

input

input

tristateyesnominal PU

yes

yes

GPIO Mode: GPIO[4] (input/output)
PCM Mode: PCM_DIN (input)
GPIO[3]

VIO

tristate

outputoutput high[3]

tristateyes

weak PUyes

yes

output high[3]

tristateyes

weak PUyes

yes

tristateyes

weak PU

yes

yes

yes

no

GPIO Mode: GPIO[3] (input/output)
LED Mode: LED_OUT_BT (output)
GPIO[2]

VIO

tristate

outputGPIO Mode: GPIO[2] (input/output)
LED Mode: LED_OUT_WLAN (output)
GPIO[1]

VIO

tristate

input

input

GPIO Mode: GPIO[1] (input/output).
This pin can also be used for 88W8987 Wi-Fi to host wake-up (out-of-band wake-up signal).
GPIO[0]

VIO

tristate

outputoutput highoutput low yes

nominal PU

GPIO Mode: GPIO[0] (input/output)
Oscillator Enable Mode: XOSC_EN (output) (active high). See Section 5.5.9 "Clock interface".
[1]
[2]
[3]
[4]
[5]

Not all GPIO pins can be used for Host-to-SoC wake-up signals.
Maximum input voltage is 0.4V when VIO has no power (or in uncertain situations).
The signal may toggle while boot code is executing.
When the device is in SDIO-SDIO mode.
When the device is in SDIO-UART mode.

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

5.5.3 Wi-Fi/Bluetooth radio interface
Table 6. Wi-Fi/Bluetooth radio interface - QFN package
Pin Name

Type

SupplyDescription

RF_TR_2

A, I/OAVDD18

Wi-Fi Transmit/Receive (2.4 GHz)

RF_TR_5

A, I/OAVDD18

Wi-Fi Transmit/Receive (5 GHz)

BRF_ANT

A, I/OAVDD18Bluetooth Transmit/Receive

Table 7. Wi-Fi/Bluetooth radio interface - eWLP package option
Pin Name

Type

SupplyDescription

RF_TR_2/BRF_ANT

A, I/OAVDD18

Wi-Fi Transmit/Receive (2.4 GHz)
Bluetooth Transmit/Receive (shared path for Wi-Fi and Bluetooth)

RF_RX_5

A, I

AVDD18

Wi-Fi Receive (5 GHz)

RF_TX_5

A, O

AVDD18

Wi-Fi Transmit (5 GHz)

5.5.4 Wi-Fi RF front-end control interface
Table 8. Wi-Fi RF front-end control interface
Pin Name

SupplyNo Pad
Power
[1]
State

Reset
State

HW State PwrDwn
State

PwrDwnProg

Internal
PU/PD

PU

PD

RF_CNTL0_N

VIO_RF

tristate

outputoutputdrive lowyesnominal PU nonooutputdrive highyes

weak PUnono

RF Control 0—RF Control Output Low (output)
RF_CNTL1_P

VIO_RF

tristate

outputRF Control 1—RF Control Output High (output)
This pin is used as a configuration pin: CON[6] (input). See Section 5.6 "Configuration pins".
RF_CNTL2_N

VIO_RF

tristate

outputoutputdrive low

yes

weak PUnono

outputdrive highyes

weak PUnono

RF Control 2—RF Control Output Low (output)
RF_CNTL3_P

VIO_RF

tristate

outputRF Control 3—RF Control Output High (output)[1]

Maximum input voltage is 0.4V when VIO_RF has no power (or in uncertain situations).

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

5.5.5 SDIO host interface
Table 9. SDIO host interface
Pin Name

SupplyNo Pad
Power
[1]
State

Reset
State

HW
State

PwrDwnState

PwrDwnProg

Internal PU/
PD

PU

PD

SD_CLK

VIO_SD

tristate

input

input

tristatenonominal PU

yes

yes

tristate

input

input

tristatenonominal PU

yes

yes

input

input

tristatenonominal PU

yes

yes

input

input

tristatenonominal PU

yes

yes

SDIO 4-bit Mode: Clock input
SDIO 1-bit Mode: Clock input
SD_CMD

VIO_SDSDIO 4-bit Mode: Command/response (input/output)
SDIO 1-bit Mode: Command line
SD_DAT[3]VIO_SD

tristate

SDIO 4-bit Mode: Data line Bit[3]SDIO 1-bit Mode: Reserved
SD_DAT[2]

VIO_SD

tristate

SDIO 4-bit Mode: Data line Bit[2] or read wait (optional)
SDIO 1-bit Mode: Read wait (optional)
SD_DAT[1]

VIO_SD

tristate

input

input

tristatenonominal PU

yes

yes

input

input

tristatenonominal PU

yes

yes

SDIO 4-bit Mode: Data line Bit[1]SDIO 1-bit Mode: Interrupt
SD_DAT[0]VIO_SD

tristate

SDIO 4-bit Mode: Data line Bit[0]SDIO 1-bit Mode: Data line
[1]

Maximum input voltage is 0.4V when VIO_SD has no power (or in uncertain situations).

5.5.6 UART host interface
Table 10. UART host interface (MFP)
Pins may be Multi-Functional Pins (MFP).
Pin Name

Type

SupplyDescription

UART_SINI

VIO

UART serial input signal - GPIO[9] input/output

UART_SOUTO

VIOUART serial output signal - GPIO[8] input/output

UART_RTSn

O

VIO

UART request-to-send output signal . Active low - GPIO[11] input/
output

UART_CTSnI

VIO

UART clear-to-send input signal - Active low - GPIO[10] input/output

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5.5.7 Audio interface
Table 11. Audio interface pins (MFP)
Pins may be Multi-Functional Pins (MFP).
Pin Name

Type

SupplyDescription

PCM_DIN

I

VIO

Receive PCM input signal. GPIO[4] input/ouput

PCM_DOUTO

VIOTransmit PCM output signal. GPIO[5] input/ouput

PCM_CLK

I/O

VIO

PCM data clock. GPIO[6] input/output• Output if central• Input if peripheral

PCM_SYNC

I/O

VIO

PCM frame sync. GPIO[7] input/ouput• Output if central• Input if peripheral

5.5.8 Configuration interface
Table 12. Configuration interface
Pin Name

SupplyNo Pad
Power
State

Reset
State

HW
State

PwrDwnState

PwrDwnProg

Internal
PU/PD

PU

PD

CONFIG_HOST[0]AVDD18tristate

input

input

tristatenoweak PU

yes

yes

yes

yes

yes

yes

This pin is used as a configuration pin: CONFIG_HOST[0] (input). See Section 5.6 "Configuration pins".
CONFIG_HOST[1]AVDD18tristate

input

input

tristatenoweak PU

This pin is used as a configuration pin: CONFIG_HOST[1] (input). See Section 5.6 "Configuration pins".
CONFIG_AUTO_
REF_DET

AVDD18tristate

input

input

tristatenoweak PU

This pin is used as a configuration pin: CONFIG_AUTO_REF_DET (input). See Section 5.6 "Configuration pins".

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5.5.9 Clock interface
Table 13. Clock interface (MFP)
Pins may be Multi-Functional Pins (MFP).
Pin Name

SupplyNo Pad
Power
[1]
State

Reset
State

HW
State

PwrDwnState

PwrDwnProg

Internal PU/ PU
PDPD

XTAL_IN

AVDD18

--

--

--

--

--

--

--

--

Reference Clock Input
Reference clock signal frequency must be 26 MHz or 38.4 MHz from an external crystal or external crystal oscillator.
Power consumption in sleep mode is lower with an external crystal compared to an external crystal oscillator when an
external sleep clock is not used.
See Section 9.9 "Reference clock specifications".
XTAL_OUT

AVDD18

--

--

--

--

--

--

--

--

yes

yes

Connect this pin to an external crystal when an external crystal is used.
When an external crystal oscillator is used, connect this pin to ground with resistance less than 5 kΩ.
SLP_CLK_IN

VIO

tristate

input

[2]

input

tristatenonominal PU

Sleep Clock Input (optional)
Used for lower power operation in sleep mode.
• An external sleep clock of 32.768 kHz can be used for lowest current consumption in sleep mode.
• An external sleep clock is required if automatic reference clock frequency detection is used. See Section 5.6"Configuration pins".
• If no external sleep clock is used, leave this pin floating (DNC).
XOSC_EN

VIO

--

--

--

--

--

--

--

--

Oscillator Enable (output) (active high)
XOSC_EN signal can be used ONLY when an external sleep clock is used.
Used to enable an external oscillator.
0 = disable external oscillator
1 = enable external oscillator
NOTE: Muxed with GPIO[0].
[1][2]Maximum input voltage is 0.4V when VIO has no power (or in uncertain situations).
Input mode after reset

5.5.10 Power down (PDn) pin
Table 14. Power down (PDn) pin
Pin Name

SupplyNo Pad
Power
State

Reset
State

HW
State

PwrDwnState

PwrDwnProg

Internal PU/
PD

PU

PD

PDn

AVDD18

--

--

--

--

--

--

--

--

Full Power-down (input) (active low)
0 = full power-down mode
1 = normal mode
• PDn can accept an input of 1.8V to 4.5V
• PDn may be driven by the host• PDn must be high for normal operation
No internal pull-up on this pin.
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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

5.5.11 Power supply and ground
Table 15. Power supply and ground
Pin Name

Type

Description

VCORE

Power

1.10V Core Power Supply

VIO

Power

1.8V/3.3V Digital I/O Power Supply

VIO_SDPower

1.8V Digital I/O SDIO Power Supply

VIO_RF

Power

1.8V/3.3V Analog I/O RF Power Supply

AVDD18Power

1.8V Analog Power Supply

VPA

Power

2.2V Analog Power Supply

AVSS

GroundGroundNC

NC

Not Connected

DNC

DNC

Do Not Connect
Do not connect these pins. Leave these pins floating.

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5.6 Configuration pins
Table 16 shows the pins used as configuration inputs to set parameters following a reset.
The definition of these pins changes immediately after reset to their usual function.
To set a configuration bit to 0, attach a 50 kΩ–100 kΩ resistor from the pin to ground. No
external circuitry is required to set a configuration bit to 1.
See Section 9.11 "Configuration pin specifications" for the internal pull-up values of theconfiguration pins.
Table 16. Configuration pins
Configuration Bits

Pin Name

Configuration Function

CON[9]

GPIO[17]

CON[8]

GPIO[11]

Reserved
Set to 1.

CON[7]

GPIO[5]

CON[6]

RF_CNTL1_P

Reserved
Set to 1.

CONFIG_XOSC_SELGPIO[8]/UART_SOUT

Reference clock frequency selectValid when CONFIG_AUTO_REF_DET = 0
0 = 38.4 MHz
1 = 26 MHz (default)

CONFIG_AUTO_REF_
DET

CONFIG_AUTO_REF_
DET

Reference clock frequency detection select0 = reference clock frequency detection by CONFIG_XOSC_SEL
1 = reference clock frequency detection using external sleep clock(default)(valid only when external sleep clock is used)

CON[1]

CONFIG_HOST[1]

CON[0]

CONFIG_HOST[0]Host configuration options
No hardware impact. Software reads and boots accordingly. See
Table 17.

Table 17. Host configuration options
Strap Value

Wi-Fi

Bluetooth/Bluetooth LE

Number of SDIO Functions

00 (reserved)

--

--

--

01 (reserved)

--

--

--

10

SDIO

UART

1 (Wi-Fi)

11

SDIO

SDIO

2 (Wi-Fi, Bluetooth)

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6

Power information
Section 5.5.11 "Power supply and ground" shows the required voltage levels for each railand for PDn input signal.

6.1 Power-up sequence• VIO/VIO_RF must be good (90%) before or at the same time all other power supplies
start ramping up.
• VIO/VIO_RF must be good (90%) before or at the same time PDn starts ramping up.
• VPA must be good (90%) before or at the same time AVDD18 starts ramping up.
• It is recommended to start ramping up AVDD18 ≤1 ms after VPA ramps up.
• AVDD18 must be good (90%) before or at the same time VCORE starts ramping up.
• Ramp-up time of VIO/VIO_RF must be <100 ms.
• Ramp-up time of VPA must be <100 ms.
• Ramp-up time of AVDD18 must be <100 ms.
• Ramp-up time of VCORE must be <5 ms.
• All supplies must be monotonic.
• If using an external crystal oscillator, the reference clock must be stable before PDn
ramps up.
Figure 10 shows the power-up sequence.

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Power_good (90%)

VIO/VIO_RF
VPAPower_good (90%)

2.2V

Power_good (90%) 1.8V

AVDD18

PDn

1.1V

VCORE

Internal POR
XTAL_IN(if external crystal
oscillator is used)
XTAL_IN(if external crystal
is used)Boot ROM execution starts
and firmware download
beginsStrap/Internal
RESETnFigure 10. Power-up sequence

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6.2 Power-down sequence
It is recommended:• To ramp down AVDD18 after VPA ramps down
• To discharge all of the power supplies to less than 0.2V to reduce leakage.
PDn must be asserted when powering down the device.
Figure 11 shows the power-down sequence.

VPA (2.2V)
Less than 0.2V

AVDD18 (1.8V)
Less than 0.2V

Figure 11. Power-down sequence

6.3 Reset
88W8987 is reset to its default operating state under any of the following conditions:• Internal Power-On Reset (POR): POR is triggered when the device receives power and
VCORE and AVDD18 supplies are good. See Section 6.1 "Power-up sequence".
• Software/Firmware reset: the software or firmware issues a reset.
• External PDn pin assertion: the device is reset when the PDn input pin is <0.2V andtransitions from low to high.
See Section 9.10 "Power-down (PDn) pin specifications" for the electrical specifications.

6.3.1 Lowest power state
The device can be put into the lowest power mode of operation to conserve energy when
Wi-Fi and Bluetooth are not in use.
To put the device in the lowest power mode, assert PDn low to enter power-down mode.
Once PDn is de-asserted, the power sequence must be followed. If the firmware is not
downloaded, the device must be kept in power-down mode to reduce leakage.

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7

Absolute maximum ratings
CAUTION: The absolute maximum ratings table defines the limitations for electrical andthermal stresses. These limits prevent permanent damage to the device. Exposure to
conditions at or beyond these ratings is not guaranteed and can damage the device.

Table 18. Absolute maximum ratings
SymbolParameter

Min

Max

Units

VCORE

1.10V core power supply

--

1.21

V

--

2.2

[1]

V

--

4.0

[2]

V

--

2.2

V

--

2.2

[3]

V

--

4.0

[4]

V

VIO

1.8V/3.3V digital I/O power supply

VIO_SD
VIO_RF

1.8V digital I/O SDIO power supply
1.8V/3.3V I/O power supply

AVDD18

1.8V analog power supply

--

1.98

V

VPA

2.2V analog power supply

--

2.3

V

TSTORAGE

Storage Temperature

-55

+125

°C

[1]
[2]
[3]
[4]

When using 1.8V digital I/O power supply
When using 3.3V digital I/O power supply
When using 1.8V I/O power supply
When using 3.3V I/O power supply

Table 19. Limiting values - QFN option
SymbolVESD

Parameter
Electrostatic discharge

Condition
human body model (HBM)

[1]
[2]

charged device model (CDM)
[1]
[2]

Min

Max

Unit

-1.5

+1.5

kV

-500

+500

V

Min

Max

Unit

-1.5

+1.5

kV

-400

+400

V

According to ANSI/ESDA/JEDEC JS-001.
According to ANSI/ESDA/JEDEC JS-002

Table 20. Limiting values - eWLP option
SymbolVESD

Parameter
Electrostatic discharge

Condition
human body model (HBM)

[1]
[2]

charged device model (CDM)[1][2]

According to ANSI/ESDA/JEDEC JS-001.
According to ANSI/ESDA/JEDEC JS-002

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8

Recommended operating conditions
Note: Operation beyond the recommended operating conditions is neither
recommended nor guaranteed.

Table 21. Recommended operating conditions
SymbolParameter

Condition

Min

Typ

Max

Units

VCORE

1.10V core power supply

--

1.05

1.10

1.15

V

VIO

1.8V/3.3V digital I/O power supply

--

1.67

1.8

1.92

V

3.07

3.3

3.53

V

VIO_SD

1.8V digital I/O SDIO power supply

--

1.67

1.8

1.92

V

VIO_RF

1.8V/3.3V I/O power supply

--

1.67

1.8

1.92

V

3.07

3.3

3.53

V

AVDD18

1.8V analog power supply

--

1.71

1.8

1.89

V

VPA

2.2V analog power supply

--

2.09

2.2

2.26

V

TA

Ambient operating temperature

Extended

-30

--

85

°C

Industrial

-40

--

85

°C

--

--

--

125

°C

TJ

Maximum junction temperature

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9

Electrical specifications
9.1 GPIO/LED interface specifications
9.1.1 VIO DC characteristics
9.1.1.1 1.8V operation

Table 22. DC electrical characteristics—1.8V operation (VIO)
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Unit

VIH

Input high voltage--

0.7*VIO--

VIO+0.4

V

VIL

Input low voltage

--

-0.4

--

0.3*VIOV

VHYS

Input hysteresis

--

100

--

--

mV

VOH

Output high voltage--

VIO-0.4

--

--

V

VOL

Output low voltage

--

--

--

0.4

V

9.1.1.2 3.3V operation
Table 23. DC electrical characteristics—3.3V operation (VIO)
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Unit

VIH

Input high voltage--

0.7*VIO--

VIO+0.4

V

VIL

Input low voltage

--

-0.4

--

0.3*VIOV

VHYS

Input hysteresis

--

100

--

--

mV

VOH

Output high voltage--

VIO-0.4

--

--

V

VOL

Output low voltage

--

--

--

0.4

V

9.1.2 LED mode
Table 24. LED mode data
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

IOH

Switching current high

Tristate on pad (requires pull-up on board)

IOL

Switching current low@ 0.4V

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Typ

Unit

Tristate whendriving high

mA

10

mA

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9.2 RF front-end control interface specifications
9.2.1 VIO_RF DC characteristics
9.2.1.1 1.8V operation
Table 25. DC electrical characteristics—1.8V operation (VIO_RF)
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Unit

VIH

Input high voltage--

0.7*VIO_RF--

VIO_RF+0.4

V

VIL

Input low voltage

--

-0.4

--

0.3*VIO_RF

V

VHYS

Input hysteresis

--

100

--

--

mV

VOH

Output high voltage--

VIO_RF-0.4

--

--

V

VOL

Output low voltage

--

--

--

0.4

V

9.2.1.2 3.3V operation
Table 26. DC electrical characteristics—3.3V operation (VIO_RF)
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Unit

VIH

Input high voltage--

0.7*VIO_RF--

VIO_RF+0.4

V

VIL

Input low voltage

--

-0.4

--

0.3*VIO_RF

V

VHYS

Input hysteresis

--

100

--

--

mV

VOH

Output high voltage--

VIO_RF-0.4

--

--

V

VOL

Output low voltage

--

--

--

0.4

V

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9.3 Wi-Fi radio specifications
9.3.1 Wi-Fi radio performance measurement
The Wi-Fi transmit/receive performance is measured either at the antenna port or at thechip port.

88W8987

Wi-Fi 5G Tx/Rx

Filter
Diplexer

Wi-Fi 2.4G Tx/Rx

FilterAntenna
port

Chip port

Figure 12. RF performance measurement points

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9.3.2 2.4 GHz Wi-Fi receiver performance
Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and atchip port.
Table 27. 2.4 GHz Wi-Fi receiver performance
Parameter

Conditions

Min

Typ

Max

Unit

RF frequency range

20 MHz and 40 MHz bandwidths

2400

—

2500

MHz

Rx input IP3 at RF high gain (In-Band)Rx input IP3 when LNA in high gainmode (24 dB) at chip input

—

-20

—

dBm

Maximum Rx input level

Maximum Rx input level without device
damage

—

—

2

dBm

1 Mbit/s

—

-99

—

dBm

2 Mbit/s

—

-95

—

dBm

5.5 Mbit/s

—

-93

—

dBm

11 Mbit/s

—

-90

—

dBm

6 Mbit/s

—

-89

—

dBm

9 Mbit/s

—

-89

—

dBm

12 Mbit/s

—

-88

—

dBm

18 Mbit/s

—

-87

—

dBm

24 Mbit/s

—

-85

—

dBm

36 Mbit/s

—

-81

—

dBm

48 Mbit/s

—

-77

—

dBm

54 Mbit/s

—

-76

[1]

—

dBm

MCS0

—

-89

—

dBm

MCS1

—

-88

—

dBm

MCS2

—

-85

—

dBm

MCS3

—

-83

—

dBm

MCS4

—

-80

—

dBm

MCS5

—

-76

—

dBm

MCS6

—

-74

—

dBm

MCS7

—

-73

—

dBm

MCS0

—

-87

—

dBm

MCS1

—

-86

—

dBm

MCS2

—

-84

—

dBm

MCS3

—

-81

—

dBm

MCS4

—

-77

—

dBm

MCS5

—

-73

—

dBm

MCS6

—

-72

—

dBm

MCS7

—

-71

—

dBm

Receiver sensitivity 802.11b

Receiver sensitivity 802.11g

Receiver sensitivity 802.11n HT20
BCC waveform

Receiver sensitivity 802.11n HT40
BCC waveform

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Table 27. 2.4 GHz Wi-Fi receiver performance...continued
Parameter

Conditions

Min

Typ

Max

Unit

802.11b

—

-1

—

dBm

802.11g

—

-2

—

dBm

802.11n MCS0-4

—

-1

—

dBm

802.11n MCS5-6

—

-2

—

dBm

802.11n MCS7

—

-5

—

dBm

1 Mbit/s

—

54

—

dB

Receiver adjacent channel interference 2 Mbit/s
rejection (ACI) 802.11b
5.5 Mbit/s

—

49

—

dB

—

47

—

dB

11 Mbit/s

—

45

—

dB

6 Mbit/s

—

37

—

dB

9 Mbit/s

—

35

—

dB

12 Mbit/s

—

39

—

dB

Receiver adjacent channel interference 18 Mbit/s
rejection (ACI) 802.11g
24 Mbit/s

—

36

—

dB

—

33

—

dB

36 Mbit/s

—

27

—

dB

48 Mbit/s

—

27

—

dB

54 Mbit/s

—

24

—

dB

MCS0

—

37

—

dB

MCS1

—

36

—

dB

MCS2

—

36

—

dB

Receiver adjacent channel interference MCS3
rejection (ACI) 802.11n, HT20
MCS4

—

30

—

dB

—

28

—

dB

MCS5

—

26

—

dB

MCS6

—

21

—

dB

MCS7

—

20

—

dB

MCS0

—

33

—

dB

MCS1

—

32

—

dB

MCS2

—

29

—

dB

Receiver adjacent channel interference MCS3
rejection (ACI) 802.11n, HT40,
MCS4

—

27

—

dB

—

26

—

dB

MCS5

—

22

—

dB

MCS6

—

19

—

dB

MCS7

—

17

—

dB

Receiver maximum input level[1]

De-sense of ~2 dB at 2472 MHz

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9.3.3 5 GHz Wi-Fi receiver performance
Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at thechip port.
Table 28. 5 GHz Wi-Fi receiver performance
Parameter

Conditions

Min

Typ

Max

Unit

RF frequency range

5 GHz—IEEE 802.11ac/n/a

4900

--

5925

MHz

Rx input IP3 at RF high gain (In-Band)Rx Input IP3 when LNA in high gainmode (24 dB) at chip input

—

-20

—

dBm

Maximum Rx input level

Maximum Rx input level without device
damage

—

—

2

dBm

6 Mbit/s

--

-92

--

dBm

9 Mbit/s

--

-92

--

dBm

12 Mbit/s

--

-91

--

dBm

18 Mbit/s

--

-89

--

dBm

24 Mbit/s

--

-86

--

dBm

36 Mbit/s

--

-83

--

dBm

48 Mbit/s

--

-78

--

dBm

54 Mbit/s

--

-77

--

dBm

MCS0

--

-92

--

dBm

MCS1

--

-90

--

dBm

MCS2

--

-87

--

dBm

MCS3

--

-84

--

dBm

MCS4

--

-81

--

dBm

MCS5

--

-76

--

dBm

MCS6

--

-75

--

dBm

MCS7

--

-73

--

dBm

MCS0

--

-88

--

dBm

MCS1

--

-87

--

dBm

MCS2

--

-84

--

dBm

Receiver sensitivity 802.11n HT40 BCC MCS3
waveform
MCS4

--

-81

--

dBm

--

-78

--

dBm

MCS5

--

-74

--

dBm

MCS6

--

-73

--

dBm

MCS7

--

-71

--

dBm

Receiver sensitivity 802.11a

Receiver sensitivity 802.11n HT20
BCC waveform

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Table 28. 5 GHz Wi-Fi receiver performance...continued
Parameter

Receiver sensitivity 802.11ac VHT20
BCC waveform

Receiver sensitivity 802.11ac VHT40
BCC waveform

Receiver sensitivity 802.11ac VHT80
BCC waveform

Receiver maximum input level

88W8987_SDS

Product short data sheet

Conditions

Min

Typ

Max

Unit

MCS0

--

-92

--

dBm

MCS1

--

-90

--

dBm

MCS2

--

-88

--

dBm

MCS3

--

-85

--

dBm

MCS4

--

-83

--

dBm

MCS5

--

-80

--

dBm

MCS6

--

-78

--

dBm

MCS7

--

-76

--

dBm

MCS8

--

-72

--

dBm

MCS0

--

-88

--

dBm

MCS1

--

-87

--

dBm

MCS2

--

-85

--

dBm

MCS3

--

-82

--

dBm

MCS4

--

-80

--

dBm

MCS5

--

-76

--

dBm

MCS6

--

-75

--

dBm

MCS7

--

-74

--

dBm

MCS8

--

-70

--

dBm

MCS9

--

-68

--

dBm

MCS0

--

-84

--

dBm

MCS1

--

-84

--

dBm

MCS2

--

-82

--

dBm

MCS3

--

-79

--

dBm

MCS4

--

-78

--

dBm

MCS5

--

-73

--

dBm

MCS6

--

-72

--

dBm

MCS7

--

-71

--

dBm

MCS8

--

-66

--

dBm

MCS9

--

-64

--

dBm

802.11a 6-36 Mbit/s

--

-3

--

dBm

802.11a 48-54 Mbit/s

--

-5

--

dBm

802.11n MCS0-4

--

-3

--

dBm

802.11n MCS5

--

-4

--

dBm

802.11n MCS6

--

-5

--

dBm

802.11n MCS7-9

--

-8

--

dBm

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Table 28. 5 GHz Wi-Fi receiver performance...continued
Parameter

Conditions

Min

Typ

Max

Unit

6 Mbit/s

--

34

--

dB

9 Mbit/s

--

32

--

dB

12 Mbit/s

--

33

--

dB

Receiver adjacent channel interference 18 Mbit/s
rejection (ACI) 802.11a
24 Mbit/s

--

32

--

dB

--

29

--

dB

36 Mbit/s

--

24

--

dB

48 Mbit/s

--

24

--

dB

54 Mbit/s

--

17

--

dB

MCS0

--

32

--

dB

MCS1

--

31

--

dB

MCS2

--

31

--

dB

Receiver adjacent channel interference MCS3
rejection (ACI) 802.11n, HT20
MCS4

--

26

--

dB

--

22

--

dB

MCS5

--

20

--

dB

MCS6

--

17

--

dB

MCS7

--

15

--

dB

MCS0

--

29

--

dB

MCS1

--

28

--

dB

MCS2

--

28

--

dB

Receiver adjacent channel interference MCS3
rejection (ACI) 802.11n, HT40
MCS4

--

22

--

dB

--

23

--

dB

MCS5

--

19

--

dB

MCS6

--

18

--

dB

MCS7

--

16

--

dB

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

9.3.4 2.4 GHz Wi-Fi transmitter performance
Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at thechip port.
Table 29. 2.4 GHz Wi-Fi transmitter performance
Parameter

Conditions

Min

Typ

Max

Unit

RF frequency range

2.4 GHz—IEEE 802.11n/g/b

2400

—

2500

MHz

2.4 GHz—IEEE 802.11ac, bandwidth
20 MHz and bandwidth 40 MHz
Transmitter output saturation

Saturation power at chip output

—

27

—

dBm

Transmit carrier suppression (CW)

Carrier suppression at chip output

—

-36

—

dB

Transmit I/Q suppression with IQ
calibration

I/Q suppression at chip output

—

-45

—

dBc

802.11b

—

22

—

dBm

OFDM BPSK

—

21

—

dBm

OFDM QPSK

—

21

—

dBm

OFDM 16-QAM

—

21

—

dBm

OFDM 64-QAM

—

21

—

dBm

OFDM BPSK

—

20

—

dBm

OFDM QPSK

—

20

—

dBm

OFDM 16-QAM

—

20

—

dBm

OFDM 64-QAM

—

20

—

dBm

Transmit output power level control
range

—

—

22

[1]

—

dB

Transmit output power control step

—

—

1

[2]

—

dB

Transmit output power accuracy

—

—

±1.5

—

dB

Transmit carrier suppression

802.11n HT40 MCS7 at 18 dBm

—

49

—

dB

Transmit power (EVM and mask
compliant) 20 MHz

Transmit power (EVM and mask
compliant) 40 MHz

[1]
[2]

0-22 dBm
Hardware capability = 0.5 dB, software capability = 1 dB

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

9.3.5 5 GHz Wi-Fi transmitter performance
Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at thechip port.
Table 30. 5 GHz Wi-Fi transmitter performance
Parameter

Conditions

Min

Typ

Max

Unit

RF frequency range

5 GHz—IEEE 802.11ac/n/a

4900

—

5925

MHz

Transmit output saturation

Saturation power at chip output

—

27

—

dBm

Transmit carrier suppression (CW)

Carrier suppression at chip output

—

-36

—

dB

Transmit I/Q suppression with IQ
calibration

I/Q suppression at chip output

—

-45

—

dBc

OFDM BPSK

—

21

—

dBm

OFDM QPSK

—

21

—

dBm

OFDM 16-QAM

—

21

—

dBm

OFDM 64-QAM (MCS7)

—

21

—

dBm

OFDM 256-QAM (MCS8)

—

20

—

dBm

OFDM BPSK

—

20

—

dBm

OFDM QPSK

—

20

—

dBm

OFDM 16-QAM

—

20

—

dBm

OFDM 64-QAM (MCS7)

—

20

—

dBm

OFDM 256-QAM (MCS9)

—

18

—

dBm

OFDM BPSK

—

17

—

dBm

OFDM QPSK

—

17

—

dBm

OFDM 16-QAM

—

17

—

dBm

OFDM 64-QAM (MCS7)

—

17

—

dBm

OFDM 256-QAM (MCS9)

—

15

—

dBm

Transmit output power level control
range

—

21

[1]

—

dB

Transmit output power control step

—

1

[2]

—

dB

Transmit output power accuracy

—

±1.5

—

dB

—

51

—

dBc

Transmit power (EVM and mask
compliant) 20 MHz

Transmit power (EVM and mask
compliant) 40 MHz

Transmit power (EVM and mask
compliant) 80 MHz

Transmit carrier suppression[1][2]

802.11ac MCS9 VHT80, at 15 dBm

0-21 dBm
Hardware capability = 0.5 dB, software capability = 1 dB

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

9.3.6 Local oscillator
Table 31. Local oscillator
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"Parameter

Condition

Min

Typ

Max

Units

Phase noise

Measured at 2.438 GHz at 100 kHz
offset—-103—

dBc/HzPhase noise

Measured at 5.501 GHz at 100 kHz
offset—-100—

dBc/HzIntegrated RMS phase noise at RF
output (from 1 kHz–10 MHz)

Reference clock frequency = 38.4 MHz(2.4 GHz)

—

0.3

—

degrees

Integrated RMS phase noise at RF
output (from 10 kHz–10 MHz)

Reference clock frequency = 38.4 MHz(5 GHz)—0.5—

degreesFrequency resolution

—

0.02

—

—

kHz

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

9.4 Bluetooth radio specifications
The Bluetooth radio interface pin is powered by AVDD18 voltage supply.

9.4.1 Bluetooth and Bluetooth LE receiver performance
Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at
BRF_ANT pin.
Table 32. Bluetooth and Bluetooth LE receiver performance
Parameter

Conditions

Min

Typ

Max

Unit

RF frequency range

—

2.4

—

2.5

GHz

IF frequency

—

—

2

—

MHz

Input IP3 (@ maximum gain of 72 dB)

—

—

-19

—

dBm

In-band blocking

GFSK
C/I (Co-channel)

—

10

—

dB

C/I (1 MHz)

—

-4

—

dB

C/I (2 MHz)

—

-45

—

dB

C/I (3 MHz)

—

-49

—

dB

C/I (Image)

—

-21

—

dB

C/I (Image ±1 MHz)

—

-32

—

dB

Pi/4-DQPSKC/I (Co-channel)

—

10

—

dB

C/I (1 MHz)

—

-9

—

dB

C/I (2 MHz)

—

-47

—

dB

C/I (3 MHz)

—

-51

—

dB

C/I (Image)

—

-19

—

dB

C/I (Image ±1 MHz)

—

-35

—

dB

8-DPSKC/I (Co-channel)

—

16

—

dB

C/I (1 MHz)

—

-6

—

dB

C/I (2 MHz)

—

-42

—

dB

C/I (3 MHz)

—

-48

—

dB

C/I (Image)

—

-12

—

dB

C/I (Image ±1 MHz)

—

-33

—

dB

30–2000 MHz

—

-12.5

—

dBm

2–2.399 GHz

—

-12.4

—

dBm

2.484–3 GHz

—

-18

—

dBm

3–12.75 GHz

—

-2.6

—

dBm

RSSI range

Resolution = 1 dB

—

-90

0

dBm

50 Ω return loss

—

—

—

-10

dB

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 32. Bluetooth and Bluetooth LE receiver performance...continued
Parameter
Bluetooth sensitivity (RCV/CA/01/C &RCV/CA/02/C & RCV/CA/07/C)
Bluetooth LE sensitivity(RCV-LE/CA/02/C)
[1]
[2]
[3]
[4]

Conditions
DH5
2DH5

Min

Typ

Max

Unit

—

-96

[1]

—

dBm

-95

[2]

—

dBm

-88

[3]

—

dBm

-99

[4]

—

dBm

-96

[4]

—

dBm

—

3DH5

—

Bluetooth LE 1 Mbit/s
Bluetooth LE 2 Mbit/s——

Desense of ~9.5 dB at CH 2419 MHz, ~6 dB at 2457 MHz, ~9 dB at 2458 MHz due to internal clock harmonics
Desense of ~8.5 dB at CH 2419 MHz, ~3 dB at CH 2432 MHz, ~5 dB at 2457 MHz, ~7.5 dB at 2458 MHz due to internal clock harmonics
Desense of ~9 dB at CH 2419 MHz, ~3.5dB at CH 2432 MHz,~4.5 dB at 2457 MHz, ~7.5 dB at 2458 MHz due to internal clock harmonics
Desense of ~7 dB at CH 2432 MHz and ~9 dB at 2458MHz due to internal clock harmonics

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9.4.2 Bluetooth and Bluetooth LE transmitter performance
Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at
BRF_ANT pin.
Table 33. Bluetooth and Bluetooth LE transmitter
Parameter

Conditions

Min

Typ

Max

Unit

RF frequency range

—

2.4

—

2.5

GHz

Gain range

Class 1 without external PA

—

30

—

dB

Gain resolution

—

—

0.5

—

dB

Spurious emission (BDR) (in-band)±500 kHz

—

—

-20

dBc

±2 MHz

—

-33

-20

dBm

±3 MHz

—

-45

-40

dBm

±1 MHz

—

—

-26

dBc

±1.5 MHz

—

—

-20

dBm

±2.5 MHz

—

—

-40

dBm

30–88 MHz—-65

-41.25dBm

88–960 MHz—-65-41.250.96–20 GHz
All frequencies in this range < -41.25 dBm,
except at 2x Bluetooth channel frequency.
Measured at pin without external filter.

—

-35

-25

Restricted—2.38–2.39 GHz—-55-41.25

Restricted—2.4835–2.6 GHz—-50-41.25

GSM850 (869–894 MHz)

—

-140

—

GSM900 (925–960 MHz)

—

-140

—

GSM DCS (1805–1880 MHz)

—

-135

—

GSM PCS (1930–1990 MHz)

—

-135

—

GPS (1575.42 ±1.023 MHz)

—

-140

—

WCDMA Band I (2110–2170 MHz)

—

-130

—

WCDMA Band V (869–894 MHz)

—

-140

—

Transmit output power(TRM/CA/01/C)

BDR

—

13

—

dBm

EDR

—

10

—

dBm

Transmit output power accuracy

—

—

±1.5

—

dB

—

5

—

dB

Freq Low—

2400.9—MHz

Freq High

—

2481

—

MHz

-20dB BW (TRM/CA/05/C)

DH5

—

955

—

kHz

Modulation characteristics(TRM/CA/07/C)

Delta F1 avg

—

164

—

kHz

Delta F2 max Threshold

—

100

—

%

Spurious emission (EDR) (in-band)

Spurious emission (out-of-band)

Out-of-band/
Cellular band noise

Power control (TRM/CA/03/C)
Frequency range (TRM/CA/04/C)

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 33. Bluetooth and Bluetooth LE transmitter...continued
Parameter

Conditions

Min

Typ

Max

Unit

Modulation characteristics(TRM/CA/07/C)

Delta F2/Delta F1

—

0.9

—

—

Delta F2 avg

—

148

—

kHz

ICFT (TRM/CA/08/C)

DH1

—

19

—

kHz

Max Drift - DH1

—

-7

—

kHz

Drift Rate - DH1

—

-0.9

—

kHz

Max Drift - DH3

—

-7

—

kHz

Drift Rate - DH3

—

-1

—

kHz

Max Drift - DH5

—

-7

—

kHz

Drift Rate - DH5

—

-1.3

—

kHz

2DH5 (DPSK/GFSK)

—

-0.1

—

dB

3DH5 (DPSK/GFSK)

—

-0.1

—

dB

2DH5 Peak DEVM

—

0.07

—

—

2DH5 RMS DEVM
EDR carrier frequency stability andmodulation accuracy (TRM/CA/11/C) 3DH5 Peak DEVM

—

0.03

—

—

—

0.08

—

—

3DH5 RMS DEVM

—

0.03

—

—

2DH5

—

100

—

%

3DH5

—

100

—

%

Bluetooth LE 1 Mbit/s

—

10

—

dBm

Bluetooth LE 2 Mbit/s

—

10

—

dBm

Delta F1 avg - Bluetooth LE 1 Mbit/s

—

247

—

kHz

Delta F2/Delta F1- Bluetooth LE 1 Mbit/s

—

0.9

—

kHz

Delta F2 avg - Bluetooth LE 1 Mbit/s

—

223

—

kHz

Delta F1 avg - Bluetooth LE 2 Mbit/s

—

504

—

kHz

Delta F2/Delta F1- 2 Mbit/s

—

1

—

kHz

Delta F2 avg- Bluetooth LE 2 Mbit/s

—

474

—

kHz

Max Drift - Bluetooth LE 1 Mbit/s

—

0.5

—

kHz

Drift Rate - Bluetooth LE 1 Mbit/s

—

1.5

—

kHz

Max Drift - Bluetooth LE 2 Mbit/s

—

-1.5

—

kHz

Drift Rate - Bluetooth LE 2 Mbit/s

—

1

—

kHz

Bluetooth LE 1 Mbit/s

—

-9

—

kHz

Bluetooth LE 2 Mbit/s

—

-10

—

kHz

Carrier frequency drift(TRM/CA/09/C)

EDR relative power (TRM/CA/10/C)

Diff. phase encoding (TRM/CA/12/C)
Bluetooth LE output power(TRM/-Bluetooth LE/CA/01/C)

Bluetooth LE modulation
characteristics(TRM-Bluetooth LE/CA/05/C)

Bluetooth LE carrier frequency drift(TRM-Bluetooth LE/CA/06/C)

Frequency accuracy(TRM-LE/CA/BV-06-C)

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

9.5 Current consumption
Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, acrossfrequency and typical value with SDIO 2.0 SDR25 50 MHz clock (4-bit mode). Data iscollected with SDIO-SDIO interface configuration. The transmit power level in transmit
mode refers to the chip port (Section 9.3.1).
Table 34. Current consumption
Mode

VIO_3.3 V

2.2 V

1.8 V

1.1 V

Unit

Power down

0.11

0

0.04

2.8

mA

Wi-Fi and Bluetooth in deep-sleep mode

0.08

0

0.02

1.22

mA

Wi-Fi only in deep-sleep mode

0.08

0

0.024

1.14

mA

Bluetooth only in deep-sleep mode

0.08

0

0.025

1.04

mA

0.08

0

0.02

1.01

mA

Bluetooth LE advertise (interval = 1.28 s)

0.08

0

0.05

1.1

mA

Bluetooth LE scan (interval = 1.28 s, window = 11.25 ms)

0.08

0

0.15

1.2

mA

Bluetooth LE link (central mode, interval=1.28 s)

0.08

0

0.07

1.2

mA

Bluetooth LE peak transmit (at 0 dBm), 1 Mbit/s

0.44

0

25

21

mA

Bluetooth LE peak transmit (at 5 dBm), 1 Mbit/s

0.44

0

37

23

mA

Bluetooth LE peak transmit (at 10 dBm), 1 Mbit/s

0.44

0

53

22

mA

Bluetooth LE peak receive, 1 Mbit/s

0.44

0

17

21

mA

Bluetooth page scan

0.08

0

0.18

1.2

mA

Bluetooth page and inquiry scan

0.08

0

0.32

1.33

mA

Bluetooth ACL link, central sniff mode, (interval = 1.28s)

0.08

0

0.09

1.3

mA

Bluetooth ACL link, central sniff mode, (interval = 500 ms)

0.08

0

0.18

1.7

mA

Bluetooth ACL (data pump) DH1

0.44

0

11.7

18

mA

Bluetooth ACL (data pump) 2-DH3

0.44

0

17.2

19.5

mA

Bluetooth ACL (data pump) 3-DH5

0.44

0

19.3

20

mA

Bluetooth SCO HV3 peak transmit (at 0 dBm)

0.44

0

25

21

mA

Bluetooth SCO HV3 peak transmit (at 5 dBm)

0.44

0

37

23

mA

Bluetooth SCO HV3 peak transmit (at 10 dBm)

0.44

0

53

22

mA

Bluetooth SCO HV3 peak transmit (at 13 dBm)

0.44

0

67

22

mA

Bluetooth SCO HV3 Peak Receive

0.44

0

17

21

mA

Bluetooth peak transmit (at 0 dBm), DH5

0.44

0

25

21

mA

Bluetooth peak transmit (at 5 dBm), DH5

0.44

0

37

23

mA

Bluetooth peak transmit (at 10 dBm), DH5

0.44

0

53

22

mA

Bluetooth peak transmit (at 13 dBm), DH5

0.44

0

67

22

mA

Sleep mode current consumption

Bluetooth LE only in deep-sleep mode[1]

Bluetooth LE current consumption[1]

Bluetooth current consumption

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 34. Current consumption...continued
Mode

VIO_3.3 V

2.2 V

1.8 V

1.1 V

Unit

0.44

0

17

21

mA

IEEE-PS_2GHz-Legacy (DTIM-1)

0.08

0

1

3.18

mA

IEEE-PS_2GHz-Legacy (DTIM-3)

0.08

0

0.35

1.88

mA

IEEE-PS_2GHz-Legacy (DTIM-5)

0.08

0

0.2

1.7

mA

IEEE-PS_2GHz-Legacy (DTIM-10)

0.08

0

0.14

1.27

mA

IEEE-PS_5GHz-Legacy (DTIM-1)

0.08

0

0.7

2.33

mA

IEEE-PS_5GHz-Legacy (DTIM-3)

0.08

0

0.25

1.6

mA

IEEE-PS_5GHz-Legacy (DTIM-5)

0.08

0

0.15

1.43

mA

0.08

0

0.12

1.32

mA

802.11b, 11 Mbit/s

0.41

0

44

87

mA

802.11g, 54 Mbit/s

0.41

0

44

87

mA

0.41

0

44

87

mA

802.11b, 11 Mbit/s

0.41

0

40

95

mA

802.11g, 54 Mbit/s

0.41

0

38

112

mA

0.41

0

38

118

mA

802.11a, 54 Mbit/s

0.41

0

62

95

mA

802.11n, HT20 MCS7

0.41

0

64

95

mA

802.11n, HT40 MCS7

0.41

0

76

100

mA

802.11ac, VHT20 MCS8

0.41

0

64

95

mA

802.11ac, VHT40 MCS9

0.41

0

76

100

mA

0..41

0

82

108

mA

802.11a, 54 Mbit/s

0.41

0

54

118

mA

802.11n, HT20 MCS7

0.41

0

55

120

mA

802.11n, HT40 MCS7

0.41

0

65

140

mA

802.11ac, VHT20 MCS8

0.41

0

55

120

mA

802.11ac, VHT40 MCS9

0.41

0

65

140

mA

802.11ac, VHT80 MCS9

0..41

0

70

158

mA

Bluetooth peak receive, DH5[2]IEEE power save mode

IEEE-PS_5GHz-Legacy (DTIM-10)
2.4 GHz Wi-Fi receive idle mode[3]

802.11n, HT20 MCS7
[3]

2.4 GHz Wi-Fi receive mode

802.11n, HT20 MCS7
5 GHz Wi-Fi 5 receive idle mode

802.11ac, VHT80 MCS9

[3]

[3]

5 GHz Wi-Fi 5 receive mode

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 34. Current consumption...continued
Mode

VIO_3.3 V

2.2 V

1.8 V

1.1 V

Unit

802.11b, 11 Mbit/s at 20 dBm

0.41

400

80

221

mA

802.11g, 54 Mbit/s at 20 dBm

0.41

377

79

220

mA

802.11n, HT20 MCS0 at 20 dBm

0.41

382

80

238

mA

802.11n, HT20 MCS7 at 20 dBm

0.41

382

80

238

mA

802.11a, 6 Mbit/s at 19 dBm

0.41

285

141

215

mA

802.11a, 54 Mbit/s at 19 dBm

0.41

285

141

220

mA

802.11n, HT20 MCS0 at 19 dBm

0.41

290

145

238

mA

802.11n, HT20 MCS7 at 19 dBm

0.41

290

145

238

mA

802.11n, HT40 MCS0 at 17 dBm

0.41

230

138

239

mA

802.11n, HT40 MCS7 at 17 dBm

0.41

230

138

239

mA

802.11ac, VHT20 MCS0 at 19 dBm

0.41

290

144

235

mA

802.11ac, VHT20 MCS8 at 19 dBm

0.41

290

144

235

mA

802.11ac, VHT40 MCS0 at 17 dBm

0.41

230

138

238

mA

802.11ac, VHT40 MCS9 at 17 dBm

0.41

230

138

238

mA

802.11ac, VHT80 MCS0 at 15 dBm

0.41

190

132

232

mA

802.11ac, VHT80 MCS9 at 15 dBm

0.41

190

132

232

mA

0.41

1040

223

231

mA

[3]

2.4 GHz Wi-Fi transmit mode

5 GHz Wi-Fi transmit mode

[3]

Peak current consumption during device initialization[4]

Maximum peak current consumption during device initialization
[1]
[2]
[3]
[4]

Wi-Fi core in sleep mode
Beacon interval = 100 ms. Bluetooth not enabled
Bluetooth in deep-sleep mode
Ambient temperature 85°C

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9.6 SDIO host interface specifications
The SDIO host interface pins are powered by VIO_SD voltage supply.
The SDIO electrical specifications are identical for the 4-bit SDIO and 1-bit SDIO modes.

9.6.1 VIO_SD DC characteristics
9.6.1.1 1.8V operation
Table 35. DC electrical characteristics—1.8V operation (VIO_SD)
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Unit

VIH

Input high voltage--

0.7*VIO_SD--

VIO_SD+0.4

V

VIL

Input low voltage

--

-0.4

--

0.3*VIO_SD

V

VHYS

Input hysteresis

--

100

--

--

mV

VOH

Output high voltage--

VIO_SD-0.4

--

--

V

VOL

Output low voltage

--

--

--

0.4

V

9.6.2 Default speed, high-speed modes
fPP
TWL

TWH

Clock
TISU

TIH

Input
TODLY
Outputaaa-036116

Figure 13. SDIO protocol timing diagram—Default speed mode

fPP
TWL

TWH

Clock
TISU

TIH

Input
TODLY

TOH

Outputaaa-036119

Figure 14. SDIO protocol timing diagram—High-speed mode

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Table 36. SDIO timing data—Default Speed, High-Speed Modes
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Unit

fPP

Clock frequency

Normal

0

--

25

MHz

High-speed

0

--

50

MHz

Normal

10

--

--

ns

High-speed

7

--

--

ns

Normal

10

--

--

ns

High-speed

7

--

--

ns

Normal

5

--

--

ns

High-speed

6

--

--

ns

Normal

5

--

--

ns

High-speed

2

--

--

ns

Output delay time

Normal

--

--

14

ns

CL ≤ 40 pF (1 card)

High-speed

--

--

14

ns

Output hold timeHigh-speed

2.5

--

--

ns

TWL
TWH
TISU
TIH
TODLY
TOH

Clock low time
Clock high time
Input setup time
Input hold time

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9.6.3 SDR12, SDR25, SDR50 modes (up to 100 MHz) (1.8V)
TCLK
fPP
Clock
TCR

TCF

TIS

TIH

Input
TODLY

TOH

Outputaaa-036120

Figure 15. SDIO protocol timing diagram—SDR12, SDR25, SDR50 Modes (up to 100 MHz) (1.8V)

Table 37. SDIO timing data——SDR12, SDR25, SDR50 Modes (up to 100 MHz) (1.8V)
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Units

fPP

Clock frequency

SDR12/25/50

25

--

100

MHz

TIS

Input setup time

SDR12/25/50

3

--

--

ns

TIH

Input hold time

SDR12/25/50

0.8

--

--

ns

TCLK

Clock time

SDR12/25/50

10

--

40

ns

TCR, TCF

Rise time, fall time
TCR, TCF < 2 ns (max) at
100 MHz
CCARD = 10 pF

SDR12/25/50----

0.2*TCLK

ns

TODLY

Output delay time
CL ≤ 30 pF

SDR12/25/50

--

--

7.5

ns

TOH

Output hold time
CL = 15 pF

SDR12/25/50

1.5

--

--

ns

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9.6.4 SDR104 mode (208 MHz) (1.8V)
TCLK
fPP
Clock
TCR

TCF

TIS

TIH

Input
TOP

TODW

Outputaaa-036121

Figure 16. SDIO protocol timing diagram—SDR104 mode (208 MHz)

Table 38. SDIO timing data—SDR104 mode (208 MHz)
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Unit

fPP

Clock frequency

SDR104

0

--

208

MHz

TIS

Input setup time

SDR104

1.4

--

--

ns

TIH

Input hold time

SDR104

0.8

--

--

ns

TCLK

Clock time

SDR104

4.8

--

--

ns

TCR, TCF

Rise time, fall time
SDR104
TCR, TCF < 0.96 ns (max) at
208 MHz
CCARD = 10 pF----

0.2*TCLK

ns

TOP

Card output phase

SDR104

0

--

10

ns

TODW

Output timing of variabledata window

SDR104

2.88

--

--

ns

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9.6.5 DDR50 mode (50 MHz) (1.8V)
TCLK

Clock
TCR

TCF

TIS

TIH

CMD Input
TODLY

TOHLD

CMD Output
aaa-036117

Figure 17. SDIO CMD timing diagram—DDR50 mode (50 MHz)

TCLK
Clock
TIH2x

TIH2x

TIS2x

TIS2x

DAT[3:0]Input
TODLY2x(max)
TODLY2x(max)DAT[3:0]
OutputTODLY2x(min)TODLY2x(min)aaa-036118

Figure 18. SDIO DAT[3:0] timing diagram—DDR50 mode
[1]

[1]

(50 MHz)In DDR50 mode, DAT[3:0] lines are sampled on both edges of the clock (not applicable for CMD line).

Table 39. SDIO timing data—DDR50 mode (50 MHz)
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Units

TCLK

Clock time
50 MHz (max) between
rising edges

DDR50

20

--

--

ns

TCR, TCF

Rise time, fall time
DDR50
TCR, TCF < 4.00 ns (max) at
50 MHzCCARD = 10 pF----

0.2*TCLKns

Clock Duty

--

45

--

55

%

6

--

--

ns

Clock

DDR50

CMD Input (referenced to clock rising edge)
TIS

Input setup time
CCARD ≤ 10 pF (1 card)

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Table 39. SDIO timing data—DDR50 mode (50 MHz)...continued
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Units

TIH

Input hold time
CCARD ≤ 10 pF (1 card)

DDR50

0.8

--

--

ns

CMD Output (referenced to clock rising edge)
TODLY

Output delay time during
data transfer modeCL ≤ 30 pF (1 card)

DDR50

--

--

13.7

ns

TOHLD

Output hold time
CL ≥ 15 pF (1 card)

DDR50

1.5

--

--

ns

DAT[3:0] Input (referenced to clock rising and falling edges)
TIS2x

Input setup time
CCARD ≤ 10 pF (1 card)

DDR50

3

--

--

ns

TIH2x

Input hold time
CCARD ≤ 10 pF (1 card)

DDR50

0.8

--

--

ns

DAT[3:0] Output (referenced to clock rising and falling edges)
TODLY2x (max)

Output delay time during
data transfer modeCL ≤ 25 pF (1 card)

DDR50

--

--

7.0

ns

TODLY2x (min)Output hold time
CL ≥ 15 pF (1 card)

DDR50

1.5

--

--

ns

9.6.6 SDIO internal pull-up/pull-down specifications
Table 40. SDIO internal pull-up/pull-down specifications
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"Parameter

Condition

Min

Typ

Max

Unit

Internal nominal pull-up/pull-downresistance

--

60

90

120

kΩ

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9.7 High-speed UART specifications
The UART Tx and Rx pins are powered by VIO voltage supply.
See Section 9.1.1 "VIO DC characteristics" for DC specifications.
TBAUD
UART Tx
UART Rx
aaa-036128

Figure 19. UART timing diagram[1]

Table 41. UART timing data
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Unit

TBAUD

Baud rate

38.4 MHz input clock

250

--

--

ns

[1]

The acceptable deviation from the UART Rx target baud rate is ±3%.

9.8 Audio interface specifications
9.8.1 PCM interface specifications
The PCM pins are powered by VIO voltage supply. See Section 9.1.1 "VIO DC
characteristics" for specifications.

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Central Mode
1/FBCLKTBCLK fall

PCM_CLKTBCLK rise

TDO
PCM_DOUT

TDISU

TDIHO

PCM_DIN

Figure 20. PCM timing specification diagram for data signals—Central mode

TBCLK
PCM_CLK
TBF

TBF

PCM_SYNC

Figure 21. PCM timing specification diagram for PCM_SYNC signal—Central mode

Table 42. PCM timing specification data—Central mode
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Unit

FBCLK

Bit clock frequency--

2

2/2.048

2.048

MHz

Duty CycleBCLK

Bit clock duty cycle

--

0.4

0.5

0.6

--

TBCLK rise/fall

PCM_CLK rise/fall time

--

--

3

--

ns

TDO

Delay from PCM_CLK rising edge to
PCM_DOUT rising edge

--

--

--

15

ns

TDISU

Setup time for PCM_DIN before
PCM_CLK falling edge

--

20

--

--

ns

TDIHO

Hold time for PCM_DIN after PCM_CLK -falling edge

15

--

--

ns

TBF

Delay from PCM_CLK rising edge to
PCM_SYNC rising edge

--

--

15

ns

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Peripheral mode
1/FBCLKTBCLK fall

PCM_CLKTBCLK rise

TDO
PCM_DOUT
TDIHO

TDISU
PCM_DIN

Figure 22. PCM timing specification diagram for data signals—Peripheral mode

TBCLK
PCM_CLK
TBFSU

TBFHO

TBF

PCM_SYNC

Figure 23. PCM timing specification diagram for PCM_SYNC signal—Peripheral mode

Table 43. PCM timing specification data—Peripheral mode
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Unit

FBCLK

Bit clock frequency

--

0.512

2/2.048

4

MHz

Duty CycleBCLK

Bit clock duty cycle

--

0.4

0.5

0.6

--

TBCLK rise/fall

PCM_CLK rise/fall time

--

--

3

--

ns

TDO

Delay from PCM_CLK rising edge to
PCM_DOUT rising edge

--

--

--

30

ns

TDISU

Setup time for PCM_DIN before
PCM_CLK falling edge

--

15

--

--

ns

TDIHO

Hold time for PCM_DIN after PCM_CLK -falling edge

10

--

--

ns

TBFSU

Setup time for PCM_SYNC before
PCM_CLK falling edge

--

15

--

--

ns

TBFHO

Hold time for PCM_SYNC after
PCM_CLK falling edge

--

10

--

--

ns

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9.9 Reference clock specifications
9.9.1 External crystal oscillator specifications
The reference clock from the external crystal oscillator requires a CMOS input signal.
Note: All new designs should use the 38.4 MHz reference clock. For existing designs
the 26 MHz reference clock can still be used.
Table 44. Clock DC specifications[1]

Parameter

Condition

Min

Typ

Max

Unit

Single-ended high-level voltage

--

--

--

1.8

V

Single-ended low-level voltage

--

0

--

--

V

Clock amplitude (pk-pk)

--

0.5

--

1

V

Mid-point slope

--

125

--

--

MV/s

[1]

The AC-coupling capacitor is integrated into the SoC.

Table 45. 26 MHz clock timing
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"Parameter

Condition

Min

Typ

Max

Unit

XO26 period--

38.46 20 ppm

38.46

38.46 +
20 ppmns

XO26 rise time

--

--

--

5.00

ns

XO26 fall time

--

--

--

5.00

ns

XO26 duty cycle

--

48.05

50

51.95

%

Table 46. 38.4 MHz clock timing
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"Parameter

Condition

Min

Typ

Max

Unit

XO38_4 period--

26.04 20 ppm

26.04

26.04 +
20 ppmns

XO38_4 rise time

--

--

--

2.50

ns

XO38_4 fall time

--

--

--

2.50

ns

XO38_4 duty cycle

--

47.12

50

52.88

%

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Table 47. Phase Noise—2.4 GHz operation
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"Parameter

Test Conditions

Min

Typ

Max

Unit

Fref = 26 MHz

Offset = 1 kHz

--

--

-126

dBc/HzOffset = 10 kHz

--

--

-137

dBc/HzOffset = 100 kHz

--

--

-145

dBc/HzOffset > 1 MHz

--

--

-145

dBc/HzOffset = 1 kHz

--

--

-123

dBc/HzOffset = 10 kHz

--

--

-134

dBc/HzOffset = 100 kHz

--

--

-142

dBc/HzOffset > 1 MHz

--

--

-142

dBc/HzFref = 38.4 MHz

Table 48. Phase Noise—5 GHz operation
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"Parameter

Test Conditions

Min

Typ

Max

Unit

Fref = 26 MHz

Offset = 1 kHz

--

--

-130

dBc/HzOffset = 10 kHz

--

--

-150

dBc/HzOffset = 100 kHz

--

--

-156

dBc/HzOffset > 1 MHz

--

--

-156

dBc/HzOffset = 1 kHz

--

--

-126

dBc/HzOffset = 10 kHz

--

--

-146

dBc/HzOffset = 100 kHz

--

--

-154

dBc/HzOffset > 1 MHz

--

--

-154

dBc/HzFref = 38.4 MHz

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9.9.2 External crystal specifications
Note: All new designs should use the 38.4 MHz reference clock. For existing designs
the 26 MHz reference clock can still be used.
Table 49. External crystal specifications
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"Parameter

Condition

Min

Typ

Max

Unit

Fundamental frequencies----

26 or 38.4

--

MHz

Resonance mode

--

--

A1,
Fundamental----

Equivalent differential load
capacitance

--

--

5

--

pF

Shunt capacitance

--

--

2

--

pF

Frequency tolerance

Over process at 25ºC

--

±10

--

ppm

Frequency stability

Over operating temperature

--

±10

--

ppm

Aging

--

--

±2

--

ppm/
5 years

Series resistance (ESR)

38.4 MHz

--

--

60

Ω

26 MHz

--

--

60

Ω

Insulation resistanceat DC 100V

500

--

--

MΩ

Drive level

--

150

--

--

µW

Parameter

Min

Typ

Max

Units

Clock frequency range/accuracy• CMOS input clock signal type
• ±250 ppm (initial, aging, temperature)--

32.768--kHz

Phase noise requirement (@ 100 kHz)

--

-125

--

dBc/HzCycle jitter

--

1.5

--

ns (RMS)

Slew rate limit (10-90%)

--

--

100

ns

Duty cycle tolerance

20

--

80

%

9.9.3 External sleep clock specifications[1]

Table 50. External sleep clock specifications[1]

Voltage input levels = 1.8V or 3.3V. See Section 8 "Recommended operating conditions".

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9.10 Power-down (PDn) pin specifications
9.10.1 PDn asserted low—All power supplies good
Figure 24 and Table 51 show the specifications for the PDn signal when it is asserted(low) while all power supplies to the device are good.

Power

TRPW

PDn
TPU_RESET

aaa-036126

Figure 24. Power-down (PDn) pin timing—The power remains high at PDn assertion

Table 51. Power-down (PDn) pin specifications—The power remains high at PDn assertion
Unless otherwise specified, the values apply per the Recommended operating conditions
SymbolParameter

Condition

Min

Typ

Max

Unit

TPU_RESET

Valid power to PDn deasserted

--

0

--

--

ms

TRPW

PDn pulse width

--

1

[1]

--

--

µs

VIH

Input high voltage

--

1.4

--

4.5

V

VIL

Input low voltage

--

-0.4

--

0.5

V

[1]

Minimum value guaranteed for a valid reset. Smaller values may put the device in an undefined state.

9.10.2 PDn asserted Low—One or more power supplies ramp down
Figure 25 and Table 52 show the specifications for the PDn signal when it is asserted(low) while 1 or more of the power supplies (including VCORE) ramps down.

Power

0.2 V
TRD

PDn
TPU_RESETTRPW
TRD = time from PDn assertion until power supply drops to 0.2 V

aaa-036125

Figure 25. Power-down (PDn) pin timing—Power ramps down at PDn assertion

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Table 52. Power-down (PDn) pin secifications—Power ramps down at PDn assertion
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Unit

TPU_RESET

Valid power to PDn deasserted

--

0

—

—

ms

TRPW

PDn pulse width

--

TRD

—

—

µs

VIH

Input high voltage

--

1.4

—

4.5

V

VIL

Input low voltage

--

-0.4

—

0.2

V

[1]

[1]

Minimum value guaranteed for a valid reset. Smaller values may put the device in an undefined state.

9.11 Configuration pin specifications
For a list of configuration pins, see Section 5.6 "Configuration pins".
[1]

Table 53. Configuration pin specifications
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"Parameter

Condition

Min

Typ

Max

Unit

Internal weak pull-up resistanceAround 1 ms following any reset

—

800

—

kΩ

Internal nominal pull-up resistance Around 1 ms following any reset

—

100

—

kΩ

[1]

After approximately 1 ms, the configuration pins become functional pins.

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9.12 JTAG interface specifications
The test interface pins are powered by VIO voltage supply.
See Section 9.1.1 "VIO DC characteristics" for specifications.
TP_TCK
TL_TCK

TH_TCK

JTAG_TCKTSU_TDITHD_TDI

JTAG_TDIJTAG_TMS
TDLY_TDO
JTAG_TDO
aaa-036123

Figure 26. JTAG timing diagram[1]

Table 54. JTAG timing data
Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"SymbolParameter

Condition

Min

Typ

Max

Unit

TP_TCK

TCK period

--

40

--

--

ns

TH_TCKTCK high

--

12

--

--

ns

TL_TCKTCK low

--

12

--

--

ns

TSU_TDI

TDI, TMS to TCK setup time --

10

--

--

ns

THD_TDI

TDI, TMS to TCK hold time

--

10

--

--

ns

TDLY_TDO

TCK to TDO delay

--

0

--

15

ns

[1]

Does not apply to JTAG enabled by the JTAG_TMS pin.

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10 Package information
10.1 Package thermal conditions
10.1.1 68-pin QFN thermal conditions
Table 55. Thermal conditions—QFN package
SymbolθJA

Parameter

Condition

Typ

Unit

Thermal resistanceJunction to ambient of package.
θJA = (TJ - TA)/ P
P = total power dissipation

24 x 30 x 1.05 mm
6-layer PCB
no air flow

43.00

°C/W

24 x 30 x 1.05 mm
6-layer PCB
1 meter/sec air flow

36.90

°C/W

24 x 30 x 1.05 mm
6-layer PCB
2 meter/sec air flow

32.50

°C/W

24 x 30 x 1.05 mm
6-layer PCB
3 meter/sec air flow

30.30

°C/W

ψJT

Thermal characteristic parameter
Junction to top-center of package.
ψJT = (TJ - TTOP)/P
TTOP = temperature on top-center ofpackage

24 x 30 x 1.05 mm
6-layer PCB
no air flow

4.10

°C/W

ψJB

Thermal characteristic parameter
Junction to bottom surface, center ofpackage.
ψJB = (TJ - TB)/P
TB = surface temperature of package

24 x 30 x 1.05 mm
6-layer PCB
no air flow

13.80

°C/W

θJC

Thermal resistanceJunction to case of the package.
θJC = (TJ - TC)/ PTOP
TC = temperature on top-center ofpackage
PTOP = power dissipation from top of
package

24 x 30 x 1.05 mm
6-layer PCB
no air flow

13.80

°C/W

θJB

Thermal resistanceJunction to board of package.
θJB = (TJ - TB)/ PBOTTOM
PBOTTOM = power dissipation from bottomof package to PCB surface

24 x 30 x 1.05 mm
6-layer PCB
no air flow

14.10

°C/W

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10.1.2 83-bump eWLP thermal conditions
Table 56. Thermal conditions—eWLP package
SymbolParameter

Condition

Typ

Unit

Thermal resistanceJunction to ambient of package.
θJA = (TJ - TA)/ P
P = total power dissipation

JEDEC 4 in. x 4.5 in.
4-layer PCB with 41 thermal via
no air flow

28.07

°C/W

JEDEC 4 in. x 4.5 in.
4-layer PCB with no thermal via
no air flow

41.96

°C/W

ψJT

Thermal characteristic parameter
Junction to top-center of package.
ψJT = (TJ - TTOP)/P
TTOP = temperature on top-center ofpackage

JEDEC 4 in. x 4.5 in.
4-layer PCB with no thermal via
no air flow

0.08

°C/W

ψJB

Thermal characteristic parameter
Junction to bottom surface, center ofpackage.
ψJB = (TJ - TB)/P
TB = surface temperature of package

JEDEC 4 in. x 4.5 in.
4-layer PCB with no thermal via
no air flow

15.30

°C/W

θJA

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10.2 Package mechanical drawing
10.2.1 68-pin QFN mechanical drawing

Figure 27. 68-pin QFN mechanical drawing

Note: See also Section 10.1.1 "68-pin QFN thermal conditions" and Section 10.3.1 "68pin QFN package marking".

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10.2.2 83-bump eWLP mechanical drawing

Figure 28. 83-bump eWLP mechanical drawing• Dimensions in mm. Also refer to Section 10.1.2 "83-bump eWLP thermal conditions"and Section 10.3.2 "83-bump eWLP package marking".

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10.3 Package marking
10.3.1 68-pin QFN package marking

Country of origin(contained in the mold ID or
marked as the last line on the
package)Part number, package code, environmental code
xxx = package code
2 = environmental code

88W8987-xxx2
Lot number
YYWW xx#
Country of origin
E

Date code, die revision, assembly plant
YYWW = date code
(YY = year, WW = work week)
xx = die revision# = assembly plant code

Temperature code
E = extended
I = Industrial

Pin 1 location

Note: The above drawing is not drawn to scale. The location of markings is approximate.

Figure 29. 68-pin QFN package marking and pin 1 location

10.3.2 83-bump eWLP package marking

Country of origin(contained in the mold ID or
marked as the last line on the
package)

W8987EAH2
Lot Number
YYWW xx#
Country of Origin

Part number, package code, environmental code
EAH = package code
2 = environmental code
Date code, die revision, assembly plant
YYWW = date code
(YY = year, WW = work week)
xx = die revision# = assembly plant code

Pin 1 location

Note: The above drawing is not drawn to scale. The location of markings is approximate.

Figure 30. eWLP package marking and pin 1 location
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11 Acronyms and abbreviations
Table 57. Acronyms and abbreviations

88W8987_SDS

Product short data sheet

AcronymDefinition

A2DP

Advanced audio distribution profiles

ABR

Automatic baud rate

ACK

Acknowledgment

ADAS

Advanced driver assistance systems

ADC

Analog-to-digital converter

AES

Advanced encryption standard

AFC

Automatic frequency correction

AFH

Adaptive frequency hopping

AGC

Automatic gain control

AHB

Advanced high-performance bus

AIFS

Arbitration inter-frame space

AoA

Angle of arrival

AoD

Angle of departureAP

Access point

APB

Advanced peripheral bus

API

Application program interface

ARM

Advanced RISC machine

ATIM

Announcement traffic indication message

BAMR

Base address mask register

BAR

Base address register

BBU

Baseband processor unit

BCB

Benzocyclobutene (flip chip bump process)

BDR

Basic data rate

BER

Bit error rate

BOM

Bill of materials

BR

Baud rate

BRF

Bluetooth RF unit

BSS

Basic service set

BSSID

Basic service set identifier

BTM

BSS transition management

BTU

Bluetooth baseband unit

BWQ

Bandwidth queue

CBC

Cipher block chaining

CBP

Contention-based period

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 57. Acronyms and abbreviations...continued

88W8987_SDS

Product short data sheet

AcronymDefinition

CCA

Clear channel assessment

CCK

Complementary code keying

CCMP

Counter mode CBC-MAC protocol

CDE

Close descriptor enable

CFP

Contention-free period

CFQ

Contention-free queue

CID

Connection identifier

CIS

Card information structure

CIU

CPU interface unit

CMD

Command

CMQ

Control management queue

CRC

Cyclic redundancy check

CS

Card select

CSL

Coordinated sampled listening

CSMA/CA

Carrier sense multiple access / collision avoidance

CSMA/CD

Carrier sense multiple access / collision detection

CSU

Clocked serial unit

CTS

Clear to send

DAC

Digital-to-analog converter

DBPSK

Differential binary phase shift keying

DCD

Device controller driver

DCE

Data communication equipment

DCF

Distributed coordination function

DCLA

Direct current level adjustment

DCLB

Digital contactless bridge

DCU

DMA controller unit

DFS

Dynamic frequency selection

DIFS

Distributed inter frame space

DMA

Direct memory access

DPD

Digital pre distortion

dQH

Device queue head

DQPSK

Differential quadrature phase shift keying

DSM

Distribution system medium

DSP

Digital signal processor

DSRC

Dedicated short range communications

dTD

Linked list transfer descriptors
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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 57. Acronyms and abbreviations...continued

88W8987_SDS

Product short data sheet

AcronymDefinition

DTIM

Delivery traffic indication message

DUP

Duplicated packet

DVSC

Digital voltage scaling control

EAP

Extensible authentication protocol

EBRAM

Extended block random access memory

ECDSA

Elliptic curve digital signature algorithm

ED

Energy detect

EDCA

Enhanced distributed channel access

EEPROM

Electrically erasable programmable read only memory

EIFS

Extended inter frame Space

ELS

Embedded Edgelock® secure subsystem

EMC

Electromagnetic compatibility

ER

Extended range

ERP-OFDM

Extended rate PHY-orthogonal frequency division multiplexing

ETSI

European telecommunications standards instituteeWLP

Embedded wafer level package

FCC

Federal communications commission

FIFO

First in first out

FIPS

Federal information processing standards

FIQ

Fast interrupt request

FPU

Floating point unit

FW

FirmwareGATT

Generic attribute profile

GCMP

Galois/counter mode protocol

GI

Guard interval

GPIO

General purpose input/output

GPL

General Public License

GPT

General purpose timer

GPU

General purpose input/output unit

HID

Human interface device

HIU

Host interface unit

HOGP

HID over GATT profile

HSP

Hands-free profile

HTHigh throughput

HVQFN

Thermal enhanced very thin quad flat package

HW

Hardware
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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 57. Acronyms and abbreviations...continued

88W8987_SDS

Product short data sheet

AcronymDefinition

I/F

Interface

I/Q

In-phase/quadratureIBIn bandICE

In-circuit emulator (or emulation)

ICRInterrupt cause register

ICU

Interrupt controller unit

ICV

Integrity check value

IE

Information element

IEEE

Institute of electrical and electronics engineers

IEMR

Interrupt event mask register

IFS

inter frame space

IMR

Interrupt mask register

IPG

Inter-packet gap

IPsec

Internet protocol security

IR

Infrared

IRQ

Interrupt request

ISA

Instruction set architecture

ISDN

Integrated services digital network

ISM

Industrial, scientific, and medical

ISMR

Interrupt status mask register

ISR

Interrupt status register

JEDEC

Joint electronic device engineering council

JTAG

Joint test action group

LC3

Low complexity communication codec

LDPC

Low density parity checkLE

Low energy

LEDLight emitting diodeLME

Layer management entity

LNA

Low noise amplifier

LPM

Low power management

LSb

Least significant bit

LSB

Least significant byte

LSP

Low-speed peripheral

LTE

Long term evolution

MAC

Media/medium access controller

MC

Memory controller
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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 57. Acronyms and abbreviations...continued

88W8987_SDS

Product short data sheet

AcronymDefinition

MCI

Microcontroller subsystem

MCS

Modulation and coding scheme

MCU

MAC Control unit

MDI

Modem data interface

MIB

Management information base

MIC

Message integrity code

MII

Media independent interface

MIMO

Multiple input multiple output

MIPS

Million instructions per second

MLME

MAC sublayer management entity

MMI

Modem management interface

MMPDU

MAC management protocol data unit

MMU

Memory management unit

MPDU

MAC protocol data unit

MPU

Memory protection unit

MSb

Most significant bit

MSB

Most significant byte

MSDU

MAC service data unit

MU-MIMO

Multi user MIMOMU-PPDU

Multi user PPDU

MWS

Mobile wireless system
Multimedia wireless system

NAV

Network allocation vector

NBS

Narrow band speech

NDP

Null data packet

NL

No loadNPTR

Next descriptor pointer

Nsts

Number of space time streams

NVIC

Nested vector interrupt controller

OCB

Outside the context of a BSS

OFDM

Orthogonal frequency division multiplexing

OID

Object identifier

OOB

Out of band

OTP

One time programmable

OTT

Over-the-top (device)

P2P

Peer-to-peer

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 57. Acronyms and abbreviations...continued

88W8987_SDS

Product short data sheet

AcronymDefinition

PA

Power amplifier

PAD

Packet assembler/disassembler

PBU

Peripheral bus unit

PC

Point coordinator

PCB

Printed circuit board

PCF

Point coordination function

PCI

Peripheral component interconnect

PCIe

PCI express

PCM

Pulse code modulation

PDn

Power down

PDU

Protocol data unit

PEAP

Protected EAP

PHYPhysical layer

PIFS

Priority inter frame space

PLL

Phase-locked loop

PLME

Physical layer management entity

PMU

Power management unit

POS

Point of sale

POST

Power-on self test

PPDU

PHY protocol data unit

PPK

Per-packet key

PPM

Pulse position modulation

PSK

Pre shared keys

PTA

Packet traffic arbitration

PUF

Physically unclonable function

PWK

Pairwise key

QAM

Quadrature amplitude modulation

QFN

Quad flat non-leaded package

QoS

Quality of service

RA

Receiver address

RBDS

Radio broadcast data system

RDSRadio data system

RFRadio frequency

RFID

Radio frequency identification

RIFS

Reduced inter frame space

RISC

Reduced instruction set computer
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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 57. Acronyms and abbreviations...continued

88W8987_SDS

Product short data sheet

AcronymDefinition

ROM

Read only memory

RSSI

Receiver signal strength indication

RTC

Real time clock

RTS

Request to send

RTU

General purpose timer unit

RU

Resource unit

SA

Source address

SAP

Service access point

SCLK

Serial interface clock

SDA

Serial interface data

SDK

Software development kit

SE

Secure element

SFD

Start of frame delimiter

SHA

Secure hash algorithm

SIFS

Short inter frame space

SISO

Single input single output

SIU

Serial interface unit (UART)SJU

System/software JTAG controller unit

SM

Switch module

SMI

Serial management interface

SNR

Signal-to-noise ratio

SO

Serial out

SoC

System-on-chip

SPDT

Single pole double throw

SPI

Serial peripheral interface

SQU

Internal SRAM unit

SRWB

Serial interface read writeSS

Service set

SSID

Service set identifier

STA

Station

STBC

Space-time block code

SWD

Serial wire debug

SWP

Single wire protocol

SysTick

System tick timer

TA

Transmitter address

TBG

Time base generator
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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 57. Acronyms and abbreviations...continued

88W8987_SDS

Product short data sheet

AcronymDefinition

TBTT

Target beacon transmission time

TCM

Tightly coupled memory

TCP/IP

Transmission control protocol/internet protocol

TCQ

Traffic category queue

TEE

Trusted execution environment

TIM

Traffic indication map

TKIP

Temporal key integrity protocol

TPC

Transmit power control

TQFP

Thin quad flat pack

TRPC

Transmit rate-based power control

TSF

Timing synchronization function

TWT

Target wait time

UART

Universal asynchronous receiver/transmitter

USART

Universal synchronous/asynchronous receiver/transmitter

UBM

Under bump metal

UDP

User datagram protocol

UNII

Unlicensed national information infrastructure

VCO

Voltage controlled oscillator

VHT

Very high throughput

VIF

Voice interface

WAP

Wireless application protocol

WAVE

Wireless access in vehicular environments

WBS

Wide band speech

WCI-2

Wireless coexistence interface 2

WEP

Wired equivalent privacy

WFI

Wait for interrupt

WI

Wired interface

Wi-Fi

Hardware implementation of IEEE 802.11 for wireless connectivity

WLAN

Wireless local area network

WLCSP

Wafer level chip scale package

WMM

Wi-Fi multimedia

WPA

Wi-Fi protected access

WPA2

Wi-Fi protected access 2

WPA2-PSK

Wi-Fi protected access 2 - pre shared key

WPA3

Wi-Fi protected access 3

WPA-PSK

Wi-Fi protected access - pre shared key
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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Table 57. Acronyms and abbreviations...continued

88W8987_SDS

Product short data sheet

AcronymDefinition

XIP

Execute in place

XOSC

Crystal oscillator

ZIF

Zero intermediate frequency

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12 Revision history
Table 58. Revision history
Document ID

Release date

Data sheet status

Change notice

Supersedes

88W8987_SDS v.6.0

20221202

Product short data
sheet

-

88W8987_SDS v.5.0

Modifications

Bluetooth subsystem• Section 4.1 "2.4 GHz Bluetooth Tx/Rx": added a note to AES encryption feature• Section 4.2 "Bluetooth Low Energy (LE)": added a note to AES encryption and Bluetooth
LE Secure Connection features

88W8987_SDS v.5.0

20221111

Modifications

Electrical specifications• Section 9.3.4 "2.4 GHz Wi-Fi transmitter performance": added ± to Transmit output power
accuracy typical value• Section 9.3.5 "5 GHz Wi-Fi transmitter performance": added ± to Transmit output power
accuracy typical value• Section 9.4.2 "Bluetooth and Bluetooth LE transmitter performance": added Transmit
power accuracy typical value• Section 9.5 "Current consumption":– Updated the note above the table– Added the column and values for VIO_3.3 V– Added the rows and values for Wi-Fi 2.4 GHz receive idle mode
– Added the rows and values for Wi-Fi 5 GHz receive idle mode
– Updated Maximum peak current consumption during device initialization values andconditions

88W8987_SDS v.4.0

20220503

Modifications

Electrical specifications• Section 9.5 "Current consumption": updated the values for sleep mode

88W8987_SDS v.3.0

20210915

Modifications• Removed the content about WEP and TKIP as these encryption methods are no longer
supported. Updated sections:– Section 1 "Product overview"– Section 1.2 "Wi-Fi key features"– Section 3.5 "Wi-Fi encryption"• Section 9.8.1 "PCM interface specifications":– PCM_CLK in Figure 20 and Figure 22: renamed TBCLK as 1/FBCLK , added TBCLK rise
and TBCLK fall
– Table 42 and Table 43: added FBCLK min and max values

88W8987_SDS v.2.0

20210521

Modifications• Updated Bluetooth certification compliance to version 5.2

88W8987_SDS v.1.0

20201008

88W8987_SDS

Product short data sheet

Product short data
sheet

Product short data
sheet

Product short data
sheet

Product short data
sheet
Product short data
sheet

-

-

-

-

-

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88W8987_SDS v.4.0

88W8987_SDS v.3.0

88W8987_SDS v.2.0

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13 Legal information
13.1 Data sheet status
Document status[1][2]

Product status[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for productdevelopment.

Preliminary [short] data sheet

Qualification

This document contains data from the preliminary specification.

Product [short] data sheet

Production

This document contains the product specification.

[1]
[2]
[3]

Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

13.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may resultin modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have noliability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet isintended for quick reference only and should not be relied upon to containdetailed and full information. For detailed and full information see therelevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with theshort data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Productdata sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors andcustomer have explicitly agreed otherwise in writing. In no event however,shall an agreement be valid in which the NXP Semiconductors productis deemed to offer functions and qualities beyond those described in the
Product data sheet.

13.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. NXP Semiconductors takes noresponsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited inaccordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right tomake changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
88W8987_SDS

Product short data sheet

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical orsafety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability forinclusion and/or use of NXP Semiconductors products in such equipment orapplications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of theirapplications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for thecustomer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use bycustomer’s third party customer(s). Customer is responsible for doing allnecessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above thosegiven in the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects toapplying the customer’s general terms and conditions with regard to thepurchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of thisdocument, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Suitability for use in non-automotive qualified products — Unless
this data sheet expressly states that this specific NXP Semiconductors
product is automotive qualified, the product is not suitable for automotive
use. It is neither qualified nor tested in accordance with automotive testingor application requirements. NXP Semiconductors accepts no liability forinclusion and/or use of non-automotive qualified products in automotive
equipment or applications.
In the event that customer uses the product for design-in and use inautomotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warrantyof the product for such automotive applications, use and specifications, and(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design anduse of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document, including
the legal information in that document, is for reference only. The English
version shall prevail in case of any discrepancy between the translated andEnglish versions.

88W8987_SDS

Product short data sheet

Security — Customer understands that all NXP products may be subject tounidentified vulnerabilities or may support established security standards or
specifications with known limitations. Customer is responsible for the designand operation of its applications and products throughout their lifecycles
to reduce the effect of these vulnerabilities on customer’s applications
and products. Customer’s responsibility also extends to other open and/or
proprietary technologies supported by NXP products for use in customer’s
applications. NXP accepts no liability for any vulnerability. Customer should
regularly check security updates from NXP and follow up appropriately.
Customer shall select products with security features that best meet rules,
regulations, and standards of the intended application and make theultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may beprovided by NXP.
NXP has a Product Security Incident Response Team (PSIRT) (reachable
at PSIRT@nxp.com) that manages the investigation, reporting, and solution
release to security vulnerabilities of NXP products.

13.4 Trademarks
Notice: All referenced brands, product names, service names, andtrademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

TablesTab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
Tab. 15.
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.
Tab. 20.
Tab. 21.
Tab. 22.
Tab. 23.
Tab. 24.
Tab. 25.
Tab. 26.
Tab. 27.
Tab. 28.
Tab. 29.
Tab. 30.
Tab. 31.

Part order codes ............................................... 6
Pin types ......................................................... 16
Pin list by number ........................................... 18
Pad locations—83-bump eWLP ...................... 21
General purpose I/O (GPIO) (MFP) ................ 24
Wi-Fi/Bluetooth radio interface - QFN
package ........................................................... 27
Wi-Fi/Bluetooth radio interface - eWLP
package option ................................................27
Wi-Fi RF front-end control interface ................ 27
SDIO host interface .........................................28
UART host interface (MFP) .............................28
Audio interface pins (MFP) ............................. 29
Configuration interface .................................... 29
Clock interface (MFP) ..................................... 30
Power down (PDn) pin .................................... 30
Power supply and ground ............................... 31
Configuration pins ........................................... 32
Host configuration options ...............................32
Absolute maximum ratings .............................. 36
Limiting values - QFN option ...........................36
Limiting values - eWLP option ........................ 36
Recommended operating conditions ............... 37
DC electrical characteristics—1.8V
operation (VIO) ................................................38
DC electrical characteristics—3.3V
operation (VIO) ................................................38
LED mode data ............................................... 38
DC electrical characteristics—1.8V
operation (VIO_RF) ......................................... 39
DC electrical characteristics—3.3V
operation (VIO_RF) ......................................... 39
2.4 GHz Wi-Fi receiver performance ...............41
5 GHz Wi-Fi receiver performance ..................43
2.4 GHz Wi-Fi transmitter performance ...........46
5 GHz Wi-Fi transmitter performance ..............47
Local oscillator ................................................ 48

Tab. 32.
Tab. 33.
Tab. 34.
Tab. 35.
Tab. 36.
Tab. 37.
Tab. 38.
Tab. 39.
Tab. 40.
Tab. 41.
Tab. 42.
Tab. 43.
Tab. 44.
Tab. 45.
Tab. 46.
Tab. 47.
Tab. 48.
Tab. 49.
Tab. 50.
Tab. 51.
Tab. 52.
Tab. 53.
Tab. 54.
Tab. 55.
Tab. 56.
Tab. 57.
Tab. 58.

Bluetooth and Bluetooth LE receiver
performance .................................................... 49
Bluetooth and Bluetooth LE transmitter ...........51
Current consumption ....................................... 53
DC electrical characteristics—1.8V
operation (VIO_SD) .........................................56
SDIO timing data—Default Speed, HighSpeed Modes .................................................. 57
SDIO timing data——SDR12, SDR25,
SDR50 Modes (up to 100 MHz) (1.8V) ........... 58
SDIO timing data—SDR104 mode (208
MHz) ................................................................ 59
SDIO timing data—DDR50 mode (50 MHz) .... 60
SDIO internal pull-up/pull-down
specifications ................................................... 61
UART timing data ............................................62
PCM timing specification data—Centralmode ............................................................... 63
PCM timing specification data—Peripheral
mode ............................................................... 64
Clock DC specifications .................................. 65
26 MHz clock timing ........................................65
38.4 MHz clock timing .....................................65
Phase Noise—2.4 GHz operation ................... 66
Phase Noise—5 GHz operation ...................... 66
External crystal specifications ......................... 67
External sleep clock specifications ..................67
Power-down (PDn) pin specifications—The
power remains high at PDn assertion ............. 68
Power-down (PDn) pin secifications—Power ramps down at PDn assertion .............. 69
Configuration pin specifications .......................69
JTAG timing data ............................................ 70
Thermal conditions—QFN package ................ 71
Thermal conditions—eWLP package .............. 72
Acronyms and abbreviations ........................... 76
Revision history ...............................................85

FiguresFig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.

Application diagram—QFN package option .......2
Application diagram—eWLP package
option .................................................................2Internal block diagram—QFN package
option .................................................................5Internal block diagram—eWLP package
option .................................................................5
Part numbering scheme .................................... 6
Signal diagram—QFN ..................................... 14
Signal diagram—eWLP ................................... 15
Pin assignment—68-pin QFN package
option ...............................................................17
Pad locations—83-bump eWLP (nonbump-side view, bumps down) ........................20
Power-up sequence ........................................ 34

88W8987_SDS

Product short data sheet

Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Fig. 15.
Fig. 16.
Fig. 17.
Fig. 18.

Power-down sequence ....................................35
RF performance measurement points ............. 40
SDIO protocol timing diagram—Default
speed mode .................................................... 56
SDIO protocol timing diagram—High-speed
mode ............................................................... 56
SDIO protocol timing diagram—SDR12,
SDR25, SDR50 Modes (up to 100 MHz)
(1.8V) ...............................................................58
SDIO protocol timing diagram—SDR104
mode (208 MHz) ............................................. 59
SDIO CMD timing diagram—DDR50 mode
(50 MHz) ......................................................... 60
SDIO DAT[3:0] timing diagram—DDR50
mode (50 MHz) ............................................... 60

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NXP Semiconductors

2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.

UART timing diagram ......................................62
PCM timing specification diagram for data
signals—Central mode .................................... 63
PCM timing specification diagram for
PCM_SYNC signal—Central mode ................. 63
PCM timing specification diagram for data
signals—Peripheral mode ............................... 64
PCM timing specification diagram for
PCM_SYNC signal—Peripheral mode ............ 64

88W8987_SDS

Product short data sheet

Fig. 24.
Fig. 25.
Fig. 26.
Fig. 27.
Fig. 28.
Fig. 29.
Fig. 30.

Power-down (PDn) pin timing—The power
remains high at PDn assertion ........................ 68
Power-down (PDn) pin timing—Powerramps down at PDn assertion ......................... 68
JTAG timing diagram .......................................70
68-pin QFN mechanical drawing ..................... 73
83-bump eWLP mechanical drawing ...............74
68-pin QFN package marking and pin 1
location ............................................................ 75
eWLP package marking and pin 1 location ..... 75

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

Contents
1
Product overview ................................................ 1
1.1
Applications ........................................................3
1.2
Wi-Fi key features ............................................. 3
1.3
Bluetooth key features .......................................3
1.4
Host interfaces ...................................................3
1.5
Operating characteristics ................................... 3
1.6
General features ................................................ 4
1.7
Internal block diagram ....................................... 5
2
Ordering information .......................................... 6
3
Wi-Fi subsystem ..................................................7
3.1
IEEE 802.11 standards ......................................7
3.2
Wi-Fi MAC ......................................................... 8
3.3
Wi-Fi baseband ................................................. 9
3.4
Wi-Fi radio ....................................................... 10
3.5
Wi-Fi encryption ...............................................10
3.6
Wi-Fi host interfaces ........................................10
4
Bluetooth subsystem ........................................11
4.1
2.4 GHz Bluetooth Tx/Rx .................................11
4.2
Bluetooth Low Energy (LE) ..............................12
4.3
Bluetooth host interfaces ................................. 13
4.4
Coexistence ..................................................... 13
4.5
PCM interface ..................................................13
5
Pin information ..................................................14
5.1
Signal diagrams ............................................... 14
5.1.1
Signal diagram for QFN package option ..........145.1.2
Signal diagram for eWLP package option ........15
5.2
Pin types ..........................................................16
5.3
Pin assignment—68-pin QFN .......................... 17
5.3.1
Pin list by number ............................................18
5.4
Pad locations—83-bump eWLP .......................20
5.5
Pin description ................................................. 24
5.5.1
Pin states .........................................................24
5.5.2
General purpose I/O (GPIO) ............................24
5.5.3
Wi-Fi/Bluetooth radio interface ........................ 27
5.5.4
Wi-Fi RF front-end control interface .................27
5.5.5
SDIO host interface ......................................... 28
5.5.6
UART host interface ........................................ 28
5.5.7
Audio interface .................................................29
5.5.8
Configuration interface .....................................29
5.5.9
Clock interface .................................................30
5.5.10Power down (PDn) pin .................................... 30
5.5.11
Power supply and ground ................................31
5.6
Configuration pins ............................................32
6
Power information .............................................33
6.1
Power-up sequence .........................................33
6.2
Power-down sequence .................................... 35
6.3
Reset ................................................................35
6.3.1
Lowest power state ......................................... 35
7
Absolute maximum ratings .............................. 36
8
Recommended operating conditions .............. 37
9Electrical specifications ................................... 38
9.1
GPIO/LED interface specifications ...................38
9.1.1
VIO DC characteristics .................................... 38
9.1.1.1
1.8V operation ................................................. 38
9.1.1.2
3.3V operation ................................................. 38
9.1.2
LED mode ........................................................38
88W8987_SDS

Product short data sheet

9.2
9.2.1
9.2.1.1
9.2.1.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.4.1

RF front-end control interface specifications ....39
VIO_RF DC characteristics ..............................39
1.8V operation ................................................. 39
3.3V operation ................................................. 39
Wi-Fi radio specifications .................................40
Wi-Fi radio performance measurement ........... 40
2.4 GHz Wi-Fi receiver performance ............... 41
5 GHz Wi-Fi receiver performance .................. 43
2.4 GHz Wi-Fi transmitter performance ........... 46
5 GHz Wi-Fi transmitter performance .............. 47
Local oscillator .................................................48
Bluetooth radio specifications .......................... 49
Bluetooth and Bluetooth LE receiver
performance .....................................................49
9.4.2
Bluetooth and Bluetooth LE transmitter
performance .....................................................51
9.5
Current consumption ....................................... 53
9.6
SDIO host interface specifications ...................56
9.6.1
VIO_SD DC characteristics ............................. 56
9.6.1.1
1.8V operation ................................................. 56
9.6.2
Default speed, high-speed modes ................... 56
9.6.3
SDR12, SDR25, SDR50 modes (up to 100MHz) (1.8V) ..................................................... 58
9.6.4
SDR104 mode (208 MHz) (1.8V) .................... 59
9.6.5
DDR50 mode (50 MHz) (1.8V) ........................ 60
9.6.6
SDIO internal pull-up/pull-down
specifications ................................................... 61
9.7
High-speed UART specifications ..................... 62
9.8
Audio interface specifications .......................... 62
9.8.1
PCM interface specifications ........................... 62
9.9
Reference clock specifications ........................ 65
9.9.1
External crystal oscillator specifications ...........65
9.9.2
External crystal specifications ..........................67
9.9.3
External sleep clock specifications .................. 67
9.10
Power-down (PDn) pin specifications .............. 68
9.10.1
PDn asserted low—All power supplies good ... 68
9.10.2
PDn asserted Low—One or more power
supplies ramp down ........................................ 68
9.11
Configuration pin specifications ....................... 69
9.12
JTAG interface specifications .......................... 70
10Package information .........................................71
10.1
Package thermal conditions .............................71
10.1.168-pin QFN thermal conditions ........................ 71
10.1.2
83-bump eWLP thermal conditions ..................72
10.2
Package mechanical drawing .......................... 73
10.2.168-pin QFN mechanical drawing ..................... 73
10.2.2
83-bump eWLP mechanical drawing ............... 74
10.3
Package marking ............................................. 75
10.3.168-pin QFN package marking ..........................75
10.3.2
83-bump eWLP package marking ................... 75
11
Acronyms and abbreviations ...........................76
12
Revision history ................................................ 85
13
Legal information .............................................. 86

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2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section 'Legal information'.

© 2022 NXP B.V.

All rights reserved.

For more information, please visit: http://www.nxp.com
Date of release: 2 December 2022
Document identifier: 88W8987_SDS