Total Ionization Damage Effects in Double
Silicon-on-Insulator Devices
S. Honda, K. Hara, M. Asano, T. Maeda, N. Tobita, Y. Arai, T. Miyoshi, M. Ohno, T. Hatsui, T. Tsuru, N. Miura,
H. Kasai, M. Okihara
Abstract– We are developing monolithic pixel sensors based ona 0.2 μm fully-depleted silicon-on-Insulator (SOI) technology.
The major issue in applications them in high-radiation
environments is the total ionization damage (TID) effects. Theeffects are rather substantial in the SOI devices since thetransistors are enclosed in the oxide layers where generated holes
are trapped and affect the operation of the near-by transistors.
The double SOI sensors that provide an independent electrode
underneath the buried oxide layer have been developed. We have
irradiated transistor test elements and pixel sensors with γ-rays.
By adjusting the potential of this electrode, the TID effects areshown to be compensated. The pixel sensor irradiated to 20 kGy
recovered its functionality by applying a bias to the electrode.
The radiation tolerance of the SOI devices has been substantially
improved by the double SOI.

I. INTRODUCTION
of novel monolithic pixel devices utilizing
Tthe potentiality
0.2-μm fully depleted silicon-on-insulator (FD-SOI)
HEtechnology provided by Lapis Semiconductor [1] has been
intensively explored for various applications including space,γ/X-ray imaging, high-energy, and other applications[2][3][4][5]. Our technology characteristics, in addition toutilization of the commercial reliable process, is adaption ofbonded wafers provided by SOITEC Co.[6] We adopt highresistive silicon as the SOI handle wafer to use it as thesensing part. A schematic diagram of typical SOI pixel device
is illustrated in Fig. 1. Nominally the top is 40-nm thicksilicon of 18 Ωcm, separated by a 200-nm thick buried oxide(BOX) layer with the handle wafer. Table 1 summarizes theLapis FD-SOI process, where the silicon types and resistivity
Manuscript received November 15, 2013. This work was supported in partby Kakenhi [grant number 25109006A].
S. Honda, K. Hara, M. Asano, T. Maeda, and N. Tobita are with Graduate
School of Pure and Applied Sciences, University of Tsukuba, Tsukuba,Ibaraki 305-8571 Japan (telephone: +81-29-853-4270, e-mail: hara@px.tsukuba.c.jp).
Y. Arai and T. Miyoshi are with Institute of Particle and Nuclear Studies,High Energy Accelerator Organization (KEK), Tsukuba, Ibaraki 305-0801
Japan.
M. Ohno is with National Institute of Advanced Industrial Science andTechnology (AIST), Tsukuba, Ibaraki, Japan.
A. Takeda is with School of High Energy Accelerator Science, The
Graduate University for Advanced Studies, Tsukuba, Ibaraki 305-0801 Japan.
T. Hatsui is with RIKEN SPring-8 Center, RIKEN, Sayo, Hyogo, Japan.
T. Tsuru is with Division of Physics and Astronomy, Graduate School ofScience, Kyoto University, Sakyo, Kyoto, Japan.
N. Miura and H. Kasai are with Lapis Semiconductor Miyagi Co., Ltd.,Ohira, Miyagi, Japan.
M. Okihara is with Lapis Semiconductor Co., Ltd., Yokohama, Kanagawa,Japan.

values adopted so far are also shown. Thicker devices (up to700 μm thickness) are of particular useful for X-ray detectors
while thin devices (down to 50 μm) for high-energy physics
applications, both being able to be fully depleted.
There are a couple of issues to solve, though, have becomeobvious. The back-gate effect where the voltage applied to theback as the detector bias affects the operation of top-side
circuit. This has been diminished by applying BPW (buried pwell) for p-type pixel nodes (BNW for n-type pixel nodes), as
also illustrated in the figure. The potential of such electrodes isstabilized externally or by the pixel node.
Another issue is that the total ionization damage (TID)
effect [7] is rather substantial since each SOI transistor is fully
enclosed in oxide and the holes trapped in the oxide layers
shift negatively the transistor threshold [8][9][10]. The
operation of the transistors, e.g., threshold voltages, should berestorable by applying negative voltage to the positivelyFig. 1. Schematics of SOI monolithic pixel device. The pixel electrodes,
fabricated through the BOX layer, and SOI MOS transistor terminals areinterconnected via metal layers on top of the device. The device is biased
from the back or from the front n+ contact (Bias Ring).

TABLE 1. MAIN PROCESS PARAMETERS
Process
0.2μm low leakage fully-depleted SOI CMOS
1 poly+5 metal layers, MIM (1.5 μF/μm2), DMOS
Core (I/O) voltage=1.8 (3.3)VSOI wafer Diameter : 200 mmφ
Top Si : Cz ~18Ωcm (p-type) ,40 nm thickBuried oxide: 200 nm thickHandle wafer: Cz(n, 0.7kΩcm), FZ(n,7k),FZ(p,25k)
Double SOI available

Backside

Mechanical grind (down to 200 μm), chemicaletching, implant, laser annealing, Al plating
Further thinning to (50,100 μm) available

charged area. The developed BPW is not suitable for thispurpose because of the potential configurations among thepixel node, BPW, and the back. The BNW with n-type pixel
nodes may be effective provided that the sheet resistance islow enough. The additional BPW/BNW electrodes, though,modify the detector capacitance, hence the response shape,
and tend to increase the coupling noise among the circuitry
through this common electrode.
Recently double SOI wafers were fabricated by SOITEC
per our request. Their patented SmartCutTM process wasrepeated twice to form two sets of silicon and BOX pair layer.
Usual electronics part is processed on the top silicon, whereas
the second silicon layer is used as an individual electrode thatcan control the potential to suppress the TID effect. Also thesame layer should be effective to suppress the back-gate effectand the noise coupling.
We have fabricated transistor test element groups (TrTEG)
and conducted Co γ irradiation to investigate the effectivenessof the double SOI in TID suppression. The functionality of awhole pixel device was examined by irradiating integration
type pixel sensors INTPIXh2.

II. DOUBLE SOI PROCESS AND TESTED SAMPLES
The double SOI wafers provided by SOITEX employ ptype Cz silicon (10-18 Ωcm) for top and second (middle)
layers of about 80 nm thickness each, and a handle wafer of ntype Cz 700 Ωcm. The top two layers are interleaved with aSiO2 layer (BOX2) of 150 nm thickness, and the middle layer
and the handle wafer with BOX1 of another 150 nm thickness.
(The values are typical.) Fig. 2 is a TEM image showing one
set of transistor at left and a pixel node reaching through to thehandle wafer. Connections to the gate and to the middle layer
are provided in a different slice cross-section. The sheet
resistance of the middle layer is 170 kΩ/sq with CoSi2 layer
fabricated on top and 1 MΩ/sq without.

Fig. 2. TEM image of a double SOI transistor and a pixel node.

TABLE IIA. CHARACTERISITICS OF 11 TRANSISTORS IN TRTEG_O. L
AND W ARE IN MICRONS; M SHOWS THE NUMBER OF TRANSISITORS TIEDIN SERIES TO EFFECTIVELY LENGTHEN W. LV T: LOW-VOLTAGE
THRESHOLD, NVT: NORMAL-VOLTAGE THRESHOLD, HVT: HIGHVOLTAGE THRESHOLD. THERE ARE TWO TYPES OF SOURCE-TIE (TIE ANDTIE2).
TRLWMCOMMENT00.20

51LVT10.2051NVT

20.40

51

NVT_S-TIE230.35

51

NVT_S-TEI240.20

51

NVT_S-TIE

50.35

51IOHVT

60.35

51IONVT

70.40

51IOHVT_S-TIE280.35

51IONVT_S-TIE2

90.35

51

IONVT_S-TIE

100.402.5

2

NVT_S-TIE2

TABLE IIB. CHARATCERISTICS OF 18 TRANSISTORS IN TRTEG6.
MULT_B-TIE : MULTIPLE BODY TIE. THE EFFECTIVE W/L IS 100 FOR ALL.
TRLW

MCOMMENT

00.20

54

NVT

10.50

510

NVT

21.00

520

NVT

30.20

54LVT

40.50

510

LVT

51.00

520

LVT

60.35

57

IOHVT

70.35

57

IOHVT

80.20

54

LVT_S-TIE

90.50

510

LVT_S-TIE

101.00520

LVT_S-TIE

110.40104

NVT_S-TIE2

120.60610

NVT_S-TIE2

131.00520

NVT_S-TIE2

140.2054

NVT_MULT_B-TIE

150.50510

NVT_MULT_B-TIE

16

1.00

520

NVT_MULT_B-TIE

17

1.00

520

IONVT_S-TIE

We evaluated the radiation damage using two versions ofTrTEG, TrTEG_o and TrTEG6, where various transistors
were fabricated as listed in Tables IIA and IIB. There are intotal 29 transistor types each for PMOS and NMOS. The W/Lratios range from 25 to 100. The core transistors (tOX=4 nm)

include low (LVT) and normal (NVT) threshold types, and IO(tOX=7 nm) include normal (IONVT) and high (IOHVT)
threshold types. We examined source-tie schema with two
versions for both core and IO, and multiple body ties for thecore.
The INTPIXh2 sensor is composed of pixels of 18 μmsquare, which has an on-pixel circuit as shown in Fig. 3. The
pixel outputs in the same column are sent out one after theother to a 12-bit ADC located outside the chip. Since theirradiation was performed on a chip basis, the functionality ofthe on-pixel circuits and a common on-chip peripheral circuit
including output buffers and switching logics was examined.

ranged from 500 Gy up to 200 kGy for TrTEG samples and up
to 20 kGy for INTPIXh2. Most of the samples were irradiatedwith all the terminals grounded. Some TrTEG6 samples for 20
kGy irradiation were examined in other biasing conditions,which is detailed in later section. The irradiation wasperformed at room temperature. The samples, each received
the target dose for a time span of typically 20 h, were brought
to University of Tsukuba in four hours and then kept
refrigerated at −20oC except during the characterization
measurements.
Fig. 4 shows a typical example (TrTEG6 no.14) of ID-VG
curves measured at pre-irradiation and at different doses withthe middle SOI voltage VSOI2=0 V. The curves were obtainedat VD=1.8 V and VS=0 V for NMOS, and VD= −1.8 V and
VS=0 V for PMOS. For both NMOS and PMOS, the curve
shifts negatively as accumulating the dose, as expected thatthe holes trapped in the oxide effectively reduce the required
transistor threshold voltage. The transistor performance wascharacterized by three quantities:(1) threshold voltage (Vth), defined as VG at ID=100 W/L [nA](2) trans-conductance (gm), gm in [S](3) sub-threshold swing (S), S in [V/dec]

Fig. 3. On-pixel circuit employed in INTPIXh2. Analog data isextracted to an off-chip 12-bit ADC through COL_OUT via buffer
amplifier.

III. COBALT IRRADIATION AND EXAMPLE CHARACTERISTICS
The 60Co γ irradiation was performed at Takasaki
Advanced Radiation Research Institute, JAEA. The total dose

The threshold voltages for a typical sample are shown inFig. 5 as a function of the dose for different VSOI2 settings. By
properly adjusting VSOI2, the threshold voltage can be restored
to the original value. Similar plots for the trans-conductanceand swing compensations are shown in Fig. 6. In the following,
the curves are used to determine the VSOI2 voltage per dose torestore each of the three transistor quantities to the preirradiation value measured at VSOI2=0; we call the voltage as
optimum VSOI2.

Fig. 4. ID-VG curves for typical (left) NMOS and (right) PMOS transistors, measured at VSOI2=0 V. The curve shifts negatively with accumulating the dose.

IV. COMPENSATION BY SOI2
A. Compensating threshold voltage shift
The optimum VSOI2 voltages are plotted in Fig. 7 tocompensate the threshold voltage shifts. The data are shown
separately for core and IO transistors, and for NMOS andPMOS. While the PMOS shows a monotonic decrease withthe dose, there are two groups for the NMOS, clearlyseparated by either body-floating or source-tied. The trend ofbody-floating transistors is illustrated by the phenomenon
called ``rebound’’ [11]. The Si-SiO2 interface traps generated
by irradiation are negatively charged for NMOS, which

partially compensate the effects caused by hole traps in theoxide. The interface traps are dependent on oxide processing
and conditions such as applied voltage at irradiation. Sourcetied NMOS transistors manifest smaller compensating effects,
hence larger VSOI2 is required. No noticeable difference isobserved between core and IO transistors.
B. Compensating gm and S shifts
Fig. 8 shows the optimum VSOI2 to compensate the transconductance and sub-threshold shifts. Since gm variation withdose is moderate for NMOS, the optimum voltages apparently
differ between NMOS and PMOS.

Fig. 5. Threshold voltages as function of dose for (left) NMOS and (right) PMOS. Different curves are for VSOI2 varied from 0 to -15 V. The
dashed lines indicate the threshold voltage of the pre-irradiation sample measured at VSOI2=0 V.

Fig. 6. (Top) Trans-conductance shifts and (above) swing shifts in percentage as function of the dose. Left: NMOS and Right: PMOS. Different
curves are for VSOI2 varied from 0 to -15 V

Vth_core_NMOS〇B o d y F lo a tin g△ S o u rce T ie
□ S o u rce T ie T y p e 2◇B o d y T ie (V B o d y = G N D )Vth_core_PMOS〇B o d y F lo a tin g△ S o u rce T ie
□ S o u rce T ie T y p e 2◇B o d y T ie (V B o d y = G N D )Vth_IO_NMOS〇B o d y F lo a tin g△ S o u rce T ie
□ S o u rce T ie T y p e 2◇B o d y T ie (V B o d y = G N D )Vth_IO_PMOS〇B o d y F lo a tin g△ S o u rce T ie
□ S o u rce T ie T y p e 2◇B o d y T ie (V B o d y = G N D )Fig. 7. Optimum VSOI2 voltages as function of dose to compensate the threshold voltage shifts. The data are shown for all the tested transistors
separately for the core (top) and IO (above) transistors, and for (left) NMOS and (right) PMOS.

gm_core_NMOS〇B o d y F lo a tin g

gm_core_PMOS〇B o d y Flo a tin g△ S o u rce T ie

△ S o u rce T ie

□ S o u rce T ie T yp e 2◇B o d y T ie (V B o d y = G N D )□ S o u rce T ie T y p e 2◇B o d y T ie (V B o d y= G N D )S_core_NMOS〇B o d y F lo a tin g

S_core_PMOS〇B o d y Flo a tin g△ S o u rce T ie

△ S o u rce T ie

□ S o u rce T ie T yp e 2◇B o d y T ie (V B o d y = G N D )□ S o u rce T ie T y p e 2◇B o d y T ie (V B o d y= G N D )Fig. 8. Optimum VSOI2 voltages as function of dose to compensate (top) the trans-conductance shifts and (above) sub-threshold shifts. The data areshown for all the tested transistors separately for (left) NMOS and (right) PMOS.

C. Dependence on biasing
The effect of biasing configuration during irradiation wasevaluated at one irradiation point of 20 kGy. The thresholdvoltages for a typical sample are summarized in Fig. 9. With
the condition VDS=1.8 V and VG=0 V (VS=0 V for NMOS andVD=0 V for PMOS), the threshold shift becomes larger for
NMOS while it becomes smaller for PMOS. This isunderstandable since the potential of gate is lower (higher) in
NMOS (PMOS) than the body potential, demoting(promoting) holes in the gate oxide to recombine. Thismechanism is diminished when VSOI2 is set negative.

V. PIXEL RESPONSE
The functionality of the pixel sensor as a whole wasexamined by irradiating four pixel sensors to the dose from 1
kGy to 20 kGy. The electronics functionality evaluated as theresponse to reset voltages RSTV (see Fig. 3) is presented inFig. 10. The output pulse height increases with the dose for thesame RSTV, reaching the ADCs full count range. TheAt
response curve is mostly restored by applying VSOI2.
VSOI2= −7 V, the threshold voltage of the main PMOS
transistor, shown in Fig. 3, is expected to be compensated at20 kGy (see Fig. 7). Since multiple and various transistors areFig. 9. Threshold voltages for samples irradiated to 20 kGy for (left) NMOS and (right) PMOS. The data are compared among different biasing
conditions during irradiation: all terminals were grounded; VDS=1.8 V and VSOI2=0 V; VDS =1.8 V and VSOI2= −5 V. TR6 of TrTEG6.

Fig. 10. Response measured with varying RESET Voltage (RSTV). (Left) Samples irradiated to 1 kGy to 20 kGy and measured at VSOI2=0 arecompared with pre-irradiation sample. (Right) Sample irradiated to 20 kGy is measured with varying VSOI2 voltage. In both measurements thesensors were biased at 50 V. The ADC is 12 bits.

Fig. 11. Response to white light of the sample irradiated to 20 kGy are measured at (left) VSOI2=0 V and (right) VSOI2= −4 V.

involved in the circuit, the response curve is not completely
back to the original curve, yet the functionality as a pixel
device is recovered.
The recovery is clearly seen in the pixel response to whitelight spotted around the chip center, as shown in Fig. 11.
While the response is almost saturated at VSOI2= 0 V, showing
small signal ADC counts, the spot image is obtained by setting
VSOI2 at −4 V.
VI. SUMMARY
We have evaluated the TID effects in the newly developed
double SOI devices, demonstrating that the TID effects in theSOI transistors are mostly compensable by VSOI2 adjustment in
the dose range up to 200 kGy. The pixel devices irradiated up
to 20 kGy showed substantial recovery in response, although
periodical calibration should be required to maintain theoriginal performance.
The optimum VSOI2 is found to show some modest
differences among the samples, NMOS and PMOS, sourcetied and body floating, depending on the transistor
characteristics values (threshold voltage, trans-conductance,sub-threshold swing) to compensate. Differences dependingon the biasing condition during irradiation are observed.
In summary, the radiation tolerance has been enhanced
substantially by employing the innovative double SOI. Underconsideration of the observed differences and the impact
factors of the individual transistors in view of the required
pixel performance, it should be possible to design radiation
tolerant devices. The present study encourages us anddesigning SOI pixel sensors for future collider experiments isset forward.
ACKNOWLEDGMENT
This work is supported by KEK Detector Technology
Project and also by VLSI Design and Education Center(VDEC), The University of Tokyo, with the collaboration ofthe Cadence Corporation, Synopsys Corporation, and Mentor
Graphics Corporation.
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