Selected Papers

Packet-level Optical Timing-pulse Generator and Its
Application to 40-Gbit/s Optical Packet Self-routing
Tatsushi Nakahara†, Ryo Takahashi,
and Hirokazu Takenouchi
Abstract
We describe a novel packet-level optical timing-pulse (clock-pulse) generator that generates one optical pulse per incoming asynchronous burst optical packet: the generated optical pulse is accurately synchronized with the input optical packet. We also describe 40-Gbit/s optical packet self-routing based on
40-Gbit/s 16-bit serial optical-label recognition by a CMOS (complementary metal-oxide-semiconductor) circuit operated together with an all-optical serial-to-parallel converter and the optical timing-pulse
generator.

1. Introduction
Optical packet switching is a promising way tomeet bandwidth requirements as they increase withthe rapid growth of Internet traffic, because it enables
the maximum utilization of a single channel provided
in the optical network [1]. The fundamental functionsof a switching node in such an optical packetswitched network are burst-mode synchronization,
recognition of the optical label attached to each packet and label-based packet forwarding of incoming
high-bit-rate burst optical packets. For both the label
recognition and packet forwarding control, the label
refers to a routing table listing many addresses andcorresponding route information. The execution ofthese rather complicated label processing functions isinevitably entrusted to electronic circuits, especially
CMOS LSIs (complementary metal-oxide-semiconductor circuits on large-scale integrated circuits).
However, it is difficult to process serial-bit signals,
especially asynchronous burst ones, that have a bit
rate of 40 Gbit/s or higher directly with such electronic circuits because of their limited operating
speed. Therefore, a method of interfacing high-bitrate burst optical packets with a smart but rather slow

electronic label processor is essential. The self serialto-parallel conversion (self-SPC*1) system shown in
Fig. 1 provides such an interface in the opticaldomain. The self-SPC system consists of an all-optical serial-to-parallel converter (SPC) [2], [3] and apacket-level optical timing-pulse (clock-pulse) generator (OCG) [4]. When a high-bit-rate asynchronousburst optical packet arrives, the self-SPC system converts the n-bit serial optical label attached to the optical packet into n parallel channels of signals by operating its all-optical SPC once per packet. For thisoperation, the OCG feeds one synchronized control
signal to the SPC per packet. Because the bit rate of
the parallelized label signals is as slow as the packet
rate, the parallel signals can be processed by a rather
slow CMOS circuit after they have been converted
into electrical signals with an appropriate duration bya slow photodetector (PD) array. The self-SPC system can thus decrease the bit rate of high-bit-rate
burst optical packets and interface them with a
CMOS-based label processor that enables overall andsystematic control of the packet switching.
In this paper, we describe a novel OCG composedof optoelectronic circuits [4]. The OCG detects an
incoming asynchronous burst optical packet of arbitrary length that does not have any preamble bits and† NTT Photonics Laboratories
Atsugi-shi, 243-0198 Japan
E-mail: nak@aecl.ntt.co.jp*1 SPC: refers to both a serial-to-parallel converter and the process ofserial-to-parallel conversion.

Vol. 2 No. 7 July 200431

Selected Papers

Label recognition&
packet switching
control

Self-SPC system
High-bit-rate
optical packet(≥ 40 Gbit/s)

SPC
Payload

n-bit
label

OCG

Slow
PD
array

CMOS

n parallel
channelsof signals

Fig. 1. Self-SPC system for processing high-bit-rate optical labels.

Incoming optical packets(≥ 40 Gbit/s)

One generated opticalpulse per incoming packet

OCG• Asynchronous & bursty• Arbitrary length• Fluctuations in intensity and polarization• Synchronized with input packet(bit-level accuracy)• Constant pulse energy and polarization

Fig. 2. Operating functions of the packet-level optical timing-pulse (clock-pulse) generator (OCG).

generates one optical pulse per packet. The generated
optical pulse is accurately synchronized with theleading pulse of the input packet. We also describe aself-routing scheme for 40-Gbit/s burst optical packets [5], [6], which is constructed using the self-SPC
system as an interface for 40-Gbit/s optical labelswith a CMOS label processing circuit.
2. Packet-level optical timing-pulse (clock-pulse)
generator (OCG)
Figure 2 shows a schematic diagram of the operating functions required for an OCG. An OCG must
detect burst optical packets and generate one opticalpulse per packet. The output optical pulse must be
accurately synchronized with the input packet [4],[7], [8]. Some fluctuation of the intensity and polarization of input packets is inevitable. Asynchronous
packets with arbitrary lengths should be detected [4],[7]-[9] and output pulses should have constant energy and polarization. The most important requirement
is that the optical-pulse generation must be on a packet-by-packet basis, but the generated optical pulse
must have bit-level timing accuracy.
Figure 3 shows the optoelectronic circuit we have32

developed as the OCG [4]. It is composed of an optical-to-electrical (OE) converter, which generates asingle electrical pulse synchronized with an input
packet, and an EO converter, which is a gainswitched*2 distributed feedback laser diode (DFBLD) driven by the OE converter. The OE converter
consists of i) a photoconductive sample-and-hold(S/H) circuit, which generates an electrical step signal by detecting the leading pulse of the input packet,ii) an optical receiver, which provides the S/H circuitwith set and reset signals, and iii) a pulse generating
circuit, which transforms the step signal into the single output electrical pulse. The S/H circuit consists ofa metal-semiconductor-metal photodetector (MSMPD), a hold capacitor, a high electron mobility transistor (HEMT) buffer circuit, and a resetting transistor. The optical receiver has a rather slow response
time, so that it can generate an output signal in
response to the leading ‘1’ bit of an incoming optical*2 Gain switching is a popular method of driving a semiconductor
LD to generate a short optical pulse. Using the phenomenon ofrelaxation oscillation induced in an abruptly switched-on LD, we
can obtain an optical pulse with a duration shorter than that of thedriving current-pulse from the driven (gain-switched) LD.

NTT Technical Review

Selected Papers

Optical line
Electrical line
Step

OE
Photoconductive
S/H circuit

Reset

Set

OEIC

Input optical packets

HEMT
buffer

MSMPD
Leading pulse
Opticalreceiver

Set
(OFF)

(

Resettingtransistor
NormallyON

Ch

Pulse generating
circuitQAND_ τ
Q 10 Gbit/s)

EO
Outputoptical pulses

OEIC: optoelectronic integrated circuit
Ch: hold capacitor

Pulse

Gain-switching

Pulse

10 ps

DFBLD

≈150 ps

Fig. 3. Optoelectronic circuit for the OCG.

packet and keeps generating it for the whole packet
duration without responding to any ‘0’ bits includedin the packet. Thus, it generates one rectangular electrical signal per incoming packet. (An IP (Internet
protocol) packet never has more than eight continuous ‘0’ bits. Thus, an optical receiver having a
response time longer than a few bytes can operatecorrectly as mentioned above, provided the guardband length is longer than the response time so thatthe output signal disappears during the guard band.)
When there is no incoming optical packet, the S/Hcircuit is always reset. (The resetting transistor is normally on and short-circuits the hold capacitor.) Whena packet arrives, the optical receiver receives a split
input packet a moment earlier than the S/H circuit
does, and this sets the S/H circuit. (The electrical signal generated by the optical receiver switches off theresetting transistor to make it possible for the holdcapacitor to hold a charge.) Then, the split identicalpacket with a slight delay launched into the S/H circuit induces a charge in the MSM-PD by its leading
pulse and the S/H circuit generates a step-like electrical signal by holding the charge in the hold capacitor.
The step signal is then transformed to an electricalpulse about 150 ps wide by the pulse generating circuit, which detects the rising edge of the S/H output.
Vol. 2 No. 7 July 2004

Here, the pulse width is adjusted by an electricaldelay (τ) in the pulse generating circuit so that it issuitable for the gain switching of the following DFBLD. By inputting the electrical pulse to the DFB-LD,
a single optical pulse having a width of about 10 ps
and constant pulse energy and polarization can beobtained from the gain-switched LD. When the packet leaves, the set signal sent from the optical receiverdisappears during the guard band before a subsequent
input packet arrives, resulting in leaking of the heldcharge (resetting of the step signal). The OCG thus
outputs a single optical pulse synchronized with theleading pulse of the input packet. It can accept burst
optical packets that do not contain any preamble bits
for clock extraction because it detects only the leading pulse. For the same reason, it can operate regardless of the input packet bit rate. In addition, it can
detect arbitrarily long asynchronous packets because
the set/reset function is controlled by the input packet itself.
Figure 4(a) shows the waveforms of electricalpulses obtained from the pulse generating circuit(after the pulses were amplified to 6.5 Vpp to drive the
DFB-LD). The measurement was done using 1.543µm optical pulses with a 2-ps full width at half maximum (FWHM). The parameter was input optical33

Selected Papers

135
15

Relative delay (ps)Output (V)± 1 ps0.52 pJ
to10.30 pJ

–0.3

0.26 pJ–0.2

0.18 pJ

–0.1

130

10
125
5
0.5 pJ

FWHM (ps)Attenuated by 26 dB

120
0± 2 ps

0
0

100

200
300
Time (ps)

400

500

1
Input pulse energy (pJ)

(a)

10

115

(b)

Fig. 4. (a) Waveforms of electrical pulses generated in the OCG (parameter: input optical-pulse energy) and (b) relative
delay and FWHM dependencies on input pulse energy.

34

Beforecompression
FWHM: 9.2 ps

Aftercompression
FWHM: 3.0 ps

Auto correlation

pulse energy. A unique 130-ps FWHM single electrical-pulse waveform having the same voltage swing
and timing was obtained when the energy of the leading pulse of the input packet was larger than 0.5 pJ.
(The pulse width was adjusted to match the DFB-LD
used in the experiment.) The waveform also exhibited fast rise and fall times of less than 50 ps due to theuse of 10-Gbit/s GaAs integrated circuits (ICs) for thepulse generating circuit (Fig. 3), which is fast enoughto be applied to the gain switching of the DFB-LD.
Figure 4(b) shows the input pulse energy versus output relative delay and FWHM of the generated electrical pulses. The variation of the delay was within ±2
ps when the input energy was larger than 0.5 pJ, evenwhen the input energy was changed by more than 10
dB. The fluctuation of the pulse width was within ±1
ps. Figure 5 shows auto-correlation traces measured
for the output optical pulses from the OCG. As shownby the dashed line, a 9.2-ps FWHM (assuming
Gaussian waveforms) was achieved, which can beapplied to 40-Gbit/s systems as described in section
3. The solid line shows the trace for output pulses towhich linear chirp compensation was applied forpulse compression. In this case, a 3-ps FWHM wasachieved, which can be applied to systems operating
at higher bit rates.
The OCG can thus generate one optical pulse perincoming optical packet. The generated optical pulse
has bit-level timing accuracy within ±2 ps. The OCG
features high input sensitivity and tolerance for input
polarization and power as well as constant output
polarization and power. These features come from theOEO configuration. It can detect arbitrarily long

–30

–20

–10

0

10

20

30

Delay (ps)Fig. 5. Auto-correlation traces of optical pulses
generated by the OCG.

asynchronous burst optical packets with no preamble
bits because its operation is based on leading pulse
detection and because the set/reset function is controlled by the input packet itself.
3. 40-Gbit/s optical packet self-routing
In this section, we describe self-routing of 40Gbit/s burst optical packets [5], for which the selfSPC system is used as an interface for 16-bit serialbit optical labels with a CMOS label recognition circuit. Figure 6 shows the experimental setup. Each of
the 1.543-µm, 2-ps-FWHM optical pulses launchedfrom a passively mode-locked fiber-laser with a repNTT Technical Review

Selected Papers

Optical line
1×4
optical switch

Electrical line
40-Gbit/s 16-bit
input optical packets

16-bitmultiplexer
Opticalpulse
sourceOutputpackets

H

A

H

L

L

H

B
B
A
Packet rate: 42 MHz

B

A

L

Self-SPC system

2-chcontrolsignals
PD array andlimiting amps

OCG
Controlpulse

All-optical
SPC

Label
recognition
circuit(CMOS-FPGA)

16 channels of parallel
LVTTL signals

Fig. 6. Setup for 40-Gbit/s 16-bit label recognition and 1×4 self-routing.

etition rate of 21 MHz was split into two and thenconverted into two different 16-bit optical packets A(1001011011010010) and B (1000111001110001)
using PLC-based multiplexers (PLC: planar lightwave circuit). The bit separation in the two packets
was 25 ps (corresponding to 40 Gbit/s). These packets were combined to create an input packet stream
consisting of the two alternating packets at a packet
rate of about 42 MHz. In the experiment, we assigned
all 16 bits in each packet to the label and assumed an
empty payload. The packet stream was split into two,with one launched into the self-SPC system for label
recognition and the other into a 1×4 routing switch.
The self-SPC system consisted of the OCG [4]described in section 2 and a 40-Gbit/s 16-ch all-optical SPC [2], [3]. The OCG generates a 10-ps opticalpulse synchronized with the input packet. The generated optical pulse has well-defined polarization as
well as constant timing and energy, making it very
suitable as a control pulse (pump pulse) of the alloptical SPC.
The 16 parallel output signals from the self-SPC
system were converted to low-voltage transistor-transistor-logic (LVTTL) electrical signals (3.3 V) using
a 16-ch PD array and limiting amplifiers with
Vol. 2 No. 7 July 2004

response bandwidth of 155 MHz. They were theninput to a CMOS label recognition circuit made witha field programmable gate array (FPGA). Figure 7
shows the functions of the CMOS circuit operated
with the self-SPC system. The circuit checks the
input 16-ch signals against a programmable routing
table encapsulated in the circuit and generates 2-ch
LVTTL signals for control of the packet forwarding
according to the result. The control signal has an
NRZ-like waveform, which is held until a subsequent
input packet arrives, and is switched quickly enough(in about 3 ns) to allow a short guard band between
packets (NRZ: non-return-to-zero). The 2-ch control
signals are then input to the 1×4 routing switch,which consists of three 1×2 LiNbO3 switches in a
two-stage configuration.
Figure 8 shows a photograph of a fabricated 40Gbit/s 16-bit optical-label recognition module. It
consists of the all-optical SPC, the PD and limiting
amplifier arrays, and the CMOS label recognition circuit. These components are mounted on a printed circuit board that is 15 cm × 8 cm. The module has two
optical input ports: one for the 40-Gbit/s optical signal to be converted to parallel signals and the otherfor the control pulse (pump pulse). The module also35

Selected Papers

Input
serial-bit
optical label

Latch

CMOS circuit
SelfSPC

Refer

OutputOutputport #A

1

Forwardingcontrol
signals

Control signals
Ch. 1
Ch. 2
High

High

B

3

Low

High

C

2

High

Low

•

•

•

•

•

•

•

•

Routing table
Rewritable
PC

Fig. 7. Functions of CMOS circuit operated using the self-SPC system.

Label recognition
circuit(CMOS-FPGA)

All-optical SPC
PLC

LOTOS

2-ch
control signals

PD arrayLimiting amplifier array(hidden inside)

Board size:
15 cm × 8 cm
Control pulse
Signal pulses

Fig. 8. 40-Gbit/s 16-bit optical-label recognition module.

has two electrical output ports that output the 2-ch
forwarding control signals. Using the module, theOCG, and the 1×4 optical switch, we performed aself-routing experiment. Figures 9(a), (b), and (c)show the input packet stream, 2-ch forwarding control signals, and output packets from the 1×4 switch,
respectively. When the routing table was set to produce the 2-ch control signals of HH and LH (H: high,
L: low) for packets A and B, respectively (setting (i)),
36

we obtained the correct control signals (left side ofFig. 9(b)), and packets A and B were successfully
self-routed to the appropriate ports (ports 1 and 3) of
the four output ports, respectively (left side of Fig.
9(c)). Furthermore, when the routing table was
rewritten by an external computer to produce LH and
HL for packets A and B, respectively (setting (ii)), theoutput ports of packets A and B were correctly
changed to ports 3 and 2, respectively (right side of
NTT Technical Review

Selected Papers

Setting (i)
(a)

A

B

A

Setting (ii)
A

B

B

A

B

(b)
Ch. 1

Ch. 2

(c)
Port 1

A

A
1001011011010010

Port 3B

25 ps/div

Port 2
B

B

A

B

A

1001011011010010

Port 4
Time (10 ns/div)

Time (10 ns/div)

Fig. 9. Results of 40-Gbit/s optical packet self-routing.
(a) Input packets, (b) control signals, (c) output packets.

Figs. 9(b) and (c)). We thus experimentally confirmed that the CMOS circuit recognized the 16-bitlabel for each incoming 40-Gbit/s burst optical packet, generated control signals matched to the routing
table, and forwarded the packets to the correct output
ports. The processing time (from label input to control signal output) of the CMOS circuit used here isabout 20 ns. It should be possible to expand the number of addresses in the routing table against which the
input label is checked in one try to more than 1000
without much additional processing time even if acommercially available FPGA is used.

decreases the bit rate of attached 16-bit serial-bit optical labels and thus interfaces them with a CMOS
label recognition circuit. 40-Gbit/s optical packets
were successfully self-routed to the appropriate output ports as a result of correct label recognition ofeach optical packet according to a programmablerouting table. The self-SPC system acts as an interface between high-bit-rate optical packets and electronic circuits that can achieve a wide variety of functions. It is promising for implementing fast intelligent
switching nodes in optical packet-switched networks.
References

4. Conclusion[1]

We have developed a novel packet-level opticaltiming-pulse (clock-pulse) generator (OCG) for self
serial-to-parallel conversion (self-SPC). The OCG
can detect a high-bit-rate arbitrarily long asynchronous burst optical packet with no preamble bits,
regardless of its bit rate, and generate one opticalpulse per packet. The generated optical pulse is accurately synchronized with the leading pulse of the
input packet with timing accuracy within ±2 ps. The
OCG features high input sensitivity and tolerance toinput polarization and power (>10 dB) as well as constant output polarization, power, and delay. We havealso achieved 1×4 self-routing of 40-Gbit/s burst optical packets by using the self-SPC system. The system
Vol. 2 No. 7 July 2004

[2]

[3]

[4]

[5]

[6]

D. J. Blumenthal, B. E. Olsson, G. Rossi, T. E. Dimmick, L. Rau, M.
Masanovic, O. Lavrova, R. Doshi, O. Jerphagnon, J. E. Bowers, V.
Kaman, L. A. Coldren, and J. Barton, “All-Optical Label Swapping
Networks and Technologies,” IEEE J. Lightwave Technol., Vol. 18,
pp. 2058-2075, 2000.
R. Takahashi and H. Suzuki, “1-Tbit/s 16-bit All-Optical Serial-toParallel Conversion Using a Surface-Reflection Optical Switch,”
IEEE Photon. Technol Lett., Vol. 15, pp. 287-289, 2003.
T. Yasui, R. Takahashi, and N. Kondo, “Ultrafast All-optical Serialto-parallel Converter Using a Surface-reflection Optical Switch,”
NTT Technical Review, Vol. 2, No. 7, pp. 23-30, 2004.
T. Nakahara, R. Takahashi, H. Takenouchi, and H. Suzuki, “Optical
Single-Clock-Pulse Generator Using a Photoconductive Sample-andHold Circuit for Processing Ultrafast Asynchronous Optical Packets,”
IEEE Photon. Technol. Lett., Vol. 14, pp. 1623-1625, 2002.
R. Takahashi, T. Nakahara, H. Takenouchi, and H. Suzuki, “40-Gbit/s
Label Recognition and 1×4 Self-Routing Using Self-Serial-to-Parallel Conversion,” IEEE Photon. Technol Lett., Vol. 16, pp. 692-694,
2004.
T. Nakahara, R. Takahashi, and H. Suzuki, “Self-Routing of 100-37

Selected Papers

[7]

[8]

[9]

Gbit/s Optical Packets Using Self Serial-to-Parallel ConversionBased Label Recognition,” IEEE Photon. Technol Lett., Vol. 15, pp.
602-604, 2003.
D. Cotter, J. K. Lucek, M. Shabeer, K. Smith, D. C. Rogers, D. Nesset, and P. Gunning, “Self-routing of 100-Gbit/s packets using 6-bit‘keyword’ address recognition,” Electron. Lett., Vol. 31, pp. 14751476, 1995.
H. J. Lee, H. G. Kim, J. Y. Choi, K. Kim, and J. Lee, “A simple packet-level clock extraction scheme using a terahertz optical asymmetric
demultiplexer,” IEEE Photon. Technol Lett., Vol. 11, pp. 1310-1312,
1999.
G. T. Kanellos, L. Stampoulidis, N. Pleros, T. Houbavlis, D. Tsiokos,
E. Kehayas, H. Avramopoulos, and G. Guekos, “Clock and Data
Recovery Circuit for 10-Gbit/s Asynchronous Optical Packets,” IEEE
Photon. Technol Lett., Vol. 15, pp. 1666-1668, 2003.

Tatsushi Nakahara
Senior Research Engineer, Advanced Optoelectronics Laboratory, NTT Photonics Laboratories.
He received the B.S. and M.S. degrees inapplied physics from the University of Tokyo,
Tokyo in 1988 and 1990, respectively. In 1990,
he joined NTT Opto-electronics (now Photonics)
Laboratories, Kanagawa, Japan, where he wasinitially engaged in research on smart pixels integrating electronic logic circuits with quantumwell modulators or vertical-cavity surface-emitting lasers. Since 1999, he has been engaged inresearch on high-speed optical packet processing
and switching based on optoelectronic circuits.
He is a member of the Optical Society of America and the Japan Society of Applied Physics(JSAP).

Ryo Takahashi
Senior Research Engineer, Advanced Optoelectronics Laboratory, NTT Photonics Laboratories.
He received the B.E., M.E., and D.E. degrees
in electronic engineering from the University ofTokyo, Tokyo, Japan, in 1987, 1989, and 1992,
respectively. In 1992, he joined NTT Opto-electronics Laboratories, Kanagawa, Japan. From1998 to 1999, he was a visiting scholar at the
Ginzton Laboratory, Stanford University, Stanford, CA. Currently, he is engaged in R&D ofultrafast all-optical devices and optical packet
processing technologies for optical packetswitched networks. He is a member of JSAP and
the Institute of Electronics, Information andCommunication Engineers of Japan (IEICE).

Hirokazu Takenouchi
Research Engineer, Advanced Opto-electronics Laboratory, NTT Photonics Laboratories.
He received the B.S. and M.S. degrees in pureand applied sciences from the University ofTokyo, Tokyo in 1992 and 1994, respectively. In
1994, he joined the NTT Opto-electronics (nowPhotonics) Laboratories, Kanagawa, Japan,
where he was initially engaged in research onvertical-cavity surface-emitting lasers. Since
1997, has been engaged in the research on ultrafast optical signal processing by spectral filtering. He is now studying ultrafast optical packet
processing. He is a member of JSAP and IEICE.

38

NTT Technical Review