19-0401; Rev 0; 6/95

Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface____________________________Features♦ 12-Bit Resolution, 1/2LSB Linearity♦ Single +5V Operation♦ Software-Selectable Input Ranges:±VREF, ±VREF/2, 0V to VREF, 0V to VREF/2♦ Internal 4.096V or External Reference♦ Fault-Protected Input Multiplexer (±16.5V)♦ 8 Analog Input Channels♦ 6µs Conversion Time, 100ksps Sampling Rate
♦ Internal or External Acquisition Control♦ Two Power-Down Modes♦ Internal or External Clock________________________Applications
Industrial-Control Systems
Robotics
Data-Acquisition Systems
Automatic Testing Systems
Medical Instruments
Telecommunications

Functional Diagram appears at end of data sheet.

______________Ordering InformationPART

TEMP. RANGE

PIN-PACKAGE

MAX199ACNI

0°C to +70°C

28 Narrow Plastic DIP

MAX199BCNI
0°C to +70°C
28 Narrow Plastic DIP
MAX199ACWI
0°C to +70°C
28 Wide SO
MAX199BCWI
0°C to +70°C
28 Wide SO
MAX199ACAI
0°C to +70°C
28 SSOP
MAX199BCAI
0°C to +70°C
28 SSOP
MAX199BC/D
0°C to +70°C
Dice*
Ordering Information continued at end of data sheet.
*Dice are specified at TA = +25°C, DC parameters only.

__________________Pin Configuration
TOP VIEW
CLK 1

28 DGND

CS 2

27 V DDWR 3

26 REFRD 4

25 REFADJ

HBEN 5SHDN 6

MAX199D7 7

24 INT
23 CH722 CH6D6 8

21 CH5D5 9

20 CH4D4 10

19 CH3

D3/D11 11

18 CH2

D2/D10 12

17 CH1

D1/D9 1316 CH0D0/D8 1415 AGND

DIP/SO/SSOP/Ceramic SB________________________________________________________________ Maxim Integrated Products

Call toll free 1-800-722-8266 for free samples or literature.

1

MAX199_______________General Description
The MAX199 multi-range, 12-bit data-acquisition system(DAS) requires only a single +5V supply for operation,and converts analog signals up to ±4V at its inputs. Thissystem provides eight analog input channels that are
independently software programmable for a variety ofranges: ±VREF, ±VREF/2, 0V to VREF, or 0V to VREF/2.
This increases effective dynamic range to 14 bits, andprovides the user flexibility to interface 4mA-to-20mA,±12V, and ±15V powered sensors to a single +5V system. In addition, the converter is fault-protected to±16.5V; a fault condition on any channel will not affectthe conversion result of the selected channel. Other features include a 5MHz bandwidth track/hold, 100ksps
throughput rate, internal/external clock, internal/externalacquisition control, 8+4 parallel interface, and operation
with an internal 4.096V or external reference.
A hardware SHDN pin and two programmable powerdown modes (STBYPD, FULLPD) provide low-current
shutdown between conversions. In STBYPD mode, thereference buffer remains active, eliminating start-up
delays.
The MAX199 employs a standard microprocessor (µP)
interface. Its three-state data I/O interface is configured
to operate with 8-bit data buses, and data-access andbus-release timing specifications are compatible withmost popular µPs. All logic inputs and outputs are
TTL/CMOS compatible.
The MAX199 is available in 28-pin DIP, wide SO, SSOP,
and ceramic SB packages.
For a different combination of input ranges (±10V, ±5V,
0V to 10V, 0V to 5V), see the MAX197 data sheet. For 12bit bus interfaces, see the MAX196/MAX198 data sheet.

MAX199

Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface
ABSOLUTE MAXIMUM RATINGSVDD to AGND............................................................-0.3V to +7V
AGND to DGND.....................................................-0.3V to +0.3V
REF to AGND..............................................-0.3V to (VDD + 0.3V)
REFADJ to AGND.......................................-0.3V to (VDD + 0.3V)
Digital Inputs to DGND...............................-0.3V to (VDD + 0.3V)
Digital Outputs to DGND ............................-0.3V to (VDD + 0.3V)
CH0–CH7 to AGND ..........................................................±16.5V
Continuous Power Dissipation (TA = +70°C)
Narrow Plastic DIP (derate 14.29mW/°C above +70°C)....1143mW

Wide SO (derate 12.50mW/°C above +70°C)..............1000mW
SSOP (derate 9.52mW/°C above +70°C) ......................762mW
Narrow Ceramic SB (derate 20.00mW/°C above +70°C)..1600mW
Operating Temperature Ranges
MAX199_C_ _ .......................................................0°C to +70°C
MAX199_E_ _.....................................................-40°C to +85°C
MAX199_M_ _ ..................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.)
PARAMETERSYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

ACCURACY (Note 1)
Resolution

12

Integral Nonlinearity

INL

Differential Nonlinearity

DNL

±1/2

MAX199B±1±1

UnipolarOffset Error
BipolarChannel-to-Channel Offset
Error Matching

MAX199A±3

MAX199B±5

MAX199A±5

MAX199B±0.1

Bipolar±0.5

Gain Error(Note 2)
Bipolar

LSB
LSB

LSB

±10

Unipolar

UnipolarGain Temperature Coefficient(Note 2)

Bits

MAX199A

LSB

MAX199A±7

MAX199B±10

MAX199A±7

MAX199B

LSB±10Unipolar3

Bipolar5ppm/°CDYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±4.096Vp-p, fSAMPLE = 100ksps)
Signal-to-Noise + Distortion Ratio

SINAD

Total Harmonic Distortion

THD

Spurious-Free Dynamic Range

SFDR

MAX199A

70

MAX199B69

Up to the 5th harmonic

dB
-85

80

-78

dB
dB

Channel-to-Channel Crosstalk

50kHz, VIN = ±4V (Note 3)

-86

dB

Aperture Delay

External CLK mode/external acquisition control

15

ns

<50

ps

Aperture Jitter

External CLK mode/external acquisition
controlInternal CLK mode/internal acquisition
control (Note 4)

10

ns

2

_______________________________________________________________________________________

Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.)
PARAMETERSYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

3

µs

ANALOG INPUT
Track/Hold Acquisition Time

fCLK = 2.0MHz

Small-Signal Bandwidth-3dB rolloff±VREF range

5±VREF/2 range

2.5

0V to VREF range

2.5

0V to VREF/2 range
Unipolar (see Table 2)
Input Voltage Range
Bipolar (see Table 2)

1.25
0

VREF

0

VREF/2

-VREF

VREF

-VREF/2

BipolarInput Dynamic Resistance
Input CapacitanceV

VREF/2

Unipolar range
Input Current

MHz

0.1

10

±VREF range

-1200

10

±VREF/2 range

-600

10

Unipolar

40

Bipolar10(Note 5)

µA
MΩ
kΩ

40

pF

4.116

V

INTERNAL REFERENCEREF Output Voltage
REF Output Tempco(Contact Maxim Applications
for guaranteed temperaturedrift specifications)

VREF
TC VREFTA = +25°C

4.076

4.096

MAX199_C±15

MAX199_E±30

MAX199_M±40

Output Short-Circuit Current

30
0mA to 0.5mA output current (Note 6)

Load Regulation

7.5

0mA to 0.1mA output current (Note 6)

0.8

Capacitive Bypass at REF

4.7

REFADJ Output Voltage

2.465

REFADJ Adjustment Range

ppm/°CWith recommended circuit (Figure 1)

Buffer Voltage Gain

mA
mV
µF

2.500

2.535

V

±1.5

%

1.6384V/V

REFERENCE INPUT (Buffer disabled, reference input applied to REF pin)
Input Voltage Range
Input Current

Input Resistance
REFADJ Threshold for
Buffer Disable

2.4

4.18

V

Normal, or STANDBY
power-down mode
VREF = 4.18V
FULL power-down
modeNormal, or STANDBY power-down mode

10kΩ

FULL power-down mode

5

MΩ

400
µA
1

VDD - 50mVV_______________________________________________________________________________________

3

MAX199ELECTRICAL CHARACTERISTICS (continued)

MAX199

Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.)
PARAMETERSYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

5.25

V

POWER REQUIREMENTS
Supply Voltage

VDD

4.75
Normal mode, bipolar ranges

Supply Current

Power-Supply Rejection Ratio(Note 8)

IDD

PSRR

18

Normal mode, unipolar ranges

610Standby power-down (STBYPD)

700

850

Full power-down mode (FULLPD) (Note 7)

60

120
±1/2

External reference = 4.096V±1/2

Internal reference

mA
µA
LSB

TIMINGInternal Clock Frequency

fCLK

External Clock Frequency Range

fCLK
tACQI

Acquisition TimetACQE
Conversion TimetCONV

CCLK = 100pF

1.25

1.56

0.1
Internal acquisition

External CLK

3.0Internal CLK

3.0

External acquisition (Note 9)
After FULLPD or STBYPD

Bandgap Reference
Start-Up Time

6.0

Internal CLK, CCLK = 100pF

6.0

5.0

7.7

100

200

To 0.1mV, REF
CREF = 4.7µF
bypass capacitor
CREF = 33µF
fully discharged
DIGITAL INPUTS (D7–D0, CLK, RD, WR, CS, HBEN, SHDN) (Note 11)
VINH
VINL

Input Leakage Current

IIN

Input Capacitance

CIN

µs

µs
ksps
µs

8

Reference Buffer Settling

Input Low Voltage

10.0

62

Power-up (Note 10)

Input High Voltage

MHz

5

External CLK

Internal CLK, CCLK = 100pF

MHz

2.0

3.0

External CLK

Throughput Rate

2.00

ms

60
2.4

V
0.8

V

VIN = 0V or VDD

±10

µA

(Note 5)

15

pF

0.4

V

15

pF

DIGITAL OUTPUTS (D7–D4, D3/D11, D2/D10, D1/D9, D0/D8, INT)
Output Low Voltage

VOL

VDD = 4.75V, ISINK = 1.6mA

Output High Voltage

VOH

VDD = 4.75V, ISOURCE = 1mA

Three-State Output Capacitance

COUT(Note 5)

4

VDD - 1_______________________________________________________________________________________V

Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA = TMIN to TMAX, unless otherwise noted.)
PARAMETERSYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CS Pulse Width

tCS

80

ns

WR Pulse Width

tWR

80

ns

CS to WR Setup Time

tCSWS

0

ns

CS to WR Hold Time

tCSWH

0

ns

CS to RD Setup Time

tCSRS

0

ns

CS to RD Hold Time

tCSRH

0

CLK to WR Setup Time

tCWS

100

ns

CLK to WR Hold Time

tCWH

50

ns

Data Valid to WR Setup

tDS

60

Data Valid to WR HoldtDH0RD Low to Output Data ValidtDO

Figure 2, CL = 100pF (Note 12)

120

ns

HBEN High or HBEN Low to
Output ValidtDO1

Figure 2, CL = 100pF (Note 12)

120

ns

RD High to Output DisabletTR(Note 13)70

ns

RD Low to INT High Delay

tINT1

120

ns

ns

ns
ns

Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Rejection test. Tested for the ±4.096V input range.
Note 2: External reference: VREF = 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
Note 3: Ground “on” channel; sine wave applied to all “off” channels.
Note 4: Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5: Guaranteed by design. Not tested.
Note 6: Use static loads only.
Note 7: Tested using internal reference.
Note 8: PSRR measured at full-scale. VDD = 4.75V to 5.25V.
Note 9: External acquisition timing: starts at rising edge of WR with control bit ACQMOD = low; ends at rising edge of WR with
ACQMOD = high.
Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with tR = tF = 5ns from a voltage level of 0.8V to 2.4V.
Note 12: tDO and tDO1 are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V
or 2.4V.
Note 13: tTR is defined as the time required for the data lines to change by 0.5V.

Note 1:_______________________________________________________________________________________

5

MAX199TIMING CHARACTERISTICS

__________________________________________Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
EFFECTIVE NUMBER OF BITS
vs. INPUT FREQUENCYFFT PLOTfTONE = 10kHz
fSAMPLE = 100kHz

-20

0.050
0

-40
-60
-80

-0.050-100-0.100-120-0.150
2000

1000

3000

4000

0

25

50

FREQUENCY (kHz)DIGITAL CODE

MAX199-4

PSRR (LSB)

VREF (V)1

10

VDD = 5V ±0.25V

4.090

100

120Hz

0
100Hz
-0.2

-0.4

REF

5 25 45 65 85 105 125
TEMPERATURE (°C)

-0.6
-70 -50 -30 -10 10 30 50 70 90 110 130
TEMPERATURE (°C)

CHANNEL-TO-CHANNELOFFSET-ERROR MATCHING vs. TEMPERATURE

CHANNEL-TO-CHANNEL
GAIN-ERROR MATCHING vs. TEMPERATURE

4.080-55 -35 -15

0.33
CHANNEL-TO-CHANNEL
GAIN-ERROR MATCHING (LSB)

MAX199-6

0.20
CHANNEL-TO-CHANNELOFFSET-ERROR MATCHING (LSB)

10.0

0.4

0.2

AV = 1.6384+2.5V
INTERNAL
REFERENCE
REFADJ

10.5

POWER-SUPPLY REJECTION RATIO
vs. TEMPERATURE

4.095

4.085

11.0

INPUT FREQUENCY (kHz)REFERENCE OUTPUT VOLTAGE (VREF)
vs. TEMPERATURE
4.100

11.5

0.18

0.16

0.14

0.12

0.10
-70 -50 -30 -10 10 30 50 70 90 110 130
TEMPERATURE (°C)

MAX199-7

0

6

fSAMPLE = 100kHz

MAX199-5

AMPLITUDE (dB)

0.150
0.100

12.0
EFFECTIVE NUMBER OF BITS

0.200

MAX199-2

0

MAX199-1

0.250

MAX199-3

INTEGRAL NONLINEARITY
vs. DIGITAL CODEINTEGRAL NONLINEARITY (LSB)

MAX199Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface

0.32
0.31
0.30
0.29
0.28
0.27
-70 -50 -30 -10 10 30 50 70 90 110 130
TEMPERATURE (°C)_______________________________________________________________________________________

Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface
PIN

NAME

FUNCTION

1

CLK

Clock Input. In external clock mode, drive CLK with a TTL/CMOS compatible clock. In internal clock mode,
place a capacitor (CCLK) from this pin to ground to set the internal clock frequency; fCLK = 1.56MHz typicalwith CCLK = 100pF.

2CS

Chip Select, active low.

3

WR

When CS is low, in the internal acquisition mode, a rising edge on WR latches in configuration data and starts an
acquisition plus a conversion cycle. When CS is low, in the external acquisition mode, the first rising edge on
WR starts an acquisition and a second rising edge on WR ends acquisition and starts a conversion cycle.

4

RD

When CS is low, a falling edge on RD will enable a read operation on the data bus.

5

HBEN

Used to multiplex the 12-bit conversion result. When high, the 4 MSBs are multiplexed on the data bus;when low, the 8 LSBs are available on the bus.

6

SHDN

Shutdown. Puts the device into full power-down (FULLPD) mode when pulled low.

7–10

D7–D4

Three-State Digital I/O

11

D3/D11Three-State Digital I/O. D3 output (HBEN = low), D11 output (HBEN = high).

12

D2/D10Three-State Digital I/O. D2 output (HBEN = low), D10 output (HBEN = high).

13

D1/D9

Three-State Digital I/O. D1 output (HBEN = low), D9 output (HBEN = high).

14

D0/D8

Three-State Digital I/O. D0 output (HBEN = low), D8 output (HBEN = high). D0 = LSB.

15

AGND

16–23

CH0–CH7

24

INT

25

REFADJ

26

REF

Reference Buffer Output / ADC Reference Input. In internal reference mode, the reference buffer provides a
4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internalbuffer by pulling REFADJ to VDD.

27

VDD

+5V Supply. Bypass with 0.1µF capacitor to AGND.

28

DGND

Digital Ground

Analog Ground
Analog Input Channels
INT goes low when conversion is complete and output data is ready.
Bandgap Voltage-Reference Output / External Adjust Pin. Bypass with a 0.01µF capacitor to AGND.
Connect to VDD when using an external reference at the REF pin.

+5V

3k

+5V

MAX199

510k
100k

DOUT

REFADJ

DOUT
3k

CLOAD

CLOAD

0.01µF
24ka) High-Z to VOH and VOL to VOH

Figure 1. Reference-Adjust Circuitb) High-Z to VOL and VOH to VOL

Figure 2. Load Circuits for Enable Time_______________________________________________________________________________________

7

MAX199______________________________________________________________Pin Description

MAX199

Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface_______________Detailed Description
Converter Operation
The MAX199, a multi-range, fault-tolerant ADC, uses
successive approximation and internal input track/hold(T/H) circuitry to convert an analog signal to a 12-bit
digital output. The parallel-output format provides easyinterface to microprocessors (µPs). Figure 3 shows the
MAX199 in its simplest operational configuration.

Analog-Input Track/Hold
In the internal acquisition control mode (control bit D5
set to 0), the T/H enters its tracking mode on WR’s rising edge, and enters its hold mode when the internally
timed (6 clock cycles) acquisition interval ends. In bipolar mode, a low-impedance input source, which settles
in less than 1.5µs, is required to maintain conversion
accuracy at the maximum conversion rate.
When configured for unipolar mode, the input does notneed to be driven from a low-impedance source. The
acquisition time (tAZ) is a function of the source output
resistance (RS), the channel input resistance (RIN), andthe T/H capacitance.
Acquisition time is calculated by:
For 0V to VREF: tAZ = 9 x (RS + RIN) x 16pF
For 0V to VREF/2: tAZ = 9 x (RS + RIN) x 32pF

1

CLK

DGND

where RIN = 7kΩ, and tAZ is never less than 2µs (0V to
VREF range) or 3µs (0V to VREF/2 range).
In the external acquisition control mode (D5 = 1), theT/H enters its tracking mode on the first WR rising edge
and enters its hold mode when it detects the second WR
rising edge with D5 = 0. See the External Acquisition
section.

Input Bandwidth
The ADC’s input tracking circuitry has a 5MHz smallsignal bandwidth. When using the internal acquisitionmode with an external clock frequency of 2MHz, a
100ksps throughput rate can be achieved. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended (MAX274/MAX275 continuous-time filters).

Input Range and Protection
Figure 4 shows the equivalent input circuit. The MAX199
can be programmed for input ranges of ±VREF, ±VREF/2,
0V to VREF, or 0V to VREF/2 by setting the appropriate
control bits (D3, D4) in the control byte (see Tables 1 and
2). When an external reference is applied at REFADJ, thevoltage at REF is given by VREF = 1.6384 x VREFADJ (2.4V< VREF < 4.18V).

28

BIPOLAR

100pF
2µP
CONTROL
INPUTS

3
4
5
6
7
8
9
10

REF

WR

REFADJ

RD
HBEN
SHDN
D7
D6
D5
D4

11 D3/D11
12
D2/D10
13
D1/D9
14 D0/D8µP DATA BUS

Figure 3. Operational Diagram
8+5V

MAX199 VDD 27
CS

INT
CH7
CH6
CH5
CH4
CH3
CH2

24

0.1µF

UNIPOLAR
4.7µF

5.12k

OUTPUT STATUS

23

CHOLD
S2

21

T/H
OUT

ON

20
19

OFF

5.12k
CH_

22

ANALOGINPUTS18

CH1 1716
CH0
AGND+4.096V

26
25

VOLTAGEREFERENCE

S1

S3
HOLD

TRACK
TRACK

15
S1 = BIPOLAR/UNIPOLAR SWITCHS2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH

Figure 4. Equivalent Input Circuit_______________________________________________________________________________________

S4

HOLD

Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface

Output Data Format
The output data format is binary in unipolar mode andtwos-complement binary in bipolar mode. When reading the output data, CS and RD must be low. When
HBEN is low, the lower eight bits are read. When HBEN
is high, the upper four MSBs are available and the output data bits D4–D7 are either set low (in unipolarmode) or set to the value of the MSB (in bipolar mode)(Table 5).

Digital Interface
Input data (control byte) and output data are multiplexed
on a three-state parallel interface. This parallel I/O caneasily be interfaced with a µP. CS, WR, and RD control
the write and read operations. CS is the standard chipselect signal, which enables a µP to address the MAX199
as an I/O port. When high, it disables the WR and RD
inputs and forces the interface into a high-Z state.

Table 1. Control-Byte Format
D7 (MSB)

D6

D5

D4

D3

D2

D1

D0 (LSB)

PD1

PD0

ACQMOD

RNG

BIP

A2

A1

A0

BIT

NAME

7, 6

PD1, PD0

These two bits select the clock and power-down modes (Table 3).

DESCRIPTION

5ACQMOD0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition

4

RNG

Selects the full-scale voltage magnitude at the input (Table 2).

3

BIP

Selects unipolar or bipolar conversion mode (Table 2).

2, 1, 0A2, A1, A0

These are address bits for the input mux to select the “on” channel (Table 4).

Table 2. Range and Polarity Selection
BIP

RNG

Table 3. Clock and Power-Down Selection
PD1 PD0

INPUT RANGE (V)00

0 to VREF/2

0

1

0 to VREF

1

0±VREF/2

1

1

±VREF

DEVICE MODE

00

Normal Operation / External Clock Mode01

Normal Operation / Internal Clock Mode

10Standby Power-Down (STBYPD); clock mode
is unaffected11Full Power-Down (FULLPD); clock mode isunaffected

Table 4. Channel Selection
A2

A1

A0

CH0

0

0

0

∗

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

CH1

CH2

CH3

CH4

CH5

CH6

CH7

∗
∗
∗
∗
∗
∗
∗

_______________________________________________________________________________________

9

MAX199Input Format
The control byte is latched into the device, on pins
D7–D0, during a write cycle. Table 1 shows the controlbyte format.

The input channels are overvoltage protected to±16.5V. This protection is active even if the device is in
power-down mode.
Even with VDD = 0V, the input resistive network provides
current-limiting that adequately protects the device.

MAX199

Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface
Writing a new control byte during the conversion cycle
will abort the conversion in progress and start a newacquisition interval.

Table 5. Data-Bus Output
PIN

HBEN = LOW

D0

B0 (LSB)

B8

HBEN = HIGH

D1

B1

B9

D2

B2

B10

D3

B3

B11 (MSB)

D4B4B11 (BIP = 1) / 0 (BIP = 0)D5B5

B11 (BIP = 1) / 0 (BIP = 0)

D6B6

B11 (BIP = 1) / 0 (BIP = 0)D7B7

B11 (BIP = 1) / 0 (BIP = 0)

Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this six-clock-cycle acquisition interval (3µs with
fCLK = 2MHz) ends. See Figure 5.

How to Start a Conversion
Conversions are initiated with a write operation, which
selects the mux channel and configures the MAX199 foreither unipolar or bipolar input range. A write pulse (WR+ CS) can either start an acquisition interval or initiate a
combined acquisition plus conversion. The samplinginterval occurs at the end of the acquisition interval.
The ACQMOD bit in the input control byte offers two
options for acquiring the signal: internal or external.
The conversion period lasts for 12 clock cycles in either
internal or external clock or acquisition mode.

tCS
CS

tCSRH

tCSRS
tACQI

tCSWS

External Acquisition
Use the external acquisition timing mode for precise control of the sampling aperture and/or independent control ofacquisition and conversion times. The user controls acquisition and start-of-conversion with two separate write pulses. The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0, terminates acquisition and starts conversion on WR’s rising edge (Figure 6).
However, if the second control byte contains ACQMOD =1, an indefinite acquisition interval is restarted.
The address bits for the input mux must have the samevalues on the first and second write pulses. Powerdown mode bits (PD0, PD1) can assume new values on
the second write pulse (see Power-Down Mode).

tCSWH

tWR

tCONV

WR

tDH

tDS
CONTROL
BYTE

D7–D0

ACQMOD ="0"

tINT1

INT

RD

HBEN

tD0
HIGH-Z
DOUT

tTR

tD01
HIGH / LOW
BYTE VALIDHIGH / LOW
BYTE VALID

Figure 5. Conversion Timing Using Internal Acquisition Mode10______________________________________________________________________________________

HIGH-ZMulti-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface
MAX199

tCSRS

tCS

tCSRH

CS

tCSWS

tACQI
tCSHW

tWR

tCONV

WR

tDH

tDS
D7–D0

CONTROLBYTE
ACQMOD = "1"

CONTROLBYTE
ACQMOD = "0"

tINT1

INT

RD

HBEN

tD01

tD0
HIGH-ZHIGH / LOW
BYTE VALID

DOUT

tTR
HIGH / LOW
BYTE VALID

HIGH-Z

Figure 6. Conversion Timing Using External Acquisition Mode

Clock Modes
The MAX199 operates with either an internal or an
external clock. Control bits (D6, D7) select either internal or external clock mode. Once the desired clockmode is selected, changing these bits to program
power-down will not affect the clock mode. In eachmode, internal or external acquisition can be used. At
power-up, the MAX199 defaults to external clock mode.

Internal Clock Mode
Select internal clock mode to free the µP from theburden of running the SAR conversion clock. To selectthis mode, write the control byte with D7 = 0 and D6 = 1.
A 100pF capacitor between the CLK pin and groundsets this frequency to 1.56MHz nominal. Figure 7

shows a linear relationship between the internal clock
period and the value of the external capacitor used.

INTERNAL CLOCK PERIOD (ns)How to Read a Conversion
A standard interrupt signal, INT, is provided to allow thedevice to flag the µP when the conversion has ended
and a valid result is available. INT goes low when theconversion is complete and the output data is ready(Figures 5 and 6). It returns high on the first read cycle
or if a new control byte is written.

2000

1500

1000

500

0
0

50

100 150 200

250 300 350

CLOCK PIN CAPACITANCE (pF)

Figure 7. Internal Clock Period vs. Clock Pin Capacitance______________________________________________________________________________________

11

MAX199

Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface
External Clock Mode
Select external clock mode by writing the control byte
with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR
timing relationships in internal and external acquisition
modes, with an external clock. A 100kHz to 2.0MHz

external clock with 45% to 55% duty cycle is requiredfor proper operation. Operating at clock frequencies
lower than 100kHz will cause a voltage droop acrossthe hold capacitor, and subsequently degrade performance.

ACQUISITION STARTSACQUISITION ENDSCONVERSION STARTSACQUISITION ENDSCONVERSION STARTS

CLK

tCWS
WR
ACQMOD = "0"tCWHWR GOES HIGH WHEN CLK IS HIGHACQUISITION STARTS

CLKWR
ACQMOD = "0"

WR GOES HIGH WHEN CLK IS LOW

Figure 8a. External Clock and WR Timing (Internal Acquisition Mode)ACQUISITION ENDSACQUISITION STARTSCONVERSION STARTS

CLK

tCWS

tDH
WR

ACQMOD = "0"

ACQMOD = "1"
WR GOES HIGH WHEN CLK IS HIGHACQUISITION STARTSACQUISITION ENDSCONVERSION STARTS

CLK

tCWH

tDH
WR
ACQMOD = "1"

WR GOES HIGH WHEN CLK IS LOW

ACQMOD = "0"Figure 8b. External Clock and WR Timing (External Acquisition Mode)12______________________________________________________________________________________

Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface
Power-On Reset
At power-up, the internal power-supply circuitry sets INT
high and puts the device in normal operation / external
clock mode. This state is selected to keep the internal
clock from loading the external clock driver when thepart is used in external clock mode.

Internal or External Reference
The MAX199 can operate with either an internal or externalreference. An external reference can be connected toeither the REF pin or to the REFADJ pin (Figure 9).
To use the REF input directly, disable the internal buffer
by tying REFADJ to VDD. Using the REFADJ input eliminates the need to buffer the reference externally.
When the reference is applied at REFADJ, bypass
REFADJ with a 0.01µF capacitor to AGND.
The REFADJ internal buffer gain is trimmed to 1.6384 toprovide 4.096V at the REF pin from a 2.5V reference.

external reference at REF must be able to deliver
400µA DC load currents, and must have an output
impedance of 10Ω or less. If the reference has higher
input impedance or is noisy, bypass it close to the REF
pin with a 4.7µF capacitor to AGND.
With an external reference voltage of less than 4.096V
at the REF pin or less than 2.5V at the REFADJ pin, theincrease in the ratio of the RMS noise to the LSB value(FS / 4096) results in performance degradation (loss ofeffective bits).

REF

VDD

AV = 1.638

Internal Reference
The internally trimmed 2.50V reference is gained
through the REFADJ buffer to provide 4.096V at REF.
Bypass the REF pin with a 4.7µF capacitor to AGND
and the REFADJ pin with a 0.01µF capacitor to AGND.
The internal reference voltage is adjustable to ±1.5%(±65 LSBs) with the reference-adjust circuit of Figure 1.

REF

MAX1992.5V

Figure 9b. External Reference at REF

REF

REFADJ

4.7µF
CREF

REFADJ25
0.01µF

2.5V

Figure 9a. Internal Reference

26 4.096V

MAX199AV = 1.638

AV = 1.638

10k

25

10k

26 4.096V
4.7µF
CREF

4.096V
4.7µF
CREF

REFADJ

External Reference
At REF and REFADJ, the input impedance is a minimum of 10kΩ for DC currents. During conversions, an

26

MAX19925

2.5V
0.01µF

10k

2.5V

Figure 9c. The external reference at REFADJ overdrives theinternal reference.

______________________________________________________________________________________

13

MAX199__________Applications Information

MAX199

Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface
Power-Down Mode
To save power, you can put the converter into lowcurrent shutdown mode between conversions. Two
programmable power-down modes are available, in
addition to a hardware shutdown. Select STBYPD or
FULLPD by programming PD0 and PD1 in the input
control byte. When software power-down is asserted, it
becomes effective only after the end of conversion. In all
power-down modes, the interface remains active andconversion results may be read. Input overvoltage protection is active in all power-down modes. The device
returns to normal operation on the first WR falling edge
during a write operation.
For hardware-controlled (FULLPD) power-down, pull
the SHDN pin low. When hardware shutdown is asserted, it becomes effective immediately and the conversion is aborted.

Choosing Power-Down Modes
The bandgap reference and reference buffer remain
active in STBYPD mode, maintaining the voltage on the
4.7µF capacitor at the REF pin. This is a “DC” state that
does not degrade after power-down of any duration.
Therefore, you can use any sampling rate with thismode, without regard to start-up delays.

However, in FULLPD mode, only the bandgap reference is active. Connect a 33µF capacitor between REF
and AGND to maintain the reference voltage between
conversion and to reduce transients when the buffer isenabled and disabled. Throughput rates down to 1ksps
can be achieved without allotting extra acquisition time
for reference recovery prior to conversion. This allows aconversion to begin immediately after power-downends. If the discharge of the REF capacitor during
FULLPD exceeds the desired limits for accuracy (lessthan a fraction of an LSB), run a STBYPD power-downcycle prior to starting conversions. Take into accountthat the reference buffer recharges the bypass capacitor at an 80mV/ms slew rate and add 50µs for settling
time. Throughput rates of 10ksps offer typical supply
currents of 470µA, using the recommended 33µF
capacitor value.

Auto-Shutdown
Selecting STBYPD on every conversion automaticallyshuts the MAX199 down after each conversion without
requiring any start-up time on the next conversion.

OUTPUT CODEOUTPUT CODE
FULL-SCALE
TRANSITION

11... 111FS
1 LSB =
4096

1 LSB =
011... 111
011... 110

11... 110
11... 101000... 001
000... 000
111... 111

00... 011

100... 010

00... 010

100... 001

00... 001

100... 000

00... 000
0

1

2

FS

3
INPUT VOLTAGE (LSB)

Figure 10. Unipolar Transfer Function

14

FS - 3/2 LSB-FS

0V
INPUT VOLTAGE (LSB)

Figure 11. Bipolar Transfer Function______________________________________________________________________________________+FS - 1 LSB

2FS
4096

Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface

Layout, Grounding, and Bypassing
Careful printed circuit board layout is essential for bestsystem performance. For best performance, use aground plane. To reduce crosstalk and noise injection,
keep analog and digital signals separate. Digital
ground lines can run between digital signal lines tominimize interference. Connect analog grounds and
DGND in a star configuration to AGND. For noise-free
operation, ensure the ground return from AGND to the
supply ground is low impedance and as short as possible. Connect the logic grounds directly to the supply
ground. Bypass VDD with 0.1µF and 4.7µF capacitors
to AGND to minimize high- and low-frequency fluctuations. If the supply is excessively noisy, connect a 5Ω
resistor between the supply and V DD , as shown in
Figure 12.

_Ordering Information (continued)
PART

TEMP. RANGE

PIN-PACKAGE

MAX199AENI-40°C to +85°C

28 Narrow Plastic DIP

MAX199BENIMAX199AEWIMAX199BEWIMAX199AEAI
MAX199BEAI
MAX199AMYIMAX199BMYI-40°C to +85°C-40°C to +85°C-40°C to +85°C-40°C to +85°C-40°C to +85°C-55°C to +125°C-55°C to +125°C

28 Narrow Plastic DIP
28 Wide SO
28 Wide SO
28 SSOP
28 SSOP
28 Narrow Ceramic SB**
28 Narrow Ceramic SB**** Contact factory for availability and processing to MIL-STD-883.

___________________Chip Topography
WR CLK
V DD
CS
DGND

V CC
REF

RD
REFADJ
HBEN
INT

SHDN
D7

CH7
0.231"(5.870mm)
SUPPLY

CH6
GND

+5V

CH5
D6

0.1µF

AGND

MAX199

CH3

D3

**
VDD

CH4

D5
D4

4.7µF
R* = 5Ω

DGND

+5V

DGND

DIGITAL
CIRCUITRY* OPTIONAL** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE

CH2
D1
D2

CH0
D0

AGND

CH1

0.144"(3.659mm)

TRANSISTOR COUNT: 2956
SUBSTRATE CONNECTED TO GND

Figure 12. Power-Supply Grounding Connection______________________________________________________________________________________

15

MAX199Transfer Function
Output data coding for the MAX199 is binary in unipolar
mode with 1LSB = (FS / 4096) and twos-complement
binary in bipolar mode with 1LSB = [(2 x |FS|) / 4096].
Code transitions occur halfway between successiveinteger LSB values. Figures 10 and 11 show the
input/output (I/O) transfer functions for unipolar andbipolar operations, respectively.

MAX199

Multi-Range (±4V, ±2V, +4V, +2V),+5V Supply, 12-Bit DAS with 8+4 Bus Interface_________________________________________________________Functional Diagram
REF

CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0

REFADJ

AV =1.638
SIGNAL
CONDITIONINGBLOCK&
OVERVOLTAGE
TOLERANT
MUX

10k

+2.5V
REFERENCE

T/H
CHARGE REDISTRIBUTION
12-BIT DAC

COMP

12
SUCCESSIVEAPPROXIMATIONREGISTER

CLK

CS
WR
RD
SHDN

CLOCK

CONTROL LOGIC&LATCHES

4

8

4

8
MUX

8

8
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE

INT

HBEN

MAX199

VDD
AGND
DGND

D0–D7
8-BIT DATA BUS

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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600© 1995 Maxim Integrated Products

Printed USA

is a registered trademark of Maxim Integrated Products.