PROBLEMS ON THE NEW COMPUTER CONTROL SYSTEM FOR THE MAIN RING MAGNET POWER SUPPLY OF 12 GeV PS

SOMESATORU MATSUMOTO, HITOSHI BABA, TSUYOSHI SUENO, KATSUHIKO MIKAWA, KEN'ICHI MUTO AND MAKOTO TODA
National Laboratory for High Energy Physics,
Oho-machi, Tsukuba-gun, Ibaraki-ken, 305, Japan.

On these pattern generations including Qf and Qd
tracking, the bending magnet power supply (BPS) has thecormost predominant contribution to complicatedrelations among power apparatus and analog and digital
Therefore, we describe some problems
control system.
on the BPS to be overcome for these optimized patternoperations.

ABSTRACT
Replacing plan of the H-350 system is reported.
theIn the whole analog and digital hybrid system,
control makes the new computer system resposible forthe periodic control (a kind of adaptive control) andthe analog loops resposible for real time feedback
control.
The distributed system consists of three systems
The main carry out theof the HD-68000 family.
periodic and the other control tasks and background
Input- and outputjobs under supervision of UNIX.
controller engage in running data log to seven sets ofADC and in pattern data distribution to fifteen sets of
DAC in every 1.67ms locked in six phase ac power line.
The systems will have been installed at the end of1960.

SURVEY OF THE RUNNING SYSTEM
Pattern Generation and Periodic Control

INTRODUCTION
Since 1979, the control computer system of dual H350 1 has been working reliably on routine operations of
the main ring magnet power supply (MPS)2 for the 12 GeV
machine. On the other hand, the trial accelerations ofpolarized and light ion have been taken on the main
But usedring at several times for the last year.
ofbecause
optimum,
not always
werepatterns
restrictions by high power apparatus, by analog and bydigital control system.
We will make clear on these restrictions anddescribe a plan replacing to the new computer control
systemremove some of them under minimum

toments to analog control system and to power
And we discuss on the remained problems.

improve-apparatus.

REQUIREMENTS FOR PATTERNSFor polarized proton, patterns of bending
1.
field B have the time gradient B as large as possible
The final beam energy take in from 500
within Bmax.
MeV to 12 GeV.
2. For light ions, B patterns have to have multisteps coresponding to beam energy to rebunch the beam
Figure 1 shows a schematicfor RF-acceleration 3
pattern of B.

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Fig. 1. A Proposed Bending Field Pattern forLight Ion Beam Acceleration.

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The bending magnet power supply (BPS) consists ofThese
six groups of 12 pulsed thyristor converter.
groups have power ratings designed for fixed operation
For a desired current pulse, the H-350 systemmodes.
calculate the applied voltages to the magnet by every
group based on the mode. These voltages are regarded as
the reference patterns named Vc, Vi, V23-1, V23-2, V233, and V23-4. These patterns have data in every 10 ms.
Vc group has a constant value except the magnet reset
time interval from beam-ejection-end to next-beaminjection-start with 0 value for bypassing and gives
beam injection field in the magnet by adding Vi groupof constant inverter voltage. The Vi group compensatesohmic voltage drop between from injection inverter up
The V23-j ( j=1 to 4 )to ejection coverter voltage.
have the same pattern ammong the \123 group.
These patterns do not generate the desired current
pulse because of neglecting transfer function of defilters and of minor automatic voltage regulator (MA\IR)
Periodic control algorithmof every SCR bridge.
on steadycorrection voltage patterncalculates
current deviations from a desired current pattern andadds it to Vi pattern. These functions give underdamping characteristics at transient regions of acceleration start and end. The periodic control4 could notcompensate these oscillations within a several times ofby correction data interporlated in a quater
ripplesstep between data of every 10ms control clock, though
the corrections are effectively improved comparing withthe case of single 10ms step.
In the smoothing interval from acceleration toejection, \123-j groups are controlled serially in groupunit, independently on their pattern data, by thetiming parameters for the purpose of reducing reactive
power within controllable range of reactive powercompensator (TQC)5.
The similar timing controls have applied to theOn continuous periodic
magnet reset time interval.
control, the steady current deviation on the reset
start region induces oscillations near-by flat top end
By program maintenance or developby the algorithm.
ments, it might be possible for the oscillation to beBut, the periodic control has carried out
suppressed.
only for the optimization of the reference voltage
patterns at a new pattern generation and modificationor for drift corrections to automatic current regulator(ACR) deviation by manual control.
voltagetheAs results of timing controls,patterns are not effective in the interval and foranalysis to effective factors to be difficult by very
complicated correlations among ac power system and deirregular
Thesetransient.
includingcomponents
controls would be attributed to underestimation ofsaturation in self-inductance of the bending magnet andto lack of flexibility and processing power of the cpusystem. However, as for routine 12 GeV pulse patterns,
optimizations have been done in sufficient level toaccelerate stably and reliably the beams. But theseoptimizations needed long time to converge.

2 85 0 A

and memory elements by LSI technology, reliability andperformances of their composed system have been improved up to almost the same level as a mini-computerfor process control, like H-350, which constructed by
Developments of periphediscrete or SSI components.
rals have made reasonable circumstances on software
works compared with the H-350 system in display, external storage memory and data transfer or communication
These advances suggest for the costs replacingetc..
the system to a new powerful microcomputer systems toreduce reasonably, comparing with reconstruction of theH-350 system with developing the system design insoftware and in hardware to solve problems on theflexible pattern operations.

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System Design Principle
Since most of all the problems would be related on
the computer control, the system design is the mostimportant to construct the minimum system in hard- andsoft-wares but the maximum in cost performance to ourThe analog
whole analog and digital hybrid system.
control system have to play in main role on real time
But, it is reasonable for the digitalprocesses.
system to be responsible for fast feedforward pattern
to slow but reliable feedback control
control andloop, periodic control part of ACR. Real time part ofACR transfers to the analog loop with not-expensive
cost.
isStructure of the control computer systemdesirable for these loops to be constructed reasonably
by multi-cpu. The main parts of the digital system areconstructed from a 16-bit-microprocessor and theirfamily LSI components on a industrial standard bus andsupported by universal operating system as the softwarebus and standard peripherals, commercially available.
Under these circmtst'l.nces, high level language andpowerful utilities sur~ort development and maintenanceof soft-wares for the flexible pattern control withThe main cpu system controls
reasonable total cost.
for the slow loops and supports the other tasks and
For the fast loop, other cpu systems
background jobs.
exclusively in tasks of which application
engageprograms would be described by assembler.

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A Typical Thyristor current
Fig. 2
Bridge on a Routine 12GeV operation.

of8Extinction of Thyristor Current
One of these correlations is extinction of SCR
current, Iscr, in pulse operation of magnets fed byserially connected multi-stage bridges. The extinction
would occur at down-step voltage for SCR current to be
suppressed by discharge current of capacitors in low
Theif Iscr less than holding current.
pass filter,
extincted element is suffered from accumulated overvoltage by the other bridges connected serially ancttransient voltage oscillations and will break down
simultaneously.
Figure 2 gives typical SCR current Ibi of Vi-bridgerectified by 3-phase diode bridge on a routine 12 GeV
The maximum current suppression would beoperation.
estimated at about 400 A on the reset time interval.
The similar current suppression may occur at the end ofacceleration in non-optimized patterns, especially inThis is theadjusting the pattern by timing control.
reason for the restriction of flat top current. To
guard the element, these transient over-voltages arebypassed by CR-networks, although it is impossible tooperate by the patterns which induce a extinction. The
networks have been installed last February.

H-V90/5 SystemTheFigure 3 shows a layout of the new system.
system consists of the main cpu system HIDIC-V90/5 andinput and output controller HISEC-04M. The distributed
three systems are not hierarchical in software, butrather independent even in assembler level between thestructure
because theand the controller,
mainThesupported only by upper version of H-V90 series.
main components are LSI of HD-68000 cpu (second source
These have assembled onof MC-68000) and the family.
boards as function module given in rectangular block inFig. 3.
The system has DRAM of 2MB, standard peripherals(i.e. 5"-20MB hard disc and 8"-2MB floppy disc drive,
two stations of CRT terminal, and two printers) and twoloops of local area network based on IEEE 802 (LAN 1
These resources supervised by the main OSand 2).
compatible with UNIX.
The system is responsible for almost of all controls except fast real time parts undertaken by input
and output controllers and to developments and mainteThe applicationnances of control programs and data.
programs will be descibed in the system language C andThe main tasks are the operation controls
FORTRAN 77.
including start-stop and status monitoring, correction
pattern calculation of the periodic control and fineForadjustments of pattern data for on-line control.
supporting tasks, the system works on pattern generations, processing of pattern and operation data, control program development, and background processes.

Software Development
The character of the system is in a real time
multi-tasking process controller under the standard OS
The OS does not support control program
named PMS II.
Indevelopment and maintenance except object level.
the cpu, these works are supported at assembler level
only by the other OS-NPMS I at off-line, but both OSs
are never able to implement at the same time. Usually,
like the running control programs, application control
programs are developed by assembler and high level
FORTRAN like language PCL on an upper version system of
the same family, H-500 or H-700, or on a main framewith special tools for the HIDIC-family. But we havenot any supporting system. Therefore, the maintenancesof control programs were forced to be confined patchlevel. In pattern generation, desired pattern parameter
input by paper tape and the data are checked merely toSince the last March all of the systemprinted data.
family have been manufactured only by a claim as thesupply parts for maintenance, including peripherals. In
the system may not be supported invery near future,hard- and soft-ware.
In recent developments of microcomputer families

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04M:___________l ______________ F--~~~j~~~~~<,''_______________ !''!. -------------- ~Block Diagram of theA3.
Fig.
Distributed Control Computer System.

For a flexible pattern control,
control of BPS bridges especially thoseof V23-groups have to be flexible. But
the time interval of flat top would berather determined by the thermal rating
ifof bypass thyristors in V23-bridges,
the flat top currnt was larger than 2000
A within power rating of bridges. These
have two elements of the same rating tobridge arm thyristors.
In the transient regions of pulse
theoperation, phase lock control in
power line is important to estimate
steady deviations to pattern data for
But there are
the periodic control.
several times larger systematic differnces between phase lock control by upand down-ward zero cross pulse thanIn the limit
those of voltage ripples.
of memory space of controllers, realtime control pattern have to choose theAs a result,one by up- or down-pulse.
jitter between the main ring and thebooster PS will be 20ms at the maximum,
twice times of the H-350.
These problems would not be fatal
to practical operations of PS.

ACKNOWLEDGEMENTS
New

The authors would like to express their glatitude prof.
Michio Nakano (Tokyo Inst. Tech.) for his discussions
They would like toand advices on the system.
describe their thanks to the director prof. T. Kamei
for his advices and (inancial support under very severe
circumstances on the budget. They are much indebted toprof. M. Kondoh for his discussions on the project andto many colleagues of PS group for their discussions
and collaborations.

The system communicates exclusively the input andthe output controller by LAN 2 because of reliability
data transfer. The network transfers pattern or logged
data between the main and output or input controller by
the speed 20 kB/sec corresponding to a quarter of theone of H-350. But, on a fine adjust practical responsewould not be so slow comparing with every clocktransfer of the H-350 because of block transfer and theexclusive path, though the data increased six times aslarge as those of the H-350.

REFERENCES
1. T. Kubo et al., IEEE NS-26 N0.4, 3322 (1979).
2. KEK ANNUAL REPORT 1973, 1974 and 1975.
3. M. Kondoh & K. Muto, IEEE NS-30 N0.4, 2045 (1983).
4. T. Inoue et al., Contl. Sci. & Tech. for Prog. ofSoc. (IFAC 82) vol. 6, 3137, Pergamon Press (1982).
5. S. Matsumoto et al., IEEE NS-30 No.4, 2932 (1983).

Controller SystemThe output controller schedules nine sets of 16bit-DAC for BPS, that is, six of them serve as
reference pattern voltage of the converter group, twoas the dynamic filter detector and one as the reference
Figure 4 shows shematic relation
for the analog ACR.
among these hybrid loops for one group 12-pulse converter of BPS and Qf- and Qd-PS. And also 3x2 sets for Qf
The system outputs these pattern data to theand Qd.
fifteen sets of DAC in every clock of 1.67ms. But thedata convert in synchronizing to the zero-cross pulse
Bridge control signals ofof six phase ac power line.
by-pass and gate suppress are distributed to working
bridges by the system.
The input controller reads data of seven sets ofThree sets serve for the DCCT current
16-bi t-ADC ·.
signal and the others for the de voltage applied to theB-, Qf- and Qd- magnet in the same sampling clock of
The clock synchronizes zero-crossthe DAC system.
pulse perfectly, but has a constant lag of about 100
microsec. At the edge of clock pulse, ADCs have ceased
their sampling because they had started synchronizing
to the zero cross pulse. These de voltage data serve asa new periodic control loop for the magnet voltages.

Fig. 4. A Schematic Diagram of the improved
Hybrid Control Loops for a 12-Pulsed Converter.

DISCUSSIONS
After the project, we shall have still some problems by the power and control system.

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