A Content Addressable Memory Using
Magnetic Domain Wall Motion Cells
R. Nebashi1, N. Sakimura1, Y. Tsuji1, S. Fukami1,
H. Honjo1, S. Saito1, S. Miura1, N. Ishiwata1,K. Kinoshita1, T. Hanyu2, T. Endoh2, N. Kasai2, H. Ohno2,and T. Sugibayashi1
1 NEC Corporation, Japan
2 Tohoku University, Japan

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Outline• Introduction• Demonstration of Spintronics-based CAM Test Chip
– Multi-free layer domain wall (DW) motion cell
– Shared write transistor• Future Challenge– Multi-context Spin CAM– Domain wall motion in CoFeB• SummarySymposia on VLSI Technology and Circuits

Slide 1

Motivation
Logic

CAM

MemoryNon-volatilestorage element(MTJ: magnetic tunnel junction)
Data are retained even ina power off stateNon-volatile Spintronics SoC with power gating• Reduced leakage current• Small power penalty for state retention and reload
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Slide 2

Overview of Spintronics Core on SoC
Magnetic F/F
p1

CLK

Logic

Q

p2

PON
p2

p2

This work
CAM

p2

Dp1

p1
p2

MemoryWCK

CICC 2008

Speed~ 500 MHz~ 200 MHz~ 33 MHz

Capacity

SmallMediumLarge

5T2MTJ

2T1MTJ

9T8MTJ/8bit

VLSI Cir. 2006

VLSI Cir. 2006

Cell•
•

A-SSCC 2007

Different MTJ cell is needed for different layer in memory hierarchy
However, the best MTJ cell for CAM is not existed
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Slide 3

Content Addressable Memory (CAM)
1000

10

110

Non-volatile test chipin this work Future challenge
1(Multi-context)
Matchlocation
CAMcellSearch Data { 0, 1, 0 }Design target
Fast search and Compact

Search delay (ns)

Search line

Match line

10SRAM-based CAM

100Spin TCAM [1]100010010Cell Size (F2)
[1] S. Matsunaga et al.,
APEX, 2, 023004, 2009.

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Slide 4

Basic Concept of Spin CAM

Search line

Match line

Spin CAM Cell

1000

1011Search result

Comparison
circuitbased onSRAM

Load0

Non-volatilememory cellWrite• Once data are transferred from non-volatile memory tocomparison circuit, fast search is executable
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Slide 5

2Tr-1MTJ Cell for High Speed R/W Operation
2Tr-1MTJ cell
BL/BL RBL

ReadMTJ

250MHz (ASSCC 2007)

WLWrite32Mbit (ISSCC 2009)• High speed operations were demonstrated by using 3terminal element with magnetic field writing.
3-terminal magnetic element

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Slide 6

Magnetic Domain Wall Motion Cell“0” statew
Pinning layer
Free layer
Fixedregion

Data
regionFixedregion

DW motion
electron“1” state

Domain wall (DW)
DW motion
electron
VLSI 2009• Low writing current (200 µA @ w = 90 nm) was obtained
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Slide 7

Multi-free Layer Domain Wall Motion Cell
Sense layer“0” state

P1

MTJ

Tunnelbarrier

MTJfor read

Referencelayer

DataregionPinninglayer
Freelayer

P2

Data
regionMagneticstray field“1” state
MTJ

P3

= P1
P2

P3

Data
regionMagneticstray field• Fast read operation and low writing current were obtained
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Slide 8

Multi-free layer Domain Wall Motion Cell
250 nmSense layer
M5

V4

MTJ
Tunnel barrier
Reference layer

Thin free layer (Co/Ni)

Pinning layeron thin free layerV4

Pinning layeron thin free layer

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Slide 9Spin CAM with Shared Write Transistor
CommonWord line
Pull down

Shared cell
M13

Comparison circuit
Non-volatilememory cell 1

R1

R1b

M121

Word line 1
Non-volatilememory cell 0

R0
M120

R0b

IBLb

Comparison circuit

CAM cell 0 CAM cell 1

M14

Word line 0•3-terminal elements(R1 and R1b) sharewrite transistor (M13,M121)•CAM cells sharewrite transistor (M13)
Cell area reduced

Write current Iw (0)Bit line/Bit line

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Slide 10

Spin CAM with Shared Write Transistor
CommonWord line
Pull down

Shared cell
M13

Comparison circuit
Non-volatilememory cell 1

R1

R1b

M121

Word line 1
Non-volatilememory cell 0

R0
M120

R0b

IBLb

Comparison circuit

CAM cell 0 CAM cell 1

M14

Word line 0•3-terminal elements(R1 and R1b) sharewrite transistor (M13,M121)•CAM cells sharewrite transistor (M13)
Cell area reduced

Write current Iw (1)Bit line/Bit line

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Slide 11

M5

DM2
M11

M9M3M4Bit line

Db M6
IsbIsR

M8RbM12

M14/Search line

Match line/LoadM1
M10

M7
Search line

Comparison circuit

Load Operation of Spin CAM

M13

Shared cell
/Bit line

Memory cell
Word line

Pull down

Commonword line

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Slide 12

Search Operation of Spin CAM

M6/Search line n

M5

M8

Search line n

M7/Search line 0

Search line 0

Match Line

Match line
sense amp.

( search operation )1. Search line precharged to Gnd
2. Match line precharged to Vdd
3. Match line evaluate• Search operation is executed in same way as
conventional SRAM-based CAM• Search speed is comparable to SRAM-based CAM
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Slide 13

16-Kbit Spin-CAM Test Chip

16 Kb CAM

330 µmMatch line sense amp.

Row decoder

460 µmColumn decoder

Technology

90 nm CMOS
+ DW Process

Cell size

6.6 um2/bit

Organization 128 word x 128 bit
Supply voltage

1.0 V

Searchcycle time

5 ns

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Slide 14

Measured 5-ns Search Waveform
CLKCLK
Miss cycle Macth cycle Miss cycle Macth cycle

Vdd = 1.0 V
T=27oCQ
MatchT(match)~ 4 nsT(1-bit miss)~ 5 nsMiss

MatchMissTcycle = 5 ns
Time (sec)
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Slide 15

Vdd (V)

Measured Search Cycle Time
1.7
1.6
1.5
1.4
1.3
Fail1.2
1.1
1
0.9
0.8

T=27oC

Pass

56

Fail789Tcycle (ns)Symposia on VLSI Technology and Circuits

Slide 16

Outline• Introduction• Demonstration of Spintronics-based CAM Test Chip
– Multi-free layer domain wall (DW) motion cell
– Shared write transistor• Future Challenge– Multi-context Spin CAM– Domain wall motion in CoFeB• SummarySymposia on VLSI Technology and Circuits

Slide 17

Basic Concept of Multi-context CAM
Multi context CAM Cell

Match line
01

Search result

Search line

Comparison
circuitset01

1

Non-volatilememory cell

Load
set1Write• Non-volatile memory cells share comparison
circuitcell efficiency improves
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Slide 18

Cell area / bit normalized bySRAM based CAM cell area

Reduced Area of Multi-context CAM
1.51~ 25% area reduction
1 set x 40.54 set x 1002 4 6 8 10
Number of context sets

Comparisoncircuit
Non-volatilememory cell• A 25% reduction in effective cell area was estimated withthe CAM compared to an SRAM based CAM
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Slide 19

Search Operation of Multi-context CAM
Set 0 is active

Set 000

Search line

1Fast contextswitching

10Set 1

Match01

Set 1 is active

Set 00010
Set 1100Match
1011111010Search Data { 0, 1 }Search Data { 1, 0 }• Fast context switching• Context switching cause increased overhead in power and delay
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Slide 20

Application Example : Translation Look-aside Buffer
Process ID
PID_H

Virtual Address
VA_H

PID_L

Time domain
pre-classification•Low switching frequency•Sets associated with PID

Set3
Set2
Set1
Set0

VA_L

PID_L = 11
PID_L = 10
PID_L = 01
PID_L = 00

PID_H

VA_H

PA_H

PID_H

VA_H

PA_H

PID_H

VA_H

PA_H

Small load overhead from MTJ

Multi-context Spin CAM
Avoid “cold start” with small areaoverhead

Physical AddressPA_H

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PA_LSlide 21

CoFeB

DW motion
electron

RHall ( a. u. )Domain Wall Motion in CoFeB

050 100 150

Write current (μA)
S. Fukami , Intermag 2011, GC-02.

• Domain wall moves with ~ 50 µA current in CoFeB• Future challenge is optimization and integration
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Slide 22

Summary• 16-Kb Spin CAM test chip
– 5-ns search operation• Multi-free layer domain wall (DW) cell– Fast read operation and small writing current• 3-terminal device with shared write transistor– 6.6-µm2/bit cell area

• Multi-context Spin CAM– 25 % effective cell area reduction comparable to SRAMbased CAM• Domain wall motion in CoFeB– Domain wall moves with ~ 50 µA current
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Slide 23