5th international Conference on Superconductivity and Magnetism
April 24 – 30, 2016, Fethiye, Turkey

Spintronics Nano-Devices for VLSIs
Hideo Ohno1,2,3,4
1 Laboratory for Nanoelectronics and Spintronics, Res. Inst. of Electrical Communication, Tohoku University
2 Center for Spintronics Integrated Systems, Tohoku University
3 Center for Innovative Integrated Electronic Systems, Tohoku University
4 WPI-AIMR, Tohoku University

Collaborators: S. Fukami, C. Zhang, T. Anekawa, H. Sato, S. Kanai,
F. Matsukura, S. Ikeda, T. Hanyu and T. EndohWork supported in part by the FIRST Program from JSPS, ImPACT from JST,and by the R & D for Next-Generation Information Technology of MEXT

http://www.csis.tohoku.ac.jp/

Logic VLSIs
研究開発の目的
Mobile phone

IOT

IOT

Digital camera

Videocamera

Audio-Video
Equipment

TV$227 billion（$16 billion）

Gamemachine(Internet of Things)$1300 billion（$111 billion）

Logic LSIs

ComputerCommunication
Equipment

DigitalRadiography$141 billion（$20 billion）

RocketTomographic
equipment$273 billion（$23 billion）

Car

Artificial
satellite

Computer

Medical, Health
Equipment$1773 billion（$340 billion）

Aircraftserver$552 billion（$37 billion）

AutomobileCarelectronics

Tablet PC

Information source:
Hitachi Techno-Information
Services, Ltd
WW Market in 2012
PC
(JPN Market in 2012)
IDC Japan
http://www.idcjapan.co.jp/Pres
Network s/Current/20150205Apr.html(also 20141118/Apr. html)

Smart CitySpace
Aircraft

SmartCommunity$338 billion（$14 billion）$104 billion（$15 billion）

Electricity
storage
Electric generation
Renewable energy

Challenges VLSI Technology FaceMPU Power Consumption（W）

Power Consumption

Interconnection Delay
Interconnect wiring

Active power

Logic

MemorySignal bottleneck

Standby powerby leakage current

Year

Logic

MemoryLeakage Current

Toward Nonvolatile CMOS VLSIPresent Logic VLSIs

Volatile memory

Logic

Logic VLSIs withSpintronics Memory
Non‐volatile memory
Logic

Si sub.

Spintronics Logic‐
in‐Memory VLSIs

Leakage current

Non‐volatile memory
Zero standby power of memory bynon‐volatile spintronics devices

Low Power Consumption

Logic
Si sub.
Logic‐in‐Memory Architecture by fusion
between logic circuits and MTJs （Reduction ofdevice number and interconnect wiring length）

Low Power, High Performance, Low Cost

Si sub.

Nonvolatile Memories

Features of non‐volatilefor memory device

FlashFRAMSpinDevice

Access Speed
Non destructive ReadWrite Endurance
Scalability
Operation Voltage

△○○△○
○

×○
×△△
△

○
○
○

Magnetic Tunnel
Junction (MTJ)
Low resistance “０”High resistance “１”Nonvolatile Memories
Comparison: ReRAM, PCRAM, and STT‐MRAM (Spin)
ReRAM

PCRAM

STT-MRAM

Program Current

10-4A

10-4A

10-5A

Program Time

50ns

100ns

0.5ns-10ns

Read Time

< 5ns

< 5ns

< 5ns

Retention

10yrs

10yrs

10yrs

Endurance

106

109 - 1012

1015
6

Magnetic Tunnel Junction
RAP  RP2P 2
Tunnel MagnetoResistance (TMR) 
RP1 P2
ParallelEE

Half Metal
Antiparallel

Ferromagnet 1

Insulator

Ferromagnet 2

Room temperature TMR: Miyazaki and Tezuka (Tohoku U.), J. Mag. Mag. Mat. 1995 and Moodera et al. Phys. Rev. Lett. 1995.

Required Properties
 High tunnel magnetoresistance ratio > 100%
 High thermal stability  = E/kBT > 60
 Unlimited endurance Low switching current
 High speed read and write High temperature tolerance ~ 400 oC
 Scalability 40 nm → 20 nm → 10 nm

TMR ratio of MTJs700

トンネル磁気抵抗比TMR ratio (%) (%)

600500

MgO‐barrier
Tohoku‐HitachiAIST

400300CanonANELVA & AISTAISTIBMAIST

200
100604%(1144%@5K)

AlOx‐barrier@ RT01994 1996 1998 2000 2002 2004 2006 2008 2010year
年Ic0 and =E/kBT
in-planeE  K eff V2 e *IC 0 
K eff VB gParallel

Antiparallel

E
100

K eff

80

Thermal fluctuation

70

kBT

60
E/kT

*K eff

90

50
40
30
20

α=0.0165

α=0.033

10
0
0

0.01

0.02

0.03
α

0.04

0.05

Ic0=50uA
Ic0=100uA
Ic0=200uA

Ic0 and =E/kBT
perpendicular

ParallelE  K eff V2 e
IC 0 K eff VB gEK eff  K eff

Parallel

Antiparallel

Antiparallel

E

Thermal fluctuation

kBT

Thermal fluctuationE  K shape  K crystalline VE

kBTComparison of MTJs (early 2010)

Type

Stack structure
(nm)

Size
(nm)

MR
(%)

RA(Ωμm2)

JC0(MA/cm2)

IC0(μA)∆=E/kBTIC0/∆Ta (oC)

Ref.

i-MTJ

CoFeB(2)/Ru(0.65)/CoF
eB(1.8) SyF

100x200>130~10

2~400

65

~6.2

300350J. Hayakawa et al., IEEE
T-Magn., 44, 1962
(2008)

p-MTJ

L10FePt(10)/Fe(t)/Mg(0.4)/
MgO(1.5)/L10-FePt(t)Blanket

120

11.8k

---500

M. Yoshizawa et al.,IEEE T-Magn., 44, 2573
(2008)

p-MTJ

L10FePt/CoFeB/MgO(1.5)/
CoFeB/Co based
superlattice-----

H. Yoda et al.,Magnetics Jpn. 5, 184(2010) [in Japanese].

p-MTJ[Co/Pt]CoFeB/CoFe/Mg
OCoFe/CoFeB/TbFeCo----225

K. Yakushiji et al., APEX
3, 053033 (2010)

p-MTJ[CoFe/Pd]/CoFeB/MgO/
CoFeB/[CoFe/Pd]----350(325)

K. Mizunuma et al.,
MMM&INTERMAG2010

p-MTJ

FePt202 SLBlanket
FePt & Co-based
Co/Pt & TbFeCo85-97
Blanket4.4-10100
18.7k
CoFe/Pd 800x800
N(20.2k)(113)
TbFeCo 130 φ ~15
L1L10-alloy
alloy 50-55 φ Fe based L1Fe-based
L1(2)/CoFeB (0.5)
0 --CoFeB (1)/ TbCoFe (3)

4.7

650

107

6.08

-

M. Nakayama et al., APL
103, 07A710 (2008)

-4956

0.88

-

T. Kishi et al., IEDM
2008-9---

H.Yoda et al., Magnetics
Jpn. 5, 184 (2010) [inJapanese].

3.94943

1.14350

S. Ikeda et al.,Nat. Mat.
9 (2010) 721.

p-MTJ
p-MTJ

p-MTJ

(CIPT)(CIPT)(CIPT)

00CoFeB(~1.7)

40 φ

124

18

Perpendicular MgO-CoFeB MTJ
JC0 = 3.8 MA/cm2(IC0 = 48 μA)
E/kBT ~ 40
TMR ratio = 110%
Ta = 350oC
1.6 nm0.9 nm
1.0 nmCo20Fe60B20

interface perpendicularanisotropy

S. Ikeda et al., Nature Mat. 9, 721 (2010)

Perpendicular anisotropy at the CoFeB/MgO interface

K. Nakamura et al., Phys. Rev. B, 81, 220409(R) (2010)

Co‐Fe atoms on O sites in MgO
MgO‐Fe system• High TMR ratio and interfacial
anisotropy are predicted by first‐principles calculation.
W. H. Butler et al., Phys. Rev. B 63, 054416 (2001).
J. Mathon et al., Phys. Rev. B 63, 220403 (2001).
K. Nakamura et al., Phys. Rev. Lett. 102, 187201 (2009).

crystal
[100]
FeCo
FeCo

(100)
Structural analysis for highperformance CoFeB‐MgO
MTJ stack confirmed thatFe(Co) atoms sit on top of Oatoms

(100)
Mg O

MgO
(2.1nm)5Å

crystal[110]

Collaborative work with Prof. Ikuhara‐Lab., Nano Lett. 16, 1530 (2016).

15

Device structure (full stack)Double (SyF)
Recordinglayer

Reference
layer

Ta/Ru
MgO
CoFeB(1.0)
Ta(0.4)
CoFeB(1.6)
MgO
CoFeB(1.0)
Ta(0.3)Co(0.4)[Co(0.4)/Pt(0.4)]x2
Ru(0.4)Co(0.4)[Co(0.4)/Pt(0.4)]x6
Si/SiO2 sub.
16

H. Sato et al., Appl. Phys. Lett. 101, 022414 (2012), IEDM 2013, p. 3.2.1., Appl. Phys. Lett. 105, 062403 (2014).

=E/kBT, IC0 and efficiency
1008060
402000

Perpendicular MTJ
1
E   M S H K  V  K eff V22 eIC 0 
K eff V 
 B g ( )H. Sato et al., Appl. Phys. Lett. 101, 022414 (2012).
H. Sato et al., IEDM 2013, p. 3.2.1.
H. Sato et al. Appl. Phys. Lett. 105, 062403 (2014).

204060Junction diameter (nm)3-1

/IC0 (A )Eg ( )

Series A
Series B

20.008100.012
 = 0.016

03060
Junction diameter (nm)9017

11 nm MTJ (smallest MTJ)
R (k)

300

11 nm
TMR = 107 %

200100-150P

1.0-100-50050
0H (mT)

10015068 = 28IC0 = 13 A

11 nm

0.50.0-8-6-4-202I (A)

4H. Sato et al. Appl. Phys. Lett. 105, 062403 (2014).

Switching current versus switching time
200150P to APIC (A)100
500-50AP to P

-100-150-910-810-710-610-510 (s)-410-310-210

MTJ stack on 300mm wafers
Ta/Ru
MgO(1.0)
CoFeB (1.0)

7000.06000.04000.0Ta(0.4)

Co/Pt based SyF
Reference layer
Ta/Ru/Ta/Pt
Si/SiO2 sub.
300 mm wafer
Ta = 360-400oC for 1hr40300 mm wafer@CIES
150
100
50

3in wafer

3000.02000.01000.040 nm

0.0

H (a.u)RA (m2)

Ta(0.4)200

TMR ratio (%)

CoFeB (1.4)
MgO(1.2, 1.3)
CoFeB (1.2)

R (a.u)5000.030300 mm wafer@CIES

20
103in wafer
00250 300 350 400 450

250 300 350 400 450

Ta (oC)Ta (oC)

S. Ikeda, et al. IEDM2014

Required Properties
 High tunnel magnetoresistance ratio > 100%
 High thermal stability  = E/kBT > 60
 Unlimited endurance Low switching current
 High speed read and write High temperature tolerance ~ 400 oC
 Scalability 40 nm → 20 nm → 10 nm

Required Properties
 High tunnel magnetoresistance ratio > 100%
 High thermal stability  = E/kBT > 60
 Unlimited endurance Low switching current
 High speed read and write High temperature tolerance ~ 400 oC
 Scalability 40 nm → 20 nm

Two and three terminal devices
Domain Wall

two terminal

three terminal(spin-transfer torque)(electric-field)(domain wall)(spin-orbit torque)

Nonvolatile, fast, low voltage and high enduranceAdvantage of 3‐terminal device
Read Write
margin margin

ReadWrite

TDDBV

Readmargin
ReadTDDBVWritemarginWrite• TDDB : Time‐dependent dielectric breakdown• EM : Electromigration

EMVThe third switching scheme
M // z  ‘Type Z’

M // y  ‘Type Y’ Type X may serve as– tool to explore the physics of SOT switching– option for device applications
S. Fukami, HO et al., Nature Nanotech. doi: 10.1038/2016.29 (2016).

M // x  ‘Type X’ Similar mechanism
to Type Z Same material
to Type Y25

Antiferromagnet (AFM) for SOT switching Exchange‐bias Inverse spin Hall effectW. Zhang et al., PRL 113, 196602 (2014).

W. H. Meiklejohn et al., Phys. Rev. 102, 1413 (1956).

FMAFM

S. Fukami, HO et al., Nature Mater. doi: 10.1038/nmat4566 (2016).

26

Film stack & m‐H loop
 tPtMn = 6 nm

 tPtMn = 8 nm

m (Tnm)

1.0

Z

0.5

X

0.0
-0.5

Hbias

-1.0
-60

-40

-20

02040

60 -60-40

 dc/rf magnetron sputtering Post annealing(300C, 2h, 1.2 T)0|Hbias| (mT)

0H (mT)tPtMn = 2, 4, 5, 6,7, 7.5, 8, 8.5 nm

Y-200204060

0H (mT)

201510500246810

tPtMn (nm) Perp easy axis is obtained for all the tPtMn.
 Bias field increases with tPtMn (≥ 7 nm).

S. Fukami, HO et al., Nature Mater. doi: 10.1038/nmat4566 (2016).

27

Switching by current under various HX
No bias (tPtMn = 6 nm)

With bias (tPtMn = 8 nm)

Resistance0HX (mT)-40 -30 -20 -10 0 10 20 30 40-40 -30 -20 -10 0 10 20 30 40

Current (mA)

Current (mA)

 Field‐free switching is observed for exchange‐biased device.
 Switching current density is ~1010 A/m2
… comparable to previous non‐magnet/ferromagnet structures
S. Fukami, HO et al., Nature Mater. doi: 10.1038/nmat4566 (2016).

28

H=0 Switching in Co/Ni‐PtMn

RH

tPtMn = 8 nm

0.02 START

END-40 -30 -20 -10 0

10 20 30 40

ICH (mA)• Spin Hall effect from an antiferromagnet• Switching without magnetic filed
S. Fukami, HO et al., Nature Mater. doi: 10.1038/nmat4566 (2016).

Non‐volatile CMOS VLSIs with spintronics

600MHzNonvolatile TCAM
1Mb Array Three
MTJ/CMOS Latch(Most compact TCAM Terminal DW Cell
(Fastest nonvolatile latch)cell, 4T-2MTJ)(High endurance)(IEDM 2011）（VLSI 2011）(VLSI 2012)

First Auto Design
Tool forSpintronics CMOS
(2011）

Nonvolatile GPU(Largest Scale
Spintronics Random
Logic 500kgate/chip)（ISSCC 2013）

Nonvolatile
microcomputer(First nonvolatile
microcomputer)（ISSCC 2014）

Nonvolatile FPGAwith TSV(First 3D Spintronics
CMOS Processor)（VLSI 2012）

1.5nsec / 1Mbit
Embedded MRAM
(Fastest nonvolatile
1Mbit memory)（VLSI 2013）

Delay×Power×Area Ratios2013 IEICE Electronics Express

2012 Symposium. on VLSI Circuits

2014 IEEE ISSCC

NV‐TCAM

NV‐FPGA

STT‐MRAM

NV‐MPU

Non‐volatile VLSIs for searchengine for big data

Non‐volatile field programmablegate array (FPGA)

Non‐volatile cash memory
embedded in high speed CPU

Non‐volatile microcontroller forbattery‐driven sensor device

3.5mm

3.39mm(delay)x1x100(power)

Spintronics
1 ≦164(area)※in case of used for full text search system

-97%

0.03

4.79mm

1-97%

0.03CMOS‐based

Spintronics

CMOS‐based

1x32

11≦64
21111xx≦
1.5
1.764291(delay)x(power)(area)※ in case of implementation to a typical application(delay)(power)Spintronics(area)※in case of typical cash operation

Power Consumption

0.98mm

14.79mm

1.44mmPower Consumption

0.01

CMOS‐based
1-99%

Power Consumption

Power Consumption

3.1mm

12.05mm2013 Symposium. on VLSI Circuits

10.02

CMOS‐based
1(delay)

-98%

x1x80

(power)Spintronics
1 ≦(area)16431※in case of use in a wireless sensor deviceOn 300 mm wafers

Paradigm Shift of VLSI by Spintronics
High Speed

High power

Storage capacity

Low power