CoFeB/MgO based perpendicular magnetic
tunnel junctions with stepped structure forsymmetrizing different retention times of“0” and “1” information
Katsuya Miura1,2,3
S. Ikeda1,2, M. Yamanouchi1, H. Sato1, H. Yamamoto3,
K. Mizunuma2, H. D. Gan1, J. Hayakawa3, R. Koizumi2,
F. Matsukura1,2, N. Kasai1, and H. Ohno1,2
1Center for Spintronics Integrated Systems, Tohoku University
2Laboratory for Nanoelectronics and Spintronics, ResearchInstitute of Electrical Communication, Tohoku University
3Central Research Laboratory, Hitachi, Ltd.
This work was supported by the FIRST Program of JSPS, and the Tohoku University GCOE Program.

Symposia on VLSI Technology and Circuits

Outline• Background• Issue of perpendicular magnetic tunnel junctions(p-MTJs)• Proposal of p-MTJs with stepped structure• Fabrication and characterization of steppedstructure• Cell area of stepped structure• Proposal of self-alignment process• SummarySlide 1

Background• Applications using MTJs as memory elements.
Logic-in-memory VLSI

STT-RAM

4Mb Array

Parallelto BLParallel
to WL

Logic circuit plane
MTJsS. Matsunaga et al., Appl. Phys. Express 1, 091301 (2006).
R. Takemura et al., VLSI Circ. Dig. pp.84-85, (2009)

Slide 2

Advantages of perpendicular MTJs
• We successfully developed CoFeB/MgO based
perpendicular MTJ (p-MTJ).
Requirements for applications
1. High TMR ratio
2. Low switching current
3. High thermal stability factor
4. Back-end-of-line compatibility

Cr/Au
Ru (5)Ta(5)CoFeB(1.7)
MgO(0.85)
CoFeB(1.0 )Ta(5)Ru(10)
Ta(5)
SiO2/Si sub.

(nm)

In-plane MTJ

p-MTJ

S. Ikeda et al., Nature Mater. 9, 721 (2010).
K. Miura et al., Abstract for 55th MMM conference, HC-02, (2010).

Slide 3Issue for p-MTJs• Different stability between states storing “0” and“1” information.
Bit Information “0”FreeReferenceSNSN

Bit Information “1”Different
polarity=StableNN

The samepolarity=Unstable

S

S

Parallel state
Low resistanceAnti-parallel stateHigh resistanceSlide 4

Reduction of thermal stability• ∆1 increases with increasing diameter of reference
layer.
∆0, 1 = ∆ [1±Hs/Hc0]2
Free“1”∆1Hs

E/kBT“0”∆0ReferencekE/kBTFreeHs
Reference“1”∆1“0”∆0kSlide 5

Objectives• Symmetrizing different retention times of“0” and “1” information.
 Development of p-MTJ with stepped structure
for suppressing reduction of ∆1.
 Verification of advantage of stepped structure
over conventional structure.

Slide 6

Sample preparation• Co20Fe60B20 ferromagnetic layers and MgO tunnel
barrier combination are used.
Ru (5)Ta(5)CoFeB(1.5)
MgO(0.9)
CoFeB(0.9 )Ta(5)Ru(10)
Ta(5)
SiO2/Si sub.

Deposition

 RF magnetron sputtering @RT
 Gas pressure : Ar 0.1-0.4 Pa
 Cathodes:4”φFabrication

 EB and Photo lithography Ar-ion milling

Post annealing 300oC H=400 mT (perpendicular)

Stacked structure
Slide 7

Two types of p-MTJs• We fabricated two types of MTJs which have samefeature size.
Conventional structure

100 nm

100 nmF = 100 nm

F = 100 nm
CoFeB
MgO
CoFeB

F : Feature size

Stepped structure

Free layer
Reference layer

CoFeB
MgO
CoFeB
300 nmSlide 8

Method to determine Hs experimentally

Resistance• Hs can be determined from shift of hysteresis loopwith respect to H=0.
“1”
Hs
“0”
0
Magnetic field
Slide 9Hs in two types of p-MTJs
4

Conventional structure

3Hs2
1-100 -50 0 50 100
Magnetic field (mT)Resistance (kΩ)

Resistance (kΩ)• Hs can be reduced by using stepped structure.
4

Stepped structure

3

Hs

2
1-100 -50 0 50 100
Magnetic field (mT)Conventional structure

Stepped structure

TMR ratio (%)

100

97

RA (Ωµm2)

1313

Hs (mT)

22

5
Slide 10

Experimental and estimated Hs• Experimental results are roughly agreed with thecalculation curve.
80tfreetbartrefHs (mT)dref

Conventional
structure

60l40
Stepped structure

2000
l=tfree/2+tref/2+tbar

100200dref (nm)300

Slide 11

Method to determine ∆0 and ∆1• We measured resistance as a function of magnetic
field 100 times to obtain switching probability.

Probability

Typical R-H loops

τp = 1 s
τ0 = 1 ns

Magnetic field
Slide 12∆0 and ∆1 in two types of p-MTJs• ∆0 and ∆1 in stepped structure are almost equivalent.
“1”->”0”
10.8
0.6
0.4
0.2
0

Stepped structure“0”->”1”
ProbabilityProbability

Conventional structure
10.8
0.6
0.4
0.2
0-150 -75 0 75 150
Magnetic field (mT)∆0∆1“1”->”0”“0”->”1”-150 -75 0 75 150
Magnetic field (mT)Conventional structure

Stepped structure

71.2

72.9

46.5

70.1
Slide 13Retention time and ∆1

Retention time (year)• Retention time over 10 years is achieved byemploying stepped structure.
Chip error rate Pchip: 10-4 for 10 years
Capacity n : 64Mb108
104∆1 of stepped

10 Years

1structure

10-4
10-840∆1 of conventionalstructure
5060

7080

∆Slide 14

Cell area of stepped structure

Cell area (µm2)• Cell area of stepped structure we demonstrated is0.09 µm2 which corresponds to SRAM cell area at 32nm technology node.
10F = 100 nm

1CoFeB
MgO
CoFeB

0.1

300 nm

0.01

SRAM 100F2(F: feature size)

32 nm
050
100
Technology node (nm)150
Slide 15

Cell area of stepped structure

Cell area (µm2)• Cell area can be down to 0.04 µm2 without degrading
the retention time over 10 years, which corresponds
to SRAM cell area at 20 nm technology node.
10F = 100 nm

1CoFeB
MgO
CoFeB

1/25

0.1

200 nmSRAM 100F2(F: feature size)

20 nm

0.01050
100
Technology node (nm)150
Slide 16

For reducing fabrication cost
• Additional masks are not necessary
Side wall spacer

Mask
CoFeB
MgO
CoFeB

Mask
CoFeB
MgO
CoFeB

1. Fabrication the 2. Deposition offree layerside wall spacer

Mask
CoFeB
MgO
CoFeB

3. Etchback

CoFeB
MgO
CoFeB

4. Completion of
stepped structure

Slide 17

Summary• Novel MTJ structure “stepped structure” isproposed.
• Different retention times of “0” and “1” information
are symmetrized.
• The stepped structure achieves retention time over
10 years.
• The cell area of the stepped structure corresponds
to that of SRAM at 20 nm technology node.
• Self-alignment process for reducing fabrication costis also proposed.
Slide 18