RECENT PROGRESS AND EMERGINGTECHNOLOGIES OF SPINTRONICS DEVICE FOR VLSI

1- Spintronics basics
2- MRAM
3- Logic-In-Memory
4- Emerging concepts

MAGNETISM BASICS

Spin moment

Orbital moment+ Spin moment+ Spin-Orbit

AtomicMomentExchange
Interactions-JexSi.Sj

Macroscopic
Magnetization

Lattice coupling+ shape anisotropy

Magnetic
anisotropy

L• Intrinsic logic system(2 states)• Non volatile• Size-independent

Ferromagnetic

S=+1/2 or -1/2

J = L +S

Permanent magnet

Eaax sy
isElectrons havea charge
and a spin

Antiferromagnetic

ΔE=KuV… as long as ΔE>kBTSPIN TRANSPORT
Exchange interaction
Band splitting

In metals, if spin flip marginal
Scattering proportional toavailable DOS just above EF

Giant MagnetoResistance (GMR)
Spin polarized current inand exiting magnetic layers

Mobility (conductance)
asymmetryJ

Sustained until spin-flipping
diffusion eventρ depends on relative orientationof spin current and local M

SPIN TRANSFER TORQUE (STT)
Magnetization(Spin) Current(Resistance)
Magnetization

Current« Magnetoresistance »« Spin Transfer Torque »xTransfer of angular momentum = STTyq

Incoming e-ThickPolarizer

Transmitted (filtered) e(spin↑)

I = -0.4 mA 9,1

Extended Gilbert equation :rrrrrdM
dM γ aJ (θ) r r r γbJ (θ) r r
α= −γ (M × Heff ) + M × +M ×(M × P) −(M × P)
dt
MS
dt
MSMS
Precession

Damping

Spin torque (ST)If spin torque < damping torqueNo switching
If spin torque > damping torqueSwitching

9R(ohms)

Reflected e- (spin↓)

8,98,88,7-400-200

0200H(Oe)

H = -4 Oe

9,1R(ohms)

z

9400

8,98,88,7-8-40I(mA)

48SPINTRONICS BUILDING BLOCK : THE MTJ
Insulator
Ferro 1
Insulator
Ferro 2Magnetic Tunnel Junction

F1F2EFeVEF0σ ∝ n1 ( E F ) × n2 ( E F )RParallel state

Low R
EF
Antiparallel state

HHigh REF

TMR =R↑↓ − R↑↑R↑↑

Tunnel Magneto-ResistanceMRAM BUILDING BLOCK : THE MTJ
T.Kawahara, Hitachi

Amorphous :Incoherent tunnelingof various Bloch states

Crystalline:
Specific wave
functionsoverlap/FeFe 3oeO
C l2oF
A u/C/RCoMRAM BUILDING BLOCK : THE MTJ
Top Electrode

Etch stop layer

Complex but mastered for volume manufacturing(1 millions heads/day since 5+ years !)Thermal barrier
Spin injectionlayerProtects MTJ during process
Capping layer

NiFe(3) / CoFe(2) : Stores data (2 stable states)

Storage layer

MgO (1.1) : Defines cell R & TMR

Tunnel barrier

CoFeB(2) / Ru(0.8)/CoFe(2) : SAF, immune to external fields

Reference layer
Pinning layer
Seed layer

Base electrode

PtMn(20) : AF layer sets direction of reference layer
Ta(5) or NiFeCr(10) : Promotes texture of critical layers
Contact to select transistor+ diffusion barrier

MTJ MANUFACTURINGGMR/TMR SENSORS
External Field

Magnetization

Resistance

HPosition sensors(earth field)

Disk drive heads(media bits stray field)

VoutI

“1”

I

TMR readhead+++++++++++++++
Pinned+++++++++++++++

φFree
PM

R(H)

- - - -Easy axis

“0”

PM

- - - - - - - - - - - - - - H = Field from media
HRH
Peripheral (CMOS) circuit not integrated
Single element devices
Volume manufacturing on Si or AlTiC wafers
Sub-‘’30nm’’ technology

“0”

“1”

MAGNETIC RANDOM ACCESS MEMORIES
“0”

Rlow

Rhigh

Logic memory state

010Rmin-110Norm alised Count

Magnetization state

“1”

Rmax

-2

10-3

10>25σ-4

10-5Address

10-610

Data out (Rhigh)Data refData out (Rlow)

0100

200

300

400

500
600
Resistance

700

800

900

1000

Figure of merit is not ΔR, but ΔR/σ
ΔR/σ >25 for functional device,>40 for production-worthy process
WW distribution 1σ need to be < 1%

WHY MRAM ?
Although not the best in each category, MRAM isthe only memory which scores everywhere

Fast, non-volatile, infinite endurance memory+ moderate power (no HV), rad-hard, easy to embedd

THERE ARE MANY MRAM !
Field-only« Toggle »HxSpin Transfer Torque« STT » or « SPRAM »Planar

Perpendicular

Thermal Assist« TAS » or « TAMRAM »Field-TAS

STT-TAS

Hy

Freescale 4Mb (2006)

Established technology
1.5M units shipped
4.5M forecasted in 2011

Infinite endurance
Scalability beyond 90 nm ?
(Write power increase )Lowest write current

1Mb Field-TAS (2011)(<100µA, scales with shrink)

Minimal cell / array size(~15F², soon not Xtor limited)

Low sensitivity to field disturb
Beware of stability(retention at small feature size)

Fully scalable(stability / retention to <20nm)

Multibit possible
Limited array efficiency(layout + large field drivers)

Combine both !

LATEST DEMO CHIPSTAS MRAM PRINCIPLE
LockUnlock

Use exchange biased bilayer to “lock” thestored data (high stability)
Heat the cell above to “unlock” the data
Analogous to Heat Assisted Recording in HDD(write at elevated T, store at RT)

ExchangebiasTAS write sequence
RR 1RHex

Ih = 0Isw = 00Hex

HIh > 0Isw > 0H

T = ambient temperature

T > blocking temperature

Step 1: Heat cell by flowing
current through transistor

Step 2: Switch magnetization bya magnetic field or STT torqueIh = 0Isw = 0H

T = ambient temperature

Step 3: Cool undermagnetic field or STT torqueSTT + TAS PROOF OF CONCEPT
5000
4500

TAS-Field MTJ stack

IrMn

4000
R(Ohm)

RxA from 30Ωµm² to 10Ωµm²
TMR up to 130%
Cell size 50nm (circular)

PtMn

Initial state
OFF

3500
3000
2500

OFFFinal state

2000-200-1000H(Oe)10020000-1000H(Oe)10020010yr ppm fail rate in 32M array, 10 years life (calculated)
4103ppm fail rate

10TAS
AR=1210SAF
AR=2

110TbFeCo
AR=1Co/Pt
AR=1108060

P to AP
AP to P

Current pulses 10ns40
2000,00,5
1,0
1,52,062
Current density (x10 A/cm )CoFeB
AR=2Voltage (V)Current density @ 10ns Jc = 2.4 106 A/cm²010Switching rate (%)

Pulsewidth (ns)10020304050
6070
technology feature size F(nm)8090

KV/kBT > 100 at 32nm feature size (AR=1)

2,5

HOW FAST CAN MRAM BE ?
Field MRAMSTT Precessional switching
IDC

In-plane analyzer(Co/IrMn)
Metallic spacer (Cu)Heat

Δt = 14ns (fuse adjustable)

0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0

Metallic spacer (Cu)

δ (ns)

Resistance (Ω)

Perpendicular polarizer(Pt/[Co/Pt]n/Co/Cu/Co)

Switching

Real-time
dynamic test

0.5
P->AP
AP>PFree layer (NiFe
3/Co0.5nm)

Field

1.0

Probability

Chip level

Write cycle 35ns

H.Liu et al, APL97, 242510 (2010)
HΔR
No switching

Switching transient ~ 1 ns
Switching time 5-10 ns (thermally activated)
Product Write cycle ~30 ns

Switching transient ~ 200 ps
Switching time < 1ns (deterministic)
Expected Write cycle ~2-3 ns

(MAGNETIC) LOGIC-IN-MEMORY“Janus” SoC

Von Neuman SoC
Logic

MTJsLogic

CMOS memory

SiSi
Large Si footprint, long interconnects
Delay, capacitive loss, complex layout, heat

Minimal Si footprint, short interconnects
Faster, simpler layout, reduced dynamic power

Logic-in-memory concept (introduced in 1969)
Storage elements are distributed over the logic plane
Non volatility directly inside the logic circuit

Non volatile memoryNo leakage
Static power off
Reduced wire count
Minimal dynamic power, delay
Optimal layout
T.Hanyu, Tohoku University, 1th Joint MMM-Intermag Conference, Jan. 21, 2010

Need NV, fast, infinite endurance, CMOS compatible memory !

MTJ-BASED LOGIC CIRCUITS- Infinite endurance (>1016 for field write)
High speed (1-30ns)
Magnetic- Cell R adjustable, from Ω‘s to MΩ’selement level
Match with CMOS (~ kΩ)- Cell is variable resistance driven by low voltage
use as standard library IP- Can be deposited on any substrate‘’end-of-back-end » » process (above-IC)
no impact on logic process
only 3 add-masks
CMOS logiclevel
Front-end contamination under control
Low-T BE process (250°C) compatible with Cuinterconnect process
Etch still « tricky »IBE vs. RIE ?
MRAM process well established
Fear for contamination (slowly) vanishing
Several fabs now enabled with 200/300mm lines

MTJ ELECTRICAL COMPACT MODEL
High-Speed compact model

Electrical behavior of MTJ written by field, STTand with/without thermal assistance.
SPECTRE (5.0) compatible (CADENCE platform analog solver).

SMTJ model

BSIM3v3 model

Simulation of a TAS-MRAM

(MAGNETIC) NV-LOGIC CIRCUITS
Hitachi + Tohoku University
S.Matsunaga et al, Applied Physics Express, vol. 1, 2008.

–

NV-Full Adder
••
•

––

One input is made non-volatile (instant startup,security)
Drastic static consumption reduction
Footprint reduction

Demonstrator : CMOS 0.18µm,
MTJs size: 200X100nm²

R-SRAM ©

Magnetic Flip-flop

Magnetic LUTREPROGRAMABLE (MAGNETIC) LOGIC

4504 ummtile# LUT 41444# TILES361 (19x19)# Sequential elements

1444# of MTJs

187 720# of Transistors

9. 106

Silicon Area

21mm 2MRAM
Reconfiguration Tile
Energy9 nJ

MRAM Restoration
Tile Energy

25,5 pJ

Clock Frequency

100 MHz

Full configuration time

72us + 93K ClockcyclesTile reconfiguration

200ns + 260 Clockcycles# Input/Output

76 Input / 76
Output4504 um

Visite Altis - 15/10/2010

21

(INTERMEDIATE) CONCLUSION
Increasing interest for MRAM for stand-alone,embedded memories or “logic-in-memory”•Spintronics brings non volatility to CMOS circuits
for low-power, normally-off electronics••

Manufacturing technology mature enough withpure-play foundries entering the game
Design environment “ready-to-use” asstandard library tools

www.scirus.com
Nb publications+brevets
Nb publi+patents
per year on MRAM

•1 10

Mot clé: "MRAM"

48000

6000

4000

20000
1998 2000 2002 2004 2006 2008 2010 2012
Année

WHAT’S NEXT ?

Courtesy Sam BaderSPIN TRANSFER OSCILLATORS (STO)
Heff

AntennaDampingM

fsig

Spin TorqueMixer
Antenafilter

fsig±fmix

Low ffilter

fsig-fmix

Reference

If damping = STTSelf-sustained precession
Oscillations of R
VCO

Frequency
synthetizer

VCO

STOL
Resonator

Precession

C
Attenuated Resonator

R0DampingAuto-Oscillator
Comp.energy losses-Rs

Spin Transfer
B

Resonnance frequency 1-40 GHz
Tunable by current and/or field
Radio-opportunism

B

Can spintonics-based device replace
VCOs in a transceiver chain ?

S(t)SPIN TRANSFER OSCILLATORS (STO)
LETI/DCIS

IrMn
Co

STO

Cu

Amp.

Cu

Source decourant

PEL

Pointes DC

Ipol
OscSpin
OSCILLATOR
MGO

Pt/(Co/Pt)5HIDC4Kohms

DC + AC

Pointe RFRF in+ AC
RF in-Bias T

GND

Pointes
RFAmpli
Analyseur de Phase

SPINAM P4Kohms

Substrat silicium
Pointes DCPhase NoiseFrequency

7.7

7.6

7.50500
Time (ns)1000

SPIN TRANSFER DOMAIN WALL MOTIONIn Domain Wall, local “magnetic” pressure
induced by STT
DW motion
MRAM & logic devices“Race Track Memory”

Rashba-induced DW motion
in ultra-thin Pt/Co/Al2O3 layers
Nature Materials Vol.9,pp.230–234 (2010)

Magnetic shift register

DW velocity (m/s)

400300200
1000Best STT value0123122
Current density (x 10 A/m )NEW MATERIALS : HEUSLER ALLOYS
Use « half »-metals (Heusler alloys)
EEFD↓(E)

D↑(E)

↑Jex

↓

TMR =Rantipar − R par
R par→∞

Integration of half-metals could
open the door for spin switches
Active logic devices

TOWARDS PURE SPIN LOGIC ?
The long quest for a spin transistor …
Problems:• No efficient spin injection from FM into SC• Short spin lifetime in SC• No magnetic SC at RT

Graphene
Spintronics
L.Hueso, N.D. Mathur, A.Fert et al, Nature 445, 410, 2007

J, J s

M1II1
1II2 M22

Extremly long lifetime + Efficient spin injectionSPIN-ONLY CURRENTS
Spin-Hall
Charge current

Inverse Spin-Hall
Spin « current »Spin current

Spin
Imbalance

Charge current

Chargecurrent
Spin
Current

ChargeCurrent

Spin injection into graphene
V

Spin current w/o charge current
Would allow full functionnality withno heating / power dissipation !

Spin
Current

Wei Kan et al (R. K. Kawakami's group), PRL 105, 167202 (2010).
B. Dlubak et al, (A. Fert's group) Appl. Phys. Lett. 97, 092502 (2010)

(FINAL) CONCLUSION
Increasing interest for MRAM for stand-alone,embedded memories or “logic-in-memory”•Spintronics brings non volatility to CMOS circuits
for low-power, normally-off electronics•••

Manufacturing technology mature enough withpure-play foundries entering the game
Design environment “ready-to-use” asstandard library tools

www.scirus.com
Nb publications+brevets
Nb publi+patents
per year on MRAM•

Mot clé: "MRAM"

4

1 10

8000

6000

4000

2000

0
1998 2000 2002 2004 2006 2008 2010 2012
Année

Huge development potential

Important “cultural” gap between magnetics and microelectronics communities
Most MRAM players have HDD experience (e.g. magnetics “culture”)“Mutual education” mandatory to move towards adoption of spintronics in VLSIDo not be afraid of magnetism and magnetic materials ! ☺