November 3-4, 2011
Berkeley, CA, USA

Nonvolatile CMOS Circuits
Using Magnetic Tunnel Junction
Hideo Ohno1,2
1Center for Spintronics Integrated Systems, Tohoku University, Japan
2Laboratory for Nanoelectronics and Spintronics, Research Institute ofElectrical Communication, Tohoku University, Japan

Shoji Ikeda, Tetsuo Endoh, Takahiro Hanyu, Katsuya Miura, Naoki Kasai, Hiroyuki Yamamoto, Kotaro
Mizunuma, Huadong Gan, Michihiko Yamanouchi, Hideo Sato, Ryouhei Koizumi, Jun Hayakawa, Kenchi
Itoh, Fumihiro Matsukura and many others

Work supported by the FIRST program of JSPS.

http://www.csis.tohoku.ac.jp/

OUTLINE
VLSI - challenges Spintronics-based nonvolatile CMOS circuits
Current status of magnetic tunnel junction
Future directions
Summary

The FIRST Program
Funding Program for World-Leading Innovative R&D on Science andTechnology (30 Programs)
Research Subject
Core Researcher“Research and Development ofUltra-low Power Spintronics-based VLSIs”
Hideo Ohno, Prof. of Tohoku University

Program Planning & Selection

The Council for Science and Technology Policy

Program Management & Operation

Japan Society for the Promotion of Science(JSPS)

Program Duration

From FY 2009 through FY 2013

Operational Support Institution

Tohoku University

Participating InstitutionsTohoku University, NEC, Hitachi, ULVACThe University of Tokyo, Kyoto University
National Institute for Materials Science
Renesas Electronics, Covalent Silicon

http://www.csis.tohoku.ac.jp/

Challenges Current VLSIs Face

DissipationPower
消費電力（W）

PowerConsumption
Power Consumption
Increase
Active PowerInterconnection
Delay
Interconnect Signal Delay
Logic

MemorySignal Bottleneck
Standby Power(leakage current)

Year

Logic

MemoryLeakage Current

What do we need?
Nonvolatile memory that isscalable
fast
virtually infinite endurance
back-end-of-line compatible5

Magnetic Tunnel Junction
RAP − RP2P 2=Tunnel MagnetoResistance (TMR) =RP
1− P2
ParallelEE

Antiparallel

Ferromagnet 1 Insulator

Ferromagnet 2

Room temperature TMR: Miyazaki and Tezuka (Tohoku U.), J. Mag. Mag. Mat. 1995 and Moodera et al. Phys. Rev. Lett. 1995.

Magnetic Tunnel Junction Configurations

Domain Wall

two terminal

three terminal

nonvolatile, fast and high endurance
7Magnetic Random Access Memory
Word Line
Bit Line
MTJTransistor

System (Memory) Hierarchy
Nonvolatile
Logic-in-Memory

current

near futurefuture

Magnetic tunnel junction based memory element to counter dynamic andstatic power, and interconnection delay
H. Ohno, E. Endoh, T. Hanyu, N. Kasai, and S. Ikeda (invited) IEDM 2010

Spintronics-based CMOS VLSIMTJ cells

MTJ(1)Nonvolatile(2)Memory in the back end(3)Use of memory in processing

M4

Memory layer
M3
Cross section
SEM imageof SPRAM cell

M2

Logic layer

M1
CMOS-Tr.

Nonvolatile Logic-in-Memory

15.5 µm

Full adder block for image processing
SUM

P : Prechargephase
E : Evaluate
phase

VDD

“ Poweroff”

P E

Standby

13.9 µm

P E“ Power-off”

Active“ PowerP Eoff”

Active

A=0,B=0,C i=0

A=0, B=0,C i=1

StandbyStandby

Sbefore=0

CARRY

P E

ActiveInputs(A,B and Ci)
CLK“ Power-off”

StandbySafter=0

S(=A B C i)S’(=A B C i)

Sbefore=1

Safter=1

S’before=0

S’after=0780mV/div

S’before=1

10.7 µm
0.18 µ m CMOS/MTJ Process

S’after=11mS/div

S. Matsunaga, … H. Ohno, T. Hanyu, APEX, 1, 091301 (2008)

MTJ: 100 x 200 nm2Nonvolatile: ultimate power gating (no static power)
Memory in the back end + part of logic(reduced # of tr. = suppression of delay and dynamic power)Full Adder Comparison

Simulation (except area/device #), 0.18 µm CMOS process
CMOS/MTJ Hybrid

24% reduction in device countS. Matsunaga, … H. Ohno, T. Hanyu, APEX, 1, 091301 (2008)

Nonvolatile CAM and TCAM
Nonvolatile CAM

Nonvolatile TCAM
226 µm
Row Dec.
Column Dec.

174 µm2-kb
TCAM
cell array
Sense Amp.

Matsunaga et al.
Nebashi et al.

VLSI Symp. 2011

Transfer curves of STT-SRAM cell(a) “0” data latch(b) “1” data latch

Parallel1.01.00.34V

1.2KΩ (linear)

0.8
V/SN [volts]

V/SN [volts]

0.8
0.6
0.4
0.2
MTJ switching (P to AP)
00.2

0.4

MTJ switching (P to AP)

0.6
0.4
1.2KΩ (linear)
0.2

Anti-parallel

0.6

0.8

0

1.0

0.2

0.4

VSN [volts]

RAP
SN

0.34V

RP
/SN

0.6

0.8

1.0

VSN [volts]

1.2KΩ

1.2KΩ

SN

/SN

RP
SN

RAP
/SN

T. Ohsawa et al., SSDM 2011

MTJ for VLSI: A wish list
1. Small footprint (F nm)
2. High output (TMR ratio > 100%)
3. Nonvolatility (∆=E/kBT >40)
4. Low switching current (IC0 < F µA)
5. Back-end-of-the-line compatibility (350 oC)
6. Endurance
7. Fast read & write
8. Low resistance for low voltage operation
9. Low error rate
10. Low cost

MTJ for VLSI: A wish list
1. Small footprint (F nm)
2. High output (TMR ratio > 100%)
3. Nonvolatility (∆=E/kBT >40)
4. Low switching current (IC0 < F µA)
5. Back-end-of-the-line compatibility (350 oC)
6. Endurance
7. Fast read & write
8. Low resistance for low voltage operation
9. Low error rate
10. Low costPerpendicular MgO-CoFeB MTJ
JC0 = 3.9 MA/cm2(IC0 = 49 μA)
E/kBT = 43
TMR ratio = 124%

40 nm

(b)
(a)

interface perpendicularanisotropy

Top electrode
Cr/Au
Ru
Ta

CoFeB
MgO
CoFeB

Ta(c)
Ru
Ta
SiO2/Si sub.

Bottom electrode

5 nm

S. Ikeda et al., Nat. Mat. 9, 721 (2010), K. Miura et al., MMM 2010

MTJ for VLSI: A wish list
1. Small footprint (F nm)

40 nm

2. High output (TMR ratio > 100%)
3. Nonvolatility (E/kBT >40)

113%
39

4. Low switching current (IC < F µA)

48 µA

5. Back-end-of-the-line compatibility (350 oC)

350 oC

6. Endurance
7. Fast read & write
8. Low resistance for low voltage operation

16 Ωµm2

9. Low error rate
10. Low cost
18How small can we go?

CoPtCr-SiO2, Takei et al., Fuji Electric review 55 (2009) 6..

19

Magnetization manipulation by

Magnetic field
write/read heads for HDD
1st generation MRAM

Spin current

http://www.hitachigst.com/

http://www.everspin.com/

L. Berger, J. Appl. Phys. 55, 1954 (1984).
J. Slonczewski, J. Magn. Magn. Mat. 159, L1 (1996).
L. Berger, Phys. Rev. B 54, 9353 (1996).

Spin torque MRAM
Spin torque oscillator
Race-track memory

Electric field

R. Takemura et al., VLSI Circ. Dig. p.84 (2009)

Switching Energy

Spin-transfer switching
VIt = 0.5 (V) × 30 (µ A) × 1 (ns) = 15 (fJ)Electric field switching
CV 2 =S × d × ε × E 230 (nm) 2= π() × 5 (nm) × 9.8 ε 0 × (5 (MV/cm)) 22= 0.08 (fJ)

21

Electric-field control of magnets
Ferromagnetic transition

Ferromagnetic semiconductor (In,Mn)As5022.5 K

Magnetization direction

Ferromagnetic Semiconductor (Ga,Mn)As2KR Hall (Ω)

2500V+1.5 MV/cm-1.5 MV/cm
0V-25-50-1.0-0.5

00.5

1.0

B (mT)
H. Ohno et al., Nature 408, 944 (2000)

D. Chiba et al., Nature 455, 515 (2008)

Electric-field effects on CoFeB
Manipulation of magnetic anisotropy in CoFeB at room temperature

M. Endo, et al. Appl. Phys. Lett. 96, 212503 (2010).

See also; FePt, FePd: M. Weisheit et al., Science (2007).
Fe/Au: T. Maruyama et al., Nature Nanotechnology (2009).

Summary
Integrating spintronics nonvolatile memory element,
magnetic tunnel junction, with CMOS realizes lowpower, high performance, and stand-by power freenonvolatile VLSIs.
Magnetic tunnel junction is much better positioned
now than before with 30 nm dimension and beyond insight. Once ready this could trigger a major paradigm
shift.
Electric field switching can realize ultra-low-powerswitching of magnetization.

Spintronics may revolutionize the way VLSIs
are made today.