2011 11th Non-Volatile Memory Technology Symposium @ Shanghai, China, Nov. 9, 20112

MTJ-Based Nonvolatile
Logic-in-Memory Architecture
and Its Application
Takahiro Hanyu1,3,S. Matsunaga1, D. Suzuki1, M. Natsui1,3, S. Ikeda1,2, T. Endoh1,4, N. Kasai1,and H. Ohno1,2
1Center for Spintronics Integrated Systems, Tohoku University,

JAPAN

2Laboratory for Nanoelectronics and Spintronics, RIEC, Tohoku University, JAPAN
3Laboratory for Brainware Systems, RIEC, Tohoku University, JAPAN
4Center for Interdisciplinary Research, Tohoku University, JAPANhttp://www.csis.tohoku.ac.jp/

Acknowledgement:This work was supported by the project “Research andDevelopment of Ultra-Low Power Spintronics-Based VLSIs”
under the FIRST program of JSPS (Leader: Prof. H. Ohno).

Outline• Nonvolatile Logic-in-Memory
Architecture Overview• NV GP-Logic: Nonvolatile-FPGA• NV SP-Logic: Nonvolatile-TCAM• Conclusions & Future Prospects
2

Background: Increasing delay & power

Leakagecurrent
Logic and Memory modules are separated
Many interconnections between modules

On-chip memory modules are volatile.

Wire delay dominates chip performance
Global wires requires large drivers.

Power supply must be continuously
applied in memory modules.

Delay: LongPower: Large

Static power: Large

3

Nonvolatile logic-in-memory architecture
Logic-in-Memory Architecture (proposed in 1969):
Storage elements are distributed over a logic-circuit plane.
•Magnetic Tunnel Junction(MTJ) device•No volatility
MTJ•Unlimited endurance
layer•Fast writability•Scalability
CMOS•CMOS compatibility
layer•3-D stack capability●Storage is nonvolatile:(Leakage current is cut off）
●MTJ devices are puton the CMOS layer●Storage/logic are merged:(global-wire count is reduced）

Static power is cut off.
Chip area is reduced.
Wire delay is reduced.
Dynamic power is reduced.
4Implementation of MTJ Device
MTJ DeviceFabricated
CMOS back-endprocess

LE

M3

M3

THTH

M2

M2

THTH

M1

UEMTJ
Layer

TH

Gate C

Substrate

MTJ

Metal
Layers

M1
C

MTJ

M1
Gate

C

CMOS
Layer

300nm

D. Suzuki, et al., VLSI Circuit Symp. 2009

Diffusion

MTJ device stacked over MOS Plane

Cross-sectional SEM image. area cost using MTJ device is small.
The5

Use of Charge and Spin
Storage“0” state

LogicSpin is used as an
information carrier.

Data is still kept
when VDD is OFF（Nonvolatile）

Spintronics

High resistance“1” state

Low resistance

Logic operationis possible

Logic

Charge is used as an
information carrier.

Storage

Silicon CMOS

Use of both charge and spin“0” state

Very highresistance“1” state

Very low
resistance

Charge is gone
when VDD is OFF（Volatile）

Logic operation
is done6

Realize no volatility and rich logic functionality

Power-Gating Suitability
Powerswitch

Powerswitch

External
Nonvolatilestorage

Leakagecurrent

VolatilestoragePowerswitch

Power

VDD

ActiveStandby

Escapeto NVM

ActiveReload
from NVM

Logic

VDD
Power switch(PMOS)

PowerTime

ActiveStandby

ActiveNonvolatilestorage(MTJ device)
Logic
Time

NV logic-in-memory architecture
Power gating is performed without data backup/reload.

7

Nonvolatile Processor Architecture
Flash

GP-Logic: General-purpose logic
SP-Logic: Special-purpose logic

DRAM

Spin RAM

Spin RAMNVSRAMNV
NV
FF GP-Logic FF SP-LogicSi
1st -step Nonvolatile Processor

NVLIM
NVLIM
GP-Logic SP-LogicSi
2nd-step Nonvolatile Processor

NVSRAM

Nonvolatile Field-Programmable
Gate Array (FPGA)

Nonvolatile Ternary ContentAddressable Memory (TCAM)
8

Outline• Nonvolatile Logic-in-Memory ArchitectureOverview• NV GP-Logic: Nonvolatile-FPGA• NV SP-Logic: Nonvolatile-TCAM• Conclusions & Future Prospects
9Nonvolatile Field-Programmable Gate Array (FPGA)
NV LUT (Lookup Table)

NV device-- Arbitrary logic functions are performed
and programmed by FPGA-- Power dissipation and hardware overhead
are two major issues.
-- NV storage elements are distributed
over the NV-FPGA (no external NVM).

☺
NVM

NVFPGALeakage current eliminationand short latency are possible.

 How to design?
Nonvolatile logic-inmemory architecture

Not required!
10

Conventional nonvolatile FPGA CMOS logic circuit requires
high-voltage input swing.
MTJMTJMTJMTJSASASASA

Combinationallogic(CMOS)

Output(SA: Sense Amplifier)Low voltage

High Voltage

How do we perform logic operation by using
low swing signal from MTJ device directly?
11

MOS/MTJ-hybrid circuitry (Proposed)
Current-mode logic (CML) Logic operation is performed even low swing voltage byusing the small difference of the current value.

MTJMTJ
MTJMTJCombinational
logic(Current-Mode)
Low voltage

SAOutput

High voltage

Device count is reduced to 28% with lessperformance degradation.

12

Operation example (XOR)
Z=0IF > IREF

IF
‘0’

‘1’
‘0’
RAP

Z=1Sense Amplifier

‘1’RP

‘0’

‘1’

RP

RAP

IREF

Truth table

‘1’

‘0’

AB

Z

001

‘0’

‘1’0

10

100

1

1

1

RREF

Logic operation in low swing voltage is performedby using a MOS/MTJ-hybrid network.
13

Test chip features
Fabricated 2-input LUT

Selection
Transistor Tree

4 MTJ devices arestacked over MOS layerD. Suzuki, et al., VLSI Circuit Symposium, June 2009.

Process

0.14mMTJ/MOS
1-Poly,3-Metal

Area287m2

MTJ Size

50nm
150nmTMR Ratio
Current
WriteTimeStandby Current

100%150A
10ns0A
14

Measured waveforms (Basic operations)P E P E P E P E

P: Pre-Charge
E: Evaluate

Input A
Input B
Output Z

‘1’

‘0’

‘0’

‘0’

‘1’

‘1’

‘1’

‘0’

Output Z
NAND

NOR
A
0.78V/div

B
Z

100s/div

‘0’

‘1’

‘1’

‘0’

‘1’

‘0’

‘0’

‘1’Z
XORXNOR

15Immediate wakeup behavior
ActiveStandby

Active

VDD= 0A B

CLKVDDA B00 01 10 1100 01 10 11Z
Z
0.78V/div
50s/div

Immediate wakeup behavior
has also measured successfully.
16

Comparison of performances

Device Counts

Standby

Proposed
29 MOSs+ 4 MTJs

702 m2

287m2

Delay *3)

140 ps185 psPower*3)

26.7 W

17.5 W

Power0 W

0 W

Area *2)
ActiveNonvolatile
SRAM *1)
102 MOSs+ 8 MTJs

*1) W. Zhao, et al., Physica Status SOLIDI a Application and Materials Science, 205, 6,1373/1377, May 2008.
*2) Estimation based on a 0.14m process*3) HSPICE simulation based on a 0.14m MOS/MTJ-hybrid process

17Outline• Nonvolatile Logic-in-Memory ArchitectureOverview• NV GP-Logic: Nonvolatile-FPGA• NV SP-Logic: Nonvolatile-TCAM• Conclusions & Future Prospects
18

Ternary Content-Addressable Memory (TCAM)
01001・・・

10

Fully parallelmasked equality
searchSearch-line / Word-line driver
222BL1
BL1’
BL2
BL2’

BLnBLn’

1012110200220・・・

1・・・

Stored words
1002・・・

Bit-line driver201・・・

1X

X

2XX

X

OUT1
OUT2OUTn

Output driver

Input key0 (Mismatch)
1 (Match)

0 (Mismatch)

Fully parallel search and fully parallel comparison can be done.
TCAM is a “functional memory.”
TCAM is the powerful data-search engine
useful for various applications such as database machine and virus checker innetwork router
TCAM must be implemented more compactly with lower power dissipation.
19

NV-TCAM Cell Function
Stored dataB01X
don’tcare(b1,b2 )SearchinputSCurrentcomparisonMatchresultML
10

IZ < IZ’1

IZ > IZ’(Mismatch)

0

IZ > IZ’(Mismatch)

1

IZ < IZ’(Match)0

IZ < IZ’(Match)

1

IZ < IZ’

(0,1)

(1,0)

(0,0)

(Match)001
11(Match)

20

CMOS-based TCAM cell circuit
1-bit storage

Equality-detection(ED) circuit

1-bit storage

ML
VDD

Leakagecurrent

WL
VSS
BL1

Leakagecurrent

SL’

SLBL2

Transistor counts : 12 (ED;4T, 2-bit storage;8T)
Input/output wires : 8 (BL;2, WL;1, VDD&VSS;2, SL;2, ML;1)
Always supply the power : Many leakage current path
How to realize compact & cut off the leakage current ?
21

MOS/MTJ-hybrid TCAM cell circuit
S. Matsunaga, et al. Applied Physics Express (APEX), 2, 2, 023004, Feb. 2009.

ML/BL

2-bit storage(MTJs)
Logic(MTJs & MOSs)

SL’/WL1

SL/WL1•Merge storage into logic circuit : Compact (2T-2MTJ)•Share wires : 4 (ML/BL, SL/WL, No-VDD)•3-D stack structure : Great reduction of circuit area
Compact & nonvolatile TCAM cell with MTJ devices
22Power-Gating Scheme of Bit-Serial NV-TCAM
S. Matsunaga, et al., JJAP 49 (2010) 04DM05.

1st-bit search
111Search word

00X

SA

ACC

010SA0X

1101

2nd-bit search
111Search word

Mismatch

00X

SA

ACC

ACC

Mismatch

010SA

SA

ACC

Mismatch

0X

1X

SA

ACC

Match

10

10

SA

ACC

Match

11X

1SA

ACC

Match

X

0X

SA

ACC

X

10

SA

X

X

1SA

3rd-bit search
11

1Search word

Mismatch

00X

SA

ACC

Mismatch

ACC

Mismatch

010SA

ACC

MismatchSA

ACC

Mismatch

0X

1SA

ACC

MismatchXSA

ACC

Mismatch

10X

SA

ACC

Mismatch

10SA

ACC

Match

110SA

ACC

Mismatch

1X

1SA

ACC

Match

1X

1SA

ACC

Match

Match

X

0X

SA

ACC

Mismatch

X

0X

SA

ACC

Mismatch

ACC

Match

X

10SA

ACC

Match

X

10

SA

ACC

Mismatch

ACC

Match

X

X

1SA

ACC

Match

X

X

1SA

ACC

Match

TCAM cell in standby mode
(Static power is suppressed.)

TCAM cell in active mode
SA Sense amplifier in active modeSA

ACC Accumulator in active mode

Sense amplifier in standby mode
(Static power is suppressed.)

According to the word length of the TCAM,
the effectiveness of the standby-power reduction is increased.

23TCAM cell circuit test chip
3.0 mChip features

9.8 mOutputgenerator
inMLSA

TCAM
cellRef.
cellDynamic
current
comparator
in
MLSA

Process

0.14m CMOS/MTJ
1-Poly, 3-Metal

Total area

29.4 m2

TCAM cell size

3.15 m2(2.1 m×1.5 m) a)

Cell structure

2MOSs-2MTJs

MTJ size

50 nm×200 nm

TMR ratio

167 %Averagewrite current

274 A (p = 10 s) b)

Standby current

0A (Power off)a) A CMOS-based TCAM cell with 12 transistors, whose cell size is 17.54 m2 under a 0.18 m CMOS process,has been reported.8) The size of the conventional TCAM cell can be estimated as 10.61 m2 under a 0.14 m
CMOS process by scaling down. Thus, the size of the fabricated TCAM cell is reduced to 30 % compared to thatof the conventional one. Moreover, minimum size of the proposed TCAM cell can be considered as 1/6 of theconventional one.
b) More high-speed write operation is possible with increase of write current. For example, with the average current
24of 327 A at 10 ns write.

Waveforms of equality-search operations
P : Precharge phase

E : Evaluate phase

Bit-level equality-search is successfully demonstrated.

25

Waveforms of sleep/wake-up operations
VDD

Power-offPower-off

ActiveP

ActiveE

StandbyPE

P

ActiveE

StandbyPE

CLKStored data B=0S

S=0Stored data B=0
S=0

OUTbefore=1

OUTafter=1

Match

Match

S=1

S=1

OUTbefore=0

OUTafter=0

Mismatch

Mismatch

OUT
780mV
10s

Instant sleep/wake-up behavior is successfully demonstrated.
26

Outline• Nonvolatile Logic-in-Memory Architecture
Overview• NV GP-Logic: Nonvolatile-FPGA• NV SP-Logic: Nonvolatile-TCAM• Conclusions & Future Prospects
27

Conclusions
Propose a MOS/MTJ-hybrid circuit (nonvolatile logic-inmemory circuit using MTJ devices) style
Two kinds of typical applications with logic-in-memoryarchitecture; NV-LUT circuit and NV- TCAM
Compact and no static power dissipation
Confirm basic behavior with fabricated test chips
under an MTJ/CMOS process.
It could open an ultra-low-power logic-circuit paradigm
Future Prospects and Issues:1. Establish the fabrication line
2. Establish the CAD tools
3. Explore the appropriate application fields(Impact towards “Reliability Enhancement”)
2829