2011 Spintronics Workshop on LSI @ Kyoto, Japan, June 13, 2011

MTJ-Based Nonvolatile
Logic-in-Memory Architecture
Takahiro Hanyu
Center for Spintronics Integrated Systems, Tohoku University, JAPAN
Laboratory for Brainware Systems, Research Institute of ElectricalCommunication, Tohoku University, JAPAN

Acknowledgement:This work was supported by the project “Research andDevelopment of Ultra-Low Power Spintronics-Based VLSIs”
under the FIRST program of JSPS.

Outline• Nonvolatile Logic-in-Memory
Architecture Overview• NV GP-Logic: Nonvolatile-FPGA• NV SP-Logic: Nonvolatile-TCAM• Conclusions & Future Prospects
2

Background: Increasing delay & power

Leakagecurrent

Logic and Memory modules are separated
Many interconnections between modules

On-chip memory modules are volatile.

Wire delay dominates chip performance
Global wires requires large drivers.

Power supply must be continuously
applied in memory modules.

Delay: Long

Power: Large

Static power: Large
3

Nonvolatile logic-in-memory architecture
Logic-in-Memory Architecture (proposed in 1969):
Storage elements are distributed over a logic-circuit plane.
•Magnetic Tunnel Junction(MTJ) device•No volatilityMTJ•Unlimited endurance
layer•Fast writability•Scalability
CMOS•CMOS compatibility
layer•3-D stack capability●Storage is nonvolatile:(Leakage current is cut off）
●MTJ devices are puton the CMOS layer●Storage/logic are merged:(global-wire count is reduced）

Static power is cut off.
Chip area is reduced.
Wire delay is reduced.
Dynamic power is reduced.
4Implementation of MTJ Device
MTJ Device→Fabricated
CMOS back-end
process

LE

M3

M3

TH

TH

M2

M2

TH

TH

M1

UEMTJ
Layer

TH

Gate C

Substrate

MTJ

Metal
Layers

M1
C

MTJ

M1
GateC

CMOS
Layer300nmD. Suzuki, et al., VLSI Circuit Symp. 2009

Diffusion

MTJ device stacked over MOS Plane

Cross-sectional SEM image. area cost using MTJ device is small.
The5

Power-Gating Suitability
Powerswitch

Powerswitch

Leakagecurrent

Powerswitch

Power

VDD

ActiveStandby

Escapeto NVM
External
Nonvolatilestorage

Volatilestorage

ActiveReloadfrom NVM

Logic

VDD
Power switch(PMOS)

PowerTime

ActiveStandby

ActiveNonvolatilestorage(MTJ device)
LogicTimeNV logic-in-memory architecture
Power gating is performed without data backup/reload.

6Nonvolatile Processor Architecture
FlashGP-Logic: General-purpose logic
SP-Logic: Special-purpose logic

DRAM

Spin RAM

Spin RAMNV
NV
FF GP-Logic FF SP-LogicSi
1st -step Nonvolatile Processor

NVSRAM

NVLIM
NVLIM
GP-Logic SP-LogicSi
2nd-step Nonvolatile Processor

NVSRAM

Nonvolatile Field-Programmable
Gate Array (FPGA)

Nonvolatile Ternary ContentAddressable Memory (TCAM)
7

Outline• Nonvolatile Logic-in-Memory Architecture
Overview• NV GP-Logic: Nonvolatile-FPGA• NV SP-Logic: Nonvolatile-TCAM• Conclusions & Future Prospects
8Nonvolatile Field-Programmable Gate Array (FPGA)
NV LUT (Lookup Table)

NV device-- Arbitrary logic functions are performed
and programmed by FPGA-- Power dissipation and hardware overhead
are two major issues.
-- NV storage elements are distributed
over the NV-FPGA (no external NVM).

☺
NVM

NV

Leakage current eliminationand short latency are possible.

 How to design?

FPGA

Nonvolatile logic-inmemory architecture
Not required!
9Conventional nonvolatile FPGA CMOS logic circuit requires
high-voltage input swing.
MTJMTJMTJMTJSASASASA

Combinationallogic(CMOS)

Output(SA: Sense Amplifier)Low voltage

High Voltage

How do we perform logic operation by using
low swing signal from MTJ device directly?
10MOS/MTJ-hybrid circuitry (Proposed)
Current-mode logic (CML) Logic operation is performed even low swing voltage byusing the small difference of the current value.

MTJ
MTJ
MTJ
MTJ

Combinational
logic(Current-Mode)
Low voltage

SAOutput

High voltage

Device count is reduced to 28% with lessperformance degradation.

11

Operation example (XOR)
Sense Amplifier

Z=0IF > IREF

IF

‘0’RAP

‘1’

‘0’

‘1’
‘1’RP

‘0’RP

‘1’RAP‘0’Z=1IREF‘0’‘1’RREF

Truth table
ABZ001010100111

Logic operation in low swing voltage is performedby using a MOS/MTJ-hybrid network.
12Test chip features
D. Suzuki, et al., VLSI Circuit Symposium, June 2009.

Fabricated 2-input LUT

Selection
Transistor Tree

4 MTJ devices arestacked over MOS layer

Process

0.14µmMTJ/MOS
1-Poly,3-MetalArea

287µm2

MTJ Size

50nm
×150nmTMR Ratio
Current
WriteTime
Standby Current

100%150µA
10ns0A
13Measured waveforms (Basic operations)P E P E P E P E

P: Pre-Charge
E: Evaluate

Input A
Input B
Output Z

‘1’

‘0’

‘0’

‘0’

‘1’

‘1’

‘1’

‘0’

Output Z
NAND

NORA
0.78V/divBZ

100µs/div

‘0’

‘1’

‘1’

‘0’

‘1’

‘0’

‘0’

‘1’

Z
XOR

XNOR

14

Immediate wakeup behavior
ActiveStandby

Active

VDD= 0A ⊕B

CLKA ⊕B

VDD

00 01 10 1100 01 10 11Z
Z
0.78V/div
50µs/div

Immediate wakeup behavior
has also measured successfully.
15

Comparison of performances

Device Counts

Proposed29 MOSs
+ 4 MTJs

702 µm2287µm2Delay *3)

140 ps185 psPower*3)

26.7 µW

17.5 µW

Power0 µW0 µW

Area *2)
ActiveStandbyNonvolatileSRAM *1)
102 MOSs+ 8 MTJs

*1) W. Zhao, et al., Physica Status SOLIDI a Application and Materials Science, 205, 6,1373/1377, May 2008.
*2) Estimation based on a 0.14µm process*3) HSPICE simulation based on a 0.14µm MOS/MTJ-hybrid process16Outline• Nonvolatile Logic-in-Memory Architecture
Overview• NV GP-Logic: Nonvolatile-FPGA• NV SP-Logic: Nonvolatile-TCAM• Conclusions & Future Prospects17Ternary Content-Addressable Memory (TCAM)
0100・・・

110

Fully parallelmasked equalitysearch

Search-line / Word-line driver
222

BL1
BL1’
BL2BL2’

BLnBLn’

10

121102022002・・・

1・・・

Stored words・・・

Bit-line driver20

1001・・・

1X

X

2X
X

X

OUT1
OUT2

OUTnOutput driver

Input key

0 (Mismatch)
1 (Match)

0 (Mismatch)

Fully parallel search and fully parallel comparison can be done.
TCAM is a “functional memory.”
TCAM is the powerful data-search engine
useful for various applications such as database machine and virus checker innetwork router
TCAM must be implemented more compactly with lower power dissipation.
18

NV-TCAM Cell Function

Stored dataB
01X
don’tcare(b1,b2 )Searchinput

S

Current
comparison

MatchresultML
10

IZ < I Z ’

1

IZ > I Z ’(Mismatch)

0

IZ > I Z ’(Mismatch)

1

IZ < I Z ’(Match)0

IZ < I Z ’(Match)

1

IZ < I Z ’

(0,1)

(1,0)

(0,0)

(Match)00
111(Match)

19

CMOS-based TCAM cell circuit
1-bit storage

Equality-detection(ED) circuit

1-bit storage

MLVDD

Leakagecurrent

WLVSS
BL1Leakage
current

SL’SL

BL2

Transistor counts : 12 (ED;4T, 2-bit storage;8T)
Input/output wires : 8 (BL;2, WL;1, VDD&VSS;2, SL;2, ML;1)
Always supply the power : Many leakage current path
How to realize compact & cut off the leakage current ?
20

MOS/MTJ-hybrid TCAM cell circuit
S. Matsunaga, et al. Applied Physics Express (APEX), 2, 2, 023004, Feb. 2009.

ML/BL

2-bit storage(MTJs)Logic(MTJs & MOSs)

SL’/WL1

SL/WL1•Merge storage into logic circuit : Compact (2T-2MTJ)•Share wires : 4 (ML/BL, SL/WL, No-VDD)•3-D stack structure : Great reduction of circuit area
Compact & nonvolatile TCAM cell with MTJ devices
21Power-Gating Scheme of Bit-Serial NV-TCAM
S. Matsunaga, et al., JJAP 49 (2010) 04DM05.

1st-bit search
111Search word

00

X

SAACC

010

SA0X

1101

2nd-bit search
111Search word

Mismatch

00XSAACC

ACC

Mismatch

010SASAACC

Mismatch

0X

1X

SA

ACC

Match

1010

SA

ACC

Match

11X

1SA

ACC

Match

X

0X

SA

ACC

X

10SA

X

X

1SA

3rd-bit search
111Search word

Mismatch

00X

SA

ACC

Mismatch

ACC

Mismatch

010

SA

ACC

MismatchSA

ACC

Mismatch

0X

1SA

ACC

Mismatch

X

SA

ACC

Mismatch

10X

SA

ACC

Mismatch

10

SA

ACC

Match

110

SA

ACC

Mismatch

1X

1SA

ACC

Match

1X

1SA

ACC

Match

Match

X

0X

SA

ACC

Mismatch

X

0X

SA

ACC

Mismatch

ACC

Match

X

10SAACC

Match

X

10SA

ACC

Mismatch

ACCMatchXX

1SAACCMatch

XX

1SAACCMatch

TCAM cell in standby mode
(Static power is suppressed.)

TCAM cell in active mode
SA Sense amplifier in active mode

SAACC Accumulator in active mode

Sense amplifier in standby mode
(Static power is suppressed.)

According to the word length of the TCAM,
the effectiveness of the standby-power reduction is increased.

22

TCAM cell circuit test chip
3.0 µmChip features

9.8 µmOutputgenerator
inMLSA

TCAM
cellRef.
cellDynamic
current
comparatorinMLSA

Process

0.14µm CMOS/MTJ
1-Poly, 3-Metal

Total area

29.4 µm2

TCAM cell size

3.15 µm2(2.1 µm×1.5 µm) a)

Cell structure

2MOSs-2MTJs

MTJ size

50 nm×200 nm

TMR ratio

167 %Averagewrite current

274 µA (τp = 10 µs) b)

Standby current

0A (Power off)a) A CMOS-based TCAM cell with 12 transistors, whose cell size is 17.54 µm2 under a 0.18 µm CMOS process,has been reported.8) The size of the conventional TCAM cell can be estimated as 10.61 µm2 under a 0.14 µm
CMOS process by scaling down. Thus, the size of the fabricated TCAM cell is reduced to 30 % compared to thatof the conventional one. Moreover, minimum size of the proposed TCAM cell can be considered as 1/6 of theconventional one.
b) More high-speed write operation is possible with increase of write current. For example, with the average currentof 327 µA at 10 ns write.
23

Waveforms of equality-search operations
P : Precharge phasePEPPEPStored data B=1SSearch
dataS=0

S=0Match

10µs

MismatchPE

Stored data B=X

S=1 ・・・・・・780mV

E・・・

Stored data B=0

S=1 ・・・

OUT

PE・・・

CLKMatch
resultE

E : Evaluate phase

S=0

S=1

Match

Match・・・
MatchMismatch

Bit-level equality-search is successfully demonstrated.
24

Waveforms of sleep/wake-up operations

VDD

Power-offPower-off

ActiveP

ActiveE

StandbyPE

P

ActiveE

StandbyP

E

CLKStored data B=0S

S=0Stored data B=0
S=0

OUTbefore=1

OUTafter=1

Match

Match

S=1

S=1

OUTbefore=0

OUTafter=0

Mismatch

Mismatch

OUT
780mV
10µs

Instant sleep/wake-up behavior is successfully demonstrated.
25

Outline• Nonvolatile Logic-in-Memory Architecture
Overview• NV GP-Logic: Nonvolatile-FPGA• NV SP-Logic: Nonvolatile-TCAM• Conclusions & Future Prospects
26

Conclusions
Propose a MOS/MTJ-hybrid circuit (nonvolatile logic-inmemory circuit using MTJ devices) style
Two kinds of typical applications with logic-in-memoryarchitecture; NV-LUT circuit and NV- TCAM
Compact and no static power dissipation
Confirm basic behavior with fabricated test chips
under an MTJ/CMOS process.
It could open an ultra-low-power logic-circuit paradigmFuture Prospects and Issues:
1. Establish the fabrication line
2. Establish the CAD tools
3. Explore the appropriate application fields(Impact towards “Reliability Enhancement”)
27