2011 11th Non-Volatile Memory Technology Symposium

Embedded MRAM Technology
For logic VLSI Application
November 7, 2011
Naoki Kasai1, Shoji Ikeda1,2, Takahiro Hanyu1,3, Tetsuo Endoh1,4,and Hideo Ohno1,2
1Center for Spintronics Integrated Systems, Tohoku University,

JAPAN
2Laboratory for Nanoelectronics and Spintronics, Research Instituteof Electrical Communication, Tohoku University, JAPAN
3Laboratory for Brainware Systems, Research Institute of ElectricalCommunication, Tohoku University, JAPAN
4Center for Interdisciplinary Research, Tohoku University, JAPANhttp://www.csis.tohoku.ac.jp/
Work supported by the FIRST program of JSPS.
1Existing Embedded Memory Market
WW Market@ 2010

MOS Micro

MOS Logic

61B (US$)77B (US$)World Semiconductor Trade Statistics

Applications
EmbeddedMemory

Micro-processor

Micro-computer

ASIC, ASSP, FPGA

(PC, Server, …)(4-32 bit MCUs)(Mobile, Graphic, …)

SRAM L1-L3 cash SRAM
NOR-Flash

Requirements Ultra high speed RAM High speed RAM
Scaling
IssuesSRAM
DRAMHigh speed RAM
Large capacity RAM
Wide band width RAM

Large capacity RAM

Large capacity NVM

Operation margin(Vth variation)
Cell size scaling

Cell size scaling
Reliable NVM

Cell size scaling
Low operation powerLow standby power

Wide temp. range
Low cost

Voltage scaling
Low cost

Key challenge Low Power

Voltage scaling

2

Memory Portfolio
LogiceSRAM
1GHigh-speed

MPU, ASIC ...
 High Speed RAM
 Logic Compatibility• Low Voltage• Design

eSRAM

eSRAM

eDRAM

100M

SRAM DRAM
eFLASH
MRAM, FRAMEEPROMNOR Flash
10M
NAND Flash
10050
105Cell Area Factor, a (a=cell area/F2)

Logic

Read Clock Frequency (Hz)High Performance

Trade-off relation between“performance” and “cost”

eSRAM

eFlash

Logic
eDRAM

MCU
 High Speed NVM
 Various Application• Wide Temp. Range• High Reliability

Graphics …
 Wide Bandwidth Low Power Large Capacity

Low Cost3

Alternative eMRAM
No universal embedded MRAM, but some types ofRead Clock Frequency (Hz)High Performance

MRAMs must be suitable for embedded applications.

1G

High-speed

High speed

eSRAM

eSRAM

eMRAM
eDRAM

100M

SRAM DRAM
eFLASH
MRAM, FRAMEEPROMNOR Flash
10M
NAND FlashHigh density
eMRAM

10050
105Cell Area Factor, a (a=cell area/F2 )Low Cost
4

Embedded MRAM Issues
 Standard CMOS Process compatible
 Suitable memory cell structure► Number of cell components; MTJ, transistor, wiring► Data write scheme; Magnetic Field, STT, ….
 MTJ: Magnetic Tunnel Junction► MR ratioin-plane► Magnetic anisotropy; anisotropy
perpendicularanisotropy

Free Layer
Tunnel Barrier
Fixed Layer

Free Layer
Tunnel Barrier
Fixed Layer► Materials of stacked thin magnetic layers andtunnel barrier film5

CMOS Process Compatible
 MTJs formed in back-end of line, BEOL
► CMOS characteristics unchanged► No Yoke (magnetic clad) lines► Cu & low-k interconnect applicable► 350 ºC thermal stability in BEOL fabrication process
MTJ Formation

Standard CMOS Logic

MTJ

Spintronics CMOS Logic
6Typical MRAM Cells
Cell Type

DataWrite Scheme

No Transistor
0Tr + 1MTJOne Transistor
1Tr + 1MTJ
Write
bit-line

Magnetic Field
induced by write current
through metal wires

Two Transistors
2Tr + 1MTJ

MTJ

MTJ

MTJ

write word-line

by current through MTJ

Domain Wall
Motion (DWM)
by current throughfree layer

unselectedcell

unselectedcell

MTJ

selectedcell

selectedcell

half-selected cell
Probability

Spin Transfer
Torque (STT)

ReadWrite

BarrierBreakdownCurrent

MTJ

Domain Wall

7

High Density eMRAM Cell
Requirements
 Simple cell structure without snake path
 Random access read/write in cell array Scalable MTJ size & write current
 Large magneto-resistance(MR) ratio

Choices
0Tr + 1MTJ
1Tr + 1MTJ
2Tr + 1MTJ
Magnetic Field
STT BEOL process temperature 350 ºC

DWM

 Reliability

Al2O5

Low tunnel current density

MgO

Non-volatality Δ=E/k BT

In plane

MgO

Perpendicular8

CoFeB/MgO/CoFeB MTJ
Large MR Ratio
In-plane anisotropy
pseudo-SV

700604%@RT(1144%@5K)

Cr/Au
Ru (5)Ta(5)CoFeB(6) →MgO(2.1)
CoFeB(5 ) →Ta(5)Ru(10)
Ta(5)
SiO2/Si sub.

CoFeB
MgO
CoFeB

bcc (001)
rock salt(001)bcc(001)

TMR ratio (%) (%)
トンネル磁気抵抗比

600

Tohoku Univ. & Hitachi
500
400300

MgO-barrier MTJs

AIST

CanonANELVA & AIST

AIST

IBM
AIST

200100AlOx-barrier MTJs
Tohoku Univ.

01994 1996 1998 2000 2002 2004 2006 2008 2010

Year年

S. Ikeda et. al., Appl. Phys. Lett. 93, 082508 (2008).

9Dependence of tCoFeB on Anisotropy
Perpendicular Anisotropy
1MgO(1)
CoFeB(tCoFeB )SiO2/Si sub.

Ta=300 oC,
4 kOe, 1h

Ta=300oC

0M (T)Ta(5)
Ru(10)Ta(5)tCoFeB = 2.0 nm

in-planeout-of-plane-11In-planeanisotropy

tCoFeB = 1.3 nm
Ta=300oC

0m0Hs_in-plane = 0.34 T
Ms = 1.58 T
K = 2.1x105 J/m3-1-0.5

Perpendicularanisotropy

0.0µ0H (T)

0.5

1.0

Ikeda et al., Nat. Mat., 9 (2010) pp.721-724
10

CoFeB/MgO/CoFeB MTJ
Perpendicular Anisotropy
V-V+CoFeB(0.9 )Ta(5)Ru(10)
Ta(5)
SiO2/Si sub.

Parallel

40302010(nm)

40 nm

Antiparallel50

R (kΩ)Al2O3

Cr/AuRu (5)Ta(5)
CoFeB(1.5 )MgO(0.9)

-0.2

-0.1

0.0

µ0H (T)

0.1

0.2

Ikeda et al., Nat. Mat., 9 (2010) pp.721-724
11

CoFeB/MgO/CoFeB MTJ
Spin Transfer Torque switching
Cr/Au

Ta(5)
Ru(10)
Ta(5)
SiO2/Si sub.

R (kΩ)

300 µsec

201.0 sec

10-0.2-0.1-910
60.0µ0H (T)-7100.1

0.2-4

τP (sec)

10-510-3-202J (MA/cm2)
10-1

P → AP

44502500

AP → P
010ln(τP/τ0)20Free752-26-25N
SIC (µA)

CoFeB(1.0 )τP =30JC (MA/cm2)

Ru (5)Ta(5)CoFeB(1.7)
MgO(0.85)

TMR ratio =124%
RA = 18 Ωμm2
Hshift = 37 mT
IC0 = 50 µA (P-> AP)- 20 µA (AP-> P)
E/kBT = (∆P )(∆AP )

ReferenceN

Different
polarity=StableS
Parallel state
Low resistanceSNN

The samepolarity=Unstable

S

40 nm

Ikeda et al., Nat. Mat., 9 (2010) pp.721-724

Antiparallel stateHigh resistance12

Stability Enhancement Structure
Conventional structure

Stepped structure

100 nm

100 nm

300 nm
100 nm

100 nm

1.5 nm CoFeB Free Layer
0.9 nm MgO
0.9 nm CoFeB Reference Layer

Hsdipole interlayer
coupling field

∆AP

“1”

CoFeB
MgO
CoFeB
E/kBT

E/kBT“0”

∆P

Hs

“1”

∆AP

“0”

∆P

K. Miura et al., 2011 VLSI Technology, 11B-3.
13

Stability Enhancement Structure
Stepped structure

43

TMR Ratio (%)

10097RA (Ωµm2)

1313

Resistance (kΩ)

Resistance (kΩ)

Conventional structure

2Hs (mT)
1-100-50

050

225100432
1-100

Magnetic field (mT)

10.8
0.6
0.4
0.2
0-150

-75

“AP”->”P”“P”->”AP”

075

050100Magnetic field (mT)

150

∆P

71.2

72.9

∆AP

46.5

70.1

Probability

Probability“AP”->”P”

-50

1
0.8
0.6
0.4
0.2
0-150

-75

“P”->”AP”

075150Magnetic field (mT)

Magnetic field (mT)K. Miura et al., 2011 VLSI Technology, 11B-3.

14

Alternative High Density RAM
1T+1R STT MRAM must have potential to be substituted

Read Clock Frequency (Hz)for not only embedded DRAM but also commodity DRAM.

1G

High-speed

eSRAM

eSRAM

eDRAM

100M

SRAM DRAM
eFLASH
MRAM, FRAMEEPROMNOR Flash
10M
NAND FlashSTTRAM(1T+1R)DRAM(1T+1C)

10050
10
5Cell Area Factor, a (a=cell area/F2)
151G

High speed RAM

ReadCurrent

High-speed

eSRAM

eSRAM

Write
Current

eDRAM

100M

SRAM DRAM
eFLASH
MRAM, FRAMEEPROMNOR Flash
10M
NAND Flash10050105
Cell Area Factor, a (a=cell area/F2)
Probability

Read Clock Frequency (Hz)

Alternative High Speed RAM

ReadWrite

MRAM(2T+1R)

SRAM (6T)High density RAM
Current Path(Read & Write)

Barrier
BreakdownCurrent

STTRAM(1T+1R)DRAM(1T+1C)
16

High Speed eMRAM Cell
RequirementsChoices

 Disturb free cell structure

0Tr + 1MTJ High speed random access read/write Scalable MTJ size & write current
 Large magneto-resistance(MR) ratio BEOL process temperature 350 ºC
 Reliability

1Tr + 1MTJ
2Tr + 1MTJ
Magnetic Field
STT
DWM
Al2O5

Low tunnel current density

MgO

Non-volatality Δ=E/k BT

In plane

Domain Wall

Perpendicular17

Domain Wall Motion(DWM) Writing
Perpendicular Anisotropy•Two Pinning Layers (PL)
•DWM Free Layer (FL)
Hc(PL) >> Hc(FL)Fixed Free Region

FixedSense Layer
Reference
Layer
PinningLayer (1)Pinning
Layer (2)Write Current

Spin
Transfer
TorqueFree Layer Domain Wall
R. Nebashi, et. al.,Sym. VLSI Circuits. p. 300, 2011.
H. Honjo, et. al.,56th MMM Conference, 2011.

Spin
Transfer Write Current
Torque18

Domain Wall Motion(DWM) Reading
In-plane Anisotropy•Sense Layer (SL)•Reference Layer (RL)
Hc(RL) >> Hc(SL)Sense Layer
Reference
Layer
Pinning
Layer (1)Pinning
Layer (2)Free Layer Domain Wall
R. Nebashi, et. al.,Sym. VLSI Circuits. p. 300, 2011.

Sense layer magnetic direction
is changed by stray field from
DWM free layer
Read Current

MTJ
parallel“0”MTJ
anti-parallel“1”

H. Honjo, et. al.,56th MMM Conference, HR-10, 2011.
19

Write Current ( Iw ) Target
1.2

Iw < 0.5mA
3.0
2.5

1.5
1.0
0.5
00Domain wall

0.8
0.6
0.4

[Co/Ni]n0.2
0.0

eMRAM
with normal logic
rule
6T- eSRAMeMRAM
with modified
rule

1.5
0.5
1.0
Write Current (mA)S. Fukami, et. al.,Sym. VLSI Tech.
p. 230, 2009.

RHall (Ohm)Cell Area (a.u.)

2T1MTJ Cell Area

Iwrite (mA)

1.0

Competitive in cost against eSRAM

2.0

W
Co/Pt
Co/Ni

0100200W (nm)CoFeB

S. Fukami ,et. al.
Appl. Phys. Lett.
Vol. 98, 082504, -150-100 -50 0 50 100 150
2011.
Current (µA)
20

DWM NVM Fabrication

140nm

Side view

Front view
R. Nebashi, et. al.,Sym. VLSI Circuits.
p. 300, 2011.

5th-Metal lineIn –Plane MTJ(Sense FL)

PL1
4th-ViaPL2
4th-Via21

FIRST Program Target“Non-volatile logic-in-memory architecture”
Logic with NVM
Static PowerReduction
By NVMLogic► 2 terminal STT► 3 terminal MRAM
► ……

Non-volatilememoryPlease visit our homepage
http://www.csis.tohoku.ac.jp/
New Energy Saving
System on a Chip for
Variety of applications

NV logic-in-memory► NV full adder► NV TCAM► NV flip-flop► NV ……
► NV ……
Storage / Logic merged

nsec

Dynamic Power
Reduction
22

Summary 1T+1MTJ STT(Spin Torque Transfer) MRAM has
the potentials for substitution of embedded DRAM
to apply high density embedded NVM application.
 2T+1MTJ DWM(Domain Wall Motion) MRAM has thepotentials for substitution of embedded SRAM to apply
high speed NVM application.
 These embedded MRAM technology leads to “logic-inmemory architecture” for future new energy saving
SoC(System on a Chip).

23

Acknowledgements
This research is granted by the Japan Society for the Promotionof Science (JSPS) through the “Funding Program for WorldLeading Innovative R&D on Science and Technology (FIRSTProgram),” initiated by the Council for Science and Technology
Policy (CSTP). Prof. Hideo Ohno has been conducting theprogram “Research and Development of Ultra-low Power
Spintronics-based VLSIs“ as the core researcher.
Thanks toK. Miura, H. Yamamoto, K. Misunuma, H. D. Gan, M, Endo, S. Kanai, J. Hayakawa, F. Matsukura,
M. Yamanouchi, J. Hayakawa, R. Kiizumi, S. Fukami, T. Suzuki, K. Nagahara, N. Ohshima, Y. Ozaki,
S. Saito, R. Nebashi, N. Sakimura, H. Honjo, K. Mori, C. Igarashi, S. Miura, N. Ishiwata, K. Kinoshita,Y. Nakatani, Y. Tsuji, R. Nebashi, N. Sakimura, H. Honjo, K. Mori, H. Tanigawa, S. Miura, andT. Sugibayashi
24