A3100
16 ch PHA & LIST
VME module

Rev. 1.5
July 30, 2007㩷ା‫ދ‬೚
Rev 1.0
Rev 1.1

Aug 4, 2004
Sep 2, 2004

Rev 1.2

Dec 1, 2004

Rev 1.3

Feb 20, 2005

Rev 1.31

Feb 20, 2005

Rev 1.4

Apr 4, 2005

Rev 1.5

Jul 30, 2007

ɬ̨ও
ɬᘢᗫᗡ೓
ɬFREE RUN LIST + TLI(Page10)ǩǈǂǤƩɟȮȽȼɭȴɅȸɊȖǶǬୁ᝿ǽȼɭȴ᦯Ǭᣜ៉ǂȐᗡ೓ɬӾɡȭȮȴǬᘐሏǩǈǂǤğ඿‫ܥ‬ʪǬᗲ‫٭ܥ‬ାȐ჉೒ǗȉȀǬĠǩǢǂǤǭǛǬ૥Ȑ૲ᗫ
ɬ3.ѷ̨ɗɭȾǥǬȮɠɭɌȸȽǩᣢǗȉᗫថȐᗡ೓
ɬ3.3 FREE RUN LIST ǩǈǂǤƩTLI ѷ̨଄Ǭ଄ᣜक‫ا‬ӢȈ᝿ǽȴșɔɨȥǬᗫថȐ‫٭‬ା
ɬP9 Ǭᘦ૲‫ג‬Ȑ FREE RUN LIST + TSI ǉȇ FREE RUN LIST + TLI Ƕ‫٭‬ାɬP10 Ǭᘦ૲‫ג‬Ȑ FREE RUN LIST + TLI ǉȇ FREE RUN LIST + TSI Ƕ‫٭‬ା
ɬ3.4 TRIGGERD LIST ʪǬȱɢȤɟȗ(Zero Clear)Ȑа୕ҕ(Initialize)ǩ‫٭‬ା
ɬ4. ɊɢɨȽɆɂɠʪǬ VETO INput ȨɂȤȴǬᘦ૲ϧܶȐ‫٭‬ା
ɬ4. ɊɢɨȽɆɂɠʪǬ Gate/Trigger Input ȨɂȤȴǬᘦ૲઺ǉȇ TLI Ȑтᤓɬ5. ATICbus ʪǬ TIC_CLR+/-͖ӹǬᘦ૲ϧܶȐ‫٭‬ା
ɬ8.2 FREE RUN LIST+TLI Ǧ 8.4 TRIGGERD LIST + TLI ǩ Flip bit Ȑពѣɬ10.23 MCSR ʪǬ TILSEL ɈȸȽǩᗲ‫ܥ‬Ǭ୴̄ȐពᗫɬƳ11. TLI ȼɭȴǩǢǂǤƴȐ૎ᗄពѣ
ɬ12. ˵ౣǩ TLI,TSI ȼɭȴƩȮɠɭɌȸȽƩFast Clear ଄ᣜǬ᦮ဧពѣǈȆǱ Power Ǭ᦮ဧǩͱȐ૲Ⴏ
ɬ5. ATICbus ʪǬሖᅆ৔ৌǬᗲ‫ܥ‬ǩǢǂǤ‫٭‬ାɬϘᎧǩȍǝȈƩ઺ᄾி೓ǩȆȉᗡ೓ɬ2. ɋɢȸȤ‫ג‬ʪǬಐጻᘦ૲઺‫܄‬৏ǏȐ͚೓
ɬ10.23 MCSR Ǭ TB1-TB3 Ȑ TB0-TB2 Ƕ͚೓ɬƳ12. ȟɭɅɭɊɢɭ࿺ཹ଄Ǭ̷‫ٲ‬ခЖ༷ǩǢǂǤƴȐ૎ᗄពѣ
ɬ13. ˵ౣʪǬᄉЧ᥼ဩቒࣕ¤0.1᭫Ȑ¤0.025᭫ǩᘢᗫᗡ೓ɬ10.19AMR ɡȭȮȴǩ PHA SEL ɈȸȽȐពѣ㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
ဧ಼
1. ైᖽ

3

2. ɋɢȸȤ‫ג‬

4

3. ѷ̨ɗɭȾ

5

3.1 PHA

5

3.2 GATED LIST

6

3.3 FREE RUN LIST

8

3.4 TRIGGERED LIST

11

4. ɊɢɨȽɆɂɠ

13

5. ATICbus(Acquire & Time Information Control bus)

14

6. VME șɨȴɭɊȜɭȮ

16

6.1 ɎɭȮȗȾɡȮ

16

6.2 AM(Address Modifier) Code16

6.3 MCST(Multicast) Addressing

16

6.4 VME Interrupt

18

7. Memory

19

8. List Data Buffer

20

8.1 GATED LIST

20

8.2 FREE RUN LIST + TLI

21

8.3 FREE RUN LIST + TSI

21

8.4 TRIGGERED LIST + TLI

21

8.5 TRIGGERED LIST + TSI

21

8.6 ɟȮȽȼɭȴɅȸɊȖǬȼɭȴɟɭȾ22

9. Register Map

24

9.1 Register Address Map

24

9.2 CDR(Channel Dependence Registers) Address Map

25

10. ӾɡȭȮȴǬᘐሏ26

10.1 CCR(Channel Control Register)26

10.2 CZLR(Channel Zero Level Register)26

10.3 CLLDR(Channel Lower Level discriminator Register)27

10.4 CRTR(Channel Real Time Register)27

10.5 CLTR(Channel Live Time Register)27

10.6 CCGR(Channel Conversion Gain Register)28

10.7 CPMR(Channel Preset Mode Register)28

10.8 CPVR(Channel Preset Value Register)29

10.9 SPROICR(Start of Preset ROI Channel Register)29

10.10 NPROICR(Number of Preset ROI Channel Register)29

10.11 IRQVR(IRQ Vector Register)30

10.12 IRQCR(IRQ Control Register)

30

Page 1 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
10.13 MCSTAR(Multicast Address Register)30

10.14 MCSTCRM(Multicast Control Register)31

10.15 LBWPR(List Buffer Write Pointer Register)31

10.16 LBRPR(List Buffer Read Pointer Register)31

10.17 LBEFR(List Buffer Empty Flag Register)32

10.18 LBFFR(List Buffer Full Flag Register)32

10.19 AMR(Acquire Mode Register)33

10.20 ECPVR(Event Count Preset Value Register)34

10.21 LDSPVR(List Data Size Preset Value Register)34

10.22 ACR(Acquire Control Register)35

10.23 MCSR(Module Control Status Register)36

10.24 LBSEMR(List Buffer Semaphore Register)38

10.25 ACSEMR(Acquire Control Semaphore Register)38

11. TLI ȼɭȴǩǢǂǤ

39

11.1 TLI ȼɭȴǦ Flip Bit

39

11.2 TLI ȼɭȴӢ᝿ǽȴșɔɨȥ

40

12. ȟɭɅɭɊɢɭ࿺ཹ଄Ǭ̷‫ٲ‬ခЖ༷ǩǢǂǤ41

13. ˵ౣ

42

Page 2 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷

᭶ ైᖽ
A3100 ǭ 16ch ϗѡǬ PHA & LIST ಐጻȐ੖ᝊǕǝ᭻U ȪșȯǬ 1 ࠌ VME ɗȭɚɭɠǥǗƪӾ Ch ǥǭͥвǩᗲǏȇȊǝϗѡȨɂȤȴǩϗǡǤǍȉ 0ᯃ10V ǼǥǬ೓ీࣕȗȿɢȥɬɆɠȮ͖ӹǬɉɭȤȐటСǕƩǛǬɡɎɠȐɉɭȤɐɭɠȾ‫׌‬ᜀǩȆȈ͔৻ǕǼǗƪӾ Ch ǬɉɭȤɐɭɠȾǉȇǬ͖ӹǭɉɭȤటС᦯ǩɓɠȶɌɡȤȪǥៜ৐ǓȊǝ࢞ƩADC ǩ̽ሦǓȊƩ13bit ǬȼȭȴɠȼɭȴǶ‫੄٭‬ǓȊǼǗƪADC ǭࢭЧဩቒࣕȐઞնǗȉǝǿǩȮɞșȼȘɨȥȮȦɭɠȐਫཽǕǤǂǼǗƪឨࠇǭȮɞșȼȘɨȥȮȦɭɠȐመǽ᝿ǾǦȵșȿɔȸȤɡɨȭǊප‫ݧ‬ǗȉǦǂǄ಻๭Ȑ̔ǂǼǗǊƩA3100 ǥǭǑǬ಻๭ȐཹǘȉǑǦǨ
ǍံǬ 13bit ȼɭȴȐࢣȉˍǊС୸ȉȆǄǩߥ‫ٽ‬Ǌ૒ǓȊǤǂǼǗƪӾ Ch ͥвǩ୊ǗȉǛǬǹǉǬಐጻǦǕǤǭƩɊɠȮȦɭɠǬ¤᭺᭫Ȑ 12 ɈȸȽЧᗛጻǥᗲ‫ܥ‬ӳጻǨȱɢɡɎɠᘬ઴ƩȱɢǉȇɊɠȮȦɭɠ
Ǭ 10%ᆐ‫ב‬ȐԃǖǍ 12 ɈȸȽЧᗛጻǥӳ‫٭‬ǥǋȉ LLD ᘬ઴ǊӳጻǥǀȉǑǦȂƩѷ̨ɗɭȾǩȆȈȧɭȽ͖ӹȂȽɟȡ͖ӹǦǕǤ̳ǂЧǏȉ‫ཽݛ‬ϗѡȨɂȤȴǊཽऴǓȊǤǂǼǗƪ
A3100 Ǌੀ̽Ǘȉѷ̨ɗɭȾǦǕǤǭ PHA ɗɭȾǦ LIST ɗɭȾǊǀȈƩǛȊǜȊҵ໶ǩǼǝǭԃ଄ǩ‫ܩ‬ᕚǗȉˍǊӳጻǥǗƪPHA ɗɭȾǥǭ Ch ǒǦǩཽऴǓȊǝ 8kch§32bit Ǭȼɭȴɖɗɟʚǩϗѡ͖ӹǬɆɠȮɉɭȤᩒǓ VS.࿺ཹᧁ࠱ǬɇȮȽȥɞɕȐ‫ކ‬ᣙǕǼǗƪɟȮȽɗɭȾǩǭ GATED LISTƩFREE RUN LISTƩTRIGGERED LIST Ǭ᭸ǢǬѷ̨ɗɭȾǊǀȈǼǗƪGATEDLIST ɗɭȾǭϘ Ch ϟឨǬȧɭȽϗѡ͖ӹǊံǬ୕ᣜʪǩƩ୊ѭǨϗѡ͖ӹǬǀǡǝ Ch Ǭ AD ‫੄٭‬ȼɭȴǬǽȐɟȮȽȼɭȴɅȸɊȖǩ͔‫܅‬ǕǼǗƪǑǬɗɭȾǥǭ AD ‫੄٭‬ȼɭȴǦϟឨȧɭȽ͖ӹǦǬᣢ͈Ȑ૲႓ǩǗȉǝǿ 28bits șɎɨȽȠțɨȽȼɭȴȀʔ቏ǩ͔‫܅‬ǕǼǗƪFREE RUN LIST ɗɭȾǥǭ໗вǨ୴̄ȐᗲǏǘǩ୊ѭǨϗѡǬǀǡǝ Ch Ǭ AD ‫੄٭‬ȼɭȴȐ଄ᇵЯǩɟȮȽȼɭȴɅȸɊȖǩ͔‫܅‬ǕǼǗƪǑǬ‫ب‬ӿǭ AD ‫੄٭‬ȼɭȴǩᘏࡿǗȉ͖ӹǊϗѡǓȊǝ଄๭Ǭ଄ᣜक‫ا‬Ȁʔ቏ǩ͔‫܅‬ǕǼǗƪTRIGGERED
LIST ɗɭȾǭ‫ؗ‬୛ခǩǭ FREE RUN LIST ɗɭȾǦԃǖǥǗǊƩ଄ᣜक‫ا‬ǊϘ Ch ϟឨǬȽɟȡ͖ӹϗѡǒǦǩа୕ҕǓȊȉ๭ǦƩ͔‫܅‬ǓȊȉȼɭȴǩǭ଄ᣜक‫ا‬ǞǏǥǨǍșɎɨȽȠțɨȽȼɭȴȀԏǼȊȉ๭Ǌ
ྡྷǨȈǼǗƪ
FREE RUN LIST Ǧ TRIGGERED LIST ɗɭȾǩ˸ѣǓȊȉ଄ᣜक‫ا‬ǩǭ TSI(Time Stamp Information)Ǧ
TLI(Time Lag Information)Ǭ 2 ჻᧎ǊǀȈƩǂǘȊȀେ‫ݧ‬ᗣ඿଄ᣜ 5ns ǥ 40bits Ǭक‫ا‬ᠶȐ৻ǟǼǗƪTSI
Ǭ‫ب‬ӿƩFREE RUN LIST ǥǭ඿‫ܥ‬ᣙ‫ڵ‬଄๭ǉȇƩTRIGGERED LIST ǥǭϟឨȽɟȡ͖ӹϗѡǬǀǡǝ଄๭ǉ
ȇӾ Ch ǩ͖ӹϗѡǬǀǡǝ଄๭ǼǥǬሜែ଄ᣜȐᕦǕƩTLI Ǭ‫ب‬ӿǭӾ Ch ǩ͖ӹϗѡǬǀǡǝ଄๭ǉȇ಼Ǭ͖ӹϗѡǬǀǡǝ଄๭ǼǥǬ଄ᣜߪक‫ا‬ȐᕦǕǼǗƪȼɚȗɠɒɭȽɖɗɟǭ 256k§32bits ǬܶᠶȐ৻ǟƩǛǬǄǟ 8k§32bits§16ch=128᮰§32bits Ȑ PHA
ɖɗɟƩ127᮰§32bits Ȑ LIST ɅȸɊȖɖɗɟƩ1k§32bits Ȑѷ̨ɗɭȾȂɆɞɖɭȴᗲ‫ཽܥ‬ǬɡȭȮȴᦸؑǦǕǤཽ̳ǕǤǂǼǗƪ
A3100 ǭ VMEbus Ǭ A24/A32 ȗȾɡȮ৽‫ܥ‬ɗɭȾǩ‫ࢻݘ‬ǕƩD16ƩD32ƩBLT ǬȼɭȴᝀមಐጻǈȆǱ
A32 Ǭ MCST(Multicast Command)ȐȪɒɭȽǕǼǗƪ

Page 3 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷

᭷ ɋɢȸȤ‫ג‬Peak
Detect & HoldSIG IN1

Peak
Detect & HoldSIG IN2

Peak
Detect & HoldSIG IN3

Peak
Detect & HoldSIG IN4

Peak
Detect & HoldSIG IN5

Peak
Detect & HoldSIG IN6

Peak
Detect & HoldSIG IN7

Peak
Detect & HoldSIG IN8Peak
Detect & HoldSIG IN9Peak
Detect & HoldSIG IN10

Peak
Detect & HoldSIG IN11

Peak
Detect & HoldSIG IN12Peak
Detect & HoldSIG IN13

Peak
Detect & HoldSIG IN14

Peak
Detect & HoldSIG IN15

Peak
Detect & Hold

G/T IN0᭿᭿
G/T IN15+

16:1
Multiplexer

14bit ADC

Sliding Scale DAC

VMEbusSlave
Controller
VMEbusSIG IN0

Dual Port
Memory256k x 32bit

᭿᭿Acquisition Control

COM_G/T IN

Sliding Scale Data Correction

FCLR IN
FIFO Control

VETO IN

Event Counter & Register

BUSY OUT

Data
Processing& Control
CPUTime Lag/Stamp Information Counter & Register
IN

ATICbus Control

ATICbus
FIFO
2k x 18bit

OUT

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᭸ ѷ̨ɗɭȾ
A3100 Ǭѷ̨ǭ PHA Ǧ LIST ɗɭȾǩЧ᧎ǓȊƩLIST ǭǓȇǩ GATEDƩFREE RUNƩTRIGGERED LIST ɗɭȾǩЧ᧎ǓȊǼǗƪPHA ɗɭȾǥǭϗѡ͖ӹɆɠȮǬ AD ‫੄٭‬ȼɭȴǉȇ 2 ಼φǬɇȮȽȥɞɕȐ Ch ǒǦǩ̨ওǕǼǗƪLIST ɗɭȾǥǭϗѡ͖ӹɆɠȮǬ AD ‫੄٭‬ȼɭȴǩ TSI(Time Stamp Information)Ʃ
TLI(Time Lag Information)Ǭ଄ᣜक‫ا‬ǼǝǭșɎɨȽȠțɨȽȼɭȴǬǂǘȊǉȐ˸ѣǕǤϗѡ͖ӹǬϗǡǤǋǝ଄ᇵЯ᦯ǩɟȮȽȼɭȴɅȸɊȖǩᗫᢉǕǼǗƪ
PHA Ǧ LIST ɗɭȾǬǂǘȊǉȐԃ଄ǩ‫ܩ‬ᕚǗȉˍǊӳጻǥǗǊƩPHA ɗɭȾǩഁǷǤ LIST ɗɭȾǬૐǊӢȈ঺Ǆक‫ا‬ᠶǊ‫ٵ‬ǂǝǿƩԃ଄‫ܩ‬ᕚǕǝ‫ب‬ӿǭ PHA ɗɭȾҵ໶ǥѷ̨ǓǙǝ‫ب‬ӿǩഁǷǤȮɠɭɌȸȽ
ǊҮЧ˿ʛǩ̞ʛǕǼǗƪѷ̨ɗɭȾȐʔᗌǩǗȉǦ˿ʛǬȆǄǩǨȈǼǗƪ
(1)PHA ɗɭȾ(2)GATED LIST ɗɭȾ

ADC ȼɭȴ 㧗 șɎɨȽȠțɨȽȼɭȴ(3)FREE RUN LIST ɗɭȾ

ADC ȼɭȴ ᭰ TSI/TLI(4)TRIGGERED LIST ɗɭȾ

ADC ȼɭȴ᭰ TSI/TLI ᭰șɎɨȽȠțɨȽȼɭȴ

3.1 PHA
Ch ǒǦǩ໶ᄳǕǝ 8kch§32bits ȼɭȴɖɗɟǩ 2 ಼φɇȮȽȥɞɕȐ̨ওǕǼǗƪɌɟȰȸȽǦǕǤǭReal Time/Live Time/Peak Counts/Integral Counts Ǭ᭹ǢǬɗɭȾǊཽऴǓȊǤǂǼǗƪ

Page 5 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
3.2 GATED LISTǑǬѷ̨ɗɭȾǭƩ໗‫ܥ‬Ǭ୕ᣜϧǩ࿺ཹǗȉˍᚍǬǽȐ਌ǆȉȆǄǨȗɌɟȦɭȬɜɨǩ។ǕǤǂǼǗƪ
Ϙ Ch ϟឨǬȧɭȽйࢨ͖ӹǥǀȉ COM_G/T IN ǬϗѡɡɎɠǊံǬ୕ᣜϧǩӾ Ch ǩϗǡǤǋǝϗѡ͖ӹǭɉɭȤɐɭɠȾǓȊǼǗƪCOM_G/T IN ͖ӹǊᄳǟʛǊȉǦƩ୕ᣜϧǩɉɭȤɐɭɠȾǓȊǤǂǝ
Ch ǬɉɭȤɡɎɠȐ᦯಼ AD ‫੄٭‬ǕƩࢣȇȊǝ 1 ͥ˿ʚǬ AD ‫੄٭‬ȼɭȴǩșɎɨȽȠțɨȽȼɭȴȐ˸ѣǕǤɟȮȽȼɭȴɅȸɊȖǩୁǋ᝿ǽǼǗƪǢǼȈ 1 șɎɨȽࡿȈǬɆȦȸȽȼɭȴǭ COM_G/T IN ୕ᣜʪǩ୊ѭǨϗѡǬǀǡǝલǬ ADC ȼɭȴǦșɎɨȽȠțɨȽȼɭȴǩȆȈౝওǓȊǼǗƪǨǈƩșɎɨȽȠțɨȴǭ COM_G/T IN Ǭ͖ӹǩȆȈșɨȤɟɖɨȽǕǼǗƪӾ Ch ǬɉɭȤɐɭɠȾ‫׌‬ᜀǊ COM_G/T IN ୕ᣜϧǩɉɭȤɐɭɠȾǗȉ͖ӹǭ୕ᣜϧǥǬେ‫ٺ‬ɆɠȮᩒǓƩȀǕǍǭ୕ᣜϧǥେаǩϗǡǤǋǝɆɠȮᩒǓǬǧǟȇǉȐៜ৐ǗȉǑǦǊС୸ǼǗƪ
6 ɏɭȭǩ GATED LIST ɗɭȾǬȴșɔɨȥȶɘɭȽȐᕦǕǼǗƪʚǬȦɭȮǊ COM_G/T IN ୕ᣜϧǬେ‫ٺ‬ɆɠȮȐɉɭȤɐɭɠȾǗȉ‫ب‬ӿƩʛǬȦɭȮǭେаǬɆɠȮɉɭȤȐɐɭɠȾǗȉ‫ب‬ӿǬ̷ǥǗƪେ‫ٺ‬ɆɠȮǼǝǭେаǬɆɠȮǬǧǟȇȐɐɭɠȾǗȉǉǭ MCSR ɡȭȮȴϧǬɉɭȤɐɭɠȾɗɭȾɬɈ
ȸȽǬᗲ‫ܥ‬ǥШȈ୆ǆǼǗƪ᭭Ƴ10.23 MCSR(Module Control Status Register)ƴȐӘ຋᭮ǑǬȴșɔɨȥȶɘɭȽǬ̷ǥǭƩ಼ǬȆǄǨȼɭȴǊɟȮȽȼɭȴɅȸɊȖǩୁǋ᝿ǼȊǼǗƪADC(IN0)ADC(IN1)

ǑȊǊ᭶Event(=1COM_G/T IN ͖ӹ)ǀADC(IN3)

ǝȈǬɆȦȸȽȼɭȴEC(n+1)˿࢞ƩɆȦȸȽȼɭȴǊ଄ᇵЯǩሴǍƪǨǈƩୁǋ᝿ǽȼɭȴǬȆȈᘐሏǨϧܶǩǢǂǤǭƳ8.1 GATED LISTƴȐӘ຋ǕǤǍǞǓǂƪ

Page 6 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
ƖGATED LIST(COM_G/T ୕ᣜϧǬେ‫ٺ‬ɆɠȮȐɉɭȤɐɭɠȾǗȉ‫ب‬ӿǬ̷)

IN0

IN1

IN2

IN3

COM_G/TIN

State

Idle

Track & Peak Hold

ADC

Event
CountsIN0EC(n)EC(n+1)ƖGATED LIST(COM_G/T ୕ᣜϧǬେаǬɆɠȮȐɉɭȤɐɭɠȾǗȉ‫ب‬ӿǬ̷)

IN0

IN1

IN2

IN3

Page 7 of 43

Idle

Conversion

Settling

IN1IN3㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
3.3 FREE RUN LISTǑǬѷ̨ɗɭȾǥǭƩӾ Ch ǩϗǡǤǋǝɆɠȮǬϗѡ᦯ǩ ADC ȼɭȴȐɟȮȽȼɭȴɅȸɊȖǩᗫᢉǕǤǂǋǼǗƪǛǬ᤮ǩҵǩ ADC ȼɭȴǞǏǥǨǍƩӾ Ch ǩϗǡǤǍȉ͖ӹǬ଄ᣜဪᣢȐၥȉဧခǥTSI(Time Stamp Information)Ǽǝǭ TLI(Time Lag Information)Ǭ଄ᣜक‫ا‬Ȑʔ቏ǩᗫᢉǕǼǗƪTSI ǭ඿‫ܥ‬ᣙ‫ڵ‬଄๭ǉȇ͖ӹǊϗǡǤǋǝ଄ǼǥǬሜែ଄ᣜȐᕦǕƩTLI ǭ଄ᣜခǩᤱȈӿǄϗѡ͖ӹᣜǬ଄ᣜߪȐᕦǕǼǗƪTSIƩTLI ϟǩ଄ᣜᗣ඿Ǭ‫ؗ‬ෛǦǨȉԣ൓લǭ 5ns/10ns/20ns/50ns/100ns/200ns/500ns/1Ìs Ǭʪǉȇ̆ऴǩៜ৐ӳጻǥǗƪTSI/TLI Ǭ଄ᣜक‫ا‬ǭ 40bits ǬɈȸȽࠌȐ৻ǡǤǂȉǬǥେ‫ٺ‬ᗣ඿଄ᣜǭៜ৐Ǖǝ‫ؗ‬ෛȤɢȸȤǩȆȈ˿ʛǬȆǄǩǨȈǼǗƪ
‫ؗ‬ෛȤɢȸȤେ‫ٺ‬ᗣ඿଄ᣜ

5ns

1.52hrs

10ns

3.05hrs

20ns

6.10hrs

50ns

15.2hrs

100ns

30.5hrs

200ns

2.5days

500ns

6.3days1Ìs

12.7days

TLI Ǭ‫ب‬ӿǩǭϗѡ͖ӹᣜǬ଄ᣜߪक‫ا‬ǥǗǉȇƩ‫ؗ‬ෛȤɢȸȤ=5ns Ȑៜ৐ǕǤȀ͖ӹᣜǬ଄ᣜߪǊ
1.52hrs Ȑ᛫ǆȉȆǄǨȦɭȮǭዥǆȇȊǼǙȑǊƩTSI Ǭ‫ب‬ӿǭ඿‫ܥ‬ᣙ‫ڵ‬ǉȇ 1.52hrs ሜែǗȉǦȟɭɅɭɊɢɭǕƩȱɢǩধǡǤǕǼǄ๭ǩǒྒྷऴǍǞǓǂƪ
TSI Ǭሜែ଄ᣜȐӢȈ᝿Ǿȴșɔɨȥǭ಼Ǭ 2 ឨȈǬʪǉȇៜǴǑǦǊС୸ǼǗƪ1 ྟဧǭ A3100 ϧ៺ǬɉɭȤటСȴșɔɨȥǥǗƪPeak Detect & Hold ‫׌‬ᜀǊϗѡ͖ӹǬɉɭȤȐటСǕǝ଄๭ǥ଄ᣜक‫ا‬Ȑ႓‫ܥ‬ǕǼǗƪ2 ྟဧǭӾ Ch ǩᗲǏȇȊǤǂȉ G/T IN ȨɂȤȴǉȇǬȽɟȡϗѡ͖ӹǩȆȈ଄ᣜक‫ا‬ȐӢȈ᝿ǽǼǗƪɉɭȤటСȴșɔɨȥǩȆȉૐ്ǭϗѡ͖ӹǬɆɠȮᩒǓǩȆȈɉɭȤటСȴșɔɨȥǊ‫٭‬ҕǗȉǝǿ೓႓Ǩ଄ᣜक‫ا‬ȐӢȈ᝿ǽǝǂ‫ب‬ӿǩǭʜԈǋǥǗǊƩ‫៺ٲ‬ǩȴșɔɨȥᇵǬ‫׌‬ᜀȐᗲǏȉǑǦǨǍɞɊǨ଄ᣜဪᣢǊࢣȇȊȊǮᎽǂ‫ب‬ӿǨǧǩཽ̳ǕǼǗƪȆȈ೓႓Ǩ଄ᣜဪᣢȐࢣǝǂ‫ب‬ӿǭƩ
CFD(Constant Fraction Discriminator)ǨǧǬȴșɔɨȥᇵ‫׌‬ᜀǉȇǬ͖ӹȐ G/T IN ǩਮሴǕǤ඿‫ܥ‬ǗȉˍȐਰ‫ڗ‬ǕǼǗƪ
TLI Ǭ଄ᣜߪक‫ا‬Ǭ‫ب‬ӿǭ A3100 ϧ៺ǬɉɭȤటСȴșɔɨȥǬǽǦǨȈǼǗƪ
TLI Ǭ‫ب‬ӿǭϗѡ͖ӹᣜǬ଄ᣜߪक‫ا‬ȐࢣȉǑǦǊဧခǥǗǉȇƩ1 ஍Ǭ A3100 ǥȠɅɭǥǋȉ 16ch ˿ϧǨȇ‫ࢻݘ‬ӳጻǥǗǊƩ16ch ˿ʚǬȬȮȻɕǬ‫ب‬ӿǭᖜલ஍ǬɗȭɚɭɠȐཽ̳ǗȉǑǦǩǨȈϘǤǬ ChᣜǬ଄ᣜߪȐࢣȉˍǊС୸ǨǍǨȈǼǗƪࢢǡǤ 16ch ˿ʚǬȬȮȻɕǬ‫ب‬ӿǩǭ TSI ɗɭȾǥᗣ඿ǗȉˍǩǨȈǼǗƪ̛ǕƩǑǬ‫ب‬ӿȀᖜલɗȭɚɭɠᣜǥǬ‫ؗ‬ෛȤɢȸȤȂ඿‫ܥ‬йࢨǬԃ୕Ȑ႓͔ǗȉࢴᖽǊǀȈƩ˸‫އ‬ՅǬ IC(Interconnect Card)ȐɊɢɨȽɆɂɠʚǬ ATICbus(Acquire & Time Information
Control bus) ǩӢȈ˸ǏǤᤱԃٟǬɗȭɚɭɠᣜȐਮሴǗȉࢴᖽǊǀȈǼǗƪ

Page 8 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
Ɩ FREE RUN LIST + TLI(Peak Detect ȴșɔɨȥǩȆȉ଄ᣜक‫ا‬ǬӢȈ᝿ǽ)

IN0

IN1

IN2

IN3

Time
Lag
tl1

ADC

tl2

IN1

tl3

IN0

tl4

IN3

tl5

tl6

IN0

IN1

tl7

IN3

tl8

IN1

tl9

tl10

IN0

IN3

tl11

IN0

tl12

tl13

IN1

IN3

tl14

IN0

IN1

ǑǬ̷ǥǭƩ಼ǬȆǄǨȼɭȴǊɟȮȽȼɭȴɅȸɊȖǩୁǋ᝿ǼȊǼǗƪADC(IN1)
tl1
ADC(IN0)
tl2
ADC(IN2)
tl3
ADC(IN0)
tl4
ADC(IN1)
tl5
ADC(IN2)
tl6
ADC(IN1)
tl7
ADC(IN0)
tl8
ADC(IN2)
tl9
ADC(IN0)t10
ADC(IN1)
tl11
ADC(IN2)
tl12
ADC(IN0)
tl13
ADC(IN1)
tl14
ǨǈƩୁǋ᝿ǽȼɭȴǬȆȈᘐሏǨϧܶǩǢǂǤǭƳ8.2 FREE RUN LIST + TLIƴȐӘ຋ǕǤǍǞǓǂƪ
Page 9 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
Ɩ FREE RUN LIST + TSI(G/T ϗѡ͖ӹȴșɔɨȥǩȆȉ଄ᣜक‫ا‬ǬӢȈ᝿ǽ)IN0
G/T IN0

IN1
G/T IN1

IN2
G/T IN2

IN3
G/T IN3

Time
Stamp
tS1

ADC

tS2 tS3

IN1

tS4

IN0

IN3

tS5

tS6 tS7

IN0

IN1

tS8

IN3

tS9

IN1

tS10 tS11 tS12

IN0

IN3

IN0

tS13 tS14

IN1

IN3

IN0

ǑǬ̷ǥǭƩ಼ǬȆǄǨȼɭȴǊɟȮȽȼɭȴɅȸɊȖǩୁǋ᝿ǼȊǼǗƪADC(IN1)
ts1
ADC(IN0)
ts2
ADC(IN2)
ts3
ADC(IN0)
ts4
ADC(IN1)
ts5
:
:
:
:
:
ADC(IN2)
ts12
ADC(IN0)
ts13
ADC(IN1)
ts14
ǨǈƩୁǋ᝿ǽȼɭȴǬȆȈᘐሏǨϧܶǩǢǂǤǭƳ8.3 FREE RUN LIST + TSIƴȐӘ຋ǕǤǍǞǓǂƪ
Page 10 of 43

IN1㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
3.4 TRIGGERED LISTǑǬѷ̨ɗɭȾǭƩ‫ؗ‬ෛǦǨȉȽɟȡේǩᘜ࿺ǓȊǤཹǘȉȆǄǨˍᚍȐ଄ᣜሜែǦϟǩ਌ǆȉȆǄǨȗ
ɌɟȦɭȬɜɨǩ។ǕǤǂǼǗƪ
Ϙ Ch ϟឨǬȽɟȡ͖ӹȐ COM_G/T IN ǩϗѡǕǤཽ̳ǕǼǗƪ‫ؗ‬୛ခǨѷ̨ǭ FREE RUN LIST ǦೢǧԃǖǥǗǊƩྡྷǨȉǬǭ TSI Ǽǝǭ TLI ǬͱǊ COM_G/T IN ͖ӹǬϗѡǒǦǩа୕ҕǓȊȉ๭ǥǗƪࢢǡǤ
Ӿ Ch Ǭ ADC ȼɭȴǩ˸ᤨǗȉ TSI Ǽǝǭ TLI Ǭ଄ᣜक‫ا‬ǭϟឨȽɟȡ͖ӹ࿺ཹǉȇǬሜែ଄ᣜǼǝǭ଄ᣜߪȐᕦǗˍǩǨȈǼǗƪȀǄʔǢǬဪ៉๭ǭ ADC ȼɭȴǩǭ TSI Ǽǝǭ TLI Ǭ଄ᣜक‫ا‬ǬǹǉǩșɎɨȽȠțɨȽȼɭȴǊ˸ѣǓȊǼǗƪșɎɨȽȠțɨȽǭϟឨȽɟȡ͖ӹ COM_G/T ͖ӹǩȆȈșɨȤɟɖɨȽǓȊƩϟឨȽɟȡ͖ӹǦ ADC ȼɭȴǦǬ‫ࢻݘ‬ᣢ͈Ȑ૲႓ǩǕǼǗƪ
11 ɏɭȭǩʔ̷ǦǕǤӾ Ch Ǭ G/T ͖ӹǩȆȉ TSI क‫ا‬ӢȈ᝿ǽᗲ‫ܥ‬଄ǬȴșɔɨȥȶɘɭȽȐ‫ג‬ႯǕǼǄƪTLI Ǭ‫ب‬ӿȀ଄ᣜक‫ا‬ǊȴșɕȮȴɨɌǉȇȴșɕɞȥǩ˽ȍȉǞǏǥƩǛǬ˶ǭԃǖǥǗƪǑǬ‫ب‬ӿǬɟȮȽȼɭȴɅȸɊȖǶǬୁǋ᝿ǽȼɭȴǭ˿ʛǬឨȈǥǗƪ
ADC(IN1)
ts1
EC(n)ADC(IN0)ts2
EC(n)ADC(IN2)
ts3
EC(n)ADC(IN0)ts4
EC(n+1)ADC(IN1)
ts5
EC(n+1)ADC(IN2)ts6
EC(n+1)ADC(IN1)
ts7
EC(n+1)ADC(IN0)ts8
EC(n+1)ADC(IN2)ts9
EC(n+1)ADC(IN0)ts10
EC(n+1)ADC(IN1)
ts11
EC(n+1)ADC(IN2)ts12
EC(n+1)ADC(IN0)ts13
EC(n+2)ADC(IN1)
ts14
EC(n+2)
ǨǈƩୁǋ᝿ǽȼɭȴǬȆȈᘐሏǨϧܶǩǢǂǤǭƳ8.4 TRIGGERED LIST + TSIƴȐӘ຋ǕǤǍǞǓǂƪ
Page 11 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
ƖTRIGGERED LIST + TSI(G/T ϗѡ͖ӹȴșɔɨȥǩȆȉ଄ᣜक‫ا‬ǬӢȈ᝿ǽ)IN0
G/T IN0

IN1
G/T IN1

IN2
G/T IN2

IN3
G/T IN3

Time
Stamp
tS1

InitializetS2 tS3

Initialize
tS4

tS5

tS6 tS7

tS8

tS9

tS10 tS11 tS12

tS13 tS14

COM_G/T IN

EventCounts

ADC

EC(n)

IN1

EC(n+1)

IN0

IN3

IN0

IN1

IN3

EC(n+2)

IN1

Page 12 of 43

IN0

IN3

IN0

IN1

IN3

IN0

IN1

㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷

᭹᭳ɊɢɨȽɆɂɠ



Data ReaDY LED(቎)ɟȮȽɗɭȾ଄ƩɟȮȽȼɭȴɅȸɊȖǩᘧǽСǗǷǋȼɭȴǊ‫ק܅‬ǗȉǦǋ
๭๝ƪ



16 ch
PHA&LIST

A3100

BUSY LED(ᛟ)ǂǘȊǉǬ ch ǩǈǂǤɉɭȤɐɭɠȾᣙ‫ڵ‬ǉȇ AD ‫੄٭‬ȐሖǆǤ FIFO ǩୁ
ǋ᝿ǼȊȉǼǥǬ୕ᣜƪǈȆǱɟȮȽɗɭȾǬ‫ب‬ӿǩǭƩɟȮȽȼɭȴɅȸɊȖǊɊɠǬ໦ेǩǀȉ଄ǩ๭๝ƪ

%86<

'5'<
90(

6,*1$/ *7
,1
,1


VME LED(ᬮ)
VMEbus ǉȇ୛ɗȭɚɭɠǶȗȤȰȮ
Ǌǀȉ೾ǩ๭๝ƪ







SIGNAL INput
AD ‫੄٭‬Ǘȉ 0ᯃ᭰10V ǥେ‫ݦ‬ᄳʚȈ଄
ᣜ 200nsƩେ‫ݧ‬ɆɠȮࠌ 500ns Ǭ೓ీࣕɛɀɒɭɞɆɠȮȐϗѡǕǼǗƪ
Zin᭿1᮰ÀƩLEMO







Fast CleaR INputϘǤǬɉɭȤɐɭɠȾ‫׌‬ᜀȐȤɟȗǕƩឳᕚʪǬ AD ‫੄٭‬ȐʪૌǕǤƩ૎ǝǨ͖ӹǬӣǏϗȊǊӳጻǨ໦ेǩǕǼǗƪେ‫ݧ‬ɆɠȮࠌ 20ns ǬȗȤȻȘɋɬɄșǬ͖ӹȐϗѡǕǼǗƪ
Signal : TTLƩZin᭿1᮰ÀƩLEMO







)&/5 &20B*7,1,1

VETO INputϗѡ͖ӹǊံǬᣜƩAD ‫੄٭‬ǕǝȼɭȴȐၷ௻ǕǼǗƪ
ȗȤȻȘɋɬɄșǬ͖ӹȐϗѡǕǼǗƪ
Signal : TTLƩZin᭿1᮰ÀƩLEMO

Gate/Trigger INputǑǬϗѡ͖ӹǭѷ̨ɗɭȾǩȆȈཽ̳ဧ
ခǊྡྷǨȈǼǗƪ
FREE RUN LIST Ǽǝǭ TRIGGERD LIST ɗɭȾǥƩǉǢ MCSR ɡȭȮȴǬ TILSEL Ɉ
ȸȽ=”1” (35 ɏɭȭӘ຋)Ǭ‫ب‬ӿǭƩǑǬϗѡ͖ӹǊ TSI ଄ᣜक‫ا‬ӢȈ᝿ǽǬȽɟȡ͖ӹǦǕǤཽ̳ǓȊǼǗƪǑǬ‫ب‬ӿǭେ‫ݧ‬ɆɠȮࠌ 20ns ǬȗȤȻȘɋɬɄșǬ͖ӹȐϗѡǕǼǗƪ
ʚᗫ˿‫ٲ‬Ǭѷ̨୴̄ǩǈǂǤǭƩȧɭȽ͖ӹǦǕǤཽ̳ǕƩǑǬ͖ӹǊӾ Ch ǬɉɭȤటСȴșɔɨȥǩǈǂǤံǥǀǡǝ‫ب‬ӿǩǬǽɉɭȤɐɭɠȾȐᕚǂƩAD‫੄٭‬Ȑ‫ܩ‬ᕚǕǼǗƪTTL ͖ӹȐϗѡǕƩᘵ༷ǭӾ Ch ǩᗲǏȇȊǤǂȉ CCR ɡȭȮȴǬ GM0,GM1 ɈȸȽ(26 ɏɭȭӘ຋)Ǭᗲ‫ܥ‬ǩȆȈ COIN/ANTI/OFF ǬǂǘȊǉǩៜ৐ӳጻǥǗƪ
Signal : TTLƩZin᭿1᮰ÀƩLEMO

9(72 %86<,1287$7,&EXV,1 287

Acquire & Time Information Control
bus IN/OUT
1 ஍˿ʚǬ୛ɗȭɚɭɠȐཽ̳ǕǤ
FREE RUN LIST + TSI Ǽǝǭ TRIGGERED
LIST + TSI Ǭѷ̨ȐǓǙȉ‫ب‬ӿǭᤱԃٟǬɗȭɚɭɠȐǑǬȨɂȤȴȐдཽǕǤɅȮਮሴǗȉࢴᖽǊǀȈǼǗƪᘐሏ
ǭƳ5. ATICbusƴȐӘ຋ǕǤǍǞǓǂƪ

COMmon Gate/Trigger INputǑǬϗѡ͖ӹǭѷ̨ɗɭȾǩȆȈཽ̳
ဧခǊྡྷǨȈǼǗƪGATED LIST Ǭ‫ب‬ӿǭƩǑǬ͖ӹǊံǬ୕ᣜǩǬǽϘ Ch ǬɉɭȤɐɭɠȾȐᕚǂƩ͖ӹǊ΍ǩǨǡǝ଄๭ǉȇ AD ‫੄٭‬Ȑᣙ‫ڵ‬ǕǼǗƪǼǝǑǬ͖ӹǥșɎɨȽȠțɨȽȐșɨȤɟɖɨȽǕǼǗƪ
TRIGGERED LIST ǥǭƩǑǬ͖ӹǊံǩǨǡǝȴșɔɨȥǥ TSI ȀǕǍǭ TLI Ǭ଄ᣜक‫ا‬ȐȱɢȤɟȗǗȉǦǦȀǩƩșɎɨȽȠțɨȽȐșɨȤɟɖɨȽǕǼǗƪʚᗫ˿‫ٲ‬ǬɗɭȾǥǭϘ Ch ϟឨǬȧɭȽ͖ӹǦǕǤಐጻǕƩǑǬ͖ӹǊӾ ChǬɉɭȤటСȴșɔɨȥǩǈǂǤံǥǀǡǝ‫ب‬ӿǩǬǽɉɭȤɐɭɠȾȐᕚǂƩAD ‫੄٭‬Ȑ‫ܩ‬ᕚǕǼǗƪȧɭȽ/Ƚɟȡ͖ӹǂǘȊǬ‫ب‬ӿȀେ‫ݧ‬ɆɠȮࠌ 20ns Ǭ͖ӹȐϗѡǕǼǗƪᘵ༷ǭ MCSR ɡȭȮȴǬ CGM0,CGM1
ɈȸȽ(35 ɏɭȭӘ຋)Ǭᗲ‫ܥ‬ǩȆȈȧɭȽ͖ӹǬ‫ب‬ӿǭ COIN/ANTI/OFF,Ƚɟȡ͖ӹǬ‫ب‬ӿǩǭȗȤȻȘɋɬɄș/ɢɭǬǂǘȊǉǩៜ৐ӳጻǥǗƪ
Signal : TTLƩZin᭿1᮰ÀƩLEMO

BUSY OUTɈȭɭ໦ेȐᕦǗСѡ͖ӹǥƩBUSY LEDԃǖ໦ेǩǀȉᣜƩɄșɡɎɠǬ͖ӹȐСѡǕǼǗƪ
Signal : TTLƩLEMO ȨɂȤȴ
Page 13 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
᭺᭳ATICbus(Acquire & Time Information Control bus)
ϗѡલǊ 16ch ˿ʚǬȬȮȻɕǩǈǂǤɟȮȽȼɭȴȐȴșɕȮȴɨɌǬ଄ᣜक‫ا‬Ǧʔ቏ǩᗣ඿Ǘȉ‫ب‬ӿǭƩᖜલǬɗȭɚɭɠᣜǥǬȤɢȸȤȂ଄ᣜʚǬȤɟȗƩ඿‫ܥ‬ᣙ‫ڵ‬Ǭԃ୕ȐӢȉࢴᖽǊཹǖǼǗƪATICbusǭǑǬဧခȐៈওǗȉǝǿǩཽऴǓȊǤǈȈƩ˸‫އ‬Ǭ IC(Interconnect Card)ȐཽǂǤᤱȈӿǄɗȭɚɭɠǬ OUT-IN ᣜȐਮሴǕǤɅȮȐౝওǕǼǗƪIC ǭߦᤱǬ
Module1-1

Module1-2

Module1-3 Module1-4

ATICbus-OUT ȨɂȤȴǦӷᤱǬ IN ȨɂȤȴȐਮሴǗȉȆǄǩᖇ၀ǕǼǗƪ
ATICbus ǩǭ LVDS(LowVoltage Differential Voltage)ɡ
ɎɠǬ଄ᣜक‫ا‬ȐᗣલǗȉȠțɨȴȤɢȸȤ TIC_CLK+/-Ǧ

%86<

'5'<

%86<

'5'<

%86<

'5'<

%86<

'5'<

90(

90(

90(

90(

6,*1$/ *7,1,1

6,*1$/ *7,1,1

6,*1$/ *7,1,1

6,*1$/ *7,1,1

Ȥɟȗ TIC_CLR+/-ƩǈȆǱ LVCMOS ɡɎɠǬ඿‫ܥ‬йࢨ͖
ӹ COM_START*ǊԏǼȊǼǗƪ









̷ǆǮߦ‫ג‬ǬȆǄǩ Module-1ᯃ4 ǼǥǬ 4 ஍Ȑ IC ǥɅȮ









ਮሴǗȉǦƩModule-1 ǊɓȮȴƩModule-2 Ǧ 3 ǭʪᣜǩ









̝ኲǗȉȮɡɭɋƩModule-4 ǭେ࢞ǬȮɡɭɋɑɭȾǥǀ









ȉȆǄǩᎉѷခǩౝওǓȊǼǗ᭭ǑǬक‫ا‬ǭ MCSR ɡȭȮ









ȴǬ M/S0ƩM/S1 ɈȸȽǩȆȈၥȉˍǊС୸ǼǗ᭮ƪ

















































COM_START*͖ӹǭȟɭɌɨȾɡșɨǩȆȉ Wired-Or Ǭ









ਮሴࢆेȐǦȈƩɓȮȴǊǑǬ͖ӹȐȾɞșɋǕǼǗƪࢢǡ









ǤϘǤǬȮɡɭɋɗȭɚɭɠǭɓȮȴɗȭɚɭɠǩԃ୕Ǖ









Ǥ඿‫ܥ‬Ǭᣙ‫ڵ‬/ሖˉƩ଄ᣜक‫ا‬ȠțɨȴǬᗣલᣙ‫ڵ‬ǊȨɨȽ









ɢɭɠǓȊȉˍǩǨȈǼǗƪ









)&/5 &20B*7,1,1)&/5 &20B*7,1,1)&/5 &20B*7,1,1

TIC_CLK+/-Ǧ TIC_CLR+/-͖ӹǭɓȮȴǥǀȉ Module-1 ǊȾɞșɋǕƩϘǤǬȮɡɭɋǭɡȬɭɅǦǨȈƩϘɗȭɚɭ
ɠǊϟឨǬȤɢȸȤǈȆǱȤɟȗ͖ӹȐཽ̳ǕǼǗƪ)&/5 &20B*7,1,1

ATICbus ȐਮሴǗȉ᤮ǩࢹȊǤǭǨȇǨǂ‫ٺ‬ШǨЖኲǊȀǄʔǢǀȈǼǗƪǛȊǭ LVDS ͖ӹǬሖᅆ৔ৌǬӢ঺ǥǗƪሖᅆ৔ৌȐ‫ܩ‬ᖇǗȉǬǭେ࢞ǬȮɡɭɋǞǏǩǕƩɓȮȴǦ

9(72 %86<,1
287

9(72 %86<,1
287

9(72 %86<,1
287

9(72 %86<,1287$7,&EXV,1 287$7,&EXV,1 287$7,&EXV,1 287$7,&EXV,1 287

Interconnect
Card

Interconnect
Card

InterconnectCardʪᣜǬȮɡɭɋǭϘǤሖᅆ৔ৌȐ‫ٲ‬ǗࢴᖽǊǀȈƩ಼ɏɭȭᗫᝊǬɑɭȾʚǬȮșȸȶ SW4 ȐǢǌǬȆǄǩᗲ‫ܥ‬ǕǼǗƪ
᭿

ϘǤ ON

ɬɓȮȴ᭬ʪᣜǬȮɡɭɋ᭿ϘǤ OFFɬେ࢞ǬȮɡɭɋ˿ʚǊ ATICbus ǩᣢǗȉᘦ૲ǥǗǊƩϗѡલǊ 16ch ˿ʚǥȀѷ̨ɗɭȾǩȆǡǤǭ ATICbus ਮሴǗȉࢴᖽǬǨǂ‫ب‬ӿǊǀȈǼǗƪǕǉǕលǩ 16ch ˿ϧǥǕǉѷ̨ǓǙȉˍǊС୸Ǩǂѷ̨ɗɭȾȀǀȈǼǗǬǥൖऴǊࢴᖽǥǗƪ
Page 14 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
˿ʛǩӾѷ̨ɗɭȾǩǈǏȉ Ch લǬйᤋƩ୴̄ǨǧǩǢǂǤᘦ૲ǕǼǗǬǥӘዥǩǕǤǍǞǓǂƪ
ѷ̨ɗɭȾ

йᤋɬ୴̄
໗ǩйᤋƩ୴̄ǭǨǕ᭭16ch ˿ʚǥȀ ATICbus ਮሴǬࢴᖽǭ๽ǂ᭮GATED LIST໗ǩйᤋƩ୴̄ǭǨǕ᭭16ch ˿ʚǥȀ ATICbus ਮሴǬࢴᖽǭ๽ǂ᭮

FREE RUN LIST + TSI

16ch ˿ʚǬ‫ب‬ӿǭ ATICbus ਮሴǕǨǏȊǮǨȇǨǂ

FREE RUN LIST + TLI

16ch ˿ϧǥǕǉཽ̳С୸ǼǙȑ

TRIGGERED LIST + TSI

16ch ˿ʚǬ‫ب‬ӿǭ ATICbus ਮሴǕǨǏȊǮǨȇǨǂ

TRIGGERED LIST + TLI

16ch ˿ϧǥǕǉཽ̳С୸ǼǙȑ

) 

 

$%

 

& '(

6:

) 



6:

 
) 



$%



& '(

 

$%



&'(

PHA Ǭǽ

6:

6:

Page 15 of 43 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷

᭻᭳VME șɨȴɭɊȜɭȮ
6.1 ɎɭȮȗȾɡȮ
A3100 ǭ 1Mbyte(256᮰§32bits)ǬɖɗɟȐ੖ᝊǕǤǈȈƩVMEbus ǩ‫ݘ‬ǕǤ 0x00000ᯃ0xFFFFF ǬȗȾɡȮᦸؑȐҹ୊ǕǼǗǊƩǑȊȐ VMEbus ϘȗȾɡȮᄗᣜǬ̣ЖǩѓȈࡿǤȉǬǉȐനǿȉǬǊɎɭȮȗȾɡȮǬᗲ‫ܥ‬ǥǗƪɎɭȮȗȾɡȮǬᗲ‫ܥ‬ǭхᦫǬɑɭȾ‫ܩ‬ᖇ‫ג‬ǩ‫ג‬ႯǓȊǤǂȉ SW1ᯃSW3 ǬȮșȸȶǥᕚǂǼǗƪ
SW1ᯃSW3 ǭʛ‫ג‬ǬౣǩǛȊǜȊ VMEbus ȗȾɡȮǬ A32-28ƩA27-24ƩA23-20 ǩ‫ࢻݘ‬ǕǤǈȈƩA32ȗȾɡȮ৽‫ܥ‬ɗɭȾǥǭϘǤǬȮșȸȶƩA24 ȗȾɡȮ৽‫ܥ‬ɗɭȾǥǭ SW3 Ǭᗲ‫ܥ‬ǬǽǊ୊ѭǦǨȈǼǗƪ

A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

A32:

SW1

SW2

SW3

A24:

§

§

SW3

A3100 ੖ᝊɖɗɟǬȗȾɡȮᄗᣜ

6.2 AM(Address Modifier) codeɎɭȮȗȾɡȮȐ˰ǕǤ A3100 ǩȗȤȰȮǗȉ‫ب‬ӿǩȪɒɭȽǓȊǤǂȉ AM ȨɭȾǭ˿ʛǬឨȈǥǗƪ
AM codeDescription

0x3F

A24 supervisory block transfer(BLT)

0x3D

A24 supervisory data access

0x3B

A24 non privileged block transfer(BLT)0x39

A24 non privileged data access

0x0F

A32 supervisory block transfer(BLT)

0x0D

A32 supervisory data access

0x0B

A32 non privileged block transfer(BLT)0x09

A32 non privileged data access

6.3 MCST(Multicast) Addressingᖜલ஍Ǭ A3100 ɗȭɚɭɠǬԃʔǬɡȭȮȴǩƩԃǖϧܶǬȼɭȴȐୁǋ᝿Ǿ‫ب‬ӿƩឨࠇǨȇ VME ɓȮȴɬɗȭɚɭɠǭ஍લЧǞǏǬȗȤȰȮȐኋឆǗࢴᖽǊǀȈǼǗǊƩǑǬ MCST ȗȾɡȸȬɨȥȐдཽǗȉǦ᭶‫׌‬ǬȗȤȰȮȐ‫ܩ‬ᕚǗȉǞǏǥϘǤǬɗȭɚɭɠǶǬୁ᝿ǽǊԃ଄ǩ‫ˉܞ‬ǗȉǦǂǄɖɟȸȽǊǀȈǼǗƪ̛ǕƩɗȭɚɭɠǊ MCST ȗȾɡȸȬɨȥǩ೓ࠇǩࢻᅭǗȉǝǿǩǭ˿ʛǬ୴̄ȐූǝǕǤǂǨ
ǏȊǮǨȈǼǙȑƪ
(1) ȗȤȰȮӳጻǨ AM ȨɭȾǭ಼Ǭ 2 ឨȈƪ
0x0D(A32 supervisory data access)
0x09(A32 non privileged data access)(2) ୁǋ᝿ǽȪșȤɠǬǽƪ(3) MCST ȗȾɡȸȬɨȥǩࢻᅭǗȉȆǄǩɡȭȮȴǊ೓ǕǍᗲ‫ܥ‬ǓȊǤǂȉɗȭɚɭɠǬǽƪ

Page 16 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
(1)Ǧ(2)ǭ VME ɓȮȴɬɗȭɚɭɠǬɌɢȥɞɔɨȥǞǏǥᗛനǥǋȉ୴̄ǥǗǊƩ(3)ǭ A3100 ǬɡȭȮȴᗲ‫ܥ‬ǩǢǂǤ೓ǕǍ༷ᗛǕƩᗲ‫ܥ‬ǗȉࢴᖽǊǀȈǼǗƪMCST ȗȾɡȸȬɨȥǩᣢ͈ǬǀȉɡȭȮȴǭ MCST Address Reg.Ǧ MCST Control Reg.Ǭ 2 ǢǥƩǛȊ
ǜȊ಼ǬȆǄǩᗲ‫ܥ‬ǕǼǗƪƖMCST ɎɭȮȗȾɡȮȐᗲ‫ܥ‬Ǘȉƪ
Ƴ6.1 ɎɭȮȗȾɡȮƴǥ‫ܥ‬ዉǕǝȗȾɡȮᄗᣜǩᕚǄឨࠇǬȗȤȰȮǦƩMCST ǩȆȉȗȤȰȮǬȗ
ȾɡȮᄗᣜȐЧǏȉǝǿǩƩMCST ȗȾɡȸȬɨȥཽǬɎɭȮȗȾɡȮȐ MCST Address Reg.ǩᗲ‫ܥ‬ǕǼǗƪVME ȗȾɡȮǬ A31-A24 Ǌ MCST Address Reg.ǩᗲ‫ܥ‬Ǖǝ 8bits ǬͱǩᅥǕǍƩǓȇǩ
A23-A20 ǼǥǬ 4bits ǊǗǷǤȱɢǥǀȉ‫ب‬ӿǬȗȾɡȮᄗᣜǊ MCST ȗȾɡȸȬɨȥǬӳጻǨᦸؑǦǨȈǼǗƪMCST ȗȾɡȸȬɨȥǩࢻᅭǓǙǝǂɗȭɚɭɠǩǭϘǤԃǖͱȐ MCST Address Reg.ǩ
ᗲ‫ܥ‬ǕǼǗƪ

A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0MCST Address Reg.

0 0 0 0

A3100 ੖ᝊɖɗɟǬȗȾɡȮᄗᣜƖɗȭɚɭɠǬȶȜɭɨ᭭ǢǨǊȈ᭮Ȑᗲ‫ܥ‬ǗȉƪMCST ǬȗȤȰȮȪșȤɠǭϘǤǬɗȭɚɭɠǩ‫ݘ‬ǕǤʔ઼ǩԃ଄ǩ‫ܩ‬ᕚǓȊȉȍǏǥǭǀȈǼǙȑƪ
VMEbus Ǭ IACKIN/IACKOUT ȼșȭɭɬȶȜɭɨȐཽ̳ǕǤƩȗȤȰȮǗȉǑǦǬС୸ȉಀдȐᕦǗȽɭȤɨȐɗȭɚɭɠǉȇ಼ǬɗȭɚɭɠǶǦමǕƩȽɭȤɨȐࢣǝɗȭɚɭɠǞǏǊୁǋ᝿ǽȪșȤɠȐ‫ܩ‬ᕚǕǼǗƪICAKIN/ICAKOUT ǬȼșȭɭɬȶȜɭɨȐཽ̳ǕǼǗǉȇȽɭȤɨǭ VMEbus ɅȸȤɌɡɭɨǬȮɢȸȽྟӹǬ‫ݦ‬ǓǨȮɢȸȽǩᖇ၀ǓȊǝɗȭɚɭɠǉȇ‫ٺ‬ǋǨȮɢȸȽྟӹǬɗȭɚɭɠǶǦɆȮǓȊǤǂǍǑǦǩǨȈǼǗǊƩҵǩȮɢȸȽǩɗȭɚɭɠǊᖇ၀ǓȊǤǂȉǞǏǥǭȽɭȤɨǭ೓ǕǍɆȮǓȊǤǂǋǼǙȑƪMCST ȗȤȰȮǩ‫ݘ‬ǕǤࢻᅭǗȉɗȭɚɭɠǬȶȜɭɨȐMCST Control Reg.ǩ೓ǕǍᗲ‫ܥ‬ǕǤǈǍࢴᖽǊǀȈǼǗƪMCST Control Reg.ǩǭ 2 ǢǬɈȸȽǊ಼ǬȆǄǩ‫ܥ‬ዉǓȊǤǂǼǗƪ
F bit

L bit

statusMCST ȶȜɭɨϧǥǬɗȭɚɭɠǬ̝ኲ

00inactiveେаǼǝǭେ࢞˿‫ٲ‬Ǭɗȭɚɭɠ

0

1

activeେ࢞Ǭɗȭɚɭɠ

1

0

activeେаǬɗȭɚɭɠ

11

activeେаǦେ࢞ǩਃǼȊǝʪᣜǩ̝ኲǗȉɗȭɚɭɠେаǬɗȭɚɭɠǦǭƩMCST ȗȤȰȮǩࢻᅭǓǙǝǂɗȭɚɭɠǬችǊȈǬʪǥେȀ‫ݦ‬ǓǨȮɢȸȽྟӹǩᖇ၀ǓȊǤǂȉɗȭɚɭɠǬǑǦǥǗƪେ࢞Ǭɗȭɚɭɠǭលǩ MCST ȗȤȰȮǩࢻᅭǓǙǝǂɗȭɚɭɠǬችǊȈǬʪǥେȀ‫ٺ‬ǋǨȮɢȸȽྟӹǩᖇ၀ǓȊǤǂȉɗȭɚɭɠǬǑǦǥǗƪ
ʪᣜǩ̝ኲǗȉɗȭɚɭɠǩ FƩL bit ϟǩ 0 Ȑᗲ‫ܥ‬Ǖǝ‫ب‬ӿǭ inactive ǨɗȭɚɭɠǦǕǤбૌǓȊȉǝǿୁǋ᝿ǽȐ‫ܩ‬ᕚǕǼǙȑǊƩȽɭȤɨǭ಼ǬɗȭɚɭɠǶ೓ࠇǩɆȮǕǼǗƪMCST ȗȾɡȸȬɨȥǭ VMEbus ɓȮȴɬɗȭɚɭɠǬ MCST ȗȾɡȮᄗᣜǶǬୁǋ᝿ǽȪșȤɠᣙ‫ڵ‬ǥ‫ڵ‬ǼȈƩǼǘǭ F,L bit=1,0 ǬେаǬɗȭɚɭɠǊୁǋ᝿ǽȐᕚǂǼǗƪୁǋ᝿ǽǊ‫ˉܞ‬ǗȉǦȽɭȤɨȐ
IACKOUT ǩСѡǕƩ಼ǬɗȭɚɭɠǶȗȤȰȮಀȐමǕǼǗƪ಼ǬɗȭɚɭɠǭǛǬȽɭȤɨǊ IACKINǩϗǡǤǋǝˍȐၥȉǦୁǋ᝿ǽȪșȤɠȐ‫ܩ‬ᕚǕǼǗƪ˿ᤉƩେ࢞ǬɗȭɚɭɠǼǥǑǬѷ̨ȐኋȈឆ
Page 17 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
ǕƩେ࢞ǬɗȭɚɭɠǊୁǋ᝿ǽȐሖǆȉǦ VMEbus Ǭȼɭȴᝀមࢻᅭǥǀȉ DTACK ɞșɨȐȾɞșɋǕǼǗƪVMEbus ɓȮȴɬɗȭɚɭɠǭ DTACK ȐӣǏǤƩаǿǤǑǬୁǋ᝿ǽɅȮȪșȤɠȐሖˉǗȉǑǦǩǨȈǼǗƪ
˿ʚǬǑǦǉȇƩMCST ȗȾɡȸȬɨȥǩǭ಼Ǭ 2 ǢǬ๭ǥൖऴǊࢴᖽǥǗƪ(1) MCST ȗȾɡȸȬɨȥǭϘǤǬɗȭɚɭɠǊԃʔȴșɔɨȥǥୁǋ᝿ǽȐᕚǄȍǏǥǭǨǂǑǦƪ
(2) MCST ȶȜɭɨȐౝওǗȉɗȭɚɭɠǬʪᣜǩᄗǋȮɢȸȽǊǀǡǤǭǨȇǨǂǑǦƪ̛Ǖ Auto
Daisy Chain ‫ࢻݘ‬ǬɅȸȤɌɡɭɨǥǀȊǮǑǬᤋȈǥǭǀȈǼǙȑƪ

6.4 VME Interrupt
A3100 Ǌ VMEbus ǶѓȈ᝿ǽȐ࿺ཹǗȉᖽ‫׍‬ǦǕǤǭƩɟȮȽȼɭȴɅȸɊȖǶǬȼɭȴୁǋ᝿ǽ໦െǩ৮ȉ 2 ឨȈǊǀȈǼǗƪ
ƖɟȮȽȼɭȴȪșȯǩȆȉѓȈ᝿ǽɟȮȽȼɭȴɅȸɊȖǩୁǋ᝿ǼȊǝȼɭȴȪșȯǊ List Data Size Preset Reg.Ǭᗲ‫ͱܥ‬ȐȟɭɅɭǕǝȇѓȈ᝿ǽȐ࿺ཹǕǼǗƪ඿‫ܥ‬Ǌʔ଄ʪૌǓȊȉǑǦǨǍሳሴǕǤᕚǆȉȆǄǩǗȉǩǭୁǋ᝿ǽȼɭȴǥɟȮȽȼɭȴɅȸɊȖǊʔ୻ǩǨȉхǩƩɟȮȽȼɭȴɅȸɊȖǬȼɭȴȐ។ࡿǨᧁ࠱ǥࠇǩᘧǽСǕǤȂȉǑǦǊࢴᖽǩǨȈǼǗƪឨࠇǥǭ List Data Size Preset Reg.ǩɟȮȽȼɭȴɅȸɊȖȪșȯǬᇹҮЧǬͱȐᗲ‫ܥ‬ǕǤѓȈ᝿ǽȐ࢙ǟǼǗƪǛǄǗȉǦ VMEbus ɓȮȴǊѓȈ᝿ǽ࿺ཹȐӣǏǤɟȮȽȼɭȴɅȸɊȖǬᘧǽСǕȐᕚǡǤǂȉᣜǩȀƩ೥ȈҮЧǬᄗǋᦸؑǩ૎ǝǨ඿‫ܥ‬ȼɭȴȐୁǋ᝿ǾǑǦǊС୸ǼǗƪǕǉǕ
ǨǊȇǑȊǭǀǍǼǥȀϘ Ch ϗѡ͖ӹǩȆȈཹǘȉୁǋ᝿ǽȼɭȴᠶǬɡɭȽǦ VMEbus ɓȮȴǩȆȉᘧǽСǕᝀមɡɭȽǊਮចǕǤǂȉ‫ب‬ӿǥǀȈƩʧዧǬɅɞɨȮǊ‫ٺ‬ǋǍྡྷǨȉ‫ب‬ӿǩǭ List Data
Size Preset Reg.ǩᗲ‫ܥ‬ǗȉͱȀǛȊǩࢻǖǤటᗦǕǨǈǗࢴᖽǊǀȈǼǗƪ
ƖșɎɨȽȠțɨȽલǩȆȉѓȈ᝿ǽșɎɨȽȠțɨȽલǊ EventCount Preset Reg.Ǭᗲ‫ͱܥ‬ȐȟɭɅɭǕǝȇѓȈ᝿ǽȐ࿺ཹǕǼǗƪǑǬѓȈ᝿ǽǭșɎɨȽȠțɨȽǊȠțɨȽȗȸɌǗȉ GATED LIST Ǽǝǭ TRIGGERED LIST Ǭ‫ب‬ӿǞǏǩ୊ѭǥǗƪǼǝ EventCount Preset Reg.Ǭᗲ‫ͱܥ‬ǦഁᝈǓȊȉșɎɨȽȠțɨȽલǦǭșɎɨȽȠțɨȽͱǛǬȀǬǬር‫ͱݘ‬ǥǭǨǍƩѓȈ᝿ǽ࿺ཹǉȇ಼ǬѓȈ᝿ǽ࿺ཹ଄ǼǥǬșɎɨȽȠțɨȽǬߪЧǬલǦǨȈǼǗƪ
COM_G/T IN ϗѡɆɠȮ 1 ͥǩȆȉ 1 șɎɨȽࡿȈǬɟȮȽȼɭȴɅȸɊȖୁǋ᝿ǽȼɭȴȪșȯǭƩ
ǛǬǦǋǩ͖ӹϗѡǬǀǡǝ Ch લǩ̾‫܅‬ǗȉǬǥʔైǩૌ‫ܥ‬С୸ǼǙȑǊƩେ‫ͱٺ‬ǭ 16ch ϘǤǩϗǡǤǋǝ‫ب‬ӿǥƩGATED LIST᭿17§32bitsƩTRIGGERED LIST᭿48§32bits ǬȼɭȴȪșȯǦǨȈǼǗƪ
លǩƩେ‫ͱݦ‬ǭ GATED LIST ɗɭȾǩǈǂǤ 1ch Ǖǉ͖ӹϗѡǊ๽ǉǡǝ‫ب‬ӿǬ 2§32bits ǥǗƪࢢǡǤᗲ‫ܥ‬ӳጻǨșɎɨȽȠțɨȽɬɌɟȰȸȽǬେ‫ͱٺ‬ǭɅȸɊȖȪșȯǩȆȉᤋྎǉȇ 127k§32bits/2§32bits=65024(0xFE00)ǦǨȈǼǗƪ
߸୒ǗȉѓȈ᝿ǽ࿺ཹ଄Ǭѓ᝿ǽɡɎɠǭ IRQ Control Reg.ǩƩǼǝѓ᝿ǽࢻᅭȪșȤɠ଄ǩ VMEbusɓȮȴǩȆǡǤᘧǽСǓȊȉѓ᝿ǽ Status/ID ǭ IRQ Vector Reg.ǩа୕ᗲ‫ܥ‬ǕǤǈǋǼǗƪ
A3100 ǉȇǬѓ᝿ǽ͖ӹǭࡿɗȭɚɭɠǶǬѓ᝿ǽࢻᅭȪșȤɠ‫ܩ‬ᕚ଄๭ǥᗛᤓǓȊǼǗƪ

Page 18 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷

᭼᭳Memory
256k§32bits Ǭɖɗɟǩǭ Ch0ᯃCh16 ǼǥǬ PHA ɖɗɟǩ 128᮰§32bitsƩɟȮȽȼɭȴɅȸɊȖǩ 127᮰§32bitsƩɡȭȮȴᦸؑǩ 1᮰§32bits ǊѓȈࡿǤȇȊǤǂǼǗƪӾ PHA ɖɗɟǬȼɭȴȪșȯǭ 8kch§32bits ǥƩϧ៺Ǭȼɭȴౝឬǭʛ‫ג‬ǬឨȈǥǗƪɟȮȽȼɭȴɅȸɊȖǩǢǂǤǭƳ8. List Data BufferƴƩɡȭȮȴǩǢǂǤǭƳ9. Register MapƴȐӘ຋ƪ
D31
BA+0x00000
ch0 PHA
BA+0x08000
ch1 PHA
BA+0x10000
ch2 PHA
BA+0x18000
ch3 PHA
BA+0x20000
ch4 PHA
BA+0x28000
ch5 PHA
BA+0x30000
ch6 PHA
BA+0x38000
ch7 PHA
BA+0x40000
ch8 PHA
BA+0x48000
ch9 PHA
BA+0x50000
ch10 PHA
BA+0x58000
ch11 PHA
BA+0x60000
ch12 PHA
BA+0x68000
ch13 PHA
BA+0x70000
ch14 PHA
BA+0x78000
ch15 PHA

D24 D23Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]
Ch0[HH]
᭿
Ch8191[HH]

D16 D15
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]
CH0[HL]᭿CH8191[HL]

D8 D7
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]
Ch0[LH]
᭿
Ch8191[LH]

BA+0x80000

List Data Buffer(127k x 32bits)

BA+0xFEFFC
BA+0xFF000

Register(1k x 32bits)
BA+0XFFFFC

  (BA: Base Address)
Page 19 of 43

D0
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]
Ch0[LL]᭿
Ch8191[LL]㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
᭽᭳List Data BufferɟȮȽȼɭȴǭɢɨȥɤɭȾ(32bits)ҵ̝ǥɟȮȽȼɭȴɅȸɊȖǩୁǋ᝿ǼȊƩǛǬϧܶǭӾѷ̨ɗɭȾǩȆȈ‫٭‬ҕǗȉǝǿƩӾȼɭȴǬʚ̝ 3bits ǩǭǛǬȼɭȴǊǧǬȆǄǨϧܶǬȀǬǥǀȉǉȐᕦǗ
DID(Data IDentification)ɈȸȽǊ‫ܥ‬ዉǓȊǤǂǼǗƪ
DIDNo.

D31

D30

D29

Description

0

0

0

0

(Reserved)

1

0

0

1

(Reserved)

2

0

1

0

GATED LIST ɗɭȾ଄Ǭ ADC ȼɭȴ

3

0

1

1

șɎɨȽȠțɨȽȼɭȴ

4

1

0

0

TLI-HI + ADC ȼɭȴ

5

1

0

1

TLI-LO ȼɭȴ

6

1

1

0

TSI-HI + ADC ȼɭȴ

7

1

1

1

TSI-LO ȼɭȴ˿ᤉƩӾɟȮȽѷ̨ɗɭȾǩǈǏȉȼɭȴౝឬȐᘦ૲ǕǼǗƪ

8.1 GATED LIST
1 șɎɨȽࡿȈǬɟȮȽȼɭȴɅȸɊȖǩୁǋ᝿ǼȊȉȼɭȴǭƩ1 ͥᯃ16 ͥǼǥǬʛ‫(ג‬a)ǩႯǗ ADC
ȼɭȴǦ(b)ǬșɎɨȽȠțɨȽȼɭȴǉȇওȈᄳǟƩADC ȼɭȴǬલǭșɎɨȽ࿺ཹ଄ǩ͖ӹϗѡǬǀǡǝ Ch લǩȆȈ‫٭‬ҕǕǼǗƪ
D31 D30 D29

D27(a) 0 1 0

D23 D22DSN

D18 D17

NAI

D14

D12

D0

Ch#

ADC Data

ɬCh#: ϗѡǬǀǡǝȶɘɨɂɠྟӹ(0 – 0xF)
ɬNAI(Number of Active Input): ϗѡǬǀǡǝ Ch Ǭቍલ(1 – 0x10)
ɬDSN(Data Sequence Number): ϋᦽǬ ADC ȼɭȴǉȇǬឨǕྟӹ(1 - NAI)
D31 D30 D29

D27

D0

(b) 0 1 1

Event Counts(28bits)

ʔ̷ǦǕǤ COM_G/T IN Ǭ୕ᣜʪ Ch0ƩCh2ƩCh3ƩCh6ƩCh10 ǩϗѡǊǀȈƩ಼Ǭ COM_G/T IN ୕ᣜʪǩǭ Ch1ƩCh3ƩCh14 ǩϗѡǊǀǡǝ‫ب‬ӿǭƩ˿ʛǬȆǄǨȼɭȴǊɟȮȽȼɭȴɅȸɊȖǩୁǋ᝿ǼȊǼǗƪ
D31 D30 D29

D27

0 1 0

0 0 0 0 1 0 0 1 0 1 0 0 0 0

ADC Data(ch0)0 1 0

0 0 0 1 0 0 0 1 0 1 0 0 1 0

ADC Data(ch2)0 1 0

0 0 0 1 1 0 0 1 0 1 0 0 1 1

ADC Data(ch3)0 1 0

0 0 1 0 0 0 0 1 0 1 0 1 1 0

ADC Data(ch6)0 1 0

0 0 1 0 1 0 0 1 0 1 1 0 1 0

ADC Data(ch10)

0 1 1

D23 D22

D18 D17

D14

D12

D0

Event Counts(n)0 1 0

0 0 0 0 1 0 0 0 1 1 0 0 0 1

ADC Data(ch1)0 1 0

0 0 0 1 0 0 0 0 1 1 0 0 1 1

ADC Data(ch3)0 1 0

0 0 0 1 1 0 0 0 1 1 1 1 0 0

ADC Data(ch14)

0 1 1

Event Counts(n+1)

Page 20 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
8.2 FREE RUN LIST + TLI᭶ϗѡ͖ӹǀǝȈ಼Ǭ 2 ǢǬɢɨȥɤɭȾȼɭȴǥౝওǓȊǼǗƪ
D31 D30 D29 D28

D18 D171 0 0

D14 D13 D12
Flip
Ch#
Bit

TLI-HI(11bits)

D0

ADC Data

ɬCh#: ϗѡǬǀǡǝȶɘɨɂɠྟӹ(0 – 0xF)
ɬTLI-HI: Time Lag Information(Higher 11bits)
ɬFlip bit: TLI ȼɭȴǬȨșɨȬȼɨȮȐбૌǗȉɈȸȽƪᘐሏǭƳ11.TLI ȼɭȴǩǢǂǤƴȐӘ຋ƪ
D31 D30 D29 D28

D0

1 0 1

TLI-LO(29bits)

ɬTLI-LO: Time Lag Information(Lower 29bits)

8.3 FREE RUN LIST + TSI᭶ϗѡ͖ӹǀǝȈ಼Ǭ 2 ǢǬɢɨȥɤɭȾȼɭȴǥౝওǓȊǼǗƪ
D31 D30 D29 D28

D18 D17

1 1 0

D14

TSI-HI(11bits)

D12

Ch#

D0

ADC Data

ɬCh#: ϗѡǬǀǡǝȶɘɨɂɠྟӹ(0 – 0xF)
ɬTSI-HI: Time Stamp Information(Higher 11bits)
D31 D30 D29 D28

D0

1 1 1

TSI-LO(29bits)

ɬTSI-LO: Time Stamp Information(Lower 29bits)

8.4 TRIGGERED LIST + TLI᭶ϗѡ͖ӹǀǝȈ಼Ǭ 3 ǢǬɢɨȥɤɭȾȼɭȴǥౝওǓȊǼǗƪ
D31 D30 D29 D28

D18 D171 0 0

D14 D13 D12
Flip
Ch#
Bit

TLI-HI(11bits)

D0

ADC Data

ɬCh#: ϗѡǬǀǡǝȶɘɨɂɠྟӹ(0 – 0xF)
ɬTLI-HI: Time Lag Information(Higher 11bits)
ɬFlip bit: TLI ȼɭȴǬȨșɨȬȼɨȮȐбૌǗȉɈȸȽƪᘐሏǭƳ11.TLI ȼɭȴǩǢǂǤƴȐӘ຋ƪ
D31 D30 D29 D28

D0

1 0 1

TLI-LO(29bits)

ɬTLI-LO: Time Lag Information(Lower 29bits)
D31 D30 D29

D27

D0

0 1 1

Event Counts(28bits)

8.5 TRIGGERED LIST + TSI᭶ϗѡ͖ӹǀǝȈ಼Ǭ᭸ǢǬɢɨȥɤɭȾȼɭȴǥౝওǓȊǼǗƪ
D31 D30 D29 D28

D18 D17

1 1 0

D14

TSI-HI(11bits)

D12

Ch#

D0

ADC Data

ɬCh#: ϗѡǬǀǡǝȶɘɨɂɠྟӹ(0 – 0xF)
ɬTSI-HI: Time Stamp Information(Higher 11bits)
D31 D30 D29 D28

D0

1 1 1

TSI-LO(29bits)

ɬTSI-LO: Time Stamp Information(Lower 29bits)
D31 D30 D29

0 1 1

D27

D0

Event Counts(28bits)
Page 21 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
8.6 ɟȮȽȼɭȴɅȸɊȖǬȼɭȴɟɭȾɟȮȽȼɭȴɅȸɊȖǭɟɨȥɅȸɊȖǦǕǤಐጻǗȉȆǄǩౝওǓȊǤǈȈƩWrPtr(ୁǋ᝿ǽɒșɨȴ)Ʃ
RdPtr(ᘧǽСǕɒșɨȴ)Ǭ 2 ǢǬɒșɨȴǦ EmpFlg(ȝɨɌȻȘɬɊɞȥ)ƩFullFlg(ɊɠɬɊɞȥ)Ǭ 2 ǢǬɊɞȥǩȆǡǤᆈ༷ǓȊǼǗƪ
ɟȮȽȼɭȴɅȸɊȖǩୁǋ᝿ǼȊȉȼɭȴǭɢɨȥɤɭȾɬȪșȯǊʔǢǬҵ̝ǦǨǡǤǂȉǝǿƩ
WrPtr Ǧ RdPtr ǭɟȮȽȼɭȴɅȸɊȖᣙ‫ڵ‬ȗȾɡȮǉȇǬȟɊȰȸȽȐɢɨȥɤɭȾલǥᕦǕƩ0ᯃ
0x1FBFF(0ᯃ127᮰-᭶)ǼǥǬᆐ‫ב‬ǬͱȐ৻ǟǼǗƪ
WrPtr ǭ A3100 ǊϧܶȐା૎Ǖ VMEbus ɓȮȴɬɗȭɚɭɠǭǛȊȐӘ຋ǕǼǗƪលǩ RdPtr ǭ VMEbusɓȮȴɬɗȭɚɭɠǊϧܶȐା૎Ǖ A3100 ǭǛȊȐӘ຋ǕǼǗƪFullFlg ǭ A3100 ǊȰȸȽǕ VMEbus ɓȮȴɬɗȭɚɭɠǩȆǡǤȤɟȗǓȊǼǗǊƩEmpFlg ǭ VMEbus ɓȮȴɬɗȭɚɭɠǩȆǡǤȰȸǓȊ
A3100 ǊǛȊȐȤɟȗǕǼǗƪ
ࢢǡǤƩVMEbus ɓȮȴɬɗȭɚɭɠǊɟȮȽȼɭȴɅȸɊȖȐɟɭȾǗȉ᤮ǭɒșɨȴǦɊɞȥȐ೓ǕǍᆈ༷ǗȉࢴᖽǊǀȈǼǗƪ˿ʛǩǛǬম᦯Ǭʔ̷ȐႯǕǼǗǬǥӘዥǩǕǤǍǞǓǂƪ
#define BUFMAX
0x1FC00
struct list{
unsigned long Buffer[BUFMAX];
unsigned long space1[(0xFF410-0xFF000)/4];
unsigned long wr_ptr;
unsigned long rd_ptr;
unsigned long emp_flg;
unsigned long full_flg;
unsigned long space2[(0xFFFC0-0xFF420)/4];
unsigned long buf_sem;};#define LIST(*(struct list *)BA + 0x80000)
unsigned longrd_buf[BUFMAX], data_siz, n;// ǑǬ̷ǥǭཽ̳ǕǨǂɡȭȮȴᦸؑ// BA+0xFF410// ǑǬ̷ǥǭཽ̳ǕǨǂɡȭȮȴᦸؑ// semaphore reg. BA+0xFFFC0

if( !LIST.emp_flg ){data_siz = (LIST.wr_ptr > LIST.rd_ptr)? (LIST.wr_ptr – LIST.rd_ptr): (BUFMAX – LIST.rd_ptr) + LIST.wr_ptr;
n = 0;
while(data_siz--){rd_buf[n++] = LIST.buffer[LIST.rd_ptr++];if( LIST.rd_ptr >= BUFMAX )LIST.rd_ptr = 0;}
LIST.buf_sem = 0;// (a) Request to get semaphore token
While( LIST.buf_sem )// (b)wait until shared resource will be released;if( LIST.full_flg )LIST.full_flg = 0;
If( LIST.rd_ptr == LIST.wr_ptr )LIST.emp_flg = 1;
LIST.buf_sem = 1;// (c)releas semaphore token}໗ǩൖऴǗǷǋ๭ǭƖɟɨȥɅȸɊȖǨǬǥ WrPtr Ǧ RdPtr Ǭ‫ݦٺ‬ᣢ͈ǊលᝀǗȉǦǋǊǀȉƪ
ƖȨɖɨȽ(a)ᯃ(c)ǬɒșɨȴȐӘ຋ǕǤɊɞȥǬб‫ܥ‬ȐᕚǄ‫ب‬ӿǬਥ˶йࢨƪǑǬ̷ǥǭ Empty ǉǧǄǉȐб‫ܥ‬Ǘȉǝǿǩ RdPtr Ǧ WrPtr ǬͱȐഁᝈǕǼǗǊƩWrPtr ǭဪমΉǊϧܶȐୁǋ੄ǆȉǬǥƩWrPtr ȐɟɭȾǕƩഁᝈǕƩб‫ܥ‬ȐʛǗǼǥǬᣜǩ WrPtr ǬϧܶǊ‫٭‬ҕǗȉǦƩ‫ܩ‬᤮Ǭ໦െǦб‫ܥ‬ሟஎǩၡာǬཹǖȉȦɭȮǊ࿺ཹǕǼǗƪǑǬժᧆȐᗛനǗȉǝǿǩཽऴǓȊǤǂȉ
ǬǊȰɓɊȞɬɡȭȮȴǥƩǑǬɡȭȮȴȐ˰ǕǤȗȤȰȮಀȐࢣǝዧǞǏǊϟ୊ᚽේǩȗȤȰȮǥǋ
Page 22 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
ȉǦǂǄਥ˶йࢨȐ‫ܩ‬༴ǕǼǗƪǛǬম᦯ǭ(1) ȰɓɊȞɬɡȭȮȴǩ 0 Ȑୁǋ᝿ȑǥȗȤȰȮಀȐᖽഘǕǼǗƪ(2) ȰɓɊȞɬɡȭȮȴǬϧܶǊ 0 ˿‫ٲ‬ǨȇƩϟ୊ᚽේȐဪমΉǊཽ̳ǕǤǂȉǬǥ 0 ǩǨȉǼǥ࢙ǟǼǗƪ(3) ȰɓɊȞɬɡȭȮȴǬϧܶǊ 0 ǨȇƩȗȤȰȮӳጻǨǬǥࢴᖽǨЖ༷ȐᕚǂǼǗƪ(4) Ж༷ǊሖˉǕǝȇƩȰɓɊȞɬɡȭȮȴǩ᭶Ȑୁǋ᝿ȑǥϟ୊ᚽේȐᗛઠǕǼǗƪ
᭭ʚᗫ(3)ᯃ(4)ǬᣜƩဪমΉǭϟ୊ᚽේǩʔШȗȤȰȮǥǋǨǂ᭮

Page 23 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
᭾ Register MapɖɗɟǬ BA + 0xFF000ᯃ 0xFFFFC ǩѓȈࡿǤȇȊǤǂȉӾɡȭȮȴǬᘐሏǩǢǂǤᘦ૲ǕǼǗƪ

9.1 Register Address Map
Offset Address

Register Content

Access0xFF000ᯃ0xFF03C

CDR(Channel Dependence Registers) for Ch0(see 9.2)

(see 9.2)

0xFF040ᯃ0xFF07C

CDR(Channel Dependence Registers) for Ch1(see 9.2)

(see 9.2)

0xFF080ᯃ0xFF0BC

CDR(Channel Dependence Registers) for Ch2(see 9.2)

(see 9.2)

0xFF0C0ᯃ0xFF0FC

CDR(Channel Dependence Registers) for Ch3(see 9.2)

(see 9.2)

0xFF100ᯃ0xFF03C

CDR(Channel Dependence Registers) for Ch4(see 9.2)

(see 9.2)

0xFF140ᯃ0xFF07C

CDR(Channel Dependence Registers) for Ch5(see 9.2)

(see 9.2)

0xFF180ᯃ0xFF0BC

CDR(Channel Dependence Registers) for Ch6(see 9.2)

(see 9.2)

0xFF1C0ᯃ0xFF0FC

CDR(Channel Dependence Registers) for Ch7(see 9.2)

(see 9.2)

0xFF200ᯃ0xFF03C

CDR(Channel Dependence Registers) for Ch8(see 9.2)

(see 9.2)

0xFF240ᯃ0xFF07C

CDR(Channel Dependence Registers) for Ch9(see 9.2)

(see 9.2)

0xFF280ᯃ0xFF0BC

CDR(Channel Dependence Registers) for Ch10(see 9.2)

(see 9.2)

0xFF2C0ᯃ0xFF0FC

CDR(Channel Dependence Registers) for Ch11(see 9.2)

(see 9.2)

0xFF300ᯃ0xFF03C

CDR(Channel Dependence Registers) for Ch12(see 9.2)

(see 9.2)

0xFF340ᯃ0xFF07C

CDR(Channel Dependence Registers) for Ch13(see 9.2)

(see 9.2)

0xFF380ᯃ0xFF0BC

CDR(Channel Dependence Registers) for Ch14(see 9.2)

(see 9.2)

0xFF3C0ᯃ0xFF0FC

CDR(Channel Dependence Registers) for Ch15(see 9.2)

(see 9.2)

0xFF400

IRQVR(IRQ Vector Register)

Read/Write

0xFF404

IRQCR(IRQ Level Register)

Read/Write

0xFF408

MCSTAR(Multicast Address Register)

Read/Write

0xFF40C

MCSTCR(Multicast Control Register)

Read/Write

0xFF410LBWPR(List Buffer Write Pointer Register)

Read only

0xFF414LBRPR(List Buffer Read Pointer Register)

Read/Write

0xFF418

LBEFR(List Buffer Empty Flag Register)

Read/Write

0xFF41C

LBFFR(List Buffer Full Flag Register)

Read/Write

0xFF420

AMR(Acquire Mode Register)

Read/Write

0xFF424

ECPVR(Event Count Preset Value Register)

Read/Write

0xFF428LDSPVR(List Data Size Preset Value Register)

Read/Write

0xFF42Cᯃ0xFF43C(Reserved)-

0xFF440

ACR(Acquire Control Register)

Read/Write

0xFF444MCSR(Module Control Status Register)

Read/Write

0xFF448ᯃ0xFFFBC(Reserved)-

0xFFFC0LBSEMR(List Buffer Semaphore Register)

Read/Write

0xFFFC4ACSEMR(Acquire Control Semaphore Register)

Read/Write

0xFFFC8ᯃ0xFFFFC(Reserved)-

Page 24 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
9.2 CDR(Channel Dependence Registers) Address Map˿ʛǬɡȭȮȴǭϘǍԃǖϧܶǬȀǬǊӾ Ch ǩᗲǏȇȊǤǂǼǗƪ
Offset Address

Register Content

Access0xFF000+0x40*n

CCR(Channel Control Register)

Read/Write

0xFF004+0x40*n

CZLR(Channel Zero Level Register)

Read/Write

0xFF008+0x40*n

CLLDR(Channel Lower Level Discriminator Register)

Read/Write

0xFF00C+0x40*n(Reserved)

0xFF010+0x40*n

CRTR(Channel Real Time Register)

Read/Write

0xFF014+0x40*n

CLTR(Channel Live Time Register)

Read/Write

0xFF018+0x40*n(Reserved)-

0xFF01C+0x40*n(Reserved)-

0xFF020+0x40*n

CCGR(Channel Conversion Gain Register)

Read/Write

0xFF024+0x40*n

CPMR(Channel Preset Mode Register)

Read/Write

0xFF028+0x40*n

CPVR(Channel Preset Value Register)

Read/Write

0xFF02C+0x40*n

SPROICR(Start of Preset ROI Channel Register)

Read/Write

0xFF030+0x40*n

NPROICR(Number of Preset ROI Channel Register)

Read/Write

0xFF034+0x40*n(Reserved)

0xFF038+0x40*n(Reserved)

0xFF03C+0x40*n(Reserved)-(n = Ch# : 0ᯃ15)

Page 25 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷

᭶᭵ ӾɡȭȮȴǬᘐሏ10.1 CCR(Channel Control Register) : BA + 0xFF000 + 0x40 * n(n=Ch#0ᯃ15)
D31

D2 D1 D0



ɈȸȽ

Ԅწ

а୕ͱ

R/W

DAT
CLR GM1 GM0

ᘦ૲

0

GM0

1

R/W

Gate Mode 1, 0

1

GM1

1

R/W

Ӿ Ch Ǭ G/T IN ϗѡ͖ӹȐȧɭȽǦǕǤཽ̳Ǘȉ‫ب‬ӿǬɗɭȾȐᗲ‫ܥ‬ǕǼǗƪ
᭭FREE RUN LIST Ǽǝǭ TRIGGERED LIST ɗɭȾ଄ǩǑǬ͖ӹȐȽɟȡ͖ӹǦǕǤཽ̳Ǘȉ‫ب‬ӿǭǑǬᗲ‫ܥ‬Ǧǭᣢ͈ǨǍƩࠇǩȗȤȻȘɋɬɄșǬᘵ༷ǩǨȈǼǗ᭮

2

DAT CLR

0

R/W

GM1

GM0

0

 0:

(๽ѭ)

0

 1:

Anti Coincidence

1

 0:

Coincidence

1

 1:

Off

Data ClearǑǬɈȸȽȐ 1 ǩȰȸȽǗȉǦƩᘏࡿǗȉȶɘɨɂɠǬ PHA ȼɭȴɖɗɟǈȆǱɟȗɠȴșɕ(CRTR)Ʃɞșɋȴșɕ(CLTR)Ȑ
ȱɢȤɟȗǕǼǗƪ
ȤɟȗǊ‫ˉܞ‬ǗȉǦ A3100 ǭǑǬɈȸȽȀ 0 ǩǕǤȤɟȗǊ‫ܞ‬ˉǕǝǑǦȐၥȇǙǼǗƪ

඿‫ܥ‬ʪǬᗲ‫٭ܥ‬ାȐ჉೒ǕǼǗ᭭́ǩ‫٭‬ାǕǝǦǕǤȀ๽ᗆǓȊǼǗ᭮10.2 CZLR(Channel Zero Level Register) : BA + 0xFF004 + 0x40 * n(n=Ch#0ᯃ15)
D31

D11

D0
Zero Level(12bits)

ɈȸȽ

Ԅწ

а୕ͱ

R/W

0 - 11 ZL0 - ZL11

0x800

R/W

ᘦ૲
Zero Level 0 - 11ɊɠȮȦɭɠǬ¤5%Ǭᆐ‫ב‬ǥȱɢᘬ઴Ȑᗲ‫ܥ‬ǕǼǗƪᗲ‫ͱܥ‬
0xFFF(4095) :ȱɢɡɎɠ+4.997558594%:
0x801(2049) :+0.002441406%

0x800(2048) :0%

0x7FF(2047) :-0.002441406%:
0x000(0) :-5.000000000%

Page 26 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
10.3 CLLDR(Channel Lower Level Discriminator Register) : BA + 0xFF008 + 0x40 * n(n=Ch#0ᯃ15)
D31

D11

D0
LLD Level(12bits)

ɈȸȽ

Ԅწ

0 - 11 LLD0 - LLD11

а୕ͱ

R/W

ᘦ૲

0x1A0

R/W

Lower Level Discriminator 0 - 11ɊɠȮȦɭɠǬ+10%Ǭᆐ‫ב‬ǥ LLD ɡɎɠȐᗲ‫ܥ‬ǕǼǗƪᗲ‫ͱܥ‬

ȱɢɡɎɠ

0xFFF(4095) :+10.000000000%

0xFFE(4094) :+9.997557998%:
0x001(1) :+0.002442002%

0x000(0) :0%10.4 CRTR(Channel Real Time Register) : BA + 0xFF010 + 0x40 * n(n=Ch#0ᯃ15)
D31

D0Real Time(32bits)

ɈȸȽ

Ԅწ

0 - 31 RT0 – RT31

а୕ͱ

R/W

0

R/W

ᘦ૲
Real Time 0 - 31
0.01secᯃ 42949672.95sec ᆐ‫ב‬Ȑ৻Ǣ 10ms ҵ̝ǬɟȗɠȴșɕɬȼɭȴǥǗƪ
ឨࠇǭɟɭȾǕǉᕚǂǼǙȑƪȀǕ CCR ɡȭȮȴǬ DAT CLRɈȸȽȐཽ̳ǙǘǩƩPHA ɖɗɟȐȤɟȗǕǝ‫ب‬ӿǩǭǑǬɡȭȮȴǩ 0 ȐɞșȽǕǤɟȗɠȴșɕȀʔ቏ǩȱɢȤɟȗǕǼǗƪ

10.5 CLTR(Channel Live Time Register) : BA + 0xFF014 + 0x40 * n(n=Ch#0ᯃ15)
D31

D0Live Time(32bits)

ɈȸȽ

Ԅწ

0 - 31 LT0 – LT31

а୕ͱ

R/W

0

R/W

ᘦ૲
Live Time 0 - 31
0.01secᯃ 42949672.95sec Ǭᆐ‫ב‬Ȑ৻Ǣ 10ms ҵ̝ǬɞșɋȴșɕɬȼɭȴǥǗƪ
ឨࠇǭɟɭȾǕǉᕚǂǼǙȑƪȀǕ CCR ɡȭȮȴǬ DAT CLRɈȸȽȐཽ̳ǙǘǩƩPHA ɖɗɟȐȤɟȗǕǝ‫ب‬ӿǩǭǑǬɡȭȮȴǩ 0 ȐɞșȽǕǤɞșɋȴșɕȀʔ቏ǩȱɢȤɟȗǕǼǗƪ

Page 27 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
10.6 CCGR(Channel Conversion Gain Register) : BA + 0xFF020 + 0x40 * n(n=Ch#0ᯃ15)
D31

D2 D1 D0



ɈȸȽ

Ԅწ

а୕ͱ

R/W

CG2 CG1 CG0

ᘦ૲

0

CG0

0

R/W

Conversion Gain 2, 1, 0

1

CG1

0

R/W

ADC Ǭ‫੄٭‬ȧșɨȐᗲ‫ܥ‬ǕǼǗƪ

2

CG2

0

R/W

CG2

CG1

CG0

0

0

 0:

8192

0

0

 1:

4096

0

1

 0:

2048

0

1

 1:

1024

1

0

 0:

512

1

0

 1:

256

1

1

 0:

(๽ѭ)

1

1

 1:

(๽ѭ)

඿‫ܥ‬ʪǬᗲ‫٭ܥ‬ାȐ჉೒ǕǼǗ᭭́ǩ‫٭‬ାǕǝǦǕǤȀ๽ᗆǓȊǼǗ᭮10.7 CPMR(Channel Preset Mode Register) : BA + 0xFF024 + 0x40 * n(n=Ch#0ᯃ15)
D31

D2 D1 D0



ɈȸȽ

Ԅწ

а୕ͱ

R/W

PM2 PM1 PM0

ᘦ૲

0

PM0

0

R/W

Preset Mode 2, 1, 0

1

PM1

0

R/W

PHA ѷ̨଄ǬɌɟȰȸȽɗɭȾȐᗲ‫ܥ‬ǕǼǗƪ

2

PM2

0

R/W

PM2

PM1

PM0

0

0

0:

OFF

0

0

1:

RT(Real Time) Preset

0

1

0:

LT(Live Time) Preset

0

1

1:

PC(Peak Counts) Preset

1

0

0:

IC(Integral Counts) Preset

1

0

1:

(๽ѭ)

1

1

0:

(๽ѭ)

1

1

1:

(๽ѭ)

඿‫ܥ‬ʪǬᗲ‫٭ܥ‬ାȐ჉೒ǕǼǗ᭭́ǩ‫٭‬ାǕǝǦǕǤȀ๽ᗆǓȊǼǗ᭮

Page 28 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
10.8 CPVR(Channel Preset Value Register) : BA + 0xFF028 + 0x40 * n(n=Ch#0ᯃ15)
D31

D0Preset Value(32bits)

ɈȸȽ

Ԅწ

0 - 31 PV0 –PV31

а୕ͱ

R/W

100

R/W

ᘦ૲
Preset Value 0 - 31ɌɟȰȸȽǬͱȐᗲ‫ܥ‬ǕǼǗƪ
Preset Modeᗲ‫ܥ‬ǥǋȉɌɟȰȸȽͱǬᆐ‫ב‬RT :100 – 4294967295(1.00 – 42949672.95sec)

LT :100 – 4294967295(1.00 – 42949672.95sec)

PC :1 – 4294967295Counts(232-1)

IC :1 – 4294967295Counts(232-1)඿‫ܥ‬ʪǬᗲ‫٭ܥ‬ାȐ჉೒ǕǼǗ᭭́ǩ‫٭‬ାǕǝǦǕǤȀ๽ᗆǓȊǼǗ᭮10.9 SPROICR(Start of Preset ROI Channel Register) : BA + 0xFF02C + 0x40 * n(n=Ch#0ᯃ15)
D31

D12

D0
Start of Preset ROI Channel(13bits)

ɈȸȽ

Ԅწ

0 - 12 SOC0 - SOC12

а୕ͱ

R/W

0

R/W

ᘦ૲
Start of Channel 0 – 12ɌɟȰȸȽɗɭȾǊ PC Ǽǝǭ IC Ǭ‫ب‬ӿǩɌɟȰȸȽǬ‫ݘ‬ᚍǦǨȉ ROI ᦸؑǬᣙ‫ڵ‬ȶɘɨɂɠȐᗲ‫ܥ‬Ǘȉƪᗲ‫ܥ‬ǥǋȉͱǬᆐ‫ב‬ǭ 0 ᯃ (Conversion Gain – 1)඿‫ܥ‬ʪǬᗲ‫٭ܥ‬ାȐ჉೒ǕǼǗ᭭́ǩ‫٭‬ାǕǝǦǕǤȀ๽ᗆǓȊǼǗ᭮

10.10 NPROICR(Number of Preset ROI Channel Register) : BA + 0xFF030 + 0x40 * n(n=Ch#0ᯃ15)
D31

D12

D0
Number of Preset ROI Channel(13bits)

ɈȸȽ

Ԅწ

0 - 12 NOC0 - NOC12

а୕ͱ

R/W

0

R/W

ᘦ૲
Number of Channel 0 - 12ɌɟȰȸȽɗɭȾǊ PC Ǽǝǭ IC Ǭ‫ب‬ӿǩɌɟȰȸȽǬ‫ݘ‬ᚍǦǨȉ ROI ᦸؑǬȶɘɨɂɠલȐᗲ‫ܥ‬Ǘȉƪᗲ‫ܥ‬ǥǋȉͱǬᆐ‫ב‬ǭ
1 ᯃ (Conversion Gain – SPROICR ᗲ‫)ͱܥ‬඿‫ܥ‬ʪǬᗲ‫٭ܥ‬ାȐ჉೒ǕǼǗ᭭́ǩ‫٭‬ାǕǝǦǕǤȀ๽ᗆǓȊǼǗ᭮

Page 29 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
10.11 IRQVR(IRQ Vector Register) : BA + 0xFF400
D31

D7

D0
Status/ID(8bits)

ɈȸȽ

Ԅწ

а୕ͱ

R/W

0-7

S/ID0 – S/ID7

0

R/W

ᘦ૲
Status/ID 0 - 7ѓ᝿ǽࢻᅭȪșȤɠ଄ǩ VME ȼɭȴɅȮǩមСǗȉɎȤȴɬȗȾɡȮȐᗲ‫ܥ‬Ǘȉƪ

10.12 IRQCR(IRQ Control Register) : BA + 0xFF404
D31

ɈȸȽ

Ԅწ

а୕ͱ

R/W

D7 D6

D2 D1 D0

LDS
PIE

LVL LVL LVL
2
1
0

EC
PIE



ᘦ૲

0

LVL0

0

R/W

IRQ Level 2, 1, 0

1

LVL1

0

R/W

ѓ᝿ǽ࿺ཹ଄Ǭѓ᝿ǽᖽഘɡɎɠȐᗲ‫ܥ‬ǕǼǗƪ

2

LVL2

0

R/W

LVL2

LVL1

LVL0

0

0

0:

IRQ OFF

0

0

1:

IRQ1

0

1

0:

IRQ2

0

1

1:

IRQ3

1

0

0:

IRQ4

1

0

1:

IRQ5

1

1

0:

IRQ6

1

1

1:

IRQ7

6

ECPIE

0

R/W

Event Counts Preset IRQ Enable
0 : șɎɨȽȠțɨȽɬɌɟȰȸȽǩȆȉѓ᝿ǽȐ჉೒
1 : șɎɨȽȠțɨȽɬɌɟȰȸȽǩȆȉѓ᝿ǽȐᗳӳ7

LDSPIE

0

R/W

List Data Size Preset IRQ Enable
0 : ɟȮȽȼɭȴȪșȯɬɌɟȰȸȽǩȆȉѓ᝿ǽȐ჉೒
1 : ɟȮȽȼɭȴȪșȯɬɌɟȰȸȽǩȆȉѓ᝿ǽȐᗳӳ

10.13 MCSTAR(Multicast Address Register) : BA + 0xFF408
D31

D7

D0
MCST Address(8bits)

ɈȸȽ

Ԅწ

а୕ͱ

R/W

0-7

MA0 – MA7

0xEE

R/W

ᘦ૲
Multicast Address 0 - 7
MCST ȗȾɡȸȬɨȥᄗᣜȐ‫ܥ‬ǿȉ A32 ȗȾɡȮ৽‫ܥ‬ɗɭȾǬ
ʚ̝ 8bits ǩᘏࡿǗȉͱȐᗲ‫ܥ‬Ǘȉƪ

Page 30 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
10.14 MCSTCRM(Multicast Control Register) : BA + 0xFF40C
D31

D1 D0



ɈȸȽ

Ԅწ

а୕ͱ

R/W

F_bit L_bit

ᘦ૲

0

L_bit

0

R/W

Last bit, F_bit

1

F_bit

0

R/W

MCST ȨɓɨȾǩ‫ݘ‬ǕǤࢻᅭǗȉɗȭɚɭɠǬȶȜɭɨȐᗲ‫ܥ‬
Ǘȉƪ
F_bit

L_bit

0

0 : େаǼǝǭେ࢞˿‫ٲ‬Ǭɗȭɚɭɠ(Inactive)0

1 : େ࢞Ǭɗȭɚɭɠ(Active)

1

0 : େаǬɗȭɚɭɠ(Active)

1

1 : େаǦେ࢞ǩਃǼȊǝʪᣜǩ̝ኲǗȉɗȭɚɭɠ
(Active)10.15 LBWPR(List Buffer Write Pointer Register) : BA + 0xFF410
D31

D16

D1 D0
List Buffer Write Pointer(17bits)

ɈȸȽ

Ԅწ

0 - 16 WRPTR0 –

а୕ͱ

R/W

0

R

ᘦ૲
Write pointer 0 - 16ɟȮȽȼɭȴɅȸɊȖǶǬȼɭȴୁǋ᝿ǽϋȐᕦǗɒșɨȴ

WRPTR16ǥƩᗳǓȊȉͱǬᆐ‫ב‬ǭ 0 ᯃ0x1FBFFƪ
ǑǬϧܶǭ A3100 ǩȆǡǤǬǽୁ੄ǆȇȊƩVMEbus ΉǭᘧǽСǕ‫ཽݛ‬ǦǕǤཽǂȉƪ

10.16 LBRPR(List Buffer Read Pointer Register) : BA + 0xFF414
D31

D16

D1 D0
List Buffer Read Pointer(17bits)

ɈȸȽ

Ԅწ

0 - 16 RDPTR0 –RDPTR16

а୕ͱ

R/W

0

R/W

ᘦ૲
Read pointer 0 - 16ɟȮȽȼɭȴɅȸɊȖǉȇȼɭȴȐᘧǽСǗǷǋ‫ب‬঩ȐᕦǗɒșɨȴǥƩᗳǓȊȉͱǬᆐ‫ב‬ǭ 0 ᯃ0x1FBFFƪ
ᘐሏǭƳ8.6 ɟɭȾȼɭȴɅȸɊȖǬȼɭȴɟɭȾƴȐӘ຋

Page 31 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
10.17 LBEFR(List Buffer Empty Flag Register) : BA + 0xFF418
D31

D0



ɈȸȽ
0

Ԅწ
EMP

а୕ͱ

R/W

1

R/W

EMP

ᘦ૲
Empty
0 : ɟȮȽȼɭȴɅȸɊȖǩȼɭȴǊǀȉǑǦȐᕦǗƪ
1 : ɟȮȽȼɭȴɅȸɊȖǊᄗǥǀȉǑǦȐᕦǗƪɟȮȽȼɭȴɅȸɊȖǉȇȼɭȴȐᘧǽСǕǝሟஎƩɅȸɊȖ
ǊᄗǩǨǡǝ‫ب‬ӿǭǑǬɊɞȥȐȰȸȽǕǨǏȊǮǨȇǨǂƪ
ᘐሏǭƳ8.6 ɟɭȾȼɭȴɅȸɊȖǬȼɭȴɟɭȾƴȐӘ຋

10.18 LBFFR(List Buffer Full Flag Register) : BA + 0xFF41C
D31

D0



ɈȸȽ
0

Ԅწ
FUL

а୕ͱ

R/W

0

R/W

FUL

ᘦ૲
Full
0 : ɟȮȽȼɭȴɅȸɊȖǊූ୻ǥǨǂǑǦȐᕦǗƪ
1 : ɟȮȽȼɭȴɅȸɊȖǊූ୻ǥǀȉǑǦȐᕦǗɟȮȽȼɭȴɅȸɊȖǉȇȼɭȴȐᘧСǕǝሟஎƩɅȸɊȖǩ
ᄗǋǊཹǖǝ‫ب‬ӿǭǑǬɊɞȥȐȤɟȗǕǨǏȊǮǨȇǨǂƪ
ᘐሏǭƳ8.6 ɟɭȾȼɭȴɅȸɊȖǬȼɭȴɟɭȾƴȐӘ຋

Page 32 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
10.19 AMR(Acquire Mode Register) : BA + 0xFF420
D31

D3 D2 D1 D0



ɈȸȽ

Ԅწ

а୕ͱ

R/W

PHA PHA
LM2 LM1 LM0
SEL MOD

ᘦ૲

0

LM0

0

R/W

3bits ǥ LIST ѷ̨ɗɭȾȐᗲ‫ܥ‬ǕǼǗƪ

1

LM1

0

R/W

LM2

LM1

LM0

2

LM2

0

R/W

0

0

0:

LIST OFF0

0

1:(Reserved)

0

1

0:

GATED LIST

0

1

1:

(Reserved)

1

0

0:

FREE RUN LIST + TLI

1

0

1:

FREE RUN LIST + TSI

1

1

0:

TRIGGERED LIST + TLI

1

1

1:

TRIGGERED LIST + TSI

3

PHAMOD

1

R/W

PHA ɗɭȾǬ ON/OFF Ȑᗲ‫ܥ‬ǕǼǗƪ
0 : PHA OFF
1 : PHA ON

4PHASEL

0

R/W

GATED LIST ɗɭȾ଄ǩ PHA ѷ̨Ǭ‫ݘ‬ᚍǦǗȉ͖ӹȐៜ৐ǕǼǗƪ
0᭿GATED LIST ǥࢣȇȊǝ͖ӹǬǽȐ PHA Ǭ‫ݘ‬ᚍǦǗȉƪ1᭿ϘǤǬϗѡ͖ӹȐ PHA Ǭ‫ݘ‬ᚍǦǗȉƪɬ ඿‫ܥ‬ʪǬᗲ‫٭ܥ‬ାȐ჉೒ǕǼǗ᭭́ǩ‫٭‬ାǕǝǦǕǤȀ๽ᗆǓȊǼǗ᭮ɬ PHASEL ǭ PHA Ǭ‫ݘ‬ᚍǦǗȉ͖ӹȐៜ৐ǗȉǬǽǥǗƪ‫ܩ‬᤮ǩ PHA ѷ̨ȐǓǙȉǩǭ PHAMOD Ȑ 1ǩᗲ‫ܥ‬ǕǨǏȊǮǨȈǼǙȑƪ

Page 33 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
10.20 ECPVR(Event Count Preset Value Register) : BA + 0xFF424
D31

D15

D0
Event Count Preset Value(16bits)

ɈȸȽ

Ԅწ

0 - 15 ECPV0 –

а୕ͱ

R/W

ᘦ૲

0

R/W

Event Count Preset Value 0 – 15

ECPV15

0 : OFF1 ᯃ0xFE00 : ᗲ‫ܥ‬ӳጻǨșɎɨȽȠțɨȽલGATED LIST Ǽǝǭ TRIGGERED LIST ѷ̨ɗɭȾǩǈǂǤƩ඿‫ܥ‬ᣙ‫ڵ‬Ǽǝǭх‫׌‬ǑǬɌɟȰȸȽǩៈǕǝ଄๭ǉȇǬșɎɨȽȠțɨȽલǊǑǬɡȭȮȴᗲ‫ͱܥ‬ȐᛪǆǝȇƩMCSR ɡȭȮȴǬECOF ɈȸȽȐ᭶ǩȰȸȽǕǤɌɟȰȸȽǬៈওȐၥȇǙǼǗƪ
ȀǕѓ᝿ǽᗳӳȐᕦǗ IRQCR ɡȭȮȴǬ ECPIE ɈȸȽǊ 1 ǩȰȸȽǓȊǤǂǝȇƩԃ଄ǩ VMEbus ǩѓȈ᝿ǽȐ࿺ཹǕǼǗƪᘐሏǭƳ6.4 VME InterruptƴȐӘ຋ǕǤǍǞǓǂƪ

10.21 LDSPVR(List Data Size Preset Value Register) : BA + 0xFF428
D31

D16

D0
List Data Size Preset Value(17bits)

ɈȸȽ

Ԅწ

0 - 16 LDSPV0 –LDSPV15

а୕ͱ

R/W

ᘦ૲

0

R/W

List Data Size Preset Value 0 – 16
0 : OFF1 ᯃ0x1FBFF : ᗲ‫ܥ‬ӳጻǨȼɭȴȪșȯ(ɢɨȥɤɭȾҵ̝)ϘǤǬɟȮȽɗɭȾѷ̨଄ǩǈǂǤƩ඿‫ܥ‬ᣙ‫ڵ‬Ǽǝǭх‫׌‬ǑǬɌɟȰȸȽǩៈǕǝ଄๭ǉȇǬɢɨȥɤɭȾɬȼɭȴȪșȯǊ
ǑǬɡȭȮȴᗲ‫ͱܥ‬ȐᛪǆǝȇƩMCSR ɡȭȮȴǬ LDSOF ɈȸȽȐ᭶ǩȰȸȽǕǤɌɟȰȸȽǬៈওȐၥȇǙǼǗƪȀǕѓ᝿ǽᗳӳȐᕦǗ IRQCR ɡȭȮȴǬ LDSPIE ɈȸȽǊ 1 ǩȰȸȽǓȊǤǂǝȇƩԃ଄ǩ VMEbus ǩѓȈ᝿ǽȐ࿺ཹǕǼǗƪᘐሏǭƳ6.4 VME InterruptƴȐӘ຋ǕǤǍǞǓǂƪ

Page 34 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
10.22 ACR(Acquire Control Register) : BA + 0xFF440
D31

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ACQ ACQ ACQ ACQ ACQ ACQ ACQ ACQ ACQ ACQ ACQ ACQ ACQ ACQ ACQ ACQ
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0

ɈȸȽ

Ԅწ

а୕ͱ

R/W

ᘦ૲

0

ACQ0

0

R/W

Acquire 0 – 15

1

ACQ1

0

R/W

Ӿ Ch Ǭ඿‫ܥ‬ǬȮȴɭȽ/ȮȽȸɌȐ৽˾ǗȉǦϟǩƩ඿‫ܥ‬໦े

2

ACQ2

0

R/W

ǬȮȻɭȴȮȀᕦǕǼǗ᭭ACQ0 – 15 ǭǛȊǜȊ Ch0 – 15 ǩ

3

ACQ3

0

R/W

‫ࢻݘ‬ǕǤǂǼǗ᭮ƪ

4

ACQ4

0

R/W

Ɩୁǋ᝿ǽ଄ǭ

5

ACQ5

0

R/W

0 : ඿‫ܥ‬Ǭ΅೒Ȑ৽˾Ǘȉƪ

6

ACQ6

0

R/W

1 : ඿‫ܥ‬Ǭᣙ‫ڵ‬Ȑ৽˾Ǘȉƪ

7

ACQ7

0

R/W

ƖᘧǽСǕ଄ǭ

8

ACQ8

0

R/W

0 : ΅೒ǕǤǂȉƪ

9

ACQ9

0

R/W

1 : ඿‫ܥ‬ʪǥǀȉƪ

10

ACQ10

0

R/W

11

ACQ11

0

R/W

PHA ɗɭȾǥɌɟȰȸȽȐᗲ‫ܥ‬ǕǤ඿‫ܥ‬ǕǤǂȉ‫ب‬ӿǭƩɌɟ

12

ACQ12

0

R/W

ȰȸȽǩៈǗȉǦ A3100 Ǌѻমǩ඿‫ܥ‬Ȑ΅೒ǕƩ‫ࢻݘ‬Ǘȉ Ch

13

ACQ13

0

R/W

Ǭ ACQ᮳ɈȸȽȐ 0 ǩǕǼǗƪࢢǡǤǑǬɡȭȮȴȐᘧǾǑǦ

14

ACQ14

0

R/W

ǥϘ Ch Ǭ඿‫ܥ‬໦ेȐɗɀȴǗȉǑǦǊС୸ǼǗƪ

15

ACQ15

0

R/W
ǑǬɡȭȮȴǭ A3100 Ǧ VMEbus ǬӞૐǉȇୁǋ੄ǆȐᕚǄȆǄǩǨǡǤǂȉǬǥƩୁǋ᝿ǽ଄ǩǭਥ˶йࢨȐᕚǄǑǦǊࢴᖽǥǗƪ̷ǆǮ Ch0 ǊɌɟȰȸȽȐᗲ‫ܥ‬ǕǤ඿‫ܥ‬ʪǥǀȉ଄ǩƩ࢞ǉȇ Ch2 Ǭ඿‫ܥ‬Ȑᣙ‫ڵ‬ǗȉȆǄǨ‫ب‬ӿƩVMEbus ɓȮȴǭǑǬɡȭȮȴȐᘧǽСǕǝȼɭȴǦ ACQ2 ɈȸȽǬᘵ༷ԲȐǦǡǤϬ࠱ǑǬɡȭȮȴǶୁǋধǛǄǦǕǼǗƪȀǕᘧǽСǕǤǉȇୁǋধǗǼǥǬᣜǩ Ch0 ǊɌɟȰȸȽǩៈǕǤǕǼǡǝ‫ب‬ӿƩA3100 Ǌ Ch0 Ǭ඿‫ܥ‬ሖˉȐᕦǗǝǿǩ ACQ0=0 ǦǕǝǩȀᣢȍȇǘƩVMEbus ɓȮȴǬୁǋধǕǩȆȈƩǼǝ ACQ0=1
ǊȰȸȽǓȊǤǕǼǂඦ˃ȐཹǘȉሟஎǦǨȈǼǗƪ
ਥ˶йࢨȐᕚǄǩǭ ACSEMR(Acquire Control Semaphore
Register)Ȑཽ̳ǕǼǗƪཽ̳ૐ്ǭƳ8.6 ɟȮȽȼɭȴɅȸɊȖǬȼɭȴɟɭȾƴȐӘ຋ǕǤǍǞǓǂƪȰɓɊȞɡȭȮȴǩǭ LBSEMR Ǧ ACSEMR ǬˎǢǊǀȈƩLBSEMR ǭɟȮȽɅȸɊȖ‫ཽݛ‬ƩACSEMR ǭǑǬ ACR ‫ཽݛ‬ǥǀȉ๭ǩǒൖऴǍǞǓǂƪ

Page 35 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
10.23 MCSR(Module Control Status Register) : BA + 0xFF444
D31 D30 D29

D27 D26

D15 D14 D13 D12

D9 D8

LBUF LDS ECOVFL OVF OVF

M/S M/S
1
0

INT EC LBUF PHARES CLR CLR CLR

TIL PH
SEL MOD

ɈȸȽ

Ԅწ

а୕ͱ

R/W

D6 D5 D4

D1 D0

TB2

CGM CGM
1
0

TB1

TB0

ᘦ૲

0

CGM0

1

R/W

Common Gate Mode 1, 0

1

CGM1

1

R/W

Ϙ Ch ϟឨǬ COM_G/T IN ϗѡ͖ӹǬᘵ༷Ȑᗲ‫ܥ‬ǕǼǗƪ
TRIGGERED LIST ɗɭȾ଄ǬȽɟȡ͖ӹƩǛǬ˶Ǭѷ̨ɗɭȾǩǈǏȉȧɭȽ͖ӹǬᘵ༷ǭ˿ʛǬȆǄǩǨȈǼǗƪ
GM1

GM0

ȧɭȽ͖ӹ

Ƚɟȡ͖ӹ

0

 0:

(๽ѭ)

(๽ѭ)

0

 1:

Anti Coincidence

Active Low

1

 0:

Coincidence

Active High

1

 1:

Off

(๽ѭ)

4

TB0

0

R/W

Time Base 0 – 2

5

TB1

0

R/W

TLI,TSI ȤɢȸȤǬȴșɕɎɭȮȐᗲ‫ܥ‬Ǘȉƪ

6

TB2

0

R/W

TB2

TB1

TB0

0

0

0:

5nsec

0

0

1:

10nsec010:20nsec01

1:50nsec100:100nsec101:200nsec11

0:500nsec

1

1

1:

1Ìsec

8

PHMOD

0

R/W

Peak Hold ModeGATED LIST ଄ǩǈǏȉ COM_G/T ͖ӹ୕ᣜϧǥǬɉɭȤɐɭɠȾǬૐ്Ȑៜ৐Ǘȉƪ
0 : େаǬɉɭȤɡɎɠȐɐɭɠȾǗȉƪ
1 : େȀ‫ٺ‬ǋǨɉɭȤɡɎɠȐɐɭɠȾǗȉƪ

9

TILSEL

0

R/W

Time Information Latch SelectFREE RUN LIST,TRIGGERED LIST ଄ǩ଄ᣜक‫ ا‬TLI/TSI ȐɞȸȶǗȉȴșɔɨȥȐៜ৐Ǘȉƪ
0 : Ӿ Ch ǬɉɭȤటСǬȴșɔɨȥ(TLI,TSI ʧૐǥᗲ‫ܥ‬ӳጻ)
1 : Ӿ Ch Ǭ G/T IN ϗѡ͖ӹǬȴșɔɨȥ(TSI ǩǬǽᗲ‫ܥ‬ӳጻ)12

PHA CLR

0R/W

PHA Memory ClearǑǬɈȸȽȐ 1 ǩȰȸȽǗȉǦƩϘ Ch Ǭ PHA ȼɭȴɖɗɟǈ
ȆǱ CRTR,CLTR ɡȭȮȴǬϧܶȐȱɢȤɟȗǕǼǗƪ
ȤɟȗǊ‫ˉܞ‬ǗȉǦ A3100 ǭǑǬɈȸȽȐ 0 ǩǕǤȤɟȗǊ‫ܞ‬ˉǕǝǑǦȐၥȇǙǼǗƪ

Page 36 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
13

LBUF CLR

0

R/W

List Buffer ClearǑǬɈȸȽȐ 1 ǩȰȸȽǗȉǦƩɟȮȽȼɭȴɅȸɊȖǬϧܶȐϘǤȱɢȤɟȗǕǼǗƪ
ȤɟȗǊ‫ˉܞ‬ǗȉǦ A3100 ǭǑǬɈȸȽȐ 0 ǩǕǤȤɟȗǊ‫ܞ‬ˉǕǝǑǦȐၥȇǙǼǗƪ

14

EC CLR

0

R/W

Event Count ClearǑǬɈȸȽȐ 1 ǩȰȸȽǗȉǦƩșɎɨȽȠțɨȴǬϧܶȐȱɢȤɟȗǕǼǗƪ
ȤɟȗǊ‫ˉܞ‬ǗȉǦ A3100 ǭǑǬɈȸȽȐ 0 ǩǕǤȤɟȗǊ‫ܞ‬ˉǕǝǑǦȐၥȇǙǼǗƪ

15

INT RES

0

R/W

Internal ResetǑǬɈȸȽȐ 1 ǩȰȸȽǗȉǦƩɆɤɭȟɨ଄Ǧԃǖౣǩ A3100
Ϙ̢ȐɟȰȸȽǕǼǗƪɟȰȸȽǊ‫ˉܞ‬ǗȉǦ A3100 ǭǑǬɈȸȽȐ 0 ǩǕǤɟȰȸȽǬሖˉȐၥȇǙǼǗƪ

26

M/S0

(ʜ‫)ܥ‬R

Master/Slave 0Ʃ1

27

M/S1

(ʜ‫)ܥ‬

R

ATICbus ǩǈǏȉ୛ɗȭɚɭɠǬਮሴ໦െȐᕦǕǼǗƪ29

ECOVF

0

R/W

M/S1

M/S0

0

 0:

ɅȮਮሴǬʪᣜǩ̝ኲǗȉȮɡɭɋ

0

 1:

ɅȮਮሴǬେ࢞ǩ̝ኲǗȉȮɡɭɋ

1

 0:

ɓȮȴ᭭ɅȮਮሴǬେаǩ̝ኲǗȉ᭮

1

 1:

ȮȴɨȾȗɢɭɨ

Event Count Over Flag
0 : șɎɨȽȠțɨȽǭɌɟȰȸȽͱǩៈǕǤǂǨǂƪ
1 : șɎɨȽȠțɨȽǭɌɟȰȸȽͱȐȟɭɅɭǕǤǂȉƪ
VMEbus ɓȮȴǭǑǬɈȸȽǊ᭶ǩȰȸȽǓȊǤǂȉǬȐɟɭȾǕǝȇƩ႓ᘘࢻᅭǬ๮ǩǑǬɈȸȽȐȱɢȤɟȗǕǨǏȊǮ
ǨȈǼǙȑƪ30

LDSOVF

0

R/W

List Data Size Over Flag
0 : ɟȮȽȼɭȴȪșȯǭɌɟȰȸȽͱǩៈǕǤǂǨǂƪ
1 : ɟȮȽȼɭȴȪșȯǭɌɟȰȸȽͱȐȟɭɅɭǕǤǂȉƪ
VMEbus ɓȮȴǭǑǬɈȸȽǊ᭶ǩȰȸȽǓȊǤǂȉǬȐɟɭȾǕǝȇƩ႓ᘘࢻᅭǬ๮ǩǑǬɈȸȽȐȱɢȤɟȗǕǨǏȊǮ
ǨȈǼǙȑƪ

31

LBUF OVFL

0

R/W

List Buffer Overflow
0 : ɟȮȽȼɭȴɅȸɊȖǭȟɭɅɭɊɢɭǕǤǂǨǂƪ
1 : ɟȮȽȼɭȴɅȸɊȖǭȟɭɅɭɊɢɭǕǤǂȉƪ
VMEbus ɓȮȴǭǑǬɈȸȽǊ᭶ǩȰȸȽǓȊǤǂȉǬȐɟɭȾǕǝȇƩ႓ᘘࢻᅭǬ๮ǩǑǬɈȸȽȐȱɢȤɟȗǕǨǏȊǮ

ǨȈǼǙȑƪ
Bit0~13 Ǽǥǭ඿‫ܥ‬ʪǬᗲ‫٭ܥ‬ାȐ჉೒ǕǼǗ᭭́ǩ‫٭‬ାǕǝǦǕǤȀ๽ᗆǓȊǼǗ᭮
Bit26,27 ǭࠇǩୁ᝿ǽ჉೒ǥǗ
Page 37 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
10.24 LBSEMR(List Buffer Semaphore Register) : BA + 0xFFFC0
D31

D0



ɈȸȽ
0

Ԅწ
LBSEM

0 - 31

LB
SEM

а୕ͱ

R/W

ᘦ૲

-

W

List Buffer Semaphore(ʜ‫)ܥ‬

R

ɟȮȽɅȸɊȖǬɒșɨȴȐӘ຋ǕǤɊɞȥȐା૎Ǘȉ‫ب‬ӿǬਥ˶йࢨǩཽ̳ǗȉȰɓɊȞɬɡȭȮȴǥǗƪ
ୁǋ᝿ǽ଄ǭ D0 ǞǏǊ୊ѭǥǗǊƩᘧǽСǕ଄ǭϘɈȸȽǩԃǖͱǊᘧǽСǓȊǼǗƪǢǼȈ All 0/All 1 ǬǧǟȇǉǥǗƪ
Ɩୁǋ᝿ǽ଄
0 : ȗȤȰȮಀȐᖽഘǗȉƪ
1 : ȗȤȰȮಀȐᣙઠǗȉƪƖᘧǽСǕ଄
0 : ȗȤȰȮಀȐ႓͔Ǖǝƪ
1 : ȗȤȰȮಀǭဪমΉǩǀȉƪ

10.25 ACSEMR(Acquire Control Semaphore Register) : BA + 0xFFFC4
D31

D0



ɈȸȽ
0
0 - 31

Ԅწ
ACSEM

AC
SEM

а୕ͱ

R/W

ᘦ૲

-

W

Acquire Control Semaphore(ʜ‫)ܥ‬

R

ACR ɡȭȮȴǬϧܶȐୁǋ੄ǆȉ᤮Ǭਥ˶йࢨǩཽ̳ǗȉȰɓɊȞɬɡȭȮȴǥǗƪ
ୁǋ᝿ǽ଄ǭ D0 ǞǏǊ୊ѭǥǗǊƩᘧǽСǕ଄ǭϘɈȸȽǩԃǖͱǊᘧǽСǓȊǼǗƪǢǼȈ All 0/All 1 ǬǧǟȇǉǥǗƪ
Ɩୁǋ᝿ǽ଄
0 : ȗȤȰȮಀȐᖽഘǗȉƪ
1 : ȗȤȰȮಀȐᣙઠǗȉƪƖᘧǽСǕ଄
0 : ȗȤȰȮಀȐ႓͔Ǖǝƪ
1 : ȗȤȰȮಀǭဪমΉǩǀȉƪ

Page 38 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
᭶ TLI ȼɭȴǩǢǂǤ
11.1 TLI ȼɭȴǦ Flip bit
FREE RUN LIST᭰TLI ȀǕǍǭ TRIGGERD LIST+TLI ɗɭȾǥƩɉɭȤటСȴșɔɨȥǊԃʔǥǀǡǝ‫ب‬ӿǬ଄ᣜߪक‫ ا‬TLI ȼɭȴǬӢȈ঺ǂǩǢǂǤᘦ૲ǕǼǗƪԃʔǦǭᗠǆƩ೓႓ǩǭ 200MHz ȤɢȸȤǥɉɭȤటСǬ୊๽ȐȪɨɌɟɨȥǕǤǂȉǝǿƩȤɢȸȤǬ
1 ԣ୕ (5ns) ᆐ‫ב‬ϧǩటСǕǝɉɭȤǭԃʔȴșɔɨȥǦᗃǨǓȊƩϘǍԃǖͱǬ TLI ȼɭȴȐӢȈ᝿ǾǑǦǩǨȈǼǗƪ
̷ǆǮ඿‫ܥ‬ǕǝɟȮȽȼɭȴǩ˿ʛǬȆǄǨϧܶǊԏǼȊǤǂǝ‫ب‬ӿƩ(2),(3)ǈȆǱ(6),(7),(8)Ǭ TLI ȼɭ
ϗѡᮨᮭ

ADC

TLI

Flip bit

:

:

:

:

3

789

3456

0

----------

(1)

0

1234

56789

1

----------

(2)

3

345

56789

1

----------

(3)

12

4567

1

0

----------

(4)

᭿

᭿

᭿

᭿

0

654

876

1

----------

(5)

12

987

6543

0

----------

(6)

0

5432

6543

1

----------

(7)

3

2345

6543

1

----------

(8)

12

4321

12321

0

----------

(9)

᭿

᭿

᭿

᭿

ȴǭԃǖͱǥǀȉǝǿƩǑȊȇǬ͖ӹǭԃʔȴșɔɨȥǥɉɭȤటСǓȊǝᮄǛȊǦȀʔǢхǬ͖ӹǉȇǬ଄ᣜߪǊ΋๿ǩȀϘǍԃǖǥǀǡǝᮄǦǂǄˎឨȈǬᗛᠰȐᕚǄǑǦǊС୸ǼǗƪǑǬྱժȐ೓ǕǍᗛനǗȉǝǿǩཽऴǓȊǤǂȉǬǊɊɟȸɌɈȸȽǥǗƪǑǬɈȸȽǭ 16ᮨᮭǬǂǘȊǉǩɉɭȤటСǊǀȊǮƩɉɭȤటСȪɨɌɟɨȥǦԃǖ 200ᮒᮍz ȤɢȸȤǩԃ୕ǕǤ 1Ʃ0 ǬͱǊ˝ˑǩӟᝀǗȉȆǄǩѷ̨ǕǼǗƪࢢǡǤƩԃǖ TLI ȼɭȴǊឯሴǕǤǈȈƩǉǢǛȊȇǬɊɟȸɌɈȸȽǬͱȀᅥǕǂ‫ب‬ӿǭɉɭȤటСǊԃʔȴșɔɨȥǥǀǡǝǑǦȐᕦǕƩɊɟȸɌɈȸȽǊྡྷǨȉ‫ب‬ӿǭԃǖ଄ᣜߪǥǭǀȉǊƩྡྷǨȉȴșɔɨȥǥ࿺ཹǕǝȀǬǥǀȉǦбૌǗȉǑǦǊС୸ǼǗƪʚᗫ(2),(3)Ǭ͖ӹǭ(1)Ǭ͖ӹǉȇ
56789 ȤɢȸȤូȊǤԃ଄ǩ 2 ǢǬɉɭȤǊటСǓȊǝǑǦȐƩ(6)Ǭ͖ӹǭ(5)ȆȈ 6543 ȤɢȸȤូȊƩǓȇǩԃǖ 6543 ȤɢȸȤូȊǤǉȇ(7),(8)Ǭ͖ӹǊɉɭȤటСǓȊǝǑǦȐ໔ᘞȈǼǗƪǟǨǽǩƩTLI ȼɭȴǬͱǭ MCSR ɡȭȮȴǩᗲ‫ܥ‬ǗȉȴșɕɎɭȮǬȤɢȸȤલȐᕦǕǼǗƪȀǕʚᗫǬɟȮȽȼɭȴǊȴșɕɎɭȮ=10ns ǥ඿‫ܥ‬ǕǝȀǬǥǀȉǨȇǮƩ(2)Ǭ͖ӹǭ(1)Ǭ͖ӹǉȇូȊȉǑǦ34.56Ìs ࢞ǩϗѡǓȊǤǋǝǑǦȐᕦǕƩ(4)Ǭ͖ӹǭ(3)ȆȈ 1 ȤɢȸȤ=10ns ǞǏូȊǝ͖ӹǥǀȉǑǦ
ȐᕦǕǤǂǼǗƪ

Page 39 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
11.2 TLI ȼɭȴӢ᝿ǽȴșɔɨȥ଄ᣜक‫ا‬ǬӢ᝿ǽȴșɔɨȥǦǕǤǭƩMCSR ɡȭȮȴǬ TILSEL ɈȸȽǥɉɭȤటСȴșɔɨȥǉƩȀǕ
ǍǭӾᮨᮭǬ G/T IN ϗѡ͖ӹȴșɔɨȥǬǂǘȊǉȐៜ৐ǗȉǑǦǊС୸ǼǗǊƩ଄ᣜߪȼɭȴȐӢࢣǗ
ȉ TLI ɗɭȾǥǭƩϧ៺ǬɉɭȤటСȴșɔɨȥǕǉៜǴǑǦǊС୸ǼǙȑƪǛǬཱྀ༷ǭƳA3100 Ǌϗѡ͖ӹȐ AD ‫੄٭‬ǕɖɗɟǩᗫॳǕǤǂǍ᦯ྟǭɉɭȤటСȴșɔɨȥ᦯ǥǀȉƴǦǂǄӌсǩǀȈǼǗƪ
TLI ɗɭȾǥ G/T IN ϗѡ͖ӹȴșɔɨȥȐཽ̳ǗȉȆǄǩǕǝ‫ب‬ӿƩӾᮨᮭǩϗǡǤǍȉ G/T IN ͖ӹǬϗѡ᦯ǦƩϗѡ͖ӹǬɉɭȤటС᦯ǊԃǖǥǀȉǦǂǄ͔ᗹǊǨǂǝǿƩɟȮȽɅȸɊȖǩᗫॳǓȊǝȼɭȴǭ଄ᣜဪᣢǬ᥿ǥ͖ᧂǩʹǕǍƩཽ͖ǬࢣȇȊǨǂȦɭȮǊ࿺ཹǗȉǉȇǥǗƪ
ǥǭƩG/T IN ϗѡ͖ӹ᦯ǩ AD ‫੄٭‬ǗȊǮժᧆǊᗛനǗȉȆǄǩȀ࣐ǆǼǗǊ༴‫ܩ‬ǭǛǄҵሀǥǭǀȈǼ
ǙȑƪG/T IN ǩȴșɔɨȥϗѡǬǀǡǝᮨᮭǬϗѡ͖ӹǭƩࠇǩ AD ‫੄٭‬ǓȊȉǦǭᤋȇǨǂǉȇǥǗƪ
̷ǆǮϗѡ͖ӹɡɎɠǊ LLD ˿ʛǥǀǡǝ‫ب‬ӿǭƩǂǢǼǥሜǡǤȀ AD ‫੄٭‬Ȑ‫ܩ‬ᕚǗȉǝǿǬ୴̄Ǌ઴
ȍǘƩA3100 ǊȼȸȾɢȸȤǕǝȆǄǨ໦ेǩᤔȈǼǗƪ́ǩȴșɕȗțȽ଄ᣜȐᗲǏǝǦǕǤȀƩǛǬ
ᣜǭȼȸȽȴșɕǦǨȈƩϘ̢ǬȮɠɭɌȸȽǊ̞ʛǗȉǦǂǄ࡞ܱȐཹǖǤǕǼǂǼǗƪ˿ʚǬǑǦǉȇ TLI ɗɭȾǥǭɉɭȤటСȴșɔɨȥǬǽǬᗲ‫ܥ‬ǦǨǡǤǕǼǂǼǕǝƪ
TSI ɗɭȾǥȀ G/T IN ͖ӹȴșɔɨȥȐៜ৐Ǖǝ‫ب‬ӿǭƩɟȮȽɅȸɊȖϧǬȼɭȴǊ଄ᇵЯ᦯ǥǭǨǍǨȉȦɭȮǊ࿺ཹǕǼǗǊƩȼɭȴϧǩᗫॳǓȊȉ଄ᣜक‫ا‬ǭሜែ଄ᣜǥǀȈƩ࢞ǥ TSI ȼɭȴȐཽǂǤ଄ᇵЯ᦯ǩʨǷ୆ǆȉǑǦǊӳጻǥǀȉǑǦǉȇƩG/T IN ͖ӹȴșɔɨȥȀៜ৐ǥǋȉȆǄǩǨǡǤǂǼǗƪ

Page 40 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷

᭶᭷ ȟɭɅɭɊɢɭ࿺ཹ଄Ǭ̷‫ٲ‬ခЖ༷ǩǢǂǤɆɠȮᩒǓǊ᭰10V ȐᛪǆȉȆǄǨϗѡ͖ӹǬ‫ب‬ӿƩǛǬ AD ‫੄٭‬ȼɭȴǊ‫੄٭‬ȧșɨȪșȯȐȟɭɅɭǗȉǉǧǄǉȐƩȗȿɢȥ͖ӹɡɎɠǬೳᤧǥбૌǗȉǬǭ‫א‬ᥑǥǀȉǝǿƩឨࠇǬϗѡ͖ӹǦԃౣǩɉɭȤɐɭɠȾȐᕚǂƩAD ‫੄٭‬Ȑ‫ܩ‬ᕚǕǼǗƪȟɭɅɭɊɢɭ᭭AD ‫࢞੄٭‬ǬȼɭȴǊȧșɨȪșȯȐ᛫ǆȉ᭮Ǌ࿺ཹǕǝ‫ب‬ӿƩࢢ୸ǬᖇኲǥǭǛǬȼɭȴȐၷ௻ǕǤǕǼǂǼǗǊƩA3100 ǥǭ಼ǬȆǄǨཱྀ༷ǉȇƩ‫੄٭‬ȧșɨǬେ‫ٺ‬ȶɘɨɂɠ᭭᭽᮰ȧșɨǬ‫ب‬ӿǨȇ 8191ᮨᮭ᭮ǩဪࡿǗȉ͖ӹǊϗǡǤǋǝȀǬǦ
ǽǨǕǤЖ༷ǕǤǂǼǗƪ
ɉɭȤɐɭɠȾ‫׌‬ᜀǭƩϗѡ͖ӹǬ‫ٺ‬ǋǓǩᣢȍȈǨǍࠇǩԃǖѷ̨ȐᕚǡǤǂȉǬǥƩȟɭɅɭɊɢɭ
Ǌ࿺ཹǗȉȆǄǨϗѡ͖ӹǬ‫ب‬ӿǥȀƩɉɭȤటС͖ӹȐСѡǕǼǗƪϗѡ͖ӹᣜǬ଄ᣜߪक‫ا‬ȐӢȈ᝿Ǿ FREE RUN LIST + TLI Ǽǝǭ TRIGGERED LIST + TLI ɗɭȾǥ඿‫ܥ‬ǕǤǂȉ‫ب‬ӿǭƩǑǬɉɭȤటС͖ӹǩȆȈ଄ᣜक‫ا‬ȐӢȈ᝿ǾǦԃ଄ǩ଄ᣜक‫ا‬ᗣલȠțɨȴȐȤɟȗǕǤǕǼǂǼǗƪǑǬѷ̨ǭ AD ‫࢞੄٭‬ǬȟɭɅɭɊɢɭб૲ȆȈȀхǩ‫ܩ‬ᕚǓȊȉǝǿƩȀǕƩȟɭɅɭɊɢɭǥǀǡǝȼɭȴȐၷ௻ǕǤǕǼǄǦƩ଄ᣜߪक‫ا‬Ǌ಻ᑈǕǤǕǼǂƩȼɭȴǬ͖ᧂࣕȐ੍ǫȉሟஎǦǨȈǼǗƪǑȊȐᤁ೒Ǘȉǝǿǩȟ
ɭɅɭɊɢɭǕǝȼɭȴȀେ‫ٺ‬ȶɘɨɂɠǩ͖ӹǊϗǡǤǋǝȀǬǦǽǨǕǤᗫᢉǗȉȆǄǩ‫ݘ‬ЖǕǤǂǼǗƪǗǨȍǟେ‫ٺ‬ȶɘɨɂɠǩဪࡿǗȉɆɠȮᩒǓ˿ʚǬϘǤǬϗѡ͖ӹǊƩେ‫ٺ‬ȶɘɨɂɠǩГቯǓȊǤǂȉǦᗛᠰǗȉǑǦǊС୸ǼǗƪǑǬЖ༷ૐ്ǭϘǤǬѷ̨ɗɭȾǩǈǂǤϟឨǥǗƪ

Page 41 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷

᭶᭸. ˵ౣ
SIG IN

16ch ϗѡƩ0ᯃ+10V ೓ీࣕɛɀɒɭɞɆɠȮେ‫ݦ‬ᄳǟʚǊȈ଄ᣜ᭿200nsƩେ‫ݦ‬ɆɠȮࠌ᭿500ns
Zin᭿1᮰ƩLEMO ȨɂȤȴZERO ADJUSTɊɠȮȦɭɠǬ±5᭫Ȑ 12bit Чᗛጻǥᗲ‫ܥ‬᭭Ӿ Ch ͥвǩ Programmable᭮

LLDɊɠȮȦɭɠǬ 10᭫Ȑ 12bit Чᗛጻǥᗲ‫ܥ‬᭭Ӿ Ch ͥвǩ Programmable᭮

ADC GAIN

256/512/1024/2048/4096/8192᭭Ӿ Ch ͥвǩ Programmable᭮‫੄٭‬଄ᣜ

500ns/input᭭ɉɭȤటСǉȇ FIFO ୁ᝿ǽሖˉǼǥ᭮ᄉЧ᥼ဩቒࣕ

ɊɠȮȦɭɠǬ±0.025᭫˿ʛ᭭ɊɠȮȦɭɠǬ 99᭫ᆐ‫ב‬ǩǈǂǤ᭮ࢭЧ᥼ဩቒࣕ

ɊɠȮȦɭɠǬ±1᭫˿ʛ᭭ɊɠȮȦɭɠǬ 99᭫ᆐ‫ב‬ǩǈǂǤ᭮඿‫ܥ‬ɗɭȾ

PHA/GATED LIST/FREE RUN LIST/TRIGGERED LIST䊶PHA Ǧ LIST ɗɭȾǬǂǘȊǉȐԃ଄ᗣ඿ӳጻ
䊶GATED LIST Ǧ TRIGGERED LIST ɗɭȾ଄ǭșɎɨȽȠțɨȽक‫ا‬Ȑʔ቏ǩᗫᢉ
䊶FREE RUN LIST Ǧ TRIGGERED LIST ɗɭȾ଄ǭ TSI/TLI Ǭ଄ᣜक‫ا‬Ȑʔ቏ǩᗫᢉ

Data Memory

256k×32bit Dual Port Memory
䊶PHA ɗɭȾ: 8kch×32bits×16ch ȼɭȴɖɗɟ䊶LIST ɗɭȾ127k×32bits ɟɨȥɅȸɊȖ䊶ɡȭȮȴ

: 1k×32bits

PHA ɗɭȾ

˿ʛǬʪǉȇӾ Ch ͥвǩᗲ‫ܥ‬ӳጻɌɟȰȸȽ䊶Real Time

: Off, 1secᯃ᭭232-1᭮/100sec

䊶Live Time

: Off, 1secᯃ᭭232-1᭮/100sec

䊶Peak Counts: Off, 1ᯃ232-1

䊶Area Counts: Off, 1ᯃ232-1

LIST ɅȸɊȖɟȮȽȼɭȴȪșȯǼǝǭșɎɨȽȠțɨȽલǊ৽‫ܥ‬ǬͱȐȟɭɅɭǕǝȇឨၥ

ɌɟȰȸȽ

Ǘȉƪ

Real & Live Timeେ‫ݦ‬ᗣલ଄ᣜ᭿10ms

Event Counter

COM_G/T IN ϗѡ͖ӹȐȤɢȸȤǦǗȉ 28bits șɎɨȽȠțɨȴƪ

TLI,TSI Counter଄ᣜक‫ا‬Ǭ Time Lag Information, Time Stamp information Ȑᗣ඿Ǘȉ 40bits
ȠțɨȴƪȤɢȸȤǭ˿ʛǬʪǉȇៜ৐᭭Programmable᭮
5ns/10ns/20ns/50ns/100ns/200ns/500ns/1Ìs

TLI,TSI ȼɭȴ䊶ᇠ࠱᭿5ns䊶Чᗛጻ᭿MCSR ɡȭȮȴǬȴșɕɎɭȮᗲ‫ܥ‬ǩȆȈ‫ܥ‬Ǽȉ଄ᣜȮɠɭɌȸȽ

䊶PHA᭿205kcps(Әዥͱ)

䊶FREE RUN LIST + TLI/TSI᭿109kcps
䊶TRIGGERD LIST + TLI/TSI᭿72kcps
䊶GATED LIST(kcps)᭿98/ϗѡ ch લ+5䊶PHA+LIST ԃ଄ᗣ඿଄(kcps)᭿(PᮽL)/(P + L)
          P=PHA ɗɭȾҵ໶ѷ̨଄ǬȮɠɭɌȸȽ          L=ǂǘȊǉǬ LIST ɗɭȾҵ໶ѷ̨଄ǬȮɠɭɌȸȽ
Page 42 of 43㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 A3100 User’s Manual (Rev.1.5)㩷
Fast Clear ଄ᣜେ‫ ٺ‬600ns

йࢨϗѡ

䊶G/T IN0 – 15

: Ch ͥвǬȧɭȽ/Ƚɟȡ͖ӹϗѡƩTTL ͖ӹƩLEMO

䊶COM_G/T IN: Ϙ Ch ϟឨǬȧɭȽ/Ƚɟȡ͖ӹϗѡƩTTL ͖ӹƩLEMO䊶FCLR IN: ɉɭȤɐɭɠȾ‫׌‬ᜀȐȤɟȗǗȉ͖ӹϗѡƩTTL ͖ӹƩLEMO

䊶VETO IN

: AD ‫੄٭‬ሟஎǬᗫᢉȐ৆йǗȉ͖ӹϗѡƩTTL ͖ӹƩLEMO

йࢨСѡ

䊶BUSY OUT

: Ɉȭɭ໦ेȐᕦǗ͖ӹСѡƩTTL ͖ӹƩLEMO

ATICbus IN,OUT

Acquire & Time Information Control bus
ᖜલ஍Ǭ A3100 Ȑཽǂȉ‫ب‬ӿǩƩᤱȈӿǄɗȭɚɭɠᣜȐਮሴǗȉɅȮ

VMEbus Interface

A24/A32 ȗȾɡȮ৽‫ܥ‬ɗɭȾƩD16/D32/BLT ȼɭȴᝀមƩMCST ‫ࢻݘ‬
6U1 ࠌ VME ɗȭɚɭɠ

Power+5V/0.85AƩ+12V/0.85AƩ-12V/0.9A

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