CH224 Datasheet

1

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USB PD and Other Fast Charging Protocol Sink Controller CH224Datasheet
Version: 1F
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1. Overview
CH224 integrates multiple fast charging protocols such as USB PD3.0/2.0, BC1.2, automatically detects VCONN
and simulates E-Mark chips, and supports up to 100W power. CH224 has a built-in PD communication module,with features of high integration and streamlined peripherals. It integrates output voltage detection function, andprovides over-temperature and over-voltage protection functions, etc. It can be widely used in various electronicequipment to expand high-power input, such as wireless charger, electric toothbrush, rechargeable shaver, lithium
battery power tools and other application scenarios.

2. Features
lllllllSupports 4V to 22V input voltage
Supports fast charging protocols such as PD3.0/2.0 and BC1.2.
Supports USB Type-C PD. Supports forward and reverse plug detection and automatic switching
Supports E-Mark simulation and automatic detection of VCONN, and supports 100W power PD request
The requested voltage can be dynamically adjusted by a variety of methods
The single chip has features of high integration, simplified peripherals and low costs
Built-in over-voltage protection module and over-temperature protection module

3. Applications
lllll

Wireless charger
Laptop charging cable
Lithium battery minor electric appliances
Lithium battery electric tool
Power bank

4. Pinouts and pin description
4.1. CH224 pinouts

QFN20-3*3

ESSOP-10

SOT23-6Lhttp://wch.cn

2CH224 Datasheet

4.2. CH221K pin description
Pin No.

Pin name

1VDD

2

GND

3PG

4, 56

CC1, CC2
CFG

Pin type

Pin description

Operating power input. An external 1uF decoupling capacitor
is required. Connected in series with a resistor to VBUS.
PowerGround
Open-drain
Indicate Power Good by default. Active low.
outputCustomized functions.
Input/Output
Type-C CC data line
Analog input
Power configuration input
Power4.3. CH224K pin description
Pin No.

Pin name

Pin type

0

GND

Power

1

VDD

4, 56, 7DP, DM
CC1, CC2
CFG1,
CFG2,
CFG3

2, 3, 9Pin description

Ground. Heat dissipation EPAD.
Operating power input. An external 1uF decoupling capacitor
Poweris required. Connected in series with a resistor to VBUS.
Input/Output
USB data line
Input/Output
Type-C CC data line
Analog input

Power configuration input

Analog input
Open-drainoutput

Voltage detection input. It is required to be connected inseries with a resistor to external input VBUS.
Indicate Power Good by default. Active low.
Customized functions.

Pin name

Pin type

Pin description

GND
VBUS

PowerPower

8

VBUS

10PG

4.4. CH224D pin description
Pin No.
CH224D0278, 910, 1119, 13, 12114, 1556Ground. Heat dissipation EPAD
Operating power inputInternal voltage regulator output. An external 1uF decoupling
VDD
Powercapacitor is required.
DP, DM Input/Output
USB data line
CC1, CC2 Input/Output
Type-C CC data line
CFG1 is analog input. CFG2 and CFG3 are digital inputs,
CFG1~3Input
with built-in pull-down resistors.
DRVAnalog output Weak driving output. Used to drive configuration resistor.
Differential
ISP, ISN
Used to detect operating current. Customized functions.
input
Used to drive high-side power channel NMOS.
GATE
HV output
Customized functions.
NMOS# Digital inputGATE pin drive NMOS enable. Active low.

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CH224 Datasheet

5. Functional specification
5.1. Overview
CH224 is a USB PD sink controller, supports fast charge protocols such as PD3.0/2.0 and BC1.2, supports 4V to22V, and can dynamically configure the request-voltage through multiple methods.
CH221K only supports PD3.0/2.0 protocols.
CH224K/CH224D supports resistance configuration mode and level configuration mode. CH221K only supports
resistance configuration mode.

5.2. Request-voltage configuration (CH224K/CH224D)
5.2.1 Resistance configuration mode
It is suitable for applications to achieve different request-voltages by modifying the value of the resistor in a single
PCB.
CFG1 is connected with a resistor to GND. Different request-voltages are available by configuring different
resistance values. In resistor configuration mode, the CFG2 and CFG3 pins cannot be connected. The resistances
and the corresponding request-voltages are shown in the table below.
Resistance on CFG1

Request-voltage

6.8KΩ

9V

24KΩ

12V

56KΩ

15V

NC

20V

5.2.2 Level configuration mode
It is suited when an MCU is used to dynamically adjust the request-voltage, or when the PCB circuit is notchanged.
CFG1, CFG2 and CFG3 can be directly connected to the external MCU IO ports, or directly connected to theVDD/GND pin on CH224K/CH224D.Different request-voltages are available by configuring the level on the 3pins, as shown in the table below.
CFG1

CFG2

CFG3

Request-voltage

1--5V

000

9V

001

12V01

115V

01020VIn level configuration mode, the voltage on IO ports and default states should be noted.
For CH224K, the input voltage on CFG2/CFG3 cannot be higher than 3.7V. For CH224D, the input voltage on
CFG2/CFG3 cannot be higher than 5V.
If the back-end circuits such as MCU start slowly, or if the MCU pins have a specific default state, CFG1 may bein floating state or in IO configuration mode before MCU starts working. In this case, 20V may be requested. Ifthe system cannot withstand 20V input, a configuration resistor should be added to the CFG1 pin to ensure thatCH224K/CH224D can request a suitable voltage by configuring the resistor before MCU starts working.

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CH224 Datasheet

5.3. CH221K voltage configuration
CFG is connected with a resistor to VDD. Different request voltages are available by configuring different
resistances, as shown in the table below.
Resistance on CFG to VDD

Request-voltage

10KΩ

5V

20KΩ

9V

47KΩ

12V

100KΩ

15V

200KΩ

20V

5.4. E-Mark simulation function
If you need to simulate E-Mark function to request voltage higher than 20V or power higher than 60W, you mustuse a Type-C male plug, and connect the CC2 pin with a 1 KΩ resistor to GND. (Please contact us for technicalsupport)

5.5. Only PD protocol used
If there is no need to use A-port protocols (varies protocols realized by DP.DM communication), CH221K can beselected.
If you want to block these protocols on CH224K/CH224D, the DP/DM pin on CH224K/CH224D is required to bedisconnected from the DP/DM on the Type-C connector, and the DP pin on CH224 is required to be shorted to theDM on CH224. For CH224K, the VBUS pin can be NC.

6. Reference schematic diagram
6.1. Connect CH224K/CH224D with a Type-C female port
9/12/15/20V request-voltage configuration by resistance (In the figures below, a 6.8 KΩ resistor is used toconfigure 9V request voltage)

Type-C

VBUS

VCC
DP
DM
CC1
CC2
GND

2891110

VBUS VDD
7

5.1KΩ
5.1KΩ

1uF

1uF

06

VBUS

GATE

UDP
UDM
CC1
CC2DRV
CFG1
CFG2
CFG3

51
19
13
12

VDD

CH224D

GND
NMOS#CH224D

ISP
ISN

1415Rset
6.8KΩ

Rset

Request-voltage

6.8 KΩ
24 KΩ
56 KΩ
NC

9V
12V
15V
20V

CH224 Datasheet

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56.2. Connect CH224K with a Type-C female port
5/9/12/15/20V request-voltage configuration by level (In the figure below, the request voltage is configured to12V by level)
CFG1

CFG2

CFG3

10000001101
10

Requestvoltage
5V9V12 V15 V20 V

6.3. Connect CH224K with a Type-C male port
Only PD protocol is used, with E-Mark simulation function (In the figure below, the request voltage is configured
to 20V with the resistor NC)

6.4. Connect CH221K with a Type-C male port
20V request-voltage configuration by levelhttp://wch.cn

6CH224 Datasheet

7. Parameters7.1. Absolute maximum ratings of CH221K
Operating in critical ratings or exceeding the absolute maximum ratings may cause the chip to work abnormally oreven be damaged.
SymbolParameter description

Min.

Max.

Unit

TA

Operating ambient temperature

-40

105℃

TS

Storage ambient temperature
Operating supply voltage (VDD is connected to power, GND toground)

-55

150℃

-0.5

5.8

V

VDD
VODHV

Voltage on high-voltage open-drain output pin PG

-0.5

13.5

V

VIOCC

Voltage on CC1 and CC2-0.58V

VIOUX

Voltage on CFG
Maximum power consumption of the entire chip
(VDD voltage * current)-0.5

VDD+0.5

V250mWPD

7.2. Absolute maximum ratings of CH224K
Operating in critical ratings or exceeding the absolute maximum ratings may cause the chip to work abnormally oreven be damaged.
SymbolParameter description

Min.

Max.

Unit

TA

Operating ambient temperature-4090℃TS

Storage ambient temperature

-55

105℃

VDD

Operating supply voltage (VDD is connected to power, GND toground)

3.0

3.6

V

VIOHV

Voltage on CFG and VBUS which support high voltage

-0.5

13.5

VVIOCC

Voltage on CC1, CC2 and CFG1-0.5

8

V

VIOUX

Voltage on DP, DM, CFG, CFG2 and CFG3-0.5

VDD+0.5

V

VIOLV

Voltage on CFGHV
Maximum power consumption of the entire chip
(VDD voltage * current)

0.8

V400mW

PD

7.3. Absolute maximum ratings of CH224D
Operating in critical ratings or exceeding the absolute maximum ratings may cause the chip to work abnormally oreven be damaged.
SymbolParameter description

Min.

Max.

UnitTA

Operating ambient temperature-40100℃TSStorage ambient temperature

-55

125℃

-0.5

6V-0.524V

VIOHV

Operating supply voltage (VDD is connected to power, GND toground)
Voltage on VBUS

VIOCC

Voltage on CC1 and CC2-0.5

20V

VIOUX

Voltage on DP, DM, CFG1, CFG2, CFG3, DRV, NMOS#, ISP andISN-0.5

VDD+0.5

V-0.5

VIOHV+6.5

V300mW

VDD

VIOHXPD

Voltage on GATE
Maximum power consumption of the entire chip
(VDD voltage * current)

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CH224 Datasheet

7.4. Electrical characteristics of CH221K
Test condition: TA=25℃
SymbolParameter description

Min.

Typ.

Max.

Unit

VLDOK

CH221K internal power regulator VDD parallel voltage

3.0

3.3

3.6

VILDO

Draw current on VDD pin

030mA

VR

Voltage threshold of power-on reset

2.2

2.4

2.6

V

7.5. Electrical characteristics of CH224K
Test condition: TA=25℃
SymbolParameter description

Min.

Typ.

Max.

Unit

VLDOK

CH224K internal power regulator VDD parallel voltage

3.24

3.3

3.36

VILDO

Draw current on VDD pin

030mA

TOTA

Reference threshold of the over-temperature module (OTA)

90105120℃VR

Power-on reset threshold

2.2

2.4

2.6

V

7.6. Electrical characteristics of CH224D
Test condition: TA=25℃
SymbolParameter description

Min.

Typ.

Max.

Unit

VLDO

Internal power regulator VDD output voltage

4.65

4.7

4.75

VILDO

Internal power regulator VDD out-load capability

10mA

VR

Power-on reset threshold

2.6

V

2.2

2.4

8. Package
Package

Body size

Lead pitch

Description

Part No.

QFN203*3mm

118mil0.40mm

15.7mil

Quad flat no-lead package

CH224DESSOP103.9mm

150mil

1.00mm39mil

Shrink small outline package withEPAD 10-pin patch

CH224K

SOT23-6L

1.6mm

63mil

0.95mm37mil

Small outline 6-pin patch

CH221KCH224 Datasheet

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Note: All dimensions are in millimeters.

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