ARTICLE IN PRESS

Nuclear Instruments and Methods in Physics Research A 579 (2007) 706–711
www.elsevier.com/locate/nima

Evaluation of OKI SOI technology
Y. Ikegamia,, Y. Araia, K. Harab, M. Hazumia, H. Ikedac, H. Ishinod, T. Kohrikia,
H. Miyakee, A. Mochizukib, S. Teradaa, T. Tsuboyamaa, Y. Unnoaa

IPNS, High Energy Accelerator Research Organization, KEK, Tsukuba, Ibaraki 305-0801, Japan
Institute of Pure and Applied Sciences, University of Tsukuba, Tsukuba, Ibaraki 305-8571, Japanc
ISAS, Japan Aerospace Exploration Agency, Kanagawa 229-8510, Japand
Department of Physics, Tokyo Institute of Technology, Tokyo 152-8551, Japane
Department of Physics, Graduate School of Science, Osaka University, Osaka 560-0043, Japanb

Available online 25 May 2007

Abstract
The silicon-on-insulator (SOI) CMOS technology has a number of advantages over the standard bulk CMOS technology, such as nolatch-up effect, high speed and low power. The fully depleted SOI (FD-SOI) technology provided by OKI Electric Industry Co., Ltd. isrealizing the full features of the advantages with lowest junction capacitance. Test element group (TEG) structures of transistors were
fabricated and irradiated with protons. The ﬁrst results are presented.
r 2007 Published by Elsevier B.V.
Keywords: SOI; CMOS; FET; Radiation damage

1. Introduction

2. Transistor TEG circuit

The silicon-on-insulator (SOI) CMOS technology has anumber of advantages over the standard bulk CMOS
technology, such as no latch-up effect, high-speed and lowpower dissipation. A monolithic pixel detector featuring
these advantages [1] is being developed under KEK
Detector Technology Project. The fully depleted SOI(FD-SOI) CMOS technology provided by OKI ElectricIndustry Co., Ltd. is realizing the full features of theadvantages with lowest junction capacitance [2]. In
addition, high-radiation tolerance is expected, especiallyagainst single-event latchup, since the devices are fabricated using a very thin (40 nm) silicon layer. Therefore, we
are investigating front-end circuits using the same technology [3] to apply them in high-radiation environment. In
this paper, we report the ﬁrst results concerning the total
dose effects for transistors fabricated using the OKI
0.15 mm FD-SOI CMOS process.

The test element group (TEG) chip consists of a matrixof 32 NMOS and 32 PMOS transistors in order to extract
DC characteristics efﬁciently [4]. Fig. 1 shows a schematic
diagram of the transistor TEG circuit. Each transistor isselected by 3-bit column and 3-bit row decoders and NOR
and NAND gates. ESD protection diodes are implemented
in all IO terminals of the TEG chip. PMOS transistors arelocated from 0 to 3 rows. NMOS transistors are locatedfrom 4 to 7 rows. The transistors in 0, 1, 4, and 5 rows havebody-tie contacts, which connect the source electrode to
the body of the transistor via metal layer. The device
structure of body ﬂoating and body-tied transistors isshown in Fig. 2. In the shuttle service, OKI provides three
types of transistors: I/O transistors (IO) with 5 nm thickgate oxide layer, and high-VT (HVT) transistors for logic
circuits and low-VT (LVT) transistors for analog circuitswith 2.5 nm thick gate oxide layer. The voltage tolerances
are 1.8 V for I/O circuits, and 1 V for core circuits. The
parameters of each type of transistors are listed in Table 1.
With ﬁxing the W/L ratio to 2000, we tested two to threewidth and length combinations for each transistor type, asCorresponding author. Tel.: +81 29 864 5353; fax: +81 29 864 2580.

E-mail address: ikegami@post.kek.jp (Y. Ikegami).
0168-9002/$ - see front matter r 2007 Published by Elsevier B.V.
doi:10.1016/j.nima.2007.05.272

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Fig. 1. Schematic diagram of the transistor TEG circuit.

Fig. 2. Device structure of ﬂoating body and body-tie transistors.

summarized in Table 2. The buried oxide layer is 200 nm
thick. The backside of wafer was ground down mechanically from 650 to 350 mm thickness, and then plated with
200 nm of aluminum, which is used for back-gate biasing.
Figs. 3 and 4 show details of N and PMOS transistor
cells. The drains of all N and PMOS DUT (device-undertest) transistors are ganged together, respectively. The gatesin the same column are connected to a common. The
sources are connected to another common via M2 and M3
switches. These switches are operated by 3-bit column and3-bit row decoders. The voltage of IDM is ﬁxed to 0 and
1 V for N and PMOS cells, respectively. The TEG
characterization is to measure the drain current (Ids) as afunction of the gate-source (Vgs) voltage while keeping
constant the drain-source voltage (Vds). The voltages of Vgs

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and Vds are controlled by the external voltages of VGF and
VDF with taking account of the ﬁnite on resistance of theM2 switch. The voltages of Vgs and Vds were actually
adjusted iteratively by monitoring the voltage of VSM. The
M8 switch was set off during measurement.

covered the TEG chip fully. Assuming an SCT environment in the SLHC operation [5], we planned to irradiate six
chips each up to 0.1, 0.2, 0.5, 1.0, 2.0, and 5.0  1015 neq/cm2.
For a beam current between 10 and 300 nA, theirradiation time was in the range between 10 and50 min. The samples were irradiated at room temperature
with their terminals shorted using conductive sponge.
The condition of terminals shorted does not necessarily
correspond to the worst case for the radiation-induced
damage. Irradiations with different bias conditions would be
useful in future tests. The ﬂuence was calculated later bymeasuring the Na24 product from the Al foil attached toeach TEG chip. Unfortunately, the obtained ﬂuence values
turned out to about 15 of those expected from the beam
current and exposure time. The beam current was ameasurement from a monitor located in the beam pipe
upstream of the samples. The beam tuning was not
appropriate inducing substantial loss hitting the beam ﬂange.
Finally, the obtained ﬂuence values were 0.03, 0.05, 0.09, 0.2,
0.4, and 1.0  1015 neq/cm2. The ionization dose to SiO2 was
0.026 MGy (SiO2) for 3  1013 1 MeV neq/cm2 and 0.85 MGy(SiO2) for 1.0  1015 1 MeV neq/cm2, respectively.

3. Irradiation
Sample TEGs were irradiated with 70 MeV protons at
Cyclotron and Radioisotope Center (CYRIC), Tohoku
University on June 26, 2006. The beam was about 5 mm
full-width at half-maximum (FWHM) in size, which
Table 1
Transistor parameters
Transistor type

HVT, highthresholdbasic logic

LVT, lowthresholdanalog

IO, highthreshold
I/O

Voltage tolerance (V)Gate oxide thickness (nm)Minimum gate length(mm)
Threshold voltage (V)

1.0
2.5
0.14

1.0
2.5
0.14

1.8
5.0
0.30

0.4

0.2

0.5

4. Results
The DC characteristics were evaluated before and after
irradiation by measuring the drain current as a function of
the gate-source voltage. Vds was ﬁxed to 0.5 and 0.5 V for
N and PMOS DUTs, respectively. Due to a layout failure,
all M2 switches are always on for the 1, 2, 4, 5, and 7
columns: four N and four P DUT transistors with the same
type and size are connected in parallel in one column.
Although distinction of N and P is possible by using
corresponding terminals, the four DUT transistors cannot
be measured individually. Since the difference among thefour is whether body ﬂoating or body tied, and the results
were almost identical among these in the data for 0, 3,
and 6 columns, we regard those data as a sum of four

Table 2
Transistor TEG types and sizes
Column ID

Transistor type

Gate width (mm)Gate length (mm)

0
1
2
3
4
5
6
7

LVT
LVT
LVT
HVT
HVT
HVT
IO
IO

280
600
1000
280
600
1000
600
1000

0.14
0.30
0.50
0.14
0.30
0.50
0.30
0.50

LVT, low threshold; HVT, high threshold; IO, I/O transistors.
VDF

M1
DUT

VGF

L-0.3U W-30U

L-0.3U W-1U
M8

M2

L-0.3U W-25U M-10

VSM
VDD

M3

L-0.3U W-2U
L-0.3U W-2U

E_x

IDM

M7

COL_x

M6

ROW_x

L-0.3U W-1U
M5

Fig. 3. NMOS transistor cell circuit.

M4

L-0.3U W-1U

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VDF
M1
DUT

VGF
VDD

L-0.3U W-15 M-2

L-0.3U W-1U
M8

M2
L-0.3U W-25U M-10

VSM

M3

VDD
M4

M5
L-0.3U W-2U

E

IDM

L-0.3U W-2U

COL

L-0.3U W-1U
M6
L-0.3U W-1U

ROW
M7

Fig. 4. PMOS transistor cell circuit.

transistors connected in parallel. The current corresponding to one transistor is obtained as one-fourth of themeasured current.
Fig. 5 shows the Ids–Vgs characteristics of typical NMOS
transistors, LVT with body ﬂoating, before and after
irradiation. The measurement relevant to the highest
ﬂuence is truncated at Vgs ¼ 0.5 V due to current compliance. Since the threshold voltage decreases after
irradiation, the drain current increases at the same Vgs.
Only minor differences can be observed between curves
relevant to different ﬂuence values: they seem to be alreadysaturated at the lowest ﬂuence. A large increase in theleakage current to a 0.1 mA level is also seen in the sub
threshold region. The leakage of the pre-irradiation
samples shold be in the range of 108A at Vgs ¼ 0 V [2].
The observed large values are probably due to an inﬂuence
from the leakage current of ESD protection diodes
implemented in the TEG IO terminals.
Fig. 6 shows the Ids–Vgs characteristics of typical PMOS
transistors. The threshold voltage also decreases after
irradiation. However, the drain current decreases, contrary
to the NMOS transistors. No increase is seen in the leakage
current in the sub-threshold region. In the case of PMOS
transistors, slight ﬂuence dependence can be seen. This
could be attributed to incorrect VSM measurement, sinceon resistance of M3 PMOS switch rises with irradiation,and cannot be ignored with respect to the input resistor of
the voltmeter (1 MO). On the other hand, in the case of
NMOS transistors, VSM can be measured correctly, since
there is no rise of the on resistance. In order to clarify thispoint, new TEG chips without having cell structure(transistor terminals will be led directly) will be designed
for the next irradiation test.
The total dose damages are primarily explained [6] byradiation-induced charge buildup in the oxides. As the
SOI-buried oxides are exposed to ionizing radiation,
radiation-induced charges are trapped throughout theFig. 5. Ids–Vgs characteristics of typical NMOS transistors before andafter irradiation.

Fig. 6. Ids–Vgs characteristics of typical PMOS transistors before and after
irradiation.

buried oxide. The trapped charges are predominantly
positive. The FD-SOI transistors are sensitive to thetrapped charges in the oxide layer and at the silicon/oxide

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interface, since the top-gate transistor is electricallycoupled to the back-gate transistor. For NMOS transistors, charge trapping in the buried oxide decreases the topgate threshold voltage. The oxide charges can invert the
body at the oxide interface and increase the leak current of
the back-gate transistors. This also affects the top-gatecharacteristics.
Fig. 7 summarizes the threshold voltage shift. The
voltage reference is deﬁned by Vgs, where ID ¼ 500 mA.
The threshold voltage shift is given by the difference of thereferences before and after irradiation. The threshold shifts
are found to be about 0.1 V for NMOS (LVT) and PMOS
(LVT, HVT), 0.2 V for NMOS (HVT), and 0.35 V for
N and PMOS (IO), respectively. Since the gate oxide layer
is thicker for IO transistors, the shifts are substantial.
Our results are compared with recent results from thebulk CMOS technology. According to Ref. [7], a 24 GeV
proton irradiation test was performed for 0.13 mm bulk
CMOS process transistors up to 1016 24 GeV protons/cm2.
No threshold shift was observed for N-type CMOS
transistors at the highest ﬂuence. On the other hand,about 20 mV threshold shift was observed at the ﬂuenceof 2.0  1015 24 GeV protons/cm2 for P-type CMOS
transistors. This ﬂuence of 2.0  1015 24 GeV protons/cm2
is about twice higher than our highest ﬂuence. Since
the back-gate transistor does not exist in bulk CMOS,
the threshold shift is considerably small compared with
FD-SOI CMOS.
In order to reduce these large threshold shifts in the
FD-SOI CMOS technology, compensation by the backgate voltage is investigated for the TEG chip with largest
ﬂuence. Figs. 8 and 9 show the Ids–Vgs characteristics forsome back-gate voltages. The threshold shift compensation

Fig. 8. Ids–Vgs characteristics of typical NMOS transistors for someback-gate voltages.

NMOS VT shift

0

-0.05

-0.05

-0.1

-0.1

-0.15

-0.15

Δ VT [V]Δ VT [V]0by biasing the back gate is shown in Fig. 10. Since wefound only minor differences in the characteristics oftransistors having different gate length, the results for the
shortest gate length only are shown. The threshold of
NMOS transistors decreases with the back-gate bias
almost linearly. On the other hand, the threshold of PMOS
transistors changes steeply in the region below 25 V.
First, the threshold shift for NMOS (LVT) is recovered bybiasing the back gate to about 20 V. Secondly, thethreshold shift for NMOS (IO) and PMOS (LVT and
HVT) is recovered by biasing the back gate to about
25 V. Lastly, the threshold shift for NMOS (HVT) and
PMOS (IO) is recovered by biasing the back gate toabout 30 V. We will check again in the next irradiation

-0.2
-0.25

-0.2
-0.25

-0.3

-0.3

-0.35

-0.35

-0.4
1.0E+13

1.0E+141.0E+15PMOS VT shift-0.4
1.0E+132]

1.0E+14
Fluence [neq/cm2]

Fluence [neq/cm

LVT 0.15/300

HVT 0.30/600

LVT 0.30/600
LVT 0.5/1000
HVT 0.15/300

HVT 0.50/1000
IO 0.30/600
IO 0.50/1000

Fig. 7. Threshold voltage shift summary.

1.0E+15

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Fig. 9. Ids–Vgs characteristics of typical NMOS transistors for someback-gate voltages.

711

Fig. 11. Leakage current compensation by back-gate voltage.

5. SummaryFig. 10. Threshold shift compensation by back-gate voltage.

We have irradiated OKI SOI CMOS transistors up to
1.0  1015 neq/cm2. The threshold shifts are found to beabout 0.1 V for NMOS (LVT) and PMOS (LVT, HVT),0.2 V for NMOS (HVT), and 0.35 V for N and
PMOS (IO), respectively. For the sample irradiated to
1.0  1015 neq/cm2, compensation by biasing the back-gate
was investigated, resulting that the threshold shifts arerecovered at about 20 V for NMOS (LVT), 25 V for
NMOS (IO) and PMOS (LVT, HVT), and 30 V NMOS
(HVT), respectively.
We are planning a next irradiation test up to
5.0  1015 neq/cm2. New TEG chips without having cellstructure will be introduced in order to measure thedetailed characteristic directly.
References

test, whether the difference among these compensation
voltages is essential or not.
Fig. 11 shows the leak currents in the sub thresholdregion evaluated by the current at Vgs ¼ 0 V. The optimalvalue of the back-gate bias is found to be about 20 V. It
turns out that the optimal back-gate voltage for threshold
shift compensation agrees mostly with the optimal value
for the leak current. The leak current after compensation isof the order of 1 mA.

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[5] CERN Council Resolution, The European Strategy for Particle
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