Nuclear Inst. and Methods in Physics Research, A 924 (2019) 404–408

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Nuclear Inst. and Methods in Physics Research, A
journal homepage: www.elsevier.com/locate/nima

Investigation of radiation hardness improvement by applying back-gatebias for FD-SOI MOSFETs
Ikuo Kurachi a, *, Kazuo Kobayashi b , Masao Okihara c , Hiroki Kasai d , Takaki Hatsui b ,Kazuhiko Hara e , Toshinobu Miyoshi a , Yasuo Arai aaHigh Energy Accelerator Research Organization, Tsukuba, Ibaraki 305-0801, JapanRIKEN Spring-8 Center, Sayo, Hyogo 679-5148, Japanc
Lapis Semiconductor Company, Ltd., Yokohama, Kanagawa 222-8575, Japand Lapis Semiconductor Miyagi Company, Ltd., Oohira, Miyagi 981-3693, Japane University of Tsukuba, Tsukuba, Ibaraki 305-8571, Japanb

ARTICLEINFO

Keywords:
Fully depleted silicon on insulator
Metal oxide silicon field effect transistor
Radiation hardness
Back-gate bias

ABSTRACT
Radiation hardness improvement of fully depleted silicon on insulator (FD-SOI) metal-oxide-silicon field effecttransistors (MOSFETs) has been investigated in terms of back-gate bias recovering to compensate generated
positive charge in buried oxide (BOX) by X-ray irradiation. In general, the radiation tolerance of FD-SOI MOSFETs
is low in total ionizing dose (TID) due to the generated positive charge in BOX. However, biasing the back-gate tonegative can compensate the charge. In the method, the electrode of back-gate should cover both N and P channel
different gate length MOSFETs to minimize area penalty. To reduce the gate length dependent characteristicchange by the irradiation, high dose lightly doped drain (LDD) is newly introduced. The back-gate bias windows
within 100 mV in the threshold voltage and 15% in the drain current change up to 112 kGy(Si) X-ray irradiation
has been confirmed for the N and P channel MOSFETs of wide gate length range from 0.2 to 10 μm.

Contents
1.
2.
3.

4.

Introduction .................................................................................................................................................................................................... 404
Experimental ................................................................................................................................................................................................... 405
Results and discussion ...................................................................................................................................................................................... 406
3.1.
RIGLEM improvement by higher dose LDD .............................................................................................................................................. 406
3.2.
Characteristic recovering by back-gate bias ............................................................................................................................................. 407
3.3.
Back-gate bias windows......................................................................................................................................................................... 408
Conclusion ...................................................................................................................................................................................................... 408
Acknowledgments ............................................................................................................................................................................................ 408
References....................................................................................................................................................................................................... 408

1. Introduction
A monolithic pixel imager using silicon on insulator (SOI) technology
has been considered to be a suitable detector for scientific experiments
such as X-ray imaging, X-ray energy spectrum analysis, and charged
particle tracking [1]. The advantages of SOI pixel imager are small pixel
size owing to sub-micron via between the sensor and the circuitry andstacking of the circuitry on the sensor, high gain owing to small parasitic
capacitance of the sense node, and low cost and high reliability owing*

to the commercial semiconductor device process [2]. From radiation
hardness point of view, the capture cross section of single event upset(SEU) is smaller than bulk complimentary metal-oxide-semiconductor(CMOS) because of the transistor’s perfect isolation by oxide and nothyristor structure in SOI [3]. However, it is well known that SOI has
weakness in total ionizing dose (TID). The major X-ray irradiation inducing damages of the metal-oxide-silicon field effect transistor (MOSFET)
are caused by the generated positive charge in oxide and the generated
traps at interface between oxide and silicon [4]. When X-ray irradiatedCorrespondence to: High Energy Accelerator Research Organization, 1-1 Oho, Tsukuba, Ibaraki 305-0801, Japan.
E-mail address: kurachii@post.kek.jp (I. Kurachi).

https://doi.org/10.1016/j.nima.2018.05.068
Received 31 January 2018; Received in revised form 7 May 2018; Accepted 29 May 2018
Available online 13 June 20180168-9002/© 2018 Elsevier B.V. All rights reserved.

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Nuclear Inst. and Methods in Physics Research, A 924 (2019) 404–408

Fig. 1. Schematic cross section of FD-SOI MOSFET after X-ray irradiation for
N channel MOSFET. In the case of P channel MOSFET, the generated positive
charge and interface traps are the same but n+, n−, and p must be replaced byp+, p−, and n, respectively.

Fig. 2. Drain current change after 112 kGy(Si) irradiation as a function of gate
length for N channel MOSFETs. The blue line indicates low dose LDD and theorange line high dose LDD. (For interpretation of the references to color in thisfigure legend, the reader is referred to the web version of this article.)

to SOI-MOSFET, electron–hole pairs are generated in gate oxide, buriedoxide (BOX), and sidewall spacer. Some of the generated electrons
and holes are recombined and the rest of electrons and holes drift byelectric field in the oxide. Because the mobility of hole in oxide islower than that of electron, some of the generated holes are trappedin the oxide. Thus, positive charge generated in the oxide by X-ray
irradiation. The holes which drift to Si-SiO2 interface create interface
traps. From the structure of SOI-MOSFET, the positive charges are
generated in gate oxide, BOX, and sidewall spacer. The traps are also
generated at the interface between body silicon and gate oxide as shownin Fig. 1. The generated positive charge in sidewall spacer and interface
traps at gate edge make gate length dependent characteristic change
called as radiation induced gate length modulation (RIGLEM) [5,6].
On the other hand, the generated positive charge in gate oxide or thegenerated positive charge in BOX and the interface traps at gate centerare considered to be no or less gate length dependence. The gate length
independent characteristic change can be compensated by applying theback-gate bias through buried well in handle wafer in the case of single
SOI or middle SOI in the case of double SOI [7]. Thus, to work the backgate bias recovering efficiently, RIGLEM must be improved. In addition,
it should be better to use the common back-gate bias electrodes for N
and P channel transistors with various gate length to minimize the area
penalty because of relatively rough design rule of the buried well or
middle SOI patterns and due to keeping N and P channel active merge
technique [8].
In this paper, RIGLEM improvement by high dose lightly doped drain(LDD) and characteristics recovering by applying proper back-gate bias
are shown. The back-gate bias windows to keep given allowable rangesof threshold voltage and drain current change are also investigated when
the back-gate electrode of the N and P channel MOSFETs with wide
range of gate length is assumed to be in the same back-gate electrodeplane.

Fig. 3. Drain current change after 112 kGy(Si) irradiation as a function of gate
length for P channel MOSFETs. The blue line indicates low dose LDD and theorange line high dose LDD [13]. (For interpretation of the references to color
in this figure legend, the reader is referred to the web version of this article.)which were relatively low or high dose were examined. BOX, final SOI,
and gate oxide thickness are 200 nm, 40 nm, and 4.5 nm, respectively.
Floating body N and P channel MOSFETs with constant gate width of
10 μm and gate length of 0.2, 0.3, 0.5, 1.0, and 10 μm were examined.
Evaluating MOSFET parameters are threshold voltages (𝑉𝑡 ) and linear
region drain current (𝐼𝑑 ) measured from 𝐼𝑑 –𝑉𝑔 characteristics with
|𝑉𝑑 | = 0.1 V and varying the back-gate bias, 𝑉back-gate , applied to theburied well from −18 to +2 V at room temperature. The thresholdvoltages are extracted from the 𝐼𝑑 –𝑉𝑔 curves at the maximum transconductance point. The linear region drain currents, 𝐼𝑑 , were measured at|𝑉𝑑 | = 0.1 V and |𝑉𝑔 | = 1.8 V. The drain current change is defined as
𝛥𝐼𝑑 ∕𝐼𝑑0 =(𝐼𝑑 –𝐼𝑑0 )/𝐼𝑑0 where 𝐼𝑑0 is linear region drain current of the
pre-irradiation MOSFET.
To perform X-ray irradiation, a newly developed wafer level X-ray
irradiation system was used [12]. The system has X-ray generator ofa molybdenum rotary target with an acceleration voltage of 40 kV
and a 0.5 mm thick aluminum filter to eliminate X-rays below 10
keV. X-ray dose rate was set to 3 Gy(Si)/s. During irradiation, allterminals of MOSFETs were connected to the ground. Even though the

2. Experimental
Test structures consisted of fully depleted SOI (FD-SOI) MOSFETs
were fabricated by using a 0.2 μm FD-SOI CMOS process preparedby Lapis semiconductor [9]. To reduce the effect of positive charge
generated by X-ray irradiation in the isolation oxide which is called
as radiation induced narrow channel effect (RINCE) [10], impurity
doping to the sidewall of SOI active was employed. Salicided active andgate poly silicon were also employed to reduce parasitic resistance andmake contact reliable [11]. Conventional LDD structure with a 100 nm
sidewall spacer was used. In the LDD process, two implant conditions405

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Nuclear Inst. and Methods in Physics Research, A 924 (2019) 404–408

Fig. 4. 𝐼𝑑 –𝑉𝑔 characteristics of pre and irradiated N channel MOSFET with (a) 𝑉back-gate = 0 V and (b) back-gate bias to align 𝑉𝑡 to pre irradiated one.

terminals should be biased under the operation condition when theactual operation is considered, data of all terminal grounded was chosen
for the simple analysis.
3. Results and discussion
3.1. RIGLEM improvement by higher dose LDD
In the case of N channel MOSFETs, increase of the drain current
is mainly caused by the generated positive charge in BOX which has
no or less gate length dependence. On the other hand, the decreaseof drain current is mainly caused by the generated interface traps at
the gate edge from analysis of charge pumping method which will bereported in the future. Therefore, to reduce the gate length dependence,
the high dose LDD is one of counter measures because the dopants of
LDD diffuse laterally and cover the gate edge region as an n- diffusion
layer. The N channel MOSFET’s drain current change after 112 kGy(Si)X-ray irradiation as a function of gate length are shown for the low andhigh dose LDD in Fig. 2. The gate length dependence of drain current
change is slightly improved by the high dose LDD. When the back-gatebias recovering is used, the improvement is obvious as described in thenext section. The P channel MOSFET’s drain current change after 112
kGy(Si) X-ray irradiation as a function of gate length are shown for
low and high dose LDD in Fig. 3. In the case of P channel MOSFETs,
the drain current decreases monotonically with X-ray dose due to thegenerated positive charge in BOX. The gate length dependence of draincurrent change for the low LDD dose is caused by the generated positive
charge in sidewall spacer [5]. By using
the high dose LDD, theFig. 5. N channel MOSFET drain current change with 𝑉back-gate to adjust 𝑉𝑡 as afunction of X-ray dose for short (0.2 μm) and long (10 μm) channel devices.
The blue lines indicate low dose LDD and the orange lines high dose LDD.
(For interpretation of the references to color in this figure legend, the reader
is referred to the web version of this article.)

Fig. 6. 𝐼𝑑 –𝑉𝑔 characteristics of pre and irradiated P channel MOSFET with (a) 𝑉back-gate = 0 V and (b) back-gate bias to align 𝑉𝑡 to pre irradiated one.
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Nuclear Inst. and Methods in Physics Research, A 924 (2019) 404–408

gate length dependent drain current change is improved as shown in
Fig. 3.
3.2. Characteristic recovering by back-gate bias
The gate length dependence of the drain current change is improvedby using the high dose LDD for both N and P channel MOSFETs. With thehigh dose LDD MOSFETs, characteristic recovering by back-gate bias isinvestigated after X-ray irradiation up to 112 kGy(Si). In this recovering,
the back-gate bias is set to adjust the threshold voltage to that of preirradiation. The N channel 0.2 μm MOSFETs’ 𝐼𝑑 –𝑉𝑔 characteristics when
the back-gate bias is the ground or set to adjust the threshold voltage
are shown in Fig. 4(a) or (b), respectively. When the back-gate bias is
the ground, the drain current increases after X-ray irradiation becauseof the threshold voltage decrease due to the generated positive charge
in BOX. On the other hand, the drain current decreases with X-ray dosewhen the threshold voltage is adjusted by the back-gate bias because of
the mobility reduction by the generated interface traps. If the generated
charge by X-ray irradiation is uniformly distributed in the plane of oxide,
the charge is easily compensated by field effect of the back-gate bias.
On the other hand, the mobility reduction by the generated interface
traps is hardly compensated by the field effect of the back-gate bias.
It is also noted that the high dose LDD improves the drain current

Fig. 7. Correlation between required 𝑉back-gate to adjust 𝑉𝑡 for N channel andthat for P channel MOSFETs.

Fig. 8. The maximum threshold voltage change (a), (c), (e) and drain current change (b), (d), (f) within the gate length range from 0.2 to 10 μm as a function of𝑉back-gate after 1.1 kGy(Si) (a), (b), 22 kGy(Si) (c), (d), and 112 kGy(Si) (e), (f) X-ray irradiation.
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Nuclear Inst. and Methods in Physics Research, A 924 (2019) 404–408

the maximum threshold voltage or drain current changes from preirradiation at 𝑉back-gate = 0 V within the gate length range of 0.2 to10 μm with varying the back-gate bias after X-ray irradiation are taken
for the N and P channel MOSFETs. The results are shown in Fig. 8 in
the case of 1.1, 22, and 112 kGy(Si) irradiation. As show in the figure,there is no back-gate bias widows up to 112 kGy(Si) irradiation when
the allowable range is 50 mV in the threshold voltage change or 10%
in the drain current change. When the allowable range is set to 100 mVin the threshold voltage change or 15% in the drain current change, theexisting of back-gate bias windows are confirmed as shown in Fig. 9.
4. Conclusion
The FD-SOI MOSFET radiation hardness improvement has been
investigated in terms of applying the back-gate bias to compensate
the generated positive charge in BOX by X-ray irradiation. The buried
well in handle wafer for the single SOI or the middle SOI for the
double SOI can be used as the back-gate electrodes. To minimize thearea penalty by introducing the back-gate electrode, the common backgate electrodes is considered for the N and P channel MOSFETs withdifferent gate length from 0.2 to 10 μm. The high dose LDD can help
to recover the characteristics of different gate length MOSFETs because
RIGLEM is reduced for the N channel and almost eliminated for the P
channel MOSFETs. It is also confirmed that the back-gate bias windows
to recover the characteristics up to 112 kGy(Si) X-ray irradiation whenthe 100 mV in the threshold voltage and 15% in the drain current
changes are assumed to be the allowable range for the device operation.
This method may be one of solution candidates for radiation hardness
improvement of TID weak FD-SOI MOSFETs.

Fig. 9. Back-gate bias windows to allow 100 mV threshold voltage change and
15% drain current change as a function of X-ray dose.

change with the back-gate bias to adjust the threshold voltage especiallyshorter gate length as shown in Fig. 5. The 𝐿 = 0.2 μm MOSFET draincurrent change of high dose LDD is only around 15% after 112 kGy(Si)irradiation while the drain current change of the low dose LDD is around40%. The P channel 0.2 μm MOSFETs’ 𝐼𝑑 –𝑉𝑔 characteristics when the
back-gate bias is the ground or set to adjust the threshold voltage areshown in Fig. 6(a) or (b), respectively. When the threshold voltage isadjusted by the back-gate bias, the drain currents are almost identicalup to 112 kGy(Si) irradiation even though the gate length is 0.2 μm.
It is confirmed that applying the back-gate bias is efficient to recover
the characteristics after X-ray irradiation for both N and P channel
MOSFETs. The correlation between the required back-gate biases toadjust the threshold voltages for N channel and those for P channel arealso shown in Fig. 7 as a parameter of the gate length. The required backgate biases are approximately on the same trend except for 𝐿 = 0.2 μm
case due to RIGLEM of the N channel MOSFETs. The biases of P channel
are always lower than those of N channel which may be caused by work
function deference between body silicon and buried well. In the case of
P channel, the generated holes tend to migrate to the buried well.

Acknowledgments
This work was supported in part by the KEK Detector Technology
Project within the Ministry of Education, Culture, Sports, Science andTechnology (MEXT) through the Grants-in-Aid for Scientific Researchunder Grant 25109001, in part by the X-ray Free Electron Laser Priority
Strategy Program within MEXT, and in part by the Japan Society for the
Promotion of Science Grants-in-Aid for Scientific Research under Grant
13321217.
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3.3. Back-gate bias windows
The applying negative back-gate bias is confirmed to be an effective
method to recover characteristics after X-ray irradiation. However,
the required back-gate voltage to adjust the threshold voltage must
be different between N and P channel MOSFETs. Even though the
back-gate voltages are different, the back-gate electrode for N and P
channel MOSFETs should be in the same plane in order to minimize
area penalty and keeping N and P channel active merge technique.
Thus, the back-gate bias windows to recover the characteristics withina given allowable range of the threshold voltage or drain current
change have to be investigated. To define the back-gate bias windows,

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