Nuclear Instruments and Methods in Physics Research A 699 (2013) 72–77

Contents lists available at SciVerse ScienceDirect

Nuclear Instruments and Methods inPhysics Research A
journal homepage: www.elsevier.com/locate/nima

Development of novel n þ -in-p Silicon Planar Pixel Sensors for HL-LHC
Y. Unno b,n, C. Gallrapp a, R. Hori b, J. Idarraga g, S. Mitsui h, R. Nagai i, T. Kishida i, A. Ishida c, M. Ishihara c,S. Kamada c, T. Inuzuka c, K. Yamamura c, K. Hara j, Y. Ikegami b, O. Jinnouchi i, A. Lounis g, Y. Takahashi j,
Y. Takubo b, S. Terada b, K. Hanagaki f, N. Kimura k, K. Nagai j, I. Nakano e, R. Takashima d, J. Tojo b,
K. Yorita kaEuropean Organization for Nuclear Research (CERN), CH-1211, Geneve 23, Switzerland
Institute of Particle and Nuclear Study, High Energy Accelerator Research Organization (KEK), 1-1 Oho, Tsukuba-shi, Ibaraki-ken 305-0801, Japanc
Solid-State Division, Hamamatsu Photonics K.K., 1126-1 Ichino-cho, Higashi-ku, Hamamatsu-shi, Shizuoka 435-8558, Japand
Department of Education, Kyoto University of Education, 1 Fukakusa-Fujimori-cho, Fushimi-ku, Kyoto 612-8522, Japane
Department of Physics, Okayama University, 3-1-1 Tshushima-naka, Kita-ku, Okayama-shi, Okayama 700-8530, Japanf
Department of Physics, Osaka University, Machikaneyama-cho, Toyonaka-shi, Osaka 560-0043, Japang
Institut Universitaire de Technologie d’Orsay, Universite de Paris Sud, plateau de Moulon, 91400 Orsay, Franceh
The Graduate University for Advanced Studies (SOKENDAI), 1-1 Oho, Tsukuba-shi, Ibaraki-ken 305-0801, Japani
Department of Physics, Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550, Japanj
Institute of Pure and Applied Sciences, University of Tsukuba, 1-1-1 Tennoudai, Tsukuba-shi, Ibaraki 305-8571, JapankResearch Institute for Science and Engineering, Waseda University, 1-6-1 Nishi-Waseda, Shinjuku-ku, Tokyo 169-8050, Japanba r t i c l e i n f o

a b s t r a c t

Available online 17 May 2012

We have been developing highly radiation-tolerant n þ -in-p planar pixel sensors for use in the highluminosity LHC. Novel n þ -in-p structures were made using various combinations of the bias structures(punch-through or polysilicon resistor), isolation structures (p-stop or p-spray), and thicknesses(320 mm or 150 mm). The 1-chip pixel modules with thin FE-I4 pixel sensors were evaluated using
test beams, before and after 2  1015 neq =cm2 irradiation. The full depletion voltages were estimated to
be 44 7 10 V and 380 7 70 V, in the non-irradiated and the irradiated modules, respectively. A reductionof efﬁciency was observed in the vicinity of the four pixel corners and underneath the bias rail after theirradiation. The global efﬁciencies were 4 99% and 4 95% in the non-irradiated and the irradiatedmodules, respectively. The collected charges were uniform in the depth direction at bias voltages well
above the full depletion voltages. The encapsulation of vulnerable edges with adhesive or parylene
prevented HV sparking. Bump bonding with the SnAg solder bumps was performed at HPKwith 150 mm- and 320 mm-thick sensors and chips. No disconnection of bumps was observed after
10 thermal cycles between  40 and þ50 1C, with a temperature slew rate of 4 70 K=min.
& 2012 Elsevier B.V. All rights reserved.

Keywords:
Silicon sensor
Pixel
n-in-pp-typeRadiation hardness
LHC
HV protection
Encapsulation
Bump bonding
Thermal cycling

1. Introduction
Hybrid pixel detectors in which the sensor and read-out chipare separate entities and connected with bump bonding havebeen used in many applications [1,2]. We have been developing
so-called n þ -in-p pixel sensors that are highly radiation-tolerant,
have a ‘‘planar’’ electrode geometry, utilize p-type silicon wafers,
and are read-out from highly doped n þ implants, as shown in
Fig. 1 [3]. We propose their use in, e.g., the high-luminosity large
hadron collider (HL-LHC) where the particle ﬂuence is expected to
be in the range of 1015 to a few 1016 1-MeV-neutron-equivalentðneq Þ=cm2 .

nCorresponding author.
E-mail address: yoshinobu.unno@kek.jp (Y. Unno).

0168-9002/$ - see front matter & 2012 Elsevier B.V. All rights reserved.
http://dx.doi.org/10.1016/j.nima.2012.04.061

The n þ -in-p silicon sensors have the following properties:
the p-type silicon wafer does not change type after irradiation(no type-inversion); read-out is from the junction side (n þ ) in allcases; and the collected carrier is the electron. These properties
lead to a number of beneﬁts: the lithographic processes are only
required on a single side, which lead to lower production costs;
partially depleted operation is allowed, which is crucial after
heavy irradiation in which the full-depletion voltage becomes
higher than the operation voltage; and stronger and faster signals
are induced by the carrier in the higher electric ﬁeld in thejunction side, thus leading to less charge-trapping. We havepreviously reported the successful development and characterization of n þ -in-p silicon ‘‘strip’’ sensors [4–7].
A typical n þ -in-p planar pixel module is shown in Fig. 1. For
the pixel sensors, the critical issues include operation at very highvoltage, implementation of isolation and bias structures, andY. Unno et al. / Nuclear Instruments and Methods in Physics Research A 699 (2013) 72–77

73

Fig. 1. Typical cross-section of an n þ -in-p hybrid pixel module.

reduction of material. For the pixel modules the critical issues
include prevention of high voltage sparking and the need to bumpbond with lead-free bumps. The R&D issues addressed in thispaper cover the following areas:
1. The pixel sensor is required to be operated up to 1000 V, tocope with the increasing full-depletion voltage caused byradiation damage.
2. An isolation structure is required to isolate the n þ pixels frombeing connected by the conductive layer of attracted electrons
in the surface of silicon, caused by the built-in and radiationinduced positive charge-up in the interface of the silicon andthe surface oxide. The isolation structure has to be robust, i.e.
not to introduce breakdown in leakage current, against thehigh electric ﬁeld caused by the high voltage operation.
3. A bias structure is required to provide a high voltage to all
pixels for testing without connecting the pixels to the read-out
chip. The insensitive area caused by the structures must be
minimized.
4. The sensors must be made as thin as possible in order to becompatible with the performance requirements for detectors
which are placed close to the interaction point. Thinningtechniques must be developed.
5. The high voltage (HV) (edge of the sensor) and the ground(GND) (read-out chip) can, in the case of n þ -in-p devices, be as
close as 20230 mm. Techniques must be developed to prevent
sparking between the HV and any GND point up to 1000 V.
6. Usage of lead-free Tin–Silver (SnAg) solder bumps has became
the industry standard. We must demonstrate the quality andyield of the SnAg bump bonding to our application.

2. Novel n þ -in-p pixel sensors
A number of n þ -in-p pixel sensors were laid out on a 6-in.
wafer [3], which was processed by Hamamatsu Photonics(HPK) [8]. A picture of the wafer is shown in Fig. 2. The pixel
sensor, mated with the ATLAS FE-I3 [2] or the FE-I4 [9] pixel readout chip, is called ‘‘FE-I3’’ or ‘‘FE-I4 pixel sensor’’, respectively. The
layout was made up of 1-chip and 4-chip tiles of the FE-I3 and1-chip and 2-chip tiles of the FE-I4 pixel sensors as indicated in
the ﬁgure. The typical parameters of the n þ -in-p KEK/HPK pixel
sensors are summarized in Table 1.
The designs of the pixel structure in the vicinity of bias
structure are shown in Fig. 3. Two types of resistive structure

Fig. 2. Layout of pixel sensors on 6 in. wafer.

Table 1
Typical parameters of KEK/HPK n þ -in-p pixel sensors.
Silicon wafer
Crystal orientation
Resistivity
Thickness

6 in. p-type FZ/100S
427 kO cm
320 mm

FE-I4 pixel sensor
Pixel size
Bias structure
Dimension
Number of pixels

1-chip2-chip50  250 mm2
PTLA (four pixel corner)
PolySi (  2:7 MO)
18.7  20.9
18.7  41.3 mm2
336  80¼ 26 880
336  160¼ 53 760

FE-I3 pixel sensor
Pixel size
Bias structure
Dimension
Number of pixels

1-chip50  400 mm2
PolySi (  1 MO)
10.5  10.0
164  18¼ 2952

Isolation (density)

p-stop (  4  1012 ions=cm2 )4-chip18.7  17.2 mm2328  36¼ 11 808

p-spray (  2  1012 ions=cm2 )Thickness after thinning

150 mmwere formed from the bias rail: (1) a punch-through structurewith an implant dot at the four pixel corners, called ‘‘PTLA’’(Fig. 3(a)–(c)) and (2) a long trace of polysilicon resistor, ‘‘PolySi’’(Fig. 3(d)–(f)). The PTLA dots were placed at all four pixel corners
by mistake, whereas it had been intended to place them only atalternate four pixel corners. The three isolation structure conditions were (1) common p-stop (Fig. 3(a) and (d)), (2) individual
p-stop (Fig. 3(b) and (e)), and (3) p-spray (Fig. 3(c) and (f)). The
p-stop structure uses a lightly doped p-implantation in a masked
area. The p-spray method, at HPK, uses a wafer with a lightly
doped p-implantation over the full surface. The bias rail is a metal
trace placed over the insulator with no implantation in the silicon
underneath.
The potential to the bias rail was provided from the bias ring at
the edge of the sensor. The bias ring was surrounded by one guardring, ﬂoating in potential. The sensors were diced at 450 mm fromthe end of pixel implants in the long pixel direction. In the short

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Y. Unno et al. / Nuclear Instruments and Methods in Physics Research A 699 (2013) 72–77

3. Evaluation of 1-chip modules before and after irradiation

Fig. 3. Pixel structures in the vicinity of bias structures: punch-through type
(PTLA: (a)–(c)) and polysilicon type (PolySi: (d)–(f)), combined with the isolation
structures of common p-stop ((a), (d)), individual p-stop ((b), (e)), and p-spray((c), (f)).

Fig. 4. Leakage currents of thin pixel sensors with p-stop isolation in wafers.

pixel direction, at 1175 mm as the requirement for narrowness
was modest in this direction.
Thin pixel sensors (150 mm in thickness) were fabricated,aiming for reducing the amount of material. The thin sensors
were made in two steps: completing the n þ pixel side in thenormal wafers of 320 mm in thickness, then thinning and completing the back-side. The leakage currents of the thin pixel
sensors are shown in Fig. 4, as measured in the wafers, before
dicing. There were 21 FE-I3 1-chip, 9 FE-I3 4-chip, 18 FE-I4 1-chip,and 18 FE-I4 2-chip pixel sensors. No sudden increase of leakage
current was observed up to 1000 V. There were four groups ofthe leakage currents:  40 nA for FE-I3 1-chip,  150 nA for FE-I3
4-chip,  200 nA for FE-I4 1-chip, and  400 nA for FE-I4 2-chip
pixel sensors, at a bias voltage of 1000 V. The linearity of theleakage currents as a function of sensor area was an indication of
the correct functionality of the PTLA and the PolySi bias structures. The p-spray sensors showed lower breakdown voltages atapproximately 900 V.
Out of four thinned wafers containing the pixel sensors, four of
the thin FE-I4 1-chip pixel sensors were diced and bump bonded,
at IZM [10]. The four pixel sensors after bump bonding still had nobreakdown in the leakage current up to 1000 V. The properties of
the thin FE-I4 1-chip pixel modules are summarized in Table 2.

We evaluated the FE-I4 1-chip modules in two beam tests at
CERN, using 120 GeV p þ particles [11], and in the laboratory,
using a 90Sr b-source. The modules that had not been irradiated(non-irradiated (NR)) were tested in the ﬁrst beam test. The
modules (KEK3, KEK5, KEK6) were then irradiated using 23 MeV
protons at Karlsruhe [12] to a ﬂuence of 2  1015 neq =cm2 . The
second beam test was performed with non-irradiated KEK4 andthe irradiated modules (irradiated (IR)). The results are presented
in detail in Ref. [13].
The signal pulse height distributions as a function of the bias
voltage of the FE-I4 1-chip modules (KEK4 and KEK5) are shownin Fig. 5. The pulse heights, measured with the time-overthreshold (TOT), included non-linearity of the ampliﬁers. The
pulse heights were then normalized to unity, for NR modules at
150 V and for IR modules at 1000 V, respectively. The normalized
pulse heights were well aligned with each other, including thelaboratory measurements (lab) using a b-source. The full-depletion voltage was approximately 50 V and 400 V in the NR and IR
modules, respectively. The charge collection was still efﬁcient atpartial-depletion voltages. The pulse heights in the IR modules
increased gradually by 10% when going from 400 V to 1000 V,
which implied smallness of the inﬂuence of, e.g., the charge
multiplication [14].
The collected charge is known to increase in proportion to thesquare-root of the applied voltage, at least in the non-irradiatedsilicon crystals [15]. The full
depletion voltages
were estimated bypﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ
ﬃ
ﬁtting a function, f ðxÞ ¼ ðxaÞ=ðbaÞ, where a represents any
offset effects and b represents the full depletion voltage at which
the function reached unity at x¼b. Fits were made to two cases for
the NR modules: 15 V to 25 V and 15 V to 50 V; three cases in the IR
modules: 50 V to 200 V, 50 V to 300 V, and 50 V to 400 V. The
average and the standard deviation of the full depletion voltage, VFD,
were 44710 V and 380770 V, in the NR and IR modules, respectively. The solid curves in Fig. 5 show the ﬁt functions with the full
depletion voltage reference and the unity. The effective doping
concentration, Neff, is related to the full depletion voltage, VFD as
Neff ¼ 2EðV FD þ V bi Þ=eW 2 , where E is the dielectric constant of silicon,
 1.05 pF/cm, e is the electronic charge, 1:6  1019 C, Vbi is thebuilt-in voltage,  0:5 V, and W is the thickness of the silicon,
150 mm in these sensors. The Neff’s were, then, derived to beð2:6 70:6Þ  1012 and ð2:2 7 0:4Þ  1013 cm3 , before and after theirradiation, respectively.
The effect of the bias and the isolation structures is shown in
Fig. 6; the local efﬁciency maps where the pixels in a chip were
folded into a pixel (at the center and parts of the adjacent pixels).
The NR module ((a) KEK4, PolySi-common p-stop, at 200 V) was
highly efﬁcient. Irradiation decreased the efﬁciencies of the IR
modules ((b) KEK5, PolySi-common p-stop, (c) KEK6, PTLA-individual p-stop, both at 1000 V), at the four pixel corners ((125, 25),
(125, 75), (275, 25) and (275, 75)), an effect which was much
more noticeable under the bias rail and at the PTLA dot, than for
the NR module. The PTLA-individual p-stop module was less
efﬁcient than the PolySi-common p-stop module, although some
efﬁciency can be recovered by correct design of the alternate PTLA
structure. The global efﬁciencies are summarized in Table 2 forthe modules in the ﬁrst and the second beam test.
The pulse height distribution, Q (TOT), in the depth direction isshown in Fig. 7. This data was collected using shallow angle incident
beams at 41. The pulse heights in the ﬁrst and the last bin were lessbecause the particles passed the pixels partially depending on theentrance or exit location. In other cases, the pulse heights were
essentially uniform over depth both in the NR (at 200 V) and IR(at 1000 V) modules, which implies that the inﬂuence of charge
trapping was small along the drift path from the back-side to the

Y. Unno et al. / Nuclear Instruments and Methods in Physics Research A 699 (2013) 72–77

75

Table 2
Properties of FE-I4 1-chip pixel modules.
ID

SCC no.

Bias st.

Isolation st.

Eff. 1st

Eff. 2nd

KEK3
KEK4
KEK5
KEK6

SCC93
SCC94
SCC95
SCC96

PolySiPolySiPolySiPTLA

Individual p-stop
Common p-stop
Common p-stop
Individual p-stop

99.7 70.02% (NR)98.7 70.17% (NR)99.7 70.02% (NR)94.2 70.04% (NR)N/A
99.87 0.02% (NR)95.67 0.15% (IR)94.97 0.14% (IR)SCC, single chip card; st., structure; eff., efﬁciency; N/A, not available; NR, non-irradiated; IR, irradiated to 2  1015 neq =cm2 .

14n+ sideKEK4-NR 200V

12
KEK5-IR 1000V

Q (TOT)10

backside

8
6
4
2
0
0

0.02 0.04 0.06 0.08 0.1
Depth (mm)0.12 0.14 0.16

Fig. 7. Pulse height distribution in the depth direction, using shallow incidentangle beam.
Fig. 5. Normalized pulse height distributions as a function of the bias voltage of
FE-I4 1-chip modules (KEK4 and KEK5). The pulse heights of non-irradiated andirradiated (2  1015 neq =cm2 ) cases are normalized to unity at 150 V and at
1000 V, respectively. Solid curves are ﬁt functions with the full depletion voltagesof 44 V and 380 V for the NR and IR modules, and the unity pulse height reference.

Fig. 8. HV protection test: (a) pixel module with FE-I3 real pixel sensor andaluminum-trace dummy read-out chip, (b) HV spark mark at cross-corner of edges
at 500 V, and (c) HV spark mark on aluminum trace that occurred at 690 V. The
gap between sensor and chip was 20230 mm.

Fig. 6. Local efﬁciency map of a pixel: (a) non-irradiated PolySi-common p-stop(KEK4) and irradiated (2  1015 neq =cm2 ), (b) PolySi-common p-stop (KEK5) and(c) PTLA-individual p-stop (KEK6) for FE-I4 1-chip modules.

(charge-collecting) n þ side. The observation was consistent with the
charge trapping distance for the ﬂuence of 2  1015 neq =cm2 of orderof 150 mm [13].

4. Prevention of high-voltage sparking using post-processapplication
4.1. Encapsulation
The HV-protection test samples were made of real FE-I3 pixel
sensors and dummy read-out chips that had been bump bonded. A
sample in which the top chip is the pixel sensor is shown in Fig. 8(a).
The dummy chips were made with aluminum patterns to make adaisy-chain connection. The aluminum patterns were passivated withsilicon oxide of  1 mm in thickness, except for the bump bonding
pads and the probing pads at the end of the traces. The gap between
the chips was 20230 mm. Three areas were of interest: the two crosscorner of the pixel sensor and the read-out chip, and the one sideedge facing the aluminum traces. Three types of encapsulation wereapplied with a silicone adhesive: encapsulating (1) no area (sample#1), the cross-corners (sample #2), and both the cross-corners andthe full length of the facing edge (sample #3). When applying highvoltage to the back-side of the pixel sensor and keeping the pixels on
the front side and the read-out chip grounded, sparks occurred at
500 V at the cross-corners of sample #1, Fig. 8(b), and at 690 V at thealuminum trace facing the edge in sample #2, Fig. 8(c). No spark was
observed up to 1000 V for the fully encapsulated sample (#3).
The HV protection of the FE-I4 1-chip pixel modules in Section 3
was applied over the full length with a silicone adhesive, as shownin Fig. 9. All non-irradiated and irradiated modules operated
successfully up to 1000 V both in the laboratory and in the beam
tests.

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Y. Unno et al. / Nuclear Instruments and Methods in Physics Research A 699 (2013) 72–77

under-bump-metallization (UBM) at HPK and FE-I3 read-out chips
applied with electro-plating UBM and lead–tin (PbSn) solder
bumps at IZM.
Because industrial bump bonding has begun shifting towards
lead-free materials, we performed tin–silver (SnAg) solder bumpbonding with the FE-I3 and the FE-I4 dummy sensors and thedummy read-out chips with daisy-chain patterns. The FE-I4
1-chip and the 4-chip bump-bonded modules are shown in
Fig. 11, (left) 1-chip with 150 mm-thick chips and (right) 4-chipwith 320 mm-thick chips. The UBM of one side was electroless andthe other side of the SnAg bumps was electroplated. We havepreviously reported a high resistance per (SnAg) bump, likely
because of the (possible) existence of a thin insulating layer [3].
The issue has been resolved by including a plasma-etchingprocess. The resistances of the daisy chains of the new FE-I4
1-chip dummy module are shown in Fig. 12. The resistance perbump was  0:28 O, comparable to the resistance of PbSn of 0:14 O reported in Ref. [3].
Fig. 9. HV encapsulation of FE-I4 module for use with test beam.

5.2. Thermal cycling
25

The pixel modules are to be cooled to, e.g.,  40 1C to reduce
the leakage current after heavy irradiation. Thermo-mechanicalresistance to the thermal cycling is an issue in bump-bonded
modules. To achieve a high cool-down/warm-up slew rate, asimple setup consisting of climate chambers was prepared: one
chamber with a low ( 40 1C) and the other with a high ( þ50 1C)
temperature; each condition included a large aluminum block
placed inside the chamber to act as a heat capacitor. Six FE-I4
1-chip dummy modules were subjected to 10 thermal cycles. The
samples were placed in an aluminum box. The aluminum box was

Leakage Current [μA]

20

15

10
KEK2
KEK1

5

0
0

200

400

600

800

1000

Bias voltage [V]Fig. 10. Leakage current as a function of the bias voltage of FE-I3 module after
Parylene-C (  3 mm) coating.

4.2. Parylene coating

Fig. 11. FE-I4 1-chip and 4-chip dummy modules.

300

10000
0.28Ω/BumpUnit

260

7000

240

6000

220

5000

200
180

4000
Resistance
Loop resistance3000

5. Bump-bonding at HPK
5.1. SnAg bump-bonding

280

8000

2000

140

1000

120

0

We have been developing bump-bonding technology at
HPK. The FE-I3 1-chip pixel modules in Section 4.2 were bumpbonded at HPK, using the pixel sensors applied with electroless

160

0

5000

10000

15000

20000

25000

Loop resistance (Ω)

9000

Resistance (Ω)

Two FE-I3 1-chip pixel modules, KEK1 and KEK2, wereassembled on FE-I3 single chip cards (SCCs) [3]. The vicinities ofthe pixel modules in the SCC’s were conformally coated with
Parylene-C of  3 mm in thickness [16], for which the breakdown
voltage is expected to be 41000 V [17]. These Parylene-coated
SCC’s were irradiated using 70 MeV protons to 1:1  1015 neq =cm2
[18]; no damage to the parylene was observed. The leakage
currents as a function of the bias voltage are shown in Fig. 10;
the breakdown was observed at approximately 700 V, which wasconsistent with the known breakdown voltage of the card. These
FE-I3 1-chip modules were in the test beams at CERN in 2010 and2011 [11]. In retrospect, the softer Parylene-N might be better
suited for our application than the harder Parylene-C, as the
Parylene-N produces a highly conformal thin coating.

100
30000

Number of bumps
Fig. 12. Resistances of SnAg solder bumps of FE-I4 1-chip dummy module.

Y. Unno et al. / Nuclear Instruments and Methods in Physics Research A 699 (2013) 72–77

placed on the aluminum block for 30 min in one climate chamber,and then transferred by hand to the other for another 30 min, tomake one thermal cycle. A platinum resistor (PT100) was attached
to a piece of silicon and placed in the box to measure thetemperature. The temperature slew rate upward was 108.2 K/min
for the ﬁrst 30 s and 73.4 K/min in 1 min. The rate downward was
115.4 K/min in the ﬁrst 30 s and  71.6 K/min in 1 min. With one
climate chamber to cool down or warm up, the temperature slew
rate was approximately 3–5 K/min.
After 10 thermal cycles between  40 1C and þ50 1C, none of
the six samples had developed any disconnection. The average
resistance of a daisy chain though full bumps was 5083 7 1374 O
and 5110 71370 O, and the difference in resistance was
27 7 31 O, before and after the thermal cycling, respectively.
6. Summary
We have been developing highly radiation-tolerant n þ -in-pplanar pixel sensors for the ﬂuence of 1015 to a few
1016 neq =cm2 expected in the HL-LHC, and we have addressed
the issues associated with the n þ -in-p hybrid pixel modules.
Novel n þ -in-p pixel sensors were fabricated with a bias structureof the punch-through dot at the four pixel corners or of thepolysilicon resistor, combined with an isolation structure ofcommon or individual p-stop, or p-spray. The pixel sensors of
150 mm in thickness were fabricated by thinning the back side of
the wafers of 320 mm in thickness, after completing the frontside
process. Little leakage current breakdown was observed up to abias voltage of 1000 V.
The thin FE-I4 1-chip pixel sensors, bump bonded with FE-I4
read-out chips, were evaluated both in test beams and in thelaboratory, both before and after 2  1015 neq =cm2 irradiation. The
full depletion voltage was estimated (from the charge collectiondata) to be 44710 V and 380770 V, and then the effective doping
concentration to be ð2:6 7 0:6Þ  1012 and ð2:2 70:4Þ  1013 cm3 , inthe non-irradiated and the irradiated sensor, respectively.
The effect of the bias and the isolation structures was comparedbased on the local efﬁciency map of a pixel. A reduction of efﬁciency
was observed in the vicinity of four pixel corners and especially
underneath the bias rail, after the irradiation. Efﬁciency in average
was 4 99% and 495% in the non-irradiated and irradiatedmodules, respectively. The charge collection in the depth direction
was studied by using the shallow angle incident beams at 41. The
collected charges were uniform in the depth direction at bias
voltages well above the full depletion voltages, and consistent withthe charge trapping distance of order of 150 mm for the ﬂuence of2  1015 neq =cm2 .
HV sparking was conﬁrmed with the dummy modules made up
of real pixel sensors and dummy read-out chips. Sparking occurred
at 500 V at the cross-corners of edges, and at 690 V at the trace on77

the chip and sensor edge. Prevention of HV sparking was achieved
either by encapsulating the vulnerable edges in a silicone adhesive
or by applying Parylene coating. The FE-I4 1-chip pixel modules
encapsulated with a silicone adhesive operated successfully up to
1000 V in test beams and the laboratory.
Bump bonding with SnAg solder bumps was performed at
HPK, with dummy FE-I4 sensors and chips of 150 mm and 320 mm
in thickness. Six dummy modules were subjected to 10 thermal
cycles between  40 and þ50 1C, with temperature slew rates of
4 70 K=min. No disconnection of bumps was observed.

Acknowledgments
This research was partially supported by a Grant-in-Aid forscientiﬁc research (A) (Grant No. 20244038) from the Japan
Society for the Promotion of Science and a Grant-in-Aid forscientiﬁc research on advanced basic research (Grant No.
23104002) from the Ministry of Education, Culture, Sports,
Science and Technology, of Japan.
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