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Nuclear Instruments and Methods in Physics Research A 518 (2004) 270–276

The CDF Run IIb silicon detector
M. Aokia, N. Bacchettab,c, S. Beharid, D. Benjamine, D. Biselloc, G. Bollaf,
D. Bortolettof, A. Burghardg, G. Busettoc, S. Cabrerae, A. Canepaf, A. Castroh,
G. Cardosob, M. Chertoki, C. Ciobanuj, G. Derylob, I. Fangb, B. Flaugherb,*,
J. Freemank, L. Galtierik, J. Galyardtl, M. Garcia-Sciveresk, G. Giurgiul,
I. Gorelovg, C. Haberk, K. Haraa, M. Hoeferkampg, B. Holbrooki, M. Hrycykb,
T. Junki, S. Kima,1, K. Kobayashim, B. Kriegerk, M. Krusee, R. Landeri, R.-S. Lun,
P. Lukensb, L. Malferrarih, C. Maneac, A. Margottih, P. Maksimovicd, P. Merkelb,
S. Mocciab, I. Nakanom, D. Naoumovg, J. Novakf, T. Okusawao, Y. Orlovb,
G. Pancaldih, D. Pantanoc, V. Pavlicekb, D. Pelletti, S. Seidelg, F. Semeriah,
Y. Takeia, R. Tanakam, Z. Wangc, P. Watjeg, M. Weberk, W. Westerb, T. Wilkesi,
K. Yamamotoo, W. Yaok, W. Yaoi, S. Zimmermannb, S. Zucchellib, A. ZucchinihaUniversity of Tsukuba, Tsukuba, Ibaraki 305-8571, Japanb
Fermilab, Batavia, IL 60510, USA2c
Universita" di Padova and INFN, Padova, ItalydJohns Hopkins University, Baltimore, MD 21218, USAe
Duke University, Durham, NC 27708, USAf
Physics Department, 1396 Physics Building, Purdue University, West Lafayette, IN 47907, USAg
University of New Mexico, Albuquerque, NM 87131, USAhUniversita" di Bologna and INFN, Bologna, Italyi
University of California, Davis, CA 95616, USAj
University of Illinois at Urbana-Champaign, Urbana, IL 61801 USAk
Lawrence Berkeley Laboratory, Berkeley, CA 94720, USAlCarnegie Mellon University, Pittsburgh, PA 15213, USAm
Okayama University, Okayama 700-8530, JapannAcademia Sinica, Taipei, Taiwan 11529, Republic of ChinaoOsaka city University, Osaka 558-8585, Japan

Abstract
Fermilab plans to deliver 5–15 fb1 of integrated luminosity to the CDF and D0 experiments. The current innersilicon detectors at CDF (SVXIIa and L00) will not tolerate the radiation dose associated with high-luminosity runningand will need to be replaced. A new readout chip (SVX4) has been designed in radiation-hard 0.25 mm, CMOS

*Corresponding author. Tel.: +1-630-840-2934; fax: +1-630-840-6776.
E-mail address: brenna@fnal.gov (B. Flaugher).
1
Supported by Grant in Aid for Scientiﬁc Research (KAK-ENIII) on Priority Areas, 13047101.
2
Operated by Universities Research Association Inc. under Contract No. DE-AC02-76CH 03000 with the United States Departmentof Energy.
0168-9002/$ - see front matter r 2003 Elsevier B.V. All rights reserved.
doi:10.1016/j.nima.2003.10.080

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271

technology. Single-sided sensors are arranged in a compact structure, called a stave, with integrated readout andcooling systems. This paper describes the general design of the Run IIb system, testing results of prototype electricalcomponents (staves), and prototype silicon sensor performance before and after irradiation.
r 2003 Elsevier B.V. All rights reserved.
PACS: 29.40.Gx; 29.40.Wk; 29.90.+r
Keywords: CDF; Run IIb; Silicon vertex detector; SVX4; Silicon sensors; Fermilab; Tevatron

1. Introduction
Until the turn-on of LHC, the Fermilab
Tevatron will continue to be the highest energy
accelerator in the world. To exploit the discovery
potential of the Tevatron, Fermilab is planningon extensive collider running, which will deliver
5–15 fb1 of integrated luminosity. The Run IIa
inner silicon detectors (L00 and SVXIIa) are
expected to suffer signiﬁcant performance degradation after roughly 4 fb1 of delivered luminosity.
For Run IIb, these detectors will be replaced by a
new silicon detector which is optimized for highluminosity running and resistance to radiation [1].
The intermediate silicon layers (ISL) will be
retained for Run IIb.
The physics goals of Run IIb are broad andfundamental. Not only is the Tevatron the only
place to search for a light Higgs boson until the
LHC era begins, but it is also currently the only
source of top quarks. Precise measurements of the
top quark and W masses will be possible. Studies
of B physics can provide constraints on the CKM
matrix and many searches for SUSY, SUSY Higgs
and extra dimensions can be performed. Crucial
for most of these physics goals is the ability to tag
the presence of B hadrons efﬁciently and with highpurity. Fig. 1 shows one example where thestandard model Higgs mass sensitivity is plotted
as a function of b-tagging efﬁciency.
Both the Run IIa and Run IIb detectors have six
layers where the outer ﬁve layers (L1-5) eachprovide two measurement points, typically anaxial and a stereo measurement. Both detectors
have layers arranged in a castellated patternaround the beam line to provide 100% axial
coverage. Fig. 2 shows an end view of the Run IIb
silicon detector.

The basic building block of the Run IIb detector
is called a ‘‘stave’’. Based on the experience ofconstructing previous generations of silicon trackers at CDF, a uniform design has been chosen for
all the outer layers which emphasizes simplicity ofdesign and assembly. Only the innermost layer,
L0, will have a different structure. L0 will have a
low mass design (similar to the Run IIa L00)
providing a good impact parameter resolution.
The component counts and diversity of ﬁxturesand procedures required have been dramaticallyreduced. While the CDF Run IIa tracker had eight
different ‘‘ladder’’ types and 13 different hybrid
designs, the Run IIb stave based design will only
require one hybrid type for the stave and one forLayer 0.
The Run IIb silicon detector design improves
over the Run IIa detector in a number of areas. To

Fig. 1. Higgs mass reach for a 5s discovery as a function of theb-tag efﬁciency relative to a nominal value of 65% for an
integrated luminosity of 15 fb1 per experiment.

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Fig. 2. End view of the Run IIb silicon detector design.

improve the radiation hardness a new readout chip
(SVX4) has been developed in 0.25 mm CMOS
technology. The sensors for Run IIb are singlesided and will be actively cooled to temperaturesof 5 C. The Run IIb detector has a longer
tracking volume (1.2 m compared to 0.9 m) andwill therefore provide a larger acceptance fortagging jets with B hadrons. The Run IIb detector
design has also expanded in radial coverage(16.6 cm compared to 10.6 cm) and the portcard
electronic components (providing regulation andinterfacing) have been relocated outside the tracking volume. This will provide a better connection
for tracking between the new SVXIIb detector andthe ISL layers. The inner layers of the Run IIb
detector are also strengthened compared to Run
IIa with redundant axial sensors at Layer 1.
Prototype staves have been constructed andextensively tested. The results are discussed below
followed by a summary of the performance of the
prototype silicon sensors.

low-temperature operation, with embedded cooling channels, minimum mass, and dead-timelessreadout and acquisition. Carbon ﬁber (CF) andfoam composites are used for light, rigid structures, and aggressive ﬁne-pitch electrical interconnects are used to minimize the areas of support
circuitry. The requirement of dead-timeless operation means that the SVX4 chips store signals on
the front end analog pipeline capacitors at thesame time as prior events are digitized or read out.
Stave electrical performance must accommodate
this.
Each stave is built around a thermal mechanicalcore. The core consists of Rohacell foam withembedded PEEK cooling tubes. CF skins arelaminated on each side providing mechanicalrigidity. The CF layers are connected to theelectrical ground of the analog circuitry.
A stave consists of six independent silicon strip
modules, three on each side. Each module iscomposed of two silicon sensors, wirebonded
together and read out by an on-board hybrid
circuit holding four SVX4 chips for a total of 512
channels. The overall length of a module is 20 cm.
The average radiation length of a stave is 1.8%
and is dominated by silicon.
A bus cable carrying data and control signals
runs on each side of the stave core, underneath thesensors. The modules are bonded to the bus cablethrough 3 mm gaps between the modules. At theend of each stave a kapton ﬂex cable and a miniportcard (MPC) provide the connections between
the top and bottom of the stave and retransmission of the signals to the external electronics racks.
The total length of the stave is 66 cm (3 modules

2. Stave design and testing results
To meet the needs of the Run IIb tracking
environment, the Run IIb stave design features

Fig. 3. Run IIb stave layout.

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Fig. 4. Detailed view of one-half of the end of the stave
showing mechanical and cooling features.

plus the MPC). Fig. 3 shows a detailed sketch of astave and its components. Fig. 4 shows an end
view, detailing the different layers.
Axial or stereo sensors can be used on either sideof the staves. The strip pitch is 75 mm for axial and
80 mm for stereo sensors. To optimize the strengthof the inner tracking, Layer 1 will have axial
sensors on both sides. Layers 2–4 will have smallangle stereo sensors (1.2 ) on one side and axial
sensors on the other. Layer 5 will have axial
sensors on both sides for a good connection to theouter tracking systems. All outer layer staves use
identical 4-chip hybrids. L0 uses a 2-chip hybrid
which follows the design of the outer layer hybrid.
This uniformity greatly simpliﬁes the assembly andconstruction.
Both thermal and mechanical properties of the
staves have been simulated and measured. Maximal sag due to gravity is 130 mm, within thespeciﬁcations for the tracker. The innermost
silicon detectors need to operate at 5 C. Thermal
studies have shown that the temperature rise in asingle stave is p2 C for the allowed pressure
drops, ﬂow rates and the full heat load. The system
is designed to run with an entrance temperature of
15 C for the coolant. Staves will be ganged
together to meet the required temperature speciﬁcations while minimizing the associated plumbing.
Layer 1 will feed the individual staves. On theouter layers three staves will be ganged together.
The bus cable is a ﬂexible etched laminate ofkapton, copper, and aluminum foil. It is insulated
from the high-voltage back plane of silicon sensors273

by a thin Kapton cover layer. The bus cable carries
wide power traces and narrow (200 mm pitch)traces for clocks, commands, and data. High
voltage is also distributed on the bus cable. Bondpads (for bonding to the hybrid) are located on thebus cable to correspond to the gaps between themodules. Bonds are made to expose gold-plated
sections of the bus lines. All hybrids on a bus sharethe data and command lines. Separate clock,power and HV lines serve each hybrid. The
readout token (priority line) is also passed between
hybrids on the bus.
Both the hybrids and the MPC are fabricated ina thick ﬁlm process with gold conductors on aberyllia substrate. Beryllia is used both for its highthermal conductivity and long radiation length.
The line work on the hybrids and MPC isaggressive, featuring 100 mm lines and spaces. Thisis achieved with a unique etchable thick ﬁlm
conductor technology. The ﬁne line work allows
for a minimum package size for the hybrid and
MPC, reducing the material burden considerably.
A critical aspect of the stave design is the noise
performance. Since the digital lines on the stave
run directly beneath the detector HV backplane, asigniﬁcant potential for performance degradation
exists. These issues have been addressed through a
program of study on various mock-ups andprototypes. It was demonstrated that a shieldlayer, connected to the analog ground is required.
With the shield, pickup effects are negligible except
for certain short periods when particular command sequences are sent to the SVX4 chips. These
sequences are associated with changes in theoperating mode of the SVX4 chip. During thesetransitions the total current supply to the digitalpart of the SVX4 chip may change resulting in
induced signals on the bus cable shield. The
magnitude of the induced effect, as seen on thepedestal of the SVX4 chip, can be regulated by anumber of factors. These include the position of
the current settings on various drivers, bandwidth
settings of the SVX4 pre-amp, bypassing, andinter-line capacitances within the bus cable. The
studies to date indicate a close-to-acceptableperformance in a dead-timeless mode of operation.
Beyond these effects, the SVX4 chip includes areal-time event-by-event pedestal subtractionARTICLE IN PRESS
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M. Aoki et al. / Nuclear Instruments and Methods in Physics Research A 518 (2004) 270–276

feature (RTPS) which can generally compensate
for any residual pickup effects as well. To study
noise performance and dead-timeless operation in
the stave environment, a set of bench testing tools
are utilized. These include a statistical noise
measurement on an ensemble of events and a‘‘differential noise’’ measurement. In the lattercase the noise is measured by studying thedifference between the two adjacent channels
event-by-event.

Fig. 5 shows noise and ‘‘dnoise’’ for all thechannels on a stave. The strips are bonded to 1 or
2 sensors or are unbonded. The near equality ofnoise and dnoise indicates that little pickup waspresent. Fig. 6 shows a measure of the pedestal ofa particular channel as a function of the number ofclock cycles between the triggered event and thepreviously triggered event. In this plot the SVX4
chip is sequenced through all its different modes ofoperation. The data indicate the effect upon aparticular charge sample due to other activities in
the chip, e.g. readout or digitize on an earlier
event. A pedestal shift of signiﬁcant magnitude, ascompared to a minimum ionizing particle, is asource for concern. Such shifts do occur, forcertain cycles, when particular commands are insequence. The lower trace shows the effect when
RTPS is invoked. In this case the pedestal shifts
always become negligible. Current studies involve
efforts to limit the transitions further in RTPS-off
mode. To date three fully functional staves havebeen assembled and studied. A pre-production
phase of the project begins in summer 2003 inwhich of order 25 staves will be built and tested.

Fig. 5. Noise (dark) and Dnoise (light) on a stave. Channels
1–512 and 1350–1536 are unbonded, channels 513–1290 are
bonded to two sensors (full load). Channels 1050–1290 aredamaged, resulting in excess leakage current and noise.
Channels 1291–1349 are bonded to one sensor. Two-sensor
noise is about 1200 electrons.

3. Silicon sensors
The Run IIb detector will have E2300 singlesided silicon microstrip sensors. The main speciﬁcations are: (1) sensors should be operational up to

Fig. 6. Study of dead-timeless operation with RTPS off (top) and on (bottom) curves. Various operating conditions of the SVX4 chip
are indicated.

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500 V; (2) full depletion voltage should be in therange from 120 to 250 V; (3) dead channel fraction
should be less than 1%; (4) sensors should be
uniform in coupling capacitance (>12 pF/cm),
bias resistance (1.570.5 MO), interstrip resistance(o1.2 pF/cm), and other electrical properties. We
have employed single-sided p+-on-n sensors withdimensions of 96.4 mm length and 40.6 mm width
for axial and 41.1 mm width for 1.2 stereo
sensors, so that two sensors can be taken from a
600 wafer. The readout pitch is 75 (80) mm for axial(stereo) sensors. A single intermediate strip is
implemented to improve position resolution.
Prototypes of 63 axial and 53 stereo sensors
were fabricated by Hamamatsu Photonics (HPK).
We have performed detailed electrical characterization of 18 sensors for each type along with othermore general tests such as I–V and C–V characteristics. The innermost sensors will receive
radiation corresponding to 1.4  1014 1 MeV Equ.
neutrons/cm2 in 30 fb1 integrated luminosity. We
have irradiated ﬁve sensors up to this ﬂuence. The
performance results of irradiated sensors are also
reported.
3.1. Initial electrical characteristics
The I–V measurement results are summarized inFig. 7. The leakage currents are normalized to20 C. Most of the sensors do not exceed 0.2 mA

Fig. 7. Leakage current distributions of 116 prototype sensors
at 500 and 950 V. The overﬂows are histogrammed on theextreme right. The inset shows the I–V curves of all the sensors.

275

even at 950 V. Only two sensors out of 116 showed
noticeable micro-discharge.
Scanning the individual strip current for the twoleaky sensors, we found that only one strip foreach sensor is contributing to the large leakage.
The micro-discharge onset voltage shifted higher
as we repeated the I–V measurements.
HPK reported 21 defective strips in total on 14
sensors out of 116. Our full characterization for 36
sensors, including these 14 sensors, recognized all
the defects reported by HPK. In addition, we
found ﬁve implant opens and a pair of low bias
resistors. The ﬁve new implant opens were notdetected by HPK because they were not set up to
test them. The low bias resistor pair is obviously
due to a discharge, probably caused by probing.
The estimated dead channel fraction is 0.08%
including these defects.
3.2. Electrical characteristics of irradiated sensors
The irradiation took place at MNRC Irradiation Facility at UC Davis. Three sensors were
irradiated to 1.4  1014 n/cm2 and two to
0.7  1014 n/cm2.
The damage constant evaluated from ﬁve
sensors is (2–3)  1014 A/cm, consistent with thepreviously known value [2]. The I–V curves aregood to 1000 V without showing signiﬁcant microdischarge.
The full depletion voltage was evaluated when
the initial beneﬁcial annealing was almost completed. It resulted in 100 V (40–50 V) for thesensors irradiated to 1.4 (0.7)  1014 n/cm2,
whereas 90 V (40 V) is the expectation from Roseparameterization [2].
The capacitance between two neighboring readout strips is plotted in Fig. 8. The data are for thetwo sensors irradiated to 1.4  1014 n/cm2. The
curves show shoulders around 130 V corresponding to the full depletion voltages (note: these were
measured at annealing conditions different fromthe above), then decrease gradually with the bias
voltage. Although the asymptotic value is consistent with the non-irradiated sensors, an excess biasof 200–250 V is required to reach the minimum.
The interstrip resistance of >1 GO is achieved fora bias of 300 V.

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Fig. 8. Interstrip capacitance of two irradiated sensors: onepair and two pairs for each.

been ordered and the construction of preproduction staves will begin this summer. The preproduction SVX4 chips arrived on May 16, 2003 and theinitial testing results look very promising. The
preproduction hybrids are expected in July and thedelivery of production sensors will begin in June
2003. The full stave production is scheduled fromFebruary to December 2004. The barrel assembly
and the ﬁnal preparations have an anticipatedcompletion date of September 2005, with theschedule contingency extending from September
2005 to May 2006.

4. Summary

References

The Run IIb silicon project is well underway.
The prototype phase has been very successful andis nearly complete. The preproduction parts have[1] CDF collaboration, The Run IIb Technical Design Report,
CDFNOTE 6261, Jan. 2003.
[2] G. Lindstrom, et al., (Rose collaboration), Nucl Instr. andMeth. A 466 (2001) 308.