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Nuclear Instruments and Methods inPhysics Research A
journal homepage: www.elsevier.com/locate/nima

Characteristics of non-irradiated and irradiated double SOI integration
type pixel sensor
M. Asano a, D. Sekigawa a, K. Hara a,b,n, W. Aoyagi a, S. Honda a, N. Tobita a, Y. Arai c,
T. Miyoshi c, I. Kurachi c, T. Tsuboyama c, M. Yamada caInstitute of Pure and Applied Sciences, University of Tsukuba, Tsukuba, Ibaraki 305-8751, Japan
Center for Integrated Research in Fundamental Science and Engineering, University of Tsukuba, Tsukuba, Ibaraki 305-8571, Japanc
Institute of Particle and Nuclear Study, KEK, Oho 1-1, Tsukuba, Ibaraki 305-0801, Japanb

art ic l e i nf o

a b s t r a c t

Article history:
Received 18 January 2016
Received in revised form
18 March 2016
Accepted 29 March 2016

We are developing monolithic pixel sensors based on a 0.2 μm fully depleted silicon-on-insulator (FDSOI) technology for high-energy physics experiment applications. With this SOI technology, the wafer
resistivities for the electronics and sensor parts can be chosen separately. Therefore, a device with full
depletion and fast charge collection is realized. The total ionizing dose (TID) effect is the major challenge
for application in hard radiation environments. To compensate for TID damage, we introduced a double
SOI structure that implements an additional middle silicon layer (SOI2 layer). Applying a negative voltage
to the SOI2 layer should compensate for the effects induced by holes trapped in the buried oxide layers.
We studied the recovery from TID damage induced by 60Co γ and other characteristics of the integrationtype double SOI sensor INTPIXh2. When the double SOI sensor was irradiated to 100 kGy, it showed a
response to the infrared laser similar to that of a non-irradiated sensor when we applied a negative
voltage to the SOI2 layer. Thus, we concluded that the double SOI sensor is very effective at sufﬁciently
enhancing the radiation hardness for application in experiments with harsh radiation environments,
such as at Belle II or ILC.
& 2016 Elsevier B.V. All rights reserved.

Keywords:
Monolithic pixel sensor
Double silicon-on-insulator
Radiation hardness

1. Introduction
1.1. Silicon-on-insulator pixel sensor
Monolithic pixel sensors are very attractive for high-energy
physics applications for various reasons. Primarily, the metal
bump-bonding used in hybrid-type pixel sensors is eliminated;
this enhances the device reliability while reducing the production
cost. It also reduces the overall device thickness, which minimizes
the multiple scattering of the charged particles, and helps reduce
the noise level owing to smaller detector capacitances realized byminimizing the pixel size. Monolithic technology is essential torealizing pixel sensors with small pixel sizes, which is a key
requirement in future experiments for better position resolution
on the order of 1 μm.
We have been developing monolithic pixel sensors [1–3] basedon 0.2 μm fully depleted silicon-on-insulator (SOI) technology forvarious applications such as medical and material sciences [4]. The
nCorresponding author at: Institute of Pure and Applied Sciences, University ofTsukuba, Tsukuba, Ibaraki 305-8751, Japan.
E-mail address: hara@hep.px.tsukuba.ac.jp (K. Hara).

sensors are processed by Lapis Semiconductor Co., Ltd. [5] on SOI
wafers fabricated with SOITEC SmartCutTM[6] technology. The
schematics of the SOI pixel sensor are illustrated in Fig. 1. The SOI
silicon layer and handle wafer are bonded via a buried oxide (BOX)layer; thus, the resistivities can be chosen based on requirements
of individual applications. The pixel nodes are implanted via a
200-nm-thick BOX layer to the handle wafer, which acts as thesensor substrate. The ﬁgure shows additional silicon layer (middle
silicon), which is a new feature of double SOI pixel sensor described in detail in the following section.
Various types of SOI wafers have been developed for single SOI,
including both n- and p-type Czochralski (Cz) and ﬂoat-zone (FZ)
grown wafers, as sensor substrates. The sensor thickness ranges
from 50 to 500 μm. The double SOI wafer is realized with a Cz
substrate.
Complementary metal-oxide semiconductor ﬁeld-effect transistors (CMOS FETs) are constructed in the SOI silicon layer of
40 nm thickness. The FETs are interconnected by aluminum lines
in the ﬁve metal layers on top; metal–insulator–metal (MIM) capacitors are also available. The buried p-well (BPW) is a key
technology for suppressing the back-gate effect [1], where thedetector bias applied to the back affects the operation of electronic
circuitry.

http://dx.doi.org/10.1016/j.nima.2016.03.095
0168-9002/& 2016 Elsevier B.V. All rights reserved.

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Fig. 1. Schematics of monolithic double SOI pixel sensor.

1.2. Double SOI device
The operation of CMOS devices is affected by the total ionization dose (TID) effect [7], which is primarily due to the accumulation of holes in the oxide layers. SOI-CMOS devices are fully
enclosed in an insulator, which almost diminishes radiation damage such as single-event effects [8]. On the other hand, the TID
damage is enhanced in the SOI-CMOS [9], which typically limits
the operation of pixel devices up to a few kGy [10]. To use suchdevices for high-energy physics applications in hard radiation
environments, the TID effect is a major issue to overcome. To
compensate for the TID damage, we introduced an independent
electrode underneath the BOX layer; the middle silicon layer (SOI2
layer). Such a double SOI wafer is fabricated by repeating the
SOITEC SmartCutTM procedure twice. A cross-sectional image of
the ﬁrst double SOI wafer and device is shown in Fig. 2. The middle
silicon layer (p-type with 10 Ω cm resistivity) has a sheet resistance of 170 kΩ/sq with CoSi2 silicide at the contact. By applying a negative voltage ( VSOI2) to the SOI2 layer, the effects due toradiation-induced holes trapped in oxide layers are cancelled [11–13]. The SOI2 layer should also suppress the back-gate effect andcross-talk between the circuitry (e.g. clock signals) and pixel nodes
through the thin BOX layer [3].
1.3. INTPIXh2
INTPIXh2 is the ﬁrst double SOI integration type SOI pixel
sensor; it has pixels in 280 rows and 240 columns, where eachpixel is 18 μm square in size. The overall chip size is 6 mm square,
including peripheral circuitry such as for the address decoder and
IO ports. We adopted the Cz n-type substrate with a resistivity of
approximately 0.7 kΩ cm. The on-pixel circuitry is illustrated inFig. 3, and the actual layout is shown in Fig. 4. The analog signal
stored in the storage capacitor is switched out in series to thecolumn line and digitized with an external 12-bit analog-to-digitalconverter (ADC).
Some of the characteristics of the double and single SOI types
are compared. In the double type, the potential of the middle silicon layer underneath the pixels and the peripheral circuitry iscontrolled by a common VSOI2 voltage. TID damage was induced by60
Co γ at a dose of 100 kGy. The sensors were irradiated at room
temperature at a rate of 5 kGy/h with all of the terminals grounded
during irradiation. Such a conﬁguration does not represent realistic operation conditions. The effects of biasing during irradiation
are under investigation using simpliﬁed FET TEGs (test element
group) for a systematic and comprehensive understanding. Evaluation with a pixel device is to follow.

2. Leakage current
The leakage current was measured at room temperature as afunction of the bias voltage. Fig. 5 shows example I–V curves for a
100 kGy irradiated sample in comparison with its curve at preirradiation. The VSOI2 voltage was varied in the post-irradiation
measurements. The breakdown voltage of 12 samples was in a

Fig. 2. Transmission electron micrography (TEM) images of the double SOI wafer and device (courtesy of Lapis Semiconductor).

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Leakage Current [A]

10-3

0V
I2=
V
O
-11
VS

range from 300 to 400 V at pre-irradiation. The breakdown of thesample shown in the ﬁgure dropped to nearly 120 V after 100 kGy
irradiation at VSOI2  0 V (another 100 kGy irradiated sample
showed 170 V breakdown), but recovers to 200 V by applying VSOI2
as small as  1 V; applying exceeding VSOI2 = − 11 V degrades
again the breakdown voltage. The degradation observed at VSOI2 ¼
0 V is dependent on the radiation dose, while the 200 V breakdown at non-zero VSOI2 stayed similar for the doses from 10 kGy to
100 kGy.

-1~-10V-4

10

preirrad

10-5
10-6

100 kGy

10-70Fig. 3. On-pixel circuit of INTPIXh2 [11].

350 100 150 200 250 300 350
VDET [V]Fig. 5. Leakage current of the sensor irradiated to 100 kGy measured at different
VSOI2 setting. The curves are compared with pre-irradiation curve. Measurements
are at 20 °C.

The leakage current is a sum of contributions from the pixels andperipheral circuitry. The contribution from the pixels evaluated as thepedestal shift does not change by irradiation, suggesting that theleakage increase is dominantly caused in the peripheral.
As we discuss in Section 6, 200 V is not enough to fully deplete
the device of 300 μm thickness. While we continue investigating
the cause of the breakdown, 200 V is appropriate for the device
thinned to 100 μm in an actual application.

VDD
RSTx
STORE
RST

GND

LOAD
RSTV
COL_OUTREADSOI2STORExFig. 4. Layout of the INTPIXh2 pixel components.

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3. Response to IR laser after 100 kGy irradiation

5. Cross talkThe response of a sensor of 300 μm thickness irradiated with100 kGy was investigated by using an infrared (1024 nm wavelength) pulse laser. The response at a reverse voltage of 100 V wasclearly conﬁrmed at VSOI2 = − 10 V while no response was observed at VSOI2 = 0 V (see Fig. 6). This demonstrates the effectiveness of the compensation using the double SOI feature.
We studied the functionality of the circuit by measuring theoutput linearity w.r.t. the reset voltage amplitude VRST (see Fig. 4).
Fig. 7 plots the results for the 100 kGy irradiated sensor (100 μm
thick, 100 V applied reverse voltage). The vertical is in ADC unit
obtained when the output voltage is integrated over 1 μs. The
ﬁgure shows the recovery of the response through the applicationof the negative voltage VSOI2. There was no response seen at
VSOI2 = 0 V . The response curve of a non-irradiated sensor is alsoplotted for comparison. Radiation-induced shifts in operating
conditions, mainly thresholds, of the FETs were not been completely recovered from. This is because the optimum VSOI2 to recover the threshold voltage depends on the FET type (n or p, bodytied or body-ﬂoating [12]) and complete compensation is notpossible in this sensor design with a single common control.
However, a responsive region was clearly recovered by VSOI2 with aslightly reduced dynamic range. Lowering VSOI2 further was notpossible because no output was observed. A study with otherdevices suggested that this is caused by the threshold shifts ofelectrostatic discharge (ESD) diodes connected at the outputs
which loose functionality at increased |VSOI2 |.

The cross-talk characteristics were measured by injecting collimated IR laser to one pixel and measuring the signals out of theFig. 7. Response to VRST before and after 100 kGy irradiation with VSOI2 of 0 V,
 4 V, and  12 V [12].

4. Signal time response
The signal time structure was evaluated by using the pulsed IR
laser. The signal shape was measured by using a fast multi-pixel
photon counter (MPPC) for a base width of 50 ns and including ajitter spread of 5 ns, as shown in Fig. 8. We measured the output
charge from INTPIXh2 with a ﬁxed integration time of 10 ns. By
varying the delay time of integration start w.r.t. the IR laser trigger,
we derived the signal time response of INTPIXh2. As shown in
Fig. 9, the measured signal width was about 150 ns with a fastpeaking time of 40 ns for the non-irradiated device. After 100 kGy,
the time response slightly degraded to a 50 ns peaking time.

Fig. 8. Signal shape of IR-laser pulse measured with MPPC.

Fig. 6. Response to IR laser of a 100 kGy irradiated INTPIXh2: (left) VSOI2 = 0.0 V , (right) VSOI2 = − 10.0 V [12].

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nodes for an n-type substrate. Those electrons attracted at theboundary prevent from creation of inversion layer which worsens
the cross talk. The negative VSOI2 tends to remove the accumulated
electrons and create an inversion layer but the applied potential is
not sufﬁcient to deteriorate the cross talk. In summary, the cross talkwas determined to not be degraded by irradiation. Note that the
middle silicon layer acts as an electrical shield [14] through thecoupling to the sensor node, which reduces the amount of charge
read out by the ampliﬁer, as we discuss in Section 6.

6. Response to minimum-ionizing particles

Fig. 9. Signal shape of (top) non-irradiated and (bottom) 100-kGy irradiated
INTPIXh2.

surrounding pixels. A no metal region (window) was assured at the
pixel center (see Fig. 4) to allow for light injection from the top. The
laser spot size was adjusted to 4 μm square so that the laser was only
injected to one pixel. We deﬁned the cross talk as the ratio of theoutput signal from the pixel being evaluated to that from the pixel
where the laser was injected. Fig. 10 shows the results for the 100 μm
thick sensor before and after irradiation to 100 kGy for a signal integration time of 1 μs. The substantial cross talk at a low reverse bias
voltage is suppressed with increasing the bias voltage before irradiation, as the inter-pixel region is fully depleted with the bias (seeFig. 11). The cross talk is small after irradiation at the same bias
voltage. The potential of VSOI2 was set at 10 V in this measurement
since a negative potential is required for observing the signal, see
Section 3. The suppression of the cross talk by irradiation is explained
because the electrical isolation between pixels is improved by irradiation through the accumulation of electrons between p-type pixel

The response to penetrating 90Sr β -rays for a double SOI INTPIXh2
was measured with a single SOI INTPIXh2 for comparison. The
available single-type INTPIXh2 was 500 μm thick with an n-type
substrate and >2 kΩ cm resistivity, while the double was 300 μm
thick with an n-type substrate and 0.7 kΩ cm resistivity. The β-ray
source enclosed in a collimator was placed on top, and the penetrating β was triggered by a plastic scintillator. The data acquisition
timing chart and the setup illustration are shown in Fig. 12. The signal
integration time was set to 1 μs. The β-ray signal was reconstructedin a 7  7 pixel cluster about the seed pixel with the maximum response to an event. The reconstructed charge distribution is shown in
Fig. 13 for the single SOI sensor which was biased at 250 V. At 200 V
and above, the reconstructed charge peak is saturated and the sensor
is fully depleted at 250 V. Fig. 14 shows the charge distribution for the
double SOI sensor biased at 200 V. The depletion depth is calculated
to 210 μm for the wafer resistivity. The measurement conditions andother parameters are summarized in Table 1. The sensor gain (μV/e  )was obtained by observing the X-ray peaks of radioactive sources.
The sensor gain of the double SOI was roughly one half of that of thesingle SOI. This is explained by the coupling between the BPW and
SOI2 layer in the double SOI sensor. The coupling increased the detector capacitance and picked up a fraction of the signal by the SOI2
layer. The peak value of the single sensor 781 ADU (Fig. 13) was determined by a ﬁt of a Landau and Gaussian convolution function. The
value is consistent with the calculation using the sensor thickness of
500 μm and the parameters as listed in the table. The double-type
sensor showed a mip peak at 158 ADU (Fig. 14). For a 210 μm depletion thickness, the value is slightly off but within the expectation if

Fig. 10. Cross talk of INTPIXh2 before and after 100 kGy irradiation. The collimated laser was spotted at pixel-235, and relative pulse heights in neighboring pixels wereplotted for typical bias voltages.

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Fig. 11. Illustration of cross talk (left) before and (right) after irradiation. The VSOI2 voltage was 0 V before and  10 V after. The broken curve represents the depleted region
at a low bias voltage.

Fig. 12. (left) Data acquisition timing chart doe the mip measurement. On receiving a trigger, the following reset is disabled, and the readout sequence is activated. (right)
Geometric illustration of the setup.

Fig. 13. Cluster charge distribution obtained in single INTPIXh2.

Fig. 14. Cluster charge distribution obtained with double SOI INTPIXh2.

we take into account of the uncertainty in the substrate resistivity
and in other parameters.

7. Discussions and summary
We introduced a double SOI structure to compensate for the TID
damage and characterized the performance of the integration-type
pixel sensor INTPIXh2. The results obtained for the non-irradiatedand 100 kGy irradiated sensors showed that the response of the irradiated sensor can be recovered by applying a negative voltage to
the SOI2 layer. The double SOI structure enhanced the radiation resistivity up to 100 kGy. Therefore the double SOI sensor is alreadysufﬁciently radiation hard for use in high-energy experiments in hardradiation environment such as at Belle II or ILC.

Table 1
Parameters used in β-ray measurement. The depletion thickness of the double
sensor is a calculated value for the substrate resistivity and applied bias voltage.
The ADC conversion factors are the slope measured in the reset response (seeFig. 7).
Item

Single SOI

Double SOI

Physical thickness (μm)
Sub. resistivity (kΩ cm)
Bias (V)
Depletion thickness (μm)
Gain (μV/e  )ADC conversion (ADC/mV)
Expected ADC/mip (ADU)

500
>2
250
500
6.0
3.5
840

300
0.7
200
210
2.4
3.4
138

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Above this dose, however, the sensor became inoperative. The
main reason is suspected to be the different radiation-induced
threshold shifts among various types of FETs and the degradationof the transconductance, especially in PMOS FETs [12]. A recent
study [15] succeeded in improving the radiation tolerance of PMOS
FETs by adjusting the lightly doped drain (LDD) proﬁle. Also individual VSOI2 adjustments in pixel, decoder and IO regions provide
a wider operational range [16]. The radiation tolerance of suchdevices is currently being evaluated.

8. Acknowledgments
The authors are grateful for the fruitful collaboration with Lapis
Semiconductor Co. Ltd. The double SOI wafers were realized
through excellent work with Lapis and SOITEC. This work was
supported by JSPS KAKENHI Grant no. 25109006, KEK Detector
Technology Project and VLSI Design and Education Center (VDEC),
the University of Tokyo, in collaboration with the Cadence Corporation and Mentor Graphics Corporation.

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