Series/Parallel Connection Method of DC-DC Transformer
for Scalable Power Converter Systems using USPM
Takumi Iwamoto, Koki Yamanokuchi, Hiroki Watanabe and Jun-ichi Itoh
NAGAOKA UNIVERSITY OF TECHNOLOGY
1603-1, Kamitomioka-machi, Nagaoka, Niigata, Japan
Tel.: +81 / (258) – 47.9533.
E-Mail: s225057@stn.nagaokaut.ac.jp, koki_yamanokuchi@stn.nagaokaut.ac.jp,
hwatanabe@vos.nagaokaut.ac.jp, itoh@vos.nagaokaut.ac.jp
URL: http://itohserver01.nagaokaut.ac.jp/itohlab/jp/index.html

Acknowledgments
This work was supported by the Council for
Science, Technology, and Innovation (CSTI), theCross-ministerial Strategic Innovation Promotion
Program (SIP), and “Energy systems of anInternet of Energy (IoE) society” (Funding
agency: JST).

Keywords«Dual Active Bridge Converter», «CircuitControl»,«Parallel
operation»,«Series
Operation».

Abstract
This paper proposes a series or parallel
connection method of a DC-DC transformer(DCX) to achieve power scalability. Universal
Smart Power Module (USPM) modularizes all
power converter components. The power
converter is realized by combining several
USPMs to simplify the power electronics design.
A USPM with galvanic isolation (isolated USPM)
operates as a DCX. Isolated USPM must havehigh efficiency over a wide power range. In
addition, the voltage or current must be balanced
when connected in series or parallel. A dualactive-bridge converter is chosen as the main
circuit for the isolated USPM for theserequirements. The proposed method isdemonstrated by an experimental setup. As aresult, the current balance is improved by 75.0pt.
in parallel connection, and the voltage balance isimproved by 37.0pt. in series connection.

Introduction
In recent years, renewable energy
applications and electric vehicles have been
attracted from the viewpoint of carbon neutrality.

Elemental technologies such as circuit topology,
control methods, and design methods have beendeveloped for various applications due to theincreasing demand for such power converters. [13]. The development of the power converters
requires specialized and multifaceted know-how
such as circuit design, software development, andheat dissipation. Therefore, the development
takes a large amount of time and costs. In order toadapt to the increasing demand for power
converters in the future, the power converters
need to be developed quickly and at a low cost.
Power conversion systems based on modular
structures, such as Power Electronics Building
Block (PEBB), are being considered to solve thisproblem [4-6]. A PEBB realizes a power
conversion system by combining several
modules, which contain main circuits designed
for high power density. The PEBB eliminates theneed to design the main circuit and reduces
development time. These systems are scalable toadapt to various specifications by changing thenumber of modules. In case of failure, the system
is easy to maintain as the modules only need to be
replaced. However, a controller and noise filter
must be developed separately, even though themain circuit and some auxiliary circuits are
modularized. These developments require
additional time and costs.
USPM has been proposed to further shorten
development times and reduce costs for the PEBB
concept [7-9]. The USPM modularizes not only
the main circuit but also all components of thepower converter, such as the controller and noise
filter. The USPM allows any power conversion
system to be built simply by combining USPMs.
Therefore, the design of the power conversion
system only requires the USPM selection, which
greatly reduces the development speed. In the
power conversion system using USPM, a single
master controller controls many USPMs, andeach USPM operates independently and isdecentralized. The behavior of each USPM is an
ideal controllable voltage or current source. The
USPM responds quickly to commands from themaster controller to achieve power conversion.
Furthermore, the USPM can be applied to highvoltage and high-current systems because it canbe connected in multiple series and parallels.
The main circuits contained in the USPM aredeployed in multiple configurations, such as
single-phase H-bridges and three-phase inverters,
to suit a wide range of applications. One of thevarious configurations is a USPM with galvanic
isolation (isolated USPM). Isolated USPMs are
required to behave like DC transformers that do
not perform voltage conversion (always at a 1:1
voltage ratio) but only provide electrical isolation
between the primary and secondary sides. In
addition, it requires bidirectional power transfer
and high-efficiency operation under a wide range
of operating conditions. Isolated USPMs have notbeen studied with specific circuit schemes,
whereas single-phase H-bridge USPMs havebeen studied in previous studies [7]. In addition,
the control method for isolated USPMs in multiserial and multi-parallel configurations has also
not yet been studied.
This paper verifies the suitable topology andcontrol methods for the isolated USPM. The newcontribution of this paper is that the balancing
method of the current or voltage for the parallelor serial connection is established. As a result, theseries or parallel connection increases the voltage
and current rating of a power converter system,
respectively. In addition, the power balance ofeach USPM is kept with low bandwidthcommunication when multiple units areconnected because the isolated USPM operates
autonomously. This paper is organized asfollows: First, isolated DC-DC converters arecompared, and their features are summarized.
Next, the control of isolated USPM is discussed.
Finally, the effectiveness of the control method isverified through the verification of actual devices.

Universal Smart Power Module(USPM)
USPM in a power electronics system issimilar to the integrated circuits (ICs) andoperational amplifiers(Op-amps) in an electronics
circuit. The USPM can construct a more complex
power converter system. This is because the
USPM has all the essential components of apower converter, such as the main circuits, noise

USPM
USPM Controller
Comm.
Port

L
N
OutputPort

Detection Circuit

Lf /2
Cf
Rdamp

iac L /2 S1

GDU

DC
Link
Port

S3

+

Vdc

b

vac

Cdc

Lf /2

Lb/2
Main circuit S2

S4-

Cooling System

Fig. 1: Schematic diagram of USPM.
Master Controller (Low-speed)
USPM

USPM

USPM

High-speed
Cont roller

High-speed
Controll er

High-speed
Cont roller

USPM

USPM

USPM

High-speed
Controller

High-speed
Controll er

High-speed
Cont roller

Fig. 2: Example of power conversion systemusing USPM.
filters, and high-speed controllers with
communication. Therefore, designers of thepower converter systems do not need the
dedicated design of the main circuits, noise filters,
and so on. As a result, The USPM achieves
decreasing development time, reducing thedesign items, unnecessary designer’s skills, andso on.
Fig. 1 shows one example of a USPM
configuration with an H-bridge USPM. This
module has the capability of AC-DC, DC-AC,
and DC-DC conversion. The whole system willconsist of several USPMs and a master controller
for the entire power conversion system.
The USPM responds quickly to commands
from the master controller by incorporating anoise filter and a high-speed controller in addition
to the main circuit. Thus, the USPM works as an
ideal controllable voltage or current source
according to the command from the master
controller. Communication cables among each
USPM will be increased when USPM constructs
the entire system. Wireless communications areused between the master and slave controllers inorder to reduce the cables. It is difficult to control
instantaneous values with a master controllerbecause the wireless communication speed isonly a few tens of milliseconds at minimum.
Thus, each USPM is controlled by sending an
RMS value command from the master controller.
Fig. 2 shows a single-phase AC-AC power
converter system as an example of a power
conversion system using USPMs connected to an
Input-Series-Output-Parallel (ISOP). USPM on
the grid side is responsible for power factor
correction (PFC) operation, while the USPM
connected to the load side controls the load
voltage.
The module used in the ISOP configuration
requires galvanic isolation between the input andoutput because the different voltage potentials of
USPMs are connected to each other. The power
converter system using the galvanic isolation
USPM has voltage and current sharing issues.
Therefore, it is necessary to develop the USPM,
which has the galvanic isolation capability,
including the balance control for serial and/or
parallel connection.

Ld
Vpr

Vse

Fig. 3: Phase-shifted full-bridge DC-DC
converter.
Ll
Cr

Vpr

Vse

Lm

Fig. 4: LLC converter.
IDAB Ise

Ipr
S1
Vpr

S3
vinv_pr

Cd

Ll

S5

iL

S7
vinv_se
Cd

Vse

1:n
S2

S4

S6

S8

Fig. 5: Dual active bridge converter.

Circuit topology for isolated
USPMs
The “isolated USPM” concept is a DC-DC
transformer for the USPM-based power converter
systems. In order to achieve the role, the isolated
USPMs should have some functions and features
as follows;- Performing as a DC transformer with avoltage ratio of unity;- High efficiency in a wide bidirectional
output range;- Adjustable current and/or voltage sharing
function among parallel and/or series connected
USPMs;In this section, the suitable circuit topology isinvestigated in order to achieve these functions
and features. Three major circuit configurationsof the isolated DC-DC converter are selected asfollows:
1. Phase-shifted full bridge DC-DC converter(PSFB) [10-11]
2. LLC converter [12-13]
3. Dual Active Bridge (DAB) converter [1415]
Fig. 3 shows a PSFB DC-DC converter. The
converter has inductor Ld, and the inductor current
is controlled. The converter also performs as thebuck chopper when the power flow is from theprimary side to the secondary side. Thus, thevoltage characteristic is changed by power flow.
In addition, the inductor Ld must have a large

Table I: Characteristics of isolated DC/DC
circuit topologies.
Isolated DC/DC converter
Phase shift
LLC
DAB
Bidirectional○
operation
Efficiency○
Size－+ : Good, － : Bad, ○ : Neutral

＋

＋

○
＋

＋
＋

inductance, which avoids the downsizing of the
DC-DC converter. Thus, a PSFB DC-DC
converter is not suitable for isolated USPMs.
Fig. 4 shows an LLC converter. This
converter has the capacitor Cr, which is connected
to a transformer in series. Ll and Lm are leakage
inductance and magnetizing inductance of thetransformer, respectively. The LLC converter
achieves soft switching by a resonance between
Cr and Ll. On the other hand, the LLC converter
controls the switching frequency according to theload in order to maintain the voltage transfer ratio.
However, the voltage characteristic of the LLC
converter is changed with the load. Then, voltage
control of the LLC converter is difficult for theisolated USPM used in a wide power range. Thus,
the LLC converter is also not suitable for theisolated USPM.
Fig. 5 shows a DAB converter. The DAB
converter has an inductor connected to a

PI

－
sC

iC*
LPF

+
+ Ise
+ － z-1iC

Vse
Base carrierεγPhase-shift modulator

Vpr+

Mode selecter

δ
IDAB*

+
+
+
+
-

0.5
Phase-shift carrier

S1
S2
S3
S4
S5
S6
S7
S8

Fig. 6: Block diagram of voltage control.
transformer in series. The circuit topology issuitable for bidirectional operation because thetransmission power characteristic is not changed
with the power flow. In the turn ratio of thetransformer matches the input-output ratio, zerovoltage switching (ZVS) is achieved over theentire power range. Thus, the soft switching
operation is achieved in all conditions when theisolated USPM uses the topology.
Table I lists the characteristics of the threeisolated DC-DC circuit configurations. The DAB
and LLC converters are suitable for bidirectional
operation. The LLC converters achieve highefficiency around the rated condition, and theDAB converters have high efficiency over a wide
power range [16]. Moreover, the wide-range ZVS
is achieved in the DAB converter. Hence, a DAB
converter is suitable for isolated USPMs.

Control strategy of isolated USPM
using DAB converter
In this chapter, the key strategies aredescribed in order to use the DAB converters as
the isolated USPM.

A. Error compensation for non-linear
transmission power
The transmission power of the DAB converter
is controlled by the phase difference of thetransformer voltage δ between the primary sideand the secondary side. However, a non-linear
characteristic occurs at the light load due to thedead time. The isolated UPSMs should keep
linear characteristics in order to support the ideal
characteristics of the UPSM-based power
converters system. Thus, the effective error
compensation method is adopted [17].
The error compensation method in Ref[17]controls the zero current period of the inductor
current by the three-level output operation. The

compensation method is divided into threemodes:
1) Two-level mode for the heavy load,2) Three-level mode I for the light load,3) Three-level mode II for the significant light
load.
The two-level mode is a two-level operationof primary and secondary inverters. Mode I
operates with the zero current period fixed to thedead time by three-level operation. Mode II
operates with the phase difference fixed to deadtime by three-level operation.

B. Output voltage control
Fig. 6 shows a block diagram of the voltage
controller for a DAB-based isolated USPM
converter with the error compensation method.
The command of the secondary voltage is set tothe primary side voltage in order to operate as a
DCX. The deviation between the primary andsecondary side voltages is converted to acommand current by a PI controller. The
operation mode is selected depending on thecommand current, and the phase difference andthe zero voltage periods (ε, γ ) are calculated. The
phase shift carrier is generated from the phasedifference, the zero voltage period, and the basecarrier. The voltage control has a high-speed
response to disturbances by estimating thesecondary side current from the secondary side
voltage and the feedforward compensation. It is
possible to realize a low-cost isolated USPM
because the voltage control does not require acurrent sensor.

C. Current balance control for parallelconnected USPMs
The isolated USPMs should support parallel
connections
toconstructhigh-current
applications. Each USPM is an independent
power converter, and each module has somevoltage detection circuits. Thus, the current
imbalance among parallel-connected USPMs
may occur because of detection gain errors, theline impedance imbalance, and so on. The current
imbalance causes a reduction of efficiency and a
breakdown of control. Therefore, the current
balance must be kept. Note that current balance
control must be achieved only by low-speed
communication through the master controller.
Fig. 7 shows the block diagram of the current
balance control, where the suffix x is the cellnumber of USPM, the suffix m is the number ofparallel-connected USPMs, and Z is the gain of
the current balance control. The current balance
control calculates the imbalance current from theaverage value of the command current. Besides,
the current balance control keeps the current
balance by increasing or decreasing the voltage
command value based on the imbalance current.
The current balance control controls the DC
current and is implemented in the outer loop of
the voltage control. Therefore, the current balance
control is implemented in the low-speed master
controller to allow a delay in wirelesscommunication.
The gain Z of the current balance control isdesigned based on the accuracy of the current
balance control and its effect on the load
response. Z affects the transient characteristics
due to the communication delay. Therefore, it isnecessary to consider not only the current balance
but also transient characteristics when designing
Z. The imbalance current due to the detection gain
error of the secondary side voltage is obtained by

Vse
(1),
( ese_avg − ese _ x )Z
where ese_avg is the average value of the detection
gain error of the secondary side voltage, and ese_x
is the detection gain error of the secondary side
voltage of the cell x. The maximum fluctuation of
the secondary side voltage during the load step isI imbalance =∆Vse_max =∆IDABZ(2),where ∆IDAB is the change in the secondary sidecurrent.
Z is designed by (1) and (2). The lower limitof Z is calculated from the allowable imbalancecurrent using (1), and the upper limit of Z iscalculated from the maximum allowable voltage
fluctuation using (2). The current balance control
achieves compensation for both current balanceand voltage fluctuations during the load step bysetting Z within the calculated upper and lower

1

IDAB_1* ++m IDAB_ avg
IDAB_x* ++IDAB_m*Master Controller
IDA B_x*

Vpr_x

+

+

-

Z

IDAB_avg

PI
sC

+
+I
se
+ -1
LPF
z
iC

IDAB_x *Vse_x
IDAB_avg - +Current balance control

Slave Controller

Fig. 7: Block diagram of current balance
control.
IDAB_1
Vse_1

Vpr_1
IDAB_x
Vpr

Vpr_x

Vpr_m

Vse_x

IDAB_mVse

Vse_mFig. 8: Equivalent circuit of DAB converters
connected in series.
limits. In this paper, the allowable imbalancecurrent is the difference between the maximum
current and the rated current of the isolated
USPM in order to prevent control breakdown due
to the current imbalance. It is also designed sothat the maximum voltage fluctuation is within
10% of the rated voltage when the secondary sidecurrent changes by 1p.u.

D. Voltage balance control for seriesconnected USPMs
The Isolated USPMs should also support
series connections to construct high-voltage
applications. The voltage imbalance among
series-connected USPMs occurs because of thegain errors of voltage detection and so on. The
voltage imbalance may destroy the device.
Fig. 8 shows the equivalent circuit of the DAB
converter when connected in series, where thesuffix x is the cell number of the USPM, and thesuffix m is the number of series-connected
USPMs. The DAB converter is equivalent to a
current source. Thus, the series-connected DAB
converter with the independent controller isequivalent to a series-connected current source.

Then, the control interference among seriesconnected cells occurs. This paper applies thecurrent droop control in order to prevent control
interference.
Fig. 9 shows the block diagram of the current
droop control with the voltage balance control. In
addition to the current droop control, which
suppresses the control interference among each
USPM, the voltage balance control compensates
for the voltage imbalance among seriesconnected USPMs. The current source
interference and the voltage imbalance in theseries connection of the DAB converters arechanged with power flow. Hence, the current
droop control switches the operation modes
depending on the power flow, which is identified
from the command current. However, the droop
admittance Yd of the conventional current droop
control is constant. Therefore, the command
value fluctuates significantly during power flow
switching, which causes voltage fluctuations. The
proposed control varies Yd according to the loadto achieve seamless power flow switching. Yd is
defined byYd =I DAB_avg(3),
Kd
Vse_avg
where Kd is the droop gain. Kd should be set toless than 1. If Kd is set to more than 1, then theoperation becomes unstable because all iDAB is thecurrent id flowing in the droop admittance. The
voltage balance control calculates the imbalance
voltage from the average value of the secondaryside voltage. It keeps the voltage balance byincreasing or decreasing the voltage command
value based on that value. The imbalance voltage
is compensated more by increasing the gain K ofthe voltage balance control. Therefore, K was set
to 1 in this paper. The current droop control andthe voltage balance control are implemented in
the outer loop of the voltage control. Therefore,
the voltage balance control is implemented in the
low-speed master controller to allow a delay inwireless communication.

Experimental Verification
Table II shows the experimental conditions.
The dead time is set to a long time to evaluate thecompensation method for the transmission power
error. The effectiveness of the output voltage
control during a single operation, the voltage
balance control in a series connection, and thecurrent balance control in a parallel connection
are verified by the following experiments.

1m

IDAB_1* ++IDAB_x * ++IDAB_m *IDAB_avg

IDAB_x

Vse_x

IDAB_avg
Vse_avg

×
/

LPF

+
+

+
-

PI

Vpr_x

K

sC

Kd

LPF

1

Vse_1 +
Vse_avg+m
Vse_x ++
Vse_m
Master Controller
IDAB_avg

Vse_avg

Yd

Current droop
control+ id+ ++- + -1zsgn
IDAB_x*sgn
Vse_avg
Vse_x

control

Slave Controller

Fig. 9: Block diagram of voltage balance
control.
Table II: Experimental specifications.
Primary side voltage
Secondary side voltage
Rated power of one unit
Leakage inductanceTurn ratio of transformer
DC capacitance
Switching frequency
Dead time

Vpr
Vse
P
Ll
n
C
fsw
tdt

380 V
380 V
1000 W
760 µH1
60 µF
20 kHz
2 µs

A. One unit operation
Fig. 10 shows the operating waveforms forthe two-level mode and three-level mode. In thisexperiment, the USPM was driven by open-loop
control with the voltage sources connected to theprimary and secondary sides to verify each modeof operation. Fig. 10 (a) shows the operating
waveform when the power command P* = 1.0p.u.
Both the primary and secondary sides areoperating in two-level mode. Here, the power
error to the command value is 2.7%. Fig. 10(b)shows the operating waveform when the powercommand P* = 0.5p.u. The operating mode isMode I, with the primary and secondary side
voltages operating at three levels. The
magnetizing inductance increases the inductor
current and current flows during the zero current
period. The current during the zero current periodcauses resonance between the leakage inductanceand the parasitic capacitance of the device.
Therefore, the voltage is applied during the zerovoltage period of vinv_pr. Furthermore, theresonance causes a power error of 26.4%.Fig.
10(c) shows the operating waveform when the
power command P* = 0.2p.u. The operating mode

0
vinv_se 500 V/div

Two-level mode

0

Transmission power P [p.u.]

1.2
1200

vinv_pr 500 V/div

Mode I

0.8 Two-level
800
400
0.4

mode

Mode I
Mode II

Without error
compensation

Two-level
mode

0

-400
-0.4

iL 5 A/div

With error compensation

-0.8
-800

10 µs/div(a) Two-level mode. This mode is thegeneral operation of the DAB converter.
vinv_pr 500 V/div

Voltage is applied during thezero-voltage period.

0
Three-level mode

vinv_se 500 V/div0
iL 5 A/div

0

Zero current
period10 µs/div(b) Mode I. This mode fixes the zero current
period at dead time in three-level
operation.

-1.2
-1200
-1.2
-1200

1p.u.=1000W
00
-0.8
-0.4
0.8
1.2
0.4
-800
-400
400
800
1200
Command transmission value P* [p.u.]

Fig. 11: Characteristic of transmission powerin single DAB unit operation.
100
100
95
95
90
97%
90
85
85
80
80
75
75
70
70
65
65
-1.2 -800-0.8 -400
-0.4
-1200

Efficiency η [%]0

1p.u.=1000W

0.4
00.8 1200
1.2
0
400
800
Transmission power P [p.u.]

Fig. 12: Efficiency characteristic of a DAB
converter.

vinv_pr 500 V/div

0
Three-level mode

vinv_se 500 V/div0
iL 5 A/div

0

iL is not 0A during the zero-voltage period.
Zero current
period10 µs/div(c) Mode II. This mode fixes the phasedifference at dead time in three-level
operation.
Fig. 10: Experimental waveforms of eachmode.
is Mode II. In Fig.10(c), the inductor current iLduring the zero current period has a slight current
flow. This reason is a delay in the discharge fromthe parasitic capacitance due to hard switching on
the secondary side, which delays the start of thezero current period. The power error of 36.4%
occurs due to the delay in the start of the zerocurrent period. The cause of these errors is themagnetizing inductance, and therefore thetransformer must be redesigned.
Fig. 11 shows the transmission power
characteristics. The characteristics without error
compensation are non-linear at light loads, but thecharacteristics with the error compensation
method are nearly linear. On the other hand, thetransmission power is higher than thecommanded value during three-level operation.
This is caused by the voltage applied during thezero voltage period in Fig. 10(b) and the current
flowing during the zero current period in Fig.
10(c).
Fig. 12 shows the efficiency characteristics of
the DAB converter. The efficiency exceeds 97%
at 0.4p.u. or higher, enabling high-efficiency
operation over a wide bidirectional power range.
These results verify the effectiveness of the DAB
converter as the main circuit scheme for theisolated USPMs, which require high-efficiency
operation over a wide power range.
Fig. 13 shows the operating waveforms when
the load is changed stepwise from 0.63p.u. to
0.93p.u. in the voltage control of Fig. 6. Fig. 13(a)shows the waveform when the estimated Ise is notcompensated feedforward. The secondary side
voltage fluctuates by 78V during the load step.
Fig. 13(a) shows the waveform when theestimated Ise is compensated feedforward. The
secondary side voltage does not fluctuate during
the load step. Thus, the control of Fig. 6 achieves
a high response to disturbances without a current
sensor.

Vse [25 V/div]

Vse [25 V/div]

380 V

380 V
Ise [1 A/div]
Ise_2 [1 A/div]

78 V

16.8%

0.63p.u.

0.93p.u.

200 ms/div(a) Without feedforward compensation of
estimated Ise.

1.31p.u.

Ise [1 A/div]

200 ms/div(b) With feedforward compensation of
estimated Ise.
Fig. 13: Experimental waveform of load stepin single DAB unit operation.

Ise_2 [1 A/div]

Two DAB converters are connected inparallel to verify the effectiveness of the current
balance control. These DAB converters are driven
by two independent controllers, respectively. In
addition, a detection gain error of 1% is added tothe secondary side voltage of the DAB converter
at cell ＃1. Note that the effect of the detection
gain error is almost the same as the impedance
imbalance of the connecting wire for each USPM.
Moreover, the circulating currents due toasynchronous carriers occur. In this experiment,an LC filter with a cutoff frequency of 2 kHz isconnected to suppress the circulating current. In
the future, the suppression method of thecirculating
current
without
additional
components must be needed to achieve compact
USPMs.
Fig. 14 shows the experimental waveforms
without the current balance control at a parallel
connection. In this experiment, the load is varied
from 1.31p.u. to 1.97p.u. The current imbalance
rate before the load change is 77.9%, and after thechange is 16.8%. Note that the current imbalance
rate αI is defined by− I se_avg

I se_avg(4),

where Ise_avg is the average of Ise_1 and Ise_2. The
current imbalance rate increases at light loads.

6.2%

Ise_1 [1 A/div]

1.97p.u.

10 [ms/div]

2.9%
0A
1.31p.u.

B. Parallel connectionI

10 [ms/div]

Vse [25 V/div]

380 V

No undershoot.

α I = se_1

1.97p.u.

Fig. 14: Experimental waveforms of load stepin parallel connection without the current
balance control.

Vse [25 V/div]

0.93p.u.

Ise_1 [1 A/div]

0A

380 V

0.63p.u.

77.9%

Fig. 15: Experimental waveforms of load stepin parallel connection with the current balance
control.
This is because the secondary side current of the
DAB converter at cell # 2 did not change before
and after the load step. The phase difference of
the DAB converter at cell # 2 at tt time is fixed at
90 degrees and is not improved by the voltage
control interference. Therefore, only the DAB
converter at cell # 1 changes the current, and thecurrent imbalance increases at light loads.
Fig. 15 shows the experimental waveforms
with the current balance control at a parallel
connection. The allowable imbalance current is
0.25A, and the allowable voltage fluctuation is
38V in this experiment. From (1) and (2), thelower and upper limits of Z are 7.6 and 14.,respectively. Therefore, Z is set to 10. In thisexperiment, the load is varied from 1.31p.u. to
1.97p.u. The current imbalance rate before theload change is 2.9%, and after the change is 6.2%.
The current balance control improves the current
imbalance rate by 75.0pt. at 1.31p.u. and by
10.6pt. at 1.97p.u. The imbalance current is 0.05
A before the load step and 0.16 A after the load
step, which is less than the allowable imbalancecurrent. Thus, the imbalance of the secondary sidecurrent due to the detection gain error iscompensated by the current balance control.

C. Series connection

Vse [25 V/div]

Two DAB converters are connected in series
to verify the effectiveness of the voltage balance
control. The primary side voltage is set to 380 V.
These DAB converters are driven by two
independent controllers, respectively. In addition,a detection gain error of 1% is added to thesecondary side voltage of the DAB converter atcell #1.
Fig. 16 shows the experimental waveforms
without the voltage balance control at the seriesconnection. In this experiment, the load is varied
from 0.36p.u. to 0.49p.u. The voltage imbalance
rate before the load step is 37.5%, and theimbalance rate after the load step is 16.1%. Notethat the current imbalance rate αV is defined by

α V_se =Vse_1 − Vse_avg(5),

Vse_avg
where Vse_avg is the average of Vse_1 and Vse_2.
The imbalance rate increases at light loads. In
addition, the phase difference of the DAB
converter at cell # 2 at this time is fixed at 90
degrees and is not improved by the voltage
control interference.
Fig. 17 shows the experimental waveforms
with the voltage balance control at the seriesconnection. The droop gain Kd of the voltage
droop control is set to 0.7, and the gain K of thevoltage balance control is set to 1. The load isvaried from 0.36p.u. to 0.49p.u. The voltage
imbalance rate before the load step is 0.5%, andthe imbalance rate after the load step is 1.0%. The
voltage balance control improves the voltage
imbalance rate by 37.0pt. at 0.36p.u. and by
15.1pt. at 0.49p.u. The imbalance of the voltage
caused by detection gain errors is compensated by
the voltage balance control.

Conclusion
In this paper, the circuit topology and control
for an isolated USPM were investigated. The
DAB converter was selected as the circuit
configuration because of its suitable bidirectional
performance and high efficiency. The
experimental verification with a single unit
verified that the efficiency exceeds 97% at 0.4p.u.
or higher and that high-efficiency operation was
possible over a wide power range. The current
and voltage balance control methods for theisolated USPMs in parallel and series connections
were verified by the experiment. As a result, thecurrent imbalance rate at 1.31p.u. was improved

380 V

Vse_1 [50 V/div]
190 V

37.5%

16.1%
Vse_2 [50 V/div]

0.36p.u.

0.49p.u.

40 [ms/div]

Fig. 16: Experimental waveforms of load stepin series connection without the voltage
balance control.
380 V
Vse [25 V/div]

Vse_1 [50 V/div]
190 V
0.5%

Vse_2 [50 V/div]

0.36p.u.

0.49p.u.

1.0%
40 [ms/div]

Fig. 17: Experimental waveforms of load stepin series connection with the voltage balance
control.
by 75.0pt. in parallel connection, and the voltage
imbalance rate at 0.36p.u. was improved by
37.0pt. in series connection. In the future, we plan
to verify power balance control that combines
voltage balance control and current balance
control in a series-parallel connection.

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