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i(t)=!" p(t)@tEC
1 - exp RC
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exp(2.6)- 2RCt(2.7)(2.8)

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 t2 RC2 RCRC t


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exp -RC- 2 B 1 - exp - t

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+ 1 exp -RC2t - T

12 RC2t - T+B2
 t
RC
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 t
RC22RCRC t-2 RC B 1 - exp exp - 1 T -  t 1 - exp -  t + B  t
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1 - exp -(2.16)

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(2.18)

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2
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1 - exp -RCT

1 - exp - 2 RT C

02RCexp -2 RCp(t) tp ( t ) = B 1 - exp - R C

21 - exp -     !"#$%&'(QQ = R2C B 1 - exp - R Ct     2T2 RC28 Q 
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allal lt
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222 exp - 2 R1 C T - 2  t + exp - R1C T - 2  t- 2exp - 2 R1 C 3 T - 4  t + exp - R1C 2 T -  t !!"#$%&  '( Q .

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2tn

ininv

Vi n - V t n(2.28)

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V i n - V DD - V t p

V o u t - V DD -V o u t - V DD
22(2.29)

O-/-"6ÕÖ±²-"O-;×Ø¡ÙÚÛÜ¤8!
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i ni n v

i n v

nI ds n=Vi n - Vtn 22(2.30)

   pMOS  D-S "
I dsp = -p
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V DD + V + V
V =1 + tptninndspin(2.32)pnp       , - =-  nMOS  pMOS .#/0#1234 V
2.5V 567  npin v

DDI ds n =n
2Vi nv - Vt n 2(2.33)

        8   V 9V :V + V ;< nMOS         => D-S "
inv

I dsn =  n

V i n - V t n V ou t -      +? pMOSI dsp = -in

p
2

DDtp

V o ut 22(2.34)!

V i n - V DD - V t p2(2.35)

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inDD

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V   B n2 V -V
in

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(1) M.Lee and K.Asada, “Ultimate Lower Bound of Power for MOS Integrated Circuitsand Their Applications,” IEICE Trans. Electron., Vol. E77-C, No.7, July, 1994.
(2) J.Akita, M.Lee and K.Asada, 2 ;;<= ! >?@ yº A þ B k ACDE , A68,p.68.
(3) NEIL H. E. WESTE, KAMRAN ESHRAGHIAN F   PRINCIPLES OF CMOS VLSI DESIGN(4) G'H& IJ F  KL EM ­  NO(5) P0 Q F      XR S TØU´U(6) VW °XYZ°[\]°^_#  F     !

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