REVISIONSLTR

DESCRIPTIONDATEAPPROVEDA

Add case outline Y. - PHN

10-02-22

Thomas M. Hess

B

Change values for low power mode 3
current ILPM3, VLO and Input leakage current Ilkg , inTable I. - PHN

11-06-14

David J. Corbett

C

Update boilerplate to current MIL-PRF-38535
requirements. - PHN

18-01-16

Thomas M. HessD

Update boilerplate paragraphs to current VID
description requirements. - PHN

23-11-20

Muhammad A. Akbar

CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24

Vendor item drawing

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REV STATUS
OF PAGESPMIC N/A

PREPARED BY
Phu H. Nguyen

Original date of drawing
YY MM DD
09-03-10

CHECKED BY

Phu H. Nguyen

APPROVED BY
Thomas M. Hess
SIZE

CODE IDENT. NO.

AREVDEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO 43218-3990
https://www.dla.mil/landandmaritime
TITLE
MICROCIRCUIT, DIGITAL, MIXED SIGNALMICROCONTROLLER, MONOLITHIC SILICONDWG NO.

V62/08631

16236
D

PAGE

1

OF

38

DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
AMSC N/A

5962-V013-24

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance mixed signal microcontroller microcircuit, with
an operating temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/08631-

Drawing
number

01

X

A

Device type
(See 1.2.1)

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic

01

Circuit function

MSP430F2274-EP

Mixed signal microcontroller

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

Package style

X
Y

40
38

JEDEC MO-220
JEDEC MO-153

Plastic quad flatpack
Plastic small outline package

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
1.3 Absolute maximum ratings.

Material
Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Other

1/

Voltage applied at VCC to VSS .......................................................................... -0.3 V to 4.1 V
Voltage applied to any pin ............................................................................... -0.3 V to VCC + 0.3 V
Diode current at any device terminal ............................................................... ±2 mA
Storage temperature range, TSTG (unprogrammed device) .............................. -55°C to 150°C 3/
Storage temperature range, TSTG (programmed device) .................................. -55°C to 125°C 3/

1/

2/
3/

2/

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltages referenced to VSS. The JTAG fuse blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage isapplied to the test pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification withpeak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

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1.4 Recommended operating conditions. 4/ 5/ 6/
Supply voltage during program execution (VCC) ................................................................... 1.8 V to 3.6 V
Supply voltage during program/erase flash memory (VCC) ................................................... 2.2 V to 3.6 V
Supply voltage (VSS) ............................................................................................................. 0 V
Processor frequency fSYSTEM (Maximum MCLK frequency): 4/ 5/ 7/
VCC = 1.8 V, Duty Cycle 50% ±10% .............................................................................. 4.15 MHz
VCC = 2.7 V, Duty Cycle 50% ±10% .............................................................................. 12 MHz
VCC ≥ 3.3 V, Duty Cycle 50% ±10% .............................................................................. 16 MHz
Operating free air temperature range, TA ............................................................................. -55°C to 125°C
2. APPLICABLE DOCUMENTSJEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)JEP95
JEDEC J-STD-020––

Registered and Standard Outlines for Semiconductor Devices
Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state
surface mount devices.

(Copies of these documents are available online at https://www.jedec.org.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as
specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.

_________
4/
5/
6/
7/

The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of thespecified maximum frequency.
Modules might have a different maximum input clock specification. Refer to the data sheet from manufacturer.
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or
distributor maintain no responsibility or liability for product used beyond the stated limits.
See figure 4.

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3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3.
3.5.4 Operating area. The operating area shall be as shown in figure 4.
3.5.5 Active mode supply current. The active mode supply current shall be as shown in figure 5.
3.5.6 POR/Brownout reset. The POR/Brownout reset shall be as shown in figure 6-8.
3.5.7 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 9-15.

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4TABLE I. Electrical performance characteristics. 1/
Test

SymbolTA

Conditions
2/
unless otherwise specified

Active mode (AM)current(1 MHz)

IAM,
1MHz

IAM,
1MHz

Active mode (AM)current(4 kHz)IAM, 4kHz

Active mode (AM)current(100 kHz)IAM,
100 kHzLow power mode 0,(LPM0) current 5/

ILPM0,

Low power mode 0,(LPM0) current 5/

ILPM0,

1 MHz

100 kHz

LimitsMin

Active mode supply current (into DVCC + AVCC) Excluding External current
Active mode (AM)current(1 MHz)VCC

fDCO = fMCLK = fSMCLK = 1 MHz,fACLK = 32,768 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1 MHz
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 1 MHz,fACLK = 32,768 Hz,
Program executes in RAM,BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1 MHz
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fMCLK = fSMCLK= fACLK = 32,768 Hz/8 =4096 Hz,fDCO = 0 Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCGO = 0, SCG1 = 0,
OSCOFF = 0
fMCLK = fSMCLK= fDCO(0,0) ≈ 100 kHz,fACLK = 0 Hz,
Program executes in flash,
RSELx = 0, DCOx = 0, CPUOFF = 0,
SCGO = 0, SCG1 = 0, OSCOFF = 1
fMCLK = 0 MHz, fSMCLK= fDCO = 1 MHz,fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1 MHz,DCOCTL = CALDCO_1 MHz,CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fMCLK = 0 MHz, fSMCLK= fDCO(0,0) ≈ 100
kHz,
fACLK = 0 Hz,
RSELx = 0, DCOx = 0, CPUOFF = 1,
SCGO = 0, SCG1 = 0, OSCOFF = 1

Unit

Typ

Max

2.2 V

270

390

3V

390

550

2.2 V
3V

240
340

-55°C to 85°C
125°C

2.2 V

5

9
18

-55°C to 85°C
125°C

3V

6

10
20

-55°C to 85°C

2.2 V

60

85

72

95
95

3/ 4/ See figure 5.

-55°C to 125°C

125°C-55°C to 85°C

3V

µA

µA

µA

µA

125

125°C
-55°C to 125°C

2.2 V
3V

75
90

90
120

µA

-55°C to 125°C

2.2 V
3V

37
41

60
75

µA

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolTA

Conditions
2/
unless otherwise specified

VCC

LimitsMin

Active mode supply current (into DVCC + AVCC) Excluding External current - Continued 3/ 4/
2.2 V
fMCLK = fSMCLK= 0 MHz, fDCO = 1 MHz,
-55°C to 85°C
Low power mode 2
ILPM2
fACLK = 32,768 Hz,
125°C
BCSCTL1 = CALBC1_1MHz,(LPM2) current 6/
3V-55°C to 85°C
DCOCTL = CALDCO_1 MHz,
125°C
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
2.2 V
-55°C
Low power mode 3(LPM3) current 6/

Low power mode 3
current (LPM3) 6/

Low power mode 4
current (LPM4) 7/

ILPM3, LFXT1

ILPM3, VLO

ILPM4

25°C
85°C

fDCO = fMCLK = fSMCLK = 0 MHz,fACLK = 32,768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0

125°C
-55°C

-55°C
25°C

fDCO = fMCLK = fSMCLK = 0 MHz,fACLK = from internal LF oscillator (VLO),CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0

-55°C
25°C
85°C
125°C
-55°C
25°C
85°C

2.2 V/
3V

Typ

Max

22

29
40

25

32
45

0.7

1.4

0.7
2.8
6

1.4
4.5
18

0.9
0.9

1.5
1.5

3.0
6.5

5.0
19

0.4
0.5

1.0
1.0

2.2
5.7
0.5

4.2
18
1.2

0.6
2.5

1.2
4.5

6.0
0.1

19
0.5

0.1
1.9
5.5

0.5
4.0
16

µA

µA

µA

µA

8/
-55°C to 125°C

VIT--55°C to 125°C

Input voltage
hysteresis(VIT+ - VIT-)
Pullup/Pulldown
resistor

Vhys-55°C to 125°C

Input capacitanceCI

For Pullup: VIN = VSS;For Pulldown: VIN = VCC
VIN = VSS or VCC

3V

125°C

Negative going input
threshold voltage

RPull

2.2 V

85°C
125°C

fDCO = fMCLK = fSMCLK = 0 MHz,fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1

Schmitt-trigger inputs (Ports P1, P2, P3, P4, and RST/NMI)
Positive going input
VIT+
threshold voltage

3V

25°C
85°C
125°C

Unit

2.2 V
3V
2.2 V
3V
2.2 V
3V

1.00
1.35
0.55
0.75
0.2
0.3
20

-55°C to 125°C

1.65
2.25
1.20
1.65
1.0
1.0
35

50

5

kΩ
pF

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.
Test

SymbolInput (Ports P1 and P2)
External interrupt timing

Conditions
2/
unless otherwise
specifiedTA

VCC-55°C to 125°C

2.2 V/
3V-55°C to 125°C

2.2 V/
3V-55°C to 125°C

2.2 V

See figure 6 through 8
See figure 6

V(B_IT-)
Vhys(B_IT-)-55°C to 125°C-55°C to 125°C

See figure 6
Pulse length needed at

td(BOR)t(reset)-55°C to 125°C

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A

RST /NMI pin to accepted
reset internallydVCC/dt ≤ 3 V/s
dVCC/dt ≤ 3 V/s

LimitsMin

Port P1, P2: P1.x toP2.x, External trigger
pulse width to set
interrupt flag 9/
Leakage current (Ports P1, P2, P3 and P4)
High impedance leakage
Ilkg(Px.x)
10/ 11/current
Output (Ports P1, P2, P3, and P4)
IOH(max) = -1.5 mA
12/High level output voltage
VOH
IOH(max) = -6 mA
13/
IOH(max) = -1.5 mA
12/
IOH(max) = -6 mA
13/
IOL(max) = 1.5 mA
12/
Low level output voltage
VOL
IOL(max) = 6 mA
13/
IOL(max) = 1.5 mA
12/IOL(max) = 6 mA
13/
Output frequency (Ports P1, P2, P3, and P4)
Port output frequency
fPx.y
P1.4/SMCLK, CL = 20
pF,
(with load) 14/ 15/
RL = 1 kΩ against VCC/2
Clock output frequency
fPort_CLK
P2.0/ACLK,
P1.4/SCMCLK,
CL = 20 pF 15/
POR/Brownout Reset (BOR) 16/ 17/
See figure 6
VCC(start) dVCC/dt ≤ 3 V/st(int)

1/

Max

20

ns

±100

nA

VCC
VCC
VCC
VCC
VSS + 0.25
VSS + 0.6
VSS + 0.25
VSS + 0.6

V

2.2 V
3V

10
12

MHz

2.2 V
3V

12
16

MHz

3V
2.2 V
3V

-55°C to 125°C

Typ

Unit

VCC – 0.25
VCC – 0.6
VCC – 0.25
VCC – 0.6
VSS
VSS
VSS
VSS

0.7 x
V(B_IT-)-55°C to 125°C

70
2.2 V/
3V

130

V

V
1.71
210

V
mV

2000

µs
µs

2

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions
2/

VCC

LimitsMin-55°C ≤ TA ≤ 125°C
unless otherwise specified

Typ

Unit
Max

DCO frequency
Supply voltage range
DCO frequency (0, 0)
DCO frequency (0, 3)
DCO frequency (1,3)
DCO frequency (2, 3)
DCO frequency (3, 3)
DCO frequency (4, 3)
DCO frequency (5, 3)
DCO frequency (6, 3)
DCO frequency (7, 3)
DCO frequency (8, 3)
DCO frequency (9, 3)
DCO frequency (10, 3)
DCO frequency (11, 3)
DCO frequency (12, 3)
DCO frequency (13, 3)
DCO frequency (14, 3)
DCO frequency (15, 3)
DCO frequency (15, 7)
Frequency step between
range RSEL and RSEL+1
Frequency step between tap
DCO and DCO+1
Duty cycle

fDCO(0,0)fDCO(0, 3)
fDCO(1, 3)
fDCO(2, 3)
fDCO(3, 3)
fDCO(4, 3)
fDCO(5, 3)
fDCO(6, 3)
fDCO(7, 3)
fDCO(8, 3)
fDCO(9, 3)
fDCO(10, 3)
fDCO(11, 3)
fDCO(12, 3)
fDCO(13, 3)
fDCO(14, 3)
fDCO(15, 3)
fDCO(15, 7)
SRSEL

RSELx < 14
RSELx = 14
RSELx = 15
RSELx = 0, DCOx = 0, MODx = 0
RSELx = 0, DCOx = 3, MODx = 0
RSELx = 1, DCOx = 3, MODx = 0
RSELx = 2, DCOx = 3, MODx = 0
RSELx = 3, DCOx = 3, MODx = 0
RSELx = 4, DCOx = 3, MODx = 0
RSELx = 5, DCOx = 3, MODx = 0
RSELx = 6, DCOx = 3, MODx = 0
RSELx = 7, DCOx = 3, MODx = 0
RSELx = 8, DCOx = 3, MODx = 0
RSELx = 9, DCOx = 3, MODx = 0
RSELx = 10, DCOx = 3, MODx = 0
RSELx = 11, DCOx = 3, MODx = 0
RSELx = 12, DCOx = 3, MODx = 0
RSELx = 13, DCOx = 3, MODx = 0
RSELx = 14, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 7, MODx = 0
SRSEL = fDCO(RSEL+1, DCO) /fDCO(RSEL,DCO)

SDCO

SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)

1.05

1.08

1.12

ratio

Measured at P1.4/SMCLK

40

50

60

%

VCC

2.2 V/3 V

3V
3V
2.2 V/3 V

1.8
2.2
3.0
0.06
0.07
0.10
0.14
0.20
0.28
0.39
0.54
0.80
1.10
1.60
2.50
3.00
4.30
6.00
8.60
12.0
16.0

3.6
3.6
3.6
0.14
0.17
0.20
0.28
0.40
0.54
0.77
1.06
1.50
2.10
3.00
4.30
5.50
7.30
9.60
13.9
18.5
26.0
1.55

V

MHz

ratio

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions
2/

VCC

Limits
Min

Typ

Max

-1
0.990

±0.2
1

1
1.010

7.920

8

8.080

11.88

12

12.12

15.84

16

16.16

-2.5
-2.5
-2.5
-3.0
0.970
0.975
0.970
7.760
7.800
7.600
11.70
11.70
11.70
15.52
15.00

±0.5
±1.0
±1.0
±2.0
1
1
1
8
8
8
12
12
12
16
16

2.5
2.5
2.5
3.0
1.030
1.025
1.030
8.400
8.200
8.240
12.30
12.30
12.30
16.48
16.48

-55°C ≤ TA ≤ 125°C
unless otherwise specified
Calibrated DCO frequencies (Tolerance at Calibration)
Frequency tolerance at calibration
TA = 25°C
BCSCTL1 = CALBC1_1MHz,
1 MHz calibration valuefCAL(1 MHz)DCOCTL = CALDCO_1MHz,
Gating time: 5 ms, TA = 25°C
BCSCTL1 = CALBC1_8MHz,
8 MHz calibration valuefCAL(8 MHz)DCOCTL = CALDCO_8MHz,
Gating time: 5 ms, TA = 25°C
BCSCTL1 = CALBC1_12MHz,
12 MHz calibration valuefCAL(12 MHz)DCOCTL = CALDCO_12MHz,
Gating time: 5 ms, TA = 25°C
BCSCTL1 = CALBC1_16MHz,
16 MHz calibration valuefCAL(16 MHz)DCOCTL = CALDCO_16MHz,
Gating time: 2 ms, TA = 25°C
Calibrated DCO frequencies (Tolerance over temperature)
1 MHz tolerance over temperature
8 MHz tolerance over temperature
12 MHz tolerance over temperature
16 MHz tolerance over temperature
BCSCTL1 = CALBC1_1MHz,
fCAL(1 MHz)
1 MHz calibration value
DCOCTL = CALDCO_1MHz,
Gating time: 5 ms
8 MHz calibration value

12 MHz calibration value
16 MHz calibration valuefCAL(8 MHz)BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5 ms

fCAL(12 MHz)BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,
Gating time: 5 ms

fCAL(16 MHz)BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
Gating time: 2 ms

3V

3V

2.2 V
3V
3.6 V
2.2 V
3V
3.6 V
2.2 V
3V
3.6 V
3V
3.6 V

Unit

%
MHz

%

MHz

See footnotes at end of table.

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9TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions
2/-55°C ≤ TA ≤ 125°C
unless otherwise specified
Calibrated DCO frequencies (Tolerance over supply voltage VCC)
1 MHz tolerance over VCC
TA = 25°C
8 MHz tolerance over VCC
12 MHz tolerance over VCC
16 MHz tolerance over VCC
BCSCTL1 = CALBC1_1MHz,
1 MHz calibration valuefCAL(1 MHz)DCOCTL = CALDCO_1MHz,
Gating time: 5 ms, TA = 25°C
BCSCTL1 = CALBC1_8MHz,
8 MHz calibration valuefCAL(8 MHz)DCOCTL = CALDCO_8MHz,
Gating time: 5 ms, TA = 25°C
BCSCTL1 = CALBC1_12MHz,
12 MHz calibration valuefCAL(12 MHz)DCOCTL = CALDCO_12MHz,
Gating time: 5 ms, TA = 25°C
BCSCTL1 = CALBC1_16MHz,
16 MHz calibration valuefCAL(16 MHz)DCOCTL = CALDCO_16MHz,
Gating time: 2 ms, TA = 25°C
Calibrated DCO frequencies (Overall tolerance)
1 MHz tolerance over temperature
8 MHz tolerance over temperature
12 MHz tolerance over temperature
16 MHz tolerance over temperature
BCSCTL1 = CALBC1_1MHz,
1 MHz calibration valuefCAL(1 MHz)DCOCTL = CALDCO_1MHz,
Gating time: 5 ms, TA = 25°C
BCSCTL1 = CALBC1_8MHz,
8 MHz calibration valuefCAL(8 MHz)DCOCTL = CALDCO_8MHz,
Gating time: 5 ms
BCSCTL1 = CALBC1_12MHz,
12 MHz calibration valuefCAL(12 MHz)DCOCTL = CALDCO_12MHz,
Gating time: 5 ms
BCSCTL1 = CALBC1_16MHz,
16 MHz calibration valuefCAL(16 MHz)DCOCTL = CALDCO_16MHz,
Gating time: 2 ms

VCC

Limits

Unit

Min

Typ

Max

1.8 V to 3.6 V

-3
-3
-3
-3
0.970

±2
±2
±2
±2
1

3
3
3
3
1.030

1.8 V to 3.6 V

7.760

8

8.240

2.2 V to 3.6 V

11.64

12

12.36

3 V to 3.6 V

15.00

16

16.48

1.8 V to 3.6 V
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V
1.8 V to 3.6 V

-5
-5
-5
-6
0.950

±2
±2
±2
±3
1

+5
+5
+5
+6
1.050

1.8 V to 3.6 V

7.6

8

8.4

2.2 V to 3.6 V

11.4

12

12.6

3 V to 3.6 V

15.00

16

17.00

1.8 V to 3.6 V
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V

%

MHz

%

MHz

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions
2/

VCC

LimitsMin-55°C ≤ TA ≤ 125°C
unless otherwise specified

Unit

Typ

Max

Wake up from lower power Modes (LPM3/4)

DCO clock wake up time from
LPM3/418/

CPU wake up time from LPM3/4
19/

tDCO,LPM3/4

BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,

2.2 V/3 V

2

2.2 V/3 V

1.5

3V

1

3V

1

tCPU,LPM3/4µs

1/fMCLK +tClock,LPM3/
4

DCO with external resistor ROSC
DCO output frequency with ROSC

fDCO,ROSCDCOR = 1, RSELx = 4, DCOx = 3,
MODx = 0, TA = 25°C

2.2 V
3V

1.8
1.95

MH
z

Temperature drift

Dt

2.2 V/3 V

±0.1

%/°C

Drift with VCC

DV

DCOR = 1, RSELx = 4, DCOx = 3,
MODx = 0
DCOR = 1, RSELx = 4, DCOx = 3,
MODx = 0

2.2 V/3 V

10%/V

1.8 V to
3.6 V

32,768Hz

32,768 50,000

Hz

500

kΩ

Crystal Oscillator (LFXT1) Low frequency Modes-55°C ≤ TA ≤ 105°C
21/
LFXT1 oscillator crystal frequency,
fLFXT1,LF
XTS = 0, LFXT1Sx = 0 or 1
LF mode 0, 1
LFXT1 oscillator logic level square fLFXT1,LF,logi XTS = 0, LFXT1Sx = 3
wave input frequency, LF modec
XTS = 0, LFXT1Sx = 0;
fLFXT1,LF = 32,768 Hz, CL,eff = 6 pF
Oscillation allowance for LF
OALF
crystal
XTS = 0, LFXT1Sx = 0;
fLFXT1,LF = 32,768 Hz, CL,eff = 12 pF
XCAPx = 0
Integrated effective load
CL,eff
XCAPx = 1
capacitance, LF mode 22/
XTS = 0
XCAPx = 2
XCAPx = 3
LF modeDuty cycle TA = -55°C to 125°C
XTS = 0, Measured at P1.4/ACLK,fLFXT1,LF = 32,768 Hz
Oscillator fault frequency
fFault,LF
TA = -55°C to 125°C
threshold, LF mode 23/
XTS = 0, LFXT1Sx = 3
24/

10,000200

2.2 V/3 V

30

2.2 V/3 V

10

1
5.5
8.5
11
50

pF

70

%

10000

Hz

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions
2/

VCC-55°C ≤ TA ≤ 125°C
unless otherwise specified
Internal very low power, Low frequency oscillator (VLO)
TA = -55°C to 85°C
VLO frequency
fVLO
TA = 125°C
VLO frequency temperature drift
dfVLO/dT
25/
VLO frequency supply voltage drift
dfVLO/dVCC TA = 25°C 26/

2.2 V/3 V

fLFXT1,HF2

LFXT1 oscillator logic level squarewave input frequency, HF modefLFXT1,HF,logic

Oscillation allowance for HF crystals
See figure 9

OAHF

Integrated effective load
capacitance, HF mode 22/
HF modeOscillator fault frequency, HF mode
23/
Timer_A

Duty cycle

fFault,HF

Timer_A clock frequency

fTA

Timer_A, capture timing
Timer_B

fTA,cap

Timer_B clock frequency

fTB

Timer_B, capture timing

fTB,cap

XTS = 1, LFXT1Sx = 2

XTS = 1, LFXT1Sx = 3

Unit

Min

Typ

Max

4

12

20
22

0.5
4

1.8 V – 3.6 V

Crystal Oscillator (LFXT1) high frequency modes 21/
LFXT1 oscillator crystal frequency,
fLFXT1,HF0
XTS = 1, LFXT1Sx = 0
HF mode 0
LFXT1 oscillator crystal frequency,
fLFXT1,HF1
XTS = 1, LFXT1Sx = 1
HF mode 1
LFXT1 oscillator crystal frequency,
HF mode 2

Limits%/°C%/V

1.8 V to 3.6 V

0.41

1.8 V to 3.6 V

14

1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V
1.8 V to 3.6 V
2.2 V to 3.6 V
3 V to 3.6 V

2
2
2
0.4
0.4
0.4

10
12
16
10
12
16

XTS = 0, LFXT1Sx = 0;
fLFXT1,HF = 1 MHz, CL,eff = 15 pF
XTS = 0, LFXT1Sx = 1;
fLFXT1,HF = 1 MHz, CL,eff = 15 pF
XTS = 0, LFXT1Sx = 2;
fLFXT1,HF = 1 MHz, CL,eff = 15 pF
XTS = 1 27/

kHz

MHz

2700

Ω

800
300
1

XTS = 1, Measured at P1.4/ACLK,fLFXT1,HF = 10 MHz
XTS = 1, Measured at P1.4/ACLK,fLFXT1,HF = 16 MHz
XTS = 1, LFXT1Sx = 3 24/

2.2 V/3 V

2.2 V/3 V

40

50

60

40

50

60

30

2.2 V
3V

Internal: SMCLK, ACLK,
External: TACLK, INCLK,
Duty cycle = 50% ±10%TA0, TA1, TA2

2.2 V/3 V

2.2 V/3 V

%

300

kHz

10
16

MHz

20

2.2 V
3V

Internal: SMCLK, ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
TB0, TB1, TB2

pF

ns
10
16

MHz

20

ns

CODE IDENT NO.
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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions
2/

VCC
Min

-55°C ≤ TA ≤ 125°C
unless otherwise specified
USCI (UART mode)
USCI input clock frequency

fUSCI

BITCLK clock frequency(equals baud rate in MBaud)UART receive deglitch time 28/

LimitsTyp

Max

Internal: SMCLK, ACLK, External:
TBCLK,
Duty cycle = 50% ±10%fSYSTEM

fBITCLK

2.2 V/3 V

tζ

2.2 V
3V

50
50

2.2 V
3V
2.2 V
3V
2.2 V
3V

110
75
0
0

USCI (SPI Master mode) See figure 10
USCI input clock frequency
tSU,MISOMI input data hold time

tHD,MISIMO output data validtVALID,MOUCLK edge to SIMO valid,
CL = 20 pF

USCI (SPI Slave mode) See figure 11
STE lead time, STE low to clocktSTE,LEAD
STE lag time, last clock to STE hightSTE,LAG
STE access time, STE low to SOMItSTE,ACC
data out
STE disable time, STE high to SOMItSTE,DIS
high impedance
SIMO input data setup time

tSU,SISIMO input data hold time

tHD,SISOMI output data validtVALID,SO

USCI (I2C mode) See figure 12
USCI clock frequency

fUSCI

SCL clock frequency
Hold time (repeated) STARTfSCLtHD,STA

Setup time for a repeated STARTtSU,STA

Data hold time
Data setup time
Setup time for STOP

tHD,DATtSU,DATtSU,STO

2.2 V/3 V
2.2 V/3 V
2.2 V/3 V

150
150

600
600

UCLK edge to SOMI valid,
CL = 20 pF

fSYSTEM MHz
ns

50

ns

10
50
50
20
15
10
10
75
50

Internal: SMCLK, ACLK, External: UCLK,
Duty cycle = 50% ±10%11075fSYSTEM
2.2 V/3 V
2.2 V/3 V

fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz

2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V

ns

30
20

2.2 V/3 V
2.2 V
3V
2.2 V
3V
2.2 V
3V

MHz

1

SMCLK, ACLK, Duty cycle = 50% ±10%

SOMI input data setup time

Unit

0
4.0
0.6
4.7
0.6
0
250
4.0

MHz
400

µs

ns
µs

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions
2/
unless otherwise specified

TA

USCI (I2C mode) - Continued
Pulse width of spikes
tSP
suppressed by input filter-55°C to 125°C

10 Bit ADC, Power supply and input range conditions
Analog supply voltage
VCC
VSS = 0 V
range 30/VAx
All Ax terminal,
Analog input voltage range
Analog input selected in ADC10AE
register
fADC10CLK = 5.0 MHz,IADC10
ADC10ON = 1, REFON = 0,
ADC10 supply current 31/
ADC10SHT0 = 1, ADC10SHT1 = 0,
ADC10DIV = 0
fADC10CLK = 5.0 MHz,ADC10ON = 0, REF2_5 = 0,
IREF+
Reference supply current,
REFON = 1, REFOUT = 0
reference buffer disabled
fADC10CLK = 5.0 MHz,32/
ADC10ON = 0, REF2_5 = 1,
REFON = 1, REFOUT = 0
fADC10CLK = 5.0 MHz, ADC10ON = 0,
Reference buffer supply
IREFB,0
REFON= 1,REF2_5 = 0,
current with ADC10SR = 0
32/
REFOUT = 1, ADC10SR = 0
fADC10CLK = 5.0 MHz, ADC10ON = 0,
Reference buffer supply
IREFB,0
REFON= 1,REF2_5 = 0,
current with ADC10SR = 1
32/
REFOUT = 1, ADC10SR = 0
Input capacitanceCI
Only one terminal Ax selected at atime
Input MUX ON resistanceRI
0 V ≤ VAX ≤ VCC

VCC

2.2 V
3V

-55°C to 125°C

Limits

Unit

Min

Typ

Max

50
50

150
150

600
600

ns

2.2

3.6

V

0

VCC

V

mA

2.2 V

0.52

1.05

3V

0.6

1.2

-55°C to 125°C

2.2 V/3 V

0.25

0.4

-55°C to 125°C

3V-55°C to 85°C
125°C

2.2 V/3 V
2.2 V/3 V

1.1

1.4
1.8

-55°C to 85°C
125°C

2.2 V/3 V

0.5

0.7

-55°C to 125°C

2.2 V/3 V

2.2 V/3 V

0.8
27

pF

2000

Ω

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions
2/

VCC

LimitsMin-55°C ≤ TA ≤ 125°C
unless otherwise specified

Typ

Unit
Max

10 Bit ADC, Built in voltage reference
Positive built in reference
analog supply voltage range

VCC,REF+

Positive built in reference
voltage

VREF+

Maximum VREF+ load current

ILD,REF+

VREF+ load regulation

VREF+ load regulation response
time
Maximum capacitance at pin
VREF+ 33/

CVREF+

Temperature coefficient

TCREF+

Setting time of internalreference voltage 34/

tREFONIVREF+ ≤ 1 mA, REF2_5V = 0
IVREF+ ≤ 0.5 mA, REF2_5V = 1
IVREF+ ≤ 1 mA, REF2_5V = 1
IVREF+ ≤ IVREF+max, REF2_5V = 0
IVREF+ ≤ IVREF+max, REF2_5V = 1

2.2 V/3 V
3V

V

1.5
2.5

1.59
2.65

2.2 V
3V
IVREF+ = 500 µA ±100 µA,
Analog input voltage VAx ≈ 0.75 V, REF2_5V = 0
IVREF+ = 500 µA ±100 µA,
Analog input voltage VAx ≈ 1.25 V, REF2_5V = 1
IVREF+ = 100 µA to 900 µA
ADC10SR = 0
VAx ≈ 0.5 x VREF+ , Error
ADC10SR = 1
conversion result ≤ 1 LSB
IVREF+ ≤ 1 mA,
REFON = 1, REFOUT = 1
IVREF+ ≤ const. with 0 mA ≤ IVREF+ ≤ 1 mA

Positive external reference
input voltage range 36/

VeREF+

Negative external reference
input voltage range 38/
Differential external reference
input voltage range,∆VeREF = VeREF+ - VeREF-

VeREF-

IVREF+ = 0.5 mA,
REF2_5V = 0, REFON = 0 to 1
IVREF+ = 0.5 mA,
ADC10SR = 0
REF2_5V = 0, REFON = 1,
ADC10SR = 1
REFBURST = 1
IVREF+ = 0.5 mA,
ADC10SR = 0
REF2_5V = 0, REFON = 1,
ADC10SR = 1
REFBURST = 1
VeREF+ > VeREF-, SREF1 = 1, SREF0 = 0
VeREF- ≤ VeREF+ ≤ VCC – 0.15 V,
SREF1 = 1, SREF0 = 1
37/
VeREF+ > VeREF-∆VeREF

VeREF+ > VeREF-

Static input current into VeREF-

IVeREF+

Static input current into VeREF-

IVeREF-

0 V ≤ VeREF+ ≤ VCC,SREF1 = 1, SREF0 = 0
0 V ≤ VeREF+ ≤ VCC – 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 137/
0 V ≤ VeREF- ≤ VCC

Setting time of reference buffer tREFBURST
34/

2.2
2.8
2.9
1.41
2.35

±0.5
±1
±2

mA
LSB

±2
400

ns

2000
2.2 V/3 V

100

pF

2.2 V/3 V

±100

3.6 V

30

ppm/°C
µs

2.2 V

1
2.5

3V

2
4.5

39/

1.4
1.4

VCC
3.0

0

1.2

1.4

VCC

V

2.2 V/3 V
2.2 V/3 V

±1
0

µA

2.2 V/3 V±1CODE IDENT NO.
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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions
2/

VCC
Min

-55°C ≤ TA ≤ 125°C
unless otherwise specified
10 Bit ADC, Timing parameters
ADC10 input clock frequency
fADC10CLKADC10 built in oscillator
frequency

fADC10OSC

Conversion timetCONVERT

Turn on setting time of ADC
tADC10ON
40/
10 Bit ADC, Linearity parameters
Integral linearity error
EI
Differential linearity error
ED
Offset error
EO

Gain error

Total unadjusted error.
See footnotes at end of table.

EGET

For specified performance of
ADC10 linearity parameters

Limits
Typ

Unit
Max

ADC10SR = 0

2.2 V/3 V

0.45

6.5

ADC10SR = 1
ADC10DIVx = 0, adc10SSELx = 0,
fADC10CLK = fADC10OSC
ADC10 built in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
fADC10CLK from ACLK, MCLK, or
SMCLK: ADC10SSELx ≠ 0

2.2 V/3 V

0.45

1.5

2.2 V/3 V

3.25

6.45

2.2 V/3 V

2.06

3.51

µs

13 = ADC10DIVx
1/fADC10CLK
100ns

Source impedance RS < 100 Ω
SREFx = 010, un-buffered external reference,
VeREF+ = 1.5 V
SREFx = 010, un-buffered external reference,
VeREF+ = 2.5 V
SREFx = 011, buffered external reference,
VeREF+ = 1.5 V
42/
SREFx = 011, buffered external reference,
VeREF+ = 2.5 V
42/
SREFx = 010, un-buffered external reference,
VeREF+ = 1.5 V
SREFx = 010, un-buffered external reference,
VeREF+ = 2.5 V
SREFx = 011, buffered external reference,
VeREF+ = 1.5 V
42/
SREFx = 011, buffered external reference,
VeREF+ = 2.5 V
42/

DEFENSE SUPPLY CENTER, COLUMBUS
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2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V

±1.1

±1
±1
±1
±2

3V

±1.1

±2

2.2 V

±1.1

±4

3V

±1.1

±3

2.2 V

±2

±5

3V

±2

±5

2.2 V

±2

±7

3V

±2

±6

MHz

LSB

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions
2/

VCC

Sensor offset voltage

TCSENSOR

ADC10ON = 1, INCHx = 0Ah

VOffset,Sensor

ADC10ON = 1, INCHx = 0Ah 44/
Temperature sensor voltage at ≤ TA = 125°C(T version only)
Temperature sensor voltage at TA = 85°C

Sensor output voltage 45/

Sample time required if channel
10 is selected 46/

tSensor(sample)

Current into divider at channel
11 47/IVMID

VCC divider at channel 11

VMID

Sample time required if channel
11 is selected 48/

tVMID(sample)

44/

Temperature sensor voltage at TA = 25°C
Temperature sensor voltage at TA = 0°C
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
ADC10ON = 1, INCHx = 0Bh
ADC10ON = 1, INCHx = 0Bh
VMID is ≈ 0.5 x VCC
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB

Operational Amplifier (OA) supply specifications
Supply voltage range
VCC
Fast mode
ICC
Supply current 49/
Medium mode
Slow mode
Power supply rejection ratio
PSSR
Noninverting.
See footnotes at end of table.

DEFENSE SUPPLY CENTER, COLUMBUS
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Max

2.2 V
3V
2.2 V/3 V

3.44

40
60
3.55

120
160
3.66

2.2 V/3 V

-100
1265

1365

100
1465

1195
985

1295
1085

1395
1185

895
30

995

1095

2.2 V/3 V

µA
mV/°C
mV
mV

µs

2.2 V
3V

NA
NA

µA
V

2.2 V

1.06

1.1

1.14

3V
2.2 V

1.46
1400

1.5

1.54

3V

1220

ns

2.2
2.2 V/3 V

SIZE
A

Unit

Min

-55°C ≤ TA ≤ 125°C
unless otherwise specified
10 Bit ADC, Temperature Sensor and Built in VMID
Temperature sensor supply
ISENSORREFON = 0, INCHx = 0Ah, TA = 25°C
current 43/

Limits

180
110
50
70

3.6
290
190
80

V
µA

dB

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions
2/

VCC-55°C ≤ TA ≤ 125°C
unless otherwise specified
Operational Amplifier (OA) Input/Output specifications
Input voltage range
VI/P-55°C ≤ TA ≤ 55°C
Ilkg
Input leakage current 50/
55°C ≤ TA ≤ 85°C
51/
85°C ≤ TA ≤ 125°C
Fast mode
Medium mode fV(I/P) = 1 kHz
Vn
Voltage noise density, I/P
Slow mode
Fast mode
Medium mode fV(I/P) = 10 kHz
Slow mode
Offset voltage, I/P
VIO
Offset temperature drift, I/P
52/
Offset temperature drift with
supply, I/PHigh level output voltage, O/P

VOH

Low level output voltage, O/P

VOL

Output resistanceSee figure 13

53/

Common mode rejection ratio

RO/P(OAx)

Limits

2.2 V/3 V

Min

Typ

Max

-0.1
-15
-20

±0.5
±5

VCC – 1.2
15
20

-100

100
nV/
Hz

2.2 V/3 V

±10
±10
±1.5
VCC – 0.2
VCC – 0.1
VSS
VSS

mV
µV/°C
mV/V

VCC
VCC
0.2
0.1

V

150
150

Ω

0.1

CMR
R
Operational Amplifier (OA) Dynamic specifications
Fast mode
Slew rate
SR
Medium mode
Slow mode
Open loop voltage gain
Phase margin
CL = 50 pF
Gain margin
Noninverting, Fast mode, RL = 47 kΩ, CL = 50 pF 2.2 V/3 V
Noninverting, Medium mode,
GBW RL = 300 kΩ, CL = 50 pF
Gain bandwidth productSee figure 14
Noninverting, Slow mode,
RL = 300 kΩ, CL = 50 pF
Enable time onten(on)ton, noninverting, Gain = 1
Enable time offten(off).
See footnotes at end of table.

SIZE
A

V
nA

50
80
140
30
50
65

0.3 V ≤ VIN ≤ VCC – 1.0 V,∆VCC ≤ ±10%, TA = 25°C
Fast mode, ISOURCE ≤ -500 µA
Slow mode, ISOURCE ≤ -150 µA
Fast mode, ISOURCE ≤ 500 µA
Slow mode, ISOURCE ≤ 150 µA
RLoad = 3 kΩ, CLoad = 50 pF, VO/P(OAx) < 0.2 V
RLoad = 3 kΩ, CLoad = 50 pF,
VO/P(OAx) > VCC – 1.2 V
RLoad = 3 kΩ, CLoad = 50 pF,
0.2 V ≤ VO/P(OAx) ≤ VCC – 1.2 V
Noninverting

DEFENSE SUPPLY CENTER, COLUMBUS
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Unit

70

dB

1.2
0.8
0.3
100
60
20
2.2
1.4

V/µs

dB
deg
dB
MHz

0.5
10

20
1

µs

CODE IDENT NO.
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18

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolTA

Conditions
2/
unless otherwise specified

VCC

LimitsMin

Operational Amplifier (OA) Feedback network, Resistor network 54/
Total resistance of resistor
RtotalstringUnit resistor of resistor
Runit
string 55/
Operational Amplifier (OA) Feedback network, Comparator mode (OAFCx = 3)
OAFBRx = 1, OARRIP = 0-55°C to 125°C 2.2 V/3 V
OAFBRx = 2, OARRIP = 0-55°C to 125°C
OAFBRx = 3, OARRIP = 0-55°C to 125°C
OAFBRx = 4, OARRIP = 0
OAFBRx = 5, OARRIP = 0
OAFBRx = 6, OARRIP = 0
VLevelComparator level
OAFBRx = 7, OARRIP = 0
OAFBRx = 1, OARRIP = 1-55°C to 125°C
OAFBRx = 2, OARRIP = 1-55°C to 125°C
OAFBRx = 3, OARRIP = 1-55°C to 125°C
OAFBRx = 4, OARRIP = 1
OAFBRx = 5, OARRIP = 1
OAFBRx = 6, OARRIP = 1-55°C to 125°C-55°C to 125°C-55°C to 125°C
OAFBRx = 7, OARRIP = 1-55°C to 125°C
Fast mode, Overdrive 10 mV
2.2 V/3 V
Fast mode, Overdrive 100 mV
Fast mode, Overdrive 500 mV
tPLH,
Propagation delay
Medium mode, Overdrive 10 mVtPHL(low high and high low)
Medium mode, Overdrive 100 mV
Medium mode, Overdrive 500 mV
Slow mode, Overdrive 10 mV
Slow mode, Overdrive 100 mV
Slow mode, Overdrive 500 mVOperational Amplifier (OA) Feedback network, Noninverting Amplifier Mode (OAFCx = 4)
OAFBRx = 0-55°C to 125°C 2.2 V/3 V
OAFBRx = 1-55°C to 125°C
OAFBRx = 2-55°C to 125°C
Gain
G
OAFBRx = 3-55°C to 125°C
OAFBRx = 4-55°C to 125°C
OAFBRx = 5-55°C to 125°C
OAFBRx = 6-55°C to 125°C
OAFBRx = 7-55°C to 125°C
Total harmonic
THD
All gains
2.2 V
distortion/nonlinearity
3V
Setting time 57/
tSettleAll power modes
2.2
V/3 V
-55°C to 125°C
See footnotes at end of table.

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO

SIZE
A

Unit

Typ

Max

96

kΩ

6

0.242

0.25

0.262

0.492
0.619

0.5

0.512
0.639

0.057

N/A 56/
N/A 56/
N/A 56/
N/A 56/
0.0625

0.071

0.122
0.182

0.125
0.187

0.128
0.197

0.242
0.367
0.492

0.25
0.375
0.50

0.262
0.383
0.512

VCC

N/A 56/
40
4
3
60
6
5
160
20
15
0.970
1.325
1.985
2.638
3.94
5.22
7.76
15.0

µs

1.00
1.334
2.001
2.667
4.00
5.33
7.97
15.8

1.035
1.345
2.017
2.696
4.06
5.44
8.18
16.7

-60
-70
7

dB
12

µs

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

Conditions
TA
VCC
2/
unlessotherwise
specified
Operational Amplifier (OA) Feedback network, Noninverting Amplifier Mode (OAFCx = 6) 58/
OAFBRx = 1
2.2 V/3 V-55°C to 125°C
OAFBRx = 2-55°C to 125°C
Gain

SymbolGOAFBRx = 3
OAFBRx = 4
OAFBRx = 5
OAFBRx = 6

Total harmonic
distortion/nonlinearity

THD

Setting time 57/

tSettleFlash memory
Program and erase supply voltage
Flash timing generator frequency
Supply current from VCC during
program
Supply current from VCC during
erase
Cumulative program time 59/

Limits-55°C to 125°C-55°C to 125°C-55°C to 125°C-55°C to 125°C

OAFBRx = 7
All gains-55°C to 125°C

All power
modes-55°C to 125°C

Unit

Min

Typ

Max

-0.385-1.023-0.335-1.002-0.305-0.979-1.712-3.10-1.668-3.00-1.624
-2.90

-4.51
-7.37

-4.33
-6.97

-4.15
-6.57

-16.6

-14.8
-60
-70
7

-13.1

2.2 V
3V
2.2 V/3 V

dB

2.2

12

µs

3.6

V

VCC(PGM/ERASE)-55°C to 125°C

fFTG
IPGM

-55°C to 125°C-55°C to 125°C

2.2 V/3.6 V

1

476
5

kHz
mA

IERASE-55°C to 125°C

2.2 V/3.6 V

1

10.5

mA

2.2 V/3.6 V

10

ms

257

tCPT

-55°C to 125°C

Cumulative mass erase time
Program/Erase endurancetCMErase-55°C to 125°C-55°C to 125°C

Data retention duration 60/
Word or byte program time
Block program time for 1st byte or
word
Block program time for each
additional byte or word
Block program end-sequence wait
time
Mass erase time
Segment erase timeRAM
RAM retention supply voltage
62/.
See footnotes at end of table.

tRetention
tWord
tBlock, 0

TJ = 25°C
61/
61/

tBlock, 1-63

61/

18

tBlock, End61/

6tMass ErasetSeg Erase

61/
61/

10593
4819

V(RAMh)CPU halted

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20
104

ms
cycles

105

100

yeras
tFTG

30
25

1.6

-55°C to 125°C

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

JTAG and Spy-Bi-Wire interface
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse length
Spy-Bi-Wire enable time
(Test high to acceptance of first clockedge 63/)
Spy-Bi-Wire return to normal operationtime
TCK input frequency 64/
Internal pulldown resistance on TESTJTAG Fuse 65/
Supply voltage during fuse-blow
condition
Voltage level on TEST for fuse blow
Supply current into TEST during fuseblow
Time to blow fuse

SymbolConditions
2/
unless otherwise
specifiedTA

VCC

LimitsMin

fSBWtSBW,LowtSBW,En-55°C to 125°C-55°C to 125°C

Unit

Typ

Max

0
0.025

-55°C to 125°C

2.2 V/3 V
2.2 V/3 V
2.2 V/3 V

20
15
1tSBW,Ret-55°C to 125°C

2.2 V/3 V

15

100

fTCK

-55°C to 125°C

RInternal-55°C to 125°C

2.2 V
3V
2.2 V/3 V

0
0
25

5
10
90

VCC(FB)

25°C

2.5

VFB

-40°C to 125°C

6

IFB
tFB

60

MHz
µs

MHz
kΩ
V

7

V

-40°C to 125°C

100

mA

-40°C to 125°C

1

ms

1/

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may notnecessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
2/ Over recommended ranges of supply voltage and operating free air temperature (unless otherwise noted).
3/ All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
4/ The current are characterized micro crystal. See manufacture data for more information.
5/ Current for brownout and WDT clocked by SMCLK included.
6/ Current for brownout and WDT clocked by ACLK included.
7/ Current for brownout included.
8/ RST/NMI limit values specified for -55°C to 125°C.
9/ An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger
signals shorter than t(int).
10/ The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
11/ The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor isdisabled.
12/ The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to hold the maximum voltage
drop specified.
13/ The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
14/ A resistive divider with 2 times 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of thedivider.

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TABLE I. Electrical performance characteristics – Continued.

1/

15/ The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
16/ The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-)+ Vhys(B_IT-) is ≤ 1.8 V.
17/ During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-), The default DCO settingsmust not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
18/ The DCO clock wake up time is measured from the edge of an external wake up signal (e.e., port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK)
19/ Parameter applicable only if DCOCLK is used for MCLK.
20/ ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C.
21/ To improve EMI on the LFXT1 oscillator the following guidelines should be observed:
a. Keep as short of a trace as possible between the device and the crystal.
b. Design a good ground plane around the oscillator pin.
c. Prevent crosstalk from other clock or data lines into oscillator pin XIN and XOUT.
d. Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
e. Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
f. If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between oscillator pins.
g. Do not rout the XOUT line to the JTAG header to support the serial programming adapter as shown in other data. This signal
is no longer required for the serial programming adapter.
22/ Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it isrecommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitanceshould always match the specification on the used crystal.
23/ Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
24/ Measured with logic level input frequency, but also applies to operation with crystals.
25/ Calculated using the box method:
I Version: [MAX(-55…85°C) – MIN(-55…85°C)]/ MIN(-55…85°C)]/[85°C – (-55°C)]
26/ Calculated using the box method:[Max(1.8…3.6V) – MIN(1.8…3.6 V)]/MIN(1.8…3.6 V)/(3.6 V – 1.8 V)
27/ Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
28/ Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that the pulses
correctly recognized, their width should exceed the maximum specification of the deglitch time.
29/ The leakage current is defined in the leakage current table with Px.x/Ax parameter.
30/ The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion result.
31/ The internal reference supply current is not included in current consumption parameter IADC10.
32/ The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10)N control bit, unless aconversion is active. The REFON bit enables the built in reference to settle before starting an A/D conversion.
33/ The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/VREF+/VeREF+ (REFOUT = 1),
must be limited; the reference buffer may become unstable otherwise.
34/ The condition is that the error in a conversion started after tREFON or tRefBuf is less than ±0.5 LSB.
35/ The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow therecommendations on analog source impedance to allow the change to settle for 10 bit accuracy.
36/ The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.

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TABLE I. Electrical performance characteristics – Continued. 1/
37/
38/
39/
40/
41/
42/
43/
44/
45/
46/
47/
48/
49/
50/
51/
52/
53/
54/
55/
56/
57/
58/
59/
60/
61/
62/
63/
64/
65/

Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer
supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be appliedwith reduced accuracy requirements.
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are
already settled.
2.2 V not production test.
The reference buffer’s offset adds to the gain and total unadjusted error.
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON =1 and INCH = 0Ah and sample signal ishigh). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature
sensor input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor (273+ T[°C]) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T[°C] + Vsensor(TA = 0°C) [mV]Results based on characterization and/or production test, not TCSensor or VOffet,sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor on time tSENSOR(on).
No additional current is needed. The VMID is used during sample.
The on time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
Corresponding pins configured as OA inputs and outputs, respectively.
ESD damage can degrade input current leakage.
The input bias current is overridden by the input leakage current.
Calculated using the box method.
Specification valid for voltage-follower OAx configuration.
A single resistor string is composed of 4 Runit + 4 Runit + 2 Runit + 2 Runit + 1 Runit + 1 Runit + 1 Runit + 1 Runit = 16 Runit = Rtotal
For the matching (i.e., the relative accuracy) of the unit resistor on a device, refer to the gain and level specifications of therespective configurations.
The level is not available due to the analog input voltage range of the operational amplifier.
The setting time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The
setting time of the amplifier itself might be faster.
This includes the 2 OA configuration “Inverting amplifier with input buffer”. Both OA needs to be set to the same power mode
OAPMx.
The cumulative program time must not be exceeded when writing to a 64 byte flash block. This parameter applies to all
programming methods: individual word/byte write and block write modes.
To test the fash data retention at various temperatures we make use of accelerated test on the flash with 500 hours baking time at
250°C. These tests are wholly based on Arrhenius law and equation. For more information refer to figure 15.
These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched
to bypass mode.

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Case X

SymbolA
A1
A2b

Dimension
Millimeters
Symbol
Min
Max
0.80
1.00
D/E
0.00
0.05
e
0.20 NOM
e1
0.18
0.30
S

Millimeters
Min
Max
5.85
6.15
0.50 BSC
4.50 BSC
0.30
0.50

NOTES:
1. All linear dimensions are in millimeters. Dimensioning and tolerance per ASME Y14.5 – 1994.
2. This drawing is subject to change without notice.
3. Quad flatpack, No-leads (QFN) package configuration.
4. The package thermal pad must be soldered to the board for thermal and mechanical performance. See manufacturer data for
details regarding the exposed thermal pad dimensions.
5. Package complies to JEDEC MO-220 variation VJJD-2.
FIGURE 1. Case outline.

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Case Y

SymbolA
A1bc
D

Dimension
Millimeters
Symbol
Min
Max
1.20
E
0.05
0.15
E1
0.19
0.30
e
0.15 NOM
L
12.40 12.60

Millimeters
Min
Max
6.00
6.20
7.90
8.30
0.65 BSC
0.50
0.75

NOTES:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 mm per side.
4. Fall within JEDEC MO-153.

FIGURE 1. Case outline - Continued.

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Terminal
number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Terminal
number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

Terminal symbol
DVSS
XOUT/P2.7
XIN/P2.6
DVSS
RST/NMI/SBWTDIO
P2.0/ACLK/A0/OA0O
P2.1/TAINCLK/SMCLK/A1/OA0O
P2.2/TA0/A2/OA0I1
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
AVSS
AVCC
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.0/TB0/A12/OA0O
P4.4/TB1/A13/OA1O
P4.5/TB2/A14/OA0I3

Terminal symbol
TEST/SBWTCK
DVCC
P2.5/Rosc
DVSS
XOUT/P2.7
XIN/P2.6
RST/NMI/SBWTDIO
P2.0/ACLK/A0/OA0I0
P2.1/TAINCLK/SMCLK/A1/OA00
P2.2/TA0/A2/OA0I1
P3.0/UCB 0STE/UCA 0CLK/A5
P3.1/UCB 0SIMO/UCB 0SDA
P3.2/UCB 0SOMI/ UCB 0SCL
P3.3/UCB 0CLK/UCA 0STE
AVSS
AVCC
P4.0/TB0
P4.1/TB1
P4.2/TB2

Case outline X
Terminal
number
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Case outline Y
Terminal
number
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

Terminal symbol
P4.6/TBOUTH/A15/OA1I3
P4.7/TBCLK
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA/0SOMI
P3.6/A6/OA0I2
P3.7/A7/OA1I2
P2.3/TA1/A3/VREF-/VeREF-/OA1I1/OA10
P2.4/TA2/A4/VREF+/VeREF+/OA1I0
P1.0/TACLK/ADC10CLK
P1.1/TA0
P1.2/TA1
P1.2/TA2
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI/TCLK
P1.7/TA2/TDO/TDITEST/SBWTCK
DVCC
DVCC
P2.5/Rosc

Terminal symbol
P4.3/TB0/A12/OA0O
P4.4/TB1/A13/OA1O
P4.5/TB2/A14/OA1I3
P4.6/TBOUTH/A15/OA1I3
P4.7/TBCLK
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SIMO
P3.6/A6/OA0I2
P3.7/A7/OA1I2
P2.3/TA1/A3/VREF-/VeREF-/OA1I1/OA10
P2.4/TA2/A4/VREF+/VeREF+/OA1I0
P1.0/TACLK/ADC 10CLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI
P1.7/TA2/TDO/TDIFIGURE 2. Terminal connections.

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FIGURE 3. Functional block diagram.

FIGURE 4. Operating area.

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FIGURE 5. Active mode supply current.

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FIGURE 6. POR/Brownout reset.

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FIGURE 7. POR/Brownout reset.

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FIGURE 8. POR/Brownout reset.

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FIGURE 9. Test circuit and timing waveforms.

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FIGURE 10. Test circuit and timing waveforms.

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FIGURE 11. Test circuit and timing waveforms.

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FIGURE 12. Test circuit and timing waveforms.

FIGURE 13. Test circuit and timing waveforms.

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FIGURE 14. Test circuit and timing waveforms.

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FIGURE 15. Test circuit and timing waveforms.

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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee ofpresent or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current
sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

1/

Vendor item drawing
administrative control
number 1/

Devicemanufacturer
CAGE code

Vendor part number

V62/08631-01XE

01295

MSP430F2274MRHATEP

V62/08631-01YE

01295

MSP430F2274MDATEPThe vendor item drawing establishes an administrative control number for
identifying the item on the engineering documentation.

CAGE code

Source of supply

01295

Texas Instruments, Inc.
Semiconductor Group
8505 Forest lane
P.O. Box 660199
Dallas, TX 75243

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

V62/08631

REV

PAGE

D

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