Experimental Assessment of Logic Circuit
Performance Variability with Regular Fabrics at
90nm Technology NodeSungdae Choi, Katsuyuki Ikeuchi, Hyunkyung Kim, Kenichi Inagaki, Masami Murakata*, Nobuyuki Nishiguchi*,
Makoto Takamiya and Takayasu Sakurai
The University of Tokyo, Japan* Semiconductor Technology Academic Research Center (STARC), Japan(sungdae@iis.u-tokyo.ac.jp)
Abstract
Regular fabric structure is expected to reduce theprocess variations and increase the yield in sub-micron technology
regime. Few experimental assessments, however, for theeffectiveness of the regular structures has been carried out yet. In
this paper, three kinds of circuit blocks are implemented with fourkinds of layout styles with different regularity, and the effect ofregularity on the circuit performance variations is evaluated. A test
chip is fabricated with 90nm CMOS logic process and measured
results show that the regular structure increases average delay, andthe worst delay of the regular structure is not better than the worst
delay of normal circuits with irregular standard cells.

I.

specially-cared frequency dividers (FD). Since the variation ofeach device is averaged out as the number of the oscillation stage
increases [8], the oscillation frequencies of RO3, the shortest
number of oscillation stage, maximize the effect of the local
random variations. RO11s are measured in order to compare theeffect of the number of the logic stage. 16-bit ripple-carry adders
with best-effort clock operation show the results of practicalcircuit situations.
Fig. 1 shows the block diagram of RO3s and RO11s. ROsconsist of static logic gates such as NAND, NOR and inverter.
All ROs place neighbored to keep the layout regularity. And alledges of the regularity-considered area are filled with regulardummy patterns to prevent the systematic variations of edgeplaced samples. In the peripheral area, each FD with minimum
capacitive load is dedicated to a single RO to minimize theinterconnection load and preserve the RO’s characteristicfrequency. Once the frequency is divided and buffered, it passes
through the shared dividing path which consists of FD and XORgates. External address activates only one RO at a time, andcorresponding frequency passes through the shared dividing
blocks. Shared dividing path of RO3, RO11 and adder has 10, 7and 6 FDs, respectively, so that the generated frequencies showorder of MHz range from the pad and are easy to measure withoff-chip measurement.

INTRODUCTION

Performance variations due to the device mismatches andrandom process parameters are crucial problems to reduce thechip cost as the technology scales down to deep submicron.
Many researches find out the source of the variations [1, 2, 3],
and regular fabric structure is expected to be one of the promisingsolutions [4, 5, 6] in the circuit design level. There are, however,few researches on how much regular structures are attractivefrom the variation and performance point of view, althoughlayout is revealed to have huge impact on lithography-inducedvariability [7]. This work focuses on the effect of the layout
regularity on the performance and variations of the chip.
TEST STRUCTURES WITH VARIOUS LAYOUT STYLES

FDII.

...
FD

FD

FD

FD

7bit

978-1-4244-2361-3/08/$25.00 ©2008 IEEE.

Address Decoder

3- and 11-stage ring oscillators (RO3, RO11) with four layout
patterns, composition of regular and irregular MOSFET fabricstructure and interconnections, are implemented. And the effectsof the regularity on the circuit performance and variation are
analyzed by measuring the oscillation frequency of each RO. The
oscillation frequency is determined only by the devices whichconstruct the RO chain. And the frequency is more robust to
noise than voltage and current. Adders with best-effort clock
operation are also implemented with various layout patterns tosurvey the performance and variations in practical logic which ismore complicated than simple ROs. They are design to generate
periodic signal as soon as they finish the calculation so that themeasured frequency distributions represent the performance andvariations. Each of RO and adder patterns has 128 and 64
samples, respectively, and the frequency is measured using

Fig. 1 Block diagram of ROs structure (16 clusters x 8 ROs)

50

The FD with minimum capacitive load shown in the Fig. 2 isrequired to catch the oscillation frequency of RO3 which
generates order of gigahertz oscillation range. The simple DFlip/Flop-based FD divides up to 8-GHz signal by two on thepost-layout simulation. Due to its simplicity and the layout
considering minimum parasitic capacitance, it consumes 0.14mW
power with 4.7GHz input frequency. Measured data show that it
successfully divides average 4.7GHz of RO3 oscillation
frequency.

height of RT is 27% higher than that of iRT, as is found in otherRT designs [5]. For regular interconnection, all the widths andspaces use minimum design rule regulations, and dummy metalbars are inserted in the empty area. For irregular interconnections,metals have various widths and no dummy bars are used.
Fig. 5 shows equivalent schematics of RO3 and RO11 withRT and iRT patterns. SOG using gate-isolation method causes
redundant MOSFETs between logic gate separations as shown inthe Fig. 5 (a) and (c). SOG using oxide-isolation eliminates such
redundancy, but it doesn’t guarantee the diffusion regularity. Sizeof all transistors is the same in all ROs, while size of transistors
in adders varies. Core area overhead of RO3, RO11 and adderblock with RT design style increases 25%, 28% and 85%
compared with those of iRT implementations, respectively.

Fig. 2 Minimum capacitive load frequency dividerFig. 3 shows the block diagram and operation flow of thebest-effort clock operation adder. It executes two calculations,critical-path calculation and recovery calculation so that the MSB
carry-out generates oscillatory signal.

0x00010xFFFF

0 1

S<15>

ADDER16COUT

CLKGEN
D
DFF16
INIT
Q
STARTER(a) Best-effort clock adder

START

SINIT = 0x7FFF
S + A = S’
1. 07FFF + 00001 = 08000(Critical-path Calculation)
2. 08000 + 0FFFF = 17FFF(Recovery Calculation)
3. 17FFF + 00001 = 18000(Critical-path Calculation)
4. 18000 + 0FFFF = 07FFF(Recovery Calculation)
5. 07FFF + 00001 = 08000(Critical-path Calculation)

Fig. 4 Regular/Irregular Transistor/Interconnection layout(b) Operation flow

Fig. 3 Adder with best-effort clock operation

Each RO and adder block is implemented with four kinds oflayout styles, namely regular transistor layout (RT) with regularinterconnections (RI), RT with irregular interconnections (iRI),irregular transistor (iRT) with RI, and iRT with iRI. Fig. 4 shows
the layout regularity of each style. RT is implemented with theSea-of-Gates (SOG) design style using gate-isolation method asshown in the Fig. 4 (a) to keep the pattern of all MOSFETs equal,
while iRT is implemented with normal standard cells. The cellFig. 5 RO schematics with RT and iRT layouts

51

Fig. 6 shows the test chip implemented with 90nm CMOS
logic process. 11 kinds of patterns are implemented in 1.6mm x0.9mm core area. For ROs, each layout style has 128 samples andadder block has 64 samples for each style on a chip. Frequenciesof 11 dies, 1216 samples for each die, are automaticallymeasured using LabVIEW [9], and analyzed to figure out theperformance variations.

Cycle Time [ns]which makes noisier environments. The increase of average delay
time in RT is mainly due to the area increase and correspdoingload increase.

Fig. 6 Measured test chipIII.

CYCLE TIME DISTRIBUTIONS

Fig. 7 distributes the average cycle time (μ) and its 3σ(standard deviation) of 11 test chips. For RO3 shown in Fig. 7 (a),composition of RT and RI shows the largest μ, and iRT+iRI
shows the shortest μ among 4 different layout styles. With thesame transistor layout style, that is, if RT or iRT is fixed, RI is
3% slower than iRI. And RT is 18% and 17% slower than iRTwith the same RI and iRI, respectively. The 3σ range is similar toeach other, regardless of the layout regularity. This is because therandom dopant fluctuation dominates the variation, which can not
be controlled by layout style.

8.0
6.4

In RO11 shown in Fig. 7 (b), average of RT is 23% and 24%slower than iRT in equal RI and iRI condition, respectively. And
RI is 1% and 2% slower than iRI with RT and iRT condition,respectively. Again the random dopant fluctuation dominates thevariation, which is independent from the layout styles. For all 11
test chips, worst cycle time of iRTs doesn’t exceed that of best
cycle time of RT, which means that the regular fabrics does notshow any advantage over normal standard cell approach in both
worst-case performance and area.

4.8
3.2
1.6Since the blocks in adders run asynchronously to generate aclock, it happens to be very sensitive to glitch noise. Thisphenomenon unexpectedly acts as a performance variability
magnifier. With the help of these magnifying effects, RT styles
show much larger variation than iRT counterpart, as shown in Fig.
7 (c). RT design style has more coupling capacitance among lines,

0.0#10 #11 #14 #17 #18 #20 #21 #02 #06 #07 #09(c) Adder block
Fig. 7 Average and 3s variation error bar of measured cycle time.
Numbers on x-axis indicates the chip number.

52

IV.

Normalized variation (σ/μ) increases as VDD decreases, asseen in Fig. 8. But the conclusion that regular fabric does not help
improve the worst-case performance is unchanged as is shown inFig. 9 which depicts variation at 0.7V VDD.

CONCLUSIONS/ [%]Three kinds of circuits are implemented with four layoutstyles with different regularities and the oscillating frequencies
are measured to investigate the effect of regular structures on theperformance. Regular transistor fabric significantly degrades theperformance due to its larger parasitic capacitance but doesn’t
reduce the variations, since the variations mostly come from therandom dopant effects. Regular interconnection fabric shows
negligible performance reduction with no variation reduction.
Thus, the regular fabric does not help improve the worst-caseperformance.

ACKNOWLEDGEMENT/ [%]This work is partially supported by STARC. The VLSI chips
were fabricated through the chip fabrication program of VLSI
Design and Education Center (VDEC), the University of Tokyo,
with the collaboration by STARC, Fujitsu Limited, Matsushita
Electric Industrial Company Limited., NEC Electronics
Corporation, Renesas Technology Corporation, and Toshiba
Corporation.

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Fig. 8 Normalized variation (σ/μ) of ROs at various VDD
[2]
[3]

[4]
[5]
[6]
[7]
[8]

[9]

Fig. 9 Delay and 3σ error bar of ROs at 0.7V VDD

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