LUPO TimeStamp Module (Ver. 1.6)
Hidetada Baba
September 8, 2014

11 General

1 General
1.1

Function

This module is a CAMAC/VME LUPO module which including the functions of Time
stamp, Output register and Interrupt register.

1.2Time stamp

Time-stamp values are obtained with a 48 bits depth and a 10 ns resolution according
to the trigger input (NIM IN1). It can be stored up to 1024 events into FIFO memory.
In ﬁrmware version 1.6, the only external clock mode is available. To use internal clock,connect NIM output ch2 and NIM input ch3. In case of external clock, 100 MHz clock isgenerated by DLL (Delay Lock Loop) circuit from 25 MHz external clock of NIM input
ch3. The clear input (NIM IN2) reset the time-stamp value. By using this clear signal,
the synchronization for all modules are achieved.

1.3

Output register

By the output register function, this module can output pulse and level signals fromNIM OUT0–1. The pulse width is ﬂexible, and it can be changed from 20 ns – 1.3 ms
with 20 ns resolution.

1.4

Interrupt register

NIM IN0 input provides the interrupt signal to CAMAC and VME bus. The interrupt
delay, which is a delay time between the signal timing and the interrupt generation timing,
can be set from 20 ns to 1.3 ms with 20 ns step. The interrupt is generated when thenumber of interrupt signals in the memory equals the value written in the Interrupt
Counter Register.

121 General

1.5

Indicator

1.6

Connector

1.6.1

NIM input ch0 : Interrupt/Busy inCAMAC/VME interrupt signal is generated by this interrupt input. More than 20 ns
width logic pulse is required. When the use busy chain is ’1’, this input channel is used
for an external busy input.

1.6.2

NIM input ch1 : Trigger

Time stamp values are stored into FIFO according to this trigger input. More than 30
ns width logic pulse is required. This minimum pulse width can be changed by setting
the Trigger Width If the Interrupt Source register is ’1’, this trigger input is also used as
an interrupt input.

1.6.3

NIM input ch2 : Time ResetWith this input, time stamp values are cleared to 0. This input is for the module
synchronization. More than 20 ns width logic pulse is required.

1.6.4

NIM input ch3 : External Clock

Input 25MHz external clock.

1.6.5

NIM output ch0 : Output 0

An output for NIM level and pulse.

1.6.6

NIM output ch1 : Output 1/Busy output

An output for NIM level and pulse. When the use busy chain is ’1’, this output channel
is used for a busy output.

1.6.7

NIM output ch2 : Int clock throughAn output of internal 25 MHz clock which is based on internal 50 MHz clock. Thissignal is used for synchronizing other modules.
231.6.8

1 General

NIM output ch3 : External clock output

Generate 25MHz clock from external clock input. This clock is used to to check theexternal clock is accepted or not. Also, to synchronize other LUPO timestamp modules,
this external clock output is used.

1.7

Block diagram㻲㻼㻳㻭
25 MHzExternal clock
DLL
External
100 MHz clockClear

48 bitCounter
FIFO

Trigger48 bitx2047 cell

Latch

VME/CAMAC
Interface

3

4

1.8

1 General

Front panel

Ex Clock OK : 0
Trigger : 2
Reset input : 4
FIFO Full : 6

1 : Module access
3 : Int/Ext clock mode
5 : Software Veto
7 : Interrupt generateInterrupt/Busy inTrigger
Time ResetExternal Clock

NIM output 0ch
NIM output 1ch/Busy out
Int clock throughTrigger through4

5

2 Interface

2 Interface
2.1

Register map

CAMAC (R/W)
F(0)A(0)F(0)A(2)F(0)A(4)F(0)A(6)F(1)A(0)F(1)A(2)F(1)A(4)F(2)A(0)F(2)A(4)F(16)A(0)F(17)A(0)F(4)A(0) F(20)A(0)F(4)A(1) F(20)A(1)F(4)A(2) F(20)A(2)F(4)A(4) F(20)A(4)F(4)A(5) F(20)A(5)F(7)A(0)F(9)A(0)F(9)A(1)F(9)A(2)F(9)A(3)F(9)A(4)F(24)A(0)F(26)A(0)VME
Base + %00
Base + %04
Base + %08
Base + %0c
Base + %10
Base + %14
Base + %18
Base + %20
Base + %28
Base + %00
Base + %10
Base + %40
Base + %42
Base + %44
Base + %48
Base + %4a
Base + %70
Base + %90
Base + %92
Base + %94
Base + %96
Base + %98
Base + %80
Base + %A0Register
Data 24 bits lower
Data 24 bits higher
Data 32 bits lower
Data 32 bits higherTrigger Counter
FIFO Counter
Data on the ﬂy
Data sequential
Clock 10k
Level Output
Pulse Output
Pulse Width
Interrupt Delay
Interrupt Counter
Interrupt Source
Use busy chain
Module version
Clear FIFO & Interrupt
Reset Time Stamp
Clear Trigger Counter
Clear All
Clear Interrupt
Disable Interrupt
Enable Interrupt

5

Data
D16
D16
D16
D16
D32
D32
D32
D32
D32
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16

VME R/W
read
read
read
read
read
read
read
read
read
write
write
read/write
read/write
read/write
read/write
read/writeread
read
read
read
read
read
write
write

62 Interface

2.1.1

Data on the fly

Return the current time stamp counter (higher 24 bits).

2.1.2

Trigger Counter

Return the number of trigger input. The data depth is 32 bits for VME, 24 bits forCAMAC. By access of Clear Trigger Counter Register, this value will be cleared.

2.1.3

Level Output

Output level signals from NIM Output connectors (1=on, 0=oﬀ).
1514

2.1.4

13121110987

654321ch10ch0Pulse Output

Output pulse signals from NIM Output connectors (1=on, 0=oﬀ). With this pulse
signal, level output will be canceled.
152.1.51413121110987654321ch10ch0Pulse WidthSet the width of the pulse output signal. 1 point corresponds to 20 ns. The default
value is 10 = 200 ns. The maximum value is 65536  1.3 ms.

2.1.6

Interrupt Delay

Set the delay time during interrupt input arrival time and actual interrupt generation.
1 point corresponds to 20 ns. The default value is 0 = 0 ns. The maximum value is 65536 1.3 ms.

6

72 Interface

2.1.7

Interrupt Counter

When the interrupt input (or trigger input when Interrupt source register is ’1’) reaches
this number, IRQ signal is generated. This resister accept up 0–2047 (0 corresponds to2048). If the value of use busy chain register is ’1’, busy signal is generated until interrupt
is cleared.

2.1.8

Interrupt Source

In the default setting, interrupt source is NIM input 0. When write ’1’ on this register,
the interrupt source is switched to the trigger input.

2.1.9

Use busy chain

When 0th bit has the value = ’1’, the busy chain mode is enabled. NIM input 0 is used
as external busy input. NIM output 1 is busy signal. The busy signal consist of OR of
external busy input, IRQ signal and 1th bit of this register. Once, interrupt occurs, thebusy signal is latched until clear interrupt. When 1th bit is ’1’, the busy signal is forced
to be high.
15142.1.10

13121110

987

654

32

10force useClear FIFO & Interrupt

Clear FIFO memory and interrupt signal. In case of VME, this function is invoked byread action.

2.1.11

Reset Time stamp

Reset the time stamp counter to 0. FIFO memory is also cleared. In case of VME, thisfunction is invoked by read action.

2.1.12

Clear Trigger Counter

Clear the trigger counter only. In case of VME, this function is invoked by read action.

7

82 Interface

2.1.13

Clear All

Clear FIFO memory, interrupt signal, the trigger counter. The time stamp counter isnot reset. In case of VME, this function is invoked by read action.

2.1.14

Clear Interrupt

Clear interrupt signal only. If CAMAC/VME interrupt signal is generated by thismodule, the clear interrupt function should be called from interrupt service routine. Incase of VME, this function is invoked by read action.

2.1.15

Disable Interrupt

Disable VME/CAMAC interrupt. In case of VME, this function is invoked by write
action. Any write value is acceptable.

2.1.16

Enable Interrupt

Enable VME/CAMAC interrupt. In case of VME, this function is invoked by write
action. Any write value is acceptable.

2.1.17

VersionReturn the version code of this module. The following is VME Time Stamp Ver 1.6case.
15141312CAMAC/VME
211109Module ID
287865Ver X.X
1432
1Ver X.X
60

93 Appendix

3 Appendix
3.1

Version Information

1.6 With FIFO, Interrupt count, Busy output, No Internal clock mode
1.5 50MHz LVDS external clock, Without FIFO
1.2 With FIFO
1.1 Without FIFO, stable version

9