LUPO TimeStamp Module (Ver. 1.2)
Hidetada Baba
November 28, 2009

11 General

1 General
1.1

Function

This module is a CAMAC/VME LUPO module which including the functions of Time
stamp, Output register and Interrupt register.

1.2Time stamp

Time-stamp values are obtained with a 48 bits depth and a 10 ns resolution according
to the trigger input (NIM IN1). It can be stored up to 1024 events into FIFO memory.
Both clock sources of internal and external are available. In case of external clock, 100
MHz clock is generated by DLL (Delay Lock Loop) circuit from 25 MHz external clockof NIM ch3. The clear input (NIM IN2) reset the time-stamp value. By using this clearsignal, the synchronization for all modules are achieved.

1.3

Output register

By the output register function, this module can output pulse and level signals fromNIM OUT0–1. The pulse width is ﬂexible, and it can be changed from 20 ns – 1.3 ms
with 20 ns resolution.

1.4

Interrupt register

NIM IN0 input provides the interrupt signal to CAMAC and VME bus. The interrupt
delay, which is a delay time between the signal timing and the interrupt generation timing,
can be set from 20 ns to 1.3 ms with 20 ns step.

1.5Indicator

1.5.1

Ex Clock OK

When the external clock is correct, this LED lights up. However even if the external
clock is not 25 MHz, sometimes this LED becomes ON. And also, after the correct op1

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1 General

eration, even if cable is removed, sometimes this LED still lights up. When the external
clock mode, please check the Ex Clock through output by oscilloscope. If this signal is 25MHz, the external clock synchronization is correct.

1.5.2FIFO Full

There is FIFO memory, and it can store 1024 event time-stamp values. When FIFO
becomes full, this LED will light up.

1.5.3

Int/Ext clock mode

With the external clock mode, this LED lights up. Internal clock mode case, this LED
is oﬀ. The default setting is the external clock mode.

1.6

Connector

1.6.1

NIM input ch0 : Interrupt

CAMAC/VME interrupt signal is generated by this interrupt input. More than 20 ns
width logic pulse is required.

1.6.2

NIM input ch1 : Trigger

Time stamp values are stored into FIFO according to this trigger input. More than 30
ns width logic pulse is required.

1.6.3

NIM input ch2 : Time ResetWith this input, time stamp values are cleared to be 0. This input is for the module
synchronization. More than 20 ns width logic pulse is required.

1.6.4

NIM input ch3 : Ext Clock

Input external clock. Duty ratio 50:50, 25 MHz NIM logic pulse is needed.

1.6.5

NIM output ch0 : Output 0

An output for NIM level and pulse.
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1 General

1.6.6

NIM output ch1 : Output 1

An output for NIM level and pulse.

1.6.7

NIM output ch2 : Int clock throughAn output of internal 25 MHz clock which is based on internal 50 MHz clock. Thissignal is used for synchronizing other modules.

1.6.8

NIM output ch3 : Ext clock throughAn output signal of external 25 MHz clock which is the through out of the external
25 MHz clock input. This signal is used for checking the external clock quality andsynchronizing other modules. This through out is not a real direct output of the externalclock. The external clock is put into the DLL circuit once, and this signal come from oneof the DLL outputs. Thus, if the 25 MHz external clock has large noise, this through out
will be not stable signal.

3

41.7

1 General

Block diagram㪝㪧㪞㪘25 MHz
External clock
DLL
External
100 MHz clockClear

48 bitCounterTrigger
Latch

FIFO

Latch

48 bitx1024 cell

48 bitCounter
100 MHz clock
50 MHzOscillator

VME/CAMAC
Interface

DLL
Internal

図 1.1: Block diagram of time stamping part.

4

5

1.8

1 General

Front panel

Ex Clock OK : 0Trigger : 2
FIFO Full : 4Interrupt : 6

1 : Module access
3 : Int/Ext clock mode5 : NIM output 0ch
7 : NIM output 1ch

InterruptTrigger
Time Reset
Ext Clock

NIM output 0ch
NIM output 1ch
Int clock throughExt clock through572 Interface

2 Interface
2.1

Register map

Command list.
CAMAC (R/W)
F(0)A(0)F(0)A(2)F(0)A(4)F(0)A(6)F(1)A(0)F(1)A(2)F(1)A(4)F(2)A(0)F(2)A(4)F(16)A(0)F(17)A(0)F(4)A(0) F(20)A(0)F(4)A(1) F(20)A(1)F(6)A(0) F(22)A(0)F(7)A(0)F(9)A(0)F(9)A(1)F(9)A(2)F(9)A(3)F(10)A(0)F(24)A(0)F(26)A(0)

2.1.1

VME
Base + %00
Base + %04
Base + %08
Base + %0c
Base + %10
Base + %14
Base + %18
Base + %20
Base + %24
Base + %00
Base + %10
Base + %40
Base + %42
Base + %60
Base + %70
Base + %90
Base + %92
Base + %94
Base + %96
Base + %94
Base + %80
Base + %A0Register
Data 24 bits lower
Data 24 bits higher
Data 32 bits lower
Data 32 bits higher
Trigger Counter
FIFO Counter
Data on the ﬂy
Data 24 bits sequential
Data 32 bits sequential
Level Output
Pulse Output
Pulse WidthInterrupt Delay
Clock Source
Module version
Clear FIFO & Interrupt
Reset Time Stamp
Clear Trigger Counter
Clear All
Clear Interrupt
Disable Interrupt
Enable Interrupt

Data lower 24 bits

Return the lower 24 bits time stamp value from FIFO.
7

Data
D32
D32
D32
D32
D32
D32
D32
D32
D32
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16

VME R/W
read
read
read
read
read
read
read
read
read
write
write
read/write
read/write
read/write
read
read
read
read
read
read
writewrite

82 Interface

2.1.2

Data lower 24 bits

Return the higher 24 bits time stamp value from FIFO. Reading of lower bits is required
before reading higher bits.

2.1.3

Data lower 32 bits

Return the lower 32 bits time stamp value from FIFO. CAMAC case, this value will be
cut 24 bits.

2.1.4

Data higher 32 bits

Return the higher 16 bits time stamp value from FIFO. Reading of lower bits is required
before reading higher bits.

2.1.5

Data on the fly

Return the current time stamp counter (higher 24 bits).

2.1.6

Trigger Counter

Return the number of trigger input. The data depth is 32 bits for VME, 24 bits forCAMAC. By access of Clear Trigger Counter Register, this value will be cleared.

2.1.7

FIFO Counter

Return the number of time stamp data in FIFO. The data depth is 11 bits. And themaximum value is 1024.

2.1.8

Data 24 bits sequential

Under development.

2.1.9

Data 32 bits sequential

Under development.

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92 Interface1514

2.1.1013121110

98

7

654

3

2

1ch10ch0

Level Output

Output level signals from NIM Output connectors (1=on, 0=oﬀ).

2.1.11Pulse Output

Output pulse signals from NIM Output connectors (1=on, 0=oﬀ). With this pulse
signal, level output will be canceled.
15142.1.12

13121110987654321ch10ch0

Pulse Width

Set the width of the pulse output signal. 1 point corresponds to 20 ns. The default
value is 10 = 200 ns. The maximum value is 65536  1.3 ms.

2.1.13

Interrupt Delay

Set the delay time during interrupt input arrival time and actual interrupt generation.
1 point corresponds to 20 ns. The default value is 0 = 0 ns. The maximum value is 65536
 1.3 ms.

2.1.14Clock Source

Choose the time stamp clock source. Default is the external clock.
0 : Internal Clock
1 : External NIM Input 0

2.1.15Clear FIFO & Interrupt

Clear FIFO memory and interrupt signal. In case of VME, this function is invoked byread action.
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102 Interface

2.1.16

Reset Time stamp

Reset the time stamp counter to 0. FIFO memory is also cleared. In case of VME, thisfunction is invoked by read action.

2.1.17

Clear Trigger CounterClear the trigger counter only. In case of VME, this function is invoked by read action.

2.1.18

Clear All

Clear FIFO memory, interrupt signal, the trigger counter. The time stamp counter isnot reset. In case of VME, this function is invoked by read action.

2.1.19Clear Interrupt

Clear interrupt signal only. If CAMAC/VME interrupt signal is generated by thismodule, the clear interrupt function should be called from interrupt service routine. Incase of VME, this function is invoked by read action.

2.1.20

Disable Interrupt

Disable VME/CAMAC interrupt. In case of VME, this function is invoked by write
action. Any write value is acceptable.

2.1.21

Enable Interrupt

Enable VME/CAMAC interrupt. In case of VME, this function is invoked by write
action. Any write value is acceptable.

2.1.22

VersionReturn the version code of this module. The following is VME Time Stamp Ver 1.2case.
15

14
13
12
CAMAC/VME
211

10
9Module ID
287

1065Ver X.X
14

32
1
Ver X.X20

113 Appendix

3 Appendix
3.1Version Information

1.2 With FIFO version.
1.1 Without FIFO. To avoid noise problem, the external clock input channel is changed.
1.0 Initial version.

3.2

Comment

To synchronize with Techno-AP DSP Module, the frequency of the external clock is 25
MHz. This frequency can be able to change by FPGA program.

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