FPGA Lecture
for LUPO and GTO
Vol. 12010, 31 August (revised 2013, 19 November)
H. BabaContents
 Basic feature of FPGA Basic usage for LUPO

◦ New project◦ Read and Write Basic behavioral VHDL simulation
 Download firmware

What is FPGA ?
 Field Programmable Gate Array

CLB

IOB
External IO

CLB

CLB

DCM
Clock Manager

CLB

CLB

CLB
SRAM

CLB

CLB

CLB

Wiring Switch
Logic Unit

Internal RAM

CLB and wiring
LUT

CLB0123In
Out0000 00001 10010 10011 10100 00101 10111 11000 0DFFClockAbout LUPO NIM signals areconverted to
LVTTL◦ NIM->LVTTL->FPGA◦ FPGA->LVTTL->NIM

8LED
4NIM IN

16 LVDS IO
32 LVTTL IO

 LVDS ports aredirect connection◦ Because of this IOB
is 2.5V, this port
can be accept 2.5V
IO signals

VME Interface(CPLD)

4NIM OUT

User FPGA(Spartan 3E)

New Project for LUPO
 Device and Design flow

Design property for GTO

The definition of IO (LUPO)
LED : LED
 A
: CAMAC/VME address
 CLOCK : 50MHz clock INIT : CAMAC Z/C, VME Init?
 IP: NIM Input 0-3
◦ IP0 : IP0 to GCLK

OP : NIM Output 0-3
 LVDSn/LVDSp : LVDS IO 0-15


◦ LVDS_CLKn/p : LVDS0 to GCLK

RD : Data Read
 WR : Data Write RD_STRB : Read strobe
 WR_STRB : Write strobe
Copy the Constraint file (UCF) vlupo.ucf
 gto.ucf
 Write constraints

for IO and others

Association = should be Implementation

Without CAMAC/VME Buses (LUPO)
 This is enoughNETs written in UCF are must be written
in “entity” also

Edit vlupo.ucf by “Edit Constraints(Text)”

Simple case (LUPO)
 Like thisIf Synthesize -> Implement Design are passed, it will workTo make the synchronous circuit When you use “if, else”, you should put values into allsignals explicitly◦ Check Warning

In this case, createdcircuit will beasynchronous circuit

Should write
values in “else”
explicitlyThis type works well, usually By using “event process”, DFF will be used, and values

are kept as you had expected

Values are changed at the Clock timing

Basically, all lines run in parallelIP(0)edBe careful about the loop circuit
 As this schematic, you can make the “Latchcircuit”, but...

 Warnings of Combinational loop

◦ It will not work, depending on the pulse width, linedelay, jitter and so onExpressly using FF is safe
 “event” in the process statement

makes DFF, basically As a circuit component, if you use
FDCE(=DFF), it will work as you
expected

Accessing VME/CAMAC buses（Read for LUPO）
 Latch data during RD_STRB = ’1’

Accessing VME/CAMAC buses (for LUPO)
 Data are read from WD at the transition timing ofWE_STRB ’1’ to ’0’Example of data readout (LUPO)
By using when statement, VME
Address (CAMAC AF) is selected During RD_STRB=‘1’, data must be
latched on RD
◦ RD <= val;

Other cases, RD is unconnected◦ RD <= (others => ‘z’);

elsif (WR_STRB = ‘1’) then

Example of data write (LUPO)
Set a flag at WR_STRB=‘1’

1.

◦ set <= ‘1’;

At WR_STRB’event and WR_STRB=‘0’
timing, if flag is 1, set values

2.

◦ val <= WR;

When WR_STRB=‘0’, value of set sholdbe kept3.

◦

set <= set;

set is connected toCE (clock enable)
WRof DFF

set
WR_STRB

elsif (WR_STRB = ‘1’) thenval

Make a scaler (counter)

By using event, make asynchronous circuit◦ cnt <= cnt + 1

When data readout, data
must be latched at theRD_STRB, otherwise you get
invalid values, sometimes◦ If cnt value is changed during
readout, it is bad◦ There are skew (- 20ps)
between all bits

Latching the value of Scaler (Counter)Prepare the vector forreadout

It is not “iq <= cnt;”
If you this, you get valueof cnt - 1

Declare usuful libraries
 library IEEE; use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;◦ cnt <= cnt + 1 requires ARITH

If you simulate with built in libraries suchas FDCE, you have to uncomment like thisDo simulation
 Create the Test BenchSet initial values
Implementation
Simulation
SwitchWrite like this clock part are generated automatically wait for 100ns; means 100ns passing

ダブルクリックでシミュレーション開始

ISimExpandRun 1 step

Download firmware to LUPO/GTO
 Generate Programming File◦ bit file is generated

 Configure Target Device◦ Launch iMPACT◦ Make file for the flash memory from bit file
◦ Load into FPGAFirst step, PROM ＝ Flash Memory fileSetting of PROM file
GTO case, it is xcf02sChoose xcf04s and Add

Choose Xilinx Flash/PROMand press

Generate PROM file

By the wizard
1. [add a device ?] -> Yes
2. Select bit file
3. [any other device ?] -> No
By double click, file (***.mcs)
will be generatedDownload firmware

For FPGA,
cleared bypower cycle(bit file)

For Flash ROM,non-volatile(mcs file)

Load FPGA option is useful, FPGA
will be reconfigured when FlashROM is updated

Ex. mistake case, conv_std_logic_vector
 Converting to the numerical value of 5000000 to the24bits vector
 conv_std_logic_vector(5000000, 24)◦ Good conv_std_logic_vector(24, 5000000)◦ Converting the numerical value of 24 to the 5000000bitsvector◦ Synthesize take so long time

“downto” and “to”signal a : std_logic_vector(3 downto 0) := “3210”◦ Using vector, downto is usual◦ Writing initial value with “bit”, it is common that the most right positionis 0-th bittype ARINT is array(3 downto 0) of integer;◦ constant b : ARINT := (0,1,2,3);◦ It will be b(0)=3, b(1)=2, b(2)=1,b(3)=0



type ARINT is array(0 to 3) of integer;◦ constant b : ARINT := (0,1,2,3);◦ b(0)=0, b(1)=1, b(2)=2,b(3)=3◦ Depending on custom,,, when array, to is easier to understandIf you find a warning of black box
attribute box_type : string; attribute box_type of FDCE : component is “black_box”;
 Warning will be solvedOr, you don’t need to declare COMPONENT that are definedin Xilinx Library, simply uncomment these lines

Using LVDSIBUFDS

Input◦ For input case, write DIFF_TERM =TRUE◦ Terminator is installed

OBUFDS

OutputGCLK and BUFGInputs assigned to GCLK can beused as a Clock (having smallSkew and Delay)◦ IP0 and LVDSClockp/n

By connecting BUFG, otherinputs are also can be used as aClock (it will be the Clock ofmany other circuit components)◦ Basically, it is automaticallyconnected at the Place & Route◦ Following declaration isnecessary in UCF

With larger circuit, pleasecheck “Place & Route Report”◦ In case of Local (not BUFGMUX)and Skew is large, the wiring
tuning with PlanAhead isnecessary