4-1

Stacked-chip Implementation of On-Chip
Buck Converter for Power-Aware
Distributed Power Supply Systems
Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya and Takayasu Sakurai
Institute of Industrial Science and Center for Collaborative Research
University of Tokyo, Tokyo, Japankohei@iis.u-tokyo.ac.jp
Abstract— An on-chip buck converter which is implemented bystacking chips and which is suitable for on-chip distributed
power supply systems is proposed and the operation isexperimentally verified for the first time. The manufactured
converter achieves the maximum power efficiency of 62% for an
output current of 70mA with a switching frequency of 200MHz
with a 2x2mm on-chip LC output filter. The active part and thepassive LC output filter are implemented on separate chips
fabricated in 0.35-µm CMOS and connected with metal bumps.
The optimization and improvement of the power efficiency andimplementation structure are also discussed.

I.

INTRODUCTION

Recently System-on-a-Chip (SoC) and System-in-a-Package(SiP) are getting focus as major integration technologies. They
are often used for integrating various types of circuit blocks
from processors, memories to analog circuits either. The
optimum supply voltage (VDD) for each circuit blocks isdifferent each other and the difference tends to increase as thetechnology scales. For example, memory and analog circuits
tend to prefer higher voltage compared with logic blocks. This
leads to the multiple-VDD implementation in low-power andhigh-performance systems. Moreover, supply voltage
sometimes is varied in time for achieving lower power
consumption, which is called dynamic voltage scaling.
Supplying many different and dynamically scaling voltages
from outside the package gives rise to much overhead in area
and the power line integrity including IR drop and noise also
Stacked memories

Stacked analog/RF

Proc. units

Sensors andinformationcollecting circuits
Figure 1. Concept of distributed power supply system.
Power
control proc.

0-7803-9735-5/06/$20.00 ©2006 IEEE

The distributed on-chip power supply circuits are useful forsolving these problems. Fig.1 shows the concept of the
distributed power supply. High voltage is distributed by a main
power grid and then it is converted to the lower voltages at thevicinity of the target blocks by distributed on-chip voltage
converters. This approach reduces cost and power integrity
issues.
For DC-DC converters, a linear regulator, a buck converters
and a switched capacitor converter are known. A buckconverter need large passive elements of inductance andcapacitance (LC) for an output filter although it shows thehigher power efficiency compared with a linear regulator. A
switched capacitor converter also needs large capacitors andone more drawback is that the output voltage levels are limitedby the ratios of prepared capacitors, and is not very suitable forlow-power dynamic voltage scaling systems.
In case of the buck converter, high switching frequency ispreferable for smaller L and C but the power efficiency isdegraded by the dynamic power of the switching transistors in
the high frequency operation. Low quality factor (Q) of aircore and on-chip inductors also degrades the power efficiency.
High inductance is good for high Q but is not easy to obtain ona chip because of the area limitation and even if high magnetic
permeability material is introduced on a chip, high-µ is usually
lost at more than 200MHz.
A couple of integrated buck converters are reported in recent
years. 80-87% efficiency was achieved at a high switchingfrequency of 233MHz for voltage conversion ratios of 0.75 and0.79 with off-chip air-core inductors in 90-nm CMOS process[1]. The air-core surface-mount inductors whose quality factor
is over 20 contribute to the high power efficiency. The part cost,
the assembly cost and area, however, are problems and theapproach is not suitable for on-chip distributed power supplies
where many inductors are required nearby.
On the other hand, 50% efficiency without Zero Voltage
Switching (ZVS) and 65% with Two-Stage ZVS were reported
at a switching frequency of 45MHz with a voltage conversion
ratio of 0.64 implemented with on-chip integrated output filter
in 0.18-µm SiGe process [2]. In this implementation, the output
filter is costly because it consumes large area in precious

Power unit
Specialized blocks
Power grid

becomes an issue.

127

silicon area which is manufactured by a scaled process.
Moreover, in this specific implementation, metal thickness ischosen to be 10 µm, which is again costly and which is not
usually available. Therefore, other approaches to implement
buck converters for distributed power supply systems are to besought through.

proportional to the product of effective resistance RT andeffective switching capacitance Ceff of switching transistors.
Here, Ceff is expressed as 1.3CG+CJ where CG and CJ indicate
the gate and junction capacitance per unit width. As technology
scales, RT and Ceff scale as 1/k0.7 and 1/k where k denotes
scaling factor. Therefore, it is better from the power efficiency
point of view to use the more advanced technology.

BASIC CONCEPT OF STACKED-CHIP IMPLEMENTATION

One may argue, however, that the maximum Vin can be lower
with more scaled transistors. When Vin is higher than the
maximum VDD for a certain technology, the switchingtransistors must be cascaded to relax the voltage over-stress. If
two transistors are cascaded, RT increases by a factor of 1.2 andCeff decreases by a factor of 0.4 [3]. As a result, even though wehave to use cascaded structure, R0C0 decreases as technology
scales. Thus, it can be said that it would be better to use themost scaled transistors for high conversion efficiency.

II.

In order to implement on-chip buck converters for distributed
power supply systems, the following two conditions should be
met. First, all elements of the converter must be integrated atleast in a package. Secondly, the implementation cost must be
minimized while the power efficiency is kept high.
To maximize the power efficiency, the power loss must be
minimized. The major components of power loss are classified
into three parts: dynamic switching loss of the switchingtransistors, resistive loss of the switching transistors and theresistive loss of the inductor. The total power loss is minimized
under the condition that previous three parts are equal and isgiven by the following expressions [3].
Ploss = Vin I L 3 24

R0 C 0τL

D (1 − D ) ∝ 3

R0 C0

τL

,

(1)

where
R0 C 0 =τL =( DR C + (1 − D )R C ) ,
2

P

P

N

L
.
RS

N

(2)
(3)

D (= Vout/Vin) is the duty cycle where Vin and Vout are the input
and output voltages, which is not a design parameter but isgiven by the specification. IL signifies the output current. RP, RN,
CP, CN denotes effective resistance and capacitance of PMOS
(high-side) and NMOS (low-side) switching transistors. L and
RS are the filter inductance and its parasitic series resistance.
For planar inductors, the maximum τL is fixed and given by thetechnology. The thicker the metal layer is, the smaller the
maximum τL is.
As seen from (1), the smaller R0C0 and the larger τL are betterfor higher power efficiency. R0C0 is shown to be roughly
L&C cells

On the other hand, τL is mainly determined by the thickness ofthe metal wire. The thicker, the better. Thus the inductor is notnecessarily fabricated by using the most advanced technology
which is expensive.
In conclusion, it is reasonable to implement active elements
and output filter on separate die whose process technologies aredifferent. Fig.2 shows the basic concept of the stacked-chip
implementation of a buck converter. The lower chip fabricatedin the advanced technology contains the controller andswitching transistors of buck converter and target circuits. The
upper chip fabricated in classical and cheap process technology
contains LC filter elements such as L’s and C’s. By stacking
two chips face-to-face and connecting via metal bumps, a buckconverter for on-chip distributed power supply systems can be
fabricated in a well balanced manner over cost and power
efficiency.
III.

TEST CHIP DESIGNTo demonstrate the feasibility of the stacked-chip buckconverter, an on-chip buck converter is designed in 0.35-µm
CMOS for upper and lower chips. The lower chip could bemanufactured by 90nm or more advanced technology for thehigher efficiency but this test chip is to show the feasibility ofthe stacked-chip approach. Fig.3 shows the circuit diagram ofthe buck converter, which is simple but parameters are
optimized for the power efficiency. The area of the filter equals
to the outer diameter of the filter inductor dout, which is set at
outputPads

Ring
oscillator

Package

Phasorwave
generator

Output filter chip
On-chip
power
supplies

Off-chip
controller
Vref
+
-

Lower chip

SoC/SiP

Upper chip

Figure 3. Circuit diagram of stacked-chip implementation of buckconverter.

Figure 2. Basic concept of stacked-chip implementation of buck converter.

128τL = L/RS

PAD
2mm

dout

Cap
1nF

din

0

0.5
din/dout

1

Figure 4. τL dependence on din/dout for square inductor.
Figure 6. Chip microphotograph of output filter.

100
80
60
40 η (%)

400

Upper chip
(Output filter)

20
100

300
80

200
f (MHz)

60
100

8

40
20

IL (mA)

Lower chip
(Active elements & load circuits)

0

Figure 5. Power efficiency dependence on load current and switchingfrequency.

2x2sq.mm by assuming that 10mm-square chip can have 25
voltage domains. The inductance is estimated by the simple
formula [4]. τL is a function of din / dout as shown in Fig.4. Thisis because the inductance and the parasitic resistance areproportional to n2 for fixed din / dout when n indicates thenumber of turns. From the calculation result, din is decided toabout 0.5dout. The open space at the center of the inductor isfilled with a MOS capacitor for the output filter. The
capacitance achieved is about 1nF. Under this condition, thepower efficiency dependence on the output current and theswitching frequency for Vin=3.3V and Vout=2.3V is estimated as
Fig.5 using newly derived formulas. Our formula includes theeffect of the output voltage drop caused by the filter inductor
which is not involved in [5]. It is impossible to choose theswitching frequency under 100MHz because the output voltage
ripple goes up above 10%. The gate width of the high-side andthe low-side transistors are designed to 1000µm and 500µm asa result of the optimization at the output current of 60mA using
formulas in [5].
IV.

Figure 7. Measurement setup of test chip.

Chip for output filter
Resin

Bumps

Chip foractive elements

Pads

Figure 8. Cross section diagram of measurement setup.

Ripple<±10%
T = 5nsf = 200MHz

SIMULATION AND MEASUREMENT RESULTS

The test buck converter with the stacked-chip implementation
was fabricated and measured. Fig.6 shows the chip
microphotograph of the output filter on the upper chip. Fig.7
and Fig.8 shows the measurement setup and its cross-sectional
diagram. Here, the pad size is 200x200sq.µm for thisexperimental setup. Micro bumps whose diameter is 30µm and

129

Figure 9. Output voltage waveform for Vout=1.86V and IL=60mA.

80

100

70

D=0.5
Efficiency (%)

Efficiency (%)

60
50
40

+14%

Measured20

050

Simulated(HSPICE)

10
0

20

40

60

50

80

Here, α is a constant.

whose resistance is as low as 14mΩ/bump have been realized
in industry environments [6] and can be used instead for further
smaller area. Fig.9 shows the output voltage waveform for
Vout=1.86V and IL=60mA. The measured voltage ripple issmaller than ±10%, which is comparable with the more
expensive solution in [1]. Fig.10 shows the simulated andmeasured power efficiency with Vout=2.3V over the output
current, IL, ranging from 20 mA to 70 mA. The maximum
efficiency of 62% is achieved at the output current of 70mA.
The measurement result coincides well with the HSPICE
simulation result with all the parasitic elements.
DISCUSSIONS

To gain higher efficiency, it is valuable to use inductors
whose τL is higher than on-chip inductors. Inductor cells onplastic or glass substrates realize it by the structure shown in
Fig.11. The thickness of the metal wire on those substrates isgenerally larger than 10µm. The capacitor cells on the upper
chip in a classical technology are connected to the lower chipin an advanced technology through the through-hole vias on thesubstrate. By doing so, high efficiency and cost reduction areachieved. The maximum power efficiency is given as follows
when the process technology and D are fixed[3].
η=

1 + ατ L(4)−1 / 3150

Figure 12. Efficiency dependence on τL.

Figure 10. Simulated and measured efficiency for Vout=2.3V and
f=200MHz.

1100
τL (nH/Ω)

Output Current (mA)V.

Implementation
with interposer

Present
implementation

30

Fig.12 shows the power efficiency dependence on τL for D=0.5
in 90-nm CMOS. τL for Cu wires whose thickness is 15µm is
increased by x15 compared to the case of on-chip wires. As aresult, the efficiency is increased by 14%.
VI.

An on-chip buck converter with stacked-chip implementation
is designed and fabricated for the first time, which is suitable
for low-cost low-power distributed power supply systems. The
switching frequency is optimized and chosen to be 200MHz.
The power efficiency of 62% is measured for the output currentof 70mA, which verifies the feasibility of this approach. If
more advanced assembly technology is used, the efficiency canbe further improved.
ACKNOWLEDGMENT
Valuable discussions with K. Osada from Hitachi Ltd., S.
Borkar, R. Krishnamurthy, S. Hsu, T. Karnik, G. Schrom fromIntel laboratories are appreciated. The chip fabrication is
supported by VLSI Design and Education Center (VDEC), theUniversity of Tokyo with the collaboration by Synopsys, Rohm
Corporation and Toppan Printing Corporation.
REFERENCES
[1]

.
[2]

Capacitor cells in classical technology

[3]

[4]

Inductor cells
on plastic/glass(flexible) interposer

[5]

[6]

Switching devices and load circuits
in advanced technology
Figure 11. Another stacked-chip implementation to gain high τL.

130

CONCLUSIONS

P.Hazucha, G.Schrom, Jae-Hong Hahn, B.Bloechel, P.Hack, G.Dermer,
S.Narendra, D.Gardner, T.Karnik, V.De and S.Borker, “A 233-MHz,80%-87% Efficient Four-Phase DC-DC Converter Utilizing Air-Core
Inductors on Package,” IEEE JSSC, vol.40, no.4, pp.838-845, 2005.
S.Svedinpour, B.Bakkaloglu and S.Kiaei, “A Multi-Stage Interleaved
Synchronous Buck Converter with Integrated Output Filter in a 0.18µm
SiGe Process,” IEEE ISSCC, pp.356-357, 2006.
G.Schrom, P.Hazucha, F.Paillet, D.S.Gardner, S.T.Moon and T.Karnik,“Optimal Design of Monolithic Integrated DC-DC Converters,” IEEEICICDT, pp.65-67, 2006.
S.Mohan, Maria del Mar Hershenson, S. Boyd and T.Lee, “Simple
Accurate Expressions for Planar Spriral Inductors,” IEEE JSSC, vol.34,
no.10, pp.1419-1424, 1999.
V.Kursun, S.Narendra, V.De and E.Friedman, “Analysis of Buck
Converters for On-Chip Integration With a Dual Supply Voltage
Microprocessor,” IEEE Trans. On VLSI Sys., vol.11, no.3, 2003.
T.Ezaki, K.Kondo, H.Ozaki, N.Sasaki, H.Yonernura, M.Kitano,
S.Tanaka and T.Hirayarna, “A 160Gb/s interface design configuration
for multichip LSI,” IEEE ISSCC, pp.140-141, 2004.