48V-to-12V Dual-Path Hybrid DC-DC Converter
Katsuhiro Hata, Yoshitaka Yamauchi, Toru Sai, Takayasu Sakurai, and Makoto Takamiya
The University of Tokyo, Tokyo, Japan
E-mail: khata@iis.u-tokyo.ac.jp
Abstract—A dual-path hybrid DC-DC converter with thestep-down ratio of less than half is proposed for the first time.
In the proposed converter, the efficiency is higher than aconventional buck converter, because the output current isdivided into inductor- and capacitor-path and the conduction
loss due to ESR of the inductor is reduced. In the measurement,
the peak efficiency of the proposed dual-path hybrid andconventional buck converters was 97.1% and 96.0% at 120W,
48V-to-12V conversion, respectively, indicating the loss is
reduced by 28.4 %. Furthermore, the efficiency of the proposedand conventional converters was 95.8% and 94.8% at 240W,
respectively, indicating the loss is reduced by 30.0 %.

S1
VIN1) Reduced voltage rating for switches: On-resistance perunit area in power MOSFETs increases rapidly as voltage
tolerance becomes higher. For example, the drift resistance isroughly proportional to the voltage tolerance to the power of
2.5 [13]. As a result, the heavy dependence on voltage
tolerance can make attractive the usage of multiple MOSFETs
with low voltage ratings in series, rather than just one
MOSFET with high voltage rating, considering to minimize
the area for power devices.
2) Smaller inductance for a given current ripple: In case ofa three-level buck converter, as an example of the hybrid buckconverter, the peak inductor current ripple can be only 1/4
with the same output LC value and switching frequency [12],which can mean a significant reduction in inductance. Thisfeature in the hybrid DC-DC is useful because the inductor ina conventional buck converter with high voltage and high step
down ratio tends to be bulky and occupy a large portion of theentire volume [14].
3) Larger duty ratio for a given step-down ratio: Theconventional buck converters with high frequency and highstep-down ratio suffer from controlling narrow turn-on signals,
because of switching noises and delays in controller circuits[15]. On the other hand, the duty ratio in hybrid DC-DC
converters can be multiple times larger than in theconventional buck converter, for example, doubled in threelevel buck converter, for a given conversion ratio. The
widened duty ratio makes hybrid DC-DC converters suitablefor high frequency and high step-down ratio operation.
In addition, [16–18] reported unique hybrid step-down
DC-DC converters, where an inductor is indirectly connected978-1-7281-4829-8/20/$31.00 ©2020 IEEE

S2

CFLY

L

S3

Keywords—DC-DC converter, Step-down converter, Hybrid
Converter, Dual-path, Series Equivalent resistance (ESR)

I. INTRODUCTION
Hybrid step-down DC-DC converters [1–12] combining abuck converter and a switched capacitor DC-DC converter
could overcome the trade-off between the efficiency and theform factor of the commonly used buck converter. Comparedwith the conventional buck converter, the hybrid step-down
DC-DC converters, reducing the inductor voltage amplitude
by employing flying capacitors, have advantages, particularly
effective for high input voltage and high step-down ratio
applications, as follows.

+

+ VC

IO
IL

+

CO

RO

+

VO

Fig. 1. Proposed dual-path hybrid DC-DC converter.

to the output and the output current is divided into a dual-path(inductor and capacitor path) unlike the conventional buckconverter and hybrid converters [1–12]. Hence, the converters[16–18] can reduce the conduction loss due to the ESR of theinductor, which is quite beneficial when the inductor loss
dominates. The step-down ratio in [16–18] with two circuit
states, however, is limited to more than half, thereby theycannot support numerous applications such as bus converters
and point of load regulators where the sub-half step-down
ratio (e.g. 48V-to-12V, 12V-to-1V, etc.) is required. Althougha modification in the hybrid step-down converter with reduced
inductor current to include the sub-half conversion ratio is
proposed in [18], it employs three states in switching
operation. Because the three-state operation causes higher
complexity and prevents a simple controller design, the usual
two-state operation in the hybrid step-down converter which
can output less than half of the input voltage is preferable.
To solve the problem, a novel topology of a dual-pathhybrid DC-DC converter with only two states and the stepdown ratio of less than half is proposed for the first time. The
proposed converter has a high step-down ratio with theadvantages of 1) − 3) in the hybrid buck converter and reduced
inductor current. Operation principle and basic characteristicsof the novel topology such as conversion ratio, inductor
current, and flying capacitor current are described analyticallyin detail. Also, the measurement results of the proposed
converter including key waveforms, efficiency, as well as
experimental comparison with a conventional buck converter
using prototypes are shown.
II. PROPOSED DUAL-PATH HYBRID CONVERTER
Fig. 1 shows the proposed dual-path hybrid DC-DC
converter topology. As shown in Figs. 2 (a) and (b), theconverter has two circuit states. While flying capacitor CFLY isconnected to inductor L in series in mode 1, CFLY is in parallelwith L in mode 2. Fig. 3 shows key operation waveforms in
the proposed converter. By considering voltage-second
balance in L, charge balance in CFLY at periodic steady state,

2279

IIN
VIN

+

IO

Vx1
IC,1 I
L
+ VC
L
CFLY

VL

+

+ CO

RO

S1

S2,3

VO

VIN

+

IO

CFLY

VL

L

t
iL (t) ≈ IL, vC (t) ≈ VO, vO (t) ≈ VO

VIN

Vx1

+ VC

(1-D)TSvx1(t)(a) Mode 1

IL

DTS

0

Vx2

IC,2

Mode2
t

0

+

Mode1

+

+ CO

RO

VO

t

0
vx2 (t)+VO

VIN - VO

Vx2

t

0

(b) Mode 2(VIN - 2VO)/LiL (t)

Fig. 2. Two circuit states in the proposed dual-path hybrid converter.

ΔiL

the voltage conversion ratio M of the proposed converter canbe shown as follows:

0(VIN − VCFLY − VO ) DTS + ( 0 − VO )(1 − D ) TS==(VIN − 2VO ) DTS − VO (1 − D ) TS

(1)

(IL - IO)/(CFLY + CO)
ΔvO(IL - IO)/CO

V
D
⇔ O =
VIN 1 + D

VO

t
vC

vO

t

0
VO
D
=
VIN 1 + D

Fig. 3. Circuit operation of the proposed dual-path hybrid converter.

(2)

1

Voltage conversion ratio M=
M

IL /CFLYvC (t)vO (t)

0 = VL-VO /L

where, VL, VO, VIN, VCFLY, <VL>, TS and D are inductor voltage,
output voltage, input voltage, flying capacitor voltage, theaverage of inductor voltage, switching period, and duty cycle,
respectively. Fig. 4 illustrates M as a function of D in the
proposed circuit in contrast with the conventional buckconverter.
III. INDUCTOR CURRENT ANALYSIS
A. DC current in inductor
As shown in Fig. 2 (b), the DC inductor current in the
proposed circuit IL,hybrid can be expressed as follows:
I L,hybrid= DI IN + (1 − D ) ( I C,2 + I O ) ,0 = IC= DI IN + (1 − D ) I C,2D⇔ I C,2 =
−
I IN
1− D

where <IC> is the average of flying capacitor current.

Hybrid

0.8
0.6
0.4
0.2
0

0

0.2

0.4
0.6
Duty cycle D

0.8

1Fig. 4. Voltage conversion ratio M vs. duty cycle D.

By combining (3) and (4),(3)

where, IIN, IO, and IC,2 are input current, output current andflying capacitor current in mode 2, respectively. By applying
the charge balance in CFLY at periodic steady-state, IC,2 can be
expressed in terms of IIN as follows:= DI C,1 + (1 − D ) I C,2

Buck

D


I L,hybri=
DI IN + (1 − D )  −I IN + I O d 1− D= (1 − D ) I O(5)On the other hand, the DC inductor current in buckconverter IL,buck is
I L,buck = I O

(4)

(6)

From (2), (5) and (6), the DC inductor current in the
proposed circuit IL,hybrid can be reduced thanks to the

2280

I
1 − 2MK = L,hybrid =1 − D =I L,buck
1− M

Inductor DC current ratio K

contribution of CFLY to the output current in mode 2, ascompared with the DC inductor current in buck converter
IL,buck as follows:(7)

B. Ripple current in inductor
In addition, since the voltage applied to the inductor L is
reduced thanks to the flying capacitor CFLY, the inductor
current ripple in the proposed converter ∆IL,hybrid can be
reduced compared with the inductor current ripple in the buckconverter ∆IL,buck as follows.

Inductor current ripple ratio Kripple(8)

Similarly, ∆IL,hybrid can be also described,

1 − 2M(1 − M )

0.2
0

0.25
0

0.1
0.2
0.3
0.4
Voltage conversion ratio M

0.5

1
0.8

0.88

0.6
0.4
0.2
0

0.25
0

0.2
0.3
0.4
0.1
Voltage conversion ratio M

0.5

Fig. 5. Comparison of inductor current between proposed dual-pathhybrid converter and conventional buck converter.

(10)

Fig. 6 (c) shows the conventional buck converter topology
and it consists of Sbuck, S3, CO, and L. Then, to prevent current
from flowing into CFLY through the freewheel diode in S2, CFLY
is disconnected from the Vx1 node in the buck operation. The
switches Sbuck, S3 are in a synchronous rectification mode andare always operated in the continuous current mode.

2

Fig. 5 shows the inductor DC current ratio K and inductor
current ripple ratio Kripple vs. voltage conversion ratio M.
In the 48V-to-12V operation, K equals to 0.66 and Kripple
is given to 0.25, respectively. As a result, the proposed dualpath hybrid converter can reduce the inductor DC current by
33.3% and inductor current ripple by 12.2% compared to theconventional buck converter. This not only reduces the
conduction current loss due to the equivalent series resistanceof the inductor, but also helps reduce the core loss of theinductor.
IV.

0.4

(9)

By combining (8) and (9),∆I L,hybrid=∆I L,buck

0.66

0.6

(b) Inductor current ripple ratio Kripple vs. voltage conversion ratio M

T∆I L,buck =(VIN − VO ) D S
LT= VIN (1 − M ) M S
L=K ripple

0.8(a) Inductor DC current ratio K vs. voltage conversion ratio M∆IL,hybrid can be expressed as follows considering thechange in mode 1,
T∆I L,hybrid =(VIN − VCFLY − VO ) D S
LTS= (VIN − 2VO ) D
LT= VIN (1 − 2 M ) D S
LM TS= VIN (1 − 2 M )1− M LM (1 − 2 M ) TS
= VIN
1− M
L

1

EXPERIMENTAL VERIFICATION

A. Experimental Setup
In order to provide a proof of concept for the dual-pathhybrid topology at 48V-to-12V conversion, the proposeddual-path hybrid converter and the conventional buckconverter were fabricated and measured for comparison.
Fig. 6 shows the circuit topology of the prototype
converter. This circuit includes the proposed dual-path hybrid
and conventional buck topologies. As shown in Fig. 6 (b), theproposed dual-path hybrid converter is composed of S1-3, CFLY,
CO, and L. Then, S1-3 are operated as in Fig. 2 and the
additional switch Sbuck does not work in the proposed dualpath hybrid operation.

Fig. 7 displays the prototype converter with key
components highlighted. This converter was implemented on
the 116.8mm x 61mm 2-layer PCB. The proposed dual-pathhybrid topology was placed on the upper side and theconventional buck topology was implemented on the lower
side. The screw terminals are attached to insert current probesof an oscilloscope. Each gate drive signal is given by an
externally connected DSP (PE-PRO/F28335A, Myway-Plus),
and the connection is changed by selecting the MOSFET to be
used for the proposed dual-path hybrid and conventional buck
operations.
The circuit components and parameters are indicated in
TABLE I. Each element and parameter is selected based on
the reference design of 48V-to-12V synchronous buckconverter (PMP6680, Texas instruments). Since the voltage
applied to CFLY and CO is the same in the proposed circuit, thesame elements were used in this design. However, the design
method of CFLY is extremely important because it can affectefficiency, responsiveness and stability. Therefore, the design
method of CFLY according to the theoretical analysis is an
important future work and will be presented.
B. Operation Waveforms
The experimental waveforms at full load condition (IO =20A) are shown in Fig. 8. They are measured by an

2281

Vx1
S1
VIN

+

CFLY

Vx2

S1
L

Sbuck S3

CO

S2

S2
IL

CFLY
RO

CO

+

CIN

VO

Sbuck

(a) Whole circuit topology

LS3(a) Overview

Vx1
S1
VIN

+

CFLY

Vx2

L

Sbuck S3

Hybrid

S2
IL
CO

RO

+

VO

(b) Proposed dual-path hybrid topology(b) Proposed dual-path hybrid topology

Vx1
S1
VIN

+

CFLY

Sbuck S3

Vx2

L

S2
IL
CO

RO

+

VO

Buck

(c) Conventional buck topology(c) Conventional buck topology

Fig. 6. Circuit topology of prototype converter.

oscilloscope (TBS2104, Tektronix). In the proposed dual-pathhybrid operation, Vx1 and Vx2 were measured, indicating thatthe operation shown in Fig. 2 can be successfully implemented.
Additionally, VO and IL were also measured to show the output
voltage regulation characteristics and the inductor current
waveform compared to the conventional buck converter. On
the other hand, since the buck operation does not change Vx1,
only Vx2, VO, and IL are shown.

Fig. 7. Photograph of prototype converter.
TABLE I.

CIRCUIT COMPONENTS AND PARAMETERS.

Parameters

Value and Design Selection

Input voltage VIN

48 V

Output voltage VO

12 V

As shown in Fig. 8 (a), the operation waveform of the
proposed dual-path hybrid converter is the same as in Fig. 2,
and the operation mode as analyzed in section 2 can bedemonstrated. Then, the voltage change at each switchingnode is smaller than VIN, and as with other hybrid converters,
it can be expected to reduce the switching loss. Additionally,
the output voltage VO was stably regulated by the proposeddual-path hybrid converter. Furthermore, in this experiment,
the output current IO was set to 20A, but the inductor current
IL was smaller than that, confirming the usefulness of the
proposed dual-path hybrid converter.

Output current IO

20 Amax

Output power Po

240 Wmax

Switching frequency

100 kHzOn the other hand, the conventional buck converter wasdemonstrated as shown in Fig. 8 (b). Although there is no
particular problem with the regulation characteristics of theoutput voltage VO, the voltage change at the switching node is

Inductor L

2282

Power MOSFET S1-3, Sbuck
Input capacitor CIN
Flying capacitor CFLY
Output capacitor CO

80 V, 100 A, RDS(on),max: 5.7 mΩ,BSC057N08NS3G, Infineon
10.56 μF (2.2 μF x 16), X7R,
C3225X7R2A225K230, TDK
264 μF (22 μF x 12), X7R,
GRM32ER71E226KE15, Murata
264 μF (22 μF x 12), X7R,
GRM32ER71E226KE15, Murata
10 μH, DCR: 2.6 mΩ,SER2918H-103KL, Coilcraft

98
2 μs

36 V

12 V

36 V

Efficiency [%]12 V
vx1 (25 V/div)48 V

vx2 (25 V/div)vO (10 V/div), VO = 12 ViL (10 A/div)

IL = 14.8 A

97.1 %10 μs

ΔiL = 7.9 A

96

94.8 %

94

Buck
92

Hybrid051015Output current IO [A]

20
10 μs

Power loss [W]iL (10 A/div)

48 V

IL = 20.1 A20(a) EfficiencyvO (10 V/div), VO = 12 V

vx2 (25 V/div)

1.7 %96.0 %(a) Proposed dual-path hybrid converter

2 μs

95.8 %

1.1 %

ΔIL = 9.0 A

15

Buck

15.0 W

Hybrid-30.0 %

1050(b) Conventional buck converter
Fig. 8. Measured waveforms of prototype converter at 240 W full loadcondition.

10.5 W
5.00 W-28.4 %

3.58 W

1020
Output current IO [A](b) Power loss

equal to VIN, and there is a concern that the switching loss andnoise will increase more than the proposed dual-path hybrid
converter.
As will be described later in the efficiency comparison, theproposed dual-path hybrid converter can reduce both theinductor DC current and ripple current compared with theconventional buck converter, and it can be confirmed from themeasured waveforms that the efficiency improvement can be
expected by reducing the conduction loss of the inductor.
C. Efficiency measurement
Fig. 9 (a) shows the measurement efficiency of the
proposed and the conventional converter versus the output
current IO under a fixed conversion ratio of 0.25(=12V/48V).
The efficiency at IO = 10A is 97.1% and 96.0% in the proposed,
and the conventional converter, respectively, resulting in the
improvement in efficiency by 1.1%. At IO = 20A, theefficiency is 95.8% and 94.8% in the proposed, and theconventional converter, respectively, increasing theimprovement in efficiency to 1.7%. The larger efficiency
improvement at higher output current can be mainly explainedby a decrease in DC inductor current in the proposed dual-pathhybrid converter.
Fig. 9 (b) compares the measured power loss in the
proposed and the conventional converter at IO = 10A and 20A.
While the power loss decreases by 28.4% from 5.00W in theconventional, to 3.58W in the proposed at IO = 10A, thereduction at IO = 20A becomes much larger by 30.0% from
15.0W in the conventional to 10.5W in the proposed.
Because the conduction loss has a square dependence on
current, the inductor current reduction in the proposed

Fig. 9. Measured efficiency and power loss comparison.

converter, as described in (7) and (10), is more effective at
higher output current conditions for reducing the loss andimproving the efficiency.
Fig. 10 (a) shows the measurement DC current in inductor,
in the proposed and the conventional converter under acondition of IO = 10A and 20A. The DC current in the
inductor at IO = 10A decreases by 25.1%, from 10.1A in theconventional to 7.5A in the proposed. Similarly, at IO = 20A,
the DC current reduces by 26.1%, from 20.1A in theconventional, to 14.8A in the proposed.
Fig. 10 (b) illustrates the measurement ripple current, in
inductor in the proposed and the conventional converter undera condition of IO = 10A and 20A. The ripple current in the
inductor at IO = 10A decreases by 11.2%, from 8.9A in theconventional to 7.9A in the proposed. Also, at IO = 20A, theripple current reduces by 12.2%, from 9.0A in theconventional, to 7.9A in the proposed.
V.

CONCLUSION AND FUTURE WORK

A dual-path hybrid DC-DC converter for the step-down
ratio of less than half with two circuit states is proposed forthe first time. In the measurement, the peak efficiency of the
proposed dual-path hybrid and conventional buck converters
was 97.1% and 96.0% at 120W, 48V-to-12V conversion,respectively, indicating the loss is reduced by 28.4 %.
Furthermore, at 240W full load condition, the efficiency of the
proposed and conventional converters was 95.8% and 94.8%,
respectively, indicating the loss is reduced by 30.0 %. Since
the proposed dual-path hybrid converter can reduce the2283Inductor DC current IL [A]

25
20

Buck

20.1 A

Hybrid-26.1 %

1510

10.1 A5
0

14.8 A-25.1 %
7.5 A

10
20
Output current IO [A]

Inductor current ripple [A](a) Inductor DC current

10
8
6

8.9 A

-11.2 %

9.0 A

7.9 A

-12.2 %
7.9 A

4
Buck

2
0

Hybrid1020Output current IO [A](b) Inductor current ripple

Fig. 10. Measured inductor current comparison.

inductor current compared to the conventional buck converter,
it was confirmed that the efficiency improvement becomeslarger under heavy load conditions, which means that the
conduction loss of the inductor becomes dominant.
As future works, the charge sharing loss between the
flying capacitor and the output capacitor will be analyzed
because it may affect the efficiency. Additionally, theproposed converter will be compared to the switched capacitor
converter and the three-level buck converter to clarify thesuperiority of the proposed topology over other circuits.
ACKNOWLEDGMENT
This work was partly supported by Toyota Industries
Corporation. The authors would like to thank Sadanori Suzukiof Toyota Industries Corporation for technical discussions.
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