JJ1-5
0.5V Image Processor with 563 GOPS/W SIMD and 32bit CPU Using High Voltage
Clock Distribution (HVCD) and Adaptive Frequency Scaling (AFS) with 40nm CMOS
M. Nomura1, A. Muramatsu1, H. Takeno1, S. Hattori1, D. Ogawa1, M. Nasu1, K. Hirairi1, S. Kumashiro1,
S. Moriwaki1, Y. Yamamoto1, S. Miyano1, Y. Hiraku1, I. Hayashi1, K. Yoshioka2, A. Shikata2, H. Ishikuro2,
M. Ahn3, Y. Okuma1, X. Zhang3, Y. Ryu1, K. Ishida3, M. Takamiya3, T. Kuroda2, H. Shinohara1, and T. Sakurai3
1Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan,2Keio University, Yokohama, Japan, 3University of Tokyo, Tokyo, Japan
Abstract
A 0.5V, 10MHz, 9mW image processor with 320
processing element (PE) SIMD and a 32bit CPU has beendeveloped using 40-nm CMOS. High voltage clock
distribution (HVCD) reduces the number of excessive holdbuffers required in a 0.5-V logic circuit design, thereby
reducing the area, delay, and energy of the SIMD by 14 %,13%, and 6%, respectively. The 0.5-V SIMD with HVCD
achieves an energy efficiency of 563 GOPS/W (= 4.26mW at7.5MHz), the highest yet reported for near-threshold SIMD.
In addition, adaptive frequency scaling (AFS), used tomitigate the impact of the ripple of a buck converters,
increases average clock frequency by 33%.
Introduction
We have developed an energy efficient programmable
0.5-V image processor for front-end signal processing ofimagers. In order to increase energy efficiency,
heterogeneous multi-cores with SIMD, 320 parallel
processing in SIMD, and near-threshold operations are used.
In the design of near-threshold logic circuits, large delayvariations due to PVT variations are a critical problem. We
propose two techniques for dealing with this: high voltage
clock distribution (HVCD) at design stage and adaptive
frequency scaling (AFS) for a post-fabrication tuning.
Image Processor with SIMD and CPU
Fig. 1 shows a block diagram of a developed image
processor that includes a 32bit CPU, a 320 PE SIMD, buckconverters, an all digital PLL (ADPLL) [1], and an A/D
converter (ADC) [2]. The clock frequency (fCLK) is 10MHz.
The image processor has four power supply voltages (VDD),including VDD for logic circuits other than those for clock
distributions (VLOGIC), VDD for clock distributions in the logiccircuits (VCLK), VDD for a 1-port SRAM [3] (VSRAM1), and VDD
for a 2-port SRAM (VSRAM2). The four VDD’s are supplied byon-chip buck converters.
High Voltage Clock Distribution (HVCD)
Fig. 2 (a) shows a hold timing design in a logic circuit. Inorder to achieve correct hold timing with regard to early andlate on-chip variation (OCV) conditions, hold buffers, buffers
added to prevent hold time violations, are required. Fig. 2 (b)shows simulated VLOGIC dependence of the normalized
minimum number (N) of stages of the logic gates that include
hold buffers. VCLK is varied. N increases with decreasing
VLOGIC because OCV increases and within-die gate delay
variations increase. N also increases with decreasing VCLK
because OCV increases and clock skew increases. For
example, at VLOGIC = 0.5V, N at VCLK = VLOGIC - 0.1V is seventimes as large as N at VCLK = VLOGIC. Increasing N increases
area and power overhead, and the setup timing design will
also be affected by an increased N. In contrast, N at VCLK =VLOGIC + 0.1V is one-fifth of N at VCLK = VLOGIC. For thisreason, we propose HVCD in which VCLK and VLOGIC are
separated and VCLK > VLOGIC, in order to reduce excessive N
due to large within-die process variations at 0.5V. Fig. 3
shows a layout for 320 PE SIMD with HVCD. In each 16 PE,
the VCLK domain and VLOGIC domains are separated, and allclock buffers are placed and routed in the V CLK domain. Figs.
4 (a) and (b) show simulated area, delay, power, and energy
for HVCD with respect to conventional VCLK = VLOGIC for
CPU and the SIMD, respectively,. In CPU, area, delay, andenergy are reduced by 11%, 13%, and 6%, respectively, at thecost of an 8% increase in power. Similarly, in the SIMD, area,
delay, and energy are reduced by 14%, 13%, and 6%,respectively.
Adaptive Frequency Scaling (AFS)
In conventional AFS [4] for a high performance 2.5 GHz
processor, fCLK is varied with ns-resolution, using voltage
detectors and digital frequency dividers. The area and thepower overheads of the conventional AFS are not acceptablein the mW-class processor in the this work. Therefore, wepropose AFS with a small area and power overheads (see Fig.
5). Adaptive voltage scaling (AVS) [5] is also implemented.
AFS is performed by a s-order and ns-order feedback loops,
while AVS is performed by a ms-order feedback loop. Ring
oscillators (ROSC’s) monitor VLOGIC and also function as
integrators for VLOGIC, which solves the area and power
overhead problem in [4]. ROSC frequency is compared with areference frequency (fREF), and an up/down signal is given tothe AVS controller every several 10ms to adapt to die-to-die
process variations and temperature variations. An up/down
signal is also given to the AFS controller every about 10s toadapt to several 100 s-order VLOGIC noise, and fCLK ischanged by changing a multiplication number in the ADPLL.
Critical path replicas also monitor VLOGIC every 100ns(cycle-by-cycle at 10MHz) by checking the setup margin.
When a setup warning is found, the critical-path-replicainterrupts the up/down signal to avoid a setup error.
Experimental Results
The proposed image processor has been fabricated in a
40-nm CMOS process. Fig. 6 shows a die photo. Table I
shows a performance summary. Fig. 7 shows measured
shmoo results for two CPUs, (CPU0 and CPU1), which were
designed and fabricated to show the advantage of HVCD.
CPU0 is designed with HVCD (VCLK = VLOGIC + 0.1V), while
CPU1 is designed with a conventional single VDD (VLOGIC =VCLK). In Fig. 7, the target 10MHz operation is achieved at0.5V only with CPU0, which is faster than CPU1 at a fixed
VLOGIC. Fig. 8 shows a measured shmoo for SIMD withHVCD. The target 10MHz operation is achieved at 0.5V. Fig.
9 shows measured VLOGIC dependence of maximum fCLK, total
power, and leakage power for SIMD. Fig. 10 shows measured
VLOGIC dependence of energy efficiency for SIMD. Themaximum 563GOPS/W is obtained at VLOGIC = 0.45V,
4.26mW, and 7.5MHz. Table II shows a comparison with apreviously reported SIMD [6]. Our design achieves thehighest energy efficiency in the reported near-threshold
SIMD. Fig. 11 shows measured waveforms of VLOGIC and fCLKwith AFS. A 4kHz sinusoidal wave is applied to VLOGIC toemulate the ripple of buck converters. The proposed AFS
makes it possible to track fCLK to VLOGIC, thereby increasing
average clock frequency by 33%.
Acknowledgment

C36

2013 Symposium on VLSI Circuits Digest of Technical Papers

978-4-86348-348-4

This work was carried out as a part of the Extremely Low Power(ELP) project supported by METI and NEDO.

References[1] Y. Hiraku, et al., A-SSCC, pp. 33-36, 2012.
[2] A. Shikata, et al., Symp. VLSI Circuits, pp. 262-263, 2011.
[3] S. Moriwaki, et al., Symp. VLSI Circuits, pp. 60-61, 2012.
[4] T. Fischer, et al., JSSC, pp. 218-228, Jan. 2006.
[5] Y. Ikenaga, et al., JSSC, pp. 832-840, Apr. 2012.
[6] R. Pawlowski, et al., ISSCC, pp. 492-493, 2012.

OCV early

0.5 V

VCLK

Buckconv.

VSRAM132 bitCPUADCVSRAM2

Normalized minimum Nfor hold timing (a.u.)fCLK(10 MHz)

Fig. 1. Block diagram of image processor.

8%+10 %

FF2

Hold buffer

Area Delay0%

N-stage-6 %-11 %

654

VCLK
=VLOGIC+0.1V(Proposed)

3210.48%
Area Delay

0%
VCLK=VLOGIC(Conv.)

x1/5

0.3

+10 %

VCLK=VLOGIC-0.1V

x7

0.5

0.6

-6 %

-10 %
0.7

-14 % -13 %0.8

VLOGIC at design stage [V](b) SIMD (16 PE)

Fig. 2. (a) hold timing design in logic circuit. (b)Simulated VLOGIC dependence of normalized
minimum number (N) of stages of the logic gates.

Fig. 4. Effect of HVCD.
Table I Performance summary

TechnologyFig. 3. Layout of SIMD with HVCD.
AVS controller
VREF

VCLK

Buck
conv.

Freq.
ctrl

Frequency

Detector
ms s

Setup
marginmonitor

PVT &VRIPPLE
monitorCounter

Supplyvoltages

fREF

PowerFig. 5. Block diagram of proposed adaptive voltage andfrequency scaling.
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1111000000001010111111111100000000101011111111114000000101011PASS110 CPU0)00000101111111100101011111111111011111111111111111010111111111111110000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111

11111111111111111111111111111111111111(CPU0 & 1)
1111111111111111111111111111

11111111

11111111

11

11

0.6
0.5
VLOGIC [V]

0.4

1111

Designtarget

0.7

Energy efficiency [GOPS/W]

Inst.

1 MbitData

256 kbitInst.

512 kbitImage

128 kbit x 4Work

64 Byte x
320 (2port)

FAIL

105

Designtarget

1

1.1

0.4

PASS

0.6
0.5
VLOGIC [V]

10 MHzVLOGIC

0.5 V

VCLK

0.6 V

VSRAM1

0.8 V (1 port)

VSRAM20.6 V (2 port)

9 mW

10M

100m
Total power 10m

1M

100k

0.7

1fCLK

Leakage power

10k0.30.4

0.5

0.60.71m

100
0.8

VLOGIC [V]Fig. 9. Measured SIMD frequency and power
consumption characteristics.

Fig. 8. Measured shmoo for SIMD.
Table II Comparison with previous SIMD.

600
500

SIMD

400

CMOS
technology

563 GOPS/W(4.26 mW@7.5 MHz)

Supplyvoltage

100
00.3

100M

70
503020Fig. 7. Measured shmoo for CPU.

200

CPUSIMD
559 GOPS/W
performance (5.73 mW@10 MHz)
Max. 563 GOPS/W(4.26 mW@7.5 MHz)

Fig. 6. Die photo.

fCLK [MHz]fCLK [MHz]120 CPU0: V =V
CLK
LOGIC+0.1V
100=V
CPU1:V
CLK
LOGIC
8060FAIL
40 PASS20 (only032 bit
4 bit, 320 PE

ROSC

fCLK
Critical path
replicansAFS
controller

CPU
SIMD

SIMD

Maximum fCLK [Hz]

ADPLL

300

31 M (Logic：16 M,
SRAM：15 M)

SRAM

0.4

0.5 0.6 0.7
VLOGIC [V]0.8

Fig. 10. Measured SIMD energy efficiency.

Ref. [ 6 ]This work

16 bit4 bit

45 nm SOI

40 nm bulk

0.53 VVLOGIC=0.45 V
VCLK=0.565 VFrequency

144 MHz

7.5 MHz

Power

19.3 mW

4.26 mW

GOPS/W

59.6

GOPS/W
normalized
to 4 bit239

x 9.4563
x 2.4

VLOGIC [V]fREF

5 mm x 5 mm

Number ofTransistors

VLOGIC
CLKtree

40 nm CMOS

Die size

Logic cores

fCLK [MHz]VIN

Voltagectrl

EnergyPower(b)

VREF
gen.

-13 %

(a) CPU

70Energy
Power

-10 %

OCV late(a)8320 PEVLOGIC

Logic

FF1

VCLK

SIMD

ADPLL

VLOGICVLOGIC

CLK

0.5 V
fREF
(1 MHz)

Data

Power [W]

VLOGIC

VIN

0.52
0.50

34 mVP-P

0.48
AFS (This work)

10Average

8+ 33 %

60100200
Time [ s ]Conv. worst
case design

Fig. 11. Measured waveforms of VLOGIC and fCLKwith AFS.

2013 Symposium on VLSI Circuits Digest of Technical Papers

C37