DS18S20
High-Precision
1-Wire Digital Thermometer
www.maxim-ic.com
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PIN ASSIGNMENT

Unique 1-Wire interface requires only one
port pin for communication
Each device has a unique 64-bit serial code
stored in an onboard ROM
Multidrop capability simplifies distributed
temperature sensing applications
Requires no external components
Can be powered from data line. Power supply
range is 3.0V to 5.5V
Measures temperatures from –55°C to+125°C (–67°F to +257°F)±0.5°C accuracy from –10°C to +85°C
9-bit thermometer resolution
Converts temperature in 750ms (max.)
User-definable nonvolatile (NV) alarm
settings
Alarm search command identifies andaddresses devices whose temperature isoutside of programmed limits (temperature
alarm condition)
Applications include thermostatic controls,industrial systems, consumer products,
thermometers, or any thermally sensitive
systemDALLASDS1820
1 2 3

NC

1

NC

2

VDD

3

DQ

4

DS1820

§

®

8

NC

7

NC

6

NC

5

GND

8-Pin 150mil SO(DS18S20Z)

GND
DQ
VDD

FEATURES

1 2

3(BOTTOM VIEW)

TO-92(DS18S20)

PIN DESCRIPTION
GND
DQ
VDD
NC

- Ground- Data In/Out- Power Supply Voltage- No Connect

DESCRIPTION

The DS18S20 Digital Thermometer provides 9-bit centigrade temperature measurements and has an
alarm function with nonvolatile user-programmable upper and lower trigger points. The DS18S20
communicates over a 1-Wire bus that by definition requires only one data line (and ground) for
communication with a central microprocessor. It has an operating temperature range of –55°C to +125°C
and is accurate to ±0.5°C over the range of –10°C to +85°C. In addition, the DS18S20 can derive power
directly from the data line (“parasite power”), eliminating the need for an external power supply.
Each DS18S20 has a unique 64-bit serial code, which allows multiple DS18S20s to function on the same
1-Wire bus; thus, it is simple to use one microprocessor to control many DS18S20s distributed over alarge area. Applications that can benefit from this feature include HVAC environmental controls,
temperature monitoring systems inside buildings, equipment or machinery, and process monitoring andcontrol systems.
1-Wire is a registered trademark of Dallas Semiconductor.

1 of 21022103

DS18S20

DETAILED PIN DESCRIPTIONS Table 1
8-PIN SOIC* TO-92 SYMBOL DESCRIPTION
51
GND
Ground.
Data Input/Output Pin. Open-drain 1-Wire interface pin. Also
4
2
DQ
provides power to the device when used in parasite power mode(see “Parasite Power” section.)
3
3
VDD
Optional VDD Pin. VDD must be grounded for operation inparasite power mode.
*All pins not specified in this table are “No Connect” pins.

OVERVIEW
Figure 1 shows a block diagram of the DS18S20, and pin descriptions are given in Table 1. The 64-bit
ROM stores the device’s unique serial code. The scratchpad memory contains the 2-byte temperatureregister that stores the digital output from the temperature sensor. In addition, the scratchpad provides
access to the 1-byte upper and lower alarm trigger registers (TH and TL). The TH and TL registers are
nonvolatile (EEPROM), so they will retain data when the device is powered down.
The DS18S20 uses Dallas’ exclusive 1-Wire bus protocol that implements bus communication using one
control signal. The control line requires a weak pullup resistor since all devices are linked to the bus via a
3-state or open-drain port (the DQ pin in the case of the DS18S20). In this bus system, the microprocessor(the master device) identifies and addresses devices on the bus using each device’s unique 64-bit code.
Because each device has a unique code, the number of devices that can be addressed on one bus isvirtually unlimited. The 1-Wire bus protocol, including detailed explanations of the commands and “timeslots,” is covered in the 1-WIRE BUS SYSTEM section of this datasheet.
Another feature of the DS18S20 is the ability to operate without an external power supply. Power isinstead supplied through the 1-Wire pullup resistor via the DQ pin when the bus is high. The high bus
signal also charges an internal capacitor (CPP), which then supplies power to the device when the bus islow. This method of deriving power from the 1-Wire bus is referred to as “parasite power.” As analternative, the DS18S20 may also be powered by an external supply on VDD.

DS18S20 BLOCK DIAGRAM Figure 1
VPU
PARASITE POWER
CIRCUIT

4.7K

MEMORY CONTROLLOGICDS18S20DQ
TEMPERATURE SENSOR
INTERNAL VDD

GND

VDD

CPP

64-BIT ROM
AND
1-wire PORTSCRATCHPAD

ALARM HIGH TRIGGER (TH)REGISTER (EEPROM)
ALARM LOW TRIGGER (TL)
REGISTER (EEPROM)

POWER
SUPPLY
SENSE

8-BIT CRC GENERATOR

2 of 21

DS18S20

OPERATION — MEASURING TEMPERATURE
The core functionality of the DS18S20 is its direct-to-digital temperature sensor. The temperature sensor
output has 9-bit resolution, which corresponds to 0.5°C steps. The DS18S20 powers-up in a low-power
idle state; to initiate a temperature measurement and A-to-D conversion, the master must issue a Convert
T [44h] command. Following the conversion, the resulting thermal data is stored in the 2-byte
temperature register in the scratchpad memory and the DS18S20 returns to its idle state. If the DS18S20
is powered by an external supply, the master can issue “read-time slots” (see the 1-WIRE BUS SYSTEM
section) after the Convert T command and the DS18S20 will respond by transmitting 0 while thetemperature conversion is in progress and 1 when the conversion is done. If the DS18S20 is powered withparasite power, this notification technique cannot be used since the bus must be pulled high by a strong
pullup during the entire temperature conversion. The bus requirements for parasite power are explained indetail in the POWERING THE DS18S20 section of this datasheet.
The DS18S20 output data is calibrated in degrees centigrade; for Fahrenheit applications, a lookup tableor conversion routine must be used. The temperature data is stored as a 16-bit sign-extended two’s
complement number in the temperature register (see Figure 2). The sign bits (S) indicate if thetemperature is positive or negative: for positive numbers S = 0 and for negative numbers S = 1. Table 2
gives examples of digital output data and the corresponding temperature reading.
Resolutions greater than 9 bits can be calculated using the data from the temperature, COUNT REMAIN
and COUNT PER °C registers in the scratchpad. Note that the COUNT PER °C register is hard-wired to
16 (10h). After reading the scratchpad, the TEMP_READ value is obtained by truncating the 0.5°C bit(bit 0) from the temperature data (see Figure 2). The extended resolution temperature can then be
calculated using the following equation:
TEMPERATURE = TEMP _ READ - 0.25 +COUNT _ PER _ C - COUNT _ REMAINCOUNT _ PER _ C

TEMPERATURE REGISTER FORMAT Figure 2
LS ByteMS Byte

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

6

2

5

2

4

2

3

2

2

2

1

2

0

2-1

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

S

S

S

S

S

S

S

S

2

TEMPERATURE/DATA RELATIONSHIP Table 2
TEMPERATURE+85.0°C*+25.0°C+0.5°C
0°C-0.5°C-25.0°C-55.0°C

DIGITAL OUTPUTDIGITAL OUTPUT(Binary)(Hex)

0000 0000 1010 1010
0000 0000 0011 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1100 1110
1111 1111 1001 0010

00AAh
0032h
0001h
0000h
FFFFh
FFCEh
FF92h

*The power-on reset value of the temperature register is +85°C

3 of 21

DS18S20

OPERATION — ALARM SIGNALING
After the DS18S20 performs a temperature conversion, the temperature value is compared to the userdefined two’s complement alarm trigger values stored in the 1-byte TH and TL registers (see Figure 3).
The sign bit (S) indicates if the value is positive or negative: for positive numbers S = 0 and for negative
numbers S = 1. The TH and TL registers are nonvolatile (EEPROM) so they will retain data when thedevice is powered down. TH and TL can be accessed through bytes 2 and 3 of the scratchpad as explainedin the MEMORY section of this datasheet.

TH AND TL REGISTER FORMAT Figure 3
bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

S

6

5

5

5

2

1

20

2

2

2

2

2

2

Only bits 8 through 1 of the temperature register are used in the TH and TL comparison since TH and TL
are 8-bit registers. If the measured temperature is lower than or equal to TL or higher than TH, an alarm
condition exists and an alarm flag is set inside the DS18S20. This flag is updated after every temperature
measurement; therefore, if the alarm condition goes away, the flag will be turned off after the next
temperature conversion.
The master device can check the alarm flag status of all DS18S20s on the bus by issuing an Alarm Search[ECh] command. Any DS18S20s with a set alarm flag will respond to the command, so the master candetermine exactly which DS18S20s have experienced an alarm condition. If an alarm condition exists andthe TH or TL settings have changed, another temperature conversion should be done to validate the alarm
condition.

POWERING THE DS18S20
The DS18S20 can be powered by an external supply on the VDD pin, or it can operate in “parasite power”
mode, which allows the DS18S20 to function without a local external supply. Parasite power is very
useful for applications that require remote temperature sensing or that are very space constrained. Figure
1 shows the DS18S20’s parasite-power control circuitry, which “steals” power from the 1-Wire bus via
the DQ pin when the bus is high. The stolen charge powers the DS18S20 while the bus is high, and someof the charge is stored on the parasite power capacitor (CPP) to provide power when the bus is low. When
the DS18S20 is used in parasite power mode, the VDD pin must be connected to ground.
In parasite power mode, the 1-Wire bus and CPP can provide sufficient current to the DS18S20 for mostoperations as long as the specified timing and voltage requirements are met (refer to the DC
ELECTRICAL CHARACTERISTICS and the AC ELECTRICAL CHARACTERISTICS sections of this data
sheet). However, when the DS18S20 is performing temperature conversions or copying data from thescratchpad memory to EEPROM, the operating current can be as high as 1.5mA. This current can cause
an unacceptable voltage drop across the weak 1-Wire pullup resistor and is more current than can besupplied by CPP. To assure that the DS18S20 has sufficient supply current, it is necessary to provide astrong pullup on the 1-Wire bus whenever temperature conversions are taking place or data is being
copied from the scratchpad to EEPROM. This can be accomplished by using a MOSFET to pull the bus
directly to the rail as shown in Figure 4. The 1-Wire bus must be switched to the strong pullup within
10ms (max) after a Convert T [44h] or Copy Scratchpad [48h] command is issued, and the bus must be
held high by the pullup for the duration of the conversion (tconv) or data transfer (twr = 10ms). No otheractivity can take place on the 1-Wire bus while the pullup is enabled.
The DS18S20 can also be powered by the conventional method of connecting an external power supply to
the VDD pin, as shown in Figure 5. The advantage of this method is that the MOSFET pullup is not
required, and the 1-Wire bus is free to carry other traffic during the temperature conversion time.
4 of 21

DS18S20

The use of parasite power is not recommended for temperatures above 100°C since the DS18S20 may not
be able to sustain communications due to the higher leakage currents that can exist at these temperatures.
For applications in which such temperatures are likely, it is strongly recommended that the DS18S20 bepowered by an external power supply.
In some situations the bus master may not know whether the DS18S20s on the bus are parasite poweredor powered by external supplies. The master needs this information to determine if the strong bus pullup
should be used during temperature conversions. To get this information, the master can issue a Skip ROM[CCh] command followed by a Read Power Supply [B4h] command followed by a “read-time slot”.
During the read-time slot, parasite powered DS18S20s will pull the bus low, and externally powered
DS18S20s will let the bus remain high. If the bus is pulled low, the master knows that it must supply thestrong pullup on the 1-Wire bus during temperature conversions.

SUPPLYING THE PARASITE-POWERED DS18S20 DURING TEMPERATURECONVERSIONS Figure 4
VPU

DS18S20Microprocessor

GND DQ VDD

VPU
4.7k

To Other
1-Wire Devices

1-Wire Bus

POWERING THE DS18S20 WITH AN EXTERNAL SUPPLY Figure 5
DS18S20

VPU

Microprocessor

VDD (External Supply)

GND DQ VDD

4.7k

To Other
1-Wire Devices

1-Wire Bus

64-BIT LASERED ROM CODE
Each DS18S20 contains a unique 64-bit code (see Figure 6) stored in ROM. The least significant 8 bits of
the ROM code contain the DS18S20’s 1-Wire family code: 10h. The next 48 bits contain a unique serial
number. The most significant 8 bits contain a cyclic redundancy check (CRC) byte that is calculated fromthe first 56 bits of the ROM code. A detailed explanation of the CRC bits is provided in the CRC
GENERATION section. The 64-bit ROM code and associated ROM function control logic allow the
DS18S20 to operate as a 1-Wire device using the protocol detailed in the 1-WIRE BUS SYSTEM sectionof this datasheet.

64-BIT LASERED ROM CODE Figure 6
8-BIT CRC
MSB

48-BIT SERIAL NUMBER
LSB

MSB

LSB
5 of 218-BIT FAMILY CODE (10h)
MSB

LSB

DS18S20

MEMORYThe DS18S20’s memory is organized as shown in Figure 7. The memory consists of an SRAM
scratchpad with nonvolatile EEPROM storage for the high and low alarm trigger registers (TH and TL).
Note that if the DS18S20 alarm function is not used, the TH and TL registers can serve as general-purpose
memory. All memory commands are described in detail in the DS18S20 FUNCTION COMMANDS
section.
Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register,
respectively. These bytes are read-only. Bytes 2 and 3 provide access to TH and TL registers. Bytes 4 and5 are reserved for internal use by the device and cannot be overwritten; these bytes will return all 1s whenread. Bytes 6 and 7 contain the COUNT REMAIN and COUNT PER ºC registers, which can be used to
calculate extended resolution results as explained in the OPERATION — MEASURING TEMPERATURE
section.
Byte 8 of the scratchpad is read-only and contains the cyclic redundancy check (CRC) code for bytes 0
through 7 of the scratchpad. The DS18S20 generates this CRC using the method described in the CRC
GENERATION section.
Data is written to bytes 2 and 3 of the scratchpad using the Write Scratchpad [4Eh] command; the data
must be transmitted to the DS18S20 starting with the least significant bit of byte 2. To verify data
integrity, the scratchpad can be read (using the Read Scratchpad [BEh] command) after the data is
written. When reading the scratchpad, data is transferred over the 1-Wire bus starting with the leastsignificant bit of byte 0. To transfer the TH and TL data from the scratchpad to EEPROM, the master mustissue the Copy Scratchpad [48h] command.
Data in the EEPROM registers is retained when the device is powered down; at power-up the EEPROM
data is reloaded into the corresponding scratchpad locations. Data can also be reloaded from EEPROM to2
the scratchpad at any time using the Recall E [B8h] command. The master can issue “read-time slots”(see the 1-WIRE BUS SYSTEM section) following the Recall E2 command and the DS18S20 will indicate
the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is done.

DS18S20 MEMORY MAP Figure 7
SCRATCHPAD (Power-up State)
byte 0 Temperature LSB (AAh)byte 1 Temperature MSB (00h)(85°C)EEPROM

byte 2 TH Register or User Byte 1*

TH Register or User Byte 1

byte 3 TL Register or User Byte 2*

TL Register or User Byte 2

byte 4 Reserved (FFh)byte 5 Reserved (FFh)byte 6 COUNT REMAIN (0Ch)
byte 7 COUNT PER °C (10h)byte 8 CRC*
*Power-up state depends on value(s) storedin EEPROM

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DS18S20

CRC GENERATION

CRC bytes are provided as part of the DS18S20’s 64-bit ROM code and in the 9th byte of the scratchpad
memory. The ROM code CRC is calculated from the first 56 bits of the ROM code and is contained in themost significant byte of the ROM. The scratchpad CRC is calculated from the data stored in thescratchpad, and therefore it changes when the data in the scratchpad changes. The CRCs provide the bus
master with a method of data validation when data is read from the DS18S20. To verify that data has
been read correctly, the bus master must re-calculate the CRC from the received data and then compare
this value to either the ROM code CRC (for ROM reads) or to the scratchpad CRC (for scratchpad reads).
If the calculated CRC matches the read CRC, the data has been received error free. The comparison of
CRC values and the decision to continue with an operation are determined entirely by the bus master.
There is no circuitry inside the DS18S20 that prevents a command sequence from proceeding if the
DS18S20 CRC (ROM or scratchpad) does not match the value generated by the bus master.
The equivalent polynomial function of the CRC (ROM or scratchpad) is:
CRC = X8 + X5 + X4 + 1
The bus master can re-calculate the CRC and compare it to the CRC values from the DS18S20 using thepolynomial generator shown in Figure 8. This circuit consists of a shift register and XOR gates, and theshift register bits are initialized to 0. Starting with the least significant bit of the ROM code or the leastsignificant bit of byte 0 in the scratchpad, one bit at a time should shifted into the shift register. After
shifting in the 56th bit from the ROM or the most significant bit of byte 7 from the scratchpad, thepolynomial generator will contain the re-calculated CRC. Next, the 8-bit ROM code or scratchpad CRC
from the DS18S20 must be shifted into the circuit. At this point, if the re-calculated CRC was correct, theshift register will contain all 0s. Additional information about the Dallas 1-Wire cyclic redundancy checkis available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Dallas
Semiconductor Touch Memory Products.

CRC GENERATOR Figure 8

INPUT

XOR

XOR

XOR

(MSB)

(LSB)

7 of 21

DS18S20

1-WIRE BUS SYSTEM
The 1-Wire bus system uses a single bus master to control one or more slave devices. The DS18S20 isalways a slave. When there is only one slave on the bus, the system is referred to as a “single-drop”
system; the system is “multidrop” if there are multiple slaves on the bus.
All data and commands are transmitted least significant bit first over the 1-Wire bus.
The following discussion of the 1-Wire bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling (signal types and timing).

HARDWARE CONFIGURATION
The 1-Wire bus has by definition only a single data line. Each device (master or slave) interfaces to thedata line via an open drain or 3-state port. This allows each device to “release” the data line when thedevice is not transmitting data so the bus is available for use by another device. The 1-Wire port of the
DS18S20 (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 9.
The 1-Wire bus requires an external pullup resistor of approximately 5kW; thus, the idle state for the 1Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle
state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wirebus is in the inactive (high) state during the recovery period. If the bus is held low for more than 480ms,
all components on the bus will be reset.

HARDWARE CONFIGURATION Figure 9
VPU

DS18S20 1-WIRE PORT
4.7k
RX

1-wire Bus

DQ
Pin

RX
5µA
Typ.

TX
100W
MOSFET

TX
RX = RECEIVE
TX = TRANSMITTRANSACTION SEQUENCE
The transaction sequence for accessing the DS18S20 is as follows:
Step 1. Initialization
Step 2. ROM Command (followed by any required data exchange)
Step 3. DS18S20 Function Command (followed by any required data exchange)
It is very important to follow this sequence every time the DS18S20 is accessed, as the DS18S20 will not
respond if any steps in the sequence are missing or out of order. Exceptions to this rule are the Search
ROM [F0h] and Alarm Search [ECh] commands. After issuing either of these ROM commands, themaster must return to Step 1 in the sequence.

8 of 21

DS18S20

INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by theslave(s). The presence pulse lets the bus master know that slave devices (such as the DS18S20) are on thebus and are ready to operate. Timing for the reset and presence pulses is detailed in the
1-WIRE SIGNALING section.

ROM COMMANDS
After the bus master has detected a presence pulse, it can issue a ROM command. These commands
operate on the unique 64-bit ROM codes of each slave device and allow the master to single out a specificdevice if many are present on the 1-Wire bus. These commands also allow the master to determine how
many and what types of devices are present on the bus or if any device has experienced an alarm
condition. There are five ROM commands, and each command is 8 bits long. The master device mustissue an appropriate ROM command before issuing a DS18S20 function command. A flowchart for
operation of the ROM commands is shown in Figure 14.
SEARCH ROM [F0h]
When a system is initially powered up, the master must identify the ROM codes of all slave devices on
the bus, which allows the master to determine the number of slaves and their device types. The masterlearns the ROM codes through a process of elimination that requires the master to perform a Search ROM
cycle (i.e., Search ROM command followed by data exchange) as many times as necessary to identify allof the slave devices. If there is only one slave on the bus, the simpler Read ROM command (see below)
can be used in place of the Search ROM process. For a detailed explanation of the Search ROM
procedure, refer to the iButton® Book of Standards at www.ibutton.com/ibuttons/standard.pdf. Afterevery Search ROM cycle, the bus master must return to Step 1 (Initialization) in the transaction sequence.
READ ROM [33h]This command can only be used when there is one slave on the bus. It allows the bus master to read theslave’s 64-bit ROM code without using the Search ROM procedure. If this command is used when there
is more than one slave present on the bus, a data collision will occur when all the slaves attempt to
respond at the same time.
MATCH ROM [55h]The match ROM command followed by a 64-bit ROM code sequence allows the bus master to address a
specific slave device on a multidrop or single-drop bus. Only the slave that exactly matches the 64-bit
ROM code sequence will respond to the function command issued by the master; all other slaves on thebus will wait for a reset pulse.
SKIP ROM [CCh]The master can use this command to address all devices on the bus simultaneously without sending out
any ROM code information. For example, the master can make all DS18S20s on the bus perform
simultaneous temperature conversions by issuing a Skip ROM command followed by a Convert T [44h]command.
Note that the Read Scratchpad [BEh] command can follow the Skip ROM command only if there is asingle slave device on the bus. In this case time is saved by allowing the master to read from the slave
without sending the device’s 64-bit ROM code. A Skip ROM command followed by a Read Scratchpad
command will cause a data collision on the bus if there is more than one slave since multiple devices willattempt to transmit data simultaneously.
iButton is a registered trademark of Dallas Semiconductor.

9 of 21

DS18S20

ALARM SEARCH [ECh]The operation of this command is identical to the operation of the Search ROM command except that
only slaves with a set alarm flag will respond. This command allows the master device to determine if
any DS18S20s experienced an alarm condition during the most recent temperature conversion. Afterevery Alarm Search cycle (i.e., Alarm Search command followed by data exchange), the bus master must
return to Step 1 (Initialization) in the transaction sequence. Refer to the OPERATION — ALARM
SIGNALING section for an explanation of alarm flag operation.

DS18S20 FUNCTION COMMANDS
After the bus master has used a ROM command to address the DS18S20 with which it wishes tocommunicate, the master can issue one of the DS18S20 function commands. These commands allow themaster to write to and read from the DS18S20’s scratchpad memory, initiate temperature conversions anddetermine the power supply mode. The DS18S20 function commands, which are described below, aresummarized in Table 4 and illustrated by the flowchart in Figure 15.
CONVERT T [44h]This command initiates a single temperature conversion. Following the conversion, the resulting thermal
data is stored in the 2-byte temperature register in the scratchpad memory and the DS18S20 returns to its
low-power idle state. If the device is being used in parasite power mode, within 10ms (max) after thiscommand is issued the master must enable a strong pullup on the 1-Wire bus for the duration of theconversion (tconv) as described in the POWERING THE DS18S20 section. If the DS18S20 is powered by
an external supply, the master can issue read-time slots after the Convert T command and the DS18S20
will respond by transmitting 0 while the temperature conversion is in progress and 1 when the conversion
is done. In parasite power mode this notification technique cannot be used since the bus is pulled high by
the strong pullup during the conversion.
WRITE SCRATCHPAD [4Eh]This command allows the master to write 2 bytes of data to the DS18S20’s scratchpad. The first byte is
written into the TH register (byte 2 of the scratchpad), and the second byte is written into the TL register(byte 3 of the scratchpad). Data must be transmitted least significant bit first. Both bytes MUST be
written before the master issues a reset, or the data may be corrupted.
READ SCRATCHPAD [BEh]This command allows the master to read the contents of the scratchpad. The data transfer starts with theleast significant bit of byte 0 and continues through the scratchpad until the 9th byte (byte 8 – CRC) isread. The master may issue a reset to terminate reading at any time if only part of the scratchpad data isneeded.
COPY SCRATCHPAD [48h]This command copies the contents of the scratchpad TH and TL registers (bytes 2 and 3) to EEPROM. If
the device is being used in parasite power mode, within 10ms (max) after this command is issued themaster must enable a strong pullup on the 1-Wire bus for at least 10ms as described in the POWERINGTHE DS18S20 section.
RECALL E2 [B8h]This command recalls the alarm trigger values (TH and TL) from EEPROM and places the data in bytes 2
and 3, respectively, in the scratchpad memory. The master device can issue read-time slots following the
Recall E2 command and the DS18S20 will indicate the status of the recall by transmitting 0 while therecall is in progress and 1 when the recall is done. The recall operation happens automatically at powerup, so valid data is available in the scratchpad as soon as power is applied to the device.
10 of 21

DS18S20

READ POWER SUPPLY [B4h]
The master device issues this command followed by a read-time slot to determine if any DS18S20s on thebus are using parasite power. During the read-time slot, parasite powered DS18S20s will pull the bus low,
and externally powered DS18S20s will let the bus remain high. Refer to the POWERING THE DS18S20
section for usage information for this command.

DS18S20 FUNCTION COMMAND SET Table 4
1-Wire Bus Activity
Description
ProtocolAfter Command is Issued
TEMPERATURE CONVERSION COMMANDS
Convert T
Initiates temperature
44h
DS18S20 transmits conversion
conversion.
status to master (not applicablefor parasite-powered DS18S20s).
MEMORY COMMANDS
Read Scratchpad Reads the entire scratchpad
BEh
DS18S20 transmits up to 9 data
including the CRC byte.
bytes to master.
Write Scratchpad Writes data into scratchpad
4Eh
Master transmits 2 data bytes tobytes 2 and 3 (TH and TL).
DS18S20.
Copy Scratchpad Copies TH and TL data from48hNone
the scratchpad to EEPROM.
2
Recalls TH and TL data from
B8h
DS18S20 transmits recall status
Recall E
EEPROM to the scratchpad.
to master.
Read Power
Signals DS18S20 power
B4h
DS18S20 transmits supply status
Supplysupply mode to the master.
to master.
Command

Notes
1

2
3
1

NOTES:
1) For parasite-powered DS18S20s, the master must enable a strong pullup on the 1-Wire bus during
temperature conversions and copies from the scratchpad to EEPROM. No other bus activity may takeplace during this time.
2) The master can interrupt the transmission of data at any time by issuing a reset.
3) Both bytes must be written before a reset is issued.

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DS18S20

1-WIRE SIGNALINGThe DS18S20 uses a strict 1-Wire communication protocol to insure data integrity. Several signal types
are defined by this protocol: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. All of thesesignals, with the exception of the presence pulse, are initiated by the bus master.

INITIALIZATION PROCEDURE: RESET AND PRESENCE PULSESAll communication with the DS18S20 begins with an initialization sequence that consists of a reset pulse
from the master followed by a presence pulse from the DS18S20. This is illustrated in Figure 10. When
the DS18S20 sends the presence pulse in response to the reset, it is indicating to the master that it is on
the bus and ready to operate.
During the initialization sequence the bus master transmits (TX) the reset pulse by pulling the 1-Wire bus
low for a minimum of 480ms. The bus master then releases the bus and goes into receive mode (RX).
When the bus is released, the 5k pullup resistor pulls the 1-Wire bus high. When the DS18S20 detects
this rising edge, it waits 15ms to 60ms and then transmits a presence pulse by pulling the 1-Wire bus low
for 60ms to 240ms.

INITIALIZATION TIMING Figure 10
MASTER TX RESET PULSEMASTER RX
480ms minimum
DS18S20 TX
presence pulse
60-240 ms

480ms minimum

VPU

DS18S20
waits 15-60 ms

1-WIRE BUS
GND
LINE TYPE LEGENDBus master pulling low
DS18S20 pulling low
Resistor pullup

READ/WRITE TIME SLOTSThe bus master writes data to the DS18S20 during write time slots and reads data from the DS18S20
during read-time slots. One bit of data is transmitted over the 1-Wire bus per time slot.

WRITE TIME SLOTS
There are two types of write time slots: “Write 1” time slots and “Write 0” time slots. The bus masteruses a Write 1 time slot to write a logic 1 to the DS18S20 and a Write 0 time slot to write a logic 0 to the
DS18S20. All write time slots must be a minimum of 60ms in duration with a minimum of a 1ms recovery
time between individual write slots. Both types of write time slots are initiated by the master pulling the
1-Wire bus low (see Figure 11).
To generate a Write 1 time slot, after pulling the 1-Wire bus low, the bus master must release the 1-Wirebus within 15ms. When the bus is released, the 5k pullup resistor will pull the bus high. To generate a
Write 0 time slot, after pulling the 1-Wire bus low, the bus master must continue to hold the bus low for
the duration of the time slot (at least 60ms). The DS18S20 samples the 1-Wire bus during a window thatlasts from 15ms to 60ms after the master initiates the write time slot. If the bus is high during the sampling
window, a 1 is written to the DS18S20. If the line is low, a 0 is written to the DS18S20.
12 of 21

DS18S20

READ-TIME SLOTSThe DS18S20 can only transmit data to the master when the master issues read-time slots. Therefore, themaster must generate read-time slots immediately after issuing a Read Scratchpad [BEh] or Read Power
Supply [B4h] command, so that the DS18S20 can provide the requested data. In addition, the master can
generate read-time slots after issuing Convert T [44h] or Recall E2 [B8h] commands to find out the statusof the operation as explained in the DS18S20 FUNCTION COMMAND section.
All read-time slots must be a minimum of 60ms in duration with a minimum of a 1ms recovery time
between slots. A read-time slot is initiated by the master device pulling the 1-Wire bus low for aminimum of 1ms and then releasing the bus (see Figure 11). After the master initiates the read-time slot,
the DS18S20 will begin transmitting a 1 or 0 on bus. The DS18S20 transmits a 1 by leaving the bus highand transmits a 0 by pulling the bus low. When transmitting a 0, the DS18S20 will release the bus by theend of the time slot, and the bus will be pulled back to its high idle state by the pullup resister. Output
data from the DS18S20 is valid for 15ms after the falling edge that initiated the read-time slot. Therefore,
the master must release the bus and then sample the bus state within 15ms from the start of the slot.
Figure 12 illustrates that the sum of TINIT, TRC, and TSAMPLE must be less than 15ms for a read-time slot.
Figure 13 shows that system timing margin is maximized by keeping TINIT and TRC as short as possible
and by locating the master sample time during read-time slots towards the end of the 15ms period.

READ/WRITE TIME SLOT TIMING DIAGRAM Figure 11
START
OF SLOTSTARTOF SLOTMASTER WRITE “0” SLOTMASTER WRITE “1” SLOT

1ms < TREC < ¥60ms < TX “0” < 120ms

> 1ms

VPU
1-WIRE BUS
GND
DS18S20 Samples
MIN

15ms

DS18S20 Samples

TYP

15ms

MAX

MIN

15ms

30ms

MASTER READ “0” SLOT

TYP

15ms

30ms

MASTER READ “1” SLOT
1ms < TREC < ¥VPU
1-WIRE BUS
GND> 1 msMaster samples

Master samples

> 1ms
15ms

MAX

45ms

15ms

LINE TYPE LEGENDBus master pulling low
Resistor pullup

13 of 21

DS18S20 pulling lowDS18S20

DETAILED MASTER READ 1 TIMING Figure 12
VPU
VIH of Master

1-WIRE BUS
GND
TINT > 1ms

TRC

Master samples

15ms

RECOMMENDED MASTER READ 1 TIMING Figure 13
VPU
VIH of Master

1-WIRE BUS
GND

Master samples

TINT = TRC =small small
15ms

LINE TYPE LEGENDBus master pulling low
Resistor pullup

14 of 21

DS18S20

ROM COMMANDS FLOW CHART Figure 14
Initialization
Sequence

MASTER TX
RESET PULSEDS18S20 TX
PRESENCE
PULSE

MASTER TX ROM
COMMAND

33h
READ ROM
COMMANDY

N

55h
MATCH ROM
COMMAND

F0h
SEARCH ROM
COMMAND

N

Y

Y

N

ECh
ALARM SEARCHCOMMANDNYYMASTER TX
BIT 0

DS18S20 TX BIT 0

DS18S20 TX BIT 0

DS18S20 TX BIT 0

DS18S20 TX BIT 0

MASTER TX BIT 0

MASTER TX BIT 0

BIT 0
MATCH?

DEVICE(S)WITH ALARM
FLAG SET?

DS18S20 TX
FAMILY CODE
1 BYTEN

BIT 0
MATCH?
DS18S20 TX
SERIAL NUMBER
6 BYTES

N

Y

Y

Y

DS18S20 TX BIT 1
DS18S20 TX
CRC BYTE

MASTER TX
BIT 1

DS18S20 TX BIT 1
MASTER TX BIT 1

BIT 1
MATCH?

NN

BIT 1
MATCH?
YY

DS18S20 TX BIT 63
MASTER TX
BIT 63

DS18S20 TX BIT 63
MASTER TX BIT 63

N
BIT 63
MATCH?

YN
BIT 63
MATCH?
Y

MASTER TX
FUNCTION
COMMAND(FIGURE 15)

15 of 21CCh
SKIP ROM
COMMAND

NN

DS18S20

DS18S20 FUNCTION COMMANDS FLOW CHART Figure 15
44h
CONVERTTEMPERATURE?

MASTER TX
FUNCTION
COMMAND

48h
COPY
SCRATCHPAD
?

N

Y

Y

N

PARASITE
POWER?

DS18S20 BEGINSCONVERSION

DEVICECONVERTINGTEMPERATURE?

N

COPY IN
PROGRESS?

MASTER DISABLESSTRONG PULLUPMASTERRX “0s”

MASTERRX “1s”

PARASITE
POWERED?

N

Y

MASTER DISABLESSTRONG PULLUP

B4h
READ
POWER SUPPLY?

NYDATA COPIED FROMSCRATCHPAD TO EEPROM

N

B8h
RECALL E2?

MASTERRX “1s”

BEh
READ
SCRATCHPAD
?

N

Y

Y

N

PARASITE
POWER?

MASTER ENABLESSTRONG PULL-UP ON DQ

DS18S20 CONVERTSTEMPERATURE

MASTERRX “0s”

N

Y

MASTER ENABLESSTRONG PULLUP ON DQ

Y

N

N

Y

Y
MASTER TX TH BYTETO SCRATCHPADMASTER RX DATA BYTEFROM SCRATCHPADYMASTER BEGINS DATARECALL FROM E2 PROM

4Eh
WRITE
SCRATCHPAD?

MASTER TX TL BYTETO SCRATCHPADMASTERRX “1s”

MASTERRX “0s”

MASTERTX RESET?
DEVICE
BUSY RECALLING
DATA
?

N

N

N

Y

MASTERRX “0s”

Y

MASTERRX “1s”

HAVE 8 BYTESBEEN READ?
Y

MASTER RX SCRATCHPADCRC BYTE

RETURN TO INITIALIZATIONSEQUENCE (FIGURE 14) FOR
NEXT TRANSACTION

16 of 21

DS18S20

DS18S20 OPERATION EXAMPLE 1
In this example there are multiple DS18S20s on the bus and they are using parasite power. The bus
master initiates a temperature conversion in a specific DS18S20 and then reads its scratchpad andrecalculates the CRC to verify the data.
MASTER MODE
TX
RX
TX
TX
TX
TX
TX
RX
TX
TX
TX
RX

DATA (LSB FIRST)
Reset
Presence55h64-bit ROM code44h
DQ line held high bystrong pullup
Reset
Presence55h64-bit ROM codeBEh
9 data bytes

COMMENTS
Master issues reset pulse.
DS18S20s respond with presence pulse.
Master issues Match ROM command.
Master sends DS18S20 ROM code.
Master issues Convert T command.
Master applies strong pullup to DQ for the duration of theconversion (tconv).
Master issues reset pulse.
DS18S20s respond with presence pulse.
Master issues Match ROM command.
Master sends DS18S20 ROM code.
Master issues Read Scratchpad command.
Master reads entire scratchpad including CRC. The masterthen recalculates the CRC of the first eight data bytes from thescratchpad and compares the calculated CRC with the read
CRC (byte 9). If they match, the master continues; if not, theread operation is repeated.

DS18S20 OPERATION EXAMPLE 2
In this example there is only one DS18S20 on the bus and it is using parasite power. The master writes to
the TH and TL registers in the DS18S20 scratchpad and then reads the scratchpad and recalculates the
CRC to verify the data. The master then copies the scratchpad contents to EEPROM.
MASTER MODE
TX
RX
TX
TX
TX
TX
RX
TX
TX
RX

DATA (LSB FIRST)
Reset
PresenceCCh
4Eh
2 data bytes
Reset
PresenceCChBEh
9 data bytes

TX
RX
TX
TX
TX

Reset
PresenceCCh48h
DQ line held high bystrong pullup

COMMENTS
Master issues reset pulse.
DS18S20 responds with presence pulse.
Master issues Skip ROM command.
Master issues Write Scratchpad command.
Master sends two data bytes to scratchpad (TH and TL)
Master issues reset pulse.
DS18S20 responds with presence pulse.
Master issues Skip ROM command.
Master issues Read Scratchpad command.
Master reads entire scratchpad including CRC. The master thenrecalculates the CRC of the first eight data bytes from thescratchpad and compares the calculated CRC with the read CRC(byte 9). If they match, the master continues; if not, the read
operation is repeated.
Master issues reset pulse.
DS18S20 responds with presence pulse.
Master issues Skip ROM command.
Master issues Copy Scratchpad command.
Master applies strong pullup to DQ for at least 10ms while copy
operation is in progress.
17 of 21

DS18S20

DS18S20 OPERATION EXAMPLE 3
In this example there is only one DS18S20 on the bus and it is using parasite power. The bus masterinitiates a temperature conversion then reads the DS18S20 scratchpad and calculates a higher resolution
result using the data from the temperature, COUNT REMAIN and COUNT PER °C registers.
MASTER MODE
TX
TR
TX
TX
TX
TX
RX
TX
TX
RX

DATA (LSB FIRST)
Reset
PresenceCCh44h
DQ line held high bystrong pullup
Reset
PresenceCChBEh
9 data bytes

TX
RX
-

Reset
Presence-

COMMENTS
Master issues reset pulse.
DS18S20 responds with presence pulse.
Master issues Skip ROM command.
Master issues Convert T command.
Master applies strong pullup to DQ for the duration of theconversion (tconv).
Master issues reset pulse.
DS18S20 responds with presence pulse.
Master issues Skip ROM command.
Master issues Read Scratchpad command.
Master reads entire scratchpad including CRC. The masterthen recalculates the CRC of the first eight data bytes from thescratchpad and compares the calculated CRC with the read
CRC (byte 9). If they match, the master continues; if not, theread operation is repeated. The master also calculates the
TEMP_READ value and stores the contents of the COUNTREMAIN and COUNT PER °C registers.
Master issues reset pulse.
DS18S20 responds with presence pulse.
CPU calculates extended resolution temperature using theequation in the OPERATION — MEASURING
TEMPERATURE section of this datasheet.

18 of 21

DS18S20

ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature Range
Storage Temperature Range
Solder Temperature
Reflow Oven Temperature-0.5V to +6.0V-55°C to +125°C-55°C to +125°C
See IPC/JEDEC J-STD-020A+220°C*These are stress ratings only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.

DC ELECTRICAL CHARACTERISTICS(-55°C to +125°C; VDD = 3.0V to 5.5V)

PARAMETER
Supply Voltage
Pullup Supply
Voltage
Thermometer Error

MIN
+3.0
+3.0
+3.0

Input Logic Low
Input Logic High

Sink Current
Standby Current
Active Current
DQ Input Current
Drift

SYMBOL
VDD
VPU
tERR

VIL
VIH

IL
IDDS
IDD
IDQ

CONDITION
Local Power
Parasite Power
Local Power-10°C to+85°C
-55°C to+125°C

TYP

MAX
+5.5
+5.5
VDD
±0.5

UNITS NOTES
V
1
V
1, 2
°C

3

V
V

1, 4, 5
1, 6

mA
nA
mA
µA
°C

1
7, 8
9
10
11

±2

Local Power

-0.3
+2.2

Parasite Power+3.0

VI/O=0.4V

4.0

VDD=5V+0.8
The lower of
5.5
or
VDD + 0.3
750
1
5
±0.2

1000
1.5

NOTES:
1) All voltages are referenced to ground.
2) The Pullup Supply Voltage specification assumes that the pullup device is ideal, and therefore thehigh level of the pullup is equal to VPU. In order to meet the VIH spec of the DS18S20, the actual
supply rail for the strong pullup transistor must include margin for the voltage drop across thetransistor when it is turned on; thus: VPU_ACTUAL = VPU_IDEAL + VTRANSISTOR.
3) See typical performance curve in Figure 16
4) Logic low voltages are specified at a sink current of 4mA.
5) To guarantee a presence pulse under low voltage parasite power conditions, VILMAX may have to be
reduced to as low as 0.5V.
6) Logic high voltages are specified at a source current of 1mA.
7) Standby current specified up to 70°C. Standby current typically is 3mA at 125°C.
8) To minimize IDDS, DQ should be within the following ranges: GND £ DQ £ GND + 0.3V or VDD –0.3V £ DQ £ VDD.
9) Active current refers to supply current during active temperature conversions or EEPROM writes.
10) DQ line is high (“hi-Z” state).
11) Drift data is based on a 1000 hour stress test at 125°C with VDD = 5.5V.
19 of 21

DS18S20

AC ELECTRICAL CHARACTERISTICS: NV MEMORY(-55°C to +100°C; VDD = 3.0V to 5.5V)
PARAMETER
NV Write Cycle Time
EEPROM Writes
EEPROM Data Retention

SYMBOL
twr
NEEWR
tEEDR

CONDITION

MIN-55°C to +55°C-55°C to +55°C

50k
10

AC ELECTRICAL CHARACTERISTICSPARAMETER
Temperature Conversion
Time
Time to Strong Pullup On
Time Slot
Recovery Time
Write 0 Low Time
Write 1 Low Time
Read Data Valid
Reset Time HighReset Time Low
Presence Detect High
Presence Detect Low
Capacitance

TYP
2

MAX
10

(-55°C to +125°C; VDD = 3.0V to 5.5V)

SYMBOLtCONVCONDITIONMIN TYP MAX
750

tSPON

Start Convert T
Command Issued

10

µs

120

µs
µs
µs
µs
µs
µs
µs
µs
µs
pF

tSLOT
tREC
rLOW0
tLOW1
tRDV
tRSTH
tRSTL

60
1
60
1

UNITS
ms

120
15
15

480
480
15
60

tPDHIGHtPDLOW
CIN/OUT60
240
25

NOTES:
1) Refer to timing diagrams in Figure 17.
2) Under parasite power, if tRSTL > 960ms, a power on reset may occur.

TYPICAL PERFORMANCE CURVE Figure 16

DS18S20 Typical Error Curve
0.5
0.4+3s Error

0.3
0.2
0.1
0
-0.1 0

10

20

30

40

50

60

-0.2
-0.3
-0.4

UNITS
ms
writesyears

Mean Error-3s Error-0.5
Temperature (°C)

20 of 21

70

NOTES
1

1
1
1
1
1
1
1, 2
1
1

DS18S20

TIMING DIAGRAMS Figure 17

21 of 21