IEEE 2008 Custom Intergrated Circuits Conference (CICC)

1/5 Power Reduction by Global Optimization basedon Fine-Grained Body Biasing
Yasumi Nakamura, David Levacq, Limin Xiao, Takuya Minakawa, Taro Niiyama, Makoto Takamiya, andTakayasu Sakurai
The University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan

II. LOCAL OPTIMIZATION VS GLOBAL OPTIMIZATION
Chip

f1_tuned

f2_tuned

f3_tuned

f4_tuned

VB3

VB4

Bias
Gen.
VBN ,V BP

0.001
0.01
0.1
Spatial frequency (1/µm)

Control VBi Æ Minimize power
while chip works at desired freq.

Fig.2. Local optimization (Left) and global optimization (Right).
VDD

Test
Start

1000
Transistor
Array

Control
Voltage

Same 90nm
CMOS process

2x 32bit
LFSR
64
64bit
DES
CODEC 1
64
64bit
DES
CODEC 24x 16step
Sig. Gen

Freq
mon.

VBN1, VBP1

Freq
mon.

VBN2, VBP2

Freq
mon.
Freq
mon.
Freq
mon.
Freq
mon.

Freq Out(just for test purpose)

4mm (4000 transistors)

Spectrum of VTH (A.U.)

VB4 Bias selector

Global optimization

4mm

0

VB3

Control VBiÆ f1=f2=…=fn after tuning

Reset &Counter1

VBH VBL

VB2

Local optimization

100

10

Critical path

VB1

Bias vector register:- Selects either VBH or VBL foreach block- Best bias assignment isdetermined by global chip test
- Critical path will go throughmultiple of bias domains

Freq. (f) monitor:
NAND ring Osc.

Scan
Out
(Pass/Fail)

Fourier transform of VTH

VB2

Mon

VB1

Mon

Chip

8 blocks are divided just by
area, not by function

The adaptive substrate bias control and the post-fabrication
tuning of parameters [1-4] are the recent trend in designing
power-efficient LSI’s to cope with the increasing random
device variability. The systematic design variation, which isthe error between the simulation results at a design stage andthe measured results of a fabricated chip, is also getting animportant issue. This is partly because the chip is getting more
and more complicated and delay estimation gets inherently
more difficult and partly because the recent process introduces
systematic delay deviation from designed value by new
phenomena such as stress-induced drain current variation andimperfect optical proximity correction.
In the post-fabrication tuning, the parameters can be either
locally or globally optimized. [4] shows a local optimization
example of the body bias by monitoring critical path replicas
in the 21 domains. Local optimization means that theparameter is locally optimized by looking at the local value ofthe parameter and modifying it to the designed value. Thisapproach, however, cannot compensate the systematic
variations and has the mismatch between the critical path
replica and the real critical path. This approach may not work

Mon

I. INTRODUCTION

for cases where short-range correlated variation is small as isshown in Fig.1 which shows that there is no specific peak inslow spatial frequencies.
In contrast, [1-3] show the global optimization of the clock
skew in the 52 clock domains [1]. In this approach, however,
the required tunable skew circuits consume power and theskew tuning does not reduces the leakage of the circuits.
In this paper, a fine-grained body bias control tocompensate both the random (process) and systematic (design)
variations is proposed and the globally minimized power at aconstant performance is investigated through measurements.

Mon

Abstract-A fine-grained body bias control to compensate both theprocess and design variations is proposed. A test chip was
fabricated in 90nm CMOS process. The proposed global
optimization scheme reduced power by 23% compared with an
as-fabricated chip power and by 11% compared with the power
optimized by the conventional local optimization approach. Also,
the proposed global optimization scheme reduced power by 19%
compared with an as-fabricated chip power within 20 test
iterations with simulated annealing algorithm.

Freq
mon.
Freq
mon.

VBN8, VBP8On-Chip
VCO
/ 128

VCO
Freq

Fig. 3. Block diagram of the fabricated test chip.

Fig. 1. Spectrum of within-die process variation

978-1-4244-2018-6/08/$25.00 ©2008 IEEE

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There are two approaches to determine the body bias
values for each biasing region (Fig.2). One is the local
optimization scheme, which aims at making VTH of all theregions is equal to compensate within-die VTH variations [4].
The other is the proposed global optimization scheme,
which aims at achieving the lowest power consumption while
the real critical path can operate at the desired frequency. RealPower reduction

0%

Designwith HDL
Logic
Synthesis

Block #1

-20%

-0.2

-0.15
was
chosen-0.1

0

VBL-VBH[V]Fig. 6. Measured VBH-VBL – power dependence for 6 chips. This is for
PMOS well bias and similar optimization is done for NMOS.

Placement withblockage

Block #8
Divided to blocks just by
area, not by function.
Blocks are separated bywell separation.

Verification

Fig. 4. Design flow of the test chip

VN1 VP1VN2 VP2VN3 VP3VN4 VP4VN5 VP5
VN6 VP6
VN7 VP7VN8 VP8

Fig.5. Chip layout (up) and micrograph of fabricated chip (down)
Table 1 Summary of the fabricated chip
1V 90nm CMOS
2400um x 2400um# of gates 1M gates
Test

-15%

-30%
-0.3

Use standard design
flow other than P&R

Biasing Area
Division

Process
Area

-10%

-25%

Place & Route

Time-driven
Routing-5%

BIST (Built-In Self-Test) with 4-bit
16step signature generator

critical paths are tested at a chip level. The global optimization
can compensate not only the process variation but also thesystematic design variation. This can be used as a method forpost-fabrication clock skew tuning (time borrowing) without
introducing parametric delay component which is large.
To evaluate the effect of the fine-grain global body bias
optimization, a test chip was fabricated in 1V 90nm CMOS
and measured. Fig. 3 shows the block diagram of the test chip.
The circuit under test is two series-connected 64bit DES
CODECs, which is driven by 2 32bit LFSR input vector
generator, and 4 out of 64bit output are compacted with 16step
signature generator. The chip has 8 body bias domains andeach region has a 31-stage FO3 NAND ring oscillator divided
by 64 as a frequency monitor. Test is carried out with a PC
with 16ch D/A board which generate the body bias voltages.
The design flow is shown in Fig.3. The only difference
between a normal digital circuit and the proposed circuit is todivide the chip into multiple body biasing domains. In the test
chip, this division is done just by area and not by function.
This means that any division can be made without considering
the functional borders and can be applied to any chip.
The micrograph and layout of the fabricated chip is shownin Fig.5. As shown in Table 1, it occupies 2400um x 2400um
in area.
III. METHODS FOR DETERMING VB VECTOR
Since each body bias voltage (VBP1~8 for PMOS and VBN1~8
for NMOS) can take any analog value, finding the best value
to obtain the lowest power out of millions of patterns isdifficult. In this paper, each body bias voltage is limited to“high” or “low”, namely VBH and VBL. VBH is set to the lowest
value
where
the
chip
can
operatewhen
VBN1=VBN2=…=VBN8=VBP1=…=VBP8= VBH.
VBL is then set to VBH-0.15V. Fig. 5 shows the reason, theVBL-VBH – Power reduction ratio dependence for 6 chips. Here,power reduction ratio = 0 when the power consumption issame as with the worst case VBH or the VBH where all the chips
can operate. Power reduction ratio shows a gentle minimum
between -0.2V and -0.1V for various chips.
Three methods are tried to determine the VB vector,
exhaustive search, best vector LUT and simulated annealing.

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140

Assign all regions to low VT, initialize temp
Power consumption [mW]

135

While i < desired iteration
Decide the number of regions to be changed
Number is proportional to e-temp
Randomly decide the region to be changed
Flip low VT / high VT

HL HHLRun built-in test

HL L HL

L HL
L HH

- 23%

125
120

Chip by chip

115

- 11%

110
105

Fine grain

100
95

No

Passed?

As fabricated

130

90
As
N1P1
Fabricated Exhau.

Yespwr_new < pwr_old?

Yespwr_new= Power. + Penalty

No
Probability ofe-Δpwr_old / temp

Adopt new set of VT

Other

Discard changes

Decrease temp

Fig. 6. Simulated annealing algorithm applied to the test chip
N1P1

N1P4

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8

N

N

P

P

N1P8

N1P4
Exhau.

N1P8
N1P8
Exhau. Sim.An

N8P8
Sim.AnFig. 8. Measured relationship between grain size and power consumption% variation of osc. frequency

pwr_new= Power consumption

N1P2
Exhau.

8%
6%
4%

Beforeoptimization

2%

8%
6%
4%

After
optimization

2%

0%

0%

-2%

-2%

-4%

-4%
1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8

Block #

Block #

Fig. 9. NAND ring monitor frequency for each bias block. Each line
corresponds to a chip

N8P8

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8

N

N

P

P

The difference among there three methods are shown in
the following section.

Fig. 7. Bias domain division and its name

A. Exhaustive Enumeration
The simplest way to find the best vector to reduce power is
to test all possible vectors. It is possible for small number ofregions, though, even for 8 regions or 16 parameters (VBN, VBP
x 8), 65536 tests are required, which is not practical if thenumber of domains are large.
B. Best Vector LUT
An alternative method is to apply the exhaustive test (orlong-series simulated annealing) in the development stage andfind out the best vector look-up table (LUT) for each VTN, VTP.
This will take time in the development stage but once the LUT
is established, there is not test time overhead in each die test.
C. Simulated Annealing
Simulated annealing is an algorithm to find a global
minimum value in large search space by stochastic approach.
To apply simulated annealing to this bias vector optimization,
the algorithm shown in Fig. 6 is adopted. The key point here isto add a “penalty constant” to the consumed power if thecircuit fails since if the circuit fails to operate at the desired
frequency, the bias vector is “very bad” even if the power islow. With the introduction of the penalty, the search becomesa simple bound-free minimum search.

IV. MEASUREMENT RESULTS
In this section, the word “NiPj” denotes that there are ibias domains for NMOS and j bias domains for PMOS asshown in Fig. 7.
First, the relationship between grain size and power
consumption is shown in Fig. 8(a). Since the within-die
process variation is small and random (see Fig. 9), the same
bias is happed to be set to all the bias domains. From thefigure, it is clear that the finer the grain size is, the lower the
power consumption becomes. N1P8 bias control is shown to
reduce 23% of the power consumption compared with asfabricated chip without post-tuning.
NAND ring oscillation frequency at the lowest power
consumption in N1P8 exhaustive search is shown in Fig. 9.
From this, it is seen that within-die variations are below 3%
while design variations goes up to 10% which is seen from thefigure at right hand side.
The measured relationship between number of test
iterations and the power reduction in the proposed simulated
annealing method for one chip is shown in Fig. 10. Within 20
iterations, more than 19% power reduction is achieved.
Fig. 11 shows the comparison among the three methods forN1P8 parameter set. The power reduction efficiency of one
certain chip is compared the methods themselves. Exhautive
search of course shows the best result of 29% power reduction
but it may not be practical in cases because the test timeincrease is considerably increased. On the other hand, by using

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As-fabricated

50
N8P8

Area overhead (%)

Simulated
Annealing

-5%
-10%

>19% power reduction
at 20 iterations

-15%
-20%
-25%
0

5

10

15

20

25

30

35

40

Block #1
Block #2
Block #3

30
20

Block #n100

Iteration count [times]

10
20
30
1
n: Number of blocks (bias domains)

Fig. 10. Measured iteration – power characteristics in simulated
annealing

Fig. 12. Number of blocks vs area overhead (calculated)

0%Power reduction ratio

40

5mm
Total logic size

0%

-5%
-10%

power optimized by the conventional local optimization
approach. Also, the proposed global optimization scheme
reduced power by 19% compared with as-fabricated chip
power within 20 test iterations with simulated annealing
algorithm. The best vector LUT approach is also practical. The
proposed schemes are considered to be promising forachieving the power-efficient LSI’s in scaled devices withreasonable area and test overhead.

-15%
-20%
-25%
-30%
-35%
As-fabricatedExhaustive

Best vector Simulated
LUT
annealing

Fig. 11. Comparison among exhaustive search, LUT, and simulated
annealing (N1P8)ACKNOWLEDGMENTS
simulated annealing, the shorter test time is expected and thepower reduction ratio stays the same as 28%. As to the best
vector LUT approach, the power reduction ratio is 28% and in
this look-up table approach, no test time overhead is needed
since the time-consuming optimization efforts are made only
once in the development stage. In measuring this value, thebest vector is not the best vector for the specific chip but it is
the best vector for the chip set.
IV. DISCUSSIONSIn order to divide a logic circuit into multiple bias blocks,
extra area for well separation is required. Fig. 12 shows therelationship between the number of division and the area
overhead caused by this well separation. In the fabricatedprocess, this overhead does not exceed 5% until 12 divisions
for 5mm x 5mm chip.
V. CONCLUSION
The fine-grained body bias control to compensate both therandom (process) and systematic (design) variations was
proposed and the effectiveness was demonstrated with the 90
nm CMOS test chips. The proposed scheme compensates dieto-die VTH variation and the systematic design variations.
Undesired inequality of critical path delay among pipeline
stages are compensated in this scheme. Compared with asfabricated chip, proposed global optimization approach
reduces the power by 23% and by 11% compared with theThis work is partially supported by MEXT and Hitachi,Ltd. The VLSI chips were fabricated through the chip
fabrication program of VLSI Design and Education Center(VDEC), the University of Tokyo, with the collaboration by
STARC, Fujitsu Limited, Matsushita Electric Industrial
Company Limited., NEC Electronics Corporation, Renesas
Technology Corporation, and Toshiba Corporation.
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