Effect of Resistance of TSV’s on Performance ofBoost Converter for Low Power 3D SSD withNAND Flash Memories
Tadashi Yasufuku1, Koichi Ishida1, Shinji Miyamoto2, Hiroto Nakai2,Makoto Takamiya1, Takayasu Sakurai1, and Ken Takeuchi1
1

University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo, Japan, 153-8505
2Toshiba Corporation, Yokohama, Japan

Abstract- This paper investigates the effect of the TSVresistance (RTSV) on the performance of boost converters for
Solid State Drive (SSD) using circuit simulation. When RTSV is0Ω, both the rising time (trise) from 0V to 15V and the energy
during boosting (Eloss) of the output voltage (VOUT) are 10.6%
and 6.6% of the conventional charge pump respectively. Incontrast, when RTSV is 200Ω, for example, trise is 30.1% and Eloss
is 22.8% of the conventional charge pump. Besides, VOUT
cannot be boosted above 20V when RTSV is larger than 210Ω.
Therefore, in order to maintain the advantages of the boost
converter over the charge pump in terms of trise and Eloss, thereduction of RTSV is very important.

NAND
controller

Interposer
NAND
flashChargepumpDRAM

1. IntroductionOne of the serious design issues of SSD is theincreasing power consumption. Fig. 1 shows a device
architecture of a conventional SSD. A typical SSD consistsof more than 16 NAND flash memories, DRAM’s and a
NAND controller. In SSD, each NAND flash chip has acharge pump circuit to generate the program voltage of 20V.
Fig. 2 shows a schematic and issues of the charge pump togenerate the program voltage (VOUT). The charge pumpprevents the area reduction, the VDD scaling, and the fast
write-operation of the NAND flash memory [1]. Forexample, 5 to 10 ％ area of each NAND flash chip isoccupied by the charge pump due to its large capacitance,
which raises the cost of SSD. Therefore, new alternative highvoltage generation circuit is strongly required to reduce thearea, the power, and the write-time of the NAND flash
memory.
Fig. 3 shows a 3D-integrated SSD proposed in [1]. The
NAND flash memories, DRAM’s, the NAND controller, anda boost converter are integrated in SiP. Through silicon vias(TSV’s) are assumed as the connection of the boost
converter and each NAND chip. Fig. 4 shows a schematic
diagram of the boost converter which consists of two
high-voltage nMOS transistors and an inductor. In theproposed 3D SSD, both the low power and the fast
write-operation are achieved, because both the voltage
conversion efficiency and the output current drivability ofthe boost converter are higher than those of the charge pump.
The die area of the NAND flash memory is also reduced,
because the charge pumps on each flash memory are merged
into the boost converter on an interposer.
In [1], the advantage of the boost converter over thecharge pump was shown by measurements. The feasibility of

978-1-4244-4512-7/09/$25.00 ©2009 IEEE

978-1-4244-4512-7/09/$25.00 ©2009 IEEEFig. 1. Conventional 3D-SSD with charge pump.
Serial MOS diodes lose energy.
Large number of stages for low VDD
VDD

VOUT =20V

Clk
Clk

Large capacitancefor large current

Fig. 2. Schematic and issues of the charge pump.

the 3D SSD with TSV connections, however, is not clear,because the measurement does not take into account theparasitic RLC’s accompanying TSV’s. In reality, when3D-SSD’s are implemented using TSV’s, the parasitic
RLC’s may degrade the performance of the boost converter.
The parasitic L and C of the TSV’s, however, can beneglected, because the parasitic L and C are under 0.03% and
1% of the inductance of the inductor and the output load
capacitance, respectively, of the boost converter [2]. Incontrast, the parasitic resistance of TSV’s (RTSV) cannot bedisregarded.
Therefore, in this paper, the impact of RTSV on theperformance of the boost converter (output voltage (VOUT),
rising time (trise), and energy during boosting (Eloss)) issimulated using SPICE. The performance is also comparedwith that of the conventional charge pump.

Shared boost converter

Controller
for boostconverter

NAND
controller

Spiral High-voltage
MOS
inductor

Smallerdie sizeInterposer

Chargepump
TSV’sCharge
pump

NAND
flash

DRAM.
Fig. 3. Proposed 3D-SSD with boost converter.
High-voltage MOS

TON

VDD

TOFF

VOUT
Clk

Frequency = 1 / (TON + TOFF)
Duty cycle = TON / (TON + TOFF)

Fig. 4. Circuit diagram of boost converter.

2. Effect of TSV’s on performance of boostconverterRTSV is determined by TSV materials, the thickness ofNAND chips and the number of stacked NAND chips. For
example, the resistance of Cu TSV’s with a diameter of
2~5μm and a height of 5µm is 80~200mΩ/via [3], while theresistance of doped poly-Si TSV with a diameter of
28~46µm and a height of 50µm is 1.3~5.0Ω/via [4].
Considering the thickness of a NAND chip which is assumed
as 35μm, the resistance of Cu TSV’s per NAND chip is0.56~1.4Ω, and the resistance of poly-Si TSV is 0.91~3.5Ω.
In a 64 chip stacked SSD where a boost converter isconnected to all the chips using only one TSV, the maximum
total RTSV becomes 224Ω (poly-silicon TSV) and 89.6Ω
(copper TSV). Therefore, RTSV up to 250Ω is considered in

VDD=1.8V

IRTSV

270nH
Rind=0.51Ω

Iin

R1

R2Clock

R5

VOUT = 20V

RWL

RWL

VWL

RWL

RTSV
CL=160pF

3.6V
Period = 55ns
Duty = 80%

R4

this section.
Fig. 5 shows the equivalent circuit of the simulated boost
converter. Input voltage (VDD) is 1.8V, and the target output
voltage (VOUT) is 20V. A NAND flash chip as the output loadof the boost converter is emulated by the load resistance(RL=1MΩ) and capacitance (CL=160pF). The resistance andcapacitance of the word line of the NAND flash chip is also
considered using distributed RC lines in order to compare
RC delay due to word lines and RC delay due to RTSV. The
total resistance of word lines (RWLtotal) is 500kΩ, thereby
RWL is 166.7kΩ. The total capacitance of word lines(CWLtotal) is 2pF, thereby CWL1 is 0.333pF and CWL2 is0.666pF. The voltage of the node after distributed RC line ofword lines is defined as VWL. VWL also need to be boosted up
to 20V. Parasitic resistance of the interconnects (R1-R5) andthe inductor (RInd) are also included. Switching frequency (orperiod) and duty cycle are 18.2MHz (55ns) and 80%
respectively, and the amplitude of the clock is 3.6V. RTSV isserially connected directly after R5. The current which flows
into RTSV is defined as IRTSV. A 270nH-inductor is used basedon the result of [5]. RInd is 0.51Ω.
Fig. 6 shows the simulated RTSV dependence of VOUT andVWL of the boost converter. VOUT and VWL are exactly sameline. The dashed line denotes the target voltage of 20V. BothVOUT and VWL decrease, as RTSV increases. In order toachieve VOUT and VWL above 20V, RTSV less than 210Ω isrequired. However, it can be said that the impact of RTSV on
VOUT and VWL is small compared with Figs. 8 and 10.
Fig. 7 shows the simulated waveforms of VOUT, VWL, Iin,and clock of the boost converter. Fig. 8 shows the simulated
RTSV dependence of trise of the boost converter. trise is definedas the time to boost VOUT and VWL from 0V to 15V as shownin Fig. 7. The right axis of Fig. 8 is trise of VOUT compared tothe conventional charge pump [1]. Simulation of the charge
pump is conducted under same output load condition of CLand RL and trise of the charge pump is 3.45μs [1]. The graphof VOUT in Fig. 8 is not smooth, because VOUT of 15V areachieved by several pulses as shown in Fig. 7. If trise of VWLis determined by RWLtotal x CWLtotal time constant, trise of VWL
does not depend on RTSV, because RWLtotal x CWLtotal is 1μs
while maximum RTSV x CL is 40ns. In reality, however, trise ofVWL is largely affected by RTSV. This means that trise is notdetermined by the RC time constant. In order to investigate

RL=1MΩ

CWL1 CWL2 CWL2 CWL1Distributed RC lineof word line

R3Emulation for a NAND chip(including word line connection)
Fig. 5. Equivalent circuit of simulated boost converter.

2.024

Rising time (trise) [μs]23VOUT and VWL

22212019181716
15050100

1502001.540301.010050Outputvoltage [V]VOUT15VWL

105

trise of VWL

02000250200
18016014012010080
60
40
200050100150200

250

150

Resistance of TSV's (RTSV) [Ω]100Fig. 9. Simulated dependence of peak current of IRTSV on resistance ofTSV’s.

80

0570

00.0

0.5

1.0

1.5

2.0Time [μs]Fig. 7. Simulated waveforms of boost converter

the reason, Fig. 9 shows simulated dependence of peakcurrent of IRTSV during the first switching on RTSV. Thisshows that the peak current of IRTSV decreases when RTSVincreases. As a result, trise increases in Fig. 8. In this way, trise
is not determined by RWLtotal x CWLtotal time constant but byIRTSV.
Fig. 10 shows the simulated RTSV dependence of Eloss ofVOUT. Eloss is calculated from equation (1) using VDD, theinput current (Iin), and trise. The right axis of Fig. 10 is Elosscompared to the conventional charge pump [1]. Eloss of thecharge pump is 253nJ [1].

Eloss = ∫t rise
0VDD ⋅ I in dt(1)Eloss is proportional to trise, because Iin is almost notaffected by RTSV.

302560205040VOUT

301020510015050

100

150

200

Energy comparedto charge pump [%]50
Energy during
boosting (Eloss) [nJ]

Iin [mA]

200

Clock [V]150

Fig. 8. Simulated dependence of rising time on resistance of TSV’s.

Peak current of IRTSV [mA]

Fig. 6. Simulated dependence of output voltage of boost converter onresistance of TSV’s.

20 trise of VOUT

100

Resistance of TSV's (RTSV) [Ω]Resistance of TSV's (RTSV) [Ω]2520

VOUT0.50.0250

50

VWL

Rising time comparedto charge pump [%]Output voltage (VOUT, VWL)[V]

250250Resistance of TSV's (RTSV) [Ω]Fig. 10. Simulated dependence of energy consumption during boosting on
resistance of TSV’s

When RTSV is 200Ω, for example, trise of VOUT is 30.1%
and Eloss of VOUT is 22.8% of the conventional charge pump.
Besides, VOUT cannot be boosted above 20V when RTSV islarger than 210Ω as shown in Fig. 6. Therefore, in order tomaintain the large advantages of the boost converter over thecharge pump in terms of trise and Eloss, reduction of RTSV isvery important.
Cu TSV’s would be are more suitable than poly-silicon
TSV’s for the proposed application, because NAND flash
chips are made with expensive processes and Cu TSV’s have

an advantage over poly-silicon TSV’s in area due to thelower resistivity.

3. Conclusions
The effect of RTSV on the boost converter was investigated.
When RTSV is 0Ω, trise and Eloss of VOUT are 10.6% and 6.6%of the conventional charge pump respectively. In contrast,
when RTSV is 200Ω, for example, trise of VOUT is 30.1% andEloss of VOUT is 22.8% of the conventional charge pump.
Besides, VOUT cannot be boosted above 20V when RTSV islarger than 210Ω. Therefore, in order to maintain the largeadvantages of the boost converter over the charge pump interms of trise and Eloss, reduction of RTSV is very important.
Acknowledgments
The authors appreciate S. Ohshima, T. Hara, Y. Watanabe,T. Futatsuyama and G. Iwasaki and Toshiba NAND team fortheir support.
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