Photon Factory Activity Report 2005 #23Part B (2006)
Surface and Interface

4C,6A,15C/2004G059

Residual Order in the Interfacial SiO2 Layer
between a High-k Material and a Si Substrate
Takayoshi SHIMURA*, Eiji MISHIMA, Kohta KAWAMURA, Heiji WATANABE, andKiyoshi YASUTAKE
Graduate School of Engineering, Osaka University,
2-1 Yamadaoka, Suit, Osaka 565-0871, Japan

Experimental
A stacked structure of HfSiOx/HfO2 layers was formedby an atomic-layer deposition (ALD) technique, after a0.5-nm thick SiO2 layer was formed on Si wafers(HfSiOx/HfO2 sample) [2]. The thicknesses of the
HfSiOx and HfO2 layers were nominally 1.0 and 1.5 nm,respectively. The high-k gate dielectrics were nitrided
using nitrogen radicals, and annealed in a N2-diluted
oxygen atmosphere (O2 concentration of 0.004%) at ahigh temperature of 1000°C (HfSiON/HfON sample).
Some of the samples were annealed in a 100% nitrogen
atmosphere at 800°C for 3.5 min (annealed
HfSiON/HfON sample).
X-ray diffraction experiments using synchrotron
radiation were performed on BL4C of the Photon Factory

56

Users' Report

102
Intensity [arb.units]

Introduction
Exceptionally low density of trap charge at theinterface between a thermal oxide layer and a Si substrateis one of the principal reasons for the enormous
development of semiconductor industries based on silicon
metal-oxide-semiconductor (MOS) devices. It is
incredible that the trap density at the interface is no more
11-1-1than 10 cm ×eV despite a large structural difference
between an amorphous oxide layer and a crystalline
silicon substrate. It is roughly estimated that only one
4
defect, such as a dangling bond, exists in 10 atomic
bonds at the interface.
High-k gate dielectric materials are forthcoming
instead of SiO2 in MOS devices in order to reduce thegate leakage current. However, a very thin interfacial SiO2
layer is still indispensable to reduce the interface trap
density between the high-k material and the Si substrate.
Therefore, it is still important to understand the SiO2/Sisystem.
One of the major research subjects for high-k gate
dielectric technology is the control of this interfacial layer,
because thermal annealing is accompanied by an increasein the electrical thickness of the gate insulator due togrowth of an interfacial oxide, even when annealed in aultrahigh-vacuum(UHV)
ambientenvironment.
Therefore, it is important to investigate the oxidation
mechanism between the high-k material and the Si
substrate.
In this report we present preliminary results for theobservation of ordered oxide in the interfacial SiO2 layer[1].

HfSiON/HfON annealed
HfSiON/HfON
HfSiOx/HfO2

101
10
10-1
10-2
10-3
0.2

0.4

0.6

0.8

1.0

1.2

1.4

11L [a*]Fig. 1 Intensity distributions along the CTR scattering
around the 111 Bragg point for the HfSiOx/HfO2,HfSiON/HfON, and annealed HfSiON/HfON samples.
(KEK) by employing a four-circle diffractometer with anSi(111) crystal analyzer.
Results
In Fig. 1, the intensity distributions along the CTR
scattering around the 111 Bragg point are shown for thethree samples. Sharp diffraction peaks are not observedon the CTR scattering, because the thickness of theinterfacial SiO2 layers is very small. However, theintensity of the low angle side of the CTR scatteringclearly increases after the nitriding and post-nitriding
annealing, although the intensity of the high angle side of
the CTR scattering does not change. This indicates thatthe oxide layers with the ordered structure are reallyformed at the interface between the high-k layer and theSi substrate. The intensity of the ordered oxide slightly
increased for the annealed HfSiON/HfON sample
compared to that for the HfSiON/HfON sample. This also
indicates additional oxidation at the interface.
References[1] T. Shimura et al., The Physics and Chemistry of SiO2
and the Si-SiO2 Interface 5, edited by H. Z. Massoud, J. H.
Stathis, T. Hattori, D. Misra, and I. Baumvol (TheElectrochemical Society, Pennington, NJ) p. 39 (2005).
[2] S. Kamiyama, et al., Ext. Abst. of the 2004 Int. Conf.
on Sol. Stat. Dev. and Mat., Tokyo, 2004, 754-755.
*shimura@prec.eng.osaka-u.ac.jp