1D-12315MHz OOK Transceiver with 38-μW Receiver and 36-μW Transmitter in 40-nmCMOS
Shunta Iguchi1, Akira Saito2, Kentaro Honda1, Yunfei Zheng1, Kazunori Watanabe2,Takayasu Sakurai1, and Makoto Takamiya1
12

University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan
Semiconductor Technology Academic Research Center, 3-17-2 Shin Yokohama, Kohoku-ku, Yokohama 222-0033, Japan

Abstract – A 1-Mbps, 315MHz OOK transceiver in 40-nm CMOS
for body area networks is developed. Both a 38-pJ/bit carrierfrequency-free intermittent sampling receiver with -55dBmsensitivity and a 36-pJ/bit transmitter applied dual supply
voltage scheme with -20dBm output power achieve the lowest
energy in the published transceivers for wireless sensor networks.

outputs of the amplifiers (V2A) are compared by proposed
variable offset comparators clocked by φCMP, and the data is
1 symbol

1 symbol

I Introduction(a) Conventional continuous sampling

A low power 315MHz band (ARIB STD-T93) OOK
transceiver for short-range wireless sensor networks isdeveloped in this paper. The target receiver (RX) sensitivity
and transmitter (TX) output power is -55dBm and -20dBm,respectively, assuming -25dB propagation loss at the 1-m
communication distance and -5dB x 2 loss at TX/RXantennas. The target power consumption is 50μW at 1Mbps.
In order to reduce the power, (1) sampling circuits are usedinstead of continuous analog circuits, (2) the RX input isdirectly sampled without LNA, because high sensitivity is not
required for the 1-m communication, (3) a carrier-frequencyfree (CFF) intermittent sampling (IS) is newly proposed toreduce the number of sampling, (4) a dual supply voltage(VDD) scheme is newly proposed to increase the efficiency of alow output power (POUT) TX. The newly proposed IS [1] anddual VDD scheme [2] reduce the power of the transceiver to
1/315 and 2/3, respectively.

1 symbol

1 symbol(b) Proposed intermittent sampling

Fig. 1. Proposed intermittent sampling concept.
5-stage
amplifiersIntermittentsamplers
φ0 φ180 φHPF
Sampler1
VINSAW

Balun

φCMP
V1

φ90 φ270+-+

Sampler2

V1Out

φ0 φ180
Sampler3

V2

φ90 φ270
Sampler4

A conventional continuous sampling and the proposed IS
concept for RX are compared in Fig. 1. The proposed IS
reduces the number of the sampling in 1 symbol in order toreduce the power consumption of the sampler. Fig. 2 shows a
block diagram of the proposed all 0.5V CFF IS RX. Only 1MHz clock instead of a 315-MHz carrier frequency is supplied
to RX. RX input (VIN) is directly sampled by intermittent
samplers without LNA. VIN is sampled by quadrature 315MHz clocks (φ0, φ90, φ180, and φ270). The timing difference ofΔT is generated by digitally controlled delay lines instead of aconventional quadrature 315-MHz PLL, thereby reducing thepower consumption. In the 315-MHz, 1-Mbps CFF IS RX, thenumber of sampling of VIN per bit is 4, while that of theconventional continuous sampling is 4x315, thereby reducing
the power consumption of the sampler to 1/315. By the clockof φHPF, the sampled VIN’s are subtracted for a high pass filter
function in order to increase the RX sensitivity by 3dB. The
outputs of the samplers ( V1 , V1 , V2 , and V2 ) are amplified by5-stage IF amplifiers with an offset cancellation. Then, theClk(1MHz)V2A+-+VIN

II Carrier-Frequency-Free Intermittent Sampling
Receiver

978-1-4673-3030-5/13/$31.00 ©2013 IEEE

Variable offset
comparators

V2

Digitally controlled delay lines
φ0 φ90 φ180 φ270 φHPF φCMP

Fig. 2. Block diagram of proposed all 0.5V carrier-frequencyfree intermittent sampling RX.
demodulated. V2A is not constant, because the DC component
is eliminated in the offset cancel amplifier.

III Transmitter with Dual VDD Class-F Power Amplifier
A dual VDD scheme is proposed to maximize global
efficiency (GE) of TX at POUT of -20dBm in this section. Fig.
3 shows a schematic of TX including the dual VDD class-F PA.
As shown in Fig. 3, PTOTAL is the sum of the buffer, the mixer,
and the PA powers. In the TX design with POUT of -20dBm,
the buffer power is not negligible and the drain efficiency(DE) of PA is quite low because the impedance transformation
ratio (n) and the loss are much higher than conventional PA’s
designs (POUT: 10~30dBm). Therefore, GE should bemaximized at POUT of -20dBm by optimizing n. In the design93

1D-12
optimization, VDD1, VDD2, CDC, and LDC are varied according
to n, and L1, C1, L3, C3, and transistor size are fixed.
Fig. 4 shows the SPICE simulated n dependence in TX
with POUT of -20dBm. Fig. 5 shows the simulated dependenceof PTOTAL, the buffer power, and the PA power on n. As shownin Fig. 4, the conventional TX with single VDD is designed at n
= 9.6 and VDD1 = VDD2 = 0.47V. In contrast, PTOTAL isminimum at n = 4.2, thereby GE is maximum at n = 4.2. Thecorresponding VDD1 = 0.56V and VDD2 = 0.2V. The reason forthe optimum dual VDD is discussed. When n is reduced from10 to 2, VDD2 is reduced and the PA power is reduced. Incontrast, VDD1 is increased and the buffer power is increased.
When n is reduced below 3, VDD1 drastically increases because
the transistor operation changes from the saturation region tothe linear region, thereby the corresponding buffer power
drastically increases. Therefore, PTOTAL is minimum at n = 4.2,thereby GE is maximum at n = 4.2 [2].
On-chip
VDD1

Table I Performance summary and comparison

OutCDC
L1C3[4]CMOS technology
nmRXV
SupplyvoltageTXV
Carrier frequency MHz
Data rate
Mbps
Modulation
RX sensitivitydBm
TX output powerdBm
RXμW
PowerTXμW
RX
pJ/bitEnergyTX
pJ/bit90
1, 1.2
1, 1.2
2400
5OOK
-75
0534
253
134
2530

130
1
4000.2
FSK-1790450

This
work
40
0.50.52, 0.2
315
1
OOK
-55
-20
3836
3836IV. Measurement Results

L3Carrier(315MHz)[3]

The proposed transceiver is fabricated in 40-nm CMOS
process. Fig. 5 shows a die photo and layout of RX and TX.
Table I shows a measured performance summary andcomparison of performance with published transceivers for
wireless sensor networks [3-4]. Thanks to the proposed IS, thepower consumption of the samplers in RX is 3μW and thetotal RX consumes 38 μW. Without IS, the continuous
sampler will consume 945μW (=3μW x 315). The TX
efficiency (GE) increases from 16% to 28% due to the dual
VDD scheme. Both the 38-pJ/bit CFF IS RX and the 36-pJ/bit
dual VDD TX achieve the lowest energy to date.

Off-chip
VDD2
LDC

Unit

C1Data(1Mbps)
Power amplifier (PA)V. Conclusion

Fig. 3. Schematic of dual VDD TX with class-F PA.

A low power OOK transceiver for short-range wirelesssensor networks is developed in this paper. In order to reduce
the power, CFF IS and dual VDD scheme are newly proposed.
The newly proposed IS and dual VDD scheme reduce thepower of the RX and TX to 1/315 and 2/3, respectively. Boththe 38-pJ/bit CFF IS RX and the 36-pJ/bit dual VDD TX
achieved the lowest energy to date.

Power consumption [μW]

Global80
Conventional single VDD

60Optimum dual VDD
Global40PA

Acknowledgments

BufferThis work was carried out as a part of the Extremely Low
Power (ELP) project supported by METI and NEDO.

2001POUT = -20dBm
234 5 6 7 8 9 10References

Impedance transformation ratio (n)[1] A. Saito, K. Honda, Y. Zheng, S. Iguchi, K. Watanabe, T.
Sakurai, and M. Takamiya, “An All 0.5V, 1Mbps, 315MHzOOK Transceiver with 38-μW Carrier-Frequency-FreeIntermittent Sampling Receiver and 52-μW Class-F Transmitterin 40-nm CMOS,” IEEE Symposium on VLSI Circuits, pp. 3839, June 2012.
[2] S. Iguchi, A. Saito, K. Honda, Y. Zheng, K. Watanabe, T.
Sakurai, and M. Takamiya, “2.1 Times Increase of Drain
Efficiency by Dual Supply Voltage Scheme in 315MHz Class-F
Power Amplifier at Output Power of -20dBm,” European SolidState Circuits Conference, pp. 345-348, Sept. 2012.
[3] M. Vidojkovic et al., “A 2.4GHz ULP OOK Single-Chip
Transceiver for Healthcare Applications,” IEEE International
Solid-State Circuits Conference, pp. 458-459, Feb. 2011.
[4] J. Pandey and B. P. Otis, “A Sub-100μW MICS/ISM Band
Transmitter Based on Injection-Locking and Frequency
Multiplication,” IEEE Journal of Solid-State Circuits, Vol. 47,
No. 5, pp. 1252-1260, May 2012.

Fig. 4. SPICE simulated impedance transformation ratio
dependence in TX with POUT of -20dBm.
1.1 mm22 μm

329 μm

0.5 mm

1.1 mm

0.6 mm56 μm473 μm(a)(b)Fig. 5. Die microphotograph and layout of (a) RX and (b) TX.

94