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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 10, OCTOBER 2000

Separation of Effects of Statistical Impurity Number
Fluctuations and Position Distribution on V th
Fluctuations in Scaled MOSFETs
Yuri Yasuda, Makoto Takamiya, Member, IEEE, and Toshiro Hiramoto, Member, IEEE

Abstract—We have investigated the effect of the statistical “posi) fluction” distribution of dopant atoms on threshold voltage (tuations in scaled MOSFETs. The effects of impurity “number”
fluctuations and impurity “position” distribution are successfully
separated in two-dimensional simulation for fully-depleted (FD)SOI MOSFETs. It is found that the contribution by the position
distribution is closely related to the charge sharing factor (CSF)
and the effect of the impurity position distribution becomes dominant as CSF is degraded. Consequently, the contribution ratio of
the impurity position distribution is kept almost constant when thedevice is properly scaled.
Index Terms—Charge sharing factor, depletion region, FD SOIMOSFET, impurity, number fluctuation, position distribution,scaling, threshold voltage.

I. INTRODUCTION

THE THRESHOLD voltage ( ) fluctuations due to thestatistical impurity fluctuations in the channel is one of themost serious problems in scaled MOSFET [1], because thefluctuations increase as the device is scaled down. The statisfluctuations have been widely studied by experimentstical[2]–[4] and simulations [5]–[12]. In these studies, the effects ofimpurity “number” fluctuations are generally discussed. It has
fluctuations are caused notbeen also pointed out that the
only by the impurity “number” fluctuations but also by the impurity “position” distribution [2], [3], [6]–[8], [10]. In an extremely scaled MOSFET where the number of impurities is reduced, the slight change of the impurity “position” would causea large change in the device characteristics [7]. Therefore, it isvery important to quantitatively evaluate the effect of impurity
fluctuations“position” distribution and clarify the origin of
flucdue to the “position” distribution. The variation of thetuations with device scaling is also of great interest.
fluctuations which include both theSome models of the“position” distribution and the “number” fluctuations have been
already studied [13]–[15]. However, these works have discussed
fluctuations and the effects of impurity number
only “total”
Manuscript received April 3, 2000. The review of this paper was arranged by
Editor D. Ferry.
Y. Yasuda was with the Institute of Industrial Science, University of Tokyo,
Tokyo 106-8558, Japan, and the Faculty of Science and Engineering, Chuo University, Tokyo, Japan. She is now with NEC Corporation, Sagamihara, Kanagawa 229-1198, Japan(e-mail: yasuda@nano.iis.u-tokyo.ac.jp).
M. Takamiya was with the Institute of Industrial Science, University ofTokyo, Tokyo, Japan 106-8558. He is now with NEC Corporation, Sagamihara,
Kanagawa 229-1198, Japan.
T. Hiramoto is with the Institute of Industrial Science and VLSI Design and
Education Center, University of Tokyo, Tokyo 106-8558, Japan.
Publisher Item Identifier S 0018-9383(00)07777-7.

Fig. 1. Device structure of fully depleted SOI MOSFET assumed in this study.
V is 0.1 V to decrease the short channel effect except for the V dependence,and the buried oxide thickness (t) is 1 m to decrease the effect of impurity
in the substrate.

and position have not been separated. Although some simulation
fluctuations andworks deal with the relation between thethe impurity position in the depth direction [10], [12], the lateral
impurity position distribution are not considered.
In this work, we have separated the impurity “number” fluctuations and impurity “position” distribution, and investigatedfluctuations by means of two-dimentheir effects on thesional (2-D) [16] and three-dimensional (3-D) device simulations [17]. It is found, for the first time, that the effect of thefluctuations depends on
impurity position distribution on
fluctuations due tothe charge sharing factor (CSF) and thethe impurity “position” distribution originate from the impurity
number fluctuations in gate-controlled depletion region.
II. SIMULATION MEHTOD
In this section, the simulation method and conditions are described. In order to investigate the effects of channel impurity
number fluctuations and impurity position distribution, the two
effects should be separated. In conventional bulk MOSFETs, it
is very hard to separate these two effects, because the depletion layer width ( ) is varied by changing the channel impurity
position distribution, and the impurity number in the depletion
layer can not be kept constant. In FD SOI MOSFET’s, on theother hand, corresponds to the SOI thickness and the impurity number can be kept constant. Therefore, the effects of imfluctuations canpurity number and position fluctuations on
be separated and we can independently set the impurity number
and position fluctuations in the simulation [18]. Fig. 1 shows the
structure of an FD SOI MOSFET.
In order to introduce the statistical impurity fluctuations into
the simulation, the channel of a MOSFET is divided into small
andin the direction of the length ( ), depth
cells [ ,0018–9383/00$10.00 © 2000 IEEEYASUDA et al.:

TH FLUCTUATIONS IN SCALED MOSFETS1839

TABLE IDEVICE PARAMETERS OF FULLY DEPLETED
SOI MOSFET USED IN THE SIMULATION

Fig. 2. Dependence of R
length (L ). Device B is used.

and width ( ), respectively] and impurities are distributed tothese cells at random, so that the possibility that each impurity
atoms is distributed is the same for all the divided cells. Two cases
are simulated for FD SOI MOSFET. In the first case, both impurity number fluctuations and impurity position distribution are
fluctuations
considered. This case corresponds to the total). In the second case, only the impurity position distri(bution are considered and the impurity number is kept constant.
fluctuations due to the position
This case corresponds to the). In the first case, we choose the imdistribution (purity number that follow Poisson distribution with an averageand the impurities are distributed
channel concentration of
into cells at random [6]. In the second case, the channel impurity number is kept constant and only the impurity positions arechosen at random. A impurity number in each cell ( ) is con]. In the caseverted into a concentration [is equal to[9]. In order to investigate
of 2-D simulation,
dependence in 2-D simulation,
is varied. Table I shows
the device parameters assumed in this study. The standard deviof each structure is derived from 800 or 200
ation ofsamples in 2-D simulation and 100 samples in 3-D simulation.
The drain voltage ( ) is 0.1 V to decrease the short channel efdependence.
fect (SCE), except for the simulation of theis derived from a current criteria of.
III. SIMULATION RESULTS
In this section, the contribution by the impurity position distribution are described.
First, the contribution ratio of the effect of impurity position
fluctuations should be defined. The
distribution to the total
fluctuations due to the statistical channel impurity fluctotal
tuations are given by(1)is standard deviation ofin which only thewhere
impurity number fluctuations are included and the impurities are
uniformly distributed over each cell resulting in no position distribution. This is because the impurity number and position fluc-(= (V=V) ) on gate

Fig. 3. Dependence of R(= (V=V
channel concentration (N ). Device B, C, D, and E are used.

) ) onFig. 4. Dependence of R
drain voltage (V ).

) ) on

(=

(V

=V

tuations are independent events. The contribution ratio
by position distributions to the total fluctuations is defined as(2)
The validity of the 2-D simulation has been confirmed bycomparing the 2-D simulation results with the experimental data
and the 3-D simulation data [18]. We also examined the effects
doesof the way of dividing into small cells. We find thatnot depend on how to divide the channel into cells in simulation.
,
Therefore, cell sizes are defined asand, and are equal to spacing. These results are inagreement with the results by Stolk et al. [9].The dependence ofon device parameters of FD SOI MOSFETs is investigated by the 2-D simulation. The device parameters investigated), gateare gate length ( ), gate width ( ), SOI thickness (), channel concentration ( ), and drainoxide thickness (voltage ( ).
does not deFigs. 2–4 show the simulation results.
,
and(not shown in the figure). In 2-D
pend uponsimulation, the effect of impurity position distribution along the1840

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 10, OCTOBER 2000

Fig. 6.

Fig. 5. Distribution of V in two kinds of devices with the same impurity
number. The device parameters used are those of Device B in Table I. (a)Impurities are distributed at random in the whole channel. The standard. (b) Impurities are distributed in region
deviation corresponds to Vcontrolled by gate and impurities are uniformly doped near source and drain.
The difference in the average V is obtained which is in agreement with [11].

channel width is not taken into account. In order to investigate
dependence in more detail, we have also perform the
the
and
are
3-D simulation. The obtained
dependence
almost the same as those in 2-D simulation, andhas not been found in 3-D simulation. The currentofpercolation due to the 3-D effect will have more influence on
fluctuations in scaled devices and should be investigated further.
has dependence on ,It is found from Figs. 2–4 that
and.
increases as anddecrease. It is also
depends onin a fixed device as shown
found that
increases asincrease.
in Fig. 4. The absolute value ofis small, more dependence on
is found.
Moreover, whenThis is in good agreement with the experiment [3]. It should be
noted that these dependences on device parameters are quite simis larger when the device
ilar to those of charge sharing.
has more short channel effects due to charge sharing. It appears
from these results that the effect of impurity position distribution
is determined by the charge sharing. As the impurity position distributes, the impurity number in the source and drain-controlled
fluctuates.
depletion region fluctuates and therefore,
IV. IMPURITY POSITION DISTRIBUTION AND CHARGE SHARING
In order to investigate the relationship between the charge
sharing and statistical position distribution, two kinds of devices
are simulated as shown in Fig. 5. Here, the charge sharing factor(CSF) is defined as
CSF
Impurity number in gate controlled depletion region
Total impurity number
Area of gate controlled depletion region
The whole channel area

(3)

Schematic of depletion region controlled by source and drain.

In both devices, channel impurity number is set constant. In
the first device, all the impurities in channel are distributedat random and therefore, CSF of individual devices would be
fluctuated by the statistical impurity position fluctuations. In
the second device, on the other hand, the regions near sourceand drain are uniformly doped and impurities are distributed at
random at the rest of the channel. In this device, CSF would
not be fluctuated because there is no position distribution
distributes
near source and drain region. Fig. 5 shows the
distribution islargely in the first device, while only a slightobtained in the second device. This result clearly indicates thatfluctuations due to the impurity position distribution
theoriginate from the CSF fluctuations in the channel depletion
region near source and drain of the individual devices.
A simple charge sharing model for FD SOI MOSFET is considered in order to evaluate the quantitative relationship between
and CSF in MOSFETs with various device parameters. The charge sharing regions controlled by source and drain
are given approximately by rectangles as shown Fig. 6 (Thisapproximation in FD SOI MOSFET is confirmed by simulation
not shown here). Hence, CSF is given by
CSF

(4)

is depletion layer width by source and drain. The
where
and
should be considered because
averages of CSF,
800 samples are simulated in a fixed device parameter to oband, respectively. In this equation,tain
is fixed at 0.1
the effect of drain voltage is ignored, because
dependence.
V in this study except for the simulation of
and
. All
Fig. 7 shows the relation between
the simulated devices in Table I are plotted. It should be notedthat most of devices are plotted on one line. On the other hand,when the simulated data are plotted as a function of gate length
or average channel impurity number (not shown in the figure),
the plots largely distribute. Therefore, Fig. 7 strongly indicatesis primarily determined by the charge sharing. It
thatis also clearly found from Fig. 7 that the effect of position disdetribution becomes dominant as CSF is degraded (creases) and the device has more short channel effects. This isbecause, when CSF is degraded, impurity number in drain-controlled depletion region is larger and consequently is fluctuatedmore largely.

YASUDA et al.:

TH FLUCTUATIONS IN SCALED MOSFETS

1841

Fig. 9. Variation of R
device scaling.
Fig. 7. Relation between R(= (V=V) ) and
L N . All simulated devices in Table I are plotted. In Device B–I, gate length
is varied. In type A–C of Table II, all parameters are scaled.

TABLE IISCALING METHODS OF FD SOI MOSFET FOR THE SIMULATION.

(=

(V

=V

) ) with

as long as the device is properly scaled, although the increase
would be a serious problem
in the absolute value of total
in the future. These results in FD SOI MOSFETs would be also
applicable to the bulk MOSFETs.
VI. CONCLUSIONSThe effects of the statistical channel impurity position distrifluctuations are investigated. The effects of impubution onrity number fluctuations and impurity position distribution are
successfully separated in 2-D simulation for FD SOI MOSFETs.
It is found that the contribution ratio of impurity position distribution to the total fluctuations is determined by charge sharing
in the depletion region and the effect of position distribution becomes dominant as the charge sharing factor is degraded. It isalso suggested that the contribution ratio of the position distribution is almost kept constant when the device is properly scaled
down.
REFERENCES

Fig. 8. Variation of the absolute value of Vwith scaling in FD
SOI MOSFETs. The standard device parameters used are Device A at
L = 0:25 m in Table I. This device is scaled by the scaling methods
summarized in Table II.

V. VARIATION OF

WITH SCALING

Finally, the variation ofwith device scaling is examined. Table II shows three different scaling methods in FD
SOI MOSFETs. Fig. 8 shows the absolute value ofand.
includes both the impurity number
includes only the impuand position fluctuations.
increase as the device isrity position distribution. Bothscaled down.
when the device size is scaled. AlFig. 9 showsincreases,
is almostthough the absolute value of
constant as the device is scaled down. This is because the charge
sharing factor is almost constant when the device is properly
scaled . Therefore, it is concluded that the effect of impurity pofluctuations
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[12] D. Vasileska, W. J. Gross, and D. K. Ferry, “Modeling of deep-submicrometer MOSFETs: random impurity effects, threshold voltage shifts
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Yuri Yasuda was born in Saitama, Japan, in 1975.
She received the B.S. and M.S. degrees in electricaland electronic engineering from Chuo University in
1998, and 2000, respectively.
She has been engaged in research on device
simulation of MOSFETs, especially the fluctuations
caused by statistical impurity fluctuations, at theInstitute of Industrial Science, University of Tokyo.
In 2000, she joined NEC Corporation, Sagamihara,
Japan.

Makoto Takamiya (S’98–M’00) was born in Hyogo,
Japan, in 1973. He received the B.S., M.S., and Ph.D.
degrees in electronic engineering from the Universityof Tokyo, Japan, in 1995, 1997, and 2000, respectively.
He has been engaged in research on low power SOICMOS devices. His research interests include scalingof MOSFETs into sub-0.1 m region and ultralowvoltage MOSFETs.
Dr. Takamiya received the Young ResearcherAward of 1999 International Conference on Solid
State Devices and Materials. In 2000, he joined NEC Corporation, Sagamihara,
Japan.

Toshiro Hiramoto (M’93) received the B.S., M.S.,
and Ph.D. degrees in electronics from the Universityof Tokyo, Japan, in 1984, 1986, and 1989, respectively.
In 1989, he joined the Device Development
Center, Hitachi Ltd., Ome, Japan, where he wasengaged in device and circuit design of ultrafast
BiCMOS SRAM. Since 1994, he has been as
Associate Professor with the Institute of Industrial
Science, University of Tokyo. He has also beenan Associate Professor with the VLSI Design and
Education Center, University of Tokyo, since 1996. His research interests
include low power device design, sub-100 nm CMOS devices, SOI MOSFETs,
silicon single electron devices, and quantum effects in scaled MOSFETs.