AMD2 - 2
InvitedFlexible Braille Sheet Display
with Organic FETs and Plastic Actuators
M. Takamiya, T. Sekitani*, Y. Kato*, H. Kawaguchi**,T. Someya*, and T. Sakurai***
VLSI Design and Education Center, University of Tokyo, Japan*Quantum-Phase Electronics Center, School of Engineering, University of Tokyo, Japan**Department of Computer and Systems Engineering, Kobe University, Japan***Center for Collaborative Research, University of Tokyo, Japan
E-mail: mtaka@iis.u-tokyo.ac.jp
ABSTRACT
Organic FETs (OFETs) are integrated with actuators, and a Braille sheet display is demonstrated. A newly developed back-gated OFETs
SRAM and the circuits technology for the Braillesheet display to enhance speed, yield and lifetime
are presented, which will be essential for future
large-area electronics made with OFETs.
INTRODUCTION
As shown in Table I, flexible and low-costorganic FETs (OFETs) are suitable for large-area
applications where functional units are distributedon plastic films, 10 cm – 10 m on a side. An integrated system of OFETs and pressure sensors
was reported in [1], and that of OFETs andphotodetector was reported in [2]. In this paper,an integrated system of OFETs and plastic actuators is proposed, and a Braille sheet display isdemonstrated [3]. Device and process technology of the OFETs and the actuators are shown in[4].
The transition time of the actuator is about 1s. The Braille sheet display has an actuator array.
When the actuator is sequentially driven, it takes
more than 1 minute to change the Braille, which isimpractical. The OFETs also have several problems. OFETs are chemically degraded by theoxygen and moisture in the atmosphere. Thresh-old voltage (VTH) control process technology suchas an ion implantation is not yet established for

Unit of Braille(6 dots)

Fig. 1

Braille sheet display.

FrameActuator
GOFETsdriverDSOFETsSRAMGDS

Pentacene Back gate

Table I Comparison between our organic FETs (OFETs) andthe state-of-the-art silicon MOSFETs.

Design ruleHardness
Drive current

OFETs

Si MOSFETs

50 Pm

90 nm

Flexible

Solid

25 nA / Pm @ 40 V 1 mA / Pm @ 1 V

Gate delay

0.3 ms

10 ps

Cost / area

Low

High

Cost / transistor

HighLow

LifetimeDaysYearsUp
Braille dot(hemisphere)
Actuator

4mmDown

Fig. 2 Device structures for the Braille sheet display.
films are stacked.

4IDW ’06

261

WLUp
Down

UpUpUp

Down

VDD
DATA

DATAb

OFETs
SRAM

100/50

OFETs. To increase the speed of the actuator,
OFET SRAM and overdrive techniques for a drivertransistor is proposed. To achieve a reliable andstable SRAM operation, a VTH control technology
using a back gate is developed. 5-transistor
SRAM cell is also developed to reduce the numberof bit lines and cell area.
BRAILLE SHEET DISPLAY
Figure 1 shows the developed Braille sheet
display. Braille characters in a 6 x 4 array are
shown on the 4 cm x 4 cm display. Each Braillecharacter consists of 2 x 3 dots, and the display
has a total of 144 dots. As shown in Fig. 2, fourfilms (frame, actuator, OFETs driver, and OFETs
SRAM) are stacked in the Braille sheet display.
The Braille character is changed by moving thedots up and down by means of the actuator, depending on the input data. Each Braille dot hasan OFET SRAM to compensate for the slow transition of the actuator. After the input data are written to all SRAMs, all the actuators are driven atonce using the drivers depending on the data. In
this way, the time required to change the whole
Braille is reduced. Figure 3 shows the display
operation showing the character “W”.
KEY CIRCUIT TECHNOLOGIES
A. 5-Transistor SRAM Cells and Pipelining for
Write-Operation
Figure 4 shows the circuit of the SRAM andthe driver for one actuator. Only pMOS OFETs
are used, because the performance of nMOS
OFETs is commonly worse than pMOS. The
OFETs for SRAM have back gates [5] to control
VTH. A write-only SRAM is enough for our Brailleapplication, because the actuator moves depending on the hold data (DATA, DATAb) and a SRAM
read-operation is not required. Therefore, to savethe film area, a 5-transistor SRAM cell is developed. Compared with a conventional 6-transistor
SRAM cell, a 5-transistor SRAM cell reduces thenumber of the bit lines by one-half and reduces theSRAM cell area by 20%. Figure 5 shows a micrograph of the 5-transistor SRAM cell. The cell

IDW ’06

49000/20

VPH

Braille dot

VPL

VBGATEpMOS withback gate

ActuatorFig. 4 Circuit of OFETs SRAM and the driver for one actuator.
Back Gate

50-Pm design rule

Drive Tr

Braille sheet display showing the character “W”.

VSS

VACT

OFETs
driverDrive Tr

0.9mm

262

4000/50UpBIAS

Fig. 3BL

Load Tr

Access Tr

Down

W/L = 4000Pm/50Pm

2.0 mmLoad Tr
3.7 mmFig. 5Micrograph of the 5-transistor SRAM cell.

area is 3.7 mm by 2.0 mm. The whole cell is covered with the back gate.
B. Control of SRAM Static Noise Margin with A
Back Gate
The VTH control technology using a back gateis shown to compensate for the immature VTH
control process technology and to achieve a reliable SRAM operation. Figure 6 shows ID – VGS
characteristics of a pMOS OFET. Back gate
voltage (VBGATE) is varied. Figure 7 shows themeasured butterfly curves of the SRAM with varied
VBGATE. The static noise margin (SNM) increases
as VBGATE increases.
The VTH control technology is also applied tocompensate for the chemical degradation ofOFETs and to achieve a reliable SRAM operation.
Figure 8 shows the measured aging characteristicsof the inverter in the SRAM. The OFETs werekept in a nitrogen atmosphere except for themeasuring time. As time passes, the inverter
characteristics show a rightward shift due to thereduced |VTH| of OFETs. Figure 9 shows the aging characteristics of SNM calculated based to Fig.
8. By compensating the reduced |VTH| of OFETs
due to the chemical degradation with the back gate,

VBGATE

20 V0VL = 50 Pm
W = 4000 Pm

60
40

40 V
60 V

2000–5 –10 –15 –20 –25 –30 –35 –40
VGS (V)

Fig. 6 ID – VGS characteristics of a pMOS OFET with varied
VBGATE.
40

VBGATE – VDD = 0V (Conv.)

40 V
DATAb

DATA–20V0V

DATAb, DATA (V)3530252015VBGATE – VDD = 40V(Proposed)

105005 10 15 20 25 30 35 40DATA, DATAb (V)Fig. 7 Measured butterfly curves of SRAM with varied
VBGATE.

C. Overdrive Techniques for Driver Transistors
Our design target for the transition time of theactuator is within 2 s. The actuator has a large
capacitance (100 PF). The breakdown voltage ofthe actuator is 3 V. Figure 10 shows the measured waveforms of the actuator voltage (VACT) andthe actuator displacement.
The step voltage
height (VX) of VPL is varied. The required displacement by Braille users is 0.2 mm. When VPL
is equal to the breakdown voltage of -3 V, the transition time is 34 s, which exceeds our design target.
In order to reduce the transition time, VPH and VPL
overdrive techniques are proposed. By increasing VX from -3 V to -10 V, the transition time is reduced from 34 s to 2.0 s, which satisfies our design target. In order to avoid the breakdown of
the actuator, the overdrive period is determined bythe time when VACT is within ±3V.
Finally, an operation of the Braille sheet display is demonstrated.
Figure 11 shows themeasured waveforms of the driver and the actuator

40–20V40 V

after 0 day
7 days10 days
15 days

100V
001020In (V)

(a)
3040

Static noise margin (SNM) (V)with compensation

765
432w/o compensation

100

DriverActuator

Fig. 8 Measured aging characteristics of the inverter in theSRAM.
8VPL

VACT Braille dot

205101520
Time after fabrication (day)Fig. 9 Aging characteristics of the static noise margin andcompensation for the aging.

VPL (V)

OutDisplacementof actuator (mm) VACT (V)40 V

Out (V)In

Chemicaldegradation

3040 VDATAb(-20V)

0VX㩷0-1

VX = –3V-2–5V–10V-3–20V
㩷
-4
–10V
0.8 –20V
17x speeding up –5V
0.6
0.4
0.2
VX = –3V
00 5 10 15 20 25 30 35 40Time (s)㩷80 VGSa constant SNM can be achieved. Because thechemical degradation is inherent in OFETs, theproposed compensation technology is essential to
OFET applications.

VBGATE = –60V–40V–20V0V–40V100

㩷Drain current (PA)

120(b)
Fig. 10 (a) Measured driver and actuator circuits.
celerated actuator by overdrive techniques.

(b) Ac-due to the chemical degradation with the back gate,

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Sequential drive of actuators

SRAM
DATAb

DATA

VACT

VPH

InitialdesignSRAM
is added

Final
design1.47 sFig. 12VPH

VACT㩷

50-5-100.4
0.2

VPL

㩷

Braille dot isUp0-0.2-0.4

01.6 s0.74 s51015Time (s)Down
2025(b)Fig. 11 (a) Measured Braille sheet display circuits.
Braille sheet display operation.

(b)

for a Braille dot. Movement of the Braille dot,
both up and down, has been successfully demonstrated. By using overdrive techniques in VPH andVPL, a 1.6-s actuator transition time is achieved.
PERFORMANCE SUMMARY
Figure 12 summarizes the time to change
144 Braille dots and the speeding up by the developed circuit technologies. At an initial design
without the SRAM, it takes 4896 s, because the144 actuators are sequentially driven. When theSRAM is added, it takes 40 s, because all actuators are a simultaneously driven after the data arewritten to SRAM. At a final design, the developed
pipelining for SRAM write-operation and overdrive
technology for the driver increased the speed ofthe Braille sheet display 1580 times, and achieved
the practical 3.1-s operation.
CONCLUSIONSOFETs were integrated with actuators, and a
Braille sheet display was demonstrated.
AnSRAM made with OFETs is demonstrated for thefirst time. Pipelining the write-operation reduced
the SRAM write-time by 74%. Threshold voltage
control technology using a back gate increased theSNM and compensated for the chemical degradation of the OFETs after 15 days. The overdrive

264

IDW ’06

1/122

1/13
1/15801.6 s

Summary of speeding up Braille sheet display.

㩷10㩷

Displacementof actuator (mm) Voltage (V)

DATA
DATAb

40 s

34 s
5.76 s
PipeliningOverdrive
3.1 s

VPL(a)

4896 s

34 s x 144
Write-time of SRAM
Simultaneous drive

techniques for the driver OFETs reduced the transition time of the actuator from 34 s to 2 s.
These developed circuit technologies will beessential for the future large area electronics madewith OFETs.
ACKNOWLEDGEMENT
The authors acknowledge Prof. M. Doi, University of Tokyo, and Dr. K. Asaka, AIST, for the
sheet-type soft actuator made of perfluorinatedpolymer electrolyte. This work is partially supported by JST, IT program, MEXT, and NEDO.
REFERENCES[1] T. Someya, H. Kawaguchi, and T. Sakurai,"Cut-and-paste organic FET customized ICs forapplication to artificial skin," ISSCC Dig. ofTech. Papers, pp. 288-289, Feb. 2004.
[2] H. Kawaguchi, S. Iba, Y. Kato, T. Sekitani, T.
Someya, and T. Sakurai, "A sheet-type scannerbased on a 3D stacked organic-transistor circuit with double word-line and double bit-line
structure," ISSCC Dig. of Tech. Papers, pp.
580-581, Feb. 2005.
[3] M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T. Sakurai," An Organic
FET SRAM for Braille sheet display with backgate to increase static noise margin," ISSCC
Dig. of Tech. Papers, pp. 276-277, Feb. 2006.
[4] Y. Kato, S. Iba, T. Sekitani, Y. Noguchi, K. Hizu,
X. Wang, K. Takenoshita, Y. Takamatsu, S.
Nakano, K. Fukuda, K. Nakamura, T. Yamaue,M. Doi, K. Asaka, H. Kawaguchi, M. Takamiya,T. Sakurai, and T. Someya, "A flexible, lightweight Braille sheet display with plastic actuators driven by an organic field-effect transistor
active matrix," IEDM Tech. Dig., pp. 105-108,Dec. 2005.
[5] S. Iba, T. Sekitani, Y. Kato, T. Someya, H. Kawaguchi, M. Takamiya, T. Sakurai, and, S. Takagi, "Control of threshold voltage of organic
field-effect transistors with double gate structure," Applied Physics Letters, 87, 023509, July
2005.