496

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016

Variation-Tolerant Quick-Start-Up CMOS Crystal
Oscillator With Chirp Injection and Negative
Resistance Booster
Shunta Iguchi, Student Member, IEEE, Hiroshi Fuketa, Member, IEEE, Takayasu Sakurai, Fellow, IEEE,
and Makoto Takamiya, Senior Member, IEEE

Abstract—This paper presents a variation-tolerant quick-startup 39.25 MHz crystal oscillator and a theoretical analysis ofa proposed chirp injector (CI) and negative resistance booster(NRB) for the quick start up. A new analysis of the theoreticalminimum start-up time provides a new criterion for evaluating thestart-up time in crystal oscillators. The calculated theoretical minimum start-up time at 39.25 MHz is 11.1 µs. A new analysis of the
proposed CI and NRB clarifies the validity of the universal optimum control method. It explains the reason why the proposed CI
and NRB reduce the start-up time and its variation. The proposed
crystal oscillator with the proposed CI and NRB exhibits a startup time of 158 µs at 39.25 MHz. The variation of the start-up time
variations is ±13% over the supply voltage range of 1.2–1.8 V and±7% over the temperature range of −30 to 125 ◦ C. The power
consumption of the crystal oscillator in the steady state is 181 µW
with a phase noise of −147 dBc/Hz at 1 kHz offset frequency,
which corresponds to a figure of merit (FoM) of 276 dB.
Index Terms—Chirp injection, crystal oscillator, negative resistance booster (NRB), quartz crystal, quick start up, variation
tolerant.

I. I NTRODUCTIONFOR almost 100 years since their invention by Nicolson [1]and Cady [2] in the 1920s, crystal oscillators have been
one of the key components in radio-frequency (RF) transceivers
and digital circuits for generating an accurate and precise clock.
RF transceivers should regulate the transmission frequency inaccordance with wireless specifications (e.g., Bluetooth [3] and
Wi-Fi [4]) because the adjacent-channel interference degrades
the sensitivity of wireless receivers. For instance, the specifications of Bluetooth specify that the variation of the transmission
frequency should be less than ±75 kHz at a 2.4 GHz carrier
frequency. The total frequency variation, including those of theManuscript received May 16, 2015; revised October 21, 2015; accepted
November 05, 2015. Date of publication December 18, 2015; date of current
version January 29, 2016. This paper was approved by Associate Editor A. M.
Niknejad. This work was supported by STARC. The VLSI chips were fabricated in the chip fabrication program of VDEC in collaboration with Rohm
Corp. and Toppan Printing Corp. The work of S. Iguchi was supported by
Japan Society for the Promotion of Science through the Program for Leading
Graduate Schools (MERIT).
S. Iguchi, T. Sakurai, and M. Takamiya are with the University of Tokyo,
Tokyo 153-8505, Japan (e-mail: shiguchi@iis.u-tokyo.ac.jp).
H. Fuketa was with the University of Tokyo, Tokyo 153-8505, Japan. He is
now with the National Institute of Advanced Industrial Science and Technology(AIST), Ibaraki 305-8568, Japan.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2015.2499240

reference clock generator, phase-lock-loop (PLL), and clock
distribution circuits, has to be less than ±31 ppm. It is difficultfor on-chip CMOS oscillators to meet this requirement because
the typical frequency variation caused by temperature fluctuations is more than ±0.1% (= 1000 ppm) [5], [6]. A study of a
CMOS oscillator with on-chip heaters achieved ±115 ppm frequency variation [7]; however, the large area of 1.04 mm2 andpower consumption of 2.9 mW make it difficult to implement
such an oscillator in a highly integrated system on chip (SoC).
The frequency variation of crystal oscillators with an AT-cut
quartz crystal is less than ±100 ppm [8], [9], owing to the ultrahigh Q factor (>10, 000) of the quartz crystal. The stable andreliable characteristics of the quartz crystal have made crystal
oscillators the de facto standard for reference clock generators
in wireless communications.
Intermittent operation between the standby mode and theactive mode in wireless transceivers is a key technique in
reducing the power consumption because RF front-end circuits(e.g., power amplifiers and low-noise amplifiers) consume large
amounts of power in the active mode. In the standby mode,
the RF front-end circuits are disabled to reduce the power consumption. The crystal oscillator specifies the start-up time fromthe standby mode to the active mode because the start-up timeof the crystal oscillator is the longest among the circuits in an
RF SoC. The start-up times of the other circuit blocks such as
the low dropout (LDO) [10], [11] and PLL1 [12] are typicallyless than 10 µs. Most crystal oscillators with a frequency of
10 MHz order settle in 1–4 ms [13]–[18]. The slow start up of
the crystal oscillator increases the system latency even when thestart-up energy is not decreased by quick-start-up techniques.
To reduce the start-up time of crystal oscillators, several
quick-start-up techniques [19]–[24] have been reported. It has
been suggested that the start-up time would be greatly reduced
from 4 ms to 50 µs by using a constant-frequency injector(CFI) [19]–[21] if the injection frequency accurately matched
the resonant frequency (f0 ) of the quartz crystal. A fine digital calibration [20] can be performed to calibrate the injection
frequency; however, such a calibration requires an accurate andcomplex feedback loop including temperature sensors and voltage sensors. Additionally, some calibration techniques requirea memory circuit to restore the calibration data. The power andarea overheads are the drawbacks of the calibration techniques.
1 The settling time is about 100 times the period in the reference clock. The
typical settling time is 2.5 µs (= 100 × 25 ns) for a 39.25 MHz reference clock.

0018-9200 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

IGUCHI et al.: VARIATION-TOLERANT QUICK-START-UP CMOS CRYSTAL OSCILLATOR

497

of the inverter, Inv1 is the CMOS inverter used for steady-state
operation, and iM (= |iM |sinωt) is the current in the node containing LM , CM , and RM . According to theoretical studies [29],[30], the start-up time (tSTARTUP ) in a Pierce crystal oscillator
is given by
0.9ωOSC CT VDD
2LM
lntSTARTUP = −.
(1)
RM − |RN ||iM (0)|Fig. 1. Schematic of (a) Pierce crystal oscillator and (b) same oscillator with aconventional CFI.

The technique of automatic level control (ALC) [22] can reduce
the start-up time to 300 µs because a bias current generator andamplitude detector can boost the negative resistance in the initial state. The reduction ratio of the start-up time is limited by
the voltage headroom of the current sources in the feedback
loop. In this technique, it is difficult to reduce the start-up time
to more than four times less than the intrinsic start-up time of
1–4 ms. To achieve a stable and quick start up, even with fluctuations in the temperature and supply voltage, a crystal oscillator
with a chirp injector (CI) [23] and a negative resistance booster(NRB) [24] was reported in 2014 [23]. This paper reports a new
analysis of the theoretical minimum start-up time, which canbe used to develop new criteria to evaluate the start-up timein crystal oscillators. Additionally, an analysis of the CI and
NRB is used to derive a universal optimum control method fora variation-tolerant crystal oscillator with a CI and NRB.

II. A NALYSIS OF T HEORETICAL M INIMUMS TART-U P T IME
To clarify the theoretical minimum start-up time in crystal
oscillators, a theoretical analysis of the start-up time is givenin this section. Analysis and discussion for a conventional CFI[19]–[21] are given because the CFI is a prospective mean ofachieving the theoretical minimum start-up time, although it isdifficult to integrate, owing to fluctuations in the temperatureand supply voltage.

A. Start-Up Time in Pierce Crystal Oscillator
Pierce crystal oscillators [25], [26], can be used in many
applications owing to their low power and low phase noise(PN). In other types of oscillator with single-pin structures [27],[28], the large parasitic capacitance in parallel with the quartz
crystal increases the power and PN. Fig. 1(a) and (b) showsa schematic of a Pierce crystal oscillator and one with a CFI,
respectively. LM , CM , and RM are the motional inductor, capacitor, and resistor in the quartz crystal, respectively. C1 is thegate-to-ground capacitor, C2 is the drain-to-ground capacitor,
C3 is the parallel parasitic capacitor in the quartz crystal, R1
is the feedback resistor, R2 is the series resistor at the output

Assuming that R2 = 0 for conciseness, where ωOSC is
the oscillation angular frequency, VDD is the supply voltage,|iM (0)| is the amplitude of iM in the initial state, and RN and CT
are the negative resistance and load capacitance, respectively,
given byg m C1 C2(2)
RN = −
2
2
2(gm C3 ) + ωOSC (C1 C2 + C2 C3 + C3 C1 )
C1 C2
+ C3
(3)
CT =
C1 + C2
where gm is the equivalent transconductance of the CMOS
inverter. Equation (1) indicates that the start-up time is determined only by |iM (0)| and |RN | because the other parameters(CT , LM , ωOSC , RM , and VDD ) are determined by the target
specifications and the quartz crystal.
In this study, the start-up time is defined as the time at which|iM | reaches 0.9 times the amplitude in the steady state. Notethat the oscillation amplitude and start-up time should be measured at the gate voltage because the gate voltage (Out) is
proportional to iM . On the other hand, the drain voltage (X1)
is not suitable for the measurement because the waveform isclipped and distorted by the nonlinearity of transistors. In this
discussion of the definition of the start-up time, it is necessary to verify the consistency of the analysis and measurement
results. A real-time measurement of the frequency error would
be the most accurate way to define the start-up time; however,it failed to measure the small frequency deviation (< 100 ppm)
during the start up even with a 40 GSa/s digital storage oscilloscope (Agilent DSO81204A) using the jitter analysis option
owing to the resolution and noise of the oscilloscope. The realtime measurement of the frequency error is not available in theusual testing environment. Owing to this limitation, the oscillation amplitude is the only available and observable quantity
for defining the start-up time of the crystal oscillator. Several
studies [29]–[31] discussed the definition of the start-up timeand defined it in terms of the oscillation amplitude. In [31], thestart-up time is defined as the time at which |iM | reaches 0.9
times the amplitude in the steady state for three reasons.
1) The threshold at 90% amplitude is used for the transition of the pulse in digital circuits and many items of
measurement equipment support this threshold.
2) The drive level (= |iM |2 × RM /2) in a quartz crystal at
90% amplitude is stable and satisfies a specified level in adatasheet.
3) The frequency error at 90% amplitude is negligibly small.
A calculation in [31] gave a frequency error of 1.1 ppm at
90% amplitude.
Additionally, a simulation result for a quartz crystal at
39.25 MHz [32], as used in this study, shows that the frequency

498IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016

the gate-to-ground voltage (|VG |) in the steady state is approximately VDD /2. According to [33] and the definition of the startup, |iM | at the start up (|iM |STARTUP ) is given by|iM |STARTUP = 0.45ωOSC VDD (C1 + 2C3 ) .

Fig. 2. Strategy to reduce the start-up time of a crystal oscillator by noise injection and the use of an NRB. Temporarily increasing |iM (0+ )| and |RN | reduces
the start-up time.

error is within 10 ppm at 90% amplitude. The frequency error
at 90% amplitude should be acceptable for a wireless specification [3]. In this paper, the threshold is defined as 90% amplitude
for the above reasons.
Fig. 2 shows the strategy used to reduce the start-up time,
assuming that the period of noise injection (tNOISE ) is negligibly small. The values of |iM (0+ )| and |RN | correspond to
the y-intercept (≈ y-value at t = tNOISE ) and gradient of thelines in Fig. 2, respectively. To reduce the start-up time inthis study, |iM (0+ )| is first increased by noise injection, whichshifts the line vertically upward. After that, |RN | is increased by
employing the NRB, which increases the gradient of the line.
B. Analysis of Theoretical Minimum Start-Up Time
Under the ideal condition without any variations, anultrahigh-accurate CFI can achieve the theoretical minimum
start-up time because the y-intercept in Fig. 2 is directly shiftedto the steady-state amplitude by the CFI. On the other hand, therate of the amplitude increase of iM by time does not increasesignificantly when the NRB excessively boosts the negative
resistance owing to the capacitance of C3 in the quartz crystal;
therefore, the NRB cannot achieve the theoretical minimum.
The differential rectangular signals from the ring oscillator
charge up the resonator in the quartz crystal, and RM limits theminimum start-up time. The effect of R2 is ignored for simplicity because the cutoff frequency (> 1 GHz) of the low-passfilter of R2 and C2 is sufficiently higher than the oscillation
frequency. The transient of iM is calculated by solving thedifferential equation

4VDD
diM
1
sin ωt = LM
+ R M iM +(4)
iM dt.
πdt
CMAssuming that the harmonics of the rectangular signals
are negligible. The differential rectangular signal is given as
4VDD /π from the Fourier series at the fundamental frequency.
At ω = ω0 ≈ ωOSC , where ω0 is the series resonant frequency of the quartz crystal. The transient of |iM | is given byR
4VDD 
− M t
1 − e 2LM .
(5)|iM | =
πRM
Equation (5) is calculated with the assumption of iM (0) = 0
for simplicity. In many cases, iM (0) is negligibly small becauseiM (0) is determined by the thermal noise in the circuit. In a
Pierce crystal oscillator with a CMOS inverter, the amplitude of(6)

Assuming C1 = C2 for conciseness. By equating (5) and(6) asR
4VDD 
− M t
1 − e 2LM = 0.45ωOSC VDD (C1 + 2C3 ) .
(7)
πRMThe theoretical minimum start-up time (tSTARTUP_MIN ) for a
39.25 MHz quartz crystal [32] is obtained as follows:2LM
ln [1 − 0.35ωOSC RM (C1 + 2C3 )]RM= 11.1 µs.
(8)tSTARTUP_MIN ≈ −The theoretical minimum start-up time of 11.1 µs is 14.2
times shorter than the shortest start-up time in a state-of-the-art
oscillator [23]. This implies that the upcoming techniques could
achieve a much shorter start-up time (e.g., less than 100 µs) incrystal oscillators with frequency of 10 MHz order. A CFI is
not practical because the worst-case start-up time specifies theeffective start-up time for the whole system. Both a short startup time and small variations of the start-up time are importantfactors from the viewpoint of system design.
III. C HIRP I NJECTION AND NRB
A. Overview of Crystal Oscillator With CI and NRB
Fig. 3(a) and (b) shows a schematic of a crystal oscillator
with the proposed CI and one with the proposed CI and NRB,
respectively. The CI consists of a chirp generator to generate a chirp-modulated signal that sweeps the frequency froma high frequency (fH ) to a low frequency (fL ). In the frequency
range, the chirp-modulated signal is equivalent to a wide-band
signal and is used to cover variations in the process, supply voltage, and temperature (PVT). The CI instantaneously charges up
the resonator when the injection frequency matches the series
resonant frequency of the resonator. The specifications (e.g.,temperature range, reliability, and yield) of the system specify the sweep range between fH and fL . In this study, fH andfL are determined to be 2fOSC and 0.5fOSC by simulation,
respectively, where fOSC is the oscillation frequency in the
crystal oscillator. Fig. 4 shows a schematic of the chirp generator, which consists of a voltage-controlled oscillator (VCO) anda sweep circuit. The control voltage (VCNT ), which is swept by
a discharge circuit consisting of CCNT and RCNT , controls thefrequency of the VCO. When an enable trigger (CI_en) transits
from a low state to a high state, VCNT changes from VDD to 0 V.
The sweep speed and period (tCI ) are controlled by the valuesof CCNT and RCNT .
A digitally controlled NRB sets an auxiliary inverter (Inv3)
at an appropriate gate width for the minimum start-up time. A
control signal (NRB_en) controls the transient timing between
the boost mode and the steady state. |RN | temporarily increases
with a large gate width during an enabled period (tNRB ). Fig. 5

IGUCHI et al.: VARIATION-TOLERANT QUICK-START-UP CMOS CRYSTAL OSCILLATOR

499

Fig. 3. Schematic of a crystal oscillator (a) with the proposed CI and (b) withthe proposed CI and NRB.
Fig. 6. Simulated time dependences of (a) frequency in the proposed CI and(b) iM .

Fig. 4. Detailed schematic of the chirp generator consisting of a VCO and asweep circuit.

90% of that in the steady state. By disabling the NRB during
the steady-state operation, the power consumption and parasitic
capacitance in the NRB can be negligible in the steady state.
A large |iM (0)| and |RN | reduce the start-up time as shown by(1). The proposed CI reduces the start-up time and its variation
because the chirp-modulated signal instantaneously charges up
the resonator at the target frequency of 39.25 MHz even in
the case of fluctuations in the temperature and supply voltage. The new digitally controlled NRB also reduces the start-up
time by providing an appropriate gate width to minimize thestart-up time. Section III-B provides details of the control andtheoretical analysis carried out to minimize the start-up time.
B. Analysis for the Optimum Control of CI and NRB
This section provides the analysis for the optimum control and capability of the CI and NRB with scaling of theoperation frequency. First, the time-domain expression for achirp-modulated signal is given byω2 − ω1 2t(9)
f (t) = sin ω1 t +2TFig. 5. Timing chart for the crystal oscillator with the proposed CI and NRB.
The NRB boosts |RN | during the period denoted by tNRB because the transistors in Inv3 are in the linear region during the period denoted by tCI . In thisstudy, the start-up time is determined as that when the oscillation amplitude
reaches 0.9 times the peak-to-peak amplitude (A) in the steady state.

where ω1 , ω2 , and T are the starting angular frequency, thefinal angular frequency, and the time period in chirp modulation, respectively. Using (9), CI charges up the resonator inaccordance with the differential equationdiM
ω2 − ω1 2
4VDD
sin ω1 t ++ R M iM
t = LM
π
2tCI
dt

1
iM dt.
+(10)CMshows a timing chart for the crystal oscillator with the CI
and NRB. First, a wake-up signal pulls up both CI_en and
NRB_en. While CI_en is high, the signal at chirp excites Out
and X1. After that, the NRB with Inv3 increases |RN | during
the period denoted by tNRB in Fig. 5. Finally, the NRB disablesthe |RN | boost when the oscillation amplitude in Out reaches

Figure. 6(a) and (b), respectively, shows the simulated injection frequency and the transient of iM corresponding to (10).
The simulation result and (10) match when the driver in the
CI can drive the load capacitors (C1 and C2 ) with rail-to-railswing. If the drive strength is insufficient, the energy charged
by the CI decreases owing to the small amplitude of the swing.
In this work, the driver is designed with sufficient drive strength500IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016

Fig. 7. Simulated gate width dependence of |RN | normalized by the gate widthof Inv1.

to drive a heavy capacitive load (C1 > 12 pF). The amplitude ofiM rapidly increases when the injection frequency matches f0 .
By solving (10) for iM assuming that the Q factor (Q) of thequartz crystal is sufficiently larger than one, the final amplitudeof iM (|iM |CI ) at t = tCI is given by4ω0 CM VDD
tCI
4VDD
(11)
= √
|iM |CI =LM
2π |ω2 − ω1 |
2πS
where S = |ω2 − ω1 |/ω02 tCI , which is the slope factor normalized by ω0 . Equation (11) is derived in Appendix A. When theoscillation frequency is scaled with a fixed S, (11) indicatesthat |iM |CI is proportional to ω0 because CM and VDD do notvary with frequency scaling. Temperature-compensated oscillators should achieve a small S and a short start-up time because
the sweep range in the CI is determined by the frequency variation of the VCO for noise injection. Additionally, the sweep
direction (ωH → ωL or ωL → ωH ) does not affect |iM |CI and thestart-up time when Q is sufficiently larger than one.
Fig. 7 shows the gate width dependence of |RN | normalized
by the gate width of Inv1. The NRB configures the gate widthof Inv3 to achieve a maximum |RN | (|RN |MAX ) in the interval tCI < t < tSTARTUP . In the initial state, the optimum gate
width takes a value of |RN |MAX given by|RN |MAX =

2C3



rO C1


1 + 1 + ω0 2 rO 2 C1 2

(12)

where rO is an equivalent output resistance in the NRB.
Equation (12) is derived in Appendix B. When rO is sufficiently
large, (12) is approximated to|RN |MAX ≈1.
2ω0 C3(13)

Equation (13) is a well-known expression for long-channeltransistors introduced by [34]. To reduce the start-up time, careful PCB design and a layout to ensure a small C3 are required
because a large C3 reduces |RN |MAX . Using (13), |RN |MAX ,and RM = 1/ω0 QCM , the time dependence of |iM | (|iM |NRB )in the interval tCI < t < tSTARTUP is given and approximatedby|iM |NRB = |iM (0)| e−

R M − |R N |
MAX t
2LM

1−2/ Q≈ |iM (0)| e 4C3 / CM

ω0 t

.
(14)

Fig. 8. Simulated time dependences of |iM | with sweep ranges of (a) 6 MHz
and (b) 60 MHz. The transients of |iM |CI shown by a black line and |iM |NRB
shown by a gray line become tangents at a universal tCI . Points A and B denotethe start-up times for |f2 − f1 | of 6 and 60 MHz, where f1 and f2 denote thestarting frequency and final frequency, respectively. A small S with |f2 − f1 |of 6 MHz achieves a shorter start-up time than that with |f2 − f1 | of 60 MHz.

The detailed derivation of (14) by Laplace transformation isshown in [29] and involves considerable mathematical manipulation. On the other hand, (14) is easily derived from (5)with the substitution RM → RM − |RN |MAX . The first term on
the right-hand side of (5) is negligible because the first term,
corresponding to the steady-state amplitude and amplitude saturation in linear circuit analysis, is about 100 times larger than|iM |STARTUP in (6). During the start up of the crystal oscillator, the effect of the amplitude saturation expressed by the firstterm on the right-hand side of (5) is negligibly small. |iM (0)| isthe equivalent amplitude of iM at t = 0 and is used for mathematical manipulation. Here, |iM (0)| has no physical meaning
because the initial value of |iM | for the NRB is determined by
the CI as shown by (11). Equation (14) indicates that |iM |NRB is
proportional to exp(ω0 ) in the case of frequency scaling because
Q, C3 , and CM are not scaled parameters.
The optimum tCI (tCI_OPT ) for switching from the CI to the
NRB is a tangent point between the two lines given by (11) and(14). By differentiating (11) and (14), tCI_OPT is given by
1
LM
2C3
∝
≈
.
tCI_OPT = −RM − |RN |MAX
ωOSC CM (1 − 2/ Q)
ωOSC
(15)
Assuming that ωOSC ≈ ω0 . Equation (15) is derived inAppendix C. Using (15), S is expressed by
S = CM |ω2 − ω1 | (|RN |MAX − RM )≈|ω2 − ω1 | CM (1 − 2/ Q)
.
ωOSC
2C3

(16)

Equation (16) implies that S is determined by the frequency
error (= |ω2 − ω1 |/ωOSC ) of the VCO due to PVT variations.
Interestingly, tCI_OPT is a universal parameter for an arbitrary
S. This indicates that circuit designers can specify tCI for the
CI regardless of the variation and sweep range of the VCO.
Fig. 8(a) and (b) shows simulated time dependences of |iM |with sweep ranges of 6 and 60 MHz, respectively. The transients of |iM | switch from |iM |CI to |iM |NRB at a universal

IGUCHI et al.: VARIATION-TOLERANT QUICK-START-UP CMOS CRYSTAL OSCILLATOR

501

TABLE ID ESIGN PARAMETERS AND P ERFORMANCE S UMMARY

Fig. 9. Die micrograph and layout fabricated in 180 nm CMOS process.

tCI_OPT of 12.5 µs, corresponding to the tangent point, evenwith different sweep ranges. From (1), (11), (13), and (15),the start-up time (tSTART_OPT ) when using the CI and NRB isgiven by
 2 
CT1
S − 0.15 ∝. (17)tSTARTUP_OPT = tCI_OPT ln
ωOSC
CM 2
Equation (17) is derived in Appendix D and verifies thattSTART_OPT does not depend on gm in Inv1 and Inv3. The relative sweep range of the VCO (proportional to S) is the only
variable parameter for the circuit designer at a target frequency.
When an accurate oscillator (e.g., relaxation oscillator) for the
CI is available, a small S can be used to minimize the start-up
time because a small S increases |iM |CI . A comparison of thestart-up time with different S is shown in Fig. 8. S in Fig. 8(a) is
10 times smaller than that in Fig. 8(b). The smaller S achieves ashorter start-up time because |iM |CI is closer to the steady state(≈ |iM |STARTUP ) than that with the larger S. Reducing S is the
only way to reduce the start-up time from the viewpoint of circuit design; otherwise, a quartz crystal with small C3 and CT
is required. Additionally, S (proportional to |ω2 − ω1 |/ωOSC )does not change significantly with PVT variations because thevariation of the delay in the transistors changes ω1 , ω2 , andωOSC by the same ratio. The variations of RCNT and CCNT
should also be considered. Assuming ±40% variations of the
RC product (approximately inversely proportional to S), thevariation of the start-up time calculated with (17) is less than
±7% because the variation of S is scaled down by ln(S). That is
why the start-up time in the proposed crystal oscillator with the
CI and NRB does not change significantly with PVT variations.
Finally, noted that the approximated expressions in (13)–(17)are effective for long-channel transistors. If short-channel transistors are used, the exact expressions should be adopted forcircuit optimization. Additionally, |RN | in the exact expressions
should be estimated by simulation owing to the inaccuracy inthe modeling of rO [35].
IV. M EASUREMENT R ESULTS AND D ISCUSSION
To demonstrate and verify the quick-start-up operation, theproposed crystal oscillator with the CI and NRB is implemented as shown in Fig. 3(b); additionally, the previous CFI
shown in Fig. 1(b) is also implemented in the same die to evaluate the effects of the proposed CI and NRB. Fig. 9 shows
the die micrograph and the layout, which was fabricated in a
180 nm CMOS process. Electrostatic discharge (ESD) is implemented with a body diode between the drain and well of thetransistors. The transistor-based structure can be simulated by

SPICE simulations without additional device simulations intechnology computer-aided design (TCAD). The target oscillation frequency of the quartz crystal is 39.25 MHz with a load
capacitance (CT ) of 8 pF [32]. The passive components (e.g.,
R1 , R2 , C1 , C2 , and the quartz crystal) are implemented on an
FR4 PCB. To compensate the parasitic capacitors on the PCB,
the values of C1 and C2 are carefully chosen. The test chip is
directly mounted on the PCB with an electrically conductive
epoxy. The bare chip and PCB are connected by bonding wires.
Table I shows the design parameters and a summary of theperformance of the proposed crystal oscillator. The start-up
time and power consumption without the CI and NRB are
2.1 ms and 181 µW, respectively. These values are comparable to those in other works [13]–[18] without quick-start-up
techniques. In the proposed crystal oscillator, 8 bit digitallycontrolled gate widths in Inv1 and Inv3 are used to configure the negative resistances in the steady-state and boost mode
to obtain an oscillation allowance of more than five [36] and
RN_MAX , respectively. The series resistance (R2 ) reduces theinjection power into the quartz crystal and prevents overtone
oscillation due to the parasitic inductors on the PCB.
The measured injection time dependence of the start-up timewith the previous CFI is shown in Fig. 10. To verify the consistency of the analysis in Section II, an arbitrary function generator (Tektronix AFG 3251) accurately regulates the injection
frequency within a variation of ±1 ppm. A tristate buffer in the
CFI is used to vary the injection time within 0−15 µs. The minimum measured start-up time is 12.8 µs. This result verifies thatthe discussion on the theoretical minimum start-up time is valid.
Fig. 11 shows the measured injection frequency dependenceof the start-up time with the previous CFI. The CFI injects
a constant-frequency signal for an injection time of 40 µs.

502Fig. 10. Measured injection time dependence of the start-up time with the previous CFI. In this measurement, an arbitrary function generator (Tektronix AFG
3251) generates an accurate injection signal to achieve good matching between
the injection frequency and the resonance frequency of the quartz crystal. The
measurement result verifies that the theoretical analysis in Section II is valid.

Fig. 11. Measured frequency dependence of the start-up time with the previous
CFI. To input an accurate injection frequency for the quartz crystal, an arbitrary function generator (Tektronix AFG 3251) injects the injection signal for
an injection time of 40 µs. The variation of the start-up time is caused by thefrequency error of the ring oscillator.

The measured start-up time with the CFI varies within 40–1067 µs depending on the injection frequency, which varies
in the range 38.0–40.5 MHz. The measured frequency variation of the embedded ring oscillator in the CFI is ±9% over
the temperature range of −30 to 125 ◦ C at the supply voltageof 1.5 V. The start-up time in the case of 0.1% variation varies
within 40−500 µs. A crystal oscillator [21] with 0.25% variation using a temperature-compensated RC oscillator achieves ashorter start-up time; however, this implies that a variation of
0.25% causes the start-up time to vary.
Measured time dependences of the chirp frequency in the
chirp generator are shown in Fig. 12. To compensate the effectof the parasitic capacitances on the PCB, the target tCI is set
to 40 µs using (15). The design target of the initial frequency
at a typical corner is 80 MHz. The chirp frequency crosses theoscillation frequency of the crystal oscillator over the best andworst corners in the test chip. The measured oscillation frequency in the VCO is 16% lower than the simulated frequency
owing to model mismatches and process variations. This test
chip matches the case of a slow transistor model in a process
design kit (PDK). This verifies that the chirp frequency crosses
39.25 MHz even in the worst case (= 1.35 V, 125 ◦ C, slow
device).

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016

Fig. 12. Measured time dependences of the frequency in the proposed CI at
three corners. All lines cross the target frequency of 39.25 MHz once before
tCI = 40 µs.

Fig. 13. Measured gate width dependences of the start-up time and the power
consumption of the proposed NRB in the steady state with infinite tNRB . The
gate width for the NRB is normalized by that of Inv1.

Fig. 13 shows the measured gate width dependences of thestart-up time and the power consumption of the NRB in thesteady state with a disabled CI and infinite tNRB . The gate width
for the NRB is normalized by that of Inv1. With increasing thegate width, |RN | increases and the start-up time decreases atthe cost of increasing the power consumption. The NRB in
the proposed crystal oscillator uses a normalized gate widthof 13, corresponding to the maximum |RN |, which minimizes
the start-up time because the aim of this study is to clarify
the theoretical limitation of the start-up time with the CI and
NRB. Additionally, the slow start-up time increases the system
latency from the standby mode to the active mode in an RF SoC.
If the start-up energy is the most important factor for the system, the optimum gate width will be smaller than the gate width
used in this paper because the start-up time at a gate width of
5–10 is not significantly larger than the minimum start-up time.
The optimum gate width should be determined from the total
start-up energy and the latency in the whole system. In this case,the start-up time is reduced by 87%, while the power consumption increases by a factor of 4.9. In the measurements, the NRB
is disabled at the time that the gate voltage at Inv1 reaches 0.9
times the amplitude in the steady state. A comparator or Schmitt
trigger could be used to detect and disable the NRB dependingon the oscillation amplitude. The optimum gate width is determined as the gate width corresponding to the maximum |RN |,which minimizes the start-up time of the crystal oscillator.

IGUCHI et al.: VARIATION-TOLERANT QUICK-START-UP CMOS CRYSTAL OSCILLATOR

503

Fig. 14. Measured start-up waveforms for (a) conventional Pierce crystal oscillator in Fig. 1(a) and (b) proposed Pierce crystal oscillator with the CI and NRB
in Fig. 3(b). The proposed CI and NRB reduce the start-up time from 2.1 ms to158 µs at a temperature of 25 ◦ C and supply voltage of 1.5 V.
Fig. 16. Measured temperature dependences of the start-up time in the fourtypes of crystal oscillator. The start-up times without any quick-start-up
technique, with the CFI, with the CI, and with the CI and NRB are compared.

Fig. 15. Measured supply voltage dependences of the start-up time in fourtypes of crystal oscillator. The start-up times without any quick-start-up
technique, with the CFI, with the CI, and with the CI and NRB are compared.

The measured start-up waveform of the crystal oscillator
without the CI and NRB is shown in Fig. 14(a). Fig. 14(b)shows the start-up waveform with the proposed CI and NRB.
By combining the CI and NRB, the start-up time is reduced by
92% from 2.1 ms to 158 µs at a temperature of 25 ◦ C and supply voltage of 1.5 V. Note that the proposed CI and NRB givean additional step response and frequency deviation when they
are turned OFF. The frequency transient induced by the NRB
is of most concern for the proposed crystal oscillator because
the NRB is turned OFF last. The NRB varies the oscillation
frequency because it uses a 13 times larger inverter than thatfor a steady state to increase the negative resistance. The parasitic capacitance in the NRB reduces the oscillation frequency
to within 5 ppm. A frequency transient of within 5 ppm resulting from the step response of the disabled signal is acceptable
for a wireless specification [3]. Additionally, no fluctuations or
glitches due to the CI and NRB are observed in the transition
from the boost mode to the steady state using a high-speed digital storage oscilloscope (Agilent DSO91294A). These results
verify that the proposed technique can reduce the start-up time
without introducing critical frequency deviations.
Fig. 15 shows measured supply voltage dependences of thestart-up time in four types of crystal oscillator at a temperatureof 25 ◦ C. The supply voltage is varied by ±20% from the typical value of 1.5 V to evaluate the variation of the start-up time.
The variation of the start-up time in the conventional CFI ismuch larger than that in the proposed CI because the calibrated
frequency in the ring oscillator at the supply voltage of 1.5 V

Fig. 17. Simulated start-up energy in the crystal oscillator with the proposed
CI and NRB. ECI , ENRB , and PSTEADY are the start-up energy in the period
denoted by tCI , the start-up energy in the period denoted by tNRB , and thepower consumption in the steady state, respectively. The start-up energy is
reduced from 380 to 349 nJ.

Fig. 18. Measured PN of the crystal oscillator in the steady state.

varies owing to the supply voltage variation. The CI is morevariation tolerant than the CFI because the slope factor variation in the CI is smaller than that of the oscillation frequency.
Additionally, the start-up time is reduced by the proposed NRB.
In the crystal oscillator with the CI and NRB, the measured
start-up times with ±20% supply voltage variation are within
145–179 µs, corresponding to a relative variation of ±13%.
Fig. 16 shows measured temperature dependences of thestart-up time in the four types of crystal oscillator at a
supply voltage of 1.5 V. The temperature is varied within−30 to 125 ◦ C. The temperature dependences are similar to504

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016

TABLE IIC OMPARISON WITH P REVIOUS W ORKS

those in Fig. 15. The start-up times for temperatures in the rangeof −30 to 125 ◦ C are 147–162 µs, corresponding to a relative
variation of ±7%.
The minimum start-up time is mainly limited by the frequency variation of the VCO and the nonlinearity of the transistors. The large frequency error of the VCO requires a broad
sweep of ω2 − ω1 and a large S. Additionally, the nonlinearity of the transistors gradually reduces the negative resistanceand the gradient of |iM |NRB in Fig. 8. An increase in the startup time of 60 µs caused by the nonlinearity would limit theminimum start-up time in this design.
The simulated start-up energy in the crystal oscillator with
the CI and NRB is shown in Fig. 17. ECI , ENRB , and PSTEADY
are the start-up energy in the period denoted by tCI , the start-up
energy in the period denoted by tNRB , and the power consumption in the steady state, respectively. Note that ECI and ENRB
are carefully calculated by block-level simulations because afull-blown circuit simulation with CI and NRB is not practicalowing to the very long simulation period.2
Specifically, a transient simulation with both oscillator coreand digital circuits requires an incredibly long period. This is
one of the issues in crystal oscillator design even with state-ofthe-art simulators [37]. On the other hand, the measurement of
the start-up energy is also difficult because of the limited time
resolution (>100 µs) for the current measurement with a dc
power supply (ADCMT 6240A). The start-up energy with the
CI and NRB is 349 nJ during the start-up time of 158 µs, compared with 380 nJ during the start-up time of 2.1 ms without any
quick-start-up technique. The proposed crystal oscillator has asmaller start-up energy than the crystal oscillator without the CI
and NRB.
Fig. 18 shows the measured PN of the proposed crystal oscillator in the steady state. The measured PN at 1 kHz offset
frequency is −147 dBc/Hz, comparable to that in previous
works. A carefully designed PCB layout with a small C3 isimportant to reduce the PN and power consumption. The measurement result verifies that the quick-start-up technique does
not increase the PN because the CI and NRB are not active inthe steady state.
2 In many cases, a full-blown transient simulation for a crystal oscillator takes
more than one week because the time step should be short for an ultrahigh-Q
resonator.

A summary of the performance of the proposed crystal oscillator and a comparison with those in previous works [13],[17], [18], [21], [38] are shown in Tables I and II, respectively. The frequency variations resulting from fluctuations in
the temperature and supply voltage are ±5.5 and ±0.6 ppm,
respectively. These values satisfy the typical requirement of lessthan ±31 ppm for a Bluetooth transceiver [3]. The crystal oscillator does not exceed the maximum drive level (= 200 µW) of
a quartz crystal [32], defined as |iM |2 × RM /2, even with the
NRB. The transient of |iM | in Fig. 8 shows this consistency.
The proposed crystal oscillator has a start-up time of 158 µs
with a variation-tolerant design. The power consumption in thesteady state is 181 µW with a PN of −147 dBc/Hz at 1 kHz
offset frequency (fOFFSET ). The corresponding figure of merit(FoM) [12] is 276 dB, where the FoM is defined as
FoM =fOSC 2.
PSTEADY × PN × fOFFSET 2(18)

V. C ONCLUSION
A variation-tolerant quick-start-up 39.25 MHz crystal oscillator with a CI and NRB was presented. This is the first reportof a variation-tolerant quick-start-up crystal oscillator. The proposed CI and NRB reduce the start-up time and its variation byusing a variation-tolerant chirp-modulated signal and a maximum negative resistance. To clarify the theoretical limit of thestart-up time in crystal oscillators, this paper presented a new
analysis of the theoretical minimum start-up time and obtained
a value of 11.1 µs for a 39.25 MHz quartz crystal. A discussion
on the optimum control for the proposed CI and NRB gave thereason why the proposed CI and NRB reduce the start-up timeand its variation by introducing a slope factor (S). The proposed
universal optimum control method automatically specifies thecircuit design, which depends on the quartz crystal and its frequency. The proposed crystal oscillator exhibits a start-up timeof 158 µs at 39.25 MHz with a variation of ±13% over the
supply voltage range of 1.2–1.8 V. The power consumption and
PN at 1 kHz offset frequency are 181 µW and −147 dBc/Hz,
respectively.

IGUCHI et al.: VARIATION-TOLERANT QUICK-START-UP CMOS CRYSTAL OSCILLATORA PPENDIX A
D ERIVATION OF (11)with the normalized expression

In this appendix, (11) is derived. Equation (11) is derived bysolving the differential equation of (10). First, the left-hand sideof (10) is transformed toω2 − ω1 2
4VDD
sin ω1 t +
t
V =
π
2tCI


(A1)
4VDD
ω 2 − ω 1  2 =
sin ω 1 t +t
π2t CI
with the normalized expressionstt = √LM C Mω  = ω LM C M
tCI.
tCI = √LM C M

(A2)
(A3)
(A4)

Equation (A1) is differentiated with respect to t as
 


dV
4VDD 
ω 2 − ω 1 ω 2 − ω 1  2
 
=
+
t
t
+
t
cos
ω
.
ω
1
1
dt
π
t CI
2t CI(A5)
ω1 → 0

505

iM =

d 2 i M+ iM ≈ St cosdt 2ω2 − ω1
ω 2 − ω 1
× LM C M =
.
tCI
t CI

(A7)

CM diM+ iM =LM dt

CM dV.
LM dt

(A10)

By substituting (A8) into (A10), (10) becomes
d2 iM
+ RM
dt 2

CM diM+ iM =LM dt

S 2
CM 4VDD St
cos t .
LM
π
2
(A11)


S 2
t
2

(A15)

4ω0 CM VDD
√
2πS

(A16)

Finally, (11) is derived as|iM |CI =by substituting (A13) into (A15).

In this appendix, (12) is derived. When the effect of anequivalent output resistance (rO ) in the inverter is assumed, thenegative resistance is given as|RN | = C 2 (1+ω 2 r 2 C 2 )
1

0

1

O

gm rO −1

rO C1 2
+ 2C1 C3 + C3 2 (gm rO − 1)f  (gm ) = 0

(B1)



gm_OPT =C3 + C1

1 + ω 2 rO 2 C1 2
.
rO C3

(B3)

By substituting (B3) into (B1), the maximum value of thenegative resistance (|RN |MAX ) is obtained as|RN |MAX =

(A12)

(B2)

to calculate the maximum value of |RN |. Then, the solution of(B2) corresponding to the optimum value of gm (gm_OPT ) for
the NRB is given by

Equation (A11) is simplified to
1 di Md2 i M+
+ iM = St cos
Q dt
dt 2

π
.
2S

|iM |CI =(A9)is transformed by (A2) to
d iM
+ RM
dt 2

(A14)

with C1 = C2 . Here, the function f (gm ) = |RN | is defined. The
derivative of f (gm ) with respect to gm is equated to zero

The derivative of the right-hand side of (10)

2


S 2
t
.
2

A PPENDIX B
D ERIVATION OF (12)By introducing the slope factor into (A6), the derivative ofthe left-hand side of (10) becomes


S 2
dV
4VDD St
cos
t
=
.
(A8)
dt
π
2

iM
dV
d 2 iM
diM= LM 2 + R M
+
dt
dt
dt
CM



The normalized final amplitude (|iM |CI ) is calculated bysolving (A14) with respect to t . However, the complete expression for the solution of (A14) is too complex to describe
here because it includes many Fresnel integrals. |iM |CI corresponding to the amplitude of the solution at infinite t isgiven bywhere a normalized slope factor (S) is defined as
S=

(A13)

When Q is sufficiently larger than one, (A12) is approximated toω2 → ω2 − ω1

andsimplifies
The substitution of(A5) to

 


dV
ω 2 − ω 1  2
4VDD ω  2 − ω  1 
=
t cos
t
(A6)
dt
π
t CI
2t CI

LM
iM .
CM

π
4VDD

2C3



rO C1
.

1 + 1 + ω0 2 rO 2 C1 2

(B4)

506

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016

Equation (C4) is simplified by substituting (C2) into (C4) to
give

2VDD
t
d|iM |NRB=−. (C5)(RM − |RN |MAX )dt
2π |ω2 − ω1 |LM 2
By equating (C3) and (C5), the optimum tCI (tCI_OPT ) corresponding the tangent point between the two lines given by(11) and (14) is derived as
tCI_OPT = −LM.
RM − |RN |MAX(C6)

A PPENDIX D
D ERIVATION OF (17)Fig. 19. Time dependences of |iM | with tCI of (a) 12.5 µs and (b) 60 µs calculated using (11) and (14) with |f2 − f1 | = 60 MHz. The shortest start-up timeis achieved at tCI of 12.5 µs, corresponding to the tangent point of two lines.

A PPENDIX CD ERIVATION OF (15)t

= |iM (0)| e−

R M − |R N |
MAX t
2LM

2π |ω2 − ω1 |
R M − |R N |
MAX t
t
4VDD
2LM
e
.
|iM (0)| =LM
2π |ω2 − ω1 |

|


−

LM
R M − |R N |MAX. (D1)|iM (0)| =4ω0 CM VDD
√
.
2πeS

(D2)

Substituting (D2) into (1) and using (15), the start-up time isderived as
0.9ωOSC CT VDD
2LM
lntSTARTUP = −RM − |RN ||iM (0)|√0.9CT 2πeS
= 2tCI_OPT ln
4CM
 2
 2 

0.9 × 2πeCT
S + ln= tCI_OPT ln
C2
42 M2 
CT≈ tCI_OPT ln(D3)
2 S − 0.15 .
CM

ACKNOWLEDGMENT(C1)

The authors thank Mr. R. Shidachi of the University of Tokyo
for the support in measurements.

(C2)
R EFERENCES

To derive the tangent point, the derivatives of (11) and (14)with respect to t are calculated as
1
2VDD
d|iM |CI=dtLM
2πt |ω2 − ω1 |R − |R− M 2L N MAX
4ω0 CM VDD
M√= |iM (0)| e
2πSThen, |iM (0)| is given by

In this appendix, (15) is derived. First, it is verified thatthe optimum tCI (tCI_OPT ) is determined at a tangent point
between the two lines given by (11) and (14). Fig. 19(a) and(b) shows the time dependences of |iM | with tCI of 12.5 and60 µs calculated using (11) and (14) with |f2 − f1 | = 60 MHz.
The calculated dependences verify that the start-up time is minimized at tCI of 12.5 µs, corresponding to the tangent point
because |iM (0)| in (14) becomes the maximum value at tCI of
12.5 µs. Note that (11) in Fig. 19 does not include the effectof the nonlinearity of the transistors and that the calculated
start-up time is shorter than that in Fig. 8. The start-up timein Fig. 19(a) corresponds to that calculated by extrapolating|iM |NRB in Fig. 8(b).
The tangent point is derived from (11) and (14) using thisfinding. To find the optimum tCI , |iM (0)| is calculated byequating (11) and (14) as follows:
4VDD
LM

In this appendix, (17) is derived. Equations (11) and (14) areequated at t = tCI_OPT as(C3)

R − |R |RM − |RN |MAX
d|iM |NRB− M 2L N MAX t
M=−|iM (0)| e. (C4)dt
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crystal oscillator,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun.
2013, pp. C142–C143.

Shunta Iguchi (S’12) received the B.S. degree inelectronic engineering from the University of ElectroCommunications, Tokyo, Japan, in 2011, and the
M.S. degree in electrical engineering and information systems from the University of Tokyo, Tokyo,
Japan, in 2013, where he is currently pursuing the
Ph.D. degree.
From August 2011 to September 2011, he worked
with Analog Devices, Tokyo, Japan. From August
2013 to September 2013, he worked with Toshiba,
Kawasaki, Japan. From August 2014 to October
2014, he worked with Taiwan Semiconductor Manufacturing Company Limited(TSMC), Hsinchu, Taiwan. His research interests include the design of lowpower RF transceiver circuits, crystal oscillators, and wireless power transmission circuits.
Mr. Iguchi is the recipient of the Best Paper Award at the 2013 IEEE WirelessPower Transfer Conference.
Hiroshi Fuketa (S’07–M’10) received the B.E.
degree in electrical and electronic engineering from
Kyoto University, Kyoto, Japan, in 2002, and the
M.E. and Ph.D. degrees in information systems engineering from Osaka University, Osaka, Japan, in 2008
and 2010, respectively.
From 2010 to 2015, he was a Research Associatewith the Institute of Industrial Science, University ofTokyo, Tokyo, Japan. Since April 2015, he has beenworking with the Nanoelectronics Research Institute,
National Institute of Advanced Industrial Science andTechnology (AIST), Ibaraki, Japan. His research interests include ultra-lowpower circuit design and large-area electronics with organic transistors.
Dr. Fuketa is a member of IEICE.
Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in electrical engineeringfrom the University of Tokyo, Tokyo, Japan, in 1981.
In 1981, he joined Toshiba Corporation, Tokyo,
Japan, where he designed CMOS DRAM, SRAM,
RISC processors, DSPs, and SoC solutions. He has
worked extensively on interconnect delay and capacitance modeling known as Sakurai model and alphapower-law MOS model. From 1988 to 1990, he wasa Visiting Researcher at the University of California,
Berkeley, CA, USA, where he conducted research in
the field of VLSI CAD. From 1996, he has been a Professor with the Universityof Tokyo, working on low-power high-speed VLSI, memory design, interconnects, ubiquitous electronics, organic ICs, and large-area electronics. He is a508

Domain Research Supervisor for nano-electronics area in Japan Science andTechnology Agency, Tokyo, Japan. He has authored more than 600 technicalpublications including 100 invited presentations and several books, and filed
more than 200 patents.
Dr. Sakurai is an IEICE Fellow. He was the Executive Committee Chair for
VLSI Symposia and a Steering Committee Chair for the IEEE A-SSCC. He
served as a Conference Chair for the Symposium on VLSI Circuits and ICICDT,a Vice Chair for ASPDAC, a TPC Chair for the A-SSCC and VLSI Symposium,
an Executive Committee Member for ISLPED, and a Program Committee
Member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED, andother international conferences. He was an elected AdCom Member for theIEEE Solid-State Circuits Society, and the IEEE CAS and SSCS Distinguished
Lecturer. He is the recipient of the 2010 IEEE Donald O. Pederson Award in
Solid-State Circuits, the 2009 and 2010 IEEE Paul Rappaport Award, the 2010
IEICE Electronics Society Award, 2009 IEICE achievement Award, the 2005
IEEE ICICDT Award, the 2004 IEEE Takuo Sugano Award, and the 2005 P&I
Patent of the Year Award, and four product awards. He was a keynote speakerat more than 50 conferences including ISSCC, ESSCIRC, and ISLPED.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 2, FEBRUARY 2016

Makoto Takamiya (S’98–M’00–SM’14) received
the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan,
in 1995, 1997, and 2000, respectively.
In 2000, he joined NEC Corporation, Tokyo, Japan,
where he was engaged in the circuit design of highspeed digital LSIs. In 2005, he joined the Universityof Tokyo, where he is an Associate Professor of VLSI
Design and Education Center. From 2013 to 2014,
he stayed at the University of California, Berkeley,
CA, USA, as a Visiting Scholar. His research interests
include the circuit design of the low-power RF circuits, the ultra low-voltage
logic circuits, the low-voltage power management circuits, and the large-areaand flexible electronics with organic transistors.
Dr. Takamiya is a member of the Technical Program Committee of the IEEE
International Solid-State Circuits Conference and the IEEE Symposium on
VLSI Circuits. He was the recipient of the 2009 and 2010 IEEE Paul RappaportAwards and the Best Paper Award in 2013 IEEE Wireless Power Transfer
Conference.