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PAPER

Special Section on Analog Circuits and Related SoC Integration Technologies

1 Gb/s, 50 µm × 50 µm Pads on Board Wireless Connector Based on
Track-and-Charge Scheme Allowing Contacted Signaling
Katsuyuki IKEUCHI†a) , Student Member, Hideki KUSAMITSU†† , Mutsuo DAITO†† ,Gil-Su KIM††† , Nonmembers, Makoto TAKAMIYA† , Member, and Takayasu SAKURAI† , Fellow

SUMMARY
A capacitive coupling wireless connector circuit is implemented with 50 μm × 50 μm pads, which is a 25X reduction of pad size
compared with previous wireless connectors by allowing contacting andnon-contacting modes. The proposed track and charge scheme allows
both contacting and non-contacting communication through PCB capacitive pads. By making the precharge level of the input VDD or VSS , insteadof 1/2 VDD , the time necessary to precharge is reduced. The proposed
digitally tunable comparator does not require analog voltages, reduces thepower to less than 1/20 at lower frequencies compared to previous capacitive coupling receivers. A test chip successfully transmitted and received
1 Gb/s, 27 − 1PRBS signal at 1 mW while increasing design freedom of thewireless connectors.
key words: capacitive coupling, proximity communication, wireless connectors

1.

Fig. 1 Examples of wireless connectors (a) showing capacitive coupling
pads and (b) in closed circuit configuration. (Structure applicable but not
used in this work)

Introduction

Wireless connectors are a promising means of connecting
highly parallel channel between two boards with small feature sizes. They provide a means to overcome some ofthe shortcomings of conventional mechanical connectors byincreasing pin density, reducing height, reducing insertion
force and providing higher reliability [1]. In a wireless connector, the proximity coupling of two terminals is madeby a flexible Printed Circuit Board (PCB) as is shown in
Fig. 1, where small pressure is generated by natural bending of the flexible PCB. For this application, a capacitive
coupling approach has advantages over inductive coupling
counterpart [2] since a coil pattern for the inductive coupling on a PCB consumes more than 10 times the area of asimple square pad area needed for the capacitive couplingassuming the same line and space design specifications on
the PCB. The clearance rules of through-hole vias on PCBs
hider the use of them for the interface. The schematic diagram of a generic capacitive coupling interface is shownin Fig. 2. When the output of the TX swings rail-to-rail,
the signal swing at the receiver side, RXIN , is expressed as
VDD CC /(CPR + CC ), where CC is the coupling capacitanceof the coupling pads and CPR is the parasitic capacitance on
the RX side. CPR includes capacitances of the wiring on
Manuscript received October 14, 2010.
Manuscript revised January 18, 2011.
†
The authors are with The University of Tokyo, Tokyo, 1538505 Japan.
††
The authors are with Association of Super-Advanced Electronics Technologies (ASET), Tokyo, 104-0033 Japan.
†††
The author is with Samsung Electronics, Seoul, Korea.
a) E-mail: ikeuchi@iis.u-tokyo.ac.jp
DOI: 10.1587/transele.E94.C.992

Fig. 2A generic capacitive coupling connector circuit.

PCB, bonding wires, bonding pads and ESD structure of thechip which amounts to 2 pF which is about two orders ofmagnitude higher than on-chip node capacitance. Thus thewireless connector must handle smaller input signals compared to chip to chip capacitive coupling interfaces [3], [4].
To cope with the small received signal the wireless connector previously reported [1] sacrificed density of the capacitive pads and used 250 μm × 250 μm to get a large enoughCC .
2.

Design Considerations for Wireless Connectors

High density, high reliability, ease of manufacturing should
be some of the key points in making a connector. To meetthose goals, two major design considerations were made between mechanical connector and wireless connectors, andinductive coupling and capacitive coupling.
2.1 Mechanical Connectors vs. Wireless Connectors
To attain a stable connection, mechanical connectors must
scrape oﬀ residue and oxides on the surface of the connec-

c 2011 The Institute of Electronics, Information and Communication Engineers
Copyright IKEUCHI et al.: 1 GB/S, 50 μM × 50 μM PADS ON BOARD WIRELESS CONNECTOR

993
Table 1

Mechanical connectors and wireless connectors.

tor pins, and apply close to 20 gf of pressure to maintainlow resistance and stability. They are facing many problems
for applying this pressure. The complex spring mechanism
implemented in each pin for low profile connectors reduces
the number of times the connector can be detached to as few
as 5 times. To reduce the force needed to attach/detach aconnector with many pins, Zero Insertion Force (ZIF) connectors which hold and release the connector pins with alever were developed, which however has large feature sizes
so cannot be used in area critical applications.
Wireless connectors on the other hand, do not needpressure to reduce resistance nor do they need scraping
mechanisms since they can communicate through the natural oxides or residue, thus simplifying the structure of theconnector. They could reduce footprint as well as faulty
connections. The capacitive coupling technique used here
will also be useful in implementing connectors have large
number of pins. In a case where 10,000 pins are necessaryand 20 gf of pressure is needed for a stable mechanical connection, 200 kgf is needed to press the connector, while inthe case of wireless connectors, there is no need to put pressure on the pins.
Table 1 compares some of the strengths and weaknesses of mechanical and wireless connectors.
2.2 Inductive Connectors vs. Capacitive Connectors
For non-contacting chip to chip communication, there are
two main approaches, using capacitive coupling and using inductive coupling. When implementing connectors on
PCBs, the inductor or capacitor must be drawn on the PCB.
Common technology for PCBs is 125 μm line and space,
so using inductors drawn on PCBs will require more area
per pin compared to capacitively coupled connectors. Wireless connectors using inductors have been published which
utilize inductors drawn on-chip, presumably because of thesmaller design rules and lower parasitic inductance and capacitance. This approach requires careful alignment of the
TX chip and RX chip so that they are on top of each other.
This will require new packaging technologies for aligning
the chip and the board with very high precision. On theother hand, if the connectors are implemented using the PCB
boards, traditional wire bonding, BGA, or packaging can beused making it easier to use. Therefore, capacitively cou-

pled technology using the pads drawn on PCBs was chosenover inductively coupled communication for wireless connectors.
The wireless connector demonstrated here, and previously reported capacitively coupled chip to chip communication circuits share similar topologies but are completely
diﬀerent in that for the connector, the parasitic capacitanceis very large (500 fF∼1 pF) and diﬀer between pin to pin because of parasitic capacitance on PCB boards which mayvary according to the pattern on the PCB, and I/O diodes on
the receiver chip which are excluded in chip to chip communication.
3.

Contact Allowing Wireless Connector

As shown in the previous section, the input swing that comesthrough the capacitive pads is VDD CC /(CPR +CC ). To reduce
the size of capacitive pads while keeping the same input
swing, you would need to either increase VDD , reduce CPR ,or keep the CC constant. Since VDD is limited by the process
and/or power dissipation of TX, it is diﬃcult to change. The
parasitic capacitance CPR strongly correlates to the lengthof the wires from the capacitive pads to the input of the
RX chip, so reducing CPR will reduce the flexibility of thedesign of the wireless connector. It is therefore needed tokeep the coupling capacitance CC constant while reducing
the pad size. Since CC can be expressed as CC = ε0 εS/d
where ε is the dielectric constant of the insulator, S is thearea of the pads, and d is the distance between the two pads,
to keep CC constant when S becomes smaller, d must be
reduced. Conventionally, d is determined by the thicknessof the insulating overcoat of the pads, which is diﬃcult tocontrol precisely and is more than 40 μm. This paper proposes to totally remove the insulating overcoat to reduce dto eventually zero. Then, the pad metal, normally Au or Cu(Au in this paper), can be in a fully contacting mode. Theremay be cases, however, that thin insulating layers exist between two pads made by oil, air-gap, or natural oxide. Thus,
two cases have to be considered: a contacting case and a
non-contacting case. Since there is a non-contacting case,the transceiver should be based on C-coupling interface circuit. In the conventional receiver, RXIN is precharged to
1/2 VDD this causes a problem when the pads get contacted.
The transmitter tries to output VSS or VDD which contends
with the 1/2 VDD precharger at the RX side resulting in theincrease of DC power. This problem is addressed by the
proposed track and charge scheme. This track and charge
scheme has two major features. The first is that it allows
the TX outputs and RX inputs to be short circuited without having leakage issues, and the second is that since theprecharge voltages are VDD and VSS instead of the normal
1/2 VDD it precharges faster, increasing data rate, and also
eliminates the need for a 1/2 VDD generator which dissipates
DC power.
The digitally tunable comparator proposed here is acurrent latch comparator with digital tunability. This tunability is fully used so that no analog DC reference voltage

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Fig. 3

Receiver circuit schematic of contact allowing wireless connector.

Fig. 4

Detailed timing charts of wireless connector.

will be needed in detecting either a high signal or a low signal, thus making this circuit completely DC free, which will
reduce the power dissipation at lower bit rates, and when thechannel is idle or is working at low data rates.
The overall circuit diagram of the receiver circuit of
the proposed wireless connector is shown in Fig. 3 and theoperation timing chart is shown in Fig. 4. The prominentcircuit elements are explained in the following sections.

4.

Track and Charge Scheme Receiver

Figure 5 describes the concept of the proposed ‘track-andcharge’ scheme to allow the contacting case without increasing DC power. Tracking the incoming data, RXIN is charged
to either VSS or VDD . By selectively charging RXIN in accordance with the TXOUT level, the contention between RX
and TX is removed eliminating the DC current path which
existed in the conventional transceiver. To implement the

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Fig. 6 Proposed digitally controlled comparator with VDD as thereference voltage.

Fig. 5 Conceptual drawing of proposed contact allowable track andcharge scheme.

scheme, two comparators are connected to RXIN . One comparator, COMPH , has a logic threshold of VTH which is close
to VDD , to detect ‘0’ and the other comparator, COMPL has
a threshold of VTL which is close to VSS , to detect ‘1’. If
the previous data is ‘1’, RXIN is charged to VDD and the ‘0’
detecting comparator, COMPH , is enabled. The circuit diagram of the overall receiver is shown in Fig. 3 together with
an operation timing chart in Fig. 4.
Although VTH and VTL are set somewhere in between
the VSS and VDD , oﬀset-adjustable comparators are used toeliminate the DC power in generating the intermediate voltages. Since there is no DC path, the power is proportional
to data rate. The design is based on synchronous clocking.
The clock itself is sent using the conventional RX with acapacitor just in front of the RX. Thus, for the clock signaltransmission, there is a half VDD generator but since there is
only one channel, the power overhead for the clock itself isminimal compared with the power consumption of multiple
data channels.
In previous capacitive coupling receivers, the input of
the receiver is precharged to 1/2 VDD . At this voltage, thesource voltage of the charger becomes closer to the gate
voltage and the gate overdrive becomes lower. This ‘track
and charge’ scheme, however precharges RXIN to VDD or
VSS so the gate overdrive is VDD which reduces the time toprecharge the input of the receiver. This increases the data
rate.
5.

Digitally Tunable Comparator

The comparator circuit used here is shown in Fig. 6. The
pull-down transistors M1-3 are in the saturation region
where the velocity saturation limits the transconductance tothe following.
gm = −VSAT WCOX

(1)

In a case where M2L is VDD , the W of the left side
will be WM1 +WM2 +WM3 and the W on the right side will
be WM1 . Replacing W=WM1 and WTUNE =WM2 +WM3 , thefollowing can be obtained as the tipping point of this comparator.

(VIN − VT H )W = (VREF − VT H )(W + WT UNE )(2)(W + WT UNE )WT UNE
VREF −
VT H
(3)
VIN =
W
W
Since the reference voltage is VDD and the threshold voltageof the nMOS transistors are constants, the tipping point is
controlled completely by the WTUNE which can be tuned by
the on and oﬀ of M2L.
6.

Charger Controller

When the comparators are precharged, the voltage of OUT
and OUTB will be both high for the nMOS input comparator
and low for the pMOS comparator. When one of the comparators is enabled and the comparator compares the input tothe reference voltage, either the OUT or OUTB will change,
so by watching the four outputs, the data can be guessed
and the input can be precharged accordingly. This scheme
reduces the delay to precharge compared to the conventional
circuit where the output of the SR latch is used to trigger theprecharge.
The actual circuit which can be seen in Fig. 3 is composed of a controller for the pMOS which precharges theline RXIN to VDD and the nMOS which precharges RXIN tolow. The controller for the pMOS works as follows. Whenthe comparator clock is low, CRGP is charged to VDD . Ifeither the LOUT or HOUTB changes, CRGP becomes low andthe pMOS is turned on. This scheme will reduce the need offinely tuning the precharge clock and data delay inside thecircuit.
Since LOUT and HOUTB are charged only when theprecharge clock is on, it is important that the outputs fromthe comparator must not dip when they are comparing. If
the voltage dips, the precharge will malfunction and boththe charger to VDD and the charger to VSS will turn on.
7.

Comparator Controller

The comparator controller which is shown in Fig. 3, controls which comparator is enabled according to the previous
data. This is mainly done by feeding the outputs of the RS
latch to the tail of the comparator. When input data changes
and the comparators detect the change, the output of the RS
latch will also change, causing the other comparator to be
activated during the same clock. This will cause an unwanted oscillation. To eliminate this mode, the outputs of

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the comparators are watched, and when the comparators detect a change in input data, the comparators are shut down
to prevent the second comparator to be activated.
8.

Measurement Results

Figure 7 shows the test chip micrograph and measurement
setup. The chip is fabricated in 65 nm CMOS technology.
The core area of the RX is 40 μm × 30 μm and TX circuit is
5 μm × 5 μm. Most of the chip area is dedicated to decoupling capacitor for test output buﬀers. Two flexible PCBs
are set and aligned so that the coupling pads of the transmitter and receiver overlap. Figure 8 shows measured waveforms of the transceiver. VDD is 1.2 V and 1 Gb/s data rateis achieved. The pad size is 50 μm × 50 μm with a misalignment approximately 25 μm. The wire length on the PCB
is 10 mm. The RXOUT drives the oscilloscope with pMOS
open drain configuration and thus the output voltage is 0.5 V.
Figure 9 shows power consumption dependence ondata rate along with the power consumption of conventional work using capacitively coupled channels with similar length and parasitic capacitance [7]. For the proposed
circuit, power scales to zero as the data rate approaches zero.
At 15 Mb/s there is a 20X improvement in power eﬃciency.
This is important since wide data rate range should be covered in connector applications. Since the VDD of TX andRX are connected during the precharge phase in the contact mode, the power dissipation of TX and RX could not
be separated in this measurement setup. Note, however thatthe sum of the TX and RX in contacting mode and non contacting mode are the same. In the contact mode, the TX
charges the parasitic capacitance of TX, and RX while in
the non-contact mode, the TX charges the parasitic capacitance of TX and RX charges the parasitic capacitance ofRX through precharge. In the non-contacting mode, thetwo pads are separated with air. The contacting and noncontacting modes were not deliberately made. Figure 10
shows the timing margin of the clock against the data. The
target BER (Bit Error Rate) of 10−12 is achieved throughout

Fig. 9 Power dissipation of TX and RX circuits when contacting and notcontacting.

Fig. 7 Measurement setup with detailed views of the coupling pads, andthe chip micrograph.

Fig. 8

Measured waveforms of input and output at 1 Gb/s.

Fig. 10 Measured BER at 800 Mb/s showing a 750 ps timing margin
between CLKP and CLKD , and stable communication.

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a 750 ps timing window, showing that the proposed receivercircuit has a short precharge time and can communicate stably. The 10−12 is the minimum BER measureable with the
bit error tester used in this work.
9.

Discussions

The HDMI type D connector which has one of the smallest
pins in mechanical connectors, has 400 μm pitch pins andthe pins have a displacement of less than ±50 μm. Presuming that wireless connectors use a similar mechanical structure, the wireless connector in this work can achieve 200 μm
pitch pins using 150 μm pads on one side and 50 μm pads on
the other side. The smaller pad size and the possibility ofplacing the pins in a 2D manner increase the number of pinsthat can be implemented using the same structure.
10.

for wafer-level and die-level assembly,” IEEE J. Solid-State Circuits,
vol.42, no.10, pp.2270–2282, Jan. 2007.
[4] L. Luo, J.M. Wilson, S.E. Mick, J. Xu, L. Zhang, and P.D. Franzon,“3 Gb/s AC coupled chip-to-chip communication using a low swing
pulse receiver,” IEEE J. Solid-State Circuits, vol.41, no.1, pp.287–
296, Jan. 2006.
[5] S. Kawai, H. Ishikuro, and T. Kuroda, “A 2.5 Gb/s/ch inductivecoupling transceiver for non-contact memory card,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. of Tech. Papers,
pp.264–265, Feb. 2010.
[6] T.B. Cho and P.R Gray, “A 10b 20 Msample/s, 35 mW pipeline A/D
converter,” IEEE J. Solid-State Circuits, vol.30, no.3, pp.166–172,
March 1995.
[7] M. Daito, Y. Nakata, S. Sasaki, H. Gomyo, H. Kusamitsu, Y. Komoto,K. Iizuka, K. Ikeuchi, G. Kim, M. Takamiya, and T. Sakurai, “Capacitively coupled non-contact probing circuits for membrane-based
wafer-level simultaneous testing,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. of Tech. Papers, pp.144–145, Feb.
2010.

Conclusion

A capacitive coupling wireless connector circuit is implemented with 25X reduction of the pad area compared toprevious works, by allowing contacting and non-contacting
modes. The proposed track and charge scheme allows bothcontacting and non-contacting communication through PCB
capacitive pads. By making the precharge level of the inputof the receiver circuit VDD or VSS , instead of 1/2VDD , thetime necessary to precharge is reduced. The proposed digitally tunable comparator along with the track and charge
scheme eliminate the need of 1/2VDD or other analog voltages thereby reducing the power to under 1/20 of previous
work at low frequencies. A test chip successfully transmitted and received 1 Gb/s, 27 − 1PRBS signal at 1 mW with
50 μm × 50 μm pads, while increasing design freedom of thewireless connectors at the same time.
Acknowledgments
This work is supported by a NEDO (New Energy and Industrial Technology Development Organization) entrustment
program. Support from Advantest, Sharp, Panasonic, andYamaichi Electronics is also acknowledged. Design environment was supported by VLSI Design and Education Center (VDEC), the University of Tokyo. Fruitful discussions
and support from the members of the Chip Test Working
Group of ASET are appreciated.
References[1] K. Ikeuchi, K. Inagaki, H. Kusamitsu, T. Ito, M. Takamiya, and T.
Sakurai, “500 Mbps, 670 μW/pin capacitively coupled receiver withself reset scheme for wireless connectors,” IEEE Asian Solid-State
Circuits Conference (A-SSCC) Dig. of Tech. Papers, pp.93–96, Nov.
2008.
[2] N. Miura, H. Ishikuro, K. Niitsu, T. Sakurai, and T. Kuroda, “A
0.14 pJ/b inductive-coupling transceiver with digitally-controlled precise pulse shaping,” IEEE J. Solid-State Circuits, vol.43, no.1,
pp.285–291, Jan. 2008.
[3] A. Fazzi, L. Magagni, M. Mirandola, B. Charlet, L. Di Cioccio, E.
Jung, R. Canegallo, and R. Guerrieri, “3-D capacitive interconnection

Katsuyuki Ikeuchi
received the B.S., and
M.S., degrees in electronics engineering fromthe University of Tokyo, Tokyo, Japan, in 2007,
and 2009, respectively. He is currently pursuinga Ph.D. degree in the University of Tokyo, also
for electronics engineering. His research interests include low-voltage low-power circuits, andproximity communication.

Hideki Kusamitsu
is a Chief Researcher
of Association of Super-Advanced Electronics
Technologies (ASET). He is responsible forelectrical design, evaluation, and electrical simulation of high speed connector. Also, he has
been researched wireless interconnect technology on ASET. He has a BSEE from the Matsue
Technical Collage, Japan.

Mutsuo Daito
received the B.S. and M.S.
degrees in mechanical engineering from Kyoto
University, Kyoto, Japan, in 2000 and 2002, respectively. In 2002, he joined Sharp Corporation, Nara, Japan, where he developed mixedsignal LSIs. In 2008, he joined Associationof Super-Advanced Electronics Technologies,
Yokohama, Japan, where he has been working
on research and development of test systems.

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Gil-Su Kim
received the B.S. degree in electrical engineering from Korea University, Seoul,
Korea, in 2002, and the Ph.D. degree in electronics engineering from Korea University in2008. In 2008, he joined the University of Tokyo, Japan, as a postdoctoral researcher. In
2010, he joined the Samsung Electronics Corporation, Korea. His research interests include thecircuit design of wired and wireless high-speed
I/O interfaces. Dr. Kim received the HumanTech Thesis Contest Bronze Award from Samsung Electronics Corporation (2006), and the Semiconductor Engineering
Contest Award from the Korean Intellectual Property Oﬃce (2006), IEEE
Seoul Section Student Paper Contest Silver Award (2007).

Makoto Takamiya
received the B.S.,
M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Japan, in
1995, 1997, and 2000, respectively. In 2000, hejoined NEC Corporation, Japan, where he wasengaged in the circuit design of high speed digital LSIs. In 2005, he joined the University ofTokyo, Japan, where he is an associate professor of VLSI Design and Education Center. His
research interests include the circuit design ofthe low-power RF circuits, the ultra low-voltage
digital circuits, and the large area electronics with organic transistors. He
is a member of the technical program committee for IEEE Symposium on
VLSI Circuits and IEEE Custom Integrated Circuits Conference (CICC).

Takayasu Sakurai
received the Ph.D. degree in EE from the University of Tokyo in 1981.
In 1981 he joined Toshiba Corporation, where
he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has
worked extensively on interconnect delay andcapacitance modeling known as Sakurai modeland alpha power-law MOS model. From 1988
through 1990, he was a visiting researcher at
the University of California Berkeley, where heconducted research in the field of VLSI CAD.
From 1996, he has been a professor at the University of Tokyo, working
on low-power high-speed VLSI, memory design, interconnects, ubiquitouselectronics, organic IC’s and large-area electronics. He has published morethan 400 technical publications including 100 invited presentations and several books and filed more than 200 patents. He will be an executive committee chair for VLSI Symposia and a steering committee chair for IEEE
A-SSCC from 2010. He served as a conference chair for the Symp. on
VLSI Circuits, and ICICDT, a vice chair for ASPDAC, a TPC chair for the
A-SSCC, and VLSI symp., an executive committee member for ISLPEDand a program committee member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED, and other international conferences. He is arecipient of 2010 IEEE Donald O. Pederson Award in Solid-State Circuits,
2010 IEEE Paul Rappaport award, 2010 IEICE Electronics Society award,
2009 achievement award of IEICE, 2005 IEEE ICICDT award, 2004 IEEE
Takuo Sugano award and 2005 P&I patent of the year award and four product awards. He gave keynote speech at more than 50 conferences including
ISSCC, ESSCIRC and ISLPED. He was an elected AdCom member for
the IEEE Solid-State Circuits Society and an IEEE CAS and SSCS distinguished lecturer. He is a STARC Fellow and IEEE Fellow.