IEEJ Journal of Industry Applications
Vol.9 No.3 pp.271–281
DOI: 10.1541/ieejjia.9.271

Paper

Theoretical and Experimental Analyses of Dynamic Performance ofThree-Level Buck Converters in Discontinuous Conduction Modefor Standby Mode Power Supply
Yoshitaka Yamauchi∗a)
Takayasu Sakurai∗

Non-member,
Non-member,

Toru Sai∗
Makoto Takamiya∗

MemberMember(Manuscript received July 18, 2019, revised Oct. 4, 2019)

A three-level buck converter in the discontinuous conduction mode (DCM), where the output power is typically lessthan 1 W and the output current is less than several hundreds of mA, is a key circuit for integrated voltage regulators
to achieve high eﬃciency at a light load in the standby mode operation of microprocessors. In this study, the fundamental circuit characteristics including the conversion ratio and transfer function are analytically derived for the firsttime. The derived transfer function is verified via time-domain small-signal-injection simulation as well as experimental measurements using a prototype of the three-level buck converter in the DCM with oﬀ-the-shelf ICs. Similar toconventional two-level buck converters in the DCM, three-level buck converters have a first-order lag transfer function,
while those in the continuous conduction mode (CCM) have a second-order lag transfer function. A compensator
design for the three-level buck converters in DCM and CCM in low-power application is discussed.
Keywords: three-level buck converter, discontinuous conduction mode, dynamic performance analysis

1.

Introduction

To make the energy-eﬃcient operation of many-core microprocessors possible, fine-grained per-core dynamic voltage scaling is required. As the number of cores increases, therequired number of power supply voltages also increases. Integrated voltage regulators (IVRs) are a means of generating
multiple power supply voltages on a chip, because increasing
the number of oﬀ-chip voltage regulators is not practical (1) (2) .
The key requirements of IVRs are a high- power conversion
eﬃciency (η) and a small form factor.
Since the first proposal (3) , three-level DC–DC converters
have attracted increasing attention in a wide range of output powers with such advantages as reduced voltage rating
for switches, smaller inductor requirement for a given current
ripple, and larger duty ratio for a given step-down ratio (4)–(14) .
In particular, for the low-power integrated circuit (IC) applications of interest in this research (typically, the output
power is less than 1 W, and the output current is less thanseveral hundred milliamperes), one of the largest advantagesof the three-level DC–DC converters is that they can handle ahigher input voltage, even with an advanced scaled complementary metal-oxide-semiconductor (CMOS) process with
reduced voltage ratings. As shown in Fig. 1, a three-levelbuck converter (7)–(14) combining a cascode two-level buck converter (1) (2) and a 1/2 switched capacitor DC–DC converter is a
key circuit for IVRs, because the 3-level buck converter has

Fig. 1. Power stage and output filters of cascade twolevel buck converter, 1/2 switched capacitor DC-DC converter, and three-level buck convertera smaller inductance and faster transient response than theconventional two-level buck converter at fixed ripples (7)–(12) .
A fully integrated three-level buck converter in the continuous conduction mode (CCM) delivering a current of 150 mA
with η of 72% for the active mode operation of microprocessors has been reported (8) . The converter, however, cannot
be applied to the stand-by mode operation of microprocessors, because η is low at a light load (e.g., < 10 mA) owinga) Correspondence to: Yoshitaka Yamauchi. E-mail: yyama@iis.utokyo.ac.jp∗
Institute of Industrial Science, University of Tokyo
4-6-1, Komaba, Meguro-ku, Tokyo 153-8505, Japanc 2020 The Institute of Electrical Engineers of Japan.
271

Theoretical and Experimental Analyses of Dynamic Performance of （Yoshitaka Yamauchi et al.）to the CCM. In IVRs for energy-eﬃcient microprocessors, ahigh η in the standby mode, as well as the active mode, isrequired. To achieve a high η at a light load, discontinuous
conduction mode (DCM) operation is necessary. However,there have been very few publications about three-level buckconverters in the DCM (12) , although a detailed analysis of athree-level buck converter in the CCM was reported (13) (14) . A
previous study (12) does not include an analysis on the fundamental circuit characteristics of a three-level buck converterin the DCM, meaning that it is not yet clarified how to design
controllers.
To solve this problem, fundamental circuit characteristics,
including the conversion ratio and the transfer function, of
three-level buck converters in the DCM are analytically derived for the first time (15) . In this work, more-detailed explanations on the analysis, as well as experimental validations for the analysis, are shown. In addition, a design ofa controller targeting low-power IC applications (typically,
the output is a few watts, and the output current is several
hundred milliamperes) is shown. In Section 2, the circuit operation of three-level buck converters in the DCM is shown.
A detailed derivation of circuit characteristics, including thetransfer function, in the DCM is given in Section 3, and, in
Section 4, a time-domain small-signal-injection simulation is
described that validates the derived results. Also, the experimental validation of the derived transfer function is shown in
Section 5. In Section 6, a practical design of a controller considering the transition between the CCM and the DCM for
low-power IC applications is discussed. Finally, Section 7
concludes this work.
2.

Fig. 2. Five circuit states of three-level buck converters(SA -SE )Circuit Operation of Three-level Buck Converters in Discontinuous Conduction Mode

The three-level buck converter in Fig. 1 includes four
switches (P1 , P2 , N 1 , and N 2 ). As shown in Fig. 2, the threelevel buck converter in the DCM has five states (SA –SE ), instead of the four states (SA –SD ) in the three-level buck converter in the CCM (13) (14) . SE only exists in the DCM, and theinductor current (I L ) is zero in the SE state. Figure 3 shows
operation waveforms of the voltage in the V X node and I L in
the three-level buck converter in the DCM. T S is the durationof one period, and D1 –D6 are duty ratios. D1 , D2 , and D3
are assumed to be equal to D4 , D5 , and D6 , respectively. The
voltage across the flying capacitor (V CFLY ) is assumed to behalf of V IN in the case of a suﬃciently large CFLY . Whenthe conversion ratio M (= V OUT /V IN ) is less than 1/2, thestate transition order is (SA , SB , SE , SC , SB , SE ) as shownin Fig. 3(a). In contrast, when M is more than 1/2, the orderis (SD , SA , SE , SD , SC , SE ) as shown in Fig. 3(b).
3.

(a)

(b)

Fig. 3. Switching patterns of three-level buck converter:(a) M ≤ 0.5 and (b) M ≥ 0.5

VOUT= IL  · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (2)ROUT
When M ≤ 0.5, Eq. (1) is expressed as
0 = (VIN −VCFLY −VOUT )D1 T S +(0−VOUT )D2 T S +0 · D3 T S+ (VCFLY −VOUT )D4 T S +(0−VOUT )D5 T S +0 · D6 T S
D1
VOUT 1⇔= ×, · · · · · · · · · · · · · · · · · · · · · (3)VIN
2 D1 + D2
and Eq. (2) becomes

Analysis of Circuit Characteristics in Threelevel Buck Converters in Discontinuous Conduction Mode

VOUT 1= IPK (D1 + D2 ) × 2
ROUT 2
1
VIN − VOUT
= 2
D1 (D1 + D2 )T S . · · · · · · · · · · · (4)L
By pairing Eqs. (3) and (4), a quadratic equation for M is acquired,

3.1 Analysis of Conversion Ratio
The conversion
ratio (M) of a three-level buck converter in the DCM is derived by combining the volt-second balance in the inductor
voltage (V L ), and the balance of the load current and the averaged I L .

0 = M2 +VL  = 0 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (1)
272

D1 2
D1 2
M−
,· · · · · · · · · · · · · · · · · · · · · · · · ·(5)K
2K
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Theoretical and Experimental Analyses of Dynamic Performance of （Yoshitaka Yamauchi et al.）

where K is defined as
K=

2L.· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (6)ROUT T S

By solving Eq. (6), taking the positive sign, M is derived as
M=


1+

1



K
1+2
D1 2

 .· · · · · · · · · · · · · · · · · · · · · · · · (7)Fig. 4. Three-level buck converter with definition ofswitch network terminal quantities, V 1 , V 2 , I 1 , and I 2When M ≥ 0.5, Eqs. (3)–(5), and (7) correspond to (8)–(11),respectively.
D1 + (D1 + D2 )VOUT=· · · · · · · · · · · · · · · · · · · · · · · (8)VIN
2 (D1 + D2 )
VOUT
VOUT ROUT T S
D1 (D1 + D2 ) · · · · · · (9)
= 1−
VIN
VIN
L


1
2D1 2
D1 2
0 = M2 −· · · · · · · · · · · · · · (10)
1−
M−
2
K
K
2
M=
· · · · · · · (11)

2
K
4K
K
1−
+
+ 2
1−
2D1 2
2D1 2
D1
Eqs. (7) and (11) are expressed in terms of only the control parameter D1 and circuit parameters, such as L, T S , and
ROUT .
3.2 Analysis of Transfer Function with Averaged
Switch Model
The transfer functions of a three-levelbuck converter in the DCM are derived by using an averaged switch model of switch networks (16) . Figure 4 shows theswitch network in a three-level buck converter in the DCM.
The voltage and current waveforms corresponding to Fig. 4
are illustrated in Fig. 5. The averaged switch network quantities, V 1 , V 2 , I 1 , and I 2 , are calculated as follows.
When M ≤ 0.5,⎧⎪
V1  = VIN
⎪
⎪
⎪
⎪
⎪
V
2  = VOUT
⎪
⎪
⎪
⎪
⎪
⎪
D1 2 T S VIN⎨· · · · · · · · · · (12)− VOUTI1  =
⎪
⎪
⎪
2L
2
⎪
⎪
⎪
⎪
⎪
⎪
D1 2 T S VIN VIN⎪⎪⎪·− VOUT ,⎩I2  =2L
VOUT 2(a)(b)

Fig. 5. Voltage and current waveforms of switch network: (a) M ≤ 0.5 and (b) M ≥ 0.5

Fig. 6. Small-signal AC models of three-level buck converter in DCM obtained by averaged switch model

vOUT
Gd0
=
· · · · · · · · · · · · · · · (14)d vIN =0 1 + s/ω p
Gd0 = j2 (ROUT ||r2 ) · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (15)1
. · · · · · · · · · · · · · · · · · · · · · · · · · · · · (16)ωp =(ROUT ||r2 ) C

Gvd (s) =and when M ≥ 0.5,⎧⎪
V1  = VIN
⎪
⎪
⎪
⎪
⎪
⎪
V
⎪
2  = VOUT
⎪
⎪
⎪
⎪
⎪
⎨
D1 2 T S VOUT (VIN − VOUT ) · · · · · · · · · · · · · · (13)⎪I1  =⎪⎪⎪
L
2 VOUT − VIN
⎪
⎪
⎪
⎪
2
⎪
⎪
D1 T S VIN (VIN − VOUT )⎪⎪⎪.
⎩I2  = L
2 VOUT − VIN

In the equivalent circuit, the inductor is in series with the input current source; thus, the inductor dynamics (particularly
at low frequencies) are assumed to be insignificant (16) . In Table 2, values of M and the control-to-output transfer function of the two-level (17) and three-level buck converters in the
DCM are summarized. For comparison, Table 3 shows valuesof M and the transfer functions of the two-level (17) and threelevel (13) (14) buck converters in the CCM. Similar to conventional two-level buck converters, three-level buck converters
in the DCM have a first-order lag transfer function, whereas
three-level buck converters in the CCM have a second-orderlag transfer function, suggesting that diﬀerent controllers are
required for the DCM and CCM. In the design of a conventional two-level buck converter operating both in the CCM

Figure 6 shows the small-signal equivalent circuit of Fig. 4.
For small signals, the equivalent circuit is obtained by linearization of the expressions for the averaged switch models.
Note that v1 , v2 , i1 , i2 , and d are small perturbations fromV 1 , V 2 , I 1 , I 2 , and D1 , respectively. The parameters(j1 , g1 , r1 , j2 , g2 , and r2 ) in Fig. 6 are summarized in Table 1.
From the small-signal equivalent model, a control-tooutput transfer function Gvd (s) can be found as follows:
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Theoretical and Experimental Analyses of Dynamic Performance of （Yoshitaka Yamauchi et al.）Table 1. Summary of parameters in Fig. 6

Table 2. Values of M and control-to-output transfer function Gvd (s) of two-level and three-level buck converters
in the DCM

Table 3. Values of M and control-to-output transfer
function Gvd (s) of two-level and three-level buck converters in the CCM

Fig. 7. Time-domain small-signal injection simulationfor validation

for heavy loads (e.g., 100 mA) in the active mode and in the
DCM for light loads (e.g., 0.1 mA) in the stand-by mode, thecontroller must be carefully designed for combined operationin the CCM and the DCM. The proposed model makes possible the design of controllers for three-level buck converters
in the DCM.
4.

Validation of Derived Transfer Function by
Time-Domain Small-signal-injection Simulation

The purpose of the research described in this section was tovalidate the theoretical analysis presented in Section 3 withthe time-domain small signal-injection simulation method (18) .
4.1 Time-domain Small-signal-injection Method
The time-domain small signal-injection simulation method (18) can be used to find the transfer function in the case of
non-resonant switching mode power supply circuits such as

Fig. 8. Calculation of the loop gain and phase at a frequency of f
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Theoretical and Experimental Analyses of Dynamic Performance of （Yoshitaka Yamauchi et al.）a three-level buck converter. A non-resonant switching mode
power supply including a three-level buck converter meansthat the switching frequency is much faster than the natural
frequency of the system.
In this method, the whole loop of the three-level buck converter is broken at the output of the error amplifier, as shownin Fig. 7. Then, a small signal voltage source V TEST whose
waveform is sinusoidal with a small magnitude at a given frequency is injected at point P, where the whole loop is broken,
as in Fig. 7. The injected small signal V TEST passes throughthe controller and the power stage and finally reaches theoutput voltage V OUT . Reflecting the control-to-output smallsignal behavior at a certain frequency point, the final small
signal appearing at the output voltage contains a gain in magnitude and a shift in phase with respect to the input small
signal. Here, the magnitude of the input small signal should
be small enough that the average DC operation point at theperiodic steady state does not change, and the output voltage
does not saturate with non-linear behavior.
To obtain the transfer function, first, Fourier analysis is performed on the output voltage as illustrated in Fig. 8. Then, again of the transfer function at an injected frequency point is

Fig. 9. Idealized behavioral models of three-level buck converter (M < 0.5) in Fig. 7 created on MATLAB/Simulink

(a)

(a)

(b)

(b)

Fig. 10. Three-level buck converter in DCM steadystate waveform of (a) output voltage and (b) inductor current under conditions of f SW = 220 kHz, L = 4.7 μH, C =100 μF, ROUT = 10 Ω, V IN = 12 V, D1 = 0.1661, M = 0.20

Fig. 11. Bode plots of derived theoretical model andtime-domain simulation results of (a) gain and (b) phase
under conditions of f SW = 220 kHz, L = 4.7 μH, C =100 μF, ROUT = 10 Ω, V IN = 12 V, D1 = 0.1661, M = 0.20
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Theoretical and Experimental Analyses of Dynamic Performance of （Yoshitaka Yamauchi et al.）obtained by dividing the output signal V 1 by the magnitudeof the injected input small V 2 . Also, a phase of the transfer
function at an injected frequency point is obtained by measuring the output phase θ1 with respect to the input phase θ2 .
Finally, by sweeping the frequency of the injection small signal f and repeating the Fourier analysis and gain/phase calculation at each frequency point, the entire frequency responseof the transfer function is collected (19) .
4.2 Simulation Results
The derived transfer function
was verified by time-domain small-signal-injection simulation, as explained above. Figure 9 shows a behavioral modelof a three-level buck converter in DCM constructed on the
MATLAB/Simulink platform. The behavioral model simulates the inductor current I L and the output voltage V OUT
based on the operation of a three-level buck converter when
V OUT > V IN /2, as shown in Fig. 3(a). The detail of the modelis as follows. The ideal switch A and switch B in the model
play a condition branch role. Switch A controls the voltage applied across the inductor based on the duty ratio D1 .
During the period given by D1 T SW , switch A determines one
state in which a voltage V IN /2–V OUT is applied across the inductor and increases the inductor current. After the periodof D1 T SW , switch A changes to the other state controlled
by switch B. In the other state, initially, a voltage–V OUT is
applied to decrease the current. Once the inductor current
reaches zero when t = (D1 + D2 )T SW , the voltage across theinductor becomes zero. Depending on whether the inductor
current is zero, switch B controls the voltage across the inductor, −VOUT or 0. This process is repeated with a given
switching period T SW . D1 , D2 , and D3 are assumed to beequal to D4 , D5 , and D6 , respectively in Fig. 3(a).
Figure 10 shows waveforms of the output voltage and inductor current in the behavioral simulation under the conditions of f SW = 220 kHz, L = 4.7 μH, C = 100 μF, CFLY =80 μF, ROUT = 10 Ω, V IN = 12 V, and V OUT = 2.4 V. D1 is
0.1661 to achieve a voltage conversion ratio M = V IN /V OUT= 0.20 according to Eq. (7).
Figure 11 shows Bode plots of the derived transfer functionin Table 2 and simulation results under the same conditions.
The Bode plot of the derived transfer function is consistent
with that of the simulated results at least approximately onethird of the switching frequency, which indicates the validityof the derived transfer function of the three-level buck converter in the DCM. The discrepancy in the high-frequency
region near the switching frequency is caused by the dynamics of the inductor in DCM, which is not considered by theaveraged switch model of switch networks (16) discussed in
Section 4. The high-frequency behavior can be accurately
captured by more-complicated analysis (20) , even for the threelevel buck converter in the DCM. However, the analysis is
suﬃcient in terms of compensator designs, because a loop
bandwidth with a compensator becomes much lower than thehigh-frequency pole because of the inductor dynamics,s as is
discussed in Section 6.
5.

Fig. 12. Prototype of three-level buck converter in the
DCM using oﬀ-the-shelf ICs

Fig. 13. Detailed implementation of gate driver, switching pattern generation, and controller in the prototype ofthree-level buck converter in the DCM using oﬀ-the-shelf
ICs

validation, as shown in Fig. 12. Asynchronous rectification
was employed using two diodes in the low side for simplicity while a control method maintaining the DCM operation with all metal-oxide-semiconductor field-eﬀect transistors (MOSFETs) was utilized (21) . Also, in this prototype, avoltage-mode controller with a type-II compensator was employed for stable voltage control. Logic circuits (22) , illustrated
in Fig. 13, were used to generate gate signal patterns for thethree-level buck converter with conventional buck converter
controller IC. The circuit in Fig. 13 also employed a cascaded bootstrap scheme (23) in the three-level buck converter.
Because the top-two MOSFETs were floating switches, thebootstrap capacitors were needed for their gate drivers. Bootstrap diode DQ1 , DQ2, and bootstrap capacitor CQ1 were used
for charging a voltage across CQ2 . Also, bootstrap diode DQ3
and bootstrap capacitor CQ2 charged the voltage across CQ3
so that the bootstrap circuit worked as a whole.
Figure 14 shows the measured waveforms of the output
voltage and inductor current in the prototype three-level buckExperimental Validation of Derived Transfer
Function

5.1 Prototype of Three-level Buck Converter in DCM

A three-level buck converter in DCM was designed
combining with oﬀ-the-shelf discrete ICs for experimental
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Theoretical and Experimental Analyses of Dynamic Performance of （Yoshitaka Yamauchi et al.）converter under the conditions of f SW = 220 kHz, L = 4.7 μH,
C = 100 μF, CFLY = 80 μF, ROUT = 10 Ω, V IN = 12 V, andV OUT = 2.4 V. The inductor current IL was in DCM, and theV B node voltage swung between VIN /2 (= 6 V) and 0. These
waveforms suggest that the prototype circuit operates properly as a three-level buck converter in DCM for experimental
validation of the transfer function. In this measurement, a
500 mΩ shunt resistor was used to sense the inductor current.
5.2 Measurement Setup
The measurement setup forthe experimental validation of the transfer function is shownin Fig. 15. A frequency response analyzer, FRA5097, wasemployed to measure the transfer function experimentally.
The oscillator of the FRA5097 was inserted through the injected resistance RINJ (50 Ω), which was connected between
the output node and the output voltage divider (24) . The injected resistance was much smaller than the voltage dividing
resistances, so it can be assumed that the injected resistor did
not aﬀect the transfer function. Also, in this measurement
setup, the open-loop gain as a whole was measured, meaning

not only the control-to-output characteristic, but also characteristics of the compensator, ramp generator, and voltage
divider were included. Hence, they had to be subtracted laterfrom the open-loop transfer function after characterizing individually the transfer function of the parts, except for thecontrol-to-output.
5.3 Measurement Results
Figures 16 and 17 show
the Bode plots of the open-loop transfer function, the compensator transfer function, and the control-to-output transfer function for the condition described in Section 5.1. Because the open loop transfer function is a product of thecompensator plant transfer function and compensator transfer function in the s-domain, the gain of the control-to-output
transfer function—Figs. 16(c) and 17(c)—was obtained bysubtracting the gain of the compensator transfer function—
Figs. 16(b) and 17(b)—from the gain of the open-loop transfer function—Figs. 16(a) and 17(a). In Figs. 16(c) and 17(c),the experimental results for the gain of the control-to-output
transfer function were −20 dB/dec after the cutoﬀ frequency,
595 Hz for C = 100 μF, V IN = 12 V and 295 Hz for C =200 μF, V IN = 14 V. They agree with the analytically derived
transfer function in Eq. (14) and experimentally verify the derived model for the transfer function of the three-level buckconverter in DCM.
6.

Discussion on Compensator Design for Threelevel Buck Converter Covering both DCM andCCM

Because the control-to-output transfer function of thethree-level buck converter in the DCM was analyzed and validated, here, the compensator design for the three-level buckconverter across DCM and CCM was investigated, particularly for low-power IC application, with simulations. A typical output power was assumed to be less than 1 W, and atypical output current was assumed to be less than several
hundred milliamperes. As was shown, the transfer functionof the three-level buck converters in the DCM has the same
form as the conventional buck converter in the DCM, which
is a first-order lag function. However, the three-level andFig. 14. Steady state waveforms of the prototype threelevel buck converter in the DCM under conditions of f SW
= 220 kHz, L = 4.7 μH, COUT = 100 μF, CFLY = 80 μF,
ROUT = 10 Ω, V IN = 12 V, V OUT = 2.4 V

Fig. 15. Measurement setup for the experimental validation of the transfer function with use of frequency response analyzer FRA5097 at f SW = 220 kHz, L = 4.7 μH, C = 100 μF or 200 μF, CFLY = 80 μF, ROUT = 10 Ω, V IN
= 12 V, V OUT = 2.4 V
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Theoretical and Experimental Analyses of Dynamic Performance of （Yoshitaka Yamauchi et al.）Fig. 16. Measurement results of transfer function in the
prototype of three-level buck converter in DCM (a) loop
gain (b) compensator gain, and (c) control-to-output gain
under conditions of f SW = 220 kHz, L = 4.7 μH, C =100 μF, CFLY = 80 μF, ROUT = 10 Ω, V IN = 12 V, V OUT= 2.4 V

Fig. 17. Measurement results of transfer function in the
prototype of three-level buck converter in DCM (a) loop
gain (b) compensator gain, and (c) control-to-output gain
under conditions of f SW = 220 kHz, L = 4.7 μH, C =200 μF, CFLY = 80 μF, ROUT = 10 Ω, V IN = 14 V, V OUT= 2.4 V

conventional buck converters have a second-order lag function in CCM. This drastic change in dynamics dependingon the CCM or DCM is illustrated in Fig. 18. When I OUT
is less than 300 mA, the three-level buck converter operates
in DCM. In contrast, when I OUT is more than 500 mA, thethree-level buck converter operates in CCM. To cover a wide
range of I OUT , a controller to manage both DCM and CCM
is required. The design methodology of the controller forthe three-level buck converter is the same as that for the conventional buck converter, because both converters have thesame-order lag function.
In high output-power DC–DC converters (e.g. output
power POUT > 2.5–800 W), it is easy to employ digital control
techniques, because the power overhead of the digital controller is negligible.
Many of excellent digital control techniques to cope withthe significant change in the converter dynamics between
CCM and DCM have been proposed including the adaptive tuning method (25) at POUT > 2.5 W, predictive nonlinear observer for state estimation (26) at POUT > 800 W, mode

estimation without current sensor (27) at POUT > 75 W, andcurrent-mode controller with two correction factors (28) at
POUT > 20 W.
In contrast, in the low-output-power DC–DC converters(e.g., output power POUT < 1 W), it is diﬃcult to use thedigital control scheme, because the power overhead of thedigital controller causes the eﬃciency of the DC–DC converter to degrade. For example, one can suppose the caseof the three-level buck converter, in which f SW = 220 kHz,
L = 4.7 μH, CFLY = 80 μF, I OUT = 100 to 500 mA, V IN =12 V, and V OUT = 2.4 V. If the requirement for the analog-todigital converter (ADC) is 12-bit, and 5-MHz sampling, thepower consumption by the ADC is typically approximately
100 mW (ADC12081 (29) , ADS803 (30) ). This degrades the eﬃciency of the DC–DC converter by 30% at low output current(∼100 mA) only because of the ADC power consumption.
Therefore, usually analog voltage-mode control without the
ADC is used for low output-power DC–DC converters (31)–(35) .
When the converter operates only in CCM, it is common touse a type-III compensator (31)–(33) (35) , as shown in Fig. 19. The
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Theoretical and Experimental Analyses of Dynamic Performance of （Yoshitaka Yamauchi et al.）Fig. 18. Duty-to-output transfer function of three-level buck converter under conditions of f SW = 220 kHz, L =4.7 μH, C = 100 μF, I OUT = 100 mA,
200 mA, 300 mA, 500 mA, V IN = 12 V,
V OUT = 2.4 V

Fig. 19. Type-III Compensator with
OTA: Vo (s)/Vi (s) = ω0 (1 + s/ωz1 ) · (1 +s/ωz2 )/[s · (1 + s/ωp1 ) · (1 + s/ωp2 )],ω0 = R4 /(R1 + R4 ) · gm /(C1 + C3 ) =2π · 1.1 kHz, ωp1 = 1/R2 (1/C1 + 1/C3 )= 2π · 66 kHz, ωp2 = 1/{[R4 R1 /(R4 +
R1 ) + R3 ]C2 } = 2π · 530 kHz, ωz1 =1/[(R1 + R3 )C2 ] = 2π · 7.34 kHz, ωz2 =1/(R2C1 ) = 2π · 7.34 kHz

(a)

(b)

Fig. 20. Type-II compensator with OTA:
V o (s)/V i (s) = ω0 (1+s/ωz )/[s · (1+s/ωp )],ωz = 1/(R2 C1 ) = 2π · 198 Hz, ω0 =R4 /(R1 + ssR4 ) · gm /(C1 +C3 ) = 2π ·26.3 Hz, ωp = (C1 +C3 )/(R2 C1 C3 ) = 2π ·1.97 kHz(c)

Fig. 21. Loop gain in three-level buck converter with type-III compensator (a) I OUT = 100 mA (DCM), (b) I OUT= 200 mA (DCM), and (c) I OUT = 500 mA (CCM)

(a)

(b)

(c)

Fig. 22. Loop gain in three-level buck converter with type-II compensator (a) I OUT = 100 mA (DCM), (b) I OUT= 200 mA (DCM), and (c) I OUT = 500 mA (CCM)

Hence, to ensure the stability for both CCM and DCM withthe analog control scheme, it is necessary to use the type-II
compensator (34) (35) shown in Fig. 20, consisting of one integrator, one pole, and one zero at the expense of the control
bandwidth. The design parameters are shown in the figure
caption of Fig. 20. The design scheme for the controller is
as follows (34) (35) : the zero in the type-II compensator is placedat the lowest pole frequency of the control-to-duty transfer
function of the three-level buck converter in the DCM withthe lowest output current, to cancel each other. Still, there is
one degree of freedom in the location of the one pole in thetype-II compensator. This pole can be placed at the higher
frequency, keeping the stability of the control loop in DCM,

design parameters are shown in the figure caption of Fig. 19.
The design scheme for the controller is as follows (31)–(33) (35) :two zeros are placed to cancel the double pole in the CCM
transfer function. One pole is set at several times higher thanunity gain frequency, and the higher-frequency pole is placedat the zero created by ESR of the output capacitor, to widen
the control loop bandwidth, as in Fig. 21(c). However, if thesame controller is used for the DCM operation as well, thecontrol loop suﬀers from less phase margin as the output current decreases as shown in Figs. 21(a) and (b). This is because the pole frequency in the control-to-duty transfer function of the three-level buck converter in the DCM moves tothe lower side as the output current decreases.
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Theoretical and Experimental Analyses of Dynamic Performance of （Yoshitaka Yamauchi et al.）as in Figs. 22(a) and (b). However, if the pole is located at
a higher frequency than the resonant frequency of the output LC filter in the three-level buck converter, the control
loop becomes unstable in CCM operation. Therefore, thepole is placed at 0.2 times the resonant frequency, so thatthe phase margin, even in CCM, can be maintained at 45◦ , asin Fig. 22(c). In this way, the analog voltage-mode controller
for the low-output-power DC–DC converters (POUT < 1 W)
is designed.

( 10 )( 11 )( 12 )( 13 )

7.

Conclusion

The modeling of three-level buck converters in the DCM
was conducted. The transfer function was derived analytically by using an averaged switch model and verified bytime-domain small-signal-injection simulations, as well as
experimental measurements using a prototype of the threelevel buck converter in DCM with oﬀ-the-shelf ICs. It was
revealed that, similar to conventional two-level buck converters in the DCM, three-level buck converters in the DCM havea first-order lag transfer function, while three-level buck converters in CCM have a second-order lag transfer function.
Hence, a controller strategy for a conventional two-level buckconverter in the DCM can be applied for in three-level buckconverter in the DCM. A controller design for three-levelbuck converter operation both in the DCM and the CCM, wasdiscussed in terms of low-power application.
Acknowledgment
This work was partially supported by JST ERATO Grant
Number JPMJER1501, Japan.

( 14 )( 15 )( 16 )( 17 )( 18 )( 19 )( 20 )( 21 )( 22 )

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Theoretical and Experimental Analyses of Dynamic Performance of （Yoshitaka Yamauchi et al.）( 34 )( 35 )

Makoto Takamiya (Member) received the B.S., M.S., and Ph.D. degrees in electronic engineering from the University ofTokyo, Japan, in 1995, 1997, and 2000, respectively.
In 2000, he joined NEC Corporation, Japan, where he
was engaged in the circuit design of high speed digital
LSI’s. He joined University of Tokyo, Japan in 2005,
where he is now a Professor of Institute of Industrial
Science. From 2013 to 2014, he stayed at University of California, Berkeley as a visiting scholar. His
research interests include the integrated power management circuits for wireless powering and energy harvesting for wearable
and IoT applications, and the digital gate driver IC for power electronics.
He is a member of the technical program committee of IEEE International
Solid-State Circuits Conference (ISSCC) and is a Far East Regional Chairin ISSCC 2020. He is a Distinguished Lecturer of IEEE Solid-State Circuits Society. He formerly served on the technical program committees ofIEEE Symposium on VLSI Circuits from 2009 to 2017 and IEEE Custom
Integrated Circuits Conference from 2006 to 2011. He received 2009 and2010 IEEE Paul Rappaport Awards and the best paper award in 2013 IEEE
Wireless Power Transfer Conference.

and Systems II: Express Briefs, Vol.61, No.12, pp.997–1001 (2014)
C. Huang and P.K.T. Mok: “An 84.7% Eﬃciency 100-MHz Package
Bondwire-Based Fully Integrated Buck Converter With Precise DCM Operation and Enhanced Light-Load Eﬃciency”, in IEEE Journal of Solid-State
Circuits, Vol.48, No.11, pp.2595–2607 (2013)“SLVA662 Demystifying Type II and Type III Compensators Using
OpAmp and OTA for DC/DC Converters”, Texas Instruments Co. Ltd.,
http://www.tij.co.jp/jp/lit/an/slva662/slva662.pdf

Yoshitaka Yamauchi (Non-member) received the A.E. in electricalengineering from Toyota National College of Technology, Japan, the B.E. degree in electrical and electronic engineering, and the M.S. degree in electricalengineering and information systems both from the
University of Tokyo, Japan, in 2011, 2014, and 2016,
respectively. He is currently working toward Ph.D.
degree at the same university. In 2017, he joined Integrated Device Technology, San Jose, CA, USA, as
PMIC design engineering intern. In 2019, he joined
IBM T.J. Watson Research Center, New York, NY, USA as a research intern.
His current research interests include power management and analog/mixedsignal IC design. He really hopes to receive the Ph.D. degree by February of2020.
Toru Sai (Member) received the B.E. and M.E. degrees, and theD.Eng. degree in electrical engineering from Chuo
University, Tokyo, Japan, in 1986, 1988, and 2012,
respectively. In 1988, he joined the research anddevelopment center of Yokogawa Electric Company,
Tokyo, Japan. Currently, he is a Project Research Associate with the University of Tokyo. His current research interests include DC-DC converters and digital gate drivers. Dr. Sai is a member of the Instituteof Electronics, Information and Communication Engineers of Japan.

Takayasu Sakurai (Non-member) received the Ph.D. degree in electrical engineering from The University of Tokyo in
1981. In 1981, he joined Toshiba Corporation, where
he designed CMOS DRAM, SRAM, RISC processors, DSPs, and system-on-chip solutions. He focused extensively on interconnect delay and capacitance modeling known as Sakurai model and alphapower-law MOS model. From 1988 to 1990, he wasa Visiting Researcher with the University of California, Berkeley, where he conducted research in thefield of very large-scale integration (VLSI) CAD. Since 1996, he has been a
Professor with The University of Tokyo, focusing on low-power highspeed
VLSI, memory design, interconnects, ubiquitous electronics, organic ICs,and large-area electronics. He has published more than 600 technical publications including 100 invited presentations and several books and filed morethan 200 patents. He is an IEICE Fellow. He was a recipient of the 2010
IEEE Donald O. Pederson Award in Solid-State Circuits, the 2009 and 2010
IEEE Paul Rappaport Award, the 2010 IEICE Electronics Society Award, the2009 IEICE Achievement Award, the 2005 IEEE ICICDT Award, the 2004
IEEE Takuo Sugano Award, and the 2005 P&I Patent of the Year Award, andfour product awards. He is the Executive Committee Chair of the VLSI Symposia and a Steering Committee Chair of the IEEE A-SSCC. He served as a
Conference Chair for the Symposium on VLSI Circuits and ICICDT, a Vice
Chair for ASPDAC, a TPC Chair for the A-SSCC and the VLSI Symposium,
an Executive Committee Member for ISLPED, and a Program Committee
Member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED,
and other international conferences. He delivered keynote speech at morethan 50 conferences, including ISSCC, ESSCIRC, and ISLPED. He was an
Elected AdCom Member of the IEEE Solid-State Circuits Society and an
IEEE CAS and SSCS Distinguished Lecturer. He is also a Domain Research
Supervisor for nano-electronics area with the Japan Science and Technology
Agency.

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