12% Power Reduction by Within-Functional-Block
Fine-Grained Adaptive Dual Supply Voltage Control
in Logic Circuits with 42 Voltage Domains
Atsushi Muramatsu∗ , Tadashi Yasufuku† , Masahiro Nomura∗ , Makoto Takamiya† ,Hirofumi Shinohara∗ and Takayasu Sakurai†∗ Semiconductor Technology Academic Research Center, Japan† University of Tokyo, Japan

Abstract— Within-functional-block fine-grained adaptive dual
supply voltage control (FADVC) is proposed to reduce the powerof CMOS logic circuits. Both process and design variations withina functional block are compensated by the fine-grained supplyvoltage (VDD ) control to minimize power at fixed clock frequency.
In the 40-nm test chips, the layout of a data encryption core isdivided into 6x7 voltage domains. Both high VDD (VDDH ) andlow VDD (VDDL ) are supplied to each power domain and either
VDDH or VDDL is adaptively selected according to the setup error
warning signals generated by canary flip-flops. Compared withthe conventional single VDD operation, the proposed FADVC
reduced the power by 12% at 1-MHz clock in the measurement.

I. I NTRODUCTION

Fig. 1.

Adaptive voltage control (AVC) is an important scheme toreduce the power consumption of a system-on-chip (SoC).
Fig. 1 shows a block diagram of a conventional core-bycore AVS [1]. The power supply voltage (VDD ) is adaptively
controlled according to a timing error warning signal. Conventional AVC schemes, however, do not take into account within-die (WID) process variation. Eireiner et al. [2] proposed
an AVC scheme with a timing error detector such as Razor
flip-flops [3]. Their proposal can detect timing error causedby WID variation. But this method can not control supply
voltage optimally, because this method changes not only
supply voltage of error path but also that of the entire core.
To achieve an extremely low-power operation, reducing
VDD to the threshold voltage is effective. The delay variation
due to random transistor variation, however, increases at low
VDD . For example, Gammie et al. [4] discussed the delayof standard library cells in 28-nm CMOS process. The delay
distribution due to WID variation at 0.5V is 15 times larger
than that at 1.0V.
Previous work [5] proposed a method of AVC which cancels the WID variation. In their proposal, the original logic
block is transformed into low voltage parallel blocks. VDD isindependently controlled in each block. However, the original
circuits need to be divided into parallel blocks at system-level
design. This means the most fine-grained block of AVC is one
function block. When a chip has large random logic blocks thatcannot be separated into small blocks, the logic block must beplaced into one power domain.

978-1-4577-0704-9/11/$26.00 ©2011 IEEEConventional adaptive voltage control (AVC).

Fig. 2. Proposed within-functional-block fine-grained adaptive dual supply
voltage control (FADVC)

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Fig. 4.

Fig. 3.

Circuit schematic of canary F/F.

Circuit schematic of each domain in FADVC.

In order to reduce the power consumption by compensating
the systematic design variation, Nakamura et al. [6] proposed a
within-functional-block fine-grained body-bias control. In theirworks, a chip is divided into 8 body-bias domains and eachbody-bias is optimized to minimize the power consumption ata fixed clock frequency with a simulated-annealing algorithm.
This post-fabrication tuning approach can reduce the leakage
power, but can not reduce the dynamic power. And the bodybias optimization requires more than 20 functional test loops,
thereby increasing the test cost. In order to reduce the power bycompensating the systematic design variation and WID variation without increasing the test cost, within-functional-block
fine-grained adaptive dual supply voltage control (FADVC) is
proposed in this paper.
II. P ROPOSED WITHIN - FUNCTIONAL - BLOCK
FINE - GRAINED ADAPTIVE DUAL SUPPLY VOLTAGE
CONTROL (FADVC)

Fig. 2 shows a block diagram of the proposed FADVC.
In FADVC, the layout of a functional logic block including
clock distribution networks is divided into many square tiles(= domains) by using a standard place-and-route tool. In
our implementation, data encryption circuits using the Date
Encryption Standard (DES) algorithm is embedded as thefunctional logic block. The area of each tile is around 100 ×
100𝜇m2 .
Fig. 3 shows a circuit schematic of each domain in FADVC.
At each domain, either high VDD (VDDH ) or low VDD(VDDL ) is supplied by a VDD selector. Each domain includes
canary flip-flops (F/F’s) [7] in order to generate setup error
warning signals and the warning signals is delivered to theVDD selector of each domain. At first, VDDL is selected inall domains. When a warnings signal is generated, VDD ofthe warning domain is switched from VDDL to VDDH tocorrect the setup error. In contrast, when no warning signal isgenerated, VDD remains VDDL . In this way, within-functionalblock fine-grained dual VDD control is adaptively achievedby utilizing the canary F/F’s and the VDD selectors, thereby
reducing the test cost.

Fig. 5. Layout of fabricated test chip. DES core is divided into 6 × 7 voltage
domains.

Fig. 4 shows a circuit schematic of the canary F/F. Canary
F/F’s are used in top 2k critical paths among 10k paths for
detecting the setup error warning. Warning signal pins of eachcanary F/F are not connected in the placement and the clocktree synthesis stage of the chip design. After the clock tree
synthesis, the warning signal pins of each canary F/F areconnected to the VDD selectors.
Fig. 5 shows a layout of the fabricated test chip in 40nm CMOS process. DES core is divided into 6 × 7 voltage
domains. No level-shifters between the 42 voltage domains areinserted. The layout is designed using a standard automaticallyplace-and-route tool. Each tile (=domain) size is 119×113𝜇m2
and the supply voltage is selected separately from two voltages

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Fig. 6. Microphotograph of test chip in 40-nm CMOS process including aDES core divided into 6 × 7 voltage domains.

Fig. 7.

Measured dependence of minimum supply voltage on 𝑉diﬀ .

by using the VDD selectors.
The VDD selectors are placed at the side of each domain.
The VDD selectors collect warning signals from the canary
F/F’s and VDDH or VDDL is selected at each domain. The
clock signal of the VDD selectors is asynchronous to theDES core circuit. These VDD selectors are placed between
each power domains, and the VDD is fixed to VDDH . The
area overhead by replacing normal F/F’s with canary F/F’s is
8% and the area overhead due to the VDD selectors is 5%.
Therefore, the total area overhead in FADVC is 13%.
Fig. 6 is a microphotograph of a test chip in 40-nm CMOS
process including a DES core divided into 6 × 7 voltage
domains. The core size is 830𝜇m × 830𝜇m and the die sizeis 1.2mm × 1.2mm.
III. M EASUREMENT RESULTS
In this section, the power reduction factor thanks to the
proposed FADVC over the conventional AVS is measured indetail. 𝑉diﬀ (=VDDH − VDDL ) is an important parameter thatdetermines the power reduction in FADVC. The measurement
steps are as follows. At first, the warning signals from all
the canary F/F’s and registers in the VDD selector were reset.
Then the DES core circuits operated. When the timing warning
signal is generated from the canary F/F’s, the warning signals
were stored in each VDD selector and VDDH or VDDL isadaptively selected at each domain according the warning
signals. Finally, the DES core circuits operated again and wedetermined whether the output data of the chip were corrector not.
Figs. 7 and 8 show the measured dependence of minimum
supply voltage and power consumption on 𝑉diﬀ , respectively.
Two dies are measured to investigate the die-to-die variation.
The clock frequency of the DES core was fixed to 1MHz. Both
VDDH and VDDL with the difference of 𝑉diﬀ were reduced
from 700mV to 500mV with a 5-mV step and the functionof the DES core was checked at each VDDH and VDDL . The
minimum functional VDDH and VDDL are shown in Fig. 7. In

Fig. 8.

Measured dependence of power consumption on 𝑉diﬀ .

Figs. 7 and 8, 𝑉diﬀ = 0 means the conventional AVC scheme
shown in Fig. 1. Fig. 7 shows that proposed FADAC scheme
can reduce VDDL compared with the conventional AVC. As𝑉diﬀ is increased in Fig. 8, the power decreases at 𝑉diﬀ <50–60mV while the power increases at 𝑉diﬀ > 50–60mV.
Therefore, the power is minimum at 𝑉diﬀ of 50mV and 60mV
in die1 and die2, respectively. In die1, the power is reducedby 12% at VDDH = 660mV and VDDL = 610mV. In die2, thepower is reduced by 8.1% at VDDH = 655mV and VDDL =595mV. The minimum voltages of die 2 is lower than that ofdie 1, while the power of die 2 is larger than that of die 1. This
will be because the threshold voltage of die2 is lower than thatof die1 and the leakage power of die2 is larger than that of
die1. The power decrease at 𝑉diﬀ < 50–60mV derives fromthe power reduction by reducing VDDL . In contrast, the powerincrease at 𝑉diﬀ > 50–60mV derives from the inter-domain

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power, delay, and area overhead of the level-shifters is large
in the fine-grained voltage control. The inter-domain leakage
issue, however, increases the total power when 𝑉diﬀ is large. Inorder to quantitatively check the inter-domain leakage, Fig. 10shows the SPICE simulated dependence of leakage current
between two domains with 𝑉diﬀ difference. 𝑉diﬀ less than
50mV will be a practical design choice, because the leakage
current rapidly increases as 𝑉diﬀ is increased.
IV. C ONCLUSION

Fig. 9. Measured distributions of VDDH and VDDL among 42 voltage
domains at minimum power conditions of (a) die1 and (b) die2.

FADVC is proposed to reduce the power of CMOS logic
circuits. Both process and design variations within a functional
block are compensated by the fine-grained supply voltage(VDD ) control to minimize power at fixed clock frequency.
In the fabricated test chips in 40-nm CMOS process, layoutof a data encryption core is divided into 6x7 voltage domains.
Both high VDD (VDDH ) and low VDD (VDDL ) are supplied toeach power domain and either VDDH or VDDL is adaptively
selected according to the setup error warning signals generatedby canary flip-flops. The total area overhead in FADVC is13%. Compared with the conventional single VDD operation,
the proposed FADVC reduced the power by 12% at VDDH =660mV, VDDL = 610mV, and 1-MHz clock.
ACKNOWLEDGMENTS
This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy and Industrial
Technology Development Organization (NEDO).
R EFERENCES

Fig. 10. Simulated dependence of leakage current between two domains
with 𝑉diﬀ difference.

leakage increase. The inter-domain leakage issue is discussed
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Fig. 9 shows measured distributions of VDDH and VDDL
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17 VDDH domains of die1. The 10 common domains will
derive from the systematic design variation and the 7 noncommon domains will derive from die-to-die and WID process
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Finally, the inter-domain leakage issue in FADVC is discussed. In the implementation of FADVC, no level-shifters
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