The 33rd International Symposium on
Power Semiconductor Devices and ICs (ISPSD)

May 30 - June 3, 2021, Nagoya Full Virtual Conference

3-2

5 V, 300 MSa/s, 6-bit Digital Gate Driver IC for
GaN Achieving 69 % Reduction of Switching Lossand 60 % Reduction of Current OvershootRyunosuke Katada1, Katsuhiro Hata1, Yoshitaka Yamauchi1, Ting-Wei Wang1, 2, Ryuzo Morikawa1, Cheng-Hsuan Wu1,
Toru Sai1,Po-Hung Chen2, and Makoto Takamiya1
1
The University of Tokyo, Tokyo, Japan
2
National Chiao Tung University, Hsinchu, Taiwan
Email: khata@iis.u-tokyo.ac.jp
Abstract—A digital gate driver (DGD) is an important
technology to reduce both switching loss and voltage and/or
current overshoot. In this paper, a 5 V, 300 MSa/s, 6-bit DGD
IC, where the gate current is varied in 64 levels for each of 16
3.3-ns time intervals, is developed using 180-nm BCD process
for GaN FETs. The parameters for DGD are automatically
optimized using a simulated annealing algorithm throughrepeated switching measurements. In the turn-on of GaN FETs
at 48 V and 8 A, compared with the conventional single-step gate
driving, the proposed gate drive using DGD reduces theswitching loss from 3.9 μJ to 1.2 μJ by 69 % at the same thecurrent overshoot of 3.4 A and reduces the current overshootfrom 8.5 A to 3.4 A by 60 % at the same switching loss of 1.2 μJ,
which clearly shows the advantage of DGD for GaN FETs.

Digital gate driver (DGD) IC

VDD

VDD

VDD (5 V)

Scan-in

Scan_Data
Scan_CLKnPMOS [5:0]

6

nNMOS [5:0]

6

D

GaN FET

Q

GND

1WP
IO

32WP

IO

32IO

1WN

32WN

VDD

IN
Enable
CLK (300 MHz)GNDInternal
clock
generator

D

Int_CLK

32IO

IG

GND

Q

GND

GND

IG = nIO= 0 A to 5 A
n = 0 to 63
IO = 80 mA

Fig. 1. Circuit schematic of 5 V, 300 MSa/s, 6-bit DGD IC for GaN FETs.

Keywords— digital gate driver, GaN, switching loss, overshootNot to scale

IN

I. INTRODUCTIONGaN FETs provide low on-resistance and fast switching,which makes them suitable for realizing high efficiency andsmall volume power converters. GaN FETs, however, are very
difficult to use because of its ultrafast switching operation,
which causes large and high frequency voltage and/or current
ringing, causing device reliability and EMI problems. A
digital gate driver (DGD) [1-8] is an important technology to
reduce both switching loss (ELOSS) and voltage and/or current
overshoot, because ELOSS and the overshoot are in a trade-off
relationship. The conventional DGDs for GaN [6-8], however,
have two problems: (1) the reduction of both ELOSS andovershoot in GaN FETs is not shown, because ELOSS is notmeasured, while the reduction of both ELOSS and overshoot in
IGBT and SiC MOSFETs is shown in [5]; and (2) the optimal
operation of DGD is not achieved, because the parameters for
DGD are manually tuned.

(e.g. 100 kHz)

On

Off

16 pulses

16 pulses

CLK(300 MHz)Int_CLK63

nPMOS [5:0]063nNMOS [5:0]0Fig. 2. Timing chart of 300 MSa/s, 6-bit DGD IC.

1.8 mmInternal clock generator

To solve the problems, in this paper, a 5 V, 300 MSa/s, 6bit DGD IC using 180-nm BCD process is developed. The
parameters for DGD are automatically optimized using asimulated annealing algorithm, and 69 % reduction of ELOSS
and 60 % reduction of the current overshoot (IOVERSHOOT)
compared with the conventional single-step gate driving(CSG) in the turn-on of GaN FETs at 48 V and 8 A are
demonstrated for the first time.

Scan-in

Predrivers

nMOS drivers

Scan-inpMOS drivers

2.4 mm

II. DIGITAL GATE DRIVER IC FOR GAN FETS

Fig. 3. Die photo of DGD IC fabricated with 180-nm BCD process.

Figs. 1 and 2 show a circuit schematic and a timing chartof the developed 5 V, 300 MSa/s, 6-bit DGD IC for GaN FETs,
respectively. The IC is designed using only 5 V transistors andrequires a single power supply of 5 V. The gate current (IG)can be varied in 64 levels for each of 16 3.3-ns time intervals
at turn-on/off of GaN FETs depending on scan-in data. 64-

level IG control from 0 A to 5 A in 80 mA increments isachieved by selectively turning on or off six nMOSFETs orpMOSFETs with binary weighted gate widths (1WN, 2WN,
4WN, 8WN, 16WN, 32WN in case of nMOSFETs) in the output

55

TABLE I.

5V

DGD

IG

48 V

ID

Q1

VDS

Component

Value and design selection

GaN FETs Q1, Q2

100 V, 16 A, EPC2045

Schottky diode D1

100 V, 20 A, STPS20M100S

Shunt resistor RS

0.1 Ω, 2 GHz-bandwidth, SDN-414-10

RS

VGS

nPMOS

Shunt resistor for
ID measurement

0

IOVERSHOOT
40 mm

Q2
Q1

n
0

t

t

VGS

Fig. 4. Circuit schematic of fabricated GaN half bridge.

Gate vector(n1, n2, n3, n4)
n1 n2 n3n4 63

nPMOS

8A

D1

CIRCUIT COMPONENTS AND PARAMETERS OF GAN HALF
BRIDGEVGSGaN FET
Q2

VDS

t
ID

IOVERSHOOT
VDS

t
ID

D1

t

t

DGD IC

3.3 ns㽢4 = 13.3 ns
(a)

(b)

Fig. 7. Definition of gate vectors and waveforms. (a) Proposed gate drive. (b)Conventional single-step gate driving (CSG).

47 mm
Fig. 5. Photo of PCB of GaN half bridge.

pulse test, respectively. Table I shows circuit components andparameters. The power supply voltage of the main circuit is
48 V and the load current is 8 A. EPC2045 (100 V, 16 A
rating) is used for GaN FETs. IG waveform of the low side
GaN FET (Q1) is controlled by the developed DGD IC withthe power supply of 5 V. A 3.3-nF capacitor is added between
the gate and the source of Q1 whose input capacitance is 767
pF, because IG of the developed DGD IC is too large for Q1.
Schottky diode (D1) is added to the high side GaN FET (Q2)in parallel to reduce the loss during the freewheeling, where
the source-to-drain voltage of Q2 and the forward voltage of
D1 are 1.7 V and 0.7 V, respectively. A shunt resistor (0.1 Ω,
2 GHz-bandwidth) is used to measure the drain current (ID)waveform to evaluate ELOSS and IOVERSHOOT. This paper
focuses on the trade-off relationship between ELOSS and
IOVERSHOOT at turn-on, because the clear trade-off relationshipbetween ELOSS and the drain-to-source voltage (VDS)
overshoot at turn-off is not observed.

CLK(300 MHz)

Shunt
resistor

DigitalinputsFig. 6. Measurement setup of GaN half bridge for double pulse test.

stage with 6-bit digital signals. IG control in 3.3-ns intervals is
required, because the turn-on/off transient of GaN FETs is
typically less than 10 ns. The 3.3-ns interval is defined by an
externally supplied 300-MHz clock signal (CLK). The main
reason why the clock frequency could be increased from 25
MHz in DGD for IGBT [5] to 300 MHz is that the high-speed
digital data input is not required and the required digital data
is pre-stored in on-chip memory (flip-flops) by scan-in. Fig. 3
shows a die photo of the developed DGD IC fabricated with
180-nm BCD process. The die size is 1.8 mm by 2.4 mm.

Figs. 7 (a) and (b) show the definition of the gate vectors
and waveforms of the proposed gate drive and CSG,
respectively. nPMOS is the level of IG at turn-on and is an
integer from 0 to 63. In the proposed gate drive, nPMOS isvaried and optimized for each of 4 3.3-ns time intervals withthe gate vector of (n1, n2, n3, n4), and nPMOS is fixed to 63 after
the fifth slot. In CSG, n is varied to emulate the conventional
gate driving with fixed gate resistor and to show the trade-off
relationship between ELOSS and IOVERSHOOT.

III. MEASUREMENT SETUP

IV. MEASURED RESULTS
The measured power consumption of the developed DGD
IC at 300 MHz is 73 mW and the power consumption isFigs. 4 to 6 show a circuit schematic, a photo of PCB, anda measurement setup of the GaN half bridge for the double

56

ELOSS, MAX

5

10
5
0

n=1

6

ELOSS [μJ]

ELOSS [μJ]
IOVERSHOOT [A]

7
6
5
4
3
2
1
0

0

10

30

20

n

50

40

60

−69%

−60%

n = 24 (Fig. 10 (b))

Proposedn = 63(Fig. 10 (c))

0

5

10

IOVERSHOOT [A] IOVERSHOOT, MAX

Fig. 9. Measured ELOSS vs. IOVERSHOOT of proposed gate drive and CSG.
Proposed DGD reduces both ELOSS and IOVERSHOOT.
TABLE II.

COMPARISON TABLE OF DGD ICS

TIA’17 [5]Si IGBT &SiC MOSFET
Process
180 nm BCD
Power supply
15 V, 10 V, 5 V
Output voltage swing
15 V
Target power device

Fig. 9 shows the measured ELOSS vs. IOVERSHOOT of the
proposed gate drive and CSG for comparison. The black line
shows the trade-off curve of CSG in Fig. 8. The red star shows
the proposed gate drive, where the gate vector is automatically
optimized using the simulated annealing algorithm [5] using
an object function (fOBJ) defined in Eq. (1) [5].
f OBJ

Conv. single-stepgate drive (CSG)

20proportional to the clock frequency. The measured maximum
clock frequency for correct operation of the developed DGD
IC is 460 MHz, which means 2.2-ns interval. Fig. 8 shows themeasured n dependence of ELOSS and IOVERSHOOT of CSG. Then dependence is non-monotonic due to the parasitic
inductance of the gate loop and the main circuit loop, whichindicates that the optimization of the parameters for DGD iscomplicated and a manual parameter tuning will not work.

2

3

1

Fig. 8. Measured n dependence of ELOSS and IOVERSHOOT of CSG.

§ ELOSS · § I OVERSHOOT ·¨¨¸¸  ¨¨¸¸© ELOSS,MAX ¹ © I OVERSHOOT,MAX ¹

n = 2 (Fig. 10 (a))

4Levels of IG(1)

where the subscript MAX signifies the maximum of thecorresponding quantity. Small fOBJ means low ELOSS and low
IOVERSHOOT. In the simulated annealing algorithm, the gate
vector (n1, n2, n3, n4) shown in Fig. 7 (a) to minimize fOBJ is
searched through repeated double pulse tests. In this case,
15000 double pulse measurements are done and the best gate
vector achieving the minimum fOBJ is adopted. Compared with
CSG, the proposed gate drive using DGD reduces ELOSS from
3.9 μJ to 1.2 μJ by 69 % at the same IOVERSHOOT of 3.4 A andreduces IOVERSHOOT from 8.5 A to 3.4 A by 60 % at the same
ELOSS of 1.2 μJ, which clearly shows the advantage of DGD
for GaN FETs. The corresponding measured waveforms areshown in Fig. 10.

TPEL’21 [8]This work

GaN FETGaN FETGaN FET

180 nm BCD
5 V, 3.3 V
3.3 V

180 nm HV CMOS 180 nm BCD
5 V, 1.8 V
5V
5V
5V
8 bit (coarse),
6 bit
6 bit (fine)
5 V / 0.12 Ω
5A= 42 A
1.25 ns (coarse),
3.3 ns100 ps (fine)

6 bit

7 bit

5A

3.3 V / 0.5 Ω= 6.6 ATime resolution

40 ns

0.3–3.0 ns

Time steps

No limit

8

104 (= 8㽢13)

16

ELOSS measurement
Parameter
optimization

Yes

No

No

Yes

Automatic

ManualManualAutomaticMax. IG

2

ISPSD’20 [7]V. CONCLUSIONS
5 V, 300 MSa/s, 6-bit DGD IC, where IG is varied in 64
levels from 0 A to 5 A in 80 mA increments for each of 16
3.3-ns time intervals, is developed using 180-nm BCD process
for GaN FETs. Novelty of this paper is ELOSS measurements
and the automatic optimization of the parameters for DGD in
GaN FETs. In the turn-on switching measurements of GaN
FETs at 48 V and 8 A, compared with CSG, the proposed gate
drive using DGD reduces ELOSS from 3.9 μJ to 1.2 μJ by 69 %at the same IOVERSHOOT of 3.4 A and reduces IOVERSHOOT from
8.5 A to 3.4 A by 60 % at the same ELOSS of 1.2 μJ, whichclearly shows the advantage of DGD for GaN FETs.

Fig. 10 shows measured waveforms and the gate vectorsof CSG and the proposed gate drive extracted from Fig. 9. Figs.
10 (a) and (b) show CSG with n = 2 and n = 24, respectively.
Fig. 10 (c) shows the proposed gate drive with the optimized
gate vector (n1, n2, n3, n4) = (0, 31, 40, 1), which successfully
reduces both ELOSS and IOVERSHOOT. Fig. 10 (a) has the same
IOVERSHOOT as Fig. 10 (c) and Fig. 10 (b) has the same ELOSS as
Fig. 10 (c).

ACKNOWLEDGMENT
This work was partially supported by JST ERATO Grant
Number JPMJER1501, Japan.
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Table II shows a comparison table of DGD ICs. Comparedwith the previously published DGD ICs, the proposed DGD
IC with the automatically optimized parameters and the single
power supply of 5 V demonstrated the reduction of both ELOSS
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