IEICE TRANS. ELECTRON., VOL.E94–C, NO.6 JUNE 2011

953

PAPER

Special Section on Analog Circuits and Related SoC Integration Technologies

A Variable Output Voltage Switched-Capacitor DC-DC Converterwith Pulse Density and Width Modulation (PDWM) for 57% Ripple
Reduction at Low Output Voltage
Xin ZHANG†a) , Yu PU† , Nonmembers, Koichi ISHIDA† , Member, Yoshikatsu RYU†† , Nonmember,
Yasuyuki OKUMA†† , Member, Po-Hung CHEN† , Nonmember, Takayasu SAKURAI† , Fellow,
and Makoto TAKAMIYA† , Member

SUMMARY
In this paper, a novel switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) is proposed with
reduced output ripple at variable output voltages. While performing pulse
density modulation (PDM), the proposed PDWM modulates the pulse
width at the same time to reduce the output ripple with high power eﬃciency. The prototype chip was implemented using 65 nm CMOS process.
The switched-capacitor DC-DC converter has 0.2-V to 0.47-V output voltage and delivers 0.25-mA to 10-mA output current from a 1-V input supply with a peak eﬃciency of 87%. Compared with the conventional PDM
scheme, the proposed switched-capacitor DC-DC converter with PDWM
reduces the output ripple by 57% in the low output voltage region with theeﬃciency penalty of 2%.
key words: DC-DC converter, low ripple, low voltage, pulse density modulation, pulse width modulation, switched-capacitor

1.

Introduction

For emerging ultra-low power SoCs which utilize nearthreshold or sub-threshold supply voltages and draw lessthan 10 mA of current [1], [2], a switched-capacitor (SC)
DC-DC converter is a viable choice for its tunable output voltage and the probability of on-chip full integration[3]. However, the previously reported SC DC-DC converters [3]–[8] often overlook the eﬀect of output ripple on the
sub-threshold digital circuits.
With the trend of the power supply voltage (VDD ) scaling, power supply ripple is extremely detrimental to theirdigital building blocks. This is because the delay of logic
circuits is influenced by VDD in an exponential way in the
sub-threshold region. The net result is that a very small
amount of injected ripple can cause a very large delay uncertainty. Figure 1 clearly shows such impact of power supply
ripples (VRipple ) on the frequency of an FO4-per-stage ringoscillator. The central frequency fcenter is obtained at VDD =200 mV. The upper and lower bounds of the frequency, i.e.,
fmax and fmin , are obtained at VDD = 200 mV + VRipple /2 and
VDD = 200 mV − VRipple /2, respectively. Note that in Fig. 1,
fmax and fmin are normalized to fcenter . As seen, an 80 mV
Manuscript received October 13, 2010.
Manuscript revised January 16, 2011.
†
The authors are with The University of Tokyo, Tokyo, 1538505 Japan.
††
The authors are with Semiconductor Technology Academic
Research Center (STARC), Yokohama-shi, 222-0033 Japan.
a) E-mail: zhangxin@iis.u-tokyo.ac.jp
DOI: 10.1587/transele.E94.C.953

Fig. 1 Normalized ring oscillator frequency at diﬀerent power supply
ripples and the target of this work.

ripple can result in a more than 200% delay uncertainty.
In the super-threshold region, the ripple of the DCDC converter and ground-bounce noise (also referred to as
Ldi/dt noise) are two major sources of power supply noiseat digital blocks. As VDD scales to the sub-threshold region,
the transient current of digital blocks also scales rapidly, inthis way mitigating the ground-bounce noise. However, theproblem of the ripple of the DC-DC converter remains andit even goes severer with the decreasing output voltage.
Motivated by the above concerns, it is of great importance to look for solutions which can reduce the output ripple of switched-capacitor DC-DC converter which supplies
variable output voltages to the sub-threshold digital circuits.
Interleaving techniques can also be employed for lower ripples [9], however, this method comes with the cost of increased component count and complicated timing control.
Therefore, exploring a more eﬀective control scheme [10]to reduce output ripple of switched-capacitor DC-DC converter with the variable output voltages for sub-thresholddigital circuits is the focus of this paper.
2.

Proposed PDWM Control Scheme of SC DC-DC
Converter

Conventional SC DC-DC converters employ pulse density

c 2011 The Institute of Electronics, Information and Communication Engineers
Copyright IEICE TRANS. ELECTRON., VOL.E94–C, NO.6 JUNE 2011954

Fig. 2

Schematic of conventional SC DC-DC converter with only PDM.

modulation (PDM) for feedback control [2]–[4], as shownin Fig. 2. The core of the system is a switch matrix which includes the charge-transfer capacitors and the charge-transfer
switches. In this paper, the switching topology of half VIN
generator is employed. A PDM based control scheme isused to regulate the output voltage to the desired value witha suitable clock density. The PDM works as follows: a comparator clocked by the clock (CK) is used to compare VOUT
and VREF . When the output voltage VOUT is above VREF ,the output of comparator, CKpulse is set to 0, which means
switching signals φCK and φCKB are paused. When VOUT
falls below VREF , the comparator triggers a pulse on CKpulse ,which will be transported to φCK and φCKB , thus charges up
the output load capacitor (COUT ). The non-overlap clock
generator is used to eliminate any overlap between φCK andφCKB , thus prevent the power loss while switching. The
clock buﬀers are employed to provide drive ability to thepower switches in the switch matrix.
With the above PDM control scheme, pulse densities
of φCK and φCKB are eﬀectively adjusted. The switches are
switched less frequently as IOUT decreases, thereby reducing
the switching losses and the power consumed by control circuit. With the PDM control scheme, this converter is able toachieve a high power eﬃciency with a wide output current
range.
However, the conventional PDM architecture suﬀers
from the problem of large ripple at low output voltage region. Combining the switch matrix shown in Fig. 2 with alinear regulator may solve the problem of large ripple. However, the additional power MOSFET and opamp required forthe linear regulator will consume large chip area, which is
uneconomic in advanced technologies.
A novel scheme which employs both PDM and pulse
width modulation (PWM) in the feed back control block is
proposed to cope with this kind of problem. In the proposed
scheme [10] shown in Fig. 3, a pulse width control block anda look up table (LUT) are introduced to perform pulse widthmodulation. Only one of the switches connected to VIN isnecessary to be controlled by a modulated pulse signal φPW ,because by controlling the pulse width of this switch, thepower transferred from VIN to the capacitors at every circle

Fig. 3

Schematic of proposed SC DC-DC converter with PDWM.

Fig. 4 Waveforms of conventional and proposed method. (a) conventional PDM with high VOUT , (b) proposed PDWM with high VOUT , (c)conventional PDM with low VOUT , (d) proposed PDWM with low VOUT .

can be precisely controlled. While applying the proposed
PDWM to other switch matrix, any switches connected to
VIN should be selected for φPW , in order to modulate thepower transferred from VIN . The pulse width of φPW is controlled by the pulse width control block. A 4-bit control
signal is read from a LUT to determine the pulse width for
φPW , according to diﬀerent IOUT and VOUT .
The function of proposed PDWM is analyzed in Fig. 4.
Figures 4(a) and (b) show the waveform of conventional
method with diﬀerent VREF ’s, and Figs. 4(c) and (d) show
proposed method. By comparing Figs. 4(a) and (b), it is observed that lower VREF causes bigger ripple, because VOUT
is charged to a VIN /2 at every pulse of CKpulse , because excessive power is transferred by the switch matrix. This implies that the ripple problem goes severer with the decreasing VREF . On the other hand, as shown Figs. 4(c) and (d),proposed PDWM has a much lower ripple due to the PWM
control. Because variable pulse width can be applied todrive φPW , according to diﬀerent VREF ’s, shown in Fig. 3,
the power transferred from VIN is thereby under control.
Therefore, VOUT is now charged to a lower value than in
the conventional scheme shown in Figs. 4(a) and (b). Thus
a significant reduction of output ripple is obtained.
Figure 5 shows the pulse width control circuit of theZHANG et al.: A VARIABLE OUTPUT VOLTAGE SWITCHED-CAPACITOR DC-DC CONVERTER

955

Fig. 54-bit pulse width control circuit.

Fig. 7

Fig. 6

Simulated result of the 4-bit pulse width control circuit.

proposed DC-DC converter. A delay generator is employed
for controllable timing delay with a 4-bit digital input signal.
The input clock signal (IN) is delayed by the delay generator and then reversed by inverters. Then the reversed signal
and original signal are connected to a nand gate. In this way
the output signal (OUT) with controlled pulse width is obtained. Post-layout simulation results show that the pulse
width control circuit generates an output with pulse widthfrom 2.7 ns to 32.8 ns, with 2.1-ns step. Good linearity isobserved, as shown in Fig. 6.
3.

Chip microphotograph and layout.

Fig. 8

Measured eﬃciency vs. output current with proposed PDWM.

Measurement Results and Discussion

The proposed SC DC-DC converter is fabricated with 65 nm
CMOS process, except for the LUT as shown in Fig. 3.
Capacitors C1 , C2 , and COUT shown in Fig. 3 are implemented using oﬀ-chip ceramic capacitors with values of
4.7 nF, 4.7 nF, and 47 nF, respectively. Figure 7 shows thechip micro-photograph and the layout. Multiple bonding
wires are applied for power lines for less parasitic resistance.
The active area of the DC-DC converter is 0.074 mm2 .
Figure 8 shows the measured dependence of the powereﬃciency on the output current at 0.47-V output voltage.
The DC-DC converter delivers 0.25 mA to 10 mA output
current from a 1 V input supply, with an eﬃciency higher
than 82%, and a peak value of 87%.
Figure 9 shows the measured transient waveform of
VOUT of both conventional and proposed DC-DC converters with 0.2-V output voltage and 1-mA output current. The

Fig. 9 Measured transient waveform of VOUT of conventional DC-DC
converter and proposed DC-DC converter.

IEICE TRANS. ELECTRON., VOL.E94–C, NO.6 JUNE 2011

956

Fig. 10

Measured ripple vs. pulse width with various VOUT .
Fig. 11

pulse width of conventional DC-DC converter is 33.33 ns, as
clock frequency is 15 MHz. While in the proposed DC-DC
converter, the pulse width is chosen to be 2.73 ns with thesame clock frequency. As analyzed in Fig. 4, in the conventional DC-DC converter, VOUT is charged much higher thanthe object voltage: 0.2 V, because excessive power is transferred by the switch matrix at every clock cycle. Therefore,
an output ripple of 80 mV is observed, as shown in Fig. 9(a).
In the proposed DC-DC converter, the power transferredfrom VIN by the switch matrix is under control, because
pulse width is controlled by the proposed PDWM. Therefore, VOUT is now charged to a lower value than in the conventional scheme. Thus a low output ripple of 34 mV is
obtained, as shown in Fig. 9(b).
Figure 10 shows the measured output ripple with different pulse width and diﬀerent VOUT . VOUT is controlled
by changing VREF . The conventional PDM with a 15 MHz
clock (equals to 33.3 ns pulse width) is shown in the right of
the graph. As seen, compared with the conventional PDM,
the proposed PDWM greatly suppresses the output ripple,
especially with low output voltages, because the pulse widthof PDM is too wide for transferring required power from theswitch matrix to the output. A maximum reduction of 57%
on output ripple is obtained. When VIN changes, for example, to 1.2 V or 0.8 V, same tendency of ripple with diﬀerent
pulse width will be observed. The conventional PDM will
have the biggest ripple and the ripple will decrease with thedecreasing pulse width.
Figure 11 shows the measured eﬃciency with diﬀerent pulse width. As seen, for each output voltage, the efficiency degrades a little with narrower pulse width. The
reason is when narrow pulse width is applied, little poweris transferred by the switch matrix at each clock cycle, thenthe pulse density will increase for transferring the required
power, in this case more power is consumed by the clock
driver and the switch matrix, therefore the power eﬃciency
decreases. On the other hand, the eﬃciency degrades greatly
with lower output voltage. That is due to the series resistance of output switches, which can be alleviated by sizing
the output switches at diﬀerent output voltage.

Measured eﬃciency vs. pulse width with various VOUT .

When VIN changes, for example, to 1.2 V or 0.8 V,
same tendency of eﬃciency with diﬀerent pulse width will
be observed. When pulse width is decreasing, eﬃciency
decreases gradually. The conventional PDM will have thehighest eﬃciency because no PWM is performed.
By combining Fig. 10 and Fig. 11, the dependence of
output ripple on power eﬃciency with diﬀerent output current is shown in Fig. 12. As observed, the ripple is reduced by narrowing the pulse width, at the cost of slightly
degraded power eﬃciency. That is because narrowing thepulse width also increases the pulse density, as discussed
above, thus increases the power consumption. Therefore, agroup of practical optimum choice on pulse width for diﬀerent IOUT and VOUT was defined by allowing a 2% degradation on power eﬃciency, as shown in Fig. 12.
The measured optimum pulse width for diﬀerent IOUT
and VOUT is shown in Fig. 13. The center of each rectangle
represents a measured point. As observed, 6 diﬀerent optimum pulse widths are selected for diﬀerent IOUT and VOUT .
The optimum pulse width tends to increase with increasing
IOUT and VOUT , because there is a larger need of power tobe transferred by the switch matrix, thus there is a demand
for wider pulse on the switch. The selected pulse width
information is then stored in the LUT. Therefore, users of
the proposed SC DC-DC converter can choose the optimum
pulse width based on Fig. 13 for the required IOUT and VOUT .
For example, with the required IOUT of 5.5 mA and VOUT
of 0.41 V, a pulse width of 9.2 ns is the optimum solution.
For the required IOUT and VOUT which lie on the crossingsof the squares shown in Fig. 13, any value of neighboredsquare could be applied for the optimum solution. In thisway, the SC DC-DC converter will be configured to the optimum pulse width for the optimum output ripple and powereﬃciency.
Further measurement would be carried out to expand
the contour shown in Fig. 13. For example, in the current
contour, the optimum pulse width does not change when
IOUT is larger than 1.5 mA. If more measurement as shown in
Fig. 12 would be carried out for IOUT larger than 10 mA, theZHANG et al.: A VARIABLE OUTPUT VOLTAGE SWITCHED-CAPACITOR DC-DC CONVERTER

957

Fig. 14 Measured ripple of conventional and proposed DC-DC
converters with regarding to IOUT and VOUT , at VIN =1.0 V.

Table 1 Performance summary of the proposed PDWM SC DC-DC
converter.

Fig. 12 Measured ripple vs. power eﬃciency with various VOUT and
IOUT , at VIN =1.0 V.

Fig. 13 Contour of optimum pulse width with regarding to IOUT and
VOUT , at VIN =1.0 V.

range of Y-axis of Fig. 13 will be extend and dependence of
optimum pulse width on IOUT will be observed. In addition,
if more measurement as shown in Fig. 12 would be carriedout for more diﬀerent VOUT ’s, the resolution of X-axis ofFig. 13 will increase.
In the future, the current sensor [11] and the LUT
would be integrated with the proposed PDWM DC-DC converter, and then the optimum pulse width will be automatically selected according to diﬀerent IOUT and VOUT . The
switch matrix shown in Fig. 3 would be improved to include
other topologies like 1/3, 2/3, etc., to further improve thepower eﬃciency of the proposed PDWM DC-DC converterat diﬀerent output voltage.
Figure 14 shows the measured output ripple of conventional and proposed PDWM DC-DC converters with regarding to IOUT and VOUT . Significant reduction of the output
ripple is observed in the whole range of IOUT and VOUT .
Moreover, the output ripple is more eﬀectively reduced in
low output voltage region (to a peak of 57%). Recall thatripple has a larger impact on digital circuits at a lower voltage, the proposed DC-DC converter provides a promising

IEICE TRANS. ELECTRON., VOL.E94–C, NO.6 JUNE 2011958

solution for sub-threshold digital circuits. The performancethe proposed PDWM SC DC-DC converter is summarizedin Table 1.
4.

Conclusion

A switched-capacitor (SC) DC-DC converter with novel
PDWM control scheme for high power eﬃciency and low
output ripple is proposed. Compared with the conventional
PDM, significant reduction of the output ripple is achievedby the proposed SC DC-DC converter with PDWM in thewhole range of IOUT and VOUT . A maximum reduction of
57% on the output ripple is observed with 0.2-V output
voltage. The proposed converter is fabricated using 65 nm
CMOS process with an active area of 0.074 mm2 . A control
scheme using both PDM and PWM is introduced to enablea high eﬃciency with wide output current range, and meanwhile suppress the output ripple with low output voltage.
The proposed SC DC-DC converter works on a 1-V input
supply, and generates 0.2-V to 0.47-V output voltage. It
achieves an eﬃciency above 82% in output current range of
0.25-mA to 10-mA, with a peak value of 87%. With the low
ripple, high eﬃciency and low output voltage, the proposed
PDWM SC DC-DC converter shows a promising solution
for sub-threshold digital circuits.
Acknowledgments
This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy and Industrial Technology Development Organization (NEDO).

“A 32 nm fully integrated reconfigurable switched- capacitor DCDC converter delivering 0.55 W/mm2 at 81% eﬃciency,” IEEE International Solid-State Circuits Conference (ISSCC), pp.210–211,
Feb. 2010.
[8] L. Chang, R. Montoye, B. Ji, A. Weger, K. Stawiasz, and R.
Dennard, “A fully-integrated switched-capacitor 2:1 voltage converter with regulation capability and 90% eﬃciency at 2.3 A/mm2 ,”IEEE Symposium on VLSI Circuits, pp.55–56, June 2010.
[9] D.J. Perreault and J.G. Kassakian, “Distributed interleaving of paralleled power converters,” IEEE Trans. Circuit Syst., vol.44, no.8,
pp.728–734, Aug. 1997.
[10] X. Zhang, Y. Pu, K. Ishida, Y. Ryu, Y. Okuma, P. Chen, K.
Watanabe, T. Sakurai, and M. Takamiya, “A 1-V Input, 0.2-V to
0.47-V output switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) for 57% ripple reduction,” IEEE
Asian Solid-State Circuits Conference (A-SSCC), pp.61–64, Nov.
2010.
[11] M. Du and H. Lee, “A 5-MHz 91% peak-power-eﬃciency buck regulator with auto-selectable peak- and valley-current control,” IEEE
Custom Integrated Circuits Conference (CICC), pp.311–314, Sept.
2010.

Xin Zhangreceived the B.S. degree in electronics engineering from Xi’an Jiaotong University, Xi’an, China in 2003, the Ph.D. degree inmicroelectronics from Peking University, Beijing, China in 2008. Since 2008, he has been a
project researcher with the Institute of Industrial
Science, the University of Tokyo, Japan. His
current research interests include low-voltage
low-power analog circuit and power supply circuit.

References[1] Y.K. Ramadass and A.P. Chandrakasan, “Minimum energy tracking
loop with embedded DC-DC converter enabling ultra-low-voltage
operation down to 250 mV in 65 nm CMOS,” IEEE J. Solid-State
Circuits, vol.43, no.1, pp.256–265, Jan. 2008.
[2] J. Kwong, Y.K. Ramadass, N. Verma, and A.P. Chandrakasan, “A
65 nm Sub-Vt microcontroller with integrated SRAM and switchedcapacitor DC-DC converter,” IEEE J. Solid-State Circuits, vol.44,
no.1, pp.115–126, Jan. 2009.
[3] Y. Ramadass, A. Fayed, B. Haroun, and A. Chandrakasan, “A
0.16 mm2 completely on-chip switched-capacitor DC-DC converter
using digital capacitance modulation for LDO replacement in
45. nm CMOS,” IEEE International Solid-State Circuits Conference(ISSCC), pp.208–209, Feb. 2010.
[4] C. Tseng, S. Chen, T.K. Shia, and P. Huang, “An integrated 1.2 V-to6 V CMOS charge-pump for electret earphone,” IEEE Symposium
on VLSI Circuits, pp.102–103, June 2007.
[5] D. Ma and F. Luo, “Robust multiple-phase switched-capacitor DC–
DC power converter with digital interleaving regulation scheme,”
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.16, no.6,
pp.611–619, June 2008.
[6] L. Su, D. Ma, and A.P. Brokaw, “A monolithic step-down SC
power converter with frequency-programmable subthreshold zdomain DPWM control for ultra-low power microsystems,” European Solid-State Circuits Conference (ESSCIRC), pp.58–61, Sept.
2008.
[7] H. Le, M. Seeman, S. Sanders, V. Sathe, S. Naﬀziger, and E. Alon,

Yu Pu
received the BS degree (cum laude)in Electrical Engineering from Zhejiang University, Hangzhou, China, in 2004. In 2009, heobtained Ph.D. degree in Electrical Engineeringfrom the Eindhoven University of Technology,
the Netherlands, in association with the National
University of Singapore. From November 2006
to February 2009, he was with the Mixed-Signal
Circuit and System Group in NXP Research
Eindhoven. From March 2009 to September
2009 he was a research scientist in the Ultra
Low-Power DSP Processor Group of the IMEC, the Netherlands. He is
now with the Sakurai Lab, University of Tokyo, Japan. His research interests focus on ultra low energy digital circuit design and EDA methodologies.

ZHANG et al.: A VARIABLE OUTPUT VOLTAGE SWITCHED-CAPACITOR DC-DC CONVERTER

959

Koichi Ishidareceived the B.S. degree
in electronics engineering from the University
of Electro-Communications, Tokyo, Japan, in
1998, and received the M.S. and Ph.D. degrees
in electronics engineering from the Universityof Tokyo, Tokyo, Japan, in 2002 and 2005, respectively. He joined Nippon Avionics Co., Ltd.
Yokohama, Japan in 1989, where he developed
high-reliability hybrid microcircuits applied toaerospace programs. Since July 2007, he has
been working at Institute of Industrial Science,
the University of Tokyo as a research associate. His research interests include low-voltage low-power CMOS analog circuits, RF wirelesscommunication circuits, and on-chip power supplies. He is a member ofIEEE.

Yoshikatsu Ryu
graduated from Kobe City
College of Technology in 1992. In 1992, hejoined SHARP Corporation, Nara, Japan. From1992 to 2001 he was involved in the development of semiconductor processing technology,
and from 2001 to 2009 he was engaged in thecircuit design of analog LSIs. Currently, he
is visiting researcher at Extremely Low Power
LSI Laboratory, Institute of Industrial Science,
the University of Tokyo from 2009. His current interests are low-voltage low-power CMOS
charge pump circuits.

Yasuyuki Okuma
received the B.S. and
M.S. degrees in electrical engineering from Tokyo University of Science, Japan in 1997 and
1999, respectively. In 1999, he joined Central Research Laboratory, Hitachi, Ltd., Japan,
where he has engaged in the research and development of low power analog circuit techniquesfor HDD driver and RF-IC. From 2003 through2006, he was a visiting researcher at YRP Ubiquitous Networking Laboratory, doing researchin the field of low-power circuits and systems
for ubiquitous computing. Currently, he is visiting researcher at Extremely
Low Power LSI Laboratory, Institute of Industrial Science, the Universityof Tokyo from 2009. He is interested in power supply circuits for extremely
low power LSI circuits and systems.

Po-Hung Chenreceived the B.S. degree
in electrical engineering from National Sun Yatsen University, Kaohsiung, Taiwan, R.O.C., in2005 and the M.S. degrees in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 2007. He iscurrently working toward the Ph.D. degree inelectronic engineering at the University of Tokyo, Tokyo, Japan. His current research interests focus on millimeter-wave circuits, lowvoltage low-power CMOS analog circuits andlow-voltage CMOS DC/DC converters.

Takayasu Sakurai
received the Ph.D. degree in EE from the University of Tokyo in 1981.
In 1981 he joined Toshiba Corporation, where
he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has
worked extensively on interconnect delay andcapacitance modeling known as Sakurai modeland alpha power-law MOS model. From 1988
through 1990, he was a visiting researcher at
the University of California Berkeley, where heconducted research in the field of VLSI CAD.
From 1996, he has been a professor at the University of Tokyo, working
on low-power high-speed VLSI, memory design, interconnects, ubiquitouselectronics, organic IC’s and large-area electronics. He has published morethan 400 technical publications including 100 invited presentations and several books and filed more than 200 patents. He will be an executive committee chair for VLSI Symposia and a steering committee chair for IEEE
A-SSCC from 2010. He served as a conference chair for the Symp. on
VLSI Circuits, and ICICDT, a vice chair for ASPDAC, a TPC chair for the
A-SSCC, and VLSI symp., an executive committee member for ISLPEDand a program committee member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED, and other international conferences. He is arecipient of 2010 IEEE Donald O. Pederson Award in Solid-State Circuits,
2010 IEEE Paul Rappaport award, 2010 IEICE Electronics Society award,
2009 achievement award of IEICE, 2005 IEEE ICICDT award, 2004 IEEE
Takuo Sugano award and 2005 P&I patent of the year award and four product awards. He gave keynote speech at more than 50 conferences including
ISSCC, ESSCIRC and ISLPED. He was an elected AdCom member for
the IEEE Solid-State Circuits Society and an IEEE CAS and SSCS distinguished lecturer. He is a STARC Fellow and IEEE Fellow.

Makoto Takamiya
received the B.S., M.S.,
and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Japan, in 1995,
1997, and 2000, respectively. In 2000, he joined
NEC Corporation, Japan, where he was engaged
in the circuit design of high speed digital LSIs.
In 2005, he joined University of Tokyo, Japan,
where he is an associate professor of VLSI Design and Education Center. His research interests include the circuit design of the low-power
RF circuits, the ultra low-voltage digital circuits,
and the large area electronics with organic transistors. He is a member of
the technical program committee for IEEE Symposium on VLSI Circuits
and IEEE Custom Integrated Circuits Conference (CICC).