The 2014 International Power Electronics Conference

On-Chip Buck Converter with Spiral Ferrite
Inductor and Reducing IR Drop in
3D Stacked Integration*Hiroshi Fuketa , Yasuhiro Shinozuka, Koichi Ishida, Makoto Takamiya, and Takayasu Sakurai

Institute of Industrial Science
University of Tokyo
Tokyo, Japan*
fuketa@iis.u-tokyo.ac.jp

Abstract- In this paper, two topics about an on-chip
DC-DC buck converter are described. First, the buck

Ferrite film

converter with an inductor on interposer is investigated formobile applications. Simulation results indicate that theefficiency of the buck converter is improved by introducing
a ferrite film to the inductor. Next, a circuit technique toreduce IR drop in 3D stacked integration using the buckconverter is proposed. In this paper, 3D stacked-die system,
which consists of stacked dies and silicon interposer, isFig. 1. Inductor on Interposer with ferrite film.

fabricated and measurement results show that the proposed
technique78%

achieves

decreaseinIR

voltagedrop

compared with the conventional approach.

Inductor

Keywords- 3D stacked integration, Ferrite, Interposer,IR Drop, On-chip DC-DC buck converterI.

Controller

INTRODUCTIONA buck converter is often used as a DC-DC voltage
down converter, since the buck converter provides highconversion efficiency at rather high current output among
different types of DC-DC voltage down converters.
In this paper, the following two topics about the buckconverter for mobile applications and 3D IC's aredescribed. 1) Efficiency improvement of the buckconverter by introducing high permeability material to an
inductor on interposer is investigated [1]. 2) A circuit
technique to reduce IR drop in 3D stacked integration
using the buck converter is presented [2].
II.

ICFig. 2.

on interposer.

Cross-sectional view

(Upperllower sides)

EFFICIENCY INCREASE IN BUCK CONVERTER BY

E

INTRODUCTION OF HIGH PERMEABILITY MATERIAL TO:::1.
oII)
co

INDUCTOR ON INTERPOSER

A buck converter requires an inductor. Since mobile
devices have been currently smaller and thinner,miniaturization of the inductor used for the buckconverter is required. Although it is one of promisingsolutions that inductors are implemented in IC package orinterposer, the inductance and Q factor of such inductors
are smaller, which results in worsening the efficiency ofthe buck converter. Therefore, introduction of highpermeability material to the inductor is expected toimprove the efficiency. In this paper, the efficiency of thebuck converter using inductor on interposer with a ferrite
film is investigated as shown in Fig. 1.

978-1-4799-2705-0/14/$31.00 ©2014 IEEE

Interposer

Circuit schematic of buck converter with inductor

850JlmFig. 3. Layout of spiral ferrite inductor.

Fig. 2 shows a circuit schematic of the buck converter
evaluated in this paper. A controller circuit, buffers, anddrivers of the buck converter are implemented in the IC,
while an inductor is fabricated in the interposer using
metal interconnects of the interposer. The layout of theinductor is illustrated in Fig. 3. In this paper, the2228

The 2014 International Power Electronics Conference

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Dependence of TT. of ferrite inductor and air core

4201TSV = 30mQ/via
VOOL = 1V

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Number of stacked dies (N)Fig. 6. Calculated IR drop in 3D integration. nL is the totalinductor.

number of TSV's per die used for power delivery. Each die
is assumed to consume 1A.

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Recently, 3-dimensional integration based on TSV's(through silicon vias) have been explored extensively forachieving low power and high performance to break thelimit of single-chip 2D integration. The TSV andassociated bump connection structure (TSV link)inherently have parasitic resistance and thus the supply
voltage is exposed to IR drop due to the TSV linkresistance [4,5]. The increase of IR drop is shown in Fig.
6. The IR drop is calculated as a function of the numberof stacked dies (N) and the total number of TSV's per die(nL) used for power delivery. If allowable IR drop is
assumed to be 3% of the nominal power supply voltage(VDDL), it is seen from the figure that hundreds of TSV'sare needed to make the IR drop within the tolerance.
In order to reduce the IR drop due to TSV, we
proposed a Buck Converter on Top die (BCT) scheme [2].
Figs. 7 and 8 show a typical 3D integration with theconventional power supply scheme and the proposed
BCT scheme. In the conventional power supply scheme(Fig. 7), all the current is supplied from a buck converter
which is either implemented on the bottom die or isimplemented as a separate die residing external to the 3D
stacked dies. Since the top die can be far from the power
supply circuit, the IR drop gets large as the current mustgo through many serially-connected TSV's.
In contrast, a buck converter is added on the topmostdie (Die N) in the proposed BCT scheme, and the current
to an upper half of the 3D integration (Die (N/2)+1 DieN) is delivered from the added BCT (Fig. 8). Each buckconverter on the top die and the bottom die stably supply
the specified voltage and the current to the furthest die(Die N/2, Die (N/2)+1) from a buck converter throughless number of TSV's compared with the conventionalcase. Thus, the maximum IR drop gets smaller andimproved.
In order to evaluate the effectiveness of the proposed
BCT scheme, we fabricated 3D stacked-die system,
which consists of stacked dies and silicon interposer. Its:��.
• ..
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+13%
......... 70%.
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60 0Yo60� ·F- ------------ ,\!�!
1] of buck converter with air core inductor

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....

5.7

10'tdferrite) l'tdair)Fig. 5.

....

'50

100

Efficiency increase of buck converter by using

ferrite inductor.

inductance of the inductor is simulated by a 3D
electromagnetic simulator (Agilent EMPro).
According to [3], the efficiency of the buck converter
depends on TL, which is given by

TL =L/RL,

REDUCING IR DROP IN 3D INTEGRATION USINGBUCK CONVERTER ON TOp DIE SCHEME(1)

where Land RL are the inductance and the DC resistanceof the inductor, respectively. As TL increases, theefficiency of the buck converter improves. Therefore, TL
is evaluated to investigate the efficiency improvement ofthe buck converter by using the ferrite inductor in thispaper.
Fig. 4 shows the dependence of TL on the thickness ofthe ferrite film. TL(jerrile) and TL(air) are TL of the ferriteinductor and the air core inductor, respectively. When thethickness of the ferrite film is lO\-lm, TL(jerrile) is 5.7 times
larger than TL(air). Fig. 5 shows the efficiency
improvement of the buck converter by using the inductor
with the ferrite film when the input/output voltage of thebuck converter is l.8/l.0V, the output current is l.OA,
and the switching frequency is 100MHz. By using theinductor with the 10\-lm-thick ferrite film, the efficiencyof buck converter is improved by 13% and 8% when theefficiencies of buck converter with the air core inductor
are 60 and 80%, respectively.

�2229

The 2014 International Power Electronics Conference

TSV's for VDDL�Fig. 7. Conventional power supply scheme.

50llm

Fig. 9.
Fig.

8.

Proposed Buck Converter on Top die (BCT)

Cross sectional view of 3D integrated system. The

upper photo is a global view and the lower photo is ascheme.

magnified view around a TSV.

cross sectional view is shown in Fig. 9. Two face-up dies
are stacked on top of a silicon interposer with a via-lastprocess. The diameter of the TSV is 20flm and theminimum pitch of the TSV's is 50flm. The resistance of aTSV linl( is 29mQ (typical). Although only two dies arestacked physically as shown in Fig. 9, 8-die stack case isemulated by the daisy chain of TSV's in two stacked diesin this paper.
The technology used to implement circuits is 8-metal,
90nm CMOS. The typical operation voltage for logictransistors is 1.2V while I/O transistors accept typically
3.3V. Thus, 3.3V is used for VDDH and 1.2V for VDDL in
the 3D stacked-die system design.
A microphotograph of the fabricated two stacked diesmounted on top of a silicon interposer is shown in Fig. 10.
The silicon interposer is needed to accept 50flm pitch
TSV's, which cannot be realized by a PCB board whose
design rule is loose. Two identical buck converters areimplemented on a die to expect yield improvement in this
3D stacked-die system.
The photo in Fig. 11 shows an assembled 3D stacked­
die device. A chip inductor and two chip capacitors aredirectly mounted on the top die. The blue part in thepicture is a silicon interposer. The chip inductor andcapacitor for a buck converter is 3. 9nH and 1flF,respectively. These values are chosen to optimize thebuck converter design following the design theory
described in [3].
Fig. 12 shows the measured and simulated IR drop in
the fabricated 3D stacked-die system. The simulation

2230

Fig. 10. Two stacked dies using TSV's are mounted on topof a silicon interposer.

results are obtained using SPICE. Although the voltage of
only selected locations can be monitored in themanufactured 3D stacked-die system due to TSVconstraints, the simulation results can be used toextrapolate the measured points since the simulation
results agree very well with the measured results as isseen in Fig. 12. [t is shown that the proposed scheme
achieves 78% decrease in [R voltage drop compared withthe conventional approach. That is, the [R drop is reduced
to less than 1/4 by introducing the BCT scheme.

The 2014 International Power Electronics Conference

0-10:;- -20
E

�c..

0...

-55mV

- 30"C0:::-40

conventional···· •.
....
....
.....
... .
•-50

Measured-Simulated......•..........

-60 L..-----JL...---''--'_--L_---'-_Die 1 Die 2 Die 3 Die 4 Die 5 Die 6 Die 7 Die 8t
BottomLocation of diestTopFig. 12. Measured lR drop and simulated results.
Fig. 11. Photograph of assembled system on a PCB board.
Chip inductor and chip capacitor are mounted directly on

REFERENCES

top of stacked dies at the center of the photo.

[1]IV.

CONCLUSIONSIn this paper, the two topics about the on-chip buckconverter were described. First, we investigated theefficiency improvement of the buck converter byintroducing high permeability material to an inductor oninterposer. The simulation results indicated that theefficiency of the buck converter is improved by 8% byusing the inductor with the lOllm-thick ferrite film whenthe efficiency of the buck converter with the air core
inductor is 80%. Next, we proposed the buck converteron top die (BCT) scheme to reduce IR drop in 3D stacked
integration. 3D stacked-die system, which consists ofstacked dies and silicon interposer, was fabricated andmeasurement results showed that the proposed BCT
scheme achieves 78% decrease in IR voltage dropcompared with the conventional approach.

[2]

[3]

[4]

[5]

ACKNOWLEDGMENT

The authors would like to thank Prof. Toshiro Satofrom Shinshu University, Mr. Tomoharu Fujii, Mr.
Hiroshi Shimizu, and Mr. Kazutaka Kobayashi fromSHINKO Electric Industries Co., Ltd. for valuable
discussions regarding the inductor on interposer with theferrite film.
The authors also would like to acknowledge Dr.
Futoshi Furuta, Dr. Kenichi Osada, and Dr. Kenichi
Takeda from Association of Super-Advanced Electronics
Technologies (ASET) for fabricating 3D stacked ICs.

2231

H. Fuketa, Y. Shinozuka, K. Ishida, M. Takamiya, T. Fujii, H.
Shimizu, K. Kobayashi, T. Sato, and T. Sakurai, "Efficiency
Increase in On-Chip Buck Converter by Introduction of High
Permeability Material to Inductor on Interposer," in Proc.
International Conference on Ferrites (ICF), p. 75,2013.
Y. Shinozuka, H. Fuketa, K. Ishida, F. Furuta, K. Osada, K.
Takeda, M. Takamiya, and T. Sakurai, "Reducing IR Drop in 3D
Integration to Less Than 114 Using Buck Converter on Top Die(BCT) Scheme," in Proc. IEEE International Symposium on
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