IEEE CICC 2023
Digital Gate ICs for Driving and Sensing Power Devices
to Achieve Low-Loss, Low-Noise, and Highly Reliable
Power Electronic Systems
Dibo Zhang, Kohei Horii, Katsuhiro Hata, and Makoto Takamiya
The University of Tokyo, Tokyo, Japan

Abstract—In order to shift the business of power electronics

systems such as power converters using power devices from a sellout type to a subscription type that provides the best service for eachuser, digital gate ICs that drive and sense power devices and areconnected to the network will be a key technology. This paper
presents several examples of the development of digital gate ICs that
integrate a sensor, a controller, and a digital gate driver to digitallycontrol gate current in fine time steps on a single chip.

1 Introduction
Fig. 1 shows a block diagram of a conventional power converter
including a gate driver IC. The gate driver IC is a circuit that switches
power devices by interfacing between a low-voltage controller and ahigh-voltage main circuit. Specifically, the gate driver IC drives thegate terminals of power devices by amplifying the 5-V amplitude
on/off signal from the PWM controller IC to the gate voltage (VGE) of
5 V to 18 V and the gate current (IG) of 1 A to 20 A. Many gate driver
ICs in products detect the over-current and/or over-voltage of IGBTs
and output an alarm signal. Conventional gate driver ICs are too
simple in functionality to enable a shift in the business of powerelectronics systems, such as power converters using power devices,from a sell-off of products to a subscription-based business thatprovides the best service for each user.
In contrast, Fig. 2 shows the proposed subscription-based service
platform, where the key technology is a digital gate IC that drives andsenses power devices and connected to a network. A sensor circuit
integrated in a digital gate IC measures the operating conditions (e.g.,
IC, VCE, and junction temperature) and degradation status (e.g.,
threshold voltage and bond wire lift-off) of power devices and sends
the measured results to the service provider’s cloud over the network.
Service providers use AI to analyze sensor data from many users
and provide the best service (e.g., digital gate driver parameters) for
each user. This paper presents digital gate drivers developed torealize digital gate ICs, including a digital gate driver IC integrating
dIC/dt sensor and automatic timing control for IGBTs, a single-input

dual-output digital gate driver IC for equalizing drain current of twoparallel-connected SiC MOSFETs, and a large current output digital
gate driver using half-bridge DAC IC and two power MOSFETs for
IGBTs.

2 Digital Gate Driver IC Integrating dIC/dt Sensor andAutomatic Timing Control for IGBTs
2-1 Research Motivation
A lot of active gate drivers (AGDs), where the gate driving waveform
is controlled during the turn-on/off transients, have been proposed toreduce both the switching loss and the switching noise of powerdevices. AGDs can be classified into two types, open-loop control [16] and closed-loop control [7-19]. The closed-loop AGDs are required
instead of the open-loop AGDs, because the optimal driving
waveform changes depending on the operating conditions (e.g. load
current and temperature) [20]. Fig. 3 summarizes the design choices
in conventional closed-loop AGDs. To make the closed-loop AGDs
practical, the following three points are required: (1) single-chip
integration instead of PCB implementation for lower cost, (2) realtime control instead of iterative control to reliably handle dynamicchange of operating conditions, and (3) programmable AGDs insteadof fixed-function AGDs that require individual optimization fordifferent product variety of power devices. In the closed-loop AGDs,
however, no previous paper has realized (1) and (2) simultaneously,
and no previous paper on (3) has been published.
To solve the problems, a digital gate driver (DGD) IC with fully
integrated automatic timing control (ATC) function for IGBTs thatrealizes all of (1) to (3) is proposed [21]. The design choices in thiswork are shown in blue in Fig. 3.

2-2 Circuit Design
Figs. 4 and 5 show a circuit schematic and a timing chart of the
proposed DGD IC with ATC, respectively. In the following, turn-on is
discussed, whereas the exact same is true for turn-off. The IC
includes dIC/dt detector for the state change, controller for ATC, anda 6-bit current-source type digital gate driver with variable gate
current (IG) in 64 levels, where IG = nPMOS × 48 mA and nPMOS is an
integer from 0 to 63. At turn-on, an active gate driving is performed
Sensorinput

ControlmethodControl
time

ImplementationdIC
dt

Continuous
time
⚫ VGE

Real-timeIC

State change
⚫ IG
⚫ VGE
⚫ RG

Iterative

PCB

IC,

Power converter
Main circuit

<5V
Sense
On/offController
IC

Alarm

Gate
driver
IC

IG

IC

VCE

VCE = 10 V to 3 kV
IC = 10 A to 1000 A

Fig. 1. Block diagram of conventional power converter including
gate driver IC.

Service providers
Cloud
Big data
AI

Parameters
Sensoroutputs

VGE, dVGE
dt

VGE(e.g.) VGE = 5 V to 18 V
IG = 1 A to 20 A

Network
connection

VCE, dVCE
dt

Fig. 3. Design choices in closed-loop AGDs. This work is shownin blue.
Digital gate driver (DGD) IC with
automatic timing control (ATC)
5V

nPMOS

SIPO 36

Power converter of User 1

PISOs

Main circuit

1WP
IO

15 V
32WP
32IO

Level shifter

Digitalgate IC

Drive

Controller

Sense

Scan In
Scan CLK
IN
5V
VREFH
VREFL

SIPO 36
dIC
dt
detector

6
PISOs

IO
nNMOS

32IO

1WN

32WN

IC
IG

VCE
VGE
Kelvinemitter(E)

15 V

Power converter of User 2

Provide best service for each user

Fig. 2. Proposed subscription-based service platform, where key
technology is digital gate IC.
979-8-3503-9948-6/23/$31.00 ©2023 IEEE

LeE
VeE

Serial-in parallel-out shift register (SIPO)
Parallel-in serial-out shift register (PISO)

Power emitter (e)Fig. 4. Circuit schematic of proposed DGD IC with ATC.

IEEE CICC 2023
in three slots from t1 to t3 with different IG of strong (n1) -weak (n2) strong (n3), and this driving method is defined as stop-and-go gate
drive (SGGD) [22]. n1 to n3 are preset by a digital input (Scan In),
while t1 and t2 are automatically determined by ATC. An importantfeature of this IC is the full integration of t1 and t2 real-time automatic
control functions on a single chip. The real-time control of t1 and t2 isdone by detecting dIC/dt by sensing the voltage (VeE) of the parasitic
inductance (LeE) between Kelvin emitter and power emitter in Fig. 4,
because VeE = − LeE (dIC/dt), where IC is the collector current.
Specifically, as shown in Fig. 5, the end timing of t1 is determined bydetecting the negative VeE at the beginning of IC flow using acomparator with the reference voltage of VREFL, and the end timingof t2 is determined by detecting the positive VeE at the timing
immediately after IC overshoots using a comparator with thereference voltage of VREFH. Fig. 6 shows a die photo of DGD IC
fabricated with 180-nm BCD process.

Automatic timing control in stop-and-go gate drive

On
n1

63

nPMOS

t3

t2

t1

IN

n2

Off

n3

0
63

nNMOS
IG

t6

t5

t4

n4

n5

n6

0

0A
15 V

VGE 0 V

IOVERSHOOT

−15 V

IC

0A

VREFH

VeE 0 V
VREFL
600 V

VCE

Figs. 7 and 8 show a circuit schematic and a measurement setup of
the double pulse test using the developed DGD IC and an IGBT
module (FS100R12N2T4, 1200 V, 100 A), respectively. Figs. 9 (a)and (b) show timing charts of the conventional single-step gate drive(SSGD) and the proposed SGGD for comparison, respectively. In
SSGD, n1 is varied, which emulates a conventional gate driver withvaried gate resistance. In SGGD, (n1, n2, n3) are preset to (27, 2, 27),
and t1 and t2 are automatically determined by ATC. Figs. 10 (a) and(b) show the measured IC and gate-emitter voltage (VGE) waveforms
in SGGD with ATC with varied load current (IL) from 10 A to 80 A,
respectively. Fig. 10 (c) shows the measured t2 vs. IL. It is clearlyobserved that as IL increases, t1 remains constant, while t2 is
automatically increased by ATC. Figs. 11 (a) to (c) show themeasured switching loss (ELOSS) vs. the collector current overshoot(IOVERSHOOT) of the conventional SSGD and the proposed SGGD at IL= 20 A, 50 A, and 80 A, respectively. The black curves show thetrade-off curves of the conventional SSGD with varied n1 from 2 to63. In all cases, the proposed SGGD has lower ELOSS and lower
IOVERSHOOT than the conventional SSGD. In Fig. 11 (c), Point A to
Point C are defined, where Point B is the proposed SGGD, and Point
A and Point C are the conventional SSGD with n1 = 4 and 63,
respectively. IOVERSHOOT of Point A and Point B are almost the same.
At IL = 80 A, compared with the conventional SSGD, the proposed
SGGD reduces ELOSS by 38 % under IOVERSHOOT-aligned condition
and reduces IOVERSHOOT by 18 % under ELOSS-aligned condition. Figs.
12 (a) to (c) show the measured waveforms in Point A, Point B, andPoint C in Fig. 11 (c), respectively. Fig. 12 (b) clearly shows that thestart of IC flow and IC overshoot are properly detected by VeE, and that
SGGD is realized with t1 and t2 correctly controlled. Table I shows acomparison table of the closed-loop AGDs. This work is the first work
achieving the fully integrated IC, the real-time control, and theprogrammable IG in the closed-loop AGDs.

0V

Fig. 5. Timing chart of proposed DGD IC with ATC.

6-bit
pMOS
drivers
2.0 mm

2-3 Measured Results

6-bit
nMOS
drivers

2.5 mmFig. 6. Die photo of DGD IC with ATC.
IGBT
moduleIL
Digitalgate
driver

DGD

200 V

IG
VGE

VCE
LeE

VeE
IC

Fig. 7. Circuit schematic of double pulse test.

Digital gate
driver IC

Table I Comparison table of closed-loop AGDs

Target powerdeviceSensor input

Feedback control
targetReal-time control
Number of states
per switching
Preset parameters
for each state
Levels ofparameter

Implementation
IC Process

TPEL’15[11]

TPEL’18
[12]

IGBT

IGBT

TPEL’21[14]SiC
MOSFET

ISSCC’19[13]
Si MOSFETISSCC’21[18]

This work[21]

GaN FET

IGBT

VGE
Timing of Timing of
wavefor
state
state
m
changechangeYes
Yes
Yes

Timing ofstatechangeNo

VDD of highside gate
driverTiming ofstatechange
No

4

3

3

3

3

IG

VGS

RG

IG

IG

NA

2

2

3

6 bit

PCB

PCB

dIC / dt,
VCE

PCB

dIC / dt,
VCE

dIC / dt

VDS

IC (Not fully
IC (Fully
integrated)* integrated)
130 nm
500 nm,HV CMOS 600 V SOI**dIC / dt
Timing ofstatechangeYes

IC (Fully
integrated)
180 nmBCD*Voltage divider for VDS is not integrated.
**High-voltage IC process with the same breakdown voltage as VCC of main circuit is required.

IGBT module

Fig. 8. Measurement setup.
IN

Off
63

nPMOS

On
n1

0
63

nNMOS
IG

0

0A

IN

Off
63

nPMOS

On
27

0
63

nNMOS
IG

Fig. 9. Timing charts for turn-on.

27

0

0A
t1

(a) Conventional single-stepgate drive (SSGD)

2t2(b) Proposed stop-and-gogate drive (SGGD) with
automatic timing control

IEEE CICC 2023

60
40

250

10

20

0
−5

t2 @IL = 10 A

−10

0

t1

t2 @IL = 80 A

0.5

1Time [ms]

−15

0

0.5

1
Time [ms]

1.5

0

2

(a)

200

IL
80 A
70 A
60 A
50 A
40 A
30 A
20 A
10 A

5

VGE [V]80

IC [A]

15

IL
80 A
70 A
60 A
50 A
40 A
30 A
20 A
10 A

t2 [ns]

100

150
100

50
0
0

2

1.5

10

20 30

40 50 60 70
IL [A]

(b)

80

(c)

Fig. 10. Measured results in SGGD with ATC with varied IL. (a) IC waveforms. (b) VGE waveforms. (c) t2 vs. IL.
1.2

n1 = 2

IL = 20A

n1 = 24

n1 = 2

IL = 50A

1.0

0.6
0.4

−18%
Proposed10

Conventional

2−21%
Proposed

1

−9%

0.2

0
0

n1 = 633

20

30
IOVERSHOOT [A]
(a)

0

40

n1 = 63

10

20

30

Point A (n1 = 4)

040

Conventional

−38%

4

Proposed
Point B −18%

2

−14%
0

6

ELOSS [mJ]

ELOSS [mJ]

ELOSS [mJ]

Conventional

0.8

IL = 80A

8

0

Point C(n1 = 63)20
40
30
IOVERSHOOT [A](c)

10

IOVERSHOOT [A](b)50

Fig. 11. Measured ELOSS vs. IOVERSHOOT of conventional SSGD and proposed SGGD at IL = 20 A, 50 A, and 80 A.
ELOSS : 0.6 mJ
ELOSS : 3.1 mJ
ELOSS : 5.0 mJ
VCE: 50 V/div

VCE: 50 V/div

VCE: 50 V/div

IC: 25 A/div

IC: 25 A/div

IC: 25 A/div

VGE: 12.5 V/div

VGE: 12.5 V/div

0

0

VeE: 2 V/div

VREFH
VREFL

Time

VeE: 2 V/div
nPMOS
63

27

27

4

0

VeE: 2 V/div

nPMOS

nPMOS

200 ns/div

200 ns/div

0

0

0

0

VGE: 12.5 V/div
200 ns/div

2

0
t1

t2

Time

0

(b) Proposed Point B(a) Point A
Fig. 12. Measured waveforms in Point A, Proposed Point B, and Point C in Fig. 11 (c) at IL = 80 A.

3 Single-Input Dual-Output Digital Gate Driver IC for
Equalizing Drain Current of Two Parallel-Connected SiC
MOSFETs
3-1 Research Motivation
In power electronics systems, when large current exceeding the
rated current of a power device is applied, it is common to connect
multiple power devices in parallel. Due to variations in thecharacteristics of the power devices, however, the current
concentrates in part of the devices and the heat generation due tolosses is localized, which degrades the reliability of the powerTime(c) Point C

devices. In the conventional method of parallel connection of powerdevices, the characteristics of the power devices are measured inadvance, and power devices with matching characteristics are
selected for parallel connection, which will increase the cost.
Therefore, a technology to automatically equalize the current of
power devices connected in parallel is required. The problem withthe previous papers of current equalization is that they require a lotof ICs including such as current sensors [23–24], timing control
circuits [14, 23–25], and regulators for gate voltage amplitude control[26–27], which will also increase the cost.
To solve the problems, a single-input, dual-output (SIDO) digital gate
driver (DGD) IC, integrating all necessary circuits including two 6-bit

IG1

6

ID1’

VTH2

VGS1

Q1
ID1 VGS230

0Current
sensors

Rogowski coils

Fig. 13. Circuit schematic of fabricated half-bridge circuit andproposed SIDO DGD IC.
nPMOS1 [0] nPMOS1 [1] nPMOS1 [2] nPMOS1 [3] nPMOS1 [4] nPMOS1 [5]

IO

2IO

4IO

8IO

16IO

32IO

WP

2WP

4WP

8WP

16WP

32WP

0.5

1

IG1 = nIO
= 0 A to 6 A
n = 0 to 63
IO = 95 mA

ID2

4IO

8IO

16IO

32IO

WN

2WN

4WN

8WN

16WN

32WN

VGS1

1

1.5

Time [ms]

1.9 A
0.5

1

1.5

VGS1

0

nNMOS nPMOS

0

20

ID1

0.5

1

ID1

10

0.5

1

1.5

0.32 A
0
0

2

1

0.5

ID1

2.7 mm

DGD1
7.7 mmFig. 15. Die photo of SIDO DGD IC.
Q3

SIDO DGD IC

1.5

2Time [ms]Time [ms]Time [ms](a) Initial state w/o control (b) DC current equalization (c) Proposed DC and surge
current equalization by(Conventional)
by nNMOS1 control
nNMOS1 and nPMOS2 control

Fig. 17. Measured waveforms of VGS1 & VGS2 and ID1 & ID2 at IL =40 A.

TIA’17 [1]

TPEL’21 [4]ISPSD’20[2]

Target power device

Si IGBT &SiC MOSFETGaN FETGaN FET

Process

180 nm BCD

Number of outputs
Output voltage swing

1
15 V

Levels of IG

6 bit

Max. IG

5A

Q1

Controller,
Current sensors

PCB
Rogowskicoils

2

0.13 AID2

180 nm HV
180 nm
CMOS
BCD
1
1
5V
3.3 V
8 bit (coarse),
7 bit
6 bit (fine)
5 V / 0.12 Ω 3.3 V / 0.5 Ω= 42 A= 6.6 AISPSD’21 This work
[3]
[28]
SiC
GaN FETMOSFET
180 nm
180 nm
BCD
BCD
1
2
5V
18 V
6 bit

6 bit

5A

6A

DGD2

Q2

1.5

Time [ms]Table II Comparison table of DGD ICs

Fig. 14. Circuit schematic of DGD1 for Q1.

Q1

2.1 V

VGS2

30

0.13 A

ID2

9.8 A
0
0

2

nNMOS2

30

2

10

IG1

2IO

0.5

20

10
0
0

VDD = 18 V

030

nNMOS1

18

0

10

0

2

2.6 A

ID1

20

nNMOS1 [0] nNMOS1 [1] nNMOS1 [2] nNMOS1 [3] nNMOS1 [4] nNMOS1 [5]

IO

1.5

Time [ms]30

nPMOS1nPMOS2

28

20

VGS1

10

0

2.1 V

VGS2

0

63

nNMOS220

10

Current
probe

nNMOS1

18

030

VGS1 = VGS2

20

Q2
ID2

63

nNMOS1 = nNMOS2

63

nPMOS1 = nPMOS2

VGS1, VGS2 [V]

6

DGD1
ID2’

300 V
VTH1

0

ID1, ID2 [A]ControlnPMOS1 [5:0]
nNMOS1 [5:0]

IG2

6

0

63

nPMOS1 = nPMOS2

ID1, ID2 [A]nPMOS2 [5:0]
nNMOS2 [5:0]63

VGS1, VGS2 [V]IN

6 DGD2ILQ30ID1, ID2 [A]Controller

63

VGS1, VGS2 [V]

SiC MOSFETs
Single-input, dual-output (SIDO)
digital gate driver (DGD) IC

nNMOS nPMOS

nNMOS nPMOSIEEE CICC 2023

Functions integrated
into IC

1 driver1 driver1 driver1 driver2 drivers,
2 current
sensors,
controller

Drain current
equalization of twoparallel MOSFETs

No

No

No

No

Yes

variations in device characteristics by controlling the gate waveforms,
SIDO DGD IC is newly developed. Except for two PCB Rogowski
coils [29], all the necessary circuits including two 6-bit DGDs, twocurrent sensors, and a controller are fully integrated into a single chip.
SIDO DGD IC has 24 bits of control bits. nPMOS1 [5:0] and nNMOS1 [5:0]
control the gate current (IG1) for Q1, while nPMOS2 [5:0] and nNMOS2[5:0] control the gate current (IG2) for Q2. Fig. 14 shows the circuit
schematic of DGD1 for Q1 in Fig. 13. IG1 can be varied in 64 levels atturn-on depending on 6-bit digital signals nPMOS1 [5:0], which isdefined as nPMOS1, where nPMOS1 is an integer between 0 and 63. The
64-level IG1 control from 0 A to 6 A in 95 mA increments at turn-on of
Q1 is achieved by selectively turning on or off six pMOSFETs withbinary weighted gate widths (WP, 2WP, 4WP, 8WP, 16WP, 32WP) in
the output stage depending on nPMOS1 [5:0]. The same design isapplied to the turn-off of Q1 by controlling nNMOS1 [5:0].

Fig. 16. Photo of PCB of half bridge.
DGDs, two current sensors, and a controller, is proposed [28] toautomatically equalize the drain current (ID) of two parallel-connected
SiC MOSFETs. The proposed SIDO DGD IC will enable a highperformance power electronics systems using SiC MOSFETs at low
cost, because SiC MOSFETs with large variations can be connectedin parallel without prior testing and selection.

3-2 Circuit Design
Fig. 13 shows a circuit schematic of the fabricated half-bridge circuitand SIDO DGD IC. The half-bridge consists of three SiC MOSFETs(Q1 – Q3 : SCT3030AL, 650V, 70A) including the low-side twoparallel Q1 and Q2. In order to equalize DC (ID1,DC, ID2,DC) and surge(ID1,SURGE, ID2,SURGE) components of ID of Q1 and Q2 (ID1, ID2) with

3-3 Measured Results
Fig. 15 shows a die photo of SIDO DGD IC fabricated with 180-nm
BCD process. Fig. 16 shows a photo of PCB of the half bridge.
Fig. 17 shows the timing chart and the measured waveforms of VGS1
& VGS2 and ID1 & ID2 at IL = 40 A. In this work, the threshold voltage ofQ1 (VTH1) is assumed to be lower than that of Q2 (VTH2). Among theeight parameters of nPMOS1, nNMOS1, nPMOS2, and nNMOS2 in the on andoff states of Q1 and Q2, nNMOS1 in the on state is controlled to equalize
ID1,DC and ID2,DC by digitally controlling the gate voltage amplitude,
and nPMOS2 in the on state is controlled to equalize ID1,SURGE and
ID2,SURGE by digitally controlling the gate current at turn-on. Vice versa,
if VTH1 > VTH2, nNMOS2 and nPMOS1 are controlled. Compared with theconventional gate driving (Fig. 17 (a)), the proposed gate driving (Fig.
17 (c)) with nNMOS1 and nPMOS2 control reduces the differenceIEEE CICC 2023
between ID1,DC and ID2,DC from 2.6 A to 0.13 A by 95% and thedifference between ID1,SURGE and ID2,SURGE from 1.9 A to 0.32 A by83%.
Table II shows a comparison table of DGD ICs. This work is theworld's first IC that achieves ID equalization of two parallel MOSFETs
by integrating two DGDs, two current sensors, and a controller.

4 Large Current Output Digital Gate Driver Using HalfBridge DAC IC and Two Power MOSFETs for IGBTs
4-1 Research Motivation
High-voltage, large-current IGBT modules (e.g. ratings of 6500 V,
1000 A) are used in many social infrastructure fields including highvoltage DC transmission systems and train traction systems [30]. In
addition to improving IGBTs themselves, gate driving technologies
can be used to reduce the loss of IGBTs. Recently, many papers
have been published on the simultaneous reduction of both switchingloss (ELOSS) and switching noise by active gate waveform control
using digital gate drivers (DGDs) [1-5, 31]. Conventional DGDs,
however, are difficult to apply to the 6500 V, 1000 A IGBT modules,
because the modules require DGD with (1) the output voltage swing(VSWING) of ± 15 V to prevent a false turn-on and (2) the gate current(IG) of up to around 20 A because of the large gate capacitance. For
example, VSWING is 3.3 V [2], 5 V [3–5], 15 V [1], and 18 V [31], andthe maximum IG is between 5 A [1, 3] and 42 A [4].
Digital gate driver (DGD)

IG Saturation
regionHalf-bridge digital-to-analog
converter (HB DAC) ICPowerMOSFETs

4-3 Measured Results

IGBT
IG

VGSH

VGE
VDD2

Q2
VDD4

DAC
VGSL

Fig. 18. Circuit schematic of proposed digital gate driver (DGD)
including HB DAC IC and two power MOSFETs.
Half-bridge digital-to-analog
converter (HB DAC) ICIN

H_nPMOS [7:0]
H_nNMOS [7:0]

EnableScan In
Scan CLK

TimingSerial-in
parallel-out
shift
register

128

8

Fig. 23 shows a timing chart for the turn-on measurement of theconventional single-step gate driving (SGD). n is varied in SGD,
where n is integers between 0 and 255. m is 60 or 100 in this work.
Fig. 24 shows the measured n dependence IG in SGD to demonstrate
the successful operation of 8-bit DGD at VDD3 = VDD4 = 3.5 V and 4
V and m = 60 and 100. To investigate the performance of DGD itself,
a 100 mF capacitor is connected to the output of DGD and IG is
measured. IG is monotonically increasing with n, although it isnonlinear. The maximum IG is 58 A.
Table III shows a comparison table of DGDs. The proposed DGD
using HB DAC IC and two power MOSFETs achieves the largest

VDD3

DAC
VGSH

8

Parallel-inserial-out
shift registers
L_nPMOS [7:0]
L_nNMOS [7:0]

Edgedetector

Figs. 18 to 20 show a circuit schematic of the proposed DGD
including HB DAC IC and two power MOSFETs (Q1 and Q2 :BSC094N06LS5, 60 V, 47 A), a block diagram of the proposed HB
DAC IC, and a timing chart of DGD, respectively. DGD is a currentsource gate driver. The novelty of this work is that power MOSFETs
are used as the output stage of the gate driver to achieve large IG,
and DGD operation is achieved by digitally controlling the gate
amplitude (VGSH and VGSL) of the power MOSFETs operating in thesaturation region instead of the linear region using the proposed HB
DAC IC to achieve the current-source gate driver. As shown in Fig.
19, HB DAC IC includes two DACs operating with different power
supply rails, shift registers for serial inputs to reduce the number of
input pins, and an edge detector to generate pulse signals fromexternally supplied “Timing” signal. HB DAC IC does not include thedriver transistors. If all the functions are integrated into a single IC,
the chip size will be huge and the cost will be high. By controlling thegate voltage of Q1 (VGSH) with a 16-bit input DAC (Fig. 19), IG can bedigitally varied four times at turn-on (Fig. 20). The four periods fromt1 to t4 are determined by “Timing” signal, and t1 to t4 can be changed
independently. The same is true for turn-off.
Fig. 21 shows a die micrograph of HB DAC IC fabricated with 180nm BCD process. The die size is 2.5 mm by 1.0 mm. Fig. 22 showsa photo of PCB of DGD.

VDS of Q1

VDD1

DAC

VDD3

4-2 Circuit Design

Edge detector

High-side
floating VSS
8

VDD4

DAC
VGSL

8

1 mm

Q1

VGSH

To solve the problems, an 8-bit DGD using a half-bridge digital-toanalog converter (HB DAC) IC and two power MOSFETs is proposed[6] to enable VSWING of ± 15 V and large IG up to 58 A for the 6500 V,
1000 A IGBT modules.

Shift registers
DAC

Low-side VSS

Fig. 19. Block diagram of proposed half-bridge digital-to-analog
converter (HB DAC) IC.
IN

On

2.5 mmFig. 21. Die micrograph of HB DAC IC.

OffTiming

VGSL
IG

Front

VDD3
0V
VDD4
0V
0A
VDD1

Q2
HB DAC IC

VGE 0 V

−VDD2

t1 t2

t3

t4

Fig. 20. Timing chart of DGD.

t5

t6 t7 t8 t9

t10

t1

Back
Q1

37 mm

VGSH

48 mm
Fig. 22. Photo of PCB of DGD.

IEEE CICC 2023
IN

Off

On

H_nPMOS 255

n

H_nNMOS

m

0
255
0

V

VGSH DD3

0V

IG

0A

Fig. 23. Timing chart for turn-on measurement of conventional
single-step gate driving (SGD).
60

VDD3 = VDD4 = 4 V

50

VDD3 = VDD4 = 3.5 V
VDD1 = VDD2 = 15 V

IG [A]

40
30

m = 6020
10m = 100

0

0

50

100

n

150

200

250

Fig. 24. Measured n dependence IG in SGD to demonstrate
operation of 8-bit DGD.
Table III Comparison table of DGDs
TIA’17 [1]Target powerdeviceProcess

Chip area
Output voltage
swing

ISPSD’20[2]

ISPSD’21[3]

TPEL’21 [4]This work[6]

Si IGBT &SiC MOSFET
180 nm
BCD
6.25 mm2

GaN FETGaN FETGaN FET

Si IGBT180 nmBCD
1.97 mm2

180 nm
BCD
4.32 mm2

180 nm HV
CMOS
5.0 mm2

180 nmBCD
2.5 mm2

15 V

3.3 V

5V

5V

30 V

Levels of IG

6 bit

7 bit

6 bit

Max. IG

5A

3.3 V / 0.5 Ω= 6.6 A

5A

Functions
integrated into IC

1 driver1 driver1 driver8 bit (coarse),
6 bit (fine)
5 V / 0.12 Ω= 42 A
1 driver

8 bit

58 A
2 DACsVSWING of 30 V and the largest IG of 58 A in DGDs. This work is thefirst to demonstrate the advantages of DGD in the high-voltage,large-current IGBT modules.

5 Summary and Future Design Challenges
This paper presents the digital gate driver IC with automatic timing
control, the single-input dual-output digital gate driver IC for
equalizing drain current of two parallel-connected SiC MOSFETs,
and the large current output digital gate driver, which were developed
to achieve a networked digital gate IC by driving and sensing powerdevices.
Future design challenges for the digital gate ICs include: (1) sensing
technology for the operating and degradation states of powerdevices via gate terminals to achieve integrated sensor circuits; (2)integration of signal isolators and isolated power supplies into ICs toeliminate external bulky transformers; and (3) development ofalgorithms to determine digital gate driver parameters based on
sensor output to meet customer needs such as loss reduction, noise
reduction, and failure prediction.
Acknowledgment:This work was partially supported by NEDO (JPNP21009) and JSPS
KAKENHI Grant Number JP21K18711.

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