1D-20
A Low Voltage Buck DC-DC Converter Using On-Chip Gate BoostTechnique in 40nm CMOSXin Zhang1, Po-Hung Chen1, Yoshikatsu Ryu2, Koichi Ishida1, Yasuyuki Okuma2,Kazunori Watanabe2, Takayasu Sakurai1, and Makoto Takamiya1
1
University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan,
Semiconductor Technology Academic Research Center (STARC), 3-17-2 Shin Yokohama, Kohoku-ku,
Yokohama 222-0033, Japan

2

Abstract - A low voltage buck DC-DC converter (0.45-V input,0.4-V output) with on-chip gate boosted (OGB) and clockfrequency scaled digital PWM controller is designed in 40-nm
CMOS process. The highest efficiency to date is achieved at theoutput power less than 40PW. In order to compensate for thedie-to-die delay variations of a delay line in the proposed digital
PWM controller, a linear delay trimming by a logarithmic
stress voltage (LSV) scheme with good controllability is also
proposed and verified in measurement.

0V

On-chip gate boost (OGB)
VIN

VIN=0.45V

Level
shifter

VIN-VIN
SC DC-DC
2VIN
SC DC-DC

CK_PWMMP
VOUT=0.4V
-VIN
2VIN

LevelshifterMNCK(20kHz)

In modern low-power applications, digital circuits areworking with near-threshold supply voltage (VDD) to achieveenergy efficient operation. Thus an adaptive VDD control
with low voltage operation becomes of great importance. In[1], a low dropout regulator (LDO) is used for the adaptive
VDD control. However, its efficiency is limited to less than
VOUT (output voltage) /VIN (input voltage). To improve theefficiency, a buck DC-DC converter is developed in thispaper [2].
Generally speaking, the efficiency of the buck converterwith low VIN and POUT is quite low, because (1) the loss inpower transistors increases due to low VIN and (2) thecontroller power dominates the total power when POUT is low.
From simple calculation, it can be shown that to achieve
more than 90% efficiency at POUT of 2mW, the quiescentpower required is less than 222nW. In order to achieve a highefficiency buck converter, this paper proposes (1) an on-chipgate boost (OGB) by fully integrated switched-capacitor(SC) DC-DC converters, (2) a low power clock frequencyscaled 0.45-V digital PWM controller, and (3) a linear delay
trimming by a novel logarithmic stress voltage (LSV)
scheme to compensate for the die-to-die delay variations of adelay line in the PWM controller with good controllability.

II. Implementation of Buck DC-DC Converter
A. On-Chip Gate Boost (OGB)
Fig. 1 shows a block diagram of the proposed buckconverter with OGB. Without OGB, driving voltages of thepower transistors are low (=VIN), thus the loss of the powertransistors increases and the efficiency decreases. In order toreduce the on-resistance of the power transistors, a fully
integrated 2VIN (=double voltage) SC DC-DC converter forthe nMOS power transistor (MN) and a minus VIN SC
DC-DC converter for the pMOS power transistor (MP) aredeveloped to boost the supply voltages for the gate drivers.
The PWM signal (CK_PWM) is boosted to “-VIN to VIN” and“0V to 2VIN”, for MP and MN, respectively.

109

IOUT

Load

VIN

I Introduction

978-1-4673-3030-5/13/$31.00 ©2013 IEEE

2VIN
VIN
0V

VIN
0V-VINVIN

OUT_VREF

Digital PWM controller

VREF=0.4V

OUT_VREF(H)

Clock frequency controller

VREF(H)=VREF+'V

OUT_VREF(L)VREF(L)=VREF-'V

Fig. 1. Block diagram of proposed buck converter.
CK_PWM

Digital PWM controller
TCK(20kHz)

Linear delay trimming by LSVDelay0

Delay1

Delay2

Delay31

VIN
110
Q00
Q10
Q20
Q31

Bi-directional shift register (SR)OUT_VREF

CK_SRSel

OUT_VREF(H)OUT_VREF(L)

1 16

Clock frequency controller

Fig. 2. Digital PWM controller and clock frequency controller.

B. Digital PWM Controller
Fig. 2 shows a circuit schematic of a digital PWMcontroller and a clock frequency controller. Instead of aconventional analog feedback control, a delay-line based
digital PWM controller is newly developed for 0.45-V
operation. A clock frequency controller is also employed forpower saving. Specifically, when VOUT is higher than thehigh reference voltage (VREF(H)) or lower than the low
reference voltage (VREF(L)), the clock signal (CK) is given toSR; when VOUT is between VREF(H) and VREF(L), CK divided
by 16 is given to SR, thereby reducing the controller power.
C. Delay Line Trimming by LSV
In the digital PWM controller, a delay-line without
feedback control is used to minimize the controller power.
Therefore, there is a risk that PWM operation may fail due tolarge variations of the delay line. To compensate for thedie-to-die variations, a delay trimming by a charge injection[3] is proposed. Fig. 3 shows a schematic of the trimmed

1D-20TABLE I
Performance Summary

Vn-well=Vstress
VDD=1.1VOut
CK(20MHz)Fig. 3. Trimmed delay line with charge injection.
1050PmTechnology40-nm CMOS

Input voltage

0.45V

Output voltage

0.34V~0.44V

Output power

270nW~165PW

Output ripple<5mV

Max. efficiency

97% at 7PW

450Pm

Quiescent power
140nW
at IOUT=0
Active areaOn-chip
SC DC-DCPowertransistors

0.043 mm2



PWM controller

III. Measurement Results

A die photo of the buck converter fabricated with a 40-nm
CMOS is shown in Fig. 4. Fig. 5 shows a measured stresstime dependence of the delay of the trimmed delay line andthe retention characteristics for 8 dies. The target delay is set
to five times of the initial delay to show the controllability ofproposed LSV scheme. The linear delay trimming by LSV
and the compensation of the die-to-die delay variations aresuccessfully demonstrated. No significant retention
degradation is observed.
Fig. 6 shows the measured dependence of the efficiency
on POUT. By using the proposed OGB, the efficiency isincreased from 55% to 96% at POUT of 15PW. On the other
hand, at POUT of 270nW, the efficiency is increased from60% to 67% by the proposed clock gating of SR. At POUT
range from 2PW to 50PҏW, the proposed buck converter
achieves more than 90% efficiency (> ideal LDO
efficiency=0.4V/ 0.45V=89%) with a peak value of 97% at
7PW. Fig. 7 shows the comparison with the published low
voltage and low power DC-DC converters [4-8]. Table Ishows a performance summary.

Delays of 8 dies are trimmed to target value
66
55
44s
ur
ho rs
72 hours48 uho24 sur
ho s
8 ur
ho surho33
22Linear delay trimmingis achieved by LSV.

1152

Delay of trimmed delaylines (a. u.)

Fig. 4. Chip micrograph.

00048121620104

24Total stress time (s)105106Time after stress (s)Fig. 5. Measured delay trimming by proposed LSV.

100

With gate boost & clock
gating (proposed)
VIN=0.45V
VOUT=0.4V

Efficiency (%)(%)
Efficiency

90
80

With clock gating& w/o gate boost

70
With gate boost &w/o clock gating

60
50

On-chipgate
boost

Clock
frequency
scaling

40
100nW
0.1

1PW
1V. Summary

10PW
100PW
10100Output
power
Output power

A 0.45-V input, 0.4-V output on-chip gate boosted (OGB)
buck converter with clock gated digital PWM controller isdesigned in 40-nm CMOS process. The proposed buckconverter achieved the highest efficiency to date with POUT
less than 40PW. Moreover, higher than 90% efficiency isachieved at POUT range from 2PW to 50PҏW. A linear delay
trimming by a logarithmic stress voltage (LSV) scheme isalso proposed to compensate for the die-to-die delay
variations of a delay line in the PWM controller with good
controllability.

1mW
1000



Fig. 6. Measured dependence of efficiency vs. output power.
100

[8]

This work

90Ref. Type CMOS

Efficiency (%)[6]807060[7][4][5]50100nW1PW

10PW

Output power

VIN(V)

VOUT(V)[4]

SC65nm 1.20.5[5]

LDO 65nm 0.50.450.5[6]Buck 65nm 1.2[7]

Buck 130nm 1.8 0.575[8]Buck 250nm 1.21.0This
Buck 40nm 0.45work

0.4

Acknowledgements
This work was carried out as a part of Extremely Low
Power (ELP) project supported by METI and NEDO.

100PW





Fig. 7. Comparison with published low voltage DC-DC converters.

delay line. During the stress for the charge injection, VDD isset to 1.1V. By applying a high n-well voltage as a stressvoltage (Vstress), the absolute value of the threshold voltage ofpMOS is raised to increase the delay.

110References[1] K. Hirairi, et al., ISSCC, pp. 486-487, 2012.
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[5] Y. Okuma, et al., CICC, pp. 323-326, 2010.
[6] Y. Ramadass, and A. P. Chandrakasan, ISSCC, pp. 64-65, 2007.
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