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Design guidelines to achieve minimum energy operation for ultra low voltage tunneling FET
logic circuits

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2015 Jpn. J. Appl. Phys. 54 04DC04(http://iopscience.iop.org/1347-4065/54/4S/04DC04)
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REGULAR PAPER

Japanese Journal of Applied Physics 54, 04DC04 (2015)
http://dx.doi.org/10.7567/JJAP.54.04DC04

Design guidelines to achieve minimum energy operation
for ultra low voltage tunneling FET logic circuits
Hiroshi Fuketa1*, Kazuaki Yoshioka1, Koichi Fukuda2, Takahiro Mori2,
Hiroyuki Ota2, Makoto Takamiya1, and Takayasu Sakurai1
1

University of Tokyo, Meguro, Tokyo 153-8505, Japan
Green Nanoelectronics Center, National Institute of Advanced Industrial Science and Technology, Tsukuba, Ibaraki 305-8569, Japan
E-mail: fuketa@iis.u-tokyo.ac.jp
2

Received September 10, 2014; accepted November 17, 2014; published online January 21, 2015
A tunneling ﬁeld effect transistor (TFET) attracts attention, because TFET circuits can achieve better energy efﬁciency than conventional MOSFET
circuits. Although design issues in ultra low voltage logic circuits, such as the minimum operatable voltage (VDDmin), have been investigated for
MOSFET’s, VDDmin for TFET’s have not been discussed. In this paper, VDDmin of TFET logic circuits is evaluated for the ﬁrst time and a closed-form
expression of VDDmin is derived, which indicates that the within-die threshold voltage variation (σVT) strongly affects VDDmin. In addition, since it is notclear how much the energy of the logic circuits is quantitatively reduced when both the subthreshold swing (S) and the power supply voltage are
reduced, an analytical equation of the minimum energy of TFET logic circuits is also derived. From the derived equations, the design guideline ispresented for the device engineers of TFET’s that σVT should be reduced as S decreases. © 2015 The Japan Society of Applied Physics

0.3

Introduction

Energynormalized by that at VDD=1.0V

1.

A tunneling ﬁeld effect transistor (TFET) is drawing attention
with the expectation that a TFET circuit provides better
energy efﬁciency than a conventional MOSFET counterpartby reducing leakage in ultra low voltage domain.1–5) Powerdissipation of CMOS logic circuits (P) is expressed as
2
fCLK þ NIOFF VDD ;P ¼ NC0 VDDð1Þ

where VDD is the supply voltage, ¡ is an activity ratio, C0 is
an input capacitance of a logic gate, such as an inverter or a
NAND gate, IOFF is a leakage current of the logic gate, N is
the total number of logic gates, and fCLK is a clock frequency.
Thus, power delay product, that is, energy of CMOS logic
circuits (E) is given by
2
E ¼ P  TCLK ¼ NC0 VDD
þ NIOFF VDD TCLK ;ð2Þwhere TCLK is a clock period. TCLK can be expressed as
TCLK ¼ LDP  K

C0 VDD;ION

ð3Þ

where LDP is the depth of the critical path, K is a delay ﬁtting
parameter,6) and ION is ON current of the logic gate, whichcorresponds to the current to charge or discharge the load
capacitance. Thus, Eq. (2) is rewritten by
C0 VDD2
E ¼ NC0 VDD
þ NIOFF VDD LDP K
ION



I
OFF
2
þ
¼ LDP K  NC0 VDD
:
LDP K
ION

ð4Þ

If the circuit structure is identical, LDP, ¡, and N are constant.
Assuming that K does not depend on VDD, the energy of
CMOS logic circuits can be expressed in the standard
notation as


IOFF
2
E / C0 VDD
þ
;
ð5Þ
ION
where ² (= ¡/LDPK) is an effective time ratio and normallyaround 10¹3 for logic circuits.7)
Figure 1 shows the energy of TFET and MOSFET logic
circuits (² = 10¹3) calculated by Eq. (5). As shown in thisﬁgure, the energy has a minimum value at around 0.1 V for

MOSFET (Conv.)(S=90mV/dec)
0.2

EOPT
TFET (This work)(S=30mV/dec)

0.1

ξ=10-3

VOPT
0
0

0.1

0.2

0.3

0.4

0.5

Supply voltage VDD (V)Fig. 1. (Color online) Energy dependence on supply voltage (VDD) for
TFET and MOSFET logic circuits.

TFET and 0.31 V for MOSFET. This is because IOFF/ION
depends on VDD and increases as VDD is reduced. In thenominal VDD region, IOFF/ION is much smaller than ², andhence the energy decreases as VDD is reduced. In the ultra low
VDD region, on the other hand, IOFF/ION is larger than ², andhence the energy increases as VDD is reduced. This means thatthe energy is minimized at a certain supply voltage, and here
we deﬁne such voltage as VOPT and the minimum energy as
EOPT. The closed-form expression of VOPT will be derived in
Sect. 4. In order to achieve the high energy efﬁciency, thecircuit must be operated at VDD = VOPT.
As shown in Fig. 1, VOPT of TFET logic circuits is much
lower than that of MOSFET logic circuits. This is because
VOPT depends on IOFF/ION in Eq. (5), and IOFF/ION of TFET’s
is smaller than that of conventional MOSFET’s at the same
VDD thanks to steeper S. It is not clear, however, how much
VOPT and EOPT are quantitatively reduced when both thesubthreshold swing (S) and VDD are reduced. Therefore, inthis paper, analytical equations of VOPT and EOPT for TFET
logic circuits are proposed in Sect. 4. These equations showthat VOPT is proportional to S, and EOPT is proportional to thesquare of S.
Such ultra low VDD operation at VOPT could cause
functional errors. A minimum operatable voltage (VDDmin)is the lowest voltage at which these functional errors do notoccur.8) If VDDmin were higher than VOPT, minimum energy

04DC04-1© 2015 The Japan Society of Applied Physics

Jpn. J. Appl. Phys. 54, 04DC04 (2015)
Gate
HfO2
Source
N+

p-SOI
BOX

H. Fuketa et al.

Poly-Si
TaN
Drain
50nm
P+

Poly-Si(50nm thick)HfO2 : 2nm
SiN : 0.7nm

TaN (10nm thick)

145nm

Lg=100nm

Si Substrate

Si

Fig. 3. Cross-sectional TEM image of pTFET.

Fig. 2. (Color online) Cross-section of pTFET.

2.

TFET model used for simulation with VTH variability

To perform TFET circuit investigation under VTH variability,
a device model is needed. A measured Si TFET device as
an example is shown in Figs. 2 and 3. A compact model iselaborated and is implemented as a SPICE Verilog-A model,
whose calculation result is shown in Fig. 4 and shows good
agreement with the measurement.11,12) Discrepancy in very
low current region is due to the gate leakage but the region is
not used in the simulations in this paper.
With the manufactured device described above, it is
impossible to achieve steep-S feature at ultra low VDD region
and thus in the simulation below, a work function parameteris modiﬁed and Si is changed to Ge to enable low VDD
operations, since Ge-based TFET’s can achieve larger ON
currents.13–15) The resultant IDS–VDS characteristics which areused in this paper are shown in Fig. 5. Esaki diode current
component is included.
IDS–VGS characteristics in Figs. 5(c) and 5(d) show thecases when VTH is shifted by «30 mV through changing thework function parameter. The exact physical origin of theVTH variation is not in focus here but rather the existence of
the VTH variation is important since VTH changes the current
exponentially, which in turn affects the circuit behavior
strongly. The compact model, being different from a tablemodel, enables the VTH variability simulation.

10 -7
Measurement
Model

10 -8
10 -9
|I DS| (A/μm)

operation could not be achieved. Especially VOPT of TFET
logic circuits is much lower than that of MOSFET logic
circuits as shown in Fig. 1, and hence investigations on
VDDmin are essential for TFET logic circuits. Althoughvariations in TFET devices have been analyzed in theprevious works,9,10) it is not clear how such variations affect
VDDmin. In this paper, VDDmin of TFET logic circuits isinvestigated for the ﬁrst time, and it is revealed that VDDminof TFET logic circuits can be modeled in the same manner as
MOSFET logic circuits, which indicates that VDDmin is
proportional to the standard deviation of the within-die
threshold voltage (VTH) variations (·VT).
From the equations of VOPT and VDDmin derived in thispaper for TFET logic circuits, this paper ﬁnally shows thedesign guideline for the device engineers of the steep S
devices that ·VT should be reduced in proportion to S.
The remainder of this paper is organized as follows.
Section 2 explains the TFET model used in this paper. Using
this model, VDDmin of TFET logic circuits is investigated andthe simulation results are shown in Sect. 3. Section 4 derives
the condition that VTH variation of TFET’s must satisfy toachieve the minimum energy operation for TFET logic
circuits and shows a guideline for the device engineers of thesteep S devices. Finally, Sect. 5 concludes this paper.

10-10
10-11
10-12
10-13
10-14
10-15
10-16
-2

-1.5

-1
VGS (V)-0.5

0Fig. 4. Measured and simulated characteristics of pTFET.

3.

Minimum operatable voltage of TFET logic circuits

In CMOS logic gates, there is a minimum operatable voltage,
VDDmin, below which a logic LSI stops operating. Although
the previous work8) has proposed the theoretical model of
VDDmin for conventional MOSFET logic circuits and veriﬁed
the model with simulation and measurement results, it is notclear whether the model is applicable to TFET logic circuits.
Thus, VDDmin model is investigated for TFET logic circuits
and veriﬁed with simulations in this section. It should be
noted that VDDmin determined by a logical failure due to setup
and hold errors is not focused on in this paper.
I–V characteristics of MOSFET’s in subthreshold region
are written by8)




VGS  VTH þ VDS
VDS
IDS ¼ IM0 exp;
1  exp S  log10 e
UTð6Þ
where IM0 is the current at VDS = VGS = 0 V, S is thesubthreshold swing parameter, © is the DIBL coefﬁcient andUT is the thermal voltage. Actually, I–V characteristics of
TFET’s in low VDS region differ from those of conventional
MOSFET’s shown in Eq. (6). In this paper, the following
approximated expression of I–V characteristics of TFET’s
based on Eq. (6) is introduced for the ease of derivation of
VDDmin asVGS  VTH
VDS
IDS ¼ IT0 exp
1  exp ;ð7ÞS  log10 emwhere IT0 is the current at VDS = VGS = 0 V, S is the averagesubthreshold swing parameter, and m is the saturation voltage
constant, which corresponds to the thermal voltage (UT) for
MOSFET’s.
Figure 6 shows IDS–VGS characteristics of TFET calculated
by Eq. (7) and obtained by SPICE simulations with the

04DC04-2© 2015 The Japan Society of Applied Physics

H. Fuketa et al.

1.0
0.8

1.0
0.8

0.6

0.6

0.4

0.4

0.2

0.2

IDS (μA)-IDS (μA)

Jpn. J. Appl. Phys. 54, 04DC04 (2015)

0
-0.2
-0.4

VGS=-0.05, -0.1,-0.15, -0.2,-0.25, -0.3V
-0.2

-0.1

VGS=0.05, 0.1, 0.15,
0.2, 0.25, 0.3V

-0.6

-0.6
-0.8
-0.3

0
-0.2
-0.4

0
0.1
VDS (V)

0.2

-0.8
-0.3

0.3

-0.2

-0.1

(a)
10-5

10-5

10-8

10-6
10-7
IDS (A)-IDS (A)10-7High VTH device(ΔVT=-σVT,P)

10-9
10-10

10-12
-0.3

-0.2

0.3

-0.1

Low VTH device(ΔVT=-σVT,N)High VTH device(ΔVT=+σVT,N)

10-9

10-11
0

Typical device (ΔVTH=0)(VDS=0.1, 0.2, 0.3V)

10-8

10-10

|ΔVTH|= σVT,P =30mV

10-11

0.2

(b)

Typical device (ΔVTH=0)(VDS=-0.1, -0.2, -0.3V)
Low VTH device(ΔVTH=+σVT,P)

10-6

0
0.1
VDS (V)

10-12
0|ΔVTH|= σVT,N =30mV

0.1

0.2

VGS (V)VGS (V)

(c)

(d)

0.3

Fig. 5. (Color online) I–V characteristics of pTFET and nTFET: (a) IDS–VDS of pTFET, (b) IDS–VDS of nTFET, (c) IDS–VGS of pTFET, and (d) IDS–VGS ofnTFET. ¦VTH represents VTH shift from center (typical) value caused by VTH variation.

10-6

VT ¼

: Simulation: Equation (7)10-7IDS (A)

10-8

VDS=0.03V

10-9
10-10

VDS=0.01V

10-11

S=30mV/dec
m=41mV

10-12
10-13

0

0.05

0.1

0.15

VGS (V)

Fig. 6. (Color online) IDS–VGS characteristics of nTFET obtained bysimulations with compact model described in Sect. 2. IDS–VGS characteristics
calculated by Eq. (7) are also plotted.

compact model described in Sect. 2. Strictly speaking, S has
voltage dependence in TFET as shown in Fig. 6. However,
it is small at ultralow VDD. Hence, in carrying out thetheoretical calculation, S is approximated as an average over
0 and 0.1 V.
The closed-form expression of VDDmin for MOSFET logic
circuits has been derived from the subthreshold characteristics of MOSFET’s shown in Eq. (6).8) Based on thisderivation, VDDmin of TFET logic circuits can be derived from
Eq. (7) asrﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ
ln N þ k  S;
ð8Þ
VDDmin ¼ VT
2
where N is the number of gates and k is the device-dependent
parameter. ·VT is deﬁned as

qﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ
2
2
VT,P
þ VT,N;

ð9Þ

where ·VT,P and ·VT,N are standard deviations of the withindie VTH variation of pTFET and nTFET, respectively, as
shown in Figs. 5(c) and 5(d). In this paper, it is assumed that
VTH is normally distributed.
In order to evaluate the validity of Eq. (8), VDDmin’s of
TFET logic gates are also obtained by Monte Carlo SPICE
simulations. These simulations comply with the proceduredescribed in the previous work.8)
Figure 7 illustrates VDDmin’s of inverter chains obtained byMonte Carlo simulations and calculated by Eq. (8). VDDmin’s
calculated by Eq. (8) agrees with those obtained by thesimulations. This coincidence of theory and simulation shows
the validity of the approximation in Eq. (7). As shown in
Fig. 7, VDDmin of TFET logic circuits is proportional to thesquare-root of logarithm of the number of gates and its slope
and y-intercept depend on ·VT and S, respectively, which isthe same conclusion drawn for a normal MOSFET case.8) The
derivation is based on inverters but it was shown that theexpression works well with NAND’s and NOR’s.8) It has
been reported that the TFET drain current has temperaturedependence but the major effect is on magnitude of the draincurrent and temperature dependence of S at low voltage
region is small.11,12)
In this section, VDDmin of TFET logic circuits wasinvestigated and we conclude that VDDmin of TFET logic
circuits can be modeled in the same manner as MOSFET’s.
4. VTH variation required for minimum energy
operation

In this section, VOPT and EOPT expressions of MOSFET and

04DC04-3© 2015 The Japan Society of Applied Physics

Jpn. J. Appl. Phys. 54, 04DC04 (2015): Monte Carlo sim.

H. Fuketa et al.
0.7: Equation (8)0.15
σVT=20mV

VOPT , VOPT,appox (V)VDDmin (V)σVT=30mV
0.1

σVT=15mV
0.05

σVT=10mV
σVT , P = σVT , N = σVT0: VOPT ( Eq. (13) ): VOPT,approx ( Eq. (14) )

0.6

0

1

2

3

0.4

1

102

ξ=10-40.3
ξ=10-30.2
0.1

4log ( N )10-6

ξ=10-50.5

0103 104 105106

0

20

40

60

80

100

120

Subthreshold swing S (mV/dec)

Number of gates (N)Fig. 8. (Color online) VOPT obtained by Eq. (13) and its approximatedvalue (VOPT,approx) calculated by Eq. (14). VOPT,approx is a good approximationof VOPT.

Fig. 7. (Color online) VDDmin’s of TFET inverter chains obtained byMonte Carlo simulations and closed-form expression [Eq. (8)].

In the subthreshold region, I–V characteristics of MOSFET’s
are given by Eq. (6). Therefore, the energy can be expressed
as



ð1 þ ÞVDD
2
E / C0 VDD  þ exp :ð11ÞS  log10 e
As shown in Fig. 1, the energy is minimized at VDD =VOPT. Thus, VOPT satisﬁes the following equation:dE¼ 0:
dVDD VDD ¼VOPT

ð12Þ

Thus, VOPT is derived as
VOPT ¼ S 

2  W1 ð2e2 Þ;ð1 þ Þ ln 10

ð13Þ

where W¹1(x) is the lower branch of lambert W function.
Although VOPT has been derived in the previous work,6) anapproximate expression VOPT,approx of Eq. (13) is newly
introduced in this paper to understand the dependence of
VOPT on ² analytically as follows:
VOPT,approx ¼ S 

4ð1  2e2 Þ  lnð2e2 Þ:ð1 þ Þ ln 10ð14Þ

Figure 8 shows VOPT and VOPT,approx. The relative error(«VOPT ¹ VOPT,approx«/VOPT) is less than 3.2% under thecondition of 10 < S < 120 mV/dec and 10¹3 < ² < 10¹5,
which means VOPT,approx is a good approximation of VOPT. It
is not easy to understand the dependence of VOPT on ² in
Eq. (13). However, Eq. (14) clearly indicates that VOPT is
reduced as ² increases.

Model ( Eq. (14) )0.8

TFET logic circuits are analytically derived. From thoseexpressions and VDDmin expression described in Sect. 3, thecondition that the within-die VTH variation must satisfy toachieve the minim energy operation is derived. This will be aguideline for the device engineers of the steep S devices.
The energy of MOSFET circuits (E) is given from Eq. (5)
by


IOFF
2
E / C0 VDD  þ
ION


I
DS ðVGS ¼ 0; VDS ¼ VDD Þ2¼ C0 VDD  þ:
ð10Þ
IDS ðVGS ¼ VDS ¼ VDD Þ

Simulation(Fig. 1)
ξ=10-3

0.6

TFET(S=30mV/dec)(This work)

ξ=10-5MOSFET

VOPT (V)(S=90mV/dec)

ξ=10-40.4

ξ=10-3
0.2

0
0

20

40

60

80

100

120

Subthreshold swing S (mV/dec)

Fig. 9. (Color online) Dependence of VOPT on subthreshold swing S.

Equation (14) suggests that VOPT is proportional to S, thatis, VOPT is reduced as S decreases. Figure 9 shows VOPT
calculated by Eq. (14). VOPT’s of MOSFET and TFET logic
circuits obtained by SPICE simulations are also plotted. The
simulated VOPT of TFET circuits agrees with VOPT calculated
by Eq. (14), because I–V characteristics of TFET’s can be
expressed in the same manner as those of MOSFET’s asshown in Eq. (7), which indicates that Eq. (14) is also
applicable to TFET logic circuits.
The minimum energy EOPT is expressed as
EOPT ¼ EðVDD ¼ VOPT Þ2S½2  W1 ð2e2 Þ3
/ C0  : ð15Þ
ð1 þ Þ ln 10
W1 ð2e2 ÞHere, an approximate expression of EOPT is also introduced toclarify the dependence of EOPT on ² as2S½ lnð2e2 Þ: ð16Þ
EOPT,approx / C0   4:65
ð1 þ Þ ln 10
Figure 10 shows EOPT and EOPT,approx. The relative error(«EOPT ¹ EOPT,approx«/EOPT) is less than 7.7% under thecondition of 10 < S < 120 mV/dec and 10¹3 < ² < 10¹5,
which means EOPT,approx is a good approximation of EOPT.
Equation (16) indicates that EOPT is a quadratic function of S.
S of the state-of-the-art MOSFET’s is around 90 mV, whereas
S of the TFET’s used in this work is 30 mV. Equation (16)implies that the energy of TFET logic circuits can be reduced

04DC04-4© 2015 The Japan Society of Applied Physics

H. Fuketa et al.

0.7
0.6

σVT,max (mV)0.5
ξ=10-50.4# of gates (N)60: EOPT ( Eq. (15) ): EOPT,approx ( Eq. (16) )(maximum σVT for VDDmin<VOPT)

EOPT , EOPT,appox
normalized by energy at VDD=1.0V

Jpn. J. Appl. Phys. 54, 04DC04 (2015)0.3
ξ=10-40.2

ξ=10-3

0.1

1M

0

20

40

60

80

100

MOSFET

MOSFET
40
30
20

TFET
σVT,max=15mV

10

S=30mV/dec(This work)

ξ=10-3σ VT , P = σ VT , N = σ VT

40

80

0
0

0

10B

TFET

50

20

60

100

120

Subthreshold swing S (mV/dec)120

Subthreshold swing S (mV/dec)
Fig. 10. (Color online) EOPT obtained by Eq. (15) and its approximatedvalue (EOPT,approx) calculated by Eq. (16). EOPT,approx is a good approximationof EOPT.

by 1/9 compared with MOSFET logic circuits if all the otherparameters such as capacitances of TFET and MOSFET
circuits (C0) are identical.
VDDmin could be an obstacle to achieve such energy
reduction in TFET logic circuits. The rise in VDDmin is causedby the increase in the within-die VTH variation (·VT) as
explained in Sect. 3, and hence we discuss here how small·VT should be controlled to achieve the minimum energy
operation.
In order to achieve the minimum energy operation, circuits
must be functional at VOPT, that is, VDDmin is less than VOPT
(VDDmin < VOPT). From Eqs. (8) and (13), ·VT must satisfy
the following condition:SVT < VT,max / pﬃﬃﬃﬃﬃﬃﬃﬃﬃ ;ln Nsquare of S. For example, when the conventional MOSFET’s
with S of 90 mV/dec are replaced with TFET’s with S of
30 mV/dec and both ·VT and VDD of TFET are reduced to 1/3of those of the conventional MOSFET, EOPT of TFET is
reduced to 1/9 of that of the conventional MOSFET, if all theother parameters are assumed to be the same between theconventional MOSFET and TFET. Therefore, we concluded
that ·VT of TFET’s should be reduced in proportion to S.
Acknowledgment

This research is partly granted by the Japan Society for the
Promotion of Science (JSPS) through FIRST Program
initiated by the Council for Science and Technology Policy(CSTP).

ð17Þ

where ·VT,max is the maximum ·VT required for the correct
operation at VDD = VOPT. Figure 11 shows ·VT,max as afunction of S for 1M and 10B gate logic circuits. In thisﬁgure, it is assumed that the strengths of pMOS and nMOS
are perfectly balanced and © is 0.1 for MOSFET logic
circuits. ·VT,max is proportional to S, as explained in Eq. (17),which means that VTH variation (·VT) should be reduced as
S becomes steeper. For 1M-gate logic circuits, ·VT has tobe controlled within 15 mV to achieve operation at VOPT of
0.1 V. It should be noted that the methodology described hereis applicable to the other TFET cases where S is different.
5.

Fig. 11. (Color online) Dependence of ·VT,max, which is the maximum·VT required for the correct operation at VDD = VOPT, on subthreshold swing
S for logic circuits (² = 10¹3).

Conclusions

In this paper, the design guideline for the device engineersof the steep subthreshold swing (S) devices was presented.
The energy of TFET logic circuits decreases as the supply
voltage (VDD) is reduced, and the energy becomes minimum
at VDD = VOPT. Such reduction of VDD is limited by theminimum operatable voltage (VDDmin), because the logic
gates with less than VDDmin have functional errors. Therefore,
in this paper, analytical equations of VDDmin and the minimum
energy (EOPT) of TFET logic circuits at VDD = VOPT were
proposed. By using the proposed equations, it was clariﬁed
for the ﬁrst time that VDDmin is proportional to the standard
deviation of the within-die threshold voltage variations (·VT),
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