Digital Gate Driver IC with Fully Integrated
Automatic Timing Control Function in Stop-and-Go
Gate Drive for IGBTs
Dibo Zhang, Kohei Horii, Katsuhiro Hata, and Makoto Takamiya
The University of Tokyo, Tokyo, Japan
Abstract— To reduce loss and noise during switching of
IGBTs at low cost even under changing operating conditions,
namely load current (IL) and junction temperature (TJ)
variation, the world’s first active digital gate driver IC with fully
integrated automatic timing control function that achieves both
single-chip integration and real-time control is developed. Inorder to handle various IGBTs with one type of gate driver, theproposed IC also has the world’s first 6-bit programmable gate
current function in the closed-loop active gate drivers. In the
double pulse test of IGBT, compared with the conventional
single-step gate drive, the stop-and-go gate drive with automatic
timing control using the proposed IC effectively reduces theswitching loss (ELOSS) under the collector current overshoot(IOVERSHOOT)-aligned condition and reduces IOVERSHOOT under
ELOSS-aligned condition with IL ranging from 10 A to 80 A and
TJ ranging from 25 ˚C (room temperature) to 125 ˚C, andparticularly at the condition of IL = 80 A at 25 ˚C, the proposed
gate driver reduces ELOSS by 49 % under the IOVERSHOOT-aligned
condition and reduces IOVERSHOOT by 33 % under the ELOSSaligned condition.

AGDs, however, no previous paper has realized (1) and (2)simultaneously, and no previous paper on (3) has been
published. To solve the problems, in this paper, a digital gate
driver (DGD) IC with fully integrated automatic timing
control (ATC) function for IGBTs that realizes all of (1) to (3)is proposed. The design choices in this paper are shown in bluein Fig. 1.
II. PROPOSED DIGITAL GATE DRIVER IC WITH AUTOMATIC
TIMING CONTROL
Figs. 2 and 3 show a circuit schematic and a timing chartof the proposed DGD IC with ATC, respectively. In thefollowing, turn-on is discussed, whereas the exact same is true
for turn-off. The IC includes dIC/dt detector for the statechange, controller for ATC, and a 6-bit current-source type
Digital gate driver (DGD) IC with
automatic timing control (ATC)
5V

PISOs

Keywords— IGBT, IC, surge current, energy loss, active gate
driverI. INTRODUCTION
A lot of active gate drivers (AGDs), where the gate driving
waveform is controlled during the turn-on/off transients, havebeen proposed to reduce both the switching loss and theswitching noise of power devices. AGDs can be classified into
two types, open-loop control [1-6] and closed-loop control [719, 22]. The closed-loop AGDs are required instead of the
open-loop AGDs, because the optimal driving waveformchanges depending on the operating conditions (e.g. load
current and temperature) [20]. Fig. 1 summarizes the design
choices in conventional closed-loop AGDs. To make theclosed-loop AGDs practical, the following three points are
required: (1) single-chip integration instead of PCB
implementation for lower cost, (2) real-time control instead of
iterative control to reliably handle dynamic change of
operating conditions, and (3) programmable AGDs instead of
fixed-function AGDs that require individual optimization fordifferent product variety of power devices. In the closed-loop
Sensorinput

ControlmethodControl
time

ImplementationdIC
dt

Continuous
time
⚫ VGE

Real-timeIC

IC,

VCE, dVCE
dt

VGE, dVGE
dt

State change
⚫ IG
⚫ VGE
⚫ RG

nPMOS

SIPO 36

1WP
IO

15 V
32WP
32IO

Scan In
Scan CLK
IN
5V
VREFH
VREFL

SIPO 36

6
PISOs

dIC
dt
detector

IO
nNMOS

32IO

1WN

32WN

978-1-6654-7539-6/23/$31.00 ©2023 IEEE

LeE

Power emitter (e)Automatic timing control in stop-and-go gate drive
t1

IN
nPMOS

n1

t3

t2

On
63

n2

nNMOS

t4

n4

0

0A

IOVERSHOOT0A

VeE 0 V
VREFL
600 V

VCE

t6

t5

Off

n3

0
63

IC

0V

Fig. 3: Timing chart of proposed DGD IC with ATC.

1225

15 V

Fig. 2: Circuit schematic of proposed DGD IC with ATC.

15 V
VGE 0 V
−15 V

Fig. 1: Design choices in closed-loop AGDs. This work is shown in blue.

Kelvinemitter(E)

Serial-in parallel-out shift register (SIPO)
Parallel-in serial-out shift register (PISO)

IG

PCB

VCE
VGE

VeE

VREFH

Iterative

IC
IG

Level shiftern5n6

digital gate driver with variable gate current (IG) in 64 levels,
where IG = nPMOS × 48 mA and nPMOS is an integer from 0 to
63 (max IG = 3A). At turn-on, an active gate driving is
performed in three slots from t1 to t3 with different IG of strong(n1) -weak (n2) -strong (n3), and this driving method is definedas stop-and-go gate drive (SGGD) [21]. IG switching isrealized by a digital timing control input from dIC/dt detector
to parallel-in serial-out registers (PISO) to drive nMOSFETs
and pMOSFETs with different gate widths connected inparallel. n1 to n3 are preset by a digital input (Scan In), while
t1 and t2 are automatically determined by ATC. An importantfeature of this IC is the full integration of t1 and t2 real-time
automatic control functions on a single chip. The real-time
control of t1 and t2 is done by detecting dIC/dt by sensing thevoltage (VeE) of the parasitic inductance (LeE) between Kelvin
emitter and power emitter in Fig. 2, because VeE = − LeE(dIC/dt), where IC is the collector current. Specifically, as
shown in Fig. 3, the end timing of t1 is determined by detecting
the negative VeE at the beginning of IC flow using a comparator
with the reference voltage of VREFL, and the end timing of t2 isdetermined by detecting the positive VeE at the timing
immediately after IC overshoots using a comparator with thereference voltage of VREFH . Similarly, at turn-off, t4 to t6 is also
automatically switched by the comparing the reference
voltage with VeE completed by dIC/dt detector.

IGBT
moduleIL
Digitalgate
driver

DGD

600 V

IG
VGE

VCE
LeE

VeE
IC

Fig. 5: Circuit schematic of double pulse test.

Digital gate
driver IC

Fig. 4 shows a die photo of DGD IC with ATC fabricatedwith 180-nm BCD process. The die size is 2.0 mm by 2.5 mm.

IGBT module

2.0 mm6-bit
pMOS
drivers

Fig. 6: Measurement setup.

IN

Off
63

nPMOS

6-bit
nMOS
drivers

On
n1

0

IN

Off
63

nPMOS

nNMOS63

IG

IG

0A

0

0A
t1

(a) Conventional single-stepgate drive (SSGD)

2.5 mm63
00

nNMOS63

0

On
40

t2

(b) Proposed stop-and-gogate drive (SGGD) with
automatic timing control

Fig. 7: Timing charts for turn-on.

Fig. 4: Die photo of DGD IC with ATC.

III.
MEASURED RESULTS
Figs. 5 and 6 show a circuit schematic and a measurement
setup of the double pulse test using the developed DGD IC
and an IGBT module (FS100R12N2T4, 1200 V, 100 A),
respectively. The IGBT module is placed on a hotplate formeasurement under different temperature. In this paper, only
turn-on measurements are discussed, and turn-off
measurements are not discussed, because, in the IGBT module,
no trade-off relationship between the turn-off loss and thecollector-to-emitter voltage overshoot was observed when IG
of DGD IC was varied.
Figs. 7 (a) and (b) show the timing charts for turn-on of theconventional single-step gate drive (SSGD) and the proposed
SGGD for comparison, respectively. In SSGD, n1 is varied
from 4 to 63, which emulates a conventional gate driver withvaried gate resistance. In SGGD, on the other hand, (n1, n2,n3) are preset to (40, 0, 63), a set of parameters where

IOVERSHOOT is optimally suppressed with the weakest driving
forced "0", and follow-up turning-on is returned with thegreatest driving force "63" to maximumly reduce further
energy loss, and t1 and t2 are automatically determined by
ATC.
Figs. 8 (a) to (c) show the measured IC and Figs. 8 (d) to (f)show the gate-emitter voltage (VGE) waveforms in SGGD with
ATC with varied load current (IL) from 10 A to 80 A, andjunction temperature (TJ) of 25 ˚C, 75 ˚C (IC averagetemperature 60 ˚C), and 125 ˚C (IC average temperature 90
˚C), respectively. VGE waveforms explicitly show the sunken
parts, which represent t2, varied in duration corresponding tovariation in IL for each of the three TJ’s measured, and t1
remains the same within each TJ. Fig. 9 shows the measured t2
vs. IL relationship of the three sets of data in different TJ. t2 is
automatically increased by ATC, and it is clearly observedthat as t2 increases approximately linearly with IL when TJ is

1226

120

IC [A]

80
60
40

TJ = 25 ˚C

IL
80 A
70 A
60 A
50 A
40 A
30 A
20 A
10 A

15

20
0.5
Time [ms]60
40

t2 @ IL = 10 A

−5t1

t2 @ IL = 80 A

−15
0

1

0.5
Time [ms]TJ = 75 ˚C

IL
80 A
70 A
60 A
50 A
40 A
30 A
20 A
10 A

15

5
0

t2 @ IL = 10 A

−5
t1

−10

0.5
Time [ms]t2 @ IL = 80 A

−15
0

1

0.5
Time [ms](b)100
IC [A]

80
60
40

TJ = 125 ˚C

IL
80 A
70 A
60 A
50 A
40 A
30 A
20 A
10 A

1

(e)

15

TJ = 125 ˚C

10VGE [V]

120

IL
80 A
70 A
60 A
50 A
40 A
30 A
20 A
10 A

TJ = 75 ˚C

10

20
0
0

1

(d)

VGE [V]IC [A]

80

0

(a)

120

IL
80 A
70 A
60 A
50 A
40 A
30 A
20 A
10 A

5

−10

0
0

100

TJ = 25 ˚C

10VGE [V]

100

5
0

t1

20

−10

0
0

−15
0

0.5
Time [ms]1

t2 @ IL = 10 A

−5

IL
80 A
70 A
60 A
50 A
40 A
30 A
20 A
10 A

t2 @ IL = 80 A

0.5Time [ms]

(c)

1

(f)

Fig. 8: Measured results in SGGD with ATC with varied IL and TJ. (a) to (c) are IC waveforms. (d) to (f) are VGE waveforms. (a) and (d) for TJ = 25 ˚C. (b)and (e) for TJ = 75 ˚C. (c) and (f) for TJ = 125˚C.

Figs. 10 (a) to (c) show the measured switching loss (ELOSS)
vs. the collector current overshoot (IOVERSHOOT) of theconventional SSGD and the proposed SGGD at IL = 20 A, 50
A, and 80 A, respectively. In each graph, TJ is varied to 25 ˚C,
75 ˚C, and 125 ˚C. The red curve, which represents TJ = 125
˚C, black curve, which represents TJ = 75 ˚C, and blue curve,
which represents TJ = 25˚C, show the trade-off curves of theconventional SSGD with varied n1 from 4 to 63. In all cases,
the proposed SGGD has lower ELOSS and lower IOVERSHOOT

1227

150

t2 [ns]the same. On the other hand, for a fixed IL, t2 duration
increases as TJ increases, because according to thecharacteristics of the IGBT module under test, IOVERSHOOT
increases as TJ increases. Therefore, the proposed gate driver
automatically extend the weaker driving slot (t2) to suppress
the surge current.

TJ = 125 ˚C

100

75 ˚C
25 ˚C

50

0

0

20

40
IL [A]

60

Fig. 9: Measured t2 vs. IL at TJ = 25 ˚C, 75 ˚C, and 125˚C.

80

TJ [˚C]
25 75 125

n1 = 4Conv.
SSGD
Proposed
SGGD

ELOSS [mJ]

5

−8%
−10%
A1
−10%

2

B1
IL = 20 A

1
0

0

−9%

Conv.
SSGD
Proposed
SGGD

n1 = 4

4
3

IL [A]
20 50 80

20

ELOSS [mJ]6n1 = 63

−8%

15
10

n1 = 63

5

−5%
C1

0
0

10 20 30 40 50 60 70 80
IOVERSHOOT [A]

TJ = 25˚C
20

40
60
IOVERSHOOT [A](a)(a)
TJ [˚C]
25 75 125

n1 = 4Conv.
SSGD
Proposed
SGGD

12
−36%

8

−33%

6

−37%

ELOSS [mJ]

10

4

20

n1 = 63−25%−25% −21%
IL = 50 A

2
0

25

ELOSS [mJ]

14

0

20

60

40
IOVERSHOOT [A]

IL [A]
20 50 8015
n1 = 63

10
5
0
0

80

TJ = 75˚C
20

A2
−46%

40
60
IOVERSHOOT [A]80(b)
TJ [˚C]
25 75 125

A3

25

Conv.
SSGD
Proposed
SGGD

ELOSS [mJ]

ELOSS [mJ]20n1 = 4Conv.
SSGD
Proposed
SGGD

n1 = 4

(b)

25

80

B3

15 −47%C3−49%
n1 = 63
10
B2
−33%
5
−34% −34%
IL = 80 A
C2
060
80 1000
40
20
IOVERSHOOT [A]

IL [A]
20 50 80
Conv.
SSGD
Proposed
SGGD

n1 = 420
15

n1 = 63

10
5
0
0

(c)
Fig. 10: Measured ELOSS vs. IOVERSHOOT of conventional SSGD andproposed SGGD at IL = 20 A (a), 50 A (b), and 80 A (c), and each varies
in TJ. Points A1 to A3, Points B1 to B3, and Points C1 to C3 are definedin (a) and (c).

TJ = 125˚C
20

40
80
60
IOVERSHOOT [A]

100

(c)
Fig. 11: Measured ELOSS vs. IOVERSHOOT of conventional SSGD andproposed SGGD at TJ = 25 ˚C (a), 75 ˚C (b), and 125 ˚C (c), and eachvaries in IL.

1228

than the conventional SSGD. In Figs. 10 (a) and (c), Points A1
to A3, Points B1 to B3, and Points C1 to C3 are defined for(IL, TJ) = (20 A, 25 ˚C), (80 A, 25 ˚C), and (80 A, 125 ˚C),
respectively, where Points "B"s are the proposed SGGD, Point"A"s are the conventional SSGD with closest IOVERSHOOT
comparing to proposed ones, and Point "C"s are theconventional SSGD with the closest ELOSS comparing toproposed ones. The measured waveforms for these nine points
are shown later in Figs. 12 to 14. At (IL, TJ) = (20 A, 25 ˚C) in
Fig. 10 (a), compared with the conventional SSGD (Point A1
and Point C1), the proposed SGGD (Point B1) reduces ELOSS
by 10 % under IOVERSHOOT-aligned condition and reduces
IOVERSHOOT by 5 % under ELOSS-aligned condition. At (IL, TJ) =(80 A, 25 ˚C) in Fig. 10 (c), compared with the conventional

VCE: 100 V/div

VCE: 100 V/div

VGE: 7.5 V/div

IC: 25 A/div

0

ELOSS : 1.9 mJ

ELOSS : 1.9 mJ

ELOSS : 2.1 mJ

VCE: 100 V/div

IC: 25 A/div

IC: 25 A/div

0

VGE: 7.5 V/div0

200 ns/div

VGE: 7.5 V/div
200 ns/div

200 ns/div
VREFH

0

0

0
VeE: 2 V/div

VREFL

VeE: 2 V/div

40

63

VeE: 2 V/div
nPMOS

nPMOS

nPMOS
13
0

Time

0

294 ns 70 ns(b) Proposed Point B1(a) Point A1

15

0

Time

0

Time

(c) Point C1

Fig. 12: Measured waveforms in Point A1, Proposed Point B1, and Point C1 in Fig. 10 (a) at IL = 20 A and TJ = 25˚C.

VCE: 100 V/div

0

VCE: 100 V/div

VCE: 100 V/div

IC: 25 A/div

IC: 25 A/div

IC: 25 A/div

0

VGE: 7.5 V/div

200 ns/div

VREFH

0
VREFL

VeE: 2 V/div

Time

0

VeE: 2 V/div

nPMOS
63

40
5

0

VeE: 2 V/divnPMOS(a) Point A2

VGE: 7.5 V/div

200 ns/div

0

nPMOS

0

VGE: 7.5 V/div

200 ns/div

0

ELOSS : 9.2 mJ

ELOSS : 9.0 mJ

ELOSS : 17.8 mJ

110294 ns 137 ns(b) Proposed Point B2

Time

0

Time
(c) Point C2

Fig. 13: Measured waveforms in Point A2, Proposed Point B2, and Point C2 in Fig. 10 (c) at IL = 80 A and TJ = 25 ˚C.

1229

ELOSS : 23.5 mJ

ELOSS : 12.6 mJ

ELOSS : 12.4 mJ

VCE: 100 V/div

VCE: 100 V/div

VCE: 100 V/div

IC: 25 A/div

IC: 25 A/div

IC: 25 A/div

0

VGE: 7.5 V/div

0

0

VGE: 7.5 V/div

VGE: 7.5 V/div
200 ns/div

VREFH

0

0

0
VeE: 2 V/div

VREFL

VeE: 2 V/div

40

63

VeE: 2 V/div
nPMOS

nPMOS

nPMOS

0

200 ns/div

200 ns/div

5Time(a) Point A3

12

0

0

Time

320 ns 162 ns(b) Point B3

0

Time

(c) Point C3

Fig. 14: Measured waveforms in Point A3, Proposed Point B3, and Point C3 in Fig. 10 (c) at IL = 80 A and TJ = 125˚C.

SSGD (Point A2 and Point C2), the proposed SGGD (Point
B2) reduces ELOSS by 49 % under IOVERSHOOT-aligned
condition and reduces IOVERSHOOT by 33 % under ELOSSaligned condition. At (IL, TJ) = (80 A, 125 ˚C) in Fig. 10 (c),compared with the conventional SSGD (Point A3 and Point
C3), the proposed SGGD (Point B3) reduces ELOSS by 46 %under IOVERSHOOT-aligned condition and reduces IOVERSHOOT by
34 % under ELOSS-aligned condition.
Figs. 11 (a) to (c), on the other hand, show the measured
ELOSS vs. IOVERSHOOT of the conventional SSGD and the
proposed SGGD at TJ = 25 ˚C, 75 ˚C, and 125 ˚C, respectively.
In each graph, IL is varied to 20 A, 50 A, and 80 A. Similarly,
in each graph, The red curve, which represents IL = 80 A, black
curve, which represents IL = 50 A, and blue curve, which
represents IL = 20 A, show the trade-off curves of theconventional SSGD with varied n1 from 4 to 63, and the
proposed SGGD has advantage over conventional SSGD on
lower ELOSS and lower IOVERSHOOT.
Figs. 12 (a) to (c) show the measured waveforms in Point
A1, which represents the waveform of SGGD with n1 = 13,
Point B1, the proposed SGGD, and Point C1, which represents
the waveform of SGGD with n1 = 15 in Fig. 10 (a),respectively, under IL = 20 A, TJ = 25˚C condition. In Fig. 12(b), SGGD is realized with t1 and t2 correctly controlled bydetecting VeE comparing to VREFH and VREFL. Figs. 13 (a) to (c)show the measured waveforms in Point A2, B2, and C2 in Fig.
10 (c), as SGGD with n1 = 5, the proposed SGGD, and SGGD
with n1 = 11, respectively, under IL = 80 A, TJ = 25˚C condition,
regarded as the standard condition, commonly loaded by the
IGBT device. Fig. 13 (b) clearly shows that the start of IC flow
and IC overshoot are properly detected by VeE. Similarly, Figs.
14 (a) to (c) show the measured waveforms in Point A3, B3,
and C3, as SGGD with n1 = 5, the proposed SGGD, and
SGGD with n1 = 12, respectively, under IL = 80 A, TJ = 125
˚C condition. In Fig. 14 (b), automatic control of t1 and t2 has

TABLE I.

Target powerdeviceSensor input

Feedback control
targetReal-time control
Number of states
per switching
Preset parameters
for each state
Levels ofparameter

Implementation
IC Process

COMPARISON TABLE OF CLOSED-LOOP AGD S
TPEL’15[11]

TPEL’18
[12]

IGBT

IGBT

dIC / dt,
VCE

dIC / dt,
VCE

TPEL’21[14]SiC
MOSFETdIC / dt

VGE
Timing of Timing of
wavefor
state
state
m
changechange
Yes
Yes
Yes

PCB

ISSCC’19[13]

ISSCC’21[18]

This work

Si MOSFETGaN FET

IGBT

VDD of highside gate
driverTiming ofstatechangeNo

Timing ofstatechangeYes

VDS
Timing ofstatechangeNo

dIC / dt

4

3

3

3

3

IG

VGS

RG

IG

IG

2

3

NA

2

PCB

PCB

IC (Not fully
IC (Fully
integrated)* integrated)
130 nm
500 nm,HV CMOS 600 V SOI**

6 bit
IC (Fully
integrated)
180 nmBCD*Voltage divider for VDS is not integrated.
**High-voltage IC process with the same breakdown voltage as VCC of main circuit is required.

been successfully achieved by detecting VeE comparing to
VREFH and VREFL. Note also that comparing t1 in Fig. 13 (b) and
Fig. 14 (b), where TJ changed from 25 ˚C to 125 ˚C, t1
increased from 294 ns to 320 ns. The TJ dependence of t1 is
successfully controlled automatically by the proposed ATC.
Table I shows a comparison table of the closed-loop AGDs.
This paper is the first work achieving the fully integrated IC,
the real-time control, and the programmable IG in the closedloop AGDs.
IV. CONCLUSIONSThe proposed DGD IC with ATC is the first work
achieving the fully integrated IC, the real-time control, and theprogrammable IG in the closed-loop AGDs. Low ELOSS and
low IOVERSHOOT can always be achieved at low cost even when
the operating conditions, load current (IL) and junction
temperature (TJ), change. At IL = 80 A and TJ = 25 ˚C,

1230

compared with the conventional SSGD, SGGD with ATCusing proposed DGD IC reduces ELOSS by 49 % under the
IOVERSHOOT-aligned condition and reduces IOVERSHOOT by 33 %under the ELOSS-aligned condition by automaticallycontrolling t1 and t2 in real-time.
ACKNOWLEDGMENT
This work was partly supported by NEDO (JPNP21009).
REFERENCES[1]

K. Miyazaki, S. Abe, M. Tsukuda, I. Omura, K. Wada, M. Takamiya,
and T. Sakurai, “General-purpose clocked gate driver IC with
programmable 63-level drivability to optimize overshoot and energy
loss in switching by a simulated annealing algorithm,” IEEE Trans. Ind.
Appl., vol.53, no.3, pp. 2350-2357, May-June 2017.
[2] W. J. Zhang, J. Yu, Y. Leng, W. T. Cui, G. Q. Deng, and W. T. Ng, “Asegmented gate driver for E-mode GaN HEMTs with simple driving
strength pattern control,” in Proc. IEEE Int. Symp. Power Semicond.
Devices ICs, Sep. 2020, pp. 102-105.
[3] R. Katada, K. Hata, Y. Yamauchi, T. -W. Wang, R. Morikawa, C. -H.
Wu, T. Sai, P. -H. Chen, and M. Takamiya, “5 V, 300 MSa/s, 6-bit
digital gate driver IC for GaN achieving 69 % reduction of switchingloss and 60 % reduction of current overshoot,” in Proc. IEEE Int. Symp.
Power Semicond. Devices ICs, May 2021, pp. 55-58.
[4] D. Liu, H. C. P. Dymond, S. J. Hollis, J. Wang, N. McNeill, D.
Pamunuwa, and B. H. Stark, “Full custom design of an arbitrary
waveform gate driver with 10-GHz waypoint rates for GaN FETs,”
IEEE Trans. Power Electron., vol. 36, no. 7, pp. 8267-8279, July 2021.
[5] W. J. Zhang, J. Yu, W. T. Cui, Y. Leng, J. Liang, Y.-T. Hsieh, H.-H.
Tsai, Y.-Z. Juang, W.-K. Yeh, and W. T. Ng, “A smart gate driver IC
for GaN power HEMTs with dynamic ringing suppression,” IEEE
Trans. on Power Electronics, vol. 36, no. 12, pp. 14119-14132, Dec.
2021.
[6] K. Horii, K. Hata, R. Wang, W. Saito, and M. Takamiya, “Largecurrent output digital gate driver using half-bridge digital-to-analog
converter IC and two power MOSFETs,” in Proc. IEEE Int. Symp.
Power Semicond. Devices ICs, May 2022, pp. 293 – 296.
[7] V. John, B.-S. Suh, and T. A. Lipo, “High performance active gate
drive for high power IGBTs,” in Proc. IEEE Industry Applications
Conf., Oct. 1998, pp. 1519-1529.
[8] Y. Sun, L. Sun, A. Esmaeli, and K. Zhao, “A novel three stage drive
circuit for IGBT,” in Proc. IEEE Conf. on Industrial Electronics andApplications, May 2006, pp. 1-6.
[9] N. Idir, R. Bausiere, and J. J. Franchaud, “Active gate voltage controlof turn-on di/dt and turn-off dv/dt in insulated gate transistors,” IEEE
Tran. on Power Electron., vol. 21, no. 4, pp. 849-855, July 2006.
[10] Z. Wang, X. Shi, L. M. Tolbert, F. Wang, and B. J. Blalock, “A di/dt
feedback-based active gate driver for smart switching and fast
overcurrent protection of IGBT modules,” IEEE Trans. on PowerElectron., vol. 29, no. 7, pp. 3720-3732, July 2014.
[11] Y. Lobsiger and J. W. Kolar, “Closed-loop di/dt and dv/dt IGBT gate
driver,” IEEE Trans. on Power Electron., vol. 30, no. 6, pp. 3402-3417,
June 2015.
[12] F. Zhang, X. Yang, Y. Ren, L. Feng, W. Chen, and Y. Pei, “Advanced
active gate drive for switching performance improvement andovervoltage protection of high-power IGBTs,” IEEE Trans. on PowerElectron., vol. 33, no. 5, pp. 3802-3815, May 2018.
[13] S. Kawai, T. Ueno, and K. Onizuka, “A 4.5V/ns active slew-ratecontrolling gate driver with robust discrete-time feedback technique for
600V superjunction MOSFETs,” in Proc. IEEE International SolidState Circuits Conf., Feb. 2019, pp. 252-254.
[14] Y. Wen, Y. Yang, and Y. Gao, “Active gate driver for improving
current sharing performance of paralleled high-power SiC MOSFET
modules,” IEEE Trans. on Power Electron., vol. 36, no. 2, pp. 14911505, Feb. 2021.
[15] Y. Ling, Z. Zhao, and Y. Zhu, “A self-regulating gate driver for highpower IGBTs,” IEEE Trans. on Power Electron., vol. 36, no. 3, pp.
3450-3461, March 2021.
[16] E. Raviola and F. Fiori, “Experimental investigations on the tuning ofactive gate drivers under load current variations,” in Proc.
International Conf. on Applied Electronics, Sep. 2021, pp. 1-4.

[17] M. Sayed, S. Araujo, F. Carraro, and R. Kennel, “Investigation of gate
current shaping for SiC-based power modules on electrical drive
system power losses,” in Proc. European Conf. on Power Electronics
and Applications, Sep. 2021, pp. 1-10.
[18] J. Zhu, D. Yan, S. Yu, W. Sun, G. Shi, S. Liu, S. Zhang, “A 600V GaN
active gate driver with dynamic feedback delay compensation
technique achieving 22.5% turn-on energy saving,” in Proc. IEEE
International Solid-State Circuits Conf., Feb. 2021, pp. 462-464.
[19] D. Han, S. Kim, X. Dong, H. Li, J. Moon, Y. Li, and F. Peng, “Anintegrated multi-level active gate driver for SiC power modules,” inProc. IEEE Transportation Electrification Conf. & Expo., June 2022,
pp. 727-732.
[20] T. Sai, K. Miyazaki, H. Obara, T. Mannen, K. Wada, I. Omura, M.
Takamiya, and T. Sakurai, “Load current and temperature dependent
optimization of active gate driving vectors,” in Proc. IEEE Energy
Conversion Congress & Exposition, Sep. 2019, pp. 3292-3297.
[21] T. Sai, K. Miyazaki, H. Obara, T. Mannen, K. Wada, I. Omura, T.
Sakurai, and M. Takamiya, “Stop-and-go gate drive minimizing test
cost to find optimum gate driving vectors in digital gate drivers,” inProc. IEEE Applied Power Electronics Conf. and Expo., March 2020,
pp. 3096-3101[22] W. T. Cui, W. J. Zhang, J. Y. Liang, H. Nishio, H. Sumida, H.
Nakajima, Y. Hsieh, H. Tsai, Y. Juang, W. Yeh, and W. T. Ng, "Adynamic gate driver IC with automated pattern optimization for SiC
power MOSFETs," in Proc. IEEE International Symposium on Power
Semiconductor Devices and ICs, May 2022, pp. 33-36.

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