92% Start-up Time Reduction by Variation-Tolerant Chirp Injection (CI) andNegative Resistance Booster (NRB) in 39MHz Crystal Oscillator
Shunta Iguchi, Hiroshi Fuketa, Takayasu Sakurai, and Makoto Takamiya
University of Tokyo, Tokyo, Japan
Abstract
To reduce the start-up time of a crystal oscillator (XO), achirp injection (CI) and a negative resistance booster (NRB)
are proposed. By combining CI and NRB, the measured
start-up time of a 39-MHz XO in 180-nm CMOS is reduced by
92% from 2.1ms to 158μs, which is the shortest time in thepublished XO’s. The measured start-up time variations due tothe ±20% supply voltage change or the temperature change areless than 13%.
Introduction
To reduce the power consumption of RF transceivers, anintermittent operation and an agile transition between a sleep
mode and an active mode are required. The start-up time(tSTART) of the RF transceiver from the sleep mode to the activemode is limited by a crystal oscillator (XO) for the RF carrier
generation, because tSTART of XO is the longest in the RFtransceiver due to a high Q ( > 10000) of a quartz crystal. Thelong tSTART prevents the agile mode transition and increases
power consumption of the RF transceiver. Therefore, in thispaper, new start-up time reduction techniques for a 39-MHz
XO are proposed.
Start-up Time Reduction TechniquesFig. 1 shows a strategy to reduce tSTART of a conventional
Pierce XO shown in Fig. 2 (a). tSTART is determined by thenegative resistance (|RN|) and the internal noise (VNOISE) [1]. To
reduce tSTART in this paper, VNOISE is increased by the proposed
chirp injection (CI), and |RN| is temporarily increased by theproposed negative resistance booster (NRB).
In the previously reported constant frequency injection (CFI)[2] shown in Fig. 2 (b), a ring oscillator (RO) is connected toOut and X1 to increase VNOISE during the start-up. RO iscalibrated to have the same frequency as XO. CFI, however,will fail to work, because XO has the high Q and the frequencyof RO should be the exactly same as that of XO. Even if RO is
perfectly calibrated, the frequency of RO drifts due to thevariation of the supply voltage (VDD) and the temperature, andCFI fails to work.
To solve the problem, CI shown in Fig. 2 (c) is proposed. InCI, instead of the constant-frequency RO in CFI, a chirpgenerator is used to increase VNOISE. The chirp is a signal inwhich the frequency decreases with time. Fig. 3 shows a circuit
schematic of the chirp generator. When CI_en changes from
low to high, the control voltage (VCNT) of VCO is varied from
VDD to 0V. The frequency of the chirp is designed to cross theXO frequency (= 39MHz) considering PVT variations.
Therefore, CI is more tolerant to PVT variations than CFI.
To increase |RN| for reducing tSTART, NRB is added to CI andthe finally proposed XO is shown in Fig. 2 (d). Fig. 4 shows atiming chart of the proposed XO. When a wake-up signal isreceived, both CI_en and NRB_en are activated. While CI_enis high, Chirp is injected to Out and X1. When NRB_en is high,Inv3 is added to Inv1 to increase |RN|, thereby reducing tSTART.
In this paper, tSTART is defined as the time from the wake-up
signal to the timing when the amplitude of Out is equal to 90%of that of the steady-state Out. The activation period of CI_en(tCI) is shorter than that of NRB_en (tNRB).
Experimental Results
The 4 XO’s in Fig. 2 are fabricated in 180-nm CMOS
process and compared. The Inv1 in Fig. 2 is designed to havean oscillation allowance of 5 for XO. Fig. 5 shows a die photo978-1-4799-3328-0/14/$31.00 ©2014 IEEEand a layout of the proposed XO with CI and NRB. Table I
shows a performance summary of the proposed XO with CIand NRB.
Fig. 6 shows a measured time dependence of the chirp
frequency of the chirp generator. The chirp frequency crosses
the XO frequency (= 39MHz) across the best and the worst
corners. Based on the results, tCI is fixed to 40μs.
Optimum gate width of Inv3 and tNRB for NRB are discussed.
Fig. 7 shows a measured gate ratio dependence of tSTART andthe steady-state power in the XO with NRB at infinite tNRB. CI
is disabled. The gate width of Inv3 is normalized to that of Inv1.
By increasing the gate ratio, |RN| is increased and tSTART isreduced at the cost of increasing power. The gate ratio of 13 isused for NRB. In this case, tSTART is reduced by 87%, while thepower increases by a factor of 4.9. Fig. 8 shows a measuredtNRB dependence of tSTART in the XO with NRB. By increasingtNRB, tSTART is decreased and saturated at tNRB > 160μs. To
reduce the power overhead due to NRB, tNRB of 164μs is used.
Fig. 9 shows measured start-up waveforms of theconventional XO (Fig. 2 (a)) and the proposed XO with CI andNRB (Fig. 2 (d)). By combining CI and NRB, tSTART is reduced
by 92% from 2.1ms to 158μs.
To compare the variation tolerance of the 4 XO’s in Fig. 2,VDD and the temperature are varied. Fig. 10 (a) shows ameasured VDD dependence of tSTART at 25ºC. The typical VDD is
1.5V and VDD is varied ±20%. Fig. 10 (b) shows a measured
VDD dependence of relative variations of tSTART. The variationof tSTART is normalized by tSTART at VDD of 1.5V. tSTARTvariation of CFI is much larger than that of CI, because CFI iscalibrated at VDD of 1.5V and the RO frequency changes withVDD, which indicates CI is more variation-tolerant than CFI.
tSTART variation of the conventional XO is as high as 201%,
while that of the proposed CI and NRB is less than 13%. Fig.
11 shows a measured temperature dependence of tSTART at VDDof 1.5V. The typical temperature is 25ºC and the temperature isvaried from -30ºC to 125ºC. Similar to Fig. 10 (a), tSTART of CFI
is longer than that of CI except for 25ºC, because CFI iscalibrated at 25ºC. tSTART variation of the proposed CI and NRB
is less than 7% and the lowest in 4 XO’s.
Fig. 12 shows comparisons of tSTART of 4 XO’s at the typical,
low VDD, and high temperature conditions. tSTART is normalized
by tSTART of the conventional XO at each condition. In CFI, thereduction of tSTART is only 31% at the high temperature
condition, while the proposed CI and NRB reduces tSTART by
more than 92% at the all conditions. Therefore, the proposed CIand NRB is variation-tolerant.
Table II shows a comparison with previously reported XO’s[3-6]. This work shows the shortest tSTART of 158μs andachieves the PVT variation tolerance. Thus, the proposed XO
with CI and NRB enables the agile mode transition between thesleep and active mode, and reduces the power consumption ofthe RF transceiver.
Acknowledgment
This work was partly supported by STARC. The VLSI
chips were fabricated in the chip fabrication program of VDEC
in collaboration with Rohm Corp. and Toppan Printing Corp.
References[1] A. Rusznyak, JSSC, pp. 259-268, 1987.
[2] Y. Kwon et al., TCAS-I, pp. 324-336, 2012.
[3] Y. Chang et al., JSSC, pp. 421-434, 2012.
[4] R. van Langevelde et al., RFIC Symp., pp. 113-116, 2009.
[5] Data sheet of CC2540, Texas Instruments, [Online].
[6] S. Iguchi et al., VLSI Symp., pp. C142-C143, 2013.

2014 Symposium on VLSI Circuits Digest of Technical Papers

236

Amplitude of XO / A
Start-up time (tSTART)
1

Constant Frequency
Injector (CFI)

Chirp Injector (CI)ChirpgeneratorfRing osc.

t10-1
10-2
10-3

|RN|

by NRBVNOISEby CI

OutTime

1AlntSTART ∝RN VNOISE

X1Inv1
R1

RN : Negative resistanceA : Steady-state amplitude
VNOISE : Internal noise

C1Fig. 1. Strategy to reduce tSTART of XO.

VCOQuartz
crystal

X1

R1C1C2

NRB_enOutX1Inv1
R1R2C2Quartz
crystalC1OutR1
C1C2Quartz
crystal

tCIt

Chirp

Chirp

Frequency

39MHz

CMOS process

180nm

Supply voltage

1.5VCore area

0.12mm2

R1500kΩ

NRB_enFig. 3. Chirp generator for CI.
350μm

2.4mm

|RN|

Out

0.9 x A
Start-up

C3434nJ

Start-up time (tSTART)at 1.5V, 25ºC

158μstSTART variation(1.2V to 1.8V) at 25ºC

< 13%tSTART variation(-30ºC to 125ºC) at 1.5V

< 7%tCI = 40μs
6039MHz20102030405060

MeasuredtNRB = ∞w/o NRB

2.0-87%1.0

Gate ratio = 13
is used for NRB.

0.5

1.5
1.0
0.5
00

1.5

5

10020

15

Start-up time (tSTART) [ms]80

Fig. 4. Timing chart of proposed XO with CI and NRB.

2.5

Power consumption [mW]

Chirp frequency [MHz]Measured0

Wake-up

XO
VCO core

Start-up time (tSTART) [ms]Fig. 5. Die photo and layout.

Time
2.5

6+20%25ºC

54Conv.

CFIFig. 932CI1 ProposedCI + NRB01.1 1.2 1.3

1.4

1.5

1.6

1.7

1.8

tSTART tSTART @ 1.5V[%]
tSTART @ 1.5V

Start-up time (tSTART) [ms]

-20%

1.9

250-20%

1.5
1.0
0.5
01000Conv.

2CFI1CI

Proposed CI + NRB
0-40 -20

020406080 100 120

Temperature [ºC]

Fig. 11. Measured temperature dependence oftSTART of 4 XO’s in Fig. 2 at VDD = 1.5V.

tSTART / tSTART of Conv. [%]Start-up time (tSTART) [ms]VDD = 1.5V

200300tNRB [μs]Fig. 8. Measured tNRB dependence of tSTARTin XO with NRB.
CI_en
NRB_en(a)CI50OuttSTART = 2.1ms0
Proposed CI + NRB-50
1.1 1.2 1.3 1.4 1.5

1.7

1.6

1.8

tCI = 40μs

1.9Supply voltage [V]Supply voltage [V](a)(b)
Fig. 10. Measured VDD dependence of (a) tSTART and (b) relative variations of 4 XO’s in Fig. 2 at 25ºC. (b)3100

CFIConv.

150

164μs is used for NRB.

25ºC

+20%

200

Measured
Gate ratio = 13w/o NRB

2.0Gate ratio = Gate width of Inv3 / Gate width of Inv1
Time after CI_en [μs]Fig. 6. Measured time dependence of chirp
Fig. 7. Measured gate ratio dependence offrequency.
tSTART and steady-state power in XO with NRB.
7

12pF, 12pF
181μW

A

Steady-state10Ω

C 1, C 2
PowertSTART

520μm

1.3mm

Resistor(R3)

R2

Start-up energy

Boost00

C2Quartz
crystalTable I Performance summary.

tNRB

C340

R2(a)
(b)
(c)
(d)
Fig. 2. (a) Conventional Pierce XO. (b) XO with CFI [2]. (c) XO with CI. (d) Proposed XO with CI and NRB.

VCNT

100X1

Inv1

R2

CI_en

R3

Negative
Resistance
Booster(NRB)

Inv3

Inv2

CI_en

Inv1

R2V

CI_en

OutCI

Chirp

Inv2

EnableCI_enOut100-31%8060-43%
-58%
-88%

-57%

-69%
-94%-92%

Fig. 9. Measured start-up waveforms. (a) Conv. XO (Fig.
2 (a)). (b) Proposed XO with CI and NRB (Fig. 2 (d)).
Table II Comparison with previously reported XO’s.

-98%

40[3]

200tSTART = 158μs

CI_en
tNRB = 164μs
NRB_en

CFI CI CI+NRB

CFI CI CI+NRB

CFI CI CI+NRB

Typical(1.5V, 25ºC)

Low VDD High temperature(1.2V, 25ºC) (1.5V, 125ºC)

Fig. 12. Comparisons of tSTART of 4 XO’s.

[4][5][6]

ThisworkFrequency

MHz

26

1932

3939

CMOS process

nm65

130

NA

40

180

Supply voltage

V

1.2

1.2

3.0

0.7

1.5

Power

μW

1440

22180

69181

Start-up time(tSTART)

μs

3200 1200

250259

158

NoNA

NoYes

tSTART is robust toPVT variations.

No2014 Symposium on VLSI Circuits Digest of Technical Papers

237