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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO. 11, NOVEMBER 2018

2/3 and 1/2 Reconfigurable Switched Capacitor
DC–DC Converter With 92.9% Efficiency at
62 mW/mm2 Using Driver Amplitude Doubler
Toru Sai , Member, IEEE, Yoshitaka Yamauchi, Student Member, IEEE, Hajime Kando, Tatsuya Funaki,
Takayasu Sakurai, Fellow, IEEE, and Makoto Takamiya, Senior Member, IEEE

Abstract—A 2/3 and 1/2 reconfigurable switched capacitor (SC)dc–dc converter is developed for a per-core dynamic voltage
scaling of many-core microprocessors. The power conversion efficiency and the output power density of the SC dc–dc converter in
2/3 mode is degraded, because full-swing and half-swing drivers
for power transistors are mixed and the resistive loss of thepower MOSFETs with the half-swing drivers is large. To solve
the problem, a fully integrated driver amplitude doubler (DAD) is
proposed. In DAD, the gate amplitude of the power MOSFETs isincreased from half-swing to full-swing by generating a 1/3 input
voltage sampled from a flying capacitor. In the fabricated 2.7-V
input SC dc–dc converter mounting four 100-nF 0402 (0.4 mm ×
0.2 mm × 0.2 mm) multilayer ceramic chip capacitors on 180-nm
CMOS die achieves the highest efficiency of 92.9% at the output
power density of 62 mW/mm2 in the published step-down SC
dc–dc converters.
Index Terms—Switched capacitor (SC), DC-DC converter, stepdown, driver amplitude doubler (DAD), multilayer ceramic chipcapacitor (MLCC), power density.

I. I NTRODUCTIONO ENABLE an energy-efficient operation of many-coremicroprocessors, a fine-grained per-core dynamic voltage
scaling is required [1]. As the number of the cores increases,
the required number of the power supply voltages (V DD ’s) also
increases. Integrated voltage regulators (IVRs) are the solution
to generate multiple V DD ’s on a chip, because increasing thenumber of off-chip voltage regulators is not practical. Key metrics of IVRs are the power conversion efficiency (η), the output
power (POUT ), the form factor, the output power density (PD)(=POUT / area), and the cost.
The design target of this brief is to develop an IVR
with (1) η > 90%, (2) PD > 50mW/mm2 , and (3) a lowcost bulk CMOS process. The conventional IVRs, however,T

Manuscript received August 28, 2017; revised October 4, 2017; accepted
October 5, 2017. Date of publication October 12, 2017; date of current version October 29, 2018. This work was supported by Murata Manufacturing
Company, Ltd. This brief was recommended by Associate Editor H.-J. Chiu.
(Corresponding author: Toru Sai.)
T. Sai, Y. Yamauchi, T. Sakurai, and M. Takamiya are with the Instituteof Industrial Science, University of Tokyo, Tokyo 153-8505, Japan (e-mail:sai@iis.u-tokyo.ac.jp).
H. Kando is with the Innovative Technology Development Department,
Murata Manufacturing Company Ltd., Shiga 520-2393, Japan.
T. Funaki is with the JISSO Technology Development Department,
Murata Manufacturing Company Ltd., Shiga 520-2393, Japan.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2017.2762347

Fig. 1.

η vs. PD of state-of-the-art step-down DC-DC converters.

do not satisfy the design target. Fig. 1 shows η and PD
of the state-of-the-art step-down DC-DC converters with theswitching frequency (f SW ), the output voltage (V OUT ), andthe output current (I OUT ) including both buck converters
and switched-capacitor (SC) DC-DC converters. The design
target of this brief is shown. In the fully integrated buckconverter [2], η of 72% is comparable to η = 67% of an
ideal LDO and η is too low due to the low quality factor (Q = 4.5) of the on-chip inductor. In the buck converterwith on-interposer inductor [3], the lack of the scalability of
inductor [2] is a problem in IVRs, though both η = 90% and
PD = 2.6W/mm2 satisfy the design target. In the fully integrated SC DC-DC converters using the bulk CMOS process,η = 79.76% [4], 81% [8], and PD = 1.3mW/mm2 [5] do notsatisfy the design target, which indicates the tradeoff between
η and PD. In the fully integrated SC DC-DC converters using
the deep trench capacitor process [6], η = 90% and PD =3.71W/mm2 are achieved. This approach does not satisfy thedesign target, because the deep trench capacitor process is not
low-cost and not generally available. In the SC DC-DC converters with off-chip capacitors, PD = 1.0mW/mm2 [7] do notsatisfy the design target.
To achieve the design target, in this brief, a 2/3 and1/2 reconfigurable SC DC-DC converter mounting four 100-nF
0402 (0.4mm × 0.2mm × 0.2mm) multilayer ceramic chipcapacitors (MLCCs) on 180-nm CMOS die is developedc 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
1549-7747 
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

SAI et al.: 2/3 AND 1/2 RECONFIGURABLE SC DC–DC CONVERTER WITH 92.9% EFFICIENCY AT 62mW/mm2 USING DAD

Fig. 3.

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Proposed driver amplitude doubler (DAD).

Fig. 4. Gate/source/drain voltages of all power transistors in conventional
SC DC-DC converter in 2/3 mode.

Fig. 2.
(a) Proposed 2/3 and 1/2 reconfigurable SC DC-DC converter.
(b) Timing chart of conventional and proposed converter in 2/3 mode.

for the dynamic voltage scaling. The developed SC DC-DC
converter with the proposed fully-integrated driver amplitude
doubler (DAD) achieved η = 92.9% and PD = 62mW/mm2
at the input voltage (V IN ) of 2.7V, V OUT of 1.71V, and I OUT
of 100mA.
II. SC DC-DC C ONVERTERS W ITH
D RIVER A MPLITUDE D OUBLER
A. Gate Amplitude in 2/3 SC DC-DC Converters
In this chapter, the problem of the conventional 2/3 SC
DC-DC converter is explained. Then, a new SC DC-DC converter with the proposed DAD is introduced. Fig. 2 (a) showsa circuit schematic of the proposed 2/3 and 1/2 reconfigurable
SC DC-DC converter with two flying capacitors (CFLY1 and
CFLY2 ). In this brief, V IN is 2.7V and V OUT is 1.8V and 1.35V
in 2/3 and 1/2 mode, respectively, because all nine power transistors are 1.8-V core transistors in 180-nm CMOS process.
Fig. 2(b) shows a timing chart of the conventional and the
proposed SC DC-DC converter in 2/3 mode. In the conventional SC DC-DC converter, the amplitude Φ1H and Φ2H is
0.9V, because DAD in Fig. 2(a) is not used and V X is connected to V OUT . In contrast, in the proposed SC DC-DC converter, the amplitude Φ1H and Φ2H is doubled to 1.8V, because
V X of 0.9V is generated by the proposed DAD shown in Fig. 3.
Figs. 4 and 5 show gate/source/drain voltages of all powertransistors in the conventional and the proposed SC DC-DC
converter in 2/3 mode, respectively. The conventional SC
DC-DC converter is based on [4]. In the conventional SC
DC-DC converter in Fig. 4, the resistive loss of M1 , M2 , M5 ,and M6 is large, because |V GS | of M1 , M2 , M5 , and M6 is 0.9V
due to the 0.9-V amplitude Φ1H and Φ2H . Thus, four powertransistors (M1 , M2 , M5 , and M6 ) are weak ON out of theworking seven power transistors (M1 , M2 , M4 , M5 , M6 , M8 ,and M9 ). Fig. 6 shows a simulated |V GS | dependence of ON
resistance of pMOSFET. When |V GS | is reduced from 1.8V
to 0.9V, the ON resistance increases to x3, which degrades ηand PD. To achieve both high η and high PD, the full-swing(=1.8-V amplitude) |V GS | is the primary design goal. In the
proposed SC DC-DC converter in Fig. 5, the resistive loss of
M1 , M5 , and M6 is reduced, because |V GS | of M1 , M5 , andM6 is doubled to 1.8V because of the 1.8-V amplitude Φ1Hand Φ2H thanks to DAD, thereby achieving higher η and PD
than the conventional SC DC-DC converter.

1656IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO. 11, NOVEMBER 2018

Fig. 5. Gate/source/drain voltages of all power transistors in proposed SC
DC-DC converter in 2/3 mode.

Fig. 6. Simulated VGS dependence of ON resistance of pMOSFET for powertransistor.

B. Proposed Driver Amplitude Doubler
How to generate V X of 0.9V is explained in Fig. 5. BothCFLY1 and CFLY2 are implemented with off-chip capacitors,
while both CX1 and CX2 are implemented with on-chip MOS
gate capacitors. DAD with and without CX2 block is discussed.
In DAD without CX2 block, V X is 0.9V in Φ2 phase, because
V X is connected to V 1 of 0.9V. In Φ1 phase, V X goes above
0.9V, because the charge (Q1 ) from the non-overlap clock generator to drive the gate voltage of the power transistors (M1 ,
M2 , M5 , and M6 ) from 2.7V to 0.9V is injected to V X . In
DAD without CX2 block, V X in Φ1 phase is shown as,
VX =CX1 V1 + CG VIN,
CX1 + CG(1)

where CG is the total gate capacitance of the power transistors (M1 , M2 , M5 , and M6 ), CG V IN is the charge amount of
CG in Φ2 phase. Because V 1 is equal to 1/3 V IN , Eq. (1) isrewritten as,
1
CX1 + CG
VIN .
VX = 3
CX1 + CG(2)

Fig. 7.

Simulated CX1 or CX1 + CX2 dependence of VX .

Fig. 8.

Simulated waveforms of VOUT , VX , 1H with CX2 .

When CG is zero, V X is equal to 1/3 V IN . Actually, however, CG is not neglected and V X is above 1/3 V IN (= 0.9V).
When V X goes above 0.9V, M7 will be turned on, which is
not acceptable. Fig. 7 shows the SPICE simulated CX1 dependence of V X . To obtain V X of 0.9V, large CX1 is required andthe die area overhead is increased, which is not acceptable.
To prevent the rise of V X and the large area overhead of
CX1 , DAD with CX2 block is proposed. In DAD with CX2block, in Φ2 phase, CX1 is charged to 0.9V and CX2 is charged
to 0V. V X in Φ1 phase is shown as,
CX1 V1 + CX2 · 0V + CG VIN
VX =CX1 + CX2 + CG
1
3 CX1 + CG
=
VIN .
(3)
CX1 + CX2 + CG
When CX2 is designed to be equal to 2 CG , V X is equal to
1/3 V IN , which achieves the design target. Fig. 8 shows thesimulated waveforms of V OUT , V X , and Φ 1H of Fig. 5 with
CX2 block at I OUT = 100mA, f SW = 5MHz. The voltage V X
samples V 1 by CX1 in Φ2 phase then holds V 1 to 0.9V inΦ1 phase thanks to DAD with CX2 block. Fig. 7 shows thesimulated CX1 + CX2 dependence of V X . CX1 is fixed to 416pF
and CX2 is varied. To obtain V X of 0.9V, the total required
capacitance (CX1 + CX2 ) is reduced by 84%, because CX2 ispre-charged to 0V instead of 0.9V. Thanks to the CX2 block,the area overhead of CX1 + CX2 is reduced.
III. M EASURED R ESULTS
Fig. 9 shows a die photo and a layout of the 2/3 and1/2 reconfigurable SC DC-DC converter directly mounting
four 100-nF 0402 (0.4mm × 0.2mm × 0.2mm) MLCCs(GRM022R60G104ME15) on 180-nm CMOS die. In Fig. 2(a),all nine power transistors are 1.8-V core transistors and otherSAI et al.: 2/3 AND 1/2 RECONFIGURABLE SC DC–DC CONVERTER WITH 92.9% EFFICIENCY AT 62mW/mm2 USING DAD

Fig. 9.

Die photo and layout of reconfigurable SC DC-DC converter.

Fig. 10.

Die photo of reconfigurable SC DC-DC converter on PCB.

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Fig. 12. Measured clock frequency dependence of efficiency in (a) 2/3 modeand (b) 1/2 mode at different IOUT .

Fig. 11.

Thermal shock test.

block also use 3.3-V I/O transistors. Die size is 3.3mm by
1.8mm and the core area is 2.1mm by 1.3mm. Four MLCCs
are used for CIN , CFLY1 , CFLY2 , and COUT . CX1 of 416pF
and CX2 of 69pF are implemented on the die. V IN is fixed to2.7V. Fig. 10 shows a die mounted on PCB.
The mounting of MLCCs on the silicon die is also reported
in [9], however, the reliability of the mounting may be anissue, because the coefficients of thermal expansion of MLCCs
and the silicon are different. To verify the reliability of themounting, the thermal shock testing is done using the thermal shock chamber (Espec TSA-71H-W). Fig. 11 shows thethermal profile of the one cycle of the thermal shock testing specified in the testing standard (JIS C 60068-2-14 [10]).
η of three SC DC-DC converters in 2/3 mode and I OUT of
100mA before and after the 101-cycle thermal shock are measured and compared. The measured η change is very small(Sample 1: η = 92.88% to 92.96%, Sample 2: η = 93.08%
to 93.14%, and Sample 3: η = 92.87% to 92.99%), indicatingthat the mounting of MLCCs on the silicon die is reliable.

Fig. 13. Measured VOUT dependence of efficiency in 2/3 and 1/2 mode withvaried clock frequency at IOUT = 10mA.

Fig. 12 shows the measured clock frequency dependence ofη in 2/3 and 1/2 mode at different I OUT . In 2/3 mode and I OUT
of 100mA, the peak η of 92.9% is obtained at 4MHz and V OUT
of 1.71V, achieving POUT of 171mW and PD of 62mW/mm2 .
In 2/3 mode and I OUT of 10mA, the peak η of 94.6% isobtained at 600kHz and V OUT of 1.75V, achieving POUT of
17.5mW and PD of 6.4mW/mm2 . In 1/2 mode and I OUT of
100mA, the peak η of 92.7% is obtained at 4MHz and V OUT of
1.28V, achieving POUT of 128mW and PD of 47mW/mm2 . In
1/2 mode and I OUT of 10mA, the peak η of 94.5% is obtained
at 500kHz and V OUT of 1.31V, achieving POUT of 13.1mW and
PD of 4.8mW/mm2 . Fig. 13 shows the measured V OUT dependence of η in 2/3 and 1/2 mode with varied clock frequency at1658

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO. 11, NOVEMBER 2018

TABLE IC OMPARISON W ITH S TATE - OF - THE -A RT S TEP D OWN SC DC-DC
C ONVERTERS

Fig. 14.

Measured IOUT dependence of efficiency in 2/3 and 1/2 mode.

IV. C ONCLUSION

Fig. 15.

Measured VOUT and Clk at IOUT = 100mA in 2/3 mode.

The 2/3 and 1/2 reconfigurable 2.7-V input SC DC-DC converter mounting four 100-nF 0402 MLCCs on 180-nm CMOS
die is developed for IVRs. The reliability of the mounting of
MLCCs on the silicon die is measured and verified. Thanks tothe proposed fully-integrated DAD, the SC DC-DC converterin 2/3 mode at V OUT of 1.71V and I OUT of 100mA achieved
the highest η of 92.9% at PD = 62mW/mm2 in the publishedstep-down DC-DC converters.
R EFERENCES

Fig. 16.

Measured VOUT and Clk at IOUT = 100mA in 1/2 mode.

I OUT = 10mA. The operation of the 2/3 and 1/2 reconfigurable
SC DC-DC converter is demonstrated.
Fig. 14 shows the measured I OUT dependence of η of the
proposed 2/3 and 1/2 reconfigurable SC DC-DC converter at
5MHz. In 2/3 mode, the peak η of 93.3% is obtained at I OUT
of 70mA and V OUT of 1.74V, achieving POUT of 122mW
and PD of 45mW/mm2 . In 1/2 mode, the peak η of 92.8%
is obtained at I OUT of 90mA and V OUT of 1.30V, achieving
POUT of 117mW and PD of 43mW/mm2 .
Figs. 15 and 16 show the measured waveforms of V OUT and
Clk of the SC DC-DC converter in 2/3 and 1/2 mode, respectively. V IN is 2.7V and f SW is 5MHz. The peak-to peak spikenoise are 127mV and 83mV in 2/3 and 1/2mode, respectively.
Table I shows the comparison with the state-of-the-art
step-down SC DC-DC converters. The proposed SC DC-DC
converter using the low-cost bulk CMOS process and MLCCs
achieved the highest η of 92.9% at PD = 62mW/mm2 in the
published step-down DC-DC converters, achieving the design
target.

[1] S. Zhang, N. R. Shanbhag, and P. T. Krein, “System-level optimization of switched-capacitor VRM and core for sub/near-Vt computing,”
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 9, pp. 726–730,
Sep. 2014.
[2] P. Kumar et al., “A 0.4V∼1V 0.2A/mm2 70% efficient 500MHz fully
integrated digitally controlled 3-level buck voltage regulator with on-die
high density MIM capacitor in 22nm tri-gate CMOS,” in Proc. IEEE
Custom Integr. Circuits Conf., San Jose, CA, USA, 2015, pp. 1–4.
[3] N. Kurd et al., “5.9 Haswell: A family of IA 22nm processors,” in Proc.
IEEE Int. Solid State Circuits Conf., San Francisco, CA, USA, 2014,
pp. 112–113.
[4] H.-P. Le, S. R. Sanders, and E. Alon, “Design techniques for fully
integrated switched-capacitor DC–DC converters,” IEEE J. Solid-State
Circuits, vol. 46, no. 9, pp. 2120–2131, Sep. 2011.
[5] N. Butzen and M. Steyaert, “12.2 A 94.6%-efficiency fully integrated
switched-capacitor DC–DC converter in baseline 40nm CMOS using
scalable parasitic charge redistribution,” in Proc. IEEE Int. Solid State
Circuits Conf., San Francisco, CA, USA, 2016, pp. 220–221.
[6] T. M. Andersen et al., “4.7 A sub-ns response on-chip switched-capacitor
DC–DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using
deep-trench capacitors in 32nm SOI CMOS,” in Proc. IEEE Int. Solid
State Circuits Conf., San Francisco, CA, USA, 2014, pp. 90–91.
[7] L. G. Salem and P. P. Mercier, “A battery-connected 24-ratio switchedcapacitor PMIC achieving 95.5%-efficiency,” in Proc. IEEE Symp. VLSI
Circuits, Kyoto, Japan, 2015, pp. C340–C341.
[8] G. V. Piqué, “A 41-phase switched-capacitor power converter with
3.8mV output ripple and 81% efficiency in baseline 90nm CMOS,” inProc. IEEE Int. Solid State Circuits Conf., San Francisco, CA, USA,2013, pp. 98–100.
[9] C. Schaef, E. Din, and J. T. Stauth, “10.2 A digitally controlled
94.8%-peak-efficiency hybrid switched-capacitor converter for bidirectional balancing and impedance-based diagnostics of lithium-ion battery
arrays,” in Proc. IEEE Int. Solid State Circuits Conf., San Francisco,
CA, USA, 2017, pp. 180–183.
[10] Japanese Standard Association, Environmental Testing-Part 2-14:
Tests-Test N: Charge of Temperature, Japanese Standard JIS
60068-2-14:2001, accessed: Aug. 28, 2017. [Online]. Available:
http://kikakurui.com/c6/C60068-2-14-2011-01.html