IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001

1633

High Drive-Current Electrically Induced Body
Dynamic Threshold SOI MOSFET (EIB-DTMOS)
with Large Body Effect and Low Threshold Voltage
Makoto Takamiya, Member, IEEE, and Toshiro Hiramoto, Member, IEEE

Abstract—A novel electrically induced body dynamic thresholdmetal oxide semiconductor (EIB-DTMOS) is proposed where thebody is electrically induced by substrate bias and its high performance is demonstrated by experiments and simulations. EIBat the same
DTMOS achieves a large body effect and a low
time. The upper limit of the supply voltage of the EIB-DTMOS ishigher than that of a conventional DTMOS, because the forward
biased p–n junction leakage current of the EIB-DTMOS is lower.
Among several DTMOSs, the accumulation mode EIB-DTMOS
shows the highest drive-current at fixed off-current due to a large
shift (or large back gate capacitance) and a suppressed shortchannel effect.
Index Terms—Body effect, DTMOS, low power, low voltage, SOI
MOSFET.

I. INTRODUCTIONTHE REDUCTION of the supply voltage of a MOSFET isessential to decrease CMOS power consumption. However, as the supply voltage is reduced, it becomes very difficult to realize both a high drive-current and a low off-current.
Therefore, the top priority in a low power device design is highdrive-current at low off-current and low supply voltage. The dynamic threshold MOSFET (DTMOS) [1]–[8], where the gateis connected to the body, can realize both high drive-current
and low off-current at very low supply voltage below 0.6 V, because it has an ideal subthreshold slope and a high drive-current.
DTMOS circuit operation at 0.5 V supply voltage is also demonstrated [9]–[11].
In [1], [2], [4], [7]–[10], the higher drive-current of the
DTMOS than that of the conventional MOSFET is explainedby its “dynamic threshold voltage,” where the threshold voltage( ) is dynamically changed by a positive body to source bias). To enhance the drive-current of the DTMOS, a(large body effect is essential [3], because the gate drive of the
DTMOS is increased byManuscript received July 27, 2000; revised March 2, 2001. This work was
supported in part by the Japan Society for the Promotion of Science (JSPS)
Research for the Future Program and by the Grant-in-Aid for Scientific Research
on Priority Areas, “Ultimate Integration of Intelligence on Silicon Electronic
Systems” from the Ministry of Education, Science, Sports, and Culture. The
review of this paper was arranged by Editor M. Hirose.
M. Takamiya was with the Institute of Industrial Science, Universityof Tokyo, Tokyo 153-8505, Japan. He is now with the NEC Corporation,
Sagamihara, Japan.
T. Hiramoto is with the Institute of Industrial Science, University ofTokyo, Tokyo 153-8505, Japan, and also with the VLSI Design and Education Center, University of Tokyo, Tokyo 113-8656, Japan (e-mail:hiramoto@nano.iis.u-tokyo.ac.jp).
Publisher Item Identifier S 0018-9383(01)05746-X.

Fig. 1. Interpretation of the DTMOS as a kind of “double gate MOSFET.” InDTMOSs, a single channel is induced not only by an n poly-Si gate but by aneutral region (body), because the gate is connected to the body.

compared with a conventional MOSFET. It is interesting thatthe requirements for the body effect in a DTMOS and a normal
MOSFET are opposite [12]. In a normal MOSFET, a small
body effect is desirable to avoid a high electric field perpendicular to the channel and a reverse body effect in stacked circuits.
Another interpretation of the higher drive-current of a
DTMOS compared with that of a conventional MOSFET is toconsider the DTMOS as a kind of “double gate MOSFET” asshown in Fig. 1. A single channel is induced by both the front) is agate and the back gate. The front gate capacitance (normal gate oxide capacitance, and the back gate capacitance( ) is a forward biased p–n junction capacitance between thechannel and the neutral body region. The total gate capacitance, and (
) times as large as that ofof DTMOS isa conventional MOSFET [2], when the body effect factor ( )is defined as(1)
is the gate
where is the channel depletion layer width andoxide thickness. Therefore, a large leads to a large drive-current of the DTMOS.
, beHowever, it is very difficult to attain a large at a low
cause is determined primarily by the ratio of gate oxide thickness ( ) to channel depletion layer width ( ) which is reduced
by a high channel doping concentration. Previously reported
due
DTMOSs [1], [2], [4], [8] have small values of(0.3 V) for a low supply voltage and do not taketo the low
full advantage of the high drive-current inherent to the DTMOS.
In this study, we propose a novel Electrically Induced Body
DTMOS (EIB-DTMOS) which achieves a large and a low
at the same time. A thin SOI layer thickness provides a very

0018–9383/01$10.00 © 2001 IEEE

1634

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001

TABLE IMEASUREMENT METHOD OF SOI nMOSFETS FOR THREE OPERATION MODES

doped wells in a normal bulk MOSFET. However, the distance
between p and n doped substrates needs to be increased to
avoid reverse bias p–n junction breakdown. Another measure
is deep trench isolation between p and n doped substrates.
Complementary doping of substrates can be done by ion implantation through the buried oxide [13], [14]. Contacts to the
p /n doped substrates are fabricated through STI (or LOCOS)
and the buried oxide [13], [14]. Complementary large static substrate biases are supplied externally or generated within the chip.
C. Large Body Effect Factor in EIB-DTMOS

Fig. 2. Schematic cross sections of the proposed EIB-DTMOSs. The gateelectrode is connected to the body. (a) Inversion mode. (b) Accumulation mode.

large , while
is determined by impurity concentration in
the SOI layer. Experimental and simulation results demonstrate
the superiority of the EIB-DTMOS to the conventional DTMOS
canand the normal SOI MOSFET. is as high as 0.8–1 andbe set to around 0.1 V.
II. PROPOSED EIB-DTMOS
A. Device Structure of EIB-DTMOS
Fig. 2 shows a schematic cross-section of the proposed
EIB-DTMOS in the inversion mode and in the accumulation
mode. They have different types of dopant in the SOI layer.
The body region is electrically induced (accumulated in the
inversion mode and inverted in the accumulation mode) by
a large static substrate bias at the back-interface in the SOI
layer. In EIB-DTMOSs the gate is tied to this electricallyinduced body (EIB) via a body contact terminal. In the caseof the inversion mode EIB-DTMOS the conducting channel
is induced by inversion, and in the case of the accumulation
mode EIB-DTMOS the conducting channel is induced byaccumulation. If a large substrate voltage is not applied, theinversion mode EIB-DTMOS operates as the fully depleted SOI
MOSFET shown in Section III, and the accumulation mode
EIB-DTMOS operates as a MOSFET with punch-through. Boththe inversion mode and the accumulation mode EIB-DTMOSs
are enhancement mode devices. In the accumulation mode
EIB-DTnMOS, holes which form the EIB are supplied fromthe p body contact region. We show in Section IV that theaccumulation mode EIB-DTMOS is the best type of DTMOS.
B. Possible Implementations of EIB-DTMOS
The layout of masks for p /n doped substrates below theburied oxide in an EIB-DTMOS is the same as that for p/n

As shown in (1), a large body effect factor ( ) can be obtained by the reduction of channel depletion layer width ( ) at
fixed gate oxide thickness. In a conventional DTMOS, is determined both by the channel profile and by the channel doping
concentration. In an EIB-DTMOS, however, is determined
only by the SOI thickness. Therefore, by thinning the SOI thickness, the EIB-DTMOS can reduce and realize a larger andthus, a higher drive-current, than the conventional DTMOS. Reduced also leads to a suppressed short channel effect.
For low voltage DTMOS design, not only large but also
are important. In a uniformly doped channel MOSFET,
lowandare closely related and large leads to high. In
independently, the channel proorder to determine andcan be obtained byfile must be optimized. Large at low
counter doping and an abrupt low-high step channel profile forthe body [3]. In the conventional DTMOSs, the channel profile
is determined by impurity doping and subsequent impurity diffusion, and it is difficult to obtain a steep low-high step channel
in an indium channel DTMOS
profile. Larger at lower
channel DTMOS has been experimencompared with atally demonstrated [8]. In an EIB-DTMOS, however, channel
profile is determined electrically and ideal abrupt low-ultra-highstep channel profile is realized, which is steeper than in any
other conventional DTMOS. Therefore, the EIB-DTMOS can.
realize the largest at the lowest
III. EXPERIMENTAL
The inversion mode EIB-DTMOS is compared with conventional fully depleted (FD) and partially depleted (PD) SOIMOSFETs by experiment. The devices measured are fully
depleted SOI nMOSFETs with body contacts fabricated on
a SIMOX wafer [15]. The thicknesses of the gate oxide, theSOI, and the buried oxide are 10 nm, 40 nm, and 100 nm,
respectively. An n poly Si gate is used and the SOI layer is
cm .
p-type with a concentration of the order of
A MOSFET is measured in three different modes (FD, PD,
and EIB-DTMOS) by changing the bias conditions shown inV andV, the entire SOI layer
Table I. WhenTAKAMIYA AND HIRAMOTO: HIGH DRIVE-CURRENT ELECTRICALLY INDUCED BODY DYNAMIC THRESHOLD SOI MOSFET

Fig. 3. (a) Measured subthreshold characteristics of a FD SOI MOSFET, a PD
SOI MOSFET, and an inversion mode EIB-DTMOS. A SOI nMOSFET withgate length of 0.8 m is measured by changing bias conditions as shown in
Table I. (b) The measured subthreshold characteristics of an EIB-DTMOS (solidline) and a PD SOI MOSFET (dotted lines). In the PD, V is varied from 0 V
to 0.7 V in 0.1 V steps. The body current ( gate current) of the EIB-DTMOS
is also shown.

=is depleted and the devices operate in the FD SOI MOSFET
V andV, holes are acmode. Whencumulated at the back-interface and the devices operate in the
PD SOI MOSFET mode. When the gate is tied to the body) andV, they operate in the inversion(
mode EIB-DTMOS mode.
Fig. 3(a) shows subthreshold characteristics in the threemodes. The EIB-DTMOS has a steep subthreshold slope.
Fig. 3(b) shows the subthreshold characteristics of the EIBis varied from 0
DTMOS and the PD SOI MOSFET whereis lowered
V to 0.7 V by 0.1 V steps. In a PD SOI MOSFET,
due to the body effect. The EIB-DTMOS
with increased
has the same as a PD SOI MOSFET, because they haveidentical device structures. Therefore for an EIB-DTMOS isdependence ofin thederived experimentally from the
PD SOI MOSFET. The derived from Fig. 3(b) is as high as
0.8, because the ratio of the gate oxide thickness to the SOI
thickness is high. The body current ( gate current) of the
EIB-DTMOS is also shown. Band-to-band tunneling current
between the EIB and the drain is not observed.
rolloff and subthreshold slope degradation
Fig. 4 showsby the short channel effect. The EIB-DTMOS suppresses theshort channel effect very well, because the potential of the backinterface is fixed and the source/drain depletion layer widthis reduced by a forward body bias in the DTMOS. The subthreshold slope of a PD SOI MOSFET is much worse comparedwith a FD SOI MOSFET even for long channel devices becauseof the different effective channel depletion layer widths ( ).
that determines the subIn FD SOI MOSFET, the effective
threshold slope is more than 140 nm, because the effective isthe sum of the SOI thickness (40 nm), the buried oxide thickness(100 nm), and the depletion layer width below the buried oxide.
On the other hand, in a PD SOI MOSFET, is 40 nm, because
is determined by the SOI thickness. In a DTMOS, the sub-1635

Fig. 4. Gate length dependence of V and the subthreshold slope in a FD SOIMOSFET, a PD SOI MOSFET, and an EIB-DTMOS (measured). The definition
of V is shown in the inset.

Fig. 5. Drive-current versus off-current characteristics in a FD SOI MOSFET,
a PD SOI MOSFET, and an EIB-DTMOS (measured). In each device, the gate
length is changed.

threshold slope is steep irrespective of . In Fig. 5, drive-current versus off-current characteristics are compared. In each device, the gate length is changed. In this figure, the supply voltageof PD
is not 0.5 V but 1.5 V just for comparison, because
SOI MOSFET is 0.9 V. Under supply voltage of 1.5 V, large
body current was actually observed in EIB-DTMOS. Nevertheless its value was measured to be only 7.1% and 0.79% of thecorresponding drive-current values in our 1 m and 0.15 m
EIB-DTMOS devices, respectively. Moreover, practical bodycurrent value is considered to be by orders of magnitude smaller
than its drive-current because the normal supply voltage forthe DTMOS operation should be 0.5–0.6 V. The EIB-DTMOS
shows a high drive-current and a low off-current due to a highand a steep subthreshold slope. These experimental results
show that the EIB-DTMOS is superior to conventional FD and
PD SOI MOSFETs.
IV. COMPARISON WITH CONVENTIONAL DTMOSS BY
SIMULATION
In order to demonstrate advantages of the EIB-DTMOS, fourtypes of DTMOS shown in Fig. 6 are compared by device simulation [16]. Fig. 6(a) is a conventional DTMOS (Conv) [1]–[11],1636IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001

(a)

(b)
Fig. 7. Body effect factor ( ) dependence of V
determined by thesimulations for four types of DTMOS at long channel length as shown in
Fig. 6. In the conventional DTMOS and the inversion mode EIB-DTMOS,
bothand V are varied by changing the channel doping concentration(N ) and the SOI thickness (t ), respectively. The gate oxide thickness is
3 nm. The experimental result for the inversion mode EIB-DTMOS with a gate
oxide thickness of 10 nm is also plotted. In the inversion mode EIB-DTMOS,
the simulation results with a gate oxide thickness of 10 nm are also shown tocompare with the experimental result.

(c)

(d)

Fig. 6. Four types of DTMOS compared by device simulation: (a) conventional
DTMOS (Conv), (b) inversion mode EIB-DTMOS (Inv EIB), (c) counter doped
DTMOS (Count), and (d) accumulation mode EIB-DTMOS (Acc EIB). (a)–(b)inversion mode devices; (c)–(d) accumulation mode devices. (b), (d) proposed int
5 nm, t = 10 nm, N = N = 1 10 cm ,this study. t
N = 5 10 cm . N ; t ; t ; N are varied.

2

= =

2

Fig. 6(b) is the inversion mode EIB-DTMOS (Inv EIB), Fig. 6(c)is a counter doped DTMOS (Count) [3], and Fig. 6(d) is the accumulation mode EIB-DTMOS (Acc EIB). The conventional
DTMOS and the inversion mode EIB-DTMOS are inversion
mode devices, and the counter doped DTMOS and the accumulation mode EIB-DTMOS are accumulation mode devices. The
gate oxide thickness is 3 nm, the buried oxide thickness is 20 nm,
the supply voltage is 0.5 V, and the extension junction depth is
15 nm in all cases. A static substrate bias for the EIB-DTMOS
is 12 V.
A. Inversion Mode DTMOSs
Two inversion mode devices are discussed here. In the conventional DTMOS shown in Fig. 6(a), a uniformly doped p typechannel is assumed and the SOI layer is partially depleted. In the
inversion mode EIB-DTMOS shown in Fig. 6(b), a very lightly
doped p type channel is assumed. Fig. 7 shows the dependence
on for the conventional DTMOS and the inversion modeof
EIB-DTMOS at long channel length. The channel doping con) is varied in the conventional DTMOS, and thecentration (SOI thickness ( ) is varied in the inversion mode EIB- DTMOS.
and smallresult in highand large due toHighthe reduced channel depletion layer width at fixed gate oxide
thickness. for the inversion mode EIB-DTMOS is two times as, becauselarge as that for the conventional DTMOS at fixedof the inversion mode EIB-DTMOS is half that of the conventional DTMOS [17]. This is due to the same theory as that
where a uniformly doped channel MOSFET and an ideal stepchannel MOSFET are compared [18], [19]. The experimental reV,sult for the inversion mode EIB-DTMOS () in Section III is also plotted, and it fits the simulation reof the experimental result is too
sults very well. However,high for supply voltages below 0.5 V. If
is decreased, isalso decreased as shown in Fig. 7. Even in the inversion mode.
EIB-DTMOS, therefore, a large can not be attained at low
B. Accumulation Mode DTMOSs, the accumulation mode
To realize both large and low
DTMOSs shown in Fig. 6(c) and (d) are required. In the accumulation mode EIB-DTMOS, a whole SOI layer is doped
and the body is composed ofby n-type dopants for low
holes generated by inversion at the back interface. The conventional counterpart of the accumulation mode EIB-DTMOS is thecounter doped DTMOS [3]. The counter doped DTMOS has a
and a deepshallow n-type doped channel region for low
p-type doped channel region for the body. In both devices, thesurface regions in the SOI layer are lightly doped to avoid mobility degradation by impurity scattering.
The difference between the counter doped DTMOS and theaccumulation mode EIB-DTMOS is discussed in the following.
In the accumulation mode EIB-DTMOS, the body region isis limited by aformed by electrically inverted carriers andthin SOI thickness. The carrier concentration of the body (holes
for nMOS) could be very high and a very steep low-high step
carrier profile is achieved. On the other hand, in the counter
doped DTMOS, not only the counter doped region but also thebody region are formed by the doping. The body concentration
is limited and it is very difficult to obtain a steep low-high carrier
profile. Therefore, the accumulation mode EIB-DTMOS can rethan the counter doped DTMOS.
alize larger at lower
These are the same discussions as those in Section II-C.
) in the accumulation
The channel donor concentration (mode EIB-DTMOS is an important device parameter and needs
dependence ofand .
to be optimized. Fig. 8 shows,
is lowered and is increased because
By increasing
the operation mode is changed from surface channel to buried
and large result in a higher drive-current.
channel. Low
results in punch-through, which is not
However, too highof
cm is used inshown in Fig. 8. Therefore,
the following.
value for the counter doped DTMOS and the accumulationof 0.12 V,
mode EIB-DTMOS are also plotted in Fig. 7. At

TAKAMIYA AND HIRAMOTO: HIGH DRIVE-CURRENT ELECTRICALLY INDUCED BODY DYNAMIC THRESHOLD SOI MOSFET

1637

(a)
Fig. 8. Channel donor concentration (N ) dependence of V and in theaccumulation mode EIB-DTMOS (simulated). The inset shows the channel
concentration profile. N
is also shown.

(b)Fig. 10. Dependence of V on L , and the subthreshold slope in four typesof DTMOS with the same V at a gate length of 0.5 m (simulated). Device
parameters are the same as for Fig. 9.
Fig. 9. Gate voltage dependence of drain current and body current in four typesof DTMOS with the same V at a gate length of 0.5 m by changing device
parameters (simulated). N
3:1 10 cm , t = 89 nm, t = 8:7 nm,
N = 1 10 cm . Other device parameters are shown in the caption ofFig. 6. Subthreshold current characteristics of the four DTMOSs are completely
the same.

2=2each DTMOS is varied. The short channel effect of the accumulation mode EIB-DTMOS is the smallest, because the channel
depletion layer width ( SOI thickness) is the smallest.
E. Drive-Current Versus Off-Currentof the inversion MOSFETs is as low as 0.1–0.2. However,of the counter doped DTMOS is 0.58, and as high as 0.92 isachieved in the accumulation mode EIB-DTMOS.
C. Junction Leakage Current
One of the most serious problems in DTMOSs is an upper
limit of supply voltage due to a forward biased p–n junction
leakage current. Fig. 9 shows forward biased p–n junction curby
rent in four types of DTMOS. The devices have the same
, , , andin Fig. 6. The inversion modechanging
and the accumulation mode EIB-DTMOSs show the smallest
leakage current due to a very small junction area and a highhole concentration. Therefore, the upper limit of supply voltage
of EIB-DTMOSs is higher than that of conventional DTMOS.
) is deFor example, the upper limit of supply voltage (when the body current is equals to drain curfined as
V. In Fig. 9, whileof the conventional
rent atof the EIB-DTMOS is increased
DTMOS is 0.65 V,
to 0.82 V. When the SOI thickness is thinned below 10 nm in
EIB-DTnMOSs to scale down the gate length, the leakage current may increase due to direct tunneling between electrons at
the front interface and holes at the back interface [20].
D. Short Channel Effectrolloff and subthreshold slope degradation
Fig. 10 showsof 0.12 V at a gate length offor four types of DTMOS with a
0.5 m. The device structures and the device parameters except
for the gate length are the same as in Fig. 9. The gate length ofFig. 11(a) shows drive-current versus off-current characteristics of the devices shown in Fig. 10, where they have theat a gate length of 0.5 m. Although the drive-cursame
rent for the four types of DTMOS is almost the same at fixedgate length, the accumulation mode EIB-DTMOS shows three
decades less off-current than the conventional DTMOS at a gate
length of 0.07 m due to the suppressed short channel effect.
Fig. 11(b) shows drive-current versus off-current characteristicsof the conventional DTMOS, the inversion mode EIB-DTMOS,
and the accumulation mode EIB-DTMOS, where the device parameters are changed to have the same off-current at a gate
length of 0.07 m. At a gate length of 0.07 m, the accumulation mode EIB-DTMOS shows one and a half times as highdrive-current as the conventional DTMOS due to a large andmuch less drain-induced-barrier-lowering (DIBL) as shown in
the inset of Fig. 11(b). These results indicate that the accumulation mode EIB-DTMOS has a better performance than any of
the other DTMOSs under any conditions.
F. Gate Delay
Finally, we compare the AC characteristics of the three
types of DTMOS shown in Fig. 11(b) by two-dimensional(2-D) mixed-mode simulations of a three-stage inverter chain[16]. Fig. 12 shows the wire capacitance dependence of thegate delay. The supply voltage is 0.5 V, the gate length is
0.07 m, and the gate width is 0.5/1 m for nMOS/pMOS. The
accumulation mode EIB-DTMOS is the fastest due to a higher
drive-current and a lower junction capacitance.

1638

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001

Fig. 13. Channel donor concentration (N ) dependence of the body sheet
resistance in the accumulation mode EIB-DTMOS with several substrate biases(simulated).

(a)

(b)
Fig. 11. (a) Drive-current versus off-current characteristics of the devices
shown in Fig. 10, where they have the same V at a gate length of 0.5
m (simulated). (b) Drive-current versus off-current characteristics of theconventional DTMOS, the counter doped DTMOS, and the accumulation
mode EIB-DTMOS, where device parameters are changed to have the same
2 10 cm ,off-current at a gate length of 0.07 m (simulated). N
t = 8 nm, N = 1 10 cm . The inset shows the DIBL at a gate
length of 0.07 m.

2= 2

Fig. 12. Wire capacitance dependence of the inverter delay in the conventional
DTMOS, the counter doped DTMOS, and the accumulation mode EIB-DTMOS(simulated). Device parameters are the same as for Fig. 11(b). The effect of the
body RC delay is not included.

V. BODY RESISTANCE PROBLEM IN DTMOSSDTMOSs have a distributed body resistance in the gate width
direction, because the body contact is located at the sides ofthe body. Body RC delay is a serious problem in a DTMOS
with wide gate width ( ), because the body potential does notfollow the gate voltage and differs in the gate width direction for
ac operation [2]–[4], [6], [7], [21]. Although the body RC delay
problem is similar to the gate RC delay problem, the body RC
delay is much larger than the gate RC delay, because the body
sheet resistance is 1 k–100 k /sq. compared with 1–10 /sq.
in gate sheet resistance. In Fig. 12, the effect of the body resisis narrow. Whenis wider,tance is negligible because
the body RC delay becomes comparable to the gate delay andthe body potential does not follow the gate voltage, resulting in
is much wider and thea slower propagation delay. When

body RC delay is much longer, the body potential will depend
strongly on the history of the input and output voltages and will
. In such a case, a history dependentvary between 0 V andpropagation delay and a large power consumption due to low
would be expected [21].
The EIB-DTMOS also has a serious body RC delay. The
body capacitance of EIB-DTMOSs is much lower than thatof a conventional DTMOSs, because the p-n junction area
is very small. However, the EIB-DTMOS has a higher bodyresistance (10 k–100 k /sq.) than the conventional DTMOS(5 k–50 k /sq.) or bulk DTMOS (1 k–10 k /sq.) [6], because
the body is electrically induced only at the SOI/buried oxide)interface. Fig. 13 shows the channel donor concentration (dependence of the body sheet resistance in the accumulation
mode EIB-DTMOS with several substrate biases. As shownis desirable for a large and a low.
in Fig. 8, a highalso leads to an increased body resisHowever, a hightance, because the back-interface is not sufficiently inverted at agiven negative substrate bias. To decrease the body resistance, ahigher substrate bias is needed but causes a reliability problem
iscm
in the buried oxide. For example, whenand required body sheet resistance is the same as the worst caseof the conventional DTMOS (50 k /sq.), a substrate bias of
12 V is needed, which results in a buried oxide electric field of
6 MV/cm. Therefore, in the accumulation mode EIB-DTMOS,
there is a trade-off between the reduction of the body resistanceand the reliability of the buried oxide. A low/high/low channel
profile in the SOI layer alleviates the problem.
In order to solve the body RC problem, an upper limit on theratio must be set. A DTMOS with a large
shouldhave multiple-finger gate layouts with each body contact, andinterdigitated source and drain regions. When a DTMOS is divided into n narrow DTMOSs with respective body contacts,. Fig. 14
the body RC delay is decreased at the rate ofshows the dependence on the number of divided DTMOSs of thegate delay including the body RC delay by 3-dimensional device and circuit mixed-mode simulations [22]. The devices used
are almost the same as the accumulation mode EIB-DTMOS in. The total
is 5 (10) m for nMOS
Fig. 12 except for(pMOS). Devices with both a one side body contact and bothsides body contact are shown. The supply voltage is 0.5 V, thegate length is 0.07 m, the load capacitance is 100 fF, and theinterconnect resistance is 50 . By increasing the finger length,
the gate delay also increases due to an increased body RC delay.
The gate delay without the body RC delay is 40 ps, determinedby 2-D device and circuit mixed-mode simulations [16]. Fig. 14

TAKAMIYA AND HIRAMOTO: HIGH DRIVE-CURRENT ELECTRICALLY INDUCED BODY DYNAMIC THRESHOLD SOI MOSFET

1639

REFERENCES

Fig. 14. NMOS finger length dependence of gate delay including the body
RC delay, deduced by three-dimensional (3-D) device and circuit mixed-mode
simulations (simulated). Upper axis shows the number of fingers corresponding
to the finger length. The inset shows an example of a two-finger gate layout andthe definition of the finger length.

shows that the influence of the body RC delay is observed onlyin the accumulation mode EIB-DTMOS
when
with a both sides body contact, which is not a serious issue inratio is determined by a relalogic circuits. The criticaltive relation between the circuit delay and the body RC delay.
Finally, a change of the influence of the body RC delay on thegate delay is considered in EIB-DTMOSs with scaling-down.
The major part of the body capacitance is the lateral abrupt p–njunction capacitance between the EIB and the source/drain, because the upper capacitance between the EIB and the gate is
negligible in a DTMOS and the lower capacitance between the
EIB and the substrate is small when the buried oxide is thick.
In EIB-DTMOSs, the body resistance is proportional tobecause of the constant sheet resistance of the EIB, and the lateral abrupt p–n junction capacitance between the EIB and the
because of the constant thicksource/drain is proportional toness of the EIB. Therefore, the body RC delay in EIB- DTMOSs. The gate delay is proportional to .
is proportional tois scaled-down at the same rate as .
It is assumed thatratio which does not suffer from theOnce a criticalbody RC delay is found, the gate delay of a future scaled-down
ratio will not be degraded
EIB-DTMOS with the sameby the body RC delay.
VI. CONCLUSION
We have proposed a low power high drive-current EIB, and its high
DTMOS with a large body effect and a low
performance has been demonstrated by experiments and simulations. An ideal low-ultra-high step channel profile made by anelectrically induced body (EIB) with a high carrier concentration
at the back interface and a thin SOI layer reduce the channel
depletion layer width and achieve the maximum body effect at. The upper limit of supply voltage for EIB-DTMOSs islowhigher than that of the conventional DTMOS due to a reduced
p-n junction leakage current. Among several DTMOSs, theaccumulation mode EIB-DTMOS shows the highest drivecurrent at fixed off-current due to a large body effect factor anda suppressed short channel effect.
ACKNOWLEDGMENT
The authors would like to thank T. Saraya and T. N. Duyet for
their great contribution to the fabrication of the devices used inthis work.

[1] F. Assaderaghi, D. Sinitsky, S. Parke, J. Boker, P. K. Ko, and C. Hu, “Adynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage
operation,” in IEDM Tech. Dig., 1994, pp. 809–812.
, “Dynamic threshold voltage MOSFET (DTMOS) for ultra-low[2]
voltage VLSI,” IEEE Trans. Electron Devices, vol. 44, pp. 414–422,
Mar. 1997.
[3] C. Wann, F. Assaderaghi, R. Dennard, C. Hu, G. Shahidi, and Y. Taur,“Channel profile optimization and device design for low-power highperformance dynamic-threshold MOSFET,” in IEDM Tech. Dig., 1996,
pp. 113–116.
[4] H. Kotaki, S. Kakimoto, M. Nakono, T. Matsuoka, K. Adachi, K. Sugimoto, T. Fukushima, and Y. Sato, “Novel bulk dynamic threshold voltage
MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate toshallow-well contact (SSS-C) processes for ultra low power dual gate
CMOS,” in IEDM Tech. Dig., 1996, pp. 459–462.
[5] T. Tanaka, Y. Momiyama, and T. Sugii, “Fmax enhancement of dynamic
threshold-voltage MOSFET (DTMOS) under ultra-low supply voltage,”in IEDM Tech. Dig., 1997, pp. 423–426.
[6] A. Shibata, T. Matsuoka, S. Kakimoto, H. Kotaki, M. Nakono, K.
Adachi, K. Ohta, and N. Hashizume, “Ultra low power supply voltage(0.3V) operation with extreme high speed using bulk dynamic thresholdvoltage MOSFET (B-DTMOS) with advanced fast-signal-transmission
shallow well,” in Proc. Symp. VLSI Technol. Dig. Tech. Papers, 1998,
pp. 76–77.
[7] H. Kotaki, S. Kakimoto, M. Nakono, K. Adachi, A. Shibata, K. Sugimoto, K. Ohta, and N. Hashizume, “Novel low capacitance sidewall
elevated drain dynamic threshold voltage MOSFET (LCSED) for ultra
low power dual gate CMOS technology,” in IEDM Tech. Dig., 1998, pp.
415–418.
[8] S. J. Chang, C. Chen, Y. J. Lee, S. D. Wu, C. Y. Chang, T. S. Chao, J.
W. Chou, T. Lin, T. P. Chen, and S. W. Sun, “High performance sub-0.1
m dynamic threshold MOSFET using indium channel implantation,”in Proc. Int. Conf. Solid State Devices Mater., 1999, pp. 452–453.
[9] T. Fuse, Y. Oowaki, M. Terauchi, S. Watanabe, M. Yoshimi, K. Ohuchi,
and J. Matsunaga, “0.5V SOI CMOS pass-gate logic,” in Proc. ISSCC
Dig. Tech. Papers, 1996, pp. 88–89.
[10] T. Fuse, Y. Oowaki, T. Yamada, M. Kamoshida, M. Ohta, T. Shino,
S. Kawanaka, M. Terauchi, T. Yoshida, G. Matsubara, S. Yoshioka, S.
Watanabe, M. Yoshimi, K. Ohuchi, and S. Manabe, “A 0.5V 200MHz
1-stage 32b ALU using a body bias controlled SOI pass-gate logic,” inProc. ISSCC Dig. Tech. Papers, 1997, pp. 286–287.
[11] T. Hirota, K. Ueda, Y. Wada, K. Mashiko, and H. Hamano, “0.5V
320MHz 8b multiplexer/demultiplexer chips based on a gate array withregular-structured DTMOS/SOI,” in Proc. ISSCC Dig. Tech. Papers,
1998, pp. 188–189.
[12] T. Hiramoto and M. Takamiya, “Low power and low voltage MOSFETs
with variable threshold voltage controlled by back-bias,” IEICE Trans.
Electron., vol. E83-C, pp. 161–169, Feb. 2000.
[13] I. Y. Yang, C. Vieri, A. Chandrakasan, and D. A. Antoniadis, “Back gated
CMOS on SOAIS for dynamic threshold voltage control,” in IEDM
Tech. Dig., 1995, pp. 877–880.
[14] T. Kachi, T. Kaga, S. Wakahara, and D. Hisamoto, “Variable
threshold-voltage SOI CMOSFETs with implanted back-gate electrodes for power-managed low-power and high-speed sub-1-V ULSIs,”in Proc. Symp. VLSI Technol. Dig. Tech. Papers, 1996, pp. 124–125.
[15] T. Saraya, M. Takamiya, T. N. Duyet, T. Tanaka, H. Ishikuro, T. Hiramoto, and T. Ikoma, “Floating body effect in 0.15 m partially depleted SOI MOSFETs below 1V,” in Proc. IEEE Int. SOI Conf., 1996,
pp. 70–71.
[16] Medici Ver. 4.1, Avant! Corp., 1998.
[17] M. Takamiya, T. Saraya, T. N. Duyet, Y. Yasuda, and T. Hiramoto,“High performance accumulated back-interface dynamic threshold SOI
MOSFET (AB-DTMOS) with large body effect at low supply voltage,”
Jpn. J. Appl. Phys., vol. 38, pp. 2483–2486, Apr. 1999.
[18] K. Noda, T. Tatsumi, T. Uchida, K. Nakajima, H. Miyamoto, and C.
Hu, “A 0.1-m delta-doped MOSFET fabricated with post-low-energy
implanting selective epitaxy,” IEEE Trans. Electron Devices, vol. 45, pp.
809–814, Apr. 1998.
[19] Y. Taur and T. H. Ning, Fundamental of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998, pp. 189–193.
[20] J. H. Choi, Y.-J. Park, and H.-S. Min, “Extremely thin film (10nm) SOIMOSFET characteristics including inversion layer to accumulation layer
tunneling,” in IEDM Tech. Dig., 1994, pp. 645–648.
[21] G. O. Workman and J. G. Fossum, “A comparative analysis of the dynamic behavior of BTG/SOI MOSFETs and circuits with distributed
body resistance,” IEEE Trans. Electron Devices, vol. 45, pp. 2138–2145,
Oct. 1998.
[22] Davinci Ver. 4.1, Avant! Corp., 1998.

1640

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001

Makoto Takamiya (S’98–M’00) was born in Hyogo,
Japan, in 1973. He received the B.S., M.S., and Ph.D.
degrees in electronic engineering from the Universityof Tokyo, Tokyo, Japan, in 1995, 1997, and 2000, respectively.
He has been engaged in research on low power
SOI CMOS devices. His research interests include
a scaling of MOSFETs into sub-0.1 m region andultra low-voltage MOSFETs. In 2000, he joined the
NEC Corporation, Sagamihara, Japan.
Dr. Takamiya received the Young ResearcherAward from the 1999 International Conference on Solid State Devices andMaterials.

Toshiro Hiramoto (M’93) received the B.S., M.S.,
and Ph.D. degrees in electronic engineering from the
University of Tokyo, Tokyo, Japan, in 1984, 1986,
and 1989, respectively.
In 1989, he joined the Device Development Center,
Hitachi, Ltd., Ome, Japan, where he was engaged in
the device and circuit design of ultra-fast BiCMOS
SRAMs. Since 1994, he has been an Associate Professor with the Institute of Industrial Science, University of Tokyo, Tokyo, Japan. He has also been an
Associate Professor with the VLSI Design and Education Center, University of Tokyo, since 1996. His research interests include
low power and low voltage design of advanced CMOS devices, SOI MOSFETs, device/circuit cooperation scheme for low power VLSI, quantum effects
in nano-scale MOSFETs, and silicon single electron transistors.