10th International Conference on Power Electronics-ECCE Asia
May 27 - 30, 2019 / BEXCO, Busan, Korea

Gate Waveform Optimization in Emergency
Turn-off of IGBT Using Digital Gate Driver
K. Miyazaki1, K. Wada2, I. Omura3, M. Takamiya1 and T. Sakurai1
1

The University of Tokyo, Tokyo, JapanTokyo Metropolitan University, Tokyo, Japan
3 Kyusyu Institute of Technology, Fukuoka, Japan2

the previous paper [6], which controls the gate waveform
for power devices digitally by changing the number ofswitching MOS transistors dynamically up to 64 levels.

Abstract— IGBTs need to be immediately turned off whena short circuit occurs [1]. This paper discusses the optimized
gate control in this emergency turn-off process. The
optimized gate waveform minimizes the energy loss, hence
the heat generation, while keeping the maximum collectoremitter voltage overshoot within a certain allowable value.
The optimized waveform is found by theoretical analysis andis verified by measurements for the first time. Analyticalexpressions are derived for the optimized control, which
explains well the experimental results. The optimized gate
waveform is realized only by a digital gate driver (DGD)
whose output drivability is programmable over 64 strength
levels. The DGD decreases the energy loss by 22% comparedwith the conventional resistor gate driver [2,3,4].

II. THEORY FOR OPTIMUM WAVEFORM
In this section, an analysis is carried out to find theoptimum gate drive waveform for the emergency turn-off.
First, the current-voltage characteristics of an IGBT should
be modeled using a simple expression for the analyticaltreatment. In this emergency turn-off process, IGBT isoperated in the active region (constant-current region). In
recent IGBTs, the collector current, IC, in the active region
is found not to follow the square-law model but rather canbe modeled by the alpha-power law model [7], that is,
IC=B(VG – VTH)  where VG is a gate voltage, VTH is a
threshold voltage of IGBT, B is constant, and  is current
index (1 <  < 2). This -power model shows an excellent
agreement with the measurement as shown in Fig.2. Since
the short-circuit state is an operation in the active region ofthe IGBT, the α power law in the saturation region of theMOS (active region in the IGBT), which is a behavioral
model taking into consideration the effects of velocity
saturation and short channel effects, was applied foranalysis. Using this model, the differential equations, Eq.1,should hold. This is to keep the voltage overshoot at theallowable maximum voltage, VOV,MAX. CG is gate

Index Terms—Gate driver, short-circuit, IGBT, Activegate control.

I. INTRODUCTION
When a short circuit occurs in a leg of IGBTs, IGBT
should be turned off immediately before it is broken byabnormal heat. The short circuit detection can be done in20-ns [5], which is sufficiently fast, but the turn-off should
be relatively slow to keep the collector-emitter voltage
overshoot, Vov, within a tolerable level. Three ways toturn off the IGBT are investigated in this paper, namely aresistor drive, a single MOS drive, and Digital Gate Drive(DGD) as shown in Fig.1. The DGD chip was reported in

Implemented on a chip
Level-shifters& Buffers Decoder D-FF

VG
VDRIVE(15V)(a) Resistor drive

VDRIVE -VPD_PMOS
VPD_NMOS

VG

BPMOS

6

CK1

BNMOS6GND(b) Single MOS drive

6BPMOS
16BNMOS
16363
DQ
NPMOS

Predriver

63-Parallel
Drivers63
GPMOS

CK6363DQ
NNMOS

VDC=500V

VG
63
GNMOS

CK(c) Digital Gate Drive (DGD)

Fig. 1 Three ways to drive gate of IGBT: (a) conventional resistor drive, (b) single MOS drive, and (c) Digital Gate Drive (DGD) with 64-levelof programmable current drivability [6].

ⓒ2019 KIPE

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104
Square-law
model

500V

IC (A)

103

VG

VCE : 250V/div

IG

VOV500V

Alpha-powerlaw model102

IG : 100mA/div
Measured points101IC = 117 (VG - VTH)1.3

VG : 10V/div

IC = 126 (VG - VTH)21000.1

101
VG - VTH (V)IC : 1000A/div

Fig. 2 -power current model fits very well to measure.

 I C = B (VG − VTH ) dVG= − IGCGdt dI C− L dt = VOV , MAX

01.5

Fig. 3 Calculated optimum waveforms using theoretical expressions inEq.2.

(Eq.1)

DUT: Infineon
FF450R12ME4

L1

VCC=500V1/VOV , MAX tVG (t ) = VTH + (VDD − VTH ) −BL 
CGVOV1( −1)/
 I G (t ) =  BLVOV , MAX V−V−t()
 DD TH
BL 

0.5
1Time (µs)

1800µFV
NI &LabVIEW(Eq.2)

L=L1+L2

 L = 105nH ,V = 15V
with  DD
CG = 25nF
V= 120V OV , MAX B = 128, VTH = 7.1V ,  = 1.3

capacitance of IGBT, IG is gate current, IC is collector
current, and L is power supply bus inductance as shown in
Fig.4. The differential equations, Eq.1, can be solved interms of the optimum gate voltage, VG(t), and the optimum
gate current, IG(t), as in Eq.2
Although the expressions seem complicated, if  is set
to 2, VG and IG have the forms, 𝑉𝑇𝐻 + √𝑎 − 𝑏𝑡 and𝑐/√𝑎 − 𝑏𝑡 , which are a gradually decreasing andincreasing function, respectively.
Considering the above discussions, the optimum gate
drive current waveform, IG, is as follows. First, the gate
should be strongly pulled down using a high gate current.
In this process, since VOV is below VOV,MAX the faster turnoff is better in terms of energy loss. Then, after VOVreaches VOV,MAX, the gate current should follow thegradually increasing function as shown in Eq.2 to keep
the VOV at VOV,MAX. This is the fastest turn-off process
within the tolerant overshoot level while making the15V
VDD=15V
GateDriverL2IGICCG VGVCEELOSS = VCE (t)IC (t)dt

Fig. 4 Circuit scheme and equipment setup for measurements.

energy loss minimum.
The optimized waveforms calculated by Eq.2 is shownin Fig.3 using the parameter values given on the right ofEq.2. These parameters correspond to the experiment inthe next Section. It is not possible to realize the optimum
IG waveform by using a resistor [2,3,4] nor a single
MOSFET. Thus, the DGD is used to verify the theory inSection III.

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III. EXPERIMENTAL SETUP

VG

The experimental setup shown in Fig.4 is used tomeasure the voltage and current of important points. Thecircuit for short-circuit measurement is composed of theIGBT module (Infineon FF450R12ME4) with a high side
always on and a DGD board equipped with the DGD chip
manufactured by TSMC 180nm BCD process. The
measurement is performed by inputting a digital signal
generated from the LabVIEW program on the PC throughthe NI PXI-6555 to the DGD board and measuring theswitching waveform of the low-side IGBT.
A schematic diagram of the DGD output waveform andthe IGBT switching waveform is shown in Fig.xx. First,
the driver outputs high during t1 to turn-on and cause ashort-circuit. In this measurement, the period of t1 is fixed
to 5μ sec. After the short-circuit period of 5 u seconds, aturn-off signal is generated at time t2, and overshootvoltage Vov and loss ELOSS generated at this time aremeasured. The digital signal from LabVIEW dynamicallychanges the DGD output current IG during t2 to generate anarbitrary turn-off waveform.
In order to improve the trade-off relationship between
VOV and ELOSS at the time of short-circuit protection, theturn-off waveform derived from the theory describedabove is generated to compare conventional resistancedrive and single MOS drive.

Turn-off(t2)

5μ sec(t1)

ICVCE

Overshootvoltage(VOV)

Fig. 5 schematic diagram of switching waveform.

(c) Digital Gate Drive(b) Single MOS drive(a) Resistor drive
IG(A)1Fig. 6(b)0.5

IC × VCE(MW)

IC(A)

VCE(V)

0VCC=500V

800
600
40020002000

VOV,MAX≈120V

VOV,MAX≈120V

VOV,MAX≈120V

1000
015

ELOSS = IC (t)xVCE (t)dt

105001Time(µs)

2ELOSS=1.29J

3012Time(µs)

ELOSS=1.38J-22%30-28%

12Time(µs)

ELOSS=1.00JFig. 6 Comparison among various drive methods. Optimum gate drive waveform realized by Digital Gate Drive reduces energy loss by 22%compared with the conventional resistor drive.

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3

Short-circuit
periodEmergency
turn-off period
IC: 400A/div
VCE: 200V/div
VG: 5V/div

Measured IG:5mA/div
Measured VG:5V/div
Digital code:0.25/div
Analytical IG (Eq.2): 5mA/div
Analytical VG (Eq.2): 5V/div

052

63

97100

Magnified view
-63012

IG: 0.5A/div
Digital code: 25/div

345678Time (µs)(a) waveforms after optimization

941005108600.5
11.5Time (µs)(b) agreement between analyticalexpression and measurement

Fig. 7 Overall waveforms in optimized case using DGD corresponding to the case in Fig.4(c). Digital code means the number of turned-on MOStransistors (positive for NMOS and negative for PMOS). Numbers in the figure signify digital code in DGD.

IV. MEASUREMENT RESULTSELOSS, and VOV can be calculated from the measured
data. The experimental results are shown in Fig.6. Threekinds of gate drivers in Fig.1 are employed. V OV iscontrolled to be within the allowable maximum, VOV,MAX,
set at 120V this time by tuning the resistor value in Fig.
6(a), by tuning the size of the driver MOSFET in Fig.6(b),and by manually tuning the current waveform throughdynamically changing the number of turned-on MOSFETs
in Fig. 6(c).
The DGD shows the energy loss 22% less than that forresistor drive and 28% less than MOSFET drive while
keeping the peak VOV,MAX around 120V. The optimum gate
drive by using DGD is to drive down VG very strongly firstas shown in Fig.6(c). When VOV approaches the allowablemaximum, the gate current is reduced to a low level andthen is increased gradually to keep VOV at VOV,MAX asshown in the upper-right corner in Fig.6.
Fig. 7 shows the overall measured waveforms in theoptimized case using DGD. In Fig.7(b), the calculation
results using Eq.2 are also overlaid on the experimentalresults. It is seen that the theory well explains themeasurement results. In practice, the optimum waveform,
that is, the digital code pattern for DGD for the emergency
turn-off should be provided before the short circuit occurs.
This can be done by using theoretical calculation andexperiments using the device under consideration in thedevelopment phase of a system. Although there arevariations in parameters, the worst case occurs when VCC

is maximum, temperature is maximum and the VTH isminimum. The optimized drive waveform has nothing to
do with the collector current in the normal operation. Thus,
assuming the worst case condition, the unique optimized
waveform can be obtained, which means that this approachis practically executable.
V. CONCLUSIONSThe optimum gate drive waveform during theemergency turn-off of IGBT is analyzed andexperimentally verified by using Digital Gate Drive. 22%energy loss saving can be achieved over the conventional
resistor drive, which in turn reduces 22% temperature
increase of the IGBT, leading to the safer turn off. The
optimum gate control is to drive down VG strongly first
followed by a sudden fall of gate current and then to
gradually increase the gate current. The optimized IG
waveform for the emergency turn-off is different from thatfor the normal turn off in that much more precise control
in the gradual increase period is needed in the turn-off
since the VCE overshoot peak cutoff is critically important.
The theoretical base for this gradual control isestablished for the first time. In the modeling of IGBT, thecollector current of IGBT in the active region is found tofollow the alpha-power law, not the conventional squarelaw. The optimum control method can be applicable toother types of power devices such as power MOS devices,since the I-V characteristic in power MOS devices can alsomodeled by alpha-power law.
This type of technology becomes increasingly important3295

as the IGBT current density increases and the temperaturerise issue gets severer. In the future, when DGD is used ina normal switching of power devices, the same DGD canbe used in the case of emergency turn-off for free.
ACKNOWLEDGMENT
This work is supported by the New Energy andIndustrial Technology Development Organization(NEDO) of Japan.
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