IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 6, JUNE 2018

1139

Clocked Hysteresis Control Scheme With
Power-Law Frequency Scaling in Buck
Converter to Improve Light-Load
Efficiency for IoT Sensor Nodes
Chung-Shiang Wu , Student Member, IEEE, Makoto Takamiya, Senior Member, IEEE,and Takayasu Sakurai, Fellow, IEEE
Abstract— A clocked hysteresis control scheme with powerlaw frequency scaling is proposed to improve the conversion
efficiency at a light load current, and it is applied to a buckconverter design. By replacing a continuously on comparator
used in conventional hysteresis control by a clocked comparator
with power-law frequency scaling, the buck converter consumes
no direct current (dc) in the comparators. Almost flat efficiency
over a load current ranging from 500 nA to 20 mA is achieved.
In addition, a quick wakeup feature is maintained because of
the inherent hysteresis control. As for the theoretical aspect,
expressions for the frequency stability condition, power consumption, and output voltage ripple of the proposed power-law
frequency scaling scheme are derived and analyzed. A leakagebased digitally controlled oscillator, which consumes only 3.5 nW
when the frequency is 15 Hz for 500-nA load current, is designed
to provide a clock signal to the clocked comparator. Experimental
results show that the buck converter implemented with the powerlaw frequency scaling scheme achieves a 90.4% peak efficiency
and higher than 87% efficiency over a load current range from
500 nA to 20 mA.
Index Terms— Clocked hysteresis control (CHC), discontinuous
conduction mode (DCM) buck converter, hysteresis control,
power-law frequency scaling, wide-load-range buck converter.

I. I NTRODUCTION
ITH the rapid growth of Internet-of-Things (IoTs)
applications, demand for the development of wirelesssensor nodes is increasing. Many applications such as smart
cities/buildings, healthcare, and even those in industrial fields
require sensors operating for a long time without the need toreplace the battery. A direct current to direct current (dc–dc)
converter used in IoT sensor nodes to convert the battery
input voltage to a well-regulated output voltage for largescale integrated (LSI) circuits should provide a high conversion efficiency to prolong the battery lifetime. Unlike mobile
applications, the wireless sensors employed in IoT applications
stay in a sleep mode for most of the time and quickly wakeup to transmit data for only a short period of time. It has

W

Manuscript received September 13, 2017; revised December 20, 2017;
accepted January 25, 2018. Date of publication March 8, 2018; date of current
version May 22, 2018. (Corresponding author: Chung-Shiang Wu.)
The authors are with the Institute of Industrial Science, University of Tokyo, Tokyo 153-8505, Japan (e-mail: cswu@iis.u-tokyo.ac.jp;
mtaka@iis.u-tokyo.ac.jp; tsakurai@iis.u-tokyo.ac.jp).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2018.2806928

been shown by calculation [1] that the energy consumption of
the sleep mode is 10 times that of the active mode when thesleep current is 1 μA, as specified in the Bluetooth low energy(BLE) specifications [2]. Therefore, the conversion efficiency
in the sleep mode is becoming increasingly important to reduceoverall energy consumption.
Thus far, several commercial products and publications onbuck converters for IoT sensor node applications have beenreported. The conversion efficiency, however, degrades rapidly
when the load current decreases to microampere order [3].
A tri-mode buck converter consisting of a digital pulsewidthmodulation, a pulse-frequency modulation (PFM), and an
asynchronized mode (AM) [4] improves the conversion efficiency and extends the possible load range to 100 nA. The
conversion efficiency, however, is still lower than 80% when
the converter operates in the AM for a 1-μA load. An adaptive
application of bias current for analog circuits depending on
the loading conditions [5] improves the conversion efficiency
when the load current is low. The quiescent current in [5] wasas low as 110 nA with low output voltage ripple performance.
The conversion efficiency, however, was still limited to 78%
when the load current was 1 μA. In contrast, the buckconverter proposed in [6] achieved 87% conversion efficiency
at 1 μA, but it did not supply sufficient load current in an
active mode and did not support a fast wakeup operation
required for IoT applications.
For IoT applications, because of the low load current in asleep mode and a limited area for an inductor, the buck converter operating in a discontinuous conduction mode (DCM)
is required. There are two basic control schemes for a buckconverter operating in the DCM: constant-on-time (COT)
control and hysteresis control. These two schemes are shownin Fig. 1(a) and (b), respectively. In COT control [7], a highspeed comparator is employed to compare the output voltage
with a reference voltage VREF . A pulse signal with a fixed
pulsewidth is applied to the power stage triggered by thecomparator output signal. The output voltage is regulated
as VOUT = VREF , and the voltage error between VREF
and VOUT is monitored continuously. On the other hand,hysteresis control uses hysteresis comparators to regulate theoutput voltage within a designed hysteresis voltage window.
In addition, hysteresis control inherently provides a high1063-8210 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 6, JUNE 2018

Fig. 1. Conventional control schemes for buck converter operating in DCM.
(a) COT control. (b) Hysteresis control.

output voltage response speed when ILOAD changes [8]. This ispreferable, especially in IoT applications when a quick wakeup operation is required to conserve the energy of a system.
Both schemes, however, consume dc current because theyrequire continuously on comparators to monitor the output
voltage. A typical circuit schematic of the continuously oncomparator in Fig. 1(a) and (b) is shown in Fig. 2(a) [9], [10].
To clarify the power distribution of the typical hysteresis
buck converter shown in Fig. 1(b), a simulation assumingthat VIN is 3 V and VOUT is 1.6 V with a 20-mV hysteresis
voltage window and 1-μA bias current is conducted. Fig. 3(a)shows the power distribution in a sensor node in an activemode when ILOAD is 10 mA. In a sleep mode where ILOAD
is 1 μA, as specified by BLE, the power consumption of
the continuously on comparator accounts for 63% of thetotal power consumption, limiting the conversion efficiency
is only 34%, as shown in Fig. 3(b), even though the power
consumption of the reference voltage can be reduced to 10-nA
order [11].
To improve the conversion efficiency in the sleep mode,a clocked hysteresis control (CHC) buck converter with apower-law frequency scaling scheme is proposed in this paper.
Replacing the continuously on comparator used in conventional hysteresis control by a clocked comparator, as shownin Fig. 2(b) [12], the buck converter consumes no dc current in the comparators. The proposed power-law frequency
scaling scheme dynamically adjusts the clock frequency forthe clocked comparator depending on the load current tostabilize the output voltage. As a result, the comparator power
consumption becomes proportional to the load current. The
buck converter can achieve almost flat conversion efficiency
over the whole load current range specified by BLE while
inheriting a quick wakeup response of hysteresis control. This
paper is organized as follows. Section II describes the systemarchitecture of the proposed CHC buck converter employing a
power-law frequency scaling scheme operating in DCM. The
power-law frequency scaling scheme, including the frequency
stability, the output voltage ripple, and the effect of the load
fluctuation, is analyzed in Section III. Circuit implementations
are illustrated in Section IV. Experimental results are shownin Section V. Finally, conclusion is presented in Section VI.
II. S YSTEM A RCHITECTURE
A system block diagram of the proposed CHC buck converter is shown in Fig. 4. The target input voltage ranges

Fig. 2.
Circuit schematic and symbol of comparator. (a) Continuously
on comparator. (b) Clocked comparator. (c) Power-gated comparator. (This
topology is used in Fig. 4.)

from 2.4 to 3.3 V, allowing it to be a battery-based system.
The output voltage is set to be 1.5–1.6 V to power LSI
circuits in sensor nodes with BLE communication. For typicalsensor node applications, the buck converter operates in DCM
because of the low load current while using an inductor withsmall inductance. Compared with the conventional hysteresis
buck converter, the continuously on comparator is replaced bya clocked comparator X1 . Comparators X2 and X3 are powergated comparators whose circuit schematic and symbol are
shown in Fig. 2(c). We note that for X3 , a topology consistingof a pMOS input differential pair with an nMOS active load isWU et al.: CHC SCHEME WITH POWER-LAW FREQUENCY SCALING IN BUCK CONVERTER

1141

Fig. 3. Simulated power dissipation of typical hysteresis buck converter in
active and sleep modes. (a) Active mode. (b) Sleep mode. PCONDUCTION and
PSW denote the conduction and switching losses of the converter, respectively.
PVREF denotes the power consumption of a reference voltage generator VREF .
Fig. 5. (a) Operating timing diagram and relative control signals in CHC
buck converter. (b) Load wakeup operation.

Fig. 4. System block diagram of the proposed CHC buck converter withpower-law frequency scaling scheme.

applied because X3 compares VX with ground. Using an enable
signal, X2 and X3 are turned ON in a short period of time inevery switching cycle. The bias points of the current mirror
and the output are reset to ground and logic “1,” respectively,by the enable signal EN. Therefore, no dc current is consumed
when the comparators are disabled. X1 and X2 are designed
to regulate VOUT within a hysteresis voltage window specified
by voltage references VMAX and VMIN . The dependence of theoutput voltage ripple on the hysteresis voltage window will be
discussed in Section III. In addition, comparator X3 is usedfor zero-current detection (ZCD), preventing reverse inductor
current loss. X3 compares V X with ground and generates asignal to turn OFF the nMOS power transistor M N when
the inductor current reaches zero. An analog-type comparator
is necessary because X2 and X3 should operate sufficiently
quickly to reduce the output voltage ripple and to prevent
reverse inductor current, respectively. Since there is no needfor X2 and X3 to be turned ON all the time, they are activatedfor a short time when the enable signal for each comparator
is ON.
A leakage-based digitally controlled oscillator (DCO) is
implemented to provide a clock signal VCLK to X1 . The
frequency of VCLK , f CLK , can be adjusted from 20 f CLK,MIN
to 221 f CLK,MIN by 22-bit clock frequency control signals
named FCLK_CTRL [21:0], where f CLK,MIN denotes the lowest clock frequency. FCLK_CTRL [21:0] are provided by afield-programmable gate array (FPGA) for an experiment but
can easily be implemented on a chip. The power-law frequency
scaling scheme is implemented by the FPGA. VCLK and theoutput signal of X1 , VOUT_LOW , are applied to the FPGA togenerate FCLK_CTRL . If f CLK is too slow considering the loadcondition, FCLK_CTRL is increased by 1 bit, making f CLKdouble. On the other hand, if f CLK is too fast for the loadcondition, FCLK_CTRL is decreased by 1 bit, making f CLK ahalf. The exact meanings of “too slow” and “too fast” aredescribed later. Therefore, f CLK is controlled in accordancewith the load conditions. Only basic logic elements are usedon the FPGA. By a simple calculation [13], the employed gate
count on the FPGA is about 700 gates, which consume lessthan 1 nW when ILOAD is 500 nA, f CLK is 15 Hz, and VIN
is 3 V, which is negligible compared with the power loss in asleep mode.
Fig. 5(a) shows the operating timing diagram of the proposed CHC buck converter. When VOUT becomes lower than
VMIN , which is detected by X1 , VOUT_LOW is logic “1” andpMOS power transistor MP is turned ON, which conducts an
inductor current and charges up the output voltage. At thesame time, comparator X2 is enabled and starts comparing
VOUT with VMAX . Once VOUT reaches VMAX , MP is turned
OFF and nMOS power transistor MN is turned ON . The
turn-ON signal for MN is also used to disable X2 andenable X3 . MN is turned OFF when the inductor current reaches
zero, which is detected by the ZCD comparator X3 . X3 isdisabled automatically when MN is turned OFF. X2 and X3 areturned ON during TON,X2 and TON,X3, respectively, in every
power stage switching period TSW . Therefore, applying the
proposed control scheme, comparators X1 , X2 , and X3 are all“clocked” and consume no dc power.
The conduction and switching losses in the buck converter
are estimated as follows:
Pconduction = I L2 ,RMS · (R DS,ON + RESR )(1)

2
Pswitching = α · f SW · CTOTAL · VIN(2)

where IL,RMS is the root mean square of the inductor current,
RDS,ON is the ON resistance of power transistors MP and MN ,RESR is the equivalent series resistance of the inductor,
f SW is the switching frequency of the power stage, VIN is the1142IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 6, JUNE 2018

input voltage, CTOTAL is the total capacitance at the gates of
MP and MN , and α is the average activity factor. In addition,
the power consumption of X2 and X3 can also be estimatedas TON,X2,3
1
Pcomp.,X2,3 =VIN I (t) dt
(3)
TSW 0
where 1/TSW is the switching frequency of the power stagef SW , TON,X2, and TON,X3 are the turn-ON time of comparators
X2 and X3 , respectively, and I (t) is the current consumed
by the comparator. As indicated in (1)–(3), by adopting PFM
in DCM operation, the conduction loss, switching loss, andpower consumption of X2 and X3 can be scaled with ILOAD
because all of them are proportional to f SW . The power consumption of clocked comparator X1 , however, is proportional
to the clock frequency f CLK . An appropriate clock frequency isrequired to regulate the output voltage while keeping the power
consumption of X1 low. Using a higher clock frequency resultsin higher power consumption of X1 and the controller circuits,thus losing the benefit of using the clocked comparator. On theother hand, applying a lower clock frequency induces a large
voltage ripple at VOUT . A power-law frequency scaling scheme
is proposed to adjust the clock frequency fCLK in the CHC
buck converter, making fCLK also proportional to ILOAD.
Therefore, the conduction loss and switching loss of the powerstage, and the controller power consumption including thecomparators are all scaled with ILOAD. Thus, the CHC buckconverter can achieve almost flat conversion efficiency over awide range of loads including a sleep mode.
For IoT sensor node applications, the buck converter must
support quick wakeup operation when the system operation
changes from a sleep mode to an active mode. The wakeup
operation of the CHC buck converter is illustrated in Fig. 5(b).
The load current as the wakeup threshold can be set depending
on applications for power and output voltage drop optimization. When the system is woken up, an external wakeup
signal WAKE_UP synchronized with a change in ILOAD isapplied to the FPGA or a controller on the chip if the logic is
implemented on a chip. The current frequency control bits,
FCLK_CTRL [21:0], are reset by WAKE_UP, making fCLK
changes from the current frequency f 1 to the highest frequency
f CLK,MAX , that is, 221 f CLK,MIN . With the proposed frequency
scaling scheme, the clock frequency f CLK gets half andhalf step by step, and automatically settles to a new value
f 2 according to the loading condition. Therefore, the buckconverter can achieve fast wakeup operation.
III. P OWER -L AW F REQUENCY S CALING S CHEME
A flowchart of the proposed frequency scaling scheme isshown in Fig. 6. At the start of the control, the clock frequency
f CLK is set to the highest value, 221 fCLK,MIN , and the VOUT
checking counter implemented on the FPGA is reset to 0.
If VOUT >VMIN at the clock edge, meaning that VOUT_LOW
is logic “0,” the counting number n increases by 1, and theprocess restarts. On the other hand, if VOUT <VMIN at the clockedge, VOUT_LOW is logic “1,” making the buck converter starts
a new switching cycle. At the same time, the counter number

Fig. 6.
scheme.

Frequency control flowchart of the proposed frequency scaling

TABLE IF REQUENCY S CALING OF f CLK AND D EPENDENCE OF f CLK ON ILOADE XPRESSED U SING n, n 1, AND n 2

n is read out and compared with two preset boundaries, n 1
and n 2 , where n 2 > n 1 . n≤n 1 indicates that the output voltage
VOUT crosses VMIN earlier than expected, that is, ILOAD ishigh but the clock frequency f CLK is too low. MP should
be turned ON frequently to transfer energy from VIN to
VOUT . Therefore, fCLK is multiplied by m 1 and the algorithm
restarts. n> n 1 and n>n 2 mean that f CLK is too high. Clocked
comparator X1 checks VOUT several times and turns ON MP
only once. In this case, fCLK is divided by m 2 . This process
operates continuously, and the VOUT checking counter number
n settles to a value larger than n 1 and smaller than n 2 , i.e.,n 2 >n> n 1 . In the steady state, an appropriate f CLK is foundby the proposed power-law frequency scaling scheme thatcan stabilize the output voltage of the buck converter, andf CLK is a multiple of the switching frequency fSW . Therefore,
the power consumption of X1 is also proportional to ILOAD
because fCLK is proportional to f SW . These three conditionsof n including the frequency scaling and the relation between
f CLK and ILOAD are summarized in Table I. An example
of implementation showing the output waveform, the clock
signal, VOUT_LOW , and the VOUT checking counter n in thetime domain when m 1 = m 2 = 2, n 1 = 2, and n 2 = 5
is illustrated in Fig. 7. In Fig. 7(a), VOUT is lower than VMIN
when n = 2 ≤ n 1 in the first switching period. This is the casewhen the initial f CLK is too low possibly generating a larger
output voltage ripple. Thus, f CLK is doubled (×m 1 ). On theWU et al.: CHC SCHEME WITH POWER-LAW FREQUENCY SCALING IN BUCK CONVERTER

1143

Fig. 8.
Simulated dependence of power consumption of comparators(X1 , X2 , and X3 ) on f SW and ILOAD .

Fig. 7. (a) When the initial f CLK is too low, f CLK is doubled. (b) Whenthe initial f CLK is too high, f CLK is halved.

other hand, when the initial f CLK is too high, VOUT is lower
than VMIN when n>n 2 , resulting in the consumption of more
power than appropriate, which is the case shown in Fig. 7(b).
f CLK becomes halved (÷m 2 ) to reduce the power consumptionof the comparator. In Sections III-A–III-C, the design parameters that make the CHC buck converter works properly are
determined. Then, the frequency stability, the output voltage
ripple, and the effect of the load current fluctuation on VOUT
are derived theoretically.
A. Frequency Multiply/Divide Ratio Decision
Parameters m 1 , m 2 , n 1 , and n 2 illustrated in Fig. 6 should
be determined to make the frequency scaling scheme operates
properly. As indicated by Fig. 6, fCLK can be expressed aswhere N is also a natural number. As indicated by (5),any natural numbers m 1 , m 2 , and γ can be chosen for the
power-law frequency scaling scheme. A higher m 1 results ina high tracking speed for the ILOAD wakeup operation, butdissipates more power in every frequency transition. On theother hand, a higher m 2 can reduce power consumption
during the transient. However, according to the analysis in
Section III-C, a higher value of m 2 rapidly reduces the clock
frequency, which induces a large output voltage drop andan unacceptable output voltage ripple. Therefore, except 1,
the minimum value of a natural number, 2, is chosen form 2 , resulting in frequency scaling of 2 N . Depending on theapplication, m 1 can be designed to be 8 or higher for a highresponse speed of load changing. In a sleep mode, however,a minimum value of 2 is designed for m 1 to reduce the power
overhead. The combination of (m 1 , m 2 ) = (2, 2) results indouble-half-frequency scaling [14], which is a special case in
the proposed power-law frequency scaling scheme.
n 1 and n 2 should be designed to prevent f CLK oscillation
between f CLK × m 1 and f CLK ÷ m 2 . The constraints on n 1
and n 2 can be represented as
1
> n1
m2
n1 × m 1 > n2.

n2 ×

(7)
(8)

Therefore, fCLK is stable between n 1 and n 2 , and its relation
with fSW in the steady state can be expressed asq

f CLK =

m1

p f CLK,MIN

m2
γm1 = m2(4)

f CLK = K × f SW

(5)

where K is a natural number and a function of n 1 and n 2 . f CLK
is determined by the power-law frequency scaling scheme
according to the load conditions, making the CHC buck converter able to operate stably without f CLK oscillation. Under
the same ILOAD condition, choosing a larger value of K results
in a higher fCLK . An additional benefit here compared with aconventional hysteresis control is that the switching frequency
f SW is fixed to 1/K · fCLK . Using the frequency scaling
scheme, the power consumption of the clocked comparator
can be adjusted to be proportional to ILOAD. The simulated
dependence of the power consumption of X1 , X2 , and X3 on
f CLK when K = 3 is shown in Fig. 8. Obviously, the power
consumption of X1 , X2 , and X3 can all be scaled with ILOAD.

where p and q denote the corresponding decision cycles andm 1 , m 2 , p, and q are natural numbers. Considering thatthe frequency scaling scheme may induce harmonics thatinterfere with other sensitive circuits such as RF blocks on
the same chip, the relation between m 1 and m 2 is expressedas (5), where γ is designed as a natural number, that is, larger
than or equal to 1. Therefore, the harmonics generated by
the frequency scaling scheme are located at integral multiples
of fCLK,MIN in the frequency spectrum. Replacing m 1 in (4)by (5), f CLK can be expressed as
fCLK = m 2N f CLK,MIN ,N = γq − p

(6)

(9)

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 6, JUNE 2018

Fig. 10. Simulated and calculated TSW and IPEAK by (13) and (14) under
different load conditions.
Fig. 9. Inductor current and output voltage waveforms. (a) Conventional
hysteresis buck converter. (b) Proposed CHC buck converter with clock timing.

B. Analysis of Output Voltage Ripple
By applying the proposed power-law frequency scaling
scheme in the CHC, the buck converter employs no continuously on comparators, resulting in no consumption ofdc current by the comparators. The output voltage ripple
VOUT,RIPPLE , however, is enlarged because comparator X1
only compares the output voltage with VMIN at the clockedge. In addition, the “real” minimum output voltage level
VOUT,MIN , which is lower than VMIN , should be analyzed toensure that the lowest output voltage level is not lower than
the specification value. By the proposed theoretical analysis,design guidelines for VMAX and VMIN are provided so that
the CHC buck converter can achieve competitive performancewith a conventional buck converter while improving the conversion efficiency in a sleep mode.
To analyze the voltage ripple of the CHC buck converter,
the voltage ripple of conventional hysteresis control is derived
first. The inductor current waveforms IL , ILOAD, and VOUT
for a conventional hysteresis control buck converter are illustrated in Fig. 9(a). IPEAK is the peak inductor current value,
VMAX − VMIN is the hysteresis window, denoted by VHYS , andILOAD is the load current. Because of the time delay between
the inductor current and the output voltage, the maximum and∗∗ , areand VMIN
minimum output voltages, denoted by VMAX
higher and lower than VMAX and VMIN , respectively. There∗∗
fore, VMAX− VMIN
represents the output voltage ripple. Whenthe output capacitor equivalent series resistance is neglected
for simplicity, the peak inductor can be expressed as [15]2+ 2COUT α1 VHYS
(10)
IPEAK = ILOAD + ILOAD
where α1 = (VIN − VOUT )/L and VHYS = VMAX − VMIN .
Using charge balance analysis [16] in combination with (10),the output voltage ripple can be expressed in terms of only
the given specification parameters of the system such as VIN ,VOUT , VHYS , L, COUT , and ILOAD
VOUT,RIPPLE = 2
 VIN 1ILOAD + 2COUT α1 VHYS.
2C OUT
VOUT α1(11)
1

A similar equation can also be found in [17] although it
involves the switching period and cannot refer to the specification parameters directly.
For IoT sensor node applications, the maximum ILOAD
usually ranges from milliampere to 10-mA order. In this case,2
the 2COUT α1 VHYS term in (10) is much larger than ILOAD
term when a microfarad output capacitor and a microhenry
inductor are applied. Therefore, (11) can be simplified to
VOUT,RIPPLE(0) = VHYS ×

VIN
.
VOUT

(12)

Equation (12) provides a simple estimation of the output
voltage ripple that is only dependent on VIN , VOUT , and VHYS .
Equation (12) is defined as the intrinsic output voltage ripple ofa hysteresis buck converter, indicating the theoretical minimum
output ripple that it can achieve. In addition, the switching
period TSW and IPEAK can also be simplified as follows when√
2COUT α1 VHYS > ILOAD:
VIN
COUT
VHYS
I
VOUT
LOAD
IPEAK = 2COUT α1 VHYS .
TSW =

(13)
(14)

Equations (12)–(14) can be used to calculate the output
voltage ripple, switching period, and peak inductor current
very simply when the load current is relatively small comparedwith IPEAK , which is the usual case in IoT applications.
The values of TSW and IPEAK calculated by (13) and (14)compared with simulation results under different ILOAD are
shown in Fig. 10. Equations (13) and (14) match the simulation
results well and provide a simple means of calculating TSW
and IPEAK for a conventional hysteresis buck converter when
ILOAD is much lower than IPEAK . In addition, on the basisof (12)–(14), the voltage ripple of the proposed CHC buckconverter can be calculated.
Fig. 9(b) shows the inductor current waveform IL , ILOAD,
VOUT , and the clock signal VCLK when CHC is applied.
The clocked comparator compares VOUT and VMIN at every∗ , howclock edge. The effective hysteresis window VHYS
ever, is enlarged by a limited clock frequency f CLK and
K as indicated by (9). The worst case of VOUT,RIPPLE
is when the clock arrives but VOUT is slightly higher∗
than VMIN . Therefore, VHYS
is effectively enlarged by a factorWU et al.: CHC SCHEME WITH POWER-LAW FREQUENCY SCALING IN BUCK CONVERTER

Fig. 11. Simulated and calculated dependences of output voltage ripple on
clock frequency f CLK . (a) ILOAD = 10 mA. (b) ILOAD = 100 μA.

of TOSC × ILOAD/COUT . Therefore, VOUT,RIPPLE can be calculated as
VIN
ILOAD
VOUT,RIPPLE (CHC) =(VHYS +TCLK ). (15)
VOUT
COUT
The calculated and simulated dependences of VOUT,RIPPLE
on f CLK , including the simulated K under VIN = 3 V, VOUT =1.6 V, VHYS = 20 mV, COUT = 1 μF, L = 4.7 μH, andILOAD = 10 mA and 100 μA, are shown in Fig. 11(a) and (b),respectively. When f CLK is closed to the switching frequency
f SW calculated by (13), the output voltage ripple increases
steeply. On the other hand, when a higher f CLK is applied,
VOUT,RIPPLE becomes smaller and close to the intrinsic output
voltage ripple calculated by (12) at the cost of higher power
consumption.
C. V OU T ,R I P P L E and V OU T ,M I N Under I L O AD Fluctuation
The lowest output voltage level VOUT,MIN and the maximum voltage ripple VOUT,RIPPLE of the proposed CHC
buck converter under time-dependent ILOAD fluctuation should
be calculated. Unlike a conventional buck converter only
depending on the output capacitor and the converter loop bandwidth, f CLK and K determine VOUT,MIN and VOUT,RIPPLE.
Considering that the ILOAD fluctuation is not sufficiently
large to change f CLK to m 1 × f CLK , a large value of K is
required to keep the minimum output voltage level above thesystem specifications. Equation (15) gives the worst ripple
voltage, and K is determined by preset numbers n 1 and n 2 .
Fig. 12(a) and (b) shows the simulated dependences of1145

Fig. 12. Simulated and calculated output voltage ripple for ILOAD with afluctuation varying from 5% to 30% in a stepped manner with different valuesof K . (a) ILOAD = 10 mA. (b) ILOAD = 100 μA.

the output voltage ripple performance of the proposed
CHC buck converter on K under ILOAD = 10 mA and100 μA, respectively. The load current is assumed tohave a fluctuation of up to 30%. The calculation results
obtained from (15) and a PFM control with an adaptive
on-time buck converter [18] are also illustrated in Fig. 12(a)and (b) for comparison. The simulation is carried out with
VIN = 3 V, VOUT = 1.6 V, VHYS = 20 mV, L = 4.7 μH, and
COUT = 1 μF. A larger value of K indicates that a higher f CLK
is applied as shown in Section III-A. When K = 2, the output
voltage is easily affected by load fluctuation. In addition, whenK = 3, the CHC buck converter achieves competitive voltage
ripple performance with the adaptive on-time control buckconverter. Applying K = 5, the voltage ripple of the CHC
buck converter is lower than that of the conventional one
when the ILOAD fluctuation varies from 5% to 30%. Therefore,
K = 3 is chosen for low-power consumption with acceptable
output voltage ripple.
To ensure that the minimum output voltage is higher than thevalue specified by the system, the lower bound of the voltage
hysteresis window VMIN should be designed so that is satisfies
VOUT,MIN (CHC) = VMIN −

ILOAD
QL
TCLK −
COUT
COUT

(16)

where Q L can be expressed as
ILOAD ×t D
ILOAD ×L
, tD =(17)
2
VIN − VOUT
and the comparator delay is neglected for simplicity. When
ILOAD is 10 mA, VIN = 3 V, and VOUT = 1.6 V,
QL =

1146

Fig. 13.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 6, JUNE 2018

Circuit schematic of the leakage-based DCO.

VMIN = 1.57 V gives the CHC buck converter with aminimum output voltage no lower than 3.4% of VOUT , and
VOUT,RIPPLE < 6% of VOUT when K = 3. Therefore,
the design parameters m 1 = m 2 = 2, n 1 = 2, andn 2 = 5, resulting in K = 3, which is the case shown in
Fig. 7(a) and (b), are chosen to implement the proposed CHC
buck converter.
IV. C IRCUIT I MPLEMENTATION
A. Leakage-Based Digitally Controlled Oscillator (DCO)
An on-chip DCO is implemented to provide a clock signal
to the clocked comparator X1 . The clock frequency is able tobe controlled digitally using a factor of 2 and ranges from hertz
to megahertz order for both active and sleep modes. A circuit
schematic of the DCO is shown in Fig. 13. As the DCO is the
only continuously on circuit block in the CHC buck converter,
the power consumption should be minimized so that it does
not limit the sleep mode conversion efficiency. The transistor
leakage current is designed as the bias current provided to thecurrent mirror. The 4-bit signals A [3:0] are used to control
the transistor size of MP and the leakage current according to
the process, voltage, and temperature (PVT) variation. A [3:0]
can be generated by additional calibrations or implementing
a PVT sensors on a chip [19], [20]. This current is mirrored
to charge and discharge the capacitors, generating a sawtooth
voltage waveform. A current-starved Schmitt trigger is used as
a comparator and output buffer so that there is no need to usean additional reference. Therefore, a square clock waveform
can be obtained at the output of the Schmitt trigger. The
frequency tuning is separated to control both the transistor
multiplier ratio and the number of capacitors. The 22-bit
thermometer codes, FCLK_CTRL [21:0], are used to adjust theclock frequency monotonically over a frequency tuning rangeof 106 . In addition, stacked transistor technology is employed
to design MN1 to dramatically reduce the transistor area.
Therefore, the MSB nMOS transistor multiplier ratio can be
reduced to 2048, which can be implemented on a test chip.
To reduce the oscillator power consumption, a supply
VDD,OSC with a lower voltage is preferred. A bootstrap circuit employing the concept in [21] is designed to boost thevoltage level of VOUT when the Schmitt trigger is switching.
Therefore, switches SN and SP can be fully turned ON tocharge and discharge the capacitor even when VDD,OSC is as

low as 0.6 V. An additional low-dropout regulator (LDO) or aswitched capacitor (SC) dc–dc converter can be employed togenerate this supply voltage. The measurement results showthat the DCO consumes only 5.6 nA at 15 Hz and 50.4 μA
at 6 MHz when VDD,OSC is 0.6 V. Therefore, it is possible
to design the LDO or the SC dc–dc converter [22] on a chipwith high conversion efficiency and a compact area although
this has not been implemented in the current design.
The frequency scaling scheme applied to the DCO may
generate interference that interferes with sensitive circuits on
the chip. In the sleep mode, however, the clock frequency
is only 10-Hz order, which is far from the usual RF signal
frequency. In addition, there are no RF circuits enabled in thesleep mode. On the other hand, in the active mode, a system
clock with a higher frequency, for example, 32 MHz, canbe applied as a base frequency for the power-law frequency
scaling scheme instead of using the internal leakage-based
DCO.
B. Clocked Comparator and Analog Comparator With
Enable Signal
A circuit schematic of clocked comparator X1 is shownin Fig. 2(b). A clocked comparator with a latch load [14] isemployed to compare VOUT with VMIN . The output followed
by a D flip-flop generates a control signal to turn ON the powertransistor MP . The input differential pair is designed with alarge transistor width and length to reduce the offset voltage.
The 1-sigma simulated and calculated offset voltages [23] areless than 2 mV, which does not have a large effect on thevoltage hysteresis window.
Fig. 2(c) shows a circuit schematic of the power-gatedcomparator with an enable signal. Comparator X2 compares
VOUT with VMAX , and is enabled when VOUT is lower than
VMIN and turned OFF when VOUT becomes higher than VMAX .
Similarly, a p-type input differential pair with an nMOS active
load power-gated comparator is designed for X3 because thecomparator compares the VX node with the ground. X3 isturned ON when VOUT becomes higher than VMAX and turned
OFF when the inductor current reaches zero. The settling time
due to the enable signal in the comparators is not an issue
because the bias points in the comparators only need to settle
in a time of 100-ns order. To demonstrate the benefit of the
proposed CHC, the power distribution of the comparators issimulated. The simulation shows that the power consumptionsof X1 , X2 , and X3 are all lower than 1% of the output power
when applying f CLK = 100 Hz under ILOAD = 1 μA.
C. Voltage Level Shifter
The proposed CHC buck converter targets BLE applications
for which the input voltage could be a battery with a voltage
ranging from 2.4 to 3.3 V. However, a lower supply voltage
is preferred for the leakage-based DCO to reduce the power
consumption. A conventional level shifter with a short current
reduction topology [24] cannot convert a clock signal with alow voltage such as 0.6–3.3 V when the clock frequency isin the megahertz order. Fig. 14 shows the designed voltage
level shifter. An auxiliary bootstrap circuit is designed toWU et al.: CHC SCHEME WITH POWER-LAW FREQUENCY SCALING IN BUCK CONVERTER

1147

Fig. 14. Schematic of the voltage level shifter, which converts 0.6–3.3 V
with the frequency ranging from 1 Hz to 5 MHz.

Fig. 16.
Measured waveforms of VOUT , VCLK , and VOUT_LOW under
different loading conditions. (a) VIN = 3 V, VOUT = 1.6 V, VHYS = 20 mV,
and ILOAD = 100 μA. (b) VIN = 3 V, VOUT = 1.6 V, VHYS = 20 mV, andILOAD = 2 mA.

Fig. 15.

Chip micrograph of the proposed CHC buck converter.

boost the amplitude of the input clock signal VCLK to nearly
2VDD,OSC (∼1.2 V), and the voltage level shifter can shiftVCLKM to VCLKH functionally. The worst case is when theclock frequency is low. In this case, the bootstrap circuit cannot
boost the input voltage for a long period. Simulation results
show that the voltage level shifter can convert the input signal
from 0.6 to 3.3 V when the frequency ranges from 1 Hz to
5 MHz. The voltage level shifter consumes 380 pW at 1 Hz
and 44.5 μW at 5 MHz.
V. E XPERIMENTAL R ESULTS
The proposed CHC buck converter implemented with the
double-half-frequency scaling scheme (m 1 = 2 and m 2 = 2)
is fabricated by a 0.18-μm standard CMOS process for verification. I/O transistors are used to design buck convertercore circuits that should withstand an input voltage of 3.3 V,
and switches providing a low leakage current. Fig. 15 shows
the chip micrograph. The active area including the buckconverter core circuits, leakage-based DCO, voltage level
shifter, and buffers is 0.71 mm2 . The test chip is measured
with a 4.7-μH off-chip inductor and a 1-μF off-chip capacitor, and the frequency scaling scheme is realized using an
Altera Cyclone V FPGA. Fig. 16(a) and (b) shows thesteady-state waveforms of VOUT , VCLK , and VOUT_LOW under
VIN = 3 V, VMIN = 1.57 V, and VMAX = 1.59 V when
ILOAD = 100 μA and 2 mA, respectively. The voltage
hysteresis window VHYS is set to 20 mV for all measurements.
The frequency scaling scheme is designed to minimize thepower consumption of the comparator and controller. Therefore, n 1 = 2 and n 2 = 5 are used, resulting in K = 3
in (9). As shown in Fig. 16, the pMOS power transistor MP
is turned ON every three VCLK clock cycles. As discussed
in Section III, m 1 , m 2 , n 1 , and n 2 can be changed easily
according to the specifications for different applications, suchas a high wakeup response speed or a low output voltage
ripple. The measurement results show that the output voltage
is regulated at 1.6 V with a voltage ripple lower than 100 mV,
which is about 6% of the output voltage. Using the frequency
scaling scheme, the clock frequency of VCLK automaticallysettles to 3.57 and 94 kHz when ILOAD = 100 μA and 2 mA,
respectively.
To verify the load wakeup operation, ILOAD changed from
30 μA to 2 mA is applied to the output. The signal WAKE_UP
resets the clock frequency to the highest value, and the clock
frequency is settled in the steady state by the frequency
scaling scheme as shown in Fig. 17(a). Fig. 17(b) shows thedetailed waveforms of VOUT , VCLK , and WAKE_UP. The clock
frequency changes from 780 Hz to 55 kHz at 2-mA loading
without an obvious voltage drop.
Fig. 18 shows the measured clock frequency and power
consumption versus FCLK_CTRL [21:0] for the leakage-based

1148IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 6, JUNE 2018

Fig. 19. Measured conversion efficiency and clock frequency f CLK versus
ILOAD and comparison with state-of-the-art low-power buck converters.
TABLE IIP ERFORMANCE S UMMARY OF THE P ROPOSED CHC B UCK C ONVERTERAND C OMPARISON W ITH S TATE - OF - THE -A RT B UCK C ONVERTERS

Fig. 17. Measured load wakeup operation when ILOAD is changed froma sleep mode (30 μA) to an active mode (2 mA). (a) Time scale = 10 ms.
(b) Time scale = 100 μs.

Fig. 18. Measured clock frequency and power consumption relationship forthe proposed DCO in Fig. 13 when digital bit of FCLK_CTRL is changed.

DCO. The clock frequency is controlled by a 22-bit thermometer code with 16 bits in the transistor multiplier ratio
and 6 bits in the capacitor bank. Three chips are measured,showing that the frequency can be adjusted monotonicallywithout large frequency and power variations. Upon applying
a 0.6-V supply voltage, the DCO consumes 3.4 nW and
30.2 μW when the clock frequency is 15 Hz and 6.3 MHz,
respectively. In addition, the DCO power consumption is also

proportional to the loading current because the frequency
is mainly controlled by the transistor multiplier ratio in thecurrent mirror. The power distribution of the DCO accounts forless than 1% of the output power of the CHC buck converter
when operating in both the sleep and the active modes.
The measured dependence of the efficiency and clock
frequency f CLK on the load current is shown in Fig. 19.
The proposed CHC buck converter achieves almost flat conversion efficiency by removing continuously on comparators and applying the double-half-frequency scaling scheme.
The frequency scaling scheme is also verified on the
y-axis on the right-hand side of Fig. 19. Higher than 87%
conversion efficiency is achieved over a load current ranging
from 500 nA to 20 mA. When ILOAD = 1 μA, which isdefined as the sleep current in BLE, efficiency is improved by
12%–34% compared with that of state-of-the-art low-powerbuck converters. A comparison of performance with state-ofthe-art buck converters is shown in Table II. The proposed
CHC buck converter achieves higher than 87% conversion efficiency over 500 nA–20 mA with a peak efficiency of 90.4%.
In addition, compared with the state-of-the-art buck converters,a higher efficiency at 1 μA is also achieved. The input
voltage, output voltage, and loading current are designed forWU et al.: CHC SCHEME WITH POWER-LAW FREQUENCY SCALING IN BUCK CONVERTER

BLE applications. CHC with the double-half-frequency scaling
scheme was also proposed to remove the continuously oncomparators in the conventional hysteresis buck converter. The
frequency scaling scheme is also suitable for other convertersthat employ continuously on comparators.
VI. C ONCLUSIONA CHC buck converter operating in DCM with a powerlaw frequency scaling scheme is developed to remove thecontinuously on comparators used in conventional hysteresis
control, resulting in no dc current being consumed by thecomparators. The frequency of the clocked comparator isdynamically adjusted in accordance with the load conditions.
Therefore, the conduction loss, switching loss, and comparator
power consumption in the converter can all be scaled withthe load. By applying the proposed topology, the CHC buckconverter achieves almost flat conversion efficiency over theentire load current range. The frequency stability, output
voltage ripple, and minimum output voltage level of the buckconverter when the power-law frequency scaling scheme isapplied are analyzed to provide design guidelines for thesystem. A CHC buck converter with the double-half-frequency
scaling scheme is implemented to verify the power-law frequency scaling. Experimental results demonstrate that the buckconverter achieves conversion efficiency of higher than 87%
over ILOAD ranging from 500 nA to 20 mA with a peak valueof 90.4%. The conversion efficiency is particularly improved
when ILOAD is 1 μA. The ILOAD wakeup operation with thefrequency scaling scheme is also verified. The proposed buckconverter achieves high conversion efficiency in a sleep modewith a quick wakeup response, making it extremely suitablefor IoT sensor node applications.
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[5] D. Lu, S. Yao, and B. Shao, “A 110nA quiescent current buck converterwith zero-power supply monitor and near-constant output ripple,” inProc. IEEE Custom Integr. Circuits Conf. (CICC), Sep. 2015, pp. 1–4.
[6] D. El-Damak and A. P. Chandrakasan, “Solar energy harvesting systemwith integrated battery management and startup using single inductorand 3.2 nW quiescent power,” in Proc. IEEE Symp. VLSI Circuits,Jun. 2015, pp. 280–281.
[7] C. Ni and T. Tetsuo, “Adaptive constant on-time (D-CAPTM) control
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[9] G. A. Ricon-Mora, “Accurate, fast, and user programmable hysteretic
comparator,” U.S. Patent 6 229 350 B1, May 8, 2001.
[10] F. Su, W.-H. Ki, and C.-Y. Tsui, “Ultra fast fixed-frequency hysteretic
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1149[11] T. Someya, K. Matsunaga, H. Morimura, T. Sakurai, and M. Takamiya,“56-Level programmable voltage detector in steps of 50mV for battery
management,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC),
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[12] S. Babayan-Mashhadi and R. Lotfi, “Analysis and design of a lowvoltage low-power double-tail comparator,” IEEE Trans. Very Large
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[13] National Instruments. FPGA Fundamentals. Accessed: May 2012.
[Online]. Available: http://www.ni.com/white-paper/6983/en/#[14] C.-S. Wu, M. Takamiya, and T. Sakurai, “Buck converter with higher
than 87% efficiency over 500 nA to 20 mA load current range for
IoT sensor nodes by clocked hysteresis control,” in Proc. IEEE Custom
Integr. Circuits Conf. (CICC), Apr./May 2017, pp. 1–4.
[15] W. Fu, S. T. Tan, M. Radhakrishnan, R. Byrd, and A. A. Fayed,“A DCM-only buck regulator with hysteretic-assisted adaptive
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[23] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis andDesign of Analog Integrated Circuits, 4th ed. New York, NY, USA:
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Chung-Shiang Wu (S’14) received the B.S. degree
in power mechanical engineering and the M.S.
degree in electronics engineering from National
Tsing Hua University, Hsinchu, Taiwan, in 2007 and2009, respectively. He is currently working toward
the Ph.D. degree in electrical engineering and information systems at the University of Tokyo, Tokyo,
Japan.
From 2013 to 2015, he was a Project Researcher
at the National Chiao Tung University, Hsinchu,
Taiwan, where he conducted research on power
management and energy harvesting integrated circuits. In 2016, he joined ON
Semiconductor, Tokyo, Japan, and in 2017, the IBM T. J. Watson ResearchCenter, New York, NY, USA, as an intern. His current research interests
include power management and energy harvesting ICs, low-power mixedsignal circuits, and isolated power supply for power-electronic gate drivers.

1150

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 6, JUNE 2018

Makoto Takamiya (S’98–M’00–SM’14) received
the B.S., M.S., and Ph.D. degrees in electronics
engineering from the University of Tokyo, Tokyo,
Japan, in 1995, 1997, and 2000, respectively.
In 2000, he joined NEC Corporation, Tokyo,
Japan, where he was engaged in the circuit design ofhigh-speed digital large-scale integration. In 2005,
he joined the University of Tokyo, where he iscurrently an Associate Professor at the VLSI Design
and Education Center. From 2013 to 2014, he wasa Visiting Scholar at the University of California,
Berkeley, CA, USA. His current research interests include the integrated power
management circuits for the ultralow-power Internet-of-Things applications
and the digital gate driver circuits for an insulated-gate bipolar transistor.
Dr. Takamiya received the 2009 and 2010 IEEE Paul Rappaport Awards andthe Best Paper Award at the 2013 IEEE Wireless Power Transfer Conference.
He is a member of the Technical Program Committee of the IEEE International
Solid-State Circuits Conference and the IEEE Symposium on VLSI Circuits.

Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in electrical engineeringfrom the University of Tokyo, Tokyo, Japan,
in 1981.
In 1981, he joined Toshiba Corporation, Kawasaki,
Japan, where he designed CMOS dynamic random
access memory, static random access memory,
reduced instruction set computers processors, DSPs,
and system-on-chip solutions. He has worked
extensively on interconnect delay and capacitancemodeling known as Sakurai model and alphapower-law MOS model. From 1988 to 1990, he was a Visiting Researcher
at the University of California, Berkeley, CA, USA, where he conducted
research in the field of very large-scale integration (VLSI) computer-aided
design. Since 1996, he has been a Professor at the University of Tokyo,
where he is involved in low-power high-speed VLSI, memory design,interconnects, ubiquitous electronics, organic IC’s and large-area electronics.
He has authored/coauthored over 600 technical publications including
100 invited presentations and several books and filed over 200 patents.
Dr. Sakurai was a recipient of the 2010 IEEE Donald O. Pederson Awardin Solid-State Circuits, the 2009 and 2010 IEEE Paul Rappaport award,
the 2010 IEICE Electronics Society Award, the 2009 IEICE Achievement
Award, the 2005 IEEE ICICDT Award, the 2004 IEEE Takuo Sugano Award,
and the 2005 P&I patent of the year award and four product awards. He is an
Executive Committee Chair for VLSI Symposia and a Steering Committee
Chair for the IEEE A-SSCC. He served as a Conference Chair for the
Symposium on VLSI Circuits and ICICDT, a Vice Chair for ASPDAC, a TPC
Chair for the A-SSCC, and VLSI Symposium, an Executive Committee
Member for ISLPED, and a Program Committee Member for ISSCC,
CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED, and other international
conferences. He delivered keynote speech at over 50 conferences including
ISSCC, ESSCIRC, and ISLPED. He was an Elected AdCom Member for theIEEE Solid-State Circuits Society and an IEEE CAS and SSCS Distinguished
Lecturer. He is also a Domain Research Supervisor for nanoelectronics area
in Japan Science and Technology Agency. He is an IEICE Fellow.