H-2-4L

Extended Abstracts of the 2013 International Conference on Solid State Devices and Materials, Fukuoka, 2013, pp888-889

Analog-Assisted Digital Low Dropout Regulator (AAD-LDO)
with 59% Faster Transient Response and 28% Ripple Reduction
Kazuaki Mori1, Yasuyuki Okuma2, Xin Zhang1, Hiroshi Fuketa1, Takayasu Sakurai1, and Makoto Takamiya1
1

University of Tokyo, Tokyo, Japan, 2 Semiconductor Technology Academic Research Center (STARC), Yokohama, JapanAbstract
An analog-assisted digital low dropout regulator(AAD-LDO) is proposed to solve the problems of a slow
transient response and a large output ripple in aconventional digital LDO. In AAD-LDO, a fast-response
auxiliary analog LDO is added to the digital LDO inparallel. Compared with the digital LDO, the measured
AAD-LDO in 180nm CMOS reduces the transient
response time and the output ripple by 59% and 28%,
respectively, at the same current efficiency of 97.1%.
1. Introduction
The number of on-chip voltage converters is increasing,
because recent SoC’s require a lot of power supply voltages.
A low dropout regulator (LDO) is a reasonable choice forthe on-chip voltage converters, because LDO requires nooff-chip components. The low power SoC’s require a low
input-voltage LDO with the low quiescent current (IQ) (=supply current for a controller in LDO) [1]. A digital LDO[1-5] achieves the low input-voltage operation with low IQ.
Problems of the digital LDO, however, are a slow transient
response and a large output ripple. In order to solve theproblems, an analog-assisted digital low dropout regulator(AAD-LDO) is proposed.
2. Problems of Conventional LDO’sFig. 1 shows a conventional analog LDO. The currentefficiency () of the analog LDO is low due to high IQ in theoperational amplifier. Fig. 2 shows a conventional digital
LDO [1]. In the digital LDO, the current efficiency is highby low IQ in the controller and the comparator, though thetransient response is slow and the output ripple is large. Inorder to reduce the transient response time, high frequency
clock (Clk) is required, which increases IQ and decreases [2-3]. In order to reduce the ripple, the unit gate width(WUNIT) of the power transistors is reduced and the number(n) of the power transistors is increased. The increased n,however, increases IQ and decreases . Therefore, a newcircuit is required to reduce both the transient response time
and the ripple without decreasing .
3. Proposed Analog-Assisted Digital LDO (AAD-LDO)
Fig. 3 shows a concept of the proposed AAD-LDO. In
AAD-LDO, a fast-response auxiliary analog LDO is added
to the digital LDO in parallel. Fig. 4 shows a detailed
schematic of the proposed AAD-LDO. In AAD-LDO, thedigital LDO is main and the analog LDO is auxiliary,
because WANALOG < WDIGITAL. The digital LDO slowly
controls the output voltage (VOUT) with a coarse digital

voltage step. In contrast, the analog LDO quickly controls
VOUT with a fine analog voltage control. By operating boththe digital LDO and the analog LDO simultaneously inparallel, AAD-LDO reduces both the transient response time
and the output ripple.
4. Measurement Results and Discussion
Both AAD-LDO and the digital LDO are fabricated in
180nm CMOS. In AAD-LDO and the digital LDO, thedigital LDO part is the same and only AAD-LDO has theanalog LDO. Fig. 5 shows the chip microphotograph and thelayout of AAD-LDO. The total chip area 1.2mm×0.5mm.
The core area of the digital and analog LDO is
200m×170m and 30m×50m, respectively. Table I
shows a performance summary of AAD-LDO. The
fabricated AAD LDO achieved the 1.2-V input voltage and0.95-V output voltage with 99.6% current efficiency and14.2-µA quiescent current at 3.4-mA load current.
Figs. 6 and 7 shows the measured  dependence of thetransient response time and the peak-to-peak ripple of VOUT,
respectively, in the conventional digital LDO and theproposed AAD-LDO. The input voltage is 1.2V, VOUT is
0.95V, and the load current is 3.4mA. The reference voltage(VREF) is changed from 0.8V to 0.95V and the response timeof VOUT is measured at the load resistance of 270. The Clk
frequency is varied from 1MHz to 14MHz in the digital
LDO, while the bias current of the operational amplifier isvaried from 1A to 15A in AAD-LDO at the Clk
frequency of 1MHz. Compared with the conventional digital
LDO, the proposed AAD-LDO reduces the response timefrom 40s to 2.4s by 94% and from 4.4s to 1.8s by 59%
at  of 99.6% and 97.1%, respectively. Fig 8 shows themeasured waveforms of VREF and VOUT at  of 99.6%.
Similarly, AAD-LDO reduces the ripple from 10.8mV to7.8mV by 28% at  of 97.1% as shown in Fig. 9.
Acknowledgements
This work was partly carried out as Extremely Low Power(ELP) project supported by METI and NEDO. The VLSI chips
have been fabricated in the chip fabrication program of VDEC incollaboration with Rohm Corp. and Toppan Printing Corp.

References[1] T. Okuma, et al., CICC, pp. 323-326, 2010.
[2] M. Onouchi, et al., A-SSCC, pp. 37-40, 2011.
[3] A. Raychowdhury, et al., Symp VLSI Circuits, pp. 148-149,2012.
[4] Y. Lee, et al., Symp VLSI Circuits, pp. 178-179, 2012.
[5] C. Chiu, et al., Symp VLSI Circuits, pp. 166-167, 2013.

- 888 -VIN

VIN

Digital

VREF

M1Controller

Comparator

Analog

VREF

VIN

M2
WUNIT

Load

VOUT

Load

Fig. 2 Conventional digital LDO [1].

Fig. 3 Concept of proposed AAD-LDO.

Sub analog LDO

1.2mm
0.5mm

VIN(1.2V)

Analog

170mm
WANALOG = 40mm

M256

10nF

Table I Performance summary of AAD-LDO.
CMOS Technology
Active area
Clock frequency
Input voltage
Output voltage
Maximum load current
Nominal load current (I 1)
Output capacitor
Quiescent current @ I 1
Current efficiency @ I 1

180 nm
0.036 mm2
1 MHz
1.2 V
0.95 V11 mA
3.4 mA
10 nF (Off-chip)
14.2 µA - 242 µA
93.3 % - 99.6 %Transient response time [ms]WDIGITAL = 1mm X 256= 256mmFig. 4 Detailed schematic of proposed AAD-LDO.

50mm

VOUT(0.95V)

DigitalLDO

503020Digital LDO(Conv.)

10-94%

5-59%

32AAD-LDO(Proposed)
Fig.8(b)

19596
9798
99
Current efficiency [%]10014Digital LDO Fig.9(a)(Conv.)

1210-28%

8Fig.9(b)6AAD-LDO(Proposed)

42095

96
9798
99
Current efficiency [%]Fig. 6 Measured transient response timevs. current efficiency.
Conv. digital LDO

Fig. 7 Measured output ripple vs.
current efficiency.

Conv. digital LDO
0.95V

40ms

1ms

VREF

VOUT10.8mV

VOUT

0.8V

50mV
10ms

Clk (1MHz)

Clk (10MHz)

(a)

(a)
Proposed AAD-LDO

Proposed AAD-LDO
0.95V

2.4ms

5ms

VREF

VOUT

7.8mV

VOUT

0.8V

Analog
LDO

Fig. 5 Chip microphotograph and layout of AAD-LDO.
Fig.8(a)Output ripple [mV]

M3200mm

VREF(0.95V)

M2LoadController

M130mmLoad

Clk

Main digital LDO

Clk(1MHz)

Analog
LDO
(Sub)

VOUT

Fig. 1 Conventional analog LDO.

VREF
(0.95V)

Clk

Mn

VOUT

8-bit
digitalDigital
LDO(Main)

VREF

M350mV
10ms

Clk (1MHz)

Clk (1MHz)(b)
Fig. 8 Measured transient waveforms of VREF and VOUT at h of 99.6%.
(a) Conv. digital LDO. (b) Proposed AAD-LDO.

- 889 -(b)Fig. 9 Measured output ripple waveforms at h of 97.1%.
(a) Conv. digital LDO. (b) Proposed AAD-LDO.

100