Ryunosuke Katada1, Katsuhiro Hata1, Yoshitaka Yamauchi1, Ting-Wei Wang1,2, Ryuzo Morikawa1, Cheng-Hsuan Wu1,
Toru Sai1, Po-Hung Chen2, and Makoto Takamiya1
1
The University of Tokyo, Tokyo, Japan
2
National Chiao Tung University, Hsinchu, Taiwan
Email: khata@iis.u-tokyo.ac.jp
Abstract— In this paper, a problem of huge voltage
overshoots (VOVERSHOOT) of VDS in GaN FETs, which rarely
happens during an automatic search of optimum gate driving
parameters in a digital gate driving (DGD), is clarified for the
first time, and a solution to avoid the problem is proposed. The
highest VOVERSHOOT in 165k measurements, where parameters of
6-bit DGD IC in 6 time slots in 3.3-ns time intervals are
randomly changed in the turn-off of GaN FET at 20 V and 10 A,
is 27.6 V, which is 115 % larger than the conventional singlestep gate driving (CSG) and is almost equal to the maximum
rated voltage of the GaN FET. To solve the problem, a safe andfast search method of optimum parameters for DGD is proposed,
which achieved 61 % reduction of the switching loss and 59 %reduction of VOVERSHOOT compared with CSG.

Digital gate driver (DGD) IC
Scan-in

Scan_Data
Scan_CLKnPMOS [5:0]

6

nNMOS [5:0]

6

D

GaN FET

Q

GND

1WP
IO

32WP

IO

32IO

1WN

32WN

VDD

IN
Enable
CLK (300 MHz)GNDInternal
clock
generator

D

32IO

IG

GND

Q

Int_CLK

GND

GND

IG = nIO= 0 A to 5 A
n = 0 to 63
IO = 80 mA

Fig. 1. Circuit schematic of 5 V, 300 MSa/s, 6-bit DGD IC for GaN FETs.
Not to scale

Keywords— digital gate drive, GaN FET, switching loss,
overshootIN(e.g. 100 kHz)I. INTRODUCTION

On

Off

16 pulses

16 pulses

CLK(300 MHz)

Fast switching of GaN FETs reduces the switching loss
(ELOSS), while current overshoot (IOVERSHOOT) and voltage
overshoot (VOVERSHOOT) increase, which is a critical problem
in GaN FETs, because a huge overshoot that exceeds the
maximum rating of GaN FETs causes serious device damage.
Active gate driving [1] and digital gate driving (DGD) [2-3]
are important technologies to reduce both VOVERSHOOT and
ELOSS in GaN FETs. The advantage of DGD is its
programmability in supporting a wide variety of powerdevices [4] and its ease of use, because the parameters of DGD
can be automatically optimized using software [4-5].

Int_CLK63

nPMOS [5:0]063nNMOS [5:0]0Fig. 2. Timing chart of 5 V, 300 MSa/s, 6-bit DGD IC for GaN FETs.

In this paper, however, it is shown for the first time that
DGD is a double-edged sword. As far as the authors know, noprevious papers show the risk of DGD. Specifically, DGD
with good parameters achieves lower VOVERSHOOT and ELOSS
than the conventional single-step gate driving (CSG), while
DGD with bad parameters causes higher VOVERSHOOT and
ELOSS than CSG, which suggests a risk of overvoltage
breakdown of GaN FETs during the random parameter search
process for DGD. In order to understand the cause of the
problem and to avoid it, in this paper, the principle of huge
VOVERSHOOT generation is analyzed and a safe and fast searchmethod for the parameters, that achieves low ELOSS and
VOVERSHOOT without generating huge VOVERSHOOT, is proposed.

Internal clock generator

Scan-in

Predrivers

nMOS drivers

Scan-inpMOS drivers

2.4 mmFig. 3. Die photo of DGD IC fabricated with 180-nm BCD process.

II. DIGITAL GATE DRIVER IC FOR GAN FETS [6]Figs. 1 and 2 show a circuit schematic and a timing chartof the developed 5 V, 300 MSa/s, 6-bit DGD IC for GaN FETs,
respectively. The IC is designed using only 5 V transistors andrequires a single power supply of 5 V. The gate current (IG)can be varied in 64 levels for each of the 16 3.3-ns timeintervals during turn-on/off of the GaN FETs depending on

978-1-7281-5135-9/21/$31.00 ©2021 IEEE

VDD

VDD

VDD (5 V)

1.8 mm2021 IEEE Energy Conversion Congress and Exposition (ECCE) | 978-1-7281-5135-9/21/$31.00 ©2021 IEEE | DOI: 10.1109/ECCE47101.2021.9595264

Digital Gate Driving (DGD) is Double-Edged
Sword: How to Avoid Huge Voltage Overshoots
Caused by DGD for GaN FETs

scan-in data. 64-level IG control from 0 A to 5 A in 80 mA
increments is achieved by selectively turning on or off six
nMOSFETs or pMOSFETs with binary weighted gate widths(1WN, 2WN, 4WN, 8WN, 16WN, and 32WN in case ofnMOSFETs) in the output stage with 6-bit digital signals. IG
control in 3.3-ns intervals is required, because the turn-on/off

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(a)

10A
20V

5V

DGD

IG

(b)

ID
Q2

VDS

(c)

RS

VGS

Conventional
single-step0
t gate driving (CSG)n1 n2 n3 n4 n5 n6 63
Original digital
gate driving (DGD)
0t for random trial

n1

63

n1

0

0 0 0 0Fig. 4. Circuit schematic of fabricated GaN half bridge.

ID

VOVERSHOOT

Stop-and-gogate driving

t

VDS
t

Q1
40 mm

t

VGS

Shunt resistor for
ID measurement

nNMOS nNMOS nNMOSGaN FETQ1

3.3 ns×6 = 20ns
Fig. 7. Three types of gate driving vectors (GVs) compared in this paper.

DGD IC

Q2

III. VOLTAGE OVERSHOOT AND SWITCHING LOSS IN DGDFOR GAN FETS
In order to investigate the relationship between
VOVERSHOOT and ELOSS in DGD with different parameters, theswitching characteristics of GaN FETs are measured bydouble pulse tests. Figs. 4 to 6 show a circuit schematic, aphoto of PCB, and a measurement setup of the GaN (EPC2030,
40 V, 48 A) half bridge for the double pulse test at 20 V and
10 A, respectively. ID was measured using a high-bandwidth
shunt resistor (SDN-414-10, T&M Research Products), and
VGS and VDS were measured using high voltage differential
probes (BUMBLEBEE, PMK).

47 mm
Fig. 5. PCB of GaN half bridge.

Shuntresistor

In this paper, only turn-off is discussed, because themeasured maximum IOVERSHOOT at turn-on is 11 A, which ismuch smaller than the maximum rated pulse current of the
GaN FET of 490 A. Fig. 7 shows the definition of three types
of DGD compared in this paper. nNMOS is an integer from 0 to
63 indicating IG at turn-off and IG = nNMOS × 80 mA. Fig. 7 (b)shows the original gate driving vectors (GVs) for DGD with 6
time slots. In this paper, GVs are defined as (n1, n2, …, n6),
where n1, n2, and n6 are integers from 0 to 63. Six 3.3-ns timeintervals are used. Fig. 7 (c) shows GVs of the stop-and-gogate driving [7] with only one variable (n1), which was
proposed to reduce the test cost to find optimum GVs. Fig. 7(a) shows GVs of CSG for comparison.

DGD IC

Fig. 6. Measurement setup of GaN half bridge for double pulse test.

transient of GaN FETs is typically less than 10 ns. The 3.3-ns
interval is defined by an externally supplied 300-MHz clock
signal (CLK). To increase the clock frequency to 300 MHz,the need for high-speed digital data input is eliminated and therequired digital data is pre-stored in on-chip memory (flipflops) by the scan-in circuit.
Fig. 3 shows a die photo of the developed DGD IC
fabricated with 180-nm BCD process. The die size is 1.8 mm
by 2.4 mm.

Fig. 8 shows the measured ELOSS and VOVERSHOOT. The
black line shows the trade-off curve of CSG with varied n1
from 1 to 63, where ELOSS decreases and VOVERSHOOT increases
with increasing n1. Point B shows the measured point at n1 =63. The red small dots show 165k measurements of therandom trial of the original GVs with 6 time slots in Fig. 7 (b),where GVs in 6 time slots are randomly changed to investigate
the range of ELOSS and VOVERSHOOT covered by the original
GVs. They are meaningful measurements to give an overview
of the range of ELOSS and VOVERSHOOT, though the 165k
measurements covers only less than 0.0003 % of the number

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n1 = 1Conv.
single-step(Fig. 7 (a))

ELOSS [μJ]3

Point E
(Fig. 9 (e))

20n1 = 63

Point A
(Fig. 9 (a))

0Point B
(Fig. 9 (b))

5

10

15

n1 = 1Conv.
single-step(Fig. 7 (a))

3

Point D
(Fig. 9 (d))

14Point C (Fig. 9 (c))

ELOSS [μJ]4Stop-and-go(Fig. 7 (c))
Random trial(Fig. 7 (b))
20

25

−61%
2

−59%
1

0

30

Point C (Fig. 9 (c))+115%

n1 = 63

Point A
(Fig. 9 (a))

0n1 = 7

Point B
(Fig. 9 (b))

5

10

15

20

25

VOVERSHOOT [V]VOVERSHOOT [V](a) Measured points and trajectories

30

Max. ratingof GaN FET(b) Improvement and deterioration results

Fig. 8. Measured ELOSS vs. VOVERSHOOT of conventional single-step gate driving, digital gate driving for random trial, and stop-and-go gate driving.

ELOSS : 1.4 μJ

ELOSS : 1.2 μJ

ELOSS : 3.3 μJ

10 ns/div

10 ns/div

10 ns/div

VDS: 15 V/div
ID: 5 A/div

VDS: 15 V/div

VDS: 15 V/div

0

VGS: 5 V/div

nNMOS

nNMOS

VGS: 5 V/div

63

60
48 47
0

0

00

2

63

0
VGS: 5 V/divnNMOS

ID: 5 A/div

ID: 5 A/div

0

Time

63

48
0 0

0000

Time

Time

Point
A
(a) Point A(b) Point B(c) Point C

ELOSS : 1.6 μJ

ELOSS : 3.3 μJ

10 ns/div

10 ns/div

VDS: 15 V/div
ID: 5 A/div

ID: 5 A/div
VDS: 15 V/div

0

nNMOS

0

VGS: 5 V/div

63

59

nNMOS

0

VGS: 5 V/div

0000

63

51
0

0000

Time
(d) Point D

Time(e) Point E

Fig. 9. Gate vectors and measurement waveforms at each measured point.

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63

0 × 14 slots

3030
2525
2020
1515
1010
5 5
0 0
1010
8 8
6 6
4 4
2 2
0 0
6 6
5 5
4 4
3 3
2 2
1 1
0 0
2525
2020
1515
1010
5 5
0 0

6
5

n1 ＝ 0VGS [V]432
1n1 ＝ 40n1 ＝ 50n1 ＝ 57
n1 ＝ 63

0
-1

-2
50

VDS [V]4030

n1 ＝ 57
n1 ＝ 6320

n1 ＝ 50n1 ＝ 40100n1 ＝ 0-10
12.5

n1 ＝ 0n1 ＝ 40n1 ＝ 50

10.0

ID [A]

7.5
5.0

n1 ＝ 57

-5.0
-7.5

0

20

40

Stop-and-go
Stop-and-go (Fig.
(Fig. 8)10)

Conv.
single-step
(Fig.
6)8)
Conv.
single-step(Fig.
Stop-and-go
Stop-and-goConv.
single-stepConv.
single-stepStop-and-go
Stop-and-go

Stop-and-go
Stop-and-go1010

n1 ＝ 0n ＝ 63n1 ＝ 40 1
n1 ＝ 50n1 ＝ 57
n1 ＝ 63-2.5

Dangerous
DangerousTarget
Targetregionregion region
region

1515

2.5
0.0

Ineffective
Ineffective
regionregionVOVERSHOOT [V]VOVERSHOOT [V]0tA

Average ID [A] Average VDS [V] Average VGS [V] ELOSS [μJ]
Average ID [A] Average VDS [V] Average VGS [V] ELOSS [μJ]nNMOS

3.3 nsn1

Stop-and-go
Stop-and-go

5 5

60

80

100

0 0
0 0

1010

Time [ns]Fig. 10. GV and measured waveforms with varied n1 in stopand-go gate driving.

2020

3030

n1n1

4040

5050

5252

6060

Fig. 11. measured n1 dependence of VOVERSHOOT, ELOSS, average VGS, average VDS, andaverage ID.

of combinations of 646 (~ 69G) in 6-bit and 6-slot GVs. Point
A shows the best measured point achieving both small ELOSS
and low VOVERSHOOT, while Point C shows the worst measured
point with the highest VOVERSHOOT. As shown in Fig. 8 (b),compared with CSG, Point A reduces ELOSS by 61 % at thesimilar VOVERSHOOT and reduces VOVERSHOOT by 59 % at thesame ELOSS. VOVERSHOOT of Point C is 27.6 V and VDS reaches
47.6 V, which is almost equal to the maximum rated voltageof 48 V and the GaN FET could be destroyed. Compared with
Point B, Point C increases VOVERSHOOT by 115 %.
Figs. 9 (a) – (c) show the GVs and measured waveformsof Point A to Point C, respectively. In Fig. 9 (a), VGS increases
temporarily when GV changes from 60 to 0, dID / dt is reduced,
and VOVERSHOOT is reduced. In contrast, in Fig. 9 (c), VGS
increases temporarily when GV changes from 48 to 0, theGaN FET is turned-on again, and VDS stays at halfway voltage(13 V). After that, the highest VOVERSHOOT is generated when
GV changes from 0 to 63, because the turn-off voltage
overshoot is added to the halfway voltage.

The meaning of GVs of Point A and Point C is discussed.
Interestingly, GVs of both Point A and Point C include a lotof zeros. Specifically, GV of Point A includes two zeros
between 60 and 48, and GV of Point C includes four zeros
between 48 and 63. The stop-and-go gate driving [7] in Fig. 7(c) also include a lot of zeros and the driving with only one
variable (n1) may be used to understand the cause of the
problem of Point C, because the original GVs with 646
combinations is too complicated to understand.
The blue line in Fig. 8 (a) shows the stop-and-go gate
driving in Fig. 7 (c) varied n1 from 0 to 63. Interestingly, theblue line covers most of the red small dots, which suggeststhat the only 64 measurements with the stop-and-go gate
driving cover most of ELOSS and VOVERSHOOT of 165k
measurements with the original GVs. The blue line also covers
Point A to Point C. Point D and Point E are the measured
points of the stop-and-go gate driving close to Point A andPoint C, respectively, and their GVs and measured waveforms
are shown in Figs. 9 (d) and (e). The only difference in GVs

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5

0

n1

63
Appropriate
search rangenNMOS

VGS [V]

Vth

QOFF
0

Stop-and-go gate driving

Limitsearch range
based on QOFF

Discharge as
much charge
as QOFF

0

0

0

0

0

t

Gate charge [nC]Fig. 12. Safe and fast search method of optimum GVs for DGD with discharging gate charge more than QOFF in the period of n1.

between Point D and Point E is n1, which suggests that n1 in
the stop-and-go gate driving is an important parameter todetermine VOVERSHOOT and ELOSS in DGD.
IV. HOW TO AVOID HUGE VOLTAGE OVERSHOOTS
In order to analyze n1 dependence of VOVERSHOOT and ELOSS,
Fig. 10 shows the GV and measured waveforms with varied
n1 in the stop-and-go gate driving and Fig. 11 shows themeasured n1 dependence of VOVERSHOOT, ELOSS, average VGS,
average VDS, and average ID. Fig. 11 also includes CSG forcomparison. Instead of the four zero segments in Fig. 7 (c), 14
zero slots are used to analyze the steady state of VGS, VDS, andID in detail. The voltage and current averaging is carried out
for the period of tA shown in Fig. 10. Fig. 11 can be classified
into three regions including an ineffective region, a dangerous
region, and a target region. In the ineffective region, n1 does
not work effectively. In the dangerous region, both
VOVERSHOOT and ELOSS increase, because the average VDS isincreased, while the average ID is constant. In the target region,
VOVERSHOOT is less than that of CSG, because the GaN FET isturned-off in the period of n1 and the average ID is reduced.
In this case, the boundary between the dangerous region
and the target region is n1 of 52, which can be explained by
the device characteristics. The discharged gate charge by
DGD in the period of n1 is 13.7 nC (= 52 × 80 mA × 3.3 ns),
while the gate charge required to discharge from VGS = 5 V to
VGS = 1.5 V (= threshold voltage Vth) is 13.9 nC according to
the gate charge curve [8]. Both values are consistent andreasonable. This gate charge is defined as QOFF shown in Fig.
12 and the stop-and-go gate driving with discharging the sameamount of charge as QOFF in the period of n1 operates at theboundary between the dangerous region and the target region.
In conclusion, it is important to discharge enough gate charge
to turn off the GaN FET in the first time slot of the stop-andgo gate driving to avoid huge VOVERSHOOT.
Therefore, in order to achieve low ELOSS and VOVERSHOOT
without generating huge VOVERSHOOT, the stop-and-go gate
driving with discharging the gate charge exceeding QOFF in the
period of n1 is practical as the safe and fast search method of
the optimum GVs for DGD, which suggests that the searchrange of n1 should be appropriately limited according to thespecifications of GaN FETs and DGD IC as shown in Fig. 12.

V. CONCLUSIONSThis paper clarified the risk of DGD, where huge
VOVERSHOOT generated during the random parameter search
process for DGD could destroy GaN FETs. In order to achieve
low ELOSS and VOVERSHOOT without generating huge
VOVERSHOOT, the stop-and-go gate driving with discharging thegate charge exceeding QOFF in the period of n1 is practical as
the safe and fast search method for DGD. In the future, theproposed search method will be experimentally demonstrated.
ACKNOWLEDGMENT
This work was partially supported by JST ERATO Grant
Number JPMJER1501, Japan.
REFERENCES
[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

P. Bau, M. Cousineau, B. Cougo, F. Richardeau, and N. Rouger,“CMOS active gate driver for closed-loop dv/dt control of GaN
transistors,” IEEE Trans. Power Electronics, vol. 35, no. 12, pp.
13322–13332, Dec. 2020.
H. Dymond, J. Wang, D. Liu, J. Dalton, N. McNeill, D. Pamunuwa, S.
Hollis, and B. Stark, “A 6.7-GHz active gate driver for GaN FETs tocombat overshoot, ringing, and EMI,” IEEE Trans. Power Electronics,
vol. 33, no. 1, pp. 581–594, Mar. 2017.
W. J. Zhang, J. Yu, Y. Leng, W. T. Cui, G. Q. Deng and W. T. Ng, “Asegmented gate driver for E-mode GaN HEMTs with simple driving
strength pattern control,” in Proc. IEEE International Symposium on
Power Semiconductor Devices and ICs (ISPSD), 2020, pp. 102–105.
K. Miyazaki, S. Abe, M. Tsukuda, I. Omura, K. Wada, M. Takamiya,
and T. Sakurai, “General-purpose clocked gate driver IC with
programmable 63-level drivability to optimize overshoot and energy
loss in switching by a simulated annealing algorithm,” IEEE Trans.
Industry Applications, vol. 53, issue 3, pp. 2350–2357, May-Jun. 2017.
Y. Cheng, T. Mannen, K. Wada, K. Miyazaki, M. Takamiya, and T.
Sakurai, “Optimization platform to find a switching pattern of digital
active gate drive for reducing both switching loss and surge voltage,”
IEEE Trans. Industry Applications, vol. 55, no. 5, pp. 5023-5031,
Sep./Oct. 2019.
R. Katada, K. Hata, Y. Yamauchi, T. Wang, R. Morikawa, C. Wu, T.
Sai, P. Chen, and M. Takamiya, “5 V, 300 MSa/s, 6-bit digital gate
driver IC for GaN achieving 69 % reduction of switching loss and 60 %reduction of current overshoot,” in Proc. International Symposium on
Power Semiconductor Devices and ICs (ISPSD), 2021, pp. 55-58.
T. Sai, K. Miyazaki, H. Obara, T. Mannen, K. Wada, I. Omura, T.
Sakurai, and M. Takamiya, “Stop-and-go gate drive minimizing test
cost to find optimum gate driving vectors in digital gate drivers,” inProc. IEEE Applied Power Electronics Conference and Exposition(APEC), 2020, pp. 3096-3101.
Data sheet of EPC2030, Efficient Power Conversion Corporation.

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