A design methodology of chip-to-chip
wireless power transmission system
Kohei Onizuka1, Makoto Takamiya1, Hiroshi Kawaguchi3, and Takayasu Sakurai2
1

Institute of Industrial Science and 2Center for Collaborative Research, University of Tokyo, Tokyo, Japan3
Department of Computer and Systems Engineering, Kobe University, Kobe, Japan

Abstract— A design methodology to transmit power using achip-to-chip wireless interface is proposed. The proposed powertransmission system is based on magnetic coupling, and the powertransmission of 5mW/mm2 was verified. The transmission
efficiency trade-off with the transmitted power is also discussed.

I. INTRODUCTION
A System-in-a-Package (SiP) is getting a major 3D
integration approach in recent years. For data communication
among stacked chips in SiP’s, wireless data transmission
technologies have been investigated for high speed, low power
and low cost [1][2]. Power delivery in these systems, however,is not wireless and is based on bonding. Then, it is difficult to
get two stacked chips close, since the bonding needs several
hundred microns separation between chips. One solution is toskew the stacked chips but this is difficult if the upper chipshould be connected in the middle of the lower chip and iscovered by the topmost chip.
If the power is supplied wirelessly, the chips can be stacked
closely and the wireless data transmission performance will beincreased, since the data bandwidth and communication
reliability increases as the chip-to-chip distance is decreased inwireless data communication. The cost is also decreased due tothe elimination of mechanical bonding. Furthermore, chip
detachability can also be achieved by combining the wirelessdata and power transmission. This opens up a totally newsystem customization scheme after the fabrication as wesometimes change a daughter board for system upgrade.
Fig.1 illustrates a proposed wireless power delivery scheme
based on inductive coupling between the lowest chip and upperchips. The shortest inductor-to-inductor distance depends on
the thinning of the chip thickness, which is as small as 20
microns. If a face-to-face configuration is possible, the distanceis further reduced, which is used in the measurement setup in
this paper.
Fig.2 shows the concept of system customization after thefabrication of an SiP to reduce mask set cost and to increase
post-fabrication system modification freedom. Chips likeaccelerators, special engines, analogs, memories are attachedwirelessly on top of the lower base chip. The lower chip
embedded in the package has a data transceiver and a “powertransmitter”. The upper chip attached to the package has a data

1-4244-0757-5/07/$20.00 ©2007 IEEE

Fig. 1. Concept of chip-to-chip wireless power transmission assisting
wireless interchip communication.

Fig. 2. Concept of system modification after fabrication of SiP’s/SoC’s.

transceiver and a “power receiver”. This system may give users
the ability to upgrade the SiP’s like a daughterboard upgrade
nowadays. The risk of ESD problem is mitigated because thissystem eliminates the naked interconnections and metal pads
with coils for wireless transmission being covered bypassivation layer.
II. TEST CIRCUIT
A. Circuit Topology
Fig.3 shows the circuit diagram of the proposed system. The
lower chip includes a transmitter circuit and an on-chip planar
inductor L1 for magnetic field generation. The transmittercircuit generates an RF signal from the DC supply voltage VDD
and activates L1. The power is transmitted by magnetic fields
rather than radio waves. Fig.4 describes a diagram of theadopted transmitter, where the oscillation frequency f of the1

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Upper ChipLower ChipDL L2
RF+ 1D+
RLTransmitter
RF-kFig. 3. Circuit diagram of proposed system.

Differential
Buffers(a)(b)
Fig. 6. Chip microphotograph of (a) transmitter and (b) receiver.

RF+

Ring
Oscillatorzx

RF-yFig. 4. Circuit diagram of transmitter.

D+D-Fig. 7. Whole image of measurement setup.

Lower Boardring oscillator is designed to be variable for the experiments.
The upper chip includes an on-chip planar inductor L2, afull-wave rectifier circuit using MOSFET-based diodes and asmoothing capacitor. Fig.5 shows the circuit diagram of thediode circuit whose two PMOS transistors reduce theundesirable body effect of the main PMOS transistor [3]. kindicates the coupling factor of the inductors.
B. Simulation and Measurement Results
The system shown in Fig.3 was designed in 0.35-µm CMOS
and fabricated. Generally, on-chip planar inductors haveconsiderable parasitic capacitive and resistive elements so thatthe Q factor is not high. Values of series resistance and parasitic
capacitances of the inductor are calculated by approximation
formulas and k is derived by momentum electromagnetic field
simulator. The parasitic resistances of buffers, diodes andinterconnections were be estimated carefully and minimized indesign and layout process. The outside diameter of the inductor
is set to 700x700µm and k is calculated to be 0.75. RF voltage
generated between two terminals of L2 is set to be twice thenominal VDD when RL=∞. This RF voltage is better to behigher to reduce the diode voltage loss but it can not surpass
twice the tolerant voltage of the PMOS shown in Fig.5. Fig.6
shows microphotographs of the fabricated power transmitterand receiver chips. Fig.7 and 8 show the measurement setup.
The lower (upper) chip is mounted on the lower (upper) board
and the two chips gets closer together face-to-face.
Fig.9 shows the simulated and measured transmitted power
dependence on output DC voltage. HSPICE is used for thesimulation. In this implementation, L1=1.0nH, L2=9.3nH and1-4244-0757-5/07/$20.00 ©2007 IEEELower Chip
UpperChip

Upper Board

Fig. 5. Circuit diagram of PMOS-based diode.

Transmitted Power (mW)

Fig. 8. Closeup view of measurement setup.

3RL=100Ω
2

10Measured
Simulated
0.2 0.4 0.6 0.8 1 1.2 1.4
Output Voltage (V)Fig. 9. Transmitted power dependence on output voltage.

the oscillation frequency is set to f = 330MHz for this graph.
Output voltage is varied by changing DC output load RL. Thepeak transmitted power 2.5mW which equals to 5mW/mm2 is2ICICDT07

Output Voltage (V)1.6

RS C1R1Ejω

R2L11.45

L2 C2

RL_ACk1.3
150

Fig. 13. Simplified circuit model.

250
Frequency (MHz)350

Fig. 10. Output voltage dependence on oscillation frequency f.

RL_DC

Output Voltage (V)

1.6

Fig. 14. Equivalent circuit of RL_AC.

0.8

0800
400
Δz (µm)1200

Fig. 15. Circuit model under resonance condition.

1.6

represents parasitic resistances of transmitter interconnections
and driving transistors which equals to the internal impedanceof the transmitter. R1 and R2 indicate series resistances of L1and L2 respectively. Capacitances C1 and C2 resonate with L1
serially and with L2 in parallel respectively. RL_AC relates to theequivalent total impedance of the rectifier, the smoothing
capacitor and the DC load resistance RL_DC as shown in Fig.14.
RL_AC was shown to be approximated as follows when therectifier is ideal and the smoothing capacitor is large enough[4].
R L _ DC(1)R≈

0.800Δy (µm) 280

RXEjωFig. 11. Output voltage dependence on ∆z.

Output Voltage (V)RYRS+R1280560 Δx (µm)

Fig. 12. Output voltage dependence on ∆x and ∆y.

observed when RL is 100Ω, which is the equivalent source
resistance of the wireless power source. The simulated results
coincide well with the measured results. Thus the modelingaccuracy is considered to be sufficiently high. Figs. 10, 11 and
12 show the measured output voltage dependence on frequency,∆z (distance between chips) and ∆x (misplacement in xdirection) and ∆y (misplacement in y direction) when the load
is open which equals to RL=∞.

L _ AC.

Here, we assume the transmitted power is high (if notmaximized) when transmitter circuit is in resonance. That is, C1is expressed as follows. Although this condition does not givethe optimum condition, the resultant transmitted power is atleast achievable.
1(2)
C =
1

III. CIRCUIT OPTIMIZATION

4 π 2 f 2 L1 .

On the other hand, C2 resonates under the following condition
and the circuit model can be converted to a simple resistancemodel as shown in Fig.15.
(3)
4 π 2 f 2 R L2 _ AC L2 C 22 − R L2 _ AC C 2 + L2 = 0 .

A. Circuit ModelAlthough the feasibility of the wireless power delivery
system is demonstrated in the previous sections, it is preferable
to increase the transmittable power and to maximize the power
efficiency to further increase the variety of applications. In thissection, the methodology for further increasing the transmitted
power and maximizing the power efficiency are describedusing simple circuit model. Improvement can be achieved byadding resonance capacitors C1 and C2 as shown in Fig.13. RS

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2

RX and RY are the transformed impedances of R2 and RL, andare described as follows.
1(4)R = 4π 2 f 2 k 2 L L.
X

3

12

R2ICICDT07

50
PRY 40(mW)30improves as the value of L1 increases although the transmittedpower degrades. On the other hand, both the power efficiency
and the transmitted power are independent of the value of L2. Ina real design, both the transmitted power and the power
efficiency are lower than the calculation results due to otherindependent power losses including switching loss andrectifying loss however, this optimization is valuable for thefundamental design.

108264 L2 (nH)

4L1 (nH)

688B. Example of Improved Design
To show further capability of the proposed system, anexample of improved design using the optimization theory isdescribed in this section. To gain higher transmitted power andpower efficiency, Class-E amplifier and improved rectifier[5]are also valuable. Assuming that those techniques are utilizedin 90nm CMOS, other parameters are chosen as f=900MHz,
k=0.75, ζ=2.6×10-9, L1=3.9nH, L2=6.8nH and C2=3.5pF withinductor outer diameter of 500µm. As a result, the transmitted
power of 306mW/mm2 and the power efficiency of 23.4% for
VDD=2.5V are simulated by using HSPICE with all the parasiticelements.

L2 (nH)

IV. CONCLUSIONS

210Fig. 16. Calculated transmitted power dependence on L1 and L2 whenpower efficiency is maximized.

4035
η(%) 3025106244L1 (nH)

6In summary, a chip-to-chip 5mW/mm2 wireless powertransmission system was proposed and demonstrated by
0.35-µm CMOS technology. Maximization of the power
efficiency and an example of improved design are alsodiscussed.

2810Fig. 17. Calculated power efficiency dependence on L1 and L2.

(1 + 4 π f C R
2RY = 4 π 2 f 2 k 2 L1 L22222L _ AC

RL _ AC).

(5)ACKNOWLEDGMENT
This work is supported by VLSI Design and Education
Center (VDEC), the University of Tokyo in collaboration withRohm Corporation, Toppan Printing Corporation and Cadence
Design Systems, Inc. This research was partially supported by
Japan Society for the Promotion of Science (JSPS),
Grant-in-Aid for Scientific Research (KAKENHI) 16760271.

In this system, high power efficiency is as important as thetransmitted power to increase the variety of applications. Thepower transmission efficiency for RY is maximized under thefollowing condition.
RY = R X

RS + R1.
RS + R1 + R X(6)In case of on-chip planar inductors, the relationship between
RN and LN is approximated as follows with ζ being a technology
parameter because both RN and LN are roughly proportional tothe square of turns.
L(7)ζ ≈ N .

REFERENCES
[1]

[2]

RN

The optimum values of C2 and RL_AC are calculated as functionsof k, f, ζ, RS, R1, R2 by using formulas (3) and (6).
C2 =

ξ (RS + R1 )R2 R + R + 4 π 2 f 2 ξ 2 R + R + k 2 R[RL _ AC =S1

ξC2(S1RS + R1
RS + R1 + 4 π 2 f 2 ξ 2 k 2 R1 .

1)] .

[3]

(8)
[4]

(9)
[5]

Figs.16 and 17 show the calculated transmitted power andpower efficiency η when f=330MHz, k=0.75 and ζ=1.7×10-9
which are the same conditions with the real circuit presented insection II, and RS=2. In this design region, the power efficiency

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