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PAPER

Special Section on Circuits and Design Techniques for Advanced Large Scale Integration

Diﬃculty of Power Supply Voltage Scaling in Large Scale
Subthreshold Logic Circuits
Tadashi YASUFUKU†a) , Member, Taro NIIYAMA† , Zhe PIAO† , Nonmembers, Koichi ISHIDA† , Member,
Masami MURAKATA†† , Nonmember, Makoto TAKAMIYA† , and Takayasu SAKURAI† , Members

SUMMARY
In order to explore the feasibility of large-scale subthreshold logic circuits and to clarify the lower limit of supply voltage (VDD ) for
logic circuits, the dependence of the minimum operating voltage (VDD min )of CMOS logic gates on the number of stages, gate types and gate width
is systematically measured with 90 nm CMOS ring oscillators (RO’s).
The measured average VDD min of inverter RO’s increased from 90 mV to
343 mV when the number of RO stages increased from 11 to 1 Mega, whichindicates the diﬃculty of VDD scaling in large-scale subthreshold logic circuits. The dependence of VDD min on the number of stages is calculatedusing the subthreshold current model with random threshold voltage (VT H )variations and compared with the measured results, and the tendency ofthe measurement is confirmed. The eﬀect of adaptive body bias control tocompensate purely random VT H variation is also investigated. Such compensation would require impractical inverter-by-inverter adaptive body bias
control.
key words: minimum operating voltage, subthreshold, logic, variations,body bias

1.

Introduction

Very low-voltage operation of VLSI’s is eﬀective in reducing both dynamic and leakage power and the maximum energy eﬃciency is achieved at low VDD (e.g., 320 mV [1]).
Thus, many works have been carried out on the subthresholdoperation of logic circuits [1]–[5] and SRAM’s [6], where
VDD is less than VT H of transistors. However, the number oftransistors in the previously reported subthreshold circuits
is small (e.g. 70 k transistor logic circuits at VDD of 230 mV[1], a 32 kbit SRAM at VDD of 160 mV [6], and a 1000-stage
inverter chain at VDD of 60 mV [4]), and the possibility ofmega-gate-scale subthreshold circuits is not clear.
VDD min is the minimum power supply voltage when thecircuits operate without functional errors. RO’s are useful
VDD min detectors [7], because RO’s stop oscillation when
the first functional error in the logic circuits arises. Figure 1 shows the simulated waveform of the 5-stage CMOS
inverter RO. VDD is varied from 0.2 V to 0 V. At VDD min of
50 mV, RO stops oscillating. In order to emulate the recent
SoC’s, mega-stage-scale RO’s are required, because the recent SoC’s have 10–100 Mega logic gates. With technology
scaling and an increased number of transistors on a chip,
Manuscript received July 12, 2009.
Manuscript revised October 2, 2009.
†
The authors are with The University of Tokyo, Tokyo, 1538505 Japan.
††
The author is with Semiconductor Technology Academic Research Center (STARC), Yokohama-shi, 220-0033 Japan.
a) E-mail: tdsh@iis.u-tokyo.ac.jp
DOI: 10.1587/transele.E93.C.332

Fig. 1 Simulated waveform of 5-stage CMOS inverter RO. Definition of
VDD min is shown.

VDD min will increase, because the more gates there are, themore likely it is that the worst-case condition will occur, andthus a higher VDD will be required. However, the systematic
measurements of VDD min of the subthreshold logic circuits
made with scaled devices have not yet been reported.
Systematically measured dependence of VDD min of
CMOS logic gates on the number of stages, gate types andgate widths with 90 nm CMOS RO’s are reported for the
first time, in order to explore the feasibility of large-scalesubthreshold logic circuits and to clarify the lower limit of
VDD for logic circuits [7], [8].
In Sect. 2, the design of CMOS RO’s for VDD min measurement and the measured VDD min is presented. Section 3
presents the analysis of the origin of VDD min with SPICE
and MATLAB to explain the measured results. Section 4
presents the fine-grain adaptive body bias control to reduce
VDD min .
2.

Measured V D D min of 90 nm CMOS RO’s

2.1 Design of CMOS RO’s for VDD min Measurement
Figure 2 shows a schematic of the proposed RO circuits toenable VDD min measurement. The output of RO should be
amplified, because the output amplitude of the RO is small

c 2010 The Institute of Electronics, Information and Communication Engineers
Copyright YASUFUKU et al.: DIFFICULTY OF POWER SUPPLY VOLTAGE SCALING IN LARGE SCALE SUBTHRESHOLD LOGIC CIRCUITS

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Fig. 4 Measured VDD dependence of oscillation frequency of 11-stage
and 1001-stage RO’s.
Fig. 2 Schematic of proposed CMOS ring oscillators (RO’s) for the
VDD min measurement.

ble.

Fig. 3(a) Micrograph of 1M-stage inverter RO. (b) Layout style of RO’s.

(e.g., 70 mV) in the VDD min measurement. The amplificationis performed by the output buﬀer where VDD and VS S of theoutput buﬀer are separated from VDD2 and VS S 2 of RO by
a triple well process. VDD2 and VS S 2 are tuned manually in
1 mV steps in order to find the lowest VDD (=VDD2 − VS S 2 )at which RO can oscillates, which means that the DC levelof the output voltage of RO matches the logic threshold of
the first stage of the output buﬀer. The tuning is necessary to achieve a precise measurement of VDD min because
the wrong setting of VDD2 and VS S 2 leads to an overestimation of VDD min . Figure 3(a) shows the micrograph of a
1 Mega-stage inverter RO in 90 nm CMOS. The core area
is 2.2 mm × 1.3 mm. Figure 3(b) shows the layout style ofRO’s. In order to remove the eﬀect of the within-die systematic transistor variation on RO’s, the interconnect length
between the inverters is as short as possible and the maximum interconnect length in the 1 Mega-stage inverter RO
is 3.5 μm. If the interconnection between inverters is long,both within-die systematic and random transistor variationsaﬀect the measurement results and degrade VDD min . Therefore, the interconnection is shortened to eliminate the eﬀect
of within-die systematic random variation as much as possi-

RO’s include three diﬀerent logic gates (inverter,
2NAND and 3NAND) and two inverters with diﬀerent gate
widths. Standard primitive cells are used for the logic gates,
and the P/N ratio was not optimized for the minimum VDD
operation. The gate length is minimum in the 90 nm CMOS
process. The gate widths of nMOS (Wn ) and pMOS (W p )are 0.54 μm and 0.82 μm, respectively. An inverter with thissize of transistors is defined as an ×1 inverter, and an inverter with a gate width four times larger than that of the×1 inverter is defined as an ×4 inverter. RO’s were fabricated by the 1 V 90 nm CMOS process in three diﬀerent
lots. The first lot includes inverter RO’s from 11 stage to
1 Mega stages that are used to investigate the dependence of
VDD min on the number of stages. The second lot includes inverter RO’s, 2NAND RO’s and 3NAND RO’s that are used
to investigate the gate-type dependence. The third lot includes inverter RO’s and ×4 inverter RO’s that are used toinvestigate the gate-width dependence.
2.2 Dependence of VDD min on Number of Stages
Figure 4 shows the measured VDD dependence of the oscillation frequency of 11-stage and 1001-stage RO’s for 13 dies.
VDD min is defined as the supply voltage (= VDD2 − VS S 2 )when the RO’s stop oscillating and no voltage transitions
from the output buﬀer are observed, which corresponds tofunctional errors in logic LSI’s. It should be noted that
VDD min of 11-stage RO’s is lower than that of 1001-stage
RO’s.
Figure 5 shows the measured die-to-die distribution of
VDD min of inverter RO’s with 11 to 1M-stages. Thirty tothirty-six dies are measured. Figure 6 shows the measured
dependence of the average VDD min with a ±1σ error bar of
inverter RO’s on the number of stages extracted from Fig. 5.
As the number of stages is increased, the average VDD min
increases, because VDD min is determined by the worst inverter(s) in each RO. For example, the average VDD min increases from 90 mV to 343 mV when the number of RO
stages increases from 11 to 1 Mega. The 343 mV indicates

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Fig. 6 Measured dependence of average VDD min of inverter RO’s onnumber of stages.

Fig. 7 Measured dependence of VDD min of inverter RO’s on number ofstages for 15 dies.

Fig. 5stage.

Die-to-die distribution of VDD min of inverter RO’s with 11 to 1M-

a superthreshold VT H operation. The results indicate that
VDD min for logic circuits depends on the scale of the circuits, and large-scale logic circuits have high VDD min . In order to analyze the die-to-die VDD min variations, Fig. 7 shows
the measured dependence of VDD min of inverter RO’s on thenumber of stages for 15 dies. Each line in Fig. 7 represents
a measured VDD min of each chip. Each chip contains 6 RO’s
with 11 to 1M stages. The 6 RO’s are isolated from eachother, and do not share any part of the circuit. Note that no
specific line is higher or lower than the others, and lines are
random. Therefore, it can be concluded that there is no systematic chip-to-chip variation such that all 6 types of RO’s
are all high or low, but rather, the RO’s vary randomly.
2.3 Dependence of VDD min on Gate Types and Gate Width
Figure 8 shows the measured dependence of the average
VDD min of the inverter, ×4 inverter, 2NAND and 3NAND
RO’s on the number of stages. In 2NAND, an nMOS tran-

Fig. 8 Measured dependence of average VDD min of all RO lots on
number of stages.

sistor connected to VS S is used for signal propagation, andthe gate of the other nMOS transistor is tied to VDD . The
lowest VDD min was 58 mV for the 11-stage RO’s. The threelines corresponding to the inverter RO’s show the measured
average VDD min in three diﬀerent lots. While increasing thenumber of stages and the number of stacked transistors increases VDD min , the wide gate width decreases VDD min .
The three lines of the inverter, 2NAND and 3NAND

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RO’s have similar gradients but diﬀerent oﬀsets. The gradient is determined by the transistor variations, and the oﬀsets
are determined by the imbalance between the current drivability of nMOS and that of pMOS. In this work, 3NAND
RO’s, have the highest average VDD min , because both Wn andW p are the same for the inverter, 2NAND and 3NAND RO’s
and the 3NAND RO’s have the largest imbalance in current
drivability. The imbalance, however, can be solved by tuning the W p /Wn ratio; this tuning minimizes VDD min because
VINV becomes equal to VDD /2 after tuning. The gradients ofcurves for inverter RO’s and ×4 inverter RO’s in Fig. 8 are
diﬀerent, because the VT H variations of the ×4 inverter RO’s
are less than that of the inverter RO’s.
3.

Analysis of V D D min

3.1 Analysis of VDD min with SPICE
The origin of VDD min is analyzed by Monte Carlo SPICE
simulations. Figure 9(a) shows the schematic of the simulated 11-stage RO’s where each transistor has a random
VT H . The inverter chain with the input of VDD is simulated.
Figure 9(b) shows the node voltages (V1 − V11 ) and the inversion voltages (VINV ’s) of the inverters. VINV is definedas the voltage when the input and output of each inverter isshorted, which is equivalent to the logic threshold of the inverter. Normally, the logical low of V1 − V11 is lower than
VINV and the logical high of V1 − V11 is higher than VIN . The
inverter chain, however, has a functional error at the #7 and#8 inverters, because the #7 inverter has slow nMOS and fast
pMOS, VINV of the #7 inverter is high, and the logical lowof V7 (VOUT LOW 7 ) is higher than VINV of the #8 inverter.
The functional error stops the RO oscillation.

Fig. 9 (a) Simulated 11-stage inverter chain where each transistor has
random VT H . (b) Node voltages (V1 − V11 ) and inversion voltages (VINV ’s)of inverters.

3.2 Comparison of Measured and Calculated VDD min
In order to investigate the increasing average VDD min with
the number of stages, the simulations of VDD min from 11stage to 1 Mega-stage RO’s are required. However, the simulations of VDD min of up to 1 Mega-stage RO’s by Monte
Carlo SPICE take too long and are not practical. Therefore,
VDD min is calculated using the subthreshold current modelwith random VT H variations, and the results are comparedwith the measured results. Equation (1) shows the drain current model of MOSFET in the subthreshold region.
ID = C1 eC2 (VGS −VT H ) (1 − e−C3 VDS )(1)

ID is the drain current, VGS is the gate-to-source voltage and VDS is the drain-to-source voltage. C1 , C2 and C3
are constants. In the CMOS inverter, the input-output characteristic of the inverter is derived by equating ID of nMOS
and pMOS. Figure 10 shows the inverter characteristics determined by SPICE and the calculation with Eq. (1). MATLAB was used for the calculation. VDD was varied from
50 mV to 0.4 V. The calculation is verified by comparison
with the result of SPICE. Below VDD of 0.2 V, the calculation error is small. In contrast, above VDD of 0.3 V, the calculation error is large, because the calculation includes only
the diﬀusion current (= subthreshold current) and neglects
the drift current (= strong inversion current).
Figure 11 shows the calculation steps for obtaining
VDD min of n-stage RO using Eq. (1), where n is an odd number. The Monte Carlo method is adopted in this calculation. VT H in Eq. (1) is varied by the Monte Carlo method,
because the transistors in the RO have random VT H variations. The probability distribution of VT H is assumed to be
Gaussian. First, the probability density function (PDF) of
the output (Vn−1 ) of the (n − 1)-stage inverter chain with the
input of 0 V is calculated by cascading the (n − 1)-stage inverters as shown in Fig. 11(b). Although the correct Vn−1 islow, Fig. 11(b) shows some incorrect high Vn−1 values due
to functional error. Figure 11(c) shows the probability of anerror (= logic low) that occurs at Vn . Figure 11(d) shows theprobability of Vn error derived by multiplying the value in
Fig. 11(b) with that in Fig. 11(c). Finally, Fig. 11(e) shows

Fig. 10Inverter characteristics obtained using SPICE and Matlab.

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Table 1

Several sets of σVT H ’s of nMOS and pMOS used in calculation.

Fig. 12 Measured and calculated dependences of average VDD min of
inverter RO’s on the number of stages.

Fig. 11 Calculation steps of VDD min of n-stage RO. (a) Calculated nstage inverters. (b) Probability of output of (n − 1)-stage inverter chain with
input of 0 V. (c) Probability of logical low (=error) of Vn . (d) Probabilityof Vn error dependence on Vn−1 . (e) Probability of Vn error dependence on
VDD .

the probability of Vn error derived by integrating the value
in Fig. 11(d). A value obtained from this integration corresponds to a point in Fig. 11(e) at a given VDD . The curvein Fig. 11(e) is obtained by sweeping VDD , and integrating
the value in Fig. 11(d), which is drawn at each VDD . Strictly
speaking, the probability of Vn error in the n-stage inverter
chain with the input of VDD should also be calculated andadded to Fig. 11(e). However, the inputs of 0 V or VDD aresymmetrical. Therefore, VDD min is defined as VDD when theprobability of Vn error equals to 25%, as shown in Fig. 11(e).
Table 1 shows the 4 sets of σVT H ’s of nMOS andpMOS used in the calculation. σVT H ’s are originally determined from the Pelgrom plot, however, σVT H ’s are varied as
the fitting parameter to fit the calculated result to the measured results. Figure 12 shows the measured and calculated
dependences of the average VDD min of inverter RO’s on thenumber of stages. The measured results for ×4 inverter RO’s
are also plotted. The calculation shows the expected increasing gradients and oﬀsets with increasing σVT H , which
confirm the tendency of the measurement. Two conceivablereasons for the quantitative error between the measurement
and MATLAB are (1) only VT H variations are considered in
the calculation and no other variations are not considered;(2) The inverter characteristic error increases with increasing VDD, as shown in Fig. 10, because the model includes
only the subthreshold current and neglects the strong inversion current.
4.

Fine-Grain Adaptive Body Bias Control to Reduce
V D D minAn increasing VDD min as the number of stages increases is
not acceptable. Fine-grain adaptive body bias control is effective for compensating for the intra die systematic VT H
variations [9]. Its eﬀectiveness on the intra die random
VT H variations, however, is not clear. The required circuit
block size for fine-grain control is also unclear. Therefore,
VDD min has been extracted by Monte Carlo SPICE simulations for diﬀerent grain sizes. Figure 13 shows the initialand compensated VDD min for the 11-stage RO. The body bias

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VDD min is low. In contrast, when they are unbalanced,
VDD min is high [3], [4]. The initial VDD min is 91 mV whenboth body biases are 0 V. Common body bias control enables
the reduction of reducing VDD min to 87 mV, i.e. by 4 mV
only. This is in agreement with the simulation results andshows that coarse-grain body bias control is not eﬀective insignificantly reducing VDD min .
When independent body bias is applied for every 2 inverters, VDD min decreases to 85 mV, as shown in Fig. 13(c).
In contrast, when inverter-by-inverter body bias is applied, VDD min is drastically reduced to 43 mV, as shown in
Fig. 13(d). Despite the significant improvement, inverterby-inverter body bias control is impractical because of thelarge area penalty. Therefore, when granularity is more than
2 inverters, fine-grain adaptive body bias control is not eﬀective for compensating the intra die random VT H variations inultra low-voltage logic circuits.
5.

Fig. 13 Initial and compensated VDD min by various fine-grain adaptive
body bias controls for 11-stage RO. (a) No body bias. (b) Common bodybias. (c) Body bias for every 2 inverters. (d) Inverter-by-inverter body bias.

Conclusions

The minimum operation voltage (VDD min ) of 90 nm CMOS
logic gates has been investigated using ring oscillators. The
measured average VDD min of inverter RO’s increased from
90 mV to 343 mV when the number of RO stages increased
from 11 to 1 Mega, which indicates the diﬃculty of VDD
scaling in large-scale subthreshold logic circuits. Whereas
increasing the number of stages and the number of stacked
transistors increases VDD min , a large gate width decreases
VDD min . It should be noted that these results are only one example of the process used in this study, because these measurement results have process dependence.
The dependence of VDD min on the number of stages wascalculated with the subthreshold current model with random
threshold voltage variations, and the tendency revealed by
the measurement was confirmed. Lowering VDD min is diﬃcult, because the compensation of purely random VT H variations would require impractical inverter-by-inverter adaptive
body bias control.
Acknowledgments

Fig. 14 Measured VDD min dependence of body bias of both nMOS andpMOS for 11-stage RO.

of pMOS is adaptively controlled to minimize VDD min andthe body bias of nMOS is fixed. When a common bodybias is applied to the 11 inverters (Fig. 13(b)), VDD min is improved from 89 mV to 87 mV, because the current drivabilityof nMOS and pMOS is balanced and VINV becomes equal to
VDD /2. The VDD min reduction by common body bias control
is also verified by the measurement results.
Figure 14 shows the measured VDD min dependence on
the body bias of both nMOS and pMOS for an 11-stage
RO. When VT H of nMOS and that of pMOS are balanced,

This work is partially supported by STARC. The VLSI chips
were fabricated using the chip fabrication program of the
VLSI Design and Education Center (VDEC), the University of Tokyo, with the collaboration of STARC, Fujitsu Microelectronics Limited, Panasonic Corporation, NEC Electronics Corporation, Renesas Technology Corporation, andToshiba Corporation.
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Tadashi Yasufuku
received the B.S. degree
in applied physics from Keio University, Japan
in 2007, and the M.S. degree in electronic engineering from the University of Tokyo, Japan in
2009. He is currently working toward a Ph.D.
degree. His research interests include sub/nearthreshold logic circuit design and switched converters.

Taro Niiyama
received the B.S. and M.S.
degrees in electronic engineering from the University of Tokyo, Japan, in 2006 and 2008, respectively. Now he is working in NTT DoCoMo, Inc.

Zhe Piao
received the B.S. degrees in electronic engineering from Tokyo Institute of Technology, Japan in 2007, and M.S. degrees in electronic engineering from the University of Tokyo,
Japan in 2009. Now he is working in HITACHI,
Ltd.

Koichi Ishidareceived the B.S. degree
in electronics engineering from the University
of Electro-Communications, Tokyo, Japan, in
1998, and received the M.S. and Ph.D. degrees
in electronics engineering from the Universityof Tokyo, Tokyo, Japan, in 2002 and 2005, respectively. He is currently working at Instituteof Industrial Science, the University of Tokyo as
a research associate. His research interests include low-voltage low-power CMOS analog circuit and RF wireless-communication circuit.

Masami Murakata
received the B.S.
and M.S. degree in electrical engineering from
Tokyo Science University, Japan, in 1980
and 1982, respectively. In 1982, he joined
TOSHIBA Research and Development center,
where he was engaged in development of Layout CAD system for custom VLSI. In 1995,
he moved to TOSHIBA semiconductor division.
In 2006, he joined Semiconductor Technology
Academic Research Center (STARC), where heis an associate general manager of Development
Department-1. His current interests are design methodology for system
LSI, design method for low power, variation aware design methodology
and design for manufacturing technology.

Makoto Takamiya
received the B.S., M.S.,
and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Japan, in 1995,
1997, and 2000, respectively. In 2000, he joined
NEC Corporation, Japan, where he was engaged
in the circuit design of high speed digital LSIs.
In 2005, he joined University of Tokyo, Japan,
where he is an associate professor of VLSI Design and Education Center. His research interests include the circuit design of the low-power
RF circuits, the ultra low-voltage digital circuits,
and the large area electronics with organic transistors. He is a member of
the technical program committee for IEEE Symposium on VLSI Circuits
and IEEE Custom Integrated Circuits Conference (CICC).

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Takayasu Sakurai
received the Ph.D. degree in EE from the University of Tokyo in 1981.
In 1981 he joined Toshiba Corporation, where
he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has
worked extensively on interconnect delay andcapacitance modeling known as Sakurai modeland alpha power-law MOS model. From 1988
through 1990, he was a visiting researcher at the
University of California Berkeley, where he conducted research in the field of VLSI CAD. From
1996, he has been a professor at the University of Tokyo, working on lowpower high-speed VLSI, memory design, interconnects, ubiquitous electronics, organic IC’s and large-area electronics. He has published more than
400 technical publications including 100 invited presentations and several
books and filed more than 200 patents. He served as a conference chairfor the Symp. on VLSI Circuits, and ICICDT, a vice chair for ASPDAC, a
TPC chair for the first A-SSCC, and VLSI symp. and a program committee
member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED,
and other international conferences. He will be an executive committee
chair for VLSI Symposia and a steering committee chair for A-SSCC from2010. He is a recepient of 2010 IEEE Donald O. Pederson Award in SolidState Circuits, 2009 achievement award of IEICE, 2005 IEEE ICICDT
award, 2004 IEEE Takuo Sugano award and 2005 P&I patent of the year
award and four product awards. He gave keynote speech at more than 50
conferences including ISSCC, ESSCIRC and ISLPED. He was an elected
AdCom member for the IEEE Solid-State Circuits Society and an IEEE
CAS and SSCS distinguished lecturer. He is a STARC Fellow and an IEEE
Fellow.