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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 52, NO. 11, NOVEMBER 2017

A Low-Power CMOS Crystal Oscillator Usinga Stacked-Amplifier Architecture
Shunta Iguchi, Member, IEEE, Takayasu Sakurai, Fellow, IEEE, and Makoto Takamiya, Senior Member, IEEE
Abstract— This paper presents a low-power 39.25-MHz crystal
oscillator with a new stacked-amplifier architecture achieving
the smallest figure of merit (FoM) ever reported for a crystal
oscillator for wireless communications. Theoretical analyses ofthe power consumption and the phase noise (PN) in the proposed
stacked-amplifier architecture are newly provided to clarify thereason why the proposed stacked-amplifier architecture achieves
the smallest FoM. Additionally, a new self-forward-body-biasing
technique and flicker noise suppression technique are shown to
reduce the minimum operational supply voltage (VDD(MIN)) and
the PN, respectively. The proposed 3.3-V, 39.25-MHz stackedamplifier crystal oscillator fabricated in a 65-nm CMOS process
exhibits the smallest FoM for a crystal oscillator of −248 dBc/Hz
with a power consumption of 19 µW and PN of −139 dBc/Hz
at 1-kHz offset frequency. The relative frequency errors among
11 samples at temperatures of −30 °C to 80 °C and for±10% supply voltage variation are ±10.5 ppm and ±0.12 ppm,
respectively. The long-term frequency error is −0.98 ppm in thefirst year (=365 days).
Index Terms— CMOS, crystal oscillator, low noise, low power,
quartz crystal, stacked-amplifier architecture.

I. I NTRODUCTIONCRYSTAL oscillators have undergone revolutionary
decades every 30–40 years since their invention by
Nicolson [1] and Cady [2] in the 1920s. Many technicalchallenges to reduce the aging effect [3] around World War II
in the 1940s–50s and to achieve low-power operation forwristwatches in the 1970s–80s [4], [5] were overcome owing
to the huge demand for crystal oscillators. In the 2020s,
the Internet of Things (IoT) [6] is a promising application
to provide the huge demand for crystal oscillators because it
requires a huge capacity for wireless communications. The
low-power and low-noise operation of crystal oscillators isthe most fundamental requirement for energy-efficient wirelesscommunications (e.g., Bluetooth with low energy (BLE) [7])in IoT applications. The tradeoff between the power consumption (Pdc )1 and the single-sideband phase noise (PN)
in oscillator circuits can be evaluated using the following
figure of merit (FoM) [8] with the unit of dBc/Hz:
FoM = PN − 20 log10 ( f OSC / f OFFSET ) + 10 log10 (Pdc )(1)

Manuscript received February 17, 2017; revised April 30, 2017 andJune 24, 2017; accepted August 14, 2017. Date of publication
September 13, 2017; date of current version October 23, 2017. This work
was partly supported by STARC. This paper was approved by Associate
Editor Seonghwan Cho. (Corresponding author: Shunta Iguchi.)The authors are with The University of Tokyo, Tokyo 153-8505, Japan(e-mail: shunta.iguchi.jp@ieee.org).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2017.2743174
1 Note that P
dc in (1) must be calculated in the unit of milliwatt forconsistency with the unit of dBc/Hz in (1).

where f OSC is the oscillation frequency, f OFFSET is the offset
frequency from f OSC , and the unit of PN is dBc/Hz. For
the low-power and low-noise operation of oscillator circuits,
circuit designers should aim to achieve a smaller FoM thanthat in conventional studies.
This paper reports a low-power and low-noise crystal
oscillator with the smallest FoM ever reported for a crystal
oscillator. In Section II, the concept of a stacked-amplifierarchitecture [9] and theoretical analyses of Pdc and PN in thestacked-amplifier architecture are newly presented to clarify
its advantages for reducing FoM, thereby demonstrating the
low-power and low-noise operation of the crystal oscillator.
In Section III, the detailed circuit designs with the stackedamplifier architecture are shown. Additionally, a new selfforward-body-biasing technique and flicker noise suppression
technique are demonstrated that, respectively, reduce Pdc and
PN for the proposed crystal oscillator. To verify the low-power,
low-noise, and reliable operation of the proposed crystal
oscillator, measurement results are given in Section IV. Finally,
conclusions are given in Section V.
II. A NALYSIS OF S TACKED -A MPLIFIER A RCHITECTURE
To clarify the advantages of the stacked-amplifier architecture for achieving low-power and low-noise operation,
theoretical analyses of Pdc and PN are newly presented inthis section. The analyses clarify the reason why the stackedamplifier architecture can achieve the smallest FoM.
A. Power Reduction With Stacked-Amplifier Architecture
The power consumption in many crystal oscillator
architectures [5], [10]–[16] is mainly determined by anegative resistance generator consisting of an amplifier circuit(e.g., an inverter amplifier and differential amplifier). Several
techniques using an energy-efficient amplifier operating in the
weak-inversion region (overdrive voltage: VOV < 0) [5], [16],an intermittent amplifier [17], [18], and a pulsed
driver [19], [20] have been reported for achieving low-power
operation. However, these conventional techniques targeteda low-frequency (e.g., 32.768 kHz) real-time-clock (RTC)
generator because PN in an RTC does not make significant
problems as a system clock. The temperature dependence
and aging effect of the oscillation frequency are themajor problems in such applications. On the other hand,
high-frequency (>10 MHz) crystal oscillators for wirelesscommunications require a low PN because the PN in a
crystal oscillator and phase-locked loop (PLL)2 degrades the
2 The PN in the crystal oscillator is amplified by the frequency multiplication
ratio in the PLL. In a case of upconversion from 24 MHz to 2.4 GHz, the PN in
the PLL is 40 dB (=20 × log10 (100)) larger than that in the crystal oscillator.

0018-9200 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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IGUCHI et al.: LOW-POWER CMOS CRYSTAL OSCILLATOR USING STACKED-AMPLIFIER ARCHITECTURE

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Fig. 1. Schematics of (a) conventional one-stage CMOS Pierce crystal oscillator, (b) proposed stacked-amplifier crystal oscillator, (c) equivalent circuit of
the quartz crystal, and (d) table comparing properties of a conventional oscillator and the proposed oscillator.

sensitivity of wireless receivers owing to adjacent-channelinterference.
To achieve low-power and low-noise operation, the stackedamplifier architecture was proposed in [9]. Fig. 1(a)–(d) shows
the schematics of a conventional one-stage CMOS Pierce crystal oscillator, a proposed stacked-amplifier crystal oscillator
with N-stages stacked amplifiers, an equivalent circuit of thequartz crystal, and a table comparing the properties of a conventional oscillator and the proposed oscillator, respectively.
C1 is the gate-to-ground capacitor, C2 is the drain-to-groundcapacitor, C3 is the parallel parasitic capacitor in the quartz
crystal, and R3 is the feedback resistor. CM , L M , and RM
are the motional capacitor, inductor, and resistor in the quartz
crystal, respectively. The current waveform (IM ) in the nodecontaining CM , L M , and RM is expressed as |IM | × cos(ωt),
where |IM | is the amplitude of the current swing, ω is theangular frequency, and t is the time. The inverter amplifiersin Fig. 1(a) and (b) configure the negative resistance (RN ) to
provide energy to the resonator of the quartz crystal. In manycases, the amplifiers are biased by a current source with abias current (ID ) to reduce the sensitivity to process, voltage,
and temperature (PVT) variations. The inverter amplifiers
except for that in the lowest stage (N = 1) in Fig. 1(b)consist of a CMOS inverter, a decoupling capacitor (CD ), andtwo coupling capacitors at the gate (CCG ) and drain (CCD ).

|V1 | and |V2 | are the amplitudes of the voltage swing at thegate and drain of the inverter amplifier, respectively. Assumingthat C1 = C2 and gm(TOTAL)  ωOSC for simplicity, the equivalent RN [5], [21] in Fig. 1(a) and (b) is approximated as
gm(TOTAL) C1 C2RN = − 2
2 (C C + C C + C C )2
gm(TOTAL) C32 + ωOSC
1 2
2 3
3 1
gm(TOTAL)≈− 2(2)
ωOSC (C1 + 2C3 )2where gm(TOTAL) is the equivalent transconductance of theinverter amplifiers and ωOSC is the angular frequency of f OSC .
In the initial state, the absolute value of RN (|RN |) is set toapproximately five times larger than RM to ensure reliableand quick startup [22]. In the steady state, |RN | settles down
to RM owing to the nonlinearity of the amplifiers. This
indicates that the characteristic of the quartz crystal (=RM )is the fundamental limitation in minimizing the value ofgm(TOTAL) and the corresponding power consumption of thecrystal oscillators. In Fig. 1(a), gm(TOTAL) is simply given by
the transconductance (gm0 ) in an inverter amplifier. On theother hand, gm(TOTAL) in Fig. 1(b) is given bygm(TOTAL) =

N

i=1

gmi = gm1 + gm2 + · · · + gmN

(3)

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 52, NO. 11, NOVEMBER 2017

where gmN is the transconductance of the inverter amplifiers in the Nth stage. When the impedances of CD , CCG ,and CCD are approximated to zero at f OSC , the stacked
amplifiers in Fig. 1(b) are equivalent to a transconductance
amplifier with a transconductance of gm(TOTAL), because all
the stacked amplifiers are virtually connected in parallelat f OSC . The minimum transconductance of each inverter
amplifier in the proposed stacked-amplifier crystal oscillator
is N times smaller than that of the conventional one-stage
CMOS Pierce crystal oscillator. The smaller transconductancein the proposed architecture makes it possible to reduce
Pdc compared with that of conventional crystal oscillators.
This discussion is summarized in Fig. 1(d), which clarifies
the difference between the conventional architecture and the
proposed stacked-amplifier architecture.
Subsequently, the power consumption of the stackedamplifier crystal oscillator is analytically derived using ideal
long-channel models [23] to verify the power reduction by the
proposed architecture. The theoretical analyses are performed
using fixed-size amplifiers because the aim of this paper is todesign a low-power crystal oscillator for low-energy wirelesscommunications (e.g., BLE). Such low-power operation isa more essential requirement than small-area implementation for this application. For simplicity, it is assumed thatthe transconductances (gmN and gmP ) and threshold voltages(VTHN and VTHP ) of the NMOS and PMOS transistors are
the same without random variations. The lengths of the
NMOS (L N ) and PMOS (L P ) transistors are the same, andtheir widths (WN and WP ) are varied as n × WN = WP tosatisfy the condition gmN = gmP , where n is the relative size
ratio of WP compared with WN .
When the sizes of the inverter amplifiers in each stage
are fixed for the stacked-amplifier architecture with N-stages
stacked amplifiers, VOV is scaled down by a factor of N. Then,the relationship between gmN , gmP , gm(TOTAL), ID , and N isgiven asgm(TOTAL) = 2μN COX (WN /L N )ID(4)
gmN = gmP =2N
where μN is the carrier mobility in the NMOS transistor and
COX is the unit capacitance of the gate oxide. Substituting (4)into (2), ID in the case of N-stages stacked amplifiers isderived as
ID =4 |R |2 (C + 2C )4
ωOSC
1
N
1
3
∝ 2.
2
8N μN COX (WN /L N )N(5)Equation (5) clarifies that ID and Pdc are proportional to 1/N 2 .
The power consumption of the proposed stacked-amplifierarchitecture is 16 times smaller than that of the conventional
one-stage CMOS Pierce crystal oscillator when four-stage
stacked amplifiers are available. To verify the consistency ofthe derived equation, the simulated N dependence of ID isshown in Fig. 2. The simulated results show that the power
is reduced by a factor of N 2 within a relative error of 42%.
The simulated ID is reduced by 91% from 65.4 μA (N = 1)
to 5.8 μA (N = 4). It is verified that the proposed stackedamplifier architecture can reduce Pdc by increasing N. Notethat the maximum value of N is limited by the minimum

Fig. 2. Simulated N dependence of ID at |RN | of 50 . The solid line
shows a function of 1/N 2 fit using the value of ID at N = 1 to verify theconsistency of the proportional relationship with the factor of 1/N 2 .

operational supply voltage (VDD(MIN)) and the design specification for PVT variations.
VDD(MIN) in the stacked-amplifier architecture is higher thanthat in the conventional one-stage Pierce crystal oscillator;
however, the higher VDD(MIN) is not a critical problem inmany cases because crystal oscillators are often powered by
I/O voltage (e.g., 3.3 V). There are several reasons why crystal
oscillators utilize I/O voltage. Firstly, crystal oscillators needto start up first and provide the clock for all sub-blocks ina system-on-chip (SoC). Second, crystal oscillators are often
designed as an I/O cell for small-area implementation withelectrostatic discharge protection circuits and I/O pads. Third,
the power supply of a crystal oscillator should be isolated
from the core supply voltage because the harmonics of theoscillation frequency in the crystal oscillator propagate tonoise-sensitive circuits (e.g., wireless receivers) through thepower supply.
In contrast, the maximum voltage swing in a crystal oscillator should be smaller than a certain voltage (e.g., 0.8 V) to
minimize the long-term frequency variation (e.g., 1 ppm/year).
The large difference between the supply voltage and oscillation
amplitude (e.g., 3.3 V − 0.8 V = 2.5 V) is the fundamental
limitation in reducing the power consumption. This large
voltage difference has been decreased by employing a resistive
divider consisting of a low-dropout (LDO) regulator and a current source in conventional approaches [13], [16]. The power
loss in the resistive divider is not negligible in low-power
applications. On the other hand, dc–dc converters (e.g., Buckconverters) are not available for low-noise crystal oscillator
designs because the output noise in a dc–dc converter is significantly larger than that in an LDO. Additionally, the overheadsof the area and cost of a capacitor, inductor, and I/O pads are
not feasible for low-cost IoT applications. The advantage ofthe proposed stacked-amplifier architecture is that it utilizes
the wasted voltage drop to increase gm(TOTAL). The proposedarchitecture reduces the total power consumption, including
the voltage drop in the LDO and current source, comparedwith conventional approaches using one-stage Pierce crystal
oscillators.
B. Phase Noise in Stacked-Amplifier Architecture
The FoM in oscillator circuits is calculated from Pdc and
PN using (1). A detailed analysis of the noise in the proposed
stacked-amplifier architecture is also important to clarify its

IGUCHI et al.: LOW-POWER CMOS CRYSTAL OSCILLATOR USING STACKED-AMPLIFIER ARCHITECTURE

advantages compared with conventional architectures. In crystal oscillator design, PN for f OFFSET of 1–10 kHz should be
reduced to as low as possible because it is difficult to suppress
PN in this frequency range by using a loop filter in a PLL. Thissection provides a theoretical analysis of the PN due to flicker
noise because the contribution of flicker noise is considerablylarger than that of thermal noise in this frequency range. The
N dependence of PN is analytically discussed using linear
time-varying (LTV) theory [24], [25].
The spectrum of PN at a low fOFFSET (=1/ f 3 region)
is mainly determined by the flicker noise in transistors
and the upconversion effect due to the impulse response in
LTV systems. In accordance with LTV theory and a theoreticalanalysis [26], PN for a Pierce crystal oscillator in the 1/ f 3
region (PN 1/f3 ) is given as


2 I2
dc
CM 2
D_n(rms)
P N 1/f3 =(6)2
C2
2(C2 |V2 |)2 ωOFFSET
where dc is the direct current (dc) value of the effective impulse sensitivity function for a sinusoidal voltage of|V2 | × sin(ωt) and ID_n(rms) is the root-mean-square (RMS)
value of the noise current in ID for a 1-Hz bandwidth.
The angular frequency of f OFFSET is denoted as ωOFFSET .
Equation (6) can be applied3 to all types of Pierce crystal oscillator including the one-stage CMOS Pierce crystal
oscillator and the stacked-amplifier crystal oscillator shownin Fig. 1. ID_n(rms) is one of a few controllable parameters forcircuit designers. PN in the 1/ f 3 region should be reduced byensuring a small ID_n(rms) .
To analyze the N dependence of PN in the 1/ f 3 region;
at first, ID_n(rms) for different numbers of stacked amplifiersis derived because ID_n(rms) can easily be calculated using asmall-signal approximation. According to [26], the square of2) at the gate of
the equivalent flicker noise voltage (V1/f_n(rms)a transistor is given as
K
(7)
ωLW
where K is the flicker noise voltage constant, L and W
are the length and width of the transistors, respectively.
In the following discussion, the values of K in NMOS andPMOS transistors are denoted as K N and K P , respectively.
2
ID_n(rms)
with the N-stages stacked amplifiers is derived
as2=
V1/f_n(rms)2(n K N + K P )gm(TOTAL)

1
.
(8)
N3
N WN
The detailed derivation of (8) is given in the Appendix.
2
Equation (8) clarifies that ID_n(rms)
is reduced by a factor of3
N when N-stages stacked amplifiers are used for the proposed stacked-amplifier architecture. A comparison between
a theoretical calculation using (8) and simulation results isshown in Fig. 3. The calculated results match to the simulation
results within a relative error of 21%. The small error verifies
that (8) is consistent with the simulation results. For the2
ID_n(rms)=

16nωN 3 L∝

3 Note that the theoretical calculation of 
dc is complicated even in theideal case assuming sinusoidal voltage waveforms. For simplicity, this study
assumes that dc is independent of N .

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2
Fig. 3. Simulated frequency dependences of ID_n(rms)with |RN | of 50 
at N = 1, 2, 3, and 4. Solid lines show the results calculated using (8). The
simulated and calculated results verify that the flicker noise in ID is inversely
proportional to N 3 .

calculations using (8), K N and K P are extracted by SPICE
simulation because they depend on the overdrive voltage ofthe transistors [27]. The N dependences of K N and K P are
not incorporated in (8) for simplicity. It is concluded that the
proposed stacked-amplifier architecture can reduce both Pdc
2
and ID_n(rms)in the 1/ f 3 region by increasing N.
To calculate PN, ID_n(rms) should be normalized by |V2 |(≈|V1|). The accurate estimation of |V2 | is difficult because
the oscillation amplitude is determined by the nonlinearity inthe inverter amplifiers. Experimentally, |V2 | is approximately
proportional to N −β (e.g., β = 0.73 when N = 2 andβ = 0.56 when N = 4). To simplify the discussion, it isassumed that |V2 | is inversely proportional to N because
the stacked amplifiers are considered as an N-stages voltage
divider. The maximum oscillation swing is limited by theequivalent supply voltage (≈VDD/N) in each stage because
the stacked amplifiers operate as CMOS inverters in the steadystate. Note that this assumption is a pessimistic approximationcompared with the experimental results. Then, N dependenceof the PN is obtained from (6) asP N 1/f3 ∝2ID_n(rms)|V2 |2

∝

1
.
N

(9)

Equation (9) shows that PN in the 1/ f 3 region is reducedby the proposed stacked-amplifier architecture. Finally, theN dependence of FoM is also easily derived using (5) and (9).
It is concluded that the proposed stacked-amplifier architecture
can reduce FoM by 10 × log10 (N 3 ) dB, thereby achieving thesmallest ever reported value of FoM for crystal oscillators.
III. C IRCUIT I MPLEMENTATION
Fig. 4(a) and (b) shows the schematics of a crystal
oscillator with the proposed stacked-amplifier architecture
for N = 4 and an amplifier cell with a proposed selfforward-body-biasing technique, respectively. To minimize thepower consumption, 1.2-V core transistors and 3.3-V I/Otransistors are used in the deep n-well process. The proposed self-forward-body-biasing technique reduces the threshold voltage (VTH ) of transistors in the stacked amplifiers for3010

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Fig. 4. Schematics of (a) crystal oscillator with the proposed stacked-amplifier architecture and (b) amplifier cell with the proposed self-forward-body-biasing
technique.
TABLE ID ESIGN PARAMETERS

low-voltage operation. CFBB , R3L , and R3R are used toconfigure the low-pass filter (LPF) to provide the forward
body bias voltage on the substrate in the NMOS and PMOS
transistors. To compensate the variation in |RN | due to the
PVT variations, a constant-gm biasing technique is used for the
proposed stacked-amplifier architecture. An area-efficient LPF
is also added to suppress the flicker noise in the constant-gm
bias generator. The values of all the capacitors and resistors
in Fig. 4 are summarized in Table I.
The stacked amplifiers are equivalent to a parallel connection at oscillation frequency. To reduce the power loss
owing to the phase mismatch, the phase differences among thestacked amplifiers should be small. This means that the cutoff
frequency ( f HPF ) of a high-pass filter (HPF) consisting of CCG

and the input resistance of the stacked amplifiers should belower than f OSC . The simulated voltage waveforms of thefour stages of the stacked amplifiers are shown in Fig. 5 toverify the small phase difference of 1.2° among the stages.
The simulation results do not include any parasitic and device
mismatches; however, non-ideal effects do not have a criticaleffect on the phase mismatch when fHPF is lower than f OSC .
The simulated phase difference of 1.2° in Fig. 5 shows thatf HPF is approximately 50 times lower than fOSC . When 10%
random mismatches are assumed among the stages, the mismatches generate a phase error of 0.1° (=tan−1 (0.1 × 1/50)).
The calculated small phase error of 0.1° verifies that the
proposed architecture is insensitive to parasitic and device
mismatches. The voltage drop in each stage is also estimatedIGUCHI et al.: LOW-POWER CMOS CRYSTAL OSCILLATOR USING STACKED-AMPLIFIER ARCHITECTURE

Fig. 5.
Simulated voltage waveforms at OUT, VG2 , VG3 , and VG4 in
the proposed stacked-amplifier crystal oscillator. The waveform at OUT isdelayed by 83 ps (=1.2°) compared with that at VG2 . The phase differences
between VG2 , VG3 , and VG4 are approximately zero owing to the symmetricalconfigurations in the second to fourth stages.

technique in Fig. 6, the substrates of the NMOS and PMOS
transistors are connected to the sources in order to prevent the
body effect. The reduced VDD(MIN) makes it possible to use
the four-stages stacked amplifiers at the supply voltage (VDD )of 3.3 V. Note that the leakage current is not increased by
the self-forward-body-biasing technique because the leakage
current is limited by a 3.3-V I/O transistor (M4 ). VTH in an
I/O transistor is approximately two times higher than that ina core transistor. This indicates that the off-resistance in thestacked amplifiers is mainly determined by the I/O transistor.
The proposed self-forward-body-biasing technique reduces
the variation of |RN | in the worst case; however, it does
not reduce the temperature and supply voltage dependencesof |RN |. To compensate the PVT variations of |RN | in thestacked amplifiers, a constant-gm bias generator is implemented. Fig. 7 shows the simulated relative variation of|RN | with and without the constant-gm bias generator. Using
the constant-gm biasing technique, the supply voltage andtemperature dependences of |RN | are respectively reduced by
89% (±24% → ±3%) and 45% (±21% → ±12%) comparedwith those without the constant-gm bias generator.
The constant-gm biasing technique increases PN owing to
the flicker noise in the constant-gm bias generator, although
the technique can reduce the PVT variation of |RN |. To reduce
the flicker noise from the constant-gm bias generator, an LPF
using an active resistor (M3 ) and an amplified capacitor (CLPF )based on the Miller effect is developed for the low-noise
operation of the crystal oscillator. The cutoff frequency of the
LPF ( f LPF ) is given by
f LPF =

Fig. 6. Simulated relative variation of |RN | with and without the proposed
self-forward-body-biasing technique in the worst case (=low temperature andslow corner). VDD(MIN) with the proposed technique is 0.3 V lower than thatwithout the proposed technique.

from the amplitude of the waveforms in Fig. 5. The voltage
drops across the stacked amplifiers at N = 1, 2, 3, and 4 are
419, 397, 397, and 396 mV, respectively. It is thus verified
that the stacked amplifiers in each stage equally provide thetransconductance.
Fig. 6 shows the simulated relative variation of |RN | withand without the proposed self-forward-body-biasing technique.
As discussed above, the proposed stacked-amplifier architecture reduces Pdc and PN; however, VDD(MIN) is increased inproportional to N. VDD(MIN) is the fundamental limitationin maximizing the value of N in the proposed stackedamplifier architecture. To reduce VDD(MIN), specifically in theworst case of a low temperature and slow corner, a new
self-forward-body-biasing technique is demonstrated in thispaper. This technique reduces VTH in the NMOS and PMOS
transistors by the body effect. Using the self-forward-bodybiasing technique, VDD(MIN) in the worst case is reduced by
0.3 V compared with that in a stacked-amplifier crystal oscillator without the proposed technique. Without the proposed3011

1
2π(1 + ALPF )RON3 CLPF

(10)

where ALPF is the voltage gain of the common source amplifierof M4 and RON3 is the on-resistance of M3 in the linear region.
To suppress the flicker noise around 1 kHz, f LPF should
be smaller than 100 Hz. In this paper, RON3 of 27 M is
implemented with a small area of 1800 μm2 because RBIAS
is amplified by the size ratio of M1 and M3 as
RON3 ∝ RBIAS × (L M3 WM1 )/(L M1 WM3 ).

(11)

The areas of CLPF and RON3 with the amplified capacitor
and active resistor are approximately 10 times and 30 times4
smaller than those with only passive components, respectively.
2
Fig. 8 shows the simulated frequency dependences of ID_n(rms)with and without the area-efficient LPF. The simulation result
verifies that the area-efficient LPF suppresses the flicker noiseof the constant-gm bias generator by 45 dB at 1 kHz.
IV. M EASUREMENT R ESULTS AND D ISCUSSION
To demonstrate the low-power and low-noise operation of
the proposed stacked-amplifier architecture, a crystal oscillator
is fabricated in a 65-nm CMOS process. Fig. 9 shows thedie micrograph of the fabricated stacked-amplifier crystal
oscillator with a core area of 420 μm × 210 μm. The large
area of CD1 , CD2 , CD3 , and CD4 is a disadvantage of the
4 Assumed that the poly resistor has a sheet resistance of 500  and a widthof 1 μm.

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Fig. 7. Simulated relative variation of |RN | with and without the constant-gm bias generator. (a) and (c) Supply voltage and temperature dependences of |RN |without the bias generator, respectively. (b) and (d) Supply voltage and temperature dependences of |RN | with the bias generator, respectively.

Fig. 9.
2
Fig. 8. Simulated frequency dependences of ID_n(rms)
at |RN | of 50  withand without the proposed LPF. To clarify the noise suppression in the LPF,
only the noise generated by the constant-gm bias generator is included in
the simulation. The noise current at 1 kHz with the proposed LPF is 45 dB
smaller than that without the LPF.

proposed stacked-amplifier architecture; however, the minimum die area of the SoC will be limited by the I/O pins
in many cases. Additionally, the total area of 88 200 μm2 is
not larger than that in conventional works [13], [28]. The area
overhead should be acceptable in most applications. In thispaper, the characteristic of the quartz crystal is the same asthat in [22] with a load capacitance of 8 pF. To achieve
an oscillation frequency of 39.25 MHz, C1 of 12 pF, andDie micrograph of test chip fabricated in 65-nm CMOS process.

C2 of 15 pF are mounted on an FR4 PCB. The reason why
C1 is smaller than C2 is to increase the oscillation amplitude
at OUT [29].
Fig. 10 shows the measured PN with and without an LPF in
the proposed stacked-amplifier crystal oscillator. By enabling
the LPF, PN at 1 kHz offset frequency is reduced from−122 dBc/Hz to −139 dBc/Hz. The 17-dB noise reduction
by the area-efficient LPF, consisting of an amplified capacitor
and active resistor, clarifies that it successfully suppresses the
flicker noise from the constant-gm generator. On the other
hand, PN at offset frequencies higher than 10 kHz is not
reduced because the thermal noise in an output buffer isdominant in this frequency range. A buffer circuit is requiredIGUCHI et al.: LOW-POWER CMOS CRYSTAL OSCILLATOR USING STACKED-AMPLIFIER ARCHITECTURE

3013

Fig. 10. Measured PN for the proposed stacked-amplifier crystal oscillator with and without the LPF. The PN at 1-kHz offset frequency is reduced by 17 dB
when using the proposed active LPF.

to provide a squire wave with a rail-to-rail swing for othercircuit blocks in integrated products. The power consumptionof a buffer circuit significantly depends on the requirementof the PN in the systems because the PN in a high offset
frequency (>100 kHz) is determined by the thermal noise
in a buffer circuit. The specification of the PN in lowpower and low-cost IoT applications would be 10–20 dB
higher than that in high-speed wireless transceivers. For IoT
applications, the power consumption in the buffer circuit will
be comparable (e.g., 1–10 μA) to that in a core circuit. For thefair comparison of the proposed techniques in a core circuit,the power consumption in a buffer circuit is not included forthe total power consumption because the power consumption
highly depends on the requirement in applications (e.g., swing
level and load impedance). Additionally, the dedicated buffer
circuit consisting of a source follower and open-drain output
in the test chip needs to drive an external load of 50  in ameasurement equipment (Keysight E5052B) for the low-noise
PN measurement. Such a huge drivability for a 50- load is
not required for commercial integrated products.
The variation of fOSC is the most important specification
for the reference clock generator. To verify that the proposed
techniques do not increase the variation of f OSC , the temperature and supply voltage dependences of f OSC for 11 samples
are measured as shown in Figs. 11 and 12, respectively.
Fig. 11(a) and (b) shows the measured temperature dependences of the absolute frequency variation and the relative
frequency variation, respectively. The absolute and relative
frequency variations at VDD of 3.3 V in the temperature rangeof −30 °C to 80 °C are ±15.8 and ±10.5 ppm, respectively.
The relative frequency variation with the same quartz crystal is±5.5 ppm [22] in the temperature range of −10 °C to 60 °C.
Note that each of the 11 samples are measured with a different

Fig. 11.
Measured temperature dependences of (a) absolute frequency
variation and (b) relative frequency variation for 11 samples.

PCB board. This indicates that the absolute frequency variations in Figs. 11 and 12 include the variations of the circuit,off-chip components, PCB, and quartz crystal. The frequency
variation of the 39.25-MHz quartz crystal (DSX221G) is±20 ppm at a temperature of 25 °C ± 3 °C. The absolute
frequency variations in Figs. 11 and 12 are considered tobe mainly determined by the variation of the quartz crystals. In the same temperature range, the measured frequency
variation in the proposed crystal oscillator is comparable to that in the conventional one-stage CMOS Pierce

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Fig. 12. Measured supply voltage dependences of (a) absolute frequency
variation and (b) relative frequency variation for 11 samples.

Fig. 13.
Measured time dependences of the frequency variation:(a) linear–linear plot and (b) log–linear plot. The predicted frequency variationin the first year (=365 days) is −0.98 ppm.

crystal oscillator. This verifies that the proposed techniques
do not increase the frequency variation.
In the same way, the measured supply voltage dependencesof the absolute frequency variation and the relative frequency
variation are shown in Figs. 12(a) and (b), respectively. The
absolute and relative frequency variations at a temperatureof 25 °C at VDD of 3.3 V ±10% are ±7.2 and ±0.12 ppm,
respectively. The supply voltage dependence of the frequency
variation in the proposed crystal oscillator is also well matchedto the relative frequency variation of ±0.6 ppm [22] in theconventional oscillator with VDD of 1.5 V ± 20%. These
measured results in Figs. 11 and 12 clearly show that the
proposed crystal oscillator can be used as a reference clock
generator for low-energy wireless communications.
Fig. 13(a) and (b) shows the measured time dependenceof the frequency variation as a linear–linear plot and a log–
linear plot, respectively. To evaluate the aging effect in the
proposed crystal oscillator, f OSC is measured for 32 days at atemperature of 25 °C and VDD of 3.3 V. The measured longterm frequency variation for 32 days is −0.57 ppm and thepredicted frequency variation in the first year (=365 days) is−0.98 ppm. The long-term frequency variation is derived byextrapolation of the logarithmic function [30] using the datafrom 10 to 32 days. The data until 10 days are excluded
from the extrapolation because f OSC is unstable in the first
several days. The measured long-term frequency variation of−0.98 ppm/year is comparable to that of conventional crystal
oscillators (e.g., 2.5 ppm/year [31]).
The Allan deviation is also used to evaluate the timedomain frequency stability of oscillators. To evaluate thefrequency stability of the proposed crystal oscillator, the Allan
deviation (σy ) is calculated from the measured PN in the offset
frequency of 1 Hz to 10 MHz using [32] fH
2
10PN/10 × sin4 (πτ f )d f
(12)
σy =
πτ f OSC
0

Fig. 14.

Measured start-up waveforms.

where f H is the upper cutoff frequency of the measuringsystem and τ is the observation time. The calculated Allan
deviations at τ = 0.1 and 1 s are 1.1 × 10−9 and 1.7 × 10−10,
respectively.
The measured start-up waveforms of the proposed crystal
oscillator are shown in Fig. 14. To prevent a long startup time (tSTART ) owing to the LPF used for flicker noise
suppression, the LPF is disabled during the startup. When
LPF_en is enabled after 4 ms from Amp_en, the measured
start-up time is 3.9 ms. The start-up time and energy are also
important specifications in IoT applications. Several quickstartup and energy-reduction techniques have been demonstrated recently [22], [33], [34]. These techniques can beapplicable to the proposed architecture because the stackedamplifier architecture is equivalent to the Pierce crystal oscillator. Using these techniques, the start-up time can easily be
reduced to less than 1 ms. The proposed architecture is able
to support the quick-startup and energy-reduction techniquesin low-energy IoT applications.

IGUCHI et al.: LOW-POWER CMOS CRYSTAL OSCILLATOR USING STACKED-AMPLIFIER ARCHITECTURE

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TABLE IIC OMPARISON W ITH P REVIOUS W ORKS

A summary of the performances of the proposed crystal oscillator [9] and a comparison with those in previous
works [13], [14], [17], [22], [28], [33] are shown in Table II
in chronological order. The proposed stacked-amplifier crystal oscillator demonstrates the smallest ever reported FoMof −248 dBc/Hz for a crystal oscillator. The values of FoM
in [9] and [22] are 30 dB larger than that in Table II, because
the power consumption was normalized by the unit of watt in
the previous publications. However, the power consumption
is normalized by the unit of milliwatt in many studies onhigh-frequency oscillators [8]. To prevent confusion due tothe different definitions among studies, all values of FoM
in Table II are calculated with the unit of milliwatt. The current
consumption of 5.8 μA is achieved by the proposed power
reduction technique of the stacked-amplifier architecture. The
relative frequency errors among the 11 samples at temperaturesof −30 °C to 80 °C and for ±10% supply voltage variation are±10.5 ppm and ±0.12 ppm (=±0.18 ppm/V), respectively.
V. C ONCLUSION
A low-power 39.25-MHz crystal oscillator with astacked-amplifier architecture was presented. The proposed
stacked-amplifier architecture reduces the power consumption
by 91% in the case of four stages of stacked amplifiers.
New theoretical analyses of the power consumption and PN
in a proposed stacked-amplifier crystal oscillator clarify thereason why the proposed oscillator achieves the smallest everreported FoM of −248 dBc/Hz with a power consumptionof 19 μW and PN of −139 dBc/Hz at 1-kHz offset frequency.
A new self-forward-body-biasing technique and flicker noise
suppression technique were also presented, which reduce theminimum operational supply voltage (VDD(MIN)) and the PN,
respectively. Using the proposed self-forward-body-biasing
technique, VDD(MIN) in the worst case (−30 °C and a slow
corner) is reduced by 0.3 V, thereby achieving reliable operation even with PVT variations. The measurement results

Fig. 15.

Equivalent circuit of the N -stages stacked amplifiers.

for 11 samples verify the reliable and accurate frequency
generation of the proposed crystal oscillator with relative
frequency errors of ±10.5 and ±0.12 ppm at temperature of−30 °C to 80 °C and for ±10% supply voltage variation,
respectively.
A PPENDIXD ERIVATION OF (8)The detailed derivation of (8) is given in this Appendix. The
equivalent circuit of the N-stages stacked amplifiers is shownin Fig. 15. The equivalent resistances of the NMOS and PMOS
transistors are denoted as REQ_N and REQ_P , respectively. The2) ofsquares of the equivalent flicker noise voltage (V1/f_n(rms)2
the NMOS and PMOS transistors are denoted as V1/f_n(rms)_N2
and V1/f_n(rms)_P, respectively. Using the relationship gmN =gmP = gm(TOTAL)/(2 × N) and Thevenin’s theorem, the total
equivalent resistance (REQ_TOTAL ) and the total square of the2equivalent flicker noise voltage (V1/f_n(rms)_TOTAL) are given
as


4N 2
1
1
=
+
(A1)
REQ_TOTAL = N ×
gmN
gmP
gm(TOTAL)

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and[17] S. Iguchi, A. Saito, Y. Zheng, K. Watanabe, T. Sakurai, and
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2
2
2
V1/f_n(rms)_TOTAL= N × (V1/f_n(rms)_N+ V1/f_n(rms)_P
)


KP
KN
. (A2)+= N×
ωL N WNωL P WP
2
Using (A1) and (A2), ID_n(rms)for the N-stages stacked
amplifiers is derived as2
ID_n(rms)=2
V1/f_n(rms)_TOTAL=

2(n K N + K P )gm(TOTAL)(A3)216nωN 3 L N WN
REQ_TOTAL
assuming with the relationships L N = L P and n ×WN = WP .
ACKNOWLEDGMENT
The authors would like to thank Y. Yoshihara, Y. Niki, andR. Fujimoto of Toshiba Corporation for technical discussions,and R. Shidachi and S. Lee of The University of Tokyo forsupport in the measurements.
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pp. 208–209.

Shunta Iguchi (S’12–M’16) received the B.S.
degree in electronic engineering from The University of Electro-Communications, Tokyo, Japan,
in 2011, and the M.S. and Ph.D. degrees in electrical engineering and information systems from The
University of Tokyo, Tokyo, in 2013 and 2016,
respectively.
He joined Analog Devices, Tokyo, Japan, in 2011,
Toshiba, Kanagawa, Japan, in 2013, and TSMC,
Hsinchu, Taiwan, in 2014, as an Intern. He was a
Project Researcher with The University of Tokyoin 2016. In 2016, he joined Qualcomm, San Diego, CA, USA, where heis involved in the circuit design of ultra-low-noise oscillators for smartphone
chipsets. His current research interests include the design of low-power andlow-noise oscillators, RF transceiver circuits, and wireless power transmission
circuits.
Dr. Iguchi was a recipient of the Outstanding Award in NE Analog
Innovation Award 2016 and the Best Paper Award at the 2013 IEEE WirelessPower Transfer Conference.

IGUCHI et al.: LOW-POWER CMOS CRYSTAL OSCILLATOR USING STACKED-AMPLIFIER ARCHITECTURE

Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in electrical engineeringfrom The University of Tokyo, Tokyo, Japan,
in 1981.
In 1981, he joined Toshiba Corporation, Kawasaki,
Japan, where he was involved in the design of
CMOS DRAM, SRAM, RISC processors, DSPs,
and system-on-chip Solutions. He was involved
extensively on interconnect delay and capacitancemodeling known as Sakurai model and alphapower-law MOS model. From 1988 to 1990,
he was a Visiting Researcher at the University of California, Berkeley,
CA, USA, where he conducted research in the field of very large scale
integration (VLSI) CAD. Since 1996, he has been a Professor with The
University of Tokyo, where he was involved in low-power high-speed
VLSI, memory design, interconnects, ubiquitous electronics, organic IC’s
and large-area electronics. He has authored or co-authored more than
600 technical publications including 100 invited presentations and several
books and holds more than 200 patents.
Dr. Sakurai is an IEICE Fellow. He served as an Executive Committee
Member of ISLPED and a Program Committee Member of ISSCC,
CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED, and other international
conferences. He was a recipient of the 2010 IEEE Donald O. Pederson Awardin Solid-State Circuits, the 2009 and 2010 IEEE Paul Rappaport Award,
the 2010 IEICE Electronics Society Award, the 2009 IEICE Achievement
Award, the 2005 IEEE ICICDT Award, the 2004 IEEE Takuo Sugano Award,
and the 2005 P&I Patent of the Year Award and four product awards. He was
the Executive Committee Chair of the VLSI Symposia and the Steering
Committee Chair of the IEEE A-SSCC. He served as the Conference
Chair of the Symposium on the VLSI Circuits and ICICDT, the Vice Chairof ASPDAC, and the TPC Chair of the A-SSCC and VLSI symposium.
He delivered keynote speech at more than 50 conferences including ISSCC,ESSCIRC, and ISLPED. He was an elected AdCom Member of the IEEE
Solid-State Circuits Society and the IEEE CAS and SSCS Distinguished
Lecturer. He is also a Domain Research Supervisor for nano-electronics areawith Japan Science and Technology Agency.

3017

Makoto Takamiya (S’98–M’00–SM’14) received
the B.S., M.S., and Ph.D. degrees in electronicengineering from The University of Tokyo, Tokyo,
Japan, in 1995, 1997, and 2000, respectively.
In 2000, he joined NEC Corporation, Sagamihara,
Japan, where he was involved in the circuit designof high-speed digital LSIs. In 2005, he joined The
University of Tokyo, where he is an Associate Professor with the VLSI Design and Education Center.
From 2013 to 2014, he was a Visiting Scholar at the
University of California, Berkeley, CA, USA. His
current research interests include the integrated power management circuits
for the ultralow power Internet of Things applications and the digital gate
driver circuits for IGBT.
Dr. Takamiya is a member of the technical program committee of the IEEE
International Solid-State Circuits Conference and the IEEE Symposium on
VLSI Circuits. He received the 2009 and 2010 IEEE Paul Rappaport Awards
and the Best Paper Award in 2013 IEEE Wireless Power Transfer Conference.