PCI Local Bus
Specification

Revision 2.2
December 18, 1998

Revision 2.2

REVISIONREVISION HISTORY

DATE

1.0

Original issue

6/22/92

2.0

Incorporated connector and expansion board specification

4/30/93

2.1

Incorporated clarifications and added 66 MHz chapter

6/1/95

2.2

Incorporated ECNs and improved readability

12/18/98

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Revision 2.2

Contents
Chapter 1 Introduction
1.1. Specification Contents............................................................................................................ 1
1.2. Motivation .............................................................................................................................. 1
1.3. PCI Local Bus Applications ................................................................................................... 2
1.4. PCI Local Bus Overview........................................................................................................ 3
1.5. PCI Local Bus Features and Benefits ..................................................................................... 4
1.6. Administration ........................................................................................................................ 6

Chapter 2 Signal Definition
2.1. Signal Type Definition ........................................................................................................... 8
2.2. Pin Functional Groups ............................................................................................................ 8
2.2.1. System Pins ..................................................................................................................... 8
2.2.2. Address and Data Pins..................................................................................................... 9
2.2.3. Interface Control Pins.................................................................................................... 10
2.2.4. Arbitration Pins (Bus Masters Only) ............................................................................. 11
2.2.5. Error Reporting Pins...................................................................................................... 122.2.6. Interrupt Pins (Optional) ............................................................................................... 13
2.2.7. Additional Signals ......................................................................................................... 15
2.2.8. 64-Bit Bus Extension Pins (Optional) ........................................................................... 17
2.2.9. JTAG/Boundary Scan Pins (Optional) .......................................................................... 18
2.3. Sideband Signals .................................................................................................................. 19
2.4. Central Resource Functions.................................................................................................. 19iii

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Chapter 3 Bus Operation
3.1. Bus Commands..................................................................................................................... 21
3.1.1. Command Definition ..................................................................................................... 21
3.1.2. Command Usage Rules ................................................................................................. 23
3.2. PCI Protocol Fundamentals .................................................................................................. 26
3.2.1. Basic Transfer Control .................................................................................................. 26
3.2.2. Addressing ..................................................................................................................... 27
3.2.2.1. I/O Space Decoding................................................................................................ 28
3.2.2.2. Memory Space Decoding ....................................................................................... 28
3.2.2.3. Configuration Space Decoding............................................................................... 30
3.2.3. Byte Lane and Byte Enable Usage ................................................................................ 38
3.2.4. Bus Driving and Turnaround......................................................................................... 39
3.2.5. Transaction Ordering and Posting ................................................................................. 40
3.2.5.1. Transaction Ordering and Posting for Simple Devices .......................................... 41
3.2.5.2. Transaction Ordering and Posting for Bridges ....................................................... 42
3.2.6. Combining, Merging, and Collapsing ........................................................................... 44
3.3. Bus Transactions .................................................................................................................. 46
3.3.1. Read Transaction ........................................................................................................... 47
3.3.2. Write Transaction .......................................................................................................... 48
3.3.3. Transaction Termination ............................................................................................... 49
3.3.3.1. Master Initiated Termination .................................................................................. 49
3.3.3.2. Target Initiated Termination .................................................................................. 52
3.3.3.3. Delayed Transactions ............................................................................................. 61
3.4. Arbitration ............................................................................................................................ 68
3.4.1. Arbitration Signaling Protocol ...................................................................................... 70
3.4.2. Fast Back-to-Back Transactions.................................................................................... 72
3.4.3. Arbitration Parking ........................................................................................................ 74
3.5. Latency ................................................................................................................................. 75
3.5.1. Target Latency............................................................................................................... 75
3.5.1.1. Target Initial Latency ............................................................................................. 75
3.5.1.2. Target Subsequent Latency .................................................................................... 77iv

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3.5.2. Master Data Latency...................................................................................................... 78
3.5.3. Memory Write Maximum Completion Time Limit ...................................................... 78
3.5.4. Arbitration Latency ....................................................................................................... 79
3.5.4.1. Bandwidth and Latency Considerations ................................................................. 80
3.5.4.2. Determining Arbitration Latency ........................................................................... 82
3.5.4.3. Determining Buffer Requirements ......................................................................... 87
3.6. Other Bus Operations ........................................................................................................... 88
3.6.1. Device Selection ............................................................................................................ 88
3.6.2. Special Cycle ................................................................................................................. 90
3.6.3. Address/Data Stepping .................................................................................................. 91
3.6.4. Interrupt Acknowledge .................................................................................................. 93
3.7. Error Functions ..................................................................................................................... 93
3.7.1. Parity Generation........................................................................................................... 94
3.7.2. Parity Checking ............................................................................................................. 95
3.7.3. Address Parity Errors .................................................................................................... 95
3.7.4. Error Reporting.............................................................................................................. 95
3.7.4.1. Data Parity Error Signaling on PERR# .................................................................. 96
3.7.4.2. Other Error Signaling on SERR# ........................................................................... 97
3.7.4.3. Master Data Parity Error Status Bit........................................................................ 98
3.7.4.4. Detected Parity Error Status Bit ............................................................................. 98
3.7.5. Delayed Transactions and Data Parity Errors ............................................................... 98
3.7.6. Error Recovery .............................................................................................................. 99
3.8. 64-Bit Bus Extension.......................................................................................................... 100
3.8.1. Determining Bus Width During System Initialization ................................................ 104
3.9. 64-bit Addressing ............................................................................................................... 105
3.10. Special Design Considerations ......................................................................................... 108v

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Chapter 4 Electrical Specification
4.1. Overview ............................................................................................................................ 113
4.1.1. 5V to 3.3V Transition Road Map ................................................................................ 113
4.1.2. Dynamic vs. Static Drive Specification ...................................................................... 115
4.2. Component Specification ................................................................................................... 115
4.2.1. 5V Signaling Environment .......................................................................................... 117
4.2.1.1. DC Specifications ................................................................................................. 117
4.2.1.2. AC Specifications ................................................................................................. 118
4.2.1.3. Maximum AC Ratings and Device Protection ..................................................... 120
4.2.2. 3.3V Signaling Environment ....................................................................................... 122
4.2.2.1. DC Specifications ................................................................................................. 122
4.2.2.2. AC Specifications ................................................................................................. 123
4.2.2.3. Maximum AC Ratings and Device Protection ..................................................... 125
4.2.3. Timing Specification ................................................................................................... 126
4.2.3.1. Clock Specification .............................................................................................. 126
4.2.3.2. Timing Parameters................................................................................................ 128
4.2.3.3. Measurement and Test Conditions ....................................................................... 129
4.2.4. Indeterminate Inputs and Metastability ....................................................................... 130
4.2.5. Vendor Provided Specification.................................................................................... 131
4.2.6. Pinout Recommendation ............................................................................................. 131
4.3. System (Motherboard) Specification.................................................................................. 132
4.3.1. Clock Skew.................................................................................................................. 132
4.3.2. Reset ............................................................................................................................ 133
4.3.3. Pull-ups........................................................................................................................ 136
4.3.4. Power ........................................................................................................................... 137
4.3.4.1. Power Requirements............................................................................................. 137
4.3.4.2. Sequencing............................................................................................................ 137
4.3.4.3. Decoupling............................................................................................................ 138
4.3.5. System Timing Budget ................................................................................................ 138
4.3.6. Physical Requirements ................................................................................................ 141
4.3.6.1. Routing and Layout Recommendations for Four-Layer Motherboards ............... 141
4.3.6.2. Motherboard Impedance....................................................................................... 141vi

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4.3.7. Connector Pin Assignments ........................................................................................ 142
4.4. Expansion Board Specification .......................................................................................... 146
4.4.1. Board Pin Assignment ................................................................................................. 146
4.4.2. Power Requirements.................................................................................................... 150
4.4.2.1. Decoupling............................................................................................................ 150
4.4.2.2. Power Consumption ............................................................................................. 150
4.4.3. Physical Requirements ................................................................................................ 151
4.4.3.1. Trace Length Limits ............................................................................................. 151
4.4.3.2. Routing Recommendations for Four-Layer Expansion Boards ........................... 152
4.4.3.3. Impedance............................................................................................................. 152
4.4.3.4. Signal Loading...................................................................................................... 152

Chapter 5 Mechanical Specification
5.1. Overview ............................................................................................................................ 153
5.2. Expansion Card Physical Dimensions and Tolerances ...................................................... 154
5.2.1. Connector Physical Description .................................................................................. 168
5.2.1.1. Connector Physical Requirements........................................................................ 176
5.2.1.2. Connector Performance Specification .................................................................. 177
5.2.2. Planar Implementation ................................................................................................ 178

Chapter 6 Configuration Space6.1. Configuration Space Organization ..................................................................................... 190
6.2. Configuration Space Functions .......................................................................................... 192
6.2.1. Device Identification ................................................................................................... 192
6.2.2. Device Control............................................................................................................. 193
6.2.3. Device Status ............................................................................................................... 196
6.2.4. Miscellaneous Registers .............................................................................................. 198
6.2.5. Base Addresses ............................................................................................................ 201
6.2.5.1. Address Maps ....................................................................................................... 201
6.2.5.2. Expansion ROM Base Address Register .............................................................. 204
6.3. PCI Expansion ROMs ........................................................................................................ 205
6.3.1. PCI Expansion ROM Contents.................................................................................... 206
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6.3.1.1. PCI Expansion ROM Header Format ................................................................... 206
6.3.1.2. PCI Data Structure Format ................................................................................... 207
6.3.2. Power-on Self Test (POST) Code ............................................................................... 209
6.3.3. PC-compatible Expansion ROMs................................................................................ 209
6.3.3.1. ROM Header Extensions ...................................................................................... 209
6.4. Vital Product Data ............................................................................................................... 212
6.5. Device Drivers.................................................................................................................... 212
6.6. System Reset ...................................................................................................................... 213
6.7. Capabilities List.................................................................................................................. 213
6.8. Message Signaled Interrupts .............................................................................................. 214
6.8.1. Message Capability Structure....................................................................................... 214
6.8.1.1. Capability ID ........................................................................................................ 215
6.8.1.2. Next Pointer .......................................................................................................... 215
6.8.1.3. Message Control ................................................................................................... 215
6.8.1.4. Message Address .................................................................................................. 217
6.8.1.5. Message Upper Address (Optional) ..................................................................... 217
6.8.1.6. Message Data........................................................................................................ 218
6.8.2. MSI Operation .............................................................................................................. 218
6.8.2.1. MSI Transaction Termination .............................................................................. 220
6.8.2.2. MSI Transaction Reception and Ordering Requirements .................................... 220

Chapter 7 66 Mhz PCI Specification
7.1. Introduction ........................................................................................................................ 221
7.2. Scope .................................................................................................................................. 221
7.3. Device Implementation Considerations ............................................................................. 222
7.3.1. Configuration Space .................................................................................................... 222
7.4. Agent Architecture ............................................................................................................. 222
7.5. Protocol............................................................................................................................... 222
7.5.1. 66MHZ_ENABLE (M66EN) Pin Definition .............................................................. 222
7.5.2. Latency ........................................................................................................................ 223

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7.6. Electrical Specification....................................................................................................... 223
7.6.1. Overview ..................................................................................................................... 223
7.6.2. Transition Roadmap to 66 MHz PCI........................................................................... 224
7.6.3. Signaling Environment ................................................................................................ 224
7.6.3.1. DC Specifications ................................................................................................. 225
7.6.3.2. AC Specifications ................................................................................................. 225
7.6.3.3. Maximum AC Ratings and Device Protection ..................................................... 226
7.6.4. Timing Specification ................................................................................................... 226
7.6.4.1. Clock Specification .............................................................................................. 226
7.6.4.2. Timing Parameters................................................................................................ 228
7.6.4.3. Measurement and Test Conditions ....................................................................... 229
7.6.5. Vendor Provided Specification ................................................................................... 231
7.6.6. Recommendations ....................................................................................................... 231
7.6.6.1. Pinout Recommendations ..................................................................................... 231
7.6.6.2. Clocking Recommendations................................................................................. 231
7.7. System (Planar) Specification ............................................................................................ 232
7.7.1. Clock Uncertainty........................................................................................................ 232
7.7.2. Reset ............................................................................................................................ 233
7.7.3. Pullups ......................................................................................................................... 233
7.7.4. Power ........................................................................................................................... 233
7.7.4.1. Power Requirements............................................................................................. 233
7.7.4.2. Sequencing............................................................................................................ 233
7.7.4.3. Decoupling............................................................................................................ 233
7.7.5. System Timing Budget ................................................................................................ 233
7.7.6. Physical Requirements ................................................................................................ 236
7.7.6.1. Routing and Layout Recommendations for Four-Layer Boards .......................... 236
7.7.6.2. Planar Impedance ................................................................................................. 236
7.7.7. Connector Pin Assignments ........................................................................................ 236
7.8. Expansion Board Specifications......................................................................................... 237

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Appendix A Special Cycle Messages .......................................239

Appendix B State Machines ......................................................241

Appendix C Operating Rules.....................................................251

Appendix D Class Codes...........................................................257

Appendix E System Transaction Ordering...............................267

Appendix F Exclusive Accesses...............................................279

Appendix G I/O Space Address Decoding forLegacy Devices ....................................................285

Appendix H Capability IDs..........................................................287

Appendix I Vital Product Data ...................................................289

Glossary .......................................................................................297x

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FiguresFigure 1-1: PCI Local Bus Applications .................................................................................... 2
Figure 1-2: PCI System Block Diagram..................................................................................... 3
Figure 2-1: PCI Pin List ............................................................................................................. 7
Figure 3-1: Address Phase Formats of Configuration Transactions ........................................ 31
Figure 3-2: Layout of CONFIG_ADDRESS Register ............................................................. 32
Figure 3-3: Host Bridge Translation for Type 0 Configuration Transactions
Address Phase....................................................................................................... 33
Figure 3-4: Configuration Read ............................................................................................... 38
Figure 3-5: Basic Read Operation ............................................................................................ 47
Figure 3-6: Basic Write Operation ........................................................................................... 48
Figure 3-7: Master Initiated Termination ................................................................................. 50
Figure 3-8: Master-Abort Termination .................................................................................... 51
Figure 3-9: Retry ...................................................................................................................... 55
Figure 3-10: Disconnect With Data.......................................................................................... 56
Figure 3-11: Master Completion Termination ......................................................................... 57
Figure 3-12: Disconnect-1 Without Data Termination ............................................................ 58
Figure 3-13: Disconnect-2 Without Data Termination ............................................................ 58
Figure 3-14: Target-Abort ........................................................................................................ 59
Figure 3-15: Basic Arbitration ................................................................................................. 70
Figure 3-16: Arbitration for Back-to-Back Access .................................................................. 74
Figure 3-17: DEVSEL# Assertion........................................................................................... 89
Figure 3-18: Address Stepping ................................................................................................. 92
Figure 3-19: Interrupt Acknowledge Cycle.............................................................................. 93
Figure 3-20: Parity Operation................................................................................................... 94
Figure 3-21: 64-bit Read Request With 64-bit Transfer ........................................................ 103
Figure 3-22: 64-bit Write Request With 32-bit Transfer ....................................................... 104
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Figure 3-23. 64-Bit Dual Address Read Cycle....................................................................... 107
Figure 4-1: PCI Board Connectors ......................................................................................... 114
Figure 4-2: V/I Curves for 5V Signaling................................................................................ 120
Figure 4-3: Maximum AC Waveforms for 5V Signaling ...................................................... 121
Figure 4-4: V/I Curves for 3.3V Signaling............................................................................. 124
Figure 4-5: Maximum AC Waveforms for 3.3V Signaling ................................................... 125
Figure 4-6: Clock Waveforms ................................................................................................ 126
Figure 4-7: Output Timing Measurement Conditions ............................................................ 129
Figure 4-8: Input Timing Measurement Conditions .............................................................. 129
Figure 4-9: Suggested Pinout for PQFP PCI Component ...................................................... 132
Figure 4-10: Clock Skew Diagram......................................................................................... 133
Figure 4-11: Reset Timing...................................................................................................... 135
Figure 4-12: Measurement of T prop, 5 Volt Signaling .......................................................... 140
Figure 5-1: PCI Raw Card (5V) ............................................................................................. 155
Figure 5-2: PCI Raw Card (3.3V and Universal) ................................................................... 155
Figure 5-3: PCI Raw Variable Height Short Card (5V, 32-bit) ............................................. 156
Figure 5-4: PCI Raw Variable Height Short Card (3.3V, 32-bit) .......................................... 156
Figure 5-5: PCI Raw Variable Height Short Card (5V, 64-bit) ............................................. 157
Figure 5-6: PCI Raw Variable Height Short Card (3.3V, 64-bit) .......................................... 158
Figure 5-7: PCI Card Edge Connector Bevel ......................................................................... 159
Figure 5-8: ISA Assembly (5V) ............................................................................................. 160
Figure 5-9: ISA Assembly (3.3V and Universal) ................................................................... 160
Figure 5-10: MC Assembly (5V) ........................................................................................... 161
Figure 5-11: MC Assembly (3.3V) ........................................................................................ 161
Figure 5-12: ISA Bracket ....................................................................................................... 162
Figure 5-13: ISA Retainer ...................................................................................................... 163
Figure 5-14: I/O Window Height ........................................................................................... 164

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Figure 5-15: Adapter Installation With Large I/O Connector ................................................ 165
Figure 5-16: MC Bracket Brace ............................................................................................. 166
Figure 5-17: MC Bracket........................................................................................................ 167
Figure 5-18: MC Bracket Details ........................................................................................... 168
Figure 5-19: 32-bit Connector ................................................................................................ 169
Figure 5-20: 5V/32-bit Connector Layout Recommendation ................................................ 169
Figure 5-21: 3.3V/32-bit Connector Layout Recommendation ............................................. 170
Figure 5-22: 5V/64-bit Connector .......................................................................................... 170
Figure 5-23: 5V/64-bit Connector Layout Recommendation ................................................ 170
Figure 5-24: 3.3V/64-bit Connector ....................................................................................... 171
Figure 5-25: 3.3V/64-bit Connector Layout Recommendation ............................................. 171
Figure 5-26: 5V/32-bit Card Edge Connector Dimensions and Tolerances .......................... 172
Figure 5-27: 5V/64-bit Card Edge Connector Dimensions and Tolerances .......................... 172
Figure 5-28: 3.3V/32-bit Card Edge Connector Dimensions and Tolerances ....................... 173
Figure 5-29: 3.3V/64-bit Card Edge Connector Dimensions and Tolerances ....................... 173
Figure 5-30: Universal 32-bit Card Edge Connector Dimensions and Tolerances ................ 174
Figure 5-31: Universal 64-bit Card Edge Connector Dimensions and Tolerances ................ 175
Figure 5-32: PCI Card Edge Connector Contacts .................................................................. 176
Figure 5-33: PCI Connector Location on Planar Relative to Datumon the ISA Connector ....................................................................................... 179
Figure 5-34: PCI Connector Location on Planar Relative to Datumon the EISA Connector..................................................................................... 179
Figure 5-35: PCI Connector Location on Planar Relative to Datumon the MC Connector ....................................................................................... 180
Figure 5-36: 32-bit PCI Riser Connector ............................................................................... 181
Figure 5-37: 32-bit/5V Riser Connector Footprint ................................................................ 182
Figure 5-38: 32-bit/3.3V Riser Connector Footprint ............................................................. 183
Figure 5-39: 64-bit/5V Riser Connector ............................................................................... 184
Figure 5-40: 64-bit/5V Riser Connector Footprint ................................................................ 185
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Figure 5-41: 64-bit/3.3V Riser Connector ............................................................................ 186
Figure 5-42: 64-bit/3.3V Riser Connector Footprint.............................................................. 187
Figure 6-1: Type 00h Configuration Space Header ............................................................... 191
Figure 6-2: Command Register Layout .................................................................................. 193
Figure 6-3: Status Register Layout......................................................................................... 196
Figure 6-4: BIST Register Layout .......................................................................................... 199
Figure 6-5: Base Address Register for Memory .................................................................... 202
Figure 6-6: Base Address Register for I/O ............................................................................. 202
Figure 6-7: Expansion ROM Base Address Register Layout................................................. 205
Figure 6-8: PCI Expansion ROM Structure ........................................................................... 206
Figure 6-9: Typical Image Layout.......................................................................................... 211
Figure 6-10: Example Capabilities List.................................................................................. 213
Figure 6-11: Message Signaled Interrupt Capability Structure .............................................. 214
Figure 7-1: 33 MHz PCI vs. 66 MHz PCI Timing ................................................................. 224
Figure 7-2: 3.3V Clock Waveform......................................................................................... 226
Figure 7-3: Output Timing Measurement Conditions ............................................................ 229
Figure 7-4: Input Timing Measurement Conditions .............................................................. 229
Figure 7-5: Tval(max) Rising Edge........................................................................................ 230
Figure 7-6: Tval(max) Falling Edge....................................................................................... 230
Figure 7-7: Tval (min) and Slew Rate.................................................................................... 231
Figure 7-8: Recommended Clock Routing............................................................................. 232
Figure 7-9: Clock Skew Diagram........................................................................................... 233
Figure 7-10: Measurement of T prop ...................................................................................... 235
Figure D-1: Programming Interface Byte Layout for IDE Controller Class Code ................ 258
Figure E-1: Example Producer - Consumer Model ................................................................ 269
Figure E-2: Example System with PCI-to-PCI Bridges ......................................................... 276
Figure F-1: Starting an Exclusive Access .............................................................................. 282

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Figure F-2: Continuing an Exclusive Access ......................................................................... 283
Figure F-3: Accessing a Locked Agent .................................................................................. 284
Figure I-1: VPD Capability Structure .................................................................................... 289
Figure I-2: Small Resource Data Type Tag Bit Definitions................................................... 290
Figure I-3: Large Resource Data Type Tag Bit Definitions................................................... 291
Figure I-4: Resource Data Type Flags for a Typical VPD ..................................................... 291
Figure I-5: VPD Format ......................................................................................................... 292

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PrefaceSpecification Supersedes Earlier Documents
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Incorporation of Engineering Change Requests (ECRs)
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Description

New Capabilities

Changes to configuration structure to define additional
capabilities of a PCI function

Sub ID

Subsystem vendor configuration space changed from optional torequired for most classes of devices

PME#

Describes wake-up function and assigns (previously reserved) pin
on PCI bus

MECH ECN# 1

Bracket mounting for EMI reduction

MECH ECN# 2

Increase size of I/O window to enable new connectors

MECH ECN# 3

I/O connector volume to enable add-in card insertion

MECH ECN# 4

Riser connector-add-in card interface

xvii

Revision 2.2

ECR

xviii

Description

MECH ECN# 5

Tighten critical tolerance to improve add-in card seating

MECH ECN# 6

Mechanical errata (wrong datum ref), components free areas

Posted Memory
WritesClarified requirements for posted memory writes to prevent
situations which may lead to a deadlock

Tprop

Clarifies measurement and determination of Tprop times for
33/66 MHz

RST# TIMING

New timing requirements between RST# and the first transaction
on the bus and the first access to a device

VPD (Revised)

Provides alternate access method to vital product data

3.3 V Aux

Specifies a standard source of power for power management
wake event logic

Max Retry Time

Devices cannot Retry a memory write request for longer than
10 µs

Msg Interrupt

Method by which an I/O controller can deliver message based
interrupt

Spread Spectrum
Clocking

Adds spread spectrum clocking (SSC) to the specification

Revision 2.2

Document Conventions
7KHIROORZLQJQDPHDQGXVDJHFRQYHQWLRQVDUHXVHGLQWKLVGRFXPHQW
asserted, deasserted

The terms asserted and deasserted refer to theglobally visible state of the signal on the clock edge,
not to signal transitions.

edge, clock edge

The terms edge and clock edge refer to the rising edgeof the clock. On the rising edge of the clock is the
only time signals have any significance on the PCIbus.

#

A # symbol at the end of a signal name indicates thatthe signal’s asserted state occurs when it is at a low
voltage. The absence of a # symbol indicates that thesignal is asserted at a high voltage.

reserved

The contents or undefined states or information are
not defined at this time. Using any reserved area in
the PCI specification is not permitted. All areas of
the PCI specification can only be changed according
to the by-laws of the PCI Special Interest Group. Any
use of the reserved areas of the PCI specification will
result in a product that is not PCI-compliant. The
functionality of any such product cannot be
guaranteed in this or any future revision of the PCI
specification.

signal names

Signal names are indicated with this bold font.

signal range

A signal name followed by a range enclosed inbrackets, for example AD[31::00], represents a rangeof logically related signals. The first number in therange indicates the most significant bit (msb) and thelast number indicates the least significant bit (lsb).

implementation notes

Implementation notes are enclosed in a box. They are
not part of the PCI specification and are included forclarification and illustration only.

xixRevision 2.2

xxRevision 2.2

Chapter 1
Introduction
1.1. Specification Contents
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1

Revision 2.2

1.3. PCI Local Bus Applications
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2

Revision 2.2

1.4. PCI Local Bus Overview
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3

Revision 2.2

1.5. PCI Local Bus Features and Benefits
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IROORZV•Transparent upgrade from 32-bit data path at 33 MHz(132 MB/s peak) to 64-bit data path at 33 MHz(264 MB/s peak) and from 32-bit data path at 66 MHz(264 MB/s peak) to 64-bit data path at 66 MHz(528 MB/s peak).

•

Variable length linear and cacheline wrap mode burstingfor both read and writes improves write dependentgraphics performance.

•

Low latency random accesses (60-ns write access latency
for 33 MHz PCI or 30-ns for 66 MHz PCI to slave
registers from master parked on bus).

•

Capable of full concurrency with processor/memory
subsystem.

•

Synchronous bus with operation up to 33 MHz or 66 MHz.

•

Hidden (overlapped) central arbitration.

•

Optimized for direct silicon (component) interconnection;i.e., no glue logic. Electrical/driver (i.e., total load) andfrequency specifications are met with standard ASIC
technologies and other typical processes.

•

Multiplexed architecture reduces pin count (47 signals fortarget; 49 for master) and package size of PCI components
or provides for additional functions to be built into aparticular package size.

•

Single PCI add-in card works in ISA-, EISA-, orMC-based systems (with minimal change to existing
chassis designs), reducing inventory cost and end user
confusion.

Ease of Use•

Enables full auto configuration support of PCI Local Bus
add-in boards and components. PCI devices containregisters with the device information required for
configuration.

Longevity•

Processor independent. Supports multiple families ofprocessors as well as future generations of processors (bybridges or by direct integration).

•

Support for 64-bit addressing.

•

Both 5-volt and 3.3-volt signaling environments are
specified. Voltage migration path enables smooth industry
transition from 5 volts to 3.3 volts.

High Performance

Low Cost

4

Revision 2.2•

Small form factor add-in boards.

•

Present signals allow power supplies to be optimized forthe expected system usage by monitoring add-in boards
that could surpass the maximum power budgeted by thesystem.

•Over 2000 hours of electrical SPICE simulation withhardware model validation.

•

Forward and backward compatibility of 32-bit and 64-bit
add-in boards and components.

•

Forward and backward compatibility with 33 MHz and
66 MHz add-in boards and components.

•

Increased reliability and interoperability of add-in cards bycomprehending the loading and frequency requirements of
the local bus at the component level, eliminating buffers
and glue logic.

•

MC-style expansion connectors.

•

Full multi-master capability allowing any PCI master peerto-peer access to any PCI master/target.

•

A shared slot accommodates either a standard ISA, EISA,or MC board or a PCI add-in board (refer to Chapter 5,"Mechanical Specification" for connector layout details).

Data Integrity•

Provides parity on both data and address and allows
implementation of robust client platforms.

SoftwareCompatibility•

PCI components can be fully compatible with existing
driver and applications software. Device drivers can be
portable across various classes of platforms.

Interoperability/
Reliability

Flexibility

5

Revision 2.2

1.6. Administration
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6

Revision 2.2

Chapter 2
Signal Definition
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Optional Pins

Required Pins
Address& DataInterfaceControl

AD[31::00]

AD[63::32]

C/BE[3::0]#

C/BE[7::4]#

PAR

PAR64

FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL

Error
Reporting

PERR#
SERR#

Arbitration

REQ#
GNT#

System

CLK
RST#(masters only)

PCI
COMPLIANT
DEVICE

64-BitExtension

REQ64#
ACK64#
LOCK#
INTA#
INTB#
INTC#
INTD#

TDI
TDO
TCK
TMS
TRST#

InterfaceControlInterrupts

JTAG(IEEE 1149.1))LJXUH3&,3LQ/LVW
1 The minimum number of pins for a planar-only device is 45 for a target-only and 47 for a master (PERR#

and SERR# are optional for planar-only applications). Systems must support all signals defined for theconnector. This includes individual REQ# and GNT# signals for each connector. The PRSNT[1::2]#
pins are not device signals and, therefore, are not included in Figure 2-1, but are required to be connected on
add-in cards.
7

Revision 2.2

2.1. Signal Type Definition
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inInput is a standard input-only signal.

out

Totem Pole Output is a standard active driver.

t/s

Tri-State is a bi-directional, tri-state input/output pin.

s/t/s

Sustained Tri-State is an active low tri-state signal owned and driven
by one and only one agent at a time. The agent that drives an s/t/s pin
low must drive it high for at least one clock before letting it float. A
new agent cannot start driving a s/t/s signal any sooner than one clock
after the previous owner tri-states it. A pullup is required to sustain
the inactive state until another agent drives it and must be provided by
the central resource.

o/dOpen Drain allows multiple devices to share as a wire-OR. A pull-up
is required to sustain the inactive state until another agent drives it andmust be provided by the central resource.

2.2. Pin Functional Groups
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2.2.1. System Pins
CLK

8

in

Clock provides timing for all transactions on PCI and is an
input to every PCI device. All other PCI signals, except
RST#, INTA#, INTB#, INTC#, and INTD#, are sampled on
the rising edge of CLK and all other timing parameters aredefined with respect to this edge. PCI operates up to 33 MHz(refer to Chapter 4) or 66 MHz (refer to Chapter 7) and, ingeneral, the minimum frequency is DC (0 Hz); however,component-specific permissions are described in Chapter 4(refer to Section 4.2.3.1.).

Revision 2.2

RST#

in

Reset is used to bring PCI-specific registers, sequencers, andsignals to a consistent state. What effect RST# has on a
device beyond the PCI sequencer is beyond the scope of thisspecification, except for reset states of required PCI
configuration registers. A device that can wake the system
while in a powered down bus state has additional
requirements related to RST#. Refer to the PCI PowerManagement Interface Specification for details. Anytime
RST# is asserted, all PCI output signals must be driven to
their benign state. In general, this means they must be
asynchronously tri-stated. REQ# and GNT# must both be tristated (they cannot be driven low or high during reset). To
prevent AD, C/BE#, and PAR signals from floating duringreset, the central resource may drive these lines during reset(bus parking) but only to a logic low level; they may not be
driven high. Refer to Section 3.8.1. for special requirements
for AD[63::32], C/BE[7::4]#, and PAR64 when they are
not connected (as in a 64-bit card installed in a 32-bit
connector).
RST# may be asynchronous to CLK when asserted ordeasserted. Although asynchronous, deassertion is guaranteed
to be a clean, bounce-free edge. Except for configuration
accesses, only devices that are required to boot the system
will respond after reset.

2.2.2. Address and Data Pins
AD[31::00]

t/s

Address and Data are multiplexed on the same PCI pins. A
bus transaction consists of an address 2 phase followed by one
or more data phases. PCI supports both read and write bursts.
The address phase is the first clock cycle in which FRAME#
is asserted. During the address phase, AD[31::00] contain aphysical address (32 bits). For I/O, this is a byte address; forconfiguration and memory, it is a DWORD address. During
data phases, AD[07::00] contain the least significant byte(lsb) and AD[31::24] contain the most significant byte (msb).
Write data is stable and valid when IRDY# is asserted; readdata is stable and valid when TRDY# is asserted. Data istransferred during those clocks where both IRDY# andTRDY# are asserted.

2 The DAC uses two address phases to transfer a 64-bit address.

9

Revision 2.2

C/BE[3::0]#t/s

Bus Command and Byte Enables are multiplexed on the same
PCI pins. During the address phase of a transaction,
C/BE[3::0]# define the bus command (refer to Section 3.1.
for bus command definitions). During the data phase,
C/BE[3::0]# are used as Byte Enables. The Byte Enables arevalid for the entire data phase and determine which byte lanes
carry meaningful data. C/BE[0]# applies to byte 0 (lsb) andC/BE[3]# applies to byte 3 (msb).

PAR

t/s

Parity is even3 parity across AD[31::00] and C/BE[3::0]#.
Parity generation is required by all PCI agents. PAR is stableand valid one clock after each address phase. For data phases,
PAR is stable and valid one clock after either IRDY# isasserted on a write transaction or TRDY# is asserted on a readtransaction. Once PAR is valid, it remains valid until one
clock after the completion of the current data phase. (PAR
has the same timing as AD[31::00], but it is delayed by one
clock.) The master drives PAR for address and write dataphases; the target drives PAR for read data phases.

2.2.3. Interface Control Pins
FRAME#

s/t/s

Cycle Frame is driven by the current master to indicate thebeginning and duration of an access. FRAME# is asserted toindicate a bus transaction is beginning. While FRAME# isasserted, data transfers continue. When FRAME# isdeasserted, the transaction is in the final data phase or has
completed.

IRDY#

s/t/s

Initiator Ready indicates the initiating agent’s (bus master’s)ability to complete the current data phase of the transaction.
IRDY# is used in conjunction with TRDY#. A data phase iscompleted on any clock both IRDY# and TRDY# areasserted. During a write, IRDY# indicates that valid data ispresent on AD[31::00]. During a read, it indicates the masteris prepared to accept data. Wait cycles are inserted until both
IRDY# and TRDY# are asserted together.

TRDY#

s/t/s

Target Ready indicates the target agent’s (selected device’s)
ability to complete the current data phase of the transaction.
TRDY# is used in conjunction with IRDY#. A data phase iscompleted on any clock both TRDY# and IRDY# areasserted. During a read, TRDY# indicates that valid data ispresent on AD[31::00]. During a write, it indicates the target
is prepared to accept data. Wait cycles are inserted until both
IRDY# and TRDY# are asserted together.

STOP#

s/t/s

Stop indicates the current target is requesting the master tostop the current transaction.

3 The number of "1"s on AD[31::00], C/BE[3::0]#, and PAR equals an even number.

10

Revision 2.2

LOCK#

s/t/s

Lock indicates an atomic operation to a bridge that may
require multiple transactions to complete. When LOCK# isasserted, non-exclusive transactions may proceed to a bridgethat is not currently locked. A grant to start a transaction on
PCI does not guarantee control of LOCK#. Control of
LOCK# is obtained under its own protocol in conjunction
with GNT#. It is possible for different agents to use PCI
while a single master retains ownership of LOCK#. Locked
transactions may be initiated only by host bridges, PCI-to-PCI
bridges, and expansion bus bridges. Refer to Appendix F for
details on the requirements of LOCK#.

IDSEL

in

Initialization Device Select is used as a chip select duringconfiguration read and write transactions.

DEVSEL#s/t/s

Device Select, when actively driven, indicates the driving
device has decoded its address as the target of the current
access. As an input, DEVSEL# indicates whether any device
on the bus has been selected.

2.2.4. Arbitration Pins (Bus Masters Only)
REQ#

t/s

Request indicates to the arbiter that this agent desires use of
the bus. This is a point-to-point signal. Every master has its
own REQ# which must be tri-stated while RST# is asserted.

GNT#

t/s

Grant indicates to the agent that access to the bus has been
granted. This is a point-to-point signal. Every master has its
own GNT# which must be ignored while RST# is asserted.

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LVGHDVVHUWHG$PDVWHUPXVWLJQRUHLWVGNT#ZKLOHRST#LVDVVHUWHGREQ#DQG
GNT#DUHWULVWDWHVLJQDOVGXHWRSRZHUVHTXHQFLQJUHTXLUHPHQWVLQWKHFDVHZKHUHWKH
EXVDUELWHULVSRZHUHGE\DGLIIHUHQWVXSSO\YROWDJHWKDQWKHEXVPDVWHUGHYLFH

4 REQ# is an input to the arbiter, and GNT# is an output.

11

Revision 2.2

2.2.5. Error Reporting Pins
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PERR#

s/t/s

Parity Error is only for the reporting of data parity errors
during all PCI transactions except a Special Cycle. The
PERR# pin is sustained tri-state and must be driven activeby the agent receiving data (when enabled) two clocks
following the data when a data parity error is detected. The
minimum duration of PERR# is one clock for each dataphase that a data parity error is detected. (If sequential dataphases each have a data parity error, the PERR# signal will
be asserted for more than a single clock.) PERR# must be
driven high for one clock before being tri-stated as with all
sustained tri-state signals. Refer to Section 3.7.4.1. for moredetails.

SERR#

o/d

System Error is for reporting address parity errors, data parity
errors on the Special Cycle command, or any other systemerror where the result will be catastrophic. If an agent does
not want a non-maskable interrupt (NMI) to be generated, adifferent reporting mechanism is required. SERR# is pureopen drain and is actively driven for a single PCI clock by theagent reporting the error. The assertion of SERR# issynchronous to the clock and meets the setup and hold timesof all bused signals. However, the restoring of SERR# to thedeasserted state is accomplished by a weak pullup (samevalue as used for s/t/s) which is provided by the central
resource not by the signaling agent. This pullup may take twoto three clock periods to fully restore SERR#. The agent thatreports SERR# to the operating system does so anytime
SERR# is asserted.

5 Some planar devices are granted exceptions (refer to Section 3.7.2. for details).

12

Revision 2.2

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INTA#

o/d

Interrupt A is used to request an interrupt.

INTB#

o/d

Interrupt B is used to request an interrupt and only has
meaning on a multi-function device.

INTC#

o/d

Interrupt C is used to request an interrupt and only has
meaning on a multi-function device.

INTD#

o/d

Interrupt D is used to request an interrupt and only has
meaning on a multi-function device.

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6 When several independent functions are integrated into a single device, it will be referred to as a multi-

function device. Each function on a multi-function device has its own configuration space.

13

Revision 2.2

Implementation Note: Interrupt Routing+RZLQWHUUXSWVDUHURXWHGRQWKHPRWKHUERDUGLVV\VWHPVSHFLILF+RZHYHUWKH
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IXQFWLRQDQGWKHUHIRUHFDQRQO\XVHINTA#RQWKHGHYLFHWKLVPHFKDQLVPGLVWULEXWHV
WKHLQWHUUXSWVHYHQO\DPRQJWKHLQWHUUXSWFRQWUROOHU VLQSXWSLQVINTA#RI'HYLFH1XPEHULVFRQQHFWHGWRIRQWRQWKHPRWKHUERDUG 'HYLFH
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FRQQHFWRU INTA#RI'HYLFH1XPEHULVFRQQHFWHGWRIRQXRQWKHPRWKHUERDUG
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14

Device Number
on Motherboard

Interrupt Pin on
DeviceInterrupt Pin on
Motherboard

0, 4, 8, 12,
16, 20, 24, 28

INTA#
INTB#
INTC#
INTD#

IRQW
IRQX
IRQY
IRQZ

1, 5, 9, 13,
17, 21, 25, 29

INTA#
INTB#
INTC#
INTD#

IRQX
IRQY
IRQZ
IRQW

2, 6, 10, 14,
18, 22, 26, 30

INTA#
INTB#
INTC#
INTD#

IRQY
IRQZ
IRQW
IRQX

3, 7, 11, 15,
19, 23, 27, 31

INTA#
INTB#
INTC#
INTD#

IRQZ
IRQW
IRQX
IRQY

Revision 2.2

2.2.7. Additional Signals
PRSNT[1:2]#

in

The Present signals are not signals for a device, but areprovided by an add-in board. The Present signals indicate to
the motherboard whether an add-in board is physicallypresent in the slot and, if one is present, the total power
requirements of the board. These signals are required for
add-in boards but are optional for motherboards. Refer to
Section 4.4.1. for more details.

Implementation Note: PRSNT# Pins
$WDPLQLPXPWKHDGGLQERDUGPXVWJURXQGRQHRIWKHWZRPRSNT[1:2]#SLQVWR
LQGLFDWHWRWKHPRWKHUERDUGWKDWDERDUGLVSK\VLFDOO\LQWKHFRQQHFWRU7KHVLJQDOOHYHORIPRSNT1#DQGPRSNT2#LQIRUPWKHPRWKHUERDUGRIWKHSRZHUUHTXLUHPHQWVRIWKH
DGGLQERDUG7KHDGGLQERDUGPD\VLPSO\WLHPRSNT1#DQGRUPRSNT2#WRJURXQG
WRVLJQDOWKHDSSURSULDWHSRZHUUHTXLUHPHQWVRIWKHERDUG 5HIHUWR6HFWLRQIRU
GHWDLOV 7KHPRWKHUERDUGSURYLGHVSXOOXSVRQWKHVHVLJQDOVWRLQGLFDWHZKHQQRERDUG
LVFXUUHQWO\SUHVHQWCLKRUN#in, o/d,s/t/s

Clock running is an optional signal used as an input for adevice to determine the status of CLK and an open drain
output used by the device to request starting or speeding up
CLK.
CLKRUN# is a sustained tri-state signal used by thecentral resource to request permission to stop or slow CLK.
The central resource is responsible for maintaining
CLKRUN# in the asserted state when CLK is running anddeasserts CLKRUN# to request permission to stop or slow
CLK. The central resource must provide the pullup for
CLKRUN#.

Implementation Note: CLKRUN#CLKRUN#LVDQRSWLRQDOVLJQDOXVHGLQWKH3&,PRELOHHQYLURQPHQWDQGQRWGHILQHGIRU
WKHFRQQHFWRU'HWDLOVRIWKHCLKRUN#SURWRFRODQGRWKHUPRELOHGHVLJQFRQVLGHUDWLRQVDUHGLVFXVVHGLQWKH3&,0RELOH'HVLJQ*XLGH

15

Revision 2.2

M66EN

in

The 66MHZ_ENABLE pin indicates to a device whether thebus segment is operating at 66 or 33 MHz. Refer to
Section 7.5.1. for details of this signal’s operation.

PME#

o/d

The Power Management Event signal is an optional signalthat can be used by a device to request a change in thedevice or system power state. The assertion anddeassertion of PME# is asynchronous to CLK. This signal
has additional electrical requirements over and above
standard open drain signals that allow it to be shared
between devices which are powered off and those which
are powered on. In general, this signal is bused between all
PCI connectors in a system, although certain
implementations may choose to pass separate bufferedcopies of the signal to the system logic.
Devices must be enabled by software before asserting thissignal. Once asserted, the device must continue to drive
the signal low until software explicitly clears the conditionin the device.
The use of this pin is specified in the PCI Bus PowerManagement Interface Specification. The system vendor
must provide a pull-up on this signal, if it allows the signal
to be used. System vendors that do not use this signal are
not required to bus it between connectors or provide pullups on those pins.

3.3VauxinAn optional 3.3 volt auxiliary power source delivers power
to the PCI add-in card for generation of power management
events when the main power to the card has been turned off
by software.
The use of this pin is specified in the PCI Bus PowerManagement Interface Specification.
A system or add-in card that does not support PCI bus
power management must treat the 3.3Vaux pin as reserved.

Implementation Note: PME# and 3.3Vaux
PME# DQG3.3VauxDUHRSWLRQDOVLJQDOVGHILQHGE\WKH3&,%XV3RZHU0DQDJHPHQW,QWHUIDFH6SHFLILFDWLRQ'HWDLOVRIWKHVHVLJQDOVFDQEHIRXQGLQWKDWGRFXPHQW

16

Revision 2.2

2.2.8. 64-Bit Bus Extension Pins (Optional)
7KHELWH[WHQVLRQSLQVDUHFROOHFWLYHO\RSWLRQDO7KDWLVLIWKHELWH[WHQVLRQLV
XVHGDOOWKHSLQVLQWKLVVHFWLRQDUHUHTXLUHG
AD[63::32]

t/s

Address and Data are multiplexed on the same pins andprovide 32 additional bits. During an address phase (whenusing the DAC command and when REQ64# is asserted), theupper 32-bits of a 64-bit address are transferred; otherwise,
these bits are reserved7 but are stable and indeterminate.
During a data phase, an additional 32-bits of data aretransferred when a 64-bit transaction has been negotiated by
the assertion of REQ64# and ACK64#.

C/BE[7::4]#t/s

Bus Command and Byte Enables are multiplexed on the samepins. During an address phase (when using the DAC
command and when REQ64# is asserted), the actual bus
command is transferred on C/BE[7::4]#; otherwise, these bits
are reserved and indeterminate. During a data phase,
C/BE[7::4]# are Byte Enables indicating which byte lanes
carry meaningful data when a 64-bit transaction has been
negotiated by the assertion of REQ64# and ACK64#.
C/BE[4]# applies to byte 4 and C/BE[7]# applies to byte 7.

REQ64#

s/t/s

Request 64-bit Transfer, when asserted by the current bus
master, indicates it desires to transfer data using 64 bits.
REQ64# also has the same timing as FRAME#. REQ64#
also has meaning at the end of reset as described in Section
3.8.1.

ACK64#

s/t/s

Acknowledge 64-bit Transfer, when actively driven by thedevice that has positively decoded its address as the target ofthe current access, indicates the target is willing to transfer
data using 64 bits. ACK64# has the same timing as
DEVSEL#.

PAR64

t/s

Parity Upper DWORD is the even8 parity bit that protects
AD[63::32] and C/BE[7::4]#. PAR64 must be valid one
clock after each address phase on any transaction in which
REQ64# is asserted.
PAR64 is stable and valid for 64-bit data phases one clock
after either IRDY# is asserted on a write transaction or
TRDY# is asserted on a read transaction. (PAR64 has thesame timing as AD[63::32] but delayed by one clock.) The
master drives PAR64 for address and write data phases; thetarget drives PAR64 for read data phases.

7 Reserved means reserved for future use by the PCI SIG Steering Committee. Reserved bits must not be
used by any device.
8 The number of “1”s on AD[63::32], C/BE[7::4]#, and PAR64 equals an even number.

17

Revision 2.2

2.2.9. JTAG/Boundary Scan Pins (Optional)
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in

Test Data Input is used to serially shift test data and test
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TDO

out

Test Output is used to serially shift test data and test
instructions out of the device during TAP operation.

TMS

in

Test Mode Select is used to control the state of the TAP
controller in the device.

TRST#

in

Test Reset provides an asynchronous initialization of the TAP
controller. This signal is optional in IEEE Standard 1149.1.

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18

Revision 2.2

2.3. Sideband Signals
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19

Revision 2.2

20

Revision 2.2

Chapter 3
Bus Operation
3.1. Bus Commands%XVFRPPDQGVLQGLFDWHWRWKHWDUJHWWKHW\SHRIWUDQVDFWLRQWKHPDVWHULVUHTXHVWLQJ%XV
FRPPDQGVDUHHQFRGHGRQWKHC/BE[3::0]#OLQHVGXULQJWKHDGGUHVVSKDVH

3.1.1. Command Definition
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C/BE[3::0]#

Command Type

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate

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21

Revision 2.2

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22

Revision 2.2

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DVZHOO$EULGJHWKDWSUHIHWFKHVLVUHVSRQVLEOHIRUDQ\ODWHQWGDWDQRWFRQVXPHGE\WKH
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23

Revision 2.2•

7KHUHDUHQRVLGHHIIHFWVRIDUHDGRSHUDWLRQ7KHUHDGRSHUDWLRQFDQQRWEH
GHVWUXFWLYHWRHLWKHUWKHGDWDRUDQ\RWKHUVWDWHLQIRUPDWLRQ)RUH[DPSOHD),)2
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24

Revision 2.2,WLVKLJKO\UHFRPPHQGHGWKDWWKH&DFKHOLQH6L]HUHJLVWHUEHLPSOHPHQWHGWRHQVXUHFRUUHFWXVHRIWKHUHDGFRPPDQGV7KH&DFKHOLQH6L]HUHJLVWHUPXVWEHLPSOHPHQWHG
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Implementation Note: Stale-Data Problems Caused By Not
Discarding Prefetch Data
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25

Revision 2.2

3.2. PCI Protocol Fundamentals
7KHEDVLFEXVWUDQVIHUPHFKDQLVPRQ3&,LVDEXUVW$EXUVWLVFRPSRVHGRIDQDGGUHVVSKDVHDQGRQHRUPRUHGDWDSKDVHV3&,VXSSRUWVEXUVWVLQERWK0HPRU\DQG,2$GGUHVV6SDFHV$OOVLJQDOVDUHVDPSOHGRQWKHULVLQJHGJHRIWKHFORFN (DFKVLJQDOKDVDVHWXSDQG
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V\QFKURQRXV






3.2.1. Basic Transfer Control
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FRAME#

is driven by the master to indicate the beginning and end of atransaction.

IRDY#

is driven by the master to indicate that it is ready to transfer data.

TRDY#

is driven by the target to indicate that it is ready to transfer data.

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ILUVWFORFNHGJHRQZKLFKFRAME#LVDVVHUWHGLVWKHDGGUHVVSKDVHDQGWKHDGGUHVVDQG
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TRDY#LVGHDVVHUWHG


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WUDQVIHUUHGZKHQIRDY#DQGTRDY#DUHERWKDVVHUWHGRQWKHVDPHULVLQJFORFNHGJH
9 The only exceptions are 567,17$,17%,17& and ,17'which are discussed in

Sections 2.2.1. and 2.2.6.
10 3$5 and 3$5 are treated like an $' line delayed by one clock.
11 The notion of qualifying $' and ,'6(/ signals is fully defined in Section 3.6.3.
12 Note: The address phase consists of two clocks when the command is the Dual Address Cycle (DAC).

26

Revision 2.2

2QFHDPDVWHUKDVDVVHUWHGIRDY#LWFDQQRWFKDQJHIRDY#RUFRAME#XQWLOWKH
FXUUHQWGDWDSKDVHFRPSOHWHVUHJDUGOHVVRIWKHVWDWHRITRDY#2QFHDWDUJHWKDV
DVVHUWHGTRDY#RUSTOP#LWFDQQRWFKDQJHDEVSEL#TRDY#RUSTOP#XQWLOWKH
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EHLPPHGLDWHO\DIWHUWKHDGGUHVVSKDVH FRAME#LVGHDVVHUWHGDQGIRDY#LVDVVHUWHG
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FRAME#DQGIRDY#GHDVVHUWHG

3.2.2. Addressing
3&,GHILQHVWKUHHSK\VLFDODGGUHVVVSDFHV7KH0HPRU\DQG,2$GGUHVV6SDFHVDUH
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3&,WDUJHWV H[FHSWKRVWEXVEULGJHV DUHUHTXLUHGWRLPSOHPHQW%DVH$GGUHVVUHJLVWHU V
WRUHTXHVWDUDQJHRIDGGUHVVHVZKLFKFDQEHXVHGWRSURYLGHDFFHVVWRLQWHUQDOUHJLVWHUVRUIXQFWLRQV UHIHUWR&KDSWHUIRUPRUHGHWDLOV 7KHFRQILJXUDWLRQVRIWZDUHXVHVWKH%DVH$GGUHVVUHJLVWHUWRGHWHUPLQHKRZPXFKVSDFHDGHYLFHUHTXLUHVLQDJLYHQDGGUHVVVSDFHDQGWKHQDVVLJQV LISRVVLEOH ZKHUHLQWKDWVSDFHWKHGHYLFHZLOOUHVLGH

Implementation Note: Device Address Space,WLVKLJKO\UHFRPPHQGHGWKDWDGHYLFHUHTXHVW YLD%DVH$GGUHVVUHJLVWHU V WKDWLWV
LQWHUQDOUHJLVWHUVEHPDSSHGLQWR0HPRU\6SDFHDQGQRW,26SDFH$OWKRXJKWKHXVHRI,26SDFHLVDOORZHG,26SDFHLVOLPLWHGDQGKLJKO\IUDJPHQWHGLQ3&V\VWHPVDQGZLOO
EHFRPHPRUHGLIILFXOWWRDOORFDWHLQWKHIXWXUH5HTXHVWLQJ0HPRU\6SDFHLQVWHDGRI,2
6SDFHDOORZVDGHYLFHWREHXVHGLQDV\VWHPWKDWGRHVQRWVXSSRUW,26SDFH$GHYLFHPD\PDSLWVLQWHUQDOUHJLVWHULQWRERWK0HPRU\6SDFHDQGRSWLRQDOO\,26SDFHE\XVLQJ
WZR%DVH$GGUHVVUHJLVWHUVRQHIRU,2DQGWKHRWKHUIRU0HPRU\7KHV\VWHP
FRQILJXUDWLRQVRIWZDUHZLOODOORFDWH LISRVVLEOH VSDFHWRHDFK%DVH$GGUHVVUHJLVWHU
:KHQWKHDJHQW¶VGHYLFHGULYHULVFDOOHGLWGHWHUPLQHVZKLFKDGGUHVVVSDFHLVWREHXVHG
WRDFFHVVWKHGHYLFH,IWKHSUHIHUUHGDFFHVVPHFKDQLVPLV,26SDFHDQGWKH,2%DVH$GGUHVVUHJLVWHUZDVLQLWLDOL]HGWKHQWKHGULYHUZRXOGDFFHVVWKHGHYLFHXVLQJ,2EXV
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27

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29

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14 In versions 2.0 and 2.1 of this specification, two mechanisms were defined. However, only one

mechanism (Configuration Mechanism #1) was allowed for new designs and the other (Configuration
Mechanism #2) was included for reference.
32

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

 
Reserved

CONFIG_ADDRESSPCI AD BUS

 

 
Bus
Number   

DeviceNumberFunction
Number  Register
NumberOnly One "1"


00

00

 



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15 If the Device Number field selects an IDSEL line that the bridge does not implement, the bridge mustcomplete the processor access normally, dropping the data on writes and returning all ones on reads. The
bridge may optionally implement this requirement by performing a Type 0 configuration access with no
IDSEL asserted. This will terminate with Master-Abort which drops write data and returns all ones onreads.

33

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34

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35

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ELWV7KHUHIRUHWKHIDSELSLQPXVWEHVXSSRUWHGE\DOOWDUJHWV'HYLFHVPXVWQRWPDNH
DQLQWHUQDOFRQQHFWLRQEHWZHHQDQADOLQHDQGDQLQWHUQDOIDSELVLJQDOLQRUGHUWRVDYH
DSLQ7KHRQO\H[FHSWLRQLVWKHKRVWEULGJHVLQFHLWGHILQHVKRZIDSELVDUHPDSSHGIDSELJHQHUDWLRQEHKLQGD3&,WR3&,EULGJHLVVSHFLILHGLQWKH3&,WR3&,%ULGJH$UFKLWHFWXUH6SHFLILFDWLRQ
7KHELQGLQJEHWZHHQDGHYLFHQXPEHULQWKH&21),*B$''5(66UHJLVWHURI3&$7
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PXVWVFDQDOOGHYLFHQXPEHUVWRHQVXUHDOOFRPSRQHQWVDUHORFDWHG1RWH7KH
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VLQJOHXQLTXHIDSELOLQHLVDVVHUWHGIRUHDFKGHYLFHQXPEHU&RQILJXUDWLRQWUDQVDFWLRQVWKDWDUHQRWFODLPHGE\DGHYLFHDUHWHUPLQDWHGZLWK0DVWHU$ERUW7KHPDVWHUWKDW
LQLWLDWHGWKLVWUDQVDFWLRQVHWVWKHUHFHLYHG0DVWHU$ERUWELWLQWKH6WDWXVUHJLVWHU

36

Revision 2.2

Implementation Note: System Generation of IDSEL+RZDV\VWHPJHQHUDWHVIDSELLVV\VWHPVSHFLILFKRZHYHULIQRRWKHUPDSSLQJLV
UHTXLUHGWKHIROORZLQJH[DPSOHPD\EHXVHG7KHIDSELVLJQDODVVRFLDWHGZLWK'HYLFH
1XPEHULVFRQQHFWHGWRAD[16]IDSELRI'HYLFH1XPEHULVFRQQHFWHGWRAD[17]
DQGVRIRUWKXQWLOIDSELRI'HYLFH1XPEHULVFRQQHFWHGWRAD[31])RU'HYLFH
1XPEHUVWKHKRVWEULGJHVKRXOGH[HFXWHWKHWUDQVDFWLRQEXWQRWDVVHUWDQ\RIWKH
AD[31::16]OLQHVEXWDOORZWKHDFFHVVWREHWHUPLQDWHGZLWK0DVWHU$ERUW7ZHQW\RQHGLIIHUHQWGHYLFHVFDQEHXQLTXHO\VHOHFWHGIRUFRQILJXUDWLRQDFFHVVHVE\
FRQQHFWLQJDGLIIHUHQWDGGUHVVOLQHWRHDFKGHYLFHDQGDVVHUWLQJRQHRIWKHAD[31::11]
OLQHVDWDWLPH7KHLVVXHZLWKFRQQHFWLQJRQHRIWKHXSSHUADOLQHVWRIDSELLVDQ
DGGLWLRQDOORDGRQWKHADOLQH7KLVFDQEHPLWLJDWHGE\UHVLVWLYHO\FRXSOLQJIDSELWR
WKHDSSURSULDWHADOLQH7KLVGRHVKRZHYHUFUHDWHDYHU\VORZVOHZUDWHRQIDSELFDXVLQJLWWREHLQDQLQYDOLGORJLFVWDWHPRVWRIWKHWLPHDVVKRZQLQ)LJXUHZLWKWKH
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FRAME# WKXVJXDUDQWHHLQJIDSELWREHVWDEOHZKHQLWQHHGVWREHVDPSOHG3UH
GULYLQJWKHDGGUHVVEXVLVHTXLYDOHQWWRDGGUHVVVWHSSLQJDVGLVFXVVHGLQ6HFWLRQ
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VXIILFLHQWO\ORQJWRDOORZIDSELWREHFRPHVWDEOHEHIRUHLQLWLDWLQJWKHFRQILJXUDWLRQWUDQVDFWLRQ)RUDOORWKHUF\FOHVIDSELLVXQGHILQHGDQGPD\EHDWDQRQGHWHUPLQLVWLFOHYHOGXULQJWKHDGGUHVVSKDVH

16 The number of clocks the address bus should be pre-driven is determined from the RC time constant on

IDSEL.

37

Revision 2.2

CLK
1

2

3

4

5

6

FRAME#AD

ADDRESS

DATA

IDSEL

C/BE#

CFG-RD

BE#'s

IRDY#

TRDY#
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3.2.3. Byte Lane and Byte Enable Usage
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38

Revision 2.2

EHIRUHFRPSOHWLQJWKHWUDQVIHURWKHUZLVHLWPXVWUHWXUQDOOE\WHV1RWH%\WHHQDEOHV
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GHVWUR\HGRUVWDWXVFKDQJHVEHFDXVHRIWKHDFFHVV 

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17 For a 32-bit data transfer, this means 4 bytes per data phase; for a 64-bit data transfer, this means 8 bytes

per data phase.

39

Revision 2.2

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3.2.5. Transaction Ordering and Posting
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Revision 2.2

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50

Revision 2.2

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51

Revision 2.2

3.3.3.2. Target Initiated Termination
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refers to termination requested before any data is transferred because
the target is busy and temporarily unable to process the transaction.
This condition may occur, for example, because the device cannot
meet the initial latency requirement, is currently locked by anothermaster, or there is a conflict for a internal resource.
Retry is a special case of Disconnect without data being transferred on
the initial data phase.
The target signals Retry by asserting STOP# and not asserting
TRDY# on the initial data phase of the transaction (STOP# cannot be
asserted during the turn-around cycle between the address phase andfirst data phase of a read transaction). When the target uses Retry, nodata is transferred.

Disconnectrefers to termination requested with or after data was transferred on
the initial data phase because the target is unable to respond within thetarget subsequent latency requirement and, therefore, is temporarily
unable to continue bursting. This might be because the burst crosses a
resource boundary or a resource conflict occurs. Data may or may nottransfer on the data phase where Disconnect is signaled. Notice that
Disconnect differs from Retry in that Retry is always on the initial
data phase, and no data transfers. If data is transferred with or before
the target terminates the transaction, it is a Disconnect. This may also
occur on the initial data phase because the target is not capable ofdoing a burst.
Disconnect with data may be signaled on any data phase by asserting
TRDY# and STOP# together. This termination is used when thetarget is only willing to complete the current data phase and no more.
Disconnect without data may be signaled on any subsequent dataphase (meaning data was transferred on the previous data phase) by
deasserting TRDY# and asserting STOP#.

52

Revision 2.2

Target-Abortrefers to an abnormal termination requested because the target
detected a fatal error or the target will never be able to complete therequest. Although it may cause a fatal error for the application
originally requesting the transaction, the transaction completes
gracefully, thus, preserving normal operation for other agents. For
example, a master requests all bytes in an I/O Address Space
DWORD to be read, but the target design restricts access to a single
byte in this range. Since the target cannot complete the request, thetarget terminates the request with Target-Abort.
Once the target has claimed an access by asserting DEVSEL#, it cansignal Target-Abort on any subsequent clock. The target signals
Target-Abort by deasserting DEVSEL# and asserting STOP# at thesame time.

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53

Revision 2.2

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54

Revision 2.2

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68

Revision 2.2

Implementation Note: System Arbitration Algorithm
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69

Revision 2.2

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19 Higher priority here does not imply a fixed priority arbitration, but refers to the agent that would win

arbitration at a given instant in time.
70

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71

Revision 2.2

3.4.2. Fast Back-to-Back Transactions
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meets the following two requirements:
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20 It is recommended that this be done by returning the target state machine (refer to Appendix B) from the

B_BUSY state to the IDLE state as soon as FRAME# is deasserted and the device’s decode time has beenmet (a miss occurs) or when DEVSEL# is asserted by another target and not waiting for a bus Idle state(IRDY# deasserted).
72

Revision 2.2

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Implementation Note: Using More Than One Option to Meet Initial
Latency$FRPELQDWLRQRIWKHGLIIHUHQWRSWLRQVPD\EHXVHGEDVHGRQWKHDFFHVVODWHQF\RID
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3.5.1.2. Target Subsequent Latency
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77

Revision 2.2

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78

Revision 2.2

Implementation Note: Meeting Maximum Completion Time Limit by
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3.5.4.1. Bandwidth and Latency Considerations
In PCI systems, there is a tradeoff between the desire to achieve low latency and thedesire to achieve high bandwidth (throughput). High throughput is achieved by allowing
devices to use long burst transfers. Low latency is achieved by reducing the maximum
burst transfer length. The following discussion is provided (for a 32-bit bus) to illustrate
this tradeoff.
A given PCI bus master introduces latency on PCI each time it uses the PCI bus to do atransaction. This latency is a function of the behavior of both the master and the target
device during the transaction as well as the state of the master’s GNT# signal. The bus
command used, transaction burst length, master data latency for each data phase, and theLatency Timer are the primary parameters which control the master’s behavior. The bus
command used, target latency, and target subsequent latency are the primary parameterswhich control the target’s behavior.

80Revision 2.2

A master is required to assert its IRDY# within eight clocks for any given data phase(initial and subsequent). For the first data phase, a target is required to assert its TRDY#or STOP# within 16 clocks from the assertion of FRAME# (unless the access hits amodified cacheline in which case 32 clocks are allowed for host bus bridges). For all
subsequent data phases in a burst transfer, the target must assert its TRDY# or STOP#
within eight clocks. If the effects of the Latency Timer are ignored, it is astraightforward exercise to develop equations for the worst case latencies that a PCI bus
master can introduce from these specification requirements.
latency_max (clocks) = 32 + 8 * (n-1)

if a modified cacheline is hit(for a host bus bridge only)or= 16 + 8 * (n-1)

if not a modified cacheline

where n is the total number of data transfers in the transaction
However, it is more useful to consider transactions that exhibit typical behavior. PCI is
designed so that data transfers between a bus master and a target occur as register toregister transfers. Therefore, bus masters typically do not insert wait states since they
only request transactions when they are prepared to transfer data. Targets typically havean initial access latency less than the 16 (32 for modified cacheline hit for host bus
bridge) clock maximum allowed. Once targets begin transferring data (complete theirfirst data phase), they are typically able to sustain burst transfers at full rate (one clock
per data phase) until the transaction is either completed by the master or the target’s
buffers are filled or are temporarily empty. The target can use the target Disconnect
protocol to terminate the burst transaction early when its buffers fill or temporarily
empty during the transaction. Using these more realistic considerations, the worst caselatency equations can be modified to give a typical latency (assuming that the target’s
initial data phase latency is eight clocks) again ignoring the effects of the Latency Timer.
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Data
Phases

Bytes
Transferred

Total
Clocks

Latency Timer(clocks)

Bandwidth(MB/s)

Latency
(ms)

8

32

16

14

60

.48

16

64

24

22

80

.72

32

128

40

38

96

1.20

64

256

72

70

107

2.16

Data Phases

Number of data phases completed during transaction

Bytes Transferred

Total number of bytes transferred during transaction (assuming
32-bit transfers)

Total Clocks

Total number of clocks used to complete the transfer
total_clocks

Latency Timer= 8 + (n-1) + 1 (Idle time on bus)

Latency Timer value in clocks such that the Latency Timer
expires in next to last data phaselatency_timer = total_clocks - 2

Bandwidth

Calculated bandwidth in MB/s
bandwidth = bytes_transferred / (total clocks * 30 ns)

Latency

Latency in microseconds introduced by transaction
latency = total clocks * 30 ns

Table 3-4 clearly shows that as the burst length increases, the amount of data transferredincreases. Note: The amount of data doubles between each row in the table, while thelatency increases by less than double. The amount of data transferred between the firstrow and the last row increases by a factor of 8, while the latency increases by a factor of
4.5. The longer the transaction (more data phases), the more efficiently the bus is being
used. However, this increase in efficiency comes at the expense of larger buffers.

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Table 3-5 lists the requirements of each device in the target system and how manytransactions each device must complete to sustain its bandwidth requirements within
10 µs time slices.
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The last column indicates how many different transactions that are required to movethe data. This assumes that the entire transfer cannot be completed as a single
transaction.
7DEOH([DPSOH6\VWHP
DeviceBandwidth(MB/s)

Bytes/10 ms

Time Used(ms)

Number ofTransactions
per Slice

Notes

Graphics

50

500

6.15

10

1

LAN

4

40

0.54

1

2

Disk

5

50

0.63

1

3

ISA bridge

4

40

0.78

2

4

PCI-to PCI
bridge

9

90

1.17

2

5

Total

72

720

9.27

16

Notes:

86

1.

Graphics is a combination of host bus bridge and frame grabber writing data to the frame buffer.
The host moves 300 bytes using five transactions with 15 data phases each, assuming eightclocks of target initial latency. The frame grabber moves 200 bytes using five transactions with10 data phases each, assuming eight clocks of target initial latency.

2.

The LAN uses a single transaction with 10 data phases with eight clocks of target initial latency.

3.

The disk uses a single transaction with 13 data phases with eight clocks of target initial latency.

4.

The ISA bridge uses two transactions with five data phases each with eight clocks of target initiallatency.

5.

The PCI-to-PCI bridge uses two transactions. One transaction is similar to the LAN and thesecond is similar to the disk requirements.

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CLK
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89

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95

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97

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24 Configuration Write or I/O Write, but never Memory Write and Invalidate or Memory Write.

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DVVHUWLQJACK64# ZKLFKPLUURUVDEVSEL# 'DWDSKDVHVDUHVWUHWFKHGE\ERWK
DJHQWVGHDVVHUWLQJWKHLUUHDG\OLQHVELWVLJQDOVUHTXLUHWKHVDPHWXUQDURXQGF\FOHVDV
WKHLUELWFRXQWHUSDUWV102

Revision 2.2

CLK
1

2

3

4

5

6

7

8

9

FRAME#
REQ64#ADDRESS

AD[63::32]

BUS CMD

DATA-3DATA-5DATA-2DATA-4DATA-6

BE#'s

C/BE[7::4]#

DATA TRANSFER

TRDY#

WAIT

WAIT

IRDY#

DATA TRANSFER

BE#'s

WAIT

C/BE[3::0]#

DATA-1DATA TRANSFER

AD[31::00]

DEVSEL#ACK64#ADDRESS
PHASE

DATA
PHASE

DATA
PHASE

DATA
PHASE

)LJXUHELW5HDG5HTXHVW:LWKELW7UDQVIHU)LJXUHLOOXVWUDWHVDPDVWHUUHTXHVWLQJDELWWUDQVIHU7KHELWWDUJHWLVQRW
FRQQHFWHGWRREQ64#RUACK64#DQGACK64#LVNHSWLQWKHGHDVVHUWHGVWDWHZLWKD
SXOOXS$VIDUDVWKHWDUJHWLVFRQFHUQHGWKLVLVDELWWUDQVIHU7KHPDVWHUFRQYHUWVWKHWUDQVDFWLRQIURPWRELWV6LQFHWKHPDVWHULVFRQYHUWLQJELWGDWDWUDQVIHUV
LQWRELWGDWDWUDQVIHUVWKHUHPD\RUPD\QRWEHDQ\E\WHHQDEOHVDVVHUWHGGXULQJDQ\
GDWDSKDVHRIWKHWUDQVDFWLRQ7KHUHIRUHDOOELWWDUJHWVPXVWEHDEOHWRKDQGOHGDWD
SKDVHVZLWKQRE\WHHQDEOHVDVVHUWHG7KHWDUJHWVKRXOGQRWXVH'LVFRQQHFWRU5HWU\
EHFDXVHDGDWDSKDVHLVHQFRXQWHUHGWKDWKDVQRDVVHUWHGE\WHHQDEOHVEXWVKRXOGDVVHUW
TRDY#DQGFRPSOHWHWKHGDWDSKDVH+RZHYHUWKHWDUJHWLVDOORZHGWRXVH5HWU\RU'LVFRQQHFWEHFDXVHLWLVLQWHUQDOO\EXV\DQGXQDEOHWRFRPSOHWHWKHGDWDWUDQVIHULQGHSHQGHQWRIZKLFKE\WHHQDEOHVDUHDVVHUWHG7KHPDVWHUUHVHQGVWKHGDWDWKDW
RULJLQDOO\DSSHDUHGRQAD[63::32]GXULQJWKHILUVWGDWDSKDVHRQAD[31::00]GXULQJWKH
VHFRQGGDWDSKDVH7KHVXEVHTXHQWGDWDSKDVHVDSSHDUH[DFWO\OLNHWKHELWWUDQVIHU
,IWKHELWVLJQDOVDUHUHPRYHG)LJXUHDQG)LJXUHDUHLGHQWLFDO

103

Revision 2.2

CLK
1

2

3

4

ADDRESS

DATA-1DATA-2

5

6

7

8

9

FRAME#

REQ64#BUS CMD

BE#'s-1

BE#'s-2

BE#'s-3

DATA
PHASE

WAIT

DATA
PHASE

DATA TRANSFER

TRDY#

WAIT

IRDY#

WAIT

BE#'s-2

C/BE[7::4]#

DATA TRANSFER

C/BE[3::0]#

DATA-3DATA-2

AD[63::32]

DATA TRANSFER

AD[31::00]

DEVSEL#ACK64#ADDRESS
PHASE

DATA
PHASE

)LJXUHELW:ULWH5HTXHVW:LWKELW7UDQVIHU

8VLQJDVLQJOHGDWDSKDVHZLWKELWWUDQVIHUVPD\QRWEHYHU\HIIHFWLYH6LQFHWKH
PDVWHUGRHVQRWNQRZKRZWKHWUDQVDFWLRQZLOOEHUHVROYHGZLWKACK64#XQWLODEVSEL#LVUHWXUQHGLWGRHVQRWNQRZWKHFORFNRQZKLFKWRGHDVVHUWFRAME# IRUDELWVLQJOHGDWDSKDVHWUDQVDFWLRQIRDY#PXVWUHPDLQGHDVVHUWHGXQWLOFRAME#
VLJQDOLQJLVUHVROYHG7KHVLQJOHELWGDWDSKDVHPD\KDYHWREHVSOLWLQWRWZRELW
GDWDSKDVHVZKHQWKHWDUJHWLVRQO\ELWVZKLFKPHDQVDWZRSKDVHELWWUDQVIHULVDW
OHDVWDVIDVWDVDRQHSKDVHELWWUDQVIHU

3.8.1. Determining Bus Width During System Initialization
REQ64#LVXVHGGXULQJUHVHWWRGLVWLQJXLVKEHWZHHQSDUWVWKDWDUHFRQQHFWHGWRDELW
GDWDSDWKDQGWKRVHWKDWDUHQRW3&,H[SDQVLRQVORWVWKDWVXSSRUWRQO\DELWGDWDSDWK
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SLQVDUHORFDWHGLQWKHELWSRUWLRQRIWKHFRQQHFWRU (DFKELWRQO\FRQQHFWRUPXVW
KDYHDQLQGLYLGXDOSXOOXSUHVLVWRUIRUREQ64#RQWKHPRWKHUERDUGACK64#LVEXVHG
WRDOOELWGHYLFHVDQGVORWVRQWKHPRWKHUERDUGDQGSXOOHGXSZLWKDVLQJOHUHVLVWRU
ORFDWHGRQWKHPRWKHUERDUGACK64#IRUHDFKELWVORWVPXVWEHGHDVVHUWHGHLWKHUE\
FRQQHFWLQJLWWRWKHACK64#VLJQDOFRQQHFWLQJWKHELWGHYLFHVDQGVORWVRUE\
LQGLYLGXDOSXOOXSUHVLVWRUVRQWKHPRWKHUERDUG

104

Revision 2.2

REQ64#LVEXVHGWRDOOGHYLFHVRQWKHPRWKHUERDUG LQFOXGLQJ3&,FRQQHFWRUVORWV WKDW
VXSSRUWDELWGDWDSDWK7KLVVLJQDOKDVDVLQJOHSXOOXSUHVLVWRURQWKHPRWKHUERDUG
7KHFHQWUDOUHVRXUFHPXVWGULYHREQ64#ORZ DVVHUWHG GXULQJWKHWLPHWKDWRST#LV
DVVHUWHGDFFRUGLQJWRWKHWLPLQJVSHFLILFDWLRQLQ6HFWLRQ'HYLFHVWKDWVHH
REQ64#DVVHUWHGRQWKHULVLQJHGJHRIRST#DUHFRQQHFWHGWRWKHELWGDWDSDWKDQG
WKRVHWKDWGRQRWVHHREQ64#DVVHUWHGDUHQRWFRQQHFWHG7KLVLQIRUPDWLRQPD\EHXVHG
E\WKHFRPSRQHQWWRVWDELOL]HIORDWLQJLQSXWVGXULQJUXQWLPHDVGHVFULEHGEHORZ
REQ64#KDVVHWXSDQGKROGWLPHUHTXLUHPHQWVUHODWLYHWRWKHGHDVVHUWLQJ KLJKJRLQJ
HGJHRIRST#:KLOHRST#LVDVVHUWHGREQ64#LVDV\QFKURQRXVZLWKUHVSHFWWR
CLK
:KHQDELWGDWDSDWKLVSURYLGHGAD[63::32]C/BE[7::4]#DQGPAR64UHTXLUH
HLWKHUSXOOXSUHVLVWRUVRULQSXWNHHSHUVEHFDXVHWKH\DUHQRWXVHGLQWUDQVDFWLRQVZLWKELWGHYLFHVDQGPD\WKHUHIRUHIORDWWRWKHWKUHVKROGOHYHOFDXVLQJRVFLOODWLRQRUKLJKSRZHUGUDLQWKURXJKWKHLQSXWEXIIHU7KLVSXOOXSRUNHHSHUIXQFWLRQPXVWEHSDUWRIWKH
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SOXJJHGLQWRDELW3&,VORW WKDW3&,GHYLFHPXVWLQVXUHWKDWLWVLQSXWVGRQRW
RVFLOODWHDQGWKDWWKHUHLVQRWDVLJQLILFDQWSRZHUGUDLQWKURXJKWKHLQSXWEXIIHUERWKEHIRUHDQGDIWHUWKHULVLQJHGJHRIRST#7KLVFDQEHGRQHLQDYDULHW\RIZD\VHJELDVLQJWKHLQSXWEXIIHURUDFWLYHO\GULYLQJWKHRXWSXWVFRQWLQXRXVO\ VLQFHWKH\DUHQRW
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SDWKAD[63::32]C/BE[7::4]#DQGPAR64XQOHVVWKHGHYLFHLQSXWEXIIHUVFDQQRWWROHUDWHWKHLULQSXWVIORDWLQJIRUDQLQGHILQLWHO\ORQJRST#SHULRG,IWKHGHYLFHLQSXW
EXIIHUVFDQQRWWROHUDWHWKLVWKHFRPSRQHQWPXVWFRQWUROLWVLQSXWVZKLOHRST#LV
DVVHUWHG,QWKLVFDVHWKHGHYLFHLVSHUPLWWHGWRHQDEOHLWVRXWSXWVFRQWLQXRXVO\ZKLOH
RST#LVDVVHUWHGDQGREQ64#LVGHDVVHUWHG LQGLFDWLQJDELWEXV EXWPXVWGULYH
WKHPWRDORJLFORZOHYHO LQFDVHWKHEXVFRQQHFWLRQLVDFWXDOO\ELWVZLGHDQG
REQ64#KDVQRW\HWVHWWOHGWRLWVILQDOYDOXH $IWHUWKHGHYLFHGHWHFWVWKDWREQ64#LV
GHDVVHUWHGDWWKHULVLQJHGJHRIRST#WKHGHYLFHPXVWFRQWLQXHWRFRQWUROWKHH[WHQGHG
EXVWRSURWHFWWKHGHYLFHLQSXWEXIIHUV

3.9. 64-bit Addressing
3&,VXSSRUWVPHPRU\DGGUHVVLQJEH\RQGWKHORZ*%E\GHILQLQJDPHFKDQLVPWRWUDQVIHUDELWDGGUHVVIURPWKHPDVWHURIWKHWUDQVDFWLRQWRWKHWDUJHW1RDGGLWLRQDO
SLQVDUHUHTXLUHGIRUDRUELWGHYLFHWRVXSSRUWELWDGGUHVVLQJ'HYLFHVWKDW
VXSSRUWRQO\ELWDGGUHVVHVDUHPDSSHGLQWRWKHORZ*%RIWKHDGGUHVVVSDFHDQG
ZRUNWUDQVSDUHQWO\ZLWKGHYLFHVWKDWJHQHUDWHELWDGGUHVVHV2QO\PHPRU\WUDQVDFWLRQVVXSSRUWELWDGGUHVVLQJ
7KHZLGWKRIWKHDGGUHVVLVLQGHSHQGHQWRIWKHZLGWKRIWKHEXVRQHLWKHUWKHPDVWHURU
WKHWDUJHW,IERWKWKHPDVWHUDQGWDUJHWVXSSRUWDELWEXVWKHHQWLUHELWDGGUHVVFRXOGWKHRUHWLFDOO\EHSURYLGHGLQDVLQJOHFORFN+RZHYHUWKHPDVWHULVUHTXLUHGLQDOO
FDVHVWRXVHWZRFORFNVWRFRPPXQLFDWHDELWDGGUHVVVLQFHWKHZLGWKRIWKHWDUJHW¶V
EXVLVQRWNQRZQGXULQJWKHDGGUHVVSKDVH
7KHVWDQGDUG3&,EXVWUDQVDFWLRQVXSSRUWVDELWDGGUHVV6LQJOH$GGUHVV&\FOH 6$& 
ZKHUHWKHDGGUHVVLVYDOLGIRUDVLQJOHFORFNZKHQFRAME#LVILUVWVDPSOHGDVVHUWHG
105

Revision 2.2

7RVXSSRUWWKHWUDQVIHURIDELWDGGUHVVD'XDO$GGUHVV&\FOH '$& EXVFRPPDQGLV
XVHGDFFRPSDQLHGZLWKRQHRIWKHGHILQHGEXVFRPPDQGVWRLQGLFDWHWKHGHVLUHGGDWD
SKDVHDFWLYLW\IRUWKHWUDQVDFWLRQ7KH'$&XVHVWZRFORFNVWRWUDQVIHUWKHHQWLUHELW
DGGUHVVRQWKHAD[31::00]VLJQDOV0DVWHUVWKDWXVHDGGUHVVVWHSSLQJFDQQRWLPSOHPHQW
ELWDGGUHVVLQJVLQFHWKHUHLVQRPHFKDQLVPIRUGHOD\LQJRUH[WHQGLQJWKHVHFRQG
DGGUHVVSKDVH:KHQDELWPDVWHUXVHV'$& ELWDGGUHVVLQJ LWPXVWSURYLGHWKH
XSSHUELWVRIWKHDGGUHVVRQAD[63::32]DQGWKHDVVRFLDWHGFRPPDQGIRUWKH
WUDQVDFWLRQRQC/BE[7::4]#GXULQJERWKDGGUHVVSKDVHVRIWKHWUDQVDFWLRQWRDOORZELW
WDUJHWVDGGLWLRQDOWLPHWRGHFRGHWKHWUDQVDFWLRQ)LJXUHLOOXVWUDWHVD'$&IRUDUHDGWUDQVDFWLRQ,QDEDVLF6$&UHDGWUDQVDFWLRQD
WXUQDURXQGF\FOHIROORZVWKHDGGUHVVSKDVH,QWKH'$&UHDGWUDQVDFWLRQDQDGGLWLRQDO
DGGUHVVSKDVHLVLQVHUWHGEHWZHHQWKHVWDQGDUGDGGUHVVSKDVHDQGWKHWXUQDURXQGF\FOH
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WUDQVDFWLRQ$'$&LVGHFRGHGE\DSRWHQWLDOWDUJHWZKHQDLVSUHVHQWRQC/BE[3::0]#GXULQJ
WKHILUVWDGGUHVVSKDVH,IDELWWDUJHWVXSSRUWVELWDGGUHVVLQJLWVWRUHVWKHDGGUHVVWKDWZDVWUDQVIHUUHGRQAD[31::00]DQGSUHSDUHVWRODWFKWKHUHVWRIWKHDGGUHVVRQWKH
QH[WFORFN7KHDFWXDOFRPPDQGXVHGIRUWKHWUDQVDFWLRQLVWUDQVIHUUHGGXULQJWKHVHFRQG
DGGUHVVSKDVHRQC/BE[3::0]#$ELWWDUJHWLVSHUPLWWHGWRODWFKWKHHQWLUHDGGUHVVRQ
WKHILUVWDGGUHVVSKDVH2QFHWKHHQWLUHDGGUHVVLVWUDQVIHUUHGDQGWKHFRPPDQGLVODWFKHGWKHWDUJHWGHWHUPLQHVLIDEVSEL#LVWREHDVVHUWHG7KHWDUJHWFDQGRIDVWPHGLXPRUVORZGHFRGHRQHFORFNGHOD\HGIURP6$&GHFRGLQJ$VXEWUDFWLYHGHFRGH
DJHQWDGMXVWVWRWKHGHOD\HGGHYLFHVHOHFWLRQWLPLQJHLWKHUE\LJQRULQJWKHHQWLUHWUDQVDFWLRQRUE\GHOD\LQJLWVRZQDVVHUWLRQRIDEVSEL#,IWKHEULGJHGRHVVXSSRUWELWDGGUHVVLQJLWZLOOGHOD\DVVHUWLQJLWVDEVSEL# LILWGRHVVXSSRUWELW
DGGUHVVLQJ 7KHPDVWHU RID'$& ZLOODOVRGHOD\WHUPLQDWLQJWKHWUDQVDFWLRQZLWK
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7KHH[HFXWLRQRIDQH[FOXVLYHDFFHVVLVWKHVDPHIRUHLWKHU'$&RU6$&,QHLWKHUFDVH
LOCK#LVGHDVVHUWHGGXULQJWKHDGGUHVVSKDVH ILUVWFORFN DQGDVVHUWHGGXULQJWKH
VHFRQGFORFN ZKLFKLVWKHILUVWGDWDSKDVHIRU6$&DQGWKHVHFRQGDGGUHVVSKDVHIRUD'$& $JHQWVPRQLWRULQJWKHWUDQVDFWLRQXQGHUVWDQGWKHORFNUHVRXUFHLVEXV\DQGWKH
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6$&DQG'$&WKHORJLFWKDWKDQGOHVLOCK#LVWKHVDPH

106

Revision 2.2

CLK
1

2

3

4

5

6

7

8

FRAME#

AD[31::00]

LO - ADDR HI - ADDR

C/BE[3::0]#

DUAL AD

AD[63::32]

DATA-1

BUS CMD

DATA-3(2)BE#[3::0]

HI ADDR

DATA-2DATA-4

Optional

WAIT

IRDY#

TRDY#

DEVSEL#F
ADDRESS
PHASE

M
DATA
PHASE

DATA TRANSFER

BE#[7::4]

WAIT

BUS CMDDATA TRANSFER

C/BE[7::4]#

S
DATA
PHASE

)LJXUH%LW'XDO$GGUHVV5HDG&\FOH

7KHPDVWHUFRPPXQLFDWHVDELWDGGUHVVDVVKRZQLQ)LJXUHUHJDUGOHVVRIZKHWKHUWKHWDUJHWVXSSRUWVDELWRUELWEXV7KHVKDGHGDUHDLQ)LJXUHLVXVHG
RQO\ZKHQWKHPDVWHURIWKHDFFHVVVXSSRUWVDELWEXV7KHPDVWHUGULYHVWKHHQWLUH
DGGUHVV ORZHUDGGUHVVRQAD[31::00]DQGXSSHUDGGUHVVRQAD[63::32] DQGERWK
FRPPDQGV '$&RQC/BE[3::0]#DQGWKHDFWXDOEXVFRPPDQGRQ
C/BE[7::4]# DOOGXULQJWKHLQLWLDODGGUHVVSKDVH2QWKHVHFRQGDGGUHVVSKDVHWKH
PDVWHUGULYHVWKHXSSHUDGGUHVVRQAD[31::00] DQGAD[63::32] ZKLOHWKHEXV
FRPPDQGLVGULYHQRQC/BE[3::0]# DQGC/BE[7::4]# 7KHPDVWHUFDQQRWGHWHUPLQHLI
WKHWDUJHWVXSSRUWVDELWGDWDSDWKXQWLOWKHHQWLUHDGGUHVVKDVEHHQWUDQVIHUUHGDQG
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Revision 2.2

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Logic internal to a device must never use the signal received from the bus while thatdevice is driving the bus. If internal logic requires the state of a bus signal while thedevice is driving the bus, that logic must use the internal signal (the one going to the
output buffer of the device) rather than the signal received from the device input
buffer. For example, if logic internal to a device continuously monitors the state of
FRAME# on the bus, that logic must use the signal from the device input bufferwhen the device is not the current bus master, and it must use the internallygenerated FRAME# when the device is the current bus master.

112

Revision 2.2

Chapter 4
Electrical Specification
4.1. Overview
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4.1.1. 5V to 3.3V Transition Road Map
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113

Revision 2.2"5 volt" Board
I/O buffers powered on
5 volt rail

"3.3 volt" Board
I/O buffers powered on
3.3 volt rail

Dual Voltage Signaling Board
I/O buffers powered onconnector dependent rail

"5 volt" Connector"3.3 volt" Connector)LJXUH3&,%RDUG&RQQHFWRUV

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27 While the primary goal of the PCI 5V to 3.3V transition strategy is to spare vendors the burden and

expense of implementing 3.3V parts that are "5V tolerant," such parts are not excluded. If a PCI componentof this type is used on the Universal board, its I/O buffers may optionally be connected to the 3.3V rail
rather than the "I/O" designated power pins; but high clamp diodes must still be connected to the "I/O"
designated power pins. (Refer to the last paragraph of Section 4.2.1.2. - "Clamping directly to the 3.3V railwith a simple diode must never be used in the 5V signaling environment.") Since the effective operation ofthese high clamp diodes may be critical to both signal quality and device reliability, the designer must
provide enough extra "I/O" designated power pins on a component to handle the current spikes associatedwith the 5V maximum AC waveforms (Section 4.2.1.3.).
114

Revision 2.2

4.1.2. Dynamic vs. Static Drive Specification
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4.2. Component Specification
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28 It may be desirable to perform some production tests at bare silicon pads. Such tests may have different

parameters than those specified here and must be correlated back to this specification.
115

Revision 2.2

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116

Revision 2.2

4.2.1. 5V Signaling Environment
4.2.1.1. DC Specifications
7DEOHVXPPDUL]HVWKH'&VSHFLILFDWLRQVIRU9VLJQDOLQJ
7DEOH'&6SHFLILFDWLRQVIRU96LJQDOLQJ
SymbolParameter

Vcc

Condition

Min

Max

Units

Supply Voltage

4.75

5.25

V

Vih

Input High Voltage

2.0

Vcc+0.5

V

Vil

Input Low Voltage

-0.5

0.8

V

Iih

Input High Leakage
Current

Vin = 2.7

70

µA

1

Iil

Input Low Leakage
Current

Vin = 0.5

-70

µA

1

Voh

Output High Voltage

Iout = -2 mA

Vol

Output Low Voltage

Iout = 3 mA, 6 mA

Cin

Input Pin CapacitanceCclk

CLK Pin Capacitance

CIDSEL

2.4

Notes

V
0.55

V

2

10

pF

3

12

pF

IDSEL Pin Capacitance

8

pF

4

Lpin

Pin Inductance

20

nH

5

IOff

PME# input leakage

1

µA

6

5

Vo ≤ 5.25 V
Vcc off or floating–

NOTES:
1.

Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.

2.

Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have
6 mA; the latter include, FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, INTA#,INTB#, INTC#, INTD#, and, when used, AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#.

3.

Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted tomotherboard-only devices up to 16 pF, in order to accommodate PGA packaging. This means, in general,that components for expansion boards need to use alternatives to ceramic PGA packaging (i.e., PQFP,
SGA, etc.).

4.

Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].

5.

This is a recommendation, not an absolute requirement. The actual value should be provided with thecomponent data sheet.

6.

This input leakage is the maximum allowable leakage into the PME# open drain driver when power isremoved from Vcc of the component. This assumes that no event has occurred to cause the device toattempt to assert PME#.

5HIHUWR6HFWLRQIRUVSHFLDOUHTXLUHPHQWVIRUAD[63::32]C/BE[7::4]#DQG
PAR64ZKHQWKH\DUHQRWFRQQHFWHG DVLQDELWH[SDQVLRQERDUGLQVWDOOHGLQDELW
FRQQHFWRU 
117

Revision 2.2

4.2.1.2. AC Specifications
7DEOHVXPPDUL]HVWKH$&VSHFLILFDWLRQVIRU9VLJQDOLQJ
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SymbolParameter

ConditionMin

Ioh(AC)

Switching0<Vout<1.4

Current High

1.4<Vout<2.4

Iol(AC)

Max

Units

Notes

-44

mA

1

-44+(Vout-1.4)/0.024

mA

1, 2

3.1<Vout<Vcc

Eqt’n A

(Test Point)

Vout = 3.1-142

Switching

Vout > 2.2

Current Low

2.2>Vout>0.55

1, 3
mA

3

95

mA

1

Vout/0.023mA

10.71>Vout>0

Eqt’n B1, 3

(Test Point)

Vout = 0.71

206

Icl

Low Clamp
Current-5 < Vin ≤ -1

-25+(Vin+1)/0.015

slewr

Output Rise Slew
Rate

0.4V to 2.4V load

1

5

V / ns4

slewf

Output Fall Slew
Rate

2.4V to 0.4V load

1

5

V / ns

4

mA

3

mA

NOTES:

118

1.

Refer to the V/I curves in Figure 4-2. Switching current characteristics for REQ# and GNT# are permitted
to be one half of that specified here; i.e., half size output drivers may be used on these signals. This
specification does not apply to CLK and RST# which are system outputs. "Switching Current High"
specifications are not relevant to SERR#, PME#, INTA#, INTB#, INTC#, and INTD# which are open drain
outputs.

2.

Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC
drive point rather than toward the voltage rail (as is done in the pull-down curve). This difference isintended to allow for an optional N-channel pull-up.

3.

Maximum current requirements must be met as drivers pull beyond the first step voltage. Equations
defining these maximums (A and B) are provided with the respective diagrams in Figure 4-3. The
equation-defined maximums should be met by design. In order to facilitate component testing, amaximum current test point is defined for each side of the output driver.

Revision 2.2
4.

This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the
instantaneous rate at any point within the transition range. The specified load (diagram below) is optional;i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI
Local Bus Specification . However, adherence to both maximum and minimum parameters is required (themaximum is not simply a guideline). Since adherence to the maximum slew rate was not required prior torevision 2.1 of the specification, there may be components in the market for some time that have fasteredge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than thisspecification could occur and should ensure that signal integrity modeling accounts for this. Rise slew
rate does not apply to open drain outputs.

pin

1/2 in. max.

outputbuffer

Vcc
1K Ω

10 pF

1K Ω

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119

Revision 2.2

Pull Up

Pull Down

Vcc

test
point

AC drive
point

Voltage

Voltage

Vcc

2.4
2.2
DC
drive point

1.4

DC drive
point

0.55

AC drivepoint-2

Current (mA)

-44

-176

Equation A:

test
point

3, 6

95

Current (mA)

380

Equation B:,RK  9RXW

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120

Revision 2.2

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Overvoltage Waveform
Voltage Source Impedance
R = 55 Ω

11 nSec(min)+ 11 v
11 v, p-to-p(minimum)5v. supply
4 nSec
(max)

R

V

Input
Buffer
Evaluation
Setup

0v

62.5 nSec(16 MHz)+ 5.25 v
10.75 v, p-to-p(minimum)

Undervoltage Waveform
Voltage Source Impedance
R = 25 Ω- 5.5 v

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29 Waveforms based on worst case (strongest) driver, maximum and minimum system configurations, withno internal clamp diodes.
30 It is possible to use alternative clamps, such as a diode stack to the 3.3V rail or a circuit to ground, if it

can be insured that the I/O pin will never be clamped below the 5V level.
121

Revision 2.2

4.2.2. 3.3V Signaling Environment
4.2.2.1. DC Specifications
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SymbolParameter

Vcc

Condition

Min

Max

Units

Supply Voltage

3.0

3.6

V

Vih

Input High Voltage

0.5VccVcc + 0.5

V

Vil

Input Low Voltage-0.5

0.3VccV

Vipu

Input Pull-up Voltage

0.7Vcc

Iil

Input Leakage Current

0 < Vin < Vcc

Voh

Output High Voltage

Iout = -500 µA

Vol

Output Low Voltage

Iout = 1500 µA

Cin

Input Pin CapacitanceCclk

CLK Pin Capacitance

CIDSEL+10
0.9Vcc

Notes

V

1

µA

2

V
0.1Vcc

V

10

pF

12

pF

IDSEL Pin Capacitance

8

pF

4

Lpin

Pin Inductance

20

nH

5

IOff

PME# input leakage

1

µA

6

5

Vo ≤ 3.6 V
Vcc off or
floating–

3

NOTES:
1.

This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors
are calculated to pull a floated network. Applications sensitive to static power utilization must assure thatthe input buffer is conducting minimum current at this input voltage.

2.

Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.

3.

Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK) with an exception granted tomotherboard-only devices up to 16 pF in order to accommodate PGA packaging. This would mean ingeneral that components for expansion boards need to use alternatives to ceramic PGA packaging; i.e.,
PQFP, SGA, etc.

4.

Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].

5.

This is a recommendation, not an absolute requirement. The actual value should be provided with thecomponent data sheet.

6.

This input leakage is the maximum allowable leakage into the PME# open drain driver when power isremoved from Vccof the component. This assumes that no event has occurred to cause the device toattempt to assert PME#.

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122

Revision 2.2

4.2.2.2. AC Specifications
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Symbol Parameter
Ioh(AC)

Iol(AC)

Condition

Min

Switching0<Vout<0.3Vcc

Current High

0.3Vcc<Vout<0.9Vcc

Max

Units

Notes

-12VccmA

1-17.1(Vcc-Vout)mA

1

0.7Vcc<Vout<Vcc

Eqt’n C

(Test Point)

Vout = 0.7Vcc-32VccSwitching

Vcc>Vout>0.6Vcc

Current Low

0.6Vcc>Vout>0.1Vcc

1, 2
mA

2

16Vcc

mA

1

26.7VoutmA

1

0.18Vcc>Vout>0

Eqt’n D

1, 2

(Test Point)

Vout = 0.18Vcc

38Vcc

Icl

Low Clamp
Current-3<Vin ≤ -1

-25+(Vin+1)/0.015

mA

Ich

High Clamp
Current

Vcc+4>Vin ≥ Vcc+1

25+(Vin-Vcc-1)/0.015

mA

slewr

Output Rise Slew
Rate

0.2Vcc - 0.6Vcc load

1

4

V/ns

3

slewf

Output Fall Slew
Rate

0.6Vcc - 0.2Vccl load

1

4

V/ns

3

mA

2

NOTES:
1.

Refer to the V/I curves in Figure 4-4. Switching current characteristics for REQ# and GNT# are permitted
to be one half of that specified here; i.e., half size output drivers may be used on these signals. This
specification does not apply to CLK and RST# which are system outputs. "Switching Current High"
specifications are not relevant to SERR#, PME#, INTA#, INTB#, INTC#, and INTD# which are open drain
outputs.

2.

Maximum current requirements must be met as drivers pull beyond the first step voltage. Equations
defining these maximums (C and D) are provided with the respective diagrams in Figure 4-5. The
equation-defined maximums should be met by design. In order to facilitate component testing, amaximum current test point is defined for each side of the output driver.

3.

This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the
instantaneous rate at any point within the transition range. The specified load (diagram below) is optional;i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI
Local Bus Specification . However, adherence to both maximum and minimum parameters is required (themaximum is not simply a guideline). Rise slew rate does not apply to open drain outputs.

pin

1/2 in. max.

outputbuffer

Vcc
1K Ω

10 pF

1K Ω

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123

Revision 2.2

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SRLQWVDUHHYDOXDWHGDWPD[LPXP9FFDQGORZWHPSHUDWXUH
Pull Down

Pull Up
Vcc

Voltage

0.9
Vcc

test
point

AC drive
point

Voltage

Vcc

0.6
Vcc

DC
drive point

0.5 Vcc
DC drive
point

0.3
Vcc
0.1
Vcc

AC drive
point

-0.5

-12

Current (mA)(TXDWLRQ&,RK  9FF 9RXW9FF-48

9RXW9FF

IRU9FF!9RXW!9FF

test
point

1.5

16

Current (mA)64

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WULVWDWHG5HIHUWR6HFWLRQIRUPRUHLQIRUPDWLRQ

124

Revision 2.2

4.2.2.3. Maximum AC Ratings and Device Protection
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Overvoltage Waveform
Voltage Source Impedance
R = 29 Ω

11 nSec(min)+ 7.1 v
7.1 v, p-to-p(minimum)3.3v. supplyRV

4 nSec(max)

Input
Buffer
Evaluation
Setup

0v

62.5 nSec(16 MHz)+ 3.6 v
7.1 v, p-to-p(minimum)- 3.5 v

Undervoltage Waveform
Voltage Source Impedance
R = 28 Ω)LJXUH0D[LPXP$&:DYHIRUPVIRU96LJQDOLQJ

125

Revision 2.2

4.2.3. Timing Specification
4.2.3.1. Clock Specification
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5 volt Clock

2.4 v

2.0 v
2 v, p-to-p(minimum)

1.5 v
0.8 v
0.4 v

T_cyc
T_high

3.3 volt Clock

0.6 Vcc

T_low

0.5 Vcc
0.4 Vcc, p-to-p(minimum)

0.4 Vcc
0.3 Vcc
0.2 Vcc)LJXUH&ORFN:DYHIRUPV126

Revision 2.2

7DEOH&ORFNDQG5HVHW6SHFLILFDWLRQV
SymbolParameter

Min

Max

Units

Notes

Tcyc

CLK Cycle Time

30

∞

ns

1

Thigh

CLK High Time

11

ns

Tlow

CLK Low Time

11

ns

-

CLK Slew Rate

1

4

V/ns

2

-

RST# Slew Rate

50

-

mV/ns

3

NOTES:
1.

In general, all PCI components must work with any clock frequency between
nominal DC and 33 MHz. Device operational parameters at frequencies under
16 MHz may be guaranteed by design rather than by testing. The clock
frequency may be changed at any time during the operation of the system solong as the clock edges remain "clean" (monotonic) and the minimum cycle
and high and low times are not violated. For example, the use of spread
spectrum techniques to reduce EMI emissions is included in this requirement.
Refer to Section 7.6.41. for the spread spectrum requirements for 66 MHz.
The clock may only be stopped in a low state. A variance on this specificationis allowed for components designed for use on the system motherboard only.
These components may operate at any single fixed frequency up to 33 MHz
and may enforce a policy of no frequency changes.

2.

Rise and fall times are specified in terms of the edge rate measured in V/ns.
This slew rate must be met across the minimum peak-to-peak portion of theclock waveform as shown in Figure 4-6.

3.

The minimum RST# slew rate applies only to the rising (deassertion) edge ofthe reset signal and ensures that system noise cannot render an otherwise
monotonic signal to appear to bounce in the switching range. RST#
waveforms and timing are discussed in Section 4.3.2.

127

Revision 2.2

4.2.3.2. Timing Parameters
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7DEOH9DQG97LPLQJ3DUDPHWHUVSymbolParameter

Min

Max

Units

Notes

Tval

CLK to Signal Valid Delay - bused signals

2

11

ns

1, 2, 3Tval(ptp)

CLK to Signal Valid Delay - point to point

2

12

ns

1, 2, 3Ton

Float to Active Delay

2

ns

1, 7

Toff

Active to Float Delay

ns

1, 7

Tsu

Input Setup Time to CLK - bused signals

7

ns

3, 4, 8Tsu(ptp)

Input Setup Time to CLK - point to point

10, 12

ns

3, 4

28

Th

Input Hold Time from CLK

0

ns

4

Trst

Reset active time after power stable

1

ms

5

Trst-clk

Reset active time after CLK STABLE

100

µs

5

Trst-off

Reset Active to Output Float delayns

5, 6,7

Trrsu

REQ64# to RST# Setup time

10*Tcyc

Trrh

RST# to REQ64# Hold time

0

Trhfa

RST# High to First configuration Access2

25

clocks

Trhff

RST# High to First FRAME# assertion

5

clocks

40

ns
50

ns

NOTES:
1.

See the timing measurement conditions in Figure 4-7.

2.

For parts compliant to the 5V signaling environment:
Minimum times are evaluated with 0 pF equivalent load; maximum times are evaluated with 50 pF
equivalent load. Actual test capacitance may vary, but results must be correlated to these
specifications. Note that faster buffers may exhibit some ring back when attached to a 50 pF lumpload which should be of no consequence as long as the output buffers are in full compliance withslew rate and V/I curve specifications.
For parts compliant to the 3.3V signaling environment:
Minimum times are evaluated with same load used for slew rate measurement (as shown in
Table 4-4, note 3); maximum times are evaluated with the following load circuits, for high-goingand low-going edges respectively.

Tval(max) Rising Edgepin

Tval(max) Falling Edge

1/2 in. max.
1/2 in. max.

outputbuffer
25 Ω

Vcc

10 pF
25 Ω
10 pF

128

3.

REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times
than do bused signals. GNT# has a setup of 10; REQ# has a setup of 12. All other signals are bused.

4.

See the timing measurement conditions in Figure 4-8.

5.

CLK is stable when it meets the requirements in Section 4.2.3.1. RST# is asserted and deasserted
asynchronously with respect to CLK. Refer to Section 4.3.2. for more information.

Revision 2.2
6.

All output drivers must be asynchronously floated when RST# is active. Refer to Section 3.10.2. for
special requirements for AD[63::32], C/BE[7::4]#, and PAR64 when they are not connected (as in a 64-bit
expansion board installed in a 32-bit connector).

7.

For purposes of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification.

8.

Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals
at the same time. Refer to Section 3.10., item 9, for additional details.

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V_th

CLK

V_test
V_tl
T_val

OUTPUT
DELAY

V_test (5v. signaling)
V_trise, V_tfall (3.3v. signaling)

output current

leakage current

Tri-State
OUTPUT
T_on
T_off)LJXUH2XWSXW7LPLQJ0HDVXUHPHQW&RQGLWLRQV

V_th

CLK

V_test
V_tl
T_su

T_h

V_th

INPUT

V_testinputsvalid

V_test

V_max

V_tl

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129

Revision 2.2

7DEOH0HDVXUH&RQGLWLRQ3DUDPHWHUVSymbol5V Signaling

3.3V Signaling

Units

Vth

2.4

0.6VccV (Note)Vtl

0.4

0.2VccV (Note)

Vtest

1.5

0.4VccV

Vtrisen/a0.285Vcc

V

Vtfalln/a0.615Vcc

V

Vmax

2.0

0.4VccV (Note)Input Signal
Edge Rate

1 V / ns

NOTE:
The input test for the 5V environment is done with 400 mV of overdrive(over Vih and Vil); the test for the 3.3V environment is done with
0.1Vcc of overdrive. Timing parameters must be met with no more
overdrive than this. V max specifies the maximum peak-to-peakwaveform allowed for measuring input timing. Production testing may
use different voltage values, but must correlate results back to theseparameters.

4.2.4. Indeterminate Inputs and Metastability$WWLPHVYDULRXVLQSXWVPD\EHLQGHWHUPLQDWH&RPSRQHQWVPXVWDYRLGORJLFDORSHUDWLRQDOHUURUVDQGPHWDVWDELOLW\E\VDPSOLQJLQSXWVRQO\RQTXDOLILHGFORFNHGJHV
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7KHIDSELSLQLVLQGHWHUPLQDWHDWDOOWLPHVH[FHSWGXULQJFRQILJXUDWLRQF\FOHV,ID
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130

Revision 2.2

7KHPME#DQGSERR#SLQVPXVWEHFRQVLGHUHGLQGHWHUPLQDWHIRUDQXPEHURIF\FOHV
DIWHUWKH\KDYHEHHQGHDVVHUWHG
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RIWLPHDIWHULWLVUHOHDVHG3LQVZLWKSXOOXSUHVLVWRUVZLOOHYHQWXDOO\UHVROYHKLJK

4.2.5. Vendor Provided Specification
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4.2.6. Pinout Recommendation
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PRWKHUERDUGVDUHHQFRXUDJHGDOVRWRIROORZWKLVVDPHVLJQDORUGHULQJWRDOORZOD\RXWVZLWKPLQLPXPVWXEV)LJXUHVKRZVWKHUHFRPPHQGHGSLQRXWIRUDW\SLFDO34)33&,
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FRPSRQHQWLQDFRXQWHUFORFNZLVHGLUHFWLRQLQWKHVDPHRUGHUWKH\DSSHDURQWKHELW
FRQQHFWRUH[WHQVLRQ

131

Revision 2.2

JTAG

{

PCI Component

RST#
CLK
GNT
REQ
All PCI Shared Signals
Below this Line

REQ64#
ACK64#
AD[0]
.
AD[7]
C/BE0#

AD[23].
AD[16]
C/BE2#
FRAME#IRDY#
TRDY#
DEVSEL#
STOP#
LOCK#
PERR#
SERR#
PAR
C/BE1#
AD[15].
.
AD[8]

AD[31].
.
AD[24]
C/BE3#IDSEL

PAR64
AD[32].
.
AD[63]
C/BE4#
C/BE5#
C/BE6#
C/BE7#PCI Card Edge

)LJXUH6XJJHVWHG3LQRXWIRU34)33&,&RPSRQHQW

3ODFLQJWKHIDSELLQSXWDVFORVHDVSRVVLEOHWRAD[31::11]DOORZVWKHRSWLRQIRUDQRQUHVLVWLYHFRQQHFWLRQRIIDSELWRWKHDSSURSULDWHDGGUHVVOLQHZLWKDVPDOODGGLWLRQDO
ORDG1RWHWKDWWKLVSLQKDVDORZHUFDSDFLWDQFHVSHFLILFDWLRQWKDWLQVRPHFDVHVZLOO
FRQVWUDLQLWVSODFHPHQWLQWKHSDFNDJH

4.3. System (Motherboard) Specification
4.3.1. Clock Skew
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GHILQHGLQ7DEOHDQG)LJXUH7KHPD[LPXPVNHZLVPHDVXUHGEHWZHHQDQ\WZRFRPSRQHQWVUDWKHUWKDQEHWZHHQFRQQHFWRUV7RFRUUHFWO\HYDOXDWHFORFNVNHZWKH
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31 Non-resistive connections of IDSEL to one of the AD[xx] lines create a technical violation of the single
load per expansion board rule. PCI protocol provides for pre-driving of address lines in configuration
cycles, and it is recommended that this be done in order to allow a resistive coupling of IDSEL. In absenceof this, signal performance must be derated for the extra IDSEL load.
32 The system designer must address an additional source of skew. This clock skew occurs between two

components that have clock input trip points at opposite ends of the Vil - Vih range. In certain
circumstances, this can add to the clock skew measurement as described here. In all cases, total clock skew
must be limited to the specified number.
132

Revision 2.2

7DEOH&ORFN6NHZ3DUDPHWHUVSymbol5V Signaling

3.3V Signaling

Units

Vtest

1.5

0.4 VccV

Tskew

2 (max)2 (max)

ns

V_ih
CLK
(@Device #1)

V_testV_il
T_skew

T_skew
T_skew
V_ih
CLK(@Device #2)

V_test
V_il)LJXUH&ORFN6NHZ'LDJUDP

4.3.2. Reset
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33 Component vendors should note that a fixed timing relationship between RST# and power sequencing

cannot be guaranteed in all cases.
133

Revision 2.2

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134

Revision 2.2

Implementation Note: Trhfa'HYLFHVDUHHQFRXUDJHGWRFRPSOHWHWKHLULQLWLDOL]DWLRQDQGEHUHDG\WRDFFHSWWKHLUILUVWF\FOH JHQHUDOO\D&RQILJXUDWLRQ5HDGF\FOH DVVRRQDVSRVVLEOHDIWHUWKHGHDVVHUWLRQRI
RST#6RPHV\VWHPLPSOHPHQWDWLRQVZLOODFFHVVGHYLFHVSULRUWRZDLWLQJWKHIXOOYDOXH
RI7UKIDLIWKH\NQRZLQDGYDQFHWKDWDOOGHYLFHVDUHUHDG\VRRQHU)RUH[DPSOHD
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WKHHPEHGGHGGHYLFHV6LPLODUO\DQLQWHOOLJHQWH[SDQVLRQERDUGWKDWLQLWLDOL]HGLWVRZQ
HPEHGGHG3&,GHYLFHVZRXOGRQO\QHHGWRZDLWIRUWKHLQLWLDOL]DWLRQUHTXLUHPHQWVRIWKRVHGHYLFHV
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FRQQHFWRU 

34 This reset timing figure optionally shows the "PWR_GOOD" signal as a pulse which is used to time the

RST# pulse. In many systems, "PWR_GOOD" may be a level, in which case the RST# pulse must be
timed in another way.
135

Revision 2.2

4.3.3. Pull-ups
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SERR#PERR#LOCK#, INTA#, INTB#, INTC#, INTD#,REQ64#DQG ACK64#
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137

Revision 2.2

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138

Revision 2.2

Implementation Note: Determining the End of Tprop
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139

Revision 2.2

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140

Revision 2.2

4.3.6. Physical Requirements
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141

Revision 2.2

4.3.7. Connector Pin Assignments
7KH3&,FRQQHFWRUFRQWDLQVDOOWKHVLJQDOVGHILQHGIRU3&,FRPSRQHQWVSOXVWZRSLQV
WKDWDUHUHODWHGWRWKHFRQQHFWRURQO\7KHVHSLQVPRSNT1#DQGPRSNT2#DUH
GHVFULEHGLQ6HFWLRQ0RWKHUERDUGVPXVWGHFRXSOHERWKRIWKHVHSLQVLQGLYLGXDOO\WRJURXQGZLWKµ)KLJKVSHHGFDSDFLWRUVEHFDXVHRQHRUERWKRIWKHSLQVDOVR
SURYLGHDQ$&UHWXUQSDWK7KHVHSLQVPD\QRWEHEXVHGRURWKHUZLVHFRQQHFWHGWRHDFKRWKHURQWKHPRWKHUERDUG)XUWKHUXVHRIWKHVHSLQVRQWKHPRWKHUERDUGLVRSWLRQDO,I
WKHPRWKHUERDUGGHVLJQDFFHVVHVWKHVHSLQVWRREWDLQERDUGLQIRUPDWLRQHDFKSLQPXVW
KDYHDQDSSURSULDWHSXOOXSUHVLVWRU RIDSSUR[LPDWHO\.Ω RQWKHPRWKHUERDUG7KH
FRQQHFWRUSLQDVVLJQPHQWVDUHVKRZQLQ7DEOH3LQVODEHOHG³5HVHUYHG´PXVWEH
OHIWXQFRQQHFWHGRQDOOFRQQHFWRUV
3LQ%LVDVSHFLDOSXUSRVHSLQWKDWKDVORJLFDOVLJQLILFDQFHLQ0+]FDSDEOH
V\VWHPVDQGLQVXFKV\VWHPVLWPXVWEHVHSDUDWHO\EXVHGSXOOHGXSDQGGHFRXSOHGDV
GHVFULEHGLQ6HFWLRQ)RUDOORWKHU3&,FRQQHFWRUVWKLVSLQPXVWEHWUHDWHGLQDOO
UHVSHFWVDVDVWDQGDUGJURXQGSLQLHWKHFRQQHFWRUSLQPXVWEHFRQQHFWHGWRWKHJURXQG
SODQH

142

Revision 2.2

7DEOH3&,&RQQHFWRU3LQRXW
5V System Environment

3.3V System Environment

Pin

Side BSide ASide BSide A

Comments

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

-12V
TCK
Ground
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
Reserved
PRSNT2#GroundGroundReserved
Ground
CLK
GroundREQ#+5V (I/O)
AD[31]
AD[29]
GroundAD[27]
AD[25]+3.3V
C/BE[3]#
AD[23]
GroundAD[21]
AD[19]+3.3V
AD[17]
C/BE[2]#GroundIRDY#+3.3V
DEVSEL#Ground
LOCK#
PERR#
+3.3V
SERR#

TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
Reserved+5V (I/O)
Reserved
GroundGround
3.3Vaux
RST#+5V (I/O)
GNT#
GroundPME#
AD[30]+3.3V
AD[28]
AD[26]
GroundAD[24]IDSEL+3.3V
AD[22]
AD[20]
GroundAD[18]
AD[16]+3.3V
FRAME#
GroundTRDY#
GroundSTOP#+3.3V
Reserved*
Reserved*
Ground-12V
TCK
Ground
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
Reserved
PRSNT2#

TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
Reserved+3.3V (I/O)
Reserved

32-bit connector start

CONNECTOR KEY
CONNECTOR KEY

Reserved
Ground
CLK
GroundREQ#+3.3V (I/O)
AD[31]
AD[29]
GroundAD[27]
AD[25]+3.3V
C/BE[3]#
AD[23]
GroundAD[21]
AD[19]+3.3V
AD[17]
C/BE[2]#GroundIRDY#+3.3V
DEVSEL#Ground
LOCK#
PERR#
+3.3V
SERR#

3.3 volt key
3.3 volt key

3.3Vaux
RST#+3.3V (I/O)
GNT#
GroundPME#
AD[30]+3.3V
AD[28]
AD[26]
GroundAD[24]IDSEL+3.3V
AD[22]
AD[20]
GroundAD[18]
AD[16]+3.3V
FRAME#
GroundTRDY#
GroundSTOP#+3.3V
Reserved*
Reserved*
Ground7KLVSLQZDVXVHGLQSUHYLRXVYHUVLRQVRIWKLVVSHFLILFDWLRQDQGPD\KDYHEHHQEXVHGWRRWKHU
FRQQHFWRUVDQGSXOOHGXS7REHFRPSODLQWZLWKWKLVYHUVLRQRIWKHVSHFLILFDWLRQWKLVSLQPXVWEH
OHIWXQFRQQHFWHG HJQRWEXVHGRUSXOOHGXS 

143

Revision 2.2

7DEOH3&,&RQQHFWRU3LQRXW FRQWLQXHG
5V System Environment
Pin

Side BSide ASide BSide A

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62

+3.3V
C/BE[1]#
AD[14]
GroundAD[12]
AD[10]
GroundPAR
AD[15]+3.3V
AD[13]
AD[11]
GroundAD[09]+3.3V
C/BE[1]#
AD[14]
GroundAD[12]
AD[10]
M66EN
GroundGroundAD[08]
AD[07]+3.3V
AD[05]
AD[03]
GroundAD[01]+3.3V (I/O)
ACK64#+5V+5V

PAR
AD[15]+3.3V
AD[13]
AD[11]
GroundAD[09]
GroundGroundC/BE[0]#+3.3V
AD[06]
AD[04]
GroundAD[02]
AD[00]+3.3V (I/O)
REQ64#+5V+5V

CONNECTOR KEY
CONNECTOR KEY

AD[08]
AD[07]+3.3V
AD[05]
AD[03]
GroundAD[01]+5V (I/O)
ACK64#+5V+5V

C/BE[0]#+3.3V
AD[06]
AD[04]
GroundAD[02]
AD[00]+5V (I/O)
REQ64#+5V+5V

CONNECTOR KEY
CONNECTOR KEY

63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

144

3.3V System Environment

Reserved
GroundC/BE[6]#
C/BE[4]#GroundAD[63]
AD[61]+5V (I/O)
AD[59]
AD[57]
GroundAD[55]
AD[53]
GroundAD[51]
AD[49]+5V (I/O)
AD[47]
AD[45]
GroundGroundC/BE[7]#
C/BE[5]#+5V (I/O)
PAR64
AD[62]
GroundAD[60]
AD[58]
GroundAD[56]
AD[54]+5V (I/O)
AD[52]
AD[50]
GroundAD[48]
AD[46]
GroundAD[44]

CONNECTOR KEY
CONNECTOR KEY

Reserved
GroundC/BE[6]#
C/BE[4]#GroundAD[63]
AD[61]+3.3V (I/O)
AD[59]
AD[57]
GroundAD[55]
AD[53]
GroundAD[51]
AD[49]+3.3V (I/O)
AD[47]
AD[45]
GroundGroundC/BE[7]#
C/BE[5]#+3.3V (I/O)
PAR64
AD[62]
GroundAD[60]
AD[58]
GroundAD[56]
AD[54]+3.3V (I/O)
AD[52]
AD[50]
GroundAD[48]
AD[46]
GroundAD[44]

Comments

66 MHz / gnd
5 volt key
5 volt key

32-bit connector end
64-bit spacer
64-bit spacer
64-bit connector startRevision 2.2

7DEOH3&,&RQQHFWRU3LQRXW FRQWLQXHG
5V System Environment

3.3V System Environment

Pin

Side BSide ASide BSide A

83
84
85
86
87
88
89
90
91
92
93
94

AD[43]
AD[41]
GroundAD[39]
AD[37]+5V (I/O)
AD[35]
AD[33]
GroundReserved
Reserved
GroundAD[42]+5V (I/O)
AD[40]
AD[38]
GroundAD[36]
AD[34]
GroundAD[32]
Reserved
GroundReserved

AD[43]
AD[41]
GroundAD[39]
AD[37]+3.3V (I/O)
AD[35]
AD[33]
GroundReserved
Reserved
GroundAD[42]+3.3V (I/O)
AD[40]
AD[38]
GroundAD[36]
AD[34]
GroundAD[32]
Reserved
GroundReserved

Comments

64-bit connector end

3LQVODEHOHG9 ,2 DQG9 ,2 DUHVSHFLDOSRZHUSLQVIRUGHILQLQJDQGGULYLQJ
WKH3&,VLJQDOLQJUDLORQWKH8QLYHUVDO%RDUG2QWKHPRWKHUERDUGWKHVHSLQVDUH
FRQQHFWHGWRWKHPDLQ9RU9SODQHUHVSHFWLYHO\5HIHUWR6HFWLRQIRUVSHFLDOUHTXLUHPHQWVIRUWKHFRQQHFWLRQRIREQ64#RQ
ELWRQO\H[SDQVLRQVORWFRQQHFWRUV

145

Revision 2.2

4.4. Expansion Board Specification
4.4.1. Board Pin Assignment
7KH3&,FRQQHFWRUFRQWDLQVDOOWKHVLJQDOVGHILQHGIRU3&,FRPSRQHQWVSOXVWZRSLQV
WKDWDUHUHODWHGWRWKHFRQQHFWRURQO\7KHVHDUHPRSNT1#DQGPRSNT2#7KH\DUH
XVHGIRUWZRSXUSRVHVLQGLFDWLQJWKDWDQH[SDQVLRQERDUGLVSK\VLFDOO\SUHVHQWLQWKH
VORWDQGSURYLGLQJLQIRUPDWLRQDERXWWKHWRWDOSRZHUUHTXLUHPHQWVRIWKHERDUG
7DEOHGHILQHVWKHUHTXLUHGVHWWLQJRIWKHPRSNT#SLQVIRUH[SDQVLRQERDUGV
7DEOH3UHVHQW6LJQDO'HILQLWLRQVPRSNT1#PRSNT2#

Expansion Configuration

Open

Open

No expansion board present

GroundOpen

Expansion board present, 25 W maximum

Open

GroundExpansion board present, 15 W maximum

GroundGroundExpansion board present, 7.5 W maximum,QSURYLGLQJDSRZHUOHYHOLQGLFDWLRQWKHH[SDQVLRQERDUGPXVWLQGLFDWHWRWDOPD[LPXP
SRZHUFRQVXPSWLRQIRUWKHERDUGLQFOXGLQJDOOVXSSO\YROWDJHV7KHH[SDQVLRQERDUGVPD\RSWLRQDOO\GUDZDOOWKLVSRZHUIURPHLWKHUWKH9RU9SRZHUUDLO)XUWKHUPRUH
LIWKHH[SDQVLRQERDUGLVFRQILJXUDEOH HJVRFNHWVIRUPHPRU\H[SDQVLRQHWF WKHSLQVWUDSSLQJPXVWLQGLFDWHWKHWRWDOSRZHUFRQVXPHGE\DIXOO\FRQILJXUHGERDUGZKLFKPD\EHPRUHWKDQWKDWFRQVXPHGLQLWVVKLSSLQJFRQILJXUDWLRQ([SDQVLRQERDUGVWKDWGRQRWLPSOHPHQW-7$*%RXQGDU\6FDQDUHUHTXLUHGWRFRQQHFW
TDIDQGTDO SLQV$DQG% VRWKHVFDQFKDLQLVQRWEURNHQ
3LQ%LVDVSHFLDOSXUSRVHSLQWKDWKDVORJLFDOVLJQLILFDQFHLQ0+]FDSDEOH
H[SDQVLRQERDUGVDQGLQVXFKERDUGVLWPXVWEHFRQQHFWHGDQGGHFRXSOHGDVGHVFULEHG
LQ6HFWLRQ)RUDOORWKHUH[SDQVLRQERDUGVWKLVSLQPXVWEHWUHDWHGLQDOOUHVSHFWVDV
DVWDQGDUGJURXQGSLQLHWKHHGJHILQJHUPXVWEHSODWHGDQGFRQQHFWHGWRWKHJURXQG
SODQHRIWKHH[SDQVLRQERDUG

146

Revision 2.2

7DEOH3&,([SDQVLRQ%RDUG3LQRXW
5V Board

Universal Board

3.3V Board

Pin

Side BSide ASide BSide ASide BSide A

Comments

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

-12V
TCK
Ground
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
Reserved
PRSNT2#GroundGroundReserved
Ground
CLK
GroundREQ#+5V
AD[31]
AD[29]
GroundAD[27]
AD[25]+3.3V
C/BE[3]#
AD[23]
GroundAD[21]
AD[19]+3.3V
AD[17]
C/BE[2]#GroundIRDY#+3.3V
DEVSEL#Ground
LOCK#
PERR#
+3.3V
SERR#

TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
Reserved+5V
Reserved
GroundGround
3.3Vaux
RST#
+5V
GNT#
GroundPME#
AD[30]+3.3V
AD[28]
AD[26]
GroundAD[24]IDSEL+3.3V
AD[22]
AD[20]
GroundAD[18]
AD[16]+3.3V
FRAME#
GroundTRDY#
GroundSTOP#+3.3V
Reserved
Reserved
Ground-12V
TCK
Ground
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
Reserved
PRSNT2#

TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
Reserved+VI/O
Reserved-12V
TCK
Ground
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
Reserved
PRSNT2#

TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
Reserved+3.3V
Reserved

32-bit start

KEYWAYKEYWAY

Reserved
Ground
CLK
GroundREQ#+VI/O
AD[31]
AD[29]
GroundAD[27]
AD[25]+3.3V
C/BE[3]#
AD[23]
GroundAD[21]
AD[19]+3.3V
AD[17]
C/BE[2]#GroundIRDY#+3.3V
DEVSEL#Ground
LOCK#
PERR#
+3.3V
SERR#

3.3Vaux
RST#
+VI/O
GNT#
GroundPME#
AD[30]+3.3V
AD[28]
AD[26]
GroundAD[24]IDSEL+3.3V
AD[22]
AD[20]
GroundAD[18]
AD[16]+3.3V
FRAME#
GroundTRDY#
GroundSTOP#+3.3V
Reserved
Reserved
GroundKEYWAYKEYWAY

Reserved
Ground
CLK
GroundREQ#+3.3V
AD[31]
AD[29]
GroundAD[27]
AD[25]+3.3V
C/BE[3]#
AD[23]
GroundAD[21]
AD[19]+3.3V
AD[17]
C/BE[2]#GroundIRDY#+3.3V
DEVSEL#Ground
LOCK#
PERR#
+3.3V
SERR#

3.3V key
3.3V key

3.3Vaux
RST#
+3.3V
GNT#
GroundPME#
AD[30]+3.3V
AD[28]
AD[26]
GroundAD[24]IDSEL+3.3V
AD[22]
AD[20]
GroundAD[18]
AD[16]+3.3V
FRAME#
GroundTRDY#
GroundSTOP#+3.3V
Reserved
Reserved
Ground147

Revision 2.2

7DEOH3&,([SDQVLRQ%RDUG3LQRXW FRQWLQXHG
5V Board

Universal Board

3.3V Board

Pin

Side BSide ASide BSide ASide BSide A

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62

+3.3V
C/BE[1]#
AD[14]
GroundAD[12]
AD[10]
GroundPAR
AD[15]+3.3V
AD[13]
AD[11]
GroundAD[09]+3.3V
C/BE[1]#
AD[14]
GroundAD[12]
AD[10]
M66EN

PAR
AD[15]+3.3V
AD[13]
AD[11]
GroundAD[09]+3.3V
C/BE[1]#
AD[14]
GroundAD[12]
AD[10]
M66EN
GroundGroundAD[08]
AD[07]+3.3V
AD[05]
AD[03]
GroundAD[01]+3.3V
ACK64#+5V+5V

PAR
AD[15]+3.3V
AD[13]
AD[11]
GroundAD[09]
GroundGroundC/BE[0]#+3.3V
AD[06]
AD[04]
GroundAD[02]
AD[00]+3.3V
REQ64#+5V+5V

KEYWAYKEYWAY

AD[08]
AD[07]+3.3V
AD[05]
AD[03]
GroundAD[01]+5V
ACK64#+5V+5V

C/BE[0]#+3.3V
AD[06]
AD[04]
GroundAD[02]
AD[00]+5V
REQ64#+5V+5V

KEYWAYKEYWAY

63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

148

Reserved
GroundC/BE[6]#
C/BE[4]#GroundAD[63]
AD[61]+5V
AD[59]
AD[57]
GroundAD[55]
AD[53]
GroundAD[51]
AD[49]+5V
AD[47]
AD[45]
GroundGroundC/BE[7]#
C/BE[5]#+5V
PAR64
AD[62]
GroundAD[60]
AD[58]
GroundAD[56]
AD[54]+5V
AD[52]
AD[50]
GroundAD[48]
AD[46]
GroundAD[44]KEYWAYKEYWAY

AD[08]
AD[07]+3.3V
AD[05]
AD[03]
GroundAD[01]+VI/O
ACK64#+5V+5V

C/BE[0]#+3.3V
AD[06]
AD[04]
GroundAD[02]
AD[00]+VI/O
REQ64#+5V+5V

KEYWAYKEYWAY

Reserved
GroundC/BE[6]#
C/BE[4]#GroundAD[63]
AD[61]+VI/O
AD[59]
AD[57]
GroundAD[55]
AD[53]
GroundAD[51]
AD[49]+VI/O
AD[47]
AD[45]
GroundGroundC/BE[7]#
C/BE[5]#
+VI/O
PAR64
AD[62]
GroundAD[60]
AD[58]
GroundAD[56]
AD[54]+VI/O
AD[52]
AD[50]
GroundAD[48]
AD[46]
GroundAD[44]KEYWAYKEYWAY

Reserved
GroundC/BE[6]#
C/BE[4]#GroundAD[63]
AD[61]+3.3V
AD[59]
AD[57]
GroundAD[55]
AD[53]
GroundAD[51]
AD[49]+3.3V
AD[47]
AD[45]
GroundGroundC/BE[7]#
C/BE[5]#
+3.3V
PAR64
AD[62]
GroundAD[60]
AD[58]
GroundAD[56]
AD[54]+3.3V
AD[52]
AD[50]
GroundAD[48]
AD[46]
GroundAD[44]

Comments

66 MHz /gnd
5V key5V key32-bit end
64-bit spacer
64-bit spacer
64-bit startRevision 2.2

7DEOH3&,([SDQVLRQ%RDUG3LQRXW FRQWLQXHG
5V Board

Universal Board

3.3V Board

Pin

Side BSide ASide BSide ASide BSide A

Comments

83
84
85
86
87
88
89
90
91
92
93
94

AD[43]
AD[41]
GroundAD[39]
AD[37]+5V
AD[35]
AD[33]
GroundReserved
Reserved
GroundAD[42]+5V
AD[40]
AD[38]
GroundAD[36]
AD[34]
GroundAD[32]
Reserved
GroundReserved

AD[43]
AD[41]
GroundAD[39]
AD[37]+VI/O
AD[35]
AD[33]
GroundReserved
Reserved
GroundAD[42]+VI/O
AD[40]
AD[38]
GroundAD[36]
AD[34]
GroundAD[32]
Reserved
GroundReserved

AD[43]
AD[41]
GroundAD[39]
AD[37]+3.3V
AD[35]
AD[33]
GroundReserved
Reserved
GroundAD[42]+3.3V
AD[40]
AD[38]
GroundAD[36]
AD[34]
GroundAD[32]
Reserved
GroundReserved

64-bit end

7DEOH3LQ6XPPDU\ELW([SDQVLRQ%RDUG
Pin Type

5V Board

Universal Board

3.3V Board

Ground
+5 V+3.3 VI/O pwr
Reserv’d

22
13
12
0
4

18 (Note)8125422 (Note)
8
17
0
4

NOTE:
If the M66EN pin is implemented, the number of ground pins for a Universal
board is 17 and the number of ground pins for a 3.3V board is 21.

7DEOH3LQ6XPPDU\ELW%RDUG LQFUHPHQWDOSLQV
Pin Type

5V Board

Universal Board

3.3V Board

Ground
+5 V+3.3 VI/O pwr
Reserv’d

16
6
0
0
5

16
0
0
6
5

16
0
6
0
5

149

Revision 2.2

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4.4.2. Power Requirements
4.4.2.1. Decoupling
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35 While the primary goal of the PCI 5V to 3.3V transition strategy is to spare vendors the burden and

expense of implementing 3.3V parts that are "5V tolerant," such parts are not excluded. If a PCI componentof this type is used on the Universal Board, its I/O buffers may optionally be connected to the 3.3V rail
rather than the "I/O" designated power pins; but high clamp diodes must still be connected to the "I/O"
designated power pins. (Refer to the last paragraph of Section 4.2.1.2. - "Clamping directly to the 3.3V railwith a simple diode must never be used in the 5V signaling environment.") Since the effective operation ofthese high clamp diodes may be critical to both signal quality and device reliability, the designer must
provide enough extra "I/O" designated power pins on a component to handle the current spikes associatedwith the 5V maximum AC waveforms (Section 4.2.1.3.).
150

Revision 2.2

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4.4.3.1. Trace Length Limits
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Chapter 5
Mechanical Specification
5.1. Overview
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36 It is highly recommended that adapter card designers implement I/O brackets which mount on thebackside of PCI cards as soon as possible to reduce their exposure to causing EMC leakage in systems.
37 It is highly recommended that system designers initiate requirements which include the use of this new

design by their adapter card suppliers.
162

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5.2.1. Connector Physical Description
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168

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5.2.1.1. Connector Physical Requirements
7DEOH&RQQHFWRU3K\VLFDO5HTXLUHPHQWV
Part

176

Materials

Connector Housing

High-temperature thermoplastic, UL flammability rating
94V-0, color: white.

Contacts

Phosphor bronze.

Contact Finish

0.000030 inch minimum gold over 0.000050 inch
minimum nickel in the contact area. Alternate finish:
gold flash over 0.000040 inch (1 micron) minimum
palladium or palladium-nickel over nickel in the contactarea.

Revision 2.2

5.2.1.2. Connector Performance Specification
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Specification

Durability

100 mating cycles without physical damage orexceeding low level contact resistance requirement
when mated with the recommended card edge.

Mating Force

6 oz. (1.7N) max. avg. per opposing contact pair using
MIL-STD-1344, Method 2013.1 and gauge per
MIL-C-21097 with profile as shown in add-in board
specification.

Contact Normal Force

75 grams minimum.

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Specification

Contact Resistance(low signal level) 30 mΩ max. initial, 10 mΩ max.
increase through testing. Contact resistance, test per
MIL-STD-1344, Method 3002.1.

Insulation Resistance1000 MΩ min. per MIL STD 202, Method 302,
Condition B.

Dielectric Withstand
Voltage

500 VAC RMS. per MIL-STD-1344, Method D3001.1
Condition 1.

Capacitance

2 pF max. @ 1 MHz.

Current Rating

1A, 30 °C rise above ambient.

Voltage Rating

125V.

Certification

UL Recognition and CSA Certification required.

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Specification

Operating Temperature-40 °C to 105 °C

Thermal Shock-55 °C to 85 °C, 5 cycles per MIL-STD-1344, Method1003.1.

Flowing Mixed Gas Test

Battelle, Class II. Connector mated with board andtested per Battelle method.

177

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5.2.2. Planar Implementation
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38 It is highly recommended that LPX system chassis designers utilize the PCI riser connector when

implementing riser cards on LPX systems and using adapter cards slots on 0.800” spacing.
39 It is highly recommended that LPX system chassis designers utilize the taller riser style of ISA and EISA

connectors when combining PCI and ISA/EISA.

181

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Revision 2.2

188Revision 2.2

Chapter 6
Configuration Space
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189

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6.1. Configuration Space Organization
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40 The device dependent region contains device specific information and is not described in this document.
41 The PC Card Standard is available from PCMCIA and contact information can be found at

http://www.pc-card.com
190

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Revision 2.2

6.2. Configuration Space Functions
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6.2.1. Device Identification)LYHILHOGVLQWKHSUHGHILQHGKHDGHUGHDOZLWKGHYLFHLGHQWLILFDWLRQ$OO3&,GHYLFHVDUH
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DUHUHDGRQO\192

Vendor ID

This field identifies the manufacturer of the device. Valid
vendor identifiers are allocated by the PCI SIG to ensure
uniqueness. 0FFFFh is an invalid value for Vendor ID.

Device ID

This field identifies the particular device. This identifier isallocated by the vendor.

Revision ID

This register specifies a device specific revision identifier.
The value is chosen by the vendor. Zero is an acceptablevalue. This field should be viewed as a vendor defined
extension to the Device ID.

Header Type

This byte identifies the layout of the second part of thepredefined header (beginning at byte 10h in Configuration
Space) and also whether or not the device contains multiple
functions. Bit 7 in this register is used to identify a multifunction device. If the bit is 0, then the device is single
function. If the bit is 1, then the device has multiple
functions. Bits 6 through 0 identify the layout of the second
part of the predefined header. The encoding 00h specifies thelayout shown in Figure 6-1. The encoding 01h is defined for
PCI-to-PCI bridges and is defined in the document PCI to
PCI Bridge Architecture Specification. The encoding 02h isdefined for a CardBus bridge and is documented in the PC
Card Standard. All other encodings are reserved.

Revision 2.2

Class Code

The Class Code register is read-only and is used to identify
the generic function of the device and, in some cases, aspecific register-level programming interface. The register isbroken into three byte-size fields. The upper byte (at offset
0Bh) is a base class code which broadly classifies the type offunction the device performs. The middle byte (at offset 0Ah)
is a sub-class code which identifies more specifically thefunction of the device. The lower byte (at offset 09h)
identifies a specific register-level programming interface (ifany) so that device independent software can interact with thedevice. Encodings for base class, sub-class, and programming
interface are provided in Appendix D. All unspecified
encodings are reserved.

6.2.2. Device Control
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15

10 9

8

7

6

5

4

3

2

1

0

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193

Revision 2.2

7DEOH&RPPDQG5HJLVWHU%LWV
Bit Location

194

Description

0

Controls a device’s response to I/O Space accesses. A value of 0
disables the device response. A value of 1 allows the device torespond to I/O Space accesses. State after RST# is 0.

1

Controls a device’s response to Memory Space accesses. A value of
0 disables the device response. A value of 1 allows the device torespond to Memory Space accesses. State after RST# is 0.

2

Controls a device’s ability to act as a master on the PCI bus. A valueof 0 disables the device from generating PCI accesses. A value of 1
allows the device to behave as a bus master. State after RST# is 0.

3

Controls a device’s action on Special Cycle operations. A value of 0
causes the device to ignore all Special Cycle operations. A value of 1
allows the device to monitor Special Cycle operations. State after
RST# is 0.

4This is an enable bit for using the Memory Write and Invalidate
command. When this bit is 1, masters may generate the command.
When it is 0, Memory Write must be used instead. State after RST# is
0. This bit must be implemented by master devices that can generate
the Memory Write and Invalidate command.

5

This bit controls how VGA compatible and graphics devices handle
accesses to VGA palette registers. When this bit is 1, palette
snooping is enabled (i.e., the device does not respond to paletteregister writes and snoops the data). When the bit is 0, the device
should treat palette write accesses like all other accesses. VGA
compatible devices should implement this bit. Refer to Section 3.10.
for more details on VGA palette snooping.

Revision 2.2

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Bit Location

Description

6

This bit controls the device’s response to parity errors. When the bit isset, the device must take its normal action when a parity error is
detected. When the bit is 0, the device sets its Detected Parity Error
status bit (bit 15 in the Status register) when an error is detected, butdoes not assert PERR# and continues normal operation. This bit’s
state after RST# is 0. Devices that check parity must implement thisbit. Devices are still required to generate parity even if parity checking
is disabled.

7

This bit is used to control whether or not a device does address/data
stepping. Devices that never do stepping must hardwire this bit to 0.
Devices that always do stepping must hardwire this bit to 1. Devices
that can do either, must make this bit read/write and have it initialize to
1 after RST#.

8This bit is an enable bit for the SERR# driver. A value of 0 disables
the SERR# driver. A value of 1 enables the SERR# driver. This bit’s
state after RST# is 0. All devices that have an SERR# pin must
implement this bit. Address parity errors are reported only if this bit
and bit 6 are 1.

9This optional read/write bit controls whether or not a master can dofast back-to-back transactions to different devices. Initialization
software will set the bit if all targets are fast back-to-back capable. A
value of 1 means the master is allowed to generate fast back-to-backtransactions to different agents as described in Section 3.4.2. A valueof 0 means fast back-to-back transactions are only allowed to thesame agent. This bit’s state after RST# is 0.

10-15

Reserved.

195

Revision 2.2

6.2.3. Device Status
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15 14 13 12 11 10 9 8

7

6

5

4

0
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Capabilities List
66 MHz Capable
Reserved
Fast Back-to-Back Capable
Master Data Parity Error
DEVSEL timing
00 - fast
01 - medium
10 - slow
Signaled Target Abort
Received Target Abort
Received Master Abort
Signaled System Error
Detected Parity Error)LJXUH6WDWXV5HJLVWHU/D\RXW

196

Revision 2.2

7DEOH6WDWXV5HJLVWHU%LWV
Bit Location

Description

0-3

Reserved.

4This optional read-only bit indicates whether or not this device
implements the pointer for a New Capabilities linked list at offset 34h.
A value of zero indicates that no New Capabilities linked list isavailable. A value of one indicates that the value read at offset 34h is apointer in Configuration Space to a linked list of new capabilities. Refer
to Section 6.7. for details on New Capabilities.

5

This optional read-only bit indicates whether or not this device iscapable of running at 66 MHz as defined in Chapter 7. A value of zero
indicates 33 MHz. A value of 1 indicates that the device is 66 MHz
capable.

6This bit is reserved42.

7This optional read-only bit indicates whether or not the target iscapable of accepting fast back-to-back transactions when thetransactions are not to the same agent. This bit can be set to 1 if thedevice can accept these transactions and must be set to 0 otherwise.
Refer to Section 3.4.2. for a complete description of requirements forsetting this bit.

8

This bit is only implemented by bus masters. It is set when three
conditions are met: 1) the bus agent asserted PERR# itself (on a read)or observed PERR# asserted (on a write); 2) the agent setting the bit
acted as the bus master for the operation in which the error occurred;and 3) the Parity Error Response bit (Command register) is set.

9-10

These bits encode the timing of DEVSEL#. Section 3.6.1. specifies
three allowable timings for assertion of DEVSEL#. These are
encoded as 00b for fast, 01b for medium, and 10b for slow (11b isreserved). These bits are read-only and must indicate the slowest timethat a device asserts DEVSEL# for any bus command except
Configuration Read and Configuration Write.

42 In Revision 2.1 of this specification, this bit was used to indicate whether or not a device supported User

Definable Features.

197

Revision 2.2

7DEOH6WDWXV5HJLVWHU%LWV FRQWLQXHG
Bit Location

Description

11

This bit must be set by a target device whenever it terminates atransaction with Target-Abort. Devices that will never signal TargetAbort do not need to implement this bit.

12

This bit must be set by a master device whenever its transaction is
terminated with Target-Abort. All master devices must implement this
bit.

13

This bit must be set by a master device whenever its transaction(except for Special Cycle) is terminated with Master-Abort. All masterdevices must implement this bit.

14

This bit must be set whenever the device asserts SERR#. Devices
who will never assert SERR# do not need to implement this bit.

15

This bit must be set by the device whenever it detects a parity error,
even if parity error handling is disabled (as controlled by bit 6 in theCommand register).

6.2.4. Miscellaneous Registers
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198

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7

6

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0

Rsvd

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Bit Location

Description

7

Return 1 if device supports BIST. Return 0 if the device is not BIST
capable.

6

Write a 1 to invoke BIST. Device resets the bit when BIST is complete.
Software should fail the device if BIST is not complete after 2 seconds.

5-4

Reserved. Device returns 0.

3-0

A value of 0 means the device has passed its test. Non-zero values
mean the device failed. Device-specific failure codes can be encodedin the non-zero value.

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IXQFWLRQV WKDWGRQRWXVHDQLQWHUUXSWSLQPXVWSXWDLQWKLVUHJLVWHU7KHYDOXHVKWKURXJK))KDUHUHVHUYHG7KLVUHJLVWHULVUHDGRQO\5HIHUWR6HFWLRQIRUIXUWKHU
GHVFULSWLRQRIWKHXVDJHRIWKHINTx#SLQV
0,1B*17DQG0$;B/$7
7KHVHUHDGRQO\E\WHUHJLVWHUVDUHXVHGWRVSHFLI\WKHGHYLFH¶VGHVLUHGVHWWLQJVIRU/DWHQF\7LPHUYDOXHV)RUERWKUHJLVWHUVWKHYDOXHVSHFLILHVDSHULRGRIWLPHLQXQLWVRIóPLFURVHFRQG9DOXHVRILQGLFDWHWKDWWKHGHYLFHKDVQRPDMRUUHTXLUHPHQWVIRUWKH
VHWWLQJVRI/DWHQF\7LPHUV
0,1B*17LVXVHGIRUVSHFLI\LQJKRZORQJDEXUVWSHULRGWKHGHYLFHQHHGVDVVXPLQJD
FORFNUDWHRI0+]0$;B/$7LVXVHGIRUVSHFLI\LQJKRZRIWHQWKHGHYLFHQHHGVWR
JDLQDFFHVVWRWKH3&,EXV'HYLFHVVKRXOGVSHFLI\YDOXHVWKDWZLOODOORZWKHPWRPRVWHIIHFWLYHO\XVHWKH3&,EXVDVZHOODVWKHLULQWHUQDOUHVRXUFHV9DOXHVVKRXOGEHFKRVHQDVVXPLQJWKDWWKHWDUJHWGRHV
QRWLQVHUWDQ\ZDLWVWDWHV

Implementation Example: Choosing MIN_GNT and MAX_LAT$IDVW(WKHUQHWFRQWUROOHU 0EV KDVDE\WHEXIIHUIRUHDFKWUDQVIHUGLUHFWLRQ
2SWLPDOXVDJHRIWKHVHLQWHUQDOUHVRXUFHVLVDFKLHYHGZKHQWKHGHYLFHWUHDWVHDFKEXIIHU
DVWZRE\WHSLQJSRQJEXIIHUV(DFKE\WHEXIIHUKDVHLJKW':25'6RIGDWDWREH
WUDQVIHUUHGUHVXOWLQJLQHLJKWGDWDSKDVHVRQWKH3&,EXV7KHVHHLJKWGDWDSKDVHVWUDQVODWHWRóPLFURVHFRQGDW0+]VRWKH0,1B*17YDOXHIRUWKLVGHYLFHLV³´
:KHQPRYLQJGDWDWKHGHYLFHZLOOQHHGWRHPSW\RUILOODE\WHEXIIHUHYHU\µV
DVVXPLQJDWKURXJKSXWRI0%V 7KLVZRXOGFRUUHVSRQGWRD0$;B/$7YDOXHRI
6XEV\VWHP9HQGRU,'DQG6XEV\VWHP,'
7KHVHUHJLVWHUVDUHXVHGWRXQLTXHO\LGHQWLI\WKHH[SDQVLRQERDUGRUVXEV\VWHPZKHUHWKH
3&,GHYLFHUHVLGHV7KH\SURYLGHDPHFKDQLVPIRUH[SDQVLRQERDUGYHQGRUVWRGLVWLQJXLVKWKHLUERDUGVIURPRQHDQRWKHUHYHQWKRXJKWKHERDUGVPD\KDYHWKHVDPH3&,
FRQWUROOHURQWKHP DQGWKHUHIRUHWKHVDPH9HQGRU,'DQG'HYLFH,' 

43 For x86 based PCs, the values in this register correspond to IRQ numbers (0-15) of the standard dual

8259 configuration. The value 255 is defined as meaning "unknown" or "no connection" to the interrupt
controller. Values between 15 and 254 are reserved.
200

Revision 2.2,PSOHPHQWDWLRQRIWKHVHUHJLVWHUVLVUHTXLUHGIRUDOO3&,GHYLFHVH[FHSWWKRVHWKDWKDYHDEDVHFODVVZLWKVXEFODVV  RUDEDVHFODVVZLWKVXEFODVV  6XEV\VWHP9HQGRU,'VFDQEHREWDLQHGIURPWKH3&,6,*DQGDUHXVHGWRLGHQWLI\WKH
YHQGRURIWKHH[SDQVLRQERDUGRUVXEV\VWHP9DOXHVIRUWKH6XEV\VWHP,'DUHYHQGRU
VSHFLILF
9DOXHVLQWKHVHUHJLVWHUVPXVWEHORDGHGDQGYDOLGSULRUWRWKHV\VWHP%,26RUDQ\
V\VWHPVRIWZDUHDFFHVVLQJWKH3&,&RQILJXUDWLRQ6SDFH+RZWKHVHYDOXHVDUHORDGHGLV
QRWVSHFLILHGEXWFRXOGEHGRQHGXULQJWKHPDQXIDFWXULQJSURFHVVRUORDGHGIURP
H[WHUQDOORJLF HJVWUDSSLQJRSWLRQVVHULDO520VHWF 7KHVHYDOXHVPXVWQRWEH
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JXDUDQWHHLQJWKHGDWDLVYDOLGEHIRUHDOORZLQJUHDGVWRWKHVHUHJLVWHUVWRFRPSOHWH7KLV
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,IDGHYLFHLVGHVLJQHGWREHXVHGH[FOXVLYHO\RQWKHPRWKHUERDUGWKHV\VWHPYHQGRUPD\
XVHV\VWHPVSHFLILFVRIWZDUHWRLQLWLDOL]HWKHVHUHJLVWHUVDIWHUHDFKSRZHURQ&DSDELOLWLHV3RLQWHU
7KLVRSWLRQDOUHJLVWHULVXVHGWRSRLQWWRDOLQNHGOLVWRIQHZFDSDELOLWLHVLPSOHPHQWHGE\
WKLVGHYLFH7KLVUHJLVWHULVRQO\YDOLGLIWKH³&DSDELOLWLHV/LVW´ELWLQWKH6WDWXV5HJLVWHU
LVVHW,ILPSOHPHQWHGWKHERWWRPWZRELWVDUHUHVHUYHGDQGVKRXOGEHVHWWRE
6RIWZDUHVKRXOGPDVNWKHVHELWVRIIEHIRUHXVLQJWKLVUHJLVWHUDVDSRLQWHULQ&RQILJXUDWLRQ6SDFHWRWKHILUVWHQWU\RIDOLQNHGOLVWRIQHZFDSDELOLWLHV5HIHUWR
6HFWLRQIRUDGHVFULSWLRQRIWKLVGDWDVWUXFWXUH

6.2.5. Base Addresses
2QHRIWKHPRVWLPSRUWDQWIXQFWLRQVIRUHQDEOLQJVXSHULRUFRQILJXUDELOLW\DQGHDVHRIXVH
LVWKHDELOLW\WRUHORFDWH3&,GHYLFHVLQWKHDGGUHVVVSDFHV$WV\VWHPSRZHUXSGHYLFH
LQGHSHQGHQWVRIWZDUHPXVWEHDEOHWRGHWHUPLQHZKDWGHYLFHVDUHSUHVHQWEXLOGDFRQVLVWHQWDGGUHVVPDSDQGGHWHUPLQHLIDGHYLFHKDVDQH[SDQVLRQ520(DFKRIWKHVH
DUHDVLVFRYHUHGLQWKHIROORZLQJVHFWLRQV

6.2.5.1. Address Maps
3RZHUXSVRIWZDUHQHHGVWREXLOGDFRQVLVWHQWDGGUHVVPDSEHIRUHERRWLQJWKHPDFKLQH
WRDQRSHUDWLQJV\VWHP7KLVPHDQVLWKDVWRGHWHUPLQHKRZPXFKPHPRU\LVLQWKH
V\VWHPDQGKRZPXFKDGGUHVVVSDFHWKH,2FRQWUROOHUVLQWKHV\VWHPUHTXLUH$IWHU
GHWHUPLQLQJWKLVLQIRUPDWLRQSRZHUXSVRIWZDUHFDQPDSWKH,2FRQWUROOHUVLQWR
UHDVRQDEOHORFDWLRQVDQGSURFHHGZLWKV\VWHPERRW,QRUGHUWRGRWKLVPDSSLQJLQD
GHYLFHLQGHSHQGHQWPDQQHUWKHEDVHUHJLVWHUVIRUWKLVPDSSLQJDUHSODFHGLQWKH
SUHGHILQHGKHDGHUSRUWLRQRI&RQILJXUDWLRQ6SDFH
%LWLQDOO%DVH$GGUHVVUHJLVWHUVLVUHDGRQO\DQGXVHGWRGHWHUPLQHZKHWKHUWKH
UHJLVWHUPDSVLQWR0HPRU\RU,26SDFH%DVH$GGUHVVUHJLVWHUVWKDWPDSWR0HPRU\
44 A company has only one Vendor ID. That value can be used in either the Vendor ID field ofconfiguration space (offset 00h) or the Subsystem Vendor ID field of configuration space (offset 2Ch). It is
used in the Vendor ID field (offset 00h) if the company built the silicon. It is used in the Subsystem Vendor
ID field (offset 2Ch) if the company built the add-in card. If a company builds both the silicon and the addin card, then the same value would be used in both fields.

201

Revision 2.2

6SDFHPXVWUHWXUQDLQELW VHH)LJXUH %DVH$GGUHVVUHJLVWHUVWKDWPDSWR,2
6SDFHPXVWUHWXUQDLQELW VHH)LJXUH )LJXUH%DVH$GGUHVV5HJLVWHUIRU0HPRU\

31

2 1 0
Base Address

0 1

Reserved
IO space indicator)LJXUH%DVH$GGUHVV5HJLVWHUIRU,2%DVH$GGUHVVUHJLVWHUVWKDWPDSLQWR,26SDFHDUHDOZD\VELWVZLGHZLWKELWKDUGZLUHGWRD%LWLVUHVHUYHGDQGPXVWUHWXUQRQUHDGVDQGWKHRWKHUELWVDUHXVHG
WRPDSWKHGHYLFHLQWR,26SDFH
%DVH$GGUHVVUHJLVWHUVWKDWPDSLQWR0HPRU\6SDFHFDQEHELWVRUELWVZLGH WR
VXSSRUWPDSSLQJLQWRDELWDGGUHVVVSDFH ZLWKELWKDUGZLUHGWRD)RU0HPRU\%DVH$GGUHVVUHJLVWHUVELWVDQGKDYHDQHQFRGHGPHDQLQJDVVKRZQLQ7DEOH
%LWVKRXOGEHVHWWRLIWKHGDWDLVSUHIHWFKDEOHDQGUHVHWWRRWKHUZLVH$GHYLFHFDQ
PDUNDUDQJHDVSUHIHWFKDEOHLIWKHUHDUHQRVLGHHIIHFWVRQUHDGVWKHGHYLFHUHWXUQVDOO
E\WHVRQUHDGVUHJDUGOHVVRIWKHE\WHHQDEOHVDQGKRVWEULGJHVFDQPHUJHSURFHVVRUZULWHV UHIHUWR6HFWLRQ LQWRWKLVUDQJHZLWKRXWFDXVLQJHUURUV%LWVDUHUHDGRQO\45 Any device that has a range that behaves like normal memory should mark the range as prefetchable. A

linear frame buffer in a graphics device is an example of a range that should be marked prefetchable.
202

Revision 2.2

7DEOH0HPRU\%DVH$GGUHVV5HJLVWHU%LWV(QFRGLQJ
Bits 2/1

Meaning00

Base register is 32 bits wide and mapping can bedone anywhere in the 32-bit Memory Space.

01

Reserved46

10

Base register is 64 bits wide and can be mapped
anywhere in the 64-bit address space.

11

Reserved

7KHQXPEHURIXSSHUELWVWKDWDGHYLFHDFWXDOO\LPSOHPHQWVGHSHQGVRQKRZPXFKRIWKH
DGGUHVVVSDFHWKHGHYLFHZLOOUHVSRQGWR$ELWUHJLVWHUFDQEHLPSOHPHQWHGWR
VXSSRUWDVLQJOHPHPRU\VL]HWKDWLVDSRZHURIIURPE\WHVWR*%$GHYLFHWKDWZDQWVD0%PHPRU\DGGUHVVVSDFH XVLQJDELWEDVHDGGUHVVUHJLVWHU ZRXOGEXLOG
WKHWRSELWVRIWKHDGGUHVVUHJLVWHUKDUGZLULQJWKHRWKHUELWVWR
3RZHUXSVRIWZDUHFDQGHWHUPLQHKRZPXFKDGGUHVVVSDFHWKHGHYLFHUHTXLUHVE\ZULWLQJ
DYDOXHRIDOO VWRWKHUHJLVWHUDQGWKHQUHDGLQJWKHYDOXHEDFN7KHGHYLFHZLOOUHWXUQ VLQDOOGRQ WFDUHDGGUHVVELWVHIIHFWLYHO\VSHFLI\LQJWKHDGGUHVVVSDFHUHTXLUHG
8QLPSOHPHQWHG%DVH$GGUHVVUHJLVWHUVDUHKDUGZLUHGWR]HUR
7KLVGHVLJQLPSOLHVWKDWDOODGGUHVVVSDFHVXVHGDUHDSRZHURIWZRLQVL]HDQGDUH
QDWXUDOO\DOLJQHG'HYLFHVDUHIUHHWRFRQVXPHPRUHDGGUHVVVSDFHWKDQUHTXLUHGEXW
GHFRGLQJGRZQWRD.%VSDFHIRUPHPRU\LVVXJJHVWHGIRUGHYLFHVWKDWQHHGOHVVWKDQ
WKDWDPRXQW)RULQVWDQFHDGHYLFHWKDWKDVE\WHVRIUHJLVWHUVWREHPDSSHGLQWR
0HPRU\6SDFHPD\FRQVXPHXSWR.%RIDGGUHVVVSDFHLQRUGHUWRPLQLPL]HWKH
QXPEHURIELWVLQWKHDGGUHVVGHFRGHU'HYLFHVWKDWGRFRQVXPHPRUHDGGUHVVVSDFHWKDQ
WKH\XVHDUHQRWUHTXLUHGWRUHVSRQGWRWKHXQXVHGSRUWLRQRIWKDWDGGUHVVVSDFH'HYLFHVWKDWPDSFRQWUROIXQFWLRQVLQWR,26SDFHPXVWQRWFRQVXPHPRUHWKDQE\WHVSHU,2%DVH$GGUHVVUHJLVWHU7KHXSSHUELWVRIWKH,2%DVH$GGUHVVUHJLVWHUPD\EH
KDUGZLUHGWR]HURIRUGHYLFHVLQWHQGHGIRUELW,2V\VWHPVVXFKDV3&FRPSDWLEOHV+RZHYHUDIXOOELWGHFRGHRI,2DGGUHVVHVPXVWVWLOOEHGRQH

46 The encoding to support memory space below 1M was supported in previous versions of thespecification. System software should recognize this encoding and handle appropriately.

203

Revision 2.2

Implementation Note: Sizing a 32 bit Base Address Register
Example'HFRGH ,2RUPHPRU\ RIDUHJLVWHULVGLVDEOHGYLDWKHFRPPDQGUHJLVWHUEHIRUHVL]LQJ
D%DVH$GGUHVVUHJLVWHU6RIWZDUHVDYHVWKHRULJLQDOYDOXHRIWKH%DVH$GGUHVVUHJLVWHUZULWHV))))))))KWRWKHUHJLVWHUWKHQUHDGVLWEDFN6L]HFDOFXODWLRQFDQEHGRQHIURP
WKHELWYDOXHUHDGE\ILUVWFOHDULQJHQFRGLQJLQIRUPDWLRQELWV ELWIRU,2ELWVIRU
PHPRU\ LQYHUWLQJDOOELWV ORJLFDO127 WKHQLQFUHPHQWLQJE\7KHUHVXOWDQW
ELWYDOXHLVWKHPHPRU\,2UDQJHVL]HGHFRGHGE\WKHUHJLVWHU1RWHWKDWWKHXSSHUELWVRIWKHUHVXOWLVLJQRUHGLIWKH%DVH$GGUHVVUHJLVWHULVIRU,2DQGELWVUHWXUQHG]HURXSRQUHDG7KHRULJLQDOYDOXHLQWKH%DVH$GGUHVVUHJLVWHULVUHVWRUHGEHIRUHUHHQDEOLQJGHFRGHLQWKHFRPPDQGUHJLVWHURIWKHGHYLFHELW PHPRU\ %DVH$GGUHVVUHJLVWHUVFDQEHKDQGOHGWKHVDPHH[FHSWWKDWWKHVHFRQG
ELWUHJLVWHULVFRQVLGHUHGDQH[WHQVLRQRIWKHILUVWLHELWV6RIWZDUHZULWHV))))))))KWRERWKUHJLVWHUVUHDGVWKHPEDFNDQGFRPELQHVWKHUHVXOWLQWRDELWYDOXH6L]HFDOFXODWLRQLVGRQHRQWKHELWYDOXH$W\SHKSUHGHILQHGKHDGHUKDVVL[':25'ORFDWLRQVDOORFDWHGIRU%DVH$GGUHVVUHJLVWHUVVWDUWLQJDWRIIVHWKLQ&RQILJXUDWLRQ6SDFH$GHYLFHPD\XVHDQ\RIWKH
ORFDWLRQVWRLPSOHPHQW%DVH$GGUHVVUHJLVWHUV$QLPSOHPHQWHGELW%DVH$GGUHVVUHJLVWHUFRQVXPHVWZRFRQVHFXWLYH':25'ORFDWLRQV6RIWZDUHORRNLQJIRU
LPSOHPHQWHG%DVH$GGUHVVUHJLVWHUVPXVWVWDUWDWRIIVHWKDQGFRQWLQXHXSZDUGVWKURXJKRIIVHWK$W\SLFDOGHYLFHZLOOUHTXLUHRQHPHPRU\UDQJHIRULWVFRQWUROIXQFWLRQV6RPHJUDSKLFVGHYLFHVPD\XVHWZRUDQJHVRQHIRUFRQWUROIXQFWLRQVDQG
DQRWKHUIRUDIUDPHEXIIHU$GHYLFHWKDWZDQWVWRPDSFRQWUROIXQFWLRQVLQWRERWKPHPRU\DQG,26SDFHVDWWKHVDPHWLPHPXVWLPSOHPHQWWZR%DVH$GGUHVVUHJLVWHUV
RQHPHPRU\DQGRQH,2 7KHGULYHUIRUWKDWGHYLFHPLJKWRQO\XVHRQHVSDFHLQZKLFK
FDVHWKHRWKHUVSDFHZLOOEHXQXVHG'HYLFHVDUHUHFRPPHQGHGDOZD\VWRPDSFRQWUROIXQFWLRQVLQWR0HPRU\6SDFH

6.2.5.2. Expansion ROM Base Address Register
6RPH3&,GHYLFHVHVSHFLDOO\WKRVHWKDWDUHLQWHQGHGIRUXVHRQH[SDQVLRQERDUGVLQ3&
DUFKLWHFWXUHVUHTXLUHORFDO(3520VIRUH[SDQVLRQ520 UHIHUWR6HFWLRQIRUD
GHILQLWLRQRI520FRQWHQWV 7KHIRXUE\WHUHJLVWHUDWRIIVHWKLQDW\SHK
SUHGHILQHGKHDGHULVGHILQHGWRKDQGOHWKHEDVHDGGUHVVDQGVL]HLQIRUPDWLRQIRUWKLV
H[SDQVLRQ520)LJXUHVKRZVKRZWKLVZRUGLVRUJDQL]HG7KHUHJLVWHUIXQFWLRQV
H[DFWO\OLNHDELW%DVH$GGUHVVUHJLVWHUH[FHSWWKDWWKHHQFRGLQJ DQGXVDJH RIWKH
ERWWRPELWVLVGLIIHUHQW7KHXSSHUELWVFRUUHVSRQGWRWKHXSSHUELWVRIWKH([SDQVLRQ520EDVHDGGUHVV7KHQXPEHURIELWV RXWRIWKHVH WKDWDGHYLFHDFWXDOO\LPSOHPHQWVGHSHQGVRQKRZPXFKDGGUHVVVSDFHWKHGHYLFHUHTXLUHV)RU
LQVWDQFHDGHYLFHWKDWUHTXLUHVD.%DUHDWRPDSLWVH[SDQVLRQ520ZRXOGLPSOHPHQWWKHWRSELWVLQWKHUHJLVWHUOHDYLQJWKHERWWRP RXWRIWKHVHKDUGZLUHGWR'HYLFHVWKDWVXSSRUWDQH[SDQVLRQ520PXVWLPSOHPHQWWKLVUHJLVWHU'HYLFHLQGHSHQGHQWFRQILJXUDWLRQVRIWZDUHFDQGHWHUPLQHKRZPXFKDGGUHVVVSDFHWKH
GHYLFHUHTXLUHVE\ZULWLQJDYDOXHRIDOO VWRWKHDGGUHVVSRUWLRQRIWKHUHJLVWHUDQGWKHQ
UHDGLQJWKHYDOXHEDFN7KHGHYLFHZLOOUHWXUQ VLQDOOGRQ WFDUHELWVHIIHFWLYHO\VSHFLI\LQJWKHVL]HDQGDOLJQPHQWUHTXLUHPHQWV7KHDPRXQWRIDGGUHVVVSDFHDGHYLFH
UHTXHVWVPXVWQRWEHJUHDWHUWKDQ0%

204

Revision 2.2

31

1 0

11 10
Expansion ROM Base Address(Upper 21 bits)

Reserved

Expansion ROM Enable)LJXUH([SDQVLRQ520%DVH$GGUHVV5HJLVWHU/D\RXW%LWLQWKHUHJLVWHULVXVHGWRFRQWUROZKHWKHURUQRWWKHGHYLFHDFFHSWVDFFHVVHVWRLWV
H[SDQVLRQ520:KHQWKLVELWLVWKHGHYLFH¶VH[SDQVLRQ520DGGUHVVVSDFHLV
GLVDEOHG:KHQWKHELWLVDGGUHVVGHFRGLQJLVHQDEOHGXVLQJWKHSDUDPHWHUVLQWKH
RWKHUSDUWRIWKHEDVHUHJLVWHU7KLVDOORZVDGHYLFHWREHXVHGZLWKRUZLWKRXWDQ
H[SDQVLRQ520GHSHQGLQJRQV\VWHPFRQILJXUDWLRQ7KH0HPRU\6SDFHELWLQWKH&RPPDQGUHJLVWHUKDVSUHFHGHQFHRYHUWKH([SDQVLRQ520HQDEOHELW$GHYLFHPXVW
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WKHH[SDQVLRQ520DQGGHYLFHLQGHSHQGHQWVRIWZDUHPXVWQRWDFFHVVWKHGHYLFHWKURXJKDQ\RWKHU%DVH$GGUHVVUHJLVWHUV

6.3. PCI Expansion ROMs
7KH3&,VSHFLILFDWLRQSURYLGHVDPHFKDQLVPZKHUHGHYLFHVFDQSURYLGHH[SDQVLRQ520
FRGHWKDWFDQEHH[HFXWHGIRUGHYLFHVSHFLILFLQLWLDOL]DWLRQDQGSRVVLEO\DV\VWHPERRW
IXQFWLRQ UHIHUWR6HFWLRQ 7KHPHFKDQLVPDOORZVWKH520WRFRQWDLQVHYHUDO
GLIIHUHQWLPDJHVWRDFFRPPRGDWHGLIIHUHQWPDFKLQHDQGSURFHVVRUDUFKLWHFWXUHV7KLV
VHFWLRQVSHFLILHVWKHUHTXLUHGLQIRUPDWLRQDQGOD\RXWRIFRGHLPDJHVLQWKHH[SDQVLRQ5201RWHWKDW3&,GHYLFHVWKDWVXSSRUWDQH[SDQVLRQ520PXVWDOORZWKDW520WR
EHDFFHVVHGZLWKDQ\FRPELQDWLRQRIE\WHHQDEOHV7KLVVSHFLILFDOO\PHDQVWKDW':25'DFFHVVHVWRWKHH[SDQVLRQ520PXVWEHVXSSRUWHG
7KHLQIRUPDWLRQLQWKH520VLVODLGRXWWREHFRPSDWLEOHZLWKH[LVWLQJ,QWHO[([SDQVLRQ520KHDGHUVIRU,6$(,6$DQG0&DGDSWHUVEXWLWZLOODOVRVXSSRUWRWKHUPDFKLQHDUFKLWHFWXUHV7KHLQIRUPDWLRQDYDLODEOHLQWKHKHDGHUKDVEHHQH[WHQGHGVRWKDW
PRUHRSWLPXPXVHFDQEHPDGHRIWKHIXQFWLRQSURYLGHGE\WKHDGDSWHUDQGVRWKDWWKH
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7KH3&,([SDQVLRQ520KHDGHULQIRUPDWLRQVXSSRUWVWKHIROORZLQJIXQFWLRQV•$OHQJWKFRGHLVSURYLGHGWRLGHQWLI\WKHWRWDOFRQWLJXRXVDGGUHVVVSDFHQHHGHGE\
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520DGGUHVVVSDFHLQHDFK520LPDJH•$UHYLVLRQOHYHOIRUWKHFRGHDQGGDWDRQWKH520LVSURYLGHG

•7KH9HQGRU,'DQG'HYLFH,'RIWKHVXSSRUWHG3&,GHYLFHDUHLQFOXGHGLQWKH520

47Note that it is the address decoder that is shared, not the registers themselves. The Expansion ROM Base

Address register and other Base Address registers must be able to hold unique values at the same time.

205

Revision 2.2

2QHPDMRUGLIIHUHQFHLQWKHXVDJHPRGHOEHWZHHQ3&,H[SDQVLRQ520VDQGVWDQGDUG,6$(,6$DQG0&520VLVWKDWWKH520FRGHLVQHYHUH[HFXWHGLQSODFH,WLVDOZD\VFRSLHGIURPWKH520GHYLFHWR5$0DQGH[HFXWHGIURP5$07KLVHQDEOHVG\QDPLF
VL]LQJRIWKHFRGH IRULQLWLDOL]DWLRQDQGUXQWLPH DQGSURYLGHVVSHHGLPSURYHPHQWVZKHQ
H[HFXWLQJUXQWLPHFRGH

6.3.1. PCI Expansion ROM Contents
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SURFHVVRUDUFKLWHFWXUHV7KLVPD\EHLPSOHPHQWHGLQDVLQJOHSK\VLFDO520ZKLFKFDQ
FRQWDLQDVPDQ\FRGHLPDJHVDVGHVLUHGIRUGLIIHUHQWV\VWHPDQGSURFHVVRUDUFKLWHFWXUHV
VHH)LJXUH (DFKLPDJHPXVWVWDUWRQDE\WHERXQGDU\DQGPXVWFRQWDLQWKH
3&,H[SDQVLRQ520KHDGHU7KHVWDUWLQJSRLQWRIHDFKLPDJHGHSHQGVRQWKHVL]HRI
SUHYLRXVLPDJHV7KHODVWLPDJHLQD520KDVDVSHFLDOHQFRGLQJLQWKHKHDGHUWR
LGHQWLI\LWDVWKHODVWLPDJHImage 0

Image 1

Image N)LJXUH3&,([SDQVLRQ5206WUXFWXUH

6.3.1.1. PCI Expansion ROM Header Format
7KHLQIRUPDWLRQUHTXLUHGLQHDFK520LPDJHLVVSOLWLQWRWZRGLIIHUHQWDUHDV2QHDUHD
WKH520KHDGHULVUHTXLUHGWREHORFDWHGDWWKHEHJLQQLQJRIWKH520LPDJH7KH
VHFRQGDUHDWKH3&,'DWD6WUXFWXUHPXVWEHORFDWHGLQWKHILUVW.%RIWKHLPDJH
7KHIRUPDWIRUWKH3&,([SDQVLRQ520+HDGHULVJLYHQEHORZ7KHRIIVHWLVD
KH[DGHFLPDOQXPEHUIURPWKHEHJLQQLQJRIWKHLPDJHDQGWKHOHQJWKRIHDFKILHOGLV
JLYHQLQE\WHV([WHQVLRQVWRWKH3&,([SDQVLRQ520+HDGHUDQGRUWKH3&,'DWD6WUXFWXUHPD\EH
GHILQHGE\VSHFLILFV\VWHPDUFKLWHFWXUHV([WHQVLRQVIRU3&$7FRPSDWLEOHV\VWHPVDUH
GHVFULEHGLQ6HFWLRQ

206

Revision 2.2

Offset0h1h2h-17h18h-19h

Length
1
1
16h
2

Value
55h
AAh
xx
xx

Description
ROM Signature, byte 1
ROM Signature, byte 2
Reserved (processor architecture unique data)
Pointer to PCI Data Structure

ROM Signature

The ROM Signature is a two-byte field containing a 55h in
the first byte and AAh in the second byte. This signaturemust be the first two bytes of the ROM address space foreach image of the ROM.

Pointer to PCI Data
Structure

The Pointer to the PCI Data Structure is a two-byte pointer inlittle endian format that points to the PCI Data Structure. The
reference point for this pointer is the beginning of the ROM
image.

6.3.1.2. PCI Data Structure Format
7KH3&,'DWD6WUXFWXUHPXVWEHORFDWHGZLWKLQWKHILUVW.%RIWKH520LPDJHDQG
PXVWEH':25'DOLJQHG7KH3&,'DWD6WUXFWXUHFRQWDLQVWKHIROORZLQJLQIRUPDWLRQ
Offset
0
4
6
8
A
C
D
10
12
14
15
16

Length
4
2
2
2
2
1
3
2
2
1
1
2

Description
Signature, the string "PCIR"
Vendor Identification
Device Identification
Reserved
PCI Data Structure Length
PCI Data Structure Revision
Class CodeImage Length
Revision Level of Code/Data
Code Type
Indicator
Reserved

Signature

These four bytes provide a unique signature for the PCI Data
Structure. The string "PCIR" is the signature with "P" being
at offset 0, "C" at offset 1, etc.

Vendor Identification

The Vendor Identification field is a 16-bit field with the samedefinition as the Vendor Identification field in the
Configuration Space for this device.

Device Identification

The Device Identification field is a 16-bit field with the samedefinition as the Device Identification field in the
Configuration Space for this device.

207

Revision 2.2

Resvd

Reserved 16-bit field.
Note that in earlier versions of the PCI Local Bus
Specification this field pointed to ROM located Vital ProductData. This has been superseded by Vital Product Data as
described in Section 6.4.

PCI Data Structure
LengthThe PCI Data Structure Length is a 16-bit field that defines
the length of the data structure from the start of the data
structure (the first byte of the Signature field). This field is inlittle-endian format and is in units of bytes.

PCI Data Structure
Revision

The PCI Data Structure Revision field is an eight-bit field that
identifies the data structure revision level. This revision level
is 0.

Class Code

The Class Code field is a 24-bit field with the same fields anddefinition as the class code field in the Configuration Spacefor this device.

Image Length

The Image Length field is a two-byte field that represents thelength of the image. This field is in little-endian format, andthe value is in units of 512 bytes.

Revision Level

The Revision Level field is a two-byte field that contains therevision level of the code in the ROM image.

Code TypeThe Code Type field is a one-byte field that identifies thetype of code contained in this section of the ROM. The code
may be executable binary for a specific processor and systemarchitecture or interpretive code. The following code types
are assigned:

Indicator

7\SH'HVFULSWLRQ


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2SHQ)LUPZDUHVWDQGDUGIRU3&,
+HZOHWW3DFNDUG3$5,6&
5HVHUYHG

Bit 7 in this field tells whether or not this is the last image in
the ROM. A value of 1 indicates "last image;" a value of 0
indicates that another image follows. Bits 0-6 are reserved.

48 Open Firmware is a processor architecture and system architecture independent standard for dealing with

device specific option ROM code. Documentation for Open Firmware is available in the IEEE 1275-1994
Standard for Boot (Initialization, Configuration) Firmware Core Requirements and Practices. A related
document, PCI Bus Binding to IEEE 1275-1994, specifies the application of Open Firmware to the PCI
local bus, including PCI-specific requirements and practices. This document may be obtained using
anonymous FTP to the machine playground.sun.com with the filename/pub/p1275/bindings/postscript/PCI.ps.
208

Revision 2.2

6.3.2. Power-on Self Test (POST) Code
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WKHGHYLFH
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6.3.3. PC-compatible Expansion ROMs
7KLVVHFWLRQGHVFULEHVIXUWKHUUHTXLUHPHQWVRQ520LPDJHVDQGWKHKDQGOLQJRI520
LPDJHVWKDWDUHXVHGLQ3&FRPSDWLEOHV\VWHPV7KLVDSSOLHVWRDQ\LPDJHWKDWVSHFLILHV,QWHO[3&$7FRPSDWLEOHLQWKH&RGH7\SHILHOGRIWKH3&,'DWD6WUXFWXUHDQGDQ\
SODWIRUPWKDWLV3&FRPSDWLEOH

6.3.3.1. ROM Header Extensions
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FRPSDWLELOLW\7ZRILHOGVDUHDGGHGRQHDWRIIVHWKSURYLGHVWKHLQLWLDOL]DWLRQVL]HIRU
WKHLPDJH2IIVHWKLVWKHHQWU\SRLQWIRUWKHH[SDQVLRQ520,1,7IXQFWLRQ
Offset0h
1h
2h

Length
1
1
1

Value
55h
AAh
xx

3h

3

xx

6h-17h18h-19h

12h
2

xx
xx

Description
ROM Signature byte 1
ROM Signature byte 2
Initialization Size - size of the code in units of
512 bytes
Entry point for INIT function. POST does a
FAR CALL to this location.
Reserved (application unique data)
Pointer to PCI Data Structure

6.3.3.1.1. POST Code Extensions
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209

Revision 2.2

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6.3.3.1.2. INIT Function Extensions
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210

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211

Revision 2.2

6.4. Vital Product Data
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212

Revision 2.2

6.6. System Reset$IWHUV\VWHPUHVHWWKHSURFHVVRU V PXVWEHDEOHWRDFFHVVERRWFRGHDQGDQ\GHYLFHV
QHFHVVDU\WRERRWWKHPDFKLQH'HSHQGLQJRQWKHV\VWHPDUFKLWHFWXUHEULGJHVPD\QHHG
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6.7. Capabilities List
&HUWDLQFDSDELOLWLHVDGGHGWR3&,DIWHUWKHSXEOLFDWLRQRIUHYLVLRQDUHVXSSRUWHGE\
DGGLQJDVHWRIUHJLVWHUVWRDOLQNHGOLVWFDOOHGWKH&DSDELOLWLHV/LVW7KLVRSWLRQDOGDWD
VWUXFWXUHLVLQGLFDWHGLQWKH3&,6WDWXV5HJLVWHUE\VHWWLQJWKH&DSDELOLWLHV/LVWELW ELWWRLQGLFDWHWKDWWKH&DSDELOLWLHV3RLQWHULVORFDWHGDWRIIVHWK7KLVUHJLVWHUSRLQWVWR
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KDQGOHGPXFKOLNHWKH&ODVV&RGHV5HIHUWR$SSHQGL[+IRUDOLVWRIFXUUHQWO\GHILQHG&DSDELOLWLHV(DFK&DSDELOLW\PXVWGHILQHWKHGHWDLOHGUHJLVWHUPDSIRUWKDWFDSDELOLW\
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Revision 2.2

6.8. Message Signaled Interrupts
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6.8.1. Message Capability Structure
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214

Revision 2.2

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6.8.1.1. Capability ID
7::0

CAP_IDThe value of 05h in this field identifies the function as
message signaled interrupt capable. This field isread only.

6.8.1.2. Next Pointer
7::0

NXT_PTR

Pointer to the next item in the capabilities list. Must
be NULL for the final item in the list. This field is readonly.

6.8.1.3. Message Control
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ILHOGV
Bits

Field

15::08Reserved

7

64 bit addresscapableDescription
Always returns 0 on a read and a write operation has
no effect.
If 1, the function is capable of generating a 64-bit
message address.
If 0, the function is not capable of generating a 64-bit
message address.
This bit is read only.

215

Revision 2.2

Bits
6::4

Field
Multiple Message
EnableDescription
System software writes to this field to indicate thenumber of allocated messages (equal to or less than
the number of requested messages). The number of
allocated messages is aligned to a power of two. If afunction requests four messages (indicated by aMultiple Message Capable encoding of “010”), system
software can allocate either four, two, or one
message by writing a “010”, “001, or “000” to thisfield, respectively. When MSI is enabled, a device willbe allocated at least 1 message. The encoding isdefined as:
Encoding# of messages allocated

000

1

001

2

010

4

011

8

100

16

101

32

110

Reserved

111

Reserved

This field’s state after reset is “000”.
This field is read/write.
3::1

Multiple Message
CapableSystem software reads this field to determine thenumber of requested messages. The number ofrequested messages must be aligned to a power oftwo (if a function requires three messages, it requests
four by initializing this field to “010”). The encoding isdefined as:
Encoding
000

1

001

2

010

4

011

8

100

16

101

32

110

Reserved

111

Reserved

This field is read/only.

216# of messages requested

Revision 2.2

Bits
0

Field
MSI Enable

Description
If 1, the function is permitted to use MSI to request
service and is prohibited from using its INTx# pin (ifimplemented). System configuration software sets
this bit to enable MSI. A device driver is prohibitedfrom writing this bit to mask a function’s service
request.
If 0, the function is prohibited from using MSI torequest service.
This bit’s state after reset is 0 (MSI is disabled).
This bit is read/write.

6.8.1.4. Message Address
Bits

Field

31::02Message
Address

Description
System-specified message address.
If the Message Enable bit (bit 0 of the Message
Control register) is set, the contents of this register
specify the DWORD aligned address (AD[31::02]) for
the MSI memory write transaction. AD[1::0] aredriven to zero during the address phase.
This field is read/write.

01::00Reserved

Always returns 0 on read. Write operations have noeffect.

6.8.1.5. Message Upper Address (Optional)
Bits
31::00

Field
Message Upper
Address

Description
System-specified message upper address.
This register is optional and is implemented only if thedevice supports a 64-bit message address (bit 7 in
Message Control register set)49. If the Message
Enable bit (bit 0 of the Message Control register) isset, the contents of this register (if non-zero) specify
the upper 32-bits of a 64-bit message address(AD[63::32]). If the contents of this register are zero,the device uses the 32 bit address specified by themessage address register.
This field is read/write.

49 This register is required when the device supports 64-bit addressing (DAC) when acting as a master.

217

Revision 2.2

6.8.1.6. Message Data
Bits

Field

Description

15::00

Message Data

System-specified message.
Each MSI function is allocated up to 32 uniquemessages.
System architecture specifies the number of uniquemessages supported by the system.
If the Message Enable bit (bit 0 of the Message
Control register) is set, the message data is driven
onto the lower word (AD[15::00]) of the memory write
transaction’s data phase. AD[31::16] are driven tozero during the memory write transaction’s dataphase. C/BE[3::0]# are asserted during the dataphase of the memory write transaction.
The Multiple Message Enable field (bits 6-4 of the
Message Control register) defines the number of loworder message data bits the function is permitted tomodify to generate its system software allocatedmessages. For example, a Multiple Message Enableencoding of “010” indicates the function has been
allocated four messages and is permitted to modify
message data bits 1 and 0 (a function modifies thelower message data bits to generate the allocatednumber of messages). If the Multiple Message
Enable field is “000”, the function is not permitted tomodify the message data.
This field is read/write.

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218

Revision 2.2

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219

Revision 2.2

6.8.2.1. MSI Transaction Termination
7KHWDUJHWRIDQ06,FDQQRWGLVWLQJXLVKEHWZHHQDQ06,ZULWHWUDQVDFWLRQDQGDQ\RWKHU
PHPRU\ZULWHWUDQVDFWLRQ7KHWHUPLQDWLRQUHTXLUHPHQWVIRUDQ06,DUHWKHVDPHDVIRU
DQ\RWKHUPHPRU\ZULWHWUDQVDFWLRQH[FHSWDVQRWHGEHORZ
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PDVWHUWKDWRULJLQDWHGWKH06,ZULWHWUDQVDFWLRQLVUHTXLUHGWRUHSRUWWKHHUURUE\
DVVHUWLQJSERR# LIELWLQWKH&RPPDQGUHJLVWHULVVHW DQGWRVHWWKHDSSURSULDWHELWV
LQWKH6WDWXVUHJLVWHU UHIHUWR6HFWLRQ 7KH06,ZULWHWUDQVDFWLRQLVLJQRUHGE\
WKHWDUJHWLILWLVWHUPLQDWHGZLWKD0DVWHU$ERUWRU7DUJHW$ERUWIf the MSI write transaction results in a data parity error, the master that originated the
MSI write transaction is required to assert SERR# (if bit 8 in the Command register isset) and to set the appropriated bits in the Status register (refer to Section 3.7.4.).

6.8.2.2. MSI Transaction Reception and Ordering Requirements$VZLWKDOOPHPRU\ZULWHWUDQVDFWLRQVWKHGHYLFHWKDWLQFOXGHVWKHWDUJHWRIWKHLQWHUUXSWPHVVDJH WKHLQWHUUXSWUHFHLYHU LVUHTXLUHGWRFRPSOHWHDOOLQWHUUXSWPHVVDJHWUDQVDFWLRQV
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VHQGWKHVHFRQGLQWHUUXSWPHVVDJHXQWLOWKHILUVWRQHKDVEHHQVHUYLFHG

220

Revision 2.2

Chapter 7
66 MHz PCI Specification

7.1. Introduction
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ODWHQF\KLJKEDQGZLGWKEULGJHVDQGSHULSKHUDOV6\VWHPVPD\DXJPHQWWKH0+]
3&,EXVZLWKDVHSDUDWH0+]3&,EXVWRKDQGOHORZHUVSHHGSHULSKHUDOV'LIIHUHQFHVEHWZHHQ0+]3&,DQG0+]3&,DUHPLQLPDO%RWKVKDUHWKHVDPH
SURWRFROVLJQDOGHILQLWLRQVDQGFRQQHFWRUOD\RXW7RLGHQWLI\0+]3&,GHYLFHVRQH
VWDWLFVLJQDOLVDGGHGE\UHGHILQLQJDQH[LVWLQJJURXQGSLQDQGRQHELWLVDGGHGWRWKH&RQILJXUDWLRQ6WDWXVUHJLVWHU%XVGULYHUVIRUWKH0+]3&,EXVPHHWWKHVDPH'&FKDUDFWHULVWLFVDQG$&GULYHSRLQWOLPLWVDV0+]3&,EXVGULYHUVKRZHYHU0+]
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UHVXOW0+]3&,EXVHVPD\VXSSRUWVPDOOHUORDGLQJDQGWUDFHOHQJWKV$0+]3&,GHYLFHRSHUDWHVDVD0+]3&,GHYLFHZKHQLWLVFRQQHFWHGWRD
0+]3&,EXV6LPLODUO\LIDQ\0+]3&,GHYLFHVDUHFRQQHFWHGWRD0+]3&,
EXVWKH0+]3&,EXVZLOORSHUDWHDVD0+]3&,EXV
7KHSURJUDPPLQJPRGHOVIRU0+]3&,DQG0+]3&,DUHWKHVDPHLQFOXGLQJFRQILJXUDWLRQKHDGHUVDQGFODVVW\SHV$JHQWVDQGEULGJHVLQFOXGHD0+]3&,VWDWXV
ELW

7.2. 6FRSH
7KLVFKDSWHUGHILQHVDVSHFWVRI0+]3&,WKDWGLIIHUIURPWKRVHGHILQHGHOVHZKHUHLQWKLVGRFXPHQWLQFOXGLQJLQIRUPDWLRQRQGHYLFHDQGEULGJHVXSSRUW7KLVFKDSWHUZLOOQRWUHSHDWLQIRUPDWLRQGHILQHGHOVHZKHUH

221

Revision 2.2

7.3. Device Implementation Considerations
7.3.1. Configuration Space,GHQWLILFDWLRQRID0+]3&,FRPSOLDQWGHYLFHLVDFFRPSOLVKHGWKURXJKWKHXVHRIWKH
UHDGRQO\0+=B&$3$%/(IODJORFDWHGLQELWRIWKH3&,6WDWXVUHJLVWHU VHH)LJXUH ,IVHWWKLVELWVLJQLILHVWKDWWKHGHYLFHLVFDSDEOHRIRSHUDWLQJLQ0+]
PRGH

7.4. Agent Architecture$0+]3&,DJHQWLVGHILQHGDVD3&,DJHQWFDSDEOHRIVXSSRUWLQJ0+]3&,
$OO0+]3&,DJHQWVPXVWVXSSRUWDUHDGRQO\0+=B&$3$%/(IODJORFDWHGLQ
ELWRIWKH3&,6WDWXVUHJLVWHUIRUWKDWDJHQW,IVHWWKH0+=B&$3$%/(ELWVLJQLILHVWKDWWKHDJHQWFDQRSHUDWHLQ0+]3&,PRGH

7.5. Protocol
7.5.1. 66MHZ_ENABLE (M66EN) Pin Definition
3LQ%RQWKH3&,FRQQHFWRULVGHVLJQDWHGM66EN([SDQVLRQERDUGVDQGEXV
VHJPHQWVQRWFDSDEOHRIRSHUDWLRQLQ0+]PRGHPXVWFRQQHFWWKLVSLQWRJURXQG$
0+]3&,SODQDUVHJPHQWPXVWSURYLGHDVLQJOHSXOOXSUHVLVWRUWR9FFRQWKHM66EN
SLQ5HIHUWR6HFWLRQIRUWKHDSSURSULDWHSXOOXSYDOXHM66ENLVEXVHGWRDOO0+]3&,FRQQHFWRUVDQGSODQDURQO\0+]3&,FRPSRQHQWVWKDWLQFOXGHWKHM66EN
SLQ7KH0+]3&,FORFNJHQHUDWLRQFLUFXLWU\PXVWFRQQHFWWRM66ENWRJHQHUDWHWKH
DSSURSULDWHFORFNIRUWKHVHJPHQW WR0+]LIM66ENLVDVVHUWHGWR0+]LI
M66ENLVGHDVVHUWHG ,ID0+]3&,DJHQWUHTXLUHVFORFNVSHHGLQIRUPDWLRQ IRUH[DPSOHIRUD3//E\SDVV 
LWLVSHUPLWWHGWRXVHM66ENDVDQLQSXW,ID0+]3&,DJHQWFDQUXQZLWKRXWDQ\NQRZOHGJHRIWKHVSHHGLWLVSHUPLWWHGWROHDYHM66ENGLVFRQQHFWHG

50 Configuration software identifies agent capabilities by checking the 66MHZ_CAPABLE bit in the Status

register. This includes both the primary and secondary Status registers in a PCI-to-PCI bridge. This allows
configuration software to detect a 33 MHz PCI agent on a 66 MHz PCI bus or a 66 MHz PCI agent on a
33 MHz PCI bus and issue a warning to the user describing the situation.
222

Revision 2.2

7DEOH%XVDQG$JHQW&RPELQDWLRQVBus
66MHZ_CAPABLE51

Agent
66MHZ_CAPABLE

00

33 MHz PCI agent located on a
33 MHz PCI bus

01

66 MHz PCI agent located on a
33 MHz PCI bus52

1

0

33 MHz PCI agent located on a
66 MHz PCI bus52

1

1

66 MHz PCI agent located on a
66 MHz PCI bus

Description

7.5.2. Latency
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LQLWLDOODWHQF\QRWH[FHHGFORFNV

7.6. Electrical Specification
7.6.1. Overview
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H[FHSWZKHUHH[SOLFLWO\VXSHUVHGHG6SHFLILFDOO\•

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•7LPLQJSDUDPHWHUVKDYHEHHQVFDOHGWR0+]

•$&WHVWORDGLQJFRQGLWLRQVKDYHEHHQFKDQJHG

51 The bus 66MHZ_CAPABLE status bit is located in a bridge’s Status registers.
52 This condition may cause the configuration software to generate a warning to the user stating that thecard is installed in an inappropriate socket and should be relocated.
223

Revision 2.2

7.6.2. Transition Roadmap to 66 MHz PCI
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Tcyc ≥ Tval + Tprop + Tskew + Tsu
Tcyc = 30 ns

33 MHZ

Tval =11 ns

Tprop = 10 ns

Tskew = 2ns

Tsu=7ns

Tcyc = 15 ns

66 MHZ

Tval
6 ns

Tprop
5 ns

Tskew
1 ns

Tsu
3 ns

)LJXUH0+]3&,YV0+]3&,7LPLQJ

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7.6.3. Signaling Environment$0+]3&,SODQDUVHJPHQWPXVWXVHWKH3&,9NH\HGFRQQHFWRU7KHUHIRUH
0+]3&,SODQDUVHJPHQWVDFFHSWHLWKHU9RU8QLYHUVDOH[SDQVLRQERDUGV9
H[SDQVLRQERDUGVDUHQRWVXSSRUWHG
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VOHZUDWH7KHPLQLPXP$&GULYHSRLQWGHILQHVDQDFFHSWDEOHILUVWVWHSYROWDJHDQG
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VSHFLILFDWLRQSURYLGHVDPRUHFRQFLVHGHILQLWLRQIRUWKHRXWSXWEXIIHU

224

Revision 2.2

7.6.3.1. DC Specifications
5HIHUWR6HFWLRQ

7.6.3.2. AC Specifications
7DEOH$&6SHFLILFDWLRQV
SymbolParameter

Condition

Min

Max

Units Notes

AC Drive Points
Ioh(AC,min)

Switching Current
High, minimum

Vout = 0.3Vcc-12Vcc-mA

Ioh(AC,max)

Switching Current
High, maximum

Vout = 0.7Vcc--32VccmA

Iol(AC,min)

Switching Current
Low, minimum

Vout = 0.6Vcc

16Vcc

-

mA

Iol(AC,max)

Switching
Current Low,
maximum

Vout = 0.18Vcc

-

38Vcc

mA

1

1

DC Drive Points
VOH

Output highvoltage

Iout = -0.5 mA

0.9Vcc

-

V

2

VOL

Output low
voltage

Iout = 1.5 mA-

0.1VccV

2

tr

Output rise slew
rate

0.3Vcc to 0.6Vcc

1

4

V/ns

3

tf

Output fall slew
rate

0.6Vcc to 0.3Vcc

1

4

V/ns

3

Ich

High clamp
current

Vcc + 4 > Vin ≥ Vcc + 1

25 + (Vin - Vcc - 1) / 0.015

-

mA

Icl

Low clamp
current-3 < Vin ≤ -1

-25 + (Vin + 1) / 0.015-

mA

Slew Rate

Clamp Current

NOTES:
1. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half
size drivers may be used on these signals. This specification does not apply to CLK and RST# which are system
outputs. "Switching Current High" specifications are not relevant to SERR#, PME#, INTA#, INTB#, INTC#, and
INTD# which are open drain outputs.
2. These DC values are duplicated from Section 4.2.2.1. and are included here for completeness.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range rather than the
instantaneous rate at any point within the transition range. The specified load (see Figure 7-7) is optional. The
designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus
Specification. However, adherence to both maximum and minimum parameters is required (the maximum is not
simply a guideline). Rise slew rate does not apply to open drain outputs.

225

Revision 2.2

7.6.3.3. Maximum AC Ratings and Device Protection
5HIHUWR6HFWLRQ

7.6.4. Timing Specification
7.6.4.1. Clock Specification
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T_cyc
T_high

3.3 volt Clock

0.6 Vcc

T_low

0.5 Vcc
0.4 Vcc, p-to-p(minimum)

0.4 Vcc
0.3 Vcc
0.2 Vcc)LJXUH9&ORFN:DYHIRUP

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7DEOH

226

Revision 2.2

7DEOH&ORFN6SHFLILFDWLRQV
33 MHz4

66 MHzSymbolParameter

Min

Max

Min

Max

Units

Notes

Tcyc

CLK Cycle Time

15

30

30

∞

ns

1,3

Thigh

CLK High Time

6

11

ns

Tlow

CLK Low Time

6

11

ns

-

CLK Slew Rate

1.5

4

1

4

V/ns

-

-

kHz

2

Spread Spectrum Requirements
fmod

modulation
frequency

30

33

fspreadfrequency
spread-1

9%

NOTES:
1. In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK
requirements vary depending upon whether the clock frequency is above 33 MHz.
a.

Device operational parameters at frequencies at or under 33 MHz will conform to the specifications in
Chapter 4. The clock frequency may be changed at any time during the operation of the system solong as the clock edges remain "clean" (monotonic) and the minimum cycle and high and low times
are not violated. The clock may only be stopped in a low state. A variance on this specification isallowed for components designed for use on the system planar only. Refer to Section 4.2.3.1. formore information.

b.

For clock frequencies between 33 MHz and 66 MHz, the clock frequency may not change except
while RST# is asserted or when spread spectrum clocking (SSC) is used to reduce EMI emissions.

2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met
across the minimum peak-to-peak portion of the clock waveform as shown in Figure 7-2. Clock slew rateis measured by the slew rate circuit shown in Figure 7-7.
3. The minimum clock period must not be violated for any single clock cycle; i.e., accounting for all systemjitter.
4. These values are duplicated from Section 4.2.3.1. and included here for comparison.

Implementation Note: Spread Spectrum Clocking (SSC)
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DQGQHYHUWRLQFUHDVHLW:KHQ3//VDUHXVHGWRWUDFNCLKWKH\QHHGWRWUDFNWKH66&
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Revision 2.2

7.6.4.2. Timing Parameters
7DEOH0+]DQG0+]7LPLQJ3DUDPHWHUV33 MHz7

66 MHzSymbolParameter

Min

Max

Min

Max

Units

Notes

Tval

CLK to Signal Valid Delay bused signals

2

6

2

11

ns

1, 2,
3, 8

Tval(ptp) CLK to Signal Valid Delay point to point signals

2

6

2

12

ns

1, 2,
3, 8

ns

1, 8, 9

ns

1, 9

Ton

Float to Active Delay

2

2

Toff

Active to Float Delay

Tsu

Input Setup Time to CLK bused signals

3

7

ns

3, 4,
10

Tsu(ptp) Input Setup Time to CLK point to point signals

5

10,12

ns

3, 4

14

28

Th

Input Hold Time from CLK

0

0

ns

4

Trst

Reset Active Time after
power stable

1

1

ms

5

Trst-clk

Reset Active Time after CLK
stable

100

100

µs

5

Trst-off

Reset Active to output float
delay

ns

5, 6

trrsu

REQ64# to RST# setup time

10Tcyctrrh

RST# to REQ64# hold time

0

Trhfa

RST# high to first
Configuration access

2

25

2

25

clocks

Trhff

RST# high to first FRAME#
assertion

5

5

clocks40

40

10Tcyc
50

0

ns
50

ns

NOTES:
1.

See the timing measurement conditions in Figure 7-3. It is important that all driven signal transitions drive to their
Voh or Vol level within one Tcyc.

2.

Minimum times are measured at the package pin with the load circuit shown in Figure 7-7. Maximum times aremeasured with the load circuit shown in Figures 7-5 and 7-6.

3.

REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT#
and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused.

4.

See the timing measurement conditions in Figure 7-4.

5.

If M66EN is asserted, CLK is stable when it meets the requirements in Section 7.6.4.1. RST# is asserted anddeasserted asynchronously with respect to CLK. Refer to Section 4.3.2. for more information.

6.

All output drivers must be floated when RST# is active. Refer to Section 4.3.2. for more information.

7.

These values are duplicated from Section 4.2.3.2. and are included here for comparison.

8.

When M66EN is asserted, the minimum specification for T val(min), Tval(ptp)(min), and Ton may be reduced to
1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when M66EN is deasserted.

228

Revision 2.2
9.

For purposes of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.

10. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at thesame time. Refer to Section 3.10., item 9 for additional details.

7.6.4.3. Measurement and Test Conditions
V_th

CLK

V_test
V_tl
T_val

OUTPUT
DELAY

V_tfall
T_val

OUTPUT
DELAY

V_trise

Tri-State
OUTPUT
T_on

T_off)LJXUH2XWSXW7LPLQJ0HDVXUHPHQW&RQGLWLRQV

V_th

CLK

V_test
V_tl
T_su

T_h

V_th

INPUT

V_testinputsvalid

V_test

V_max

V_tl

)LJXUH,QSXW7LPLQJ0HDVXUHPHQW&RQGLWLRQV

229

Revision 2.2

7DEOH0HDVXUHPHQW&RQGLWLRQ3DUDPHWHUVSymbolVth

3.3V Signaling
0.6Vcc

V

Units
1

Notes

Vtl

0.2Vcc

V

1

Vtest

0.4VccV

Vtrise0.285Vcc

V

2

Vtfall

0.615Vcc

V

2

Vmax

0.4VccV

1

Input Signal
Slew Rate

1.5

V/ns

3

NOTES:
1.

The test for the 3.3V environment is done with 0.1*V cc of overdrive.
Vmax specifies the maximum peak-to-peak waveform allowed formeasuring input timing. Production testing may use different voltage
values but must correlate results back to these parameters.

2.

Vtrise and Vtfall are reference voltages for timing measurements only.
Developers of 66 MHz PCI systems need to design buffers that launchenough energy into a 25 Ω transmission line so that correct input
levels are guaranteed after the first reflection.

3.

Outputs will be characterized and measured at the package pin withthe load shown in Figure 7-7. Input signal slew rate will be measured
between 0.3Vcc and 0.6Vcc.

pin

1/2 in. max.

outputbuffer
10 pF

25 Ω)LJXUH7YDO PD[ 5LVLQJ(GJH

1/2 in. max.

Vcc
25 Ω
10 pF

)LJXUH7YDO PD[ )DOOLQJ(GJH

230

Revision 2.2
pin

1/2 in. max.

outputbuffer

Vcc
1K Ω

10 pF

1K Ω

)LJXUH7YDO PLQ DQG6OHZ5DWH

7.6.5. Vendor Provided Specification
5HIHUWR6HFWLRQ

7.6.6. Recommendations
7.6.6.1. Pinout Recommendations
5HIHUWR6HFWLRQ
7KH0+]3&,HOHFWULFDOVSHFLILFDWLRQDQGSK\VLFDOUHTXLUHPHQWVPXVWEHPHWKRZHYHUWKHGHVLJQHULVSHUPLWWHGWRPRGLI\WKHVXJJHVWHGSLQRXWVKRZQLQ)LJXUHDV
UHTXLUHG

7.6.6.2. Clocking Recommendations
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5RXWLQJWKH0+]3&,FORFNDVDSRLQWWRSRLQWVLJQDOIURPLQGLYLGXDOORZVNHZFORFNGULYHUVWRERWKSODQDUDQGH[SDQVLRQERDUGFRPSRQHQWVZLOOJUHDWO\UHGXFHVLJQDOUHIOHFWLRQHIIHFWVDQGRSWLPL]HFORFNVLJQDOLQWHJULW\7KLVLQDGGLWLRQWRREVHUYLQJWKH
SK\VLFDOUHTXLUHPHQWVRXWOLQHGLQ6HFWLRQZLOOPLQLPL]HFORFNVNHZ'HYHORSHUVPXVWSD\FDUHIXODWWHQWLRQWRWKHFORFNWUDFHOHQJWKOLPLWVVWDWHGLQ
6HFWLRQDQGWKHYHORFLW\OLPLWVLQ6HFWLRQ)LJXUHLOOXVWUDWHVWKH
UHFRPPHQGHGPHWKRGIRUURXWLQJWKH0+]3&,FORFNVLJQDO

231

Revision 2.2

Clock Source

Add-in Board
66 MHzDevice A

PCI Add-in
Connector
66 MHzDevice B

66 MHzDevice C)LJXUH5HFRPPHQGHG&ORFN5RXWLQJ

7.7. System (Planar) Specification
7.7.1. Clock Uncertainty
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VZLWFKLQJUDQJHGHILQHGLQ7DEOHDQG)LJXUH7KHPD[LPXPVNHZLVPHDVXUHG
EHWZHHQDQ\WZRFRPSRQHQWVQRWEHWZHHQFRQQHFWRUV7RFRUUHFWO\HYDOXDWHFORFN
VNHZWKHV\VWHPGHVLJQHUPXVWWDNHLQWRDFFRXQWFORFNGLVWULEXWLRQRQWKHH[SDQVLRQERDUGDVVSHFLILHGLQ6HFWLRQ'HYHORSHUVPXVWSD\FDUHIXODWWHQWLRQWRWKHFORFNWUDFHOHQJWKOLPLWVVWDWHGLQ
6HFWLRQDQGWKHYHORFLW\OLPLWVLQ6HFWLRQ
7DEOH&ORFN6NHZ3DUDPHWHUVSymbol66 MHz 3.3V Signaling

33 MHz 3.3V Signaling

Units

Vtest

0.4Vcc0.4VccVTskew

1 (max)2 (max)

ns

53 The system designer must address an additional source of clock skew. This clock skew occurs between

two components that have clock input trip points at opposite ends of the Vil - Vih range. In certain
circumstances, this can add to the clock skew measurement as described here. In all cases, total clock skew
must be limited to the specified number.
232

Revision 2.2

V_ih
CLK
(@Device #1)

V_testV_il

T_skew
T_skew
T_skew
V_ih

CLK(@Device #2)

V_test
V_il)LJXUH&ORFN6NHZ'LDJUDP

7.7.2. Reset
5HIHUWR6HFWLRQ

7.7.3. Pullups
7KH0+]3&,EXVUHTXLUHVDVLQJOHSXOOXSUHVLVWRUVXSSOLHGE\WKHSODQDURQWKH
M66ENSLQ5HIHUWR6HFWLRQIRUWKHUHVLVWRUYDOXH

7.7.4. Power
7.7.4.1. Power Requirements
5HIHUWR6HFWLRQ

7.7.4.2. Sequencing
5HIHUWR6HFWLRQ

7.7.4.3. Decoupling
5HIHUWR6HFWLRQ

7.7.5. System Timing Budget:KHQFRPSXWLQJDWRWDO0+]3&,ORDGPRGHOGHVLJQHUVPXVWSD\FDUHIXODWWHQWLRQWR
PD[LPXPWUDFHOHQJWKDQGORDGLQJRIH[SDQVLRQERDUGV5HIHUWR6HFWLRQ$OVR
WKHPD[LPXPSLQFDSDFLWDQFHRIS)PXVWEHDVVXPHGIRUH[SDQVLRQERDUGVZKHUHDVWKHDFWXDOSLQFDSDFLWDQFHPD\EHXVHGIRUSODQDUGHYLFHV
7KHWRWDOFORFNSHULRGFDQEHGLYLGHGLQWRIRXUVHJPHQWV9DOLGRXWSXWGHOD\ 7YDO DQG
LQSXWVHWXSWLPHV 7VX DUHVSHFLILHGE\WKHFRPSRQHQWVSHFLILFDWLRQ7RWDOFORFNVNHZ
7VNHZ DQGEXVSURSDJDWLRQWLPHV 7SURS DUHV\VWHPSDUDPHWHUV7SURSLVDV\VWHP
SDUDPHWHUWKDWLVLQGLUHFWO\VSHFLILHGE\VXEWUDFWLQJWKHRWKHUWLPLQJEXGJHWFRPSRQHQWVIURPWKHF\FOHWLPH7DEOHOLVWVWLPLQJEXGJHWVIRUVHYHUDOEXVIUHTXHQFLHV
233

Revision 2.2

7SURSLVPHDVXUHGDVVKRZQLQ)LJXUH,WEHJLQVDWWKHWLPHWKHVLJQDODWWKHRXWSXWEXIIHUZRXOGKDYHFURVVHGWKHWKUHVKROGSRLQW 9WULVHRU9WIDOO KDGWKHRXWSXWEHHQ
GULYLQJWKHVSHFLILHG7YDO PD[ ORDG7KHHQGRI7SURSIRUDQ\SDUWLFXODULQSXWLV
GHWHUPLQHGE\RQHRIWKHIROORZLQJWZRPHDVXUHPHQWPHWKRGV7KHPHWKRGWKDW
SURGXFHVWKHORQJHUYDOXHIRU7SURSPXVWEHXVHG
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ODVWWLPH 6HH)LJXUHDG
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EFHI

Implementation Note: Determining the End of Tprop
7KHHQGRI7SURSLVDOZD\VGHWHUPLQHGE\WKHFDOFXODWLRQPHWKRGWKDWSURGXFHVWKH
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:KHQWKHVLJQDOULVHVRUIDOOVIURP9WHVWWRWKHODVWFURVVLQJRU9LK KLJKJRLQJ RU9LO
ORZJRLQJ IDVWHUWKDQWKH,QSXW6LJQDO6OHZ5DWHVKRZQLQ7DEOH0HWKRGZLOOSURGXFHWKHORQJHUYDOXH 6HH)LJXUHDG:KHQWKHVLJQDOULVHVRUIDOOVIURP9WHVWWRWKHODVWFURVVLQJRU9LK KLJKJRLQJ RU9LO
ORZJRLQJ VORZHUWKDQWKH,QSXW6LJQDO6OHZ5DWH0HWKRGZLOOSURGXFHWKHORQJHUYDOXH,QRWKHUZRUGVLIWKHVLJQDOSODWHDXVRUULVHV KLJKJRLQJ RUIDOOV ORZJRLQJVORZO\DIWHUFURVVLQJ9WHVWRUULQJVEDFNDFURVV9LK KLJKJRLQJ RU9LO ORZJRLQJ
VLJQLILFDQWO\DIWHUFURVVLQJ9WHVW0HWKRGZLOOSURGXFHWKHORQJHUYDOXH
6HH)LJXUHEFHI
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YDOXHRI7SURSLVZKHQWKHVLJQDOVHWWOHVDWDOORWKHUGHYLFHVRQWKHEXV7KHYDOXHRI
7SURSLVQRWDIIHFWHGE\WKHWLPHWKHVLJQDOVHWWOHVDWWKHGULYHURXWSXWVLQFHGHYLFHVDUH
QRWSHUPLWWHGWRGULYHDQGUHFHLYHDVLJQDODWWKHVDPHWLPH5HIHUWR6HFWLRQ
LWHPIRUDGGLWLRQDOGHWDLOV

234

Revision 2.2
0.7Vcc

0.7Vcc
0.6Vcc0.5Vcc0.4VccVthDriving Bus
0.6VccVih

0.5VccVtest

0.4VccInput Signal
Slew Rate

Vth
VihDrivingBus

Vtest

0.3Vcc Vtrise

0.3Vcc Vtrise
0.2VccDriving
Test Load

Tprop

0.2VccTprop

0.1Vcc0.1Vcc

0

0

(a)

(b)
0.9Vcc0.9V cc
0.8V cc

Input Signal
Slew Rate

0.7V cc
0.6V cc
0.5V cc
0.4V cc
0.3V cc

Driving
Test Load

VthDriving
Bus

0.8VccTprop
0.7Vcc
0.6VccVih

VtfallDriving
Test Load

0.5VccVtest

0.4VccVtest

0.3Vcc Vil

VtriseDriving
Test Load

0.2V cc

0.2VccDriving Bus

Vtl

Tprop
0.1Vcc0.1V cc

0

0

(d)

(c)
0.9Vcc

0.9Vcc0.8Vcc0.8Vcc

Tprop

Tprop
0.7Vcc

0.7VccVtfallDriving
Test Load

0.5Vcc0.4Vcc0.3Vcc0.2VccVtfall

0.6Vcc

0.6VccVtest

0.5Vcc0.4VccInput Signal
Slew Rate

Vil

Driving Bus

Vtl

Driving
Test Load

0.3Vcc0.2VccVtest

Vtl

0.1Vcc0.1VccInput Signal
Slew Rate

Vil

Driving Bus

0

0

(e)

(f)

)LJXUH0HDVXUHPHQWRI7SURSUHIHUWR7DEOHIRUSDUDPHWHUYDOXHV

235

Revision 2.2

7KHUHOHYDQWWLPLQJEXGJHWFDQEHH[SUHVVHGE\WKHHTXDWLRQ
7F\F≥7YDO7SURS7VX7VNHZ
7KHIROORZLQJWDEOHFRPSDUHV3&,WLPLQJEXGJHWVDWYDULRXVVSHHGV
7DEOH7LPLQJ%XGJHWVTiming Element

33 MHz66 MHz50 MHz1

Units

Tcyc

30

15

20

ns

Tval

11

6

6

ns

Tprop

10

5

10

ns

Tsu

7

3

3

ns

Tskew

2

1

1

ns

Notes

2

3

NOTES:
1.

The 50 MHz example is shown for example purposes only.

2.

These times are computed. The other times are fixed. Thus, slowing down the bus clock enables thesystem manufacturer to gain additional distance or add additional loads. The component specifications
are required to guarantee operation at 66 MHz.

3

Clock skew specified here includes all sources of skew. If spread spectrum clocking (SSC) is used on thesystem board, the maximum clock skew at the input of the device on an expansion board includes SSC
tracking skew.

7.7.6. Physical Requirements
7.7.6.1. Routing and Layout Recommendations for Four-Layer
Boards5HIHUWR6HFWLRQ

7.7.6.2. Planar Impedance
5HIHUWR6HFWLRQ7LPLQJQXPEHUVDUHFKDQJHGDFFRUGLQJWRWKHWDEOHVLQWKLVFKDSWHU

7.7.7. Connector Pin Assignments
7KHM66ENSLQ SLQ% LVWKHRQO\FRQQHFWRUGLIIHUHQFHEHWZHHQEXVVHJPHQWV
FDSDEOHRI0+]RSHUDWLRQDQGWKRVHOLPLWHGWR0+]5HIHUWR6HFWLRQIRU
SODQDUFRQQHFWRUV7KLVSLQLVDQRUPDOJURXQGSLQLQLPSOHPHQWDWLRQVWKDWDUHQRWFDSDEOHRI0+]RSHUDWLRQ

236

Revision 2.2,QLPSOHPHQWDWLRQVWKDWDUH0+]FDSDEOHWKHM66ENSLQLVEXVHGEHWZHHQDOO
FRQQHFWRUVZLWKLQWKHVLQJOHORJLFDOEXVVHJPHQWWKDWLV0+]FDSDEOHDQGWKLVQHW
LVSXOOHGXSZLWKD.ΩUHVLVWRUWR9FF$OVRWKLVQHWLVFRQQHFWHGWRWKHM66ENLQSXWSLQRIFRPSRQHQWVORFDWHGRQWKHVDPHORJLFDOEXVVHJPHQWRIWKHV\VWHPSODQDU7KLV
VLJQDOLVVWDWLFWKHUHLVQRVWXEOHQJWKUHVWULFWLRQ
7RFRPSOHWHDQ$&UHWXUQSDWKDµ)FDSDFLWRUPXVWEHORFDWHGZLWKLQLQFKHVRIWKHM66ENSLQRIHDFKVXFKH[SDQVLRQERDUGFRQQHFWRUDQGPXVWGHFRXSOHWKH
M66ENVLJQDOWRJURXQG$Q\DWWDFKHGFRPSRQHQWRULQVWDOOHGH[SDQVLRQERDUGWKDWLV
QRW0+]FDSDEOHPXVWSXOOWKHM66ENQHWWRWKH9LOLQSXWOHYHO7KHUHPDLQLQJFRPSRQHQWVH[SDQVLRQERDUGVDQGWKHORJLFDOEXVVHJPHQWFORFNUHVRXUFHDUHWKHUHE\VLJQDOHGWRRSHUDWHLQ0+]PRGH

7.8. Expansion Board Specifications
7KHM66ENSLQ SLQ% LVWKHRQO\FRQQHFWRUGLIIHUHQFHEHWZHHQH[SDQVLRQFDUGVFDSDEOHRI0+]RSHUDWLRQDQGWKRVHOLPLWHGWR0+]5HIHUWR6HFWLRQIRU
WKHH[SDQVLRQERDUGHGJHFRQQHFWRU7KHM66ENSLQLVDQRUPDOJURXQGSLQLQ
LPSOHPHQWDWLRQVWKDWDUHQRWFDSDEOHRI0+]RSHUDWLRQ,QLPSOHPHQWDWLRQVWKDWDUH0+]FDSDEOHWKHM66ENSLQPXVWEHGHFRXSOHGWRJURXQGZLWKDµ)FDSDFLWRUZKLFKPXVWEHORFDWHGZLWKLQLQFKHVRIWKHHGJH
FRQWDFWWRFRPSOHWHDQ$&UHWXUQSDWK,IWKHM66ENSLQLVSXOOHGWRWKH9LOLQSXWOHYHOLWLQGLFDWHVWKDWWKHH[SDQVLRQERDUGPXVWRSHUDWHLQWKH0+]PRGH

54 As a general rule, there will be only one such connector, but more than one are possible in certain cases.

237

Revision 2.2

238

Revision 2.2

Appendix A
Special Cycle Messages
6SHFLDO&\FOHPHVVDJHHQFRGLQJVDUHGHILQHGLQWKLVDSSHQGL[5HVHUYHGHQFRGLQJVVKRXOGQRW
EHXVHG3&,6,*PHPEHUFRPSDQLHVWKDWUHTXLUHVSHFLDOHQFRGLQJVRXWVLGHWKHUDQJHRI
FXUUHQWO\GHILQHGHQFRGLQJVVKRXOGVHQGDZULWWHQUHTXHVWWRWKH3&,6,*6WHHULQJ&RPPLWWHH
7KH6WHHULQJ&RPPLWWHHZLOODOORFDWHDQGGHILQHVSHFLDOF\FOHHQFRGLQJVEDVHGXSRQ
LQIRUPDWLRQSURYLGHGE\WKHUHTXHVWHUVSHFLI\LQJXVDJHQHHGVDQGIXWXUHSURGXFWRUDSSOLFDWLRQGLUHFWLRQ

Message Encodings
AD[15::0]

0HVVDJH7\SH

K
K
K
K
WKURXJK))))K

6+87'2:1+$/7[DUFKLWHFWXUHVSHFLILF
5HVHUYHG
5HVHUYHG

6+87'2:1LVDEURDGFDVWPHVVDJHLQGLFDWLQJWKHSURFHVVRULVHQWHULQJLQWRDVKXWGRZQPRGH
+$/7LVDEURDGFDVWPHVVDJHIURPWKHSURFHVVRULQGLFDWLQJLWKDVH[HFXWHGDKDOW
LQVWUXFWLRQ
7KH[DUFKLWHFWXUHVSHFLILFHQFRGLQJLVDJHQHULFHQFRGLQJIRUXVHE\[SURFHVVRUVDQGFKLSVHWVAD[31::16]GHWHUPLQHWKHVSHFLILFPHDQLQJRIWKH6SHFLDO&\FOHPHVVDJH
6SHFLILFPHDQLQJVDUHGHILQHGE\,QWHO&RUSRUDWLRQDQGDUHIRXQGLQSURGXFWVSHFLILFGRFXPHQWDWLRQUse of Specific Encodings
8VHRUJHQHUDWLRQRIDUFKLWHFWXUHVSHFLILFHQFRGLQJVLVQRWOLPLWHGWRWKHUHTXHVWHURIWKH
HQFRGLQJ6SHFLILFHQFRGLQJVPD\EHXVHGE\DQ\YHQGRULQDQ\V\VWHP7KHVH
HQFRGLQJVDOORZV\VWHPVSHFLILFFRPPXQLFDWLRQOLQNVEHWZHHQFRRSHUDWLQJ3&,GHYLFHVIRUSXUSRVHVZKLFKFDQQRWEHKDQGOHGZLWKWKHVWDQGDUGGDWDWUDQVIHUF\FOHW\SHV

239

Revision 2.2

240Revision 2.2

Appendix B
State Machines
This appendix describes master and target state machines. These state machines are forillustrative purposes only and are included to help illustrate PCI protocol. Actual
implementations should not directly use these state machines. The machines are
believed to be correct; however, if a conflict exists between the specification and thestate machines, the specification has precedence.
The state machines use three types of variables: states, PCI signals, and internal signals.
They can be distinguished from each other by:State in a state machine = STATE
PCI signal = SIGNAL
Internal signal = Signal
The state machines assume no delays from entering a state until signals are generated
and available for use in the machine. All PCI signals are latched on the rising edge of
CLK.
The state machines support some options (but not all) discussed in the PCI specification.
A discussion about each state and the options illustrated follows the definition of eachstate machine. The target state machine assumes medium decode and, therefore, does
not describe fast decode. If fast decode is implemented, the state diagrams (and theirassociated equations) will need to be changed to support fast decode. Caution needs tobe taken when supporting fast decode (Refer to Section 3.4.2.).
The bus interface consists of two parts. The first is the bus sequencer that performs theactual bus operation. The second part is the backend or hardware application. In a
master, the backend generates the transaction and provides the address, data, command,
Byte Enables, and the length of the transfer. It is also responsible for the address when atransaction is retried. In a target, the backend determines when a transaction is
terminated. The sequencer performs the bus operation as requested and guarantees the
PCI protocol is not violated. Note that the target implements a resource lock.
The state machine equations assume a logical operation where "*" is an AND function
and has precedence over "+" which is an OR function. Parentheses have precedence
over both. The "!" character is used to indicate the NOT of the variable. In the statemachine equations, the PCI SIGNALs represent the actual state of the signal on the PCI
bus. Low true signals will be true or asserted when they appear as !SIGNAL# and will
be false or deasserted when they appear as SIGNAL#. High true signals will be true or241

Revision 2.2

asserted when they appear as SIGNAL and will be false or deasserted when they appear
as !SIGNAL. Internal signals will be true when they appear as Signal and false when
they appear as !Signal. A few of the output enable equations use the "==" symbol torefer to the previous state. For example:
OE[PAR] == [S_DATA * !TRDY# * (cmd=read)]This indicates the output buffer for PAR is enabled when the previous state is S_DATA,TRDY# is asserted, the transaction is a read. The first state machine presented is for thetarget, the second is the master. Caution needs to be taken when an agent is both amaster and a target. Each must have its own state machine that can operate
independently of the other to avoid deadlocks. This means that the target state machine
cannot be affected by the master state machine. Although they have similar states, theycannot be built into a single machine.
Note: LOCK# can only be implemented by a bridge; refer to Appendix F for details
about the use of LOCK#. For a non-bridge device, the use of LOCK# is prohibited.

B _ BU S Y

ID LE

B A CK O F F

S _D AT A

TargetSequencer
MachineTURN_ARFREE

LOCKED

Target LOCK Machine
IDLE or TURN_AR -- Idle condition or completed transaction on bus.
goto IDLE
goto B_BUSY

242

if FRAME#
if !FRAME# * !Hit

Revision 2.2

B_BUSY -- Not involved in current transaction.
goto B_BUSY
goto IDLE
goto S_DATA
goto BACKOFF

if (!FRAME# + !D_done) * !Hit
if FRAME# * D_done + FRAME# * !D_done * !DEVSEL#
if (!FRAME# + !IRDY#) * Hit * (!Term + Term * Ready)* (FREE + LOCKED * L_lock#)*if (!FRAME# + !IRDY#) * Hit* (Term * !Ready + LOCKED * !L_lock#)

S_DATA -- Agent has accepted request and will respond.
goto S_DATA
goto BACKOFF
goto TURN_AR

if !FRAME# * !STOP# * !TRDY# * IRDY#+ !FRAME# * STOP# + FRAME# * TRDY# * STOP#
if !FRAME# * !STOP# * (TRDY# + !IRDY#)
if FRAME# * (!TRDY# + !STOP#)

BACKOFF -- Agent busy unable to respond at this time.
goto BACKOFF
goto TURN_AR

if !FRAME#
if FRAME#

Target LOCK Machine
FREE -- Agent is free to respond to all transactions.
goto LOCKED
goto FREE

if !FRAME# * LOCK# * Hit * (IDLE + TURN_AR)+ L_lock# * Hit * B_BUSY)
if ELSE

LOCKED -- Agent will not respond unless LOCK# is deasserted during the addressphase.
goto FREE
goto LOCKED

if FRAME# * LOCK#
if ELSE

Target of a transaction is responsible to drive the following signals: 55
OE[AD[31::00]]
OE[TRDY#]OE[STOP#]
OE[DEVSEL#]OE[PAR]OE[PERR#]= (S_DATA + BACKOFF) * Tar_dly * (cmd = read)= BACKOFF + S_DATA + TURN_AR (See note.)= BACKOFF + S_DATA + TURN_AR (See note.)= BACKOFF + S_DATA + TURN_AR (See note.)= OE[AD[31::00]] delayed by one clock= R_perr + R_perr (delayed by one clock)Note: If the device does fast decode, OE[PERR#] must be delayed one clock to
avoid contention.


 When the target supports the Special Cycle command, an additional term must be included to ensure

these signals are not enabled during a Special Cycle transaction.
243

Revision 2.2

TRDY#
STOP#
DEVSEL#PAR
PERR#= !(Ready * !T_abort * S_DATA * (cmd=write + cmd=read * Tar_dly))= ![BACKOFF + S_DATA * (T_abort + Term)* (cmd=write + cmd=read * Tar_dly)]= ![(BACKOFF + S_DATA) * !T_abort]= even parity across AD[31::00] and C/BE#[3::0] lines.
= R_perr

Definitions
These signals are between the target bus sequencer and the backend. They indicate how
the bus sequencer should respond to the current bus operation.
Hit
D_doneT_abortTerm
Ready
L_lock#Tar_dly
R_perr
Last_target= Hit on address decode.
= Decode done. Device has completed the address decode.
= Target is in an error condition and requires the current transaction to stop.
= Terminate the transaction. (Internal conflict or > n wait states.)= Ready to transfer data.
= Latched (during address phase) version of LOCK#.
= Turn around delay only required for zero wait state decode.
= Report parity error is a pulse of one PCI clock in duration.
= Device was the target of the last (prior) PCI transaction.

The following paragraphs discuss each state and describe which equations can beremoved if some of the PCI options are not implemented.
The IDLE and TURN_AR are two separate states in the state machine, but are combined
here because the state transitions are the same from both states. They are implemented
as separate states because active signals need to be deasserted before the target tri-states
them.
If the target cannot do single cycle address decode, the path from IDLE to S_DATA canbe removed. The reason the target requires the path from the TURN_AR state to
S_DATA and B_BUSY is for back-to-back bus operations. The target must be able todecode back-to-back transactions.
B_BUSY is a state where the agent waits for the current transaction to complete and thebus to return to the Idle state. B_BUSY is useful for devices that do slow address
decode or perform subtractive decode. If the target does neither of these two options, thepath to S_DATA and BACKOFF may be removed. The term "!Hit" may be removed
from the B_BUSY equation also. This reduces the state to waiting for the current bus
transaction to complete.
S_DATA is a state where the target transfers data and there are no optional equations.
BACKOFF is where the target goes after it asserts STOP# and waits for the master todeassert FRAME#.
FREE and LOCKED refer to the state of the target with respect to a lock operation. If
the target does not implement LOCK#, then these states are not required. FREE
indicates when the agent may accept any request when it is the target. If LOCKED, thetarget will retry any request when it is the target unless LOCK# is deasserted during theaddress phase. The agent marks itself locked whenever it is the target of a transaction
and LOCK# is deasserted during the address phase. It is a little confusing for the target
to lock itself on a transaction that is not locked. However, from an implementation pointof view, it is a simple mechanism that uses combinatorial logic and always works. The
device will unlock itself at the end of the transaction when it detects FRAME# and
LOCK# both deasserted.
244

Revision 2.2

The second equation in the goto LOCKED in the FREE state can be removed if fast
decode is done. The first equation can be removed if medium or slow decode is done.
L_lock# is LOCK# latched during the address phase and is used when the agent’s decodecompletes.

IDLE

ADDR

DR_BUS
S_TAR
M_DATA

MasterSequencer
MachineTURN_AR

FREE

BUSY

Master LOCK Machine

Master Sequencer Machine
IDLE -- Idle condition on bus.
goto ADDR
goto DR_BUS

if (Request * !Step) * !GNT# * FRAME# * IRDY#
if (Request * Step + !Request) * !GNT# * FRAME# * IRDY#

goto IDLE

if ELSEADDR -- Master starts a transaction.
JRWR0B'$7$

RQWKHQH[WULVLQJHGJHRICLK

245

Revision 2.2

M_DATA -- Master transfers data.
goto M_DATA
goto ADDR
goto S_TAR
goto TURN_AR

if !FRAME# + FRAME# * TRDY# * STOP#* !Dev_to
if (Request *!Step) * !GNT# * FRAME# * !TRDY# *STOP# * L-cycle * (Sa +FB2B_Ena)
if FRAME# * !STOP# + FRAME# * Dev_to
if ELSETURN_AR -- Transaction complete, do housekeeping.
goto ADDR
goto DR_BUS
goto IDLE

if (Request * !Step) * !GNT#
if (Request * Step + !Request) * !GNT#
if GNT#

S_TAR -- Stop was asserted, do turn around cycle.
goto DR_BUS
goto IDLE

if !GNT#
if GNT#

DR_BUS -- Bus parked at this agent or agent is using address stepping.
goto DR_BUS
goto ADDR
goto IDLE

if (Request * Step + !Request)* !GNT#
if (Request * !Step) * !GNT#
if GNT#

Master LOCK Machine
FREE -- LOCK# is not in use (not owned).
goto FREE
goto BUSY

if LOCK# + !LOCK# * Own_lock
if !LOCK# * !Own_lock

BUSY -- LOCK# is currently being used (owned).
goto FREE
goto BUSY

246

if LOCK# * FRAME#
if !LOCK# + !FRAME#

Revision 2.2

The master of the transaction is responsible to drive the following signals:
Enable the output buffers:
OE[FRAME#]= ADDR + M_DATAOE[C/BE#[3::0]] = ADDR + M_DATA + DR_BUS
if ADDR drive command
if M_DATA drive byte enables
if DR_BUS if (Step * Request) drive command else drive lines to a valid state
OE[AD[31::00] = ADDR + M_DATA * (cmd=write) + DR_BUS
if ADDR drive address
if M_DATA drive data
if DR_BUS if (Step * Request) drive address else drive lines to a valid state
OE [LOCK#]OE[IRDY#]
OE[PAR]OE[PERR#]= Own_lock * M_DATA + OE [LOCK#] * (!FRAME# + !LOCK#)== [M_DATA + ADDR]= OE[AD[31::00]] delayed by one clock= R_perr + R_perr (delayed by one clock)

The following signals are generated from state and sampled (not asynchronous) bus
signals.
FRAME# = !( ADDR + M_DATA * !Dev_to * {[!Comp* (!To + !GNT#) * STOP#] + !Ready })
IRDY#
REQ#

= ![M_DATA * (Ready + Dev_to)]= ![(Request * !Lock_a + Request * Lock_a * FREE)*!(S_TAR * Last State was S_TAR)]

LOCK#= Own_lock * ADDR + Target_abort+ Master_abort + M_DATA * !STOP# * TRDY# * !Ldt
+ Own_lock * !Lock_a * Comp * M_DATA * FRAME# * !TRDY#= even parity across AD[31::00] and C/BE#[3::0] lines.
= R_perr

PAR
PERR#

Master_abort
Target_abort
Own_lock= (M_DATA * Dev_to)= (!STOP# * DEVSEL# * M_DATA * FRAME# * !IRDY#)= LOCK# * FRAME# * IRDY# * Request * !GNT# * Lock_a+ Own_lock * (!FRAME# + !LOCK#)

247

Revision 2.2

Definitions
These signals go between the bus sequencer and the backend. They provide information
to the sequencer when to perform a transaction and provide information to the backend
on how the transaction is proceeding. If a cycle is retried, the backend will make thecorrect modification to the affected registers and then indicate to the sequencer toperform another transaction. The bus sequencer does not remember that a transaction
was retried or aborted but takes requests from the backend and performs the PCI
transaction.

Master_abort
Target_abort
Step
RequestComp
L-cycleTo
Dev_toSa
Lock_aReady
Sp_cycOwn_lock
Ldt
R_perrFB2B_Ena= The transaction was aborted by the master. (No DEVSEL#.)= The transaction was aborted by the target.
= Agent using address stepping (wait in the state until !Step).
= Request pending.
= Current transaction in last data phase.
= Last cycle was a write.
= Master timeout has expired.
= Devsel timer has expired without DEVSEL# being asserted.
= Next transaction to same agent as previous transaction.
= Request is a locked operation.
= Ready to transfer data.
= Special Cycle command.
= This agent currently owns LOCK#.
= Data was transferred during a LOCK operation.
= Report parity error is a pulse one PCI clock in duration.
= Fast Back-to-Back Enable (Configuration register bit).

The master state machine has many options built in that may not be of interest to some
implementations. Each state will be discussed indicating what affect certain options
have on the equations.
IDLE is where the master waits for a request to do a bus operation. The only option inthis state is the term "Step". It may be removed from the equations if address stepping is
not supported. All paths must be implemented. The path to DR_BUS is required toinsure that the bus is not left floating for long periods. The master whose GNT# isasserted must go to the drive bus if its Request is not asserted.
ADDR has no options and is used to drive the address and command on the bus.
M_DATA is where data is transferred. If the master does not support fast back-to-backtransactions, the path to the ADDR state is not required.
The equations are correct from the protocol point of view. However, compilers may
give errors when they check all possible combinations. For example, because of
protocol, Comp cannot be asserted when FRAME# is deasserted. Comp indicates themaster is in the last data phase, and FRAME# must be deasserted for this to be true.
TURN_AR is where the master deasserts signals in preparation for tri-stating them. The
path to ADDR may be removed if the master does not do back-to-back transactions.
S_TAR could be implemented a number of ways. The state was chosen to clarify that"state" needs to be remembered when the target asserts STOP#.

248

Revision 2.2

DR_BUS is used when GNT# has been asserted, and the master either is not prepared tostart a transaction (for address stepping) or has none pending. If address stepping is not
implemented, then the equation in goto DR_BUS that has "Step" may be removed andthe goto ADDR equation may also remove "Step".
If LOCK# is not supported by the master, the FREE and BUSY states may be removed.
These states are for the master to know the state of LOCK# when it desires to do alocked transaction. The state machine simply checks for LOCK# being asserted. Onceasserted, it stays BUSY until FRAME# and LOCK# are both deasserted signifying that
LOCK# is now free.

249

Revision 2.2

250Revision 2.2

Appendix C
Operating Rules
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DVDUHSODFHPHQWIRUWKHVSHFLILFDWLRQ7KLVDSSHQGL[RQO\FRYHUVWKHEDVLFSURWRFRODQG
UHTXLUHPHQWVFRQWDLQHGLQ&KDSWHU,WLVPHDQWWREHXVHGDVDQDLGRUTXLFNUHIHUHQFH
WRWKHEDVLFUXOHVDQGUHODWLRQVKLSVRIWKHSURWRFRO

When Signals are Stable 7KHIROORZLQJVLJQDOVDUHJXDUDQWHHGWREHVWDEOHRQDOOULVLQJHGJHVRICLK RQFH
UHVHWKDVFRPSOHWHGLOCK# IRDY#TRDY#FRAME#DEVSEL#STOP#
REQ#GNT#REQ64#ACK64#SERR# RQIDOOLQJHGJHRQO\ DQGPERR# $GGUHVV'DWDOLQHVDUHJXDUDQWHHGWREHVWDEOHDWWKHVSHFLILHGFORFNHGJHDVIROORZVD $GGUHVVAD[31::00]DUHVWDEOHUHJDUGOHVVRIZKHWKHUVRPHDUHORJLFDOGRQ W
FDUHVRQWKHILUVWFORFNWKDWVDPSOHVFRAME#DVVHUWHG
E $GGUHVVAD[63::32]DUHVWDEOHDQGYDOLGGXULQJWKHILUVWFORFNDIWHU REQ64#
DVVHUWLRQZKHQELWDGGUHVVLQJLVEHLQJXVHG 6$& RUWKHILUVWWZRFORFNVDIWHUREQ64#DVVHUWLRQZKHQELWDGGUHVVLQJLVXVHG '$& :KHQREQ64#
LVGHDVVHUWHGAD[63::32]DUHSXOOHGXSE\WKHFHQWUDOUHVRXUFH
F 'DWDAD[31::00]DUHVWDEOHDQGYDOLGUHJDUGOHVVZKLFKE\WHODQHVDUHLQYROYHG
LQWKHWUDQVDFWLRQRQUHDGVZKHQTRDY#LVDVVHUWHGDQGRQZULWHVZKHQIRDY#
LVDVVHUWHG$WDQ\RWKHUWLPHWKH\PD\EHLQGHWHUPLQDWH7KHADOLQHVFDQQRW
FKDQJHXQWLOWKHFXUUHQWGDWDSKDVHFRPSOHWHVRQFHIRDY#LVDVVHUWHGRQDZULWHWUDQVDFWLRQRUTRDY#LVDVVHUWHGRQDUHDGWUDQVDFWLRQG 'DWDAD[63::32] DUHVWDEOHDQGYDOLGUHJDUGOHVVZKLFKE\WHODQHVDUHLQYROYHG
LQWKHWUDQVDFWLRQZKHQACK64#LVDVVHUWHGDQGHLWKHUTRDY#LVDVVHUWHGRQ
UHDGVRUIRDY#LVDVVHUWHGRQZULWHV$WDQ\RWKHUWLPHWKH\PD\EH
LQGHWHUPLQDWH
H 'DWD6SHFLDOF\FOHFRPPDQGAD[31::00]DUHVWDEOHDQGYDOLGUHJDUGOHVVZKLFKE\WHODQHVDUHLQYROYHGLQWKHWUDQVDFWLRQZKHQIRDY#LVDVVHUWHG
I

'RQRWJDWHDV\QFKURQRXVGDWDGLUHFWO\RQWR3&,ZKLOHIRDY#LVDVVHUWHGRQD
ZULWHWUDQVDFWLRQDQGZKLOHTRDY#LVDVVHUWHGRQDUHDGWUDQVDFWLRQ

251

Revision 2.2

 &RPPDQG%\WHHQDEOHVDUHJXDUDQWHHGWREHVWDEOHDWWKHVSHFLILHGFORFNHGJHDV
IROORZVD &RPPDQGC/BE[3::0]# DUHVWDEOHDQGYDOLGWKHILUVWWLPHFRAME# LV
VDPSOHGDVVHUWHGDQGFRQWDLQWKHFRPPDQGFRGHVC/BE[7::4]# DUHVWDEOHDQG
YDOLGGXULQJWKHILUVWFORFNDIWHU REQ64#DVVHUWLRQZKHQELWDGGUHVVLQJLV
EHLQJXVHG 6$& DQGDUHUHVHUYHGC/BE[7::4]# DUHVWDEOHDQGYDOLGGXULQJWKH
ILUVWWZRFORFNVDIWHUREQ64#DVVHUWLRQZKHQELWDGGUHVVLQJLVXVHG '$&DQGFRQWDLQWKHDFWXDOEXVFRPPDQG:KHQREQ64#LVGHDVVHUWHGWKH
C/BE[7::4]# DUHSXOOHGXSE\WKHFHQWUDOUHVRXUFH
E%\WH(QDEOHVC/BE[3::0]# DUHVWDEOHDQGYDOLGWKHFORFNIROORZLQJWKH
DGGUHVVSKDVHDQGHDFKFRPSOHWHGGDWDSKDVHDQGUHPDLQYDOLGHYHU\FORFNGXULQJWKHHQWLUHGDWDSKDVHUHJDUGOHVVLIZDLWVWDWHVDUHLQVHUWHGDQGLQGLFDWHZKLFKE\WHODQHVFRQWDLQYDOLGGDWDC/BE[7::4]# KDYHWKHVDPHPHDQLQJDV
C/BE[3::0]# H[FHSWWKH\FRYHUWKHXSSHUE\WHVZKHQREQ64#LVDVVHUWHG

 PARLVVWDEOHDQGYDOLGRQHFORFNIROORZLQJWKHYDOLGWLPHRIAD[31::00]PAR64
LVVWDEOHDQGYDOLGRQHFORFNIROORZLQJWKHYDOLGWLPHRIAD[63::32]
 IDSELLVRQO\VWDEOHDQGYDOLGWKHILUVWFORFNFRAME#LVDVVHUWHGZKHQWKHDFFHVV
LVDFRQILJXUDWLRQFRPPDQGIDSELLVLQGHWHUPLQDWHDWDQ\RWKHUWLPH RST# INTA#INTB#INTC#DQGINTD#DUHQRWTXDOLILHGRUV\QFKURQRXVMaster Signals
 $WUDQVDFWLRQVWDUWVZKHQFRAME#LVDVVHUWHGIRUWKHILUVWWLPH
 7KHIROORZLQJJRYHUQFRAME#DQGIRDY#LQDOO3&,WUDQVDFWLRQV
D FRAME#DQGLWVFRUUHVSRQGLQJIRDY#GHILQHWKH%XV\,GOHVWDWHRIWKHEXV
ZKHQHLWKHULVDVVHUWHGWKHEXVLVEXV\ZKHQERWKDUHGHDVVHUWHGWKHEXVLVLQ
WKH,GOHVWDWH
E 2QFHFRAME#KDVEHHQGHDVVHUWHGLWFDQQRWEHUHDVVHUWHGGXULQJWKHVDPH
WUDQVDFWLRQF FRAME#FDQQRWEHGHDVVHUWHGXQOHVVIRDY#LVDVVHUWHG IRDY#PXVWDOZD\V
EHDVVHUWHGRQWKHILUVWFORFNHGJHWKDWFRAME#LVGHDVVHUWHG
G 2QFHDPDVWHUKDVDVVHUWHGIRDY#LWFDQQRWFKDQJHIRDY#RUFRAME#XQWLO
WKHFXUUHQWGDWDSKDVHFRPSOHWHV
e. The master must deassert IRDY# the clock after the completion of the last dataphase.
 :KHQFRAME#DQGIRDY# DUHGHDVVHUWHGWKHWUDQVDFWLRQKDVHQGHG
 :KHQWKHFXUUHQWWUDQVDFWLRQLVWHUPLQDWHGE\WKHWDUJHW STOP#DVVHUWHG WKH
PDVWHUPXVWGHDVVHUWLWVREQ#VLJQDOEHIRUHUHSHDWLQJWKHWUDQVDFWLRQ$GHYLFH
FRQWDLQLQJDVLQJOHVRXUFHRIPDVWHUDFWLYLW\PXVWGHDVVHUWREQ#IRUDPLQLPXPRI
WZRFORFNVRQHEHLQJZKHQWKHEXVJRHVWRWKH,GOHVWDWH DWWKHHQGRIWKH
WUDQVDFWLRQZKHUHSTOP#ZDVDVVHUWHG DQGHLWKHUWKHFORFNEHIRUHRUWKHFORFNDIWHUWKH,GOHVWDWH$GHYLFHFRQWDLQLQJPXOWLSOHVRXUFHVRIPDVWHUDFWLYLW\LV
SHUPLWWHGWRDOORZHDFKVRXUFHWRXVHWKHEXVZLWKRXWGHDVVHUWLQJREQ#HYHQLIRQH
RUPRUHVRXUFHVDUHWDUJHWWHUPLQDWHG+RZHYHUWKHGHYLFHPXVWGHDVVHUWREQ#IRU

252

Revision 2.2

WZRFORFNVRQHRIZKLFKZKLOHWKHEXVLV,GOHEHIRUHDQ\WUDQVDFWLRQWKDWZDVWDUJHWWHUPLQDWHGFDQEHUHSHDWHG
 $PDVWHUWKDWLVWDUJHWWHUPLQDWHGZLWK5HWU\PXVWXQFRQGLWLRQDOO\UHSHDWWKHVDPH
UHTXHVWXQWLOLWFRPSOHWHVKRZHYHULWLVQRWUHTXLUHGWRUHSHDWWKHWUDQVDFWLRQZKHQ
WHUPLQDWHGZLWK'LVFRQQHFWTarget Signals
 7KHIROORZLQJJHQHUDOUXOHVJRYHUQFRAME#IRDY#TRDY#DQGSTOP#ZKLOHWHUPLQDWLQJWUDQVDFWLRQVD $GDWDSKDVHFRPSOHWHVRQDQ\ULVLQJFORFNHGJHRQZKLFKIRDY#LVDVVHUWHG
DQGHLWKHUSTOP#RUTRDY#LVDVVHUWHG
E ,QGHSHQGHQWRIWKHVWDWHRISTOP#DGDWDWUDQVIHUWDNHVSODFHRQHYHU\ULVLQJ
HGJHRIFORFNZKHUHERWKIRDY#DQGTRDY#DUHDVVHUWHG
F 2QFHWKHWDUJHWDVVHUWVSTOP#LWPXVWNHHSSTOP#DVVHUWHGXQWLOFRAME#LV
GHDVVHUWHGZKHUHXSRQLWPXVWGHDVVHUWSTOP#
G 2QFHDWDUJHWKDVDVVHUWHGTRDY#RUSTOP#LWFDQQRWFKDQJHDEVSEL#
TRDY#RUSTOP#XQWLOWKHFXUUHQWGDWDSKDVHFRPSOHWHV
H :KHQHYHUSTOP#LVDVVHUWHGWKHPDVWHUPXVWGHDVVHUWFRAME#DVVRRQDV
IRDY#FDQEHDVVHUWHGI,IQRWDOUHDG\GHDVVHUWHGTRDY#STOP#DQGDEVSEL#PXVWEHGHDVVHUWHG
WKHFORFNIROORZLQJWKHFRPSOHWLRQRIWKHODVWGDWDSKDVHDQGPXVWEHWULVWDWHG
WKHQH[WFORFN $QDJHQWFODLPVWREHWKHWDUJHWRIWKHDFFHVVE\DVVHUWLQJDEVSEL# DEVSEL#PXVWEHDVVHUWHGZLWKRUSULRUWRWKHHGJHDWZKLFKWKHWDUJHWHQDEOHVLWV
RXWSXWV TRDY#STOP#RU RQDUHDG ADOLQHV  2QFHDEVSEL#KDVEHHQDVVHUWHGLWFDQQRWEHGHDVVHUWHGXQWLOWKHODVWGDWDSKDVH
KDVFRPSOHWHGH[FHSWWRVLJQDO7DUJHW$ERUWData Phases 7KHVRXUFHRIWKHGDWDLVUHTXLUHGWRDVVHUWLWV[RDY#VLJQDOXQFRQGLWLRQDOO\ZKHQ
GDWDLVYDOLG IRDY#RQDZULWHWUDQVDFWLRQTRDY#RQDUHDGWUDQVDFWLRQ  'DWDLVWUDQVIHUUHGEHWZHHQPDVWHUDQGWDUJHWRQHDFKFORFNHGJHIRUZKLFKERWK
IRDY#DQGTRDY#DUHDVVHUWHG
 /DVWGDWDSKDVHFRPSOHWHVZKHQD FRAME#LVGHDVVHUWHGDQGTRDY#LVDVVHUWHG QRUPDOWHUPLQDWLRQ RU
E FRAME#LVGHDVVHUWHGDQGSTOP#LVDVVHUWHG WDUJHWWHUPLQDWLRQ RUF FRAME#LVGHDVVHUWHGDQGWKHGHYLFHVHOHFWWLPHUKDVH[SLUHG 0DVWHU$ERUW
RU
G DEVSEL#LVGHDVVHUWHGDQGSTOP#LVDVVHUWHG 7DUJHW$ERUW 

253

Revision 2.2

 &RPPLWWLQJWRFRPSOHWHDGDWDSKDVHRFFXUVZKHQWKHWDUJHWDVVHUWVHLWKHUTRDY#RUSTOP#7KHWDUJHWFRPPLWVWR
D 7UDQVIHUGDWDLQWKHFXUUHQWGDWDSKDVHDQGFRQWLQXHWKHWUDQVDFWLRQ LIDEXUVW
E\DVVHUWLQJTRDY#DQGQRWDVVHUWLQJSTOP#
E 7UDQVIHUGDWDLQWKHFXUUHQWGDWDSKDVHDQGWHUPLQDWHWKHWUDQVDFWLRQE\DVVHUWLQJ
ERWKTRDY#DQGSTOP#
F 1RWWUDQVIHUGDWDLQWKHFXUUHQWGDWDSKDVHDQGWHUPLQDWHWKHWUDQVDFWLRQE\
DVVHUWLQJSTOP#DQGGHDVVHUWLQJTRDY#
G 1RWWUDQVIHUGDWDLQWKHFXUUHQWGDWDSKDVHDQGWHUPLQDWHWKHWUDQVDFWLRQZLWKDQ
HUURUFRQGLWLRQ 7DUJHW$ERUW E\DVVHUWLQJSTOP#DQGGHDVVHUWLQJTRDY#DQG
DEVSEL# 7KHWDUJHWKDVQRWFRPPLWWHGWRFRPSOHWHWKHFXUUHQWGDWDSKDVHZKLOHTRDY#DQG
STOP#DUHERWKGHDVVHUWHG7KHWDUJHWLVVLPSO\LQVHUWLQJZDLWVWDWHV

Arbitration
 7KHDJHQWLVSHUPLWWHGWRVWDUWDWUDQVDFWLRQRQO\LQWKHIROORZLQJWZRFDVHVD GNT#LVDVVHUWHGDQGWKHEXVLVLGOH FRAME#DQGIRDY#DUHGHDVVHUWHG E GNT#LVDVVHUWHGLQWKHODVWGDWDSKDVHRIDWUDQVDFWLRQDQGWKHDJHQWLVVWDUWLQJD
QHZWUDQVDFWLRQXVLQJIDVWEDFNWREDFNWLPLQJ FRAME#LVGHDVVHUWHGDQG
TRDY#RUSTOP#LVDVVHUWHGRUWKHWUDQVDFWLRQWHUPLQDWHVZLWK0DVWHU$ERUW 
 7KHDUELWHUPD\GHDVVHUWDQDJHQW VGNT#RQDQ\FORFN 2QFHDVVHUWHGGNT#PD\EHGHDVVHUWHGDFFRUGLQJWRWKHIROORZLQJUXOHVD ,IGNT#LVGHDVVHUWHGDQGFRAME#LVDVVHUWHGRQWKHVDPHFORFNWKHEXVWUDQVDFWLRQLVYDOLGDQGZLOOFRQWLQXH
E 2QHGNT#FDQEHGHDVVHUWHGFRLQFLGHQWZLWKDQRWKHUGNT# EHLQJDVVHUWHGLI
WKHEXVLVQRWLQWKH,GOHVWDWH2WKHUZLVHDRQHFORFNGHOD\LVUHTXLUHGEHWZHHQ
WKHGHDVVHUWLRQRIDGNT#DQGWKHDVVHUWLRQRIWKHQH[WGNT#RUHOVHWKHUHPD\
EHFRQWHQWLRQRQWKHADOLQHVDQGPAR
F :KLOHFRAME#LVGHDVVHUWHGGNT#PD\EHGHDVVHUWHGDWDQ\WLPHLQRUGHUWR
VHUYLFHDKLJKHUSULRULW\PDVWHURULQUHVSRQVHWRWKHDVVRFLDWHGREQ#EHLQJ
GHDVVHUWHG
 :KHQWKHDUELWHUDVVHUWVDQDJHQW VGNT#DQGWKHEXVLVLQWKH,GOHVWDWHWKDWDJHQW
PXVWHQDEOHLWVAD[31::00]C/BE[3::0]#DQG RQHFORFNODWHU PARRXWSXWEXIIHUVZLWKLQHLJKW3&,FORFNV UHTXLUHG ZKLOHWZRWKUHHFORFNVLVUHFRPPHQGHG

Latency
25. All targets are required to complete the initial data phase of a transaction (read or
write) within 16 clocks from the assertion of FRAME#. Host bus bridges have an
exception (refer to Section 3.5.1.1.).

56 Higher priority here does not imply a fixed priority arbitration, but refers to the agent that would win

arbitration at a given instant in time.
254

Revision 2.2

26. The target is required to complete a subsequent data phase within eight clocks fromthe completion of the previous data phase.
27. A master is required to assert its IRDY# within eight clocks for any given data phase(initial and subsequent).

Device Selection
28. A target must do a full decode before driving/asserting DEVSEL# or any othertarget response signal.
29. A target must assert DEVSEL# (claim the transaction) before it is allowed to issue
any other target response.
30. In all cases except Target-Abort, once a target asserts DEVSEL# it must notdeassert DEVSEL# until FRAME# is deasserted (IRDY# is asserted) and the last
data phase has completed.
31. A PCI device is a target of a Type 0 configuration transaction (read or write) only if
its IDSEL is asserted, and AD[1::0] are “00” during the address phase of thecommand.

Parity 3DULW\LVJHQHUDWHGDFFRUGLQJWRWKHIROORZLQJUXOHV
D 3DULW\LVFDOFXODWHGWKHVDPHRQDOO3&,WUDQVDFWLRQVUHJDUGOHVVRIWKHW\SHRU
IRUP
E 7KHQXPEHURI³´VRQAD[31::00]C/BE[3::0]#DQGPARHTXDOVDQHYHQ
QXPEHU
F 7KHQXPEHURI³´VRQAD[63::32]C/BE[7::4]#DQGPAR64HTXDOVDQHYHQ
QXPEHUG *HQHUDWLQJSDULW\LVQRWRSWLRQDOLWPXVWEHGRQHE\DOO3&,FRPSOLDQWGHYLFHV
33. Only the master of a corrupted data transfer is allowed to report parity errors tosoftware using mechanisms other than PERR# (i.e., requesting an interrupt or
asserting SERR#). In some cases, the master delegates this responsibility to a PCIto-PCI bridge handling posted memory write data. See the PCI-to-PCI Bridge
Architecture Specification for details.

255

Revision 2.2

256Revision 2.2

Appendix DClass Codes
7KLVDSSHQGL[GHVFULEHVWKHFXUUHQW&ODVV&RGHHQFRGLQJV7KLVOLVWPD\EHHQKDQFHGDW
DQ\WLPH7KH3&,6,*ZHESDJHVFRQWDLQWKHODWHVWYHUVLRQ&RPSDQLHVZLVKLQJWR
GHILQHDQHZHQFRGLQJVKRXOGFRQWDFWWKH3&,6,*$OOXQVSHFLILHGYDOXHVDUHUHVHUYHG
IRU6,*DVVLJQPHQW
Base Class

Meaning00h

Device was built before Class Codedefinitions were finalized

01h

Mass storage controller

02h

Network controller

03h

Display controller

04hMultimedia device

05h

Memory controller

06h

Bridge device

07h

Simple communication controllers

08h

Base system peripherals

09h

Input devices

0AhDocking stations

0Bh

Processors

0Ch

Serial bus controllers

0Dh

Wireless controller

0EhIntelligent I/O controllers

0FhSatellite communication controllers

10h

Encryption/Decryption controllers

11h

Data acquisition and signal processing
controllers

12h - FEh

Reserved

FFh

Device does not fit in any defined classes

257

Revision 2.2%DVH&ODVVK
7KLVEDVHFODVVLVGHILQHGWRSURYLGHEDFNZDUGFRPSDWLELOLW\IRUGHYLFHVWKDWZHUHEXLOW
EHIRUHWKH&ODVV&RGHILHOGZDVGHILQHG1RQHZGHYLFHVVKRXOGXVHWKLVYDOXHDQG
H[LVWLQJGHYLFHVVKRXOGVZLWFKWRDPRUHDSSURSULDWHYDOXHLISRVVLEOH
)RUFODVVFRGHVZLWKWKLVEDVHFODVVYDOXHWKHUHDUHWZRGHILQHGYDOXHVIRUWKHUHPDLQLQJILHOGVDVVKRZQLQWKHWDEOHEHORZ$OORWKHUYDOXHVDUHUHVHUYHG
Base Class

Sub-Class
00h

Interface
00h

01h

00h

00h

Meaning
All currently implemented devices
except VGA-compatible devices
VGA-compatible device%DVH&ODVVK
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIPDVVVWRUDJHFRQWUROOHUV6HYHUDOVXEFODVVYDOXHVDUHGHILQHG7KH,'(FRQWUROOHUFODVVLVWKHRQO\RQHWKDWKDVDVSHFLILFUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHGHILQHG
Base Class

01h

Sub-Class
00h
01h
02h
03h
04h
80h

Interface
00h
xxh
00h
00h
00h
00h

MeaningSCSI bus controller
IDE controller (see below)
Floppy disk controller
IPI bus controller
RAID controller
Other mass storage controller)LJXUH'3URJUDPPLQJ,QWHUIDFH%\WH/D\RXWIRU,'(&RQWUROOHU&ODVV&RGH

7KH3&,6,*GRFXPHQW3&,,'(&RQWUROOHU6SHFLILFDWLRQFRPSOHWHO\GHVFULEHVWKH
OD\RXWDQGPHDQLQJRIELWVWKURXJKLQWKH3URJUDPPLQJ,QWHUIDFHE\WH7KH
GRFXPHQW%XV0DVWHU3URJUDPPLQJ,QWHUIDFHIRU,'($7$&RQWUROOHUVGHVFULEHVWKH
PHDQLQJRIELWLQWKH3URJUDPPLQJ,QWHUIDFHE\WH7KLVGRFXPHQWFDQEHREWDLQHGYLD)$;E\FDOOLQJ  DQGUHTXHVWLQJGRFXPHQW

258

Revision 2.2%DVH&ODVVK
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIQHWZRUNFRQWUROOHUV6HYHUDOVXEFODVVYDOXHV
DUHGHILQHG7KHUHDUHQRUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHVGHILQHG
Base Class
02h

Sub-Class
00h
01h
02h
03h
04h
80h

Interface
00h
00h
00h
00h
00h
00h

Meaning
Ethernet controller
Token Ring controller
FDDI controller
ATM controller
ISDN controller
Other network controller%DVH&ODVVK
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIGLVSOD\FRQWUROOHUV)RU9*$GHYLFHV 6XE&ODVVK WKHSURJUDPPLQJLQWHUIDFHE\WHLVGLYLGHGLQWRDELWILHOGWKDWLGHQWLILHV
DGGLWLRQDOYLGHRFRQWUROOHUFRPSDWLELOLWLHV$GHYLFHFDQVXSSRUWPXOWLSOHLQWHUIDFHVE\
XVLQJWKHELWPDSWRLQGLFDWHZKLFKLQWHUIDFHVDUHVXSSRUWHG)RUWKH;*$GHYLFHV 6XE&ODVVK RQO\WKHVWDQGDUG;*$LQWHUIDFHLVGHILQHG6XE&ODVVKLVIRUFRQWUROOHUVWKDWKDYHKDUGZDUHVXSSRUWIRU'RSHUDWLRQVDQGDUHQRW9*$FRPSDWLEOH
Base Class

Sub-ClassInterface
00000000b

03h

00h

00000001b

01h
02h
80h

00h
00h
00h

Meaning
VGA-compatible controller. Memory
addresses 0A0000h through0BFFFFh. I/O addresses 3B0h to
3BBh and 3C0h to 3DFh and allaliases of these addresses.
8514-compatible controller -- 2E8h
and its aliases, 2EAh-2EFh
XGA controller
3D controller
Other display controller%DVH&ODVVK
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIPXOWLPHGLDGHYLFHV6HYHUDOVXEFODVVYDOXHV
DUHGHILQHG7KHUHDUHQRUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHVGHILQHG
Base Class

04h

Sub-Class
00h
01h
02h
80h

Interface
00h
00h
00h
00h

Meaning
Video device
Audio device
Computer telephony device
Other multimedia device

259

Revision 2.2%DVH&ODVVK
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIPHPRU\FRQWUROOHUV UHIHUWR6HFWLRQ 
6HYHUDOVXEFODVVYDOXHVDUHGHILQHG7KHUHDUHQRUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHV
GHILQHG
Base Class
05h

Sub-Class
00h
01h
80h

Interface
00h
00h
00h

Meaning
RAM
Flash
Other memory controller%DVH&ODVVK
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIEULGJHGHYLFHV$3&,EULGJHLVDQ\3&,GHYLFH
WKDWPDSV3&,UHVRXUFHV PHPRU\RU,2 IURPRQHVLGHRIWKHGHYLFHWRWKHRWKHU6HYHUDOVXEFODVVYDOXHVDUHGHILQHG
Base Class

06h

Sub-Class
00h
01h
02h
03h
04h

Interface
00h
00h
00h
00h
00h
01h

05h
06h
07h
08h
80h

00h
00h
00h
xxh
00h

Meaning
Host bridge
ISA bridge
EISA bridge
MCA bridge
PCI-to-PCI bridge
Subtractive Decode PCI-to-PCI
bridge. This interface code identifies
the PCI-to-PCI bridge as a device that
supports subtractive decoding in
addition to all the currently defined
functions of a PCI-to-PCI bridge.
PCMCIA bridge
NuBus bridge
CardBus bridge
RACEway bridge (see below)
Other bridge device

5$&(ZD\LVDQ$16,VWDQGDUG $16,9,7$ VZLWFKLQJIDEULF)RUWKH
3URJUDPPLQJ,QWHUIDFHELWV>@DUHUHVHUYHGUHDGRQO\DQGUHWXUQ]HURV%LWGHILQHV
WKHRSHUDWLRQPRGHDQGLVUHDGRQO\7UDQVSDUHQWPRGH
(QGSRLQWPRGH

260

Revision 2.2

Base Class 07h
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIVLPSOHFRPPXQLFDWLRQVFRQWUROOHUV6HYHUDO
VXEFODVVYDOXHVDUHGHILQHGVRPHRIWKHVHKDYLQJVSHFLILFZHOONQRZQUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHVBase Class

Sub-ClassInterface
00h

00h

01h
02h
03h
04h
05h
06h
00h
01h
02h
03h
FEh

01h

07h

02h

00h
00h
01h

03h

02h
03h
04h

80h

00h

Meaning
Generic XT-compatible serial
controller
16450-compatible serial controller
16550-compatible serial controller
16650-compatible serial controller
16750-compatible serial controller
16850-compatible serial controller
16950-compatible serial controller
Parallel port
Bi-directional parallel port
ECP 1.X compliant parallel port
IEEE1284 controller
IEEE1284 target device (not acontroller)
Multiport serial controller
Generic modem
Hayes compatible modem, 16450compatible interface (see below)
Hayes compatible modem, 16550compatible interface (see below)
Hayes compatible modem, 16650compatible interface (see below)
Hayes compatible modem, 16750compatible interface (see below)
Other communications device)RU+D\HVFRPSDWLEOHPRGHPVWKHILUVWEDVHDGGUHVVUHJLVWHU DWRIIVHWK PDSVWKH
DSSURSULDWHFRPSDWLEOH LHHWF UHJLVWHUVHWIRUWKHVHULDOFRQWUROOHUDW
WKHEHJLQQLQJRIWKHPDSSHGVSDFH1RWHWKDWWKHVHUHJLVWHUVFDQEHHLWKHUPHPRU\RU,2PDSSHGGHSHQGLQJZKDWNLQGRI%$5LVXVHG

261

Revision 2.2%DVH&ODVVK
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIJHQHULFV\VWHPSHULSKHUDOV6HYHUDOVXEFODVVYDOXHVDUHGHILQHGPRVWRIWKHVHKDYLQJDVSHFLILFZHOONQRZQUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFH
Base Class

Sub-Class

00h

01h
08h
02h
03h
04h
80h

Interface
00h
01h
02h
10h
20h
00h
01h
02h
00h
01h
02h
00h
01h
00h
00h

Meaning
Generic 8259 PIC
ISA PICEISA PIC
I/O APIC interrupt controller (seebelow)
I/O(x) APIC interrupt controller
Generic 8237 DMA controller
ISA DMA controller
EISA DMA controller
Generic 8254 system timer
ISA system timer.
EISA system timers (two timers)
Generic RTC controller
ISA RTC controller
Generic PCI Hot-Plug controller
Other system peripheral)RU,2$3,&,QWHUUXSW&RQWUROOHUWKH%DVH$GGUHVV5HJLVWHUDWRIIVHW[LVXVHGWR
UHTXHVWDPLQLPXPRIE\WHVRIQRQSUHIHWFKDEOHPHPRU\7ZRUHJLVWHUVZLWKLQWKDW
VSDFHDUHORFDWHGDW%DVH[ ,26HOHFW5HJLVWHU DQG%DVH[ ,2:LQGRZ
5HJLVWHU )RUDIXOOGHVFULSWLRQRIWKHXVHRIWKHVHUHJLVWHUVUHIHUWRWKHGDWDVKHHWIRU
WKH,QWHO(%LQWKH3&,VHW(,6$%ULGJH'DWDERRN

262

Revision 2.2%DVH&ODVVK
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRILQSXWGHYLFHV6HYHUDOVXEFODVVYDOXHVDUH
GHILQHG$UHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHLVGHILQHGIRUJDPHSRUWFRQWUROOHUVBase Class

09h

Sub-Class
00h
01h
02h
03h
04h
80h

Interface
00h
00h
00h
00h
00h
10h
00h

Meaning
Keyboard controller
Digitizer (pen)Mouse controller
Scanner controller
Gameport controller (generic)Gameport controller (see below)
Other input controller$JDPHSRUWFRQWUROOHUZLWKD3URJUDPPLQJ,QWHUIDFH KLQGLFDWHVWKDWDQ\%DVH$GGUHVVUHJLVWHUVLQWKLVIXQFWLRQWKDWUHTXHVWDVVLJQ,2DGGUHVVVSDFHWKHUHJLVWHUVLQ
WKDW,2VSDFHFRQIRUPWRWKHVWDQGDUGµOHJDF\¶JDPHSRUWV7KHE\WHDWRIIVHWKLQDQ,2UHJLRQEHKDYHVDVDOHJDF\JDPHSRUWLQWHUIDFHZKHUHUHDGVWRWKHE\WHUHWXUQMR\VWLFNJDPHSDGLQIRUPDWLRQDQGZULWHVWRWKHE\WHVWDUWWKH5&WLPHU7KHE\WHDW
RIIVHWKLVDQDOLDVRIWKHE\WHDWRIIVHWK$OORWKHUE\WHVLQDQ,2UHJLRQDUH
XQVSHFLILHGDQGFDQEHXVHGLQYHQGRUXQLTXHZD\V%DVH&ODVV$K
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIGRFNLQJVWDWLRQV1RVSHFLILFUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHVDUHGHILQHG
Base Class
0Ah

Sub-Class
00h
80h

Interface00h
00h

Meaning
Generic docking station
Other type of docking station%DVH&ODVV%K
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRISURFHVVRUV6HYHUDOVXEFODVVYDOXHVDUH
GHILQHGFRUUHVSRQGLQJWRGLIIHUHQWSURFHVVRUW\SHVRULQVWUXFWLRQVHWV7KHUHDUHQR
VSHFLILFUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHVGHILQHG
Base Class

0Bh

Sub-Class
00h
01h
02h
10h
20h
30h
40h

Interface
00h
00h
00h
00h
00h
00h
00h

Meaning386
486
Pentium
AlphaPowerPC
MIPS
Co-processor

263

Revision 2.2%DVH&ODVV&K
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIVHULDOEXVFRQWUROOHUV6HYHUDOVXEFODVVYDOXHV
DUHGHILQHG7KHUHDUHVSHFLILFUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHVGHILQHGIRU
8QLYHUVDO6HULDO%XVFRQWUROOHUVDQG,(((FRQWUROOHUVBase Class

0Ch

Sub-Class
00

Interface
00h
10h

01h
02h

00h
00h
00h

03h

10h
80h

04h
05h

FEh
00h
00h

Meaning
IEEE 1394 (FireWire)
IEEE 1394 following the 1394
OpenHCI specification
ACCESS.bus
SSA
Universal Serial Bus (USB) following
the Universal Host Controller
Specification
Universal Serial Bus (USB) following
the Open Host Controller Specification
Universal Serial Bus with no specificprogramming interface
USB device (not host controller)
Fibre Channel
SMBus (System Management Bus)

%DVH&ODVV'K
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIZLUHOHVVFRQWUROOHUV6HYHUDOVXEFODVVYDOXHV
DUHGHILQHG7KHUHDUHQRVSHFLILFUHJLVWHUOHYHOSURJUDPPLQJLQWHUIDFHVGHILQHG
Base Class
0Dh

Sub-Class
00
01h
10h
80h

Interface
00h
00h
00h
00h

MeaningiRDA compatible controller
Consumer IR controller
RF controller
Other type of wireless controller%DVH&ODVV(K
7KLVEDVHFODVVLVGHILQHGIRULQWHOOLJHQW,2FRQWUROOHUV7KHSULPDU\FKDUDFWHULVWLFRIWKLVEDVHFODVVLVWKDWWKH,2IXQFWLRQSURYLGHGIROORZVVRPHVRUWRIJHQHULFGHILQLWLRQ
IRUDQ,2FRQWUROOHU
Base Class
0Eh

Sub-Class
00

Interfacexxh
00h

Meaning
Intelligent I/O (I2O) Architecture
Specification 1.0
Message FIFO at offset 040h

7KHVSHFLILFDWLRQIRU,QWHOOLJHQW,2$UFKLWHFWXUH,2FDQEHGRZQORDGHGIURPIWSLQWHOFRPSXE,$/LR

264

Revision 2.2%DVH&ODVV)K
7KLVEDVHFODVVLVGHILQHGIRUVDWHOOLWHFRPPXQLFDWLRQFRQWUROOHUV&RQWUROOHUVRIWKLV
W\SHDUHXVHGWRFRPPXQLFDWHZLWKVDWHOOLWHV
Base Class
0Fh

Sub-Class
01h
02h
03h
04h

Interface
00h
00h
00h
00h

Meaning
TV
Audio
Voice
Data

%DVH&ODVVK
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIHQFU\SWLRQDQGGHFU\SWLRQFRQWUROOHUV6HYHUDO
VXEFODVVYDOXHVDUHGHILQHG7KHUHDUHQRUHJLVWHUOHYHOLQWHUIDFHVGHILQHG
Base Class
10h

Sub-Class
00h
10h
80h

Interface
00h
00h
00h

Meaning
1HWZRUNDQGFRPSXWLQJHQGHFU\SWLRQ(QWHUWDLQPHQWHQGHFU\SWLRQ
Other en/decryption%DVH&ODVVK
7KLVEDVHFODVVLVGHILQHGIRUDOOW\SHVRIGDWDDFTXLVLWLRQDQGVLJQDOSURFHVVLQJFRQWUROOHUV6HYHUDOVXEFODVVYDOXHVDUHGHILQHG7KHUHDUHQRUHJLVWHUOHYHOLQWHUIDFHV
GHILQHG
Base Class
11h

Sub-Class
00h
80h

Interface00h
00h

Meaning'3,2PRGXOHV
2WKHUGDWDDFTXLVLWLRQVLJQDO
SURFHVVLQJFRQWUROOHUV265

Revision 2.2

266

Revision 2.2

Appendix E
System Transaction Ordering
Many programming tasks, especially those controlling intelligent peripheral devices
common in PCI systems, require specific events to occur in a specific order. If theevents generated by the program do not occur in the hardware in the order intended by
the software, a peripheral device may behave in a totally unexpected way. PCI
transaction ordering rules are written to give hardware the flexibility to optimize
performance by rearranging certain events that do not affect device operation, yet strictly
enforce the order of events that do affect device operation.
One performance optimization that PCI systems are allowed to do is the posting of
memory write transactions. Posting means the transaction is captured by an intermediate
agent; e.g., a bridge from one bus to another, so that the transaction completes at thesource before it actually completes at the intended destination. This allows the source toproceed with the next operation while the transaction is still making its way through thesystem to its ultimate destination.
While posting improves system performance, it complicates event ordering. Since thesource of a write transaction proceeds before the write actually reaches its destination,other events that the programmer intended to happen after the write may happen before
the write. Many of the PCI ordering rules focus on posting buffers requiring them to be
flushed to keep this situation from causing problems.
If the buffer flushing rules are not written carefully, however, deadlock can occur. The
rest of the PCI transaction ordering rules prevent the system buses from deadlocking
when posting buffers must be flushed.
Simple devices do not post outbound transactions. Therefore, their requirements aremuch simpler than those presented here for bridges. Refer to Section 3.2.5.1. for therequirements for simple devices.
The focus of the remainder of this appendix is on a PCI-to-PCI bridge. This allows thesame terminology to be used to describe a transaction initiated on either interface and iseasier to understand. To apply these rules to other bridges, replace a PCI transaction
type with its equivalent transaction type of the host bus (or other specific bus). Whilethe discussion focuses on a PCI-to-PCI bridge, the concepts can be applied to all bridges.

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The ordering rules for a specific implementation may vary. This appendix covers therules for all accesses traversing a bridge assuming that the bridge can handle multiple
transactions at the same time in each direction. Simpler implementations are possible
but are not discussed here.

E.1 Producer - Consumer Ordering Model
The Producer - Consumer model for data movement between two masters is an example
of a system that would require this kind of ordering. In this model, one agent, theProducer, produces or creates the data and another agent, the Consumer, consumes oruses the data. The Producer and Consumer communicate between each other via a flag
and a status element. The Producer sets the flag when all the data has been written andthen waits for a completion status code. The Consumer waits until it finds the flag set,
then it resets the flag, consumes the data, and writes the completion status code. Whenthe Producer finds the completion status code, it clears it and the sequence repeats.
Obviously, the order in which the flag and data are written is important. If some of the
Producer’s data writes were posted, then without buffer-flushing rules it might bepossible for the Consumer to see the flag set before the data writes had completed. The
PCI ordering rules are written such that no matter which writes are posted, the Consumer
can never see the flag set and read the data until the data writes are finished. This
specification refers to this condition as “having a consistent view of data.” Notice that if
the Consumer were to pass information back to the Producer in addition to the statuscode, the order of writing this additional information and the status code becomes
important, just as it was for the data and flag.
In practice, the flag might be a doorbell register in a device or it might be a mainmemory pointer to data located somewhere else in memory. And the Consumer mightsignal the Producer using an interrupt or another doorbell register, rather than having the
Producer poll the status element. But in all cases, the basic need remains the same; theProducer’s writes to the data area must complete before the Consumer observes that theflag has been set and reads the data.
This model allows the data, the flag, the status element, the Producer, and the Consumer
to reside anywhere in the system. Each of these can reside on different buses and theordering rules maintain a consistent view of the data. For example, in Figure E-1, theagent producing the data, the flag, and the status element reside on Bus 1, while theactual data and the Consumer of the data both reside on Bus 0. The Producer writes thelast data and the PCI-to-PCI bridge between Bus 0 and 1 completes the access by posting
the data. The Producer of the data then writes the flag changing its status to indicate thatthe data is now valid for the Consumer to use. In this case, the flag has been set before
the final datum has actually been written (to the final destination). PCI ordering rules
require that when the Consumer of the data reads the flag (to determine if the data isvalid), the read will cause the PCI-to-PCI bridge to flush the posted write data to thefinal destination before completing the read. When the Consumer determines the data isvalid by checking the flag, the data is actually at the final destination.

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Consumer

Data

PCI Bus 0
PCI-PCI
BridgePCI Bus 1

Producer

Flag

Status)LJXUH(([DPSOH3URGXFHU&RQVXPHU0RGHOThe ordering rules lead to the same results regardless of where the Producer, theConsumer, the data, the flag, and the status element actually reside. The data is always
at the final destination before the Consumer can read the flag. This is true even when all
five reside on different bus segments of the system. In one configuration, the data will
be forced to the final destination when the Consumer reads the flag. In anotherconfiguration, the read of the flag occurs without forcing the data to its final destination;
however, the read request of the actual data pushes the final datum to the finaldestination before completing the read.
A system may have multiple Producer-Consumer pairs operating simultaneously, withdifferent data - flag-status sets located all around the system. But since only one
Producer can write to a single data-flag set, there are no ordering requirements between
different masters. Writes from one master on one bus may occur in one order on one
bus, with respect to another master’s writes, and occur in another order on another bus.
In this case, the rules allow for some writes to be rearranged; for example, an agent on
Bus 1 may see Transaction A from a master on Bus 1 complete first, followed byTransaction B from another master on Bus 0. An agent on Bus 0 may see Transaction B
complete first followed by Transaction A. Even though the actual transactions complete
in a different order, this causes no problem since the different masters must be
addressing different data-flag sets.

E.2. Summary of PCI Ordering Requirements
Following is a summary of the general PCI ordering requirements presented in
Section 3.2.5. These requirements apply to all PCI transactions, whether they are using
Delayed Transactions or not.
General Requirements
1. The order of a transaction is determined when it completes. Transactions terminatedwith Retry are only requests and can be handled by the system in any order.

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2. Memory writes can be posted in both directions in a bridge. I/O and Configuration
writes are not posted. (I/O writes can be posted in the Host Bridge, but some
restrictions apply.) Read transactions (Memory, I/O, or Configuration) are notposted.
3. Posted memory writes moving in the same direction through a bridge will completeon the destination bus in the same order they complete on the originating bus.
4. Write transactions crossing a bridge in opposite directions have no ordering
relationship.
5. A read transaction must push ahead of it through the bridge any posted writes
originating on the same side of the bridge and posted before the read. Before theread transaction can complete on its originating bus, it must pull out of the bridge
any posted writes that originated on the opposite side and were posted before theread command completes on the read-destination bus.
6. A bridge can never make the acceptance (posting) of a memory write transaction as atarget contingent on the prior completion of a non-locked transaction as a master on
the same bus. Otherwise, a deadlock may occur. Bridges are allowed to refuse toaccept a memory write for temporary conditions which are guaranteed to be resolved
with time. A bridge can make the acceptance of a memory write transaction as atarget contingent on the prior completion of locked transaction as a master only if
the bridge has already established a locked operation with its intended target.
The following is a summary of the PCI ordering requirements specific to Delayed
Transactions, presented in Section 3.3.3.3.
Delayed Transaction Requirements
1. A target that uses Delayed Transactions may be designed to have any number ofDelayed Transactions outstanding at one time.
2. Only non-posted transactions can be handled as Delayed Transactions.
3. A master must repeat any transaction terminated with Retry since the target may beusing a Delayed Transaction.
4. Once a Delayed Request has been attempted on the destination bus, it must continue
to be repeated until it completes on the destination bus. Before it is attempted on thedestination bus, it is only a request and may be discarded at any time.
5. A Delayed Completion can only be discarded when it is a read from a prefetchable
region, or if the master has not repeated the transaction in 2 15 clocks.
6. A target must accept all memory writes addressed to it, even while completing arequest using Delayed Transaction termination.
7. Delayed Requests and Delayed Completions are not required to be kept in their
original order with respect to themselves or each other.
8. Only a Delayed Write Completion can pass a Posted Memory Write. A Posted
Memory Write must be given an opportunity to pass everything except another
Posted Memory Write.

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9. A single master may have any number of outstanding requests terminated with
Retry. However, if a master requires one transaction to be completed before another,it cannot attempt the second one on PCI until the first one has completed.

E.3. Ordering of Requests
A transaction is considered to be a request when it is presented on the bus. When thetransaction is terminated with Retry, it is still considered a request. A transaction
becomes complete or a completion when data actually transfers (or is terminated withMaster-Abort or Target-Abort). The following discussion will refer to transactions as
being a request or completion depending on the success of the transaction.
A transaction that is terminated with Retry has no ordering relationship with any otheraccess. Ordering of accesses is only determined when an access completes (transfersdata). For example, four masters A, B, C, and D reside on the same bus segment and alldesire to generate an access on the bus. For this example, each agent can only request asingle transaction at a time and will not request another until the current accesscompletes. The order in which transactions complete are based on the algorithm of thearbiter and the response of the target, not the order in which each agent’s REQ# signal
was asserted. Assuming that some requests are terminated with Retry, the order inwhich they complete is independent of the order they were first requested. By changing
the arbiter’s algorithm, the completion of the transactions can be any sequence (i.e., A,
B, C, and then D or B, D, C, and then A, and so on). Because the arbiter can change theorder in which transactions are requested on the bus, and, therefore, the completion ofsuch transactions, the system is allowed to complete them in any order it desires. Thismeans that a request from any agent has no relationship with a request from any otheragent. The only exception to this rule is when LOCK# is used, which is described later.
Take the same four masters (A, B, C, and D) used in the previous paragraph andintegrate them onto a single piece of silicon (a multi-function device). For a multifunction device, the four masters operate independent of each other, and each function
only presents a single request on the bus for this discussion. The order their requests
complete is the same as if they where separate agents and not a multi-function device,
which is based on the arbitration algorithm. Therefore, multiple requests from a single
agent may complete in any order, since they have no relationship to each other.
Another device, not a multi-function device, has multiple internal resources that cangenerate transactions on the bus. If these different sources have some ordering
relationship, then the device must ensure that only a single request is presented on thebus at any one time. The agent must not attempt a subsequent transaction until theprevious transaction completes. For example, a device has two transactions to completeon the bus, Transaction A and Transaction B and A must complete before B to preserve
internal ordering requirements. In this case, the master cannot attempt B until A has
completed.
The following example would produce inconsistent results if it were allowed to occur.
Transaction A is to a flag that covers data, and Transaction B accesses the actual data
covered by the flag. Transaction A is terminated with Retry, because the addressedtarget is currently busy or resides behind a bridge. Transaction B is to a target that isready and will complete the request immediately. Consider what happens when these271

Revision 2.2

two transactions are allowed to complete in the wrong order. If the master allows
Transaction B to be presented on the bus after Transaction A was terminated with Retry,
Transaction B can complete before Transaction A. In this case, the data may be accessed
before it is actually valid. The responsibility to prevent this from occurring rests withthe master, which must block Transaction B from being attempted on the bus until
Transaction A completes. A master presenting multiple transactions on the bus mustensure that subsequent requests (that have some relationship to a previous request) are
not presented on the bus until the previous request has completed. The system isallowed to complete multiple requests from the same agent in any order. When a masterallows multiple requests to be presented on the bus without completing, it must repeat
each request independent of how any of the other requests complete.

E.4. Ordering of Delayed Transactions
A Delayed Transaction progresses to completion in three phases:
1. Request by the master2. Completion of the request by the target
3. Completion of the transaction by the master
During the first phase, the master generates a transaction on the bus, the target decodes
the access, latches the information required to complete the access, and terminates therequest with Retry. The latched request information is referred to as a Delayed Request.
During the second phase, the target independently completes the request on thedestination bus using the latched information from the Delayed Request. The result ofcompleting the Delayed Request on the destination bus produces a Delayed Completion,
which consists of the latched information of the Delayed Request and the completion
status (and data if a read request). During the third phase, the master successfully rearbitrates for the bus and reissues the original request. The target decodes the request
and gives the master the completion status (and data if a read request). At this point, theDelayed Completion is retired and the transaction has completed.
The number of simultaneous Delayed Transactions a bridge is capable of handling islimited by the implementation and not by the architecture. Table E-1 represents theordering rules when a bridge in the system is capable of allowing multiple transactions toproceed in each direction at the same time. Each column of the table represents anaccess that was accepted by the bridge earlier, while each row represents a transaction
just accepted. The contents of the box indicate what ordering relationship the second
transaction must have to the first.
PMW - Posted Memory Write is a transaction that has completed on the originating bus
before completing on the destination bus and can only occur for Memory Write andMemory Write and Invalidate commands.
DRR - Delayed Read Request is a transaction that must complete on the destination bus
before completing on the originating bus and can be an I/O Read, Configuration Read,
Memory Read, Memory Read Line, or Memory Read Multiple commands. As
mentioned earlier, once a request has been attempted on the destination bus, it must
continue to be repeated until it completes on the destination bus. Before it is attempted272

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on the destination bus the DRR is only a request and may be discarded at any time toprevent deadlock or improve performance, since the master must repeat the request later.
DWR - Delayed Write Request is a transaction that must complete on the destination bus
before completing on the originating bus and can be an I/O Write or Configuration Writecommand. Note: Memory Write and Memory Write and Invalidate commands must be
posted (PMW) and not be completed as DWR. As mentioned earlier, once a request has
been attempted on the destination bus, it must continue to be repeated until it completes.
Before it is attempted on the destination bus, the DWR is only a request and may bediscarded at any time to prevent deadlock or improve performance, since the mastermust repeat the request later.
DRC - Delayed Read Completion is a transaction that has completed on the destination
bus and is now moving toward the originating bus to complete. The DRC contains thedata requested by the master and the status of the target (normal, Master-Abort, TargetAbort, parity error, etc.).
DWC - Delayed Write Completion is a transaction that has completed on the destination
bus and is now moving toward the originating bus. The DWC does not contain the dataof the access, but only status of how it completed (Normal, Master-Abort, Target-Abort,parity error, etc.). The write data has been written to the specified target.
No - indicates that the subsequent transaction is not allowed to complete before theprevious transaction to preserve ordering in the system. The four No boxes found incolumn 2 prevent PMW data from being passed by other accesses and thereby maintain aconsistent view of data in the system.
Yes - indicates that the subsequent transaction must be allowed to complete before theprevious one or a deadlock can occur.
When blocking occurs, the PMW is required to pass the Delayed Transaction. If themaster continues attempting to complete Delayed Requests, it must be fair in attempting
to complete the PMW. There is no ordering violation when these subsequenttransactions complete before a prior transaction.
Yes/No - indicates that the bridge designer may choose to allow the subsequenttransaction to complete before the previous transaction or not. This is allowed since there
are no ordering requirements to meet or deadlocks to avoid. How a bridge designerchooses to implement these boxes may have a cost impact on the bridge implementationor performance impact on the system.

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Table E-1: Ordering Rules for a Bridge

Row pass Col.?

PMW(Col 2)

DRR(Col 3)DWR(Col 4)

DRC(Col 5)DWC(Col 6)PMW (Row 1)

No1

Yes5

Yes5

Yes7

Yes7

DRR (Row 2)

No2

Yes/NoYes/NoYes/NoYes/NoDWR (Row 3)

No3

Yes/NoYes/NoYes/NoYes/NoDRC (Row 4)

No4

Yes6

Yes6

Yes/NoYes/NoDWC (Row 5)

Yes/NoYes6

Yes6

Yes/NoYes/NoRule 1 - A subsequent PMW cannot pass a previously accepted PMW.
(Col 2, Row 1)
Posted Memory write transactions must complete in the order they arereceived. If the subsequent write is to the flag that covers the data, theConsumer may use stale data if write transactions are allowed to pass eachother.
Rule 2 - A read transaction must push posted write data to maintain ordering.
(Col 2, Row 2)
For example, a memory write to a location followed by an immediate
memory read of the same location returns the new value (refer to
Section 3.10, item 6, for possible exceptions). Therefore, a memory readcannot pass posted write data. An I/O read cannot pass a PMW, because theread may be ensuring the write data arrives at the final destination.
Rule 3 - A non-postable write transaction must push posted write data to maintainordering. (Col 2, Row 3)
A Delayed Write Request may be the flag that covers the data previously
written (PMW), and, therefore, the write flag cannot pass the data that it
potentially covers.
Rule 4 - A read transaction must pull write data back to the originating bus of theread transaction. (Col 2, Row 4)
For example, the read of a status register of the device writing data tomemory must not complete before the data is pulled back to the originatingbus; otherwise, stale data may be used.
Rule 5 - A Posted Memory Write must be allowed to pass a Delayed Request (reador write) to avoid deadlocks. (Col 3 and Col 4, Row 1)
A deadlock can occur when bridges that support Delayed Transactions areused with bridges that do not support Delayed Transactions. Referring to
Figure E-2, a deadlock can occur when Bridge Y (using Delayed
Transactions) is between Bridges X and Z (designed to a previous version ofthis specification and not using Delayed Transactions). Master 1 initiates aread to Target 1 that is forwarded through Bridge X and is queued as a
Delayed Request in Bridge Y. Master 3 initiates a read to Target 3 that is
forwarded through Bridge Z and is queued as a Delayed Request in Bridge

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Y. After Masters 1 and 3 are terminated with Retry, Masters 2 and 4 begin
memory write transactions of a long duration addressing Targets 2 and 4
respectively, which are posted in the write buffers of Bridges X and Z
respectively. When Bridge Y attempts to complete the read in either
direction, Bridges X and Z must flush their posted write buffers before
allowing the Read Request to pass through it.
If the posted write buffers of Bridges X and Z are larger than those of Bridge
Y, Bridge Y’s buffers will fill. If posted write data is not allowed to pass the
DRR, the system will deadlock. Bridge Y cannot discard the read request
since it has been attempted, and it cannot accept any more write data until
the read in the opposite direction is completed. Since this condition exists inboth directions, neither DRR can complete because the other is blocking thepath. Therefore, the PMW data is required to pass the DRR when the DRR
blocks forward progress of PMW data.
The same condition exists when a DWR sits at the head of both queues,
since some old bridges also require the posting buffers to be flushed on a
non-posted write cycle.
Rule 6 – A Delayed Completion (read or write) must be allowed to pass a Delayed
Request (read or write) to avoid deadlocks. (Cols 3 and 4, Rows 4 and 5)
A deadlock can occur when two bridges that support Delayed Transactions
are requesting accesses to each other. The common PCI bus segment is on
the secondary bus of Bridge A and the primary bus for Bridge B. If neither
bridge allows Delayed Completions to pass the Delayed Requests, neither
can make progress.
For example, suppose Bridge A’s request to Bridge B completes on Bridge
B’s secondary bus, and Bridge B’s request completes on Bridge A’s primarybus. Bridge A’s completion is now behind Bridge B’s request and Bridge
B’s completion is behind Bridge A’s request. If neither bridge allows
completions to pass the requests, then a deadlock occurs because neither
master can make progress.
Rule 7 - A Posted Memory Write must be allowed to pass a Delayed Completion(read or write) to avoid deadlocks. (Col 5 and Col 6, Row 1)
As in the example for Rule 5, another deadlock can occur in the system
configuration in Figure E-2. In this case, however, a DRC sits at the head of
the queues in both directions of Bridge Y at the same time. Again the oldbridges (X and Z) contain posted write data from another master. The
problem in this case, however, is that the read transaction cannot be repeateduntil all the posted write data is flushed out of the old bridge and the masteris allowed to repeat its original request. Eventually, the new bridge cannot
accept any more posted data because its internal buffers are full and it
cannot drain them until the DRC at the other end completes. When thiscondition exists in both directions, neither DRC can complete because theother is blocking the path. Therefore, the PMW data is required to pass the
DRC when the DRC blocks forward progress of PMW data.
The same condition exists when a DWC sits at the head of both queues.

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Transactions that have no ordering constraints
Some transactions enqueued as Delayed Requests or Delayed Completions have noordering relationship with any other Delayed Requests or Delayed Completions. The
designer can (for performance or cost reasons) allow or disallow Delayed Requests topass other Delayed Requests and Delayed Completions that were previously enqueued.
Delayed Requests can pass other Delayed Requests (Cols 3 and 4, Rows 2 and 3).
Since Delayed Requests have no ordering relationship with other Delayed
Requests, these four boxes are don’t cares.
Delayed Requests can pass Delayed Completions (Col 5 and 6, Rows 2 and 3).
Since Delayed Requests have no ordering relationship with Delayed
Completions, these four boxes are don’t cares.
Delayed Completions can pass other Delayed Completions (Col 5 and 6, Rows 4 and
5).
Since Delayed Completions have no ordering relationship with other Delayed
Completions, these four boxes are don’t cares.
Delayed Write Completions can pass posted memory writes or be blocked by them(Col 2, Row 5).
If the DWC is allowed to pass a PMW or if it remains in the same order,
there is no deadlock or data inconsistencies in either case. The DWC data
and the PMW data are moving in opposite directions, initiated by masters
residing on different buses accessing targets on different buses.

Target 1

Target 2

Master 3

Master 4

PCI Bus P
PCI-PCI

PCI-PCI

PCI-PCI

Bridge X

Bridge Y

Bridge Z(pre 2.1)(Rev. 2.1)

(pre 2.1)

PCI Bus N
Master 1

Master 2

Target 3

Target 4

Figure E-2: Example System with PCI-to-PCI Bridges

E.5. Delayed Transactions and LOCK#The bridge is required to support LOCK# when a transaction is initiated on its primarybus (and is using the lock protocol), but is not required to support LOCK# on
transactions that are initiated on its secondary bus. If a locked transaction is initiated on
the primary bus and the bridge is the target, the bridge must adhere to the lock semantics

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defined by this specification. The bridge is required to complete (push) all PMWs
(accepted from the primary bus) onto the secondary bus before attempting the lock on
the secondary bus. The bridge may discard any requests enqueued, allow the locked
transaction to pass the enqueued requests, or simply complete all enqueued transactions
before attempting the locked transaction on the secondary interface. Once a locked
transaction has been enqueued by the bridge, the bridge cannot accept any othertransaction from the primary interface until the lock has completed except for acontinuation of the lock itself by the lock master. Until the lock is established on thesecondary interface, the bridge is allowed to continue enqueuing transactions from thesecondary interface, but not the primary interface. Once lock has been established on thesecondary interface, the bridge cannot accept any posted write data moving toward theprimary interface until LOCK# has been released (FRAME# and LOCK# deasserted on
the same rising clock edge). (In the simplest implementation, the bridge does not accept
any other transactions in either direction once lock is established on the secondary bus,
except for locked transactions from the lock master.) The bridge must complete PMW,
DRC, and DWC transactions moving toward the primary bus before allowing the locked
access to complete on the originating bus. The preceding rules are sufficient for
deadlock free operation. However, an implementation may be more or less restrictive,
but, in all cases must ensure deadlock-free operation.

E.6. Error Conditions
A bridge is free to discard data or status of a transaction that was completed using
Delayed Transaction termination when the master has not repeated the request within 2 10
PCI clocks (about 30 µs at 33 MHz). However, it is recommended that the bridge notdiscard the transaction until 2 15 PCI clocks (about 983 µs at 33 MHz) after it acquired
the data or status. The shorter number is useful in a system where a master designed to aprevious version of this specification frequently fails to repeat a transaction exactly as
first requested. In this case, the bridge may be programmed to discard the abandoned
Delayed Completion early and allow other transactions to proceed. Normally, however,the bridge would wait the longer time, in case the repeat of the transaction is being
delayed by another bridge or bridges designed to a previous version of this specificationthat did not support Delayed Transactions.
When this timer (referred to as the Discard Timer) expires, the device is required todiscard the data; otherwise, a deadlock may occur.
Note: When the transaction is discarded, data may be destroyed. Thisoccurs when the discarded Delayed Completion is a read to a nonprefetchable region.
When the Discard Timer expires, the device may choose to report or ignore the error.
When the data is prefetchable, it is recommended that the device ignore the error sincesystem integrity is not affected. However, when the data is not prefetchable, it isrecommended that the device report the error to its device driver since system integrity isaffected. A bridge may assert SERR# since it typically does not have a device driver.

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Appendix F
Exclusive Accesses

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XVHIXOQHVVRIDKDUGZDUHEDVHGORFNPHFKDQLVPKDVGLPLQLVKHGDQGLVRQO\XVHIXOWR
SUHYHQWDGHDGORFNRUWRSURYLGHEDFNZDUGFRPSDWLELOLW\7KHUHIRUHDOORWKHUGHYLFHV
DUHUHTXLUHGWRLJQRUHLOCK#$KRVWEXVEULGJHFDQRQO\LQLWLDWHDQH[FOXVLYHDFFHVVWRSUHYHQWDGHDGORFNDVGHVFULEHG
LQ6HFWLRQLWHPRUWRSURYLGHEDFNZDUGFRPSDWLELOLW\WRDQH[SDQVLRQEXVEULGJH
WKDWVXSSRUWVH[FOXVLYHDFFHVV$KRVWEXVEULGJHFDQRQO\KRQRUDQH[FOXVLYHDFFHVVDVDWDUJHWZKHQSURYLGLQJFRPSDWLELOLW\WRDQDFFHVVLQLWLDWHGE\DQH[SDQVLRQEXVEULGJH
WKDWVXSSRUWVH[FOXVLYHDFFHVVHV 1RRWKHUDJHQWFDQLQLWLDWHDORFNHGDFFHVVWRWKH+RVW%XVEULGJH
$3&,WR3&,EULGJHLVRQO\DOORZHGWRSURSDJDWHDQH[FOXVLYHDFFHVVIURPLWVSULPDU\
EXVWRLWVVHFRQGDU\EXVDQGLVQHYHUDOORZHGWRLQLWLDWHDQH[FOXVLYHDFFHVVRILWVRZQ
LQLWLDWLYH$3&,WR3&,EULGJHLVUHTXLUHGWRLJQRUHLOCK#ZKHQDFWLQJDVDWDUJHWRQ
LWVVHFRQGDU\LQWHUIDFH
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EDFNZDUGFRPSDWLELOLW\7KLVPHDQVWKDWWKHH[SDQVLRQEXVVXSSRUWVDKDUGZDUHEDVHG
H[FOXVLYHDFFHVVPHFKDQLVP LH(,6$DQGQRW,6$ 7KHH[SDQVLRQEXVEULGJHFDQKRQRUDQH[FOXVLYHDFFHVVDVDWDUJHWZKHQVXSSRUWHGE\WKHH[SDQVLRQEXVRWKHUZLVH
LOCK#KDVQRPHDQLQJWRWKHEULGJH
7KHUHPDLQGHURIWKLVFKDSWHULVRQO\DSSOLFDEOHWRDGHYLFHWKDWLVDOORZHGWRVXSSRUW
LOCK#1RWHH[LVWLQJVRIWZDUHWKDWGRHVQRWVXSSRUWWKH3&,ORFNXVDJHUXOHVKDVWKH
SRWHQWLDORIQRWZRUNLQJFRUUHFWO\6RIWZDUHLVQRWDOORZHGWRXVHDQH[FOXVLYHDFFHVVWR
GHWHUPLQHLIDGHYLFHLVSUHVHQW

F.1. Exclusive Accesses on PCI
3&,SURYLGHVDQH[FOXVLYHDFFHVVPHFKDQLVPZKLFKDOORZVQRQH[FOXVLYHDFFHVVHVWR
SURFHHGLQWKHIDFHRIH[FOXVLYHDFFHVVHV7KLVDOORZVDPDVWHUWRKROGDKDUGZDUHORFN
DFURVVVHYHUDODFFHVVHVZLWKRXWLQWHUIHULQJZLWKQRQH[FOXVLYHGDWDWUDQVIHUVXFKDVUHDOWLPHYLGHREHWZHHQWZRGHYLFHVRQWKHVDPHEXVVHJPHQW7KHPHFKDQLVPLVEDVHGRQ
279

Revision 2.2

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FDOOHGDUHVRXUFHORFNLOCK#LQGLFDWHVZKHWKHUWKHPDVWHUGHVLUHVWKHFXUUHQWWUDQVDFWLRQWRFRPSOHWHDVDQ
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WKHEXVXQWLOLOCK#LVUHOHDVHG7KLVLVUHIHUUHGWRDVFRPSOHWHEXVORFNDQGLV
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 LOCK#PXVWEHUHOHDVHGLIWKHLQLWLDOWUDQVDFWLRQRIWKHORFNUHTXHVWLVWHUPLQDWHG
ZLWK5HWU\ /RFNZDVQRWHVWDEOLVKHG
 LOCK#PXVWEHUHOHDVHGZKHQHYHUDQDFFHVVLVWHUPLQDWHGE\7DUJHW$ERUWRU
0DVWHU$ERUW LOCK#PXVWEHGHDVVHUWHGEHWZHHQFRQVHFXWLYHORFNRSHUDWLRQVIRUDPLQLPXPRI
RQHFORFNZKLOHWKHEXVLVLQWKH,GOHVWDWH

57 In previous versions of this specification, a minimum of 16 bytes (naturally aligned) was considered thelock resource. A device was permitted to lock its entire memory address space. This definition still applies
for an upstream locked access to main memory. For downstream locked access, a resource is the PCI-toPCI bridge or the Expansion Bus bridge that is addressed by the locked operation.
58 For a SAC, this is the clock after the address phase. For a DAC, this occurs the clock after the first

address phase.
59 Once lock has been established, the master retains ownership of LOCK# when terminated with Retry or

Disconnect.
60 Consecutive refers to back-to-back locked operations and not a continuation of the current locked

operation.
280

Revision 2.2

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 7KHEULGJHLVQRWDOORZHGWRDFFHSWDQ\QHZUHTXHVWV IURPHLWKHULQWHUIDFH ZKLOHLW
LVLQDORFNHGFRQGLWLRQH[FHSWIURPWKHRZQHURILOCK#

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RILOCK#EHIRUHDVVHUWLQJREQ#7KHPDVWHUPDUNVLOCK#EXV\DQ\WLPHLOCK#LV
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WKHFXUUHQWWUDQVDFWLRQFRPSOHWHVDQGLVWKHRQO\DJHQWRQWKHEXVWKDWFDQGULYHLOCK#$OORWKHUDJHQWVPXVWQRWGULYHLOCK#HYHQZKHQWKH\DUHWKHFXUUHQWPDVWHU)LJXUH)LOOXVWUDWHVVWDUWLQJDQH[FOXVLYHDFFHVVLOCK#LVGHDVVHUWHGGXULQJWKH
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WKHILUVWDGGUHVVSKDVHZKLFKRFFXUVRQFORFNWRNHHSWKHWDUJHWLQWKHORFNHGVWDWH
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FXUUHQWWUDQVDFWLRQ

61 A locked operation is established when LOCK# is deasserted during the address phase, asserted thefollowing clock, and data is transferred during the current transaction.
281

Revision 2.2

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282

Revision 2.2$EULGJHDFWLQJDVDWDUJHWWKDWVXSSRUWVH[FOXVLYHDFFHVVHVPXVWVDPSOHLOCK#ZLWK
WKHDGGUHVVDQGRQDVXEVHTXHQWFORFN,IWKHEULGJHSHUIRUPVPHGLXPRUVORZGHFRGHLW
PXVWODWFKLOCK#GXULQJWKHILUVWDGGUHVVSKDVH2WKHUZLVHWKHEULGJHFDQQRW
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FORFNIROORZLQJWKHILUVWDGGUHVVSKDVHDQGLVIUHHWRUHVSRQGWRRWKHUUHTXHVWV

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LWVWDUWVDQRWKHUH[FOXVLYHDFFHVVWRWKHWDUJHWLWSUHYLRXVO\ORFNHGLOCK#LVGHDVVHUWHG
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WRWKHUHTXHVWLOCK#LVDVVHUWHGRQFORFNWRNHHSWKHWDUJHWLQWKHORFNHGVWDWHDQG
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CLK
1

2

3

4

5

FRAME#
ReleaseLOCK#ADContinue
ADDRESS

DATA

IRDY#
TRDY#
DEVSEL#)LJXUH)&RQWLQXLQJDQ([FOXVLYH$FFHVV

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LOCK#LVDVVHUWHGGXULQJWKHDGGUHVVSKDVHDQGLIWKHWDUJHWLVORFNHG IXOOORFNRU
WDUJHWORFN LWWHUPLQDWHVWKHWUDQVDFWLRQZLWK5HWU\DQGQRGDWDLVWUDQVIHUUHG

283

Revision 2.2

CLK
1

2

3

4

5

FRAME#(driven low by master holding lock)

LOCK#
AD

ADDRESS

DATA

IRDY#
TRDY#
STOP#

DEVSEL#)LJXUH)$FFHVVLQJD/RFNHG$JHQW

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GHDVVHUWHGZLWKWKHGHDVVHUWLRQRIIRDY#IROORZLQJWKHFRPSOHWLRQRIWKHODVWGDWDSKDVH
RIWKHORFNHGRSHUDWLRQ5HOHDVLQJLOCK# DWDQ\RWKHUWLPHPD\UHVXOWLQDVXEVHTXHQW
WUDQVDFWLRQEHLQJWHUPLQDWHGZLWK5HWU\XQQHFHVVDULO\$ORFNHGDJHQWXQORFNVLWVHOIZKHQHYHULOCK#DQGFRAME#DUHGHDVVHUWHG
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FRAME#DQGLOCK#DUHERWKGHDVVHUWHGRQWKHVDPHFORFN

F.7. Complete Bus Lock
7KH3&,UHVRXUFHORFNFDQEHFRQYHUWHGLQWRDFRPSOHWHEXVORFNE\KDYLQJWKHDUELWHU
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ORFNHGVHTXHQFHLVWHUPLQDWHGZLWK5HWU\WKHPDVWHUPXVWGHDVVHUWERWKREQ#DQG
LOCK#,IWKHILUVWDFFHVVFRPSOHWHVQRUPDOO\WKHFRPSOHWHEXVORFNKDVEHHQ
HVWDEOLVKHGDQGWKHDUELWHUZLOOQRWJUDQWWKHEXVWRDQ\RWKHUDJHQW,IWKHDUELWHUJUDQWHG
WKHEXVWRDQRWKHUDJHQWZKHQWKHFRPSOHWHEXVORFNZDVEHLQJHVWDEOLVKHGWKHDUELWHU
PXVWUHPRYHWKHRWKHUJUDQWWRHQVXUHWKDWFRPSOHWHEXVORFNVHPDQWLFVDUHREVHUYHG$FRPSOHWHEXVORFNPD\KDYHDVLJQLILFDQWLPSDFWRQWKHSHUIRUPDQFHRIWKHV\VWHPSDUWLFXODUO\WKHYLGHRVXEV\VWHP$OOQRQH[FOXVLYHDFFHVVHVZLOOQRWSURFHHGZKLOHD
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284

Revision 2.2

Appendix G
I/O Space Address
Decoding for Legacy Devices$IXQFWLRQWKDWVXSSRUWVD3&OHJDF\IXQFWLRQ ,'(9*$HWF LVDOORZHGWRFODLPWKRVH
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7KHVHDGGUHVVHVDUHQRWUHTXHVWHGXVLQJD%DVH$GGUHVVUHJLVWHUEXWDUHDVVLJQHGE\
LQLWLDOL]DWLRQVRIWZDUH,IDGHYLFHLGHQWLILHVLWVHOIDVDOHJDF\IXQFWLRQ FODVVFRGH WKH
LQLWLDOL]DWLRQVRIWZDUHJUDQWVWKHGHYLFHSHUPLVVLRQWRFODLPWKH,2OHJDF\DGGUHVVHVE\
VHWWLQJWKHGHYLFH¶V,26SDFHHQDEOHELW,IWKHGHYLFHGRHVQRWRZQDOOE\WHVZLWKLQD':25'RIDOHJDF\,2UDQJHLWLV
UHTXLUHGWRXVHAD[1::0]WRFRPSOHWHWKHGHFRGHEHIRUHFODLPLQJWKHDFFHVVE\DVVHUWLQJ
DEVSEL#,IDOHJDF\IXQFWLRQLVDGGUHVVHGE\DQ,2WUDQVDFWLRQEXWGRHVQRWRZQDOO
E\WHVEHLQJDFFHVVHGLQWKH':25'LWLVUHTXLUHGWRWHUPLQDWHWKHWUDQVDFWLRQZLWK
7DUJHW$ERUW$QH[SDQVLRQEXVEULGJHLVJUDQWHGDQH[FHSWLRQWRWKLVUHTXLUHPHQWZKHQSHUIRUPLQJVXEWUDFWLYHGHFRGH7KHEULGJHLVSHUPLWWHGWRDVVXPHWKDWDOOE\WHVZLWKLQ
WKH':25'EHLQJDGGUHVVHGUHVLGHRQWKHH[SDQVLRQEXV7KLVPHDQVWKDWWKHEULGJHLV
QRWUHTXLUHGWRFKHFNWKHHQFRGLQJRIAD[1::0]DQGWKHE\WHHQDEOHVEHIRUHSDVVLQJWKH
UHTXHVWWRWKHH[SDQVLRQEXVWRFRPSOHWH

285

Revision 2.2

286

Revision 2.2

Appendix H
Capability IDs

7KLVDSSHQGL[GHVFULEHVWKHFXUUHQW&DSDELOLW\,'V(DFKGHILQHGFDSDELOLW\PXVWKDYHD3&,6,*DVVLJQHG,'FRGH7KHVHFRGHVDUHDVVLJQHGDQGKDQGOHGPXFKOLNHWKH&ODVV&RGHV
6HFWLRQRIWKLVVSHFLILFDWLRQSURYLGHVDIXOOGHVFULSWLRQRIWKH([WHQGHG&DSDELOLWLHV/LVWIRU3&,GHYLFHV
7DEOH+&DSDELOLW\,'V
ID

Capability

0

Reserved

1

PCI Power Management Interface – This capability structure provides a
standard interface to control power management features in a PCI
device. It is fully documented in the PCI Power Management Interface
Specification. This document is available from the PCI SIG as
described in Chapter 1 of this specification.

2

AGP – This capability structure identifies a controller that is capable ofusing Accelerated Graphics Port features. Full documentation can befound in the Accelerated Graphics Port Interface Specification. This isavailable at http://www.agpforum.org.

3

VPD – This capability structure identifies a device that supports Vital
Product Data. Full documentation of this feature can be found in
Section 6.4. and Appendix I of this specification.

287

Revision 2.2

7DEOH+&DSDELOLW\,'V FRQWLQXHG
ID

288

Capability

4

6ORW,GHQWLILFDWLRQ–7KLVFDSDELOLW\VWUXFWXUHLGHQWLILHVDEULGJHWKDW
SURYLGHVH[WHUQDOH[SDQVLRQFDSDELOLWLHV)XOOGRFXPHQWDWLRQRIWKLVIHDWXUHFDQEHIRXQGLQWKH3&,WR3&,%ULGJH$UFKLWHFWXUH
6SHFLILFDWLRQ7KLVGRFXPHQWLVDYDLODEOHIURPWKH3&,6,*DV
GHVFULEHGLQ&KDSWHURIWKLVVSHFLILFDWLRQ

5

Message Signaled Interrupts – This capability VWUXFWXUHidentifies a PCI
function that can do message signaled interrupt delivery as defined in
Section 6.8. of this specification.

6

CompactPCI Hot Swap – This capability VWUXFWXUHprovides a standard
interface to control and sense status within a device that supports Hot
Swap insertion and extraction in a CompactPCI system. This capability
is documented in the CompactPCI Hot Swap Specification PICMG 2.1,
R1.0 available at http://www.picmg.org.

7-255

Reserved

Revision 2.2

Appendix I
Vital Product Data
9LWDO3URGXFW'DWD 93' LVLQIRUPDWLRQWKDWXQLTXHO\LGHQWLILHVKDUGZDUHDQG
SRWHQWLDOO\VRIWZDUHHOHPHQWVRIDV\VWHP7KH93'FDQSURYLGHWKHV\VWHPZLWK
LQIRUPDWLRQRQYDULRXV)LHOG5HSODFHDEOH8QLWVVXFKDVSDUWQXPEHUVHULDOQXPEHUDQG
RWKHUGHWDLOHGLQIRUPDWLRQ7KHREMHFWLYHIURPDV\VWHPSRLQWRIYLHZLVWRPDNHWKLV
LQIRUPDWLRQDYDLODEOHWRWKHV\VWHPRZQHUDQGVHUYLFHSHUVRQQHO6XSSRUWRI93'LV
RSWLRQDO
93'UHVLGHVLQDVWRUDJHGHYLFH IRUH[DPSOHDVHULDO((3520 LQD3&,GHYLFH$FFHVVWRWKH93'LVSURYLGHGXVLQJWKH&DSDELOLWLHV/LVWLQ&RQILJXUDWLRQ6SDFH7KH
93'FDSDELOLW\VWUXFWXUHKDVWKHIROORZLQJIRUPDW
31 30
F

16
VPD Address

15

8
Pointer to Next ID

70
ID = 03h

VPD Data)LJXUH,93'&DSDELOLW\6WUXFWXUH

5HJLVWHU)LHOG'HVFULSWLRQV
,'²&DSDELOLW\VWUXFWXUH,'KZKLFKLVDUHDGRQO\ILHOG
3RLQWHUWR1H[W,'²3RLQWHUWRWKHQH[WFDSDELOLW\VWUXFWXUHRUKLIWKLVLVWKHODVW
VWUXFWXUHLQWKH&DSDELOLW\/LVW7KLVLVDUHDGRQO\ILHOG
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LVUHDGZULWHDQGWKHLQLWLDOYDOXHDWSRZHUXSLVLQGHWHUPLQDWH
)²$IODJXVHGWRLQGLFDWHZKHQWKHWUDQVIHURIGDWDEHWZHHQWKH93''DWDUHJLVWHUDQG
WKHVWRUDJHFRPSRQHQWLVFRPSOHWHG7KHIODJUHJLVWHULVZULWWHQZKHQWKH93'$GGUHVVUHJLVWHULVZULWWHQ7RUHDG93'LQIRUPDWLRQD]HURLVZULWWHQWRWKHIODJUHJLVWHUZKHQ
WKHDGGUHVVLVZULWWHQWRWKH93'$GGUHVVUHJLVWHU7KHKDUGZDUHGHYLFHZLOOVHWWKHIODJ
WRDRQHZKHQE\WHVRIGDWDIURPWKHVWRUDJHFRPSRQHQWKDYHEHHQWUDQVIHUUHGWRWKH
93''DWDUHJLVWHU6RIWZDUHFDQPRQLWRUWKHIODJDQGDIWHULWLVVHWWRDRQHUHDGWKH
93'LQIRUPDWLRQIURPWKH93''DWDUHJLVWHU,IHLWKHUWKH93'$GGUHVVRU93''DWD
UHJLVWHULVZULWWHQSULRUWRWKHIODJELWEHLQJVHWWRDRQHWKHUHVXOWVRIWKHRULJLQDOUHDG
RSHUDWLRQDUHXQSUHGLFWDEOH7RZULWH93'LQIRUPDWLRQWRWKHUHDGZULWHSRUWLRQRIWKH
93'VSDFHZULWHWKHGDWDWRWKH93''DWDUHJLVWHU7KHQZULWHWKHDGGUHVVRIZKHUHWKH
93'GDWDLVWREHVWRUHGLQWRWKH93'$GGUHVVUHJLVWHUDQGZULWHWKHIODJELWWRDRQH DW
289

Revision 2.2

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93''DWD²93'GDWDFDQEHUHDGWKURXJKWKLVUHJLVWHU7KHOHDVWVLJQLILFDQWE\WHRIWKLVUHJLVWHU DWRIIVHWLQWKLVFDSDELOLW\VWUXFWXUH FRUUHVSRQGVWRWKHE\WHRI93'DWWKH
DGGUHVVVSHFLILHGE\WKH93'$GGUHVVUHJLVWHU7KHGDWDUHDGIURPRUZULWWHQWRWKLVUHJLVWHUXVHVWKHQRUPDO3&,E\WHWUDQVIHUFDSDELOLWLHV)RXUE\WHVDUHDOZD\VWUDQVIHUUHG
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DUHUHSURGXFHGLQWKHIROORZLQJILJXUHVOffsetField Name

Byte 0

Value = 0xxxxyyyb (Type = Small(0), Small Item Name = xxxx,
length = yy bytes

Bytes 1 to n

Actual information)LJXUH,6PDOO5HVRXUFH'DWD7\SH7DJ%LW'HILQLWLRQV

290

Revision 2.2

OffsetField Name

Byte 0

Value = 1xxxxxxxB (Type = Large(1), Large item name =xxxxxxx)

Byte 1

Length of data items bits[7:0] (lsb)

Byte 2

Length of data items bits[15:8] (msb)

Byte 3 to n

Actual data items)LJXUH,/DUJH5HVRXUFH'DWD7\SH7DJ%LW'HILQLWLRQV

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GHYLFH2QH93'5 [ WDJLVXVHGDVDKHDGHUIRUWKHUHDGRQO\NH\ZRUGVDQGRQH
93': [ WDJLVXVHGDVDKHDGHUIRUWKHUHDGZULWHNH\ZRUGV7KH93'5OLVW
LQFOXGLQJWDJDQGOHQJWK PXVWFKHFNVXPWR]HUR7KHVWRUDJHFRPSRQHQWFRQWDLQLQJ
WKHUHDGZULWHGDWDLVDQRQYRODWLOHGHYLFHWKDWZLOOUHWDLQWKHGDWDZKHQSRZHUHGRII
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WKH(QG7DJ [) $VPDOOH[DPSOHRIWKHUHVRXUFHGDWDW\SHWDJVXVHGLQDW\SLFDO
93'LVVKRZQLQ)LJXUH,

TAG

Identifier String

TAG

VPD-R list containing one or more VPD
keywords

TAG

VPD-W list containing one or more VPD
keywords

TAG

End Tag)LJXUH,5HVRXUFH'DWD7\SH)ODJVIRUD7\SLFDO93'

291

Revision 2.2

I.1. VPD Format,QIRUPDWLRQILHOGVZLWKLQD93'UHVRXUFHW\SHFRQVLVWRIDWKUHHE\WHKHDGHUIROORZHGE\
VRPHDPRXQWRIGDWD VHH)LJXUH, 7KHWKUHHE\WHKHDGHUFRQWDLQVDWZRE\WH
NH\ZRUGDQGDRQHE\WHOHQJWK$NH\ZRUGLVDWZRFKDUDFWHU $6&,, PQHPRQLFWKDWXQLTXHO\LGHQWLILHVWKHLQIRUPDWLRQ
LQWKHILHOG7KHODVWE\WHRIWKHKHDGHULVELQDU\DQGUHSUHVHQWVWKHOHQJWKYDOXH LQ
E\WHV RIWKHGDWDWKDWIROORZV
Keyword
Byte 0

Byte 1

LengthData

Byte 2Bytes 3 through n)LJXUH,93')RUPDW

93'NH\ZRUGVDUHOLVWHGLQWZRFDWHJRULHVUHDGRQO\ILHOGVDQGUHDGZULWHILHOGV
8QOHVVRWKHUZLVHQRWHGNH\ZRUGGDWDILHOGVDUHSURYLGHGDV$6&,,FKDUDFWHUV8VHRI$6&,,DOORZVNH\ZRUGGDWDWREHPRYHGDFURVVGLIIHUHQWHQWHUSULVHFRPSXWHUV\VWHPVZLWKRXWWUDQVODWLRQGLIILFXOW\$QH[DPSOHRIWKH³H[SDQVLRQERDUGVHULDOQXPEHU´93'
LWHPLVDVIROORZV.H\ZRUG

61/HQJWK

K

'DWD

³´

I.2. VPD Compatibility
2SWLRQDO93'ZDVVXSSRUWHGLQSULRUYHUVLRQVRIWKLVVSHFLILFDWLRQ)RULQIRUPDWLRQRQ
WKHSUHYLRXVGHILQLWLRQRI93'VHH3&,/RFDO%XV6SHFLILFDWLRQ5HYLVLRQ

I.3. VPD Definitions
7KLVVHFWLRQGHVFULEHVWKHFXUUHQW93'ODUJHDQGVPDOOUHVRXUFHGDWDWDJVSOXVWKH93'
NH\ZRUGV7KLVOLVWPD\EHHQKDQFHGDWDQ\WLPH&RPSDQLHVZLVKLQJWRGHILQHDQHZ
NH\ZRUGVKRXOGFRQWDFWWKH3&,6,*$OOXQVSHFLILHGYDOXHVDUHUHVHUYHGIRU6,*
DVVLJQPHQW

292

Revision 2.2

I.3.1. VPD Large and Small Resource Data Tags
93'LVFRQWDLQHGLQIRXUW\SHVRI/DUJHDQG6PDOO5HVRXUFH'DWD7DJV7KHIROORZLQJ
WDJVDQG93'NH\ZRUGILHOGVPD\EHSURYLGHGLQ3&,GHYLFHVLarge resource type Identifier
String Tag(0x2)

This tag is the first item in the VPD storage
component. It contains the name of the board inalphanumeric characters.

Large resource type VPD-R
Tag(0x10)

This tag contains the read only VPD keywords for aboard.

Large resource type VPD-W
Tag(0x11)

This tag contains the read/write VPD keywords forthe board.

Small resource type End Tag(0xF)

This tag identifies the end of VPD in the storage
component.

I.3.1.1. Read-Only Fields
PN

Board Part NumberThis keyword is provided as an extension to theDevice ID (or Subsystem ID) in the Configuration
Space header in Figure 6-1.

ECEC Level of the Board

The characters are alphanumeric and represent theengineering change level for this board.

MN

Manufacture ID

This keyword is provided as an extension to the
Vendor ID (or Subsystem Vendor ID) in the
Configuration Space header in Figure 6-1. This
allows vendors the flexibility to identify anadditional level of detail pertaining to the sourcing of
this device.

SN

Serial Number

The characters are alphanumeric and represent theunique board Serial Number.

Vx

Vendor SpecificThis is a vendor specific item and the characters arealphanumeric. The second character (x) of the
keyword can be 0 through Z.

293

Revision 2.2

CP

Extended Capability

This field allows a new capability to be identified inthe VPD area. Since dynamic control/status cannot
be placed in VPD, the data for this field identifies
where, in the device’s memory or I/O address space,
the control/status registers for the capability can befound. Location of the control/status registers is
identified by providing the index (a value between 0
and 5) of the Base Address register that defines theaddress range that contains the registers, and theoffset within that Base Address register range where
the control/status registers reside. The data area forthis field is four bytes long. The first byte contains
the ID of the extended capability. The second byte
contains the index (zero based) of the Base Address
register used. The next two bytes contain the offset(in little endian order) within that address range
where the control/status registers defined for thatcapability reside.

RV

Checksum andReserved

The first byte of this item is a checksum byte. The
checksum is correct if the sum of all bytes in VPD(from VPD address 0 up to and including this byte)
is zero. The remainder of this item is reserved space(as needed) to identify the last byte of read-only
space. The read-write area does not have achecksum. This field is required.

I.3.1.2 Read/Write Fields

294

Vx

Vendor SpecificThis is a vendor specific item and the characters
are alphanumeric. The second character (x) of
the keyword can be 0 through Z.

Yx

System SpecificThis is a system specific item and the characters
are alphanumeric. The second character (x) of
the keyword can be 0 through 9 and B throughZ.

YA

Asset Tag IdentifierThis is a system specific item and the characters
are alphanumeric. This keyword contains thesystem asset identifier provided by the systemowner.

RW

Remaining Read/Write
Area

This descriptor is used to identify the unused
portion of the read/write space. The productvendor initializes this parameter based on thesize of the read/write space or the spaceremaining following the Vx VPD items. One ormore of the Vx, Yx, and RW items are required.

Revision 2.2

I.3.2. VPD Example
The following is an example of a typical VPD.

Offset

Item

Value

0

Large Resource Type ID String Tag(0x02)

0x82 “Product Name”

1

Length

0x0021

3

Data“ABCD Super-Fast
Widget Controller”

36

Large Resource Type VPD-R Tag (0x10)

0x90

37

Length

0x005939

VPD Keyword

“PN”

41

Length

0x08

42

Data

“6181682A”

50

VPD Keyword

“EC”

52

Length

0x0A

53

Data

“4950262536”

63

VPD Keyword

“SN”

65

Length

0x08

66

Data

“00000194”

74

VPD Keyword

“MN”

76

Length

0x04

77

Data

“1037”81

VPD Keyword

“RV”

83

Length

0x2C

84

Data

Checksum85

Data

Reserved (0x00)

295

Revision 2.2

296

Offset

Item

Value

128

Large Resource Type VPD-W Tag (0x11)

0x91

129

Length0x007E131

VPD Keyword

“V1”

133

Length

0x05

134

Data

“65A01”139

VPD Keyword

“Y1”

141

Length

0x0D

142

Data

“Error Code 26”

155

VPD Keyword

“RW”

157

Length

0x61

158

Data

Reserved (0x00)

255

Small Resource Type End Tag (0xF)

0x78

Revision 2.2

Glossary
64-bit extension

A group of PCI signals that support a 64-bit data path.

Address Spaces

A reference to the three separate physical address
regions of PCI: Memory, I/O, and Configuration.

agent

An entity that operates on a computer bus.

arbitration latency

The time that the master waits after having asserted
REQ# until it receives GNT#, and the bus returns to
the idle state after the previous master’s transaction.

backplate

The metal plate used to fasten an expansion board to
the system chassis.

BIST register

An optional register in the header region used forcontrol and status of built-in self tests.

bridgeThe logic that connects one computer bus to another,allowing an agent on one bus to access an agent on
the other.

burst transfer

The basic bus transfer mechanism of PCI. A burst iscomprised of an address phase and one or more dataphases.

bus commands

Signals used to indicate to a target the type oftransaction the master is requesting.

bus device

A bus device can be either a bus master or target:

catastrophic error•

master -- drives the address phase and transaction
boundary (FRAME#). The master initiates atransaction and drives data handshaking (IRDY#)
with the target.

•

target -- claims the transaction by asserting
DEVSEL# and handshakes the transaction(TRDY#) with the initiator.

An error that affects the integrity of system operationsuch as a detected address parity error or an invalid
PWR_GOOD signal.

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central resources

Bus support functions supplied by the host system,
typically in a PCI compliant bridge or standard
chipset.

commandSee bus command.

Configuration Address SpaceA set of 64 registers (DWORDs) used for
configuration, initialization, and catastrophic error
handling. This address space consists of two regions:a header region and a device-dependent region.

configuration transaction

Bus transaction used for system initialization andconfiguration via the configuration address space.

DAC

Dual address cycle. A PCI transaction where a 64-bit
address is transferred across a 32-bit data path in twoclock cycles. See also SAC.

deadlock

When two devices (one a master, the other a target)
require the other device to respond first during asingle bus transaction. For example, a masterrequires the addressed target to assert TRDY# on awrite transaction before the master will assert IRDY#.
(This behavior is a violation of this specification.)

Delayed Transaction

The process of a target latching a request andcompleting it after the master was terminated with
Retry.

deviceSee PCI device.

device dependent region

The last 48 DWORDS of the PCI configuration space.
The contents of this region are not described in thisdocument.

Discard Timer

When this timer expires, a device is permitted todiscard unclaimed Delayed Completions (refer to
Section 3.3.3.3.3. and Appendix E).

DWORD

A 32-bit block of data.

EISA

Extended Industry Standard Architecture expansion
bus, based on the IBM PC AT bus, but extended to 32
bits of address and data.

expansion board

A circuit board that plugs into a motherboard andprovides added functionality.

expansion bus bridge

A bridge that has PCI as its primary interface and
ISA, EISA, or Micro Channel as its secondaryinterface. This specification does not preclude the useof bridges to other buses, although deadlock and othersystem issues for those buses have not been
considered.

Function

A set of logic that is represented by a single
Configuration Space.

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header region

The first 16 DWORDS of a device’s Configuration
Space. The header region consists of fields thatuniquely identify a PCI device and allow the device tobe generically controlled.
See also device dependent region.

hidden arbitration

Arbitration that occurs during a previous access sothat no PCI bus cycles are consumed by arbitration,
except when the bus is idle.

host bus bridge

A low latency path through which the processor may
directly access PCI devices mapped anywhere in thememory, I/O, or configuration address spaces.

Idle state

Any clock period that the bus is idle (FRAME# and
IRDY# deasserted).

Initialization Time

The period of time that begins when RST# is25
deasserted and completes 2 PCI clocks later.

ISA

Industry Standard Architecture expansion bus built
into the IBM PC AT computer.

keepers

Pullup resistors or active components that are onlyused to sustain a signal state.

latency

See arbitration latency, master data latency, target
initial latency, and target subsequent latency.

Latency Timer

A mechanism for ensuring that a bus master does notextend the access latency of other masters beyond a
specified value.

masterAn agent that initiates a bus transaction.

Master-Abort

A termination mechanism that allows a master toterminate a transaction when no target responds.

master data latency

The number of PCI clocks until IRDY# is asserted
from FRAME# being asserted for the first data phaseor from the end of the previous data phase.

MC

The Micro Channel architecture expansion bus asdefined by IBM for its PS/2 line of personal
computers.

motherboard

A circuit board containing the basic functions (e.g.,CPU, memory, I/O, and expansion connectors) of acomputer.

multi-function device

A device that implements from two to eight functions.
Each function has its own Configuration Space that isaddressed by a different encoding of AD[10::08]
during the address phase of a configurationtransaction.

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multi-master device

A single-function device that contains more than one
source of bus master activity. For example, a device
that has a receiver and transmitter that operate
independently.

NMI

Non-maskable interrupt.

operation

A logical sequence of transactions, e.g., Lock.

output driver

An electrical drive element (transistor) for a single
signal on a PCI device.

PCI connector

An expansion connector that conforms to theelectrical and mechanical requirements of the PCI
local bus standard.

PCI device

A device that (electrical component) conforms to the
PCI specification for operation in a PCI local bus
environment.

PGA

Pin grid array component package.

phase

One or more clocks in which a single unit of
information is transferred, consisting of:•an address phase (a single address transfer in one
clock for a single address cycle and two clocks
for a dual address cycle)•

a data phase (one transfer state plus zero or morewait states)

positive decoding

A method of address decoding in which a device
responds to accesses only within an assigned address
range. See also subtractive decoding.

POST

Power-on self test. A series of diagnostic routines
performed when a system is powered up.

pullupsResistors used to insure that signals maintain stablevalues when no agent is actively driving the bus.

run time

The time that follows Initialization Time.

SAC

Single address cycle. A PCI transaction where a
32-bit address is transferred across a 32-bit data pathin a single clock cycle. See also DAC.

shared slot

An arrangement on a PCI motherboard that allows a
PCI connector to share the system bus slot nearest the
PCI bus layout with an ISA, EISA, or MC bus
connector. In an MC system, for example, the sharedslot can accommodate either an MC expansion board
or a PCI expansion board.

single-function device

A device that contains only one function.

sideband signals

Any signal not part of the PCI specification thatconnects two or more PCI-compliant agents and hasmeaning only to those agents.

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Special Cycle

A message broadcast mechanism used forcommunicating processor status and/or (optionally)
logical sideband signaling between PCI agents.

stale data

Data in a cache-based system that is no longer validand, therefore, must be discarded.

stepping

The ability of an agent to spread assertion of qualified
signals over several clocks.

subtractive decoding

A method of address decoding in which a device
accepts all accesses not positively decoded by anotheragent. See also positive decoding.

targetAn agent that responds (with a positive
acknowledgment by asserting DEVSEL#) to a bus
transaction initiated by a master.

Target-Abort

A termination mechanism that allows a target toterminate a transaction in which a fatal error has
occurred, or to which the target will never be able torespond.

target initial latency

The number of PCI clocks that the target takes toassert TRDY# for the first data transfer.

target subsequent latency

The number of PCI clocks that the target takes toassert TRDY# from the end of the previous dataphase of a burst.

termination

A transaction termination brings bus transactions toan orderly and systematic conclusion. Alltransactions are concluded when FRAME# and
IRDY# are deasserted (an idle cycle). Termination
may be initiated by the master or the target.

transaction

An address phase plus one or more data phases.

turnaround cycle

A bus cycle used to prevent contention when one
agent stops driving a signal and another agent begins
driving it. A turnaround cycle must last one clock
and is required on all signals that may be driven bymore than one agent.

wait state

A bus clock in which no transfer occurs.

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