IEICE TRANS. ELECTRON., VOL.E94–C, NO.6 JUNE 2011

985

PAPER

Special Section on Analog Circuits and Related SoC Integration Technologies

0.6 V Voltage Shifter and Clocked Comparator for Sampling
Correlation-Based Impulse Radio UWB Receiver
Lechang LIU†a) , Nonmember, Takayasu SAKURAI† , Fellow, and Makoto TAKAMIYA† , Member

SUMMARY
A 0.6-V voltage shifter and a 0.6-V clocked comparator are presented for sampling correlation-based impulse radio UWB receiver. The voltage shifter is used for a novel split swing level schemebased CMOS transmission gate which can reduce the power consumption by four times. Compared to the conventional voltage shifter, the proposed voltage shifter can reduce the required capacitance area by half andeliminate the non-overlapping complementary clock generator. The proposed 0.6-V clocked comparator can operate at 100-MHz clock with thevoltage shifter. To reduce the power consumption of the conventional
continuous-time comparator based synchronization control unit, a novel
clocked-comparator based control unit is presented, thereby achieving thelowest energy consumption of 3.9 pJ/bit in the correlation-based UWB receiver with the 0.5 ns timing step for data synchronization.
key words: impulse radio ultra-wideband (IR-UWB), voltage shifter,
clocked comparator, low voltage

1.

Introduction

The market and the need to develop eﬃcient electronicequipment have pushed the industry to design circuits withvery low power supply voltage, and also often constrained
to low power consumption. This work targets to develop
a 0.6 V voltage shifter and a 0.6 V clocked comparator forthe multi-phase sampling application, such as correlationbased ultra-wideband (UWB) receiver or analog-to-digitalconverter (ADC). As an application example, the proposed
voltage shifter and the clocked comparator are used for theimpulse radio UWB receiver.
Impulse radio UWB refers to a radio technology fortransmitting information by means of extremely short duration pulses without radio frequency modulation. Ideal targets for IR-UWB system are low power, low cost, high data
rates, and extremely low interference, which makes it an attractive option for ad hoc and sensor network where groupsof wireless terminals are located in a limited area and communicate in an infrastructure-free fashion without any central coordinating unit or base-station.
Conventional impulse UWB transceivers usually require 1.2 V supply voltage or above [1]–[3]. However, inthe single solar cell powered ad hoc and sensor network,
the maximum available supply voltage is less than 0.6 V. To
make the existing circuits to operate at 0.6 V supply voltage,a 0.6 V to 1.2 V DC-DC converter is often used. To reduce
the DC-DC converter output power in this work, a 0.6 V
Manuscript received October 13, 2010.
Manuscript revised January 17, 2011.
†
The authors are with Institute of Industrial Science, The University of Tokyo, Tokyo, 153-8505 Japan.
a) E-mail: llch@iis.u-tokyo.ac.jp
DOI: 10.1587/transele.E94.C.985

Fig. 1 Block diagram of impulse radio UWB receiver. 0.6-V voltage
shifter supplies boosted voltage to charge-domain correlator and comparator.

voltage shifter and a 0.6 V clocked comparator are proposed
for the correlation-based IR-UWB receiver [4]. Figure 1
shows block diagram of the proposed receiver. To verify
the performance of the 0.6 V voltage shifter and the 0.6 V
comparator, a novel synchronization control unit is also implemented in the same chip with the sampling clock generator. 1.2 V supply voltage for the synchronization control unit
and the sampling clock generator are provided by a 0.6 V to
1.2 V DC-DC converter. The DC-DC converter is not implemented in this work.
Section 2 shows the switching driving problem in theconventional charge-domain sampling correlator. Section 3
presents the circuit implementations of the voltage shifter.
The 0.6 V voltage comparator is described in Sect. 4 andsynchronization scheme is described in Sect. 5. Experimental results are presented in Sect. 6 and Sect. 7 concludes thepaper.
2.

Split Swing Level Scheme for CMOS Transmission
Gates

Figure 2 shows the circuit schematic of the charge-domain
sampling correlator used in the UWB receiver [2]. Correlation operation is achieved in two steps. First the switches
controlled by clocks φ1 , φ2 . . . φ7 are turned on sequentiallyand the incoming signal is sampled and stored to the corresponding capacitors respectively, then the stored voltages
are weighted summed and averaged by turning on all theφr controlled switches. After summing and averaging, thecorrelator output is reset to 0.6 V by clock (φr ).
The sampling correlator circuits make use of two basic
building blocks, namely the capacitor and the switch. Lowering the supply voltage of the correlator has implications

c 2011 The Institute of Electronics, Information and Communication Engineers
Copyright IEICE TRANS. ELECTRON., VOL.E94–C, NO.6 JUNE 2011

986

Fig. 2

Fig. 3Charge-domain sampling correlator.

Split swing level scheme for CMOS transmission gate.

on the operation of some building blocks. The functional
property of a capacitor, namely its capacitance, is in factindependent of the supply voltage. The most problematic
issue in low voltage sampling correlator design is the switch
driving problem. One eﬀective way to cope with the low
supply is to apply voltage shifting. This technique uses circuits which convert the voltage from the available supply toanother one.
Figure 3 shows the proposed split swing level schemebased CMOS transmission gate. The DC level of the incoming signal is 0.6 V and the peak-to-peak voltage is around
40 mV. Because the thresholds of NMOS and PMOS are
higher than 0.4 V, the 0∼0.6 V inputs are used to drive the
PMOS and the 0.6∼1.2 V outputs of the voltage shifters
are directly used to drive the NMOS without converting to0∼1.2 V full swing level. This split swing level scheme canreduce the power consumption of the CMOS transmission
gates by four times due to the P ∝ CV 2 relationship.
3.

Voltage ShifterFig. 4 Conventional voltage shifter [6]. (a) Circuit schematic and wavec 2010
forms. (b) Non-overlapping complementary clock generator (IEEE).

Fig. 5 Simplified circuit schematic of the proposed voltage shifter for thec 2010 IEEE).
sampling correlator (overlapping clock. The amount of separation is set by thedelay through the NAND gate and the two inverters on
the NAND gate output. When driving a large capacitance,
where the rise time of the signals can be significant, a large
number of inverters are required as part of the delay which
will dominate the power consumption of the voltage booster.

3.1 Conventional Voltage Shifter

3.2 Proposed Voltage Shifter

Various circuits have been proposed and used in literature
to implement voltage boost. Originally monolithic boosted
voltage generators stem from non-volatile memory circuits
where a relatively high potential is needed to write orerase information [5]. A conventional voltage booster from
DRAM applications is found in [6] and shown in Fig. 4(a).
The key feature of this voltage booster is to use feedback
technique to obtain a boosted voltage of 2VDD even at low
operating voltage. When one clock is high, the bootstrapped
voltage is high enough to turn on the other NMOS, whichcharges the other capacitor to VDD . In the next phase theroles are exchanged. This feedback technique can eliminate
a voltage loss due to a threshold voltage of MOSFET.
The required clock signals used in the conventional
voltage booster can be generated by the non-overlapping
complementary clock generator show in Fig. 4(b). This circuit takes a clock signal and generates a two-phase non-In the sampling correlator, the complementary clock signals
are not required. If the conventional voltage boosters are
directly used to generate the 20-phase sampling clocks forthe correlator in Fig. 1, half of chip area and power dissipation of the voltage shifters will be wasted due to the complementary clock signals. To overcome this problem, theproposed voltage shifter for the multi-phase sampling correlator is shown in Fig. 5. The non-overlapping requirementon the adjacent input signals can be satisfied by swapping
the clocks ϕ1 , ϕ2 , ϕ3 , ϕ4 , ϕ5 , ϕ6 to ϕ1 , ϕ4 , ϕ2 , ϕ5 , ϕ3 , ϕ6 thus
eliminating the non-overlapping complementary clock generator. When driving a large capacitance, power consumption of the voltage shifter will be increased but the numbersof the required transistors and the control clocks are reducedby half and thus the power consumption can be also reducedby half. The voltage shifter outputs φ1 , φ2 . . . φ6 are used todrive the switches in Fig. 2 correspondingly.

LIU et al.: 0.6 V VOLTAGE SHIFTER AND CLOCKED COMPARATOR

987

4.

Clocked Comparator

Comparators are used for synchronization control and data
decision in the proposed UWB receiver as shown in Fig. 1.
For 0.6-V supply voltage, it doesn’t suﬃce to force an existing circuit to operate at 100-MHz clock. It requires thedevelopment of dedicated circuits.
4.1 Conventional Clocked Comparator
Figure 6 shows the circuit schematic and the simulated
waveforms of the conventional clocked comparator [7] at
1.2-V power supply voltage. The reset is done to the metastable state and the regeneration is satisfied by two MOS
inverters in positive feedback configuration. When clock islow, the drains of the two inverters (O1 , O2 ) are charged toVcor or Vref (creating an imbalance). When clock goes high,the imbalance causes the circuit latch high or low dependingon the state of the inputs. This comparator doesn’t consume
DC power in reset mode but it fails to operate at 100 MHz
clock when the supply voltage is reduced to 0.6 V.

4.2 Proposed Clocked Comparator
To make the conventional clocked comparator operate at
100 MHz with 0.6 V supply voltage, in the proposed comparator, supply voltage is doubled from 0.6 V to 1.2 V
when clock goes high. Figure 7 shows the complete circuit schematic of the proposed voltage shifter for both thesampling correlator and the clocked comparator where φ1 ,φ2 , . . . , φ6 are used for the sampling clock of the correlator and φcmp is used for the supply voltage of the comparator. Figure 8 shows the circuit schematic and the simulated waveforms of the proposed comparator. The proposed
clocked comparator operates with 100-MHz clock at a 0.6-V
power supply voltage. When φclk is low, the circuit outputs

Fig. 7 Complete circuit schematic of the proposed voltage shifter forc 2010 IEEE)
both the sampling correlator and the clocked comparator. (Fig. 6 Conventional clocked comparator [7]. (a) Circuit schematic. (b)c 2010 IEEE)
Waveforms. (Fig. 8 Proposed clocked comparator. (a) Circuit schematic.
c 2010 IEEE)(b) Waveforms. (IEICE TRANS. ELECTRON., VOL.E94–C, NO.6 JUNE 2011988

are not valid logic signals but rather, ideally, track the input
signals. This form of the latch has the advantage of lower
power dissipation because no current is flowing when thelatch is in reset mode.
5.

Synchronization Scheme

1.2 V Supply voltage for the synchronization control unit isprovided by a 0.6 V to 1.2 V DC-DC converter. One of theadvantages of the proposed clocked comparator is that theoutput swings from 0 to 1.2 V which can be used for the synchronization control unit directly without additional level
shifter. The operation principle of the sliding scheme fordata synchronization is shown in Fig. 9(a). Before synchronization is achieved, the incoming signal lags the templateof the correlator by ΔT . Sliding scheme can slide the timing
error ΔT towards zero at the step of 0.5 ns. Conventionallythe control unit for sliding scheme is implemented by tapped
delay-lines [8]. However, the delay-lines not only consume
additional power but also have uncertainty due to the variation of process, voltage, and temperature across large dies.
In the proposed discrete-time receiver, the sliding control
unit can be embedded to the charge-domain correlator seamlessly by utilizing the 2 GHz clock for the sampling correlator.
To reduce the power consumption of the continuoustime comparator based sliding control unit in [2], anovel clocked-comparator based control unit is proposed
in Fig. 9(b). The continuous-time comparator in [2] always consumes power when signals come while the clocked
comparator doesn’t consume power in reset mode and thus
power consumption can be reduced. This control unit is
implemented by preprocessing the clock signal CLK. The
gated inverter which drives the divide-by-five frequency divider is transparent to “0” but not transparent to “1”. Whenthe timing mismatch ΔT between the incoming signal andthe template of the correlator is larger than 0.5 ns, the autocorrelation result Vcor is lower than the threshold of the following comparators. In this case, both UP and DN are generated and thus the clock removal signal RM is generated.
This clock removal pulse will block the propagation of the
input clock by one period. With the one-period delay, thephase of the sampling clock slides by 0.5 ns and the period of the sampling clock is increased from 10 ns to 10.5 ns.
When the timing mismatch ΔT between the incoming signal and the template of the correlator is less than 0.5 ns, theauto-correlation result Vcor is large enough to be detectedby the comparators. In this case, either UP or DN is generated and RM is not generated, which keeps the period of
the sampling clock 10 ns. The 20-phase sampling clock isgenerated by combining the output edges of the divide-by-5
divider and the divide-by-4 divider.
Figure 10 shows the timing chart of the whole synchronization process. In the worst case the data synchronization can be finished within 19 phase slides because theperiod of input signal is 10 ns and diﬀers with the periodof the sampling clock by 0.5 ns. Before synchronization isFig. 9 Sliding scheme for data synchronization. (a) Operation principle.
(b) Circuit implementation.

Fig. 10

Timing chart of sliding scheme for data synchronization.

achieved, there is no output in the receiver and thus it cannot
be used for data communication. After the synchronizationis achieved, the sampling clock period returns to 10 ns andit can be used for communication.
6.

Measurement Results

The proposed UWB receiver without the front-end amplifier
was designed and fabricated in 1.2 V 65 nm CMOS process.

LIU et al.: 0.6 V VOLTAGE SHIFTER AND CLOCKED COMPARATOR

989
Table 1

Fig. 11

Performance summary. (w/o front-end amp.)

c 2010 IEEE)
Chip micrograph and layout of UWB receiver. (Fig. 13 Comparison with state-of-the-art correlation-based UWB receivers. (Reference and CMOS process technology are shown. [1], [2] arewithout front-end amp. [8]–[13] are with front-end amp.)

Fig. 12 Measurement results of UWB receiver. (a) Sliding scheme forc 2010timing alignment. (b) Measured waveforms in synchronization. (IEEE)

The chip micrograph and layout are shown in Fig. 11. To
verify the performance of the proposed 0.6 V voltage shifterand the 0.6 V clocked comparator, the 1.2 V level outputsof the clock generator are down-shifted to 0.6 V for the input in Fig. 1. Figure 12(a) shows the measured waveforms
before synchronization is achieved, where Vin is the incoming UWB pulse, CLK is the 2 GHz input clock, φ6 is thesixth sampling clock and OUT is the output data. Before
synchronization is achieved, due to the clock-swallow slid-

ing scheme, for every incoming UWB pulse one input clockis swallowed and the period of the sampling clock generator output is increased to 10.5 ns which corresponds tothe frequency 95.2 MHz. Figure 12(b) shows the measured
waveforms when synchronization is achieved. Because thesliding scheme for timing alignment is inactivated, the frequency of the sampling clock returns to 100 MHz and theUWB receiver receives 100-Mbps data correctly.
The receiver performance is summarized in Table 1.
Compared to the conventional 1.8 V UWB receiver [2],the total power consumption is reduced from 1.28 mW to
0.39 mW where 0.72 mW power reduction is caused by process technology and 0.17 mW power reduction is caused bycircuit topology. The power consumption of the correlator
and the comparators is reduced by 93% (from 0.75 mW to
0.05 mW) by reducing the power supply voltage from 1.8 V
to 0.6 V. The performance comparison with the state-of-theart correlation-based IR-UWB receivers is shown in Fig. 13.
The proposed UWB receiver with the 0.6-V voltage shifterand the 0.6-V clocked comparator achieves the lowest energy consumption of 3.9 pJ/bit in the correlation-based IRUWB receivers with the 0.5 ns timing step for data synchronization.
7.

Conclusions

This paper presents a 0.6-V voltage shifter and a 0.6-V

IEICE TRANS. ELECTRON., VOL.E94–C, NO.6 JUNE 2011990

clocked comparator in 65 nm CMOS. For the multi-phasesampling application, such as charge-domain correlator for
impulse UWB receivers or analog-to-digital converter, theproposed voltage shifter can reduce the power consumption
and the chip area by half compared to the conventional one.
The non-overlapping complementary clock generator usedin the conventional voltage shifter can be eliminated by simply swapping the input clock order in the voltage shifter.
The proposed 0.6-V clocked comparator can operate at 100MHz clock with the proposed voltage shifter. Compared tothe conventional 1.8 V UWB receiver [2], the power consumption of the correlator and the comparators is reduced
by 93% by reducing the power supply voltage from 1.8 V to
0.6 V.
Acknowledgments
This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy and Industrial Technology Development Organization (NEDO).
References[1] L. Liu, T. Sakurai, and M. Takamiya, “A charge-domain auto- andcross-correlation based IR-UWB receiver with power- and areaeﬃcient PLL for 62.5 ps step data synchronization in 65 nm CMOS,”IEEE Symposium on VLSI Circuits, pp.27–28, June 2010.
[2] L. Liu, T. Sakurai, and M. Takamiya, “A 1.28 mW 100 Mb/s impulse
UWB receiver with charge-domain correlator and embedded sliding
scheme for data synchronization,” IEEE Symposium on VLSI Circuits, pp.146–147, June 2009.
[3] Y. Zheng, Y. Tong, C.W. Ang, Y. Xu, and W.G. Yeoh, “A CMOS
carrier-less UWB transceiver for WPAN applications,” ISSCC Dig.
Tech. Papers, pp.116–117, Feb. 2006.
[4] L. Liu, T. Sakurai, and M. Takamiya, “0.6 V voltage shifter andclocked comparator for correlation-based impulse radio UWB receiver in 65 nm CMOS,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.301–304, Nov. 2010.
[5] J, Dickson, “On-chip high-voltage generation in NMOS integrated
circuits using an improved voltage multiplier technique,” IEEE J.
Solid-State Circuits, vol.SC-11, no.3, pp.374–378, 1976.
[6] Y. Nakagome, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T.
Kaga, Y. Kawamoto, F. Murai, R. Izawa, D. Hisamoto, T. Kisu, T.
Nishida, E. Takeda, and K. Itoh, “An experimental 1.5-V 64-Mb
DRAM,” IEEE J. Solid-State Circuits, vol.26, no.4, pp.465–472,
1991.
[7] P.E. Allen and D.R. Holberg, CMOS analog circuit design, Second
ed., Oxford University Press, 2002.
[8] T. Terada, S. Yoshizumi, M. Muqsith, Y. Sanada, and T. Kuroda,“A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data
communications and 2.5-cm range finding,” IEEE J. Solid-State Circuits, vol.41, no.4, pp.891–898, 2006.
[9] I.D. O’Donnell and R.W. Brodersen, “A 2.3 mW baseband impulseUWB transceiver front-end in CMOS,” IEEE Symposium on VLSI
Circuits, June 2006.
[10] F.S. Lee and A.P. Chandrakasan, “A 2.5 nJ/bit 0.65 V pulsed UWB
receiver in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol.42,
no.12, pp.2851–2859, Dec. 2007.
[11] Y. Zheng, M. Annamalai Arasu, W. King-Wan, T. Yen Ju, A.P.H.
Suan, T. Duy Duong, Y. Wooi Gan, and K. Dim-Lee, “A 0.18 μm
CMOS 802.15.4a UWB transceiver for communication and localization,” IEEE ISSCC Dig. Tech. Papers, pp.118–600, Feb. 2008.

[12] J. Ryckaert, M. Badaroglu, V. De Heyn, G. Van der Plas, P. Nuzzo,
A. Baschirotto, S. D’Amico, C. Desset, H. Suys, M. Libois, B.
Van Poucke, P. Wambacq, and B. Gyselinckx, “A 16 mA UWB
3-to-5 GHz 20 Mpulses/s quadrature analog correlation receiver in
0.18 μm CMOS,” IEEE International Solid-State Circuits Conference Dig. Tech. Papers, pp.114–115, 2006.
[13] J. Ryckaert, G.V. der PLas, V.D. Heyn, C. Desset, G. Vanwijnsberghe, B.V. Poucke, and J. Craninckx, “A 0.65-to-1.4 nJ/burst 3to-10 GHz UWB digital TX in 90 nm CMOS for IEEE 802.15.4a,”
ISSCC Dig. Tech. Papers, pp.120–121, Feb. 2007.

Lechang Liu
received the B.S. degreefrom Shandong University, China in 2000, theM.S. degree from Harbin Institute of Technology, China in 2002, and the Ph.D. degree inelectronic engineering from Shanghai Jiao Tong
University, China in 2006. From 2007 to 2009,he was with VLSI Design and Education Center, The University of Tokyo, Japan, where heconducted research on low-power impulse radio ultra-wideband (UWB) transceivers. Since
2009, he has been a research associate with theInstitute of Industrial Science, The University of Tokyo, Japan. His current
research interests include mixed-signal circuit design and signal processing
for low-power wireless communications.

Takayasu Sakurai
received the Ph.D. degree in EE from the University of Tokyo in 1981.
In 1981 he joined Toshiba Corporation, where
he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has
worked extensively on interconnect delay andcapacitance modeling known as Sakurai modeland alpha power-law MOS model. From 1988
through 1990, he was a visiting researcher at
the University of California Berkeley, where heconducted research in the field of VLSI CAD.
From 1996, he has been a professor at the University of Tokyo, working
on low-power high-speed VLSI, memory design, interconnects, ubiquitous electronics, organic IC’s and large-area electronics. He has publishedmore than 400 technical publications including 100 invited presentations
and several books and filed more than 200 patents. He served as a conference chair for the Symp. on VLSI Circuits, and ICICDT, a vice chair
for ASPDAC, a TPC chair for the first A-SSCC, and VLSI symp. and a
program committee member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC,
ICCAD, ISLPED, and other international conferences. He will be an executive committee chair for VLSI Symposia and a steering committee chair
for A-SSCC from 2010. He is a recepient of 2010 IEEE Donald O. Pederson Award in Solid-State Circuits, 2009 achievement award of IEICE,
2005 IEEE ICICDT award, 2004 IEEE Takuo Sugano award and 2005 P&I
patent of the year award and four product awards. He gave keynote speech
at more than 50 conferences including ISSCC, ESSCIRC and ISLPED. He
was an elected AdCom member for the IEEE Solid-State Circuits Society
and an IEEE CAS and SSCS distinguished lecturer. He is a STARC Fellow
and IEEE Fellow.

LIU et al.: 0.6 V VOLTAGE SHIFTER AND CLOCKED COMPARATOR

991

Makoto Takamiya
received the B.S.,
M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Japan, in
1995, 1997, and 2000, respectively. In 2000, hejoined NEC Corporation, Japan, where he wasengaged in the circuit design of high speed digital LSIs. In 2005, he joined the University ofTokyo, Japan, where he is an associate professor of VLSI Design and Education Center. His
research interests include the circuit design ofthe low-power RF circuits, the ultra low-voltage
digital circuits, and the large area electronics with organic transistors. He
is a member of the technical program committee for IEEE Symposium on
VLSI Circuits and IEEE Custom Integrated Circuits Conference (CICC).