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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 5, MAY 2012

Startup Techniques for 95 mV Step-Up Converter
by Capacitor Pass-On Scheme and-TunedOscillator With Fixed Charge Programming
Po-Hung Chen, Student Member, IEEE, Koichi Ishida, Member, IEEE, Katsuyuki Ikeuchi, Student Member, IEEE,
Xin Zhang, Member, IEEE, Kentaro Honda, Student Member, IEEE, Yasuyuki Okuma, Yoshikatsu Ryu,
Makoto Takamiya, Member, IEEE, and Takayasu Sakurai, Fellow, IEEE

Abstract—This paper presents a 95 mV startup-voltage step-up
DC-DC converter for energy harvesting applications. The capacitor pass-on scheme enables operation of the system from an input
voltage of 95 mV without using additional off-chip components.
To compensate for the die-to-die process variation, post-fabricatrimming is applied to reduce thetion threshold voltage
minimum operating voltageof the oscillator. Experireduction of the osmental results demonstrate the 34%
cillator by post-fabrication
trimming. The proposed step-up
converter achieves the lowest startup voltage in standard CMOS
without using a mechanical switch or large transformer.
Index Terms—Boost converter, capacitor pass-on, DC-DC converter, energy harvesting, fixed-charge programming, low voltage,-tuned oscillator.
startup,

I. INTRODUCTIONH

ARVESTING energy from the environment by using
thermoelectric generators (TEG) or the photovoltaic
cells provides solutions for battery-free sensor networks orelectronic healthcare systems [1]–[3]. One of the main challenges is the extremely low output voltage that the energy
harvesters can provide. The TEG generates output voltages in
the range of 10 mV/K to 50 mV/K, depending on its process andsize. For body-wearable applications, the output voltage is lessthan 100 mV for a temperature difference of 2K. The output
voltage of a single solar cell is 500 to 600 mV outdoors but
becomes as low as 100 to 200 mV in dark office environments.
of
These voltages are lower than the threshold voltages
most standard CMOS technologies. Even in advanced CMOS
is still around 400 mV and is difficult
technologies, theto operate under subthreshold region. Therefore, a low-startup
voltage step-up DC-DC converter is required to kick-start the
Manuscript received September 27, 2011; revised December 25, 2011; accepted January 12, 2012. Date of publication February 22, 2012; date of current
version April 25, 2012. This work was carried out as a part of the Extremely
Low Power (ELP) project supported in part by the Ministry of Economy, Tradeand Industry (METI) and in part the New Energy and Industrial Technology Development Organization (NEDO). This paper was recommended by Associate
Editor Dr. Stefan Rusu.
P. Chen, K. Ishida, K. Ikeuchi, X. Zhang, K. Honda, and T. Sakurai are with
the Institute of Industrial Science, University of Tokyo, Tokyo 153-8505, Japan(e-mail: hakko@iis.u-tokyo.ac.jp).
Y. Okuma and Y. Ryu are with Semiconductor Technology Academic Research Center (STARC), Yokohama 222-0033, Japan.
M. Takamiya is with VLSI Design and Education Center, University ofTokyo, Tokyo 113-8654, Japan.
Digital Object Identifier 10.1109/JSSC.2012.2185589

system. It also needs to convert the harvested energy to usable
output voltages because the harvested voltages are too low forelectronic devices.
In this paper, a 95 mV startup voltage step-up converter
without mechanical stimuli is proposed to extend the applicability of energy harvesting [4]. The proposed circuit converts
the 100 mV input to 0.9 V output at 0.9 mA load current.
-tuned oscillator trimmed by fixed
We also propose acharge programming to compensate for the die-to-die processof thevariation. The minimum operating voltage
oscillator can be reduced by 34%. The circuit demonstrates thefeasibility of countermeasures for the process variation thatof an on-chip ring oscillator.
limits theThis paper is organized as follows. Startup techniques
for low input voltage DC-DC converters are introduced in
Section II. Section III describes the proposed system architecture. Section IV explains the circuit implementation of
the proposed voltage detector. Section V shows the circuit-tuned oscillator with fixed charge
implementation of the
programming. The experimental results and comparison withthe state-of-the-art are shown in Section VI. Finally, a conclusion will be drawn in Section VII.
II. STARTUP TECHNIQUES IN DC-DC CONVERTERS
Developing a startup mechanism is one of the most critical issues for low input voltage DC-DC converters [5]. The conceptof the conventional step-up converter startup mechanism is illustrated in Fig. 1 [6]. The startup mechanism is used to generateand charges. It cana higher auxiliary voltage
be an external voltage or another power management circuit.
is charged to a high voltage, the control circuit
Once the. The control circuit then drives thecan be powered bypower devices in the DC-DC converter with sufficient amplifor the DC-DC converter to function. The
tude
is now charged by the main DC-DC converter and supplies thecontrol circuit. The key technique in the scheme is to generateto.
an auxiliary voltage higher than
Until now, several startup techniques were reported [6]–[11]for low voltage operation. [6], [7] kick start the system by applying the auxiliary voltage directly to the output. The 650 mV
external voltage and 2 V battery are required in [6] and [7], respectively. A battery-less 35 mV startup boost converter was
implemented by using a mechanically assisted step-up process

0018-9200/$31.00 © 2012 IEEE

CHEN et al.: STARTUP TECHNIQUES FOR 95 mV STEP-UP CONVERTER

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Fig. 1. Concept of the conventional step-up converter with a startup mechanism [6].

Fig. 3. Proposed capacitor pass-on scheme to kick-start the system. (a) Startup
mode. (b) Operation mode.

Fig. 2. Conventional startup mechanism in [12].

[8]. It uses a mechanical switch to eliminate the clock requirement at startup but vibration is required to activate the mechanical switch. This limits the application and increases the cost.
A completely electronic startup step-up converter without using
an external voltage was presented in [9]–[11]. Refs. [9] and [10]use a transformer with a large turn ratio and are not well suitedfor portable applications. In [11], it eliminates a transformer but
the startup voltage is limited to 330 mV. Therefore, our main
target in this work is to design a CMOS on-chip startup mechanism with minimal off-chip components.
Fig. 2 shows a previous CMOS on-chip startup technique reported in [12]. It applies a charge pump (CP) to generate highvoltage for the control circuit and kick-start the system from180 mV. In this approach, two off-chip capacitors are required.
One
is for the CP and the otheris for theboost converter. When operating under low input voltage,
the CP is so weak that it cannot build up the higher voltage wheneven a small amount of leakage exists. Therefore, the startup
voltage is limited by the power consumption of the control circuit. This startup voltage is higher than our target(100 mV) and further improvement is required.
To reduce the startup voltage, we propose the capacitor
pass-on scheme for the startup mechanism. The operation concept of the capacitor pass-on scheme is shown in Fig. 3.
in Fig. 2 can be eliminated by using the output capacitor of theboost converter,, as the charge buffer of the CP. During
startup,is charged by the on-chip 20-stage Dickson-type
CP [13], as shown in Fig. 4. The pumping capacitor in eachFig. 4. The circuit schematic of the 20-stage dickson charge pump.

stage is 3 pF. The CP is driven by an on-chip CMOS oscillator,
which generates a 330 kHz clock signal when provided supply
voltage as low as 95 mV. In conventional approach, Dicksoncharge pump is diode connected and has the diode voltage
drop between stages. In our application, however, the output
current is limited during startup and the output capacitor isavailable to be charged to a high voltage. Even though the clock
amplitude is smaller than
, there still exists the current
difference between
and, as shown in Fig. 4. This
current difference charges the pumping capacitor and pumps up
the output voltage. Since the amplitude of the clock provided
to CP
is small, the available output current of the CP
is limited. Therefore, we cut off the current path of the control
circuit to minimize the output current in startup mode.
Whenis charged to the preset voltage,is“passed on” with its charge inside to be the boost converter andsupplies the control circuit. To turn on the power transistors
andby using the control circuit,should be charged
to higher than
. In our design, theof the powertransistors is about 400 mV. Therefore, the preset voltage
is designed to 460 mV to make sure the clock amplitude isenough to turn-on the power transistors. By using the proposed
scheme, the startup voltage can be reduced to 95 mV and thelarge external capacitor
in Fig. 2 can be eliminated.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 5, MAY 2012

Fig. 6. Simulated dependence of leakage current on gate over-drive voltage.
Fig. 5. Block diagram of proposed step-up converter with capacitor pass-on
andarescheme. The switch status in the figure represents the initial state.
control signals.

III. SYSTEM ARCHITECTURE
The detailed block diagram of the proposed step-up DC-DC
converter with the capacitor pass-on scheme is shown in Fig. 5.
It consists of power transistors,,, a fixed-charge-tuned oscillator, the CP for startup, CP for pMOS super
cut-off (PSC), the control circuit, and two voltage detectors D1
and D2. The switch status in this figure represents the initialstate.
andare the control signals for the switches. In ourdesign, the target is to verify the on-chip startup mechanism in
the DC-DC converter. The control circuit generates the pulse
signal with fixed duty cycle for the power transistors but does
not include the pulse-width modulation control.
The fixed-charge-tuned oscillator is used to generate
the clock signals for the CP during startup. In our application,
the oscillator needs to function under sub-100 mV supply
voltage. The CP for startup is designed to charge the output
capacitor
at the startup. Although the control circuit
is not connected to, the leakage current of the powertransistors
andstill limit the startup voltage. To
reduce the leakage current, we applied the CP for PSC toprovide the overdrive voltage to the gate of pMOS transistors(
and). The simulated dependence of leakage current
on gate overdrive voltage is shown in Fig. 6. As can be seen,
before providing the gate overdrive voltage, the leakage current
is 1 A, which is too large for the low-voltage CP. Our target
leakage current of each power transistor is below 1 nA. Therefore, we applied 0.35 V of gate overdrive voltage to reduce theleakage current.
Fig. 7 illustrates the operation sequences of the proposed
step-up DC-DC converter. There are three modes, the startup
mode, the warm-up mode and the operation mode. These modes
are selected by using two voltage detectors D1 and D2 withdifferent trigger voltages. During the startup mode, theis charged by CP andrises. When(@Startup) is pumped to the preset trigger voltage of D1, thenodechanges from low to high to pass theon to theboost converter.

Fig. 7. Waveforms illustrating the operation sequences of the proposed step-up
converter.

The warm-up mode is used to ensure the output switch
turns on after the boost converter starts working and the output
can be boosted smoothly. During this mode,
becomes akind of power supply. The charge stored in
activates thecontrol circuit and starts driving the boost converter. The control circuit must provide enough voltage amplitude
to drive the power transistorsand. The power transistor
does not turn-on immediately when the capacitor ispassed-on. If the load is connected at the same time when thecapacitor is passed-on (w/o warm-up mode), the charge storedindrains out and the boost converter fails to startup.
To overcome this problem, a voltage detector D2 with 60 mV
higher trigger voltage compared to D1 is added to delay the load
connection timing a bit. Whenis boosted to the preset
trigger voltage of D2, the node changes from low to high andis almost equal to. During the operation mode,thebecomes an output capacitor of the boost converterto smooth the output voltage.

CHEN et al.: STARTUP TECHNIQUES FOR 95 mV STEP-UP CONVERTER

1255

Fig. 10. Circuit schematic of the proposed voltage detector core.

Fig. 8. Conventional voltage detector using (a) BGR and (b) voltage monitoring circuit in [14].

PMOS configuration. The trigger voltage in this scheme is determined by comparing the currents
and. The circuit
is operating under subthreshold region, thus the current draw
through the transistor
can be given as [15](1)(2)

Fig. 9. Waveform illustrating the proposed voltage detector.

IV. VOLTAGE DETECTOR
The modes of the proposed step-up converter can be automatically changed by detecting the capacitor voltage.
The key building blocks in this scheme are the voltage detectors
D1 and D2. Since the detector D1 and D2 are directly connectedtoat startup, they act as the load of the CP. Again, since
the CP is weak during startup, the operating current of the detectors may spoil the normal startup. Thus, the power consumptionof the detectors should be minimized.
Conventionally, the voltage is detected by using the bandgap
reference (BGR) and a comparator, as shown in Fig. 8(a). The
BGR consumes several microwatts since it uses DC-biased resistors. Another approach uses a voltage monitoring circuit instead of BGP to reduce the power consumption [14], as shownin Fig. 8(b). The voltage monitoring circuit, however, needs ahigh supply voltage to realize the current detection circuit. In ourstartup mechanism, both low-voltage and low-power detector
circuit is required to switch the operation modes. To meet thisrequirement, we propose a reference-less CMOS voltage detector with 1.6-nW power consumption, as shown in Fig. 9. To
further decrease the power consumption, the proposed scheme
eliminates the comparator and only one input signal is applied. It can detect the voltage level of theandprovide the trigger signal to the switches. In the following, thecircuit design of the proposed voltage detector will be describedin detail.
Fig. 10 shows the circuit schematic of the detector core. The
detector core consists of two cascode transistors:
and.
Both transistors were chosen to be pMOS transistors because
all pMOS configuration has less process variation than NMOS-

where k is the Boltzman constant, is the hole mobility,
is the gate oxide capacitance per area and m is the subthresholdswing coefficient. kT/q is the thermal voltage and isapproximately 26 mV at room temperature. If
is large enough,can be simplified
as(3)
Therefore,
increases exponentially as
increases.
Similarly, the transistor
is also operating in the subthreshold region
and assuming
is large enough. To reduce the power consumption, the gateofis connected to its source and only off-current
flows. The current
can be given as(4)
As can be seen,
is constant and only depends on thetransistor ratio. The trigger voltage
is defined aswhenchanges from low to high. Therefore,isthe input voltage when
, which can be written as(5)can be tuned easily by deThis equation shows thatsigning the transistor size ofand. Although
is proportional to the temperature, this is not a critical problem
in our application. This is because the circuit is targeted forbody-wearable applications or indoor solar cells. Therefore, thetemperature variation is limited.
In our application,
is designed to be larger thanof the transistors. Assuming
is 460 mV at room temperature and, the transistor ratio ofandcan
be calculated as
(6)

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 5, MAY 2012

Fig. 12. Simulation results of the proposed voltage detector depicting the deandon.
pendence ofFig. 11. Circuit schematic of the proposed voltage detector with a diode connected transistor to adjust the trigger voltage.

This ratio is too large and is not practical for implementation.
To solve this problem, we added a diode-connected pMOS transistor
with transistor size ofto almost double thetrigger voltage, as shown in Fig. 11. Since the transistor size ofandare the same. From (1),ofandare the same. The transistor ratio ofand
can be modified as(7)which is possible to implement in practice. Adding a transistor, however, reduces the voltage amplitude of node
to 0.5. Therefore, we designed two-stage inverters to amplify
the voltage swing.
The simulation results of the proposed voltage detector are
shown in Fig. 12. In our design, the channel width and channel
length are designed as follows:
m,
m,
and
m. Theof voltage detectors D1 and D2 are
63 m and 144 m, respectively. As can be seen, the trigger
voltage difference (in Fig. 7) between D1 and D2 can be
designed by changing the channel width. The voltage
rises when theis close to
and amplified by
the inverter buffer. Therefore, the output voltagechanges from low to high sharply at. Fig. 13 shows
the simulated dependence of power dissipation on. The
spikes in current are due to the buffer inverter shoot-throughin trigger voltage. This current can be mitigated by adjusting
the transistor size of the buffer. Reducing the W/L ratio of thetransistors can minimize this current. The power consumptionof the startup mode is most critical because it is charged by
the low-voltage CP. From the simulation, we can obtain thatthe proposed voltage detector consumes less than 1.6 nW when(Startup mode). The proposed voltage detector achieves both low voltage and low power operation to
detect the desired voltage.
V. FIXED-CHARGE-TUNED OSCILLATOR

The fixed-charge-tuned oscillator is used to generate
the clock signal for the charge pump. The minimum operation
voltageof the oscillator limits the startup voltage ofthe step-up DC-DC converter in standard CMOS technology.

Fig. 13. Simulated dependence of power consumption on.

This is because the clock signal is required for a charge pumpwhen starting up the system.
Practically, theof an oscillator is usually limitedby PMOS-NMOS
imbalance caused by within-die anddie-to-die
variations. The within-die
variation issue
can be solved by increasing the channel width and thus it can beeasily solved in this application. The problem is the die-to-die
variation which is usually adjusted by controlling the body biasof the MOSFETs. In the startup circuit, however, a body-biasing
circuit would not function before the system startup because
only the input voltage exists in the system. Therefore, a newtechnique is required to compensate for the die-to-die process
variation without using body biasing.
Fig. 14 shows the simulation results of aof 15-stage
inverter-based ring oscillator under different process corners.
SS means slow nMOS and slow pMOS. ST means slow nMOS
and typical pMOS, and so on. The simulation results show thatof lower than 100 mV can be achieved if theof nMOS and pMOS are well balanced. Therefore, if we canadjust the threshold voltage of transistors, for example, adjust
fast nMOS slow pMOS to slow nMOS slow PMOS,
can be reduced from 173 mV to 73 mV, which is as low as thetarget operation voltage.
To make sure the circuit functions even under the die-to-die
process variation, we proposed a new fixed-charge-tunedoscillator. Theof the transistors in the ring oscillator andthe buffer are trimmed by fixed-charge programming to makesure the circuit functions even under die-to-die process variation. The detailed circuit schematic is shown in Fig. 15. The circuit consists of a 15-stage inverter-based ring oscillator and inverter-based output buffer. We added two pads for the substrate

CHEN et al.: STARTUP TECHNIQUES FOR 95 mV STEP-UP CONVERTER

Fig. 14. Simulation results ofof oscillator under different process
corners. SS means slow nMOS and slow pMOS, TF means typical nMOS andfast pMOS, and so on.

1257

Fig. 16. Chip micrograph of dual-mode boost converter in 65-nm CMOS.

no body bias is applied to the nMOS transistors, theis notprogrammed and remain the same voltage.
Whenof the ring oscillator is decreased to lower
than our target voltage, the post-fabrication programming can
be stopped. The circuit is then operating under normal modeand only a 95 mV supply is provided. The
in normal
mode is provided to
to avoid the body effect. The injectedcharge is still fixed in the pMOS transistor and theremains higher than the initial value.
is now balanced withandof the oscillator can be reduced. Now, thecircuit can be operating under 95 mV and drives the CP at sucha low voltage.
We introduced the pMOS programming in this paper. Similarly, if
is higher thanand nMOS programming isrequired, the high reverse voltage toand 1 V supply
tocan be applied to increase.
VI. EXPERIMENTAL RESULTS
Fig. 15. Circuit schematic of the proposed fixed-charge(a) Program mode. (b) Normal mode.

-tuned oscillator.

of the pMOS
and nMOS
transistors toprovide the body bias.
To reduce within-die process variation, the transistor width of
the inverter in the oscillator is designed at least 16 times larger
than the standard cell. In the measured chips, since theof
an nMOSwas higher than that of a pMOS,
is adjusted (increased) to reduce theof the oscillator
here. This is because the fixed-charge programming is mucheasier to increase thethan to reduce the.
In program mode, the power supply is set to 1 V and the ringoscillator oscillates. In pMOS programming, theis programmed by applying high reverse body bias to all pMOS transistors
while the body of nMOS transistors are connected to the source. Because thehigh reverse body bias is provided, positive charges are injected
into the gate dielectrics when AC current flows. This AC current is caused by the flow-through current when the clock signal
changes its state. The injected charge is fixed in the dielectrics
and increases theeven after the high reverse body bias isremoved. Note that theshift shows nonvolatile characteristics and does not require any additional process steps. Since

The test chip is fabricated using 65-nm standard CMOS technology. Fig. 16 shows the chip micrograph of the proposed
step-up DC-DC converter. The active area including the fixedcharge-tuned oscillator, the CP for startup, the CP for PSC
and the boost converter is 0.17 mm . The circuit is measured
with an off-chip inductor of 6.8
and an off-chip capacitor of
10 nF. The startup circuit is all implemented on-chip and there
are no additional devices for the startup mechanism.
Fig. 17 shows the measured dependences ofof thefixed-charge-tuned oscillator on trimming time. Threetest chips are measured to verify
improvement. Theof the pMOS transistors are increased as trimming timeincreases and 34% of
reduction is achieved in 60
minutes. In this prototype design, we manually tested thechip and obtain the. The trimming time depends
on the bias condition of the circuit. The trimming time will
be reduced by applying higher reverse body bias and higher
supply voltage. The reverse body bias is limited by the p-njunction breakdown voltage and the supply voltage is limitedby the gate breakdown voltage. By applying the fixed-charge
programming, theof the oscillator can be reduced
from 125 mV to 82 mV, which achieves our design target.
Fig. 18 shows the measured dependences ofvariationover the time after programming is finished. In this test, thecircuit is operating under the operation mode and 95 mV supply

1258IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 5, MAY 2012

TABLE ICOMPARISON WITH PUBLISHED LOW-STARTUP VOLTAGE STEP-UP DC-DC CONVERTER

Fig. 17. Measured dependence ofof-tuned oscillator with fixedcharge programming on trimming time for 3 dies.
Fig. 19. Measured startup waveforms of the proposed step-up converter.

Fig. 18. Measured dependence offinished.

change on time when trimming is

voltage is provided without any high reverse body bias. Even
after the high reverse body bias is removed, the change is as
small as 1 mV after 3 days of stress and becomes stable.
Fig. 19 shows measured startup waveforms of the proposed
step-up DC-DC converter with the capacitor pass-on scheme.
The circuit is measured with a 95 mV ideal power supply
without any external clocks or mechanical switches. The CP
for startup pumps up the external capacitor and passes on
the capacitor to the boost converter after 262 ms. The output
voltageis obtained after the circuit is operating underoperation mode. The waveforms during warm-up mode cannot
be obtained in the measurement because the warm-up time is
too short. The oscilloscope waveform demonstrates that the
proposed converter is successfully started from the 95 mV
input.
In this system, the start-up voltage is limited by bothof the oscillator and driving capability of the charge pump. The
95 mV startup voltage in this design is limited by the charge

Fig. 20. Measured dependence of the output voltage on load current.

pump because theof the oscillator can be reduced to
82 mV. If the clock amplitude is too small, the charge pump
can not provide enough current to supply the output load. In addition, the external capacitor can not be charged to the preset
trigger voltage and the system fails to startup. In the trigger
voltage, the simulated leakage current of the power transistor
is 1.1 nA (and). The current consumed by D1 andD2 is 3.5 nA and 0.7 nA, respectively. 5.1 nA is consumed
by the CP for PSC and 0.05 nA is consumed by control circuit during startup. Therefore, the CP needs to provide at least
10.5 nA output current to charge the output loads and an output
capacitor.
The measured output voltage versus the current delivered to
the load under 100 mV input is shown in Fig. 20. The output
voltage is up-converted to higher than 0.8 V in our target output
current.

CHEN et al.: STARTUP TECHNIQUES FOR 95 mV STEP-UP CONVERTER

The performance comparison between our circuit and thestate-of-the-art step-up DC-DC converters with a startup mechanism is shown in Table I. The proposed startup mechanism
achieves the lowest startup voltage except reference [8], which
requires mechanical switch to assist the startup. By using thecapacitor pass-on scheme, the startup voltage of 95 mV isachieved by using the CMOS technology only without any
external clocks or mechanical switches.
VII. CONCLUSION

1259[14] T. Shimamura, M. Ugajin, K. Suzuki, K. Ono, N. Sato, K. Kuwabara,
H. Morimuram, and S. Mutoh, “Nano-watt power management andvibration sensing on a dust-size batteryless sensor node for ambient
intelligence application,” in IEEE Int. Solid-State Circuit Conf. Dig.
Tech Papers, Feb. 2010, pp. 504–505.
[15] L. Magnelli, F. Crupi, P. Corsonello, C. Pace, and G. Iannaccone, “A
2.6 nW, 0.45 V temperature-compensated subthreshold CMOS voltage
reference,” IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 465–474,
Feb. 2011.
[16] S. Matsumoto, T. Shodai, and Y. Kanai, “A novel strategy of a control IC for boost converter with ultra low voltage input and maximum
power point tracking for single solar sell application,” in Proc. Int.
Symp. Power Semiconductor Devices & ICs, Jun. 2009, pp. 180–183.

A step-up DC-DC converter with low startup-voltage forenergy harvesting applications is proposed. Capacitor pass-on
scheme enabled by the low power voltage detector reduces thestartup voltage from 180 mV to 95 mV. In addition, the number
of off-chip capacitors can be reduced from 2 to 1. The proposed
circuit also demonstrates the feasibility of countermeasures
for the die-to-die process variation that limits the minimum
startup voltage of an on-chip ring oscillator. Theofthe oscillator can be reduced from 125 mV to 82 mV. As aresult, the lowest startup voltage of 95 mV is achieved by using
the on-chip startup mechanism.

Po-Hung Chen (S’10) received the B.S. degree inelectrical engineering from National Sun Yat-sen
University, Kaohsiung, Taiwan, in 2005 and the M.
S. degrees in electronics engineering from National
Chiao Tung University, Hsinchu, Taiwan, in 2007.
He is currently pursuing a Ph.D. degree in electronicengineering at the University of Tokyo, Tokyo,
Japan.
His current research interests focus on low voltage
CMOS DC/DC converters, on-chip DC/DC converters, and low-voltage low-power CMOS analog
circuits.

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Koichi Ishida (S’00–M’06) received the B.S. degree
in electronics engineering from the University ofElectro-Communications, Tokyo, Japan, in 1998,
and received the M.S. and Ph.D. degrees in electronics engineering from the University of Tokyo,
Tokyo, Japan, in 2002 and 2005, respectively.
He joined Nippon Avionics Co., Ltd. Yokohama,Japan in 1989, where he developed high-reliability
hybrid microcircuits for aerospace programs. Since
July 2007, he has been working at Institute of Industrial Science, the University of Tokyo as a research
associate. His research interests include low-voltage low-power CMOS analog
circuits, on-chip power supply circuits, and large-area flexible electronics.
Dr. Ishida is a member of IEICE.

Katsuyuki Ikeuchi (S’09) received the B.S., and
M.S. degrees in electronics engineering from the
University of Tokyo, Tokyo, Japan, in 2007, and2009, respectively, where he is currently pursuing
the Ph.D. degree in electronics engineering.
His research interests include low-voltage
low-power circuits, and proximity communication.

Xin Zhang (S’06–M’08) received the B.S. degree inelectronics engineering from Xi’an Jiaotong University, Xi’an, China in 2003, the Ph.D. degree in microelectronics from Peking University, Beijing, China in2008.
Since 2008, he has been a project researcher with
the Institute of Industrial Science (IIS), University ofTokyo, Tokyo, Japan. His research interests include
low-voltage low-power analog and mixed-signal circuits, variation aware circuits, power management integrated circuits, and renewable energy harvesting.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 5, MAY 2012

Kentaro Honda (S’10) received the B.S. degree inelectronic engineering from the University of Tokyo,
Japan, in 2010. He is currently studying in Department of Electrical Engineering and Information Systems, Graduate School of Engineering, the Universityof Tokyo.
His research interests are in the field of low-power
circuit design of the RF transceiver circuits and digital circuits.

Yasuyuki Okuma received the B.S. and M.S. degrees in electrical engineering from Tokyo Universityof Science, Japan, in 1997 and 1999, respectively.
In 1999, he joined Central Research Laboratory,
Hitachi, Ltd., Japan, where he has engaged in the
research and development of low power analog
circuit techniques for HDD driver and RF-IC. From2003 through 2006, he was a visiting researcher at
YRP Ubiquitous Networking Laboratory, doing research in the field of low-power circuits and systems
for ubiquitous computing. Currently, he is visiting
researcher at Extremely Low Power LSI Laboratory, Institute of Industrial
Science, the University of Tokyo, Japan, from 2009. he is interested in power
supply circuits for extremely low power LSI circuits and systems.

Yoshikatsu Ryu graduated from Kobe City College
of Technology, Kobe, Japan, in 1992.
In 1992, he joined SHARP Corporation, Nara,
Japan. From 1992 to 2001 he was involved in thedevelopment of semiconductor processing technology, and from 2001 to 2009 he was engaged
in the circuit design of analog LSIs. Currently,
he is visiting researcher at Extremely Low Power
LSI Laboratory, Institute of Industrial Science, theUniversity of Tokyo from 2009. His current interests
are low-voltage low-power CMOS charge pump
circuits.

Makoto Takamiya (S’98–M’00) received the B.S.,
M.S., and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Tokyo, Japan, in
1995, 1997, and 2000, respectively.
In 2000, he joined NEC Corporation, Japan, where
he was engaged in the circuit design of high speed
digital LSIs. In 2005, he joined University of Tokyo,
Japan, where he is an associate professor of VLSI Design and Education Center. His research interests include the circuit design of the low-power RF circuits,
the ultra low-voltage logic circuits, the low-voltage
DC-DC converters, and the large area electronics with organic transistors.
Dr. Takamiya is a member of the technical program committee for IEEE Symposium on VLSI Circuits. He received 2009 and 2010 IEEE Paul RappaportAwards.

Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in electrical engineeringfrom the University of Tokyo, Tokyo, Japan, in 1981.
In 1981 he joined Toshiba Corporation, where hedesigned CMOS DRAM, SRAM, RISC processors,
DSPs, and SoC Solutions. He has worked extensively
on interconnect delay and capacitance modelingknown as Sakurai model and alpha power-law MOS
model. From 1988 through 1990, he was a visiting
researcher at the University of California Berkeley,
where he conducted research in the field of VLSICAD. From 1996, he has been a Professor at the University of Tokyo, working
on low-power high-speed VLSI, memory design, interconnects, ubiquitouselectronics, organic IC’s and large-area electronics. He has published morethan 600 technical publications including 100 invited presentations and several
books and filed more than 200 patents.
Prof. Sakurai has been an executive committee chair for VLSI Symposia anda steering committee chair for IEEE A-SSCC since 2010. He served as a conference chair for the Symposium on VLSI Circuits, and ICICDT, a vice chair
for ASPDAC, a TPC chair for the A-SSCC and VLSI Symposium, an executive committee member for ISLPED and a program committee member for
ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED, and other international conferences. He is a recipient of the 2010 IEEE Donald O. Pederson
Award in Solid-State Circuits, 2009 and 2010 IEEE Paul Rappaport awards,
2010 IEICE Electronics Society award, 2009 achievement award of IEICE,
2005 IEEE ICICDT award, 2004 IEEE Takuo Sugano award, and 2005 P&I
patent of the year award and four product awards. He gave the keynote speech
at more than 50 conferences including ISSCC, ESSCIRC, and ISLPED. He wasan elected AdCom member for the IEEE Solid-State Circuits Society and an
IEEE CAS and SSCS distinguished lecturer. He is a STARC Fellow, IEICE
Fellow and IEEE Fellow.