Inductor Design of 20-V Boost Converter for Low Power
3D Solid State Drive with NAND Flash Memories
Tadashi Yasufuku 1, Koichi Ishida 1, Shinji Miyamoto 2, Hiroto Nakai 2,
Makoto Takamiya 1, Takayasu Sakurai 1, Ken Takeuchi 1
1

University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo, Japan, 153-8505
2
Toshiba Corporation, Yokohama, JAPANtdsh@iis.u-tokyo.ac.jp
NAND
controller

ABSTRACTA 3D-integrated Solid State Drive (SSD) with the boost converter
can achieve both the low power and the fast write-operation at thesmall die area of the NAND flash memory. The performance ofthe boost converter, however, is critically affected by the inductor,
because the output voltage of the boost converter, the rising time,
and the energy consumption during the boost are determined by
the inductor. Therefore, this paper proposes a spiral inductor
design of the boost converter for the 3D SSD. By using the boost
converter with the optimized inductor, the energy during writeoperation of the proposed 1.8-V 3D-SSD is decreased by 68%
compared with the conventional 3.3-V 3D-SSD with the charge
pump.

Interposer
NAND
flash
Chargepump
DRAM

Categories and Subject Descriptors

Figure 1. Conventional SSD with charge pump.

B.7.0 [Integrated Circuits]: General

General Terms

Serial MOS diodes lose energy.
Large number of stages for low VDD

Measurement, Performance, Design, Experimentation, Theory.

Keywords

VDD

SSD, boost converter, charge pump, inductor design

1. INTRODUCTIONVOUT =20VClk
Clk

One of the serious design issues of Solid State Drive (SSD) is theincreasing power consumption. Figure 1 shows a device
architecture of a conventional SSD. A typical SSD consists ofmore than 16 NAND flash memories, DRAM’s and a NAND
controller. In SSD, each NAND flash chip has a charge pump
circuit to generate the program voltage of 20V. Figure 2 shows aschematic and issues of the charge pump to generate the program

Large capacitancefor large current

Energy during write [a.u.]

Figure 2. Schematic and issues of the charge pump.

voltage (VOUT). 5 to 10 ％ area of each NAND flash chip is
occupied by the charge pump due to its large capacitance, whichraises the cost of SSD. Unacceptably large current (e.g. 800mA)
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CBL: Bit-line capacitance

Memorycore∝CBLV2

ChargepumpEnergyincreases.

Memorycore
Chargepump

OthersConventional
3.3V NAND [2]1.8V NAND(Simulated)

Figure 3. Energy consumption of NAND flash memories during
write-operation at VDD of 3.3V and 1.8V.

87merged into the boost converter on an interposer. In theconventional NAND flash memory, the implementation of theinductor for the boost converter was difficult, because an on-chip
inductor occupies the large die area and raises the cost. In contrast,in the proposed 3D SSD, the inductor is implemented on the blankspace of the original interposer, which does not raise the cost for
the inductor. The area penalty of high voltage MOS of the boost
converter on the interposer is negligible, because the area is just
15% of the conventional charge pump. Thus, the proposed 3Dintegrated SSD with the boost converter can achieve both the low
power and the fast write-operation at the small die area of the
NAND flash memory.
The performance of the boost converter, however, is criticallyaffected by the inductor, because the output voltage of the boost
converter, the rising time from an initial voltage to a target
voltage (VOUT), and the energy consumption during the boost are
determined by the inductor. Therefore, the inductor design of theboost converter for the 3D SSD is very important. A spiralinductor design, however, is not clear and has not been publishedyet, because the output load of the boost converter of the NAND
flash memory is different from that of a widely-used boost
converter. Normally, the output load of the boost converter isresistive and the boost converter including that for a NOR flash
memory [5] operates in a continuous conduction mode and thesteady-state analysis is important and well understood. In contrast,
the output load of the boost converter of the NAND flash memory
is capacitive, and the boost converter operates in a discontinuous
conduction mode. As shown in [4], the transient analysis during
the boosting is important in this application. Although analyticalequations of the discontinuous conduction mode have beendeveloped in [6-7], their output load is resistive (less than tens ofohms). Therefore, the analytical equations cannot be used in thispaper. Hence, this paper proposes a spiral inductor design of theboost converter for the 3D SSD with the NAND flash memories
using SPICE circuit simulation.

will flow to charge huge bit-line capacitance of NAND flash
memories in a sub-30nm SSD [1], when 8 or more NAND chips
operate in parallel, because the bit-line capacitance drasticallyincreases with the device scaling. A good strategy to decrease thepower is lowering the power supply voltage (VDD) from 3.3V to
1.8V. Figure 3 compares the energy consumption of NAND flash
memories during a write-operation at VDD of 3.3V [2] and 1.8V
(simulated). When VDD is decreased from 3.3V to 1.8V, eventhough the energy of the memory core decreases, the total energy
decreases by only 18%, because the energy of the charge pumpincreases. This is because the number of capacitance stages
increases to generate 20V from reduced VDD and the energy loss
at the NMOS diodes increases as shown in Figure 2.
The poor output current drivability of the charge pump is also the
problem, because 8 or more NAND flash chips in SSD need to be
simultaneously programmed in order to achieve the 100MByte/sec write speed of the hard disk drive, because the write
speed of the NAND flash memory is only 10MByte/sec [2][3].
In this way, the charge pump prevents the area reduction, the VDD
scaling, and the fast write-operation of the NAND flash memory.
Therefore, a new alternative high voltage generation circuit isstrongly required to reduce the area, the power, and the write-timeof the NAND flash memory.
Figure 4 shows a 3D-integrated SSD proposed in [4]. The NAND
flash memories, DRAM’s, the NAND controller, and a boost
converter are integrated in SiP. Figure 5 shows a schematic
diagram of the boost converter which consists of two high-voltage
nMOS transistors and an inductor. In the proposed 3D SSD, boththe low power and the fast write-operation are achieved, because
both the voltage conversion efficiency and the output current
drivability of the boost converter are higher than those of thecharge pump. The die area of the NAND flash memory is also
reduced, because the charge pumps on each flash memory are

Shared boost converter

NAND
controller

Adaptive High-voltage Spiral
MOS
controller
inductor

Interposer

2. Spiral inductor design for boost converter

Smallerdie size

In this chapter, the spiral inductor design of the boost converter
for the 3D SSD is investigated. In order to implement the inductorin the 3D SSD, three types of inductors including an on-chip
inductor (L), an on-interposer inductor, and an on-board inductor
are compared. Figure 6 shows design parameters of the inductor.
A square-shaped inductor is assumed. Table.1 shows theparameters of the three types of inductors used in this chapter.
The inductance of the inductors is calculated by equations (1)-(4)[8].

Chargepump

Charge
pump

NAND
flash

μ 0 n 2 d avg c1 ⎡ ⎛ c2 ⎞2⎤⎢ln ⎜⎜ ⎟⎟ + c3 ρ + c4 ρ ⎥
2
⎣ ⎝ρ⎠
⎦
d out + d in
d avg =
2d out − dinρ≡d out + din
L≈

DRAM

Figure 4. Proposed 3D-SSD with boost converter.
High-voltage MOS
TON

TOFF

VDD

(1)
(2)
(3)

(4)
c1 = 1.27, c2 = 2.07, c3 = 0.18, c4 = 0.13
L shows the inductance, μ0 shows the vacuum permeability, nshows the number of turns, dout shows the outer diameter, din
shows the inner diameter, and c1-c4 are constants. din / dout = 1/3 isassumed in this study to increase the quality factor of the inductor.

VOUT
Clk

Frequency = 1 / (TON + TOFF)
Duty cycle = TON / (TON + TOFF)

Figure 5. Circuit diagram of boost converter.

88

Outer diameter

memory is 150mm2 - 200mm2 and the 15% of the area can beused for the inductor. Figure 8 shows the inductance dependenceof the parasitic resistance of the three types of inductors
calculated from total length of inductor. The on-chip inductor has
the small area and the large parasitic resistance, because the line
and space is narrow and the metal thickness is thin. In contrast,
the on-board inductor has the large area and the small parasitic
resistance, because the line and space is wide and the metal
thickness is thick. In the on-board inductor, 330nH is the
maximum inductance with the 25mm2-area constraint.
The various inductors shown in Figures 7 and 8 are adopted in the
boost converter and the best design of the inductor is investigated.
Figure 9 shows the equivalent circuit of the simulated boost
converter. Input voltage (VDD) is 1.8V, and target output voltage(VOUT) is 20V. A NAND flash chip as the output load of the boost
converter is emulated by the load resistance (1MΩ) andcapacitance (160pF). Parasitic resistance of the interconnects (R1R5) and the inductor (RL) are also included. Switching frequency(or period) and duty cycle are 18.2MHz (55ns) and 80%
respectively, and the amplitude of the switching transistor is 3.6V.
Inductance dependence of key performances of the boost
converter including the output voltage, the rising time, and theenergy consumption are simulated with this circuit.
Figure 10 shows the simulated dependence of the output voltage
on the inductance in the three types of inductors. The boost
converter with the on-chip inductor cannot boost the voltage
above 4V, because the parasitic resistance of the on-chip inductor
is very large. In contrast, both the on-interposer and the on-board

Inner
diameterSpace
ThicknessLine

Figure 6. Design parameters of inductor.
Table 1. Parameters of three types of inductors.
Line / Space

Thickness Metal material

On-chip inductor

10µm / 10µm

2µm

Al

On-interposer inductor

25µm / 25µm

15µm

Cu

On-board inductor

100µm / 100µm

35µm

Cu

Outer diameter [mm]10Area limitation(25mm2)
oard
On-b

L

ser L
erpo
t
n
i
On
hip L
O n- c1

VDD=1.8V

0.1
10

100

Inductance [nH]

Iin

1000

0.1

0.01
10

hip L

R2

R4

R5

160pF

1MΩ

R3

Emulation for
a NAND chip

Figure 9. Equivalent circuit of simulated boost converter.

30
O

R1

Period = 55ns
Duty = 80%s er L
erpo
n-int

Output voltage [V]Parasitic resistance [Ω]

1

L

3.6V

100

10

RL

Inductor
Clock

Figure 7. Calculated inductance dependence of outer diameterof three types of inductors.

On-c

VOUT = 20V

L
oard
On-b

100

Inductance [nH]1000

Figure 8. Calculated inductance dependence of parasitic
resistance of three types of inductors.

25

On-board L

20

Optimal region
70nH - 270 nH

15

Targetvoltage10
50

As a first step of the inductor design, the range of the inductanceis calculated with an area constraint.
Figure 7 shows the calculated inductance dependence of the outer
diameter of the three types of inductors. Area limitation of 25mm2
for the inductor is assumed, because the die area of a typical flash

Optimal region
50nH - 330 nH

On-interposer L
On-chip L

0

50 100 150 200 250 300 350 400 450 500

Inductance [nH]Figure 10. Simulated dependence of output voltage on
inductance in three types of inductors.

89

Rising time [ns]Energy during boost [nJ]

inductors can boost the voltage above 20V. In order to boost theoutput voltage above 20V, a 50-nH to 330-nH on-board inductor
and a 70-nH to 270-nH on-interposer inductor are needed. Toolarge or too small inductance cannot be used, because of the
tradeoff between the inductance and the parasitic resistance.
When the inductance is too small, the inductor cannot store
enough energy to boost the voltage. When the inductance is toolarge, on the other hand, the inductor also cannot store enoughenergy because of the large parasitic resistance.
Figure 11 shows the simulated dependence of the rising time (trise)on the inductance in the two types of inductors. Figure 12 shows
the simulated waveforms of the boost converter. trise is defined as
the time to boost Vout from 0V to 15V as shown in Figure 12. The
graph in Figure 11 is not smooth, because Vout of 15V is achievedby several pulses as shown in Figure 12. To realize short trise, therange of inductance is limited by 130nH to 260nH for the oninterposer inductor, and 110nH to 330nH for the on-board
inductor. The reason for the optimum inductance region is similar
to the previous discussion.
Figure 13 shows the simulated inductance dependence of energy
consumption (Eloss) during boosting in the two types of inductors.
Eloss is calculated from equation (5) using VDD, the input current
1000
On-interposer L00

On-board L

50 100 150 200 250 300 350 400 450 500

Vout [V]0

50 100 150 200 250 300 350 400 450 500

t rise0

VDD ⋅ I in dt

To demonstrate the performance of the boost converter with the
optimized inductor in the chapter 2, the boost converter with the
270-nH on-board inductor shown Table1 is fabricated andmeasured. Figure 14 shows the microphotographs of the on-board
spiral inductor and the fabricated boost converter LSI where thehigh voltage MOSFET’s are integrated. The area of the inductor
is 5mm by 5mm, and the area of the boost converter LSI is

15
10

trise

0

(5)

3. Measurement results

20

Iin [mA]

0

Optimal region
250nH - 320nH

When the on-interposer inductor is used, Eloss is minimum ataround 400nH. This optimal range, however, does not match therange shown in Figures 10 and 11. In contrast, the inductance
range from 250nH to 320nH is optimal with the on-board inductor.
This is the best design point which meets all requirements
including the high output voltage, the fast rising time, the low
energy consumption, and the area limitation of 25mm2, because
this range is also within optimal region as shown in Figures 10
and 11. If the thicker metal is available in the on-interposer
inductor, the boost converter with the on-interposer inductor will
also achieve the similar performance as that with the on-board
inductor.

Inductance [nH]

Clock [V]10

Eloss = ∫Figure 11. Simulated dependence of rising time on inductancein two types of inductors.

520(Iin), and trise shown in Figure 9.

400

Optimal region
110nH - 330 nH

On-board L

30

Figure 13. Simulated inductance dependence of energy
consumption during boosting in two types of inductors.

Optimal region
130nH - 260 nH

200

On-interposer L

40

Inductance [nH]

800
600

50

VDD

200
150
100
50
0

VOUT

Clk

5

VSS
On-board Spiral Inductor(5mm x 5mm)

0
0

200

400

600

Time [ns]800

20V CMOS process(0.35mm × 0.50mm)

Figure 14. Microphotographs of on-board spiral inductor
and fabricated boost converter LSI where high voltage
MOSFET’s are integrated.

1000

Figure 12. Simulated waveforms of boost converter.

90

5. Acknowledgment

Table 2. Summary of key features of proposed boost converterand conventional charge pump.
Proposedboost converter(Measured)Supply voltage

0.175mm2 (15%)

1.19mm2 (100%)(0Î15V)

0.92µs (27%)

3.45µs (100%)

Energy during boost(0Î15V)

30nJ (12%)

253nJ (100%)

Energy during write (a.u.)

Memorycore

Others

6. REFERENCES

1.8V

Chip area
Rising time

The authors appreciate S. Ohshima, T. Hara, Y. Watanabe, T.
Futatsuyama and G. Iwasaki and Toshiba NAND team for theirsupport and chip fabrication.

Conventionalcharge pump
(Simulated)

Chargepump

Memorycore
Chargepump

Conventional Conventional
3.3V NAND [2] 1.8V NAND
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Boost
converter

Total
-68%
Memorycore
This work
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T. Arizono, T. Hisada, S. Miyamoto, M. Noguchi, T.
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Maruyama, K. Ino, S. Ohshima, “A 120mm2 16Gb 4-MLC
NAND Flash Memory with 43nm CMOS Technology,”IEEE International Solid-State Circuits Conference, pp.430431, 2008.

Figure 15. Comparison of the energy during write between
conventional 3D-SSD with charge pump and proposed 3D-SSD
with the boost converter.
0.35mm by 0.50mm. The measured parasitic resistance of theinductor is 1.05Ω. Table 2 summarizes measured key features ofthe boost converter and the conventional charge pump for typical
NAND flash memory. Measured energy consumption to 15V is
30nJ which is 12% of the charge pump, and the rising time is
0.92ns which is 27% of the charge pump. The area of the highvoltage MOSFET’s is 0.175mm2 which is 15% of the charge
pump. Figure 15 shows the comparison of the energy during write
between the conventional 3D-SSD with the charge pump and the
proposed 3D-SSD with the boost converter. By decreasing VDD of
the NAND from 3.3V to 1.8V, the total energy during write of a
NAND flash memory decreases by 68% compared with theconventional 3.3V NAND because the energy of the high voltage
generator decreases by 88% compared to the charge pump. In the
charge pump, the number of stage will increase when the VDD islowered to 1.8V, and therefore energy loss by MOS diodes
increases. In contrast, since the boost converter achieves 20-V
program voltage with single-stage circuit, the energy loss does notincrease. In this way, the proposed spiral inductor design of theboost converter contributes to the low power and the fast writeoperation of the 3D SSD.

[4] K. Ishida, T. Yasufuku, S. Miyamoto, H. Nakai, M.
Takamiya, T. Sakurai, and K. Takeuchi, “A 1.8V 30nJ
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4. Conclusion[7] A. Davoudi, J. Jatskevich, and T.D. Rybel, “NumericalState-space Average-value Modeling of PWM DC-DC
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The design methodology of the inductor of the boost converter forthe 3D SSD is proposed. The on-board inductor from 250nH to
320nH is the best design point which meets all requirements
including the high output voltage above 20V, the fast rising time,
the low energy consumption, and the area below 25mm2. Byusing the boost converter with the proposed inductor, the energy
during write-operation of the proposed 1.8-V 3D-SSD isdecreased by 68% compared with the conventional 3.3-V 3D-SSD
with the charge pump.

[8] S. Mohan, M. Hershenson, S. Boyd, and T. Lee, "Simple
Accurate Expressions for Planar Spiral Inductances," IEEE
Journal of Solid-Sate Circuits, vol. 34, no. 10,pp. 1419-1424,
Oct. 1999.

91