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Large-Current Output Digital Gate Driver for 6500 V,
1000 A IGBT Module to Reduce Switching Loss andCollector Current OvershootKohei Horii, Hiroki Yano, Katsuhiro Hata , Member, IEEE, Ruizhi Wang, Kazuto Mikami, Kenji Hatori,
Koji Tanaka, Wataru Saito , Senior Member, IEEE, and Makoto Takamiya , Senior Member, IEEE

Abstract—An 8-bit digital gate driver (DGD) using a half-bridge
digital-to-analog converter IC and two power MOSFETs is proposed
to enable the output voltage swing of ±15 V and the large gate
current up to 28 A to reduce the switching loss (ELOSS ) andthe collector current overshoot (IOVERSHOOT ) in a high-voltage,large-current IGBT module (HVIGBT) rated at 6500 V and 1000 A.
By using the DGD to drive HVIGBT, the effectiveness of the active
gate driving (AGD) is demonstrated for the first time in the world in
the high-voltage and large-current range of 3.0–4.5 kV, 1000 A. The
values of 1000 A, 4500 V, and ±15 V are the world’s highest records
in AGD. For the purpose of investigating the optimum gate driving
waveforms of AGD for HVIGBT, four different gate drive methods
are compared in detail by measurements at 3.6 kV, 1000 A, andthe stop-and-go gate driving is selected from a cost–performance
perspective. Finally, a design guideline of AGD for HVIGBTs isclarified. The design guideline is to align the two peak heights ofthe collector current waveforms, thereby minimizing ELOSS and
IOVERSHOOT .
Index Terms—Gate driver, IGBT, loss, overshoot.

I. INTRODUCTION
HE needs for power electronics’ applications in the highvoltage, large-current area, such as renewable energy andhigh-voltage dc transmission systems, are rapidly increasing torealize the carbon neutral society. Thus, it is very importantto reduce the losses of the high-voltage, large-current powerdevices. Active gate drivers (AGDs), which control gate waveforms during the switching transient of power devices, andT

Manuscript received 7 October 2022; revised 23 January 2023; accepted
13 March 2023. Date of publication 20 March 2023; date of current version
19 May 2023. This work was supported by NEDO under Grant JPNP21009.
Recommended for publication by Associate Editor F. Luo. (Corresponding
author: Makoto Takamiya.)
Kohei Horii, Hiroki Yano, Katsuhiro Hata, Ruizhi Wang, and Makoto
Takamiya are with the Institute of Industrial Science, The University of Tokyo, Tokyo 153-8505, Japan (e-mail: horii@iis.u-tokyo.ac.jp;
hyano@iis.u-tokyo.ac.jp; khata@iis.u-tokyo.ac.jp; oueichi@iis.u-tokyo.ac.jp;
mtaka@iis.u-tokyo.ac.jp).
Kazuto Mikami, Kenji Hatori, and Koji Tanaka are with the Mitsubishi
Electric Corporation, Fukuoka 819-0192, Japan (e-mail: mikami.kazuto@
dp.mitsubishielectric.co.jp; hatori.kenji@dx.mitsubishielectric.co.jp; tanaka.
koji@ds.mitsubishielectric.co.jp).
Wataru Saito is with the Research Institute for Applied Mechanics, Kyushu University, Fukuoka 816-8560, Japan (e-mail:wataru3.saito@riam.kyushu-u.ac.jp).
Color versions of one or more figures in this article are available athttps://doi.org/10.1109/TPEL.2023.3259521.
Digital Object Identifier 10.1109/TPEL.2023.3259521

Fig. 1. (a) Voltage and current ratings of power devices and (b) supply voltage
and load current of measurements in previous papers on AGDs [1], [2], [3], [4],[5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20],[21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35],[36] by type of power devices.

digital gate drivers (DGDs), which digitize AGDs, have attracted
attention as technologies that simultaneously reduce both theswitching loss (ELOSS ) and the switching noise.
Fig. 1(a) shows the voltage and current ratings of powerdevices used in previous papers on AGDs by type of powerdevices [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12],[13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23],[24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34],[35], [36]. There have been few reports on AGDs of powerdevices above 3000 V and 1000 A. Fig. 1(b) shows the supply
voltage and the load current of measurements in previous papers
on AGDs by type of power devices [1], [2], [3], [4], [5], [6],[7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18],0885-8993 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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Fig. 2. (a) Definitions of gate current (IG ) and gate swing voltage (VSWING ).
(b) Maximum IG versus VSWING of previously reported DGDs [11], [19], [24],[25], [26] and requirements in HVIGBT.

[19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29],[30], [31], [32], [33], [34], [35], [36]. No measurements above
3600 V or 800 A are reported. Therefore, the effectiveness of
AGDs in high-voltage, large-current regions above 3600 V and800 A is unproven and unknown, even though the absolute valueof ELOSS increases in power electronics’ applications in thehigh-voltage, large-current area, making the need for ELOSS
reduction by AGDs increasingly important.
To solve the problem, the research contributions of this article
are the following two points.
1) This article is the first to demonstrate the advantages of
AGDs in a double pulse test at the world’s highest voltage(4.5 kV) and the largest load current (1000 A) using the6500 V, 1000 A IGBT modules, defined as high-voltage
IGBTs (HVIGBTs).
2) To enable the active gate driving in the 6500 V, 1000 A
IGBT module, a new DGD with a maximum gate current(IG ) of 28 A and the world’s largest gate swing voltage(VSWING ) of 30 V in DGDs is developed in this article.
Fig. 2(a) shows the definitions of IG and VSWING . Fig. 2(b)shows the maximum IG versus VSWING of the previously reported DGDs [11], [19], [24], [25], [26] and the requirements
in HVIGBT. The 6500 V, 1000 A IGBT module (CM1000HG130XA) used in this work requires a maximum IG of at least
10 A and the gate-to-emitter voltage (VGE ) of ±15 V or VSWING= 30 V. As shown in Fig. 2(b), however, none of the previously reported DGDs satisfy the above required specifications.
Therefore, in this article, a DGD that satisfies the required
specifications is newly developed.
In addition, a new DGD circuit technology combining a halfbridge digital-to-analog converter (HB DAC) IC and two power

MOSFETs is proposed to solve the problem of cost increase dueto the increased chip area of DGD ICs with large IG . By using
the proposed circuit technology, a DGD with large IG has beensuccessfully realized in the small chip area, namely at low cost.
This article is an extended version of the conference paper[37]. The two main additions to the conference paper [37] aredescribed as follows.
1) The conference paper [37] compared ELOSS and the collector current overshoot (IOVERSHOOT ) reduction of two
different gate drive methods, including the conventional
single-step gate driving (SGD) and the stop-and-go gate
driving (S&G) [20], which is a type of active gate driving.
In contrast, in this article, ELOSS and IOVERSHOOT offour different gate drive methods, two-variable digital gate
driving (2DG) with two slots, and four-variable digital gate
driving (4DG) with four slots in addition to the above twoare compared. The details of the four different gate drive
methods are described later in Fig. 10. In addition, in thisarticle, three types of active gate driving (S&G, 2DG, and
4DG) are compared in terms of ELOSS and IOVERSHOOT
reduction performance and in terms of test cost to findthe optimal gate driving parameters, and S&G is usedin subsequent measurements from a cost–performance
perspective. These details are explained in Section III.
2) In the conference paper [37], only the measured results ofthe double pulse tests under one condition of the power
supply voltage (VCC ) of 3.0 kV and the load current (IL )of 1000 A were shown because the proposed HB DAC
IC was broken by overvoltage when VCC was increased
to 3.6 kV. In contrast, in this article, the measured resultsof the double pulse tests under four conditions of VCC= 3.0 kV, 3.6 kV, 4.0 kV, and 4.5 kV, and IL = 1000 A,
suitable for the target 6500 V, 1000 A IGBT module, aresuccessfully obtained because the proposed HB DAC IC
is not broken by overvoltage by fully revising the PCB
design of DGD. As a result, VCC dependence of the ELOSS
reduction performance of the active gate driving, which
is most important for the target 6500 V, 1000 A IGBT
module, is clarified. In addition, a design guideline for the
optimum gate driving parameters of the active gate driving
for VCC changes is clarified. These details are explainedin Section IV.

II. DESIGN OF DGD USING HB DAC IC AND TWO POWER
MOSFETS
Fig. 3 shows a circuit schematic of the proposed DGD,
including HB DAC IC and two power MOSFETs (Q1 and Q2 :IRLZ34NS, 55 V, 30 A). This DGD is a two-stage gate drive
system: first the HB DAC IC drives the two power MOSFETs,
and then the two power MOSFETs drive the IGBT. DGD is acurrent-source gate driver. HB DAC IC does not include theoutput stage to drive IGBTs. The two power MOSFETs (Q1 andQ2 ) work as the output stage. If the output stage that can output
more than 20 A of IG , which is the target of this article, is also
integrated into the IC, the chip size will be huge and the cost will
be high, which is unacceptable. Therefore, in this article, a DGD

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Fig. 3. Circuit schematic of the proposed DGD, including HB DAC IC andtwo power MOSFETs.
Fig. 5.

Fig. 4.

Block diagram of the proposed HB DAC IC.

combining HB DAC IC and two power MOSFETs is proposed torealize a DGD that can output more than 20 A of IG with a
low-cost small-area IC. As shown in Fig. 3, the novelty of thiswork is that the power MOSFETs are used as the output stageof the gate driver to achieve large IG , and DGD operation isachieved by digitally controlling the gate amplitude (VGSH and
VGSL ) of the power MOSFETs operating in the saturation region
instead of the linear region using the proposed HB DAC IC toachieve the current-source gate driver. VDD1 and VDD2 are set
to 15 V to achieve VGE = ±15 V required for the target IGBT.
Figs. 4 and 5 show a block diagram of the proposed HB DAC
IC and a timing chart of DGD, respectively. As shown in Fig. 4,
HB DAC IC includes two DACs and two parallel-in serial-out
shift registers (PISOs) operating with different power supply
rails. For example, the high-side 16-bit input DAC controls
VGSH depending on the two sets of 8-bit inputs (H_nPMOS [7:0],
H_nNMOS [7:0]) given by PISO. By controlling the gate voltageof Q1 (VGSH ) (see Fig. 3) with a 16-bit input DAC (see Fig. 4), IG
can be digitally varied four times at turn-ON (see Fig. 5). The fourslots from t1 to t4 are determined by “Timing” signal, and t1 –t4
can be changed independently. The same is true for turn-OFF. To
control the low-side and high-side 16-bit input DACs four times
in four slots, 128-bit (=16 bits × 2 × 4 slots) control signals are

Timing chart of DGD.

required. The 128-bit control signals are provided by externallysupplied two-pin inputs (Scan In, Scan CLK) using a serial-inparallel-out shift register (SIPO) to reduce the number of input
pins. The edge detector generates a pulse signal from the risingand falling edges of externally supplied “Timing” signal. The
pulse signal works as a clock signal for PISO. The high-side
floating VSS varies between 0 and 30 V relative to the low-side
VSS . VDD3 and VDD4 for HB DAC IC are 3.5 or 4 V. The circuitdesign of the HB DAC IC is performed using CMOS transistors
with the gate-to-source and drain-to-source breakdown voltageof 5 V and the well-to-substrate breakdown voltage of 45 V ina 180 nm BCD process.
Fig. 6(a) and (b) show a circuit schematic and an equivalent circuit of the 16-bit input DAC for Q1, respectively. This
DAC has a similar circuit configuration to DGD with binary
weighted gate widths (WP , 2WP , 4WP , 8WP, 16WP , 32WP ,64WP , 128WP ) in the output stage [24]; however, the methodof operation is different. VGSH can be digitally controlled by
H_nPMOS [7:0] and H_nNMOS [7:0] on the principle of a shunt
regulator, where some of the eight pMOSFETs and some of theeight nMOSFETs in Fig. 6(a) are turned ON. This DAC has 16-bit
inputs; however, for simplicity, 8-bit digital signals H_nNMOS[7:0] are fixed and 8-bit digital signals H_nPMOS [7:0] are variedin this article. VGSH can be varied in 256 levels depending on
H_nPMOS [7:0], which is defined as H_nPMOS , where H_nPMOS
is an integer between 0 and 255. Similarly, H_nNMOS is an
integer between 0 and 255.
Fig. 7 shows a circuit schematic of the high-side PISO for one
bit (H_nPMOS [0] and H_nNMOS [0]). The actual HB DAC IC
includes eight sets of the circuits, as shown in Fig. 7, on the highside for 8-bit control. PISO consists of 12 clock-synchronized
set–reset flip-flops (FFs). In PISO, as shown in Fig. 5, eachtime the edge of the Timing signal occurred, the pulse signal
is provided and the data in FFs are shifted one bit to the rightto achieve IG control for five slots from t1 to t5 . PISO has twomodes: initial mode (Enable = low) and operating mode (Enable= high). In the initial mode, Enable is set to low to ensure that
IGBT is turned OFF even if the other input signals of DGD are

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Fig. 8. (a) Layout and (b) die micrograph of HB DAC IC fabricated with
180-nm BCD process.

Fig. 6. (a) Circuit schematic and (b) equivalent circuit of 16-bit input DAC
for Q1 .

Fig. 9.

Fig. 7. Circuit schematic of high-side PISO for one bit (H_nPMOS [0] and
H_nNMOS [0]).

not properly set. Specifically, as shown in Fig. 7, when Enable isset to low, FF6 is reset and H_nPMOS [0] is low, and FF12 is set
and H_nNMOS [0] is high. As a result, VGSH is 0 V and IGBT isdefinitely turned OFF. In the subsequent operating mode (Enable= high), during the period of IN = low, i.e., IGBT is OFF, thecontrol signals for the four slots from t1 to t4 (H_nPMOS1 [0]to H_nPMOS4 [0] and H_nNMOS1 [0] to H_nNMOS4 [0]) given
by SIPO are fed into FF2–FF5 and FF8–FF11. As shown in
Fig. 7, in this article, during t5 , H_nPMOS5 [0] is fixed to highand H_nNMOS5 [0] is fixed to low, resulting in H_nPMOS being
fixed to 255 and H_nNMOS to 0. Then, when IN = high, each

Photograph of PCB of DGD.

time the pulse signal is received, the data in FFs are shifted
one bit to the right to achieve five-slot IG control. The circuit
schematic of the low-side PISO is also similar to Fig. 7. Whenthe two CMOS inverters with IN input are removed from Fig. 7,
the circuit schematic of the low-side PISO is obtained.
Fig. 8(a) and (b) show a layout and a die micrograph of HB
DAC IC fabricated with 180-nm BCD process, respectively. The
die size is 2.5 mm × 1.0 mm. As explained in Fig. 3, note that the
DAC area is small (0.014 mm2 ) because the HB DAC IC does
not include the output stage of DGD. As a result, the proposed
HB DAC IC is low cost because of its small chip area, although
the DGD can output the maximum IG of 28 A.
Fig. 9 shows a photograph of PCB of DGD. As described in
Section I, PCB of DGD in this article makes the following threedesign revisions to PCB of DGD in the conference paper [37].
1) Transient-voltage-suppression diodes are added to VGSH ,VGSL , VDD3 , and VDD4 in Fig. 3 to prevent overvoltage
breakdown of the proposed HB DAC IC.
2) The two power MOSFETs (Q1 and Q2 ) are changed from
BSC094N06LS5 (60 V, 47 A) to IRLZ34NS (55 V, 30 A)
because IG of BSC094N06LS5 was too much for the output voltage of the HB DAC IC (VGSH , VGSL ), specifically,

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Fig. 11. Measured n dependence VGSH in SGD to demonstrate the successful
operation of 8-bit DAC at VDD3 = VDD4 = 3.5 V and 4 V and m = 60 and
110.

(Step 1) Examine the turn-ON delay (td(on) ) and the turn-ON
rise time (tr ) shown in the datasheet of IGBT and determinetTOTAL defined by the following:td(on) + tr < t1 + t2 + t3 + t4 ≡ tTOTAL .

Fig. 10. Timing charts of turn-ON measurements for four different gate drive
methods compared in this article. (a) Conventional SGD. (b) S&G gate driving.
(c) Two-variable digital gate driving with two slots. (d) Four-variable digital
gate driving with 560 ns × 4 slots.

IG is 15 A to 68 A at VGSH = VGSL = 3 V to 4 V in
BSC094N06LS5, while IG is 6 A to 25 A at VGSH =VGSL = 3 V to 4 V in IRLZ34NS.
3) Four isolated dc–dc converters for VDD1 –VDD4 aremounted on the PCB to stabilize the power supply to DGD.
III. COMPARISON OF FOUR DIFFERENT GATE DRIVE METHODS
IN 6500 V, 1000 A IGBT MODULE
In this article, the comparison of four different gate drive
methods in the 6500 V, 1000 A IGBT module is performed bymeasurements using the developed gate driver. In this article,
only IOVERSHOOT at turn-ON is discussed and the collector–
emitter voltage (VCE ) overshoot at turn-OFF is not discussed
because IOVERSHOOT is large, while the voltage overshoot issmall, being less than 500 V.
A. Definition of Four Different Gate Drive Methods
Fig. 10(a)–(d) show the timing charts of the turn-ON measurements for the four different gate drive methods compared inthis article, including the conventional SGD [see Fig. 10(a)], theS&G gate driving [20] [see Fig. 10(b)], 2DG with two slots [seeFig. 10(c)], and 4DG with 560 ns × 4 slots [see Fig. 10(d)].
The steps for determining the values of the slots (t1 –t4 ) in
the 4DG in Fig. 10(d) are explained below. As shown in Figs. 5
and 10(d), this DGD has a total of eight variables of freedom:t1 –t4 and n1 –n4 . However, since parameter optimization ofeight variables is difficult to implement, t1 –t4 were fixed andparameter optimization of four variables of n1 –n4 was performedin this article.

(1)

tTOTAL is set to 2 ms because td(on) = 1.2 ms and tr = 0.3 ms
for this HVIGBT.
(Step 2) Determine t1 –t4 by the following equation:
tTOTAL.
(2)
4
The calculation results in t1 = t2 = t3 = t4 = 500 ns. In themeasurements, however, instead, t1 = t2 = t3 = t4 = 560 ns,
as shown in Fig. 10(d), because the lower limit of the time stepof the signal generator that generates “Timing” signal in Fig. 5,
which determines the values of t1 –t4 , is 80 ns.
S&G, 2DG, and 4DG are a kind of active gate driving. n isvaried in SGD, n1 is varied in S&G, (n1 and n2 ) are varied in
2DG, and (n1 , n2 , n3 , and n4 ) are varied in 4DG, where n and n1 –n4 are integers between 0 and 255. m in SGD is 60 or 110 in thisarticle. SGD with varied n emulates a conventional gate driverwith varied gate resistance. 2DG and 4DG are based on the article
presented in [11]. The optimal values of the variables (n1 and n2 )in 2DG and (n1 , n2 , n3 , and n4 ) in 4DG (defined as gate vectors
in this article) are searched by repeated measurements using
the simulated annealing algorithm [11]. Details are explainedlater. S&G was proposed to reduce the effort of searching forthe optimal gate vectors of 4DG [20]. As shown in Fig. 10(b),in S&G, IG waveform of “medium–zero–strong” is used. The
advantage of S&G is that it has only one variable (n1 ) whileachieving almost the same performance as 4DG [20].
t1 = t2 = t3 = t4 =B. Measurements of Gate DriverFig. 11 shows the measured n dependence VGSH in SGD todemonstrate the successful operation of 8-bit DAC at VDD3
= VDD4 = 3.5 V and 4 V and m = 60 and 110. VGSH ismonotonically increasing with n, although DAC is nonlinear.
The maximum output current of DAC is 100 mA. Fig. 12 shows
the measured n dependence of IG in SGD to demonstrate thesuccessful operation of 8-bit DGD at VDD3 = VDD4 = 3.5 V
and 4 V and m = 60 and 110. To investigate the performance

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Fig. 12. Measured n dependence of IG in SGD to demonstrate the successful
operation of 8-bit DGD at VDD3 = VDD4 = 3.5 V and 4 V and m = 60 and
110.

Fig. 13. Circuit schematic of double pulse test using DGD and two IGBT
modules (Q3 and Q4 : CM1000HG-130XA, 6500 V, 1000 A).

Fig. 15. (a) Overall view of the measured ELOSS versus IOVERSHOOT offour different gate drive methods for comparison at VCC = 3.6 kV. (b) Enlarged
view of (a).

Fig. 14. Measurement setup of double pulse test using DGD and IGBT
modules.

of DGD itself, a 100 µF capacitor is connected to the output
of DGD and IG is measured. IG is monotonically increasing
with n, although it is nonlinear. The maximum IG is 28 A. In
all following measurements in this article, measurements are
performed under condition of VDD3 = VDD4 = 3.5 V and m =110, with the maximum IG of 10 A because 10 A is enough toactively drive the target IGBT.
C. Measurements of ELOSS Versus IOVERSHOOT in 6500 V,
1000 A IGBT Module
Figs. 13 and 14 show a circuit schematic and a measurement
setup of the double pulse test using DGD and two IGBT modules(Q3 and Q4 : CM1000HG-130XA, 6500 V, 1000 A), respectively. In the measurement, as shown in Fig. 13, the proposed
DGD is isolated by the four isolated dc–dc converters, as shownin Fig. 9 (CHS1202412 for VDD1 and VDD2 and MGS100505
for VDD3 and VDD4 ) and the signal isolator IC (IL260-3E).

In this experiment, the signal isolator IC was used to simplify
the measurement setup. Optical isolators, however, have beenoriginally used in the HVIGBTs. Therefore, if the signal isolator
IC is replaced with the optical isolator, the proposed DGD will
be able to drive the high-side IGBT (Q3 ), as shown in Fig. 13,
normally without causing CMRR-induced malfunctions.
The measurement conditions are room temperature and IL of
1000 A. The power supply voltage (VCC ) of the main circuit in
Section III is 3.6 kV.
Fig. 15(a) and (b) show the overall view of the measured
ELOSS versus IOVERSHOOT of four different gate drive methods
for comparison at VCC = 3.6 kV and an enlarged view ofFig. 15(a), respectively. This article discusses the switching at
turn-ON and does not discuss the switching at turn-OFF because
IOVERSHOOT is large, VCE overshoot at turn-OFF is small, being
less than 500 V in the HVIGBT. The definition of ELOSS atturn-ON is given as follows:
ELOSS = t1
IC VCE dt(3)t0

where t0 is the time when IC reaches 10% of IL , and t1 is thetime when VCE reaches 10% of VCC .

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Fig. 16. Gate vectors and measured waveforms from point A to point I in Fig. 15. (a) Point A (4DG). (b) Point B (SGD). (c) Point C (SGD). (d) Point D (2DG).
(e) Point E (S&G). (f) Point F (S&G). (g) Point G (SGD). (h) Point H (S&G). (i) Point I (SGD).

TABLE IRANKING OF FOBJ OF POINT A TO POINT I IN FIG. 15 AND DETAILSOF EACH POINT

For S&G, the measured results at two different t2 are shown
because t2 is the second most important parameter after n1
in S&G. To quantitatively compare the different gate drive
methods, an evaluation function (fOBJ ) in (4) is defined as aperformance index of gate driving [11], and it is discussed thata gate driving with small fOBJ is an excellent gate driving

2 
2
IOVERSHOOT
ELOSS
+
(4)
fOBJ =ELOSS,MAX
IOVERSHOOT,MAX
where ELOSS, MAX is 27 J and IOVERSHOOT, MAX is 5600 A
in this article. The dashed concentric curves in Fig. 15(a) and(b) show the contour of fOBJ from 0.1 to 1.0. Table I presents

the ranking of fOBJ of Point A to Point I, the representative
points in Fig. 15(a) and (b), and the details of each point. Fig. 16
shows the gate vectors and measured waveforms from Point A to
Point I.
A way to estimate IGBT switching characteristics, such as
dVCE /dt, dIC /dt, ELOSS , and IOVERSHOOT , and the controllable
performance range when applying this DGD to unknown IGBTs
will be explained. The DGD is the current-source gate driver, as
described in Fig. 3. Actually, as the measured waveform of IG in
Fig. 16(c) shows, IG is almost constant from VGE of −15 V tothe threshold voltage of IGBT. Therefore, by modeling the DGD
as a constant current source and performing SPICE simulations
to drive IGBTs, the switching characteristics of IGBTs can be
estimated. Furthermore, the controllable performance range ofthe switching characteristics can be estimated by varying thevalue of the constant current source in the IG range of DGD, as
shown in Fig. 12.
1) Conventional SGD: The black lines in Fig. 15(a) and(b) show the tradeoff curves of the conventional SGD [seeFig. 10(a)] with varied n from 138 to 255. The tradeoff curves
emulate the conventional gate driving with varied gate resistance, and this study aims to achieve a performance lower left
than this tradeoff curve, i.e., low ELOSS and low IOVERSHOOT ,by active gate driving. Fig. 16(g) and (i) show the measured
waveforms at Point G and Point I, where IG is maximum andminimum in SGD, respectively.
2) S&G Gate Driving: The blue and red lines in Fig. 15(a)and (b) show the measured results of S&G [see Fig. 10(b)] withvaried n1 from 0 to 255 at t2 = 720 ns and 1040 ns, respectively.
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Fig. 18. ELOSS versus IOVERSHOOT for all 2745 measured points in search
process in 4DG at VCC = 3.6 kV.

Fig. 17. Measured n1 dependence of (a) ELOSS , (b) IOVERSHOOT , and (c)fOBJ in S&G.

IOVERSHOOT , and fOBJ in S&G, respectively. When n1 is varied
from 0 to 255, ELOSS has the maximum value, IOVERSHOOT
has the minimum value, and fOBJ has the minimum value. Bychanging the input data given to “Scan In” terminal in Fig. 4
from an external signal generator, the value of n1 was changed
from 0 to 255, and the measurement was repeated 256 times toobtain the results, as shown in Fig. 17.
In S&G at t2 = 720 ns, the measured point at n1 = 236 is
the best point where fOBJ is the minimum, which is Point E
in Fig. 15(b). The measured waveforms at Point E are shown in
Fig. 16(e). Similarly, in S&G at t2 = 1040 ns, the measured point
at n1 = 234 is the best point where fOBJ is the minimum, which
is Point F in Fig. 15(b). The measured waveforms at Point F are
shown in Fig. 16(f). As shown in Fig. 17(b), IOVERSHOOT is
minimum at n1 = 234, so fOBJ is also minimum at n1 = 234. The
reason why IOVERSHOOT is minimum at n1 = 234 is explained
below. When n1 is decreased from 234, IOVERSHOOT increases
because the first peak of IC in Fig. 16(f) decreases and the second
peak of IC increases; thus, IOVERSHOOT determined by thesecond peak increases. In contrast, increasing n1 from 234 also
increases IOVERSHOOT because the first peak of IC in Fig. 16(f)increases and the second peak of IC decreases, thus increasing
IOVERSHOOT determined by the first peak. Therefore, as shownin Fig. 16(e) and (f), by adjusting n1 to align the two peak heights
of IC waveforms, ELOSS and IOVERSHOOT are reduced and thebest point with the smallest fOBJ is achieved in S&G. When t2
is increased in S&G from 720 ns (Point E) to 1040 ns (PointF), as shown in Fig. 15(b) and Table I, IOVERSHOOT decreases
from 1650 to 1450 A as the optimum n1 decreases from 236 to
234, while ELOSS increases from 6.35 to 7.37 J. On the other
hand, as shown in Table I, fOBJ at Points E and F are almost thesame, and therefore, it can be said that S&G can tune ELOSS and
IOVERSHOOT of the best point by varying t2 and n1 .
At Point H, as shown in Fig. 15(a), IOVERSHOOT is at a
maximum of 5330 A, as shown in Fig. 16(h), because, as shown

TABLE IIDETAILS OF TOP TEN RANKING OF FOBJ IN 2745 MEASURED RESULTS OF 4DG

in Fig. 10(b), at the moment H_nPMOS changes from 0 to 255,
H_nNMOS also changes from 110 to 0, resulting in the maximum
IG of 14 A in Fig. 16(h).
3) 2DG and 4DG: Points D and A in Fig. 15(a) and (b) are thebest points where the smallest fOBJ is achieved by repeatedly
measuring and searching for n1 to n2 and n1 to n4 using thesimulated annealing algorithm [11] for 2DG [see Fig. 10(c)] and4DG [see Fig. 10(d)], respectively. In the following, the detailsof the best point search method in 4DG will be explained, and theexact same method is used for 2DG. In 4DG, using the methodof Miyazaki et al. [11], the simulated annealing algorithm wasapplied to repeatedly perform switching measurements whilevarying the gate vectors (n1 , n2 , n3 , and n4 ), measure ELOSS and
IOVERSHOOT , calculate fOBJ , and search for the gate vector thatminimizes fOBJ .
Fig. 18 shows ELOSS versus IOVERSHOOT for all 2745 measured points in the search process in 4DG at VCC = 3.6 kV.
Fig. 18 also shows the tradeoff curve of the conventional SGD
for comparison. 4DG has many measurement points to the lower
left of the tradeoff curve of SGD. Fig. 19 shows the time seriesof gate vectors, ELOSS , IOVERSHOOT , and fOBJ for 2745 searchmeasurements in 4DG. The simulated annealing algorithm isused to search the gate vectors (n1 , n2 , n3 , and n4 ). It can be seenthat fOBJ varies greatly at the beginning of the search, while at theend of the search, fOBJ converges to a constant value, indicatingthat the search has been completed. Table II presents the details

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of the top ten ranking of fOBJ in all 2745 measured results of
4DG. The top ten fOBJ ’s occur near the 1000th search, not at theend of the search. Therefore, in this article, the 966th measured
point that achieved the smallest fOBJ is adopted as the best pointin 4DG (Point A) in this study. The measured waveforms of thebest points (Point A and Point D) of 4DG and 2DG are shownin Fig. 16(a) and (d), respectively.
D. Comparison of Four Different Gate Drive Methods

Fig. 19. Time series of gate vectors, ELOSS , IOVERSHOOT , and fOBJ for2745 search measurements in 4DG.

Fig. 20. (a) Overall view of the measured VCC dependence of ELOSS versus
IOVERSHOOT of the conventional SGD and S&G at t2 = 560 ns at room
temperature and the load current of 1000 A. (b) Enlarged view of (a).

The four different gate drive methods for the 6500 V, 1000 A
IGBT module are compared. As shown in Table I, fOBJ ranks
Point A (best point in 4DG) in first place, Point F (best point
in S&G with t2 = 1040 ns) in second place, Point E (bestpoint in S&G with t2 = 720 ns) in third place, and Point D(best point in 2DG) in fourth place, with 4DG showing thebest performance. As shown in Fig. 15(b), all four points arelower left than the tradeoff curve of SGD, resulting in lower
ELOSS and IOVERSHOOT than SGD by the active gate driving.
As shown in Fig. 15(b), Table I, and Fig. 16(a)–(c), comparedwith Point B of SGD, Point A (best point in 4DG) reduces
ELOSS from 7.91 to 7.04 J by 11% under IOVERSHOOT -aligned
condition. Compared with Point C of SGD, Point A (best pointin 4DG) reduces IOVERSHOOT from 1580 to 1400 A by 11%
under ELOSS -aligned condition.
Here, the similarities among 4DG, 2DG, and S&G are discussed. Interestingly, comparing the best waveforms of 4DG,
2DG, and S&G in Fig. 16(a) and (d)–(f), the gate vectors aredifferent, while VGE and IG waveforms are similar, and IC
waveforms have two peaks with equal peak height. Therefore,aligning the two peak heights of IC waveforms in the target
IGBT is a common design guideline for active gate drivingthat minimize fOBJ . Also, comparing Fig. 16(a) and (d)–(f), IG
waveforms are “medium–(almost) zero–strong” in common. As
shown in Fig. 12, IGs of gate vectors n3 = 150 and n4 = 130 in
Point A (best point in 4DG) and n2 = 130 in Point D (best pointin 2DG) are almost zero. The same is true for the top ten rankingof fOBJ of 4DG in Table II, where IG waveforms are “medium(n1 and n2 )–(almost) zero (n3 and n4 )–strong.” Therefore, as
shown in Fig. 10(b)–(d), although 4DG, 2DG, and S&G havedifferent gate driving waveform constraints, the derived optimal
gate driving waveforms are all “medium–(almost) zero–strong”
in common, and their fOBJ ’s are not significantly different, asshown in Table I. Here, the physical reasons why AGD with IG
waveforms of “medium–(almost) zero–strong” perform better
than the conventional SGD are explained. AGD achieves smaller
fOBJ than the conventional SGD by shortening the turn-ON delayin the first medium drive, reducing IOVERSHOOT in the next
(almost) zero drive and reducing ELOSS in the last strong drive.
On the other hand, the test cost to find the optimum gate
vectors for 4DG, 2DG, and S&G is very different. The numberof combinations in gate vector for 4DG, 2DG, and S&G is (28 )4(>109 ), (28 )2 (>104 ), and 28 (=256), respectively. In this article,
as shown in Fig. 19, the optimization of (28 )4 gate vectors of
4DG is successfully performed in only 2745 iterations using thesimulated annealing algorithm. The test cost for 4DG is still highAuthorized licensed use limited to: University of Tokyo. Downloaded on June 03,2023 at 02:36:32 UTC from IEEE Xplore. Restrictions apply.

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Fig. 21.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 38, NO. 7, JULY 2023

Gate vectors and measured waveforms from Point J to Point L in Fig. 20 at VCC = 3.0 kV.

because 2745 measurements in 4DG are more than ten times
higher than 256 measurements in S&G. As shown in Table I,
fOBJ of Point A (best point in 4DG) is 0.361, while fOBJ of Point
E (best point in S&G with t2 = 720 ns) is 0.377, and that of Point
F (best point in S&G with t2 = 1040 ns) is 0.376, showing only asmall difference. Therefore, in this article, S&G will be used insubsequent measurements from a cost–performance perspective.
Adopting S&G eliminates the need for the four slots (t3 , t4 , t8 ,and t9 ) in Fig. 5 and, thus, has the advantage of reducing thecircuit size of the HB DAC IC, as shown in Fig. 4.
IV. VCC DEPENDENCE OF ACTIVE GATE DRIVE IN 6500 V,
1000 A IGBT MODULE
In the target 6500 V, 1000 A IGBT module, the VCC dependence of ELOSS reduction effect of the active gate driving
is very important yet unknown. For low-voltage, small-current
IGBTs (rated 600 V, 100 A), the load current dependence andthe temperature dependence of ELOSS reduction effects of theactive gate drive (4DG and S&G) over the conventional SGD
have been quantitatively investigated in [16], while the VCC
dependence has not been reported. Therefore, in this article, theVCC dependence of ELOSS reduction effect of the active gate
driving over the conventional SGD in the 6500 V, 1000 A IGBT
module is investigated in detail by measurements.
Fig. 20(a) and (b) show the overall view of the measured VCC
dependence of ELOSS versus IOVERSHOOT of the conventional
SGD and S&G at t2 = 560 ns at room temperature and IL of
1000 A and an enlarged view of Fig. 20(a), respectively. Notethat since the IGBT samples are different in Figs. 15 and 20,
the measured results of the two do not match. As shown in
Fig. 20(a), when VCC increases from 3.0 to 4.5 kV, both ELOSS
and IOVERSHOOT increase, as expected. The points of interest,
Point J to Point U, are defined in Fig. 20(a) and (b). The points ofmaximum IG (n = 255) of SGD at VCC = 3.0 kV, 3.6 kV, 4.0 kV,
and 4.5 kV are defined as Point J, Point M, Point P, and Point S,
respectively. The best points with the smallest fOBJ of S&G at
VCC = 3.0 kV, 3.6 kV, 4.0 kV, and 4.5 kV are defined as Point
L, Point O, Point R, and Point U, respectively. These four points

are lower left than the tradeoff curve for the conventional SGD,
indicating that the S&G advantage is maintained even when
VCC varies from 3.0 to 4.5 kV. The points of SGD with the same
IOVERSHOOT as the best point of S&G at VCC = 3.0 kV, 3.6 kV,
4.0 kV, and 4.5 kV are defined as Point K, Point N, Point Q, andPoint T, respectively.
Figs. 21–24 show the gate vectors and the measured waveforms from Point J to Point U at VCC = 3.0 kV, 3.6 kV, 4.0 kV,
and 4.5 kV, respectively. As shown in Figs. 21(a), 22(a), 23(a),and 24(a), the maximum IG is 8 A. At VCC = 3.0 kV, as shownin Figs. 20 and 21, compared with Point K of the conventional
SGD, Point L (best point in S&G) reduces ELOSS from 7.03 to
4.78 J by 32% under IOVERSHOOT -aligned condition. At VCC= 3.6 kV, as shown in Figs. 20 and 22, compared with Point Nof the conventional SGD, Point O (best point in S&G) reduces
ELOSS from 7.01 to 6.10 J by 13% under IOVERSHOOT -aligned
condition. At VCC = 4.0 kV, as shown in Figs. 20 and 23,
compared with Point Q of the conventional SGD, Point R (bestpoint in S&G) reduces ELOSS from 8.38 to 6.94 J by 17% under
IOVERSHOOT -aligned condition. At VCC = 4.5 kV, as shownin Figs. 20 and 24, compared with Point T of the conventional
SGD, Point U (best point in S&G) reduces ELOSS from 11.7 to
9.88 J by 16% under IOVERSHOOT -aligned condition.
In summary, in VCC range from 3.0 to 4.5 kV, the proposed S&G reduces ELOSS by 13%–32% compared with theconventional SGD under IOVERSHOOT -aligned condition. This
result indicates that applying the proposed S&G to high-voltage
converter/inverter systems using the HVIGBTs would reduce
ELOSS by 13%–32%; thus, the benefit of the proposed AGD tohigh-voltage applications is significant. Interestingly, similar to
Section III, comparing the best waveforms of S&G in Figs. 21(c),22(c), 23(c), and 24(c), IC waveforms have two peaks withequal peak height by tuning n1 regardless of VCC . Table III
presents VCC dependence of the optimum n1 in S&G, as shownin Figs. 21(c), 22(c), 23(c), and 24(c). The common design
guideline, as described in Section III, for active gate driving thatminimize fOBJ , aligning the two peak heights of IC waveforms,
is successfully achieved by increasing n1 from 234 to 242 as
VCC increases from 3.0 to 4.5 kV.

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HORII et al.: LARGE-CURRENT OUTPUT DGD FOR 6500 V, 1000 A IGBT MODULE

Fig. 22.

Gate vectors and measured waveforms from Point M to Point O in Fig. 20 at VCC = 3.6 kV.

Fig. 23.

Gate vectors and measured waveforms from Point P to Point R in Fig. 20 at VCC = 4.0 kV.

Fig. 24.

Gate vectors and measured waveforms from Point S to Point U in Fig. 20 at VCC = 4.5 kV.

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TABLE IIIVCC DEPENDENCE OF OPTIMUM N1 IN S&G

TABLE IV
COMPARISON TABLE OF DGDS

minimize fOBJ . The high-speed operating limit of the developed
DGD, i.e., the minimum value of time slot (t1 –t4 and t6 –t9 ), is
determined by the rise time and fall time of VGSH and VGSL in
Fig. 5. The minimum value of time slot is estimated to be about
150 ns because the rise time of VGSH is 110 ns and the fall timeof VGSH is 40 ns, as shown in the measured VGSH waveform in
Fig. 16(f). Therefore, this DGD with a minimum time step of
150 ns would be applicable to silicon power devices (IGBTs andpower MOSFETs) but not to WBG devices (SiC and GaN) because
the WBG devices require the time step of 100 ns or less. The time
step, however, can be shortened by modifying the HB DAC IC
output driving force to be stronger. Although this article focusedon IOVERSHOOT as an evaluation index of switching noise, it
is also possible to reduce electromagnetic interference (EMI)with DGD. Articles [21], [38], and [39] report the measurement
results of minimizing ELOSS while meeting EMI regulations by
optimizing gate vectors using DGD. It is possible to achieve thesimilar EMI countermeasures as above using the proposed DGD
in this article.
REFERENCES

Table IV presents a comparison table of DGDs. The proposed
DGD using HB DAC IC and two power MOSFETs achieves thelargest VSWING of 30 V and the second largest IG of 28 A in
DGDs. This article is the first to demonstrate the advantages of
DGD in HVIGBT.
V. CONCLUSION
This article is the first to demonstrate the advantages of
AGDs in the double pulse test at the world’s highest voltage(4.5 kV) and the largest load current (1000 A) using the 6500 V,
1000 A IGBT modules. To enable the active gate driving in the6500 V, 1000 A IGBT module, a new DGD circuit technology
combining HB DAC IC and two power MOSFETs is proposed
to realize a DGD that can output large IG up to 28 A with a
low-cost small-area IC. The four different gate drive methods,
including SGD, S&G, 2DG, and 4DG, are compared by measurements at 3.6 kV, 1000 A in terms of ELOSS and IOVERSHOOT
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Kohei Horii received the B.S. degree from The University of Electro-Communications, Tokyo, Japan,
in 2020, and the M.S. degree from The Universityof Tokyo, Tokyo, Japan, in 2022, both in electronicengineering.
Since 2022, he has been with Sony Semiconductor
Solutions Corporation, Kanagawa, Japan, where he iscurrently engaged in the design of analog-to-digitalconverter for CMOS image sensors.

Hiroki Yano received the B.S. degree in electricalengineering from the Tokyo Institute of Technology,
Tokyo, Japan, in 2022. He is currently working toward
the M.S. degree in electrical engineering with The
University of Tokyo, Tokyo, Japan.
His research interests include integrated circuits for
power electronics.

Katsuhiro Hata (Member, IEEE) received the M.S.
degree in advanced energy and the Ph.D. degree inelectrical engineering from the University of Tokyo,
Tokyo, Japan, in 2015 and 2018, respectively.
He is currently a Research Associate with the Institute of Industrial Science, University of Tokyo. His
research interests include hybrid dc–dc converters,
digital active gate driving, wireless power transfer,and e-mobility for transportation.
Dr. Hata was a recipient of the Best Paper Award in
2018 IEEE Transportation Electrification Conference
and Expo, Asia-Pacific.

Ruizhi Wang received the B.S. degree in optoelectronic information science and engineering from Beijing Jiaotong University, Beijing, China, in 2017, andthe M.Eng. degree in electronic engineering in 2020
from The University of Tokyo, Tokyo, Japan, where
he is currently working toward the Ph.D. degree inelectronic engineering.
His research interests include integrated circuits forhigh-energy efficiency and high-speed computing.

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 38, NO. 7, JULY 2023

Kazuto Mikami received the B.E. and M.E. degrees in electrical engineering from Nihon University,
Tokyo, Japan, in 2015 and 2017, respectively.
He has joined Power Device Works, Mitsubishi
Electric Corporation, Fukuoka, Japan. He worked
in the application engineering section from 2017 to2020. Since 2021, he has been working in the highvoltage design and development section.

Kenji Hatori received the B.S. and M.S. degrees inelectronic engineering from Osaka University, Suita,
Japan, in 2004 and 2006, respectively. He is currently
working toward the Ph.D. degree in power electronics
with the University of Bremen, Bremen, Germany.
He is currently a Senior Manager of high-voltage
device design and development section with Mitsubishi Electric Corporation, Fukuoka, Japan. He
worked on the research of reliable design and reliability test of HVIGBT modules. His research interests include the reliability issues of high-voltage SiC
modules.

Koji Tanaka received the B.E. and M.E. degrees inelectrical engineering from Meiji University, Tokyo,
Japan, in 2012 and 2014, respectively.
In 2014, he has joined Power Device Works with
Mitsubishi Electric Corporation, Fukuoka, Japan,
where he is currently involved in the developmentof IGBTs and power diodes.

Wataru Saito (Senior Member, IEEE) received theB.Eng., M.Eng., and Dr.Eng. degrees in electrical andelectronics engineering from the Tokyo Institute ofTechnology, Tokyo, Japan, in 1994, 1996, and 1999,
respectively.
In 1999, he joined the Toshiba Corporation,
Kawasaki, Japan, where he was engaged in the development of power semiconductor devices. Since 2019,he has been with Kyushu University, Fukuoka, Japan.
His current research interests include basic researchon next-generation power semiconductor devices andrelated application technologies.
Dr. Saito was a recipient of the Conference Prize Paper Award in 2008
IEEE Power Electronics Specialists Conference. He is an Editor for IEEE
TRANSACTIONS ON ELECTRON DEVICES. He formerly served on the committee
member of Power Devices and ICs Committee in IEEE Electron Device Society
from 2015 to 2020. He is a member of the Technical Program Committee ofIEEE Electron Devices Technology and Manufacturing Conference. He formerly
served on the Technical Program Committees of IEEE International Electron
Devices Meeting from 2020 to 2021 and IEEE International Symposium on
Power Semiconductor Devices and ICs from 2016 to 2020.

Makoto Takamiya (Senior Member, IEEE) received
the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan,
in 1995, 1997, and 2000, respectively.
In 2000, he joined NEC Corporation, Japan, where
he was engaged in the circuit design of high-speed
digital LSIs. In 2005, he joined the University ofTokyo, Japan, where he is currently a Professor with
the Institute of Industrial Science. From 2013 to 2014,
he was a Visiting Scholar with the University ofCalifornia, Berkeley. His research interests include
the digital gate driver and sensor ICs for power electronics and the integrated
power management circuits for automotive and industrial applications.
Dr. Takamiya was a recipient of the 2009 and 2010 IEEE Paul RappaportAwards and the Best Paper Award in 2013 IEEE Wireless Power Transfer Conference. He is an elected member of Administrative Committee in IEEE Solid-State
Circuits Society from 2023 to 2025. He is a member of the Technical Program
Committee of IEEE Symposium on VLSI Technology and Circuits, IEEE Asian
Solid-State Circuits Conference, and IEEE International Symposium on Power
Semiconductor Devices and ICs. He formerly served on the Technical Program
Committees of IEEE International Solid-State Circuits Conference (ISSCC)
from 2015 to 2020 and IEEE Custom Integrated Circuits Conference from2006 to 2011. He was a Far East Regional Chair in ISSCC 2020. He was aDistinguished Lecturer of IEEE Solid-State Circuits Society from 2019 to 2020.

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