A 1-ps resolution on-chip sampling oscilloscope with 64:1 tunable sampling range
based on ramp waveform division scheme
Kenichi Inagaki, Danardono Dwi Antono, Makoto Takamiya*, Shigetaka Kumashiro**,and Takayasu Sakurai
University of Tokyo, Center for Collaborative Research, Tokyo, Japan*University of Tokyo, VLSI Design and Education Center, Tokyo, Japan**Semiconductor Technology Academic Research Center, Shin-Yokohama, Japan
Abstract
An on-chip sampling oscilloscope with 1ps timing
resolution is realized in 90nm CMOS process based on a
proposed ramp waveform division scheme for precise signal
integrity and power-line integrity measurement. The
resolution in time is variable from 1ps to 64ps in 64 steps. A
novel on-chip inductance measurement procedure is also
proposed.
Keywords: sampling oscilloscope, signal integrity
Introduction
Recently power and signal integrity issues such as IR drop,
di/dt noise, substrate noise, and crosstalk between
interconnects are getting severer and hinders high-speed
operation of VLSI’s. In order to maintain thesignal/power/substrateintegrity,
noise
waveformmeasurement is essential but measuring the waveform on thelower-level interconnects from the outside of the chip [1] isdifficult due to the higher-level metals that block the access to
the lower-level metals physically and electrically. Measuring
the interconnect voltage precisely from the back of thesubstrate is also impossible. Thus, an on-chip high-resolution
oscilloscope is required. The on-chip oscilloscope shouldhave a wide range of time resolution tenability, since thenoise on a chip contains multiple frequency components
caused by clocking, RLC resonance of interconnects, bonding
wires, package and circuit board effects.
The fastest on-chip sampling oscilloscope ever reportedachieved 100 GS/s based on a phase interpolator for thehigh-resolution sampling timing generation [2]. The phaseinterpolator circuit, however, fails to generate equally divided
timing signals between two delayed signals if the delay isgetting longer. Consequently, the tunable resolution range islimited to almost 2:1 and is not suitable for measuring various
noise components. In this paper, a ramp waveform division
scheme is proposed to achieve 1ps resolution while realizing
the tunable resolution range of 64:1.
Sampling oscilloscope circuits
Fig. 1 shows a block diagram of the proposed sampling
oscilloscope, which consists of one timing generator blockand multiple sampling heads. The sampling oscilloscope
block generates excitation timing, sampling enable timing(SE) and reference voltage (VREF), which are connected toeach sampling head. All timings are generated from a masterclock (CK). There is no clock jitter issue nor jitter
accumulation issue because all circuit operations are reset andrestarted with every master clock edge. A repetitive waveform(VDUT) is incident to the sampling comparator. VDUT is
compared with the VREF at SE edge. By scanning VREF and SE

1-4244-0006-6/06/$20.00 (c) 2006 IEEEand monitoring ‘1’ and ‘0’ of the CompOUT which is a digital
signal, VDUT can be reconstructed. As shown in Fig.2, random
noise, if there is any, can be reduced by averaging several
reconstructed waveforms.
Although DUT is driven by an excitation circuit in Fig.1,excitation circuit is eliminated if noise on a chip is to bemeasured. In that case, CK is generated from the main clockof the circuit block under test. 128 levels of VREF aregenerated by a resistor ladder to achieve 10mV voltage
resolution. The offset voltage of the sampling comparator canbe fully compensated by measuring a known DC voltage andobserving the difference between the known voltage and themeasured voltage. The rising edge rate of the VS&H anddynamic characteristics of MS&H determine the maximum
measurable frequency within 10% voltage error, which ismore than 20GHz estimated from the measured and simulated
waveforms by applying known sinusoidal wave from outside.
Fig.3 shows a sampling timing generator based on ramp
waveform division (RWD) scheme. A variable edge-rate ramp
waveform is generated by a ramp generator shown in theupper half of the figure, which is compared with the static
voltage, VSCAN, and generates Sampling Enable (SE) signal.
64 levels of voltages in the range of VSCAN,L to VSCAN,H aregenerated by a resistor ladder and digitally selected step bystep to generate VSCAN. By scanning VSCAN, the timing edge ofSE is varied step by step by the minimum resolution of 1ps.
The sampling time resolution can be easily varied bychanging the number of ISRC’s connected to VRAMP smoothly
up to 64ps (= 64 x 1ps). The timing resolution is measured byobserving a waveform of a reference ring oscillator whose
frequency is divided and monitored outside of the chip.
This oscilloscope is applied to extract inductance (L) andresistance (R) values of an on-chip line based on a novel
principle. A previous approach extracts only characteristic
impedance [3]. As shown in Fig.4, DUT is precharged firstand then excited by a short pulse of the duration about 50ps
(1). The negative voltage edge generated by the pulse travels
through the line and reflected at the far-end of DUT which isopen (2). The wave is reflected again at the near-end (3) andthe process repeats. The waveform at the near-end of the DUT
oscillates with a cycle time of 4 LC and an attenuation rate()of exp −2R C / L . It is to be noted that the total charge on
the DUT is decreased by the short pulse but remains
unchanged during the oscillation. Since the extraction
procedure employs only the cycle time and the voltage ratio
information, the results do not depend on the absolute voltage
value of the waveform. The measurement was carried out on a12µm-wide and 3.8mm-long Cu line representing a powerline. The extracted L and R are 0.74nH/mm and 8.0Ω/mm.

2006 Symposium on VLSI Circuits Digest of Technical Papers

Fig.5 shows measured and simulated waveforms of a linewith changing the location of a capacitor of 1.9pF
representing a decoupling capacitor at the far-end, center andnear-end. Good agreement is observed. The measurement iscarried out at 1ps resolution and the SPICE simulation wasconducted using L and R values extracted by using SPICElinkfield solver. A sequence of measurements for the same DUT is
conducted by changing the time resolution. The measured
waveforms are shown in Fig.6 to show wide tunable range ofsampling resolution.
Fig.7 shows a microphotograph of a test chip fabricated in
90nm CMOS technology with a typical voltage of 1V. The
test chip contains one sampling oscilloscope block and 36
DUT’s for characterizing on-chip interconnects and noise.
The oscilloscope uses several static analog voltages, whoselines are protected from noise sources by surrounding shieldlines. The area of the each sampling head is 64µm x 35µm,
while that of the sampling oscilloscope block is 0.14mm2.

VDD
VBIAS

2Ramp
generator

4ISRC

ISRCISRC8ISRC

16ISRCCont.
V RAMPCKCLOADCKLinearity error < 5%Cont.

1Ramp
generator

Delay
CK

Voltage [V]

Cont.

VRAMP
Comparator

VSCAN,H VSCAN,LSE
6bit DAC

VSCAN

Dimmed VRAMP
are to change
0.8 resolution.
SE1
SE2
0.6
VSCAN,H V RAMP
0.4 V
SCAN20.2 VSCAN1VSCAN,L00100 200 300 400 500
Time [ps]Fig.3 Ramp waveform division scheme
φPRECH

Level shifter

ExcitationtimingC exp − 2RL 

VDDEX

DUT
VDUT
φEXCITEVSSEX

Acknowledgement

T = 4 LC

Technical support and valuable discussions with STARC,
especially with S.Ohkawa, are deeply appreciated.
Fabrication support from VDEC, University of Tokyo andASPLA are acknowledged. This project is supported byNEDO technology development organization as part of theFocus 21 promotion exercise.

(1)

Near-end

Far-endV

φEXCITEonX
Far-endNear-end

Charge(2)
off(3)
toff

Fig.4 Measuring method of inductance and resistance

References
110.80.80.6

3.8mm

0.4
0.2

Timinggenerator
block

Cont.
CK0Device under test
(DUT)

VREF,H VREF,L Excitation

6 bit DAC

Voltage [V]

VDUT
CompOUTVRESCONT

Cont.

VREF

0.6

VREF

P-DIFF

Width= 12µm
100 200 300 400 500 600 700
Time [ps]Cross section

LINT = 0.74nH/mm
CINT = 0.21pF/mm
RINT = 8.0Ω/mm
1.9pF
CDECOUPLE=

Fig.5 Measured and simulated waveforms of power supply
line with varying decoupling capacitor location

VDUT

M S&H

DelaySE

30µm

100µm

CDECOUPLE
0GND
metal

12µm

3.8mm

0.4Measured
Simulated

VS&H

QOUT

100 200 300 400 500 600 700
Time [ps]M6

CompOUT

FOUT

03.5µm0-200 -100

Sampling
Enable(SE)Digital I/O

0-200 -100

0.83.8mm
CDECOUPLE

GND
metal

0.2

DUT SelectSampling
headResolution
measurementblock

100 200 300 400 500 600 700
Time [ps]1timingSampling
timinggenerator

01.9mm

0.40.2

CDECOUPLE-200 -100

0.6

Excitation
circuitDelay

Cont. VSCAN,H VSCAN,L

Voltage [V]Voltage [V][1] M. Nagata et al., IEEE JSSC, pp. 813-819, Apr. 2005.
[2] M. Takamiya et al., ISSCC, pp.182-183, Feb. 2002.
[3] B. Kleveland et al., IEEE JSSC, pp. 716-725, June 2002.

Sampling
comparator

Analog input

Fig.1 Overall block diagram of on-chip sampling oscilloscope
10.8
0.60.40.202σ = 27mV
n = 1280

2σ300
Number250
200
150
1003025

Standard error = σ / √nn = Number of sample

20Error < 10mV (@n=10)
Error < 1mV (@n=1000)

15

Voltage [V]350

Voltage error (mV)

400

Theoretical1050

501.01 1.03 1.05 1.07 1.09 1.11
Voltage (V)0010121010
Number of samples310

Measured voltage distribution of one
sampling point

Fig.2 Measured distribution fits well withnormal distribution

1-4244-0006-6/06/$20.00 (c) 2006 IEEE

10.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
01ps resolution
02040

2.5ps resolution
040

80

Device Under Test
(DUT’s)

60

120

160

Sampling heads

10ps resolution
0200

400

600

62ps resolusion
01000

2000
Time [ps]

3000

4000

Fig.6 Same waveform measured byvarious timing resolutions

Timinggenerator
block

Fig.7 Photomicrograph of test chip2006 Symposium on VLSI Circuits Digest of Technical Papers