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Design Method of Class-F Power Amplifier
With Output Power of 20 dBm and Efficient
Dual Supply Voltage Transmitter
Shunta Iguchi, Student Member, IEEE, Akira Saito, Kazunori Watanabe, Takayasu Sakurai, Fellow, IEEE, and
Makoto Takamiya, Senior Member, IEEE

Abstract—The efficiency of power amplifiers (PAs) with a small
for short-range wireless sensor networks is
output power
limited by the loss in matching networks. To achieve high efficiency,
a new design method which calculates the complicated design parameters in a class-F PA with a merged filter and matching networks is proposed. The design method provides a new quantitative
conclusion that reducing both the power supply voltage
and the impedance transformation ratio increases the efficiency of. Using this result, a dualscheme isa PA with a small
realized to increase the efficiency of a transmitter (TX). At aof 20 dBm, compared with the conventional singlescheme,
the drain efficiency (DE) of the PA and the global efficiency (GE) ofscheme are increased by factors of 2.1
the TX with the dualand 1.5, respectively. A PA fabricated by a 40 nm CMOS processof 17 dBm. The TX with the PA
achieved a DE of 42% at aof 20 dBm and theachieves the highest GE of 28% at a
@1Mbps with on-off keying)lowest energy of 36pJ/bit (among the published results for TXs.
Index Terms—Dual power supply voltage, high efficiency, lowpower, low voltage, matching networks, power amplifier.

W

I. INTRODUCTION

IRELESS sensor networks comprise a large number ofsmall sensor nodes distributed throughout the home, inbuildings, or in cities. The sensors continuously monitor andsense the activity of people, the temperature, and the humidity,
and the measured data are transmitted and received by eachsensor node via short-range wireless communication (e.g., 1–10m). In such a system, the sensor nodes have the potential to operate autonomously using energy harvested from the environment via solar cells or thermoelectric generators, because thecost of maintaining and supplying power to a huge number of
sensors is preventing the commercial realization of such systems. For autonomous operation, one of the challenges is theManuscript received December 14, 2013; revised March 28, 2014; accepted April 08, 2014. Date of publication June 09, 2014; date of current
version September 25, 2014. This work was carried out as part of the Extremely Low Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy and Industrial Technology
Development Organization (NEDO). This paper was recommended by Associate Editor S. Levantino.
S. Iguchi, T. Sakurai, and M. Takamiya are with the University ofTokyo, Tokyo 153-8505, Japan (e-mail: shiguchi@iis.u-tokyo.ac.jp;
tsakurai@iis.u-tokyo.ac.jp; mtaka@iis.u-tokyo.ac.jp).
A. Saito was with the Semiconductor Technology Academic Research Center,
Kanagawa 222-0033, Japan. He is now with Sharp Corp., Nara 632-8567, Japan(e-mail: saito.akira@sharp.co.jp).
K. Watanabe was with the Semiconductor Technology Academic ResearchCenter, Kanagawa 222-0033, Japan.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2014.2321202

severe constraint of the power consumption of the transmitter(TX). The huge power consumption of the power amplifier (PA)is one of the critical problems in TXs. Therefore, in this paper,
we report the development of an ultralow-power TX with aforhighly efficient PA having a small output power
short-range wireless communication.
In the target application, each node operates as a router andconfigures an ad hoc network with symmetrical communication.
The power consumptionof the TX and the receiver(RX) should be equalized in symmetrical communication. In
this study, the target communication distance is 1 m and thedata rate is 1 Mbps with modulation by on-off keying (OOK)
in the 314 MHz band of the ARIB STD-T93 radio communication standard of Japan. The pass loss is assumed to be 25 dB andthe typical TX/RX antenna loss is 5 dB in the 314 MHz band.
A loss of 35 dB and an RX sensitivity of 55 dBm [1] specifyof the TX as 20 dBm. In addition,
the target
for the TX should be less than 38[1] owing to the symmetrical communication. This means that the global efficiencyof the TX must be higher than 26%.
Fig. 1 shows the dependence of the drain efficiency (DE) on
for previously reported PAs [1]–[12]. In PAs [2]–[5] forconventional wireless communications (e.g., cell phones and
WLANs) where the communication distance is 100 m–1 km,
is 10 to 30 dBm and DE is higher than 40%. In contrast, in PAs [1], [6]–[8] for short-range wireless sensor netis
works where the communication distance is 1–10 m,
20 to 10 dBm and DE is less than 30%. This implies thatis quitethe design of a highly efficient PA with a smalldifficult. In [1], DE and GE are respectively 20% and 16% atof 20 dBm (with OOK modulation), which does nota. Therefore, the purpose
meet the design targetofof this study is to achieve a GE higher than 26% at a
20 dBm.
An outline of this paper is given as follows. In Section II, a deis shown withsign method for a class-F PA with a small
a new quantitative analysis of the loss in the matching networks
and the degradation of DE at a small. In
scheme [13]Section III, a dual power supply voltagethat reduces the power consumption of a TX is described. In
Section IV, the measured results for a TX with the dualscheme having aof 20 dBm are given. In Section V,
the conclusions are given.
II. DESIGN OF PA WITH SMALL
The DE of a PA with a small
must be maximized beaccounts for a large procause its power consumption
portion of that of a TX. However, there has been little research1549-8328 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

IGUCHI et al.: DESIGN METHOD OF CLASS-F POWER AMPLIFIER

Fig. 1. Dependence of drain efficiency on
and target of this work.

2979

for previously reported PAs
Fig. 3. Dependence of output power on
calculated using (3). The
impedance transformation ratio (n) is varied from 0.01 to 100.

achieved by inserting matching networks. The load impedance
viewed from a transistor has to satisfy(1)(2)

Fig. 2. Schematic of class-F PA. The up-conversion L-section, filter, andmatching networks are clearly distinguished.

on the development of PAs with aof 20 to 10 dBm,
has not been quanand the degradation of DE at a small
titatively discussed. In this section, the difference between PAs
is explained from the viewpoint ofwith a small and large
the impedance transformation. Then, a new design method for1) is presented.
a class-F PA with a small
andFinally, a quantitative discussion on reducing
is given.
increasing DE at a small
A. Difference Between PAs With Small and Large
Fig. 2 shows a schematic of a class-F PA. The up-conversion L-section, filter, and matching networks are clearly distinguished in this figure to clarify the importance of the impedance. These three sections are finallytransformation at a small
ismerged to reduce the circuit components and the loss.
is the power supply
the amplitude of the input (In) andis a choke inductor,
is an AC-couvoltage of the PA.
is a load resistance,andpling capacitor,
resonate at the fundamental frequency
, and
and
resonate at the third harmonic. These resonators provide
high impedance at the third harmonic of the fundamental frequency. The third-harmonic peaking with maximally flat waveforms [14] achieves the theoretically maximum DE of 88%. Because of their high efficiency, class-F PAs are used in many wireless applications.
In digital PAs (e.g., class D, E, F), the highest DE is obtained
where the power factor
at an appropriate load impedance. Generally, such load impedance isis 1
1When the averageof a TX is 20 dBm with OOK modulation, theof the PA is 17 dBm.
maximum

where n is the impedance transformation ratio andis the. When (1) and (2) are
fundamental angular frequency
satisfied, theof the class-F PA in Fig. 2 is theoreticallygiven by [15](3)is the ideal
without losses except for
where
the switching lossof 12%.
oncalculated
Fig. 3 shows the dependence ofusing (3) when n is varied from 0.01 to 100. DE reaches the
because the impedance transformation
maximum value at. A larger distance fromresults in a
is not required atand lower DE owing to the large impedancelargerof 10 totransformation. In the typical PA design with a
30 dBm, a higherdesign is effective for reducing n andwhile it may have the problem of breakdown in
the power transistor. On the other hand, the PA design with aof 17 dBm in this study is different from the typical. To reduce n at a small,aPA design with a large
design is preferable. The ideal
at alowerof 17 dBm is 0.04 V while conventional PAs with a small[1], [6]–[8] have been designed with aof 0.5–1.0
between the ideal value and that in
V. This difference in, thereby DE isthe conventional designs increases
reduced. To achieve a highly efficient design for a PA with a, in this section, the dependences ofsmall
and DE on n are quantitatively analyzed.
B. Design Method for Class-F PA With Small
PAs (class A, B, C, E, F) intrinsically have an up-converandas shown insion L-section topology comprising
Fig. 2. The up-conversion L-section topology transforms
to. Therefore, in conventional class-F PAs, a down-conversion impedance[16]–[18] with a large
must be transformed fromtransformation is required and2980

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 10, OCTOBER 2014

with a conduction angle of . In this design method, the complicated design parameters in a class-F PA with a merged filter
and matching networks are calculated using some approximations to reduce the complexity of the equations. Using this de,, andare determinedsign method, , , ,, BW, n, ,, ,,from the given parameters of, Q, and.
is given byFirst,(4)andshould provide
because the resonator consisting ofhigh impedance at the third harmonic. In this design method, thein the resonator consisting ofandis negloss
is negligibly small. The third harmonic
ligible becausethat corresponds to the voltage between the resonatorandis 9 times smaller than the fundamental
consisting ofof the drain voltage [14]. This verifies thatcomponent
is negligibly small compared with.
should be) bechosen to easily implement the other parameters (e.g.,does not affect DE.
cause
without
is written as
In Fig. 4(b),Fig. 4. Schematic of class-F PA with merged filter and matching networks.
(a) Block diagram. (b) Detailed schematic.

(5)
Then,
and
are calculated as follows by solving (5)for the conditions given by (1) and (2) using the approximation
:
of

(6)
(7)
is
By choosing appropriate values of these parameters,
and a third harmonic-peaking is obtained.
converted toare given byThen, , , andFig. 5. Proposed design method for class-F PA with small.

to a lower value (e.g., 10 ). In contrast, for PAs with a,should be transformed to a higher value (e.g.,
small250 ). This indicates that the appropriate impedance transformation can be provided by the intrinsic up-conversion L-section.
topology at a small
In this study, a class-F PA with merged filter and matching
networks is adopted to reduce the matching components and theloss. Figs. 4(a) and (b) respectively show a block diagram and a, in which
detailed schematic of a class-F PA with a small
the filter and matching networks are merged by using the inis the equivalenttrinsic up-conversion L-section topology.
,
is the equivalent parallel resistanceseries resistance of, Q is the quality factor of the inductors, andis theofparasitic capacitance of the drain of the transistor in Fig. 4(b).
Fig. 5 shows the proposed design method for a class-F PA, where BW is the bandwidth of the TX,
with a small
is the channel-length modulation coefficient of the power tranis the loss in the resonator consisting ofandsistor,, andis the average drain current of the power transistor

(8)
(9)
(10)
In the design of the PA with a small, BW can be
widened because the regulations for low-power radio communication (e.g., UWB and ARIB STD-T93) are not strict
compared with those for high-speed radio communication (e.g.,
WLANs and cellular networks). The BW in the design should.
be widened by a large , thereby achieving a small
Fig. 6(a) and (b) show respectively an equivalent circuit of theclass-F PA and another equivalent circuit including the outputof the power transistor, whereis the drain
resistancecurrent in the small-signal model. In this design method, thepower transistor is modeled as a current source in the saturation

IGUCHI et al.: DESIGN METHOD OF CLASS-F POWER AMPLIFIER

Fig. 6. Equivalent circuits of class-F PA in proposed design method. (a) Equiv. (b) Equivalent circuit inalent circuit using transformer model includingof power transistor.
cluding2981

Fig. 9. Simulated dependence of DE on n and dependence calculated usingof 20, CP of 1.5 pF, of 0.5, andof 19.5. Q is(19) withvaried from 7 to 21.

region.2
andapproximation of

in Fig. 6(b) are written as follows using the
:
(11)
(12)

in Fig. 6(b) is given by(13)
From (13),is given by
(14)

Then,

is given by(15)

Fig. 7. Simulated dependence of
of 20
and
using (17) withon n and dependence calculatedof 1.5 pF. Q is varied from 7 to 21.

In this design method, the dominant losses of,, and, and the loss ofin the power
are considered and estimated. These losses
transistor
given by (3). The modified
change the ideal equation foris given by
(16)
where
, and
and

is
upon taking,,
into consideration. In (16), the effects ofare included in .

C. Quantitative Analysis for Reducing
Increasing DE at smallandIn PAs with a small,
and the loss in the
power transistor
are the dominant losses. Therefore, theandquantitative estimation and analysis of
are required to design highly efficient PAs with a small.

Fig. 8. Simulated dependence ofon n and dependence calculated usingof 20,
of 1.5 pF, of 0.5, andof 19.5.Q(18) withis varied from 7 to 21.

2This assumption may include a small error because the power transistor operates in a large-signal mode; however, a rough estimation can be obtained fromthis assumption [19]. Therefore, the power transistor is modeled as a current
source to make the design method concise. The error resulting from this assumption is discussed in Section II-C.

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 10, OCTOBER 2014

Fig. 10. Schematic of TX with class-F PA.

In this section,,, and DE are quantitatively
estimated.
.
is modeled as the loss in
In Fig. 6(b),The impedance transformation is carried out using the intrinsic
and. Therefore,
up-conversion L-section topology ofthe value ofcorresponding to the impedance.
is the sum oftransformation is given by the loss in
and
.
and
in the power transistor
are calculated as follows using (14) with consideration of the:loss due to
(17)

(18)
on n
Fig. 7 shows the simulated dependence ofand the dependence calculated using (17). Q is varied from 7 to21, because Q for an on-chip inductor is less than 10 [19] and Q
for an off-chip inductor is less than 20 [20] in the 314 MHz band.
is mainly determined by n, while it is
From (17),. The dependence ofshown
independent of.
in Fig. 7 shows that a larger n results in a largerof 0.5 V
When n and Q are 9.7 and 14, respectively, at a
is 42
, which is 2.1 times[1], the calculated. Therefore, it is difficult to achieve a high DE
larger thanof 0.5 V. To reduce, a low
at a, a miniaturized process, and an inductor
with a high Q should be used.
on n andFig. 8 shows the simulated dependence ofthe dependence calculated using (18). The dependence ofshown in Fig. 8 shows that a larger n results in a larger
while the dependence is less than that of. The infor
is next discussed. At small values
consistency ofof n,is increased, and the power transistor operates in thelinear region. The modeling of the power transistor as a current source is not valid in this region, resulting in the inconsis. As shown in Fig. 8, upon reducing,ntency whenshould be reduced. This gives the same conclusion as that for, a design with a smaller n is preferable at a small.
From (10), (17), and (18), DE is given by(19)

Fig. 9 shows the simulated and calculated dependences of
DE on n. The agreement of the results obtained using (19)and by simulation verifies the consistency of the proposed
design method and the discussion. For the target GE of 26%,
DE should be higher than 26% because the driver power
is included in. For DEs of more than30, 35, and 40%, n should be smaller than 6.1, 4.5, and 2.9,
, a design withrespectively. To increase DE at a small
is essential. Hence, both n anda smaller nmust be reduced (andin thiswork) to smaller values than those in conventional designs(–1.0 V) [1], [6], [7], [9].
III. DESIGN OF LOW-POWER TRANSMITTER WITH
DUALSCHEME
In this section, a dualscheme [13] is realized to maxiof 20 dBm with OOK modumize GE for a TX with alation. In the previous section, the importance of a small n andfor the design of a highly efficient class-F PA was
a low
, the
explained. However, in the TX design with a small
is not negligible. In previous studies,
driver power
was 100
at aof 20–560[9], andwas 8.5at aof 8[1]. Thus,. Therefore, an optimization method foris comparable tominimizingby considering
is realized forthe class-F PA designed by the proposed design method. In the, corresponding to the
optimized design, the minimum
for every n.
maximum GE, is determined by calculating
Fig. 10 shows a schematic of the TX with the class-F PA.
The carrier frequency is 314 MHz for the ARIB STD-T93 radio
communication standard of Japan and the data rate is 1 Mbps
is thewith OOK modulation. As shown in Fig. 10,(the power of the mixer can be neglected) andsum of.
does not depend on
In an ideal class-F PA [14],must be changed
and n. However, in this optimization,is given bywith n. The reason for this is discussed below.
(15). Fig. 11 shows the simulated and calculated dependences ofdecreases as n increases.
ison n. As shown in Fig. 11,
determined by the drive capability of the power transistor in the
PA. To control the drive capability, the design can be optimized
scheme with variable W at fixed
by a conventional singleor a dualscheme with a variable
at a fixed W. In the previous section, it was verified that a smallern achieves a higher DE; therefore, a design with a smaller n isfundamentally required to maximize GE. However, the smaller, therebyis less than 0.5 V atn results in a lower

IGUCHI et al.: DESIGN METHOD OF CLASS-F POWER AMPLIFIER

2983

Fig. 11. Simulated dependence of ID on n and dependence calculated usingforis caused by modeling as the current(15). The inconsistency ofsource in the linear region.

. This implies that the singlescheme is not suitablefor design optimization at a smaller n because the transistors inowing to the huge
the driver do not operate atdelay in the sub-/near-threshold operation. On the other hand,scheme, the transistors can operate atin the dualbecause the smaller n results in a larger( 0.5 V). Fromis changed with n to control the drive
this discussion,
capability of the transistor to maximize GE.
Figs. 12(a), (b), and (c) show the simulated and calculatedof 20 dBm.
,
n dependences in a TX with a,, andare calculated by [21]

(20)
(21)
(22)
(23)
(24)
where
is
in the saturation region of the powerisin the linear region of the powertransistor,, is a fitting parameter used to detransistor,
is the threshold voltage
scribe the degradation of mobility,
is the equivalent capacitanceof the power transistor,
is the mobility of electrons, W is the width ofof the driver,the power transistor, and L is the length of the power transistor.
Equations (20) and (21) are selectively used depending on theoperation mode of the transistor.
Fig. 12(a) shows the simulated and calculated dependences of,, andon n, Fig. 12(b) shows the simuand
on n, andlated and calculated dependences ofFig. 12(c) shows the simulated and calculated dependences ofandon n. In Fig. 12(b), when n is reduced,
is inis increased because thecreased as shown in Fig. 11, then,requires a higher drive voltage
in the power
highertransistor. In a similar manner, as shown in Fig. 12(a),is increased when n is reduced because
is proportional.
to
As shown in Fig. 12(b), a conventional TX [1] with ais designed withandsingle-Fig. 12. SPICE-simulated and calculated impedance transformation ratio (n)of 20 dBm. (a) Power consumption vs. n.
dependences in TX at
andvs. n. (c)andvs. n.
(b). In contrast, as shown in Fig. 12(a),is min, thereby GE is maximized at.
imized atandare 0.56 V and
The corresponding values of
0.2 V, respectively, as shown in Fig. 12(b). Table I shows thedesign and theparameters in the conventional singledesign.
dualFig. 12 shows the good agreement between the results obtained by simulation and calculation. This shows the validity

2984IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 10, OCTOBER 2014

TABLE IPARAMETERS IN CONVENTIONAL SINGLEDUALDESIGN

Fig. 13. Die micrograph and layout of TX with dualby 40 nm CMOS process.

DESIGN AND

scheme fabricatedof the new design method for a class-F PA with merged filter
and matching networks, and that the quantitative analysis of theis consistent.
losses with a small
The difference between the optimization of DE and GE is
discussed. In the optimization of DE, when n is reduced fromis reduced [Fig. 12(b)] andis reduced
10 to 1,decreases in proportional to[Fig. 12(a)] because. Alternatively,n (Fig. 7); therefore, DE is maximized at
is increasedin the optimization of GE as n decreases,
is increased [Fig. 12(a)]. When n is
[Fig. 12(b)] andrapidly increases [Fig. 12(b)] because the tranreduced,
sistor operation changes from the saturation region to the linear
region, thereby the corresponding
rapidly increases
is minimized at[Fig. 12(a)]. Therefore,[Fig. 12(a)] and GE is maximized at. By consideringand, the optimum n can
this trade-off between
scheme.
be decided in the dualIV. MEASUREMENT RESULTS AND DISCUSSION
To demonstrate the advantageousness of the dualscheme [13], a test chip is fabricated by a 1.1 V, 40 nm CMOS
process. Fig. 13 shows a die micrograph and the layout. The
0.6 mm and the core area of the TX is
die size is 0.5 mm. The measured parameters of the conventional
scheme and the dualscheme are given insingleTable I, and the same two resonators with the following param,,, andeters are used:.
for the TX in
Fig. 14 shows the measured GE andthe dualscheme whenandare varied. Atof 20 dBm, the maximum GE is 28% at
the target
and, which corresponds to thesimulated results in Figs. 12(a) and (b). These results show that
scheme and the design optimization
the dualachieve the highest GE at aof 20 dBm.
Fig. 15 shows the measured output spectrum of the TX. The
314 MHz carrier is modulated with 1 Mbps OOK modulation.
of 20 dBm satisfies the ARIB STD-T93
The measured
radio communication standard of Japan. The spectrum mask iseven with the larger harsatisfied as a result of the low
monics owing to the operation of the power transistor in theFig. 14. Measured contours of GE and
when
and
are
varied. Gray levels represent the values of GE. The lines are the contours of. At the targetof 20 dBm, the maximum GE is 28% at
andFig. 15. Measured output spectrum of the TX. The 314 MHz carrier is modulated by 1 Mbps OOK.

linear region. In addition, the robustness against spectrum distortion can loosen the ripple requirement of DC-DC converters
in the dualmethod.
to generate
Figs. 16 and 17 show the measured dependences of DE, respectively. The conventional singleand GE on
scheme and the dualscheme are compared. In thescheme,is equal toandissinglescheme,andare variedvaried. In the dualandshown in Fig. 14.
according to the optimum
At the targetof 17 dBm for DE and 20 dBm for GE,
scheme are 2.1 andDE and GE for the TX with the dual1.5 times higher than those with the conventional singlescheme, respectively.
from
The power overhead required to generate
is next discussed. The design issue of the dualscheme
is that a DC-DC converter is required to generatefrom. DC-DC converters with an input voltage of 0.56 V,, and efficiency
output voltage of 0.2 V, output current of 50
of more than 66% are required in this study. Some low-voltage
and low-output-power DC-DC converters that have the potenscheme havetial to satisfy these requirements of the dual-

IGUCHI et al.: DESIGN METHOD OF CLASS-F POWER AMPLIFIER

2985

TABLE IICOMPARISON WITH RESULTS OF PREVIOUS STUDIES

Fig. 16. Measured dependence of DE on output power. The conventional
scheme and dualscheme are compared. Results of previous
singlestudies are also shown.

Fig. 17. Measured dependence of GE on output power. The conventional
scheme and dualscheme are compared. Results of previous
singlestudies are also shown.

been reported. A 0.45 V-input and 0.34 to 0.44 V-output buckwas usedconverter [22] with an output current of 0.67–410
in an on-chip gate boost technique to achieve an efficiency
of more than 90% at a low input voltage and a low output
current. A-low-output voltage (0.3–0.55 V) buck converter[23] with an input voltage of 0.6–1.1 V and a discontinuous
conduction mode (DCM) controller was reported to achieve
an efficiency of 90% at an output voltage of 0.35 V. Neither
DC-DC converter, however, satisfies all the requirement of thescheme. Therefore, the development of 0.2 V-output
dualDC-DC converters with an efficiency of more than 66% is a
future research challenge to achieve a higher GE using thescheme.
dualIn Figs. 16 and 17 and Table II, the results of this work [13]are compared with those of previously reported TXs with smallvalues of 20 to 10 dBm. [1], [6], [7], [9]. The previous
in Table II. The
results are shown in descending order of
TX with the dualscheme achieves the highest DE of 42%
and the highest GE of 28%, thereby achieving the lowest energy@1 Mbps) among the reported TXs.
of 36 pJ/bit (V. CONCLUSION
A low-power and highly efficient transmitter (TX) was
developed. To achieve a highly efficient power amplifier (PA)
, a new design method whichwith a small output power
calculates the complicated design parameters for a class-F PA
is proposed. The proposed design methodwith a small
provides a quantitative analysis of the low efficiency in aclass-F PA with a small, in particular, the dependences
and theof the loss in the matching networks
drain efficiency (DE) on the impedance transformation ratio
are discussed. On the basis of the quantitative analysis, weand a small
conclude that a low power supply voltage
impedance transformation ratio result in higher efficiency of. Using this result, a dualthe PA with a small
scheme is realized to increase the efficiency of a TX with a. At aof 20 dBm, compared
PA having a small
with the conventional singlescheme, DE and GE for thescheme are 2.1 and 1.5 times higher,
TX with the dualrespectively. Compared with previously reported TXs, the TX
scheme achieves the highest DE of 42%
with the dualof 20 dBm, thereby
and the highest GE of 28% at a
@1 Mbps)achieving the lowest energy of 36 pJ/bit (among the reported TXs.
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Shunta Iguchi (S’12) received the B.S. degree
in electronic engineering from the University ofElectro-Communications, Tokyo, Japan, in 2011
and the M.S. degree in electrical engineering andinformation systems from the University of Tokyoin 2013, where he is currently pursuing the Ph.D. degree. His research interests include the circuit designof the low-power RF transceiver circuits, the crystal
oscillators, and the wireless power transmission
circuits.
From August 2011 to September 2011, he worked
at Analog Devices, Tokyo, on voltage reference circuits. From August 2013
to September 2013, he worked in the wireless and analog division in Toshiba,
Kawasaki, Japan, designing low power wireless transceiver circuits. He isa recipient of the best paper award in 2013 IEEE Wireless Power Transfer
Conference.
Akira Saito received the B.S. degree in electronics
and communication from Waseda University, Tokyo,
Japan, in 1990, and received M.S. degree in electronic engineering and Ph.D. degrees in physics fromthe University of Tokyo in 1992 and 2000. He joined
the Sharp Corporation in 1996. He was a Visiting
Researcher at Extremely Low Power LSI Laboratory,
Institute of Industrial Science, University of Tokyo,
from 2009 to 2013. He has engaged in the researchesof the silicon and germanium nano-crystals, liquid
crystal display fabrication process, and the digital

and analog circuits designs for the digital communication and broadcasting
systems such as Bluetooth, 802.11, W-CDMA, and ISDB-T.
Kazunori Watanabe graduated from theTomakomai Technical College, Japan, in 1975.
In 1975, he joined Matsushita Communication
Industrial Co., Ltd. (presently Panasonic Mobile
Communications Co., Ltd.), Yokohama, Japan. He
was engaged in development of a digital system forpager. From 1997 through 2003, he has managed
development of the technology for cdmaOne cellular
phone. From 2003, he was engaged in system design
development of using high frequency semiconductor integrated circuit in Panasonic Corporation
Semiconductor Company, Kyoto, Japan. He has been a Visiting Researcher
at Extremely Low Power LSI Laboratory, Institute of Industrial Science,
University of Tokyo since 2009. He is interested in analog circuits, power
supply circuits, and wireless communication systems for extremely low power
LSI circuits and systems.

Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in EE from the Universityof Tokyo, Japan, in 1981. In 1981 he joined Toshiba
Corporation, where he designed CMOS DRAM,
SRAM, RISC processors, DSPs, and SoC Solutions.
He has worked extensively on interconnect delay
and capacitance modeling known as Sakurai modeland alpha power-law MOS model. From 1988
through 1990, he was a Visiting Researcher at the
University of California Berkeley, USA, where
he conducted research in the field of VLSI CAD.
Since 1996, he has been a professor at the University of Tokyo, working
on low-power high-speed VLSI, memory design, interconnects, ubiquitouselectronics, organic ICs, and large-area electronics. He has published morethan 600 technical publications including 100 invited presentations and several
books and filed more than 200 patents.
He is the executive committee chair for VLSI Symposia and a steering committee chair for the IEEE A-SSCC. He served as a conference chair for the
Symp. on VLSI Circuits, and ICICDT, a vice chair for ASPDAC, a TPC chairfor the A-SSCC, and VLSI symp., an executive committee member for ISLPEDand a program committee member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED, and other international conferences. He is a recipient of 2010 IEEE Donald O. Pederson Award in Solid-State Circuits, 2009
and 2010 IEEE Paul Rappaport award, 2010 IEICE Electronics Society award,
2009 IEICE achievement award, 2005 IEEE ICICDT award, 2004 IEEE Takuo
Sugano award and 2005 P&I patent of the year award and four product awards.
He delivered keynote speech at more than 50 conferences including ISSCC, ESSCIRC and ISLPED. He was an elected AdCom member for the IEEE SolidState Circuits Society and an IEEE CAS and SSCS distinguished lecturer. He
is an IEICE Fellow.

Makoto Takamiya (S’98–M’00–SM’14) received
the B.S., M.S., and Ph.D. degrees in electronicengineering from the University of Tokyo, Japan,
in 1995, 1997, and 2000, respectively. In 2000,
he joined NEC Corporation, Japan, where he wasengaged in the circuit design of high speed digital
LSI’s. In 2005, he joined the University of Tokyo,
where he is an Associate Professor of VLSI Design
and Education Center. From 2013 to 2014, he waswith the University of California, Berkeley, USA, asa Visiting Scholar. His research interests include thecircuit design of the low-power RF circuits, the ultra low-voltage logic circuits,
the low-voltage power management circuits, and the large area and flexible
electronics with organic transistors.
He is a member of the technical program committee of IEEE International
Solid-State Circuits Conference and IEEE Symposium on VLSI Circuits. He
received 2009 and 2010 IEEE Paul Rappaport Awards and the best paper award
in 2013 IEEE Wireless Power Transfer Conference.