Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme
to Achieve Leakage-FreeGiga-Scale Integration
T. Inukai', M. Takamiya', K.Nose', H. Kawaguchi', T. Hiramoto'72and T. Sakurai"3'Institute of Industrial Science, the University of Tokyo, Roppongi, Minato-ku, Tokyo 106-8558, Japan
Phone: +81-3-3402-623l(ex.2337), Fax: +81-3-54] 1-0695, E-mail: inukai0nano.iis.u-tokyo.ac.jp'VLSI Design and Education Center, the University of Tokyo, Hongo, Bunkyo-ku, Tokyo 106-8656, Japan
3Center for Collaborative Research, the University of Tokyo, Roppongi, Minato-ku, Tokyo 106-8558, Japan

Abstract
This paper proposes a new device and circuit scheme thatdrastically suppresses the stand-by leakage current for the
deep sub-0.1 pm era while maintaining the circuit speed.
Applying boosted gate voltage on the low leakage switcheswith higher V , and thicker To,, extremely low stand-by power
for battery type application is achieved, while degradation of
circuit performance and an increase of area overhead are
sufficiently suppressed. The combination with a negativegate voltage scheme and the application of the boosted
voltage scheme to SRAMs are also discussed.

Table 1 List of the device parameters for simulations[4].
Twh.Node 180nm 130nm l00nm
Lg(nm)

100

70

1.5

1.2
2
30

Tox (nm)

140
1.8
3.5

Xj (nm)50

335

Ndd (cm-')1x10I95x1Ol9Side Wall

100

70

Vdd(V)

70nm

S0nm

SO
0.9

35
0.6
I

1.5
20

1.5

1 ~ 1 0 2 ~1 ~ 1 0 2 1~ ~ 1 0 2 ~
30

10

7

Introduction
10%
The performance of VLSI chips will further increase by10.'
continuous device scaling. However, the present device
scaling method will certainly confront the practical limits
10"
caused by increased stand-by power. In the deep sub-0.1 pm
lo4
generation, the MOS device is no longer an ideal device andthe odoff ratio would be severely degraded. The off-current
1o-'O
0will consist of (i) subthreshold current due to very low
lo-"threshold voltage (V,) that is required by low supply voltage(Vdd), (ii) gate direct tunnel current due to very thin gate oxide(To,), and (iii) band-to-band tunnel leakage current due toheavily-doped halo. Therefore, stand-by current rapidly(180nm)(130nm)(100nm)(70nm)(50nm)
increases as the device is scaled. Fig. 1 shows the variation
Year (Technology Node)of leakage current with device scaling. The leakage current
will become far above the requirement for battery-operated Fig. 1 The trend of off-current of MOSFETs. Three types of off-current will
become problematic: (i) subthreshold leakage, (ii) gate tunneling leakage andchips.
(iii) junction leakage due to band-to-band tunneling with substrate bias.
Several proposals have been reported to suppress the Parameters assumed m listed in Table 1.
stand-by power, including VTCMOS [ I ] and MTCMOS [2].
In VTCMOS, however, gate tunnel current cannot be
VDD
suppressed and junction leakage becomes even worse by
substrate bias [3]. In MTCMOS, gate tunnel current andjunction current cannot be suppressed and area penalty
rapidly increases as the supply voltage is scaled. On theother hand, gate dielectrics with high k will suppress the gate
tunnel current, but the subthreshold and junction leakage can
not be reduced. The stand-by power problem will not be
Leak cut-off Switch (LS)solved by the conventional device and circuit scheme.
-high VthMoreover, no solutions have been proposed for stand-by
leakage of SRAMs.
In this paper, we propose a new devicelcircuit cooperation
scheme, the boosted gate MOS (BGMOS) scheme, thatdrastically suppresses the stand-by current while maintaining
circuit performance. The effectiveness of the BGMOS Fig. 2 A schematic of the proposed BGMOS scheme. Logic circuits consist
scheme is confmed by means of device simulation as well as of high performance MOSFETs with ultra-thin TOxand low V,. In stand-by
circuit simulation. This scheme can be applied to the whole mode, leak cut-off switches (Us), whose T,, is thick enough, Va is high, andoff-current is extremely low, suppress the stand-by current sufficiently. On
circuits in the chip including flip-flop, SRAMs, and YO circuits. theother hand, in active mode, LSs are driven by boosted gate voltage andThis scheme would be the only solution, ever reported, that the area penalty is well suppressed.
achieves high speed and low stand-by current at the same time.

-

5.
3
-

d[

19-2-10-7803-5809-O/00/$10.000 2000 IEEE

IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE

409

Boosted Gate MOS (BGMOS)

SPICE Simulation

In order to solve the stand-by power issue with maintaining
The effect of boosted gate and the area penalty of LS are
the circuit speed, two types of devices are necessary. One is discussed by SPICE simulation, where the SPICE parameters
an ultra-high speed, large leakage device with low V, and are derived from the results of device simulation. Fig. 4
thin To, that follows the roadmap [4] and is used for logic shows the dependence of active performance of 2-way NAND
circuits. The other is an extremely small stand-by current on the gate width of LS. When the gate is not boosted
device with high V, and thick To, that is used for the leak (conventional MTCMOS), the voltage drop across LS is large
cut-off switches (LSs), SRAh4 cells, and U 0 circuits. As the and logic performance is degraded, which means that the
supply voltage is reduced, however, the drive current of such conventional scheme needs extremely large area overhead.
low leakage switches is extremely low, which causes an Fig. 5 compares the area overheads. Using boosted gate,increase of area overhead if used for the LSs. Therefore, the area penalty is kept less than 10 % in each technology node,
improvement of the drive current of LSs is essential for the while the area penalty rapidly increases without boosted gate.
suppression of the area overhead. The proposed device On the other hand, Fig. 6 shows the trend of stand-by power
scheme makes it possible by applying higher gate voltage of a chip., The BGMOS scheme also drastically reduces thestand-by Curtent. This low stand-by current cannot be(Vhst)than v d d in the active mode.
Fig. 2 shows a schematic of the proposed BGMOS scheme. achieved by conventional CMOS without LS or conventional
Logic circuits consist of high-performance devices with MTCMO!?
ultra-thin To, and aggressively low V,. The supply voltage
2-NAND(F.O.3)
Tech. Node: Wnm
is reduced to suppress the ac power. On the other hand, LSs
Conventional(w/o LS)
consist of leakage-free devices with high V, and thick Tox.
LSs are inserted in series and the stand-by power iscompletely suppressed. The gate voltage of LS is boosted toreduce the area penalty.

Design of Leak Cut-off Switches
The optimal condition for LS, which acts as a leakage-freedevice, is discussed. With thick To,, the gate voltage can beboosted. However, LS with thicker To, cannot suppress
short channel effect sufficiently and needs longer Lg. To
take the short channel effects and other device issues into
consideration, two dimensional device simulation was
performed. Fig. 3 shows the drain conductance in the linear
region and required Lg for suppression of short channel effectin the 50nm technology node. The condition is constant V,
lowering by DIBL of 50mV. Boosted gate voltage is varied
proportional to To, , assuming constant gate electric field(SMV/cm). With boosted gate voltage, drain conductance of
LS is drastically improved without sacrificing gate oxide
reliability. The optimal To, and boosted-gate voltage arefound to be 4nm and 2V respectively.
1
h

F

I

"boost (")

2

3

'

;1200
J

Tech. Node: SOnm
Vth = 0.5V (const.)

1

Conv. MTCMOS

BGMOS

16

Conventional (w/o LS)
1

100

10

lo00

ws" I WgnMOS
Fig. 4 The active performance of proposed BGMOS compared withconventional MTCMOS. (a) effective supply voltage and (b) propagation
delay time. In conventional MTCMOS (without boosted gate), LS
conductance is too small and extraordinarily large gate,widthis required.

- 50:

2005(1m)

Fig. 3 Drain conductance of LS in the linear region. Boosted gate voltage is
proportional to oxide thickness (Tm) and gate length is derived from thecondition of constant short channel effect (DIBL).Drain conductance has its
maximum value when To, is about 4nm. Moreover, this optimal condition isapplicable to other technology nodes (not shown).

410

(bq*'

2008(7Gm)

2011(Sam)

node)
Fig. 5 The vend of area penalty due to the insertion of I
S for constant Atpd.
While the area penalty in conventional MTCMOS is rapidly increasing withtechnology node, the area penalty in the proposed BGMOS is increasingslightly.

19-2-2

Tach Nods. Wnm'"'&' ' 2 &~Km"'' 2 o b 5 ' '2&'
.20111Vam)(sorm)Conv.
MTCMOS("I)( 1 m )

Year (1NW
Fig. 6 The variation of stand-by power at constant area penalty. Stand-by
power will increase and become intolerable for battery type operation inconventional CMOS (without Is)and conventional MTCMOS. On the other
hand, proposed BGMOS can suppress tunneling leakage and subthresholdleakage, thus reducing the stand-by power efficiently.

BGMOS

SCCMOS:zzs

fig. 8 Comparison of area penalty for various circuits schemes. SCCMOS
scheme needs thicker To. for oxide reliability, which makes its area penalty alittle larger than BGMOS's. On the other hand, SCCMOS combined with
BGMOS scheme shows the smallest area penalty.

Application to SRAMs and F/F

Combination with Super Cut-off Scheme

For SRAM cells, leak cut-off switch scheme cannot be
Another solution to the degradation of circuit performance used because the stored data are lost in the stand-by mode.
and increase of area overhead might be super cut-off CMOS To reduce the stand-by power, leakage free devices with high
(SCCMOS) scheme [ 5 ] . In SCCMOS, LSs consist of low vdd and high V, (equal to V b S J should be used in SRAMs.
V, devices and the gate is negatively biased in stand-by mode On the other hand, the data in flip-flop (FE) circuits, which
in order to suppress stand-by subthreshold leakage as low as consist of high performance devices and connect with LS,
high V, devices. With low V,, LSs can get higher drive would be lost in stand-by mode. This problem can be solved
current in active mode and the degradation of circuit by the circuits that combine low v d d F E and high vdd SRAM,
performance is suppressed well.
However, applying as shown in Fig. 9, where stored data in F E are transferred tonegative bias in stand-by mode causes higher voltage across high Vdd SRAMs and stored temporally in stand-by mode [5].
gate oxide resulting in the reliability problem.
Moreover, this circuit scheme is applicable to U 0 circuits that
BGMOS can solve this problem. Using thicker To,for are conventionally consisted of devices with high Vdd for
LSs in SCCMOS, the oxide reliability is improved and compatibility with peripheral equipments. Fig. 10 shows aboosted gate voltage in active mode becomes possible. Fig. 7 schematic of the proposed circuit scheme.
shows the effect of this combined scheme and bias conditions
The device for the proposed SRAM cells can be common
in stand-by and active modes. Applying gate voltage to the to that for LS, except that high vdd is applied to drain inlimit determined from oxide reliability in both modes, the SRAM. Therefore, Lg of SRAM MOSFET cannot be so
drain conductance of LSs is maximized. While BGMOS much scaled as conventional devices because of large DIBL,
uses the maximized voltage only in active mode, SCCMOS as shown in Fig. 11. On the other hand, Fig. 12 shows theuses it only in stand-by mode. Therefore, the combined speed ( v d d / Zen) of the proposed SRAM MOSFET comparedscheme enables further suppression of area overhead, with the conventional SRAM MOSFET assuming constant V,
compared with BGMOS and SCCMOS, which is confirmed and constant Z,,respectively. While the proposed device is
by SPICE simulation as shown in Fig. 8.
much faster than the conventional device with constant V,, it
is slower than conventional device with constant Zen. This
Vboostdegradation of speed is due to longer Lgand higher vdd in the
4
1
2
3
proposed SRAM. Therefore, some measures should betaken to avoid the speed degradation of SRAM. Dividing
macrocells into small macros is one of the good examples.
The area penalty of the proposed SRAM cells increases withtechnology node as shown in Fig. 13. However, when we
take To,= 3 nm (hence vdd = 1.5 V), for both LSs and SRAMs,the total area penalty is suppressed. Although the area
penalty increases, this device and circuit scheme would be
one of the best solutions for the suppression of stand-by
power in SRAMs.
4
5 6
7
8
Tox (nm)Fig. 7 Drain conductance of LS in SCCMOS combined with BGMOS
scheme. Using SCCMOS scheme, drain conductance is drastically improved.
However voltage across gate oxide in stand-by mode is over Vu and oxide
reliability becomes an issue (grayed region). BGMOS scheme does not only
solve this problem but also enable further improvement of drain conductanceof Ls.

"

1

2

Conclusion

3

We have proposed a new device and circuit scheme for
sub-0.1pm generation to achieve extremely small stand-by
power without degrading circuit performance. This scheme
would be only solution ever reported to several problems,
which conventional schemes will face, that is, stand-by power,
speed degradation and area overhead.

19-2-3411

[21 S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, andJ. Yamada, "I-V power supply high-speed digital circuit technology
The authors thank T. Kuroda of Toshiba corp. for fruitfulwith multithreshold-volgate CMOS, IEEE Journal of Solid-Sfare
discussion. This work is partly supported by the JSPS
Circuits, vol. 30, pp. 847-854, 1995.
Research for the Future Program.
r31 A. Keshavarzi, S. Narendra, S . Borkar, C. Hawkins, K. Roy, and V. De,"Technology scaling behavior of optimum reverse body bias for standby
References
leakage power reduction in CMOS IC's", Proceedings ofInternational Symposium on Low Power Electronics and Design,[ I ] T. Kuroda, T. Fujita, S, Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki,
pp. 252-254, 1999.
F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu,
and T. Sakurai,"A 0.9V. 150-MHz. IO-mW, 4 mm', 2-D discrete cosine [41 Intemational Technology Roadmap for Semiconductors, 1998 update.
transform COR processor with variable threshold-voltage (VT) scheme", [51 H. Kawaguchi, K. Nose, and T. Sakurai, "A CMOS scheme for 0.5V
supply voltage with pico-ampere standby current", ISSCC Digest ofIEEE Journal of Solid-State Circuits, vol. 3 I , pp. 1770-1779, 1996.
Technical Papers, pp. 192-193, 1998.

Acknowledgment

CLK4
Q

Q

"G
I I<L S I

Fig. 11 The trend of gate length for conventional transistor and SRAM
transistor. SRAM transistor can not be so much scaled due to large DIBL. If
we take T, = 3nm ( V , = I SV), further scaling of Lg becomes possible.

CLK

Stand-by'5

Conventional SRAM

Fig. 9 A flip-flop (F/F) is an important element of logic circuits. If LS isThis work
inserted in series with the conventional F/F and the switch tums off, theconventional F F s lose stored information. A F/F proposed in this figure
consists of FIF with LS in series and an SRAM cell with the higher V , andV d . The information stored in the F/F is written to the SRAM by activating(const.)the WL when standby signal is asserted. In the wakeup process, theinformation in the SRAM is written back again to the F/F and thus theinformation is not lost. The delay overhead is 5%. since the speed isdetermined by the F/F with the BGMOS scheme. The area overhead is
about 30% in 201 1, since the SRAM area is 20% of the total FIF area when
the same transistors are used for both Fff and SRAM.
Fig. 12 The trend of device speed ( V , / I,,,). Although the speed ofproposed SRAM design is degraded compared with conventional transistor
whose on-current is kept constant, but this design can keep off-current
sufficiently low and keep its speed faster than conventional transistor withconstant off-current.
70

0Lowvoltage

I

Cell SireTor

4nm (V,= 2V)

Additional Area for Sense Amp.

1

Tox = 3nm (V,= 1S V )1

HihVoltage

Elg. 10 A schematic of the proposed circuit scheme. In addition to logic Fig. 13 The trend of area penalty for the proposed SRAM design. Area
circuits with LS, as shown in Fig. 2, this scheme is applicable to whole penalty has two origins: (i) an increase of cell area due to the increased Lg
circuits including F/F circuits, SRAM and VO circuits.
and (ii) an increase of additional area for sense amplifiers due to division ofmacro-cell into small macro in order to keep high speed.

412

19-2-4