ISSCC 2011 / SESSION 12 / DESIGN IN EMERGING TECHNOLOGIES / 12.1
12.1

A 95mV-Startup Step-Up Converter with VTH-TunedOscillator by Fixed-Charge Programming andCapacitor Pass-On Scheme

Po-Hung Chen1, Koichi Ishida1, Katsuyuki Ikeuchi1, Xin Zhang1,Kentaro Honda1, Yasuyuki Okuma2, Yoshikatsu Ryu2,Makoto Takamiya1, Takayasu Sakurai1
1

University of Tokyo, Tokyo, Japan,Semiconductor Technology Academic Research Center, Yokohama, Japan2

Harvesting energy from the environment by using a thermoelectric generator(TEG) or photovoltaic cells provides a solution for battery-free sensor networks
or electronic healthcare systems. In these systems, the harvested energy is supplied at a very low voltages, requiring a low-startup-voltage power circuit for
kick-start from low voltage. A previous sub-100mV-startup-voltage boost converter [1] was implemented by using a mechanically assisted step-up processthat needs vibration at startup and the application is rather limited. In this paper,
a 95mV startup voltage step-up converter without any mechanical stimulus
extends the applicability of energy harvesting. The circuit converts a 100mV
input to a 0.9V output with 72% conversion efficiency without any external
clocks or mechanical switches. A capacitor pass-on scheme eliminates an additional external output capacitor that functions only at the startup.
The minimum startup voltage of a step-up DC-DC converter in standard CMOS
technology is limited by the oscillator since a clock signal is required for acharge pump (CP). Practically, the minimum supply voltage of an oscillator(VDDMIN) is limited by PMOS-NMOS VTH unbalance caused by within-die and dieto-die VTH variations. The within-die VTH variation issue can be solved byincreasing the channel width and thus it is easily solved in this application. Theproblem is the die-to-die variation, which can usually be adjusted by controllingthe body bias of the MOSFET. In the startup circuit, however, the body-biasing
circuit is not functional since the body-biasing circuit needs another oscillator,
which does not function below VDDMIN. To solve this problem, post-fabrication
VTH programming is applied to the oscillator.
Figure 12.1.1 compares the conventional and our step-up converter architectures. In the conventional approach, two external capacitors are required. One(COUT1) is used in the charge-pumping startup circuit and the other (COUT2) is forthe boost converter. COUT1 is needed to separate the boost converter from the CPat the start-up. Otherwise the start-up CP needs to drive the boost converter
control circuit, which is seen as leakage current (ILeak) for the CP. In our scheme,
COUT1 is eliminated by using the output capacitor of the booster, COUT2, as thecharge buffer of the CP as shown in Fig. 12.1.1(b). Once the COUT is charged
without leakage, COUT is “passed on” with its charge inside to the boost converter. By doing so, the large external capacitor of COUT1 is eliminated.
The detailed block diagram of the proposed step-up converter and the timing
chart are shown in Fig. 12.1.2. The capacitor pass-on controller contains a CP
for PMOS super cut-off (PSC) and two voltage detectors D1 and D2. The CP for
PSC provides the overdrive voltage to the gate of PMOS switch and reduces theleakage current. At startup, COUT is charged by the CP and VSTART rises. When
VCP1 (=VSTART) is pumped to the preset trip voltage of D1, the node Y changes
from low to high to pass on the COUT to the boost converter and COUT becomes
the output capacitor of the boost converter. The charge stored in COUT activatesthe clock generator for the boost converter and start driving the boost converter. If the load is connected at the same time when the capacitor is passed on, thecharge stored in COUT drains out and boost converter fails to start up. To overcome this problem, a voltage detector D2 with 60mV higher trigger voltage comparing to D1 is added to delay the load connection timing a bit. This ensures theoutput switch M2 to turn on after the boost converter starts working and the output is boosted smoothly.

reduce the power consumption, the gate of MD3 is connected to its source andonly off-current flows. VDETECT changes sharply from low to high when drain current of MD1 and MD2 get larger than off-current of MD3 exponentially. The trigger
voltage can be written as (1) in Fig. 12.1.3, which can be tuned by designing thesize of MD2 and MD3. MD1 is applied to almost double the trigger voltage without
using unreasonable size ratio of MD2 and MD3.
To make sure the circuit functions even under the die-to-die process variation,
the VTH of transistors in the ring oscillator, which generates the CP clocks, aretrimmed by fixed-charge programming, as shown in Fig. 12.1.4. The upper partshows the detailed circuit schematic when post-fabrication VTH programming isin progress. Since the VTH of NMOS, VTN, was higher than that of PMOS, VTP, inthe measured chips, VTP is increased to reduce the VDDMIN of the oscillator here.
The VTP is programmed by applying the high reverse body bias to all PMOSFETs(VNWELL=8.5V, VPWELL=0) when the ring oscillator is oscillating under 1V power
supply. If VTN programming is required, the high reverse voltage to VPWELL and1V supply to VNWEL can be applied. In the PMOS programming, holes are injected into the gate oxide and the fixed charge changes VTP. To verify VDDMIN
improvement by this post-fabrication VTH-trimming, three test chips of 15-stage
ring oscillators are measured. Figures 12.1.4(b) and 12.1.4(c) show VDDMIN
change under stress and after stress. VDDMIN is improved (decreased) by 34%
compared with the initial value. In Fig. 12.1.4(c), the measured dependence of
VDDMIN after stress is shown. The change is as small as 1mV after 3 days ofstress and gets stable.
The step-up converter containing the startup circuit with VTH-trimmed oscillator
is realized in 65nm CMOS technology. The chip micrograph is shown in Fig.
12.1.7 with 0.17mm2 active area. Fig. 12.1.5(a) shows measured waveforms of
the step-up converter with the capacitor pass-on mechanism. The circuit ismeasured under 95mV input voltage without any external clocks or mechanicalswitches. The CP for startup pumps up the 10nF external capacitor COUT andpasses on the capacitor to the boost converter after 262ms. The power efficiency versus the current delivered to the load under 100mV input is shown in Fig.
12.1.5(b). It provides maximum efficiency of 72% at 1.5mA output current with
0.9V output voltage.
The performance comparison between our circuit and the state-of-the-art stepup converters applying startup mechanism is shown in Fig. 12.1.6. The proposed circuit achieves the lowest startup voltage except for reference [1]. which
requires mechanical vibration to assist the startup. The proposed circuit also
demonstrates the feasibility of countermeasures for the process variation thatlimits the minimum startup voltage of an on-chip ring oscillator.

Acknowledgement:This work was carried out as a part of the Extremely Low Power (ELP) project
supported by the Ministry of Economy, Trade and Industry (METI) and the New
Energy and Industrial Technology Development Organization (NEDO).
References:[1] Y. K. Ramadass and A. P. Chandrakasan, “A Batteryless Thermoelectric
Energy-Harvesting Interface Circuit with 35mV Startup Voltage,” IEEE ISSCC
Dig. Tech. Papers, pp. 486-487, Feb 2010.
[2] E. Carlson et al., “20mV input Boost Converter for Thermoelectric Energy
Harvesting,” IEEE J. Solid-State Circuits, vol. 45, pp. 741-750, Apr., 2010.
[3] P. Chen et al., “0.18-V Input Charge Pump with Forward Body Biasing inStartup Circuit using 65nm CMOS,” IEEE Custom Integrated Circuit Conference,
pp.239-242, Sep. 2010.
[4] S. Matsumoto et al., “A Novel Strategy of a Control IC for Boost Converterwith Ultra Low Voltage Input and Maximum Power Point Tracking for Single
Solar Cell Application,” International Sym. on Power Semiconductor Devices &ICs, pp. 180-183, June 2009.

Since the detector D1 has to be connected to COUT at startup, it acts as the loadof the CP. Thus the power consumption of the detectors should be minimized.
The circuit schematic of the voltage detector and its simulated waveforms areshown in Fig. 12.1.3. It consumes less than 1.6nW when VSENSE < VTrigger. To

216• 2011 IEEE International Solid-State Circuits Conference

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ISSCC 2011 / February 22, 2011 / 1:30 PM

Figure 12.1.1: The system architecture of (a) the conventional and (b) theproposed startup mechanism in step-up DC-DC converter.

Figure 12.1.2: (a) The detailed block diagram of the proposed step-up
converter. (b) Timing chart illustrating the circuit operation sequences.

12Figure 12.1.3: (a) Circuit schematic of 1.6-nW voltage detector (b) Simulated
waveforms of the proposed voltage detector.

Figure 12.1.4: (a) Circuit schematic of VTH-tuned oscillator. (b) Measured
VDDMIN change under stress. (c) Measured VDDMIN change after stress.

Figure 12.1.5: (a) Measured startup waveforms of the proposed step-up
converter. (b) Measured conversion efficiency versus output current.

Figure 12.1.6: Comparison of recently published step-up converter applying
startup mechanism.

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Figure 12.1.7: Chip micrograph of the proposed step-up converter.

• 2011 IEEE International Solid-State Circuits Conference

978-1-61284-302-5/11/$26.00 ©2011 IEEE