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Transactions Briefs
On-Chip Measurement System for Within-Die Delay
Variation of Individual Standard Cells in 65-nm CMOSXin Zhang, Koichi Ishida, Hiroshi Fuketa, Makoto Takamiya, andTakayasu Sakurai

Abstract—New measurement system for characterizing within-die delay
variations of individual standard cells is presented. The proposed measurement system are able to characterize rising and falling delay variations separately by directly measuring the input and output waveforms of individualgate using an on-chip sampling oscilloscope in 65 nm 1.2V CMOS process.
Seven types of standard cells are measured with 60 DUTs for each type.
Good correlations of within-die delay distributions between measured andMonte Carlo simulated results are observed. The measured results of risingand falling delay are of great use to the modeling of standard cell library of
deep-submicrometer process. By virtue of the proposed scheme, the relationship between the rising and falling delay variations and the active areaof the standard cells is experimentally shown for the first time.
Index Terms—Active area, delay variation, on-chip oscilloscope, standard cell, within-die delay.

I. INTRODUCTION
With the advancement in deep submicrometer CMOS technology beyond 65 nm, accurate characterization and measurement of delay variation of standard cells is becoming essential for design for manufacture, process optimization, and yield enhancement [1]–[5]. Meanwhile,
digital systems with increasing complexity and gigabytes per second
data rate today are also demanding a more accurate timing analysis.
Hence, there is a demand for a measurement technique which can perform delay characterization at individual gate level.
Measuring the waveform on the single gate level from the outsideof the chip is almost impossible. Using external probes is an intrusiveand complex way with limited accuracy, because large parasitic LC
of probes may affect the measured waveform drastically. On the other
hand, the transition time of on-chip signal reaches sub-10 ps order withthe latest LSIs, whose bandwidth is too high for off-chip measurement.
Thus, on-chip measurement techniques have been proposed by many
researchers in order to measure the on-chip delays.
Conventionally, delay variation is measured with ring oscillator orgate-chain [6]–[10] because it’s easily implemented on-chip and has ahigh sensitivity to process parameters. However, the period of ring oscillators and gate chain is determined by the sum of delays of all thestages, so measured  of delay is averaged to = n, where n is thenumber of total stages. Thus, it is impossible to measure single-gate
contributions. Even though the authors in [11] proposed a modifiedpManuscript received December 14, 2010; revised May 18, 2011; accepted
July 04, 2011. Date of publication August 30, 2011; date of current version
July 19, 2012. This work was supported in part by Semiconductor Technology
Academic Research Center (STARC). The VLSI chips were fabricated throughthe chip fabrication program of VLSI Design and Education Center (VDEC),
the University of Tokyo, with the collaboration by STARC.
The authors are with the Institute of Industrial Science, University of Tokyo,
Tokyo 153-8505, Japan (e-mail: zhangxin@iis.u-tokyo.ac.jp; ishida@iis.utokyo.ac.jp; mtaka@iis.u-tokyo.ac.jp; tsakurai@iis.u-tokyo.ac.jp).
Digital Object Identifier 10.1109/TVLSI.2011.2162257

Fig. 1. Block diagram of on-chip sampling oscilloscope.

ring oscillator to characterize individual gate delay, they fail to separate the rising and falling delays, so the delay and variation with risingand falling transition are still averaged. Therefore, exploring an on-chipmeasurement system [12] to characterize the rising and falling delays
separately is the focus of this paper. (In this paper, rising/falling delay
is also referred as tpLH =tpHL , which means the propagation delay witha low-to-high /high-to-low transition in the output.)
Our proposed method for measuring the delay variation of standard cells utilizes the directly measured waveform of individual gate
by using on-chip sampling oscilloscope [13], which is chosen becauseof its pico-second resolution and simple sampling head structure overprior art such as [14]. In this way, the input and output waveforms ofan individual gate are captured separately, therefore enables the characterization of rising and falling delays separately. Seven types of standard cells: INV 1, INV 2, INV 4, NAND2, NOR2, NAND3, and NOR3 aremeasured with 60 DUTs for each type. Good correlations of within-diedelay distributions between measured and Monte Carlo simulated results are observed. By virtue of proposed scheme, a relationship between the rising and falling delay variation and the active area is experimentally shown for the first time.
Experimental results of the test chip in 65-nm process successfully
demonstrate the feasibility of measuring rising and falling delay variations of individual standard cells.

2

2

2

II. MEASURING WAVEFORM WITH ON-CHIP OSCILLOSCOPE
In order to measure the input and output waveform of individual standard cells directly, the on-chip sampling oscilloscope is implemented
in 65 nm 1.2 V CMOS process. Fig. 1 shows the block diagram of the
on-chip sampling oscilloscope, which consists of a sampling timing
generator (STG), a reference voltage generator (a 7 bit DAC), and asampling head (SH). VDUT is connected to input or output of individual
standard cell, and is repetitively sampled by the sampling head at sampling enable (SE) edge and compared with VREF . By both scanning
VREF and the timing of SE, transient waveform of VDUT can be converted to digital data by a voltage comparator (comp_head). Furthermore, in this operation, any random noise introduced by the on-chipsampling oscilloscope can be reduced by averaging hundreds of reconstructed waveforms.
The reference voltage generator is implemented by resistor ladder togenerate 128 level of VREF . VSCAN L and VSCAN H are connected to1063-8210/$26.00 © 2011 IEEEIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 10, OCTOBER 2012

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Fig. 3. Top level block diagram of within-die delay variation measurement
using on-chip sampling oscilloscope.
Fig. 2. Circuit schematic of within-die delay variation measurement using
on-chip sampling oscilloscope.

00.2 and 1.4 V, respectively, for a voltage range of 00.2 to 1.4 V witha 12.5-mV voltage resolution. The STG consists of a delay unit, a ramp
generator, a 7 bit DAC and a voltage comparator (comp_timing). The
delay unit in STG is employed to enable adjustable observing window
for on-chip sampling oscilloscope. The 7 bit DAC is also implemented
by resistor ladder and is used to generate 128 level of VSCAN fromVREF L = 0.2 V to VREF H = 0.4 V. The ramp generator produces
a ramp waveform VRAMP , which is then compared with 128 level of
VSCAN by comp_timing to provide 128 SE’s with a pico-second step.
Then SE is connected to SH as a scanning timing signal for a picosecond resolution of on-chip sampling oscilloscope.

Fig. 4. Photo and layout of the test chip.

III. IMPLEMENTATION OF DELAY VARIATION MEASUREMENT
Based on the above on-chip sampling oscilloscope, a scheme to measure the input and output waveform of individual standard cells is presented in Fig. 2. For one type of standard cell (shown as a NAND2gate), 60 duplicates of DUTs and SHs are implemented to characterize
within-die delay variation. The number of DUTs and SHs is chosen
by a trade off of adequate number to show distribution, total available
layout area, and types of standard cells to be measured.
Same comparator (comp_head) is used for measuring both input andoutput waveform, thus the offset of measured input and output signal
brought by comparator can be cancelled out. Switch size of I/O select is carefully selected to minimize parasitic RC from DUT to comparator and the mismatch of the two channels. Inverters are employed
as input and output load to DUT, as a normal situation of “fan-out 4” in
a common digital system. A rise-fall controller is implemented to apply
rising or falling edge of excitation (EX) signal to the DUT. Buffers fromEX to DUT is sized bigger than normal, in order to introduce less variation on the buffer line, thus less disturbance on the variation of interest.
An oscilloscope controller is shared among all the 60 DUTs and SHs
in order to minimize the variation introduced by the controlling circuit.
The oscilloscope controller consists of a delay unit, a STG, and a reference voltage generator. The delay unit is controlled by a 6 bit digital
signal to enable the tunability of timing control for EX.
Fig. 3 shows the top level block diagram of the fabricated within-diedelay variation measurement circuit. Seven types of standard cells:
INV21, INV22, INV24 (named by increasing drivability), NAND2,
NOR2, NAND3, and NOR3 are implemented with 60 DUTs for each inorder to show the delay distributions. Great efforts have been madeto reduce unwanted noise and variation introduced by the sampling
oscilloscope control circuit, the power rail, and the signal buffers for
DUTs.

2

Fig. 5. (a) Measured DUT (INV 1) output waveform using the on-chip sampling oscilloscope. (b) Histogram of half V
timing of (a).

The oscilloscope controller is shared among all the 420 DUTs andSHs for the same reason mentioned above. “A resolution measurement
block [13] shown in Fig. 3 is implemented to measure the timing resolution of the on-chip sampling oscilloscope. A reference ring oscillator
is employed and its frequency can be measured by using frequency
divider. The timing resolution (step of SE’s) is measured by using calibration technique and measured result shows that the test chip achieves
a minimum time resolution of 1 ps.”
The test chip is designed and fabricated in 65 nm bulk CMOS
process. Fig. 4 shows the chip microphotograph and the layout. The
total 420 DUT’s and 420 sampling heads consumes an area of 1200
m 2 1500 m, and the oscilloscope controller occupies 280 m 2
780 m.
IV. MEASUREMENT RESULTS AND ANALYSIS
Rising and falling delays of 7 types, 420 DUTs are measured with
1.2 V VDD . Measurement is at first carried out to evaluating the timing
error introduced by the on-chip sampling oscilloscope. The noise due

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Fig. 7. Histogram of measured and simulated delay among 60 DUTs of 7 typesand (b) t.
of standard cells: (a) t

Fig. 6. Measured waveforms of an inverter with (a) rising output transition and(b) falling output transition.

to on-chip sampling oscilloscope can be reduced by averaging several reconstructed waveforms. In this study, each waveform is sampled
190 times and averaged to suppress random noise introduced by the
sampling oscilloscope. Time interleave between each measurement is
500 ns. In order to evaluate the timing error, one DUT output (INV21) ismeasured 190 times, and the time when the measured waveform crosses
0.6 V (half VDD ) is extracted in Fig. 5(a). Histogram of the measured
half VDD timing is shown in Fig. 5(b). It is observed that by measuring
the same waveform for 190 times, the proposed scheme has a  errorof 0.82 ps, which is quite small compared with the delay of DUTs, thus
ensure the measurement accuracy of on-chip transition signal. It is also
smaller than the accuracy of 1 ps reported in [11], which is a ring oscillator-based design.
Fig. 6 shows the measured input and output waveforms of an INV22
gate with rising output transition and falling output transition. 1.2 V
VDD is applied in the measurement. In this way, the rising and fallingdelays of each DUT are measured for the within-die delay variation.
The histogram of within-die delay variations of 7 standard cells withrising output transition and falling output transition is shown in Fig. 7.
The distribution is observed to be close to normal. The measured results are in accordance with well-known knowledge that the tpd from
INV21, INV22 to INV24 are decreasing because of the increasing gatearea. Also, as expected, in the rising/falling transition, NOR3/NAND3 isobserved to be the slowest, because there are three pMOSs/nMOSs inseries from output to power/ground.
Fig. 8 shows the within-die delay distribution map with rising andfalling output transition, respectively. The positions of totally 420
DUTs are corresponding to the actual test chip shown in Fig. 4. As
shown in Fig. 8, the within-die delay variation is random and nosystematic component due to IR-drop on power lines is observed,
because ultra wide metals and multiple pads are used for power supply

Fig. 8. Within-die delay distribution of (a) tof DUT’s corresponding to (a) and (b).

, (b) t, and (c) actual layout

and ground, moreover, power supply and ground are connected to each
DUT through crossed metal layers.
Monte Carlo simulation has been carried out for the 7 types of standard cells with 60 samples each, with rising and falling output, respectively. Simulation is carried out by SPICE with after LPE netlist, andvery close results are observed in Fig. 7 for simulated and measured result. Because the variations of gate length and oxide thickness and othereffects that are not able to be included in the Monte Carlo simulation,
parameters like AVT , 1VT , and gamma are modified in the simulation. Fig. 9 shows the comparison of measured and simulated average
delay with rising output transition and falling output transition. Great
correlation for all types of standard cells can be observed.
As well acknowledged, for rising and falling output, the transition isa result of conduction through the devices in the path from output to thepower or ground rail. Therefore, for a rising/falling output, the active
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Fig. 10. Active transistors in DUTs with (a) rising output transition, and(b) falling output transition.

Fig. 9. Comparison of measured and simulated average delay. (a) t
(b) t
.

.

the delay variation, as depicted in Fig. 10. In this way, we can calculate the active area of each type of DUT by summing the gate area ofactive transistors, with both rising output transition and falling output
transition.
Fig. 11 shows the measured sigma tp =average tp (tp =tp ), thex-axis is chosen to be 1= Active area(m2 ), where active area iscalculated by the total gate area of active transistors at rising and fallingtransition.
Variation of threshold voltage (VT ) is known to be proportional to
1= W L [15]. As shown in Fig. 11, tp =tp has strong correlation with 1= Active area(m2 ), which is similar to the relationshipbetween VT and 1= W L. Moreover, the gradient of Fig. 11(b)is bigger than Fig. 11(a), which reveals a simple concept that nMOSs
have bigger variation than pMOSs, because the gate area of nMOSs are
smaller than that of pMOSs and AVT of nMOSs is larger than that ofpMOSs.
In the conventional methods, because tpLH and tpHL are mixed together, the dependency of tp =tp on active area shown in Fig. 11 is
impossible to be measured. By measuring tpLH and tpHL separately,such dependency is shown for the first time.

p 2

p 2

Fig. 11. Measured sigma t =average t (t =t ) with (a) rising output transition, and (b) falling output transition.

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V. CONCLUSION
The proposed measurement system is able to characterize rising andfalling delay variations separately by directly measuring the input andoutput waveforms of individual gate. 7 types of standard cells: INV21,
INV22, INV24, NAND2, NOR2, NAND3, and NOR3 in 65-nm process aremeasured with 60 DUT’s for each type. Good correlations of within-diedelay distributions between measured results and Monte Carlo simulated results are observed. The measured results of rising and fallingdelay are of great use to the modeling of standard cell library of deepsubmicrometer process. By virtue of the proposed method, the relationship between the rising and falling delay variations and the active area
is experimentally shown for the first time.
ACKNOWLEDGMENT
The authors would like to thank M. Murakata, K. Inagaki, and
Y. Nakamura for the useful discussions.

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[2] A. Hamoui and N. Rumin, “An analytical model for current, delay
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[3] S. Nassif, “Delay variability: Sources, impacts and trends,” in IEEE
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[5] S. Mukhopadhyay, K. Kim, K. A. Jenkins, C. T. Chuang, and K. Roy,
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Solid-State Circuits, vol. 43, no. 9, pp. 1951–1963, Sep. 2008.
[7] J. Panganiban, “A ring oscillator based variation test chip,” M.Eng.
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[8] H. Masuda, S. I. Ohkawa, A. Kurokawa, and M. Aoki, “Challenge:
Variability characterization and modeling for 65- to 90-nm processes,”in Proc. IEEE Custom Integr. Circuits Conf, 2005, pp. 593–599.
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[11] B. P. Das, B. Amrutur, H. S. Jamadagni, N. V. Arvind, and V.
Visvanathan, “Within-die gate delay variability measurement using
re-configurable ring oscillator,” in Proc. IEEE Custom Integr. Circuits
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[12] X. Zhang, K. Ishida, M. Takamiya, and T. Sakurai, “An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS,” in Proc. Asia South Pacific Design Autom. Conf. (ASP-DAC), 2011, pp. 109–110.
[13] K. Inagaki, D. D. Antono, M. Takamiya, S. Kumashiro, and T. Sakurai,“A 1-ps resolution on-chip sampling oscilloscope with 64:1 tunablesampling range based on ramp waveform division scheme,” in Proc.
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[14] M. Takamiya, M. Mizuno, and K. Nakamura, “An on-chip 100 GHzsampling rate 8-channel sampling oscilloscope with embedded sampling clock generator,” in IEEE ISSCC Dig. Tech. Papers, 2002, pp.
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[15] M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matchingproperties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24,
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A High Performance Switched Capacitor-Based
DC-DC Buck Converter Suitable for Embedded
Power Management Applications
Biswajit Maity and Pradip Mandal

Abstract—Here, we propose high performance buck converter architecture suitable for embedded applications. The proposed converter has highpower efficiency, high power density, good driving capability, low output
ripple, and good line and load regulation. The step down converter is constructed using a simple building block called cross coupled converter. As
this block use low swing internal signals to control half of its switches,
the required switching loss decreases and these internal control signals enable us to use thin oxide transistor for making switch smaller and reducing
power further. In addition, converter uses all the good features of non-overlapping rotational interleaving switching scheme. Switching frequency ofthe converter is dynamically adjusted based on load current to maintainhigh power efficiency. Good transient performance is achieved by using
dynamic leaker circuit with a marginal increase of static current. The converter is designed in 0.18- m CMOS process to get regulated 1.3–1.6 V
output from 3.3 V input supply while output ripple is below 42 mV andprovides 86% peak power. For 75% power efficiency, power density of theconverter is 0.43 W/mm using total 490 pF capacitor.
Index Terms—Controlled cross-coupled, frequency control (FC), nonoverlapping rotational time interleaving (NRTI) switching scheme, shootthrough (ST) current, switched-capacitor (SC).

I. INTRODUCTION
Since long back switched-capacitors (SCs) are used for DC-DC converters [1], [2]. But there is a recent trend to use these SC based DC-DC
converter for embedded power management applications in order toachieve high power efficiency and power density. SC converter of [3]has high power efficiency but, it uses off-chip capacitor to keep output
ripple at acceptable level. On the other hand, for high dropout applications, SC converter and linear regulator are combined to develop a
hybrid converter [4]. Converter has 200 mV ripple with 200 pF load
capacitor to get 1.05 regulated outputs. Such high ripple at the output is
not suitable for embedded applications. In [5] the on-chip output capacitor is implemented but the power efficiency remains low and the output
ripple is high due to unavailability of large flying capacitor and load capacitor for such embedded applications. The output ripple is reducedwith less output capacitor in [6]–[8] by increasing effective switchingfrequency using interleaving switching schemes. Though shoot through(ST) current reduction technique is discussed in [7], but in [9] total ST
current is eliminated by using non-overlapping rotational time interleaving (NRTI) switching scheme and power efficiency is improved. In
addition, output ripple is also reduced in the converter. One drawbackof NRTI, however, is power overhead due its control signal generationand control signal swing. In SC boost converter [10], [11], cross-coupled techniques are used to make use of internal node voltages as control signal. This helps to improve power efficiency by reducing dynamic
Manuscript received May 21, 2010; revised November 18, 2010, February 12,2011, and May 14, 2011; accepted July 19, 2011. Date of publication August22, 2011; date of current version July 19, 2012. This work was supported by the
National Semiconductor Corporation.
The authors are with the Department of Electronics and Electrical Communications, Indian Institute of Technology, Kharagpur, West Bengal 721032, India(e-mail: biswajitmaity.iitkgp@gmail.com; pradip@ece.iitkgp.ernet.in).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2011.2163206

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