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PAPER

Special Section on Analog Circuits and Related SoC Integration Technologies

A 315 MHz Power-Gated Ultra Low Power Transceiver in 40 nm
CMOS for Wireless Sensor Network
Lechang LIU†∗a) , Nonmember, Takayasu SAKURAI† , Fellow, and Makoto TAKAMIYA† , Member

SUMMARY
A 315 MHz power-gated ultra low power transceiver for
wireless sensor network is developed in 40 nm CMOS. The developed
transceiver features an injection-locked frequency multiplier for carrier
generation and a power-gated low noise amplifier with current second-reusetechnique for receiver front-end. The injection-locked frequency multiplier implements frequency multiplication by edge-combining and thereby
achieves 11 μW power consumption at 315 MHz. The proposed low noise
amplifier achieves the lowest power consumption of 8.4 μW with 7.9 dB
noise figure and 20.5 dB gain in state-of-the-art designs.
key words: injection lock, power gating, low noise amplifier, ultra low
power

1.

Fig. 1 Proposed injection-locked OOK transmitter and power-gatedreceiver for wireless sensor network.

Introduction

An ad hoc wireless sensor network refers to a group of
spatially distributed sensors, or nodes, linked by a wirelessmedium to report on the physical world. To protect safety
and security, promote healthcare and welfare, and provide
entertainment and convenience, 1000–10,000 sensor nodes
are distributed around the user’s environment. These sensor nodes are usually powered either by batteries or throughenergy harvesting and thus each of the nodes should be implemented at a minimal power level.
Figure 1 shows the block diagram of the proposed lowpower transceiver for wireless sensor network [1]. To reduce
the power consumption, carrier frequency should be as low
as possible. Due to the well-known fundamental limits ofantenna miniaturization, 315 MHz is chosen for this workand a commercial ϕ12 × 86 mm antenna is assumed in thiswork. The transceiver employs on-oﬀ keying (OOK) modulation. Typically in a transmitter, a carrier wave is generated
by a phase-locked loop which usually consists of a phasefrequency detector, a charge pump, a loop filter, a voltagecontrolled oscillator and a frequency divider and therefore
consumes a lot of power. To reduce the power consumption, this work employs injection-locked frequency multiplier for carrier generation. As shown in Fig. 1, on the transmitter side, the 39.375 MHz reference frequency is multiplied to 315 MHz by injection locking and then the generated 315 MHz carrier is modulated by input data and amplified by power amplifier for transmission. On the receiver
Manuscript received October 17, 2011.
Manuscript revised January 26, 2012.
†
The authors are with The University of Tokyo, Tokyo, 1538505 Japan.
∗
Presently, with the Dept. of Electronics and Electrical Engineering, Keio University.
a) E-mail: lcliu@kuroda.elec.keio.ac.jp
DOI: 10.1587/transele.E95.C.1035

side, the received signal is first amplified by the front-end
power-gated low noise amplifier (LNA) where the power
gating signal φPG comes from oﬀchip and then the envelopeof the signal is detected by the envelope detector. This envelope detection based architecture can eliminate the need fora local oscillator in the receiver and therefore most of thepower in the receiver is consumed the front-end low noise
amplifier. In this work a power-gated LNA with current
second-reuse technique is proposed to minimize the power
consumption.
This paper is organized as follows. Section 2 describes
the power-gated LNA with current second-reuse technique.
Section 3 explains the proposed 315 MHz injection-locked
frequency multiplier. Experimental results are presented in
Sect. 4 and Sect. 5 concludes the paper.
2.

Current Second-Reused Amplifier with Power Gating

2.1 Current Second-Reuse Technique
To achieve low noise figure and 50-Ω input match, a large
current is required at the first stage of the front-end amplifier. Current reuse technique can halve the current by stacking NMOS and PMOS transistors as amplifying devices [2].
On the left of Fig. 2(a) a NMOS with aspect ratio Wn /L anddrain current I is split to two NMOS with aspect ratio Wn /2Land drain current I/2. Thus, the transconductance of thecompound device with Wn /2L is the same as the transconductance of the device with Wn /L. On the right of Fig. 2(a),one of the Wn /2L NMOS is substituted by a PMOS withdrain current I/2. By sizing the aspect ratio of the PMOS,
its transconductance can be the same as NMOS with Wn /2L
and thereby the total voltage gain of the current-reused amplifier with drain current I/2 can be the same as a single

c 2012 The Institute of Electronics, Information and Communication Engineers
Copyright IEICE TRANS. ELECTRON., VOL.E95–C, NO.6 JUNE 2012

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Fig. 3 (a) Conventional power-gated amplifier [4]. (b) Receiverc 2011 IEEE)
front-end with proposed power-gated LNA. (Fig. 2 Shunt-shunt feedback amplifier. (a) Conventional current reused[2]. (b) Proposed current second-reused. (c) Simulated noise figure and S
parameter of the proposed current second-reused amplifier.

respectively. Compared with the conventional current-reusetechnique, for the same voltage gain the DC current is decreased by 1.5 times and thus the performance deterioration
due to process variation is also increased by 1.5 times dueto the stacked topology.
2.2 Power Gating Technique

NMOS amplifier with drain current I.
As shown in Fig. 2(b), the drain current can be further reduced to 1/3 by overlapping the NMOS and PMOS
pairs. The outputs of the two overlapped MOS pairs can besummed at the second stage. Shunt-shunt feedback can not
only prevent amplitude distortion and self-bias at the firststage but also eliminate the bias voltage generator for thesecond stage. The width of the overlapped transistors in thefirst stage is half of the top and the bottom transistors so the
DC voltages at the overlapped points are VDD /3 and 2VDD /3
respectively which can be used as voltage bias for the second stage.
Without narrowband matching network, the proposed
topology can be directly used as wideband amplifier [3].
Figure 2(c) shows the simulated noise figure and Sparameters with 50 Ω input and output impedance of the
proposed current second-reused amplifier. The simulated
power gain, IIP3 and noise figure are 19 dB, −10 dBm and12 dB from 200 MHz to 960 MHz while in [3] the power
gain, IIP3 and noise figure are 13 dB, −10 dBm and 3.6 dB

Power gating is an eﬀective low-power design techniquewhich originally stems from logic circuits where a circuit
block is cut oﬀ from voltage supply when the block is notswitching. In [4] power gating is introduced to the designof front-end LNA for pulse receiver. As shown in Fig. 3(a),to keep the additional DC bias point when the amplifier iscut oﬀ, a replica of the amplifier, called bias keeper is used.
Power consumption of the amplifier is reduced by power
gating but the bias keeper is not power-gated and thus thepower consumption of the receiver is dominated by the bias
keeper.
This bias keeper can be eliminated by two φ̄PG controlled capacitors in Fig. 3(b). During start-up, the voltageof the two capacitors is charged to VDD /3 and 2 VDD /3 respectively. When the amplifier is cut oﬀ, DC bias voltage isheld on the capacitors dynamically. The capacitance for DC
voltage holding is 750 fF. The resistors for feedback are implemented by CMOS transmission gates operating in deep
triode-region. The proposed LNA achieves low power con-

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Fig. 4c 2011 IEEE)
Proposed fast-settling OOK transmitter. (sumption at the cost of doubled impedance matching networks due to the stacked NMOS and PMOS pairs. As shownin Fig. 4, this technique can also be applied to the mixer
design to enable fast modulation and thus high energy efficiency.
3.

Injection-Locked Frequency MultiplierFig. 5 Conventional Injection-locked frequency multiplier. (a) LC
oscillator based [5]–[7]. (b) Ring oscillator based [8], [9].

3.1 Conventional Injection-Locked Frequency MultiplierPrinciple of conventional injection-locked frequency multiplier based on LC oscillator is shown in Fig. 5(a) [5]–[7].
The frequency multiplier consists of an LC tank and a current source clocked at the reference frequency, which injects
the LC tank with a stream of current pulses. Assuming thatthe free running frequency of the oscillator is very close to
the Nth harmonic of the reference, the oscillator will lockto that harmonic such that its average frequency becomes
N times the reference frequency. These characteristics are
similar to the action of an integer-N phase-locked loop frequency synthesizer. However, since no phase detector, loop
filter, and frequency divider are required in this system, inprinciple, an injection-locked frequency multiplier provides
a very simple and low power means of achieving frequency
multiplication.
Ring oscillator based injection locked frequency multiplier is shown in Fig. 5(b) where an NMOS modulator isinserted between two output nodes of three inverters [8], [9].
When the NMOS turns on, the output nodes in the ring oscillator are connected through the NMOS so the gain of thethird inverter decreases and the output amplitude is modulated. As a result, the output waveform is distorted and the
spurious tones become large, and thus the locking range isreduced. To reduce waveform distortion and spurious tones,
the injected pulse width should be as narrow as possible.

achieve injection-locking. For the LC oscillator based frequency multiplier, locking has been traditionally achieved
by first tuning the LC resonant frequency of the oscillator
with a varactor such that its value is suﬃciently close to thedesired harmonic as determined with the aid of a frequency
detector [5]–[7]. Without oﬀ-line tuning Vtune , the locking
range of an 8 × 315 MHz frequency multiplier designed inthis way is less than 1 MHz.
The second issue is that the oscillator operates at themultiplied frequency so the power consumption is increasedby the same multiplication factor.
To address these issues, an edge-combing based
injection-locked frequency multiplier is proposed inFig. 6(a). In the proposed frequency multiplier, the 315 MHz
output frequency is achieved by combining the 16-phaseedges of the eight delay cells. Figure 6(b) shows the timing diagram. Each of the delay cells [10], [11] operates at
39.375 MHz and thus the power is reduced to 1/8 of conventional way without the consideration of the power consumption of the edge combiner. Since the delay-cell frequency is
the same as reference frequency, wide locking range can beachieved by full-period forced oscillation instead of narrowpulse injection-locked oscillation.

3.2 Proposed Injection-Locked Frequency Multiplier

The proposed transmitter with injection-locked frequency
multiplier and power-gated receiver front-end without inductors were designed and fabricated in 40 nm CMOS process. Chip micrographs and layouts of LNA and frequency
multiplier are shown in Fig. 7. By disabling the on-chip capacitors of the LNA, the same chip is used as the mixer for

In practice, there are several challenges in building the frequency multiplier shown in Fig. 5. The first issue is thatthe free running frequency of the oscillator must be very
close to the desired harmonic of the reference in order to4.

Measurement Results

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Fig. 8Fig. 6 Proposed injection-locked frequency multiplier. (a) Circuit
c 2011 IEEE)
schematic. (b) Timing diagram. (Fig. 7 Chip micrographs and layouts. (a) LNA. (b) Frequency multiplier.
c 2011 IEEE)(measurement. To measure the performance of the transmitter, an evaluation printed circuit board (PCB) is prepared.
The chip is bonded to the PCB by bonding-wire machine
and the oﬀ-chip inductor for impedance matching is weldedto the board. The waveforms of the LNA are measured
by Agilent DSO91304A infiniium high performance oscilloscope and the noise figure is measured by Agilent ESA
series spectrum analyzer.
Figure 8 shows the measured LNA noise figure andc 2011 IEEE)
Measured LNA noise figure and gain. (gain. At the target frequency 315 MHz, the noise figure andgain are 7.9 dB and 20.5 dB respectively. Power gating ratio of Fig. 8 is 100% because it takes more than one second for Agilent ESA series spectrum analyzer to calculate
the noise figure for each frequency point. To measure thenoise figure for 3.12% power gating ratio, the response timeof the measurement equipment should be less than 31.2 ns.
The measured LNA waveforms for data “0” and data “1” areshown in Fig. 9(a) and Fig. 9(b) respectively. φPG is power
gating control signal and VRX is the LNA output. From themeasured waveforms for data “0”, it can be seen that thesettling time of power gating is 9.7 ns which is determinedby the time constant of the power-gating node. The time
constant is the product of the input capacitance of the second stage and the output resistance of the first stage. This
short settling time enables fast power gating in receiver andfast modulation in transmitter. As shown in Fig. 9(b), thedata rate is 1 Mb/s and the power-gating duty is 3.12% so
the pulse width is only 31.2 ns. The measured transmitter
waveforms are shown in Fig. 10. DATA is the modulation
input and VT X is the mixer output.
The measured LNA power dependency on duty isshown in Fig. 11. Power consumption is reduced linearlywith the power-gating duty and thereby achieves 8.4 μW at
3.12% duty. The minimum detectable power for the oscilloscope is 5 μW.
The frequency multiplier waveforms and spectrum areshown in Fig. 12(a) and Fig. 12(b) respectively. The reference frequency is 39.375 MHz and output frequency is
315 MHz. The measured power consumption at 0.6 V
are 11 μW. The measured locking range of the proposed
full-period injection-locked frequency multiplier is 5 MHz
which is limited by the phase asymmetry due to the singlephase injection. Compared with the conventional pulse injection locked frequency multiplier, the locking range is increased by five times.
Table 1 shows the transmitter performance summaryand comparisons with state-of-the-art ultra low power transmitter for wireless sensor network. In this work, the supply
voltage for the mixer is 1.2 V while the supply voltage forLIU et al.: A 315 MHz POWER-GATED ULTRA LOW POWER TRANSCEIVER IN 40 NM CMOS FOR WIRELESS SENSOR NETWORK

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Fig. 10c 2011 IEEE)
Measured transmitter waveforms. (cFig. 11 Measured LNA power dependency on power-gating duty. (2011 IEEE)

Table 1

Transmitter performance summary and comparisons.

Fig. 9 Measured LNA waveforms. (a) Data “0”. (b) 31.2 ns Data “1”.
(c) 250 ns Data “1”.

the injection-locked carrier generator is 0.6 V. Compared toconventional work with 1.8 V supply voltage, the carrier frequency is reduced to 34.4% but power consumption of thecarrier generator and the mixer are reduced to 1.38% and12.8% respectively. The settling time is reduced to 3.59%.
The LNA performance summary and comparisons withstate-of-the-art design is shown in Table 2. Without power
gating, power consumption of the LNA with the proposedcurrent second-reuse technique is 598 μw. With power gating, power consumption of the LNA can be reduced withpower gating duty and thereby achieves the lowest power

consumption of 8.4 μW with 7.9 dB noise figure and 20.5 dB
gain.
5.

Conclusions

This paper presents a 315 MHz injection-locked OOK transmitter and a power-gated receiver front-end for wirelessad hoc network in 40 nm CMOS. To address the issuesof power consumption and locking range in the conventional injection-locked frequency multiplier, the proposedfrequency multiplier achieves frequency multiplication byedge-combining. It can reduce power consumption toIEICE TRANS. ELECTRON., VOL.E95–C, NO.6 JUNE 2012

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Fig. 12 Measurement results for frequency multiplier. (a) Waveforms.
c 2011 IEEE)(b) Spectrum. (Table 2

LNA performance summary and comparison.

11 μW at 315 MHz and increase the locking range by fivetimes. The proposed power-gated LNA with the current
second-reuse technique achieves the lowest power consumption of 8.4 μW with 7.9 dB noise figure and 20.5 dB
gain.
Acknowledgments
This work was carried out as a part of the Extremely Low
Power (ELP) project supported by the Ministry of Economy,
Trade and Industry (METI) and the New Energy and Industrial Technology Development Organization (NEDO).
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Lechang Liu
received the Ph.D. degree inelectronic engineering from Shanghai Jiao Tong
University in 2006. From 2007 to 2009, he held
a postdoctoral research position in VLSI Design
and Education Center at University of Tokyo,
Japan. From 2010 to 2011, he was a research associate with the Institute of Industrial Science atUniversity of Tokyo. Since 2011, he has been a
research assistant professor with Department ofElectronics and Electrical Engineering at Keio
University, Japan. His current research interests
include CMOS RF/mixed-signal IC design and analog signal processing
for wireless communications.

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Takayasu Sakurai
received the Ph.D. degree in EE from the University of Tokyo in 1981.
In 1981 he joined Toshiba Corporation, where
he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has
worked extensively on interconnect delay andcapacitance modeling known as Sakurai modeland alpha power-law MOS model. From 1988
through 1990, he was a visiting researcher at
the University of California Berkeley, where heconducted research in the field of VLSI CAD.
From 1996, he has been a professor at the University of Tokyo, working
on low-power high-speed VLSI, memory design, interconnects, ubiquitous electronics, organic IC’s and large-area electronics. He has publishedmore than 400 technical publications including 100 invited presentations
and several books and filed more than 200 patents. He served as a conference chair for the Symp. on VLSI Circuits, and ICICDT, a vice chair
for ASPDAC, a TPC chair for the first A-SSCC, and VLSI symp. and a
program committee member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC,
ICCAD, ISLPED, and other international conferences. He will be an executive committee chair for VLSI Symposia and a steering committee chair
for A-SSCC from 2010. He is a recepient of 2010 IEEE Donald O. Pederson Award in Solid-State Circuits, 2009 achievement award of IEICE,
2005 IEEE ICICDT award, 2004 IEEE Takuo Sugano award and 2005 P&I
patent of the year award and four product awards. He gave keynote speech
at more than 50 conferences including ISSCC, ESSCIRC and ISLPED. He
was an elected AdCom member for the IEEE Solid-State Circuits Society
and an IEEE CAS and SSCS distinguished lecturer. He is a STARC Fellow
and IEEE Fellow.

Makoto Takamiya
received the B.S., M.S.,
and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Japan, in 1995,
1997, and 2000, respectively. In 2000, he joined
NEC Corporation, Japan, where he was engaged
in the circuit design of high speed digital LSIs.
In 2005, he joined University of Tokyo, Japan,
where he is an associate professor of VLSI Design and Education Center. His research interests include the circuit design of the low-power
RF circuits, the ultra low-voltage logic circuits,
the low-voltage DC-DC converters, and the large area electronics with organic transistors. He is a member of the technical program committee forIEEE Symposium on VLSI Circuits. He received 2009 and 2010 IEEE Paul
Rappaport Awards.