Buck Converter with Higher Than 87% Efficiency over
500nA to 20mA Load Current Range for IoT Sensor Nodes
by Clocked Hysteresis Control
Chung-Shiang Wu, Makoto Takamiya and Takayasu Sakurai
The University of Tokyo, Tokyo, Japan
Email: cswu@iis.u-tokyo.ac.jp
Abstract—This paper presents a buck converter that achieves
an almost flat conversion efficiency higher than 87% over theload current ranging from 500nA to 20mA. A leakage-based
oscillator and a newly proposed double-half frequency control
algorithm are introduced to provide a clock signal that triggers ahysteresis control, which is called Clocked Hysteresis Control(CHC). By removing continuously-on comparators in theconventional hysteresis control, the buck converter improves theconversion efficiency under light load current conditions while
maintaining a fast transient response. The conversion efficiencyof 87.7% at 1mA and 90.4% at 1µA are achieved. Comparedwith state-of-the-art buck converter, the efficiency at 1µA is
improved 12% to 34%.

I.

INTRODUCTION

The growing development of Internet-of-Things (IoTs)
pushes the increasing of wireless sensor nodes. Rather thanmobile applications, the IoT sensor nodes may stay in a sleep
mode for most of the time and quickly wakes up to work only
in a short time. Several wireless communication specifications
such as Bluetooth low energy (BLE) [1] have been proposed tosupport these applications. The sleep current indicated in BLE
is about 1µA. However, for a wireless sensor node transmitting
data in every 60 seconds, the sleep mode consumes much moreenergy than the active mode. Therefore, the conversion
efficiency of a buck converter in a sleep mode becomesincreasingly important to extend the battery lifetime.
The conversion efficiency of the previously announced
buck converters, such as TPS62736 provided by Texas
Instrument [2], drops steeply when the load current, ILOAD, isless than 10µA. A tri-mode buck converter using PWM, PFM,
and asynchronous mode proposed by [3] improves theconversion efficiency in the light current load condition, but it
is still relatively low compared with the efficiency in the active
mode. A buck converter with the conversion efficiency of 87%
has been achieved at 1µA in [4], but it cannot supply mA rangeof the load current. Moreover, in order to realize a quick modechange including a wake-up, the hysteresis control is preferred.
Nevertheless, the static current of continuously-on comparator
strongly degrades conversion efficiency especially with a low
load current. Even though [5] which is based on hysteresis
control claims that the quiescent current is only 110nA, but it
still limits the conversion efficiency to be 78% when ILOAD is
1µA.
In this paper, a clocked hysteresis control scheme is
proposed for a buck converter which inherits the quick
response of a hysteresis control while removing the power

978-1-5090-5191-5/17/$31.00@2017 IEEE

consumed by continuously-on comparators. By replacing thecontinuously-on comparators in the conventional hysteresis
control by clocked comparators, the buck converter consumes
no static current in comparators. A leakage-based oscillator anda double-half control algorithm have also been proposed to
track the appropriate system frequency. The target input
voltage is 2.4V to 3.3V for high-reliability battery-poweredsystem, and the output voltage is 1.5 to 1.6V for BLE. To
indicate the advantage of removing continuously-on
comparators, Fig. 1 shows the simulated controller power
consumption distribution of the conventional hysteresis control.
In order to clarify the power issue in the conventional
hysteresis control, a simulation is carried out assuming ILOAD is
1µA, the hysteresis window is 20mV with VIN being 3V, VOUT
being 1.6V, and the bias current of the comparator being 1µA.
The simulation result shows that 66% power consumption is
occupied by the comparator, and the conversion efficiency is
only 32%.
This paper is organized as follows: the system architecture
is introduced in Section II. The double-half frequency control
algorithm and the schematic of leakage-based oscillator arepresented in Section III. Section IV shows the experimental
results and the comparison with other buck converters. A
conclusion is presented in Section V.

Fig. 1. Simulated power distribution of conventional hysteresis control
employing continuously-on comparator.

II.

SYSTEM ARCHITECTURE

The system block diagram and the control signal timing of
the proposed buck converter are shown in Fig. 2 (a) and (b),respectively. There are 3 comparators, X1, X2, and X3. X1 andX2 are employed to stabilize VOUT within the hysteresis

window forming by VMIN and VMAX. X3 is designed for zerocurrent detection (ZCD) to prevent inverse inductor current.
X1 is a latch-type comparator used to replace the continuously
on comparator in the conventional hysteresis control. It
consumes no static current and consumes power only at theclock edge. The clock signal VOSC of X1 is provided by theleakage-based oscillator, and the frequency fOSC is controlled
by the output signal, VGP. fOSC becomes double or half oncethe control signal bus CTRL_bit changes. On the other hand,
X2 and X3 should operate fast to reduce the output voltage
ripple and to prevent the reverse current. An analog
comparator topology is chosen. These two comparators,
however, are only turned on during designated time interval,
as shown in Fig. 2(b), that is, these two comparators are also
clocked and do not consume DC power. X2 is only enabled
when PMOS power transistor MP is turned on, and it is turned
off when the inductor current reaches zero. On the other hand,
X3 is only enabled when NMOS power transistor MN is turned
on, and turned off once it outputs a “1” signal. Thus, it ispossible to remove normally-on DC current of comparators in
the proposed clocked hysteresis control scheme. Moreover, thepower consumption of the proposed system can be scaled with
fOSC, which is proportional to load current conditions.
Therefore, the converter can achieve an almost-flat conversion
efficiency over the wide load current range. An FPGA isemployed to realize a sequencer which realizes the proposed
double-half frequency control algorithm in the current
implementation. The FPGA provides the CTRL_bit control
signals outside according to VOSC and VGP, and adjusts thesystem frequency fOSC. Only registers and look-up table (LUT)
logic in the FPGA are used [6]. The number of gates used is
700 gates, which is estimated to consume 300pW in thetechnology used in the implementation for ILOAD equal 500nA
and VIN equal to 3V. Consequently, the power consumption
for the control logic itself is negligibly small. The algorithm of
the double-half control will be described in the next section.

(b)
Fig. 2. (a) System block diagram of the proposed buck converter with leakage
based oscillator and double-half frequency control algorithm. (b) Timing ofrelative control signals in the buck converter.

Fig. 3. Flowchart of the proposed double-half frequency control algorithm.

III.

(a)

DOUBLE-HALF FREQUENCY CONTROL IMPLEMENATION

The flowchart of the proposed double-half frequency
control algorithm is shown in Fig. 3. The algorithm starts when
VOUT becomes lower than VMIN. Once it starts, it will wait foranother 1 clock cycle to monitor whether VOUT is still lower
than VMIN or not. If VOUT is still lower than VMIN, meaning thecomparator clock frequency is too slow. The control signal
CTRL_bit will increase fOSC to 2 fOSC, and the sequencer logic
restarts the above-mentioned process. On the other hand, if thenext cycle VOUT is higher than VMIN, the sequencer will wait foranother 1 cycle to judge that fOSC should be double or half. This
process operates continuously until an appropriate fOSC is foundthat can make the buck converter operate stably. Some may
argue that a buck converter with a hysteresis control in general
may have an issue that the switching frequency is not fixed andthat the harmonics of the switching frequency may interferewith the RF circuits on a chip. This situation can be eliminatedby the proposed ‘clocked’ hysteresis control scheme by using

an external system clock as a base clock for the double-halfcontrol instead of the internal leakage-based oscillator output
only in the active mode, although this function is not
implemented in the current design.
Fig. 4 illustrates the schematic of the leakage-based
oscillator. The oscillator should provide the double-halffrequency controllability, and consume low power toprevent the conversion efficiency from degrading.
Transistor leakage current is designed to bias the current
source to achieve low current consumption and low
frequency (~Hz) for µ-A ILOAD. 8 NMOS transistors areconnected in series to make diode-connected NMOS
current mirror, it reduces the total number of NMOS
transistors, which is dependent on the current mirror ratio.
Moreover, the control bits are separated to control NMOS
current mirror ratio and number of charging/discharging
capacitors. The multiplier ratio of MSB NMOS transistor
can be reduced to 2048. Low VDD,OSC is applied to achieve
low power consumption. To fully turn on switches SP and
SN to charge and discharge the capacitor, additionalbootstrap circuit is also designed to boost VOSC when outputof the Schmitt trigger is switching.

15Hz. The power consumption is less than 1% when ILOAD is
500nA. As is discussed in Section II, the power consumptionof the sequencer is negligible.
The measured dependences of the conversion efficiency on
the load current are shown in Fig. 8. By removing
continuously-on comparators and applying the leakage-based
oscillator with the double-half frequency control algorithm,
the converter can achieve the almost-flat conversion efficiency
and 90.4% when ILOAD is 1µA. The conversion efficiency ishigher than 87% all over the range from 500nA to 20mA. The
performance comparison with state-of-the-art buck converter
for BLE is shown in Table I.

Fig. 5. Chip microphotograph.

Fig. 4. Circuit schematic of the leakage-based oscillator.

IV.

EXPERIMENTAL RESULTS

The proposed buck converter with leakage-based oscillator
is implemented in 0.18-µm standard CMOS technology. I/Otransistors are used to implement circuits that should endure
VIN as high as 3.3V. The chip micrograph is shown in Fig. 5.
The total chip size is 2.7mm2 and the active area including thebuck converter, leakage-based oscillator, and voltage level
shifter is 0.71mm2. The off-chip inductor and output capacitor
are 4.7µH and 1µF, respectively. The hysteresis window, i.e.
the voltage difference between VMAX and VMIN, is set to 20mV.
The measured output waveforms under different load current
condition are shown in Fig. 6(a) and (b). In Fig. 6(a), the 100µA load current is applied, and VIN is 3V. The frequency of
VOSC is 3.57KHz. The maximum output voltage ripple is lessthan 100mV, which is about 6% of output voltage. The
transient response is measured with a system signal that resets
fOSC to the highest value before the load current changes. From
Fig .6(c), it can be said that no large voltage drop is observed.
Fig. 7 illustrates the oscillating frequency and the power
consumption of the proposed oscillator when VDD,OSC is 0.6V.
3 chips were measured, and the proposed leakage-based
oscillator consumes only 3.5nW while the frequency is about

(a)

(b)

(c)
Fig. 6. Measured waveforms of VOUT, VOSC, and comparator X1 output VGP. (a)VIN = 3 V, VOUT = 1.58 V, and ILOAD = 100 µA. (b) VIN = 3 V, VOUT = 1.58 V,
and ILOAD = 2 mA. (c) Output transient response when ILOAD changes from 1 µA
to 10mA.

V.

Fig. 7. Measured oscillating frequency and power consumption of the leakage
based oscillator.

CONCLUSION

A buck converter with a leakage-based oscillator and the
double-half frequency control algorithm is developed toremove the static current in the comparators employed in theconventional hysteresis buck converter. The proposed approach
improves the conversion efficiency when ILOAD is lower than
1µ A and achieves an almost-flat efficiency of higher than 87%
over the range from 500nA to 20mA load current by a uniform
control and circuit scheme. In addition, the buck converter
maintains a fast transient response of the conventional
hysteresis control, making it suitable for IoT sensor nodeapplications.
Table 1. Summary of performance comparison

Fig. 8. Measured conversion efficiency of the proposed buck converter and thecomparison with state-of-the-art.

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