IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE 2013

Minimizing Energy of Integer Unit by Higher Voltage
Flip-Flop: V DDmin -Aware Dual Supply Voltage Technique

Abstract— To achieve the most energy-efficient operation, thisbrief presents a circuit design technique for separating thepower supply voltage (V DD ) of flip-flops (FFs) from that of
combinational circuits, called the higher voltage FF (HVFF).
Although V DD scaling can reduce the energy, the minimum
operating voltage (V DDmin) of FFs prevents the operation at the
optimum supply voltage that minimizes the energy, because theV DDmin of FFs is higher than the optimum supply voltage. In
HVFF, the V DD of combinational logic gates is reduced below theV DDmin of FFs while keeping the V DD of FFs at their V DDmin.
This makes it possible to minimize the energy without powerand delay penalties at the nominal supply voltage (1.2 V) as wellas without FF topological difications. A 16-bit integer unit with
HVFF is fabricated in a 65-nm CMOS process, and measurement
results show that HVFF reduces the minimum energy by 13%
compared with the conventional operation, which is 1/10 times
smaller than the energy at the nominal supply voltage.

Measured
65nm CMOS
Flip-flop

300

VDDmin (mV)

Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya,
Masahiro Nomura, Hirofumi Shinohara, and Takayasu Sakurai

400

200

NAND
100

NOR
0

1

10

100

1k

10k

Number of gatesFig. 1. Measured VDDmin s of two-input NAND, NOR, and FF chains as afunction of number of gates in a 65-nm CMOS process [10].
Contention occurs at wired-OR point.
Leakage current
Drive current

Index Terms— Minimum operating voltage, subthresholdcircuits, variations.

I. I NTRODUCTION

1175

Master

CK2

Slave

D

With the growing markets of mobile devices,energy-efficient LSIs are strongly required. Since reducing
the supply voltage (VDD ) is one of the most effective methods
for improving the energy efficiency of logic circuits, many
research studies on sub- or near-threshold logic circuits
have been reported [1]–[6]. VDD scaling, however, degrades
throughput. Therefore, ultradynamic voltage scaling [7],which uses a nominal supply voltage when high performanceis required and reduces VDD when low performance isallowed, is a promising approach to the optimization of theenergies of applications with various workloads.
As VDD is reduced, the dynamic energy decreases
quadratically with VDD , while the leakage energy, which is a
product of the leakage power and delay, dramatically increases
in the subthreshold region owing to the increase in delay.
Therefore, the total energy has its minimum value, and VDD
at which the energy is minimized is typically around 0.3 V ina logic circuit [1]. Thus, this voltage is the target for energyefficient LSIs.
VDD scaling is, however, obstructed by the minimum
operating voltage (VDDmin), which is the minimum power
Manuscript received December 15, 2011; revised April 6, 2012; accepted
June 3, 2012. Date of publication July 10, 2012; date of current version
May 20, 2013. This work was supported in part by the Extremely Low Power
Project supported by the Ministry of Economy, Trade and Industry, and the
New Energy and Industrial Technology Development Organization.
H. Fuketa, T. Yasufuku, M. Takamiya, and T. Sakurai are with theInstitute of Industrial Science, University of Tokyo, Tokyo 153-8505,
Japan (e-mail: fuketa@iis.u-tokyo.ac.jp; tdsh@iis.u-tokyo.ac.jp; mtaka@
iis.u-tokyo.ac.jp; tsakurai@iis.u-tokyo.ac.jp).
K. Hirairi, M. Nomura, and H. Shinohara are with the Semiconductor
Technology Academic Research Center, Yokohama 222-0033, Japan (e-mail:hirairi.koji@starc.or.jp; nomura.masahiro@starc.or.jp; shinohara.hirofumi@
starc.or.jp).
Digital Object Identifier 10.1109/TVLSI.2012.2203834

CKB

CK2
CKB

CK2

CK

Fig. 2. Schematic of an FF. The contention occurring at the wired-OR point
increases the VDDmin of FF.

supply voltage when circuits operate without functional errors[8], [9]. Fig. 1 shows the measured VDDmin s of various gate
chains [10]. The VDDmin of the flip-flop (FF) chain is muchhigher than those of the other logic gates, such as the twoinput NAND and NOR. This implies that FFs determine the
VDDmin s of sequential circuits, which might make it impossible
to operate at the most energy-efficient supply voltage of around
0.3 V. Therefore, it is essential to reduce the VDDmin of FFs
for ultralow-voltage circuits.
The increase in the VDDmin of FFs is induced by acontention that occurs at the wired-OR point in the FFs,
as shown in Fig. 2 [11]. To reduce the VDDmin of FFs, thefollowing two techniques have been proposed. 1) The sizesof transistors contained in the FF are adjusted to mitigate thecontention [2], [12]. 2) The architecture of FFs is changed
to eliminate the contention [11]. These techniques, however,result in power and delay penalties as well as additional costs
to re-layout the FFs.
In this brief, higher voltage FF (HVFF), which is a VDDmin aware circuit design technique for separating the VDD of FFs
from that of combinational circuits, is proposed. In HVFF, any

1063-8210/$31.00 © 2012 IEEE

1176

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE 2013

VDDmin of 5000 FF’sof 50 FF’s (514mV)

1

VDD(LOGIC)VDD(FF)1

10-2: Monte Carlo SPICE: Fitted curve

10-3
10-4

Failure rate required toensure correct operation of
50 and 5000 FF’s

10-5

PF(VDD(FF))

10-6
10-7

VDDmin of 5000 FF’s
(514mV)
VDDmin of 50 FF’s
(432mV)

FF

10-1

0

100

200

300

400

500

600

VDD(FF) (mV)Fig. 3. Simulated functional failure rate of a single FF as a function of
supply voltage of FF (VDD(FF) ). The PF (VDD(FF) ) curve is fitted to theresults obtained by Monte Carlo SPICE simulations. The VDDmin s of 50 and5000 FFs are estimated to be 432 and 514 mV, respectively, when the yieldis 99% in a 65-nm CMOS process.

FF architectural modifications are not required, and the VDDof combinational logic gates is reduced below the VDDmin ofFFs while keeping the VDD of FFs at their VDDmin , whichmakes it possible to reduce the minimum energy without
power and delay penalties at the nominal supply voltage. In
this brief, HVFF is applied to a 16-bit integer unit (IU), and themeasurement results indicate that the minimum energy can be
reduced by 13%. In addition, the physical implementation of
HVFF is discussed. This brief reveals that the implementation
is easily carried out using an existing P&R tool and although
the total wire length increases by HVFF, any area, delay, andpower overheads are not observed in our design.
There are several research studies on the dual-VDD
technique. Clustered voltage scaling has been proposed in [13].
In this technique, the reduced power supply voltage is applied
to the circuit on noncritical paths, whereas the nominal supply
voltage is applied to the circuit on critical paths, which makes
it possible to reduce the power dissipation while keeping theentire circuit performance. In [14] and [15], the use of thetechnique for separating the VDD of FFs from that of combinational circuits has been reported. This technique, however, isused for the power gating of combinational circuits. During theoperation mode, the same voltage is supplied to both FFs andcombinational circuits, and the VDDmin of FFs is not considered. To the best of our knowledge, this brief is the first to propose a dual-VDD technique that considers the VDDmin of FFs.
The remainder of this brief is organized as follows. In
Section II, the VDDmin of FFs and the effectiveness of the
proposed HVFF technique are discussed. In Section III, theapplication of HVFF to a 16-bit IU and the measurement
results are shown. Finally, Section IV concludes this brief.
II. V DDmin OF FF S AND HVFF
To estimate the VDDmin of FFs, the dependence of thefunctional failure rate of a single FF on VDD is obtained

Failure rate of single FF

Failure rate of single FF

VDD(LOGIC) < VDD(FF)VDDmin(432mV): VDD(FF)=432mV

10-1(VDDmin of 50 FF’s)?

PF VDD(LOGIC)

10-2: VDD(FF)=514mV?

(VDDmin of 5000 FF’s)

10-3-100mV

10-4: Monte Carlo SPICE: Fitted curve

10-5
10-6
10-7

0

Failure rate requiredfor 5000 FF’s

-140mV

100

400

200

300

500

600

VDD(LOGIC) (mV)Fig. 4. Simulated failure rate of a single FF as a function of supply voltageof combinational logic gates (VDD(LOGIC) ) when supply voltages of FFs andcombinational logic gates are separated and VDD(FF) is kept at VDDmin ofFFs (HVFF) without level converters in a 65-nm CMOS process.

by Monte Carlo SPICE simulations (5000 trials) with withindie threshold voltage variation. Fig. 3 shows the simulated
failure rate as a function of the supply voltage of the FF(VDD(FF)). When PF (VDD(FF) ) is defined as the failure rateof a single FF at VDD(FF), the VDDmin of N-gate FFs can be
expressed as
1 − PF VDDmin

N=Y⇔ VDDmin = PF−1

(1)
1−Y

1
N

(2)

where N is the number of FFs and Y is the yield.
As shown in Fig. 3, PF (VDD(FF) ) is derived from thedependence of the simulated failure rate on VDD(FF) by extrapolation, and the VDDmin of FFs is calculated from (2) using
PF (VDD(FF)). For example, the VDDmin s of 50 and 5000 FFs
are estimated to be 432 and 514 mV, respectively, when theyield Y is 99%.
These estimated VDDmin s are much higher than the mostenergy-efficient supply voltage of around 0.3 V. In conventional circuits with a single power supply, all logic gatesmust operate at the VDDmin of FFs despite the fact thatcombinational logic gates can operate at a supply voltage much
lower than the VDDmin of FFs, which prevents the energy
reduction achieved by VDD scaling. Thus, the energy canbe further reduced, if different supply voltages between FFs
and combinational circuits are supplied.
On the other hand, it is possible that the voltage difference
between FFs and combinational circuits worsens the VDDmin ofFFs without level converters. Fig. 4 shows the dependenceof the failure rate of a single FF on the supply voltage ofcombinational logic gates VDD(LOGIC), when VDD(FF) is kept
at the VDDmin of FFs. The lines represent the fitted PF(failure rate) curves. If PF increases, the VDDmin of FFs

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE 2013

HVFF; separated VDD between
FF’s and combinational logics

VDD(FF)VDD(LOGIC)(1.2 - 0.4V)(1.2 - 0.25V)

VDD(FF)

1177

VSS
VDD(LOGIC)
Power/ground line

Row for FF’s (VDD(FF))
Row for combinational logics (VDD(LOGIC))

Inputswith carry-in
17

Clock

FF

1-bit L/R shifter

16

FFArithmetic andlogic operation unit

16

Inputs17

FF

Row for combinational logics (VDD(LOGIC))

Outputs
with carry-out
17

Row for FF’s (VDD(FF))

Row for FF’s (VDD(FF))

Combinational logic
Integer unit (IU)
Implemented commands
in 16-bit ALU- ADD/SUB with/without saturation

Fig. 6.

HVFF implementation with row-by-row architecture [13].
TABLE IC OMPARISON B ETWEEN IUS W ITH AND W ITHOUT HVFF

- Universal logic operation

IU without HVFF
(Conv.)- MIN/MAX operation

IU with HVFF
(row-by-row architecture)- Absolute difference

Data inputs

FF’s(3 rows)

Data outputs

Data outputs

FF’s(2 rows)

Dual VDD

No

Yes

Total wire length

13.8 mm

14.1 mm (+2.4%)

Maximum
1.2 V
clockfrequency&
0.5 V
Power(*)

1.4 GHz
5.6 mW

1.4 GHz
5.6 mW

110 MHz
76 µW

110 MHz
76 µW

Minimum
Energy(*)

0.54 pJ

0.45 pJ (-17%)@ VDD(FF)=VDD(LOGIC)=432 mV@ VDD(FF) = 432 mVVDD(LOGIC) = 330 mV

Fig. 5. Block diagram of the developed 16-bit IU implemented with theproposed HVFF.

rises according to (2). In Fig. 4, however, the PF curves
do not increase even if VDD(LOGIC)s are reduced by 100 and
140 mV when VDD(FF)s are 432 and 514 mV, respectively.
This indicates that level converters are not required if thevoltage difference between FFs and combinational circuits
is around 100 mV.
When VDD(FF) is 514 mV (in the case of 5000 FFs), theenergy of combinational circuits is reduced by at most 47%.
It should be noted that the VDDmin of combinational circuits
is not considered in this discussion, since it is much lower
than that of FFs, as shown in Fig. 1. If HVFF technique isapplied to random logic circuits, where FFs are used for otherthan inputs and outputs of circuits, such as processor cores,
the delay and power overheads would become larger.

Layout(70 µm x 100 µm)

Combinational
logic gatesFF’s andcombinational logic gates

Data inputs(*) Obtained by simulations.

III. E XPERIMENTAL R ESULTS
A. Overview of IU With HVFF
Fig. 5 shows the block diagram of the developed 16-bit IU
implemented with popular media processing commands [11].
In this brief, HVFF, which is the proposed circuit design
technique for separating the supply voltage of FFs (VDD(FF))
from that of combinational circuits (VDD(LOGIC)), is applied to
the IU. The IU consists of 13K gates including 50 FFs. Level
converters are not used.
B. Physical Design of HVFF
One of the concerns in HVFF is its physical implementation
to separate the VDD of FFs from that of combinational circuits.
In this brief, the so-called row-by-row architecture [13] shownin Fig. 6 is used. In this architecture, each row is assigned for

either FFs or combinational logic gates. The advantages of the
row-by-row architecture are as follows: 1) implementation
is easily carried out using existing P&R tools and 2) any
modifications of standard cells described in [14] and [15] are
not required.
Table I shows the overhead of HVFF with the row-by-row
architecture. The P&R was performed with a fixed area of
70 μm × 100 μm in a 65-nm CMOS process. Comparedwith the IU without HVFF, the total wire length of the IU
with HVFF is increased by 2.4%, yet the delay and power are
not increased and the minimum energy is reduced by 17% in
our design. This is because the IU is suitable for HVFF withthe row-by-row architecture since the number of FFs includedin the IU is relatively large and the FFs are only used for
inputs and outputs.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE 2013

VDD(FF) = 400mV
2G
1G

100

Fail

Clock frequency (MHz)

90
80

70

Fails at any frequencies
below 450mV

60

50
40
30

Pass

20

10
5
350

400

450

500

550

VDD(LOGIC) = VDD(FF) (mV)

VDD(FF) = VDD(LOGIC)
100m
10m

100M

1m

10M

100??

1M

10??

100k

Leakage power of FF’s
Increase due to voltage difference
between combinational logic
gates and FF’s

10k
1k
0.2

0.4

0.6

VDD(FF) = VDD(LOGIC)

100

Fail

Fig. 8. Measured VDD(LOGIC) dependence of maximum clock frequency
and power dissipation of IU which consists of combinational logic gates andFFs at 25 °C. The measured chip is different from the chip shown in Fig. 7,
and the VDDmin of FFs in this chip is 400 mV.

70

VDD(FF)=VDD(LOGIC) (conv.)
HVFF (proposed)

60
50

VDD(FF) = 400mV

Pass

40

VDD(FF) = VDD(LOGIC)

6.0

30

Further VDD scaling
is possible

20
10
5

350

400

450

500

550

VDD(LOGIC) (mV)(b)

Fig. 7. Measured shmoo plot of IU. (a) VDD(FF) is equal to VDD(LOGIC)(conventional). (b) VDD(FF) and VDD(LOGIC) are separated (proposed HVFF).

Energy (pJ/instruction)

Clock frequency (MHz)

90
80

100n
1.2

1.0

VDD(LOGIC) (V)(a)
VDD(FF) = 450mV

0.8

1??

Power dissipation (W)VDDmin= 450mVMaximum clock frequency (Hz)

1178

0.8

Conventional

5.0

4.0
3.0

0.7

Proposed

-13%

1/10

0.6
0.25 0.3 0.35 0.4 0.45

2.0
1.0

C. Measurement Results
A 16-bit IU with HVFF is fabricated in a 65-nm CMOS
process. Fig. 7(a) shows the measured shmoo plot of the
IU with the conventional implementation VDD(FF) is equal
to VDD(LOGIC), while Fig. 7(b) shows the shmoo plot with
HVFF VDD(FF) and VDD(LOGIC) are separated. In Fig. 7(a),the IU does not operate correctly below 450 mV even if theclock frequency is reduced from 35 MHz to 10 kHz, whichindicates that the VDDmin of the IU of this chip is 450 mV.
In contrast, VDD(FF) is fixed to the FF VDDmin of 450 mV
and only VDD(LOGIC) is reduced when VDD(LOGIC) is less than
450 mV, as shown in Fig. 7(b). In this case, the IU with
HVFF is still functional even when VDD(LOGIC) is reduced
to 350 mV.
Fig. 8 shows the measured VDD(LOGIC) dependence of the
maximum clock frequency and the power dissipation of the
IU with HVFF. The VDDmin of the chip is 400 mV. The
power dissipation was measured when the add operation
with random input patterns was performed. As the voltage
difference between FFs and combinational circuits increases,
the power dissipation of FFs increases, since level converters
are not used. However, when the voltage difference is 100
mV (VDD(FF) = 400 mV and VDD(LOGIC) = 300 mV), theleakage power of FFs increases by 29%, whereas the total

0
0.2

0.4

0.6

0.8

1.0

1.2

VDD(LOGIC) (V)
Fig. 9. Measured energy of IU. The proposed IU with HVFF (VDD(LOGIC) =320 mV and VDD(FF) = 400 mV) can achieve a minimum energy of 0.61 pJ,
which is 13% smaller than that of conventional operation (VDD(LOGIC) =VDD(FF) . The VDDmin of FFs is 400 mV.

power of combinational logic gates and FFs is reduced by
85% at 25 °C. Although the rise in temperature increases theleakage power, the reduction of the total power is estimated to
be still 62% at 85 °C by simulation. Therefore, the increase in
the leakage power of FFs due to the voltage difference between
FFs and combinational circuits is not a critical problem in
actual use.
Fig. 9 shows the measured energies of the IUs with theconventional operation and HVFF. The minimum energy of
the IU with the conventional operation is 0.70 pJ/instruction
at VDD(LOGIC) = VDD(FF) = 400 mV, which is equivalent
to the VDDmin of FFs. On the other hand, the minimum
energy of 0.61 pJ/instruction is achieved in the IU with HVFF
when VDD(LOGIC) = 320 mV and VDD(FF) = 400 mV, whichis 13% smaller than that obtained in the case of conventional

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE 2013

70 µm
IU

100 µm

0.9 mm

1.2 mmFig. 10. Chip micrograph fabricated in a 65-nm CMOS process. The IU
occupies 70 μm × 100 μm.

operation and is 1/10 times smaller than the energy at thenominal supply voltage of 1.2 V. In addition, HVFF has noenergy penalties above 400 mV. This indicates that HVFF can
reduce the minimum energy without any energy penalties at
the nominal supply voltage.
Finally, the chip micrograph is shown in Fig. 10.
IV. C ONCLUSION
To achieve the most energy-efficient operation, HVFF,
which is a VDDmin -aware circuit design technique for separating the VDD of FFs from that of combinational circuits, wasproposed. In HVFF, the VDD of combinational logic gates isreduced below the VDDmin of FFs while keeping the VDD of
FFs at their VDDmin to reduce the energy, since the VDDminof FFs is much higher than that of combinational logic gates.
HVFF was applied to a 16-bit IU. The measurement results
in a 65-nm CMOS process showed that HVFF can reducethe minimum energy by 13% compared with conventional
operation, which is 1/10 times smaller than the energy at thenominal supply voltage, without power and delay penalties at
the nominal supply voltage, as well as without FF topologicalmodifications.
R EFERENCES[1] A. W. Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-Threshold
Design for Ultralow Power Systems. New York: Springer-Verlag,
2006.
[2] H. Kaul, M. Anders, S. Mathew, S. Hsu, A. Agarwal, R. Krishnamurthy,
and S. Borkar, “A 320mV 56 μW 411 GOPS/Watt ultralow voltage
motion estimation accelerator in 65 nm CMOS,” in IEEE Int. SolidState Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 316–317.

1179[3] Y. Pu, J. P. Gyvez, H. Corporaal, and H. Yajun, “An ultralowenergy/frame multi-standard JPEG co-processor in 65 nm CMOS with
sub/near-threshold power supply,” in IEEE Int. Solid-State Circuits Conf.
Dig. Tech. Papers, Feb. 2009, pp. 146–147.
[4] H. Kaul, M. A. Anders, S. K. Mathew, S. K. Hsu, A. Agarwal, R.
K. Krishnamurthy, and S. Borkar, “A 300 mV 494 GOPS/W reconfigurable dual-supply 4-way SIMD vector processing accelerator in 45 nm
CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb.
2009, pp. 260–261.
[5] A. Agarwal, S. K. Mathew, S. K. Hsu, M. A. Anders, H. Kaul, F.
Sheikh, R. Ramanarayanan, S. Srinivasan, R. Krishnamurthy, and S.
Borkar, “A 320 mV-to-1.2 V on-die fine-grained reconfigurable fabricfor DSP/media accelerators in 32 nm CMOS,” in IEEE Int. Solid-State
Circuits Conf. Dig. Tech. Papers, 2010, pp. 328–329.
[6] J. Kwong, Y. Ramadass, N. Verma, M. Koesler, K. Huber, H. Moormann,and A. Chandrakasan, “A 65 nm sub-Vt microcontroller with integrated
SRAM and switched capacitor DC-DC converter,” IEEE J. Solid-State
Circuits, vol. 44, no. 1, pp. 115–126, Jan. 2009.
[7] B. H. Calhoun and A. P. Chandrakasan, “Ultradynamic voltage scaling(UDVS) using sub-threshold operation and local voltage dithering,”
IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 238–245, Jan. 2006.
[8] T. Yasufuku, S. Iida, H. Fuketa, K. Hirairi, M. Nomura, M. Takamiya,
and T. Sakurai, “Investigation of determinant factors of minimum
operating voltage of logic gates in 65-nm CMOS,” in Proc. Int. Symp.
Low Power Electron. Design, Aug. 2011, pp. 117–122.
[9] H. Fuketa, S. Iida, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara,
and T. Sakurai, “A closed-form expression for estimating minimum
operating voltage (V D Dmin ) of CMOS logic gates,” in Proc. Design
Autom. Conf., Jun. 2011, pp. 984–989.
[10] T. Yasufuku, K. Hirairi, Y. Pu, Y. F. Zheng, R. Takahashi, M. Sasaki, H.
Fuketa, A. Muramatsu, M. Nomura, H. Shinohara, M. Takamiya, and T.
Sakurai, “245% power reduction by post-fabrication dual supply voltage
control of 64 voltage domains in V D Dmin limited ultralow voltage logic
circuits,” in Proc. Int. Symp. Quality Electron. Design, 2012, pp. 586–
591.
[11] H. Fuketa, K. Hirairi, T. Yasufuku, M. Takamiya, M. Nomura, H.
Shinohara, and T. Sakurai, “A 12.7-times energy efficiency increase of
16-bit integer unit by power supply voltage (V D D ) scaling from 1.2V
to 310 mV enabled by contention-less flip-flops (CLFF) and separated
V D D between flip-flops and combinational logics,” in Proc. Int. Symp.
Low Power Electron. Design, Aug. 2011, pp. 163–168.
[12] B. H. Calhoun, A. Wang, and A. Chandrakasan, “Modeling and sizing
for minimum energy operation in subthreshold circuits,” IEEE J. SolidState Circuits, vol. 40, no. 9, pp. 1778–1786, Sep. 2005.
[13] K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M. Kanazawa, M.
Ichida, and K. Nogami, “Automated low-power technique exploiting
multiple supply voltages applied to a media processor,” IEEE J. SolidState Circuits, vol. 33, no. 3, pp. 463–472, Mar. 1998.
[14] J. S. Wang, H. Y. Li, C. Yeh, and T. F. Chen, “Design techniques for
single-low-V D D CMOS systems,” IEEE J. Solid-State Circuits, vol. 40,
no. 5, pp. 1157–1165, May 2005.
[15] J. S. Wang, J. S. Chen, Y. M. Wang, and C. Yeh, “A 230 mV-to500 mV 375 KHz-to-16 MHz 32b RISC Core in 0.18?m CMOS,”
in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2007,
pp. 294–295.