0.5-V Input Digital LDO
with 98.7% Current Efficiency and2.7-µA Quiescent Current in 65nm CMOS
Yasuyuki Okuma1, Koichi Ishida2, Yoshikatsu Ryu1, Xin Zhang2, Po-Hung Chen2,
Kazunori Watanabe1, Makoto Takamiya2, and Takayasu Sakurai2
1
Semiconductor Technology Academic Research Center (STARC),
3-17-2 Shin Yokohama, Kohoku-ku, Yokohama 222-0033, Japan
2
The University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan
Abstract- Digital LDO is proposed to provide the low noise andtunable power supply voltage to the 0.5-V near-threshold logic
circuits. Because the conventional LDO feedback-controlled by
the operational amplifier fail to operate at 0.5V, the digital LDO
eliminates all analog circuits and is controlled by digital circuits,
which enables the 0.5-V operation. The developed digital LDO in
65nm CMOS achieved the 0.5-V input voltage and 0.45-V output
voltage with 98.7% current efficiency and 2.7-µA quiescentcurrent at 200-µA load current. Both the input voltage and thequiescent current are the lowest values in the published LDO’s,
which indicates the good energy efficiency of the digital LDO at
0.5-V operation.

LDO shown in Fig. 1(b) is proposed. The digital LDO
includes a switch array, a comparator, and a digital controller.
The analog controlled power transistor is replaced with theswitch array and the number of turned-on switches is changed
digitally by the controller. The output voltage (VOUT) is
monitored by the comparator instead of the operational
amplifier. Thus, the digital LDO eliminates all analog circuits
and is controlled by digital circuits, which enables the 0.5-V
LDO operation, because the digital circuits including the
VIN
AnalogVREF

I. INTRODUCTION

II. PROPOSED DIGITAL LDO
In order to explain the concept of the proposed digital
LDO, Fig. 1 shows the circuit schematic of the digital LDO incontrast with the conventional analog LDO. The conventional
analog LDO shown in Fig. 1(a) consists of an operational
amplifier and a power transistor. The conventional LDO fails
to operate at 0.5V, because the operational amplifier does notoperate at 0.5V and can not control the analog gate voltage ofthe power transistor. In order to solve the problem, the digital

978-1-4244-5759-5/10/$26.00 ©2010 IEEE

Load

VOUT

(a)
n-bit
digitalVIN
M1Comparator
VREF

Controller

M2
M3
Mn
VOUT
Load

Very low-voltage operation of VLSI's is effective in
reducing both dynamic and leakage power and the maximum
energy efficiency is achieved at low power supply voltage(VDD) below 0.5V (e.g., 340 mV [1] and 320 mV [2]). Thus,
many works have been carried out on the sub/near-thresholdlogic circuits [1-5]. Stable and tunable VDD (e.g., 320 mV±
50mV [2]) is required in the near-threshold logic circuits,
because the gate delay in the near-threshold logic circuits isvery sensitive to VDD and the process variations. Therefore, a0.5-V LDO enabling the low ripple and tunable VDD isstrongly required. The conventional analog LDO, however,fails to operate at 0.5V. In order to solve the problem, thedigital LDO enabling the 0.5-V operation is proposed anddemonstrated in this paper. The concept and the circuit
implementation of the proposed digital LDO is shown in
Section II. Measurement results from 65-nm CMOS test chips
are described in Section III.

(b)
Fig. 1. (a) Conventional analog LDO. (b) Proposed digital LDO.

comparator can operate at 0.5V.
Fig. 2 shows is the circuit schematic of the fabricateddigital LDO. The digital LDO consists of a comparator, aserial-in parallel-out bi-directional shift register, and switch
array of 256 pMOS FET’s. In order to reduce the ripple due tothe switching of the switches, in this implementation, the shift
register is used as the controller, because the number ofswitching in the switch array is only one at each clock edge.
The typical input voltage (VIN) and VOUT are 0.5V and 0.45V,
respectively. The typical clock frequency of the comparator
and the shift register is 1MHz. The off-chip decouplingcapacitor is 100nF and the typical load current (ILOAD) is
200µA.
Fig. 3 shows the circuit schematic of the clocked
comparator used in the digital LDO. In the design of LDO
with ILOAD of 200µA, low quiescent current is very important,because the large quiescent current degrades the current
efficiency of LDO. In order to reduce the quiescent current,
the clocked comparator is used in the digital LDO, because theclocked comparator can operate at 0.5V and consumes no DCpower.
Fig. 4(a) shows the operation of the bi-directional shift
register. At first, all 256 bits are set to “1” in order to turn off
all pMOS switches. After that, when the comparator output(Compout) is low, which means VOUT is lower than thereference voltage (VREF), all 256 bits are shifted toward rightin order to increase the number of turned-on switches. In
contrast, when Compout is high, which means VOUT is higher
than VREF, all 256 bits are shifted toward left in order todecrease the number of turned-on switches.
Fig. 4(b) shows the circuit implementation of the serial-inparallel-out bi-directional shift register. The bi-directional
shift register consists of selectors and D-FF’s. The shift-rightor the shift-left operation of the bi-directional shift register isdetermined by Compout. When Compout is low, each QK
except Q1 moves to QK+1, and Q1 is set to “0”, which achieves
the shift-right operation. In contrast, when Compout is high,each QK except Q256 moves to QK-1, and Q256 is set to “1”,which achieves the shift-left operation.
Fig. 5 shows the schematic of the transient of the numberof turned-on switches in order to explain the feedback controlof the digital LDO. The digital LDO controls the number ofturned-on switches at each clock edge depending on Compout.
When VOUT equals to VREF, the number of turned-on switcheschanges up and down by 1-bit, which determines the ripple ofthe digital LDO.

VIN (0.5V)
On chip

Off chip

Q1
Serial-in
Q2parallel-out Q
bi-directional 3
Compout
shift register(Fig. 4(b)) Q256

VREF
(0.45V)

VOUT(0.45V)
Clk(1MHz)

100nF

Switch array

ILOAD(200µA)

Fig. 2. Circuit schematic of the fabricated digital LDO.

Compout

VREF

VOUT
Clk

Fig. 3. Circuit schematic of clocked comparator used in digital LDO.

0(i) Initialize(Step = 0)

Q1

Qk-1 Qk Qk+1 Qk+2

1

1

1

Q256

1

1

1

1

All “1” = All switches are turned off.

0(ii) Step = x

0

0

1

1

1
Shift right(iii-a) Step = x+1(when Compout = L) 0

0

0

0

1

1

(iii-b) Step = x+10(when Compout = H)

0

1

1

1

1

Shift left(a)III. MEASUREMENT RESULTS AND DISCUSSION
Q1

To demonstrate the advantage of the proposed digital LDO,
a test chip is fabricated in 65nm CMOS. Fig. 6 shows the chip
microphotograph and the layout. The total chip area including
pads is 0.9×0.8mm2 and the active area of the digital LDO is
0.042mm2.
Fig. 7(a) shows measured VOUT – VIN characteristics at
ILOAD of 200µA. VREF is varied from 0.35V to 0.55V by 0.05V step. The digital LDO successfully regulates VOUT from
0.35 to 0.45V at VIN of 0.5V. At the design target of VIN of
0.5V and VOUT of 0.45V, the dropout voltage is 50mV and themeasured line regulation is 3.1mV/V. Fig. 7(b) shows
measured VOUT – VIN characteristics at VREF of 0.45V. ILOAD isvaried from 20µA to 200µA. The LDO achieves a successful
load regulation of 0.65mV/mA with VIN from 0.5V to 1.2V.
Fig. 8 shows the measured ILOAD dependence of the current
efficiency and the quiescent currents at 1-MHz and 10-MHz
clock. Thanks to the digital LDO architecture, the measured
quiescent current does not depend on ILOAD, though thequiescent current increases with ILOAD in the conventional
analog LDO. At 1-MHz clock, the measured quiescent current

Qk-1

Qk

Q2
D Q

Q1
S

Q255

Qk-1

D Q

Qk
S

Q256
1

Qk+2

D Q

0

Qk+1

D Q

Qk+1

Q255

S

S

Compout
Clk
Set

(b)
Fig. 4. (a) Operation of bi-directional shift register. (b) Circuit
implementation of serial-in parallel-out bi-directional shift register.
Number of turned-on switches
256
Target0

Step

Fig. 5. Schematic of the transient of the number of turned-on switches inorder to explain feedback control of digital LDO.

Shift register

900µm

Switch array
Comparator

Fig. 6. Chip microphotograph and layout.

0.6

95

Clk=10MHz

90
85

20
Clk=10MHz

15

80

10
75

5

Clk=1MHz

70
0

50

100
150
200
Load current (ILOAD) [µA]

Quiescent current (IQ) [µA]

Clk=1MHz

0250

VREF=0.45V
VREF=0.40V

0.4
VOUT [V]100

Fig. 8. Measured ILOAD dependence of the current efficiency and thequiescent currents at 1-MHz and 10-MHz clock.

VREF=0.55V
VREF=0.50V

0.5

Fig. 10 shows the measured transient waveform of VOUT
when VREF changes between 0.4V to 0.45V at 100Hz. The
clock frequency is 1MHz and ILOAD is 200µA. Fig. 11 shows
the measured transient waveform of VOUT when ILOAD changes
between 0A to 200µA at 100Hz. VOUT is 0.45V and the clock
frequency is 1MHz. The measured undershoot and overshootof VOUT are 40mV and 30mV, respectively. As shown in Figs.
10 and 11, these results show reasonable performance of thedigital LDO to be applied to the power supply for nearthreshold logic circuit.
Since the switch array in the digital LDO is switched
Current efficiency () [%]800µm

is 2.7µA, which is the smallest quiescent current in LDO’s tothe author’s knowledge. The current efficiency is 98.7% at
ILOAD of 200µA.
Fig. 9 shows the measured transient waveform of VOUT
when VREF changes from 0V to 0.45V at 1-MHz and 10-MHz
clock and ILOAD of 200µA. The settling time of VOUT at 1-MHz
clock is 590µs. By increasing the clock frequency from 1MHz
to 10-MHz, the settling time can be reduced by 60% from
590µs to 240µs at the cost of increasing quiescent current
from 2.7µA to 15µA and the corresponding degradation of thecurrent efficiency by 5% at ILOAD of 200µA as shown in Fig. 8.
The tunable performance by changing the clock frequency isthe advantage of the digital LDO.

0.45V

VREF

VREF=0.35V

0V

0.3

0.45V

Target of this work

0.2

VOUT@Clk=10MHz

0.1

ILOAD=200µA

VOUT@Clk=1MHz

0
0

0.2

0.4

0.6
VIN [V]
(a)

0.8

1

1.2

0V
240µs

0.5

590µs

ILOAD=200µA

Fig. 9. Measured transient waveform of VOUT when VREF changes from 0V
to 0.45V at 1-MHz and 10-MHz clock and ILOAD of 200µA.

VOUT [V]0.4
ILOAD=100µA

0.3

VOUT

0.45V
0.4V

0.2

ILOAD=200µA

ILOAD=20µA

ILOAD=200µA

0.1
VREF=0.45V
0

0

0.2

0.4

0.6
VIN [V]

0.8

1

1.2

(b)
Fig. 7. Measured VOUT – VIN characteristics. (a) VREF is varied from 0.35V
to 0.55V at ILOAD of 200µA. (b) ILOAD is varied from 10µA to 200µA at
VREF of 0.45V.

VREF

0.45V
0.4V
10ms

Fig. 10. Measured transient waveform of VOUT when VREF changes
between 0.4V to 0.45V at 100Hz. The clock frequency is 1MHz and ILOAD
is 200µA.

TABLE I
KEY PERFORMANCE SUMMARY OF THE PROPOSED DIGITAL LDO ANDCOMPARISON WITH PREVIOUS REGULATORSVOUT =0.45V

30mV

Unit

40mV

ILOAD

0µA
200µA
10ms

Fig. 11. Measured transient waveform of VOUT when ILOAD changes
between 0A to 200µA at 100Hz. VOUT is 0.45V and the clock frequency is
1MHz.
ILOAD=200µA, VREF= 0.45V

VOUT=0.45V

3mV

Type of regulator-

Control
CMOS Technology
Active area
Minimum input
voltageNominal output
voltage
Maximum load
current
Line regulation
Load regulation
Decoupling
capacitor

mm2

0.5V

1µs

Fig. 12. Measured waveforms of VOUT and 1-MHz clock. VOUT is 0.45V
and ILOAD is 200µA.

digitally, the clock-related digital noise may cause LDO
output ripple. To evaluate the ripple caused by the digitalnoise, output ripple is measured as shown in Fig. 12. VOUT is
0.45V and the clock frequency is 1MHz. The ripple of VOUT is
less than 3mV. The measured VOUT shows no significant
ripple at clock edges and its harmonic tones, which indicatesthat the clock-related digital noise does not affect the LDO
output ripple in the developed digital LDO.
The key performance summary of the proposed digital
LDO and comparison with some previous regulators are listed
in Table I. The digital control is proposed in [6]. The regulatorin [6], however, is not LDO but a half VDD generator. In thispaper, both the digital LDO and 0.5-V LDO are demonstrated
for the first time. The developed digital LDO achieved the 0.5V input voltage and 0.45-V output voltage with 98.7% current
efficiency and 2.7-µA quiescent current at 200-µA load
current. Both the input voltage and the quiescent current are
the lowest values in the published LDO’s.

IV. CONCLUSION
In this paper, the digital LDO enabling the 0.5-V operation
is proposed and demonstrated for the first time. The developed
digital LDO in 65nm CMOS achieved the 0.5-V input voltage
and 0.45-V output voltage with 98.7% current efficiency and2.7-µA quiescent current at 200-µA load current. Both the
input voltage and the quiescent current are the lowest values in
the published LDO’s, which indicates the good energy
efficiency of the digital LDO at 0.5-V operation.

[8]

[9]

LDO

LDO

LDO

Analog350nm
0.264

Analog350nm
0.053

Digital
65nm
0.042This work

V

2.4

1.2

2

1.05

0.5

V

1.2

0.9

1.8

0.9

0.45

mA

1000

100

200

50

0.2

mV/V
mV/mA

-

1

2
0.17

1.1
0.06

3.1
0.65

µF

0.00240.00061
1
0.1(on-chip) (on-chip) (off-chip) (off-chip) (off-chip)Quiescent current

µA

25700

6000

20 to 320

Current efficiency

%

97.5

94.3

99.8

4.02 to
164
99.7

2.7
98.7

ACKNOWLEDGMENTS

5mV

Clk =1MHz[6][7]
Half VDD
LDO
generator
DigitalAnalog
90nm
90nm
0.03
0.008

The authors would like to thank Yu Pu for his help during
the design of this test chip and Hirofumi Shinohara for his
support and encouragement. This work was carried out as apart of Extremely Low Power (ELP) project supported by the
New Energy and Industrial Technology Development
Organization (NEDO).

REFERENCES
[1]

[2]

[3]

[4]

[5]
[6]

[7]

[8]

[9]

A. Agarwal, Amit, S. Mathew, S. Hsu, M. Anders, H. Kaul, F. Sheikh,
R. Ramanarayanan, S. Srinivasan, R. Krishnamurthy, and S. Borkar, "A
320mV-to-1.2V on-die fine-grained reconfigurable fabric for
DSP/Media accelerators in 32nm CMOS," IEEE International SolidState Circuits Conference, pp. 328-329, Feb. 2010.
H. Kaul, M. Anders, S. Mathew, S. Hsu, A. Agarwal, R. Krishnamurthy,
and S. Borkar, "A 320mV 56µW 411GOPS/Watt ultra-low voltage
motion estimation accelerator in 65nm CMOS," IEEE International
Solid-State Circuits Conference, pp. 316-317, Feb. 2008.
B. Calhoun and A. Chandrakasan, "Ultra-dynamic voltage scaling(UDVS) using sub-threshold operation and local voltage dithering,"
IEEE Journal of Solid-State Circuits, Vol. 41, No. 1, pp. 238-245, Jan.
2006.
S. Hanson, B. Zhai, M. Seok, B. Cline, K. Zhou, M. Singhal, M.
Minuth, J. Olson, L. Nazhan-dali, T. Austin, D. Sylvester, and D.
Blaauw, "Performance and variability optimization strategies in a sub200mV, 3.5pJ/inst, 11nW subthreshold processor," IEEE Symposium
on VLSI Circuits, pp. 152-153, June 2007.
M. Hwang, A. Raychowdhury, K. Kim, and K. Roy, "A 85mV 40nW
process-tolerant subthreshold 8x8 FIR filter in 130nm technology,"IEEE Symposium on VLSI Circuits, pp. 154-155, June 2007.
P. Hazucha, S. T. Moon, G. Schrom, F. Paillet, D. S. Gardner, S.
Rajapandian, and T. Karnik, "A linear regulator with fast digital control
for biasing integrated DC-DC converters," IEEE International SolidState Circuits Conference, pp. 536 - 537, Feb. 2006.
P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan, and S.
Borkar, “Area-efficient linear regulator with ultra-fast load regulation,”
IEEE Journal of Solid-State Circuits, Vol.40, no.5, pp. 933-940, Apr.
2005.
M. Al-Shyoukh, H. Lee, and R. Perez, "A transient-enhanced lowquiescent current low-dropout regulator with buffer impedance
attenuation," IEEE Journal of Solid-State Circuits, Vol.42, no.8, pp.
1732-1742, Aug. 2007.
Y. H. Lam and W. H. Ki, "A 0.9V 0.35um adaptively biased CMOSLDO regulator with fast transient response," IEEE International SolidState Circuits Conference, pp. 442-443, Feb. 2008.