IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH 2005

719

A 6.7-fF=m2 Bias-Independent Gate Capacitor(BIGCAP) With Digital CMOS Process and Its
Application to the Loop Filter of a Differential PLL
Makoto Takamiya, Member, IEEE, and Masayuki Mizuno, Member, IEEE

Abstract—A linear bias-independent gate capacitor (BIGCAP)
with large intrinsic capacitance and low parasitic capacitance is
proposed. BIGCAP is composed of a pair of accumulation-moden-poly gate capacitors in an n-well and a pair of pMOS gate
capacitors, which requires no additional fabrication process steps.
Measured results with 1.5-V 0.13- m digital CMOS technology
show that the intrinsic capacitance is 6.7 fF m2 (6.7 times bigger
than that of typical MIM capacitors) and the parasitic capacitanceis 1.9% of the intrinsic capacitance (1/5 that of typical MIM capacitors). The linearity is 2.9% and capacitance variation acrossa wafer is as small as = 0.096%. For a 0.1-V threshold voltage
variation, the capacitance variation was only
= 0.69% andthe linearity ranged from 2.84% to 2.93%. For three types of
BIGCAP using 1.5-V, 2.5-V, and 3.3-V MOSFETs, less than 4%
linearity is achievable by optimizing the ratio ( ) of the pMOS
gate capacitors’ area to the area of the n-poly gate capacitors, andthe optimum value is within a range of 15%–25%.
BIGCAP has been applied to the loop filter of a differential
phase-locked loop (PLL) and reduces the gate area of the largest
loop filter capacitor to only 35% of that of the conventional design
while achieving reasonable jitter of 7.0 ps (rms) and 74.4 ps(peak-to-peak) at 840 MHz with a 1.5-V supply.
Index Terms—Bias dependence, differential, gate capacitor, loop
filter, phase-locked loop (PLL).

I. INTRODUCTION

B

IAS-INDEPENDENT (i.e., linear) capacitors areneeded for many applications such as the loop filterof a phase-locked loop (PLL), level-shifter in I/O buffers,
switched-capacitor circuits, phase compensation in operational
amplifiers, data converters, and mixers. Metal–insulator–metal(MIM) or poly-to-poly capacitors are often used for bias-independent capacitors. Fig. 1 shows the capacitance density and thelinearity of various capacitors in a 0.13- m CMOS. MIM andpoly-to-poly capacitors have excellent linearity. However, theyrequire extra process steps and have small capacitance density.
Recently, interdigitated metal capacitors such as vertical parallel plate capacitors [1]–[3] that require no additional process
steps have been proposed. Kim et al. [3] presented a verticalparallel plate capacitor with 80% greater capacitance density
than an MIM capacitor in a 0.12- m CMOS, however, it usedas many as eight metal layers and the capacitance density wasless than 1/5 of that of conventional MOS gate capacitors. On
Manuscript received April 21, 2004; revised November 22, 2004.
The authors are with the System Devices Research Laboratories, NEC Corporation, Kanagawa 229-1198, Japan (e-mail: mizuno@mel.cl.nec.co.jp).
Digital Object Identifier 10.1109/JSSC.2005.843620

Fig. 1. The capacitance density and the linearity of various capacitors in a
0.13-m CMOS.

the other hand, conventional MOS gate capacitors have large
capacitance density and need no extra process steps. However,the linearity in MOS gate capacitors is terrible. There is a large
gap between MIM capacitors and MOS gate capacitors in termsof the linearity and the capacitance.
In this paper, we propose a novel bias-independent gate
capacitor (BIGCAP) to bridge the gap. The BIGCAP structure
can be fabricated using a standard digital CMOS process withno extra process steps, has good linearity performance, andachieves high capacitance density. Bias-independent MOS gate
capacitors have also been proposed in [4]–[6]; however, they
have the following shortcomings: 1) the capacitance density
is small, because the gate capacitors are serially connected[4]–[6], and 2) the functional bias range is narrow [5], [6]. Our
BIGCAP solves both of these problems. The BIGCAP wasapplied to the loop filter of a differential PLL, and normal PLL
operation was possible at small area.
II. BIGCAP CONCEPTS AND CONFIGURATIONS
Fig. 2 shows the configuration of BIGCAP, which is composed of a pair of accumulation-mode n-poly gate capacitors in
an n-well and a pair of pMOS gate capacitors. All these capacitors can be fabricated using the standard digital CMOS process,because the pMOS gate capacitors are the same as pMOSFETs
and the n-poly gate capacitors are the same as nMOSFETs with
the n-well which is also used for pMOSFETs. In order to obtainsymmetrical bias dependence, i.e., bipolarity, each pair has thesame layout and only the connections are reversed.
Fig. 3 shows the measured – characteristics of n-poly gate
capacitors and pMOS gate capacitors fabricated with a 1.5-V
0.13- m digital CMOS technology [7]. The thin solid lines are

0018-9200/$20.00 © 2005 IEEE720

Fig. 2. Configuration of BIGCAP. The bias dependence of the capacitance ofthe n-poly and pMOS gate capacitors cancel each other out.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH 2005

Fig. 4. Measured C –V characteristics of BIGCAP fabricated with a 1.5-V
0.13-m CMOS for various values of x at a fixed area of the n-poly gate
capacitors.

condition under the gate electrode changes from an inversion
condition to a depletion condition to an accumulation condition[8]. In contrast, the – curve of the single n-poly gate capacitor shown in Fig. 3(a) reveals that the capacitor variation varies
from small to large under the same bias conditions as the surface
condition changes from the depletion condition to the accumulation condition. As shown in Fig. 3(a), the pair of n-poly gate
capacitors shows its maximum capacitance at 0 V, while the pairof pMOS gate capacitors [Fig. 3(b)] shows its minimum capacitance at 0 V. The n-poly and pMOS gate capacitors demonstrate the opposite bias dependence of capacitance. Therefore,by combining them appropriately, the bias dependence of the capacitance of the n-poly and pMOS gate capacitors can be used
to cancel each other out and we can achieve a very low dependence of capacitance on bias.
III. EXPERIMENTAL RESULTS OF BIGCAP
A. Linearity

Fig. 3. Measured C –V characteristics. (a) The pair of n-poly gate capacitors.
(b) The pair of pMOS gate capacitors.

the data for a single capacitor. The broken lines are the data fora single capacitor where the connection is reversed. The thicklines are the data for the pair of capacitors. The shape of the– curve of the single pMOS gate capacitor is different fromthat of the single n-poly gate capacitor due to its ready access toboth holes and electrons from n+ and p+ diffusion regions next
to the pMOS gate. In contrast, the n-poly gate has ready accessonly to electrons from nearby n+ diffusion regions. As shown inthe – curve of the single pMOS gate capacitor in Fig. 3(b), an
increase of the bias voltage from 2 V to 2 V leads to a capacitance variation from large to small to large as the silicon surface

Fig. 4 shows the measured – characteristics of BIGCAP
fabricated with a 1.5-V 0.13- m CMOS process. The capacitance was measured at 100 kHz with an HP4284A precisionof the pMOS gate capacitors’ area to
LCR meter. The ratio
the area of the n-poly gate capacitors was varied by changing thepMOS gate capacitors’ area at the fixed area of the n-poly gate
capacitors. When is 0%, BIGCAP uses only the pair of n-polygate capacitors, which is the same as Fig. 3(a), and it shows its
maximum capacitance at 0 V. As is increased, the – curvechanges as shown in Fig. 4. When is 15%, and the curve is theflattest. Fig. 5 shows the dependence of the linearity extracted
from Fig. 4 on . The linearity is defined as the difference between the maximum capacitance and the minimum capacitancenormalized by twice the average capacitance from 2 V to 2 V.
There is an optimum to realize good linearity. The best linearity of 2.9% was achieved when was 15%. This optimum
value depends on each CMOS process.
In order to investigate the CMOS process dependence of the
optimum value, we studied the optimum and the best linearity for BIGCAP using two other CMOS processes. In our
1.5-V 0.13- m CMOS [7], thick-oxide MOSFETs for 2.5-V
and 3.3-V I/O are available. Fig. 6(a) and (b) show the –TAKAMIYA AND MIZUNO: A 6.7-fF

Fig. 5.

m BIAS-INDEPENDENT GATE CAPACITOR (BIGCAP) WITH DIGITAL CMOS PROCESS

Dependence of the linearity on x extracted from Fig. 4.

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Fig. 7. Dependence of the linearity on x extracted from Fig. 6. The data in
Fig. 5 are also included.

Fig. 8. Equivalent circuit of BIGCAP.

included in Fig. 7. For 2.5-V MOSFETs, the best linearity of
2.9% was achieved, when was 15%, which is the same as
1.5-V MOSFETs. For 3.3-V MOSFETs, the best linearity of
3.9% was achieved, when was 25%. Therefore, BIGCAP
achieves better than 4% with an optimum in the range of
15%–25% for each of the three 0.13- m CMOS process variations considered.
B. Parasitic CapacitanceFig. 6. C –V characteristics of BIGCAP using thick-oxide MOSFETs forvarious values of x at a fixed area of the n-poly gate capacitors. (a) 2.5-V
MOSFETs. (b) 3.3-V MOSFETs.

characteristics of BIGCAP using 2.5-V and 3.3-V thick-oxide
MOSFETs, respectively. was varied by changing the pMOS
gate capacitors’ area while the n-poly gate capacitors’ area remained fixed. The capacitance of the 200- m pMOS gate capacitors and the 200- m n-poly gate capacitors was measured
separately at 10 kHz, and the capacitance of BIGCAP was calculated by combining the measured results. Fig. 7 shows thedependence of the linearity extracted from Fig. 6 on . The dataof BIGCAP using 1.5-V thin-oxide MOSFETs in Fig. 5 are also

Fig. 8 shows an equivalent circuit of BIGCAP. The intrinsic
is gate capacitance, and the parasitic capacicapacitanceis the capacitance between the n-well and p-subtancestrate. When was 15%,of BIGCAP using 1.5-V thinoxide MOSFETs was 6.7 fF m , which is 70% of the gate
capacitance of 9.6 fF m at inversion. Fig. 9 shows the meaof BIGCAP on the terminal voltage,
sured dependence ofwhen was 15%. The terminal voltage is a voltage between T1(or T2) shown in Fig. 8 and the ground. The measured sample
was the same as that used in Fig. 4. As the terminal voltage indecreases because the parasitic capacitance is acreases,reverse-biased p-n junction. The measured
was as smallof.
asFig. 10(a) shows the calculated dependence of the relativeonfor various gateparasitic capacitancelengths. Here,isoverin percentage. A measured data point at length equal to 25 m
is shown on the same plot. Fig. 10(b) and (1)–(3) show the722IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH 2005

Fig. 9. Measured dependence of the parasitic capacitance of BIGCAP on theterminal voltage, when x was 15%. The measured sample was the same as thatused in Fig. 4.

Fig. 11. Measured C –V characteristics of BIGCAP for various pMOS
threshold voltages.

the design rule,fF m is the gate capacitance, andfF m is the capacitance between the n-well andp-substrate. In (3), the sidewall capacitance of the n-well isneglected so that only the bottom capacitance of the n-well
is varied by changing
is considered. In Fig. 10(a),and. A long
achieves the smallest
for abecause the relative diffusion area resulting
large, fixedfrom a longis smaller than that with a short. In
achieves the smallest
for acontrast, a shortbecause the relative area of a long and narrowsmall, fixed) is larger than the relativen-well (corresponding to a longarea of a square n-well (corresponding to a short). Theseto achieve theresults indicate that there is an optimum
for a given
Whenis larger thansmallest
is achievable.
100 fF, less than 4%
C. Capacitance Variation

Fig. 10. (a) Calculated dependence of the relative parasitic capacitance on the
intrinsic capacitance. (b) Layout of BIGCAP.

layout of BIGCAP and equations used to calculate Fig. 10(a),respectively.
(1)
(2)
(3)
m and
m are the gate width of n-poly gatewherem,capacitors and pMOS gate capacitors, respectively,
m , andm are the minimum spacing determined by

To investigate the capacitance variation, the capacitance valueof BIGCAP when is 15% in Fig. 4 was measured for nine spots
across an 8-inch wafer. The average capacitance was 266.6 pF,
and the maximum and minimum capacitance was 0.21% and0.22% of the average capacitance, respectively. The standard
deviation was as small as 0.096% of the average capacitance,
which is much smaller than the 1.5% reported in [9] because
the capacitance of BIGCAP is determined by the gate-oxide
thickness, unlike the inter-layer dielectrics (ILD) thickness in[9]. Commonly, the gate oxide is made by thermally oxidizing
the silicon substrate, while the ILD is made by a deposition
process such as a chemical vapor deposition (CVD). Therefore,
the thickness variation of the gate oxide is much smaller thanthat of the ILD.
To investigate the process sensitivity, the threshold voltageof MOSFETs was varied. Fig. 11 shows the measured – of
BIGCAP for different pMOS threshold voltages. The thresholdvoltage was varied by changing the channel doping concentration of five wafers. For a 0.1-V threshold voltage variation,
0.69% and the linthe capacitance variation was only
earity ranged from 2.84% to 2.93%. The parasitic capacivariation of five samples in Fig. 11 was also meatance
1.0%.
sured, and it was

TAKAMIYA AND MIZUNO: A 6.7-fF

m BIAS-INDEPENDENT GATE CAPACITOR (BIGCAP) WITH DIGITAL CMOS PROCESS

Fig. 13.

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Block diagram of a fabricated differential PLL.

Fig. 12. Measured dependence of the quality factor (Q) of BIGCAP on
frequency.
TABLE IPERFORMANCE SUMMARY

Fig. 14. Configuration of the loop filter of the differential PLL.
(a) Conventional configuration. (b) Proposed configuration. BIGCAP was used
for C in (b), and n-poly gate capacitors were used for the other capacitances.

D. Quality Factor
Fig. 12 shows the dependence of the quality factor ( ) of
BIGCAP on frequency as measured with an HP8510C vector
network analyzer. The is defined in the inset. The gate lengthmeans that BIGCAP is caof BIGCAP is 5 m. Positivemeans that BIGCAP is inductive.
pacitive, while negative
BIGCAP was capacitive below 800 MHz, while BIGCAP was
inductive above 800 MHz due to the parasitic inductance of thetest structures. The resonant frequency was as low as 800 MHz
because the capacitance of BIGCAP was as much as 217 pF.
Therefore, we could not obtain the positive at the frequency
over 800 MHz with our test structures.
However, BIGCAP has the potential for high comparable
to MIM capacitors by a careful layout optimization. For example, for accumulation MOS varactors, which are often usedin RF applications and are the same as the n-poly gate capacitors in BIGCAP, peak of 120 and 56 have been reported at 2.4
and 5 GHz, respectively [10], while MIM capacitors have of
166 and 63 at 2.4 and 5 GHz, respectively [10].
E. Performance Summary
Table I summarizes the performance of our proposed
BIGCAP using 1.5-V thin-oxide MOSFETs and compares itwith conventional MIM and MOS gate capacitors. The linearity
of BIGCAP is 1/20 that of conventional gate capacitors. The
capacitance of BIGCAP is 6.7 times larger than that of MIM capacitors and 70% that of conventional gate capacitors. BIGCAP
needs no extra process steps. The parasitic capacitance andvariations of BIGCAP are the same as those of conventional
gate capacitors. The parasitic capacitance of BIGCAP is lessthan 1/5 that of MIM capacitors. The capacitance variations in
BIGCAP are less than 1/10 that of MIM capacitors, because
the variation in the gate-oxide thickness is smaller than that in
the MIM insulator thickness. Therefore, we see that BIGCAP
offers significant advantages over both MIM and MOS gate
capacitors with regards to simultaneously achieving high capacitive density, good linearity, and low variation.
IV. APPLICATION OF BIGCAP TO THE LOOP FILTER
OF A DIFFERENTIAL PLL
In this section, we discuss the application of BIGCAP to theloop filter of a differential PLL, and achieved normal PLL operation at small area.
Differential PLLs [11]–[16] that have differential control
voltages have often been used to avoid the jitter increase createdby the power supply noise. Fig. 13 shows a block diagram of,) of thea fabricated differential PLL. Two outputs (two charge pump circuits are differential control voltages ofring-oscillator-type VCO. When one of the differential control
voltages increases, the other decreases. The loop filter (LF) isand. The common-mode feedconnected between
back circuit sets the common-mode of the differential control
voltages.
Here, we discuss the LF configuration and the capacitance of
the LF in a differential PLL. Fig. 14(a) shows the conventional
configuration of the LF of a differential PLL, and Fig. 14(b)shows our proposed configuration. Both the loop filters havethe same transfer function. The conventional LF in Fig. 14(a)requires twice as much capacitance as the LF of a single-ended
PLL. Therefore, the PLL area is nearly twice as large, because
it is generally determined by the large capacitance of LF which
in Fig. 14. If the capacitor used in the LF isis shown as
can be inserted between
andbias-independent,

724IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH 2005

Fig. 15. Microphotograph of the fabricated PLL with the proposed loop filter
shown in Fig. 14(b).

as shown in Fig. 14(b). In this case, the capacitance needed to,achieve the same transfer function as in Fig. 14(a) is only
which is 1/4 the size of that in Fig. 14(a) and half the size ofthat of the single-ended PLL. However, a conventional n-polygate capacitor, which is widely used in LF, cannot be inserted
and, because the capacitance of the n-poly
betweengate capacitor changes 60% depending on the bias voltage asshown in Fig. 3(a) and Table I, the transfer function of the PLLchanges, and the jitter will increase. It has been reported that the
proposed LF in Fig. 14(b) can be made by using a bias-independent poly-to-poly capacitor [14]. However, the area of the PLL
is very large, because the capacitance density of the poly-to-poly
capacitor is about 1/10 that of the n-poly gate capacitor. To solve
in Fig. 14(b). BIGCAP
this problem, BIGCAP is applied tois adequately linear for the given PLL application, because the
2.9% capacitance variation depending on the bias voltage asshown in Figs. 4 and 5 is smaller than the typical 20% or more
VCO gain variation across the full VCO range and the variationof the transfer function of the PLL due to the nonlinearity of
BIGCAP is negligible.
A PLL with the proposed LF in Fig. 14(b) was fabricatedusing a 1.5-V 0.13- m CMOS to demonstrate a PLL operation
with BIGCAP. Fig. 15 shows a microphotograph of the fabri, and the n-poly gate cacated PLL. BIGCAP was used forin Fig. 14(b). Parameters of the fabpacitor was used for
pF,
, and
ricated LF were
pF. As shown in Fig. 16, the measured jitter of the PLL
with the proposed LF at 840 MHz was 7.0 ps (rms) and 74.4
ps (peak-to-peak) for a 1.5-V supply. The jitter is larger thanthe previously reported jitter such as 3.3 ps (rms) and 29 ps(peak-to-peak) at 1 GHz for a 2.5-V supply [17]. We guessthat the large jitter is caused not by BIGCAP but by the VCO
and the charge pump. Table II compares the gate area of the
MOS capacitor for the conventional and proposed LFs shown in
Fig. 14. The area of the proposed LF with BIGCAP is only 35%of that of the conventional LF without BIGCAP.
It is 70% of that of a single-ended PLL. Therefore, by applying
the BIGCAP to the LF, we can avoid an increase in PLL area
when changing from the single-ended design to the differential
design.

V. CONCLUSION
The proposed BIGCAP showed good linearity of 2.9%,
large capacitance of 6.7 fF m , and as low as 1.9% relative

Fig. 16. Measured jitter of the PLL with the proposed loop filter. The jitter at
840 MHz was 7.0 ps (rms) and 74.4 ps (peak-to-peak) for a 1.5-V supply.
TABLE IIGATE AREA OF MOS CAPACITOR FOR THE LOOP FILTER FOR THE
DIFFERENT LOOP FILTERS SHOWN IN FIG. 13

parasitic capacitance without any additional fabrication processes on 1.5-V 0.13- m standard digital CMOS technology.
Capacitance variation across a wafer was as small as
0.096%. For a 0.1-V threshold voltage variation, the capacitance variation was only
0.69% and the linearity ranged
from 2.84% to 2.93%. In order to investigate the CMOS
process dependence of the optimum value, we studied the optimum and the best linearity for BIGCAP in three variationsof the 0.13- m CMOS process. For 2.5-V MOSFETs, the best
linearity of 2.9% was achieved, when was 15%, which isthe same as 1.5-V MOSFETs. For 3.3-V MOSFETs, the best
linearity of 3.9% was achieved, when was 25%.
By applying BIGCAP to the loop filter of a differential PLL,
we reduced the gate area of the MOS capacitor for the loop
filter to only 35% of that of the conventional design without
degrading the performance of the PLL. BIGCAP is adequately
linear for the given PLL application, because the 2.9% capacitance variation depending on the bias voltage as shown in Figs. 4
and 5 is smaller than the typical 20% or more VCO gain variation across the full VCO range and the variation of the transfer
function of the PLL due to the nonlinearity of BIGCAP is negligible. BIGCAP is widely applicable to many other circuits suchas I/O buffers, switched-capacitor circuits, operational amplifiers, data converters, and mixers.

TAKAMIYA AND MIZUNO: A 6.7-fF

m BIAS-INDEPENDENT GATE CAPACITOR (BIGCAP) WITH DIGITAL CMOS PROCESSACKNOWLEDGMENT
The authors would like to thank Y. Hamada and T. Enomoto
for providing the chip layout, and M. Yamashina, N. Nishi, S.
Ohya, and M. Fukuma for their useful comments and advice
during the course of this work.
REFERENCES[1] R. Aparicio and A. Hajimiri, “Capacity limits and matching properties
of integrated capacitors,” IEEE J. Solid-State Circuits, vol. 37, no. 3, pp.
384–393, Mar. 2002.
[2] K. T. Christensen, “Design and characterization of vertical mesh capacitors in standard CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, 2001,
pp. 201–204.
[3] J. Kim, J. Plouchart, N. Zamdmer, M. Sherony, L. Lu, Y. Tan, M. Yoon,
K. A. Jenkins, M. Kumar, A. Ray, and L. Wagner, “3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated
RF circuits,” in Symp. VLSI Circuits Dig. Tech. Papers, 2003, pp. 29–32.
[4] H. Yoshizawa, Y. Huang, P. F. Ferguson Jr., and G. C. Temes, “MOSFETonly switched-capacitor circuits in digital CMOS technology,” IEEE J.
Solid-State Circuits, vol. 34, no. 3, pp. 734–747, Mar. 1999.
[5] T. Tille, J. Sauerbrey, and D. Schmitt-Landsiedel, “A 1.8-V MOSFETmodulator using substrate biased depletion-mode MOS capaconly
itors in series compensation,” IEEE J. Solid-State Circuits, vol. 36, no.
7, pp. 1041–1047, Jul. 2001.
[6] T. Tille, J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, “A 0.7-V
MOSFET-only switched-opamp
modulator in standard digital
CMOS technology,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp.
1662–1669, Dec. 2002.
[7] K. Imai et al., “A 0.13-m CMOS technology integrating high-speed
and low-power/high-density devices with two different well/channel
structures,” in IEEE Int. Electron Devices Meeting Tech. Dig., 1999,
pp. 667–670.
[8] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York:
Wiley, 1981, pp. 363–379.
[9] H. Samavati, A. Hajimiri, A. R. Shahani, G. N. Nasserbakht, and T. H.
Lee, “Fractal capacitors,” IEEE J. Solid-State Circuits, vol. 33, no. 12,
pp. 2035–2041, Dec. 1998.
[10] C. H. Chen et al., “A 90 nm CMOS MS/RF based foundry SOC technology comprising superb 185 GHz f RFMOS and versatile, high-Q
passive components for cost/performance optimization,” in IEEE Int.
Electron Devices Meeting Tech. Dig., 2003, pp. 39–42.
[11] M. Soyuer, J. F. Ewen, and H. L. Chuang, “A fully monolithic 1.25 GHz
CMOS frequency synthesizer,” in Symp. VLSI Circuits Dig. Tech. Papers, 1994, pp. 127–128.
[12] W. Lin and W. C. Black Jr., “A low jitter 1.25 GHz CMOS analog PLL
for clock recovery,” in Proc. IEEE Int. Symp. Circuits and Systems, 1998,
pp. 167–170.
[13] D. W. Boerstler, “A low-jitter PLL clock generator for microprocessors
with lock range of 340–612 MHz,” IEEE J. Solid-State Circuits, vol. 34,
no. 4, pp. 513–519, Apr. 1999.

61

61

725

[14] H. Djahanshahi and C. A. T. Salama, “Differential CMOS circuits for
622-MHz/933-MHz clock and data recovery applications,” IEEE J.
Solid-State Circuits, vol. 35, no. 6, pp. 847–855, Jun. 2000.
[15] Y. M. Greshishchev and P. Schvan, “SiGe clock and data recovery IC
with linear-type PLL for 10-Gb/s SONET application,” IEEE J. SolidState Circuits, vol. 35, no. 9, pp. 1353–1359, Sep. 2000.
[16] J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector,” IEEE J. Solid-State Circuits,
vol. 36, no. 5, pp. 761–768, May 2001.
[17] M. Mansuri and C.-K. K. Yang, “A low-power adaptive bandwidth PLL
and clock buffer with supply-noise compensation,” IEEE J. Solid-State
Circuits, vol. 38, no. 11, pp. 1804–1812, Nov. 2003.

Makoto Takamiya (S’98–M’00) received the B.S.,
M.S., and Ph.D. degrees in electronic engineeringfrom the University of Tokyo, Tokyo, Japan, in 1995,
1997, and 2000, respectively.
In 2000, he joined Silicon Systems ResearchLaboratories, NEC Corporation, Kanagawa, Japan,
where he has been engaged in the circuit design ofhigh speed digital LSIs. His research interests include power integrity issues, signal integrity issues,and clock generation and distribution for MPUs.
Dr. Takamiya received the Young ResearcherAward of 1999 International Conference on Solid State Devices and Materials.

Masayuki Mizuno (M’95) received the B.S., M.S.,
and Dr.Eng. degrees in electronic engineering from
Osaka University, Osaka, Japan, in 1991, 1993, and2000, respectively.
In 1993, he joined the System ULSI ResearchLaboratory, Microelectronics Research Laboratories,
NEC Corporation, Kanagawa, Japan, where he has
been engaged in the research and development of
low-power single-chip MPEG2 video encoder LSIs,
low-power PLLs, and high-speed clock distribution
networks. While on leave during 1999–2000, he
studied interconnection network for chip multiprocessors at Stanford University, Stanford, CA, as a Visiting Scholar. His research interests are low-power
techniques for high-speed CMOS LSIs, high-speed serial links, and high-speed
clocking. He is currently a Principal Researcher of the System Devices
Research Laboratories, NEC Corporation.
Dr. Mizuno is a member of the Institute of Electronics, Information, and Communication Engineers of Japan.