A 0.45-V Input On-Chip Gate Boosted (OGB) Buck Converter in 40-nm
CMOS with More Than 90% Efficiency in Load Range from 2μW to 50μW
Xin Zhang1, Po-Hung Chen1, Yoshikatsu Ryu2, Koichi Ishida1, Yasuyuki Okuma2, Kazunori Watanabe2,Takayasu Sakurai1, and Makoto Takamiya1
1
University of Tokyo, Tokyo, Japan, 2Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan
Abstract
A 0.45-V input, 0.4-V output on-chip gate boosted (OGB)
buck converter with clock gated digital PWM controller in
40-nm CMOS achieved the highest efficiency to date withthe output power less than 40μW. A linear delay trimming by
a logarithmic stress voltage (LSV) scheme to compensate forthe die-to-die delay variations of a delay line in the PWM
controller with good controllability is also proposed.
Introduction
Adaptive power supply voltage (VDD) control is importantfor near-threshold logic circuits to achieve an energy
efficient operation against PVT variations, because low VDD
circuits are very sensitive to the variations. In [1], a low
dropout regulator (LDO) is used for the adaptive VDD control.
The LDO is, however, not suitable for the adaptive VDD
control, because the efficiency is limited to less than
VOUT/VIN, where VOUT is an output voltage and VIN is an
input voltage. To improve the efficiency, a 0.45-V VIN, 0.4-V
VOUT buck converter with 2~50-μW output power (POUT)
range is developed in this paper. The efficiency of the buckconverter with such low VIN and POUT is, however, normallylow, because (1) the loss in power transistors increases due tolow VIN and (2) the controller power dominates the total
power due to low POUT. Fig. 1 shows a calculated
dependence of efficiency on quiescent power (= controllerpower). As the quiescent power increases, the efficiency
decreases. For example, to achieve more than 90% efficiency
at POUT of 2μW, the quiescent power should be less than
222nW. In order to achieve a high efficiency buck converter,
this paper proposes (1) a gate boost by fully integrated
switched-capacitor (SC) DC-DC converters to overdrive thepower transistors in buck converter, (2) a low power clockgated 0.45-V digital PWM controller to improve theefficiency at low POUT, and (3) a linear delay trimming by anovel logarithmic stress voltage (LSV) scheme tocompensate for the die-to-die delay variations of a delay linein the PWM controller with good controllability.
On-chip Gate Boosted (OGB) Buck Converter
Fig. 2 shows a block diagram of the proposed on-chip gate
boosted (OGB) buck converter. Without OGB, driving
voltages of the power transistors are low (=VIN), thus the lossof the power transistors increases and the efficiency
decreases. In order to reduce the on-resistance of the powertransistors, a fully integrated 2VIN (=double voltage) SC
DC-DC converter for the nMOS power transistor (MN) and aminus VIN SC DC-DC converter for the pMOS powertransistor (MP) are developed to boost the supply voltages forthe gate drivers. The PWM signal (CK_PWM) is boosted to“-VIN to VIN” and “0V to 2VIN”, for MP and MN, respectively.
Fig. 3 shows a circuit schematic of a digital PWM controller
and a clock gating controller. Instead of a conventional
analog feedback control, a delay-line based digital PWMcontroller is newly developed for 0.45-V operation. A newclock gating technique is applied to shift registers (SR) in thePWM controller for power saving. Specifically, when VOUT
is higher than the high reference voltage (VREF(H)) or lower
than the low reference voltage (VREF(L)), the clock signal(CK) is given to SR; when VOUT is between VREF(H) andVREF(L), CK divided by 16 is given to SR, thereby reducing
the controller power by 26%. Fig. 4 shows a schematic of afully integrated 2VIN SC DC-DC converter [2] employed inthe proposed OGB buck converter.

978-1-4673-0849-6/12/$31.00 ©2012 IEEE

Delay Line Trimming by LSV
In the digital PWM controller in Fig. 3, a delay-line
without feedback control is used to minimize the controller
power. Large die-to-die delay variations of the delay line at
low VIN, however, might fail the PWM operation. To
compensate for the die-to-die process variations, a delay
trimming by a charge injection is newly proposed, while thetrimming to reduce a minimum operating voltage of anoscillator is previously proposed in [3]. Fig. 5 shows aschematic of the trimmed delay line. During the stress for thecharge injection, VDD is set to 1.1V. By applying a highn-well voltage as a stress voltage (Vstress), the absolute valueof the threshold voltage of pMOS is raised to increase thedelay. Fig. 6 shows a conventional linear stress voltage
scheme and the proposed LSV scheme. Fig. 7 shows ameasured stress time dependence of the delay of the trimmed
delay lines. The conventional linear stress voltage scheme
exponentially increases the delay, which means a poor
controllability. In contrast, the proposed LSV linearlyincreases the delay, which means a good controllability. Fig.
8 shows a measured stress time dependence of the delay of
the trimmed delay line and the retention characteristics for 8dies. The target delay is set to five times of the initial delay
to show the controllability of proposed LSV scheme. The
linear delay trimming by LSV and the compensation of thedie-to-die delay variations are successfully demonstrated. No
significant retention degradation is observed.
Experimental Results
A die photo of the buck converter fabricated with a 40-nm
CMOS is shown in Fig. 9. Table I shows a performancesummary. The 140-nW quiescent power is less than thetarget 222nW in Fig. 1. Fig. 10 (a) shows measured
waveforms of load regulation. Overshoot of 10mV and 8mV,and ripple voltage of 5mV are observed. Fig. 10 (b) shows astartup transition. At the beginning, when VOUT is lower than
VREF(L), the SR is clocked by CK of 20kHz. When VOUT isbetween VREF(L) and VREF(H), the clock gating is activatedthus the SR is clocked by (20/16)kHz, thereby reducing thepower of the PWM controller. Fig. 11 shows the measured
dependence of the efficiency on POUT. By using the proposed
OGB, the efficiency is increased from 55% to 96% at POUT of15μW. On the other hand, at POUT of 270nW, the efficiency isincreased from 60% to 67% by the proposed clock gating ofSR. At POUT range from 2μW to 50μW, the proposed buckconverter achieves more than 90% efficiency (> ideal LDO
efficiency=0.4V/ 0.45V=89%) with a peak value of 97% at
7μW. Fig. 12 shows the comparison with the published
DC-DC converters [4-8]. The proposed buck converterachieved the highest efficiency to date with the output power
less than 40μW. Moreover, the lowest input voltage is alsoachieved.
Acknowledgment
This work was carried out as a part of Extremely Low
Power (ELP) project supported by METI and NEDO.
References[1] K. Hirairi, et al., ISSCC, 2012, to be presented.
[2] H. San, et al., Trans. IEEJ, vol. 120-C, pp. 1339-1345, 2000.
[3] P. Chen, et al., ISSCC, pp. 216-217, 2011.
[4] J. Kwong, et al., ISSCC, pp. 318-319, 2008.
[5] Y. Okuma, et al., CICC, pp. 323-326, 2010.
[6] Y. Ramadass, et al., ISSCC, pp. 64-65, 2007.
[7] S. R. Sridhara, et al., Symp VLSI Circuits, pp. 15-16, 2010.
[8] C. Hsieh, et al., Symp VLSI Circuits, pp. 242-243, 2011.

2012 Symposium on VLSI Circuits Digest of Technical Papers

194

W
1m80
P OU

μW=2T

60
40
2090%

W
0μ10μW
10Efficiency (%)

1000V

On-chip gate boost (OGB)

222nW for90% efficiency

0VIN10nW 100nW 1μW 10μW 100μW 1mW
Quiescent power (nW)VIN

Linear delay trimming by LSVT
Delay0CK(20kHz)CK_PWM

Digital PWM controller

Delay1

Delay2Level
shifter-VIN
SC DC-DC
2VIN
SC DC-DC

VIN

VIN=0.45V
MP
VOUT=0.4V
-VIN
2VIN

Level
shifter

MN

CK(20kHz)

Delay31

OUT_VREF

Digital PWM controller
VIN
110
Q00
Q10
Q2

VREF=0.4V

OUT_VREF(H)0

Clock gating controller

Q31

VREF(H)=VREF+ΔV

OUT_VREF(L)OUT_VREF

Bi-directional shift register (SR)VREF(L)=VREF-ΔV

CK_SR
OUT_VREF(H)OUT_VREF(L)

Sel

1 16

IOUT

LoadFig. 1. Calculated dependence of efficiency on quiescent power.
CK_PWM

2VIN
VIN
0V

VIN
0V-VIN

VIN

Fig. 2. Block diagram of proposed buck converter with on-chip gate boost anddigital PWM controller.

Clock gating controller

VIN
CK

CK
2.5pF

2.5pF
CK

CK

CK

Vn-well=Vstress

CK
VOUT=2VIN=0.9V

VIN=0.45V

VDD=1.1V

10pF

VIN

Out

10pF

CK(20MHz)

CK

66

20

Conventional linear
stress voltage
scheme13

Conventional linear
stress voltage
scheme1512111010

Proposed logarithmic
stress voltage (LSV) scheme
Vstress=1.67×log10N+9.5 (V)9804812 16 20
Stress time (s)Proposed
LSV scheme

502404812 16 20
Stress time (s)24Fig. 7. Measured delay vs. stress timeof conventional linear stress voltage
scheme and proposed LSV scheme.

Fig. 6. Conventional linear stress voltage
scheme and proposed logarithmic stressvoltage (LSV) scheme.

Fig. 5. Circuit schematic oftrimmed delay line with charge
injection.

Delays of 8 dies are trimmed to target value
50ms

55

IOUT

0.45V
VIN

5μA
10μA

44surho rs72 hours48 ouh24 surho s
8 urho surho33
22

Linear delay trimmingis achieved by LSV.

11

VOUT=0.4V8mV

812162024

Total stress time (s)104105500μs

106Time after stress (s)(a)

Fig. 8. Measured delay trimming by proposed LSV and retention characteristics for 8 dies.

(b)Fig. 10. Measured waveforms. (a) Load regulation. (b) Start up transition.

1050μm100450μm

With gate boost & clock
gating (proposed)
PWM controller

Powertransistors

On-chip
SC DC-DC100

VIN=0.45V
VOUT=0.4V

Fig. 9. Chip micrograph.
TABLE I Performance summaryTechnology40-nm CMOS

Input voltage

0.45V

Output voltage

0.34V~0.44V

Output power

270nW~165μW

Output ripple<5mV

Max. efficiency

97% at 7μW

Quiescent power
140nW
at IOUT=0Active area

0.043 mm2

978-1-4673-0849-6/12/$31.00 ©2012 IEEE

Efficiency (%)(%)
Efficiency

9080

With clock gating& w/o gate boost

6050[6]80[7]70100nW

With gate boost &w/o clock gating

Clockgating
of SR

1μW
11μW

10μW

100μW

Output power

On-chipgateboost

Reference
Type40100nW
0.1[5]

[4]

6050

70[8]

This work90
Efficiency (%)

40.45VVOUT

00

020/16kHz

VREF(H)
VREF
VREF(L)

5mV

10mV0V20kHzCK_ SR

52

Delay of trimmed delaylines (a. u.)

Fig. 4. Circuit schematic of 2VIN(=double voltage) switched-capacitor(SC) DC-DC converter.

14

Delay of trimmed delay lines(a. u.)

VIN

Stress voltage (Vstress) (V)

Fig. 3. Circuit schematic of digital PWM controller and clock gating controller.

10μW
100μW
10100
Output power
power

1mW
1000Fig. 11. Measured dependence of efficiency on output powerwith and without gate boost and clock gating of shift register.

[4]
ISSCC
2008

[5]
[6]
[7]
CICC ISSCC VLSI2010 2007 2010

SwitchedLDO Buckcapacitor

Buck[8]ThisVLSIwork
2011
Buck Buck

CMOS

65nm

65nm 65nm 130nm 250nm 40nm

Input voltage
(V)

1.2

0.5

1.2

1.8

1.2

0.45

Output voltage
(V)

0.5

0.45

0.5

0.575

1.00.4Fig. 12. Comparison with published low voltage
and low output power DC-DC converters.

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195