Fully Integrated Overcurrent Protection Method
During SiC MOSFET Conduction
Haifeng Zhang1, Dibo Zhang1, Katsuhiro Hata1, Keiji Wada2, Kan Akatsu3, Ichiro Omura4, and Makoto Takamiya1
1 The University of Tokyo, Tokyo, Japan
2 Tokyo Metropolitan University, Tokyo, Japan
3 Yokohama National University, Kanagawa, Japan
4 Kyusyu Institute of Technology, Fukuoka, Japan
Abstract—A gate driver IC with fully integrated overcurrent
protection functions developed for IGBTs is successfully applied
to overcurrent protection for SiC MOSFETs. In the gate driver IC,
while the SiC MOSFETs are ON, constant gate charge isperiodically discharged and charged, and when gate-to-source
voltage dropped by each discharge is less than the reference
voltage, it is detected as the overcurrent and the SiC MOSFETs
are immediately turned off to protect from the overcurrent.
Overcurrent protection can be achieved at low cost, since external
components such as high-voltage diodes are not required. While
the overcurrent detection threshold is constant and cannot bechanged for IGBTs, it is found for the first time in SiC MOSFETs
that the overcurrent detection threshold can be varied by changing
the gate charge to be discharged. In a single-pulse test of an
inductive load at 300 V for an SiC MOSFET with DC rating of 134
A and pulse rating of 240 A, the gate driver IC successfully
protected the overcurrent with the protection delay of 226 ns or
less, while the overcurrent detection threshold is variable in therange of 104 A to 306 A.
Keywords— overcurrent, protection, gate driver, IC, gate voltage,
SiC

I. INTRODUCTION
Overcurrent detection and protection of power devices areimportant technologies to realize reliable power electronicsystems. The target of this work is to develop an overcurrent
protection method for SiC MOSFETs used in large-current,
short-pulse current generator circuits with an inductive load [1]that (1) can be fully integrated into a gate driver IC without
external components such as high-voltage diodes for low cost,(2) can detect overcurrent while the SiC MOSFETs are ON, and(3) has a variable overcurrent detection threshold (ITH).
Table I shows a summary of conventional detection andprotection for overcurrent. Methods for detecting overcurrent bymeasuring drain current (ID) [2-5], and drain-to-source voltage(VDS) [3, 6] of SiC MOSFETs have been proposed. ID
measurement requires a current sensor, and VDS measurement fordesaturation detection requires a high-voltage diode, which areexpensive. All conventional overcurrent detection methods bygate-to-emitter voltage (VGE) measurement in IGBTs [7, 8, 10]
and gate-to-source voltage (VGS) measurement in SiC MOSFETs[9, 11] have the disadvantage that overcurrent during ON of
IGBTs/SiC MOSFETs cannot be detected, because VGE/VGS ismeasured during the turn-on transient. No conventional
overcurrent protection methods, however, satisfy all threetargets.

TABLE I.

COMPARISON TABLE OF DETECTION AND PROTECTIONFOR OVERCURRENT

Reference[2-5]

Method[3, 6][10]

V at
Current Desatu GE
Millermonitor ration
plateau

Measured
ID
VDS
value
Power device SiC
SiC
Measurement
NoNo
from gate
terminal
Overcurrent
Yes
Yes
detection
during ON
Fully
No
No
integrated
protection
Variablethreshold forYes
Yes
overcurrent
detection
Detection /22 [2] 250 [3]protection
100 [3] 400 [6]delay [ns]

[11]

[12]

This
work

Gate
charge

MGDC

MGDC

VGE

QG, VGS

VGE

VGS

IGBT

SiC

IGBT

SiC

Yes

Yes

Yes

Yes

No

No

Yes

Yes

No

No
(Only
detection)

Yes

Yes

Yes

No

No

Yes
by VDOS

500

369

810

< 226

Therefore, in this paper, an overcurrent protection method
for SiC MOSFETs that satisfies all three targets is proposed byapplying the gate driver IC [12] with a fully integrated
overcurrent protection function called “monitoring gate voltage
while periodically repeating discharging and charging of
constant gate charge (MGDC) [13]” developed for IGBTs to SiC
MOSFETs. When the gate driver IC [12] is applied to SiC
MOSFETs, a new phenomenon called “VGS drop due tooverheating of SiC (VDOS)” is found. Therefore, the variable
ITH using the phenomenon is achieved in this paper.
II. PROPOSED FULLY INTEGRATED OVERCURRENT PROTECTION
A. Gate Driver IC with Fully Integrated Overcurrent
Protection
Fig. 1 shows an operation principle of the gate driver IC [12]with a fully integrated overcurrent protection function bymeasuring gate-to-source voltage (OPV) while SiC MOSFETs
are ON. Two functions, a periodic constant gate charge (QC)
discharger and recharger, and an overcurrent protection by VGS,
are added to the gate driver IC. While the SiC MOSFETs are ON,
the periodic QC discharger and recharger periodically discharges
and recharges QC. When VGS dropped by each discharge is lessthan the reference voltage (VREF), it is detected as the overcurrent

ID

VG
R1 / R2 = 7
ClockedR1
comparator

Gate driverIN

Periodic QC
discharger& recharger

5V
D

Q

−

VGS

R2

Over-ID protection
by VGS

Attenuator& LPF

Constant gate charge (QC)

+

C1

Alarm

Reset

VREF DCO_out

ResetFig. 4. Circuit schematics of VGS detector.

3

1WP
IO

32WP
32IO

IO
nNMOS

32IO

1WN

32WN

ID
IG

Level shifter
Scan In
Scan CLK
IN
5V

VREF
Reset
VG

SIPO 24
10
OPV

6
PISOs

3

(Fig. 3)

OPV

18 V

VGS

VDS

Edge
detector

Pulse

outputs of the OPV circuits (Alarm, Internal_ONOFF, andPulse) are fed into the low-side and high-side parallel-in serialout shift registers (PISOs) in Fig. 2.

VGS
detector(Fig. 4)

DCO_out

Alarm

6-bit
nMOS
drivers

Fig. 5. Die photo of gate driver IC with OPV fabricated with 180-nm BCD
process.

Fig. 2. Circuit schematics of gate driver IC with OPV.

DCO
T1 [4:0],
T2 [4:0] 10
VREF
Reset
VG

6-bit
pMOS
drivers

2.5 mmSerial-in parallel-out shift register (SIPO)
Parallel-in serial-out shift register (PISO)

IN

PISOs

6
PISOs

SIPO

SIPO 24

2.0 mm

5V

nPMOS

PISOs

Gate driver (GD) IC withover-ID protection by VGS (OPV)

SIPO

Fig. 1. Operation principle of gate driver IC with fully integrated
overcurrent protection function by measuring VGS (OPV).

Internal_ONOFF

Digitally controlled oscillator (DCO)

Fig. 3. Circuit schematics of OPV circuits.

and the gate driver is forced to turn off to complete theovercurrent protection.
Fig. 2 shows a circuit schematics of the gate driver IC with
OPV [12]. All circuits are integrated on a single chip except for
the isolated power supplies. To achieve the two functions shownin blue in Fig. 1, an OPV circuit is added to our previously
developed 6-bit current-source type digital gate driver [14, 15]with variable gate current (IG) in 64 levels, where IG = nPMOS ×
40 mA and nPMOS is an integer from 0 to 63 at turn-on. At turnoff, |IG| = nNMOS × 41 mA and nNMOS is an integer from 0 to 63 at
turn-on.
Fig. 3 shows a circuit schematics of the OPV circuits [12].
The OPV circuits include a digitally controlled oscillator (DCO)
to determine charging and discharging time and a VGS detector
to detect the overcurrent by comparing VGS and VREF. The threeFig. 4 shows a circuit schematics of the VGS detector [12].
The VGS detector includes an attenuator with an attenuation ratioof one-eighth to prevent the input gate voltage (VG) fromdamaging the clocked comparator with overvoltage, and a low
pass filter (LPF) with a cutoff frequency of 57 MHz to remove
high-frequency ringing of VG. When the attenuated and low passfiltered VG drops below VREF, Alarm output changes from low tohigh, forcing the SiC MOSFET to turn off. Fig. 5 shows a die
photo of the gate driver IC [12] with OPV fabricated with 180nm BCD process. The die size is 2.0 mm by 2.5 mm.
B. Proposed Overcurrent Protection Using MGDC
Fig. 6 shows timing charts of the proposed overcurrent
protection using MGDC. Table II shows the summary of themeasured four parameters (t1, t2, I1, and |I2|) that can be digitallycontrolled by this IC to achieve MGDC [13]. The gate driver IC
has a total of 22 control bits including T1 [4:0], T2 [4:0], I1 [5:0],
and I2 [5:0]. All control bits are written in advance to the on-chip
memory (two serial-in parallel-out shift registers (SIPOs) in Fig.
2) by scan-in, eliminating the need for the high-speed digital
signal generator to determine t1 and t2.

t1

t2

Off

IN
DCO_out

t1

t2

t2

t1

20

t2

On

t1 [s]Internal_ONOFF

0
63

nNMOS
IG

0

0A

REF

0V
ITH

ID

ILEAK

0
0

VDOS

Fig. 7. Measured t1 vs. T1 [4:0].

QC

|I2|

4

VGS comparison timing

5

10

t2 [s]0V

Overcurrent protection

20

Measured2530

3.4 s2

1

3.4 s= 110 ns / step
31

Fig. 6. Timing charts of proposed overcurrent protection using MGDC.

00TABLE II.
MEASURED FOUR PARAMETERS DIGITALLYCONTROLLED BY IC TO ACHIEVE MGDC

Parameters Control bits
t1

15

T1 [4:0]

3

0A
300 V

VDS

17 s
= 535 ns / step31

I2 [5:0]

18 V

VGS V

10

5

I1 [5:0]

I1

17 s

15

Alarm
nPMOS63

MeasuredT1 [4:0]

Range

Step

0 s to 17 s

535 ns

3.0

T2 [4:0]

0 s to 3.4 s

110 nsI1

I1 [5:0]

0 A to 2.5 A

40 mA

2.0

|I2|

I2 [5:0]

0 A to 2.6 A

41 mA

I1 [A]t2

15

T2 [4:0]

20

25

30

Measured

2.5 A

1.5
1.0

2.5 A
= 40 mA / step
63

0.5

0
0

10

20

30

I1 [5:0]

40

50

60

Fig. 9. Measured I1 vs. I1 [5:0].

3.0

Measured

2.6 A

2.5
2.0

|I2| [A]In MGDC in Fig. 6, while the SiC MOSFETs are ON, QC (=|I2| × t2) is periodically discharged and recharged with the t1 + t2
cycle. nPMOS = I1 [5:0] and nNMOS = 0 in the t1 period, while nPMOS= 0 and nNMOS = I2 [5:0] in the t2 period. When VGS dropped byeach discharge is greater than VREF, it is judged normal, andwhen VGS dropped by each discharge is less than VREF, it isdetected as the overcurrent and the SiC MOSFETs are
immediately turned off to protect from the overcurrent. VREF
should be set lower than VGS after the first discharge and higher
than VGS when the overcurrent occurs. Unlike IGBTs, VDOS isfound for the first time to occur in MGDC of SiC MOSFETs.

10

Fig. 8. Measured t2 vs. T2 [4:0].

2.5

Figs. 7 to 10 show the measured t1 vs. T1 [4:0], t2 vs. T2 [4:0],
I1 vs. I1 [5:0], and |I2| vs. I2 [5:0], respectively. The charging time(t1) of MGDC in Fig. 6 is digitally controlled by 5-bit T1 [4:0] of
DCO from 0 s to 17 s in 535 ns steps as shown in Fig. 7. The
charging gate current (I1) during t1 in Fig. 6 is digitally controlledby 6-bit I1 [5:0] of the digital gate driver from 0 A to 2.5 A in 40
mA steps as shown in Fig. 9. Similarly, the discharging time (t2)of MGDC in Fig. 6 is digitally controlled by 5-bit T2 [4:0] of
DCO from 0 s to 3.4 s in 110 ns steps as shown in Fig. 8. The
discharging gate current (|I2|) during t2 in Fig. 6 is digitallycontrolled by 6-bit I2 [5:0] of the digital gate driver from 0 A to
2.6 A in 41 mA steps as shown in Fig. 10.

5

1.5
1.0

2.6 A
= 41 mA / step
63

0.5

0
0

10

20

Fig. 10. Measured |I2| vs. I2 [5:0].

30

I2 [5:0]

40

50

60

VDOS means the drop in VGS from 18V that occurs in the t1
period when ID exceeds ITH. The advantage of the proposed
method is that ITH is variable using VDOS, because the SiC
overheating changes by varying QC using T2 [4:0] and/or I2 [5:0].

Fig. 11 shows an equivalent circuit that illustrates theprinciple of VDOS during t1. RON is the on-resistance of the gate
driver, RG,INT is the internal gate resistance of the SiC MOSFET,
and RG,LEAK is the resistance of the gate dielectric of the SiC
MOSFETs due to IG,LEAK. Fig. 11 shows that RG,LEAK is afunction of TJ. As TJ increases, IG,LEAK increases and RG,LEAK
decreases, and thus VGS decreases due to resistance divider,which is the reasons for VDOS. ITH can be controlled by QC. For
example, increasing QC lowers ITH, because it increases the VGS
drop, VDS, heat generation, and TJ increase.
The physics of IG,LEAK in SiC MOSFETs is explained below.
Unlike silicon power devices, SiC MOSFETs are known to have
IG,LEAK during a short circuit [16-22]. This IG,LEAK was firstreported in 2015 in [16], and in [17] it was reported that IG,LEAK
flows during a short circuit in all five commercially available
SiC MOSFETs.
The following three stages of phenomena occur in SiC
MOSFETs during a short circuit as TJ increases.
• Stage 1: High power due to short-circuit current underhigh voltage (e.g. 300 V × 300 A = 90 kW) causes TJ of
SiC MOSFETs to increase in the order of microseconds.
For example, [20] shows that TJ rises from room
temperature to 800 °C in 2.7 s.
• Stage 2: When TJ reaches about 800 °C [20], thermally
excited electrons overcome the SiC-SiO2 interface
barrier and IG,LEAK begins to flow [18, 19, 21], as shownin the band diagram in Fig. 12 (a). This phenomenon iscalled Schottky emission [18, 19, 21]. The SiC
MOSFETs are not yet broken, because Schottky
emission is an electrothermal phenomenon [18, 21].
• Stage 3: When TJ reaches about 1100 °C [20], the SiC
MOSFETs are destroyed due to thermomechanicalreasons [21].
The proposed overcurrent protection method in this paper is atechnique to detect and protect SiC MOSFETs from overcurrent
in Stage 2, before they are destroyed.
Note that IG,LEAK due to Schottky emission in Stage 2 does
not occur in silicon power devices [18], because the barrierheight at the Si/SiO2 interface (3.2 eV) is higher than that at the
SiC/SiO2 interface (2.7 eV), as shown in the band diagram in Fig.

IG,LEAK
18 V

RG,INT

RG,LEAK

VGS
IG,LEAKVGS

RG,LEAKTJ

Fig. 11. Equivalent circuit that illustrates principle of VDOS during t1.
IG,LEAKNo IG,LEAK

Schottky emission
2.7 eV

3.2 eV

EC

EF

EC

EF

Poly-Si SiO2
(Gate)(a)

SiC

Poly-Si SiO2
(Gate)(b)

Si

Fig. 12. Band diagram of n-type MOSFET in strong inversion. (a) SiC
MOSFET. (b) Si MOSFET.
QC discharge

15

Measured
VDS = 300 V

ID [A]
20
50
80
100
`
150
200
250
300
350
400

Point C
10

Point BVGS [V]

C. Reasons for “VGS Drop due to Overheating of SiC(VDOS)”The reasons for VDOS is explained below. In Fig. 6, during
t2, the on-resistance of the SiC MOSFET increases, when VGS islowered by discharging QC. As a result, VDS increases and the
SiC MOSFET generates more heat, because the power
determined by VDS × ID is consumed. When the SiC MOSFET
junction temperature (TJ) exceeds a certain value, the gateleakage (IG,LEAK) of the SiC MOSFET begins to flow and VGS
drops during t1.

RON

Point A(Start)

VREF
5

Point D

NormalOvercurrent
0
−500

−400

−300

−200

−100

gate

charge0Gate charge (QG) [nC]Fig. 13.
Measured(BSM120D12P2C005).

VGS

vs.

of

SiC

module12, and thus TJ at which Schottky emission occurs is higher than
the thermal runaway temperature of silicon [18].
III. MEASURED RESULTS
A. Gate-Charge Curve to Understand MGDC
To quantitatively understand the principle of MGDC
operation in case of no VDOS, Fig. 13 shows the measured
gate-charge curve (VGS vs. gate charge (QG)) of the SiC module
used in this paper (BSM120D12P2C005, 1200 V rating) with a
DC rating of 134 A and a pulse rating of 240 A at VDS = 300 V.
Since MGDC repeats QC discharge and charge from the initialstate of SiC MOSFET turned on, unlike the typical gate-charge
curve, QG at VGS = 15V is defined as zero.

As an example, the operation of MGDC at QC = 240 nC is
described below. In case of ID = 20A, when QC is discharged,
the operating point moves from Point A with VGS = 15 V to
Point B with VGS = 8 V. In case of ID = 50A, when QC isdischarged, the operating point moves from Point A with VGS =15 V to Point C with VGS = 10 V. Furthermore, at ID = 350 A,
which exceeds the pulse rating of 240 A for this SiC MOSFET,
when QC is discharged, the operating point moves from Point A
with VGS = 15 V to Point D with VGS = 4 V.
Therefore, when the SiC MOSFETs operate in the normal
region, the Miller plateau voltage increases with increasing ID,
increasing VGS after QC discharge, in contrast, when the SiC
MOSFETs operate in the overcurrent region, the gate
capacitance decreases with increasing ID, decreasing VGS after
QC discharge. Since VGS in normal and overcurrent regions aredifferent, the overcurrent can be detected by comparing VGS and
VREF using a comparator.

SiC
module

300 V
GD IC

IG

VDS

VGS
ID

Fig. 14. Circuit schematic of single-pulse test with inductive load.

B. Overcurrent Protection with Variable ITH
Figs. 14 and 15 show a circuit schematic and a photo of themeasurement setup for a single-pulse test of an inductive load of
34 H at 300 V for the SiC module (BSM120D12P2C005),
respectively.

Gate driver IC
with OPV

Fig. 16 shows the conventional measured waveforms of theovercurrent exceeding 350 A. In the conventional desaturation
detection, the overcurrent is detected by the VDS increase in Fig.
16. In Fig. 16, the SiC MOSFET is turned off manually. VDOS
does not occur in Fig. 16, because VGS is constant at 18 V afterturn-on and no heating during t2 period of MGDC occurs.
Figs. 17 (a) to (f) show the measured waveforms of the
proposed overcurrent protection with variable ITH from 306 A to104 A by changing QC. t1 = 1.9 s, t2 = 0.52 s, and I1 = 1.6 A
are fixed, and QC (= |I2| × t2) is changed by varying only |I2| tochange ITH. In Figs. 17 (a) to (f), |I2| is varied from 0.53 A to 0.74
A by varying I2 [5:0] by one from 13 to 18, respectively, and QC
is varied from 276 nC to 385 nC, where |I2| = I2 [5:0] × 41 mA.
Increasing QC accelerates SiC MOSFET heating and increases
VDOS, which lowers ITH. In Fig. 17, “(1) QC discharge in t2, (2)comparison of VGS and VREF at the end of t2, and (3) recharge to
VGS = 18 V in t1”, is repeated in t1 + t2 cycles. When VGS < VREF,
overcurrent is detected, Alarm changes from low to high,Internal_ONOFF changes from high to low, and the gate driver
is forced to turn off to complete the overcurrent protection. The
overcurrent protection delay in Fig. 17 (a) is 207 ns. By changing
QC from 276 nC to 385 nC, ITH is reduced from 306 A to 104 A,
because increasing |I2| increases VDS during t2, which increases
VDOS due to the increased overheating of SiC. In contrast, in
IGBTs, the QC dependence of ITH is very small and ITH is almost
constant, since VDOS does not occur [13].
Figs. 18 (a) to (d) show the QC dependence of ITH, VREF, theovercurrent protection delay, and the relative loss increase due
to MGDC (RLI) extracted from Fig. 17, respectively. The
definition of RLI is as follows

(
RLI
=

tEND

tSTART

I DVDS dt)(With MGDCtENDtSTART(− 

I DVDS dttENDtSTART)

I DVDS dt

Without MGDC)

Without MGDC

100

SiC module

Fig. 15. Photo of measurement setup.

VGS: 3 V/div

0

10 μs/div
VDS: 100 V/div

Enlarged vertical axis
10 μs/div0

VDS: 4 V/div

Fig. 16. Conventional measured waveforms.

where tSTART and tEND indicate the start and end time of thesingle-pulse test, respectively.
As shown in Fig. 18 (a), increasing QC from 276 nC to 385
nC enables ITH to be varied from 306 A to 104 A. Since the SiC
MOSFET used in this paper has a DC rating of 134 A and a pulse
rating of 240 A, the users of the gate driver can freely set ITH ina wide range from 134 A or lower to 240 A or higher, which isa major advantage of this proposal.
As shown in Fig. 18 (b), the proposed overcurrent protection
does not work unless VREF is manually adjusted to the

IN

IN

10 μs/div

5 V/div

5 V/div

DCO_out

DCO_out

Alarm

Alarm

Internal_ONOFF

10 μs/div

Internal_ONOFF

VDOS

VDOS
VDS

VGS

VGS

ID

0
EnlargedIN

VDS

Enlarged
200 ns/div

IN

200 ns/div

DCO_out

DCO_out

Alarm

Alarm

Internal_ONOFF

Internal_ONOFF

ID: 100 A/div

VGS comparison
timing207 ns

VDS: 100 V/div
0

306 A

VGS: 3 V/div

IN

VGS: 3 V/div

VGS comparison
timing 215 ns

ID: 100 A/div
VDS: 100 V/div0

t1
t2
Overcurrent protection(a) QC = 276 nC (I2 [5:0] = 13 and |I2| = 0.53 A)

DCO_out

268 A

t2
Overcurrent protection(b) QC = 302 nC (I2 [5:0] = 14 and |I2| = 0.58 A)IN

5 V/div

ID

0

5 V/div

DCO_out

Alarm

10 μs/div

Internal_ONOFF

10 μs/div

AlarmInternal_ONOFF

VDOS

VDOS
VDS

VGS

VGS

ID

0

Enlarged
200 ns/div

IN

VDS

EnlargedIN

200 ns/div

DCO_out

DCO_out

Alarm

Alarm

Internal_ONOFF

VGS: 3 V/div
ID: 100 A/div
VDS: 100 V/div
0

ID

0

Internal_ONOFF

VGS comparison
timing226 ns

VGS: 3 V/div
VDS: 100 V/div
ID: 100 A/div

223 A

t1
t2
Overcurrent protection(c) QC = 322 nC (I2 [5:0] = 15 and |I2| = 0.62 A)

0

VGS comparison
timing118 ns173 A

t1
t2 Overcurrent protection(d) QC = 343 nC (I2 [5:0] = 16 and |I2| = 0.66 A)

Fig. 17 (a) to (d). Measured waveforms of proposed overcurrent protection with variable ITH from 306 A to 104 A by changing QC. (a) QC = 276 nC (I2 [5:0] =13 and |I2| = 0.53 A). (b) QC = 302 nC (I2 [5:0] = 14 and |I2| = 0.58 A). (c) QC = 322 nC (I2 [5:0] = 15 and |I2| = 0.62 A). (d) QC = 343 nC (I2 [5:0] = 16 and |I2| =0.66 A).

IN

IN

5 V/div

DCO_out

5 V/div

DCO_out

10 μs/div

10 μs/div

Alarm

Alarm
Internal_ONOFF

Internal_ONOFF

VDOS
VGS

VDOS
VGS

VDS

ID

0

ID

0

Enlarged
200 ns/div

EnlargedININ

200 ns/div

DCO_out

DCO_out

Alarm

Alarm

Internal_ONOFF

Internal_ONOFF

VGS: 3 V/div

VGS comparison
timing

VDS: 100 V/div

VGS: 3 V/div
VDS: 100 V/div

123 ns

ID: 100 A/div

VDS

VGS comparison
timing152 ns

ID: 100 A/div
138 A

0

0

104 A

t2
t1
Overcurrent protection(f) QC = 385 nC (I2 [5:0] = 18 and |I2| = 0.74 A)

t2 Overcurrent protectiont1(e) QC = 364 nC (I2 [5:0] = 17 and |I2| = 0.70 A)

300

240 A (Pulse rating)

250
200

150
100
50

134 A (DC rating)

(a)

0
250

300

Protection delay [ns]250

QC [nC]

350

400

200
150
100
50

(c)
0
250

300

QC [nC]

350

400

Relative loss increase (RLI) [%]Overcurrent detection
threshold (ITH) [A]350

Reference voltage (VREF) [V]

Fig. 17 (e) to (f). Measured waveforms of proposed overcurrent protection with variable ITH from 306 A to 104 A by changing QC. (e) QC = 364 nC (I2 [5:0] = 17
and |I2| = 0.70 A). (f) QC = 385 nC (I2 [5:0] = 18 and |I2| = 0.74 A).

1.0

0.5

0
250

(b)
300

150

QC [nC]

350

400

350

400

100

50

(d)

0
250

300

QC [nC]

Fig. 18. QC dependence extracted from Fig. 17. (a) ITH. (b) VREF. (c) Overcurrent protection delay. (d) Relative loss increase due to MGDC (RLI).

appropriate value depending on QC. From the viewpoint ofpracticality, VREF should be fixed or automatically adjusted, thus
the method of setting VREF is a future challenge in this proposal.
As shown in Fig. 18 (c), depending on QC, the overcurrent
protection delay varies in the range of 118 ns to 226 ns, because
the difference between VGS and VREF at the VGS comparison
timing (specifically the rise edge of DCO_out) in Fig. 6 is notconstant, and the comparator delay varies.
As shown in Fig. 18 (d), increasing QC from 276 nC to 385
nC increases RLI from 22% to 146%. Increasing QC increases
RLI, which is also true for IGBTs [13]. It is inevitable that the
QC discharge will increase RLI, because the proposed
overcurrent protection method detects the overcurrent bymonitoring the change in VGS caused by the QC discharge.
Reducing RLI by optimizing the MGDC parameters is a futurechallenge in this proposal. For MGDC in IGBTs, RLI has beensuccessfully reduced to 0.8% by parameter optimization [13].
Table I shows a comparison table of detection and protection
for overcurrent. This paper is the first work achieving the fully
integrated overcurrent protection method for SiC MOSFETs
while the SiC MOSFETs are ON with variable ITH.
IV. CONCLUSIONSThe overcurrent protection method with variable ITH andfully integrated in the gate driver IC is proposed, which candetect overcurrent while SiC MOSFETs are ON. In theovercurrent protection measurements of the SiC MOSFET with
the DC rating of 134 A and the pulse rating of 240 A, bychanging QC from 276 nC to 385 nC, ITH is reduced from 306 A
to 104 A, the overcurrent protection delay varies in the range of
118 ns to 226 ns, and RLI increases from 22% to 146%. The
variable ITH is a major advantage of this proposal.
ACKNOWLEDGMENT
This work was partly supported by JST-Mirai Program,Grant Number JPMJMI20E1, Japan.
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