Always-Dual-Path Hybrid DC-DC Converter
Achieving High Efficiency at Around 2:1 StepDown Ratio
Katsuhiro Hata1, Yang Jiang1, 2, Man-Kay Law2, and Makoto Takamiya1
1The University of Tokyo, Tokyo, Japan
2
University of Macau, Macau, China
E-mail: khata@iis.u-tokyo.ac.jp
Abstract— An always-dual-path hybrid (ADPH) DC-DC
converter using one inductor and two flying capacitors with thestep-down ratio from 3:1 to 1:1 is proposed to achieve highefficiency at the commonly used 2:1 step-down ratio by reducing
the inductor current. The proposed ADPH converter is designed
for a 24 V-to-13 V bus converter for truck auxiliary equipment.
In the measurement, the peak efficiency of the proposed 24 Vto-13 V converter is 97.4 % at 146 W, and the inductor
conduction loss is reduced by 67.2 % by reducing the inductor
DC current by 42.7 %.

VIN

Keywords— DC-DC converter, Step-down converter, Hybrid
converter, Always-dual-path, Equivalent series resistance (ESR)

Fig. 1. Proposed always-dual-path hybrid (ADPH) converter.

L
S1,Φ1

IL

IOUT

S4,Φ2

+ C
FLY1
VC1

+ CFLY2

VC2

S3,Φ1

+
S2,Φ2

+

S5,Φ1 COUT

R

+

VOUT

S6,Φ2

Figs. 2 (a) and (b), the converter has two circuit states. In bothstates, the output current is always divided into a dual path.

I. INTRODUCTION
Hybrid step-down DC-DC converters [1-11] combining abuck converter and a switched capacitor DC-DC converter
could overcome the trade-off between the efficiency and theform factor of the commonly used buck converter. In addition,[12-15] reported unique hybrid step-down DC-DC converters,
where an inductor is indirectly connected to the output and theoutput current is divided into a dual-path (inductor andcapacitor path). Hence, the converters [12-15] can reduce theconduction loss due to the ESR of the inductor. This is quite
beneficial when the inductor loss dominates at heavy loadconditions. The converters [12-15], however, cannot be usedin the applications requiring around 2:1 step-down ratio,
because the step-down ratio with two circuit states is limited
to either more than half or less than half [12-15]. Meanwhile,the conventional 3-level buck converters require different
control schemes to operate across a half step-down ratio [16,17], which complicates the controller. In addition, the inductor
current in a 3-level converter equals to the output current,
which results in a high DCR loss in heavy load conditions.

First, the voltages VC1, 2 in the flying capacitors CFLY1, 2 are
obtained from the steady-state analysis of the proposed ADPH
converter. Assuming that the output voltage VOUT is well
regulated and its ripple is small enough, the flying capacitor
voltages VC1 and VC2 described as follows:

VC1 = VIN − VC2 − VOUT
= VIN − 2VOUT
VC2 = VOUT .

(1)
(2)

where, VIN represents the input voltage and its value isassumed to remain unchanged in a short period of time.
Next, the voltage conversion ratio M of the proposed
ADPH converter is derived from the inductor voltage VL ineach circuit state. By considering voltage-second balance in L,
the voltage conversion ratio M can be obtained as follows:

0 = VL= (VIN − VOUT ) DTSW + (VC1 − VOUT )(1 − D ) TSW

To solve the problems, an always-dual-path hybrid(ADPH) DC-DC converter using one inductor and two flying
capacitors with only two circuit states and the step-down ratio
from 3:1 to 1:1 is proposed for the first time. The proposed
ADPH converter can dramatically reduce inductor conduction
loss and achieve high efficiency, especially at around 2:1 stepdown ratio. In this paper, operation principle and basic
characteristic of the proposed ADPH converter are describedanalytically. Also, the proposed ADPH converter is designed
for a 24 V-to-13 V bus converter for truck auxiliary equipment
and is measured using a prototype.

= (VIN − VOUT ) DTSW − (VIN − 3VOUT )(1 − D ) TSW


VOUT
1
=
VIN
3 − 2DV1
M = OUT =VIN
3 − 2D
3M − 1
D=
2M

(3)

(4)
(5)

II. PROPOSED ALWAYS-DUAL-PATH HYBRID CONVERTER

where, <VL>, D, and TSW are the average of inductor voltage,
the duty cycle, and the switching period, respectively.

A. Circuit operation and voltage conversion ratio
Fig. 1 shows the proposed ADPH converter topology
using one inductor and two flying capacitors. As shown in

Fig. 3 illustrates M as a function of D in the proposed
ADPH converter in contrast with the conventional buckconverter. The step-down operation range of the proposed
ADPH converter is from 3:1 to 1:1. In this study, the design

978-1-7281-8949-9/21/$31.00 ©2021 IEEE

1302

VIN

+
+ VC1

L

IOUT

Voltage conversion ratio M

IL

IC1 Dual-Path
+

IC2 C

+

OUT

CFLY1 VC2

R

+

VOUT

CFLY2
(a) State 1

IL

+ IC1

VIN

IOUT

Dual-Path

IC2

+

COUT

+ VC1

+

CFLY1 VC2

R

Fig. 3.

+VOUT

Inductor current ratio KDC

L

CFLY2
(b) State 2
Fig. 2.

Two circuit states in the proposed ADPH converter.

target is set to 0.4 < M < 0.6, because the target application isa 24 V-to-13 V bus converter for truck auxiliary equipment
and the input voltage is assumed to change from 22 V to 32 V
depending on the battery voltage.

Inductor current ripple ratio

(6)
(7)

By combining (6) and (7), the relationship between IL and IOUT
in the proposed ADPH converter can be expressed as follows:

I OUT = ( 3 − 2 D ) I L
 IL =(8)

1
I OUT = MI OUT
3 − 2D

I L,DC,ADPH = MI OUT
I L,DC,Buck = I OUT .

I L,DC,Buck= M.

Designtarget
0

0.2

0.4
0.6
Duty cycle D

0.8

1

Voltage conversion ratio M vs. duty cycle D.

10.8
Eq. (11)

0.6
0.4

Designtarget0.2

0
0.4 0.5 0.6 0.7 0.8 0.9
Voltage conversion ratio M

1

1.2
1
Eq. (14)

0.8

0.6
0.4

Designtarget0.2

0
0.3

0.4 0.5 0.6 0.7 0.8 0.9
Voltage conversion ratio M

1

C. Inductor current ripple
Additionally, in order to compare the inductor conduction
loss of the proposed ADPH converter and the conventional
buck converter, the inductor current ripple is also analyzed.
From the inductor voltage VL in the circuit state 1, whichis shown in Fig. 2(a), the inductor current ripple of the
proposed ADPH converter ∆IL,ADPH is obtained as follows:

(9)
(10)

Consequently, the inductor DC current of the proposed ADPH
converter IL,DCADPH can be reduced compared with that of thebuck converter IL,buck as follows:

I L,DC,ADPH

Eq. (4)

Fig. 5. Inductor current ripple ratio Kripple vs. voltage conversion ratio M.

As a result, the inductor DC currents of the proposed converter
and the conventional converter can be summarized as follows:

K DC =

Proposed

Fig. 4. Inductor DC current ratio KDC vs. voltage conversion ratio M.

IL and IOUT are defined as the periodic average current
flowing to the output and through the inductor, and from thecharge balance in CFLY1 and CFLY2 at periodic steady state, theoutput current IOUT and the capacitor currents IC1 and IC2 aredescribed as follows:

I C1 = I C2 = (1 − D ) I L .

Buck

0.3

B. Inductor DC current
To show that the proposed ADPH converter can reduce theinductor current IL compared to the conventional buckconverter, the relationship between IL and the output current
IOUT in the proposed ADPH converter is analyzed.

I OUT = ( DI L + I C1 ) + (1 − D ) I L + I C2 

1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0

I L,ADPH ==(11)

DTSW (VIN − VOUT )L
2 D (1 − D )VOUT
LfSW( 3M − 1)(1 − M ) .
V
= OUT
LfSW
2M 2

The Inductor DC current ratio KDC is indicated in Fig. 4.

1303

(12)

where, fSW is the switching frequency. Similarly, the inductor
current ripple of the conventional buck converter ∆IL,Buck isalso described as follows:

Loss reduction ratio

VOUT(1 − M ) .
LfSWI L,Buck =

6

(13)

Therefore, the inductor current ripple ratio Kripple is expressedby the following equation and is shown in Fig. 5.

K ripple =I L,ADPH
I L,Buck=

3M − 1
2M 2(14)

Designtarget543
2

Eq. (20)

0

i 2
+ L
12

(16)

I

=I

2
L,DC

where, RL,DC is the parasitic DC resistance of the inductor.
If the inductor current ripple ∆IL is sufficiently small withrespect to the inductor DC current IL,DC, the second term in(16) can be ignored. In addition, as shown in Fig. 5, theinductor current ripple ratio between the proposed ADPH
converter and the conventional buck converter is around 1, so
the conduction loss caused by ∆IL is not considered in thisstudy. As a result, the inductor conduction loss PL,DC issimplified as follows:
2
PL,DC = RL,DC I L,DC.

IS3 = I C1,1
I S4 = I C1, 2
IS5 = I C1,1
I S6 = I C1, 2

2
2
PL,DC,Buck = RL,DC I L,DC,Buck= RL,DC I OUT.

(19)

K L,DC =PL,DC,Buck= M 2.

(25)
(26)

1− D
IL
D
I C1, 2 = I C2, 2 = I L .

(27)
(28)

From these results and the operating conditions of each circuit
state, the switch conduction loss PRon is derived as follows:22+ (1 − D ) ( RS2 I S2
+ RS4 IS4
+ RS6 IS62 )21
(1 − D ) R + R
 RS1 +
 2
( S3 S5 )
= D
 IL
D

+ (1 − D )( RS2 + RS4 + RS6 ) Assuming that the inductor current ripple is small enough,the current flowing through each switch is obtained as follows:(29)

For design simplicity, assuming that the same device isused for all power switches employ, i.e. RSW = RS1 = RS2 = RS3= RS4 = RS5 = RS6, the switch conduction loss of the proposed
ADPH converter PRon,ADPH can be described as follows:3
PRon,ADPH =  − 1 − D  RSW I L2
D

−3M 3 + 8M 2 − M
2=RSW I OUT.
6M − 2(20)

B. Switch conduction loss
While the proposed ADPH converter can reduce theinductor DC current, the number of power switches isincreased, so it is necessary to analyze the switch conduction
loss. Assuming that the on-state resistance of the power switch
does not change significantly, the switch conduction loss canbe calculated from the current flowing through each switch.

IS1 = I L + I C1,1
I S2 = I C1, 2

(24)

2
2
PRon = D ( RS1 I S1
+ RS3 IS3
+ RS5 IS52 )Therefore, the proposed ADPH converter can reduce theinductor conduction loss PL,DC in proportion to the square of
the voltage conversion ratio M compared to the conventional
buck converter, and this reduction ratio KL,DC can be describedas follows:

PL,DC,ADPH(23)

I C1,1 = I C2,1 =From (9) and (10), the inductor conduction losses of the
proposed ADPH converter PL,DC,ADPH and the conventional
buck converter PL,DC,Buck are obtained as follows:(18)

1

where, IC,Φ1 and IC,Φ2 are the flying capacitor currents of eachcircuit state and they are described as follows:

(17)

2
2
PL,DC,ADPH = RL,DC I L,DC,ADPH= M 2 RL,DC I OUT

0.4 0.5 0.6 0.7 0.8 0.9
Voltage conversion ratio M

Fig. 6.
Loss reduction ratios KL,DC, KRon, KSW vs. voltage
conversionratio M.

A. Inductor conduction loss
From the inductor DC current and ripple analyses, theinductor conduction loss PL,RMS can be calculated as follows:

2
L,RMS

KSW
KSW

1

III. LOSS ANALYSIS

(15)

KRon
KRon

Eq. (32)

0.3

2
PL,RMS = RL,DC I L,RMS

KL,DC
KL,DC

Eq. (43)(30)

Similarly, the switch conduction loss of the conventional buckconverter PRon,Buck is obtained as follows:222PRon,Buck = DRSW I OUT+ (1 − D ) RSW I OUT= RSW I OUT.

(31)As a result, the switch conduction loss ratio between the
proposed ADPH and conventional buck converters KRon canbe derived as follows:

(21)
(22)

1304

K Ron =

PRon,ADPH
PRon,Buck=−3M 3 + 8M 2 − M.
6M − 2(32)

Inductor conduction loss [W]

C. Switching loss
Since an increase in the number of power switches also
leads to an increase in switching loss, this study conducts a
simple analysis to confirm this tendency.
First, the sustained voltage of each switch is consideredassuming a small ripple of each capacitor voltage. Since eachcapacitor voltage is given by (1) and (2), the sustained voltage
for the power switches during their turned-off state is obtained
as follows:

VS1 = VS2 = 2VOUT
VS3 = VS4 = VS5 = VS6 = VOUT .

(33)
(34)

Switch conduction loss [W]

(35)
(36)
(37)
(38)

Buck
Proposed1

0.5
Eq. (30)
Eq. (31)0510Output current IOUT

15(b) Switch conduction loss

1.5
Switching loss [W]Buck
Proposed1

Eq. (41)0.5
Eq. (42)0(41)From these analyses, the switching loss ratio between the
proposed ADPH and conventional buck converters KSW canbe obtained as follows:

PSW,Buck

15

0

Although the lower switch of the conventional buck converter
achieves soft switching in a synchronous rectification, its
switching loss is described as hard switching because the deadtime period is not considered in this study.

14M 3 − 2 M 2.
3M − 15
10Output current IOUT [A]

1.5

(40)

(43)

Fig. 6 shows the tendency of the loss reduction ratios KL,DC,
KRon, KSW in the operating range of the voltage conversion
ratio M. Although the proposed ADPH converter can

510Output current IOUT [A]15(c) Switching loss
Fig. 7.
Loss comparison between proposed ADPH converter andconventional buck converter under conditions of VIN = 24 V, VOUT = 13
V, M = 13/24, RL,DC = 6.8 mΩ, RSW = 2.2 mΩ, fSW = 100 kHz, and(tON + tOFF) = 6 ns.

1
1
PSW,Buck = fSWVIN I OUT ( tON + tOFF ) + fSWVIN I OUT ( tON + tOFF )2
2(42)= fSWVIN I OUT ( tON + tOFF )=Eq. (18)00Similarly, the switching loss of the conventional buckconverter PSW,Buck is calculated as follows:

PSW,ADPH

Eq. (19)0.5(39)From these results, the switching loss of the proposed
ADPH converter PSW,ADPH can be obtained as follows:

KSW =Proposed

1(a) Inductor conduction loss

where, tON and tOFF are the turn-on time and turn-off time,
respectively. Here, since a dead time is not considered as abasic analysis, all switching losses are calculated as hardswitching. If soft switching can be achieved, the switchingloss can be reduced, but its implementation is a future study.

14M − 2
PSW,ADPH =fSWVOUT I L ( tON + tOFF )3M − 1
14 M 3 − 2 M 2=fSWVIN I OUT ( tON + tOFF ) .
3M − 1Buck

0

Since the current flowing through each power switch is
calculated from (21) – (28) with small ripple assumption, eachswitching loss can be derived as follows:1
1
PSW1 = fSWVS1I S1 ( tON + tOFF ) = fSWVOUT I L ( tON + tOFF )2
D
1
PSW2 = fSWVS2 I S2 ( tON + tOFF ) = fSWVOUT I L ( tON + tOFF )2
1
1− D
PSW3 = fSWVS3 I S3 ( tON + tOFF ) =fSWVOUT I L ( tON + tOFF )2
2D1
1
PSW4 = fSWVS4 I S4 ( tON + tOFF ) = fSWVOUT I L ( tON + tOFF )
2
2
1
1− D
PSW5 = fSWVS5 I S5 ( tON + tOFF ) =fSWVOUT I L ( tON + tOFF )2
2D1
1
PSW6 = fSWVS6 IS6 ( tON + tOFF ) = fSWVOUT I L ( tON + tOFF ) .
2
2

1.5

drastically reduce the inductor conduction loss by reducing theinductor DC current, the switch conduction loss and switchingloss significantly increase in M < 0.4, and the superiority overthe conventional buck converter cannot be maintained in thisrange. Additionally, in 0.6 < M, the conduction losses havegood characteristics, but the increase in the switching loss
cannot be ignored. Therefore, the appropriate design target ofthe proposed ADPH converter is 0.4 < M < 0.6.
D. Case study
In order to compare not only the loss reduction ratios but
also the magnitude of losses, the proposed ADPH converter isdesigned and each loss is calculated. Because the target
application is a 24 V-to-13 V bus converter for truck auxiliary
equipment, the voltage conversion ratio was set to M = 13/24

1305

Loss reduction ratio K

3

COUT

Design target

L

CIN

2

S1
1

CFLY1
S2

Eq. (44)

S4
S3

CFLY2

S5

S6

0
0

5
10
Output current IOUT [A]15

Fig. 9. Prototype of the proposed ADPH converter.

Fig. 8. Loss reduction ratio K under conditions of VIN = 24 V, VOUT =13 V, M = 13/24, RL,DC = 6.8 mΩ, RSW = 2.2 mΩ, fSW = 100 kHz, and(tON + tOFF) = 6 ns.

TABLE I.

and the rated voltage of each switch was selected as 40 V or
higher. Other selected components are listed in TABLE I.
Fig. 7 shows the loss comparison between the proposed
ADPH converter and the conventional buck converter underconditions of VIN = 24 V, VOUT = 13 V, M = 13/24, RL,DC = 6.8
mΩ, RSW = 2.2 mΩ, fSW = 100 kHz, and (tON + tOFF) = 6 ns. In
the range where the output current is small, the switch loss isdominant over the inductor conduction loss, but the inductor
conduction loss increases significantly as the output current
increases, so the proposed ADPH converter is superior to theconventional buck converter.

PL,DC,ADPH + PRon,ADPH + PSW,ADPH
PL,DC,Buck + PRon,Buck + PSW,Buck

.

(44)

Value and Design Selection

Input voltage VIN

22 – 32 V (24 Vnominal)

Output voltage VOUT

13 V

Output current IOUT

15 Amax

Output power POUT

200 Wmax

Switching frequency

100 kHz

Input capacitor CIN
Flying capacitors CFLY1, 2
Output capacitor CO
Inductor L

40 V, RDS(on),max: 2.2 mΩ,BSC022N04LS6, Infineon
80 μF (10 μF × 8), X7S,
GCM32EC71H106KA03, Murata
264 μF (22 μF × 12), X7R,
GRM32ER71E226KE15, Murata
264 μF (22 μF × 12), X7R,
GRM32ER71E226KE15, Murata
10 μH, DCR: 6.8 mΩ,
XAL1510-103, CoilcraftB.]][ Measurement results

With the design parameters listed in TABLE I, the loss
reduction ratio K is calculated and depicted in Fig. 8. As aresult, the proposed ADPH converter offers lower loss thanthe conventional buck converter when the output current islarger than 5 A.
IV.

Parameters

Power MOSFETs S1–6

To consider the loss reduction ratio corresponding tochanges in loss distribution, the loss reduction rate K including
the inductor conduction loss, the switch conduction loss, andthe switching loss at the same time is calculated as follows:K=

CIRCUIT COMPONENTS AND PARAMETERS.

EXPERIMENTAL VERIFICATION

A. Experimental setup
In order to measure the efficiency of the proposed ADPH
converter and compare it with the conventional buck converter,
the prototype converter was implemented on the 116.8 mm ×
61 mm 2-layer PCB as shown in Fig. 9.
The proposed ADPH converter was operated based on thetwo circuit state shown in Fig. 2. On the other hand, theconventional buck converter was composed of S1, S2, L, CIN,
and COUT in Fig. 9. In the buck converter operation, S3-6 and
CFLY1,2 are removed, and the source of S1 and the drain of S2
are connected with a jumper resistor. The conventional buckconverter was operated in a synchronous rectification mode.
The efficiency was calculated from the input power andoutput power, and each power was measured using a power
analyzer (PW3390, HIOKI). The inductor DC current wasmeasured by an oscilloscope (MDO34 3-BW-200, Tektronix)
with an AC/DC current probe (TPC0030A, Tektronix).

Fig. 10 shows the measured efficiency of the proposed
ADPH and conventional buck converters under conditions of
VIN = 24 V, VOUT = 13 V, M = 13/24, and fSW = 100 kHz. The
peak efficiency of both converters is 97.4 %, but theconventional buck converter achieved this in the range of IOUT
= 7 – 8 A and the proposed ADPH converter was achieved in
the range of IOUT = 7 – 11 A. At IOUT = 15 A, the efficiency is
97.0 % and 96.7 % in the proposed and the conventional
converters, respectively, increasing the improvement inefficiency to 0.3 %. Under these conditions, it is expected thatthe superiority of the proposed ADPH converter will be
confirmed in the range where the output current is even larger,
so future measurements will be carried out as a future work.
The measured inductor DC current IL is indicated in Fig.
11. In the conventional buck converter, IL has the same value
as IOUT, but in the proposed ADPH converter, IL can be
drastically reduced from IOUT. As a result, the inductor
conduction loss can be significantly suppressed as shown in
Fig. 12. This result helps to cool the coil and suggests that it isadvantageous when using an inductor with a large DCR.
V. CONCLUSIONSAn always-dual-path hybrid (ADPH) DC-DC converter is
proposed to achieve high efficiency at the most commonlyused 2:1 step-down ratio by reducing the inductor current. In
the measurement, the peak efficiency of the proposed 24 V-

1306

97.4 %

99

REFERENCES

97.0 %[1]

Efficiency [%]

97

95
93
Buck
Proposed

91
89
0

5
10
Output current IO [A]15

Inductor current IL [A]

Fig. 10. Measured efficiency comparison between proposed ADPH
converter and conventional buck converter.

15
Buck
Proposed10- 42.7 %- 42.7 %- 42.6 %

5

0
0

5
10
Output current IO [A]15

Inductor conduction loss [W]Fig. 11. Measured inductor DC current comparison between proposed
ADPH converter and conventional buck converter.

2
Buck
Proposed

1.5
1- 67.8 %0.5- 67.2 %- 67.1 %00

510Output current IO [A]15

Fig. 12.
Calculated inductor conduction loss comparison between
proposed ADPH converter and conventional buck converter based on
measured inductor DC current.

to-13 V converter is 97.4 % at 146 W, and the inductor
conduction loss is reduced by 67.2 % by reducing the inductor
DC current by 42.7 %.
As future tasks, we will select power switches suitable forthe proposed ADPH converter and carry out a demonstration
experiment using an inductor with a larger DCR.
ACKNOWLEDGMENT
This work was partly supported by Toyota Industries
Corporation and JSPS KAKENHI Grant Number 20K14710.
The authors would like to thank Sadanori Suzuki of Toyota
Industries Corporation for the technical discussion on theconverter design.

E. Candan, A. Stillwell, N. C. Brooks, R. A. Abramson, J. Strydom,
and R. C. N. Pilawa-Podgurski, "A 6-level Flying Capacitor Multilevel Converter for Single Phase Buck-type Power Factor Correction,"in Proc. IEEE Applied Power Electronics Conference and Exposition(APEC), 2019, pp. 1180-1187.
[2] T. Xie, R. Das, G. Seo, D. Maksimovic, and H-P. Le, "Multiphase
Control for Robust and Complete Soft-charging Operation of Dual
Inductor Hybrid Converter," in Proc. IEEE Applied Power Electronics
Conference and Exposition (APEC), 2019, pp. 1-5.
[3] M. Halamicek, T. McRae, N. Vukadinović, and A. Prodić, "Modulation
Scheme for an Effective Increase in the Number of Levels of DC-DC
Multi-Level Flying Capacitor Converters," in Proc. IEEE AppliedPower Electronics Conference and Exposition (APEC), 2019, pp. 4549.
[4] J. S. Rentmeister and J. T. Stauth, "Zero Voltage Switching for Flying
Capacitor Multilevel Converters at Nominal Conversion Ratios," inProc. IEEE Applied Power Electronics Conference and Exposition(APEC), 2019, pp. 30-36.
[5] Y. Lei, W. Liu, and R. C. N. Pilawa-Podgurski, "An Analytical Method
to Evaluate and Design Hybrid Switched-Capacitor and Multilevel
Converters," IEEE Transactions on Power Electronics, vol. 33, no. 3,
pp. 2227-2240, March 2018.
[6] F. Bez, G. Bonanno, L. Corradini, and C. Garbossa, "Control techniquefor reliable operation of the synchronous series capacitor tapped
inductor converter," in Proc. IEEE Applied Power Electronics
Conference and Exposition (APEC), 2018, pp. 113-120.
[7] S. Biswas and D. Reusch, "GaN Based Switched Capacitor ThreeLevel Buck Converter with Cascaded Synchronous Bootstrap Gate
Drive Scheme," in Proc. IEEE Energy Conversion Congress andExposition (ECCE), 2018, pp. 3490-3496.
[8] O. Kirshenboim and M. M. Peretz, "High-Efficiency Nonisolated
Converter With Very High Step-Down Conversion Ratio," IEEE
Transactions on Power Electronics, vol. 32, no. 5, pp. 3683-3690, May
2017.
[9] P. S. Shenoy, O. Lazaro, R. Ramani, M. Amaro, W. Wiktor, J. Khayat,
and B. Lynch, "A 5 MHz, 12 V, 10 A, monolithically integrated twophase series capacitor buck converter," in Proc. IEEE Applied PowerElectronics Conference and Exposition (APEC), 2016, pp. 66-72.
[10] P. S. Shenoy, M. Amaro, J. Morroni, and D. Freeman, "Comparison ofa Buck Converter and a Series Capacitor Buck Converter for HighFrequency, High-Conversion-Ratio Voltage Regulators," IEEE
Transactions on Power Electronics, vol. 31, no. 10, pp. 7006-7015, Oct.
2016.
[11] N. Vukadinović, A. Prodić, B. A. Miwa, C. B. Arnold, and M. W.
Baker, "Extended wide-load range model for multi-level Dc-Dc
converters and a practical dual-mode digital controller," in Proc. IEEE
Applied Power Electronics Conference and Exposition (APEC), 2016,
pp. 1597-1602.
[12] G. Seo and H-P. Le, "S-Hybrid Step-Down DC-DC ConverterAnalysis of Operation and Design Considerations," IEEE Transactions
on Industrial Electronics, vol. 67, no. 1, pp. 265–275, Jan. 2020.
[13] G. Seo and H-P. Le, "An inductor-less hybrid step-down DC-DC
converter architecture for future smart power cable," in Proc. IEEE
Applied Power Electronics Conference and Exposition (APEC), 2017,
pp. 247-253.
[14] Y. Huh, S. Hong, and G. Cho, "A Hybrid Structure Dual-Path StepDown Converter With 96.2% Peak Efficiency Using 250-mΩ LargeDCR Inductor," IEEE Journal of Solid-State Circuits, vol. 54, no. 4, pp.
959-967, April 2019.
[15] K. Hata, Y. Yamauchi, T. Sai, T. Sakurai, and M. Takamiya, "48V-to12V Dual-Path Hybrid DC-DC Converter," in Proc. IEEE AppliedPower Electronics Conference and Exposition (APEC), 2020, pp.
2279-2284.
[16] X. Liu, P. K. T. Mok, J. Jiang, and W. H. Ki, "Analysis and design
considerations of integrated 3-level buck converters," IEEE
Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 5,
pp. 671–682, May 2016.
[17] Y. Yamauchi, T. Sai, T. Sakurai, and M. Takamiya, "Modeling of 3Level Buck Converters in Discontinuous Conduction Mode for Standby Mode Power Supply," in Proc. IEEE International Symposium for
Circuits and Systems (ISCAS), 2017, pp. 1282-1285.

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