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Japanese Journal of Applied Physics 53, 04EE22 (2014)
http://dx.doi.org/10.7567/JJAP.53.04EE22

Analog-assisted digital low dropout regulator with fast transient response
and low output ripple
Kazuaki Mori1, Yasuyuki Okuma2, Xin Zhang1, Hiroshi Fuketa1, Takayasu Sakurai1, and Makoto Takamiya1
1

University of Tokyo, Meguro, Tokyo 153-8505, Japan
Semiconductor Technology Academic Research Center (STARC), Yokohama 222-0033, Japan

2

Received September 23, 2013; accepted January 13, 2014; published online March 28, 2014
An analog-assisted digital low dropout regulator (AAD-LDO) is proposed to solve the problems of a slow transient response and a large output
ripple in a conventional digital LDO. In the AAD-LDO, a fast-response auxiliary analog LDO is added to the digital LDO in parallel. Compared withthe digital LDO, the measured AAD-LDO in 180 nm CMOS reduces the transient response time and the output ripple by 59 and 28%, respectively,
at the same current efﬁciency of 97.1%. The line regulation is 15 mV/V and the load regulation is 0.63 mV/mA.
© 2014 The Japan Society of Applied Physics

VINIntroduction

The number of on-chip voltage converters is increasing,
because recent SoC’s require a lot of power supply voltage. Alow dropout regulator (LDO) is a reasonable choice for theon-chip voltage converters, because LDO requires no offchip components. The low-power SoC’s require a low-inputvoltage LDO with the low quiescent current (IQ) (= supplycurrent for a controller in LDO).1–23) A digital LDO1–5,24,25)
achieves the low-input-voltage operation with a low IQ. The
problems of the digital LDO, however, are a slow transient
response and a large output ripple. To solve these problems,
an analog-assisted digital low dropout regulator (AAD-LDO)
is proposed.

LoadVOUTFig. 1. Conventional analog LDO.

Problems of conventional LDOs

VIN

DigitalComparator
VREF

M1
M2
M3
WUNIT
Mn
VOUT
LoadFigure 1 shows a conventional analog LDO. The current
efﬁciency (©) of the analog LDO is low owing to the high IQ
in the operational ampliﬁer. Figure 2 shows a conventional
digital LDO.1) In the digital LDO, the current efﬁciency ishigh owing to the low IQ in the controller and the comparator,
though the transient response is slow and the output ripple islarge. In order to reduce the transient response time, a highfrequency clock (Clk) is required, which increases IQ anddecreases ©.2,3) In order to reduce the ripple, the unit gate
width (WUNIT) of the power transistors is reduced and thenumber (n) of power transistors is increased. The increasedn, however, increases IQ and decreases ©. Therefore, a newcircuit is required to reduce both the transient response timeand the ripple without decreasing ©.
3.

VREF

ClkFig. 2. Conventional digital LDO.1)

VIN

Proposed analog-assisted digital LDO

Figure 3 shows the concept of the proposed AAD-LDO. In
the AAD-LDO, a fast-response auxiliary analog LDO isadded to the digital LDO in parallel. Figure 4 shows adetailed schematic of the proposed AAD-LDO. In the AADLDO, the digital LDO is the main LDO and the analog LDO
is auxiliary LDO, because WANALOG < WDIGITAL. The digital
LDO slowly controls the output voltage (VOUT) with a coarse
digital voltage step. In contrast, the analog LDO quicklycontrols VOUT with a ﬁne analog voltage control. By
operating both the digital LDO and the analog LDO
simultaneously in parallel, the AAD-LDO reduces both thetransient response time and the output ripple.
04EE22-1

VREF
ClkDigital
LDO(Main)

AnalogLDO(Sub)
VOUTLoad2.

AnalogController

1.

Fig. 3. Concept of proposed AAD-LDO.

© 2014 The Japan Society of Applied Physics

Jpn. J. Appl. Phys. 53, 04EE22 (2014)

K. Mori et al.

Sub analog LDO

Main digital LDO

VREF(0.95V)

VIN(1.2V)
M1
VREF(0.95V)

M2
M3AnalogWANALOG = 40µm

M256

LoadController

8-bit
digital

10nF

Clk(1MHz)WDIGITAL = 1µm X 256= 256µm

VOUT(0.95V)

Fig. 4. Detailed schematic of proposed AAD-LDO.

Table I. Performance summary of AAD-LDO.

0.5mm

1.2mm

170µm

Analog
LDO

Fig. 5. (Color online) Chip photomicrograph and layout of AAD-LDO.

4.

Measurement results and discussion

Both the AAD-LDO and the digital LDO are fabricated in
180 nm CMOS. In the AAD-LDO and the digital LDO, thedigital LDO part is the same and only the AAD-LDO has theanalog LDO. Figure 5 shows the chip photomicrograph andthe layout of the AAD-LDO. The total chip area was
1.2 © 0.5 mm2. The core areas of the digital and analog
LDOs are 200 © 170 µm2 and 30 © 50 µm2, respectively.
Table I shows a measured performance summary of theAAD-LDO. The fabricated AADLDO achieved the 1.2 V
input voltage and 0.95 V output voltage with 99.6% current
efﬁciency and a 14.2 µA quiescent current at a 3.4 mA loadcurrent (IOUT). The static line regulation is 15 mV/V when
the input voltage (VIN) is varied from 1.15 to 1.25 V. The
static load regulation is 0.63 mV/mA when IOUT is varied
from 1.7 to 3.4 mA.
In the following measurement, VIN is 1.2 V, VOUT is 0.95 V,and IOUT is 3.4 mA. The reference voltage (VREF) is changed
from 0.8 to 0.95 V and the response time of VOUT is measured
at the load resistance of 270 ³.
In the design of the LDO, ©, the transient response time ofVOUT, and the ripple of VOUT are three important characteristics. In the conventional digital LDO, the clock frequency is180 nm

Active area0.036 mm2

Clock frequency
Input voltage

1 MHz
1.2 V

Output voltage

0.95 V

Maximum load current

11 mA

Nominal load current (l1)

3.4 mA

Output capacitor

10 nF (Off-chip)Quiescent current at l1

14.2–242 µA

Current efﬁciency at l1

93.3–99.6%

Line regulation
Load regulation

15 mV/V
0.65 mV/mA

Transient response time [µs]DigitalLDO

30µm

200µm

50µm

CMOS technology

3200KHz

21MHz4MHz
1AAD-LDO(Proposed)
096979899
Current efficiency [%]100Fig. 6. Measured © dependence of transient response time in AAD-LDO.

a key parameter to tune the characteristics. In contrast, in the
proposed AAD-LDO, both the clock frequency and the bias
current of the operational ampliﬁer in the analog LDO are
key parameters to tune the characteristics.
In order to ﬁnd the optimum clock frequency in the AADLDO, Fig. 6 shows the measured © dependence of thetransient response time in the AAD-LDO. Both the clock
frequency and the bias current are varied. When the clock
frequency is increased from 200 kHz to 4 MHz, both thetransient response time and © are reduced. In this work, theclock frequency of 1 MHz is used in the following measure-

04EE22-2© 2014 The Japan Society of Applied Physics

Transient response time [µs]Jpn. J. Appl. Phys. 53, 04EE22 (2014)

K. Mori et al.
Fig.9(a)50Conv. digital LDO

30
20
10

VREF

-94%

5-59%

32
195

0.95V

40µs

Digital LDO(Conv.)

VOUT

0.8V

50mV

AAD-LDO(Proposed)

10µs

Fig.9(b)

96
97
98
99
Current efficiency [%]Clk (1MHz)100(a)

Proposed AAD-LDO

Fig. 7. Measured transient response time vs current efﬁciency.

0.95V

2.4µs
VREF

Output ripple [mV]

141210

VOUTDigital LDO Fig.10(a)0.8V

50mV(Conv.)
10µs

-28%

864Clk (1MHz)

Fig.10(b)AAD-LDO(Proposed)

(b)

2095

96979899
Current efficiency [%]Fig. 9. (Color online) Measured transient waveforms of VREF and VOUT at© of 99.6%. (a) Conventional digital LDO. (b) Proposed AAD-LDO.

100

Fig. 8. Measured output ripple vs current efﬁciency.

Conv. digital LDO
1µµsment to achieve © larger than 98% and a fast transientresponse time.
Figures 7 and 8 show the measured © dependence ofthe transient response time and the peak-to-peak ripple ofVOUT, respectively, in the conventional digital LDO and theproposed AAD-LDO. The clock frequency is varied from 1to 14 MHz in the digital LDO, while the bias current of theoperational ampliﬁer is varied from 1 to 15 µA in the AADLDO at the clock frequency of 1 MHz. Compared with theconventional digital LDO, the proposed AAD-LDO reduces
the response time from 40 to 2.4 µs by 94% and from 4.4 to
1.8 µs by 59% at © of 99.6 and 97.1%, respectively. Figure 9shows the measured waveforms of VREF and VOUT at © of99.6%. Similarly, AAD-LDO reduces the ripple from 10.8 to
7.8 mV by 28% at © of 97.1%, as shown in Fig. 10.
In order to investigate the dynamic line regulation, Fig. 11
shows the measured waveforms of VIN and VOUT of theconventional digital LDO and the proposed AAD-LDO at ©
of 99.6%. The clock frequency is 1 MHz. VIN is changed
between 1.15 and 1.25 V at 10 kHz. In the digital LDO inFig. 11(a), the transient drop of VOUT at the falling edge ofVIN is 50 mV. In contrast, in AAD-LDO in Fig. 11(b), thetransient drop is reduced to 5 mV by adding the fast-response
auxiliary analog LDO.
In order to investigate the dynamic load regulation, Fig. 12shows the measured waveforms of IOUT and VOUT of theconventional digital LDO and the proposed AAD-LDO at ©
of 97.1%. The clock frequencies of the digital LDO andAAD-LDO are 10 and 1 MHz, respectively. IOUT is changed

10.8mVVOUT

Clk (10MHz)(a)

Proposed AAD-LDO
5µµs
VOUT

7.8mVClk (1MHz)(b)
Fig. 10. (Color online) Measured output ripple waveforms at © of 97.1%.
(a) Conventional digital LDO. (b) Proposed AAD-LDO.

between 1.7 and 3.4 mA at 10 kHz. In the digital LDO inFig. 12(a), the transient drop of VOUT is 100 mV. In contrast,in the AAD-LDO in Fig. 12(b), the transient drop is reduced
to 40 mV by adding the fast-response auxiliary analog LDO.

04EE22-3© 2014 The Japan Society of Applied Physics

Jpn. J. Appl. Phys. 53, 04EE22 (2014)

K. Mori et al.

Conv. digital LDOConv. digital LDO
1.25V

IOUT

VIN

1.7mA

3.4mA

1.15V
50mV

VOUT

95mV

100mV

20µµs

20µs

(a)

(a)

Proposed AAD-LDO

Proposed AAD-LDO

1.25V

IOUT

VIN

1.7mA

3.4mA

1.15V

40mV

5mV

VOUT

95mV
20µs

20µs

(b)

(b)
Fig. 11. (Color online) Measured waveforms of VIN and VOUT .
(a) Conventional digital LDO. (b) Proposed AAD-LDO.

Fig. 12. (Color online) Measured waveforms of IOUT and VOUT .
(a) Conventional digital LDO. (b) Proposed AAD-LDO.

5.

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Conclusions

The AAD-LDO is proposed to solve the problems of the slow
transient response and the large output ripple in a conventional digital LDO. Compared with the digital LDO, themeasured AAD-LDO in 180 nm CMOS reduces the transient
response time and the output ripple by 59 and 28%,
respectively, at the same current efﬁciency of 97.1%. At
the dynamic change of VIN, the transient drop of VOUT isreduced from 50 to 5 mV by adding the fast-responseauxiliary analog LDO in the AAD-LDO. Similarly, at thedynamic change of IOUT, the transient drop of VOUT is reduced
from 100 to 40 mV in the AAD-LDO.
Acknowledgements

This work was partly carried out as a part of the Extremely
Low Power (ELP) project supported by the Ministry ofEconomy, Trade and Industry (METI) and the New Energyand Industrial Technology Development Organization(NEDO). The VLSI chips were fabricated in the chip
fabrication program of VDEC in collaboration with Rohm
Co., Ltd. and Toppan Printing Co., Ltd.

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04EE22-4© 2014 The Japan Society of Applied Physics