IEICE TRANS. ELECTRON., VOL.E94–C, NO.6 JUNE 2011

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BRIEF PAPER

Special Section on Analog Circuits and Related SoC Integration Technologies

Power Supply Voltage Dependence of Within-Die Delay Variation ofRegular Manual Layout and Irregular Place-and-Route Layout
Tadashi YASUFUKU†a) , Member, Yasumi NAKAMURA† , Zhe PIAO† , Nonmembers,
Makoto TAKAMIYA† , Member, and Takayasu SAKURAI† , Fellow

SUMMARY
Dependence of within-die delay variations on power supply voltage (VDD ) is measured down to 0.4 V. The VDD dependence of thewithin-die delay variation of manual layout and irregular auto place androute (P&R) layout are compared for the first time. The measured relative
delay (=sigma/average) variation diﬀerence between the manual layout andthe P&R layout decreases from 1.56% to 0.07% with reducing VDD from
1.2 V to 0.4 V, because the random delay variations due to the random transistor variations dominate total delay variations instead of the delay variations due to interconnect length variations at low VDD .
key words: within-die delay variation, design methodology, low voltage

1.

Introduction

Reduction of power supply voltage (VDD ) is an eﬀective
method for achieving ultra low power logic circuits, andmaximum energy eﬃciency is achieved at low VDD (e.g.,340 mV [1]). Thus, many works have been carried out on
the low VDD operation of logic circuits [1]–[4]. Transistor
variation is, however, more pronounced at low VDD [2]. Thismeans that the design of logic circuit becomes more diﬃcult
at low VDD because the transistor variation makes it diﬃcult
for logic gate paths to meet timing constraints. Therefore,
in this paper, the within-die delay variation dependence on
VDD in several types of design under tests (DUT’s) is discussed.
Many works on within-die delay variation have been
carried such as [5]. The impact of methodology of physicallayout on within-die delay variation, however, is not clear.
Layout of logic circuits is usually designed by place androute (P&R) tools. In this case, the interconnect capacitanceis larger than the manual layout. The eﬀect of the auto P&R
layout on delay variation is not clear at low voltages. Thus,DUT delay dependence on methodology of physical layout
is mainly discussed in this paper.
Section 2 presents an all digital delay measurement circuit, and explains its operation. Section 3 shows the experimental results. The delay variation dependence on several
types of DUT’s are discussed. The manual layout and theauto P&R are also compared. Section 4 concludes this paper.

Manuscript received January 21, 2011.
The authors are with The University of Tokyo, Tokyo, 1538505 Japan.
a) E-mail: tdsh@iis.u-tokyo.ac.jp
DOI: 10.1587/transele.E94.C.1072

2.

All Digital Delay Measurement Circuit

Figure 1(a) shows a single unit of the all digital delay measurement circuit. DUT delay is measured by sweeping clock
frequency. The left part of the schematic diagram is VDD region (= 0.4 V to 1.2 V), and the right side is VDDH region (=1.2 V). DUT’s are placed in the VDD region. Delay of one
DUT is measured in this unit. Error memory and scan chain
for reading results are placed in the VDDH region.
Figure 1(b) shows a timing chart of delay measurement
circuit. All F/F’s are reset before starting measurement.
When the DUT delay is shorter than the clock period (T),an error does not occur. On the other hand, when the DUT
delay is longer than T, an error is detected and the Error
Out signal changes from low to high. Error Out signal isconverted to VDDH level by the level shifter and is stored inan error memory. Output of this error memory can be readusing the scan chain. In this way, DUT delay is measured
digitally. Figure 2 shows the chip micrograph. The die size

†Fig. 1 Schematic and timing chart of proposed tester-friendly all digitaldelay measurement circuit. (a) Schematic diagram. (b) Timing chart.

c 2011 The Institute of Electronics, Information and Communication Engineers
Copyright BRIEF PAPER1073

Fig. 2 Chip micrograph of delay measurement circuit fabricated in65 nm standard CMOS process.

Table 1

Key features of manual layout and auto place and route layout.

is 1500 μm × 490 μm fabricated in 65 nm standard CMOS
process. The test chip has two types of DUT’s and each
DUT type consists of 128 delay measurement units shownin Fig. 1(a). This enables the measurement of within-die delay variation of 128 DUT’s.
Various types of DUT’s are implemented to survey dependence of DUT delay on gate type, gate width, and layoutmethodology. Regarding the gate type, ×1 size inverter and1 size NAND are implemented. Regarding the gate width,×0.5 size inverter and ×1 size inverter are implemented. Regarding the layout methodology, the layout of ×0.5 size inverter is designed using auto P&R tool, and compared withthe manual layout. Each DUT includes 100 stages. √This
means that the measured within-die variation is 1/ 100
compared to the delay variation at each stage.
In the case of the manual layout, 128 paths of 100-stage
inverters are in a line and the layout of each path is completely regular. In contrast, in the auto P&R layout 100×128
inverters are entangled and the layout of each path is irregular. Table 1 compares key features of the manual layout andthe auto P&R layout. In case of manual layout, interconnect
delay is small and there is no interconnect length diﬀerence.
On the other hand, auto P&R has larger interconnect delayand interconnect length of each path is diﬀerent.
3.

Fig. 3 Measured histogram of within-die DUT delay. (a) VDD =1.2 V. (b)VDD =0.4 V.

Experimental Results

Figure 3(a) shows the measured histogram of within-die
DUT delay at VDD =1.2 V. The auto P&R ×0.5 inverter has
the largest variation of DUT delay because of large interconnect variation. Figure 3(b) shows the measured histogram ofDUT delay at VDD =0.4 V. By comparing Figs. 3(a) and (b),DUT delay and its delay variation at 0.4 V are larger thanthose at 1.2 V. At 0.4 V, the diﬀerence of delay variation between the manual layout and the auto P&R layout is reduced
compared with that at 1.2 V.
Figure 4 shows the dependence of average delay of 128
DUT’s on VDD . This shows average DUT delay (μ) increases with lowering VDD . The delay of the manual layout

Fig. 4Dependence of average DUT delay on VDD .

inverter is always smaller than that of the auto P&R layout.
The ×1 inverter is the fastest due to its high current drivability. Figure 5 shows the measured dependence of standard
deviation (σ) of 128 DUT’s on VDD . Although the diﬀerence of σ between auto P&R layout and other gates is large
at high VDD , the diﬀerence reduces as VDD is reduced. In order to fairly compare delay variation, relative delay variation(σ/μ) is introduced. Figure 6 shows the measured dependence of relative delay variation (σ/μ) on VDD . This shows

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Fig. 5VDD .

Measured dependence of standard deviation (s) of DUT delay onFig. 7 Measured spatial within-die DUT delay distributions normalized
by the average DUT delay at 1.2 V and 0.4 V. (a) Manual layout. (b) Autoplace and route layout.

Fig. 6

Measured dependence of relative delay variation on VDD.

that the diﬀerence of relative delay variation between manual layout and auto P&R decreases from 1.56% to 0.07%
when reducing VDD from 1.2 V to 0.4 V. This eﬀect is explained by the following equations. Regarding manual layout, average delay (μ M ), standard deviation (σ M ) and relative delay variation (σ M /μ M ) is expressed as Eqs. (1)–(3),μ M = RT · CTσ M = RT · ΔCT + ΔRT · CT
σMΔCT ΔRT=+μM
CTRT(1)(2)(3)

where RT is resistance of transistor, ΔRT is standard deviation of RT , CT is transistor capacitance, and ΔCT is standard
deviation of CT . The resistance and capacitance of the interconnect are ignored in Eq. (1). Regarding auto P&R layout,
Average (μA ), Standard deviation (σA ) and relative delay
variation (σA /μA ) of manual layout is expressed as (4)–(6),μA = RT · (CT + C I )σA = RT · (ΔCT + ΔC I ) + ΔRT · (CT + C I )σA ΔCT + ΔC I ΔRT=+μA
CT + C I
RT(4)
(5)
(6)

where C I is capacitance of interconnection and ΔC I is stan-dard deviation of C I . The resistance of the interconnect isignored in Eq. (4). In (3) and (6), ΔRT /RT term dominants
σ M /μ M and σA /μA at low VDD , the transistor variation islarger than the interconnect length variation at low VDD . In
this way, the diﬀerence of relative delay variation becomes
small in low VDD region.
In Fig. 6, NAND has the smallest σ/μ, because the total gate size is the largest in four types of DUT’s. Morespecifically, NAND consists of 4 transistors and other gateshave 2 transistors. It also proved that σ/μ of ×1 inverter issmaller than ×0.5 manual layout√ inverter, because transistor
variation is proportional to 1/ LW [6].
The spatial distribution of delay variation for the manual layout and the auto P&R layout is investigated. Figure 7 shows the measured spatial distribution of within-die
DUT delay normalized by the average delay. This figure
also shows the measured histogram of normalized DUT delay. Figure 7(a) shows the distribution of the manual layout inverter and Fig. 7(b) shows the distribution of the auto
P&R layout inverter. In Fig. 7(a), DUT delay has only random variations caused by the random transistor variations.
The magnitude of the DUT delay variation at 0.4 V is larger
than that at 1.2 V. Figure 7(b) shows that center location haslarger delay than the both ends. This is caused by interconnect length diﬀerence in the auto P&R layout. In orderto check the randomness of the spatial delay distribution at0.4 V in Fig. 7(a), the correlation coeﬃcient of the measured
delay of 128 DUT’s of two dies at 0.4 V is calculated. Thecorrelation coeﬃcient is 0.023. Therefore, the measured

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than the random delay variations due to the random transistor variations. In contrast, the diﬀerence at 0.4 V is verysmall (0.07%), because the random delay variations due torandom transistor variation increases with the reduced VDD
and dominates the total delay variation.
Acknowledgments
This work was carried out as a part of the next-generation
circuit architecture technical development program supported by METI and STARC.
Fig. 8 Measured and simulated spacial within-die DUT delay
distributions of auto P&R layout at 1.2 V.

variation of manual layout inverter is mainly caused by therandom transistor variations.
Figure 8 shows the measured and simulated spatial
within-die DUT delay distributions at 1.2 V. DUT is the auto
P&R layout inverter. The simulated results are obtained byMonte Carlo SPICE simulation after LPE. In this simulation
the threshold voltage of each transistor is changed accordingto standard deviation calculated from AVT of this technology. The spatial delay distribution is similar between themeasured and simulated results. This aﬃrms that the longer
delay seen at the center location is caused by the interconnect length diﬀerence.
4.

Conclusion

VDD dependence of the within-die delay variation on layout
methodology (manual layout and auto P&R layout) is investigated and measured for the first time. The relative delay(=σ/μ) variation diﬀerence between the manual layout andthe P&R layout at 1.2 V is large (1.56%), because the delay variations due to interconnect length diﬀerence is larger

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