1D-19

An On-Chip Characterizing System for Within-Die Delay Variation Measurement ofIndividual Standard Cells in 65-nm CMOSXin Zhang, Koichi Ishida, Makoto Takamiya, and Takayasu Sakurai
University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan
E-mail: zhangxin@iis.u-tokyo.ac.jp

Cont.

1Cont.

CK

VRAMP
Ramp
generator

Delay

VREF_H
VREF_L

0.4
0.2

VSCAN

VSCAN128VSCAN1
100

200

300

400500Time (ps)Sampling
Enable (SE)Sampling timing
generator (STG)

VSCAN_L Reference voltage
generator (7bit DAC) V

OUT=1OUT

Waveform

REFcomp_headsampling enable timing

VDUTFig. 1.

OUT=0VSamplinghead (SH)

VREF

CKt

Block diagram of on-chip sampling oscilloscope.

each type of standard cell (shown as a NAND2 gate forexample), 60 duplicates of DUT’s and SH’s are implemented.
The number of DUT’s and SH’s is chosen by a trade off ofadequate number to show distribution, total available layout
area, and types of standard cells to be measured.
Same comparator (comp_head) is used for measuring both
input and output waveform, thus the offset from comparator
can be cancelled out. A rise-fall controller is implemented toapply rising or falling edge of excitation (EX) signal to theDUT. The oscilloscope controller is shared among all the 60
DUT’s and SH’s in order to minimize the variation introducedby the controlling circuit. Inverters are employed as input andoutput load to DUT, as a common fan-out 4 situation in a real
digital system.
DUT and sampling head #60
DUT and sampling head #2
DUT and sampling head #1

FO4 Load

FO4 Load

Device undertest (DUT)

Rise-fallcontrollercomp_head

I/O selectOutDUTs and sampling heads
DUT# Select

Cont.
Cont.
CKDelay

VSCAN_HVSCAN_L

Sampling Timing
generator (STG)

VREF_H
VREF_LIII. Implementation of On-Chip Characterizing System

Reference voltage
generator (7bit DAC)

Sense enable (SE)

VREF

Oscilloscope controller

Based on the above oscilloscope, an on-chip characterizing
system for individual standard cells is presented in Fig. 2. For

978-1-4244-7514-8/11/$26.00 ©2011 IEEE

VRAMP

0.60Excitation (EX)II. On-Chip Oscilloscope for Waveform Measuring

SE128

SE10.80I Introduction

An on-chip sampling scheme with pico-second timing
resolution was presented in 90nm CMOS [5]. Based on thisarchitecture, an on-chip sampling oscilloscope is implemented
in 65nm CMOS process for on-chip waveform measuring. Fig.
1 shows the block diagram of the on-chip sampling
oscilloscope, which consists of sampling timing generator(STG), reference voltage generator (a 7 bit DAC), and thesampling head (SH).
VDUT is repetitively sampled by the sampling head atsampling enable (SE) edge and compared with VREF. By bothscanning VREF and the timing of SE, VDUT can be converted todigital signal by comp_head. Furthermore, any random noise
introduced by the on-chip sampling oscilloscope can bereduced by averaging hundreds of reconstructed waveforms.

SEcomp_timing

7bit DACVSCAN_H

With the advancement in the deep submicron CMOS
technology beyond 65nm, accurate characterization andmeasurement of delay variation of standard cells is becoming
essential for design for manufacturing, process optimizationand yield enhancement [1,2].
Conventional ways of measuring the delay variation using
ring oscillator or gate-chain [3-4] failed to measure single-gate
contributions, because the period of ring oscillators and gate
chain is determined by the sum of gate delays. Based on the
directly measured waveform of individual gate by using
on-chip sampling oscilloscope [5], our proposed method isable to measure the input and output waveforms of anindividual gate separately, therefore enables thecharacterization of both rising and falling delays.

Voltage (V)Abstract - New characterizing system for within-die delay
variations of individual standard cells is presented. The proposedcharacterizing system is able to measure rising and falling delay
variations separately by directly measuring the input and output
waveforms of individual gate using an on-chip sampling
oscilloscope in 65nm CMOS process. 7 types of standard cells aremeasured with 60 DUT’s for each type. Thanks to the proposedsystem, a relationship between the rising and falling delay
variations and the active area of the standard cells is
experimentally shown for the first time.

Fig. 2.

Circuit schematic of within-die delay variation measure-ment using on-chip sampling oscilloscope.

109

1D-193030
INVx1
NOR2 INVx2 NAND315NOR3INVx4 NAND2

σtpHL/μtpHL (a. u.)

NOR3

Rising output transition

σtpLH/μtpLH (a. u.)

The test chip is fabricated in 65nm CMOS process. Fig. 3
shows the chip microphotograph and the layout. 7 types ofstandard cells: INVx1, INVx2, INVx4 (named by increasingdrivability), NAND2, NOR2, NAND3, and NOR3 aremeasured with 60 DUT’s for each. The total 420 DUT’s and420 sampling heads consume an area of 1200μm×1500μm,
and the oscilloscope controller occupies 280μm×780μm.

NAND3150NAND2

Falling output transition

0024168100Active area (μm )The noise due to on-chip sampling oscilloscope can be
reduced by averaging several reconstructed waveforms. In thisstudy, each waveform is sampled 190 times and averaged tosuppress random noise introduced by the sampling
oscilloscope.
Fig. 4 shows the measured rising and falling delays. (In thispaper, rising/falling delay is also referred as tpLH/tpHL, whichmeans the propagation delay with a low-to-high/high-to-lowtransition in the output.) As we expected, in the rising/fallingtransition, NOR3/NAND3 is observed to be the slowest,
because there are 3 PMOS’s/NMOS’s in series from output topower/ground.
Fig. 5 shows the sigma tp/average tp (σtp/μtp), the x-axis ischosen to be 1 / Active area ( μm 2 ) , where active area means

24168

10

Active area (μm )2

IV. Measurement Results and Analysis

INVx1

INVx2
INVx4
NOR2

2(a)

(b)

Fig. 5. Measured sigma tp/average tp (σtp / μtp) with (a) rising
output transition, and (b) falling output transition.

because tpLH and tpHL are mixed in conventional methods, thedependency of σtp/μtp on active area shown in Fig. 5 is
impossible to be measured. By measuring tpLH and tpHL
separately, such dependency is shown for the first time.

V. Conclusion
An on-chip characterizing system for within-die delay
variations measurement of individual standard cells isproposed and fabricated. Thanks to the proposed scheme, arelationship between the rising and falling delay variation andthe active area is experimentally shown for the first time.

the total gate area of transistors which are on the conducting
path at rising and falling transition, respectively.
As well known, for rising and falling output, the transition
Acknowledgments
is a result of conduction through the devices in the path fromoutput to the power or ground rail. Therefore, for a
The authors would like to thank Masami Murakata, Kenichirising/falling output, the PMOS/NMOS on the transition path
Inagaki and Yasumi Nakamura for the useful discussions. This
will be the significant contributors to the delay variation. Thus,
work was partially supported by STARC. The VLSI chips
were fabricated through the chip fabrication program of VLSI
Design and Education Center (VDEC), the University ofTokyo, with the collaboration by STARC.
Array of DUT’s andArray of DUT’s andsampling heads

sampling heads

Oscilloscope
controller

780 μm

1500 μm

Oscilloscope
controller

1200 μm

tpLH
RisingOutput453015Y

1 2 3 4X

5 6 7 8(a)Fig. 4.

tpHL
Falling
Output60 (ps)delay

510152025
45 30
3540455055
60
65
30 70
7580859095
100
105
15 110
115
Y 120
125
130
135140145150
1 2 3 4X

delay (ps)

5 6 7 8(b)510152025303540
45505560
65707580859095100105110115120125 Y
130135140145150[1] S. Nassif, “Delay variability: sources, impacts and trends,” IEEE
International Solid-State Circuits Conference, pp. 368-369, 2000.
[2] K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, “A gate
delay model focusing on current fluctuation over wide-range ofprocess and environmental variability,” IEEE/ACM International
Conference on Computer Aided Design, pp. 47–53, 2006.

280 μmFig. 3. Photo and layout of the test chip.

60References

NAND2NOR3INVx4

NAND3 INVx2

NOR2INVx1X(c)[3] S. Mukhopadhyay, K. Kim, K. A. Jenkins, C. T. Chuang, and K.
Roy, " An on-chip test structure and digital measurement method
for statistical characterization of local random variability in aprocess," IEEE Journal of Solid-State Circuits, Vol. 43, No. 9, pp.
1951-1963, Sep. 2008.
[4] H. Masuda, S. I. Ohkawa, A. Kurokawa, and M. Aoki, “Challenge:variability characterization and modeling for 65- to 90-nm
processes,” in Proc. IEEE Custom Integrated Circuits Conference,
pp. 908–913, 2005.
[5] K. Inagaki, D. D. Antono, M. Takamiya, S. Kumashiro, and T.
Sakurai, “A 1-ps resolution on-chip sampling oscilloscope with
64:1 tunable sampling range based on ramp waveform division
scheme,” in Proc. IEEE Symp. on VLSI Circuits, pp. 61–62,
2006.

Within-die delay distribution of (a) tpLH, (b) tpHL, (c) actual

layout of DUT’s corresponding to (a) and (b).

110