Low Power and Flexible Braille Sheet Display
with Organic FET's and Plastic Actuators
Makoto Takamiya1, Tsuyoshi Sekitani2, Yusaku Kato2, Hiroshi Kawaguchi3,
Takao Someya2, and Takayasu Sakurai4
1

2

VLSI Design and Education Center, University of Tokyo, Japan
Quantum-Phase Electronics Center, School of Engineering, University of Tokyo, Japan3
Department of Computer and Systems Engineering, Kobe University, Japan
4
Center for Collaborative Research, University of Tokyo, Japan
E-mail: mtaka@iis.u-tokyo.ac.jp

Abstract
Organic FETs (OFETs) are integrated with actuators,
and a Braille sheet display is demonstrated. A newly
developed back-gated OFETs SRAM and the circuits
technology for the Braille sheet display to enhance
speed, yield and lifetime are presented, which will beessential for future large-area electronics made with
OFETs.

4 cm

Introduction
As shown in Table I, flexible and low-cost organic
FETs (OFETs) are suitable for large-area applications
where functional units are distributed on plastic films,
10 cm – 10 m on a side. An integrated system of OFETs Fig. 1 Braille sheet display.
and pressure sensors was reported in [1], and that of
OFETs and photodetector was reported in [2]. In thisFramepaper, an integrated system of OFETs and plastic actuaActuator
tors is proposed, and a Braille sheet display is demonstrated [3]. Device and process technology of the
G
OFETs
D
OFETs and the actuators are shown in [4].
driver
The transition time of the actuator is about 1 s.
S
OFETs
The Braille sheet display has an actuator array. WhenGSRAM
the actuator is sequentially driven, it takes more than 1
minute to change the Braille, which is impractical. The
S
D
OFETs also have several problems. OFETs are chemiBack
gate
Pentacene
cally degraded by the oxygen and moisture in the atmosphere. Threshold voltage (VTH) control process
technology such as an ion implantation is not yet established for OFETs. To increase the speed of the actuator,
OFET SRAM and overdrive techniques for a driver transistor is proposed. To achieve a reliable and stable Fig. 2 Device structures for the Braille sheet display. 4
SRAM operation, a VTH control technology using a back films are stacked.
gate is developed. 5-transistor SRAM cell is also deBraille Sheet Display
veloped to reduce the number of bit lines and cell area.
Figure 1 shows the developed Braille sheet display.
Table I Comparison between our organic FETs (OFETs) and
Braille characters in a 6 x 4 array are shown on the 4 cm
the state-of-the-art silicon MOSFETs.
x 4 cm display. Each Braille character consists of 2 x 3
dots, and the display has a total of 144 dots. The
OFETs
Si MOSFETs
Braille character is changed by moving the dots up and
Design rule
90 nm
50 μm
down by means of the actuator, depending on the input
Hardness
FlexibleSoliddata. As shown in Fig. 2, four films (frame, actuator,
OFETs driver, and OFETs SRAM) are stacked in the
Drive current
25 nA / μm @ 40 V 1 mA / μm @ 1 V
Braille sheet display. Each Braille dot has an OFET
Gate delay
0.3 ms
10 ps
SRAM to compensate for the slow transition of the acCost / areaLow
Hightuator. After the input data are written to all SRAMs,
Cost / transistor
High
Low
all the actuators are driven at once using the drivers depending on the data. In this way, the time required toLifetime
Days
Years

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change the whole Braille is reduced.

DATAb

Key Circuit Technologies
A. 5-Transistor SRAM Cells and Pipelining for
Write-Operation

100/50BIAS

49000/20

VBGATE

Access Tr

Drive Tr

2.0 mmLoad Tr
3.7 mmFig. 450
100
Time (ms)

40ms 40ms
40ms
Total write-time = 5.76 s(b) with pipelining

40ms
40ms

74% delay reduction(a) Without

The VTH control technology using a back gate isshown to compensate for the immature VTH control
process technology and to achieve a reliable SRAM operation. Figure 7 shows ID – VGS characteristics of apMOS OFET. Back gate voltage (VBGATE) is varied.
Figure 8 shows the measured butterfly curves of the
SRAM with varied VBGATE. The static noise margin(SNM) increases as VBGATE increases.
The VTH control technology is also applied tocompensate for the chemical degradation of OFETs andto achieve a reliable SRAM operation. Figure 9 shows
the measured aging characteristics of the inverter in the
SRAM. The OFETs were kept in a nitrogen atmosphere except for the measuring time. As time passes,
the inverter characteristics show a rightward shift due tothe reduced |Vth| of OFETs. Figure 10 shows the aging
characteristics of SNM calculated based to Fig. 9. Bycompensating the reduced |Vth| of OFETs due to thechemical degradation with the back gate, a constant

50-μm design rule

Drive Tr
Load Tr

DATAb(10% – 50% delay)

B. Control of SRAM Static Noise Margin with A Back
Gate

Fig. 3 Circuit of OFETs SRAM and the driver for one actuator.
Back Gate

Voltage (V)Voltage (V)

VPH

pMOS withback gate

Actuator

10 ms

when BL is high, the transition time of DATAb is 40ms,
because the drive current of M1 in Fig. 5 is small. This
slow transition time can be hidden in the SRAM system-level by pipelining the write-operation. Figure 6
shows the timing chart for the pipeline. By pipelining,
the total write-time for the 12 x 12 SRAM cells is reduced from 5.76 s ( = 40 ms x 144) to 1.47 s ( = 10 ms x
143 + 40 ms), which satisfies our design target.

Braille dot

VPL

DATA
40 ms (10% – 90%)

Fig. 6 Timing chart for write-time of SRAM.
pipelining. (b) With pipelining.

VACT

OFETs
driver(c) BL = high(a) w/o pipelining

40ms
1.47 s4000/50

VSS

15
10
DATAb
5
0
-5
-10
2 ms
-15
-20
DATA
-25
-30
5
10
15
20
0
Time (ms)

10 ms

DATA

DATAb

15
10
5
0
-5
-10
-15
-20
-25
-30
0

(b) BL = low

144 SRAM cells

VDD
OFETs
SRAM

BL

Fig. 5 (a) Measured SRAM circuits. Measured SRAM
write-operation when BL is low (b) and high (c).

BL

W/L = 4000μm/50μm

DATA

M1

Figure 3 shows the circuit of the SRAM and thedriver for one actuator. Only pMOS OFETs are used,because the performance of nMOS OFETs is commonly
worse than pMOS. The OFETs for SRAM have backgates [5] to control VTH. A write-only SRAM isenough for our Braille application, because the actuatormoves depending on the hold data (DATA, DATAb) anda SRAM read-operation is not required. Therefore, tosave the film area, a 5-transistor SRAM cell is developed. Compared with a conventional 6-transistor
SRAM cell, a 5-transistor SRAM cell reduces the number of the bit lines by one-half and reduces the SRAM
cell area by 20%. Figure 4 shows a micrograph of the
5-transistor SRAM cell. The cell area is 3.7 mm by 2.0
mm. The whole cell is covered with the back gate.
In the 5-transistor SRAM cell, a foremost concern
is the slow write-time of DATAb, because DATAb has
no access transistors.
Our design target for thewrite-time of the whole SRAM (= 144 cells) is within 2
s. Figure 5 shows the measured waveforms of DATA
and DATAb during a write-operation. When BL is low,
the transition time of DATAb is 2 ms. In contrast,
WL

WL

(a)

Micrograph of the 5-transistor SRAM cell.

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Drain current (μA)

120

–40V

100
VBGATE

VGS

80

40

C. Overdrive Techniques for Driver Transistors

20 V

0V
L = 50 μm
W = 4000 μm

60

SNM can be achieved. Because the chemical degradation is inherent in OFETs, the proposed compensation
technology is essential to OFET applications.

VBGATE = –60V
–40V
–20V
0V

Our design target for the transition time of the actuator is within 2 s. The actuator has a large capacitance (100 μF). The breakdown voltage of the actuatoris 3 V. Figure 11 shows the measured waveforms of
the actuator voltage (VACT) and the actuator displacement. The step voltage height (VX) of VPL is varied.
The required displacement by Braille users is 0.2 mm.
When VPL is equal to the breakdown voltage of -3 V, thetransition time is 34 s, which exceeds our design target.
In order to reduce the transition time, VPH and VPL overdrive techniques are proposed. By increasing VX from
-3 V to -10 V, the transition time is reduced from 34 s to
2.0 s, which satisfies our design target. In order toavoid the breakdown of the actuator, the overdrive period is determined by the time when VACT is within ±3V.
Finally, an operation of the Braille sheet display isdemonstrated. Figure 12 shows the measured waveforms of the driver and the actuator for a Braille dot.
Movement of the Braille dot, both up and down, hasbeen successfully demonstrated. By using overdrive
techniques in VPH and VPL, a 1.6-s actuator transition
time is achieved.

40 V
60 V

20
0

0

–5 –10 –15 –20 –25 –30 –35 –40
VGS (V)

Fig. 7 ID – VGS characteristics of a pMOS OFET with varied
VBGATE.
40

VBGATE – VDD = 0V (Conv.)

DATAb

DATA

–20V

0V

DATAb, DATA (V)

35
40 V

30
25
20
15

VBGATE – VDD = 40V(Proposed)

10
5
0
0

5 10 15 20 25 30 35 40
DATA, DATAb (V)Fig. 8 Measured butterfly curves of SRAM with varied
VBGATE.
40

40 V

20

after 0 day
7 days10 days
15 days

10

0V
0

0

10

20
In (V)(a)30

40

Displacementof actuator (mm) VACT (V)Static noise margin (SNM) (V)with compensation

7

5
4
3
w/o compensation

1
0

0

5
10
15
20
Time after fabrication (day)

VX
0
-1

VX = –3V(b)Fig. 11 (a) Measured driver and actuator circuits.
celerated actuator by overdrive techniques.

Fig. 10 Aging characteristics of the static noise margin andcompensation for the aging.

1-4244-0098-8/06/$20.00 ©2006 IEEE.

0

-2
–5V
–10V
-3
–20V
-4
–10V
0.8 –20V
17x speeding up –5V
0.6
0.4
0.2
VX = –3V0
0 5 10 15 20 25 30 35 40
Time (s)62

DriverActuator

Fig. 9 Measured aging characteristics of the inverter in the
SRAM.
8

VPL

VACT Braille dot

VPL (V)Out

Out (V)

40 V

–20V

Chemicaldegradation

30

40 V
In

DATAb
(-20V)

3(b) Ac-

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Sequential drive of actuators

SRAM
DATAb

DATA

VACT

VPH

InitialdesignSRAM
is added

Final
design1.47 s

Displacementof actuator (mm) Voltage (V)

DATA
DATAb

Fig. 13

1/122

40 s

34 s
5.76 s
Pipelining
Overdrive
3.1 s

VPL
(a)

4896 s

34 s x 144
Write-time of SRAM
Simultaneous drive

1/13

1/15801.6 s

Summary of speeding up Braille sheet display.
Total: 51.9 mW

10

VPH

VACT

5
0
-5
-10
0.4
0.2

SRAM leakage
17.3 mW (33%)

VPL
Braille dot isUp

Dynamic @ 0.1 Hz
13.0 mW (25%)

Actuator leakage
21.6 mW (42%)

0

-0.2
-0.4

0

1.6 s

0.74 s5

1015Time (s)Down
20

Fig. 14 Power consumption for the Braille sheet display at
0.1-Hz operation.

25

overdrive techniques for the driver OFETs reduced thetransition time of the actuator from 34 s to 2 s.
These developed circuit technologies will be essential for the future large area electronics made with
OFETs.

(b)
Fig. 12 (a) Measured Braille sheet display circuits.
Braille sheet display operation.

(b)

Performance Summary
Figure 13 summarizes the time to change 144
Braille dots and the speeding up by the developed circuit
technologies. At an initial design without the SRAM,
it takes 4896 s, because the 144 actuators are sequentially driven. When the SRAM is added, it takes 40 s,
because all actuators are a simultaneously driven after
the data are written to SRAM. At a final design, thedeveloped pipelining for SRAM write-operation andoverdrive technology for the driver increased the speedof the Braille sheet display 1580 times, and achieved thepractical 3.1-s operation.
Figure 14 shows the power consumption for thewhole Braille sheet display at 0.1-Hz operation. The
dominant component is the leakage power of the actuators (21.6 mW= 50 μA x 3 V x 144). In contrast, theleakage power of piezo actuators used in a commerciallyavailable Braille display [6] is 230.4 mW ( = 8 μA x 200
V x 144) which is 10.7 times larger than that of our actuators.

Acknowledgement

The authors acknowledge Prof. M. Doi, University ofTokyo, and Dr. K. Asaka, AIST, for the sheet-type soft actuator
made of perfluorinated polymer electrolyte. This work is
partially supported by JST, IT program, MEXT, and NEDO.

References[1] T. Someya, H. Kawaguchi, and T. Sakurai, "Cut-and-pasteorganic FET customized ICs for application to artificial
skin," ISSCC Dig. of Tech. Papers, pp. 288-289, Feb.
2004.
[2] H. Kawaguchi, S. Iba, Y. Kato, T. Sekitani, T. Someya, and
T. Sakurai, "A sheet-type scanner based on a 3D stackedorganic-transistor circuit with double word-line and double bit-line structure," ISSCC Dig. of Tech. Papers, pp.
580-581, Feb. 2005.
[3] M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T.
Someya, and T. Sakurai," An Organic FET SRAM for
Braille sheet display with back gate to increase static noise
margin," ISSCC Dig. of Tech. Papers, pp. 276-277, Feb.
2006.
[4] Y. Kato, S. Iba, T. Sekitani, Y. Noguchi, K. Hizu, X. Wang,
K. Takenoshita, Y. Takamatsu, S. Nakano, K. Fukuda, K.
Nakamura, T. Yamaue, M. Doi, K. Asaka, H. Kawaguchi,
M. Takamiya, T. Sakurai, and T. Someya, "A flexible,
lightweight Braille sheet display with plastic actuators
driven by an organic field-effect transistor active matrix,"
IEDM Tech. Dig., pp. 105-108, Dec. 2005.
[5] S. Iba, T. Sekitani, Y. Kato, T. Someya, H. Kawaguchi, M.
Takamiya, T. Sakurai, and, S. Takagi, "Control of threshold voltage of organic field-effect transistors with double
gate structure," Applied Physics Letters, 87, 023509, July
2005.
[6] Braille cells, http://www.kgs-jpn.co.jp/epiezo.html, KGS
Corporation.

Conclusions
OFETs were integrated with actuators, and a Braillesheet display was demonstrated. An SRAM made with
OFETs is demonstrated for the first time. Pipelining
the write-operation reduced the SRAM write-time by
74%. Threshold voltage control technology using aback gate increased the SNM and compensated for thechemical degradation of the OFETs after 15 days. The

1-4244-0098-8/06/$20.00 ©2006 IEEE.

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