Digital Active Gate Driving Automatically
Minimizing Switching Loss While Keeping
Surge Current Below User-Specified Target
Toshiaki Inuma1, Dibo Zhang1, Katsuhiro Hata1, Kazuto Mikami2, Kenji Hatori2, Koji Tanaka2,
Wataru Saito3, and Makoto Takamiya1
1
The University of Tokyo, Tokyo, Japan2
Mitsubishi Electric Corporation, Fukuoka, Japan
3
Kyushu University, Fukuoka, Japan
Abstract-- To address the user-specified surge current
targets and the trade-off problem between surge current andswitching loss in gate drivers, a digital active gate driving
method is proposed that automatically minimizes theswitching loss while keeping the surge current below the userspecified target. A 6.5 kV IGBT is driven at 3.6 kV and 56 A
load current using a digital gate driver (DGD) IC that canchange the gate current in 64 levels from 0 A to 1 A in 480 ns
steps. For each of the four user-specified surge current
targets at turn-on, the optimum parameters of DGD aresearched by repeating the double-pulse test 2500 times using
the simulated annealing algorithm. As a result, the switchingloss is successfully reduced by 18 % to 27 % compared withthe conventional gate driving while automatically meeting thesurge current targets.

voltage/current [1-9]. In DGD, ELOSS and surge
voltage/current are programmable within a certain range,
because IG is software-controlled and can be automatically
optimized [1-2, 9]. In gate driver design, there is a highdemand for minimizing ELOSS while keeping surge
voltage/current below the user-specified target. Previous
DGD papers [1-2, 9], however, minimize both ELOSS andsurge voltage/current with the same weights and do notachieve the above need. To solve the problem, in this paper,a digital active gate driving method is proposed that
automatically minimizes ELOSS while keeping the surge
current (IOVERSHOOT) below the user-specified target.

Index Terms-- Gate driver, switching loss, surge current,
IGBT.

Figs. 1 and 2 show a circuit schematic and a timing chartof the developed DGD IC, respectively. In the following,
turn-on is discussed for simplicity, whereas the exact sameis true for turn-off. This open-loop DGD IC is modified
from the closed-loop DGD IC [6-7]. The modifications are
the following three points. (1) The sensor for the closedloop active gate driver is removed and “Timing” input isadded to define the timing to change IG. (2) The number ofslots for IG change at turn-on is increased from 3 to 9. (3)I. INTRODUCTION
Digital gate drivers (DGDs), which digitally change thegate current (IG) multiple times in fine time slots during theswitching period of power devices, are attracting attention
as a technology that can solve the trade-off problem
between the switching loss (ELOSS) and surge

II. PROPOSED DIGITAL ACTIVE GATE DRIVING METHOD

Digital gate driver (DGD) IC
5V

SIPO 108

nPMOS
6
PISOs

15 V

1WP
IO

32WP
32IO

IO

32IO

Level shifter
Scan In
Scan CLKIN
5V
TimingSIPO 108

6
PISOs

nNMOS

IC
IG
VGE

VCE

15 V
1WN

Serial-in parallel-out shift register (SIPO)
Parallel-in serial-out shift register (PISO)

32WN

IG = nPMOS×16 mA
nPMOS : Integer from 0 to 63

Fig. 1. Circuit schematic of developed DGD IC.

tON1 tON2 tON3 tON4 tON5 tON6 tON7 tON8
IN

tON1 tON2

tOFF1 tOFF2 tOFF3 tOFF4 tOFF5 tOFF6 tOFF7 tOFF8
Off

On

On

Timing
63

nPMOS

0

63

nNMOS

0

IG 0 A
15 V

VGE
−15 V

IC

ITARGETIL

IOVERSHOOT

0A
3.6 kV

VCE
0V

Timing chart of developed DGD IC.

2

f OBJ = ELOSS 
max ( I OVERSHOOT , I TARGET ) − I TARGET 5 + 10 E
I TARGET LOSS, MAX (1)

where ELOSS,MAX is the maximum of ELOSS in SGD. The
intent of defining this fOBJ is to keep IOVERSHOOT below
ITARGET in the first priority and minimize ELOSS in thesecond priority. For the purpose of differentiating between
the first and second priority, 105 is multiplied by the later

6-bit
pMOS
drivers

2.0 mm

The maximum IG value is reduced from 3 A to 1 A, because
the gate charge of the target IGBT is small. The equation
for IG is shown in Fig. 1. As shown in Fig. 2, IG can bevaried 9 times with 6 bits ( = 64 levels) in time steps fromtON1 to tON8. tON1 to tON8 are determined by the period of“Timing”. tON1 to tON8 need not be identical and can bedifferent values for each. Definitions of the load current(IL), IOVERSHOOT and the surge current target (ITARGET) are
shown in Fig. 2. Figs. 3 and 4 show photos of DGD IC
fabricated with 180-nm BCD process and a gate driver
PCB including DGD IC, respectively. The die size is 2.0
mm by 2.5 mm. The gate driver PCB also includes a signal
isolator (IL260-3E), two 15 V isolated DC-DC converters(MGS1R50515), and two 5 V isolated DC-DC converters(MGS1R50505). Figs. 5 and 6 show a circuit schematicand a measurement setup of the double pulse test at 3.6 kV
and IL = 56 A using the developed DGD IC and two 6.5
kV IGBT modules, respectively. Figs. 7 (a) and (b) show
timing charts of the conventional single-step gate driving(SGD) and the proposed active gate driving (AGD) at turnon for comparison, respectively. In SGD, n is varied,
which emulates a conventional gate driver with varied gate
resistance. In AGD with 480 ns × 4 slots and last long slot,
five parameters (n1 to n5) are varied. n and n1 to n5 are
integers from 0 to 63. To achieve the proposed digital
active gate driving method, the double pulse tests arerepeated 2500 times, and each time ELOSS and IOVERSHOOT
are measured to calculate an evaluation function (fOBJ)
defined in Eq. (1), and the combination of the fiveparameters (n1 to n5) that minimizes fOBJ is searched using
the simulated annealing algorithm [1]. The search takes 37
minutes.

6-bit
nMOS
drivers

2.5 mmFig. 3.

Die photo of DGD IC.

50 mm

Fig. 2.

DGD IC275 mm
Fig. 4.

Photo of gate driver PCB including DGD IC.

IGBTmodules

IN
IL

Off
0

IG

IG
VGE

n

nPMOS 63
3.6 kVDGD IC

On

0A

VCE

(a) Conventional single-stepgate driving (SGD)

IC
Fig. 5. Circuit schematic of double pulse test.

IN

Off

On
n1

nPMOS 63

n3

n2

n5
n4

0

IG
IGBT modules

0A

480 ns(b) Proposed active gate
driving (AGD)

DGD IC

Fig. 7. Timing charts at turn-on. (a) Conventional single-step gate
driving (SGD). (b) Proposed active gate driving (AGD).

term, where 105 has no physical meaning and can be anylarge number. The definition of fOBJ differs from theprevious papers [1-2, 9] that minimize both ELOSS and
IOVERSHOOT with the same weights.
III. MEASURED RESULTS
Fig. 8 shows the measured ELOSS vs. IOVERSHOOT of theconventional SGD and the proposed AGD. The black
curve is the trade-off curve for SGD with varying n. The
proposed AGDs at user-specified ITARGET of 50 A, 60 A,
70 A, and 80 A are Points A, B, C, and D, respectively,
where each has successfully achieved minimizing ELOSS
while keeping IOVERSHOOT below ITARGET. Points E and F
are the conventional SGD points with IOVERSHOOT
approximately the same as the proposed Points A and D,
respectively. Compared with SGD (Points E and F), theproposed AGD (Points A and D) reduces ELOSS by 27 %and 18 % under IOVERSHOOT-aligned condition, respectively.
Figs. 9 (a) to (f) show the measured waveforms of
Points A to F in Fig. 8, respectively. In the proposed AGDs
(Points A to D), for each of four ITARGET, ELOSS is
minimized while keeping IOVERSHOOT below ITARGET byautomatically searching for the optimum five parameters(n1 to n5). Comparing the waveforms of Points D and F
with IOVERSHOOT = 80 A, the proposed Point D (Fig. 9 (d))
suppresses IOVERSHOOT by n2 = 4 while reducing ELOSS by
n4 = 54, compared with the conventional Point F (Fig. 9(f)) with the constant n = 12.

400

Point E
Conv. SGD

350
300

ELOSS [mJ]Fig. 6. Measurement setup of double pulse test.

ELOSS, MAX

ITARGET = 50 A to 80 A

250

200
150

−27%

Point F−18%
Point A
Point B
Point C Point D

100

Proposed
AGD

50

0
0

20

40

60

80

100

120

140

IOVERSHOOT [A]Fig. 8. Measured ELOSS vs. IOVERSHOOT of conventional SGD andproposed AGD at user-specified ITARGET of 50 A, 60 A, 70 A, and 80
A.

IV. DISCUSSION
A. Lower Limit of ITARGET
Not surprisingly, the proposed digital active gate
driving method is not a perfect solution, and there is alower limit of ITARGET that can be achieved. Therefore, thelower limit of ITARGET in the proposed digital active gate

(IOVERSHOOT, ELOSS) = (50 A, 262 mJ)(IOVERSHOOT, ELOSS) = (59 A, 249 mJ)(IOVERSHOOT, ELOSS) = (70 A, 238 mJ)

1 μs/div

1 μs/div

1 μs/div

VCE: 1 kV/div

VCE: 1 kV/div

VCE: 1 kV/div

ITARGET = 70 A

ITARGET = 60 A

ITARGET = 50 A

IC: 40 A/div

IC: 40 A/div

IC: 40 A/div

000
VGE: 20 V/div

1

9

VGE: 20 V/div

58 6356

0

7

2

63

nPMOS

0

36
36
14
14

nPMOS

nPMOS

VGE: 20 V/div
63
63

2530
0 14

2

480 ns×4 slot(a) Point A (AGD, ITARGET = 50 A)

480 ns×4 slot(b) Point B (AGD, ITARGET = 60 A)

480 ns×4 slot(c) Point C (AGD, ITARGET = 70 A)(IOVERSHOOT, ELOSS) = (80 A, 230 mJ)(IOVERSHOOT, ELOSS) = (48 A, 360 mJ)(IOVERSHOOT, ELOSS) = (80 A, 279 mJ)

1 μs/div

1 μs/div

VCE: 1 kV/div

1 μs/div

VCE: 1 kV/div

VCE: 1 kV/div

ITARGET = 80 A
IC: 40 A/div

IC: 40 A/div

IC: 40 A/div

0

0

0

2

480 ns×4 slot(d) Point D (AGD, ITARGET = 80 A)

nPMOS

0

54
22 31
4

VGE: 20 V/div

VGE: 20 V/div
nPMOS

nPMOS

VGE: 20 V/div

6

0

12

0

(e) Point E (SGD, n = 6)(f) Point F (SGD, n = 12)

Fig. 9. Measured waveforms of Points A to F in Fig. 8.

ELOSS, MAX

ITARGET = 40 A to 80 A
400

Point H
350
−30%

Point E
Conv. SGD
Point F

300

ELOSS [mJ]

driving method is discussed below. In Fig. 10, Point G of
the proposed AGD at user-specified ITARGET of 40 A is
added to Fig. 8. IOVERSHOOT at Point G is 42 A and fails tokeep IOVERSHOOT below ITARGET of 40 A. The reason for thisis discussed below. As a representative example of the
proposed AGD, Fig. 11 shows the results of 2500
measurements performed to search for the optimal gate
driving waveform at ITARGET = 50 A, with blue dots. The
best AGD with the smallest fOBJ among 2500 points is
Point A. In the proposed digital active gate driving method,by varying the five parameters (n1 to n5) controlling thegate driving waveform using the simulated annealing
algorithm, it can be clearly seen that the best gate driving
waveform (Point A) that minimizes ELOSS while keeping
IOVERSHOOT below 50 A is searched over a wide range of
ELOSS and IOVERSHOOT. Among the 2500 measurements, theminimum value of IOVERSHOOT is 42 A. This means thatAGD defined in Fig. 7 (b) would not be able to achieve
IOVERSHOOT of less than 42 A, which is the reason why Point
G failed to achieve IOVERSHOOT below ITARGET of 40 A in
Fig. 10.

250 Point G

200
150

−18%
Point A
Point B
Point C Point D

100

Proposed
AGD

50

0
0

20

40

60

80

100

120

140

IOVERSHOOT [A]Fig. 10. Measured ELOSS vs. IOVERSHOOT of conventional SGD andproposed AGD at user-specified ITARGET of 40 A, 50 A, 60 A, 70 A,
and 80 A.

ELOSS, MAX

ITARGET = 40 A to 80 A

(IOVERSHOOT, ELOSS) = (42 A, 275 mJ)
VCE: 1 kV/div

400

1 μs/div

Conv. SGD

350

ITARGET = 40 A

250

IC: 40 A/div2500 measured points@ ITARGET = 50 A
to find Point A

150
100
50

0
0

0

VGE: 20 V/div
20

40

60

80

100

120

140

IOVERSHOOT [A]Fig. 11. Measured ELOSS vs. IOVERSHOOT of conventional SGD andproposed AGD at user-specified ITARGET of 50 A.

B. ITARGET Dependence of ELOSS Reduction Rate
In Fig. 10, ITARGET dependence of the ELOSS reduction
rate of the proposed AGD to the conventional SGD is
discussed. Compared with SGD, the proposed AGD
reduces ELOSS by 30 %, 27 %, 21 %, 19 %, and 18 % at
ITARGET = 40 A, 50 A, 60 A, 70 A, and 80 A under
IOVERSHOOT-aligned condition, respectively. Thus, as
ITARGET increases, the ELOSS reduction rate decreases. The
reason for this is that, as shown in Fig. 11, in SGD, ELOSS
increases rapidly when IOVERSHOOT is reduced, while in
AGD, focusing on the lower envelope of the blue point
group, ELOSS increases slowly when IOVERSHOOT is reduced.
Figs. 12 (a) and (b) show the measured waveforms of
Point G and Point H in Fig. 10, respectively, where Point
H is the conventional SGD with IOVERSHOOT approximately
the same as the proposed Point G. Compared with Point H,
Point G reduces ELOSS by 30 % from 395 mJ to 275 mJ
under IOVERSHOOT-aligned condition.
V. CONCLUSIONSThe proposed AGD minimizes ELOSS while keeping
IOVERSHOOT below user-specified ITARGET by automaticallysearching for the optimum parameters of DGD, which will
enable prompt development of low-loss power converters
while meeting customer surge specifications. In the double
pulse tests at 3.6 kV and 56 A for 6.5 kV IGBT, comparedwith the conventional SGD, the proposed AGD reduces
ELOSS by 27 % and 18 % at ITARGET = 50 A and 80 A,
respectively.
ACKNOWLEDGMENT
This work was partly supported by NEDO (JPNP21009).

nPMOS

200

Point A

63

0

55

19

6

0

480 ns×4 slot(a) Point G (AGD, ITARGET = 40 A)(IOVERSHOOT, ELOSS) = (42 A, 395 mJ)

1 μs/div

VCE: 1 kV/div

IC: 40 A/div
0
VGE: 20 V/divnPMOS

ELOSS [mJ]

300

0

5
(b) Point H (SGD, n = 5)

Fig. 12. Measured waveforms of Point G and Point H in Fig. 10.

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