DS2450
1-Wire Quad A/D Converter
www.maxim-ic.com

FEATURES
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PIN ASSIGNMENTFour high-impedance inputs to measure
analog voltages over the 1-Wire® bus
User programmable input range (2.56V,
5.12V), resolution (1 to 16 bits) and alarm
thresholds
5V, single supply operation
Very low power: 2.5 mW active, 25 μW idle
Built-in multidrop controller allows multiple
DS2450’s to be identified and operated on acommon 1-Wire bus
Responds to Conditional Search if the analog
voltage crosses the alarm thresholds
Channels not used as analog input can serve
as open drain digital outputs for closed-loop
control
Directly connects to a single port pin of a
microprocessor and communicates at up to
16.3k bits per second
Overdrive mode boosts communication speed
to 142k bits per second
On-chip
16-bitCRC-generatorforsafeguarding data transfers
Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48bit serial number 8-bit CRC tester) assuresabsolute traceability because no two parts are
alike
8-bit
familycode
specifies
devicecommunication requirements to bus master
Operating temperature range from -40°C to+85°C
Compact, low cost 8-pin SOIC surface mountpackage

VCC

1

8

AIN-D

NC

2

7

AIN-C

DATA

3

6

AIN-B

GND

4

5

AIN-A

8-PIN SOIC (208 MIL)PIN DESCRIPTION
VCC
NC
DATA
GND
AIN-A
AIN-B
AIN-C
AIN-D

4.5 to 5.5V
Do Not Connect
1-Wire Bus
GroundAnalog Input A
Analog Input B
Analog Input C
Analog Input D

ORDERING INFORMATION
DS2450S
DS2450S/T&R
DS2450S+
DS2450S+T&R

8-pin SOIC
8-pin SOIC Tape-and-Reel
8-pin SOIC
8-pin SOIC Tape-and-Reel+ Indicates lead-free compliance.
1-Wire is a registered trademark of Dallas Semiconductor.

DESCRIPTION
The DS2450 1-Wire Quad A/D Converter is based on a successive-approximation analog to digitalconverter with a four to one analog multiplexer. Each input channel has its own register set to store theinput voltage range, resolution, and alarm threshold values as well as flags to enable participation of thedevice in the conditional search if the input voltage leaves the specified range. Two alarm flags for eachchannel indicate if the voltage measured was too high or too low without requiring the bus master to do
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DS2450

the comparison. Each A/D conversion is initiated by the bus master. A channel not used as analog input
can serve as a digital open-drain output. After disabling the input the bus master can directly switch on or
off the open-drain transistor at the selected channel. All device settings are stored in SRAM and kept
non-volatile while the device gets power either through the 1-Wire bus or through its VCC pin. After
powering up, a power-on reset flag signals the bus master the need to restore the device settings before
the regular operation can resume. All device registers and conversion read-out registers are organized as
three 8-byte memory pages similar to the Status Memory of a DS2505/6 device. An on-chip CRC16
generator protects the communication against transmission errors when reading through the end of amemory page as well as when writing individual bytes.

OVERVIEWThe block diagram in Figure 1 shows the major function blocks of the device. The DS2450 contains afactory-lasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8bit family code (20H). The 64-bit ROM portion of the DS2450 not only creates an absolutely uniqueelectronic identification for the device itself but also is a means to locate and address the device in order
to exercise its control functions.
The device gets its power either from the 1-Wire bus or through its VCC pin. Without a VCC supply thedevice stores energy on an internal capacitor during periods where the signal line is high and continues tooperate off of this “parasite” power source during the low times of the 1-Wire line until it returns to highto replenish the parasite (capacitor) supply. This, however, provides sufficient energy only forcommunication. To perform an A/D conversion a strong pullup of the 1-Wire bus to 5V or a VCC supply
is required.

DS2450 BLOCK DIAGRAM Figure 1

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DS2450

HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2

The DS2450 uses the standard Dallas Semiconductor 1-Wire protocol for data transfers. Communication
to and from the DS2450 requires a single bi-directional line that is typically a port pin of a
microcontroller. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The 1-Wire bus
master must first provide one of the seven ROM Function Commands, 1) Read ROM, 2) Match ROM, 3)
Search ROM, 4) Conditional Search ROM, 5) Skip ROM, 6) Overdrive-Skip ROM or 7) OverdriveMatch ROM. Upon completion of an overdrive ROM command byte executed at standard speed, thedevice will enter Overdrive mode where all subsequent communication occurs at a higher speed. The
protocol required for these ROM function commands is described in Figure 9. After a ROM functioncommand is successfully executed, the memory and control functions become accessible and the mastermay provide any one of the available commands. The protocol for these commands is described in Figure
6. All data is read and written least significant bit first.

64-BIT LASERED ROM
Each DS2450 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (SeeFigure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the
Dallas 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButtonTM Standards. The
shift register acting as the CRC accumulator is initialized to zero. Then starting with the least significant
bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered,then the serial number is entered. After the 48th bit of the serial number has been entered, the shift
register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all
zeros.
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DS2450

64-BIT LASERED ROM Figure 3

1-WIRE CRC-GENERATOR Figure 4

DEVICE REGISTERS
All registers of the DS2450 are mapped into a linear memory range of 24 adjacent bytes organized as
three 8-byte pages. The first page, called conversion read-out, contains the memory area where the chipinternal logic places the results of a conversion for the bus master to read. Starting with channel A at thelowest address, each channel has an area of 16 bits assigned for the conversion result, as shown in Figure
5a. The power-on default for the conversion read-out registers is all zeros. Regardless of the resolution
requested, the most significant bit of the conversion is always at the same bit position. If less than 16-bit
resolution is requested, the least significant bits of the conversion result will be filled with zeros in order
to always generate a 16-bit result. For applications that require less than four analog inputs, one should
start using input D for the first channel, input C for the second one, etc. The advantage is that whenreading the conversion results one reaches the end of the page and with it the CRC16 sooner andminimizes the traffic on the 1-Wire bus. For more details on reading please refer to the Read Memorycommand description.

MEMORY MAP PAGE 0, CONVERSION READ-OUT Figure 5a
Address
00
01
02
03
04
05
06
07

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

A
MSBIT AB
MSBIT BCMSBIT CD
MSBIT D

A
A
B
B
C
C
D
D

A
A
B
B
C
C
D
D

A
A
B
B
C
C
D
D

A
A
B
B
C
C
D
D

A
A
B
B
C
C
D
D

A
A
B
B
C
C
D
D

LSBIT AA
LSBIT BB
LSBIT CCLSBIT DDThe control and status information for all channels is located in memory page 1 (Figure 5b). As for theconversion read-out, each channel has assigned 16 bits. The four least significant bits, called RC3 to
RC0, are an unsigned binary number that represents the number of bits to be converted. A code of 1111
(15 decimal) will generate a 15-bit result. For a full 16-bit conversion the code number needs to be 0000.
The next two bits beyond RC3 will always read 0. They have no function and cannot be changed to 1s.

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DS2450

The next bits, OC (output control) and OE (enable output) control the alternate use of a channel as output.
For normal operation as analog input the OE bit of a channel needs to be 0, rendering the OC bit to a
don’t care. With OE set to 1, a 0 for OC will make the channel’s output transistor conducting, a 1 for OC
will switch the transistor off. With a pullup resistor to a positive voltage, for example, the OC bit will
directly translate into the voltage equivalent of its logic state. Enabling the output does not disable theanalog input. Conversions remain possible, but will result in values close to 0 if the transistor isconducting.
The IR bit in the second byte of a channel’s control and status memory selects the input voltage range.
With IR set to 0, the highest possible conversion result is reached at 2.55V. Setting IR to 1 requires aninput voltage of 5.10V for the same result. The next bit beyond IR has no function. It will always read 0
and cannot be changed to 1.
The next two bits, AEL alarm enable low and AEH alarm enable high, control whether the device will
respond to the Conditional Search command (see ROM Functions) if a conversion results in a value
higher (AEH) than or lower (AEL) than the channel’s alarm threshold voltage as specified in the alarm
settings. The alarm flags AFL (low) and AFH (high) tell the bus master whether the channel’s input
voltage was beyond the low or high threshold at the latest conversion. These flags are cleared
automatically if a new conversion reveals a non-alarming value. They can alternatively be written to 0 by
the bus master without a conversion.
The next bit of a channel’s control and status memory always reads 0 and cannot be changed to 1. The
POR bit (power on reset) is automatically set to 1 as the device performs a power-on reset cycle. As longas this bit is set the device will always respond to the Conditional Search command in order to notify thebus master that the control and threshold data is no longer valid. After powering-up the POR bit needs tobe written to 0 by the bus master. This may be done together with restoring the control and thresholddata. It is possible for the bus master to write the POR bit to a 1. This will make the device participate in
the conditional search but will not generate a reset cycle. Since the POR bit is related to the device andnot channel-specific the value written with the most recent setting of an input range or alarm enableapplies. The power-on default setting for the control/status data is 08h for the first and 8Ch for thesecond byte of each channel.

MEMORY MAP PAGE 1, CONTROL/STATUS DATA Figure 5b
Address
08
09
0A
0B
0C
0D
0E
0F

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

OE-A
POR
OE-B
POR
OE-C
POR
OE-D
POR

OC-A
0
OC-B
0
OC-C
0
OC-D
0

0
AFH-A
0
AFH-B
0
AFH-C
0
AFH-D

0
AFL-A
0
AFL-B
0
AFL-C
0
AFL-D

RC3-A
AEH-A
RC3-B
AEH-B
RC3-C
AEH-C
RC3-D
AEH-D

RC2-A
AEL-A
RC2-B
AEL-B
RC2-C
AEL-C
RC2-D
AEL-D

RC1-A
0
RC1-B
0
RC1-C
0
RC1-D
0

RC0-A
IR-A
RC0-B
IR-B
RC0-C
IR-C
RC0-D
IR-D

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DS2450MEMORY MAP PAGE 2, ALARM SETTINGS Figure 5c
Address
10
11
12
13
14
15
16
17

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

MSBL-A
MSBH-A
MSBL-B
MSBH-B
MSBL-C
MSBH-C
MSBL-D
MSBH-D

A
A
B
B
C
C
D
D

A
A
B
B
C
C
D
D

A
A
B
B
C
C
D
D

A
A
B
B
C
C
D
D

A
A
B
B
C
C
D
D

A
A
B
B
C
C
D
D

LSBL-A
LSBH-A
LSBL-B
LSBH-B
LSBL-C
LSBH-C
LSBL-D
LSBH-D

The registers for the alarm threshold voltages of each channel are located in memory page 2 with the low
threshold being at the lower address (Figure 5c). The power-on default thresholds are 00h for low alarmand FFh for high alarm. The alarm settings are always eight bits. For a resolution higher or equal toeight bits the alarm flag will be set if the eight most significant bits of the conversion result yield anumber higher than stored in the high alarm register (AFH) or lower than stored in the low alarm register(AFL). For a resolution lower than eight bits the least significant bits of the alarm registers are ignored.

MEMORY MAP PAGE 3, Factory Calibration, VCC Control Byte Figure 5d
Address
18
19
1A
1B
1C
1D
1E
1F

Factory Calibration (do not change)
Factory Calibration (do not change)
Factory Calibration (do not change)
Factory Calibration (do not change)
Set to 40 hex if VCC powered
Factory Calibration (do not change)
Factory Calibration (do not change)
Factory Calibration (do not change)

There is a fourth memory page in the address range of 18 to 1F used during calibration at the factory.
This memory page is accessible to the user through the Read Memory and Write Memory commands.
Changing the data of this page arbitrarily will de-calibrate the A/D converter or make the device
nonfunctional until it undergoes a power-on reset. If the device is VCC powered the analog circuitry
must be kept permanently active by writing a value of 40 hex to memory address 1C after power-up.
This also eliminates the offset time otherwise needed with each CONVERT command. See thedescription of the CONVERT command for details.

FUNCTION COMMANDSThe Function Command Flow Chart (Figure 6) describes the protocols necessary for accessing the device
registers. Since the memory map of the DS2450 is small compared to the 16-bit addressing capabilities
the 11 most significant bits of the address will be forced to 0 before they enter the CRC-generator. The
communication between master and DS2450 takes place either at regular speed (default, OD = 0) or at
Overdrive Speed (OD = 1). If not explicitly set into Overdrive mode the device assumes regular speed.

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DS2450READ MEMORY [AAH]
The Read Memory command is used to read conversion results, control/status data and alarm settings.
The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) thatindicates a starting byte location within the memory map. With every subsequent read data time slot thebus master receives data from the DS2450 starting at the supplied address and continuing until the end ofan eight-byte page is reached. At that point the bus master will receive a 16-bit CRC of the command
byte, address bytes and data bytes. This CRC is computed by the DS2450 and read back by the bus
master to check if the command word, starting address and data were received correctly. If the CRC readby the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated.
Note that the initial pass through the Read Memory flow chart will generate a 16-bit CRC value that is theresult of clearing the CRC-generator and then shifting in the command byte followed by the two address
bytes, and finally the data bytes beginning at the first addressed memory location and continuing throughto the last byte of the addressed page. Subsequent passes through the Read Memory flow chart will
generate a 16-bit CRC that is the result of clearing the CRC-generator and then shifting in the new databytes starting at the first byte of the next page.

WRITE MEMORY [55H]
The Write Memory command is used to write to memory pages 1 and 2 in order to set the channelspecific control data and alarm thresholds. The command can also be used to write the single control byteon page 3 at address 1Ch. The bus master will follow the command byte with a two byte starting address(TA1=(T7:T0), TA2=(T15:T8)) and a data byte of (D7:D0). A 16-bit CRC of the command byte, address
bytes, and data byte is computed by the DS2450 and read back by the bus master to confirm that thecorrect command word, starting address, and data byte were received. Now the DS2450 copies the databyte to the specified memory location. With the next eight time slots the bus master receives a copy ofthe same byte but read from memory for verification. If the verification fails, a Reset Pulse should be
issued and the current byte address should be written again.
If the bus master does not issue a Reset Pulse and the end of memory was not yet reached, the DS2450
will automatically increment its address counter to address the next memory location. The new two-byte
address will also be loaded into the 16-bit CRC-generator as a starting value. The bus master will send
the next byte using eight write time slots. As the DS2450 receives this byte it also shifts it into the CRCgenerator and the result is a 16-bit CRC of the new data byte and the new address. With the next sixteen
read time slots the bus master will read this 16-bit CRC from the DS2450 to verify that the addressincremented properly and the data byte was received correctly. Following the CRC the master receives
the byte just written as read from the memory. If the CRC or read-back byte is incorrect, a Reset Pulse
should be issued in order to repeat the Write Memory command sequence.
Note that the initial pass through the Write Memory flow chart will generate a 16-bit CRC value that is
the result of shifting the command byte into the CRC-generator, followed by the two address bytes, andfinally the data byte. Subsequent passes through the Write Memory flow chart due to the DS2450
automatically incrementing its address counter will generate a 16-bit CRC that is the result of loading (notshifting) the new (incremented) address into the CRC-generator and then shifting in the new data byte.
The decision to continue after having received a bad CRC or if the verification fails is made entirely by
the bus master. Write access to the conversion read-out registers is not possible. If a write attempt ismade to a page 0 address the device will follow the Write Memory flow chart correctly but theverification of the data byte read back from memory will usually fail. The Write Memory commandsequence can be ended at any point by issuing a Reset Pulse.
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DS2450FUNCTION COMMAND FLOW CHART Figure 6

8 of 24

DS2450FUNCTION COMMAND FLOW CHART Figure 6 (continued)

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DS2450

CONVERT [3CH]
The Convert command is used to initiate the analog to digital conversion for one or more channels at theresolution specified in memory page 1, control/status data. The conversion takes between 60 and 80 μs
per bit plus an offset time of maximum 160 μs every time the convert command is issued. For fourchannels with 12-bit resolution each, as an example, the convert command will not take more than
4x12x80 μs plus 160 μs offset, which totals 4 ms. If the DS2450 gets its power through the VCC pin, thebus master may communicate with other devices on the 1-Wire bus while the DS2450 is busy with A/Dconversions. If the device is powered entirely from the 1-Wire bus, the bus master must instead provide astrong pullup to 5V for the estimated duration of the conversion in order to provide sufficient energy.
The conversion is controlled by the input select mask (Figure 7a) and the read-out control byte (Figure7b). In the input select mask the bus master specifies which channels participate in the conversion. A
channel is selected if the bit associated to the channel is set to 1. If more than one channel is selected, theconversion takes place one channel after another in the sequence A, B, C, D, skipping those channels thatare not selected. The bus master can read the result of a channel’s conversion before the conversion of all
the remaining selected channels is completed. In order to distinguish between the previous result and the
new value the bus master uses the read-out control byte. This byte allows presetting the conversion readout registers for each selected channel to all 1’s or all 0’s. If the expected result is close to 0 then one
should preset to all 1’s or to all 0’s if the conversion result will likely be a high number. In applications
where the bus master can wait until all selected channels are converted before reading, a preset of theread-out registers is not necessary. Note that for a channel not selected in the input select mask, thechannel’s read-out control setting has no effect. If a channel constantly yields conversion results close to
0 the channel’s output transistor may be conducting. See section Device Registers for details.

INPUT SELECT MASK (CONVERSION COMMAND) Figure 7a
bit 7

bit 6
bit 5
“don’t care”

bit 4

bit 3
D

bit 2
C

bit 1
B

bit 0
A

bit 1
Set A

bit 0
Clear A

READ-OUT CONTROL (CONVERSION COMMAND) Figure 7b
bit 7
Set D
Set
0
0
1
1

bit 6
Clear D

bit 5
Set C
Clear
0
1
0
1

bit 4
Clear C

bit 3
Set B

bit 2
Clear B

Explanationno preset, leave as ispreset to all 0’s
preset to all 1’s(illegal code)

Following the Convert command byte the bus master transmits the input select mask and the read-out
control byte. Now the bus master reads the CRC16 of the command byte, select mask and control byte.
The conversion will start no earlier than 10 μs after the most significant bit of the CRC is received by thebus master.
With a parasitic power supply the bus master must activate the strong pullup within this 10 μs window fora duration that is estimated as explained above. After that, the data line returns to an idle high state andcommunication on the bus can resume. The bus master would normally send a reset pulse to exit theConvert command. Read data time slots generated after the strong pullup has ended but before issuing a
reset pulse should result in all 1’s if the conversion time was calculated correctly.
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DS2450

With VCC power supply the bus master may either send a reset pulse to exit the Convert command orcontinuously generate read data time slots. As long as the DS2450 is busy with conversions the bus
master will read 0’s. After the conversion is completed the bus master will receive 1’s instead. Since in a
open-drain environment a single 0 overwrites multiple 1’s the bus master can monitor multiple devices
converting simultaneously and immediately knows when the last one is ready. As in the parasiticallypowered scenario the bus master finally has to exit the Convert command by issuing a rest pulse.

1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances theDS2450 is a slave device. The discussion of this bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling (signal types and timing). A 1-Wire protocol
defines bus transactions in terms of the bus state during specific time slots that are initiated on the fallingedge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of
the Book of DS19xx iButton Standards.

HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able todrive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain or 3-state outputs. The 1-Wire port of the DS2450 is open drain with an internal circuit equivalent
to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At
regular speed the 1-Wire bus has a maximum data rate of 16.3k bits per second. The speed can beboosted to 142k bits per second by activating the Overdrive Mode. The 1-Wire bus requires a pullup
resistor of approximately 5kΩ at regular speed or maximum 2.2kΩ at Overdrive speed forcommunication. During A/D conversions the bus master must provide a strong pullup to 5V to supply
sufficient energy if the DS2450 is powered entirely from the 1-Wire bus.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 16 μs (Overdrive Speed) or more than 120 μs (regular speed), one or more devices on thebus may be reset.

HARDWARE CONFIGURATION Figure 8

SEE TEXT

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DS2450

TRANSACTION SEQUENCE
The protocol for accessing the DS2450 via the 1-Wire port is as follows: Initialization
 ROM Function Command Memory/Convert Function Command Transaction/Data

INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by theslave(s). The presence pulse lets the bus master know that the DS2450 is on the bus and is ready tooperate. For more details, see the “1-Wire Signaling” section.

ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the seven ROM function commands. All
ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in
Figure 9):

Read ROM [33H]
This command allows the bus master to read the DS2450’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used if there is a single DS2450 on the bus. If morethan one slave is present on the bus, a data collision will occur when all slaves try to transmit at the sametime (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number
will result in a mismatch of the CRC.

MATCH ROM [55H]
The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a
specific DS2450 on a multidrop bus. Only the DS2450 that exactly matches the 64-bit ROM sequence
will respond to the following memory/convert function command. All slaves that do not match the 64-bit
ROM sequence will wait for a reset pulse. This command can be used with a single or multiple deviceson the bus.

SKIP ROM [CCH]This command can save time in a single drop bus system by allowing the bus master to access thememory/ convert functions without providing the 64-bit ROM code. If more than one slave is present on
the bus and a read command is issued following the Skip ROM command, data collision will occur on thebus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result).

SEARCH ROM [F0H]
When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a processof elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process
is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write thedesired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM.
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of theBook of DS19xx iButton Standards for a comprehensive discussion of a Search ROM, including an actual
example.
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DS2450

CONDITIONAL SEARCH [ECH]
The Conditional Search ROM command operates similarly to the Search ROM command except that only
devices fulfilling the specified condition will participate in the search. The DS2450 will respond to theConditional Search command if a channel’s alarm enable flags AEH and/or AEL are set and theconversion results in a value outside the range specified by the channel’s alarm threshold voltages. See
section Device Registers for details. The Conditional Search ROM provides an efficient means for thebus master to determine devices on a multidrop system that have to signal an important event, such as a
voltage leaving the tolerance band. After each pass of the Conditional Search that successfully
determined the 64-bit ROM for a specific device on the multidrop bus, that particular device can be
individually accessed as if a Match ROM had been issued since all other devices will have dropped out of
the search process and are waiting for a reset pulse.

OVERDRIVE SKIP ROM [3CH]On a single-drop bus this command can save time by allowing the bus master to access thememory/convert functions without providing the 64-bit ROM code. Unlike the normal Skip ROM
command the Overdrive Skip ROM sets the DS2450 in the Overdrive Mode (OD = 1). All
communication following this command has to occur at Overdrive Speed until a reset pulse of minimum
480 μs duration resets all devices on the bus to regular speed (OD = 0).
When issued on a multidrop bus this command will set all Overdrive-supporting devices into Overdrive
mode. To subsequently address a specific Overdrive-supporting device, a reset pulse at Overdrive speed
has to be issued followed by a Match ROM or Search ROM command sequence. This will speed up thetime for the search process. If more than one slave supporting Overdrive is present on the bus and theOverdrive Skip ROM command is followed by a read command, data collision will occur on the bus asmultiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result).

Overdrive Match ROM [69H]
The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive
Speed, allows the bus master to address a specific DS2450 on a multidrop bus and to simultaneously set itin Overdrive Mode. Only the DS2450 that exactly matches the 64-bit ROM sequence will respond to thesubsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive
Skip or Match command will remain in Overdrive mode. All overdrive-capable slaves will return toregular speed at the next Reset Pulse of minimum 480 μs duration. The Overdrive Match ROM
command can be used with a single or multiple devices on the bus.

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DS2450

ROM FUNCTIONS FLOW CHART Figure 9

14 of 24

DS2450

ROM FUNCTIONS FLOW CHART Figure 9 (continued)

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DS2450

USAGE EXAMPLE (set-up section)
There is a single VCC powered DS2450 on the 1-Wire bus. Set-up channel D for 12 bits, 5.12V range andalarm thresholds of 2.0V (64h) and 3.0V (96h) (increment 20 mV) and convert the input voltage; turn on
the channel A output if low alarm occurs and the channel B output if high alarm occurs, respectively.
MASTER MODE
TX
RX
TX
TX
TX
TX
TX
RX
RX
TX
RX
RX
TX
RX
RX
TX
RX
RX
TX
RX
RX
TX
RX
RX
TX
RX
RX
TX
RX
RX

DATA (LSB FIRST)
Reset
Presence
CCh
55h
08h
00h
C0h
<CRC16>C0h
00h<CRC16>00h
C0h<CRC16>C0h
00h<CRC16>00h
C0h<CRC16>C0h
00h<CRC16>00h
0Ch<CRC16>0Ch
0Dh<CRC16>
0Dh

COMMENTS
Reset Pulse (480 - 960 μs)
Presence Pulse
Issue “Skip ROM” Command
Issue “Write Memory” Command
TA1, beginning address
TA2, address = 0008h
data byte (address 0008)
CRC of command, address, data byte
read-back for simple verificationnext data byte (address 0009h)
CRC of address, data byte
read-back for simple verification
data byte (address 000A)
CRC of address, data byte
read-back for simple verificationnext data byte (address 000Bh)
CRC of address, data byte
read-back for simple verification
data byte (address 000C)
CRC of address, data byte
read-back for simple verificationnext data byte (address 000Dh)
CRC of address, data byte
read-back for simple verification
data byte (address 000E)
CRC of address, data byte
read-back for simple verificationnext data byte (address 000Fh)
CRC of address, data byte
read-back for simple verification

CH-A

CH-B

CH-C*

CH-D

Continued on the next page.
*In a multi-drop environment it takes less time to set-up an unused channel rather than skipping it.

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DS2450

USAGE EXAMPLE (set-up continued, conversion, read flags)
MASTER MODE
TX
RX
TX
TX
TX
TX
TX
RX
RX
TX
RX
RX
TX
RX
TX
TX
TX
TX
RX
RX
TX
RX
TX
TX
TX
TX
RX
RX

DATA (LSB FIRST)
Reset
Presence
CCh
55h
16h
00h
64h
<CRC16>64h
96h<CRC16>96h
ResetPresence
CCh
3Ch
08h
40h
<CRC16><multiple data bytes>
Reset
Presence
CCh
Aah
0Fh
00h
<data byte><CRC16>

COMMENTS
Reset Pulse (480 - 960 μs)
Presence Pulse
Issue “Skip ROM” Command
Issue “Write Memory” Command
TA1, beginning address
TA2, address = 0016h
data byte (address 0016)
CRC of command, address, data byte
read-back for simple verificationnext data byte (address 0017h)
CRC of address, data byte
read-back for simple verification
Reset Pulse (480 - 960 μs)
Presence Pulse
Issue “Skip ROM” Command
Issue “Convert” Command
input select mask
read-out control byte
CRC of command, mask, control byte
continue reading until byte is FFh
Reset Pulse (480 - 960 μs)
Presence Pulse
Issue “Skip ROM” Command
Issue “Read Memory” Command
TA1, beginning address
TA2, address = 000Fh
status data*
CRC of command, address, data byte

CH-D

CH-D

CH-D

Continued on the next page.
*The status data byte includes the channel D alarm flags AFH and AFL which are used to control thechannel A and B outputs (see next page).

17 of 24

DS2450

USAGE EXAMPLE (control channel A and channel B outputs)
MASTER MODE
TX
RX
TX
TX
TX
TX
TX
RX
RX
TX
RX
RX
TX
RX
RX
TX
RX

DATA (LSB FIRST)
Reset
Presence
CCh
55h
08h
00h
80h if AFL = 1 / C0h if
AFL = 0
<CRC16><data byte>
00h<CRC16>00h
80h if AFH = 1 / C0h if
AFH = 0
<CRC16><data byte>
Reset
Presence

COMMENTS
Reset Pulse (480 - 960 μs)
Presence Pulse
Issue “Skip ROM” Command
Issue “Write Memory” Command
TA1, beginning address
TA2, address = 0008h
data byte (address 0008)

CH-A

CRC of command, address, data byte
read-back for simple verificationnext data byte (address 0009h)*
CRC of address, data byte
read-back for simple verification
data byte (address 000A)

CH-B

CRC of address, data byte
read-back for simple verification
Reset Pulse (480 - 960 μs)
Presence Pulse*In a multi-drop environment it takes less time to perform a non-changing write cycle rather thanskipping a byte.

1-WIRE SIGNALINGThe DS2450 requires strict protocols to ensure data integrity. The protocol consists of four types ofsignaling on one line: reset sequence with reset pulse and presence pulse, Write 0, Write 1 and Read Data.
All these signals except presence pulse are initiated by the bus master. The DS2450 can communicate at
two different speeds, regular speed and Overdrive Speed. If not explicitly set into the Overdrive mode,
the DS2450 will communicate at regular speed. While in Overdrive mode the fast timing applies to allwave forms.
The initialization sequence required to begin any communication with the DS2450 is shown in Figure 10.
A Reset Pulse followed by a Presence Pulse indicates the DS2450 is ready to send or receive data given
the correct ROM command and memory function command. The bus master transmits (TX) a reset pulse(tRSTL, minimum 480 μs at regular speed, 48 μs at Overdrive Speed). The bus master then releases theline and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor.
After detecting the rising edge on the data pin, the DS2450 waits (tPDH,15-60 μs at regular speed, 2-6 μs
at Overdrive speed) and then transmits the Presence Pulse (tPDL, 60-240 μs at regular speed, 8-24 μs at
Overdrive Speed).
A Reset Pulse of 480 μs or longer will exit the Overdrive Mode returning the device to regular speed. If
the DS2450 is in Overdrive Mode and the Reset Pulse is no longer than 80 μs the device will remain in
Overdrive Mode.

18 of 24

DS2450INITIALIZATION PROCEDURE “RESET AND PRESENCE PLUSES” Figure 10*IN ORDER NOT TO MASK INTERRUPT SIGNALING BY OTHER DEVICES ON THE 1-WIRE BUS, tRSTL + tR
SHOULD ALWAYS BE LESS THAN 960 μs**INCLUDES RECOVERY TIME

READ/WRITE TIME SLOTSThe definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by themaster driving the data line low. The falling edge of the data line synchronizes the DS2450 to the masterby triggering a delay circuit in the DS2450. During write time slots, the delay circuit determines when
the DS2450 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay
circuit determines how long the DS2450 will hold the data line low overriding the 1 generated by themaster. If the data bit is a “1”, the device will leave the read data time slot unchanged.

READ/WRITE TIME DIAGRAM Figure 11
Write-one Time Slot

19 of 24

READ/WRITE TIMING DIAGRAM Figure 11 (continued)
Write-zero Time Slot

Read-data Time Slot

20 of 24

DS2450CRC HARDWARE DESCRIPTION AND POLYNOMIAL Figure 12

DS2450CRC-GENERATIONWith the DS2450 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is a 8bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC
value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2450 todetermine if the ROM data has been received error-free by the bus master. The equivalent polynomial
function of this CRC is X8 + X5 + X4 + 1. This 8-bit CRC is received in the true (non inverted) form
when reading the ROM of the DS2450. It is computed once at the factory and lasered into the ROM.
The other CRC is a 16-bit type, generated according to the standardized CRC16 polynomial function X16+ X15 + X2 + 1. This CRC is used to safeguard data when reading from or writing to the device’s
memory. It is the same type of CRC as is used with NV RAM based iButtons to safeguard data packetsof the iButton File Structure. In contrast to the 8-bit CRC, the 16-bit CRC is always returned in thecomplemented (inverted) form. A CRC-generator inside the DS2450 chip (Figure 12) will calculate a
new 16-bit CRC at every situation shown in the command flow chart of Figure 6.
The DS2450 provides this CRC value to the bus master to validate the transfer of command, address, anddata to and from the bus master. When reading the memory, the 16-bit CRC is transmitted when the endof each 8-byte memory page is reached. At the initial pass through the Read Memory flow chart the 16bit CRC will be generated by clearing the CRC-generator, shifting in the command byte, low address,
high address and the data bytes beginning at the first addressed memory location and continuing until thelast byte of the addressed memory page is reached. Subsequent passes through the Read Memory flow
chart will generate a 16-bit CRC that is the result of clearing the CRC-generator and then shifting in the
new data bytes starting at the first byte of the next page and continuing until the last byte of the page isreached.
When writing to the DS2450, the bus master receives a 16-bit CRC to verify the correctness of the datatransfer before the device copies the data byte to its memory. With the initial pass through the Write
Memory flow chart the 16-bit CRC will be generated by clearing the CRC-generator, shifting in thecommand, address low, address high and the data byte. Subsequent passes through the Write Memoryflow chart due to the DS2450 automatically incrementing its address counter will generate an 16-bit CRC
that is the result of loading (not shifting) the new (incremented) address into the CRC-generator and thenshifting in the new data byte.
For more details on generating CRC values including example implementations in both hardware andsoftware, see the Book of DS19xx iButton Standards.
21 of 24

DS2450

TRANSFER CHARACTERISTIC

INCREMENT AND MINIMUM FULL SCALE INPUT VOLTAGE VERSUSRESOLUTION
Resolution

2 bits3 bits4 bits5 bits6 bits7 bits8 bits9 bits
10 bits
11 bits
12 bits
13 bits
14 bits
15 bits
16 bits

Range = 2.56V
1 LS bit equivalent
minimum full scale
input voltage(mV)
input voltage (V)

640
320
160
80
40
20
10
5
2.5
1.25
0.625
0.313
0.156
0.078
0.039

1.60
2.08
2.32
2.44
2.50
2.53
2.545
2.55252.55632.55812.55912.55952.55982.55992.5599Range = 5.12V
1 LS bit equivalent
minimum full scale
input voltage (mV)
input voltage (V)

1280
640
320
160
80
40
20
10
5
2.5
1.25
0.625
0.313
0.156
0.078

3.20
4.16
4.64
4.88
5.00
5.06
5.09
5.105
5.11255.11635.1181
5.1191
5.11955.11985.1199In the shaded areas the accuracy is less than the resolution. The conversion results may include random
noise.

22 of 24

DS2450

ABSOLUTE MAXIMUM RATINGS*
Voltage on DATA to Ground
Operating Temperature
Storage Temperature
Soldering Temperature-0.5V to +7.0V-40°C to +85°C-55°C to +125°C
See J-STD-020 Specification* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.

DC ELECTRICAL CHARACTERISTICSPARAMETER
Supply Voltage
Logic 1
Logic 0
Output Logic Low @ 4 mA
Output Logic High
Input Load Current
Operating Current
Quiescent Current

SYMBOL
VCC
VIH
VIL
VOL
VOH
IL
ICC
ICCQ

(-40°C to +85°C)

MIN
4.5
2.2
-0.3

TYP
5.0

VPUP
5
0.5

MAX
5.5
+0.8
0.4
6.0

20

SYMBOL
CIN/OUT
CAIN

MIN

TYP
100

MAX
800
50

UNITS
pF
pF

NOTES
5

(tA= 25°C)

RESISTANCESPARAMETER
Analog Input

NOTES
10
1
1
1
1, 2
3
7
8

(tA= 25°C)

CAPACITANCE
PARAMETER
I/O (1-Wire)
Analog Input

UNITS
V
V
V
V
V
μA
mA
μA

SYMBOL
ZAIN

MIN
0.5

TYP

MAX
1.5

UNITS
MΩ

NOTES

AC ELECTRICAL CHARACTERISTICS REGULAR SPEED(-40°C to +85°C)

PARAMETERTime Slot
Write 1 Low Time
Write 0 Low Time
Read Low Time
Read Data Valid
Release Time
Read Data Setup
Recovery Time
Reset Time HighReset Time Low
Presence Detect High
Presence Detect Low

UNITS
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs

SYMBOL
tSLOT
tLOW
tLOW0
tLOWR
tRDV
tRELEASE
tSU
tREC
tRSTH
tRSTL
tPDH
tPDL

MIN
60
1
60
1
0
1
480
480
15
60

23 of 24

TYP

exactly 15
15

MAX
120
15
120
15
45
1

60
240

NOTES

4

6

DS2450

AC ELECTRICAL CHARACTERISTICS
OVERDRIVE SPEED
PARAMETERTime Slot
Write 1 Low Time
Write 0 Low Time
Read Low Time
Read Data Valid
Release Time
Read Data Setup
Recovery Time
Reset Time HighReset Time Low
Presence Detect High
Presence Detect Low

SYMBOL
tSLOT
tLOW1
tLOW0
tLOWR
tRDV
tRELEASE
tSU
tREC
tRSTH
tRSTL
tPDH
tPDL

(-40°C to +85°C)

MIN
6
1
6
1
0

TYP

Exactly 2
1.5

1
48
48
2
8

MAX
16
2
16
2
4
1

80
6
24

AC ELECTRICAL CHARACTERISTICS
MIN

UNITS
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs

NOTES

4

(-40°C to +85°C)

PARAMETER
Sample & Hold Aperture

SYMBOLtSH

TYP
20

Equivalent Input NoiseVINOISEt.b.d.

Total Conversion Error

NERR

± 1/2

MAX

UNITS
μs
μV
RMS
LSB

NOTES

9

NOTES:
1.
2.
3.
4.

All voltages are referenced to ground.
VPUP = external pullup voltage.
Input load is to ground.
Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data isguaranteed to be valid within 1 μs of this falling edge.
5. Capacitance on the data pin could be 800 pF when power is first applied. If a 5 kΩ resistor is used topull up the data line to VPUP, 5 μs after power has been applied the parasite capacitance will not affectnormal communications.
6. The reset low time (tRSTL) should be restricted to a maximum of 960 μs, to allow interrupt signaling,otherwise, it could mask or conceal interrupt pulses.
7. Measured with VCC = 5.0V supply and 1-Wire input open.
8. Measured with VCC = 5.0V supply, 1-Wire input open and analog circuitry inactive.
9. At 8-bit resolution regardless of range and temperature; includes offset, non-linearity and noise. Outof range is denoted by an all zeros reading. Input voltage at or near minimum and maximum input
range may include additional non-linearity error.
10. VCC or 1-Wire pullup voltage must ramp to 4.5V or higher at least 1µs before voltage can be applied
to analog inputs. This can be achieved through low-pass filtering of the analog input voltage.

REVISION HISTORY
Pages changed at Rev 071906: 1, 2, 6, 7, 23, 24
Pages changed at Rev 112706: 1, 7, 23, 24

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