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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 66, NO. 3, MARCH 2019

A 0.90–4.39-V Detection Voltage Range, 56-Level
Programmable Voltage Detector Using Fine
Voltage-Step Subtraction for Battery Management
Teruki Someya , Member, IEEE, Kenichi Matsunaga, Hiroki Morimura, Member, IEEE,
Takayasu Sakurai, Fellow, IEEE, and Makoto Takamiya, Senior Member, IEEE

Abstract— A programmable voltage detector (PVD) for battery
management is proposed to achieve the programmability of thedetection voltage (VDETECT ). Thanks to the programmability,
users can set an appropriate VDETECT for battery management
considering the operating voltage of the battery. For batteries
including Li-ion and NiMH batteries, a PVD is required toachieve wide programmed VDETECT range from 1.0 to 4.35 V
with a fine voltage step of ±42 mV. Furthermore, the power
consumption of the PVD must be minimized since the PVD
is always operating in battery management. To achieve boththe target programmability of VDETECT and the low power
consumption of the PVD, a programmable voltage reference(PVREF) using a fine voltage-step subtraction (FVS) method
is proposed. The FVS is a combination of fine and coarse
programming for the output of the PVREF, which achieves afine voltage step and a wide programmable range of VDETECT
achieving both a low temperature coefficient of VDETECT andlow power consumption of the PVD. The measurement results of
the PVD fabricated in a 250-nm CMOS process show a current
consumption of the PVD of 1.2 nA at 3.5 V and a temperature
coefficient of VDETECT of 0.28 mV/°C. The PVD enables thewidest programmable range of VDETECT from 0.90 to 4.39 V, fine
VDETECT resolution of ±31.5 mV, and 56-level linear, monotonic
programmability of VDETECT .
Index Terms— Voltage detector, programmable voltage detector, voltage reference, programmable voltage reference, lowpower.

I. I NTRODUCTIONTHE Internet of Things (IoT) is expected to enhance thequality of our lives by using information gathered from
IoT sensor nodes. In an IoT sensor node, a voltage detector (VD) is one of the key circuits for battery management.
As shown in Fig. 1, the VD is connected to a battery to monitor
its terminal voltage (VBAT ) and prevent the battery from being

Manuscript received July 18, 2018; revised October 7, 2018; accepted
October 31, 2018. Date of publication November 28, 2018; date of current
version February 5, 2019. This paper was recommended by Associate Editor
K.-H. Chen. (Corresponding author: Teruki Someya.)
T. Someya was with The University of Tokyo, Tokyo 153-8505, Japan. He is
now with the Tokyo Institute of Technology, Tokyo 152-8550, Japan (e-mail:someya@ssc.pe.titech.ac.jp).
K. Matsunaga and H. Morimura are with the NTT Device Innovation Center,
NTT Corporation, Atsugi 243-0198, Japan.
T. Sakurai and M. Takamiya are with The University of Tokyo,
Tokyo 153-8505, Japan.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2018.2880776

Fig. 1.

Voltage detector for battery management.

damaged by overcharge or overdischarge. Since the VD isalways on, the low-power operation of the VD is indispensable
to an energy-limited IoT node. A challenge of the VDs forbattery management is to improve the accuracy of the detection
voltage (VDETECT) since the lifetime of the battery is sensitive
to its charging voltage. For example, the battery managementof lithium-ion batteries (LiBs) requires the precise control of
VDETECT with inaccuracy of less than ±1 % of the charge
voltage (= ±42 mV) to maximize their performance [1].
Another challenge for the VDs is to achieve the programmability of VDETECT . Since the operating voltages vary among
batteries (e.g., 3.0 to 4.35 V [2], [3], 1.0 to 1.5 V [4], 1.8 to
2.7 V [5], and 2.0 to 3.3 V [6]), an appropriate VDETECT
must be set for the operating voltage of the battery. Recently,
many low-power VDs have been proposed [7]–[10] and madecommercially available [11]–[13]. However, their VDETECT for
the VDs are fixed at certain voltages. As a result, VDs require
special factory trimming to tune VDETECT to meet the user
requirements, increasing the cost and delivery time. Although
VDETECT of VDs in a battery management IC [14] can be
programmed using external resistors, the method increases thecost and area because several bulky resistors are required forthe programming. Furthermore, resistor-based programming is
not suitable for the sub-10 nA operation of VDs because theresistance exceeds 100 M. In [15], a 248 pW programmable
VD that can program VDETECT to mitigate the effect of process
variation is presented although the range of the programmed
VDETECT is only from 0.52 to 0.85 V, making it unsuitable forthe use in battery management.
In this work, an ultra-low-power programmable VD (PVD)
is newly presented that allows users to program VDETECT

1549-8328 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

SOMEYA et al.: 0.90–4.39-V DETECTION VOLTAGE RANGE, 56-LEVEL PVD

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Fig. 2.
(a) Circuit schematic of a typical VD and (b) its input-output
characteristics.

freely in accordance with a battery in an IoT node. Although
the PVD in [16] does not cover the target VDETECT rangeof 1.0 to 4.35 V which is determined based on the operating
voltages of the batteries [2]–[6], the PVD in this work shows a
programming range of 0.90V to 4.39 achieving the resolutionof the programmed VDETECT of ±31.5 mV that is less than
±1 % of the typical charge voltage of a LiB (= ±42 mV).
The PVD in this work is more suitable for various types ofbattery management than [16].
This paper is organized as follows. In Section II, conventional PVDs are described with emphasis on the problems
with their programmability. In Section III, an overview of the
proposed PVD is introduced. Section IV shows measurement
results of the proposed PVD fabricated in a 250-nm CMOS
process. Section V concludes this paper.
II. C ONVENTIONAL P ROGRAMMABLE
VOLTAGE D ETECTOR
Fig. 2 (a) and (b) show a circuit schematic of a typical
VD and the input-output characteristics, respectively. The VD
comprises a voltage reference that generates a constant standard voltage (VREF ), a voltage divider composed of resistors,
and a comparator. In the schematic, some additional circuits
such as a feedback circuit to add some hysteresis to VDETECT,and a delay cell to ensure that the VD is stabilized before
the load system starts their operation, are removed to simplify
the discussion. When VIN (= VBAT in Fig. 1) is lower than apredefined voltage (VDETECT), the output voltage of the VD(VOUT1) is 0 V. When VIN exceeds VDETECT , VOUT1 changes
into the voltage level of VIN . In the circuit topology, VDETECT
is described as
VDETECT = kVREF ,(1)

where 1/k (<1) is the division ratio of the voltage divider.
One simple way to attain the programmability of VDETECT
is to incorporate the programmability of VREF as shownin Fig. 3 (a). A resistive ladder and a selector are added toenable the programmable VDETECT . The method achieves linear VDETECT programmability and fine programmed VDETECT
steps by increasing m. However, the TC of VDETECT deteriorates as m increases owing to the temperature dependenceof VREF1 originating from the voltage drop at the input ofthe MUX (V1 , V2 , …Vm ). The voltage drop is caused by theleakage currents of the transistor switches [17] in the MUXFig. 3. Concept of the programming of VDETECT . (a) Typical implementationto achieve the programmability of VDETECT . (b) Implementation proposedin [15].

(I1 ,I2 , …Im ). Since the leakage current is a strong functionof the temperature, the voltage drop becomes temperaturedependent that increases the TC of VDETECT . The TC of
VDETECT is determined by the ratio of I1 to the amount ofleakage currents in the MUX ISUM (= I1 + I2 + … + Im ’).
Fig. 4 shows the simulated m dependence of the TC of
VDETECT in the PVD shown in Fig. 3 (a) when VREF = 0.5 V
and I1 = 200 pA. Due to the increase in the leakage currentof the MUX, the TC of VDETECT exceeds 0.6 mV/°C whenm = 32, which results in a ±18 mV error of VDETECT in the
typical battery operating temperature range of 0 to 60 °C. This
result indicates a tradeoff relation between the resolution of
the programmed VDETECT and the TC of VDETECT . One way
to solve the tradeoff is to increase I1 so that ISUM become
negligible, although it increases the power consumption of
the PVD. The concept of the PVD proposed in [15] isshown in Fig. 3 (b). By adding the programmability into both
VREF1 and VIN1 , the resolution of the programmed VDETECT is
improved. On the other hand, the conventional PVD [15] does
not achieve linear VDETECT programmability. Fig. 5 shows theoperation principle of the conventional PVD [15]. The offset
of VREF1 is varied by changing m and the gradient of VIN1
is varied by changing n. Points at the intersection of VREF1and VIN1 voltages are the obtained programmed voltages of
VDETECT. As shown in Fig. 5, VDETECT changes nonlinearlyand non-monotonically with the number of control bits. Furthermore, some points overlap, which reduces the number ofthe programmed voltages and resolution of VDETECT . As thesame way to the PVD shown in Fig. 3 (a), the resolution canbe improved by increasing m and n at the cost of the TC of
VDETECT or the power consumption of the PVD. As describedso far, the programming methods shown in Fig. 3 (a) and (b)have the tradeoff relationship between the resolution and TC
of programmed VDETECT. The only way to solve the problem
is to increase the power consumption of the PVD. In the next

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Fig. 4.
Simulated m dependence of the TC of VDETECT in the PVD
in Fig. 3 (a).

Fig. 5.

Operation principle of the conventional PVD [15].

section, the way to solve the tradeoff without increasing thepower consumption of the PVD is proposed.
III. P ROPOSED P ROGRAMMABLE VOLTAGE D ETECTOR
Fig. 6 shows a block diagram of the proposed PVD. The
proposed PVD solves the tradeoff described in Section II
by utilizing the proposed programmable voltage reference(PVREF) that supplies a programmed reference voltage VREF2 .
By applying proper digital codes into SCOARSE and SFINE ,users can program VREF2 , which leads the programmability of
VDETECT. The PVREF achieves both low-power operation (=0.63 nA) and a low TC of VREF2 (= 21 μV/°C) while enabling
the fine voltage-step programmability of VREF2 thanks to the
proposed fine-voltage-step subtraction (FVS) method. As avoltage reference, a VDD -regulated voltage reference (VRVR)
is also newly proposed in Fig. 6. The VRVR improves the linearity of the programmed VDETECT in the PVD by reducing the
supply voltage (= VIN ) sensitivity of VREF . The voltage divider
composed of R1 and R2 is implemented with stacked diodeconnected pMOSFETs. The current of the voltage divider
is reduced to sub-100 pA, which is negligible comparedwith the total current of the PVD. The proposed PVREF isinserted between the VRVR and the comparator. The PVD
shown in Fig. 6 includes a glitch-free, short-circuit-currentfree output stage. The proposed output stage removes a glitch
in VOUTB [15] even though VIN is as low as 0 V. The glitchfree operation is indispensable for the PVD applied to a system
where VIN drops to near 0 V such as battery management for

Fig. 6.

Block diagram of the proposed PVD.

Fig. 7. Concept of the programmability of the PVD. (a) PVD in [16].
(b) PVD in this work.

energy harvesting [18]–[22]. In addition, short-circuit-current
is also reduced in the output stage. During a transition of
VOUT1, there is a period when both pull-up pMOSFET andpull-down nMOSFET conduct a current in the NAND gate
in Fig. 6. The energy loss caused by large short-circuit-current
is critical for the battery management since the transition of
VIN is relatively slow that the short-circuit-current flows from
VIN to GND for a long time. The proposed output stage
reduces the short-circuit-current in the output stage to savethe energy in the battery.
Figs. 7 (a) and (b) show the concept of the programmabilityof the PVDs in [16] and in this work. In [16], m-level VREF2
and n-level VIN1 achieves mn-level programmable VDETECT
while mn-level VREF2 and 1-level VIN1 achieves mn-level
programmable VDETECT in Fig. 6. Both topologies achievemn-level VDETECT with almost identical characteristics. On theother hand, the programming concept in Fig. 7 (b) is selectedin this work because we expect the PVREF used in this work
can be applied to various circuits as well as the PVD. Therefore, the analysis and the measured results of the proposed
PVREF are also described in detail in this work.
A. Programmable Voltage Reference Using Fine Voltage-Step
Subtraction Method
Users can program VDETECT in the PVD shown in Fig. 6 byprogramming the output of the PVREF (VREF2 ) with suitable
digital codes for SCOARSE and SFINE . The proposed PVD using

SOMEYA et al.: 0.90–4.39-V DETECTION VOLTAGE RANGE, 56-LEVEL PVD

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Fig. 9. (a) Operation principle and (b) schematic of the proposed voltage
subtractor.

Substituting (2) into (4),j
VREF
(m + 4)n

(5)



1
j
VREF2 =
i +2−
VREF
m+4
n

(6)

VREF2 = VREF1 −Substituting (3) into (5)Fig. 8. Circuit schematic of the proposed PVREF with the fine voltage-step
subtraction (FVS) method.

the PVREF achieves both fine-resolution programming and a
low TC of VDETECT at the same time while covering the target
VDETECT range of 1.0 to 4.35 V with the current consumptionof 1.2 nA. As shown in Section II, a large number of transistor
switches for a MUX increases the TC of the output voltage of
the PVREF and VDETECT . The proposed FVS method in the
PVREF reduces the number of the transistor switches for a
MUX while maintaining the fine resolution of the programmed
VREF2 . The reduction of the number of the switches for each
MUX leads to a lower TC of VDETECT without increasing thepower consumption.
Fig. 8 shows the circuit schematic of the proposed PVREF
using the FVS method. The circuit implementation of theresistors for the voltage dividers, the MUXs, and the comparator is similar to that in [15]. The multiple voltage duplicator(MVD) works as a multiple-input and multiple-output voltage
buffer that copies each input voltage to each output node as
V1 = V1 ’, V2 = V2 , . . . , Vm = Vm ’ reducing the current consumption of the voltage reference preceding the PVREF [15].
The FVS method used in the PVREF is a combination ofcoarse and fine programming of VREF2 that results in a finestep, monotonically programmed VREF2 . In Fig. 8, VREF is
the coarse voltage-step and VREF /n is the fine voltage-stepfor the programming. In the FVS, the fine VREF2 steps areachieved by subtracting the fine voltage-steps of VREF /nfrom the coarsely varied VREF1 . Linear and monotonic VREF2
programmability is achieved because the fine voltage-step isgenerated from the coarse voltage step. An equation for VREF2
is derived below.
VREF
m+4
i +2
VREF (i = 1, . . . , m)
VREF1 =m+4
j
VREF2 = VREF1 − VREF ( j = 0, 1, . . . , n − 1)n

VREF =

(2)
(3)
(4)

As shown in (6), by subtracting the fine voltage-step of
VREF /(m + 4)n from the coarse voltage step of VREF /(m + 4),
both linear VREF2 programmability and fine VREF2 steps areachieved. The programmability of VREF2 enables the PVD
shown in Fig. 6 to have linear and monotonic programmabilityof VDETECT as follows:
1j
VDETECT = k
(7)
i +2−
VREF .
m+4n
In our design, k, m, and n are determined to be 12, 8, and 8,
respectively, to achieve 6-bit programmability of VDETECT.
The conventional PVD shown in Fig. 3 (a) requires 26 transistors for the MUX to achieve the 6-bit programmability of
VDETECT while the proposed PVD requires 23 transistors foreach MUX. The reduction of the transistor switches for the
MUX improves the TC of VDETECT without increasing thepower consumption.
In the FVS, the low-power voltage subtractors are the keybuilding blocks. Fig. 9 (a) shows the operation principle ofthe proposed voltage subtractor. M1 and M2 are the identicaltransistors operating in the subthreshold region and I3 = 0
because the input impedance of the MUX is sufficiently large.
When the drain-to-source voltages of M1 and M2 are over 3VT ,the gate-to-source voltages of M1 and M2 becomes Vj since
I1 = I2 . Then, VSUB = VREF1 –Vj and the voltage subtraction isachieved. A problem with the subtractor shown in Fig. 9 (a) is,
however, that the result of the subtraction is dependent on VIN .
Since the drain node of M1 is directly connected to VIN ,M1 suffers from the drain-induced barrier lowering (DIBL)
effect. Therefore, the threshold voltage of M1 changes with
VIN , which results in the VIN -dependence of the subtraction
results. Fig. 9 (b) shows a circuit schematic of the proposed
voltage subtractor. The concept of the voltage subtraction isbased on Fig. 9 (a). Compared with the subtractor shownin Fig. 9 (a), M3 is added to the drain node of M2 (V2 ) to keep
V2 constant regardless of VIN . M3 works as a voltage regulator

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 66, NO. 3, MARCH 2019

Output of the voltage subtractors when VREF1 = 0.2 V, Vj = 0 V.

and regulates V2 to V1 –Vj . 2VREF for V1 is obtained from the
proposed VRVR shown later in Fig. 14 (b). The regulation
technique makes V2 less sensitive to VIN and removes the VIN
dependence of the subtraction result. Furthermore, a power
gating switch is added to turn off the non-selected voltage
subtractors. Fig. 10 shows the output characteristics of thevoltage subtractors shown in Figs. 9 fabricated in a 250-nm
CMOS process when VREF1 = 0.2 V and Vj = 0 V. To verify
the efficacy of M3 shown in Fig. 9 (b) in reducing the line
sensitivity (LS) of the subtraction result, the subtractor without
M3 shown in Fig. 9 (a) is also implemented and measured aswell as the subtractor shown in Fig. 9 (b) under the same
conditions. The measured LS of the subtractors shown in
Fig. 9 (a) and (b) are 1.7 mV/V and 0.006 mV/V, respectively.
Thanks to M3 , the LS of the subtractor becomes sufficiently
small not to affect the linearity of the proposed PVREF. The
proposed voltage subtractor is designed to have a currentof 0.2 nA at 20 °C.
The proposed PVREF shown in Fig. 8 is fabricated in a
250-nm CMOS process and verified by measurements with
VREF of 500 mV supplied by a voltage source, externally. The
ideal VREF makes it possible to evaluate the pure performanceof the PVREF regardless of the characteristics of VREF . The
proposed PVREF achieves 631 pA operation at 3.5 V supply
voltage as described later in Fig. 21. Fig. 11 shows the programmed VREF2 when VIN and the temperature are 3.5 V and
20 °C, respectively. The acquired 6-bit VREF2 is ranging from83 to 409 mV, in steps of 5.17 mV. The measured programmed
VREF2 is in good agreement with theoretical programmed
VREF2 ranging from 83 to 411 mV in steps of 5.21 mV,within a VDETECT offset of 2 mV and a step error of 0.04 mV.
The measured current consumption is 631 pA at 3.5 V, andthe TC of the programmed VREF2 is 21 μ V/°C as shownin Fig. 12. The measurement results show that the PVREF
achieves both 631 pA low-power operation and a low TC of
the programmed VREF2 , enabling the 6-bit programmability of
VREF2 which contributes to the linear and monotonic programmability of VDETECT with the fine voltage steps in the proposed
PVD.

Fig. 11.

Measured VREF2 dependence on the digital code of the PVD.

Fig. 12.

Measured TC of the programmed VREF2 .

Fig. 13. Operation principle of the proposed PVD when VREF includes VDD
dependence.

B. V D D -Regulated Voltage Reference (VRVR)
The LS of VREF in the PVD shown in Fig. 6 affects thelinearity of the programmed VDETECT. Fig. 13 shows theoperation principle of the proposed PVD when the PVREF
with m = n = 2 in Fig. 8 is applied. The points whereSOMEYA et al.: 0.90–4.39-V DETECTION VOLTAGE RANGE, 56-LEVEL PVD

Fig. 14. (a) Conventional voltage reference based on [23]. (b) Proposed
VDD -regulated voltage reference (VRVR).

VIN1 and VREF2 intersect are the obtained programmed valueof VDETECT. Fig. 13 shows that the LS of VREF causes anincrease in the step size of the programmed VDETECT (VSTEP ).
The step variation causes the nonlinearity of the programmed
VDETECT. Assuming that VREF is expressed as VREF,R +α(VIN –
VIN,R ), where VREF,R is VREF at a reference VIN (= VIN,R ),α is the LS of the voltage reference (= VREF /VIN ), and
VIN,R = VDETECT,MIN in Fig. 13, VSTEP,MIN and VSTEP,MAX
are expressed as
1
VREF,R(8)
VSTEP,MIN ≈ k(m + 4)n
1
VSTEP,MAX ≈ k(9)
VREF,R + αVIN(m + 4)nwhere VIN = VDETECT,MAX–VDETECT,MIN. From (8) and (9),the largest step difference (VSTEP,MAX ), defined as
VSTEP,MAX –VSTEP,MIN , is expressed as
1αVIN .
(10)
VSTEP ≈ k(m + 4)nAs mentioned previously, m = n = 8 and k = 12 inour design. Assuming that VDETECT,MAX = 4.35 V and
VDETECT,MIN = 1 V considering the target VDETECT , VIN ≈3.4 V. As shown later in Fig. 15, our VRVR supplies VREF
of about 500 mV. Under the condition of VREF,R = 500 mV,
VSTEP,MIN is calculated to 62.5 mV from (8). When VSTEP
is required to be less than 0.1 % of VSTEP,MIN (= 0.06 mV)
to prevent the step error from reducing the linearity of the
programmed VDETECT , α must be less than 140 μV/V. In
this work, a VRVR with the LS of 37 μV/V and the current
consumption of 300 pA is proposed. Figs. 14 (a) and (b)show circuit schematics of a conventional 2-transistor voltage
reference circuit based on [23] and the proposed VRVR,
respectively. In Fig. 14 (a), VREF is determined by the threshold voltages of M1 and M2 asmpμ p C O X P W2 L 1
VTHN) − m p VT ln
VREF = (|VTHP | −mn
μn C O X N W1 L 2(11)where m n (m p ), VTHN (VTHP ), and μn (μp ) are the bodyeffect coefficient, the threshold voltage, and the mobility of1275

Fig. 15.

Measured VIN dependence of VREF .

the nMOSFET (pMOSFET), respectively. VT is the thermal
voltage (= kB T /q), kB is the Boltzmann constant, T is theabsolute temperature, and q is the elementary charge. W1 (W2 )and L 1 (L 2 ) are the gate width and length of each transistor,
respectively, and COXN (COXP ) is the gate capacitance of eachtransistor. The first and second terms in (11) have the opposite
temperature dependences. By taking a suitable ratio of M1
to M2 , the temperature dependences of the first and second
terms cancel each other. Ideally, VREF shown in Fig. 14 (a)is temperature/VIN-independent with the appropriate transistor
size ratio of M1 to M2 . On the other hand, M1 suffersfrom the DIBL effect, that is, VTH1 decreases as VIN (=VIN in Fig. 6) increases, which deteriorates the LS of thevoltage reference shown in Fig. 14 (a). In the proposed
VRVR shown in Fig. 14 (b), a VIN regulator is added to the
2-transistor voltage reference to improve the LS of VREF . The
power overhead of the regulator is 10 % in the total power
consumption of the VRVR. In the VRVR, V1 = V2 ≈ 2VREF ,which shows that V2 is regulated to be a constant voltage.
Assuming that the LS of VREF is α (< 0.01) in Fig. 14 (a),V2 / VIN is 2α in the VRVR, which reduces the LS of
VREF to 2α 2 . Fig. 15 shows the measured VIN dependence ofthe conventional voltage reference shown in Fig. 14 (a) and the
proposed VRVR fabricated in a 250-nm CMOS process. The
proposed VRVR achieves the LS of 37 μV/V (= 0.007 %/V),
whereas the LS of the voltage reference shown in Fig. 14 (a)is 1.5 mV/V (= 0.3 %/V). The VRVR improves the LS ofthe voltage reference dramatically and achieves the target
LS of 140 μV/V. The simulated PSRR of the VRVR is 83 dB at 100 Hz, which shows that the VRVR has a noisetolerant performance against VIN noise. The measured TC
of the VRVR in the temperature range of -20 to 160 °C is
33.6 μV/°C (= 63 ppm/°C) which is sufficiently low TC
compared with the other Sub-1nA CMOS voltage references(e.g., 62 ppm/°C [23], 64 ppm/°C [24] and 252 ppm/°C [25]).
The measured power consumption is sufficiently small valueof 300 pA. The measurement results show that the VRVR
achieves both low-power and VIN -independent operation while
maintaining the temperature-independent characteristics.

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Fig. 18. Measured input and output characteristics of the PVD. VDETECT
is set to 4.2 V.

Fig. 16. (a) Circuit schematic of the output stage in the PVD including
glitch-free VD and NAND gate and (b) their voltage characteristics.

Fig. 19.

Fig. 17.

Die photograph and a layout of the proposed PVD.

C. Glitch-Free and Short-Circuit-Current-Free Output Stage
Fig. 16 (a) and (b) show the circuit schematic of the output
stage in the PVD shown in Fig. 6 and the characteristics ofeach node. The output stage realizes glitch-free and shortcircuit-current-free operation. The glitch is due to the unknown
states of the comparator, the voltage reference, and the output
buffer in the PVD when VIN is near 0 V. Typically, the minimum VIN (e.g., 0.8 to 1 V) is specified in commerciallyavailable VDs [11]–[13] where the VDs operate properly.
Glitch-free operation is indispensable for the PVD when it
is applied to the battery management for energy harvestingsince a glitch in the output of the PVD adversely affects the

Measured VDETECT dependence on the digital code of the PVD.

energy harvesting [15]. In the proposed PVD, the glitch-freeprogrammable operation is achieved by the combination of the
PVD and a glitch-free VD based on the concept shown in [15].
In addition, short-circuit-current-free operation is achieved toreduce the energy loss of the battery. The short-circuit-current
occurs when a typical CMOS NAND gate is applied to the
PVD in Fig. 6. When VIN is close to VDETECT, neither the pullup pMOSFETs nor the pull-down nMOSFETs are turned offcompletely in the NAND gate and a short-circuit current flows
from VIN to GND. Since the transition of the battery voltage
is relatively slow, the short-circuit-current flows for a while,which causes additional energy loss. The proposed NAND
stage with a glitch-free VD shown in Fig. 16 (a) achieves
both the glitch-free and short-circuit-current-free operation.
In Fig. 16 (a), M7 and M8 work as a glitch-free VD.VDETECT2
is expressed asmp
μ p C O X P W8 L 7VTHN −m p VT ln
VDETECT2 = |VT H P |−.
mn
μn C O X N W7 L 8(12)where W7 (W8 ) and L 7 (L 8 ) are the gate width and length ofeach transistor, respectively. VDETECT2 becomes temperatureindependent with the proper size ratio of W8 /L 8 to W7 /L 7 .

SOMEYA et al.: 0.90–4.39-V DETECTION VOLTAGE RANGE, 56-LEVEL PVD

Fig. 20.

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Measured TC of VDETECT for each digital code.

Fig. 22.
Response time of the PVD. (a) Block diagram of the test
environment. (b) Measured waveform of the output node in the PVD.

IV. M EASUREMENT R ESULTS OF P ROPOSEDP ROGRAMMABLE VOLTAGE D ETECTOR

Fig. 21. Measured current of the entire PVD. Currents of the PVREF andthe VRVR are also measured aside from the PVD.

In our design, VDETECT2 ≈ 500 mV. When VIN < VDETECT2,VOUTB is maintained at the voltage level of VIN by the glitchfree voltage detector and the low VTH pMOSFET M3 . When
VIN > VDETECT2, M3 and M2 are turned off and turned on,
respectively, and M1 and M4 comprise a common source
amplifier working as an inverter. M4 is a current source
whose current (I4 ) is similar to I6 . Thanks to the limited
current of M4 , the short-circuit-current in the output stage
is removed. In our design, W4 /L 4 = W5 /L 5 = W6 /L 6 andW6 /L 6 : W1 /L 1 = 400 : 1, which makes I1 400 times lower
than I6 when VOUT1 = 0. I4 maintains VOUTB High when
VDETECT2 < VIN < VDETECT. Assuming that the sub-thresholdswing of the nMOSFET is 80 mV/dec, VOUT1 that invert
VOUTB from Low to High or High to Low is about 200 mV.
Since the output stage always consumes I6 , I6 is set to a
sufficiently low current of 100 pA at room temperature to
make the current consumption of the output stage negligibly
low in the PVD.

In this section, measurement results of the proposed
PVD fabricated in a 250-nm CMOS process are presented.
Fig. 17 shows a chip photograph of the proposed PVD.
The core area is 480 μm by 180 μm. Fig. 18 shows themeasured input and output characteristics of the PVD when
VDETECT is set to 4.2V. The measurement result shows thatthe glitch is successfully removed from VOUTB . Fig. 19 shows
the programmed VDETECT of the PVD. Although the PVD isdesigned to achieve the 6-bit programmability of VDETECT,
56-level valid VDETECT for covering the target VDETECT
range of 1.0 to 4.35 V are extracted. The programmed
VDETECT shown in Fig. 19 ranges from 902 to 4388 mVin steps of 63 mV, which covers the target VDETECT rangeof 1.0 to 4.35V with steps of less than the target resolutionof ±42 mV. Fig. 20 shows the temperature coefficient of
the programmed VDETECT . The average TC of the 56-level
programmed VDETECT is competitive value of 0.28 mV/°C.
To further increase the accuracy of battery charging, we can
improve the resolution of the programmed VDETECT or the TC
of VDETECT by increasing the power consumption of the PVD.
Fig. 21 shows the power consumption of the entire PVD, the
VRVR, and the PVREF at room temperature (20 °C). The
power consumption of the entire PVD is 1.2 nA at 3.5 V
including those of 0.3 nA and 0.63 nA for the VRVR and
the PVREF, respectively. The PVD achieves the ultra-low
power consumption with the reasonable TC of VDETECT thanks
to the proposed PVREF utilizing the FVS method and the1278IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 66, NO. 3, MARCH 2019

TABLE ICOMPARISON WITH PREVIOUS VOLTAGE DETECTORSVRVR. The response time of the PVD is measured as shownin Figs. 22. Fig. 22 (a) shows the block diagram of the test
equipment. In this measurement, the detection voltages forbattery management, that is, VHIGH and VLOW shown in Fig. 1,
are defined as 4.2 V and 3.0 V. A PC and a signal generator areused to define the VDETECT of the PVD as a replacement of an
MCU. A power source is used to reproduce a terminal voltageof the battery. We set the cycle time of the power source to
1 Hz with the VIN slope (dVIN /dt) of 10V/s. The slope is set to
be faster than the charging speed of an RF energy harvesting
system reported in [19] (= 2V/s). For the usage of the energy
harvesting system, the PVD is required to respond sufficiently
faster than those increase/decrease in VIN . Fig. 22 (b) showsthat the measured delays are 7.4 ms and 10.1 ms for the riseand fall edges of VOUT , respectively. These time-lags causes
the inaccuracy of 74mV/-101 mV in the supply voltage forthe load system. If the higher accuracy of the input voltage
for the system is required, the response time of the PVD must
be reduced at the cost of the power consumption.
In Table I, this work is compared with the previously
reported VDs. The proposed PVD enables the field programmability of the VD, allowing users to determine VDETECT
freely, making it suitable for the batteries and applications. The
programmed VDETECT covers the widest range from 902 to
4388 mV, covering the operating voltages of many typesof battery. Compared with [16], the programming range of
VDETECT is improved to be more suitable for the operation
voltages of various batteries. The step of the programmed
VDETECT is 63 mV, which is less than ±1 % of a typicalcharging voltage for a LiB (= ±42 mV). The measured
TC of the programmed VDETECT has a competitive valueof 0.28 mV/°C.
V. C ONCLUSIONSIn this work, a programmable voltage detector (PVD) fabricated in a 250-nm CMOS process that achieves the widest

programmed detection voltage (VDETECT) range of 0.90 to
4.39 V with a step voltage of 63 mV is newly presented.
The programmability of the PVD enables users to program
VDETECT freely to set an appropriate VDETECT for battery
management considering the operating voltage of the battery.
The proposed PVD achieves linear, monotonic voltage-step
programmed VDETECT and a low TC of 0.28 mV/°C at 1.2 nA
current consumption when VIN = 3.5 V thanks to the proposed
programmable voltage reference using the fine voltage-step
subtraction method.
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Teruki Someya (S’16–M’18) received the B.S.,
M.S., and Ph.D. degrees in electrical and electronicengineering from The University of Tokyo in 2013,2015, and 2018, respectively. He is currently a
Researcher with the Tokyo Institute of Technology.
His research interests include energy-efficient ultralow power circuits for Internet of Things applications.

Kenichi Matsunaga received the M.E. degree inelectronics from the Tokyo Institute of Technology
in 2010. He joined NTT Microsystem Integration
Laboratories in 2010 and studied low-power CMOS
circuits design for wireless sensor nodes. Since
2015, he has been with the NTT Device Innovation
Center, where he is currently developing Internetof Things devices. His research interests include
CMOS circuits and sensor network. He is a memberof IEICE and JSAP.

1279

Hiroki Morimura (M’94) received the B.E. degreein physical electronics, the M.E. degree in applied
electronics, and the Dr. Eng. degree in advanced
applied electronics from the Tokyo Institute of Technology, Japan, in 1991, 1993, and 2004, respectively.
In 1993, he joined Nippon Telegraph and Telephone(NTT) Corporation, Tokyo, Japan, where he is currently a Project Manager with the Product Strategy
Planning Project, NTT Device Innovation Center. He
is a member of IEICE and JSAP.

Takayasu Sakurai (S’77–M’78–SM’01–F’03)
received the Ph.D. degree in electrical engineeringfrom The University of Tokyo in 1981. In
1981, he joined Toshiba Corporation, where hedesigned CMOS DRAM, SRAM, RISC processors,
DSPs, and system-on-chip solutions. He focused
extensively on interconnect delay and capacitancemodeling known as Sakurai model and alphapower-law MOS model. From 1988 to 1990, he
was a Visiting Researcher with the University ofCalifornia, Berkeley, where he conducted researchin the field of very large-scale integration (VLSI) CAD. Since 1996, he has
been a Professor with The University of Tokyo, focusing on low-power highspeed VLSI, memory design, interconnects, ubiquitous electronics, organicICs, and large-area electronics. He has published more than 600 technicalpublications including 100 invited presentations and several books and filed
more than 200 patents. He is an IEICE Fellow. He was a recipient of the2010 IEEE Donald O. Pederson Award in Solid-State Circuits, the 2009 and2010 IEEE Paul Rappaport Award, the 2010 IEICE Electronics SocietyAward, the 2009 IEICE Achievement Award, the 2005 IEEE ICICDT Award,
the 2004 IEEE Takuo Sugano Award, and the 2005 P&I Patent of the YearAward, and four product awards. He is the Executive Committee Chair of
the VLSI Symposia and a Steering Committee Chair of the IEEE A-SSCC.
He served as a Conference Chair for the Symposium on VLSI Circuits and
ICICDT, a Vice Chair for ASPDAC, a TPC Chair for the A-SSCC and the
VLSI Symposium, an Executive Committee Member for ISLPED, and a
Program Committee Member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC,
ICCAD, ISLPED, and other international conferences. He delivered keynote
speech at more than 50 conferences, including ISSCC, ESSCIRC, andISLPED. He was an Elected AdCom Member of the IEEE Solid-State
Circuits Society and an IEEE CAS and SSCS Distinguished Lecturer. He is
also a Domain Research Supervisor for nano-electronics area with the Japan
Science and Technology Agency.

Makoto Takamiya (S’98–M’00–SM’14) received
the B.S., M.S., and Ph.D. degrees in electronicengineering from The University of Tokyo, Japan,
in 1995, 1997, and 2000, respectively. In 2000,
he joined NEC Corporation, Japan, where he wasengaged in the circuit design of high-speed digital large-scale integrations. In 2005, he joined
The University of Tokyo. From 2013 to 2014, hestayed at the University of California, Berkeley, as a
Visiting Scholar. He is an Associate Professor with
the Very Large-Scale Integration (VLSI) Design and
Education Center, The University of Tokyo. His research interests include
the integrated power management circuits for wireless powering and energy
harvesting for Internet of Things applications, and the digital gate driver IC
for power electronics. He is a member of the Technical Program Committee of
the IEEE International Solid-State Circuits Conference. He was a recipient of
the 2009 and 2010 IEEE Paul Rappaport awards. He received the Best Paper
Award at the 2013 IEEE Wireless Power Transfer Conference. He served on
the Technical Program Committees of the IEEE Symposium on VLSI Circuits
from 2009 to 2017 and the IEEE Custom Integrated Circuits Conference from2006 to 2011.